1998_TI_Data_Acquisition_Circuits_Data_Book 1998 TI Data Acquisition Circuits Book

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~TEXAS

INSTRUMENTS

Data Acquisition Circuits
Data Conversion and DSP Analog Interface

1998

1998

Mixed-Signal Products

General Information
General Purpose ADCs
General Purpose DACs
DSP AICs and CODECs
Special Functions
Video Interface Palettes
Digital Imaging Sensor Products
Mechanical Information

Data Acquisition Circuits
Data Book
Data Conversion and DSP Analog Interface

SLAD001A
DECEMBER 1997

•

'TEXAS

INSTRUMENTS

Printed on Recycled Paper

IMPORTANT .NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.

Copyright © 1998, Texas Instruments Incorporated

Printed in U.S.A. by
Custom Printing Company
Owensville, Missouri·

INTRODUCTION
Texas Instruments offers an extensive line of industry-standard data acquisition integrated circuits. They are
designed to provide highly reliable circuits for peripheral support applications of microprocessor-based
systems, DSP (digital signal processing) related analog interfaces, video and high-speed converters,
digitizing requirements that demand ADC and DAC conversion, and general-purpose functions.
This data book provides information on the following product groups:
•
•
•
•
•
•
•
•
•
•
•
•
•

Serial 1/0 Analog-to-Digital Converters
General Purpose Parallel Output Analog-to-Digital converters
Stereo Audio Analog-to-Digital Converters
Multiplexed BCD-Output, Dual Slope Analog-to-Digital Converters
Video and High-Speed Analog-to-Digital Converters
Video and High-Speed Digital-to-Analog Converters
General Purpose Serial-Input Digital-to-Analog Converters
General Purpose Parallel-Input Digital-to-Analog Converters
Stereo Audio Digital-to-Analog Converters
Analog Interface Circuits (AICs)
Special Function Circuits (PLL, Clamping, Filter, Amplifier)
Video Interface Palettes
CCD Interface Analog-to-Digital Converters

These products cover applications such as audio, graphics, communications, modems and cellular phones,
video capture and image processing, industrial control and disk-drive servo-loop control, automotive,
electronic instrumentation, digital audio, and any DSP or microprocessor-based system.
Texas Instruments, the world's leading supplier of DSP solutions, is committed to meeting the needs of
industry by accelerating the development of new differentiated analog products, while continuing to provide
world-class quality, and customer support.
An electronic version of this data book, including all Mixed-Signal & Analog products, is available from TI.
The InfoNavigator CD-ROM, which is both a designer's guide and data book may be ordered via the Internet
at: http://www.ti.com/sc/docs/cdrom/ordercd.htm You may also order by calling Texas Instruments toll-free
at: 1:..a00-477-8924 ext. 5047
To provide full technical support, Texas Instruments has a large fUlly-staffed product information center
available to help you. Simply call our U.S. headquarters at (972) 644-5580. Texas Instruments Sales Offices,
listed on the last page of this book, also provide sales and technical support.

v

vi

General Information

1-1

Contents
Page
Alphanumeric Index: : ......................... ,............................ 1-3
Analog-to-Digital Converter Selection Guide: .......................... 1-4
Digital":to-Analog' Converter Selection Guide: .......................... 1-8
Analog Interface Circuit Selection Guide: ...... ; ....................... 1-11
Special Function Selection Guide: ...................................... 1-12
Video Interface Palette Selection Guide: ............................... 1-13
Digital Imaging Sensor Products Selection Guide: .................... 1-14
Cross Reference: ......................................................... 1-15
Glossary: .......................... ,........................................ 1..:..20

-o.....
::::I

...

3
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o

...
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1-2

ALPHANUMERIC INDEX

AD7524M .........................
ICL7135 ..........................
MF4A-50 .........................
MF4A-100 ................... :....
TL5501 ...........................
TL5632 ...........................
TL7726 ...........................
TL32088 ........... .. . . . . . . . . . . . ..
TLC04 ...........................
TLC14 ...........................
TLC540 ..........................
TLC541 ..........................
TLC542 ..........................
TLC545 ..........................
TLC546 ..........................
TLC548 ..........................
TLC549 ..........................
TLC0820A ........................
TLC0831 .........................
TLC0832 .........................
TLC0834 .........................
TLC0838 .........................
TLC876 ..........................
TLC876M .........................
TLC1541 .........................
TLC1542 .........................
TLC1543 .........................
TLC1549 .........................
TLC1550 .........................
TLC1551 .........................
TLC2543 .........................
TLC2932 .........................
TLC2933 .........................
TLC5510 .........................
TLC5540 .........................
TLC5602 .........................
TLC5604 .........................
TLC5614 .........................
TLC5615 .........................
TLC5616 .........................
TLC5617 .........................
TLC5618 .........................
TLC5618M .......................
TLC5620 .........................
TLC5628 .........................
TLC5733 .........................
TLC7135 .........................
TLC7225 .........................

3-3
2-3
5-7
5-7
2-13
3-11
5-3
5-61
5-7
5-7
2-19
2-19
2-29
2-39
2-39
2-51
2-51
2-61
2-71
2-71
2-83
2-83
2-97
2-119
2-123
2-133
2-133
2-153
2-167
2-167
2-175
5-19
5-41
2-197
2-209
3-19
3-27
3-29
3-31
3-47
3-55
3-75
3-95
a:-97
3-107
2-225
2-3
3-117

TLC7226 .........................
TLC7524 .........................
TLC7528 .........................
TLC7628 .........................
TLC8044 .........................
TLC8144 .........................
TLC8188 .........................
TLC32040 ........................
TLC32041 ........................
TLC32044 ........................
TLC32045 ........................
TLC32046 .........................
TLC32047 ........................
TLC320AC01 .....................
TLC320AC02 .....................
TLC320AD50 .....................
TLC320AD52 .....................
TLC320AD55 .....................
TLC320AD56 .....................
TLC320AD57 .....................
TLC320AD58 .................. '...
TLC320AD75 .....................
TLC320AD80 .....................
TLV0831 .... . . . . . . . . . . . . . . . . . . . ..
TLV0832 .........................
TLV0834 .........................
TLV0838 .........................
TLV1543 .........................
TLV1544 .........................
TLV1548 .........................
TLV1548M ........................
TLV1549 .........................
TLV1570 .........................
TLV1572 .........................
TLV2543 .........................
TLV5510 ..........................
TLV5613 .........................
TLV5619 .........................
TLV5620 .........................
TLV562.1 ........ . . . . . . . . . . . . . . . ..
TLV5628 .........................
TMS57014A ......................
TVP3026 .........................
TVP3030 .........................
TVP3033 .........................
TVP3409 .........................
TVP3703 .........................

3-137
3-153
3-163
3-177
7-3
7-33
7-61
4-3
4-3
4-35
4-35
4-73
4-129
4-187
4-273
4-361
4-361
4-417
4-455
2-247
2-267
4-495
4-535
2-291
2-291
2-303
2-303
2-317
2-335
2-335
2-367
2-373
2-387
2-397
2-409
2-429
3-187
3-195
3-203
3-215
3-231
3-243
6-3
6-7
6-11
6-13
6-15

Devices in bold type are in the PRODUCT PREVIEW stage of development.

~TEXAs

INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75265

1-3

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TLC7135

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8
~

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TLC0820A

@

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TLC1550*
TLC1551*

::D

o_~

TLV0831
TLV0832
TLV0834
TLV0838

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01

TL5501*

TLV5510t

TLC5510*
TLC5510d
TLC5540*
TLC5733d

TLC876*
TLV157N

TLC320AD57
TLC320AD58

~

TLC320AD75§

TLVl543
TLV1~
TLV15~

TLV1549

t This part is in the Product Preview stage of development.
:j: This part is TMS320 compatible.
§ For this part see Section 4, Analog Interface Circuits, for more information.

TLC1541
TLCl542
TLC1543
TLC1549
TLV15W
TLV1548*

TLC0831
TLC0832
TLC0834
TLC0838
TLC540
TLC541

TLC542
TLC545
TLC546
TLC548
TLC549

en

Serial 1/0 Analog-to-Digital Converters (ADC)
Device

~

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fri (I)
!!!o;.

! :;jd
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TLC2543
TLV2543
TLC1541
TLC1542
TLC1543
TLC1549
TLV1543
TLV1544
TLV1548
TLV1548M
TLV1549
TLC0831
TLC0832
TLC0834
TLC0838
TLC540
TLC541
TLC542
TLC545
TLC546
TLC548
TLC549

Resolution
(bits)

VCC(V)

Power
(mW)
max

Conversion
T1me{J.ts)

Sampling Rate
(kSPS)
max

Number of
Analog
Inputs

Internal
System
Clock

Standby

12
12
10
10
10
10
10
10
10
10
10
8
8
8
8
8
8
8
8
8
8
8

5
3.3
5
5
5
5
3.3
2.7 -5.5
2.7 - 5.5
2.7 - 5.5
3.3
5
5
5
5
5
5
5
5
5
5
5

12
8
12
12
12
12
8
4
4
4
8
12.5
26
12.5
12.5
12
12
10
12
12
12
12

10
10
21
21
21
21
21
10
10
10
21
13.3
13.3
13.3
13.3
9
17
20
9
17
17
17

66
66
32
38
38
38
38
85
85
85
38
31
22
20
20
75
40
25
76
40
45.5
40

11

X
X

X
X

11
11
11
11

1
11
4
8
8
1
1
2
4
8
11
11
11
19
19
1
1

X
X
X
X
X
X
X
X

X

X
X

X
X
X

Linearity Error
(LSB)

±1.0
±1.0
±1.0
±0.5
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5

Page
No.

2-175
2-409
2-123
2-133
2-133
2-153
2-317
2-335
2-335
2-367
2-373
2-71
2-71
2-83
2-83
2-19
2-19
2-29
2-39
2-39
2-51
2-51

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zm
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Serial 1/0 Analog-to-Digital Converters (ADC) (continued)
Resolution
(bits)

VCC(V)

Power
(mW)
max

Conversion
Time (Ils)

Sampling
Rate
(kSPS)
max

Number of
Analog
Inputs

TLV0831

8

3.3

4.1

13.3

49

TLV0832

8

3.3

15.5

13.3

44.7

Device

Internal
System
Clock

Linearity Error
(LSB)

Page No.

1

±1.0

2-291

2

±1.0

2-291

Standby

TLV0834

8

3.3

4.1

13.3

41

4

±1.0

2-303

TLV0838

8

3.3

4.1

13.3

37.9

8

+1.0

2-303

Device

g...

VCC(V)

Power
(mW)
max

Conversion
Time{j.iS)

Sampling Rate
(kSPS) max

Number of
Analog
Inputs

Linearity Error
(LSB)

5

40

6

164

1

±0.5

TLC1550

10

TLC1551

10

5

40

6

164

1

~~d

TLC0820A

8

5

7.5

2.5

392

1

/;len

!~~
~~

~.~
i'!i

~

Stllndby

Internal
System
Clock

Page No.
2-167

±1.0

X
X

±1.0

X

2-6.1

2-167

Stereo Audio Analog-to-Digital Converters (ADC)
Resolution
(bits)

VCC(V)

TLC320AD57

16/18

TLC320AD58

16/18

Device

'C)
2c:
C)-0

::1m
»
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Resolution
(bits)

o_~
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So

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OZ

o
o

General Purpose Parallel Output Analog-to-Digital Converters (ADC)
."

0C) 0.....

Number of
Analog
Inputs

Power
(mW)max

Sampling Rate
(kSPS) max

5

220

48

2

Serial

5

220

48

2

Serial

Output Type

Page No.
2-247
2-267

-------

<
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~
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Multiplexed BCD-Output, Dual Slope Analog-to-Digital Converters (ADC)
Device
TLC7135

Resolution
(bits)

VCC
(V)

Power
(mW)
max

Conversion
Time (ms)

Sampling Rate
(SPS) max

Number
of Analog
Inputs

Output
Type

Linearity
Error
(LSB)

Page No.

4.5

±5

30

33.3

30

1

BCD

0.5

2-3

Video and High-Speed Analog-to-Digital Converters (ADC)
Resolution
(bits)

Conversion
Time
(ns)

VCC(V)

TL5501

10

50

5

131

TLC876

10

50

5

150

g

TLC876Ml

10

50

5

150

20

TLV1570l

10

2.7 - 5.5

9

o_~
:llz
-.
£(1)
~:ad

TLV1572

10

80.0

2.7 - 5.5

8

1.25

TLC5510

8

50

5

135

20

TLC5510A

8

50

5

150

TLC5733A

8

50

5

TLC5540

8

25

TLV5510l

8

Device

~t:~

':i:ti)

~~
rn

I!i

~C/)
I!i

I

Power
(mW)
max

Number of
Analog
Inputs

Output
Type

Differential
Error (DNL)
(LSB)

20

1

Parallel

±0.5

20

1

Parallel

±0.5

55

1

Parallel

±0.5

55

8

Serial

±0.5

1

Serial

±0.5

1

Parallel

±0.5

46

2-197

20

1

Parallel

±0.5

46

2-197

300

20

1

Parallel

±0.5

-

2-225

5

150

40

1

Parallel

±0.75

45

2-209

3.3

50

20

1

Serial

±0.5

Sampling Rate
(MSPS) max

SNR
(dB)

Page No.
2-13
2-97
2-119
2-387
2-397

2-429

t This part is in the Product Preview stage of development.

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TLC7524*
TLC7528*
TLC7628*

<
m
TLV5613't
TLV5620
TLV5621
TLV5628

t This part is in the Product Preview stage of development.
:I: This part is TMS320 compatible.
§ For this part see Section 4, Analog Interface Circuits, for more information.

AD7524M
TLC5620
TLC5628
TLC7225*
TLC7228*

~

TLV5619t

TLC5614t
TLC5616t
TLC5618*
TLC5619*

m
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TMS57014A

TLC320AD75§

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Video and High-Speed Digital-to-Analog Converters (DAC)
Resolution
(bits)

Device

Vee
(V)

Power
(mW)
max

Bus
Interface

Output
(lor V)

Number
ofDACs

Ref.

Settling
Time
(ns)

linearity
Error
(lSB)

Conversion
Rate (MHz)
min

Page No.

Tl5632

8

5

450

Parallel

V

3

In!

10

±0.5

60

3-11

TLC5602

8

5

125

Parallel

V

1

Ext

30

±0.2

20

3-19

Multiplying

Page No.

General Purpose Serial-Input Digital-to-Analog Converters (DAC)
Device

~

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~(I)

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Resolution
{bits)

Vee (V)

Bus
Interface

Output Number
(I or V) ofDACs

Ref.

Settling
Time(J.IS)

Linearity
Error
(LSB)

Conversion
Rate (kHz)
min

TLC5618

12

5

3.5

Serial

V

2

Ext

2.5

±0.5

121

TLC5618MT

12

5

3.5

Serial

V

2

Ext

2.5

±0.5

121

TLC5614t

12

3105

7.25

Serial

V

4

Ext

-

TLC5615

10

5

1.75

Serial

V

1

Ext

12.5

±0.5

TLC5616t

10

5

3

Serial

V

1

Ext

2.5-12.5

±0.5

-

TLC5617

10

5

3.5

Serial

V

2

Ext

2.5

±0.5

121

TLC5604t

10

3t05

7.25

Serial

Ext

-

-

3-27

8

5

10

Serial

V
V

4

TLC5620

4

Ext

10

±1.0

10

3-97

TLC5628

8

5

20

Serial

V

8

Ext

10

±1.0

10

3-107

TLV5620

8

2.7105.5

6.6

Serial

V

4

Ext

10

±1.0

10

3-203

TLV5621

8

2.7 to 5.5

4.5

Serial

V

4

Ext

10

±1.0

10

3-215

TLV5628

8

2.7105.5

13.2

Serial

V

8

Ext

10

±1.0

10

3-231


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General Purpose Parallel-Input Digital-to-Analog Converters (DAC)
Resolution
(bils)

Device

VCC(V)

Power
(mW)
max

Bus
Interface

Outpul
(lor V)

-m

Number
ofDACs

Ref.

Settling
Time
(IJS)

Linearity
Error
(LSB)

Multiplying

Page No.

TLV5619t

12

3105

7.25

Parallel

V

1

Ext

0.8

±0.5

3-195

TLC7225

8

51015

V

Exl
Ext

5
5

3-117

15

4
4

±1.0

8

Parallel
Parallel

V

TLC7226

60
240

±1.0

3-137

TLC7524

8

5 to 15

5

Parallel

I

1

Ext, M

0.1

±0.5

TLC7528

8

51015

10

Parallel

I

2

Ext,M

0.1

±0.5

TLC7628

8

111015

20

Parallel

I

2

Ext,M

0.1

±0.5

AD7524M

8

51015

5

Parallel

I

1

Exl, M

0.1

±0.5

TLV5613t

8

3105

7.25

Parallel

V

1

Ext

0.8

±0.5

X
X
X
X

3-153

i~~
~rntll

~~

~tIl

j

TMS57014A

Resolution
(bits)
16/18 .

~­
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3-3

~
~
m

3-187

o

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Device

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VCC(V)

Power
(mW)
max

Bus
Interface

Output

Number of
DACs

Conversion
Rate (kHz)
max

Page No.

5

350

Serial

PWM

2

48

3-243

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ANALOG INTERFACE
CIRCUITS

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TLC32041
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TLC320AD75

Analog Interface Circuits (AICs)
Supply
Voltage(s)

Resolution
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Sampling
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Bandwidth
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TlC320AD75

20

44.1

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18

48

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22.05

8.8

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22.05

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Device

(V)

Pd(mW)
typ

SNR(dB)
typ

400

104

Conversion
Method

Description

Page No.

Sigma-delta

Stereo ADA circuit (audio)

4-495

Sigma-delta

Audio processor subsystem

4-535

70

Sigma-delta

Sigma-delta AIC

4-455

175

70

Sigma-delta

Sigma-delta AIC with mstrlslv function

4-361

+5/+3

175

70

Sigma-delta

Sigma-delta AIC with mstrlslv function

4-361

4

+5

150

70

Sigma-delta

Sigma-delta AIC

4-417

25

10.8

+5

100

70

Successive approx.

Single-supply AIC

4-273

14

25

10.8

+5

100

72

Successive approx.

Single-supply AIC

4-187

TlC32047

14

25

0.3 -11.4

±5

375

70

Successive approx.

Wide-band AIC with (sin x)/x correction

4-129

TlC32046

14

25

0.3-7.2

±5

375

85

Successive approx.

AIC with (sin xlIx correction

4-73

TlC32045

14

19.2

0.1 - 3.8

±5

375'

80

Successive approx.

Voice-band AIC (relaxed TLC32044)

4-35

TLC32044

14

19.2

0.1 - 3.8

±5

375

80

Successive approx.

Voice-band AIC

4-35

TLC32041

14

19.2

0.3 - 3.6

±5

375

89

Successive approx.

Ale wlo internal reference

4-3

TLC32040

14

19.2

0.3- 3.6

±5

375

89

Successive approx.

AIC

4-3

+5
+5

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Special Functions
Device

Function

VCC(V)

TLC2932

PLL

3.3 to 5

50-MHz high-accuracy phase-locked loop

@

TLC2933

PLL

3.3 to 5

100-MHz high-accuracy phase-locked loop

5-41

~z4r

TLC7726

Clamping

4.5 to 5.5

Provides active clamping at 0.2 V above Vct and 0.2 V belOW ground

5-3

TLC04/MF4A-50

Filter

3.75

Butterworth fourth-order low-pass

filter

5-7

TLC14IMF4A-100

Filter

3.75

Butterworth fourth-order low-pass switched-capacitor filter

5-7

Amplifier

5

Differential analog buffer amplifier

5-61

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TL32088

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Description

switched~apacitor

Page No.
5-19

l
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PIXEL BUS WIDTH
16 BITS

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VIDEO INTERFACE
PALETIES

I

PIXEL BUS WIDTH
32 BITS

TVP3409
TVP3703

TVP3033

J

l

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PIXEL BUS WIDTH
64 BITS

J

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TVP3026

PIXEL BUS WIDTH
128 BITS

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TVP3030

Video Interface Palettes (RAMDACs)

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Pixel
Bus
Width
(bits)

Number
of PLLs

Hardware
Cursor

Gamma
CorrectIon

Packed
Pixel

Max Resolution and
Refresh Rate

Max
Resolution
with
24 bits/Pixel

Description

Page No.

TVP3026·135

64

Triple

Yes

Yes

Yes

1280 x 1024@ 75 Hz

1280 x 1024

Packed·pixel modes VIP

6-3

TVP3026-175

64

Triple

Yes

Yes

Yes

1600 x 1200@ 60 Hz

1280 x 1024

Packed-pixel modes VIP

6-3

TVP3026-220

64

Triple

Yes

Yes

Yes

1600 x 1200@75 Hz

1280 x 1024

Packed·pixel modes VIP

6-3

TVP3026-250

64

Triple

Yes

Yes

Yes

1600 x 1200@75 Hz

1280 x 1024

Packed-pixel modes VIP

6-3

TVP3030·175

128

Triple

Yes

Yes

Yes

1600 x 1200@ 60 Hz

1600 x 1200

1600 x 1200, 24-bit true color VIP

6-7

TVP3030-220

128

Triple

Yes

Yes

Yes

1600 x 1200@ 75 Hz

1600 x 1200

1600 x 1200, 24-bit true color VIP

6-7

TVP3030-250

128

Triple

Yes

Yes

Yes

1600 x 1200@85 Hz

1600x 1200

1600 x 1200, 24-bit true color VIP

6-7

TVP3033-175

32

Dual

Yes

Yes

Yes

1600 x 1200@ 86 Hz

1600 x 1280

1600 x 1280, 24-bit true color VIP

6-11

TVP3033-220

32

Dual

Yes

Yes

Yes

1600 x 1200@ 86 Hz

1600 x 1280

1600 x 1280, 24-bit true color VIP

6-11

TVP3033-250

32

Dual

Yes

Yes

Yes

1600 x 1200@86 Hz

1600 x 1280

1600 x 1280, 24-bit true color VIP

6-11

TVP3409-135

16

Dual

No

No

Yes

1280 x 1024@75 Hz

1024 x 768

Advanced VIP

6-13

TVP3409-170

16

Dual

No

No

Yes

1600 x 1200@ 60 Hz

1024 x 768

Advanced VIP

6-13

TVP3703-135

16

Dual

No

No

Yes

1280 x 1024@ 75 Hz

1024 x 768

Advanced VIP

6-15

TVP3703-170

16

Dual

No

No

Yes

1600 x 1200@ 60 Hz

1024 x 768

Advanced VIP

6-15

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TLC8044
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Power
(mW)
typ

Conversion
Time (/lS)

Sampling
Rate
(kSPS)
max

Number of
Analog
Inputs

5

400

0.16

6000

6

12

5

400

0.16

6000

3

10

5

400

0.16

6000

3

Resolution
(bits)

VCC(V)

TLC8044

12

TLC8144
TLC8144

Device

~

Z

~

:0

Powerdown
Mode

Linearity Error
(LSB)

Page No.

X
X
X

±1.5

7-3

±1.0

7-33

±1.0

7-61

"tJ

:0

o

o
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~

CROSS REFERENCE GUIDE

Suggested TI
Replacement

Part No

Vendor

Replacement Type

Page No

AD573

TLC1549

Analog Devices

SIMILAR FUNCTIONALITY (see Note 4)

2-153

AD573

TLC1550

Analog Devices

SIMILAR FUNCTIONALITY (see Note 4)

2-167

AD775

TLC5540

Analog Devices

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-209

AD875

TLC5510

Analog Devices

SIMILAR FUNCTIONALITY (see Note 4)

2-197

AD876

TLC876

Analog Devices

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-97

AD1878

TLC320AD57

Analog Devices

SIMILAR FUNCTIONALITY (see Note 4)

2-247

AD1878

TLC320AD58

Analog Devices

SIMILAR FUNCTIONALITY (see Note 4)

2-267

AD1887

TLC320AD58

Analog Devices

SIMILAR FUNCTIONALITY (see Note 4)

2-267

AD7524

TLC7524

Analog Devices

SAME FUNCTIONALITY AND PINOUT (see Note 2)

3-153

AD7524

TLC7528

Analog Devices

SIMILAR FUNCTIONALITY (see Note 4)

3-163

AD7528

TLC7524

Analog Devices

SIMILAR FUNCTIONALITY (see Note 4)

3-153

AD7528

TLC7528

Analog Devices

SAME FUNCTIONALITY AND PINOUT (see Note 2)

3-163

AD7579

TLCI549

Analog Devices

SIMILAR FUNCTIONALITY (see Note 4)

2-153

AD7579

TLV1549

Analog Devices

SIMILAR FUNCTIONALITY (see Note 4)

2-373

AD7628

TLC7628

Analog Devices

SAME FUNCTIONALITY AND PINOUT (see Note 2)

3-177

AD7810

TLV1572

Analog Devices

SAME FUNCTIONALITY (see Note 3)

2-397

AD7812

TLV1570

Analog Devices

SAME FUNCTIONALITY (see Note 3)

2-387

AD7820

TLC0820A

Analog Devices

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-61

AD7890

TLC2543

Analog Devices

SIMILAR FUNCTIONALITY (see Note 4)

2-175

AD7890

TLV2543

Analog Devices

SIMILAR FUNCTIONALITY (see Note 4)

2-409

AD9048

TLC5510

Analog Devices

SIMILAR FUNCTIONALITY (see Note 4)

2-197

AD9048

TLC5540

Analog Devices

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-209

ADC0811

TLC540

National Semiconductor

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-19

ADC0811

TLC541

National Semiconductor

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-19

ADC0820

TLC0820A

Phillips

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-61

ADC0820

TLC0820A

Maxim

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-61

ADC0820

TLC0820A

National Semiconductor

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-61

ADC0830

TLC546

National Semiconductor

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-39

ADC0831

TLC0831

National Semiconductor

EXACT EQUIVALENT (see Note 1)

2-71

ADC0831

TLC549

National Semiconductor

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-51

ADC0832

TLC0832

National Semiconductor

EXACT EQUIVALENT (see Note 1)

2-71

ADC0834

TLC0834

National Semiconductor

EXACT EQUIVALENT (see Note 1)

2-83

ADC0838

TLC0838

National Semiconductor

EXACT EQUIVALENT (see Note 1)

2-83

ADC1001

TLC1541

National Semiconductor

SIMILAR FUNCTIONALITY (see Note 4)

2-123

ADC100l

TLC1550

National Semiconductor

SIMILAR FUNCTIONALITY (see Note 4)

2-167

ADC1005

TLC1541

National Semiconductor

SIMILAR FUNCTIONALITY (see Note 4)

2-123

ADC1021

TLC1541

National Semiconductor

SIMILAR FUNCTIONALITY (see Note 4)

2-123

ADC1031

TLC1549

National Semiconductor

SIMILAR FUNCTIONALITY (see Note 4)

2-153

ADC1038

TLC1542

National Semiconductor

SIMILAR FUNCTIONALITY (see Note 4)

2-133

NOTES:

1.
2.
3.
4.

The device
The device
The device
The device

an EXACT EQUIVALENT in functionality and parametrics to the competitors device
has the SAME FUNCTIONALITY AND PINOUT as the competitors device but is NOT an exact equivalent
has the SAME FUNCTIONALITY as the competitors device, but is not pin-for-pin and/or parametrically equivalent
has SIMILAR FUNCTIONALITY but is not functionally equivalent to the competitors device

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

1-15

CROSS REFERENCE GUIDE

Part No

Suggested TI
Replacement

Vendor

Page No

Replacement Type

ADC1038

TLC1543

National Semiconductor

SIMILAR FUNCTIONAUTY ($Eje Note 4)

ADC1241

TLC2543

National Semiconductor

SAME FUNCTIONAUTY AND PINOUT (see Note 2)

2-133

ADC1241

TLV2543

National Semiconductor

SAME. FUNCTIONALITY AND PINOUT (see Note 2)

2.~409

ADC12030

TLC2543

National Semiconductor

SIMILAR FUNCTIONALITY (see Note 4)

2-175

..

2-175

ADC12032

TLC2543

National Semiconductor

SIMILAR FUNCTIONAUTY (see Note 4)

2-175

ADC12034

TLC2543

National Semiconductor

SIMILAR FUNCTIONALITY (see Note 4)

2-175

ADC12038

TLC2543

National Semiconductor

SIMILAR FUNCTIONALITY (see Note 4)

2-175

ADC12H038

TLC2543

National Semiconductor

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-175

ADC12H038

TLV2543

National Semiconductor

SAME FUNCTIONAUTY AND PINOUT (see Note 2)

2~409

ADS574

TLC2543

Burr Brown

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-175

ADS7804

TLC2543

Burr Brown

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-175

ATI20C409

TVP3409-135

AT&T

SAME FUNCTIONALITY AND PINOUT (see Note 2)

6-13

ATI20C409

TVP3409-170

AT&T

SAME FUNCTIONALITY AND PINOUT (see Note 2)

6-13

CS4328

TMS570.14A

Crystal

SIMILAR FUNCTIONALITY (see Note 4)

3-243

CS5336

TLC320AD57

Crystal

SIMILAR FUNCTIONALITY (see Note 4)

2-247

CS5389

TLC320AD58

Crystal

SIMILAR FUNCTIONALITY (see Note 4)

2-267

CS7820

TLCOB20A

Crystal

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-61

CXA1096

TLC5510

Sony

SIMILAR FUNCTIONALITY (see Note 4)

2-197

CXA1175

TLC5510

Sony

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-197

CXA1176

TLC5510

Sony

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-197

CXA1179

TLC5540

Sony

. SAME FUNCTIONALITY AND PtNOUT(see Note 2)

2-209

CXD1175

TLC1550

Sony

SIMILAR FUNCTIONALITY (see Note 4)

2-167

CXD1175

TLC5510

Sony

EXACT EQUIVALENT (see Note 1)

2-197

CXD1179

TLC5540

Sony

SIMILAR FUNCTIONALITY (see Note 4)

2-209

DAC-8800

TLC5628

Analog Devices

SIMILAR FUNCTIONALITY (see Note 4)

3-.107

DAC08

TLC7524

Motorola

SIMILAR FUNCTIONALITY (see Note 4)

3-153

DAC08

TLC7524

National Semiconductor

SIMILAR FUNCTIONALITY (see Note 4)

3.,,153

DACOBOO

TLC7524

Phillips

SIMILAR FUNCTIONALITY (see Note 4)

3-153

DAC0800

TLC7524

National Semiconductor

SIMILAR FUNCTIONALITY (see Note 4)

3-153

DAC0801

TLC7524

National Semiconductor

SIMILAR FUNCTIONALITY (see Note 4)

3-153

DAC0802

TLC7524

National Semiconductor

SIMILAR FUNCTIONALITY (see Note 4)

DAC0808

TLC7524

SG&-Thomson

SIMILAR FUNCTIONALITY (see Note 4) .

DAC0854

TLC5620

National Semiconductor

SIMILAR FUNCTIONALITY (see Note 4)

3-97

DAC0854

TLV5620

National Semiconductor

SIMILAR FUNCTIONALITY (see Note 4)

3-203

DAC7249

TLC5618

Analog Devices

SAME FUNCTIONALITY (see Note 3)

3-75

DAC7528

TLC7528

Burr Brown

SAME FUNCTIONALITY AND PINOUT (see Note 2)

3-163

DAC8229

TLC7628

Analog Devices

SAME FUNCTIONALITY (see Note 3)

3_177

LTC1091

TLC1543

Linear Technology

SAME FUNCTIONAUTY AND PINOUT (see Note 2)

LTC 1091

Tl,.C1549

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

NOTES:

1.
2.
3.
4.

The deVice
The device
The device
The device

3-153

2-133

,..

2-1.53

an EXACT EQUIVALENT In functionality and parametncs to the competitors deVice
has the SAME FUNCTIONALITY AND PINOUT as the competitors device but is NOT an exact equivalent
has the SAME FUNCTIONALITY as the competitors device, but is not pin-for-pin and/or parametrically equivalent
has SIMILAR FUNCTIONALITY but is not functionally equivalent to the competitors device

~TEXAS

INSTRUMENTS
1-16

3-153
.,

POST OFFICE BOX 655303 • OALLAS, TEXAS 75265

CROSS REFERENCE GUIDE

Part No

Suggested TI
Replacement

Vendor

Replacement Type

LTC1092

TLC1542

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

2-133

LTC1092

TLCl543

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

2-133

LTC1092

TLC1549

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

2-153

LTC1093

TLC1542

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

2-133

LTC1093

TLC1543

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

2-133

LTC1094

TLC1542

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

2-133

LTC1094

TLC1543

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

2-133

LTC1197

TLV1572

Linear Technology

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-397

LTC1199L

TLV1572

Linear Technology

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-397

LTC1283

TLC1549

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

2-153

LTC1290

TLC2543

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

2-175

LTC1291

TLC1543

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

2-133

LTC1283

TLV1543

Linear Technology

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-317

LTC1283

TLV1549

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

2-373

LTC1289

TLC2543

Linear Technology

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-175

LTC1289

TLV2543

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

2-409

LTC1292

TLC1543

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

2-133

LTC1293

TLC1543

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

2-133

LTC1293

TLV1543

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

2-317

LTC1294

TLC1543

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

2-133

LTC1294

TLC2543

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4) .

2-175

LTC1296

TLC2543

Linear Technology

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-175

LTC1296

TLV2543

Linear Technology

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-409

LTC1400

TLC5618

Linear Technology

SAME FUNCTIONALITY (see Note 3)

3-75

Page No

LTC1446

TLC5618

Linear Technology

SAME FUNCTIONALITY (see Note 3)

3-75

MAX148

TLV1570

Maxim

SAME FUNCTIONALITY (see Note 3)

2-387

MAX149

TLV1570

Maxim

SAME. FUNCTIONALITY (see Note 3)

2-387

MAX186

TLC2543

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

2-173

MAX188

TLC2543

Maxim

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-173

MAX192

TLC1543

Maxim

SAME FUNCTIONALITY (see Note 3)

2-133

MAX192

TLC1549

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

2-153

MAX192

TLV1543

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

2-317

MAX192

TLV1544

Maxim

SAME FUNCTIONALITY (see Note 3j

2-335

MAX192

TLV1548

Maxim

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-335

MAX192

TLV1549

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

2-373

MAX500

TLC5620

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

3-97

MAX500

TLV5620

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

3-203

MAX509

TLC5620

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

3-97

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

3-107

MAX509
NOTES:

TLC5628
1.
2.
3.
4.

The device
The device
The device
The device

an EXACT EQUIVALENT In functionality and parametncs to the competitors device
has the SAME FUNCTIONALITY AND PINOUT as the competitors device but is NOT an exact equivalent
has the SAME FUNCTIONALITY as the competitors device, but is not pin-for-pin and/or paraf1\etrically equivalent
has SIMILAR FUNCTIONALITY but is not functionally equivalent to the competitors device

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-17

CROSS REFERENCE GUIDE

Suggested TI
Replacement

Part No

Vendor

Replacement Type

Page No

MAX509

TLV5620

Maxim

SIMILA.R FUNc·noNALITY (see Note 4)

MAX51 0

TLC5620

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

3-203

MAX510

TLV5620

Maxim

SIMILAR FUNCTIONALITY (see Note4)

3~203

MAX528

TLC5628

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

3-107

MAX529

TLC5628

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

3-107

MAX1160

TLC876

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

2-97

MAX1204

TLV1570

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

2-387
3-47

..

3-97

MAX5351

TLC5616

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

MAX5352

TL05616

Maxim

SIMI.LAR Fl)NOTIONALlTY{seeNote 4)

3~47

MAX5628

TLC5620

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

3-97

MAX5628

TLC5628

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

3-107

MAX5628

TLV5620

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

3-203

MAX7524

TLC7524

Maxim

SAME FUNCTIONAl-ITY AND PINOUT(see Note 2)

3-153

MAX7528

TLC7528

Maxim

SAME FUNCTIONALITY AND PINOUT (see Note 2)

3-163

MAX7628

TLC7628

Maxim

SAME FUNCTIONALITY AND PINOUT (see Note 2)

3-177

MAX7820

TLC0820A

Maxim

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-61

MB4056

TLC548

Fujitsu

SIMILAR FUNCTIONALITY (see Note 4)

2-51

MB4056

TLC549

Fujitsu

SIMILAR FUNCTIONALITY (see Note 4)

2-51

MB4066

TLC540

Fujitsu

SIMILAR FUNCTIONALITY (see Note 4)

2-19

MB4066

TLC541

Fujitsu

SIMILAR FUNCTIONALITY (see Note 4)

2-19

MB40778

TLC5602

Fujitsu

EXACT EQUIVALENT (see Note 1)

3-19

MC10319

TLC5540

Motorola

SIMILAR FUNCTIONALITY (see Note 4)

2-209

MC10321

TLC5540

Motorola

SIMILAR FUNCTIONALITY (see Note 4)

2-209

MC10322

TLC5540

Motorola

SIMILAR FUNCTIONALITY (see Note 4)

2-209

MC14050

TLC1541

Motorola

EXACT EQUIVALENT (see Note 1)

2,...123

MC14051

TLC1541

Motorola

SIMILAR FUNCTIONALITY (see Note 4)

2-123

MC14a51

TLC1542

Linear Technology

SIMILAR FUNCTIONALITY (see Note 4)

2-133

MC14051

TLC1542

Motorola

SIMILAR FUNCTIONALITY (see Note 4)

2-133

MC14051

TLC1543

Motorola

SIMILAR FUNCTIONALITY (see Note 4)

2-133

MC14051

TLC1549

Motorola

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-153

MC14444P

TLC546

. Motorola

SAME FUNCTIONALITY AND PINOUT (see Note 2)

MC145040

TLC541

MotOrola·

SAME FU"!CTIONALITY AND PINOUT (see Note 2)

MC145041

TLC542

Motorola

SAM.E FUNCTIONALITY AND PINOUT (see NQle 2)

2-29

MC145051

TLC1543

Motorola

SIMII.,AR FUNCTIONALITY (see Note 4)

2-133

MC145051

TLV1543

Motorola

SIMILAR FUNCTIONALITY (see Note 4)

2-317

MC1508

TLC7524

Motorola

SIMILAR FUNCTIONALITY (see Note 4)

3-153

MP0820

TLC0820A

MPR

SAME FUNOTiQNAL1TYAND PINOUT (see Note 2)

MP7524

TLC7524

MPR

SAME FUNcTIONALITY ANO PINOUT (see Nole 2)

MPR

. SAMEF'l)NCTIONALITY AND PINOUT (see Note 2)

TLC7528

MP7!?28
NOTES:

1.
2.
3.
4.

The deVice
The device
The device
The device

2..,19

2-'61

..

3 ... 153 •

3..,163

an EXACT EQUIVALENT In funcllOnality and parametncs to the competitors deVice
has the SAME FUNCTIONALITY AND PINOUT as the competitors device but is NOT an exact equivalent
has the SAME FUNCTIONALITY as the competitors device. but is not pin-for-pin and/or parametrically equivalent
has SIMILAR FUNCTIONALITY but is not functionally equivalent to the competitors device

~TEXAS

INSTRUMENTS
1-18

2-39
...

POST OFFICE

eox 656303 •

OALLAS. TEXAS 76266

CROSS REFERENCE GUIDE

Part No

Suggested TI
Replacement

Vendor

Replacement Type

MP7628

TLC762B

MPR

SAME FUNCTIONALITY AND PINOUT (see Note 2)

3-1n

MX7524

TLC7524

Maxim

SAME FUNCTIONALITY AND PINOUT (see Note 2)

3-153

MX7528

TLC7528

Maxim

SIMILAR FUNCTIONALITY (see Note 4)

3-163

MX7628

TLC7628

Maxim

SAME FUNCTIONALITY AND PINOUT (see Note 2)

3-ln

NE5036

TLC549

Phillips

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-51

NE5037

TLC549

Phillips

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-51

PCM67

TMS57014

Burr Brown

SIMILAR FUNCTIONALITY (see Note 4)

3-243

PCM69

TMS57014

Burr Brown

SIMILAR FUNCTIONALITY (see Note 4)

3-243

PCM1700

TMS57014A

Bu[r Brown

SIMILAR FUNCTIONALITY (see Note 4)

3-243

PM7524

TLC7524

Analog Devices

SAME FUNCTIONALITY AND PINOUT (see Note 2)

3-153

PM7524

TLC7528

Analog Devices

SIMILAR FUNCTIONALITY (see Note 4)

3-163

PM7528

TLC7524

Analog Devices

SIMILAR FUNCTIONALITY (see Note 4)

3-153

f>M7528

TLC7528

Analog Devices

SAME FUNCTIONALITY AND PINOUT (see Note 2)

3-163

PM7628

TLC7628

MPR

SAME FUNCTIONALITY AND PINOUT (see Note 2)

3-1n

Page No

PM7628

TLC7628

Analog Devices

SAME FUNCTIONALITY AND PINOUT (see Note 2)

3-1n

SGT1703

TVP3703-135

SGS-Thomson

SAME FUNCTIONALITY AND PINOUT (see Note 2

6-15

SGT1703

TVP3703-170

SGS-Thomson

SAME FUNCTIONALITY AND PINOUT (see Note 2

6-15

ST7546

TLC320AD55

SGS-Thomson

SIMILAR FUNCTIONALITY (see Note 4)

4-417

ST7546

TLC320AD56

SGS-Thomson

SIMILAR FUNCTIONALITY (see Note 4)

4-455

TDA8703

TLC5540

Phillips

SAME FUNCTIONALITY AND PINOUT (see Note 2)

2-209

TSC8701

TLC1541

Teledyne (Telcom)

SIMILAR FUNCTIONALITY (see Note 4)

2-123

TSC8701

TLC1550

Teledyne (Telcom)

SIMILAR FUNCTIONALITY (see Note 4)

2-167

TSC8704

TLC1541

Teledyne (Telcom)

SIMILAR FUNCTIONALITY (see Note 4)

2-123

UPD7528

TLC7528

NEC

SAME FUNCTIONALITY AND PINOUT (see Note 2)

3-163

NOTES:

1.
2.
3.
4.

The deVice
The device
The device
The device

an EXACT EQUIVALENT In functionality and parametncs to the competitors deVice
has the SAME FUNCTIONALITY AND PINOUT as the competitors device but is NOT an exact equivalent
has the SAME FUNCTIONALITY as the competitors device, but is not pin-for-pin and/or parametrically equivalent
has SIMILAR FUNCTIONALITY but is not functionally equivalent to the competitors device

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-19

GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR
ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERS
INTRODUCTION
These terms, definitions, and letter symbols are in accordance with those currently approved by the JEDEC
Council of the Electronic Industries Association (EIA) for use in the USA and by the International Electrotechnical
Commission (IEC) for international use.

1. GENERAL TERMS
Analog-to-Digital Converter (ADC)
A converter that uniquely represents all analog input values within a specified total input range by a limited
number of digital output codes, each of which exclusively represents a fractional part of the total analog input
range (see Figure 1).
NOTE:

This quantization procedure introduces inherent errors of one-half LSB (least significant bit) in the
representation since, within this fractional range, only one analog value can be represented free of
error by a single digital output code.
CONVERSION CODE

RANGE OF
ANALOG
INPUT
VALUES

Digital Output
Code

DIGITAL
OUTPUT
CODE

4.5·5.5

0 ... 101

3.5·4.5

0 .•. 100

r - - - - - -----..,.

0 ... 011 )
I 2.5·3.5
'------ ------"
1.5·2.5

0 ..• 010

0.5 ·1.5

0 ... 001

0·0.5

0 ... 000

Ideal Straight Line

0 ... 101

Step

0 ••• 100

/~-.:( 0 ... 011
'----0 ... 010

0 ... 001

0 ... 000

I'-...I..--+----j---+---+--+--+
2
4
o
3
5"

Analog Input
Value

Midstep Value
of 0 ... 011
Quantization
Error
+1/2
LSB

___-+-tIII--+--e+-+-__e--i---4._-+-....- - . Analog Input

o
-1/2
LSB

Figure 1. Elements of Transfer Diagra'!l for an Ideal Linear ADC

~TEXAS
1-20

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

~~

GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Analog-ta-Digital Processor
An integrated circuit providing the analog part of an ADC; provision of external timing, counting, and arithmetic
operations is necessary for implementing a full analog-to-digital converter.
Companding DAC
A DAC whose transfer function complies with a compression or expansion law.
NOTE 1: The corresponding ADC normally consists of such a companding DAC and additional external
circuitry.
NOTE 2: The compression or expansion law is usually a logarithmic function, e.g., A-law or 11-law.
Conversion Code (of an ADC or a DAC)
The set of correlations between each of the fractional parts of the total analog input range or each of the digital
input codes, respectively, and the corresponding digital output codes or analog output values, respectively (see
Figures 1 and 2).
NOTE:

Examples of output code formats are straight binary, 2's complement, and binary-coded decimal.
Analog Output
Value

5

4

+------

Step Height (1 LSB)

3

2
1 4 - - - Step Value

o~--r--~-~-+-r~-r--~--'

0 ... 000

0 ... 001 0 ... 010

9... 01~

Digital Input Code

0 ... 100 0 ... 101

l )'

'--' , / ' Step

CONVERSION CODE
Digital Input Code
Analog Output Value

r

..,

0 ... 000

0 ... 001

0 ... 010

I 0 ... 011 I

0 ... 100

0 ... 101

0

1

2

IIL _ _
3 _ .JI

4

5

Figure 2. Elements of Transfer Diagram for an Ideal Linear DAC
Digital-to-Analog Converter (DAC)
A converter that represents a limited number of different digital input codes by a corresponding number of
discrete analog output values (see Figure 2)
NOTE:

Examples of input code formats are straight binary, 2's complement, and binary-coded decimal.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303. DALLAS, TEXAS 75265

1-21

GLOSSARY.
TERMS, DEFINITIONS AND LETTER SYMBOLS
Full Scale (of a unipolar ADC or DAC)
A term used to refer a characteristic to that step within the transfer diagram whose nominal midstep value or
nominal step value has the highest absolute value [see Figure 3(a) for a linear unipolar ADCj.
NOTE 1: The subscript for the letter symbol of a characteristic at full scale is FS.
NOTE 2:

In place of a letter symbol, the abbreviation FS is in common use.

Full Scale, Negative (of a bipolar ADC or DAC) [see Figures 3(b) and 3(c))
A term used to refer a characteristic to the negative end of the transfer diagram, that is, to the step whose nominal
midstep value or nominal step value has the most-negative value.
NOTE 1: The subscript for the letter symbol of a characteristic at negative full scale is FS- (VFS-, IFS-).
NOTE 2:

In place of a letter symbol, the abbreviation FS- is in common use.

Full Scale, Positive (of a bipolar ADC or DAC) [see Figure 3(b) and 3(c)]
A term used to refer a characteristic to the positive end of the transfer diagram, that is, to the step whose nominal
midstep value or nominal step value has the most-positive value.
NOTE.1: The subscript for the letter symbol. of a characteristic at positive full scale is FS+ (VFS+, IFS+)
NOTE 2:

In place of a letter symbol, the abbreviation FS+ is in common use.

Full-Scale Range, Nominal (of a linear ADC or DAC) (VFSRnom, IFSRnom) (see·Figure 3)
The total range in analog values that can be coded with uniform accuracy by the total number of steps with this
number rounded to the next higher power of 2.
NOTE:
Example:

In place of the letter symbols, the abbreviation FSR(nom) can be used.
Using a straight binary n-bit code format, it follows:
- for an ADC: FSR(nom) = 2 n x (nominal value of step width)
- for a DAC: FSR(nom) = 2 n x (nominal value of step height)

Full-Scale Value, Nominal (VFSnom, IFSnom)
A value derived from the nominal full-scale range:
- for a unipolar converter: VFSnom = VFSRnom
- for a bipolar converter: VFSnom = 1/2 VFSRnom (see Figure 3)
NOTE 1:

In a few data sheets, this analog value is used as a reference value for adjustment procedures or
as a rounded value for the full-scale range(s).

NOTE 2:

In place of letter symbols, the abbreviation FS(nom) is in common use.

Full-Scale Range, (Practical) (of a linear ADC or DAC) (VFSR, IFSR) (VFSRpr, IFSRpr) (see Figure 3)
The total range of analog values that correspond to the ideal straight line.
NOTE 1: The qualifying adjective practical can usually be deleted from this term provided that, in a very few
critical cases, the term nominal full-scale range is not also shortened in the same way. This permits
use of the shorter letter symbols or abbreviations (see Note 2).
NOTE 2:

In place of the letter symbols, the abbreviations FSR and FSR(pr) are in common use.

NOTE 3: The (practical) full-scale range has only a nominal value because it is defined by the end points of
the ideal straight line.
.
Example:

Using a straight binary n-bit code format, it follows:
- for an ADC: FSR = (2n -1) x (nominal value of step width)
- for a DAC: FSR = (2n -1) x (nominal value of step height)

~TEXAS

1-22

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Digital Output
Code

------------------1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
VZS~
I
......l-.--t----t----t----t---+--+--.-.I

r-.

o

2
3
4
5
678
~14----- VFSR ----~~

VFS(NOM)

Analog Input
Value

(a) UNIPOLAR ADC
Digital Output
Code

Digital Output
Code

---------1

---------1
I
I
I
I
I
I
I
I

ra

+4

e=:.....--t---+--+-,....;...-'-+--+--.-.. VI
I
I
I
I
I
I
I
I
I
L

-'4

I
I
I
I
I
I
I
I

+VFS(NOM)

~~----- VFSR - - - - - - . t

=

I
I
I
I
I
I
I
I

VZS:\
-VFS(NOM)
VFS-

-2

_____

-1

~__

_ ______ _

t e - - - - - - VFSR - - - - - - - . t

VI Analog
Input Value

(b) BIPOLAR ADC WITH TRUE ZERO

(e) BIPOLAR ADC WITH NO TRUE ZERO

Figure 3. Ideal Straight Line, Full-Scale Value and Zero-Scale Value
(Shown for Ideal Linear ADCs)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-23

GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Gain Point (of an adjustable ADC or DAC)

The point in the transfer diagram corresponding to the midstep value (for an ADC) or the step value (for a DAC)
of the step for which gain error is specified (usually full scale), and in reference to which the gain adjustment
is performed (see Figures 4 and 5).
NOTE:

Gain adjustment causes only a change of the slope of the transfer diagram, without changing the offset
error.

Ideal Straight Line (of a linear ADC or DAC)

In the transfer diagram, a straight line between the specified points for the most-positive (least-negative) and'
most-negative (least-positive) nominal midstep values or nominal step values, respectively (see Figures 1, 2,
and 3).
NOTE:

The ideal straight line passes through all the points for nominal midstep values or nominal step values,
respectively.

Linear ADC

An ADC having steps ideally of equal width excluding the steps at the two ends of the total range of analog input
values.
NOTE:

Ideally, the width of each end steps is one half of the width of any other step (see Figure 1).

Linear DAC

A DAC having steps ideally of equal height (see Figure 2).
LSB, Abbreviation

The abbreviation for Least Significant Bit, that is, for the bit that has the lowest positional weight in a natural
binary numeral.
Example:

In the natural binary numeral 1010, the rightmost bit 0 is the LSB.

LSB, Unit Symbol (for linear converters only)

The unit symbol for the magnitude of the analog resolution of a linear converter, which serves as a reference
unit to express the magnitude of other analog quantities of that same converter, especially of analog errors, as
multiples or submultiples of the magnitude of the analog resolution.
Example:
NOTE:

1/2 LSB means an analog quantity equal to 0.5 times the' analog resolution.

The unit symbol LSB refers to the fact that, for a natural binary code, the analog resolution corresponds
to the nominal positional weight attributed to the least significant bit of the binary numeral.
In this case, the identity:
1 LSB = analog resolution
leads, for an n-bit resolution, to:
1 LSB

=

FSR
2" - 1

= FSR(nom)
2"

Midstep Value (of an ADC)

The analog value for the center of the step excluding the steps at the two ends of the total range of analog input
values.
NOTE:

For the end steps, the midstep value is defined as the analog value that results when the analog value
for the transition to the adjacent step is reduced or enlarged, as appropriate, by half the nominal value
of the step width (see Figure 1).

~TEXAS

1-24

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

GLOSSARY
TERMS, DEFINITIONS AND LETIER SYMBOLS
Gain Point

111

-------------~~
1// I

r"71
1/
I

110

rT

101

~

1
0

~

g

Ideal Straight

I

Lln~

~~/

100

r

011

,L..J
/1

010

.,L-1

001

//1
2

4

3

5

6

7

Analog Input Value
(a) BEFORE ADJUSTMENT
Gain Adjustment ~

111

111

110

110

101

a

1
0

~

g

r-1

--~----------~-~

101

1

CD
'0

8

100

'5

011

1

011

is

010

I
I

I
I

1 1/
1 V

rT'"""~J/~1

I

LJ,/

'ED

010

17
),/

r-1~I~<....1

100

!!

1
/~ I
I »< I I
1
~/
I
1/1
I
1

I

~

I

11/
001

001

000 ~~Y---~---r---+--~---4--~
7
6
0112345
~
Analog Input Value

000

~

0

I

I
I

2

3

4

5

6

7

Analog Input Value
(e) AFTER OFFSET AND GAIN ADJUSTMENTS

Offset Adjustment

(b) AFTER OFFSET ADJUSTMENT
NOTE A: In the above examples, the offset point is referred to the step with the digital code 000, and the gain point is referred to the step with
the digital code 111,

Figure 4. Adjustment in Offset Point and Gain Point for an ADC

~TEXAS

INSTRUMENTS '
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-25

GLOSSARY
TERMS; DEFINITIONS AND LETTER SYMBOLS
----------------~

7

/:.~

,
6

CD
:::J

5

j

0

C)

/

/

)1'/

3

0

~

c(

.

/

2

/
/

/

/

II / /

/

/

/

/

/""

/

/

/

/

,tI'//

/

/

'S 4
a.
'S

/~

Gain Point

"."
~

Ideal Straight Line

/

0~---+--_+---4--~----~--+___1

000

Offset Point

001

010

011

100

101

110

111

Digital Input Code
(a) BEFORE ADJUSTMENT

~;:r~]~ment

,
7

----------------~

7

x/ /1~

6

Value Before
Adjustment ~

6

/

...

"'AX/"......
~.....

1
1
1

,/

1

X ~
~

1

1

X ~

1

~

'S

4

~
o
8'

3

c(

2

iii
c

~--~---+--~----r---+_--_r--_1

010

011

,100

101

110

111

o

1

:

Value After Offset
Adjustment

~

I

1

1

//;(/ ~,

JI: /
/

1

.;

000

//

//
/-// X
/ /ox

5

1

X 'l
.?
X .,,-

o

1

______________

:
1
1

~~

:

~--+---+---+---+---+---+-~

000

001

010

Digital Input Code

011

100

101

110

111

Digital Input Code
(c) AFTER OFFSET AND GAIN ADJUSTMENTS

(b) AFTER OFFSET ADJUSTMENT

NOTE A: In the above examples, the offset point is referred to the step with the digital code 000, and the gain point is referred to the step with
the digital code 111.

Figure 5. Adjustment in Offset and Gain Point for aDAC
Midstep Value, Nominal (of an ADC)
\

A specified analog value within a step that is ideally represented free of error by the corresponding digital output
code (see Figure 1).

~TEXAS

INSTRUMENTS
1-26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS

0 ••• 111

1Missing Code - - - - - - - . :

0 ... 110
1

I

0 •.• 101

1

~'!5

0 ... 100

~

_

0 ... 011

I

i

0 .•. 010

g

I

I

r---1
I

0 ... 001

Missing Code

..&--+--+--+--+--+--+--+-..

0 ..• 000 . .
0,

3
4
2
5
Analog Input Value (LSB)

6

7

Figure 6. Missing Code for an ADC
Missing Code (of an ADC)

An intermeliiate code that is absent when the changing analog input to an ADC causes a multiple code change
in the digital output (see Figure 6).
Monotonicity (of an ADC or a DAC)

A property of the transfer function that ensures the consistent increase or decrease of the analog output of a
DAC or the digital output of an ADC in response to a consistent increase or decrease of the digital or analog
input. respectively (Figure 7 illustrates non monotonic conversion).
NOTE:

An intermediate increment with the value of zero does not invalidate monotonicity.

:'I
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265

1-27

GLOSSARY
TERMS, DEFINITiONS AND LETTER SYMBOLS

r

0 ... 111

7

I

r--1
I
r--1
I

0 •.. 110
0 ... 101
CD

-g
(J

~

S

j

~

!i 0 ... 100
CI.
.!i
0

6

iii'
f/)
:::!. 5

0 ... 011

rJ
I

r--1
I
r--1
I

0 ... 010
0 ... 001

I

!i

4

~

I
I
I

0

Cl

3

0

'ii

c

L-J

c(

2

0 ... 000
2
4
3
5
Analog Input Value (LSB)

0

6

7
0 ... 001

(a)ADC

0 ... 011

0 ... 101

0 ... 111

Digital Input Code
(b) DAC

Figure 7. Nonmonotonic Conversion of an ADC or DAC
Multiplying DAC

A DAC having at least two inputs, at least one of which is digital, and whose analog output value is proportional
to the product of the inputs.
Nonlinear ADC or DAC

An ADC or a DAC with a specified nonlinear transfer function between the nominal midstep values or nominal
step values, respectively, and the corresponding step widths or step heights, respectively.
NOTE:

The function may be continuously nonlinear or piece-wise linear.

Offset Point (of an adjustable ADC or DAC)

The poinf in the transfer diagram corresponding to the midstep value (for an ADC) or the step value (for a DAC)
of the step about which the transfer diagram rotates when gain is adjusted (see Figures 4 and 5).
NOTE:

Offset adjustment must be performed with respect to this point so that it causes only a parallel
displacement of the transfer diagram, without changing its slope.

Resolution (general term)

NOTE 1: Resolution as a capability can be expressed in different forms: (see resolution, analog, resolution,
numerical, and resolution, relative).
NOTE 2: Resolution is a design parameter and therefore has only a nominal value.
NOTE 3: The terms for these different forms may all be shortened to resolution if no ambiguity is likely to occur
(for example, when the dimension of the term is also given).
Resolution (of an ADC)

The degree to which nearly equal values of the analog input quantity can be discriminated.

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INSTRUMENTS
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GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Resolution (of a DAC)
The degree to which nearly equal values of the analog output quantity can be produced.

Resolution, Analog (of a linear or nonlinear ADC or DAC)
For an ADC: The nominal value of the step width.
For a DAC: The nominal value of the step height.
NOTE:

For a linear ADC or DAC, the constant magnitude of the analog resolution is often used as the
reference unit LSB.

Resolution, Numerical
The number (n) of digits in the chosen numbering system necessary to express the total number of steps.
NOTE 1: The numbering system is normally a binary or a decimal system.
NOTE 2:

In the binary-coded-decimal numbering system, the term 1/2 digit refers to an additional decimal digit
with the highest positional value, but limited to the decimal figures 0 or 1 as it is represented by only
a single bit. This additional digit serves to double the range of values covered by the other n digits.

Resolution, Relative (of a Linear ADC or DAC)
The ratio of the analog resolution to the full-scale range (practical or nominal).
NOTE:

This ratio is normally expressed as a percentage of the full-scale range [% of FSR, % of FSR(nom)].
For high resolutions (high value of n), it is of little importance whether this ratio refers to the practical
or nominal full-scale range.

Step (of an analog-to-digital or digital-to-analog conversion)
In the conversion code: Any of the individual correlations.
In the transfer diagram: Any part of the diagram equating to an individual correlation.
For an ADC, a step represents both a fractional range of analog input values and the corresponding digital output
code (see Figure 1).
For a DAC, a step represents both a digital input code and the corresponding discrete analog output value (see
Figure 2).

Step Height (Step Size) (of a DAC)
The absolute value of the difference in step value between two adjacent steps in the transfer diagram. (see
Figure 2).
NOTE:

For companding DACs, the term step size is in general use.

Step Value (of a DAC)
The value of the analog output representing a digital input code (see Figure 2).

Step Value, Nominal (of a DAC)
A specified step value that represents free of error the corresponding digital input code (see Figure 2).

Step Width (of an ADC)
The absolute value of the difference between the two ends of the range of analog values corresponding to one
step (see Figure 1).

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1-29

GLOSSARY
TERMS; DEFINITIONS AND LEITER SYMBOLS
Temperature Coefficients of Analog Characteristics (a)
NOTE 1: The letter symbol for the temperature coefficient of an analog characteristic consists of the letter
symbol a with a subscript referring to the relevant characteristic.
Example:

Temperature coefficient of the gain error: aEG

NOTE 2: Temperature coefficients are usually specified in parts per million (relative to the full-scale value) per
degrees Celsius, that is, in ppm/cC.
Zero Scale (of an ADC or a DAC with true zero) [see Figures 3(a) and 3(b)]
A term used to refer a characteristic to the step whose nominal midstep value or nominal step value equals zero.
NOTE 1: The subscript for the letter symbol of a characteristic at zero scale is ZS.
NOTE 2:

In place of a letter symbol, the abbreviation ZS is in common use.

Zero Scale, Negative (of an ADC or a DAC with no true zero) [see Figure 3(c)]
A term used to refer a characteristic to the negative step closest to analog zero.
NOTE .1: The subscript for the letter symbol of a characteristic at negative zero scale is ZS- (Vzs-, IzS-)'
NOTE 2:

In place of a letter symbol, the abbreviation ZS- is in common use.

Zero Scale, Positive (of an ADC or a DAC with no true zero) [see Figure 3(c)]
A term used to refer a characteristic to the positive step closest to analog zero.
NOTE 1: The subscript for the letter symbol of a characteristic at positive zero scale is ZS+ (Vzs+, Izs+).
NOTE 2: In place of a letter symbol, the abbreviation ZS+ is in common use.

2. STATIC PERFORMANCE
Accuracy (see Errors, Part 4)
Asymmetry, Full-Scale (of a DAC with a bipolar analog range) (~IFSS, ~VFSS)
The difference between the absolute values of the two full-scale analog values.
Compliance, Current (of a DAC) (IO(op»
The permissible range of output current within which the specifications are valid.
Compliance, Voltage (of a DAC) (VO(Op»
The permissible range of output voltage within which the specifications are valid.
Error (see Part 4)
Supply Voltage Sensitivity, (of a DAC) (ksvs)
The change in full scale output current (or voltage) caused by a change in supply voltage.
NOTE:

This sensitivity is usually expressed as the ratio of the percent change of full-scale current (or voltage)
.
to the percent change of supply voltage.

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INSTRUMENTS
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GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
3. DYNAMIC PERFORMANCE
Conversion Rate (of an externally controlled ADC) (fe)

The number of conversions per unit time.
NOTE 1: The maximum conversion rate should be specified for full resolution.
NOTE 2: The conversion rate is usually expressed as the number of conversions per second.
NOTE 3:

Due to additionally needed settling or recovery times, the maximum specified conversion rate is
smaller than the reciprocal of the worst-case conversion time.
.

Conversion Time (of an ADC) (tel

The time elapsed between the command to perform a conversion and the appearance at the converter output
of the complete digital .representation of the analog input value.
Delay Time, (Digital) (of a linear or a multiplying DAC) (td. tdd)

The time interval between the instant when the digital input changes and the instant when the analog output
passes a specified value that is close to its initial value, ignoring glitches (see Figure 8).
NOTE:

For a multiplying DAC, the full term and the additional subscript d must be used to distinguish
between the digital and the delay time.

Delay Time, Reference (of a multiplying DAC) (tdr)

The time interval between the instant when a step change of the reference voltage occurs and the instant when
the analog output passes a specified value that is close to its initial value.
Feedthrough Capacitance (CF)

The value of the capacitance for a specified value of R in an .equivalent circuit for the calculation of the
feedthrough error.
NOTE:

The equivalent circuit consists of a high-pass R-C filter between the reference input and the analog
output.

Feedthrough Error (see Part 4)
Glitch (of a DAC)

A short, undesirable transient in the analog output occurring following a code change at the digital input (see
Figure 8).
Glitch Area (of a DAC)

The time integral of the analog value of the glitch transient.
NOTE 1: Usually, the maximum specified glitch area refers to a specified worst-case code change.
NOTE 2:

Instead of a letter symbol, the abbreviation GA is in use.

Glitch Energy (of a DAC)

The time integral of the electrical power of the glitch transient.
NOTE 1: Usually, the maximum specified glitch energy refers to a specified worst-case code change.
NOTE 2:

Instead of a letter symbol, the abbreviation GE is in use.

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GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Analog Output

1 4 - - - - - t sd

-----~

1 4 - - - tsa -----.t
Final Value

~,(Glitch

=
=

tsd Digital Settling Time
tsa Analog Settling Time
Somd Digital Slew Rate
tdd = Digital Delay Time

Digital Change

=

J

Figure 8. Output Characteristics of a Linear or a Multiplying DAC
for a Step Change in the Digital Input Code
Pedestal (Error) (Ep) (see Part 4)
Ramp Delay, Steady-state (of a multiplying DAC) (td(ramp)
The time separation between the actual curve of the analog output and the theoretical curve (with no delay) for
a ramp in reference voltage,after the settling time to steady-state ramp has elapsed (see Figure 9).

Settling Time, Analog (of a DAC) (tsa)
The time interval between the instant when the analog output passes a specified value and the instant when
the analog output enters for the last time a specified error band about its final value (see Figures 8 and 10).

Settling Time, (Digital) (of a linear or a multiplying DAC) (ts, tsd)
The time interval between the instant when the digital input changes and the instant when the analog output
value enters for the last time a specified error band about its final value (see Figure 8).
NOTE:

For a multiplying DAC, the full term and the additional subscript d must be used to distinguish between
the digital and the settling time.

Settling Time, Reference (of a multiplying DAC) (t sr)
The time interval between the instant when a step change of the reference voltage occurs and the instant when
the analog output enters for the last time a specified error band about its final value (see Figure 10).
NOTE:

Specifications for the reference settling time are usually given for the highest allowed step change in
reference voltage.

Settling Time to Steady-State Ramp (of a multiplying DAC) (ts(ramp)
The time interval between the instant a ramp in the reference voltage starts and the instant when the analog
output value enters for the last time a specified error band about the final ramp in the output (see Figure 9).

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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Analog Output

Ramp in Reference
Voltage Vref

,":\""

~

,~

,&

v

).,<~ ~""-:7.
""
Final Ramp In Output

, ",,"" ;""
" """",,,,""yo

Specified Error Band

--~-""/"" ""

"

,""'''''-:::'- ""
v""",,""

-_..../" ""f
i4-----.t- td(ramp)
~--ts(ramp)

ts(ramp)
td(ramp)

------.t

=Settling Time to Steady·State Ramp Delay
= Steady·State Ramp Delay

Figure 9. Output Characteristics for a Ramp in Reference Voltage of a Multiplying OAC
Analog Output

tsa

r---I
I

Specified
Error Band (± e)

~--~~l-

Vref~1

I
I
___ ...1I

Final Value
tdr = Reference Delay Time
tsr Reference Settling Time
tsa Analog Settling Time
Somr = Reference Slew Rate

=
=

Figure 10. Output Characteristics for a Step Change in Reference Voltage of a Multiplying OAC
Skewing Time, Internal (of a OAC)

The difference in internal delay between the individual output transitions for a given change of digital input.
NOTE:

The internal (and external) skew has a major influence on the settling time for critical changes in the
digital input, for example, for a 1·LSB change from 011 ... 111 to 100 ... 000, and is an important
source of commutation noise.

Slew Rate, (Digital) (of a linear or a multiplying OAC) (SOM, SOMO)

The maximum rate of change of the analog output value when a change of the digital input code causes a large
step change of the analog output value (see Figure 8).

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1-33

GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
NOTE 1: For a multiplying DAC, the full term and the additional subscript D must be used .to distinguish
between the digital and the slew rate.
NOTE 2: The abbreviations SR and SR(dig) are also used.

Slew Rate, Reference (of a multiplying OAC) (SOMR)
The maximum rate of change of the analog output following a large step change of the reference voltage (see
Figure 10).
NOTE:

The abbreviation SR(ref) is also used.

4. ERRORS, ACCURACY
The definitions in this section describe the errors as the difference between the actual value and the nominal
value of the analog quantity. As such they may be expressed in conventional units (for example, millivolts) or
as multiples or submultiples of 1 LSB. An error can also be expressed as a relative value, for example, in % of
FSR. In this case, it is common practice to use the same term as for the analog value.

Absolute Accuracy Error
Synonym for total error.

Feedthrough Error (of a multiplying OAt) (EF)
An error in analog output due to variation in the reference voltage that appears as an offset error and is
proportional to frequency and amplitude of the reference signal.
NOTE 1: The specification for the feedthrough error is given for the digital input for which the offset error is
specified, and for a reference signal of specified frequency and amplitude.
NOTE 2: This error may also be expressed as a peak-to-peak analog value.

Full-Scale Error (of a linear AOCor OAC) (EFS)
The difference between the actual midstep value or step value and the nominal midstep value or step value,
respectively, at specified full scale.
NOTE:

Normally, this error specification is applied to converters that have no arrangement for an external
adjustment of offset error and gain error.

Gain Error (of a linear AOC or OAC) (Eo)
For an ADC:

The difference between the actual midstep value and the nominal midstep value in the transfer
diagram at the specified gain point after the offset error has been adjusted to zero [see
Figure 11 (a)].

For a DAC:

The difference between the actual step value and the nominal step value in the transfer
diagram at the specified gain pOint after the offset error has been adjusted to zero [see
Figure 11 (b)].

NOTE:

See Notes 1 and 2 under Offset Error.

~TEXAS

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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Nominal Gain
Point

----------~T-J

111

(1/2 LSB) --111I0Il1----.1

Actual Diagram

.,
;3

\

I
I
I

I

/

/

/y
I
I
// I
_"""T"..I.I-/ _.J

~

101

I /
I/

.1'

I

I+-+-.r---l

~ 5

/,;II'

5
6
Analog Input Value (lSB)

7

//

//
//
//
//

4

~I-()----+----+-------1
o

-/ /~

"

Ideal Diagram

T ///:

//

~//

Ideal Diagram

'SQ.

Gain Error
(-3/4 LSB)

~-

'-

------~

Gain Error
(-11/4 lSB)

I /
1/

o

000

---------

7

I

.1/ I

/1

I ~r---'.'---r-....I-

110

'S
Q.
'S

5

Nominal Gain Point ~

/

/

/!

Actual Gain
Point

//

000

100

(a)ADC

I
I
I

::;;-1:

......." "...

/1'

0~\1

/1

I

I
I
I
I
I

I
101
110
Digital Input Code

111

(b)DAC

Figure 11. Gain Error of a Linear 3-Bit Natural Binary Code Converter
(Specified at Step 111), After Correction of the Offset Error
Instability, Long-Term (Accuracy) (~E(dt), ~E(t»
The additional error caused by the aging of the components and specified for a longer period in time.
Linearity Error, Best-Straight-Line (of a linear and adjustable ADC) (EL(adj»
The difference between the actual analog value at the transition between any two adjacent steps and its ideal
value after offset error and gain error have been adjusted to minimize the magnitude of the extreme values of
this difference [see Figure 12(a)].
NOTE 1: The inherent quantization error is not included in the best-straight-line linearity error of an ADC. The
ideal value for the transition corresponds to the nominal midstep value ± 112 LSB.
NOTE 2:

For a uniformly curved transfer diagram, the extreme values will be very close to half of the magnitude
of the end-point linearity error [see Figure 12(a)].

Linearity Error, Best-Straight-Line (of a linear and adjustable DAC) (EL(adj»
The difference between the actual step value and the nominal step value after offset error and gain error have
been adjusted to minimize the magnitude of the extreme values of this difference [see Figure 12(b)].
NOTE:

For a uniformly curved transfer diagram, the extreme values will be very close to half of the magnitude
of the end-point linearity error [see Figure 12(b)].

-!!1
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1-35

GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Remaining Gain Error
(+1/4 lSB)

1 r--

Remaining Gain Error

---------------~

111

(-1/4lSB) I ..Y __
_____________

7

/11 I

~iI

110

JI'

~II
;,

101
III

~
'5
!0
~

~

~

100

'~

011

)r
0L

VI'

000

I

~--J~

010
001

i

1

I
~

6

iii' 5
til
:::!.
III
::I

~

!

0

!
I
I
I

Extreme Value of the
linearity Error in the
Diagram (-1/4 lSB)

4

'5

'"0

iii
c

3

o
2
3
4
5
Analog Input Value (lSB)

Remaining Offset
Error (+114 lSB)

6

Extreme Value of the
linearity Error in the
Diagram (+1/4 lSB)

2

//".

,

/.

_~

At Transition
011/100

~.J

011

//

/!/

(

~. rI %

100

6

//~---.

rJj~ ~ (-;LSB)

010

I .r /

001
)

~
~

oI~

End-Point Lin. Error

4
2
3
5
Analog Input Value (lSB)

o __
7

000

:

I

Jf

. /.

End-~nt lin. Error

/'''

6

V

.t.t~AtStep

.t

At Transition
001/010 (-1/4 LSB)

000
0

*

'//

/.

At Step
/ ' 011 (1/2 lSB)

I
I
I
I
I
I

I

I
:

001 (1/4 lSB)

--~--~--~--_+--~--_1--~

001

010

011

100

101

110

111

Digital Input Code

(s)ADC

(b)DAC

Figure 14. End-Point Linearity Error of a Linear 3-Bit Natural Binary-Coded ADC or DAC
(Offset Error and Gain Error are Adjusted to the Value Zero)
Offset Error (of a linear ADC or DAC) (EO)
For an ADC: The difference between the actual midstep value and the nominal midstep value at the offset point
[see Figure 15(a)].
For a DAC:
NOTE 1:

The difference between the actual step value and the nominal step value at the offset point
[see Figure 15(b)].
.

Usually, the specified steps for the specification of offset error and gain error are the steps at the ends
of the practical full-scale range. For anADC, the midstep value of these steps is defined as the value
for a point 1/2 LSB apart from the adjacent transition (see Figures 11 and 15).

NOTE 2: The terms offset error and gain error should be used only for error that can be adjusted to zero.
Otherwise, the terms zero-scale error and full-scale error should be used.

Pedestal (Error) (Ep)
A dynamic offset produced in the commutation process.

1-38

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GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS

,.",,' /

",,""

011

I

CD

'8

0

'S

~

010

lit,.
I "-

0

~Dl

:

is

Actual ~
,."
Diagram ~,.~

3

I
I
I
I

,;j
/

Actual
Diagram

//

/

/

~
/'-

/

/

Ideal Diagram

/

Offset Error
(+11/4 LSB)

14--+1--- +1/2 LSB

Nominal
Offset Point

//

//

~
/

I

001

000

""
,/" ""

/

/

[I

2
3
Analog Output Value

Actual
Offset Point

Offset Error
(+11/4 LSB)

Nominal
Offset Point

Digital Input Code

(b)DAC

·1
(a)ADC

Figure 15. Offset Error of a Linear 3-Bit Natural Binary Code Converter (Specified at Step 000)
Quantization Error, Inherent (of an ideal ADC)
Within a step, the maximum (positive or negative) possible deviation of the actual analog input value from the
nominal midstep value.
NOTE 1: This error follows necessarily from the quantization procedure. For a linear ADC, its value equals
± 1/2 LSB (see Figure 1).
NOTE 2: The term resolution error for the inherent quantization error is deprecated, because resolution as a
design parameter has only a nominal value.

Rollover Error (of an ADC with decimal output and auto-polarity) (ERO)
The difference in output readings with the analog input switched between positive and negative values of the
same magnitude (close to full scale).

Total Error (of a linear ADC) (ET)
The maximum difference (positive or negative) between an analog value and the nominal midstep value within
any step [see Figure 16(a)).
NOTE 1: If this error is expressed as a relative value, the term relative accuracy error should be used instead
of absolute accuracy error.
NOTE 2: This error includes contributions from offset error, gain error, linearity error, and the inherent
quantization error.

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GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Total Error (of a linear DAC) (ET)
The difference (positive or negative) between the actual step value and the nominal step value for any step [see
Figure 16(b)].
NOTE 1:

If this error is expressed as a relative value, the term relative accuracy error should be used instead
of absolute accuracy error.

NOTE 2: This error includes contributions from offset error, gain error, and linearity error.

r
/
I /

0 ... 111

~/

0 ... 110

..

I

"S

0 ... 100

~

I /

0

~

0 ... 011

B

f/

~
V

'0.

is

/

~n

'D
0

0

/

0 ... 010

~

0 ... 001

f. L_~

/ I

I~

,,//;4/
.//

Total Error
At Step 0 ... 101
(-11/4 LSB)

.

/

J"-

/ ?/ /
/
/

/

JI' ~

/-

/

/

/

/

// .t /

Total Error
At Step
0 ... 001 (1/2 LSB)

/

~/
//

6

r--:1-

0 ... 101

,.

",i'

~/

7

Total Error
At Step 0 ... 011
(1114 LSB)

o

0 ... 000

4
2
5
3
Analog Input Value (LSB)

0

6

7
0.,.001

(a)ADC

0 ... 011

0 ... 101

0 ... 111

Digital Input Code
(b)DAC

Figure 16. Absolute Accuracy Error, Total Error of a Linear ADC or DAC
Zero-Scale Error (of a linear ADC or DAC) (EzS)
The difference between the actual midstep value or step value and the nominal midstep value or step value,
respectively, at specified zero scale.
NOTE:

Normally, this error specification is applied to converters that have no arrangement for an external
adjustment of offset error and gain error.

5. Dynamic and Sigma-Delta Definitions
Resolution
The number of different output codes possible. Expressed as N, where 2N is the number of available output
codes.

Dynamic Range
The ratio of the largest allowable input Signal to the noise floor.

Total Harmonic Distortion
The ratio of the rms sum of all harmonics to the rms value of the largest allowable input signal. Units in dB's.

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GLOSSARY
TERMS, DEFINITIONS AND LETTER SYMBOLS
Signal to Intermodulation Distortion
The ratio of the rms sum of two input signals to the rms sum of all discernible intermodulation and harmonic
distortion products.

Linearity Error
The deviation of a code from a straight line passing through the endpoints of the transfer function after zeroand full-scale errors have been accounted for. Zero-scale is a point 1/2 LS8 below the first code transition and
full-scale is a point 1/2 LSB beyond the code transition to all ones. The deviation is measured from the middle
of each particular code. Units in %FS.

Differential Nonlinearity
The deviation of a code's width from the ideal width in LSB's.

Positive Full Scale Error
The deviation of the last code transition from the ideal, (Vref - 1.5 LSB).

Positive Full Scale Drift
The drift in effective, positive, full-scale input voltage with temperature.

Negative Full Scale Error
The deviation of the first code transition from the ideal, (-Vref + 0.5 LS8).

Negative Full Scale Drift
The drift in effective, negative, full-scale input voltage with temperature.

Bipolar Offset
The deviation of the midscale transition from the ideal. The ideal is defined as the middle transition lying on a
straight line between actual positive full-scale and actual negative full-scale.

Bipolar Offset Drift
The drift in the bipolar offset error with temperature.

Absolute Group Delay
The delay through the filter section of the part.

Passband Frequency
The upper -3 dB frequency.

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2-1

I

Contents.
Page

TLC7135, ICL7135: ..... : ....................................... ~ .......... 2-3
TL5501 : ........................................ ; ........................... 2-13
TLC540,TLC541 : .......................................................... 2-19
TLC542: ............... ; ................................................... 2-29
TLC545, TLC546: .......................................................... 2-39
TLC548, TLC549: ..................... ~ ................................... 2-51
TLC0820A: ....... : ........................................................ 2-61
TLC0831, TLC0832: .............. , ....................................... 2-71
TLC0834, TLC0838: ...................................................... 2-83
TLC876: ......................................................... , .......... 2-97
TLC876M; ................................ '........ ; ....................... 2-119
TLC1541 : : ............................................................... 2-123
TLC1542, TLC1543: ................ ,................. , .................. 2-133
TLC1549: ................................................................ 2-153
TLC1550, TLC1551: ......................................... ~ .......... 2-167
TLC2543 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. 2-175
T·LC5510: ................................................................ ·2-197
TLC5540 : . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-209
TLC5733A: .............................................................. 2-225
TLC320AD57: ........................................................... 2-247
TLC320AD58: ......................................... . . . . . . . . . . . . . . . . .. 2-267
TLV0831, TLV0832: ..................................................... 2-:-291
TLV0834, TLV0838: ..................................................... 2-303
TLV1543: ................................................................ 2-317
TLV1544, TLV1548: ..................................................... 2-335
TLV1548M: .............................................................. 2-367
TLV1549: ................................................................ 2-373
TLV1570: ................................................................ 2-387
TLV1572: ................................................................ 2-397
TLV2543: ................................................................ 2-409
TLV5510 : ................................................................ 2-429

2-2

ICL7135C, TLC7135C
41/2-DIGIT PRECISION
ANALOG-TO-DIGITAL CONVERTERS
MAY 1995

•
•
•
•
•
•
•
•
•
•
•

Zero Reading for O-V Input
Precision Null Detection With True Polarity
at Zero
1-pA Typical Input Current
True Differential Input
Multiplexed Binary-Coded-Decimal (BCD)
Output
Low Rollover Error: ±1 Count Max
Control Signals Allow Interfacing With
UARTs or Microprocessors
Autoranging Capability With Over-and
Under-Range Signals
TTL-Compatible Outputs
Direct Replacement for. Teledyne TSC7135,
IntersillCL7135, Maxim ICL7135, and
Siliconix Si7135
CMOS Technology

N PACKAGE
(TOP VIEW)
UNDER RANGE

VccREF

2

OVER RANGE

ANlG COMMON

3

STROBE

INTOUT

4
5
6

DGTlGND
POLARITY

Crel-

7

ClK

Crel+
IN-

8

AUTO ZERO
BUFF OUT

9

RUN/HOLD

BUSY

IN+

10

20
19

VCC+
D5

11
12

18
17

D3

B1

13
14

16
15

B8

B2

D1
D2
D4
B4

description
The ICL7135C and TLC7135C converters are manufactured with Texas Instruments highly efficient CMOS
technology. This 4 1/2-digit, dual-slope-integrating, analog-to-digital converter (DAC) is designed to provide
interfaces to both a microprocessor and a visual display. The digit-drive outputs D1 through D4 and multiplexed
binary-coded-decimal outputs B1, B2, B4, and B8 provide an interface for LED or LCD decoder/drivers as well
as microprocessors.
The ICL7135C and TLC7135C offer 50-ppm (one part in 20,000) resolution with a maximum linearity error of
one count. The zero error is less than 10 I1V and zero drift is less than 0.5I1V/oC. Source-impedance errors are
minimized by low input current (less than 10 pAl. Rollover error is limited to ±1 count.
The BUSY, STROBE, RUN/HOLD, OVER RANGE, and UNDER RANGE control signals support
microprocessor-based measurement systems. The control signals also can support remote data acquisition
systems with data transfer through universal asynchronous receiver transmitters (UARTs).
The ICL7135C and TLC7135C are characterized for operation from O°C to 70°C.
AVAILABLE OPTIONS
PACKAGE
TA

O°C to 70°C

PLASTIC DIP
(N)
ICL7135CN
TLC7135CN

Caution. These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive loam
during storage or handlilng to prevent electrostatic damage to the MOS gates.

~TEXAS

Copyright © 1995, Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-3

ICL7135C, TLC7135C
41/2-DIGIT PRECISION
ANALOG-TO-DIGITAL CONVERTERS
SlAS074A - DECEMBER 1986 -. REVISED MAY 1995 .

functional block diagram
DIGITAL SECTION
POLARITY
From Analog
Section

23

19

STROBE
BUSY
DGTlGND

}

Di9it
Dnve
Output

Counters
Multiplexer

25

RUN/HOLD
OVER RANGE
UNDER RANGE

01 (lSD)

02
18
03
17
04
12
05 (MSD)
Control
logic

22

ClK

20

Polarity
Flip-Flop

27
28

13

26
21
24

14
B2
15
B4
16
B8(MSB)

a. ,Ula, }

Binary
Coded .
Decimal
Output

ANALOG SECTION

Cref

r--

.

I

8

BUFF

Cref+_ ...!:ref-

L_O~6

5

AUTO
ZERO

-----,

4 INTOUT

AlZ

REF~r----'

Input
Hfgh

To
Digital

liNT
IN+

ANlG
COMMON

~~~~---.----+--*-~ o--t----t~~====j-----:-'

3

I
I
I
I

Section

Zli

AlZ

Input
low

IL I~
_ _ _ _ _ _ _ _ _ _ _ _ _ ._ _ _ _ _ _

9
IN- ~ cr------.---------~

~TEXAS

2-4

I
I
I
I

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

~

ICL7135C,TLC7135C
41/2-DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTERS
SLAS074A- DECEMBER 1986 - REVISED MAY 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage (Vcc+ with respect to Vcc-) .................................................. 15 V
Analog input voltage (IN- or IN+) ................................................... Vcc- to Vcc+
Reference voltage range ........................................................... Vcc- to Vcc+
Clock input voltage range ............................................................ 0 V to VCC+
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ..................... 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions
UNIT

MIN

NOM

MAX

Supply voltage, VCC+

4

5

6

v

Supply voltage, VCC-

-3

-5

-8

V

1

Reference voltage, Vref

V

2.8

High-level input voltage, ClK, RUN/HOLD, VIH

V

low-level input voltage, ClK, RUN/HOLD, Vil

0.8

Differential input voltage, VID

1.2

Maximum operating frequency, fclock (see Note 1)
Operating free-air temperature range, TA

V
V

VCC+-0.5

VCC-+l
2

MHz
70

0

°C

NOTE 1: Clock frequency range extends down to 0 Hz.

electrical characteristics, Vcc+
otherwise noted)

=5 V, Vcc- =5 V, Vref =1 V, fclock =120 kHz, TA =25°C (unless

PARAMETER
VOH

High-level output voltage

TEST CONDITIONS

MIN

TYP

MAX

I Dl-D5,Bl,B2,B4,B8

10=-1 mA

2.4

5

lather outputs

10=- lO IlA

4.9

5

UNIT
V

Val

low-level output voltage

10= 1.6mA

VON(PP)

Peak-to-peak output noise voltage (see Note 2)

VID = 0,

Full scale = 2 V

avo

Zero-reading temperature coefficient of output voltage

VID=O,

O°C ~ TA ~ 70°C

0.5

2

IIH

High-level input current

VI=5V,

O°C ~ TA ~ 70°C

0.1

10

!!A

III

low-level input current

VI=OV,

O°C ~ TA ~ 70°C

-0.02

-0.1

mA

II

Input leakage current, IN- and IN +

VID=O

ICC+

Positive supply current

fclock = 0

ICC-

Negative supply current

fclock =0

Cjld

Power dissipation capacitance

See Note 3

TA = 25°C

0.4
15

1

O°C ~TA ~ 70°C
TA = 25°C

1

O°C ~ TA ~ 70°C
TA= 25°C

10
250
2
3

-0.8

O°C ~ TA ~ 70°C

-2
-3

40

NOTES: 2. This IS the peak-to-peak value that IS not exceeded 95% of the time.
3. Factor-relating clock frequency to increase in supply current. At VCC+ = 5 V, ICC+ = ICC+(fclock = 0) + Cpd

V
IlV
IlV/o C

pA

mA

mA
pF

x 5 V x fclock

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-5

ICL7135C,TLC7135C
41/2·DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTERS
SLAS074A- DECEMBER 1986 - REVISED MAY 1995

operating characteristics, VCC+
otherwise noted)

=5 V, VCC- =5 V, Vref =1 V, fclock =120 kHz, TA =25°C (unless

PARAMETER

TEST CONDITIONS

TYP

MIN

(XFS

Full-scale temperature coefficient (see Note 4)

VID=2V,

EL

Li nearity error

-2V SVID S2 V

0.5

ED

Differential linearity error (see Note 5)

-2VSVID S2 V

0.01

EFS

± Full-scale symmetry error (rollover error) (see Note 6)

VID=±2V

Display reading with O-V input

VID=O,

ooe STAS 70°C

VID - Vref,

TA = 25°C

Display reading in ratiometric operation
NOTES:

MAX

ooe STAS 70°C

5

count
LSB

0.5

ooe S TA S 70°C

-0.0000

..

1

±O.OOOO

0.0000

0.9998

0.9999

1.0000

0.9995

0.9999

1.0005

4. This parameter IS measured with an external reference having a temperature coefficient of less than 0.01 ppm/oe.
5. The magnitude of the difference between the worst case step of adjacent counts and the ideal step.
6. Rollover error is the difference between the absolute values of the conversion for 2 V and -2 V.

timing diagrams
~ End of Conversion

BUSYt~~)__~________________________________

B1-B8 __~~D~S__L-~D~4~~~D~3__~~D~2__L-_D~1~~~D~S__L--

STROBEt

I

DS.J

.1

I..

D4

200 Counts

I
200 Counts

201 Counts

II..

200 Counts

~I

I..

I

D2

200 Counts

I..

~

I

D1

200 Counts

I..

~I

Delay between BUSY going low and the first STROBE pulse is dependent upon the analog input.

Figure 1

~TEXAS

2-6

L

.1

I

I

.1

D3

t

I..

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT
ppm/oe

count
Digital
Reading
Digital
Reading

ICL7135C, TLC7135C
41/2-DIGIT PRECISION
ANALOG-TO-DIGITAL CONVERTERS
SLAS074A- DECEMBER 1986 - REVISED MAY 1995

timing diagrams (continued)
Digital Scan
for OVER-RANGE

~

D5

~D4
~D3

~D2

1000 Counts

:--_.....n
I..
.1

n

D1

Figure 2

Integrator Output

AUTO ZERO
10,001 Counts

Signalint

fO,OOO

De-Integrate
20,001 Counts Max

Counts

I~

Full Measurement Cycle
40,002 Counts

~I

BUSY

OVER RANGE
When Applicable

UNDER RANGE ~
When Applicable "::~~'::"::",""",:...::...I'--_ _ _ _ _ _ _ _ _ _ _...I

Figure 3

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-7

ICL7135C, TLC7135C
4 1/2·DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTERS
SLAS074A- DECEMBER 1986 - REVISED MAY 1995

timing diagrams (continued)
STROBE

IIIII
r-AUTOZERO

Digit Scan
for OVER RANGE

n

Signal Integrate

-+/.-

DSt

L.,;",,;;_ _ _ _ _ _ _- \

-1l~D~4

'j';

_____~

'J';

----...r,

-DI,.;;;D.;..3

--11~D~2

I'J

________

__....In D1

~
'I';

';1;

Deintegratet

nI
n
I
I n
~
I
I
n-.
I n
I
I
n n..
I
I
I
I
n r
I

t First D5 of AUTO ZERO and deintegrate is one count longer.

Figure 4

PRINCIPLES OF OPERATION
A measurement cyde for the ICL7135C and TLC7135C consists of the following four phases.
1.

Auto-Zero Phase. The internallN+ and IN- inputs are disconnected from the terminals and internally
connected to ANLG COMMON. The reference capacitor is charged to the reference voltage. The
system is configured in a closed loop and the auto-zero capacitor is charged to compensate for offset
voltages in the buffer amplifier, integrator, and comparator. The auto-zero accuracy is limited only by the
system noise, and the overall offset, as referred to the input, is less than 1 ~ V.

a

2.

Signal Integrate Phase. The auto-zero loop is opened and the internal IN+ and IN- inputs are
connected to the external terminals. The differential voltage between these inputs is integrated for a
fixed period of time. When the input signal has no return with respect tothe converter power supply, INcan be tied to ANLG COMMON to establish the correct common-mode voltage. Upon completion of this
phase, the polarity of the input signal is recorded.

3.

deintegrate Phase. The reference is used to perform the deintegrate task. The internal IN- is internally
connected to ANLG COMMON and IN+ is connected across the previously charged reference
capacitor. The recorded polarity of the input signal ensures that the capacitor is connected with the
correct polarity so that the integrator output polarity returns to zero. The time required for the output to
return to zero is proportional to the amplitude of the input signal. The return time is displayed as a digital
reading and is determined by the equation 10,000 x (VIONref). The maximum or full-scale conversion
occurs when VIO is two times Vref.

4.

Zero Integrator Phase. The internal IN- is connected to ANLG COMMON. The system is configured in a
closed loop to cause the integrator output to return to zero. Typically, this phase requires 100 to 200
clock pulses. However, after an over-range conversion, 6200 pulses are required.

~TEXAS

INSTRUMENTS
2-8

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

ICL7135C, TLC7135C
4 1/2·DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTERS
SLAS074A- DECEMBER 1986- REVISED MAY 1995

PRINCIPLES OF OPERATION

description of analog circuits
input signal range
The common mode range of the input amplifier extends from 1 V above the negative supply to 1 V below the
positive supply. Within this range, the common-mode rejection ratio (CMRR) is typically 86 dB. Both differential
and common-mode voltages cause the integrator output to swing. Therefore, care must be exercised to ensure
that the integrator output does not become saturated.

analog common
Analog common (ANLG COMMON) is connected to the internal IN- during the auto-zero, deintegrate, and zero
integrator phases. When IN- is connected to a voltage that is different than analog common during the signal
integrate phase, the resulting common-mode voltage is rejected by the amplifier. However, in most applications,
IN- is set at a known fixed voltage (Le., power supply common for instance). In this application, analog common
should be tied to the same point, thus removing the common-mode voltage from the converter. Removing the
common-mode voltage in this manner slightly increases conversion accuracy.

reference
The reference voltage is positive with respect to analog common. The accuracy of the conversion result is
dependent upon the quality of the reference. Therefore, to obtain a high accuracy conversion, a high quality
reference should be used.

description of digital circuits
RUN/HOLD input
When RUN/HOLD is high or open, the device continuously performs measurement cycles every 40,002 clock
pulses. When this input is taken low, the integrated circuit continues to perform the ongoing measurement cycle
and then hold the conversion reading for as long as the terminal is held low. When the terminal is held low after
completion of a measurement cycle, a short positive pulse (greater than 300 ns) initiates a new measurement
cycle. When this positive pulse occurs before the completion of a measurement cycle, it will not be recognized.
The first STROBE pulse, which occurs 101 counts after the end of a measurement cycle, is an indication of the
completion of a me asurement cycle. Thus, the positive pulse could be used to trigger the start of a new
measurement after the first STROBE pulse.

:::::S'"'T""R""'O""BC=E input
Negative going pulses from this input transfer the BCD conversion data to external latches, UARTs, or
microprocessors. At the end of the measurement cycle, STROBE goes high and remains high for 201 counts.
The most significant digit (MSD) BCD bits are placed on the BCD terminals. After the first 101 counts, halfway
through the duration of output D1-D5 going high, the STROBE terminal goes low for 1/2 clock pulse width. The
placement of the STROBE pulse at the midpoint of the D5 high pulse allows the information to be latched into
an external device on either a low-level or an edge. Such placement of the STROBE pulse also ensures that
the BCD bits for the second MSD are not yet competing for the BCD lines and latching of the correct bits is
ensured. The above process is repeated for the second MSD and the D4 output. Similarly, the process is
repeated through the least significant digit (LSD). Subsequently, inputs D5 through D1 and the BCD lines
continue scanning without the inclusion of STROBE pulses. This subsequent continuous scanning causes the
conversion results to be continuously displayed. Such subsequent scanning does not occur when an over-range
condition occurs.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-9

ICL7135C,TLC7135C
41/2-0IGIT PRECISION
ANALOG..TO-DIGITAL CONVERTERS
SLAS074A- DEGEIlABER 1986- REVISED MAY 1995

PRINCIPLES OF OPERATION
BUSY output
The BUSY output goes high at the beginning of the signal integrate phase. BUSY remains high until the first
clock pulse after zero crossing or at the end of the measurement cycle when an over-range condition occurs.
It is possible to use the BUSY terminal to serially transmit the conversion result. Serial, transmission can be
accomplished by ANDing the BUSY and CLOCK signals and transmitting the ANDed output. The transmitted
output consists of 10,001 clock pulses, which occur during the signal integrate phase, and the number of clock
pulses that occur during the deintegrate phase. The conversion result can be obtained by subtracting 10,001
from the total number of clock pulses.
OVER-RANGE output
When an over-range condition occurs, this terminal goes high after the BUSY signal goes low at the end of the
measurement cycle. As previously noted, the BUSY signal remains high.until the end of the measurement cycle
when an over-range condition occurs. The OVER RANGE output goes hi,gh at the end of BUSY and goes low
at the beginning of the deintegrate phase in the next measurement cycle.
UNDER-RANGE output
At the end of the BUSY signal, this terminal goes high when the conversion result is less than or equal to 9%
(count of 1800) of the full-scale range. The UNDER RANGE output is brought low at the beginning of the signal
integrate phase of the next measurement cycle.
POLARITY output
The POLARITY output is high for a positive input signal and updates at the beginning of each deintegrate phase.
The polarity output is valid for all inputs including ±O and OVER RANGE signals.
digit-drive (D1, D2, D4 and D5) outputs
Each digit-drive output (D1 through D5) sequentially goes high for 200 clock pulses. This sequential process
is continuous unless an over-range occurs. When an over-range occurs, all of the digit-drive outputs are blanked
from the end of the strobe sequence until the beginning of the deintegrate phase (when the sequential digit-drive
activation begins again). The blanking activity during an over-range condition can cause the display to flash and
indicate the over-range condition.
BCD outputs
The BCD bits (B1, B2, B4 and B8) for a given digit are sequentially activated on these outputs. Simultaneously,
the appropriate digit-drive line for the given digit is activated.

system aspects
integrating resistor
The value of the integrating resistor (RINT) is determined by the full-scale input voltage and the output current
of the integrating amplifier. The integrating amplifier can supply 20 JJA of current with negligible nonlinearity. The
equation for determining the value of this resistor is:
R

_ Full Scale Voltage
INT liNT

Integrating amplifier current, liNT, from 5 to 40 JJA yields good results. However, the nominal and recommended
current is 20 ~A.

~TEXAS

2-10

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

•

ICL7135C, TLC7135C
41/2-DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTERS
SLAS074A - DECEMBER 1986 - REVISED MAY 1995

PRINCIPLES OF OPERATION

integrating capacitor
The product of the integrating resistor and capacitor should be selected to give the maximum voltage swing
without causing the integrating amplifier output to saturate and get too close to the power supply voltages. When
the amplifier output is within 0.3 V of either supply, saturation occurs. With ±5-V supplies and ANLG COMMON
connected to ground, the designer should design for a ±3.5-V to ±4-V integrating amplifier swing. A nominal
capacitor value is 0.47 1lF. The equation for determining the value of the integrating capacitor (CINT) is:
10,000 x Clock Period x liNT
Integrator Output Voltage Swing
Where:
liNT is nominally 20 !lA.
Capacitors with large tolerances and high dielectric absorption can induce conversion inaccuracies. A capacitor
that is too small could cause the integrating amplifier to saturate. High dielectric absorption causes the effective
capacitor value to be different during the signal integrate and deintegrate phases. Polypropylene capacitors
have very low dielectric absorption. Polystyrene and polycarbonate capacitors have higher dielectric
absorption, but also work well.

auto-zero and reference capacitor
Large capacitors tend to reduce noise in the system. Dielectric absorption is unimportant except during power
up or overload recovery. Typical values are 1 1lF.

reference voltage
For high-accuracy absolute measurements, a high quality reference should be used.

rollover resistor and diode
The ICL7135C and TLC7135C have a small rollover error; however, it can be corrected. The correction is to
connect the cathode of any silicon diode to INT OUT and the anode to a resistor. The other end of the resistor
is connected to ANLG COMMON or ground. For the recommended operating conditions, the resistor value is
100 kil. This value may be changed to correct any rollover error that has not been corrected. In many noncritical
applications the resistor and diode are not needed.

maximum clock frequency
For most dual-slope AID converters, the maximum conversion rate is limited by the frequency response of the
comparator. In this circuit, the comparator follows the integrator ramp with a 3-lls delay. Therefore, with a
160-kHz clock frequency (6-JlS period), half of the first reference integrate clock period is lost in delay. Hence,
the meter reading changes from 0 to 1 with a 50-IlV input, 1 to 2 with a 150-IlV input, 2 to 3 with a 250-IlV input,
etc. This transition at midpoint is desirable; however, when the clock frequency is increased appreciably above
160 kHz, the instrument flashes 1 on noise peaks even when the input is shorted. The above transition points
assume a 2-V input range is equivalent to 20,000 clock cycles.
When the input signal is always of one polarity, comparator delay need not be a limitation. Clock rates of 1 MHz
are possible since nonlinearity and noise do not increase substantially with frequency. For a fixed clock
frequency, the extra count or counts caused by comparator delay are a constant and can be subtracted out
digitally.

-!11 TEXAS

INSTRUMENTS
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2-11

ICL7135C, TLC7135C
4 1/2·DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTERS
SLAS074A -DECEMBER 1986 - REVISED MAY 1995

PRINCIPLES OF OPERATION
maximum clock frequency (continued)

For signals with both polarities, the clock frequency can be extended above 160 kHz without error by using a
low value resistor in series with the integrating capacitor. This resistor causes the integrator to jump slightly
towards the zero~crossing level at the beginning of the deintegrate phase, and thus compensates for the
comparator delay. This series resistor should be 10 Q to 50 Q. This approach allows clock frequencies up to
480 kHz.
minimum clock frequency

The minimum clock frequency limitations result from capacitor leakage from the auto-zero and reference
capacitors. Measurement cycles as high as 10 j.lS are not influenced by leakage error.
rejection of 50-Hz or 60-Hz pickup

To maximize the rejection of 50-Hz or 60-Hz pickup, the clock frequency should be chosen so that an integral
multiple of 50-Hz or 60-Hz periods occur during the signal integrate phase. To achieve rejection of these signals,
some clock frequencies that can be used are:
'
50 Hz: 250, 166.66, 125, 100 kHz, etc.
60 Hz: 300, 200, 150, 120, 100, 40, 33.33 kHz, etc.
zero-crossing flip-flop

This flip-flop interrogates the comparator's zero-crossing status. The interrogation is performed after the
previous clock cycle and the positive half of the ongoing clock cycle has occurred, so any comparator transients
that result from the clock pulses do not affect the detection of a zero-crossing. This procedure delays the
zero-crossing detection by one clock cycle. To eliminate,the inaccuracy, which is caused by this delay, the
co.unter is disabled for one clock cycle at the beginning of the deintegrate phase. Therefore, when the
zero-crossing is detected one clock cycle later than the zero-crossing actually occurs, the correct number of
counts is displayed.
noise

The peak-to-peak noise around zero is approximately 15 ~V (peak-to-peak value not exceeded 95% of the
time). Near full scale, this value increases to approximately 30 ~V. Much of the noise originates in the auto-zero
loop, and is proportional to the ratio of the input signal to the reference.
analog and digital grounds

For high"accuracy applications, ground loops must be avoided. Return currents from digital circuits must not
be sent to the analog ground line.

power supplies
The ICL7135C and TLC7135C are designed to work with ±5-V power supplies. However, 5-V operation is
possible when the input signal does not vary more than ± 1.5 V from midsupply.

~TEXAS

2-12

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL5501
6-81T ANALOG-TO-DIGITAL CONVERTER
1989 - REVISED APRIL 1990

•
•
•
•
•
•
•
•
•

N PACKAGE
(TOP VIEW)

6-Bit Resolution
Linearity Error ... ±0.8%
Maximum Conversion Rate ... 30 MHz Typ
Analog Input Voltage Range
Vee to Vee - 2 V
Analog Input Dynamic Range ... 1 V
TTL Digital 1/0 Level
Low Power Consumption
200mWTyp
5-V Single-Supply Operation
Interchangeable With Fujitsu MB40576

(lSB) DO

D1

02
03
D4
(MSB) 05

elK
GNO

GNO
OGTl Vee
ANlG Vee
REFB

ANlGINPUT
REFT

ANlG Vee
DGTl Vee

description
The TL5501 is a low-power ultra-high-speed video-band analog-to-digital converter that uses the Advanced
Low-Power Schottky (ALS) process. It utilizes the full-parallel comparison (flash method) for high-speed
conversion. It converts wide-band analog signals (such as a video signal) to a digital signal at a sampling rate
of dc to 30 MHz. Because of this high-speed capability, the TL5501 is suitable for digital video applications such
as digital TV, video processing with a computer, or radar signal processing.
The TL5501 is characterized for operation from O°C to 70°C.

functional block diagram
ClK - - - - - - - \
ANlG INPUT - - - - - ,
REFT

R

EN

05 (MSB)

04
R

03
63-10-6
Encoder

latch
and
Buffer

02

R

01
DO (lSB)

R

R
REFB

~~~~:fo:1: 8;'~=~~si~~r: ::I.::~~~i

standard warranty. Production proceaalng dolS not necessarily include

testing of all parameters.

~TEXAS

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright © 1990, Texas Instruments Incorporated

2-13

TL5501
6-81T ANALOG-TO-DiGITAL CONVERTER
SLAS026 - OCTOBER 1989 - REVISED APRIL 1990

equivalents of analog input circuit

ANLGVee

ANLG vee

- - - - - - - - - - - <....
D

ei

ANLG GND - - -.....-+----'

(see Note A)

NOTE A: Ci - nonlinear emitter-follower junction capacitance
fj - linear resistance model for input current transition caused by comparator switching.
VI < VrefB: Infinite; ClK high: infinite.
VrefB- voltage at REFS terminal
Ibias - constant input bias current
D - base-collector junction diode of emitter-follower transistor

equivalent of digital input circuit
r-----------------------------------------~
DGTLVee--~~---+------
"CI

0

(J

'5
a.
'5

••
•
100001

S
';;,
is

~

011111

I

VFT=VFS+ 33
1/2 LSB

~V

VZT
VZS

000000

~

~

ott':;

... ;

~

31

I

•

I 2••

II '/~ '/

~

a.

32

I

•• +)'2 LSB /.~ '/
• VZSII ~
000010
000001

62

~ ~ 61
vr •
'/1
~
V I.
••

~ '/

100000

0

63

.,t

s~e No;eA

I
I

0

~

••

VI - Analog Input Voltage - V
NOTE A: This curve is based on the assumption that VrefB and VrefT have been
adjusted so that the voltage at the transition from digital 0 to 1 (VZT) is
4.000 Vand the transition to full scale (VFT) is 4.992 V. 1 LSB = 16 mY.

Figure 1
END-POINT LINEARITY ERROR
111111

t
J:/ V1

111110
111101

11>
"CI

0

(J

••
•
100001

U~

~ 100000
0
S 011111

is

••
•
000010
000001
000000

62
61

1 •
•

I-li1o- EL 1

'5

;;,

63

J~

/

Jj ~'" EL3

AI-

EL3

"rio- EL31

~

,,'"

I

I
I
I

I
I

U~ ~~EL2

~ ~ ~EL1

I

•

33
32

a.

11>

iii
31

•
2

0

VI - Analog Input Voltage - V

Figure 2

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-17

TL5501
6-81T ANALOG·TO·DIGITAL CONVERTER
SLAS026 - OCTOBER 1989 - REVISED APRIL 1990.

PARAMETER MEASUREMENT INFORMATION
Measurement
Point

Vee

To
Digital
Output

Figure 3. Load Circuit

~TEXAS

2-18

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC5401, TLC541I
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
•
•

8-Bit Resolution AID Converter
Microprocessor Peripheral or Stand-Alone
Operation

•

On-Chip 12-Channel Analog Multiplexer

OW OR N PACKAGE
(TOP VIEW)
INPUTAO
INPUT A1
INPUT A2
INPUT A3
INPUT A4
INPUT A5
INPUT A6

• Built-in Self-Test Mode
• Software-Controllable Sample and Hold
• Total Unadjusted Error .•• ±0.5 LSB Max
• . TLC541 is Direct Replacement for Motorola
MC145040 and National Semiconductor
ADC0811. TLC540 is Capable of Higher
Speed
•

•

TLC540

TLC541

21ls
9!l5
75 x 103
12.5mW

3.6 !l5
171ls
40 x 103
12.5mW

9

VCC
SYSTEM CLOCK
1/0 CLOCK
ADDRESS INPUT
DATA OUT
CS
REF+
REFINPUT A10
INPUT AS

FNPACKAGE
(TOP VIEW)

CMOS Technology
PARAMETER

4
5
6
7

INPUT A8
GND

Pinout and Control Signals Compatible
with TLC1540Family of 10-Bit AID
Converters

Channel Acquisition Sample Time
Conversion Time (Max)
Samples per Second (Max)
Power Dissipation (Max)

1

description

4 3 2 1 20 1918 110 CLOCK
INPUT A3
The TLC540 and TLC541 are CMOS A/D
INPUT A4
17 ADDRESS INPUT
5
converters built around an 8-bit switched16 DATA OUT
INPUT A5
6
AID
capacitor
successive-approximation
INPUT A6
15
7
converters. They are designed for serial interface
INPUT A7
8
14 REF+
9 10 11 1213
to a microprocessor or peripheral via a 3-state
output with up to four control inputs, including
independent SYSTEM CLOCK, I/O CLOCK, chip
select (CS), and ADDRESS INPUT. A 4-MHz
system clock for the TLC540 and a 2.1-MHz
system clock for the TLC541 with a design that
includes simultaneous read/write operation allow high-speed data transfers and sample rates of up to
75, 180samples per second for the TLC540 and 40,000 samples per second for the TLC541. In addition to the
high-speed converter and versatile control logic, there is an on-chip 12-channel analog multiplexer that can be
used to sample anyone of 11 inputs or an internal self-test voltage, and a sample-and-hold that can operate
automatically or under microprocessor control. Detailed information on interfacing to most popular
microprocessors is readily available from the factory.
AVAILABLE OPTIONS
PACKAGE
TA

-40°C to 85°C
-55°C to 125°C

=~~~~~~:1~ s==~~sl~':f,:~: :lle::~=~

standard warranty. Production processing does not necessarily Include
testing of all parameters.

SO PLASTIC OIP
(OW)

PLASTICOIP
(N)

CHIP CARRIER
(FN)

TLC5411DW

TLC540lN
TLC541IN

TLC540lFN
TLC5411FN

-

TLC541MN

-

-

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright © 1995, Texas Instruments Incorporated

2-19

TLC5401, TLC541I
8"BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A - OCTOBER 1983 - REVISED MARCH 1995

The converters incorporated in the TLC540 and TLC541 ·feature differential high-impedance reference. inputs
that facilitate ratiometric conversion, scaling, and analog circuitry isolation from logic and supply noises~ A .
switched-capacitor design allows low-error (±O.5 LSB) conversion in 9 I1s for the TLC540 and 17 I1S for the
TLC541 over the full operating temperature range.
The TLC5401 and TLC541I are characterized for operation from -40°C to 85°C.Th.e TLC541 M is chiiracterized
for operation from -55°C to 125°(:.
.• .

functional block diagram
REF+

REF-

f3

f4
--!-

AO
A1 ~
A2 ~
A3
5
A4
6"
A5
A6
A7
A8
A9 -'-'A10

~

---4-

Analog
Inputs

7"

8
9
11
.n.

Sample
and
Hold

8-Blt
Analog-ta-Digital
Converter
(Switched·Capacltors)

-

12·Channel
Analog
Multiplexer

r.:......

~

I
I

Self-Test
Reference

I
I
I

ADDRESS 17
INPUT

I

Input
Address
Register

I
I

2

r

8-to-1 Data
Selector
and Driver

16

r---

DATA
OUT

Control Logic
and 110
Counters

,

±

110 18
CLOCK
CS

Output
Data
Register

4

4
Input
Multiplexer

8

15

SYSTEM 19
CLOCK

typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE

INPUT

INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 knTYP
'

AO-A10~

." I

INPUT

Cj =60pFTYP
(equivalent Input
capacitance)

~TEXAS

2-20

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS ·75265

AO-A10~

;h

5 MOTYP

TLC5401, TLC541I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A - OCTOBER 1983 - REVISED MARCH 1995

operating sequence
1/0
CLOCK

I

1

2

I

I

3

I

4

I

5

I

6

7

I

8

I

Sample
Cycle B

I

~

Don't

~

~

j4----- tconv

I+-

---..j

I
I

See Note A

r'--+-----------41I

I

2

I

Access
CycleC

I'
I

~

I

---I

4

I

5

I

6

I

7

I

8

: - SamPle--l
CycleC

LSB

Don't Care

HI-ZState~

OUT~A7
_

3

r

!+-- twH(CS) ---.j MSB
Don't Care
I,

LSB

I

DATA

I

" 'r-----1\
"
~~·~i----------------~

. CS" 'L-'
ADDRESS I
INPUT"'"'i-"

1

A7

~

Previous Conversion Data A _

MSB
(See Note B)

LSB

MSB

.4---MSB

Conversion Data B ---.~
LSB
MSB

NOTES: B. The conversion cycle, which requires 36 system clock periods, is initiated on the 8th falling edge of I/O CLOCK after CS goes low
for the channel whose address exists in memory at that time. If CS is kept low during conversion, I/O CLOCK must remain low
for at least 36 system clock cycles to allow conversion to be completed.
C. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining seven
bits (AS-AO) will be clocked out on the first seven I/O CLOCK falling edges.
D. To minimize errors caused by noise at CS, the internal circuitry waits for three system clock cycles (or less) after a chip select
falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in address data
until the minimum chip-select setup time has elapsed.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ........................................................... 6.5 V
Input voltage range, VI (any input) ............................................ -0.3 V to Vee +0.3 V
Output voltage range, Vo .................................................... -0.3 V to Vee +0.3 V
Peak input current range (any input) ....................................................... ±10 mA
Peak total input current (all inputs) ......................................................... ±30 mA
Operating free-air temperature range, TA: TLC5401, TLC541I .......................... -40°C to 85°C
Storage temperature range, T5tg .................................................... -65°C to 150°C
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package ............... 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to digital ground with REF- and GND wired together (unless otherwise noted).

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-21

TLC5401, .TLC541I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A - OCTOBER 1983 - REVISED MARCH 1995

recommended operating conditions
TLC540
MIN

Supply voltage, VCC

MAX

MIN

5

5.5

4.75

VCC VCC+O.l
2.5
0

2,5

4.75

Positive reference voltage, Vref+ (see Note 2)

2.5

..

-0.1

Negative reference voltage, Vref':" (see Note 2)
Differential reference voltage, Vref+ - Vref- (see Note 2)

1

Analog input voltage (see Note 2)

0

High-level control input voltage, VIH

2

TLC541

NOM

VCC

-0.1

VCC+0.2

1

VCC

0

Low-level control input voltage, VIL
Setup time, address bits at data input before 1/0 CLOCKi,
tsu(A)
Hold time, address bits after 1/0 CLOCKi, theA)
Setup time, CS low before clocking in first address bit, tsu(CS)
(see Note 3)

CS high during conversion, twH(CS)

Pulse duration, SYSTEM CLOCK frequency, fclock(SYS)
Pulse duration, SYSTEM CLOCK high, twH1SYS)

5

5.5

V

VCC VCC+O.l
0
2.5

V

VCC

V

VCC+0.2

V

VCC

V
V

0.8

V

200

400

0

0

ns

3

3

System
clock
cycles

36

36

System
clock
cycles

0

1/0 CLOCK frequency, fclock(I/O)

MAX

2
0.8

UNIT

NOM

fclock(l/O)
110

2.048
4

a
fclock(l/O)
210

ns

1.1

MHz

2.1

MHz
MHz

Pulse duration, SYSTEM CLOCK low, twL(SYS)

100

190

MHz

Pulse duration, I/O clock high, twHlIIO\

200

404

ns

Pulse duration, 1/0 clock low, twL(I/O

200

404

System
Clock transition timll
(see Note 4)
I/O
Operating free-air temperature, TA

30

fclocklSYS\ :;; 1048 kHz
fclock(SYS) > 1048 kHz
fclocklllO\ :;; 525 kHz
fclock(llO) > 525 kHz
TLC5401, TLC5411

20

20

100

100

40
-40

ns
30

85

ns

40
-40

85

°C

NOTES: 2. Analog input voltages greater than that applied to REF + convert as all "1"s (11111111), while input voltages less than that applied
to REF- convert as all "O"s (00000000). For proper operation, REF+ voltage must be at least 1 V higher than REF- voltage. Also,
the total unadjusted error may increase as this differential reference voltage falls below 4.75 V.
3. To minimize errors caused by noise at CS, the internal circuitry waits for three SYSTEM CLOCK cycles (or less) after a chip select
falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock in an address until
the minimum chip select setup time has elapsed.
4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2 fJ.S for remote data acquisition
applications where the sensor and the AID converter are placed several feet away from the controlling microprocessor.

~ThXAS
2-22

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5401, TLC541I
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A - OCTOBER 1983 - REVISED MARCH 1995

electrical characteristics over recommended operating temperature range, Vee = Vref+ = 4.75 V to
5.5 V, fclock(I/O) 2.048 MHz for TLC540 or fclock(I/O) 1.1 MHz for TLC541 (unless otnerwise noted)

=

=

PARAMETER

TEST CONDITIONS

VOH

High-level output voltage. DATA OUT

Vee = 4.75 V.

IOH = 360 ~A

VOL

Low-level output voltage

Vee=4.75V.

IOL= 1.6 rnA

IOZ

Off-state (high-impedance state) output current

IIH

High-level input current

VI =Vee

IlL

Low-level input current

VI=O

ICC

Operating supply current

Selected channel leakage current

ICC + Iref
ei

Supply and reference current
Input capacitance

II Analog inputs

MIN

TYPt

MAX

2.4

UNIT
V

0.4

Vo = Vee.

esatVee

10

VO=O.

es at Vee

-10

V

!1A

0.005

2.5

-0.005

-2.5

!1A

eSatOV

1.2

2.5

mA

Selected channel at Vee.
Unselected channel at 0 V

0.4

1

-0.4

-1

Selected channel at 0 V.
Unselected channel at Vee
Vref+ = Vee.

eSatOV

Control inputs

IlA

!1A
1.3

3

7

55

5

15

mA
pF

t All typical values are at TA = 25°C.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-23

TLC5401, TLC541I
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A - OCTOBER 1983 - REVISED MARCH 1995

operating characteristics over recommended operatingfree·air temperature range,
Vee Vref+ - 4.75 V to 5.5 V, f810CkWO}= 2.048 MHz for TLC540 or 1.1 MHz for TLC541,
fclock(SYS) 4 MHz for TLC54 or 2.1 MHz for TLC541

=

=

PARAMETER

TLC540

TEST CONDITIONS

MIN

TLC541

MAX

MIN

MAX

UNIT

EL

Linearity error

See Note 5·

±0.5

±0.5

LSB

EZS

Zero-scale error

See Notes 2 and 6

±0.5

±0.5

LSB

EFS

Full-scale error

See Notes 2 and 6

±0.5

±0:5

LSB

Total unadjusted error

See Note 7

±0.5

±0.5

LSB

Self-test output code

Input All address = 1011,
(see NoteS)

Conversion time

See Operating Sequence

9

17

Total access and conversion time

See Operating Sequence

13.3

25

!conv

ta

Channel aoquisition time (sample cycle)

tv

Time output data remains valid after
1I0CLOCK.j,

ld

Delay time, I/O CLOCK.j, to data output
valid

ten

Output enable time

tdis

Output disable time

tr(bus}
tf{bus)
NOTES:

01111101
(125)

See Operating Sequence

01111101
(125)

4

10

10000011
(131)

4

10

~
~

I/O
clock
cylces
ns

300

400

ns

150

150

ns

150

150

ns

Data bus rise time

300

300

ns

Data bus fall time

300

300

ns

See Parameter
Measurement
Information

2. Analog input voltages greater than that applied to REF+ convert to all "1"s (11111111) while input voltages less than that applied to
REF- convert to all "O"s (00000000). For proper operation, REF+ voltage must be at least 1 V higher than REF- voltage. Also, the
total unadjusted error l11ay increase as this differential reference voltage falls below 4.75 V.
5. Linearity error is the maximum deviation from the best straight line through the ND transfer cnaracteristics.
6. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
7. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic.

~TEXAS

INSTRUMENTS
2-24

10000011
(131)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5401, TLC541I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A - OCTOBER 1983 - REVISED MARCH 1995

PARAMETER MEASUREMENT INFORMATION

J

VCC

1.4 V

kQ

OUlpul
Under Tesl

CL
(see Note A)

Tesl
Point

Output
Under Test

n

CL
(see Nole A)

T

I

Test
Point

CL
(see Nole A)

3 kQ

I

See Note B
LOAD CIRCUIT FOR
tpZL AND tpLZ

LOAD CIRCUIT FOR
tpZH ~ND tpHZ

,

) ~kQ

OUlpul
Under Test

See Nole B

LOAD CIRCUIT FOR
td. I ... AND If

CS

Test
Point

...."",._ _ _ _ _ _ _ _ _ _ _

...I4~o~

______

VCC
OV

1

SYSTEM
CLOCK
tPZL ~
OUlput Waveform 1
(see Note C)

~

I.--tPLZ
----VCC

----------11-""'1
See Nole B

1

!
~----OV
----+i:'--_ _---III+\50%

tpZH

tpHZ

I~

Oulput Waveform 2
(see Note C) _ _ _ _ _ _ _ _ _ _ _ _-J.

V

-\ 90%---- VOH

1 50%

,

OV

VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES

1/0 CLOCK

\------JX========

ou~

O.BV

1

14-

td

-.I

DATAOUT_ _ _ _ _ _ _

1 1

2.4 V

O.BV

Ir~

~

VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES

VOLTAGE WAVEFORMS FOR DELAY TIME
NOTES: A. CL = 50 pF for TLC540 and 100 pF for TLC541.
B. ten = tpZH or tPZL, tdis = tPHZ or tpLZ·
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-25

TLC5401, TLC541I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A - OCTOBER 1983 - REVISED MARCH 1995

APPLICATION INFORMATION

simplified analog input analysis
Using the equivalent circuit in Figure 1, the time required to charge the analog input capacitance from 0 to Vs
within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by
(1 )

where
Rt = Rs + rj
The final voltage to 1/2 LSB is given by
Vc (1/2 LSB) '" Vs - (Vs/512)

(2)

Equating equation 1 to equation 2 and solving for time tc gives
Vs - (VS/512)

= Vs ( 1_e-tc/RtCi)

(3)

and
tc (1/2 LSB) = Rt x Cj x In(512)

(4)

Therefore, with the values given the time for the analog input signal to settle is

(5)

tc (1/2 LSB) = (Rs + 1 kil) x 60 pF x In(512)
This time must be less than the converter sample time shown in the timing diagrams.

1

Driving Sourcet ..
Rs

I
I
I

VI

• TLC54011
r/

VS~VC
I 1knMAX
:

I

I

C/
50pFMAX

=
=
=

VI Input Voltage at INPUT AO-A10
Vs = External Driving Source Voltage
Rs Source Res/stance
rl = Input Resistance
Ci Equivalent Input Capacitance

t Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.

Figure 1. Equivalent Input Circuit Including the Driving Source

~TEXAS

2-26

INSTRUMENTS
POST OFFICE BOX 655303 • ,DALLAS, TEXAS 75265

TLC5401, TLC541I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A - OCTOBER 1983 - REVISED MARCH 1995

PRINCIPLES OF OPERATION
The TLC540 and TLC541 are each complete data acquisition systems on.a single chip. They include such functions
as analog multiplexer, sample and hold, a-bit AID converter, data and control registers, and control logic. For flexibility
and access speed, there are four control inputs [two clocks, chip select (CS), and address]. These control inputs and
a TTL-compatible 3-state output are intended for serial communications with a microprocessor or microcomputer.
With judicious interface timing, with TLC540 a conversion can be completed in 9 ~s, while complete
input-conversion-output cycles can be repeated every 13 ~s. With TLC541 a conversion can be completed in 17 ~s,
whiie complete input-conversion-output cycles are repeated every 25 ~s. Furthermore, this fast conversion can be
executed on any of 11 inputs or its built-in self-test and in any order desired by the controlling processor.
The system and I/O clocks are normally used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for the device.
Once a clock signal within the specification range is applied to SYSTEM CLOCK, the control hardware and software
need only be concerned with addressing the desired analog channel, reading the previous conversion result, and
starting the conversion by using I/O CLOCK. SYSTEM CLOCK will drive the conversion crunching circuitry so that
the control hardware and software need not be concerned with this task.
When CS is high, DATA OUT is in a 3-state condition and ADDRESS INPUT and I/O CLOCK are disabled. This feature
allows each of these terminals, with the exception of CS, to share a control logic point with their counterpart terminals
on additional AID devices when additional TLC540/541 devices are used. In this way, the above feature serves to
minimize the required control logic terminals when using multiple AID devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain
the conversion result. A normal control sequence is:
1. CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges
and then a falling edge of SYSTEM CLOCK after a low CS transition, before the low transition is recognized.
This technique is used to protect the device against noise when the device is used in a noisy environment.
The MSB of the previous conversion result automatically appears on DATA OUT.
2. A new positive-logic multiplexer address is shifted in on the first four rising edges of I/O CLOCK. The MSB
of the address is shifted in first. The negative edges of these four I/O clock pulses shift out the second, third,
fourth, and fifth most significant bits of the previous conversion result. The on-chip sample and hold begins
sampling the newly addressed analog input after the fourth falling edge. The sampling operation basically
involves the charging of internal capacitors to the level of the analog input voltage.
3. Three clock cycles are then applied to I/O CLOCK and the sixth, seventh, and eighth conversion bits are
shifted out on the negative edges of these clock cycles.
4. The final eighth clock cycle is applied to I/O CLOCK. The falling edge of this clock cycle completes the
analog sampling process and initiates the hold function. Conversion is then performed durin.Q the next 36
system clock cycles. After this final I/O clock cycle, CS must go high or the I/O CLOCK must remain low
for at least 36 system clock cycles to allow for the conversion function.
CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple
conversion, special care must be exercised to prevent noise glitches on I/O CLOCK. If glitches occur on I/O CLOCK,
the I/O sequence between the microprocessor/controller and the device loses synchronization. Also, if CS is taken
high, it must remain high until the end of the conversion. Otherwise, a valid falling edge of CS causes a reset condition,
which aborts the conversion in progress.
A new conversion can be started and the ongoing conversion simultaneously aborted by performing steps 1 through
4 before the 36 system clock cycles occur. Such action yields the conversion result of the previous conversion and
not the ongoing conversion.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265

2-27

TLC5401, TLC541I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065A- OCTOBER 1983 - REVISED MARCH 1995

PRINCIPLES OF OPERATION
It is possible to connect SYSTEM CLOCK and I/O clock together in special situations in which controlling circuitry
points must be minimized. In this case, the following-special points must be considered in addition to the requirements
of the normal control sequence previously described.
1. The first two clocks are required for this device to recognize CS is at a valid low level when the common clock
signal is used as an I/O CLOCK-When CS is recognized by the device to be at a high level, the common clock
signal is used for the conversion clock also.
2: A low CS must be recognized before the I/O CLOCK can shift in an analog channel address. The device
recognizes a CS transition when the SYSTEM CLOCK terminal receives two positive edges and then a
negative edge. For this reason, after a CS negative edge, the first two clock cycles do not shift in the address.
Also, upon shifting in the address, CS must be raised after the eighth valid (10 total) I/O CLOCK. Otherwise,
additional common clock cycles are recogniied as I/O CLOCKS and will shift in an erroneous address.
For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.
This device accommodates these applications. Although the on-Chip sample and hold begins sampling upon the
negative edge of the fourth valid I/O clock cycle, the hold function is not initiated until the negative edge of the eight~
valid I/O clock cycle. Thus, the control circuitry can leave the I/O clock signal in its high state during the eighth valid
1/0 clock cycle until the moment at which the analog signal must be converted. The TLC540ITLC541 continues
sampling the analog input until the eighth falling edge of the 1/0 clock. The control circuitry or software then
immediately lowers the 1/0 clock signal and holds the analog signal at the desired point in time and start conversion.
Detailed information on interfacing to most popular microprocessors is readily available from the factory.

~TEXAS .
2-28

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC542C, TLC5421
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075A - FEBRUARY 1989 - REVISED

•
•
•
•
•
•
•

B-Bit Resolution AID Converter
Microprocessor Peripheral or Stand-Alone
Operation
On-Chip 12-Channel Analog Multiplexer
Built-in Self-Test Mode
Software-Controllable Sample and Hold
Total Unadjusted Error. .. ±O.5 LSB Max
Direct Replacement for Motorola
MC145041

•
•
•

On-Board System Clock
End-of-Conversion (EOC) Output
Pinout and Control Signals Compatible
With the TLC1542/3 10-Bit AID Converters

•

CMOS Technology

OW OR N PACKAGE
(TOP VIEW)

INPUT AO
INPUT A1
INPUT A2
INPUT A3
INPUT A4
INPUT A5
INPUT A6
INPUT A7
INPUT AS
GND

VCC

3
4
5
6

9
11

EOC
.1/0 CLOCK
ADDRESS INPUT
DATA OUT
CS
REF+
REFINPUTA10
INPUT A9

FN PACKAGE
(TOP VIEW)

PARAMETER

VALUE

Channel Acquisition/Sample lime

161ls

Conversion Time (Max)

20llS
25 x 103

Samples per Second (Max)
Power Dissipation (Max)

10mW

INPUT A3
INPUT A4
INPUT A5
INPUT AS
INPUTA7

description

43

2

1 201918

5
6
7
8

17
16

I/O CLOCK
ADDRESS INPU
DATA OUT
CS
REF+

The TLC542 is a CMOS converter built around an
15
8-bit switched-capacitor successive-approximation
14
9 10 11 1.213
analog-to-digital converter. The device is designed
for serial interface to a microprocessor or peripheral
via a 3-state output with three inputs [including I/O
CLOCK, CS (chip select), and ADDRESS INPUT].
The TLC542 allows high-speed data transfers and
sample rates of up to 40,000 samples per second.
In addition to the high-speed converter and
versatile control logic, an on-chip 12-channel
analog multiplexer can sample anyone of 11 inputs or an internal "self-test" VOltage, and the sample and hold
is started under microprocessor control. At the end of conversion, the end-of-conversion (EOC) output pin goes
high to indicate that conversion is complete. Detailed information on interfacing to most popular
microprocessors is readily available from the factory.
AVAILABLE OPTIONS
PACKAGE
TA

CHIP CARRIER
(FN)

PLASTlC DIP
(N)

SMALL OUTLINE
(OW)

O°C to 70°C

-

TLC542CN

TLC542CDW

-40°C to 85°C

TLC5421FN

TLC5421N

TLC5421DW

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

Copyright © 1995. Texas Instruments Incorporated

2-29

TlC542C, TlC5421
8·BIT ANAlOG·TO·DIGITAl CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075A - FEBRUARY 1989 - REVISED MARCH 1995

description (continued)
The converter incorporated in the TLC542 features differential high-impedance reference inputs that facilitate
ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noises. A switchedcapacitor design allows low-error (±0.5 LSB) conversion in 20 IlS over the full operating temperature range.
The TLC542C is characterized for operation from O°C to 70°C and the TLC5421 is characterized for operation
from -40°C to 85°C.

functional block diagram

--.-.-

-

-Analog
Inputs

Sample and
Hold

r---

REF+

REF-

I

I

8-Bit
Analog-to-Dlgltal
Converter
(Switched-Capacitors)
8

12-Channel
Analog
Multiplexer

-

Output
Data
Register

-

~

Input Address
Register

8

~

8-to-1 Data
Selector and I-- DATA
OUT
Driver
~

4

~

Self-Test
Reference

CS

EOC

I

4

I

ADDRESS
INPUT

110 CLOCK

Input
Multiplexer

Control Logic
and 110
Counters

2

tI

±

.

•

typical equivalent inputs
. INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE

"INPUT

INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 knTYP

AO-A10~

I

INPUT

CI=60 pFTYP
(equivalent input
capacitance)

~TEXAS

2-30

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

AO-A10~.
.

~ 5MQTYP

TLC542C, TLC5421
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075A - FEBRUARY 1989 - REVISED MARCH 1995

operating sequence
1112131415161718

110
CLOCK

--I

I+-

I I

--I

tsu(A)"'1
~;:~
I I (see Note A)
Isu(cs) ~I

I
-+1

cs1h~\~iri--------------~i~
1

1
I ,
ADDRESS
~
INPUT
1

II

IMSB

1

LSB

OUT

I

:+-- ----1
tacq

1
I
I
14--- 12 Internal System Clocks :512 ~9

)r-tl~~i--------------~rI

HI-Z State

A6 AS

i+" ~;~~s~ -+II

I

1

I

1

1

M~B

1
1
LSB
Don't Care 1
I I
~
Don't Care
}------;---~Ir--I--+I~ C3 C2 Cl CO - - - - - - - 1 1

I

DATA {

I I

1

:~ tacq ---+---+i+- toonv ~

A4 A3 A2

1

AI
1

See Note B

Previous Conversion Data A ~
I
MSB
LSB.I
1
I (see Note B)
I, _1cI(EOC-DATA)-t'1
~
td(1/O-EOC) ---+i 14-

i4--

EOC

I"

I.

tcycle

~~r---------'L~

NOTES: D. To minimize errors caused by noise at the chip select input, the internal circuitry waits for two rising edges and one falling edge
of the internal system clock after CSJ. before responding to control input signals. The CS setup time is given by the tsu(CS)
specifications. Therefore, no attempt should be made to clock-in an address until the minimum chip select setup time has elapsed.
E. The output is 3-stated on CS going high or on the negative edge of the eighth
clock.

va

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6.5 V
Input voltage range (any input) .............................................. -0.3 V to Vee + 0.3 V
Output voltage range ....................................................... -0.3 V to Vee+ 0.3 V
Peak input current range (any input) ...................................................... ±20 mA
'Peak total input current (all inputs) ........................................................ ±30 mA
Operating free-air temperature range: TLC542C ........................................ O°C to 70°C
TLC5421 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
Storage temperature range ....................................................... -65°C to 150°C
Case temperature for 10 seconds: FN package ........................................... " 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package .............. 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to digital ground with REF- and GND wired together (unless otherwise noted).

-!II
TEXAS
INSTRUMENTS.
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-31

TLC542C, TLC5421
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075A -'- FEBRUARY 1989 - REVISED MARCH 1995

recommended operating conditions, Vee

=4.75 to 5.5 V
MIN

NOM

MAX

4.75

5

5.5

Positive reference voltage, Vref+.(see Note 2)

Vref-

VCC

Negative reference voltage, Vref- (see Note 2)

-0.1

0
VCC

Supply voltage, VCC

Differential reference voltage, Vref+ - Vref- (see Noie 2)

1

Analog input voltage (see Note 3)

0

High-level control input voltage, V,H .

2

UNIT
V

VCC+O.l

V

VCC + 0.2

V

VCC

V
V

0.8

Low-level control input voltage, V,L
Setup time, address bits at data input before 1/0 CLOCK1', tsu(A)

V

Vref+

V

400.

ns

Hold time, address bits after 1/0 CLOCK1', thlA)

0

Hold time; CS low after 8th 1/0 CLOCK1', th(CS)

de

ns

3.8

itS

Setup time, CS low before clocking in first address bit, tsulCS) (see Note 4)
Input/output clock frequency, fclock(l!O)

0

Input/output clock high, twH(l/O)

404

Input/output clock low, twL(I!O)

404

1/0 CLOCK transition time, tt (see Note 3)
Operating free-air temperature, TA
NOTES:

ns

1.1

MHz
ns
ns

fclock(I/O)!> 525'kHz

100

fclock(l!O) > 525 kHz

40
0

70

,...40

85

TLC542C
TLC5421

ns

°c

2. Analog Input voltages greater than that applied to REF+ convert as all ones (11111111), while Input vOltages less than that applied
to REF- convert as all zeros (00000000). For proper operaiion,' REF+ must be at least 1 V higher than REF-. Also, the total
unadjusted error may increase as this differential reference voltage falls below 4.75 V
3. This is the time required for the clock input signal to fall from V,H min to V,L max or to rise from V,L max to V,H min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2 I!S for remote data acquisition
applications where the sensor and the AID converter are placed several feet away from the controlling microprocessor.
4. To minimize errors caused by noise at the chip select input, the internal circuitry waits for two rising edges and one falling edge of
the internal system clock after CS .\, before responding tei control input signals. The CS setup time is given by the tsu(CS)
specifications. Therefore, no attempt should be made to clock-in address data until the minimum chip select setup time has elapsed.

electrical characteristics over recommended operating temperature range, Vee = Vref+ = 4.75 V to
5.5 V, fclock(IIO) 1.1 MHz (unless otherwise noted)

=

PARAMETER

t

TEST CONDITIONS

MIN

I!A

VOH

High-level output voltage (DATA OUT)

Vce=4.75V,

10H = -360

VOL

Low-level output voltage

Vce =4.75 V,

'OL = 1.6 rnA

Off-state (high-impedance state)
output current

VO=VCC,

CS atVcc

VO=O,

CS atVce

IIH

High-level input current

V, = VCC

I,L

Low-level input current

V, = 0

ICC

Operating supply current

CSatOV

Selected channel leakage current

Selected at VCC,
Unselected channel at 0 V

'ref

Maximum static analog reference current into
REF+

Vref+= VCC,

Ci

1Analog inputs
Input capacitance 1

10
-10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I!A

2

-0.005

-2.5

I!A
I!A

2

rnA

0.4
-0.4
10

Vref_=GND

~TEXAS

V

0.005

1- 40°C to 85°C

INSTRUMENTS

.mIT
V

1.2

Control inputs

MAX
0.4

I ooe to 70 °e

All typical values are at TA = 25°C.

2-32

TYPt

2.4

7

55

5

15

itA

I!A
pF

TLC542C, TLC5421
8-BIT ANALOG-TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075A - FEBRUARY 1989 - REVISED MARCH 1995

operating characteristics over recommended operating free-air temperature range,
Vee = Vref+ = 4.75 to 5.5 V, fclock(I/O) =1 MHZ
PARAMETER

TEST CONDITIONS

MIN

TYPt

MAX

UNIT

±O.5

lSB

El

Linearity error (see Note 5)

EZS

Zero-scale error (see Note 6)

See Note 2

±O.S

lSB

EFS

Full-scale error (see Note 6)

See Note 2

±0.5

lSB

±O.S

lSB

Total unadjusted error (see Note 7)

= 1011,

Self-test output code

Input All address
See Note 8

01111101
(126)

!conv

Conversion time

See operating sequence

20

~s

!cycle

Total access and conversion cycle time

See operating sequence

40

~

tacq

Channel acquisition time (sample cycle)

See operating sequence

16

~

tv

lime ouput data remains valid after 1/0 ClK.!.

See Figure 5

!d(lO-DATA)

Delay time, 1/0 ClK.!. to data output valid

See Figure S

400

ns

!dIlO-EOC)

Delay time, 8th I/O ClK.!. to EOC.!.

See Figure 6

SOO

ns

!d(EOC-DATA)

Delay time, EOCt to data out (MSB)

See Figure 7

400

ns

tpZH, tpZl

Delay time, CS.!. to data out (MSB)

See Figure 2

3.4

~s

128

10000011
(130)

10

ns

tPHZ, tplZ

Delay time, cst to data out (MSB)

See Figure 2

150

ns

tr(EOC)

Rise time

See Figure 7

100

ns

tf(EOC)

Fall time

See Figure 6

100

ns

tr(bus)

Data bus rise time

See Figure 5

300

ns

tf(bull)

Data bus fall time

See Figure 5

300

ns

t All typical values are at TA = 25°C
NOTES: 2. Analog input voltages greater than that applied to REF+ convert to all ones (11111111), while input voltages less than that applied
to REF- convert to aU zeros (00000000). For proper operation, REF+ must be at least 1 V higher than REF-. Also, the total
unadjusted error may increase as this differential reference voltage falls below 4.75 V.
5. Linearity error is the maximum deviation from the best straight line through the AID transfer characteristics.
6. Zero-scale Error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
7. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic. The All analog input signal is internally generated and
is used for test purposes.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-33

TLC542C, TLC5421
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075A - FEBRUARY 1989 - REVISED MARCH 1995

PARAMETER MEASUREMENT INFORMATION

J

Output
Under Test

j

VC: kQ

1 4V
. 3kQ

Output
Test
u n d e r T e s t n Point

Test
Point

CL
(see Note A)

CLI
(see Note A) _

LOAD CIRCUIT FOR
!d, t ... AND tf

T

Output
Under Test

CL
(see Note A)

3kQ

LOAD CIRCUIT FOR
tPZH AND tPHZ

Test
Point

T

LOAD CIRCUIT FOR
tPZL AND tpLZ

NOTE A: CL = 50 pF

Figure 1. Load Circuits

!.- Address -.1
CS

1-

~~~
____J2VT:
\-. 0.8 V
/!

tpZH,tpZL

~
I~
~i

~
~

An

,+
,

J,-

Figure 3. Address Timing

Figure 2. CS to Data Output Timing

I/O CLOCK

\o.av

',c)

~I,.

I..
1

2Vr-\.

----./

2r

r;;\. i

1

~I

th(CS)

y~ Ci~~k U ! . L -

Figure 4. Figure 4. CS to I/O CLOCK Timing

~TEXAS

2-34

X=

lit
tsu(A) ~ h(A)

I/O _ _ _ _ _ _-J2V
CLOCK
/'

~

tsu(CS)

1

=X~.~V

tPHZ, tpLZ

2.4V(
)90%
DATA OUT - - - - ( .
•
0.4 V _ _ _ _ _
10%

CS

Valid

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC542C, TLC5421
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075A - FEBRUARY 1989 - REVISED MARCH 1995

PARAMETER MEASUREMENT INFORMATION
t'(I/O)

---+I 14--1

1/0 CLOCK

2V

1

0.8 V

~,

_ _...-T

,4
td(I/O-DATA)

,

0.8 V

fclock(I/O) - - - - . ,

~

tv~

1

J.

2.4 V{
2.4 V
DATA OUT ____0~.4~V~)\~._~0.~4~V_____________

,,

~ tr(bus). tf(bus)

---.!

Figure 5. Data Output Timing

~h

1/0 CLOCK
/
--.../

Clock

\

~...;O.;;..8..;.V___________
1

td(I/O-EOC) -+II141----~.1

1

2.4V

EOC

tf(EOC)

"\i

!\ 0.4V
1,----

---+I J+-

Figure 6. EOC Timing

---+I,
EOC

*,

tr(EOC)

, ,~-------------------if
2.4V

,

~!
~ td(EOC-DATA) ~{
DATA OUT

_______--<. Je-2:-.4":""!V~------!"-0:::;.4;:;.,.V'--_______
,
J4-

Valid MSB

--+

Figure 7. Data Output to EOC Timing

~TEXAS

. INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-35

TLC542C,TLC5421
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075A - FEBRUARY 1989 - REVISED. MARCH 1995'

APPLICATION INFORMATION

simplified analog input analysis
Using the equivalent circuit in Figure 8, the time required to charge the analog input capacitance from 0 to Vs .
within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by
Vc

= Vs

(1-e -te/RtCi)

(1 )

where
Rt=Rs+ri
The final voltage to 1/2 LSB is given by
Vc (1/2 LSB) = Vs - (Vs/512)

(2)

Equating equation 1 to equation 2 and solving for time Ie gives
Vs-(Vs/512) = Vs (1-e -teIRtC')
I

(3)

Ie (1/2 LSB) = Rt x Ci x In(512)

(4)

and
Therefore, with the values given the time for the analog input signal to settle is
te (1/2 LSB) = (Rs + 1 kn) x 60 pF x In(512)

(5)

This time must be less than the converter sample time shown in the timing diagrams.
Driving Sourcet 4
Rs

I
I
I
I

VI

• TLC542
ri

VS~VC
I 1 knMAX
I
I
I

I

Ci
50pFMAX

=
=

VI Input Voltage at INPUT AO-A10
Vs = External Driving Source Voltage
Rs Source Resistance
rl = Input Resistance
CI = Input CapacitanCe

t Driving source requirements:
• Noise and distortion for the source must be equivalent 10 the
resolution of the converter.
• Rs must be real at the input frequency.

Figure 8. Equivalent Input Circuit Including the Driving Source

~TEXAS

2-36

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC542C,TLC5421'
a-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075A - FEBRUARY 1989 - REVISED MARCH 1995

PRINCIPLES OF OPERATION
The TLC542 is a complete data acquisition system on a single chip. The device includes such functions as analog
multiplexer, sample and hold, 8-bit NO converter, data and control registers, and control logic. Three control inputs
(I/O CLOCK, CS (chip select), and ADDRESS INPUT) are included for flexibility and access speed. These control
inputs and a TIL-compatible 3-state output are intended for serial communications with a microprocessor or
microcomputer. With judicious interface timing, the TLC542 can complete a conversion in 20 Ils, while complete
input-conversion-output cycles canbe repeated every 40 j.1S. Furthermore, this fast conversion can be executed on
any of 11 inputs or its built-in self-test and in any order desired by the controlling processor.
When CS is high, the DATA OUT terminal is in a 3-state condition, and the ADDRESS INPUT and I/O CLOCK
terminals are disabled. When additional TLC542 devices are used, this feature allows each of these terminals, with
the exception of the CS terminal, to share a control logic point with their counterpart terminals on additional NO
devices. Thus, this feature minimizes the control logic terminals required when using multiple A/D devices.
The control sequence is designed to minimize the time and effort required to initiate conversion and obtain the
conversion result. A normal control sequence is as follows:
1. CS is brought low. To minimize errors caused by noise at the CS (nput, the internal circuitry waits for two
rising edges and then a falling edge of the internal system clock before recognizing the low CS transition.
The MSB of the result of the previous conversion automatically appears Dn the DATA OUT terminal.
2. On the first four rising edges of the I/O CLOCK, a new positive-logic multiplexer address is shifted in, with
the MSB of this address shifted first. The negative edges of these four I/O CLOCK pulses shift out the
second, third, fourth, and fifth most significant bits of the result of the previous conversion. The on-Chip
sample and hold begins sampling the newly addressed analog input after the fourth falling edge of the I/O
CLOCK. The sampling operation basically involves charging the internal capacitors to the level of the analog
input voltage.
3. Three clock cycles are applied to the I/O CLOCK terminal and the sixth, seventh, and eighth conversion
bits are shifted out on the negative edges of these clock cycles.
4. The final eighth clock cycle is applied to the I/O CLOCK terminal. The falling edge of this clock cycle initiates'
a 12-system clock (=- 12 Ils) additional sampling period while the output is in the high-impedance state.
Conversion is then performed during the next 20 j.1S. After this final I/O CLOCK cycle, CS must go high or
the I/O CLOCK must remain low for at least 20 IlS to allow for the conversion function.
CS can be kept low during periods of multiple conversion. If CS is taken high, it must remain high until the end of
conversion. Otherwise, a valid falling edge of CS causes a reset condition, which aborts the conversion process.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through
4 before the 20-j.1S conversion time has elapsed. Such action yields the conversion result of the previous conversion
and not the ongoing conversion.
The end-of-conversion (EOC) output goes low on the negative edge of the eighth I/O CLOCK. The subsequent
low-to-high transition of EOC indicates the NO conversion is complete and the conversion is ready for trar:lsfer.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-37

2-38

TLC545C, TLC5451, TLC546C, TLC5461
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B - DECEMBER 1985 - REVISED OCTOBER 1996

•
•

S-Bit Resolution AID Converter
Microprocessor Peripheral or Stand-Alone
Operation

•

On-Chip 20-Channel Analog Multiplexer

•

Built-in Self-Test Mode

•
•

Software-Controllable Sample and Hold
Total Unadjusted Error ••• ±O.5 LSB Max

•

Timing and Control Signals Compatible
With S-Bit TLC540 and 10-Bit TLC1540 AID
Converter Families

•

CMOS Technology
PARAMETER
Channel Acquisition Time
Conversion Time (Max)
Sampling Rate (Max)
Power Dissipation (Max)

TL545

TL546

1.511S
91lS
76 x 103
15mW

2.711S
1711S
40 x 103
15mW

N PACKAGE
(TOP VIEW)
INPUT AO
INPUT A1
INPUT A2
INPUT A3
INPUT A4
INPUT AS
INPUT AS
INPUT A7
INPUT A8
INPUT A9
INPUT A10
INPUT A11
INPUT A12
GND

1

6
7
8

21
20
19
18
17
16
15

VCC
SYSTEM CLOCK
1/0 CLOCK
ADDRESS INPUT
DATA OUT
CS
REF+
REFINPUT A18
INPUT A17
INPUT A1S
INPUT A15
INPUT A14
INPUT A13

FN PACKAGE
(TOP VIEW)

description
The TLC545 and TLC546 are CMOS
analog-to-digital converters built around an 8-bit
switched capacitor successive-approximation
analog-to-digital converter. They are designed for
serial interface to a microprocessor or peripheral
via a 3-state output with up to four control inputs
including independent SYSTEM CLOCK, 1/0
CLOCK, chip select (CS), and ADDRESS INPUT.
A 4-MHz system clock for the TLC545 and a
2.1-MHz system clock for the TLC546 with a
design that includes simultaneous read/write
operation allowing high-speed data transfers and
sample rates of up to 76,923 samples per second
for the TLC545, and 40,000 samples per second
for the TLC546.

~

()

9

~~;;;:~
1-1-1-1::J::J::J::J
Il.. Il.. Il.. Il..

()~

:i:()

~9
OCJ)()
0>- 0

~~.~~>CJ);::'

INPUT A4
INPUT A5
INPUT AS
INPUT A7
INPUT A8
INPUT A9
INPUT A10

5
6
7
8

4 321 28 27 26

9
10
11
121314 1516 1718

25
24
23
22
21
20
19

ADDRESS INPUT
DATA OUT
CS
REF+
REFINPUT A18
INPUT A17

In addition to the high-speed converter and
versatile control logic, there is anon-chip
20-channel analog multiplexer that can be used to
sample anyone of 19 inputs or an internal self-test
voltage, and a sample-and-hold that can operate
automatically or under microprocessor control.
The converters incorporated in the TLC545 and TLC546 feature differential high-impedance reference inputs
that facilitate ratiometric conversion, scaling, and analog circuitry isolation from logic and supply noises. A totally
switched capaCitor design allows low-error (±0.5 LSS) conversion in9 I1S for the TLC545, and 171J.S for the
TLC546, over the full operating temperature range.

~TEXAS

INSTRUMENtS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright © 1996, Texas Instruments Incorporated

2-39

TLC545C, TLC5451, TLC546C, TLC5461
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B - DECEMBER 1985 - REVISED OCTOBER 1996

AVAILABLE OPTIONS
PACKAGE
TA

CHIP CARRIER
(FN)

PLASTIC DIP
(N)

TLC545CFN

TLC545CN

TLC5451FN
TLC5461FN

TLC5451N
TLC5461N

O°C to 70°C

-

-40°C to 85°C

-

description (continued) .
The TLC545C and the TLC546C are characterized for operation from O°C to 70°C. )"he TLC5451 and the
TLC5461 are characterized for operation from -40°C to 85°C.

functional block diagram
AO ~
A1 ~
A2 ~
4
A3
5
A4
A5
A6 -;.A7 .~
9
A8
10
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18 -==-

6
7

INPUTS

11
12
13
is
16
17
18

Sample
and
Hold

20-Channel
Analog
Multiplexer

8-Bit
Analog-to-Digital
Converter
(Switched-capacitors)

_

8

I

Input
Address
Register

19
2D

Output
Data
Register

8

-<

1 Self-Test
1 Reference
ADDRESS
INPUT

25

1/0
CLOCK

26

CS
SYSTEM
CLOCK

4

I

5

I
I

-

Input
1 2
MUltiPlexer!-1 ....--1

Control Logic
and 1/0
Counters

a.......,-t~

23

27

~ThxAs'

'

INSTRUMENTS .
2-40

8-to-1 Data
Selector and
Driver

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

~DATA
OUT

TLC545C, TLC5451, TLC546C, TLC5461
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B - DECEMBER 1985 - REVISED OCTOBER 1996

typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE

INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 k.Q TYP

INPUT
AD-A18

~

I

INPUT

AD-A18~

Ci =60pFTYP
(equivalent input
capacitance)

~ 5 MnTYP

operating sequence

CL~6~ --.J,
I
I
I

I
I

1112131415161718

!-I-____

I(

I

'

--+I

~J

I

J..r

Care

I
I 1
'--I
tconv
I~ Access ~I 1
t+I"--_~f-1- Sample Cycle B
I
Cycle B
I (see Note C)
See Note A

cs~ (~~I______________~I
ADDRESS
INPUT---rJ

.: ;Do: n: .;'t:.,~

j+-----

MSB

i+- CycleC
Access-J
I

I

I
I
I
()~I"""'JI _ _ _ _ _- - - - Ir

twH(CS) ~

LSB
I MSB
} -__~D~on~'~tC~a~r~e______~\~____~I( C4

LSB

Don't Care

I'
I

I
I
DATA~

HloZStaty

OUT~

I

MSB +-- Previous Conversion Data A - (see Note B)
MSB

oil

MSB

Conversion Data B

---+~

MSB

NOTES: A. The conversion cycle, which requires 36 system clock periods, is initiated with the eighth 1/0 CLOCK,J, after CS,J, for the channel
whose address exists in memory at that time.
B. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining seven bits
(A6-AO) will be clocked out on the first seven I/O CLOCK falling edges.
C. To minimize errors caused by noise at the CS input, the internal circuitry waits for three system clock cycles (or less) after a chip
select transition before responding to control input signals. Therefore, no attempt should be made to clock-in address data until the
minimum chip-select setup time has elapsed.

~TEXAS

'.

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-41

TLC545C j TLC5451, TLC546C, TLC5461
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B - DECEMBER 1985 - REVISED OCTOBER 1996

absolute maximum ratings over operating free·air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ........................................................... 6.5 V
Input voltage range, VI (any input) ............................................. -0.3 V to Vee +0.3 V
Output voltage range, Vo .................................................... -0.3 V to Vee +0.3 V
Peak input current range (any input) ....................................................... ± 10 mA
Peak total input current (all inputs) ........................................................ ±30 mA
Operating free-air temperature range, TA: TLC545C, TLC546C .......................... O°C to 70°C
TLC5451, TLC5461 .......................... -40°C to 85°C
Storage temperature range, Tst9 ................................................... -65°C to 150°C
Case temperature for 10 seconds, T e: FN package .......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ..................... 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is. not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.

-!!11EXAS

INSTRUMENTS .

2-42

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC545C, TLC5451, TLC546C, TLC5461
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B - DECEMBER 1985 - REVISED OCTOBER 1996

recommended operating conditions
TLC545
MIN

TLC546

NOM

MAX

MIN

NOM

MAX

UNIT

4.75

5

5.5

4.75

5

5.5

V

0

VCC +0.1

0

V

VCC

-0.1

VCC
0

VCC +0.1

-0.1

VCC
0

VCC

V

Differential reference voltage, Vref+ - Vref- (see Note 3)

0

VCC

VCC +0.2

0

VCC

VCC +0.2

V

Analog input voltage (see Note 3)

0

VCC

0

VCC

V

High-level control input voltage, VIH

2

Supply voltage, VCC
Positive reference voltage, Vref+ (see Note 2)
Negative reference voltage, Vref- (see Note 3)

Low-level control input voltage, VIL

2
0.8

Setup time, address bits at data input before 1/0 CLOCKi,
tsu{A)
Address hold time, th
Setup time, CS low before clocking in first address bit, lsu(CS)
(see Note 2)

V

200

400

0

0

ns

3

System
clock
cycles

3
0

1/0 CLOCK frequency, fclock(l/O)
SYSTEM CLOCK frequency, fclock(SYS}

V
0.8

fclock(I/O)

2.048

ns

0

1.1

4 fclock{I/O)

2.1

MHz
MHz

36

36

System
clock
cycles

Pulse duration, SYSTEM CLOCK high, twH(SYS}

110

210

ns

Pulse duration, SYSTEM CLOCK low, twL(SYS) .

100

190

ns

Pulse duration, 1/0 CLOCK high, twH(I/O)

200

404

ns

Pulse duration, I/O CLOCK low, twL(l/O)

200

404

Pulse duration, CS high during conversion, twH(CS)

Clock transition time
(see Note 4)

System
1/0

Operating free-air temperature, TA

ns

fclock(SYS) ~ 1048 kHz

30

30

fclock(SYS) > 1048 kHz

20

20

fclock(l/O) ~ 525 kHz

100

100

fclock{l!O) > 525 kHz
TLC545C, TLC546C

40

40

TLC5451, TLC5461

0

70

0

70

-40

85

-40

85

ns
ns

°c

"
. errors caused by nOise at CS, the mternal circUitry walts for three system clock cycles (or less) after a chip select failing
NOTES: 2. To minimize
edge or rising edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in address
data until the minimum chip select setup time has elapsed.
3. Analog input voltages greater than that applied to REF+ convert as all "l"s (11111111), while input voltages less than that applied
to REF- convert as all "O"s (00000000). As the differential reference voltage decreases below 4.75 V, the total unadjusted error tends
to increase.
4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2 !is for remote data acquisition
applications where the sensor and the ND converter are placed several feet away from the controlling microprocessor.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-43

TLC545C, TLC54,51, TLC546C, TlC5461
a-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B -: DECEMBER 1985::: REVISED, OCTOBER 1996

electrical characteristics over recommended operating temperature range,
Vee Vref+ 4.75 V to 5.5 V, fClock{1I0) 2.048 MHz for TLC545 or fcioCk(1I0)
(unless otherwise noted)
',','
.,

=

=

=

PARAMETER

TEST CONDITIONS

VOH

High-level output voltage (DATA OUT) .

VCC =4.75 V,

IOH = -360 IIA

VOL

Low-level output voltage

VCC =4.75 V,

IOL=3.2 mA

IOZ

Off-state (high-impedance state)ouput current

VO=O,

IIH

High-level input current

VI =VCC

IlL

Low-level input current

VI=O

ICC

Operating supply current

Selected channel leakage current

ICC + Iref
Ci

t

VO=VCC,

Input capacitance

TYpt

MAX

2.4

UNIT
V

0.4
10

CSatVcc

-10

V

IIA

0.005

2.5

-0.005

-2.5

IIA
IIA

CSatOV

1.2

2.5

mA

Selected channel at VCC,
Unselected channel at 0 V

0.4

1

-0.4

-1

1.3

3

7

55

I Control inputs

5

15

Vref+= VCC,

CSatOV

IIA

I Analog inputs

All tYPical values are at TA = 25°C.

-!I1'TEXAS
INSTRUMENTS
2-44

MIN

.CSatVcc

Selected channel at 0 V,
Unselected channel at VCC

Supply and reference current

=1.1 MHz for TLC546

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

mA

pF

TLC545C, TLC5451, TLC546C, TLC5461
8-BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL 'AND 19 INPUTS
SLAS066B - DECEMBER 1985 - REVISED OCTOBER 1996

operating characteristics over recommended operating fr~e·air temperature range,
VCC Vref+ 4.75 V to 5.5 V, fClock(I/O) 2.048 MHz for TLC545 or 1.1 MHz for TLC546,
fclock(SYS) = 4 MHz for TLC545 or 2.1 MHz for TLC546

=

=

PARAMETER

=

TLC545

TEST CONDITIONS

MIN

TYP

TLC546
MAX

MIN

TYP

MAX

UNIT

EL

Linearity error

See Note 5

±0.5

±0.5

LSB

EZS

Zero-scale error

See Note 6

±0.5

±0.5

LSB

EFS

Full-scale error

See Note 6

±0.5

±0.5

LS!3

Total unadjusted error

See Note 7

±0.5

±0.5

LSB

Self-test output code

INPUT A19 address =10011
(see Note8)

01111101
(125)

10000011
(131)

01111101
(125)

10000011
(131)

Conversion time

See Operating Sequence

9

17

liS

Total access and
conversion time

See Operating Sequence

13

25

liS

tacq

Channel acquisition time
(sample cycle)

See Operating Sequence

3

3

clock
cycles

tv

Time output data remains
valid after I/O CLOCK.!.

td

Delay time, I/O CLOCK to
DATA OUT valid

len

Output enable time

'dis

Output disable time

trlbus)

Data bus rise time

!conv

110

10

See Parameter
Measurement Information

10

ns

300

400

ns

150

150

ns

150

150

ns

300

300

ns

Data bus fall time
300
300
ns
tf(bus)
NOTES: 5. Linearity error IS the maximum deViation from the best straight line through the AID transfer characteristics.
6. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
7. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic. The INPUT A19 analog input signal is internally
generated and is used for test purposes.

..

-!11 TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-45

TLC545C,·TLC54SI, TLC546C, TLC5461
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAtCONTROL AND 19 INPUTS
SLAS066B -, DECEMBEfl1985 - REVISED OCTOBER 1996

PARAMETER MEASUREMENT INFORMATION

.

t3k.Q

Output
Under Test

.

CL
(see Note A)

T

.

j

k.Q

VCC

1.4 V

Output
Under Test

Test
. . Point

n

CL
(see Note A)

Test
Point

T

Output
Under Test

CL

3kO

($ee Nole A)

T

See Note B

See NoleB

LOAD CIRCUIT FOR
td. t ... AND If

Test
Point

LOAD CIRCUIT FOR
tpZL AND tpLZ

LOAD CIRCUIT FOR
IpZH AND IPHZ

t

VCC

50%

:1. ________
I
I

OV

SYSTEM
CLOCK
IPZL ~

. Output Waveform 1
(see Note C)

~

J+-

----------------~I~I
.
tpZH

4

I

Output Waveform 2
(see Note C)

VC.C

f 10%

I \. 50%

See Nole B

tpLZ

}~

I \-..---t-~------ OV
j+-I+-- tpHZ
I
I

/50%

" \ : : - - - - VOH

------------'.

OV

VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES

\-~----

1/0 CLOCK

I

~

Id

ou~

0.8V

-.I

-JX========

DATA OUT_ _ _ _ _ _

2.4 V
0.8 V

Ir

I I
-+I I*-

i't~-I
I

~

---

I+-

2.4V
0.4V

tf

VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES

VOLTAGE WAVEFORMS FOR DELAY TIME
NOTES: A. CL = 50 pF for TLC545 and 100 pF for TLC546
B. ten tpZH or tpZL. telis tPHZ or tPLZ
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

=

=

~TEXAS .
INSTRUMENTS
2-46

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC545C, TLC5451, TLC546C, TLC5461
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B - DECEMBER 1985 - REVISED OCTOBER 1996

PARAMETER MEASUREMENT INFORMATION

simplified analog input analysis
Using the equivalent circuit in Figure 1, the time required to charge the analog input capacitance from 0 to Vs
within 112 LSB can be derived as follows:
The capacitance charging voltage is given by
Vc = Vs (1-e -t c/RtCi )

(1 )

where
Rt = Rs + q
The final voltage to 1/2 LSB is given by
(2)

Vc (1/2 LSB) = Vs - (Vs/512)
Equating equation 1 to equation 2 and solving for time

Vs -(VS/512)

= Vs ( 1-e

tc gives

-t CIRtC'I )

(3)

and
tc (1/2 LSB) = Rt x Ci

(4)

x In(512)

Therefore, with the values given the time for the analog input signal to settle is

tc (112 LSB) = (Rs + 1 kill x 60 pF x In(512)

(5)

This time must be less than the converter sample time shown in the timing diagrams.
Driving Sourcet ..
Rs

I
I
I
I

VI

•

TLC545/6

ri

VS~VC
I
1 kOMAX
II

.

I

I

C.

I

50pFMAX

VI = Input Voltage at INPUT AO-A18
VS= External Driving Source Voltage
Rs = Source Resistance
rl = Input Resistance
Ci = Input Capacitance

t Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.

Figure 1. Equivalent Input Circuit Including the Driving Source

-!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2--47

TLC545C, TLC5451, TLC546C, TLC5461
8~BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS

SLAS066B - DECEMBER 1985 - REVISED OCTOBER 1996

PRINCIPLES OF OPERATION
The TLC545 and TLC546 are both complete data acquisition systems on single chips. Each includes such functions
as system clock, sample and hold, 8-bit AID converter, data and control registers, and control logic. For flexibility and
access speed, there are four control inputs; CS, ADDRESS INPUT, I/O CLOCK, and SYSTEM CLOCK. These control
inputs and a TTL-compatible 3-state output facilitate serial communications with a microprocessor or microcomputer.
The TLC545 and TLC546 can complete conversions in a maximum of 9 and 17 IlS respectively, while complete
input-conversion-output cycles can be repeat~d at a. maximum of 13 and 25 IlS, respectively.
The system clock and I/O clock are normally used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for the device.
Once a clock signal within the specification range is applied to the SYSTEM CLOCK input, the control hardware and
software need only be concerned with addressing the desired analog channel, reading the previous conversion result,
and starting the conversion by using the I/O CLOCK. SYSTEM CLOCK will drive the "conversion crunching" circuitry
so that the control hardware and software need not be concerned with this task.
When CS is high, DATA OUT is in a high-impedance condition, and ADDRESS INPUT and I/O CLOCK are disabled.
This feature allows each of these terminals, with the exception of CS, to share a control logic point with their
counterpart terminals on additional AID devices when additional TLCS45/TLC546 devices are used. Thus, the above
feature serves to minimize the required control logic terminals when using multiple AID devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain
the conversion result. A normal control sequence is:
.
1. CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges
and thEm a falling edge of the SYSTEM CLOCK after a CS transition before the transition is recognized. The
MSB of the previous conversion result automatically appears on DATA OUT.
2.

A new positive-logic multiplexer address is shifted in on the first five rising edges of I/O CLOCK. The MSB.of
the address is shifted in first. The negative edges of these five I/O clocks shift out the second, third, fourth,
fifth, and sixth most significant bits of the previous conversion result. The on-chip sample and hold begins
sampling the newly addressed analog input after the fifth falling edge. The sampling operation basically
involves the charging of internal capacitors to the level of the analog input voltage.

3. Two clock cycles are then applied to I/O CLOCK and the seventh and eighth conversion bits are shifted out on
the negative edges of these clock cycles.
4. The final eighth clock cycle is applied to I/O CLOCK. The falling edge of this clock cycle completes the analog
sampling process and initiates the hold function. Conversion is then performed during the next 36 system
clock cycles. After this final I/O clock cycle, CS must go high or the I/O CLOCK must remain low for at least 36
system clock cycles to allow for the conversion function.
CS carl be kept low during periods of multiple conversion. When keeping CS low during periods of multiple
conversion, special care must be exercised to prevent noise glitches on the I/O CLOCK line. If glitches occur on the
I/O CLOCK line, the I/O sequence between the microprocessor/controller and the device loses synchronization. Also,
if CS is taken high, it must remain high until the end of conversion. Otherwise, a valid falling edge of CS causes a
reset condition, which aborts the conversion in progress.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through
4 before the 36 system clock cycles occur. Such action yields the conversion result of the previous conversion and
not the ongoing conversion.

-!II TEXAS

2-48

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC545C, TLC5451, TLC546C, TLC5461
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B - DECEMBER 1985 - REVISED OCTOBER 1996

PRINCIPLES OF OPERATION
It is possible to connect SYSTEM CLOCK and I/O CLOCK together in special situations in which controlling circuitry
points must be minimized. In this case, the following special points must be considered in addition to the requirements
of the normal control sequence previously described.
1.

The first two clocks are required for this device to recognize CS is at a valid low level when the common clock
signal is used as an 1/0 CLOCK. When CS is recognized by the device to be at a high level, the common clock
signal is used for the conversion clock also.

2.

A low CS must be recognized before the 1/0 CLOCK can shift in an analog channel address. The device
recognizes a CS transition when the SYSTEM CLOCK terminal receives two positive edges and then a
negative edge. For this reason, after a CS negative edge, the first two clock cycles do not shift in the address.
Also, upon shifting in the address, CS must be raised after the eighth valid (10 total) 1/0 CLOCK. Otherwise,
additional common clock cycles are recognized as 1/0 CLOCKS and shift in an erroneous address.

For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.
This device accommodates these applications. Although the on-chip sample and hold begins sampling upon the
negative edge of the fourth valid 1/0 clock cycle, the hold function is not initiated until the negative edge of the eighth
valid 1/0 clock cycle. Thus, the control circuitry can leave the 1/0 clock signal in its high state during the eighth valid
1/0 clock cycle, until the moment at which the analog signal must be converted. The TLC545/546 continues sampling
the analog input until the eighth valid falling edge of the 1/0 clock. The control circuitry or software must then
immediately lower the 1/0 clock signal to initiate the hold function at the desired point in time and to start conversion.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-49

2-50

TLC548C, TLC5481, TLC549C, TLC5491
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
•
•
•
•
•

•
•
•
•
•
•

•

•

o OR P PACKAGE

Microprocessor Peripheral or Standalone
Operation
8-Bit Resolution AID Converter
Differential Reference Input Voltages
Conversion Time . .. 17 I1S Max
Total Access and Conversion Cycles Per
Second
- TLC548 ... up to 45 500
- TLC549 ... up to 40 000
On-Chip Software-Controllable
Sample-and-Hold Function
Total Unadjusted Error . .. ±0.5 LSB Max
4-MHz Typical Internal System Clock
Wide Supply Range . .. 3 V to 6 V
Low Power Consumption . .. 15 mW Max
Ideal for Cost-Effective, High-Performance
Applications including Battery-Operated
Portable Instrumentation
Pinout and Control Signals Compatible
With the TLC540 and TLC545 8-Bit AID
Converters and with the TLC1540 10-Bit
AID Converter
CMOS Technology

(TOP VIEW)

REF+D8
REF-

ANALOG IN
GND

2
3
4

7
6
5

VCC

1/0 CLOCK
DATA OUT
CS

description
The TLC548 and TLC549 are CMOS analog-to-digital converter (ADC) integrated circuits built around an 8~bit
switched-capacitor successive-approximation ADC. These devices are designed for serial interface with a
microprocessor or peripheral through a 3-state data output and an analog input. The TLC548 and TLC549 use
only the input/output clock (1/0 CLOCK) input along with the chip select (CS) input for data control. The
maximum 1/0 CLOCK input frequency of the TLC548 is 2.048 MHz, and the 1/0 CLOCK input frequency of the
TLC549 is specified up to 1.1 MHz.
AVAILABLE OPTIONS
PACKAGE
TA

SMALL OUTLINE
(0)

PLASTICOIP
(P)

O°Cto 70°C

TLC548CD
TLC549CD

TLC548CP
TLC549CP

-40°C to 85°C

TLC5481D
TLC5491D

TLC5481P
TLC5491P

~TEXAS

Copyright © 1996, Texas Instruments Incorporated

.

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-51

TLC548C, TLC5481, TLC549C, TLC5491
8·BIT ANALOG·TO· DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C - NOVEMBER 1983 - REVISED SEPTEMBER 1996

description (continued)
Operation of the TlC548 and the TLC549 is very similar to that of the more complex TLC540 and TLC541
devices; however,.the TLC548 and TLC549 provide an on-chip system clock that operates typically at4 MHz
and requires no external components. The on-chip system clock allows internal devic:e operation to proceed
independently of serial input/output data timing and permits manipulation of the TLC548 and TLC549 as desired
for a wide range of software and hardware requirements. The I/O CLOCK together with the internal system clock
allow high-speed data transfer and conversion rates of 45 500 conversions per second for the TLC548, and
40 000 conversions per second for the TLC549.
Additional TLC548 and TLC549 features include versatile control logic, an on-chip sample-and-hold circuit that
can operate automatically or under microprocessor control, and a high-speed converter with differential
high-impedance reference voltage inputs that ease ratiometric conversion, scaling, and circuit isolation from
logic and supply noises. Design of the totally switched-capacitor successive-approximation converter circuit
allows conversion with a maximum total error of ±0.5 least significant bit (LSB) in leSS than 17 Ils.
The TLC548C and TLC549C are characterized for operation from O°C to 70°C. The TLC5481 and TLC5491 are
characterized for operation from -40°C to 85°C.

functional block diagram
REF+
REF-

ANALOG IN

1

3

~

Sample
and
Hold
r-

8-Bit
Analog-to
Digital
Converter
(SwitchedCapacitors)

H'-

8

Output
Data
Regiser

4r--

r-

Internal
System
Clock

cs
1/0 CLOCK

5

7

8-to-1 Data
Selector
and
Driver

6 DATA
OUT

f-

~

'--

I--Control
Logic and
Output Counter

typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
1 kOTYP
ANALOGIN~

I

INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

ANALOGIN~

Ci =60pFTYP
(equivalent Input
capacitance)

~TEXAS'

2-52

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

.

;h

5 MOTYP

TLC548C, TLC5481, TLC549C, TLC5491
8·BIT ANALOG·TO·DIGITALCONVERTERS
WITH SERIAL CONTROL
SLAS067C - NOVEMBER 1983 - REVISED SEPTEMBER 1996

operating sequence

11 12 13 14 15 16 17 18
1/0

Don'l

CLOCK --..,

Access

I"- Cycle B -+J

I

tsu(CS) ~
CS

OUT

Sample
Cycle B

I+-----+j

11 12 13 14 15 16

~

tconv ----I
(see Note A)

r- Cycle
Access ~
C

I

~

18

I"-- Sample ---+J
CycleC

-i~~\~I~
I
________________~I,...._ _~() ~U(CS)
~(~):__________________~r-:

DATA

rI

"ci;;e"-, .

-1<

:

j4-- twH(CS)

i

:

Hi-Z State

A7

II
A7
I I . - - Previous Conversion Data A _ _
II MSB
LSB
MSB
II (see Note B)
ten~r

II
II

111+
.. - - -

II MSB
ten~~

B7
Conversion Data B ----~

LSB

MSB

(17

NOTES: A. The conversion cycle, which requires 36 internal system clock periods
IlS maximum), is initiated with the eighth 1/0 clock pulse
trailing edge after CS goes low for the channel whose address exists in memory at the time.
B. The most significant bit (A7) is automatically placed on the DATA OUT bus after CS is brought low. The remaining seven b~s (AG-AO)
are clocked out on the first seven 1/0 clock falling edges. 87-80 follows in the same manner.

absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) .......................................................... 6.5 V
Input voltage range at any input ........................................... :. -0.3 V to Vee + 0.3 V
Output voltage range ...................................................... -0.3 V to Vee + 0.3 V
Peak input current range (any input) ..................................-................... ±10 mA
Peak total input current range (all inputs) ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±30 mA
Operating free-air temperature range, TA (see Note 2): TLC548C, TLC549C ............. O°C to 70°C
TLC5481, TLC5491 ............ -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTES:

1. All voltage values are with respect to the network ground terminal with the REF- and GND terminals connected together, unless
otherwise noted.
2. The D package is not recommended below -40°C.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-53

TLC548C, TLC5481, TLC549C, TLC5491
8-81T ANALOG·TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C - NOVEMBER 1983 - REVISED SEPTEMBER 1996

recommended operating conditions
TLC549

TLC548

MIN
Supply voltage, Vce

3
2.5

Positive reference voltage, Vref+ (see Note 3)

NOM
5

MAX

6

-{).1

Vec VCC+0.1
0
2.5

1

VCC VCC+0.2

1

VCC VCC+0.2

Analog input voltage (see Note 3)

0

High-level control input voltage, VIH (for VCC = 4.75 V to 5.5 V)

2

VCC

0

VCC

2
0.8

0

5

3

-0.1

InpuVoutput clock frequency, fclock(llO) (for VCC = 4.75 V to 5.5 V)

MAX

2.5

Differential reference voltage, Vref+, Vref- (see Note 3)

Low-level control input voltage, VIL (for VCC = 4.75 V to 5.5 V)

NOM

6,

Vee VCC+O.1
0
2.5

Negative reference voltage, Vref- (see Note 3)

MIN

2.048

0

UNIT
V
V
V
V
V
V

0.8

V

1.1

MHz

InpuVoutput clock high, twH(lfOI (for VCC = 4.75 V to 5.5 V)

200

404

ns

InpuVoutput clock low, twL(IIO) (for VCC = 4.75 V to 5.5 V)

200

404

ns

InpuVoutput clock transition time, tt(IIO)
(for VCC = 4.75 V to 5.5 V) (see Note 4 and Operating Sequence)

100

100

ns

Duration of CS input high state during conversion, twH(CS)
(for VCC = 4.75 V to 5.5 V) (see Operating Sequence)

17

17

liS

Setup time, CS low before first 110 CLOCK, tsu(CS)
(for VCC = 4.75 V to 5.5 V) (see Note 5)

1.4

1.4

lIS

TLC548C,TLC549C
TLC548t, TLC549i

0

70

0

70

-40

85

-40

85

·C

NOTES: 3. Analog Input voltages greater than that applied to REF+ convert to all ones (11111111), while inPut voltages less than that applied
to REF- convert to all zeros (00000000). For proper operation, the positive reference voltage Vref+, must be at least 1 V greater than
the negative reference voltage, Vref-. In addition, unadjusted errors may increase as the differential reference voltage, Vref+- Vref-,
falls below 4.75 V.
4. This is the time required for the 110 CLOCK input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2 lIS for remote data acquisition
applications in which the sensor and the ADC are placed several feet away from the contrOlling microprocessor.
5. To minimize errors caused by noise at the CS input, the internal circuitry waits for two rising edges and one falling edge of internal
system clock after CS.\. before responding to control input signals. This CS setup time is given by the len and tsu(CS) specifications.

~1ExAs

2-54

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC548C, TLC5481, TLC549C, TLC5491
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C - NOVEMBER 1983 - REVISED SEPTEMBER 1996

electrical characteristics over recommended operating free-air temperature range,
Vee Vref+ 4.75 V to 5.5 V, fclock(I/O) 2.048 MHz for TLC548 or 1.1 MHz for TLC549
(unless otherwise noted)

=

=

=

PARAMETER

TEST CONDITIONS

MIN

TYpt

MAX

VOH

High-level output voltage

VCC = 4.7SV.

IOH =- 360 11A

VOL

Low-level output voltage

VCC =4.7SV.

IOL= 3.2 mA

VO=VCC.

CSat VCC

10

Vo =0.

CSatVcc

-10

IOZ

High-impedance off-state output current

IIH

High-level input current. control inputs

VI = VCC

IlL

Low-level input current. control inputs

VI=O

II(on)

Analog channel on-state input current during sample
cycle

Analog input at 0 V

ICC

Operating supply current

ICC+lref

Supply and reference current

I Analog inputs

Input capacitance

Ci

UNIT
V

2.4
0.4

O.OOS

2.S

-O.OOS

-2.S

V
llA

!1A
!1A

0.4

1

-0.4

-1

CS atOV

1.B

2.S

mA

Vref+= VCC

1.9

3

mA

7

5S

S

15

Analog input at VCC

I Control inputs

.!1A

pF

operating characteristics over recommended operating free·air temperature range,
Vee Vref+ 4.75 Vto 5.5 V, fclock(I/O) 2.048 MHz for TLC548 or 1.1 MHz for TLC549
(unless otherwise noted)

=

=

=

TLC549

TLC548
TEST CONDITIONS

PARAMETER

MIN

TYpt

MAX

MIN

TYPt

MAX

. UNIT

EL

Li nearity error

See Note 6

±O.5

±O.S

LSB

EZS

Zero-scale error

See Note 7

±O.S

±0.5

LSB

EFS

Full-scale error

See Note 7

±0.5

±O.5

LSB

Total unadjusted error

See Note 8

±0.5

±D.5

LSB

Conversion time

See Operating Sequence

8

17

12

17

lls

Total access and conversion time

See Operating Sequence

12

22

19

25

lls

ta

Channel acquisition time (sample cycle)

See Operating Sequence

4

clock
cycles

tv

Time output data remains
valid after 1/0 CLOCKJ.

!conv

1/0
4

10
I/OCLOCKJ.

ns

10

!d

Delay time to data output valid

200

400

ns

len

Output enable time

1.4

1.4

lls

!dis

Output disable time

150

150

ns

tr(bus)

Data bus rise time

300

300

ns

Iflbus)

Data bus fall time

300

300

ns

See Figure 1

tAli typlcals are at VCC = 5 V. TA = 25°C.
NOTES: 6. Linearity error is the deviation from the best straight line through the AID transfer characteristics.
7. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
8. Total unadjusted error is the sum of linearity. zero-scale, and full-scale errors.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-55

TLC548C, TLC5481, TLC549C, TLC5491
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C - NOVEMBER 1983 - REVISED SEPTEMBER 1996

PARAMETER MEASUREMENT INFORMATION
1.4 V

3ka
Output
Under Test
CL
(see Note A)

Output
Under Test

Test
Point

n.

CL
(see Note A)

I

Test
Point

Output
Under Test

3kO

T

j

VCC

3kO
Test
. Point

.

CL
(see Note A)

I

See Note B
See Note B

LOAD CIRCUIT FOR
td, t r , AND tf

CS

LOAD CIRCUIT FOR
tpZH AND tpHZ

~~5_0_%________________~~~1r50-~-._--_-_--_--_-_--_-_--_---

rII

Output Waveform 1
(see Note C)

:

r

I

~
.
I

14-

tpZL

I
j4-

~

1

41

tpHZ

~

I

I

50%

_ _ _ _ _ _- - J

::C

_ - - - - Vcc

~___ _

: .

I .

tpZH

tPLZ

I

\50%

I

Output Waveform 2 .
(see Note C)

LOAD CIRCUIT FOR
tpZL AND tPLZ

ov
VOH

\::----

0V

See Note B

VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES

1/0 CLOCK

outPu~

\ - - - - - - 0.8 V

I

I+-

td

-.I

-JX==== ====

DATA OUT___________

2.4 V
0.8 V

I I
I+--

tr(bus) ~

kc---

2.4V

I - - - 0.4V
I I
~ I+-- tf(bus)

VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES

VOLTAGE WAVEFORMS FOR DELAY TIME
NOTES: A. CL = 50 pF for TLC548 and 100 pF for TLC549; CL includes jig capacitance.
B. ten = tPZH or tPZL, Ictis '" tPHZ or tPLZ·
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

Figure 1. Load Circuits and Voltage Waveforms

~'TEXAS

2-56

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC548C, TLC5481, TLC549C, TLC5491
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C - NOVEMBER 1983 - REVISED SEPTEMBER 1996

APPLICATIONS INFORMATION

simplified analog input analysis
Using the equivalent circuit in Figure 2, the time required to charge the analog input capacitance from 0 to Vs
within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by
Vc

= Vs

(1-e -te/RtCj )

(1 )

where
Rt = Rs + q

The final voltage to 1/2 LSB is given by
Vc (112 LSB) = Vs - (VS/512)

(2)

Equating equation 1 to equation 2 and solving for time Ie gives
Vs -(Vs/512) = Vs ( 1-e -teIRtC'I )

(3)

te (112 LSB) = Rt x Cj x In(512)

(4)

and

Therefore, with the values given the time for the analog input signal to settle is
te (112 LSB)

= (Rs + 1 kn) x 60 pF x In(512)

(5)

This time must be less than the converter sample time shown in the timing diagrams.
Driving Sourcet

.~---:

---..

TLC548/9

I
Rs

VI

ri

VS~VC

i

1. kQMAX

I
I

~

I

Ci
55pFMAX

VI = Input Voltage at ANALOG IN
VS= External Driving Source Voltage
Rs = S\lurce Resistance
ri = Input Resistance
CI = Input Capacitance

t Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.

Figure 2. Equivalent Input Circuit Including the Driving Source

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-57

TLC548C, TLC5481, TLC549C, TLC5491
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C - NOVEMBER 1983 - REVISED SEPTEMBER 1996

'PRINCIPLES OF OPERATION
The TLC548 and TLC549 are each complete data acquisition systems on a single chip. Each contains an internal
system clock, sample-and-hold function, 8-bit AJD converter, data register, and control logic circuitry. For flexibility
and access speed, there are two control inputs: 1/0 CLOCK and chip select (CS). These control inputs and a
TTL-compatible 3-state output facilitate serial communications with a microprocessor or minicomputer, A conversion
can be completed in 17 I1s or less, while complete input-conversion-output cycles can be repeated in 2211S for the
TLC548 and in 25 I1S for the TLC549,
The internal system clock and 1/0 CLOCK are used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for the device.
Due to this independence and the internal generation of the system clock, the control hardware and software need
only be concerned with reading the previous conversion result and starting the conversion by using the I/O clock, In
this manner, the internal system clock drives the "conversion crunching" circuitry so that the control hardware and
software need not be concerned with this task.
When CS is high, DATA OUT is in a high-impedance condition and I/O CLOCK is disabled, This CS control function
allows I/O CLOCK to share the same control logic pOint with its counterpart terminal when additional TLC548 and
TLC549 devices are used. This also serves to minimize the required control logic terminals when using multiple
TLC548·and TLC549 devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain
the conversion result. A normal control sequence is:
1. CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges
and then a falling edge of the internal system clock after a CS,J, before the transition is recognized, However,
upon a CS rising edge, DATA OUT goes to a high-impedance state within the specified tdis even though the
rest of the integrated circuitry does not recognize the transition until the specified tsu(CS) has elapsed, This
technique protects the device against noise when used in a noisy environment. The most significant bit (MSB)
of the previous conversion result initially appears on DATA OUT when CS goes low.
2. The falling edges of the first four I/O CLOCK cycles shift out the second, third, fourth, and fifth most significant
bits of the previous conversion result. The on-chip sample-and-hold function begins sampling the analog
input after the fourth high-to-Iow transition of I/O CLOCK. The sampling operation basically involves the
charging of internal capacitors to the level of the analog input voltage.
3, Three more I/O CLOCK cycles are then applied to the I/O CLOCK terminal and the sixth, seventh, and eighth
conversion bits are shifted out on the falling edges of these clock cycles,
4, The final (the eighth) clock cycle is applied to I/O CLOCK. The on-chip sample-and-hold function begins the
hold operation upon the high-to-Iow transition of this clock cycle, The hold function continues for the next four
internal system clock cycles, after which the holding function terminates and the conversion is performed
during the next 32 system clock cycles, giving a total of 36 cycles, After the eighth I/O CLOCK cycle, CS must
go high or the I/O clock must remain low for at least 36 internal system clock cycles to allow for the completion
of the hold and conversion functions, CS can be kept low during periods of multiple conversion, When
keeping CS low during periods of multiple conversion, special care must be exercised to prevent noise
glitches on the I/O CLOCK line. If glitches occur on I/O CLOCK, the I/O sequence between the
microprocessor/controller and the device loses synchronization. When CS is taken high, it must remain high
until the end of conversion, Otherwise, a valid high-to-Iow transition of CS causes a reset condition, which
aborts the conversion in progress,
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through
4 before the 36 internal system clock cycles occur, Such action yields the conversion result of the previous conversion
and not the ongoing conversion.

~TEXAS

2-58

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC548C, TLC5481, TLC549C, TLC5491
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C - NOVEMBER 1983 - REVISED SEPTEMBER 1996

PRINCIPLES OF OPERATION
For certain applications, such as strobing applications. it is necessary to start conversion at a specific point in time.
This device accommodates these applications. Although the on-chip sample-and-hold function begins sampling
upon the high-to-Iow transition of the fourth I/O CLOCK cycle, the hold function does not begin until the high-to-Iow
transition of the eighth I/O CLOCK cycle, which should occur at the moment when the analog signal must be
converted. The TLC548 and TLC549 continue sampling the analog input until the high-to-Iow transition of the eighth
I/O CLOCK pulse. The control circuitry or software then immediately lowers I/O CLOCK and starts the holding function
to hold the analog signal at the desired point in time and starts the conversion.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265

2-59

2-60

TLC0820AC, TLC0820AI
Advanced LinCMOSTM HIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
•

Advanced LinCMOSTM Silicon-Gate
Technology

DB, OW, OR N PACKAGE
(TOP VIEW)

•
•
•
•

8-Bit Resolution
Differential Reference Inputs
Parallel Microprocessor Interface
Conversion and Access Time Over
Temperature Range
Read Mode •.. 2.5 J.tS Max

•

No External Clock or Oscillator
Components Required

•

On-Chip Track and Hold

•
•

Single 5-V Supply
TLC0820A Is Direct Replacement for
National Semiconductor ADC0820C/CC and
Analog Devices AD7820KlBIT

ANLGIN
(LSB) DO
D1
D2
D3
WRIRDY
MODE

VCC

6
7

GND

11

NC
OFLW
D7 (MSB)
D6
D5
D4
CS
REF+
REF-

FNPACKAGE
(TOP VIEW)

description
The TLC0820AC and the TLC0820AI are
Advanced LinCMOSTM 8-bit analog-to-digital
converters each consisting of two 4-bit flash
3 2 1 20 19
D2
4
18 OFLW
converters, a 4-bit digital-to-analog converter, a
D3
5
17 D7(MSB)
summing (error) amplifier, control logic, and a
WR/RDY
16 D6
6
result latch circuit. The modified flash technique
MODE
7
15 D5
allows low-power integrated circuitry to complete
8
14 D4
an 8-bit conversion in 1.18 J.1s over temperature.
9 10 11 12 13
The on-chip track-and-hold circuit has a 100-ns
sample window and allows these devices to
convert continuous analog signals having slew
rates of up to 100 mV/J.1s without external
NC-No internal connection
sampling components. TTL-compatible 3-state
output drivers and two modes of operation allow
interfacing to a variety of microprocessors. Detailed information on interfacing to most popular microprocessors
is readily available from the factory.
AVAILABLE OPTIONS
PACKAGE-

TA

TOTAL
UNADJUSTED
ERROR

SSOP
(DB)

O°C to 70°C

±1 LSB

TLC0820ACDB

-40°C to 85°C

±1 LSB

-

PLASTIC
CHIP CARRIER
(FN)

PLASTIC DIP
(N)

TLC0820ACDW

TLC0820ACFN

TLC0820ACN

TLC0820AIDW

TLC0820AIFN

TLC0820AIN

PLASTIC
SMALL OUTLINE
(OW)

Advanced LinCMOS is a trademark of Texas Instruments Incoreorated.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright © 1994. Texas Instruments Incorporated

2-61

TLC0820AC,TLC0820AI
Advanced LinCMOSTM HIGH·SPEED 8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A- SEPTEMBER 1966 - REVISED JUNE 1994

functional block diagram
REF+
REF-

12

4-Bit Flash
Analog-ta-Digltal
Converter
(4 MSBs)

11

4

4

r-----!! OFLW
~ DO (LSB)

4

3

f - - - D1

4

I--

r -

Summing
Amplifier
'-- -1

ANLGIN

1

L...-..-

4-Blt
Dlgltal-to-Analog ~
Converter

4-Bit Flash
Analog-to-Digital
Converter
(4 LSBs)

Output
Latch
and
3-State
Buffers

f - - - D2

r---2 D3
~ D4
~ D5

r----!! D6
4

~ D7(MSB)

+1

II
MODE
WRiRDY
CS
.RD

7

6

Timing
and
Control

13

8

~TEXAS

2-62

INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75265

r--9

Digital
Outputs

TLC0820AC,TLC0820AI
Advanced LinCMOSTM HIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A-SEPTEMBER 1986 - REVISED JUNE 1994

Terminal Functions
TERMINAL
NAME
ANLGIN

NO.

DESCRIPTION

1/0

1

I

CS

13

I

Analog input
Chip select. CS must be low in order for RD or WR to be recognized by the ADC.

DO

2

Digital, 3-state output data, bit 1 (LSB)

03

5

04

14

05

15

06

16

0
0
0
0
0
0
0

07

17

0

GNO

10

INT

9

0

Interrupt. In the write-read mode, the interrupt output (INT) going low indicates that the internal count-down delay
time, Id(int), is complete and the data result is in the output latch. The delay time Id(int) is typically 800 ns starting
after the rising edge of WR (see operating characteristics and Figure 3). If RD goes low prior to the end of Id(int),
INT goes low at the end ~(R!.!.Land the conversion reslilts are available sooner (see Figure 2). INT is reset by
the rising edge of either RD or es.

MODE

7

I

Mode select. MODE is internally tied to GND through a 50-f.IA current source, which acts like a pulldown resistor.
When MODE is low, the read mode is selected. When MODE is high, the write-read mode is selected.

01

3

02

4

Digital, 3-state output data, bit 2
Digital, 3-state output data, bit 3
Digital, 3-state output data, bit 4
Digital, 3-state output data, bit 5
Digital, 3-state output data, bit 6
Digital, 3-state output data, bit 7
Digital, 3-state output data, bit 8 (MSB)
Ground

NC

19

OFLW

18

0

Overflow. Normally OFLW is a logical high. However, if the analog input is higher than Vref+, OFLW will be low at
the end of conversion. It can be used to cascade two or more devices to improve resolution (9 or 10 bits).

8

I

Read. In the write-read mode with CS low, the 3-state data outputs DO through 07 are activated when RD goes
low. RD can also be used to increase the conversion speed by reading data prior to the end of the internal
count-down delay time. As a result, the data transferred to the output latch is latched after the falling edge of RD.
In the read mode with CS low, the conversion starts with RD going low. RD also enables the 3-state data outputs
on completion of the conversion. ROY going into the high-impedance state and INT going low indicate completion
of the conversion.

REF-

11

I

Reference voltage. REF- is placed on the bottom of the resistor ladder.

REF+

12

I

Vee

20

RD

WRIRDY

6

No internal connection

Reference voltage. REF + is placed on the top of the resistor ladder.
Power supply voltage

110

Write ready. In the write-read mode with CS low, the conversion is started on the falling edge of the WR input signal.
The result of the conversion is strobed into the output latch after the internal count-down delay time, td(int), provided
that the RD input does not go low prior to this time. The delay time td(in~ is approximately 800 ns. In the read mode,
ROY (an open-drain output) goes low after the falling edge of CS an goes into the high-impedance state when
the conversion is strobed into the output latch. It is used to simplify the interface to a microprocessor system.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 555303 • OALLAS. TEXAS 75265

2-63

TLC0820AC;,TLC0820AI
Advanced LinCMOSTM HIGH·SPEED 8·BIT ANALOG~TO~DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A - SEPTEMBER'1986 - REVISED JUNE 1994

absolute maximum ratings over operating free-air. temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ........................................................... 10 V
Input voltage range, all inputs (see Note j) ..................................... -0.2 V to Vec+0.2 V
Output voltage range, all outputs (see Note 1) .................................. -0.2 V to Vee+0.2 V
Operating free-air temperature range: TLC0820AC ................ :.................... O°C to 70°C
TLC0820AI ................ : ................... -40°C to 85°C
Storage temperature range ........................................................ -65°C to 150°C
Case temperature for 10 seconds: FN package .............................................. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DB, DWor N package ........... 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to network GND.

recommended operating conditions
MIN

NOM

MAX

Supply voltage, Vee

4.5

5

8

Analog input voltage

-0.1

UNIT
V

Vee+ 0.1

V

Positive reference voltage, Vref+

Vref-

Vee

v

Negative reference voltage, Vref-

GND

Vref+

V

High-level input voltage, VIH

Vee = 4.75 V to 5.25 V

Low-level input voltage, VIL

Vee = 4.75 V to 5.25 V

es, WRIRDY, RD
MODE

0.8

MODE

1.5

TLe0820Ae
TLe0820AI

-!!1TEXAS
2-64

V

3.5

es, WRIRDY, RD

Pulse duration, write in write-read mode, t~(W) (see Figures 2, 3, and 4)
Operating free-air temperature, TA

2

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

0.5

50

0

70

-40

85

V
!ls
°e

TLC0820AC,TLC0820AI
Advanced LinCMOSTM HIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A - SEPTEMBER 1986 - REVISED JUNE 1994

electrical characteristics at specified operating free-air temperature, Vee
noted)
PARAMETER

TEST CONDITIONS

Vee =4.75 V,
VOH

VOL

High-level output voltage

Low-level output voltage

00-07, INT, or
OFLW

DO-D7,OFLW, INT,
orWR/ROY

IOH=-360~

High-level input current

Low-level input current

Off-state (high-impedance-state)
output current

25°C

4.6
0.4

25°C

0.34

Full range

VIL=O

t

ICC

Supply cu rrent

ei

Input capacitance

Co

Output capacitance

Full range

IS

..

as specified

eSat5V,

VI =

a

VO=5V

DO-D7 or OFLW

es, WR/RDY, and
RDatOV

In

00-07

-1

-0.1

..

3
0.3

Full range

-3
7

25°C

8.4

Full range

-6
-7.2

Full range

-4.5

25°C

-5.3

Full range

1.25

25°C

1.4

14

Full range

mA

-12

-9
6
2.3

Full range
25°C

~

-0.3

25°C

25°C

IlA

-0.3

25°C

Full range

~

0.3
-3

Full range

Full range

ANLGIN
00-07

-0.005

0.1

25°C
VI=5V

~

3

25°C

INT
Reference resistance

170

Full range

eSat5V,

0.3

50

Full range

DO-D7 or WRiRDY

1

200

25°C

VO=O

Rref

0.1

Full range

es, WRiRDY, RO,
or MODE

V

3

25°C

VIH =5 V

Analog input current

Short-circuit output current

0.005

Full range

WR/ROY

UNIT

V

Full range
Full range

00-D7, OFLW, INT,
orWR/ROY
lOS

2.4

MAX

Vee = 5.25 V,
IOL = 1.6 mA

VO=O

II

Full range

TYP

4.5

VO=5V
IOZ

MIN

Full range

MODE
IlL

TAt

IOH=-10~

Vee =4.75 V,

eSorRD

IIH

=5 V (unless otherwise

15
7.5

k.Q

5.3
13

5

mA
pF

45
5

pF

recommended operating conditions .

"!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-65

TLC0820AC, TLC0820AI
Advanced LinCMOSTM HIGH·SPEED 8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A - SEPTEMBER 1986 - REVISED JUNE 1994

operating characteristics,
noted)

Vee = 5 V, Vref+ = 5 V, Vref- = 0, tr = tf =20 ns, TA = 25°C (unless otherwise

PARAMETER
Supply-voltage sensitivity

TEST CONDITIONSt

MIN

TVP

MAX

UNIT

±1/16

±1/4

LSB

1

LSB

VCC= 5V± 5%,

TA = MIN to MAX

MODEatOV,

TA = MIN to MAX

Conversion time, read mode

MODEatOV,

See Figure 1

1.6

2.5

J1S

ta(R)

Access time, RDJ. to data valid

MODE atOV,

See Figure 1

tconv(R)
+20

iconV(RJ
+5

ns

190

280

Access time, RDJ. to data valid

MODEat5 V,
td(WR) < td(int),
See Figure 2

CL = 15 pF

ta(Rl)

CL = 100 pF

210

320

. kSVS

. Total unadjusted error=l=
iconv(R)

ns

MODEat5V,

CL = 15 pF

70

120

id(WR) > id~nt),
See Figure

CL=100pF

90

150

Access time, INTJ. to data valid

MODEat5V,

See Figure 4

20

50

ns

idis

Disable time, RDt to data valid

RL=lkn,
CL = 10 pF,
See Figures I, 2, 3, and 5

70

95

ns

id(int)

Delay time, WR/RDVi to INTJ.

MODEat5V,
CL= 50 pF,
See Figures 2, 3, and 4

800

1300

ns

id(NC)

Delay time, to next conversion

See Figures I,

id(WR)

Delay time, WRlRDVt to RDJ. in
write-read mode

See Figure 2

id(RDY)

Delay time, CSJ. to WRIRDY J.

MODEatOV,
See Figure 1 .

CL= 50 pF,

id(RIH)

Delay time, RDt to INTt

CL= 50 pF,

See Figures I, 2, and 3

id(RIL)

Delay time, RDJ. to INTJ.

MODEat5V,
See Figure 2

td(WR) < id(int),

id(WIH)

Delay time, WR/RDyt to INTt

MODE at5 V,
See Figure 4

CL = 50 pF,

Access time, RDJ. to data valid

ta(R2)
ta(lNn

Slew-rate tracking

..

ns

2, 3, and 4

..

500

ns

0.4

J1S

..

50

100

ns

125

225

ns

200

290

ns

175

270

ns

0.1

t For conditions shown as MIN or MAX, use the appropriate value specIfied under recommended operating conditions .
=1= Total. unadjusted error includes offset, full-scale, and linearity errors.

~TEXAS

INSTRUMENTS
2-66

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

V/flS

TLC0820AC, TLC0820AI
Advanced LinCMOSTM HIGH·SPEED 8·BIT ANALOG· TO·DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A - SEPTEMBER 1986 - REVISED JUNE 1994

PARAMETER MEASUREMENT INFORMATION
\

\

CS\50%
/
I~----------------~

I

1

50%/-

50%

I

~ ~O%

I
I

WRiROY

f+-t

--+j

I+--

td(ROY)

I

--.i i....

~,-5O_._YO__-+,i,

----~-t-----~~~{
~ ta(R) ------.j

1'---

td(NC)~

With External Pullup

*- tconv(R)~

0G-07

50% ' \

1

~

'-----

:1

~

td(RIH)

50%

~~~----I+-- tdis

Figure 1. Read-Mode Waveforms (MODE Low)

cs
tw(W) ~

1

WRiROY

I __--------~--,_--

5ii%'\..J'
td(WR)

50%

I-

50%

~,

-I-

-----+I--~I

\'---

j+--- td(NC) --I

!d(NC)

------T--------+~.

~-----

,~50%

RO

td(RIL)

-1

i

I-

____...-+-,__~ I
INT
I
'~50%
td(lnt)

00-07

T\._.l

I
I_

.~_--

F-+"'l
-I r

I

0

1

.o
I
~

90%
10%

10%

_I I
ta(R2) ~ j4-- -.j

,

I+- tdis

Figure 2. Write-Read-Mode Waveforms
[MODE High and td(WR) < tdClnOJ

I

, .........I----~
~ I
I

00-07 - - - - - - - - - - -

.

--.j

50%\

I+---td(lnt)

td(RIH)

-------+I1~90%
--1
10%

r--

I

1150%

I
I ~,

t a(R1) -+j

I
,
I - - td(WR)--+---.i,
,
I

1

I+- tdls

Figure 3. Write-Read-Mode Waveforms
[MODE High and td(WR) > tdOnt)]

-!!1 TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-67

TLC0820AC, TLC0820AI
Advanced LinCMOSTM HIGH·SPEED'8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A - SEPTEMBER 1966 - REVISED JUNE 1994

PARAMETER MEASUREMENT INFORMATION
CSLow
RDLow
tw(W)
WR/RDY

--t----+l:,.....---"""""\.,
50% .

!+-.l-

~ td(WIH) I

-+J
INT

50%

I I
I 150%

------~I·

"

I

50%
I~'----~'

14-- td(int) --+j
00- 07

td(NC)

.

~

----""")

~~:

I-- ta(INT)

t

Data Valid } -

Figure 4. Write-Read-Mode Waveforms
(Stand-Alone Operation, MODE High, and RD Low)
VCC

CL=10pF

TLC0820 r---I..---,
Input

RD

1---+-_ _On

CS

-1 ~90%
vcc
I
~
tr

Data
Output

RD

50%

.

GND

,.1!l~ _ _ _ _ GND

tdls--l
Data
Outp'uts

~

~VOH
- - - - - - - - - - - - GND

t r =20ns
VOLTAGE WAVEFORMS

TEST CIRCUIT
VCC
TLC0820

~9~0%~--- VCC

1 kn

Input

50%

RD
CS
GND

_.....J.4.1!l~ - - - -

1--......_ . . - _ Data
On
Output

tdis

--I

r--

----.,.....----- Vce

~-VOL

Data
Outputs
t r =20ns

On=00 ... 07

VOLTAGE WAVEFORMS

-'
TEST CIRCUIT

Figure 5. Test Circuit and Voltage Waveforms

~TEXAS

2-68

GND

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC0820AC, TLC0820AI
Advanced LinCMOSTM HIGH·SPEED 8·BIT ANALOG· TO·DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A - SEPTEMBER 1986 - REVISED JUNE 1994

PRINCIPLES OF OPERATION
The TLC0820AC and TLC0820AI each employ a combination of sampled-data comparator techniques and flash
techniques common to many high-speed converters. Two 4-bit flash analog-to-digital conversions are used to give
a full 8-bit output
The recommended analog input voltage range for conversion is -0.1 V to Vee + 0.1 V. Analog input signals that are
less than Vref- + 1/2 LSB or greater than Vref+ -1/2 LSB convert to 00000000 or 11111111, respectively. The reference
inputs are fully differential with common-mode limits defined by the supply rails. The reference input values define
the fUll-scale range of the analog input. This allows the gain of the ADC to be varied for ratio metric conversion by
changing the Vref+ and Vref- voltages.
The device operates in two modes, read (only) and write-read, that are selected by MODE. The converter is set to
the read (only) mode when MODE is low. In the read mode, WR/RDY is used as an output and is referred to as the
ready terminal. In this mode, a low on WR/RDY while CS is low indicates that the device is busy. Conversion starts
on the falling edge of RD and is completed no more than 2.5 IlS later when INT falls and WR/RDY returns to the
high-impedance state. Data outputs also change from high-impedance to active states at this time. After the data is
read, RD is taken high, INT returns high, and the data outputs return to their high-impedance states.
When MODE is high, the converter is set to the write-read mode and WR/RDY is referred to as the write terminal.
Taking CS and WR/RDY low selects the converter and initiates measurement of the input signal. Approximately
600 ns after WR/RDY returns high, the conversion is completed. Conversion starts on the rising edge of WR/RDY
in the write-read mode.
The high-order 4-bit flash ADC' measures the input by means of 16 comparators operating simultaneously. A
high-precision 4-bit DAC then generates a discrete analog voltage from the result of that conversion. After a time
delay, a second bank of comparators does a low-order conversion on the analog difference between the input level
and the high-order DAC output. The results from each of these conversions enter an 8-bit latch and are output to the
3-state output buffers on the falling edge of RD.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-69

TLC0820AC, TLC0820AI
Advanced LinCMOSTM HIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A - SEPTEMBER 1986 - REVISED JUNE 1994

APPLICATION INFORMATION

r-cs
WR

13
CS
Vcc ~5V
6
1
WR/RDY ANLG
IN

~

~

DO
01
J.Lp . 02
Bus
03
04
05
06
07
08
OFL

2
3
4
5
14
15
16

RD

TLC0820
MODE

DO

01
02
03
04
05
06
17
07

REF+

r-2- 5V
12

5V

1 0.1 J.LF
I

REF-

11

1
I

0.1 J.LF

.".

18

OFLW

GNO

h......

13
CS
Vcc
6
WR/RDY ANLG
IN

fY--!
2
3
4
5
14
15
16

17

18

11-20

I--

1

~

5V

RO
TLC0820
00
01
02
03
04
05

MOOE r-J5V
12
REF+

REF-

D6

07
OFLW

1'.'.

F

GNO

11

1-7~

~0.1J.LF

Fi~ure

6. Configuration for 9-Bit Resolution

~TEXAS

2-70

ANLG
IN

INSTRUMENTS .
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC0831 C, TLC0831I
TLC0832C, TLC08321
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
•
•
•
•

•
•
•
•

•

8-Bit Resolution
Easy Microprocessor Interface or
Standalone Operation
Operates Ratiometrically or With 5-V
Reference
Single Channel or Multiplexed Twin
Channels With Single-Ended or Differential
Input Options
Input Range 0 to 5 V With Single 5-V Supply
Inputs and Outputs Are Compatible With
TTL and MOS

TLC0831 •.• 0 OR P PACKAGE
(TOP VIEW)

C S Q 8 Vec

IN+
IN-

2
3

7
6

CLK
DO

GND

4

5

REF

TLC0832 ••• 0 OR P PACKAGE
(TOP VIEW)

C S Q 8 Vec/REF

Conversion Time of 32 ~ at
fclock = 250 kHz
Designed to Be Interchangeable With
National Semiconductor ADC0831 and
ADC0832
Total Unadjusted Error ___ ± 1 LSB

CHO
CH1

2
3

7
6

CLK
DO

GND

4

5 01

description
These devices are 8-bit successive-approximation analog-to-digital converters. The TLC0831 has single input
channels; the TLC0832 has multiplexed twin input channels. The serial output is configured to interface with
standard shift registers or microprocessors.
The TLC0832 multiplexer is software configured for single-ended or differential inputs. The differential analog
voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition, the
voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of
resolution.
The operation of the TLC0831 and TLC0832 devices is very similar to the more complex TLC0834 and TLC0838
devices. Ratiometric conversion can be attained by setting the REF input equal to the maximum analog input
signal value, which gives the highest possible conversion resolution. Typically, REF is set equal to VCC (done
internally on the TLC0832).
The TLC0831 C and TLC0832C are characterized for operation from O°C to 70°C. The TLC0831I and TLC08321
are characterized for operation from -40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA
O'C

to 70'C
to 85'C

-40'C

SMALL OUTLINE
(D)

PLASTIC DIP
(P)

TLC0831CD

TLC0832CD

TLC0831CP

TLC0832CP

TLC083110

TLC08321D

TLC08311P

TLC08321P

~TEXAS

Copyright © 1996, Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-71

TLC0831 C, TLC0831I
TLC0832C, TLC08321
8.. BITANALOG·TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107B- JANUARY 1995- REVISED APRIL 1996

functional block diagram
Start
Flip-Flop

CLK--~------------------------~--'

cs ___.>-+-------------------<1

}+--1""--"'"

~~___t.,_"

'----------[>CLK

Shift Register

I -W-----f'i:;--, ODD/EVEN
Ir---DII
D

S·

I (TLC0832 I

R

L~~2...J

.-----------~------_+--~CLK

SGUDIF
CHO/IN+ - - - - \ Analog

MUX

CH1/IN-

Comparator

EN

r---REF

I

(TLC0831

EN

I

L~~~.J

Ladder
and
Decoder

Bits 0-7

EN R
SAR
Logic
and
Latch

Bits 0-7
Bit 1
MSB
First

EOC
9-Bit
Shift
Register

LSB
First

~TEXAS

2-72

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DO

TLC0831 C, TLC0831I
TLC0832C, TLC08321
8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107B-JANUARY 1995 - REVISED APRIL 1996

functional description
The TLC0831 and TLC0832 use a sample-data-comparator structure that converts differential analog inputs
by a successive-approximation routine. The input voltage to be converted is applied to an input terminal and
is compared to ground (single ended), or to an adjacent input (differential). The TLC0832 input terminals can
be assigned a positive (+) or negative (-) polarity. The TLC0831 contains only one differential input channel with
fixed polarity assignment; therefore it does not require addressing. The signal can be applied differentially,
between IN+ and IN-, to the TLC0831 or can be applied to IN+ with IN- grounded as a single ended input. When
the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the
converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. An interval of one clock period is
automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance
state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares
successive outputs from the resistive ladder with the incoming analog Signal. The comparator output indicates
whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds,
conversion data is simultaneously output from DO, with the most significant bit (MSB) first. After eight clock
periods, the conversion is complete. When CS goes high, all internal registers are cleared. At this time, the
output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-Iow
transition followed by address information.
A TLC0832 input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (01) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. In addition to selecting the differential mode, the polarity
may also be selected. Either channel of the channel pair may be designated as the negative or positive input.
On each low-to-high transition of the clock input, the data on 01 is clocked into the multiplexer-address shift
register. The first logic high on the input is the start bit. A 2-bit assignment word follows the start bit on the
TLC0832. On each sucqessive low-to-high transition of the clock input, the start bit and assignment word are
shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register,
the input channel is selected and conversion starts. The TLC0832 01 terminal to the multiplexer shift register
is disabled for the duration of the conversion.
The TLC0832 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. The 01 and DO
terminals can be tied together and controlled by a bidirectional processor 1/0 bit received on a single wire. This
is possible because 01 is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-73

TLC0831 C, TLC0831I
TLC0832C, TLC08321
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107B-JANUARY 1995 - REVISED APRIL 1996

sequence of operation
TlC0831

2

3

4

6

5

7

8

9

10

ClK

t
CS

..J!.-I 1
su I I 1 1

l

,+14,1---,----- tconv

~.------~

1 1

1
1

J1JlJUlJl

1

1

~.~I~I~----------------------------~lrrr------~
1 1 14
MSB·First Data
~I ) )
Settling Time -+I 1+-1
MUX

DO

~..._=IM=S:B....I. . .

~-_-

_-_-..L.'I""_-_-.........

~-_:_-......r,....,:l'r-;SB_ _~...;.;H;;..;;i.Z~_-

.............,-_-.............,-_:
.....

.....

765432

0

TLC0832

7

6

•••

2

o

2

•••

TLC0832 MUX·A[)ORESS CONTROL LOGIC TABLE
MUXADDRESS
SGl/DIF

ODD/EVEN

CHANNEL NUMBER
CHO

CH1

+
L
L
H
L
+
+
L
H
H
+
H
H = high level, L = low level,
- or + = terminal polarity for the selected input channel

~TEXAS

INSTRUMENTS
2-74

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6

7

TLC0831 C, TLC0831I
TLC0832C, TLC08321
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107B-JANUARY 1995 - REVISED APRIL 1996

absolute maximum tatings over recommended operating free-air temperature range (unless
otherwise noted)t
Supply voltage, Vee (see Note 1) ........................................................... 6.5 V
Input voltage range, Vr Logic ............................................... -0.3 V to Vee + 0.3 V
Analog .............................................. -0.3 V to Vee + 0.3 V
Input current, II .......................................................................... ±5 mA
Total input current ....................................................................... ±20 mA
Operating free-air temperature range, TA: e suffix .................... '.................. ooe to 70°C
I suffix ..................................... -40°C to 85°C
Storage temperature range, TSI9 ...................... , ............................ -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: P package ..................... 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device, These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute·maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.

recommended operating conditions
Supply voltage, VCC
High-level input voltage, VIH

MIN

NOM

MAX

4.5

5

5.5

2

Clock duly cycle (see Note 2)

V
V

0,8

V

10

600

kHz

40%

60%

low-level input voltage, Vil
Clock frequency, fclock

UNIT

Pulse duration, CS high, twH(CS)

220

ns

Setup time, CS low or TlC0832 data valid before ClK'!', tsu

350

ns

Hold time, TlC0832 data valid after ClK'!', th
Operating free-air temperature, TA

90

I Csuffix
II suffix

70

-40

85

NOTE 2: The clock-dUly-cycle range ensures proper operation at all clock frequencies. When a clock frequency
recommended duty-cycle range, the minimum pulse duration (high or low) is 1 Ils,

~TEXAS

ns

0

IS

°C

used outSide the

.

INSTRUMENTS
POST OFFICE

eox 655303 •

DALLAS, TEXAS 75265

2-75

TLC0831 C, TLC0831I
TLC0832C, TLC08~21
,
.
8-BlT ANALOG-TO-DIGITAl CONVERTERS WITH SERIAL CONTROL
SLAS1 07B.- JANUARY 1995 _ REVISED APRIL 1996..

electrical characteristics over recommended range of operating free-air temperature, Vcc= 5 V,
fclock 250 kHz (unless otherwise noted)

=

digital section
PARAMETER

CSUFFIX

TEST CONDITIONSt

MIN

iJA
iJA

TVP*

I SUFFIX
MAX

MIN

TVP*

MAX

UNIT

Vee =4.75 V,

10H = -360

2.8

2.4

Vee =4.75 V,

10H =-10

4.6

4.5

Low-level output voltage

Vee =4.75 V,

10L= 1.6mA

High-level input current

VIH =5 V

IlL

LOW-level input current

VIL=O

10H

High-level output
(source) current

VOH = VOTA = 25°C

10L

Low-level output (sink) current

VOL = Vee,

TA = 25°C

VO=5 V,

TA = 25°C

0.01

3

0.01

3

10Z

High-impedance-state output
current (DO)

VO=O,

TA = 25°C

-0.01

-3

-0.01

-3

Ci

Input capacitance

5

5

pF

Co

Output capacitance

5

5

pF

VOH

High-level output voltage

VOL
IIH

t

0.34

V

0.4

V

0.005

1

0.005

1

-0.005

-1

-0.005

-1

-6.5

-24

8

-6.5

26

..

8

-24

iJA
itA
rnA

26

rnA

iJA

All parameters are measured under open-loop conditions with zero common-mode Input voltage .
All typical values are at Vee = 5 V, TA = 25°C.

=1=

analog and converter section
PARAMETER
VIC

TEST CONDITIONSt

Common-mode input voltage

II(stdby)

Standby input current (see Note 4)

fi(REF)

Input resistance to REF

See Note 3

MIN

TYP*

MAX

-0.05
to
Vee+ 0.05

UNIT
V

On channel·

VI=5V

Off channel

VI

=0

-1

1

On channel

VI =0

-1

Off channel

VI=5V

ItA

1
1.3

2.4

5.9

kQ

t All parameters are measured under open-loop conditions with zero common-mode input voltage.
=1= All typical values are at Vee = 5 V, TA = 25°C.
NOTES: 3. When channel IN- is more positive than channeIIN+, the digital output code is 0000 0000. Connected to each analog input are two
on-chip diodes that conduct forward current for analog input voltages one diode drop above Vee. Care must be taken during testing
at low Vee levels (4.5 V) because high-level analog input voltage (5 V) can, especially at high temperatures, cause the input diode
to conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed the supply
voltage by more than 50 mY, the output code is correct. To achieve an absolute 0- to 5-V input range requires a minimum Vee of
4.95 V for all variations of temperature and load.
4. Standby input currents go in or out of the on or off channels when the AID converter is not performing conversion and the clock is
in a high or low steady-state conditions.

total device
PARAMETER
ICC
=1=

Supply current

I TLe0831

I TLe0832

All typical values are !'It Vee = 5 V, TA = 25°C.

~TEXAS

2-76

INSTRUMENTs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MIN

TVP*

MAX

0.6

1.25

2.5

4.7

UNIT
rnA

TLC0831 C, TLC0831I
TLC0832C, TLC08321
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS1 07B - JANUARY 1995 -REVISED APRIL 1996

op~rating

noted)

characteristics Vee = Vref = 5 V, fclock = 250 kHz, tr = tf = 20 ns, TA = 25°C (unless otherwise
PARAMETER

VCC = 4.75 V to 5.25 V

Total unadjusted error (see Note 5)

Vref=5 V,
TA = MIN to MAX
Differential mode

Common-mode error

t

MIN

TEST CONDITIONSt

Supply-voltage variation error

I MSB-first data

tpd

Propagation delay time,
output data after CLKi (see Note 6)

!dis

Output disable time, DO after cSi

!conv

Conversion time (multiplexer-addressing
time not included)

ILSB-first data

CL=100pF
CL = 10 pF,

RL= 10kn

CL = 100 pF,

RL= 2 kn

TVP

MAX

UNIT

±1!16

±1!4

LSB

±1

LSB

±1!16

±1!4

LSB

650

1500

250

600

125

250
500
8

..

..

ns

ns
clock
periods

All parameters are measured under open-loop conditions with zero common-mode Input voltage. For conditIOns shown as MIN or MAX, use the
appropriate value specified under recommended operating conditions.
NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
6. The MSB-first data is output directly from the comparator and, therefore, requires additional delay to allow for comparator response
time. LSB-first data applies only to TLC0832.

~TEXAS .•
INSTRUMENTS .
POST OFFICE BOX 655303 • DALLAS. TeXAs 75265

2-77

TLC0831 C, TLC0831 I
TLC0832C, TLC08321
8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107B-JANUARY 1995.- REVISED APRIL 1996

PARAMETER MEASUREMENT INFORMATION
Vee
elK

---'I

I

--1

~ ~tsu

GND

~tsu

C;-\il------T-r-----• 0.4V\

II

I

I

1

l--l
I
I
---, I
2V
\I
0.4 V

Vec

.
.1

--

1,_-

--_...I'-=---

\

GND

tpd

DO~';;-

Vcc

vcc

50%

I
I.
GND

~th

~

~

ClK

VOH
VOL

Figure 2. Data-Output Timing

GND

Figure 1. TLC0832 Data-Input Timing
Vcc
Test
Point
1
Rl
From Output ---;I--~.t--'\IV'v
Under Test

I

Cl
(see Note A)

S1

1

~l

lOAD CIRCUIT

-+I
: , - - - - - VCC
90%

_ _~'1-1!!0&.. - - - -

CS

GND

~

Output

I. .1

~
90%

S~~~d_ -

-'- - - -

Vce

_ _.......!!.t_10-&. - - - -

---VCC

S10pen

tr

50%190%

~tdis
DO

I+-

GND

O

DO
utput

VOLTAGE WAVEFORMS

1

VOLTAGE WAVEFORMS

Figure 3. Output Disable Time Test Circuit and Voltage Waveforms

~TEXAS

2-78

tdls

-Vcc
~
S2 closed
10%
- - - - GND

1 open

NOTE A: CL includes probe and jig capacitance.

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

GND

TLC0831 C, TLC0831I
TLC0832C, TLC08321
8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS1 078 - JANUARY 1995 - REVISED APRIL 1996

TYPICAL CHARACTERISTICS
UNADJUSTED OFFSET ERROR

16
III

LINEARITY ERROR

vs

vs

REFERENCE VOLTAGE

REFERENCE VOLTAGE
1.5

VI~ = IVII_I~ ~I ~

14

I/)
..J

1.25

I

!

12

III

~

I

..g
I

10

I

8

1c

6

.~

\

I

4

c

~

9

0.75

:c

;:)

.

1.0

w

~

W

Vee =5 V
fclock = 1 MHz
TA= 25°C

2

::i
I

0.5

..J

\

w

~

0.25

r-

o

0.01

0.1

1.0

"

10

2

Figure 4

Figure 5

LINEARITY ERROR

LINEARITY ERROR

vs

vs

FREE-AIR TEMPERATURE

CLOCK FREQUENCY

0.5

3
Vref=5 V
fclock = 1 MHz

III

~

.g
I

w

f
c

0.4

0.35

::i

I
Vref = 5 V
Vee =5 V

I

2.5

"'""

III

~

..J

w

0.3

-25

o

..

2

:E

1.5

I

"'"

I

0.25
-50

5

4

Vref _ Reference Voltage - V

Vref - Reference Voltage - V

0.45

3

25

i

/

:c

J
8~V25~

:::i
I

.........

50

..J

w
........

0.5

r--..

75

100

_40°C

-

o0

TA - Free-Air Tempertature - °e

100

200

/

300

400

500

600

fclock -. Clock Frequency - kHz

Figure 6

Figure 7

-!11 TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-79

TLC0831 C, TLC0831I
TLC0832C, TLC08321
8~BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107B - JANUARY 1995 - REVISED APRIL.1996

TYPICAL CHARACTERISTICS
TLC0831

TlC0831

SUPPLY CURRENT

SUPPLY CURRENT

vs

vs

FREE·AIR TEMPERATURE

CLOCK FREQUENCY

1.5

1.5 r---..,----r--,-.,.-..,----r---,

I

=

VCC=5V
TA = 25°C

fclock 1 MHz
CS= High

1
I

C

I!!

a
~

8:

::I

II)

I

0.5

-------

i"""""

~
o

0.5 '----'----"--"'----'----"----'
-50
-25
o
25
50
75
100

o

100

200

Figure 8

Figure 9
OUTPUT CURRENT

vs
FREE·AIR TEMPERATURE

25r---..,---,--,----r--,---,

20r-~-r-~----~--~----+----;
c(

E
I

~

15r----r~~~--~~~~--+----;

::I

o

1
::I

10r----r--~---4---~----+---~

o

-IOH (VOH

= 2.4 V)

I

.9

O'----'--~--~-~--~-~

-50

-25

o

25

50

TA - Free-Air Temperature - °C

Figure 10

~TEXAS

2-80

400

fclock - Clock Frequency - kHz

TA - Free-Air Temperature - °C

C

300

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

75

100

500

TLC0831 C, TLC0831I
TLC0832C, TLC08321
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107B- JANUARY 1995 - REVISED APRIL 1996

TYPICAL CHARACTERISTICS
a:a
~
I
~

0.5

1---+---+----+---+---+---1---+-----1

i

.5

~

1!

i

Vref = 5 V

=

C -0.5

O

TA 250C
FCLK = 250 kHz

-1

VOO=5V

o

32

64

128

96

160

192

224

256

224

256

Output Code

Figure 11. Differential Nonlinearity With Output Code
Vref = 5 V

=

TA 25°C
FCLK = 250 kHz
VOO=5V

32

64

96

128

160

192

Output Code

Figure 12. Integral Nonlinearity With Output Code

~

vref=5 V

=

TA 25°C
FCLK = 250 kHz

I

~

~
Iii

0.5

VOO=5V

I

1
~

-o.5r---+---~---r---+--_1---r----+_--~

S

~

~

L -_ _ _ _

o

~

32

____

~

64

_ _ _ _ _ L_ _ _ _

96

~

____

128

~

_ _ _ _ _ _L -_ _ _ _

160

192

~

224

__

~

256

Output Code

Figure 13. Total Unadjusted Error With Output Code

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-81

2-82

TLC0834C, TLC08341, TLC0838C, TLC08381
8-BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C - MARCH 1995 - REVISED APRIL 1997

TLC0834 ..• 0 OR N PACKAGE
(TOP VIEW)

•
•

8-Bit Resolution
Easy Microprocessor Interface or
Stand-Alone Operation

•

Operates Ratiometrically or With 5-V
Reference

NC

4- or 8-Channel Multiplexer Options With
Address Logic

•
•
•

Input Range 0 to 5 V With Single 5-V Supply
Remote Operation With Serial Data Link
Inputs and Outputs Are Compatible With
TTL and MOS

•

•

VCC

01

ClK

CHO

•

•

1

CS

SARS

00
CH3

9

REF

OGTlGNO

8

ANlG GNO

TLC0838 ••. OW OR N PACKAGE
(TOP VIEW)

Conversion Time of 32 IlS at
fclock = 250 kHz
Functionally Equivalent to the ADC0834
and ADC0838 Without the Internal Zener
Regulator Network

CHO
CH1

VCC

NC

CS
01

ClK

Total Unadjusted Error ... ±1 LSB
CH5
CH6

description
These
devices
are
8-bit
successiveapproximation analog-to-digital converters, each
with
an
input-configurable
multichannel
multiplexer and serial input/output. The serial
input/output is configured to interface with
standard shift registers or microprocessors.
Detailed information on interfacing with most
popular microprocessors is readily available from
the factory.

SARS

CH7

6
7
8

COM

9

SE
REF

10

ANlGGNO

OGTlGNO

00

The TLC0834 (4-channel) and TLC0838 (8-channel) multiplexer is software configured for single-ended or
differential inputs as well as pseudo-differential input assignments. The differential analog voltage input allows
for common-mode rejection or offset of the analog zero input voltage value. In addition, the voltage reference
input can be adjusted to allow encoding of any smaller analog voltage span to the full 8 bits of resolution.
The TLC0834C and TLC0838C are characterized for operation from O°C to 70°C. The TLC08341 and TLC08381
are characterized for operation from -40°C to 85°C. The TLC0834Q is characterized for operation from -40°C
to 125°C.
AVAILABLE OPTIONS
PACKAGE
TA

SMALL
OUTLINE
(D)

SMALL
OUTLINE
(OW)

PLASTIC DIP
(N)

O°C to 70°C

TLC0834CD

TLC0838CDW

TLC0834CN

TLC0838CN

-40°C to 85°C

TLC08341D

TLC08381DW

TLC08341N

TLC08381N

-40°C to 125°C

-

-

TLC0834QN

-

~ThXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALUIS. TEXAS 75265

Copyright © 1997, Texas Instruments Incorporated

2-83

~

C/l

CO-l

'r> !:!!o
-10

functional block diagram

.

C/l
0

CD

C::: ~

01 17
(see Note A)

r -_

I

T
0

R
5-Blt Shift Register

Ip>RrFD

Start
Flip-Flop

JCLK
S

0

II;::

CS

>

:II

0
I


"0

:II

IL Only
I
_ _~i

~

~-

~~~
o~

i~g
~~~
. l'r1 t/)
~~

TlC0834 {

TlC0838

r=

cI



<-I

CH1
CH2 4
CH3
CH4
CH5
CH6
CH7
COM

mr-

S

A~~~g

::IJO
-10
meo
::IJW

R

enS2

::e

cs

EN

~

=i
::E:

en
cs

~cn

I

"

I> ClK

-10

m

:II

r:---,
I TlC0838 I

»eo
z~
»0
r-0-1
C)r,0

REF

~

m

::IJ

CS
18

18

5>
r-

R

and

Latch

0

ClK

SAR
logic
Bit 1

9-Bit
IEOC,
Shift
Register

r-ID

DO

I

0

Z

-I
::IJ
0

r-

NOTE A: For the TlC0834, 01 is input direCily to the 0 input of SElECT1 ; SELECTO is forced to a high.
B: Terminal numbers shown are for the OW or N package.

TLC0834C, TLC08341, TLC0838C, TLC08381
8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C - MARCH 1995 - REVISED APRIL 1997

functional description
The TLC0834 and TLC0838 use a sample-data-comparator structure that converts differential analog inputs
by a successive-approximation routine. Operation of both devices is similar with the exception of SE, an analog
common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal
and is compared to ground (single ended), to an adjacent input (differential), or to a common terminal (pseudo
differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative (-)
polarity. When the signal input applied to the assigned positive terminal is less than the signal on the negative
terminal, the converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A particular input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (01) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel
pairs. For example, channel 0 and channel 1 may be selected as a differential pair. These channels cannot act
differentially with any other channel. In addition to selecting the differential mode, the polarity may also be'
selected. Either channel of the channel pair may be designated as the negative or positive input.
The common input on the TLC0838 can be used for a pseudo-differential input. In this mode, the voltage on
the common input is considered to be the negative differential input for all channel inputs. This voltage can be
any reference potential common to all channel inputs. Each channel input can then be selected as the positive
differential input. This feature is useful when all analog circuits are biased to a potential other than ground.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. On each low-to-high transition of the
clock input, the data on 01 is clocked into the multiplexer-address shift register. The first logic high on the input
is the start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of
the clock input, the start bit and assignment word are shifted through the shift register. When the start bit is
shifted into the start location of the multiplexer register, the input channel is selected and conversion starts. The
SAR status output (SARS) goes high to indicate that a conversion is in progress, and 01 to the multiplexer shift
register is disabled for the duration of the conversion.
An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. 00
comes out of the high-impedance state and provides a leading low for one clock period of multiplexer settling
time. The SAR comparator compares successive outputs from the resistive ladder with the incoming analog
signal. The comparator output indicates whether the analog input is greater than or less than the resistive-ladder
output. As the conversion proceeds, conversion data is simultaneously output from DO, with the most significant
bit (MSB) first. After eight clock periods, the conversion is complete and SARS goes low.
The TLC0834 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. When SE is held
high on the TLC0838, the value of the LSB remains on the data line. When SE is forced low, the data is then
clocked out as LSB-first data. (To output LSB first, SE must first go low, then the data stored in the 9-bit shift
register outputs LSB first.) When CS goes high, all internal registers are cleared. At this time, the output circuits
go to the high-impedance state. If another conversion is desired, CS must make a high-to-Iow transition followed
by address information.

01 and 00 can be tied together and controlled by a bidirectional processor 1/0 bit received on a single wire. This
is possible because 01 is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-85

TLC0834C, TLC08341, TLC0838C, TLC08381
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C - MARCH 1995 - REVISED APRIL 1997

sequence of operation
TlC0834

2

4

3

5

6

7

I
I
I

12

13

14

15

20

21

~.~----------+I~r--~s~r~----------I~--~S~~----------~~
tsu

I

+Sign

SGl ggD

Hi·Z

l

I

si~~~~

mFEYEN'Ii

I

~~

~_

I

II

14-1

Mux Settling Time ~

i

II

I

I

i4--- MSB·First Data - - - '
I
I"

1

lSB·Flrst Data ~

I ~I:: I

Hi-Z

- H I . Z - - - - - . L . . - - . LMS--a....
-B

7

6

o

2

6

2

TLC0834 MUX·ADDRESS CONTROL LOGIC TABLE
SGLlDIF

=

L
L
L
L
H
H
H
H

MUXADDRESS
ODD/EVEN
SELECT BIT 1
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

CHANNEL NUMBER
CHO CH1 CH2 CH3
+
+
+
+
+
+
+
+

-

H high level, L = low level, - or + = terminal polanty for the selected
input channel

~1ExAs

2-86

19

I
I

11

DI~III

DO

18

~

tconv

-JI
t~'r

SARS

11

J1JUlfl-J1flJ1J1J1-f1Jl-

ClK

CS

10

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

-

7

r-

TLC0834C, TLC08341, TLC0838C, TLC08381
8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C - MARCH 1995 - REVISED APRIL 1997

sequence of operation
TLC0838
7

8

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

eLK

~H
cs

11 I~
I1
II

.....- - - tconv

lau

\~S____~__________________________~r

I

---...!"I

Mux
Addressing

---., 14- leu

I

I
Si~n
SEL SEL I I
I
Brl BII BII I
I Start.
BnSGLODD I
o~

01

~

,

,

,

,_

DIFEVEN10

I

I

I

: I
HI-Z
SARS -,

I

H

II
I

HI-Z
r-

--------~+---------I-----------------------I I

BE

l

:I

I I I+--

OOHI-_Z_ _ _

I

SS

I 1

14
----:

MSB-Flrsl Data

~I:..I!IM~SBLI~I:: I

I

LSB-Flrsl Data

~BII

.1
HI-Z

IMSBI

r

1:762101234567

--------i,--------~~~~~w~~~-----------------

------------~I~I----~S~S--------------~
MuxSottling --.I :......._ _ _ _ _ _ _ _ _ _ _...!
Time

I

I i4-- MSB-Firat Data
I . I

i

DO _ _ _--,IMSB 1
76

~

LSB Held -..,~
__- - LSB-FlrsIDal.

I

I

---.I

I

i

l
""":"""I~Il
_--:LSB:----____
I -:-&.1"",=,",I~I~1'"'!""I"-="MSB_-......r

I: T'-:
1

2

34567

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-87

TLC0834C, TLC08341, TLC0838C, TLC08381
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C - MARCH 1995 - REVISED APRIL 1997

TLC0838 MUX-ADDRESS CONTROL LOGIC TABLE
MUXADDRESS
SGLlDIF

ODD/EVEN

SELECTED CHANNEL NUMBER
SELECT

1

a

CHO

CH1

+

-

L

L

L

L

L

L

L

H

L

L

H

L

L

L

H

H

L

H

L

L

L

H

L

H

L

H

H

L

L

H

H

H

H

L

L

L

H

L

L

H

H

L

H

L

H

L

H

H

H

H

L

L

H

H

L

H

H

H

H

L

H

H

H

H

1

0

-

CH2

CH3

+

-

2
CH4

CH5

+

-

3
CH6

CH7

+

-

-

.+

COM

+

-

+

-

+

-

+
+
+

-

+

-

+
+
+
+

-

H = high level, L = low level, - or + = polarity of external Input

absolute maximum ratings over recommended operating free-air temperature range (unless
otherwise noted)t
Supply voltage, Vee (see Note 1) .................................. : ........................ 6.5 V
Input voltage range: Logic .................................................. -0.3 V to Vee + 0.3 V
Analog .................................................. -0.3 V to Vee+ 0.3 V
Input current, I, .......................................................................... ±5 mA
Total input current ....................................................................... ±20 mA
Operating free-air temperature range, TA: e suffix ...................................... ooe to 70°C
I suffix ..................................... -40°C to 85°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ..................... 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.

~TEXAS

2-88

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC0834C, TLC08341, TLC0838C, TLC08381
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C - MARCH 1995 - REVISED APRIL 1997

recommended operating conditions
Supply voltage, VCC

MIN

NOM

MAX

4.S

S

S.S

High-level input voltage, VIH

2

Clock duty cycle (see Note 2)

V
V

Low-level input voltage, VIL
Clock frequency, fclock

UNIT

0.8

V

10

SOD

kHz

40%

SO%

Pulse duration, CS high, twHICS)

220

ns

Setup time, CS low, SE low, or data valid before CLKt, tsu (see Figures 1 and 2)

3S0

ns

Hold time, data valid after CLKt, th (see Figure 1)
Operating free-air temperature, TA

90

I C suffix
II suffix

ns

0

70

-40

8S

°C

NOTE 2: The clock-duty-cycle range ensures proper operation at all clock frequencies. When a clock frequency is used outSide the
recommended duty-cycle range, the minimum pulse duration (high or low) is 1 ~s.

Vee =5 V,

electrical characteristics over recommended range of operating free-air temperature,
fclock 250 kHz (unless otherwise noted)

=

digital section
CSUFFIX
PARAMETER

VOH

High-level output voltage

TEST CONDITIONSt

MIN

TYt>*

I SUFFIX
MAX

MIN

Vee =4.7SV,

IOH=-3S0~

2.8

2.4

Vee =4.7SV,

10H =-10 ~A

4.S

4.S

TVP*

MAX

UNIT

V

0.34

Low-level output voltage

Vee =S.2SV,

10L = 1.S rnA

IIH

High-level input current

VIH=5V

VIH =S V

IlL

Low-level input current

VIL=O

VIL=O

10H

High-level output (source) current

VOH =0,

TA = 25°C

-6.S

10L

Low-level output (sink) current

VOL = \ICC,

TA=2Soe

8

VO= SV,

TA = 25°C

0.01

3

0.01

3

10Z

High-impedance-state output
current (DO or SARS)

VO=O,

TA=25°e

-0.01

-3

-0.01

-3

Ci

I nput capacitance

5

pF

Co

Output capacitance

5

pF

O.OOS

1

-O.OOS

-1

-24

0.4

V

VOL

-6.S

26

8

O.OOS

1

~A

-O.OOS

-1

~
rnA

-24
26

..

rnA

~

t All parameters are measured under open-loop conditions with zero common-mode Input voltage (unless otherwise specified) .
:I: All typical values are at Vee = S V, TA = 25°C.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-89

TLC0834C, TLC08341, TLC0838C, TLC08381
8·BIT ANALOG·TO·DIGITALCONVERTERS WITH SERIAL CONTROL
SLAS094C - MARCH 1995 - REVISED APRIL 1997

analog and converter section
PARAMETER
VIC

MIN

See Note 3

-0.05
to
VCC+0.05

Common·mode input voltage

II(stdby)' Standby input current (see Note 4)

rj(REF)

TEST CONDITIONSt

TYP*

MAX

V
1

On channel

VI=5V

Off channel

VI=O

-1

On channel

VI=O

-1

Off channel

VI=5V

).IA

1
1.3

Input resistance to REF

UNIT

2.4

5.9

kn

total device
PARAMETER
ICC

MIN

Supply current

TYP*

MAX

0.6

1.25

t All parameters are measured under open-loop conditions with zero common'mode input voltage.

:t: All typical values are at VCC = 5 V, TA = 25°C.
NOTES: 3. When channel IN- is more positive than channel IN+, the digital output code is 0000 0000. Connected to each analog input are
two on-chip diodes that conduct forward current for analog input voltages one diode drop above VCe.Care must be taken during
testing at low VCC levels (4.5 V) because high-level analog input voltage (5 V) can, especially at high temperatures, cause the input
diode to conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed the supply
voltage by more than 50 mV, the output code is correct. To achieve an absolute 0- to 5-V input range requires a minimum VCC of
4.950 V for all variations of temperature and load.
4. Standby input currents go in or out of the on or off channels when the ND converter is not performing conversion and the clock is
in a high or low steady-state condition.
operating characteristics, Vee
(unless otherwise noted)

=5 V, fclock =250 kHz, tr =tf =20 ns, TA =25°C
TEST CONDITIONS§

PARAMETER
Supply-voltage variation error

VCC = 4.75 V to 5.25 V

Total unadjusted error (see Note 5)

Vref=5 V,

Common-mode error

lpd
lc:Iis

Output disable time, DO or SARS after

!conv

Conversion time (multiplexer-addressing time not included)

I lSB-first data

cst (see Figure 3)

TYP

MAX

±1/16

±1/4

lSB

±1

LSB

±1/4

lSB

TA = MIN to MAX

Differential mode

I MSB-first data

Propagation delay time, output
data after ClK.!. (see Note 6) (see Figure 2)

MIN

±1/16

1500
Cl = 100pF

600

Cl=10pF,

Rl=10kQ

250

Cl = 100 pF,

Rl=2 kQ

500

..

8

UNIT

ns

ns
clock
periods

§ All parameters are measured under open-loop conditions with zero common-mode Input voltage. For conditions shown as MIN or MAX, use the
appropriate value specified under recommended operating conditions.
NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
6. The MSB-first data is output directly from the comparator and, therefore, requires additional delay to allow for comparator response
time.

~TEXAS

2-90

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC0834C, TLC08341, TLC0838C, TLC08381
8-81T ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C - MARCH 1995 - REVISED APRIL 1997

PARAMETER MEASUREMENT INFORMATION

elK
_ _.J

I

1

GNO

'Ir-----:T-------1

co

1

0.4V).
I

I

r-tsu

1

~tsu

1

I+*I

th

1

1

------,
2V

I

GNO

-.i

Vee

1

\I

01

Yee

\

0.4 V

Figure 1. Data-Input Timing

Vee

I

14--1......
1- tpd

tpd

---.l

~

GNO

I
I
----~r------------~~v__ vee
DO ____

J~

50%

:

~\_~Io GNO

I

~

tsu -+I

SE ----------~'\~~--.

Vee
GNO

Figure 2. Data-Output Timing

~1ExAs

INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265

2-91

TLC0834C, TLC08341, TLC0838C, TLC08381
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C - MARCH 1995 - REVISED APRIL 1997

PARAMETER MEASUREMENT INFORMATION
VCC
Test
Point

S1

6

From Output ~~_____-,\RIVL'V--_ _•
Under Test

I

CL
(see Note A)

LOAD CIRCUIT

--.! 14- tr

cs

--.!

II
50%.Jr, 90%

l

VCC

_ _....J.'+110~ ____

GND

90%
~

14 .1

I ____ VCC

S10pen

S~~~«!.-_____

tr

50%[
90%
_10%
_ _....J.'+I
- -

~tdis

DO and SARS

r.---

DO and SARS
GND

VOLTAGE WAVEFORMS

- - -

VOLTAGE WAVEFORMS

Figure 3. Output Disable Time Test Circuit and Voltage Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

GND

tdis

S1 Closed:
S20pen

NOTE A: CL includes probe and jig capacitance.

2-92

VCC

-VCC

TLC0834C, TLC08341, TLC0838C, TLC08381
8·BIT ANALOG·TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C - MARCH 1995 - REVISED APRIL 1997

TYPICAL CHARACTERISTICS
LINEARITY ERROR

UNADJUSTED OFFSET ERROR

vs

vs

REFERENCE VOLTAGE

REFERENCE VOLTAGE

16

m

....

14

e
w

12

UI

1.5

III

1.25

I

'Wi

~

.!l

8

III

m

~

10

'0

I

~

!

6

fc

4

:1

2

CD

::I
I

::J

0.75

fc

::J

'6'

VCC=5V
fclock = 250 kHz
TA = 25°C

V,(+) = V,(_) = 0 V

::i

~

\

0.5

....I

"

w

0.25

r--...

r-

o

0.01

0.1

2

10

Figure 5

Fiaure4
LINEARITY ERROR

LINEARITY ERROR

vs

vs

FREE-AIR TEMPERATURE

CLOCK FREQUENCY

0.5

3

I

vref=15 V

fcloc~ = 250 kHz

m

0.45

UI

....

.
g
I

0.4

'\

~
I

"-

0.35

I

0.3

0.25
-50

2.5

~

::i

....
w

Vre f=5 V
VCC=5V

i

m

w

f

5

4

3

Vref _ Reference Voltage - V

Vref - Reference Voltage - V

-25

g

""""

o

25

50

w
l;'
.;:

2

/

1.5
85°C

III

CD

J
V25O~

c

::i
I

.........

....
w
0.5

i".....

75

100

/

o0

-40°C

100

TA - Free-Air Tempertature - °c

Figure 6

200

300

400

500

600

fclock - Clock Frequency - kHz

Figure 7

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-93

TLC0834C, TLC08341, TLC0838C, TLC08381
8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C - MARCH 1995 - REVISED APRIL 1997

TYPICAL CHARACTERISTICS
SUPPLY CURRENT

SUPPLY CURRENT

vs

vs

FREE-AIR TEMPERATURE

CLOCK FREQUENCY

1.5,...--...,---,---r--r---...,---,

1.5

I

~Ck=250kHz

CS

VCC=5V
TA=25DC

=HIgh

~
I

~

~

:I

U

ic1l
I

~

-

0.5

~
0.5 '--_-'-_-'-_--J._ _'--_-'-_-'
-50
-25
o
25
50
75
100

o

o

100

200

Figure 8

Figure 9
OUTPUT CURRENT

vs
FREE-AIR TEMPERATURE
25~-~---r--r--~---r-~

VCC=5V
20~=-~---+----~--~---+--~

~
I

C
I!!

15r---~~-'~--~~~~-+--~

8

1 10r---~---+----~--4----+--~
0

-IOH (VOH = 2.4 V)

I

.9

O'---~---J.--~-~---J.-~

-50

-25

o

25

50

TA - Free-AIr Temperature - DC

Figure 10

~TEXAS

2-94

300

400

fclock - Clock Frequency - kHz

TA - Free-AIr Temperature - 'C

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

75

100

500

TLC0834C, TLC08341, TLC0838C, TLC08381
8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C - MARCH 1995 - REVISED APRIL 1997

TYPICAL CHARACTERISTICS
III

~

b

:!c

0.5

1---+----+----+---+---t---+---+-----1

O~~fI~~~HNtrnn~~~~~~~~UftRMIft~~ftr~~~

~

Vref = 5 V

Ci

~

:EC

=

TA 25°C

-0.5

FCLK = 250 kHz
VOO=5V

-1

o

32

64

128

96

160

224

192

256

Output Code

Figure 11. Differential Nonlinearity With Output Code
Vref=5 V

III

~
I

=

TA 25°C

=

FCLK 250 kHz
VOO=5V

0.5

€
j

co
z

e -0.5 1---+----+----+---+---t---+---+-----1

I

-1

L -_ _

o

~

__

32

~

64

_ _- k_ _

~

__

128

96

~

___

160

~

__

~_~

224

192

256

Output Code

Figure 12. Integral Nonlinearity With Output Code

~

Vref= 5 V

TA = 25°C

I

..

~

=

0.5

FCLK 250 kHz
VOO=5V

I

1
~

-O.5r---+_--~---r---+--~---r---+_-~

S
~

~

L -_ _

o

~

32

__

~

64

_ __ L_ _

96

~

_ _- J_ _ _L -_ _

128

160

192

~_~

224

256

Output Code

Figure 13. Total Unadjusted Error With Output Code

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-95

2-96

TLC8761, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
•

10-Bit Resolution 20 MSPS Sampling
Analog-to-Digital Converter (ADC)

•
•
•

Power Dissipation ... 107 mW Typ
5-V Single Supply Operation
Differential Nonlinearity ••. ±O.5 LSB Typ

•
•
•
•

No Missing Codes
Power Down (Standby) Mode
Three State Outputs
DigitalllOs Compatible With 5-V or 3.3-V
Logic

•
•

Adjustable Reference Input
Small Outline Package (SOIC). Super Small
Outline Package (SSOP). or Thin Small
Outline Package (TSOP)

•

DB, OW, OR PW PACKAGE
(TOP VIEW)

AGND

AVoo
AIN
CMl

REFBS
REFBF
NC

08
D9

DRGND
DGND

Pin Compatible With the Analog
Devices AD876

REFTF
REFTS
DGND
AGND
OVoo
STBY
DE
ClK

NC - No internal connection

applications
•

Communications

•
•
•

Multimedia
Digital Video Systems
High-Speed DSP Front-End ••• TMS320C6x

description
The TLC876 is a CMOS, low-power, 10-bit, 20 MSPS analog-to-digital converter (ADC). The speed, resolution,
and single-supply operation are suited for applications in video, multimedia, imaging, high-speed acquisition,
and communications. The low-power and single-supply operation satisfy requirements for high-speed portable
applications. The speed and resolution ideally suit charge-coupled device (CCD) input systems such as color
scanners, digital copiers, electronic still cameras, and camcorders. A multistage pipelined architecture with
output error correction logic provides for no missing codes over the full operating temperature range. Force and
sense connections to the reference inputs provide a more accurate internal reference voltage to the reference
resistor string.
A standby mode of operation reduces the power to typically 15 mW. The digital 110 interfaces to either 5-V or
3.3-V logic and the digital output terminals can be placed in a high-impedance state. The format of the output
data is straight binary coding.
A pipelined multistaged architecture achieves a high sample rate with low power consumption. The TLC876
distributes the conversion over several smaller ADC sub-blocks, refining the conversion with progressively
higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a
small fraction of the 1023 comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within
each of the stages permits the first stage to operate on a new input sample while the second through the fifth
stages operate on the four preceding samples.
The TLC876C is characterized for operation from
from -40°C to 85°C.

aoc to 70°C, and the TLC8761 is characterized for operation

-!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

Copyright © 1997. Texas Instruments Incorporated

2-97

TLC8761, TLC876C
1O-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG·TO-DIGITAL CONVERTERS
SLAS140B-JULY 1997 - REVISED NOVEMBER 1997

AVAILABLE OPTIONS
PACKAGE
TA

SUPER SMALL

SMALL
OUTLINE

OUTLINE
(DB)

TSSOP
(PW)

(OW)

O°C to 70°C

TLC876CDB

TLC876CDW

TLC876CPW

-40°C to 85°C

TLC8761DB

TLC8761DW

TLC8761PW

functional block diagram
SHAt

SHAt

GAIN

SHAt

GAIN

SHAt

GAIN

SHAt

GAIN

2

.-------,1=2 (MSB) 09

10

t Sample and hold amplifier

~TEXAS
2-98

INSTRUMENTS

POST oFFice BOX 655303 • DALLAS, TEXAS 75265

,--_3=- (LSB) DO

TLC8761, TLC876C
1a-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLASl40B - JULY 1997 - REVISED NOVEMBER 1997

equivalent input and output circuits
00-09 OUTPUT CIRCUIT

All DIGITAL INPUT CIRCUITS

AIN INPUT CIRCUIT

DVDD
AVDD

~.5PFtYP

AIN
ClK

O.3pF
DRGND

DGND

'J

AGND

DGND
REFERENCE INPUT CIRCUIT
AVDD

30 .-'VV\,------,
REFTF

AVDD
Internal Reference
Voltage
REFTS 29

AVDD

Internal Reference
Voltage

REFBS 35

AVDD
34 ._'VV\,-----'

REFBF
AGND

~TEXAS

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2-99

I

TLC8761, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140B- JULY 1997 - REVISED NOVEMBER 1997

Terminal Functions
TERMINAL
NAME

AGND

NO.

1.19

AIN

27

AVDD

28

CLK
CML

I/O

DESCRIPTION

Analog ground
I

Analog input

15

I

Clock input

26

0

5-V analog supply
Bypass for an internal bias point. Typically a 0.1 I-lF capacitor minimum is connected from this terminal to ground.

DGND

14.20

Digital ground

DVDD

18

5-V digital supply

DRVDD

2

3.3-V/5-V digital supply. Supply for digital input and output buffers.

DRGND

13

DO-D9

3-12

0

Digital data out. DO:LSB. D9:MSB

OE

16

I

Output enable. When OE
impedance.

REFBF

24

I

Reference bottom force

REFBS

25

I

Reference bottom sense

REFTF

22

I

Reference top force

REFTS

21

I

Reference top sense

STBY

17

I

Standby enable. When STBY =low or NC. the device is in normal operating mode. When STBY =high. the device
is in standby mode.

3.3-V/5-V digital ground. Ground for digital input and output buffers.

=low or NC. the device is in normal operating mode. When OE =high. Do-D9 are high

~TEXAS

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INSTRUMENTS
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TLC8761, TLC876C
1O-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140B - JULY 1997 - REVISED NOVEMBER 1997

absoh,lte maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, AVDD to AGND, DVDD to DGND ...................................... -0.3 V to 6.5 V
Reference voltage input range to AGND, V'(REFTF),
V'(REFBF), V'(REFBS), V'(REFTS) ........................................... -0.3 V to AVDD + 0.3 V
Analog input voltage range to AGND ........................................ -0.3 V to AVDD + 0.3 V
Digital input voltage range ................................................. -0.3 V to DVDD + 0.3 V
Digital output voltage range applied from external source ............................. -0.5 V to DVDD
Operating virtual junction temperature range, TJ ..................................... -40°C to 150°C
Operating free-air temperature range, TA TLC876C ..................................... O°C to 70°C
TLC8761 .................................... -40°C to 85°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions
analog and reference inputs
MAX

UNIT

VI(REFB) + 1

MIN

3.6

4.5

V

Reference input voltage (bottom). VI(REFB)

0

1.6

VI(REFT)-1

Analog input voltage. VI(AIN)

1

2

Reference input voltage (top). VI(REFTl

NOM

V
Vpp

power supply
MIN
Supply voltage

NOM

MAX

AVDD*

4.5

5.25

DVDD*

4.5

5.25

DRVDD

3

5.25

UNIT

V

..

* The voltage difference between AVDD and DVDD terminals cannot exceed 0.5 V to maintain performance speCifications .

digital inputs
MIN
DRVDD = 3 V
High-level input voltage. VIH

DRVDD = 5V
DRVDD = 5.25 V

NOM

UNIT

v

4
4.2
0.6

DRVDD =3 V
Low-level input voltage. VIL

MAX

2.4

1

DRVDD = 5V

V

1.05

DRVOO = 5.25 V
Clock period. Ie (see Figure 1)

ns

50

Pulse duration. clock high. tw(CLKH)

23

25

ns

Pulse duration. clock low. tw(CLKL)

23

25

ns

Operating free-air temperature. TA

TLC876C
TLC8761

0

70

'C

-40

85

'C

~TEXAS

INSTRUMENTS
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2-101

TLC8761, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140B-JULY 1997- REVISED NOVEMBER 1997

=

electrical characteristics at AVOO DVOO
fCLK 20 MSPS (unless otherwise noted)

=

=5 V, DRVOO =3.3 V, VI(REFT) =3.6 V, VI(REFB) =1.6 V,

power supply
PARAMETER

IDD

Operating supply current

PD

Power dissipation

PD(STBY)

Standby power

TYP

MAX

AVDDt

TEST CONDITIONS

MIN

17

25

mA

DVDDt

2.7

5

mA

25

100

!1A

107

150

mW

DRVDD

t

STBY = High

I ClK running
IClK inhibited at VDD or 0 V

45

85

15

35

TYP

MAX

..
The voltage difference between AVDD and DVDD terminals cannot exceed 0.5 V to maintain performance specifications .

UNIT

mW

digital logic inputs
PARAMETER

TEST CONDITIONS

MIN

IIH

High-level input current

DVDD= 5 V

-10

10

III

low-level input current

DVDD = 5V

-50

50

Ill{ClK)

low-level input current, ClK

DVDD= 5V

-10

Ci

Input capacitance

10
5

UNIT
!1A
!1A
pF

logic outputs
PARAMETER

VOH

TEST CONDITIONS
IOH = 50!1A

High-level output voltage

IOH=0.5mA

VOL

IOl = 50!1A

low-level output voltage

IOl=0.6 mA
Co

Output capacitance

IOZ

High-impedance-state output current

MIN

DRVDD=3 V

2.4

DRVDD = 5 V

3.8

DRVDD = 5 V

2.4

TYP

MAX

UNIT

V

DRVDD=3.6V

0.7

DRVDD = 5.25 V

1.05

DRVDD = 5.25 V

0.4
pF

5
-10

V

10

!1A

dc accuracy
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Integral nonlinearity (INl)

±1.5

Differential nonlinearity (DNl) (see Note 1)

±O.5

Offset error

-0.4

O/OFSR

0.2

O/OFSR

Gain error

<±1

lSB

NOTE 1: A differential nonlinearity error of less than ±1 lSB ensures no missing codes.

analog input
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

5

Input capacitance

reference input
PARAMETER
Rref

Reference input resistance

Iref

Reference input current

TEST CONDITIONS

TYP

MAX

350

500

750

UNIT

n

4

mA

Reference top offset voltage

35

mV

Reference bottom offset voltage

35

mV

~TEXAS

INSTRUMENTS
2-102

MIN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC8761, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140B - JULY 1997 - REVISED NOVEMBER 1997

=

operating characteristics at AVoo DVoo
fCLK 20 MSPS (unless otherwise noted)

=

=5 V, DRVoo =3.3 V, VI(REFT) =3.6 V, VI(REFB) =1.6 V,

dynamic performancet
PARAMETER

TEST CONDITIONS

MIN

Effective number of bits (ENOB)

fl = 3.58 MHz

8

8.5

Bits

50

fl = 3.58 MHz

dB

53

II = 10 MHz

51

11= 1 MHz

-63

fl = 3.58 MHz

-62

fl=10MHz

-61

fl = 3.58 MHz

-64

dB

200

MHz

Differential phase

0.5

degrees

Differential gain

1%

Total harmonic distortion (THD)

Spurious Iree dynamic range

t

UNIT

53

11= 1 MHz

BW

MAX

8.1

11=10MHz
Signal-to-total harmonic distortion+noise (S/(THD+N))

TYP
8.5

fl = 1 MHz

Analog input lull-power bandwidth

..

-56

dB

The voltage difference between AVDD and DVDD cannot exceed 0.5 V to maintain performance specifications. At Input clock rise times less than
20 ns, the offset full-scale error increases approximately by a factor of (20/t r)0.5 where tr equals the actual rise time in nanoseconds.

timing requirements
PARAMETER

TEST CONDITIONS

fconli

Maximum conversion rate (see Note 2)

Id(o}

Delay time, output

Id(pipe)
Id(A}

MIN

TYP

MAX

20
CL = 20 pF

5

MHz
ns

20

Delay time, pipeline, latency

3.5

Delay time, aperture
Aperture jitter

ldis(DDI Disable time, OE'I to Hi-Z
CL = 20 pF
Enable time, DE! to valid data
Ien(HL}
..
..
NOTE 2: The conversion rate can be a minimum of 10kHz without degradatIOn In specified performance.

UNIT

Clock
cycles

4

ns

22

ps

5

15

ns

5

15

ns

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2-103

TLC8761, TLC876C
10..BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140B - JULY 1997 - REVISED NOVEMBER 1997

PARAMETER MEASUREMENT INFORMATION
sa~m..
p_le_N_ _ Sample N+1

AIN

Sample N+2 __--~

1

---+I :.-

Id(A)

1144- - - - : - - - - - -

1
tw(ClKH)

14

~4

1

1

.1

td(pipe)

-------+'

tw(ClKl)

1

ClK

1
.1

~
00-09

<

Data N-4

14----

1

tc
tC

Figure 1. Timing Diagram

J

OE

D~D9

tdis(DD)

\~

I
-114-4----.t.1

____A_c_ti_W__

______

I

ten(Hl) -M141-----1.~1

_J~~I----~--------~vr------I
Hlgt\ Impedance

\

Figure 2. Output Enable to Data Output Timing Diagram
STBY /

i'~----~---------I~.-!

~tPut Data Valid

ClK

Figure 3. Standby Timing

~TEXAS

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TLC8761, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140B- JULY 1997 - REVISED NOVEMBER 1997

TYPICAL CHARACTERISTICS
SIGNAl-TO-NOISE AND DISTORTION

GAIN

vs

vs

INPUT FREQUENCY

INPUT FREQUENCY

2

55

I

I

0

,

-2

ID

f5

i

f\

'C

is

c

'a

-r-.50

'C

Ii

I

-4

CJ

.~

felK = 20 MSPS
AIN=-0.5dB

ID

'C

=

'is

z

I

~

CJ

-6

III

6.

45

iii
I
Q
c(

-8

z

iii
-10
1

10
100
f - Input Frequency - MHz

40

1000

10

1
f -Input Frequency - MHz

Figure 4

Figure 5
SIGNAL-TO-NOISE AND DISTORTION

TOTAL HARMONIC DISTORTION

vs

vs

INPUT FREQUENCY

CLOCK FREQUENCY

-10

60

fiN = 3.58 MHz
AIN =-0.5 dB

ID

'C

I

ID

c

'C

~0

I

c
0

'E

-30

7ii

~

.~
0

E

~

'C

.
C
III

-50

'0

z

lii
:

S

~

cC)

iii

-70

I

Q

...
:

TI iii

-90
1

50

Oi

THO

{:.
I

55

i5

45

Q
c(

z

iii
10

40 5

f -Input Frequency - MHz

Figure 6

10
15
f - Clock Frequency - MHz

20

Figure 7

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2-105

TLC8761, TLC876C
1O-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS

SLAS140B - JULY 1997 - REVISED NOVEMBER 1997

TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
CLOCK FREQUENCY
150
140

==E
I

c

130

0

~

CL

'iii
.r!!

120

c

j

110

~

0
DI

c

-V

100

D-

90
80

o

5

10

~

15

20

f - Clock Frequency - MHz

Figure 8
In
UI
..J

I

:Eas
CD

.5
C
0

z
iii

~
I!!
CD
!E

c

I
..J

z

C

0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1

0

255

511
Input Code

Figure 9. Differential Nonlinearity

~TEXAS

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767

1023

TLC8761, TLC876C
1O-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140B-JULY 1997 - REVISED NOVEMBER 1997

TYPICAL CHARACTERISTICS
ID

3

I

2

~

~

=
z

.5
C
0

0

'l!

-1

S

-2

l

I
..J

3:

-3

255

0

511

767

1023

Input Code

Figure 10. Integral Nonlinearity

o

0.5

1

1.5

SFDR
SNRD
SNR
THD

: -64 dB

4th

: -68 dB

: 52dB

:-71 dB

: 55dB

5th
6th

: -62 dB

7th

: -70 dB

2nd

: -69 dB

8th

:-70 dB

3rd

: -72 dB

9th

: -60 dB

2

2.5

3

3.5

4 4.5

5

5.5

:-71 dB

6

6.5

7

7.5

8

8.5

9

9.5 10

Frequency - MHz

Figure 11. FFT Plot of Dynamic Performance

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2-107

TLC8761, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140B-JULY 1997 - REVISED NOVEMBER 1997

PRINCIPLES OF OPERATION
definitions of specifications and terminology
integral nonlinearity (INL)

Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 L8B before the first code transition. The full-scale point is defined as a level
1/2 L8B beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two points. This parameter is sometimes referred to as linearily error.
differential nonlinearity (DNL)

An ideal ADC exhibits code transitions that are exactly 1 L8B apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than ± 1 L8B ensures no missing codes. This parameter is sometimes
referred to as differential error.
offset error

The first transition should occur at a level 1/2 L8B above zero. Offset is defined as the deviation of the actual
first code transition from that point.
gain error

The first code transition should occur for an analog value 1/2 L8B above nominal negative full scale (the voltage
applied to the REFBF terminal). The last transition should occur for an analog value 1 1/2 L8B below nominal
positive full scale (the voltage applied to the REFTF terminal). Gain error is the deviation of the actual difference
between the fir!>t and last code transitions from the ideal difference between the first and last code transitions.
pipeline delay (latency)

The number of clock cycles between conversion initiation on an input sample and the corresponding output data
being made available. Once the data pipeline is full, new valid output data are provided every clock cycle.
reference top/bottom offset

Resistance between the reference input and comparator input tap points causes offset errors. These errors can
be nulled out by using the force-sense connection as shown in the driving the reference terminals section.

driving the analog input
Figure 12 shows an equivalent input circuit of the TLC876 sample-and-hold amplifier and it represents an
excellent first order approximation.
The total equivalent capacitance, CE, is typically less than 5 pF and the input source must be able to charge
or discharge this capacitance to 10-bit accuracy in the sample period of one half of a clock cycle. When the
switch 81 closes, the input source must charge or discharge the capacitor CE from the voltage already stored
on CE (the previously captured sample) to the new voltage. In the worst case, a full-scale voltage step on the
input, the input source must provide the charging current through the switch resistance Rsw (50 0) of 81 and
quickly settle (within 1/2 CLK period), and, therefore, the source is driving a low input impedance. However,
when the source voltage equals the value previously stored on CE, the hold capacitor requires no input current
to maintain the charge and the equivalent input impedance is extremely high.
Adding series resistance between the output of the source and the AIN terminal reduces the drive requirements
placed on the source, as shown in Figure 13. To maintain the frequency performance outlined in the
specifications, the resistor should be limited to 200 0 minus the sourcetesistance or less. The maximum source
resistance, RS, for 10-bit, 1/2 L8B accuracy is given by equation 1.

~TEXAS

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TLC8761, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140B-JULY 1997 - REVISED NOVEMBER 1997

PRINCIPLES OF OPERATION

driving the analog input (continued)
(1 )

R <
1
- R
S - 2f(CLK) (C E In 2048)
SW

For I(CLKl =20 MHz, CE = 10 pF, and Rsw = 100 Q, this equation gives 228 Q as a maximum value; hence the
200 Q limit on the total source resistance. For applications with an input clock less than 20 MHz, the size 01 the
series resistor can increase proportionally. Alternatively, adding a shunt capacitor between the AIN terminal and
analog ground can lower the ac source impedance. This capacitance value depends on the source resistance
and the required signal bandwidth.
The input span is determined by the reference voltages (see driving the reference terminals section).
TLC876

Ideal Source

I
I RS S; 200 Q

S1

AIN

AIN

RSW

RS

TLC876

Vs

Figure 12. TLC876 Simplified Equivalent Input

Figure 13. Sample TLC876 Drive Requirements

For many applications, particularly in single supply operation, ac coupling offers a convenient way 01 biasing
the analog input signal at the proper signal range. Figure 14 shows a typical configuration for ac coupling the
analog input Signal to the TLC876. Maintaining the outlined specifications requires careful selection of the
component values. The most important concern is the L3 dB high-pass corner that is a function 01 R2, and the
parallel combination 01 C1 and C2. The L3 dB point can be approximated by equation 2.
1

-

1

(2)

-3 dB - 2lt x (R2)Ceq

where Ceq is the parallel combination of C1 and C2. Since C1 is typically a large electrolytic or tantalum
capacitor, the impedance becomes inductive at high frequencies. Adding a small ceramic or polystyrene
capacitor, C2 of approximately 0.01 IlF, which is not inductive within the frequency range of interest, maintains
a low impedance. If the minimum expected input signal frequency is 20 kHz, and R2 equals 1 kQ and R1 equals
50 Q, the parallel capacitance of C1 and C2 must be a minimum 01 0.008 IlF to avoid attenuating signals close
to 20 kHz.
C1

VIN

R1
---r-1~t--e--J\j\I\r-+-

Y

TLC876
AIN

R2

C2

+

-=-

1-

VBIAS

Figure 14. AC·Coupled Inputs

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TLC8761, TLC876C
1O-SIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140B - JULY 1997 - REVISED NOVEMBER 1997

PRINCIPLES OF OPERATION
driving the analog input (continued)
The expanded input circuit shown in Figure 15 aids in understanding the voltage offset generation when using
the external input circuit in Figure 14.
The ac coupling capacitors, C1 and C2, integrate the switching transients present at the input of the TLC876
causing a net dc bias current, IB, to flow into the input. The magnitude of this bias current increases with
increasing the dc signal level, VB, and also increases with sample frequency. When the sample clock frequency
is 20 MHz, the dc bias current is approximately 30 I1At at VBIAS equal to 3 V dc. This bias current causes an
offset error of (R1 + R2) x IB at the AlN terminal. Making R2 negligibly small or modifying VBIAS to account for
the resultant offset can compensate for this error. Note however that R2 loads the signal driving source and the
value must be sufficient for the application.
For example, as shown in Figure 15, when VBIAS is 3 V and the resistor values stated above, the bias current
causes a 31.5 mV:J: offset from the 3 V bias, VBIAS, at the AIN terminal. For the TLC876, VBIAS can be as low
as 1 V for a 2 V peak-to-peak input signal swing.
C1

TLC876

R1

VB

AIN
RSW

R2

C2
+

-=-

1-

VBIAS

Figure 15. Bias Current and Offset
For systems that require dc-coupling, an op-amp can level-shift a ground-referenced Signal to comply with the
input requirements of the TLC876. Figure 16 shows an amplifier in an inverting mode with ac signal gain of -1.
The dc voltage at the non inverting input of the op-amp controls the amount of dc level shifting. A resistive voltage
divider attenuates the REFBF signal and the op-amp then multiplies the attenuated signal by 2. In the case
where REFBF = 1.6 V, the dc output level is 2.6 V which is approximately equal to (V(REFTF) - V(REFBF)/2.

t IB(AVG) = CE (VB) fCLK ~ 30 flA, with RSW = 50 Q, CE = 5 pF, R1
:I: VOFFSET = 'B(AVG) (R1 + R2)

= 50 Q, and R2 = 1 kQ

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TLC8761, TLC876C
1O-SIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140B-JULY 1997 - REVISED NOVEMBER 1997

PRINCIPLES OF OPERATION

driving the analog input (continued)
RL

=4.99 k!l

VCC

O.1IlF

~

NC
RIN

=4.99 kQ
3k!l

TLC876

>-=6_.__. AIN

REFBF ----'I!V\,---i.-=-t
14.7 k!l

t Amplifier A can be an AD817 or AD818 with terminal numbers as shown. The AD817 and AD818
are wide bandwidth single'supply op-amps,

Figure 16. Bipolar Level Shift

driving the reference terminals
dc considerations
The TLC876 requires an external reference on terminals REFTF and REFBF and a resistor array, nominally
500 Q, is connected between terminals REFTF and REFBF. A Kelvin connection, using the TLC876 reference
sense terminals REFTS and REFBS, minimizes voltage drops caused by external and internal wiring
resistance.
Figure 17 shows the equivalent input structure for the reference terminals. There is approximately 5 Q of
resistance between both REFTF and REFBF terminals and the reference ladder. If the force-sense connections
are not used, the voltage drop across the 5-Q resistors results in a reduced voltage appearing across the ladder
resistance. This reduces the input span of the converter. Applying a slightly larger span between the REFTF
and REFBF terminals compensates for this error. Note that the temperature coefficients of the 5-Q resistors are
1350 ppm. The effects of temperature should be considered when a force-sense reference configuration is not
used.

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TLC8761, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140B - JULY 1997 - REVISED NOVEMBER 1997

PRINCIPLES OF OPERATION
dc considerations (continued)
50

TLC876

REFTF
REFTS

100

I

50 .

--T --I

50

I--

50

I

DAC

REFBS
100

1-

1
50

-

50

1-

ClK

}«

RARRAY

5000

Equivalent)

~

ClK
50

REFBF
50

Figure 17. TLC876 Equivalent Reference Structure

The REFTS and REFBS terminals should not be connected in configurations that do not use a force-sense
reference. Connecting the force and sense lines together allows current to flow in the sense lines. Any current
allowed to flow through these lines must be negligibly small. Current flow causes voltage drops across the
resistance in the sense lines. Because the internal DACs tap different points along the sense lines, each DAC
would receive a slightly different reference voltage if current were flowing in these lines. To avoid this undesirable
condition, leave the sense lines unconnected. Any current allowed to flow through these lines must be negligibly
small « 100 J.LA).
.
The voltage drop across the internal resistor array (RARRAy) determines the input span. The nominal differential
voltage is 2 Vpp. The full-scale input span is given by equation 3.
.
Input Voltage Span

=V(REFTS) -

V(REFBS)

(3)

Therefore, a full-scale input span is approximately 2 V when [V(REFTS) - V(REFBS») = 2 V. The external
reference must provide approximately 4 mA for a 2-V drop across the internal resistor array.
Figure 18 shows the flexibility in determining both the full-scale span of the analog input and where to center
this voltage without degrading the typical performance.

~TEXAS

2-112

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ..

TLC8761, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140B - JULY 1997 - REVISED NOVEMBER 1997

PRINCIPLES OF OPERATION
dc considerations (continued)
5
4.5
4
3.5
III

ILL.

3

W

a:

If
LL.
w

a:

2.5
2
1.5

0.5
0

0

0.5

1.5

2

2.5

3

3.5

4

REFBF, REFBS

Figure 18. TLC876 Reference Ranges
ac considerations
The simplified diagram of Figure 17 shows that the reference terminals connect to a capacitor for one half of
the clock period. The size of the capacitor is a function of the analog input voltage, therefore producing dynamic
impedance changes at the reference inputs.
The external reference source must be able to maintain a low impedance over all frequencies of interest to
provide the charge required by the capacitance. By supplying the requisite charge, the reference voltages
remain relatively constant maintaining specified performance. For some reference configurations, voltage
transients are present on the reference lines, especially during the falling edge of ClK. The reference must
recover from the transients and settle to the desired level of accuracy prior to the rising edges of ClK.
Several useful reference configurations can be used depending on the application, desired level of accuracy,
and cost tradeoffs. The simplest configuration, shown in Figure 19, utilizes a resistor divider to generate the
reference voltages from the converters analog power supply. The 0.1 /-IF bypass capacitors reduce high
frequency transients. The 10 /-IF capacitors reduce the impedances at the REFTF and REFBF terminals at lower
frequencies; however, as input frequencies approach dc, the capacitors become ineffective, and small voltage
deviations appear across the biasing resistors. This reference method maintains 10-bit accuracy for input
frequencies above approximately 200 Hz and a-bit accuracy applications for input frequencies above
approximately 50 Hz.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-113

TLC8761, TLC876C
1a-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140B-JULY 1997 - REVISED NOVEMBER 1997

PRINCIPLES OF OPERATION
ac considerations (continued)
TLC876
NC

REFTS

1400(±1%)
4V

5 V --'\A/v--..---..-----'--'--f-.!REFTF
5000
250 O(± 1%)

2V
REFBF

-=-

REFBS

NC - No connect

Figure 19. Low Cost Reference Circuit
The reference configuration in Figure 19 provides the lowest cost, but the disadvantages include reduced dc
power supply rejection and reduced accuracy due to the variability of the internal and external resistors.
The force-sense reference connections can eliminate the voltage drops associated with the internal
connections to the reference ladder. Figure 20 shows a circuit using a dual, rail-to-rail single-supply operational
amplifier. The operational amplifier should provide stable 3.6 V and 1.6 V reference voltages. Each half of the
amplifier is compensated to drive 1 IlF and 0.1 IlF decoupling capacitors at the REFTF and REFBF terminals
maintaining stability. The operational amplifiers are connected as voltage followers.
By connecting the operational amplifier feedback through the sense connections of the TLC876, the outputs
of the operational amplifiers automatically adjust to compensate for the voltage drops that occur within the
converter.
TLC876
. - - - - - - - - - 4 t - - - - I REFTS

REFT

>--.....--_----1 REFTF,
r------~~--~REFBS

REFB

>----........----1 REFBF

Figure 20. Kelvin Connection Reference Using an Operational Amplifier
with Unlimited Capacitive Load Drive Capability

-!11
TEXAS
INSTRUMENTS
2-114

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC8761, TLC876C
10·BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG·TO·DIGITAL CONVERTERS
SLASI40B- JULY 1997 - REVISED NOVEMBER 1997

PRINCIPLES OF OPERATION
ac considerations (continued)
Figure 21 shows a circuit using a dual operational amplifier with unlimited capacitive load drive. The operational
amplifier should provide stable 3.6 V and 1.6 V reference voltages for REFTF and REFBF, respectively. The
amplifier must be able to maintain stability while driving unlimited capacitive loads, so the 0.1 IlF capacitors C1
and C2 can connect directly to the outputs of the operational amplifiers, which reduces high frequency
transients. Capacitors C3 and C4 shunt across the internal resistors of the force-sense connections and prevent
instability. The stability of any operational amplifier used must be examined closely when driving capacitive
loads.
TLC876
10 kQ

r------.~~r_------------_1RE~S

0.11!F
~~~--'---~------~RE~F

T

0.11!F

10ka
r------.~V0r_------------_1REFBS

T

0.11!F

t This device is 1/2 of a TLV2442. The TLV2442 is a rail·to·rail output dual operational
amplifier.

Figure 21. Kelvin Connection Reference Using an Operational Amplifier
with Unlimited Capacitive Load Drive Capability

~TEXAS

INSTRUMENTS
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2-115

TLC8761, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140B - JULY 1997 - REVISED NOVEMBER 1997

PRINCIPLES OF OPERATION

layout and decoupling
With high-frequency high-resolution converters, the layout and decDupling of the reference is critical. The actual
voltage digitized by the TlC876 is relative to the reference voltages. In Figure 22, for example, the reference
return and the bypass capacitors are connected to the shield of the incoming analog signal. Disturbances in the
ground of the analog input, that are common mode to the REFTF, REFBF, and AIN terminals because of the
common ground, are effectively removed by the TlC876 high common mode rejection. Also, these capacitors
should be connected as close to reference terminals as possible.
High-frequency noise sources, VN1 and VN2, are shunted to ground by decoupling capacitors. Any voltage drops
between the analog input ground and the reference bypassing points are treated as input signals by the
converter using the reference inputs. Consequently, the reference decoupling capacitors should be connected
to the same physical analog ground pOint used by the analog input voltage (see the grounding and layout rules
section).

Figure 22. Recommended Bypassing For The Reference
clock input
The clock input is buffered internally with an inverter powered from the DRVoo terminal, which accommodates
either 5-V or 3.3-V CMOS logic input signal swings with the input threshold for the ClK terminal nominally at
DRVoO/2.
The internal pipelined architecture operates on both rising and falling edges of the input clock. To minimize duty
cycle variations, the recommended logic family to drive the clock input is high-speed or advanced CMOS
(HC/HCT, AC/ACT) logic. CMOS logic provides both symmetrical voltage threshold levels and sufficient rise and
fall times to support 20 MSPS operation.
The power dissipated by the correction logic and output buffers is largely proportional to the clock frequency.
Figure 8 illustrates this tradeoff between clock rates and a reduction in power consumption.

~TEXAS

2-116

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC8761, TLC876C
1a-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140B-JULY 1997 - REVISED NOVEMBER 1997

PRINCIPLES OF OPERATION

digital Inputs and outputs
Each of the digital control inputs, OE and STBY, has an input buffer powered from the DRVoo supply terminal.
With DRVoo set to 5 V, all digital inputs readily interface with 5 V CMOS logic. Using lower voltage CMOS logic,
DRVoo can be set to 3.3 V, lowering the nominal input threshold of all digital inputs to (3.3 V)/2 = 1.65 V, typically.
The digital output format is straight binary. For example, Table 1 shows the output format for voltage levels of
V(REFTS) = 4 V and V(REFBS) = 2 V.
A low power mode feature is provided such that when STBY is high and the clock is disabled, the static power
of the TLC876 drops significantly (see electrical characteristics table).
Table 1. Output Data Format
AINVOLTAGE
(APPROXIMATE)

THREE
STATE

>4V

DATA

08

07

06

05

04

03

02

01

DO

0

09
1

1

1

1

1

1

1

1

1

1

4V

0

1

1

1

1

1

1

1

1

1

1

3V

0

1

0

0

0

0

0

0

0

0

0
0

2V

0

0

0

0

0

0

0

0

0

0

<2V

0

0

0

0

0

0

0

0

0

0

0

X

1

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

grounding and layout rules
Proper grounding and layout techniques are essential for achieving optimal performance. The analog and digital
grounds on the TLC876 have been separated to optimize the management of return currents in a system. A
printed circuit board (PCB) of at least 4 layers employing a ground plane and power planes should be used with
the TLC876. The use of ground and power planes offers distinct advantages:
•

Minimizes the loop area encompassed by a signal and its return path

•

Minimizes the impedance associated with ground and power paths

•

The inherent distributed capacitor formed by the power plane, PCB insulation, and ground plane

These characteristics produce a reduction of electromagnetic interference (EMI) and an overall improvement
in performance.
A properly designed layout prevents noise from coupling onto the input signal. Digital signal traces should not
run parallel with the input Signal traces and should be routed away from the input Circuitry. The separate analog
and digital grounds should be joined together directly under the TLC876. A solid ground plane under the TLC876
is also acceptable if no significant currents are flowing in that portion of the ground plane under the device. The
general rule for mixed signal layouts is that return currents from digital circuitry should not pass through or under
critical analog circuitry. The system design should minimize the analog lead-in to reduce potential noise pickup.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-117

TLC8761, TLC876C
1O-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140B.., JULY 1997 - REVISED NOVEMBER 1997

PRINCIPLES OF OPERATION
digital outputs

The ORVoo supply terminal powers each of the on-chip buffers for the output bits (00-09) and is a separate
lead from AVOO or OVOO' The output drivers are sized to drive a variety of logic families while minimizing the
amount of glitch energy generated. A recommended fan-out of one keeps the capacitive load on the output data
drivers below the specified 20 pF level.
For ORVoo = 5 V, the output signal swing can drive both high-speed CMOS and TTL logic families. For TTL,
the on-chip output drivers are designed to support several of the high-speed TIL families (F, AS, S). For
applications where the clock rate is below 20 MSPS, other TTL families are appropriate. For interfacing with
lower voltage CMOS logic, the TLC876 sustains 20 MSPS operation with ORVoo =3.3 V. Refer to logic family
data sheets for compatibility with the TLC876 digital specifications~

-!!1TEXAS

2-118

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC876M
1O-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG·TO·DIGITAL CONVERTER
•
•
•
•
•
•
•
•
•
•

•

10-Bit Resolution 20 MSPS Sampling
Analog-to-Digital Converter (ADC)
Power Dissipation ... 107 mW Typ
S-V Single Supply Operation
Differential Nonlinearity ••• ±O.S LSB Typ
No Missing Codes
Power Down (Standby) Mode
Three State Outputs
DigitalllOs Compatible With S-V or 3.3-V
Logic
Adjustable Reference Input
28-Termilial Small Outline Package (SOIC)
or 28-Terminal Super Small Outline
Package (SSOP)
Pin Compatible With the Analog
Devices AD876

ORVDD
DO
03
04
06

09

DRGNO
OGNO

AVDD
AIN
CMl
REFBS
REFBF
NC
REFTF
REFTS
OGNO
AGNO
OVDD
STBY
OE
ClK

3:
w

NC - No internal connection

applications
•
•
•

DB OR DW PACKAGE
(TOP VIEW)

Communications
Imaging Systems
High-Speed DSP Front-End ... SMJ320C6x

:>
w
a:

D..

description
The TLC876 is a CMOS, low-power, 10-bit, 20 MSPS analog-to-digital converter (AOC). The speed, resolution,
and single-supply operation are suited for military applications in video, imaging, high-speed acquisition, and
communications. The low-power and single-supply operation satisfy requirements for high-speed portable
applications. The speed and resolution ideally suit charge-coupled device (CCO) input systems such as
electronic still cameras. A multistage pipelined architecture with output error correction logic provides for no
missing codes over the full operating temperature range. Force and sense connections to the reference inputs
provide a more accurate internal reference voltage to the reference resistor string.
A standby mode of operation reduces the power to typically 15 mW. The digital 1/0 interfaces to either 5-V or
3.3-V logic and the digital output terminals can be placed in a high-impedance state. The format of the output
data is straight binary coding.
A pipelined multistaged architecture achieves a high sample rate with low power consumption. The TLC876
distributes the conversion over several smaller AOC sub-blocks, refining the conversion with progressively
higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a
small fraction of the 1023 comparators used in a traditional flash AOC. A sample-and-hold amplifier (SHA) within
each of the stages permits the first stage to operate on a new input sample while the second through the fifth
stages operate on the four preceding samples.
The TLC876M is characterized for operation over the full military temperature range of -55°C to 125°C. The
target release timeframe for the TLC876M is estimated to be during the second half of 1998.

PRODUCT PREVIEW information concerns products in the formative or

=~~caC::aareo~1~~~.e~ascl~~C:.'::~cre!~s;~ rlgo::

change or discontinue these products without notice.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright © 1997, Texas Instruments Incorporated

2-119

ti

:;:)

c

oa:

D..

TLC876M
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTER

SGLS1 05 - DECEMBER 1997

equivalent input and output circuits
Do-D9 OUTPUT CIRCUIT

All DIGITAL INPUT CIRCUITS

AIN INPUT CIRCUIT

DVDD
DVDD

AVDD

DRVDD

~.5PFtYP

AIN
ClK

0.3pF
DRGND

DGND

AGND

DGND

"tJ

:D

oC

REFERENCE INPUT CIRCUIT
AVDD

c:

30 .......'VVI.----,

o-I

REFTF

"tJ

AVDD

:D

m
<
m

Internal Reference
Voltage

-

REFTS 29

:e

AVDD

35

.-'VV\.....-VV'v....

REFBS

Internal Reference
Voltage

AVDD

34

_'VV\~-~

REFBF
AGND

~TEXAS

2-120

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

~

TLC876M
1O-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTER
SGLSI 05 - DECEMBER 1997

AVAILABLE OPTIONS
PACKAGE
SMALL
OUTLINE

TA

-55°C to 125°C

SUPER SMALL

(OW)

OUTLINE
(DB)

TlC876MDW

TlC876MDB

functional block diagram
SHAt

SHAt

SHAt

GAIN

GAIN

SHAt

GAIN

SHAt

GAIN

12
10

3:
w
:;:

(MSB) 09

'--_ _3~ (LSB) DO

w

t Sample and hold amplifier

a:
a..

Terminal Functions
TERMINAL
NAME

AGND

NO.

I/O

1,19

I-

o

DESCRIPTION

::J
Q

Analog ground

oa:

AIN

27

AVDD
ClK

28
15

I

Clock input

CMl

26

0

Bypass for an internal bias point. Typically a 0.1 !IF capacitor minimum is connected from this terminal to ground.

I

Analog input
5-V analog supply

a..

DGND

14,20

DVDD

18

5-V digital supply

DRVDD

2

3.3-V/5-V digital supply. Supply for digital input and output buffers.

DRGND

13

DO-D9

3-12

0

Digital data out. DO:LSB, D9:MSB

OE

16

I

Output enable. When OE = low or NC, the device is in normal operating mode. When OE
impedance.

REFBF

24

I

Reference bottom force

REFBS

25

I

Reference bottom sense

REFTF

22

I

Reference top force

REFTS

21

I

Reference top sense

STBY

17

I

Standby enable. When STBY = low or NC, the device is in normal operating mode. When STBY =high, the device
is in standby mode.
.

Digital ground

3.3-V/5-V digital ground. Ground for digital input and output buffers.

=high, DO-D9 are high

~TEXAS

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2-121

2-122

TLC1541
10·81T ANALOG·TO·DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 INPUTS
•
•

10·Bit Resolution AID Converter
Microprocessor Peripheral or Standalone
Operation

•

On-Chip 12-Channel Analog Multiplexer

•
•

Built-In Self-Test Mode
Software-Controllable Sample-and-Hold
Function

•
•

Total Unadjusted Error ... ±1 LSB Max
Pinout and Control Signals Compatible
With TLC540 and TLC549 Families of 8-Bit
AID Converters

•

ow OR N PACKAGE
(TOP VIEW)
INPUT AO
INPUT AI
INPUT A2
INPUT A3
INPUT A4
INPUTA5
INPUT A6
INPUT A7
INPUT A8
GND

CMOS Technology
PARAMETER

3
4
5

9
11

VCC
SYSTEM CLOCK
I/O CLOCK
ADDRESS INPUT
DATA OUT
CS
REF+
REFINPUT Al0
INPUT A9

VALUE

Channel Acquisition Sample Time
Conversion Time (Max)
Samples Per Second (Max)
Power Dissipation (Max)

5.51ls
21 1ls
32x 103
6mW

description
The TLC1541 is a CMOS AID converter built
around a 10-bit switched-capacitor successiveapproximation AID converter. The device is
designed for serial interface to a microproc~ssor
or peripheral using a 3-state output with up to four
control inputs (including independent SYSTEM
CLOCK, 1/0 CLOCK, chip select [CS], and
ADDRESS INPUT). A 2.1-MHz system clock for
the TLC1541, with a design that includes
simultaneous readlwrite operation, allows highspeed data transfers and sample rates up to
32 258 samples per second. In addition to the
high-speed converter and versatile control logic,
there is an on-chip, 12-channel analog multiplexer
that can be used to sample anyone of 11 inputs
or an internal self-test voltage and a sample-andhold function that operates automatically.

INPUT A3
INPUT A4
INPUT A5
INPUT A6
INPUT A7

4
5
6
7
8

3 2 1 2019

18
17
16
15
14
9 10 11 1213

I/O CLOCK
ADDRESS INPUT
DATA OUT
CS
REF+

AVAILABLE OPTIONS
PACKAGE
SMALL
OUTLINE
(oW)

PLASTIC CHIP
CARRIER
(FN)

(N)

O°C to 70°C

TLC1541COW

TLC1541CFN

TLC1541CN

-40°C to 85°C

TLC1541 lOW

TLC15411FN

TLC1541IN

TA

~TEXAS

INSTRUMENTS
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PLASTIC
DIP

Copyright © 1996, Texas Instruments Incorporated

2-123

TLC1541
1O-SIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996

description (continued)
The converters incorporated in the TLC1541 feature differential high-impedance reference inputs that facilitate
ratiometric conversion, scaling, and analog circuitry isolation from logic and supply noises. A totally
switched-capacitor design allows low-error conversion in 21 ~s over the full operating temperature range.
The TLC1541 is available in OW, FN, and N packages. The C-suffix versions are characterized for operation
from O°C to 70°C. The I-suffix versions are characterized for operation from -40°C to 85°C.

functional block diagram
REF+

REF-

14+

H

-b-

~
~
..!...
...L
ANALOG
INPUTS

.L
l

49
11
12
-=

Sample and
Hold

~

13+

10-8it
Swltched·Capacltors
Analog·to·Dlgital
Converter

12-Channel
Analog
Multiplexer

10

~ Input Address
Register

Output
Data
' Register

I

~

10·to-1 Data
Selector and
Driver

-

~ DATA
OUT

t
4
L-

Y
ADDRESS 17
INPUT

4

Control Logic
and 110
Counters

Self·Test
Reference

I
I

~

Input
Multiplexer

I
I

2

110 CLOCK 18
15
CS
SYSTEM 19
CLOCK

~

typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE

INPUT

INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kOTYP

AO-A10~

I

INPUT

=

Ci 60 pFTYP
(equivalent Input
capacitance)

~TEXAS

2-124

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AO-A10~
~ 5 MOTYP

TLC1541
10·81T ANALOG·TO·DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996

operating sequence
\1

\ 2 \ 3 \ 4 \ 5 \ 6 \ 7 \ 8 \ 9

\1

\10

\ 2 \ 3 \ 4 \ 5 \ 6 \ 7 \ 8 \ 9 \10

1/0

CLOCK--\

r-

I
I I
I+- Access...., I+-- Sample -----1~
I Cycle B I I
Cycle B

I

CS~~)~I______________________~

I
I

MSB

SeeNoleC

Access
Cycle C

I

I

I

~I

Sample

-+I r--- CycieC ~
1_

I

~I______________~r
I
I

LSB

Don'l Care

ADDRESS ~ ~
B3 B2 B1 BO -----------~
INPUT
Don'lCare

DATAJ

OUT~

. - - Previous Conversion Data A - - -••
MSB
LSB MSB
lsee Nole BI

+ - - - - Conversion Data B ------I••
MSB

LSB MSB

NOTES: A. The conversion cycle, which requires 44 system clock periods, initiates on the tenth falling edge of the I/O clock after CS goes low
for the channel whose address exists in memory at that time. When CS is kept low during conversion, the 110 clock must remain
low for at least 44 system clock cycles to allow the conversion to complete.
B. The most significant bit (MSB) is automatically placed on the DATA OUT bus after CS is brought low. The remaining nine bits (A8-AD)
clock out on the first nine 110 clock falling edges.
C. To minimize errors caused by noise at the CS input, the internal circuitry waits for three system clock cycles (or less) after a
chip-select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in
address data until the minimum chip-select setup time elapses.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ........................................................... 6.5 V
Input voltage range, VI (any input) ............................................ -0.3 V to Vee + 0.3 V
Output voltage range, Va ................................................... -0.3 V to Vee + 0.3 V
Peak input current (any input) ............................................................ ± 10 mA
Peak total input current (all inputs) ........ , .. ,"', ........................................ ±30 mA
Operating free-air temperature range, TA: C suffix ....................................... O°C to 70°C
I suffix ...................................... -40°C to 85°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Case temperature for 10 seconds, T e: FN package .......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: DW or N package ........... 260°C

t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to digital ground with REF- and GND wired together (unless otherwise noted).

~TEXAS

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2-125

TLC1541
1O-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996

recommended operating conditions
UNIT

MIN

NOM

MAX

4.75

5

5.5

2.5

VCC+O.1

-0.1

VCC
0

Differential reference voltage, Vref+ - Vref- (see Note 2)

1

VCC

VCC+0.2

V

Analog input voltage (see Note 2)

0

VCC

V

High-level control input voltage, VIH

2

Supply voltage, Vcc
Positive reference voltage, Vref+ (see Note 2)
Negative reference voltage, Vref- (see Note 2)

Low-level control input voltage, VIL
0

Input/output clock frequency, fclock(I/O)
System clock frequency, fclock(SYS}

fclock(l!O}
400

Setup time, address bits before 1/0 CLOCKi, tsu(A}
Hold time, address bits after 1/0 CLOCKi, theA}
Setup time, CS low before clocking in first address bit, tsu(CS)
(see Note 3 and Operating Sequence)

Pulse duration, CS high during conversion, twH(CS) (see Operating Sequence)

2.5

V
V
V

V
0.8

V

1.1

MHz

2.1

MHz
ns

0

ns

3

System
clock
cycles

44

System
clock
cycles

Pulse duration, SYSTEM CLOCK high, twH(SYS}

210

ns

Pulse duration, SYSTEM CLOCK low, twL(SYS}

190

ns

Pulse duration, 1/0 CLOCK high, twH(I/O}

404

ns

Pulse duration, 1/0 CLOCK low, twL(I/O}

404
System

Clock transition time (see Note 4)
1/0
Operating free-air temperature,

TA

ns

fclock(SYS) ,;; 1048 kHz

30

fclock(SYS) > 1048 kHz

20

fclock(I/O) ,;; 525 kHz

100

fclock(l!O} > 525 kl{z

40

Csuffix
I suffix

0

70

-40

85

ns
ns
°C

NOTES: 2. Analog Input voltages greater than that applied to REF + convert as all ones (1111111111), while Input voltages less than that applied
to REF- convert as all zeros (0000000000). For proper operation, REF + voltage must be at least 1 V higher than REF- voltage.
Also, the total unadjusted 9(ror may increase as this differential reference voltage falls below 4.75 V.
3. To minimize errors caused by noise at the, chip select input, the internal circuitry waits for three system clock cycles (or less) after
a dhip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock in
an address until the minimum chip select setup time elapses.
'
4. The amount of time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal room temperature', the devices function with input clock transition time as slow as 2 I!S for remote data acquisition
applications where the sensor and the AID converter are placaQ several feet away from the controlling microprocessor.

~TEXAS

2-126

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC1541
10-81T ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996

electrical characteristics over recommended operating temperature range,
Vee Vref+ 4.75 V to 5.5 V, fclock(1I0) 1.1 MHz, fclock(SYS) 2.1 MHz (unless otherwise noted)

=

=

=

=

PARAMETER

TEST CONDITIONS

TYPt

MAX

High-level output voltage (terminal 16)

Vee = 4.75 V,

10H = 360!1A

VOL

Low-level output voltage

Vee =4.75 V,

10L= 3.2 rnA

High-impedance-state output current

Vo = Vee,

es at Vee

10

10Z

VO=O,

es at Vee

-10

IIH

High-level input current

VI = Vee

IlL

Low-level input current

VI = 0

lee

Operating supply current

Selected channel leakage current

lee + Iref
ei

t

MIN

VOH

Input capacitance

UNIT

V
0.4

V
!1A

0.005

2.5

-0.005

-2.5

I!A

eSatO V

1.2

2.5

mA

Selected channel at Vee,
Unselected channel at 0 V

0.4

1

-0.4

-1

Selected channel at 0 V,
Unselected channel at Vee

Supply and reference current

2.4

es atOV

IlA
1.3

3

[Analog inputs

7

55

I eontrol inputs

5

15

Vref+= Vee,

I!A

mA
pF

All tYPical values are at Vee = 5 V and TA = 25°e.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-127

TLC1541
1O-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996

operating characteristics over recommended operating temperature range,
Vee Vref+ 4.75 V to 5.5 V, fclock(I/O) 1.1 MHz, fclock(SYS) 2.1 MHz

=

=

=

=

MAX

UNIT

EL

Linearity error

See Note 5

±1

LSB

EZS

Zero-scale error

See Notes 2 and 6

±1

LSB

EFS

Full-scale error

See Notes 2 and 6

±1

LSB

ET

Total unadjusted error

See Note 7

±1

LSB

Self-test output code

Input A11 address = 1011 (see Note 8)

PARAMETER

!conv

TEST CONDITIONS

MIN

0111110100
(500)

1000001100
(524)

Conversion time

21

Total access and conversion time

31

J.lS
J.lS

110
Channel acquisition time (sample cycle)

See Operating Sequence

6

clock
cycles

tv

TIme output data remains valid after 1/0
CLOCKt

!el
ten

Delay time, 1/0 CLOCKt to DATA OUT valid

400

ns

Output enable time

150

ns

!elis

Output disable time

150

ns

tr(bus)

Data bus rise time

300

ns

10

See Figure 1

ns

300
ns
tf(bus) Data bus fall time
NOTES: 2. Analog mput voltages greater than that applied to REF+ convert as all ones (1111111111), while Input voltages less than that applied
to REF- convert as all zeros (0000000000). For proper operation, REF + voltage must be at least 1 V higher than REF- voltage.
Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V.
5. Linearity error is the maximum deviation from the best straight line through the AID transfer characteristics.
6. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the
difference between 1111111111 and the converted output for full-scale input voltage.
7. Total unadjusted error includes linearity, zero-scale, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic. The A11 analog input signal is internally generated and
used for test purposes.

~TEXAS

2-128

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1541
10·81T ANALOG·TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996

PARAMETER MEASUREMENT INFORMATION

J

VCC

1.4V

Ien

Output
Under Test

CL
(see Note A)

Output
Under Test

Test
Point

flo
I

CL
(see Note A)

T

+I

Under Test

Point

CL
(see Note A)

3 len

See NoteB

See Note B

LOAD CIRCUIT FOR
!d. t ... AND tf

~ '~m

__

Test
Point

LOAD CIRCUIT FOR
tPZL AND tPLZ

LOAD CIRCUIT FOR
tpZH AND tpHZ

f

VCC

50%

:1 ________
I
I

OV

SYSTEM
CLOCK
_ ______
Output Waveform 1
(see Note C)

I_"'\i

t_P_ZL_~_...
I

See Note B

:
tpZH

~

l

l+-

V
CC

~,-50_%_ _-+-_....f 1~ _ _ _ _ 0 V
I+-- tPHZ
I

j+-

I
Output Waveform 2
(see Note C)

tpLZ

~/"

~----::H

___________....11

50%

VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES

110 CLOCK

O~

\ - - - - - - 0.4V

I
I+-

td

DATAOUT_ _ _ _ _ _

-+I
I

I I

__'X---------=-=-=-= ~:: ~

tr(bus)

--+I I+-

rt--I
I

~

2.4V

- - - 0.4V

I+- tf(bus)

VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES

VOLTAGE WAVEFORMS FOR DELAY TIME

NOTES: A. CL = 50 pF
B. ten = tPZH or tPZL and 'dis = tPHZ or tpLZ'
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

Figure 1. Load Circuits and Voltage Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-129

TLC1541
10·81T ANALOG·TO·DIGITAL CONVERTER
WITH SER1AL CONTROL AND 11 INPUTS
SLAS073C - DECEMBER 1995 - REVI.SED AUGUST 1996

APPLICATION INFORMATION

simplified analog input analysis
Using the equivalent circuit in Figure 2, the time required to charge the analog input capacitance from 0 V to
Vs within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by
Vc

= Vs

(1-e -te/RtCi)

(1 )

where
Rt = Rs + ri
The final voltage to 112 LSB is given by

(2)

Vc (112 LSB) = Vs - (VS/2048)
Equating equation 1 to equation 2 and solving for time (Ie) gives
Vs -(VS/2048) = Vs ( 1-e-te IRtC.)
I

(3)

tc (1/2 LSB) = Rt x Ci x In(2048)

(4)

and

Therefore, with the values given, the time for the analog input signal to settle is
tc (1/2 LSB)

= (Rs + 1 kil) x 55 pF x In(2048)

(5)

This time must be less than the converter sample time shown in the timing diagrams.

I

Driving Sourcet III

I

Rs

I
I

VI

• TLC1541
rj

VS~VC
.
IlkOMAX
.

I
I
I

I

Cj
55pFMAX

VI = Input Voltage at INPUT AO-Al0
Vs = External Driving Source Voltage
Rs = Source Resistance
rj = Input Resistance
Ci = Input CapaCitance

t Driving source requirements:
• Noise and distortion levels for the source must be at least
equivalent to the resolution of the converter.
• Rs must be real at the input frequency.

Figure 2.

Equi~alent

Input Circuit Including the Driving Source

~TEXAS

2-130

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1541
10·81T ANALOG·TO·DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996

PRINCIPLES OF OPERATION
The TLC1541 is a complete data acquisition system on a single chip. The device includes such functions as sample
and hold, 10-bit AID converter, data and control registers, and control logic. For flexibility and access speed, there
are four control inputs: chip select (CS), address input, I/O clock, and system clock. These control inputs and a
TTL-compatible, 3-state output are intended for serial communications with a microprocessor or microcomputer. The
TLC1541 can complete conversions in a maximum of 211ls, while complete input-conversion output cycles can be
repeated at a maximum of 31 Ils.
The system and I/O clocks are normally used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for the device.
Once a clock signal within the specification range is applied to the SYSTEM CLOCK input, the control hardware and
software need only be concerned with addressing the desired analog channel, reading the previous conversion result,
and starting the conversion by using I/O CLOCK. SYSTEM CLOCK drives the conversion-crunching circuitry so that
the control hardware and software need not be concerned with this task.
When CS is high, DATA OUT is in a 3-state condition and ADDRESS INPUT and I/O CLOCK are disabled. This feature
allows each of these terminals, with the exception of the CS terminal, to share a control logic point with its counterpart
terminals on additional AID devices when using additional TLC1541 devices. In this way, the above feature serves
to minimize the required control logic terminals when using multiple AID devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain
the conversion result. A normal control sequence is:
1.

CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits for two
rising edges and then a falling edge of SYSTEM CLOCK after a low CS transition before recognizing the
low transition. This technique protects the device against noise when the device is used in a noisy
environment. The MSB of the previous conversion result automatically appears on DATA OUT.

2.

A new positive-logic multiplexer address shifts in on the first four rising edges of I/O CLOCK. The MSB of
the address shifts in first. The negative edges of these four I/O clock pulses shift out the second, third, fourth,
and fifth most-significant bits of the previous conversion result. The on-chip sample-and-hold begins
sampling the newly addressed analog input after the fourth falling edge. The sampling operation basically
involves the charging of internal capacitors to the level of the analog input voltage.

3.

Five clock cycles are then applied to the I/O CLOCK, and the sixth, seventh, eighth, ninth, and tenth
conversion bits shift out on the negative edges of these clock cycles.

4.

The final tenth-clock cycle is applied to the I/O CLOCK. The falling edge of this clock cycle completes the
analog sampling process and initiates the hold function. Gonversion is then performed during the next 44
system clock cycles. After this final I/O clock cycle, CS must go high or the I/O CLOCK must remain low
for at least 44 system-clock cycles to allow for the conversion function.

CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple
conversion, special care must be exercised to prevent noise glitches on I/O CLOCK. When glitches occur on I/O
CLOCK, the I/O sequence between the microprocessor/controller and the device loses synchronization. Also, when
CS goes high, it must remain high until the end of the conversion. Otherwise, a valid falling edge of CS causes a reset
condition, which aborts the conversion in progress.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through
4 before the 44 system-clock cycles occur. Such action yields the conversion result of the previous conversion and
not the ongoing conversion.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-131

TLC1541
10·BIT ANALOG·TO·DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 INPUTS

SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996

PRINCIPLES OF OPERATION
It is possible to connect SYSTEM CLOCK and 1/0 CLOCK together in special situations in which controlling-circuitry
points must be minimized. In this case, the following special points must be considered in addition to the requirements
of the normal control sequence previously described.
1. This device requires the first two clocks to recognize that CS is at a valid low level when the common clock
signal is used as an I/O CLOCK. When CS is recognized by the device to be at a high level, the common clock
signal is used for the conversion clock also.
2.

A low CS must be recognized before the I/O CLOCK can shift in an analog channel address. The device
recognizes a CS transition when the SYSTEM CLOCK terminal receives two positive edges and then a
negative edge. For this reason, after a CS negative edge, the first two clock cycles do not shift in the address.
Also, upon shifting in the address, CS must be raised after the tenth valid (12 total) I/O CLOCK. Otherwise,
additional common-clock cycles are recognized as I/O CLOCK cycles and shift in an erroneous address.

For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.
This device accommodates these applications. Although the on-chip sample-and-hold begins sampling upon the
negative edge of the fourth valid I/O CLOCK cycle, the hold function does not initiate until the negative edge of the
tenth valid I/O CLOCK cycle. Thus, the control circuitry can leave the I/O CLOCK signal in its high state during the
tenth valid 110 CLOCK cycle until the moment at which the analog signal must be converted. The TLC1541 continues
sampling the analog input until the eighth valid falling edge of the I/O CLOCK. The control circuitry or software then
immediately lowers the I/O CLOCK signal and holds the analog signal at the desired point in time and starts the
conversion.

~TEXAS

2-132

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
•
•
•
•
•

10-Bit Resolution AID Converter
11 Analog Input Channels
Three Built-In Self-Test Modes
Inherent Sample-and-Hold Function
Total Unadjusted Error ... ± 1 LSB Max

•
•
•

On-Chip System Clock
End-of-Conversion (EOC) Output
Terminal Compatible With TLC542

•

CMOS Technology

DB,

J, ow, OR N PACKAGE
(TOP VIEW)

Vee

A1
A2
A3

EOC
I/O CLOCK
ADDRESS
DATA OUT
CS
REF+
REFA10

A4

description
The TLC1542C, TLC15421, TLC1542M, TLC1542Q,
TLC1543C, TLC15431, and TLC1543Q are CMOS
10-bit switched-capacitor successive-approximation
analog-to-digital converters. These devices have three
inputs and a 3-state output [chip select (CS),
input-output clock (110 CLOCK), address input
(ADDRESS), and data output (DATA OUT)] that
provide a direct 4-wire interface to the serial port of a
host processor. These devices allow high-speed data
transfers from the host.
In addition to a high-speed AID converter and versatile
control capability, these devices have an on-chip
14-channel multiplexer that can select anyone of 11
analog inputs or anyone of three internal self-test
voltages. The sample-and-hold function is automatic.
At the end of AID conversion, the end-of-conversion
(EOC) output goes high to indicate that conversion is
complete. The converter incorporated in the devices
features differential high-impedance reference inputs
that facilitate ra!iometric conversion, scaling, and
isolation of analog circuitry from logic and supply noise.
A switched-capacitor design allows low-error conversion over the full operating free-air temperature range.

FK OR FN PACKAGE
(TOP VIEW)

00

~::;( ~~@

A3
A4
A5

AS
A7

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3 2 1 2019
18
17
5
16
6
15
7
14
8
9 10 11 1213

4

exlOOlO

1/0 CLOCK
ADDRESS
DATA OUT
CS
REF+

I

T -J!lTREF-J:>TREF- J~ REF-J:

"j j j"j j j j j j
Figure 1. Simplified Model of the Successive-Approximation System
chip-select operation
The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode.
A high-to-Iow transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device
returns to the initial state (the contents of the output data register remain at the previous conversion result).
Exercise care to prevent CS from being taken low close to completion of conversion because the output data
can be corrupted.

reference voltage inputs
There are two reference inputs used with the device: REF+ and REF-. These voltage values establish the upper
and lower limits of the analog input to produce a full-scale and zero reading respectively. The values of REF +,
REF-, and the analog input should not exceed the positive supply or be lower than GND consistent with the
specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher
than REF + and at zero when the input signal is equal to or lower than REF-.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-139

TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
10-81T ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052D - MARCH 1992 - APRIL 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................. -0.5 V to 6.5 V
Input voltage range, VI ............................ , ......................... -0.3 V to Vee + 0.3 V
Output voltage range, Vo ................................................... -0.3 V to Vee + 0.3 V
Positive reference voltage, Vref+ ...................................................... Vee + 0.1 V
Negative reference voltage, Vref- ................................ ; ......................... -0.1 V
Peak input current (any input) ............................................................ ±20 mA
Peak total input current (all inputs) ........................................................ ±30 mA
Operating free-air temperature range, TA: TLC1542C, TLC1543C ....................... O°C to 70°C
TLC15421, TLC15431 ........................ -40°C to 85°C
TLC15420, TLC15430 ..................... -40°C to 125°C
TLC1542M ............................... -55°C to 125°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds ............................ 260°C

t Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to digital ground with REF- and GND wired together (unless otherwise noted).

recommended operating conditions
Supply voltage, VCC

MIN

NOM

MAX

4.5

5

5.5

Positive reference voltage, Vref+ (see Note 2)
Differential reference voltage. Vref + - Vref- (see Note 2)
Analog input voltage (see Note 2)
High-level control input voltage, VIH

VCC = 4.5 V to 5.5 V

Low-level control input voltage, VIL

VCC = 4.5 V to 5.5 V

Setup time, address bits at data input before I/O CLOCKi, tsu(A) (see Figure 4)

2.5
0

VCC

V
V

VCC
0

Negative reference voltage, Vref- (see Note 2)

UNIT

V
VCC+O.2

V

VCC

V

2

V
0.8

V

100

ns

Hold time, address bits after I/O CLOCKi, theA) (see Figure 4)

0

ns

Hold time, CS low after I/lst I/O CLOCK'!', th(CS) (see Figure 5)

0

ns

1.425

~s

Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3 and Figure 5)
Clock frequency at I/O CLOCK (see Note 4)

0

Pulse duration, I/O CLOCK high, twH(J!O)

190

Pulse duration, I/O CLOCK low, twL(I/Ot

190

Transition time, I/O CLOCK, tt(l/O) (see Note 5 and Figure 6)
Transition time, ADDRESS and CS, tt(CS)
TLC1542C,TLC1543C
Operating free-air temperature, TA

0

2.1

MHz
ns
ns

1

~s

10

~s

70

TLC15421, TLC15431

-40

85

TLC1542Q,TLC1543Q

-40

125

TLC1542M

-55

125

°C

NOTES: 2. Analog Input voltages greater than that applied to REF+ convert as all ones (1111111111), While Input vo~ages less than that applied
to REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref+ - Vref-); however,
the electrical specifications are no longer applicable.
3. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS.!. before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
4. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (~ 2 V) at least 1 I/O CLOCK rising edge (~ 2 V) must occur within
9.5~s.

5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the devices function with input clock transition time as slow as 1 ~s for remote data-acquisition
applications where the sensor and the AID converter are placed several feet away from the controlling microprocessor.

2-140

-!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 555303 • DALLAS, TEXAS 75255

TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
10-81T ANALOG·TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052D - MARCH 1992 - APRIL 1996

electrical characteristics over recommended operating free-air temperature range,
Vee Vref+ 4.5 V to 5.5 V, I/O CLOCK frequency 2.1 MHz (unless otherwise noted)

=

=

=

PARAMETER

VOH

High-level output voltage

VOL

Low-level output voltage

IOZ

v,

IOH =-1.6 rnA

TYPt

MAX

2.4

Vee =4.5 V,

IOL= 1.6 rnA

0.4

Vee = 4.5 V to 5.5 V,

IOL = 20 J.LA

0.1

Off-state
(high-impedance-state)
output current

Va = Vee,

es at Vee

10

es at Vee

-10

VO=O,

IIH

High-level input current

VI=Vee

Low-level input current

VI=O

lee

Operating supply current

eSatOV

Selected channel leakage
current TLe 15421TLe 1543
e,l,orO

Selected channel at Vee,

Unselected channel at 0 V

Selected channel at 0 V,

Unselected channel at Vee

Selected channel at Vee,
TA = 25°e

Unselected channel at 0 V,

Selected channel at 0 V,
TA = 25°e

Unselected channel at Vee,

Selected channel at Vee,

Unselected channel at 0 V

Selected channel at 0 V,

Unselected channel at Vee

Vref+ = Vee,

Vref-= GND

Maximum static analog
reference current into REF +
Input
capacitance

UNIT

V

IOH =-20 J.LA

IlL

ei

MIN

Vee = 4.5 V to 5.5 V,

Selected channel leakage
current TLe1542M

t

TEST CONDITIONS

Vee =4.5

Vee-O.1
V

J.LA

0.005

2.5

-0.005

-2.5

J.LA

0.8

2.5

rnA

J.LA

1
J.LA

I Analog inputs

-1
1
-1

-2.5
10

7

I eontrol inputs

J.LA

2.5

5

J.LA
pF

All typical values are at Vee = 5 V, TA = 25°e.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-141

TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
1O-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052D - MARCH 1992 - APRIL 1996

operating characteristics over recommended operating free-air temperature range,
Vee Vref+ 4.5 V to 5.5 V,IIO CLOCK frequency 2.1 MHz (unless otherwise noted)

=

=

=

TEST CONDITIONS

Linearity error (see Note 6)

EL

Zero-scale error (see Note 7)

EZS

Full-scale error (see Note 7)

EFS

Total unadjusted error (see Note 8)

MIN

MAX

UNIT

±0.5

LSB

TLC1543C, I, or Q

±1

LSB

TLC1542M

±1

LSB

TLC1542C, I, or Q

See Note 2

±1

LSB

TLC1543C, I, or Q

See Note 2

±1

LSB

TLC1542M

See Note 2

±1

LSB

TLC1542C, I, or Q

See Note 2

±1

LSB

TLC1543C, I, or Q

See Note 2

±1

LSB

TLC1542M

See Note 2

±1

LSB

TLC1542C, I, or Q

±1

LSB

TLC1543C, I, or Q

±1

LSB

TLC1542M

±1

LSB

See timing diagrams

21

j.ls

21
+10 I/O
CLOCK
periods

j.lS

ADDRESS = 1011
Self-test output code (see Table 3 and Note 9)

Conversion time

tconv

TYpt

TLC1542C,I, or Q

512

ADDRESS = 1100

0

ADDRESS = 1101

1023

tc

Total cycle time (access, sample, and conversion)

See timing diagrams
and Note 10

tacq

Channel acquisition time (sample)

See timing diagrams
and Note 10

tv

Valid time, DATA OUT remains valid after 1/0 CLOCK,!.

See Figure 6

!d(I/O-DATA)

Delay time, I/O CLOCK,!. to DATA OUT valid

See Figure 6

tdOlO-EOC)

Delay time, tenth 1/0 CLOCK,!. to EOC'!'

See Figure 7

td(EOC-DATA)

Delay time, EOC! to DATA OUT (MSB)

See Figure 8

6

I/O
CLOCK
periods
ns

10

70

240

ns

240

ns

100

ns

t All tYPical values are at TA = 25°C.
NOTES:

2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied
to REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref+ - Vref-); however,
the electrical specifications are no longer applicable.
6. Linearity error is the maximum deviation from the best straight line through the AID transfer characteristics.
7. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the
difference between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
9. Both the input address and the output codes are expressed in positive logic.
10. 1/0 CLOCK period = 1/(1/0 CLOCK frequency) (see Figure 6)

~TEXAS .
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TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
10-81T ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052D - MARCH 1992 - APRIL 1996

operating characteristics over recommended operating free-air temperature range,
Vcc Vref+ 4.5 V to 5.5 V, I/O CLOCK frequency 2.1 MHz (unless otherwise noted) (continued)

=

=

=

TEST CONDITIONS

TYPt

MIN

MAX

UNIT

See Figure 3

1.3

See Figure 3

150

ns

Rise time, EOC

See Figure 8

300

ns

tPZH, tpZL

Enable time, CSJ. to DATA OUT (MSB driven)

tPHZ, tPLZ

Disable time,

tr{EOC)

cst to DATA OUT (high impedance)

~

tf(EOC}

Fall time, EOC

See Figure 7

300

ns

tr(DATA)

Rise time, data bus

See Figure 6

300

ns

tf(DATA}

Fall time, data bus

See Figure 6

300

ns

1ct(I/O-CS)

Delay time, tenth 1/0 CLOCKJ. to CSJ. to abort conversion
(see Note 11)

9

j.1S

t All tYPical values are at TA = 25°C.
NOTE 11. Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock
(1.425 j.1s) after the transition.

PARAMETER MEASUREMENT INFORMATION
Test Point

Test Point

VCC

VCC

DATA OUT -_-4t--..--I4I--_.

EOC

Figure 2. Load Circuits
L...
~

cs

~~~
7:
\-'0.8 V____~2(!

IPZH. tpZL
DATA
OUT

~
I~
~i

ADDRESS

!..~
. .J

=X:~.~V

tpHZ. tpLZ

I"

'\ 90%
-110%

Figure 3. DATA OUT Enable and Disable
Voltage Waveforms

Isu(A)

1/0 CLOCK

~
I

1

0.4 V\.

2.4 V

Address ---.J
Valid -----..,

~

.1 ~
.

':

th(A)

J,

0.8V¥

Figure 4. ADDRESS Setup and Hold Time
Voltage Waveforms

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2-143

TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
10·81T ANALOG·TO·DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052D-MARCH 1992-APRIL 1996

PARAMETER MEASUREMENT INFORMATION

CS \

V

0.8

I

ISU{CS)

~

2r

rr

l

JJ

1/0 CLOCK

0.8, "V"

~l

14

I

Ih{CS)

1

~i

1;-;;:::\
i Flrsl

~ CI~~k \.--s~ ci:~k ~

Figure 5. 110 CLOCK Setup and Hold Time Voltage Waveforms
II{I/O)

I+-- II{I/O)

---.I I+-I 1
1

110 CLOCK
0.8 V

0.8 V

0.8 V

'+-- 1/0 CLOCK Period --.11
.

1

-14-+1 1

tv
DATA OUT

~I

14

"td{I/O-DATA)

~ 10

2.4 V
2.4 V
__~0~.4UV~)\~._~0.4~V~____________

I I
I+- tr{DATA). tf{DATA)

~

Figure 6. 110 CLOCK and DATA OUT Voltage Waveforms

I

1/0 CLOCK ,"

---../

10th \
Clock

0_.8_v_ _ _ _ _ _ __

l I_
Oo. _

1

1d{1I0-EOC) -11~4---~~1
1

2.4V

EOC

"N

0.4V

11;....;..;..;----

tf{EOC) ---.j 14--

Figure 7. 1/0 CLOCK and EOC Voltage Waveforms
~

j4-- tr{EOC)

1

EOC

'

i ,It 2.4 V

~i

14- td(EOC-DATA) -+I

-<10 2.4 V

DATA OUT _ _ _ _ _ _ _ _

\:~_0:::;.4~V:....__ _ __
1

~

ValidMSB-+

Figure 8. EOC and DATA OUT Voltage Waveforms

~1EXAS

2-144

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
10-81T ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052D - MARCH 1992 - APRIL 1996

PARAMETER MEASUREMENT INFORMATION

timing diagrams

'1

cSI
(see Note A)
1/0

,!--------------------------'
I
I

"'1-I

~~~~
I

CLOCK_-+-~

--------~

HI-Z State

DATA
OUT

I

-------------L-S-+B. I

I
I

ADDRESS

B3
MSB
EOC

B2

B1

J~
Initialize

BO
LSB

I

i

I

r-"--....,~
I
I

-~~

-~~
I

rljl

Shift in New Multiplexer Address;
I
I
Simultaneously Shift Out Previous -------------1.~I4f----------.!.1
Conversion Value
AID Conversion
Interval
Initialize

NOTE A: To minimize errors caused by noise at es, the internal circuitry waits for a setup time plus two falling edges of the internal system clock
after esJ, before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
es setup time has elapsed.

Figure 9. Timing for 10-Clock Transfer Using CS

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2-145

TLC1542C, TLC15421, TLC1542M, TLC1542Q, TLC1543C, TLC15431, TLC1543Q
10·BIT ANALOG·TO·DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052D - MARCH 1992 - APRIL 1996

PARAMETER MEASUREMENT INFORMATION

timing diagrams (continued)

cs""'---(see Note A)
I/O
CLOCK

Must be High on Power Up

~\--------------------------------'l()z

The TLC1549C, TLC15491, and TLC1549M
are 1O-bit, switched-capacitor, successiveapproximation
analog-to-digital
converters.
These devices have two digital inputs and a
3-state output [chip select (CS), input-output clock
(1/0 CLOCK), and data output (DATA OUT)] that
provide a three-wire interface to the serial port of
a host processor.

NC
ANALOG IN
NC
REF-

NC

4
5
6
7
8

3 2 1 2019
18
17
16
15
14
9 10 11 1213

NC
I/O CLOCK
NC
DATA OUT
NC

°

o Cl 01C/)
zzzoz
(!)

The sample-and-hold function is automatic. The
converter incorporated in these devices features
differential high-impedance reference inputs that
facilitate ratiometric conversion, scaling, and
isolation of analog circuitry from logiC and supply
noise. A switched-capacitor deSign allows lowerror conversion over the full operating free-air
temperature range.

NC - No internal connection

The TLC 1549C is characterized for operation from DOC to 70°C. The TLC15491 is characterized for operation
from -40°C to 85°C. The TLC1549M is characterized for operation over the full military temperature range of
-55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
TA

SMALL OUTLINE
(D)

O°C to 70°C

TLC1549CD

-40°C to 85°C

TLC15491D

-55°C to 125°C

-

CHIP CARRIER
(FK)

TLC1549MFK

CERAMIC DIP
(JG)

PLASTIC DIP
(P)

-

TLC1549CP

-

TLC15491P

TLC1549MJG

-!II
TEXAS
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-

Copyright © 1995. Texas Instruments Incorporated

2-153

TLC1549C, TLC15491, TLC1549M
10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995

functional block diagram
REF+

I1

REF-

I3

10-8it
Analog-to-Dlgital
Converter
(switched capacitors)
10

ANALOG IN -

2

10

Output
Data
Register

Sample and
Hold

~

10-to-1 Data
Selector and
Driver

-

6
DATA OUT

4

-

1/0 CLOCK
CS

System Clock,
Control Logic,
and 1/0
Counters

t

7

5

Terminal numbers shown are for the D, JG, and P packages only.

typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE

INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 knTYP
ANALOGIN~

ANALOGIN~

I

Ci=60 pFTYP
(equivalent Input
capacitance)

~TEXAS

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INSTRUMENTS
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~ 5 MnTYP

TLC1549C, TLC15491, TLC1549M
10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995

Terminal Functions
TERMINAL
NAME

NO.

1/0

DESCRIPTION

ANALOG IN

2

I

Analog signal input. The driving source impedance should be s 1 kn. The external driving source to ANALOG IN
should have a current capability ~ lOrnA.

CS

5

I

Chip select. A high·to·low transition on CS resets the internal counters and controls and enables DATA OUT and
1/0 CLOCK within a maximum of a setup time plus two falling edges of the internal system clock. A low·to-high
transition disables 110 CLOCK within a setup time plus two falling edges of the internal system clock.

DATA OUT

6

0

This 3-state serial output for the AID conversion result is in the high-impedance state when CS is high and active
when es is low. With a valid chip select, DATA OUT is removed from the high-impedance state and is driven to
the logic level corresponding to the MSB value of the previous conversion result. The next falling edge of 1/0
CLOCK drives DATAOUT to the logic level corresponding to the next most significant bit, and the remaining bits
are shifted out in order with the LSB appearing on the ninth falling edge of 1/0 CLOCK. On the tenth falling edge
of 1/0 CLOCK, DATA OUT is driven to a low logic level so that serial interface data transfers of more than ten clocks
produce zeroes as the unused LSBs.

GND

4

1/0 CLOCK

7

I

Input/output clock. 1/0 CLOCK receives the serial 110 CLOCK input and performs the following three functions:
1) On the third falling edge of 1/0 CLOCK, the analog input voltage begins charging the capacitor array and
continues to do so until the tenth falling edge of 110 CLOCK.
2) It shifts the nine remaining bits of th~e previous conversion data out on DATA OUT.
3) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock.

REF+

1

I

The upper reference voltage value (nominally Vec) is applied to REF+. The maximum input voltage range is
determined by the difference between the voltage applied to REF + and the voltage applied to REF-.

REF-

3

I

The lower reference voltage value (nominally ground) is applied to REF-.

VCC

8

The ground return for internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.

Positive supply voltage

detailed description
With chip select (CS) inactive (high), I/O CLOCK is initially disabled and DATA OUT is in the high impedance
state. When the serial interface takes CS active (low), the conversion sequence begins with the enabling of I/O
CLOCK and the removal of DATA OUT from the high-impedance state. The serial interface then provides the
I/O CLOCK sequence to I/O CLOCK and receives the previous conversion result from DATA OUT. I/O CLOCK
receives an input sequence that is between 10 and 16 clocks long from the host serial interface. The first ten
I/O clocks provide the control timing for sampling the analog input.
There are six basic serial interface timing modes that can be used with the TLC1549. These modes are
determined by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are (1) a
fast mode with a 1O-clock transfer and CS inactive (high) between transfers, (2) a fast mode with a 10-clock
transfer and CS active (low) continuously, (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high)
between transfers, (4) a fast mode with a 16-bit transfer and CS active (low) continuously, (5) a slow mode with
an 11- to 16-clock transfer and CS inactive (high) between transfers, and (6) a slow mode with a 16-clock transfer
and CS active (low) continuously.
The MSB of the previous conversion appears on DATA OUT on the falling edge of CS in mode 1, mode 3, and
mode 5, within 21 IlS from the falling edge of the tenth I/O CLOCK in mode 2 and mode 4, and following the
sixteenth clock falling edge in mode 6. The remaining nine bits are shifted out on the next nine falling edges of
I/O CLOCK. Ten bits of data are transmitted to the host serial interface through DATA OUT. The number of serial
clock pulses used also depends on the mode of operation, but a minimum of ten clock pulses is required for
conversion to begin. On the tenth clock falling edge, the internal logic takes DATA OUT low to ensure that the
remaining bit values are zero if the I/O CLOCK transfer is more than ten clocks long.
Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that
can be used, and the timing on which the MSB of the previous conversion appears at the output.

~TEXAS

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TLC1549C, TLC15491, TLC1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995

detailed description
Table 1. Mode Operation
MODES
. Mode 1
Fast Modes

Slow Modes

. .

NO. OF
110 CLOCKS

CS

Mode 2

Mse AT TermInal st

TIMING
DIAGRAM

High between conversion cycles

10

CS fidling edge

Figure 6

Low continuously

10

Within 21 115

Figure 7

CS falling edge

FigureS

Mode 3

High between conversion cycles

Mode 4

Low continuously

ModeS

High between conversion cycles

Mode 6

Low continuously

11 to 16*
16*
11 to 16*
16*

Within 21 115

Figure 9

CS falling edge

Figure 10

16th clock falling edge

Figure 11

t This timing also initiates serial interface communication .
* No more than 16 clocks should be used.

All the modes require a minimum period of 21 ~s after the falling edge of the tenth 1/0 CLOCK before a new
transfer sequence can begin. During a serial I/O CLOCK data transfer, CS must be active (low) so that 1/0
CLOCK is enabled. When CS is toggled between data transfers (modes 1, 3, and 5), the transitions at CS are
recognized as valid only if the level is maintained for a minimum period of 1.425 ~s after the transition. If the
transfer is more than ten I/O clocks (modes 3, 4, 5, and 6), the rising edge of the eleventh clock must occur within
9.5 ~s after the falling edge of the tenth I/O CLOCK; otherwise, the device could lose synchronization with the
host serial interface and CS has to be toggled to restore proper operation.
fast modes

The TLC1549 is in a fast mode when the serial I/O CLOCK data transfer is completed within 21 ~s from the falling
edge of the tenth 110 CLOCK. With a ten-clock serial transfer, the device can only run in a fast mode.
mode 1: fast mode, CS Inactive (high) between transfers, 10-clock transfer
In this mode, CS is inactive (high) between serial 1/0 CLOCK transfers and each transfer is ten clocks long. The
falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge
of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time.
Also, the rising edge of CS disables I/O CLOCK within a setup time plus two falling edges of the internal system
clock.
mode 2: fast mode, CS active (low) continuously, 10-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After
the initial conversion cycle, CS is held active (low) for subsequent conversions. Within 21 J.1s after the falling
edge of the tenth I/O CLOCK, the MSB of the previous conversion appears at DATA OUT.
mode 3: fast mode, CS Inactive (high) between transfers, 11- to 16-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks
long. The falling edge of CSbegins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables I/O CLOCK within a setup time plus two falling edges of the
internal system clock.
mode 4: fast mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. Within 21 ~s after
the falling edge of the tenth I/O CLOCK, the MSB of the previous conversion appears at DATA OUT.
slow modes

In a slow mode, the serial I/O CLOCK data transfer is completed after 21
I/O CLOCK.

~TEXAS

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~s

from the falling edge of the tenth

TLC1549C, TLC15491, TLC1549M
10·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995

mode 5: slow mode, CS inactive (high) between transfers, 11- to 16-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables I/O CLOCK within a setup time plus two falling edges of the
internal system clock.
mode 6: slow mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of
the sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the
MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next 16
clock transfer initiated by the serial interface.
analog input sampling

Sampling of the analog input starts on the falling edge of the third I/O CLOCK, and sampling continues for seven
I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK.
converter and analog input

The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the Se switch and all Sr switches simultaneously.
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all Sr and Se switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF-)
voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector
looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF-. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-hal! Vee), a bit 0 is placed in the
output register and the 512-weight capacitor is switched to REF-. I! the voltage at the summing node is less
than the trip point of the threshold detector, a bit 1 is placed in the register and this 512-weight capacitor remains
connected to REF + through the remainder of the successive-approximation process. The process is repeated
for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are determined.
With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB.

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TLC1549C, TLC15491, TLC1549M
10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995

Threshold
Detector

51J

OOOEr:.

2SJ

1281

J

To Output
Latches

r 16

r;;r;:;t;:;t~r~r;:;t;:;r

M

T

REF-~.S:EF-~~;EF- ~~REF-~~TREF-~~REF-~.5TREF-~.5TREF-~: REF- ~~

"j j j

\J

j j j j j

Figure 1. Simplified Model of the Successive-Approximation System
chip-select operation
The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode.
A high-to-Iow transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device
returns to the initial state (the contents of the output data register remain at the previous conversion result). Care
should be exercised to prevent CS from being taken low close to completion of conversion because the output
data may be corrupted.

reference voltage inputs
There are two reference inputs used with the TLC1549: REF+ and REF-. These voltage values establish the
upper and lower limits of the analog input to produce a full-scale and zero reading respectively. The values of
REF +, REF-, and the analog input should not exceed the positive supply or be lower than GND consistent with
the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or
higher than REF+ and at zero when the input signal is equal to or lower than REF-.

~TEXAS

2-158

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TLC1549C, TLC15491, TLC1549M
10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995

absolute maximum ratings over operating free·air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1): TLC1549C, TLC15491 ........................ -0.5 V to 6.5 V
TLC1549M ................................... -0.5 V to 6 V
Input voltage range, VI (any input) ............................................ -0.3 V to Vee + 0.3 V
Output voltage range, Vo ................................................... -0.3 V to Vee + 0.3 V
Positive reference voltage, Vref+ ...................................................... Vee + 0.1 V
Negative reference voltage, Vref- .......................................................... -0.1 V
Peak input current (any input) ............................................................ ±20 mA
Peak total input current (all inputs) ........................................................ ±30 mA
Operating free-air temperature range, TA: TLC1549C ................................... O°C to 70°C
TLC15491 ................................. -40°C to 85°C
TLC1549M ............................... -55°C to 125°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from' the case for 10 seconds ............................ 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to ground with REF- and GND wired together (unless otherwise noted).

recommended operating conditions
Supply voltage, VCC

MIN

NOM

MAX

4.5

5

5.5

Positive reference voltage, Vref + (see Note 2)

V

0

Differential reference voltage, Vref+ - Vref- (see Note 2)

2.5

Analog input voltage (see Note 2)

0

High-level control input voltage, VIH

VCC = 4.5 V to 5.5 V

Low-level control input voltage, VIL

VCC = 4.5 V to 5.5 V

Clock frequency at I/O CLOCK (see Note 3)
Hold time, CS low after last I/O CLOCKt, th(CS)

VCC+O.2

V

VCC

V

2
0

Setup time, CS low before first I/O CLOCKt, tsu(CS) (see Note 4)

VCC

V
V

VCC

Negative reference voltage, Vref- (see Note 2)

UNIT

V
0.8

V

2.1

MHz

1.425

I!S

0

ns

Pulse duration, 110 CLOCK high, twH(I/Q)

190

ns

Pulse duration, 110 CLOCK low, twL(I/O)

190

Transition time, I/O CLOCK, tt(l/O) (see Note 5 and Figure 5)
Transition time, CS, tt(CS)
TLC1549C
Operating free-air temperature, TA

a

ns
1

I!S

10

I!S

70

TLC15491

-40

85

TLC1549M

-55

125

°C

NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied
to REF- convert as all zeros (0000000000). The TLC1549 is functional with reference voltages down to 1 V (Vref+ - Vref-); however,
the electrical specifications are no longer applicable.
3. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (~ 2 V) at least 1 1/0 CLOCK rising edge (~ 2 V) must occur within
9.5 !!S.
4. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after cst before responding to the 1/0 CLOCK. No attempt should be made to clock out the data until the minimum CS setup
time has elapsed.
5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the devices function with input clock transition time as slow as 1 I!S for remote data-acquisition
applications where the sensor and the A/ D converter are placed several feet away from the controlling microprocessor.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-159

TLC1549C, TLC15491, TLC1549M
10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS059C - DECEMBER 1992 - REVISED MARCH 1995

electrical characteristics over recommended operating free-air temperature range,
Vee Vref+ 4.5 V to 5.5 V,IIO CLOCK frequency 2.1 MHz (unless otherwise noted)

=

=

=

PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

VOL

low-level output voltage

10Z

Off-state (high-impedance-state) output current

IOH=-1.6 rnA

Vee = 4.5 V to 5.5 V,

10H =

10l = 1.6 rnA

Vec = 4.5 V to 5.5 V,

10l = 20

0.4

I1A

0.1

CSatVcc

10
-10

VI=Vec
VI = 0

ICC

Operating supply current

CSatOV

IlA

0.005

2.5
-2.5

I1A

0.8

2.5

rnA

IlA

1
-1

VI=O
Vref+= Vce,

V

-0.005

VI = Vee

. Maximum static analog reference
current into REF+

UNIT
V

Vec-O.l

CSatVee

low-level input current

Analog input leakage current

MAX

VO=O,

High-level input current

10

Vref-= GND

TlC1549C, I

(Analog)

During sample cycle

30

TlC1549M

(Analog)

During sample cycle

30

TlC1549C, I

(Control)

5

Tle1549M

(Control)

5

t All typical values are at VCC = 5 V, TA = 25'C.

~TEXAS

INSTRUMENTS
2-160

TYpt

2.4

Vo = Vee,

IIH

Input capacitance

-:,!O I1A

Vec=4.5V,

III

Ci

MIN

Vee = 4.5 V,

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

IlA

I1A

55
15

pF

TLC1549C, TLC15491, TLC1549M
10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995

operating characteristics over recommended operating free-air temperature range,
Vee Vref+ 4.5 V to 5.5 V, 1/0 CLOCK frequency 2.1 MHz

=

=

=

PARAMETER

EL

Linearity error (see Note 6)

EZS

Zero-scale error (see Note 7)

EFS

Full-scale error (see Note 7)

TEST CONDITIONS

MIN

MAX

UNIT

±1

LSB

See Note 2

±1

LSB

See Note 2

±1

LSB

±1

LSB

See Figures 6-10

21

~

21
+10110
CLOCK
periods

).1S

Total unadjusted error (see Note 8)
!conv

Conversion time

tc

Total cycle time (access, sample, and conversion)

See Figures 6-10,
See Note 9

tv

Valid time, DATA OUT remains valid after 110 CLOCK.J,

See Figure 5

IeIWO-DATA)
tPZH, tpZL

Delay time, 1/0 CLOCK,!. to DATA OUT valid

See Figure 5

240

ns

Enable time, CS.J, to DATA OUT (MSB driven)

See Figure 3

1.3

~

cst to DATA OUT (high impedance)

10

ns

tPHZ, tPLZ

Disable time,

See Figure 3

180

ns

tr(bus)

Rise time, data bus

See Figure 5

300

ns

tHbus)

Fall time, data bus

See Figure 5

300

ns

1eI(I/O-CS)

Delay time, tenth 1/0 CLOCK,!. to CS'!' to abort conversion
(see Note10)

9

).1S

NOTES: 2. Analog Input voltages greater than that apphed to REF+ convert as all ones (1111111111), while Input voltages less than that apphed
to REF- convert as all zeros (0000000000). The TLC1549 is functional with reference voltages down to 1 V (Vref+ - Vref-); however,
the electrical specifications are no longer applicable.
6. Linearity error is the maximum deviation from the best straight line through the AI D transfer characteristics.
7. Zero error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference
between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero, and full-scale errors.
9. 110 CLOCK period = 1/(1/0 CLOCK frequency). Sampling begins on the falling edge of the third 1/0 CLOCK, continues for seven
1/0 CLOCK periods, and ends on the falling edge of the 10th 1/0 CLOCK (see Figure 5).
10. Any transitions of CS are recognized as valid only if the level is maintained for a minimum of a setup time plus two falling edges of
the internal clock (1 .425 ).1s) after the transition.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-161

TLC1549C, TLC15491, TLC1549M
10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995

PARAMETER MEASUREMENT INFORMATION
Test Point

VCC

DATAOUT---.~~e-~--~

FT

12 lin

CL=100 P

Figure 2. Load Circuit

CS

~L.::::~
\0.8V

/!T:

_ _2..JV

I

I...J
~

tpZH. tpZL ~

1

DATA

2.4 V

f

\

90%

110%

0.4V\

OUT

IPHZ.IPLZ

Figure 3. DATA OUT to Hi-Z Voltage Waveforms

~0.8V
I

cs

2r

r,rj

tsu(CS)~

~

'I

I"

I
110 CLOCK

I
I
.1

____ ;;-;;:-\.

yr---J

~ CI~~k

Figure 4. CS to I/O CLOCK Voltage Waveforms
11(110)

I
I
I

I
I

110 CLOCK

/+-

~

---.I l+0.8 V

It(IIO)

0.8V
: . - - 110 CLOCK Period

Id(IIO·DATA) I"
Iv ---l+-+i
DATA OUT

0.8 V

-.i

.1
1

~2.4

2.4 V{
v
_ _~0~.4~V~~~,_0~.4~V~___________

I I

~

~ Ir(bus).lf(bus)

Figure 5. I/O CLOCK and DATA OUT Voltage Waveforms

~TEXAS

2-162

th(CS)

~I ___ _
Ci~~k ~
1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1549C, TLC15491, TLC1549M
10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995

1-------------------------.. .

CSl

(see Note A)

1
1

1/0
CLOCK

1
I

DATA
OUT

I

r-------~~~
AID

I f - - - - - - - - Previous Conversion Data - - - - - - - -...,144- Conversion
LSB

I

Interval
(S; 21 Ils)

---.11
Initialize

Figure 6. Timing for 10-Clock Transfer Using CS
_~ Must Be High on Power Up

CS

(see Note A)

------------------------------~~r_____

)

110

1

CLOCK~

L....-._ _ _......

-----~

1

DATA~ A9

Low Level

OUTN

14

1

MSB

~

See Note C

--------~I-

1

-.I

~

AID Conversion
Interval
1
(S; 21 Ils)
Initialize

Initialize

Figure 7. Timing for 10-Clock Transfer Not Using CS
See Note B

'r,Ir----

CS!

111111111)

(see Note A)f

110

r~

1
1

CLOCK

1

DATA
OUT

Low
Level

1

~""7"'H7i._Z-r'l~
1
1--Al""D"'-'-.6 I
114"-------- Previous Conversion Data - - - - - - - -..~1441_ Conversion -.I

1 MSB
Initialize

LSB

Interval
I
(s; 21 1lS) Initialize

Figure 8. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed Within 21

~s)

NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS.j. before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup
time has elapsed.
B. A low-to-high transition of CS disables I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system
clock.
C. The first I/O CLOCK must occur after the end of the previous conversion.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-163

TLC1549C, TLC15491, TLC1549M
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995

_ ~ Must Be High on Power Up
CS
,
j
(see Note A)
I/O

tl

11

-h
1

CLOCK

1

Jr

DATA
OUT

~

A9

rB9V

Low Level

'---------'l~...

1

1

1~4-M-SB------ Previous Conversion Data ------L-S-B~t1.4-

1
Initialize

I

AID Conversion
Interval
---+1
(~21 ¢I)
Initialize

Figure 9. Timing for 16·Clock Transfer Not Using CS (Serial Transfer Completed Within 21 J..ls)

111111111

CS --,
(see Note A)

1

1
1/0

'j~,---_

1

11

CLOCK-I_-'

1

1[161~
-'
L.

See Note B

I

1

1

1

t-..!I-::-v

Low 1 Hi-Z State
Level
~

DATA
OUT
MSB

Previous Conversion Data

I

-------LS-S-+..!.- AID

1

Conversion
Interval
(~ 21 115)

Initialize

1

-..I

1

1
1
Initialize

Figure 10. Timing for 11· to 16·Clock Transfer Using CS (Serial Transfer Completed After 21 J..ls)
_ ~ Must Be High on Power Up
CS
"
j
(see Note A)
I/O

f(

I}

~r-Pl

1

CLOCK-f,

See Note B

1

See Note C

DATAJr A9

OUT~

1r44-M-S-B----1

AID Conversion Interval
(~21 J.1s)

1

Initialize

Figure 11. Timing for 16·Clock Transfer Not Using CS (Serial Transfer Completed After 21 J..ls)
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two failing edges of the internal system
clock aiter CS.j, before responding to the I/O CLOCK. No attempt should be made to clock oul the·data until the minimum CS setup
time has elapsed.
B. A low-to-high transition of CS disables I/O CLOCK within a maximum of a setup time plus two failing edges of the internal system
clock.
C. The first I/O CLOCK must occur after the end of the previous conversion.

~TEXAS

2-164

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC1549C, TLC15491, TLC1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995

APPLICATION INFORMATION
1111111111

I

I

See Notes A and B

/

1111111110

~ 1L \!.
)~V /1I

1111111101

CD

'8

(.)

••
•

A~

1000000001

~

'5
a.
'5 1000000000

~

VZT =VZS + 1/2 LSB

/'

0111111111

/

••
•

VZS

/

0000000010
0000000001
0000000000

1023
1022
1021

••
•

VFS

0

~

~V

1/

/1 V~

v,;;

/'

I

VFT = VFS -1/2 LSB

V

§0.0048

513

I
I

512

Ii

~V

V

••
•

I

/' ./'

./1'/ . .

I

2

I
I

/

0.0096

•••

ci

2.4528

2.4576

•••

2.4624

VI- Analog Input Voltage - V

I

4.9056

a.

CD

iii

511

I
I

li{/
o

!

o

~ 4.9104 4.9152

...O!

NOTES: A. This curve is based on the assumption that Vref+ and Vref- have been adjusted so that the voltage at the transition from digital 0
to 1 (VZT) is 0.0024 V and the transition to full scale (VFT) is 4.908 V. 1 LSB = 4.8 mY.
B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is
the step whose nominal midstep value equals zero.

Figure 12. Ideal Conversion Characteristics

TLC1549
Analog Input

CS

ANALOG IN

110 CLOCK
Processor

Control
Circuit

DATA OUT

5-V DC Regulated

REF+

r--+-

REFGND

To Source
Ground

...

-

~

l
Figure 13. Typical Serial Interface

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-165

TLC1549C, TLC15491, TLC1549M
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C - DECEMBER 1992 - REVISED MARCH 1995

APPLICATION INFORMATION

simplified analog input analysis
Using the equivalent circuit in Figure 14, the time required to charge the analog input capacitance from 0 V to
Vs within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by
(1 )
where
Rt

=Rs + rj

The final voltage to 1/2 LSB is given by
Vc (1/2 LSB) = Vs - (Vs/2048)

(2)

Equating equation 1 to equation 2 and solving for time

tc gives

Vs - (VS/2048) = VS(1-e-tc/RtCi)

(3)

and
tc (1/2 LSB)

= Rt x Cj x In(2048)

(4)

Therefore, with the values given the time for the analog input signal to settle is
to (1/2 LSB) '" (Rs + 1 kO) x 60 pF x in(204S)

(5)

This time must be less than the converter sample time shown in the timing diagrams.
Driving Sourcet 4
Rs

I
I
I
I

~ TLC1549

VI

ri

VS~VC

!

1knMAX

I.

I

~

T

rh

CI
50pFMAX

VI = Input Voltage at ANALOG IN
VS= External Driving Source Voltage
Rs = Source Resistance
ri = Input Resistance
Ci = Input Capacitance

t Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.

Figure 14. Equivalent Input Circuit Including the Driving Source

~ThXAS

2-166

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC15501, TLC1550M, TLC15511
10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
MARCH 1995

•
•

Jt OR NW PACKAGE

Power Dissipation ... 40 mW Max
Advanced LinEPICTM Single-Poly Process
Provides Close Capacitor Matching for
Better Accuracy

•

Fast Parallel Processing for DSP and J..lP
Interface

•

Either External or Internal Clock Can Be
Used

•
•

Conversion Time ... 6 J..lS
Total Unadjusted Error. .. ±1 LSB Max

•

CMOS Technology

(TOP VIEW)

REF+
REFANLG GNO
AIN
ANLG VDD
OGTLGN01
OGTLGN02
OGTL VDD1
OGTL VDD2
EOC
00
01

description
The TLC1550x and TLC1551 are data acquisition
analog-to-digital converters (ADCs) using a 10-bit,
switched-capacitor,
successive-approximation
network. A high-speed, 3-state parallel port directly
interfaces to a digital signal processor (DSP) or
microprocessor (J..lP) system data bus. DO through
09 are the digital output terminals with DO being the
least significant bit (lSB). Separate power
terminals for the analog and digital portions
minimize noise pickup in the supply leads.
Additionally, the digital power is divided into two
parts to separate the lower current logic from the
higher current bus drivers. An external clock can be
applied to ClKIN to override the internal system
clock if desired.

t

RO
WR
CLKIN
CS
09
08
07
06
05
04
03
02

Refer to the mechanical data for the JW
package.

o
z

FK OR FN PACKAGE
(TOP VIEW)

~

~

~

+

I

z! tt tt 0 10 Ig; ~
«OCOCZOC>O

The TlC15501 and TlC15511 are characterized for
operation from -40°C to 85°C. The TlC1550M is
characterized over the full military range of -55°C
to 125°C.

4

3 2 1 28 27 26

AIN

5

ANLG VDD
OGTLGN01
NC
OGTLGN02
OGTL VDD1
OGTL VDD2

6

24

7

23

8

22

25

9

21

10

20

11

19

CS
09
08
NC
07
06
05

12 1314 15 16 1718

0 a

1

~

0

C\I

"'"*

TLC15511

See Note 5

ta(D)

Data access time after RD goes low
Data valid time after RD goes high

idis(D)

Disable time, delay time from RD high to high
impedance

Id(EOC)

Delay time, RD low to EOC high

UNIT

±0.5
±1

25°C

±0.5

Full range

±1

Full range

±0.5

Full range

±1

25°C

±0.5

Full range

±1

Full range

±0.5

Full range

±1

25°C

±0.5

Full range

±1

Full range

±0.5

Full range

±1

25°C

±1

fclock(external) =4.2 MHz or
internal clock

tvlDl

MAX

Full range

TLC1550M
!conv

MIN

Full range

LSB

LSB

LSB

6

I1S

35

ns

5

ns

See Figure 3

30
0

LSB

15

ns
ns

t Full range IS -40°C to 85°C for the TL 155xI devices and -55°C to 125°C for the TLC1550M.
All typical values are at VDD = 5 V, TA = 25°C.
NOTES: 2. Analog input voltages greater than that applied to REF+ convert to all1s (1111111111), while input voltages less than that applied
to REF- convert to all Os (0000000000). The total unadjusted error may increase as this differential voltage falls below 4.75 V.
3. Linearity error is the difference between the actual analog value at the transition between any two adjacent steps and its ideal value
after zero-scale error and full-scale error have been removed.
4. Zero-scale error is the difference between the actual mid-step value and the nominal mid-step value at specified zero scale.
Full-scale error is the difference between the actual mid-step value and the nominal mid-step value at specified full scale.
5. Total unadjusted error is the difference between the actual analog value at the transition between any two adjacent steps and its
ideal value. It includes contributions from zero-scale error, full-scale error, and linearity error.

=1=

PARAMETER MEASUREMENT INFORMATION

See Note A
Output
Under Test

Vcp= 1 V

J;

CL=62pF
Sink Current

=6 mA

Vcp = voltage commutation point for switching between source and sink currents

NOTE A: Equivalent load circuit of the Teradyne A500 tester for timing parameter measurement

Figure 1. Test Load Circuit

~1EXAS

2-172

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC15501, TLC1550M, TLC1551I
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
SLAS043C - MAY 1991 - REVISED MARCH 1995

APPLICATION INFORMATION

simplified analog input analysis
Using the circuit in Figure 2, the time required to charge the analog input capacitance from 0 to Vs within 1/2
LSB can be derived as follows:
The capacitance charging voltage is given by
(1 )

where
Rt

= Rs + q

The final voltage to 1/2 LSB is given by
Vc (1/2 LSB)

= Vs -

(2)

(VS/1 024)

Equating equation 1 to equation 2 and solving for time tc gives
Vs - (VS/512)

= Vs(1_e-tc/RtCi)

(3)

and

(4)

tc (1/2 LSB) = Rt x Cj x In(1024)
Therefore, with the values given, the time for the analog input signal to settle is
tc (1/2 LSB)

= (Rs + 1 kll) x 60 pF x In(1 024)

(5)

This time must be less than the converter sample time shown in the timing diagrams.

I

Driving Sourcet ..

I

Rs

• TLC1550!1

I
I

VI

ri

VS~VC

!

1 kQ MAX

I
I

-.l
T
rh

CI
50pFMAX

VI = Input voltage at AIN
Vs = External driving source voltage
Rs Source resistance
rr = Input resistance
Ci Input capacitance

=
=

t Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.

Figure 2. Input Circuit Including the Driving Source

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-173

TLC15501, TLC1550M, TLC1551I
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
SLAS043C - MAY 1991 - REVISED MARCH 1995

PRINCIPLES OF OPERATION
The operating sequence for complete data acquisition is shown in Figure 3. Processors can address the TLC1550
and TLC1551 as an external memory device by simply connecting the address lines to a decoder and the decoder
output to CS. Like other peripheral devices, the write (WR) and read (RD) input signals are valid only when CS is low.
Once CS is low, the on-board system clock permits the conversion to begin with a simple write command and the
converted data to be presented to the data bus with a simple read command. The device remains in a sampling (track)
mode from the rising edge of EOC until conversion begins with the rising edge of WR, which initiates the hold mode.
After the hold mode begins, the clock controls the conversion automatically. When the conversion is complete, the
end-of-conversion (EOC) signal goes low indicating that the digital data has been transferred to the output latch.
Lowering CS and RD then resets EOC and transfers the data to the data bus for the processor read cycle.

~
I I

cs

--:::x i
I

tsu(CS)

~ th(CS)
1 1

i Yo.8

V

1

Ij.,

1

~ tw(WR) ---+i 114-,.-- tconv ---·~i

_ _--.11

1ci~VX

/a.8V

\ - 0.8 V

I..

ft.H

1
1

I
I
I

i4-f-

~

I

tsu(CS)

1

--------------------------~:----~
:
00-09

EOC

0.8V

----r:

-------------------.j.:

-«

tV(O)~

~.X

~ tdls(O)

V Data Valid .

o.~~ )>-----

1
j+- td(EOC) -.I
\1"",1__________-'!~~2~V------------

0.8V'l

Figure 3. TLC1550 or TLC1551 Operating Sequence

~TEXAS

2-174

j4- th(CS)

2Jf~1-------

T

taCO) ~

I
I
I
I

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

.

TLC2543C, TLC25431, TLC2543M
12-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SlAS079D - DECEMBER 1993 - REVISED MAY 1997

•
•
•
•
•
•
•
•
•

•
•
•
•
•

DB, ow, J, OR N PACKAGE
(TOP VIEW)

12-Bit-Resolution A/D Converter
10-).!S Conversion Time Over Operating
Temperature
11 Analog Input Channels
3 Built-In Self-Test Modes
Inherent Sample-and-Hold Function
Linearity Error ... ± 1 LSB Max
On-Chip System Clock
End-of-Conversion Output
Unipolar or Bipolar Output Operation
(Signed Binary With Respect to 1/2 the
Applied Voltage Reference)
Programmable MSB or LSB First
Programmable Power Down
Programmable Output Data Length
CMOS Technology
Application Report Availablet

description
The TLC2543C and TLC25431 are 12-bit, switchedcapacitor, successive-approximation, analog-todigital converters. Each device has three control
inputs [chip select (CS), the input-output clock (I/O
CLOCK), and the address input (DATA INPUT)] and
is designed for communication with the serial port of
a host processor or peripheral through a serial 3-state
output. The device allows high-speed data transfers
from the host.

AI NO

Vcc

1

AIN1

EOC

AIN2

I/O CLOCK

AIN4
AIN5
AIN6

7

AIN8

9

17

DATA INPUT

16
15
14

DATA OUT
CS
REF+
REFAIN10

GND

FK OR FN PACKAGE
(TOP VIEW)

~ ~ ~ 88
«««>w
AIN3

4

AIN4

5
6
7

AIN5
AIN6
AIN7

3 2 1 2019
18
17
16

15
14
8
9 10 11 1213

I/O CLOCK
DATA INPUT
DATA OUT
CS
REF+

000"'°1
~Z~Zu..
«(!J«1J---'\I\J'\r---t AINO-AIN10
VI-----t
C1

C3
470pF

10 ~F

son
-1SV
LOCATION

DESCRIPTION

PART NUMBER

-

U1

OP27

Cl
C2
C3

10-~F

-

35-V tantalum capacitor
O.I-~F ceramic NPO SMD capacitor
470-pF porcelain Hi-Q SMD capacitor

AVX 121 05Cl 04KAI 05 or equivalent
Johanson 201 S420471JG4L or equivalent

Figure 1. Analog Input Buffer to Analog Inputs AINO-AIN10
Test Point

Test Point

VCC

VCC

~=~8~

EOC

~=~8~

DATA OUT-__.---4J--._1e--..

CL=100pF

-=

I

12~

-=
Figure 2. Load Circuits

!.CS

~~
______2JVT.11
\O.8V
/!

tpZH. tpZL

-l..--..t
1-i

DATA INPUT

!....J
~

tPHZ.tpLZ

DATA

2.4 V ;-

\

OUT

0.4 V \;

.j 10%

90%

==>< ~.~

110 CLOCK

~TEXAS

V

1

r

:X::==

I~";"""---I-I

tsu(A)

Figure 3. DATA OUT to Hi-Z Voltage Waveforms

--.1

Data
Valid

1

~

.!

th(A)

0.8VY

Figure 4. DATA INPUT and I/O CLOCK
Voltage Waveforms

.

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS ,75265

2-181

TLC2543C, TLC25431,.TLC2543M
12·81T ANALOG·TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D,. DECEMBER 1993 - REVISED MAY 1997

PARAMETER MEASUREMENT INFORMATION
\ . 0.8V

CS

2r

II

~,)j

1/0 CLOCK

.1
;-;::;\1 ... -

1

r-j

Isu(CS)

14

..... i r - \

~

I

Ih(CS)
•• \

~~Ci~~k~

NOTE A: To ensure full conversion acciJracy, it is recommended that no input signal change
occurs while a conversion is ongoing.

Figure 5. CS and 1/0 CLOCK Voltage Waveforms
11(1/0)

1"--

---.II 1..-- ~
I
I

1/0 CLOCK

0.8 V

11(110)

1
1

0.8 V

~ 1/0 CLOCK Period

0.8 V

4

td(I/O.DATA) ~
Iv -----l4-+1 I

2.4 V

DATA OUT

{~ 2.4 V

~0~.4~V~~~._~0.~4~V.............................

........

I I

-+j

.

r

tr(bus).lf(bus)

Figure 6. 1/0 CLOCK and DATA OUT Voltage Waveforms

1/0 CLOCK

/
--.-/

Last \
Clock

td(I/O·EOC)

~0;.;...8..;.V_ _................

110.._

~~I-----...I

N·

...................................~

2.4V

EOC

1

1

0.4 V

I;"';';';~"'"

i"-

t'(EOC) - . :

Figure 7. 1/0 CLOCK and EOC Voltage Waveforms

~ ~
EOC

1 J.
m..Y!

tr(EOC)

2.4V

i~

I

.(1
-<.

DATA OUT ...._ _ _ _ _ _ _

td(EOC.DATA)

2.4 V
~0.~4~V

_ _ __

:.- Valid MSB

~

Figure 8. EOC and DATA OUT Voltage Waveforms

~TEXAS

2-182

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2543C, TLC25431, TLC2543M
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D - DECEMBER 1993 - REVISED MAY 1997

PARAMETER MEASUREMENT INFORMATION

11----

Clli

11--------------------""'S~Ir-------'

(see Note A)

1
1

1/0

1

J11l-Fl f%W/M4-fi

CLOCK_-+...-o!

------~~I

1

~ Jr-::-\t
HI.ZState

DATA
OUT

A1

~

AO

1

1

--------------L-S-B~~

1

-~~

___ ...JI

DATA
INPUT
B7

B6

B5

MSB

B4

B3

B2

B1

BO

1
1

LSB

~

EOCJ

_~~

~

C7

r"l

II

\\
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value

1
1

Ir;:: toonv ~
1l1li

~I

AID Conversion

Initialize
Interval
Initialize
NOTE A: To minimize errors caused by noise at es, the internal circuitry waits for a setup time aiter es,J, before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum es setup time has elapsed.

Figure 9. Timing for 12·Clock Transfer Using CS With MSB First

cst
(see Nme A)

II---------------------~~\~\--------------'l~r_____
1

110
1
CLOCK ~_-!
1

DATA
OUT

1
1

1

I

--------L-SB-+~I

DATA
INPUT
B7

B6

B5

MSB
EOC

B4

B3

B2

B1

BO

LSB

---~

Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value

r;::.:..A

~

1

1

~--------------------------~~--__hl
II
14--------------

~

Low Level

Ur----r'

11------1
1 I+-- toonv -----+I

-----------I~~TI4--------------+I

Initialize

AID Conversion
Interval

Initialize

NOTE A: To minimize errors caused by noise at es, the internal circuitry wails for a setup time aiter es,J, before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum es setup time has elapsed.

Figure 10. Timing for 12-Clock Transfer Not Using CS With MSB First

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-183

TLC2543C, TLC25431, TLC2543M
12-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D - DECEMBER 1993 - REVISED MAY 1997

PARAMETER MEASUREMENT INFORMATION
CS
(~NoteA)

lr----------'

110 CLOCK
1
1

r-_ _...;H.;;.I•.;;;Z~~

DATA OUT

1
1

DATA INPUT
B7

B6

MSB
EOC

B5

B4

B3

B2

Bl

'"I''''--'J...

BO

LSB

-~~
:L-_...,

1

,

M~,I-----

II

.

C7

1

~------------~----~I

J~~

1

1'-'

Shift In New Multiplexer Address,
1 j4-- teonv ----.!
Simultaneously Shift Out Previous ----t~Ii 1 + - - - - - - - - - + 1
Conversion Value

Initialize

Initialize

NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time aiter CSJ. before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.

Figure 13. Timing for 16·Clock Transfer Using CS With MSB First

csl

(see Note A)
I/O
CLOCK

11----------.....---------....1',1',.\-------------1')11-"- - 1
1

1

~----L-O-w-L-e-v-el--.J~:

DATA
OUT

LSB 1

1

~

1

1

87

B6

B5

B4

B3

82

B1

--t--

BO

IMSB

~~

LSB
1
~I~--________________________~(,\~----~I

EO:J'~

r-

)

r

--------..:1
DATA
INPUT

815

1
IM,I-____

II

I '
---+I

Shift in New Multiplexer Address,
1 J4-- tconv
Simultaneously Shift Out Previous - - - - - -...,...141--------~.1
Conversion Value
AID Conversion

Initialize

Interval

NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time aiter CSJ. before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.

Figure 14. Timing for 16·Clock Transfer Not Using CS With MSB First

~TEXAS

.

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-185

TLC2543C, TLC25431, TLC2543M
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D~DECEMBER

1993 - REVISED MAY 1997

PRINCIPLES OF OPERATION
Initially, with chip select (CS) high, 1/0 CLOCK and DATA INPUT are disabled and DATA OUT is in the
high-impedance state. CS going low begins the conversion sequence by enabling 1/0 CLOCK and DATA INPUT
and removes DATA OUT from the high-impedance state.
The input data is an 8-bit data stream consisting of a 4-bit analog channel address (D7-D4), a 2-bit data length
select (D3-D2), an output MSB or LSB first bit (D1), and a unipolar or bipolar output select bit (DO) that are
applied to DATA INPUT. The 1/0 CLOCK sequence applied to the 1/0 CLOCK terminal transfers this data to the
input data register.
During this transfer, the 1/0 CLOCK sequence also shifts the previous conversion result from the output data
register to DATA OUT. 1/0 CLOCK receives the input sequence of 8, 12, or 16 clock cycles long depending on
the data-length selection in the input data register. Sampling of the analog input begins on the fourth falling edge
of the input 1/0 CLOCK sequence and is held after the last falling edge of the 1/0 CLOCK sequence. The last
falling edge of the I/O CLOCK sequence also takes EOC low and begins the conversion.

converter operation
The operation of the converter is organized as a succession of two distinct cycles: 1) the I/O cycle and 2) the
actual conversion cycle.

110 cycle
The 1/0 cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods, depending
on the selected output data length.
During the I/O cycle, the following two operations take place simultaneously.
An S-bit data stream consisting of address and control information is provided to DATA INPUT. This data is
shifted into the device on the rising edge of the first eight I/O CLOCKs. DATA INPUT is ignored after the first
eight clocks during 1.2- or 16-clock I/O transfers.
The data output, with a length of 8, 12, or 16 bits, is provided serially on DATA OUT. When CS is held low, the
first output data bit occurs on the rising edge of EOC. When CS is negated between conversions, the first output
data bit occurs on the falling edge of CS. This data is the result of the previous conversion period, and after the
first output data bit, each succeeding bit is clocked out on the falling edge of each succeeding I/O CLOCK.

conversion cycle
The conversion cycle is transparent to the user, and it is controlled by an internal clock synchronized to
I/O CLOCK. During the conversion period, the device performs a successive-approximation conversion on the
analog input voltage. The EOC output goes low at the start of the conversion cycle and goes high when
conversion is complete and the output data register is latched. A conversion cycle is started only after the I/O
cycle is completed, which minimizes the influence of external digital noise on the accuracy of the conversion.

~TEXAS .....
INSTRUMENTS .
2-186

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2543C, TLC25431, TLC2543M
12·81T ANALOG·lO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D - DECEMBER 1993 - REVISED MAY 1997

PRINCIPLES OF OPERATION
power up and initialization
After power up, CS must be taken from high to low to begin an I/O cycle. EOC is initially high, and the input data
register is set to all zeroes. The contents of the output data register are random, and the first conversion result
should be ignored. To initialize during operation, CS is taken high and is then returned low to begin the next I/O
cycle. The first conversion after the device has returned from the power-down state may not read accurately
due to internal device settling.

Table 1. Operational Terminology
Current (N) 1/0 cycle

The entire 1/0 CLOCK sequence that transfers address and control data into the data register and clocks
the digital result from the previous conversion from DATA OUT

Current (N) conversion cycle

The conversion cycle starts immediately after the current I/O cycle. The end of the current 1/0 cycle is the
last clock falling edge in the 1/0 CLOCK sequence. The current conversion result is loaded into the output
register when conversion is complete.

Current (N) conversion result

The current conversion result is serially shifted out on the next 1/0 cycle.

Previous (N-1) conversion cycle

The conversion cycle just prior to the current 1/0 cycle

Next (N+ 1) 1/0 cycle

The 1/0 period that follows the current conversion cycle

Example: In the 12-bitmode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during
the next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even
when this corrupts the output data from the previous conversion. The current conversion is begun
immediately after the twelfth falling edge of the current I/O cycle.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265

2-187

TLC2543C, TLC25431, TLC2543M
12-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D - DECEMBER 1993 - REVISED MAY 1997

PRINCIPLES OF OPERATION
data input
The data input is internally connected to an 8-bit sed ai-input address and control register. The register defines
the operatiori of the converter and the output data length. The host provides the data word with the MSB first.
Each data bit is clocked in on the rising edge of the lID CLOCK sequence (see Table 2 for the data input-register
format).

Table 2. Input-Register Format
INPUT DATA BYTE
ADDRESS BITS

FUNCTION SELECT

Select input channel
AI NO
AINI
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
Select test voltage
(Vref+ - Vref-)/2
VrefVref+
Software power down

D7
(MSB)

D6

D5

D4

0
0
0
0
0
0
0
0
1
1
1

0
0
0
0
1
1
1
1
0
0
0

0
0

0

1
1
0
0
1
1
0
0
1

0
1
0
1
0
1
0
1
0

1
1
1

0
1
1

1
0
0

1
0
1

1

1

1

0

LO

LSBF

BIP

D2

Dl

DO
(LSB)

1

Output data length
8 bits
12 bits
16 bits

0

Output data format
MSBfirst
LSB first (LSBF)

t

L1
D3

1

xt

b

1

1

.

0
1

Unipolar (binary)

0

Bipolar (BIP) 2s complement

1

X represents a do not care condition.

data input address bits
The four MSBs (07 - 04) of the data register address one of the 11 input channels, a reference-test voltage,
or the power-down mode. The address bits affect the current conversion, which is the conversion that
immediately follows the current lID cycle. The reference voltage is nominally equal to Vref+ - Vref-.

~ThxAs

INSTRUMENTS
2-188

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2543C, TLC25431, TLC2543M
12·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D - DECEMBER 1993 - REVISED MAY 1997

PRINCIPLES OF OPERATION
data output length

The next two bits (D3 and D2) of the data register select the output data length. The data-length selection is
valid for the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the
current 1/0 cycle, allows device startup without losing I/O synchronization. A data length of 8, 12, or 16 bits can
be selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.
With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current
conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be exactly
12 bits long for proper synchronization, even when this means corrupting the output data from a previous
conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.
With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication
with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial
data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must
be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the
previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current
I/O cycle.
With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit
serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream
during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even
when this means corrupting the output data from the previous conversion. The four LSBs of the conversion
result are truncated and discarded. The current conversion is started immediately after the eighth falling edge
of the current I/O cycle.
Since D3 and D2 take effect on the current I/O cycle when the data length is programmed, there can be a conflict
with the previous cycle when the data-word length is changed from one cycle to the next. This may occur when
the data format is selected to be least significant bit first, since at the time the data length change becomes
effective (six rising edges of I/O CLOCK), the previous conversion result has already started shifting out.
In actual operation, when different data lengths are required within an application and the data length is changed
between two conversions, no more than one conversion result can be corrupted and only when it is shifted out
in LSB-first format.
sampling period

During the sampling period, one of the analog inputs is internally connected to the capacitor array of the
converter to store the analog input signal. The converter starts sampling the selected input immediately after
the four address bits have been clocked into the input data register. Sampling starts on the fourth falling edge
of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge
of the I/O CLOCK depending on the data-length selection. After the EOC delay time from the last I/O CLOCK
falling edge, the EOC output goes low indicating that the sampling period is over and the conversion period has
begun. After EOC goes low, the analog input can be changed without affecting the conversion result. Since the
delay from the falling edge of the last I/O CLOCK to EOC low is fixed, time-varying analog input signals can be
digitized at a fixed rate without introducing systematic harmonic distortion or noise due to timing uncertainty.
After the 8-bit data stream has been clocked in, DATA INPUT should be held at a fixed digital level until EOC
goes high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the
influence of external digital noise.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-189

TLC2543C, TLC25431, TLC2543M
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D - DECEMBER 1993 - REVISED MAY 1997

PRINCIPLES OF OPERATION
data register, LSB first

D1 in the input data register (LSB first) controls the direction of the output binary data transfer. When D1 is reset
to 0, the conversion result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of
MSB first orLSB first always affects the next I/O cycle and not the current I/O cycle. When changing from one
data direction to anoth.~r, the current 1/0 cycle is never disrupted.
data register, bipolar format

DO (BIP) in the input data register controls the binary data format used to represent the conversion result. When
DO is cleared to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the
conversion result of an input voltage equal to Vref- is a code of all zeros (000 ... 0), the conversion result of
an input voltage equal to Vref+ is a code of all ones (111 ... 1), and the conversion result of (Vref + + Vref-)/2
is a code of a one followed by zeros (100 ... 0).
When DO is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion
of an input voltage equal to Vref- is a code of a one followed by zeros (100 ... 0), conversion of an input voltage
equal to Vref+ is a code of a zero followed by all ones (011 ... 1), and the conversion of (Vref+ + Vref-) 12 is a
code of all zeros (000 ... 0). The MSB is interpreted as the sign bit. The bipolar data format is related to the
unipolar format in that the MSBs are always each other's complement.
Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next 1/0 cycle. When changing between unipolar and bipolar formats, the data output during the
current 1/0 cycle is notaffected.
EOC output

The EOC signal indicates the beginning and the end of conversion. In the reset state, EOC is always high. During
the sampling period (beginning after the fourth falling edge of the 1/0 CLOCK sequence), EOC remains high
until the internal sampling switch of the converter is safely opened. The opening of the sampling switch occurs
after the eighth, twelfth, or sixteenth 1/0 CLOCK falling edge, depending on the data-length selection in the input
data register. After the EOG signal goes low, the analog input signal can be changed without affecting the
conversion result.
The EOC signal goes high again after the conversion is completed and the conversion result is latched into the
output data register. The rising edge of EOC returns the converter to a reset state and a new 1/0 cycle begins.
On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When
GS is negated between conversions, the first bit of the current conversion result occurs at DATA OUT on the
falling edge of CS.
data format and pad bits

D3 and D2 of the input data register determine the number of significant bits in the digital output that represent
the conversion result. The LSB-first bit determines the direction of the data transfer while the BIP bit determines
the arithmetic conversion. The numerical data is always justified toward the MSBin any output format.
The internal conversion result is always 12 bits long. When an a-bit data transfer is selected, the four LSBs of
the internal result are discarded to provide a faster one-byte transfer. When a 12-bit transfer is used, all bits are
transferred. When a 16-bit transfer is used, four LSB pad bits are always appended to the internal conversion
result. In the LSB-first mode, four leading zeros are output. In the MSB-first mode, the last four bits output are
zeros.

~TEXAS

2-190

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2543C, TLC25431, TLC2543M
12-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D - DECEMBER 1993 - REVISED MAY 1997

PRINCIPLES OF OPERATION
data format and pad bits (continued)
When CS is held low continuously, the first data bit of the newly completed conversion occurs on DATA OUT
on the rising edge of EOC. When a new conversion is started after the last falling edge of 1/0 CLOCK, EOC goes
low and the serial output is forced to a setting of 0 until EOC goes high again.
When CS is negated between conversions, the first data bit occurs on DATA OUT on the falling edge of CS.
On each subsequent falling edge of 1/0 CLOCK after the first data bit appears, the data is changed to the next
bit in the serial conversion result until the required number of bits has been output.

chip-select input (CS)
CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not
necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data
transfer of several devices sharing the same bus.
When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing
its output data line to other devices that may share it. After an internally generated debounce time, 1/0 CLOCK
is inhibited, thus preventing any further change in the internal state.
When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce
time before the reset operation takes effect. After CS is debounced low, 1/0 CLOCK must remain inactive (low)
for a minimum time before a new 1/0 cycle can start.
CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough
before the end of the current conversion cycle, the previous conversion result is saved in the internal output
buffer and shifted out during the next 1/0 cycle.

power-down features
When a binary address of 1110 is clocked into the input data register during the first four 1/0 CLOCK cycles,
the power-down mode is selected. Power down is activated on the falling edge of the fourth 1/0 CLOCK pulse.
During power down, all internal circuitry is put in a low-current standby mode. No conversions are performed,
and the internal output buffer keeps the previous conversion cycle data results provided that all digital inputs
are held above Vee - 0.5 V or below 0.5 V. The 1/0 logic remains active so the current 1/0 cycle must be
completed even when the power-down mode is selected. Upon power-on reset and before the first 1/0 cycle,
the converter normally begins in the power-down mode. The device remains in the power-down mode until a
valid input address (other than 1110) is clocked in. Upon completion of that 1/0 cycle, a normal conversion is
performed with the results being shifted out during the next 1/0 cycle.

~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-191

TLC2543C; TLC25431, TLC2543M
12·811' ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D - DECEMBER 1993 - REVISED MAY 1997

PRINCIPLES OF: OPERATlQN
analog input, test, and power-down mode

The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer
according to the input addresses shown in Tables 2, 3, and 4. The input multiplexer is a break-before-make type
to reduce input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on
the falling edge of the fourth 1/0 CLOCK and continues for the remaining 1/0 CLOCK pulses. The sample is held
on the falling edge of the last 1/0 CLOCK pulse. The three internal test inputs are applied to the multiplexer, then
sampled and converted in the same manner as the external analog inputs. The first conversion after the device
has returned from the power-down state may not read accurately due to internal device settling.
Table 3. Analog-Channel-Select Address
ANALOG INPUT
SELECTED

VALUE SHIFTED INTO
DATA INPUT
BINARY

HEX

AIND

.0.0.0.0

.0

AINl

.0.0.01

1

AIN2

.0.01.0

2
3

AIN3

.0.011

AIN4

.01.0.0

4

AIN5

.01.01

5

AIN6

.011.0

6

AIN7

.0111

7

AIN8

10.0.0

8

AIN9

1.0.01

9

AIN1D

1.01.0

A

Table 4. Test-Mode-Select Address
INTERNAL
SELF·TEST
VOLTAGE
SELECTEDt

VALUE SHIFTED I,NTO
DATA INPUT

UNIPOLAR OUTPUT
RESULT (HEX)*

BINARY

HEX

Vref+ - Vref2

1.011

B

Vref-

11.00

C

ODD

11.01

D

FFF,

8.0.0

Vref+
t Vref+ IS the voltage appiJed to REF +, and Vref-IS the voltage applied to REF-.
:I: The output results shown are the ideal values and may vary with the reference stability
and with internal offsets.

Table 5. Power-Down-Select Address
INPUT COMMAND

VALUE SHIFTED INTO
DATA INPUT
BINARY

Power down

111.0

I
I

RESULT

HEX

E

ICC~25I!A

~TEXAS'
2-192

INSTRUMENTS
POST OFFICE BOX 6553Q3 • DALLAS, TEXAS 75265

TLC2543C, TLC25431, TLC2543M
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D- DECEMBER 1993 - REVISED MAY 1997

PRINCIPLES OF OPERATION
converter and analog input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the Se switch and all ST switches simultaneously.
This action charges all tfie capacitors to the input voltage.
In the next phase of the conversion process, all ST and Se switches ·are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF-)
voltage. In the switching sequence, 12 capacitors are examined separately until all 12 bits are identified and
the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks
at the first capacitor (weight = 4096). Node 4096 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF-. When the voltage at the
summing node is greater than the trip point of the threshold detector (approximately 1/2 Vee), a bit 0 is placed
in the output register and the 4096-weight capacitor is switched to REF-. When the voltage at the summing node
is less than the trip point of the threshold detector, a bit 1 is placed in the register and this 4096-weight capacitor
remains connected to REF + through the remainder of the successive-approximation process. The process is
repeated for the 2048-weight capacitor, the 1024-weight capacitor, and so forth down the line until all bits are
determined. With each step of the successive-approXimation process, the initial charge is redistributed among
the capacitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB.
reference voltage inputs
The two reference inputs used with the device are the voltages applied to the REF+ and REF- terminals. These
voltage values establish the upper and lower limits of the analog input to produce a full-scale and zero-scale
reading respectively. These voltages and the analog input should not exceed the positive supply or be lower
than ground consistent with the specified absolute maximum ratings. The digital output is at full scale when the
input signal is equal to or higher than REF+ terminal voltage and at zero when the input signal is equal to or lower
than REF- terminal voltage.

Threshold
Detector

409~

204J 1021

I)

To Output
Latches

16

-;:;REF-J_s:EFr;:;J_s~EFr;:,'r;:;'r;:-;
r;:,'r;:;t;:;T
T
J_s:EF-J_s:EF-J_s:EF- J_s~EF- J_s;EF-J_ REF-J_
M

"i i i \J i

j j j j

Figure 15. Simplified Model of the Successive-Approximation System

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-193

TLC2543C, TLC25431, TLC2543M
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D - DECEMBER 1993 - REVISED MAY 1997

APPLICATION INFORMATION
111111111111
seJ Notes A

~nd B

VFS -

111111111110

.~

111111111101

CD

••
•

8

100000000001

i
o

100000000000

I~

)~ /

A~
VZT

=VZS + 1/2 LSB
/

011111111111

•••

f-- VZS

/

000000000010
000000000001
000000000000

/~

/

1/

IIV~

~

X
/'

§0.0012

r1

VFT

••
•
2049

I
I

Do

2048

~

i
I
I

••
•
2

I
I

•••

2.4564

ci

2.4576

•••

2.4588

VI- Analog Input Voltage - V

I
4.9128

i'i

5

DI

2047

Ii

V

0.0024

4093

=VFS -1/2 LSB

.

L,{/"

4094

FSnom

II I

V

/' . /

/1

4095

~!

/'

/'

~

o

/

~
/'

o
4.9140

4.9152

NOTES: A. This curve is based on the assumption that Vref+ and Vref- have been adjusted so that the voltage at the transition from digital 0
to 1 (VZT) is 0.0006 V and the transition to full scaie (VFT) is 4.9134 V. 1 LSB =1.2 mY.
B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is
the step whose nominal midstep value equals zero.

Figure 16. Ideal Conversion Characteristics
TLC2543
1
2
3
4
5
Analog
Inputs

6
7
8

9
11
12

AINO
AIN1
AIN2

15
CS

18

1/0 CLOCK
17
DATA INPUT
Processor

AIN3
AIN4

DATA OUT

AIN5

EOC

16
19

AIN6
AIN7
14
REF+ ~ S·V DC Regulated

AIN8
AIN9
AIN10

REF-

.14-

GND
110

To Source
Ground

l
Figure 17. Serial Interface

~TEXAS·
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

Control
Circuit

TLC2543C, TLC25431, TLC2543M
12-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D - DECEMBER 1993 - REVISED MAY 1997

APPLICATION INFORMATION

simplified analog input analysis
Using the equivalent circuit in Figure 18, the time required to charge the analog input capacitance from 0 V to
Vs within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by

(1 )
where
At = As + ri
The final voltage to 1/2 LSB is given by
(2)

Vc (1/2 LSB) = Vs - (Vs/8192)
Equating equation 1 to equation 2 and solving for time tc gives
Vs - (VS/8192) = V s ( 1--e-tc/AtCi)

(3)

tc (1/2 LSB) = At x Ci x In(8192}

(4)

and

Therefore, with the values given, the time for the analog input signal to settle is
tc (1/2 LSB)

= (As + 1 kO) x 60 pF x In(8192}

(5)

This time must be less than the converter sample time shown in the timing diagrams.
Driving Sourcet ~
Rs

I
I
I
I

VI

•

TLC2543

rl

VS~VC
I 1 len Max

i
I

I

CI
60pFMax

VI = Input Voltage at AIN
Vs = External Driving Source Voltage
Rs = Source Resistance
rj = Input Resistence
CI = Input Capacitance
VC= capacitance Charging Voltage

t Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.

Figure 18. Equivalent Input Circuit Including the Driving Source

~TEXAS

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2-195

2-196

TLC5510, TLC5510A
8·BIT HIGH·SPEED ANALOG· TO· DIGITAL CONVERTERS
APRIL 1997

•

NSPACKAGEt
(TOP VIEW)

Analog Input Range
- TLC5510 ... 2 V Full Scale
- TLC5510A ... 4 V Full Scale

OE
OGNO

8-Bit Resolution
Linearity Error
±O.75 LSB Max (25°C)
±1 LSB Max (-20°C to 75°C)

•

Differential Linearity Error
±0.5 LSB (25°C)
±0.75 LSB. Max (-20°C to 75°C)

06
07

9

AGNO
AGNO
ANALOG IN
VOOA

11

elK

5-V Single-Supply Operation
Low Power Consumption
TLC5510 •.. 127.5 mW Typ
TLC5510A •.. 150 mW Typ
(includes reference resistor dissipation)

•

TLC5510 is Interchangeable With Sony
CXD1175

Digital TV
Medicallmaging
Video Conferencing
High-Speed Data Conversion
QAM Demodulators

4

VOOO

•
•

•
•
•
•
•

02

08(MSB)

Maximum Conversion Rate
20 Mega-Samples per Second
(MSPS) Min

applications

REFB
REFBS

01 (lSB)

•
•

•

OGNO

1

REFT
REFTS

VOOA
VOOA
VOOO

t Available in tape and reel only and ordered
as the shown in the Available Options table
below.

AVAILABLE OPTIONS
TA

NSPACKAGE
(TAPE AND REEL ONLY)

- 20°C to 75°C

MAXIMUM FULL·SCALE
INPUT VOLTAGE
(VOLTS)

TLC5510lNSLE

2V

TLC5510AINSLE

4V

description
The TLC5510 and TLC5510A are CMOS, 8-bit, 20 MSPS analog-to-digital converters (ADCs) that utilize a
semiflash architecture. The TLC551 0 and TLC551 OA operate with a single 5-V supply and typically consume
only 130 mW of power. Included is an internal sample-and-hold circuit, parallel outputs with high-impedance
mode, and internal reference resistors.
The semiflash architecture reduces power consumption and die size compared to flash converters. By
implementing the conversion in a 2-step process, the number of comparators is significantly reduced. The
latency of the data output valid is 2.5 clocks.
The TLC551 0 uses the three internal reference resistors to create a standard, 2-V, full-scale conversion range
using VOOA' Only external jumpers are required to implement this option and eliminates the need for external
reference resistors. The TLC5510A uses only the center internal resistor section with an externally applied 4-V
reference such that a 4-V input signal can be used. Differential linearity is 0.5 LSB at 25°C and a maximum of
0.75 LSB over the full operating temperature range. Typical dynamic specifications include a differential gain
of 1% and differential phase of 0.7 degrees.
The TLC551 0 and TLC551 OA are characterized for operation from -20°C to 75°C.

~TEXAS

Copyright © 1997, Texas Instruments Incorporated

INSTRUMENTS
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2-197

TLC5510,TLC5510A
8·BIT HIGH·SPEED ANALOG·TO·DIGITAL CONVERTERS
SLAS0951- SEPTEMBER 1994 - REVISED APRIL 1997

functional block diagram
Resistor
Reference 1+------------,
Divider
REFB

2700

NOM~_+~~--~~-,
REFT

r--+--+-I~

REFBS

Lower Sampling
Comparators
(4-Bit)

800
NOM

01 (LSB)

02

Lower Data
Latch

03

04
__-t-+-l

Lower Sempllng
Comparators
(4-Blt)

05

-===~U-l--I~

Uppar Data
Latch

D6

07

Upper Sampling
Comparators
(4-Blt)

D8(MSB)

CLK

schematics of inputs and outputs
EQUIVALENT OF ANALOG INPUT

EQUIVALENT OF EACH DIGITAL INPUT

VDDA

VDDD

OE,CLK

ANALOG IN

AGND

01-08

DGND

~TEXAS
2-198

EQUIVALENT OF EACH DIGITAL OUTPUT

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS0951- SEPTEMBER 1994 - REVISED APRIL 1997

Terminal Functions
TERMINAL
NAME
AGND

NO.

DESCRIPTION

1/0

Analog ground

20,21

ANALOG IN

19

I

Analog input

CLK

12

I

Clock input

DGND

2,24

D1-D8

3-10

0

Digital data out. D1 = LSB, D8 = MSB

1

I

Output enable. When OE = low, data is enabled. When OE = high, D1-D8 is in high-impedance state.

OE
VDDA

14,15,18

VDDD

11,13

REFB

23

REFBS

22

REFT

17

REFTS

16

Digital ground

Analog supply voltage
Digital supply voltage
I

Reference voltage in bottom
Reference voltage in bottom. When using the TLC551 0 internal voltage divider to generate a nominal 2-V
reference, REFBS is shorted to REFB (see Figure 2). When using the TLC551 OA, REFBS is connected to
ground.

I

Reference voltage in top
Reference voltage in top. When using the TLC5510 internal voltage divider to generate a nominal 2-V
reference, REFTS is shorted to REFT (see Figure 2). When using the TLC551 OA, REFTS is connected to
VDDA

absolute maximum ratingst
Supply voltage, VDDA, VDDD

7V

.................................................................

Reference voltage input range, Vref(T), Vref(B) ....................................... AGND to VDDA
Analog input voltage range, VI(ANLG) ............................................... AGND to VDDA
Digital input voltage range, VI(DGTL) ................................................ DGND to VDDD
Digital output voltage range, VO(DGTL} ............................................. DGND to VDDD
Operating free-air temperature range, TA ............................................ -20°C to 75°C
Storage temperature range,

t

Tstg

.......................•....................... , ...

-55°C to 150°C

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

Supply voltage

MIN

NOM

MAX

VDDA-AGND

4.75

5

5.25

VDDD-AGND

4.75

5

5.25

-100

0

100

'AGND-DGND
Reference input voltage (top), Vref(T):t:

TLC5510A

Reference input voltage (bottom), Vref(B):t:

TLC5510A

Vre f(B)+2

Analog input voltage range, VI(ANLG)
High-level input voltage, VIH

4

V
V

Vref(B)

Vref(T)

V
V

1

..

mV

Vref(T)-4

LOW-level input voltage, VIL

Pulse duration, clock low, t"",(L} (see Figure 1)

V

0
4

Pulse duration, clock high, tw(H) (see Figure 1)

UNIT

V

25

ns

25

ns

:t: The reference voltage levels for the TLC551 0 are denved through an Internal resistor diVider between VDDA and ground and therefore are not
derived from a separate external voltage source (see the electrical characteristic~ and text). For the 4 V input range of the TLC5510A, the
reference voltage is externally applied across the center divider resistor.

~TEXAS

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2-199

TLC5510, TLC5510A
8·BIT HIGH·SPEED ANALOG·lO·DIGITAL CONVERTERS
SLAS0951- S!:PTEMBER 1994 - REVISED APRIL 1997

electric.al characteristics at Voo =5 V, Vref(T) =2.5 V, Vref(B)
otherwise noted)

=0.5 V, f(CLK) =20 MHz, TA =25°C (unless

digital 1/0
PARAMETER

TEST CONDITIONSt

IIH

High-level input current

VOO=MAX,

III

Low-level input current

VOO=MAX,

Vll= 0

MIN

TYP

MAX
5

. VIH = VOO

5

IOH

High-level output current

OE=GNO,

VOO=MIN,

VOH = VOO-0.5 V

IOl

low-level output current

OE=GND,

VOO=MIN,

VOl= 0.4 V

IOZH

High-level high-impedance-state
output leakage current

OE =VOO,

VOO=MAX

VOH = VOO

16

IOZl

low-level high-impedance-state
output leakage current

OE =VOO,

VOO= MIN

VOl=O

16

-1.5

UNIT
!LA
rnA

2.5

!LA

t Conditions marked MIN or MAX are as stated in recommended operating conditions.

power
PARAMETER
100

Supply current

Iref

Reference voltage current

TEST CONDITIONSt

MIN

f(ClK) = 20 MHz, National Television System Committee (NTSC)
ramp wave input, reference resistor dissipation is separate
TlC5510
TlC5510A

..

t Conditions marked MIN or MAX are as stated

In

I Vref = REFT I Vref = REFT -

..

TYP

MAX

UNIT

18

27

rnA

REFS = 2 V

5.2

7.5

10.5

rnA

REFS = 4 V

10.4

15

21

rnA

recommended operating .condltlons .

static performance
PARAMETER

TEST CONDITIONSt

Self-bias (I), at REFS
Self-bias (2), REFT - REFS
Self-bias (3), at REFT

,

Short REFS to REFSS,

Short REFT to REFTS

Short REFS to AGNO,

Short REFT to REFTS

Rref

Reference voltage resistor

Setween REFT and REFS

Ci

Analog input capacitance

VI(ANlG) = 1.5 V + 0.07 Vrms
f(ClK) = 20 MHz,
VI = 0.5 V to 2.5 V

TlC5510A

~ClK) = 20 MHz,
I=Ot04V

TA = 25'C

TlC5510

~ClK) = 20 MHz,
I = 0.5 V to 2.5 V

TA=25'C

TlC5510A

f(ClK) = 20 MHz,
VI = Ot04 V

TA = 25'C

Differential nonlinearity
(ONl)

Zero-scale .error

EZS

Full-scale error

EFS

..

MAX

0.61

0.65

1.9

2.02

2.15

2.18

2.29

2.4

190

270

350

16

UNIT
V

n
pF

±0.4

±0.75

±0.4

±0.75

±0.3

±0.5

±1

fA = -20'C to 75'C

±1

TA =-20'C to 75'C

lSS

±0.75

TA = -20'C to 75'C
±0.3

±0.5
±0.75

TA = -20'C to 75'C

TlC5510

Vref = REFT - REFS = 2 V

-18

--43

-68

mV

TlC5510A

Vref= REFT - REFS = 4 V

-36

'-86

-136

mV

TlC5510

Vref = REFT - REFS = 2 V

-20

0

20

mV

TlC5510A

Vref = REFT - REFS = 4 V

-40

0

40

mV

..

t ConditIOns marked MIN or MAX are as stated In recommended operating conditIOns .

~TEXAS

2-200

TYP

TA=25'C

TlC5510
Integral nonlinearity
(INl)

MIN
0.57

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5510,TLC5510A
8·BIT HIGH·SPEED ANALOG·TO·DIGITAL CONVERTERS
SLAS0951- SEPTEMBER 1994 - REVISED APRIL 1997

operating characteristics at VDD
otherwise noted)

= 5 V, VRT = 2.5 V, VRB = 0.5 V, f(CLK) = 20 MHz, TA = 25°C (unless

PARAMETER

TEST CONDITIONS
LTLC5510

ITLC5510A

II

= I-kHz ramp

MIN

VILANLG) ~ 0.5 V - 2.5 V

TYP

Maximum conversion rate

BW

Analog input bandwidth

At-l dB

14

td(D)

Digital output delay time

CL:S; 10 pF (see Note 1 and Figure 1)

18·

Differential gain

NTSC 40 Institute 01 Radio Engineers (IRE)
modulation wave,
Iconv = 14.3 MSPS

Differential phase
tAJ

Aperture jitter time

td(s)

Sampling delay time

ten

Enable time, OEJ. to valid data

CL=10pF

tdis

Disable time, OEi to high impedance

CL

= 1 MHz

Input tone

= 3 MHz

Input tone

= 6 MHz

Spurious free dynamic range (SF DR)

Input tone

= 10 MHz

MSPS

degrees

30

ps

4

ns

5

ns

7

ns

45

Full range

43

= 25°C

45

Full range

46

= 25°C

43

TA

TA

Full range

42

= 25°C

39

TA

ns

0.7

= 25°C

TA

MHz
30

1%

Full range

dB

39

= 25°C

46

Full range

44

TA

Signal-to-noise ratio

20

= 10 pF

Input tone

SNR

= 0 V-4 V

UNIT
MSPS

Iconv

VI(ANLG)

MAX

20

dB

NOTE 1: CL includes probe and jig capacitance.
tw(H) _.--Mf------.!CLK(clock)

ANALOG IN
(input signal)

01-08
(output data)

I

I

I

IN

i td(s)1 ~

~~I

__N_-_3__

1~~~-r_N_-_2 ~)(~~1
__

td(D)~

_,N_-_1__

~)(~~_N ~~)(~~
__

__
N_+1__

~_

I

Figure 1. 1/0 Timing Diagram

~TEXAS .
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TLC5510,TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS0951- SEPTEMBER 1994- REVISED APRIL 1997

PRINCIPLES OF OPERATION

functional description
The TLC551 0 and TLC551 OA are semiflash ADCs featuring two lower comparator blocks of four bits each.
As shown in Figure 2, input voltage V,(1) is sampled with the falling edge of CLK1 to the upper comparators block
and the lower comparators block(A), S(1). The upper comparators block finalizes the upper data UD(1) with the
rising edge of CLK2, and simultaneously, the lower reference voltage generates the voltage RV(1)
corresponding to the upper data. The lower comparators block (A) finalizes the lower data LD(1) with the rising
edge of CLK3. UD(1) and LD(1) are combined and output as OUT(1) with the rising edge of CLK4. As shown
in Figure 2, the output data is delayed 2.5 clocks from the analog input voltage sampling point.
Input voltage V,(2) is sampled with the falling edge of CLK2. UD(2) is finalized with the rising edge of CLK3, and
LD(2) is finalized with the rising edge of CLK4 at the lower comparators block(8). OUT(2) data appears with
the rising edge of CLK5.
VI(1)

ANALOG IN
(sampling points)

CLK(clock)

I

I
I

Upper Data

I

~ 5(1) I C(1) ~

=*
=x
I

U~(O)

I

Lower Reference Voltage

I

Lower Data (A)

I

~

I

I
I

C(2)

I

5(4)

U+)

I

I

C(3)

I

I

I

U+3)

I

I
RV(3)

I

I

I

I

I

I

I

I +) I I I
C(1)

LD~-1)

+i~l~i
: LO(-2)

I

X
I
I

OUT(-2)

X

OUT(-1)

H(3)

I

I

I

LD(O)

~

I
I

I
I

X

OUTeD)

X

~TEXAS

.

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

~
I

C(3)

K:

L~(1)

I

I

I I

*
+i~l~i
5(3)

*=
I

>K

5(1)

I

C(4)

RV(2)

Figure 2. Internal Functional Timing Diagram

.2-202

I

>K

~

::x

I

RV(1) "

I

D1-D8 (data output)

5(3)

>K

I

Lower Data (B)

I

*U~(1) * *
5(2)

I

" Lower Comparators Block (B)

I

RV(O)

I

Lower Comparators Block (A)

I

Fi-t'i~r5t---1~t---"-1r

--1
Upper Comparators Block

VI(4)

I

I

$

I

LD(2)

I
I

OUT(1)

x=

TLC5510,TLC5510A
8·BIT HIGH·SPEED ANALOG·TO·DIGITAL CONVERTERS
SLAS0951- SEPTEMBER 1994 - REVISED APRIL 1997

PRINCIPLES OF OPERATION

internal referencing
TLC551 0
The three internal resistors shown with VOOA can generate a 2-V reference voltage. These resistors are brought
out on VOOA, REFTS, REFT, REFB, REFBS, and AGND.
To use the internally generated reference voltage, terminal connections should be made as shown in Figure 3.
This connection provides the standard video 2-V reference for the nominal digital output.
TLC5510
18

VODA
(analog supply)

R1
320 0 NOM

RE FTS

I

16
17

REFT
Rref
2700 NOM

REFB

23

I

22

RE FBS

AG ND

R2
800 NOM
21

..1
Figure 3. External Connections for a 2-V Analog Input Span Using the Internal-Reference Resistor Divider

TLC5510A
For an analog input span of 4 V, 4 V is supplied to REFT, and REFB is grounded and terminal connections should
be made as shown in Figure 4. This connection provides the 4-Vreference for the nominal zero to full-scale
digital output with a 4 Vpp analog input at ANALOG IN.
TLC5510A
18

VDDA
(analog supply)

R1
320 0 NOM
16
REFTS

4V

J.

- REFT

17

REFB

23

Rref
270 0 NOM

REFBS 22

21

R2
80 o NOM

AGND ..1

-=-

Figure 4. External Connections for 4-VAnalog Input Span

~TEXAS

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2-203

TLC5510, TLC5510A
8·BIT HIGH·SPEED ANALOG·TO·DIGITAL CONVERTERS
SLAS0951 ~ SEPTEMBER 1994- REVISED APRIL 19.97

PRINCIPLES OF OPERATION

functional operation
The output code change with input voltage is shown in Table 1.

Table 1. Functional Operation
INPUT SIGNAL
VOLTAGE

STEP

Vref(B)

255

·
·
·
·
·
·

Vref(T)

DIGITAL OUTPUT CODE
MSB

0

LSB

0

·· ·· ··
·· ·· ··

0

0

0

0

0

0

128

0

1

· · · · · ·
· · · · · ·
1

1

1

1

1

1

127

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

· · · · · ·
· · · · · ·

APPLICATION INFORMATION
The following notes are design recommendations that should be used with the device.
•

External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.

•

RF breadboarding or printed-circuit-board (PCB) techniques should be used throughout the evaluation and
production process. Breadboards shoUld be copper clad for bench evaluation.

•

Since AGNO and DGNO are connected internally, the ground lead in must be kept as noise free as possible.
A good method to use is twisted-pair cables for the supply lines to minimize noise pickup. An analog and
digital ground plane should be used on PCB layouts when additional logic devices are used. The AGNO
and OGNO terminals of the device should be tied to the analog ground plane.

•

VDDA to AGND and VDDD to DGND should be decQupled with 1-IlF and 0.01-IlF capacitors, respectively,
and placed as close as possible to the affected device terminals. A ceramic-chip capacitor is recommended
for the 0.01-IlF capacitor. Care should be exercised to ensure a solid noise-free ground connection for the
analog and digital ground terminals.

•

VDDA, AGND, and ANALOG IN should be shielded from the higher frequency terminals, ClK and 00-07.
When possible, AGNO traces should be placed on both sides of the ANALOG IN traces on the PCB for
'
shielding.

•

In testing or application of the device, the resistance of the driving source connected to the analog input
should be 10 Q or less within the analog frequency range of interest.

~TEXAS

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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC5510,TLC5510A
8·BIT HIGH·SPEED ANALOG·TO·DIGITAL CONVERTERS
SLAS0951- SEPTEMBER 1994 - REVISED APRIL 1997

APPLICATION INFORMATION
OVOO
5V

~(
C12
TLC551 0

AVOO
5V

13
VREF
AOJ

~

FB3

14

-

-±- C8

FB2

b -

R5

15

~C7

FB7 JP1 JP2

Video J
1
Input ~

ri/

Q1

1\

01~~
R1 ~

TP1 ;;:: ::::C3

L+

~C9

R3
..A

R4

\1

c;~

R2
C2

r

.¢.

03~ <-

~

-5V

02~

TP3

~

r: C5
:::: :::::: C4
JP3 JP4

I1

;;::

r: C10

VOOA

Clock

VOOO rU~~
C11
10
08 (MSB)
07 9

17 REFT

06 8

18

VOOA

05 7

ANALOG IN

04 6

19
;;::

VOOA

16 REFTS

C6 II

FB1

ClK 12

VOOO

20 AGNO

03 5

21 AGNO

02 4

22 REFBS 01 (lSB) 3
23 REFB

OGNO 2

24 OGNO

OE 1

./

Output

..... Enable

r:'7
NOTE A: Shorting JP1 and JP3 allows adjustment of the reference voltage by R5 using temperature-compensating diodes 02 and 03
which compensate for 01 and 01 variations. By shorting JP2 and JP4, the internal divider generates a nominal 2-V reference.

lOCATION

DESCRIPTION

CI, C3-C4, C6-C12

0.1-IlF capacitor

C2

I O-pF capacitor

C5

47-IlF capacitor

FBI,FB2,FB3,FB7
01

,

Ferrite bead
2N3414 or equivalent

RI,R3

75-0 resistor

R2

500-0 resistor

R4

10-kO resistor, clamp voltage adjust

R5

300-0 resistor, reference-voltage fine adjust

Figure 5. TLC5510 Evaluation and Test Schematic

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TLC5510, TLC5S1.0A
8·BIT HIGH·SPEED ANALOG·TO·DIGITAL CONVERTERS
SLAS0951- SEPTEMBER 1994 - REVISED APRIL 1997

APPLICATION INFORMATION
DVDD
5V
If

~~
TlC5510A

AVDD
5V

13
VREF
AOJ

FB3

-

r--<

R5

Video
Input

J1

C1

"

1\

If

R1

R4

C~~

R2

I
FB1

r

C2;;:: [=::

~

-

r: C3

14
15

~C7k

FB7

R3

D1~~

4;

FB2

b

TP1 ;;::

Q1

,Tcs

17

~C9
\1
C6 /1

-

18

T

19
20

C5

21
-5V

~

VDDO

ClK

VDOA

VDDD

VOOA

D8 (MSB)

;-

REFTS

07 9

REFT

06 8

VODA

05 7

ANALOG IN

D4 6

AGNO

D3 5

AGND

D2 4

C11

REFBS D1 (lSB) 3

OGND

OE 1

NOTE A: R5 allows adjustment of the reference voltage to 4 V. R4 adjusts for the desired 01 quiescent operating point.
lOCATION

DESCRIPTION
0.1-~F

capacitor

C2

10-pF capacitor

C5

47-~F

FB1,FB2,FB3,FB7

capacitor

Ferrite bead
2N3414 or equivalent

01
R1,R3

75-0 resistor

R2

500-0 resistor

R4

10-kQ resistor, clamp voltage adjust·

R5

300-0 resistor, reference-voltage fine adjust

Figure 6. TLC5510A Evaluation and Test Schematic

~TEXAS

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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

r

..
r

OGNO 2

rt7

C1, C3-C4, C6-C11 .

Clock

.u~~
10

~ REFB
24

12

Output
Enable

TLC5510, TLC5510A
8·BIT HIGH·SPEED ANALOG·TO·DIGITAL CONVERTERS
SLAS0951- SEPTEMBER 1994 - REVISED APRIL 1997

APPLICATION INFORMATION
AVOO
5V

an

4.711':

O.1I1F

~~

10kPOT

TLC5510
CLOCK

OE
01
02
03
04
05
06
07
08

To Processor

+

4.711F

OVOO

~

5V
REFTS

VOOO
VOOO

REFT

O.1I1F

REFBS
REFB
OGNO
OGNO
AGNO
AGNO

t FB - Ferrile Bead
Figure 7. TLC5510 Application Schematic

~TEXAS

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2-207

TLC5510, TLC5510A
.
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS0951- SEPTEMBER 1994 - REVISED APRIL 1997

APPLICATION INFORMATION
AVOO

1 kQ

TLC5510A
CLOCK

VOOA
VOOA
VOOA

OE
01
02
03
04
05
D6
07
08

OVOO
5V

+

4.7/lF ~

REFTS

VOOO
VOOO

REFT
REFBS
REFB
OGNO
OGNO

t

FB - Ferrite Bead

Figure 8. TLC5510A Application Schematic

~TEXAS

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INSTRUMENTS
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To Processor

TLC5540
8·BIT HIGH·SPEED ANALOG· TO·DIGITAL CONVERTER
SLAS1 058 ~ JANUARY 1995 - REVISED APRIL 1996

NSPACKAGE
(TOP VIEW)

•

8-Bit Resolution

•

Differential Linearity Error
- ±0.3 LSB Typ, ±1 LSB Max (25°C)
- ±1 LSB Max

•

Integral Linearity Error
- ±0.6 LSB, ±0.75 LSB Max (25°C)
- ±1 LSB Max

•

Maximum Conversion Rate of
40 Megasamples Per Second (MSPS) Min

OE
OGNO
01(lSB)
02

•

Internal Sample and Hold Function

•

5-V Single Supply Operation

•

Low Power Consumption . .. 85 mW Typ

•

Analog Input Bandwidth . .. ;:::75 MHz Typ

•

Internal Reference Voltage Generators

•

VODA

06
07
08(MSB)
VDOO

applications
Quadrature Amplitude Modulation (QAM)
and Quadrature Phase Shift Keying (QPSK)
Demodulators

•

Digital Television

•

Charge-Coupled Device (CCD) Scanners

•

Video Conferencing

•

Digital Set-Top Box

•

Digital Down Converters

•

High-Speed Digital Signal Processor
Front End

3
4

OGNO
REFB
REFBS
AGNO
AGNO
ANALOG IN

elK

9
11

REFT
REFTS
VODA
VODA
VODD

AVAILABLE OPTIONS
TA

NSPACKAGE

O'C to 70'C

TLC5540CNSLE

-40°C to 85'C

TLC5540lNSLE

description
The TLC5540 is a high-speed, a-bit analog-to-digital converter (ADC) that converts at sampling rates up to
40 megasamples per second (MSPS). Using a semiflash architecture and CMOS process, the TLC5540 is able
to convert at high speeds while still maintaining low power consumption and cost. The analog input bandwidth
of 75 MHz (typ) makes this device an excellent choice for undersampling applications. Internal resistors are
provided to generate 2-V full-scale reference voltages from a 5-V supply, thereby reducing external
components. The digital outputs can be placed in a high impedance mode. The TLC5540 requires only a single
5-V supply for operation.

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Copyright © 1996. Texas Instruments Incorporated

2-209

TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105B- JANUARY 1995-REVISED APRIL 1996

functional block diagram
Resistor
Reference ....- - - - - - - - - - - - ,
Divider
REFB

270n

NOM~_+~~--~~~
REFT

r--+--H~

REFBS

Lower Sampling
Comparators
(4 Bit)

01 (LSB)

02

Lower Data
Latch

BOn

D3

NOM
AGND

D4

AGND

.....1----++1

Lower Sampling
Comparators
(4 Bit)

05

VDDA

320n
NOM
REFTS
ANALOG IN

06

Upper Data
Latch

-====-J.--l--I---..1 Upper
Sampling
Comparators

07
D8(MSB)

(4 Bit)
CLK

Clock
Generator

schematics of inputs and outputs
EQUIVALENT OF ANALOG INPUT

EQUIVALENT OF EACH DIGITAL INPUT

VDDA

ANALOG IN

VDDD

OE,CLK

EQUIVALENT OF EACH DIGITAL OUTPUT
VDDD

01-08

DGND

~TEXAS

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INSTRUMENTS
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TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105B- JANUARY 1995 - REVISED APRIL 1996

Terminal Functions
. TERMINAL

NAME
AGND

NO.

1/0

20,21

DESCRIPTION

Analog ground

ANALOG IN

19

I

Analog input

ClK

12

I

Clock input

DGND

2,24

D1-DS

3-10
1

OE
VDDA

14,15,1S

VDDD
REFB

11,13

REFBS

22

REFT

17

REFTS

16

23

Digital ground

0

Digital data out. 01 :LSB, OS:MSB

I

Output enable. When OE = l, data is enabled. When OE = H, Dl-DS is high impedance.
AnalogVDD
DigitalVDD

I

ADC reference voltage in (bottom)
Reference voltage (bottom). When using the internal voltage divider to generate a nominal 2-V reference,
the REFBS terminal is shorted to the REFB terminal and the REFTS terminal is shorted to the REFT terminal
(see Figure 13 and Figure 14).

I

Reference voltage in (top)
Reference voltage (top). When using the internal voltage divider to generate a nominal2-V reference, the
REFTS terminal is shorted to the REFT terminal and the REFBS terminal is shorted to the REFB terminal
(see Figure 13 and Figure 14).

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, VDDA, VDDD ................................................................. 7 V
Reference vDltage input range, VI(REFT), VI(REFB), VI(REFBS), VI(REFTS) ............... AGND to VDDA
Analog input voltage range, VI(ANLG) ............................................... AGND to VDDA
Digital input voltage range, VI(DGTL) ................................................ DGND to VDDD
Digital output voltage range, VO(DGTL) ............................................. DGND to VDDD
Operating free-air temperature range, TA: TLC5540C ........ , .......................... O°C to 70°C
TLC55401 ................................. -40°C to 85°C
Storage temperature range, Ts1g ................................................... -55°C to 150°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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2-211

TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER.
SLAS105B- JANUARY 1995 - REVISED APRIL 1996

recommended operating conditions
MIN
Supply voltage

5

5.25

VDDD-AGND

4.75

5

5.25

AGND-DGND

-100
VI{REFB)+ 1.8

Reference input voltage (bottom), VI(REFB)

0

Analog input voltage range, VI(ANlG) (see Note 1)

VI(REFB)
1.8

Full scale voltage, VI(REFT)- VI(REFB)
High-level input voltage, VIH

0

100

V

VI(REFTl-l.8

V

VI(REFT)

V

5

TlC55401

NOTE 1: 1.8 V ~ VI(REFT) - VI(REFB) < VDD

~TEXAS

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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

V
V
V
ns

12.5
TlC5540C

mV

0.6

12.5

Pulse duration, clock low, twill

V

VDDA

1

Pulse duration, clock high, tw(H)

UNIT

VI(REFB)+2

4

low-level input voltage, Vil

2-212

MAX

4.75

Reference input voltage (top), VI(REFTl

Operating free-air temperature, TA

NOM/

VDDA-AGND

ns

0

70

°C

-40

85

°C

TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS1 058 - JANUARY 1995 - REVISED APRIL 1996

electrical characteristics at Voo
(unless otherwise noted)

=5 V, VI(REFT) =2.6 V, VI(REFB) =0.6 V, f8 =40 MSPS, TA =25°C

PARAMETER
EL

TEST CONDITIONSt

Linearity error, integral
fs =40 MSPS,
VI = 0.6 V to 2.6 V

EO

MIN

TA = 25°C

Linearity error, differential

TYP

MAX

±0.6

±1

±0.3

±0.75

0.61

0.65

2.63

2.80

TA = MIN to MAX

±1

TA = 25°C
TA = MIN to MAX

Self bias (1), VRB

Short REFB to REFBS

Self bias (1), VRT

Short REFT to REFTS

Self bias (2), VRB

Short REFB to AGNO

2.47

AGNO

See Figure 14

Self bias (2), VRT

Short REFT to REFTS

2.18

2.29

Iref

Reference-voltage current

VI(REFT)- VI(REFB) = 2 V

5.2

7.5

12

Rref

Reference-voltage resistor

Between REFT and REFB terminals

165

270

350

Ci

Analog input capacitance

VI(ANLGl = 1.5 V + 0.07 Vrms

EZS

Zero-scale error

EFS

Full-scale error

IIH

High-level input current

VOO= 5.25 V,

VIH =VOO

5

IlL

Low-level input current

VOO = 5.25 V,

VIL=O

5

V

2.4

4

VI(REFT) - VI(REFB) = 2 V

LSB

±1
0.57

See Figure 13

UNIT

rnA
fA

pF

-18

-43

-68

-25

0

25

IOH

High-level output current

OE=GNO,

VOO = 4.75 V,

VOH = VOO-0.5 V

IOL

Low-level output current

OE=GNO,

VOO = 4.75 V,

VOL= 0.4 V

-1.5

IOZH(lkg)

High-level
high-impedance-state
output leakage current

OE=VOO,

VOO =5.25,

VOH = VOO

16

IOZL(lkg)

Low-level
high-impedance-state
output leakage current

OE =VOO,

VOO =4.75,

VOL=O

16

100

Supply current

fs =40 MSPS,
CL ::::;~25 pF,

NTSC:j: ramp wave input,
See Note 2

mV

IlA
rnA

2.5

I!A

17

27

rnA

tConditions marked MIN or MAX are as stated in recommended operating conditions.
:j: National Television System Committee
NOTE 2: Supply current specification does not include Iref.

~TEXAS

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TLC5540
8~BIT HIGH-SPEED ANALOG-TO;'DIGITAL CONVERTER
SLAS1 058 - JANUARY 1995 - REVISED APRIL 1996

operating characteristics at Voo.= S V,VRT = 2.6 V, VRB=·0.6 V,fs = 40 MSPS, TA = 25°C (unless
otherwise noted)
TEST CONDITIONst

PARAMETER

MIN

.TYP

MAX

UNIT

Maximum conversion rate

TA'; MIN to MAX

Is

Minimum conversion rate

TA = MIN to MAX

BW

Analog input lull-power bandwidth

At - 3 dB, VI(ANLG) = 2 Vpp

ted

Delay time, digital output

CL'" 10 pF (see Note 3)

tPHZ

Disable time, output high to hi-z

CL" 15 pF,

IOH =-4.5 mA

20

ns

tPLZ

Disable time, output low to hi-z

CL'" 15 pF,

IOL=5mA

20

ns

tpZH

Enable time,hi-z to output high

CL'" 15 pF,

IOH =-4.5mA

15

ns

tpZL

Enable time, hi-z to output low

CL'" 15 pF,

IOL=5mA

15

ns

Differential gain

NTSC 40 IRE:j: modulation wave,
Is = 14.3 MSPS

Is

Differential phase
tAJ

Aperture jitter time

ld(s)

Sampling delay time

SNR

Signal-to-noise ratio

II =3 MHz

9

44

Is =40 MSPS

42

THD

Total harmonic distortion
Is=40 MSPS
Spurious Iree dynamic range

47

42
7.61

II =6 MHz

7.47

11= 10 MHz

7.16

II =3 MHz

7

II =6 MHz

6.8

II =3 MHz

42
41

11=10MHz

38

II =3 MHz

40

Is=40 MSPS,

II =3 MHz

Conditions marked MIN or MAX are as stated in recommended operating conditions.
:j: Institute 01 Radio Engineers
NOTE 3: CL includes probe and jig capacitance.

~TEXAS

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dBc

38

II =6 MHz
II =3 MHz

Bits

43
35

II =6 MHz

Is=20 MSPS,

dB

44

II =3 MHz

t

2-214

ns

7.64

11=1 MHz
Is = 20 MSPS

ps

4

45

11= 1 MHz

Effective number 01 bits

degrees

30

45.2

11=10MHz

ENOB

0.7

46

II =3 MHz

Is=20 MSPS

ns

47

II =6 MHz

II =6 MHz

MHz
15

1%

11=10MHz
Is=40 MSPS

MSPS

5
75

11= 1 MHz
Is = 20 MSPS

MSPS

40

41

46

dBc

42

dBc

TLC5540
8·BIT HIGH·SPEED ANALOG·TO·DIGITAL CONVERTER
SLAS1 058 - JANUARY 1995 - REVISED APRIL 1996

PARAMETER MEASUREMENT INFORMATION

I

D1-D8
(Output Data)

I

Jr--\Ly--

CLK(Clock)

ANALOG IN
(Input Signal)

I

11
I
I
I
I

I
I
I
I

N

~

I
I
I
N-3

I

¥

I N+2
I
I
I
I

N+1

X~

N-2

N-1
____

I
I
I
I

1\........11
I
I
I

I
I
I

~)(~~_N__~)(~__N+_1~__

tpd~

Figure 1. 1/0 Timing Diagram

I

I

k,-------.. .\J

OE

:Jj

~'------ Refer(~.~J>eVel

I
I

Data Output

~
Active

~

tPHZ ~
tpLZ :- .,

Hi-Z

I
I
I

(-~._ _
Ac_ti_ve_ _

-1.---.l.,

2.4 V
0.4 V

tpZH
tPZL: .

Figure 2. 1/0 Timing Diagram

-!!1
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TLC5540
8·BIT HIGH·SPEED ANALOG·TO·DIGITAL CONVERTER
SLAS1 058 - JANUARY 1995 - REVISED APRIL 1996

TYPICAL CHARACTERISTICS
POWER DISSIPATION

vs
ANALOG INPUT BANDWIDTH

SAMPLING FREQUENCY
0.5

200

I

.'

VOO=5V
TA=25°e

r--... r-..

0
-0.5

~

150

~

-1

E
-1.5

I

c

III

0

~
Q.

·w

"C

100

-2
-2.5

c

.!!l

c
lii
~
Q.

I

~

50

f-o
o

--5

l..--

,--

I--

....--V

<:)

-3
-3.5

Vee = 5 V, VRT = 2.6 V, VRB = 0.6 V
eLK =40 MHz
ANALOG IN = 100 k -100 MHz Sine Wave

-4
-4.5

VI 1= 21 Vf~~)111I

-5

10
15
20
25
30
35
fs - sampling Frequency - MHz

40

Figure 4
SIGNAL-TO-NOISE RATIO

vs

vs

INPUT FREQUENCY

INPUT FREQUENCY
50

8

fs = 20 MHz

fs = 20 MHz

7

.~

6

"0
lii
.c

5

----=:::
fs = 40 MHz

III

E
:::I

Z

>

4

III
"C

I
0

3

I
III

2

35

~

25

c

20

fs=40 MHz

30

D>

iii

I,
II:

15

en

10

Z

0

Z

w

o
o

40

iII:
III
·0
~

 O.02-J.lF capacitor

C2

< 1O-J.lF capacitor

FB1, FB2, FB3

Ferrite beads, C type

Figure 11. AVOO, DVOO, AGND, and DGND Connections

~TEXAS

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TLC5540
a-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105B- JANUARY 1995- REVISED APRIL 1996

APPLICATION INFORMATION
printed circuit board (PCB) layout considerations
When designing a circuit that includes high-speed digital and precision analog signals such as a high speed
ADC, PCB layout is a key component to achieving the desired performance. The following recommendations
should be considered during the prototyping and PCB design phase:
•

Separate analog and digital circuitry physically to help eliminate capacitive coupling and crosstalk. When
separate analog and digital ground planes are used, the digital ground and power planes should be several
layers from the analog Signals and power plane to avoid capacitive coupling.

•

Full ground planes should be used. Do not use individual etches to return analog and digital currents or
partial ground planes. For prototyping, breadboards should be constructed with copper clad boards to
maximize ground plane.

•

The conversion clock, ClK, should be terminated properly to reduce overshoot and ringing. Any jitter on
the conversion clock degrades ADC performance. A high-speed CMOS buffer such as a 74ACT04 or
74AC04 positioned close to the ClK terminal can improve performance.

•

Minimize all etch runs as much as possible by placing components very close together. It also proves
beneficial to place the ADC in a corner of the PCB nearest to the I/O connector analog terminals.

•

It is recommended to place the digital output data latch (if used) as close to the TlC5540 as possible to
minimize capacitive loading. If DO through D7 must drive large capacitive loads, internal ADC noise may
be experienced.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-219

TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105B- JANUARY 1995- REVISED APRIL 1996

PRINCIPLES OF OPERATION

functional description
The TLC5540 uses a modified semiflash architecture as shown in the functional block diagram. The four most
significant bits (MSBs) of every output conversion result are produced by the upper comparator block CB1. The
four least significant bits (LSBs)of each alternate output conversion result are produced by the lower
comparator blocks CB-A and CB-B in turn (see Figure 12).
The reference voltage that is applied to the lower comparator resistor string is one sixteenth of the amplitude
of the refence applied to the upper comparator resistor string. The sampling comparators of the lower
comparator block require more time to sample the lower voltages of the reference and residual input voltage.
By applying the residual input voltage to alternate lower comparator blocks, each comparator block has twice
as much time to sample and convert as would be the case if only one lower comparator block were used.
VI(l)

VI(2)

I

i

VI(3)

VI(4)

ANALOG IN
(Sampling Points)

CLK(Clock)

Upper Comparators Block (CB1)

Upper Data

Lower Reference Voltage

, S(l)

Lower Data (A)

U~(O)*I

U+)

=:>K

I

I

I

I
I

RV(O)

>K

RV(l)

>K

I

I

I

I
I

S(l)

LD~-1)

==>K

u+)

*

; C(4)

U~(3)

I

I
I

RV(2)

>K

RV(3)

I

I

I

j

*=
I
I

>K=:
I

I

I

I

*

S(3)

I

C(3)

L~(1)
I

I

~
I

I

+) i I i +) i I i +)
0 L~(O) ~.
C(O)

S(2)

C(2)

I

I

S(4)

I

I

: LD(-2)

LD(2);

I+-

==:x

tpd--+i
01-08 (Data Output)

j S(4)

C(3)

II

C(l)

I

Lower Data (B)

*

I

I I +) I I I +) I I
I

Lower Comparators Block (CB-B)

j S(3)

C(2)

=*
I

Lower Comparators Block (CB-A)

C(l) , S(2)

I

OUT(-2)

X

I
OUT(-1)

X

I
OUT(O)

X

I
OUT{l)

K.

Figure 12. Internal Functional Timing. Diagram
This conversion scheme, which reduces the required sampling comparators by 30percent compared to
standard semiflash architectures, achieves significantly higher sample rates than the conventional semiflash
conversion method.

~TEXAS

2-220

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC5540
8·BIT HIGH·SPEED ANALOG·TO·DIGITAL CONVERTER
SLAS1 058 - JANUARY 1995 - REVISED APRIL 1996

PRINCIPLES OF OPERATION
functional description (continued)
The M8S comparator block converts on the falling edge of each applied clock cycle. The l8S comparator blocks
CS-A and CS-S convert on the falling edges of the first and second following clock cycles, respectively. The
. timing diagram of the conversion algorithm is shown in Figure 12.

analog input operation
The analog input stage to the TlC5540 is a chopper-stabilized comparator and is equivalently shown below:

VOOA

To

=
ANALOG IN

O-+ftL E'~LogO
CS3lcp1t<1>2l S

...-_ _-0<1>1
S1

To Encoder Logic

"""-'>---1

-0"'2

Vref(N)

'f

C

S

L--.,..---<:r=-----iltL
Cs

To

E,~

LogO

Figure 13. External Connections for Using the Internal Reference Resistor Divider
Figure 13 depicts the analog input for the TlC5540. The switches shown are controlled by two internal clocks,
. <1>1 and <1>2. These are nonoverlapping clocks that are generated from the ClK input During the sampling period,
<1>1, 81 is closed and the input signal is applied to one side of the sampling capacitor, s. Also during the sampling
period,·82 through 8(N) are closed. This sets the comparator input to approximately 2.5 V. The delta voltage
is developed across Cs. During the comparison phase, <1>2, 81 is switched to the appropriate reference voltage
for the bit value N. 82 is opened and Vref(N) - VC s toggles the comparator output to the appropriate digital 1 or
O. The small resistance values for the switch, 81, and small value of the sampling capacitor combine to produce
the wide analog input bandwidth of the TlC5540. The source impedance driving the analog input of the
TlC5540 should be less than 100 n across the range of input frequency spectrum.

e

reference inputs - R.EFB, REFT, REFBS, REFTS
The range of analog inputs that can be converted are determined by REFS and REFT, REFT being the
maximum reference voltage and REFS being the minimum reference Voltage. The TlC5540 is tested with
REFT = 2.6 V and REFS = 0.6 V producing a 2-V full-scale range. The TlC5540 can operate with
REFT - REFS = 5 V, but the power dissipation in the reference resistor increases significantly (93 mW
nominally). It is recommended that a 0.1 J.1F capacitor be attached to REFS and REFT whether using externally
or internally generated voltages.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-221

TLC5540
8-81T HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105B- JANUARY 1995 - REVISED APRIL 1996

PRINCIPLES OF OPERATION

internal reference voltage conversion
Three internal resistors allow the device to generate an internal reference voltage. These resistors are brought
out on terminals VOOA, REFTS, REFT, REFB, REFBS, and AGND. Two different bias voltages are possible
without the use of external resistors.
Internal resistors are provided to develop REFT = 2.6 V and REFB = 0.6 V (bias option one) with only two
external connections. This is developed with a 3-resistor network connected to VOOA- When using this feature,
connect REFT to REFTS and connect REFB to REFBS. For applications where the variance associated with
VOOA is acceptable, this internal voltage reference saves space and cost (see Figure 14).
A second internal bias option (bias two option) is shown in Figure 15. Using this scheme REFB =AGND and
REFT = 2.28 V nominal. These bias voltage options can be used to provide the values listed in the following
table.
Table 1. Bias Voltage Options
BIAS VOLTAGE

BIAS OPTION
VRB
1

0.61

VRT
2.63

2

AGND

2.28

VRT-VRB
2.28

2.02

To use the internally-generated reference voltage, terminal connections should be made as shown in
Figure 14 or Figure i 5. The connections in Figure i 4 provide the standard video 2-V reference.
TLC5540
18

VDDA
V (Analog)

R1
320QNOM

REFTS

0.11!F

±

T

16
17

REFT

-=

REFB

±

2.63 Vdc

~ Rref
270QNOM
23

0.61 Vdc

22
REFBS

? R2

-=

AGND

21

~

80QNOM

..1
Figure 14. External Connections Using the Internal Bias One Option

~TEXAS

INSTRUMENTS

2-222

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105B- JANUARY 1995 - REVISED APRIL 1996

PRINCIPLES OF OPERATION
TLC5540
18

VDDA

5 V (Analog)

R1
320 n NOM
>

REFTS

O.1I1F

±

16
17

2.2BVdc

REFT

-=-

REFB

23

Rref
270nNOM

~

OVdc

22
REFBS
AGND

21

R2
80nNOM

~

Figure 15. External Connections Using the Internal Bias Two Option

functional operation
Table 2 shows the TLC5540 functions.
Table 2. Functional Operation
INPUT SIGNAL
VOLTAGE

STEP

Vref(T)

255

··
·
··
·

Vref(B)

DIGITAL OUTPUT CODE
MSB

LSB

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

1

1

1

1

128

1

0

· · · · · ·
· · · · · ·

127

0

1

0

· · · · · ·

· ·· ··
· · ·
· · ·
·

0

0

· · · · · ·
0

0

0

0

0

0

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-223

2-224

TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-OIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
- REVISED NOVEMBER 1996

•

3-Channel CMOS ADC

•

Analog Input Bandwidth ... >14 MHz

•

5-V Single-Supply Operation or 5-V Analog
Supply with Digital Supply from
2.7 V to 5.25 V

•

Suitable for YUV or RGB Applications

•

Digital Clamp Optimized for NTSC or PAL
YUV Component

•

8-Bit Resolution

•

High-Precision Clamp . .. ±1 LSB

•

Differential Linearity Error . .. ±0.5 LSB Max

•

Automatic Clamp Pulse Generator

•

Linearity Error . .. ±0.75 LSB Max

•

Output-Data Format Multiplexer

•

Maximum Conversion Rate
20 Megasamples per Second
(MSPS) Min

•

Low Power Consumption

•

Analog Input Voltage Range
2 VI(PP) Min
64-Pin Shrink QFP Package

•

description
The TLC5733A is a 3-channel 8-bit semiflash analog-to-digital converter (ADC) that operates from a single 5-V
power supply. It converts a wide-band analog signal (such as a video signal) to digital data at sampling rates
up to 20 MSPS minimum. The TLC5733A contains a feed-back type high-precision clamp circuit for each ADC
channel for video (YUV) applications and a clamp pulse generator that detects COMPOSITE SYNCt pulses
automatically. A clamp pulse can also be supplied externally. The output-data format multiplexer selects a ratio
of Y:U:V of 4:4:4, 4:1:1, or 4:2:2. For RGB applications, the 4:4:4 output format without clamp function can be
used. The TLC5733A is characterized for operation from -20°C to 75°C.
AVAILABLE OPTIONS
PACKAGE
TA
-20°C to 75°C

t

QUAD FLATPACK
TLC5733AIPM

COMPOSITE SYNC refers to the externally generated synchronizing signal that is a combination of vertical and horizontal sync information
used in display and TV systems.

PRODUCTION DATA Information Is currenl 88 of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include

testing of all parameters.

~TEXAS

Copyright © 1996, Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-225

TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS1 04A - JULY 1995 - REVISED NOVEMBER 1996

PM PACKAGE
(TOP VIEW)
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o
0

«
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«::>

ID
0..1....J::>ID

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0
0

ID

>
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C:( ~ ~
(!)««a:OO~OO~OOa:IDID(!)

AD1

e

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48
10
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2
46
3
45
4
44
5
43
6
42
7
41
40
10
39
11
38
37
12
36
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15
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~TEXAS
2-226

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Z
(!)

RBB
OEB
MOD EO
MODE1
QC DGND
CD1
CO2
CD3
CD4
CDS
CD6
CD7
CDa
QC DVDD
OEC
RBC

TLC5733A
20 MSPS 3·CHANNEL ANALOG·TO·DIGITAL CONVERTER
WITH HIGH·PRECISION CLAMP
SLAS104A-JULY 1995 - REVISED NOVEMBER 1996

functional block diagram

r---------------,
C~A
I

I
AIN
RT A
RBA
CLPV A
CLP OUT A

il

mJ
ii

RT C

II

,-

t-

tfiI 1
Ii

ADC

r

(Sampling
Comparators)

-:1
r

Clamp
Circuit

8

I
II
I

~

II

mJ

r

RB C

I

i

i

Output Data
Latch

Multiplexer
For
Output Format

~.----.
1,8
ADC
t-+>'~~+--'"
(Sampling
Comparators)

I

CLPV C
CLP OUT C

8

~+-- BDl-8

II

~~-------------~
CLKC

I
CIN

Clamp
Circuit

_____ ...J
~KB
I
•
I
1,,8
I

RBB
CLPV B
CLPOUTB

I

---=1

I- ~
I
I

BIN!
RT B

8
I
8
8
ADC
I-~~~+-----.....;:,"'r--'...
~+-- ADl-8
(Sampling
!I
Output Data
Comparators)
8 I
Latch

l
I

---I

~I

1'8

8

~+--

!

CDl-8

Output Data
Latch

I
Clamp
Circuit

~"'+---.I

L.___________ ___

1I--.----L---...J

EXTCLP - - - . . . . . . Control For
CLPEN
INT/EXT
NT/PAL
Clamp Circuit

iil
Clock
Generator

i

CLK

-

Output
Forniat
Selector
and Test

.....~I---- MODEO

H - - - MODEl
.........1 - - - - TEST

i

INIT

~TEXAS

INSTRUMENTS
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2-227

TLC5733A
20 MSPS 3·CHANNEL ANALOG;'TO·DIGITAL CONVERTER
WITH HIGH·PRECISION CLAMP
SLAS1 04A - JULY 1995 - REVISED NOVEMBER 1996

Terminal Functions
TERMINAL

I/O

DESCRIPTION

NAME

NO.

A AVCC
AD8-AD1 '

62

I

6-13

0

Data output of ADC A (LSB: AD1, MSB:AD8)

63

I

Analog input of ADC A
Analog supply voltage of ADC B

AIN
BAVCC
BD8-BD1
BIN
CAVCC
CD8-CD1

Analog supply voltage of ADC A

51

I

17-24

0

Data output of ADC B (LSB: BD1, MSB:BD8)

50

I

Analog input of ADC B

30

I

Analog supply voltage of ADC C

36-43

0

Data output of ADC C (LSB:CD1. MSB: CD8)
When MOD EO = L, MODE1 = L, CD8 outputs MSB flag of BD8-BD5
When MOD EO = L, MODE1 = L, CD7 outputs MSB flag of BD8-BD5
When MOD EO = L, MODE1 = H, CD8 outputs B channel flag of CD8-BD1
When MODEO = L. MODE1 = H, CD8 outputs B channel flag ofCD8-BD1

CIN

31

I

Analog input of ADC C

CLK

56

I

Clock input The clock frequency is normally 4 x the frequency subcarrier (fsc) for most video systems (see
Table 3), The nominal clock frequency is 14,31818 MHz for National Television System Committee (NTSC)
and 17,745 MHz for phase alteration line (PAL),

CLPEN

57

I

Clamp enable. When using an internal clamp pulse, CLPEN should be high, When using an external clamp
pulse, CLPEN should be low.

ClP OUT A

59

0

Clamping bias current of ADC A,

ClP OUT B

54

0

Clamping bias current of ADC B, A resistor-capacitor combination that sets the clamp timing.

~

resistor-capacitor combination that sets the clamp timing,

CLP OUTC

27

0

Clamping bias current of ADC C. A resistor-capacitor combination that sets the clamp timing.

ClPVA

60

0

Clamping level of ADC A. A capacitor is connected to CLPV A to set the clamp timing. The clamp level at
ClPV A is connected to an output code of 16 (001 OOOO).

ClPVB

53

0

Clamping level of ADC B. A capacitor is connected to CLPV B to set the clamp timing. The clamp level at
CLPV B is connected to an output code of 128 (1000000).

ClPVC

28

0

Clamping level of ADC C. A capacitor is connected to CLPV C to set the clamp timing. The clamp level at
CLPV C is connected to an output code of 128 (1 OOOOOO).

DGND

15

I

Digital ground

DVDD

26

I

Digital supply voltage

EXTCLP

55

I

External clamp pulse input When EXTCLP and ClPEN are low, the internal clamp circuit cannot be used.
The external clamp pulse when used is active high.

GNDA

64

I

Ground of ADC A

GND B

49

I

Ground of ADC B

GNDC

32

I

Ground of ADC C

INIT

58

I

Output initialized. The output data is synchronous when INIT is taken high from low. INIT is a control terminal
that allows the external system to initialize the TlC5733A data conversion cycle. INIT is usually used at
power up or system reset

MODEO

46

I

Output format mode selector O. When MODE1 is low and MODEO is low, output data format1 is selected.
When MODE1 is low and MODE9 is high, output data format2 is selected, When MODE1 is high and
MODEO is low, output data format3 is selected. A high level on MODE1 and a high level on MODEO is not
used.

MODE1

45

I

Output format mode selector 1. When MODE1 is low and MODEO is low, output data format1 is selected.
When MODE1 is low and MODEO is high, output data format2 is selected. When MODE1 is high and
MODEO is low, output data format3 is selected. A high level on MODE1 and a high level on MODEO is not
used.

NT/PAL

3

I

NTSC/PAL control. NTSC/PAl should be low for NTSC and high for PAL.

OEA

2

I

Output enable A. OE A enables the output of ADC A.

OEB

47

I

Output enable B. OE B enables the output of ADC B.

~TEXAS

2-228

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A-JULY 1995 - REVISED NOVEMBER 1996

Terminal Functions (Continued)
TERMINAL
NAME

NO.

DESCRIPTION

1/0

34
5
14
25

I

Output enable C. OE C enables the output of ADC C.

I

Digital ground for output of ADC A

I

Digital supply voltage for output of ADC B

I

Digital ground for output of ADC C

RBA

16
44
35
1

RBB

OEC
QADGND
QADVDD
QB DGND
QBDVDD
QC DGND

I

Digital supply voltage for output of ADC A

I

Digiial ground for output of ADC B

I

Digital supply voltage for output of ADC C

I

Bottom reference voltage of ADC A. The nominal externally applied dc voltage between RT A and RB A is
2 V for video signals.

48

I

Bottom reference voltage of ADC B. The nominal externally applied dc voltage between RT Band RB B is
2 V for video signals ..

RBC

33

I

Bottom reference voltage of ADC C. The nominal externally applied dc voltage between RT C and RB C
is 2 V for video signals.

RTA

61

I

Top reference voltage of ADC A. The nominal externally applied dc voltage between RT A and RB A is
V for video signals ..

2

RTB

52

I

Top reference voltage of ADC B. The nominal externally applied dc voltage between RT Band RB B is
V for video signals.

2

RTC

29

Top reference voltage of ADC C. The nominal externally applied dc voltage between RT C and RB C is
V for video signals.

2

TEST

4

QC QVDD

I

Test. TEST should be tied low when using this device.

absolute maximum ratingst
Supply voltage, Vee, Voo ................................................................... 7 V
Reference voltage input range,Vr~f(RT A), Vref(RT B), Vref(RT C), Vref(RB A),
Vref(RB B), Vref(RB e) ........................................................... AGND to Vee
Analog input voltage range ......................................................... AGND to Vee
Digital input voltage range, VI ....................................................... DGND to Voo
Digital output voltage range, Vo .................................................... DGND to Voo
Operating free-air temperature range, TA ............................................ -20°C to 75°C
Storage temperature range, Tstg ................................................... -55°C to 150°C
t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-229

TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLASI 04A - JULY 1995 - REVISED NOVEMBER 1996

recommended operating conditions

Supply voltage;

MIN

NOM

MAX

VCC-AGND

4.75

5

5.25

VDD-DGND

2.7

5

5.25

-100

0

AGND-DGND
Reference input voltage, Vref(RT A), Vref(RT B), Vref(RT C)

Vref(RB)+2

UNIT
V

100

mV

VCC

V

Reference input voltage, Vref(RB A), Vrei(RB B), Vref(RB C)

0

Vref(Rn- 2

V

Analog input voltage, VI

0

Vref(RT)

V

High-level input voltage, VIH

2

V
0.8

Low-level input voltage, VIL

V

High-level pulse duration, tw(H)

25

ns

Low-level pulse duration, twill

25

·ns

. Setup time for INIT input, tsul

ns

5

Operating free-air temperature range, TA

'c

75

-20

:j: Within the electrical and operating characteristics table, when the term VDD is used, all XOVOD terminals are tied together, and when the term
VCC is used, all XAVCC terminals are tied together.

=

electrical characteristi~s at Voo 2.7 V to 5.25 V, Vee
f(elK) 20 MHz, TA 25°C (unless otherwise noted)

=

=

PARAMETER

=5 V, Vref(RT)= 2.5 V, Vref(BB) =0.5 V,

TEST CONDITIONS

MIN

Clamp level accuracy

t

MAX

±1

Rref

Reference voltage resistor

Measured between RT and RB

Cj

Analog input capacitance

VI = 1.5 V + 0.07 Vrms

IIH

High-level input current

VOO = MAXt,
VCC = 5V

VIH =VOD,

IlL

Low-level input current

VDD = MAXt,
VCC = 5V

VIL= 0,

VOH

High-level output voltage

All DVDO terminals = 2.7 V to 5.25 V,
IOH =-1 rnA

VOL

Low-level output voltage

All DYDD terminals =2.7 Y to 5.25 Y,
IOL=2 rnA

IOH(lkg)

High-level output leakage current

YOD = MAXt,
VCC =5V

VOH=YDD,

IOL(lkg)

Low-level output leakage current

YDD= MINt,
YCC=5V

YQL=O,

ICC

Supply current

fc= 20 MSPS,
NTSC ramp wave input

160

220

~TEXAS

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT
LSB

350

16

..
Conditions marked MIN or MAX are as stated in recommended operating conditions .

2-230

TYP

n
pF

5

~
5
OVDO-O.7V
V
0.8
16

~
16
50

75

rnA

TLC5733A
20 MSPS 3·CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH·PRECISION CLAMP
SLAS104A-JULY 1995 - REVISED NOVEMBER 1996

=

operating characteristics at Voo 2.7 V to 5.25 V, Vee
f(elK) 20 MHz, TA 25°C (unless otherwise noted)

=

=

PARAMETER

=5 V, Vref(RT) =2.5 V, Vref(RB) =0.5 V,
MIN

TYP

MAX

UNIT

EZS

Zero-scale error

Vrel = REFT - REFB = 2 V

TEST CONDITIONS

-18

-43

-68

mV

EFS

Full-scale error

Vrel = REFT - REFB = 2 V

-20

0

20

mV

±0.4

±0.75

±0.4

±1

±0.3

±0.5

±0.3

±0.75

I{ClK) = 20 MHz,

VI = 0.5 V to 2.5 V

I{ClK) = 20 MHz,
TA = -20°C to 75°C

VI = 0.5 V to 2.5 V

El

Linearity error

I{ClK) = 20 MHz,

VI = 0.5 V to 2.5 V

ED

Linearity error, differential

I{ClK) = 20 MHz,
TA = -20°C to 75°C

VI = 0.5 V to 2.5 V

Ic

Maximum conversion rate

VI = 0.5 V - 2.5 V,

II = 1-kHz ramp wavelorm

BW

Analog input bandwidth

At-1 dB

14

Ipd

Digital output delay time

Cl= 10 pF

18

Differential gain

NTSC 40 IRE:J: modulation wave,

Ic = 14.3 MSPS

1%

Differential phase

NTSC 40 IRE:J: modulation wave,

Ic = 14.3 MSPS

0.7

deg

30

ps

4

ns

Aperture jitter time
Sampling delay time

20

lSB

lSB
MSPS
MHz

30

ns

:J: Institute 01 Radio Engineers

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-231

TLC5733A
20 MSPS 3-CHANNEL ANALOG·TO·DIGITAL CONVERTER
WITH HIGH·PRECISION CLAMP
SLAS104A-JULY 1995 - REVISED NOVEMBER 1996

detailed description
clamp function

The clamp function is optimized for a YUV video signal and has two clamp modes. The first mode uses the
COMPOSITE SYNC signal as the input to the EXTCLP terminal to generate an internal clamp pulse and the
second mode uses an externally generated clamp pulse as the input to the EXTCLP terminal.
In the first mode, the device detects false pulses in the COMPOSITE SYNC signal by monitoring the rising and
falling edges of the COMPOSITE SYNC signal pulses. This monitoring prevents faulty operation caused by
disturbances and missing pulses of the COMPOSITE SYNC signal input on EXTCLP and external spike noise.
When fault pulses are detected, the device internally generates a train of clamp pulses at the proper positions
(1 H) by an internal 91 O-counter for NTSC and a 1136-counter for PAL. The device checks clamp pulses for 1H
time and generates clamp pulses at correct positions when COMPOSITE SYNC pulses are in error in time.
The internal counter continually produces a horizontal sync period (1 H) that is NTSC or PAL compatible as
selected by the condition of the NT/PAL terminal.

clamp voltages and selection
Table 1 shows the clamping level during the clamp interval. Table 2 shows the selection of the internal or external
clamp pulse. With either NTSC or PAL, the internal clamp pulse is always used.
Table 1. Clamp Level (Internal Connection Level)
CHANNEL OF ADC

OUTPUT CODE

APPLICATION

ADC A. VI(A)

00010000
10000000
10000000

(U, V)

ADC B. VI(B)
ADC C. VI(C)

Y

(U, V)

Table 2. Clamp Level (Internal Connection Level)
CONDITION
CLPEN
L

H

EXTCLP

n
L
COMPOSITE SYNC input

FUNCTION (EACH ADC)
NT/PAL

INTERNAL CLAMP

CLAMP PULSE

Don't Care

Inactive

External clamp pulse

Don't Care

Inactive

No clamping

L

Active

Synchronous with NTSC

H

Active

Synchronous with PAL

The clamp circuit is shown in Figure 6. The clamp voltage is stored on capacitor C2 during the back porch of
the horizontal blanking period.
During the clamp pulse the input to channel A is clamped to:
Vc(A) = (16/256) x (voltage difference from terminal RT A to RB A)
Vc(B) = (128/256) x (voltage difference from terminal RT B to RB B)
Vc(C) = (128/256) x (voltage difference from terminal RT C to RB C)
COMPOSITE SYNC time monitoring

When CLPEN is high, COMPOSITE SYNC generates an internal clamp pulse on the horizontal blanking interval
back porch. The TLC5733A has a timing window into which the horizontal sync tip must occur. There is a noise
time window for the falling edge and one for the rising edge (see Figure 1, Figure 2, and Table 3).

~TEXAS

2-232

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A- JULY 1995 - REVISEO NOVEMBER 1996

correct COMPOSITE SYNC timing
The Noise Gate 1 signal provides the timing window for the COMPOSITE SYNC falling edge. After an interval
A of 867 clocks for NTSC or 1075 for PAL from the last falling edge of COMPOSITE SYNC, Noise Gate 1 signal
goes high for 43 clocks for NTSC or 61 clocks for PAL (interval B). The falling edge of the input signal to the
EXTCLP terminal can occur at any time within this window to be a valid COMPOSITE SYNC falling edge.
The Noise Gate 2 signal provides the timing window for the COMPOSITE SYNC rising edge. On the falling edge
of the horizontal sync tip, the internal logic generates Noise Gate 2 as a low signal for 58 clocks (interval C) for
both NTSC and PAL and then returns to a high active state. At this time if the input to EXTCLP is still low, it is
considered a valid COMPOSITE SYNC signal.
normal clamp pulse generation
On the rising edge of COMPOSITE SYNC, the internal logic generates an internal delay (interval D) and then
generates the internal positive clamp pulse 54 clocks wide (interval F).
clamp operation with incorrect COMPOSITE SYNC timing
noise suppression
If the input to EXTCLP goes low prior to Noise Gate 1 going high (within 43 clocks for NTSC or 61 clocks for
PAL of the normal 1H timing for the falling edge of COMPOSITE SYNC) then that input is not considered a valid
COMPOSITE SYNC and is ignored.
If the input to EXTCLP is high when Noise Gate 2 goes to the high state, the input signal is considered noise
and is ignored.
Therefore, the correct signal must be high for a maximum of 43 1clocks for NTSC or 61 clocks for PAL, before
the 1H timing, to be a valid sync signal. Also, the input to EXTCLP must be at least 58 clocks wide (interval C)
to be valid.
This function of monitoring the timing eliminates spurious noise spikes from falsely synchronizing the system.
timing error of COMPOSITE SYNC
The internal counter resets to zero on the first falling edge of COMPOSITE SYNC. After that time, if there is a
missing COMPOSITE SYNC signal, then the internal logic waits an interval of 76 clocks (interval E) for NTSC
or 93 for PAL from the counter zero count and then generates an internal clamp pulse 54 clocks wide
(interval F).
This function maintains the synchronization pattern when COMPOSITE SYNC is not present.
summary of device operation with COMPOSITE SYNC
This internal timing allows the TLC5733A to correctly position the clamp pulse when an external COMPOSITE
SYNC input:
•
•
•
•

Is delayed with respect to the horizontal sync period
Is early with respect to the horizontal sync period
Is nonexistent during the horizontal sync period
Has falling edge noise spikes within the horizontal sync period

The device operation is summarized as follows for these improper external clamp conditions:
•

Under all four. conditions on EXTCLP, the internal clamp generation circuit generates a clamp pulse at
the proper time after the horizontal sync period as shown in Figure 1.

•

The TLC5733A internal clamp circuit generates an internal clamp pulse each 1H time for the entire time
interval that the COMPOSITE SYNC input is missing.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-233

TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A- JULY 1995 - REVISED NOVEMBER 1996

14
COMPOSITE
SYNC

Noise Gate 1

Noise Gate 2

Internal Clamp
Pulse

~I

1H

.'. 1

I

r--l

A

.1

~ i'1
I
1
I
1

I

I

I--_.J

I
I
I

"'-

1

I
1
1
1
1
1
1
0-'1 14-

....

COMPOSrr, SYNC,
/therefore, Noise Gate Is Not
Generated

I

I

I

i

'1'1

C.J
1
1

1

NTSC/PAL Counter Reset

NTSC/PAL Counter at
Max Count

Figure 1. COMPOSITE SYNC and Internal Clamp liming
COMPOSITE
SYNC

Nc!seGate 1

~\\\

1/1///

__~r-B-'~_ _ _ _ _ _

+!__________

1

1

1

I

1

1

\\\~

Noise Gate 2

I

Figure 2. Proper COMPOSITE SYNC liming
Table 3. Sync and Clamp Timing for NTSC and PAL withCLK = 4 fsc
NTSC
TIME
INTERVAL

fse

PAL

= 3.58 MHz

fse

= 4.43 MHz

NO. OF
CLOCKS

TIME
(lUI)

NO. OF
CLOCKS

TIME
(Ils)

A

867

60.6

1075

60.7

B

43

3

61

3.5

C

58

4.05

58

3.27

0

6

0.42

6

0.34

E

76

5.3

93

5.25

F

54

3.77

84

4.74

using an external clamp pulse

When CLPEN is taken low, EXTCLP accepts an externally generated active-high clamp pulse. This pulse must
occur within the horizontal-blanking interval back porch. CLPEN low inhibits the internal counters and no internal
clamp pulse is generated.

~TEXAS

2-234

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC5733A
20 MSPS 3·CHANNEL ANALOG·TO·DIGITAL CONVERTER
WITH HIGH·PRECISION CLAMP
SLASl 04A - JULY 1995 - REVISED NOVEMBER 1996

output digital code (for each channel of ADC)
Table 4. Input Signal Versus Digital Output Code
INPUT SIGNAL
VOLTAGE

STEP

Vref(RT)

255

DIGITAL OUTPUT CODE
LSB

MSB
1

1

1

1

1

1

·· ·· ·· ·· ·· ·· ··
a
a
a
a
a
a
· · · · · · ·
· · · · · · ·

·
·
··
·
·

128

1

127

a

a

Vref(RB)

1

1

1

1

1

a

a

a

a

a

1

1

· ·
· a·
a
1

1

0

0

·
· ··

output data format

The TLC5733A can select three output data formats to various TV/vCR (video) data processing by the
combination of MODEO and MODE1. The output is synchronous when INIT is taken high.
Table 5. Output Data Format Selection
CONDITION
MODEl

MODEO

OUTPUT DATA
OUTPUT DATA
FORMAT

RATIO OF Y:U:V

L

L

Format 1

4:1:1

L

H

Format 2

4:4:4

H

L

Format 3

4:2:2

H

H

Not used

N/A

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-235

TlC5733A
20 MSPS3-CHANNEL ANALOG·TO·DIGITAL CONVERTER
WITH HIGH·PRECISION CLAMP
SLAS104A - JULY 1995 - REVISED NOVEMBER 1996

output data format (continued)

ClK

INIT

---L.......L...JI

OEA
OEB
OECAnalog
,nput VI(ANlG)

Output Data A

Output Data B
BD8-BD5
BD4~BD1:

Hi-Z

I
.I
I
I

:

I

Output Data C
CD8

I

CD7
CD6-CD1: Hi-Z
o = Input signal sampling point

Figure 3. Format 1, 4:1:1

~TEXAS

2-236

B01
C02
C01

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

B47
C48
C47
I

:

I

B45
C46
C45
I

:

I

I

I

TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS1 04A - JULY 1995 - REVISED NOVEMBER 1996

output data format (continued)
Table 6. Format 1
OUTPUT DATA
CHANNEL OF
ADC

BIT

6

7

S

9

10

.11

12

13

A

ADS
AD?
AD6
AD5
AD4
AD3
AD2
AD1

A08
AD?
A06
A05
A04
A03
A02
A01

A18
A1?
A16
A15
A14
A13
A12
A11

A28
A27
A26
A25
A24
A23
A22
A21

A38
A3?
A36
A35
A34
A33
A32
A31

A48
A4?
A46
A45
A44
A43
A42
A41

A58
A5?
A56
A55
A54
A53
A52
A51

AS8
A6?
A66
A65
A64
A63
A62
A61

A?8
A77
A?6
A75
A?4
A?3
A?2
A?1

B

BD8
BD?
BD6
BD5
BD4
BD3
BD2
BD1

B08
BO?
C08
CO?
Hi-Z
Hi-Z
Hi-Z
Hi-Z

B06
B05
C06
C05
Hi-Z
Hi-Z
Hi-Z
Hi-Z

B04
B03
C04
C03
Hi-Z
Hi-Z
Hi-Z
Hi-Z

B02
B01
CO2
C01
Hi-Z
Hi-Z
Hi-Z
Hi-Z

B48
B4?
C48
C4?
Hi-Z
Hi-Z
Hi-Z
Hi-Z

B46
B45
C46
C45
Hi-Z
Hi-Z
Hi-Z
Hi-Z

B44
B43
C44
C43
Hi-Z
Hi-Z
Hi-Z
Hi-Z

B42
B41
C42
C41
Hi-Z
Hi-Z
Hi-Z
Hi-Z

C

CD8
CD?
CD6
CD5
CD4
CD3
CD2
CD1

H
l
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z

l
l
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z

l
l
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z

l
H
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z

H
l
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z

l
l
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z

l
l
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z

l
H
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z

ClK (see Note 1)

NOTES: 1. The value of the fIrst sampling clock at ND conversIon IS ClK O.
2. A06 is an example of an entry in the table where A is the ADC channel, 0 is the sampling order, and
6 is the bit number.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-23?

TLC5733A
20 MSPS 3-CHANNEL ANALOG·TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
.
SLAS194A - JULY 1995 - REVISED NOVEMBER ·1996

output data format (continued)

ClK

INIT

-+-+-'

OEA
OEB

Analog
Input VI{ANlG)

Output Data A
AD8-AD1
Output Data B
BD8-BD1

Output Data C·
CD8-CD1

o = Input signal sampling point

Figure 4. Format 2, 4:4:4

~TEXAS
2-238

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5733A
20 MSPS 3·CHANNEL ANALOG·TO·DIGITAL CONVERTER
WITH HIGH·PRECISION CLAMP
SLAS1 04A - JULY 1995 - REVISED NOVEMBER 1996

output data format (continued)
Table 7. Format 2
OUTPUT DATA
CHANNEL OF
ADC

BIT

6

7

8

9

10

11

12

13

A

AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1

A08
A07
A06
A05
A04
A03
A02
A01

A18
A17
A16
A15
A14
A13
A12
A11

A28
A27
A26
A25
A24
A23
A22
A21

A38
A37
A36
A35
A34
A33
A32
A31

A48
A47
A46
A45
A44
A43
A42
A41

A58
A57
A56
A55
A54
A53
A52
A51

A68
A67
A66
A65
A64
A63
A62
A61

A78
A77
A76
A75
A74
A73
A72
A71

6

6D8
6D7
6D6
6D5
6D4
6D3
6D2
6D1

608
607
606
605
604
603
602
601

618
617
616
615
614
613
612
811

628
627
626
625
624
623
622
621

63B
637
636
635
634
633
632
631

648
647
646
645
644
643
642
641

658
657
656
655
854
653
652
651

6BB
667
666
665
664
663
662
861

678
677
676
675
674
673
672
671

C

CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1

C08
C07
C06
C05
C04
C03
CO2
C01

C18
C17
C16
C15
C14
C13
C12
C11

C28
C27
C26
C25
C24
C23
C22
C21

C38
C37
C36
C35
C34
C33
C32
C31

C48
C47
C46
C45
C44
C43
C42
C41

C58
C57
C56
C55
C54
C53
C52
C51

C68
C67
C66
C65
C64
C63
C62
C61

C78
C77
- C76
C75
C74
C73
C72
C71

NOTES:

ClK (see Note 1)

1. The value of the first sampling clock at AID conversion is ClK O.
2. A06 is an example of an entry in the table where A is the ADC channel,
6 is the bit number.

a is the sampling order, and

~TEXAS

INSTRUMENTS
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2-239

TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS1 04A - JULY 1995 - REVISED NOVEMBER 1996

output data format (continued)
tw(H) -I4-N-l1I-

ClK

INIT

--'--'-.II

OEA
OEB
OECAnalog
Input VI(ANlG)

Output Data A
AD8-AD1
Output Data B
BD8-BD1

Output Data C
CD8

CD7
CD6 - CD1 : Hi-Z

o = Input signal sampling point

Figure 5. Format 3, 4:2:2

~TEXAS

2-240

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5733A
20 MSPS 3-CHANNEL ANALOG-lO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A-JULY 1995 - REVISED NOVEMBER 1996

output data format (continued)
Table 8. Format 3
OUTPUT DATA
CHANNEL OF
ADC

BIT

6

7

8

9

10

11

12

13

A

AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1

A08
A07
A06
A05
A04
A03
A02
AOI

A18
A17
A16
A15
A14
A13
A12
All

A28
A27
A26
A25
A24
A23
A22
A21

A38
A37
A36
A35
A34
A33
A32
A31

A48
A47
A46
A45
A44
A43
A42
A41

A58
A57
A56
A55
A54
A53
A52
A51

A68
A67
A66
A65
A64
A63
A62
A61

A78
A77
A76
A75
A74
A73
A72
A71

B

BD8
BD7
BD6
BD5
BD4
BD3
BD2
BD1

B08
B07
B06
B05
B04
B03
B02
B01

C08
C07
C06
C05
C04
C03
CO2
C01

B28
B27
B26
B25
B24
B23
B22
B21

C28
C27
C26
C25
C24
C23
C22
C21

B48
B47
B46
B45
B44
B43
B42
B41

C48
C47
C46
C45
C44
C43
C42
C41

B68
B67
B66
B65
B64
B63
B62
B61

C68
C67
C66
C65
C64
C63
C62
C61

H
l
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z

l

H

l
H
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z

H

l

H

l

H
Hi-Z
Hi-z
Hi-Z
Hi-Z
Hi-Z
Hi-Z

l

l

H
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z

l

C

CD8
CD7
CD6
CD5
CD4
CD3
CO2
CD1

H
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z

NOTES:

ClK (see Note 1)

Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z

Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z

Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z

1. The value of the first sampling clock at NO conversion IS ClK O.
2. A06 is an example of an entry in the table where A is the ADC channel, 0 is the sampling order, and
6 is the bit number.

~TEXAS

INSTRUMENTS
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2-241

TLC5733A
20 MSPS3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A-JULY 1995 - REVISED NOVEMBER 1996

APPLICATION INFORMATION

r--;~;;~;~~~;~;;--­

I
I

Vref (Top)

Video Signal Input
(Composite or Component)

ClK

---+------1

C2
0.22 ~F
~

I
I

AID

lAIN

~f-----I--'=''-----1It----I

Vref (Bottom) ---II"-----t----1L...-_ _....I
Digital
Feedback

R1
16 k!l

J

Output

C1

I
I
I
I
I
I

' - - - - - -......--.._--I--+--

I

2200pF

Clamp Gate

Magnitude

L _______ ~:~~: _____ _

FEEDBACK CLAMP AND CHARGE PUMP ACT!VITY
INPUT DATA
CONDITIONS

PQ

OUTPUT

CHARGE PUMP
CONDITIONS

Active

H

Hold

Z

Charge
Hold

Active

L

Discharge

Figure 6. Feedback Clamp Circuit

~TEXAS

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TLC5733A
20 MSPS 3·CHANNEL ANALOG·TO·DIGITAL CONVERTER
WITH HIGH·PRECISION CLAMP
SLAS104A-JULY 1995- REVISED NOVEMBER 1996

APPLICATION INFORMATION

r----------------------------- ,

Channel-A

,..-----,
I PNP: 2SA733

2.2 kil

I
I'-NPN:
_ _2SC1815
_ _ _ .JI

1100

4.3 kil

10l1F
Analog
Signal Input

TlC5733A

63

VIN(A)

60

ClPV(A)

1 kil

1V1(PP)

CW
750

5.6 kil

Gain Adjust
5.6kO

4700

Buffer Amplifier

_

~-----------------------------~~
C2
---

~

. _ Amp

~
~

•

.22:

ADO

m

15kO
C1
2200pF

0'1' R1 ..
2

CL'OIlT(A)

OE(A)

I

,'-----'

ffi

55

56

ClKIN

57

58
3

4

EXTClP

ClK
ClPEN

INIT
NT/PAL

TEST

Figure 7. Interface Without Clamping

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-243

TLC5733A
20 MSPS 3':CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP

SLAS104A- JULY 1995 - REVISED NOVEMBER 1996

APPLICATION INFORMATION

r-----------------------------

Channel-A

r-----'

2.2kQ

I PNP: 2SA733 I
IL.NPN:
2SC1815 I
_____

TlC5733A

110 Q

~

.-t-il-....:6=3.. VIN(A)

Analog
Signal Input

.12VI(pp)

I
I
I
I
I
I
I
I

1V1(PP)

75Q

L _____________
_ _Amplifier
_ _ _ _ _ _ _ _ _ _ _ _ _ _ ~J
Buffer
_

C2

~

Buffer Amp •

o 22

---TlC5733A

F

• RI11

r------,6=0.. ClPV(A)
R1 59

____ vv,~. ClP OUT A

ADC
C1

15kQ
C1
2200pF

,

J71

J7

2

OE(A)

'1..-_ _- - '

10l1F

Composite SYNC
OV

---1 +

55
1 kQ

-5V·ru

OV~

ClKIN

56

57
58
3

4

Figure 8. Interface Connection Using Composite Sync Signal

~TEXAS

2-244

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

EXTClP

ClK

ClPEN
INIT
NT/PAL
TEST

TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A- JULY 1995 - REVISED NOVEMBER 1996

APPLICATION INFORMATION

r----------------------------- ,

Channel-A

r-----'
I PNP: 2SA733 I

16kQ

110 Q

4.3 kQ

TlC5733A

1.8 kn

IL NPN:
_ _2SC1815
_ _ _ .JI

C2
Analog
Signal Input

01+--......---1

1V1(PP)

75Q

470Q

Gain Adjust
5.6kQ

Buffer Amplifier

~-----------------------------~~

©-i
L---I

60

TlC5733A

R1 59

ADC

Buffer Amp

C1

to
Channel-C
C1
2200pF

2

ClP OUT A
OE(A)

I
I

J;

J;

ClPV(A)

L...-_ _--I

Clamp Pulse IN

0

Q

ClKIN

55

56
57
58
3
4

EXTClP

ClK
ClPEN
INIT
NT/PAL
TEST

Figure 9. Interface Using External Clamp Pulse With Synchronization

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-245

TLC5733A
20 MSPS 3-CHANNEL ANALOG·TO·DIGITAL CONVERTER
WITH HIGH·PRECISIONCLAMP

SLAS104A ~ JULY·1995 - REVISED NOVEMBER 1996

APPLICATION INFORMATION
AVDD
-i~

ADC
Block

r----'
RREF

VRT<, the effect of changing MCLK
.
is shown in Table 2-1.
When the device is in master mode, SCLK is derived from MCLK in order to provide clocking of the serial
communications between the sigma-delta audio ADC and a digital signal processor (DSP) or control logic.
This is equivalent to a clock running at 64 x LRClk.
When the device is in slave mode, SCLK is externally derived.

2-257

Table 2-1. Master-Clock to Sample-Rate Comparison
(modes 1, 3,4, 5)
MCLK
(MHz)

2.7

CMODE

12.2880

Low

18.4320

High

11.2896

Low

16.9344

High

8.1920

Low

12.2880

High

0.2560

Low

0.3840

High

SCLK
(MHz)

LRClk
(kHz)

3.0720

48

2.8224

44.1

2.0480

32

0.0640

1

Test

When the TEST input is high, the test mode is selected, which routes the high speed one-bit modulator result
to the serial port output. When in the test mode, the SCLK output frequency is equal to the data output rate.
LRClk is an input when the test mode is selected. This allows for the selection of the left or right modulator
output to be routed to the serial port (high = left and low = right).

2.8

Serial Interface

Although the serial data is shifted out in two seperatetime packets that represent the left and right channels,
the inputs are sampled and converted simultaneously.
The serial interface protocol has master and slave modes each with different read-out modes. The master
mode sources the control signals for conversion synchronization while the slave mode allows an external
controller to provide conversion synchronization signals.
The five master modes are shown in Figures 2-3(a) through 2-3(e) and the three slave modes are shown
in Figures 2-4(a) through 2-4(c). For a 16-bit word, 015 is the most significant bit and DO is the least
significant bit. Unless otherwise specified, all values are in 2s complement format.
In the master mode, SCLK is generated internally and is sourced as an output. The relationship of SCLK
to LRClk is 64x (modes 1, 3, 4, 5) or 32x (modes 6, 7). In the slave mode, SCLK is an input. SCLK timing
must meet the timing specifications listed in the Recommended Operating Conditions section.

2.8.1

Master Mode

As the master, the TLC320AD57C generates LRClk, Fsync, and SCLK from MCLK. These signals are
provided for synchronizing the serial port of a DSP or other control devices.
Fsync designates valid data from the ADC, and accomplishes this in the master modes by one of two
methods. The first method is to place a single pulse on Fsync prior to valid data. This indicates the starting
point for the data. The second method of frame synchronization is to hold Fsync high during the entire valid
data cycle which provides boundaries for the data.
LRClk is generated internally from MCLK. The frequency of this signal is fixed at the sampling frequency
fs [MCLK/256 (CMODE low) or MCLK/384 (CMODE high)]. During the high period of this signal, the left
channel data is serially shifted to the output; during the low period, the right channel data is shifted to the
output. The conversion cycle synchronizes with the rising edge of LRClk.
Five modes are available when the device is configured as a master. Two modes are for 18-bit
communications. These modes differ from each other in that the MSB is transferred first in one mode while
the LSB is transferred first in the second mode [see Figures 2-3(b) and 2-3(c)]. When the LSB is transferred
first, the data is right justified to the LRClk [see Figures 2-3(a) through 2-3(e)]. The three other modes
2-258

available as a master are .16-bit modes. Two of the modes differ as MSB first versus LSB first. These two
modes set SCLK = LRClk x 32. This is one half the frequency used in the other transfer modes [see Figures
2-3(d) and2-3(e)]. The third 16-bit mode provides the data MSB first with one clock delay after LRClk [see
Figure 2-3(a)].
Mode 011

(8) MASTER MODE (Fsync bound)

SCLK
Fayne - - - I - - - - ' f - - - - '

DOUT-_--t_.--,t----'

I Right

LRClk

Mode 100

(b) 18-BIT MASTER MODE

SCLKJ\./)J\..AJ\./\

LRClk

Mode 101

(c) 18-BIT MASTER MODE

SCLK

I

Fayne

--i---";'---i-..J0----;"'-;'/I-,---il---'----;--.;-I----i-II\-\-i-I--i-I-,-,-11

DOUT_-J~~~_~_-£~0~~1~=~:~~1~6~~17~~_~_~r.O~~~1·~~~~~~.~

l

I

LRClk - - - i - - - J f Left

I

I

I 1 1

64 SCLKs

~~R....;i9:;;...h_t

1\

Mode 110

I

I

I

,I

I

---+-I---i--;I~

'1-1

(d) DSP CONTINUOUS MODE

DOUT_~'I...---Jl~1~5~~1~4~'~~~~~1~0~~~15~~1~4~~''''';''~~~1~1~0~~1~5~,

I

'32SCLKs

LRClk _ _+-___ CLeft

1

Mode 111

1

\.

1

1

I

Right

I

II

1

1

'I

I

I

I

'I

i

y----j

(e) DSP CONTINUOUS MODE

SCLK~

Fayne~~1-~-4----I---+---+-I'
DOUT

I

0

I

LRClk
"

14

Left

I

1\

15

0

132SCLKS
" Right
I
1

II
I

14

I

II

15

I

0

rI

Figure 2-3. Serial Master Transfer Modes

2-259

2.8.2

Slave Mode

As a slave, the TLC320AD57C receives LRClk, Fsync, and SCLK as inputs. The conversion cycle
synchronizes to the rising edge of LRClk, and theda~a synchronizes to the falling edge of SCLK. SCLKmust
meet the setup time requirements specified in Section 3.2, Recommended Operating Conditions.
Synchronization of the slave modes is accomplished with the digital power-down control.
In slave mode, Fsync is an input. Three modes are provided as shown in Figures 2-4(a) through 2-4(c).
SCLK and LRClk are externally generated and sourced. The first rising edges of SCLK and LRClk after a
power-down cycle initiate the conversion cycle. Refer to Section 2.8.1, Master Mode for signal functions.
Several modes are available when the TLC320AD57C is configured as a slave. Using the ModeO, Mode1,
and Mode2 terminals, the TLC320AD57C can be set to shift out the MSB first or the LSB first [see Figures
2-4(a) and 2-4(b)]. The number of bits shifted out can be controlled by the number of valid SCLK cycles
provided within the left or right channel period. If only enough clocks are provided to shift out 16 data bits
before LRClk changes state, this is equivalent to a 16-bit mode.
Mode 000
SCLK /"'I\. /"'I\. /"'I\. .iii. /"'I\. /"'1\..
, i~Pift I""' I""' I""' I ""' I '"I
Fsync i~put I
I I I I II
DOUT
LRClk

Mode 001
SCLK

Fsync
DOUT
LRClk

output I

I
I
i~put I

I

I

I

I
~.. I

0
~~~~~--+-~~~~~-~~~~~~-+--+~7-~

11L

I

(8) SLAVE MODE (Fsync high)

ftl

1e I

I
I

I',

I
I
(b) SLAVE MODE (Fsync high)

l1v1v1v-IV-IVl'-./]\fM
1
1

I

1
1

I

1
1

I

iii

1
I

I
I

I

I

~Lefti

1
1

I

1

1

1

1
I

1

1

1

1

~~.~:J2~..:..1::-::7~;>--r-__;---+-~;~~'~
'--1-1'""' I i 64 SCLKs _i---+--+_+I_l""'.;-II-r-11--r.--li

iii

i II i

1

~..;.;R;,;jiIlg~rt~f---I-~-l-i-II~,,-+i-+i---'If

(c) SLAVE MODE (Fsync controlled)
Fsync(l)

I~

-+__+--+__+-__

1

DOUT(2)

~--~~--~-'f-

~II

1

1

I

I-i--+--+---+--+-I-+-1----Lr"

~
: ! ~* ·f· Pi i f
321-12V~~gr~

1:

LRClk - t - - - t - - + - ;.---I---i---t---r--t----+-:

'1

Figure 2-4. Serial Slave Transfer Modes

2-260

1'\

: k 1:7b~
i i }
I I { I I

DOUT(l) -t---t---t---"'I--'fFsync(2) --r---r---r---...----

1

:

',I:

::

:

:.

(

3 Specifications
3.1

Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)t
Analog supply voltage range, AVoo (see Note 1) ................... -0.3 V to 6.5 V
Digital supply voltage range, DVoo (see Note 2) ................... -0.3 V to 6.5 V
Digital output voltage range, (externally applied) ........... -0.3 V to DVoo + 0.3 V
Digital input voltage range, MODEO - MODE2 ............ -0.3 V to DVoo + 0.3 V
Analog input voltage range, INLP, INLM, INRP, INRM ...... -0.3 V to AVoo + 0.3 V
Operating free-air temperature range, TA ............................. O°C to 70°C
Storage temperature range, Tstg ................................ -65°C to 150°C
Case temperature for 10 seconds, TC .......................... ~ .......... 260°C
Lead temperature 1,6 ~~ for 10 seconds .............. 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for
extended periods may affect device reliability.
NOTES: 1. Voltage values for maximum ratings are with respect to AVSS.
2. Voltage values for maximum ratings are with respect to DVSS.

3.2

Recommended Operating Conditions
MIN

NOM

MAX

UNIT

4.75

5

5.25

V

Digital supply voltage, DVDD

4.75

5

5.25

V

Analog logic supply voltage, at Vlogic

4.75

5

5.25

V

Analog supply voltage, AVDD (see Note 3)

3.2

V

Setup time, DigPDJ. to LRClki, slave mode, tsu1 (see Figure 2-1 (a»

30

ns

Setup time, DigPDJ. to LRClki, master mode, tsu2 (see Figure 2-1 (b»

30

ns

Reference voltage, Vref

Setup time, SCLKi to LRClk, slave mode, tsu3 (see Figures 4-5 and 4-6)

30

ns

Setup time, LRClk to SCLKi, slave mode, tsu4 (see Figure 4-5)

30

ns

Setup time, SCLKi to Fsync, slave mode, tsu5 (see Figure 4-6)

30

ns

Setup time, Fsync to SCLKi, slave mode, tsu6 (see Figure 4-6)

30

Load resistance at DOUT, RL
Operating free-air temperature, TA

ns

kn

10
0

70

°C

NOTE 3: Voltages at analog inputs and outputs and AVDD are with respect to the AVSS terminal.

2-261

3.3

Electrical Characteristics

3.3.1

Digital Interface, TA = 25°C, AVoo = DVoo = 5 V
PARAMETER

VIH

TEST CONDITIONS

MIN

TYP

2

4.6

2.4

4.6

High-level input voltage

VIL

Low-level inputvoltage

VOH

High-level output voltage, DOUT

VOL

Low-level output voltage, DOUT

0.2
IOH=2mA

0.2

10L = 2 rnA

MAX

UNIT
V

0.8

V
V

0.4

V

IIH

High-level input current, any digital input

1

IlL
Cj

Low-level input current, any digital input

1

ItA
ItA

Input capacitance

5

pF

Co

Output capacitance

5

pF

3.3.2

Analog Interface

3.3.2.1

ADC Modulator, TA = 25°C, AVoo = DVoo = 5 V, fs
HPByp = 1, CMODE = 0, MODEO - 2 = 101
PARAMETER

= 48 kHz, Bandwidth = 24 kHz,

TEST CONDITIONS

MIN

Resolution

TYP

MAX

UNIT

18

Bits

93

97

dB

9;

95

dB

91

dB

DYNAMIC PERFORMANCE
Signal to noise (EIAJ)
Dynamic range
Signal to noise + distortion (THO + N)
Total harmonic distortion (THO)
Interchannel isolation

INLP = INRP = 2.5 V dc
INLM = INRM = 2.5 V dc
-1 dB down from
6-V differential input between
INRP (INLP) and INRM (INLM)

0.001%
108

dB

Gain error

±O.2

dB

Interchannel gain mismatch

±0.2

dB

DC ACCURACY

Offset error (18-bit resolution)
Offset drift

2-262

±5
±0.17

mV
LSB/oC

3.3.2.2

Inputs/Supplies, TA = 25°C, AVOO
HPByp = 1

= DVoo = 5 V, fs = 48 kHz,

PARAMETER

TEST CONDITIONS

MIN

Bandwidth
TYP

= 24 kHz,

MAX

UNIT

ANALOG INPUT
Input voltage

Differential input

6.4

Single-ended input

3.2

Input impedance

V
kQ

50

POWER SUPPLIES

Power-supply current

IDD (analog), operating

22

30

mA

IDD (digital), operating

24

32

mA

IDD (analog), power down

100

IDD (digital), power down

40

I-1A

230

mW

Power dissipation

3.3.3

Channel Characteristics, TA

=25°C, AVoo=DVoo =5 V, fs = 48 kHz, HPByp =1

PARAMETER

TEST CONDITIONS

Passband (-3 dB)

HPByp = 0

Passband ripple

30 Hz - 21.8 kHz

Stopband attenuation

26.2 kHz - 3046 kHz

TYP

MIN
0.001

MAX
24

±0.01

UNIT
kHz
dB

80

dB

Group delay

3.4

I-1A

s

25/Fs

Switching Characteristics
PARAMETER

MIN

TYP

MAX

td1

Delay time, AnaPD,l, to DOUT valid (see Figure 2-1 (c))

td(MFSD)

Delay time, SCLK,l, to Fsync, master mode
(see Figures 4-1,4-2,4-3, and 4-4)

-20

20

td(MDD)

Delay time, SCLK,l, to DOUT, master mode
(see Figures 4-1, 4-2, 4-3, and 4-4)

0

50

td(MIRD)

Delay time, SCLK,l, to LRClk, master mode
(see Figures 4-2 and 4-4)

-20

20

td(SDD1)

Delay time, LRClk to DOUT, slave mode (see Figure 4-5)

50

td(SDD2)

Delay time, SCLK,l, to DOUT, slave mode
(see Figures 4-5 and 4-6)

50

UNIT
ns

30

ns
ns
ns
ns
ns

2-263

2-264

4 Parameter Measurement Information
SCLK
td(MFSD)
Fsync
td(MDD)

I~

I
I
I

I~

·1

I
I

~

X
X. . _____________________

DOUT

MSB-1

MSB

X

LRClk _ _ _ _ _ _ _

Figure 4-1. SCLK to Fsync and DOUl - Master Mode 3

SCLK
to{MFSD)

~j

I

i\

Fsync
td(MDD)

~

I

I
I

DOUT
td(MIRD)

I~

LRClk

·1

I

MSB

X

MSB-1

X

.1

X

Figure 4-2. SCLK to Fsync, DOUl, and LRClk - Master Modes 4 and 6

SCLK~

Fsync

..,(M::=:;
td(MDD)

DOUT~

(

~J

1\
I ~.-------------------------I~

~

"~-LS-B--X~_L_SB_-_1__)(~_______

LRClk~(J
Figure 4-3. SCLK to Fsync, DOUl, and LRClk - Master Mode 5

2-265

SCLK
td(MFSD)
Fsync

~J""""---:~

:\~------------------.1

.

td(MDD) ,...

DOUT ________________________+:__~"_~_-_L=S=B~=)(~_L_S_B_-_1__J)(~

.1

td(MIRD):'"
LRClk

_____

.
-----------------~/~-----------------Figure 4-4. SCLK to Fsync, DOUT, and LRClk - Master Mode 7

,

SCLK

:
LRClk

,

---------J*"'--------....;...-----------:f---:------------I
td(SDD1)~

DOUT ________________

td(SPD2)--i+--+l

~;'_~_-_17==~~~~~)(

)(~._________~

16

Figure 4-5. SCLK to LRClk and DOUT - Slave Mode 0, Fsync High

tsu3

.
',

tsus

.1,. .

tsu6

SCLK

I
I
I

Fsync

I,
17
V
,

DOUT

LRClk

td(SDD2)-*-1

X

)
Figure 4-6. SCLK to Fsync, LRClk, and DOUT - Slave Mode 2, Fsync Controlled

2-266

>C

TLC320AD58C
Data Manual

Sigma-Delta Stereo Analog-to-Digital Converter

SLAS102
May 1995

•
TEXAS
INSTRUMENTS

Printed on Recycled Paper

IMPORTANT NOTICE
Texas Instruments (TI) reserves therightto make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality
control 'techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
.
.,
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL .A:PPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.

Copyright © 1995, Texas Instruments Incorporated

Contents
Section

Title

Page

1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.1 Features............................................ . . . . . . . . . . . . . . ..
1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.3 Terminal Assignments ................................................
1.4 Ordering Information .................................................
1.5 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

2-271
2-271
2-271
2-272
2-272
2-272

2

Detailed Description .....................................................
2.1 Power-Down and Reset Functions .....................................
2.1.1 Power Down ..................................................
2.1.2 Reset Function ................................................
2.2 Differential Input .....................................................
2.3 Sigma-Delta Modulator ...............................................
2.4 Decimation Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.5 High-Pass Filter .....................................................
2.6 Master-Clock Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.7 Test................................................................
2.8 Serial Interface ......................................................
2.8.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.8.2 Slave Mode ...................................................

2-275
2-275
2-275
2-275
2-276
?-277
2-277
2,-277
2-277
2-277
2-277
2-278
2-279

3

Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range '"
3.2 Recommended Operating Conditions ...................................
3.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.3.1 Digital Interface, TA = 25°C, AVoo = DVoo = 5 V ..................
3.3.2 Analog Interface ...............................................
3.3.3 Channel Characteristics, TA = 25°C, AVOO = DVOO = 5 V,
fs = 48 kHz ..... ".........................................". . . . ..
3.4 Switching Characteristics .............................................

2-281
2-281
2-281
2-282
2-282
2-282
2-283
2-283

4

Parameter Measurement Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-285

5

Application Information .................................................. 2-287

2-269

List of Illustrations
Figure

Title

Page

2-1.
2-2.
2....;3.
2-4.

Power-Down Timing Relationships ........ , ................................
Differential Analog Input Configuration .....................................
Serial Master Transfer Modes ........................ ~ . . . . . . . . . . . . . . . . . . ..
Serial Slave Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

2-276
2-276
2-279
2-280

4-1.
4-2.
4-3.
4-4.
4-5.
4-6.

SCLK to
SCLK to
SCLK to
SCLK to
SCLK to
SCLK to

2-285
2-285
2-285
2-286
2-286
2-286

Fsync and DOUT - Master Mode 3 ................................
Fsync, DOUT, and LRClk - Master Modes 4 and 6 . . . . . . . . . . . . . .. . . ..
Fsync, DOUT, and LRClk - Master Mode 5 .........................
Fsync, DOUT, and LRClk - Master Mode 7 .........................
LRClk and DOUT - Slave Mode 0, Fsync High ......................
Fsync, LRClk, and DOUT - Slave Mode 2, Fsync Controlled ... , . . . . ..

5:-1. TLC320AD58C Configuration Schematic ................................... 2-288
5-2. TLC320AD58C External Digital Timing and Control-Signal Generation Schematic 2-289
5-3. TLC320AD58C External Analog Input Buffer Schematic .......... ,........... 2-290

List of Tables
Table

2-1.

2-270

Title

Page

Master-Clock to Sample-Rate Comparison ............................... 2-277

1 Introduction
The TLC320AD58C provides high-resolution signal conversion from analog to digital using oversampling
sigma-delta technology. This device consists of two synchronous conversion paths. Also included is a
decimation filter after the modulator as shown in the functional block diagram. Other functions provide
analog filtering and on-chip timing and control.
A functional block diagram of the TLC320AD58C is included in Section 1.2. Each block is described in the
detailed description section.

1.1

1.2

Features
•

Single 5-V Power Supply

•

Sample Rates up to 48 kHz

•

18-Bit Resolution

•

Signal-to-Noise Ratio (EIAJ) of 97 dB

•
•

Dynamic Range of 95 dB
Total Signal-to-Noise+Distortion of 95 dB

•

Internal Reference Voltage (Vref)

•

Serial-Port Interface

•

Differential Architecture

•

Power Dissipation of 200 mW. Power-Down Mode for Low-Power Applications

•

One-Micron Advanced LinEPIC1 ZTM Process

Functional Block Diagram
INLP
INLM

DOUT
Fsync

REFO~
REFI
Serial
Interface

INRP

LRClk
OSFR

INRM

OSFL

MCLK
CMODE
MODE(O-2)

CONTROL
SCLK

LinEPIC1 Z is a trademark of Texas Instruments Incorporated.
2-271

Terminal Assignments

1.3

OW PACKAGE
(TOP VIEW}
INLP

INRP

INLM

INRM

REFI

REFO

AVDD

LGND

AVSS
AnaPD

Vlogic

TEST1

NC
MODE1

MODE2

OSFR

OSFL

MCLK

DigPD

DVSS

TEST2

DVDD
Fsync

CMODE
MOOED

DOUT

LRClk

SCLK

NC - No internal connection

Ordering Information

1.4

PACKAGE

1.5

TA

SMALL OUTLINE
(OW)

O°C to 70°C

TLC320AD58CDW

Terminal Functions
TERMINAL

NAME

NO.

1/0

DESCRIPTION

I

Analog power-down mode. The analog power-down mode disables the analog
modulators. The single-bit modulator outputs become invalid, rendering the outputs of the
digital filters invalid. When AnaPD is pulled high, normal. operation of the device is
resumed.

AnaPD

6

AVDD

4

I

Analog supply voltage

5

I

Analog ground

CMODE

12

I

Clock mode. CMODE is used to select between two methods of determining the master
clock frequency. When CMODE is high, the master clock input is 384x the conversion
frequency. When CMODE is low, the master clock input is 256x the conversion frequency.

DOUT

16

0

Data output. DOUT is used to transmit the sigma-delta audio ADC output data to a DSP
serial port or other compatible serial interface and is synchronized to SCLK. This output
is low when DigPD is high.

DVDD

18

I

Digital supply voltage

DVSS

19

I

Digital ground

DigPD

10

I

Digital power-down mode. The digital power-down mode shuts down the digital filters and
clock generators. All digital outputs are brought to unasserted states. When DigPD is
pulled high, normal operation of the device is resumed.

Fsync

17

I/O

AVSS

2-272

Frame sync. Frame sync is used to designate the valid data from the ADC.

1.5

Terminal Functions (Continued)
TERMINAL

NAME
INLM
INLP

NO.

1/0

DESCRIPTION

2

I

Inverting input to left analog input amplifier
Noninverting input to left analog input amplifier

1

I

INRM

27

I

Inverting input to right analog input amplifier

INRP

28

I

Noninverting input to right analog input amplifier

LGND

25

I

Logic power supply ground for analog modulator

LRClk

14

1/0

Left/right clock. LRClk signifies whether the serial data is associated with the left channel
ADC (when LRClk is high) or the right channel ADC (when LRClk is low). LRClk is low
when DigPD is low.

MCLK

20

I

Master clock. MCLK is used to derive all the key logic signals of the sigma-delta audio
ADC. The nominal input frequency range is 18.432 MHz to 256 kHz.

13,22,
8

I

Serial modes. MODE(0-2) configure this device for many different modes of operation.
The different configurations are:
Master versus slave
16 bit versus 18 bit
MSB first versus LSB first
Slave: Fsync controlled versus Fsync high
Each of these modes is described in the serial interface section along with timing
diagrams.
MODE MASTERI
MSB/LSB
012
SLAVE
BITS
FIRST
000
slave
up to 18
MSB
001
slave
18
LSB
010
slave
up to 18
MSB
1 1
master
16
MSB
100
master
18
MSB
1 0 1
master
18
LSB
110
master
16
MSB
1 1 1
master
16
LSB

MODE(0-2)

o

OSFL,
OSFR

9, 21

0

Over scale flag left/right. If the left/right channel digital output exceeds full scale output
range for two consecutive conversions, this flag is set high for 4096 LRClk periods.
OSFL and OSFR are low when DigPD is low.

SCLK

15

1/0

Shift clock. If SCLK is configured as an input, SCLK is used to clock serial data out of
the sigma-delta audio ADC. If SCLK is configured as an output, SCLK stops clocking
when DigPD is low.

TEST1

7

I

Test mode 1. TEST1 should be low for normal operation.

TEST2

Test mode 2. TEST2 should be low for normal operation.

11

I

REFI

3

I

Input voltage for modulator reference (normally connected to REFO, terminal 26).

REFO

26

I

Internal voltage reference

Vlogic

24

I

Logic power supply voltage (5 V) for analog modulator

2-273

2-274

2 Detailed Description
The sigma-delta converter allows for simple antialias external filtering. Typically, a first order RC filter is
sufficient.

2.1
2.1.1

Power-Down and Reset Functions
Power Down

The power-down state is comprised of a separate digital and analog power down. The power consumption
of each is detailed in the electrical characteristics section.
The digital power-down mode shuts down the digital filters and clock generators. All digital outputs are set
to an unasserted level. When the digital power-down terminal is pulled high, normal operation of the device
is initiated. In slave mode, the conversion process must synchronize to an input on the LRClk terminal as
well as the SCLK terminal. Therefore, tha conversion process is not initiated until the first rising edges of
both SCLK and LRClk are detected after DigPD is pulled high. This synchronizes the conversion cycle; all
conversions are performed at a fixed LRClkrate [MCLK/256 (CMODE low) or MCLK/384 (CMODE high)]
after the initial synchronization. After the digital power-down terminal is brought high, the output of the digital
filters remains invalid for 50 LRClk cycles [see Figures 2-1 (a) and 2-1 (b)].
In master mode, LRClk is an output; therefore, the conversion process initiates based on internal timing.
The first valid data out occurs as shown in Figure 2-1 (c).
The analog power-down mode disables the analog modulators. The single-bit modulator outputs become
invalid which renders the outputs of the digital filters invalid. When the analog power-down terminal is
brought high, the modulators are brought back online; however, the outputs of the digital filters require 50
LRClk cycles for valid results.

2.1.2

Reset Function

The conversion process is not initiated until the first rising edges of both SCLK and LRClk are detected after
DigPD is pulled high. This synchronizes the conversion cycle; all conversions are performed at a fixed LRClk
rate [MCLK/256 (CMODE low) or MCLK/384 (CMODE high)] after the initial synchronization.

2-275

r-

DigPD

Y

tsus

-.I--

I

LRClk

Slave-Mode Digital Power Down

:I

\ ....._-"/
I

DOUT

Data Valid

(a)

DigPD

~ tsu6 ---.II
I
I

Master-Mode Digital Power Down

Y

I

LRClk

\'-------'/

DOUT

/

Data Valid

(b)
I..

I

AnaPD

Y

td1

.!

I
I

Analog Power Down

I

DOUT ~~
_ _"lII:'._~."'lII:"'lI'I~i""lII:"'l'~~I~----------(c)

Figure 2-1. Power-Down Timing Relationships

2.2

Differential Input

The input is differential in order to provide common-mode noise rejection and increase the input dynamic
range. Figure 2-2 shows the analog input· signals used in a differential configuration to achieve a
6.4 VI(PP) differential swing with a 3.2 VI(PP) swing per input line. Both a differential and a single-ended
configuration are shown in the application information section.
TLC320ADS8
4.1 V

2.SV

INLP,INRP

0.9V

4.1 V

2.SV

INLM,INRM

0.9 V

Figure 2-2. Differential Analog Input Configuration

2-276

2.3

Sigma-Delta Modulator

The modulator is a fourth-order sigma-delta modulator with 64 times oversampling. The ADC provides
high-resolution, low-noise performance from a one-bit converter using oversampling techniques.

2.4

Decimation Filter

The decimation filter used after the sigma-delta modulator reduces the digital data rate to the sampling rate
of LRClk. This is accomplished by decimating with a ratio of 1:64. The output of this filter is a 2s complement
data word of up to 18 bits serially clocked out.
If the input value exceeds the full range of the converter, the output of the decimator is held at the appropriate
extreme until the input returns to the dynamic range of this device.

2.5

High-Pass Filter

The high-pass filter removes dc from the input.

2.6

Master-Clock Circuit

The master-clock circuit is used to generate and distribute necessary clocks throughout the device. MCLK
is the external master clock input. CMODE is used to select the relationship of MCLK to the sample rate of
LRClk. When CMODE is low, the sample rate of the data paths is set as LRClk = MCLKJ256. When CMODE
is high, the sample rate is set as LRClk = MCLKJ384. With a fixed oversampling ratio of 64><, the effect of
changing MCLK is shown in Table 2-1.
When the TLC320AD58C is in master mode, SCLK is derived from MCLK in order to provide clocking of
the serial communications between the sigma-delta audio ADC and a digital signal processor (DSP) or
control logic. This is equivalent to a clock running at 64 x LRClk.
When the TLC320AD58C is in slave mode, SCLK is externally derived.
Table 2-1. Master-Clock to Sample-Rate Comparison
(Modes 1, 3, 4, 5)
MCLK
(MHz)

2.7

CMODE

12.2880

Low

18.4320

High

11.2896

Low

16.9344

High

8.1920

Low

12.2880

High

0.2560

Low

0.3840

High

SCLK
(MHz)

LRClk
(kHz)

3.0720

48

2.8224

44.1

2.0480

32

0.0640

1

Test

TEST1 and TEST2 are reserved for factory test and should be tied to digital ground (DVss).

2.8

Serial Interface

Although the serial data is shifted out in two seperate time packets that represent the left and right channels,
the inputs are sampled and converted simultaneously.
The serial interface protocol has master and slave modes each with different read out modes. The master
mode is used to source the control signals for conversion synchronization, while the slave mode allows an
external controller to provide conversion synchronization signals.
The five master modes are shown in Figures 2-3(a) through 2-3(e), and the three slave modes are shown
in Figures 2-4(a) through 2-4(c). For a 16·bit word, 015 is the most significant bit and DO is the least
Significant bit. Unless otherwise specified, all values are in 2s complement format.
2-277

In master mode, SCLK is generated internally and is sourced as an output. The relationship of SCLK to
LRClk is 64x (modes 1, 3, 4, 5) or 32x (modes 6, 7) .. In slave mode, SCLK is an input. SCLK timing must
meet the timing specifications shown in the recommended operating conditions section.

2.8.1

Master Mode

As the master, the TLC320AD58C generates LRClk, Fsync, and SCLK from MCLK. These signals are
provided for synchronizing the serial port of a digital signal processor (DSP) or other control devices.
Fsync is used to designate the valid data from the ADC, and this is accomplished in the master modes by
one of two methods. The first is a single pulse on Fsync prior to valid data. This indicates the starting point
for the data. The second method of frame synchronization is to hold Fsync high during the entire valid data
cycle, which provides boundaries for the data.
LRClk is generated internally from MCLK. The frequency of this signal is fixed at the sampling frequency
fs [MCLKJ256 (CMODE low) or MCLKJ384 (CMODE high)]. During the high period of this signal, the left
channel data is serially shifted to the output; during the low period, the right channel data is shifted to the
output. The conversion cycle is synchronized with the riSing edge of LRClk.
.

,

Five modes are available when the device is configured as a master. Two modes are for 18-,bit
communications. These modes differ from each other in that the MSB is transferred first in one mode while
the LSB is transferred first in the second mode [see Figures 2-3(b) and 2-3(c)]. When the LSB is transferred
first, the data is right justified to the LRClk [see Figures 2-3(a) through 2-3(e)]. The three other master
modes are 16-bit modes. Once again, two of the modes differ as MSB first versus LSB first. These two
modes set SCLK = LRClk x 32. This is half the frequency used in the other transfer modes· [see
Figures2-3(d) and 2-3(e)]. The third 16-bit mode provides the data MSB first with one clock delay after
LRClk [see Figure 2-3(a)].
.

2-278

Mode 011

(a) 16-BIT MASTER MODE (Fsync bound)

~

SCLK

Fsync_--+-_.....,I_._~~

I

1/

I

i

i \

I Right

I

\11

I \

I

I

I

1

DOUT----r---;I-;==!~=1=5~1t4~,~~~·t=1~jO==16~4SSCJCL~K~S~I=~=1=5j.t=14~~.~~.~1=T=0===r1==~{
LRClk

---+---+-'1f

Left I

I"

I

I

{

(b) 18-BIT MASTER MODE

DOUT
LRClk
Mode 101

(c) 18-BIT MASTER MODE

SCLK

'vVVvV1

Fsync ----r---...,-----;--'

"

LRClk ---r----'

1

1

1

Left

Mode 110

(d) 16-BIT DSP CONTINUOUS MODE

SCLK~

~I

FSync~II---+__--+____+-__-+__~IH'j~
DOUT~~
..-.~~~~0~~~15~~1~4--~~
LRClk

IIIIIIII~
~
1
1 II
32 SCLKs
:
:
:
:

1
1

1 Left

1

Mode 111

~

1

Right 1

H

'i,

1

(e) 16-BIT DSP CONTINUOUS MODE

SCLK~

~I

Fsync~II---+-_-+-_--+_ _+--_+-I1'I~
I
DOUT~'"
10
1
~
LRClk

1
I
I

~t:1===t=1I ===~iii==i===~132gjS!£C~LKS
',I
" Right

; Left
I

I

I

I

I

I
I

I
I,
I \1

I
I

I
I
I

~I

r1

I

1

I

Figure 2-3. Serial Master Transfer Modes

2.8.2

Slave Mode

As a slave, the TLC320AD58C receives LRClk, Fsync, and SCLK as inputs. The conversion cycle is
synchronized to the rising edge of LRClk, and the data is synchronized to the falling edge of SCLK. SCLK
must meet the setup requirements specified in the recommended operating conditions section.
Synchronization of the slave modes is accomplished with the digital power-down control.
In slave mode, Fsync is an input. Three modes are provided as shown in Figures 2-4(a) through 2-4(c).
SCLK and LRClk are externally generated and sourced. The first rising edges of SCLK and LRClk after a
power-down cycle initiate the conversion cycle. Refer to the master-mode section for signal functions.

2-279

Several modes are available when the TLC320AD58C is configured as a slave. Using the ModeO, Mode1,
and Mode2 terminals, the TLC320AD58C can be set to shift out the MSB first or the. LSB first [see Figures
2-4(a) and 2-4(b)]. The number of bits shifted out, however, can be controlled by the number of valid SCLK
cycles provided within the left or right channel period. If only enough clocks are provided to shift out 16 data
bits before LRClk changes state, then this is equivalent to a 16-bit mode. Modes 1 and 2 both require 64
SC.LK periods per LRClk period.
(a) l8-BIT SLAVE MODE (Fsync high)

Mode 000
SCLK

I

I

tput :

I

Fsync

Input

DOUT

°r

1

LRClk

f1V1V1V1V1Vl

~

"put

I
I

I
I

I

I

I

I

I

I

~

J,.

I I I
iI i
ii

I

I

1 Le~

I

DOUT

I

I

I

I

I

I I
I ',I I . I

I
I

I
I

I
I

321':'128~
~

I

\1

I
I

I

I

I

I

~"I

I

?Le~

LRClk

~

I

~
~

I
I

I
I

1\1

I

I
I

r1JM

I
I

17

..

164SCLK~

I

I

I

DOUT_1

::

Fsync_2

I

I

I

y--rii I

I

lk

I

r---HI

I

I

~17: ~~

1

17 :

C I

--+--1---+---1 Le~

I

f~O:
1.\1

I

I
I

I
I

I

I

17

I
I
I

~

f1V1V1V1V1Vl

I

r---r

I

LYI

l

I

I

lk

I

I

I

I

I

I

{,

I

I

i

f

~17: ~~

: : ~17:
I
I

I

I

6

I
I
1\', I

~ RI~ht

SCLK ~
Fsync_1

I

I

(c) l8-BIT SLAVE MODE (Fsync controlled)

Mode 010

::~

f9
: : :

... :

321-128SCL~S
I !
: '1
I ~-.;.;;RI.;;yh;.;..t-+-II1,,\-',-+.-+.-+-.--I.f--4·---,if

Figure 2-4. Serial Slave Transfer Modes

2-280

I

(b) l8-BIT SLAVE MODE (Fsync high)

Fsync

LRClk

I

~-+--+i..--~~

Mode 001
SCLK

DOUT_2

I

3 Specifications
3.1

Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(unless otherwise noted)t
Supply voltage range, AVoo (see Note 1) ......................... -0.3 V to 6.5 V
Supply voltage range, DVoo (see Note 2) ......................... -0.3 V to 6.5 V
Analog input voltage range, INLP, INLM, INRP, INRM ............... -0.3 V to 6.5 V
Operating free-air temperature range, TA ........................... -ooe to 70°C
Storage temperature range, Tstg ................................ -65°C to 150°C
Case temperature for 10 seconds ........................................ 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds .............. 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for
extended periods may affect device reliability.
NOTES: 1. Voltage values for maximum ratings are with respect to AVSS.
2. Voltage values for maximum ratings are with respect to DVSS.

3.2

Recommended Operating Conditions
MIN

NOM

MAX

UNIT

Analog supply voltage, AVDD (see Note 3)

4.75

5

5.25

V

Digital supply voltage, OVOO

4.75

5

5.25

V

Analog logic supply voltage, Vlogic

4.75

5

5.25

V
V

3.2

Reference voltage, Vref
Setup time, SCLKi to LRClk, slave mode, tsu1

30

ns

Setup time, LRClk to SCLKi, slave mode, tsu2

30

ns

Setup time, SCLKi to Fsync, slave mode, tsu3

30

ns

Setup time, Fsync to SCLKi, slave mode, tsu4

30

ns
ns

Setup time, OigPO to LRClki, slave mode, tsu5

30

Setup time, DigPO to LRClki, master mode, tsu6

30

ns

Load resistance at OOUT, RL

10

kQ

Input dc offset range
Operating free-air temperature, TA

-50

0

0

50

mV

70

°C

NOTE 3: Voltages at analog inputs and outputs and AVOD are with respect to the AVSS terminal.

2-281

3.3

Electrical Characteristics

3.3.1

Digital Interface, TA

= 25°C, AVoo = DVoo = 5 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIH

High-level input voltage

VIL

Low-level input voltage

VOR

High-level output voltage at OOUT

IOH = 2 rnA

VOL

Low-level output voltage at OOUT

IOL= 2 rnA

IIH

High-level input current, any digital input

1

IlA

IlL

Low-level input current, any digital input

1

IlA

Ci

Input capacitance

5

pF

Co

Output capacitance

5

pF

3.3.2

2

4.6
0.2

2.4

V
0.8

V

4.6
0.2

V

0.4

V

Analog Interface

3.3.2.1 ADC Modulator, TA = 25°C, AVoo = DVoo = 5 V, fs = 48kHz, Bandwidth = 24 kHz,
CMODE = 0, MODE(0-2) = 000
PARAMETER

TEST CONDITIONS

MIN

TYP

Resolution

MAX

UNIT

18

Bits

100

dB

DYNAMIC PERFORMANCE

ANSI A-weighting filter

Signal to noise (EIAJ)

INLP = INRP = 2.5 V dc
INLM = INRM = 2.5 V dc

96
90

95

dB

-1 dB down from
6-V differential input

88

93

dB

Dynamic range
Signal to noise + distortion (THO + N)
Total harmonic distortion (THO)

0.0015%

Interchannel isolation

120

dB

Absolute gain error

±0.6

dB

Interchannel gain mismatch

±0.2

dB

DC ACCURACY

Offset error (18-bit resolution)
Offset drift

3.3.2.2

120±5

mV

±0.17

LSB/oC

Inputs/Supplies, TA = 25°C, AVoo = DVoo = 5 V, fs = 48 kHz, Bandwidth = 24 kHz
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUT
Input voltage range

(differential)

6.2

(0 to peak)

3.1

Input impedance

V

200

kO

POWER SUPPLIES
24

32

rnA

100 (digital), normal mode

26

32

rnA

100 (analog), power down

250

IlA

100 (digital), power down

150

IlA

250

mW

100 (analog), normal mode
Power-supply current

Power dissipation

2-282

3.3

Electrical Characteristics (Continued)

3.3.3

Channel Characteristics, TA

=25°C, AVoo =DVoo =5 V, fs =48 kHz

PARAMETER

TEST CONDITIONS

Passband (-3 dB)

MIN
0.001

Passband ripple

30 Hz - 21.8 kHz

Stopband attenuation

26.2 kHz - 3046 kHz

MAX
24

±0.01

UNIT
kHz
dB
dB

80

Group delay

3.4

TYP

s

25/fs

Switching Characteristics
PARAMETER

MIN

TYP

MAX

30

UNIT

td1

Delay time, AnaPD to DOUr valid

~(MFSD)

Delay time, SCLK.L to Fsync, master mode

-20

20

ns
ns

td(MDD)

Delay time, SCLK.L to DOUr, master mode

0

50

ns

td(MIRD)

Delay time, SCLK.L to LRClk, master mode

-20

20

ns

~(SDD1)

Delay time, LRClk to DOUr, slave mode

50

ns

td(SDD2)

Delay time, SCLK.L to DOUr, slave mode

50

ns

2-283

2-284

4 Parameter Measurement Information
SCLK
td(MFSD)
Fsync

td(MDD)

I.

~I

1
1
1
14

I
~I

X
X
-JX'--____________________

DOUT

/

MSB

MSB-1

LRClk _ _ _ _ _ _

Figure 4-1. SCLK to Fsync and DOUl - Master Mode 3

SCLK
"'(MFSO)

Fsync

~_ _ _ _ _Ih

J

i\

td(MDD) --..~-"--.t-~I--------------

DOUT _ _ _ _ _ _ _ _ _ _ _ _+i_~"_~=M~S~B~~)("___
M_S_B-_1_J)("__ _ ___
td(MIRD) ---i'I1.1---+l~1

...J)("________________

LRClk _ _ _ _ _ _ _ _ _ _ _ _ _

Figure 4-2. SCLK to Fsync, DOUl, and LRClk - Master Modes 4 and 6

SCLK~
Fsync

~

td(MF(S::J)
.

----....,j

DOUT~

i\~.------------------------1

td(MDD) I.
(

~j

~I

"~LS-B~)(~_L_SB_-_1__)(~_______

LRClk~(j
Figure 4-3. SCLK to Fsync, DOUl, and LRClk - Master Mode 5

2-285

SCLK

,«UFSD)

~)

I

Fsync
td(MDD)

!\
1111

I
I

DOUT

td(MIRD)

~I

/

,'III

LSB

X

LSB-1

X

·1

/

LRClk

Figure 4-4. SCLK to Fsyne, DOUT,and LRClk - Master Mode 7

I
I
I

SCLK

LRClk

----------Xll-----------------~----------..
I.

.I

tct(SDD2)-l4-+i

td(SDD1)~

1

I'--l:-=17======X

DOUT _ _ _ _ _ _ _

Xl:-----~

16

Figure 4-5. SCLK to LRClk and DOUT - Slave Mode 0, Fsyne High
tsu1

.1

I

tsu3

~IIII

I

tsu4

SCLK

I
I
I

Fsync

I
I

V

DOUT

I

LRClk

td(SDD2)--J+--+i

I

17

X

)
Figure 4-6. SCLK to Fsyne, LRClk, and DOUT - Slave Mode 2, Fsyne Controlled

2-286

>C

5 Application Information

2-287

RP

I\)

u..

r6

LM

u..

Co
0
0

Co
0

....

0)
0)

u..

Co
0
0

....

~

I Al:, IAV!,

.....

n

~

~

AVSS1

SN74HC14

LP

.....

EXFS CLK

Shift Register

J-H------f'i:DI-, ODD/EVEN

S
R

~-----~----+-~CLK

SGL/DIF
CHO/IN+ - - - - I Analog

MUX

CH1/1N-

S
Comparator

R

EN

EN

r--;;F!----I

I

(TLV0831

I

L~~~J

Ladder
and
Decoder

Bits 0-7

EN R
SAR
Logic
and
Latch

Bits 0-7
Bit 1

9-Bit
Shift
Register

MSB

~TEXAS

2-292

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

EOC

DO

TLV0831 C, TLV0831I
TLV0832C, TLV08321
3·VOLT 8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 - SEPTEMBER 1996

functional description
The TLV0831 and TLV0832 use a sample-data-comparator structure that converts differential analog inputs by
a successive-approximation routine. The input voltage to be converted is applied to an input terminal and is
compared to ground (single ended), or to an adjacent input (differential). The TLV0832 input terminals can be
assigned a positive (+) or negative (-) polarity. The TLV0831 contains only one differential input channel with
fixed polarity assignment; therefore it does not require addressing. The signal can be applied differentially,
between IN+ and IN-, to the TLV0831 or can be applied to IN+ with IN- grounded as a single ended input. When
the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the
converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of lOW-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. An interval of one clock period is
automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance
state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares
successive outputs from the reSistive ladder with the incoming analog signal. The comparator output indicates
whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds,
conversion data is simultaneously output from ~O, with the most significant bit (MSB) first. After eight clock
periods, the conversion is complete. When CS goes high, all internal registers are cleared. At this time, the
output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-Iow
transition followed by address information.
A TLV0832 input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (01) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. In addition to selecting the differential mode, the polarity
may also be selected. Either channel of the channel pair may be designated as the negative or positive input.
On each low-to-high transition of the clock input, the data on 01 is clocked into the multiplexer-address shift
register. The first logic high on the input is the start bit. A 2-bit assignment word follows the start bit on the
TLV0832. On each successive low-to-high transition of the clock input, the start bit and assignment word are
shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register,
the input channel is selected and conversion starts. The TLV0832 01 terminal to the multiplexer shift register
is disabled for the duration of the conversion.
The TLV0832 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. The 01 and DO
terminals can be tied together and controlled by a bidirectional processor 110 bit received on a single wire. This
is possible because" 01 is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-293

TLV0831C, TLV0831I
TLV0832C, TLV08321
3·VOLT 8-81T ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148-SEPTEMBER 1996

sequence of operation
TlV0831
2

5

4

3

7

6

10

9

8

ClK
t su

~ 1+-11 11

1

ll"l

CS

teonv

1

1 1
________________________ 1
1 1
_ _ _ _~~IJJ
MSB-Flrst Data
1 1 I..
1+-1
-+I

~~~~

MUX
Settling Time

---,

~Irr~

Hi-Z

DO

JlJlJ1JlJl

1

IMSBI

7

6

I I
5

4

____

~

2

3
TlV0832

I

ClK

....!-,
CS

Lo..

r

2

3

I4

5

6

I

tsu

hJiJ1[tflIl'" " "

y)

I

I

I

~I

~I

I~i~~;;;::

---1
1 ~I I I:': I I I I I I:: I I I

DIF EVEN
MUX

DO

\,~,__~__==~====dr----

!

. 1 I

S~~:tSG;S~;DB~lt
II

(TlV~~!2 J

Settling Time

i r-

MSB-Flrst Data

~

MSB

7

lSB-Flrst Data

lSB

6

•••

MSB

o

2

2

•••

TlV0832 MUX-ADDRESS CONTROL lOGIC TABLE
MUXADDRESS

CHANNEL NUMBER

SGUDIF

ODD/EVEN

CHO

CH1

L
L
H
H

L
H
L
H

+
+

+
+

H = high level, L = low level,
- or + = terminal polarity for the selected input channel

~TEXAS

INSTRUMENTS .
2-294

21

~I

teonv

l~__________.i~____~j\
.

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6

7

Hi-Z

r-

TLV0831 C, TLV0831I
TLV0832C, TLV08321
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 - SEPTEMBER 1996

absolute maximum ratings over recommended operating free-air temperature range (unless
otherwise noted)t
Supply voltage, Vee (see Note 1) ........................................................... 6.5 V
Input voltage range, Vr Logic ............................................... -0.3 V to Vee + 0.3 V
Analog .............................................. -0.3 V to Vee + 0.3 V
Input current, II .......................................................................... ±5 mA
Total input current ....................................................................... ±20 mA
Operating free-air temperature range, TA: e suffix ...................................... ooe to 70°C
I suffix ..................................... -40°C to 85°C
Storage temperature range, Ts1g ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 Jnch) from case for 10 seconds: P package ..................... 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.

recommended operating conditions
Supply voltage, VCC (see clock operating conditions)
High-level input voltage, VIH

MIN

NOM

MAX

2.7

3.3

3.6

2
0.8

V
kHz

10

600

kHz

40%

60%

IVcc=2.7V

1VCC= 3.3V

Clock duly cycle (see Note 2)

V
V

250

low-level input voltage, Vil
Clock frequency, f(ClK)

UNIT

Pulse duration, CS high, twH(CS)

220

ns

Setup time, CS low or TlV0832 data valid before ClKi, tsu

350

ns

Hold time, TlV0832 data valid after ClKi, th
Operating free-air temperature, TA

ns

90

I C suffix
II suffix

0

70

-40

85

°C

NOTE 2: The clock-duly-cycle range ensures proper operation at all clock frequencies. When a clock frequency is used outside the
recommended duly-cycle range, the minimum pulse duration (high or low) is 1 lJ.S.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-295

TLV0831 C, TLV0831I
TLV0832C, TLV08321
3-VOLT 8-BIT ANALOG-TO-DIGITALCONVERTERS WITH SERIAL CONTROL
SLAS148 - SEPTEMBER 1996

electrical characteristics over recommended range of operating free-air temperature, VCC
f(ClK) 250 kHz (unless otherwise noted)

=

=3.3 V,

digital section
eSUFFIX

PARAMETER

VOH

TEST eONDITIONSt

High-level output voltage

MIN

TYP:j:

I SUFFIX
MAX

MIN

Vce =3V,

10H = -360 1lA

2.8

2.4

VCC =3V,

10H =- 1O I1A

2.9

2.8

10L = 1.6 mA

VOL

Low,level output voltage

Vec = 3 V,

IIH

High-level input current

VIH =3.6 V

IlL

Low-level input current

VIL= 0

10H

High-level output
(source) current

At VOH, DO= 0 V,

TA = 25°C

-6.5
8

TYP:j:

MAX

V

0.34

0.4

0.005

1

0.005

1

-0.005

-1

-0.005

-1

-15

-6.5

-16

-15

V
I1A

1lA
mA

10L

Low-level output (sink) current

At VOL, DO= 0 V,

TA = 25°C

VO= 3.3 V,

TA = 25°C

0.01

3

0.01

3

10Z

High-impedance-state output
current (DO)

VO=O,

TA = 25°C

-0.01

-3

-0.01

-3

8

UNIT

-16

mA
I1A

Ci

Input capacitance

5

5

pF

Co

Output capacitance

5

5

pF

t All parameters are measured under open-loop conditions with zero common-mode input voltage.
:1= All

typical values are at V CC = 3.3 V, TA = 25°C.

analog and converter section
PARAMETER
VIC

II(stdby)

Common-mode input voltage

Standby input current (see Note 4)

MIN

See Note 3

-0.05
to
VCC+0.05

TYP:j:

MAX

UNIT
V

On channel

VI =3.3V

Off channel

VI=O

-1

On channel

VI = 0

-1

Off channel
ri(REF)

TEST eONDITIONSt

1

1lA

1

VI =3.3 V

Input resistance to REF

1.3

2.4

5.9

kn

.. With zero common-mode mput voltage .
t All parameters are measured under open-lOOp conditions
All typical values are at VCC = 3.3 V, TA = 25°C.
NOTES: 3. When channel IN- is more positive than channeIIN+, the digital output code is 0000 0000. Connected to each analog input are two
on-Chip diodes that conduct forward current for analog input voltages one diode drop above VCC. Care must be taken during testing
at low VCC levels (3 V) because high-level analog input voltage (3.6 V) can, especially at high temperatures, cause the input diode
to conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed the supply
voltage by more than 50 mY, the output code is correct. To achieve an absolute 0- to 3.3-V input range requires a minimum VCC of
3.25 V for all variations of temperature and load.
4. Standby input currents go in or out of the on or off channels when the AID converter is not performing conversion and the clock is
in a high or low steady-state conditions.

:1=

total device
TYP:j:

MAX

I

TLV0831

0.2

0.75

I

TLV0832

1.5

2.5

PARAMETER
ICC
:1=

Supply current

MIN

All tYPical values are at VCC = 3.3 V, TA = 25°C.

~TEXAS

INSTRUMENTS
2-296

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT
mA

TLV0831 C, TLV0831I
TLV0832C, TLV08321
3·VOLT 8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148-SEPTEMBER 1996

operating characteristics VCC
otherwise noted)

=Vref =3.3 V, f(CLK) =250 kHz, tr =tf =20 ns, TA =25°C (unless

PARAMETER

Common-mode error
tpd

Propagation delay time,
output data after CLKt
(see Note 6)

TVP

MAX

UNIT

±1/16

±1/4

LSB

±1

LSB

Differential mode

±1/16

±1/4

LSB

200

500

80

200

VCC

Total unadjusted error (see Note 5)

MSB-first data

CL = 100 pF

Output disable time, DO after cst

tconv

Conversion time (multiplexer-addressing
time not included)

ns

LSB-first data
CL

tdis

MIN

= 3 V to 3.6 V
Vref = 3.3 V,
TA = MIN to MAX

TEST CONDITIONSt

Supply-voltage variation error

= 10 pF,

CL = 100 pF,

RL=10kn
RL = 2 kn

80

125
250
8

ns
clock
periods

.. with zero common-mode Input voltage. For conditions
.. shown as MIN or MAX, use the
.t All parameters are measured under open-loop conditions
appropriate value specified under recommended operating conditions.
NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
6. The MSB-first data is output directly from the comparator and, therefore, requires additional delay to allow for comparator response
time. LSB-first data applies only to TLV0832.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-297

· TLV0831C, TLV08311
TLV0832C, TLV08321
3-VOLT8-BIT ANALOG~TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLASI48-SEPTEMBER 1996

PARAMETER MEASUREMENT INFORMATION
Vee
elK

--""I

1

-1

~tsu

I

GND

~

~~fl------T-r-----'Q.4v).1
I

I

~th

1

1

GND

---,I\1

vee

elKSO%

Vee

--

~I

1<111

I~

I

~

tsu

1,_-

VOH

---....I~

VOL

DO~~;-

I

Vee

GND

tpd

2V

0.4V

\

Figure 2. Data-Output Timing

GND

Figure 1. TLV0832 Data-Input Timing
Vee
Test
Point
1
Rl
From Output ---tI---t.I--~VVV
Under Test

I

el
(see Note A)

S1

1

~l

lOAD CIRCUIT

-.I

_ _--JCj-1!!0&.. - - - -

GND

~tdls
DO
Output

----90-°'.-\- - - S10pen
lC
S2closed

~ tr

I 1.----- Vee
50% I 90%
---.J!.t1!!"&..---- GND

: , - - - - - Vee
90%

1<111
Vee
GND

DO
Output

VOLTAGE WAVEFORMS

~I

tdis

~1
closed

Vee
10%
- - - - GND

1

S20pen

.

VOLTAGE WAVEFORMS

NOTE A: CL includes probe and jig capacitance.

Figure 3. Output Disable Time Test Circuit and Voltage Waveforms

~TEXAS

2-298

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV0831 C, TLV0831I
TLV0832C, TLV08321
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SlAS148-SEPTEMBER 1996

TYPICAL CHARACTERISTICS
UNADJUSTED OFFSET ERROR

16
ID
Ul

.e

...I

LINEARITY ERROR

vs

vs

REFERENCE VOLTAGE

REFERENCE VOLTAGE
1.5

I ~I!.

VCC= 3.3 V

VI+=VI_=OV

~ClK) = 250 kHz

14
1.25

I

w

12

5'D'"
l

10

ti

ID

~
I

~

8

:::I

'S'
c

'"

6

;s:

4

'"

~

1.0

f

0.75

I

0.5

CD

::J
I

C
:::I

A=25°C

1\

\

2

c
::::i

,

...I

III

0.25

""'-

o

0.01

0.1

1.0

"

10

2

Vref - Reference Voltage - V

Figure 4

Figure 5

LINEARITY ERROR

0.5

0.45

.e

0.4

w
~
m
c

vs

FREE-AIR TEMPERATURE

CLOCK FREQUENCY

1.8 -

0.35

"

...I

I\..

I

"-

~

I
...I

0.3

0.25
-50

-25

o

.1
l
Vref =3.3 V
VCC=3.3V

/

1.6
ID
Ul

::::i

III

2.0

f(ClK) = 250 kHz

~
I

LINEARITY ERROR

vs

I I
Vref = 3.3 V

ID

4

3

Vref _ Reference Voltage - V

~
;e

""

25

0.8

I

0.6

III

i'--

III

85°C /
1.2

VI I
/ /11

/

...I

75

50

If}

1.4

!!!'"

:::i

I

~

/r""

Jt:!i"""

0.4

125oc

If

~oc

0.2
100

o0

100

TA - Free-Air Tempertature - °c

200

300

400

500

600

700

800

f(ClK) - Clock Frequency - kHz

Figure 6

Figure 7

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-299

TLV0831C, TLV0831I
TLV0832C, TLV08321
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 - SEPTEMBER 1996

TYPICAL CHARACTERISTICS
TLV0831
SUPPLY CURRENT

TlV0831
SUPPLY CURRENT

vs

vs

FREE-AIR TEMPERATURE

CLOCK FREQUENCY

0.3

0.5

I

VCC = 3.3 V
TA= 25'C
0.4

'E"

'E"

1:

1:
!!!

I

I

~:I

r;.

5

0.3

()

0.2

2-

C.

Co
Co

Co

:I

:I

If)

If)

I

I

U

u

9

9

0.1 L...-_...l...._--l._ _.L.-_-1..._
-50
-25
25
o
50

~

100

~

0.1

o

___'_.......l

75

0.2

o

100

TA - Free-Air Temperature -'C

200

Figure 9
OUTPUT CURRENT

vs
FREE-AIR TEMPERATURE

r---.,..-----;--,-----,--,...---,
VCC = 3.3 V

16r-~~--~----~---+----+---~

'"
E
I

1: 15.5

~:I

I---~""""-...j;;;;;::::--~-="'"-Io;;;:::---+---~

U

:;

~

o
I
.9

15

1-----+-----+----+----+----+----1
-IOH (DO = 2.4 V)

14.5

~:::::::!~~:::_~;::::::t::=t---1
__
50
75

14L.---1...-~--~-___'

. -50

-25

o

25

TA - Free-Air Temperature -'C

Figure 10

~TEXAS

2-300

400

f(ClK) - Clock Frequency - kHz

FigureS

16.5

300

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

~_~

100

500

TLV0831C, TLV0831I
TLV0832C, TLV08321
3·VOLT 8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 - SEPTEMBER 1996

TYPICAL CHARACTERISTICS
m

UJ

..J

I

~

0.5

"faQ)

.5

0

C

z0

1i

~ -0.5
I!!

~
is

-1
0

32

64

96

128

160

192

224

256

Output Code

Figure 11. Differential Nonlinearity With Output Code
Vref = 3.3 V
TA=25°C
F(CLK) = 250 kHz
VOO = 3.3 V

m

~
I

~

0.5

:!
~

E

f

-0.5 
__--+---+----+--~-+--_+---I__--+_-___I

-1

~

__

o

~

__

32

~

64

_ _- L_ _

~

__

128

96

~

___

160

~

__

192

~_~

224

256

Output Code

Figure 12. Integral Nonlinearity With Output Code
Vref = 3.3 V
TA = 25°C
F(CLK) = 250 kHz
Voo = 3.3 V

-O.5r_--+---+----r---+--~---r_--+_-~

-1

~

o

__

~

32

__

~

64

_ _-L_ _

96

~

__

128

~

_ _ _L __ _

160

192

~_~

224

256

Output Code

Figure 13. Total Unadjusted Error With Output Code

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-301

2-302

TLV0834C, TLV08341, TLV0838C, TLV08381
3-VOLT 8-BIT ANALOG-TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147 - SEPTEMBER 1996

TLV0834 ••. 0 OR N PACKAGE
(TOP VIEW)

•

8-Bit Resolution

•
•

2.7Vt03.6VVcc
Easy Microprocessor Interface or
Standalone Operation

•

Operates Ratiometrically or With VCC
Reference

•

4- or 8-Channel Multiplexer Options With
Address Logic

•
•
•

Input Range 0 V to Vcc With VCC Reference
Remote Operation With Serial Data Link
Inputs and Outputs Are Compatible With
TTL and MOS

•

Conversion Time of 32Jls at
f(ClK) 250 kHz
Functionally Equivalent to the ADC0834
and ADC0838 at 3-V Supply Without the
Internal Zener Regulator Network

•

•

VCC

DI

ClK
CH1

11

CH2
CH3

DGTl GND

SARS
DO
REF

ANlG GND

TLV0838 ••• OW OR N PACKAGE
(TOP VIEW)

CHO
CH1

=

VCC

NC

CS
DI

ClK

Total Unadjusted Error ... ±1 LSB

SARS
DO

CH6
CH7

description

COM
DGTlGND

These devices are 8-bit successive-approximation
analog-to-digital converters, each with an
input-configurable multichannel multiplexer and
serial input/output. The serial input/output is
configured to interface with standard shift registers
or microprocessors. Detailed information on
interfacing with most popular microprocessors is
readily available from the factory.

SE
9

REF

ANlG GND

The TLV0834 (4-channel) and TLV0838 (8-channel) multiplexer is software configured for single-ended or
differential inputs as well as pseudo-differential input assignments. The differential analog voltage input allows
for common-mode rejection or offset of the analog zero input voltage value. In addition, the voltage reference
input can be adjusted to allow encoding of any smaller analog voltage span to the full 8 bits of resolution.
The TlV0834C and TlV0838C are characterized for operation from O°C to 70°C. The TlV08341 and TlV08381
are characterized for operation from -40°C to 85°C.
AVAILABLE OPTIONS
PACkAGE
SMALL
OUTLINE
(0)

SMALL
OUTLINE
(OW)

O'Cte 70'C

TLV0834CD

TLV0838CDW

TLV0834CN

TLV0838CN

-40'C te 85'C

TLV08341D

TLV08381DW

TLV08341N

TLV08381N

TA

~~~~~~~~:fo~:I: S~~rfr~i~~si;e~~~::r: gJ le~:i::t~~m~~~

standard warranty. Production processing dOBS not necessarily include
testing of all parameters.

PLASTICOIP
(N)

~TEXAS

Copyright © 1996. Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-303

~

I

a

.".

Start
ClK
CS
DI
(see Note A)

rIn1:.

ffClF Jhb

,.
R

S R

5-Bit Shift Register

0

~-~
~ ~ ~.
~~

I~~

~~
~

TlC0834 " {
TLC0838

00

m
~

CD~

m

:s::

SARS

.,

m

:n
co
0>

!:4~

.0

-m-.....

..... 1"'"

»<
ZO
»CD
r~

0--

e> .....

.!.j!<

0
. 0
CD
OW

To Internal
Circuits

....UJ

:!J

III

I TlC0838 I
I Only SE I
L ___

""0

w .....

I
UJ

r----,

0

UJ

>
«." I"'"
~

functional block diagram

-CD
eO

ClK

CHO
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM

S

Analog

MUX

R

EN

CS

~:...

r!<
00
OCD
Zw
<~
m

:::a
.....
m

:::a
en

(Tnll

~~
~

Comparator

::E

CS

CS

::::j
:J:

CS

(;I

R

81
REF
Bits 0-7

CS

R
ClK

SAR
logic
and
Latch

Bit 1
MSBI

I lSB

9-Bit
Shift
Register

EOC

DO

en
m
:::a
l>
r
0
0

Z
.....

:::a

0

r

NOTE A: For the TLC0834, DI is input directly to the D input of SELECT1; SELECTO is forced to a high,

TLV0834C, TLV08341, TLV0838C, TLV08381
3·VOLT 8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147 - SEPTEMBER 1996

functional description
The TLV0834 and TLV0838 use a sample-data-comparator structure that converts differential analog inputs by
a successive-approximation routine. Operation of both devices is similar with the exception of SE, an analog
common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal
and is compared to ground (single ended), to an adjacent input (differential), or to a common terminal (pseudo
differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative (-)
polarity. When the signal input applied to the assigned positive terminal is less than the signal on the negative
terminal, the converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A particular input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (01) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel
pairs. For example, channel 0 and channel 1 may be selected as a differential pair. These channels cannot act
differentially with any other channel. In addition to selecting the differential mode, the polarity may also be
selected. Either channel of the channel pair may be designated as the negative or positive input.
The common input on the TLV0838 can be used for a pseudo-differential input. In this mode, the voltage on the
common input is considered to be the negative differential input for all channel inputs. This voltage can be any
reference potential common to all channel inputs. Each channel input can then be selected as the positive
differential input. This feature is useful when all analog circuits are biased to a potential other than ground.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. On each low-to-high transition of the
clock input, the data on 01 is clocked into the multiplexer-address shift register. The first logic high on the input
is the start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of
the clock input, the start bit and assignment word are shifted through the shift register. When the start bit is
shifted into the start location of the multiplexer register, the input channel is selected and conversion starts. The
SAR status output (SARS) goes high to indicate that a conversion is in progress, and 01 to the multiplexer shift
register is disabled for the duration of the conversion.
An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. DO
comes out of the high-impedance state and provides a leading low for one clock period of multiplexer settling
time. The SAR comparator compares successive outputs from the resistive ladder with the incoming analog
signal. The comparator output indicates whether the analog input is greater than or less than the resistive-ladder
output. As the conversion proceeds, conversion data is simultaneously output from DO, with the most significant
bit (MSB) first. After eight clock periods, the conversion is complete and SARS goes low.
The TLV0834 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. When SE is held
high on the TLV0838, the value of the LSB remains on the data line. When SE is forced low, the data is then
clocked out as LSB-first data. (To output LSB first, SE must first go low, then the data stored in the 9-bit shift
register outputs LSB first.) When CS goes high, all internal registers are cleared. At this time, the output circuits
go to the high-impedance state. If another conversion is desired, CS must make a high-to-Iow transition followed
by address information.
01 and DO can be tied together and controlled by a bidirectional processor 1/0 bit received on a single wire. This
is possible because 01 is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-305

TLV0834C, TLV08341, TLV0838C, TLV08381
3-VOLT 8-BITANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147 - SEPTEMBER 1996

sequence of operation
TLV0834
2

4

3

6

5

10

7

11

12

14

15

18

19

21

~

tconv

C~ I
J41

I

I

,

Bit

SGLODD

j I I I
HI-Z

DIF

,

~

,

I

S\

I,

,

,

BiI~~

EVEN

SARS,

Sr\----------~~

I
I

S\

I
tsu +Sign
'
IStart
Bit
SELECT I

,

I,

,
MUX Selliing Time ~

DO-HI-Z_ _

S\

~I

,
I
LSB-First Data ---.I

I

r--

MSB-First Data

~--I..IM_SB.L-I~I::
7

--+l~

Hi-Z
I
2

6

o

2

6

TLV0834 MUX-ADDRESS CONTROL LOGIC TABLE
MUXADDRESS

CHANNEL NUMBER

ODD/EVEN
SELECT BIT 1
CHO CH1 CH2 CH3
SGL/DIF
L
+
L
L
+
L
L
H
+
L
H
L
L
H
H
+
H
L
L
+
+
L
H
H
L
+
H
H
+
H
H
H
H = high level. L = low level. - or + = terminal polarity for the selected Input channel

~TEXAS

2-306

20

J1JUlf1MJlJU1IU1-

,

,

DI

13

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

7

TLV0834C, TLV08341, TLV0838C, TLV08381
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147 - SEPTEMBER 1996

sequence of operation
TLV0838
8

11

12

13

14

15

. 16

17

18

19

20

21

22

23

24

25

26

27

eLK

~H

........- - - tconv

tsu

csl l I

~~\

I

MUX
~
II
Addressing
-I
~l4-tsu
I I
si~n
SEL SEL I I
II Start
BIt Bit Bit I
Bit SGL ODD 1
0

____ __________________________
~

~r-

1114-

DI~

I
I

1111£:0_
I

0lFEVEN10

I

I: III

HI-Z

SARS...,

II

.
S\

rHi-Z

--------i+---------,--~--------------------SE

l ~--------~rl
: : ----~~r\--------------------------------------~I
I I .
I 14--

~I-z------LI I~MS!lBI~I::
Wi

1176

I..

4

MSB-First Data

.1

LSB-Flrst Data

HI-Z

I

IMSBj

I LSBI

r

2101234567

--------i,-------~u~~~~~~~~-----------------

\r\-----------------,

I I

SE
MUXSettlIng
Time

-.I :.I
I
I
1

00 _ _- - - .

..I!

L..-______________________

14--

MSB-Flrst Data

_ _ _ LSB Held

I

I 1 1:
MSB

76

-~~...- - LSB-Flrst Data

I
1

2

I

~I_~LSB:--------L...:-I ~I

:\-,-10:-'-1

---.I

I
I

..L....:1

I

~I-:-,IM~SB

-:-L-1o:-L
1

r

L..------I

34567

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-307

TLV0834C, TLV08341, TLV0838C, TLV08381
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147 - SEPTEMBER 1996

TLV0838 MUX-ADDRESS CONTROL LOGIC TABLE
MUXADDRESS

SELECTED CHANNEL NUMBER

SGL/DIF

ODD/EVEN

1

0

CHO

CHI

+

-

L

L

L

L

L

L

L

H

L

L

H

L

L

L

H

H

L

H

L

L

L

H

L

H

L

H

H

L

L

H

H

H

H

L

L

L

H

L

L

H

H

L

H

L

H

L

H

H

H

H

L

L

H

H

L

H

H

H

H

L

H

H

H

H

-

2

1

0

SELECT

CH2

CH3

+

-

CH4

CH5

+

-

3
CH6

CH7

+

-

-

+

COM

+

-

+

-

+

-

+

-

+
+

-

+

-

+

-

+

-

+
+

-

H = high level,. L = low level, - or + = polanty of externalmput

absolute maximum ratings over recommended operating free-air temperature range (unless
otherwise noted)t
.
Supply voltage, Vee (see Note 1) ........................................................... 6.5 V
Input voltage range: Logic .................................................. -0.3 V to Vee + 0.3 V
Analog ................................................. -0.3 V to Vee+ 0.3 V
Input current, II .......................................................................... ±5 mA
Total input current ....................................................................... ±20 mA
Operating free-air temperature range, TA: e suffix ...................................... ooe to 70 0 e
I suffix ..................................... -40 oe to 85°e
Storage temperature range, T5t9 ................................................... -65°e to 1500 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ..................... 260 0 e

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.

~TEXAS

INSTRUMENTS
2-308

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV0834C, TLV08341, TLV0838C, TLV08381
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SlAS147 - SEPTEMBER 1996

recommended operating conditions
Supply voltage, Vcc (see clock frequency operating conditions)
High-level input voltage, VIH

MIN

NOM

MAX

2.7

3.3

3.6

low-level input voltage, Vil
I VCC =2.7V

Clock frequency, f(ClK)

IVcc=3.3V

0.8

V

250

kHz

10

600

kHz

40%

60%

10

Clock duty cycle (see Note 2)

V
V

2

Clock frequency, f(ClK)

UNIT

Pulse duration, CS high, twH(CS)

220

ns

Setup time, CS low, SE low, or data valid before ClK!, tsu

350

ns

Hold time, data valid after ClK!, th
Operating free-air temperature, TA

90
II suffix

ns

0

70

-40

85

I C suffix

NOTE 2: The clock-duly-cycle range ensures proper operation at all clock frequencies. When a clock frequency
recommended duly-cycle range, the minimum pulse duration (high or low) is 1 Ils.

IS

electrical characteristics over recommended range of operating free-air temperature,
250 kHz (unless otherwise noted)

'(elK)

=

°C

used outside the

Vee =3.3 V,

digital section
PARAMETER

VOH

High-level output voltage

CSUFFIX

TEST CONDITIONSt

MIN

J.lA

VCC= 3 V,

IOH = -360

VCC = 3 V,

10H =-10 IlA
10l = 1.6 mA

Val

low-level output voltage

VCC = 3 V,

IIH

High-level input current

VIH =3.6 V

III

low-level input current

Vll= 0

10H

High-level output (source) current

At VOH, DO = 0 V, TA = 25°C

TYP*

I SUFFIX
MAX

MIN

2.8

2.4

2.9

2.8

TYP*

MAX

V
0.4

V

0.005

1

IlA

-0.005

-1

IlA
mA

0.34

-6.5

0.005

1

-0.005

-1

-15

-6.5

-15

10l

Low-level output (sink) current

A t Val, DO = VCC, TA = 25°C
Va =3.3 V,

TA = 25°C

0.01

3

0.01

3

10Z

High-impedance-state output
current (DO or SARS)

VO=O,

TA=25°C

-0.01

-3

-0.01

-3

16

8

8

UNIT

mA

16

IlA

Ci

Input capacitance

5

pF

Co

Output capacitance

5

pF

..

..

t All parameters are measured under open-loop condlllOns with zero common-mode mput voltage (unless otherwise specified) .
* All Iypical values are at VCC = 3.3 V, TA = 25°C.

-!!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-309

TLV0834C, TLV08341, TLV0838C, TLV08381
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147-SEPTEMBER 1996

analog and converter section
PARAMETER
VIC

TEST CONDITIONSt

Cemmen-mode input veltage

See Nete3
• On channel

II(stdby)

Standby input current (see Nete 4)

ri(REF)

Input resistance te REF

MIN

TYP*

MAX

-0.05
te
VCC+0.05

UNIT
V

VI =3.3 V

1

Off channel

VI = 0

-1

On channel

VI=O

-1

Off channel

VI =3.3V

lIA

1
1.3 \

2.4

5.9

TYP*

MAX

kn

total device
PARAMETER

MIN

Supply current
0.2
0.75
ICC
t All parameters are measured under epen-Ieep cenditiens with zere commen-mede input veltage.
=!: All typical values are at VCC = 3.3 V, TA = 25°C.
NOTES: 3. When channel IN- is mere pesitive than channeIIN+, the digital .output cede is 0000 0000. Cennected te each analeg input are
twe en-chip diedes that conduct ferward current fer analeg input veltages .one diede drop abeve VCC. Care must be taken during
testing at lew VCC levels (3 V) because high-level analeg input veltage (3.6 V) can, especially at high temperatures, cause the input
diede te conduct and cause errers fer analeg inputs that are near full scale. As leng as the analeg veltage dees net exceed the supply
veltage by mere than 50 mV, the .output cede is cerrect. Te achieve an abselute 0- te 3.3-V input range requires a minimum VCC .of
3.25 V fer all variatiens .of temperature and lead.
4. Standby input currents ge in .or .out .of the en .or .off channels when the ND converter is net perferming cenversien and the cleck is
in a high .or lew steady-state cenditien.

operating characteristics, VCC
(unless otherwise noted)
.

=3.3 V, f(CLK) =250 kHz, tr =tf =20 ns, TA =25°C
TEST CONDITIONS§

PARAMETER
Supply-veltage variatien errer

VCC = 3 V te 3.6 V

Tetal unadjusted errer (see Nete 5)

Vre f=3.3 V, TA = MIN te MAX
Differential mede

Cemmen-mede error

I MSB-first data
I lSB-first data

tpd

Prepagatien delay time,
.output data alter ClK'\' (see Nete 6)

Idis

Output disable time, DO .or SARS alter cst

tcenv

Cenversien time (multiplexer-addressing time net included)

MIN

TYP

MAX

UNIT

±1/16

±1/4

lSB

±1/16

±1

lSB

±1/4

lSB

500

Cl = 100pF

200

Cl= 10pF,

Rl=10kn

80

Cl = 100 pF,

Rl= 2kn

250

..

8

..

ns
ns
clock
perieds

§ All parameters are measured under epen-Ieep cendltlOns with zere cemmen-mede Input veltage. Fer cendltlens shewn as MIN .or MAX, use the
apprepriate value specified under recommended .operating cenditiens.
NOTES: 5. Tetal unadjusted errer includes .offset, full-scale, linearity, and multiplexer errers.
6. The MSB-first data is .output directly frem the comparater and, therefere, requires additienal delay te allew fer cemparater respense
time.

~TEXAS

2-310

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV0834C, TLV08341, TLV0838C, TLV08381
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147 - SEPTEMBER 1996

PARAMETER MEASUREMENT INFORMATION
,
.ClK

_ _.II

,rr-----:-r------1

os

--1

' - - - - GND.

~tsu

I

0.4 V).

I\

~

I

2V

01

I

VCC

GND

1-.1
\

th

------,
I

~tsu

~---VCC

\

\\

\

......""'"0.4
....V......._--I._.Q,'!.Y - - - -

GND

Figure 1. Data-Input Timing

VCC

ClK
1

14

GND

\

.\

tpd

i4-

tpd - . :

\

\

--...,\I,r-------------+"'~ Vec
DO ____

J1f\.

50%

:

",-~./. GND

\

tsu

-+I

i+---

~o_:;. -

SE - - - - - - - - - - " " ' ' \

- - Vee

.

GND

Figure 2. Data-Output Timing

~TEXAS .

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-311

TLV0834C, TLV08341, TLV0838C, TLV08381
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147 - SEPTEMBER 1996

PARAMETER MEASUREMENT INFORMATION

Vcc
Test
Point

S1

6

From Output ~,-______-,\RI'vLI\r-_ _"
Under Test

I

CL
(see Note A)

LOAD CIRCUIT

l!,----

---.I
CS

/4-- tr

50~1

t ----

---.I
VCC

90%
_ _....._'+ 10°&.. ~ ~ __ GND

CS

50%~ 90%
1

~tdis.
1----Vcc

. 90%
~
S!.~~______
GND

S10pen

14 .1
DO and

1
1

tdis

SARS~1
closed

VOLTAGE WAVEFORMS

S20pen

VOLTAGE WAVEFORMS

Figure 3. Output Disable Time Test Circuit and Voltage Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265

VCC

10%
- - - - GND

NOTE A: CL includes probe and jig capacitance.

2-312

vcc

_ _....._'+10°&..- ___ GND

1

DOandSARS

~ tr

TLV0834C, TLV08341, TLV0838C, TLV08381
3·VOLT 8·BIT ANALOG·TO·DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147 - SEPTEMBER 1996

TYPICAL CHARACTERISTICS

LINEARITY ERROR

UNADJUSTED OFFSET ERROR

16
III
UI
....I

_I

vs

vs

REFERENCE VOLTAGE

REFERENCE VOLTAGE
1.5

I 1__" ""

- VI(+) = VI(_) = 0 V
14
1.25

I

VCC= 3.3 V
~CLK) = 250 kHz
A = 25°C

~

~

I...

12

~

8

'S'
os
c

6

~

~.

::0

:::l
I

·fc

4

9

2

::0

1.0

I

10

..

.!!

III

c
::::i

~

\

0.75

0.5

I
....I

w

"-

'-...

0.25

"'""-

o

0.01

0.1

10

2

Figure 4

Figure 5
LINEARITY ERROR

LINEARITY ERROR

0.5

0.45
....I

I

c
::::i

CLOCK FREQUENCY

1.8 -

0.4

....I

I
~

"-

0.35

g

~

....I

0.3

0.25
-50

-25

o

I

I

Vref = 3.3 V
VCC=3.3V

/

1.6
III
UI

I

w

2.0

I

"-r"....

w

~.

vs

FREE-AIR TEMPERATURE

Vref = 3.3 V
f(CLK) = 250 kHz

III
UI

g

vs

I

4

3

Vref _ Reference Voltage - V

Vref - Reference Voltage - V

If
1.4

w

~

"

25

m
c

0.8

I

0.6

::::i

i'-..
50

....I

w

i'
75

J!!

0.4

-

I

1

I VL

85°C
1.2

I

II /
/ II

/ ,I
..../

/25 0 C

/"

-40°C

0.2
100

o0

100

200

300

400

500

600

700

800

f(CLK) - Clock Frequency - kHz

TA - Free-Air Tempertature - °C

Figure 6

Figure 7

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-313

TLV0834C, TLV08341, TLV0838C, TLV08381
.
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147 - SEPTEMBER 1996

TYPICAL CHARACTERISTICS
TLV0831
SUPPLY CURRENT

TLV0831
SUPPLY CURRENT

vs

vs

FREE-AIR TEMPERATURE

CLOCK FREQUENCY

0.3

0.5

I

VCC= 3.3 V
TA=25'C
0.4

OI
versatile control capability, these devices have an
«Z«T OFFICE BOX 655303 • DALLA!>. TEXA!3 75265

To Output
Latches

TLV1544C, TLV15441, TLV1548C, TLV15481
LOW-VOLTAGE 10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B - DECEMBER 1996 - REVISED DECEMBER 1997

extended sampling, asynchronous start of sampling: CSTART operation
The extended sampling mode of operation programs the acquisition time (tACO) of the sample-and-hold circuit.
This allows the analog inputs of the device to be directly interfaced to a wide range of input source impedances.
The extended sampling mode consumes higher power depending on the duration of the sampling period
chosen.
CSTART controls the sampling period and starts the conversion. The falling edge of CSTART initiates the
sampling period of a preset channel. The low time of CSTART controls the acquisition time of the input
sample-and-hold circuit. The sample is held on the rising edge of CSTART. Asserting CSTART causes the
converter to perform a new sample of the signal on the preset valid MUX channel (one of the eight) and discard
the current conversion result ready for output. Sampling continues as long as CSTART is active (negative). The
rising edge of CSTART ends the sampling cycle. The conversion cycle starts two internal system clocks after
the rising edge of CSTART.
Once the conversion is complete, the processor can initiate a normal liD cycle to read the conversion result and
set the MUX address for the next conversion. Since the internal flag AsyncFlag is set high, this flag setting
indicates the cycle is an output cycle so no conversion is performed during the cycle. The internal state machine
tests the AsyncFlag on the falling edge of CS. AsyncFlag is set high at the rising edge of CSTART, and it is reset
low at the rising edge of each CS. A conversion cycle follows a sampling cycle only if AsyncFlag is tested as
low at the falling edge of CS. As shown in Figure 2, an asynchronous liD cycle can be removed by two
consecutive normal liD cycles.

Table 4. TLV154411548 Hardware Configuration for Different Operating Modes
CS

CSTART

AsyncFlag at CS,J,

ACTION

Normal sampling

Low

High

low

Fixed 6 110 ClK sampling, synchronous conversion follows

Normal 110 (read out only)

low

High

High

No sampling, no conversion

N/A

Flexible sampling period controlled by CSTART,
asynchronous conversion follows

OPERATING MODES

Extended sampling

High

low

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2-343

TLV1544C, TLV15441, TLV1548C, TLV15481
LOW·VOLTAGE10·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B - DECEMBER 1996 - REVISED DECEMBER 1997

Complete Extended
~
Sample Cycle

I
I

Extended

I Sample

Normal
Cycle

I

i4

J
1
~

I

Cycle.!
~

Read Out
Cycle

I

I..
Read out ll

Extended
Sample
Cycle

~

I
Read Out
Cycle
Cycle
~------~----~

Normal
Cycle

FS
(DSPMode)

DATA IN

EOC

DATA OUT

~
X

Async Flag

~
Hi-Z

Hi-Z
I

I
I
I
I

n

0
Db

~
HI-Z

~

~
Db

Dc

NOTES: C. Aa = Address for input channel a.
D. Da = Conversion result from channel a.

Figure 2. Extended Sampling Operation
reference voltage inputs
There are two reference inputs used with the TLV15441TLV1548, REF+ and REF-. These voltage values
establish the upper and lower limits of the analog inputs to produce a full·scale and zero-scale reading
respectively. The values of REF+, REF-, and the analog input should not exceed the positive supply or be lower
than GND consistent with the specified absolute maximum ratings. The digital output is at full scale when the
input signal is equal to or higher than REF+ and is at zero when the input signal is equal to or lower than REF-:.

programmable conversion rate
The TLV1544ITLV1548 offers two conversion rates to maximize battery life when high-speed operation is not
necessary. The conversion rate is programmable. Once the conversion rate has been selected, it takes effect
immediately in the same cycle and stays at the same rate until the other rate is chosen. The conversion rate
should be set at power up. Activation and deactivation of the power-down state (digital logic active) has no effect
on the preset conversion rate.

~TEXAS

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INSTRUMENTS
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TLV1544C, TLV15441, TLV1548C, TLV15481
LOW-VOLTAGE 10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B - DECEMBER 1996 - REVISED DECEMBER 1997

Table 5. Conversion Rate and Power Consumption Selection
TYPICAL SUPPLY CURRENT, ICC

CONVERSION TIME,
tconv

AVAILABLE VCC
RANGE

Fast conversion speed

7 ~s typ

5.5 V to 3.3 V

9h

0.6 rnA typ

Slow conversion speed

15 ~s typ

5.5 V to 2.7V

Ah

0.4 rnA typ

CONVERSION RATE

INPUT DATA

OPERATING

I
I

POWER
DOWN

1.5 rnA max

1 ~typ

1 rnArnax

1 ~typ

programmable power-down state
The device is put into the power-down state by writing 8h to DATA IN. The power-up state is restored during
the next active access by pulling CS low. The conversion rate selected before the device is put into the
power-down state is not affected by the power-down mode. Power-down can be used to achieve even lower
power consumption. This is because the sustaining power (when not converting) is only 1.3 mA maximum and
standby power is only 1 I1A maximum. By averaging out the power consumptioncan be much lower than the
1 mA peak when the conversion throughput is lower.
Power Down

CS

1

~~______________~
Hi·Z

DATA IN

7"""~~"7""7'''''''~~"7""7'''''''~~"7""7'''''''~"?7"7"

Hi·Z
1 0 0 0

I
I
I
I
I
I
I

EOC

I

Supply Current

- - r " : I ' - r 7 - r 7 - r 7 - r 7 r - - - - - - - - - -I- - - i - - - - - - -

I

1 mA
(Typical Peak Supply)
O.3mA
(Typical Sustaining)

ICC

o IL..<..-L...'-L...L.L...L...L...-L...'-L...L.L...L...L.C.L....<-L...L.L.L...L.C.L....<-L...L.L.L...L.C.L....<-L...L.L.L...L.'-L...L.L...L...L...-L...'-L...L.L.....

O.OOO7mA
(Typical Power Down
Supply)

Figure 3. Typical Supply Current During Conversion/Power Down
power up and initialization
After power up, if operating in DSP mode, CS and FS must be taken from high to low to begin an I/O cycle. EOC
is initially high, and the input data register is set to all zeroes. The contents of the output data register is random,
and the first conversion result should be ignored. For initialization during operation, CS is taken high and
returned low to begin the next I/O cycle. The first conversion after the device has returned from the power-down
state can be invalid and should be disregarded.
When power is first applied to the device, the conversion rate must be programmed, and the internal Async Flag
must be taken low once. The rising edge of CS of the same cycle then takes Async Flag low.

~TEXAS

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2-345

TLV1544C, TLV15441, TLV1548C, TLV15481
LOW·VOLTAGE 10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL ANDA/8 ANALOG INPUTS
SLAS139B - DECEMBER 1996 - REVISED DECEMBER 1997

First Cycle After Powerup

1

cs
FS
(For DSP Mode)
Async Flag
(Internal)

DATA IN

I
I
I

I
I I·
I I

!ih

I

Oh
Ab
Signal Channel 0 Converted

I

I I

l!J~! ~~

EOC
DATA OUT

~I

Hi-Z

xV I

Conversion Rate Set to Fast

Hi-Z

• ...-_ _.......

u------.

0

x

Hi-Z

U

Ol--_H..;;.i-Z...;;..._

DO

j ~ AsyncFlag Reset low

L

Conversion Result From Channel 0

Figure 4. Power Up Initializatio.n

input clock inversion - INV elK
The input data register uses I/O elK as the source of the sampling clock. This clock can be inverted to provide
more setup time. INV elK can invert the clock. When INV elK is grounded, the input clock for the input data
register is inverted. This allows an additional one-half I/O elK period for the input data setup time. This is useful
for some serial interfaces. When the input sampling clock is inverted, the output data changes at the same time
that the input data is sampled.
Table 6. Function of INV elK
CONDITION
CLOCK
INVClK

FSat CSJ.

1/0 ClK ACTIVE EDGE

OUTPUT DATA
CHANGES ON

INPUT DATA
SAMPLED ON

High

High (MPt mode)

J.

i

High

Low (OSP:l: mode)

i

J.

Low

High (MPt mode)

J.

J.

Low

Low (OSP:I: mode)

i

i

t MP =microprocessor mode
:I: OSP =digital signal processor mode

~TEXAS

2-346

'

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1544C, TLV15441, TLV1548C, TLV15481
LOW·VOLTAGE 10·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS·
SLAS139B- DECEMBER 1996 - REVISED DECEMBER 1997

REF+ - - - - - - -....
REF- - - - - - - - - t H SampleandHold
Function
AO-A7

~---------+----------'EOC

E~~~~illr-----------'"
Conversion
Clock

REF+

Output Shift Clock

REF-

~---------INVCLK

CS
FS
I/OCLK

OSC

Input
Data
Register

DATA OUT

SMCLK
.-==c:......
___-j-+-II> Control
State

Input Shift Clock
Invert

,.----,. If mode

Machine

2-to-1

DSP§

Microprocessor*

t Successive approximation register
:j: If_mode = 1, microprocessor interface mode
§ If_mode = 0, DSP interface mode

Figure 5. Clock Scheme

absolute maximum ratings over operating free·air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................. -0.5 V to 6.5 V
Input voltage range, VI (any input) ............................................ -0.3 V to Vee + 0.3 V
Output voltage range, Va ................................................... -0.3 V to Vee + 0.3 V
Positive reference voltage, Vref+ ...................................................... Vee + 0.1 V
Negative reference voltage, Vref- .......................................................... -0.1 V
Peak input current, II (any input) .......................................................... ±20 mA
Peak total input current (all inputs) ........................................................ -30 mA
Operating free-air temperature range, TA: TLV1544C, TLV1548C ........................ DoC to 70°C
TLV15441, TLV15481 ........................ -40°C to 85°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds ............................ 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND with REF- and GND wired together (unless otherwise noted).

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TLV1544C, TLV15441, TLV1548C, TLV15481
LOW-VOLTAGE 1O-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B - DECEMBER 1996 - REVISED DECEMBER 1997

recommended operating conditions
MIN

NOM

2.7

Supply voltage, VCC
Positive reference voltage, Vref+ (see Note 2)

MAX

5.5

2.5

Differential reference voltage, Vref + - Vref- (see Note 2)
Analog input voltage, VI (analoo) (see Note 2)

VCC

0

High-level control input· voltage, VIH

V
VCC +0.2

V

VCC

V

2.1

V

low-level control input voltage, Vil

0.6

Setup time, input data bits valid before 1/0 ClKi .I., tsu(A) (see Figure 9)
Hold time, input data bits valid after 1/0 ClKi .I., theA} (see Figure 9)

V
V

VCC
0

Negative reference voltage, Vref- (see Note 2)

UNIT

V
ns

100
5

30

ns

Setup time, cst to 1/0 ClKi, tsu(CS)

See Figure 10

5

30

ns

Hold time, 1/0 ClKt to csi, th(CS}

See Figure 10

65

ns
I/0ClK
periods

Pulse duration, FS high, twH(FS)

See Figure 12

Pulse duration, CSTART, tw(CSTART)

Source impedance :s; 1 kn,
VCC =5.5 V,
See Figure 14

Setup time, CSi to CSTART .I., tsu(CSTART)

See Figure 14

10

VCC = 5.5V

0.1

6

10

VCC = 2.7V

0.1

2

2.81

Clock frequency at 1/0 ClK, fClK
Pulse duration, 1/0 ClK high, twH(I/O)
Pulse duration, 1/0 ClK low, twl(I/O)

1

0.84

VCc=5.5V

50

VCC =2.7V

100

VCC = 5.5 V

50

VCC = 2.7 V

100

Transition time, 1/0 ClK, tt(llO) (see Figure 11 and Note 4)

lls
ns
MHz
ns
ns
1

llS

Transition time, DATA IN, tt(DATA IN) (see Figure 9)

10

llS

Transition time, CS, tt(CS) (see Figure 10)

10

Transition time, FS, tt(FS) (see Figure 13)

10

l1S
llS

10

llS

Transition time, CSTART, ttlCSTART) (see Figure 14)
Operating free-air temperature, TA

TlV1544C, TlV1548C

0

70

°c
TlC15441, TlV15481
-40
85
NOTES: 2. Analog Input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while Input voltages less than
the voltage applied to REF- convert as all zeros (000000000000). The device is functional with reference (Vref+ - Vref-) down to 1
V; however, the electrical specifications are no longer applicable.
3. To minimize errors caused by noise at cst, the internal circuitry waits for a setup time after cst before responding to control input
signals. No attempt should be made to clock in an input dat until the minimum CS setup time has elapsed.
4. This is the time required for the 1/0 ClK signal to fall from VIHmax to Vilmin or to rise from Vilmax to vlHmin. In the vicinity of normal
room temperature, the devices function with an input clock transition time as slow as 1 l1S for remote data-acquisition applications
where the sensor and the AID converter are placed several feet away from the controlling microprocessor.

~TEXA.S

2-348

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1544C, TLV15441, TLV1548C, TLV15481
LOW·VOLTAGE 10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B- DECEMBER 1996 - REVISED DECEMBER 1997

electrical characteristics over recommended operating free-air temperature range,
Vee Vref+ 2.7 V to 5.5 V, 110 elK frequency 2.2 MHz (unless otherwise noted)

=

=

=

PARAMETER

TEST CONDITIONS

10H = -20

Vee = 5.5 V,

10l= 0.8 mA

0.4

Vee =2.7V,

IOl=20 ~A

0.1

VOL

low-level output voltage

10Z

High-impedance output current

IIH

High-level input current

VI = Vee

III

low-level input current

VI=O

eS=Vee

1

2.5

-1

-2.5

0.005

2.5

~A

-0.005

2.5

~A

Vee = 3.3 V to 5.5 V

0.6

1.5

Vee = 3.3 Vto 5.5 V

0.4

1

Vee = 2.7 V to 3.3 V

0.35

0.75

Conversion speed = fast,
For all digital inputs,
0,,; VI ,,; 0.3 V or
VI ~ Vee - 0.3 V
Conversion speed = slow,
For all digital inputs,
0,,; VI ,,; 0.3 V or

t

Vee = 3.3 V to 5.5 V

1.5

mA

Vee = 2.7 V to 3.3 V

1

mA

0.3

mA

lee(ST)

Conversion speed = slow,
For all digital inputs,
0,,; VI"; 0.3 V or
VI ~Vee- 0.3 V

lee(PD)

Power-down supply current

For all digital inputs,
0,,; VI"; 0.3 V or VI ~ Vee - 0.3 V

Zi

Vee = 2.7 V to 3.3 V

25

~A

Selected channel at Vee, unselected channel at 0 V

1

Selected channel at 0 V, unselected channel at Vee

-1

t-tA
t-tA

1

~A

Vref+ = Vee = 5.5

Y,

1

Vref-= GND

Input capacitance, analog inputs

20

55

Input capacitance, control inputs

20

15

Input multiplexer on resistance

t-tA

mA

Sustaining supply current

ei

V

es = Vee

Extended sampling mode
operating current

Maximum static analog
reference current into REF+

V

Vee-0.1

VO=O,

lee(ES)

Selected channel leakage current

t-tA

UNIT

Vo = Vee,

VI~Vee-0.3V

Ilkg

MAX

Vee = 2.7 V,

High-level output voltage

·Operating supply current

TYPt

2.4

10H =-0.2 mA

VOH

ICC

MIN

Vee = 5.5 V,

Vee=4.5V

1

Vee=2.7V

5

pF
kQ

All typical values are at Vee = 5 V, TA = 25°C.

~TEXAS

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2-349

TLV1544C, TLV15441, TLV1548C, TLV15481
LOW·VOLTAGE 10·81T ANALOG·TO·DlGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B - DECEMBER 1996 - REVISED DECEMBER 1997

operating characteristics over recommended operating free-air temperature range,
Vee Vref+ 2.7 V to 5.5 V, 1/0 elK frequency 2.2 MHz (unless otherwise noted)

=

=

=

TEST
CONDITIONS

PARAMETER

MIN

TYPt

MAX

UNIT

±0.5

±1

lSB

±D.5

±1

lSB

El

Linearity error (see Note 6)

ED

Differentil\llinearity error

See Note 2

EO

Offset error (see Note 7)

See Note 2

±1.5

lSB

EG

Gain error (see Note 7)

See Note 2

±1

lSB

ET

Total unadjusted error (see Note 8)

±1.75

lSB

DATA IN = 1011
Self-test output code (see Table 3 and Note 9)

tconv

Ie

Fast conversion speed

Conversion time

Slow conversion speed

Total cycle time (access,
sample, conversion and
EOCi to CS.J.- delay)

512

DATA IN -1100

0

DATA IN = 1101

1023

See Figu res 15
through 17

7

10

I1S

15

25

Ils

Fast conversion speed

See Figures 15
through 18 and
Notes 10,11,12

10.1
+ 10 I/0ClK

Slow conversion speed

See Figures 15
through 18 and
Notes 10 and 12

40.1
+101l0ClK

tacq

Channel acquisition time (sample)

See Figures 15
through 18 and
Note 10

I1S

6

I/OClK
periods
ns

tv

Valid time, DATA OUT remains valid after I/O ClK.J.-

See Figure 11

50

Id1(FS)

Delay time, 1/0 ClK high to FS high

See Figure 13

.5

30

50

ns

1d2(FS)

Delay time, 1/0 ClK high to FS low

See Figure 13

10

30

60

ns

Id(EOCi - CS.J.-)

Delay time, Eoci to cs low

See Figure 14
and Note 5

100

ld(cs.J.- - FSi)

Delay time, CS.J.-to FSi

See Figures 17
and 18

1d(I/O-CS)

Delay time, 10th 1/0 ClK low to CS low to abort
conversion (see Note 13)

See Figure to

t

1

ns
7
1.1

I/0ClK
periods

IlS

All tYPical values are at TA = 25°C.
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that
applied to REF- convert as all zeros (000000000000). The device is functional with reference down to 1 V (Vref+ - Vref - 1); however,
the electrical specifications are no longer applicable.
5. For all operating modes.
6. Linearity error is the maximum deviation from the best straight line through the ND transfer characteristics.
7. Zero error is the difference between 0000000000 and the converted output for zero input voltage. Full-scale error is the difference
between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zerc~-scale, and full-scale errors.
9. Both the input data and the output codes are expressed in positive logic.
10. 1/0 ClK period = 1/(1/0 ClK frequency) (see Figure 8).
11. For 3.3 V to 5.5 V only
12. For microprocessor mode
13. Any transitions of CS are recognized as valid only when the level is maintained for a setup time after the transition.

~TEXAS

INSTRUMENTS

2-350

POST OFFICE BOX 655303 • DALLAS, TeXAS 75265

TLV1544C, TLV15441, TLV1548C, TLV15481
LOW·VOLTAGE 10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B - DECEMBER 1996 - REVISED DECEMBER 1997

operating characteristics over recommended operating free-air temperature range,
Vcc Vref+ 2.7 V to 5.5 V, I/O elK frequency 2.2 MHz (unless otherwise noted) (continued)

=

=

=

PARAMETER

t

TEST CONDITIONS

MIN

TYPt

MAX

UNIT

!d(IIO-DATA}

Delay time, 110 CLK low to DATA OUT valid

See Figure 11

!d(l/O-EOC}

Delay time, 10th 110 CLK! to EOC low

See Figure 12

70

240

ns

tPZH, tpZL

Enable time, CS low to DATA OUT valid (MSB driven)

See Figure 8

0.7

1.3

~s

50

ns

tPHZ, tPLZ

Disable time, CS high to DATA OUT invalid (high impedance)

See Figure 8

70

150

ns

tf(EOC}

Fall time, EOC

See Figure 12

15

50

ns

tr(bus)

Rise time, output data bus at 2.2 MHz 110 CLK

See Figure 11

50

250

ns

tf(bus)

Fall time, output data bus at 2.2 MHz 110 eLK

See Figure 11

50

250

ns

All typical values are at TA = 25°C.

PARAMETER MEASUREMENT INFORMATION
15 V

~d

10~F

O.I~F

EOC
TLV1544/48

>-41------1 Ax

DO

VI-----i
r - - - -..........-

Cl

-15 V

C2

""'Q
LOCATION

DESCRIPTION

Ul
Cl

OP27
1O-~F 35-V tantalum capacitor

C2

O.I-~F

PART NUMBER

-

ceramic NPO SMD capacitor

AVX 12105Cl04KA105 or equivalent

Figure 6. Analog Input Buffer to Analog Inputs
Test Point

VCC

Test POint

VCC

~=~8~

EOC

CL=50pF

I

~=~8~

DATA OUT-~~e-........,........- - .

12kn

CL=100pF

I

12kn

Figure 7. Load Circuits

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2-351

TLV1544C, TLV15441, TLV1548C, TLV15481
LOW·VOLTAGE 10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B- DECEMBER 1996 - REVISED DECEMBER 1997

PARAMETER MEASUREMENT INFORMATION
~ Address --+1

Valid

1

~
CS
tpZH. tpZL

90%T

~1

L..
_..L
~

DATA _ _ _ _
90_%-('
OUT

10% \.

DATA IN

VIH

.

\.~_10_o/c_._ _.J.f,-L~ ______

VIL

II (DATA IN)

X 90%--

VOH

£100/,,- -

VOL

~

~~~~

~: ~

I/OCLK

10%

X----:::

II(CS)

10%

-+i ~ ~-VIH
WI

I~

10%

II

1

VIL

j}

1/0 CLK

1

1

~

1

~

1"

Ih(CS) 1

I
~ld(1I0.CS)-+l
~
10%

Firsl
Clock

1

Lasl
Clock

10%

Figure 10. CS and I/O ClK Voltage Waveforms
11(1/0)

11(1/0)

1

1

r-

!d(IIO-DATA)
Iv
DATA OUT

14--

~
I 1

-.I

I/OCLK

14

...J4..--+1

1/0 Clock Period ----.:

.1

X

90%
_ _ _1..,;;0.;.,;%....

1

90%

>c

VALID

~1.;.;0.;.;%______

VIH
vlL

1 I

-+i i+-

Ir(bus). If(bus)

Figure 11. DATA OUT and I/O ClK Voltage Waveforms
~14--- Id(E5-FS

~

!

CS\

I
FS

r-\I
' ......1

_ _ _ _- - - J

Figure 12. CS low to FS low

~TEXAS

2-352

Ih(A)

Figure 9. DATA IN Setup Voltage Waveforms

i

Isu(CS)

:::

-+i !4c- 11(1/0)

II(C~S)
---+I.
~

....

-..l j.- II (DATA IN) ~ I.-

Isu(A)

IpHZ.IPLZ

Figure 8. DATA OUT to Hi·Z Voltage Waveforms

~

~::

1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VIL

TLV1544C, TLV15441, TLV1548C, TLV15481
LOW·VOLTAGE 10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B - DECEMBER 1996 - REVISED DECEMBER 1997

PARAMETER MEASUREMENT INFORMATION
10lh
Clock

J,O%

I/OCLK

I

\

10%
1

1

td(I/O-EOC) ---i~
____~.1

1::-t---------

EOC
(llpMode)

VIH
VIL

1

'-t----

Id(I/O-EOC) ---1~4----+l.1
EOC

90%

(DSPMode)

VIH

!\I 10%

VIL

1

If(EOC)

-+I J+-

Figure 13. 1/0 ClK and EOC Voltage Waveforms

I/OCLK
I

Id1(FS)

II(FS)
FS

1

1

Id2(FS) ~

j+-

--.I

-.I

*-

'i .It

II(FS)

90%

-..f

90%

----1';10%

I

VIL

141'-

t+------

10%"\

1

VIH
VIL

1

14

.1

IwH(FS)

Figure 14. FS and 1/0 ClK Voltage Waveforms

CS

~O%I

-\tQ-

II(CSTART)
Isu(CSTART) ~
II(CSTART)
1
__
90%. I
Iw(CSTART) " ) : 90%
CSTART
_ 10%

--.I :.-

f

Id(I/O-EOC)
EOC

~:4

10·L

vlL

I

iI
I

~

Id(EOC1'-CSJ.)

-----------~~~----- VIL
Figure 15. CSTART and CS Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-353

TLV1544C, TLV15441, TLV154BC, TLV154BI
LOW-VOLTAGE 10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/BANALOG INPUTS
SLAS139B - DECEMBER 1996 - REVISED DECEMBER 1997

PARAMETER MEASU!=IEMENT INFORMATION

~
Address Sampled

~,

,

ro;- Access

cs
(see Note A)

Rise After 10th 1/0 ClKt

~I

td(EOCt-CSt)

po"

Sample
(6 1/0 ClKs)

II II II II

~

I

I

I

r--S1-

L

I

I I

I

I

I

1

2

3

4

I

1/0 ClK

Conversion Starts on 10th 1/0 ClKt

II

I

L

I

'r-"1

1LJnillj-JnLJnLJnL

01

I MSB

I
I
~
I

Hi-Z
DO

EOC

I MSB
I
I........

lSB

Hi-Z

ro.
\::

I

L--.,~

Initialize State Machine
and Counter
NOTE A: To minimize errors caused by noise at cs, the internal circuitry waits for a setup time after cst before responding to control input
signals. No attempt should be made to clock in input data until the minimum CS setup time elapses.

Figure 16. Microprocessor Interface Timing (Normal Sample Mode, INV ClK
Address Sampled

~

Conversion Starts on 10th I/O ClKt

r ( l"'l
;..-..+I
1114
I

CS
(see Note A)

----1 : : : :
I II II II I
:

OO~K

Ac~ess

1

2

=High)

Rise After 10th 1/0 ClKt

I

Sample

Conversion

I

r--Sr-

I

td(EOCt-CSt)

L

--""'"""'--"M-'<-----..-----~

(5.51/0ClKs)

:

L

I

I
I

3

I

10

II

I

'r-"1

I

:

EOC
Initialize State Machine
and Counter
NOTE A: To minimize errors caused by noise at cs, the internal circuitry waits for a setup time after cst before responding to control input
signals'. No attempt should be made to clock in input data until the minimum CS setup time has elapsed.

Figure 17. Microprocessor Interface Timing (Normal SampleMode, INV ClK = low)

~TExAS

2-354

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1544C, TLV15441, TLV1548C, TLV15481
LOW·VOLTAGE 10·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B - DECEMBER 1996 - REVISED DECEMBER 1997

PARAMETER MEASUREMENT INFORMATION
Initialize Counter ~I Address Sampled
Initialize State

7 110 ClKs
Maximum
CS

Machine~:
i4
1~
I

1

~I

(see
NoteA) .

:
'I

~

((

)

Conversion Starts on 10th 110 ClKt

"'l

i+r Access --I~~--

Iii i I

11 I
I I I

I
I

I
I

I

1

2

3

4

1

CS Rise After 16th 110 ClKt

""
Sample

""~

(6110ClKs)

I

\
1

Hold/Conversion

)&1
I

td(E;\CS:
1

Ir:n

--11--

1
1

1I0ClK

lSB

----IIIr--l

EOC

1,---1

NOTE A: To minimize errors caused by noise at es, the internal circuitry waits for a setup time after est before responding to control input
signals. No attempt should be made to clock in input data until the minimum CS setup time elapses.

Figure 18. DSP Interface Timing (16-Clock Transfer, Normal Sample Mode, INV ClK = High)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-355

TLV1544C, TLV15441, TLV1548C, TLV15481
LOW-VOLTAGE 10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B - DECEMBER 1996 -REVISED DECEMBER 1997

PARAMETER MEASUREMENT INFORMATION
Initialize Counter .1 Address Sampled

Machine~ i

Initialize State

71/0 ClKs I..
Maximum I

(s~~ --l

Note A)

I/OClK

~

Conversion Starts on 10th I/O ClKt

I~ ( ( 1 ~
I h Access ~~~
.. - -

!

i

~

Sample

(6 I/O CLKs)

CS Rise After 16th I/O CLKt

\

Hold/Conversion

i

td(EOCt-CSt)

I
\
-+I---~
..It--L-~~

i [~,~H

Y\-'J--ilr-+I...,..........,,.-..;.........;---------io---------+-I.1....\
I
16 1
I
I

I
I

LSB

I
EOC
NOTE A: To minimize errors caused by noise at cs, the internal circuitry waits for a setup time after cst before responding to control input
'signals. No attempt should be made to clock in input data until the minimum CS setup time elapses.

Figure 19. DSP·lnterface Timing (16-Clock Transfer, Normal Sample Mode, INV ClK

~TEXAS
2-356

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

=low)

TLV1544C, TLV15441, TLV1548C, TLV15481
LOW·VOLTAGE 10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B - DECEMBER 1996 - REVISED DECEMBER 1997

TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR

CD
III
..J

..
I

g

w

f

CD

INTEGRAL NONLINEARITY ERROR

vs

vs

FREE-AIR TEMPERATURE

FREE-AIR TEMPERATURE

--- ---

0.485
0.48
0.475
0.47
0.465
0.46
0.455
0.45

0.24
CD

~

.g

Maximu~

O.

w

0.1 8

f

0.1 6

.5

VCC=2.7V

-0.45
"!01 -0.455
.!!! -0.46
-0.465
I
..J
-0.47
3l: -0.475
-0.48

0

..,.......,

---

-o.48~5

--- ---

~

"!01

-0.1 8

I

-0. 2

..J

3l:

Minimum -

22.5
TA - Free-Air Temperature -

z

-0.1 6

~

-0.22

V-0.24

90

-45

'c

DIFFERENTIAL NONLINEARITY ERROR

..J

I

e

w

DIFFERENTIAL NONLINEARITY ERROR

vs

FREE-AIR TEMPERATURE

FREE-AIR TEMPERATURE

O. 2

l!

O. 1

'c

.5

I!!

~
I

..J

Z

Q

-0. 5
-0. 6
-45

..g

o.3f'....

I

~

-0. 2

-0. 4

o.4

w

-0. 1

-0. 3

CD

~

Maximum

VCC=2.7V

C

z0
m
'E

_____

O. 3

~

90

22.5
TA - Free-Air Temperature - 'C

o.5

5~

O. 4

Minimum

vs

o.6
CD
III

-------

~

Figure 21

Figure 20

O.

Maximum _

VCC =5.5 V

C

z

.e

2~

I

CD

c

'E0

0.22

-----

----Minimum

22.5
TA - Free-Air Temperature -

o.2

:1

o.1

z

-0. 1

~

~

j

is
I
..J

Z

Q

90

'c

~

-

VCC =5.5 V

-0.2

-0. 3~

~

Maximum

-----

Minimum

-0. 4
-0. 5
-45

22.5
TA - Free-Air Temperature - 'C

90

Figure 23

Figure 22

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-357

TLV1544C, TLV15441, TLV1548C,TLV15481
LOW-VOLTAGE 10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B - DECEMBER 1996 - REVISED DECEMBER 1997

TYPICAL CHARACTERISTICS
OFFSET ERROR

GAIN ERROR

vs

vs

FREE·AIR TEMPERATURE

FREE-AIR TEMPERATURE

o. 6
o. 5
o. 4

o.2

0.3
III

~

-g
I

w

~
I

B

L

0.1 5
Vee

0.2 i'"""
o. 1

=5.5 V

~

0

vee=2.7V'/

o. 1

-

~

III

~

0.05

I

-.........

!

0

!:::

c

·ii

o.7
o.6
o. 5
o.4
o.3
o.2

---

-45

0

Cl
I

r--

Jr

Vee = 2.7 V

-0. 1

-............

22.5
TA - Free-Air Temperature -

'"

-0.2 5
-45

vs

FREE·AIR TEMPERATURE

-

0.5

~

0.4

I

0.3
0.2

-g

w

I

~
::J
!
t!!.

1.2

~ .......

1.1

Maximum -

-0. 1
-0.2

0.8

--

Vee = 5.5 V

---

o

Minim~

!
t!!.

I'

-0. 3

Jj

-0. 5
-45

-0. 1

22.5
TA - Free-Air Temperature -

90

°e

--- --Minimum

-0. 2
-0. 3

-0. 4

-0. 4
-45

Figure 26

22.5
TA - Free-Air Temperature -

Figure 27

~TEXAS

INSTRUMENTS
2-358

Maxi~u~

0.9

Vee=2.7V

I

Jj

-------

FREE-AIR TEMPERATURE

o. 1
0

°e

TOTAL UNADJUSTED ERROR

vs

III

90

22.5
TA - Free-Air Temperature -

Figure 25

TOTAL UNADJUSTED ERROR

0.6

/'

~

-0. 2

Figure 24

0.7

ve~

-

-0.1 5

90

°e

-0.05

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

90

°e

TLV1544C, TLV15441, TLV1548C, TLV15481
LOW-VOLTAGE 10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B- DECEMBER 1996 - REVISED DECEMBER 1997

TYPICAL CHARACTERISTICS
SUPPLY CURRENT

vs
FREE·AIR TEMPERATURE

0.55
0.54

r------

0.53
C

E

~

"-.~

0.52

I

"E
~
;:,
(.)

0.51

"

0.5

'\

~

Q.
Q.

;:,

0.49

III
I

0.48

E

0.47

(.)

0.46

\

VCC = 5.5 V
Clock Mode =
Fast Conversion

0.45

-45

22.5
TA - Free·Alr Temperature - °C

90

Figure 28
INTEGRAL NONLINEARITY ERROR

DIFFERENTIAL NONLINEARITY ERROR

vs

vs

DIGITAL OUTPUT CODE

DIGITAL OUTPUT CODE

2~----------~-------------,
VCC=2.7V
1.6 TA 25°(;
Clock Mode = Fast
1.21---------i---------i

=

0.81---------i---------i

2

VCC = 2.7 V
TA = 25°C
Clock Mode = Fast

III

~

.g
I

w

~

'm

.5
"2
0

z

S
-O.81---------i---------i

"E
!!

.!:!
-1.21----------+-------1

2i

-1

-1.61-------t-,-------j
-2~

o

__________

~

_____________ J

512
Digital Output Code

1023

~~---------~------------~

o

Figure 29

512
Digital Output Code

1023

Figure 30

-!/}TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-359

TLV1544C, TLV15441, TLV1548C, TLV15481
LOW·VOLTAGE 10·81T ANALOG·TO-DIGJTALCONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B - DECEMBER 1996 - REVISED DECEMBER 1997

TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR

III

~

-g

DIFFERENTIAL NONLINEARITY ERROR

vs

vs

DIGITAL OUTPUT CODE

DIGITAL OUTPUT CODE

VCC =5V
TA = -40°C
Clock Mode = Fast

0.8
0.6

~

-g

0.41-------+---------1

w

w

~

.~

:1

~

iii

~

"E

~

o

Z

.5
I

-0.41-------+---------1

1
_

-O.4t-------+----------1

is

-0.61--------+---------1

...I

i!!:

=

0.8

I

I

f
5:'

VCC=5V
TA -40°C
Clock Mode = Fast
0.61--------+----------1

III

-0.81--------+---------1
-1~

o

I
...I

~

-0.6 t - - - - - - - + - - - - - - - - - - : - - - - 1
-0,81-------+----------1

__________~~----------~
512
Digital Output Code

-1~----------~------------...I
1023
o
512

1023

Digital Output Code

Figure 31

Figure 32

INTEGRAL NONLINEARITY ERROR

~

vs

DIGITAL OUTPUT CODE

DIGITAL OUTPUT CODE

VCC =5V
TA = 25°C
Clock Mode = Fast

0.8
III

~-

DIFFERENTIAL NONLINEARITY ERROR

vs

~I
e
w

-

0.6

I

~

••"E~
f

l

.5
I

0.4
0.2

k~.

o1'111'

_.j,

.Il ".,IL

.. IIl• I.IL . II

"

,1IIII.1 .. 1r.1Iia&.,tIL'&1i:

""1",",' ." "

-0.2

0.4t-------+----------1

iii

1
_

-0.4

-O.41--------+-----------l

is

-0.6

I
...I

...I

i!!:

f~

VCC=5V
TA=25°C
Clock Mode = Fast
0.61--------+----------1
0.8

~

-0.8
-1

o

512
Digital Output Code

1023

-0.61-------+--------1
-0.81-------+--------1

~~----------~----------...1

o

Figure 33

Figure 34

~TEXAS
2-360

512
Digital Output Code

INSTRUMENTS

POST OFfiCE BOX 655303 • DALLAS, TEXAS 75265

1023

TLV1544C, TLV15441, TLV1548C, TLV15481
LOW-VOLTAGE 10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B - DECEMBER 1996 - REVISED DECEMBER 1997

TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR

vs
DIGITAL OUTPUT CODE
VCC=5 V

TA = 85'C

0.8

Clock Mode = Fast

CD

~

0.6

I

~~•1.&.."1/","
'~""Ilto

-1

.,

o

,,,-I •.

~.

'l'~

rit/<'V'Y

512

1023

Digital Output Code

Figure 35
DIFFERENTIAL NONLINEARITY ERROR

vs
DIGITAL OUTPUT CODE
VCC=5V
0.8 I- TA 85'C
Clock Mode
0.6

=

=Fast

0.4

0.2

o 11

I

-0.2

~

-0.4

1

-0.6

'lij

,j,

.1.

I"

I "L

I. ,.1,

'" , ''"r

'"

L I .. ~.I, .,",

"I

'.,,"

c

...J

Z

C

-{I.8

-1

o

512

1023

Digital Output Code

Figure 36

~.TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-361

TLV1544C, TLV15441, TLV1548C, TLV15481
.LOW-VOLTAGE 10-81T ANALOG-TO-DIGITALCONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B - DECEMBER 1996 - REVISED DECEMBER 1997

APPLICATION INFORMATION
1111111111
seJ Notes A

~nd B

VFS -

1111111110

.~

1111111101

•
••

ell

'8
(,)

)~V

1000000001

~

'S

!0

1000000000

~CIl

VZT = VZS + 1/2 LSB

7

0111111111

is

•••

-VZS

/

0000000010
0000000001
0000000000

/

1/

//V~

./

/~
./

A:

~ /'

V

I
I

II
I
I

I
2.4528

2.4576

2.4624

C!

1021

••
•

I

Ii

IA/'

•••

1022

FSnom

~!

I
I

V

~ 0.0048 0.0096

<:>

1i
/1

1023

VFT = VFS - 1/2 uiB

/'

~

o

./

-;; t;:r/'V/

•••

VI- Analog Input Voltage - V

513
512

I:L

Dl

511

••
•
2

o

4.912814.9140 4.9152
oi

NOTES: A. This curve is based on the assumption that Vref+ and Vref- have been adjusted so that the voltage at the transition from digital 0
to 1 (VZT) is 0.0024 V, and the transition to full scale (VFT) is 4.908 V. 1 LSB = 4.8 mY.
B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is
the step whose nominal midstep value equals zero.

Figure 37. Ideal Conversion Characteristics

~·TEXAS
2-362

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1544C, TLV15441, TLV1548C, TLV15481
LOW·VOLTAGE 10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B- DECEMBER 1996 - REVISED DECEMBER 1997

APPLICATION INFORMATION
VCC
20
12
11

TLV1548t

Microprocessor

VCC
FS

15

CS

INVCLK

I/OCLK

AO-A7

CLKX
CLKR
DX

17

DATA IN
DATA OUT

1-8
Analog Inputs

1/02

18

16

DR
3Vdc
Regulated

To Source Ground

t

DB package is shown for TLV1548

Figure 38. Typical Interface to a Microprocessor
VCC

TLV1548*
20
11

VCC

CS
I/OCLK

1-8
Analog Inputs

15

102

INVCLK

AO-A7

DATA IN
DATA OUT

18
17
16

CLKX
CLKR

TMS320 DSP

DX
DR
FSX
FSR

To Source GND

:j: DB package is shown for TLV1548

Figure 39. Typical Interface to a TMS320 DSP

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-363

T~V1544C,

TLV15441, TLV1548C, TLV15481
LOW·VOLTAGE 10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B- DECEMBER 1996 - REVISED DECEMBER 1997

APPLICATIONS INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 33, the time required to charge the analog input capacitance from 0 to Vs
within 1/2 lSB can be derived as follows:
The capacitance charging voltage is given by:
V C = V s( 1-e-tc!RtCi)
where

(1 )
Rt = Rs + rj
tc = Cycle time

The input impedance Zj is 1 kQ at 5 V, and is higher (- 5 kQ) at 2.7 V. The final voltage to 1/2 lSB is given by:
Vc (1/2 lSB)

=Vs -

(2)

(Vs/2048)

Equating equation 1 to equation 2 and solving for cycle time

tc gives:

Vs - (VS!2048) = Vs(1_e-tc!RtCi)
and time to change to 1/2 lSB (minimum sampling time) is:

(3)

tch (1/2 lSB) = Rt x CI x In(2048)
where
In(2048)

= 7.625

Therefore, with the values given, the time for the analog input signal to settle is:
tch (1/2 lSB) = (Rs + 1 kQ) x 55 pF x In(2048)

(4)

This time must be less than the converter sample time shown in the timing diagrams. Which is 6x liD ClK ..
(5)

tch (1/2 lSB)::;; 6x 1/fl/0
Therefore the maximum liD ClK frequency is:
inax(fI/O)

= 6/tch (1/2 lSB) = 6/(ln(2048) x Rt x Cj)

~TEXAS

2-364

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

(6)

TLV1544C, TLV15441, TLV1548C, TLV15481
LOW·VOLTAGE 10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139B - DECEMBER 1996 - REVISED DECEMBER 1997

APPLICATIONS INFORMATION
I
I
I
I

Driving Sourcet 4
Rs

~ TLV1544/48

.

VI

ri

VS~VC
I
1 kn

.

I

I

i

C.

5~PFMAX

VI = Input Voltage at AIN
VS= External Driving Source Voltage
Rs = Source Resistance
ri = Input Resistance (MUX'on Resistance)
Ci = Input Capacitance
VC= Capacitance Charging Voltage

t

Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.

Figure 40. Equivalent Input Circuit Including the Driving Source

maximum conversion throughput
For a supply voltage at 5 V, if the source impedance is less than 1 kQ, this equates to a minimum sampling
time teh(0.5 lSB) of 0.84 lis. Since the sampling time requires six I/O clocks, the fastest I/O clockfrequency is
6/tch = 7.18 MHz. The minimal total cycle time is given as:
tc

= taddress + tsample + tconv + td(EOCt = 0.56 lis + 0.84 lis + 10 liS + 0.1 !is

CS.J,,)

= 11.5 liS

A maximum throughput of 87 KSPS. The throughput can be even higher with a smaller source impedance.
When source impedance is 100Q, the minimum sampling time is 0.46 llS. The maximum I/O clock frequency
possible is almost 13 MHz. Then 10 MHz clock (maximum I/O elK for TlV1544/1548) can be used. The minimal
total cycle time is:
tc

= taddress + tsample + teonv + td(EOCt -

= 4 x 1/f + 0.46 lls + ~ 0 liS + 0.1
= 0.4 lls + 0.46 llS + 10 lls + 0.1

CS.J,,)

lis
llS

= 10.9611S

The maximum throughput is 1/1 0.9611S = 91 KSPS for this case.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-365

2-366

TLV1548M
LOW-VOLTAGE 10-81T ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 8 ANALOG INPUTS
04 - DECEMBER 1997

•
•
•
•
•
•
•
•
•
•
•
•
•

Conversion Time ~ 10 ~s
10-Bit-Resolution ADC
Programmable Power-Down
Mode ... 1 ~A
Wide Range Single-Supply Operation of
2.7 V dc to 5.5 V dc
Analog Input Range of 0 V to Vee
Built-in Analog Multiplexer with ~ Analog
Input Channels
SMJ320xxx DSP and Microprocessor SPI
and QSPI Compatible Serial Interfaces
End-of-Conversion (EOC) Flag
Inherent Sample-and-Hold Function
Built-In Self-Test Modes
Programmable Power and Conversion Rate
Asynchronous Start of Conversion for
Extended Sampling
Hardware I/O Clock Phase Adjust Input

JPACKAGE
(TOP VIEW)

AD

A1
A2
A3
A4

CSTART
GND

1
2
3

4
5

9

17
16
15
14
13

Vee
EOC
I/OCLK
DATA IN
DATA OUT
CS
REF+
REFFS
INVCLK

?:
w

description
The TlV1548 is a CMOS 10-bit switched-capacitor successive-approximation (SAR) analog-to-digital (AID)
converter. Each device has a [chip select (CS), input-output clock (I/O ClK), data input (DATA IN) and serial
data output (DATA OUT) that provide a direct 4-wire synchronous serial peripheral interface (SPFM, QSPITM) port
of a host microprocessor. When interfacing with a SMJ320 DSP, an additional frame sync signal (FS) indicates
the start of a serial data frame. The devices allow high-speed data transfers from the host. The INV ClK input
provides further timing flexibility for the serial interface.
In addition to a high-speed converter and versatile control capability, the device has an on-chip 11-channel
multiplexer that can select anyone of eight analog inputs or anyone of three internal self-test voltages. The
sample-and-hold function is automatic except for the extended sampling cycle where the sampling cycle is
started by the falling edge of asynchronous CSTART. At the end of the A/D conversion, the end-of-conversion
(EOG) output goes high to indicate that the conversion is complete. The TlV1548 is designed to operate with
a wide range of supply voltages with very low power consumption. The power saving feature is further enhanced
with a software-programmed power-down mode and conversion rate. The converter incorporated in the device
features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and
isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error
conversion over the full operating temperature range.
The TlV1548 has eight analog input channels. The TlV1548M will be characterized for operation over the full
military temperature range of - 55°C to 125°C. The target release timeframe for the TlV1548M is estimated
to be during the first half of 1998.

SPI and aSPI are registered trademarks of Motorola, Inc.
PRODUCT PREVIEW information concerns products In the formative or
desiQn phase of development Characteristic data and other

~=~~~~~~:!~t~~~~~,!:a~~o~~: :i~~::;~~~~S the right to

~TEXAS

INSTRUMENTS
pnST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright © 1997, Texas Instruments Incorporated

2-367

:;
w
a:
D.
~

o

::::»

c

oa:

D.

TLV1548M
LOW·VOLTAGE 10·81T ANALOG·TO·DIGITAL CONVERTER
WITH SERIAL CONTROL AND 8 ANALOG INPUTS
SGLS1 04 - DECEMBER 1997

functional block diagram

I

Sample
and
Hold Function

AO-A7
REF+

r

~ CLOCK

J+

1-a

DATA IN

+

Analog
MUX

13

+

r---

I

17

;----+-

r

:xl

oC

o.....

10-to-1
Data Selector

19.
Control
Logic
and
1/0
Counters

12
15

9
11

18

Terminals shown are for the J package,
AVAILABLE OPTIONS

"tJ

PACKAGES

:xl

TA

<
-

-55°C to 125°C

m

(J)

I

(FK)

TLV1548MJB

I

TLV1548MFKB

m

=e

-!!1

TEXAS
INSTRUMENTS
2-368

16

DATA OUT

f
Input
Data
Register

"tJ

,C:

•
•

Output Data Register
14

Self-Test
Reference

REF-

10-Blt ADC
(Switch Capacitors)

POST OFFICE BOX 655303 • OALLAS, TEXAS 75265

EOC
FS
CS
CSTART
INVCLK
1I0CLK

TLV1548M
LOW·VOLTAGE 10·81T ANALOG·TO·DIGITAL CONVERTER
WITH SERIAL CONTROL AND 8 ANALOG INPUTS
SGLS104- DECEMBER 1997

Terminal Functions
TERMINAL

1/0

DESCRIPTION

1-4
5-8

I

Analog inputs. The analog inputs are internally multiplexed. (For a source impedance greater than
1 kQ, the asynchronous start should be used to increase the sampling time.)

CS

15

I

Chip select. A high·to-Iow transition on CS resets the internal counters and controls and enables DATA IN, DATA
OUT, and 1/0 ClK within the maximum setup time. A low-to-high transition disables DATA IN, DATA OUT, and 1/0
ClK within the setup time.

CSTART

9

I

Sampling/conversion start control. CSTART controls the start of the sampling of an analog input from a selected
multiplex channel. A high-to-low transition starts the sampling of the analog input signal. A low-to-high transition puts
the sample-and-hold function in hold mode and starts the conversion. CSTART is independent from I/O ClK and
works when CS is high. The low CSTART duration controls the duration of the sampling cycle for the switched
capacitor array. CSTART is tied to VCC if not used.

DATA IN

17

I

Serial data input. The 4-bit serial data selects the desired analog input and test voltage to be converted next in a
normal cycle. These bits can also set the conversion rate and enable the power-down mode.
When operating in the microprocessor mode, the input data is presented MSB first and is shifted in on the first four
rising (INV ClK = VCC) or falling (INV ClK = GND) edges of I/O ClK (after CSJ,).
When operating in the DSP mode, the input data is presented MSB first and is shifted in on the first four falling (INV
ClK = VCC) or rising (INV ClK = GND) edges of I/O ClK (after FSJ,).
After the four input data bits have been read into the input data register, DATA IN is ignored for the remainder of the
current conversion period.

DATA OUT

16

0

Three-state serial output of the AID conversion result. DATA OUT is in the high-impedance state when CS is high
and active when CS is low. With a valid CS signal, DATA OUT is removed from the high-impedance state and is
driven to the logic level corresponding to the MSB or lSB value of the previous conversion result. DATA OUT
changes on the falling (microprocessor mode) or rising (DSP mode) edge of I/O ClK.

EOC

19

0

End of conversion. EOe goes from a high to a low logic level on the tenth rising (microprocessor mode) or tenth
falling (DSP mode) edge of I/O ClK and remains low until the conversion is complete and data is ready for transfer.
EOC can also indicate that the converter is busy.

NAME
AD-A3
A4-A7

NO.

12

GND

10

Ground return for internal circuitry. All voltage measurements are with respect to GND, unless otherwise noted.

11

Inve"!ed clock input. INV ClK is tied to GND when an inverted I/O ClK is used as the source of the input clock. This
affects both microprocessor and DSP interfaces. INV ClK is tied to Vec if I/O ClK is not inverted. INV ClK can also
invoke a built-in test mode.

INVClK

I

DSP frame synchronization input. FS indicates the start of a serial data Irame into or out of the device. FS is tied
to VCC when interfacing the device with a microprocessor.

FS

I

3:

w

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w

a:
D..

tO

::)

C

oa:
D..

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-,369

TLV1548M
LOW-VOLTAGE 10-81T ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 8 ANALOG INPUTS
SGLS104-DECEMBER 1997

Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/OCLK

18

1/0

DESCRIPTION

I

Input/output clock. 1/0 ClK'receives the serial 1/0 clock input in the two modes and performs the following four
functions in each mode:

Microprocessor mode

•

•
•
•

When INVClK = VCC. 1/0 ClK clocks the four input data bits into the input data register on the first four rising
edges of 1/0 ClK after CSJ. with the multiplexer address available after the fourth rising edges. When INV ClK
= GND, input data bits are clocked in on the first four falling edges instead.
"
On the fourth falling edge of 1/0 ClK, the analog input voltage Of! the selected multiplex input begins charging
the capacitor array, and continues to do so until the tenth rising edge of 1/0 ClK except in the extended sampling
cycle where the duration of CSTART determines when to end the sampling cycle.
Output data bits change on the first ten falling 110 clock edges regardless of the condition of INV ClK.

1/0 ClK transfers control of the conversion to the internal state machine on the tenth rising edge of 1/0 ClK
regardless of the condition of INV ClK.

Digital signal processor (DSP) mode

•
•

"tJ

::D

oC

•
•

c:

o-I

REF+

14

I

When INV ClK = VCC, 1/0 ClK clocks the four input data bits into the input data register on the first four falling
edges of 1/0 ClK after FSJ. with the multiplexer address available after the fourth falling edges. When INV ClK
= GND, input data bits are clocked in on the first four rising edges instead.
On the fourth rising edge of 1/0 CtK, the analog input voltage on the selected multiplex input begins charging
the capacitor array and continues to do so until the tenth falling edge of 1/0 ClK except in the extended sampling
cycle where the, duration of CSTART determines when to end the sampling cycle.
Output data bits change on the first ten rising 1/0 ClK edges regarless <:,f the condition of INV ClK.

1/0 ClK transfers control cif the conversion to the internal state machine on the tenth falling edge of 1/0 ClK
regardless of the condition of INV ClK.

Upper reference voltage (nominally VCC ). The maximum input voltage range is determined by the difference between
the voltages applied to REF+ and REF-.

"tJ

REF-

13

I

lower reference voltage (nominally ground)

m
<
m

VCC

20

I

Positive supply voltage

::D

-:e

~TEXAS

2-370

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75285

TLV1548M
LOW-VOLTAGE 10-81T ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 8 ANALOG INPUTS
SGLS104- DECEMBER 1997

APPLICATION INFORMATION
vcc
20
12
11

TLV1548M

INT

EOC

VCC
FS

1/01
1/02
CLKX

INVCLK

CLKR
OX
DR

1-8
AQ-A7

Analog Inputs

Microprocessor

To Source Ground

Figure 1. Typical Interface to a Microprocessor
VCC
20
11

TLV1548M
CSTART
VCC
CS
INVCLK
EOC
I/OCLK
DATA IN

1-8
Analog Inputs

AQ-A7

DATA OUT

9
-------15

17
16

~

XF1

W

:;

XF2
810
CLKX
CLKR

W

IX:

SMJ3200SP

D..

OX
DR

t-

O

FSX

::l
C

FSR

oIX:

To Source GNO

D..

Figure 2. Typical Interface to a SMJ320 DSP

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-371

2-372

TLV1549C, TLV15491, TLV1549M
10-81T ANALOG·lO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 C - JANUARY 993 - REVISED MARCH 1995

0, JG, OR P PACKAGE
(TOP VIEW)

• 3.3-V Supply Operation

• 10-Bit-Resolution Analog-to-Digital
Converter (ADC)
• Inherent Sample and Hold Function
• Total Unadjusted Error .. . ±1 LSB Max
• On-Chip System Clock
• Terminal Compatible With TLC1549 and
TLC1549x
• Application Report Availablet
• CMOS Technology

REF+Q8

ANALOG IN

2

7

REF-

3

6

GND

4

5

VCC

110 CLOCK
DATA OUT
CS

FKPACKAGE
(TOP VIEW)

+

otbo8o
za:z;:>z

description
NC
ANALOG IN
NC

The TLV1549C, TLV15491, and TLV1549M are
10-bit,
switched-capacitor,
successiveapproximation, analog-to-digital converters. The
devices have two dJ9!tal inputs and a 3-state
output [chip select (CS), input-output clock (1/0
CLOCK), and data output (DATA OUT)] that
provide a three-wire interface to the serial port of
a host processor.

43 2

1 201~8
17

16

REF-

5
6
7

NC

8

14
9 10 11 12 13

15

NC
1I0CLOCK
NC
DATA OUT
NC

ozzz
0 0l~ 0
...... z
(!)

The sample-and-hold function is automatic. The
converter incorporated in the device features
differential high-impedance reference inputs that
facilitate ratiometric conversion, scaling, and
isolation of analog circuitry from logic and supply
noise. A switched-capacitor design allows lowerror conversion over the full operating free-air
temperature range.

NC - No internal connection

The TLV1549C is characterized for operation from O°C to 70°C. The TLV15491 is characterized for operation
from -40°C to 85°C. The TLV1549M is characterized for operation over the full military temperature range of
-55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
TA

SMALL OUTLINE
(D)

t

O°C to 70°C

TLV1549CD

-40°C to 85°C

TLV15491D

- 55°C to 125°C

-

CHIP CARRIER
(FK)

TLV1549MFK

CERAMIC DIP
(JG)

PLASTIC DIP
(P)

-

TLV1549CP
TLV15491P

TLV1549MJG

-

Interfacing the TLV1549 1O-Bit Serial-Out ADC to Popular 3.3·V Microcontrollers (SLAA005)

~TEXAS

Copyright © 1995, Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-373

TLV1549C, TLV15491, TLV1549M
1Q·BITANALOG·TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 C - JANUARY 1993 - REVISED MARCH 1995

typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE

INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kQTYP

ANALOGIN~,

I

,ANALOG

Cj=60pFTYP
(equivalent Input
capacitance)

IN~"
,
,

' ,;h

5MQTYP

functional block diagram
REF+

REF-

I1

I3

10-8it
Analog-to-Digital
Converter
(switched capacitors)
10

ANALOG IN

~

Samj>leand
Hold

I

Output
Data
Register

M

10-to-1 Data
6
Selector and t - - DATA OUT
Driver
~

4
' - System Clock,

Control Logic,
and 1/0
Counters

7
1/0 CLOCK

CS

/

~

5

Terminal numbers shown are for the D, JG, and P packages only.

~TEXAS

INSTRUMENTS
2-374

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1549C, TLV15491, TLV1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 C - JANUARY 1993 - REVISED MARCH 1995

Terminal Functions
TERMINAL

I/O

DESCRIPTION

2

I

Analog input. The driving source impedance should be ,.; 1 kQ. The external driving source to ANALOG IN should
have a current capability 2: 10 mA.

CS

5

I

Chip select. A high-to-Iow transition on CS resets the internal counters and controls and enables DATA OUT and
I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system clock. A low-to-high
transition disables I/O CLOCK within a setup time plus two falling edges of the internal system clock.

DATA OUT

6

0

This 3-state serial output for the ND conversion result is in the high-impedance state when CS is high and active
when CS is low. With a valid chip select, DATA OUT is removed from the high-impedance state and is driven to
the logic level corresponding to the MSB value of the previous conversion result. The next falling edge of I/O
CLOCK drives DATA OUT to the logic level corresponding to the next most significant bit, and the remaining bits
are shifted out in order with the LSB appearing on the ninth falling edge of I/O CLOCK. On the tenth falling edge
of I/O CLOCK, DATA OUT is driven to a low logic level so that serial interface data transfers of more than ten clocks
produce zeroes as the unused LSBs.

GND

4

I

The ground return for internal circuitry. Unless otherwise noted, all voltage measurements are with respect to·GND.

I/O CLOCK

7

I

The input/output clock receives the serial I/O CLOCK input and performs the following three functions:
1) On the third falling edge of I/O CLOCK, the analog input voltage begins charging the capacitor array and
continues to do so until the tenth falling edge of I/O CLOCK.
2) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.
3) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock.

REF+

1

I

The upper reference voltage value (nominally VCC) is applied to REF+. The maximum input voltage range is
determined by the difference between the voltage applied to REF + and the voltage applied to REF-.

NAME

NO.

ANALOG IN

REF-

3

I

The lower reference voltage value (nominally ground) is applied to this REF-.

VCC

8

I

Positive supply voltage

detailed description
With chip select (CS) inactive (high), the 110 CLOCK input is initially disabled and DATA OUT is in the highimpedance state. When the serial interface takes CS active (low), the conversion sequence begins with the
enabling of I/O CLOCK and the removal of DATA OUT from the high-impedance state. The serial interface then
provides the 110 CLOCK sequence to I/O CLOCK and receives the previous conversion result from DATA OUT.
I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface.
The first ten I/O clocks provide the control timing for sampling the analog input.
There are six basic serial interface timing modes that can be used with the TLV1549. These modes are
determined by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are:
(1) a fast mode with a 1O-clock transfer and CS inactive (high) between transfers, (2) a fast mode with a 10-clock
transfer and CS active (low) continuously, (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high)
between transfers, (4) a fast mode with a 16-bit transfer and CS active (low) continuously, (5) a slow mode with
an 11- to 16-clock transfer and CS inactive (high) between transfers, and (6) a slow mode with a 16-clock transfer
and CS active (low) continuously.
The MSB of the previous conversion appears on DATA OUT on the falling edge of CS in mode 1, mode 3, and
mode 5, within 21 ~s from the falling edge of the tenth I/O CLOCK in mode 2 and mode 4, and following the
16th clock falling edge in mode 6. The remaining nine bits are shifted out on the next nine falling edges of the
I/O CLOCK. Ten bits of data are transmitted to the host serial interface through DATA OUT. The number of serial
clock pulses used also depends on the mode of operation, but a minimum of ten clock pulses is required for
conversion to begin. On the tenth clock falling edge, the internal logic takes DATA OUT low to ensure that the
remaining bit values are zero if the I/O CLOCK transfer is more than ten clocks long.
Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that
can be used, and the timing on which the MSB of the previous conversion appears at the output.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-375

TLV1549C, TLV15491, TLV1549M
1O-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 C - JANUARY 1993 - REVISED MARCH 1995

Table 1. Mode Operation
MODES

Fast Modes

Slow Modes

CS

NO. OF

110 CLOCKS

MSB AT DATA ourt

Mode 1

High between conversion cycles

10

CS falling edge

Mode 2

Low continuously

10

Within 21

Mode 3

High between conversion cycles

Mode 4

Low continuously

Mode 5

High between conversion cycles

Mode 6

Low continuously

..
t This timing also .Initiates
sen ai-Interface commUnication .
:I: No more than 16 clocks should be used.

11 to 16:1:
16:1:
11 to 16:1:
16:1:

~s

CS falling edge
Withih21

~

TIMING
D.IAGRAM
Figure 6
Figure 7
Figure 8
Figure 9

CS falling edge

Figure 10

16th clock falling edge

Figure 11

All the modes require a minimum period' of 21 Ils after the falling edge of the tenth 1/0 CLOCK before a new
transfeJ sequence can begin. During a serial 1/0 CLOCK data transfer, CS must be active (low) so that the 1/0
CLOCK input is enabled. When CS is toggled between data transfers (modes 1, 3, and 5), the transitions at CS
are recognized as valid only if the level is maintained for a minimum period of 1.425 Ils after the transition. If
the transfer is more than ten 1/0 clocks (modes 3, 4, 5, and 6), the rising edge of the eleventh clock must occur
within 9.5 j.lS after the falling edge of the tenth I/O CLOCK; otherwise, the device could lose synchronization with
the host serial interface and CS has to be toggled to restore proper operation.
fast modes

The device is in a fast mode when the serial 1/0 CLOCK data transfer is completed within 21 Ils from the falling
edge of the tenth 1/0 CLOCK. With a 1O-clock serial transfer, the device can only run in a fast mode.
mode 1: fast mode, CS inactive (high) between transfers, 10-clock transfer
In this mode, CS is inactive (high) between seriaII/O-CLOCK transfers and each transfer is ten clocks long. The
falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge
of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time.
Also, the rising edge of CS disables 1/0 CLOCK within a setup time plus two falling edges of the internal system
clock.
mode 2: fast mode, CS active (low) continuously, 10-clock transfer
In this mode, CS is active (low) between seriaII/O-CLOCK transfers and each transfer is ten clocks long. After
the initial conversion cycle, CS is held active (low) for subsequent conversions. Within 21 Ils after the falling
edge of the tenth 1/0 CLOCK, the MSB of the previous conversion appears at DATA OUT.
mode 3: fast mode, CS inactive (high) between transfers, 11- to 16-clock transfer
In this mode, CS is inactive (high) between seriaII/O-CLOCK transfers and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables 1/0 CLOCK within a setup time plus two falling edges of the
internal system clock.
mode 4: fast mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between seriaII/O-CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. Within 21 j.lS after
the falling edge of the tenth 1/0 CLOCK, the MSB of the previous conversion appears at DATA OUT.
slow modes

In a slow mode, the serial 110 CLOCK data transfer is completed after 21 IlS from the falling edge of the tenth
110 CLOCK.

~TEXAS

2-376

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1549C, TLV15491, TLV1549M
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 c - JANUARY 1993 - REVISED MARCH 1995

mode 5: slow mode, CS inactive (high) between transfers, 11- to 16-clock transfer
In this mode, CS is inactive (high) between seriaIIiO-CLOCK transfers and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables 110 CLOCK within a setup time plus two falling edges of the
internal system clock.

mode 6: slow mode, CS active (Jow) continuously, 16-clock transfer
In this mode, CS is active (low) between seriaII/O-CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cyeie, CS is held active (low) for subsequent conversions. The falling edge of
the sixteenth 1/0 CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the
MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next
16-clock transfer initiated by the serial interface.

analog input sampling
Sampling of the analog input starts on the falling edge of the third 1/0 CLOCK, and sampling continues for seven
1/0 CLOCK periods. The sample is held on the falling edge of the tenth 1/0 CLOCK.

converter and analog input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by cloSing the Se switch and all ST switches simultaneously.
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all ST and Se switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF-)
voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector
looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF-. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half Vee), a bit 0 is placed in
the output register and the 512-weight capacitor is switched to REF-. If the voltage at the summing node is less
than the trip point of the threshold detector, a bit 1 is placed in the register and this 512-weight capacitor remains
connected to REF+ through the remainder of the successive-approximation process. The process is repeated
for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are determined.
With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-377

TLV1549C, TLV15491, TLV1549M
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 c - JANUARY 1993 - REVISED MARCH 1995

Threshold
Detector

51J 25J 1281 () 16

To Output
Latches

"OOE~r~r;:;r~t;:;r;:;r~t~f

T
REF-~_s;EF-~~;EF- ~~TREF-~~TREF-~~TREF-~_STREF-~_SrREF-~! REF-~;

"i

j j

,J 'j i i i

r<'1

j

Figure 1. Simplified Model of the Successive-Approximation System
chip-select operation
The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode.
A high-to-Iow transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device
returns to the initial state (the contents of the output data register remain at the previous conversion result).
Exercise care to prevent CS from being taken low close to completion of conversion because the output data
may be corrupted.

reference voltage inputs
There are two reference inputs used with the TLV1549: REF+ and REF-. These voltage values establish the
upper and lower limits of the analog input to produce a full-scale and zero reading, respectively. The values of
REF+, REF-, and the analog input should not exceed the positive supply or be lower than GND consistent with
the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or
higher than HEF + and at zero when the input signal is equal to or lower than REF-.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1): TLV1549C .................................. -0.5 V to 6.5 V
TLV15491 ................................... -0.5 V to 6.5 V
TLV1549M ................................... -0.5 V to 6 V
Input voltage range, V, (any input) ............................................ -0.3 V to Vee + 0.3 V
Output voltage range, Vo ................................................... -0.3 V to Vee + 0.3 V
Positive reference voltage, Vref+ ...................................................... Vee + 0.1 V
Negative reference voltage, Vref- .......................................................... -0.1 V
Peak input current (any input) ............................................................. ±20 rnA
Peak total input current (all inputs) ........................................................ ±30 mA
Operating free-air temperature range, TA: TLV1549C ................................... O°C to 70°C
TLV15491 .................................. -40°C to 85°C
TLV1549M ................................ -55°C to 125°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds ............................ 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to ground with REF- and GND wired together (unless otherwise noted).

~TEXAS

2-378

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLV1549C, TLV15491, TLV1549M
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 C - JANUARY 1993 - REVISED MARCH 1995

recommended operating conditions
Supply voltage, VCC

MIN

NOM

MAX

3

3.3

3.6

Positive reference voltage, Vref+ (see Note 2)

0
2.5

Differential reference voltage, Vref+ - Vref- (see Note 2)
Analog input voltage (see Note 2)

0

High-level control input voltage, VIH

I VCC = 3 V to 3.6 V

Low-level control input voltage, VIL

I VCC = 3 V to 3.6 V

Clock frequency at I/O CLOCK (see Note 3)

V
VCC+O.2

V

VCC

V

0.6

V

2.1

MHz

2

0

Setup time, CS low before first I/O CLOCK1'. tsu(CS) (see Note 4)

VCC

V
V

VCC

Negative reference voltage, Vref- (see Note 2)

UNIT

V

1.425

lJS

0

ns

Pulse duration, 1/0 CLOCK high, twH(IIO)

190

ns

Pulse duration, 1/0 CLOCK low, twL(l/O)

190

Hold time, CS low after last 1/0 CLOCK!, th(CS)

Transition time, 1/0 CLOCK, ttlllO) (see Note 5 and Figure 5)
Transition time, CS, tt(CS)

NOTES:

!ls

10

!lS

0

70

°C

TLV15491

-40

85

°C

TLV1549M

-55

125

°C

TLV1549C
Operating free-air temperature, TA

ns
1

2. Analog Input voltages greater than that applied to REF + convert as all ones (1111111111), while Input voltages less than that applied
to REF- convert as all zeros (0000000000). The TLV1549 is functional with reference voltages down to 1 V (Vref + - Vref-); however,
the electrical specifications are no longer applicable.
3. For 11- to 16-bit transfers, after the tenth 1/0 CLOCK falling edge (S 2 V), at least one 1/0 CLOCK rising edge (~2 V) must occur
within 9.5 !ls.
4. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS! before responding to the 1/0 CLOCK. Therefore, no attempt should be made to clock out the data until the minimum
CS setup time has elapsed.
5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the device functions with input clock transition time as slow as 1 lJS for remote data-acquisition
applications where the sensor and the AI D converter are placed several feet away from the controlling microprocessor.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-379

TLV1549C, TLV15491, TLV1549M
1O~BIT ANALOG..TO..DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 C - JANUARY 1993 - REVISED MARCH 1995

electrical characteristics over recommended operating free-air temperature range,
Vee Vref+ 3 V to 3.6 V, I/O CLOCK frequency 2.1 MHz (unless otherwise noted)

=

=

=

PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

VOL

Low-level output voltage

IOZ

Off-state (high-impedance-state) output current

MIN

TYPt

IOH=-1.6mA

Vee = 3 V to 3.6 V.

IOH =-20 !!A

Vee =3V.

IOL = 1,6 mA

0.4

Vee:" 3 Vto 3.6 V.

IOL = 20 !!A

0.1

Vo=Vee.

CSatVec

10

VO=O.

CSat VCC

-10

IIH

High-level input current

VI = VCC

IlL

Low-level input current

VI=O

ICC

Operating supply current

eSatOV

ei

t

Input capacitance

Vref+ =VCC.

2.5
-2.5

!!A
!!A

0.4

2.5'

mA

-1

During sample cycle

30

TLV1549M. (Analog)

During sample cycle

30

TLVl549C. I (Control)

5

TLV1549M. (Control)

5

~TEXAS

2-380

10

Vref-=GND

TLV1549C. I (Analog)

INSTRUMENTS
POST OFFICE BOX655303 • DALLAS. TEXAS 75265

Il A

0.005

1

All typical values are at VCC = 3.3 V. TA = 25°C.

V

-0.005

VI=O
Maximum static analog reference current into REF+

UNIT
V

Vee-0.1

VI=Vce

Analog input leakage current

MAX

2.4

Vee =3 V.

!!A
!!A

55
15

pF

TLV1549C, TLV15491, TLV1549M
10-81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 C - JANUARY 1993 - REVISED MARCH 1995

operating characteristics over recommended operating free-air temperature range,
Vee vref+ 3 V to 3.6 V, 1/0 CLOCK frequency 2.1 MHz

=

=

=

PARAMETER

TEST CONDITIONS

MIN

Linearity error (see Note 6)

UNIT

±1

LSB

Zero error (see Note 7)

See Note 2

±1

LSB

Full-scale error (see Note 7)

See Note 2

±1

LSB

±1

LSB

21

~s

Total unadjusted error (see Note 8)
!conv

MAX

Conversion time

See Figures 6-11

21
+101/0
CLOCK
periods

!c

Total cycle time (access, sample, and conversion)

See Figures 6-11
and Note 9

tv

Valid time, DATA OUT remains valid after 1/0 CLOCKJ-

See Figure 5

!d(l/O-DATA)

Delay time, 110 CLOCKJ- to DATA OUT valid

See Figure 5

240

ns

tPZH, tpZL

Enable time, CSJ- to\ DATA OUT (MSB driven)

See Figure 3

1.3

~s

tpHZ, tpLZ

Disable time,

See Figure 3

180

ns

tr{bus)

Rise time, data bus

See Figure 5

300

ns

tf(bus)

Fall time, data bus

See Figure 5

300

ns

9

~s

cst to DATA OUT (high impedance)

Delay time, 10th 1/0 CLOCK! to cst to abort conversion (see Note 10)

10

~s

ns

ld(l/O-CS)
NOTES: 2. Analog Input voltages greater than that applied to REF + convert as all ones (1111111111), while Input voltages less than that applied
to REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref+ - Vref-); however,
the electrical specifications are no longer applicable.
6. Linearity error is the maximum deviation from the best straight line through the AID transfer characteristics.
7. Zero error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference
between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero, and full-scale errors.
9. 1/0 CLOCK period =1/(1/0 CLOCK frequency). Sampling begins on the falling edge of the third 1/0 CLOCK, continues for seven
1/0 CLOCK periods, and ends on the falling edge of the tenth 1/0 CLOCK (see Figure 5).
10. Any transitions of CS are recognized as valid only if the level is maintained for a minimum of a setup time plus two falling edges of
the internal clock (1.425 ~s) after the transition.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-381

TLV1549C, TLV15491, TLV1549M
10-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071C - JANUARY 1993 - REVISED MARCH 1995

PARAMETER MEASUREMENT INFORMATION

Vcc

Test Point

DATAOUT---'~~~~--.

Figure 2. Load Circuit

~o::....:::::"':"
_ _. .J2V {I
.
\-0.8 V
I!

CS

J.----.f-I

~
I
2.4V(
-----(.

tPZH. tpZL
DATA OUT

tPHZ. tPLZ

)90%

0.4 v

10%

Figure 3. DATA OUT to Hi-Z Voltage Waveforms

CS

~

2Vr-:
I!

\- 0.8V

t

su(CS)

((, .....
, _ _ _ _ _ _...J

1"'",
~

0.8V

.1

th(CS)

I

1

1/0 CLOCK

I

I"

~I

iJ;;\.

O.8V

~ CI~~k y~Ci~~k ~
Figure 4. CS to 1/0 CLOCK Voltage Waveforms

---+I 14-

tt(I/O)

1

I
1

1/0 CLOCK

0.8 V

0.8 V
: . - - 1/0 CLOCK Period

0.8 V

---.l

td(I/Q-DATA) ~

tv
DATA OUT

-\<11--+1 I

2.4 V { } 2.4 V
_ _ _0~.4~V~~,..._~0.4~V~_ _ _ _ _ _...

I I
I+- tr(bus). tf(bus)

~

Figure 5. 1/0 CLOCK and DATA OUT Voltage Waveforms

~TEXAS

2-382

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLV1549C, TLV15491, TLV1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 C - JANUARY 1993 - REVISED MARCH 1995

PARAMETER MEASUREMENT INFORMATION

CSl1----------------------------'

(see Note A)

1
1

1/0

CLOCK
1
1

r---..,-',~

DATA
OUT

1

1

~~-M-S-B------ Previous Conver,sion Data ---------t~ojoIIl..1_
LSB

1

1

Initialize

AID
Conversion -+11
Interval
(S; 21 !ls) Initialize

Figure 6. Timing for 10-Clock Transfer Using CS
_ . . . , . - Must Be High on Power Up
(see

Not~~) ~)-------------~--------------------'J'jl-1/0

:

'------......,,.fl

CLOCK-M

-----~

1

See Note B

'~ A9

DATA
OUT

Low Level

1

I..
1

- - - - - - - - - t o j o I I 1 - AID Conversion

MSB

Interval
(S; 21 J.lS)

1

--..I

~

1

Initialize

Initialize

Figure 7. Timing for 10-Clock Transfer Not Using CS
See Note C

CSI

111111111

(see Note A)f
1/0

'r--,!r--j

r~

1
1

CLOCK

1

DATA
OUT

Low
Level

1~--Al~D~~

1

1

r7~H;ri.-=Z1-lr-JC§)(

1

11401-------- Previous Conversion Data ---------t~ojoIIl..1_ Conversion ~
1 MSB
LSB
Interval
1
Initialize
(S; 21 J.lS) Initialize

Figure 8. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed Within 21 Ils)
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock aiter CSJ. before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup
time has elapsed.
B. A low-to-high transition of CS disables I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system
clock.
C. The first I/O CLOCK must occur aiter the end of the previous conversion.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-383

TLV1549C, TLV15491, TLV1549M
10-81T ANAlOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 C - JANUARY 1993 - REVISED MARCH 1995

PARAMETER MEASUREMENT INFORMATION
_ ~ Must Be High on Power Up
CS
(
(see Note A)
j
1/0

CLOCK

((

Jj

~~

1

~

See NoteC

1

D~~~ ~

Lo_w_L_e_v_el_--'l~

A9

'--_ _

1
1
AID Conversion
i
1I*4Interval
--+1
M-S-B- - - - - Previous Conversion Data ------.,.-LS::-:B~~.41
($ 21 J!s)lnitialize
Initialize

Figure 9. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Completed Within 21 J.ls)

111111111

CS --,
(see Note A)
1

1

I

1/0

11

CLOCK _.1---'

I

(j~,--_
1

f161L..~~·L
~m 111

....I

See Note B

I
DATA
OUT

I
Low 1 Hi-Z State ~
Level
~

.AD

I

14--------- Previous Conversion Data - - - - - - - - ' - - . . , .
MSB

LSB

Initialize

1
1
1

I

_I

~ AID ....

Conversion
Interval
($ 21 J!s)

I
I
I
I
Initialize

Figure 10. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed After 21 J.LS)
_ ~ Must Be High on Power Up
CS
.
(see Note A)
\
1/0

~r---R-

1

CLOCK~

See Note B

1

See Note C

~--~~

DATAJr A9

OUT~

'--JI'-_ _ _

1r404-M-S-B-----

I
I

AID Conversion Interval
($ 21 J!S)

Initialize

Figure 11. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Completed After 21 J.ls)
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal system
clock after CSJ. before responding to the 1/0 CLOCK. No attempt should be made to clock out the data until the minimum CS setup
time has elapsed.
B. A low-to-high transition of CS disables 1/0 CLOCK within a maximum of a setup time plus two falling edges of the internal system
clock.
C. The first 1/0 CLOCK must occur after the end of the previous conversion.

2-384

:II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1549C, TLV15491, TLV1549M
10-81T ANALOG-TO-DiGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 C - JANUARY 1993 - REVISED MARCH 1995

APPLICATION INFORMATION
1111111111

!

I.

See Notes A and B

/

1111111110

~ Vii

1111111101

G>
"D

0

()

••
•
1000000001

:;

~

1000000000

~."

0111111111

VZT = VZS + 1/2 LSB

0

is

-/

.,••

/

I~ lLf'. . . . . .
IIV~V
~

0000000001
0000000000

VFT

~

0.003

0.006

1022

\

1021

\

•
••

VFS

= VFS -1/2 LSB

/'

513

I
I

512

II

/'

V

c.
G>

iii

511

I
I

••
•

II

T

o :!!

~V

)~ / ' II I
/'
I!

/' ,/'

VZS

0000000010

/~

~

~

A:

1023

2

I

Ii

•••

1.5315

o

1.5345

•••

1.5375

3.066

~

o
3.069

3.072

'"

VI - Analog Input Voltage - V

NOTES: A. This curve is based on the assumption that Vref+ and Vref- have been adjusted so that the voltage at the transition from digital 0
to 1 (VZT) is 0.0015 V and the transition to full scale (VFT) is 3.0675 V. 1 LSB = 3 mY.
B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is
the step whose nominal midstep value equals zero.

Figure 12. Ideal Conversion Characteristics
TLV1549
Analog Input

2

CS

ANALOG IN

110 CLOCK

5
7
Processor

DATA OUT

5-V DC Regulated

1

~

Control
Circuit

6

REF+
REFGND

To Source
Ground

14

l
Figure 13. Typical Serial Interface

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-385

TLV1549C, TLV15491, TLV1549M
10·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071 c - JANUARY 1993 - REVISED MARCH 1995

APPLICATION INFORMATION

simplified analog input analysis
Using the equivalent circuit in Figure 14, the time required to charge the analog input capacitance from 0 to Vs
within 112 LSB can be derived as follows:
The capacitance charging voltage is given by
(1 )
where
Rt = Rs + rj
The final voltage to 1/2 LSB is given by
Vc (1/2 LSB)

= Vs -

(Vs/2048)

(2)

Equating equation 1 to equation 2 and solving for time

tc gives

Vs - (VS/2048) = Vs(1_e-tc/RtCi)

(3)

tc (1/2 LSB) = Rt x Cj x In(2048)

(4)

and

Therefore, with the values given the time for the analog input signal to settle is
tc (1/2 LSB)

= (Rs + 1 kQ) x 60 pF x In(2048)

(5)

This time must be less than the converter sample time shown in the timing diagrams.
Driving Sourcet ~
Rs

I
I
I
I

VI

• TLV1549
ri

VS~VC

!

1 kO MAX.

I

I

1.
T

rh

Cj
50pFMAX

=
=
=
=

VI Input Voltage at ANALOG IN
Vs = External Driving Source Voltage
Rs Source Resistance
Input Resistance
ri
Ci Equivalent Input Capacitance

t Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.

Figure 14. Equivalent Input Circuit Including the Driving Source

2-386

~TEXAS .
INSTRUMENTS.·
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLV1570
3-V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169- DECEMBER 1997

•
•
•
•
•
•
•
•
•
•
•

Fast Throughput Rate: 1.25 MSPS
Eight Analog Input Channels
Channel Auto-Scan
Differential Nonlinearity Error: < ±1 LSB
Inte,gral Nonlinearity Error: < ±1 LSB
Signal-to-Noise and Distortion Ratio: 57 dB,
fl = 500 kHz
Single 3-V Supply Operation
Low Power ..• 21 mW
Auto·Power Down: 10 J.lA Max
Glueless Serial Interface to TMS320 DSPs
and (Q)SPI Compatible Microcontrollers
Internal Reference Voltage

applications
•
•
•

Mass Storage and Hard Disk Drive
Industrial Process Control
Communications

•
•

Automotive
High-Speed Digital Signal Processing
ow PACKAGE
(TOP VIEW)

CH4
CH3
CH2
CH1
CHO
DVDD
DGND

description

10
2
3
4

20

AIN

19

MO
CH5
CH6
CH7

18

5
6
7
8
9
10

15
14
13
12

AVDD
AGND

VREF+
FS
The TLV1570 is a 10-bit data acquisition system
SCLK
CS
that combines an a-channel input multiplexer
11
SDIN
SDOUT
(MUX), a high-speed 10-bit ADC, an on-Chip
reference, and a high-speed serial interface. The
part contains an on-chip control register allowing
control of channel selection, channel auto-scan, and power down via the serial port. The MUX is independently
accessible. This allows the user to insert a signal conditioning circuit such as an anti-aliasing filter or an amplifier,
if required, between the MUX and the ADC. This means that one signal conditioning circuit can be used for all
eight channels.

The TLV1570 operates from a single 3 V power supply. It accepts an analog input range from 0 V to AVDD and
digitizes the input at a maximum 1.25 MSPS throughput rate. The power dissipation is only 21 mW. The part
features an auto-powerdown mode that automatically powers down to 10llA whenever the conversion is not
performed.
The TLV1570 communicates with digital microprocessors via a simple 4- or 5-wire serial port that interfaces
directly to the Texas Instruments' TMS320 DSPs and (Q)SPI compatible microcontrollers without using
additional glue logic.
Very high throughput rate, simple serial interface, 3 V operation, and low power consumption make the TLV1570
an ideal choice for compact or remote high-speed systems.
AVAILABLE OPTIONS
PACKAGED DEVICES
SMALL OUTLINE
(OW)

SMALL OUTLINE
(PW)

O°C to 70°C

TLV1570CDW

TLV1570CPW

-40°C to 85°C

TLV1570lDW

TLV1570lPW

TA

PRODUCT PREVIEW information concerns products in the formative or
daslqn phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products wtthout notice.

~TEXAS

Copyright © 1997, Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-387

::w
:>
w
a:
D..

I-

o
~
o

oa:
D..

TLV1570
3-V a-CHANNEL 10,,81T 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169 - DECEMBER 1997

functional block diagram
MO

AVDD

AIN

DVDD

VREF+

CHO
CH1
CH2
CH3

10-BIT
SARADC

MUX

CH4
CH5
CH6
CH7

AGND

SCLK

::a
oc

AGND

DGND

o-I

Terminal Functions
TERMINAL

"tJ

::a

:e

FS

CS

c:

m
<
m

SDOUT

1/0 REGISTERS
AND CONTROL LOGIC

SDIN

"tJ

NAME

NO.

AGND

14

AIN

20

AVDD

15

DESCRIPTION

1/0
Analog ground
I

ADC analog input
Analog supply voltage

5,4,3
2.1,18
17,16

I

Analog input channels 0 - 7

CS/Powerdown

12

I

Chip Select. A logic low on this input enables the TLV1570. A logic high disables the device and disconnects
the power to the TLV1570.

CHO-CH7

DGND

7

Digital ground

DVDD

6

Digital. supply voltage, 3 V

FS

8

1/0

Frame sync inpuVoutput (bi-directional) in DSP mode. The falling edge of the frame sync pulse from DSP
indicates the start of a serial data frame shifted out of the TLV1570. The FS terminal is pulled high when
interfacing to a microcontroller.

MO

19

a

On-chip MUX analog output

SCLK

9

I

Serial clock input. This clock synchronizes the serial data transfer and is also used for internal data
conversion.

SDIN

10

I

Serial data input to configure the internal control register.

SDOUT

11

0

Serial data output. ND conversion results are provided at this output terminal.

VREF+

13

1/0

Internal reference voltage output for external coupling.

~TEXAS

INSTRUMENTS
2-388

POST OFFICE BOX 6~5303 • DALLAS. TEXAS 75265

TLV1570
3-V a-CHANNEL 10.-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169 - DECEMBER 1997

absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage, AGND to AVDD, DGND to DVDD ..................................... -0.3 V to 6.5V
Analog input voltage range ................................................... -0.3 V to AVDD+0.3
Reference input voltage ............................................................... AVDD+0.3
Digital input voltage range .................................................... -0.3 V to DVDD+0.3
Operating virtual junction temperature range, TJ ..................................... -40°C to 150°C
Operating free-air temperature range, TA ..............................................
to 70°C
Storage temperature range, T5t9 ................................................... -65°C to 150°C
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds ............................... 260°C

ooe

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operations of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions
power supplies
MIN

NOM

MAX

AVDD

Analog supply voltage

2.7

3

3.6

V

DVDD

Digital supply voltage

2.7

3

3.6

V

UNIT

~

analog inputs
MIN
AIN

Analog input voltage

AGND

w

MAX

:>
w

VREF+

a:

digital inputs
High-level input voltage, VIH

DVDD = 2.7 V to 3.6 V

Low-level input voltage, VIL

DVDD = 2.7 V to 3.6 V

MIN

NOM

2.1

2.4

MAX

UNIT
V

0.8

V

20

MHZ

Input SCLK frequency

DVDD = 2.7 V to 3.6 V

SCLK pulse duration, clock high, tw(SCLKH)

DVDD = 2.7 V to 3.6 V

23

ns

SCLK pulse duration, clock low, tw(SCLKL)

DVDD = 2.7 Vto 3.6 V

23

ns

D..

I-

o

::::l
C

oa:

D..

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-389

TLY1570
3·Y a·CHANNEL 10·81T 1.25·MSPS
SERIAL ANALOG·TO·DIGITAL CONYERTER
SLAS169- DECEMBER 1997

electrical characteristics,over recommended operating free-air temperature range, AVoo = DVOO
= 2.7 V to 3.6 V, fSCLK = 20MHz, VREF+ = 2.4 V (Internal VREF Mode) (unless otherwise noted)
digital specifications
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Logic inputs
IIH

High-level input current

OVDD =3 V

-50

50

j.lA

IlL

Low-level input current

OVDO =3 V

-50

50

j.lA

CI

Input capacitance

5

pF

Logic outputs
VOH

High-level output voltage

10H = 50 j.lA - 0.5 rnA

DVDo-O·4

V

VOL

Low-level output voltage

10L = 50 j.lA - 0.5 rnA

0.4

V

102

High-impedance-state output current

Co

Output capacitance

-50

50
5

j.LA
pF

dc specifications
PARAMETER

"'tJ

TEST CONDITIONS

MIN

Resolution

TYP

MAX

UNIT

1

10

Bits

:D

Accuracy
INL

Integral nonlinearity

±0.6

±1

C

DNL

Differential nonlinearity

±0.4

±1

Offset error

±0.1

±0.15

%FSR

Gain error

±0.1

±0.2

%FSR

o

c:
o.....

Input full scale range

:e

GND

Input capacitance

:D

-m<

LSB
LSB

Analog input

"'tJ

m

Best fit

VREF+
15

Input leakage current

±1

VAIN = 0 to AVOD

V
pF

j.LA

Voltage reference
VREF+

Internal reference voltage

Internal reference mode

VREF+

External reference voltage

External reference mode

2.37

2.38

2.4

V

AVDO

V

Power supply
100 + IREF

Operating supply current

AVOO = OVOO = 3 V,

IpO

Supply current in powerdown mode

100 + IREF

Power dissipation

AVOD = OVDD = 3 V

fSCLK = 20M Hz

~TEXAS

INSTRUMENTS
2-390

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

rnA
10

21

j.LA
mW

TLV1570
3-V a-CHANNEL 10-81T 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169 - DECEMBER 1997

electrical characteristics, over recommended operating free-air temperature range, AVoo = DVoo
2.7 V to 3.6 V, fSCLK 20M Hz, VREF+ 2.4 V (Internal VREF Mode) (unless otherwise noted)
(continued)

=

=

=

ac specifications
PARAMETER

THD

MIN

TYP

Signal-to-noise ratio + distortion

f(input) = 100 kHz

TEST CONDITIONS

54

57

MAX

UNIT

Total harmonic distortion

fOnout) = 100 kHz

56

60

dB

Effective number of bits

f(input) = 100 kHz

8.7

9.35

Bits

Spurious-free dynamic range

fOnoutl = 100 kHz

57

62

dB

dB

Analog Input

Channel-to-channel cross talk

-75

dB

BW

Full-power bandwidth

12

MHz

BW

Small-signal bandwidth

20

MHz

timing specifications
PARAMETER

Ie

SCLK period

t(rs)

Reset and sampling period

TEST CONDITIONS

DVDD =3 V

tc

Conversion period

tsu1

FS setup time to SCLK falling edge in DSP mode

th1

FS hold time to SCLK falling edge in DSP mode

tsu2

FS setup time to CS falling edge in DSP mode

th2

FS hold time to CS falling edge in DSP mode

td1

Output delay after SCLK rising edge in DSP mode

MIN

TYP

MAX

50

UNIT

ns
6

SLCK
cycles

10

SLCK
cycles

10

ns

4

ns

5.5

ns

9

ns
15

25

ns

id(L) 1

FS falling edge to next SCLK falling edge in DSP mode

6

ns

id(L)2

SCLK rising edge after CS falling edge in I!C mode

4

ns

id2

Output delay after SCLK rising edge in I!C mode

tsu3

Serial input data setup time to SCLK falling edge

10

ns

th3

Serial input data hold time to SCLK falling edge

4

ns

15

25

ns

Specifications subject to change without notice.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-391

3:
w

:>
w
a:

0...

I-

o

::l
C

oa:

0...

TLV1570
3-V a-CHANNEL 10-81T 1.25-MSPS
.SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169- DECEMBER 1997

PARAMETER MEASUREMENT INFORMATION
1

I+------ Ie

SCLK

cs

\

~

1
----'1

I

FS

\\~
tsu2

"tJ

::D

SOIN

0

I
I
I
I
I

\\\\\
Isu1

I..
I
I

/

\

I
I
I
I
I
I
I

4

I
I·

~

I"

.1

0115

}('--___r-___
!
-'X

K\\~

1

I
I

·1

(

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
l~td(L)1 I
I
I
I
I
I
I
I
I
I
I
I
I
I
II
..
tsu3
·1
II
. -_ _.~I_lh3
I"
II r----r----~I~--------

I
I

·1

Ih2

I

-------------------(

0114

-I

0113

I

C

l+-+td1

c::

0

~

\
I
I
I
I
I
I
I
I

:.-- th1

I

3

2

11

I

SOOUT

-----------(

"tJ

><'---_----'x'-__

0

0

Figure 1. DSP Mode Timing Diagrams

::D

m

td(L)2

-<

SCLK

m

=E

I..
I
I

I
I
I

cs

Y

\

/

\

I
I
I
I
I
I
I
I
I
I

\\ \ \1I
I
I

FS

SOIN

I
I
I
I
I

tsu3

----~--i---(

0115

I
I
I

SOOUT

-------,-(

I..
I
I
I

·1

/

\'------II

I
I

I
I
I
I

X

I ~---------~I

X

0114

X-·

0113
'--_________
...II
td2

0

X

L

I
I
I
I

l+-th3~

I

-0

Figure 2. IlC Mode Timing Diagrams

~TEXAS

INSTRUMENTS
2-392

4

3

21

.1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0112

I. . . 1

'------'*---

X

0

I

I

TLV1570
3-V a-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169 - DECEMBER 1997

definitions of specifications and terminology
integral nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full scale point is defined as level
1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two points.

differential nonlinearity
An ideal AOC exhibits code transitions that are exactly 1 LSB apart. ONL is the deviation from this ideal value.
A differential nonlinearity error of less than ±1 LSB ensures no missing codes.

zero offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.

gain error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code transitions.

;:
W

signal-to-noise ratio + distortion (SINAO)
SINAO is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAO is expressed in
decibels.

effective number of bits (ENOB)

Q.

I-

N = (SINAO - 1.76)/6.02
It is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAO.

total harmonic distortion (THO)
THO is the ratio of the rms sum Df the first six harmonic components to the rms value of the measured input signal
and is expressed as a percentage or in decibels.

spurious free dynamic range (SFOR)
SFOR is the difference in dB between the rms amplitude of the input signal and the peak spurious Signal.

~TEXAS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

a:

o

For a sine wave, SINAO can be expressed in terms of the number of bits. Using the following formula,

INSTRUMENTS

s:w

2-393

::J
C

oa:
Q.

TLV1570
3-V 8-CHANNEL to-BIT1.25·MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169 - DECEMBER 1997

PRINCIPLES OF OPERATION
serial input data format

I 0115 I 0114 I 0113 I 0112

0111

0110

019

018

017

016

015

014

013

011·

012

010

internal register description
Bit

Oescrlptlon

0115

Software powerdown. 0- powerup, 1 - powerdown

0114

Reads out values of the internal register, 1 - read. Only 0115 - 011 will be read out.
These two bits select the self-test voltage to be applied to the ADC input during next ciock cycle:
0113

0112
0
1
0
1

a

0113,0112

0
1
1

Allow AIN to com in normally
Apply AGNO to AIN,
Apply VREF to AIN,
Apply VREF/2 to AIN

0111

Low power mode. If CLKC < 10 MHz, then 0111 can be set to 0 and power consumption is reduced 20%.

0110

This bit controls channel auto-scan function. 0 - auto-scan disabled, 1 - auto-scan enabled.
These two bits selectthe channel auto-scan modes (when 0110 is 1).

."
:D

o-f

018
0
1
0
1

a
1
1

oC

c:

019
0

019; 018

017
019, 018, 017

CH1, CH2, CH3, ..... , CH8
CH1, CH3, CH5, CH7
CH2, CH4, CH6, CH8
CH 8, CH7, CH6, ..... , CH1

Auto-scan reset, 1 - reset. To use auto-scan feature, this bit must be set to 1 in the first cycle after power up.
These three bits select which of the eight channels is to be used for sampling when the auto-scan is disabled (0110 is 0).
See channel selection format tables for details.

016

Internal or external reference. If 016 = 1 then the internal reference is enabled. If 016 = 0 then the external reference is
enabled .

015

Reserved (always set to 0)

014

Enables/Disables auto-powerdown function,

-

013

Reserved (always set to 1).

012

Reserved (always set to 0)

011

Reserved (always set to 0)

==

010

Don't care

."
:D

m
<
m

a - Enable, 1 -

Disable.

channel selection format
019

018

017

CHO

0

0

a

+

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

CH1

CH2

CH3

CH5

CH6

CH7

+
+
+
+
+
+
+

~TEXAS

2-394

CH4

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1570
3-V a-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DiGITAL CONVERTER
SLAS169 - DECEMBER 1997

APPLICATION INFORMATION
The TLV1570 is a 10-bit a-analog input channel analog-to-digital converter with the throughput up to
1.25 MSPS. To run at its fastest conversion rate, it must be clocked at 20 MHz. The TLV1570 can be easily
interfaced to microcontrollers, ASICs, DSPs, or shift registers. Its serial interface is designed to be fully
compatible with Serial Peripherallnterface(SPI) and the TMS320 DSP serial ports. It requires no hardware to
interface between the TLV1570 and the microcontrollers (I!Cs) with the SPI serial port or the TMS320 DSPs.
However, the speed will be limited by the SCLK rate of the I!C or the DSP.
The TLV1570 interfaces to the DSPs over five lines: CS, SCLK, SDOUT, SDIN, and FS, and interfaces to I!CS
over four lines: CS, SCLK, SDOUT, and SDIN. The FS input should be pulled high in I!C mode. The chip is in
tristate and powerdown mode when the CS is high. After the CS fails, the TLV1570 checks the FS input at the
CS's falling edge to determine the operation mode. If the FS is low, the DSP mode is set, else the I!C mode is
set.
TMS320

TLV1570

O.111F

f

CS
VREF+ SCLK

,

FS

4L.-

..

-=-

SOIN
SOOUT

XF
CLKX
CLKR
FSX
FSR
OX
DR

::w

:>
w
a:

Figure 3. DSP to TLV1570 Interface
2

3

4

5

6

7

8

9

15

16

1

2

3

4

5

6

c..

7

I-

SCLK

o

CS ~u~-r""r-""""""""""""""""""""""~((I-""""""""""""""""""""""""""-I
jj
FS ~~____________________~)\
,,~._________________

::J

C

oa:
c..

Figure 4. Typical Timing Diagram for DSP Application

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-395

TLV1570
3-VS-CHANNEL 1a-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169-DECEMBER 1997
I

APPLICATION INFORMATION
TLV1570

f

CS
VREF+ SCLK
FS -

1/0 Terminal
SCLK
DVDD

-=-

SDIN

DX

SDOUT

DR

Figure 5.IlC to TLV1570 Interface
SCLK

CS
FS

"tJ

~r-""T-""""""""""""""""""""~J{~j""""""""""""""""""""""""-~

........~....+-........................................~)(~j................................................--

:II

0

SDIN

C

c:
0

-I

SDOUT

"tJ

Figure 6. typical Timing Diagram for IlC Application

:II

m

-m<
:e

~TEXAS

2-396

INSTRUMENTS'
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1572
2.7 V TO 5.5 V, 10-BIT, 1.25 MSPS
SERIAL ADe WITH AUTO-POWER DOWN
1997

•
•
•
•
•
•
•
•
•
•

o PACKAGE

Fast Throughput Rate: 1.25 MSPS
a-pin SOIC Package
Differential Nonlinearity Error: < ± 1 LSB
Integral Nonlinearity Error: < ±1 LSB
Signal-to-Noise and Distortion Ratio: 59 dB,
f(input) = 500 kHz
Single 3-V to 5-V Supply Operation
Very Low Power: a mW at 3Vj 25mW at 5 V
Auto-Powerdown: 10 IlA Maximum
Glueless Serial Interface to TMS320 DSPs
and (Q)SPI Compatible Micro-controllers
Inherent Internal Sample and Hold
Operation

(TOP VIEW)

CSD8
VREF
2
7
GND 3
6
AIN 4
5

DO
FS
VCC
SCLK

Applications
•
•
•
•
•
•

Mass Storage and HDD
Automotive
Digital Servos
Process Control
General Purpose DSP
Contact Image Sensor Processing

description
The TLV1572 is a high-speed 1a-bit successive-approximation analog-to-digital converter (ADC) which
operates from a single 2.7-V to 5.5-V power supply and is housed in a small8-pin SOIC package.
The TLV1572 accepts an analog input range from a to Vce and digitizes the input at a maximum 1.25MSPS
throughput rate. The power dissipation is only 8 mW with 3-V supply or 25 mW with 5-V supply. The part features
an auto-powerdown mode that automatically powers down to 1a IlA whenever the conversion is not performed.
The TLV1572 communicates with digital microprocessors via a simple 3- or 4-wire serial port that interfaces
directly to the Texas Instruments' TMS32a DSPs and (Q)SPI compatible microcontrollers without using
additional glue logic.
Very high throughput rate, simple serial interface, SO-8 package, 3-V operation, and low power consumption
make the TLV1572 an ideal choice for compact or remote high-speed systems.
AVAILABLE OPTIONS
PACKAGE
TA

~~~~;~~o~:1: 8i;=~~:"~e~~::r::: le:,::g~m:~

standard warranty. Production processing does not necessarily Include
testlng of all parameters.

SMALL OUTLINE
(0)

QOC to 7QoC

TLV1572CD

-4QoC to 85°C

TLV1572ID

~TEXAS

Copyright © 1997, Texas Instruments Incorporated

.

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-397

TLV1572
2.7 V TO 5.5 V, 10-BIT, 1.25 MSPS
SERIAL ADC WITH AUTO-POWER DOWN
SLAS171-DECEMBER 1997

functional block diagram
VCC

VREF~-----------.

10·BIT
SARADC

VREF
GND
SCLK
FS

CONTROL LOGIC

DO

CS

GND

Terminal Functions
TERMINAL
NAME
CS/Powerdown

NO.
1

1/0

DESCRIPTION

I

Chip Select. A logic low on this input enables the TLV1572. A logic high disables the device and disconnects
the power to the TLV1572.
Analog input

AIN

2

I

VREF

3

I

GND

4

Reference voltage input. The voltage applied to this pin defines the input span of the TLV1572.
Ground

DO

5

0

Serial data output. ND conversion results are provided at this output pin.

FS

6

I

Frame sync input in DSP mode. The falling edge of the frame sync pulse from DSP indicates the start of
a serial data frame shifted out of the TLV1572. The FS input is tied to Vce when interfacing to' a
micro-controlier.

SCLK

7

I

Serial clock input. This clock synchronizes the serial data transfer and is also used for internal data
conversion.

VCC

8

Power supply, recommend connection to analog supply

~TEXAS

2-398

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLV1572
2.7 V TO 5.5 V, 10-BIT, 1.25 MSPS
SERIAL ADC WITH AUTO-POWERDOWN
SLAS171 - DECEMBER 1997

absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage, GND to Vee ....................................................... -0.3 V to 6.5V
Analog input voltage range .................................................... -0.3 V to Vee + 0.3
Reference input voltage ............................................................... Vee + 0.3
Digital input voltage range .................................................... -0.3 V to Vee + 0.3
Operating virtual junction temperature range, TJ .................................... -40°C to 150°C
Operating free-air temperature range, TA .............................................. ooe to 70°C
Storage temperature range, T519 ................................................... -65°C to 150°C.
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operations of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions
power supply
MIN
VCC

Supply voltage

NOM

2.7

MAX
5.5

analog inputs
VAIN

Analog input voltage

VREF

Reference input voltage

MIN

MAX

GND

VREF

UNIT
V

2.7

VCC

V

MIN

NOM

MAX

UNIT

2.1

2.4

digital inputs
High-level input voltage. VIH

Vee = 3 V to 5.5 V

Low-level input voltage, VIL

Vee = 3 V to 5.5 V

V

Input SCLK frequency

Vec = 4.5 V to 5.5 V

SCLK pulse duration, clock high. tw(SeLKH)

Vee = 4.5 V to 5.5 V

23

SCLK pulse duration. clock low. Iw(SCLKL)

Vec = 4.5 V to 5.5 V

23

Input SCLK frequency

Vee=3V

SeLK pulse duration. clock high. tw(SCLKH)

Vec=3 V

45

ns

SCLK pulse duration. clock low. tw(SCLKL)

Vee =3

v

45

ns

0.8

V

20

MHZ
ns
ns

10

MHZ

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-399

TLV1572
2.7 V TO 5.5 V, 10·BIT, 1.25 MSPS
SERIAL ADC WITH AUTO·POWERDOWN
SLAS171 - DECEMBER 1997

electrical characteristics over recommended operating free-air temperature range, VCC= 5 V, VREF
= 5V, fSCLK = 20MHz (unless otherwise noted)
digital specifications
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Logic Inputs

IIH.

High-level input current

Vee = 5V

-50

50

IlL

low-level input current

Vee =5V

-50

50

ei

input capacitance

5

!lA
!lA
pF

Logic outputs

VOH

High-level output voltage

IOH = 50~A - 0.5mA

Val

low-level output voltage

IOl = 50~A - 0.5mA

IOZ

High-impedance-state output current

eO

Output capacitance

V

Vee-O.4
0.4

V

-50

50

5

!lA
pF

dc specifications
PARAMETER

TEST CONDITIONS

MIN

Resolution

TYP

MAX

10

UNIT

Bits

Accuracy

INl

Integral nonlinearity

DNl

Differential nonlinearity

to.5
t1
to.3
t1
to.1 to.15
to.1
to.2

Best fit

Offset error
Gain error

lSB
lSB
%FSR
%FSR

Analog input

Input full scale range

GND

Input capacitance

Vee
15

input leakage current

50

VAIN = 0 to Vce

V
pF
~A

Voltage reference input

VREF+

Positive reference voltage

VREF-

Negative reference voltage

3
Internally connects to GND

Input resistance

Vec
GND

V

K.a

2

Input capcitance

V

300

pF

Power supply

VCC =5.5V,

fSClK = 20MHz

5.5

VCC =3 V,

fSClK = 10MHz

2.7

8.5

ICC + IREF

Operating supply current

IpD

Supply current in powerdown mode

VCC

Power dissipation

Vce =5 V

25

mW

Power dissipation

VCC =3 V

8

mW

~TEXAS

INSTRUMENTS
2-400

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10.

rnA

!lA

TLV1572
2.7 V TO 5.5 V, 10-BIT, 1.25 MSPS
SERIAL ADC WITH AUTO-POWERDOWN
SLAS171-DECEMBER 1997

electrical characteristics over recommended operating free-air temperature range, VCC= 5 V, VREF
= 5V, fSCLK = 20MHz (unless otherwise noted) (continued)
ac specifications
PARAMETER

THD

MIN

TYP

Signal-to-noise ratio + distortion

f(input) ~ 200 kHz

TEST CONDITIONS

54

58

MAX

UNIT

dB

Total harmonic distortion

fOnp!Jt) ~ 200 kHz

56

60

dB

Effective number of bits

f(input) ~ 200 kHz

8.7

9.35

Bits

Spurious-free dynamic range

fnnoutl ~ 200 kHz

57

62

dB

Analog Input

BW

FUll-power bandwidth

Source impedance

~

1 kQ

12

MHz

BW

Small-signal bandwidth

Source impedance

~

1 kQ

20

Mhz

timing specifications
PARAMETER

Ie
Ie

TEST CONDITIONS

MIN

SCLKperiod

VCC ~ 4.5 V - 5.5 V

50

SCLKperiod

VCC~2.7V-3.3V

100

trs

Reset and sampling period

tc

Conversion period

TYP

MAX

UNIT

ns
ns

6

SLCK
cycles

10

SLCK
cycles

tsul

FS setup time to SCLK falling edge in DSP mode

10

ns

thl

FS hold time to SCLK falling edge in DSP mode

4

ns

tsu2

FS setup time to CS falling edge in DSP mode

6

ns

th2

FS hold time to CS falling edge in DSP mode

9

tdl

Output delay after SCLK rising edge in DSP mode

id(L)l

FS falling edge to next SCLK falling edge in DSP mode

6

tLd(L)2

SCLK rising edge after CS falling edge in I!C mode

4

id2

Output delay after SCLK rising edge. in I!C mode

ns
15

25

ns
ns
ns

15

25

ns

Specifications subject to change without notice.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-401

TLV1572
2.7 V TO 5.5 V, 10-SIT, 1.25 MSPS
SERIAL ADC WITH AUTO-POWER DOWN
SLAS171-DECEMBER 1997

PARAMETER MEASUREMENT INFORMATION

I

I

SCLK

CS

~

\

I

tsu1
FS

\\l
tsu2

DO

14

I
I

I
I
I
I
I
I
I

I
I
I

\\\\\

~

I
:.-- th1
I
I
I I
I
14 "I
I
I
I .
I
I
I
I
"I
th2
14 .. I
I

(

~

/

\I

I

1+-+1- td(L)1

K\\~

~

3

2

11

I

1-4---:- te --'-----+1

L

/

\

I
I
I
I
I
I
I
I
I
I

I

I
I

~td1

-----------<

I

I

X

X

0

Figure 1. DSP Mode Timing Diagrams
td(L)2
SCLK

I..

..I

I
I
I
I

Y

I

I

\

\\\\:
FS

DO

I
I
I
I
I
I

--------{

td2

I
I
I
I
I
I
I
I
I

14

I
0

3

2

I

/

\

/

\

L

.. I
I

*

0

Figure 2. /lC Mode Timing Diagrams

~TEXAS

2-402

4

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

X

0

X

TLV1572
2.7 V TO 5.5 V, 10·SIT, 1.25 MSPS
SERIAL ADC WITH AUTO·POWERDOWN
SLAS171 - DECEMBER 1997

definitions of specifications and terminology
integral nonlinearity

Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full scale pOint is defined as level
1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two points.
differential nonlinearity

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
zero offset

The first code transistion should ideally occur at an analog value 1/2 LSB above VREF-. The zero offset error
is defined as the error between the ideal first transistion point and the actual first transistion. This error efectively
shifts left or right an ADC transfer function
gain error

The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code transitions.
signal-to-noise ratio + distortion (SINAO)

SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
effective number of bits (ENOS)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N = (SINAD - 1.76)/6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective'
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
'
total harmonic distortion (THO)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal
and is expressed as a percentage or in decibels.
spurious free dynamic range (SFOR)

SFDR is the difference in dB between the rms amplitude of the input signal and the largest peak spurious signal.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-403

TLV1572
2.7 V TO 5.5 V, 10-SIT, 1.25 MSPS
SERIALADC WITH AUTO-POWER DOWN
SLAS171 - DECEMBER 1997

APPLICATION INFORMATION
The TLV1572 is a 600ns, 1O-bit analog-to-digital converter with the throughput up to 1.25MSPS at 5V and up
to 625KSPS at 3V respectively. To run at its fastest conversion rate, it must be clocked at 20MHz at 5V or 10MHz
at 3V. The TLV1572 can be easily interfaced to microcontrollers, ASICs, DSPs, or shift registers. Its serial
interface is designed to be fully compatible with Serial Peripheral Interface(SPI) and the TMS320 DSP serial
ports. It requires no hardware to interface between the TLV1572 and the microcontrollers (!lCs) with the SPI
serial port or the TMS320 DSPs. However, the speed will be limited by the SCLK rate of the !lC or the DSP.
The TLV1572 interfaces to the DSPs over four lines: CS, SCLK, DO, and FS, and interfaces to !lCS over three
lines: CS, SCLK, and DO. The FS input should be pulled high in IlC mode. The chip is in tristate and powerdown
mode when the CS is high. After the CS falls, the TLV1572 checks the FS input at the CS's falling edge to
determine the operation mode. If the FS is low, the DSP mode is set, else the IlC mode is set.

Interfacing TLV1572 to TMS320 DSPs
The TLV1572 is compatible with Texas Instruments TMS320 DSP serial ports. Figures 3 and 4 show the pin
connections to interface the TLV1572 to the TMS320 DSPs.
TLV1572

TMS320

CS
SCLK
FS

....

44-

....

CS
SCLK

XF
CLKX
CLKR
FSX
FSR
DR

DO

From
System

TLV1572

a) DSP Serial Port Operating in Burst Mode

TMS320

FS

XF
CLKX
CLKR
FSR

DO

DR

4-

b) FS Externally Generated

Figure 3. DSP to TLV1570 Interface
2

3

4

5

6

7

16

~

SCLK
CS
FS

~~~--------------~((
--, I
jj
I ~~_ _ _ _ _ _ _--\

---+' . '-I

DO

mr

')\1----

----J(::~o::KJ~~x:~~)(~C!~

Figure 4. Typical Timing Diagram for DSP Application
In the DSP mode, the FS input should be low when the CS goes low. There is a hold time before FS input can
go high after the CS's falling edge to ensure proper mode latching. With the CS going low, the DO comes out
of tristate but the chip is still in powerdown until the FS (Frame Sync signal from DSP) comes.
The TLV1572 checks for the FS at the falling edges of SCLK. Once the FS is detected high, the sampling of input
is started. As soon as the FS goes low, the chip starts shifting the data out on the DO line. After six null bits,
the AID conversion data becomes available on the SCLK rising edges and is latched by DSP on the falling
edges. Figure 5 shows the DSP mode timing diagram.

~TEXAS

2-404

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1572
2.7 V TO 5.5 V, 1a-BIT, 1.25 MSPS
SERIAL ADC WITH AUTO-POWER DOWN
SLAS171- DECEMBER 1997

APPLICATION INFORMATION
Interfacing TLV1572 to TMS320 DSPs(continued)
The TLV1572 goes into auto-powerdownafter the LSB is shifted out. The next FS pulls it out of auto-powerdown
as shown in Fig. 6. If the FS comes on the 16th bit, next conversion cycle starts from next rising edge of the SCLK
allowing back to back conversions as shown in Figure 7. An FS in the middle of a conversion cycle resets the
chip and starts a new conversion cycle. Therefore variable-bit transfer is supported if the FS appears earlier.
The CS can be pulled high asynchronously to put chip into tristate and powerdown. The CS can also be pulled
low asynchronously to start checking for the FS on the falling edges of clock.
~

11

~

Sample (N)
2

3

4

5

6

7

SCLK

CS
FS

~I
~

16

~

I
I
j+-- Sampling ---¥- Conversion -+j
r,)
I

'II

I

11

Sample (N+1)
2

3

4

5

6

7

16

r-fV\-

',)

I
I
I

'I~-----------------

---l,p

'---=--J'I...-=..."'-.,;J'-...:..J'--=-".....:...ro...:M::;:s;:J,~LiB(N) !,1-r--...;.". . .:...ro....:;..,'\,.;;"",•...:..J'\"";,,,.....
6 Leading Zeros J
1
1

DO

Aulo-Powerdown

14

LSB(N+ 1)

~I

Figure 5. DSP Application Timing (Intermittent Conversion)
~Sample(N)

2

11

3

4

~

5

6

16

7

11

Sample (N+1)
2
3
4
5

6

7

I I
CS
FS

~ I
~
I

16

r-fV\-

SCLK
~sampling

I
I
I

((

JJ

----------------~~

1r--~~'r~J~.~'r~,~~~~r-'r~'~'~~'~~'r~J-~~
MSB(N+1)

Figure 6. DSP Application Timing (Continuous Conversion)
key points
1, When CS goes low, if FS is low, it is DSP mode. FS is sampled twice by CS falling edge and again by
internally delayed CS falling edge. Even if a glitch appears and one latch latches 1 and another latches 0,
chip goes into DSP mode (~C mode requires both latches to latch 1). There is a hold time before FS can
go high again after CS falling edge to ensure proper mode latching as detailed above. With CS going low,
DO is in tristate and the chip is in powerdown until FS rising edge.
2.

1572 checks for FS at every falling edge of SCLK. If FS is detected high, chip goes into reset. When FS
goes low, 1572 waits for DSP to latch the first bit 0.

3.

Sampling occurs from first falling edge of SCLK after FS going low till the rising edge when 6th bit is given
out. There after decisions are taken on rising edges and data is given out on rising edges a bit delayed. DSP
samples on falling edge of SCLK. Data is padded with 6 leading zeros.
'

°

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-405

TLV1572
2.7 V TO 5.5 V, 10-BIT, 1.25 MSPS
SERIAL ADC WITH AUTO-POWERDOWN
SLAS171 - DECEMBER 1997

APPLICATION INFORMATION
key pOints (continued)
4.

Note that chip goes into autopowerdown on the 17th falling edge of SCLK (just after LSB). FS rising edge
pulls it out Of autopowerdown. If FS comes on the 16th bit itself, next conversion cycle starts from next rising
edge allowing back to back conversions. An FS in the middle of a conversion cycle starts a new conversion
cycle. Thus variable-bit transfer is supported if FS appears earlier.

5.

DO goes into tristate on the 17th rising edge and comes out on FS rising edge.

6.

CS can be pulled high asynchronously to put chip into tristate and powerdown. CS may also be pulled low
asynchronously to start checking for FS on falling edges Of clock

For applications where the analog input must be sampled at a precise instant in time, the data conversion can
be initiated by an external conversion start pulse which is completely asynchronous to the SCLK as shown in
Figure 4. When a conversion start pulse is received, the pulse is used as a Frame Sync (FS) signal to initiate
the data conversion and transfer. The corresponding timing diagram is shown in Figure 6.

Interfacing TLV1572to SPI/QSPI compatible microcontrollers(IlCs)
The TLV1572 is compatible with SPI and QSPI serial interface standards (Note: the TLV1572 supports the
following SPI clock options: CLOCK_POLARITY= 0, i.e. SCLK idles low, and CLOCK_PHASE = 1). Figure 8
shows the pin connections to interface the TLV1572 to the SPI/QSPI compatible microcontrollers.

TLV1572

!1C

CS
SCLK

XF
SCLK

FS -

VCC

DR

DO

Figure 7.IlC to TLV1572 Interface
2

3

4

5

6

7

16

rI'--

SCLK

CS~

((
Jj

FS

(/,
,

SDOUT

'IlllI
I
I
I

----~::~o::~~:I)[I>C!)(~~M~S~B~

Figure 8. Typical Timing Diagram for IlC Application
To use the TLV1572 in a non-OSP application, the FS input should be pulled high as shown in Figure 8.
A total of 16 clocks are normally supplied for each conversion. If IlC cannot take in 16 bits at a time, it may take
8 bits with B clocks and next B bits with another 8 clocks. The CS should be kept low throughout the conversion.
The delay between these two 8-clock periods should not be longer than 1DOllS.

~TEXAS

2-406

",

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1572
2.7 V TO 5.5 V, 10·8IT, 1.25 MSPS
SERIAL ADC WITH AUTO·POWERDOWN
SLAS171 - DECEMBER 1997

APPLICATION INFORMATION
Interfacing TLV1572 to SPI/QSPI compatible microcontrollers(/lCs)(continued)
Unlike the DSP mode in which the conversion is initiated by the FS input signal from the DSP, the conversion
is initiated by the incoming SCLK after the CS falls. The sampling of input is started on the first rising edge of
the SCLK after the CS goes down. After six null bits, the AJD conversion data becomes available on the SCLK
rising edges and is latched by l!C on the falling edges. The CS can be pulled high during the conversion before
the LSB is shifted out to use the chip as a lower resolution ADC. Figure 9 shows the l!C mode timing diagram.
The chip goes into autopowerdown after the LSB is shifted out and is brought out of the powerdown by next
clock's rising edge as shown in Figure 10.

j4- Sample (N)
11

2

3

4

5

6

7

2

3

4

5

6

7

16

r,A-

o

P<::=
MSB(N+1)

LSB(N+l)

Figure 9. l!C Application

key points
1.

When CS goes low, if FS is high, it is !lC ({Q}SPI) mode. Thus, FS should be tied to VDD. FS is latched twice,
on CS falling edge and again on internally delayed CS falling edge. Only if both latches latch 1, the !lC mode
is set else DSP mode is set Only polarity = 0 is supported i.e. SCLK idles low. Only clock-phase = 1 is
supported as shown in timing diagrams.

2.

16 clocks have to be supplied for each conversion. If !lC cannot take in 16 bits at a time, it may take a bits
with a clocks and next a bits with another a clocks keeping CS low throughout the conversion. The delay
between these two a-clock periods should not be higher than 100 ns.

3.

Sampling starts on first falling edge of SCLK and ends on the edge when 6th bit 0 is given out. Decisions
are made on the rising edge and data is output on the same edge but a bit delayed to avoid noise.

-!11

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-407

TLV1572
2.7 V TO 5.5 V, 10·BIT, 1.25 MSPS
SERIAL ADC WITH AUTO·POWERDOWN
SLAS171-DECEMBER 1997

4.

Chip goes into autopowerdown on the 16th clock's falling edge and is brought out of it by next 1st(17th)
clock's rising edge.

5.

If (Q)SP wants less than 16-bit transfer, CS must go high after each transfer. The falling edge of CS will reset
the 1572 for the next conversion. Thus one may do a 14-bit transfer to use the chip as an 8-bit AID.

6. CS going high puts chip in tristate and complete powerdown. CS going low merely sets the mode and pulls
DO out of tristate.

~TEXAS

2-408

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2543C, TLV25431
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
I

•
•

12-Bit-Resolution AID Converter
10-lls Conversion Time Over Operating
Temperature Range

•
•
•
•
•
•
•

11 Analog Input Channels
3 Built-In Self-Test Modes
Inherent Sample and Hold Function
Linearity Error ..• ± 1 LSB Max
On-Chip System Clock
End-of-Conversion (EOC) Output
Unipolar or Bipolar Output Operation
(Signed Binary With Respect to Half of the
Applied Referenced Voltage)
Programmable MSB or LSB First
Programmable Power Down
Programmable Output Data Length
CMOS Technology

•
•
•
•

DB, ow, OR N PACKAGE
(TOP VIEW)

AINO
AINl
AIN2
AIN3

4

AIN6

7

AIN8
GND

9

VCC
EOC
1/0 CLOCK
DATA INPUT
DATA OUT
CS
REF+
REFAIN10

1

description
The TLV2543C and TLV2543I are 12-bit, switched-capacitor, successive-approximation, analog-to-digital
converters (ADCs). Each device has three control inputs [chip select (CS), the input-output clock (I/O CLOCK),
and the address input (DATA INPUT)] and is designed for communication with the serial port of a host processor
or peripheral through a serial 3-state output. The device allows high-speed data transfers from the host.
In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel
multiplexer that can select anyone of 11 inputs or anyone of three internal self-test voltages. The
sample-and-hold function is automatic. At the end of conversion, the end-of-conversion (EOC) output goes high
to indicate that conversion is complete. The converter incorporated in the device features differential
high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry
from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating
temperature range.
The TLV2543 is available in the OW, DB, and N packages. The TLV2543C is characterized for operation from
QOC to 7QoC, and the TLV25431 is characterized for operation from -4QoC to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA

SMALL OUTLINE

PLASTIC DIP

owt

OBt

N

O°C to 70°C

TLV2543CDW

TLV2543CDB

TLV2543CN

-40°C to 85°C

TLV25431DW

-

TLV25431N

t Available in tape and reel and ordered as the TLV2543CDWR, TLV2543CDBLE, or TLV2543IDWR.

=~ct8~:,:r:1: 81=r=~':.I~~fa'ee.:!r:

::-==,::

standard warranty. ProducUon processing does not necessarily include

testing of all parameters.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright © 1995, Texas Instruments Incorporated

2-409

TLV2543C, TLV25431
12·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096B - MARCH 1995 - REVISED OCTOBER 1995

functional block diagram

AINO ~
AIN1 ~
AIN2 ..L
AIN3
AIN4 ~
AIN5 ~
AIN6 ~
AIN7
AIN8 9

r---

Sample and
Hold

AIN9
AIN10

-!-1:1
12
~

REF131

12-81t
Analog-to-Digltal
Converter
(switched capacitors)

r--

4-

14-Channel
Analog
Multiplexer

REF+
141

12
~

M

L

Output
Data
Register

Input Address
Register

12-to-1 Data
Selector and
Driver

~

DATA
OUT

I'"

4
3

-

~
DATA
INPUT
1/0 CLOCK

CS

Self-Test
Reference

I

Control Logic
and 1/0
Counters
19

I---

17

~

18

I

15

~TEXAS

2-410

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I

+

EOC

TLV2543C, TLV25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096B - MARCH 1995 - REVISED OCTOBER 1995

Terminal Functions
TERMINAL

110

DESCRIPTION

1-9,
11,12

I

Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should
be less than or equal to 50 n for 4.1-MHz 110 CLOCK operation and capable of slewing the analog input
voltage into a capacitance of 60 pF.

CS

15

I

Chip select. A high-to-Iow transition on CS resets the internal counters and controls and enables DATA OUT,
DATA INPUT, and 110 CLOCK. A low-to-high transition disables DATA INPUT and 110 CLOCK within a setup
time.

DATA INPUT

17

I

Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted. The
serial data is presented with the MSB first and is shifted in on the first four rising edges of 110 CLOCK. After
the four address bits are read into the address register, 110 CLOCK clocks the remaining bits in order.

DATA OUT

16

0

Serial data output. This is the 3·state serial output for~e AID conversion result. DATA OUT is in the
high-impedance state when CS is high and active when CS is low. With a valid CS, DATA OUT is removed
from the high-impedance state and is driven to the logic level corresponding to the MSBILSB value of the
previous conversion result. The next falling edge of 110 CLOCK drives DATA OUT to the logic level
corresponding to the next MSBILSB, and the remaining bits are shifted out in order.

EOC

19

0

End of conversion. EOC goes from a high to a low logic level after the falling edge of the last 110 CLOCK and
remains low until the conversion is complete and data are ready for transfer.

GND

10

110 CLOCK

18

I

Input/output clock. 110 CLOOK receives the serial input and performs the following four functions:
1. It clocks the eight input data bits into the input data register on the first eight rising edges of 110 CLOCK
with the multiplexer address available after the fourth rising edge.
2. On the fourth falling edge of If0 CLOCK, the analog input voltage on the selected multiplexer input
begins charging the capacitor array and continues to do so until the last falling edge of 110
CLOCK.
3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on
the falling edge of 110 CLOCK.
4. It transfers control of the conversion to the internal state controller on the falling edge of the last
110 CLOCK.

REF+

14

I

Reference+. The upper reference voltage value (nominally VCC) is applied to REF+. The maximum input
voltage range is determined by the difference between the voltage applied to this terminal and the voltage
applied to the REF - terminal.

REF-

13

I

Reference-. The lower reference voltage value (nominally ground) is applied to REF-.

VCC

20

NAME

NO.

AINO-AIN10

Ground. This is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage
measurements are with respect to GND.

Positive supply voltage.

detailed description
Initially, with chip select (CS) high, 1/0 CLOCK and DATA INPUT are disabled and DATA OUT is in the
high-impedance state. CS, going low, begins the conversion sequence by enabling 1/0 CLOCK and DATA
INPUT and removes DATA OUT from the high-impedance state.
The input data is an 8-bit data stream consisting of a 4-bit analog channel address (07-04), a 2-bit data length
select (03-02), an output MSB or LSB first bit (01), and a unipolar or bipolar output select bit (DO) that are
applied to DATA INPUT. The 1/0 CLOCK sequence applied to the 110 CLOCK terminal transfers this data to the
input data register.
During this transfer, the 1/0 CLOCK sequence also shifts the previous conversion result from the output data
register to DATA OUT. 1/0 CLOCK receives the input sequence of 8, 12, or 16 clocks long depending on the
data-length selection in the input data register. Sampling of the analog input begins on the fourth falling edge
of the input 1/0 CLOCK sequence and is held after the last falling edge of the 1/0 CLOCK sequence. The last
falling edge of the 1/0 CLOCK sequence also takes EOC low and begins the conversion.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-411

TLV2543C, TLV25431
12-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096B - MARCH 1995 - REVISED OCTOBER 1995

converter operation
The operation of the converter is organized as a succession of two distinct cycles: 1) the I/O cycle, and 2) the
actual conversion cycle. The I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16
clock periods depending on the selected output data length.
1. I/O cycle
During the I/O cycle, two operations take place simultaneously.
a. An 8-bit data stream consisting of address and control information is provided to DATA INPUT. This data
is shifted into the device on the rising edge of the first eight I/O CLOCKs. DATA INPUT is ignored after
the first eight clocks during 12- or 16-clock I/O transfers.
b. The data output with a length of 8, 12, or 16 bits is provided serially on DATA OUT. When CS is held low,
the first output data bit occurs on the rising edge of EOC. When. CS is negated between conversions, the
first output data bit occurs on the falling edge of CS. This data is the result of the previous conversion
period, and after the first output data bit each succeeding bit is clocked out on the falling edge of each
succeeding I/O CLOCK.
2.

Conversion cycle
The conversion cycle is transparent to the user, and it is controlled by an internal clock synchronized to the
I/O CLOCK. During the conversion period, the device pei'forms a successive-approximation conversion on
the analog input voltage. The EOC output goes low at the start of the conversion cycle and goes high when
conversion is complete and the output data register is latched. A conversion cycle is started only after the I/O
cycle is completed, which minimizes the influence of external digital noise on the accuracy of the
conversion.

power up and initialization
After power up, CS must be taken from high to low to begin an I/O cycle. EOC is initially high, and the input data
register is set to all zeros. The contents of the output data register are random, and the first conversion result
should be ignored. To initialize during operation, CS is taken high and returned low to begin the next I/O cycle.
The first conversion after the device has returned from the power-down state may not read accurately due to
internal device settling.

operational terminology
Previous (N-1) conversion cycle

The conversion cycle prior to the current 1/0 cycle.

Current (N) 1/0 cycle

The entire 1/0 CLOCK sequence that transfers address and control data into the data register and clocks
the digital result from the previous conversion cycle from DATA OUT. The last falling edge of the clock in
the 1/0 CLOCK sequence signifies the end of the current 1/0 cycle.

Current (N) conversion cycle

Immediately after the current 1/0 cycle, the current conversion cycle starts. When the current conversion
cycle is complete, the current conversion result is loaded into the output register.

Current (N) conversion result

The result of the current conversion cycle that is serially shifted out during the next 1/0 cycle.

Next (N + 1) 1/0 cycle

The 1/0 cycle after the current conversion cycle.

Example: In the 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during
the next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even
when this corrupts the output data from the previous conversion. The current conversion begins
immediately after the twelfth falling edge of the current I/O cycle.

data input
The data input is internally connected to an 8-bit serial-input address and control register. The register defines
the operation of the converter and the output data length. The host provides the data word with the MSB first.
Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 1 for the data register
format).

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WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096B - MARCH 1995 - REVISED OCTOBER 1995

data input (continued)
Table 1. Input-Register Format
INPUT DATA BYTE
ADDRESS BITS

FUNCTION SELECT
07
(MSB)
Select input channel
AI NO
AINI
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
Select test voltage
(Vrel+ -Vrel-l/2
VrelVrel+
Software power down

0
0

a
a
0

a
0

a

06

04

L1

LO

LSBF

03

02

01

BIP

00
(LSB)

0

a
a
a
1
1
1
1

1

a
a
a

1

a

1
1
1

1

1
1

05

0

a

0
1

1
1

a

1

a

a
a
1

a
a
1
1

1

a
1
1

a
1

a
1

a

1

a
a

1

1

0

1

Output data length
8 bits
12 bits
16 bits

a

Output data format
MSBlirst
LSBlirst

X

1
0

1

1

a
1

Unipolar (binary)

a

Bipolar (BIP, 2s complement)

1

data input address bits
The four MSBs (07 - 04) of the data register address one of the 11 input channels, a reference-test voltage,
or the power-down mode. The address bits affect the current conversion, which is the conversion that
immediately follows the current I/O cycle. The reference voltage is nominally equal to Vret+ - Vret-.

data output length
The next two bits (03 and 02) of the data register select the output data length. The data-length selection is
valid for the current 1/0 cycle (the cycle in which the data is read). The data-length selection, which is valid for
the current 1/0 cycle, allows device start-up without losing 1/0 synchronization. A data length of 8, 12, or 16 bits
can be selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.
With 03 and 02 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current
conversion is output as a 12-bit serial-data stream during the next 1/0 cycle. The current 1/0 cycle must be
exactly 12 bits long for proper synchronization, even when this means corrupting the output data from a previous
conversion. The current conversion is started immediately after the twelfth falling edge of the current 1/0 cycle.
With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication
with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit
serial-data stream during the next I/O cycle with the four LSBs always set to 0 (pad bits). The current I/O cycle
must be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from
the previous conversion. The current conversion is started immediately after the sixteenth falling edge of the
current 1/0 cycle.

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12·81T ANALOG·TO·DIGITAL CONVERTERS
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SLAS096B - MARCH 1995 - REVISED OCTOBER 1995

data output length (continued)

With bits D3 and D2 s~t to 01 , the 8-bit data-length mode is selected, which allows fast communication with 8-bit
serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial-data stream
during the next I/O cycle. The current I/O cycle must be exactly 8 bits long to maintain synchronization, even
when this. means corrupting the output data from the previous conversion. The four LSBs of the conversion
result are truncated and discarded. The current conversion is immediately started after the eighth falling edge
of the current I/O cycle.
Since D3 and D2 take effect on the current I/O cycle when the data length is programmed, there can be a conflict
with the previous cycle when the data-word length is changed from one cycle to the next. This may occur when
the data format is selected to be least significant bit first, since at the time the data length change becomes
effective (six rising edges of I/O CLOCK), the previous conversion result has already started shifting out.
In actual operation, when different data lengths are required within an application and the data length is changed
between two conversions, no more than one conversion result can be corrupted and only when it is shifted out
in LSB first format.
sampling period

During the sampling period, one of the analog inputs is internally connected to the capacitor array of the
converter to store the analog input signal. The converter starts sampling the selected input immediately after
the four address bits have been clocked into the input data register. Sampling starts on the fourth falling edge
of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge
of the I/O CLOCK depending on the data-length selection. After the EOC delay time from the last I/O CLOCK
falling edge, the EOC output goes low indicating that the sampling period is over and the conversion period has
begun. After EOC goes low, the analog input can be changed without affecting the conversion result. Since the
delay from the falling edge of the last I/O CLOCK to EOC low is fixed, time-varying analog input signals can be
digitized at a fixed rate without introducing systematic harmonic distortion or noise due to timing uncertainty.
After the 8-bit data stream has been clocked in, DATA INPUT should be held at a fixed digital level until EOC
goes high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the
influence of external digital noise.
data register, LSB first

D1 in the input data register (lSB first) controls the direction of the output binary data transfer. When D1 is set
to 0, the conversion result shifts out MSBfirst. When set to 1, the data shifts out lSa first. Selection of MSB
first or lSB first always affects the next I/O cycle and not the current I/O cycle. When changing from one data
direction to another, the current I/O cycle is never disrupted.
data register, bipolar format

DO in the input data register controls the binary data format used to represent the conversion result. When DO
is set to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion
result of an input voltage equal to Vref- is a code of all zeros (000 ... 0), the conversion result of an input voltage
equal to Vref+ is a code of all ones (111 ... 1), and the conversion result of (Vref + + Vref _) /2 is a code of a one
followed by zeros (100 ... 0).
When DO is set to 1, the conversion result is represented as bipolar data (signed binary). Nominally, conversion
of an input voltage equal to Vref- is a code of a 1 followed by zeros (100 ... 0), conversion of an input voltage
equal to Vref+ is a code of a 0 followed by all ones (011 ... 1), and the conversion of (Vref+ + Vref-) 12 is a code
of all zeros (000 ... 0). The MSB is interpreted as the sign bit. The bipolar data format is related to the unipolar
format in that the MSBs are always each other's complement.
Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next.l/O cycle. When changing between unipolar and bipolar formats, the data output during the
current I/O cycle is not affected.

~TEXAS

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12·81T ANALOG-TO· DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096B - MARCH 1995 - REVISED OCTOBER 1995

EOC output

The EOC signal indicates the beginning and the end of conversion. In the reset state, EOC is always high. During
the sampling period (beginning after the fourth falling edge of the 1/0 CLOCK sequence), EOC remains high
until the internal sampling switch of the converter is safely opened. The opening of the sampling switch occurs
after the eighth, twelfth, or sixteenth 1/0 CLOCK falling edge, depending on the data-length selection in the input
data register. After the EOC signal goes low, the analog input signal can be changed without affecting the
conversion result.
The EOC signal goes high again after the conversion completes and the conversion result is latched into the
output data register. The rising edge of EOG returns the converter to a reset state and a new 1/0 cycle begins.
On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When
CS is negated between conversions, the first bit of the current conversion result occurs at DATA OUT on the
falling edge of CS.
data format and pad bits

03 and D2 of the input data register determine the number of significant bits in the digital output that represent
the conversion result. The LSB-first bit determines the direction of the data transfer while the BIP bit determines
the arithmetic conversion. The numerical data is always justified toward the MSB in any output format.
The internal conversion result is always 12 bits long. When an a-bit data transfer is selected, the four LSBs of
the internal result are discarded to provide a faster one-byte transfer. When a 12-bit transfer is used, all bits are
transferred. When a 16-bit transfer is used, four LSB pad bits are always appended to the internal conversion
result. In the LSB-first mode, four leading zeros are output. In the MSB-first mode, the last four bits output are
zeros.
When CS is held low continuously, the first data bit of the just completed conversion occurs on DATA OUT on
the rising edge of EOC. When a new conversion is started after the last falling edge of 1/0 CLOCK, EOC goes
low and the serial output is forced to a logic zero until EOC goes high again.
When CS is negated between conversions, the first data bit occurs on DATA OUT on the falling edge of CS.
On each subsequent falling edge of 1/0 CLOCK after the first data bit appears, the data is changed to the next
bit in the serial conversion result until the required number of bits has been output.
chip-select input (CS)

The chip-select input (CS) enables and disables the device. During normal operation, CS should be low.
Although the use of CS is not necessary to synchronize a data transfer, it can be brought high between
conversions to coordinate the data transfer of several devices sharing the same bus.
When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing
its output data line to other devices that may share it. After an internally generated debounce time, the 1/0
CLOCK is inhibited, thus preventing any' further change in the internal state.
When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce
time before the reset operation takes effect. After CS is debounced low, 1/0 CLOCK must remain inactive (low)
for a minimum time before a new 1/0 cycle can start.
CS can be used to interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low
long enough before the end of the current conversion cycle, the previous conversion result is saved in the
internal output buffer and then shifted out during the next 1/0 cycle.

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12-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096B - MARCH 1995 - REVISED OCTOBER 1995

power-down features
When a binary address of 1110 is clocked into the input data register during the first four 1/0 CLOCK cycles,
the power-down mode is selected. Power down is activated on the falling edge of the fourth I/O CLOCK pulse.
During power down, all internal Circuitry is put in a low-current standby mode. No conversions are performed,
and the internal output buffer keeps the previous conversion cycle data results, provided that all digital inputs
are held above Vce - 0.3 V or below 0.3 V. The I/O logic remains active so the current I/O cycle must be
completed even when the power-down mode is selected. Upon power-on reset and before the first I/O cycle,
the converter normally begins in the power-down mode. The device remains in the power-down mode until a
valid (other than 1110) input address clocks .in. Upon completion of that I/O cycle, a normal conversion is
performed with the results being shifted out during the next 1/0 cycle.
analog input, test, and power-down mode
The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer
according to the input addresses shown in Tables 2, 3, and 4. The input multiplexer. isa break-before-make type
to reduce input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on
the failing edge of the fourth 1/0 CLOCK and continues for the remaining 1/0 CLOCK pulses. The sample is held
on the falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the mUltiplexer,
sampled, and converted in the same manner as the external analog inputs. The first conversion after the device
has returned from the power-down state may not read accurately due to internal device settling.
Table 2. Analog-Channel-Select Address
ANALOG INPUT
SELECTED

VALUE SHIFTED INTO
DATA INPUT
BINARY

HEX

AI NO

0000

0

AIN1

0001

1

AIN2

0010

2

AIN3

0011

3

AIN4

0100

4

AIN5

0101

5

AIN6

0110

6

AIN7

0111

7

AIN8

1000

8

AIN9

1001

9

AIN10

1010

A

Table 3. Test-Mode-Select Address
INTERNAL
SELF-TEST'
VOLTAGE
SELECTEDt

VALUE SHIFTED INTO
DATA INPUT

UNIPOLAR OUTPUT
RESULT (HEX)*

BINARY

HEX

Vref + - Vref2

1011

B

Vref-

1100

C

000

Vref+

1101

D

3FF

200

t Vref+ is the voltage applied to REF+, and Vref- is the voltage applied to REF-.

'* The output results shown are the ideal values and may vary with the reference stability
and with internal offsets,

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12-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096B - MARCH 1995 - REVISED OCTOBER 1995

analog input, test, and power-down mode (continued)
Table 4. Power-Down-Select Address
VALUE SHIFTED INTO
INPUT COMMAND

DATA INPUT

BINARY

Power down

1110

I
I

RESULT

HEX

E

ICC ~ 25J.LA

converter and analog input

The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the Se switch and all ST switches simultaneously.
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all ST and Se switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF-)
voltage. In the switching sequence, 12 capacitors are examined separately until all 12 bits are identified and
the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks
at the first capacitor (weight = 4096). Node 4096 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF-. When the voltage at the
summing node is greater than the trip point of t~e threshold detector (approximately one-half Vee), a bit a is
placed in the output register and the 4096-weight capacitor is switched to REF-. When the voltage at the
summing node is less than the trip point of the threshold detector, a bit 1 is placed in the register and the
4096-weight capacitor remains connected to REF + through the remainder of the successive-approximation
process. The process is repeated for the 2048-weight capacitor, the 1024-weight capacitor, and so forth down
the line until all bits are determined. With each step of the successive-approximation process, the initial charge
is redistributed among the capacitors. The conversion process relies on charge redistribution to determine the
bits from MSB to LSB.

Sc
Threshold
Detector

To Output
Latches

Figure 1. Simplified Model of the Successive-Approximation System

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TLV2543C, TLV25431
12-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096B - MARCH 1995 - REVISED OCTOBER 1995

reference voltage inputs
There are two reference voltage inputs on the device, REF+ and REF-. The voltage values on these terminals
establish the upper and lower limits of the analog input to produce a full-scale and zero-scale reading
respectively. These voltages and the analQg input should not exceed the positive supply or be lower than ground
consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal
is equal to or higher than REF+ terminal voltage and at zero when the inp4t signal is equal to or lower than REFterminal voltage.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................. -0.5 V to 6.5 V
Input voltage range, VI (any input) .................................... : ....... -0.3 V to Vee + 0.3 V
Output voltage range, Vo ................................................... -0.3 V to Vee + 0.3 V
Positive reference voltage, Vref+ ...................................................... Vee + 0.1 V
Negative reference voltage, Vref- .......................................................... -0.1 V
Peak input current, II (any input) .......................................................... ±20 mA
Peak total input current (all inputs) ........................................................ ±30 mA
Operating free-air temperature range, TA: TLV2543e ................................... DoC to 70°C
TLV25431 .................................. -40°C to 85°C
Storage temperature range, Tstg ................................................ ; .. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds ............................ 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods· may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminal with REF- and GND wired together (unless otherwise noted).

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12-81T ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS0968 - MARCH 1995 - REVISED OCTOBER 1995

recommended operating conditions
Supply voltage, VCC

MIN

NOM

MAX

3

3.3

3.6

Positive reference voltage, Vref+ (see Note 2)

Analog input voltage (see Note 2)

2.5

VCC

0

High-level control input voltage, VIH

V

0

Differential reference voltage, Vref+ - Vref- (see Note 2)

. I VCC = 3 V to 3.6 V

Low-level control input voltage, VIL

2.1

0

Setup time, address bits at DATA INPUT before I/O CLOCKi, tsu(A) (see Figure 5)

VCC+O.l
VCC

V
V
V

I VCC = 3 V to 3.6 V

Clock frequency at I/O CLOCK

V
V

VCC

Negative reference voltage, Vref- (see Note 2)

UNIT

3

0.6

V

4.1

MHz

100

ns

Hold time, address bits at DATA INPUT atter I/O CLOCKi, thlA) (see Figure 5)

0

ns

Hold time, CS low atter last I/O CLOCK.]., th(CS) (see Figure 6)

0

ns

1.425

/-1S

Pulse duration, I/O CLOCK high, twH(I/O)

190

ns

Pulse duration, I/O CLOCK low, twlll/O)

190

Setup time, CS low before clocking in first address bit, tsulCS) (see Note 3 and Figure 6)

Transition time, I/O CLOCK, tt(llO) (see Note 4 and Figure 7)
Transition time, DATA INPUT and CS, tIlCS)
Operating free-air temperature, TA
NOTES:

. ITLV2543C

I TLV25431

ns
1

/-1s

10

/-1s

0

70

-40

85

°C

2. Analog Input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than
the voltage applied to REF- convert as all zeros (000000000000).
3. To minimize errors caused by noise at the CS input, the internal circuitry waits for a setup time atter CS.]. before responding to control
input signals. No attempt should be made to clock in an address until the minimum CS setup time elapses.
4. This is the time required for the clock input signal to fall from VIHmin to VIL max or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the devices function with input clock transition time as slow as 1 ~s for remote data acquisition applications
where the sensor and the AID converter are placed several feet away from the controlling microprocessor.

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12-BIT ANALOG-TO-DIGITAL CONVERTERS
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SLAS096B - MARCH 1995 - REVISED OCTOBER 1995

electrical characteristics over recommended operating free-air temperature range,
Vee Vref+ 3 V to 3.6 V (unless otherwise noted)

=

=

PARAMETER

IOH =-0.2 mA

Vee = 3 V to 3.6 V.

IOH =-20 IJA

Vee=3V.

IOL= O.B mA

Vee = 3 V to 3.6 V.

IOL = 20

MIN

TYpt

MAX

2.4

UNIT

VOH

High-level output voltage

VOL

Low-level output voltage
Off-state (hig~-impedance-state)
output current

Vo=Vee.

es at Vee

1

2.5

IOZ

VO=O,

es at Vee

1

-2.5

IIH

High-level input current

VI = Vee

1

2.5

llA

IlL

Low-level input current

VI = 0

1

-2.5

llA

ICC

Operating supply current

eSatO V

1

2.5

mA

lee(PD)

Power-down current

For all digital inputs.
0::; VI ::; 0.3 V or VI ~ Vee - 0.3 V

4

25

IJA

Ilkg

Selected channel leakage
current

Selected channel at 0 V. Unselected channel at Vee

Maximum static analog
reference current into REF +

Vref+ = Vee.

ei

t

TEST CONDITIONS

Vee = 3 V.

Input
capacitance

IJA

0.4
0.1

1

Selected channel at Vee. Unselected channel at 0 V

-1
1

2.5

I Analog inputs

30

60

I Control inputs

5

15

Vref-= GND

All typical values are at Vee = 5 V, TA = 25°C.

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TLV2543C, TLV25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096B - MARCH 1995 - REVISED OCTOBER 1995

operating characteristics over recommended operating free·air temperature range,
Vee Vref+ 3 V to 3.6 V, I/O CLOCK frequency 4.1 MHz, (unless otherwise noted)

=

=

=

PARAMETER

TEST CONDITIONS

MIN

TYPt

MAX

UNIT

EL

Linearity error (see Note 6)

See Figure 2

±1

LSB

ED

Differential linearity error

See Figure 2

±1

LSB

EO

Offset error (see Note 7)

See Note 2 and
Figure 2

±1.5

LSB

EG

Gain error (see Note 7)

See Note 2 and
Figure 2

±1

LSB

ET

Total unadjusted error (see Note 8)

±1.75

LSB

DATA INPUT = 1011
Self-test output code (see Table 3 and Note 9)

Conversion time

2048

2058

0

10

4075

4095

DATA INPUT = 1100
DATA INPUT = 1101

tconv

2038

See Figures 10-15

8

10
10 + total
1/0 CLOCK
periods +

~s

Total cycle time (access, sample, and conversion)

See Figures 10-15
and Note 10

tacq

Channel acquisition time (sample)

See Figures 10-15
and Note 10

tv

Valid time, DATA OUT remains valid after 1/0 CLOCK.!.

See Figure 7

td(l/O-DATA)

Delay time, 1/0 CLOCK.!. to DATA OUT valid

See Figure 7

idOlO-EOC)

Delay time, last 1/0 CLOCK.!. to EOC.!.

See Figure 8

id(EOC-DATA)

Delay lime, EOCt to DATA OUT (MSB/LSB)

See Figure 9

200

ns

tPZH, tpZL

Enable time, CS.!. to DATA OUT (MSB/LSB driven)

See Figure 4

0.7

1.3

~s

tPHZ, tpLZ

Disable time, cst to DATA OUT (high impedance)

See Figure 4

70

150

ns

tr{EOC)

Rise time, EOC

See Figure 9

15

50

ns

tf(EOC)

Fall time, EOC

See Figure 8

15

50

ns

tr{bus)

Rise time, data bus

See Figure 7

15

50

ns

tf(bus)

Fall time, data bus

See Figure 7

15

50

ns

id{I/O-CS)

Delay time, laslllO CLOCK.!. 10 cs.!. to abort conversion
(see Note 11)

5

~s

tc

~s

td(I/O-EOC)
4

12

10

1/0
CLOCK
periods

ns

1.5

250

ns

2.2

~s

t All typical values are at TA = 25°C.
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that
applied to REF- convert as all zeros (OOOOOOOOOOOO).
6. Linearity error is the maximum deviation from the best straight line through the ND transfer characteristics.
7. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified
gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the
nominal midstep value at the offset point.
8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
9. Both the input address and the output codes are expressed in positive logic.
10. 1/0 CLOCK period 1/{I/0 CLOCK frequency) (see Figure 7).
.
11. Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at,;; 5 ~s
of the tenth I/O CLOCK falling edge to ensure that a conversion is aborted. Between 511S and 10 ~s, the result is uncertain as to
whether the conversion is aborted or the conversion results are valid.

=

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-421

TLV2543C, TLV25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096B - MARCH 1995 - REVISED OCTOBER 1995

PARAMETER MEASUREMENT INFORMATION
15 V

C1
10 ItF

C3
470pF
TLV2543

10n
>-II>---J\I\I~~-I

AINO-AIN10

VI------1
C3
470 pF

-15V
LOCATION

PART NUMBER

DESCRIPTION

-

U1
C1

OP27
10-ItF 35-V tantalum capacitor

C2

O.1-ItF ceramic NPO SMD capacitor

AVX 12105C104KA105 or equivalent

C3

470-pF porcelain high-Q SMD capacitor

Johanson 201S420471JG4L or equivalent

-

Figure 2, Analog Input Buffer to Analog Inputs AINO-AIN10

Output
Under Test

Vep= 2 V

NOTE A: Equivalent load circuit of the Teradyne A580 tester for timing
parameter measurerr.9nl.

Figure 3. Timing Load Circuits

!.-

Dala
Valid

I

CS

~~
______~2VT:
\ - O.SV
I!

tpZH; tpZL ---j+----+\II

I

DATA
OUT

DATA INPUT

!...

.J
~ IPHZ,IPLZ

T

"\ 90%

0.4V\

10%

2.4 V

~

Figure 4. DATA OUT to Hi-Z Voltage Waveforms

~ I- ~.~

I

r--

--A~-"--I
I
I
tsu(A)

14

V

.! r

:\

Ih(A)

1/0 CLOCK

O.SV}

Figure 5. DATA INPUT and I/O CLOCK
Voltage Waveforms

~TEXAS

2-422

~I

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLV2543C, TLV25431
12·BIT ANALOG· TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096B - MARCH 1995 - REVISED OCTOBER 1995

PARAMETER MEASUREMENT INFORMATION
CS

o.sv

\-

JI

ISU(CS)~

I/OCLOCK

2;;r--

rr

1

~rj

~~~~

/

1
1

'i
1

o.s:1

Ih(CS)

Figure 6. CS and 1/0 CLOCK Voltage Waveformst
t To ensure full conversion accuracy, it is recommended that no input signal change occurs while
a conversion is ongoing.
11(110)

-1

--41 ~
1

110 CLOCK

2

~

11(110)

1

vii
o.sv

o.SV

o.sv

~/O CLOCK period~:
i4

Id(II()"DATA)

.1

Iv~1
DATA OUT

2.4 V {

~ 2.4 V

0.4V AO.4V
~----~I ~I--------------~

r

Ir(bus),lf(bus)

Figure 7. 1/0 CLOCK and DATA OUT Voltage Waveforms

110 CLOCK
/
--./

:asl \
Clock

1d(IIO-EOC)

"".
__O_.s_V_ _ _ _ _ __

-"'~~_ _+1.11
I'

N'
I

EOC

2.4V

1
1

0.4 V

~.;.....--

If(EOC) - . : :..........

Figure 8. 1/0 CLOCK and EOC Voltage Waveforms
--.:
EOC

:

~

J.

~!

Ir(EOC)

2.4 V

i~

1

.~I

DATA OUT _ _ _ _ _ _ _ _---(.

Id(EOC-DATA)
2.4 V

.

0.4 V
:.- Valid MSB

--+

Figure 9. EOC and DATA OUT Voltage Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-423

TLV2543C, TLV25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096B - MARCH 1995 - REVISED OCTOBER 1995

PARAMETER MEASUREMENT INFORMATION

(seeNoteC~II--_ _ _ _ _ _~_ _ _ _ _ _ _ _ _-I'/'r)_ _ _~I

CLO~~_~:

I1L.i___

~ W/$/)~

.....

.:

I

~
Hi-.zState

DATA
OUT

A1

AO

I

-------------LS-B~.I

B7

B6

B5

MSB
EOC

J

B4

B3

B2

B1

BO

~~

Initialize

I

-~~
--'l~

----I

1
1

LSB

~
1

:

DATA
INPUT

~

I
I

1
\\1----+0

.

IIr;::

C7

n,l

"

Shift in New Multiplexer Address,
:
tconv --+I
Simultaneously Shift Out Previous - - - - - - - I••~I..t-----------.J.1
Conversion Value
AID Conversion
Interval

Initialize

Figure 10. Timing for 12-Clock Transfer Using CS With MSB First

CSI
(see Note A)

110

.11----------------------'1JJ
({

I

'))---

rFl--fl

1

CLOCK -t---!

.1
1
1

DATA
OUT

rj

Low Level

1

I

LSB· 1

1
1

1

DATA
INPUT
B7

B6

B5

B4

B3

B2

B1

BO

LSB

1
1
1

1
1

EOC

1+--------

Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value

Initialize

~

~

___ ..l-1
MSB

~

)---

tconv
AID Conversion
Interval

Initialize

Figure 11. Timing for 12-Clock Transfer Not Using CS With MSB First
NOTE A: To minimize errors caused by noise at cs, the internal circuitry waits for a setup time after cst before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.

~TEXAS

2-424

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2543C, TLV25431
12·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096B - MARCH 1995 - REVISED OCTOBER 1995

PARAMETER MEASUREMENT INFORMATION
CS
(see Note A)

ll------------'

1/0 CLOCK

I
I

_---H-i.-Z... ~

DATA OUT

I
I

I

I+-M-S-B- - - - Previous Conversion Data ----L-S-B~~

///---'l~

I
DATA INPUT
B7

B6

MSB
EOC

B5

B4

B3

B2

Bl

BO

LSB

I
I

U.L __ ~~
I C7
I

II

1'-

~------------------------------~I

J7~

Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value

I

n~(~I-----

j4--- tconv

..

-+I

------1~or-I-------~.1

AID Conversion
Interval

Initialize

Initialize

Figure 12. Timing for 8·Clock Transfer Using CS With MSB First

CS
(see Note A)

l

,.----------------------------~(J'r___

,r7'l

1/0 CLOCK

~-------""JrJ

~

Low Level

'--_ _ _ _ _J'!I"I ;:.....A

DATA OUT

I

--------~

~

DATA INPUT

I
I
EOC

L.

I

I

---'b'r---

Jr.'-------------ni,...1____

II
Shift in New Multiplexer Address,
I j4---- tconv
1....- - - - Simultaneously Shift Out Previous ------..1<111
..- - - - - - - - - + /

:1

Conversion Value

Initialize

AID Conversion
Interval

Initialize

Figure 13. Timing for 8-Clock Transfer Not Using CS With MSB.First
NOTE A: To minimize errors caused by noise at cs, the internal circuitry waits for a setup time after cst before responding to control
input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-425

TLV2543C, TLV25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS0968 - MARCH 1995 - REVISED OCT08ER 1995

PARAMETER MEASUREMENT INFORMATION

')---,

;

.
(see
NoteCS--,
A)
L..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _"""":"'_ _ _----\\<\-;- - - -......

L-

I
I

1/0

_+---!

CLOCK

DATA
OUT

DATA
INPUT
87

86

85

84

MSB

EOC

83

82

81

80

LSB

J~
.

«

;;

Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value

,....._____....1'/)

---------t.;+------~

Initialize

Initialize

Figure 14. Timing for 16-Clock Transfer Using CS With MSB First

csl

------------""/"r----

(see Note A) !I----------~----------I'/\-;
1/0

CLOCK

I
I
I

~

DATA
OUT

Low Level

------------+~~I
LSB

I

:

DATA
INPUT
87

MSB

86

85

84

83

82

81

80

LSB

--rI
I

EO:J~I.---------~\i-\-~:I .
Initialize

~~
I

~~
~
I
I

r

l

Shift in New Multiplexer Address,
I ~ tconv ------.I
Simultaneously Shift Out Previous - - - - - -..
~·i'lI..I--------~~1
Conversion Value
AID Conversion
Interval

Figure 15. Timing for 16-Clock Transfer Not Using CS With MSB First
NOTE A: To minimize errors caused by neise at cs, the internal circuitry waits for a setup time after cst before responding to control input Signals.
Therefore, no attempf should be made to clock in an address until the minimum CS setup time has elapsed.

~TEXAS

2-426

INSTRUMENTS
£,OST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2543C, TLV25431
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096B - MARCH 1995 - REVISED OCTOBER 1995

APPLICATION INFORMATION
111111111111

I

I
VFS -

See Notes A and B
111111111110

~VI
):; II I

111111111101

GI

•••

A~

~

'S

~ 100000000000

o

Cl

is

VZT

/

011111111111

•••

f- VZS

000000000000

~~

/

1/
/1 Vk
/

000000000010
000000000001

= VZS + 1/2 LSB

/'

4093

g0.0008

VFT = VFS - 1/2 LSB

~Y

c..

2048 .!!

Ii

V

U)

2047

I
I

••
•

Ii

2

I
I

V

0.0016

2049

I
I

/'

:A. . . . /

••
•

I!

,/'

~

o

/'

•••

1.6376

1.6384

•••

1.6392

C!

o

4094

VFSnom

,/'

8100000000001
~

~ ~l

4095

I

3.2752

l!! 3.2760

o
3.2768

"!

'"

VI- Analog Input Voltage - V

NOTES: A. This curve is based on the assumption that Vref+ and Vref- have been adjusted so that the voltage'at the transition from digital 0
to 1 (VZT) is 0.0004 V and the transition to full scale (VFT) is 3.2756 V. 1 LSB = 0.8 mY.
B. The fUll-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is
the step whose nominal midstep value equals zero.

Figure 16. Ideal Conversion Characteristics
TLV2543
1
2
3
4
5
Analog
Inputs

6
7
8
9
11
12

AINO
AIN1
AIN2

15
CS

18
I/O CLOCK
17
DATA INPUT
Processor

AIN3
AIN4

DATA OUT

AIN5

EOC

Control
Circuit

16
19

AIN6
AIN7
AIN8

REF+

AIN9
AIN10

REF-

14
r--

3-V DC Regulated

~

GND

110
To Source
Ground

I

1.
Figure 17. Serial Interface

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-427

TLV2543C, TLV25431
12·81T ANALOG·TO·DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096B - MARCH 1995 - REVISED OCTOBER 1995

APPLICATIONS INFORMATION

simplified analog input analysis
Using the equivalent circllit in Figure 18, the time required to charge the analog input capacitance from a to V S
within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by

(1 )
where
Rt = Rs + ri
The final voltage to 1/2 LSB is given by
Vc (1/2 LSB)

= Vs -

(2)

(VS/8192)

Equating equation 1 to equation 2 and solving for time te gives
(3)
and
te (112 LSB) = Rt x Cj x In(8192)

(4)

Therefore, with the values given the time for the analog input signal to settle is
te (1/2 LSB)

= (Rs + 1 kf.l) x 60 pF x In(8192)

(5)

This time must be less than the converter sample time shown in the timing diagrams.
Driving Sourcet ~

Rs

I
I
I
I

VI

• TLV2543
rJ

VS~VC
I 1kOMAX
I
I
I

I

C.

I

50pFMAX

VI = Input Voltage at AIN
VS= External Driving Source Voltage
Rs = Source Resistance
ri '" Input Resistance
Ci Input Capacitance

=

t Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.

Figure 18. Equivalent Input Circuit Including the Driving Source

-!!1

2-428

TEXAS
.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5510
3·V 8·BIT HIGH·SPEED ANALOG· TO·DIGITAL CONVERTER
•
•

•

•

•
•
•

NSPACKAGEt
(TOP VIEW)

8-Bit Resolution
Linearity Error
±0.75 LSB Max (25°C)
±1 LSB Max (-20°C to 75°C)
Differential Linearity Error
± 0.5 LSB (25°C)
±0.75 LSB Max (-20°C to 75°C)
Maximum Conversion Rate
10 Mega-Samples per Second
(MSPS) Min
3-V Single-Supply Operation
Low Power Consumption. .. 40 mW Typ
Low Voltage Replacement for CXD1175

OE
OGNO
01(lSB)
02
03
04
05
06

VDDA

REFT
REFTS

07

Applications
•
•
•
•

OGNO
REFB
REFBS
AGNO
AGNO
ANALOG IN

08(MSB)

VDOA

VDDO

VDDA

elK

VDDO

t Available in tape and reel only and
ordered as the TLV551 OINSLE.

Communications
Digitallmaging
Video Conferencing
High-Speed Data Conversion

AVAILABLE OPTIONS

TLV5510lNSLE

-20°C to 75°C

description

3:
w

NSPACKAGE
(TAPE AND REEL ONLY)

TA

The TLV551 0 is a CMOS 8-bit resolution semiflash analog-to-digital converter (ADC) with a 2.7-V to 3.6-V single
power supply and an internal reference voltage source. It converts a wide band analog signal (such as a video
signal) to a digital signal at a sampling rate of dc to 10 MHz.

I-

functional block diagram

o

::)

Resistor
Reference
Divider

c

OE

oa:

REFB

REFT

200
0
NOM

REFBS

Q.

Lower Sampling
Comparators
(4 Bit)

600
NOM

01(LSB)
Lower Data
Latch

AGNO

eLK

03

05

VOOA

REFTS
ANALOG IN

02
04

Lower Sampling
Comparators
(4 Bit)

AGNO

>
w
a:
Q.

400
NOM
Upper Sampling
Comparators
(4 Bit)

Upper Data
Latch

06
07
08(MSB)

Clock
Generator

PRODUCT PREVIEW infonnalion concerns products in the formative or

deslSl" phase of development. Characteristic data and other
:1:~~C:r~~:t~~~~~~~~~ :i:~~~~w:erves the right to

-!11

Copyright © 1997, Texas Instruments Incorporated

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-429

TlV5510
3-V8-BIT HIGH-SPEED ANALOG-TO-DiGITAL CONVERTER'
SLAS124- DECEMBER 1997

schematics of inputs and outputs
EQUIVALENT OF ANALOG INPUT

EQUIVALENT OF EACH DIGITAL INPUT

VDDA

EQUIVALENT OF EACH DIGITAL OUTPUT

VDDD

VDDD

01-08

OE,CLK

ANALOG IN

AGND

DGND

Terminal Functions
TERMINAL
NAME
AGNO

"tJ

:u

ANALOG IN

oc

CLK

o

OE

c:
-I
"tJ

:u
m
<
m

-

:e

NO.

I/O

20,21

DESCRIPTION
Analog ground

19

I

Analog input

12

I

Clock in

OGNO

2,24

01-08

3-10
1

Digital ground

0

Digital data out. 01 :LSB, 08:MSB

I

Output enable. When OE

VODA

14,15,18

VOOD

11,13

REFB

I

REFBS

23
22 .

REFT

17

I

REFTS

16

=L, data is enabled. When OE =H, D1 -

08 is high impedance.

Analog supply voltage
Digital supply voltage
Reference voltage in (bottom)
Reference voltage (bottom). When using the internal voltage divider to generate a nominal 2-V reference,
this terminal is shorted to the REFB terminal and the REFTS terminal is shorted to the REFT terminal (see
Figure 3).
Reference voltage in (top)
Reference voltage (top). When using the internal voltage divider to generate a nominal 2-V reference, this
terminal is shorted to the REFT terminal and the REFBS terminal is shorted to the REFB terminal (see
Figure 3).

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, VOOA, Vooo ................................................................. 7 V
Reference voltage input range, Vref(T), Vref(B), Vref(BS), Vref(TS) ....................... AGND to VOOA
Analog input voltage range, V'(ANLG) ............................................... AGND to VOOA
Digital input voltage range, V'(OGTL) ................................................ DGND to VOOO
Digital output voltage range, VO(OGTL) ............................................. DGND to VOOO
Operating free-air temperature range, TA ............................................ -20°C to 75°C
Storage temperature range, TSl9 .............................. '..................... -55°C to 150°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

~'TEXAS

INSTRUMENTS
2-430

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLV5510
3-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124 - DECEMBER 1997

recommended operating conditions

Supply voltage

MIN

NOM

MAX

VOOA-AGNO

2.7

3.3

3.6

VOOO-OGNO

2.7

3.3

3.6

AGNO-OGNO

-100

Reference input voltage (top), Vref{T) .

Vre f(S)+2
0

Reference input voltage (bottom), Vref(S)
Analog input voltage range, VI(ANlG) (see Note 1)

0.6

Vref{S)

High-level input voltage, VIH

V

100

0
Vref(S)+2

UNIT

mV

VCC-0.3

V

Vre f(T)-2

V

Vref{T)

V

0.5

V

2.5

V

low-level input voltage, Vil
Pulse duration, clock high, tw(H)

50

ns

Pulse duration, clock low, tw(l)

50

ns

NOTE 1: REFT - REFS!> 2.4 V maximum

electrical characteristics at Voo = 3 V, Vref(T) = 2.6 V, Vref(B) = 0.6 V, fconv = 10 MSPS, TA = 25°C
(unless otherwise noted)
PARAMETER

TEST CONOITIONSt

Linearity error

El

fconv = 10 MSPS,
VI = 0.6 V to 2.6 V
Linearity error, differential

EO

Self bias (1)

Iref

MAX
±0.75
±1

±0.3

TA = 25°C

Short REFT to REFTS

Self bias (3)

Short REFS to AGNO,

Short REFT to REFTS

Reference current

Vref(T) - Vref(S) = 2 V

Rref

Reference voltage resistor

Between REFT and REFB terminals

Analog input capacitance

VI(ANlG) = 1.5 V + 0.07 Vrms

EZS

Zero-scale error

±0.5

0.57

0.61

0.65

1.9

2.02

2.15

2.18

2.29

2.4

6

10

14

140

200

260

16

Vref = REFT - REFB = 2 V

lSB

-18

-43

-68

-20

0

20

EFS

Full-scale error
High-level input current

VOO=MAX,

VIH = VOO

5

III

low-level input current

VOO = MAX,

Vll=O

5

IOH

High-level output current

OE=GNO,

VOO = MIN,

VOH = VOO-0.5 V

IOl

low-level output current

OE=GNO,

VOO = MIN,

VOL = 0.4 V

-1.5

w

V

fl.

mA

o

Q

IOZH

High-level high-impedancestate output leakage current

OE=VOO,

VOO = MAX,

VOH = VOO

16

IOZl

low-level high-impedancestate output leakage current

OE=VOO,

VOO = MIN,

VOl=O

16

Supply current

fs= 10 MSPS,

NTSC ramp wave input

mV

J.LA
mA

2.5

J.LA

..

13

20

mA

Conditions marked MIN or MAX are as stated In recommended operating condllions .

~'TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3:
w
:;:
a:

pF

IIH

..

UNIT

±0.75

TA = -20°C to 75°C

Ci

100

t

TYP
±0.4

TA = -20°C to 75°C

Short REFS to REFBS,

Self bias (2)

MIN

TA=25'C

2-431

I-

:::>

c

oa:
fl.

TLV5510
3-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITALCONVERTER
SLAS124 - DECEMBER 1997

operating characteristics at VOD
(unles$ otherwise noted)

=3 V,Vref(T) =2.6 V, Vref(B) =0.6 V, fCLK =10 MHz, TA =25°C

PARAMETER

TEST CONDITIONS

Iconv

Maximum conversion rate

VI(ANLG) = 0.5 V - 2.5 V,

TYP

MIN

II = I-kHz ramp wave form

MAX

10

UNIT
MSPS

BW

Analog input bandwidth

At-l dB

14

tpd

Digital output delay time

CL :> 10 pF (see Note 2)

18

tAJ

Aperture jitter time

tps

Sampling delay time

..

MHz
30

ns

30

ps

4

ns

NOTE 2: CL Includes probe and Jig capacitance

I

I

CLK(Clock)

11

i\-I1

I

.I

I

ANALOG IN

(Input Signal)

"tJ

-:0

oC

01-08
(Output Data)

I

IN

~~I_N_-_3~IJ~~~_N-_2~JX

I N+2
I
I
N-l

tpd~

c:

Figure 1. 1/0 Timing Diagram

5l
"tJ

':0

m
<
m

-

==

~TEXAS

INSTRUMENTS
2-432

I

Y""-\Ly---

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

X

N

I

X

I

N+l

TLV5510
3-V 8-811 HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124 - DECEMBER 1997

PRINCIPLES OF OPERATION

functional description
The TlV551 0 is a semiflash ADC featuring two lower comparator blocks of four bits each.
As shown in Figure 2, input voltage VI(1) is sampled with the falling edge of ClK1 to the upper comparators block
and the lower comparators block(A), 8(1). The upper comparators block finalizes the upper data UD(1) with the
rising edge of ClK2, and simultaneously, the lower reference voltage generates the voltage RV(1)
corresponding to the upper data. The lower comparators block (A) finalizes the lower data lD(1) with the rising
edge of ClK3. UD(1) and lD(1) are combined and output as OUT(1) with the rising edge of ClK4. According
to the above internal operation described, output data is delayed 2.5 clocks from the analog input voltage
.
sampling point.
Input voltage VI(2) is sampled with the falling edge of ClK2. UD(2) is finalized with the rising edge of ClK3, and
lD(2) is finaliz,ed with the rising edge of ClK4 at the lower comparators block(B). OUT(2) is output with the rising
edge of ClKS.
VI(1)

VI(3)

VI(4)

~

w

ANALOG IN

:>
w

(Sampling Points)

a:

D..
I-

CLK (Clock) .

Upper Comparators Block

~

S(1)

I I i I I
C(1)

S(2)

C(2)

S(3)

C(3) IS(4)

i I

o

C(4)

::l
C

o
a:

Upper Data

D..

Lower Reference Voltage

Lower Comparators Block (A)
Lower Data (A)

Lower Comparators Block (B)

Lower Data (B)

~

LD~-1)

I

I

: ~D(-2)

I

I

*
I

L~(1)
I

~

I

I

I

+) i I i +) i I i' +)
C(O)

=x
I

01- 08 (Data Output)

I

OUT(-2)

S(2)

I

X

C(2)

I

I

LD(O)

S(4)

~.

I

I

I

I

I

I

X

OUT(-1)

X

OUT(O)

X

I

LD(2)

I

x=
I

OUT(1)

Figure 2. Internal Functional Timing Diagram

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-433

TLV5510
3-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124- DECEMBER 1997

PRINCIPLES OF OPERATION

internal referencing
Three internal resistors are provided such that the device can generate an internal refer~nce voltage. These
resistors are brought out on terminals VOOA, REFTS, REFT, REFS, REFSS, and AGND.
To use the internally generated reference voltage, terminal connections should be made as shown in Figure 3.
This connection provides the standard video 2-V reference for the nominal digital output.
TLV5510
18

VDDA

(Analog Supply)

?

RE FTS

I

16

~

R1
40 Q NOM

17

REFT

"tJ

::D

oC

Rref
200 Q NOM

REFB

23

I

22

RE FBS

;> R2

AGND

c:

~

21

60 Q NOM

1-

o-I

Figure 3. External Connections for Using the Internal Reference Resistor Divider

"tJ

::D

m
S
m
:E

functional operation
The TLV551 0 functions as shown in the Table 1.
Table 1. Functional Operation
DIGITAL OUTPUT CODE

INPUT SIGNAL
VOLTAGE

STEP

Vref(T)

255

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

o.

0

0

0

0

0

0

0

128

1

0

0

0

0

0

0

0

0

127

0

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Vref(B)

0

0

0

0

0

0

0

0

0

MSB

LSB

I

~TEXAS

INSTRUMENTS
2-434

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5510
3-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124- DECEMBER 1997

APPLICATION INFORMATION
The following notes are design recommendations that should be used with the TlV551 O.
•

External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.

•

RF breadboarding or printed-circuit-board (PCB) techniques should be used throughout the evaluation and
production process. Breadboards should be copper clad for bench evaluation.

•

Since AGNO and OGNO are connected internally, the ground lead in must be kept as noise free as possible.
A good method to use is twisted-pair cables for the supply lines to minimize noise pickup. An analog and
digital ground plane should be used on PCB layouts when additional logic devices are used. The AGNO
and OGNO terminals of the device should be tied to the analog ground plane.

•

VOOA to AGNO and VOOO to OGND should be decoupled with 1-J.tF and 0.01-IlF capacitors, respectively,
placed as close as possible to the appropriate device terminals. A ceramic chip capacitor is recommended
for the 0.01-IlF capacitor. Care should be exercised to assure a solid noise-free ground connection for the
analog and digital grounds.

•

VOOA, AGND, and ANALOG IN terminals should be shielded from the higher frequency terminals, ClK and
00-07. If possible, AGNO traces should be placed on both sides of the ANALOG IN traces on the PCB for
shielding.

•

In testing or application of the device, the resistance of the driving source connected to the analog input
should be 10 n or less within the analog frequency range of interest.

3:
w

:>
w
a:

0..

I-

o

:J
C

oa:

0..

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-435

TLV5510
3-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITALCONVERTER
SLAS124 - DECEMBER 1997

APPLICATION INFORMATION
OVOO
3. 3V

HI~9
TlV5510
AVOO
3.3 V

13
FB1

14
-LC3

FB2

15

~

-~

T-=-

&C4

C5

"tJ

oC

Video Input
(2Vpp)

II

<

c:

o-I

R1

~1

I
I

Buffer

ClK

VOOA

VOOO

VOOA

DB (MSB)

C7

Hi

G

I
I

Hi

C6

t

1a

VOOA

05 7

ANALOG IN

04 6

AGNO

03

AGNO

02 4

21

r:

Tca

"tJ

23

:II

m
<
m

-

24

OGNO 2

OGNO

OE 1

DESCRIPTION
0.1 IlF Capacitor

C2

10 pF Capacitor

C5

47 IlF Capacitor

FBI, FB2

Ferrite Bead

RI

75 Q resistor

Figure 4. Application and Test Schematic

~TEXAS

INSTRUMENTS
2-436

I~

I
C10

5 ,

REFB

r.
lOCATION

Clock

REFBS 01 (lSB) 3

:e

CI, C3, C4, C6-CIO

10

06 a

20

~

11

17 REFT

19

C2

12

07 9

REFTS

From Clamp
Output

:II

VOOO

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Output
Enable

3-1

Contents
Page

AD7524M: ................................................'.................. 3-3
TL5632: ....................................' ....... ; ........................ 3-11
TLC5602: .................................................. ; ............... 3-19
TLC5604: .................................................................. 3-27
TLC5614: .................................................................. 3-29
TLC5615: .................................................................. 3-31
TLC5616 : .................................................................. 3-47
TLC5617 : .................................................................. 3-55
TLC5618 : ..................................................' ................ 3-75
TLC5618M: ................................................................ 3-95
TLC5620: .................................................................. 3-97
TLC5628 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-107
TLC7225: ................................................................. 3-117
TLC7226 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-137
TLC7524 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-153
TLC7528 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-163
TLC7628 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-177
TLV5613: ................................................................ 3-187
TLV5619: ................................................................ 3-195
TLV5620: ................................................................ 3-203
TLV5621 : ................................................................ 3-215
TLV5628: ................................................................ 3-231
TMS57014A: ............................................................ 3-243

'"C
c:
"""&

"C

oen

(I)

C

:t=-

O

en

3-2

AD7524M
Advanced LinCMOSTM 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTER
SGLS028A - SEPTEMBER 1989 - REVISED MARCH 1995

•

Advanced LinCMOSTM Silicon-Gate
Technology

JPACKAGE
(TOP VIEW)

•

Easily interfaced to Microprocessors

•

On-Chip Data Latches

•

Monotonicity Over Entire AJD Conversion
Range

•

Segmented High-Order Bits Ensure
Low-Glitch Output

•

Designed to Be interchangeable With
Analog Devices AD7524, PMI PM-7524, and
Micro Power Systems MP7524

•

Fast Control Signaling for Digital Signal
Processor Applications Including Interface
With SMJ320

OUT1
OUT2
GND
DB7
DB6
DB5
DB4
DB3

RFB
REF
VDD
WR

CS
DBO
DB1
DB2
FKPACKAGE
(TOP VIEW)

C\I~

KEY PERFORMANCE SPECIFICATIONS

~~()~tt

Resolution

8 Bits

Linearity error

1/2 LSB Max

OOZa:a:

Power dissipation at VDD =,5 V

5mWMax

Settling time

100 ns Max

Propagation delay

80 ns Max

GND
DB7
NC
DB6
DB5

description

The AD7524M is an Advanced LinCMOSTM 8-bit
digital-to-analog converter (DAC) designed for
easy interface to most popular microprocessors.

3 2

1 2019

4

18

5

17

6

16

7

15

8

14
9 10 11 1213

~

£

0

0

~ ~
0

VDD
WR

NC
CS
DBO

co
0

NG-No intern,!1 connection

The AD7524M is an 8-bit multiplying DAC with input latches and with a load cycle similar to the write cycle of
a random access memory. Segmenting the high-order bits minimizes glitches during changes in the
most-significant bits, which produce the highest glitch impulse. The AD7524M provides accuracy to 1/2 LSB
without the need for thin-film resistors or laser trimming, while dissipating less than 5 mW typically.
Featuring operation from a 5-V to 15-V single supply, the AD7524M interfaces easily to most microprocessor
buses or output ports. Excellent multiplying (2 or 4 quadrant) makes the AD7524M an ideal choice for many
microprocessor-controlled gain-setting and signal-control applications.
The AD7524M is characterized for operation from -55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
CERAMIC CHIP
CARRIER
(FK)

TA

-55°C to 125°C

AD7524MFK

CERAMIC DIP
(J)
AD7524MJ

Advanced LinCMOS is a trademark of Texas Instruments Incorporated.

~~O:~~~~to~T: 8i=~~~~~s'~~~:~r:~:: Ie:~~o~m~~~

standard warranty. Production processing does not necessarl'v Include
testing of all parameters.

~TEXAS

Copyright © 1995, Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-3

AD7524M
Advanced LinCMOSTM 8·BIT MULTIPLYING
DIGITAL~To-ANALOG .CONVERTER
SGLS028A - SEPTEMBER 1989 - REVISED MARCH 1995

functional block diagram
R

15

R

R

2R
r -_ _1.. ::..6 RFB

R
'--h-*---jf--;--*---+--;-~-+-*----'-

OUT1

'---;-_ _---,----+-:----+---.,---+----2 OUT2
CS 12

3

-t.....,..__..,...__.,..----'! Ir-...,.....:-...-----=-

WR ....,1:-'.3_ _

4
DB7
(MSB)

5

6

11

DB6

DB5

DBO
(lSB)

GND

~------~v~--------~I
Data Inputs

operating sequence

114-4--1

tsu(CS) ------I~~If__....:-*,4
~I
th(CS)

~--------10~%\L~________________-+I__~~r--------

r--

I

twCWR)

~i

10%\~_______~0%
I+- tsu(D) -+! _ _
I
-th(D)
I

D B O _ D B 7 - - - - - - - - - - - - - - - - t t l r - - - - - - -.....,J-'- - - - - -

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS '75265

AD7524M
Advanced LinCMOSTM 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
SGLS028A - SEPTEMBER 1989 - REVISED MARCH 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Voo ......................................................... -0.3 V to 17 V
Voltage between RFB and GND ............................................................. ±25 V
Digital input voltage range, V, ................................................. -0.3 V to Voo+0.3 V
Reference voltage range, Vref .............................................................. ±25 V
Peak digital input current, I, ................................................................ 10 I1A
Operating free-air temperature range, TA ........................................... -55°C to 125°C
Storage temperature range, TSIg ................................................... -65°C to 150°C
Case temperature for 60 seconos, T c: FK package .......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ..................... 300°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions
VOO= 15V

VOO=5 V
MIN

4.75

Supply voltage, VDD

NOM

MAX

MIN

5

5.25

14.5

Low-level input volage, VIL

15.5

40

UNIT

V
V

V
1.5

0.8

CS setup time, tsu(eS)

15

13.5

2.4

High-level input voltage, VIH

MAX

±10

±10

Reference voltage, Vref

NOM

V

40

ns

0

0

ns

Data bus input setup time, tsu(D)

25

25

ns

Data bus input hold time, thlDl

10

10

ns

Pulse duration, WR low, tw(WR)

40

40

CS hold time, thlCS)

-55

Operating free-air temperature, TA

125

-55

ns

125

°C

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-5

AD7524M
Advanced LinCMOSTM 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTER
SGLS028A - SEPTEMBER 1989 - REVISED MARCH 1995

electrical characteristics over recommended operating free-air temperature range, Vref
OUTt and OUT2 at GND (unless otherwise noted)
PARAMETER

IIH

High-level input current

VI = VDD

IlL

Low-level input current

VI = 0

OUTl
Ipkg

DBO-DB? at 0,
WR and CS at 0 V

OUT2

DBO-DB? at VDD,
WR and CS at 0

IDD

kSVS

Supply current

Standby

Supply voltage sensitivity,

dgainltNDD

Ci

Input capacitance, DBO-DB?,
WR,CS

Co

Output
capacitance

TYP

MAX

10
1

Full-range

-10

-10

25°C

-1

-1

Full-range

±400

±200

25°C

±50

±50

Full-range

±400

±200

±50

±50

25°C

2

2

Full-range

500

500

25°C

100

100

Full-range
dVDD = 10%

0.16
0.002

25°C

0.001

0.02

DBO-DB? at 0, WR and CSat 0 V

DBO-DB? at VDD, WR and CS at 0 V.

Reference input impedance
(REF to GND)

flA

nA

mA
~A

%1%
pF

5

pF

30

30
120

120

120

30

30
20

5

~

0.04

120

20

5

UNIT

0.02

5

VI =0

OUTl
OUT2

MAX

1

OUTl
OUT2

TYP

10

DBO-DB? at VIHmin or VILmax
DBO-DB? at 0 V or VDD

MIN

25°C

Vref= ±10V
Quiescent

MIN

Full-range

Vref= ±10V

Output leakage
current

VOO= 15 V

VOo=5 V

TEST CONOITIONS

=10 V,

pF

kQ

operating characteristics over recommended operating free-air temperature range, Vref = 10 V,
OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER

.VOO=15V

VCC=5V

TEST CONDITIONS

MIN

Linearity error

I Full range
I 25°C

MAX

MIN

MAX

±0.2

±0.2

±1.4

±0.6

±1

±0.5

UNIT
%FSR
%FSR

Gain error

See Note 1

Settling time (to 112 LSB)

See Note 2

100

100

ns

Propagation delay from digital input to
90% of final analog output current

See Note 2

80

80

ns

Feedthrough at OUTl or OUT2

Vref = ±10 V (100 kHz sinewave),
WR and CS at 0, DBa-DB? at a

Temperature coefficient of gain

TA = 25°C to tmin or t max

NOTES:

I Full range
I

25°C

0.5
0.25·

±0.004

1. Gain error IS measured uSing the Internal feedback resistor. Nominal Full Scale Range (FSR) = Vref - 1 LSB.
2. OUTl load = 100 (2, Cext = 13 pF, WR at a V, CS at a V, DBO-DB? at 0 V to VDD or VDD to 0 V.

~TEXAS

INSTRUMENTS
3-6

0.5
0.25

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

±0.001

%FSR
%FSRI
°C

AD7524M
Advanced LinCMOSTM 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
SGLS028A - SEPTEMBER 1989 - REVISED MARCH 1995

PRINCIPLES OF OPERATION
The AD7524M is an 8-bit multiplying D/A CDnverter consisting of an inverted R-2R ladder, analog switches, and
data input latches. Binary weighted currents are switched between the OUT1 and OUT2 bus lines, thus
maintaining a constant current in each ladder leg independent of the switch state. The high-order bits are
decoded and these decoded bits, through a modification in the R-2R ladder, control three equally weighted
current sources. Most applications only require the addition of an external operational amplifier and a voltage
reference.
The equivalent circuit for all digital inputs low is seen in Figure 1. With all digital inputs low, the entire reference
current, Iref, is switched to OUT2. The current source 1/256 represents the constant current flowing through the
termination resistor of the R-2R ladder, while the current source Ilkg represents leakage currents to the
substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all
digital inputs high, the off-state switch capacitance (30 pF maximum) appears at OUT2 and the on-state switch
capacitance (120 pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown
in Figure 1. Analysis of the circuit for all digital inputs high is similar to Figure 1; however, in this case, Iref would
be switched to OUT1.
Interfacing the AD7524M D/A converter to a microprocessor is accomplished via the data bus and the CS and
WR control signals. When CS and WR are both low, the AD7524M analog output responds to the data activity
on the DBO-DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects
the analog output. When either the CS signal or WR signal goes high, the data on the DBa-DB7 inputs are
latched until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless
of the state of the WR signal.
The AD7524M is capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant or 4-quadrant multiplication are shown in Figures 2 and 3. Input coding for unipolar and bipolar
operation are summarized in Tables 1 and 2, respectively.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-7

AD7524M
Advanced LinCMOSTM 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER

SGLS028A - SEPTEMBER 1989 - REVISED MARCH 1995

PRINCIPLES OF OPERATION
!'-R-----RFB

.

"~~,....--i----f.- 30-P-F-~- OUT1
-::-

-:-+

REF--'I/IA~6------.-6~1~OUT2
112561'

~

11kg

-::-

l' ~T
-::-

120 pF

-::-

Figure 1. AD7524M Equivalent Circuit With All Digital Inputs Low

RB
C (see Note B)

DBO-DB7

-~-v

>----<_-- Output

CS - - - I
WR - - - I

-::-

Figure 2. Unipolar Operation (2-Quadrant Multiplication)
Vref

VDD
20kQ

RA= 2kQ
(see Note A)

RB

20kQ

>-*"--

DBO-DB7

CS---I
WR-----I

5kQ
-::-

-::-

Figure 3. Bipolar Operation (4-Quadrant Operation)
NOTES: A. RA and RS used only if gain adjustment is required.
S. C phase compensation (10- 15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655803 • DALLAS. TEXAS 75265

Output

AD7524M
Advanced LinCMOSTM 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTER
SGLS028A - SEPTEMBER 1989 - REVISED MARCH 1995

PRINCIPLES OF OPERATION
Table 1. Unipolar Binary Code
DIGITAL INPUT
(see NOTE 3)
MSB

I

ANALOG OUTPUT

LSB

11111111
10000001
10000000
01111111
00000001
00000000
NOTES:

-Vref
-Vref
-Vref
-Vref
-Vref
0

(255/256)
(129/256)
(128/256) = -Vref /2
(127/256)
(1/256)

= 1/256 (Vref).

3. LSB

Table 2. Bipolar (Offset Binary) Code
DIGITAL INPUT
(see NOTE 4)
MSB

I

ANALOG OUTPUT

LSB

11111111
10000001
10000000
01111111
00000001
00000000
NOTES:

Vref (127/128)
Vref (128)
0
-Vref (128)
-Vref (127/128)
-Vref

4. LSB = 1/128 (Vref).

microprocessor interfaces
DO-D7~

_________________D_a_la_B_u_s_________1

Z-80A

WR

IORQ

AO-A15

1-------;--....

~--------------,

I----~_--_I

Decode
Logic

Address Bus

Figure 4. AD7S24M-Z-80A Interface

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-9

AD7524M
Advanced LinCMOSTM 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTER

SGLS028A - SEPTEMBER 1989 - REVISED MARCH 1995

PRINCIPLES OF OPERATION
DO-D7r-__________________
D_at_a_B_us______- .

6800
cI>2 r------j

10---------------1 WR

Decode
Logic

VMA 1------<.......__+_---1

AO-A15

Address Bus

Figure 5. AD7524M-6800 Interface

A8-A15

Address Bus
Decode
Logic
----,/

B-Bit
Latch

8051

CS

I

ALE

WR

ADO-AD7

WR

I
Address/Data Bus

Figure 6. AD7524M-8051 Interface

~TEXAS

3-10

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD7524M

OUT1
OUT2

DBO-DB7

II

TL5632C
a·BIT 3·CHANNEL HIGH·SPEED DIGITAL·TO·ANALOG CONVERTER
•
•
•
•
•
•
•
•

8-Bit Resolution
Linearity ... ±1/2 LSB Maximum
Differential Nonlinearity ... ±1/2 LSB
Maximum
Conversion Rate ... 60 MHz Min
Nominal Output Signal Operating Range
VCctoVCC-1 V
TTL Digital Input Voltage
S-V Single Power Supply Operation
Low Power Consumption ... 3S0 mW Typ

description
The TL5632C is a low-power ultra-high-speed
video digital-to-analog converter that uses the
Advanced Low-Power Schottky (ALS) process.
The device has a three channel 1/0; the red, the
blue, and the green channel. The red, blue, and
green signals are referred to collectively as the
RGB signal. An internally generated reference is
also provided for· the standard video output
voltage range. Conversion of digital signals to
analog signals can be at a sampling rate of dc to
60 MHz. The high conversion rate makes the
TL5632C suitable for digital television, computer
digital video processing, and high-speed data
conversion.

FRPACKAGE
(TOP VIEW)

I-I-I-~

o

080:::l0:::l0:::l0LL

O»ZOZOZOZUJ

zo «

(!)a: (!)(!) (!) CD (!) a:

044 43 42 41 40 39 38 3736 3534

(MS8) R1

1

R2
R3
R4
R5
R6
R7

2

§

.

3
4
5
6
7
8
9
10
11

(LS8) R8
(MS8)G1
G2
G3

33

REF OU'T

~

AVcc

31
30
29
28
27
26
25
24
23

CCOMP

DVcc
GND
CLKRIN
CLKGIN
CLKslN
88 (LS8)
87
86

12 13 14 15 16 17 18 19 20 21 22

NC - No internal connection

The TL5632C is characterized for operation from
QOC to 7QoC.
FUNCTION TABLE
STEP

I

DIGITAL INPUT

OUTPUT VOLTAGE

0
1

LLLLLLLL
LLLLLLLH

3.980 V
3.984 V

127
128
129

LHHHHHHH
HLLLLLLL
HLLLLLLH

4.488 V
4.492 V
4.996 V

254
255

HHHHHHHL
HHHHHHHH

4.996 V
5.000 V

···

···

··
·

··
·

··
·
··
·

AVAILABLE OPTIONS

~~:r~~~~1: 8=~ftTc~li:sl~~~~~::: !e=!'=~m~:;

standard warranty. Production processing don not necessarily Include
testing of all parameters.

TA

PACKAGE

O°C to 70°C

TL5632CFR

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright © 1994. Texas Instruments Incorporated

3-11

TL5632C
8~BIT 3~CHANNEL

HIGH·SPEED DIGITAL·TO·ANALOG CONVERTER

SLAS091 - DECEMBER 1994

functional block diagram
ROUT

GOUT

BOUT

r-----------+-~~----------+-~~---------------AVCC

8

8

8

r-----

CCOMP

' - - - - - REF IN

REF OUT

CLKRIN

R1-R8

CLKGIN

G1-G8

B1-B8

CLKBIN

schematics of outputs
EQUIVALENT OF REF OUT

EQUIVALENT OF ROUT. GOUT. BOUT

AVCC
- - . - - - - - - AVCC
1 kQ
REF OUT

240 Q typical
. _ - - - - - ROUT. GOUT. BOUT

-+-----GND

~TEXAS

3-12

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL5632C
8·BIT 3·CHANNEL HIGH·SPEED DIGITAL·TO·ANALOG CONVERTER
SLAS091 - DECEMBER 1994

Terminal Functions
TERMINAL
NAME

NO.

DESCRIPTION

1/0

18-25

I

BOUT

36

0

CCOMP

31

CLKBIN

26

I

B-channel clock input

CLKGIN

27

I

G-qhannel clock input

CLKRIN

28

I

R-channel clock input

G1- G8

9-16

I

G-Channel digital input (G1= MSB)

81- B8

GND

Phase compensation capacitance. A 1 IlF capacitor is connected from CCOMP to GND.

29,35,37,
39,41

GOUT

38

B-channel digital input (B1 = MSB)
B-channel analog output

Ground. All GND terminals are connected internally; however, all GND terminals should be connected
externally to a ground plane or equivalent low impedance ground return.

0

G-channel analog output

NC

17,44

R1- R8

1-8

I

No connection internally

ROUT

40

0

AVCC

32,42

DVCC

30,43

REF IN

34

I

Reference voltage input. REF IN accepts the reference voltage on REF OUT. An external reference can
also be applied consistent with Note 1.

REF OUT .

33

0

Reference voltage output. An internal voltage divider generates the voltage level (see schematics of
outputs, page 2).

R-channel digital input (R1= MSB)
R-channel analog output
Analog power supply voltage
Digital power supply voltage

NOTE 1: VCC- VrefS 1.2 V

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Power supply voltage range, AVec, DVcc (see Note 2) ................................. -0.3 V to 7 V
Digital input voltage range,VI ...................................................... -0.3 V to DVcc
Analog output voltage range, ROUT, GOUT, BOUT, eCOMP (externally applied) .... -0.3 V to AVec + 0.3 V
Reference input range, REF IN ............................................. -0.3 V to AVec + 0.3 V
Reference output range, REF OUT .......................................... -0.3 V tD AVec + 0.3 V
Operating free-air temperature range, TA .............................................. ooe to 70 0 e
Storage temperature range ........................................................ -65°e to 1500 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260 0 e

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operllting conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 2: All voltage values are with respect to GND.

~TEXAS.

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-13

TL5632C
8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO·ANALOG CONVERTER
SLAS091 - DECEMBER 1994

recommended operating conditions
Supply voltage, AVec, DVec

MIN

NOM

MAX

UNIT

4.75

5

5.25

V

0.8

V

High-level input voltage, VIH

2

V

Low-Ievel'input voltage, VIL
Reference voltage, Vref (see Note 1)

4

3.8

Setup time, data before eLK!, tsu1
Hold time, data after eLK!, th1

4.2

V

10

ns

3

ns

Pulse duration at high level, tw1

8.3

ns

Pulse duration at low level, tw2

8.3

ns

External phase compensation capacitance, eeOMP

1

!LF

Operating free-air temperature, TA

0

70

°e

NOTE 1: Vee- Vret'; 1.2 V

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TEST CONDITIONS

PARAMETER

MIN

TVPt

MAX

Resolution
High-level input current

Vee = 5.25 V,

VIH =2.7V

IlL

Low-level input current

Vee =5.25 V,

VIH=2.7V

Iref

Reference input current

REF IN = 4 V

Vref

Reference output voltage

Vee=5V,

With internal reference

VFS

Full-scale analog output voltage

VIH =2V,

REF IN =4 V

VZS

Zero-scale analog output voltage

VIL = 0.8 V,

REF IN =4 V

IIH

Bit

20

!LA

-400

!LA
10
4

3.8
AVec-15

UNIT

8

AVec

4.2

!LA
V

AVce+ 15

mV
V

3.9

3.98

4.05

RGB full-scale ratio

0%

4%

8%

zo

Output impedance

200

240

280

ICC

Supply current

70

90.'

W
rnA

operating characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER

TEST CONDITIONS

EL

Linearity error

End point,

ED

Differential linearity error

REF IN =4 V

fc

Maximum conversion rate

MIN

TVPt

REF IN =4 V

tPLH

Propagation delay time, low-to-high level

10

Propagation delay time, high-to-Iow level

10

tr

Rise time

tf

Fall time

~TEXAS

INSTRUMENTS
3-14

eLS5 pFj:

5
5

All tYPical values are at Vce = 5 V, TA = 25°C.
:j: CL includes probe and jig capacitances.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

LSB
LSB
MHz

tPHL

t

UNIT

±0.5
±0.5
60

TA=25°e,

MAX

ns

ns

TL5632C
8·BIT 3·CHANNEL HIGH·SPEED DIGITAL·TO·ANALOG CONVERTER
SLAS091 - DECEMBER 1994

PARAMETER MEASUREMENT INFORMATION
~tW1~tW2~
I
I __- - r -

I
CLKRIN,CLKGIN,CLKBIN
(Clock)

'--_J

____-.. rR1- Ra,G1- G8,B1- Ba
(Input Oata) _ _ _ _ _

tsu1

\l/

,..,1\

I
I

o

--¥-: th1 --4 ...._----1.--\l/
~30V
1\
~

i1

ROUT, GOUT, BOUT
(Analog Output)

tr

~ j4-

i

50%
10%
1

1
1

I

1

tpLH

tf

~ ~

+- - -

Jtie-m90~%r----i-1~90OC:o"",o~S:-

~.I

50%
10%

VFS
VZS

1

~

14

tPHL

TYPICAL CHARACTERISTICS

5-------------'----

VFS - - - - - - - - - - - - - - .1,1

>

4.996

------------

>

I

f
~

i

4.492
4.488

n

~

I
I
I
I
I
I
I
I

'SQ.
'S

0

'"0

~
~

1

'"

S

4.496

og>
I

i

I

G>

iii
I:



07-00

8

8

--..,---i >-f--I

Buffer
OriverWith
Register
Oecode

63
AOUT

3

1-+--Ilxl

FUNCTION TABLE
STEP

OIGITAL INPUTS

00

OUTPUT
VOLTAGEt

L

L

3.980 V

L

H

3.984 V

H

H

4.488 V

07

06

05

04

03

02

01

0

L

L

L

L

L

L

1

L

L

L

L

L

L

H

H

I

I

I
H

127

L

H

H

128

H

L

L

L

L

L

L

L

4.492 V

129

H

L

L

L

L

L

L

H

4.496 V

I

I

I

254

H

H

H

H

H

H

H

L

4.996 V

255

H

H

H

H

H

H

H

H

5.000 V

t VDD = 5 V and Vref = 4.02 V

~TEXAS

3-20

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5602C,TLC5602M
VIDEO 8-BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS023C - FEBRUARY 1989 - REVISED MAY 1995

schematics of equivalent input and output
EQUIVALENT OF EACH DIGITAL INPUT
DGTL VDD

.

~

On

.

~

ANLG*
GND

EQUIVALENT OF ANALOG OUTPUT

--

DGTLVDD

l:d
J-

ANLG VDD1

80n
AOUT

--

J~

DGTL*
GND

~
ANLG*
GND

--

*

ANlG GND and DGTl GND do not connect internally and should be tied together as close to the device terminals as possible.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, ANLG Voo, DGTL Voo ......................................... -0.5 V to 7 V
Digital input voltage range, VI ........................................................ -0.5 V to 7V
Analog reference voltage range, Vref ................................... Voo - 1.7 V to Voo + 0.5 V
Operating free-air temperature range, TA: TLC5602C ................................... O°C to 70°C
TLC5602M ............................... -55°C to 125°C
Storage temperature range, Tstg ....... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C

t

Stresses beyond those listed 'under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum·rated conditions for extended periods may affect device reliability.

recommended operating conditions
Supply voltage, VDD
Analog reference voltage, Vref
High-level input voltage, VIH

MIN

NOM

MAX

UNIT

4.75

5

5.25

V

3.8

4

4.2

V

0.8

V

V

2

lOW-level input voltage, Vil
Pulse duration, ClK high or low, tw

25

ns

Setup time, data before ClK!, tsu

16.5

ns

Hold time, data after ClK!, th

12.5

ns

1

IlF

Phase compensation capacitance, C como (see Note 1)
load resistance, Rl
Operating free·air temperature,TA

n

75k
ITlC5602C

0

70

I TlC5602M

-55

125

°C

NOTE 1: The phase compensation capaCitor should be connected between COMP and ANlG GND.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-21

TLC5602C,TLC5602M
VIDEO 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS023C - FEBRUARY 1989 - REVISED MAY 1995

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
IIH

High-level input current

IlL

Low-level input current

Iref
VFS

VZS

ro

TEST CONDITIONS

I Digital
I inputs

MIN

1

UNIT

tl

I1A

VI =OV

tl

Input reference current

Vre f=4 V

10

I1A
I1A

Full-scale analog output voltage

VDD = 5 V,

Zero-scale analog output voltage

Output resistance

VDD = 5 V,
TA = full range§

Vref = 4.02 V
Vref = 4.02 V,

mV

VDD-15

VDD

VDD+15

TLC5602C

3.919

3.98

4.042

TLC5602M

3.919

3.98

4.042

TLC5602M

3.919

3.98

4,062

60

80

120

Q

25

mA

TA = 25°C

TLC5602C

TA = full range§

TLC5602M

Ci

Input capacitance

fclock = 1 MHz,

TA = 25°C

15

IDD

Supply current

fclock = 20 MHz,

Vref = VDD-0.95 V

16

*

MAX

TVP*

VI =5V

V

pF

All typical values are at VDD = 5 V and TA = 25'C.
§ Full range for the TLC5602C is O°C to 70°C, and full range for the TLC5602M is -55°C to 125'C.

operating characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER

TEST CONDITIONS
TA = full range=!:

EL(adj)

Linearity error, best-straight-line

TA = 25'C
TA = full range=!:

EL

Linearity error, end point

ED

Linearity error, differential

Gdiff

Differential gain

MIN

TVPt

TLC5602C

MAX

UNIT

to.2%
to.2%

TLC5602M

to.4%
to.15%
to.2%
0.7%

fdiff

Differential phase

NTSC 40-IRE modulated ramp,
fclock = 14.3 MHz, ZL;o, 75 kQ

ted

Propagation delay time, CLK to analog output

CL = 10 pF

25

ns

ts

Settling time to within 1/2 LSB

CL = 10 pF

30

ns

t

All tYPical values are at VDD = 5 V and TA = 25°C.
=!: Full range for the TLC5602C is O°C to 70'C, and full range for the TLC5602M is -55°C to 125°C.

~TEXAS

INSTRUMENTS
3-22

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

0.4°

TLC5602C,TLC5602M
VIDEO 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS023C - FEBRUARY 1989 - REVISED MAY 1995

PARAMETER MEASUREMENT INFORMATION

I+-- tsu --M--- th -+I

I
00-07

*50%

I

I

!

)l(

I+-- tw
I

.14

A OUT

tw

I

elK

50%

~--

I

----+l
I

50%

'-----I
I
I
I
I

I'F----

50%

I
I . I

±1/2lSB

~ts~

14- tpd---+l

Figure 1. Voltage Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-23

TLC5602C, TLC5602M
VIDEO 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS023C - FEBRUARY 1989 - REVISED MAY 1995

TYPICAL CHARACTERISTICS
BEST-STRAIGHT-LiNE LINEARITY ERROR

IDEAL CONVERSION CHARACTERISTICS
5
4.996 -

I

VDD =5 V
Vref = 4.02 V

I

••
•

G>

C)

s

;g

/

steplk8

0

Step~27

_

4.488 -

C)

•

/

•
•

0(

I

C)

/

C)

0
0
0
0
0
0
0

C;

t::

I

~

0
0
0
0
0
0

o·

::
0
0
0
0

ELO ~

3.988

...

0
0
0
0
0
0
0

0

.-

0

C;

.....-

~ >--.

•••

0
0
0
0
0

..-

.-

't

0
0
0
0
0
0
0
0

C;

0

:30
0
0

0
.-

;:
0
0
0
0

...

vs

VDD=5V
Vref = 4.02 V
See Note A

-

75

3.96

*~

3.95

o

65

.9

60

.

3.97

. /V

I

V

OJ

~

G>

N

'S
c.
'S

I

UI
N

>

90

80

0

G>

~~

. /V

VDD =5 V
VDD = Vo = 0.5 V
Data Input = FF

95

2lt::

3.98

....-

V

-

--

I--

I-""""

--

r--

-

70

I

3.94

55

3.93
3.92
-55 -35 -15

5

25

45

65

85

105

125

50
-55 -35 -15

TA - Free-Air Temperature - °C

5

25

45

Figure 5

Figure 4

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

65

85

TA - Free-Air Temperature - °C

NOTE A: Vref is relative to ANLG GND. VDD is the voltage between
ANLG VDD and DGTL VDD tied together and ANLG GND
and DGTL GND tied together.

3-24

....-

100

85

~

.......-

OUTPUT RESISTANCE

c:

3.99

S!

.-

FREE·AIR TEMPERATURE

4

~
'S

•••

0
0
0
0

FREE-AIR TEMPERATURE

C)

,g

0

C;

vs
4.02

I

0
0
0
0
0
0
0

.,...
.-

Figure 3

ZERO-SCALE OUTPUT VOLTAGE

G>

..,...

Digital Input Code

Figure 2

>

EL2

C;

Digital Input Code

4.01

~

ELl
I
~i- VZS

~..L

t-r -

3.98

......,...

EL253

v- -*

~:I

3.984

.......-

T

/~

r--=' Best·Fit Straight Line -

•
••



V

'IVi=sl~~55 -

VDD=5V
Vref = 4.02 V

4.996

>

/

//

'S
c. 4.492
'S

cot::

~.

Step 129

4.496

0

I

Step 253

4.992

>

I

Step 2 /

I

5

105

125

TLC5602C,TLC5602M
VIDEO 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS023C - FEBRUARY 1989 - REVISED MAY 1995

TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE·AIR TEMPERATURE
21

20

«

E
I

C

~

19

::I
(J

.J!:o
Co
Co
::I

18

C/)

I
Q

E

ZERO·SCALE OUTPUT VOLTAGE
vs
REFERENCE VOLTAGE
5

I .

\

vtio = 5 1V
Vref = 4.02 V
fcl~ck = 20 MHz

\

>

~

vo6=5
4.8 f- TA=25°C
See Note A

I

"'"

'"

4.6

:;

4.4

0

4.2

...'"

4

Cl

/

S

;g
~

~

17

/

/

'ii

"""

..........

1

r--.... '"""'- ....

I

3.8

C/)

N

>
16
-55 -35 -15

5

25

45

65

85

105

3.6

3.43.4

125

/

/

V
/
3.6

TA - Free-Air Temperature - °C

/

V

3.8

/

I'

4

4.2

4.4

4.6

4.8

5

Vref - Reference Voltage - V
NOTE A: Vref is relative to ANLG GND. VDD is the voltage
between ANLG VDD and DGTL VDD tied together and
ANLG GND and DGTL GND tied together.

Figure 6

Figure 7

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-25

TLC5602C,TLC5602M
VIDEO 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS023C - FEBRUARY 1989- REVISED MAY 1995

APPLICATION INFORMATION
The following design recommendations benefit the TLC5602 user:
•

Physically separate and shield external analog and digital circuitry as much as possible to reduce system
noise.

•

Use RF breadboarding or RF printed-circuit-board (PCB) techniques throughout the evaluation and
production process.

•

Since ANLG GNO and OGTL GNDare not connected internally, these terminals need to be connected
externally. With breadboards, these ground lines should connect to the power-supply ground through
separate leads with proper supply bypassing. A good method is to use a separate twisted pair for the analog
and digital supply lines to minimize noise pickup.
Use wide ground leads or a ground plane on the PCB layouts to minimize parasitic inductance and
resistance. The ground plane is the better choice for noise reduction.

•

ANLG VOO and OGTL Voo are also separated internally, so they must connect externally. These external
PCB leads should also be made as wide as possible. Place a ferrite bead or equivalent inductance in .series
with ANLG VoO,and the decoupling capacitor as close to the device terminals as possible before the ANLG
Voo and DGTL Voo leads are connected together on the board.

•

Decouple ANLG Voo to ANLG GND and DGTL Voo to DGTL GND with a 1-IlF and O.01-IlF capacitor,
respectively, as close as possible to the appropriate device terminals. A ceramic chip capacitor is
recommended for the O.01-IlF capacitor.

•

Connect the phase compensation capacitor between COMP and ANLG GND with as short a lead-in as
possible.

•

The no-connection (NC) terminals on the small-outline package should be connected to ANLG GNO.

•

Shield ANLG Voo, ANLG GND, and A OUT from the high-frequency terminals CLK and D7-00. Place
ANLG GND traces on both sides of the A OUT trace on the PCB.

~TEXAS

3-26

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLCS604
3-V TO S-V 10-81T 3-/lS QUADRUPLE DIGITAL-TO-ANALOG CONVERTER
WITH POWERDOWN
SLAS176 - DECEMBER 1997

•
•
•
•

•
•
•

o OR PW PACKAGE

Four 10-bit D/A Converters
SPI and TMS320 Compatible Serial
Interface
Internal Power-on Reset
Low Power Consumption
7.25 mW for 5V Supply
3.93 mW for 3V Supply
Reference Input Buffers
Voltage Output Range ... 2x the Reference
Input Voltage
Monotonic Over Temperature

(TOP VIEW)

DVDD
LDAC
SCLK
SDIN
PD
CS
FS
DGND

AVDD
REF1
DACA
DACB
DACC
DACD
REF2
AGND

applications
•
•
•
•
•

Battery Powered Test Instruments
Digital Offset and Gain Adjustment
Battery Operated/Remote Industrial
Controls
Machine and Motion Control Devices
Cellular Telephones

3:
w

:>
w

description
The TLC5604 device is 3-ILS quadruple 1O-bit voltage output digital-to-analog converter (DAC) with a SPI and
TMS320 compatible serial interface. This interface accepts 16 bit words comprised of 4 instruction bits and 12
DAC data bits. The unique feature of this part is that it is four separate DACs in one package. TLC5604 only
dissipates 7.25 mW of power with a 5 V supply and 3.93 mW of power with a 3 V supply.
There is an asynchronous LDAC pin for updating the output voltage, and a powerdown pin to ensure repeatable
startup conditions.
The resistor string output voltage is buffered by a 2x gain rail-to-rail output buffer. The buffer operates with a
Class A output stage to improve stability and reduce settling time.
AVAILABLE OPTIONS
PACKAGE
TA

.A.

~

SOIC
(0)

TSSOP
(PW)

O'C to 70'C

TLC5604CD

TLC5604CPW

-40'C to 85'C

TLC56041D

TLC56041PW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCT PREVIEW Information concerns products In the formative or

=~\icaC:=ar8o~es1:~~~.efexa;I~~~~~~:cre:e~es ~~ rigO~rf!

change or discontinue these products without notice.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright © 1997, Texas Instruments Incorporated

3-27

a:

D..

I-

o

:::l
C

oa:

D..

TLC5604
3-V TO 5-V 10-81T 3-IlS QUADRUPLE DIGITAL-TO-ANALOG CONVERTER
WITH POWERDOWN
SLAS176-DECEMBER 1997

functional block diagram
AVDD

161

REF1-1~5----------------____________~

14

7

"'C

:a

SDIN
CS

6

12

12-Bit
DAO
Latch

2

S-Blt
Control
DATA
Latch

14-Bit
Data
, and
Control
Register

Serial
Input
Register

-=-

0

C

c:

13

DACB

DACB

0

~

"'C

:a
m
<

-m

DACC

12

DACC

DACD

11

DACD

:e

10

911- sl1AGND

3-28

DGND

REF2

LDAC

"!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PD

TLCS614
3·Y TO S·Y 12·81T QUADRUPLE DIGITAL·TO·ANALOG CONYERTER
WITH POWERDOWN
o OR PW PACKAGE

•

Four 12-Bit DACs

•

SPI and TMS320 Compatible Serial
Interface

•

Hardware Powerdown

•

Internal Power-on Reset

•

Low Power Consumption
7.25 mW for 5-V Supply
3.93 mW for 3-V Supply

(TOP VIEW)

•

Reference Input Buffers

•

Voltage Output Range . .. 2x the Reference
Input Voltage

•

Monotonic Over Temperature

DVDD
LDAC
SCLK
SDIN
PD
CS
FS
DGND

AVDD
REF1
DACA
DACB
DACC
DACD
REF2
AGND

applications
•

Battery Powered Test Instruments

•

Digital Offset and Gain Adjustment

•

Battery Operated/Remote Industrial
Controls

•

Machine and Motion Control Devices

•

Cellular Telephones

:=w

:>
w
IX

description

C.

The TLC5614 device is 3-l.ls quadruple 12-bit voltage output digital-to-analog converter (DAC) with a SPI and
TMS320 compatible serial interface. This interface accepts 16 bit words comprised of 4 instruction bits and 12
DAC data bits. The unique feature of this part is that it is four separate DACs in one package. TLC5614 only
dissipates 7.25 mW of power with a 5-V supply and 3.93 mW of power with a 3-V supply.

o::;)

There is an asynchronous LDAC pin for updating the output voltage, and a powerdown pin to ensure repeatable
startup conditions.

oIX

The resistor string output voltage is buffered by a 2x gain rail-to-rail output buffer. The buffer operates with a
Class A output stage to improve stability and reduce settling time.
AVAILABLE OPTIONS
PACKAGE

.~
A

TA

SOIC
(0)

TSSOP
(PW)

O'C to 70'C

TLC5614CD

TLC5614CPW

-40'C to 85'C

TLC56141D

TLC56141PW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCT PREVIEW information concerns products in the formative or
deai"n phase of development. Characteristic data and other

:C::::~'l:c~~~:~~~:~o~~: :1W::::=:'erves the right to

~TEXAS

Copyright © 1997, Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-29

I-

c

C.

TLCS614
3-V TO S-V 12-81T QUADRUPLE DIGITAL-TO-ANALOG CONVERTER
WITH POWERDOWN
SLAS175- DECEMBER 1997

functional block diagram
AVDD

161

REF1-1=5----------------------------~

r------------------------,I

I
I
I
I
I
I
I
4
SDIN-

."

SDIN
CS

7

6

:D

Serial
Input
Register

14

Level
Shift

I
I
I
I.
I

DACA

I
I
114 DACA
12
14-Blt
Data
and
Control
2
Register ......-1--1

12-Bit
DAO
Latch

I
IL... _ _ _ _

Serial
Input
Register

8-Blt

Latch

o
C

c:

DACB

o-t

13

DACB

."

:D

m
<
m

DACC

12

DACC

DACD

11

DACD

-

=e

9[1- 8[1AGND

DGND

~TEXAS

3-30

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 .

TLC5615C, TLC56151
10-81T DIGITAL-TO-ANALOG CONVERTERS
SLAS142B - OCTOBER 1996 - REVISED MARCH 1997

•
•
•
•
•
•
•
•
•
•
•

o OR P PACKAGE

10-Bit CMOS Voltage Output DAC in an
a-Terminal Package

(TOP VIEW)

DINDs

5-V Single Supply Operation
3-Wire Serial Interface

SCLK
CS
DOUT

High-Impedance Reference Inputs
Voltage Output Range . .. 2 Times the
Reference Input Voltage

2
3
4

7
6
5

VDD

OUT

REFIN

AGND

Internal Power-On Reset
Low Power Consumption . .. 1.75 mW Max
Update Rate of 1.21 MHz
Settling Time to 0.5 LSB ... 12.511S Typ
Monotonic Over Temperature
Pin Compatible with the Maxim MAX515

applications
•

Battery-Powered Test Instruments

•

Digital Offset and Gain Adjustment

•

Battery Operated/Remote Industrial
Controls

•

Machine and Motion Control Devices

•

Cellular Telephones

description
The TLC5615 is a 1O-bit voltage output digital-to-analog converter (DAC) with a buffered reference input (high
impedance). The DAC has an output voltage range that is two times the reference voltage, and the DAC is
monotonic. The device is simple to use, running from a single supply of 5 V. A power-an-reset function is
incorporated to ensure repeatable start-up conditions.
Digital control of the TLC5615 is over a three-wire serial bus that is CMOS compatible and easily interfaced to
industry standard microprocessor and niicrocontroller devices. The device receives a 16-bit data word to
produce the analog output. The digital inputs feature Schmitt triggers for high noise immunity. Digital
communication protocols include the SPITM, QSPITM, and Microwire™ standards.
The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications.
The TLC5615C is characterized for operation from DOC to 70°C. The TLC56151 is characterized for operation
from -40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINEt
(D)

TA

t

PLASTIC DIP
(P)

O°C to 70°C

TLC5615CD

TLC5615CP

-40°C to S5°C

TLC56151D

TLC56151P

Available

In

tape and reel as the TLC5615CDR and the TLC56151DR

SPI and aSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.

:~~~~~~:fo~:1: s~!~r~~~'~~si;:~~~~~~ :: !e~!I~:~~m~~~

standard warranty. Production processing does not necessarily Include
testing of all parameters.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

Copyright © 1997, Texas Instruments Incorporated

3-31

TLC5615C, TLC56151
10·81T DIGITAL·TO·ANALOG CONVERTERS
SLASI42B-OCTOBER 1996- REVISED MARCH 1997

functional block diagram

REFIN

>-_--OUT
(Voltage Output)

AGND - - - - - -...-A,JIV'v--I
R

R

Control
Logic

CS
SCLK

DIN - - - - - - - + - 1
16-81t Shif,t Register

DOUT

Terminal Functions
TERMINAL
NAME

NO.

DESCRIPTION

1/0

DIN

1

I

Serial data input

SCLK

2

I

Serial clock input

CS

3

,I

Chip select, active low

DOUT

4

0

Serial data output for daisy chaining

AGND

5

REFIN

6

I

OUT

7

0

VDD

8

Analog ground
Reference input
DAC analog voltage output
Positive power supply

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage (VDD to AGND) ............................................................... 7 V.
Digital input voltage range to AGND .......................................... - 0.3 V to VDD + 0.3 V
Reference input voltage range to AGND .................................. ; ... - 0.3 V,to VDD + 0.3 V
Output voltage at OUT from external source ............................................ VDD + 0.3 V
Continuous current at any terminal ........................................................ ±20 mA
Operating free-air temperature range, TA: TLC5615C .................................... O°C to 70°C
TLC56151 ................................... -40°C to 85°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

~TEXAS

3-32

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5615C, TLC56151
10-81T DIGITAL-TO-ANALOG CONVERTERS
SLASI42B- OCTOBER 1996 - REVISED MARCH 1997

recommended operating conditions
MIN

NOM

MAX

Supply voltage, VOO

4.5

5

5.5

High-level digital input voltage, VIH

204
0.8
2

Load resistance, RL

2

Operating free-air temperature, TA

I TLC5615C
ITLC56151

V
V

Low-level digital input voltage, VIL
Reference voltage, Vref to REFIN terminal

UNIT

2.048

VOO-2

V
V

kn

0

70

°C

-40

85

°C

electrical characteristics over recommended operating free-air temperature range, Voo =5 V ±5%,
Vref 2.048 V (unless otherwise noted)

=

static OAC specifications
PARAMETER

MIN

TEST CONDITIONS

Resolution

EZS

EG

PSRR

Integral nonlinearity, end point adjusted (INL)

Vref = 2.048 V,

See Note 1

Differential nonlinearity (ONL)

Vrel = 2.048 V,

See Note 2

Zero-scale error (offset error at zero scale)

Vref = 2.048 V,

See Note 3

Zero-scale-error temperature coefficient

Vref = 2.048 V,

See Note 4

Gain error

Vref = 2.048 V,

See Note 5

Gain-error temperature coefficient

Vref = 2.048 V,

See Note 6

Power-supply rejection ratio
Analog full scale output

NOTES:

TYP

MAX

UNIT

±1

LSB

±0.5

LSB

10

IZero scale

IGain

bits

±0.1

±3

LSB
ppm/oC

3
±3

LSB
ppm/oC

1
80

See Notes 7 and 8

dB

80
RL= 100 kn

V

2Vref( 102311 024}

1. The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors (see text).
2. The differential nonlinearity (ONL), sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change 01 any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
•
3. Zero-scale error is the deviation from zero-voltage output when the· digital input code is zero (see text).
4. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (T max) - EZS (T min}]Nref x 106/(T max - T min).
5. Gain error is the deviation from the ideal output (Vref - 1 LSB) with an output load of 10 kn excluding the effects of the zero-scale
error.
6. Gain temperature coefficient is given by: EG TC = [EG(T max} - EG (T min)]Nref x 106/(T max - T min)·
7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VOO from 4.5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the zero-code output voltage.
8. Gain-error rejection ratio (EG-RR) is measured by varying the Voo from 4.5 V to 5.5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero-scale change.

voltage output (OUT)
PARAMETER

TEST CONDITIONS

Voltage output range .

RL = 10 kn

Output load regulation accuracy

VO(OUT) = 2 V,

lose

Output short circuit current

OUT to VOO or AGNO

VOL(lQw}

Output voltage, low-level

IO(OUT) 5: 5 mA

VOH(hiQh)

Output voltage, high-level

IO(OUT} 5: -5 mA

Vo

MIN

TYP

0

MAX
VOO-Oo4

RL = 2 kn

0.5
20

V
LSB
mA

0.25
4.75

UNIT

V
V

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-33

TLC5615C, TLC56151
10·81T DIGITAL·TO·ANALOG CONVERTERS
SLAS142B - OCTOBER 1996 - REVISED MARCH 1997

reference input (REFIN)
TEST CONDITIONS

PARAMETER
VI

Input voltage

q

Input resistance

Ci

Input capacitance

MIN

TYP

MAX

0

VDD-2

UNIT
V

Mn

10
5

pF

digital inputs (DIN, SCLK, CS)
Tt:ST CONDITIONS

PARAMETER
VIH

High-level digital input voltage

VIL

Low-level digital input voltage

IIH

High-level digital input current

IlL

Low-level digital input current

Ci

Input capacitance

MIN

TYP

MAX

2.4

UNIT
V

0.8

V

VI =VDD

±1

VI =0

±1

IJ.A
IJ.A

8

pF

digital output (DOUT)
TEST CONDITIONS

PARAMETER
VOH

Output voltage, high-level

lo=-2mA

VOL

Output voltage, low-level

lo=2mA

MIN

TYP

MAX

UNIT
V

VDD-l
0.4

V

power supply
PARAMETER
VDD

IDD

TEST CONDITIONS

Supply voltage

Power supply current

MIN

TYP

MAX

4.5

5

5.5

V

UNIT

VDD =5.5 V,
No load,
All inputs = 0 V or VDD

Vref= 0

150

250

flA

VDD= 5.5 V,
No load,
All inputs = 0 V or VDD

Vref = 2.048 V

230

350

flA

MAX

UNIT

analog output dynamic performance
PARAMETER

TEST CONDITIONS
Vref = 1 Vpp at 1 kHz + 2.048 Vdc,
code = 11 1111 1111,
See Note 9

Signal-to-noise + distortion, S/(N+D)

MIN

TYP

dB

60

NOTE 9: The limiting frequency value at 1 Vpp is determined by the output-amplifier slew rate.

digital input timing requirements (see Figure 1)
PARAMETER
tsu(DS)

Setup time, DIN before SCLK high

th(Df:ll

Hold time, DIN valid after SCLK high

tsu(CSS)

Setup time, CS low to SCLK high

tsu(CS1)

Setup time, CS high to SCLK high

th(CSHO)

MIN

NOM

MAX

UNIT

45

ns

0

ns

1

ns

50

ns

Hold time, SCLK low to CS low

1

ns

th(CSH1)

Hold time, SCLK low to CS high

0

ns

tw(CS)

Pulse duration, minimum chip select pulse width high

20

ns

tw(CL)

Pulse duration, SCLK low

25

ns

tw(CH)

Pulse duration, SCLK high

25

ns

~TEXAS

INSTRUMENTS
3--34

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5615C, TLC56151
10-81T DIGITAL-TO-ANALOG CONVERTERS
SLAS142B- OCTOBER 1996 - REVISED MARCH 1997

output switching characteristic
PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

50

operating characteristics over recommended operating free-air temperature range, VOO = 5 V ±5%,
Vref 2.048 V (unless otherwise noted)

=

analog output dynamic performance
PARAMETER

TEST CONDITIONS

SR

Output slew rate

CL = 100 pF,
TA = 25°C

ts

Output settling time

To 0.5 LSB,
RL= 10kn,

Glitch energy

DIN = All Os to all 1s

RL = 10 kil,
CL = 100 pF,
See Note 10

MIN

TYP

0.3

0.5

V/IlS

12.5

IlS

..

MAX

UNIT

nVos

5

NOTE 10: Settling time IS the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital Input code change of
000 hex to 3FF hex or 3FF hex to 000 hex.

reference input (REFIN)
PARAMETER

TEST CONDITIONS

Reference feedthrough

REFIN = 1 Vpp at 1 kHz + 2.048 Vdc (see Note 11)

Reference input
bandwidth (f-3dB)

REFIN = 0.2 Vpp + 2.048 Vdc

I

REF IN = 0.2 Vpp + 2.048 Vdc

MIN

TYP

MAX

UNIT

-BO

dB

30

kHz

NOTE 11: Reference feedthrough IS measured at the DAC output with an input code = 000 hex and a Vref Input = 2.048 Vdc + 1 Vpp at 1 kHz.

'!I1TEXAS

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-35

TLC5615C, TLC56151
10-81T DIGITAL-TO-ANALOG CONVERTERS
SLAS142B - OCTOBER 1996 - REVISED MARCH 1997

PARAMETER MEASUREMENT INFORMATION

\~

CS

____________

-

SCLK

~ ..

I..

th(CSHO)

I
I

~

i

__

)j-

" tsu(CSS)

I
I

I..

tw(CH)

I

.1..
I

.1

I

tw(CL)

-si.el(:e2N2ot2e ~AIo.--J I
tsu(DS)

~r~r

14~"~

th(CSH1) -.:

~
I

I

r-

tw(CS) ~

~

tsu(CS1)

~
See Note C

See Note A

th(DH)

~J-----l/'

DIN~"r---:------'l~~
tpd(DOUT)

-IIII'-~~.1

P_~_V_iO_U_S_LS_B_____J><

DOUT ______

See Note B

MSB

X'--_...JX'---_><;It-:_-JX,--_L__

SB_ _

NOTES: A" The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough.
B. Data input from preceeding conversion cycle.
C. Sixteenth SCLK falling edge

Figure 1. Timing Diagram

~TEXAS

INSTRUMENTS
3-36

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5615C, TLC56151
10·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS142B- OCTOBER 1996 - REVISED MARCH 1997

TYPICAL CHARACTERISTICS
OUTPUT SINK CURRENT

vs
OUTPUT PULLDOWN VOLTAGE
20
18
ct

E
I

C

~:I

...c
tJ

iii

'5

.e-:I

0

I

.9

t-

VIOO~5VI

V V

I

VREFIN = 2.048 V
16 _ TA = 25°C
14
12

/

10

/
o

/

V

6

2

V

/

8

4

/

./

V

/

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

1.1 1.2

Vo - Output Pulldown Voltage - V

Figure 2
OUTPUT SOURCE CURRENT

vs
OUTPUT PULLUP VOLTAGE
30

ct

E

I

25 -

I

I

I

VOO=5V
VREFIN = 2.048 V
TA=25°c

I

C
~
:I

V

20

V

tJ

III

!:!

:I

15

en0

'5

.e-:I

10

0

.9

J

5

o ........
5

/

/

.--- V '"

V

V

/

4.8 4.6

4.4 4.2

4

3.8 3.6 3.4

3.2

3

Vo - Output Pullup Voltage - V

Figure 3

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-37

TLC5615C, TLC56151
10-81T DIGITAL-TO-ANALOG CONVERTERS
SLAS142B - OCTOBER 1996 - REVISED MARCH 1997

TYPICAL CHARACTERISTICS
SUPPLY CURRENT

vs
TEMPERATURE
280
240

-

CC

::!.
I

'E
~::I

200
160

(J

~

a.

Co
::I

120

en
I

Q

E

80
VOO=SV
40 I-- VREFIN = 2.048 V
TA= 2S0C

o

i

-1

-60 -40 -20

-1

i

0 20 40 60 80
t - Temperature - °C

100 120 140

Figure 4
VREFIN

to V(OUT)

RELATIVE GAIN

4
2 t-

SIGNAL·TO·NOISE + DISTORTION

vs

vs

INPUT FREQUENCY

INPUT FREQUENCY AT REFIN
70

""
Voo = S'V
VREFIN = 0.2 Vpp + 2.048 V dc
TA=2SoC

0
III
'0
I

III
'0
I

I........

'0;

CJ

~

-4

SO

i

40

I ~~D=~vl III
I'\.

\ I\.

,

TA = 2SoC
VREFIN = 4 Vpp

[\

+

~

-6

I

-8

II>

III

'0

30

~
iiic

20

z

II:

CJ

c

~

-2

c

60

-10

~

'"

\

Cii

10

-12
-14

1

100

1k

10 k

100 k

o
1k

fl - Input Frequency - Hz

10 k

100 k

Frequency - Hz

Figure 5

Figure 6

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

300k

TLC5615C, TLC56151
10·81T DlGITAL·TO·ANALOG CONVERTERS
SLAS142B-OCTOBER 1996- REVISED MARCH 1997

TYPICAL CHARACTERISTICS
m

0.2,---------,-------,-------,-----------,

~ 0.15 f - - - - - - - + - - - - - - - : / - - - - - - - t - - - - - - - - i
I
~

0.1 f - - - - - - - - + - - - - - - - - , - : / - - - - - - - t - - - - - - - - i

·m

0.051-T-:-+-t-If--;--+-t-Hr--;---r-+-H-:I---::--+-t-+-Ih-.l-t-r-----r;:-:-1

Z

.NI. .WttMIHI"""..,. . . .,."""~

~

~.1f-------+-------+------r-------1

;:
o
.5

0

:§ -0.05

~ ~.15 f - - - - - - - + - - - - - - - + - - ' - - - - - - r - - - - - - - 1
is -0.2'--_ _ _ _ _--'-_ _ _ _ _---'--_ _ _ _ _ _'----_ _ _ _---'
255
511
767
1023
o
Input Code

Figure 7. Differential Nonlinearity With Input Code

m

0.8
0.6
I
0.4
.~

.5
0
;:
~
0
-0.2
z
(/l

....I

f

'"

!

A

_f"
..r"\J ~Vv

/V-

~-

-J"y

~
""'- \(¥AN
-.

..I'>.J-...Y
~.

~.4
~.6

.5 -0.8
-1

o

255

511

767

1023

Input Code

Figure 8. Integral Nonlinearity With Input Code

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-39

TLC5615C, TLC56151
10-81T DIGITAL-TO-ANALOG CONVERTERS
SLAS142B - OCTOBER 1996 - REVISED MARCH 1997

APPLlCATION INFORMATION
general function
The TLC5615 uses a resistor string network buffered with an op amp in a fixed gain of 2 to convert 1O-bit digital
data to analog voltage levels (see functional block diagram and Figure 9). The output of the TLC5615 is the
same polarity as the reference input (see Table 1).
An internal circuit resets the DAC register to all zeros on power up.
DIN

r---~--

SCLK

CS

DOUT

__ l_J __ L_l __,

I

~AN

I
I
I

I

I
I

I
I
I
I
I
I

AGND

OUT

I
I

VDD

~------~-[ ;=r=~~--~
-=

0.1 ~F

Figure 9; TLC5615 Typical Operating Circuit
Table 1. Binary Code Table (0 V to 2 VREFIN Output>, Gain = 2
INPUrt

OUTPUT

.

11(00)

1000

0000

01(00)

1000

0000

00(00)

0111

1111

11(00)

1111

1111

:

(
) 1023
2 VREFIN 1024

:
(
) 513
2 V REFIN 1024
(
) 512
2 VREFIN 1024 = VREFIN
(
) 511
2 VREFIN 1024

:

:

t

0000

0000

01(00)

0000

0000

00(00)

2(VREFIN)

OV

A 1O-bit data word with two bits below the LSB bit (sub-LSB) with 0 values
must be written since the DAC input latch is 12 bits wide.

~TEXAS

INSTRUMENTS

3-40

10~4

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC5615C, TLC56151
10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS142B - OCTOBER 1996 - REVISED MARCH 1997

APPLICATION INFORMATION
buffer amplifier
The output buffer has a rail-to-rail output with short circuit protection and can drive a 2-kQ load with a 100-pF
load capacitance. Settling, time is 12.5 Ils typical to within 0.5 LSB of final value.

external reference
The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore,
the REFIN input resistance is 10 MQ and the REFIN input capacitance is typically 5 pF independent of input
code. The reference voltage determines the DAC full-scale output.

logic interface
The logic inputs function with either TTL or CMOS logic levels. However, using rail-to-rail CMOS logic achieves
the lowest power dissipation. The power requirement increases by approximately 2 times when using TTL logic
levels.

serial clock and update rate
Figure 1 shows the TLC5615 timing. The maximum serial clock rate is:

f

(SCLK)max - tw(CH)

1

+

tW(CL)

or approximately 14 MHz. The digital update rate is limited by the chip-select period, which is:

tp(CS) = 16 x (tW(CH)

+ tW(CL)) + tw(CS)

and is equal to 820 ns which is a 1 .21 MHz update rate. However, the DAC settling time to 10 bits of 12.5 IlS
limits the update rate to 80 kHz for full-scale input step transitions.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-41

TLC5615C, TLC56151
10-81T DIGITAL-TO-ANALOG CONVERTERS
SLAS142B - OCTOBER 1996 - REVISED MARCH 1997

APPLICATION INFORMATION

serial interface
When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in most
significant bit first. The rising edge of the SLCK input shifts the data into the input register.
. The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot be clocked
into the input register. All CS transitions should occur when the SCLK input is low.
If the daisy chain (cascading) function (see daisy-chaining devices section) is not used, a 12-bit input data
sequence with the MSB first can be used as shown in Figure 10:
....- - - - - - - - - - - - - - - - - - 1 2 Bits - - - - - - - - - - - - - - - - - -••

x

10 Data Bits
MSB

II

x

2 Extra (Sub-LSB) Bits

LSB

x ,= don't care

Figure 10. 12-Bit Input Data Sequence
or 16 bits of data can be transferred as shown in Figure 11 with the 4 upper dummy bits first.
....- - - - - - - - - - - - - - - - - - 1 6 Bits - - - - - - - - - - - - - - - - - -••
4 Upper Dummy Bits

10 Data Bits

II
MSB

II
LSB

x

II

x

2 Extra (Sub-LSB) Bits

x = don't care

Figure 11. 16-Bit Input Data Sequence
The data from DOUT requires 16 falling edges of the input clock and, therefore, requires an extra clock width.
When daisy chaining multiple TLC5615 devices, the data requires 4 upper dummy bits because the data
transfer requires 16 input-clock cycles plus one additional input-clock falling edge to clock out the data at the
DOUT terminal (see Figure 1).
The two extra (sub-LS8) bits are always required to provide hardware and software compatibility with 12-bit data
converter transfers.
The TLC5615 three-wire interface is cO[Tlpatible with the SPI, aSPlt, and Microwire serial standards. The
hardware connections are shown in Figure 12 and Figure 13.
The SPI and Microwire interfaces transfer data in 8-bit bytes, therefore, two write cycles are required to input
data to the DAC. The aSPI interface, which has a variable input data length from 8 to 16 bits, can load the DAC
input register in one write cycle.

t

CPOL

=0, CPHA =0, aSPI protocol designations

~TEXAS

3-42

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5615C, TLC56151
10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS142B - OCTOBER 1996 - REVISED MARCH 1997

APPLICATION INFORMATION

serial interface (continued)
SK

SClK

SO Microwire
Port

DIN
TlC5615
CS

~

I/O
SI

DOUT

NOTE A: The DOUT-SI connection is not required for writing
to the TLC5615 but may be used for verifying data
transfer if desired.

Figure 12. Mlcrowire Connection
SClK
DIN
TlC5615

....

SCK

,

MOSI

CS
DOUT

I/O

SPI/QSPI
Port

MISO
CPOl = 0, CPHA =0

NOTE A: The DOUT-MISO connection is not required for
writing to the TLC5615 but may be used for verifying
data transfer.

Figure 13. SPI/QSPI Connection

daisy-chaining devices
DACs can be daisy-chained by connecting the DOUT terminal of one device to the DIN of the next device in
the chain, providing that the setup time, tsu(CSS), (CS low to SCLK high) is greater than the sum of the setup
time, tsu(DS), plus the propagation delay time, tpd(DOUT), for proper timing (see digital input timing requirements
section). The data at DIN appears at DOUT, delayed by 16 clock cycles plus one clock width. DOUT is a
totem-poled output for low power. DOUT changes on the SCLK falling edge when CS is low. When CS is high,
DOUT remains at the value of the last data bit and does not go into a high-impedance state.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-43

TLC5615C, TLC56151
10-81T DIGITAL-TO-ANALOG CONVERTERS
SLAS142B - OCTOBER 1996 - REVISED MARCH 1997

APPLICATION INFORMATION

linearity, offset, and gain error using single ended supplies
When an amplifier is operated froin a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage
may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage,; resulting in the transfer function shown in Figure 14.

Output
Voltage

o V 1---.,;£=-----------+
Negative {
Offset

DACCode

Figure 14. Effect of Negative Offset (Single Supply)

This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage. For the
TLC5615, the zero-scale (offset) error is plus or minus 3 LSB maximum. The code is calculated from the
maximum specification for the negative offset.
.

~TEXAS

3-44

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5615C, TLC56151
10-81T DIGITAL-TO-ANALOG CONVERTERS
SLAS142B - OCTOBER 1996 - REVISEO MARCH 1997

APPLICATION INFORMATION
power-supply bypassing and ground management
Printed circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane making sure that analog ground
currents are well managed and there are negligible voltage drops across the ground plane.
A O.1-!,lF ceramic-capacitor bypass should be connected between Vooand AGND and mounted with short leads
as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the
digital power supply.
Figure 15 shows the ground plane layout and bypassing technique.

Figure 15. Power-Supply Bypassing

saving power
Setting the DAC register to all Os minimizes power consumption by the reference resistor array and the output
load when the system is not using the DAC.

ac considerations
digital feedthrough
Even with CS high, high-speed serial data at any of the digital input or output terminals may couple through the
DAC package internal stray capacitance and appear at the DAC analog output as digital feedthrough. Digital
feedthrough is tested by holding CS high and transmitting 0101010101 from DIN to DOUT.
analog feedthrough
Higher frequency analog input signals may couple to the output through internal stray capacitance. Analog
feedthrough is tested by holding CS high, setting the DAC code to all Os, sweeping the frequency applied to
REFIN, and monitoring the DAC output.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-45

TLC5616C, TLC56161
2.7 V TO 5.5 V LOW POWER 12·BIT DIGITAL·TO·ANALOG
CONVERTERS WITH POWER DOWN
•
•

•
•
•

•

•

12·Bit Voltage Output DAC
Programmable Settling Time vs Power
Consumption
2.5 /lS in Fast Mode
8.2 /lS in Slow Mode
Compatible With TMS320 and SPI Serial
Ports
Differential Nonlinearity ... <0.5 LSB Typ
Ultra Low Power Consumption:
600 /lW Typ in Slow Mode
1.74 mW Typ in Fast Mode at 3 V
Buffered High-Impedance Reference Input

•

Voltage Output Range ... 2 Times the
Reference Input Voltage
Monotonic Over Temperature

applications
•
•
•
•
•

Digital Servo Control Loops
Digital Offset and Gain Adjustment
Industrial Process Control
Machine and Motion Control Devices
Mass Storage Devices

description

o OR PW PACKAGE

The TLC5616 is a 12-bit voltage output
digital-to-analog converter (DAC) with a flexible
4-wire serial interface. The 4-wire serial interface
allows seamless interface to TMS320 and SPI,
aSPI, and Microwire serial ports. The TLC5616 is
programmed by writing a 16-bit serial string into
the device with four programming bits and 12 data
bits. Developed for a wide range of supply
voltages, the TLC5616 can operate from 2.7 V to

(TOP VIEW)

D1NUa

SClK
CS

2
3

7
6

FS

4

5

VDD

3:
w

OUT
REF

GND

:>
w
a:
c..

5.5V.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer operates with a
Class A output stage to improve stability and reduce settling time. The settling time of the DAC is programmable
to allow the designer to optimize settling time versus power dissipation. The settling time of the DAC is easily
toggled by programming one of the 16 bits loaded along with the data. A high-impedance buffer is integrated
on the REF terminal to reduce the need to use a low source impedance drive to the terminal.
Implemented with a CMOS process, the TLC5616 is designed for single supply operation from 2.7 V to 5.5 V.
The device is available in 8 terminal SOIC and TSSOP packages to reduce board space and is available in
standard commercial and industrial temperature ranges. The TLC5616C is characterized for operation from O°C
to 70°C. The TLC56161 is characterized for operation from -40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA
O°C

to 70°C
to 85°C

-40°C

t

SMALL OUTLlNEt
(0)

SMALL OUTLINE
(PW)

TLC5616CD

TLC5616CPW

TLC56161D

TLC56161PW

Available In tape and reel as the TLC5616CDR and the TLC56161DR

PRODUCT PREVIEW information concerns products in the formative or
phase of development. Characteristic data and other

desi~n

specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notlce.

~TEXAS

Copyright © 1997. Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-47

I-

o
::)
c

oa:
c..

TLC5616C, TLC56161
2.7 V TO 5.5V LOW POWER 12·81T DIGITAL·TO·ANALOG
CONVERTERS WITH POWER DOWN
SLASI52- DECEMBER 1997

functional block diagram

~

6
REF

DIN

SCLK
CS
FS

~

12

Serial Input
Register

1

2
Update

16 Cycle
Timer

3
4

~~
,/

12-81t
Data
Latch

I

2

-=-

/

2

Power-Up
Reset

Speed/Power-Down
Reset

;:
w

5'

Terminal Functions

w
a..

TERMINAL

a:

NAME
CS

I-

o

~

c
oa:
a..

NO.

3

I/O

DESCRIPTION.

I

Chip select. Digital output used to enable and disable inputs,
active low.

DIN

1

I

Serial digital data input

FS

4

0

Frame sync. Digital input used for 4-wire serial interfaces
such as the TMS320 DSP interface.

GND

5

OUT

7

0

REF

6

I

Reference analog input voltage

SCLK

2

I

Serial digital clock input

VDD

8

Analog ground
DAC analog output

Positive power supply

~ThXAS

3-48

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

OUT

TLC5616C, TLC56161
2.7 V TO 5.5 V LOW POWER 12·81T DIGITAL·TO·ANALOG
CONVERTERS WITH POWER DOWN
SLAS152 - DECEMBER 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage (Voo to AGND) ..........................................................' ..... 7 V
Reference input voltage range ............................................... - 0.3 V to Voo + 0.3 V
Digital input voltage range .................................................. - 0.3 V to Voo + 0.3 V
Operating free-air temperature range, TA: TI.,C5616C .................................... O°C to 70°C
TLC56161 ................................... -40°C to 85°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

Supply voltage, VDD

MIN

NOM

MAX

5V

4.5

5

5.5

V

3V

2.7

3

3.3

V

VDD

Low-level digital input voltage, V,L

VDD

Reference voltage, Vrefto REFIN terminal

5V

GND

Reference voltage, Vref to REFIN terminal

3V

GND

0.8

V

2.048

VDD-1.1

V

1.024

VDD-1.1

V

100

Load capacitance, CL
TLC5616C
TLC56161

3:
w

kQ

2

Load resistance, RL

Operating free-air temperature, TA

V

2

High-level digital input voltage, V,H

UNIT

pF

0

70

°C

'-40

85

°C

:>
w
a:
a..
I-

o

~

c

oa:
a..

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-49

TLC5616C, TLC56161
2.7 V TO 5.5 V LOW POWER 12·81T DIGITAL·TO·ANALOG
CONVERTERS WITH POWER DOWN
SLAS152- DECEMBER 1997

electrical characteristics over recommended operating free·air temperature range, Voo = 5 V ± 10%,
=3 V± 10%, Vref =2.048 V, Vref =1.024 V (unless otherwise noted)

VOO

static OAC specifications
PARAMETER

EZS

EG

s:w

:>
w
a:

c..

TEST CONDITIONS

See Note 1

±3

LSB

Differential nonlinearity (DNL)

Vref = 2,048 V,
1,024V

See Note 2

±O,5

LSB

Zero-scale error (offset error at
zero scale)

Vref = 2,048 V,
1,024V

See Note 3

±12

LSB

Zero-scale-error temperature
coefficient

Vref = 2,048 V,
1,024V

See Note 4

Vref = 2,048 V,
1,024V

See Note 5

Vref = i048 V,
1,024V

See Note S

5V

See Notes 7 and 8

' -SI

dB

See Notes 7 and 8

--49

dB

- Gain error

Power supply rejection ratio

Zero scale n
Full scale
Zero scale

3V

t-

:::J
C

oa:

c..

12

bits

3

ppm;oC

±O,29

1

%of
FSvoltage
ppm/oC

See Notes 7 and 8

--45

dB

See Notes 7 and 8

--49

dB

1, The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors (see text),
2, The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change ,of any two adjacent codes, Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code,
3, Zero-scale error is the deviation from zero voltage output when the digital input code is zero (see text),
4, Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (T max) - EZS (T min))/Vref x 1OS/(Tmax - Tmin),
5, Gain error is the deviation from the ideal output (Vref -1 LSB).with an output load of 10 k!l excluding the effects of the zero-error,
S, Gain temperature coefficient is given by: EG TC = [EG(T max) - EG (T min))/Vref x 1OS/(T max - T min),
7, Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4,5 V to 5,5 V dc and measuring the proportion of
this signal imposed on the zero-code output voltage,
S. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4,5 V to 5,5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero scale change,

~TEXAS

INSTRUMENTS
3-50

UNIT

Vref = 2,048 V,
1,024V

Full scale

O

MAX

Integral nonlinearity (INL), end
point adjusted

-

NOTES:

TYP

Vref = 2,048 V, 1,024V

Gain error temperature coefficient

PSRR

MIN

Resolution

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5616C, TLC56161
2.7 V TO 5.5 V LOW POWER 12·BIT DIGITAL·TO·ANALOG
CONVERTERS WITH POWER DOWN
SLAS152 - DECEMBER 1997

=

electrical characteristics over recommended operating free-air temperature range, Voo 5 V
± 10%,Voo 3 V ± 10%, Vref 2.048 V, Vref 1.024 V (unless otherwise noted) (Continued)

=

=

=

output specifications
PARAMETER

Vo

TEST CONDITIONS

Output voltage

RL=2kQ

Output load regulation accuracy

VO(OUT) = 4.096 V,
2.048 V

MIN

TYP

MAX

VOO-O·I

UNIT

V
%of
FS
Voltage

RL=2kQ

IOSC

Output short circuit current

IO(sink)

Output sink current

20

rnA
rnA

IO(source)

Output source current

rnA

reference input (REF)
PARAMETER

VI

Input voltage

Ri

Input resistance

Ci

Input capacitance

MIN.

TEST CONDITIONS

TVP

0

MAX

VOo-l.1

pF

5

Harmonic distortion, reference
input

Reference feedthrough

REFIN = 0.2 Vpp + 1.024 V dc

V
MQ

10

Reference input bandwidth

UNIT

Fast

1.3

MHz

Slow

525

kHz

REFIN = 1 Vpp + 1.024 V dc, frequency = 10kHz

Fast

-73

dB

REFIN = I Vpp + 1.024 V dc, frequency = 100 kHz

Fast

-51

dB

REFIN = 1 Vpp + 1.024 V dc, frequency = 200 kHz

Fast

-36

dB

REFIN = 1 Vpp + 1.024 V dc, frequency = 10kHz

Slow

-78

dB

REFIN = 1 Vpp + 1.024 V dc, frequency = 50 kHz

Slow

-41

dB

-80

dB

REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 9)

NOTE 9: Reference feedthrough is measured at the OAC output with an input code = 000 hex and a Vref input = 1.024 V dc + 1 Vpp at 1 kHz.

digital inputs
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNfT

IIH

High-level digital input current

VI =VOO

±1

~

IlL

LOW-level digital input current

VI=OV

±I

~

Ci

Input capacitance

pF

8

power supply
PARAMETER

VOO = 5 V, No load, All inputs = 0 V or VOO
IDO

TVP

MAX

Fast

0.67

1

Slow

0.28

0.4

rnA

Fast

0.58

0.9

rnA

Slow

0.20

0.30

rnA

0.18

0.30

~

TEST CONDITIONS

Power supply current
VOO = 3 V, No load, All inputs = 0 V or VOO
Power down supply current

MIN

UNIT

rnA

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265

3-51

:=w
5>
w
a:
a.
~

o

::l
C

oa:
a.

TLC5616C, TLC56161
2.7 V TO 5.5 V LOW POWER 12-81T DIGITAL-lO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS152 - DECEMBER 1997

operating characteristics over recommended operating free-air temperature range, VDD
10%, Vref 2.048 V, (unless otherwise noted)

=

=5 V ±

analog output dynamic performance
PARAMETER

ts(FS)

ts(CC)

TEST CONDITIONS

MAX

2.5

3.9

UNIT

Slow

8.2

18.1

!1S

Fast

3.2

5.3

!is

Slow

5.7

20.4

!is

VDD = 3 V, To 0.5 LSB,
RL= 10kn,

CL = 100 pF,
See Note 10

VDD = 5 V, To 0.5 LSB,
RL= 10kn,

CL = 100 pF,
See Note 11

Fast

!is

Slow

!is

VDD = 3 V, To 0.5 LSB,
RL= 10kn,

CL = 100 pF,
See Note 11

Fast

!is

Slow

Output settling time, full scale

Output settling time, code to code

Output slew rate
VDD = 3 V, To 0.5 LSB, CL = 100 pF,
RL= 10kn,

3:
w

MIN

CL = 100 pF,
See Note 10

VDD = 5 V, To 0.5 LSB, CL = 100 pF,
RL= 10kn,
SR

TYP

Fast

VDD = 5 V, To 0.5 LSB,
RL = 10 k.Q,

!is

!1S

Fast

3

Slow

0.6

V/!iS

Fast

2.8

V/!iS

Slow

0.6

V/!iS

V/!iS

Signal to noise + distortion,
S/(N+D)

dB

w

NOTES: 10. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of 000 hex to 3FF hex or 3FF hex to 000 hex.
11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count.

0.

digital input timing requirements

5>

a:
I-

o

::l
C

oa:
0.

MIN

NOM

MAX

UNIT

tsu(C8-FS}

Setup time, CS low before FS!

10

ns

tsu(Fs-GLK}

Setup time, FS low before first negative SCLK edge

10

ns

tsu (Cl6-FS)

Setup time, sixteenth negative edge after FS low on which bit DO is sampled before
rising edge of FS

10

ns

tsu(Cl6-CS)

Setup time, sixteenth positive CLK edge (first positive after DO is sampled) before CS
rising edge. Or is FS is used instead of sixteenth positive edge to update DAC, then
setup time between FS rising edge and CS rising edge.

10

ns

lwH

Pulse duration, SCLK high

25

ns

twL

Pulse duration, SCLK low

25

ns

lsu(D)

Setup time, data ready before SCLK falling edge

8

ns

thLQl.

Hold time, data held valid after SCLK falling edge

5

ns

Id(CS1)

Delay time, positive clock edge after DO sampled to internal latch (and shift register)
control high

~TEXAS

INSTRUMENTS
3-52

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

!is

TLC5616C, TLC56161
2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS152- DECEMBER 1997

PARAMETER MEASUREMENT INFORMATION
~I
I..
I4----*- tsu(CS-FS)
tsU(C16-CS)
I
I
~~I_______________________________________________________________________________________________~
I __________- J
CS\
:
I
1.. 1
~
I
tsu(C16-FS) ----1~---'
I I
I I
FS
I I
I
I I
---.I 14-- tsu(FS-CK)
I I
I I
I
x
SCLK
X

y---

I

~--------------------------------------~-r--~)I

DIN

In~:~~
Control

X

\

X

I
I

:=

I I

td(CSI)~

r

w
. . . . ____________________________________--',,...--------- :>
w
a:

Figure 1. Timing Diagram

0..

I-

o

::l
C

oa:
0..

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-53

;:
w

5>
w
a:

D..

I-

o

:::J
Q

oa:

D..

3-54

TLC5617,TLC5617A
PROGRAMMABLE DUAL 1O-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151A-JULY 1997 - REVISED DECEMBER 1997

•
•

•
•
•
•
•
•
•

Programmable Settling Time to 0.5 LSB
2.5 JlS or 12.5 Jls Typ

•

TMS320 and SPI Compatible

•

Low Power Consumption:
3 mW Typ in Slow Mode
8 mW Typ in Fast Mode

Two 10-Bit CMOS Voltage Output DACs in
an 8 Pin Package
Simultaneous Updates for DAC A
and DAC B

•

Input Data Update Rate of 1.21 MHz

•

Monotonic Over Temperature

Single Supply Operation
applications

3-Wire Serial Interface
High-Impedance Reference Inputs

•

Battery Powered Test Instruments

Voltage Output Range . .. 2 Times the
Reference Input Voltage

•

Digital Offset and Gain Adjustment

•

Battery Operated/Remote Industrial
Controls

•

Machine and Motion Control Devices

•

Cellular Telephones

Software Power Down Mode
Internal Power-On Reset

D OR P PACKAGE
(TOP VIEW)

description
The TLC5617 and TLC5617A are dual 10-bit
voltage output digital-to-analog converters (DAC)
with buffered reference inputs (high impedance).
The DACs have an output voltage range that is
two times the reference voltage, and the DACs are
monotonic. The device is simple to use, running
from a single supply of 5 V. A power-on reset
function is incorporated to ensure repeatable
start-up conditions.

DINDs

SCLK
CS
OUT A

VDD

2

7

OUT B

3
4

6
5

AGND

REFIN

Digital control of the TLC5617 is over a 3-wire CMOS compatible serial bus. The device receives a 16-bit word
for programming and to produce the analog output. The digital inputs feature Schmitt triggers for high noise
immunity. Digital communication protocols include the SPITM, QSPITM, and Microwire™ standards.
Two versions of this device are available. The TLC5617 does nothave any internal state machine and is
dependent on all external timing signals. The TLC5617 A has an internal state machine that will count the
number of clocks from falling edge of CS and then update and disable the device to accepting further data inputs.
The TLC5617 A is recommended for TMS320 and SPI processors and the TLC5617 is recommended only for
use in SPI or 3-wire serial port processors. The TLC5617 A is backward compatible and designed to work in
TLC5617 designed systems.
The 8-terminal small-outline 0 package allows digital control of analog functions in space-critical applications.
The TLC5617C is characterized for operation from O°C to 70°C. The TLC56171 is characterized for operation
from -40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and aSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.

~~~~:~~fo~:l: s~~~~~~~i;e~~~:~r~~ :: 1e~~~!~~m~~f8

standard warranty. Production processing does not necessarily include
testing of all parameters.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright © 1997, Texas Instruments Incorporated

3-55

TLC5617, TL.C5617A
PROGRAMMABLE DUAL 10-81T DIGITAL-TO-ANALOG CONVERTERS
SLAS151A-JULY 1997-REVISED DECEMBER 1997

AVAILABLE OPTIONS
PACKAGE
SMALL OUTLlNEt
(D)

TA

PLASTIC DIP
(P)

O'C to 70'C

TLC5617CD
TLC5617ACD

TLC5617CP
TLC5617ACP

-40'C to 85°C

TLC56171D
TLC5617AID

TLC56171P
TLC5617AIP

t Available In fape and reel as the TLC5617CDR and the TLC56171DR
DEVICE

COMPATIBILITY

TLC5617

SPI, aSPI and Microwire

TLC5617A

TMS320Cxx, SPI, aSPI and Microwire

functional block diagram

6

REFIN --e------,I

7

OUTA
(Voltage Output)

5

AGND

--=--IT--;::::==:;--~~

CS --=3_+-+-_-1

Control
Logic

......_..,......

SCLK ~2~+-~~-1
DIN

----'--+-+-f---+-+--f___.....

>-...._4

R

~TEXAS

3-56

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

R

OUTB
(Voltage Output)

TLC5617, TLC5617A
PROGRAMMABLE DUAL 10·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS151A- JULY 1997 - REVISED DECEMBER 1997

Terminal Functions
TERMINAL
NAME

NO.

1/0

DESCRIPTION

OIN

1

I

SCLK

2

I

Serial data input
Serial clock input

CS

3

I

Chip select, active low

OUTB

4

0

AGNO

5

OAC B analog output
Analog ground

REFIN

6

I

OUTA

7

0

VOD

8

Reference voltagll input
OAC A analog output
Positive power supply

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage (Voo to AGND) ............................................................... 7 V
Digital input voltage range to AGND .......................................... - 0.3 V tQ Voo + 0.3 V
Reference input voltage range to AGND ...................................... - 0.3 V to Voo + 0.3 V
Output voltage at OUT from external source ............................................ Voo + 0.3 V
Continuous current at any terminal ........................................................ ±20 mA
Operating free-air temperature range, TA: TLC5617C .................................... O°C to 70°C
TLC56171 ................................... -40°C to 85°C
Storage temperature range, Tstg .................................... ; .............. -65°C to 150"C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260"C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions
Supply voltage, VOO
High-level digital input voltage, VIH
Low-level digital input voltage, VIL

IVOO =5V
IVOO =5 V

MIN

NOM

MAX

4.5

5

5.5

0'.3 VOO
1

Load resistance, RL

2

Operating free-air temperature, TA

ITLC5617C

ITLC56171

V

V

0.7VOO

Reference voltage, Vref to REFIN terminal

UNIT

2.048

VOO-1.1

V
V
kQ

0

70

'C

-40

85

'C

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-57

TLC5617, TLC5617A
PROGRAMMABLE DUAL 10·BIT DIGITAL·TO·ANALOG CONVERTERS
SLASI51A-JULY 1997 - REVISED DECEMBER 1997

electrical characteristics over recommended operating free-air temperature range, Voo =5 V ± 5%,
Vref (REFIN)= 2.048 V (unless otherwise noted)
static OAe specifications
PARAMETER

TEST CONDITIONS

MIN

Resolution

EZS
EG

Integral nonlinearity (INL), end point adjusted

Vref(REFIN) = 2.048 V,

See Note 1

Differential nonlinearity (DNL)

VreflREFIN) = 2.048 V,

See Note 2

Zero-scale error (offset error at zero scale)

Vref(REFIN) = 2.048 V,

See Note 3

MAX

UNIT

±1

LSB

±0.5

LSB

Zero-scale-error temperature coefficient

Vref(REFIN) = 2.048 V,

See Note 4

Gain error

Vref(REFIN) = 2.048 V,

See Note 5

Gain error temperature coefficient

Vref(REFIN) = 2.048 V,

See Note 6

Power-supply rejection ratio

bits
±0.1

±3
3.

LSB
ppmfOC

±3
1

Zero scale
PSRR

TYP

10

LSB
ppm/'C

80
Slow

Gain

80

See Notes 7 and 8

Zero scale

dB

80
Fast

Gain

80

NOTES: 1. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
2. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (T max) - EZS (T min)]Nref x 106/(T max - T min).
5. Gain error is the deviation from the ideal output (Vref - 1 LSB) with an output load of 10 k.Q excluding the effects of the zero-error.
6. Gain temperature coefficient is given by: EG TC = [EG(T max) - EG (T min)]Nref x 106/(T max - Tmin).
7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the zero-code output voltage.
8. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero scale change.

A OUT and B OUT output specifications
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

0

UNIT

V

Voltage output range

RL= 10 kn

Output load regulation accuracy

VO(OUT) = 2V,

IOSC

Output short circuit current

VO(A OUT) or VO(B OUT) to VDD or AGND

IO(sink)

Output sink current

VO(OUT) > 0.25 V

5

mA

IO(source)

Output source current

VO(OUT) < 4.75 V

5

mA

Vo

VDD-O.4

RL from 10 kn to 2 kn

0.5
20

LSB
mA

reference input (REFIN)
PARAMETER

VI

Input voltage range

Ri

Input resistance

Ci

TYP

0

Input capacitance
REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 9)

Reference input bandwidth (f-3dB)

REFIN = 0.2 Vpp + 1.024 V dc

IS

MAX

VDD-2

10

Reference feedthrough

NOTE 9: Reference feedthrough
kHz.

UNIT

V
Mn

5

pF

-80

dB

ISlow

0.5

I Fast

1

MHz

measured at the DAC output with an input code = 00 hex and a Vref(REFIN) Input = 1.024 V dc + 1 Vpp at 1

"'TEXAS
INSTRUMENTS
3-58

MIN

TEST CONDITIONS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLASI51A-JULY 1997 - REVISED DECEMBER 1997

electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ±5%,
Vref (REFIN)= 2.048 V (unless otherwise noted) (continued)
digital inputs (DIN, SCLK, CS)
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IIH

High-level digital input current

VI =VDD

±1

IlA

IlL

Low-level digital input current

VI=OV

±1

IlA

Ci

Input capacitance .

8

pF

power supply
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

4.5

5

5.5

Slow

0.6

1

Fast

1.6

2.5

Supply voltage, VDD
IDD

VDD= 5.5 V,
No load,
All inputs = 0 V or VDD

Power supply current
Power down supply current

=

free~air

V
mA

D13 = 0 (see Table 3)

operating characteristics over recommended operating
Vref(REFIN) 2.048 V (unless otherwise noted)

UNIT

I!A

1

temperature range, VDD = 5 V ±5%,

analog output dynamic performance
PARAMETER
SR

ts

ts(c}

S/(N+D}

MIN

TYP

CL = 100 pF,
RL = 10 kQ,
Code 32 to Code 1024,

TEST CONDITIONS
Vref(REFIN} = 2.048 V,
TA = 25°C,
Vo from 10% to 90%

Slow

0.3

0.5

Fast

2.4

3

To ±0.5 LSB,
RL=10kQ,

CL = 100 pF,
See Note 10

Slow

12.5

Fast

2.5

Output settling time,
code to code

To±0.5 LSB,
RL= 10kn,

CL = 100 pF,
See Note 11

Slow

2

Fast

2

Glitch energy

DIN = All Os to allis,
f(SCLK} = 100 kHz

CS=VDD,

Signal to noise + distortion

Vref(REFIN) = 1 Vpp at 1 kHz and 10 kHz + 1.024 V dc,
Input code = 10 0000 0000

Output slew rate

• Output settling time

MAX

UNIT
VIliS

1!5
liS
nV-s

5
Slow

78

Fast

81

dB

NOTES: 10. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of 020 hex to 3FF hex or 3FF hex to 020 hex.
11. Setting time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of one count.

digital input timing requirements
MIN

NOM

MAX

UNIT

tsu(DS)

Setup time, DIN before SCLK low

5

ns

th(DH)

Hold time, DIN valid after SCLK low

5

ns

5

ns

10

ns

5

ns
ns

tsu(CSS}

Setup time, CS low to SCLK low

tsu(CS1)

Setup time, SCLK t to CS

tsu(CS2)

Setup time, SCLK t

t",(CL)

Pulse duration, SCLK low

25

tw(CH)

Pulse duration, SCLK high

25

Id(CS1}

Delay time, CLKt to Disable (TLC5617A only)

J., external end-of-write
to CS J., start of next write cycle

ns
5

ns

~TEXAS

INSTRUMENTS
POST OFFice BOX 655303 • DALLAS, TeXAS 75265

3-59

TLC5617,TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151A-JUlY 1997 - REVISED DECEMBER 1997

I

\~----------------~\~\--~~~~~
:.--.:- tSU(CSS)

I

(see Note A)

m<

.:

~

.1'"
D15

th(DH)

X

I
I

X

D14

X

D13

D12

I

I..

:

~

:

I0Il

tsu(DS)

:

1'- t~u(CS2) -+1

I

I

SCLK

DIN

tSIi(CS1):'"

tw(CL)

Program Bits (4)

V;;~O ~~~~~~~~
~r-.:...

I

DAC Data
Bits (12)

I

--.!- I

1.-I

t ---.:
s
I

DACO~~ ______________________________________________________-J:~-;3I:s; Final Value ±O.5 LSB
NOTE B: The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough.

Figure 1. Timing Diagram for the TLC5617
Internally Generated
Disable at This Time

td(CS1)

"1

----.I

~

\~------------------~\\\~--~!*~~~
~t
I~"I

su(CSS)

tsu(CS1)

tw(CL) -I41---.~I....-~I
I I

SCLK

I (see Note A)

-~
DIN ~
~
I
I
I

DACO~~ ~!

III
I
I I ·1
I
14-t- t"u(CS2) -+I

~II
I I
I I
I I

:

~. ~ '~DH)
D15)(

D14

_D_12_>0S~

X. .

_D_1_3---JX....

I

I...

tw(CH)

I
I'"
I

I I

DO

I

Program Bits (4)

-------I~~II-

~,.,'rlo~0'I::"0'I::"~~
I

DAC Data
Bits (12)

-..!- I

________________________________________________

I

(see Note A)

I

i4--I

t

s

--J~ ~
:s; Final Value ±O.5 LSB

NOTE C: Tile input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough.

I
Figure 2. Timing Diagram for TLC5617A only

~TEXAS

3-60

--+-.:
I I

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5617, TLC5617A
PROGRAMMABLE DUAL 10·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS151 A - JULY 1997 - REVISED DECEMBER 1997

TYPICAL CHARACTERISTICS
OUTPUT SINK CURRENT (FAST MODE)

OUTPUT SOURCE CURRENT (FAST MODE)

vs

vs

OUTPUT LOAD VOLTAGE
40
35

E
I

'E
~::I

25

'S
Do
'S

0

5

~ -40

\

~ -30

i~

/

1

1.5

2

2.5

I

I

I

3

3.5

4

1\

-20

\

-10

Vcc= 5V
Input Code = 0

0
0.5

o
o

4.5

0.5

Output Load Voltage - V

'E
~
::I

...c

(,)

vs
OUTPUT LOAD VOLTAGE

cC

E
I

'E -20
~
::I

~

4

4.5

..

\\
l1

(,)

J

f

-1 5

\

::I

in
'S

- r- ~

-25

/
If

o

~

3.5

OUTPUT LOAD VOLTAGE

1/

5

3

OUTPUT SOURCE CURRENT (SLOW MODE)

-3 0

E

2.5

vs
25

cC

2

Figure 4

OUTPUT SINK CURRENT (SLOW MODE)

I

1.5

Output Load Voltage - V.

Figure 3

20

~

(3

/

10

.........

)

I

/

15

in

-50

E

If

(,)

VOO=5 V
Input Code = 4095

r--

cC

J

20

...c

-60

v

/

30

cC

OUTPUT LOAD VOLTAGE

0

I/)

5 /

'[ -1 0

'S

0

0
0

-5

Voo=5 V
Input Code = 0
...{)

o

0.5

1.5

2

2.5

3

3.5

4

Voo =5V
Input Code = 4095
4.5

0

o

0.5

Output Load Voltage - V

1.5

2

2.5

3

3.5

4

4.5

Output Load Voltage - V

Figure 5

Figure 6

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-61

TLC5617,TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151A-JULY 1997 - REVISED DECEMBER 1997

TYPICAL CHARACTERISTICS
SUPPLY CURRENT

1.4

t--

1.2

RELATIVE GAIN (FAST MODE)

vs

vs

TEMPERATURE

FREQUENCY
5

I
I
I
I
VOO =5 V
VREFIN = 2.048 V
TA = 25'C

0

r-r-

I\.

\

I

Fast Mode

oQ;

-5
In

E
I

C

~

"

"

..

-15

0.6

.2:

~
II:

0.4

,

~

-20

Slow Mode

VCC=5V
-25 f- VREFIN = 0.2 Vpp + 2.048 Vdc

0.2

o

TA

-30

-60 -40 -20

0

20 40 60 80
Temperature - 'C

100 120 140

i

25'f I I I 111I

100

o

Figure 8

-5

"c

vs

FREQUENCY

FREQUENCY

IIVcc=15V I

~

I'

95

I I I I

VREFIN = 0.2 Vpp +
2.048Vdc
TA = 25'C

In

"cI

-1 5

.~

-20

&!

-25

1ii

~.

85

'"'\

c

.2
c

~
~

0

80

E

a
:x:
]I
~

1000

75

I

1,

-35
100

~

l1

-30

-40

90

0

:e0

-10

I

~

TOTAL HARMONIC DISTORTION (SLOW MODE)

vs

I-

C

:x:

I-

10 K

70

65

1

f - Frequency - kHz

~
V

10
f - Frequency - kHz

Figure 9

Figure 10

~TEXAS

INSTRUMENTS
3-62

10 K

f - Frequency - kHz

RELATIVE GAIN (SLOW MODE)

5

,

J

1000

Figure 7

In

\

1\

c:J

CL

If)

-10

I

c
.;

(J

>i5..

"

0.8

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

100

TLC5617,TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151A- JULY 1997 - REVISED DECEMBER 1997

TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION + NOISE (SLOW MODE)

In

SIGNAl-TO-NOISE RATIO (SLOW MODE)

vs

vs

FREQUENCY

FREQUENCY

85

85

"c:s
I

.

,!!!
0

z

"c:s

I

c

0

..

a:

75

'0

'2
0
E

/!.

z

u

75

'"

iii

S
I

'\

ic

70

:r:
~

...........

III

is

:;;

80

:;

0

~-;;

~- ..,-

In

80

+

I

a:

z

65

70

en

z

c+

:r:

60
1

10

65

100

10

1

f - Frequency- kHz

100

f - Frequency- kHz

Figure 11

Figure 12

In
"c:s
I

.

\-

III

'0
90~--~---------r------------~

Z

+

80

c
0

t:

~

85~------~~--t-----------~

is
u

'2

75

0

E
III

:r:
80~------------~~----------~

S
~

'"

~

70

I
Z

~

1

__________

10

C

:r:

I-

~

____________

~

~

5

+

7

I-

100

65
1

10

f - Frequency - kHz

f - Frequency - kHz

Figure 13

Figure 14

100

~TEXAS

INSTRUMENTS
rOGT OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-63

TLC5617,TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151A-JULY 1997 - REVISED DECEMBER 1997

TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE RATIO (FAST MODE)

vs
FREQUENCY
85~----------~------------~

o

. \..r-

.~
o
z

75~----------~~-+--------~

m

'C

I

~
~
~

.2'
Ul
I

70~----------~--~~-------;

a:
Z

Ul

65~

__________

1

~~

__________

10

~

100

f - Frequency - kHz

Figure 15
m
~

0.2,-----------,-----------,-----------,-----------,

::.. 0.15 ~----------t_----------+_----------+_--------___1

~

0.1 ~----------t_--------_y_+_---------+_--------___1

~ 0.051--r--::--t-IH-.-+-H-+-;-r-l-+++-----:----lf-+--t-hr-ot-+-.----.:--:--I

__

~ O~~. .~II~~~~~~~~~IW ~MI...
c -0.05 f-I--'---...J---'....::.!.--I---t_----------+------'-..:....c:......L.-----++-=----------=---_l
I!!

~

-O.1~----------t_----------+_----------+_----------_l

C-015~----------t_----------+_----------+_----------_l
I
•
~

Q

-O.2~

0

______

~

__L __ _ _ _ _ _ _ _ _ _

255

~_ _ _ _ _ _ _ _ _ _~ _ _ _ _ _ _ _ _ _ _ ~

511

767

InpulCode

Figure 16. Differential Nonlinearity With Input Code

~TEXAS

3-64

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1023

TLC5617, TLC5617A
PROGRAMMABLE DUAL 10·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS151A- JULY 1997 - REVISED DECEMBER 1997

TYPICAL CHARACTERISTICS
III

1

~

O.S

I

0.6

.~

0.4
0.2

~
..

~

e

A

..,.... \f-#IVV'I-"'"

~

.

"""

0

'\ AJ-..Y
-{l.2 ,.~.

~ -{l.4

.5

h

/""'11.
.

A.M

. V'" ...

~

-{l.6

.!.

-{l.S

2!:

-1

o

255

511

767

1023

Input Code

Figure 17. Integral Nonlinearity With Input Code

APPLICATION INFORMATION

general function
The TLC5617 uses a resistor string network buffered with an op amp to convert 10-bit digital data to analog
voltage levels (see functional block diagram and Figure 17). The output of the TLC5617 is the same polarity
as the reference input (see Table 1).
The output code is given by:

2( V REFIN) ~~~4E

An internal circuit resets the DAC register to ali Os on power-up.

r------------------,

I
I
I

REFIN

-+---1

I
--I
I

DIN

CS

SCLK

>-.....-OUT

---1

I

-+-----'-----'

I
I
I
I
I
I

R

AGND

VDD

~------~~~~--=-

0.1 !iF

Figure 18. TLC5617 Typical Operating Circuit

~TEXAS

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3-65

TLC5617, TLC5617A
PROGRAMMABLE DUAL 10~BIT DIGITAL-TO-ANALOG CONVERTERS
SLASI51A- JULY 1997 - REVISED DECEMBER 1997

APPLICATION INFORMATION
Table 1. Binary Code Table (0 V to 2 VREFIN Output), Gain
INPurt
1111

1111

=2

OUTPUT
(

) 1023
2 VREFIN 1024

11(00)

:

:

1000

0000

01(00)

1000

0000

00(00)

0111

1111

11(00)

0000

0000

01(00)

0000

0000

00(00)

(
) 513
2 V REFIN 1024
(
) 512
2 VREFIN 1024 = VREFIN
(
) 511
2 VREFIN 1024

:

:
2( V REFIN) 1

0~4

OV

tAl O-bit data word with two sub-LSB Os must be written since the DAC input
latch is 12 bits wide.

buffer amplifier
The output buffer has a rail-to-rail output with short circuit protection and can drive a 2-kQ load with a 100 pF
load capacitance. Settling time is a software selectable 12.5 IlS or 2.5 IlS typical to within ±0.5 LSB of final value:

external reference
The reference voltage input is buffered which makes the DAC input resistance not code dependent. Therefore,
the REFIN input resistance is 10 MQ and the REFIN input capacitance is typically 5 pF, independent of input
code. The reference voltage determines the DAC full-scale output.

logic interface

,

The logic inputs function with CMOS logic levels. Most of the standard high-speed CMOS logic families may
be used.

serial clock and update rate
Figure 1 shows the TLC5617 timing. The maximum serial clock rate is
f

-'
1
(SCLK)max - tw(CH)min + tW(CL)min

= 20 MHz

The digital update rate is limited by the chip-select period, which is
tp(CS) = 16 x (tW(CH)

+ tW(CL)) + tSU(CS1)

This equals 820-ns or 1.21-MHz update rate. However, the DAC settling time to 10 bits limits the update rate
for full-scale input step transitions.

~TEXAS'

INSTRUMENTS
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TLC5617,TLC5617A
PROGRAMMABLE DUAL 10·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS151 A - JULY 1997 - REVISED DECEMBER 1997

APPLICATION INFORMATION

serial interface
When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in most
significant bit first. The falling edge of the SCLK input shifts the data into the input register.
The rising edge of CS then transfers the data to the DAC register. All CS transitions should occur when the SCLK
input is low.
The 16 bits of data can be transferred with the sequence shown in Figure 18.
4

16 Bits

4

I

t..

Program Bits
D15

I

I

D14

MSB (Input Word)

D13

I

D12

.

Data Bits
D11

10 Data Bits

MSB (Data)

D2
LSB (Data)

•
Fill Bltst
D1=x

I

-+

DO=x

I

LSB (Input Word)

t Two extra (sub-LSB) bits (can be don't care)

Figure 19. Input Data Word Format
Table 2 shows the function of program bits D15 - D12.
Table 2. Program Bits 015 - 012 Function
PROGRAM BIT

DEVICE FUNCTION

D15

D14

D13

D12

1

X

X

X

Write to latch A with serial
interface register data and latch B
updated with buffer latch data

0

X

X

0

Write to latch B and double buffer
latch

1

Write to double buffer latch only

X

12.5 ~s settling time
2.5

Powered-down mode

0

X

X

1

X
X

X
X

0

X

X

0

X
X

X

X

1

X

~s

settling time

Powered-up operation

function of the latch control bits (015 and 012)
Three data transfers are possible. All transfers occur immediatly after CS goes high and are described in the
following sections.
latch A write, latch B update (015 = high, 012 = X)
The serial interface register (SIR) data are written to latch A and the double buffer latch contents are written to
latch B. The double buffer contents are unaffected. This control bit condition allows simultaneous output updates
of both DACs.

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TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151 A - JULY 1997 - REVISED DECEMBER 1997

APPLICATION INFORMATION
Serial
Interface
Register
012=X
015 = High

Figure 20. Latch A Write, Latch B Update
latch B and double-buffer 1 write (D15

=low, D12 =low)

The SIR data are written to both latch B and the double buffer. Latch A is unaffected.
Latch A

Serial
Interface
Register
012 = Low
015= Low

~

To OAC A

ToOACB

Buffer
Latch

Figure 21. Latch B and Double-Buffer Write
double-buffer-only write (D15 = low, D12 = high)

The SIR data are written to the double buffer only. Latch A and B contents are unaffected.
Serial
Interface
Register
012 = High
015= Low

Latch A

~

ToOACA

Latch B

~

To OAC B

Figure 22. Double-Buffer-Only Write
purpose and use of the buffer

Normally only one DAC output can change after a write. The double buffer allows both DAC outputs to change
after a single write. This is achieved by the two following steps.
1. A double-buffer-only write is executed to store the new DAC B data without changing the DAC A and B
outputs.
2.

Following the previous step a write to latch A is executed. This writes the SIR data to latch A and also writes
the double-buffer contents to latch B. Thus both DACs receive their new data at the same time and so both
DAC outputs begin to change at the same time.

Unless a double-buffer-only write is issued, the latch B and double-buffer contents are identical. Thus, following
a write to latch A or B with another write to latch A does not change the latch B contents.

~TEXAS

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TLC5617,TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151A-JULY 1997 - REVISED DECEMBER 1997

APPLICATION INFORMATION
operational examples

changing the latch A data from zero to full code
Assuming that latch A starts at zero code (e.g., after power-up), the latch can be filled with 1s by writing (bit 015
on the left, DO on the right)
1XOX 1111 1111 11 XX
to the serial interface. Bit 014 can be zero to select slow mode or one to select fast mode. The other Xs can
be zero or one (don't care).
The latch B contents and the OAC B output are not changed by this write unless the double-buffer contents are
different from the latch B contents. This can only be true if the last write was a double-buffer-only write.

changing the latch B data from zero to full code
Assuming that latch B starts at zero code (e.g., after power-up), the latch can be filled with 1s by writing (bit 015
on the left, DO on the right).
OXOO 1111 1111 11 XX
to the serial interface. Bit 014 can be zero to select slow mode or one to select fast mode. The other Xs can
be zero or one (don't care). The data (bits DO to 011) are written to both the double buffer and latch B.
The latch A contents and the OAC A output are not changed by this write.

double-buffered change of both DAC outputs
Assuming that OACs A and B start at zero code (e.g., after power-up), if OAC A is to be driven to mid-scale and
OAC B to full-scale, and if the outputs are to begin rising at the same time, this can be achieved as follows:
First,
Od01 1111 1111 11XX
is written (bit 015 on the left, DO on the right) to the serial interface. This loads the full-scale code into the double
buffer latch but does not change the latch B contents and the OAC B output voltage. The latch A contents and
the OAC A output are also unaffected by this write operation.
Changing from fast to slow mode or slow to fast mode changes the supply current which can glitch the outputs,
and so 014 (designated by d in the data word) should be set to maintain the speed made set by the previous
write. The other Xs can be ones or zeros (don't care).
Next,
1XOX 1000 0000 OOXX
is written (bit 015 on the left, DO on the right) to the serial interface. Bit 014 can be zero to select slow mode
or one to select fast mode. The other Xs can be zero or one (don't care). This writes the mid-scale code
(1000000000XX) to latch A and also copies the full-scale code from the double buffer to latch B. Both OAC
outputs thus begin to rise after the second write.

-!!1
TEXAS
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TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151A- JULY 19~7 - REVISED DECEMBER 1997

APPLICATION INFORMATION
DSP serial interface

Utilizing a simple 3 wire serial interface, the TLC5617A can be interfaced to TMS320 compatible serial ports.
The 5617A has an internal state machine that will count 16 clocks after receiving a falling edge of /CS and then
disable further clocking in of data until the next falling edge is received on /CS. Therefore the /CS can be
connected directly to the FS pins of the serial port and only the leading falling edge of the DSP will be used to
start the write process. The TLC5617A is designed to be used with the TMS320Cxx DSP's in Burst Mode Serial
Port Transmit operation.
VCC

FSR
CS .....- -.......-1 FSX
Analog
Output

OUT A
TLC5617

Analog
Output

OUT B

SCLK 1-+--+----1 CLKX

TMS320C32
DSP

CLKR
DIN
REFIN

OX
2.5 V dc

GND
To Source
Ground

+---.

Figure 23. Interfacing The TLC5617 To TMS320C32 DSP
SPI serial interface

Both the TLC5617 and TLC5617A are compatible with SPI, aSPI or Microwire serial standards. The hardware
connections are shown in Figures 23 and 24. The TLC5617A has an internal state machine that will count 16
clocks after the falling edge to /CS and then internally disable the device. The internal edge is or'd together with
the /CS so that the rising edge can be provided to /CS prior to the occurrence of the internal edge to also disable
the device.
general serial interface

The TLC5617 three-wire interface is compatible with the SPI, aSPI, and Microwire serial standards. The
hardware connections are shown in Figure 23 and Figure 24.
The SPI and Microwire interfaces transfer data in 8-bit bytes, therefore, two write cycles are required to input
data to the DAC. The aSPI interface, which has a variable input data length from 8 to 16 bits, can load the DAC
input register in one write cycle.

~TEXAS

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TLC5617, TLC5617A
PROGRAMMABLE DUAL 10·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS151A- JULY 1997 - REVISED DECEMBER 1997

SCLK
DIN
TLC5617
CS

SK
SO Microwire
Port
1/0

Figure 24. Microwire Connection
SCLK
DIN
TLC5617
CS

SCK
MOSI SPI/QSPI
Port

110
CPOL = 1, CPHA = O.

Figure 25. SPIIQSPI Connection
linearity, offset, and gain error using single end supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage
may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

~TEXAS

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3-71

TLC56t7, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151A- JULY 1997 - REVISED DECEMBER 1997

APPLICATION INFORMATION

linearity, offset, and gain error using single end supplies (continued)
The output voltage remains at zero until the input code value produces a sufficient positive output voltage to
overcome the negative offset voltage, resulting in the transfer function shown in Figure 24.

Output
Voltage

ov ~----~~-------------------.
Negative {
Offset
.

DACCode

Figure 26. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full scale code and the lowest code that produces a positive output voltage. For the
TLC5617, the zero-scale (offset) error is plus or minus 3 LSB maximum. The code is calculated from the
maximum specification for the negative offset.

power-supply bypassing and ground management
Printed circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane making sure that analog ground
currents are well managed.
A 0.1 IlF ceramic bypass capacitor should be connected between VDD and AGND and mounted with short leads
as close as possible to the device. Use of ferrite beads may further isolate the system analog and digital power
supplies.
Figures 25 shows the ground plane layout and bypassing technique.

Figure 27. Power-Supply Bypassing

~TEXAS
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TLC5617,TLC5617A
PROGRAMMABLE DUAL 10·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS151A- JULY 1997 - REVISED DECEMBER 1997

APPLICATION INFORMATION
saving power
Setting the DAC register to all Os minimizes power consumption by the reference resistor array and the output
load when the system is not using the DAC.

ac considerations/analog feedthrough
Higher frequency analog input signals may couple to the output through internal stray capacitance. Analog
feedthrough is tested by holding CS high, setting the DAC code to all Os, sweeping the frequency applied to
REFIN, and monitoring the DAC output.

~TEXAS

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3-73

3-74

TLC5618,TLC5618A
PROGRAMMABLE DUAL 12·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS156B -JULY 1997 - REVISED DECEMBER 1997

•
•
•
•
•
•

•
•
•

Programmable Settling Time to 0.5 LSB
2.5 J.IS or 12.511S Typ
Two 12-Bit CMOS Voltage Output DACs in
an S-Pin Package
Simultaneous Updates for DAC A
and DAC B
Single Supply Operation
3-Wire Serial Interface
High-Impedance Reference Inputs
Voltage Output Range .•• 2 Times the
Reference Input Voltage
Software Power Down Mode
Internal Power-On Reset

•
•

•
•

TMS320 and SPI Compatible
Low Power Consumption:
3 mW Typ in Slow Mode
S mW Typ in Fast Mode
Input Data Update Rate of 1.21 MHz
Monotonic Over Temperature

applications
•
•
•
•
•

Battery Powered Test Instruments
Digital Offset and Gain Adjustment
Battery Operated/Remote Industrial
Controls
Machine and Motion Control Devices
Cellular Telephones

o PACKAGE

description

(TOP VIEW)

The TLC5618 is a dual 12-bit voltage output
digital-to-analog converter (DAC) with buffered
reference inputs (high impedance). The DACs
have an output voltage range that is two times the
reference voltage, and the DACs are monotonic.
The device is simple to use, running from a single
supply of 5 V. A power-on reset function is
incorporated to ensure repeatable start-up
conditions.

a
D1Nu
SCLK 2
. 7
CS 3
6
OUT A 4
5

VDD
OUT B
REFIN
AGND

Digital control of the TLC5618 is over a 3-wire CMOS-compatible serial bus. The device receives a 16-bit word
for programming and to produce the analog output. The digital inputs feature Schmitt triggers for high noise
immunity. Digital communication protocols include the SPITM, QSPITM, and Microwire™ standards.
Two versions of this device are available. The TLC5618 does not have any internal state machine and is
dependent on all external timing signals. The TLC5618A has an internal state machine that will count the
number of clocks from falling edge of CS and then update and disable the device to accepting further data inputs.
The TLC5618A is recommended for TMS320 and SPI processors and the TLC5618 is recommended only for
use in SPI or 3-wire serial port processors. The TLC5618A is backward compatible and deSigned to work in
TLC5618 deSigned systems.
The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications.
The TLC5618C is characterized for operation from O°C to 70°C. The TLC56181 is characterized for operation
from -40°C to 85°C.

A.

....

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI and aSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.

~~~cts~:o~1: ::r~~~':w'~'::~ar::: ,e=:~=~m~n:;

standard warranty. Production processing does not necessarily Include
testing of all parameters.

~TEXAS

INSTRUMENTS
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Copyright© 1997, Texas Instruments Incorporated

3-75

TLC5618,TLC5618A
PROGRAMMABLE DUAL 12·BIT DIGITAL·TO·ANALOGCONVERTERS
SLAS156B - JULY 1997 - REVISED DECEMBER 1997'

AVAILABLE OPTIONS
PACKAGE
TA

SMALL OUTLINEt
(D)

PLASTIC DIP
(P)

O°C to 70°C

TLC5618CD
TLC5618ACD

TLC5618CP
TLC5618ACP

-40°C to 85°C

TLC56181D
TLC5618AID

TLC56181P
TLC5618AIP

t The D pacakge IS available
(e.g., TLC5618CDR)

In

tape and reel by adding R to the part number

DEVICE

COMPATIBILITY

TLC5618

SPI, aSPI and Microwire

TLC5618A

TMS320Cxx, SPI, aSPI and Microwire

functional block diagram

REFIN -"6_---._ _ _--1

>----.~-"4

OUT A

(Voltage Output)

IT---;===;-----v;;"1

AGND -=..5-

CS

"'3_-+-+_---1

Control
Logic

SCLK ...,,2_-+-+-'---1

L...-_,....-I

DIN

-'--+-+-t--...-+-----1H.....

>--e---,"7

OUTB

(Voltage Output)

R

R

Terminal Functions
TERMINAL
NAME
DIN

NO.
1

1/0

I

DESCRIPTIOM
Serial data input

~TEXAS

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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156B- JULY 1997 - REVISED DECEMBER 1997

SClK

2

I

Serial clock input

CS

3

I

Chip select, active low

OUTA

4

0

AGND

5

DAC A analog output
Analog ground

REFIN

6

I

OUTS

7

0

VOO

8

Reference voltage input
DAC S analog output
Positive power supply

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage (Voo to AGND) ............................................................... 7 V
Digital input voltage range to AGND .......................................... - 0.3 V to Voo + 0.3 V
Reference input voltage range to AGND ...................................... - 0.3 V to Voo + 0.3 V
Output voltage at OUT from external source ............................................ VOD + 0.3 V
Continuous current at any terminal ........................................................ ±20 mA
Operating free-air temperature range, TA: TLC5618C .................................... O°C to 70°C
TLC56181 ................................... -40°C to 85°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended cperating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions
Supply voltage, VDD
High-level digital input voltage, VIH
low-level digital input voltage, Vil

I VDD= 5V
I VDD =5V

MIN

NOM

4.5

5

load resistance, Rl

2

I TlC5618C

UNIT
V
V

0.3 VOD
2

ITlC56181

5.5

O.7VDD

Reference voltage, Vref to REFIN terminal

Operating free-air temperature, TA

MAX

2.048

VDD-l.l

V
V
kn

0

70

°C

-40

85

°C

~TEXAS

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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS156B-JULY 1997 - REVISED DECEMBER 1997

electrical characteristics over recommended operating free·air temperature range, VDD
Vref(REFIN) = 2.048 V (unless otherwise noted)

=5 V ±5%,

static DAC specifications
PARAMETER

TEST CONDITIONS

MIN

Resolution
Integral nonlinearity (INL), end point adjusted

EZS

EG

TYP

Vref(REFIN) = 2.048 V,

See Note 1

Oifferential nonlinearity (ONL)

Vref(REFIN) = 2.048 V,

See Note 2

Zero-scale error (offset error at zero scale)

Vref(REFIN) = 2.048 V,

See Note 3

Zero-scale-error temperature coefficient

Vref(REFIN) = 2.048 V,

See Note 4

Gain error

Vref(REFIN) = 2.048 V,

See Note 5

=2.048 V,

See Note 6

Gain error temperature coefficient

Vref(REFIN)

±4

LSB

±0.5

±1

LSB

±12
3

Power-supply rejection ratio

mV
ppml"C

±0.29

%ofFS
voltage
ppm/oC

1
65

Slow

Gain

65

See Notes 7 and 8

dB

Zero scale

65

Fast

Gain
NOTES:

UNIT
bits

Zero scale
PSRR

MAX

12

65

1. The relative accuracy or Integral nonllneanty (INL) sometimes referred to as IIneanty error, IS the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
2. The differential nonlinearity (ONL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) - EZS (T min)]Nref x 106/(Tmax - T min).
5. Gain error is the deviation from the ideal output (Vref - 1 LSB) with an output load of 10 kn excluding the effects of the zero-error.
6. Gain temperature coefficient is given by: EG TC = [EG(Tmax) - EG (T min)]Nref x 106/(Tmax - T min)·
7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VOO from 4.5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the zero-code output voltage.
8. Gain-error rejection ratio (EG-RR) is measured by varying the VOO from 4.5 V to 5.5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage aiter subtracting the zero scale change.

OUT A and OUT B output specifications
PARAMETER
Vo

IOSC(sink)

IOSC(source)

TEST CONDITIONS

Voltage output range

MIN

TYP

0

RL= 10kO

Output load regulation accuracy

VO(OUT) = 4.096 V,

RL= 2kO

VO(A OUT) = VOO,
VO(B OUT) = VOO,
Input code zero

Fast

38

Output short circuit sink current

Slow

23

VO(A OUT) = 0 V,
VO(B OUT) = 0 V,
Full-scale code

Fast

-54

Slow

-29

Output short circuit source current

MAX

UNiT

VOO-D·4

V

±0.29

%ofFS
voltage
mA

mA

IO(sink)

Output sink current

VO(OUT) = 0.25 V

5

mA

IO(source)

Output source current

VO(OUT) = 4.2 V

5

mA

~TEXAS

INSTRUMENTS
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TLC5618,TLC5618A
PROGRAMMABLE DUAL 12·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS156B -JULY 1997 - REVISED DECEMBER 1997

electrical characteristics over recommended operating free·air temperature range, Voo = 5 V ±5%,
Vref(REFIN) 2.048 V (unless otherwise noted) (continued)

=

reference input (REFIN)
PARAMETER
VI

Input voltage range

Ri

Input resistance

Ci

TEST CONDITIONS

MIN

TYP

MAX

0

VOO-2

Input capacitance
HEFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 9)

Reference input bandwidth (f-3dB)

REFIN = 0.2 Vpp + 1.024 V dc

V
MQ

10

Reference feedthrough

UNIT

5

pF

-60

dB

I Slow

0.5

I Fast

1

MHz

NOTE 9: Reference feedthrough is measured at the OAC output with an input code = 000 hex and a Vref(REFIN) input = 1.024 V dc + 1 Vpp at 1
kHz.
.

digital inputs (OIN, SCLK, CS)
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IIH

High-level digital input current

VI = VOO

±1

IlA

IlL

Low-level digital input current

VI=OV

±1

IiA

Ci

Input capacitance

pF

8

power supply
PARAMETER
100

TYP

MAX

Slow

0.6

1

Fast

1.6

2.5

TEST CONDITIONS
VOO =5.5 V,
No load,
All inputs = 0 V or VOO

Power supply current
Power down supply current

MIN

UNIT
mA

013 = 0 (see Table 2)

IlA

1

operating characteristics over recommended operating free-air temperature range, Voo = 5 V ±5%,
Vref(REFIN) 2.048 V (unless otherwise noted)

=

analog output dynamic performance
PARAMETER
SR+

SR-

Output slew rate, positive

Output slew rate, negative

MIN

TYP

Slow

0.3

0.5

Fast

2.4

3

Vref(REFIN) = 2.048 V,
TA = 25°C,
Va from 10% to 90%

Slow

0.15

0.25

Fast

1.2

1.5

TEST CONDITIONS
CL = 100 pF,
RL = 10 kQ,
Code 32 to Code 4096,

Vref(REFIN) = 2.048 V,
TA='25'C,
Va from 10% to 90%

CL = 100 pF,
'RL= 10 kQ,
Code 4096 to Code 32,

UNIT

ViliS

V/IlS

Output settling time

To ±0.5 LSB,
RL= 10kn,

CL = 100 pF,
See Note 10

Slow

12.5

ts

Fast

2.5

Output settling time,
code-to-code

To±0.5 LSB,
RL = 10 kg,

CL = 100 pF,
See Note 11

Slow

2

ts(c)

Fast

2

Glitch energy

DIN = All Os to allls,
f(SCLK) = 100 kHz

CS= VOO,

Signal to noise + distortion

Vref(REFIN) = 1 Vpp at 1 kHz and 10kHz + 1.024 V dc,
Input code = 10 0000 0000

S/(N+O)

MAX

5
78

liS

liS

nV-s
dB

NOTES: 10. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of 020 hex to 3FF hex or 3FF hex to 020 hex.
11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of one count.

~TEXAS

INSTRUMENTS
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3-79

TLC5618, TLC5618A
PROGRAMMABLE DUAL 12·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS156B- JULY 1997 - REVISED DECEMBER 1997

operating characteristics over recommended operating free-air temperature range, VDD
Vref(REFIN) = 2.048 V (unless otherwise noted) (continued)

=5 V ±5%, .

digital input timing requirements
NOM

MIN

MAX

UNIT

tsu(DS}

Setup time, DIN before SCLK low

5

thIDH)

Hold time, DIN valid after SCLK low

5

ns

5

ns

10

ns

tsu(CS$}

Setup time, CS low to SCLK low

tsu{CSll

Setup time, SCLK i to CS

tsu(CS2}

Setup time, SCLK i to CS

tw(CL}

t, external end-of-write
t, start of next write cycle

ns

5

ns

Pulse duration, SCLK low

25

ns

tw(CH)

Pulse duration, SCLK high

25

td(CS1}

Delay time, CLKi to Disable (TLC5618A only)

ns
5

ns

,

\~----------------~(\)~\--~*~--~
~I
1-

I

su(CSS)

m<

14

DIN

,
14

:

~4
015

"

,.,

,,

~

"

tsu(DS)

,4

" . - tIlU(CS2) ---.,

SCLK
(see Note A)

,

Isu(CS1)

tw(CL) -+41----I....I4I---.+_ tw(CH)

,

'

~

th(DH)

X

014

,

X

013

X,--_D_12_v;:j,
011 \ DO

Program Bits (4)

~\
.14

DAC Data
Blls (12)

~r:.~,.:::ooo::o"':l"'~~~

',.

--J-I ,'..-- I s - -.. i,

DACO~~ ______________________________________________________-J:~ ~
:;:; Final Value ±D.S LSB
NOTE A: The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough.

Figure 1. Timing Diagram for the TLC5618

3-80

"'TEXAS
INSTRUMENTS
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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156B- JULY 1997 - REVISED DECEMBER 1997

Internally Generated
Disable at This Time )

td(CS1)

~~________________________~\~\----~l~~~~

CS

~t
1~"1
SU(CSS)
SCLK

I (see Note A)

~ -~
DIN

--.I 14-

~
I
I

I..

I
I
I
I
.,.

tsu(CS1)

tw(CL)

I
I"
I

III
I I ·1
I
14i- tIilU(CS2) -.1

~II
I I
I I
I I

>I- '~DH)

D")(

014

X

013

Program Bits (4)

¥E:

X,,-_D_12___

--------J~I!III-

(see Note A)

I .

DO

DAC Data
Bits (12)

~r"I""""'''''''''''''''''''''''''''''''
-..!- I

i4-I

t

s

---+--..:
I I

DACt~~ ~l--------------------------------------------------~~-~I

,,; Final Value ±a.s LSB

NOTE B: T~e input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough.

I
Figure 2. Timing Diagram for TLC5618A only

-!I1TEXAS

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3-81

TLC5618,TLC5618A
PROGRAMMABLE DUAL 12·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS156B - JULY 1997 - REVISED DECEMBER 1997

TYPICAL CHARACTERISTICS
OUTPUT SINK CURRENT (FAST MODE)

OUTPUT SOURCE CURRENT (FAST MODE)

vs

vs

OUTPUT LOAD VOLTAGE

OUTPUT LOAD VOLTAGE
-60

40
35
c(

E

1:
~

20

0
r:

15

iii

-50
I

0

o

1\

0

~

-30

1\

::J

0

/
/
II

5

-5

1: -40
~
::J

/

% 10
0

i

I/)

-20

\

0
-10

VOO =5 V
Input Code = 0

0.5

1.5

2

2.5

I

I

I

3

3.5

4

o
o

4.5

1\
0.5

Figure 3

l

c

vs
OUTPUT LOAD VOLTAGE

- r-- b

-25

/
II

c(

E
I

1: -20
~
::J

~ -15

/

:;

5

4

4.5

~

\

::J

Jl

&.

-10

'S

o
0

-5
VOO=5 V
Input Code = 0

-0

o

0.5

1.5

2

2.5

3

3.5

4

VOO=5 V
Input Code = 4095
4.5

o
o

0.5

Output Load Voltage - V

1.5

2

2.5

3

3.5

Output Load Voltage - V

Figure 5

Figure 6

~TEXAS

3-82

1\

o

J

10

iii

g

3.5

OUTPUT LOAD VOLTAGE

1/

::J

~

3

OUTPUT SOURCE CURRENT (SLOW MODE)

-30

15

2.5

vs
25

c(

2

Figure 4

OUTPUTSINK CURRENT (SLOW MODE)

.. EI

1.5

Output Load Voltage - V

Output Load Voltage - V

20

"' !'\

E

II

:;

Voo =5V
Input Code = 4095

-..

c(

I

25

....

/

30

I

::J

v

INSTRUMENTS
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4

4.5

TLC5618, TLC5618A
PROGRAMMABLE DUAL 12·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS156B -JULY 1997 - REVISED DECEMBER 1997

TYPICAL CHARACTERISTICS
SUPPLY CURRENT

1.6

RELATIVE GAIN (FAST MODE)

vs

vs

TEMPERATURE

FREQUENCY

_, :N-

V

5

Fast Mode

1.4
1.2

"g

I

I

C

~
Q.

c
'iii

-10

.::

-15

.

Slow Mode

a;

0.6

1\

Gi

:::I

-20
VCC=5 V
-25 I- VREFIN = 0.2 Vpp + 2.048 Vdc

VOO =5 V
0.2 f- VREFIN = 2.048 V
TA = 25"C

o

-60 -40 -20

0

20 40 60 80
Temperature - "C

-30
100

100 120 140

TA

i "f
25

I I I IIII

0

-5
-10

I

c
'iii
CI
>

..
:;
Gi

II:

-15
-20

Figure 8
TOTAL HARMONIC DISTORTION (SLOW MODE)

vs

vs

FREQUENCY

FREQUENCY

II

1\

~

I

I

I

95

I I I

VCC=5V
VREFIN = 0.2 Vpp +
2.048 Vdc
TA=25"C

ID
"g

90

I

""

c
0

1:

~

~

\

-25

"0

'2

-~

80

E
as

\

::t:

S

-40

1000

75

I

\,

-35

85

is

~

-30

100

10 K

f - Frequency - kHz

RELATIVE GAIN (SLOW MODE)

I-

,

~

I

1000

Figure 7

5

,

1\

II:

0.4

"g

\

CI

0.8

III

ID

\

ID

E

~

~

-5

CC

:::I
(,)

-

0

C

::t:

I-

10 K

70

\

1\

V

65

1

f - Frequency - kHz

10

100

f - Frequency - kHz

Figure 9

Figure 10

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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12 BIT DIGITAL-TO-ANALOG CONVERTERS
w

SlAS~56B.,. JULY 1997 - REVISED DECEMBER 1997 .

TYPICAL CHARACTERISTICS
TOTAL HARMONIC DisTORTION + NOISE (SLOW MODE)

SIGNAL-TO-NOISE RATIO (SLOW MODE)

vs

vs

FREQUENCY

FREQUENCY

85

85

~

ID

"1:1

I
0

80

,

-...

..,- r-.....

"

iII:
3l
"0

z

~
ic

75

~
I

II:

70

Z

1

__________

10

~

____________

~

~

0

6

Ul

65

100

f - Frequency- kHz

Figure 11

Figure 12

TOTAL HARMONIC DISTORTION (FAST MODE)

vs

FREQUENCY

FREQUENCY
85

90

80

§

85

75

~

80

70

""

ID

~

-

!

Q

u

~

I
Q

100

TOTAL HARMONIC DISTORTION + NOISE (FAST MODE)

vs
95~------------~------~----.

"cI

10

1

f - Frequency- kHz

h

::c

....
10

100

65
1

f - Frequency - kHz

Figure 13

Figure 14

~TEXAS

3-84

10

f - Frequency - kHz

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

100

TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156B - JULY 1997 - REVISED DECEMBER 1997

TYPICAL CHARACTERISTICS
SIGNAL·TO·NOISE RATIO (FAST MODE)

vs
FREQUENCY
85~-----------,~----------,

n~-----------r--~------~

ro~-----------r---+------~

~~----------~----------~
1
10
100
f - Frequency - kHz

Figure 15

~TEXAS

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3-85

TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156B -JULY 1997 - REVISED DECEMBER 1997

TYPICAL CHARACTERISTICS
~

:~

c

0.8r-----+-----+-----~----_r----_r----_+----_+----~~
0.6r-----+-----+-----~----_r----_r----_+----_+----~~
0.4r-----+-----+-----4------r----~----_+----_+----~~

~

0.2

iii

o

~

I!!

-0~2

I

-0.4
-0.6
-0.8

~
c
....I

Z

,....,. ...............

j

~,

I

.........

l

~

.....

I

~_......---........,..

".

....J.

I

....................... _________ _", ..." ....... .,...,.r'

,....

.Ill

•

I

I

lIW ........~~~~............

C

500

1000

1500

2000

2500

3000

Samples

Figure 16. Differential Nonlinearity With Input Code

m
~
I

.~

ii
.5
C
0

z

f!Ol

0.5
0
-0.5
-1
-1.5

.!!
.5

-2

I

-2.5

....I

~

Samples

Figure 17. Integral Nonlinearity With Input Code

~TEXAS

INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3500

4095

TLC5618, TLC5618A
PROGRAMMABLE DUAL 12·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS156B- JULY 1997 - REVISED DECEMBER 1997

APPLICATION INFORMATION
general function
The TLC5618 uses a resistor string network buffered with an op amp to convert 12-bit digital data to analog
voltage levels (see functional block diagram and Figure 17). The output is the same polarity as the reference
input (see Table 1).
The output code is given by: 2(V REFIN) ~~~6E
An internal circuit resets the DAC register to all Os on power-up.

r------------------,

I
I
I

REFIN

-+----1

I
---l
I
CS --J
I

DIN

SCLK

>-e-J.-

OUT

-+-----'--------'

I
I
I
I
I
I

AGND

VDD

~------~~~;--=-

O.lI1F

Figure 18. TLC5618 Typical Circuit
Table 1. Binary Code Table (0 V to 2 VREFIN Output), Gain = 2
INPUT

1111

1111

OUTPUT

(

)4095
2 VREFIN 4096

1111

:

:

1000

0000

0001

1000

0000

0000

0111

1111

1111

(

)2049
2 V REFIN 4096
(
)2048
2 VREFIN 4096 = V REFIN
(
)2047
2 V REFIN 4096

:

:

0000

0000

0001

0000

0000

0000

2( VREFIN)

40~6

OV

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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156B- JULY 1997 - REVISED DECEMBER 1997

APPLICATION INFORMATION

buffer amplifier
The output buffer has a rail-to-rail output with short circuit protection and can drive a 2-kil load with a 100-pF
load capacitance. Settling time is a software selectable 12.5 Ils Dr 2.5 JlS, typical to within ± 0.5 LSB of final value.

external reference
The reference voltage input is buffered which makes the DAC input resistance not code dependent. Therefore,
the REFIN input resistance is 10 Mil and the REFIN input capacitance is typically 5 pF, independent of input
code. The reference voltage determines the DAC full-scale output.

logic interface
The logic inputs function with CMOS logic levels. Most of the standard high-speed CMOS logic families may
be used.

serial clock and update rate
Figure 1 shows the TLC5618 timing. The maximum serial clock rate is:
f

-.
1
= 20 MHz
(SCLK)max - tw(CH)min + tW(CL)min

The digital update rate is limited by the chip-select period, which is:
tp(CS) = 16 x (tW(CH)

+ tW(CL)) + tsu(CS1)

This equals an 820-ns or 1.21-MHz update rate. However, the DAC settling time to 12 bits limits the update rate
for full-scale input step transitions.

serial interface
When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in most
significant bit first. The falling edge of the SCLK input shifts the data into the input register.
The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot be clocked
into the input register. All CS transitions should occur when the SCLK input is low.
The 16 bits of data can be transferred with the sequence shown in Figure 18.
...
...

16Blts--------------..
Program Bits

Data Bits
012

MSB (Input Word)

011

12 Data Bits

MSB(Data)

Figure 19. Input Data Word Format

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DO
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TLC5618,TLC5618A
PROGRAMMABLE DUAL 12·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS156B-JULY 1997 - REVISED DECEMBER 1997

APPLICATION INFORMATION
Table 2 shows the function of program bits 015 - 012.

Table 2. Program Bits 015 - 012 Function
PROGRAM BITS

DEVICE FUNCTION

D15

D14

D13

D12

1

X

X

X

Write to latch A with serial
interface register data and latch B
updated with buffer latch data

0

X

X

0

Write to latch B and double buffer
latch

0

X

X

1

Write to double buffer latch only

X
X
X
X

1

X
X

X
X

2.5 ItS settling time

0

X
X

0

X
X

1

12.5 ~ settling time
Powered-up operation
Power down mode

function of the latch control bits (015 and 012)
Three data transfers are possible. All transfers occur immediately after CS goes high and are described in the
following sections.

latch A write, latch B update (015

=high, 012 =X)

The serial interface register (SIR) data are written to latch A and the double buffer latch contents are written to
latch B. The double buffer contents are unaffected. This program bit condition allows simultaneous output
updates of both OACs.
ToDACA

Serial
Interiace
Register
D12=X
D15 = High

ToDAC B

Figure 20. Latch A Write, Latch B Update
latch B and double-buffer 1 write (015 = low, 012 = low)
The SIR data are written to both latch B and the double buffer. Latch A is unaffected.
Serial
Interiace
Register

Latch A

~

D12= Low
D15 = Low

To DAC A

To DAC B

Figure 21. Latch B and Double-Buffer Write

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TLC5618,TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156B- JULY 1997 - REVISED DECEMBER 1997

APPLICATION INFORMATION
double-butter-only write (015

=low, 012 =high)

The SIR data are written to the double buffer only. Latch A and B contents are unaffected.
Serial
Interface
Register
012
015

= High
= Low

Latch A

~. To OAC A

Latch B

~

To OAC B

Figure 22. Double-Buffer-Only Write
purpose and use of the double buffer
Normally only one OAC output can change after a write. The double buffer allows both OAC outputs to change
after a single write. This is achieved by the two following steps.
1.

A double-buffer-only write is executed to store the new OAC B data without changing the OAC A and B
outputs.
.

2.

Following the previous step, a write to latch A is executed. This writes the SIR data to latch A and also
writes the double-buffer contents to latch B. Thus both OACs receive their new data at the same time
and so both OAC outputs begin to change at the same time.

Unless a double-buffer-only write is issued, the latch B and double-buffer contents are identical. Thus, following
a write to latch A or B with another write to latch A does not change the latch B contents.

operational examples .
changing the latch A data from zero to full code
Assuming that latch A starts at zero code (e.g., after power-up), the latch can be filled with 1s by writing (bit 015
on the left, 00 on the right)
1XOX 1111 1111 1111
to the serial interface. Bit 014 can be zero to select slow mode or one to select fast mode. The other X can be
zero or one (don't care).
The latch B contents and the OAC B output are not changed by this write unless the double-buffer contents are
different from the latch B contents. This can only be true if the last write was a double-buffer-only write.

changing the latch B data from zero to full code
Assuming that latch B starts at zero code (e.g., after power-up), the latch can be filled with 1s by writing (bit 015
on the left, 00 on the right).
OXOO 1111 1111 1111
to the serial interface. Bit 014 can be zero to select slow mode or one to select fast mode. The data (bits 00
to 011) are written to both the double buffer and latch B.
The latch A contents and the OAC A output are not changed by this write.

~TEXAS

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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS156B- JULY 1997 - REVISED DECEMBER 1997

APPLICATION INFORMATION
double-buffered change of both DAC outputs
Assuming that DACs A and B start at zero code (e.g., after power-up), if DAC A is to be driven to mid-scale and
DAC B to full-scale, and if the outputs are to begin rising at the same time, this can be achieved as follows:
First,
Od01 1111 1111 1111
is written (bit D15 on the left, DO on the right) to the serial interface. This loads the full-scale code into the double
buffer but does not change the latch B contents and the DAC B output voltage. The latch A contents and the
DAC A output are also unaffected by this write operation.
Changing from fast to slow or slow to fast mode changes the supply current which can glitch the outputs, and
so D14 (designated by d in the above data word) should be set to maintain the speed mode set by the previous
write.
Next,
1XOX 1000 0000 0000
is written (bit D15 on the left, DO on the right) to the serial interface. Bit D14 can be zero to select slow mode
or one to select fast mode. The other X can be zero or one (do not care). This writes the mid-scale code
(100000000000) to latch A and also copies the full-scale code from the double buffer to latch B. Both DAC
outputs thus begin to rise after the second write.

DSP serial interface
Utilizing a simple 3 wire serial interface, the TLC5618A can be interfaced to TMS320 compatible serial ports.
The 5618A has an internal state machine that will count 16 clocks after receiving a falling edge of /CS and then
disable further clocking in of data until the next falling edge is received on /CS. Therefore the /CS can be
connected directly to the FS pins of the serial port and only the leading falling edge of the DSP will be used to
start the write process. The TLC5618A is designed to be used with the TMS320Cxx DSP's in Burst Mode Serial
Port Transmit operation.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 .'DALLAS. TEXAS 75265

3-91

TLC5618, TLC5618A
PROGRAMMABLE DUAL 12·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS156B - JULY 1997 - REVISED DECEMBER 1997

Vcc
FSR
CS 1+--"*--1 FSX
Analog
Output

OUT A

Analog
Output

OUT B

TLC5618
SCLK 1 - + - -___---1 CLKX

TMS320C32
DSP

CLKR
DIN
REFIN

DX
2.5 V de

GND
To Source
Ground

+-----.

Figure 23. Interfacing The TLC5618 To TMS320C32 DSP
SPI serial interface

Both the TLC5618 and TLC5618A are compatible with SPI, aSPI or Microwire serial standards. The hardware
connections are shown in Figures 23 and 24. The TLC5618A has an internal state machine that will count 16
clocks after the falling edge to /CS and then ihternally disable the device. The internal edge is or'd together with
the /CS so that the rising edge can be provided to /CS prior to the occurrence of the internal edge to also disable
the device.
general serial interface

The TLC5618 three-wire interface is compatible with the SPI, aSPI, and Microwire serial standards. The
hardware connections are shown in Figure 22 and Figure 23.
The SPI and Microwire interfaces transfer data in 8-bit bytes, therefore, two write cycles are required to input
data to the DAC. The aSPI interface, which has a variable input data length from 8 to 16 bits, can load the DAC
input register in one write cycle.
SCLK
DIN
TLC5618
CS
DOUT

SK
SO Mierowire
Port
1/0

51

Figure 24. Microwire Connection

~TEXAS

3-92

INSTRUMENTS
POST OFFICE BOX 655303 •. DALLAS, TEXAS 75265

TLC5618, TLC5618A
PROGRAMMABLE DUAL 12·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS156B- JULY 1997 - REVISED DECEMBER 1997

APPLICATION INFORMATION
SCK

SCLK

MOSI

DIN
TLC5618

1/0

CS
DOUT

SPI/QSPI
Port

MISO
CPOL

=1, CPHA =0

Figure 25. SPI/QSPI Connection
linearity, offset, and gain error using single end supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage
may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 24.

Output
Voltage

OVr-....~~------------------+
Negative {
Offset

DACCode

Figure 26. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage. The code is
calculated from the maximum specification for the negative offset.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-93

TLC5618, TLC5618A
PROGRAMMABLE DUAL 12·81T DIGITAL·TO·ANALOG CONVERTERS
SLAS156B-JULY 1997- REVISED DECEMBER 1:997

APPLICATION INFORMATION
power-supply bypassing and ground management
Printed circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane making sure that analog ground
currents are well managed.
A 0.1 IlF ceramic bypass capaCitor should be connected between Voo and AGND and mounted with short leads
as close as possible to the device. Use of ferrite beads may further isolate the system analog and digital power
supplies.
Figures 25 shows the ground plane layout and bypassing technique.

Figure 27. Power-Supply Bypassing
saving power
Setting the DAC register to all Os minimizes power consumption by the reference resistor array and the output
load when the system is not using the DAC.

ac considerations/analog feedthrough
Higher frequency analog input signals may couple to the output through internal stray capacitance. Analog
feedthrough is tested by holding CS high, setting the DAC code to all Os, sweeping the frequency applied to
REFIN, and monitoring the DAC output.

-!!1 TEXAS
3-94

.
INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5618M
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER
SGLS106- DECEMBER 1997

•
•
•
•
•
•
•
•
•

Programmable Settling Time to 0.5 LSB
3 I1s or 1511S Typ
Two 12-Bit CMOS Voltage Output DACs in
an a-Pin Package
Simultaneous Updates for DAC A
and DAC B
Single Supply Operation
3 Wire Serial Interface
High-Impedance Reference Inputs
Voltage Output Range ... 2 Times the
Reference Input Voltage
Software Power Down Mode
Internal Power-On Reset

•

•
•

Low Power Consumption:
3 mW Typ in Slow Mode
a mW Typ in Fast Mode
Input Data Update Rate of 1.21 MHz
Monotonic Over Temperature

applications
•
•
•
•
•

Battery Powered Test Instruments
Digital Offset and Gain Adjustment
Battery Operated/Remote Military Controls
Machine and Motion Control Devices
Military Communications

description

JG (C--DIP) PACKAGE
(TOP VIEW)

The TLC5618 is a dual 12-bit voltage output
digital-to-analog converter (DAC) with buffered
reference inputs (high impedance). The DACs
have an output voltage range that is two times the
reference voltage, and the DACs are monotonic.
The device is simple to use, running from a single
supply of 5 V. A power-on reset function is
incorporated to ensure repeatable start-up
conditions.

3:
w

D I N ( J S VDD
SCLK 2
7 OUT B
CS 3
6 REFIN
OUT A 4
5 AGND

5>
w
a:
a..

I-

Digital control of the TLC5618 is over a 3-wire CMOS-compatible serial bus. The device receives a 16-bit word
for programming and to produce the analog output. The digital inputs feature Schmitt triggers for high noise
immunity. Digital communication protocols include the SPITM, QSPITM, and Microwire™ standards.
The 8-terminal JG package allows digital control of analog functions in space-critical applications. The
TLC5618M is characterized for operation over the full military temperature range of -55°C to 125°C. The target
release timeframe for the TLC876M is estimated to be during the first half of 1998.
AVAILABLE OPTION
PACKAGE
TA

CERAMIC DIP
(JG)

-55°C to 125°C

TLC561SMJG

SPI and aSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
PRODUCT PREVIEW information concerns products in the formative or
desili" phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright © 1997, Texas Instruments Incorporated

3-95

o

~

c

oa:
a..

TLC5618M
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER
SGLSI 06 - DECEMBER 1997

functional block diagram

REFIN -",6_-,_ _-'---1

>-____--"4

OUT A

(Voltage Output)
AGND

-"-5-1r----;===;-+~"1

CS -".3--+--1----1

Control
Logic

SCLK ....
2_--f-+.....--I
DIN

L--"r""""'

-'--~+--t-t----+-t--j

____>-I

"'tJ

:D

oC

c:

o

-I
>--....--'-7

"'tJ

:D

m
m

<

R

R

:e

OUT B
(Voltage Output)

Terminal Functions
TERMINAL
NAME

NO.

DESCRIPTION

1/0

DIN

1

I

SCLK

2

I

Serial clock input

CS

3

I

Chip select, active low

OUTA

4

0

Serial data input

DAC A analog output
Analog ground

AGND

5

REFIN

6

I

OUTB

7

0

VDD

8

Reference voltage input
DAC B analog output
Positive power supply

~TEXAS

INSTRUMENTS
3-96

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

,

TLC5620C, TLC56201
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS081 D - NOVEMBER 1994 - REVISED APRIL 1997

N OR D PACKAGE

•

Four 8-Bit Voltage Output DACs

•

S-V Single-Supply Operation

•

Serial Interface

•

High-Impedance Reference Inputs

•

Programmable 1 or 2 Times Output Range

•

Simultaneous Update Facility

•

Internal Power-On Reset

•

Low-Power Consumption

•

Half-Buffered Output

(TOP VIEW)

GND
REFA
REFC
REFD
DATA

VDD

11
10

6

9
8

LDAC
DACA
DACB
DACC
DACD
LOAD

applications
•

Programmable Voltage Sources

•

Digitally Controlled Amplifiers/Attenuators

•

Mobile Communications

•

Automatic Test Equipment

•

Process Monitoring and Control

•

Signal Synthesis

description
The TLC5620C and TLC56201 are quadruple 8-bit voltage output digital-to-analog converters (DACs) with
buffered reference inputs (high impedance). The DACs produce an output voltage that ranges between either
one or two times the reference voltages and GND, and the DACs are monotonic. The device is simple to use,
running from a single supply of 5 V. A power-on reset function is incorporated to ensure repeatable start-up
conditions.
Digital control of the TLC5620C and TLC56201 are over a simple three-wire serial bus that is CMOS compatible
and easily interfaced to all popular microprocessor and microcontroller devices. The 11-bit command word
comprises eight bits of data, two DAC-select bits, and a range bit, the latter allowing selection between the times
1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be
written to the device, then all DAC outputs are updated simultaneously through control of LDAC. The digital
inputs feature Schmitt triggers for high noise immunity.
The 14-terminal small-outline (D) package allows digital control of analog functions in space-critical
applications. The TLC5620C is characterized for operation from O°C to 70°C. The TLC56201 is characterized
for operation from -40°C to 85°C. The TLC5620C and TLC56201 do not require external trimming.
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE

TA

to 70°C
-40°C to 85°C
O°C

~~~~~~~~o~:I: S=Hrc:~~sl;:~~:~~:~ :l ,.e~::i~~~~m~~is

standard warranty. Production processing does not necessarily include
testing of all parameters.

PLASTIC DIP

(D)

(N)

TLC5620CD

TLC5620CN

TLC5620lD

TLC5620lN

~TEXAS

Copyright © 1997, Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 65530,3 • DALLAS. TEXAS 75265

3-97

TLC5620C, TLC56201
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS081 D - NOVEMBER 1994 - REVISED APRIL 1997

functional block diagram

>---.----o12=_ DACA

>---.----01-=--1

DAce

>---...-,,10,- DACC

>--._...:9,-

ClK

1----r---I.................- - ,

DATA ...:6_ _-1

8

Serial

lOAD ~-L

Interface
______
....J

13
lDAC

Power-On
Reset

Terminal Functions
TERMINAL

1/0

DESCRIPTION

7

I

Serial interface clock. The input digital data is shifted into the serial interface
register on the falling edge of the clock applied to the CLK terminal.

DACA

12

0

DAC A analog output

DACB

11

0

DAC B analog output

DACC

10

DAC C analog output

DACD

9

0
0

DATA

6

I

Serial interface digital data input. The digital code for the DAC is clocked into the
serial interface register serially. Each data bit is clocked into the register on the
falling edge of the clock signal.

NAME

CLK

GND

NO.

DAC D analog output

1

I

Ground return and reference terminal

LDAC

13

I

Load DAC. When the LDAC signal is high, no DAC output updates occur when
the input digital data is read into the serial interface. The DAC outputs are only
updated when LDAC is taken from high to low.

LOAD

8

I

Serial Interface load control. When LDAC is low, the falling edge of the LOAD
signal latches the digital data into the output latch and immediately produces the
analog voltage at the DAC output terminal.

REFA

2

I

Reference voltage input to DAC A. This voltage defines the output analog range.

REFB

3

I

Reference voltage input to DAC B. This voltage defines the output analog range.

REFC

4

I

Reference voltage input to DAC C. This voltage defines the output analog range.

5

I

Reference voltage input to DAC D. This voltage defines the output analog range.

14

I

Positive supply voltage

REFD
VDD

~TEXAS

3-98

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

DACD

TLC5620C, TLC56201
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLASD81 D - NOVEMBER 1994 - REVISED APRIL 1997

detailed description
The TlC5620 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with
256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected
to the GND terminal and the other end is fed from the output of the reference input buffer. Monotonicity is
maintained by use of the resistor strings. Linearity qepends upon the matching of the resistor elements and upon
the performance of the output buffer. Since the inputs are buffered, the DACs always present a high-impedance
load to the reference source.
Each DAC output is buffered by a configurable-gain output amplifier that can be programmed to times 1 or times
2 gain.
On power up, the DACs are reset to CODE O.
Each output voltage is given by:
V dDACAIBIClD) = REF x

Cg~E

x (1

+

RNG bit value)

where CODE is in the range 0 to 255 and the range (RNG) bit is 0 or 1 within the serial control word.

Table 1. Ideal Output Transfer
07

06

05

04

03

02

01

00

0

0

0

0

0

0

0

0

GND

0

0

0

0

0

0

0

1

1

·· ··

(11256) x REF (1+RNG)

1

1

(1271256) x REF (1+RNG)

0

0

0

(1281256) x REF (1+RNG)

1

1

(2551256) x REF (1 +RNG)

·· ·· ··
·· ·· ··
0

1

1

1

0

0

1

1

1

··
··
1

0

1

··
··
1

0

1

··
··
1

·· ··

OUTPUT VOLTAGE

··
··

data interface
With lOAD high, data is clocked into the DATA terminal on each falling edge of ClK. Once all data bits have
been clocked in, lOAD is pulsed low to transfer the data from the serial input register to the selected DAC as
shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when lOAD goes low. When
lDAC is high during serial programming, the new value is stored within the device and can be transferred to
the DAC output at a later time by pulsing lDAC low as shown in Figure 2. Data is entered most significant bit
(MSB) first. Data transfers using two 8~clock cycle periods are shown in Figures 3 and 4.
ClK

-tI 14-

1--1

I

tsu(OATA-ClK)

tsu(lOAD-ClK) - - r - - -....-~.I

14-- tY(OATA-ClK)

1

OATA

_ I "-"-"'---"'--'-"'---.J

lOAO

Figure 1. LOAD-Controlled Update (LDAC

=Low)

-!11

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-99

TLC5620C,TLC56201
QUADRUPLE 8-81T DIGITAL·TO~ANALOG CONVERTERS
SLAS081 D - NOVEMBER 1994 - REVISED APRIL 1997

ClK

DATA

01

DO

tsu(lOAD-lDAC)~

'-.{'....--tl-

lOAD

tW(lDAC)~1

V

lDAC

I

DACUpdate

Figure 2. LDAC-Controlled Update

ClK

lOAD
LDAC _____________________________________________________________________

Figure 3. Load-Controlled Update Using 8-Bit Serial Word (LDAC

= Low)

ClK

lOAD
lDAC

Figure 4. LDAC-Controlled Update Using 8-Bit Serial Word
Table 2 lists the A 1 and AD bits a.nd the selection of the updated DACs. The RNG bit controls the DAC output
range. When RNG = low, the output range is between the applied reference voltage and GND, and when
RNG = high, the range is between twice the applied reference voltage and GND.

Table 2. Serial Input Decode
A1

AD

DACUPDATED

0

0

0

1

1

0

1

1

DACA
DACB
DACC
DACD

~TEXAS

3-100

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5620C, TLC56201
QUADRUPLE a·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS081D- NOVEMBER 1994 - REVISED APRIL 1997

linearity, offset, and gain error using single-end supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset voltage, the output voltage changes on the first code change. With a negative offset the output
voltage may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 5.

Output
Voltage

OV f---~~---------+
DACCode

Negative {
Offset

Figure 5. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below ground.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single-supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage. The code is
calculated from the maximum specification for the negative offset voltage.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-101

TLC5620C, TLC56201
QUADRUPLE 8-BIT DIGITAL-lO-ANALOG CO.NVERTERS
SLAS081 D- NOVEMBER 1994 - REVISED APRIL 1997

equivalent inputs and outputs
.INPUT CIRCUIT

OUTPUT CIRCUIT
VDD

- - . - - VDD
Input from
Decoded DAC
Register String

Vref
Input

DAC
Voltage Output

ToDAC
Resistor
String

ISINK
60l1A
Typical

~~--.-~- GND

--------~

GND

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage (Voo - GND) ................................................................. 7 V
Digital input voltage range ........... , ................................. GND - 0.3 V to Voo + 0.3 V
Reference input voltage range, VIO ...................................... GND - 0.3 V to Voo + 0.3 V
Operating free-air temperature range, TA: TLC5620C .................................... O°C to 70°C
TLC56201 ................................... -40°C to 85°C
Storage temperature range, Tstg ................................................... -50°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions
MIN
Supply voltage, VDD

NOM

4.75

High-level input voltage, VIH

MAX

UNIT

5.25

V
V

0.8 VDD

Low-level input voltage, VIL

0.8

-

Reference voltage, Vref [AIBIClD]
Analog full-scale output voltage, RL = 10 kO

VDD-1.5
3.5

V
V
V

Load resistance, RL

10

kO

Setup time, data input, tsu(DATA-CLK) (see Figures 1 and 2)

50

ns

Valid time, data input valid after CLKJ., tv(DATA-CLK) (see Figures 1 and 2)

50

ns

Setup time, CLK eleventh falling edge to LOAD, tsu(CLK-LOAD) '(see Figure 1)

50

ns

Setup time, LOADi to CLKJ., tsu(LOAD-CLK) (see Figure 1)

50

ns

Pulse duration, LOAD, tw(LOAD) (see Figure 1)

250

ns

Pulse duration, LDAC, tw(LDAC) (see Figure 2)

250

ns

Setup time, LOADi to LDACJ., tsu(LOAD-LDAC) (see Figure 2)
CLK frequency
Operating free-air temperature, TA

1

ITLC5620C
I TLC56201

~TEXAS

INSTRUMENTS
3-102

ns

0

POST OFFICE BOX 655303 • DALLAS, rEXAs 75265

0

70

-40

85

MHz

°c
°c

TLC5620C, TLC56201
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS081 D- NOVEMBER 1994 - REVISED APRIL 1997

electrical characteristics over recommended operating free-air temperature range, Voo =5 V ± 5%,
Vref = 2 V, x 1 gain output range (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IIH

High-level input current

VI = VDD

±10

I1A

IlL

Low-level input current

VI =OV

±10

I1A

IO(sink)

Output sink current

IO(source)

Output source current

Ci

Each DAC output

15
15

Supply current

VDD = 5 V

Reference input current

VDD = 5 V,

Vref= 2V

EL

Linearity error (end point corrected)

Vref= 2 V,

x 2 gain (see Note 1)

pF
2

ED

Differential-linearity error

Vre f=2 V,

x 1 gain (see Note 2)

EZS

Zero-scale error

Vre f=2 V,

x 2 gain (see Note 3)

Zero-scale-error temperature coefficient

Vref= 2 V,

x 2 gain (see Note 4)

Full-scale error

Vref= 2V,

x 2 gain (see Note 5)

Full-scale-error temperature coefficient

V re f=2 V,

x 2 gain (see Note 6)

Power-supply rejection ratio

See Notes 7 and 6

PSRR

rnA

I Input capacitance

IDD

NOTES:

I1A

2

I Reference input capacitance

Iref

EFS

20

0

rnA

±10

I!A

±1

LSB

±0.9

LSB

30

mV
I1V/oC

10
±60

mV

±25

11V!°C

0.5

mVN

1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects
of zero code and full-scale errors).
.
2. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes.
Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale-error temperature coefficient is given by: ZSETC = [ZSE(Tmax) - ZSE(T min)]Nref x 106/(Tmax - Tmin).
5. Full-scale error is the deviation from the ideal full-scale output (Vref - 1 LSB) with an output load of 10 kn.
6. Full-scale-error temperature coefficient is given by: FSETC = [FSE(T max) - FSE (T min)]Nref x 106/(T max - T min)·
7. Zero-scale-error rejection ratio (ZSE RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the zero-code output voltage.
6. Full-scale-error rejection ratio (FSE RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the full-scale output voltage.

operating characteristics over recommended operating free-air temperature range, Voo = 5 V ±5%,
Vref 2 V, x 1 gain output range (unless otherwise noted)

=

TEST CONDITIONS

MIN

TYP

1

MAX

UNIT

Output slew rate

CL = 100 pF,

RL = 10 kQ

Output settling time

To ±0.5 LSB,

CL = 100 pF,

Large-signal bandwidth

Measured at -3 dB point

100

kHz

RL = 10 kQ,

See Note 9

10

V/I1S
I1S

Digital crosstalk

CLK = I-MHz square wave measured at DACA-DACD

-50

dB

Reference feedthrough

See Note 10

-60

dB

Channel-to-channel isolation

See Note 11

-60

dB

Reference input bandwidth

See Note 12

100

kHz

NOTES:

9. Settling time is the time between a LOAD falling edge and the DAC output reaching full scale voltage within +/-0.5 LSB starting from
an initial output voltage equal to zero.
10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input = 1 V dc + 1 Vpp at.1 0 kHz.
11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex
with Vref input = 1 V dc + 1 Vpp at 10 kHz.
12. Reference bandwidth is the -3 dB bandwidth with an input at Vref = 1.25 V dc + 2 Vpp and with a full-scale digital-input code.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-103

TLC5620C, TLC56201
QUADRUP~E 8~BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS081 D - NOVEMBER 1994 - REVISED APRIL 1997

PARAMETER MEASUREMENT INFORMATION
TLC5620
OACA

OAce

1----...------,
10kn

CL=100pF

OACO

Figure 6. Slew, Settling Time, and Linearity Measurements

TYPICAL CHARACTERISTICS
NEGATIVE FALL AND SETTLING TIME

POSITIVE RISE AND SETILING TIME
LbAC

3

>

.
I

i

~

I

VOO=5 V
TA = 25°C
I
Code 00 10 FF Hex I
2 Range = x2
Vref = 2 V

~
~

!-

,I,

:;
Q.
:;

I
I

o

2

4

6

~

;g

\'
\

1

o
10

12

14

16

18

o

2

4

'"

6

8

10

I-Time-~

I-Time-~

Figure 7

Figure 8

~TEXAS

3-104

I

14

16

\

~

=/
8

2

:;
Q.
:;

oI

!

VOO=5 V
TA = 25°C
Code FF 10 00 Hex
Range =x2
Vref = 2 V

I

I

i

o

.

I

J

>

II

i

1

LbAC

3

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12

18

TLC5620C, TLC56201
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS081 D - NOVEMBER 1994 - REVISED APRIL 1997

TYPICAL CHARACTERISTICS
DAC OUTPUT VOLTAGE

DAC OUTPUT VOLTAGE

vs

vs

OUTPUT LOAD

OUTPUT LOAD
4

5
4.8

,r

>

3.5

I

4.6

>
I


~
"ii

-10

CJ

-14

II:
I

't:I

\

_ VOO=5 V
TA = 25°C
-18 _ Vref = 1.25 Vdc + 2 Vpp
Input Code = 255
I
-20
1
10
-16

\

I

c

'0;

CJ

-20

~
"ii

-30

II:
I

VOO=5V

CJ

-40 _ TA=25°C

.,>

\
\
\
\

-12

\

-10

III

J

CJ

/"'..

0

~

\~

-50
. -60
1000

V

1

10

100
f - Frequency - kHz

f - Frequency - kHz

Figure 14

Figure 13

APPLICATION INFORMATION
TLC5620
OACA

OAce

1-----.---1."."
R

OACO

NOTE A: Resistor R ;" 10 kn

Figure 15. Output Buffering Scheme

~TEXAS

3-106

\

Vref = 2 Vdc + 0.5 Vpp
Input Code = 255

\

100

_\

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

Vo

1000

10000

TLC5628C, TLC56281
OCTAL 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS089E - NOVEMBER 1994 - REVISED APRIL 1997

•
•
•
•
•
•
•
•
•

N OR ow PACKAGE
(TOP VIEW)

Eight 8-Bit Voltage Output DACs
5-V Single-Supply Operation
Serial Interface
High-Impedance Reference Inputs
Programmable 1 or 2 Times Output Range
Simultaneous Update Facility
Internal Power-On Reset
Low-Power Consumption
Half-Buffered Output

16
15

DACC

DACA
GND

14

REF1

DATA

13

LDAC

ClK

12
11

lOAD

10

DACH

9

DACG

DACB

VDD
DACE
DACF

DACD

REF2

applications
•
•
•
•
•
•

Programmable Voltage Sources
Digitally Controlled Amplifiers/Attenuators
Mobile Communications
Automatic Test Equipment
Process Monitoring and Control
Signal Synthesis

description
The TLC5628C and TLC56281 are octal8-bit voltage output digital-to-analog converters (DACs) with buffered
reference inputs (high impedance). The DACs produce an output voltage that ranges between either one or two
times the reference voltages and GND and are monotonic. The device is simple to use, running from a single
supply of 5 V. A power-on reset function is incorporated to ensure repeatable start-up conditions.
Digital control of the TLC5628C and TLC56281 are over a simple three-wire serial bus that is CMOS compatible
and easily interfaced to all popular microprocessor and microcontroller devices. The i2-bit command word
comprises eight bits of data, three DAC select bits, and a range bit, the latter allowing selection between the
times 1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values
to be written to the device, then all DAC outputs are updated simultaneously through control of LDAC. The digital
inputs feature Schmitt triggers for high-noise immunity:
The i6-terminal small-outline (D) package allows digital control of analog functions in space-critical
applications. The TLC5628C is characterized for operation from O°C to 70°C. The TLC56281 is characterized
for operation from -40°C to 85°C. The TLC5628C and TLC56281 do not require external trimming.
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
(OW)

TA

PLASTIC DIP
(N)

O°C to 70°C

TLC5628CDW

TLC5628CN

-40°C to 85°C

TLC56281DW

TLC56281N

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright © 1997, Texas Instruments Incorporated

3-107

TLC5628C, TLC56281
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E - NOVEMBER 1994 - REVISED APRIL 1997

functional block diagram

DACA

••
•
15 DACD

DACE

•••
10 DACH

CLK

5

DATA

4
12

LOAD

Serial
Interface

Power-On
Reset

13
LDAC

Terminal Functions
TERMINAL
NAME

NO.

1/0

DESCRIPTION

I

Serial interface clock. The input digital data is shifted into the serial interface register on the falling edge of the clock
applied to the ClK terminal.

ClK

5

DACA

2

0

DAC A analog output

DACB

1

0

DAC B analog output

DACC

16

0

DAC C analog output

DACD

15

0

DAC D analog output

DACE

7

0

DAC E analog output

DACF

8

0

DAC F analog output

DACG

9

0

DAC G analog output

DACH

10

0

DAC H analog output

DATA

4

I

Serial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially.
Each data bit is clocked into the register on the falling edge of the clock signal.

GND

3

I

Ground return and reference terminal

lDAC

13

I

load DAC. When lDAC is high. no DAC output updates occur when the input digital data is read into the serial
interface. The DAC outputs are only updated when lDAC is taken from high to low.

lOAD

12

I

Serial interface load control. When LDAC is low. the falling edge of the lOAD signal latcheS the digital data into
the output latch and immediately produces the analog voltage at the DAC output terminal.

REF1

14

I

Reference voltage input to DAC AI Bici D. This voltage defines the analog output range.

REF2

11

I

Reference voltage input to DAC ElF I G I H. This voltage defines the analog output range.

VDD

6

I

Positive supply voltage

~TEXAS

INSTRUMENTS
3-108

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC5628C, TLC56281
OCTAL 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS089E - NOVEMBER 1994 - REVISED APRIL 1997

detailed description
The TlC5628 is implemented using eight resistor-string DACs. The core of each DAC is a single resistor with
256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected
to GND and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use
of the resistor strings. Linearity depends upon the matching of the resistor segments and upon the performance
of the output buffer. Since the inputs are buffered, the DACs always present a high-impedance load to the
reference sources. There are two input reference terminals; REF1 is used for DACA through DACD and REF2
is used by DACE through DACH.
Each DAC output is buffered by a configurable-gain output amplifier, that can be programmed to times 1 or times
2 gain.
On power up, the DACs are reset to CODE O.
Each output voltage is given by:
VO(DACAIBICIDIEIFIGIH) = REF x

C~~E

x (1

+ RNG

bit value)

where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word.

Table 1. Ideal Output Transfer
D7

D6

D5

D4

D3

D2

D1

DO

0

0

0

0

0

0

0

0

GND

0

0

0

0

0

0

0

1

(1/256) x REF (1+RNG)

·· ·· ·•
·· ·· ··
0

1

1

1

0

0

1

1

1

··
··
1

0

1

··
··
1

0

1

·· ·· ··
·· ·· ··

OUTPUT VOLTAGE

··

1

1

1

(127/256) x REF (1+RNG)

0

0

o.

(128/256) x REF (1+RNG)

1

1

1

(255/256) x REF (1+RNG)

··

data interface
With lOAD high, data is clocked into the DATA terminal on each falling edge of ClK. Once all data bits have
been clocked in, lOAD is pulsed low to transfer the data from the serial input register to the selected DAC as
shown in Figure 1. When lDACis low, the selected DAC output voltage is updated when lOAD goes low. When
lDAC is high during serial programming, the new value is stored within the device and can be transferred to
the DAC output at a later time by pulsing lDAC low as shown in Figure 2. Data is entered most significant bit
(MSB) first. Data transfers using two 8-clock cycle periods are shown in Figures 3 and 4.
ClK

--!

I+-

I .,.II

tsu(DATA-ClK)
tv(DATA-ClK)

~

tsu(lOAD-ClK)

.

I

r

D4~---:~--------

DATA

---------------------------1\()
lOAD

tsu(ClK-lOAD)

~I+-J.I
I I tw(lOAD)

~

I
DAC Update

Figure 1. LOAD-Controlled Update (LDAC

= Low)

~TEXAS

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3-109

TlC5628C, TlC56281
OCTAl8-BIT DIGITAl-TO-ANAlOG CONVERTERS
SLAS089E - NOVEMBER 1994 - REVISED APRIL 1997

data interface· (continued)
ClK

D4~_____
· _____

DATA

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~\\

"

lOAD

lDAC

tsu(lOAD-lDAC)

...

\

..

----------------------------------------~\\

1"_.-+1_ _

Jt-I

~

I

tw(lDAC)~

V

DAC Update

Figure 2. LDAC-Controlled Update
ClK

lOAD
lDAC ________________________________________________________________-----

Figure 3, Load-Controlled Update Using 8-Bit Serial Word (LDAC

=Low)

ClK

Figure 4. LDAC-Controlled Update Using 8-Bit Serial Word

Table 2 lists the A2, A1, and AO bits and the selection of the updated DACs. The RNG bit controls the DAC output
range. When RNG = low, the output range is between the applied reference voltage and GND, and when
RNG = high, the range is between twice the applied reference voltage andGND.
Table 2. Serial Input Decode

-

A2

A1

AO

DACUPDATED

0
0
0
0
1
1

0
0
1
1
0

0
1

DACA
DAce
DACC
DACD
DACE
DACF
DACG
DACH

1
1

0
1
1

0
1
0
1
0
1

~TEXAS

3-110

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC5628C, TLC56281
OCTAL 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLASOB9E- NOVEMBER 1994 - REVISED APRIL 1997

linearity, offset, and gain error using single-end supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset voltage, the output voltage changes on the first code change. With a negative offset the output
voltage may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier, therefore, attempts to drive the output to a negative voltage. However, because the most
negative supply rail is ground, the output cannot drive below ground.
The output voltage remains at 0 V until the input code value produces a sufficient output voltage to overcome
the inherent negative offset voltage, resulting in the transfer function shown in Figure 5.

Output
Voltage

o V f----~~---------+
Negative {
Offset

DACCode

Figure 5. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces the breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below ground.
For a DAC, linearity is measured between the zero-input code (all inputs are 0) and the full-scale code (all inputs
are 1) after offset and full scale are adjusted out or accounted for in some way. However, single-supply operation
does not allow for adjustment when the offset is negative due to the breakpOint in the transfer function. So the
linearity in the unipolar mode is measured between full-scale code and the lowest code that produces a positive
output voltage.
The code is calculated from the maximum specification for the negative offset Voltage.

~TEXAS .
INSTRUMENTS
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3-111

TLC5628C, TLC56281
OCTAL 8·BIT DIGITAL·lO·ANALOG CONVERTERS
SLAS089E - NOVEMBER 1994 - REVISED APRIL 1997

equivalent of inputs and outputs
INPUT CIRCUIT

OUTPUT CIRCUIT

VDD

VDD

Input from
Decoded DAC
Register String

Vref
Input

DAC
Voltage Output

To DAC
Resistor
String

ISINK

SOIlA
Typical

84kQ

---il1------<_---il1-- GND

GND

-=-

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage (Voo -.GND) ................................................................. 7 V
Digital input voltage range, VIO ......................................... GND - 0.3 V to Voo + 0.3 V
Reference input voltage range .......................................... GND - 0.3 V to Voo + 0.3 V
Operating free-air temperature range, TA: TLC5628C .................................... O°C to 70°C
TLC56281 ................................... -40°C to 85°C
Storage temperature range, TSl9 ................................................... -50°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions
MIN
Supply voltage, VOO

NOM

4.75

High-level voltage, VIH

MAX

UNIT

5.25

V
V

0.8 VOO
0.8

low-level voltage, Vil
Reference voltage, Vref [AIBICIOIEIFIGIH]

VOO-1.5

Analog full-scale output voltage, Rl = 10 kQ

3.5

V
V
V

load resistance, Rl

10

kQ

Setup time, data input, tsu(OATA-ClK) (see Figures 1 and 2)

50

ns

Valid time, data input valid after ClK.!., tv(OATA-ClK) (see Figures 1 and 2)

50

ns

Setup time, ClK eleventh falling edge to lOAD, tsu(ClK-lOAD) (see Figure 1)

50

ns.

Setup time, LOAOt to ClK.!., tsu(lOAD-ClK) (see Figure 1)

50

ns

Pulse duration, lOAD, tw(lOAO) (see Figure 1)

250

ns

Pulse duration, LDAC, tw(lDAC) (see Figure 2)

250

ns

Setup time, lOAOt to LDAC.!., tsu(lOAD-lDAC) (see Figure 2)
ClK frequency
Operating free-air temperature, TA

1

ITlC5628C
I TlC56281

.~TEXAS

INSTRUMENTS

3-112

ns

0

POST OFFICE BOX 655303 • OALLAS. TEXAS 75265

MHz

0

70

°c

-40

85

°C

TLC5628C, TLC56281
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E - NOVEMBER 1994 - REVISED APRIL 1997

electrical characteristics over recommended operating free-air temperature range, Voo =5 V ± 5%,
Vref = 2 V, x 1 gain output range (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IIH

High-level input current

VI =VDD

±10

!lA

IlL

Low-level input current

VI=OV

±10

!lA

IO(sink)

Output sink current

IO(source)

Output source current

Ci

Each DAC output

15
15

Supply current

VDD= 5 V

Reference input current

VDD = 5 V,

Vref= 2 V

EL

Linearity error (end pOint corrected)

Vref= 2 V,

x 2 gain (see Note 1)

Differential-linearity error

Vref= 2 V,

x 2 gain (see Note 2)

EZS

Zero-scale error

Vref= 2 V,

x 2 gain (see Note 3)

Zero-scale-error temperature coefficient

Vre f=2V,

x 2 gain (see Note 4)

Full-scale error

Vref= 2 V,

x 2 gain (see Note 5)

Full-scale-error temperature coefficient

x 2 gain (see Note 6)
Vre f=2 V,
See Notes 7 and S

Power supply rejection ratio

pF
4

ED

PSRR

mA

l!nput capacitance

IDD

NOTES:

!lA

2

I Reference input capacitance

Iref

EFS

20

0

mA

±10

!lA

±1

LSB

±0.9

LSB

30
10

mV
!lVrC

±60

mV

±25

!lVrC

0.5

mVIV

1. Integral nonlmearlty (INL) IS the maximum deviation of the output from the line between zero. and full scale (excludmg the effects
of zero code and full-scale errors).
2. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes.
Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale-error temperature coefficient is given by: ZSETC = [ZSE(T max) - ZSE(T min)]lVref x 106/(T max - Tmin)·
5. Full-scale error is the deviation from the ideal full-scale output (Vref - 1 LSB) with an output load of 10 k!l
6. Full-scale error temperature coefficient is given by: FSETC = [FSE(T max) - FSE (Tmin)]lVref x 106/(T max - Tmin).
7. Zero-scale-error rejection ratio (ZSE RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of
this sign'll imposed on the zero-code output voltage.
S. Full-scale-error rejection ratio (FSE RR) is measured by varying the VDD from 4."5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the full-scale output voltage.

operating characteristics over recommended operating free-air temperature range, Voo =5 V ± 5%,
Vref = 2 V, x 1 gain output range (unless otherwise noted)
TEST CONDITIONS

Output slew rate

CL = 100 pF,

RL= 10 kn

Output settling tima

To±O.5 LSB,

CL = 100 pF,

Large signal bandwidth

Measured at -3 dB point

RL=10kQ,

MIN

See Nota 9

TYP

MAX

UNIT

1

V/!lS

10
100

!is
kHz

Digital crosstalk

CLK = I-MHz square wave measured at DACA-DACD

-50

dB

Reference feedthrough

See Note 10

-60

dB

Channel-to-channel isolation

Sea Note 11

-60

dB

Reference input bandwidth

See Note 12

100

kHz

NOTES: 9. Settling time is the time between a LOAD falling edge and the DAC output reaching full-scale voltage within ±O.S LSB starting from
an initial output voltage equal to zero.
10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input = 1 V dc + 1 Vpp at 10kHz.
11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex
with Vref input = 1 V dc + 1 Vpp at 10 kHz.
12. Reference bandwidth is the -3 dB bandwidth with an input at Vref = 1.25 V dc + 2 Vpp and with a full-scale digital input code.

"!!1
TEXAS
INSTRUMENTS
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3-113

TLC5628C, TLC56281
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E - NOVEMBER 1994 - REVISED APRIL 1997

PARAMETER MEASUREMENT INFORMATION
TLC5628
DACA 1-------411----.

DAce

10kQ

CL=100pF

DACH

Figure 6. Slew, Settling Time, and Linearity Measurements

TYPICAL CHARACTERISTICS
POSITIVE RISE AND SETTLING TIME
LbAC

6

>

.,
E
I

~

c.
I

I

I
I

~

:

o
o

2

4

6

.,

~

!
II

4

~

io
I

\

\'
\

2

~

V
8

o
10

12

14

16

1&

o

2

t-Time-~s

4

"

6

8

10

t-Time-~s

FigureS

Figure 7

~TEXAS

3-114

I

VDD=5 V
TA = 25°C
Code FF to 00 Hex
Range = x2
Vref = 2 V

I

I
2

II

I

>
h.

,I,

:;

LbAC

6

I

VDD=5 V
TA = 25°C
I
Code 00 to FF Hex I
4 Range = x2
Vref=2V

:;

o

NEGATIVE FALL AND SETTLING TIME

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12

14

16

18

TLC5628C, TLC56281
OCTAL 8-BIT DlGITAL-TO-ANALOG CONVERTERS
SLAS089E - NOVEMBER 1994 - REVISED APRIL 1997

TYPICAL CHARACTERISTICS
DAC OUTPUT VOLTAGE

DAC OUTPUT VOLTAGE

vs

vs

OUTPUT LOAD

OUTPUT LOAD
4

5
4.8

>

3.5

J'fI'

4.6

>
I

I

CD
CI

I

3

4.4

,g!
~

,g!
~

2.5

4.2

"S
Co
"S

4

"S
Co
"S

2

CD
CI

0

~
Q
I

~

0

(.)

ct

3.8

Q

I

VOO=5 V,
Vref = 2.5 V,
Range = 2x

3.4

-

o

10

20

30 40 50 60 70 80
RL - Output Load - kn

Voo = 5 V,
Vref = 3.5 V,
Range = 1)(

0.5

3.2

3

1.5

~

3.6

o
o

90 100

10

20

30

40

7

I

~
'"
~
'"

6

(.)
CD

5

0
UI

4

"S
.&

'"

3

I

2

0

I

I

80

90

vs

OUTPUT VOLTAGE

TEMPERATURE

-r-... '~

100

SUPPLY CURRENT

vs
1.2
VOO= 5 V
TA = 25°C
Vref = 2 V
Range = x2
Input Code = 255

-

1.15

ct

E

"\ I\.

1.1

I

\

1:
~

1.05

~
Range = x2
Input Code = 255

--

r---......

VOO =5 V
Vref = 2V

"-

'>-"

(.)

\

Ii
Co

c1J

0.95

I

I

.'"

I
70

Figure 10

OUTPUT SOURCE CURRENT

ct
E

60

RL - Output Load - kQ

Figure 9

8

50

-

Q

E

0

0.9

0.85

§'
2
3
4
Vo - Output Voltage - V

5

0.8
-50

o

50

100

t - Temperature - °C

Figure 11

Figure 12

~TEXAS

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3-115

TLC5628C, TLC56281
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E- NOVEMBER 1994 - REVISED APRIL 1997

TYPICAL CHARACTERISTICS
RELATIVE GAIN

RELATIVE GAIN

vs

vs

FREQUENCY

FREQUENCY
10

0

"

-2

-4

..,
III

-6

\

I

c
'iii
0

-8

.~
~
IX:

-10
-12
-14

III

\

1

10

100

1\

I

\
\

..

-20

!!

-30

.!
I

0

VOO=5 V
-40 I- TA = 25'C
Vref = 2 Vdc + 0.5 Vpp
Input Code = 255
-50
-60

1000

1

10

100
f - Frequency - kHz

f - Frequency - kHz

Figure 13

Figure 14

APPLICATION INFORMATION
TLC5628
OACA F--- _ - - I

OAce

R

OACH
NOTE A: Resistor R "" 10 kQ

Figure 15. Output Buffering Scheme

C~TEXAS
3-116

\
\

.i!:

\

I

\

-10

c

'iii
0

\
\

-16 r- VOO=5V
TA=25'C
-18 I- Vref = 1.25 Vdc + 2 Vpp
Input Code = 255
-20

..,

1

I

0

~

0

\.

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

Vo

\~

V

1000

10000

TLC7225C, TLC72251
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS109A- OCTOBER 1996 - REVISED APRIL 1997

•

Four 8·Bit D/A Converters With Individual
References

•

Direct Bipolar Operation Without an
External Level-Shift Amplifier

•

Microprocessor Compatible

•
•

TTL/CMOS Compatible
Single Supply Operation Possible

•

Simultaneous Update Facility

•

Binary Input Coding

DWPACKAGE
(TOP VIEW)

OUTB
OUTA
Vss
REFB
AGND
DGND
LDAC
(MSB) DB7
DB6
OB5
DB4

applications
•

Process Control

•

Automatic Test Equipment

•

Automatic Calibration of Large System
Parameters e.g., Gain/Offset

4

8
9

OUTC
OUTO
VDD
REFC
REFO
AO
A1
WR
DBO (LSB)
DB1
DB2
OB3

description
The TLC7225 consists of four 8-bit vOltage-output digital-to-analog converters (DACs), with output buffer
amplifiers and interface logic with double register-buffering.
Separate on-Chip latches are provided for each of the DACs. Data is transferred into one of these data latches
through a common 8-bit TTUCMOS-compatible (5 V) input port. Control inputs AO and A 1 determine which DAC
is loaded when WR goes low. Only the data held in the DAC registers determines the analog outputs of the
converters. The double register buffering allows simultaneous update of all four outputs under control of LDAC.
All logic inputs are TTL- and CMOS-level compatible and the control logic is speed compatible with most 8-bit
microprocessors. Each DAC includes an output buffer amplifier capable of driving up to 5 mA of output current.
The TLC7225 performance is specified for input reference voltages from 2 V to VDO - 4 V with dual supplies.
The voltage-mode configuration of the DACs allow the TLC7225 to be operated from a single power-supply rail
at a reference of 1Q V.
The TLC7225 is fabricated in a LinBiCMOSTM process that has been specifically developed to allow high-speed
digital logic circuits and precision analog circuits to be integrated on the same chip. The TLC7225 has a common
8-bit data bus with individual DAC latches. This provides a versatile control architecture for simple interface to
microprocessors. All latch-enable signals are level triggered.
Combining four DACs, four operational amplifiers, and interface logic into a small, O.3-inch wide, 24-terminal
SOIC allows significant reduction in board space requirements and offers increased reliability in systems using
multiple converters. The pinout optimizes board layout with all of the analog inputs and outputs at one end of
the package and all of the digital inputs at the other.
The TLC7225C is characterized for operation from QOC to 7QoC. The TLC72251 is characterized for operation
from -40°C to 85°C.

LinBiCMOS is a trademark of Texas Instruments Incorporated.

~TEXAS

Copyright © 1997. Texas Instruments Incorporated

INSTRUMENTS
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3-117

TLC7225C, TLC72251
QUADRUPLE 8·BIT DIGITAL·lO·ANALOG CONVERTERS
SLAS109A- OCTOBER 1996, - REVISED APRIL 1997

AVAILABLE OPTIONS
PACKAGED DEVICES
TA

SMALL OUTLINE
(DW)

QOC to 70°C

TLC7225CDW

-40°C to 85°C

TLC72251DW

functional block diagram
REFA --=5'--_ _ _ _ _ _ _ _ _ _ _ _ _-::12 . OUTA
>--e-_....

REFB~4~--_+---~-~----""_

>-....

1
_.L

OUTB

DBO-DB7 9-16
8
REFC--=2~1_ _ _._-~_+~_r----_.
>-....-"'24"- OUTC
REFD --=2:;;O_ _ _._--+-+~_r----___::L
>--e--",23,,- OUTD

LDAC -=8'-------1-++-1----'
WR 17
AO 19
A1

18

L-~-----'

schematic of outputs
EQUIVALENT ANALOG OUTPUT
VDD -----1.-------,

__ .--J
Output

VSS - - - . - - - - - - - '

~TEXAS

3-118

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC7225C, TLC72251
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS109A- OCTOBER 1996 - REVISED APRIL 1997

Terminal Functions
TERMINAL
NAME

NO.

AGND

6

AO,AI

18,19

DGND

?

DBO- DB?

9-16

1/0

DESCRIPTION
Analog ground

I

DAC select inputs
Digital ground

I

Digital DAC data inputs
Load DAC. A high level simultaneously loads all four DAC registers. DAC registers are transparent when LDAC
is low.

LDAC

8

OUTA

2

a

DACAoutput

OUTB

1

a

DACBoutput

OUTC

24

a

DACC output

aUTO

23

a

DACD output

REFA

5

I

Voltage reference input to DACA

REFB

4

I

Voltage reference input to DACB

REFC

21

I

Voltage reference input to DACC

I

Voltage reference input to DACD

REFD

20

VDD

22

Positive supply voltage

VSS

3

Negative supply voltage

WR

17

I

Write input selects DAC transparency or latch mode

absolute maximum ratings over operating free-air temperature range (unless otherwise note)t
Supply voltage range, VDD: to AGND or DGND ....................................... -0.3 V to 17 V
to VSS .................................................. -0.3 V to 24 V
Supply voltage range, Vss: to'AGND or DGND ...... ,"', ...... , ........ , .............. -7 V to VDD
Voltage range between AGND and DGND ........................................... -0.3 V to VDD
Input voltage range, VI (to DGND) ......................... : .................. -0.3 V to VDD + 0.3 V
Reference voltage range, Vref (to AGND) ............................................ -0.3 V to VDD
Output voltage range, Va (to AGND) (see Note 1) ........................................ Vss to VDD
Continuous total power dissipation at (or below) TA = 25°C (see Note 2) ....................... 500 mW
Operating free-air temperature range: C suffix ................................... ,..... O°C to 70°C
I suffix ........................................ -40°C to 85°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1 116 inch) from case for 10 seconds ............................... 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device, These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability,
NOTES: 1. Output voltages may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically short circuit
current to AGND is 50 mA,
2, For operation above TA = 75'C derate linearly at the rate of 2,0 mW/'C_

~TEXAS

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3-119

TLC7225C, TLC72251
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS109A- OCTOBER 1996 - REVISED APRIL 1997

recommended operating conditions
MIN

MAX

Supply voltage, VDD

11.4

16.5

V

Supply voltage, VSS

-5.5

0

V

High-level input voltage, VIH

2

V

Low-level input voltage, VIL

0.8

Reference voltage, Vref

2

Load resistance, RL

2

Operating free-air temperature, TA

IIC suffix
.
I suffix

UNIT

VDD-4

V
V

kg

0

70

°C

-40

85

°C

MAX

UNIT

timing requirements (see Figure 1)
PARAMETER

TEST CONDITIONS

tsu(AW)

Setup time, address valid before WR,j,

tsu(DW)

Setup time, data valid before WRf

VDD = 11.4 V to 16.5 V,

th(AW)

Hold time, address valid after WRf

VDD = 11.4 V to 16.5V,

th(DW)

Hold time, data valid after WRf

VDD = 11.4 V to 16.5 V,

twl

Pulse duration, WR low

VDD = 11.4 V to 16.5 V,

tw2

Pulse duration, LDAC low

VDD = 11.4 V to 16.5 V,

~TEXAS

INSTRUMENTS
3--120

POST OfFICE BOX 655303 • DALLAS, TEXAS 75265

MIN

0

ns

VSS = 0 or-5 V

45

ns

Vss=00r-5V

0

ns

VSS = 0 or-5 V

10

ns

VSS = 0 or-5 V

50

ns

VSS = 0 or-5 V

50

ns

TLC7225C, TLC72251
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS109A- OCTOBER 1996 - REVISED APRIL 1997

electri~al

characteristics over recommended operating free-air temperature range

reference inputs (all supply ranges)
TEST CONDITIONS

PARAMETER
ri
Ci

Input resistance, REFA, REFB, REFC, REFD
Input capacitance, REFA, REFB, REFC, REFD

ac feedthrough

TYP

1.5

4

DAC loaded with all 1s
DAC loaded with all Os

Channel-to-channel isolation

MIN

Vref = 10 Vpp sine wave at 10 kHz

MAX

UNIT
kn

300

pF

65

pF

60

dB

70

dB

dual power supply over recommended supply and reference voltage ranges, AGND = DGND = 0 V (unless
otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

TYP

II

Input current, digital

VI = 0 orVDD

IDD

Supply current, VDD

VI = VIL or VIH,

No load

10

ISS

Supply current, VSS

VI = VIL or VIH,

No load

4

Power supply sensitivity

!NDD=±5%

Ci

Input capacitance

single power supply, VOO

MAX

UNIT

±1

~

16

rnA

10

rnA

0.01

%/0/0

I Digital inputs

8

pF

=14.25 V to 15.75 V, VSS =AGND =DGND =0 V, Vref (A, e, C, D) =10 V

PARAMETER

TEST CONDITIONS

II

Input current, digital

VI = OorVDD

IDD

Supply current, VDD

VI = VIL or VIH,

Ci

Input capacitance

Power supply sensitivity

No load

!NDD =±5%

I Digital inputs

MIN

TYP
5

MAX

UNIT

±1

~

13

rnA

0.01

8

0/0

/0/0

pF

~TEXAS

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3-121

TLC7225C, TLC72251
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS.l09A- OCTOBER 1996 - REVISED APRIL 1997

operating characteristics over recommended operating free-air temperature range
dual power supply over recommended supply and reference voltage ranges, AGND = DGND = 0 V (unless
otherwise noted)
.
PARAMETER

TEST CONDITIONS

MIN

ts

Settling time to 1/2 LSB

II Positive full scale
Negative full scale

Vref{A, B, C, D)

7
a

Total unadjusted error

VDD

Integral nonlinearity (INL)

VDD

= 15 V ±5%,
= 15 V ±5%,

±2

LSB

±1

LSB

±1

LSB

±2

LSB

Differential nonlinearity (DNL)

VDD = 15 V ±5%,

Full-scale error

VDD

= 15 V ±5%,

EG

Gain error

VDD';' 15 V ±5%,

Vref(A B, C, D) = 10 V

IZero-code error

VDD = 14 V to 16.5 V,

Vref(A, B C Dl

Vref(A, B, C, D)

±0.25

= 10 V

Vref(A, B, C, D) = 0

TEST CONDITIONS

=10 V (unless otherwise

MIN

TYP

20

Negative full scale

a

Resolution

Full-scale error
Full-scale error

UNIT
V/~s

Total unadjusted error

VDD = 14 V to 16.5 V,
Vref{A, B, C, D) = 10 V

Zero-code error

Bits
LSB

±2

LSB
ppm/DC
~V;oC

±50
±1

Digital crosstalk or feedthrough glitch impulse area

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

50

~s

±2

±20

Differential nonlinearity error (DNL)

3-122

MAX

5

Positive fu II scale

Temperature coefficient of gain

mV
nV-s

2

Slew rate

EFS

±ao

50

single power supply, VOO =14.25 V to 15.75 V, VSS =AGND =DGND =0 V, Vref(A B C 0)
noted)
, , ,

Settling time to 1/2 LSB

~V/oC

±50
±20

PARAMETER

LSB
ppm/DC

±20

Zero-code error
Digital crosstalk or feedthrough glitch
impulse area

~s

Bits

Vref(A B, C, D) = 10 V

EFS

I Full-scale error

UNIT
V/iJS

= 10 V

= 10 V
Vref(A B C, D) = 10 V
Vref(A, B, C, D) = 10 V

ts

MAX

5

Resolution

Temperature coefficient
of gain

TYP

2.5

Slew rate

LSB
nV-s

TLC7225C, TLC72251
QUADRUPLE a-BIT DIGITAL-TO-ANALOG CONVERTERS
SLASI 09A - OCTOBER 1996 - REVISED APRIL 1997

PARAMETER MEASUREMENT INFORMATION

Addres~

x================================ ::0

I4-*- th(AW)

tsu(AW) ---l4-+I

!+-- tw1 --+i

WR

t------------------------------------------- ::0

----"1\

I
I

r

tW2~

i4

LOAC--------"T:----------"""'\

i4------t-

I

tSU(OW)~

Oata In

------~x: ~a~:~

th(OW)

VOO
0V

I...._ _..L.

I

X'-_______________ ::0

NOTES: A. tr = tl = 20 ns over VDD range.
B. The timing-measurement reference level is equal to VIH + VIL divided by 2.
C. If LDAC is activated prior to the riSing edge of WR, then it must remain low for at least tw2 after WR
goes high.

Figure 1. Write-Cycle Voltage Waveforms

TYPICAL CHARACTERISTICS
OUTPUT CURRENT

vs

OUTPUT VOLTAGE

OUTPUT VOLTAGE

200
150

<

E

100 -

OUTPUT CURRENT (SINK)

vs

(

r--

Source Current ~
Short·Circuit
Limiting

700

~
VOO=15V _

<::1.

l

I

:i"
c

!a.

I

C
~
:::I

(J

50

c
~

::

0

'Sa.
'S

VSS =-5 V
400
300

tI

(
lk-'

I
I
VSS=O

0

I

I

TA=25°C
VSS=-5 V
OBO-OB7=OV

-0.2

.9

200
100

-0.3
-0.4

500

:::I
(J

'S
a.
'S
0 -0.1

.9

TA = 25°C
VOO=15V
600

}

-2

Sinking
.Current Source

-1
o
Vo - Output Voltage - V

2

o
o

2 . 3

4

5

6

7

8

9

10

Vo - Output Voltage - V

Figure 2

Figure 3

~TEXAS

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3-123

TLC7225C, TLC72251
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS109A-OCTOBER 1996 - REVISED APRIL 1997

APPLICATION INFORMATION

specification ranges
For the TLC7225 to operate to rated specifications, the input reference voltage must be at least 4 V below the
power supply voltage at the Voo terminal. This voltage differential is the overhead voltage requirE1d by the output
amplifiers.
The TLC7225 is specified to operate over a Voo range from 12 V ± 5% to 15 V ± 10% (Le., from 11.4 V to 16.5 V)
with a Vss of - 5 V ± 10%. Operation is also specified for a single supply with a Voo of 15 V ± 5%. Applying a
Vss of - 5 V results in improved zero-code error, improved output sink capability with outputs near AGND, and
improved negative-going settling time.
Performance is specified over the range of reference voltages from 2 V to (VDO - 4 V) with dual supplies. This'
allows a range of standard refence generators to be used such as the TL 1431, with an adjustable 2.5-V bandgap
reference. Note that an output voltage range of 0 V to 10 V requires a nominal 15 V ± 5% power supply Voltage.

DAC section
The TLC7225 contains four, identical, 8-bit voltage-mode DACs. Each converter has a separate reference input.
The output voltages from the converters have the same polarity as the reference voltages, thus allowing single
supply operation.
The simplified circuit diagram for channel A is shown in Figure 4. Note that AGND (terminal 6) is common to
all four DACs.
R

R

R

OUTA
2R
DB7

REFA -+-_.-+_---'\ .....f--+-_.-+_--'
AGND

-~-:----<~---'\\--*-----1

__- - - '
Shown For AII1s On DAC

Figure 4. DAC Simplified-Circuit Diagram
The input impedance at any of the reference inputs is code dependent and can vary from 1.4 kn minimum to
an open circuit. The lowest input impedance at any reference input occurs when that DAC is loaded with the
digital code 01010101. Therefore, it is important that the reference source presents a low output impedance
under changing load conditio_ns. The nodal capacitance at the reference terminals is also code dependent and
typically varies from 60 pF to 300 pF.
Each OUTx terminal can be considered as a digitally programmable voltage source with an output voltage of:
VOUTx = Dx X VREFx
where Dx is the fractional representation of the digital input code and can vary from 0 to 255/256.
The output impedance is that of the output buffer amplifier.

~TEXAS

3-124

INSTRUMENTS
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TLC7225C, TLC72251
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS109A- OCTOBER 1996 - REVISED APRIL 1997

APPLICATION INFORMATION

output buffer
Each voltage-mode DAC output is buffered by a unity-gain non inverting amplifier. This buffer amplifier is capable
of developing 10 V across a 2-kQ load and can drive capacitive loads of 3300 pF.
The TLC7225 can be operated as a single or dual supply; operating with dual supplies results in enhanced
performance in some parameters which cannot be achieved with a single-supply operation. In a single supply
operating (Vss = 0 V = AGND) the sink capability of the amplifier, which is normally 400 !lA, is reduced as the
output voltage nears AGND. The full sink capability of 400 IlA is maintained over the full output voltage range
by tying Vssto -5 V. This is indicated in Figure 3.
Settling time for negative-going output signals approaching AGND is similarly affected by VSS. Negative-going
settling time for single supply operation is longer than for dual supply operation. Positive-going settling-time is
not affected by Vss.
Additionally, the negative Vss gives more headroom to the output amplifiers which results in better zero code
performance and improved .slew rate at the output than can be obtained in the single-supply mode.

digital inputs
The TLC7225 digital inputs are compatible with either TTL or 5-V CMOS levels. To minimize power supply
currents, it is recommended that the digital input voltages be driven as close to the supply rails (VDD and DGND)
as practically possible.

interface logic information
The TLC7225 contains two registers per DAC, an input register and a DAC register. Address lines AO and A 1
select which input register accepts data from the input port. When the WR signal is low, the input latches of the
selected DAC are transparent. The data is latched into the addressed input register on the rising edge of WR.
Table 1 shows the addressing for the input registers on the TLC7225.

Table 1. TLC7225 Addressing

CONTROL
INPUTS
A1
AD
L
L
L
H
,L
H
H

H

SELECTED INPUT
REGISTER
DAC A input register
DAC B input register
DAC C input register
DAC D input register

Only the data held in the DAC register determines the analog output of the converter. The LDAC signal is
common to all four DACs and controls the transfer of information from the input registers to the DAC registers.
Data is latched into all four DAC registers simultaneously on the rising edge of LDAC. The LDAC signal is level
triggered and, therefore, the DAC registers may be made transparent by tying LDAC low (the outputs of the
converters responds to the data held in their respective input latches). LDAC is an asynchronous signal and
is independent of WR. This is useful in many applications. However, in systems where the asynchronous LDAC
can occur during a write cycle (or vice versa) care must be taken to ensure that incorrect data is not latched
through to the output. In other words, if LDAC is activated prior to the rising edge of WR (or WR occurs during
LDAC), then LDAC must stay low for a time of tw2 or longer after WR goes high to ensure that the correct data
is latched through to the output. Table 2 shows the truth table for TLC7225 operation. Figure 5 shows the input
. control logic for the device and the write cycles timing diagram is shown in Figure 1.

~TEXAS

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3-125

TLC7225C, TLC72251
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLASI 09A - OCTOBER 1996 - REVISED APRIL 1997

APPLICATION INFORMATION

Table 2. TLC7225 Truth Table
CONTROL INPUTS
WR

FUNCTION

LDAC

H

H

No operation. Device not selected

L

H

Input register of selected DAC is transparant.

t

H

Input register of selected DAC Is latched.

H

L

All four DAC registers are transparent (i.e., outputs respond to data
held in respective input registers) input registers are latched.

H

i

All four DAC registers are latched.

L

L

DAC registers and,selected input register are transparent. Output
follows input data for selected channel.

X)--~:t:=:r-\:>----

A1

18

To Latch A

1 : ) - - - To Latch B

1 : ) - - - To Latch C

L===t:::f-~>---Figure 5. Input Control Logic

~TEXAS

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To Latch 0

TLC7225C, TLC72251
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS109A - OCTOBER 1996 - REVISED APRIL 1997

APPLICATION INFORMATION

ground management and layout
The TLC7225 contains four reference inputs that can be driven from ac sources (see multiplying DAC using ac
input to the REF terminals section) so careful layout and grounding is important to minimize analog crosstalk
between the four channels. The dynamic performance of the four DACs depends upon the optimum choice of
board layout. Figure 6 shows the relationship between input frequency and channel-to-channel isolation.
Figure 7 shows a printed circuit board layout that minimizes crosstalk and feedthrough. The four input signals
are screened by AGND. Vref was limited between 2 V and 3.24 V to avoid slew-rate limiting effects from the
output amplifier during measurements.
-80
-70
III
'0
I

s::

-60

Vref

0

:;

-50

-----...

=1.24 Vpp

=

TA 25°C
VOO=15V
VSS=-5V -

~

'0

.!/l

-40

~

-30
-20
10 k

20 k

50k

100k

200k

fl - Input Frequency - Hz

500k

1M

'.

Figure 6. Channel-to-Channel Isolation
System GNO

OUTB 0

-0

0

OUTC

OUTA 0

-0

0

OUTO

VSS 0

-0

0

VOO

REFB 0

-0

0

REFC

REFA 0

-0

0

REFO

-0

0

-0

0

AGND
OGND

--------0-

MSB - 0 -0-0-0-

----------0-

- 0 - LSB
-0-

-0-

-0-

Figure 7. Suggested PCB Layout (Top View)

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TLC7225C, TLC72251
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS1 09A - OCTOBER 1996 - REVISED APRIL 1997

APPLICATION INFORMATION

unipolar output operation
The unipolar output operation is the basic mode of operation for each channel of the TLC7225, with the output
voltages having the same positive polarity as Vref. The TLC7225 can be operated with a single supply
(Vss = AGND) or with positive or negative supplies. The voltage at Vrel must never be negative with respect
to DGND to prevent parasitic transistor turn-on. Connections for the unipolar output operation are shown in
Figure 8. The transfer values are shown in Table 3.

~l
~l

2 OUTA

REFA~

DACA

REFB

~

DACB

REFC

~

DACC

Lp,l

REFD

~

DACD

~ourn
VSS

I

1

24

OUTB

OUTC

DGND

AGND

L!

I

-::-

Figure 8. Unipolar Output Circuit
Table 3. Unipolar Code
DAC LATCH CONTENTS
MSB
LSB

1111

1111

+ Vret (255)
256

0001

+ Vret 256

1000

0000

0111

1111

C29)
V
C28)
+ ret 256
+ Vret C27)
256

0000

0001

+ Vret

0000

0000

1000

,

NOTE 3: 1 LSB = (V ret

3-128

ANALOG OUTPUT

=

(2~6)
OV

r8) = Vret (2~6)

-!i1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

Vret

+ -2-

TLC7225C, TLC72251
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS1 09A - OCTOBER 1996 - REVISED APRIL 1997

APPLICATION INFORMATION
AGND bias for direct bipolar-output operation
The TLC7225 can be used in bipolar operation without adding additional external operational amplifiers by
biasing AGND to Vss as shown in Figure 9. This configuration provides an excellent method for providing a
direct bipolar output with no additional components. The transfer values are shown in Table 4.

Output range
(5 Vto-5 V)

t

Digital inputs omitted for clarity.

Figure 9. AGND Bias for Direct Bipolar-Output Operation
Table 4. Bipolar (Offset Binary) Code
DAC LATCH CONTENTS
LSB
MSB

ANALOG OUTPUT

C27)

1111

1111

+ Vref 128

1000

0001

+ Vref

1000

0000

0111

1111

0000

0001

0000

0000

(1~8)
OV

- Vref

(1~8)

C27)
-V ref C28)
128
- Vref 128

= - Vref

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3-129

TLC7225C, TLC72251
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS109A - OCTOBER 1996 - REVISED APRIL 1997

APPLICATION INFORMATION
AGND bias for positive output offset
The TLC7225 AGND terminal can be biased above or below the system ground terminal, DGND, to provide an
offset-zero analog-output voltage level. Figure 10 shows a circuit configuration to achieve this for channel A of
the TLC7225. The output voltage, Vo at aUTA, can be expressed as:
Va

=

V bias

+ DA

(VI)

where DA is a fractional representation of the digita.l input word (0::; D ::; 255/256).

rV~ND

VO(OUTA)

-~~-{6

t

Digital inputs omitted for clarity.

Figure 10. AGND Bias Circuit
Increasing AGND above system ground reduces the output range. VDD - Vref must be at least 4 V to ensure
specified operation. Since the AGND terminal is common to all four DACs, this method biases up the output
voltages of all the DACs in the TLC7225. Supply voltages VDD and VSS for the TLC7225 should be referenced
to DGND.

~TEXAS

3-130

INSTRUMENTS
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TLC7225C, TLC72251
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS109A-OCTOBER 1996 - REVISED APRIL 1997

APPLICATION INFORMATION
bipolar-output operation using external amplifier
Each of the DACs of the TLC7225 can also be individually configured to provide bipolar output operation using
an external amplifier and two resistors per channel. Figure 11 shows a circuit used to implement offset binary
coding (bipolar operation) with DAC A of the TLC7225. In this case (see equation 1):
_
V0 - 1

R2 (
)
R2 (
)
+ FIT
D A V ref - FIT V ref

= R2
V 0 = (2D A

(1 )

with R1

- 1) V ref

where DAis a fractional representation of the digital word in latch A.
Mismatch between R1 and R2 causes gain and offset errors. Therefore, these resistors must match and track
over temperature. The TLC7225 can be operated with a single supply or from positive and negative supplies.
REFA - - - . _ - - - - - - - - ,

,,
,,'.--..1..-..,

R2t

5
1""--

15 V

Vo

,

L.. _ _ _ _ _ _ _ _ _ _ .J

tR1 =R2=10kQ±O.1%

Figure 11. Bipolar-Output Circuit

multiplying DAC using ae input to the REF terminals
The TLC7225 can be used as a multiplying DAC when the reference signal is maintained between 2 V and
Voo - 4 V. When this configuration is used, Voo should be 14.25 V to 15.75 V. A low output-impedance buffer
should be used so that the input signal is not loaded by the resistor ladder. Figure 12 shows the general
schematic.
15 V

15 V

R1

REF (A, B, C, OJ
5,4,21,20
AC Reference
Input Signal

-1

OAC

>-......-

Vo

6
R2

Figure 12. AC Signal-Input Scheme

~TEXAS

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3-131

TLC7225C,TLC72251
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS1 09A - OCTOBER 1996 - REVISED APRIL 1997

APPLICATION INFORMATION

digital word multiplication
Since each DAC of the TLC7225 has a separate reference input, the output of one DAC Can be used as the
reference input for another. Therefore, multiplication of digital words can be performed (with the result given in
analog form). For example, when the output from DAC A is applied to REFB then the output from DAC B, VOUTB,
can be expressed as given in equation 2:
VOUTB = (DA) (DB) (VREFA)

(2)

where DA and DB are the fractional representations of the digital words in DAC latches A and 8 respectively.
If DA = DB = D then the result is D2 (VREFA)
In this manner, the four DACs can be used on their own or in conjunction with an extemal summing amplifier
to generate complex waveforms. Figure 13 shows one such application with the output waveform, Y, which is
represented by equation 3:
Y = -(x4 + 2x3 + 3x2 + 2x + 4) VI

(3)

where x is the digital code that is applied to all four DAC latches.
15V

REFA

VOO

OUTA 1--+--.A.llJ'v-........-I

TLC7225t
REFB

OUTB I--____---'VV'..-.

REFC

50kQ
OUTC I-+t-'VV'..-.

REFO

100 kQ
OUTO 1---f-I-.A.llJ'v--'

t Digital inputs omitted for clarity

Figure 13. Complex-Waveform Generation

3-132

~TEXAS .
INSTRUMENTS
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v

TLC7225C, TLC72251
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS1 09A - OCTOBER 1996 - REVISED APRIL 1997

APPLICATION INFORMATION
microprocessor interface
Figures 14, 15, 16, and 17 show the hardware interface to some of the standard processors.
A~~

________________________________- - n

••

Address Bus

A8

AO
' - - - - i A1

r:~=-b----~

8085/8088

LDAC
TLC7225t
WR

DB7

••
•

ALE

DBO

AD7

••
•

Address Data Bus

ADO
t Linear circuitry omitted for clarity
Figure 14. TLC7225 to 8085A/8088 Interface, Double-Buffered Mode
A15~-----------------------------------n

•

••

Address Bus

AS

AO
8085/8088

' - - - - I A1

LDAC

RIW

TLC7225t
E or <\>2

WR
~--------------------",-~

DB7

••
•

DBO

·

AD7

~--------------------~
: r-__________
~D~a=ta~B~u~s__________________

_J

ADO
t Linear circuitry omitted for clarity
Figure 15. TLC7225 to 6809/6502 Interface, Single-Buffered Mode

~TEXAS

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TLC7225C,TLC72251
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS109A - OCTOBER 1996 - REVISED APRIL 1997

APPLICATION INFORMATION
A15

•••

~

Address Bus

L

A8

Z-SO

AO
A1

Address
Decode

EN

MREQ

LDAC

Pi)'

-

WR

WR

r

~

AD7

•
••
ADO

TLC7225t

Data Bus

DB7

••
•

DBO

~

t Linear circuitry omitted for clarity
Figure 16. TLC7225 to Z-80 Interface, Double-Buffered Mode
A23

••
•

L

U

Address
Decode

68008
AS

~

Address Bus

A1

f------<:

EN

RiW

A1

~

TLC7225t

-J-r

DTACK

r

~

AD7

••
•
ADO

AO

Data Bus

WR
LDAC
DB7

•
••

DBO

t Linear circuitry omitted for clarity

Figure 17. TLC7225 to 68008 Interface, Single-Buffered Mode

~TEXAS

3-134

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

~

TLC7225C, TLC72251
QUADRUPLE a-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS109A- OCTOBER 1996 - REVISED APRIL 1997

APPLICATION INFORMATION

linearity, offset, and gain error using single-ended supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage
may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, since the most negative supply
rail is ground, the output cannot drive below ground.
So with this output offset voltage, the output voltage remains at zero until the input-code value produces a
sufficient output voltage to overcome the inherent offset voltage, resulting in a transfer function shown in
Figure 18.

Output
Voltage

OV +---~~----------+
Negative {
Offset

DAC Code

Figure 18. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below ground.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale is adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
in the unipolar mode is measured between full-scale code and the lowest code, which produces a positive output
voltage.
The code is calculated from the maximum specification for the zero offset error.

~TEXAS

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3-135

3-136

TLC7226C,TLC7226E
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS060B - JANUARY 1995 - REVISED AUGUST 1996

res
•
•
•
•
•

OW OR N PACKAGE
(TOP VIEW)

Four 8-Bit D/A Converters
Microprocessor Compatible
TTL/CMOS Compatible
Single Supply Operation Possible
CMOS Technology

OUTB
OUTA

applications
,•
•
•

Vss

VDD

REF
AGND

AO
A1
WR
DBO
DB1
DB2
DB3

DB7
DB6
DB5
DB4

Process Control
Automatic Test Equipment
Automatic Calibration of Large System
Parameters, e.g. Gain/Offset

OUTe
OUTO

description
The TLC7226C and TLC7226E consist of four 8-bit voltage-output digital-to-analog converters (DACs) with
output buffer amplifiers and interface logic on a single monolithic chip.
Separate on-chip latches are provided for each of the four DACs. Data is transferred into one of these data
latches through a common 8-bit TTL/CMOS-compatible 5-V input port. Control inputs AO and A1 determine
which DAC is loaded when WR goes low. The control logic is speed compatible with most 8-bit microprocessors.
Each DAC includes an output buffer amplifier capable of sourcing up to 5 mA of output current.
The TLC7226 performance is specified for input reference voltages from 2 V to VDD - 4 V with dual supplies.
The voltage mode configuration of the DACs allows the TLC7226 to be operated from a single power supply
rail at a reference of 10 V.
The TLC7226 is fabricated in a LinBiCMOSTM process that has been specifically developed to allow high-speed
digital logic circuits and precision analog circuits to be integrated on the same chip. The TLC7226 has a common
8-bit data bus with individual DAC latches. This provides Ii versatile control architecture for simple interface to
microprocessors. All latch-enable signals are level triggered.
Combining four DACs, four operational amplifiers, and interface logic into either a O.3-inch wide, 20-terminal
dual-in-line IC (DIP) or a small 20-terminal small-outline IC (SOl C) allows a dramatic reduction in board space
requirements and offers increased reliability in systems using multiple converters. The pinout is aimed at
optimizing board layout with all of the analog inputs and outputs at one end of the package and all of the digital
inputs at the other.
The TLC7226C is characterized for operation from ODC to 70 DC. The TLC7226E is characterized for operation
from -25 DC to 85 DC.
AVAILABLE OPTIONS
PACKAGE
TA

SMALL OUTLINE
(OW)

PLASTIC DIP
(N)

O°C to 70°C

TLC7226CDW

TLC7226CN

-25°C to 85°C

TLC7226EDW

TLC7226EN

LinBiCMOS is a trademark of Texas Instruments Incorporated.

~~~~~~~o~r:1: sl~!~Wc~~:si~e~~h:~r:~ :1 /e~:~~:e~~~~rs

standard warranty. Production processing does not necessarily include

testing of all parameters.

~TEXAS

INSTRUMENTS
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Copyright © 1996, Texas Instruments Incorporated

3-137

TLC7226C,TLC7226E
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLASOeOB - JANUARY 1995 - REVISED AUGUST 19ge

functional block diagram
REF_4__________________~----_,
>-*_..,,2- OUTA

>--+---'OBO-OB7 7-14

OUTB

8

>-_-=2::...0 OUTC

>-_-,1-,-9 OUTO

__ 15 , . . - - . ,
WR 17 Control 1-+_-'
AO
Logic
A1 16 L_J+-------'

schematic of outputs
EQUIVALENT ANALOG OUTPUT
VOO -------it-----------,

•

--~

Vss

----~.-----------'

~TEXAS

3-138

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC7226C, TLC7226E
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS060B - JANUARY 1995 - REVISED AUGUST 1996

Terminal Functions
TERMINAL
NAME

NO.t

AGND

5

AO,Al

16,17

OGND

6

DBO-OB7

DESCRIPTION

1/0

Analog ground. AGND is the reference and return terminal for the analog signals and supply.
I

OAC select inputs. The combination of high or low levels select either DACA, DACB, DACC, or DACD.
Digital ground. OGNO is the reference and return terminal for the digital signals and supply.

7-14

I

Digital DAC data inputs. DBO-OB7 are the input digital data used for conversion.

OUTA

2

0

DACA output. OUTA is the analog output of DACA.

OUTB

1

0

DACB output. OUTB is the analog output of DACB.

OUTC

20

a

DACC output. OUTC is the analog output of DACC.

aUTD

19

a

REF

4

I

VDD

18

VSS
WR

3
15

OACD output. aUTD is the analog output of DACD.

Voltage reference input. The voltage level on REF determines the full scale analog output.
Positive supply voltage input terminal
Negative supply voltage input terminal

I

Write input. WR selects DAC transparency or latch mode. The selected input latch is transparent when WR
is low.

t Terminal numbers shown are for the OW and N packages.

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TLC7226C,TLC7226E
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS060B - JANUARY 1995 - REVISED AUGUST 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Voo: AGND or DGND ......................................... -0.3 V to 17 V
VSS:t ......................................... , ......... -0.3 V to 24 V
Supply voltage range, VSS: AGND or DGND .......................................... -7 V to 0.3 V
Voltage range between AGND and DGND ............................................ -17 V to 17 V
Input voltage range, VI (to DGND) ............................................ -0.3 V to Voo + 0.3 V
Reference voltage range: Vref' (to AGND) ........................................... -0.3 V to Voo
Vredto VSS) ............................................. -0.3 V to 20 V
Output voltage range, Va (to AGND) (see Note 1) ........................................ VSS to Voo
Continuous total power dissipation at (or below) TA = 25°C (see Note 2) .•..................... 500 mW
Operating free-air temperature range, TA: C suffix ....................................... O°C to 70°C
E suffix ..................................... -25°C to 85°C
Storage temperature range, Tstg .................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 1.0 seconds: DW or N packages .............. 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recomm!3nded operating conditions" is not
implied; Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
:j: The VSS terminal is connected to the substrate and must be tied to the most negative supply voltage applied to the device.
NOTES: 1. Output voltages may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically short circuit
current to AGND is 60 mAo
2. For operation above TA = 75°C, derate linearly at the rate of 2 mW/oC.

recommended operating conditions
MIN

MAX

Supply voltage, VDD

11.4

16.5

V

Supply voltage, VSS

-5.5

0

V

2

High-l!3vel input voltage, VIH
Low-level input voltage, VIL

V
0.8

0 VDD-4

Reference voltage, Vref
Load resistance, RL

UNIT

V
V

2

k.Q

Setup time, address valid before WR.J., tsu{AW) (see Figure 6)

VDD = 11.4 V to 16.5 V

0

ns

Setup time, data valid before WRi, tsu(DV\I) (see Figure 6)

VDD = 11.4 Vto 16.5 V

45

ns

Hold time, address valid before WRi, th(AW) (see Figure 6)

VDD = 11.4 V to 16.5 V

0

ns

Hold time, data valid before WRi, th{DW) (see Figure 6)

VDD = 11.4 V to 16.5 V

10

ns

Pulse duration, WR low, tw (see Figure 6)

VDD = 11.4 Vto 16.5 V

50

Operating free-air temperature, TA

0

70

°C

E suffix

-25

85

°C

~TEXAS
3-140

ns

C suffix

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TLC7226C,TLC7226E
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS060B - JANUARY 1995 - REVISED AUGUST 1996

electrical characteristics over recommended operating free-air temperature range
dual power supply over recommended power supply and reference voltage ranges, AGND = DGND = 0 V
(unless otherwise noted)
PARAMETER

TEST CONDITIONS

Input current, digital

VI = OVorVDD

IDD

Supply current

VI = 0.8 V or 2.4 V,
VSS=-5V,

VDD= 16.5 V,
No load

ISS

Supply current

VI = 0.8 V or 2.4 V,

No load

fi(ref)

Reference input resistance

II

2

Power supply sensitivity

Ci

Input capacitance

MIN

TYP

All Os loaded

UNIT

±1

!lA

6

16

mA

4

10

mA

0.01

%1%

300

pF

kQ

4

,WDD=±5%
REF input

MAX

65

All1s loaded

8

Digital inputs

operating characteristics over recommended operating free-air temperature range
dual power supply over recommended power supply and reference voltage ranges, AGND
(unless otherwise noted)
PARAMETER

TEST CONDITIONS

Slew rate

MIN

TYP

=DGND =0 V
MAX

2.5

I Positive full scale

Settling time to 1/2 LSB

I Negative full scale

VOIlS
5

Vre f=10V

7
8

Resolution
Total unadjusted error

I Differentiallintegral

Linearity error
Full-scale error

VDD = 15 V ±5%,

Vre f=10V

Gain error
Temperature coefficient of gain

VDD = 14 V to 16.5 V,

bits
LSB

±1

LSB

±2

LSB

I Zero-code error

±20

Digital crosstalk glitch impulse area

PARAMETER

VI = 0.8 V or 2.4 V,

MIN

No load

Slew rate

TYP

MAX

5

13

2
Positive full scale

5
20

Resolution

8

Total unadjusted error
Full-scale error

Linearity error

±2

= 14 V to 16.5 V,

Zero-code error

Vre f=10V

LSB
LSB
IlVloC

±50
±1
50

Ils,

ppm/oC

±20

Differential

Digital crosstalk-glitch impulse area

mA

bits
±2

VDD

UNIT

VOIlS

Negative full scale

Full scale

mV
nVos

=0 V, Vref =10 V (unless otherwise noted)

TEST CONDITIONS

Supply current, IDD

±80

50

Vref=O

single power supply, VOO =14.25 V to 15.75 V, VSS =AGND =DGND

Temperature coefficient of gain

IlV/0 C

±50

Zero-code error

Settling time to 1/2 LSB

LSB
ppm/oC

±20

Vre f=10V

Ils

±2

±0.25

I Full scale

UNIT

LSB
nVos

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TLC7226C, TLC7226E
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS060B-JANUARY 1995- REVISED AUGUST 1996

PARAMETER MEASUREMENT INFORMATION

~",,"I_tsu(ow)

, J,J.,-:_ _

Data

=============l\

Voo

(<======= OV

~th(OW)

Voo

Address

----'0~----:~~'---- OV
tsu(AW)

.

~

'\

NOTES: A. Ir = tf

~ th(AW)

14-- tw -----.I

1--

Voo
OV

= 20 ns over VOO range.

B. The timing measurement reference level is equal to VIH + VIL
divided by 2.
C. The selected input latch is transparent while WR is low. Invalid
data during this time can cause erroneous outputs.

Figure 1. Write-Cycle Voltage Waveforms

~TEXAS

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TLC7226C,TLC7226E
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS060B - JANUARY 1995 - REVISED AUGUST 1996

TYPICAL CHARACTERISTICS
OUTPUT CURRENT (SINK)

OUTPUT CURRENT

vs

vs

OUTPUT VOLTAGE

OUTPUT VOLTAGE

200
150
0(

E

100 -

(
Source Current ~
Short-Circuit
Limiting

700

~
VOO= 15V _

TA = 25°C
VOO = 15 V
600

l

0(
::1.

I

'E

!!!
5
u
'S

.e:::I

0

~I I

VSS=-5V

c

50

1[
'E
~
:::I

0
-0.1

I

.9

500

~

I

-0.3

-2

300

0

200

VSS=O

I

.9
}

-0.4

u
'S

~

TA = 25°C
VSS =-5 V
Oigital In = 0 V

-0.2

IT

400

Sinking
Current Source

-1
o
Vo - Output Voltage - V

100
0

2

0

Figure 2

2

3
4
5
6
7
8
Vo - Output Voltage - V

9

10

Figure 3

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TLC7226C, TLC7226E
QUADRUPLE a·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS060B - JANUARY 1995 - REVISED AUGUST 1996

PRINCIPLES OF OPERATION
AGND bias for direct bipolar output operation
The TLC7226 can be used in bipolar operation without adding more external operational amplifiers as shown
in Figure 1 by biasing AGND to Vss. This configuration provides an excellent method for providing a direct
bipolar output with no additional components. The transfer values are shown in Table 1 .

Output range
(5 Vto-5 V)

:1=

Digital inputs omitted for clarity.

Figure 4. AGND Bias for Direct Bipolar Operation
Table 1. Bipolar (Offset Binary) Code
DAC LATCH CONTENTS
LSB
MSB

ANALOG OUTPUT

1111

1111

+ Vref

C27)
128

1000

0001

+ Vref

(1~8)

1000

0000

0111

1111

0000

0001

0000

0000

OV
- Vref

(1~8)

(27)
128
(28)
-V ref 128
- Vref

= - V ref

AGND bias for positive output offset
The TLC7226 AGND terminal can be biased above or below the system ground terminal, DGND, to provide an
offset analog output voltage level. Figure 2 shows a circuit configuration to achieve this for channel A of the
TLC7226. The output voltage, Yo, at aUTA can be expressed as:
(1 )
where DA is a fractional representation of the digital input word (0::; D ::; 255/256).
Increasing AGND above system GND reduces the output range. VDD - Vref must be at least 4 V to ensure
specified operation. Since the AGND terminal is common to all four DACs, this method biases up the output
voltages of all the DACs in the TLC7226. Supply voltages VDD and VSS for the TLC7226 should be referenced
to DGND.

~TEXAS

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TLC7226C, TLC7226E
QUADRUPLE a·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS060B - JANUARY 1995 - REVISED AUGUST 1996

PRINCIPLES OF OPERATION
AGND bias for positive output offset (continued)

rV~~D

OUTA

-~~-{5

t

Digital inputs omitted for clarity.

Figure 5. AGND Bias Circuit

interface logic information
Address lines AD and A 1 select which DAC accepts data from the input port. Table 2 shows the operations of
the four DACs. Figure 3 shows the input control logic. When the WR signal is low, the input latches of the
selected DAC are transparent and the output responds to activity on the data bus. The data is latched into the
addressed DAC latch on the rising edge of WR. While WR is high, the analog outputs remain at the value
corresponding to the data held in their respective latches.
Table 2. Function Table
CONTROL INPUTS
WR

AI

A2

H

X

X

L

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

i
L

i
L

i
L

i
L = low,

H = high,

OPERATION

No operation
Device not selected
DAC A transparent
DAC A latched
DAC B transparent
DAC B latched
DAC C transparent
DAC C latched
DAC D transparent
DAC D latched

X = Irrelevant

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-145

TLC7226C, TLC7226E
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLASOSOB - .JANUARY 1995 - REVISED AUGUST 1995'

PRINCIPLES OF OPERATION
interface logic information (continued)

D - - - To Latch A

A1

16

D - - - To Latch B

D - - - To Latch C

D - - - To Latch D

Figure 6. Input Control Logic

unipolar output operation
The unipolar output operation is the basic mode of operation for each channel of the TLC7226, with the output
voltages having the same positive polarity as Vref' The TLC7226 can be operated with a single power supply
(Vss = AGND) or with positive/negative power supplies. The voltage at Vref must never be negative with respect
to AGND to prevent parasitic transistor turn-on. Connections for the unipolar output operation are shown in
Figure 4. Transfer values are shown in Table,3.

~TEXAS

3-146

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC7226C,TLC7226E
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS060B - JANUARY 1995 - REVISED AUGUST 1996

PRINCIPLES OF OPERATION

unipolar output operation (continued)
~.-_ _
2 OUTA
REF _4-=--.----1

>-,.-_ _1-=-- OUTB

~.-_.::::.20=-

OUTe

~.-_....:.19=-- OUTO

Figure 7. Unipolar Output Circuit
Table 3. Unipolar Code
OAC LATCH CONTENTS
MSB
LSB

ANALOG OUTPUT

1111

1111

+ Vref (255)
256

1000

0001

+ Vref 256

1000

0000

Vref
+ Vref C2B)
256 =+2

0111

1111

+ Vref 256

0000

0001

+ Vref

0000

0000

C29)
C27)
(2~6)
OV

NOTE A. 1 LSB = (V ref 2- B) = V ref

(2~6)

linearity, offset, and gain error using single-ended power supplies
When an amplifier is operated from a single power supply, the voltage offset can still be either positive or
negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the
output voltage may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier, with a negative voltage offset, attempts to drive the output to a negative voltage. However,
because the most negative supply rail is ground, the output cannot be driven to a negative voltage.
So when the output offset voltage is negative, the output voltage remains at zero volts until the input code value
produces a sufficient output voltage to overcome the inherent negative offset voltage, resulting in a transfer
function shown in Figure 5.

~TEXAS

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3-147

TLC7226C,TLC7226E
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS060B- JANUARY 1995 - REVISED AUGUST 1996

PRINCIPLES OF OPERATION

linearity, offset, and gain error using single-ended power supplies (conUnued)

Output
Voltage

o V 1---"'":......---------+
DACCode

Negative {
Offset

Figure 8. Effect of Negative Offset (Single Power Supply)

This negative offset error, not the linearity error, produces the breakpoint. The transfer function would have
followed the dotted line if the output buffer could be driven to a negative voltage.
For a DAC, linearity is measured between zero input code. (all inputs 0) and full scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single power supply operation does
not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
in the unipolar mode is measured between full scale code and the I.owest code which produces a positive output
voitage.
The code is calculated from the maximum specification for the negative offset.

-!11

TEXAS
INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC7226C, TLC7226E
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS060B - JANUARY 1995 - REVISED AUGUST 1996

APPLICATION INFORMATION
bipolar output operation using external amplifier
Each of the OACs of the TLC7226 can also be individually configured to provide bipolar output operation, using
an external amplifier and two resistors per channel. Figure 9 shows a circuit used to implement offset binary
coding (bipolar operation) with OAC A of the TLC7226. In this case:
Vo = ,1 +

~~

x (OA x V ref ) -

~~

(2)

x (V ref)

with H1 = R2

V0 = (20 A - 1) x Vref
where 0 A is a fractional representation of the digital word in latch A.
Mismatch between R1 and R2 causes gain and offset errors. Therefore, these resistors must match and track
over temperature. The TLC7226 can be operated with a single power supply or from positive and negative
power supplies.
REF----~~------------,

R2t

4

r--

1
1
1,....-...1..-....
1
1L _ _ _ _ _ _ _ _ _ _ .J1

vo

tR1 =R2=10kn±O.1%

Figure 9. Bipolar Output Circuit

staircase window comparator
In many test systems, it is important to be able to determine whether some parameter lies within defined limits.
The staircase window comparator shown in Figure 10 is a circuit that can be used to measure the VOH and VOL
thresholds of a TTL device under test. Upper and lower limits on both VOH and VOL can be programmed using
the TLC7226. Each adjacent pair of comparators forms a window of programmable size (see Figure 11). When
the test voltage (Vtest) is within a window, then the output for that window is higher. With a reference of 2.56 V
applied to the REF input, the minimum window size is 1'0 mY.

~TEXAS

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3-149

TLC7226C,TLC7226E
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS060B - JANUARY 1995 - REVISED AUGUST 1996

APPLICATION INFORMATION

staircase window comparator (continued)
Reference Voltage
Vtest
From OUT

-+---------,

5V
10kQ

4

Window 1

REF

5V
2 VOH
OUTA i-=-----'::":":""-++---1

10 kQ

Window 2

5V

TLC7226

10kQ
OUTB

1

VOH
Window 3

5V
OUTC

20 VOL

10 kQ

t-=---++---I
Window 4

5V
19 VOL
OUTO \-=---++--I
AGNO

5

Figure 10. Logic Level Measurement

~TEXAS

3-150

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10 kQ

Window 5

TLC7226C, TLC7226E
QUADRUPLE 8·BIT DlGITAL·TO·ANALOG CONVERTERS
SLAS060B - JANUARY 1995 - REVISED AUGUST 1996

APPLICATION INFORMATION

staircase window comparator (continued)
REF - - - - - - - - - - - - . , . . - Window 1
aUTA ------------~­
Window 2
aUTB -----------~~Window 3
aUTC -----------~~Wiildow4
aUTO -----------~~Window 5
AGND _ _ _ _ _ _ _ _ _ _ _ _z-_

Figure 11. Adjacent Window Structure
The circuit can easily be adapted as shown in Figure 12 to allow for overlapping of windows. When the three
outputs from this circuit are decoded, five different nonoverlapping programmable window possibilities can
again be defined (see Figure 13).
Reference Voltage
Vtest
From OUT

5V
10 kQ

4

Window 1
REF
aUTA

2
5V
10 kQ

OUTB
Window 2

TLC7226
aUTC

aUTO

20

19

5V
10kQ

Window 3

AGND

5

Figure 12. Overlapping Window Circuit

~TEXAS

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3-151

TLC7226C, TLC7226E
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS060B - JANUARY 1995 - REVISED AUGUST 1996

APPLICATION INFORMATION
staircase window comparator (continued)
REF
OUTB

WI ndow1

l

Windows 1 and 2
OUTA

Window 2
OUTD
Windows 2 and 3
OUTC

1
Win dow 3

AGND

Figure 13. Overlapping Window Structure

output buffer amplifier
The unity-gain output amplifier is capable of sourcing 5 mA into a 2-kQ load and can drive a 3300-pF capacitor.
The output can be shorted to AGND indefinitely or it can be shorted to any voltage between Vss and Voo
consistent with the maximum device power dissipation.

multiplying DAC
The TLC7226 can be used as a multiplying DAC when the reference signal is maintained between 2 V and
Voo - 4 V. When this configuration is used, Voo should be 14.25 V to 15.75 V. A low output-impedance buffer
should be used so that the input signal is not loaded by the resistor ladder. Figure 14 shows the general
schematic.
15 V

1/4 TLC7226
Vref

4
AC Reference
Input Signal

-1

>-~-VO

DAC

5
R2

Figure 14. AC Signallnpu\ Scheme

~TEXAS

3-152

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC7524C, TLC7524E, TLC75241
a·BIT MULTIPLYING DIGITAL·TO·ANALOG CONVERTERS
B - SEPTEMBER 1986-

•
•
•
•
•

•

•

D OR N PACKAGE
(TOP VIEW)

Easily Interfaced to Microprocessors
On-Chip Data Latches
Monotonic Over the Entire AJD Conversion
Range
Segmented High-Order Bits Ensure
Low-Glitch Output
Interchangeable With Analog Dewces
AD7524, PMI PM-7524, and Micro Power
Systems MP7524
Fast Control Signaling for Digital
Signal-Processor Applications Including
Interface With TMS320

OUTl
OUT2
GND
DB?
DB6
DB5
DB4
DB3

RFB
REF
VDD
WR

CS
DBO
DBl
DB2

FN PACKAGE
(TOP VIEW}

CMOS Technology

N

~

I- I-

Resolution
Linearity error
Power dissipation at VDD = 5 V
Setting time
Propagation delay time

CD LL

66~~~

KEY PERFORMANCE SPECIFICATIONS
8 Bits
1/2 LSB Max
5mWMax
100nsMax
80 ns Max

GND
DB?
NC
DB6
DB5

description
The TLC7524C, TLC7524E, and TLC75241 are
CMOS, 8-bit, digital-to-analog converters (DACs)
designed for easy interface to most popular
microprocessors.

4

3 2

1 20 19
18

5
6

17
16

7

15

8

14
9 10 11 1213

VDD
WR

NC
CS
DBO

a'i16~~co

ClCl

ClCl

NC-No internal connection

The devices are 8-bit, multiplying DACs with input latches and load cycles similar to the write cycles of a random
access memory. Segmenting the high-order bits minimizes glitches during changes in the most significant bits,
which produce the highest glitch impulse. The devices provide accuracy to 1/2 LSB without the need for thin-film
resistors or laser trimming, while dissipating less than 5 mW typically.
Featuring operation from a 5-V to 15-V single supply, these devices interface easily to most microprocessor
buses or output ports. The 2- or 4-quadrant multiplying makes these devices an ideal choice for many
microprocessor-controlled gain-setting and signal-control applications.
The TLC7524C is characterized for operation from DOC to 7DoC. The TLC75241 is characterized for operation
from -25°C to 85°C. The TLC7524E is characterized for operation from -40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA

SMALL OUTLINE
PLASTIC DIP
(D)

PLASTIC CHIP
CARRIER
(FN)

PLASTIC DIP
(N)

DoC to 70°C

TLC7524CD

TLC7524CFN

TLC7524CN

-25°C to 85°C

TLC75241D

TLC75241FN

TLC75241N

-40'C to 85°C

TLC7524ED

TLC7524EFN

TLC7524EN

~~~~~;~~:to~~1: sj~~~T:i~~81~~~~:~r:: :1 le=::~~m~~fs

standard warranty. Production processing does not necessarily Include
testing of all parameters.

~TEXAS

Copyright © 1997, Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-153

TLC7524C, TLC7524E, TLC75241
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061 B - SEPTEMBER 1986 - REVISED NOVEMBER 1997

functional block diagram
REF

R

15
2R

I

\
5-1

IL
I

R

R
2R

I

;>
5-2

IJ
I

2R

I

2R

16

;>
5-3

IT
I

I

5-8

11
I

12
13

I

2R

Data Latches

R
1
2

I

I

3

OUT1
OUT2

GND

11
4
5
6
DB7
DB6
DB5
DBO
(M5B)
(L5B)
\~--------~vr--------~/
Data Inputs
Terminal numbers shown are for the 0 or N package.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Voo ................ ", . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to 16.5 V
Digital input voltage range, VI ............................................... -0.3 V to Voo + 0.3 V
Reference voltage, Vref .................................................................. ±25 V
Peak digital input current, II ............................................................... 10 IlA
Operating free-air temperature range, TA: TLC7524C .................................. O°C to 70°C
TLC75241 ................................ -25°C to 85°C
TLC7524E ........ . . . . . . . . . . . . . . . . . . . . . .. -40°C to 85°C
Storage temperature range, Tstg ................................. :................ -65°C to 150°C
Case temperature for 10 seconds, Tc: FN package .......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ................ 260°C

~TEXAS

INSTRUMENTS
3-154

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC7524C, TLC7524E, TLC75241
a-BiT MULTIPLYING DIGITAL-TO·ANALOG CONVERTERS
SLAS061B -SEPTEMBER 1986 - REVISED NOVEMBER 1997

recommended operating conditions
VOO=15V

VOO=5V
MIN
4.75

Supply voltage. VDD
Reference voltage. Vref

NOM

MAX

MIN

5

5.25

14.5

±10

High-level input voltage. VIH

NOM

MAX

15

15.5

V
V

±10

2.4

13.5

V
1.5

0.8

Low-level input voltage. VIL

UNIT

V

40

40

ns

0

0

ns

Data bus input setup time. tsu(Dl

25

25

ns

Data bus input hold time. th(D)

10

10

ns

Pulse duration. WR low. tw(WRl

40

40

ns

CS setup time. tsu(CSl
CS hold time. th(CS)

TLC7524C
Operating free-air temperature. TA

0

70

0

70

TLC75241

-25

85

-25

85

TLC7524E

-40

85

-40

85

electrical characteristics over recommended operating free-air temperature range, Vref
OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER

TEST CONOITIONS

IIH

High-level input current

VI =VDD

IlL

Low-level input current

VI =0

Ilkg

Output leakage
current

OUT1

DBO-DB7 at 0 V.
Vref=±10V

WR. CSatOV.

OUT2

DBO-DB7 at VDD.
Vre f=±10V

WR. CSatOV.

Quiescent

DBO-DB7 at VIHmin or VILmax

Standby

DBO-DB7 at 0 V or VDD

100

Supply current

kSVS

Supply voltage sensitivity.
t..gain/t..VDD

t..VDD=±10%

Ci

Input capacitance.
DBO-DB7. WR. CS

VI=O

Co

Output capacitance

0.01

MIN

DBO-DB7 at 0 V.

WR. CSatOV

DBO-DB7 at VDD.

WR.CSatOV

Reference input impedance
(REF to GND)

TYP

MAX

10

10

-10

-10

±400

±200

±400

±200

UNIT

I!A
I!A

1

2

mA

500

500

IlA

0.04

%FSR/%

0.16

0.005

5

OUT1
OUT2

MAX

nA

OUT1
OUT2

TYP

=±10 V,

VOo= 15 V

VOO=5V
MIN

°C

5

5

30

30

120

120

120

120

30

30

20

5

20

pF

pF

kQ

~TEXAS

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3-155

TLC7524C, TLC7524E, TLC75241
8-BIT MULTIPLYING DIGITAL-lO-ANALOG CONVERTERS
SLAS061 B - SEPTEMBER 1986 ~ REVISED NOVEMBER 1997

operating characteristics over recommended operating free-air temperature range, Vref= ±10 V,
OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER

VOO=5 V

TEST CONDITIONS

MIN

TYP

VOO=15V
MAX

TYP

MIN

MAX

UNIT

±0.5

±0.5

LSB

Gain error

See Note 1

±2.5

±2.5

LSB

Settling time (to 1/2 LSB)

See Note 2

100

100

ns

Propagation delay from digital input
to 90% of final analog output current

See Note 2

80

80

ns

Feedthrough at OUT1 or OUT2

Vref = ±10 V (100-kHz sinewave)
WR and CS at 0 V, DBO-DB7 at a v

0.5

0.5

%FSR

Temperature coefficient of gain

TA = 25°C to MAX

Linearity error

NOTES:

±0.004

±0.001

1. Gain error is measured using the internal feedback resistor. Nominal full scale range (FSR) = Vref - 1 LSB.
2. OUT1 load = 100 Q, Cext = 13 pF, WR at a V, CS at a V, DBO - DB7 at a v to VDD or VDD to a V.

operating sequence
tsu(CS) ----~.I~-___*.J-

I..
CS--------~

PI,

I

1

th(CS) .

~--------

)~--------~-+:~/
.j+--- tw(WR)

WR------------~.~

1

.1

Ir--------------

~----....-.....I"
I.ti+*I

tsu(O)

-+I

08~OB7--------------------~(

~TEXAS
3-156

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS, TEXAS 15265

th(O)

)~-----------

%FSR/oC

TLC7524C, TLC7524E, TLC75241
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061 B - SEPTEMBER 1986 - REVISED NOVEMBER 1997

APPLICATION INFORMATION

voltage-mode operation
It is possible to operate the current-multiplying DAC in these devices in a voltage mode. In the voltage mode,
a fixed voltage is placed on the current output terminal. The analog output voltage is then available at the
reference voltage terminal. Figure 1 is an example of a current-multiplying DAC, which is operated in voltage
mode.
R
R
R
REF (Analog Output Voltage) ~ \--,\N\r-..---,
} 2R

} 2R

2R

2R

?

' - - + - - - - + - - - + - - O U T 1 (Fixed Input Voltage)
'---~---~--~~--OUT2

Figure 1. Voltage Mode Operation
The relationship between the fixed-input voltage and the analog-output voltage is given by the following
equation:
Vo

= VI (D/256)

where

Vo = analog output voltage
VI = fixed input voltage
D = digital input code converted to decimal
In voltage-mode operation, these devices meet the following specification:
PARAMETER

Linearity error at REF

TEST CONDITIONS
VDD = 5 V,

OUT1 = 2.5 V,

OUT2 at GND,

TA = 25°C

~TEXAS

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3-157

TLC7524C, TLC7524E, TLC75241
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061 B - SEPTEMBER 1986 - REVISED NOVEMBER 1997

PRINCIPLES .OF OPERATION
The TLC?524C, TLC?524E, and TLC?5241 are 8-bit multiplying DACs consisting of an inverted R-2R ladder,
analog switches, and data input latches. Binary-weighted currents are switched between the OUT1 and OUT2
bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. The high-order
bits are decoded. These decoded bits, through a modification in the R-2R ladder, control three equally-weighted
current sources. Most applications only require the addition of an external operational amplifier and a voltage
reference.
The equivalent circuit for all digital inputs low is seen in Figure 2. With all digital inputs low, the entire reference
current, Iref, is switched to OUT2. The current source 1/256 represents the constant current flowing through the
termination resistor of the R-2R ladder, while the current sciurce Ilkg represents leakage currents to the
substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all
digital inputs high, the off-state switch capacitance (30 pF maximum) appears at OUT2 and the on-state switch
capacitance (120 pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown
in Figure 2. Analysis of the circuit for all digital inputs high is similar to Figure 2; however, in this case, Iref would
be switched to OUT1 .
The DAC on these devices interfaces to a microprocessor through the data bus and the CS and WR control
signals. When CS and WR are both low, analog output on these devices responds to the data activity on the
DBO-DB? data bus inputs. In this mode, the input latches are tran~parent and input data directly affects the
analog output. When either the CS signal or WR signal goes high, the data on the DBO-DB? inputs are latched
until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless of the state
of the WR signal.
These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant or 4-quadrant multiplication are shown in Figures 3 and 4. Tables 1 and 2 summarize input coding
for unipolar and bipolar operation respectively.

R

.-------e-_.------OUT1

lref

---+

---'-----1- O U T 2
i
T

REF-'V\I\,----'-!----+-!
1/256 ' : (

~

Ilkg ' : (

120 pF

Figure 2. TLC7524 Equivalent Circuit With All Digital Inputs Low

~TEXAS

3-158

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TLC7524C, TLC7524E, TLC75241
a·BIT MULTIPLYING DIGITAL·TO·ANALOG CONVERTERS
SLAS061B- SEPTEMBER 1986 - REVISED NOVEMBER 1997

PRINCIPLES OF OPERATION
Vref

VDD

RA=2 kQ
(see Note A)

DBC-DB7

RB
r----'\fV\~-.....- - - - - - - - - ,

'----v
> - - * - - - Output

CS - - - - I

WR - - - - I

NOTES: D. RA and RB used only if gain adjustment is required.
E. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent
ringing or oscillation.

Figure 3. Unipolar Operation (2-Quadrant Multip!ication)
Vref

VDD

20kQ
RA=2 kQ

RB

20kQ

(see Note A)

>-+-- Output

DBC-DB7
CS - - - - I

WR - - - - I

GND

NOTES: A. RA and RB used only if gain adjustment is required.
B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.

Figure 4. Bipolar Operation (4-Quadrant Operation)
Table 1. Unipolar Binary Code
DIGITAL INPUT
(see Note 3)
MSB

NOTES:

ANALOG OUTPUT

Table 2. Bipolar (Offset Binary) Code
DIGITAL INPUT
(see Note 4)
MSB

LSB

ANALOG OUTPUT

LSB

11111111

-Vref (255/256)

11111111

Vref (127/128)

10000001

-Vref (129/256)

10000001

Vref (1/128)

= -Vref/2

10000000

-Vref (128/256)

10000000

0

01 1 1.1 111

-Vref (1271256)

01 1 11 1 1 1

-Vref (1/128)

00000001

-Vref (1/256)

00000001

-Vref (127/128)

00000000

0

00000000

-Vref

3. LSB = 1/256 (Vref)
4. LSB = 1/128 (Vref)

-!!1
TEXAS
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3-159

TLC7524C, TLC7524E, TLC75241
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061 B - SEPTEMBER 1986 - REVISED NOVEMBER 1997

PRINCIPLES OF OPERATION

microprocessor interfaces
DO-D7

Z~OA

WR

IORQ

Data Bus

r_---------------------------,

1------,...........

>----------------1 WR

1----il1---+--I

Decode
Logic

A~A15r_--------------~A=dd~re~s=s~B~Us~------------_if

Figure 5. TLC7524 - Z-80A Interface

Data Bus

D~D7

~J

6800

$2

DB~DB7

~
Lr

WR

OUT2
CS

VMA

A~A15

I

Decode
Logic

Jl

Address Bus

Figure 6. TLC7524 - 6800 Interface

~TEXAS

INSTRUMENTS
3--160

OUT1

TLC7524

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC7524C, TLC7524E, TLC75241
8·BIT MULTIPLYING DIGITAL·TO-ANALOG CONVERTERS
SLAS061B-SEPTEMBER 1986- REVISED NOVEMBER 1997

PRINCIPLES OF OPERATION
microprocessor interfaces (continued)

A8-A15
8051

t__---'-===-=c=.--v
Decode
Logic

t--___J>--,

cs
r - - - - - - I WR
ALE

TLC7524

~--+-+---I_....J

WR t---+-+----~

AD~AD7t__-------A~d-re~ss~/D-a-ta-B-u-s------_v

Figure 7. TLC7524 - 8051 Interface

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-161

3-162

TLC7528C, TLC7528E, TLC75281
DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
SLAS062A - JANUARY 1987 - REVISED MARCH 1995

•
•
•
•
•

•
•

OW OR N PACKAGE
(TOP VIEW)

Easily Interfaced to Microprocessors
On-Chip Data Latches
Monotonic Over the Entire AJD Conversion
Range
Interchangeable With Analog Devices
AD7528 and PMI PM-7528
Fast Control Signaling for Digital Signal
Processor (DSP) Applications Including
Interface With TMS320

AGND

OUTB
RFBB

OUTA

REFB
REFA

4

VDD
WR

DGND
DACA/DACB
(MSB) DB?

Voltage-Mode Operation
CMOS Technology

CS
DBD (LSB)

DB6

DB1

DBS
DB4

DB2
DB3

KEY PERFORMANCE SPECIFICATIONS
Resolution
Linearity Error
Power Dissipation at VDD = 5 V
Settling Time at VDD = 5 V
Propagation Delay Time at VDD = 5 V

FNPACKAGE
(TOP VIEW)

8 bits
1/2 LSB
20mW
100 ns
80 ns

I414f--""""~II- th(DAC)

I--

'\

tw(WR)

j.----

..IX

DBD-DB7 _ _ _ _ _ _

!I
1:---

---+I

tsu(D) ~th(D)

Data In Stable

X,..----

~TEXAS

3-164

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

,

OUTB

TLC7528C, TLC7528E, TLC75281
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062A - JANUARY 1987 - REVISED MARCH 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Voo (to AGND or DGND) .................................... -0.3 V to 16.5 V
Voltage between AGND and DGND ......................................................... ±Voo
Input voltage range, VI (to DGND) .............................................. -0.3 V to Voo + 0.3
Reference voltage, VrefA or VrefB (to AGND) ................................................. ±25 V
Feedback voltage VRFBA or VRFBB (to AGND) ............................................... ±25 V
Output voltage, VOA or VOB (to AGND) ...................................................... ±25 V
Peak input current ........................................................................ 10 ~
Operating free-air temperature range, TA: TLC7528C ................................... O°C to 70°C
TLC7528I ....................... :........ -25°C to 85°C
TLC7528E ................................ -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Case temperature for 10 seconds, T c: FN package .......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package ............... 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and'
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions
Voo

= 4.75 V to 5.25 V
MAX
NOM

MIN

VOO = 14.5 V to 15.5 V
MIN

High-level input voltage, VIH

2.4

Low-level input voltage, VIL
50

CS hold time, th(CS)

UNIT
V

13.5
0.8

CS setup time, lsu(CS)

MAX

±10

±10

Reference voltage, VrefA or VrefB

NOM

V
1.5

V

50

ns
ns

0

0

DAC select setup time, tsu(DAC)

50

50

ns

DAC select hold time, th(DAC)

10

10

ns

Data bus input setup time tsu(D)

25

25

ns

Data bus input hold time th(D)

10

10

ns

Pulse duration, WR low, tw(WR)

50

50

TLC7628C
Operating free-air temperature, TA

ns

0

70

0

70

TLC76281

-25

85

-25

85

TLC7628E

-40

85

-40

85

'C

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-165

TLC7528C, TLC7528E, TLC75281
DUAL 8·BITMULTIPLYING
DIGITAL·TO·ANALOG .CONVERTERS
SLAS062A - JANUARY 1987 - REVISED MARCH 1995

electrical characteristics over recommended operating free-air temperature range,
VrefA VrefB 10 V, VOA and VOB at 0 V (unless otherwise noted)

=

=

PARAMETER

TEST CONDITIONS

IIH

High-level input current

VI =VOO

IlL

Low-level input cu rrent

VI=O

TYPt

MAX

5

12

-10

MAX
10

!LA

5

12

-10

!LA

20

20

kQ

OAC data latch loaded with
00000000, VrefA = ±10 V

±400

±200

OUTB

OAC data latch loaded with
00000000, V refS = ± 10 V

±400

±200

±1%

±1%

0.04

0.02

%/%

2

2

mA

DC supply sensitivity, t.gainltNoo

t.VOO=±10%

100

Supply current (quiescent)

All digital inputs at VIHmin or
VILmax

100

Supply current (standby)

All digital inputs at 0 V or VOO

nA

0.5

0.5

mA

OBO-OB7

10

10

pF

WR,CS,
OACAlOACB

15

15

pF

OAC data latches loaded with
00000000

50

50

OAC data laiches loaded with
11111111

120

120

Ci

I nput capacitance

Co

Output capacitance (OUTA, OUTB)

All tYPical values are at TA = 25°C.

"!11 TEXAS \
INSTRUMENTS
3-166

TYPt

OUTA
Output leakage current

Input resistance match
(REFA to REFB)

t

UNIT

MIN

10

Reference input impedance
REFA or REFB to AGNO

Ilkg

VOO=15V

VDD=5 V
MIN

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

pF

TLC7528C, TLC7528E, TLC75281
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062A - JANUARY 1987 - REVISED MARCH 1995

operating characteristics over recommended operating free-air temperature range,
VrefA VrefS 10 V, VOA and VOS at 0 V (unless otherwise noted)

=

=

PARAMETER

VOD=15V

Voo=5 V

TEST CONDITIONS

MIN

TYP

Linearity error

MAX

MIN

TYP

UNIT

MAX

LSB

±1/2

±1/2

Settling time (to 1/2 LSB)

See Note 1

100

100

ns

Gain error

See Note 2

2.5

2.5

LSB

-65

-65

-65

-65

AC feedthrough

I REFA to OUTA
I REFB to OUTB

See Note 3

Temperature coefficient of gain

See Note 4

0.007

0.0035

Propagation delay (from digital input to
90% of final analog output current)

See Note 5

80

80

Channel-to-channel
isolation

I REFA to OUTB

See Note 6

I REFB to OUTA

See Note 7

dB
%FSR/OC
ns

77
77

77
77

dB

Digital-to-analog glitch impulse area

Measured for code transition
from 00000000 to 11111111,
TA= 25°C

160

440

nV.s

Digital crosstalk

Measured for code transition
from 00000000 to 11111111,
TA = 25°C

30

60

nV·s

Harmonic distortion

Vi=6V,

NOTES:

1.
2.
3.
4.
5.
6.
7.

f= 1 kHz,

TA = 25°C

a

-85

a

-85

dB

a

OUTA, OUTB load = 100 Q, Cext = 13 pF; WR and CS at V; DBO-DB7 at V to VDD or VDD to V.
Gain error is measured using an internal feedback resistor. Nominal full scale range (FSR) = Vref - 1 LSB.
Vref = 20 V peak-to-peak, 100-kHz sine wave; DAC data latches loaded with 00000000.
Temperature coefficient of gain measured from O°C to 25°C or from 25°C to 70°C.
VrefA = VrefB = 10 V; OUTNOUTB load = 100 Q, Cext = 13 pF; WR and CS at V; DBO-DB7 at V to VDD or VDD to
Both DAC latches loaded with 11111111; VrefA = 20 V peak,to-peak, 100-kHz sine wave; VrefB = 0; TA = 25°C.
Both DAC latches loaded with 11111111; VrefB = 20 V peak-to-peak, 100-kHz sine wave; VrefA = 0; TA = 25°C.

a

a

a v.

PRINCIPLES OF OPERATION
These devices contain two identical, 8-bit-multiplying D/A converters, DACA and DACB. Each DAC consists
of an inverted R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched
between DAC output and AGND, thus maintaining a constant current in each ladder leg independent of the
switch state. Most applications require only the addition of an external operational amplifier and voltage
reference. A simplified D/A circui.t for DACA with all digital inputs low is shown in Figure 1.
Figure 2 shows the DACA equivalent circuit. A similar equivalent circuit can be drawn for DACB. Both DACs
share the analog ground terminal 1 (AGND). With all digital inputs high, the entire reference current flows to
OUTA. A small leakage current (Ilkg) flows across internal junctions, and as with most semiconductor devices,
doubles every 10°C. Co is due to the parallel combination of the NMOS switches and has a value that depends
on the number of switches connected to the output. The range of Co is 50 pF to 120 pF maximum. The equivalent
output resistance (ro) varies with the input code from O.8R to 3R where R is the nominal value of the ladder
resistor in the R-2R network.
These devices interface to a microprocessor through the data bus, CS, WR, and DACAJDACB control signals.
When CS and WR are both low, the TLC?528 analog output, specified by the DACAJDACB control line,
responds to the activity on the DBO-DB? data bus inputs. In this mode, the input latches are transparent and
input data directly affects the analog output. When either the CS signal or WR signal goes high, the data on the
DBa-DB? inputs is latched until the CS and WR signals go low again. When CS is high, the data inputs are
disabled regardless of the state of the WR signal.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-167

TLC7528C, TLC7528E, TLC75281
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062A - JANUARY 1987 - REVISED MARCH 1995

PRINCIPLES OF OPERATION
The digital inputs of these devices provide TIL compatibility when operated from asupply voltage of 5 V. These
devices can operate with any supply voltage in the range from 5 V to 15 V; however, input logic levels are not
TIL compatible above 5 V.
R

R

R
2R
~'VV\r--

~-+--+-+-'f----'+-+---\

--t-.......,

L---+......

RFBA

1--......+-+--+-"*---- OUTA

I----+......~---- AGND

Figure 1. Simplified Functional Circuit for DACA
RFBA
RFB
R
OUTA

REFA
I
Ilkg

256

t

COUT
AGND

Figure 2. TLC7528 Equivalent Circuit, DACA Latch Loaded With 11111111
MODE SELECTION TABLE
'DACAlDACB

CS

WR

DACA

DACB

L
H

L
L
H

L
L

X

X

H

Write
Hold
Hold
Hold

Hold
Write
Hold
Hold

X
X
L = low level,

H= high level,

X = don't care

~TEXA.S

3-168

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC7528C, TLC7528E, TLC75281
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062A - JANUARY 1987 - REVISED MARCH 1995

APPLICATION INFORMATION
These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant and 4-quadrant multiplication are shown in Figures 3 and 4. Tables 1 and 2 summarize input coding
for unipolar and bipolar operation.
VI(A)
±10V

R1 (see Note A)

17r-------------------

VDD -:-:11
DBO 4

: I
•

DB7

--+-----1
7

6
15

DACAfDACB

R2 (see Note A)

RFBA

REFA'
,...--_
~::":"::''--!--''''--I

8

Input
Buffer

Latch

8

I
I
I
I
I
I
I
I

I
I
~-+--;.I__"'-I
I

Latch

CS

r.L___________________ _____ I

WR~
DGND

REFB

>-----<-- VOB

~

-=-

RECOMMENDED TRIM
RESISTOR VALUES

R1, R3
R2, R4

R3 (see Note A)
VI(B)

500n
150n

±10V

NOTES: A. RI, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment with
digital input of 255.
B. CI and C2 phase compensation capacitors (I 0 pF to 15 pF) are required when using high-speed amplifiers to prevent ringing or
oscillation.

Figure 3. Unipolar Operation (2-Quadrant Multiplication)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3--169

TLC7528C, TLC7528E, TLC75281
DUAL 8·BIT MULTIPLYING
DIGITAL-TO·ANALOG CONVERTERS
SLAS062A - JANUARY 1987 - REVISED MARCH 1995

APPLICATION INFORMATION·
R6
20kn
(see Note B)

VI(A)
±10 V

VDD
DBO

RFBA

,---------------

R2 (see Note A)

-ll..J
14

Input
Buffer

8

(see Note B)

DB7

DACN_6~--r_~--1

RFBB

R8
20kn

-,1~6r--L-----1
5 I

~I

IL. _ _ _ _ _ _ _ _ _ _ _

DGND

VOA

R11
5kQ

R4 (see Note A)

~r----.

DACB
CS -,1=5-+---I

WR

R5
20kQ

R7
10kn

~

R9
10kn
(see Note B)

__ _

VOB

(see Note A)
R10
20kn
(see Note B)

VI(B)
±10V

NOTES: A. Rl, R2, R3, and R4 are used only if gain adjustment is required. See ·table in Figure 3 for recommended values. Adjust R1 for
VOA = 0 V with code 10000000 in DACA latch. Adjust R3 for VOB = 0 V with 10000000 in DACB latch.
B. Matching and tracking are essential for resistor pairs R6, R7, R9, and RIO.
C. Cl and C2 phase compensation capacitors (10 pF to 15 pF) may be required if Aland A3 are high-speed amplifiers.

Figure 4. Bipolar Operation (4-Quadrant Operation)
Table 1. Unipolar Binary Code
DAC LATCH CONTENTS
MSB

LSBt

11111111
10000001
10000000
01111111
00000001
00000000

Table 2. Bipolar (Offset Binary) Code

ANALOG OUTPUT
-VI (255/256)
-VI (129/256)
-VI (128/256) = - Vi/2
-VI (127/256)
-VI (1/256)
-VI (0/256) = 0

DAC LATCH CONTENTS
MSB

11111111
10000001
10000000
01111111
00000001
00000000

t 1 LSB = (2-8)VI

~TEXAS

3-170

LSB:j:

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ANALOG OUTPUT
VI (127/128)
VI (1/128)
OV
-VI (1/128)
-VI (127/128)
-VI (1281128)

TLC7528C, TLC7528E, TLC75281
DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
SLAS062A - JANUARY 1987 - REVISED MARCH 1995

APPLICATION INFORMATION

microprocessor interface information

AS-A15

Address Bus

1-_ _--,

,------___1~----___1

Address
Decode
Logic

CPU

DACAlDACB

A
CS

,--------1~------___1 WR TLC7528

8051

DBO

••

WRI----j

DB7
ALE

Data Bus

ADO-AD7b-----------~~----~~~-----------------v

NOTE A: A =decoded address for TLC7528 DACA
A + 1 = decoded address for TLC7528 DACB

Figure 5. TLC7528 - Intel 8051 Interface

8
Address Bus

A8-A15/--____--,

DACA/DACB

VMA

Address
Decode
Logic

A
CS
WR TLC7528

CPU

6800

DBO

••

DB7

4>21----1

8
Data Bus _____________________v
ADO-AD7/--__________-+__~~~

NOTE A: A = decoded address for TLC7528 DACA
A + 1 = decoded address for TLC7528 DACB

Figure 6. TLC7528 - 6800 Interface

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3--171

TLC7528C, TLC7528E, TLC75281
DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
SLAS062A- JANUARY 1987 - REVISED MARCH 1995

APPLICATION INFORMATION
8
Address Bus

A8-A15 1 - - - - - ,

.-----1---____t DACAlDACB
Address
Decode
Logic

IORQ

A

CS
TLC7528
.----~---____tWR

CPU

010
•
DB7

Z8D-A
WRI----L_~

8
DO-D71--_ _ _ _ _~-D-a-ta-B-u-s----------~

NOTE A: A = decoded address for TLC7528 DACA
A + 1 = decoded address for TLC7528 DACB

Figure 7. TLC7528 To Z-80A Interface

programmable window detector
The programmable window comparator shown in Figure 8 determines if voltage applied to the DAC feedback
resistors are within the limits programmed into the data latches of these devices. lnput signal range depends
on the reference and polarity, that is, the test input range is 0 to -Vref. The DACA and DACB data latches are
programmed with the upper and lower test limits. A signal within the programmed limits drives the output high.

~TEXAS

3-172

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC7528C, TLC7528E, TLC75281
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062A - JANUARY 1987 - REVISED MARCH 1995

APPLICATION INFORMATION
VOD

Test Input - - - . - - - - - - - - - - - ,
o to -Vref
3
RFBA

VCC

17
1 kQ

4
REFA
... DBO-OB7
Data Inputs _,..8,,","+-+-..;1_4_-7
TLC7528
15 CS

AGNO

.....

.-+-~~

PASS/FAIL Output

_ _--+-+---.:.16"-1 WR
_ _~...j-_6-1 OACA/DACB
20
18 REFB
Vref --+-.__--I-'-=-=--I
5 DGND
RFBB
19

Figure 8. Digitally-Programmable Window Comparator (Upper- and Lower-Limit Tester)

digitally controlled signal attenuator
Figure 9 shows a TLC7528 configured as a two-channel programmable attenuator. Applications include stereo
audio and telephone signal level control. Table 3 shows input codes vs attenuation for a 0 to 15.5 dB range.
Attenuation dB

VDD

=-20 10910 D/256, D =digital input code

17

VIA _ _ _ _ _ _ _
4-t-R_E_F_A-t

RFBA

3

OUTA

2
Output

8
14-7
DBO-DB7 ~.;....;--...,."--- Data Bus
TLC7528

CS
WR

DACA/DACB
REFB

15
16
6
18

VOB
AGND
DGND
19 "--_ _ _ _ _ _ _ _ _..1

Figure 9. Digitally Controlled Dual Telephone Attenuator

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-173

TLC7528C, TLC7528E, TLC75281
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062A - JANUARY 1987 - REVISED MARCH 1995

APPLICATION INFORMATION

Table 3. Attenuation vs DACA, DACB Code
ATTN (dB)

DAC INPUT CODE

CODE IN
DECIMAL

ATTN (dB)

DAC INPUT CODE

CODE IN
DECIMAL

0

11111111

255

8.0

01100110

102

0.5

11 110010

242

8.5

01100000

96

1.0

11 100100

228

01011011

91

1.5

1 1010111

215

9.0
9.5

01010110

2.0

1 1001011

203

10.0

01010001

86
81

2.5

11000000

192

10.5

01001100

76

3.0

10110101

181

.11.0

01001000

72

3.5

10101011

171

11.5

01000100

68
64

4.0

10100010

162

12.0

01000000

4.5

10011000

152

12.5

001 11 101

61

5.0

1001 1 111

144

13.0

001 11001

57

5.5

10001000

136

13.5

001101 10

54

6.0

128
121

14.0

001 10011

51

6.5

10000000
01111001

14.5

00110000

48

7.0

01 1 10010

114

15.0

00101110

46

7.5

01 101 100

108

15.5

0010101 1

43

programmable state-variable filter
This programmable state-variable or universal filter configuration provides low-pass, high-pass, and bandpass
outputs, and is suitable for applications requiring microprocessor control of filter parameters.
As shown in Figure 10, DACA 1 and DACB1 control the gain and Q of the filter while DACA2 and DACB2 control
the cutoff frequency. Both halves of the DACA2 and DACB2 must track accurately in order for the
cutoff-frequency equation to be true. With the TLC7528, this is easy to achieve.

f -

1
c - 2n R1C1

The programmable range for the cutoff or center frequency is 0 to 15 kHz with a Q ranging from 0.3 to 4.5. This
defines the limits of the component values.

~TEXAS

3-174

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC7528C, TLC7528E, TLC75281
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062A - JANUARY 1987 - REVISED MARCH 1995

APPLICATION INFORMATION
C3

47pF
4 REFA

VI

OUTA 2

17
VDD

RFBA

814-7

Dala In

R5
30 k.Q

3

R4

AGND

1

OUTB

20

R3
15
16

CS
WR

RFBB

5

REFB
6

High Pass
Oul

10kO

19
18

DACA/DACB
Bandpa~s

Out

DACA1 AND DACB1
C1

4
17
8 14-7

Dalaln

15
16
5

-=

6

OUTA 2

REFA
VDD

RFBA

DBO-DB7

TLC7528

CS
WR

AGND

1

OUTB

20

RFBB

DGND

3

REFB

C2

19

>--411--- Low Pass Out

18

DACA/DACB
DACA2 and DACB2

Circuit Equations:
C1

= C2. R1 = R2. R4 = R5

Q = R3 .

R4

RF
Rfb(DACB1)

where:
Rfb is the Internal resistor connected between OUTB and RFBB
RF
G=-RS
NOTES: A. Op-amps AI, A2, A3, and A4 are TL287.
B. CS compensates for the op-amp gain-bandwidth limitations.
C. DAC equivalent resistance equals

256 x (DAC ladder resistance)
DAC digital code

Figure 10. Digitally Controlled State-Variable Filter

~TEXAS

INSTRUMENTS
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3-175

TLC7528C, TLC7528E, TLC75281
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062A ~ JANUARY 1987 - REVISED MARCH 1995

APPLICATION INFORMATION

voltage-mode operation
It is possible to operate the current multiplying D/A converter of these devices in a voltage mode. In the voltage
mode, a fixed voltage is placed on the current output terminal. The' analog output voltage is then available at
the reference voltage terminal. Figure 11 is an example of a current multiplying D/A, that operates in the voltage
mode.
R

R

REF--'-~v-~--~v-

R
__--~0r--~--~

(Analog Output Voltage)

2R

2R

2R

R
Out (Fixed Input Voltage)
AGND

Figure 11. Voltage-Mode Operation

The following equation shows the relationship between the fixed input voltage and the analog output voltage:
Va

= VI (0/256)

where
Va = analog output voltage
VI =fixed input voltage
o =digital input code converted to decimal

In voltage-mode operation, these devices meet the following specification:
PARAMETER

Linearity error at REFA or REFS

TEST CONDITIONS
VDD

=5 V,

OUTA or OUTS at 2.5 V,

~TEXAS

INSTRUMENTS
3--176

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TA

=25°C

TLC7628C, TLC7628E, TLC76281
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS063A -APRIL 1989 - REVISED MAY

•
•
•
•
•

•

DW OR N PACKAGE
(TOP VIEW)

Easy Microprocessor Interface
On-Chip Data Latches
Digital Inputs Are TTL-Compatible With
10.S-V to 1S.7S-V Power Supply
Monotonic Over the Entire AJD Conversion
Range
Fast Control Signaling for Digital Signal
Processor (DSP) Applications Including
Interface With TMS320

AGND
OUTA
RFBA
REFA
DGND
DACAlDACB
(MSB) DB?
DB6
DB5
DB4

CMOS Technology
KEY PERFORMANCE SPECIFICATIONS
Resolution
Linearity Error
Power Dissipation
Settling Time
Propagation Delay TIme

OUTB
RFBB
REFB
VDD

WR
CS
DBO (LSB)
DB1
DB2
DB3

8 bits
1/2 LSB

FN PACKAGE
(TOP VIEW)

20mW
100 ns
80 ns

iii~~~ffi
tE6~6tE

description

3 2 1 20 19
The TLC7628C, TLC7628E, and TLC7628I are
REFB
REFA
4
18
dual, 8-bit, digital-to-analog converters (DACs)
DGND
5
17
VDD
designed with separate on-chip data latches and
WR
16
DACAlDACB
6
exceptionally
close
DAC-to-DAC
feature
15 CS
(MSB) DB?
7
matching. Data is transferred to either of the two
DBO (LSB)
DB6
8
14
DAC data latches through a common, 8-bit input
9 10 11 1213
port. Control input DACA/DACB determines
which DAC is loaded. The load cycle of these
devices is similar to the write cycle of a
random-access memory, allowing easy interface
to most popular microprocessor buses and output ports. Segmenting the high-order bits minimizes glitches
during changes in the most significant bits, where glitch impulse is typically the strongest.

The TLC7628C operates from a 10.8-V to 15.75-V power supply and is TTL-compatible over this range. 2- or
4-quadrant multiplying makes these devices a sound choice for many microprocessor-controlled gain-setting
and signal-control applications.
The TLC7628C is characterized for operation from O°C to 70°C. The TLC76281 is characterized for operation
from -25°C to 85°C. The TLC7628E is characterized for operation from -40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA

PLASTIC CHIP
CARRIER
(FN)

PLASTIC DIP
(N)

O°c to 70°C

TLC7628CDW

TLC7628CFN

TLC7628CN

-25°C to 85°C

TLC76281DW

TLC76281FN

TLC76281N

-40°C to 85°C

TLC7628EDW

TLC7628EFN

TLC7628EN

~~~~I~~~o~1: S~~rfr~~i~~S~e~~~~~!r: :llei:~~~~~~m~~s

standard warranty. Production processing does not necessarily include

testing of all parameters.

SMALL OUTLINE
PLASTIC DIP
(DW)

~TEXAS

Copyright © 1995. Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-177

TLC7628C, TLC7628E, TLC76281
DUAL 8-BIT MULTIPLYING
DIGITAL..TO-ANALOG CONVERTERS
SLAS063A - APRIL 1989 - REVISED MAY 1995

functional block diagram
DBD

14

REFA

3

13

Data
Inputs

••
•

11
10

Input
Buffer

2

8
Latch A

DACAlDACB
WR
CS

OUTA

DACA

9
8

DB7

RFBA

4

12

AGND

7

19
6
16
15

20
Logic
Control

Latch B

RFBB
OUTB

8

REFB

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Voo (to AGND or DGND) ...................................... -0.3 V to 17 V
Voltage between AGND and DGND .......................................................... VOO
Input voltage range, VI (to DGND) ............................................ -0.3 V to Voo + 0.3 V
Reference voltage range, VrefA or VrefB (to AGND) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±25 V
Feedback voltage range, VRFBA or VRFBB (to AGND) . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .. ±25 V
Output voltage range, VOA or VOB (to AGND) ............................................... ±25 V
Peak input current .................... '................................................... 10 ~
Operating free-air temperature range, TA: TLC7628C .................................. O°C to 70°C
TLC7628I ................................. -25°C to 85°C
TLC7628E ... . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -40°C to 85°C
Storage temperature range, T5tg ................................................... -65°C to 150°C
Case temperature for 10 seconds, T c: FN package .......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DWor N package .............. 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions lor extended periods may affect device reliability.

~TEXAS

3-178

INSTRUMENTS
POST OFFice BOX 655303 • OALLAS, TeXAS 75265

TLC7628C, TLC7628E, TLC76281
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS063A-APRIL 1989- REVISED MAY 1995

recommended operating conditions
MIN

NOM

10.8

Supply voltage, VOO

MAX
15.75

±10

Reference voltage, VrefA or VrefB
High-level input voltage, VIH

V
V

2.4

V
0.8

Low-level input voltage, VIL
CS setup time, tsu(CS)

UNIT

V

50

ns

0

ns

DAC select setup time, tsu(DAC) (see Figure 1)

60

ns

DAC select hold time, thIOAC) (see Figure 1)

10

ns

Data bus input setup time tsu(D) (see Figure 1)

25

ns

Data bus input hold time tt1f.DL (see Figure 1)

10

ns

Pulse duration, WR low, tw(WR) (see Figure 1)

50

CS hold time, thlCS) (see Figure 1)

TLC7628C
Operating free-air temperature, TA

ns

0

70

TLC7628I

,...25

85

TLC7628E

-40

85

electrical characteristics over recommended ranges of operating free-air temperature and
VrefA VrefB 10 V, VOA and VOB at 0 V (unless otherwise noted)

=

=

PARAMETER
IIH

IlL

TEST CONDITIONS

MIN
Full range

High-level input current

VI = VDO

Low-level input current

VI=O

-10

25°C

-1

DAC data latch loaded with 00000000,
VrefA =±10V

Full range
25°C

±50

OUTB

DAC data latch loaded with 00000000,
VrefB = ±10 V

Full range

±200

25°C

AVDD=±5%
Quiescent

Ci

Input capacitance

Co

Output capacitance (OUTA, OUTB)

UNIT
J.lA

J.lA
kQ

±200
nA

±50
±1%

DC supply sensitivity Again/AVDD

Supply current

20

OUTA

Input resistance match (REFA to REFB)

IDD

1

25°C

5

Output leakage current

Voo,

10

Full range

Reference input impedance REFA or REFB to
AGND

Ikg

MAX

°C

Full range

0.02

25°C

0.01
2

All digital inputs at VIHmin or VILmax

Standby

All digital inputs at 0 V or VDD

%/%

Full range

0.5

25°C

0.1

DBO-DB7

10

WR,CS,
DACNOACB

15
DAC data latches loaded with 00000000

25

DAC data latches loaded with 11111111

60

rnA

pF

pF

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-179

TLC7628C, TLC7628E, TLC76281
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS063A - APRIL 1989 - REVISED MAY 1995

operating characteristics over recommended ranges of operating free-air temperature and Voo,
VrefA = VrefB = 10 V, VOA and VOB at 0 V (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

TYP

Linearity error
Settling time (to 1/2 LSB)

See Note 1

Gain error

AC feedthrough

See Note 2

I REFA to OUTA

IREFB to OUTB

See Note 3

UNIT

±1/2

LSB

100

ns

Full range

±3

25°C

±2

Full range

-65

25°C

-75

LSB

dB

±0.0035 %FSR/OC

Temperature coefficient of gain
Propagation delay (from digital input to
90% of final analog output current)
Channel-to-channel
isolation

MAX

LREFA to OUTB
IREFB to OUTA

See Note 4

80

See Note 5

25f'C

80

See Note 6

25°C

80

ns
dB

Digital-to-analog glitch impulse area

Measured for code transition from 00000000 to 11111111,
TA = 25°C

330

nVos

Digital crosstalk

Measured for code transition from 00000000 to 11111111,
TA = 25°C

60

nVos

Harmonic distortion
NOTES:

Vi = 6 V, f = 1 kHz,

=

-85

TA = 25°C

=

14
CS

DACAlDACB

.1

.14
1
1
1
.14
1
1
1

1s\l(CS)

1.3V'{

14

tsu(DAC)

1.3V'l

I+-

DBO-DB7

1.3V

~

tsu(D)

3.SV
0.3 V

th(DAC)

l~~~_

3.SV

4~~~---.14.1

3.SV

1.3V'\

WR

th(CS)

A~~~.1

i+-- tw(WR) ~

Data In Stable

For all input signals, tr = tf = 5 ns (10% to 90% points).

*

Figure 1. Setup and Hold Tim,es

~TEXAS

INSTRUMENTS
3-180

dB

1. OUTA, OUTB load 100 n, Cext 13 pF; WR and CS at a V; DBD-DB7 at a V to VDD or VDD to a V.
2. Gain error is measured using an internal feedback resistor. Nominal full scale range (FSR) = Vref - 1 LSB. Both DAC latches are
loaded with 11111111,
3. Vref = 20 V peak-to-peak, 1a-kHz sine wave
4. VrefA = VrefB = 10 V; OUTAlOUTB load = 100 n, Cext = 13 pF; WR and CS at a V; DBD-DB7 at a V to VDD or VDD to 0 V.
5. VrefA = 20 V peak-to-peak, 1a-kHz sine wave; VrefB = 0
6. VrefB = 20 V peak-to-peak, 1a-kHz sine wave; VrefA = a

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.3 V

0.3 V

th(D)

1.3V

3.SV
0.3 V

TLC7628C, TLC7628E, TLC76281
DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
SLAS063A - APRIL 1989 - REVISED MAY 1995

APPLICATION INFORMATION
These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant and 4-quadrant multiplication are shown in Figures 2 and 3. Input coding for unipolar and bipolar
operation are summarized in Tables 2 and 3, respectively.
VI(A)
±10V

••
•

Input
Buffer

>---.......-

vOA

I DB7

7

1-

Ig:2:'

6
15
16

CS

I

WR

Control
Logic

>----+-

7

VOB

,--------------,

RECOMMENDED TRIM
RESISTOR VALUES
R1, R3

R2, R4

500n
150n

VI(B)
±10V

NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment with
digital input of 255.
B. C1 and C2 phase compensation capacitors (10 pF to 15 pF) are required when using high-speed amplifiers to prevent ringing or
oscillation.

Figure 2. Unipolar Operation (2-Quadrant Multiplication)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-181

TLC7628C, TLC7628E, TLC76281
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS063A - APRIL 1989 - REVISED MAY 1995

APPLICATION INFORMATION
VI(A)

±10V

R6 (see Nole B)

20kn

VOA

6

15
16
VOB
7

(see Nole B)

,--------------,

R10

RECOMMENDED TRIM
RESISTOR VALUES

R1, R3
R2, R4

20kn

±10V

soon
Is0n

VI(B)

NOTES: A. RI, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Adjust RI for VOA = a V with
code 10000000 in DACA latch. Adjust R3 for Vas = a V with 10000000 in DACS latch.
S. Matching and tracking are essential for resistor pairs R6, R7, R9, and RIO.
C. CI and C2 phase compensation capacitors (10 pF to 15 pF) may be required if Aland A3 are high-speed amplifiers.

Figure 3. Bipolar Operation (4-Quadrant Operation)

Address Bus

AS-A1S 1-____-,

, - - - - - - -....-------1 DACA/DACB
Address
Decode
Logic
CPU

r:A)---~-a
CS
TLC7628
,------1_---------1 WR

8051

DBD

••

WR 1-------1

DB7
ALE

ADO-AD71-________________~D~a~la_B_u_s____________________v

NOTE D: A = decodl3d address for TLC7628 DACA
A + I = decoded address for TLC7628 DACB

Figure 4. TLC7628 -

Intel 8051 Interface

~TEXAS

INSTRUMENTS
3-182

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC7628C, TLC7628E, TLC76281
DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
SLAS063A- APRIL 1989 - REVISED MAY 1995

APPLICATION INFORMATION

Address Bus

A8-A15 t - - - - - - - ,

.------+------f DACAlDACB
Address
Decoder
Logic

--a

KA>-......

TLC7628

.---__--------f WR

CPU
6800

DBO

••

DB7

<1>21------1

DO-D71--_ _~------~D~a=ta~B~u=s---------~

NOTE 0: A = decoded address for TLC7628 DACA
A + 1 = decoded address for TLC7628 DACS

Figure 5. TLC7628 - 6800 Interface

voltage-mode operation
The current-multiplying DAC in these devices can be operated in a voltage mode. In the voltage mode, a fixed
voltage is placed on the current output terminal. The analog output voltage is then available at the reference
voltage terminal. An example of a current-multiplying DAC operating in voltage mode is shown in Figure 6. The
relationship between the fixed input voltage and the analog output voltage is given by the following equation:
Analog output voltage = fixed input voltage (D/256)
where D = the digital input. In voltage-mode operation, these devices meet the following specification:
LINEARITY ERROR

TEST CONDITIONS

Analog output voltage for REFA, REFS

R

VDD

=12 V,

OUTA or OUTS at 5 V,

TA =25°C

R

R

REF-'-V~-'-~VV~-'--~~-~~--,

(Analog output voltage)

R
'------+--i....----+-...- - - + - - i...._1--- OUT (Fixed Input voltage)
L----~....-

- - -__- - - - - i....~---AGND

Figure 6. Current-Multiplying DAC Operating in Voltage Mode

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-183

TLC7628C, TLC7628E, TLC76281
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLI:\S063A - APRIL'1989 - REVISED MAY 1995

PRINCIPLES OF OPERATION
These devices contain two, identical, 8-bit, multiplying DACs: DACA and DACB, Each DAC consists of an
inverted R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched between
the DAC output and AGND, thus maintaining a constant current in each ladder leg independent of the switch
state. Most applications require only the addition of an external operational amplifier and voltage reference. A
simplified D/A circuit for DACA or DACB with all digital inputs low is shown in Figure ?
Figure 8 shows the DACA or DACB equivalent circuit. Both DACs share the analog ground terminal 1 (AGND).
With all digit\ll inputs high, the reference currerit flows to OUTA. A small leakage current (llkg) flows across
internal junCtions, and as with most semiconductor devices, doubles every 10°C. The Co is caused by the
parallel combination of the NMOS switches and has a value that depends on the number of switches connected
to the output. The range of Co is 25 pF to 60 pF maximum. The equivalent output resistance (ro) varies with the
input code from 0.8R to 3R where R is the nominal value of the ladder resistor in the R-2R network.
These devices interface to a microprocessor through the data bus, CS, WR, and DACA/DACB control signals.
When CS and WR are both low, the analog output on these devices, specified by the DACNDACB control line,
responds to the activity on the DBa-DB? data bus inputs. In this mode, the input latches are transparent and
input data directly affects the analog output. When either the CS signal or WR signal goes high, the data on the
DBa-DB? inputs is latched until the CS and WR signals go low again. When CS is high, the data inputs are
disabled, regardless of the state of the WR signal.
.
The digital inputs of these devices provide TTL compatibility when operated from a supply voltage of 10.8 V to
15.?5 V.

R

REF

R

R
2R

2R

2R
RFB
S8

R
OUT

I

AGND

Figure 7. Simplified Functional Circuit for DACA or D.ACB

RFB
R

R

REF ---'\,/\/\.,-----....-----.--~.____- - OUTA

i

1/256

COUT

L-----~---*----AGND

Latch A or Latch B Loaded With 11111111

Figure 8_ TLC7628 Equivalent Circuit for DACA or DACB

~TEXAS

3-184

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

, TLC7628C, TLC7628E, TLC76281
DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
SLAS063A - APRIL 1989 - REVISED MAY 1995

PRINCIPLES OF OPERATION
Table 1. Mode Selection Table
DACA/DACB

CS

WR

DACA

DAce

L
H

L
L
H

L
L

X

X

H

Write
Hold
Hold
Hold

Hold
Write
Hold
Hold

X
X
L = low level,

H = high level,

Table 3. Bipolar (Offset Binary) Code

Table 2. Unipolar Binary Code
DAC LATCH CONTENTS
(see Note 7)
MSB

ANALOG OUTPUT

DAC LATCH CONTENTS
(see Note 8)
MSe

LSB

11111111
10000001
10000000
01111111
00000001
00000000

X = don't care

-VI (255/256)
-VI (129/256)
-VI (128/256) = - Vi/2
-VI (127/256)
-VI (1/256)
-VI (0/256) = 0

ANALOG OUTPUT

LSB

11111111
10000001
10000000
01111111
00000001
00000000

VI (1271128)
VI (1/128)
OV
-VI (1/128)
-VI (127/128)
-VI (128/128)

NOTES: 7. 1 LSB =(2 - 8)V1
8. 1 LSB = (2 - 7)VI

-!II

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3--185

3-186

TLV5613C, TLV56131
3 V TO 5 V a·BIT PARALLEL DIGITAL·TO·ANALOG CONVERTERS
WITH POWER DOWN
SLASI74- DECEMBER 1997

•
•
•
•

8 + 4 Bit Parallel Interface
Compatible with 8-Bit Microprocessor
Low Power Mode
Low Power Consumption:
7.25 mW or 1.8 mW for 5 V
3.93 mW or 0.87 mW for 3 V

•
•

Reference Input Buffers
Voltage Output Range 2 Times the
Reference Input Voltage
Monotonic Over Temperature

•

OW OR PW PACKAGE
(TOP VIEW)

05
06
07

AD
AI
SPEED
OVDD

Applications
•
•
•
•
•

Dl
DO
CS
WE
LDAC
PO
Vss
OUT
9

REFIN

Battery Powered Test Instruments
Digital Offset and Gain Adjustment
Battery Operated/Remote Industrial
Controls
Machine and Motion Control Devices
Cellular Telephones

:=w

description
The TLV5613 device is a 8-bit voltage output digital-to-analog converter (DAC) with a parallel interface
compatible with most 8-bit microprocessors. The TLV5613 has a low power mode, and address lines A 1 and
AO which determine whether the parallel data (up to eight bits) consists of LSB DAC data, MSB DAC data, or
control data. This control data gives the TLV5613 another method of setting power down and makes the low
power mode available.
There is an asynchronous LDAC pin for updating the output voltage, and a power down pin to ensure repeatable
startup conditions.
The resistor string output voltage is buffered by a x 2 gain rail-to-rail output buffer. The buffer operates with a
Class A output stage to improve stability and reduce settling time.
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
(OW)

TA
O°C 10 70°C

TLV5613CDW

TLV5613CPW

-40°C 10 85°C

TLV56131DW

TLV56131PW

PRODUCT PREVIEW information concerns products in the formative or
design ph... of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

SMALL OUTLINE
(PW)

~TEXAS

Copyright © 1997. Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-187

:>
w
a:

c.
I-

o
::::»
o
o
a:
c.

TLV5613C, TLV56131
3 V TO 5 V 8-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS174-DECEMBER 1997

functional block diagram
REFIN 19
DO
D1

12

8

B-Bit
LSW
Register

20

1
D2
2
D3
3
D4
4
D5
5
D6
6
D7

4

~

..!-

A1

"tJ

::JJ

0

7
8

~m'~

Register

WE

13
14

12-Bit
DAC
Latch

10

(

Address
Decoder

-V_

I

3-Bit
Control
Register

~

Select
Logic

I
15
9
-LDAC SPEED

"tJ

::JJ

m

S

m

==

3-188

~

-::...

C

.....

--.L 10

2

c:
0

DV DD

Resistor
String DAC

MSW
r----

I
cs

--.L

r-

3

AO

AVDD
11

"!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

16
PD

Control
Logic

Power-On
Reset

rJ

VSS

I

OUT

TLV5613C, TLV56131
3 V TO 5 V 8-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS174 - DECEMBER 1997

Terminal Functions
TERMINAL

NO.

NAME

1/0

DESCRIPTION

AVDD

11

AO

7

I

Address line

Power supply

A1

8

I

Address line

CS

13

I

Chip select

DVDD

10

DO (LSB)-D7
(MSB)

1-6,12,
20

Power supply

I

Parallel data input

LDAC

15

I

Load DAC

OUT

18

a

Analog output

PO

16

I

Power down

REFIN

19

I

Voltage reference input

SPEED

9

Speed control

VSS

17

Ground

WE

14

I

Write enable

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage (Voo to GND) ................................................................ 7 V
Analog input voltage range .................................................. - 0.3 V to Voo + 0.3 V
Reference input voltage range ........................................................ Voo + 0.3 V
Digital input voltage range to GND ........................................... - 0.3 V to Voo + 0.3 V
Operating free-air temperature range, TA: TLV5613C ................................. :.. DoC to 70 c C
TLV56131 ................................... -40°C to 85°C
Storage temperature range, T8t9 ................................................... -65°C to 150°C
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds ............................... 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute· maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions
MIN

NOM

Supply voltage, VDD (5·V Supply)

4.5

5

5.5

Supply voltage, VDD (3-V Supply)

2.7

3

3.3

High-level digital input voltage, VIH

IVDD

Low·level digital input voltage, VIL

IVDD

MAX

UNIT
V
V
V

2
0.8 VDD

V

Reference voltage, Vref to REFIN terminal (5V Supply)

2

2.048

VDD-1.1

V

Reference voltage, Vref to REFIN terminal (3V Supply)

2

1.024

VDD-1.1

Load resistance, RL

2

Load capacitance, C L
Operating free·air temperature, TA

I TLV5613C
I TLV56131

V

kn
100

pF

0

70

'C

-40

85

'C

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-189

3:
w

s:w
a::

D.
~

o

::l
C

oa::

D.

TLV5613C, TLV56131
3 V TO 5 V 8-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS174 - DECEMBER 1997

electrical characteristics over recommended operating free-air temperature range, VDD =5 V±10%,
VDD = 3 V ± 10%, Vref(REFIN) = 2.048 V, Vref(REFIN) = 1.024 V (unless otherwise noted)
static DAC specifications
PARAMETER

EZS

EG

TEST CONDITIONS

Resolution

Vref(REFIN) = 2.048V, 1.024V

Integral nonlinearity (INL), end pOint adjusted

Vref(REFIN) = 2.048V, 1.024V,

MIN

MAX

UNIT

See Note 1

±3

LSB
LSB

Differential nonlinearity (DNL)

VrefiREFIN) = 2.048V, 1.024V,

See Note 2

±0.5

Vref(REFIN) = 2.048V, 1.024V,

See Note 3

±12

Zero-scale-error temperature coefficient

VrefiREFIN) = 2.048V, 1.024V,

See Note 4

Gain error

Vref(REFIN) = 2.048V, 1.024V,

See Note 5

Vref(REFIN) = 2.048V, 1.024V,

See Note 6

±0.29
1

5-V supply
65
dB
65

3-V Supply

Gain

"'0

o-I
"'0

:c

m
<
m
:E

-

PpmrC

See Notes 7 and 8
Zero scale

:c
oc
c

%ofFS
voltage

65

Gain
Power-supply rejection ratio

MV
Ppm/oC

3

Zero scale

NOTES:

bits

Zero-scale error (offset error at zero scale)

Gain error temperature coefficient

PSRR

TYP

8

65

1. The relative accuracy or Integral nonlinearity (INL) sometimes referred to as linearity error, IS the maximum deviatIOn of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
2. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (T max) - EZS (Tmin)]Nref x 1OS/(Tmax - T min).
5. Gain error is the deviation from the ideal output (Vref - 1 LSB) with an output load of 10 kQ excluding the effects of the zero-error.
6. Gain temperature coefficient is given by: EG TC = [EG(Tmax) - EG (T min)]Nref x 106/(T max - T min).
7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4,5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the zero-code output voltage.
8. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero scale change.

output specifications
PARAMETER
Va

TEST CONDITIONS

Voltage output range
Output load regulation accuracy

VO(OUT) = 4.096 V,
Vref(REFIN) = 2.048 V

MIN

TYP

MAX

UNIT

TBD

V

RL = 2 kO

TBD

%ofFS
voltage

5-V Supply

TBD

3-V Supply

TBD

5-V Supply

TBD

3-V Supply

TBD

rnA

IOSC(sink)

Output short circuit sink current

IOSC(source)

Output short circuit source current

IO(sink)

Output sink current

TBD

rnA

IO(source)

Output source current

TBD

rnA

-!!1
TEXAS
INSTRUMENTS
3-190

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

rnA

TLV5613C, TLV56131
3 V TO 5 V 8-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS174- DECEMBER 1997

electrical characteristics over recommended operating free-air temperature range, Voo = 5 V±10%,
Voo 3 V ± 10%, Vref(REFIN) 2.048 V, Vref(REFIN) 1.024 V (unless otherwise noted)

=

=

=

reference input (REFIN)
PARAMETER
VI

Input voltage range

Ri

Input resistance

Ci

Input capacitance

TEST CONDITIONS

MIN

TYP

0

Reference feed through

UNIT
V

10

MQ

5

pF

REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 9)

TBO

Small
signal

1.6

MHz

Large
signal

3.3/21tV m

MHz

Small
signal

1

MHz

Large
signal

3.3/91tV m

MHz

Fast
mode
REFIN = 0.2 Vpp + 1.024 V dc

Reference input bandwidth

MAX
VOO-1.1

Slow
mode

NOTE 9: Reference feedthrough is measured at the OAC output with an input code = 000 hex and a Vref(REFIN) input = 1.024 V dc + 1 Vpp at 1 kHz.

digital inputs (00- 011, CS, WE, LOAC, Power Down)
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IIH

High-level digital input current

VI = VOO

±1

flA

IlL

Low-level digital input current

VI=OV

±1

!LA

Ci

Input capacitance

8

pF

power supply
PARAMETER

100

Power supply current

TEST CONDITIONS
No load
All inputs 0 V or VOO

MIN

TYP

MAX

15-V Supply

1.45

1.9

13-V Supply

1.31

1.69

Power down supply current

0.17

UNIT
mA

!LA

3:
w

:>
w
a:
a..

....o

::l

o

oa:
a..

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3--191

TLV5613C, TLV56131
3 V TO 5 V 8-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS174- DECEMBER 1997

operating characteristics over recommended operating free-air temperature range, Voo
±10%, Voo 3 V ± 10%, Vref(REFIN) 2.048 V, Vref(REFIN) 1.024 V

=

=

=

=5 V

analog output dynamic performance
PARAMETER

TEST CONDITIONS

MIN

SR+

Output slew rate, positive

CL = 100 pF,
RL= 10kn,
Code 32 to Code 4096,

SR-

Slew rate, negative

CL = 100 pF,
RL=10kn,
Code 32 to Code 4096,

Vref(REFIN) = 2.048 V, 1.024 V,
TA= 25°C,
Vo from 10% to 90%

ts

Output settling time
(Full scale)

To ±0.5 LSB,
RL= 10kn,

CL = 100 pF,
See Note 10

8

V/IJS

5V
To±0.5 LSB,
RL = 10 kn,

CL = 100 pF,
See Note 11
3V

'"t'J

:c
oc
c:

o-I

S/(N+D)

UNIT

V/IJS

3V

Output settling time,
(Code-to-Code)

MAX

8

5V

ts(c)

TYP

Vref(REFIN) = 2.048 V, 1.024 V,
TA = 25°C,
Vo from 10% to 90%

Fast

0.9

1.3

Slow

3.4

5.2

Fast

0.8

1.1

Slow

3.1

3.9

Fast

TBD

Slow

TBD

Fast

TBD

Slow

TBD

Glitch energy

TBD

Signal to noise + distortion

TBD

I1S

I1S

..

NOTES: 10. Settling time IS the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital Input code change
of 020 hex to 3FF hex or 3FF hex to 020 hex.
11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of one count.

'"t'J operating characteristics over recommended operating free-air temperature range, Voo =5 V ±5%,

:c

m
S
m

:e

VOO

=3V ± 5%, Vref(REFIN) =2.048V, Vref(REFIN) =1.024V

digital input timing requirements
MIN
tsu(D-WE)

Setup time, data ready before positive WE edge

tsu(CS-WE)

Setup time, CS low before positive WE edge

tsu(A-WE)

Setup time, address bits AD, A1

tH(D)

Hold time, data held after positive WE edge

ts

Settling time, full scale

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

UNIT

ns
ns
ns

0

0.9

-!!1

MAX

ns

13
TBD

TEXAS
INSTRUMENTS
3-192

NOM

9

I1s

TLV5613C, TLV56131
3 V TO 5 V 8-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS174-DECEMBER 1997

A1

fOSS' X X X

X

00-07

1

f

X

14

I
A2

cs~
~

I
WE

I
I
I

\
/

X

tsu(A.WE)

I
I

I
I
I
I
I
I

X

X

CTRL

~

X

\
\

/
/

X

X

7
7

~
~

/

~

I

X

tsu(O.WE)

~

\

X

~

LSBs

tsu{CS·WE)

\J

\

\

/

/

LDAC
ts

~

~

-==>
W

,-VV¥-

r

OUT

W

a:

::; Final Value +/- 0.5 LSB

C.

Figure 1. Timing Diagram

I0

::J
C

0
a:
c.

.~TEXAS

. INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-193

3-194

TLV5619C, TLV56191
3 V TO 5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS172 - DECEMBER 1997

•
•
•
•

•
•
•
•

OW OR PW PACKAGE
(TOP VIEW)

New 12-Bit Parallel Interlace
Compatible with TMS320 DSP Line
Internal Power on Reset
Low Power Consumption:
7.25 mW for 5-V Supply
3.93 mW for 3-V Supply

02

01

00

CS
WE
LOAC

Reference Input Buffers
Voltage Output Range 2 Times the
Reference Input Voltage
Monotonic Over Temperature
Asynchronous or Synchronous Update

PO

Vss

08
09

OUT
REFIN

010
011

VDD

applications
•
•
•
•
•

Battery Powered Test Instruments
Digital Offset and Gain Adjustment
Battery Operated/Remote Industrial
Controls
Machine and Motion Control Devices
Cellular Telephones

description
The TLV5619 device is a 12-bit voltage output digital-to-analog converter (DAC) with a TMS320 compatible
parallel interface. While accepting 12-bit data words, the TLV5619 only dissipates 7.25 mW of power with a 5-V
supply and 3.93 mWof power with a 3-V supply.
There is an asynchronous LDAC pin for updating the output voltage, and a power down pin to ensure repeatable
startup conditions.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer operates with a
Class A output stage to improve stability and reduce settling time.
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
(OW)

TA

SMALL OUTLINE
(PW)

aoc to 7aoc

TLV5619CDW

TLV5619CPW

-4aoc to 85°C

TLV56191DW

TLV56191PW

PRODUCT PREVIEW information concerns products in the formative or
phase of development. C~aracteristic data and other

desi~n

:~:::~I~~:c:~~:~~!~a~~~~~~: ::~~::;~::e~rves

the right to

~TEXAS

Copyright © 1997, Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-195

3:
w
:>
w
a:
c.
I-

o

~

c

oa:

c.

TLV5619C, TLV56191
3 V TO 5 V 12·81T PARALLEL DIGITAL·TO·ANALOG CONVERTERS
WITH POWER DOWN
SLAS172 - DECEMBER 1997

functional block diagram
REFIN

DO

19

"tJ

:xl

0

CS
WE

r-V

12
20

01
1
02
2
03
3
04
4
05
5
06
6
07
7
08
8
09
9
010
10
011

13
14

12-8it
Input
r - - Register

,--t

12-8it
'OAC
Latch

I

Select
and
Control
Logic
115

16
LOAC

-I
"tJ

:xl

m
<
-m

:e

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 752G5

~

10

2

0

3-196

Resistor
String OAC

12

12

C

c::

VOO

--.L 11

-'=

Power-On
Reset

I
~

VSS 17

OUT

TLV5619C, TLV56191
3 V TO 5 V 12-81T PARALLEL DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS172 - DECEMBER 1997

Terminal Functions
TERMINAL
NAME

NO.

110

DESCRIPTION

CS

13

I

Chip select

DO (LSB)

12

I

Parallel data input

D1

20

I

Parallel data input

D2

1

I

Parallel data input

D3

2

I

Parallel data input

D4

3

I

Parallel data input

D5

4

I

Parallel data input

D6

5

I

Parallel data input

D7

6

I

Parallel data input

DB

7

I

Parallel data input

D9

8

I

Parallel data input

D10

9

I

Parallel data input

D11 (MSB)

10

I

VSS

17

Parallel data input
Ground

LDAC

15

I

Load DAC

OUT

18

0

Analog output

PO

16

I

REFIN

19

I

Voltage reference input

I

Write enable

VOD

11

WE

14

3:
w

:>
w
a::

Positive power supply

c..
I-

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage (Voo to GND) ................................................................ 7 V
Analog input voltage range .................................................. - 0.3 V to Voo + 0.3 V
Reference input voltage ............................................................. Voo + 0.3 V
Digital input voltage range to GND ........................................... - 0.3 V to VOD + 0.3 V
Operating free-air temperature range, TA: TLV5619C .................................... DoC to 70°C
TLV56191 ................................... -40°C to 85°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-197

o::)
c

oa::

c..

TLV5619C, TLV56191
3 V TO 5 V 12·BIT PARALLEL DIGITAL·TO·ANALOG CONVERTERS
WITH POWER DOWN
SLAS172 - DECEMBER 1997

recommended operating conditions
MIN

NOM

Supply voltage, Voo (5-V Supply)

4.5

5

5.5

V

Supply voltage, Voo (3-V Supply)

2.7

3

3.3

V

High-level digital input voltage, VIH

I VOO

Low-level digital input voltage, VIL

Ivoo

MAX

2

V
0.8 VOO

V
V

Reference voltage, Vref to REFIN terminal (5-V Supply)

2

2.048

VOO-1.1

Reference voltage, Vref to REFIN terminal (3-V Supply)

2

1.024

VOO-1.1

Load resistance, RL

2

Operating free-air temperature, TA

I TLV56191

"'C

:lJ

o
C

c:

o-I
"'C

:lJ

m
m

<

~

~'TEXAS

INSTRUMENTS
3-198

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

V

kQ
100

pF

0

70

°C

-40

85

°C

Load capacitance, CL
I TLV5619C

UNIT

TLV5619C, TLV56191
3 V TO 5 V 12·81T PARALLEL DIGITAL·TO·ANALOG CONVERTERS
WITH POWER DOWN
SLAS172 - DECEMBER 1997

=

electrical characteristics over recommended operating free-air temperature range, VDD 5 V
3 V ± 10%, Vref(REFIN) 2.048 V, Vref(REFIN) 1.024 V (unless otherwise noted)

± 10%, VDD

=

=

=

static DAC specifications
PARAMETER

EZS

EG

TEST CONDITIONS

Resolution

Vref(REFIN}= 2.048 V, 1.024 V

Integral nonlinearity (INL), end point adjusted

Vref(REFIN) = 2.048 V, 1.024 V,

MIN

TYP

MAX

UNIT

See Note 1

±3

LSB
LSB

12

bits

Differential nonlinearity (DNL)

Vref(REFIN} = 2.048 V, 1.024 V,

See Note 2

±0.5

Zero-scale error (offset error at zero scale)

Vref(REFIN) = 2.048 V, 1.024 V,

See Note 3

±12

Zero-scale-error temperature coefficient

Vref(REFIN) = 2.048 V, 1.024 V,

See Note 4

Gain error

Vref(REFIN} = 2.048 V, 1.024 V,

See Note 5

Vref(REFIN) = 2.048 V, 1.024 V,

See Note 6

Gain error temperature coefficient

±0.29

%ofFS
voltage

ppm/'C

1

Zero scale

MV

ppm/'C

3

65
5-V Supply

PSRR

Power-supply'rejection ratio

Gain

65
See Notes 7 and 8

dB

Zero scale

65

3-V Supply

65

Gain
NOTES:

1. The relative accuracy or Integral nonllneanty (INL) sometimes referred to as linearity error, IS the maximum deViation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
2. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (T max) - EZS (Tmin))IVref x 106/(T max - T min).
5. Gain error is the deviation from the ideal output (Vref - 1 LSB) with an output load of 10 kQ excluding the effects of the zero-error.
6. Gain temperature coefficient is given by: EG TC = [EG(T max) - EG (T min}]IVref x 106/(T max - T min)·
7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the zero-code output voltage.
8. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V de and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero scale change.

output specifications
PARAMETER
Vo

TEST CONDITIONS

Voltage output range
Output load regulation accuracy

VO(OUT) = 4.096V, 2.048V

MIN

TYP

MAX

I,lNIT
V

TBD

%ofFS
voltage

5-V Supply

TBD

3-V Supply

TBD

mA

IoSC(sink)

Output short circuit sink current

IOSC(source)

Output short circuit source current

IO(sink)

Output sink current

TBD

rnA

IO(source}

Output source current

TBD

mA

TBD

3-V Supply

TBD

mA

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

w

~

D.
I-

o

::l
C

o~

D.

TBD
RL=2 k(!

5-V Supply

3:
w
:;:

3-199

TLV5619C, TLV56191
3 V TO 5 V 12·81T PARALLEL DIGITAL·TO·ANALOG CONVERTERS
WITH POWER DOWN
SLAS172 - DECEMBER 1997

=

electrical characteristics over recommended operating free-air temperature range, VDD 5 V
3 V ± 10%, Vref(REFIN) 2.048 V, Vref(REFIN) 1.024 V (unless otherwise noted)

± 10%, VDD

=

=

=

reference input (REFIN)
PARAMETER
VI

Input voltage range

Ri

Input resistance

Ci

Input capacitance

TEST CONDITIONS

MIN

TVP

MAX

0

Reference feed through

REFIN = 1 Vpp at 1 kHz + 1.024 V de (see Note 9)

Reference input bandwidth

REFIN '" 0.2 Vpp + 1.024 V de

VOo-1.1

UNIT
V

10

MO

5

pF

1.6

MHz

NOTE 9: Reference feedthrough IS measured at the OAC output with an Input code '" O?O hex and a Vref(REFIN) Input '" 1.024 V de + 1 Vpp at 1 kHz.

digital inputs (DO - D11, CS, WE, LDAC, Power Down)
PARAMETER
IIH

High-level digital input current

IlL

Low-level digital input current

Ci

Input capacitance

.TEST CONDITIONS

,

MIN

TVP

MAX

UNIT

VI ",VOO

±1

~

VI=OV

±1

~A

pF

8

." power supply

:D

o
C

100

c:

o

-I

m

-

tsu(CS-WE)

/

w

a:

ts

OUT

D..

/

\

LOAC

lOIII

tO

1
.1

::l
C

vv:~--,--

oa:

I

::::; Final Value +/- 0.5 LSB

D..

Figure 1. Timing Diagram

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-201

3-202

TLV5620C, TLV56201
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B-JANUARY 1995- REVISED APRIL 1997

•
•
•
•
•
•
•
•
•

o OR N PACKAGE

Four a-Bit Voltage Output DACs
3-V Single-Supply Operation
Serial Interface
High-Impedance Reference Inputs
Programmable for 1 or 2 Times Output
Range

(TOP VIEW)

GND
REFA

REFC
REFD

Simultaneous Update Facility
Internal Power-On Reset
Low-Power Consumption
Half-Buffered Output

VDD

11

LDAC
DACA
DACB
DACC

applications
•
•
•
•
•
•

Programmable Voltage Sources
Digitally Controlled Amplifiers!Attenuators
Mobile Communications
Automatic Test Equipment
Process Monitoring and Control
Signal Synthesis

description
The TLV5620C and TLV56201 are quadruple 8-bit voltage output digital-to-analog converters (DACs) with
buffered reference inputs (high impedance). The DACs produce an output voltage that ranges between either
one or two times the reference voltages and GND; and, the DACs are monotonic. The device is simple to use,
because it runs from a single supply of 3 V to 3.6 V. A power-on reset function is incorporated to ensure
repeatable start-up conditions.
Digital control of the TLV5620C and TLV56201 is over a simple three-wire serial bus that is CMOS compatible
and easily interfaced to all popular microprocessor and microcontroller devices. The 11-bit command word
comprises eight bits of data, two DAC select bits, and a range bit, the latter allowing selection between the times
1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be
written to the device, then all DAC outputs update simultaneously through control of LDAC. The digital inputs
feature Schmitt triggers for high noise immunity.
The 14-terminal small-outline (SO) package allows digital control of analog functions in space-critical
applications. The TLV5620C is characterized for operation from O°C to 70°C. The TLV56201 is characterized
for operation from -40°C to 85°C. The TLV5620C and TLV56201 do not require external trimming.
AVAILABLE OPTIONS
PACKAGE
TA
O°C

to 70°C
to 85°C

-40°C

SMALL OUTLINE
(0)

PLASTIC DIP
(N)

TLV5620CD

TLV5620CN

TLV5620lD

TLV5620lN

~TEXAS

Copyright © 1997, Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-203

TLV5620C, TLV56201
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS110B -JANUARY 1995 - REVISED APRIL 1997

functional block diagram

12

:>-<......-

DACA

:>-<......--'-11'- DAce

>...-_1.:..:0,- DACC

:>-<......-'9=- DACD

ClK 7
Serial
Interface

DATA 6
lOAD 8

13
LDAC

Power-On
Reset

Terminal Functions
TERMINAL

1/0

DESCRIPTION

7

I

Serial interface clock. The input digiial data is shifted into the serial interface register on the falling edge of the clock
applied to the ClK terminal.

DACA

12

0

DAC A analog output

DACB

0

DAC B analog output

DACC

11
10

0

DAC C analog output

DACb

9

0

DAC D analog output

DATA

6

I

Serial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially.
Each data bit is clocked into the register on the falling edge of the clock signal.

GND

1
13

I

Ground return and reference terminal

lDAC

I

Load DAC. When this signal is high, no DAC output updates occur when the input digital data is read into the serial
interface. The DAC outputs are only updated when LDAC is taken from high to low.

LOAD

8

I

Serial interface load control. When the LDAC terminal is low, the falling edge of the LOAD signal latches the digital
data into the output latch and immediately produces the analog voltage at the DAC output terminal.

REFA

2

I

Reference voltage input to DAC A. This voltage defines the output analog range.

REFB

3

I

Reference voltage input to DAC B. This voltage defines the analog output range.

REFC

4

I

Reference voltage input to DAC C. This voltage defines the analog output range.

5

I

Reference voltage input to DAC D. This voltage defines the analog output range.

14

I

Positive supply voltage

NAME
ClK

REFD
VDD

NO.

~TEXAS

3-204

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLV5620C, TLV56201
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS110B -JANUARY 1995 - REVISED APRIL 1997

detailed description
The TlV5620 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with
256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected
to GND and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use
of the resistor strings. Linearity depends upon the matching of the resistor segments and upon the performance
of the output buffer. Since the inputs are buffered, the DACs always presents a high-impedance load to the
reference source.
Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times 1 or
times 2 gain.
On power up, the DACs are reset to CODE O.
Each output voltage is given by:
V O(DACAIBICiD) = REF x

Cg~E

x (1

+ RNG bit value)

where CODE is in the range 0 to 255 and the range (RNG) bit is aO or 1 within the serial control word.

Table 1. Ideal Output Transfer
07

06

05

04

03

02

01

DO

0

0

0

0

0

0

0

0

GND

0

0

0

0

0

0

0

1

1

·· ·· ··

(1/256) x REF (1+RNG)

1

1

1

(127/256) x REF (1+RNG)

0

0

0

0

(128/256) x REF (1 +RNG)

1

1

1

(255/256) x REF (1 +RNG)

··
··
0

1

1

··
··
1

0

1

··
··
1

0

1

··
··
1

0

1

··
··

·· ·· ··

1

OUTPUT VOLTAGE

··
··

data interface
With lOAD high, data is clocked into the DATA terminal on each falling edge of ClK. Once all data bits have
been clocked in, lOAD is pulsed low to transfer the data from the serial input register to the selected DAC as
shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when lOAD goes low. When
lDAC is high during serial programming, the new value is stored within the device and can be transferred to
the DAC output at a later time by pulsing lDAC low as shown in Figure 2. Data is entered MSB first. Data
transfers using two a-clock-cycle periods are shown in Figures 3 and 4.
Table 2 lists the A 1 and AO bits and the selection of the updated DACs. The RNG bit controls the DAC output
range. When RNG = low, the output range is between the applied reference voltage and GND, and when
RNG = high, the range is between twice the applied reference voltage and GND.

Table 2. Serial Input Decode
OACUPOATEO

A1

AD

0

0

DACA

0

1

DACB

1

0

DAce

1

1

DACD

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-205

TLV5620C, TLV56201
QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLASll0B - JANUARY 1995 - REVISED APRIL 1997

ClK

--t

I+-

11

I

tsu(DATA-ClK)

tsu(lOAD-ClK) --r---I4--~~1

14- tv(DATA-ClK)

1

DATA

A1

lOAD

Figure 1_ LOAD-Controlled Update (LDAC = Low)
ClK

DATA

D1

DO

tsu(lOAD-lDAC) -j4+I

~~i-

lOAD

tW(lDAC)~

V

lDAC

1
DAC Update

Figure 2_ LDAC-Controlled Update

~TEXAS

3-206

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5620C, TLV56201
QUADRUPLE a·DIGITAL·TO·ANALOG CONVERTERS
SLAS110B -JANUARY 1995 - REVISED APRIL 1997

'i
0
..J

..

II

'C

(J



3

2.5

2.5

2

I

I

8.

~

1.5

I

~
'5

~

0

~I

0.5

~~

I

~

NEGATIVE FALL TIME AND SETTLING TIME

3

0
-0.5

-1

o

I

.

II

4

6

8

10

12

-

1.5

01

=

\

~
'5

VDD= 3V
TA=25°C
Code 00 to
FFHex
Range =x2
Vref = 1.25 V
(see Note A)

S-

14

16

18

\

0.5

O

\

I

~

0

""

-0.5

I I I
2

-

VDD=3V
TA = 25°C
Code FFto
00 Hex
Range = x2
Vref = 1.25 V (see Note A)

2

>

-1

20

o

2

Time-Ils

4

6

8

10

12

14

16

18

20

Tlme-Ils

NOTE A: Rise time - 2.051ls, positive slew rate _ 0.96 V/IlS, settling
time = 4.5 Ils.

NOTE A: Fall time = 4.251ls, negative slew rate = 0.46 VIllS, settling
time = 8.5 Ils.

Figure 3

Figure 4

~lExAs

INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75266

3-211

TLV5620C, TLV56201
QUADRUPLE 8-BIT DIGITAL·TO-ANALOG CONVERTERS
SlJ\Sl10B - JANUARY 1995 - REVISED APRIL 1997

TYPICAL CHARACTERISTICS
DAC OUTPUT VOLTAGE

DAC OUTPUT VOLTAGE

vs

vs

OUTPUT LOAD

OUTPUT LOAD
1.6

3
2.8

>

1.4

>

I

2.6

I

1
~
:i

~

0

()

~

:i
CL
:i

2.2
2

0.8

0

()

'"

1.8
1.6

~

1.4

I

f

2.4

'"
Q

1.2

II)

I

II)

0.6

Q

I

~

VOO= 3V,
Vref = 1.5 V,
Range=2x

0.4

1.2

1

o

10

20

30 40 50 60 70 80
RL - Output Load - kQ

VOO=3V,
Vref = 1.5 V,
Range = lx

0.2

o
o

90 100

10

20

30

40

Figure 6
SUPPLY CURRENT

vs
TEMPERATURE
1.2
Range=x2
Input Code = 255
VOO =3V
Vref = 1.25 V

1.15
1.1

C
...2!

1.05

E
I

"

()

J!o

CL
CL

"I

(/)

0.95

---

,--

Q

E

0.9
0.85
0.8
-50

o

.........

50

t - Temperature - °C

Figure 7

~1ExAs

INSTRUMENTS

3-212

60

I

I

70

80

RL - Output Load - kQ

Figure 5

'"

50

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

"'
100

-

I
90 100

TLV5620C, TLV56201
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLASll0B-JANUARY 1995- REVISED APRIL 1997

APPLICATION INFORMATION
TLV5620

DACA t - -....---'I
DAce
DACC
R
DACD

Vo

NOTE A: Resistor R ;;, 10 kg

Figure 8. Output Buffering Scheme

:illExAs
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS, TEXAS 75265

3-213

3-214

TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
38B - APRIL 1996 - REVISED FEBRUARY

•

2.7-V to S.S-V Single-Supply Operation

•

Low Power Consumption

•

Three a-Bit Voltage Output DACs

•

Half-Buffered Output

•

One-Half Power a-Bit Voltage Output DAC

•

Power-Down Mode

•

Fast Serial Interface . .. 1 MHz Max

•

Simple Two-Wire Interface In Single
Buffered Mode

•

Programmable Voltage Sources

•

High-Impedance Reference Inputs For Each
DAC

•

Digitally-Controlled Amplifiers/Attenuators

•

Cordless/Wireless Communications

•

Programmable for 1 or 2 Times Output
Range

•

Automatic Test Equipment

•

Portable Test Equipment

•

Simultaneous-Update Facility In
Double-Buffered Mode

•

Process Monitoring and Control

•

Internal Power-On Reset

•

Signal Synthesis

•

Industry Temperature Range

applications

o PACKAGE
(TOP VIEW)

description
The TLV5621I is a quadruple 8-bit voltage output
digital-to-analog converter (DAC) with buffered
reference inputs (high impedance). The DAC
produces an output voltage that ranges between
either one or two times the reference voltages and
GND, and the DAC is monotonic. The device is
simple to use since it operates from a single
supply of 2.7 V to 5.5 V. A power-on reset function
is incorporated to provide repeatable start-up
conditions. A global hardware shut-down terminal
and the capability to shut down each individual
DAC with software are provided to minimize
power consumption.

GND
REFA
REFB
REFC

1

4

VDD
HWACT
11

DACA
DACB
DACC

Digital control of the TLV5621I is over a simple 3-wire serial bus that is CMOS compatible and easily interfaced
to all popular microprocessor and microcontroller devices. A TLV5621I 11-bit ,command word consists of
eight bits of data, two DAC select bits, and a range bit for selection between the times one or times two output
range. The TLV5621I digital inputs feature Schmitt triggers for high noise immunity. The DAC registers are
double buffered which allows a complete set of new values to be written to the device, and then under control
of the HWACT signal, all of the DAC outputs are updated simultaneously.
The 14-terminal small-outline (D) package allows digital control of analog functions in space-critical
applications. The TLV5621I does not require external trimming. The TLV5621I is characterized for operation
from -40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA

-40'C to 85'C

SMALL OUTLINE

(0)
TLV56211D

~TEXAS

Copyright © 1997, Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-215

TLV5621I
LOW·POWER QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTER
SLAS138B- APRIL 1996 - REVISED FEBRUARY 1997

functional block diagram
REFA

>-.....--DACA
REFB

>-.....--DACB
REFC

>----.---

DACC

>-.....- -

DACD

REFD

ClK
DATA
EN
HWACT

Power-On
Reset

Serial
Interface

Terminal Functions
TERMINAL
NAME
ClK

NO.

7
12

110
I

DACC

11
10

DACD

9

0
0
0
0

DATA

6

I

EN

8

I

GND

1

DACA
DACB

DESCRIPTION
Serial interface clock, data enters on the negative edge
DAC A analog output
DAC B analog output
DAC C analog output
DAC D analog output
Serial-interface digital-data input
Input enable
Ground return and reference

13
2

I

Global hardware activate

I

Reference voltage input to DACA

I

Reference voltage input to DACB

REFC

3
4

I

Reference voltage input to DACC

REFD

5

I

Reference voltage input to DACD

HWACT
REFA
REFB

VDD

14

Positive supply voltage

detailed description
The TLV5621 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with
256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected
to GND and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use
of the resistor strings. Linearity depends upon the matching of the resistor elements and upon the performance
of the output buffer. Because the inputs are buffered, the DACs always present a high-impedance load to the
reference source.

~TEXAS

3-216

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLV5621I
LOW·POWER QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTER
SLAS138B- APRIL 1996 - REVISED FEBRUARY 1997

Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times one
or times two gain.
On power-up, the DACs are reset to CODE O.
Each output voltage is given by:
VdDACAIBICiD)

=

REF x

C~~E

x (1

+ RNG bit value)

where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word.

Table 1. Ideal-Output Transfer
07

06

05

04

03

02

01

DO

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

·· ·· ··
·· ·· ··

OUTPUT VOLTAGE
GND
(1/256)

x REF (1+RNG)

0

1

1

·· ·· ·· ·· ··
1

1

1

1

1

(127/256)

1

0

0

0

0

0

0

0

(128/256)

x REF (1+RNG)
x REF (1+RNG)

1

1

1

1

1

1

1

1

(255/256)

x REF (1 +RNG)

·· ·· ·· ·· ··

··
··

data interface
The data interface has two modes of operation; single and double buffered. Both modes serially clock in bits
of data using DATA and ClK whenever EN is high. When EN is low, ClK is disabled and data cannot be loaded
into the buffers.
In the single buffered mode, the DAC outputs are updated on the last/twelfth falling edge of ClK, so this mode
only requires a two-wire interface with EN tied high (see Figure 1 and Figure 2).
In the double buffered mode (startup default), the outputs of the DACs are updated on the falling edge of the
EN strobe (see Figure 3 and Figure 4). This allows multiple devices to share data and clock lines by having only
separate EN lines.

single-buffer mode (MODE

= 1)

When a two wire interface is used, EN is tied high and the input to the device is always active; therefore, random
data can be clocked into the input latch. In order to regain word synchronization, twelve zeros are clocked in
as shown in Figure 1, and then a data or control word is clocked in. In Figure 1, the MODE bit is set to one, and
a control word is clocked in with the DAC outputs becoming active after the last falling edge of the control word.
Figure 2 shows valid data being written to a DAC, note that ClK is held low while the data is invalid. Data can
be written to all four DACs and then the control word is clocked in which sets the MODE bit to 1. At the end of
the control word, the data is latched to the inputs of the DACs.
Note that once the MODE bit has been set, it is not possible to clear it, i.e., it is not possible to move from single
to double-buffered mode.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-217

~

en
S;;
en

00

~
OJ

ClK

I

»'U
:IJ

r=

~

'"I

DATA

:IJ

m
:5
en
m
0

DAC

"m
OJ
:IJ

c
»
:IJ
-<

EN
(Tied High)

U;

<0

~

NOTE A: Twelve zeros enable word synchronization and the output can change after the leading edge of ClK depending on the data in the latches.

Figure 1. Register Write Operation Following Noise or Undefined levels on DATA or elK (Single-Buffer Mode)

o_~
:HZ
-.

~c::~
~~;l>
tli
...,
Rl

8l

::ec.n
"tJm
O~

~-

m

:XJ

"c:

:J>
C
:XJ

c:

"tJ

r

m

co

•
m
=i

c

G)

r;-

9

ClK

:J>
Z
:J>

~ lT1(I)

~~

O~

~

~(I)

~;Jd

"

r-l

r
0

DATA

G)

0

0

DAC

Z

<
m

EN

:XJ
-I

(Tied High)

m

NOTE A: EN is held high and data is written to a DAC register. The data is latched to the output of the DAC on the falling edge of the last ClK of the control word, where the
mode is set.

Figure 2. First Nonzero Write Operation After Startup (EN

= High)

::;D

TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B - APRIL 1996 - REVISED FEBRUARY 1997

double-buffered mode (MODE

=0)

In this mode, data is only latched to the output of the DACs on the falling edge of the EN strobe. Therefore, all
four DACs can be written to before updating their outputs.
Any number of input data blocks can be written with all having the same length. Subsequent data blocks simply
overwrite previous ones with the same address until EN goes low.
Multiple data blocks can be written in any sequence provided signal timing limits are met. The negative going
edge of EN terminates and latches all data.
Multiple Random Sequence Data Blocks
DATA

II

II
Data Latched Into DAC Control Registers and Control Word

\.

t

Figure 3. Data and Control Serial Control

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-219

%
o

(/)

;;;
ex>

elK

(IJ

I

»

-0
:IJ

;=
co
co

DATA

0>

I
:IJ

m

<

DAC

i'ii
m
0

EN

---1

.- -

...-~

U

tL....-_

-n
m
(IJ

:IJ

c

»
-<

:IJ

NOTE A: Data is written to the output of a DAC, and the data is latched to the output on the falling edge of EN. A control word then selects double-buffered mode. When the
range is changed, the output changes on the falling edge of EN.

(!l
~

o_~

~2
m(/)

!!III.

~~d
~~~

~~;;J>
~lT.IUl

~~
&;

~

r--t

> 0,<
::EUI
(/)

N

Figure 4. First Nonzero Write Operation After Startup

co
~

"tIQ)

O~

=em

::D

0

c:
l>

0

::D

c:
"tI
r-

m
•
aJ
:::::;

ClO

0

C5
~

r:-

9l>
Z
l>

r-

0

C)

0

0

Z

<
m

::D

-t

m

::D

TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B- APRIL 1996 - REVISED FEBRUARY 1997

control register
The control register contains ten active bits. Four bits are range select bits as on the TLC5620. The register also
contains a software shutdown bit (ACT) and four shutdown inhibit bits (SIA, SIB, SIC, SID). The shutdown inhibit
bits act on each DAC (DACA through DACD). The mode select bit is used to change between single and double
buffered modes. The bits in the control register are listed in Table 2.
Table 2. Control Register Bits
BIT

FUNCTION

MODE

Selection bit for type of interface (see data interface section)

RNGA

Range select bit for DACA, 0 ~ x 1, 1 ~ x 2

RNGB

Range select bit for DACB, 0 ~ X 1, 1 = x2

RNGC

Range select bit for DACC, 0 = X 1, 1 = X 2
Range select bit for DACD, 0 = X 1, 1 = x2

RNGD
SIA

Shutdown inhibit bit for DACA

SIB

Shutdown inhibit bit for DACB

SIC

Shutdown inhibit bit for DACC

SID

Shutdown inhibit bit for DACD

ACT

Software shutdown bit

. The Six bits inhibit the actions of the shutdown bits as shown in Table 3. When the ACT bit is 1 or the HWACT
signal is high (active), the inhibit bits act as enable bits in inverse logic terms. The ACT software shutdown bit
and HWACT (asynchronously acting hardware terminal) are logically ORed together.
This configuration allows any combination of DACs to be shut down to save power.
Table 3. Shutdown Inhibit Bits and HWACT Signal
Six

ACT

HWACT

0

0

L

Shutdown (see Note 1)

DACxSTATUS

0

0

H

Shutdown

0

1

L

Shutdown

0

1

H

Active (see Note 1)

1

0

L

Active

1

0

H

Active

1

1

L

Active

1

1

H

Active

NOTE 1: Sense of HWACT terminal and ACT bit were changed from early
versions of this specification.

The values of the input address select bits, AD and A1, and the updated DAC are listed in Table 4.
Table 4. Serial Input Decode
INPUT ADDRESS SELECT BITS

DACUPDATED

A1

AD

0

0

DACA

0

1

DACB

1

0

DACC

1

1

DACD

-!11

TEXAS
INSTRUMENTS
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3-221

TLV5621I
LOW·POWER QUADRUPLE 8-BIT DIGITAL·TO·ANALOG CONVERTER
SLAS138B - APRIL 1996 - REVISED FEBRUARY 1997

power-on reset
Power-on reset circuitry is available on the TLV5621I. The threshold to trigger a power-on reset is 1;95 V typical
(1.4 V min and 2.5 V max). For a power-on reset, all DACs are shut down. The control register bit values and
states after a power-on reset are listed in Table 5.

Table 5. Control Register Bit Values and States After POwer-On Reset
BIT

VALUE

MODE

0

Double buffer mode selected

STATE AFTER POWER-ON RESET

RNGA

1

Range x2

RNGB

1

Range x2

RNGC

1

Range x2

RNGD

1

Range x2

SIA

0

Shutdown affects DACA according to ACT state

SIB

0

Shutdown affects DACB according to ACT state

SIC

0

Shutdown affects DACC according to ACT state

SID

0

Shutdown affects DACD according to ACT state

ACT

0

DACs in shutdown state-

~TEXAS

INSTRUMENTS
3-222

POST OfFICE BOX 655303 • DALLAS. TEXAS 75265

TLV5621I
LOW-POWER QUADRUPLE a·BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B - APRIL 1996 - REVISED FEBRUARY 1997

linearity, offset, and gain error using single-end supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage
may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative Voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 5.

Output
Voltage

ov I---~:"-'---------+
Negative {
Offset

.,///
,.

DACCode

Figure 5. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage. The code is
calculated from the maximum specification for the negative offset.

equivalent inputs and outputs
INPUT CIRCUIT

OUTPUT CIRCUIT

- - . - - VDD

VDD
Input from
Decoded DAC
Register String

Vref
Input

DAC
Voltage Output

ToDAC
Resistor
String
--~-_.-~-

I
•

--'--1-

GND

ISINK
60llA
Typical
GND

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-223

TLV5621I
LOW·POWER QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTER
SLAS138B- APRIL 1996 - REVISED FEBRUARY 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage (Voo - GND) ................................................................. 7 V
Digital input voltage range ............................................. GND - 0.3 V to Voo + 0.3 V
Reference input voltage range, VID ...................................... GND - 0.3 V to Voo + 0.3 V
Operating free-air temperature range, TA ............................................. -40°C to 85°C
Storage temperature range, Tstg ................................................... -50°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions
MIN

NOM

MAX

Supply voltage, VOO (see Note 2)

2.7

3.3

5.5

High-level digital input voltage, V,H

0.8 VOO

Low-level digital input voltage, V,L
GNO

Reference voltage, Vref [AIBIClO], xl gain

UNIT

V
V

0.2VOO

V

VOO-1.5

V

Load resistance, RL

10

kn

Setup time, data input, tsu(OATA-CLK) (see Figure 6)

50

ns

Hold time, data input valid after CLK,j" th(OATA-CLK) (see Figure 6)

50

ns

100

ns

Setup time, ENt to CLK,j" tsu(EN-CLK) (see Figure 7) (see Note 3)

100

ns

Pulse duration, EN low, tw(EN) (see Figure 7) (see Note 3)

200

ns

Pulse duration, CLK high, tw(CLK) (see Figure 6) (see Note 3)

400

Setup time, CLK,j, to EN,j"tsu(CLK-EN) (see Figure 7)

CLK frequency

ns
1

Operating free-air temperature, TA

-40

85

MHz
°C

NOTES: 2. The device operates over the supply voltage range of 2.7 V to 5.5 V. Over this voltage range the device responds correctly to data
input by changing the output voltage but conversion accuracy is not specified over this extended range.
3. This is specified by design but is not production tested.

3-224

~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5621I
LOW-POWER QUADRUPLE a-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B-APRIL 1996 - REVISED FEBRUARY 1997

electrical characteristics over recommended operating free-air temperature range,
VOO 3 V to 3.6 V, Vref 1.25 V, GND 0 V, RL 10 kQ, CL 100 pF, x 1 gain output range
(unless otherwise noted)

=

=

=

PARAMETER

=

=

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Vomax

Maximum full-scale output
voltage

Vref = 1.5 V, open circuit output, x 2 gain

IIH(digital)

High-level digital input current

VI= VDD

±10

flA

IILldiaitall

Low-level digital input current

VI=OV

±10

flA

Output sink current, DACA

DAC code 0

5

flA

IO(sink)

Output sink current, DAC8,
DACC,DACD

DACcodeO

20

flA

IO(source)

Output source current

Each DAC output,

DAC code 255

VDD-100

mV

1

Input capacitance
Ci

2

rnA
15

Reference input capacitance

A, 8, C, D inputs

pF

15

VDD=3.6 V

1

1.5

rnA

VDD=5 V

1

1.5

rnA

VDD = 3.6 V, See Note 4

150

250

f!A

Supply current, all DACs shut
down

VDD = 3.6 V, See Note 4

50

100

flA

Iref

Reference input current

A, 8, C, D inputs

EL

Integral linearity error

Vref = 1.25 V,

x 2 gain, See Notes 5 and 13

IDD

Supply current

IDD(active)

Supply current, one low power
DAC active

IDD(shutdown)

ED

Differential linearity error

Vref = 1.25 V,

x 2 gain, See Notes 6 and 13

EZS

Zero-scale error

Vref = 1.25 V,

x 2 gain, See Note 7

Zero-scale error temperature
coefficient

Vref = 1.25 V,

x 2 gain, See Note 8

Vref = 1.25 V,

x 2 gain, See Note 9

Zero-scale error supply rejection
EFS

Full-scale error
Full-scale error temperature
coefficient

Power-supply sensitivity

Vref = 1.25 V,

x 2 gain, See Note 10

See Notes 11 and 12

Feedback resistor network
resistance
NOTES:

f!A

±1

LS8

±0.9

LS8

30

mV
flV/o C

10
2

Full-scale error supply rejection
PSRR

±0.1
0

±10

mVN
±60

mV

±25

flV/o C

2

mVN

0.5

mVN

168

kg

4. This IS measured with no load (open CircUit output), Vref = 1.25 V, range = x 2.
5. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects
of zero code and full-scale errors).
6. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LS8 amplitude change of any two adjacent codes.
Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
7. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
8. Zero-scale error temperature coefficient is given by: ZSETC = [ZSE(Tmax) - ZSE(T min)]lVref x 106/(T max - T min).
9. Full-scale error is the deviation from the ideal full-scale output (Vref - 1 LS8) with an output load of 10 lin.
10. Full-scale temperature coefficient is given by: FSETC = [FSE(Tmax) - FSE (T min)]Nref x 10S/(Tmax - T min).
11. Zero-scale error rejection ratio (ZSE-RR) is measured by varying the VDD voltage from 4.5 V to 5.5 V dc and measuring the effect
of this signal on the zero-code output voltage.
12. Full-scale error rejection ratio (FSE-RR) it! measured by varlng the VDD voltage from 3 V to 3.S V dc and measuring the effect of
this signal on the full-scale output voltage.
13. Linearity is only specified for DAC codes 1 through 255.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-225

TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B - APRIL 1996 - REVISED FEBRUARY 1997

operating characteri.stics over recommended operating free-air temperature range,
VOO 3 V to 3.6 V, Vref 1.25 V, GND 0 V, RL 10 kn, CL 100 pF, x 1 gain output range
(unless otherwise noted)

=

=

=

=

PARAMETER

=

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output slew rate, rising (DACA)

0.8

Output slew rate, falling (DACA)

0.5

V/JlS

1

V/IlS

Output slew rate (DACB, DACC, DACD)

V/IlS

Output settling time, rising (DACA)

To 1/2 LSB,

VDD =3V

20

Output settling time, falling (DACA)

To 1/2 LSB,

VDD= 3 V

75

Il s
IlS

Output settling time, rising (DACB, DACC,
DACD)

To 1/2 LSB,

VDD= 3 V

10

IlS

Output settling time, falling (DACB, DACC,
DACD)

To 1/2 LSB,

VDD= 3 V

75

JlS

Output settling time, HWACT or ACTt to
output volts (DACA) (see Note 14)

To 1/2 LSB,

VDD = 3 V

40

120t

JlS

Output settling time, HWACT or ACTt to
output volts (DACB, DACC, DACD)
(see Note 14)

To 1/2 LSB,

VDD=3V

25

75t

Il s

Large-signal bandwidth

Measured at -3 dB point

100

kHz

Digital crosstalk

CLK = 1-MHz square wave measured at DACA-DACD

-50

dB

Reference feedthrough

A, B, C, D inputs, See Note 15

-60

dB

Channel-to-channel isolation

A, B, C, D inputs, See Note 16

-60

dB

Channel-to-channel isolation when in
shutdown

A, B, C, D inputs

-40

dB

Reference bandwidth (DACA)

See Note 17

20

kHz

Reference bandwidth (DACB, DACC, DACD)

See Note 17

100

kHz

. .

..

t This IS specified by charactenzatlOn but IS not production tested .
NOTES: 14. The ACT bit is latched on EN.J..
15. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input = 1 V dc + 1 Vpp at 10kHz.
16. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex
with Vref input = 1 V dc + 1 Vpp at 10kHz.
17. Reference bandwidth is the -3 dB bandwidth with an ideal input at Vref = 1.25 V dc + 2 Vpp and with a digital input code of full-scale
(range set to x 1 and VDD = 5 V).

3-226

"'TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLV5621I
LOW·POWER QUADRUPLE 8·BIT DIGITAL·TO·ANALOG CONVERTER
SLAS138B - APRIL 1996 - REVISED FEBRUARY 1997

PARAMETER MEASUREMENT INFORMATION
14

.1

1

1

ClK

tw(ClK)
50%

iIII:4f----~~f- th(DATA-ClK)

tsu(DATA-ClK)
DATA

i
*,..-----..x~----

--.I

j4-

Figure 6. Timing of DATA Relative to ClK

~~

DATA _________

__- - - - _

Figure 7. Timing of ClK Relative to EN
TlV5621
DACA 1---41------,
DACB
DACC
10 krl
DACD

;:::r: Cl =100 pF

Figure 8. Slewing Settling Time and linearity Measurements

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-227

TLV5621I
LOW-POWER QUADRUPLE 8-81T DIGITAL-TO-ANALOG CONVERTER
SLAS138B - APRIL 1996 - REVISED FEBRUARY 1997

TYPICAL CHARACTERISTICS
NEGATIVE FALL TIME AND SETTLING TIME

POSITIVE RISE TIME AND SETTLING TIME
3

3

2.5

2.5

2

>

.

I
I

I

1.5

CI

~

~

"S
Co
"S

:f

0.5

0

f
..;I

I

-?

0
-0.5
-1

o

2

4

6

8

10

12

>

.

-

CI

~
~

1

L

I

16

18

\

"S

VOO=3V
TA=25'C
Code 00 to
FFHex
Range=x2
Vref = 1.25 V
(see Notes
A and B)
14

1.5

t

0

\

0.5

-?

0
-0.5

-1
20

o

2

4

6

~s, positive slew rate = 0.96
settling time = 4.5 ~s.
B. For DACB, DACC, and DACD

V/~s,

settling time = 8.5

1.4

I

>

.
I

I

CI

2.2

"S

t

2

0

0
C

1.8

0
C

I

1.6

Q

I

VOO=3V
Vref = 1.5 V
Range =x2
(see Note A)

1.4
1.2

1

1.2

~
~

2.4

-?

-?

I I I
o

10

20

30 40 50 60 70 80
RL - Load Resistance - kQ

90 100

0.8
0.6
VOO=3V
Vref = 1.5 V
Range = x1
(see Note A)

0.4
0.2

o
o

-

1 1 'I
10

20

30

40

50

60

70

RL - Load Resistance - kQ

NOTE A: For DACB, DACC, and DACD

NOTE A: For DACB, DACC, and DACD

Figure 11

Figure 1.2

~TEXAS

3-228

~s.

1.6

2.6

Q

20

vs

2.8

~

18

LOAD RESISTANCE

3

0

16

DAC OUTPUT VOLTAGE

LOAD RESISTANCE

"S

14

Figure 10

vs

~

12

B, For DACB, DACC, and DACD

DAC OUTPUT VOLTAGE

~

10

NOTES: A. Fall time = 4.25!!S, negative slew rate = 0.46 V/~s,

Figure 9

CI

8

t- Tlme-!!S

NOTES: A. Rise time = 2.05

..

-

\

I

t- Tlme-!!S

>

VOO=3V
TA=25'C
Code FFto
00 Hex
Range = x2
Vref = 1.25 V (see Notes
A and B)

2

I

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

80

90

100

TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLASI38B-APRIL 1996 - REVISED FEBRUARY 1997

TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
1.2
Range=x2
Input Code = 255
VDD=3 V
Vref = 1.25 V

1.15
CC

E

1.~

:,

I

C

~

1.05

:::I

...

()

.2:-

-....... .......

....-

CI.
CI.

en:::I

0.95

I

Q

E

0.9
0.85
0.8
-50

o

50

100

TA - Free-Air Temperature - °C

Figure 13

APPLICATION INFORMATION
TLV5621
DACA 1---'---;1+/
DACB
DACC
R
DACD

Vo

NOTE A: Resistor R ;" to k.Q

Figure 14. Output Buffering Scheme.

'~TEXAS

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-229

3-230

TLV5628C, TLV56281
OCTAL 8·BIT DIGITAL·TO·ANALOG CONVERTERS
•
•
•
•
•

Eight 8-Bit Voltage Output DACs
3-V Single Supply Operation
Serial Interface
High-Impedance Reference Inputs
Programmable for 1 or 2 Times Output
Range

•
•
•
•

Simultaneous Update Facility
Internal Power-On Reset
Low Power Consumption
Half-Buffered Output

ow OR N PACKAGE
(TOP VIEW)
DACB

DACC

DACA

DACD

GND

REF1

DATA

LDAC

ClK

lOAD

VDD
DACE

REF2

DACF

DACG

DACH

applications
•
•
•
•
•
•

Programmable Voltage Sources
Digitally Controlled Amplifiers/Attenuators
Mobile Communications
Automatic Test Equipment
Process Monitoring and Control
Signal Synthesis

description
The TLV5628C and TLV56281 are octal 8-bit voltage output digital-to-analog converters (DACs) with buffered
reference inputs (high impedance). The DACs produce an output voltage that varies between one or two times
the reference voltages and GND, and the DACs are monotonic. The device is simple to use, running from a
single supply of 3 to 3.6 V. A power-on reset function is incorporated to ensure repeatable start-up conditions.
Digital control of the TLV5628C and TLV56281 is over a simple three-wire serial bus that is CMOS compatible
and easily interfaced to all popular microprocessor and microcontroller devices. The 12-bit command word
comprises eight bits of data, three DAC select bits, and a range bit, the latter allowing selection between the
times 1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values
to be written to the device, then all DAC outputs are updated simultaneously through control of LDAC. The digital
inputs feature Schmitt triggers for high noise immunity.
The 16-terminal small-outline DW package allows digital control of analog functions in space-critical
applications. The TLV5628C is characterized for operation from O°C to 70°C. The TLV56281 is characterized
for operation from -40°C to 85°C. The TLV5628C and TLV56281 do not require external trimming.
AVAILABLE OPTIONS
PACKAGE
TA

SMALL OUTLINE
(OW)

PLASTICOIP
(N)

O°C to 70°C

TLV5628CDW

TLV5628CN

-40°C to 85°C

TLV56281DW

TLV56281N

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

Copyright © 1997. Texas Instruments Incorporated

3-231

TLV5628C,TLV56281
OCTAL B-BITDIGITAl-TO-ANALOG CONVERTERS
SLAS1 088 - JANUARY 1995 - REVISED APRIL 1997

functional block diagram

DACA

••
•
15 DACD

DACE

•
••
10 DACH

elK 5
Serial
Interface

DATA 4
lOAD 12

Power-On
Reset

13
lDAC

Terminal Functions
TERMINAL
NAME

NO.

1/0

DESCRIPTION

ClK

5

I

Serial interface clock. The input digital data is shifted into the serial interface register on the falling edge of the clock
applied to the ClK terminal.
DAC A analog output

DACA

2

DACe

1

DACC

16

DACD

15

0
0
0
0

DACE

7

0

DAC E analog output

DACF

8

DAC F analog output

DACG

9

0
0

DACH

10

DAC H analog output

DATA

4

0
I

GND

3

I

Ground return and reference terminal

LDAC

13

I

load DAC. When this signal is high, no DAC output updates occur when the input digital data is read into the serial
interface. The DAC outputs are only updated when lDAC is taken from high to low.

LOAD

12

I

Serial Interface load control. When the lDAC terminal is low, the falling edge of the lOAD signal latches the digital
data into the output latch and immediately produces the analog voltage at the DAC output terminal.

REFI

14

I

Reference voltage input to DAC AI el ci D. This voltage defines the output analog range.

REF2

11

I

Reference voltage input to DAC ElF I G I H. This voltage defines the analog output range.

6

I

Positive supply voltage

VDD

DAC e analog output
DAC C analog output
DAC D analog output

DAC G analog output
Serial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially.
Each data bit is clocked into the register on the falling edge of the clock signal.

~.TEXAS

~232

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5628C, TLV56281
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS10BB- JANUARY 1995 - REVISED APRIL 1997

detailed description
The TlV5620 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with
256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected
to GND and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use
of the resistor strings. Linearity depends upon the matching of the resistor segments and upon the performance
of the output buffer. Since the inputs are buffered, the DACs always presents a high-impedance load to the
reference source.
Each DAC output is buffered by a configurable-gain output amplifier, that can be programmed to times 1 or times
2 gain.
On power up, the DACs are reset to CODE O.
Each output voltage is given by:
V dDACAIBICiD) = REF x

C~~E

x (1

+ RNG bit value)

where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word.

Table 1. Ideal-Output Transfer
07

06

05

04

03

02

01

DO

a
a

a
a

a
a

a
a

a
a

a
a

a
a

a

GND

1

(1/256) x REF (1+RNG)

1

1

1

··a
··
1

1

·· ·· ··
a a a
·· ·· ··
1

1

1

·· ·· ··
a
·· ·· ··
1

1

1

1

0

0

1

1

··
··

OUTPUT VOLTAGE

··
··

1

(127/256) x REF (1+RNG)

0

(128/256) x REF (1+RNG)

1

(255/256) x REF (1 +RNG)

data interface
With lOAD high, data is clocked into the DATA terminal on each falling edge of ClK. Once all data bits have
been clocked in, lOAD is pulsed low to transfer the data from the serial input register to the selected DAC as
shown in Figure 1. When lDAC is low, the selected DAC output voltage is updated when lOAD goes low. When
lDAC is high during serial programming, the new value is stored within the device and can be transferred to
the DAC output at a later time by pulsing lDAC low as shown in Figure 2. Data is entered MSB first. Data
transfers using two a-clock-cycle periods are shown in Figures 3 and 4.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-233

TLV5628C, TLV56281
OCTAL 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS1 088 - JANUARY 1995 - REVISED APRIL 1997

CLK

1

i+-

I -.:
I
DATA

I

tsu(DATA-CLK)

tsu(LOAD-CLK) --t----.--·~I

14- tv(DATA-CLK)

A1

LOAD

Figure 1. LOAD·Controlied Update (LDAC = Low)
CLK

DATA

D1

DO

tsu(LOAD-LDAC) ~

\..{'...-T-l-

LOAD

tw(LDAC)
LDAC

--l4--tt

VI

DAC Update

Figure 2. LDAC·Controlied Update

~TEXAS

3-234

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ClK

ClKlow

-'

x.r

lOAD
lDAC

------------------------------------------------~------------------------------Figure 3. Load-Controlled Update Using 8-Bit Serial Word (LDAC

ClK
C'3

~
o_~

~ Z ~.
men
~;Jd
~~~
';~fii

!~

,

=Low)

ClKlow

DATA~

V--

lOAD
lDAC

0
0

Figure 4. LDAC-Controlled Update Using 8-Bit Serial Word

:;!

x.r

.

r-

eo
a::J

=i

c
is

In

~
(J)

~

5l
til
I
'-

>
z
c
>
:IJ
-<
<0
<0

'"

I
:IJ

m

<

enm

.:..
0

.

l>
Z
l>-I

5!<

"en
0)
O~
0 0
Z_
<-I

!;a!<
-len

<0

2JN

0

'"'"

r-

;E

>
-a

~

:;!

r

!!l

rnO)

cn2i!

TLV5628C, TLV56281
OCTAL 8·BITDIGITAL·TO·ANALOG CONVERTERS
SLAS108B - JANUARY 1995 - REVISED APRIL 1997

data interface (continued)
Table 2 lists the A2, A1, and AO bits and the selection of the updated DACs. The RNG bit controls the DAC output
range. When RNG = low, the output range is between the applied reference voltage and GND, and when
RNG = high, the range is between twice the applied reference voltage and GND.
Table 2. Serial Input Decode
A2

A1

AD

DACUPDATED

0

0

0

0

0

1

0

DACA
DACB
DACC
DACD
DACE
DACF
DACG
DACH

0

1

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

linearity, offset, and gain error

When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset voltage, the output voltage changes on the first code change. With a negative offset the output
voltage may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier, therefore, attempts to drive the output to a negative voltage. However, because the most
negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 5.

Output
Voltage

DV
Negative {
Offset

~--~~~-------------------.
DACCode

Figure 5. Effect of Negative Offset (Single Supply)

The offset error, not the linearity error, produces the breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below ground.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in som~ way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output Voltage. The code is
calculated from the maximum specification for the negative offset.

~TEXAS

3-236

INSTRUMENTS
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TLV5628C, TLV56281
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS1 08B - JANUARY 1995 - REVISED APRIL 1997

equivalent inputs and outputs
INPUT CIRCUIT

OUTPUT CIRCUIT
VDD

VDD
Input from
Decoded DAC
Register String

Vref
Input

DAC
Voltage Output

ToDAC
Resistor
String

-41>------.-....-

ISINK
60~A

Typical

GND

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage (Voo - GND) ................................................................. 7 V
Digital input voltage range, V,O ......................................... GND - 0.3 V to Voo + 0.3 V
Reference input voltage range .......................................... GND - 0.3 V to Voo + 0.3 V
Operating free-air temperature range, TA: TLV5628e .................................... ooe to 70°C
TLV56281 ................................... -40°C to 85°C
Storage temperature range, T81g ...••.............................................. -50°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 230°C

t Stre.sses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions
Supply voltage, VDD
High-level input voltage, V,H

MIN

NOM

MAX

UNIT

2.7

3.3

5.25

V
V

0.8 VDD
0.8

low-level input voltage, V,l
Reference voltage, Vref [AIBICIDIEIFIGIH1, X1 gain

VOO-1.5

V
V

load resistance, Rl

10

kQ

Setup time, data input, tsu(OATA-ClK) (see Figures 1 and 2)

50

ns

Valid time, data input valid after ClK"', tv(DATA-ClK) (see Figures 1 and 2)

50

ns

Setup time, ClK eleventh falling edge to lOAD, tsu(ClK-lOAD) (see Figure 1)

50

ns

Setup time, LOAOi to ClK"', tsu(lOAD-ClK) (see Figure 1)

50

ns

Pulse duration, lOAD, tw(lOAD) (see Figure 1)

250

ns

Pulse duration, LDAC, tw(lDAC) (see Figure 2)

250

ns

Setup time, LOADi to LDAC"', tsu(lOAD-lDAC) (see Figure 2)

0

Operating free-air temperature, TA

ns

1

ClK frequency

ITlV5628C
ITlV56281

MHz

0

70

'C

-40

85

'C

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-237

TLV5628C, TLV56281
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108B-JANUARY 1995 - REVISED APRIL 1997

electrical characteristics over recommended operating free-air temperature·range,
Voo = 3 V to 3.6 V, Vref = 2 V, x 1 gain output range (unless otherwise noted)
MAX

UNIT

IIH

High-level input current

VI =VDD

±10

~

IlL

Low-level input current

VI=OV

±10

~

IO(sink)

Output sink current

IO(source}

Output source current

PARAMETER

TEST CONDITIONS

' Each DAC output

MIN

20

~A

1

mA

I Input capacitance
I Reference input capacitance

Ci

15

IDD

Supply current

VDD=3.3 V

Reference input current

VDD =3.3 V,

Vref = 1.5 V

EL

Linearity error (end point corrected)

Vrel = 1.25 V,

x 2 gain, See Note 1

ED,

Differential linearity error

Vref = 1.25 V,

x 2 gain, See Note 2

EZS

Zero-scale error

Vrel = 1.25 V,

x 2 gain, See Note 3

Zero-scale error temperature coefficient

Vref = 1.25 V,

x 2 gain, See Note 4

PSRR

pF

15

Iref

EFS

TYP

Full-scale error

Vrel = 1.25 V,

x 2 gain, See Note 5

Full-scale error temperature coefficient

Vref = 1.25 V,

x 2 gain, See Note 6

Power supply sensitivity

See Notes 7 and 8

0

4

mA

±10
±1

~
LSB

±0.9

LSB

30

mV
~V/oC

10
±60

mV

±25

~V/oC

0.5

mVN

NOTES: 1. Integral nonllneanty (INL) IS the maximum deViation of the output from the line between zero-scale and full scale (excluding the
effects of zero code and lull-scale errors).
2. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change 01 any two adjacent codes.
Monotonic means the output voltage changes in the same direction (or remains constant) as a Change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale error temperature coefficient is given by: ZSETC = [ZSE(T max) - ZSE(Tmin}]Nref x 106/(Tmax - Tmin}·
5. Full-scale error isjhe deviation from the ideal full-scale output (Vref - 1 LSB) with an output load of 10 kQ.
6. Full-scale error temperature coefficient is given by: FSETC = [FSE(T max) - FSE (Tmin)]Nref x 106/(T max - Tmin).
7. Zero-scale error rejection ratio (ZSE-RR) is measured by varying the VDD voltage from 4.5 V to 5.5 V dc and measuring the effect
of this signal on the zero-code output voltage.
8. Full-scale error rejection ratio (FSE-RR) is measured by varing the VDD voltage from 3 V to 3.6 V dc and measuring the effect of
this signal on the full-scale output voltage.

operating characteristics over recommended operating free-air temperature range,
Voo 3 V to 3.6 V, Vref 2 V, x 1 gain output range (unless otherwise noted)

=

=

TEST CONDITIONS

Output slew rate

CL = 100 pF,

RL = 10 kQ

Output settling time

To ±0.5 LSB,

CL = 100 pF,

Large-signal bandwidth

MIN

TYP

1
RL = 10 kO, See Note 9

MAX

UNIT
V/~s

10

I1S

Measured at ~3 dB pOint

100

kHz

Digital crosstalk

CLK = I-MHz square wave measured at DACA-DACH

-50

dB

Reference feedthrough

See Note 10

-60

dB

Channel-to-channel isolation

See Note 11

-60

dB

Reference input bandwidth

See Note 12

100

kHz

NOTES: 9. Settling time IS the time between a LOAD failing edge and the DAC output reaching full-scale voltage within ±0.5 LSB starting from
an initial output voltage equal to zero.
.
10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input = 1 V dc + 1 Vpp at 1.0 kHz.
11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex
with Vref input = 1 V dc + 1 Vpp at 10 kHz.
12. Reference bandwidth is a -3 dB bandwidth with an input at Vref = 1.25 V dc + 2 Vpp and with a full-scale digital input code.

~TEXAS

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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5628C, TLV56281
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108B-JANUARY 1995 - REVISED APRIL 1997

PARAMETER MEASUREMENT INFORMATION
TLV5628
DACA I-_~'----,

DAce

10 kQ
DACH

Figure 6. Slew, Settling Time, and Linearity Measurements

TYPICAL CHARACTERISTICS
POSITIVE RISE TIME AND SETTLING TIME

>

.'"

3

3

2.5

2.5

2
1.5

I

;g

'S
a.
'S

0

~I

0.5

I

~

~

0

~

-0.5
-1

o

.'"
I

4

6

8

10

12

-

1.5

.l!

;g

'Sa.
'S

VDD=3V
TA=25°C
Code 00 to
FFHex
Range =x2
Vref = 1.25 V
(see Note A)

0

\

14

16

18

\

'0.5

\

I

~

0

"

-0.5

I I I
2

VDD=3V
TA=25°C
CodeFFto
00 Hex
Range = x2
Vref = 1.25 V (see Note A)

2

>

I

I

.l!

NEGATIVE FALL TIME AND SETTLING TIME

-1

20

o

2

Time-~s

4

6

8

10

12

14

16

18

20

Time-~s

NOTE A: Rise time = 2.05 ~, positive slew rate = 0.96
settling time = 4.5 ~S.

V/~s,

NOTE A. Fall time = 4.25 ~s, negative slew rate
settling time = 8.5 ~s.

Figure 7

=0.46 V/~s,

Figure 8

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-239

TLV5628C, TLV56281
OCTAL 8·BIT DIGITAL·TO·ANALOG CONVERTERS
SLAS1 08B - JANUARY 1995 - REVISED APRIL 1997

TYPICAL CHARACTERISTICS
DAC OUTPUT VOLTAGE

DAC OUTPUT VOLTAGE

vs

vs

OUTPUT LOAD

OUTPUT LOAD

3

1.6

2.8

>

I

2.6

v
I

CI)

I

CI)

!'"
~

'S

!0
0
0

"'I"
-?

1.4

>

1.2

!'"

2.4

~

2.2

'S

!0

2

0.8

0

1.8

"'0I"
-?

1.6
VOO =3 V,
Vref = 1.5 V,
Range = 2x

1.4

0.6
0.4

1

o

10

20

30 40 50 60 70 80
RL - Output Load - kQ

VOO=3 V,
Vref = 1.5 V,
Range = 1x

0.2

1.2

1 1 1

o
o

90 100

10

20

Figure 9

30 40 50 60 70 80
RL - Output Load - kQ

Figure 10
SUPPLY CURRENT

vs
TEMPERATURE
1.2
Range = x2
Input Code = 255
VOO =3V
Vref 1.25 V

1.15

"'EI"
"E
~

1.1
1.05

:J

U

i

:J

If)

0.95

---

I

0

E

0.9

r--......
~

0.85
0.8
-50

o

50

" t - Temperature - °C

Figure 11

~TEXAS

3-240

-

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

100

90 100

TLV5628C, TLV56281
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108B- JANUARY 1995 - REVISED APRIL 1997

APPLICATION INFORMATION
TLV5628

DACA
DAce

I---e---I

Vo

DACH
t

Resistor R <: 10 kn

Figure 12. Output Buffering Scheme

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-241

3-242

TMS57014A
DUAL AUDIO DIGITAl-TO-ANAlOG CONVERTER

•
•
•
•
•
•
•
•
•

•
•
•
•

Single 5-V Power Supply
Sample Rates (Fs) up to 48 kHz
18-Bit Resolution
Pulse-Width-Modulation (PWM) Output
De-emphasis Filter for Sample Rates of
32, 37.8, 44.1, and 48 kHz
Mute With Zero-Data-Detect Flags
Digital Attenuation to -60 dB
Total Harmonic Distortion of 0.004%
Maximum
Total-Channel Dynamic Range of 96 dB
Minimum
Serial-Port Interface
Differential Architecture
CMOS Technology
2s-Complement Data Format

OWB PACKAGE
(TOP VIEW)

INIT
TEST
ATT
SHIFT
LATCH
256FSO
TEST
DGND
TEST
BCK
DATA
LRCK
MUTEL
MUTER

DVOO
L1
AVOOL
L2
AGNDL
XGND
XIN
XOUT
XVOO
AGNDR
R2
AVOOR
R1
DVOD

description

The TMS57014A is a stereo oversampled-sigma-delta digital-to-analog converter (DAC) designed for use in
systems such as compact disks, digital audio tapes, multimedia, and video cassette recorders. The device
provides high-resolution signal conversion. This device consists of two identical synchronous conversion paths
for left and right audio channels. Other overhead functions provide on-chip timing and control.
Additional features include muting, attenuation, de-emphasis, and zero-data detection. Control words (16-bit)
from a host controller or processor implement these functions.
The TMS57014A is characterized for operation from O°C to 70°C.
AVAILABLE OPTIONt
PACKAGE
TA

SMALL OUTLINE
(OWB)

OOG to 700G

TMS57014ADWBLE

t Available on tape and reel (LE) only.

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields;
however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these
high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed
in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either
VCC or ground.

=~:to~~1: sl~!:r:c:~sl~~~~:~:~:: !~::~~~~~n!a:s

standard warranty. Production processing does not necessarily include
testing of a" parameters.

~TEXAS

INSTRUMENTS
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Copyright © 1995, Texas Instruments Incorporated

3-243

TMS57014A
DUAL AUDIO

DIGITAL·TO~ANALOG

CONVERTER

SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995

functional block diagram
INIT

XIN

XOUT 256FSO

ATT
SHIFT
LATCH

Interpolation
Filter

DATA 11
BCi< 10
LRCK 12

Serial
Data
Interface

Zero-Data
Detect
Zero-Data
Detect
Interpolation
Filter

De-emphasis
Filter
Left Channel

Right Channel
De-emphasis
Filter

~lEXAS

3-244

L1
L2

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

R1
R2

TMS57014A
DUAL AUDIO DIGITAL·lO·ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995

Terminal Functions
TERMINAL
NAME
ATT

NO.

1/0

DESCRIPTION

3

I

Serial control data. ATT is a 16-bit word configured as LSB first (see Tables 2, 3, and 4).

AVDDL

26

I

Analog power supply (left channel)

AVDDR

17

I

Analog power suppiy (right channel)

AGNDL

24

I

Analog ground (left channel)

AGNDR

19

I

Analog ground (right channel)

BCK

10

I

Bit clock input. BCK clocks serial audio data into the device.

DATA

11

I

Audio data input. DATA can be configured as 16 or 18 bits with MSB or LSB first. DATA is 2s complement.

DVDD

15,28

I

Digital supply

DGND

8

I

Digital ground

INIT

1

I

Reset. When INIT is brought low, the device is reset. The device is activated on the rising edge of INIT. The LRCK
signal must be applied to the device for a reset to occur.

LATCH

5

I

Serial-control data latch. Control data loads into the internal registers when LATCH is brought low.

LRCK

12

I

Leftlright clock. LRCK signifies whether the serial data is associated with the left-channel DAC (when high) or the
right-channel DAC (when low).

MUTEL

13

0

Left-channel mute flag active. When the left channel is mute or the data through the channel remains at zero for the
system-register selected. time, MUTEL is brought low.

MUTER

14

0

Right-channel mute flag active. When the right channel is mute or the data through the channel remains at zero for
the system-register selected time, MUTER is brought low.

L1

27

0

Left PWM output 1

L2

25

R1

16

Right PWM output 1

R2

18

0
0
0

SHIFT

4

I

Shift clock. SHIFT clocks the control data into the internal registers.

TEST

All TEST inputs should be tied low.

2,7,9

I

XIN

22

I

XOUT

21

0

XVDD

20

I

XGND

23

I

6

0

256FSO

Left PWM output 2

Right PWM output 2

Master clock in. XIN derives all the key logic signals of the device. XIN runs at 512 Fs , where Fs is the sample rate.
Master clock out
Power supply for clock section
Ground for clock section
System clock out: 256FSO reflects the master clock input divided by 2. The rate is 256Fs, where Fs is the sample
rate.

detailed description
The TMS57014A incorporates an interpolation impUlse-response filter (FIR) and oversampled modulator.
The pulse-width modulation (PWM) digital output feeds into an external low-pass filter to recover the analog
audio signal.
Two control registers configure the device, the attenuation register controls the attenuation range and the
system register controls additional functions (see register set section).

reset/initialization
When INIT is brought low, an internal reset signal becomes active approximately 120 cycles of the sampling
frequency (Fs) after the falling edge of INIT. Under this condition, all internal circuits are initialized and the PWM
output is held at zero data (50% duty cycle). When INIT is brought high, the internal reset signal goes inactive
for a maximum of five LRCK periods after the rising edge of INIT. At this point, internal clocks are synchronous
with LRCK and the PWM output is valid (see Figure 1). The LRCK Signal must be applied for proper initialization.

~TEXAS

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TMS57014A
DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995

reset/initialization (continued)

/4-- 5 periods max ---.I

~ 120 Cycles of Fs ~

INIT
Internal
Reset

----~~I-----------4I------------~1
I

I

:
nI

~------------------~I

LRCK

Figure 1. Reset Timing Relationships
timing and control
The timing and control circuit generates and distributes necessary clocks throughout this design. XIN is the
external master clock input. The sample rate of the data paths is set as LRCK = XIN/512. With a fixed
oversampling ratio of 32x and each PWM output value requiring 16 XIN cycles, the effect of changing XIN is
shown in Table 1.
The DAC can be operated at any conversion rate between 48 kHz and 32 kHz by choosing the appropriate
.master-clock frequency. Some of the functions of the converter, such as the de-emphasis filter, operate only
at the frequencies in Table 1.

Table 1. Master Clock to Sample Rate Comparison
XIN
(MHz)

256FSO
(MHz)

LRCK
(kHz)
48.0

24.5760

12.2880

22.5792

11.2896

44.1

19.3536

9.6768

37.8

16.3840

8.1920

32.0

digital-audio data interface
The conversion cycle is synchronized to the rising edge of LRCK, and the data must meet the setup
requirements specified in the timing requirements table. The input data is 16 or 18 bits with the MSB or LSB
first as selected in the system register. The BCK frequency must be equal to or greater than 32 Fs for 16·bit data
or 36 Fs for 18·bit data where Fs is the sample rate. Figure 2 illustrates the input timing.

Figure 2. Audio-Data Input Timing

~TEXAS

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS57014A
DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995

serial-control interface
This device uses the least-significant-bit-first format. Therefore, for a 16-bit word, 015 is the most significant
bit and 00 is the least significant bit. Unless otherwise specified, all values are in 2s-complement format.

serial-control-data input
The 16-bit control-data input implements the device-control functions. The TMS57014A has two registers for
this data: the system register and the attenuation register. The system register contains most of the system
configuration information, and the attenuation register controls audio output level, de-emphasis, and mute.
Figure 3 illustrates the input timing for ATT, SHIFT, and LATCH. The data loads internally on the falling edge
of LATCH. The shift clock should be high for the LATCH setup time before LATCH goes low.
SHIFT

ATT

6

17

8

9

110 111 12 113 114 115 1

LSB

MSB

Figure 3. Control-Data-Input Timing

mute
When mute is activated, the output PWM becomes zero data (50% duty cycle). The two mute flags, MUTEL
and MUTER, are independently set low based on the data in the respective channel being zero. This function
becomes active under the following conditions:
1.

When the zero-data detector detects that the input data has been zero for 2500 cycles of Fs or 12500
cycles of Fs (as selected in the control registers), output is 50% duty cycle.

2.

When the MUTE register value is set high by means of the serial-control data.

3.

When INIT is active (low), output is 50% duty cycle.

zero-data detect
After the input data remains zero for 2500 or 12500 cycles of Fs as set by the system register (04,05), the
channel-mute flag becomes active. Zero-data detection is available for both channels independently, so the two
outputs (MUTER and MUTEL) indicate that zero data has been detected on the respective channel. The
zero-detect register value in the serial-control data selects the detection period. The mute flag returns high
immediately when nonzero input data is received.

de-emphasis filter
Four sets of de-emphasis-filter coefficients support four sampling rates (Fs): 32, 37.8, 44.1, and 48 kHz. Internal
register values select the filter coefficients. The internal register values enable or disable the filter. Figure 4
illustrates the de-emphasis characteristics.
Many audio sources have been recorded with pre-emphasis characteristics that are the inverse of the
de-emphasis characteristic~ shown in Figure 4. This device provides reconstruction of the original frequency
response.

~TEXAS

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TMS57014A
DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995

de-emphasis filter (continued)
10
III
'a
I

3:c

o 1-----..,..__

i

-10

De-emphasis

3.18

10.6

(50~s)

(15~)

Frequency - kHz

Figure 4. De-emphasis Characteristics
digital attenuation
A value selected in the internal attenuation register determines the attenuation of the digital-audio-data input.
The attenuation value is 11 bits long with a valid range of hex values from 400h to OOOh. A data value of 001 h
corresponds to an attenuation value of -60 dB and a data value of 400h corresponds to 0 dB. The attenuation
function is nonlinear (see equation 1). Figure 5 illustrates the attenuation function in dB. The default attenuation
value is 400h.
Attenuation

= 20

log (attenuation data)
1024

-r-- -- -......

0

-10

III

'a

(1)

'\

-20

1\

I

c
0

;::I

-30

\

c

~

-.40

-50

-60
1024 896

768

640

512

384

256

128

0

Attenuation Data (decimal values)

Figure 5. Digital Attenuation Characteristics

~TEXAS

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75255

TMS57014A
DUAL AUDIO DIGITAL·TO·ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995

register set
Table 2 contains the register-set selection. Tables 3 and 4 list the bit functions.
Table 2. Register-Set Selection
BITS

DESCRIPTION

15

14

0

0

Attenuation register

0

1

System register

1

x

Invalid conditiont

t Sit 15 should always be set to 0 when writing
data for proper operation.

Table 3. Attenuation-Register Bit Functions
BITS*

13

1'1

FUNCTION

10-0

0

-

-

-

De-emphasis off

1

-

-

-

De-emphasis on

-

-

-

-

-

*

12

-

0

-

-

Channel mute off

1

-

-

Channel mute on

-

0

-

-

0

Digital attenuation, mute

-

...

-

lFF
200

Digital attenuation, -6.02 dS§

-

201

Digital attenuation, -6.00 dS§

-

3FF

Digital attenuation, -0.01 dS§

-

400

Digital attenuation, 0.00 dS§

-

-

Sit 11 must be low

1

Digital attenuation, -60.2 dS§

2

Digital attenuation, -54.2 dS§

3

Digital attenuation, -50.7 dS§

Digital attenuation, -6.04 dS§

...

Default value =0400h
§ The attenuation values shown are typical values. Refer to the digital
attenuation section for a description of the attenuation function.

~TEXAS

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TMS57014A
DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995

Table 4. System·Register Bit Functions
BITSt
13

12

11-6

5

0

-

-

-

1

-

-

-

-

-

-

-

-

-

0

-

1

-

-

0

-

-

0

-

1

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

4

0

-

3-2

-

-

-

FUNCTION

1

0

-

-

-

-

18-bit, audio data

-

-

Bits 11-6 must be low

-

-

Zero data detect period (2500 cycles of Fs)

-

Bit 4 must be low

-

MSB first, audio data
LSB first, audio data
16-bit, audio data

Zero data detect period (12500 cycles of Fs)

0

-

-

De-emphasis -44.1 kHz

-

1

-

De-emphasis -48.0 kHz

-

2

-

-

De-emphasis -37.8 kHz

LRCK and PWM are not synchronized

1

-

-

0

Bit 0 must be low

-

-

-

-

3

-

0

De-emphasis -32.0 kHz

LRCK and PWM synchronized

t Default value = OOOOh

interpolation filter
The interpolation filter used prior to the DAC increases the digital-data rate from the LRCK speed to the
oversampled rate by interpolating with a ratio of 1:32. The oversampling modulator receives the output of this
filter with de-emphasis as an option.

DAC modulator
The DAC is a third-order modulator with 32 times oversampling. The DAC provides high-resolution, low-noise
performance using a 15-value PWM output as shown in Figure 6.
APB(max}~
Quantization Noise Power With Noise Shaping

o
0.2

0.3

0.4

0.5

Normalized Analog-Output Frequency (fOfFs:!:>
:!:fO is the output frequency at the low-pass filter output (Va) shown in Figure 7.
§ fS is the highest frequency of interest within the baseband.
~ APB(max) is the passband maximum amplitude.

Figure 6. Oversampling Noise Power With and Without Noise Shaping

~TEXAS

INSTRUMENTS
3-250

POST OFFICE BOX 655303 • OALLAS, TEXAS 75265

TMS57014A
DUAL AUDIO DIGITAL-lO-ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995

PWM output (L2-L 1 and R2-R1)
The L2-L 1 and the R2-R1 output pairs are PWM signals with the L2-L 1 differential pulse duration determining
the left-channel analog voltage and the R2-R1 differential pulse duration determining the right-channel analog
voltage.
Each DAC left and right output consists of 15 levels of PWM and provides a differential signal as the input to
two external differential amplifiers configured as a low-pass filter to produce the left and right audio outputs (see
Figure 7).

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Analog supply voltage range, left and right, AVOOL, AVOOR (see Note 1) .................. -0.3 V to 7 V
Digital supply voltage range, DVOO (see Note 2) ........................................ -0.3 V to 7 V
Clock supply voltage range, XVOO (see Note 3) ........................................ -0.3 V to 7 V
Output voltage range, Yo: L 1, L2 ........................................... -0.3 V to AVOOL + 0.3 V
R1, R2 ......................................... -0.3 V to AVOOR + 0.3 V
Input voltage range, VI ..................................................... -0.3 V to DVOO + 0.3 V
Operating free-air temperature range, TA ............................................... O°C to 70°C
Case temperature for 10 seconds, T C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Storage temperature range, Tstg .................................................... -55°C to 150°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values for maximum ratings are with respect to AGNDL and AGNOR respectively.
2. Voltage values for maximum ratings are with respect to DGND.
3. Voltage values for maximum ratings are with respect to XGND.

recommended operating conditions (see Note 4)
MIN

NOM

MAX

UNIT

Analog supply voltage, left and right, AVDOL, AVDDR

4.75

5

5.25

V

Digital supply voltage, DVOD

4.75

5

5.25

V

Clock supply voltage, XVOO

4.75

5

5.25

V

High-level input voltage, VIH

Low-level input voltage, VIL

XIN

0.9 VOD

All other digital inputs

0.76 VOD

V

XIN

0.1 VOO

All other digital inputs
10

Load resistance at PWM, RL
Master clock frequency at XIN
Operating free-air temperature, TA

V

0.24 VOD
kQ

16.3

24.6

0

70

MHz
'C

NOTE 4: DVDD, AVODL, XVDD and AVODR tied together represents VOD.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-251

TMS57014A
DUAL AUDIO DIGITAL·TO·ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995

electrical char.acteristics over recommended operating free-air temperature range (unless
otherwise noted)
digital interface, AVoo = DVoo = 5 V ± 5% (see Note 4)
PARAMETER

VOH

High-level output voltage

TEST CONDITIONS

MIN

TYPt

256FSO

10 =-0.4 mA

VDD-0.5

Ll, L2, Rl, R2

10=-12mA

VDD-0.5

XOUT

10=-1.2mA

VDD-0.5
VDD-0.5

MAX

UNIT

V

MUTEL, MUTER

10=-1 mA

256FSO

10 = 0.4 mA

0.4

Ll, L2, Rl, R2

10= 12mA

0.5

XOUT

10= 1.2mA

0.5

MUTEL, MUTER

10= 1 mA

VOL

Low-level output voltage

V

IIH

High-level input current, any digital input

±1

±5

~

IlL

Low-level input current, any digital input

±1

±5

I1A

0.4

Ci

Input capacitance

5

pF

Co

Output capacitance

5

. pF

t All typical values are at TA = 25°C.
NOTE 4: DVDD, AVDDL, XVDD and AVDDR tied together represents VDD.

supplies, AVoo

=DVoo =5 V ± 5%, no load
PARAMETER

TEST CONDITIONS

Analog power supply current

MIN

TYPt

AVDDL and AVDDR are shorted together

Digital power supply current

MAX

UNIT

15

mA

15

mA

Total device supply current over operating
temperature range
Power dissipation

60

mA

350

mW

t All typical values are at TA = 25°C.

DAC modulator, AVoo = DVoo = 5 V± 5%, sample rate (Fs)
TA 25°C, bandwidth is 20 Hz to 20 kHz

=

PARAMETER

= 44.1

kHz, full-scale input sine wave at 1 kHz,

TEST CONDITIONS

Resolution

See Note 5

Signal-to-noise ratio

A-weighted,
20 Hz to 20 kHz,
See Figure 10, Table 5, and Note 5

Total harmonic distortion

20 Hz to 20 kHz,

TYPt

MIN

MAX

18
De-emphasis not selected

UNIT
bits

96

100

See Note 5

0.003%

dB
0.004%

t All tYPical values are at TA = 25°C.
NOTE 5: These specifications are measured at the output (Va) of the low-pass filter shown in Figure 7.

, filter characteristics,AVoo

= DVoo = 5 V± 5%, de-emphasis disabled

PARAMETER
Pass-band ripple
Stop-band attenuation

TEST CONDITIONS
Sample rate (Fs) = 48 kHz,

See Note 5

Pass band (-3 dB) (DAC)
Stop band

TYPt

See Note 5

~TEXAS'

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT
dB

0.46 Fs

kHz

dB
kHz

0.54 Fs
29/Fs

t All tYPical values are at TA = 25°C.
NOTE 5: These specifications are measured at the output (Va) of the low-pass filter shown in Figure 7.

MAX
0.002

75
0

Group delay

3-252

MIN
-0.002

s

TMS57014A
DUAL AUDIO DIGITAL·TO·ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995

timing requirements (see Figures 8 and 9 and Note 6)
MIN

MAX

UNIT

tw1

Pulse duration, BCK

tsu1

Setup time, DATA before BCKi

20

ns

th1

Hold time, DATA after BCKi

20

ns

tsu2

Setup time, LRCK before BCKi

50

ns

th2

Hold time, LRCK after BCKi

50

ns

tw2

Pulse duration, SHIFT

100

ns

tsu3

Setup time, ATT before SHIFTi

20

ns

th3

Hold time, ATT after SHIFTi

20

ns

160

ns

tw3

Pulse duration, LATCH

100

ns

tsu4

Setup time, LATCH before SHIFTi

100

ns

th4

Hold time, LATCH after SHIFTi

tw2 + 20

ns

NOTE 6: All timing measurements were taken at the VDD/2 voltage level.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-253

TMS57014A·
DUAL AUDIO DIGITAL·TO·ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 -REVISED NOVEMBER 1995

PARAMETER MEASUREMENT INFORMATION

22kn
4700 pF
15 V

L2 (R2)

_ ' \ I \ I \ .....J\I"'\~ __

-+__

L -_ _. . -_ _ _

L1 (R1)

_ ' \ I \ I \ .....J\I\,'\~ __

10kn

-15V

5.6 kn

,~~~1 ~~~

-

AGNOL (AGNOR)

AGNOL (AGNOR)

100 pF
22kn
-

AGNOL (AGNOR)

Figure 7. Analog Low-Pass Filter Recommended for Measuring the
Dynamic Specifications of the TMS57014A
~~~
BCK

J

I+- tw1 -+I

{

tsu1 ~I"'I---~~I....-

I

th1

I+--

---.I

},-------\\-..l_--J'r---"""\\\-.
.
. l_--Jl
.

~~~
th2

-+I

*

..JX'-______...J*

DATA _ _ _ _ _

0

I

r
$e:::::::::x

I

LATCH

----------------t:--______)
I

I

i+- th4 ~ tw3
Figure 9. Control-Data Serial Timing

~TEXAS

3-254

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

{
J.
'I"

I
I
0

:

I

:
I

tsu4 ~

TMS57014A
DUAL AUDIO DIGITAL·TO·ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995

PARAMETER MEASUREMENT INFORMATION
Table 5. A-Weighted Data
FREQUENCY

A WEIGHTING (dB)

FREQUENCY

A WEIGHTING (dB)

25

-44.6±2

800

31.5

-39.2±2

1000

-0.1 ±1
O±O

40

-34.5 ±2

1250

0.6±1

50

-30.2±2

1600

1.0±1

63

-2S.1 ±2

2000

1.2±1
1.2 ±1

BO

-22.3±2

2500

100

-19.1 ±1

3150

1.2±1

125

-1S.1 ±1

4000

1.0±1

160

-13.2±1

5000

0.S±1

200

-10.B±1

6300

-0.1 ±1

250

-B.6±1

BOOO

-1.1 ±1

315

-S.S±1

10000

-2.4±1

400

-4.B±1

12500

-4.2±2

500

-3.2±1

16000

-S.S±2

630

-1.9±1

10

0

..,
CD

/

I
C

.2

1;;
c

~

1/,1
-10

-20

"

!

-30

-40

I

/

/

-50
20

100

1k

10 k 20 k

f - Signal Frequency - Hz

Figure 10. A-Weighted Function

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-255

TMS57014A
DUAL AUDIO DIGITAL·TO·ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995

APPLICATION INFORMATION
circuit and layout considerations
The designer should follow these guidelines for the best device performance.
•

Separate digital and analog ground planes should be used. All digital device functions should be over the
digital ground plane, and all analog device functions should be over the analog ground plane. The ground
planes should be connected at only one point to the direct power supply, and this is usually at the connector
edge of the board.

•

A single crystal-controlled clock should synchronously generate all digital signals

•

All power supply lines should include a O.1-IlF and a 1-IlF capacitor. When clock noise is excessive, a
toroidal inductance of 10 IlH should be placed in series with XVoo before connecting to DVoo.

•

The digital input control signals should be buffered when they are generated off the card.

•

Clock jitter should be minimized, and precautions taken to prevent clock overshoot. This minimizes any
high-frequency coupling to the analog output.

PCB footprint
Figure 11 shows the printed-circuit-board (PCB) land pattern for the TMS57014A small-outline package.

L1

f

•t
L

t
f

WI1 r-t

P

DDD DD r

L2

S

L2

f
L

•

it
f

DDD

DDl

L1

NOTE A: All linear dimensions are in millimeters.

Figure 11. Land Pattern for PCB Layout

~TEXAS

3-256

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-1

Contents
Page
TLC32040, TLC32041 : ..................................................... 4-3
TLC32044, TLC32045 : .................................................... 4-35
TLC32046: ................................................................ 4-73
TLC32047: .............................................................. 4-129
TLC320AC01 : ........................................................... 4-187
TLC320AC02: ........ ,.................................................. 4-273
TLC320AD50, TLC320AD52 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-361
TLC320AD55:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-417
TLC320AD56: ........................................................... 4-455
TLC320AD75: ......................................... ; . . . . . . . . . . . . . . . .. 4-495
TLC320AD80:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-535

C
(IJ

""C
~

otn
S»
::::J

C-

O

o
C

m

o

tn

4-2

TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

•
•

14-Bit Dynamic Range ADC and DAC
Variable ADC and DAC Sampling .Rate Up
to 19,200 Samples per Second

•

Switched-Capacitor Antialiasing Input Filter
and Output-Reconstruction Filter

•

•

•

•
•
•

N PACKAGE
(TOP VIEW)

Serial Port for Direct Interface to TMS32011,
TMS320C17, TMS32020, and TMS320C25
Digital Signal Process

NU

NU

RESET

NU

EODR

IN+
IN-

FSR
DR
MSTR CLK

Synchronous or Asynchronous ADC and
DAC Conversion Rate With Programmable
Incremental ADC and DAC Conversion
Timing Adjustments

AUXIN+
AUXINOUT+
OUT-

VDD
REF
DGTl GND
EODX

VCC+
VCCANlG GND

DX

ANlG GND

SHIFT ClK

Serial Port Interface to SN74299
Serial-to-Parallel Shift Register for Parallel
Interface to TMS32010, TMS320C15, or
Other Digital Processors

WORD/BYTE

NU

FSX

NU

600-Mil Wide N Package (CL to Cd
2s Complement Format
CMOS Technology

FN PACKAGE
(TOP VIEW)

tli

rr.l [B ::) ::)::) ~
ffi I8
Iu..wrr.zzz_

PART
NUMBER

OESCRIPTION

TLC32040

Analog interface circuit with internal reference.
Also a plug-in replacement for TLC32041 .

TLC32041

Analog interface
reference

circuit

without

internal

description
The TLC32040 and TLC32041 are complete
. analog-to-digital and digital-to-analog input!
output systems, each on a single monolithic
CMOS chip. This device integrates a bandpass
switched-capacitor antialiasing input filter, a
14-bit-resolution
AID
converter,
four
microprocessor-compatible serial port modes, a
14-bit-resolution D/A converter, and a low-pass
switched-capacitor output-reconstruction filter.

4 321

28 27 26

25

IN-

S

24

VDD
REF
DGTlGND

7

23

AUX IN+
AUX IN-

SHIFTClK

DR
MSTRClK

EODX

5

8

22

9

21

10

20

11
19
12 13 14 15 16 1718

OUT+
OUTVCC+
VCC-

NU - Nonusable; no external connection should be made to
these terminals.

AVAILABLE OPTIONS
PACKAGE
TA

O°C to 70°C

PLASTIC CHIP
CARRIER
(FN)

PLASTIC DIP
(N)

TLC32040CFN
TLC32041 CFN

TLC32040CN
TLC32041CN
TLC32040lN
TLC32041IN

-40°C to 85°C

~~~~T~~~o~~1~ s';~ift~~~I~~~h~r:~ :: fe'x::~~~~r::~fs

standard warranty. Production processing does not necessarilv include
testing of all parameters.

~TEXAS

Copyright © 1995. Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-3

TLC32040C, TLC320401, TLC32041 C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E -SEPTEMBER 1987 - REVISED MAY 1995

description (continued)
The device offers numerous combinations of master clock inpu(frequencies and conversion/sampling rates,
which can be changed via digital processor control.
Typical applications for this integrated circuit include modems (7.2~, 8-, 9.6-,14.4-, and 19.2-kHz sampling rate),
analog interface for digital signal processors (DSPs), speech recognition/storage systems, industrial process
control, biomedical instrumentation, acoustical signal processing, spectral analysis, data acquisition, and
instrumentation recorders. Four serial modes, which allow direct interface to the TMS32011, TMS320C17,
TMS32020, and TMS320C25 digital signal processors, are provided. Also, when the transmit and receive
sections of the analog interface circuit (AIC) are operating synchronously, it can interface to two SN74299
serial-to-parallel shift registers. These serial-to-parallel shift registers can then interface in parallel to the
TMS32010, TMS320C15, other digital signal processors, or external FIFO circuitry. Output data pulses are
emitted to inform the processor that data transmission is complete Or to allow the DSP to differentiate between
two transmitted bytes. A flexible control scheme is provided so that the functions of this integrated circuit can
be selected and adjusted coincidentally with signal processing via software control.
The antialiasing input filter comprises seventh-order and fourth-order CC-type (Chebyshev/elliptic transitional)
low-pass and high-pass filters, respectively and a fourth-order equalizer. The input filter is implemented in
switched-capacitor technology and is preceded by a continuous time filter to eliminate any possibility of aliasing
caused by sampled data filtering. When no filtering is desired, the entire composite filter can be switched out
of the signal path. A selectable, auxiliary, differential analog input is provided for applications where more than
one analog input is required.
.
The AID and D/A converters each have 14 bits of resolution. The AID and D/A architectures ensure no missing
codes and monotonic operation. An internal voltage reference is provided on the TLC32040 to ease the deSign
task and to provide complete control over the performance of this integrated circuit. The internal voltage
reference is brought out to a terminal and is available to the designer. Separate analog and digital voltage
supplies and grounds are provided to minimize noise and ensure a wide dynamic range. Also, the analog circuit
path contains only differential circuitry to keep noise to an absolute minimum. The only exception is the DAC
sample and hold, which utilizes pseudo-differential circuitry.
The output-reconstruction filter is a seventh-order CC-type (Chebyshev/elliptic transitional low-pass filter
followed by a fourth-order equalizer) and is implemented in switched-capacitor technology. This filter is followed
by a continuous-time filter to eliminate images of the digitally encoded signal.
The TLC32040C and TLC32041 C are characterized for operation from O°C to 70°C, and the TLC320401 and
TLC32041I are characterized for operation from -40°C to 85°C.

~TEXAS

INSTRUMENTS
4-4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TlC32040C, TlC320401, TlC32041C, TlC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

functional block diagram
Band-Pass Filter
Serial
Port

IN + --I--I~'"
IN---r-tl........'"

r--

AUX IN + --'-a............
AUX IN -

I
I
I

_-to........""

---------------------,

DR

---,

EODR

I
I
I
I
I
_ _ _ .JI

Internal
Voltage
Reference
(TLC32040
only)

I
I1... _ _

MSTRCLK
SHIFTCLK
WORD/BYTE

Low-Pass Filter
OUT++t----j

1J

OUT - ++--,----1
Transmit Section

VCC+ VCC- ANLG
GND

DTGL
VDD
GND (DIGITAL)

Terminal Functions
TERMINAL
NAME
ANLGGND

NO.

I/O

17,18

DESCRIPTION
Analog ground return for all internal analog circuits. Not internally connected to DGTl GND.

AUX IN+

24

I

AUXIN-

23

I

DGTlGND

9

DR

5

0

DR is used to transmij the ADC output bits from the AIC to the TMS320 serial port. This transmission of bits
from the AIC to the TMS320 serial port is synchronized with the SHIFT ClK signal.

DX

12

I

DX is used to receive the DAC input bits and timing and control information from the TMS320. This serial
transmission from the TMS320 serial port to the AIC is synchronized with the SHIFT ClK signal.

EODR

3

0

End of data receive. See the WORD/BYTE description and the Serial Port Timing diagrams. During the
word-mode timing, EODR is a low-going pulse that occurs immediately after the 16 bits of AID information
have been transmitted from the AIC to the TMS320 serial port. EODR can be used to interrupt a
microprocessor upon completion of serial communications. Also, EODR can be used to sirobe and enable
external serial-to-parallel shift registers, latches, or external FIFO RAM, and to facilitate parallel data bus
communications between the AIC and the serial-to-parallel shift registers. During the byte-mode timing,
EODR goes low after the first byte has been transmitted from the AIC to the TMS320 serial port and is kept
low until the second byte has been transmitted. The TMS32011 or TMS320C17 can use this low-going
signal to differentiate between the two bytes as to which is first and which is second. EODR does not occur
after secondary communication.

Noninverting auxiliary analog input state. This input can be switched into the bandpass filter and AID
converter path via software control. If the appropriate bit in the control register is a 1, the auxiliary inputs
replace the IN+ and IN- inputs. If the bit is a 0, the IN+ and IN- inputs are used (see the AIC DX data word
format section).
Inverting auxiliary analog input (see the above AUX IN + description)
Digital ground for all internal logic circuits. Not internally connected to ANlG GND.

~TEXAS

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4-5

TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

Terminal Functions (continued)
TERMINAL
NAME

NO.

I/O

DESCRIPTION

EODX

11

a

End of data transmit. See the WORD/BYTE description and the Serial Port Timing diagram. During the
word-mode timing, EODX is a low-going pulse that occurs immediately after the 16 bits of D/A converter
and control or register information have been transmitted from the TMS320 serial port to, the AIC. EODX
can be used to interrupt a microprocessor upon the completion of serial communications. Also, EODX can
be used to strobe and enable external serial-to-parallel shift registers, latches, or an external FIFO RAM,
and to facilitate parallel data-bus communications between the AIC and the serial-to-parallel shift registers.
During the byte-mode timing, EODX goes low after the first byte has been transmitted from the TMS320
serial port to the AIC and is kept low until the second byte has been transmitted. The TMS32011 or
TMS320C17 can use this low-going signal to differentiate between the two bytes as to which is first and
which is second.

FSR

4

a

Frame sync receive. In the serial transmission modes, which are described in the WORD/BYTE description,
FSR is held low during bit transmission. When FSR goes low, the TMS320 serial port begins receiving bits
from the AIC via DR of the AIC. The most significant DR bit is present on DR before FSR goes low. (See
Serial Port Timing and Internal Timing Configuration diagrams.) FSR does not occur after secondary
communication.

FSX

14

a

Frame sync transmit. When FSX goes low, the TMS320 serial port begins transmitting bits to the AIC via
DX of the AIC. In all serial transmission modes, which are described in the WORD/BYTE description, F5X
is held low during bit transmission (see the Serial Port Timing and Internal TIming Configuration diagrams).

IN+

26

I

IN-

25

I

Inverting input to analog input amplifier stage

MSTR ClK

6

I

Master clock. MSTR ClK is used to derive all the key logic signals of the AIC, such as the shift clock, the
switched-capacitor filter clocks, and the ND and D/A timing signals. The Internal Timing Configuration
diagram shows how these key signals are derived. The frequencies of these key signals are synchronous
submultiples of the master clock frequency to eliminate unwanted aliasing when the sampled analog signals
are transferred between the SWitched-capacitor filters and the ND and D/A converters (see the Internal
Timing Configuration).

OUT+

22

a

Noninverting output of analog output power amplifier. OUT + can drive transformer hybrids or
high-impedance loads directly in either a differential or a single-ended configuration.

OUT-

21

a

Inverting output of analog output power amplifier. OUT - ip functionally identical with and complementary
to OUT +.

REF

8

I/O

Internal voltage reference for the TlC32040. For the TlC32040 and TlC32041 an external voltage
reference can be applied to this terminal.

RESET

2

I

Reset. A reset function is provided to initialize the TA, TA', TB, RA, RA', RB, and control registers. This r.eset
function initiates serial communications between the AIC and DSP. The reset function initializes all AIC
registers including the control register. After a negative-going pulse on RESET, the AIC registers are
initialized to provide an 8-kHz data conversion rate for a 5.184-MHz master clock input signal. The
conversion rate adjust registers, TA' and RA', are reset to 1. The control register bits are reset as follows
(see AIC DX data word format section):
d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1
This initialization allows normal serial-port communication to occur between AIC and DSP.

SHIFTClK

10

a

Shift clock. SHIFT ClK is obtained by dividing the master clock signal frequency by four. SHIFT ClK is used
to clock the serial data transfers of the AIC, described in the WORD/BYTE description below (see the Serial
Port TIming and Internal Timing Configuration diagrams).

VDD

7

Noninverting input to analog input amplifier stage

Digital supply voltage, 5 V ±5%

VCC+

20

Positive analog supply voltage, 5 V ±5%

VCC-

19

Negative analog supply voltage, -5 V ±5%

~TEXAS

4-6

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

Terminal Functions (continued)
TERMINAL
NAME

NO.

WORD/BYTE

13

I/O

DESCRIPTION

I

WORD/BYTE, in conjunction with a bit in the control register, is used to establish one of four serial modes.
These four serial modes are described below.
A/C transmit and receive sections are operated asynchronously.
The following description applies when the AIC is configured to have asynchronous transmit and receive
sections. If the appropriate data bit in the control register is a 0 (see the AIC DX data word format section).
the transmit and receive sections are asynchronous.
L
Serial port directly interfaces with the serial port of the TMS32011 or TMS320C 17 and
communicates in two 8-bit by1es. The operation sequence is as follows (see Serial Port Timing
diagrams).
1. FSX or FSR is brought low.
2. One 8-bit byte is transmitted or one 8-bit byte is received.
3. EODX or EODR is brought low.
4. FSX or FSR emits a positive frame-sync pulse that is four shift clock cycles wide.
5. One 8-bit byte is transmitted or one 8-bit by1e is received.
6. EODX or EODR is brought high.
7. FSX or FSR is brought high.
H Serial port directly interfaces with the serial port of the TMS32020, TMS320C25, or TMS320C30
and communicates in one 16-bit word. The operation sequence is as follows (see Serial Port
Timing diagrams):
1. FSX or FSR is brought low.
2. One 16-bit word is transmitted or one 16-bit word is received.
3. FSX or FSR is brought high.
4. EODX or EODR emits a low-going pulse.
AIC transmit and receive sections are operated synchronously.
If the appropriate data bit in the control register is a 1, the transmit and receive sections are configured to
be synchronous. In this case, the bandpass switched-capacitor filter and the ND conversion timing are
derived from the TX counter A, TX counter B, and TA, TA', and TB registers, rather than the RX counter A,
RX counter B, and RA, RA', and RB registers. In this case, the AIC FSX and FSR timing are identical during
primary data communication; however, FSR is not asserted during secondary data communication since
there is no new ND conversion result. The synchronous operation sequences are as follows (see Serial
Port Timing diagrams).
Serial port directly interfaces with the serial port of the TMS32011 or TMS320C17 and
L
communicates in two 8-bit bytes. The operation sequence is as follows (see Serial Port Timing
diagrams):
1. FSX and FSR are brought low.
2. One 8-bit byte is transmitted and one 8-bit byte is received.
3. EODX and EODR are brought low.
4. FSX and FSR emit positive frame-sync pulses that are four shift clock cycles wide
5. One 8-bit byte is transmitted and one 8-bit byte is received.
6. EODX and EODR are brought high.
7. FSX and FSR are brought high.
H Serial port directly interfaces with the serial port of the TMS32020, TMS320C25, or TMS320C30
and communicates in one 16-bit word. The operation sequence is as follows (see Serial Port
Timing diagrams):
1. FSX and FSR are brought low.
2. One 16-bitword is transmitted and one 16-bit word is received.
3. FSX and FSR are brought high.
4. EODX or EODR emit low-going pulses.
Since the transmit and receive sections of the AIC are now synchronous, the AIC serial port with additional
NOR and AND gates will interface to two SN74299 serial-to-parallel shift registers. Interfacing the AIC to
the SN74299 shift register allows the AIC to interface to an external FIFO RAM and facilitates parallel data
bus communications between the AIC and the digital signal processor. The operation sequence is the same
as the above sequence (see Serial Port Timing diagrams).

~TEXAS

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ANALOG INTERFACE CIRCUITS
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detailed description
analog input
Two sets of analog inputs are provided. Normally, the IN + and IN- input set is used; however, the auxiliary input
set, AUX IN + and AUX IN- , can be used if a second input is required. Each input set can be operated in either
differential or single-ended modes, since sufficient common-mode range and rejection are provided. The gain
for the IN +, IN-, AUX IN +, and AUX IN- inputs can be programmed to be either 1, 2, or 4 (see Table 2). Either
input circuit can be selected via software control. It is important to note that a wide dynamic range is assured
by the differential internal analog architecture and by the separate analog and digital voltage supplies and
grounds.

AID bandpass filter, AID bandpass filter clocking, and AID conversion timing
The NO bandpass filter can be selected or bypassed via software control. The frequency response of this filter
is presented in the following pages. This response results when the switched-capacitor filter clock frequency
is 288 kHz. Several possible options can be used to attain a 288-kHz switched-capacitor filter clock. When the
filter clock frequency is not 288 kHz, the filter transfer function is frequency scaled by the ratio of the actual clock
frequency to 288 kHz. The low-frequency roll-off of the high-pass section is 300 Hz.
The internal timing configuration and Ale OX data word format sections of this data sheet indicate the many
options for attaining a 288-kHz bandpass switched-capacitor filter clock. These sections indicate that the RX
counter A can be programmed to give a 288-kHz bandpass switched-capacitor filter clock for several master
clock input frequencies.
The NO conversion rate is then attained by frequency dividing the 288-kHz bandpass switched-capacitor filter
clock with the RX counter B. Thus, unwanted aliasing is prevented because the NO conversion rate is an
integral submultiple of the bandpass switched-capacitor filter sampling rate, and the two rates are
synchronously locked.

AID converter performance specifications
Fundamental performance specifications for the AID converter circuitry are presented in the AID converter
operating characteristics section of this data sheet. The realization of the AID converter circuitry with
switched-capacitor techniques provides an inherent sample-and-hold.

analog output
The analog output circuitry is an analog output power amplifier. Both non inverting and inverting amplifier outputs
are brought out of this integrated circuit. This amplifier can drive transformer hybrids or low-impedance loads
directly in either a differential or Single-ended configuration.

DIA low-pass filter, DIA low-pass filter clocking, and DIA conversion timing
The frequency response of this filter is presented in the following pages. This response results when the
low-pass switched-capacitor filter clock frequency is 288 kHz. Like the NO filter, the transfer function of this filter
is frequency scaled when the clock frequency is riot 288 kHz. A continuous-time filter is provided on the output
on the output of the D/A low-pass filter to greatly attenuate any switched-capacitor clock feedthrough.
The D/A conversion rate is then attained by frequency dividing the 288-kHz switched-capacitor filter clock with
TX counter B. Thus, unwanted aliasing is prevented because the D/A conversion rate is an integral submultiple
of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously locked.

~TEXAS

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ANALOG INTERFACE CIRCUITS
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asynchronous versus synchronous operation
If the transmit section of the AIC (low-pass filter and DAC) and receive section (bandpass filter and ADC) are
operated asynchronously, the low-pass and band-pass filter clocks are independently generated from the
master clock signal. Also, the D/A and AID conversion rates are independently determined. If the transmit and
receive sections are operated synchronously, the low-pass filter clock drives both low-pass and bandpass
filters. In synchronous operation, the AID conversion timing is derived from, and is equal to, the D/A conversion
timing. (See description of WORD/BYTE in the Terminal Functions table.)

D/A converter performance specifications
Fundamental performance specifications for the D/A converter circuitry are presented in the D/A converter
operating characteristics section of the data sheet. The D/A converter has a sample-and-hold that is realized
with a switched-capacitor ladder.

system frequency response correction
The (sin xlix correction circuitry is performed in the digital processor software. The system frequency response
can be corrected via DSP software to ±0.1-dB accuracy to band edge of 3000 Hz for all sampling rates. This
correction is accomplished with a first-order digital correction filter, which requires only seven TMS320
instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of only 1.1 %
and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the (sin x}/x correction section for more details).

serial port
The serial port has four possible modes that are described in detail in the Terminal Functions table. These
modes are briefly described below and in the description for WORD/BYTE in the Terminal Functions Table.
•

The transmit and receive sections are operated asynchronously, and the serial port interfaces directly with
the TMS32011 and TMS320C17.

•

The transmit and receive sections are operated asynchronously, and the serial port interfaces directly with
the TMS32020 and the TMS320C25.

•

The transmit and receive sections are operated synchronously, and the serial port interfaces directly with
the TMS32011 and TMS320C17.

•

The transmit and receive sections are operated synchronously, and the serial port interfaces directly with
the TMS32020, TMS320C25, or two SN74299 serial-to-parallel shift registers, which can then interface in
parallel to the TMS320C1 0, TMS32015, to any other digital signal processor, or to external FIFO circuitry.

operation of TLC32040 with internal voltage reference
The internal reference of the TLC32040 eliminates the need for an external voltage reference and provides
overall circuit cost reduction. Thus, the internal reference eases the design task 'and provides complete control
over the performance of this integrated circuit. The internal reference is brought out to a terminal and is available
to the designer. To keep the amount of noise on the reference signal to a minimum, an external capacitor may
be connected between REF and ANLG GND.

operation of TLC32040 or TLC32041 with external voltage reference
REF can be driven from an external reference circuit if so desired. This external circuit must be capable of
, supplying 250 /lA and must be adequately protected from noise such as crosstalk from the analog input.

~TEXAS

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ANALOG INTERFACE CIRCUITS
SLAS014E- SEPTEMBER 1987 - REVISED MAY 1995

reset

A reset function is provided to initiate serial communications between the AIC and DSP and allow fast,
cost-effective testing during manufacturing. The reset function initializes all AIC registers, including the control
register. After a negative-going pulse on RESET, the AIC is initialized. This initialization allows normal serial port
communications activity to occur between AIC and DSP (see AIC DX data word format section).

loop back
This feature allows the user to test the circuit remotely. In loopback, OUT + and OUT - are internally connected
to IN+ and IN-. Thus, the DAC bits (d15 to d2), which are transmitted to DX, can be compared with the ADC
bits (d15 to d2), which are received from DR. An ideal comparison would be that the bits on DR equal the bits
on DX. However, in practice there is some difference in these bits due to the ADC and DAC output offsets.
In loopback, if IN+ and N- are enabled, the external signals on IN+ and IN- are ignored. If AUX IN+ and AUX
IN- are enabled, the external signals on these terminals are added to the OUT + and OUT - signals in loopback
operation.
The loopback feature is implemented with digital signal processor control by transmitting the appropriate serial
port bit to the control register (see AIC DX data word format section).
explanation of internal timing configuration

All of the internal timing of the AIC is derived from the high-frequency clock signal that drives the master clock
input. The shift clock signal, which strobes the serial port data between the AIC and DSP, is derived by dividing
the master clock input signal frequency by {our.
SCF Clock Frequency

=

Master Clock Frequency
2 x Contents of Counter A

SCF Clock Frequency
.
Conversion Frequency = Contents of Counter B
Shift Clock Frequency = Master CIOC~ Frequency
TX counter A and TX counter B, which are driven by the master clock signal, determine the D/A conversion
timing. Similarly, RX counter A and RX counter B determine the AID conversion timing. In order for the
switched-capacitor low-pass and band pass filters to meet their transfer function specifications, the frequency
of the clock inputs of the switched-capacitor filters must be 288 kHz. If the frequencies of the clock inputs are
not 288 kHz, the filter transfer function frequencies are scaled by the ratios of the clock frequencies to 288 kHz.
Thus, to obtain the specified filter responses, the combination of master clock frequency and TX counter A and
RX counter A values must yield 288-kHz switched-capacitor clock signals. These 288-kHz clock signals can
then be divided by the TX counter Band RX counter B to establish the D/A and AID conversion timings.
TX counter A and TX counter B are reloaded every D/A conversion period, while RX counter A and RX counter
B are reloaded every AID conversion period. The TX counter Band RX counter B are loaded with the values
in the TB and RB registers, respectively. Via software control, the TX counter A can be loaded with either the
TA register, the TA register less the TA' register, or the TA register plus the TA' register. By selecting the TA
register less the TA' register option, the upcoming conversion timing will occur earlier by an amount of time that
equals TA' times the signal period of the master clock. By selecting the TA register plus the TA' register option,
the upcoming conversion timing will occur later by an amount of time that equals TA' times the signal period of
the master clock. Thus, the D/A conversion timing can be advanced or retarded. An identical ability to alter the
AID conversion timing is provided. In this case, however, the RX counter A can be programmed via software
control with the RA register, the RA register less the RA' register, or the RA register plus the RA' register.

~TEXAS

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ANALOG INTERFACE CIRCUITS
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explanation of internal timing configuration (continued)

The ability to advance or retard conversion timing is particularly useful for modem applications. This feature
allows controlled changes in the AJD and D/A conversion timing. This feature can be used to enhance
signal-to-noise performance, to perform frequency-tracking functions, and to generate nonstandard modem
frequencies.
If the transmit and receive sections are configured to be synchronous (see WORD/BYTE description), then both
the low-pass and bandpass switched-capacitor filter clocks are derived from TX counter A. Also, both the D/A
and AID conversion timing are derived from the TX counter A and TX counter B. When the transmit and receive
sections are configured to be synchronous, the RX counter A, RX counter B, RA register, RA' register, and RS
registers are not used.

~TEXAS

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ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

r-----------------,
D' 'd b

I

MSTR ClK
5.184 MHz (1)
10.368 MHz (2) . L

IVI

e y4

-----------------'

SHIFTClK
1.296 MHz (1)
2.592 MHz (2)

------------------~----------,

Optional External Circuitry
for Full-Duplex Modems

r

I
I
I
I
I
I
I

Divide by2'

--------------,
153.6 -kHz
Clock (1)

Commercial
External
Front-End
Full-Duplex
Split-Band
Filterst

I
I
I
I
I
I
I

dO, d1 = 0,0
dO, d1 = 1,1*

~----------------'

dO, d1 = 0,1
dO, d1 = 1,0*

TXCounter A
[TA = 9 (1))
[TA = 18 (2))
(6 bits)

576-kHz
Pulses

TXCounterB
[TB = 40; 7.2 kHz
[TB = 36; 8.0 kHz
[TB = 30; 9.6 kHz
[TB = 20; 14.4 kHz
ITB = 15; 19.2 kHz

Divideby2

I
I
I
I
I
I
I
I
I

dO, d1 = 0,0
dO, d1 = 1,1*

dO d1 - 0 1
do: d1 : 1:0*

RX Counter A
IRA = 9 (1)]
IRA = 18 (2))
(6 bits)

576-kHz
Pulses

RX Counter B
IRB = 40; 7.2 kHz
IRB = 36; 8.0 kHz
IRB = 30; 9.6 kHz
IRB = 20; 14.4 kHz
IRB = 15; 19.2 kHz

low-Pass!
Switched
Capacitor Filter
ClK= 288-kHz
Square Wave

D!A
Conversion
Frequency

Band-Pass
Switched
Capacitor Filter
elK= 288-kHz
Square Wave

AID
Conversion
Frequency

L ______________________________

SCF Clock Frequency

=

J

Master Clock Frequency
2 x Contents of Counter A

t Split-band filtering can alternatively be performed after the analog input function via software in the TMS320.
:j: These control bits are described in the AIC OX data word format section.

NOTE A: Frequency 1 (20.736 MHz) is used to show how 153.6 kHz (for comm.ercially available modem split-band filter clock), popular speech
and modem sampling signal frequencies, and an internal 288-kHz switched-capacitor filter clock can be derived synchronously and as
submultiples of the crystal oscillator frequency. Since these derived frequencies sre synchronous submultiples of the crystal frequency,
aliasing. does not occur as the sampled analog signal passes between the analog converter and switched-capacitor filter stages.
Frequency 2 (41.472 MHz) is used to show that the AIC can work with high-frequency signals, which are used by high-speed digital
signal processors.

Figure 1. Internal Timing Configuration

~TEXAS
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.

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ANALOG INTERFACE CIRCUITS
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AIC DR or OX word bit pattern
AID or D/A MSB,
1st bit sent

AID or D/A LSB

1st bit sent of 2nd byte

AIC OX data word format section
d15

I d14 I d13J d12Jd11 Jd10 Id9 Jd8 Id7

I d6 I d5 I d4 I d3\ d21d1 IdO

COMMENTS

primary OX serial communication protocol
;-d15 (MSB) through d2 go to the D/A
converter register

--->

I0

0

The TX and RX counter As are loaded with ihe TA
and RA register values. The TX and RX counter Bs
are loaded with TB and RB register values.

;-d15 (MSB) through d2 go to the D/A
converter register

--->

I0

1

The TX and RX counter As are loaded with the TA +
TA' and RA + RA: register values. The TX and RX
counter Bs are loaded with TB and RB register
values. Bits dl = 0 and dO =1 cause the next D/A and
AID conversion periods to be changed by the
addition of TA: and RA' master clock cycles, in which
TA' and RIA: can be positive or negative or zero (refer
to Table 1).

<-d15 (MSB) through d2 go to the D/A
converter register

--->

II

0

The TX and RX counter As are loaded with the TA TA: and RA - RA: register values. The TX and RX
counter Bs are loaded with TB and RB register
values. Bits dl = 1 and dO = 0 cause the next D/A and
AID conversion periods to be changed by the
subtraction of TA' and RA: master clock cycles, in
which TA: and RIA: can be positive or negative or zero
(refer to Table 1).

<-d15 (MSB) through d2 go to the D/A
converter register

---> 11

1

The TX and RX counter As are loaded with the TA
and RA register values. The TX and RX counter Bs
are loaded with the TB and RB register values. After
a delay of four shift clock cycles, a secondary
transmission immediately follows to program the AIC
to operate in the desired configuration.

NOTE: Setting the two least Significant bits to 1 in the normal transmission of DAC information (primary communications) to the AIC initiates
secondary communications upon completion of the primary communications.
Upon completion of the primary communication, FSX remains high for four SHIFT ClK cycles and then goes low and initiates the
secondary communication. The timing specifications for the primary and secondary communications are identical. In this manner, the
secondary communication, if initiated, is interleaved between successive primary communications. This interleaving prevents the
secondary communication from interfering with the primary communications and DAC timing, thus preventing the AIC from skipping a DAC
output. In the synchronous mode, FSR is not asserted during secondary communications.

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ANALOG INTERFACE CIRCUITS
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secondary OX serial communication protocol
x x I ~ to TA register -7 I x x

I

~ to RA register

x I ~ to TA' register -7 I x
x I ~ to TB register

1 ~ to RA' register
-7 1x 1 ~ to RB register

x x x x x x x x

a a
a 1
1 a

-71
-71
-71

d7 d6 d5 d4 d3 d2

~

Control
register

1

d13 and d6 are MSBs (unsigned binary)
d14 and d7 are 2's complement sign bits
d14 and d7 are MSBs (unsigned binary)

1

= all
= all
d4 = all
d5 = all
d6 = all
d7 = all
d2

---+I

d3

deletes/inserts the bandpass filter
disables/enables the loopback function

.disables/enables the AUX IN + and AUX IN- terminals
asynchronouslsynchronous transmit receive sections
gain control bits (see gain control section)
gain control bits (see gain control section)

rese.t function
A reset function is provided to initiate serial communications between the Ale and DSP, The reset function
initializes all Ale registers, including the control register. After power has been applied to the Ale, a
negative-going pulse on RESET initializes the Ale registers to provide an 8-kHz AID and D/A conversion rate
for a 5.184-MHz master clock input signal. The Ale, except the control register, is initialized as follows (see Ale
DX data word format section):
INITIALIZED
REGISTER
VALUE (HEX)

REGISTER

9

TA
TA'
TB

24

RA

9

RA'
RB

24

The control register bits are reset as follows (see Ale DX data word format section):
d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1
This initialization allows normal serial port communications to occur between Ale and DSP. If the transmit and
receive sections are configured to operate synchronously and the ,user wishes to program different conversion
rates, only the TA, TA', and TB register need to be programmed, since both transmit and receive timing are
synchronously derived from these registers (see the terminal descriptions and Ale DX word format sections).
The circuit shown below provides a reset on power up when power is applied in the sequence given under
power-up sequence. The circuit depends on the power supplies reaching their recommended values a minimum
of 800 ns before the capacitor charges to 0.8 V above DGTL GND.
TLC320401
TLC32041

r--::Vc-=-c-=-+"l--.- 5 v
200kQ
RESET ---.

Vcc-

::::r:O.5~F

-5V

~TEXAS

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power-up sequence
To ensure proper operation of the Ale, and as a safeguard against latch-up, it is recommended that a Schottky
diode with a forward voltage less than or equal to 0.4 V be connected from Vcc- to ANLG GND (see Figure 17).
In the absence of such a diode, power should be applied in the following sequence: ANLG GND and DGTL GND,
VCC-, then VCC+ and Voo. Also, no input signal should be applied until after power up.

AIC responses to improper conditions
The Ale has provisions for responding to improper conditions. These improper conditions and the response of
the Ale to these conditions are presented in Table 1 below.

AIC register constraints
The following constraints are placed on the contents of the Ale registers:
1.
2.
3.
4.
5.
6.
7.
8.
9.

TA register must be ~ 4 in word mode (WORD/BYTE = high).
TA register must be ~ 5 in byte mode (WORD/BYTE = low).
TA' register can be either positive, negative, or zero.
RA register must be ~ 4 in word mode (WORD/BYTE = high).
RA register must be ~ 5 in byte mode (WORD/BYTE = low).
RA' register can be either positive, negative, or zero.
(TA register ± TA' register) must be > 1.
(RA register ± RA' register) must be > 1.
TB register must be > 1.
Table 1. Ale Responses To Improper Conditions

IMPROPER CONDITIONS

AIC RESPONSE

TA register + TA' register = 0 or 1
TA register - TA' register = 0 or 1

Reprogram TX counter A with TA register value

TA register + TA' register < 0

MODULO 64 arithmetic is used to ensure that a positive value is loaded into the TX counter A, i.e., TA
register + TA' register + 40 hex is loaded into TX counter A.

RA register + RA' register = 0 or 1
RA register - RA' register = 0 or 1

Reprogram RX counter A with RA register value

RA register + RA' register = 0 or 1

MODULO 64 arithmetic is used to ensure that a positive value is loaded into RX counter A, i.e., RA
register + RA' register + 40 hex is loaded into RX counter A.

TA register = 0 or 1
RA register = 0 or 1

The AIC is shut down.

TA register < 4 in word mode
TA register < 5 in byte mode
RA register < 4 in word mode
RA register < 5 in byte mode

The AIC serial port no longer operates.

TB register = 0 or 1

Reprogram TB register with 24 hex

RB register = 0 or 1

Reprogram RB register with 24 hex

AIC and DSP cannot communicate

Hold last DAC output

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ANALOG INTERFACE CIRCUITS
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improper operation due to conversion times being too close together
If the difference between two successive D/A conversion frame syncs is less than 1/19.2 kHz, the Ale operates
improperly. In this situation, the second D/A conversion frame sync occurs too quickly and there is not enough
time for the ongoing conversion to be completed. This situation can occur if the A and B registers are improperly
programmed or if the A + A' register or A - A' register result is too small. When incrementally adjusting the
conversion period via the A + A' register options, the designer should be very careful not to violate this
.
requirement (see following diagram).
11

.

(

~)

Frame Sync --;'
FSX or FSR
~

12

,

I

.....,,!

1-._ _

t4-- Ongoing Conversion ~
12 - 11 2': 1/19.2 kHz

asynchronous operation frame syncs

more than one receive frame sync occurring between two transmit

When incrementally adjusting the conversion period via the A + f:< or A - f:< register options, a specific protocol
is followed. The command to use the incremental conversion period adjust option is sent to the Ale during a
FSX frame sync. The ongoing conversion period is then adjusted. However, either receive conversion period
A or B may be adjusted. For both transmit and receive conversion periods, the incremental conversion period
adjustment is performed near the end of the conversion period. Therefore, if there is sufficient time between
t1 and t2, the receive conversion period adjustment is performed during receive conversion period A. Otherwise,
the adjustment is performed during receive conversion period B. The adjustment command only adjusts one
transmit conversion period and one receive conversion period. To adjust another pair of transmit and receive
conversion periods, another command must be issued during a subsequent FSX frame (see figure below).

w
11

W

!oII~------ Transmit Conversion Period ------~~

Conversion
Period A

-+-

Conversion
Period B

---I

~TEXAS

4-16

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

asynchronous operation - more than one receive frame sync occurring between two receive frame syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register optiDns, a specific protocol
is followed. For both transmit and receive conversion periods, the incremental conversion period adjustment
is performed near the end of the conversion period. The command to use the incremental conversion period
adjust options is sent to the AIC during a FSX frame sync. The ongoing transmit conversion period is then
adjusted. However, three possibilities exist for the receive conversion period adjustment in the diagram as
shown in the following figure. If the adjustment command is issued during transmit conversion period A, receive
conversion period A is adjusted if there is sufficient time between t1 and t2' Or, if there is not sufficient time
between t1 and t2, receive conversion period B is adjusted. Or, the receive portion of an adjustment command
can be ignored if the adjustment command is sent during a receive conversion period, which is already being
or is adjusted due to a prior adjustment command. For example, if adjustment commands are issued during
transmit conversion periods A, B, and C, the first two commands can cause receive conversion periods A and
B to be adjusted, while the third receive adjustment command is ignored. The third adjustment command is
ignored since it was issued during receive conversion period B, which already is adjusted via the transmit
conversion period B adjustment command.

l+-

Transmit
Conversion
Period A

-+-

Transmit
Conversion
Period B

--+-

Transmit
Conversion
Period C

1--Jr-------,W

-...J

t2

FSR

~

Receive Conversion Period A

~..

~
Receive Conversion Period B

------.j

asynchronous operation - more than one set of primary and secondary OX serial communication occurring
between two receive frame sync (see Ale ox data word format section)
The TA, TA', TB, and control register information that is transmitted in the secondary communications is always
accepted and is applied during the ongoing transmit conversion period. If there is sufficient time between t1 and
t2, the TA, RA', and RB register information, which is sent during transmit conversion period A, is applied to
receive conversion period A. Otherwise, this information is applied during receive conversion period B. If RA,
RA', and RB register information has already been received and is being applied during an ongoing conversion
period, any subsequent RA, RA', or RB information that is received during this receive conversion period is
disregarded (see diagram below).'
Primary
FSxl

t1
secondaryi-_ _--. Primary

Secondaryi-_ _..., Primary

nil n

14~---

Transmit
Conversion
Period A

~

Transmit
Conversion
Period B

1n

---~~~---

2
11-1_ _...

FSR

secondaryr-_ _--.

I

Transmit
Conversion
Period C

~

---~~

1

+- Receive Conversion -l+~---- Receive Conversion Period B ----~~
Period A

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-17

TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

Table 2. Gain Control Table Analog Input Signal Required for Full-Scale AID Conversion
CONTROL REGISTER BITS

INPUT CONFIGURATIONS

Differential configuration
Analog input = IN + -IN= AUX IN+-AUX IN-

Single-ended configuration
Analog input = IN + - ANLG GND
= AUX IN + - ANLG GND

ANALOG INPUrt

AID CONVERSION
RESULT

d6

d7

1

1

0

0

1

0

±3V

Full scale

0

1

±1.5V

Full scale

±3V

Half scale

±6V

Full scale

1

1

0

0

1

0

±3V

Full scale

0

1

±1.5 V

Full scale

..
. .
t In this example, Vref IS assumed to be 3 V. In order to minimize distortion, It IS recommended that the analog mput not exceed 0.1 dB below full
scale.
Rfb

Rfb
R

R

AUXIN+

IN+
}

IN-

To Multiplexer

}

AUXIN-

To MUltiplexer

R

R

Rfb

Rfb

Rfb = R for d6 = I, d7 = 1
d6=O,d7=0
Rfb = 2R for d6 = I, d7 = 0
Rfb=4Rford6=O,d7= 1

Rfb = R for d6 = I, d7 = 1
d6 =0, d7 = 0
Rfb = 2R for d6 = I, d7 = 0
Rfb = 4R for d6 = 0, d7 = 1

Figure 2. IN+ and IN- Gain
Control Circuitry

Figure 3. AUX IN+ and AUX INGain Control Circuitry

(sin x)/x correction section
The Ale does not have (sin x)/x correction circuitry after the digital-to-analog converter. The (sin x)/x correction
can be accomplished easily and efficiently in digital signal processor (DSP) software. Excellent correction
accuracy can be achieved to a band edge of 3000 Hz by using a first-order digital correction filter. The results,
which are shown below, are typical of the numerical correction accuracy that can be achieved for sample rates
of interest. The filter requires only seven instruction cycles per sample on the TMS320 DSPs. With a 200-ns
instruction cycle, nine instructions per sample represents an overhead factor of 1.4% and 1.7% for sampling
rates of 8000 Hz and 9600 Hz, respectively. This correction adds a slight amount of group delay at the upper
.
edge of the 30D-3000-Hz band.

~TEXAS

INSTRUMENTS
4-18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E- SEPTEMBER 1987 - REVISED MAY 1995

(sin x)/x roll-off for a zero-order hold function
The (sin x)/x roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for the
various sampling rates is shown in the table below.

Table 3. (sin x)/x Roll-Off
20 log

tits
tits
(t: 3000 Hz)
sin

11
11

ts (Hz)

(dB)

7200

-2.64

8000

"';2.11

9600

-1.44

14400

-0.63

19200

-0.35

The actual AIC (sin x)/x roll-off is slightly less than the above figures, because the AIC has less than a 100%
duty cycle hold interval.

correction filter
To compensate for the (sin x)/x roll-off of the AIC, a first-order correction filter shown below, is recommended.

p1

The difference equation for this correction filter is:
yi + 1 = p2(1 - p1)

(Uj +

1) + p1 yi

where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
IH(f)12 =

p2 2(1 - p1)2
1 - 2p1 cos(2 11: f/fs)

+ p12

~TEXAS

INSTRUMENTS
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4-19

TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

correction results
Table 4 below shows the optimum p values and the corresponding correction results for BOOO-Hz and 9600-Hz
sampling rates.
Table 4. Correction Results
f (Hz)

ERROR (dB)

ERROR (dB)

fs .. 8000 Hz
p1 .. -0.14813
p2 =0.9888

fs = 9600 Hz
p1 .. -0.1307
p2 .. 0.9951

300

-0.099

-0.043

600

-0.089

-0.043

900

-0.054

0

1200

-0.002

0

1500

0.041

a

1800

0.079

0.043

2100

0.100

0.043

2400

0.091

2700

-0.043

3000

-0.102

0.043

a
-0.043

TMS320 software requirements
The digital correction filter equation can be written in state variable form as follows:
Y = k1 x Y + k2 x U
where
k1 = p1
k2 =·(1 - p1) x p2
Y = filter state
U '" next 1/0 sample
The coefficients k1 and k2 must be represented as 16-bit integers. The SACH instruction (with the proper shift)
will yield the correct result. With the assumption that the TMS320 processor page pointer and memory
configuration are properly initialized, the equation can be executed in seven instructions or seven cycles with
the following program: .
ZAC
LT K2
MPYU
LTA K1
MPYY
APAC
SACH (dma), (shift)

~TEXAS

4--20

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage range, VCC+ (see Note 1) ............................................ -0.3 V to 15 V
Supply voltage range, Voo ......................................................... -0.3 V to 15 V
Output voltage range, Va .......................................................... -0.3 Vto 15 V
Input voltage range, VI ............................................................. -0.3 V to 15 V
Digital ground voltage range ........................................................ -0.3 V to 15 V
Operating free-air temperature range, TA: TLC32040C, TLC32041 C ...................... O°C to 70°C
TLC320401, TLC.32041 ...................... -40°C to 85°C.
Storage temperature range, Tstg ................................................... -40°C to 125°C
Case temperature for 10 seconds: FN package .............................................. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ..................... 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values for maximum ratings are with respect to VCC-.

recommended operating conditions
MIN

NOM

MAX

UNIT

Supply voltage, V CC + (see Note 2)

4.75

5

5.25

V

Supply voltage, VCC- (see Note 2)

-4.75

-5

-5.25

V

4.75

5

5.25

V

4

V

Digital supply voltage, VDD (see Note 2)
Digital ground voltage with respect to ANLG GND, DGTL GND
Reference input voltage, Vref(ext) (see Note 2)

0
2

High-level input voltage, VIH

2

VDD+0.3

-0.3

LOW-level input voltage, VIL (see Note 3)
Load resistance at OUT + and/or OUT -, RL

MSTR CLK frequency (see Note 4)

0.075

Analog input amplifier common mode input voltage (see Note 5)

NOTES:

2.

V

100

pF

Q

5

10.368
±1.5

AID or D/A conversion rate

20
ITLC32040C,TLC32041C

ITLC320401, TLC32041I

V

0.8

300

Load capacitance at OUT + and/or OUT -, CL

Operating free-air temperature, TA

V

0

70

-40

85

MHz
V
kHz
°C

..
Voltages at analog Inputs and outputs, REF, VCC +, and VCC-, are With respect to ANLG GND. Voltages at digital Inputs and outputs

and VDD are with respect to DGTL GND.
3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for
logic voltage levels and temperature only.
4. The bandpass low-pass switched-capacitor filter response specifications apply only when the switched-capacitor clock frequency
is 288 kHz. For switched-capacitor filter clocks at frequencies other than 288 kHz, the filter response is shifted by the ratio of
switched-capacitor filter clock frequency to 288 kHz.
.
5. This range applies when (IN+ -IN-) or (AUX IN+ - AUX IN-) equals ± 6 V.

"!!1
TEXAS
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4-21

TLC32040C, TLC320401, TLC32041 C, TLC32041I
ANALOG INTERFACE CIRCUITS.
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

electrical characteristics over recommended operating free-air temperature range, Vcc+
Vcc- -5 V, Voo;:: 5 V (unless otherwise noted)

=

total device, MSTR ClK frequency

= 5.184 MHz, outputs not loaded

PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

VDD = 4.75 V,

IOH = -300

VOL

Low-level output voltage

VDD =4.75 V,

IOL=2 mA

ICC+

Supply current from VCC +

ICC-

Supply current from VCC-

=5 V,

MIN

ItA

TYPt

MAX

2.4

V
0.4

TLC3204_C

35

TLC3204 I

40

TLC3204_C

-35

TLC3204 I

-40

IDD

Supply current from VDD

Vref

Internal reference output voltage

~Vref

Temperature coefficient of internal reference voltage

ro

Output resistance at REF

7

fMSTR CLK = 5. t 84 MHz
3

-

UNIT

3.3

V
mA

mA
mA
V

200

ppm/'C

100

kQ

receive amplifier input
PARAMETER

TEST CONDITIONS

MIN

TYPt

MAX

AID converter offset error (filters bypassed)

25

65

mV

AID converter offset error (filters in)

25

65

mV

CMRR

Common-mode rejection ratio at IN +, IN-, or AUX IN +,
AUX IN-

q

Input. resistance at IN+, IN-, or AUX IN+,AUX IN-, REF

See Note 6

UNIT

55

dB

100

kQ

transmit filter output
PARAMETER

TEST CONDITIONS

VOO

Output offset voltage at OUT +, OUT -, (single-ended
relative to ANLG GND)

VOM

Maximum peak output voltage swing across RL at OUT +
or OUT -, (single ended)

RL;" 300 Q,

VOM

Maximum peak output voltage swing between RL at OUT +
and OUT -, (differential output)

RL;" 600 Q

Offset voltage = 0

MIN

TYPt

MAX

15

75

UNIT
mV

±3

V

±6

V

system distortion specifications, SCF clock frequency = 288 kHz
PARAMETER

TEST CONDITIONS

Attenuation of second harmonic of AID
input signal

Single ended

Attenuation of third and higher harmonics
of AID input signal

Single ended

Attenuation of second harmonic of D/A
input signal

Single ended

Attenuation of third and higher harmonics
of D/A input signal

Single ended.

Differential

Differential

Differential

Differential

MIN

70

VI = -0.5 dB to -24 dB referred to Vref,
See Note 7

62

VI = -0.5 dB to -24 dB referred to Vref,
See Note 7

57

VI = -O·dB to ~24 dB referred to Vref,
See Note 7

62

VI = -0 dB to -24 dB referred to Vref,
See Note 7

57

t

TYPt

70
65
65
70
70
65
65

MAX

UNIT
dB

dB

dB

dB

All tYPical values are at TA = 25'C.
NOTES: 6. The test condition is a O-dB.ll, I-kHz input signal with an 8-kHz conversion rate.
7. The test condition VI is a 1-I58§

>58§

VI =-12 dB to -6 dB

58

58

>58§

VI = -18 dB to -12 dB

56

58.

58

VI =-24 dB to -18 dB

50

56

58

VI = -30 dB to -24 dB

44

50

56

VI = -36 dB to -30 dB

38

44

50

VI = -42 dB to -36 dB

32

38

44

VI = -48 dB to -42 dB

26

32

38

VI = -54 dB to -48 dB

20

26

32

MAX

UNIT

dB

D/A channel signal-to-distortion ratio
TEST CONDITIONS
(see Note 7)

PARAMETER

MIN

UNIT

58

VI = -6 dB to 0 dB

D/A channel signal-to-distortion ratio

MAX

VI =-12 dB to-6 dB

58

VI = -18 dB to -12 dB

56

VI = -24 dB to -18 dB

50

VI = -30 dB to -24 dB

44

VI = -36 dB to -30 dB

38

VI = -42 dB to -36 dB

32

VI = -48 dB to -42 dB

26

VI = -54 dB to -48 dB

20

dB

gain and dynamic range
PARAMETER

TYP*

MAX

UNIT

See Note 8

±0.05

±0.15

dB

See Note 8

±0.05

±0.15

dB

TEST CONDITIONS

Absolute transmit gain tracking error
while transmitting into 600 Q

-48-dB to O-dB signal range,

Absolute receive gain tracking error

-48-dB to O-dB signal range,

Absolute gain 01 the ND channel

Signal input is a -0.5-dB,
I-kHz sinewave

Absolute gain 01 the DIA channel

Signal input is a O-dB,
I-kHz sinewave

MIN

0.2

dB

-0.3

dB

power supply rejection and crosstalk attenuation
PARAMETER

VCC + or VCC- supply voltage
rejection ratio, receive channel
VCC + or VCC- supply voltage
rejection ratio, transmit channel
(single ended)

TEST CONDITIONS

I=Ot030kHz
1= 30 kHz to 50 kHz
1 = 0 to 30 kHz
1 = 30 kHz to 50 kHz

Idle channel, supply signal at 200 mV p-p
measured at DR (ADC output)
Idle channel, supply signal at 200 mV p-p
·measured at OUT +

Crosswalk attenuation, transmit-to-receive (single ended)

MIN

TYP*

30
45

MAX

UNIT

dB

30
dB
45
80

dB

t

Av IS the programmable gain 01 the input amplilier.
:j: All typical values are at TA = 25°C.
§ A value> 58 is overrange and signal clipping occurs.
NOTES: 7. The test condition Vin is a I-kHz input signal with an 8-kHz conversion rate (0 dB relative to Vrel). The load impedance for the DAC
is 600 fl.
8. Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 dB relative to Vrel).

~TEXAS

INSTRUMENTS
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TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLASOI4E- SEPTEMBER 1987 - REVISED MAY 1995

delay distortion, SCF clock frequency = 288 kHz ±2%, input (IN+ -IN-) is ±3-V sinewave
Refer to filter response graphs for delay distortion specifications.

TLC32040 and TLC32041 bandpass filter transfer function (see curves),
SCF clock frequency = 288 kHz, ±2%, input (IN+ -IN-) is a ±3-V sinewave (see Note 9)
PARAMETER

TEST CONDITIONS

FREQUENCY
RANGE

MIN

-25

1= 170 Hz
Input signal relerence is 0 dB

UNIT

-42

1= 100 Hz
"Filter gain, (see Note 10)

MAX

300 Hz ::; I::; 3.4 kHz

-0.5

0.5

1=4 kHz

-16

12:4.6 kHz'

-58

dB

low-pass filter transfer function, SCF clock frequency = 288 kHz ±2% (see Note 9)
PARAMETER

TEST CONDITIONS

FREQUENCY
RANGE
I::; 3,4 kHz

Filter gain, (see Note 10)

Output signal relerence is 0 dB

MIN

MAX

-0,5

0.5
-4

1= 3,6 kHz
1=4 kHz

-30

f 2: 4,4 kHz

-58

UNIT

dB

serial port
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

IOH =-300IlA

VOL

Low-level output voltage

IOL=2 mA

II

Input current

MIN

TYPt

MAX

2,4

UNIT
V

0,4

V

±10

IlA

Ci

Input capacitance

15

pF

Co

Output capacitance

15

pF

operating characteristics over recommended operating free-air temperature range, VCC+ = 5 V,
VCC_=-5V, VOO=5V
noise (measurement includes low-pass and bandpass switched-capacitor filters)
PARAMETER

TEST CONDITIONS

Transmit noise
Differential
Receive noise (see Note 11)

MIN

TYPt

MAX

UNIT

500

IlVrms
dBrncO

200

Single ended
DX input = 00000000000000,
constant input code

300

IlVrms

20
Inputs grounded,

t

gain = 1

300
20

475

IlVrms
dBrncO

All tYPical values are at TA = 25'C.
NOTES: 9, The above filter specifications are for a switched-capacitor filter clock range of 288 kHz ±2%. For switched-capacitor filter clocks
at frequencies other than 288 kHz ±2%, the filter response is shifted by the ratio of switched-capacitor filter clock Irequency to
288 kHz,
10. The filter gain outside of the passband is measured with respect to the gain at 1 kHz, The filter gain within the passband is measured
with respect to the average gain within the passband. The passbands are 300 to 3400 Hz and 0 to 3400 Hz for the bandpass and
low-pass filters respectively,
11. The noise is reftered to the input with a buffer gain of one. If the buffer gain is two or four, the noise figure is correspondingly reduced.
The noise is computed by statistically evaluating the digital output 01 the ND converter,

~TEXAS

INSTRUMENTS
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TLC32040C, TLC320401, TLC32041 C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

timing requirements
serial port recommended input signals
MIN

MAX

95

UNIT

tc(MCLK)

Master clock cycle time

trtMCLK)

Master clock rise time

10

ns

tf(MCLK)

Master clock fall time

10

ns

42%

Master clock duty cycle
RESET pulse duration (see Note 12)
tsu(DX)

OX setup time before SCLKJ,

th(DX)

OX hold time after SCLKJ,

ns

58%

800

ns

20

ns
ns

tc(SCLK)/4

serial port - AIC output signals, CL = 30 pF for SHIFT ClK output, CL = 15 pF for all other outputs
MIN
tc(SCLK)

Shift clock (SCLK) cycle time

tf(SCLK)

Shift clock (SCLK) fall time

tr(SCLK)

TYPt

MAX

3

8

ns

8

ns

380

Shift clock (SCLK) rise time

ns

3

Shift clock (SCLK) duty cycle

UNIT

45

55

%

td(CH-FL)

Delay from SCLKt to FSRI FSXI FSDJ,

30

IcJ(CH-FH)

Delay from SCLKt to FSR/FSX/FSDt

35

90

ns

IcJ(CH-DR)

DR valid after SCLKt

90

ns

tQLCH-EU

Delay from SCLKt to EODX/EODRJ, in word mode

90

ns

IcJ(CH-EH)

Delay from SCLKt to EODXI EODRt in word mode

90

ns

If{EODX)

EODX fall time

2

8

ns

2

ns

tf(EODR)

EODR fall time

td(CH-EL)

Delay from SCLKt to EODXI EODRJ, in byte mode

td(CH-EH)

Delay from SCLKt to EODX/EODRt in byte mode

90

ns

td(MH-SL)

Delay from MSTR CLKt to SCLKJ,

65

170

ns

td(MH-SH)

Delay from MSTR CLKt to SCLKt

65

170

ns

8

ns

90

ns

t

Typical values are at TA = 25°C.
NOTE 12: RESET pulse duration is the amount of time that the reset terminal is held below 0.8 V after the power supplies have reached their
recommended values.

~TEXAS

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TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

serial port - Ale output signals
TEST CONDITIONS

MIN

TYPt

MAX

UNIT

tc(SCLK)

Shift clock (SCLK) cycle time

tf(SCLK)

Shift clock (SCLK) fall time

50

ns

tr(SCLK)

Shift clock (SCLK) rise time

50

ns

380

Shift clock (SCLK) duty cycle

ns

45

55

%

52

ns

52

ns

Delay from SCLKi to FSR/FSXJ.

CL = 50 pF

td(CH-FH)

Delay from SCLKi to FSR/FSxi

CL

Id(CH-DR)

DR valid after SCLKi

90

ns

td(CH-EL)

Delay from SCLKi to EODX/EODRJ. in word mode

90

ns

tc!lCH-FL)

= 50 pF

td(CH-EH)

Delay from SCLKi to EODXI EODRt in word mode

90

ns

tf(EODX)

EODX fall time

15

ns

tf(EODR)

EODR fall time

15

ns

td(CH-EL)

Delay from SCLKi to EODXI EODRJ. in byte mode

100

ns

100

ns

td(CH-EH)

Delay from SCLKi to EODXI EODRi in byte mode

Id(MH-SL)

Delay from MSTR CLKi to SCLKJ.

65

ns

tdiMH-SH)

Delay from MSTR CLKt to SCLKt

65

ns

tTypical values are at TA = 25°C.

~TEXAS

INSTRUMENTS
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TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

PARAMETER MEASUREMENT INFORMATION
~te(SCLK)
SHIFTCLK

I 0.8 V
td(CH·FL)~ l4--

I I

I

0.8 V

FSR, FSX

I I
I -+[ 14- td(CH·DR)
I 2V

DR ____

EODR,

td(CH·FL) ~ [4-

td(CH.FH) ~.,.r4-=-_

0.8 V\I..",_ _~\,,..;_ _ _ _ _ _..1'(2 V
I

I
I
I

I

~D~15~_~~__~:---=D8~------~~~D1~~D~0~i----

~
015 014 D13'x:QlD9[)(:::§lD---.....::::::::...:..:::..:=-------(
SU(DX)

DX

I
II

I

I I
td(CH.FH) ~ ~
\I."'_o_.8_V--!I--I
-----\'i';--........~'( 2 V

~

I

I

~
~

Don'! Care

EODX-------~---!4--th-l;~I.,..DX-)----~...;.,t.8t~(CH.EL)

'i;

td(CH·EH)

~J.!4--;"'2V---

(a) BYTE·MODE TIMING

~te(SCLK)

I

SHIFTCLK

I

0.8 V

-.[ j4- td(CH.FL)
• FSX, FSR

DR

:

2V

0.8 V

:

I
I
-+[ l4-- I
2 v....I..i- - - - -

td(CH·FH)

I I

---0-.8'"'V\!.
____

I

I

:).J.-

'I

: -.[ t.- td(CH.D~)

I

I

~D1~5___~~~D~1-~DO~I-~i---tsu(DX)

I

-.I ~

I

Don'! Care

DX

~

!4- th(DX)

j4--.:

td(CH.EL) --+[
14- td(CH.EH)
' ; I i
'j~~0.8V'----/2V

(b) WORD·MODE TIMING

MSTRCLK

I

I

_______..J14).'
.
SHIFTCLK _

I

~td(MH.SL)

td(MH·SH)

'ill'-i_ _ __

(e) SHIFT·CLOCK TIMING

Figure 4. Serial Port Timing

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-27

TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E- SEPTEMBER 1987 - REVISED MAY 1995

PARAMETER MEASUREMENT INFORMATION
ClKOUT

_.J
il~--------------------

......_-...,.,....
,
,

SO,G1

00-015

-------~(

1

Valid

»-.. . .-------~-------

(a) IN INSTRUCTION TIMING

~lKOUT_.J
:I~---------------------1...-_--11....·
1

SN74lS138 Y1

1
1

SN74lS299 ClK

00-015-------~(

Valid

»-.-------------~--

(b) OUT INSTRUCTION TIMING

Figure 5. TMS32010-TLC32040ITLC32041 Interface Timing

~TEXAS

4-28

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

TYPICAL CHARACTERISTICS
AIC TRANSMIT CHANNEL FILTER
10

0.3
Magn'ilude

0

0.25

\

-10

0.2

'Group De ay
-20
III
'tI

.
.
I

'tI

.i3

-30
See NoieB
-40

'2

01

0.15

1\

-50

::E

-60
-70

Ii\

/ r-v.
V-l r-o

0.05

g.

e

o

0

0.05

!!

.~

.

II:

eeNole

-

-80

-90

~ /
j \../

0.1

\
\
\

I

~I
1;'
'ii
c

0.1

Y

ee Nole

0.15
0.2

2

3

4

5

Normalized Frequency _ kHz x SCF clock frequency
288 kHz
NOTES: A.
B.
C.
D.

Maximum relative delay (0 Hz 10600 Hz) = 12511S
Maximum relative delay (600 Hz to 3000 Hz) = ± 50 I1s
Absolute delay (600 Hz to 3000 Hz) = 700 I1S
Test conditions are VCC +. VCC-. and VDD within recommended operating conditions. SCF clock f = 288 kHz ±2% input = ±3-V
sinewave. and TA = 25°C.

Figure 6

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-29

TLC32040C, TLC320401, TLC32041 C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

TYPICAL CHARACTERISTICS
TLC32040 AND TLC32041
RECEIVE CHANNEL FILTER
10

0.35

Magnit~de

S~NoteA

0

0~3

0.25

-10

\

-20
"C

.
:e
.
I

"C

-30
-40

c

DI

0.2

\

III

\
\
\

Group Delay

-50

'\ 7 ,\ /\

:!5

-60

V, /\ l/ V

-70

L

1\

ee Note

-80
See NoteC -

-90

,

\

~I

t;0.15 "ii
c
0.1 §-

e

0.05

o

c;
.:!:
~

II:

0.05
0.1
0.15

4
3
5
SCF clock frequency
Normalized Frequency - kHz x - - - 288 kHz
0

2

I

NOTES: A.
B.
C.
D.

Maximum relative delay (200 Hz to 600 Hz) = 3350 Jls
Maximum relative delay (600 Hz to 3000 Hz) = ± 50 Jls
Absolute delay (600 Hz to 3000 Hz) = 1230 Jls
Test conditions are VCC+. VCC-. and VDD within recommended operating conditions. SCF clock f = 21\8 kHz ±2%. input = ±3·V
sinewave. and TA = 25°C.

Figure 7

~TEXAS

INSTRUMENTS
4-30

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

TYPICAL CHARACTERISTICS
AID SIGNAL-TO-DISTORTION RATIO

AID GAIN TRACKING
(GAIN RELATIVE TO GAIN
AT O-dB INPUT SIGNAL)

vs

INPUT SIGNAL
80

70

0.5
l-kHz Input Signal With an
8-kHz Conversion Rate
I

Gain=4X
60

50
40

0.4

~=lX

.....

~

"V V

l·kHz Input Signal
8-kHz Conversion Rate

0.3

0.2

III
"0
I

V

0.1

g>

o

:iii

~c

30

....

-0.1

"iii
C!l

-0.2

20
-0.3
10

o

-50

-0.4

-40

-30

-20

-10

o

-0.5
-50

10

-40

Input Signal Relative to Vref - dB

-30

-20

-10

o

10

Input Signal Relative to Vref - dB

Figure 8

Figure 9
DIA GIAN TRACKING

DIA CONVERTER SIGNAL-TO-DISTORTION RATIO

vs

vs

(GAIN RELATIVE TO GAIN
AT 0 OdB INPUT SIGNAL)

INPUT SIGNAL

100
90
III

80

o

70

"0
I

~c

l-kHz'lnput Si~nal int~ 600 a
8-kHz Conversion Rate

Si~nal

l-kHz lin put
into'600
8-kHz Conversion Rate

a

+---+---1

0.61---+--+---+---+----1---1

60

/

o

~

1.0
0.8

50

-

k"'"

"0
I

0.21---+--+---+---+----1---1

'"c

..

:iii

~c

./V

'Iii

0.41---+--+---+---+----1---1

III

0~--~---r---+----~--+---4

- 0.2 1---+--+---+---+----1---1

is

40

"iii
c

30

iii

20

-0.61---+--+---+---+----1---1

10

-0.8 1---+--+---+---+----1---1

~

'"

o

-50

'a;
C!l

-0.41---+--+---+---+----1---1

-1~

-40

-30

-20

-10

o

10

__

-50

~

-40

Input Signal Relative to Vref - dB

Figure 10

__

~~

__

~

__

~

____

~

-20
-10
o
Input Signal Relative to Vref - dB

-30

__

~

10

Figure 11

NOTE: Test conditions are VCC+. VCC-. VOO and within recommended operating conditions set clock f = 288 kHz ±2%. and TA = 25°C.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-31

TLC32040C, TLC320401, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
.
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

TYPICAL CHARACTERISTICS
ATTENUATION OF THIRD HARMONIC OF AJD INPUT

ATTENUATION OF SECOND HARMONIC OF AJD INPUT

100

..,m
I

'c"0

E
01

90
80

vs

vs

INPUT SIGNAL

INPUT SIGNAL
100

1\
I ~
,--II

'-i"'"

70

"

..,m

./

I

'c"o

80
70

E
01

60

'E

50

..,J:

60

0

.

50

'0

40

'0

~

30

o
~

30

~

20

~

20

I:

en"

J:

~

:J
I:

/ ' r'-J
\

'"

40

:J
I:

1·kHz Input Signal
8-kHz Conversion Rate

10

o

-50

I

I

I

-40

-30

-20

10

o
-10

o

-50

10

-40

ATTENUATION OF SECOND HARMONIC OF D/A INPUT

90

I

80

'c"o
E

70

..,

60

~

vs
INPUT SIGNAL

-"

100

.-

90

..,
'c"o

m

-

I

50

'E

50

40

'0

40

~

o

:;:J

30

~

20

I:

~I:

~

30
20
10

10

o
-50

. /f---"""

I:

I:

o

70
60

J:

Si~nal

1·kHz Iinput
intol 600. n
8·kHz Conversion Rate

80

E
01

I:

'0

10

ATTENUATION OF THIRD HARMONIC OF D/A INPUT

INPUT SIGNAL

... . /

o

-10

vs
1·kHz Iinput Si~nal intol 600 n
8·kHz Conversion Rate

t;;

J:

-20

Figure 13

Figure 12

..,m

-30

Input Signal Relative to Vref - dB

Input Signal Relative to Vref - dB

100

~ ~

I:

I:

0

1·kHz Input Signal
8·kHz Conversion Rate

90 -

-40

-30

-20

-10

o

o
10

-50

-40

Input Signal Relative to Vref - dB

Figure 14

-30

-20

-10

_0

10

Input Signal Relative to Vref .:.. dB

Figure 15

NOTE: Test conditions are VCC+, VCC-, and VDD within recommended operating conditions set clock f = 288 kHz ±2%, and TA = 25°C.

~TEXAS .
INSTRUMENTS
4-32

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32040C, TLC320401, TLC32041 C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995

APPLICATION INFORMATION

cr-

TMS32010
I--

I

OEN

L

G1
A

A1/PA1

B

Y1 YO

C
SN74LS138

so

\

WE
CLKOUT
INT

\

~

ox
TLC32040/
TLC32041

CLK< I--

A-H

SR

~

~

SN74LS299
Sl
-<32
SO
<31

00-015

V

G1

08-015

bD
00-015

SN74LS299
Sl
QH
G2

AO/PAO
A2/PA2

FSX

C2

QH

CLK<

~
~

00-07

\

SHIFTCLK

A-H

SR

---~n

~
C1
Q 10

OR

MSTRCLK
EOOX

Figure 16. TMS32010-TLC32040ITLC32041 Interface Circuit

"'TEXAS

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-33

TLC32040C, TLC320401, TLC32041 C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLASOI4E- SEPTEMBER 1987 - REVISED MAY 1995

APPLICATION INFORMATION
TMS32020/C25

TlC32040ITlC32041

ClKOUT 1--<1111----1 MSTR ClK
FSX

FSX

ox

ox

FSR

FSR

DR

DR

ClKR
ClKX

T

VCC+~--LI(-----------'---5V

REF

*'

1\

;::r: C

cl

ANlGGNO~~~~-'~---'

BAT42t+ C
-5 V
VCC
VOO ~-------.>- 5 V

SHIFT ClK

*

--l

OGTl GNO

C = 0.2

t

~F,

0.1 ~F

Ceramic

Thomson Semiconductors

Figure 17. AIC Interface to the TMS32020/C25 Showing Decoupling Capacitors and Schottky Diodet
VCC

3 V Output

0.01 ~F

Tl431

For:

0.1 f.1F Ceraminc

VCC = 12 V, R = 7200 Q
VCC = 10 V, R = 5600 Q
VCC=5V, R= 1600Q

Figure 18. External Reference Circuit For TLC32045

~TEXAS

4-34

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
MAY 1995

•

14-Bit Dynamic Range ADC andDAC

•
•

2's Complement Format
Variable ADC and DAC Sampling Rate Up
to 19,200 Samples per Second

•
•

•

•

Jt OR N PACKAGE
(TOP VIEW)

NU
RESET
EODR
FSR
DR
MSTR ClK

Switched-Capacitor Antialiasing Input Filter
and Output-Reconstruction Filter
Serial Port for Direct Interface to
TMS(SMJ)320C17, TMS(SMJ)32020,
TMS(SMJ)320C25,
and TMS320C30 Digital Signal Processors

Serial Port Interface to SN74(54)299
Serial-to-Parallel Shift Register for Parallel
Interface to TMS(SMJ)3201 0,
TMS(SMJ)320C15, or Other Digital
Processors

•

Internal Reference for Normal Operation
and External Purposes, or Can Be
Overridden by External Reference

•

CMOS Technology

description
The TLC32044 and TLC32045 are complete
analog-to-digital and digital-to-analog input and
output systems on single monolithic CMOS chips.
The TLC32044 and TLC32045 integrate a
bandpass switched-capacitor antiaJiasing input
filter, a 14-bit-resolution AID converter, four
microprocessor-compatible serial port modes, a
14-bit-resolution D/A converter, and a low-pass
switched-capacitor output-reconstruction filter.
The devices offer numerous combinations of
master clock input frequencies and conversion/
sampling rates, which can be changed via digital
processor control.

=~~~~I;T~~~o~1: sl=t:r:~~si~e~%:~!r~~ g: le::~~~~r!~a~

standard warranty. Production processing does not necessarily include
testing of all parameters.

3
4
5
6
7

Voo
REF
DGTlGND
SHIFTClK
EODX
DX
WORD/BYTE
FSX

Synchronous or Asynchronous ADC and
DAC Conversion Rates With Programmable
Incremental ADC and DAC Conversion
Timing Adjustments

t

NU
NU
IN+
INAUXIN+
AUX INOUT+
OUT-

2

8
9

Vcc+
VccANlG GND
ANlG GND
NU
NU

10
11
12
13
14

Refer to the mechanical data for the JT package.
FK OR FN PACKAGE
(TOP VIEW)

4

3 2

1 28 27 26

DR
MSTRClK

5
6

24

VOO

7

23

REF
DGTlGND
SHIFTClK
EO OX

8

22

9

21

10

20

25

11
19
12131415161718

Ix

IUJ

IX

::l ::l 0

IN-

OUT+
OUT-

VCC+
VCC-

0

O~(/)ZZZz

>-u..
~
a:

o

$

(!}(!)
(!}(!)
...J...J

ZZ

««

NU - Nonusable; no external connection should be made to
these terminals (see Table 2).

-!!1

Copyright © 1995. Texas Instruments Incorporated

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4--35

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

AVAILABLE OPTIONS
PACKAGE
TA

PLASTIC CHIP
CARRIER
(FN)

O°C

to 70°C

-20°C

to 85°C

-40°C

to 85°C

PLASTIC DIP

CERAMIC DIP

CHIP CARRIER

(N)

(J)

(FK)

TLC32044MJ

TLC32044MFK

TLC32044CFN

TLC32044CN

TLC32045CFN

TLC32045CN

TLC32044EFN
TLC320441N
TLC320451N

-55°C to 125°C

description (continued)
Typical applications for the TLC32044 and TLC32045 include speech encryption for digital transmission,
speech recognition/ storage systems, speech synthesis, modems (7.2-, B-, 9.6-, 14.4-, and 19.2-kHz sampling
rate), analog interface for digital signal processors (OSPs), industrial process control, biomedical
instrumentation, acoustical signal processing, spectral analysis, data acquisition, and instrumentation
recorders. Four serial modes, which allow direct interface to theTMS(SMJ)320C17, TMS(SMJ)32020,
TMS(SMJ)320C25, and TMS(SMJ)320C30 digital signal processors, are provided. Also, when the transmit and
receive sections of the analog interface circuit (AIC) are operating synchronously, it will interface to two
SN74(54)299 serial-to-parallel shift registers. These serial-to-parallel shift registers can then interface in
parallel to the TMS(SMJ)32010, TMS(SMJ)320C15, and other digital signal processors, or external FIFO
circuitry. Output data pulses are emitted to inform the processor that data transmission is complete or to allow
the OSP to differentiate between two transmitted bytes. A flexible control scheme is provided so that the
functions of the TLC32044 or TLC32045 can be selected and adjusted coincidentally with signal processing via
software control.
The anti aliasing input filter comprises eighth-order and fourth-order CC-type (Chebyshev/elliptic transitional)
low-pass and high-pass filters, respectively. The input filter is implemented in switched-capacitor technology
and is preceded by a continuous time filter to eliminate any possibility of aliasing caused by sampled data
filtering. When only low-pass filtering is desired, the high-pass filter can be switched out of the signal path. A
selectable, auxiliary, differential analog input is provided for applications where more than one analog input is
required.
The NO and D/A architectures ensure no missing codes and monotonic operation. An internal voltage reference
is provided to ease the design task and to provide complete control over the performance of the TLC32044 or
TLC32045. The internal voltage reference is brought out to a terminal and is available to the designer. Separate
analog and digital voltage supplies and grounds are provided to minimize noise and ensure a wide dynamic
range. Also, the analog circuit path contains only differential circuitry to keep noise to an absolute minimum.
The only exception is the OAC sample and hold, which utilizes pseudo-differential circuitry.
The output-reconstruction filter is an eighth-order CC-type (Chebyshev/elliptic transitional low-pass filter)
followed by a second-order (sin xlix correction filter and is implemented in switched-capacitor technology. This
filter is followed by a contil)uous-time filter to eliminate images of the digitally encoded signal. The on-board
(sin xlix correction filter can be switched out of the signal path using digital signal processor control, if desired.
The TLC32044C and TLC32045C are characterized for operation from O°C to 70°C. The TLC32044E is
characterized for operation from -20°C to B5°C. The TLC320441 and TLC320451 are characterized for
operation from -40°C to B5°C. The TLC32044M is characterized for operation from -55°C to 125°C.

-!!1 TEXAS

INSTRUMENTS
4-36

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

functional block diagram
Filter

IN+ -'--a..........

I - - -...... M

IN- ---t----.........."

SERIAL
PORT

AID

U
X

AUX IN + -'--a..........

DR

AUX IN - -f"-II>-Lo"
Receive Section

r-I
---------------------1

EODR

--..,I

Internal
Voltage
Reference

Filter

I
I
I
IL __
--...I

OUT + ~--J''''''''~
OUT - ....-

D/A.

..........1--;

MSTERCLK
SHIFTCLK
WORD/BYTE
OX
FSX
EODX

Transmit Section

VCC+ VCC- ANLG DTGL VDD
GND GND (Digital)

REF

Terminal Functions
TERMINAL
NAME
ANLGGND

NO.

I/O

17,18

DESCRIPTION
Analog ground return for all internal analog circuits. Not internally connected to DGTl GND.

AUX IN+

24

I

Noninverting auxiliary analog input stage. AUX iN + can be switched into the bandpass filter and AID
converter path via software control. If the appropriate bit in the control register is a 1, the auxiliary inputs
will replace the IN+ and IN- inputs. If the bit is a 0, the IN+ and IN- inputs will be used (see the AIC DX
data word format section).

AUXIN-

23

I

DGTlGND

9

DR

5

0

Data receive. DR is used to transmit the ADC dutput bits from the AIC to the TMS320 (SMJ320) serial port.
This transmission of bits from the AIC to the TMS320 (SMJ320) serial port is synchronized with the SHIFT
ClKsignal.

DX

12

I

Data transmit. DX is used to receive the DAC input bits and timing and control information from the TMS320
(SMJ320). This serial transmission from the TMS320 (SMJ320) serial port to the AIC is synchronized with
the SHIFT ClK signal.

EODR

3

0

End of data receive. (See the WORD/BYTE description and Serial Port Timing diagram.) During the
word-mode timing, EODR is a low-going pulse that occurs immediately after the 16 bits of AID information
have been transmitted from the AIC to the TMS320 (SMJ320) serial port. EODR can be used to interrupt
a microprocessor upon completion of serial communications. Also, EODR can be used to strobe and enable
external serial-to-parallel shift registers, latches, or external FIFO RAM, and to facilitate parallel data bus
communications between the AIC and the serial-to-parallel shift registers. During the byte-mode timing,
EODR goes low after the first byte has been transmitted from the AIC to the TMS320 (SMJ320) serial port
and is kept low until the second byte has been transmitted. The DSP can use this low-going signal to
differentiate between the two bytes as to which is first and which is second. EODR does not occur after
secondary communication.

Inverting auxiliary analog input (see the above AUX IN + description).
Digital ground for all internal logic circuits. Not internally connected to ANlG GND.

-!!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-37

TlC32044C, TlC32044E, TlC320441, TlC32044M, TlC32045C, TlC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F-MARCH 1988-REVISED MAY 1995

Terminal Functions (continued)
TERMINAL
NAME

NO.

I/O

DESCRIPTION

EODX

11

0

End of data transmit. (See the WORD/BYTE description and Serial Port Timing diagram.) During the
word-mode timing, EODX is a low-going pulse that occurs immediately after the 16 bits of D/A converter
and control or register information have been transmitted from the TMS320 (SMJ320) serial port to the AIC.
EODX can be used to interrupt a microprocessor upon the completion of serial communications. Also,
EODX can be used to strobe and enable external serial-to-parallel shift registers, latches, or an external
FIFO RAM, and to facilitate parallel data-bus communications between the AIC and the serial-to-parallel
shift registers. During the byte-mode timing, EODX goes low after the first byte has been transmitted from
the TMS320 (SMJ320) serial port to the AIC and is kept low until the second byte has been transmitted. The
DSP can use this low-going' signal to differentiate between the two bytes as to which is first and which is
second.

FSR

4

0

Frame sync receive. In the serial transmission modes, which are described in the WORD/BYTE description,
FSR is held low during bit transmission. When FSR goes low, the TMS320 (SMJ320) serial port begins
receiving bits from the AIC via DR of the AIC. The most significant DR bit is present on OR before FSR goes
low. (See Serial Port Timing and Internal Timing Configuration diagrams.) FSR does not occur after
secondary communications.

FSX

14

0

Frame sync transmit. When FSX goes low, the TMS320 (SMJ320) serial port begins transmitting bits to the
AIC via OX of the AIC. In all serial transmission modes, which are described in the WORD/BYTE description,
FSX is held low during bit transmission (see Serial Port Timing and Internal Timing Configuration diagrams).

IN+

26

I

IN-

25

I

Inverting input to analog input amplifier stage

MSTR ClK

6

I

Master clock. MSTR ClK is used to derive all the key logic signals of the AIC, such as the shift clock, the
switched-capacitor filter clocks, and the AID and D/A timing signals. The Internal Timing Configuration
diagram shows how these key signals are derived. The frequencies of these key signals are synchronous
submultiples of the master clock frequency to eliminate unwanted aliasing when the sampled analog signals
are transferred between the switched-capacitor filters and the AID and D/A converters (see the Internal
Timing Configuration diagram).

OUT+

22

0

Noninverting output of analog output power amplifier. OUT+ can drive transformer hybri~s or
high-impedance loads directly in either a differential or a single-ended configuration.

OUT-

21

0

Inver/ing output of analog output power amplifier. OUT-is functionally identical with and complementary
to OUT +.

REF

8

I/O

Internal voltage reference. An internal reference voltage is brought out on REF. An external voltage
reference can also be applied to REF.

RESET

2

I

Reset function. RESET is provided to initialize the TA, TA', TB, RA, RA', RB, and control registers. A reset
initiates serial communications between the AIC and DSP. A reset initializes all AIC registers including the
control register. After a negative-going pulse on RESET, the AIC registers are initialized to provide an a-khz
data conversion rate for a 5.184-MHz master clock input signal. The conversion rate adjust registers, TA'
and RA', are reset to I.The control register bits are reset as follows (see AIC DX data word format section):
d9 = I, d7 = I, d6 = I, d5 = I, d4 = 0, d3 = 0, d2 = 1.
This initialization allows normal serial-port commu~ication to occur between the AIC and OSP.

SHIFTClK

10

0

Shift clock. SHIFT ClK is obtained by dividing the master clock signal frequency by four. SHIFT ClK is used
to clock the serial data transfers of the AIC, described in the WORD/BYTE description below (see the Serial
Port Timing and Internal Timing Configuration diagrams).

Noninverting input to analog input amplifier stage

VDD

7

Digital supply voltage, 5 V ±5%

VCC+

20

Positive analog supply voltage, 5 V ±5%

VCC-

19

Negative analog supply voltage, -5 V ±5%

~TEXAS

INSTRUMENTS

4-38

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

Terminal Functions (continued)
TERMINAL
NAME

NO.

WORD/BYTE

13

I/O

DESCRIPTION

I

Used in conjunction with a bit in the control register, WORD/BYTE is used to establish one of four serial
modes. These four serial modes are described below.

AIC transmit and receive sections are operated asynchronously.
The following description applies when the AIC is configured to have asynchronous transmit and receive
sections. If the appropriate data bit in the control register is a 0 (see the AIC DX data word format section),
the transmit and receive sections are asynchronous.
Serial port directly interfaces with the serial port of the DSP and communicates in two
L
8-bit bytes. The operation sequence is as follows (see Serial Port Timing diagrams).
1. FSX or FSR is brought low.
2. One 8-bit byte is transmitted or one 8-bit byte is received.
3. EODX or EODR is brought low.
4. FSX or FSR emits a positive frame-sync pulse that is four shift clock cycles wide.
5. One 8-bit byte is transmitted or one 8-bit byte is received.
6. EODX or EODR is brought high.
7. FSX or FSR is brought high.
H
Serial port directly interfaces with the serial ports of the TMS(SMJ)32020, TMS(SMJ)320C25, or
TMS(SMJ)320C30, and communicates in one 16-bit word. The operation sequence is as follows
(see Serial Port Timing diagrams):
1. FSX or FSR is brought low.
2. One 16-bit word is transmitted or one 16-bit word is received.
3. FSX or FSR is brought high.
4. EODX or EODR emits a low-going pulse.

AIC transmit and receive sections are operated synchronously.
If the appropriate data bit in the control register is I, the transmit and receive sections are configured to be
synchronous. In this case, the bandpass switched-capacitor filter and the AID conversion timing are derived
from the TX counter A, TX counter B, and TA, TA', and TB registers, rather than the RX counter A, RX counter
B, and RA, RA', and RB registers. In this case, the AIC FSX and FSR timing are identical during primary
data communication; however, FSR is not asserted during secondary data communication since there is
no new AID conversion result. The synchronous operation sequences are as follows (see Serial Port Timing
diagrams).
Serial port directly interfaces with the serial port of the DSP and communicates in two 8-bit
L
bytes. The operation sequence is as follows (see Serial Port Timing diagrams):
1. FSX and FSR are brought low.
2. One 8-bit byte is transmitted and one 8-bit byte is received.
3. EODX and EODR are brought low.
4. FSX and FSR emit positive frame-sync pulses that are four shift clock cycles wide.
5. One 8-bit byte is transmitted and one 8-bit byte is received.
6. EODX and EODR are brought high.
7. FSX and FSR are brought high.
Serial port directly interfaces with the serial port of the TMS(SJM)32020, TMS(SMJ)320C25, or
H
TMS320C30, and communicates in one 16-bit word. The operation sequence is as follows (see
Serial Port Timing diagrams):
1. FSX and FSR are brought low.
2. One 16-bit word is transmitted and one 16-bit word is received.
3. FSX and FSR are brought high.
4. EODX or EODR emit low-going pulses.
Since the transmit and receive sections of the AIC are now synchronous, the AIC serial port with additional
NOR and AND gates interface to two SN74(54)299 serial-to-parallel shift registers. Interfacing the Ale to
the SN74(54)299 shift register allows the Ale to interface to an external FIFO RAM and facilitates parallel,
data bus communications between the Ale and the digital signal processor. The operation sequence is the
same as the above sequence (see Serial Port Timing diagrams).

~TEXAS

INSTRUMENTS
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4-39

TlC32044C, TLC32044E, TlC320441, TlC32044M, TlC32045C, TlC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

PRINCIPLES OF OPERATION
analog input
Two sets of analog inputs are provided. Normally, the IN+ and IN- input set is used; however, the auxiliary input
set., AUX IN + and AUX IN-, can be used if a second input is required. Each input set can be operated in either
differential or single-ended modes, since sufficient common-mode range and rejection are provided. The gain
for the IN +, IN-, AUX IN +, and AUX IN- inputs can be programmed to be either 1, 2, or 4 (see Table 2). Either
input circuit can be selected via software control. It is important to note that a wide dynamic range is assured
by the differential internal analog architecture and by the separate analog and digital voltage supplies and
grounds.

AID bandpass filter, AID bandpass filter clocking, and AID conversion timing
The AID high-pass filter can be selected or bypassed via software control. The frequency response of this filter
is presented in the following pages. This response results when the switched-capacitor filter clock frequency
is 288 kHz and the AID sample rate is 8 kHz. Several possible options can be used to attain a 288-kHz
switched-capacitor filter clock. When the filter clock frequency is not 288 kHz, the low-pass filter transfer function
is frequency scaled by the ratio of the actual clock frequency to 288 kHz. The ripple I;>andwidth and 3-dB
low-frequency roll-off points of the high-pass section are 150 Hz and 100 Hz, respectively. However, the
high-pass section low-frequency roll-off is frequency scaled by the ratio of the AID sample rate to 8 kHz.
The internal timing configuration and Ale DX data word format sections of this data sheet indicate the many
options for attaining a 288-kHz bandpass switched-capacitor filter clock. Thl3se sections indicate that the RX
counter A can be programmed to give a 288-kHz bandpass switched-capacitor filter clock for several master
clock input frequencies.
The AID conversion rate is then attained by frequency dividing the 288-kHz bandpass switched-capacitor filter
clock with the RX counter B. Unwanted aliasing is prevented because the AID conversion rate is an integral
submultiple of the bandpass switched-capacitor filter sampling rate, and the two rates are synchronously
locked.

AID converter performance specifications
Fundamental performance specifications for the AID converter circuitry are presented in the AID converter
operating characteristics section of this data sheet. The realization of the AID converter circuitry with
switched-capacitor techniques provides an inherent sample-and-hold.

analog output
The analog output circuitry is an analog output power amplifier. Both noninverting and inverting amplifier outputs
are brought out. This amplifier can drive transformer hybrids or low-impedance loads directly in either a
differential or single-ended configuration.

DIA low-pass filter, DIA low-pass filter clocking, and DIA conversion timing
The frequency response of this filter is presented in the following pages. This response results when the
low-pass switched-capacitor filter clock frequency is 288 kHz. Like the AID filter, the transfer function of this filter
is frequency scaled when the clock frequency is not 288 kHz. A continuous-time filter is provided on the output
of the (sin x)/x correction filter to eliminate the periodic sample data signal information, which occurs at multiples
of the 288-kHz switched-capacitor filter clock. The continuous time filter also greatly attenuates any
switched-capacitor clock feedthrough.

~TEXAS

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INSTRUMENTS
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TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

PRINCIPLES OF OPERATION

D/A low-pass filter, D/A low-pass filter clocking, and D/A conversion timing (continued)
The D/A conversion rate is attained by frequency dividing the 288-kHz switched-capacitor filter clock with TX
Counter B. Unwanted aliasing is prevented because the D/A conversion rate is an integral submultiple of the
switched-capacitor low-pass filter sampling rate, and the two rates are synchronously locked.

asynchronous versus synchronous operation
If the transmit section of the AIC (low-pass filter and DAC) and receive section (bandpass filter and ADC) are
operated asynchronously, the low-pass and bandpass filter clocks are independently generated from the master
clock signal. Also, the D/A and AID conversion rates are independently determined. If the transmit and receive
sections are operated synchronously, the low-pass filter clock drives both low-pass and bandpass filters. In
synchronous operation, the AID conversion timing is derived from, and is equal to, the D/A conversion timing
(see description of the WORD/BYTE in the Terminal Functions table.)

D/A converter performance specifications
Fundamental performance specifications for the D/A converter circuitry are presented in the D/A converter
operating characteristics section of the data sheet. The D/A converter has a sample-and-hold that is realized
with a switched-capacitor ladder.

system frequency response correction
The (sin x)/x correction for the D/A converter zero-order sample-and-hold output can be provided by an
on-board second-order (sin x)/x correction filter. This (sin x)/x correction filter can be inserted into or deleted
from the signal path by digital signal processor control. When inserted, the (sin x)/x correction filter follows the
switched-capacitor low-pass filter. When the TB register (see Internal Timing Configuration section) equals 36,
the correction results of Figures 11 and 12 can be obtained.
The (sin x)/x correction can also be accomplished by deleting the on-board second-order correction filter and
performing the (sin x)/x correction in digital signal processor software. The system frequency response can be
corrected via DSP software to ±0.1-dB accuracy to a band edge of 3000 Hz for all sampling rates. This correction
is accomplished with a first-order digital correction filter, which requires only seven TMS320 (SMJ320)
instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of only 1.1 %
and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the (sin x)/xcorrection section for more details).

serial port
The serial port has four possible modes that are described in detail in the Terminal Functions table. These
modes are briefly described below and in the functional description for WORD/BYTE.
•

The transmit and receive sections are operated asynchronously, and the serial port interfaces directly
with the DSP.

•

The transmit and receive sections are operated asynchronously, and the serial port interfaces directly
with the TMS(SMJ)32020, TMS(SMJ)320C25, and the TMS(SMJ)320C30.

•

The transmit and receive sections are operated synchronously, and the serial port interfaces directly
with the DSP.

•

The transmit and receive sections are operated synchronously, and the serial port interfaces directly
witli the TMS(SMJ)32020, TMS(SMJ)320C25, TMS(SMJ)320C30, or two SN74(54)299 serial-toparallel shift registers, which can then interface in parallel to the TMS(SMJ)3201 0, TMS(SMJ)320C15,
and SMJ320E15 to any other digital signal processor or to external FIFO circuitry.

~TEXAS

INSTRUMENTS
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4-41

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

PRINCIPLES OF OPERATION
operation of TLC32044 or TLC32045 with internal voltage reference
The internal reference eliminates the need for an external voltage reference and provides overall circuit cost
reduction. Thus, the internal reference eases the design task and provides complete control over device
performance. The internal reference is brought out to a terminal and is available to the designer. To keep the
amount of noise on the reference. signal to a minimum, an external capacitor can be connected between REF
and ANLG GNO.

operation of TLC32044 or TLC32045 with external voltage reference
REF can be driven from an external reference circuit. This external circuit must be capable of supplying
250 IlA and must be adequately protected from noise such as crosstalk from the analog input.

reset
A reset function is provided to initiate serial communications between the AIC and OSP and to allow fast,
cost-effective testing during manufacturing. The reset function initializes all AIC registers, including the control
register. After a negative-going pulse on RESET, the AIC is initialized. This initialization allows normal serial 'port
communications activity to occur between AIC and OSP (see AIC OX data word format section).

loop back
This feature allows the user to test the circuit remotely. In loopback, OUT + and OUT-are internally connected
to the IN+ and IN-. Thus, the OAC bits (d15 to d2), which are transmitted to OX, can be compared with the AOC
bits (d15 to d2), which are received from DR. An ideal comparison would be that the bits on DR equal the bits
on OX. However, there are some difference in these bits due to the AOC and OAC output offsets. The loopback
feature is implemented with digital signal processor control by transmitting the appropriate serial port bit to the
control register (see AIC OX data word format section).

~TEXAS

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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

INTERNAL TIMING CONFIGURATION

r-----------------,

MSTR ClK
5.184MHz(1)
10.368 MHz (2) L

I

Divideby4
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .J

SHIFTClK
1.296 MHz (1)
2.592 MHz (2)

-----------------------------,
Optional External Circuitry
for Full Duplex Modems

Divide by 2

- - - - - - - - - - ,I
Ir - - - -153.6-kHz
I
Clock (1)
Commercial
I
I
External
I
Front-End
I
I
Full-Duplex
I
I
Split-Band
I
I
_ _ _ _ .JI
Filterst
I~ _ _ _ _ _ _ _ _ _ _ _

dO, d1 = 0,0
dO,d1 =1,1*

dO, d1 = 0,1
dO,d1 =1,0*

TXCounter A
ITA= 9 (1)]
ITA = 18 (2)]
(6 bits)

576-kHz
Pulses

TX Counter B
ITB = 40; 7.2 kHz]
ITB = 36; 8.0 kHz]
ITB = 30; 9.6 kHz]
ITB = 20; 14.4 kHz]
ITB = 15; 19.2 kHz]

Divide by 2

dO, d1 = 0,0
dO, d1 = 1,1*

~

dO, d1 = 0,1
dO, d1 = 1,0*

low-Passl
(sin xix
Correction
Switched
Capacitor Filter
ClK = 288-kHz
Square Wave

D/A
Conversion
Frequency

low-Pass
Switched
Capacitor Filter
ClK = 288-kHz
Square Wave

AID

RX Counter B
Conversion
IRB = 40; 7.2 kHz]
Frequencyl
RX Counter A
IRB= 36; 8.0 kHz]
High-Pass
IRA = 9 (1)]
IRB = 30; 9.6 kHz]
Switched
576-kHz
IRB = 20; 14.4 kHz]
Capacitor
IRA = 18 (2)]
(6 bits)
Pulses
IRB = 15; 19.2 kHz]
Filter ClK
______________________________
J

t Split-band filtering can alternatively be perfor~ed after the analog input function via software in the TMS(SMJ)320.
* These control bits are described in the AIC DX data word format section.
NOTE: Frequency 1 (20.736 MHz) is used to show how 153.6 kHz (for a commercially available modem split-band filter clock), popular speech
and modem sampling signal frequencies, and an internal 288-kHz switched-capacitor filter clock can be derived synchronously and as
submultiples of the crystal oscillator frequer]CY. Since these derived frequencies are synchronous submultiples of the crystal frequency,
aliasing does not occur as the sampled analog signal passes between the analog converter and switched-capacitor filter stages.
Frequency 2 (41.472 MHz) is used to show that the AIC can work with high-frequency signals, which are used by high-speed digital signal
processors.

~TEXAS

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TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

explanation of internal timing configuration
All of the internal timing of the AIC is.derived from the high-frequency clock signal that drives the master clock
input. The shift clock signal, which strobes the serial port data between the AIC and DSP, is derived by dividing
the master clock input signal frequency by four.
Low-pass:
SCF Clock Frequency (D/A or AID path)
C

=2

Master Clock Frequency
x Contents of Counter A

.
F
_ SCF Clock Frequency (D/A or AID path)
onverslon requency Contents of Counter B

High-pass:
SCF Clock Frequency (AID Path) = AID Conversion Frequency
Frequency
Sh I'ft CI ock F requency = Master Clock
4
TX counter A and TX counter B, which are driven by the master clock, determine the D/A conversion timing.
Similarly, RX counter A and RX counter B determine the NO conversion timing. In order for the low-pass
switched-capacitor filter in the D/A path to meet its transfer function specifications; the frequency of its clock
input must be 288 kHz. If the clock frequency is not 288 kHz, the filter transfer function frequencies are
frequency-scaled by the ratios of the clock frequency to 288 kHz. Thus, to obtain the specified filter response,
the combination of master clock frequency and TX counter A and RX counter A values must yield a 288-kHz
switched-capacitor clock signal. This 288-kHz clock signal can then be divided by the TX counter B to establish
the D/A conversion timing.
The transfer function of the bandpass switched-capacitor filter in the NO path is a composite of its high-pass
and low-pass section transfer functions. The high-frequency roll-off of the low-pass section meets the bandpass
filter transfer function specification when the low-pass section SCF is 288 kHz. Otherwise, the high-frequency
roll-off will be frequency-scaled by the ratio of the high-pass section's SCF clock to 288 kHz. The low-frequency
roll-off of the high-pass Section meets the bandpass filter transfer function specification when the AID
conversion rate is 8 kHz. Otherwise, the low-frequency roll-off of the high-pass section is frequency-scaled by
the ratio of the NO conversion rate to 8 kHz.
TX counter A and TX counter B are reloaded every D/A conversion period, while RX counter A and RX counter
B are reloaded every NO conversion period. The TX counter Band RX counter B are loaded with the values
in the TB and RB registers, respectively. Via software control, the TX counter A can be loaded with either the
TA register, the TA register less the TA' register, or the TA register plus the TA' register. By selecting the TA
register less the TA' register option, the upcoming conversion timing occurs earlier by an amount of time that
equals TA' times the signal period of the master clock. By selecting the TA register plus the TA' register option,
the upcoming conversion timing occurs later by an amount of time that equals TA' times the signal period of the
master clock. The D/A conversion timing can be advanced or retarded. An identical ability to alter the AID
conversion timing is provided. In this case, however, the RX counter A can be programmed via software control
with the RA register, the RA register less the RA' register, or the RA register plus the RA' register.
The ability to advance or retard conversion timing is particularly useful for modem applications. This feature
allows controlled changes in the NO and D/A conversion timing. This feature can be used to enhance
signal-to-noise performance, to perform frequency-tracking functions, and to generate nonstandard modem
frequencies.

~TEXAS'

INSTRUMENTS
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SLASO.17F - MARCH 1988 - REVISED MAY 1995

explanation of internal timing configuration (continued)
If the transmit and receive sections are configured to be synchronous (see WORD/BYTE description), then both
the low-pass and bandpass switched-capacitor filter clocks are derived from TX counter A. Also, both the D/A
and ND conversion timing are derived from the TX counter A and TX counter B. When the transmit and receive
sections are configured to be synchronous, the RX counter A, RX counter B, RA register, RA' register, and RB
registers are not used.

AIC DR or OX word bit pattern
AID or D/A MSB,
1st bit sent

AID or D/A LSB

1st bit sent of 2nd byte

AIC OX data word format section
Comments

d15 Id14 Id13 Id12 Id11 Id10 Id91dSld71d61d51d41d31d21d1 IdO
primary OX serial communication protocol

~ I 0

0

~ I 0

1 The TX and RX counter As are loaded with the TA +
TA: and RA + RA' register values. The TX and RX
counter Bs are loaded with the TB and RB register
values. LSBs d1 = 0 and dO =1 cause the next D/A
and AID conversion periods to be changed by the
addition of TA' and RA: master clock cycles, in which
TA: and AA: can be positive or negative or zero (refer
to Table 1).

rd15 (MSB) through d2 go to the D/A converter register

~ 11

0

The TX and RX counter As are loaded with the TATA: and RA - RA' register values. The TX and RX
counter Bs are loaded with the TB and RB register
values. LSBs d1 = 1 and dO = 0 cause the next D/A
and AID conversion periods to be changed by the
subtraction of TA: and RA: master clock cycles, in
which TA: and RA: can be positive or negative or zero
(refer to Table 1).

rd15 (MSB) through d2 go to the D/A converter register

~ 11

1

The TX and RX counter As are loaded with the TA
and RA register converter register values. The TX
and RX counter Bs are loaded with the TB and RB
register values. After a delay of four shift clock
cycles, a secondary transmission immediately
follows to program the AIC to operate in the desired
configuration.

rd15 (MSB) through d2 go to the D/A converter register

rd15 (MSB) through d2 go to the D/A converter register

.

The TX and RX counter As are loaded with the TA
and RA register values. The TX and RX counter Bs
are loaded with TB and RB register values .

NOTE: Setting the two least significant bits to 1 in the normal transmission of DAC information (primary communications) to the AIC initiates
secondary communications upon completion of the primary communications. Upon completion of the primary communication, FSX
remains high for four shift clock cycles and then goes low and initiates the secondary communication. The timing specifications for the
primary and secondary communications are identical. In this manner, the secondary communication, if initiated, is interleaved between
successive primary communications. This interleaving prevents the secondary communication from interfering with the primary
communications and DAC timing, thus preventing the AIC from skipping a DAC output. In the synchronous mode, FSR is not asserted
during secondary communications.

-!/}

TEXAS
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4--45

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
SLAS017F-'MARCH 1988- REVISED MAY 1995

secondary OX serial communication protocol
x x I <- to TA register

I x x I <- to RA register ~ I
I x I <- to RA' register ~ I
x I <- to TB register ~ I x I <- to RB register ~I
x d7 d6 d5 d4 d3 d2
x x x x x x d9
x I <- to TA' register

~

~

I+-

Control
Register

0 0 d13 and d6 are MSBs (unsigned binary)
0 1 d14 and d7 are 2's complement sign bits
1 0 d14 and d7 are MSBs (unsigned binary)
1 1

---+I

d2 = 0/1 deletes/inserts the AID high-pass filter
d3

=0/1

disables/enables the loopback function

d4 = 0/1 disables/enables the AUX IN + and AUX INd5 = 0/1

asynchronous/synchronous transmit and receive sections

d6 = 0/1 gain control bits (see gain control section)
d7 = 0/1 gain control bits (see gain control section)
d9 = 0/1 delete/insert on-board second-order {sin

xlix correction filter

reset function
A reset function is provided to initiate serial communications between the Ale and DSP. The reset function
initializes all Ale registers, including the control register. After power has been applied to the Ale, a
negative-going pulse on RESET initializes the Ale registers to provide an 8-kHz AID and D/A conversion rate
for a 5.184 MHz master clock input signal. The Ale, except the control register, is initialized as foUows (see Ale
DX data word format section):
REGISTER

INITIALIZED
REGISTER
VALUE (HEX)

TA

9

TA'

1

TB

24

RA

9

RA'
RB

24

The control register bits are reset as follows (see Ale DX data word format section):
d9

= 1 , d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1

This initialization aUows normal serial port communications to occur between Ale and DSP. Ifthe transmit and
receive sections are configured to operate synchronously and the user wishes to program different-conversion
rates, only the TA, TA', and TB register need to be programmed, since both transmit and receive timing are
synchronously derived from these registers (seethe terminal functions table and Ale DX word format sections).
The circuit shown in Figure 1 provides a reset on power up when power is applied in the sequence given under
power-up sequence. The circuit depends on the power supplies reaching their recommended values a minimum
of 800 ns before the capacitor charges to 0.8 V above DGTL GND.
TLC32044/TLC32045
VCC+

RESET

5V
200kO

f----4
*O.5~F

vCC-

-5V

Figure 1. Power-Up Reset

~TEXAS

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power-up sequence
To ensure proper operation of the Ale and as a safeguard against latch-up, it is recommended that Schottky
diodes with forward voltages less than or equal to 0.4 V be connected from Vcc- to ANLG GND and from VCCto DGTL GND (see Figure 21). In the absence of such diodes, power should be applied in the following
sequence: ANLG GND and DGTL GND, VCC-, then Vcc+ and Voo. Also, no input signal should be applied until
after power up.

AIC responses to improper conditions
The Ale has provisions for responding to improper conditions. These improper conditions and the response of
the Ale to these conditions are presented in Table 1 below.

AIC register constraints
The following constraints are placed on the contents of the Ale registers:
1.

TA register must be <:: 4 in word mode (WORD/BYTE

= high).

2.

TA register must be <:: 5 in byte mode (WORD/BYTE

= lOw).

3.

TA' register can be either positive, negative, or zero.

4.

RA register must be <:: 4 in word mode (WORD/BYTE = high).

5.
6.

RA register must be <:: 5 in byte mode (WORD/BYTE = lOw).
RA' register can be either positive, negative, or zero.

7.

(TA register ± TA' register) must be > 1.

8.

(RA register ± RA' register) must be > 1.

9.

TB register must be > 1.
Table 1. AIC Responses to Improper Conditions

IMPROPER CONDITION

Ale RESPONSE

TA register + TA' register = 0 or 1
TA register - TA' register = 0 or 1

Reprogram TX counter A with TA register value

TA register + TA' register < 0

MODULO 64 arithmetic is used to ensure that a positive value is loaded into the TX counter A, Le., TA
register + TA' register + 40 hex is loaded into TX counter A.

RA register + RA' register = 0 or 1
RA register - RA' register = 0 or 1

Reprogram RX counter A with RA register value

RA register + RA' register = 0 or 1

MODULO 64 arithmetic is used to ensure that a positive value is loaded into RX counter A, Le., RA
register + RA' register + 40 hex is loaded into RX-counter A.

TA register = 0 or 1
RA register = 0 or 1

AIC is shut down.

TA register < 4 in word mode
TA register < 5 in byte mode
RA register < 4 in word mode
RA register < 5 in byte mode

The AIC serial port no longer operates.

TB register = 0 or 1

Reprogram TB register with 24 hex

RB register = 0 or 1

Reprogram RB register with 24 hex

AIC and DSP cannot communicate

Hold last DAC output

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-47

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

improper operation due to conversion times being too close together
If the difference between two successive D/A conversion frame syncs is less than 1/19.2 kHz, the Ale operates
improperly. In this situation, the second D/A conversion frame sync occurs too quickly and there is not enough
time for the ongoing conversion to be completed. This situation can occur if the A and B registers are improperly
programmed or if the A + A' register or A - A' register result is too small. When itJ,crementaily adjusting the
conversion period via the A + A' register options, the designer should be careful not to violate this requirement
(see following diagram).
_

t1

t2

Frame!~nCFSX ~~
FSR

~

asynchronous operation frame syncs

Ongoing
Conversion

~

more than one receive frame sync occurring between two transmit

When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific protocol
is followed. The command to use the incremental conversion period adjust option is sent to the Ale during a
FSX frame sync. The ongoing conversion period is then adjusted. However, either receive conversion period
A or B can be adjusted. For both transmit and receive conversion periods, the incremental conversion period
adjustment is performed near the end of the conversion period. Therefore, if there is sufficient time between
t1 and t2, the receive conversion period adjustment is performed during receive conversion period A. Otherwise,
the adjustment is performed during receive conversion period B. The adjustment command only adjusts one
transmit conversion period and one receive conversion period. To adjust another pair of transmit and receive
conversion periods, another command must be issued during a subsequent FSX frame (see figure below).

w'

W

j'II,.1_ _ _ _ _ _ Transmit Conversion Period - - - - - -..
~

l.--

Receive Conv.
Period A

-.l.--

Receive Conv.
Period B

--J

Figure 2. Adjusted Transmit and Receive Conversion Periods

asynchronous operation frame syncs

more than one transmit frame sync occurring between two receive
'

When incrementally adjusting the conversion period via the A + A' or A - P\ register options, a specific protocol
is followed. For both transmit and receive conversion periods, the incremental conversion period adjustment
is performed near the end of the conversion period. The command to use the incremental conversion period
adjust options is sent to the Ale during a FSX frame sync. The ongoing transmit conversion period is then
adjusted. However, three possibilities exist for the receive conversion period adjustment in the diagram as
shown in the following figure. If the adjustment command is issued during transmit conversion period A, receive
conversion period A is adjusted if there is sufficient time between t1 and t2' If there is not sufficient time between
t1 and t2, receive conversion period B is adjusted. The receive portion of an adjustment command can be

~TEXAS

4-48

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

ignored if the adjustment command is sent during a receive conversion period, which is already being or will
be adjusted due to a prior adjustment command. For example, if adjustment commands are issued during
transmit conversion periods A, B, and C, the first two commands can cause receive conversion periods A and
B to be adjusted, while the third receive adjustment command is ignored. The third adjustment command is
ignored since it was issued during receive conversion period B, which already is adjusted via the transmit
conversion period B adjustment command.

I

J4--

Transmit
Conversion
Period A

I

I

Transmit

--¥-- Conversion

Transmit
Conversion
Period C

~

Period B

I
~

t2
FSR

~r--------'W

j.--

Receive

+

Conver~ion Period A

Receive Conversion Period B

-----I

Figure 3. Receive and Transmit Conversion Period Adjustments

asynchronous operation - more than one set of primary and secondary OX serial communication
occurring between two receive frame sync (see Ale OX data word format section)
The TA, TA', TB, and control register information that is transmitted in the secondary communications is always
accepted and is applied during the ongoing transmit conversiDn period. If there is sufficient time between t1 and
t2, the TA, RA', and RB register information, which is sent during transmit conversion period A, is applied to
receive conversion period A. Otherwise, this information is applied during receive conversion period B. If RA,
RA', and RB register information has already been received and is being applied during an ongoing conversion
period, any subsequent RA, RA', or RB information that is received during this receive conversion period is
disregarded (see Figure 4).
Primary
FSxl

n

t1

secondar..
y _ _ _.., Primary

14~f----

Transmit
Conversion
Period A

I

n

---"'~'I'II~I---

secondaryi-_ _....... Primary

Transmit
Conversion
Period B

I

---~~4----

---------:1__

...1

4-- Receive Conversion

I

Transmit
Conversion
Period C

~

---~~

1

t2

FSR

n

Secondaryi-_ _.......

--1.~:"J------ Receive Conversion Period B ----~~

Period A

Figure 4. Receive and Transmit Periods for Primary and Secondary Data

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-49

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

test modest
The TLC32044 or TLC32045 can be operated in special test modes. These test modes are used by Texas
Instruments to facilitate testing of the device during manufacturing. They are not intended to be used in real
applications; however, they allow the filters in the AID and D/A paths to be used without using the AID and D/A
converters.
In normal operation, the nonusable (NU) terminals are left unconnected. These NU terminals are used by the
factory to speed up testing of the TLC32044 or TLC32045 analog interface circuits (AIC). When the device is
used in normal (non-test mode) operation, the NU terminal (terminal 1) has an internal pulldown to -5 V.
Externally connecting 0 V or 5 V to terminal 1 puts the device in test-mode operation. Selecting one of the
possible test modes is accomplished by placing a particular voltage on certain terminals. A description of these
modes is provided in Table 2 and Figures 5 and 6.

Table 2. List of Test Modes
TEST
TERMINALS

DIA PATH TEST (TERMINAL 1 to 5 V)
TEST FUNCTION

TEST FUNCTION

5

The low-pass switched·capacitor filter clock is brought out to
DR. This clock signal is normally internal.

The bandpass switched-capacitor filter clock is brought out to
DR. This clock signal is normally internal.

11

No . change from normal operation. The EODX signal is
brought out to EODX.
.

The pulse that initiates the AID conversion is brought out here.
This signal is normally internal.

3

The pulse that initiates the D/A conversion is brought out here.

No change from normal operation. The EODR signal is
brought out.

27 and 28

There are no test output signals provided on these terminals.

The outputs of the AID path low·pass or bimdpass filter
(depending upon control bit d2 - see AIC OX data word format
section) are brought out to these terminals. If the high-pass
section is inserted, the output will have a (sin xlix droop. The
slope of the droop is determined by the ADC sampling
frequency, which is the high-pass section clock frequency
(see diagram of bandpass or low-pass filter test for receive
section). These outputs drive small (30·pF) loads.

15 and 16

AID PATH TEST (TERMINAL 1 to 0)

D/A PATH LOW·PASS FILTER TEST: (WORD/BYTE) to -5 V
TEST FUNCTION
The inputs of the DIA path low·pass filter are brought out to terminals 15 and 16. The D/A input to this filter is removed. If (sin xlix
correction filter is inserted, the OUT + and OUT - signals have a flat response (see Figure 2). The common·mode range of these
inputs must not exceed to.5 V.

t

In the test mode, the AIC responds to the setting of WORD/BYTE to -5 V, as if WORD/BYTE were set to 0 V. Thus, the byte mode is selected
for communicating between DSP and AIC. Either of the path tests (D/A or AID) can be performed simultaneously with the D/A low'pass filter test.
In this situation, WORD/BYTE must be connected to -5 V, which initiates byte-mode communications.

~TEXAS'

4-50

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

Terminal 27 (positive)
Terminal 28 (negative)t

Test Control
(terminal 1 at 0 V)
Filter

1----I-----t M

U 1---+_-+---1
X

t

AID

All analog signal paths have differential architecture and hence have positive and negative
components.

Figure 5. Bandpass or Low-Pass Filter Test for Receiver Section
Filter

.......--+---I

M
U 1--+---1

D/A

X

......._

Test Control

(terminal 13 at-5 V)

Terminal 16 (positive)

Terminal 15 (negative)t

t

All analog signal paths have differential architecture and hence have positive and negative components.

Figure 6. Low-Pass Filter Test for Transmit Section

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-51

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vcc+ (see Note 1) ............................................ -0.3 V to 15 V
Supply voltage range, VDD ......................................................... -0.3 V to 15 V
Output voltage range, Va .......................................................... -0.3 V to 15 V
Input voltage range, VI ...................................................•......... -0.3 V to 15 V
Digital ground voltage range ........................................................ -0.3 V to 15 V
Operating free-air temperature range: TLC32044C, TLC32045C ......................... O°C to 70°C
TLC32044E ................................... -20°C to 85°C
TLC320441, TLC320451 ......................... -40°C to 85°C
TLC32044M .................................. -55°C to 125°C
Storage temperature range: TLC32044C, I, TLC32045C, I ........................... -40°C to 125°C
TLC32044M .......................................... -65°C to 150°C
Case temperature for 10 seconds: FN or FK package ......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package .................... 260°C
J package .................... 300°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values for maximum ratings are with respect to VCC-.

recommended operating conditions
MIN

NOM

MAX

UNIT

Supply voltage, VCC + (see Note 2)

4.75

5

5.25

V

Supply voltage, VCC- (see Note 2)

-4.75

-5

-5.25

Digital supply voltage. VDD (see Note 2)

4.75

Digital ground voltage with respect to ANLG GND, DGTL GND
2

High-level input voltage. VIH

2

MSTR CLK frequency (see Note 4)

0.075

V

0.8

V

100

pF

Q

5

10.368

MHz

±1.5

AID or D/A conversion rate

V
kHz

20
0

70

TLC32044E

-20

85

TLC320441, TLC320451

-40

85

TLC32044M

-55

125

TLC32044C,TLC32045C

°C

..

2. Voltages at analog Inputs and outputs, REF, VCC +, and VCC-, are with respect to the ANLG GND terminal. Voltages at digital Inputs
and outputs and VDD are with respect to the DGTL GND terminal.
3. The algebraic convention, in which the least po~itive (most negative) value is designated minimum, is used in this data sheet for
logic voltage levels and temperature only.
4. The bandpass switched-capacitor filter (SCF) specifications apply only when the low-pass section SCF clock is 288 kHz and the
high-pass section SCF clock is 8 kHz. If the low-pass SCF clock is shifted from 288 kHz, the low-pass roll-off frequency will shift
by the ratio of the low-pass SCF clock to 288 kHz. If the high-pass SCF is shifted from 8 kHZ, the high-pass roll-off frequency will
shift by the ratio of the high-pass SCF clock to 8 kHz. Similarly, the low-pass switched-capacitor filter (SCF) specifications apply only
when the SCF clock is 288 kHz. If the SCF clock is shifted from 288 kHz, the low-pass roll-off frequency will shift by the ratio of the
SCF clock to 288 kHz.
5. This range applies when (IN+ -IN-) or (AUX IN+ - AUX IN-) equals ± 6 V.

~TEXAS

4-52

V

300

Analog input amplifier common mode input voltage (see Note 5)

NOTES:

V

VDD+0.3

Load capacitance at OUT + and lor OUT -, CL

Operating free-air temperature, TA

V

4

-0.3

Load resistance at OUT + and lor OUT -, RL

V

5.25
0

Reference input voltage, Vref(ext) (see Note 2)

LOW-level input voltage, VIL (see Note 3)

5

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

electrical characteristics over recommended operating free-air temperature range, Vcc+
Vcc- = -5 V, Voo = 5 V (unless otherwise noted)

=5 V,

total device, MSTR ClK frequency = 5.184 MHz, outputs not loaded
PARAMETER
VOH

High-level output voltage

VOL

Low-level output voltage

ICC+

Supply current from VCC +

TEST CONDITIONS
VDD = 4.75 V,
IOH=-300~

MIN

TYPt

Supply current from VCC-

IDD

Supply current from VDD

V

VDD = 4.75 V,
IOL=2 mA

0.4

Vref

Internal reference output voltage

35

TLC320441, TLC320451,
TLC32044E, TLC32044M

40

TLC32044C,TLC32045C

-35

TLC320441, TLC320451,
TLC32044E,TLC32044M

-40

TLC3204xC, E, I
TLC32044M

UNIT

2.4

TLC32044C,TLC32045C

ICC-

MAX

mA

7
fMSTR CLK = 5.184 MHz

TLC3204xC, E, I
TLC32044M

8
3

3.3

2.9

3.3

V

=Vref

Temperature coefficient of internal reference voltage

200

ppm/oC

ro

Output resistance at REF

100

kn

receive amplifier input
TYpt

MAX

TLC32044C, E, I

10

70

TLC32044M

10

85

TLC32045C, I

10

75

PARAMETER

TEST CONDITIONS

ND converter offset error (filters in)

TLC3204xC, E, I

CMRR

Common-mode rejection ratio at IN+, IN-, or
AUX IN +, AUX IN-

q

Input resistance at IN+, IN-, or AUX IN+, AUX IN-, REF

TLC32044M

See Note 6

MIN

55
35

UNIT

mV

dB

55
100

kn

transmit filter output
TEST CONDITIONS

PARAMETER

MIN

TYPt

MAX

I TLC3204xC, E, I

15

80

ITLC32044M

15

75

VOO

Output offset voltage at OUT + OUT (single-ended relative to ANLG GND)

VOM

Maximum peak output voltage swing across RL at OUT + or OUT (single ended)

RL2:300n,
Offset voltage = 0

±3

VOM

Maximum peak output voltage swing between OUT + and OUT (differential output)

RL2:600n

±6

UNIT
mV

V

t

All typical values are at TA = 25°C.
NOTE 6: The test condition is a O-dBm, 1-kHz input signal with an 8-kHz conversion rate.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-53

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG .INTERFACE CIRCUITS
SLAS017F- MARCH 1988- REVISED MAY 1995

system distortion specifications, SCF clock frequency
PARAMETER
Attenuation of second
harmonic of NO input
signal

Attenuation of third and
higher harmonics of NO
input signal

Single ended

Differential

Single ended

Differential

Attenuation of second
harmonic of D/A input
signal

Single ended

Attenuation of third and
higher harmonics of D/A
input signal

Single ended

Differential

Differential

= 288 kHz (see Note 7)
TEST CONDITIONS

TLC3204xC, E, I
TLC32044M
TLC32044C, E, I
TLC32045C, I
TLC3204xC, E, I
TLC32044M
TLC32044C, E, I
TLC32045C, I

VI = -0.5 dB to -24 dB reterred to Vret,
TA = 25°C
VI = -0.5 dB to -24 dB referred to Vref
VI = -0.5 dB to -24 dB referred to Vref,
TA = 25°C
VI = -0.5 dB to -24 dB referred to Vref

MIN

UNIT

62

70

62

70

55

70

57

65

57

65

55

65

65

dB

70
VI = -0 dB to -24 dB referred to Vref

TLC32045C, I

62

70

55

70

57

65

55

65

TLC3204xC, I, M
TLC32044P, E, I

MAX

70

TLC3204xC, I, M
TLC32044C, E, I

TYPt

65
VI = -0 dB to -24 dB referred to Vref

TLC32045C, I

t

All typical values are at TA = 25°C.
NOTE 7: The test condition VI is a 1·kHz input signal with an 8·kHz conversion rate (0 dB relative to Vref). The load impedance for the DAC is
600 Q (300 Q for TLC32044M).

~TEXAS

INSTRUMENTS
4-54

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
. VOICE·BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

AID channel signal-to-distortion ratio (see Note7)
PARAMETER

TEST CONDITIONS

AID channel signal-to-distortion ratio, TLC32044C,
TLC320441, TLC32044E

AID channel signal-to-distortion ratio, TLC32044M

AID channel signal-to-distortion ratio, TLC32045C,
TLC320451

.. .
t Av IS the programmable gain of the Input amplifier

Av=1t
MIN

MAX

Av=2t
MIN

MAX

Av=4t
MIN

VI= -6 dB to -0.1 dB

58

>58;

>58;

VI=-12dBto-6dB

58

58

>58;

VI = -18 dB to -12 dB

56

58

58

VI = -24 dB to -18 dB

50

56

58

VI = -30 dB to -24 dB

44

50

56

VI = -36 dB to -30 dB

38

44

50

VI = -42 dB to -36 dB

32

38

44

VI = -48 dB to -42 dB

26

32

38

VI = -54 dB to -48 dB

20

26

32

VI = -6 dB to -0.5 dB

58

>58;

>58;

VI=-12dBIo-6dB

58

58

>58;

VI = -18 dB to -12 dB

56

58

58

VI = -24 dB to -18 dB

50

56

58

VI = -30 dB to -24 dB

44

50

56

VI = -36 dB to -30 dB

38

44

50

VI = -42 dB to -36 dB

32

38

44

VI = -48 dB to -42 dB

26

32

38

VI = -54 dB to -48 dB

20

26

32

VI = -6 dB to -0.1 dB

55

>55;

>55;

VI = -12 dB to-6 dB

55

55

>55;

VI = -18 dB to -12 dB

53

55

55

VI = -24 dB to-18 dB

47

53

55

VI = -30 dB to -24 dB

41

47

53

VI = -36 dB to -30 dB

35

41

47

VI = -42 dB to -36 dB

29

35

41

VI = -48 dB 10 -42 dB

23

29

35

VI = -54 dB to -48 dB

17

23

29

MAX

UNIT

dB

; A value> 60 is over range and signal clipping occurs.
NOTE 7: The test condition VI is a l-kHz input signal with an 8-kHz conversion rate (0 dB relative to Vref). The load impedance for the DAC is
600 (1 (300 (1 for TLC32044M).

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-55

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE.;BAND ANALOG INTERFACE CIRCUITS
SLAS017F ~ MARCH 1988 - REV!SED MAY 1995

D/A channel signal-to-distortion ratio (see Note 7)
PARAMETER

TEST CONDITIONS

D/A channel signal-to-distortion ratio, TLC32044C, TLC32044E, TLC320441,
TLC32044M

D/A channel signal-to-distortion ratio, TLC32045C, TLC320451

MIN

VI = -6 dB to 0 dB

58

VI = -12 dB to -6 dB

58

VI = -18 dB to -12 dB

56

VI = -24 dB to -18 dB

50

VI = -30 dB to -24 dB

44

VI = -36 dB to -30 dB

38

VI = -42 dB to -36 dB

32

VI = -48 dB to -42 dB

26

VI = -54 dB to -48 dB

20

VI = -6 dB to 0 dB

55

VI =-12 dB to-6 dB

55

VI = -18 dB to -12 dB

53

VI = -24 dB to -18 dB

47

VI = -30 dB to -24 dB

41

VI = -36 dB to -30 dB

35

VI = -42 dB to -36 dB

29

VI = -48 dB to -42 dB

23

VI = -54 dB to -48 dB

17

MAX

UNIT

dB

NOTE 7: The test condition VI is a I-kHz input signal with an 8-kHz conversion rate (0 dB relative to Vref). The load impedance for the DAC is
600 n (300 n for TlC32044M).

gain and dynamic range
PARAMETER

TEST CONDITIONS

MIN

TYPt

MAX

UNIT

±0.05

±0.15

dB

±0.05

±0.25

dB

±OA

dB

±0.05

±0.15

dB

±0.05

±0.25

dB

±OA

dB

Absolute transmit gain tracking error while transmitting
into 600 n

-48-dB to O-dB signal range,

See Note 8

Absolute transmit gain tracking error while transmitting
into 300 n, TLC32044M

-48-dB to O-dB signal range,
See Note 8

TA= 25'C,

Absolute transmit gain tracking error while transmitting
into 300 n, TLC32044M

-48-dB to O-dB signal range,
TA =-55'C to 125'C,

Absolute receive gain tracking error

-48-dB to O-dB signal range,

See Note 8

Absolute receive gain tracking error, TLC32044M

-48-dB to O-dB signal range,
See Note 8

TA = 25'C,

Absolute receive gain tracking error, TLC32044M

-48-dB to O-dB signal range,
TA = -55'C to 125'C,

See Note 8

Absolute gain of the AID channel

Signal input is a -0.5-dB,

I-kHz sinewave

0.2

Absolute gain of the D/A channel

Signal input is a O-dB,

I-kHz sinewave

-0.3

See Note 8

t

All typical values are at TA = 25'C.
NOTE 8: Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 dB relative to Vref).

~TEXAS

INSTRUMENTS
4-56

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

dB

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

power supply rejection and crosstalk attenuation
PARAMETER
VCC+ or VCG- supply voltage rejection
ratio, receive channel

TEST CONDITIONS
f = 0 to 30 kHz
f = 30 kHz to 50 kHz

V CC + or V CC _ supply voltage rejection
ratio, transmit channel (single ended)

f=Ot030kHz

Crosstalk attenuation, transmit-to-receive
(single ended)

TLC3204xC, E, I

f = 30 kHz to 50 kHz

t

TYPt
30

Idle channel, supply signal at 200 mV
p-p measured at OUT +

30

MAX

UNIT

45

45

dB

80

TLC32044M

Crosstalk attenuation, receive-to-transmit, TLC32044M

MIN

Idle channel, supply signal at 200 mV
p-p measured at DR (ADC output)

65
Inputs grounded,

Gain = 1, 2, 4

80

65

All tYPical values are at TA = 25'C.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-57

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOI.CE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

delay distortion
bandpass filter transfer function, SCF fclock
PARAMETER

TEST CONDITIONS

f~

Filter gain,
TlC32044C,
TlC32044E,
TlC320441

Filter gain,
TlC32044M

Filter gain,
TlC32045C,
TlC320451

Input signal reference to 0 dB

Input signal reference to 0 dB

Input signal reference to 0 dB

= 288 kHz IN+ -IN- is a ±3 V sinewavet (see Note 9)

FREQUENCY RANGE

ADJUSTMENT ADDEND*

50 Hz

K1 x OdB

MIN

TYP§

MAX

-33

-29

-25

f= 100 Hz

K1 x-0.26 dB

-4

-2

-1

f = 150 Hz to 3100 Hz

K1 xOdB

-0.25

0

0.25

f = 3100 Hz to 3300 Hz

K1 x 0 dB

-0.3

0

0.3

f = 3300 Hz to 3650 Hz

K1 x 0 dB

-0.5

0

0.5

f = 3800 Hz

K1 x2.3dB

-3

-1

f = 4000 Hz

K1 x2.7dB

-17

-16

f;:,,4400 Hz

K1 x3.2dB

f;:" 5000 Hz

K1 x 0 dB

f~

K1 xO dB

50 Hz

-40
-65
-33

-29

-4

-2

-25
-1

-0.25

0

0.25

f = 100 Hz

K1 x-0.26 dB

f = 150 Hz to 3100 Hz

K1 x 0 dB

f = 3100 Hz to 3300 Hz

K1 x 0 dB

-0.3

0

0.3

f = 3300 Hz to 3500 Hz

K1 x OdB

-0.5

0

0.5

f = 3800 Hz

K1 x2.3dB

-3

-0.5

f = 4000 Hz

K1 x2.7dB

-17

f;:" 4400 Hz

K1 x 3.2 dB

f;:" 5000 Hz

K1 x 0 dB

f~50

K1 xO dB

Hz

f = 100 Hz

K1 x-0.26 dB

f = 150 Hz to 3100 Hz

Kl x 0 dB

-16
-65

-33

-29

-4

-2

-25
-1

-0.25

0

0.25

f = 3100 Hz to 3300 Hz

Kl x 0 dB

-0.3

0

0.3

K1 x OdB

-0.5

0

0.5

f = 3800 Hz

Kl x2.3dB

-3

-1

f = 4000 Hz

Kl x2.7dB

-17

-16

f;:" 4400 Hz

Kl x3.2dB

-40

f;:" 5000 Hz

Kl xOdB

-65

*

dB

-40

f = 3300 Hz to 3650 Hz

t

UNIT

See filter curves in typical characteristics
The MIN, TYP, and MAX specifications are given for a 288-kHz SCF clock frequency. A slight error in the 288-kHz SCF may result from
inaccuracies in the MSTR ClK frequency, resulting from crystal frequency tolerances. If this frequency error is less than 0.25%, the
ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specifications, where Kl = 100 '[(SCF frequency - 288 kHz) / 288 kHz].
For errors greater than 0.25%, see Note 8.
§ All typical values are at TA = 25'C.
NOTE 9: The filter gain outside of the passband is measured with respect to the gain at 1 kHz. The filter gain within the passband is measured
with respect to the average gain within the passband. The passbands are 150 to 3600 Hz and 0 to 3600 Hz for the bandpass and
low-pass filters respectively. For switched-capacitor fitler clocks at frequencies other than 288 kHz, the Mer response is shifted by the
ratio of switched-capacitor filter clock frequency to 288 kHz.

~TEXAS

4-58

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS; TEXAS 75265

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

low-pass filter transfer functiont,SCF fclock: 288 kHz (see Note 9)
PARAMETER

Filter gain,
TlC32044C,
TlC32044E,
TlC320441

Filter gain,
TLC32044M

Filter gain,
TlC32045C,
TlC320451

TEST CONDITIONS

Input signal relerence is 0 dB

Input signal relerence is 0 dB

Input signal relerence is 0 dB

FREQUENCY RANGE

MIN

TYP§

MAX

-0.25

0

0.25

Kl x 0 dB

-0.3

0

0.3

Kl x 0 dB

-0.5

0

0.5

ADJUSTMENT ADDENo*

1=0 Hz to 3100 Hz

Kl x 0 dB

1= 3100 Hzto 3300 Hz
I = 3300 Hz to 3650 Hz
1= 3800 Hz

Kl x2.3dB

-3

-1

1= 4000 Hz

Kl x2.7dB

-17

-16

12: 4400 Hz

Kl x3.2dB

12: 5000 Hz

Kl x 0 dB

1= 0 Hz to 3100 Hz

Kl x OdB

1= 3100 Hz to 3300 Hz
I = 3300 Hz to 3500 Hz
1= 3800 Hz

'= 4000 Hz
12:4400 Hz

Kl x3.2dB

12: 5000 Hz

Kl x 0 dB

1= 0 Hz to 3100 Hz

Kl xO dB

-0.25

0

0.25

1= 3100 Hz to 3300 Hz

Kl xO dB

-0.3

0

0.3

I = 3300 Hz to 3650 Hz

Kl x 0 dB

-0.5

0

0.5

1= 3800 Hz

Kl x2.3dB

-3

-1

1= 4000 Hz

Kl x2.7dB

-17

-16

12: 4400 Hz

Kl x 3.2 dB

-40

12: 5000 Hz

Kl xOdB

-65

UNIT

-40
-65
-0.25

0

0.25

Kl xO dB

-0.3

0

0.3

Kl xOdB

-0.5

0

0.5

Kl x2.3dB

-3

-0.5

Kl x2.7dB

-17

-16

dB

-40
-65

t

See Iilter curves In typical characteristics
:j: The MIN, TYP, and MAX specilications are given for a 288-kHz SCF clock Irequency. A slight error in the 288-kHz SCF may result lrom
inaccuracies in the MSTR ClK Irequency, resulting Irom crystal Irequency tolerances. If this Irequency error is less than 0.25%, the
ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specilications, where Kl = 100 '[(SCF frequency - 288 kHz) 1288 kHz].
For errors greater than 0.25%, see Note 8.
§ AU typical values are at TA = 25'C.
NOTE 9: The lilter gain outside 01 the passband is measured with respect to the gain at 1 kHz. The Iilter gain within the passband is measured
with respect to the average gain within the passband. The passbands are 150 to 3600 Hz and 0 to 3600 Hz lor the bandpass and
low-pass filters respectively. For switched-capacitor filter clocks at Irequencies other than 288 kHz, the Ii Iter response is shifted by the
ratio 01 switched-capacitor filter clock frequency to 288 kHz.

serial port
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

IOH=-300 itA

VOL

lOW-level output voltage

IOl=2 mA

II

Input current

MIN

TYPt

MAX

2.4

UNIT

V
0.4

V

±10

itA

Ci

Input capacitance

15

pF

Co

Output capacitance

15

pF

t All typical values are at TA = 25'C.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-59

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

operating characteristics over recommended operating free-air temperature range, Vcc+

Vcc- = -5 V, Voo = 5 V

=5 V,

noise (measurement includes low-pass and bandpass switched-capacitor filters)
PARAMETER

TEST CONDITIONS

MIN

TYPt

TLC32044M

575

~Vrms

600

~Vrms

325

425

~Vrms

325

450

~Vrms

450

~Vrms

With sin x/x correction

Transmit noise

OX input = 00000000000000.
constant input code

TLC32044M '
TLC32045C. I

Without sin x/x correction

TLC32044C. E. I

18

TLC32045C. I

24

TLC32044C. E.I. M
Receive noise
(see Note 10)

300

TLC32045C. I

dBrncO
dBrncO
500
530

Inputs grounded. gain = 1

TLC32044C. E. I. M

UNIT
~Vrms

TLC32045C. I
TLC32044C. E. I

MAX
550

TLC32044C. E. I

TLC32045C. I

~Vrms

~Vrms

18

dBrncO

24

dBrncO

t

All typIcal values are at TA = 25°C.
NOTE 10: The noise is computed by statistically evaluating the digital output of the NO converter.

timing requirements
serial port recommended input signals
MIN
tc(MCLK)

I Master clock cycle time
I Master clock cycle time. TLC32044M

tr(MCLK)

Master clock rise time

tf(MCLK)

Master clock fall time

tsu(OX)
th(OX)

MAX

95
100

UNIT
ns

192

ns

10

ns

10

ns

Master clock duty cycle

25%

75%

Master clock duty cycle. TLC32044M

42%

58%

RESET pulse duration (see Note 11)

800

ns

lOX setup time before SCLKt

20

ns

I OX setup time before SCLKt. TLC32044M

28

OX hold time after SCLKt

tc(SCLK)/4

ns
ns
,

NOTE 11: RESET pulse duratIon IS the amount of tIme that the reset pIn IS held below 0.8 V after the power supplies have reached theIr
recommended values.

~TEXAS

INSTRUMENTS
4-60

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

.

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

serial port -

AIC output signals
TEST CONDITIONS

MIN

TYpt

MAX

380

UNIT

Ic(SCLK)

Shift clock (SCLK) cycle lime

If(SCLK)

Shift clock (SCLK) fall lime

50

ns

Ir(SCLK)

Shift clock (SCLK) rise lime

50

ns

Shift clock (SCLK) duty cycle

ns

45

55

%
ns

Id(CH-FL)

Delay from SCLKilo FSR/FSX.l-

CL = 50 pF

52

IdICH-FHI

Delay from SCLKi to FSR/FSxi

CL = 50 pF

52

ns

Id(CH-DR)

DR valid after SCLKi

90

ns

Id(CH-EL)

Delay from SCLKi to EODX/EODR.l- in word mode

90

ns

Id(CH-EH)

Delay from SCLKi 10 EODX/EODRi in word mode

90

ns

If(EODX)

EODX fall time

15

ns

If(EODRI

EODR fall time

15

ns

Id(CH-EL)

Delay from SCLKi 10 EODX/EODR.l- in byte mode

100

ns

Id{CH-EH)

Delay from SCLKi 10 EODX/EODRi in byte mode

100

ns

Id(MH-SL)

Delay from MSTR CLKi 10 SCLK.l-

65

ns

Id(MH-SH)

Delay from MSTR CLKi 10 SCLKi

65

ns

serial port -

AIC output Signals, TLC32044M
MIN

TYPt

MAX

UNIT

ic{SCLKI

Shift clock (SCLK) cycle lime

If(SCLK)

Shift clock (SCLK) fall time

50

ns

trlSCLKI

Shift clock (SCLK) rise time

50

ns

Shift clock (SCLK) duty cycle

50

400

ns

%

IdICH-FLl

Delay from SCLKi 10 FSR/FSX.l-

260

ns

Id(CH-FH)

Delay from SCLKito FSR/FSxi

260

ns

Id(CH-DR)

DR valid after SCLKi

316

ns

Id{CH-EL)

Delay from SCLKi 10 EODXI EODR.l- in word mode

280

ns

Id(CH-EH)

Delay from SCLKi to EODX/EODRi in word mode

280

ns

If(EODX)

EODX fall time

15

ns

If(EODR)

EODR fall time

15

ns

IdICH-ELI

Delay from SCLKi to EODX/EODR.l- in byte mode

100

ns

Id(CH-EH)

Delay from SCLKi 10 EODX/EODRi in. byte mode

100

ns

IdIMH-SLI

Delay from MSTR CLKi 10 SCLK.l-

65

ns

Id(MH-SH)

Delay from MSTR CLKi 10 SCLKi

65

ns

tTYPlcal values are al TA = 25°C.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-61

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988- REVISED MAY 1995

Table 3. Gain Control Table (Analog Input Signal Required for Full-Scale AID Conversion)
CONTROL REGISTER
BITS

INPUT CONFIGURATIONS

d6
Differential configuration
Analog input = IN + - IN= AUX IN+-AUX IN-

Single-ended configuration
Analog input = IN + - ANLG GND
= AUX IN + - ANLG GND

AID
ANALOG INPUT*

CONVERSION
RESULT

±6V

Full-scale

d7

1

1

0

0

1

0

±3V

Full-scale

0

1

±1.5V

Full-scale

1

1

0

0

±3V

Ha~-scale

1

0

±3V

Full-sale

0

1

±1.5V

Full-scale

..

..

:j: In this example, Vref IS assumed to be 3 V. In order to minimize distortion, It IS recommended that the analog
input not exceed 0.1 dB below full scale.

Rfb

R
IN -

Rfb

I--"'-}

-'VV'v---4...-t

R
To Multiplexer

R

AUX IN +

-'V\IIr-<.....-t

AUX IN-

-'V\IIr-<.....-t

I-"'-}

R
Rfb

To Multiplexer

Rfb

Rfb = R for d6 = 1, d7 = 1
d6=0,d7=0
Rfb = 2R for d6 = 1, d7 = 0
Rfb = 4R for d6 = 0, d7 = 1

Rfb = R for d6 = 1, d7 = 1
d6=0,d7=0
Rfb = 2R for d6 = 1, d7 = 0
Rfb 4R for d6 0, d7 1

=

Figure 7. IN+ and IN- Gain Control Circuitry

=

=

Figure 8. AUX IN+ and AUX INGain Control Circuitry

(sin x)/x correction
The Ale does not have (sin x)/x correction circuitry after the digital-to-analog converter. (Sin x)/x correction can
be accomplished easily and efficiently in digital signal processor (DSP) software. Excellent correction accuracy
can be achieved to a band edge of 3000 Hz by using a first-order digital correction filter, The results, which are
shown in Table 4, are typical of the numerical correction accuracy that can be achieved for sample rates of
interest. The filter requires only seven instruction cycles per sample on the TMS(SMJ)320 DSPs, With,a 200-ns
instruction cycle, nine instructions per sample represents an overhead factor of 1.4% and 1,7% for sampling
rates of 8000 Hz and 9600 Hz, respectively, This correction adds a slight amount of group delay at the upper
edge of the 300-3000-Hz band.

~TEXAS

4-62

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

(sin x)/x roll-off for a zero-order hold function
The (sin x)/x roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for the
•
various sampling rates is shown in the table below.

Table 4. (sin x)/x Roll-Off
Ills
Ills
(I.;: 3000 Hz)
(dB)

20 log

sin

It

It

Is (Hz)
7200

-2.64

8000

-2.11

9600

-1.44

14400

-0.63

19200

-0.35

The actual AIC (sin x)/x roll-off will be slightly less than the above figures because the AIC has less than a 100%
duty cycle hold interval.

correction filter
To compensate for the (sin x)/x roll-off of the AIC, a first-order correction filter (shown below) is recommended.

U(I+1)~.
~.~
•

(1-:"P2

y

1-4----14;

I

~

p1

The difference equation for this correction filter is:
yi + 1 = p2(1 -p1) (Uj + 1) + p1 yi
where the constant p1 determines the pole locations'.
The resulting squared magnitude transfer function is:

1 - 2p1 cos(2

it

f/fs)

+

p1 2

~TEXAS

INSTRUMENTS
POST-OFFICE BOX 655303. DALLAS, TEXAS 75265

4-63

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F-MARCH 1988- REVISED MAY 1995

correction results
Table 5 shows the optimum p values and the corresponding correction results for BODO-Hz and 9600-Hz
sampling rates.
Table 5. Optimum P Values

f(Hz)

ERROR (dB)

ERROR (dB)

fs =8000 Hz
p1 = -0.14813
p2 = 0.9888

fs = 9600 Hz
p1 = -0.1307
p2 = 0.9951

300

-0.099

-0.043

600

-0.089

-0.043

900

-0.054

0

1200

-0.002

0

1500

0.041

0

1800

0.079

0.043

2100

0.100

0.043

2400

0.091

0.043

2700

-0.043

0

3000

-0.102

-0.043

TMS(SMJ}320 software requirements
The digital correction filter equation can be written in state variable form as follows:
Y = k1 x Y + k2 x U
where.
k1 = p1
k2 = (1 - p1) x p2
Y = filter state
U = next 1/0 sample
The coefficients k1 and k2 must be represented as 16-bit integers. The SACH instruction (with the proper shift)
yields the correct result. With the assumption that the TMS(SMJ)320 processor page pointer and memory
configuration are properly initialized, the equation can be executed in seven instructions or seven cycles with
the following program:
ZAC
LT K2
MPYU
LTA K1
MPYY
APAC
SACH (dma), (shift)

~TEXAS

4-64

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

PARAMETER MEASUREMENT INFORMATION

I+---*- le(SCLK)
SHIFTCLK

I

0.8 V

Id(CH-FL)~~

I I

I I

_+I-+:--II\';---~r
:

I

Id(CH-FH)~ ~

'J._0.8_ v

FSR, FSX

DR

I

0.8 V

~ ~ td(CH-DR)

I

Id(CH-FL)~~

Id(CH-FH)~,~:.....-_ _

'J.____'I/I-;-----~r 2 V

2V

0.8 V

:

:

---~~~~
:
D15
~~""'-----'"---~D8:------~k¥\
~~~~~

D1

II

DO

I

I

~
Don't Care
~
OX ~~JD9DQD---"':::'~;":::::.!---{JO~7:X!D8!1~
EODR,

~

i4- I~,~DX)

~ I+- Id(CH-EL)

EOD-X----------~\-----"

Id(CH-EH)

II .

0.8 V

-.I')J.-~2~V~.

(a) BYTE-MODE TIMING
~te(SCLK)
I
I
2V

SHIFTCLK
0.8 V

I

_ _....
--!.!-ld(CH-FL)
0.8V'b

DR

__

I

I

I I
I~

I

td(CH-FH)~)!4- I

:

1.~2V~1- - -

I';

*- td(CH-DR)

::

~01~5_~~~__D_1___DO~I__~I_____
tsu(DX)

OX

:

015

-.I ~

014

I
D2

01

DO

Don'l Care

~ !4- Ih(DX)
Id(CH-EL) ~ ~ ~ 14- Id(CH-EH)
-------------~\I\-----0-.8~V~~2~V:---(b) WORD-MODE TIMING

MSTRCLK

SHIFTCLK

I
--:

I
14- Id(MH-SH)

_ _ _-----J/iJ(e) SHIFT-CLOCK TIMING

I

~

14- td(MH-SL)

~~--'------

Figure 9. Serial-Port Timing

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-65

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

PARAMETER MEASUREMENT INFORMATION

TMS32010/
SMJ32010

SN74(54)lS299
I-

I

OEN

L

G1

AO/PAD

A

A1/PA1

B

A2/PA2

WE

A-H

-

ClKOUT
INT

S1
<12

00-07

<11
./ A-H

TlC32044/
TlC32045

SHIFTClK

QH

SO ClK

\

ox

a-

SR

SN74(54)lS299

bD
~

cr

G1

C
SN74(54)lS138

\

QH

G2
SOClK

Y1 I---YO
08-015

00-015

00-015

S1

FSX

C2

SR

~
Y

,~

~
C1
Q 10

OR

MSTRClK
EOOX

Figure 10. TMS(SMJ)32010ITMS(SMJ)320C15/(SMJ320E15)-TLC32044/45Interface Circuit

~TEXAS

INSTRUMENTS
4--66

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

PARAMETER MEASUREMENT INFORMATION
ClKOUT

.-J
~

__~i~Ir-----------------------I
I
I

SO,G1·

00-015---------«

Valid

»)-----------------

(a) IN INSTRUCTION TIMING

ClKOUT

.-J
---------------------

~--~I
SN74(54)lS138

Y1
SN74(54)lS299
ClK

00-015

---------«

Valid

)>----------....,...------

(b) OUT INSTRUCTION TIMING

Figure 11. TMS(SMJ)3201 OITMS(SMJ)320C15-TLC32044ITLC32045 Interface Timing

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-67

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

TYPICAL CHARACTERISTICS
AIC TRANSMIT AND RECEIVE
LOW·PASS FILTER

AIC TRANSMIT AND RECEIVE
LOW·PASS FILTER
20

3

S~F

2.5 -

0

\,

-10

m

'0
I

-20

::I

~

Cl

~

--30
-40

>-

a;

c

SCF Clock f = 288 kHz
TA = 25°C
Input = ±3-V Sine wave

-70

o

0.5

1

1.5

2

2.5

1.5

E

CI

~

II
3.5

4

4.5

J

0.5

,..
3

II

Co
::I

\

-50

-80

..
I

\

-60

2

fIJ

E

1\

GI

'0

o

Figure 12

20

10

\,

-10
-20

..

':"40

c

Cl

:i!

-50

m
'0
I

-70

o

i

I

I

I

I

I

I

0.5

1

1.5

2

2.5

3

3.5

I

GI

'0

::!

-20

';:

..

r,

Cl

:i!

,..

\/
4

I

-10

--30
-40

Low-Pass SCF Clock f = 288 kHz
High-Pass SCF Clock f = 8 kHz
TA = 25°C
Input = ±3-V Sine wave

-60

-80

0

1\
\
\

GI

--30

SCF Clock f = 8 kHz
TA=25°C
Input = ±3-V Sine wave

10

0

~

4.5

I

-50
-60

5

Frequency - kHz

o

50 100 150 200 250 300 350 400 450 500

Normalized Frequency _ kHz x AiD Conversion Rate
8 k samples/s

Figure 14

Figure 15

~TEXAS

INSTRUMENTS
4-68

........

AIC RECEIVE·CHANNEL
HIGH·PASS FILTER

20

'0

"-

Figure 13

AIC RECEIVE·CHANNEL
BANDPASS FILTER

m

V

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
.
SCF Clock Frequency
Normalized Frequency - kHz x--------'----=
288 kHz

5

Normalized Frequency _ kHz x SCF Clock Frequency
288 kHz

'0
I

2~8 kH~

clock} =
TA=25°C
Input = ±3-V Sine wave

10

POST OFFice BOX 655303 • DALLAS, TeXAS 75265

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE·BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

TYPICAL CHARACTERISTICS
AIC RECEIVE CHANNEL
BANDPASS FILTER

AIC (sin x)/x CORRECTION FILTER
5

Low·Pass SCF Clock f = 288 kHz
2.S

.,

f-

f- Hlgh·Pass SCF Clock f = 8 kHz

4.S

-

TA = 2SoC
Input = ±3·V Sine wave

f-4

..

'0

.
I

~

1.S

Q.

'2"
CJ

)

/

1.0

\

O.S

l...-

.......

3

:E

'0

2.S

"'"

:Ill

2

)

-7

1.S

\
l/
I-"

"-r--

0.5

.-V

0
1

1.5

2

2.5

3

3.5

V

/

0.0
0.5

~

il

m

I

~

I

3.S

2.0

E

>-

SCF Clock f = 288 kHz
TA=2SoC
Input = ±3·V Sine wave

4

4.5

O.S

5

1

/
1.5

2

2.S

3

3.S

4

4.S

S

Normalized Frequency _ kHz x SCF Clock Frequency
288 kHz

Frequency - kHz

. Figure 17

Figure 16

AID SIGNAL-TO-DISTORTION RATIO

vs
INPUT·SIGNAL LEVEL

AIC (sin x)/x CORRECTION FILTER
6

I I I

m

.

Filte/ '/

2

-

'0

I

'0

:!

~

0

r - r-....

C

Cl

,:Ill

,,/

/

Error

.........

-2

.........

"-

-4 I---6

V

(sin x)/x
Correction

4

o

-

0.5

1

1.5

2

2.5

3

3.5

4

1

-"
4.5

_I

1

1·kHz Input Signal
90 - 8·kHz Conversion Rate
1

80

70

x)~
'\
I I I I I I I
i\
DIA Converter (sin
.Distortion for TB Register = 36

100

60
50
40

Galn=1x

Gain=4x

-

V /
V

30
20
10

o

5

-SO

Normalized Frequency _ kHz x SCF Clock Frequency
288kHz

-40

-30

-20

-10

o

10

Input Signal Relative to Vref - dB

Figure 18

Figure 19

-!11 TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-69

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988- REVISED MAY 1995

TYPICAL CHARACTERISTICS
D/A CONVERTER SIGNAL·TO·DISTORTION RATIO
vs

AID GAIN TRACKING
(GAIN RELATIVE TO GAIN
AT O·dB INPUT·SIGNAL LEVEL)

INPUT·SIGNAL LEVEL

0.5

100

1.kH~ Input S~gnal I
0.4 ,- 8-kHz Conversion Rate

90

0.3

III

1.kHzl lnput Si~nal int~ 600 Q
8-kHz Conversion Rate

80

'D

III

I

0.2

I
CI

c
:;;

0.1

g

0

c

-0.1

C1

-0.2

~

70

o

~

'D

15

.

iq
i

'iij

/:

60

50

,/

40

~

/

""

30

CI

iii

-0.3
-0.4
-0.5
-SO

20
10

-40

-30

-20

o

-10

o

10

-10
-40
-30
-20
o
Input Signal Relative to Vref - dB

-50

Input Signal Relative to Vref - dB

Figure 21

Figure 20
D/A GAIN TRACKING
(GAIN RELATIVE TO GAIN
AT O·dB INPUT·SIGNAL LEVEL)

AID SECOND HARMONIC DISTORTION

vs
INPUT·SIGNAL LEVEL

0.5
0.4

-100
l-kHz Input Signal into 600 Q
8-kHz Conversion Rate

l-kHz Input Signal

-90 8-kHz Conversion Rate

!g

0.3

-80

c

0.2

o

'D

I
CI

c
:;;

0.1

.

0

c

-0.1



c

-70

'E0

-60

()

-50

~

-50

0

..E
:z:
1?

~

-20

UI

-10

...

~~

-40
-30
-20
-10

o
-50

V
./

'E

-40

c

0

-80

0

:z: -30
'0
()

1-kHz Input Signal
8-kHz Conversion Rate

-40

-30

-20

-10

o

o-50

10

-40

Input Signal Relative to Vref - dB

-30

-20

-10

o

10

Input Signal Relative to Vref - dB

Figure 24

Figure 25
D/A THIRD HARMONIC DISTORTION

vs
INPUT-SIGNAL LEVEL
-100
-90
III
'0
I

1-kHz Input Signal into 600 Q
8-kHz Conversion Rate

-80

c

-70

'E0

-60

0

~

Q

()

'c0

E

:;;

-50

.--/'"

./'

-

~

\

-40

:z: -30
1?

:c

I-

-20
-10

o-50

-40

-30

-20

-10

o

10

Input Signal Relative to Vref - dB

Figure 26

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-71

TLC32044C, TLC32044E, TLC320441, TLC32044M, TLC32045C, TLC320451
VOICE· BAND ANALOG INTERFACE CIRCUITS
SLAS017F - MARCH 1988 - REVISED MAY 1995

APPLICATION INFORMATION
TMS(SMJ)32020/C25

TlC32044ITlC32045

ClKOUT 1---- 288 kHz, please call the factory.
To obtain the specified filter response, the combination of master clock frequency and the TX(A) counter
and the RX(A) counter values must yield a 288-kHz switched-capacitor clock signal. This 288-kHz clock
signal can then be divided by the TX(B) counter to establish the D/A conversion timing.
The transfer function of the band-pass switched-capacitor filter in the AID path (see Functional Block
Diagram) is a composite of its high-pass and low-pass transfer functions. When the shift-clock frequency
(SCF) is 288 kHz, the high-frequency roll-off of the low-pass section will meet the band-pass filter transfer
function specification. Otherwise, the high-frequency roll-off is frequency-scaled by the ratio of the
high-pass section SCF clock to 288 kHz (see Figure 5-5). The low-frequency roll-off of the high-pass section
meets the band-pass filter transfer function specification when the AID conversion rate is 16 kHz. If not, the
low-frequency roll-off of the high-pass section is frequency-scaled by the ratio of the AID conversion rate
to 16 kHz.
The TX(A) counter and the TX(B) counter are reloaded each D/A conversion period, while the RX(A) counter
and the RX(B) counter are reloaded every AID conversion period. The TX(B) counter and the RX(B) counter
are loaded with the values in the TB and RB registers, respectively. Via software control, the TX(A) counter
can be loaded with the TA register, the TA register less the TA' register, or the TA register plus the TN register.
By selecting the TA register less the TN register option, the upcoming conversion timing occurs earlier by
an amount of time that equals TN times the signal period of the master clock. If the TA register plus the TN
register option is executed, the upcoming conversion timing occurs later by an amount of time that equals
TN times the signal period of the master clock. Thus, the D/A conversion timing can be advanced or
retarded. An identical ability to alter the AID conversion timing is provided. However, the RX(A) counter can
be programmed via software control with the RA register, the RA register less the RN register, or the RA
register plus the RN register.
The ability to advance or retard conversion timing is particularly useful for modem applications. This feature
allows controlled changes in the AID and D/A conversion timing and can be used to enhance signal-to-noise
performance, to perform frequency-tracking functions, and to generate nonstandard modem frequencies.
If the transmit and receive sections are configured to be synchronous, then the low-pass and band-pass
switched-capacitor filter clocks are derived from the TX(A) counter. Also, both the D/A and AID conversion
timings are derived from the TX(A) counter and the TX(B) counter. When the transmit and receive sections
are configured to be synchronous, the RX(A) counter, RX(B) counter, RA register, RN register, and RB
registers are not used.

4-88

TMS320 DSP
MASTER CLOCK

5.184 MHz
10.368 MHz

SHIFT CLOCK
1.296 MHz
2.592 MHz

TA' REGISTER
(6 Bits)
SCFCLOCK
Low-Pass Filter,
(sin x)/x Filter
Transmit Section
D/A Conversion
Timing
7.20 kHz
8.00 kHz
9.60 kHz
14.4 kHz
16.0 kHz
19.2 kHz

TX (A) Counter
(6 Bits)

....._ _.....;...--It---'----i

'--------'

576kHz

288 kHz

TX (B) Counter

L...._ _ _ _.....

for
for
for
for
for
for

TB = 40
TB = 36
TB = 30
TB = 20
TB = 18
TB = 15

D/A Conversion
Frequency

SCF CLOCK
Low-Pass Filter

Receive Section
AID Conversion
Timing
D1t DO SELECT
o 0 RA
1 RA + RA'
1 0 RA-RA'
1
1 RA

o

!jl.;lt""::J~H~lflj
RX (A) Counter
(6 Bits)

7.20 kHz
8.00 kHz
9.60 kHz
14.4 kHz
16.0 kHz
19.2 kHz

for
for
for
for
for
for

RB = 40
RB = 36
RB = 30
RB = 20
RB = 18
RB = 15

n~deiBv:21--L~ RX (B) Counter 1 - - - - - - - - - .
High-Pass Filter,
AID Conversion
Frequency

t

These control bits are described in the DX Serial Data Word Format section.
NOTES: A. Tables 2-2 and 2-3 are primary and secondary communication protocols, respectively.
8. In synchronous operation, RA, RA', R8, RX(A), and RX(8) are not used. TA, TA', T8, TX(A), and TX(8) are
used instead.
C. Items in italics refer only to frequencies and register contents, which are variable. A crystal oscillator driving
20.736 MHz into the TMS320-series DSP provides a master clock frequency of 5.184 MHz. The TLC32046
produces a shift clock frequency of 1.296 MHz. If the TX(A) register contents equal 9, the SCF clock
frequency is 288 kHz, and the D/A conversion frequency is 288 kHz + T(8).

Figure 2-1. Asynchronous Internal Timing Configuration

4-89

2.2

Analog Input

Two pairs of analog inputs are provided. Normally, the IN+ and IN~ input pair is used; however, the auxiliary
input pair, AUX IN+ and AUX IN-, can be used if a second input is required. Since sufficient common-mode
range and rejection are provided, each input set can be operated in differential or single-ended modes. The
gain for the IN+, IN-, AUX IN+, and AUX IN- inputs can be programmed to 1,2, or 4 (see Table 4-1). Either
. input circuit can be selected via software control. Multiplexing is controlled with the D4 bit (enable/disable
AUX IN+ and AUX IN-) of the secondary DX word (see Table 2-3). The multiplexing requires a 2-ms wait
at SCF = 288 kHz (see Figure 5-3) for a valid output signal. A wide dynamic range is ensured by the
differential internal analog architecture and the separate analog and digital voltage supplies and grounds.

2.3

AID Band-Pass Filter, Clocking,and Conversion Timing

The receive-channel AID high-pass filter can be selected or bypassed via software control (see Functional
Block Diagram). The frequency response of this filter is found in the electrical characteristic section. This
response results when the switched-capacitor filter clock frequency is 288 kHz and the A/D sample rate is
16 kHz. Several possible options can be used to attain a 288-kHz switched-capacitor filter clock. When the
filter clock frequency is not 288 kHz, the low-pass filter transfer function is frequency-scaled by the ratio of
the actual clock frequency to 288 kHz (see Typical Characteristics section). The ripple bandwidth and 3-dB
low-frequency roll-off points of the high-pass section are 300 Hz and 200 Hz, respectively. However, the
high-pass section low-frequency roll-off is frequency-scaled by the ratio of the A/D sample rate to 16 kHz.
Figure 2-1 and the DX serial data word format sections of this data manual indicate the many options for
attaining a 288-kHz band-pass switched-capacitor filter clock. These sections indicate that the RX(A)
counter can be programmed to give a 288-kHz band-pass switched-capacitor filter clock for several master
clock input frequencies.
The AID conversion rate is attained by frequency-dividing the band-pass switched-capacitor filter clock with
the RX(B) counter. Unwanted aliasing is prevented because the AID conversion rate is an integer
submultiple of the band-pass switched-capacitor filter sampling rate, and the two rates are synchronously
locked.

2.4

AID Converter

Fundamental performance specifications for. the receive channel ADC circuitry are in the electrical
characteristic section of this data manual. The ADC circuitry, using switched-capacitor techniques, provides
an inherent sample-and-hold function.

2.5

Analog Output

The analog output circuitry is an analog output power amplifier. Both non inverting and inverting amplifier
outputs are brought out of the IC. This amplifier can drive transformer hybrids or low-impedance loads
directly in either a differential or single-ended configuration.

2.6

DIA Low-Pass Filter, Clocking, and Conversion Timing

The frequency response results when the low-pass switched-capacitor filter clock frequency is 288 kHz (see
equation 1). Like the AID filter, the transfer function of this filter is frequency-scaled when the clock frequency
is not 288 kHz (see Typical Characteristics section). A continuous-time filter is provided on the output of the
low-pass filter to eliminate the periodic sample data signal information, which occurs at multiples of the
288-kHz switched-capacitor clock feedthrough.
The D/A conversion rate is attained by frequenc.y-dividing the 288-kHz switched-capacitor filter clock with
the T(B) counter. Unwanted aliasing is prevented because the D/A conversion rate is an integer submultiple
of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously locked.

2.7

DIA Converter

Fundamental performance specifications for the transmit channel DAC circuitry are in the electrical
charactenistic section. The DAC has a sample-and-hold function that is realized with a switched-capacitor
ladder.
4-90

2.8

Serial Port

The serial port has four possible configurations summarized in the function table on page 1-2. These
configurations are briefly described below.

2.9

•

The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS320Ci7. The communications protocol is two a-bit bytes.

•

The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS32020, TMS320C25, and TMS320C30. The communications protocol is
one 16-bit word.

•

The transmit and receive sections are operated synchronously, and the serial port interfaces
directly with the TMS320C17. The communications protocol is two a-bit bytes.

•

The transmit and receive sections are operated synchronously, and the serial port interfaces
directly with the TMS32020, TMS320C25, TMS320C30, or two SN74299 serial-to-parallel shift
registers, which can interface in parallel to the TMS32010, TMS320C15, to any other digital
signal processor, or to external FIFO circuitry. The communications protocol is one 16-bit word.

Synchronous Operation

When the transmit and receive sections are operated synchronously, the low-pass filter clock drives both
low-pass and band-pass filters (see Functional Block Diagram). The AID conversion timing is derived from
and equal to the D/A conversion timing. When data bit 05 in the control register is a logic 1, transmit and
receive sections are synchronous. The band-pass switched-capacitor filter and the AID converter thning are
derived from the TX(A) counter, the TX(B) counter, and the TA and TA' registers. In synchronous operation,
both the AID and the D/A channels operate from the same frequencies. The FSX and the FSR timing is
identical during primary communication, but FSR is not asserted during secondary communication because
there is no new AID conversion result.

2.9.1

One 16-Bit Word (Dual-Word [Telephone Interface] or Word Mode)

The serial port interfaces directly with the serial ports of the TMS32020, TMS320C25, and the TMS320C30,
and communicates in one 16-bit word. The operation sequence is as follows:
1.
2.
3.
4.

The FSX and FSR pins are brought low by the TLC32046 AIC.
One 16-bit word is transmitted and one 16-bit word is received.
FSX and FSR are brought high.
EODX and EODR emit low-going pulses one shift clock wide. EODX and EODR are valid in the
word or byte mode only.

If the device is in the dual-word (telephone interface) mode, FSD goes low during the secondary
communication period and enables the data word received at the DATA-DR/CONTROL input to be routed
to the DR line. The secondary communication period occurs four shift clocks after completion of primary
communications.

2.9.2

Two a-Bit Bytes (Byte Mode)

The serial port interfaces directly with the serial port of the TMS320C17 and communicates in two a-bit
bytes. The operation sequence is as follows:
1.
2.
3.
4.
5.
6.
7.

FSX and FSR are brought low.
One a-bit word is transmitted and one a-bit word is received.
EODX and EODR are brought low.
FSX and FSR emit positive trame-sync pulses that are four shift clock cycles wide.
One a-bit byte is transmitted and one a-bit byte is received.
FSX and FSR are brought high.
EODX and EODR are brought high.
4-91

2.9.3

Synchronous Operating Frequencies

The synchronous operating frequencies are determined by the following equations.
Switched capacitor filter (SCF) frequencies (see Figure 2-1):
Low-pass SCF clock frequency

(D/A and AID channels)

master clock frequehcy
T(A) x 2

High-pass SCF clock frequency (AID channel) = AID conversion frequency
Conversion frequency (AID and D I A channels)

low-pass SCF clock frequency
T(B)
master clock frequency
T(A) x 2 x T(B)

NOTE: T(A), T(B), R(A), and R(B) are the contents of the TA, TB, RA, and RB registers, respectively.

2.10 Asynchronous Operation
When the transmit and the receive sections are operated asynchronously, the low-pass and band-pass filter
clocks are independently generated from the master clock. The D/A and the AID conversion timing is also
determined independently.

D/A timing is set by the counters and registers described in synchronous operation, but the RA and RB
registers are substituted for the TA and TB registers to_determine the AID channel sample rate and the AID
path switched-capacitor filter frequencies. Asynchronous operation is selected by control register bit D5
~~~~
.

2.10.1

One 16-Bit Word (Word Mode)

The serial port interfaces directly with the serial ports of the TMS32020, TMS320C2S, and TMS320C30 and
communicates with 16-bit word formats. The operation sequence is as follows:
1.
2.
3.
4.

2.10.2

FSX or FSR are brought low by the TLC32046 AIC.
One 16-bit word is transmitted or one 16-bit word is received.
FSX or FSR are brought high.
EODX or EODR emit low-going pulses one shift clock wide. EODX and EODR are valid in either
the word or byte mode only.

Two 8-Bit Bytes (Byte Mode)

The serial port interfaces directly with the serial port of the TMS320C17 and communicates in two 8-bit
bytes. The operating sequence is as follows:
1.
2.
3.
4.
5.
6.
7.

2.10.3

FSX or FSR are brought low by the TLC32046 AIC.
One byte is transmitted or received.
EODX or EODR are brought low.
FSX or FSR are brought high for four shift clock periods and then brought low.
The second byte is transmitted or received.
FSX or FSR are brought high.
EODX or EODR are brought high.

Asynchronous Operating Frequencies

The asynchronous operating frequencies are determined by the following equations.
Switched-capacitor filter frequencies (see Figure 2-1):
Low-pass D/A SCF clock frequency =

4-92

master clock frequency.
T(A) x 2

Low-pass AID SCF clock frequency =

master clock frequency
R(A) x 2

High-pass SCF clock frequency (AID channel) = AID conversion frequency

(2)

Conversion frequency:
DI A conversion frequency

.

A I D conversion frequency =

low-pass D/A SCF clock frequency
T(8)

low-pass AID SCF clock frequency (for low pass receive filter)
R(8)

(3)

NOTE: T(A), T(8), R(A), and R(8) are the contents of the TA, T8, RA, and R8 registers, respectively.

2.11 Operation of TLC32046 With Internal Voltage Reference
The internal reference of the TLC32046 eliminates the need for an external voltage reference and provides
overall circuit cost reduction. The internal reference eases the design task and provides complete control
of the IC performance. The internal reference is brought out to REF. To keep the amount of noise on the
reference signal to a minimum, an external capacitor can be connected between REF and ANLG GND.

2.12 Operation of TLC32046 With External Voltage Reference
REF can be driven from an external reference circuit. This external circuit must be capable of supplying
250 ~A and must be protected adequately from noise and crosstalk from the analog input.
..

2.13 Reset
A reset function is provided to initiate serial communications between the AIC and DSP and to allow fast,
cost-effective testing during manufacturing. The reset function initializes all AIC registers, including the
control register. After a negative-going pulse on RESET, the AIC is initialized. This initialization allows
normal serial port communications activity to occur between AIC and DSP (see AIC DX Data Word Format
section). After RESET, TA= T8=RA=R8=18 (or 12 hexadecimal), TA'=RA'=01 (hexadecimal), the AID
high-pass filter is inserted, the loop-back function is deleted, AUX IN+ and AUX IN- are disabled, transmit
and receive sections are in synchronous operation, programmable gain is set to 1, the on-board (sin x)/x
correction filter is not selected, D100UT is set to 0, and D110UT is set to O.

2.14 Loopback
This feature allows the circuit to be tested remotely. In loopback, OUT+ and OUT-are internally connected
to IN+ and IN-. The DAC bits (D15 to D2), which are transmitted to DX, can be compared with the ADC bits
(D15 to D2), received from DR. The bits on DR equal the bits on DX. However, there is some difference in
these bits due to the ADC and DAC output offsets.
The loopback feature is implemented with digital signal processor control by transmitting a logic 1 for data
bit D3 in the DX secondary communication to the control register (see Table 2-3).

4-93

2.15 Communications Word Sequence
In the dual-word (telephone interface) mode, there are two data words that are presented to the DSP or ~P
from the DR terminal. The first data word is the ADC conversion result occurring during the FSR time, and
the second is the serial data applied to DATA-DR during the FSD time. FSR is not asserted during secondary
communications and FSD is not asserted during primary communications.
Primary
Communications

I

I

4 Shift
Clocks

Secondary
Communications

~

14
DX-14 Bits Digital 11
From DSP to DAC

Input for D/A
Conversion

DX

Input for Register
Program

TLC32046

I
2s Complement Output
From ADC to the DSP

FSR

I

I

I

I
I
I
I

I
I
I
I

I

FSD

I

14--I

16 bits Digital From
DATA-DR to DR

TLC32046
Dual-Word
(telephone interface)
Mode Only

I

TLC32046
Dual-Word
(telephone interface)
Mode Only

I

TLC32046
Dual-Word
(telephone interface)
Mode Only

Data From DATA-DR
to the DSP

2s Complement Output
From ADC to the DSP

DR

TLC32046

DX-14 Bits Digital XX
From DSP

I

I

16 bits - -..
~

14-----

I

I

16 bits - -..
~

I

Figure 2-2. Primary and Secondary Communications Word Sequence

2.15.1

DR Word Bit Pattern

The data word is the 14-bit conversion result of the receive channel to the processor in 2s complement
format. With 16-bit processors, the data is 16 bits long with the two LSBs at zero.
AID MSB
AID LSB

1st bit sent

.t
015

4-94

.t

I 014 I 013 I 012 I 011 I 010 I

09

I

08

I

07

I

06

I

05

I

04

I

03

I

02

I

01

I

DO

2.15.2

Primary OX Word Bit Pattern

Using 8-bit processors, the data word is transmitted in the same order as one 16-bit word, but as two bytes
with the two LSBs of the second byte set to zero.
AID OR O/A MSB
1st bit sent

1st bit sent of 2nd byte

AID or 01 A LSB

J,

J,

J,
D15

I 014 I D13 I 012 I 011 I 010 I

09

I

08

I

07

I

06

I

05

I

04

I

D3

I

02

I

D1

I

00

Table 2-2. Primary OX Serial Communication Protocol
01

00

D15 (MSB)-D2 --7 OAC Register.
TA --7 TX(A), RA --7 RX(A) (see Figure 2-1).
TB --7 TX(B), RB --7 RX(B) (see Figure 2-1).

0

0

015 (MSB)-02 --7 OAC Register.
TA+TA' --7 TX(A), RA+RA' --7 RX(A) (see Figure 2-1).
TB --7 TX(B) , RB --7 RX(B) (see Figure 2-1).
The next O/A and AlO conversion period is changed by the addition of TA' and RA' master clock cycles,
in which TA' and RA' can be positive, negative, or zero (refer to Table 2-4).

0

1

015 (MSB)-02 --7 DAC Register.
TA-TA' --7 TX(A), RA-RA' --7 RX(A) (see Figure 2-1).
TB --7 TX(B), RB --7 RX(B) (see Figure 2-1).
The next O/A and AiO conversion period is changed by the subtraction of TA' and RA' master clock cycles,
in which TA' and RA' can be positive, negative, or zero (refer to Table 2-4).

1

0

015 (MSB)-02 --7 OAC Register.
TA --7 TX(A), RA --7 RX(A) (see Figure 2-1).
TB --7 TX(B), RB --7 RX(B) (see Figure 2-1).
After a delay of four shift cycles, a secondary transmission follows to program the AIC to operate in the
desired configuration. In the telephone interface mode, data on OATA DR is routed to OR during
secondary transmission.

1

1

FUNCTIONS

NOTE: Setting the two least significant bits to 1 in the normal transmission of OAC information (primary communications)
to the AIC initiates secondary communications upon completion of the primary communications. When the
primary communication is complete, FSX remains high for four SHIFT CLOCK cycles and then goes low and
initiates the secondary communication. The timing specifications for the primary and secondary communications
are identical. In this manner, the secondary communication, if initiated, is interleaved between successive
primary communications. This interleaving prevents the secondary communication from interfering with the
primary communications and OAC timing. This prevents the AIC from skipping a OAC output. FSR is not asserted
during secondary communications activity. However, in the dual-word (telephone interface) mode, FSO is
asserted during secondary communications but not during primary communications.

4-95

2.15.3

Secondary OX Word Bit Pattern

D/A MSB
1st bit sent

t
D15

D/A LSB

1st bit sent of 2nd byte

J-

J-

I D14 I D13 I D12 I D11 I D10 I

D9

I

D8

I

D7

I

I

D6

D5

I

D4

I

D3

I

D2

I

D1

I

DO

Table 2-3. Secondary OX Serial Communication Protocol
01

DO

D13 (MSB)-D9 ~ TA, 5 bits unsigned binary (see Figure 2-1).
D6 (MSB)-D2 ~ RA, 5 bits unsigned binary (see Figure 2-1).
D15, D14, D8, and D7 are unassigned.

FUNCTIONS

0

0

D14 (sign bit)-D9 ~ TA', 6 bits 2s complement (see Figure 2-1).
D7 (sign bit)-D2 ~ RA', 6 bits 2s complement (see Figure 2-1).
D 15 and D8 are unassigned.

0

1

D14 (MSB)-D9 ~ TB, 6 bits unsigned binary (see Figure 2-1).
D7 (MSB)-D2 ~ RB, 6 bits unsigned binary (see Figure 2-1).
D15 and D8 are unassigned.

1

0

D2 = 0/1 deletes/inserts the AID high-pass filter.
D3 = 0/1 deletes/inserts the loopback function.
D4 = 0/1 disables/enables AUX IN+ and AUX IN-.
D5 = 0/1 asynchronous/synchronous transmit and receive sections.
D6 = 0/1 gain control bits (see Table 4-1).
D7 = 0/1 gain control bits (see Table 4-1).
D9 = 0/1 delete/insert on-board second-order (sinx)/x correction filter
D10 = 0/1 output to D1 OOUT (dual-word (telephone interface) mode)
D11 = 0/1 output to D11 OUT (dual-word (telephone interface) mode)
D8, D12-D15 are unaSSigned.

1

1

2.16 Reset Function
A reset function is provided to initiate serial communications between the Ale and DSP. The reset function
initializes all Ale registers, including the control register. After power has been applied to the Ale, a
negative-going pulse on RESET initializes the Ale registers to provide a 16-kHz AID and DfA conversion
rate for a 10.368-MHz master clock input signal. Also, the pass-bands of the AID and DfA filters are 300
Hz to 7200 Hz and 0 Hz to 7200 Hz, respectively; therefore, the filter bandwidths are half those shown in
the filter transfer function specification section. The Ale, except the CONTROL register, is initialized as
follows (see Ale DX Data Word Format section):
REGISTER
INITIALIZED VALUE (HEX)

TA
12

TA'
01

TB
12

RA
12

RA'
01

RB
12

The CONTROL register bits are reset as follows (see Table 2-3):
D11

= 0,

D10

= 0,

D9

= 1, D7 = 1, D6 = 1, D5 = 1, D4 = 0,

D3

= 0,

D2

=1

This initialization allows normal serial port communications to occur between the AIC and the DSP. If the
transmit and receive sections are configured to operate synchronously and the user wishes to program
different conversion rates, only the TA, TA', and TB register need to be programmed. Both transmit and
receive timing are synchronously derived from these registers (see the Terminal Functions and DX Serial
Data Word Format sections).
Figure 2-3 shows a circuit that provides a reset on power-up when power is applied in the sequence given
in the power-up sequence section. The circuit depends on the power supplies reaching their recommended
values a minimum of 800 ns before the capacitor charges to 0.8 V above DGTL GND.
4-96

TLC32046

VCC+

5V

0.5 iJ.F
VCC-

-5V

Figure 2-3. Reset on Power-Up Circuit

2.17 Power-Up Sequence
To ensure proper operation of the Ale and as a safeguard against latch-up, it is recommended that Schottky
diodes with forward voltages less than or equal to 0.4 V be connected from VCC- to ANLG GND and from
VCC- to DGTL GND. In the absence of such diodes, power is applied in the following sequence: ANLG GND
and DGTL GND, VCC-, then VCC+ and Voo. Also, no input signal is applied until after power-up.

2.18 AIC Register Constraints
The following constraints are placed on the contents of the Ale registers:
TA register must be ~ 4 in word mode (WORD/BYTE= high).
TA register must be ~ 5 in byte mode (WORD/BYTE= low).
3. TN register can be either positive, negative, or zero.
4. RA register must be ~ 4 in word mode (WORD/BYTE == high).
5. RA register must be ~ 5 in byte mode (WORD/BYTE = low).
6. RA' register can be either positive, negative, or zero.
7. (TA register ± TA' register) must be > 1.
8. (RA register ± RN register) must be > 1.
9. TB register must be ~ 15.
10. RB register must be ~ 15.
1.
2.

2.19 AIC Responses to Improper Conditions
The Ale has provisions for responding to improper conditions. These improper conditions and the response
of the Ale to these conditions are presented in Table 2-4.

4-97

Table 2-4. AIC Responses to Improper Conditions
IMPROPER CONDITION
TA register + TA' register = 0 or 1
TA register - TA' register = 0 or 1

AIC RESPONSE
Reprogram TX(A) counter with TA register value

TA register + TA' register < 0

MODULO 64 arithmetic is used to ensure that a positive value is loaded into
TX(A) counter, i.e., TA register + TA' register + 40 HEX is loaded into TX(A)
counter.

RA register + RN register = 0 or 1
RA register - RN register = 0 or 1

Reprogram RX(A) counter with RA register value

RA register + RA' register = 0 or 1

MODULO 64 arithmetic is used to ensure that a positive value is loaded into
RX(A) counter, i.e., RA register + RA' register + 40 HEX is loaded into RX(A)
counter.

TA register = 0 or 1
RA register = 0 or 1

AIC is shut down. Reprogram TA or RA registers after a reset.

TA register < 4 in word mode
TA register < 5 in byte mode
RA register < 4 in word mode
RA register < 5 in byte mode

The AIC serial port no longer operates. Reprogram TA or RA registers after
a reset.

TB register < 15
RB register < 15
AIC and DSP cannot communicate

Reprogram TB register with 12 HEX
Reprogram RB register with 12 HEX
Hold last DAC output

2.20 Operation With Conversion Times Too Close Together
If the difference between two successive OfA conversion frame syncs is less than 1/25 kHz, the AIC
operates improperly. In this situation, the second OfA conversion frame sync occurs too quickly, and there
is not enough time for the ongoing conversion to be completed. This situation can occur if the A and B
registers are improperly programmed or if the A + A' register result is too small. When incrementally
adjusting the conversion period via the A + A' register options, the designer should not violate this
requirement (see Figure2-4).
Frame sYnclt1
(FSX or FSR)

..._ _......

I+-t2 - t1

S;

r - - - -.......(J'!""(J_ _ _-.t2

Ongoing Conversion

1

r-

...._ _....1

---'1

1/25 kHz

Figure 2-4. Conversion Times Too Close Together

2.21 More Than One Receive Frame Sync Occurring Between Two Transmit
Frame Syncs - Asynchronous Operation
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the AIC
during an FSX frame sync. The ongoing conversion period is then adjusted; however, either receive
conversion period A or conversion period B can be adjusted. For both transmit and receive conversion
periods, the incremental conversion period adjustment is performed near the end of the conversion period.
If there is sufficient time between t1 and t2, the receive conversion period adjustment is performed during
receive conversion period A. Otherwise, the adjustment is performed during r~ceive conversion period B.
The adjustment command only adjusts one transmit conversion period and one receive conversion period.
To adjust another pair of transmit and receive conversion periods, another command must be issued during
a subsequent FSX frame (see Figure 2-5).

4-98

u
1
.
+
.,
-

-

-

-

Transmit Conversion Period

I I"
Receive Conversion
Period A

·1

-------+I.,U

I

Receive Conversion
Period B

Figure 2-5. More Than One Receive Frame Sync Between Two Transmit Frame Syncs

2.22 More Than One Transmit Frame Sync Occurring Between Two Receive
Frame Syncs - Asynchronous Operation
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol must be followed. For both transmit and receive conversion periods, the incremental conversion
period adjustment is performed near the end of the conversion period. The command to use the incremental
conversion period adjust options is sent to the AIC during an FSX frame sync. The ongoing transmit
conversion period is then adjusted. However, three possibilities exist for the receive conversion period
adjustment as shown in Figure 2-6. When the adjustment command is issued during transmit conversion
period A, receive conversion period A is adjusted if there is sufficient time between t1 and t2' If there is not
sufficient time between t1 and t2, receive conversion period B is adjusted. The third option is that the receive
portion of an adjustment command can be ignored if the adjustment command is sent during a receive
conversion period, which is adjusted due to a prior adjustment command. For example, if adjustment
commands are issued during transmit conversion periods A, B, and C, the first two commands may cause
receive conversion periods A and B to be adjusted, while the third receive adjustment command is ignored.
The third adjustment command is ignored since it was issued during receive conversion period B, which
already is adjusted via the transmit conversion period B adjustment command.

,
j4-

1

Transmit
,
Transmit
,
Transmit
,
Conversion -¥- Conversion--¥- conversion ...... ,
Period A
1
Period B
1 Period C

FSFiU

r--

Receive Conversion Period A

+U

Receive Conversion Period B

4

L.J

Figure 2-6. More Than One Transmit Frame Sync Between Two Receive Frame Syncs

2.23 More than One Set of Primary and Secondary DX Serial Communications
Occurring Between Two Receive Frame Syncs (See DX Serial Data Word
Format section) - Asynchronous Operation
The TA, TA', TB, and control register information that is transmitted in the secondary communication is
accepted and applied during the ongoing transmit conversion period. If there is sufficient time between t1
and t2, the TA, RA', and RB register information, sent during transmit conversion period A, is applied to
receive conversion period A; otherwise, this information is applied during receive conversion period B. If RA,
RA', and RB register information has been received and is being applied during an ongoing conversion
period, any subsequent RA, AA', or RB information received during this receive conversion period is
disregarded (see Figure 2-7).
4-99

Primary

FS~

I

n

Secondaryt1

-I~I

I

Transmit
j4--- Conversion
Preload A

Receive

Primary

~14

n

Secondary

Primary

-I~I

n

Secondary

I~L

Transmit
I
Transmit
I
Conversion ---+Io~f---- Conversion --""~I
Preload B
Preload C

I I-----...I
' - I_ . . . . . .

Receive

+-- Conversion - _____~1414------ Conversion
Period A

1

------~~I

Period B

Figure 2-7. More Than One Set of Primary and Secondary OX
Serial Communications Between Two Receive Frame Syncs

2.24. System Frequency Response Correction
The (sin x)/x correction for the DAC zero-order sample-and-hold output can be provided by an on-board
second-order (sin x)/x correction filter (see Functional Block Diagram). This (sin x)/x correction filter can be
inserted into or omitted from the Signal path by digital-signal-processor control (data bit 09 in the OX
secondary communications). When inserted, the (sin x)/x correction filter precedes the switched-capacitor
low-pass filter. When the TB register (see Figure 2-1) equals 15, the correction results of Figures 5-5, 5-6,
and 5-7 can be obtained.
The (sin x)/x correction [see section (sin x)/x] can also be accomplished by disabling the on-board
second-order correction filter and performing the (sin x)/x correction in digital signal processor software. The
system frequency response can be corrected via DSP software to ± 0.1 dB accuracy to a band edge of
3000 Hz for all sampling rates. This correction is accomplished with a first-order digital correction filter, that
requires seven TMS320 instruction cycles. With a 200-ns instruction cycle, seven instructions represent an
overhead factor of 1.1 % and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the (Sin x)/x
Correction Section for more details).

2.25 (Sin x)/x Correction
If the designer does not wish to use the on-board second-order (sin x)/x correction filter, correction can be
accomplished in digital signal processor (DSP) software. (Sin x)/x correction can be accomplished easily
and efficiently in digital signal processor software. Excellent correction accuracy can be achieved to a band
edge of 3000 Hz by using a first-order digital correction filter. The results shown are typical of the numerical
correction accuracy that can be achieved for sample rates of interest. The filter requires seven instruction
cycles per sample on the TMS320 OS. With a 200-ns instruction cycle, nine instructions per sample
represents an overhead factor of 1.4% and 1.7% for s~mpling rates of 8000 Hz and 9600 Hz, respectively.
This correction adds a slight amount of group delay at the upper edge of the 300-Hz to 3000-Hz band.

2.26 (Sin x)/x Roll-Off for a Zero-Order Hold Function
The (sin x)/x roll-off error for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz
for the various sampling rates is shown in Table 2-5 (see Figure 5-7).

4-100

Table 2-5. (sin x)/x Roll-Off Error
sin 1t flfs
1t f/fs
f = 3000 Hz
(dB)

Error = 20 log
fs (Hz)

7200
8000
9600
14400
16000
19200
25000

-2.64
-2.11
-1.44
-0.63
-0.50
-0.35
-0.21

The actual Ale (sin x)/x roll-off is slightly less than the figures in Table 2-5 because the Ale has less than
100% duty cycle hold interval.

2.27 Correction Filter
To externally compensate for the (sin x)/x roll-off of the Ale, a first-order correction filter can be implemented
as shown in Figure 2-S.
U

(i + 1) ---1M

Y(i + 1)

p1

Figure 2-8. First-Order Correction Filter
The difference equation for this correction filter is:

Yo + 1) = p2 . (1 - p1) . Uo + 1) + p1 '. Y(i)

(4)

where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
(p2)2 V (1-p1)2

I H (f) I 2 = 1-2 V p1 V cos (2p flfs) + (p1 )2

(5)

2.28 Correction Results
Table 2-6 shows the optimum p values and the corresponding correction results for SOOO-Hz and 9600-Hz
sampling rates (see Figures 5-S, 5-9, and 5-10).

4-101

Table 2-6. (Sin x)fx Correction Table for fs = 8000 Hz and fs = 9600 Hz

f (Hz)

ROLL-OFF ERROR (dB)
fs = 8000 Hz

ROLL-OFF ERROR (dB)
fs = 9600 Hz

p1 = -0.14813
p2 = 0.9888

p1 = -0.1307
p2 = 0.9951

300

-0.099

-0.043

600

-0.089·

-0.043

900

-0.054

0

1200

-0.002

0

1500

0.041

0

1800

0.079

0.043

2100

0.100

0.043

2400

0.091

0.043

2700

-0.043

0

3000

-0.102

-0.043

2.29 TMS320 Software Requirements
The digital correction filter equation can be written in state variable form as follows:
Y(i+1) = Y(i)' k1 + U(i+1) . k2

Where
k1 = p1
k2 = (1 - p1) p2
y(i) = filter state
u(i+ 1)

= next I/O sample

The coefficients k1 and k2 must be represented as 16-bit integers. The SACH instruction (with the proper
shift) yields the correct result. With the assumption that the TMS320 processor page pointer and memory
configuration are properly initialized, the equation can be executed in seven instructions or seven cycles
with the following program:
ZAC
LT K2
MPY U
LTA Kl
MPY Y
APAC
SACH (dma) ,

4-102

(shift)

3
3.1

Specifications
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)
Supply voltage range, VCC+ (see Note 1) .......................... -0.3 V to 15 V
Supply voltage range, Voo ....................................... -0.3 V to 15 V
Output voltage range, Va ........................................ -0.3 V to 15 V
Input voltage range, VI ........................................... -0.3 V to 15 V
Digital ground voltage range ...................................... -0.3 V to 15 V
Operating free-air temperature range: TLC32046C ................... O°C to 70°C
TLC320461 .................. -40°C to 85°C
TLC32046M ................ -55°C to 125°C
Storage temperature range: TLC32046C, TLC320461 ............. -40°C to 125°C
TLC32046M ........................ -65°C to 150°C
Case temperature for 10 seconds: FN or FK package ....................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds:
N or J package .................................................... 260°C

NOTE 1: Voltage values for maximum ratings are with respect to VCC-.

3.2

Recommended Operating Conditions
MIN

NOM

MAX

Supply voltage, VCC+ (see Note 2)

4.75

5

5.25

V

Supply voltage, Vcc- (see Note 2)

-4.75

-5

-5.25

V

4.75

5

5.25

V

4

V

Digital supply voltage, VDD (see Note 2)
Digital ground voltage with respect to ANLG GND, DGTL GND

0
2

Reference input voltage, Vreflextl (see Note 2)
High-level input voltage, VIH

2

Load resistance at OUT+ and/or OUT-, RL
MSTR CLK frequency (see Note 4)

V

100

pF

n
5

10.368
±1.5

Analog input amplifier common mode input voltage (see Note 5)
AID or D/A conversion rate

25
TLC32046C

0

V

0.8

300

Load capacitance at OUT + and/or OUT-, CL

Operating free-air temperature range, TA

V

VDD+0.3

-0.3

Low-level input voltage, VIL (see Note 3)

UNIT

MHz
V
kHz

70

TLC320461

-40

85

TLC32046M

-55

125

°c

NOTES: 2. Voltages at analog mputs and outputs, REF, VCC+, and VCC- are with respect to ANLG GND. Voltages at
digital inputs and outputs and VDD are with respect to DGTL GND.
3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used
in this data manual for logic voltage levels only.
4. The band-pass switched-capacitor filter (SCF) specifications apply only when the low-pass section SCF
clock is 288 kHz and the high-pass section SCF clock is 16 kHz. If the low-pass SCF clock is shifted from
288 kHz, the low-pass rOil-off frequency shifts by the ratio of the low-pass SCF clock to 288 kHz. If the
high-pass SCF clock is shifted from 16 kHz, the high-pass roll-off frequency shifts by the ratio of the
high-pass SCF clock to 16 kHz. Similarly, the low-pass switched-capacitor filter (SCF) specifications apply
only when the SCF clock is 288 kHz. If the SCF clock is shifted from 288 kHz, the low-pass roll-off frequency
shifts by the ratio of the SCF clock to 288 kHz.
5. This range applies when (IN+ - IN-) or (AU X IN+ - AUX IN-) equals ± 6 V.
4-103

3.3

3.3.1

Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, VCC+ 5 V, VCC- -5 V, VDD 5 V (Unless
Otherwise Noted)

=

=

=

Total Device, MSTR ClK Frequency =5.184 MHz, Outputs Not loaded
TEST CONDITIONS

PARAMETER
VOH

High-level output voltage

VDD = 4.75 V,

IOH = -300 IlA

VOL

Low-level output voltage

VDD = 4.75 V,

IOL=2 mA

MIN

TYPt

ICC-

Supply current from
VCC+

Supply current from
VCC-

UNIT
V

0.4

TLC32046C
ICC+

MAX

2.4

V

35

TLC320461

40

TLC32046M

45

TLC32046C

-35

TLC320461

-40

TLC32046M

-45

mA

mA

100

Supply current from VDD

Vref

Internal reference
output voltage

aVref

Temperature coefficient of internal
reference voltage

250

ppm/oC

ro

Output resistance at REF

100

kQ

3.3. 2

7

mA

TLC32046M

2.9

VCC+ or VCC _ supply voltage
rejection ratio, receive channel

TEST CONDITIONS
f = 0 kHz to 30 kHz
f = 30 kHz to 50 kHz

VCC+ or VCC _ supply voltage
rejection ratio, transmit channel
(single-ended)

f = 0 kHz to 30 kHz

Crosstalk attenuation, transmitto-receive (single-ended)

TLC32046C, I

Crosstalk attenuation, receiveto-transmit (single-ended)

f = 30 kHz to 50 kHz

,

MIN

TYPt

Idle channel, supply
signal at 200 mV p-p
measured at DR
(ADC output)

30

Idle channel, supply
signal at 200 mV p-p
measured at OUT +

30

UNIT

dB

dB
45
80
60

80

TLC32046M

70

80

MIN

TYPt

dB
dB

Serial Port
TEST CONDITIONS

VOH

High-level output voltage

IOH = -300

VOL

Low-level output voltage

IOL= 2 mA

II

Input current

II

input current, DATA-DR/CONTROL

!lA

UNIT
V

Input capacitance

15

Co

Output capacitance

15

All typical values are at TA = 25°C.

MAX

2.4

C·I

4-104

MAX

45

TLC32046M

PARAMETER

t

V

I Rejection
.
Power S uppy
an dC rossta IkAttenuatlon
PARAMETER

3.3.3

3.3

0.4

V

±10

IlA

±100

IlA
pF
pF

3.3.4

Receive Amplifier Input
TEST
CONDITIONS

PARAMETER

MIN

TYPt

MAX

10

70

AID converter offset error (filters in)
CMRR

Common-mode rejection ratio at IN+, IN-, or AUX
IN+, AUX IN-

q

Input resistance at IN+, IN- or
AUXIN+,AUXIN+,AUXIN-, REF

See Note 6

UNIT
mV

55

dB

100

kn

NOTE 6: The test condition is a O-dBm, 1-kHz input signal with a 16-kHz conversion rate.

3.3.5

Transmit Filter Output
TEST
CONDITIONS

TYPt

MAX

TLC32046C, I

15

80

mV

TLC32046M

15

85

mV

PARAMETER

VOO

VOM

t

Output offset voltage at OUT+ or
OUT- (single-ended relative to
ANLG GND)
Maximum peak output voltage
swing across RL at OUT+ or OUT(single-ended)

TLC32046C, I

Maximum peak output voltage
swing between OUT+ and OUT(differential output)

UNIT

RL<:: 300 n,
Offset voltage
=0

±3

V

RL<:: 600 n

±6

V

Ali typical values are at TA = 25°C.

3.3.6

Receive and Transmit Channel System Distortion, SCF Clock
Frequency 288kHz (see Note 7)

=

PARAMETER
Attenuation of second harmonic of
AID input signal

TEST CONDITIONS

MIN

Single-ended
Differential

Attenuation of third and higher
harmonics of AID input signal

Single-ended

Attenuation of second harmonic of
D/A input signal

Single-ended

Attenuation of third and higher
harmonics of D/A input signal

t

MIN

70
VI =-0.1 dBto-24dB

Differential

Differential
Single-ended
Differential

TYPt

62

70
65

57

65
70

VI = -0 dB to -24 dB

62

70
65

57

65

MAX

UNIT
dB

dB

dB

dB

Ali typical values are at TA = 25°C.

4-105

3.3.7

Receive Channel Signal-to-Distortion Ratio (see Note 7)
PARAMETER

TEST CONDITIONS

= -6 dB to -0.1 dB
VI = -12 dB to -6 dB
VI = -18 dB to -12 dB
VI = -24 dB to -18 dB
VI = -30 dB to -24 dB
VI = -36 dB to -30 dB
VI = -42 dB to -36 dB
VI = -48 dB to -42 dB
VI = -54 dB to -48 dB
VI

AID channel signal-todistortion ratio

Av= 1*
MIN

MAX

Av =4t

Av =2*
MIN

MAX

MIN

58

§

§

58

58

§

56

58

58

50

56

58

44

50

56

38

44

50

32

38

44

26

32

38

20

26

32

MAX

UNIT

dB

:j: Av is the programmable gain of the input amplifier.

§ Measurements under these conditions are unreliable due to overrange and signal clipping.
NOTE 7: The test condition is a 1-kHz input signal with a 16-kHz conversion rate. The load impedance for the DAC is
600 Q. Input and output voltages are referred to Vref.

3.3.8

Transmit Channel Signal-to-Distortion Ratio (see Note 7)
PARAMETER

TEST CONDITIONS

MIN

= -6 dB to -0.1 dB
VI = -12 dB to -6 dB
VI = -18 dB to -12 dB
VI = -24 dB to -18 dB
VI = -30 dB to -24 dB
VI = -36 dB to -30 dB
VI = -42 dB to -36 dB
VI = -48 dB to -42 dB
VI = -54 dB to -48 dB

D/A channel signal-to-distortion ratio

MAX

UNIT

58

VI

58
56
50
44

dB

38
32
26
20

NOTE 7: The test condition is a 1-kHz input signal with a 16-kHz conversion rate. The load impedance for the DAC is
600 Q. Input and output voltages are referred to Vref.

3.3.9

Receive and Transmit Gain and Dynamic Range (see Note 8)
PARAMETER

TEST CONDITIONS

Transmit gain tracking error

C,I

Receive gain tracking error

C, I

Transmit gain tracking error

M

Receive gain tracking error

M

Transmit gain tracking error

M

Receive gain tracking error

M

= -48 dB to 0 dB signal range
VI = -48 dB to 0 dB signal range
Va = -48 dB to 0 dB signal range,
TA = 25°C
VI = -48 dB to 0 dB signal range,
TA = 25°C
Va = -48 dB to 0 dB signal range,
TA = -55°C TO 125°C
Va

MIN

TYPt

MAX

UNIT

±0.05

±0.15

dB

±0.05

±0.15

dB

±0.05

±0.25

dB

±0.05

±0.25

dB

±O.4

dB

±O.4

dB

NOTE 8: Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 dB relative to Vref).

4-106

3.3.10

Receive Channel Band-Pass Filter Transfer Function, SCF fclock
Input (IN+ - IN-) Is A ±3-V Sine Wave* (see Note 9)

PARMETER

TEST
CONDITION

FREQUENCY

3.3.11

Input signal
reference is 0 dB

MIN

TYPt

MAX

-33

-29

-25

-4

-2

-1

K1 x 0 dB

-0.25

0

0.25

K1 x 0 dB

-0.3

0

0.3

0

0.5

K1 x 2.3 dB

-2

-0.5

K1 x 2.7 dB

-16

-14

ADJUSTMENT

f::; 100 Hz

K1 x 0 dB

= 200 Hz
f = 300 Hz to 6200 Hz
f = 6200 Hz to 6600 Hz
f = 6600 Hz to 7300 Hz
f = 7600 Hz
f = 8000 Hz

K1 x-O.26 dB

f ~ 8800 Hz

K1 x 3.2 dB

-40

f ~ 10000 Hz

K1 x 0 dB

-65

f

Filter gain

=288 kHz,

K1 x 0 dB

UNIT

dB

Receive and Transmit Channel Low-Pass Filter Transfer Function,
SCF fclock 288 kHz (see Note 9)

=

TEST
CONDITION

Filter gain

Input signal
reference is 0 dB

FREQUENCY
RANGE

ADJUSTMENT
ADDEND*

I

I

= 0 Hz to 6200 Hz
= 6200 Hz to 6600 Hz
f = 6600 Hz to 7300 Hz
f = 7600 Hz
f = 8000 Hz

I ~ 8800 Hz

K1 x 3.2 dB

-40

I ~ 10000 Hz

K1 x 0 dB

-65

MIN

TYPt

MAX

K1 x 0 dB

-0.25

0

0.25

K1 x 0 dB

-0.3

0

0.3

K1 x 0 dB

-0.5

0

0.5

K1 x 2.3 dB

-2

-0.5

K1 x2.7 dB

-16

-14

UNIT

dB

tAli typicaLvalues are atTA = 25°C.
:j: The MIN, TYP, and MAX specifications are given for a 288-kHz SCF clock frequency. A slight error in the 288-kHz SCF
may result from inaccuracies in the MSTR ClK Irequency, resulting from crystal Irequency tolerances. If this Irequency
error is less than 0.25%, the ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specifications,
where K1 = 100 • [(SCF frequency - 288 kHz)/288 kHz]. For errors greater than 0.25%, see Note 9.
NOTE 9: The filter gain outside of the pass band is measured with respect to the gain at 1 kHz (2 kHz for M version).
The filter gain within the pass band is measured with respect to the average gain within the pass band. The
pass bands are 300 Hz to 7200 Hz and 0 to 7200 Hz for the band-pass and low-pass filters, respectively. For
switched-capacitor filter clocks at frequencies other than 288 kHz, the lilter response is shifted by the ratio of
switched-capacitor filter clock frequency to 288 kHz.

4-107

3.4

Operating Characteristics Over Recommended Operating Free-Air
Temperature Range, VCC+ 5 V, VCC- -5 V, Voo 5 V

=

3.4.1

=

=

Receive and Transmit Noise (measurement includes low-pass and band-pass
switched-capacitor filters)
PARAMETER

Transmit
noise

MIN

TEST CONDITIONS

TYPt

MAX

Broadband with (sin x)/x

250

500

Broadband without (sin x)/x

200

450

o to 30 kHz with (sin x)/x
o to 30 kHz without (sin x)/x
o to 3.4 kHz with (sin x)/x
o to 3.4 kHz without (sin x)/x
o to 6.8 kHz with (sin x)/x

200

400

200

400

180

300

160

300

180

350

160

350

300

500

OX input = 00000000000000,
Constant input code

(wide-band operation with 7.2 kHz
roll-off)

UNIT

flVrms

o to 6.8 kHz without (sin x)/x
(wide-band operation with 7.2 kHz
roll-off)
Receive noise (see Note 10)

Inputs grounded,

Gain = 1

18

flVrms
dBrncO

t All typical values are at TA = 25°C.
NOTE 10: The noise is computed by statistically evaluating the digital output of the AJO converter.

3.5

Timing Requirements

3.5.1

Serial Port Recommended Input Signals, TLC32046C and TLC320461
PARAMETER

MIN

Master clock cycle time

tc(MCLK)

MAX

95

UNIT
ns

tr(MCLKJ

Master clock rise time

10

ns

tf(MCLK)

Master clock fall time

10

ns

Master clock duty cycle

25%

RESET pulse duration (see Note 11)
tsu(OX)

OX setup time before SCLK-l-

th(OX)

OX hold time after SCLK-l-

75%

800

ns

20

ns
ns

tc(SCLK)/4

NOTE 11: RESET pulse duration is the amount of time that the RESET is held below 0.8 V after the power supplies have
reached their recommended values.

3.5.2

Serial Port Recommended Input Signals, TLC32046M
PARAMETER

tc(MCLK)

Master clock cycle time

tr(MCLKJ.

Master clock rise time

tf(MCLK)

MIN

Master clock fall time

tsu(OX)

OX setup time before SCLK-l-

th(OX) .

OX hold time after SCLK-l-

MAX

UNIT
ns

95
10

ns

10

ns

50%

Master clock duty cycle
RESET pulse duration (see Note 11)

TYPt

800

ns

28

ns

tc(SCLK)!4

ns

NOTE 11: RESET pulse duration is the amount of time that the RESET is held below 0.8 V after the power supplies have
reached their recommended values.
4-108

3.5.3

Serial Port - AIC Output Signals, CL =30 pF for SHIFT ClK Output, CL
For All Other Outputs, TlC32046C and TlC320461
PARAMETER

MIN

Shift clock (SCLK) cycle time

tc(SCLK)

TYPt

=15 pF

MAX

380

UNIT
ns

tf(SCLK)

Shift clock (SCLK) fall time

3

8

ns

tr(SCLK)

Shift clock (SCLK) rise time

3

8

ns

Shift clock (SCLK) duty cycle

45%

55%

tc!(CH-FL)

Delay from SCLKi to FSR/FSXlFSD-l.

30

td(CH-FH)

Delay from SCLKi to FSRlFSXlFSDi

35

ns
90

ns

tc!(CH-DR)

DR valid after SCLKi

90

ns

td(CH-El)

Delay from SCLKi to EODXlEODR-l. in word mode

90

ns

tc!CCH-EH)

Delay from SCLKi to EODXlEODRi in word mode

90

ns

tf{EODX)

EODX fall time

2

8

ns

2

8

ns

tf{EODR)

EODR fall time

td(CH-EL)

Delay from SCLKi to EODX/EODR-l. in byte mode

90

ns

td(CH-EH)

Delay from SCLKi to EODXlEODRi in byte mode

90

ns

td(MH-SL)

Delay from MSTR CLKi to SCLK-l.

65

170

ns

td(MH-SH)

Delay from MSTR CLKi to SCLKi

65

170

ns

tTypical values are at TA = 25°C.

3.5.4

Serial Port - AIC Output Signals, CL
For All Other Outputs, TlC32046M

=30 pF for SHIFT ClK Output, CL =15 pF

PARAMETER
tc(SCLK)

Shift clock (SCLK) cycle time

tf(SCLK)

Shift clock (SCLK) fall time

tr(SCLK)

Shift clock (SCLK) rise time
Shift clock (SCLK) duty cycle

MIN

TYPt

MAX

400

UNIT
ns

3

ns
ns

3
45%

55%

tc!(CH-FL)

Delay from SCLKi to FSR/FSXlFSD-l.

30

250

ns

35

td(CH-FH)

Delay from SCLKi to FSRlFSXlFSDi

250

ns

tc!(CH-DR)

DR valid after SCLKi

250

ns

tc!(CH-EL)

Delay from SCLKi to EODXlEODR-l. in word mode

250

ns

td(CH-EH)

Delay from SCLKi to EODXlEODRi in word mode

250

ns

tf(EODX)

EODX fall time

2

tf(EODR)

EODR fall time

2

tc!(CH-EL)

Delay from SCLKi to EODXlEODR-l. in byte mode

250

ns

td(CH-EH)

Delay from SCLKi to EODXlEODRi in byte mode

250

ns

td(MH-SL)

Delay from MSTR CLKi to SCLK-l.

65

170

ns

td(MH-SH)

Delay from MSTR CLKi to SCLKi

65

170

ns

t Typical values are at TA

ns
ns

=25°C.

4-109

4-110

4 Parameter Measurement Information
Rfb
IN+
or
AUXIN+

R

INor
AUXIN-

R

I-+-__- }

To Mublplexe.

Rfb
Rfb=Rfor06= 1and07= 1
06 = 0 and 07 = 0
Rfb = 2R for 06 = 1 and 07 = 0
Rfb = 4R for 06 = 0, and 07 1

=

Figure 4-1. IN + and IN - Gain Control Circuitry
Table 4-1. Gain Control Table (Analog Input Signal Required for
Full-Scale Bipolar AID Conversion Twos Complement)t
INPUT
CONFIGURATIONS
Differential configuration
Analog input = IN + - IN= AUX IN+ - AUX IN-

Single-ended configuration
Analog input = IN + - ANLG GND
= AUX IN+ -ANLG GND

CONTROL REGISTER BITS
06

07

ANALOG
INPUTU

AID CONVERSION
RESULT

1

1

0

0

1

0

VID = ±3 V

±full scale

0

1

VID = ±1.5 V

±full scale

VI =±3 V

±hal! scale

VID =±6 V

±full scale

1

1

0

0

1

0

VI = ±3 V

±full scale

0

1

VI =±1.5 V

±full scale

tvcc+ = 5 V, VCC-=-5 V, VDD = 5 V
:j: VID = Differential Input Voltage, VI = Input voltage referenced to ground with IN- or AUX IN- connected to GND.
§ In this example, Vref is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog input not
exceed 0.1 dB below full scale.

4-111

1+----* te (SClK)

SHIFT
ClK

1
_ _ _-+I...,;

FSX, FSR, FSD

r-

8 V\.

12V

td (CH-Fl)

I
I

td (CH-FH)
I

. _ ..J...::!. ~~l-.._

tsu (OX) -+j

I

~ lI'-~~-+I----

II

DR---0-1-5--~i!J\D2\

2V

1

8V

1/ 2 V I

I
01

I.-

I

OX----{

I

i

DO:

DO

I

Don't Care

I

DAT~OR _ _~0~1~5_ _ _~~__~0~1__0_0~1_ _~_ _ __
1

Figure 4-2. Dual-Word (Telephone Interface) Mode Timing

1+----* te (SClK)

SHIFT
ClK

12
8V

td (CH-Fl)
FSX, FSRt

DR

I
I

I
I

'I

. _ ..J...::!. ~'!:!ciL._

:::::0:1:5::::~i!J\D2\

OX _ _ _-<

tsu (OX) -+j

I

2'1l

I

td (CH-FH) ~ ];o~~~I---1/2VI

I
01

DO:

I

:.-DO

I
td (CH-El) -.j ~

I

i
I

Don't Care

-+I

14- Id (CH-EH)

-----------------~\'~J-------~I
I~~-EOOX, EOOR*
8 V"----.I 2 V
Figure 4-3. Word Timing

t The time between falling edges of FSR is the AID conversion period and the time between falling edges of FSX is the
D/A conversion period,
:j: In the word format, EODX and EODR go low to signal the end of a 16-bit data word to the processor. The word-cycle

is 20 shift-clocks wide, giving a four-clock period setup time between data words.

4-112

~ I+- t f (SCLK)
SHIFT
CLK

2V

I

td (CH-FL)"1 ~
FSR,
8VX
FSX
DR

015

I

2V

r-

-.I
I

I
I I
: I"
I ~ ~ Id 'iCH-DR)
~~

tsu (DX)---.J

__

2V

I

~~

f

td (CH-FH)
2V

I
08

td (CH-FH)

I

1t

(~2~V~I

~_D_1_D_0.....
1

_ _ __

:-

DX~
EODR,
EODX

t r (SCLK)

th

(r~X)
'

08

-J

Don't Care

r-

01

td (CH-EH) ---.I

td (CH-EL)

8V\

DO

r

\,

I

J,-t_ __
2V

Figure 4-4. Byte-Mode Timing

tThe time between falling edges of FSR is the AID conversion period, and the time between faliling edges of FSX is the D/A conversion period.
:j: In the byte mode, when EODX or EODR is high, the first byte is transmitted or received, and when these signals are low, the second byte is
transmitted or received. Each byte-cycle is 12 shift-clocks long, allowing for a four-shift-clock setup time between byte transmissions.

!
w

MSTRClK

~-

SHIFTClK

I

-+I

td (MH-SH)

14- td (MH-Sl)

_______~/~----------\{II

1iO_._ _ _ _ __

Figure 4-5. Shift-Clock Timing

4.1

TMS3201 OITMS320C15 - TLC32046 Interface Circuit
ClKOUT ~

L

SO,G1

00-015

-------«

Valid ) ......- - - - - - - - - -

IN INSTRUCTION TIMING

ClKOUT

~

L

WE

SN74lS138 Y1

SN74lS299 ClK

00-015

-------«

Valid

) ......- - - - - - - - -

OUT INSTRUCTION TIMING

Figure 4-6. TMS32010ITMS320C15-TLC32046 Interface Timing

4-114

SN74lS74
Q

SN74lS299
J--

DEN
G1

'--

Y1 t--- 08-015
YO t-

AO/PAO
A1/PA1
A2/PA2

A
B
C
SN74lS138

TMS32010

I~h

....--

-'",

(

WE
ClK
OUT

~

OX

-

ClK< t--

-KJ:-

SR t-

SHIFT
ClK

SN74lS299
~

'--

r-

\,

C2<

FSX

QH

A-H

00-015
00-015

S1
G2
SO
G1

20

\

S1
G2
SO
G1

ClK.....

A-H

00-07'

-

"-r1

TlC32046

QH t-

SR

~

SN74lS7tj
C1<
Q

10 ~ DR

-P

J

INT

MSTR
ClK
EOOX

Figure 4-7. TMS32010ITMS320C15 - TLC32046 Interface Circuit

4-115

4-116

5 Typical Characteristics
DIA AND AID LOW-PASS FILTER
RESPONSE SIMULATION
0.4

I

I

I

I

I

=25°C
Input =± 3 V Sine Wave

TA
0.2
III

"C

I

-

-8::I

·2

0

til

..,/'r

\\I

:l!l

"C

c

\\I

-0.2

III
III
III
\\I

Q.

-

"

~

1\

" ~V\

-0.4

-0.6

o

1

2

3

4

5

6

7

8

9

10

Normalized Frequency

Figure 5-1
DIA AND AID LOW-PASS FILTER RESPONSE
0
See Figure 2-1
for Pass Band
Detail

-10

~

TA
_

=25°C
=± 3 V Sine Wave

Input

_

-20
III

-30

"C

I
III
"C
::I

==ctil

-40
-50

\\I

:l!l

-60
-70

r\

-80
-90

o

II
2

4

6

8

10

12

I

~

d

14

16

18

20

Normalized Frequency

Figure 5-2
Normalized Frequency x SCF f clock (kHz)
288
For Low-Pass SCF fclock > 288 kHz, please call the factory.

NOTE : Absolute Frequency (kHz)

4-117

DIA AND AID LOW·PASS GROUP DELAY
I

0.9 _

I

I

I

I

TA=25°C
Input = ± 3 V Sine Wave

0.8
0.7
III

E
I

.0.6

GI

0.5

>S

c

Q.

:::I

e

~

0.4
0.3

--

0.2
0.1

o
o

1

2

.,/'

/

J

!\
..........

3
4
5
6
7
Normalized Frequency

8

9

10

9

10

Figure 5-3
AID BAND·PASS RESPONSE
0.4

I

I

I

I

I

I

I

High·Pass SCF fclock = 16 kHz
TA = 25°C
Input = ±3 V Sine Wave

0.2
III
'til
I

GI

'til

:::I

:t::

0

../

C

C)

as
::E
'til
c
as

I'

f\

"

~

-0.2

III

III
III

as

a.

V

,,-'

-0.4

-0.6

o

1

2

3· 4
5
6
7
Normalized Frequency

8

Figure 5-4

Normalized Frequency x SCF fclock (kHz)
NOTE : Absolute Frequency (kHz)

288
For Low-Pass SCF fclock > 288 kHz, please call the factory.

4-118

AID BAND-PASS FILTER RESPONSE SIMULATION
0

\

-10

High-Pass SCF
fclock 16 kHz
TA 25°C
Input ± 3 V Sine Wave

=

-20
III

=
=

-

-30

"CI

I
G)

"CI
:::J

:=
c
as
::&

DI

-40
-50
-60
-70

(

-80
-100

o

2

4

6

8

10

-

\ I """
12

~I

14

16

18

20

Normalized Frequency

Figure 5-5
AID BAND-PASS FILTER GROUP DELAY

2

I
I
I
I
I
I
I
High-Pass SCF fclock 16 kHz
TA 25°C
Input ±3 V Sine wave

1.8

=

1.6
I/)

E
I

1.2
1.1

:::J

=

-

-

1.4

~
iii
Q
a.

...0
C!J

=

1\

0.8

\
I \

0.6
0.4

-'~

\

0.2

o
o

0.8 1.6 2.4 3.2 4.0 4.8 5.6 6.4 7.2 8.0
Normalized Frequency

Figure 5-6

NOTE : Absolute Frequency (kHz)

Normalized Frequency x SCF fclock (kHz)

288
For Low-Pass SCF fclock > 288 kHz, please call the factory.
4-119

AID CHANNEL HIGH-PASS FILTER
20

I

TA = 25°C
Input = ± 3 V Sine Wave

10
0
III

'C

/"

-10

I

III

'C

:::J

-20

"2

r

CI

10

:::i

-30

I

-40
-50
-60

o

100 200 300 400 500 600 700 800 900 1000
Normalized Frequency

Figure 5-7
DIA (sin x)/x CORRECTION FILTER RESPONSE

4

/

2

L

III

'C

I

0

V

v

~

/

~\

\

III

'C

.a
"2

CI

10

\
\

-2

:::i

\
\

-4 e- TA = 25°C

Input = ± 3 V Sine Wave

-6

o

l I

I

I

I

2

6

8

10

4

12

14

16

18

\
20

Normalized Frequency

.Figure 5-8
Normalized Frequency x SCF fclock (kHz)
NOTE: Absolute Frequency (kHz)

288
For Low-Pass SCF fclock > 288 kHz, please call the factory"

4-120

D/A (sin x)/x CORRECTION FILTER RESPONSE
500
TA = 25°C
Input = ± 3 V Sine Wave
400

Vr\

(II

:::l
I

~

300

/ \

ii)
Q

Q.

:s

...0
C)

200

-

100

o

o

./

/

\
"

2

4

6
8 10 12 14 16
Normalized Frequency

18

20

Figure 5-9

D/A (sin x)/x CORRECTION ERROR
2
TA = 25°C
Input = ± 3 V Sine Wave

1.6
1.2

III

ell
'tJ

.a
'2

/

0.4

-'
............

o

~ -0.4

r-.....

-0.8
-1.2
-1.6

o

V

V "

:E

-2

/V

V (sin x) Ix Correction

0.8

~

/

2

Error

..........

" ""'

~

19.2 kHz (sin x)
Distortion

IX\

"I\.\

3
4
5
6
7
Normalized Frequency

8

9

10

. Figure 5-10

Normalized Frequency x SCF fclock (kHz)
288
For Low-Pass SCF fclock > 288 kHz, please call the factory.

NOTE: Absolute Frequency (kHz)

4-121

AID BAND-PASS GROUP DELAY
760

1/1

T

680

~

640

I

Low-pass SCF tclock = 144 kHz
High-pass SCF fclock = 8 kHz
TA = 25°C
Input = ± 3 V Sine Wave

720 r--r-

I

>ca

g,
:::J
0
C!)

..

600

1/1
1/1

560

-b
c

520

!.
III

J

/
\

\\

al

~

480
440
400

o

0.4

"

0.8

/'

1.2

1.6

V

/

2.0

/

/

/

2.4

2.8

3.2 3.6

f - Frequency - Hz

Figure 5-11
D/A LOW-PASS GROUP DELAY
560

I

III

I

T
.eGI

440

1/1

I

I

Low-pass SCF fclock = 144 kHz
520 f- TA=250 C
Input = ± 3 V Sine Wave
480

/

>-

Q

V

g,

..6

400

1/1
1/1

ca

360

-b
c

320

/
)'

C!)

g,
III

V

al
Q

Ci:

280
240
200

/
o

0.4

0.8

/

1.2 1.6 2.0 2.4
f - Frequency - Hz

Figure 5-12

4-122

2.8

3.2 3.6

AID SIGNAL-TO-DISTORTION RATIO

vs
INPUT SIGNAL
100

III

1-kHz Input Signal
90 r- 1S-kHz Conversion Rate
TA = 25°C
80

I
0

70

'll

ia:
c

SO

:e0

50

0

'lii
is
I

40

i;j

30

~
c

Gain
Gain = 4

=1

"..-

V

/

"V

CI

(ij

20
10

o
- 50

o
- 40
- 30
- 20
-10
Input Signal Relative to Vref - dB

10

Figure 5-13
AID GAIN TRACKING
(GAIN RELATIVE TO GAIN AT O-dB INPUT SIGNAL)
0.5

1-kHz Input Signal
0.4 - 1S-kHz Conversion Rate
TA = 25°C
0.3
III

0.2

'll

I
CI

0.1

c

:il
f.)

~

·ac
C)

". ~

-

-0.1
-0.2
-0.3
-0.4
-0.5
-50

-40
-30
-20
-10
o
Input Signal Relative to Vref - dB

10

Figure 5-14

4-123

DIA CONVERTER SIGNAL-TO-DISTORTION RATIO

vs
INPUT SIGNAL
100

I

I

I

CD

1-kHz Input Signal Into 600 Q
90 f-- 16-kHz Conversion· Rate
TA = 25°C
80

:;

I
0

70

c

60

:e0

50

is
{!.

40

..!.
1\1
C
til

30

"

a:
0

"iii
I

en

V

/

V

/

",

.......

,./

20
10

o

-50

-30
-20
-10
-40
o
Input Signal Relative to Vref - dB

10

Figure 5-15
01 A GAIN TRACKING (GAIN RELATIVE TO GAIN
AT O-dB INPUT SIGNAL)
0.5
1-kHz Input Si~nallnto'600 Q
0.4 16-kHz Conversion Rate
TA = 25°C
0.3
CD

"
I

til

0.2
0.1

c

:i2
u

0

c

-0.1

~
~
~

-0.2

--

V

"'

-0.3
-0.4
-0.5
-50

-30
-20
-10
-40
o
Input Signal Relative to Vref - dB

Figure 5-16

4-124

10

AID SECOND HARMONIC DISTORTION

vs
INPUT SIGNAL
-100
-90
ID

'tI

1-kHz Input Signal
16-kHz.conversion Rate
TA = 25°C

~

-80

I

c
0

-70

Ui

-60

u

-50

..

-40

:e0

-~

is
'2
0
E
111

:z::

'tI

c

/'

'-

-30

0

u

c7l

-20
-10

o
- 50

o
- 40
- 30
- 20
-10
InJ)ut Signal Relative to Vref - dB

10

Figure 5-17
D/A SECOND HARMONIC DISTORTION

vs
INPUT SIGNAL
-100
-90
ID

'tI

-80

1-kHz Input Signal Into 600 Q
16-kHz Conversion Rate
TA = 25°C

I

c
0

-70

~

-60

u

-50

..

-40

:e

V

V- i"'--

, .-.......

Q

'2
0
E
111

:z::
'tI

c

-30

0

u

c7l

-20
-10

o

-50

-40
-30
-20
-10
o
Input Signal Relative to Vref - dB

10

Figure 5-18

4-125

AID THIRD HARMONIC DISTORTION

vs
INPUT SIGNAL
-100

al

"c
I

0

:e0

-

1-Hz Input Signal
-90 I- 16-kHz Conversion Rate
TA = 25°C
-80

-60

1/1

C
u
"2

-50

..

E

-40

::E:

-30

0

".

-70

..

V
./

~~

".,

III

"E

:c
I-

-20
-10

o

-50

-40
-30
-20
-10
o
Input Signal Relative to Vref - dB

10

Figure 5-19
DIA THIRD HARMONIC DISTORTION
vs
INPUT SIGNAL
-100

al

"c
I

0

:e0
"Iii
C
u
"2

..
"..
:c
0

E

I

I

I

_ 1-kHz Input Signal Into 600 n
-90 16-kHz Conversion Rate '
TA = 25°C
-80
-70
-60

~..,,;"

./

~
'\

-50
-40

III

::E:

-30

I-

-20
-10

o

- 50

- 40
- 30
- 20
-10
o
InputSignal Relative to Vref - dB

Figure 5-20

4-126

10

6 Application Information
TMS32020/C25

TLC32046

CLKOUT

MSTRCLK

FSX

FSX

OX

OX

FSR

FSR

DR

DR

CLKR

+5V

VCC+
REF

C

ANLGGNO

VCC-

-5V

VOO

+5V

SHIFTCLK

CLKX
QGTLGNO
A

C = 0.2 IlF, Ceramic

Figure 6-1. AIC Interface to the TMS32020/C25 Showing Decoupling Capacitors
and Schottky Diodet

t

Thomson Semiconductors

VCC

R
3 V Output
500n
0.011lF

TL431

25QO

n

FOR: VCC = 12 V, R = 7200.Q
VCC = 10 V, R = 5600.Q
VCC = 5 V, R = 1600n

Figure 6-2. External Reference Circuit for TLC32046

4-127

4-128

TLC32047C, TLC320471
Data Manual

Wide-Band Analog Interface Circuit

SLASD49A
April 1995

•
TEXAS
INSTRUMENTS

Printed on Recycled Paper

IMPORTANT NOTICE
Texas Instruments (TI) re13erves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with Tl's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
.
.
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.

Copyright © 1995, Texas Instruments Incorporated

Contents
Section

Title

Page

1

Introduction . ............................................................. 4-135
1.1· Features ............................................................. 4-136
1.2 Functional Block Diagrams ............................................. 4-137
1.3 Terminal Assignments ................................................. 4-140
1.4 Odering Information ................................................... 4-140
1.5 Terminal Functions .................................................... 4-141

2

Detailed Description ..... ............................................ ..... 4-145
2.1 Internal Timing Configuration ........................................... 4-146
2.2 Analog Input ......................................................... 4-148
2.3 AID Band-Pass Filter, Clocking, and Conversion Timing .................... 4-148
2.4 AID Converter ........................................................ 4-148
2.5 Analog Output ........................................................ 4-148
2.6 D/A Low-Pass Filter, Clocking, and Conversion Timing ..................... 4-148
2.7 D/A Converter ........................................................ 4-149
2.8 Serial Port ........................................................... 4-149
2.9 Synchronous Operation ................................................ 4-149
2.9.1 One 16-Bit Word ................................................ 4-149
2.9.2 Two 8-Bit Bytes ................................................. 4-149
2.9.3 Synchronous Operating Frequencies .............................. 4-150
2.10 Asynchronous Operation ............................................... 4-150
2.10.1 One 16-Bit Word ................................................ 4-150
2.10.2Two 8-Bit Bytes ................................................. 4-150
2.10.3 Asynchronous Operating Frequencies ............................. 4-151
2.11 Operation of TLC32047 With Internal Voltage Reference ................... 4-151
2.12 Operation of TLC32047 With External Voltage Reference .................. 4-151
2.13 Reset ............................................................... 4-151
2.14 Loopback ............... , ............................................ 4-151
2.15 Communications Word Sequence ....................................... 4-152
2.15.1 DR Word Bit Pattern, ............................................ 4-152
2.15.2 Primary OX Word Bit Pattern ..................................... 4-153
2.15.3 Secondary OX Word Bit Pattern ................................... 4-154
2.16 Reset Function ....................................................... 4-154
2.17 Power-Up Sequence .................................................. 4-155
2.18 AIC Register Constraints ............................................... 4-155
2.19 AIC Responses to Improper Conditions .................................. 4-155
2.20 Operation With Conversion Times Too Close Together ..................... 4-156
2.21 More Than One Receive Frame Sync Occurring Between
Two Transmit Frame Syncs - Asynchronous Operation .................... 4-156
4-131

2.22 More than One Transmit Frame Sync Occurring Between Two Receive
Frame Syncs - Asynchronous Operation ................................. 4-157
2,23 More than One Set of Primary and Secondary OX Serial Communications
Occurring Between Two Receive Frame Syncs - Asynchronous Operation ... 4-157
2.24 System Frequency ResponseCol'rection ................................. 4-158
2.25 (sin x)/x Correction .................................................... 4-158
2.26 (sin x)/x Roll-Off for a Zero-Order Hold Function .......................... 4-158
2.27 Correction Filter ...................................................... 4-159
2.28 Correction Results .................................................... 4-159
2.29 TMS320 Software Requirements ........................................ 4-160

Specifications ............................................................... 4-161
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range ... 4-161
3.2 Recommended Operating Conditions .................................... 4-161
3.3 Electrical Characteristics .............................................. 4-162
3.3.1 total device .................................................... 4-162
3.3.2 power supply rejection and crosstalk attenuation .................... 4-162
3.3.3 serial port ...................................................... 4-162
3.3.4 receive amplifier input ........................................... 4-162
3.3.5 transmit filter output ............................................. 4-163
3.3.6 receive and transmit system distortion specifications .............. :.4-163
3.3.7 receive channel signal-to-distortion ratio ........................... 4-163
3.3.8 transmit channel signal-to-distortion ratio ........................... 4-164
3.3.9 receive and transmit gain and dynamic range ....................... 4-164
3.3.10 receive channel band-pass filter transfer function ................... 4-164
3.3.11 receive and transmit channel low-pass filter transfer function ......... 4-165
3.4 Operating Characteristics (Noise) ....................................... 4-165
3.4.1 Timing Requirements ............................................ 4-166
3.4.1 Receive and Transmit Noise (Measurement Includes Low-Pass and
Band-Pass Switched-Capacitor Filters) ..... , ...................... 4-166
3.5 Timing Requirements .................................................. 4-167
3.5.1 Serial Port Recommended Input Signals ........................... 4-167
3.5.2 Serial Port - AIC Output Signals For All Other Outputs ............... 4-167
4

Parameter Measurement Information - Timing Diagrams .................... 4-169
4.1 TMS32047 - Processor Interface ....................................... 4-169

5

Typical Characteristics .................................................... 4-175

6

Applications Information . ................................................. 4-185

4-132

List of Illustrations
Figure

1-1
1-2
1-3
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
4-1
4-2

4-3
4-4
4-5
4-6
4-7
5-1
5-2
5-3
5-4
5-5
5-6
5-7

5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
6-1

6-2

Title

Page

Dual-Word (Telephone Interface) Mode .................................... 4-138
Word Mode ............................................................ 4-139
Byte Mode ............................................................. 4-139
Asynchronous Internal Timing Configuration ................................. 4-147
Primary and Secondary Communications Word Sequence ................... 4-152
Reset on Power-Up Circuit ............................................... 4-155
Conversion Times Too Close Together ..................................... 4-156
More Than One Receive Frame Sync Between Two Transmit Frame Syncs .... 4-157
More Than One Transmit Frame Sync Between Two Receive Frame Syncs .... 4-157
More Than One Set of Primary and Secondary DX Serial Communications
Between Two Receive Frame Syncs ...................................... 4-158
First-Order Correction Filter .............................................. 4-159
IN+ .and IN- Gain Control Circuitry ........................................ 4-159
Dual-Word (Telephone Interface) Mode Timing .............................. 4-170
Word Timing ........................................................... 4-170
Byte-Mode Timing ...................................................... 4-171
Shift-Clock Timing ...................................................... 4-172
TMS32010fTMS320C15-TLC32047 Interface Circuit ........................ 4-172
TMS32010fTMS320C15-TLC32047 Interface Timing ............... ~ ....... 4-173
DIA and AID Low-Pass Filter Response Simulation .......................... 4-175
D/A and AID Low-Pass Filter Response .................................... 4-175
D/A and AID Low-Pass Group Delay ...................................... 4-176
AID Band-Pass Response ............................................... 4-176
AID Band-Pass Filter Response Simulation ................................ 4-177
AID Band-Pass Filter Group Delay ........................................ 4-177
AID Channel High-Pass Filter ............................................. 4-178
D/A (sin x)/x Correction Filter Response ................................... 4-178
D/A (sin x)/x Correction Filter Response ................................... 4-179
D/A (sin x)/x Correction Error ............................................. 4-179
AID Band-Pass Group Delay ............................................. 4-180
D/A Low-Pass Group Delay .............................................. 4-180
AID Signal-to-Distortion Ratio vs Input Signal ............................... 4-181
AID Gain Tracking ........................ , ............................. 4-181
D/A Converter Signal-to-Distortion Ratio vs Input Signal ..................... 4-182
D/A Gain Tracking ...................................................... 4-182
AID Second Harmonic Distortion vs Input Signal ............................ 4-183
D/A Second Harmonic Distortion vs Input Signal ............................ 4-183
AID Third HarmonicDistortion vs Input Signal .............................. 4-184
D/A Third Harmonic Distortion vs Input Signal .............................. 4-184
AIC Interface to the TMS32020/C25 Showing Decoupling Capacitors
and Schottky Diode ..................................................... 4-185
External Reference Circuit for TLC32047 .................................. 4-185
4-133

List of Tables
Table

2-1
2-2
2-3
2-4
2-5
2-6
4-1

4-134

Title

Page

Mode-Selection Function Table ........................................... 4-145
Primary OX Serial Communication Protocol ................................ 4-153
Secondary OX Serial Communication Protocol .............................. 4-154
AIC Responses to Improper Conditions .................................... 4-156
(sin x)/x Roll-Off Error ................................................... 4-159
(sin x)/x Correction Table for fs = 8000 Hz and fs = 9600 Hz .................. 4-160
Gain Control Table ...................................................... 4-169

1 Introduction
The TLC32047 wide-band analog interface circuit (AIC) is a complete analog-to-digital and digital-to-analog
interface system for advanced digital signal processors (DSPs) similar to the TMS32020, TMS320C25, and
TMS320C30. The TLC32047 offers a powerful combination of options under DSP control: three operating
modes [dual-word (telephone interface), word, and byte] combined with two word formats (8 bits and 16 bits)
and synchronous or asynchronous operation. It provides a high level of flexibility in that conversion and
sampling rates, filter bandwidths, input circuitry, receive and transmit gains, and multiplexed analog inputs
are under processor control.
This AIC features a
•
•
•
•

band-pass switched-capacitor antialiasing input filter
14-bit-resolution AID converter
14-bit-resolution D/A converter
low-pass switched-capacitor output-reconstruction filter

The antialiasing input filter comprises eighth-order and fourth-order CC-type (Chebyshev/elliptic
transitional) low-pass and high-pass filters, respectively. The input filter is implemented in switchedcapacitor technology and is preceded by a continuous time filter to eliminate any possibility of aliasing
caused by sampled data filtering. When low-pass filtering is desired, the high-pass filter can be switched
out of the signal path. A selectable auxiliary differential analog input is provided for applications where more
than one analog input is required.
The output-reconstruction filter is an eighth-order CC-type (Chebyshev/elliptic transitional low-pass filter)
followed by a second-order (sin x)/x correction filter and is implemented in switched-capacitor technology.
This filter is followed by a continuous-time filter to eliminate images of the sample data signal. The on-board
(sin x)/x correction filter can be switched out of the signal path using digital signal processor control.
The AID and D/A architectures ensure no missing codes and monotonic operation. An internal voltage
reference is provided to ease the design task and to provide complete control over the performance of the
IC. The internal voltage reference is brought out to REF. Separate analog and digital voltage supplies and
ground are provided to minimize noise and ensure a wide dynamic range. The analog circuit path contains
only differential circuitry to keep noise to a minimum. The exception is the DAC sample-and-hold, which
utilizes pseudo-differential circuitry.
The TLC32047C is characterized for operation from O°C to 70°C, and the TLC320471 is characterized for
operation from -40°C to 85°C.

4-135

1.1

Features

•
•
•

14-Bit Dynamic Range ADC and DAC
1S-Bit Dynamic Range Input With Programmable Gain
Synchronous or Asynchronous ADC and DAC Sampling Rates Up to 25,000 Samples Per
Second

•

Programmable Incremental ADC and DAC Conversion Timing Adjustments

•

Typical Applications
- Speech Encryption for Digital Transmission
- Speech Recognition and Storage Systems
- Speech Synthesis
- Modems at 8-kHz, 9.S-kHz, and 1S-kHz' Sampling Rates
- Industrial Process Control
- Biomedicallnstrumentation
- Acoustical Signal Processing
- Spectral Analysis
- Instrumentation Recorders

•
•

- Data Acquisition
Switched-Capacitor Antialiasing Input Filter and Output-Reconstruction Filter
Three Fundamental Modes of Operation: Dual-Word (Telephone Interface), Word, and Byte

•
•
•

SOO-mil Wide N Package
Digital Output in Twos Complement Format
CMOS Technology
FUNCTION TABLE
SYNCHRONOUS
(CONTROL
REGISTER
BIT D5 = 1)

ASYNCHRONOUS
(CONTROL
REGISTER
BIT D5 =0)

16-bit format

Dual-word
(telephone
interface) mode

Dual-word
(telephone
interface) mode

DATA-DR/CONTROL = 0 to 5 V
FSDIWORD-BYTE = 0 to 5 V

TMS32020,
TMS320C25,
TMS320C30

16-bit format

Word mode

Word mode

DATA-DR/CONTROL = VCC-(-5 Vnom)
FSDIWORD-BYTE = VCC+ (5 V nom)

TMS32020,
TMS320C25,
TMS320C30,
indirect
interface to
TMS320C10
(see Figure 7)

a-bit format
(2 bytes
required)

Byte mode

Byte mode

DATA-DR/CONTROL = VCC-(-5 Vnom)
FSDIWORD-BYTE = VCC- (-5 V nom)

TMS320C17

DATA
FORMAT

4-136

FORCING CONDITION

DIRECT
INTERFACE

1.2

Functional Block Diagrams
WORD OR BYTE MODE

IN + 2:;:6+---1""""IN _ 25:71""_""""""
AUX IN + 2_4_ _.....

AUX IN _ 2_3_--t...,

M
U

X

Receive Section

Low-Pass
Filter

Serial
Port

AID

5 DR
4
3

High-Pass
Filter

6

r,:----:;,

I
------------------~I

FSR

MSTR CLK

10 SHIFTCLK

I
~~~ II
Reference
~ ____ ::.J
Internal

1 WORD-

BYTE
13 CONTROL
12
OX

14 _

FSX
OUT +

Low-Pass
Filter

OUT-

20

11 EO OX

7
DGTL
VDD
GND (Digital)

VCC+

DUAL·WORD (TELEPHONE INTERFACE) MODE
IN + 2:,:6+---1""""-

IN _ 2~5t-----t.."
AUX IN + 2_4_ _.....

Low-Pass
Filter

Serial
Port

AID

AUX IN _ 2_3_ _"

5
4

3

Receive Section

High-Pass
Filter

r,:----:;,
I
I

I
I
~ ____ ::.J

------------------~
Transmit Section

Internal
Voltage
Reference

I

6
10

DR
FSR

011 OUT
MSTRCLK
SHIFTCLK

1_
FSD

13
12

DATA-DR
OX

14_
FSX

OUT +

Low-Pass
Filter

OUT-

20
VCC+

VCC-

7
DGTL
VDD
GND (Digital)

D/A

11

010 OUT

8
REF

4-137

FRAME SYNCHRONIZATION FUNCTIONS
TLC32047 Function,

Frame Sync Output

Receiving serial data on DX from processor to internal DAC

FSXlow

Transmitting serial data on DR from internal ADC to processor, primary communications

FSR low

Transmitting serial data on DR from DATA-DR to processor, secondary communications in '
dual-word (telephone interface) mode only

FSD low

5V
201
26

VCC+

-5V
191
VCCDR

IN+

Analog In

25

IN-

TLC32047

FSR

Serial Data Out
5
4
3

D110UT
22

Analog Out

...

21

OUT+
OX

12

Serial Data In

TMS32020,
TMS320C25,
TMS320C30,
, or Equivalent
16·Bit DSP

OUTFSX

14

TTL or CMOS
Logic Levels

11
D100UT

...

1

FSD

Secondary Commu nication (see Table above)
13
Serial Data Input

DATA·DR

...

16·Bit Format TTL
or CMOS Lo9 ic Levels

Figure 1-1. Dual-Word (Telephone Interface) Mode
When the DATA-DR/CONTROL input is tied to a logic signal source varying between 0 and 5 V, the
TLC32047 is in the dual-word (telephone interface) mode. This logic signal is routed to the DR line for input
to the DSP only when terminal 1, data frame synchronization (FSD), outputs a low level. The FSD pulse
duration is 16 shift clock pulses. Also, in this mode, the control register data bits 010 and 011 appear on
D100UT and D110UT, respectively, as outputs.

4-138

5V

-5V

201

191
VCC-

VCC+
26

Analog In

25

DR

IN+
IN-

TLC32047

FSR
EODR

22
-~

An alog Out

....

21

OUT+

DX

EODX

..

Serial Data Out

4
3

TMS32020,
TMS320C25,
TMS320C30,
or Equivalent
16-Bit DSP

...
Serial Data In

12
~

OUTFSX

VCC+
(5 V nom)

5

14

TTL or CMOS
Logic Levels

11

.. ~

VCC1

~

WORD-BYTE

CONTROL

(- 5 V nom)

13
~

Figure 1-2. Word Mode
5V

-5V

201

191

Vcc+
26

Analog In

25

VCCDR

IN+
IN-

TLC32047

FSR
EODR

22

Analog Out

.....

21

OUT+

DX

EODX

1

Serial Data Out

4

WORD-BYTE

CONTROL

..
..
~

3

~

12

TMS320C17
or Equivalent
8-Bit Serial
Interface
(2 Bytes Required)

Serial Data In

TTL or CMOS

OUTFSX

VCC(-5 V nom)

5

14

..

Logic Levels

11

13

VCC(-5 V nom)

Figure 1-3. Byte Mode
The word or byte mode is selected by first connecting the DATA-DR/CONTROL input to VeeFSDIWORD-BYTE becomes an input and can then be used to select either word or byte transmission
tormats. The end-ot-data transmit (EODX) and the end-ot-data receive (EODR) signals on terminals 11 and
3, respectively, are used to signal the end of word or byte communication (see the Terminal Functions
section)_

4-139

Terminal Assignments

1.3

FNPACKAGE
(TOP VIEW)

NPACKAGEt
(TOP VIEW)
FSDIWORD-BYTE:j:

NU
NU

RESET
D110UT/EODR:j:

IN+
IN-

FSR
DR

AUX IN+
AUX IN-

MSTR CLK

::::l

OUT+
OUT-

VDD
REF
DGTLGND

VCC+
VCCANLGGND
ANLG GND
NU

SHIFTCLK
D100UT/EODX:j:
OX
DATA-DR/CONTROL:j:
FSX

NU

+

z~

5

4 321 28272625

6

24

7

23

AUXIN+
AUXIN-

8

22
21

OUT+
OUT-

20
19
11
121314 1516 1718

VCC+
VCC-

9
SHIFTCLK
D100UT/EODX:j:

10

X-t::!JIX

IN-

::::l00

::::l Z Z Z
°O(/)Z

a:LI..

C!)C!)

I-

gg

~
o

««

z
o

zz

~

 1.
(RA register ± RA' register) must be > 1.
TB register must be ~ 15.
RB register must be ~ 15.

2.19 AIC Responses to Improper Conditions
The Ale has provisions for responding to improper conditions. These improper conditions and the response
of the Ale to these conditions are presented in Table 2-4. The general procedure for correcting any improper
operation is to apply a reset and reprogram the registers to the proper value.

4-155

Table 2-4. AIC Responses to Improper Conditions
IMPROPER CONDITION

AIC RESPONSE

TA register + TA' register = 0 or 1
TA register - TN register = 0 or 1

Reprogram TX(A) counter with TA register value

TA register + TA' register < 0

MODULO 64 arithmetic is used to ensure that a positive value is loaded
into TX(A) counter, i.e., TA register + TA' register + 40 hex is loaded into
TX(A) counter.

RA register + RA' register = 0 or 1
RA register - RA' register = 0 or 1

Reprogram RX(A) counter with RA register value

RA register + RA' register = 0 or 1

MODULO 64 arithmetic is used to ensure that a positive value is loaded
into RX(A) counter, i.e., RA register + RA' register + 40 hex is loaded
into RX(A) counter.

TA register = 0 or 1
RA register = 0 or 1

AIC is shut down. Reprogram TA 0 .. RA registers after a reset.

TA register < 4 in word mode
TA register < 5 in byte mode
RA register < 4 in word mode
RA register < 5 in byte mode

The AIC serial port no longer operates. Reprogram TA or RA registers
after a reset.

. TS register < 15

ADC no longer operates

RS register < 15

DAC no longer operates

AIC and DSP cannot communicate

Hold last DAC output

2.20 Operation With Conversion Times Too Close Together
If the difference between two successive D/A conversion frame syncs is less than 1/25 kHz, the AIC
operates improperly. In this situation, the second D/A conversion frame sync occurs too quickly, and there
is not enough time for the ongoing conversion to be completed. This situation can occur if the A and B
registers are improperly programmed or if the A + A' register result is too small. When incrementally
adjusting the conversion period via the. A + A' register options, the designer should not violate this
requirement. See Figure2-4.
Frame Sync
(FSX or FSR)

l

t1

S; 1/25

1

----~

I+-t2 - t1

..-----I,'J""',___-It2
Ongoing Conversion

I

~--~

--'1

kHz

Figure 2-4. Conversion Times Too Close Together

2.21 More Than One Receive Frame Sync Occurring Between Two Transmit
Frame Syncs - Asynchronous Operation
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the AIC
during an FSX frame sync. The ongoing conversion period is then adjusted; however, either receive
conversion period A or conversion period B may be adjusted. For both transmit and receive conversion
periods, the incremental conversion period adjustment is performed near the end of the conversion period.
If there is sufficient time between t1 and t2, the receive conversion period adjustment is performed during
receive conversion periodA. Otherwise, the adjustment is performed during receive conversion period B.
The adjustment command only adjusts one transmit conversion period and one receive conversion period.
To adjust another pair of transmit and receive conversion periods, another command must be issued during
a subsequent FSX frame (see Figure 2-5).
4-156

u
1+1

4 - - - - Transmit Conversion Period

I

~I

j"I
Receive Conversion
Period A

U

----~~I

I

Receive Conversion
Period B

Figure 2-5. More Than One Receive Frame Sync Between Two Transmit Frame Syncs

2.22 More Than One Transmit Frame Sync Occurring Between Two .Receive
Frame Syncs - Asynchronous Operation
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol must be followed. For both transmit and receive conversion periods, the incremental conversion
period adjustment is performed near the end of the conversion period. The command to use the incremental
conversion period adjust options is sent to the AIC during an FSX frame sync. The ongoing transmit
conversion period is then adjusted. However, three possibilities exist for the receive conversion period
adjustment as shown in Figure 2-6. When the adjustment command is issued during transmit conversion
period A, receive conversion period A is adjusted if there is sufficient time between t1 and t2. If there is not
sufficient time between t1 and t2, receive conversion period B is adjusted. The third option is that the receive
portion of an adjustment command can be ignored if the adjustment command is sent during a receive
conversion period, which is adjusted due to a prior adjustment command. For example, if adjustment
commands are issued during transmit conversion periods A, B, and C, the first two commands may cause
receive conversion periods A and B to be adjusted, while the third receive adjustment command is ignored.
The third adjustment command is ignored since it was issued during receive conversion period B, which
already is adjusted via the transmit conversion period B adjustment command.

14- Transmit ----.- Transmit......- Transmit
Conversion I
Conversion I Conversion
Period A
Period B
Period C
t2

I

FSRU

J.---

Receive Conversion Period A

U

~~

-+1

LJ

Receive Conversion Period B

---+l

Figure 2-6. More Than One Transmit Frame Sync Between Two Receive Frame Syncs

2.23 More than One Set of Primary and Secondary OX Serial Communications
Occurring Between Two Receive Frame Syncs (See OX Serial Data Word
Format section) - Asynchronous Operation
The TA, TA', TB, and control register information that is transmitted in the secondary communication is
accepted and applied during the ongoing transmit conversion period. If there is sufficient time between t1
and t2, the TA, RA', and RB register information, sent during transmit conversion period A, is applied to
receive conversion period A. Otherwise, this information is applied during receive conversion period B. If
RA, RA', and RB register information has been received and is being applied during an ongoing conversion
period, any subsequent RA, RA', or RB information received during this receive conversion period is
disregarded. See Figure 2-7.

4-157

Primary

Fsxl

n

Secondary t1

Primary

r-I-'';'';1

,
Transmit
\4--Conversion
Preload A

Receive
. . - Conversion
Period A

,
.,..

n

Secondary

1""'------;';1

Transmit
Conversion
Preload B

I
I

--t.~I"~-----

Primary

Receive
Conversion
Period B

,
~

n

Secondary

Ir-------"""1L

Transmit
Conversion
Preload C

,
~

-----..1
I

-----------...1

Figure 2-7. More Than One Set of Primary and Secondary OX Serial Communications
Between Two Receive Frame Syncs

2.24 System Frequency Response Correction
The (sin x)/x correction for the DAC zero-order sample-and-hold output can be provided by an on-board
second-order (sin x)/x correction filter (see Functional Block Diagram). This (sin x)/x correction filter can be
inserted into or omitted from the signal path by digital-signal-processor control (data bit D9 in the DX
secondary communications). When inserted, the (sin x)/x correction filter precedes the switched-capacitor
low-pass filter. When the TB register (see Figure 2-1) equals 15, the correction results of Figures 5-8, 5-9,
and 5-10 can be obtained.
The (sin x)/x correction can also be accomplished by disabling the on-board second-order correction filter
and performing the (sin x)/x correction in digital signal processor software. The system frequency response
can be corrected via DSP software to ± 0.1 dB accuracy to a band edge of 3000 Hz for all sampling rates.
This correction is accomplished with a first-order digital correction filter, that requires seven TMS320
instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of 1.1 %
and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the (sin x)/x Correction Section for more
details).

2.25 (sin x)/x Correction
If the designer does not wish to use the on-board second-order (sin x)/x correction filter, correction can be
accomplished in digital signal processor (DSP) software. (sin x)/x correction can be accomplished easily
and efficiently in digital signal processor software. Excellent correction accuracy can be achieved to a band
edge of 3000 Hz by using a first-order digital correction filter. The results shown below are typical of the
numerical correction accuracy that can be achieved for sample rates of interest. The filter requires seven
instruction cycles per sample on the TMS320 DSP. With a 200-ns instruction cycle, nine instructions per
sample represents an overhead factor of 1.4% and 1.7% for sampling rates of 8000 Hz and 9600 Hz,
respectively. This correction adds a slight amount of group delay at the upper edge of the 300-Hz to 3000-Hz
band.

2.26 (sin x)/x Roll-Off for a Zero-Order Hold Function
The (sin x)/x roll-off error for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz
for the various sampling rates is shown in Table 2-5 (see Figure 5-10) ..

4-158

Table 2-5. (sin x)/x Roll-Off Error
Error
ts (Hz)

=20 log sin tItstIts
t =3000 Hz
1t

1t

(dB)

7200
8000
9600
14400

-2.64
-2.11
-1.44
-0.63
-0.50
-0.35
-0.21

16000

19200
25000

The actual Ale (sin x)/x roll-off is slightly less than the figures above because the Ale has less than 100%
duty cycle hold interval.

2.27 Correction Filter
To externally compensate for the (sin x)/x roll-off of the Ale, a first-order correction filter can be implemented
as shown in Figure 2-8.
U (i

+ 1)

Y(i + 1)

p1

Figure 2-8. First-Order Correction Filter
The difference equation for this correction filter is:
Y(i + 1)

= p2· (1

- p1)· uti + 1) + p1 . Y(i)

(4)

where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:

I H (f) I 2 =

(p2)2. (1-p1)2
1-2. p1 . cos (21t f/fs) + (p1 )2

(5)

2.28 Correction Results
Table 2-6 shows the optimum p values and the corresponding correction results for 8000-Hz and 9600-Hz
.
sampling rates (see Figures 5-8,5-9, and 5-10).

4-159

Table 2-6. (sin x)/x Correction Table for Is

=8000 Hz and fs =9600 Hz

ROLL-OFF ERROR (dB)
fs 8000 Hz
p1 =-0.14813
p2 = 0.9888

=

f (Hz)

ROLL-OFF ERROR (dB)
fs 9600 Hz
p1 = -0.1307
p2 = 0.9951

=

300

-0.099

-0.043
-0.043

600

-0.089

900

-0.054

0

1200

-0.002

0

1500

0.041·

0

1800

0.079

0.043

2100

0.100

0.043

2400

0;091

0.043

2700

-0.043

3000

-0.102

0
-0.043

2.29 TMS320 Software Requirements
The digital correction filter equation can be written in state variable form as follows:
Y(i+1) = Y(i) xk1

+ U(i+1) xk2

where
k1 = p1
k2 = (1 - p1 )p2
y(i) is the filter state
u(i+ 1)
The coefficients k1 and k2 must be represented as 16-bit integers. The SACH instruction (with the proper
shift) yields the correct result. With the assumption that the TMS320 processor page pointer and memory
configuration are properly initialized, the equation can be executed in seven instructions or seven cycles
with the following program:

ZAC
LT K2
MPY U
LTA Kl
MPY Y
APAC
SACH (dma) ,

4-160

(shift)

3
3.1

Specifications
Absolute Maximum Ratings Over Operating. Free-Air Temperature Range
(Unless Otherwise Noted)t
Supply voltage range, VCC+ (see Note 1) .......................... -0.3 V to 15 V
Supply voltage range, VCC- (see Note 1) .......................... -0.3 V to 15 V
Supply voltage range, VDD ....................................... -0.3 V to 15 V
Output voltage range, Va ........................................ -0.3 V to 15 V
Input voltage range, VI ........................................... -0.3 V to 15 V
Digital ground voltage range ...................................... -0.3 V to 15 V
Operating free-air temperature range: TLC32047C ............ ;...... O°C to 70°C
TLC320471 .................. -40°C to 85°C
Storage temperature range .................... :................. -40°C to 125°C
Case temperature for 10 seconds: FN package ............................ 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ... 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for
extended periods may affect device reliability.
NOTE 1: Voltage values for maximum ratings are with respect to VCC-.

4-161

3.2

Recommended Operating Conditions
MIN

NOM

UNIT

Supply voltage, VCC+ (see Note 2)

4.75

5

5.25

V

Supply voltage, VCC- (see Note 2).

-4.75

-5

-5.25

V

4.75

5

5.25

Digital supply voltage, VDD (see Note 2)
Digital ground voltage with respect to ANLG GND, DGTL GND

0

Referenc~ input VOltage, Vref(ext) (see Note 2)

V
V

2

4

V

High-level input voltage, VIH

2

VDD

V

Low-level input voltage, VIL (see Note 3)

0

0.8

Load resistance at OUT + and/or OUT-, RL ".

100

Load capacitance at OUT+ and/or OUT-, CL
5

Analog input amplifier common mode input voltage (see Note 5)

NOTES:

3.3

3.3.1

10.368
±1.5

AID or D/A conversion rate

25

Operating free-air temperature range, TA

1TLC32047C
.1
TLC320471

V
Q

300

MSTR CLK frequency (see Note 4)

0

70

-40

85

pF
MHz
V
kHz
°C

2. Voltages at analog inputs and outputs, REF, VCC+, and VCC- are with respect to ANLG GND. Voltages at
digital inputs and outputs and VDD are with respect to DGTL GND.
3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used
in"this data manual for logic voltage levels only.
4. The band-pass switched-capacitor filter (SCF) specifications apply only when the low-pass section SCF
clock is 432 kHz and the high-pass section SCF clock is 24 kHz. If the low-pass SCF clock is shifted from
432 kHz, the low-pass roll-off frequency shifts by the ratio of the low-pass SCF clock to 432 kHz. If the
high-pass SCF clock is shifted from 24 kHz, the high-pass roll-off frequency shifts by the ratio of the
high-pass SCF clock to 24 kHz. Similarly, the low-pass switched-capacitor filter (SCF) specifications apply
only when the SCF clock is 432 kHz. If the SCF clock is shifted from 432 kHz, the low-pass roll-off frequency
shifts by the ratio of the SCF clock to 432 kHz.
5. This range applies when (IN+ - IN-) or (AUX IN+ - AUX IN-) equals ± 6 V.

Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, VCC+ 5 V, VCC- -5 V, VDD 5 V (Unless
Otherwise Noted)

=

=

Total Device, MSTR ClK Frequency

=

=5.184 MHz, Outputs Not loaded

TEST CONDITIONS

PARAMETER

t

MAX

MIN

I1A

TYPt

MAX

VOH

High-level output voltage

VDD = 4.75 V,

IOH = -300

2.4

VOL

Low-level output voltage

VDD = 4.75 V,

IOL =2 mA

Supply current from
VCC+

TLC32047C

35

ICC+

TLC32047t

40

Supply current from
VCC-

TLC32047C

-35

ICC-

TLC320471

-40

UNIT
V

0.4

7

V
mA
rnA
mA

100

Supply current from VDD

Vref

Internal reference output voltage

aVref

Temperature coefficient of
internal reference voltage

250

ppm/oC

ro

Output resistance at REF

100

kQ

All typical values are at TA = 25°C.

4-162

3.3

3

V

3.3.2

Power Supply Rejection and Crosstalk Attenuation
PARAMETER

VCC+ or VCC- supply voltage
rejection ratio, receive channel
VCC+ or VCC- supply voltage
rejection ratio, transmit channel
(single-ended)

f = 0 to 30 kHz
f = 30 kHz to 50 kHz
f = 0 to 30 kHz
f = 30 kHz to 50 kHz

TEST CONDITIONS

MIN

Idle channel, supply
signal at 200 mV p-p
measured at DR (ADC
output)

30

Idle channel, supply
signal at 200 mV p-p
measured at OUT+

30

MAX

UNIT

dB
45

dB
45

Crosstalk attenuation, transmit-to-receive
(single-ended)

t

TYPt

80

dB

All typical values are at TA = 25°C.

3.3.3

Serial Port
PARAMETER

TEST CONDITIONS

MIN

TYPt

MAX

UNIT

High-level output voltage

IOH =-300 ~

VOL

Low-level output voltage

IOL=2 mA

II

Input current

II

Input current, DATA-DR/CONTROL

Ci

Input capacitance

15

pF

Co

Output capacitance

15

pF

VOH

2.4

V
0.4

V

±10

~

±100

IlA

t All typical values are at TA = 25°C.
3.3.4

Receive Amplifier Input
PARAMETER

TEST CONDITIONS

MIN

A/D converter offset error (filters in)
CMRR

Common-mode rejection ratio at IN+, IN-, or
AUX IN+, AUX IN-

q

Input resistance at IN+, IN- or AUX IN+,
AUX IN-, REF'

See Note 6

TYPt

MAX

10

70

UNIT
mV

55

dB

100

kn

t All typical values are at TA = 25°C.
NOTE 6: The test condition is a O-dBm, 1-kHz input signal with a 24-kHz conversion rate.

3.3.5

Transmit Filter Output
PARAMETER

VOO

Maximum peak output voltage swing across
RL at OUT+ or OUT- (single-ended)
VOM

TEST CONDITIONS

MIN

Output offset voltage at OUT+ or OUT(single-ended relative to ANLG GND)

Maximum peak output voltage swing between
OUT + and OUT- (differential output)

TYPt

MAX

15

80

UNIT
mV

RL~300 n,
Offset voltage = 0

±3

V

RL~ 600 n,

±6

V

t All typical values are at TA = 25°C.

4-163

3.3.6

Receive and Transmit Channel System Distortion, SCF Clock
Frequency 432kHz (see Note 7)

=

PARAMETER
Attenuation of second harmonic of
AID input signal

TEST CONDITIONS

differential
single-ended

Attenuation of third and higher
harmonics 'of AID input signal

MIN

single-ended
62

VI =-0.1 dB to-24 dB

single-ended

Attenuation of third and higher
harmonics of OrA input signal

dB

65
70

62

VI = -0 dB to -24 dB

dB

70
65

differential

57

UNIT
dB

70
65

57

single-ended
differential

MAX

70

' differential

Attenuation of second harmonic of
OrA input signal

TYPt

dB

65

t All typical values are at TA = 25°C.
3.3.7

Receive Channel Signal-to-Distortion Ratio (see Note 7)
PARAMETER

AID channel signal-todistortion ratio

=1=

TEST CONDITIONS

Av = 1 VIV*
MIN

MAX

Av = 2 VIV*
MIN

MAX

A v =4VIV*
MIN

VI = -6 dB to -0.1 dB

56

~

VI =-12dBto-6dB

56

56

§

VI = -18 dB to -12 dB

53

56

56

VI = -24 dB to -18 dB

47

53

56

MAX

UNIT

§

VI = -30 dB to -24 dB

41

47

53

VI = -36 dB to -30 dB

35

41

47

VI = -42 dB to -36 dB

29

35

41

VI = -48 dB to -42 dB

23

29

35

VI = -54 dB to -48 dB

17

23

29

dB

Av is the programmable gain of the input amplifier.

§ Measurements under these conditions are unreliable due to overrange and signal clipping.
NOTE 7:

4-164

The test condition is a 1-kHz input signal with a 24-kHz conversion rate. The load impedance for the DAC is
600 Q. Input and output voltages are referred to Vref.

3.3.8

Transmit Channel Signal-to-Distortion Ratio (see Note 7)
PARAMETER

MIN

TEST CONDITIONS

=-6 dB to -0.1 dB
=-12 dB to -6 dB
VI =-18 dB to -12 dB
VI =-24 dB to -18 dB
VI =-30 dB to -24 dB
VI =-36 dB to -30 dB
VI =-42 dB to -36 dB
VI =-48 dB to -42 dB
VI =-54 dB to -48 dB

UNIT

58

VI

58

VI

D/A channel signal-to-distortion ratio

MAX

56
50
44

dB

38
32
26
20

NOTE 7: The test condition is a 1-kHz input signal with a 24-kHz conversion rate. The load impedance for the DAC is
600 Q. Input and output voltages are referred to Vref.

3.3.9

Receive and Transmit Gain and Dynamic Range (see Note 8)
PARAMETER

TEST CONDITIONS

MIN

= -48 dB to 0 dB signal range
VI =-48 dB to 0 dB signal range

Transmit gain tracking error

Vo

Receive gain tracking error

TYPt

MAX

UNIT

±0.05

±0.25

dB

±0.05

±0.25

dB

NOTE 8: Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 dB relative to Vretl.

3.3.10

Receive Channel Band-Pass Filter Transfer Function, SCF fclock
Input (IN+ - IN-) is a ±3-V Sine Wave* (see Note 9)

PARAMETER

TEST
CONDITION

FREQUENCY

ADJUSTMENT

MIN

TYPt

MAX

f::; 150 Hz

K1 x 0 dB

-33

-29

-25

=300 Hz
f = 450 Hz to 9300 Hz
f =9300 Hz to 9900 Hz
f = 9900 Hz to 10950 Hz
f = 11.4 kHz
'f = 12 kHz

K1 x-0.26 dB

-4

-2

-1

K1 x 0 dB

-0.25

0

0.25

K1 x 0 dB

-0.3

0

0.3

K1 x 0 dB

-0.5

0

0.5

K1 x 2.3 dB

-2

-0.5

K1 x 2.7 dB

-16

-14

f

Filter gain

Input signal
reference is 0 dB

=432 kHz,

f ~ 13.2 kHz

K1 x 3.2 dB

-40

f~15kHz

K1 x 0 dB

-60

UNIT

dB

All typical values are at TA =25°C.
:j: The MIN, TYP, and MAX specifications are given for a 432-kHz SCF clock frequency. A slight error in the 432-kHz SCF
can result from inaccuracies in the MSTR ClK frequency, resulting from crystal frequency tolerances. If this frequency
error is less than 0.25%, the ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specifications, where
K1 = 100 x [(SCF frequency - 432 kHz)/432 kHz). For errors greater than 0.25'0/0, see Note 9.
NOTE 9: The filter gain outside of the pass band is measured with respect to the gain at 1 kHz. The filter gain within the
pass band is measured with respect to the average gain within the pass band. The pass bands are 450 Hz
to 10.95 kHz and 0 to 10.95 kHz for the band-pass and low-pass filters, respectively. For switched-capacitor
filter clocks at frequencies other than 432 kHz, the filter response is shifted by the ratio of switched-capacitor
filter clock frequency to 432 kHz.

t

4-165

3.3.11

Receive and Transmit Channel Low-Pass Filter Transfer Function,
SCF fclock 432 kHz (see ,Note 9)

=

PARAMETER

TEST
CONDITION

,

Filter gain

Input signal
reference is 0 dB

FREQUENCY
RANGE

= 0 Hz to 9300 Hz
= 9300 Hz to 9900 Hz .
f = 9900 Hz to 10950 Hz
f = 11.4 kHz
f = 12 kHz

ADJUSTMENT
ADDEND*

MIN

TYPt

MAX

f

K1 x 0 dB

-0.25

0

0.25

f

K1 x 0 dB

-0.3

0

0.3

K1 x 0 dB

-0.5

0

0.5

-5

-2

-0.5

-16

-14

f

~

13.2 kHz

f ~ 15 kHz

K1 x 2.3 dB
K1 x2.7 dB
K1 x 3.2 dB

-40

K1 x 0 dB

-60

UNIT

dB

t All tYPical values are at TA = 25°C.
:j: The MIN, TYP, and MAX specifications are given for a 432-kHz SCF clock frequency. A slight error in the 432-kHz SCF
may result from inaccuracies in the MSTR ClK frequency, resulting from crystal frequency tolerances. If this frequency
error is less than 0.25%, the ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specifications, where
K1 = 100 x [(SCF frequency - 432 kHz)/432 kHz]. For errors greater than 0.25%, see Note 9.
NOTE 9: The filter gain outside of the pass band is measured with respect to the gain at 1 kHz. The filter gain within the
pass band is measured with respect to the average gain within the pass band. The pass bands are 450 Hz
to 10.95 kHz and 0 to 10.95 kHz for the band-pass and low-pass filters, respectively. For switched-capacitor
filter clocks at frequencies other than 432 kHz, the filter response is shifted by the ratio of switched-capacitor
filter clock frequency to 432 kHz.

3.4

Operating CHaracteristics Over Recommended Operating Free-Air
Temperature Range, VCC+ 5 V, VCC- -5 V, Voo 5 V

3.4.1

=

=

=

Receive and Transmit Noise (Measurement Includes Low-Pass and Band-Pass
Switched-Capacitor Filters)
PARAMETER

TEST CONDITION.S

broadband with (sin x)/x
Transmit
noise

broadband without (sin x)/x

oto 12 kHz with (sin x)/x
oto 12 kHz without (sin x)/x

Receive noise (see Note 10)

t

DX = input = 00000000000000,
constant input code

Inputs grounded, gain

=1

MIN

TYPt

MAX

280

500

250

450

250

400

240

400

300

500

18

All typical values are at TA = 25°C.
NOTE 10: The noise is computed by statistically evaluating the digital output of the AID converter.

4-166

UNIT

~Vrms

~Vrms

dBrncO

3.5

Timing Requirements

3.5.1

Serial Port Recommended Input Signals
MIN

PARAMETER

tc(MCLK)

Master clock cycle time

tr(MCLK)

Master clock rise time

tf(MCLK)

Master clock fall time
25%

RESET pulse duration (see Note 11)
tsu(DX)

OX setup time before SClKt

OX hold time after SCLKJ,

UNIT

ns

95

Master clock duty cycle

th(DX)

MAX

10

ns

10

ns

75%

800

ns

20

ns
ns

tc(SCLK)/4

NOTE 11: RESET pulse duration is the amount of time that the reset pin is held below 0.8 V after the power supplies have
reached their recommended values.

3.5.2

Serial Port - AIC Output Signals, CL
For All Other Outputs

=30 pF for SHIFT ClK Output, CL =15 pF

PARAMETER

tc(SCLK)

Shift clock (SCLK) cycle time

tf(SClK)

Shift clock (SCLK) fall time

tr(SCLK)

Shift clock (SCLK) rise time
Shift clock (SCLK) duty cycle

MIN

TYPt

MAX

3

8

ns

8

ns

ns

380

3
45

55

Delay from SCLKt to FSRlFSXlFSDt

30

td(CH-FH)

Delay from SCLKt to FSR/FSXlFSDt

35

td(CH-DR)

DR valid after SCLKt

td(CH-FL)

UNIT

%
ns

90

ns

90

ns

td(CH-ELI

Delay from SCLKt to EODXlEODRJ, in word mode

90

ns

td(CH-EH)

Delay from SCLKt to EODXlEODRt in word mode

90

ns

tf(EODX)

EO OX fall time

2

8

ns

tf(EODR)

EODR fall time

2

8

ns

td(CH-EL)

Delay from SCLKt to EODXlEODRJ, in byte mode

90

ns

td(CH-EH)

Delay from SCLKt to EODXlEODRt in byte mode

90

ns

Id(MH-SL)

Delay from MSTR CLKt to SCLKt

65

170

ns

td(MH-SH)

Delay from MSTR ClKt to SClKt

65

170

ns

tTypical values are at TA = 25°C.

4-167

4-168

4

Parameter Measurement Information
Rfb
IN+
or
AUXIN+

R

INor
AUXIN-

R

Rfb
Rfb = R for 06 = 1 and 07 = 1

06=Oand07= 0
Rfb = 2R for 06 = 1 and 07 = 0
Rfb = 4R for 06 = 0, and 07 = 1

Figure 4-1. IN+ and IN - Gain Control Circuitry
Table 4-1. Gain Control Table (Analog Input Signal Required for
Full-Scale Bipolar AID Conversion Twos Complement)t
INPUT
CONFIGURATIONS
Differential configuration
Analog input = IN+ - IN= AUX IN+ - AUX IN-

Single-ended configuration
Analog input = IN+ - ANLG GND
= AUX IN+ - ANLG GND

CONTROL REGISTER BITS

ANALOG
INPUrt§

A/O CONVERSION
RESULT

06

07

1
0

1
0

VID =±6 V

±full scale

1

0

VID =±3 V

±full scale

0

1

VID = ±1.5 V

±full scale

1
0

1
0

VI =±3 V

±half scale

1

0

VI =±3 V

±full scale

0

1

VI=±1.5V

±full scale

t VCC+ = 5 V, VCC- = -5 V, VDD = 5 V
:j: VID = Differential Input Voltage, VI = Input voltage referenced to ground with IN- or AUX IN- connected to ground.
§ In this example, Vref is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog input not
exceed 0.1 dB below full scale.

4-169

SHIFT
ClK

2V

8V

,

,

I

,

'

, --.J

r- td (CH·DR)
II

DR ____~D~15~__~~--~D1~~D~O~-------------

I-

tsu (OX) -+j

Don't Care

DX------~~~~~~~~~~~~~~~~CJD~O~---~~~--­

,

DATA.DR ____~D~15~__~~--~D1~~D~O~'----~-------

I

Figure 4-2. Dual-Word (Telephone Interface) Mode Timing

SHIFT
ClK

2V

8V,

td (CH·Fl)
FSX, FSRt

,

,

I

,

I

I --.J

';\

r- td (CH-DR)

DR _____D_15____~~--~D1~~~-------------

r

tsu (OX) -+j
DX ______~E!~[J~)(~!)(J~)(~~Jc=~)(~~c=~D~O=>--~D7o~n'~t~Ca~r~e--I

td (CH·El) --.j j4-

-.j ~

td (CH·EH)

EODX, EODR*-----------------------------*\\------------~I
8 V"------./I~~--2V

Figure 4-3. Word Timing

t The time between falling edges of FSR is the AID conversion period and the time between falling edges of FSX is the
D/A conversion period.
'
:j: In the word format, EODX and EODR go low to signal the end of a 16-bit data word to the processor. The word-cycle

is 20 shift-clocks wide, giving a four-clock period setup time between data words.

4-170

-.j

r-- t r (SCLK)

Ir\.
FSR,
FSX
DR

r \ . . /II '-"

~~

'-"

'-"

td (CH-FH)

'I 2 V
I

'C.:J'

I '-" 'C.:J'
~ td (CH-FL)

x

8V
08

r-

'C.:J'

'-"

'C.:J'

td (CH-FH)

I Ir.~~-f 2V

I
~:JCi?f\,----D_1__DO--+-1____
I
II

Don't Care

EODR,
EODX

II

Figure 4-4. Byte-Mode Timing
tThe time between falling edges of FSR is the AID conversion period, and the time between failling edges of"FSX is the D/A conversion period.
roox- or roDR is high, the first byte is transmitted or received, and when these signals are low, the second byte is
transmitted or received. Each byte-cycle is 12 shift-clocks long, allowing for a four-shift·clock setup time between byte transmissions.

:j: In the byte mode, when

!

----J

MSTRCLK

SHIFTCLK

_______

I
-+I J+~/~--------~\{II
~-

td (MH-SH)

""--------

Figure 4-5. Shift-Clock Timing

4.1

fd (MH-SL)

TMS32047 - Processor Interface
SN74lS74

SN74lS299
~

Sl
G2

OEN
'--

AO/PAO
A1/PA1
A2/PA2

TMS32010

G1
A

00-015

\

elK
OUT
INT

if

A-H

\

'---

G2
so ClK
G1

00-07
A-H

'\

-----J'

ox

~

---

SR

SN74lS299
Sl
QH

Dn

00-015

WE

08-015

\

L:3-

so ClK< r--G1

Y1 f--

YO IB
C
SN74lS138

QH

FSX

C2

SR

~
~

~
C1
10

TlC32047

OR

-

~

Figure 4-6. TMS320101TMS320C15-TLC32047 Interface Circuit

4-172

SHIFT
ClK

MSTR
ClK
EOOX

ClK OUT

-.--J

L
: I

SO,G1

00-015

-------«

Valid

)>-----------

(a) IN INSTRUCTION TIMING

ClK OUT

-.--J

L

WE

SN74lS138 V1

SN74lS299 ClK

00-015

-------«

Valid

)>----------

(b) OUT INSTRUCTION TIMING

Figure 4-7. TMS32010ITMS320C15-TLC32047 Interface Timing

4-173

5

Typical Characteristics
DIA AND AID LOW-PASS FILTER
RESPONSE SIMULATION
0.4

I

I

V

V\ '\

=25°C
Input =± 3 V Sine Wave

TA
0.2
III

"g

I
GI

"g

.a

·2

0

CI
III

:l5

/

"g

c

III

1\

~

-0.2

III

III
III

III

,

0.

-0.4

-0.6

o

3

15

12

6
9
Normalized Frequency

Figure 5-1
DIA AND AID LOW-PASS FILTER
RESPONSE SIMULATION
0

=

TA 25°C
See Figure 2-1 \
for Pass Band
,.. Input ± 3 V Sine Wave _
Detail

-10

=

-20
III

-30

"g

I
GI

"g

-40

::I

:::
c

CI
III

:l5

-50
-60
-70

(

-80
-90

o

\

I

II
3

6

9

12

15

18

~

d

21

24

i.--

27

30

Figure 5-2
NOTE: Absolute Frequency (kHz)

Normalized Frequency x SCF fclock (kHz)
432
4-175

D/A AND AID LOW·PASS GROUP DELAY
0.6

I

I

TA = 25°C
Input =±3 V Sine Wave
0.5
1/1

E
I

0.4

~
Gi
Q

..

CI.

::J
0

0.3

Cl

/'"

0.2

I

J
r\

"-

o
o

3

9
6
f - Frequency -kHz

12

15

Figure 5-3
AID BAND·PASS RESPONSE
0.4

1

1

=

I,

Hlgh·Pass SCF fclock 24 kHz
TA 25°C
Input ±3 V Sine Wave

=

0.2

=

10
'C

I
GI

'C

~

0

C

01

as
::E
'C
c
as

~

-0.2

1\

"v1\~ V

10
1/1
1/1

as

a..
-0.4

-0.6

o

3

6
9
f - Frequency - kHz

12

15

Figure 5-4
Normalized Frequency x SCF f clock (kHz)
NOTE : Absolute Frequency (kHz)

4-176

432

AID BAND-PASS FILTER RESPONSE SIMULATION
0
High-Pass SCF
fclock 24 kHz
-10
TA 25°C
Input ± 3 V Sine Wave
-20
-

\,

III

=

=
=

-30

"'0

I
Gl
"'0
::J

-

'2

Cl
111

::i!

-40
-50
-60
-70

,

(

:\ L
\/

-80
-90

II

o

3

6

9 12 15 18 21
f - Frequency - kHz

24

i.---

27

30

Figure 5-5
AID BAND-PASS FILTER GROUP DELAY
1.0

I

I

I

I

I

=

I

I

High-Pass SCF fclock 24 kHz
TA 25°C
Input ±3 V Sine Wave

=

0.9

=

0.8
III

E
I

0.6

>-

111

Qi

Q

1/\

0.5

~\

a.

..
::J

0

0.4

CJ

0.2

\

-'

/ \

0.1

o
o

1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
f - Frequency - kHz

Figure 5-6
NOTE : Absolute Frequency (kHz)

Normalized Frequency x SCF fclock (kHz)
432

4-177

AID CHANNEL HIGH-PASS·FILTER
20
TA

=25°C
=± 3 V Sine Wave

Input

10
0
III
't:I

I~

-10

I
Q)

't:I

:s
c

-20

«I

-30

:I:

r

CI

:::E

I

-40
-50
-60

o

150 300 450 600 750 900 1050 1200 1350 1500
Normalized Frequency

Figure 5-7
DIA (sin x)/x CORRECTION FILTER RESPONSE
4

2

't:I

I

V

/

III

0 r--

V

/

/

r

\

\

\

Q)

't:I
:s
:I:

c

CI

«I

:::E

-2

\

~

\

-4
TA

~

\

=25°C
=± 3 V Sine Wave

Input

":'6

o

I

I

I

3

6

9

I

I

12

15

18

21

24

27

30

f - Frequency - kHz

Figure 5-8
NOTE : Absolute Frequency (kHz)

4-178

Normalized Frequency x SCF f clock (kHz)
432

D/A (sin x)/x CORRECTION FILTER RESPONSE
325

=

TA 25°C
Input ± 3 V Sine Wave

=

260

Vr\

I/)

::1.

I

[;'
'ii

195

I \

0

a..

::I

e

130

<:)

65

V

./

-

o
o

3

6

9

12 15 18 21
f - Frequency - kHz

\
24

"
27

30

Figure 5-9
D/A (sin x)/x CORRECTION ERROR
2
TA = 25°C
Input = ± 3 V Sine Wave

1.6
1.2

/
/V
(sin x) Ix Correction

/
0.8
!XI

"tI
I
CII
"tI

0.4

CI
111

-0.4

.a
'2

./

"".,.

io"""

Er1ror

r-....
---- ...........

0

.........

"

:i

-0.8
-1.2
-1.6

-2

/'

o

\

......

"

28.8 kHz (sin x) Ix
Distortion
_

"

"'1\

\
1.5

3

4.5 6 7.5 9 10.5 12 13.5 15
f - Frequency - kHz

Figure 5-10
Normalized Frequency x SCF fclock (kHz)
NOTE : Absolute Frequency (kHz)

432

4-179

AID BAND.PASS GROUP DELAY
760

I

720 - I -

=

fII

::1.

I

680

~
"i

640

Q

CI.
:::I

e

600

as

560

~
fII
fII

-

,

I

I
V

=

J

/

\

520

CC

480

\,

"- -

440
400

I

=
=

V

c
as

al
Q

I

I

/

CI.
"g

I

Low·pass SCF fclock 144 kHz
High·pass SCF fclock 8 kHz
TA 25°C
Input ± 3 V Sine Wave

o

0.4

0.8

1.2

/'
1.6

V

V

/

2.0

2.4

2.8

3.2 3.6

f - Frequency - Hz

Figure 5-11
D/A LOW·PASS GROUP DELAY
560

fII

::1.

I

>..!!!

£!
as

360

c

as

320

cc

280

9"g
al
Q

II

I

=

200

/

V

/

J

240

,/

o

0.4

0.8

/

'I

'/

1.2 1.6 2.0 2.4
f - Frequency - Hz

Figure 5-12

4-180

I

I

=

440
400

~
fII
fII

I

=

..

CI.
:::I
0

I

520 r- Low·pass SCF fclock 144 kHz
TA 25°C
Input ± 3 V Sine Wave
480 r-

2.8

3.2 3.6

AID SIGNAL-TO-DISTORTION RATIO

vs
INPUT SIGNAL
100

III

"0
I
0

~
a:
c

1-kHz Input Signal
90 r- 16-kHz Conversion Rate
TA = 25°C
80
Gain = 1

70

Gain'= 4

60

, ./ V

0

t:
0
u;

50

is

40

m
c

30

en

20

~

~-

/

CI

10

o

-50

-40
-30
-20
-10
o
Input Signal Relative to Vref - dB

10

Figure 5-13
AID GAIN TRACKING
(GAIN RELATIVE TO GAIN AT O-dB INPUT SIGNAL)
0.5
0.4

I-

0.3
III

"0
I
CI

0.2
0.1

c

:i2
u

as

~

c
·i

Cl

1-kHz Input Signal
16-kHz Conversion Rate
TA = 25°C

0.0

,,

-

-0.1
-0.2
-0.3
-0.4
-0.5
-50

-40
-30
-20
-10
o
Input Signal Relative to Vref - dB

10

Figure 5-14

4-181

D/A CONVERTER SIGNAL-TO-DISTORTION RATIO
vs
INPUT SIGNAL
100

III
"0
I
0
;
111

II:

I

1-kHz Input Signal Into 600 n
90 r- 16-kHz Conversion Rate
TA = 25°C
80
70

c

60

:e0

50

0

' II

Q

40

iii

30

~
c

,

V
./

/

V

""

./

........

CI

i:i)

20
10

o
- 50

- 40
- 30
- 20
-10
o
Input Signal Relative to Vref - dB

10

Figure 5-15
D/A GAIN TRACKING (GAIN RELATIVE TO GAIN
AT O-dB INPUT SIGNAL)
0.5
0.4
0.3
III

"0
I
CI

I

0.2
0.1

c

:ii2
U

0.0

111

~

c

·iii
0

I

1-kHz Input Signal Into 600 n
16-kHz Conversion Rate
TA = 25°C

-

'-

,V

-0.1
-0.2
-0.3
-0.4
-0.5
- 50

o
- 40
- 30
- 20
-10
Input Signal Relative to Vref - dB
Figure 5-16

4-182

10

AID SECOND HARMONIC DISTORTION

vs
INPUT SIGNAL
-100
-90
III
"0
I

-80

0

-70

c

1::
0

iii

-60

(,)

-50

1·kHz Input Signal
16·kHz Conversion Rate
TA = 25°C

,/

-

is

'2

V

~ ...............

0

...111

E

-40

::c
"0
c

-30

0

(,)

~

-20
-10

o

-50

-40
-30
-20
-10
o
Input Signal Relative to Vref - dB

10

Figure 5-17
DfA SECOND HARMONIC DISTORTION

vs
INPUT SIGNAL
-100
-90
III
"0
I

-80

0

-70

Ul

-60

c

r0

-

1·kHz Input Signal Into 600 Q
16·kHz Conversion Rate
TA = 25°C

V

~~

-

V"

........

is
(,)

'2
0
E

...
111

-50
-40

::c
"0
c
0

-30

Q)

-20

(,)

en

-10

o

-50

-40
-30
":20
-10
o
Input Signal Relative to Vref - dB

10

Figure 5-18

4-183

AID THIRD HARMONIC DISTORTION

vs
INPUT SIGNAL
-1000

.11:1

"c
I

0

-70

1:
0

-60

is
()

-50

'2
0
E

-40

Ui

..
"..
:c

"

1-Hz Input Signal
-90 - 16-kHz Conversion Rate
TA = 25°C
-80 -

..V' . /

/'

.., ~ ~

1\1

:r:

-30

I-

-20
-10

o

- 50

- 40
- 30
- 20
-10
o
Input Signal Relative to Vref - dB

10

Figure 5-19
D/A THIRD HARMONIC DISTORTION

vs
INPUT SIGNAL
-100
-90
11:1

"c
I

0

-80

-60

is
,2

-50

..

-40

c
0
E

I

I

V""\.

-.70

1:0
Ui

I

1-kHz Input Signal Into 600 n
16-kHz Conversion Rate
TA = 25°C

~

./

"

1\1

:r:

'E

:c

I-

-30
-20
-10

o
- 50

o
- 40
- 30
- 20
-10
Input Signal Relative to Vref - dB
Figure 5-20

4-184

10

6

Application Information
TMS32020/C25

TLC32047

CLKOUT

MSTRCLK

FSX

FSX

DX

DX

FSR

FSR

DR

DR

C

REF
ANLGGND

-5V

VCC-

SHIFTCLK

CLKR

5V

VCC+

5V

VDD

CLKX
DGTLGND
A

C = 0.2 JlF, Ceramic

Figure 6-1. AIC Interface to the TMS32020/C25 Showing Decoupling
Capacitors and Schottky Diodet

t Thomson Semiconductors
VCC

3 V Output
5000
0.01 JlF

TL431
25000

=

=
=

FOR: VCC 12 V, R 7200 0
VCC = 10V, R = 56000
VCC:: 0 V, R 1600 0

Figure 6-2. External Reference Circuit for TLC32047

4-185

4-186

TLC320AC01C
Data Manual
Single-Supply Analog Interface Circuit

SLAS057D
October 1996

•
TEXAS
INSTRUMENTS

Printed on Recycled Paper

IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
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performance, or infringement of patents or services described herein. Nor does TI warrant or
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Copyright © 1996, Texas Instruments Incorporated

Contents
Section

Title

Page

1

Introduction ................................................... ..........
1.1 Features......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.3 Terminal Assignments ................................................
1.4 Terminal Functions ...................................................
1.5 Register Functional Summary .........................................

4-193
4-194
4-195
4-195
4-197
4-200

2

Detailed Description .....................................................
2.1 Definitions and Terminology ...........................................
2.2 Reset and Power-Down Functions .....................................
2.2.1 Reset ........................................................
2.2.2 Conditions of Reset ............................................
2.2.3 Software and Hardware Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.2.4 Register Default Values After POR,
Software Reset, or RESET Is Applied .............................
2.3 Master-Slave Terminal Function .......................................
2.4 ADC Signal Channel .................................................
2.5 DAC Signal Channel ...... :..........................................
2.6 Serial Interface ......................................................
2.7 Number of Slaves ....................................................
2.8 Required Minimum Number of MCLK Periods ...........................
2.8.1 TLC320AC01 AIC Master-Slave Summary ........................
2.8.2 Notes on TLC320AC01/02 AIC Master-Slave Operation .............
2.9 Operating Frequencies ...............................................
2.9.1 Master and Stand-Alone Operating Frequencies ...................
2.9.2 Slave and Codec Operating Frequencies .........................
2.10 Switched-Capacitor Filter Frequency (FCLK) ............................
2.11 Filter Bandwidths ....................................................
2.12 Master and Stand-Alone Modes .......................................
2.12.1 Register Programming. . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . . ..
2.12.2 Master and Stand-Alone Functional Sequence. . . . . . . . . . . . . . . . . . . ..
2.13 Slave and Codec Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.13.1 Slave and Codec Functional Sequence ..... . . . . . . . . . . . . . . . . . . . . ..
2.13.2 Slave Register Programming ....................................
2.14 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.14.1 Frame-Sync Function ..........................................
2.14.2 Data Out (DOUT) ..............................................
2.14.3 Data In (DIN) ..................................................
2.14.4 Hardware Program Terminals (FC1 and FCO) ......................
2.14.5 Midpoint Voltages (A DC VMID and DAC VMID) .....................
2.15 Device Functions ....................................................
2.15.1 Phase Adjustment .............................................
2.15.2 Analog Loopback ..............................................

4-201
4-201
4-202
4-202
4-202
4-202
4-202
4-204
4-204
4-204
4-204
4-205
4-206
4-206
4-207
4-209
4-209
4-209
4-209
4-209
4-209
4-209
4-210
4-210
4-211
4-211
4-211
4-211
4-212
4-212
4-212
4-213
4-213
4-213
4-214
4-189

Contents (Continued)
Section

2.16

2.17

2.18

2.19

2.20

3

Title

Page

2.15.3 16-Bit Mode ...................................................
2.15.4 Free-Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.15.5 Force Secondary Communication ................................
2.15.6 Enable Analog Input Summing ...................................
2.15.7 DAC Channel (sin x)/x Error Correction ...........................
Serial Communications ...............................................
2.16.1 Stand-Alone and Master-Mode Word Sequence and
Information Content During Primary and
Secondary Communications .....................................
2.16.2 Slave and Codec-Mode Word Sequence and
Information Content During Primary and
Secondary Communications .....................................
Request for Secondary Serial Communication and Phase Shift ............
2.17.1 Initiating a Request ............................................
2.17.2 Normal Combinations of Control .................................
2.17.3 Additional Control Options ......................................
Primary Serial Communications ........................................
2.18.1 Primary Serial Communications Data Format . . . . . . . . . . . . . . . . . . . . ..
2.18.2 Data Format From DOUT During
Primary Serial Communications ..................................
Secondary Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.19.1 Data Format to DIN During Secondary Serial Communications .......
2.19.2 Control Data-Bit Function in Secondary Serial Communication .......
Internal Register Format ..............................................
2.20.1 Pseudo-Register 0 (No-Op Address) .............................
2.20.2 Register 1 (A Register) .........................................
2.20.3 Register 2 (B Register) .........................................
2.20.4 Register 3 (A' Register) .........................................
2.20.5 Register 4 (Amplifier Gain-Select Register) . . . . . . . . . . . . . . . . . . . . . . ..
2.20.6 Register 5 (Analog Configuration Register) ........................
2.20.7 Register 6 (Digital Configuration Register) .........................
2.20.8 Register 7 (Frame-Sync Delay Register) ..........................
2.20.9 Register 8 (Frame-Sync Number Register) ........................

4-214
4-214
4-214
4-215
4-215
4-215

Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.1 Absolute Maximum Ratings Over Operating
Free-Air Temperature Range ..........................................
3.2 Recommended Operating Conditions ...................................
3.3 Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, MCLK = 5.184 MHz, Voo = 5 V, Outputs
Unloaded, Total Device ...............................................
3.4 Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, Voo = 5 V, Digital 1/0 Terminals (DIN, DOUT, EOC,
FCO, FC1, FS, FSD, MCLK, MIS, SCLK) ................................

4-190

4-215

4-216
4-217
4-217
4-217
4-217
4-218
4-219
4-219
4-219
4-219
4-219
4-220
4-220
4-220
4-221
4-221
4-222
4-222
4-223
4-223
4-224

4-225
4-225
4-225

4-226

4-226

Contents (Continued)
Section

3.5

3.6

3.7

Title

Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, Voo = 5 V, ADC and DAC Channels ...............
3.5.1 ADC Channel Filter Transfer Function,
FCLK = 144 kHz, fs = 8 kHz .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.5.2 ADC Channel Input, Voo = 5 V,
Input Amplifier Gain = 0 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.5.3 ADC Channel Signal-to-Distortion Ratio,
Voo = 5 V, fs = 8 kHz ............................................
3.5.4 DAC Channel Filter Transfer Function,
FCLK = 144 kHz, fs = 9.6 kHz, Voo = 5 V .........................
3.5.5 DAC Channel Signal-to-Distortion Ratio,
Voo = 5 V, fs = 8 kHz ...........................................
3.5.6 System Distortion, Voo = 5 V, fs = 8 kHz,
FCLK = 144 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.5.7 Noise, Low-Pass and Band-Pass SwitchedCapacitor Filters Included, Voo = 5 V .............................
3.5.8 Absolute Gain Error, VOO = 5 V, fs = 8 kHz .......................
3.5.9 Relative Gain and Dynamic Range, VOO = 5 V, fs = 8 kHz ...........
3.5.10 Power-Supply Rejection, Voo = 5 V ..............................
3.5.11 Crosstalk Attenuation, Voo = 5 V ................................
3.5.12 Monitor Output Characteristics, VOO = 5 V ........................
Timing Requirements and Specifications in Master Mode .................
3.6.1 Recommended Input Timing Requirements for
Master Mode, Voo = 5 V ........................................
3.6.2 Operating Characteristics Over Recommended Range of
Operating Free-Air Temperature, Voo = 5 V .......................
Timing Requirements and Specifications in Slave Mode and
Codec Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.7.1 Recommended Input Timing Requirements for
Slave Mode, Voo = 5 V .........................................
3.7.2 Operating Characteristics Over Recommended Range of Operating
Free-Air Temperature, Voo = 5 V ................................

Page

4-226
4-226
4-227
4-227
4-227
4-228
4-228
4-229
4-229
4-229
4-230
4-230
4-231
4-232
4-242
4-232
4-233
4-233
4-233

4

Parameter Measurement Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-235

5

Typical Characteristics ........................... ........................ 4-241

6

Application Information .................................................. 4-255

A ,Primary Control Bits ..................................................... 4-259
B

Secondary Communications ............................................. 4-261

C

TLC320AC01 C/TLC320AC02C Specification Comparisons . . . . . . . . . . . . . . . . .. 4-263

o

Multiple TLC320AC01 ITLC320AC02 Analog Interface Circuits
on One TMS320C5X DSP Serial Port ...................................... 4-267
4-191

List of Illustrations
Figure

Title

Page

1-1

Control Flow Diagram ................................................. 4-199

2-1
2-2
2-3

Functional Sequence for Primary and Secondary Communication ...........
Timing Sequence ......................................... ,...........
Master and Stand-Alone Functional Sequence ............................
Slave and Codec Functional Sequence ..................................

4-205
4-206
4-216
4-216

IN+ and IN- Gain-Control Circuitry ......................................
AIC Stand-Alone and Master-Mode Timing ...............................
AIC Slave and Codec Emulation Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Master or Stand-Alone FS and FSD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Slave FS to FSD Timing ...............................................
Slave SCLKto FSD Timing .............................................
DOUT Enable Timing From Hi-Z ........................................
DOUT Delay Timing to Hi-Z ............................................
EOC Frame Timing ....................................................
Master-Slave Frame-Sync Timing After a Delay Has Been
Programmed Into the FSD Registers ....................................
4-11 Master and Slave Frame-Sync Sequence with One Slave ..................

4-235
4-236
4-236
4-237
4-237
4-237
4-238
4-238
4-238

Stand-Alone Mode (to DSP Interface) ....................................
Codec Mode (to DSP Interface) .........................................
Master With Slave (to DSP Interface) ....................................
Single-Ended Input (Ground Referenced) ................................
Single-Ended to Differential Input (Ground Referenced) ....................
Differential Load ......................................................
Differential Output Drive (Ground Referenced) ............................
Low-Impedance Output Drive ...........................................
Single-Ended Output Drive (Ground Referenced) .........................

4-255
4-255
4-256
4-256
4-257
4-257
4-257
4':"'258
4-258

2-4
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10

6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9

4-239
4-239

List of Tables
Table

Title

Page

1-1

Operating Frequencies ................................................ 4-199

2-1
2-2
2-3

Master-Slave Selection
Sampling Variation With
Software and Hardware
Phase-Shift Truth Table

4-1

Gain Control (Analog Input Signal Required for
Full-Scale Bipolar AID-Conversion 2s Complement) ....................... 4-235

4-192

................................................ 4-204
A' ............................................. 4-213
Requests for Secondary Serial-Communication and
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-218

1

Introduction

The TLC320AC01 t analog interface circuit (AIC) is an audio-band processor that provides an
analog-to-digital and digital-to-analog input/output interface system on a single monolithic CMOS chip. This
device integrates a band-pass switched-capacitor antialiasing input filter, a 14-bit-resolution
analog-to-digital converter (ADC), a 14-bit-resolution digital-to-analog converter (DAC), a low-pass
switched-capacitor output-reconstruction filter, (sin x)/x compensation, and a serial port for data and control
transfers.
The internal circuit configuration and performance parameters are determined by reading control
information into the eight available data registers. The register data sets up the device for a given mode of
operation and application.
The major functions of the TLC320AC01 are:
1.

To convert audio-signal data to digital format by the ADC channel

2.

To provide the interface and control logic to transfer data between its serial input and output
terminals and a digital signal processor (DSP) or microprocessor

3.

To convert received digital data back to an audio signal through the DAC channel

The antialiasing input low-pass filter is a switched-capacitor filter with a sixth-order elliptic characteristic. The
high-pass filter is a singlecpole filter to preserve low-frequency response as the low-pass filter cutoff is
adjusted. There is a three-pole continuous-time filter that precedes this filter to eliminate any aliaSing caused
by the filter clock signal.
The output-reconstruction switched-capacitor filter is a sixth-order elliptic transitional low-pass filter followed
by a second-order (sin x)/x correction filter. This filter is followed by a three-pole continuous-time filter to
eliminate images of the filter clock signal.
The TLC320AC01 consists of two signal-processing channels, an ADC channel and a DAC channel, and
the associated digital control. The two channels operate synchronously; data reception at the DAC channel
and data transmission from the ADC channel occur during the same time interval. The data transfer is in
2s-complement format.
There are three basic modes of operation available: the stand-alone analog-interface mode, the
master-slave mode, and the linear-codec mode. In the stand-alone mode, the TLC320AC01 generates the
shift clock and frame synchronization for the data transfers and is the only AIC used. The master-slave mode
has one TLC320AC01 as the master that generates the master-shift clock and frame synchronization; the
remaining AICs are slaves to these signals. In the linear-codec mode, the shift clock and the framesynchronization signals are externally generated and the timing can be any of the standard codec-timing
patterns.
Typical applications for this device include modems, speech processing, analog interface for DSPs,
industrial-process control, acoustical-signal processing, spectral analysis, data acquisition, and
instrumentation recorders.
The TLC320AC01 C is characterized for operation from ODC to 70 DC.

tThe TLC320AC01 is functionally equivalent to the TLC320AC02 and differs in the electrical speCifications as shown
in Appendix C.

4-193

Features

1.1

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•

t

General-Purpose Signal-Processing Analog Front End (AFE)
Single 5-V Power Supply
Power Dissipation ... 100 mW Typ
Signal-to-Distortion Ratio ... 70 dB Typ
Programmable Filter Bandwidths (Up to 10.8 kHz) and Synchronous ADC and DAC Sampling
Serial-Port Interface
Monitor Output With Programmable Gains of 0 dB, -8 dB, -18 dB, and Squelch
Two Sets of Differential Inputs With Programmable Gains of 0 dB, 6 dB, 12 dB, and Squelch
Differential or Single-Ended Analog Output With Programmable Gains of 0 dB, -6 dB, -12 dB,
and Squelch
Differential Outputs Drive 3-V Peak Into a 600-0 Differential Load
Differential Architecture Throughout
1-~m

Advanced LinEPICTM Process

14-Bit Dynamic-Range ADC and DAC
2s-Complement Data Format
Application Report Availablet

Designing with the TLC320AC01 Analog Interface for DSPs (SLAA006)

LinEPIC is a trademark of Texas Instruments Incorporated.

4-194

1.2

Functional Block Diagram

IN+
INAUXIN+
AUXIN-

26
25
28
27

11 DOUT
12
FS

MONOUT

Mis

14
13

18

FCO
FC1
OUT+
OUT-

MCLK
SCLK

10 DIN
17 FSD

3
4

19 EOC

2
PWR
DWN

DAC
VDD

DAC
GND

DGTL
VDD

ADC
VMID

ADC
VDD

ADC
GND

SUBS

DAC
VMID

RESET

Terminal numbers shown are for the FN package.

1.3

Terminal Assignments
FNPACKAGE
(TOP VIEW)

I

I~ 5

+ I
+oo~z

xx +
I-I-Ia:z
:::::>:::::> so:::::>:::::> z

000..:2:««
DAC VDD
DAC VMID
DAC GND
RESET
DGTL VDD
DIN
DOUT

4 3 2
282726
S
0
6
7
8
9
10
11
12 13 1415161718
ICI) ~

25
24
23
22
21
20
19

INADC VDD
ADC VMID
ADC GND
SUBS
DGTLGND
EOC

'-1

0 ICI)
0
u.....J ~
...JOO(j)~
0 Ou..u..u..
(j) :2:

4-195

1.3

Terminal Assignments (Continued)
PM PACKAGE
(TOP VIEW)

§
>
.....

a
0

f-

LU

Q

0

>:::E

>0

0000000fBoo~00~0~
zzzzzoza:zzozzozo
DIN
NC
DOUT
FS
NC
NC
NC
SCLK
NC
MCLK
FCD
FC1
NC
FSD
NC

Mis

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
10
2
47
46
3
4
45
5
44
43
6
7
42
8
41
40
9
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

000000(1)00000000
ZZZZZZOJZZZZZ~Z



>

«

«

0
0

0
0

NC
NC
OUTNC
NC
OUT+
PWR DWN
NC
MaN OUT
NC
AUXIN+
AUXININ+
INNC
NC

1.4

Terminal Functions
TERMINAL

NAME

I/O

DESCRIPTION

NO.t

NO.*

ADCVDD

24

32

I

Analog supply voltage for the ADC channel

ADCVMID

23

3D

0

Midsupply for the ADC channel (requires a bypass capacitor). ADC VMID must be
buffered when used as an external reference.

ADCGND

22

27

I

Analog ground for the ADC channel

AUX IN+

28

38

I

Noninverting input to auxiliary analog input amplifier

AUX IN-

27

37

I

Inverting input to auxiliary analog input amplifier

DACVDD

5

49

I

Digital supply voltage for the DAC channel

DACVMID

6

51

0

Midsupply for the DAC channel (requires a bypass capacitor). DAC VMID must be
buffered when used as an external reference.

DACGND

7

54

I

Analog ground for the DAC channel

DIN

1D

1

I

Data input. DIN receives the DAC input data and command information and is
synchronized with SCLK.

DOUT

11

3

0

Data output. DOUT outputs the ADC data results and register read contents.
DOUT is synchronized with SCLK.

DGTL VDD

9

59

I

Digital supply voltage for control logic
Digital ground for control logic

DGTLGND

2D

22

I

EOC

19

17

0

End-of-conversion output. EOC goes high at the start of the ADC conversion
period and low when conversion is complete. EOC remains low until the next ADC
conversion period begins and indicates the internal device conversion period.

FCD

15

11

I

Hardware control input. FCD is used in conjunction with FC1 to request secondary
communication and phase adjustments. FCD should be tied low if it is not used.

FC1

16

12

I

Hardware control input. FC1 is used in conjunction with FCD to request secondary
communication and phase adjustments. FC1 should be tied low if it is not used.

FS

12

4

I/O

Frame synchronization. When FS goes low, DIN begins receiving data bits and
DOUT begins transmitting data bits. In master mode, FS is low during the
simultaneous 16-bit transmission to DIN and from DOUT. In slave mode, FS is
externally generated and must be low for one shift-clock period minimum to initiate
the data transfer.

FSD

17

14

0

Frame-synchronization delayed output. This active-low output synchronizes a
slave device to the frame synchronization timing of the master device. FSD is
applied to the slave FS input and is the same duration as the master FS signal but
delayed in time by the number of shift clocks programmed in the FSD register.

IN+

26

36

I

Noninverting input to analog input amplifier

IN-

25

35

I

Inverting input to analog input amplifier

MCLK

14

1D

I

The master-clock input drives all the key logic signals of the AIC.

1

4D

0

The monitor output allows monitoring of analog input and is a high-impedance
output.

18

16

I

Master/slave select input. When M/S is high, the device is the master and when
low, it is a slave.

MONOUT
M/S

Terminal numbers shown are for the FN package.
:j: Terminal numbers shown are for the PM package.

4-197

1.4

Terminal Functions (Continued)
TERMINAL

I/O

DESCRIPTION

43

0

Noninverting output of analog output power amplifier. OUT+ can drive transformer
hybrids or high·impedance loads directly in a differential connection or a
single·ended configuration with a buffered VMID.

4

46

0

Inverting output of analog output power amplifier. OUT-is functionally identical
with and complementary to OUT +.

PWRDWN

2

42

I

Power-down input. When PWR DWN is taken low, the device is powered down
such that the existing internally programmed state is maintained. When PWR
DWN is brought high, full operation resumes.

RESET

8

57

I

Reset input that initializes the internal counters and control registers. RESET
initiates the serial data communications, initializes all of the registers to their
default values, and puts the device in a preprogrammed state. After a low-going
pulse on RESET, the device registers are initialized to provide a 16-kHz
data-conversion rate and 7.2-kHz filter bandwidth for a 1O.368-MHz master clock
input signal.

SCLK

13

8

I/O

Shift clock. SCLK clocks the digital data into DIN and out of DOUT during the
frame-synchronization interval. When configured as an output (MiS high), SCLK
is generated internally by dividing the master clock signal frequency by four. When
configured as an input (MiS low), SCLK is generated externally and
synchronously to the master clock. This signal clocks the serial data into and out
of the device.

SUBS

21

24

NAME

t

NO.t

NO.*

OUT+

3

OUT-

*

I

Substrate connection. SUBS should be tied to ADC GND.

Terminal numbers shown are for the FN package.
Terminal numbers shown are for the PM package.

4-198

I

Processor

.~

5.184 MHz
10.368 MHz

- - - - - - - - - - - - - - - ~-------MCLK

SCLK

......

1.296 MHz ~
2.592 MHz

A Register + A' Register
(8 bits)
2s Complement

A Register
(8 bits)

I

Divide by 4

FCLK [Iow~pass filter and
(sin x)/x filter clock]

I

p-

Control

t

Normal

Phase ShiH

0'

--

Single, A-Counter
Period
One-Shot

)

B Register
(8 bits)

~

I
Program Divide
A Counter
(8 bits)

576kHz

Divide by2l
288kHz

Conversion
Rate

B Counter

Figure 1-1. Control Flow Diagram
Table 1-1. Operating Frequencies
FCLK
(kHz)

LOW-PASS FILTER
BANDWIDTH
(kHz)

144

3.6

288

432

NOTES:

B REGISTER CONTENTS
(Program No. of Filter Clocks)
(Decimal)

CONVERSION
RATE
(kHz)

HIGH-PASS
POLE FREQUENCY
(Hz)

20 (see Note 1)
18
15
10 (see Note 2)

7.2
8
9.6
14.4

36
40
48
72

7.2

20 (see Note 1)
18
15
10 (see Notes 2 and 3)

14.4
16
19.2
28.8

72
80
96
144

10.8

20 (see Note 1)
18
15 (see Note 3)
10 (see Notes 2 and 3)

21.6
24
28.8
43.2

108
120
144
216

1. The B register can be programmed for values greater than 20; however, since the sample rate is lower than
7.2 kHz and the internal filter remains at 3.6 kHz, an external antialiasing filter is required.
2. When the B register is programmed for a value less than 10, the ADC and the DAC conversions are not
completed before the next frame-sync signal and the results are in error.
3. The maximum sampling rate for the ADC channel is 43.2 kHz. The maximum rate for the DAC channel is
25 kHz.

4-199

1.5

Register Functional Summary

There are nine data registers that are used as follows:
Register 0

The No-op register. The 0 address allows phase adjustments to be made without
reprogramming a data register.

Register 1

The A register controls the count of the A counter.

Register 2

The B register controls the count of the B counter.

Register 3

The A' register controls the phase adjustment of the sampling period. The adjustment is
equal to the register value multiplied by the input master period.

Register 4

The amplifier gain register controls the gains of the input, outp,ut, and monitor amplifiers.

Register 5

The analog configuration register controls:

Register 6

•

The addition/deletion of the high-pass filter to the ADC signal path

•

The enable/disable of the analog loopback

•

The selection of the regular inputs or auxiliary inputs

•

The function that allows processing of signals that are the sum of the regular inputs and
the auxiliary inputs (VIN + VAUX IN)

The digital configuration register controls:
•

Selection of the free-run function

•

FSD [frame-synchronization (sync) delay] output enable/disable

•

Selection of 16-bit function

•

Forcing secondary communications

•

Software reset

•

Software power down

Register 7

The frame-sync delay register controls the time delay between the master-device frame
sync and slave-device frame sync. Register 7 must be the last register programmed when
using slave devices since all register data is latched and valid on the sixteenth falling edge
of SCLK. On the sixteenth falling edge of SCLK, all delayed frame-sync intervals are shifted
by this programmed amount.

Register 8

The frame-sync number register informs the master device of the numbe~ of slaves that are
connected in the chain. The frame-sync number is equal to the number of slaves plus one.

4-200

2
2.1

Detailed Description
Definitions and Terminology

ADC Channel
Codec Mode

d
Dxx
DAC Channel

All signal processing circuits between the analog input and the digital conversion
results at DOUT
The operating mode under which the device receives shift clock and frame-sync
signals from a host processor. The device ,has no slaves.
The d represents valid programmed or default data in the control register format
(see Section 2.19) when discussing other data-bit portions of the register.
Bit position in the primary data word (xx is the bit number)
All signal processing circuits between the digital data word applied to DIN and the
differential output analog signal available at OUT + and OUT-

Data Transfer Interval The time during which data is transferred from DOUT and to DIN. This interval is 16
shift clocks regardless of whether the shift clock is internally or externally generated.
The data transfer is initiated by the falling edge of the frame-sync signal.
DSxx
Bit position in the secondary data word (xx is the bit number)
FCLK

An internal clock frequency that is a division of MCLK that controls the low-pass filter
and (sinx)/x filter clock (see Figure 1-1 and Table 1-1).

fj
Frame Sync

The analog input frequency of interest
The falling edge of the signal that initiates the data-transfer interval. The primary
frame sync starts the primary communications, and the secondary frame sync starts
the secondary communications.

Frame Sync and
Sampling Period

The time between falling edges of successive primary frame-sync signals

Frame-Sync Interval

The time period occupied by 16 shift clocks. Regardless of the mode of operation,
there is always an internal frame-sync interval signal that goes low on the rising
edge of SCLK and remains low for 16 shift clocks. It is used for synchronization of
the serial-port internal signals. It goes high on the seventeenth rising edge of SCLK.

fs
Host

The sampling frequency that is the reciprocal of the sampling period.
Any processing system that interfaces to DIN, DOUT, SCLK, or FS.

Master Mode

The operating mode under which the device generates and uses its own shift clock
and frame-sync signal and generates all delayed frame-sync signals necessary to
support slave devices.
The programmed time variation from the falling edge of one frame-sync signal to the
falling edge of the next frame sync signal. The time variation is determined by the
contents of the A' register. Since the time between falling edges of successive
frame-sync signals is the the sampling period, the sampling period is adjusted.

Phase Adjustment

Primary (Serial)
Communications
Secondary (Serial)
Communications

The digital data-transfer interval. Since the device is synchronous, the signal data
words from the ADC channel and to the DAC channel occur simultaneously.
The digital control and configuration data-transfer interval into DIN and the register
read-data cycle from DOUT. The data-transfer interval occurs when requested by
hardware or software.

Signal Data

The input signal and all of the converted representations through the ADC channel
and return through the DAC channel to the analog output. This is contrasted with
the purely digital software-control data.

Slave Mode

The operating mode under which the device receives shift clock and frame-sync
signals from a master device.

4-201

Stand-Alone Mode

The operating mode under which the device generates and uses its own shift clock
and frame-sync signal. The device has no slave devices.

X

The X represents a don't-care bit position within the control register format.

2.2

Reset and Power-Down Functions

2.2.1

Reset

The TLC320AC01 resets both the internal counters and registers, including the programmed registers, by
any of the following:
•
•
•

Applying power to the device, causing a power-on reset (POR)
Applying a low reset pulse to RESET
Reading in the programmable software reset bit (OS01 in register 6)

PWR OWN resets the counters only and preserves the programmed register contents.

2.2.2

Conditions of Reset

The two internal reset signals used for the reset and synchronization functions are as follows:
1.

Counter reset: This signal resets all flip-flops and latches that are not externally programmed with
the exception of those generating the reset pulse itself. In addition, this signal resets the software
power-down bit.
Counter reset

2.

= power-on reset + RESET + RESET bit + PWR OWN

Register reset: This signal resets all flip-flops and latches that are not reset by the counter reset
except those generating the reset pulse itself.
Register reset = power-on reset + RESET + RESET bit

Both reset signals are at least one master-clock period long and release on the falling edge of the master
clock.

2.2.3

Software and Hardware Power-Down

Given the definitions and conditions of RESET, the software-programmed power-down condition is cleared
by resetting the software bit (OSOO in register 6) to zero. It is also cleared by either cycling the power to the
device, bringing PWR OWN low, or bringing RESET low.
PWR OWN powers down the entire chip ( < 1 mA ). The software-programmable power-down bit only
powers down the analog section of the chip ( < 3 mA ), which allows a software power-up function. Cycling
PWR OWN high to low and back to high resets all flip-flops and latches that are not externally programmed,
thereby preserving the register contents.
When PWR OWN is not used, it should be tied high.

2.2.4

Register Default Values After POR, Software Reset, or RESET Is Applied

Register 1 - The A Register
The default value of the A-register data is decimal 18 as shown below.

4-202

Register 2 - The B Register
The default value of the B-register data is decimal 18 as shown below.

Register 3 - The A' Register
The default value of the A'-register data is decimal 0 as shown below.

Register 4 - The Amplifier Gain-Select Register
The default value of the amplifier gain-select register data is shown below.

Register 5 - The Analog Control-Configuration Register
The power-up and reset conditions are as shown below. In the read mode, 8 bits are read but the 4 LSBs
are repeated as the 4 MSBs.

Register 6 - The Digital Configuration Register
The default value of DS07 - DSOO is 0 as shown below.

Register 7 - The Frame-Sync Delay Register
The default value of DS07 - OSOO is 0 as shown below.

Register 8 - The Frame-Sync Number Register
The default value of OS07 - OSOO is 1 as shown below.

4-203

2.3

Master-Slave Terminal Function

Table 2-1 describes the function of the masterlslave (MiS) input. The only difference between master and
slave operations in the TLC320AC01 is that SCLK and FS are outputs when MIS is high and inputs when
MIS is low.

Table 2-1. Master-Slave Selection

MIst

FS

SCLK

Master and Stand Alone

H

Output

Output

Slave and Codee Emulation

L

Input

Input

MODE

t

2.4

When the stand-alone mode is desired or when the device is
permanently in the master mode, Mis must be high.

ADC Signal Channel

To produce excellent common-mode rejection of unwanted signals, the analog signal is processed
differentially until it is converted to digital data. The signal is amplified by the input amplifier at one of three
software-selectable gains (typically 0 dB, 6 dB, or 12 dB). A squelch mode can also be programmed for the
input amplifier.
The amplifier output is filtered and applied to the ADC input. The ADC converts the signal into discrete digital
words in 2s-complement format corresponding to the analog-signal value at the sampling time. These 16-bit
digital words, representing sampled values of the analog input signal, are clocked out of the serial port
(DOUT), one word for each primary communication interval. During secondary communications, the data
previously programmed into the registers can be read out with the appropriate register address and with the
read bit set to 1. When a register read is not requested, all 16 bits are o.

2.5

DAC Signal Channel

DIN receives the 16-bit serial data word (2s complement) from the host during the primary communications
interval and latches the data on the seventeenth rising edge of SCLK. The data are converted to an analog
voltage by the DAC with a sample and hold and then through a (sin x)/x correction circuit and a smoothing
filter. An output buffer with three software-programmable gains (0 dB, -6 dB, and -12 dB), as shown in
register 4, drives the differential outputs OUT + and OUT -. A squelch mode can also be programmed for
the output buffer. During secondary communications, the configuration program data are read into the
device control registers.

2.6

Serial Interface

The digital serial interface consists of the shift clock, the frame-synchronization signal, the ADC-channel
data output, and the DAC-channel data input. During the primary 16-bit frame-synchronization interval, the
SCLK transfers the ADC channel results from DOUT and transfers 16-bit DAC data into DIN.
During the secondary frame-synchronization interval, the SCLK transfers the register read data from DOUT
when the read bit is set to a 1. In addition, the SCLK transfers control and device parameter information into
DIN. The functional sequence is shown in Figure 2-1.

4-204

1"-- [(8 register)/2] FCLK Periodst
I
1'- Frame-Sync Interval -+1

SCLK

I

~ Frame-Sync

Interval -+1

hlin:~~AA
I
I
1..-- 16 SCLKs

FS

~I

1

I
I
~I

I
I
I..

(/) I

I
I
16 SCLKs ---.1

()r--r

(/) I

I

DOIIT

Ro,",., ....

I
I

DIN

t

I

I

DAC,"PWD~ >

-!(

~

Dataw

I

~Coo"'md~re~~

The time between the primary and secondary frame sync is the time equal to filter clock (FCLK) period multiplied by the
B-register contents divided by two. The time interval is rounded to the nearest shift clock. The secondary frame-sync
signal goes from high to Iowan the next shift clock low-to-high transition after (B register/2) filter clock periods.

Figure 2-1. Functional Sequence for Primary and Secondary Communication

2.7

Number of Slaves

The maximum number of slaves is determined by the sum of the individual device delays from the
frame-sync (FS) input low to the frame-sync delayed (FSD) low for all slaves according to equation 1 :

(1 )

(n) 1 tp(FS-FSD) < 1/2 shift-clock period
Where:
n is the number of slave devices.
Example:
From equation 1 above, the number of slaves is given by equation 2:
(n)

~ ~

x (SCLK period) x tp(FS

~

(2)

FSD)

assuming the master clock is 10.368 MHz and the shift clock is 2.5965 MHz and tp(FS - FSD) is 40 ns, then
according to equation 3, the number of slaves is:
n

1

1

1

1000

~ 2.5965 MHz x :2 x 40 ns = 192

=

4.8

(3)

The maximum number of slaves under these conditions is four.

4-205

2.8

Required Minimum Number of MCLK Periods

Master with slave operation is summarized in the following sections.

2.8.1

TLC320AC01 AIC Master-Slave Summary

After initial setup and the master and slave frame syncs are separated, when secondary communication is
needed for a slave device, a 11 must be placed in the 2 LSBs of each primary data word for all devices in
the system, master and slave, by the host processor. In other words, all AICs must receive secondary frame
requests.
The host processor must issue the command by setting D01 and DOD to a 1 in the primary frame sync data
word of all devices. Then the master generates the master primary frame sync and, after the number of shift
clocks set by the FSD register value, the slave primary frame sync intervals. Then, after (B register value/2)
FCLK periods, the master secondary frame sync occurs first, and then the slave secondary frame sync
occurs. These are also rippled through the slave devices.
In other words, when a secondary communications interval is requested by the host processor as described
above:
1.

The master outputs the master primary frame sync interval, and then the slave primary frame
sync intervals after the FSD register value number of shift clocks.

2.

After (B register value/2) FCLK periods, the master then outputs the master secondary frame
sync interval, and after the FSD register value number of shift clocks, the slave secondary frame
sync intervals.

This sequence is shown in Figure 2-2.
The host must keep track of whether the master or a slave is then being addressed and also the number
of slave devices. The master always outputs a 00 in the last 2 bits of the DOUT word, and a slave always
outputs a 1 in the LSB of the DOUT word. This information allows the system to recognize a starting point
by interrogating the least significant bit of the DOUT word. If the LSB is 0, then that device is the master,
and the system is at the starting point.
Note: This identification always happens except in 16-bit mode when the 2 LSBs are not available
for identification purposes.

10IIII10lIl1-------------...+1- (8 Register Value/2) FCLK Periods
1

I

10lIl

Sampling Period

FSD Value 1
I
in SCLKs~r--I----~·i
1

I

Frame Sync
Sequence
Period Symbol

MP

SP1

SP2

SPn

MS

SS1

SS2

SSn

Periods shown: Each period must be a minimum of 16 SCLKs plus 2 additional SCLKs
MP
SP1
SP2
SPn

= Master Primary Period
= 1st Slave Primary Period
= 2nd Slave Primary Period
= nth Slave Primary Period

MS
SS1
SS2
SSn

= Master Secondary Period
= 1st Slave Secondary Period
= 2nd Slave Secondary Period
= nth Slave Secondary Period

Figure 2-2. Timing Sequence
4-206

MP

2.8.2

Notes on TLC320AC01/02 AIC Master-Slave Operation

Master/slave operational detail is summarized in the following notes:
1.

The slave devices can be programmed independently of the master as long as the clock divide
register numbers are not changed. The gain settings, for example, can be changed
independently.

2.

The method that is used to program a· slave independently is to request a secondary
communication of the master and all slaves and ripple the delayed frame sync to the desired slave
device to be programmed.

3.

Secondary frame syncs must be requested for all devices in the system or none. This is required
so that the master generates secondary frames for the slaves and allows the slaves to know that
the second frame syncs they receive are secondary frame syncs. Each device in the system must
receive a secondary frame request in its corresponding primary frame sync period (11 in the last
2 LSBs).

4.

Calculation of the sampling frequency in terms of the master clock and the shift clock and the
respective register ratios is (see equations 4-6):
Sampling frequency = fs = B

~~LK I
regis er va ue

f(MCLK)
2 (A register value) x (B register value)

(4)

Therefore,

f(M~LK)
s

=

2 x (A register value) x (B register value)

(5)

and in terms of the shift clock frequency, since
f(MCLK) = 4 x f(SCLK)
then
f(SCLK)

(A register value) x (B register value)

fs

2
Number of SCLK periods
Sampling period

5.

(6)

The minimum number of shift clocks between falling edges of any two frame syncs is 18 because
the frame sync delay register minimum number is 18.
When a secondary communication is requested by the host, the master secondary frame sync
begins at the middle of the sampling period (followed by the slave secondary frame syncs), so all
primary frame sync intervals (master and slave) must occur within one-half the sampling time.

4-207

The first secondary frame-sync falling edge, therefore, occurs at the following time (see
equation 7):
.
.
B register value
.
2
(FCLK periods) =
Time to first secondary frame sync =
A register value x B register value (number of MCLK periods) =
A register value x B register value
4
(number of SCLK periods)
6.

(7)

Number of frame sync intervals using equation 8.
All master and slave primary frame sync intervals must occur within the time of equation 7.
Since 18 shift clocks are required for each frame sync interval, then the number of frame sync
intervals from equation 8 is:
.
A register value x B register value
Number of frame sync Intervals = 4 x 18 (SCLKs /f rame sync .Int ervaI)
A register value x B register value

72
7.

(8;

Number of devices, master and slave, in terms of f(MCLK) and f8 .
Substituting the value from equation 5 for the A x B register value product gives the total number
of devices, including the master and all slaves that can be used, for a given master clock and
sampling frequency. Therefore, using equation 9:
.
Number of devices

8.

=

f(MCLK)
144 x fs

(9)

Number of devices, master and slave, if slave devices are reprogrammed.
Equation 9 does not include reprogramming the slave devices after the frame sync delay occurs.
So if programming is required after shifting the slave frame syncs by the FSD register, then the
total number of devices is given by equation 10 is:
.
Number of devices

9.

=

f(MCLK)
288 x f s

Example of the maximum number of devices if the slave devices are reprogrammed assuming
the following values:

f(MCLK) = 10.368 MHz, f8 = 8 kHz
then from equation 10,
Maximum number of devices = 10.368 MHz = 4 5
288 (8 kHz)
.
therefore, one master and three slaves can be used.

4-208

(10)

2.9

Operating Frequencies

2.9.1

Master and Stand-Alone Operating Frequencies

The sampling (conversion) frequency is derived from the master-clock (MCLK) input by equation 11:
fs = Sampling (conversion) frequency = (A regis
. ter vaIue
) xM~~Kregis
. t er vaIue
) x 2 (11)
The inverse is the time between the falling edges of two successive primary frame-synchronization signals.
The input and output data clock (SCLK) frequency is given in equation 12:
SCLK frequency = MCLK frequency
4

2.9.2

(12)

Slave and Codec Operating Frequencies

The slave operating frequencies are either the default values or programmed by the control data word from
the master and codec conversion and the data frequencies are determined by the externally applied SCLK
and FS signals.

2.10 Switched-Capacitor Filter Frequency (FCLK)
The filter clock (FCLK) is an internal clock signal that determines the filter band-pass frequency and is the
B counter clock. The frequency of the filter clock is derived by equation 13:
FCLK =

MCLK
(A register value) x 2

(13)

2.11 Filter Bandwidths
The low-pass (LP) filter -3 dB corner is derived in equation 14:
f (LP)

=

FCLK
40

=

MCLK
40 x (A register value) x 2

(14)

The high-pass (HP) filter -3 dB corner is derived in equation 15:
f (HP) = Sampling frequency =
MCLK
200
200 x 2 x (A register value) x (B register value)

(15)

2.12 Master and Stand-Alone Modes
The difference between the master and stand~alone modes is that in the stand-alone mode there are no
slave devices. Functionally these two modes are the same. In both, the AIC internally generates the shift
clock and frame-sync signal for the serial communications. These signals and the filter clock (FCLK) are
derived from the input master clock.The master clock applied at the MCLK input determines the internal
device timing. The shift clock frequency is a divide-by-four of the master clock frequency and shifts both the
input and output data at DIN and DOUT, respectively, during the frame-sync interval (16 shift clocks long).
To begin the communication sequence, the device is reset (see Section 2.2.1), and the first frame sync
occurs approximately 648 master clocks after the reset condition disappears.

2.12.1

Register Programming

All register programming occurs during secondary communications, and data is latched and valid on the
sixteenth falling edge of SCLK. After a reset condition, eight primary and secondary communications cycles
are required to set up the eight programmable registers. Registers 1 through 8 are programmed in
secondary communications intervals 1 through 8, respectively. If the default value for a particular register
is desired, that register does not need to be addressed during the secondary communications. The no-op
command addresses the pseudo-register (register 0), and no register programming takes place during this
communications. The no-op command allows phase shifts of the sampling period without reprogramming
any register.
During the eight register programming cycles, DOUT is in the high-impedance state. DOUT is released on
the rising edge of the eighth primary internal frame-sync interval. In addition, each register can be read back

4-209

during DOUT secondary communications by setting the read bit to 1 in the appropriate,register. Since the
register is in the read mode, no data can be written to the register during this cycle. To return this register
to the write mode requires a subsequent secondary communication (see Section 2.19 for detailed register
description).

2.12.2

Master and Stand-Alone Functional Sequence

The A counter counts according to the contents of the A register, and the A counter frequency is divided by
two to produce the filter clock (FCLK). The B counter is clocked by FCLK with the following functional
sequence:
1.

The B counter starts counting down from the B register value minus one. Each count remains in
the counter for one FCLK period including the zero count. This total counter time is referred to
as the B cycle. The end of the zero count is called the end of B cycle.

2.

When the B counter gets to a count of nine, the analog-to-digital (A-to-D) conversion starts.

3.

The A-to-D conversion is complete ten FCLK periods later.

4.

FS goes low on a rising edge of SCLK after the A-to-D conversion is complete. That rising edge
of SCLK must be preceded by a falling edge of SCLK, which is the first falling edge to occur after
the end of B cycle.

5.

The D-to-A conversion cycle begins on the rising edge of the internal frame-sync interval and is
complete ten FCLK periods later.

2.13 Slave and Codec Modes
The only difference between the slave and codec modes is that the codec mode is controlled directly by the
host and does not use a delayed frame-sync signal. In both modes, the shift clock and the frame sync are
both externally generated and must be synchronous with MCLK. The conversion frequency is set by the time
interval of externally applied frame-sync falling edges except when the free-run function is selected by bit 5
of register 6 (see Section 2.15.4). The slave device or devices share the shift clock generated by the master
device but receive the frame sync from the previous slave in the chain. The Nth slave FS receives the
(N -1 )st slave FSD output and so on. The first slave device in the chain receives FSD from the master.

4-210

2.13.1

Slave and Codec Functional Sequence

The A counter counts according to the contents of the A register, and the A counter frequency is divided by
two to produce the FCLK. The device function in the slave or codec mode is the same as steps 1 through
3 of the B cycle description in the master mode but differs as follows:
1.

Same as master

2.

Same as master

3.

Same as master

4.

All internal clocks stop 1/2 FCLK before the end of count 0 in the B counter cycle.

5.

All internal clocks are restarted on the first rising edge of MCLK after the external FS input goes
low. This operation provides the synchronization necessary when using an external FS signal.

6.

The D-to-A conversion starts on the rising edge of the internally generated frame-sync interval
at the end of the 16-shift clock data transfer.

In the slave mode, the master controls the phase adjustments for itself and all slaves since all devices are
programmed in the same frame-sync interval. In the codec mode, the shift clock and frame sync are
externally generated and provide the timing for the ADC and DAC if the free-run function has not been
selected (see Subsection 2.15.4). In the codec mode, there is usually no need for phase adjustments;
however, any required phase adjustments must be made by adjusting the external frame-sync timing
(sampling time).

2.13.2

Slave Register Programming

When slave devices are used on power-up or reset, all slave frame-sync signals occur at the same time as
the master frame-sync signal and all slave devices are programmed during the master secondary framesync interval with the same data as the master. The last register programmed must be the frame-sync delay
(FSD) register because the delay starts immediately on the rising edge of the seventeenth shift clock of that
frame- sync interval. After the FSD register programming is completed for the master and slave, the slave
primary frame interval is shifted in time (time slot allocated) according to the data contained in the slave FSD
registers. The master then generates frame-sync intervals for itself and each slave to synchronize the host
serial port for data transfers for itself and all slave devices.
The number of slaves is specified in the FSN register (register 8); therefore, the number of frame-sync
intervals generated by the master is equal to the number of slaves plus one (see Section 2.7). These master
frame-sync intervals are separated in time by the delay time specified by the FSD register (register 7). These
master-generated intervals are the only frame-sync interval signals applied to the host serial port to provide
the data-transfer time slot for the slave devices.

2.14 Terminal Functions
2.14.1

Frame-Sync Function

The frame-sync signal indicates that the device is ready to send and receive data for both master and slave
modes. The data transfer begins on the falling edge of the frame-sync signal.

2.14.1.1 Frame Sync (FS), Master Mode
The frame sync is generated internally. FS goes low on the rising edge of SCLK and remains low for the
16-bit data transfer. In addition to generating its own frame-sync interval, the master also outputs a frame
sync for each slave that is being used.

4-211

2.14.1.2 Frame-Sync Delayed (FSD), Master Mode
For the master, the frame-sync delayed output occurs 1/2 shift-clock period ahead of FS to compensate for
the time delay through the master and slave devices. The timing relationships are as follows:
1.

When the FSD register data is 0, then FSD goes low on the falling edge of SCLK prior to the rising
edge of SCLK when FS goes low (see Figure 4-4).

2.

When the FSD register data is greater than 17, then FSD goes low on a rising edge of SCLK that
is the FSD register number of SCLKs after the falling edge of FS.

Register data values from 1 to 17 should not be used.

2.14.1.3 Frame Sync (FS), Slave Mode
The frame-sync timing is generated externally, applied to FS, and controls the ADC and DAC timing (see
Subsection 2.15.4). The external frame-sync width must be a minimum of one shift clock to be recognized
and can remain low until the next data frame is required.

2.14.1.4 Frame-Sync Delayed (FSD), Slave Mode
This output is fed from the master to the first slave and the first slave FSD output to the second and so on
down the chain. The FSD timing sequence in the slave mode is as follows:
1.

When the FSD register data is 0, then FSD goes low after FS goes low (see Figure 4-5).

2.

When the FSD register data is greater than 17, FSD goes low on a rising edge of SCLK that is
the FSD register number of SCLKs after the falling edge of FS.

Data values from 1 to 17 should not be used.

2.14.2

Data Out (DOUT)

DOUT is placed in the high-impedance state on the seventeenth rising edge of SCLK (internal or external)
after the falling edge of frame sync. In the primary communication, the data word is the ADC conversion
result. In the secondary communication, the data is the register read results when requested by the
read/write (R/W) bit with the eight MSBs set to 0 (see Section 2.16). If no register read is requested, the
secondary word is all zeroes.

2.14.2.1 Data Out, Master Mode
In the master mode, DOUT is taken from the high-impedance state by the falling edge of frame sync. The
most significant data bit then appears on DOUT.

2.14.2.2 Data Out, Slave Mode
In the slave mode, DOUT is taken from the high-impedance state by the falling edge of the external frame
sync or the rising edge of the external SCLK, whichever occurs first (see Figure 4-7). The falling edge of
frame sync can occur ±1/4 SCLK period around the SCLK rising edge (see Figure 4-3). The most
significant data bit then appears on DOUT.

2.14.3

Data In (DIN)

In the primary communication, the data word is the digital input signal to the DAC channel. In the secondary
communication, the data is the control and configuration data to set up the device for a particular function
(see Section 2.16).

2.14.4

Hardware Program Terminals (FC1 and FCO)

These inputs provide for hardware programming requests for secondary communication or phase
adjustment. These inputs work in conjunction with the control bits 001 and 000 of the primary data word
or control bits DS15 and DS14 of the secondary data word. The data onFC1 and FCO are latched on the
rising edge of the next internally generated primary or secondary frame-sync interval. These inputs should
be tied low if not used (see Section 2.17 and Table 2-3).
4-212

2.14.5

Midpoint Voltages (ADC VMID and DAC VMID)

Since the device operates at a s'ingle-supply voltage, two midpoint voltages are generated for internal signal
processing. ADC VMID is used for the ADC channel reference, and DAC VMID is used for the DAC channel
reference. Two references minimize channel-to-channel noise and crosstalk. ADC VMID and DAC VMID
must be buffered when used as a reference for external signal processing.

2.15 Device Functions
2.15.1

Phase Adjustment

In some applications, such as modems, the device sampling period may require an adjustment to
synchronize with the incoming bit stream to improve the signal-to-noise ratio. The TLC320AC01 can adjust
the sampling period through the use of the A' register and the control bits.

2.15.1.1 Phase-Adjustment Control
A phase adjustment is a programmed variation in the sampling period. A sampling period is adjusted
according to the data value in the A' register, and the phase adjustment is that number of master clocks
(MCLK). An adjustment is made during device operation with data bits D01 and DOO in the primary
communication, with data bits DS15 and DS14 in the secondary word or in combination with the hardware
terminals FC1 and FCO (see Table 2-3). This adjustment request is latched on the rising edge of the next
internal frame-sync interval and is only valid for the next sampling period. To repeat the phase adjustment,
another phase request must be initiated.

2.15.1.2 Use of the A' Register for Phase Adjustment
The A' register value makes slight timing adjustments to the sampling period. The sampling period
increases or decreases according to the sign of the programmed A' register value and the state of data bits
D01 and DOO in the primary data word.
The general equation for the conversion frequency is given in equation 16:
MCLK
(16)
f = conversion frequency =
s
(2 x A register value x B register value) ± (A' register value)
Therefore, if A' = 0, the device conversion (sampling) frequency and period is constant.
If a nonzero A' value is programmed, the sampling frequency and period responds as shown in Table 2-2.

Table 2-2. Sampling Variation With A'
SIGN OF THE A' REGISTER VALUE

001

000

PLUS VALUE
(+)

NEGATIVE VALUE

0

1
(increase command)

Frequency decreases,
period increases

Frequency increases,
period decreases

0

Frequency increases,
period decreases

Frequency decreases,
period increases

1

(decrease command)

H

An adjustment to the sampling period, which must be requested through D01 and DOO of the primary data
word to DIN, is valid for the following sampling period only. When the adjustment is required for the
subsequent sampling period, it must be requested again through D01 and DOO of the primary data word.
For each request, only the sampling period occurring immediately after the primary data word request is
affected.

4-213

The amount of time shift in the entire sampling period (1/fs) is as follows:
When the sampling period is set to 125 ~s (8 kHz), the A' register is loaded with decimal 10 and the
TLC320AC01 master clock frequency is 10.386 MHz. The amount of time each sampling period is increased
or decreased, when requested, is given in equation 17:
Time shift = (A' register value) x (MCLK period)

(17)

The device changes the entire sampling period by only the MCLK period times the A' register value as given
in equation 18:
Change in sampling period = contents of A' register x master clock period
= 10 x 96.45 ns = 964 ns (less than 1% of the sampling period)

(18)

The sampling period changes by 964.5 ns each time the phase adjustment is requested by the primary data
word (i.e., once per sampling period).
It is evident then that the change in sampling period is very small compared to the sampling period. To
observe this effect over a long period of time (> sampling period), this change must be continuously
requested by the primary data word. If the adjustment is not requested again, the sampling period changes
only once and it may appear that there was no execution of the command. This is especially true when bench
testing the device. Automatic test equipment can test for results within a single sampling period.
Internally, the A' register value only affects one cycle (period) of the A counter. The A and A' values are
additive, but only for one A-counter period. The A counter begins the first count at the default or programmed
A-register value and counts down to the A'-register value. As the A' value increases or decreases, the first
clock cycle from the A counter is lengthened or shortened. The initial A-counter period is the only counter
period affected by the A' register such that only this single period is increased or decreased.

2.15.2

Analog Loopback

This function allows the circuit to be tested remotely. In loopback, OUT+ and OUT-are internally connected
to IN+ and IN-. The DAC data bits D15 to D02 that are applied to DIN can be compared with the ADC output
data bits D15 to D02 at DOUT. There are some differences due to the ADC and DAC channel offset. The
loopback function is implemented by setting DS01 and DSOO to zero in control register 5 (see Section 2.19).
When analog loopback is enabled, the external inputs to IN+ and IN- are disconnected, but the signals at
OUT+ and OUT- may still be read.

2.15.3

16-Bit Mode

In the 16-bit mode, the device ignores the last two control bits (D01 and 000) of the primary word and
requests continual secondary communications to occur. By ignoring the last two primary communication
bits, compatibility with existing 16-bit software can be maintained. This function is implemented by setting
bit OS03 to 1 in register 6. To return to normal operation, OS03 must be reprogrammed to o.

2.15.4

Free-Run Mode

With the free-run bit set in register 6, the external shift clock and frame sync control only the data transfer.
The ADC and DAC timing are controlled by the A and B register values, and the phase-shift adjustment must
be done as if the device is in stand-alone mode (by the software or the state of FC1 and FCO).
Phase adjustment cannot be made by adjustment of the frame-sync timing. The external frame sync must
occur within 112 FCLK period of the internal frame sync (FCLK as determined by the values of the A and
B registers).
When the external frame sync occurs simultaneously with the internal load, the data-transfer request by the
external frame sync takes precedence over an internal load command. The latching of the AOC conversion
data in the output register is inhibited until the current 16 bits are shifted out of the register by the shift clock.

2.15.5

Force Secondary Communication

With bit 2 in register 6 set to 1, secondary communication is requested continuously. It overrides all software
and hardware requests concerning secondary communication. Phase shifting, however, can still be
performed with the software and hardware.
4-214

2.15.6

Enable Analog Input Summing

By setting bits OS01 and OSOO to 11 in register 5, the normal analog input voltage is summed with the
auxiliary input voltage. The gain for the analog input amplifier is set by data bits OS03 and OS02 in register 4.

2.15.7

DAC Channel (sin x)/x Error Correction

The (sin x)/x compensation filter is designed for zero (sin x)/x error using a B-register value of 15. Since the
filter cannot be removed from the signal path, operation using another B-register value results in an error
in the reconstructed analog output. The error is given by equation 19. Any error compensation needed by
a given application can be performed in the software.
sin (2JtXAXB x f)
f MCLK

OAC channel frequency response error = 20

x

log 10

- - - - - - - - x .!§.
sin

(30JtXA x f)
f MCLK

(19)

B

where:
= the frequency of interest

fMCLK
A
B

=the TLC320AC01

master-clock frequency

= the A-register value

=the B-register value

and the arguments of the sin functions are in radians.

2.16 Serial Communications
2.16.1 Stand-Alone and Master-Mode Word Sequence and Information Content During
Primary and Secondary Communications
For the stand-alone and master modes, the sequence in Figure 2-2 shows the relationship between the
primary and secondary communications interval, the data content into OIN, and the data content from
OOUT.
The TLC320AC01 can provide a phase-shift command or the next secondary communications interval by
decoding 1) the programmed state of the FC1 and FCO inputs and the 001 and 000 d,ata bits in the primary
data word, or 2) the state of the FC1 and FCO inputs and the OS15 and OS14 data bits in the secondary
data word (see Table 2-3). When OS13 (the RlW bit) is the default value of 0, all 16 bits from OOUT are
o during secondary communication. However, when the RIW bit is set to 1 in the secondary communication
control word, the secondary transmission from OOUT still contains Os in the eight MSBs. The lower order
8 bits contain the data of the register currently being addressed. This function provides register status
information for the host.

4-215

4f---- [ (B register)/2] FCLK Periodst - - -••

1:...

1

I

I
Primary Frame Sync
(16 SCLKs long)

Secondary Frame Sync
(16 SCLKs long)

2s-Complement ADC Output
(14 bits plus 00 for the two LSBs)

16 Bits All Os, Except When in
Read Mode (then least significant
8 bits are register data)

Input Data for the Internal Registers
2s-Complement Input for the DAC
Channel (14 bits plus two
(16 bits containing control,
' - - - - - - . . 1 address, and data information)
function bits). If the 2 LSBs Are
Set to 1, Secondary Frame Sync Is I
Generated by the TLC320AC01
I

t The time between the primary and secondary frame sync is the time equal to filter clock (FCLK) period multiplied by the
B-register contents divided by two. The time interval is rounded to the nearest shift clock. The secondary frame-sync
signal goes from high to low on the next shift clock low-to-high transition after (B register/2) filter clock periods.

Figure 2-3. Master and Stand-Alone Functional Sequence
2.16.2 Slave and Codec-Mode Word Sequence and Information Content During
Primary and Secondary Communications
For the slave and codec modes, the sequence is basically the same as the stand-alone and master modes
with the exception that the frame sync and the shift clock are generated and controlled externally as shown
in Figure 2-3. For the codec mode, the frame-sync pulse width needs to be a minimum of one shift clock
long. The timing relationship between the frame sync and shift clock is shown in the timing diagrams. Phase
shifting is usually not required in the slave or codec mode because the frame-sync timing can be adjusted
externally if required.

-+1

I+-

1 SCLK Minimum

Fill _i_i_f_t_J_J
Primary Frame Sync

~

~ 1 SCLK Minimum

L1_1_J_J_J_J_J
Secondary Frame Sync

2s-Complement ADC Output
16 Bits, All Os, Except When in
(14 bits plus 00 for the 2 LSBs in ' - - - - - -.... Read Mode (then least significant
8 bits are register data)
master and stand-alone mode and
01 in slave mode)

DOUT

Input Data for the Internal
2s-Complement Input for the DAC
'--_ _ _ _.... Registers (16 bits containing
Channel (14 bits plus two
I control, address, and data
I function bits)
I information)

I

NOTE A: The time between the primary and secondary frame syncs is determined by the application; however, enough
time must be provided so that the host can execute the required number of software instructions in the time
between the end of the primary data transfer (rising edge of the primary frame-sync interval) and the falling
edge of the secondary frame sync (start of secondary communications).

Figure 2-4. Slave and Codec Functional Sequence

4-216

2.17 Request for Secondary Serial Communication and Phase Shift
The following paragraphs describe a request for secondary serial communication and phase shift using
hardware control inputs FC1 and FCO, primary data bits 001 and 000, and secondary data bits OS15 and
OS14.

2.17.1

Initiating a Request

Combinations of FC1 and FCO input conditions, bits 001 and 000 in the primary serial data word, FC1 and
FCO, and bits OS15 and OS14 in the secondary serial data word can initiate a secondary serial
communication or request a phase shift according to the following rules (see Table 2-3).
1.

Primary word phase shifts can be requested by either the hardware or software when the other
set of signals are 11 or 00. If both hardware and software request phase shifts, the software
request is performed.

2.

Secondary words can be requested by either the software or hardware at the same time that the
other set of signals is requesting a phase shift.

3.

Hardware inputs FC1 and FCO are ignored during the secondary word unless OS15 and OS14
are 11. When OS15 and OS14 are 01 or 10, the corresponding phase shift is performed. When
OS15 and OS14 are 00, no phase shift is performed even when the hardware requests a phase
shift.

2.17.2

Normal Combinations of Control

The normal combinations of control are as follows:
1.

Use 001 and 000 and OS15 and OS14 to request phase shifts and secondary words by holding
FC1 and FCO to 00.

2.

Use FC1 and FCO exclusively to request phase shifts and secondary words by holding 001 and
000 to 00 and OS15 and OS14 to 11.

3.

Use 001 and 000 only to request secondary words and FC1 and FCO to perform phase shifts
once per period by holding OS15 and OS14 to 00.

2.17.3

Additional Control Options

Additional control options are unusual and are rarely needed or used; however, they are as follows:
1.

Use 001 and 000 only to request secondary words and FC1 and FCO to perform phase shifts
twice per period by holding OS 15 and OS 14 to 11 .

2.

Use FC1 and FCO exclusively to request secondary words and 001 and 000 and OS15 and OS14
to perform phase shifts twice per period.

3.

Use FC1 and FCO to perform the phase shift after the primary word and OS15 and OS14 to
perform a phase shift after the secondary word by holding 001 and 000 to 11.

4-217

Table 2-3. Software and Hardware Requests for
Secondary Serial-Communication and Phase-Shift Truth Table
WITHIN PRIMARY
OR SECONDARY
DATA WORD

Primary

Secondary

CONTROL
BITS

HARDWARE
TERMINALS

PHASE·SHIFT
ADJUSTMENT
(see Section 2.15.1)

D01

DOO

FC1

FCO

EARLIER

LATER

0
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

0
0
1
0

0
1
0
0

0
0
0
1

0
0
0
0

1
1
1
1

0
0
1
1

0
1
0
1

0
0
0
0

1
1
1
1

0
0
0
1

1
1
1
1

0
0
0
0

0
0
1
1

1
0
1

1
1
1
1

0
0
0
0

0
0
0
1

1
1
1
1

1
1
1
1

0
0
1
1

0
1
0
1

0
0
1
0

0
1
0
0

1
1
1
1

DS15

DS14

FC1

FCO

EARLIER

LATER

0
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

0
0
0
0

0
0
0
0

0
0
0
0

1
1
1
1

0
·0
1
1

0
1
0
1

0
0
0
0

1
1
1
1

1
1
1
1

0
0
0
0

0
0
1
1

0
1
0
1

1
1
1
1

0
0
0
0

1
1

1
1
1
1

0
0
1
1

0
1
0
1

0
0
1
0

0
1
0
0

1

1

o.

SECONDARY
REQUEST
(see Note 1)

No request can be made for
secondary communication
within the secondary word.

NOTE 1: The 0 state indicates that a secondary communication is not being requested. The 1 state indicates that a
secondary communication is being requested.

2.18 Primary Serial Communications
Primary serial communications transfer the 14-bit DAC input plus two control bits (001 and 000) to DIN of
the TLC320AC01.They simultaneously transfer the 14-bit ADC conversion result from DOUT to the
processor. The 2 LSBs are set to 0 in the ADC result.

4-218

2.18.1

Primary Serial Communications Data Format

\~--------------------------~V~----------------------~/~
14-bit OAC Conversion Result
2s-Complement Formatt

Control Bits

t Since the supply voltage is single ended, the reference for 2s-complement format is AOC VMIO. Voltages above
this reference have a 0 as the MSB, and voltages below this reference have a 1 as the MSB.

During primary serial communications, when D01 and DOO are both high in the DAC data word to DIN, a
subsequent 16 bits of control information is received by the device at DIN during a secondary
serial-communication interval. This secondary serial-communication interval begins at 112 the programmed
conversion time when the B register data value is even or 1/2 the programmed value minus one FCLK when
the B register data value is odd. The time between primary and secondary serial communication is
measured from the falling edge of the primary frame sync to the falling edge of the secondary frame sync
(see Section 2.19 for function and format of control words).

2.18.2

Data Format From DOUT DuringPrimary Serial Communications

V
14-Bit AOC Conversion Result
2s-Complement Format
015 is the Sign Bit

2.19 Secondary Serial Communications
2.19.1

Data Format to DIN During Secondary Serial Communications

There are nine 16-bit configuration and control registers numbered from zero to eight. All register data
contents are represented in 2s-complement format. The general format of the commands during secondary
serial communications is as follows.
OSOO
Control Bits
2 bits

Rm
Bit

Register Address
5 bits

Register Oata Value
8 bits

All control register words are latched in the register and valid on the sixteenth falling edge of SCLK.

2.19.2

Control Data-Bit Function in Secondary Serial Communication

2.19.2.1 DS15 and DS14
In the secondary data word, bits DS15 and DS14 perform the same control function as the primary control
bits D01 and DOO do in the primary data word.
OS1510S14 OS13 OS12 1 OS11 1 OS1O 1 OS091 OS08
Control Bits

RIW

Register Address

OS071 OS061 OS051 OS041 OS031 OS021 OS011 OSOO
Register Oata

Hardware terminals FC1 and FCO are valid inputs when DS15 and DS14 are both high, and they are ignored
for all other conditions.

4-219

2.19.2.2

OS13 (RIW Bit)

Reset and power-up procedures set this bit to a 0, placing the device in the write mode. When this bit is set
to 1, however, the previous data content of the register being addressed is read out to the host from DOUT
as the least significant 8 bits of the 16-bit secondary word. The first 8 bits remain set to O. Reading the data
out is nondestructive, and the contents of the register remain unchanged.
A. Write Mode (D813 = 0)
Data In. The data word to DIN has the following general format in the write mode.
OS1510S_14 OS13 OS121 OS11 1OS1O 1OS091 OS08
Control Bits

OS071 OS061 OS051 OS041 OS031 OS021 OS011 OSOO
Register Oata

Register Address

0

Data Out. The shift clock shifts out all Os as the pattern to the host from DOUT.
OS15 OS14 OS13 OS12 OS11 OS10 OS09 OS08
0

0

0

0

0

0

0

0

OS07 OS06 OS05 OS04 OS03 OS02 OS01 OSOO
0

0

0

0

0

0

0

0

B. Read Mode (D813 = 1)
Data In. The data word to DIN has the following format to allow a register read. Phase shifts can
also be done in the read mode.
.
OS1510S14 OS13 OS121 OS11 1OS1 0 1OS091 OS08 OS071 OS061 OS051 OS041 OS031 OS021 OS011 OSOO
Control Bits

1

Register Address

Ignored

Data Out. The shift clock clocks out the data of the register addressed from DOUT in the read mode in
the 8 L8Bs.
OS15 OS14 OS13 OS12 OS11 OS10
0

0

0

0

0

0

OS09 OS08
0

OS07J OS061 OS051 OS041 OS031 OS021 OS011 OSOO
Register Oata

0

2.20 Internal Register Format
2.20.1

Pseudo-Register 0 (No-Op Address)

This address represents a no-operation command. No register 1/0 operation takes place, so the device can
receive secondary commands for phase adjustment without reprogramming any register. A read of the
no-op is o. The format of the command word is as follows:
OS1510S14 OS13 OS12 OS11 OS10
Control Bits

2.20.2

X

0

0

0

OS09 OS08 OS07 OS06 OS05 OS04 OS03 OS02 OS01 OSOO
0

0

X

X

X

X

X

X

X

X

Register 1 (A Register)

The following command loads D807 (M8B) - D800 into the A register.
OS1510S14 OS13 OS12 OS11 OS10
Control Bits R/W

0

0

0

OS09 OS08 OS071 OS061 OS051 OS041 OS031 OS021 OS011 OSOO
0

1

Register Oata

The data in D807 - D800 determines the division of the master clock to produce the internal FCLK.
FCLK frequency = MCLKI(A register contents x 2)

4-220

The default value of the A-register data is decimal 18 as shown below.
OS07 OS06 OS05 OS04 OS03 OS02 OS01 OSOO
0

2.20.3

0

0

1

0

0

1

0

Register 2 (8 Register)

The following command loads OS07 (MSB) - OSOO into the B register.
OS1510S14 OS13 OS12 OS11 OS10 OS09 OS08 OS071 OS061 OS051 OS041 OS031 OS021 OS01 1OSOO
Control Bits

RIW

0

0

0

1

Register'Data

0

The data in OS07 - OSOO controls the division of FCLK to generate the conversion clock as given in
equation 20:
Conversion frequency

= FCLK/(B register contents)

MCLK
2 x A register contents x B register contents

(20)

The default value of the B-register data is decimal 18 as shown below.
OS07 OS06 OS05 OS04 OS03 OS02 OS01 OSOO
0

2.20.4

0

0

1

0

0

1

0

Register 3 (A' Register)

The following command contains the A'-register address and loads OS07(MSB) - OSOO into the A' register.
OS1510S14 OS13 OS12 OS11 OS10 OS09 OS08 OS071 OS061 OS051 OS041 OS031 OS021 OS011 OSOO
Control Bits

RIW

0

0

0

1

Register Oata

1

The data in OS07 - DSOO is in 2s-complement format and controls the number of master-clock periods that
the sampling time is shifted.
The default value of the A'-register data is 0 as shown below.
OS07
0

OS06 OS05 OS04 OS03 OS02 OS01 OSOO
0

0

0

0

0

0

0

2.20.5

Register 4 (Amplifier Gain-Select Register)

The following command contains the amplifier gain-select register address with selection code for the
monitor output (0805-0804), analog input (0803-0802), and analog output (0801-0800)
programmable gains.
OS1510S14 OS13 OS12 OS11 OS10
Control Bits

RJW

Monitor output gain
Monitor output gain
Monitor output gain
Monitor output gain

0

0

1

OS09 OS08 OS07 OS06 OS05 OS04 OS03 OS02 OS01 OSOO
0

0

X

X

••
••

= squelch
= 0 dB
= -8 dB
= -18 dB

= squelch
= 0 dB
= 6 dB

Analog
Analog
Analog
Analog

input gain
input gain
input gain
input gain

Analog
Analog
Analog
Analog

output gain
output gain
output gain
output gain

*

*
0

*

*

*

*

0
1
0
1

0
1
1

••
••

12 dB

= squelch
= 0 dB .
= -6 dB

0
0
1
1

0
1
0
1

•••
•

12 dB

0
0
1
1

0
1
0
1

The default value of the monitor output gain is squelch, which corresponds to data bits 0805 and 0804 equal
to 00 (binary).
The default value of the analog input gain is 0 dB, which corresponds to data bits 0803 and 0802 equal
to 01 (binary).
The default value of the analog output gain is 0 dB, which corresponds to data bits 0801 and 0800 equal
to 01 (binary).
The default data value is shown below.
OS07 OS06 OS05 OS04 OS03 OS02 OS01 OSOO
0

2.20.6

0

0

0

0

1

1

0

Register 5 (Analog Configuration Register)

The following command loads the analog configuration register with the individual bit functions described

,

~~

OS1510S14 OS13 0812 OS11 OS10
Control Bits

RiW

0

0

1

OS09 OS08 OS07 OS06 OS05 .OS04 OS03 OS02 OS01 OSOO
0

1

Must be set to 0
High-pass filter disabled
High-pass filter enabled
Analog loopback enabled
Enables IN+ and IN- (disables AUXIN+ and AUXIN-)
Enables AUXIN+ and AUXIN- (disables IN+ and IN-)
Enable analog input summing

X

X

X

X

•

*

*

*

*

0

0

0

••

1
0

••
•
•

0

1

1

0

1

1

The default value of the high-pass~filter enable bit is 0, which places the high-pass filter in the signal path.
The default values of 0801 and 0800 are 0 and 1 which enables IN+ and IN-.

4-222

The power-up and reset conditions are as shown below.
OS03
0

OS02 OS01 OSOO
0

1

0

In the read mode, eight bits are read but the 4 L8Bs are repeated as the 4 M8Bs.

2.20.7

Register 6 (Digital Configuration Register)

The following command loads the digital configuration register with the individual bit functions described
below.
OS1510S14 OS13 OS12 OS11 OS10
Control Bits

RiW

0

0

1

OS09 OS08
1

OS07 OS06 OS05 OS04 OS03 OS02 OS01 OSOO

X

0

X

*

••

AOC and OAC conversion free run
Inactive
FSO output disable
Enable

*

*

*

*

*

1
0

••
••
••
1
0

16-Bit mode, ignore primary LSBs
Normal operation

1
0

Force secondary communications
Normal operation
Software reset
(upon reset, this bit is automatically reset to 0)
Inactive reset
Software power:Qown active (automatically reset to 0
after PWR OWN is cycled high to low and back to high)
Power-down function external
(uses PWR OWN)

1
0

•
•

1
0

•
•

1
0

The default value of 0807-0800 is 0 as shown below.
OS07 OS06 OS05 OS04 OS03 OS02 OS01 OSOO
0

2.20.8

0

0

0

0

0

0

0

Register 7 (Frame-Sync Delay Register)

The following command contains the frame-sync delay (F80) register address and loads 0807
(M8B)-0800 into the F80 register. The data byte (0801-0800) determines the number of 8CLKs
between F8 and the delayed frame-sync signal, F80. The minimum data value for this register is
decimal 18.
OS1510S14 OS13 OS12 OS11 OS10 OS09 OS08
Control Bits RIW

0

0

1

1

OS071 OS061DS05j OS041 OS031 OS021DS01j OSOO
Register Oata

1

The default value of 0807 - 0800 is 0 as shown below.
OS07 OS06 OS05 OS04 OS03 OS02 OS01 OSOO
0

0

0

0

0

0

0

0

When using a slave device, register 7 must be the last register programmed.
4-223

2.20.9

Register 8 (Frame-Sync Number Register)

The following command contains the frame-sync number (F8N) register address and loads 0807
(M88)-0800 into the F8N register. The data byte determines the number of frame-sync signals generated
by the TLC320AC01. This number is equal to the number of slaves plus one.
081510814 0813 0812 0811
Control Bits

RJW

0

1

0810 0809 0808 08071 08061 08051 08041 08031 08021 0801 10800
0

0

0

Register Oata

The default value of 0807-0800 is 1 as shown below.
0807 0806 0805 0804 0803 0802 0801 0800
0

4-224

0

0

0

0

0

0

1

3

Specifications

3.1

Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)t
Supply voltage range, DGTL Voo (see Notes 1 and 2) ............... -0.3 V to 6.5 V
Supply voltage range, DAC Voo (see Notes 1 and 2) ................ -0.3 V to 6.5 V
Supply voltage range, ADC Voo (see Notes 1 and 2) ................ -0.3 V to 6.5 V
Differential supply voltage range, DGTL Voo to DAC Voo ............ -0.3 V to 6.5 V
Differential supply voltage range, all positive supply voltages to
ADC GND, DAC GND, DGTL GND, SUBS .................... -0.3 V to 6.5 V
Output voltage range, DOUT ......................... -0.3 V.to DGTL Voo + 0.3 V
Input voltage range, DIN ............................. -0.3 V to DGTL Voo + 0.3 V
Ground voltage range, ADC GND, DAC GND,
DGTL GND, SUBS ............................ -0.3 V to DGTL Voo + 0.3 V
Operating free-air temperature range, TA ............................ O°C to 70°C
Storage temperature range, Tstg ................................. -40°C to 125°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds .............. 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for
extended periods may affect device reliability.

3.2

Recommended Operating Conditions (see Note 2)

VDD

Positive supply voltage

MIN

NOM

MAX

4.5

5

5.5

v

0.1

V

Steady-state differential voltage between any two supplies

UNIT

V

V,H

High-level digital input voltage

V,L

Low-level digital input voltage

0.8

V

'0

Load output current from ADC VMID and DAC

100

~

15

MHz

Conversion time for the ADC and DAC channels
fMCLK
V'D(PP)
RL
TA
NOTES:

2.2

10 FCLK periods
10.368

Master-clock frequency
Analog input voltage (differential, peak to peak)

I Differential output load resistance
I Single-ended to buffered DAC VMID voltage load resistance
Operating free-air temperature

V

6
600

Q

300
0

70

°C

1. Voltage values for DGTL VDD are with respect to DGTL GND, voltage values for DAC VDD are with respect
to DAC GND, and voltage values for ADC VDD are with respect to ADC GND. For the subsequent electrical,
operating, and timing specifications, the symbol VDD denotes all positive supplies. DAC GND, ADC GND,
DGTL GND, and SUBS are at 0 V unless otherwise specified.
2. To avoid possible damage to these CMOS devices and associated operating parameters, the sequence
below should be followed when applying power:
(1) Connect SUBS, DGTL GND, ADC GND, and DAC GND to ground.
(2) Connect voltages ADC VDD,and DAC VDD.
(3) Connect voltage DGTL VDD.
(4) Connect the input signals.
When removing power, follow the steps above in reverse order.

4-225

3.3

Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, MCLK = 5.184 MHz, Voo = 5 V, Outputs
Unloaded, Total Device
PARAMETER

TEST CONDITIONS
PWR OWN = 1 and clock signals
present

Supply
current

100

MIN

MAX

UNIT

20

25

rnA

1

2

rnA

PWR OWN = 0 after 500 JlS and
clock signals present
PWR OWN = 1 and clock signals
present

Power
dissipation

Po

TYPt

100

rnW

PWR OWN = 0 after 500 JlS and
clock signals present

5

rnW

Software power down, (bit 000,
register 6 set to 1)

15

20

rnW

AOCVMIO

Midpoint
voltage

No load

AOC VOO/2
-0.1

AOC VOO/2
+0.1

V

OACVMIO

Midpoint
voltage

No load

OAC VOO/2
-'0.1

OAC VOO/2
+0.1

V

3.4

Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, Voo = 5 V, Digital I/O Terminals (DIN, DOUT, EOC,
FCO, FC1, FS, FSD, MCLK, Mis, SCLK)
PARAMETER

VOH

High-level output voltage

TEST CONDITIONS

MIN

TYPt

MAX

2.4

IOH =-1.6 rnA

UNIT
V

VOL

Low-level output voltage

IOL = 1.6 rnA

0.4

V

IIH

High-level input current, any digital input

VI = 2.2 V to OGTLVOO

10

IlL

Low-level input current, any digital input

VI = 0 V to 0.8 V

10

J.tA
J.tA

Ci

Input capacitance

5

pF

Co

Output capacitance

5

pF

t All typical values are at VOO =5 V and TA = 25°C.

3.5
3.5.1

Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, Voo = 5 V, ADC and DAC Channels
AOC Channel Filter Transfer Function, FCLK
PARAMETER

=144 kHz, fs =8 kHz

TEST CONDITIONS

MIN

MAX

-1.8

-0.15

fi = 300 Hz to 3 kHz

-0.15

,0.15

fi = 3.3 kHz

-0.35

0.03

fi = 3.4 kHz

-1

-0.1

-2

fi = 50 Hz
fi = 200 Hz

Gain relative to gain at Ii = 1020 Hz (see Note 3)

=4 kHz

-14

fi<: 4.6 kHz

-32

Ii

UNIT

dB

NOTE 3; The differential analog input signals are sine waves at 6 V peak to peak. The reference g"lin is at 1020 Hz.

4-226

3.5.2

ADC Channel Input, Voo
Noted)

=5 V, Input Amplifier Gain =0 dB (Unless Otherwise

PARAMETER

VI(PP)

Peak-to-peak input voltage (see Note 4)
ADC converter offset error

CMRR

Common-mode rejection ratio atIN+, IN-,
AUX IN+, AUX IN- (see Note 5)

q

Input resistance atIN+, IN-, AUX IN+,
AUX IN-

TEST CONDITIONS

MIN

MAX

Differential

6

Band-pass filter selected

10

UNIT

V

3

DS03, DS02 = 0 in
register 4

Squelch

TYPt

Single-ended

V
30

mV

55

dB

100

kQ

60

dB

t

All typical values are at VDD = 5 V and TA = 25°C.
NOTES: 4. The differential range corresponds to the full-scale digital output.
5. Common-mode rejection ratio is the ratio of the ADC converter offset error with no signal and the ADC
converter offset error with a common-mode nonzero signal applied to either IN + and IN- together or
AUX IN + and AUX IN-together.

3.5.3

ADC Channel Signal-to-Distortion Ratio, Voo
Otherwise Noted)
PARAMETER

ADC channel signal-todistortion ratio
(see Note 6)

TEST CONDITIONS

=5 V, f9 =8 kHz (Unless

AV = OdB

AV =6dB

AV = 12 dB

MIN

MIN

MIN

MAX

MAX

VI = -6 dB to -1 dB

68

-

VI =-12 dB to -6 dB

63

68

-

VI = -18 dB to -12 dB

56

63

68

VI = -24 dB to -18 dB

51

57

63

VI = -30 dB to -24 dB

43

51

57

VI = -36 dB to -30 dB

39

45

51

VI = -42 dB to -36 dB

33

39

45

VI = -48 dB to -42 dB

27

32

39

MAX

UNIT

dB

NOTE 6: The analog-input test signal is a 1020-Hz sine wave with 0 dB = 6 V peak to peak as the reference level for
the analog-input signal.

3.5.4

DAC Channel Filter Transfer Function, FCLK
PARAMETER

=144 kHz, fs =9.6 kHz, Voo =5 V

TEST CONDITIONS

MIN

fi = 200 Hz
Gain relative to gain at fi = 1020 Hz (see Note 7)

MAX

UNIT

0.15

fi < 200 Hz
~0.5

0.15
0.15

fi = 300 Hz to 3 kHz

-0.15

Ii = 3.3 kHz

-0.35

0.03

fi = 3.4 kHz

-1

-0.1

fi = 4 kHz

-14

Ii;::: 4.6 kHz

-32

dB

NOTE 7: The input signal is the digital equivalent 01 a 1020-Hz sine wave (digital full scale = 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak.

4-227

3.5.5

DAC Channel Signal-to-Distortion Ratio, Voo= 5 V, fs = 8 kHz (Unless
Otherwise Noted)
PARAMETER

TEST CONDITIONS

DAC channel signal-todistortion ratio
(see Note 8)

Av=O.dB
MIN

MAX

AV=-6dB
MIN

MAX

Av=-12dB
MIN

Va = -6 dB to 0 dB

68

-

Va =-12 dBto-6 dB

63

68

-

Va = -18 dB to -12 dB

57

63

68

Va = -24 dB to -18 dB

51

57

63

Va = -30 dB to -24 dB

45

51

57

Va = -36 dB to -30 dB

39

45

51

Va = -42 dB to -36 dB

33

39

48

Va = -48 dB to -42 dB

27

33

39

MAX

UNIT

dB

NOTE 8: The input signal, VI, is the digital equivalent of a 1020-Hz sine wave (full-scale ;lnalog output at full-scale digital
input = 0 dB). The nominal differential DAC channel output with this input condition is 6 V peak to peak. The
load impedance for the DAC output buffer is 600 Q from OUT + to OUT -.

3.5.6

System Distortion, Voo = 5 V, fs = 8 kHz, FCLK = 144 kHz (Unless Otherwise
Noted)
PARAMETER
Second harmonic

ADC channel
attenuation

TEST CONDITIONS
Single-ended input (see Note 9)
Differential input (see Note 9)

Third harmonic and
higher harmonics

Second harmonic
DAC channel
attenuation

Differential input (see Note 9)

MAX

UNIT

82

77
70

Single-ended output
(buffered DAC VMID)
(see Note 10)

77
82

70

Single-ended output
(see Note 10)
Differential output (see Note 10)

Typt
82

70

Single-ended input (see Note 9)

Differential output (see Note 10)
Third harmonic and
higher harmonics

MIN

dB

82

77
70

77

t All typical values are at VDD = 5 V and TA = 25°C.
NOTES: 9. The input signal is a 1020-Hz sine wave for the ADC channel. Harmonic distortion is defined for an input
level of -1 dB.
.
10. The input signal is the digital equivalent of a 1020-Hz sine wave (digital full scale"; 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the
DAC output buffer is 600 Q from OUT + to OUT -. Harmonic distortion is specified for a signal input level
of 0 dB.
'

4-228

3.5.7

Noise, Low-Pass and Band-Pass Switched-Capacitor Filters Included,

Voo =5 V (Unless Otherwise Noted)
PARAMETER

TEST CONDITIONS
Inputs tied to ADC VMID,
fs = 8 kHz, FCLK = 144 kHz,
(see Note 11)

ADC idle-channel noise
Broad-band noise
DAC idle-channel
noise

MIN

DIN INPUT =00000000000000,
fs = 8 kHz, FCLK = 144 kHz,
(see Note 12)

Noise (0 to 7.2 kHz)
Noise (0 to 3.6 kHz)

TVPt

MAX

180

300

180

300

180

300

180

300

UNIT

~Vrms

t All typical values are at VDD = 5 V and TA = 25°C.
NOTES: 11. The ADC channel noise is calculated by taking the RMS value of the digital output codes of the ADC
channel and converting to microvolts.
12. The DAC channel noise is measured differentially from OUT + to OUT-across 600 Q.

3.5.8

Absolute Gain Error, Voo

=5 V, is =8 kHz (Unless Otherwise Noted)

PARAMETER

TEST CONDITIONS

ADC channel absolute gain error (see Note 13)

-1-dB input signal

DAC channel absolute gain error (see Note 14)

O-dB input signal,
RL= 600 Q

MIN

MAX

UNIT

±0.5

TA = 25°C

±1

TA = 0-70°C

dB

±0.5

TA = 25°C

±1

TA = 0-70°C

NOTES: 13. ADC absolute gain error is the variation in gain from the ideal gain over the specified input signal levels .
The gain is measured with a -1-dB, 1020-Hz sine wave. The -1-dB input signal allows for any positive gain
or offset error that may affect gain measurements at or close to O-dB input signal levels.
14. The DAC input signal is the digital equivalent of a 1020-Hz sine wave (full-scale analog output at digital fullscale input = 0 dB). The nominal differential DAC channel output voltage with this input condition is 6 V peak
to peak. The load impedance for the DAC output buffer is 600 Q from OUT + to OUT -.

3.5.9

Relative Gain and Dynamic Range, Voo
Noted)
.
PARAMETER

=5 V, is =8 kHz (Unless Otherwise

TEST CONDITIONS

MIN

MAX

ADC channel relative gain tracking error
(see Note 15)

-48-dB to -1-dB input signal range

±0.15

DAC channel relative gain tracking error
(see Note 16)

-48-dB to O-dB input signal range
RL(diff) = 600 Q

±0.15

UNIT

dB

NOTES: 15. ADC gain tracking is the ratio of the measured gain at one ADC channel input level to the gain measured
at any other input level. The ADC channel input is a -1-dB 1020-Hz sine wave input Signal. A -1-dB input
signal allows for any positive gain or offset error that may affect gain measurements at or close to O-dBADC
input signal levels.
16. DAC gain tracking is the ratio of the measured gain at one DAC channel digital input level to the gain
measured at any other input level. The DAC-channel input signal is the digital equivalent of a 1020-Hz sine
wave (digital full scale = 0 dB). The nominal differential DAC channel output voltage with this input condition
is 6 V peak to peak. The load impedance for the DAC output buffer is 600 Q from OUT + to OUT -.

4-229

3.5.10

Power-Supply Rejection, Voo

=5 V (Unless Otherwise Noted) (see Note 17)

PARAMETER

TEST CONDITIONS

ADCVDD

Supply-voltage rejection ratio, ADC channel

DACVDD

Supply-voltage rejection ratio,. DAC channel

DGTL VDD

Supply-voltage rejection ratio, ADC channel

DGTL VDD

Supply-voltage rejection ratio, DAC channel

MIN

TYPt

Ii = 0 to 30 kHz

50

Ii = 30 to' 50 kHz

55

Ii = 0 to 30 kHz

40

Ii = 30 to 50 kHz

45

Ii = 0 to 30 kHz

50

fi = 30 to 50 kHz

55

Single ended,
Ii = 0 to 30 kHz

40

Ii = 30 to 50 kHz

45

Differential,
Ii = 0 to 30 kHz

40

Ii = 30 to 50 kHz

45

MAX

UNIT

dB

t

All typical values are at VDD = 5 V and TA = 25°C.
NOTE 17: Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200-mV
peak-to-peak signal applied to the appropriate supply.

3.5.11

Crosstalk Attenuation, Voo
PARAMETER

ADC channel crosstalk attenuation

DAC channel crosstalk attenuation

t

=5 V (Unless Otherwise Noted)
TEST CONDITIONS

MIN

TYPt

DAC channel idle with
DIN = 00000000000000,
ADC input = 0 dB,
1020-Hz sine wave,
Gain = 0 dB (see Note 18)

80

ADC channel idle with INP, INM,
AUX IN +, andAUX IN- at ADC VMID

80

DAC channel input = digital equivalent
of a 1020-Hz sine wave (see Note 19)

80

MAX

UNIT

dB

dB

All typical values are at VDD = 5 V and TA = 25°C.
NOTES: 18. The test signal is a 1020-Hz sine wave with a 0 dB = 6-V peak-to-peak reference level lor the analog input
signal.
19. The input signal is the digital equivalent of a 1020-Hz sine wave (digital lull scale = 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the
DAC output buffer is 600 Q from OUT + to OUT -.

4-230

3.5.12

Monitor Output Characteristics, Voo
(see Note 20)
PARAMETER

=5 V (Unless Otherwise Noted)

TEST CONDITIONS

MIN

TVPt

1.3

1.S

VO(PP)

Peak-to-peak ac output
voltage

Quiescent level = ADC VMID
ZL = 10 kn and 60 pF

VOO

Output offset voltage

No load, single ended
relative to ADC VMID

VOC

Output common-mode voltage

No load

ro

DC output resistance

AV

Voltage gain (see Note 21)

S
O.4ADC
VDO

O.SADC
VDO

MAX

V
10
0.6ADC
VDD

SO

mV
V
Q

Gain = 0 dB

-0.2

0

0.2

Gain 2 =-8 dB

-8.2

-8

-7.8

Gain 3 = -18 dB

-18.4

-18

-17.6

Squelch (see Note 22)

UNIT

dB

-60

t All typical values are at VDD = S V and TA =2SoC.
NOTES: 20. All monitor output tests are performed with a 10-kn load resistance.
21. Monitor gains are measured with a 1020-Hz, 6-V peak-to-peak sine wave applied differentially between
IN + and IN-.The monitor output gains are nominally 0 dB, -8 dB, and -18 dB relative to its input; however,
the output gains are -6dB relative to IN + and IN- or AUX IN + and AUX IN-.
22. Squelch is measured differentially with respect to ADC VMIO~

4-231

3.6

Timing Requirements and Specifications in Master Mode

3.6.1

Recommended Input Timing Requirements for Master Mode, Voo = 5 V
MIN

NOM

MAX

UNIT

tr(MCLK}

Master clock rise time

5

ns

tf(MCLK}

Master clock fall time

5

ns

Master clock duty cycle

40%

tw(RESET)

RESET pulse duration

1 MCLK

tsu(DIN)

DIN setup time before SCLK low (see Figure 4-2)

th(DIN)

DIN hold time after SCLK low (see Figure 4-2)

3.6.2

60%

25

ns
20

ns

Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, Voo = 5 V (Unless Otherwise Noted) (see Note 23)
PARAMETER

MIN

TYPt

MAX

UNIT

tf(SCLK)

Shift clock fall time (see Figure 4-2)

13

18

ns

tr(SCLK)

Shift clock rise time (see Figure 4-2)

13

18

ns

Shift clock duty cycle

45%

55%

td(CH-FL)

Delay time from SCLK high to FSD low
(see Figures 4-2 and 4-4 and Note 24)

5

15

ns

td(CH-FH}

Delay time from SCLK nigh to FS high (see Figure 4-2)

5

20

ns

td(CH-DOUT)

Delay time from SCLK high to DOUT valid
(see Figures 4-2 and 4-7)

20

ns

td(CH-DOUTZ)

Delay time from SCLKt to DOUT in high-impedance state
(see Figure 4-8)

20

ns

td(ML-EU

Delay time from MCLK low to EOC low (see Figure 4-9)

40

ns

td(ML-EH)

Delay time from MCLK low to EOC high (see Figure 4-9)

40

ns

tf(EL)

EOC fall time (see Figure 4-9)

13

ns

tr(EH)

EOC rise time (see Figure 4-9)

13

ns

td(MH-CH}

Delay time from MCLK high to SCLK high

50

ns

td(MH-CL}

Delay time from MCLK high to SCLK low

50

ns

t

All typical values are at VDD = 5 V and TA = 25°C.
NOTES: 23. All timing specifications are valid with CL = 20 pF.
24. FSD occurs 1/2 shift-clock cycle ahead of FS when the device is operating in the master mode.

4-232

3.7

Timing Requirements and Specifications in Slave Mode and Codec
Emulation Mode

3.7.1

Recommended Input Timing Requirements for Slave Mode, Voo
MIN

=5 V

NOM

MAX

UNIT

tr(MCLK)

Master clock rise time

5

ns

tf(MCLK)

Master clock fall time

5

ns

Master clock duty cycle

40%

twlRESET)

RESET pulse duration

1 MCLK

tsu(DIN)

DIN setup time before SCLK low (see Figure 4-3)

ns

20
20

ns

±SCLK/4

ns

DIN hold time after SCLK high (see Figure 4-3)

th{DIN)
tsu(FL-CH)

3.7.2

60%

, Setup time from FS low to SCLK high

Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, Voo = 5 V (Unless Otherwise Noted) (see Note 23)
PARAMETER

tc(SCLK)

Shift clock cycle time (see Figure 4-3)

MIN

TYPt

MAX

125

UNIT
ns

tf(SCLK)

Shift clock fall time (see Figure 4-3)

18

ns

tr(SCLK)

Shift clock rise time (see Figure 4-3)

18

ns

Shift clock duty cycle

45%

55%

td(CH-FDL)

Delay time from SCLK high to FSD low (see Figure 4-6)

50

ns

td(CH-FDH)

Delay time from SCLK high to FSD high

40

ns

td(FL-FDL)

Delay time from FS low to FSD low (slave to slave)
(see Figure 4-5)

40

ns

td(CH-DOUT)

Delay time from SCLK high to DOUT valid
(see Figures 4-3 and 4-7)

40

ns

td(CH-DOUTZ)

Delay time from SCLKi to DOUT in high-impedance state
(see Figure 4-8)

20

ns

Id(ML-EL)

Delay time from MCLK low to EOC low (see Figure 4-9)

40

ns

Id(ML-EH)

Delay time from MCLK low to EOC high (see Figure 4-9)

40

ns
ns

tHEL)

EOC fall time (see Figure 4-9)

13

tr(EH)

EOC rise time (see Figure 4-9)

13

td(MH-CH)

Delay time from MCLK high to SCLK high

50

ns

td(MH-CL)

Delay time from MCLK high to SCLK low

50

ns

ns

t All typical values are at VDD = 5 V and TA = 25°C.
NOTE 23: All timing specifications are valid with CL = 20 pF.

4-233

4-234

4

Parameter Measurement Information
Rfb

R
IN + or AUX IN + - - - ' V ' V V -___---1

}

R
IN-orAUXIN---~VV--

___--~

To MuO;p'ex",

+
Rfb

=
=

=
=

=
=

Rfb R for OS03 0 and OS02 1
Rfb 2R for OS03 1 and OS02 0
Rfb = 4R for OS03 = 1 and OS02 = 1
R = 100 kQ nominal

Figure 4-1. IN+ and IN- Gain-Control Circuitry
Table 4-1. Gain Control (Analog Input Signal Required for
Fu"-Scale Bipolar AID-Conversion 2s Complement)t
INPUT CONFIGURATION

Oifferential configuration
Analog input = IN + - IN= AUX IN+ - AUX IN-

Single·ended configuration§
Analog input = IN + - VMIO
= AUX IN+ - VMIO

CONTROL REGISTER 4
ANALOG INPUT:I:

AID CONVERSION
RESULT

OS03

OS02

0

0

0

1

VID = ±3 V

±Full scale

1

0

VID = ±1.5 V

±Full scale

1

1

VID = ±0.75 V

±Full scale

0

0

All

Squelch

All

Squelch

0

1

VI=±1.5V

±Half scale

1

0

VI=±1.5V

±Full scale

1

1

VI = ±0.75 V

±Full scale

tVOO =5 V
= differential input voltage, VI = input voltage referenced to ADC VMIO with IN- or AUX IN- connected to
AOC VMIO. In order to minimize distortion, it is recommended that the analog input not exceed 0.1 dB below full scale.
§ For single-ended inputs, the analog input voltage should not exceed the supply rails. All single-ended inputs should be
referenced to the internal reference voltage, AOC VMIO, for best common-mode performance.

:I: VIO

4-235

--1 I+-

I+--

tf(SCLK)

SCLK 2V
1

---.:
FSt

tr(SCLK)

1

1

~ td(CH-FL)

~F-------------+--~

OOUT*~

014

__________________________________~~
td(CH-FH)

--J

X

02

01

X

00

01

X

00

>>-

t The time between falling edges of two primary FS signals is the conversion period.

:t: The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling
edge of the shift clock.

Figure 4-2. AIC Stand-Alone and Master-Mode Timing

-1 ~tf(SCLK)

'4----I~II---- tc(SCLK)

14-- tr(SCLK)

1

SCLK

0.8 V

1

1.1

I'lli

FSt

~
II

1

§

1

~~__________~I

-

OOUT*

~

1

!~ ~

014

r

__~I________________________________- J

I

X ~13

X

"'>-

t The time between falling edges of two primary FS signals is the conversion period.

:t: The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling

edge of the shift clock.
§ The high-to-Iow transition of FS must must occur within ±1/4 of a shift-clock period around the 2-V level of the shift clock
for the codec mode.

Figure 4-3. AIC Slave and Codec Emulation Mode

4-236

SCLK

\ 2.4/1

---J/

\~r

I

:~

,..

0.8

SCLK Period/2

~---I:----lil-------­
I I
~

I+- td(CH-FL)

0.8~w;;.1_ _ _ _ _ __
NOTE A: Timing shown is for the TLC320AC01 operating as the master or as a stand-alone device.

Figure 4-4. Master or Stand-Alone FS and FSD Timing

0.8~w;;., _ _ _ _ _ _ _ _ __
~

I

Id(FL-FDL)

0.8~_ _ _ _ _ _ _ __

NOTE A: Timing shown is for the TLC320AC01 operating in the slave mode (FS and SCLK signals are generated
externally). The programmed data value in the FSD register is

o.

Figure 4-5. Slave FS to FSD Timing

SCLK

__
2'...,4/1

--.I :----

0.8

---.l/

~_ _

td(CH-FDL)

------0-.8~~_______________________________________
NOTE A: Timing shown is for the TLC320AC01 operating in the slave mode (FS and SCLK signals are generated
externally). There is a data value in the FSD register greater than 18 (decimal).

Figure 4 - 6. Slave SCLK to FSD Timing

4-237

SCLK

2(V
_ _......,..

HDOUT

\~

\
/
0.8 V\;1Iio _ _--J.
td(CH-DOUT)

X

....;.;H.;..;I-Z;"""_-Cl" 2.4 V

~1Iio._~0.~4~V_ _ _ _ _ _ _~.

2.4 V
~._0.~4_V_ ___

Figure 4-7. DOUT Enable Timing From Hi-Z
SCLK

0.8~

2V;f

~

/

.1
1
0.81

I

DOUT

td(CH-DOUTZ)
Hi-Z

Figure 4-8. DOUT Delay Timing to Hi-Z

I....--I.~II
I

MCLK

__

td(ML-EH)

~;tr--0-.8~>l~~i____--J~~~0~.8.;..;V_________
l

I

I
I

~ tr(EH)

I
I

r 2.4 V

2.4 V

1

I j" 0.4 V

___________.......;;O.;..;..4..;.V..;/I

I

I...

Internal ADC
Conversion Time

Figure 4-9. EOC Frame Timing

4-238

td(ML-EL)

Yfi --~--~(J(~J---~NI .
l

EOC

I
.1

~

---l

J+-

I
.1

tf(EL)

I..
1

.1

Delay Is m Shift Clockst

1

Master
FS
Delay Is m Shift Clockst

I

t4-----tJIf--

Master FSD,
Slave Device 1 FS

I

Delay Is

I

I
I
I

Slave Device 1 FSD,
Slave Device 2 FS
Slave Device 2 FSD,
Slave Device 3 FS

~--------------~LJ

I

I
I
I

i
I

LJ

Slave Device
(n -1) FSD,
Slave Device n FS

t

~ Shift Clockst

The delay time from any FS signals to the corresponding FSD signals is m shift clocks with the value of m being the
numerical value of the data programmed into the FSD register. In the master mode with slaves, the same data word
slave devices; therefore, master to slave 1, slave 1 to slave 2, slave 2 to slave 3, etc., have
programs the master and
the same delay time.

all

Figure 4-10. Master-Slave Frame-Sync Timing After a Delay Has Been
Programmed Into the FSD Registers

Master AIC
Only Primary

Frame Sync
Master AIC
Only Primary
and Secondary
Frame Sync
Master and Slave
AIC Primary
Frame Sync
Master and Slave
AIC Primary and
Secondary

Frame Sync
MP = Master Primary
MS = Master Secondary

SP = Slave Primary
SS = Slave S~condary

Figure 4-11. Master and Slave Frame-Sync Sequence with One Slave

4-239

4-240

5

Typical Characteristics
ADC LOW-PASS RESPONSE
0

"

-10

ID

=

TA 25°C
FCLK 144 kHz

-20

=

't:I

I
C

.S!

1U
:J

-30

C

~

-40

(

-50

-60

~

j,.oo"

II

-

~I
o

1

2

3
4
5
6
7
8
fi - Input Frequency - kHz

9

10

NOTE A : Absolute Frequency (kHz) = Normalized Frequency x FCLK (kHz)
144

Figure 5-1

4-241

ADC LOW-PASS RESPONSE

o.5
o.4

1_1

I

TA = 25°C
FCLK = 144 kHz

o.3
o.2
ID
"CI

I

c

0.1

~

0

i

-0.1

~

~

..... r-......

1,.00"'"

---'

V

,

/ '\

-0.2
-0.3
-0.4
-0.5

o

0.5

1
fj ~

1.5
2
2.5
3
Input Frequency - kHz

3.5

4

NOTE A : Absolute Frequency (kHz) = Normalized Frequency x FCLK (kHz)
144

Figure 5-2

4-242

ADe GROUP DELAY
1

=

25°C
FCLK 144 kHz

TA

o.9
o.8

=

0.7
1/1

0.6

I

0.5

E
CP

E
i=

0.4
0.3

0.2
0.1

~~

o
o

,

J

~

f".... r-;..

2

3

4

5

6

7

8

9

10

fj - Input Frequency - kHz

NOTE A : Absolute Frequency (kHz) = Normalized Frequency x FCLK (kHz)
144

Figure 5-3

4-243

,

ADC BAND-PASS RESPONSE

Or
-1 0

TA = 25°C
fs = 8 kHz
FCLK = 144 kHz

-20

-30
-40

(

-50

-60

o

~

r\ 1/
~I

23456

7

8

fi - Input Frequency - kHz
NOTE A : Absolute Frequency (kHz)

=

Normalized Frequency x FCLK (kHz)
144

Figure 5-4

4-244

ADC BAND-PASS RESPONSE

o.5
o.4

TA = 25°C
fS = 8 kHz
FCLK = 144 kHz

o.3
III
"0
I

c

o
:;

o.2
0.1

0

c
~

-0.1

I

-0.2

-

V

~

~~

J

,

./1\

I

-0.3

-0.4
-0.5

o

0.5

1
fj -

1.5
2
2.5
3
Input Frequency - kHz

3.5

4

NOTE A : Absolute Frequency (kHz) = Normalized Frequency x FCLK (kHz)

144

Figure 5-5

4-245

ADC HIGH-PASS RESPONSE

0

/

-5

III

/

-10

/
I

"D

I
C

o

~c

-15

.!

-

300

/ 1\
1\

-m
Q
~

..

::J
0

200

CJ

100

'/

-

o
o

2

4

/

"

6
8 10 12 14 16
Normalized Frequency

NOTE A: Absolute Frequency (kHz)

=

20

Normalized Frequency x FCLK (kHz)
288

Figure 5-12

4-252

18

CAC (sin x)/x CORRECTION ERROR

2

=

=

1.2

ID

!

~V

V (sin x) Ix Correction

0.8

"'f

/

TA 25°C
Input ± 3-V Sine Wave

1.6

./

0.4

-'
...........

0

c
:1-0.4
::E
-0.8

/

I"""

V

I

Error

~

["-......

"

-1.2

.......

""

19.2-kHz (sin x)
Distortion

"

'\

-1.6

-2

I~

~

\
o

1

2

3

4

5

6

7

8

9

10

Normalized Frequency

NOTE A : Absolute Frequency (kHz)

=

Normalized Frequency x FCLK (kHz)
288

Figure 5-13

4-253

4-254

6

Application Information
TMS320C2x/3x

TLC320AC01
5V

DACVDD
CLKOUT
OX
DR
FSX

14
10
11
12

MCLK

DACVMID

DIN

0.1 IlF

DACGND

DOUT

24
ADCVDD

FS
ADCVMID

FSR
CLKX

13

ADCGND

SCLK

9
DGTL VDD

CLKR

DGTLGND

20

5V
0.1 IlF

NOTE A: Terminal numbers shown are for the FN package.

Figure 6-1. Stand-Alone Mode (to DSP Interface)

TMS320C2x13x

TLC320AC01

14

CLKOUT

MCLK

10
OX
DR
FSX
FSR
CLKX
CLKR

DIN
11
~

12

~
13

~

DOUT
FS

SCLK

NOTE A: Terminal numbers shown are for the FN package.

Figure 6-2. Codec Mode (to DSP Interface)

4-255

TMS320C2x/3x

TLC320AC01
.,14

::.

CLKOUT

.,10

DX

11

DR
FSX
FSR

..

'

W

CLKX

12

-

MCLK
DIN
DOUT
Master Mode

FS
FSD

13

,

SCLK

CLKR ~.
TLC320AC01
.,14
.,10
11

MCLK
DIN
DOUT

~ FS
-

FSD
.,13

...

"

Slave Mode

SCLK

..

NOTE A: Terminal numbers shown are for the FN package.

Figure 6-3. Master With Slave (to DSP Interface)

10kO
10 kQ
IN+
10kQ
10kO
ADCVMID

IN-

tThe VI source must be capable of sinking a current equal to lADe VMID + IVII(max))/10 kl.1.

Figure 6-4. Single-Ended Input (Ground Referenced)

4-256

IN+
10 k.Q

10kO
10 kO
TLE2064
4

IN-

10 k.Q

1 - - - - - - - - ADC VMID
10kO

t

The VI source must be capable of sinking a current equal to [(AOC VMIO/2) + IVII(max)]/1 0 kO.

Figure 6-5. Single-Ended to Differential Input (Ground Referenced)

OUT-

600-0
Load

OUT+

Figure 6-6. Differential Load

10 k.Q
. 10kO
OUT- I---A../'I/'v---ef----I
OUT+I-~VY-----~

10kO

TLE2062

600-0
Load

NOTE A: When a signal changes from a single supply with a nonzero reference system to a
grounded load, the operational amplifier must be powered from plus and minus supplies
or the load must be capacitively coupled.

Figure 6-7. Differential Output Drive (Ground Referenced)

4-257

OUT+~--------~

600-a
Load·

OUT -1--------'--1

Figure 6-8. Low-Impedance Output Drive

100 k.Q
600-a
Load

OUT+
DAC VMID I----'VI/\r--_.f.---i

TLE2062

NOTE A: When a signal changes from a single supply with a nonzero reference system to a
grounded load, the operational amplifier must be powered from plus and minus supplies
or the load must be capacitively coupled.

Figure 6-9. Single-Ended Output Drive (Ground Referenced)

4-258

Appendix A
Primary Control Bits
The function of the primary-word control bits 001 and 000 and the hardware terminals FCO and FC1 are
shown below. Any combinational state of 001, 000, FC1, and FCO not shown is ignored.

CONTROL FUNCTION OF CONTROL BITS
BITS

TERMINALS

001

000

FC1

FCO

0

0

0

0

On the next falling edge of FS, the AIC receives DAC data D15-D02 to DIN and
transmits the ADC data DI5-DOO from DOUT.

0

0

0

1

On the next falling edge of FS, the AIC receives DAC data D15-D02 to DIN and
transmits the ADC data D 15 - DOO from DOUT.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of the next internal FS, the next ADC/DAC sampling time occurs later
by the number of MCLK periods equal to the value contained in the A' register. When
the A' register value is negative, the internal falling edge of FS occurs earlier.

0

0

1

0

On the next falling edge of FS, the AIC receives DAC data D15-D02 at DIN and
transmits the ADC data D15-DOO from DOUT.
The phase adjustment is determined by the state of FCI and FCO such that on the
rising edge of the next internal FS, the next ADC/DAC sample time occurs earlier by
the number of MCLK periods determined by the value contained ~he A' register.
When the A' register value is negative, the internal falling edge of FS occurs later.

0

0

1

1

On the next falling edge of the primary FS, the AIC receives DAC data D15-D02 at
DIN and transmits the ADC data D15-DOO from DOUT.
When FCO and FC1 are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync occurs at 1/2 the
sampling time as measured from the falling edge of the primary FS.

0

1

0

0

On the next falling edge of FS, the AIC receives DAC data D15-D02 to DIN and
transmits the ADC data D15-DOO from DOUT.
The phase adjustment is determined by the state of D01 and DOO such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number.
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, the falling edge of FS occurs earlier.

1

0

0

0

On the next falling edge of FS, the AIC receives DAC data D15-D02 at DIN and
transmits the ADC data DI5-DOO from DOUT.
The phase adjustment is determined by the state of D01 and DOO. On the next rising
edge of FS, the next ADC/DAC sampling time occurs earlier by the number of MCLK
periods determined by the value contained in the A' register. When the A' register
value is negative, the internal falling edge of FS occurs later.

1

1

0

0

On the next falling edge of FS, the AIC receives DAC data D15-D02 to DIN and
transmits the ADC data D 15 - DOO from DOUT.
When DOO and D01 are both high, the AIC initiates a secondary FS to receive a
secondary control word at DIN. The secondary frame sync occurs at 1/2 the sampling
time as measured from the falling edge of the primary FS.

4-259

CONTROL FUNCTION OF CONTROL BITS (Continued)
BITS

TERMINALS

001

000

FC1

FCO

0

1

1

1

.

On the next falling edge of FS, the AIC receives OAC data 015-002 to DIN and
transmits the AOC data 015-000 from DOUT.
The phase adjustment is determined by the state of D01 and DOO such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, FS occurs earlier.
When FCO and FC1 are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync~curs at 1/2 the
sampling time as measured from the falling edge of the primary FS.

1

0

1

1

On the next falling edge of FS, the AIC receives OAC data 015-002 at DIN and
transmits the AOC data 015-000 from OOUT.
The phase adjustment is determined by the state of 001 and 000. On the next rising
edge of FS, the next AOC/OAC sample time occurs earlier by the number of MCLK
periods determined by the value contained in the A' register. When the A' register
value is negative, FS occurs later.
When FCO and FC1 are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync occurs at 1/2 the
sampling time as measured from the falling edge of the primary FS.

1

1

1

1

On the next falling edge of the primary FS, the AIC receives OAC data 015- 002 at
DIN and transmits the AOC data 015-000 from OOUT.
When FC1 and FCO are both high or 001 and 000 are both high, the AIC initiates a
secondary FS to receive a secondary control word at DIN. The secondary FS occurs
at 1/2 the sampling time measured from the falling edge of the primary FS.

1

1

0

1

On the next falling edge of FS, the AIC receives OAC data 015-002 to DIN and
transmits the AOC data 015-000 from OOUT.
When DOO and D01 are high, the AIC initiates a secondary FS to receive a secondary
control word at DIN. The secondary frame sync occurs at 1/2 the sampling time as
measured from the falling edge of the primary FS.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of FS, the next ADC/OAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, FS occurs earlier.

1

1

1

0

On the next falling edge of FS, the AIC receives OAC data 015-002 to DIN and
transmits the AOC data 015-000 from OOUT.
When 000 and 001 are high, the AIC initiates a secondary FS to receive a secondary
control word at DIN. The secondary frame sync occurs at 1/2 the sampling time as
measured from the falling edge of the primary FS.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of FS, the next AOC/OAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, FS occurs earlier.

1

1

1

1

On the next falling edge of FS, the AIC receives OAC data 015-002 at DIN and
transmits the AOC data 015-000 from OOUT.
When FC1 and FCO are both high or 001 and 000 are both high, the AIC initiates a
secondary FS to receive a secondary control word at DIN. The secondary FS occurs
at 1/2 the sampling time measured from the falling edge of the primary FS.

4-260

Appendix B
Secondary Communications
The function of the control bits OS15 and OS14 and the hardware terminals FCD and FC1 are shown below.
Any combinational state of OS15, OS14, FC1, and FCD not shown is ignored.

CONTROL FUNCTION OF SECONDARY COMMUNICATION
TERMINALS

BITS

FC1

FCO

OS15

OS14

0

0

Ignored

On the next falling edge of FS, the AIC receives OAC data 015-002 at OIN and
transmits the AOC data 015-000 from OOUT.

0

1

Ignored

On the next falling edge of the FS, the AIC receives OAC data 015-002 at OIN and
transmits the AOC data 015-000 from OOUT.
The phase adjustment is determined by the state of OS15 and OS14 such that on the
next rising edge of FS, the next AOC/OAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, FS occurs earlier.

1

0

Ignored

On the next falling edge of FS, the AIC receives OAC data 015-002 at OIN and
transmits the AOC data 015-000 from OOUT.
The phase adjustment is determined by the state of 001 and 000. On the next rising
edge of FS, the next AOC/OAC sampling time occurs earlier by the number of MCLK
periods determined by the value contained in the A' register. When the A' register
value is negative, FS occurs later.

1

1

0

0

On the next falling edge of FS, the AIC receives OAC data 015-002 at OIN and
transmits the AOC data 015-000 from OOUT.

1

1

0

1

On the next falling edge of the FS, the AIC receives OAC data 015-002 at OIN and
transmits the AOC data 015-000 from OOUT.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of FS, the next AOC/OAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, FS occurs earlier.

1

1

1

0

On the next falling edge of FS, the AIC receives OAC data 015-002 at OIN and
transmits the AOC data 015-000 from OOUT.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of FS, the next AOC/OAC sampling time occurs earlier by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, FS occurs later.

1

1

1

1

On the next falling edge of FS, the AIC receives OAC data 015-002 at OIN and
transmits the AOC data 015-000 from OOUT.

4-261

4-262

Appendix C
TLC320AC01 CITLC320AC02C Specification Comparisons
Texas Instruments manufactures the TLC320AC01 C and the TLC320AC02C specified for the O°C to 70°C
commercial temperature range and the TLC320AC021 specified for the -40°C to 85°C temperature range.
The TLC320AC02C and TLC320AC021 operate at a relaxed TLC320AC01 C specification. The differences
are listed in the following tables.

ADC Channel Signal-to-Distortion Ratio, Voo
Otherwise Noted) (see Note 1)
PARAMETER

TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02

TEST CONDITIONS

VI=-6dBto-1 dB
VI=-12dBto-6dB
VI = -18 dB to -12 dB
VI = -24 dB to -18 dB
VI

= -30 dB to -24 dB

VI = -36 dB to -30 dB
VI

= -42 dB to -36 dB

VI

= -48 dB to -42 dB

AV=OdB
MIN

MAX

=5 V, fs =8 kHz (Unless
AV=6dB

Av = 12 dB

MIN

MIN

MAX

64

-

63

68

59

64

-

57

63

68

56

59

64

68

MAX

UNIT

-

51

57

63

50

56

59

45

51

57

44

50

56

39

45

51

38

44

50

33

39

45

32

38

44

27

33

39

26

32

38

dB

NOTE 1: The analog-input test signal is a 1020-Hz sine wave with 0 dB = 6 V peak to peak as the reference level for
the analog input signal.

4-263

DAC Channel Signal-to-Distortion Ratio, Vee
Otherwise Noted) (see Note 2)
PARAMETER
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02

TEST CONDITIONS
Vo = -6 dB to 0 dB
VO=-12dBto-6dB
Vo = ~ 18 dB to -12 dB
Vo = -24 dB to -18 dB
Vo = -30 dB to -24 dB

Vo = -36 dB to -30 dB
Vo = -42 dB to -36 dB
Vo = -48 dBlo -42 dB

Av=OdB
MIN

MAX

=5 V, 1s =8 kHz (Unless
Av =-6dB
MIN

64

-

63

68

68

MAX

AV =-12 dB
MIN

MAX

UNIT

-

-

..

-

59

64

57

63

68

56

59

64

51

57

63

50

56

59

45

51

57

44

50

56

39

45

51

38

44

50

33

39

45

32

38

44

27

33

39

26

32

38

dB

NOTE 2: The input signal, VI, is the digital equivalent of a 1020-Hz sine wave (full-scale analog output at full-scale digital
input = 0 dB). The nominal differential DAC channel output with this input condition is 6 V peak to peak. The
load impedance for the DACoutput buffer is 600 n from OUT + to OUT -.

4-264

System Distortion, ADC Channel Attenuation, Voo
FCLK 144 kHz (Unless Otherwise Noted)

=

PARAMETER
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02

=5 V, fs =8 kHz,

TEST CONDITIONS

Second harmonic
Differential input
(see Note 3)
Third harmonic and higher harmonics

MIN

MAX

UNIT

70

dB

64

dB

70

dB

64

dB

NOTE 3: The input signal is a 1020 Hz-sine wave for the ADC channel. Harmonic distortion is defined for an input level
of -1 dB.

System Distortion, DAC Channel Attenuation, VOO
FCLK 144 kHz (Unless Otherwise Noted)

=

PARAMETER
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02

=5 V, fs =8 kHz,

TEST CONDITIONS

Second harmonic
Differential output
(see Note 4)
Third harmonic and higher harmonics

MIN

MAX

UNIT

70

dB

64

dB

70

dB

64

dB

NOTE 4: The input signal is the digital equivalent of a 1020-Hz sine wave (digital full scale = 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the DAC
output buffer is 600 Q from OUT + to OUT -. Harmonic distortion is specified for a signal input level of 0 dB.

4-265

4-266

Appendix 0
Multiple TLC320AC01/02 Analog Interface Circuits on One
TMS320C5X DSP Serial Port
In many applications, digital signal processors (OSP) must obtain information from multiple analog-to-digital
(NO) channels and transmit digital data to multiple digital-to-analog (O/A) conversion channels. The
problem is how to do it easily and efficiently.
This application report addresses the issue of connecting two channels of an analog interface circuit (AIC)
to one TMS320C5X OSP serial port. In this application report, the AIC is the TLC320AC01.
The TLC320AC01 (and TLC320AC02) analog interface circuit contains both NO and O/A converters and
using the master/slave mode, it is possible to connect two of them to one TMS320C5X OSP serial port with
no additional logic. The hardware schematic is shown in Figure 0-1.

4-267

TMS320C5x

TLC320AC01
.. 14

CLKOUT

~

.. 10

DX

~

11

DR
FSX
FSR

12

W

,----

13

CLKX

MCLK
DIN
DOUT
Master Mode

FS
FSD
SCLK

CLKR ~
TLC320AC01
14
.. 10
11

MCLK
DIN
DOUT

~ FS
,----

13

~,

~~

~

, ,
~

FSD
SCLK

Slave Mode

~,

NOTE A: Terminal numbers shown are for the FN package.

Figure 0-1. Master With Slave (to OSP Interface)

HARDWARE AND SOFTWARE SOLUTION
Once the hardware connections are completed, the issue becomes distinguishing one channel from
another. Fortunately, this is very easy to do in software and adds very little overhead. The mode that the
AC01 s run in is called master/slave mode. One AC01 is the master and all of the rest of the AC01 s are
slaves. The master can be distinguished from all of the slaves by examining the least significant bit (LSB)
in the receive word coming from the AC01. The master has a 0 in the LSB and all of the slaves have a 1
in the LSB.
The AC01 s in master/slave mode take turns communicating with the DSP serial port. They do this is a round
robin or circular fashion. Synchronizing the system involves looking for the master AC01 and then starting
the software associated with the first AC01. All other AC01 s follow in order. It is possible to have different
software for each AC01.
A reference design was constructed using a TMS320C5X OSP starter kit (OSK). The AC01 s were
connected to the TOM serial port which is available at the headers on the edge of the DSK.
A listing of the OSK assembly code for a simple stereo input/output program is included in the following
section.
4-268

SOFTWARE MODULE
*****************************************************************************

*
:*
*
:*

**
*
:*

MODULE NAME: INOUTB. ASM

:

In-out routine for C5X DSK with two TLC320ACOls on the
TDM serial port of the C5X in master/slave mode.

:

:

*

:
:

This version performs the in/out task for both the master
and slave TLC320ACOl in the receive interrupt service
routine.

:*
:

*
*
**
*
******************************************************************************
.mmregs

*

.ds

OlOOOh

PRl

. word

0104h

;A register

PR2

.word

0219h

;B register

PR3

. word

0300h

;A prime register

PR4

.word

0405h

;amplifier gain register

PR5

.word

0501h

;analog configuration register

PR6

.word

0600h

;digital configuration register

PR7

. word

0730h

; frame synch delay register

PR8

. word

0802h

; frame synch number register

value

. word

0800h

value2

. word

0800h

val_add

. word

0200h

val_add2

. word

0400h

~****************************************************************************

*: Set up the ISR vector

:*
*.*****************************************************************************
.ps

080ah

rint:

B

RECEIVE

OA; Serial port receive interrupt RINT.

xint:

B

TRANSMIT

OC; Serial port transmit interrupt XINT.

trint:

B

TDMREC

txint:

B

TDMTX

i---------------------------

*
*****************************************************************************

:*

:*

TMS32OC5X INITIALIZATION

*
*
*****************************************************************************
.ps OaOOh
. entry
START:

SETC

INTM

Disable interrupts

LDP

#0

Set data page pointer

OPL

#0834h,PMST

LACC

#0

SAMM

CWSR

SAMM

PDWSR

4-269

splk

#OOcBh

SPLK

OB2h,IMR

call

ACOlINIT

CLRC

OVM

OVM

SPM

0

PM

SPLK

#042h,IMR

TDMA ser port rec interrupt

SPLK

#OC8h,TSPC

CLRC

INTM

loop

=0
=0

enable interrupts
main program here does nothing.

nop
b

a user program can be inserted.
loop

; - - - - - - - - - - end of main p r o g r a m - - - - - - - - - TDM serial port receiver interrupt service routine
TDMREC:
This loop insures that the master AC01
ldp

#trcv

bit

trcv,l5

loop. the slave AC01(s) will follow in

bcnd

xxx, tc

sequential order. The master AC01 has a

is the first one that is written to in the

o

in the 1sb. the slave AC01(s) have a 1

in the 1sb of the receive word.
ldp

#trcv

lacc

trcv

and

#Offfch
user code would go here for master AC01

sacl

tdxr

b

yyy

xxx
ldp

#trcv

lacc

trcv

and

#Offfch
user code would go here for slave AC01

sacl
yyy

rete

4-270

tdxr

TDM serial port transmit interrupt service routine
TDMTX:
rete
RECEIVER INTERRUPT SERVICE ROUTINE
RECEIVE:
rete
TRANSMIT:
RETE

4-271

ACOlINIT
SPLK

#020h,TCR

SPLK

#Olh,PRD

MAR

* ,ARO

LACC

#0008h

SACL

TSPC

LACC

#00c8h

SACL

TSPC

SETC

SXM

;----------------------------LDP

#PRl

LACC

PRl

CALL

AC01_2ND

i----------------------------LDP

#PR2

LACC

PR2

CALL

AC01_2ND

LDP

#PR8

LACC

PR8

CALL

AC01_2ND

;---~-------------------------

LDP

#PR7

LACC

PR7

CALL

AC01_2ND

ret
AC01_2ND:
LDP

#0

SACH

TDXR

CLRC

INTM

IDLE
ADD

#6h, 15

SACH

TDXR

0000 0000 0000 0011 XXXX XXXX XXXX XXXX b

IDLE
SACL

TDXR

IDLE
LACL

#0

SACL

TDXR

IDLE
SETC
RET

4-272

INTM

make sure the word got sent

TLC320AC02C, TLC320AC021
Data Manual
Single-Supply Analog Interface Circuit

SLAS084C
October 1997

•
TEXAS
INSTRUMENTS

Printed on Recycled Paper

IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants p,ertormance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.

Copyright © 1997, Texas Instruments Incorporated

Contents
Section

Title

Page

1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.1 Features.......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.3 Terminal Assignments ................................................
1.4 Terminal Functions ...................................................
1.5 Register Functional Summary .........................................

4-281
4-282
4-283
4-283
4-285
4-288

2

Detailed Description .....................................................
2.1 Definitions and Terminology .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.2 Reset and Power-Down Functions .....................................
2.2.1 Reset ........................................................
2.2.2 Conditions of Reset ............................................
2.2.3 Software and Hardware Power-Down .............................
2.2.4 Register Default Values After POR, Software Reset
or RESET Is Applied ...........................................
2.3 Master-Slave Terminal Function .......................................
2.4 ADC Signal Channel :................................................
2.5 DAC Signal Channel .................................................
2.6 Serial Interface ......................................................
2.7 Number of Slaves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.8 Required Minimum Number of MCLK Periods ...........................
2.8.1 TLC320AC02 AIC Master-Slave Summary ........................
2.8.2 Notes on TLC320AC01/02 AIC Master-Slave Operation . . . . . . .. . . . ..
2.9 Operating Frequencies ...............................................
2.9.1 Master and Stand-Alone Operating Frequencies ...................
2.9.2 Slave and Codec Operating Frequencies .........................
2.10 Switched-Capacitor Filter Frequency (FCLK) ............................
2.11 Filter Bandwidths ....................................................
2.12 Master and Stand-Alone Modes .......................................
2.12.1 Register Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.12.2 Master and Stand-Alone Functional Sequence. . . . . . . . . . . . . . . . . . . ..
2.13 Slave and Codec Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.13.1 Slave and Codec Functional Sequence ...........................
2.13.2 Slave Register Programming ....................................
2.14 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.14.1 Frame-Sync Function ..........................................
2.14.2 Data Out (DOUT) ..............................................
2.14.3 Data In (DIN) ..................................................
2.14.4 Hardware Program Terminals (FC1 and FCO) ......................
2.14.5 Midpoint Voltages (ADC VMIO and DAC VMIO) .....................

4-289
4-289
4-290
4-290
4-290
4-290
4-290
4-292
4-292
4-292
4-292
4-293
4-294
4-294
4-295
4-297
4-297
4-297
4-297
4-297
4-297
4-297
4-298
4-298
4-299
4-299
4-299
4-299
4-300
4-300
4-300
4-301
4-275

2.15 Device Functions .................................................... 4-301
2.15.1 Phase Adjustment ............................................. 4-301
2.15.2 Analog Loopback .............................................. 4-302
2.15.316-BitMode ................................................... 4-302
2.15.4 Free-Run Mode ................................................ 4-302
2.15.5 Force Secondary Communication .................... . . . . . . . . . . .. 4-302
2.15.6 Enable Analog Input Summing ................................... 4-303
2.15.7 DAC Channel (sin x)/x Error Correction ........................... 4-303
2.16 Serial Communications ............................................... 4-303
2.16.1 Stand-Alone and Master-Mode Word Sequence and Information Content
During Primary and Secondary Communications ................... 4-303
2.16.2 Slave and Codec-Mode Word Sequence and Information Content During
Primary and Secondary Communications ......................... 4-304
2.17 Request for Secondary Serial Communication and Phase Shift ............ 4-305
2.17.1 Initiating a Request ............................................ 4-305
2.17.2 Normal Combinations of Control ................................. 4-305
2.17.3 Additional Control Options ................ ,..................... 4-305
2.18 Primary Serial Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-306
2.18.1 Primary Serial Communications Data Format ...................... 4-307
2.18.2 Data Format From DOUT During Primary Serial Communications .... 4-307
2.19 Secondary Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-307
2.19.1 Data Format to DIN During Secondary Serial Communications ....... 4-307
2.19.2 Control Data-Bit Function in Secondary Serial Communication ....... 4-307
2.20 Internal Register Format .............................................. 4-308
2.20.1 Pseudo-Register 0 (No-Op Address) ............................. 4-308
2.20.2 Register 1 (A Register) ......................................... 4-308
2.20.3 Register 2 (B Register) ......................................... 4-309
2.20.4 Register 3 (A' Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-309
2.20.5 Register 4 (Amplifier Gain-Select Register) ........................ 4-310
2.20.6 Register 5 (Analog Configuration Register) ........................ 4-310
2.20.7 Register 6 (Digital Configuration Register) . . . . . . . . . . . . . . . . . . . . . . . .. 4-311
2.20.8 Register 7 (Frame-Sync Delay Register) .......................... 4-311
2.20.9 Register 8 (Frame-Sync Number Register) ........................ 4-312

3

Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range . "
3.2 Recommended Operating Conditions ....................... , ......... "
3.3 Electrical Characteristics Over Recommended Range of Operating Free-Air
Temperature, MCLK = 5.184 MHz, Voo = 5 V, Outputs Unloaded,
Total Device .........................................................
3.4 Electrical Characteristics Over Recommended Range of Operating Free-Air
Temperature, Voo = 5 V, Digital 1/0 Terminals (DIN, DOUT, EOC,
FCO, FC1, FS, FSD, MCLK, MIS, SCLK) ............ -....................
3.5 Electrical Characteristics Over Recommended Range of Operating Free-Air
Temperature, Voo = 5 V, ADC and DAC Channels .......................
3.5.1 ADC Channel Filter Transfer Function, FCLK = 144 kHz, fs = 8 kHz ..
3.5.2 ADC Channel Input, Voo = 5 V, Input Amplifier Gain = 0 dB .........
3.5.3 ADC Channel Signal-to-Distortion Ratio, Voo = 5 V, fs = 8 kHz ......

4-276

4-313
4-313
4-313

4-314

4-314
4-314
4-314
4-315
4-315

3.6

3.7

3.5.4 DAC Channel Filter Transfer Function, FCLK = 144 kHz, f5 = 9.6 kHz,
Voo = 5 V .................................................... 4-315
3.5.5 DAC Channel Signal-to-Distortion Ratio, Voo = 5 V, f5 = 8 kHz ...... 4-316
3.5.6 System Distortion, Voo = 5 V, f5 = 8 kHz, FCLK = 144 kHz .......... 4-316
3.5.7 Noise, Low-Pass and Band-Pass Switched-Capacitor Filters Included,
Voo = 5 V .................................................... 4-317
3.5.8 Absolute Gain Error, Voo = 5 V, f5 = 8 kHz ........................ 4-317
3.5.9 Relative Gain and Dynamic Range, Voo = 5 V, f5 = 8 kHz ........... 4-317
3.5.10 Power-Supply Rejection, Voo = 5 V .............................. 4-318
3.5.11 Crosstalk Attenuation, Voo = 5 V ................................ 4-318
3.5.12 Monitor Output Characteristics, VOO = 5 V ........................ 4-319
Timing Requirements and Specifications in Master Mode ................. 4-320
3.6.1 Recommended Input Timing Requirements for Master Mode,
Voo = 5 V .................................................... 4-320
3.6.2 Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, Voo = 5 V ........................................ 4-320
Timing Requirements and Specifications in Slave Mode and Codec
Emulation Mode ..................................................... 4-321
3.7.1 Recommended Input Timing Requirements for Slave Mode,
Voo = 5 V .................................................... 4-321
3.7.2 Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, Voo = 5 V ........................................ 4-321

4

Parameter Measurement Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-323

5

Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-329

6

Application Information .................................................. 4-343

A

Primary Control Bits ..................................................... 4-347

B

Secondary Communications ............................................. 4-349

C

TLC320AC01 C/TLC320AC02C Specification Comparisons ................. 4-351

D

Multiple TLC320AC01/02 Analog Interface Circuits
on One TMS320C5X DSP Serial Port ...................................... 4-355

4-277

List of Illustrations
Figure

Title

1-1 Control Flow Diagram .................................................
2-1 Functional Sequence for Primary and Secondary Communication ...........
2-2 Timing Sequence .....................................................
2-3 Master and Stand-Alone Functional Sequence ............................
2-4 Slave and Codec Functional Sequence ..................................
4-1 IN + and IN- Gain-Control Circuitry ......................................
4-2 AIC Stand-Alone and Master-Mode Timing ...............................
4-3 AIC Slave and Codec Emulation Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-4 Master or Stand-Alone FS and FSD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-5 Slave FS to FSD Timing ...............................................
4- 6 Slave SCLK to FSD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-7 DOUT Enable Timing From Hi-Z ........................................
4-8 DOUT Delay Timing to Hi-Z ............................................
4-9 EOC Frame Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-10 Master-Slave Frame-Sync Timing After a Delay Has Been Programmed
Into the FSD Registers .................................................
4-11 Master and Slave Frame-Sync Sequence with One Slave ..................
5-1 ADC Low-Pass Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-2 ADC Low-Pass Response ..............................................
5-3 ADC Group Delay .....................................................
5-4 ADC Band-Pass Response ........................................... "
5-5 ADC Band-Pass Response .............................................
5-6 ADC High-Pass Response .............................................
5-7 ADC Band-Pass Group Delay ..........................................
5-8 DAC Low-Pass Response ..............................................
5-9 DAC Low-Pass Response ..............................................
5-10 DAC Low-PASS Group Delay ...........................................
5-11 DAC (sin x)/x Correction Filter Response .................................
5-12 DAC (sin x)/x Correction Filter Response .................................
5-13 DAC (sin x)/x Correction Error ..........................................

4-278

Page
4-287
4-293
4-294
4-304
4-304
4-323
4-324
4-324
4-325
4-325
4-325
4-326
4-326
4-326
4-327
4-327
4-329
4-330
4-331
4-332
4-333
4-334
4-335
4-336
4-337
4-338
4-339
4-340
4-341

List of Tables
Table

1-1
2-1
2-2
2-3
4-1

Title

Page

Operating Frequencies ................................................
Master-Slave Selection ................................................
Sampling Variation With A' .............................................
Software and Hardware Requests for Secondary Serial-Communication and
Phase-Shift Truth Table ............ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Gain Control ..........................................................

4-287
4-292
4-301
4-306
4-323

4-279

4-280

1

Introduction

The TLC320AC02t analog interface circuit (AIC) is an audio-band processor that pr~)Vides an
analog-to-digital and digital-to-analog input/output interface system on a single monolithic CMOS chip. This
device integrates a band-pass switched-capacitor antialiasing input filter, a 14-bit-resolution
analog-to-digital converter (ADC), a 14-bit-resolution digital-to-analog converter (DAC), a low-pass
switched-capacitor output-reconstruction filter, (sin x)/x compensation, and a serial port for data and control
transfers.
The internal circuit configuration and performance parameters are determined by reading control
information into the eight available data registers. The register data sets up the device for a given mode of
operation and application.
The major functions of the TLC320AC02 are:
1.

To convert audio-signal data to digital format by the ADC channel

2.

To provide the interface and control logic to transfer data between its serial input and output
terminals and a digital signal processor (DSP) or microprocessor

3.

To convert received digital data back to an audio signal through the DAC channel

The antialiasing input low-pass filter is a switched-capacitor filter with a sixth-order elliptic characteristic. The
high-pass filter is a single-pole filter to preserve low-frequency response as the low-pass filter cutoff is
adjusted. There is a three-pole continuous-time filter that precedes this filter to eliminate any aliasing caused
by the filter clock signal.
The output-reconstruction switched-capacitor filter is a sixth-order elliptic transitional low-pass filter followed
by a second-order (sin x)/x correction filter. This filter is followed by a three-pole continuous-time filter to
eliminate images of the filter clock signal.
The TLC320AC02 consists of two signal-processing channels, an ADC channel and a DAC channel, and
the associated digital control. The two channels operate synchronously; data reception at the DAC channel
and data transmission from the ADC channel occur during the same time interval. The data transfer is in
2s-complement format.
There are three basic modes of operation available: the stand-alone analog-interface mode, the
master-slave mode, and the linear-codec mode. In the stand-alone mode, the TLC320AC02 generates the
shift clock and frame synchronization for the data transfers and is the only AIC used. The master-slave mode
has one TLC320AC02 as the master that generates the master-shift clock and frame synchronization; the
remaining AICs are slaves to these signals. In the linear-codec mode, the shift clock and the framesynchronization Signals are externally generated and the timing can be any of the standard codec-timing
patterns.
Typical applications for this device include modems, speech processing, analog interface for DSPs,
industrial-process control, acoustical-signal processing, spectral analysis, data acquisition, and
instrumentation recorders.
The TLC320AC02C is characterized for operation from O°C to 70°C and the TLC320AC021 is characterized
for operation from -40°C to 85°C.

t The TLC320AC02 is functionally equivalent to the TLC320AC01

and differs in the electrical specifications as shown

in Appendix C.
~281

1.1

Features
•

General-Purpose Signal-Processing Analog Front End (AFE)

•

Single 5-V Power Supply

•

Power Dissipation ... 100 mW Typ

•

Signal-to-Distortion Ratio ... 70 dB Typ

•

Programmable Filter Bandwidths (Up to 10.8 kHz) and Synchronous ADC and DACSampling

•

Serial-Port Interface

•

Monitor Output With Programmable Gains of 0 dB, -8 dB, -18 dB, and Squelch

•

Two Sets of Differential Inputs With Programmable. Gains of

•

Differential or Single-Ended Analog Output With Programmable Gains of 0 dB, -6 dB, -12 dB,
and Squelch

•

Differential Outputs Drive 3-V Peak Into a 600-a Differential Load

•

Differential Architecture Throughout

•

1-llm Advanced LinEPICTM Process

•

14-Bit Dynamic-Range ADC and DAC

•

2s-Complement Data Format

linE PIC is a trademark of Texas Instruments Incorporated.

4-282

a dB, 6 dB, 12 dB, and Squelch

1.2

Functional Block Diagram

IN+
INAUXIN+
AUXIN-

26
25
28
27

11 DOUT
12 FS

MONOUT

14

MIS

18

FCO
FC1

15
16

OUT+
OUT-

MCLK
13 SCLK

10 DIN
17 FSD

3
4

19 EOC

2
PWR
OWN

DAC
VDD

DAC
GND

DGTL
GND

DGTL
VDD

DAC
VMID

RESET

Terminal numbers shown are for the FN package.

1.3

Terminal Assignments
FN PACKAGE
(TOP VIEW)

I~

~

+

I

I +OO~~

xx +
I-I-Ia:z
::::>::::> ~ 0::::>::::> z_
OOI:l.:iEc(c(

DAC vee
DAC VMle
DAC GND
RESET
DGTL Vee
DIN
DOUT

4

5

3 2

282726
0

25

6

24

7

23

8
9

22

10

20

21

11
19
1213 1415161718

INADC Vee
ADC VMID
ADC GND
SUBS
DGTLGND
EOC

(/)::t:: ::t::
""',0
ILL....J....JOO(/);;;;;
OOLLLLLL"':::
0

I(/)

(/):iE

4-283

1.3

Terminal Assignments (Continued)
PM PACKAGE
(TOP VIEW)

g
>
..J

Cl

I-

W

~

9

~

0

~

I(f)
0
0
0
OOOOO"OWOO«OO«O«
ZZZZZClZa:ZZClZZClZCl

DIN
NC
DOUT
NC
NC
NC
SCLK
NC
MCLK
FCD
FC1
NC
NC

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2
47
3
46
45
4
44
5
43
6
7
42
41
8
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 1920 21 22 23 242526 2728 29 30 31 32

10

OOOOOClO(f)OOClOOClOCl

@ZZZZZZ~ZZZZZ~ZCl

"
(f)
..J
~
Cl
NC - No internal connection

4-284

"0
Cl
«

>

0

Cl
«

>
0

Cl
«

NC
NC
OUTNC
NC
OUT+
PWRDWN
NC
MONOUT
NC
AUXIN+
AUXININ+
INNC
NC

1.4

TerminalFunctions
TERMINAL

I/O

DESCRIPTION

NO.t

NOJ

AOCVOD

24

32

I

Analog supply voltage for the ADC channel

ADC VMID

23

30

0

Midsupply for the ADC channel (requires a bypass capacitor). ADC VMID must be
buffered when used as an external reference.

NAME

ADCGND

22

27

I

Analog ground for the ADC channel

AUX IN+

28

38

I

Noninverting input to auxiliary analog input amplifier

AUX IN-

27

37

I

Inverting input to auxiliary analog input amplifier

DAC VOD

5

49

I

Digital supply voltage for the DAC channel

DACVMID

6

51

0

Midsupply for the DAC channel (requires a bypass capacitor). DAC VMID must be
buffered when used as an external reference.

DACGND

7

54

I

Analog ground for the DAC channel

DIN

10

1

I

Data input. DIN receives the DAC input data and command information and is
synchronized with SCLK.

DOUT

11

3

0

Data output. DOUr outputs the ADC data results and register read contents.
DOUT is synchronized with SCLK.

DGTL VDD

9

59

I

Digital supply voltage for control logic

DGTLGND

20

22

I

Digital ground for control logic

EOC

19

17

0

End-of-conversion output. EOC goes high at the start of the ADC conversion
period and low when conversion is complete. EOC remains low until the next ADC
conversion period begins and indicates the internal device conversion period.

FCO

15

11

I

Hardware control input. FCO is used in conjunction with FC1 to request secondary
communication and phase adjustments. FCO should be tied low if it is not used.

FC1

16

12

I

Hardware control input. FC1 is used in conjunction with FCO to request secondary
communication and phase adjustments. FC1 should be tied low if it is not used.

FS

12

4

I/O

Frame synchronization. When FS goes low, DIN begins receiving data bits and
DOUT begins transmitting data bits. In master mode, FS is low during the
simultaneous 16-bit transmission to DIN and from DOUT. In slave mode, FS is
externally generated and must be low for one shift-clock period minimum to initiate
the data transfer.

FSD

17

14

0

Frame-synchronization delayed output. This active-low output synchronizes a
slave device to the frame synchronization timing of the master device. FSD is
applied to the slave FS input and is the same duration as the master FS signal but
delayed in time by the number of shift clocks programmed in the FSD register.

IN+

26

36

I

Noninverting input to analog input amplifier

IN-

25

35

I

Inverting input to analog input amplifier

MCLK

14

10

I

The master-clock input drives all the key logic signals of the AIC.

1

40

0

The monitor output allows monitoring of analog input and is a high-impedance
output.

18

16

I

Master/slave select input. When M/S is high, the device is the master and when
low, it is a slave.

MONOUT
M/S

t Terminal numbers shown are for the FN package.
:t: Terminal numbers shown are for the PM package.

4-285

1.4

Terminal Functions (Continued)
TERMINAL

1/0

DESCRIPTION

43

a

Noninverting output of analog output power amplifier. OUT+ can drive transformer
hybrids or high-impedance loads directly in a differential connection or a
single-ended configuration with a buffered VMID.

4

46

a

Inverting output of analog output power amplifier. OUT-is functionally identical
with and complementary to OUT +.

PWRDWN

2

42

I

Power-down input. When PWR DWN is taken low, the device is powered down
such that the existing internally programmed state is maintained. When PWR
DWN is brought high, full operation resumes.

RESET

8

57

I

Reset input that initializes the internal counters and control registers. RESET
initiates the serial data communications, initializes all of the registers to their
default values, and puts the device in a preprogrammed state. After a low-going
pulse on RESET, the device registers are initialized to provide a 16-kHz
data-conversion rate and 7.2-kHz filter bandwidth for a 10.368-MHz master clock
input signal.

SCLK

13

8

I/O

Shift clock. SCLK clocks the digital data into DIN and out of DOUT during the
frame-synchronization interval. When configured as an output (MIS high), SCLK
is generated internally by dividing the master clock signal frequency by four. When
configured as an input (MIS low), SCLK is generated externally and
synchronously to the master clock. This signal clocks the serial data into and out
of the device.

SUBS

21

24

I

NO.t

NO.*

OUT+

3

OUT-

NAME

t

Substrate connection. SUBS should be tied to ADC GND.

Terminal numbers shown are for the FN package.
:j: Terminal numbers shown are for the PM package.

4-286

I

Processor

~

5.184 MHz
10.368 MHz

- - - - - - - - - - - ~-------MCLK

Divide by4

SCLK

--""

1.296MHz
2.592 MHz

r

A Register + A' Register
(8 bits)
2s Complement

A Register
(8 bits)

I

I

FCLK [Iow·pass filter and
(sin x)/x filter clock] --"

I

...

Control

t

Normal

Phase Shift

0

(

--

Single, A·Counter
Period
One·Shot

B Register
(8 bits)

9

I
Program Divide
A Counter
(8 bits)

: Divide by 2

576kHz

Conversion
Rate
--""
r

B Counter

288kHz

Figure1-1. Control Flow Diagram
Table 1-1. Operating Frequencies
CONVERSION
RATE
(kHz)

HIGH·PASS
POLE FREQUENCY
(Hz)

20 (see Note 1)
18
15
10 (see Note 2)

7.2
8
9.6
14.4

36
40
48
72

7.2

20 (see Note 1)
18
15
10 (see Notes 2 and 3)

14.4
16
19.2
28.8

72
80
96
144

10.8

20 (see Note 1)
18
15 (see Note 3)
10 (see Notes 2 and 3)

21.6
24
28.8
43.2

108
120
144
216

FCLK
(kHz)

LOW·PASS FILTER
BANDWIDTH
(kHz)

144

3.6

288

432

NOTES:

B REGISTER CONTENTS
(Program No. of Filter Clocks)
(Decimal)

1. The B register can be programmed for values greater than 20; however, since the sample rate is lower than
7.2 kHz and the internal filter remains at 3.6 kHz, an external antialiasing filter is required.
2. When the B register is programmed for a value less than 10, the ADC and the DAC conversions are not
completed before the next frame-sync signal and the results are in error.
3. The maximum sampling rate for the ADC channel is 43.2 kHz. The maximum rate for the DAC channel is
25 kHz.

4-287

1.5

Register Functional Summary

There are nine data registers that are used as follows:
Register 0

The No-op register. The 0 address allows phase adjustments to be made without
reprogramming a data register.

Register 1

The A register controls the count of the A counter.

Register 2

The B register controls the count of the B counter.

Register 3

The A' register controls the phase adjustment of the sampling period. The adjustment is
equal to the register value multiplied by the input master period.

Register 4

The amplifier gain register controls the gains of the input, output, and monitor amplifiers.

Register 5

The analog configuration register controls:

Register 6

•

The addition/deletion of the high-pass filter to the ADC signal path

•

The enable/disable of the al"lalog loopback

•

The selection of the regular inputs or auxiliary inputs

•

The function that allows processing of signals that are the sum of the regular inputs and
the auxiliary inputs (VIN + VAUX IN)

The digital configuration register controls:
•

Selection of the free-run function

•

FSD[frame-synchronization (sync) delay] output enable/disable

•

Selection of 16-bit function

•

Forcing secondary communications

•

Software reset

•

Software power down

Register 7

The frame-sync delay register controls the time delay between the master-device frame
sync and slave-device frame sync. Register 7 must be the last register programmed when
using slave devices since all register data is latched and valid on the sixteenth falling edge
of SCLK. On the sixteenth falling edge of SCLK, all delayed frame-sync intervals are shifted
by this programmed amount.

Register 8

The frame-sync number register informs the master device of the number of slaves that are
connected in the chain. The frame-sync number is equal to the number of slaves plus one.

4-288

2
2.1

Detailed Description
Definitions and Terminology

ADC Channel
Codec Mode

d
Dxx
DAC Channel

All signal processing circuits between the analog input and the digital conversion
results at DOUT
The operating mode under which the device receives shift clock and frame-sync
signals from a host processor. The device has no slaves.
The d represents valid programmed or default data in the control register format
(see Section 2.19) when discussing other data-bit portions of the register.
Bit position in the primary data word (xx is the bit number)
All signal processing circuits between the digital data word applied to DIN and the
differential output analog signal available at OUT+ and OUT-

Data Transfer Interval. The time during which data is transferred from DOUT and to DIN. This interval is 16
shift clocks regardless of whether the shift clock is internally or externally generated.
The data transfer is initiated by the falling edge of the frame-sync signal.
DSxx

Bit position in the secondary data word (xx is the bit number)

FCLK

An internal clock frequency that is a division of MCLK that controls the low-pass filter
and (sinx)/x filter clock (see Figure 1-1 and Table 1-1).

Frame Sync

Frame Sync and
Sampling Period
Frame-Sync Interval

f5
Host
Master Mode

Phase Adjustment

Primary (Serial)
Communications

The analog input frequency of interest
The falling edge of the signal that initiates the data-transfer interval. The primary
frame sync starts the primary communications, and the secondary frame sync starts
the secondary communications.
The time between falling edges of successive primary frame-sync signals
The time period occupied by 16 shift clocks. Regardless of the mode of operation,
there is always an internal frame-sync interval signal that goes low on the rising
edge of SCLK and remains low for 16 shift clocks. It is used for synchronization of
the serial-port internal signals. It goes high on the seventeenth rising edge of SCLK.
The sampling frequency that is the reciprocal of the sampling period.
Any processing system that interfaces to DIN, DOUT, SCLK, or FS.
The operating mode under which the device generates and uses its own shift clock
and frame-sync signal and generates all delayed frame-sync signals necessary to
support slave devices.
The programmed time variation from the falling edge of one frame-sync signal to the
falling edge ofthe next frame sync signal. The time variation is determined by the
contents of the A' register. Since the time between falling edges of successive
frame-sync signals is the the sampling period, the sampling period is adjusted.
The digital data-transfer interval. Since the device is synchronous, the signal data
words from the ADC channel and to the DAC channel occur simultaneously.

Secondary (Serial)
Communications

The digital control and configuration data-transfer interval into DIN and the register
read-data cycle from DOUT. The data-transfer interval occurs when requested by
hardware or software.

Signal nA.ta

The input signal and all of the converted representations through the ADC channel
and return through the DAC channel to the analog output. This is contrasted with
the purely digital software-control data.

Slave Mode

The operating mode under which the device receives shift clock and frame-sync
signals from a master device.

4-289

Stand-Alone Mode

The operating mode under which the device generates and uses its own shift clock
and frame-sync signal. The device has no slave devices.

X

The X represents a don't-care bit position within the control register'format.

2.2

Reset and Power-Down Functions

2.2.1

Reset

The TLC320AC02 resets both the internal counters and registers, including the programmed registers, by
any of the following:
•
•
•

Applying power to the device, causing a power-on reset (POR)
Applying a low reset pulse to RESET
Reading in the programmable software reset bit (OS01 in register 6)

PWR OWN resets the counters only and preserves the programmed register contents.

2.2.2

Conditions of Reset

The two internal reset signals used for the reset and synchronization functions are as follows:
1.

Counter reset: This signal resets all flip-flops and latches that are not externally programmed with
the exception of those generating the reset pulse itself. In addition, this signal resets the software
power-down bit.
Counter reset = power-on reset + RESET + RESET bit + PWR OWN

2.

Register reset: This signal resets all flip-flops and latches that are not reset by the counter reset
except those generating the reset pulse itself.
Register reset = power-on reset + RESET + RESET bit

Both reset signals are at least one master-clock period long and release on the falling edge of the master
clock.

2.2.3

Software and Hardware Power-Down

Given the definitions and conditions of RESET, the software-programmed power-down condition is cleared
by resetting the software bit (OSOO in register 6) to zero. It is also cleared by either cycling the power to the
device, bringing PWR OWN low, or bringing RESET low.
PWR OWN powers down the entire chip ( < 1 mA ). The software-programmable power-down bit only
powers down the analog section of the chip ( < 3 mA ), which allows a software power-up function. Cycling
PWR OWN high to low and back to high resets all flip-flops and latches that are not externally programmed,
thereby preserving the register contents.
When PWR OWN is not used, it should be tied high.

2.2.4

Register Default Values After POR, Software Reset, or RESET Is Applied

Register 1 - The A Register
The default value of the A-register.data is decimal 18 as shown below.

4-290

Register 2 - The B Register
The default value of the B-register data is decimal 18 as shown below.

Register 3 - The A' Register
The default value of the A'-register data is decimal 0 as shown below.

Register 4 - The Amplifier Gain-Select Register
The default value of the amplifier gain-select register data is shown below.

Register 5 - The Analog Control-Configuration Register
The power-up and reset conditions are as shown below. In the read mode, 8 bits are read but the 4 LSBs
. are repeated as the 4 MSBs.

Register 6 - The Oigital Configuration Register
The default value of OS07 - OSOO is 0 as shown below.

Register 7 - The Frame-Sync Oelay Register
The default value of OS07 - OSOO is 0 as shown below.

Register 8 - The Frame-Sync Number Register
The default value of OS07 - OSOO is 1 as shown below.

4-291

2.3

Master-Slave Terminal Function

Table 2-1 describes the function of the masterlslave (MIS) input. The only difference between master and
slave operations in the TLC320AC02 is that SCLK and FS are outputs when MIS is high and inputs when
MIS is low.

Table 2-1. Master-Slave Selection

MIst

FS

SCLK

Master and Stand Alone

H

Output

Output

Slave and Codee Emulation

L

Input

Input

MODE

t When the stand-alone mode is desired or when the device is
permanently in the master mode, Mis must be high.

2.4

ADC Signal Channel

To produce excellent common-mode rejection of unwanted signals, the analog signal is processed
differentially until it is converted to digital data. The signal is amplified by the input amplifier at one of three
software-selectable gains (typically 0 dB, 6 dB, or 12 dB). A squelch mode can also be programmed for the
input amplifier.
The amplifier output is filtered and applied to the ADC input. The ADC converts the signal into discrete digital
words in 2s-complement format corresponding to the analog-signal value at the sampling time. These 16-bit
digital words, representing sampled values of the analog input signal, are clocked out of the serial port
(DOUT), one word for each primary communication interval. During secondary communications, the data
previously programmed into the registers can be read out with the appropriate register address and with the
read bit set to 1. When a register read is not requested, all 16 bits are O.

2.5

DAC Signal Channel

DIN receives the 16-bit serial data word (2s complement) from the host during the primary communications
interval and latches the data on the seventeenth rising edge of SCLK. The data are converted to an analog
voltage by the DAC with a sample and hold and then through a (sin x)/x correction circuit and a smoothing
filter. An output buffer with three software-programmable gains (0 dB, -6 dB, and -12 dB), as shown in
register 4, drives the differential outputs OUT + and OUT -. A squelch mode can also be programmed for
the output buffer. During secondary communications, the configuration program data are read into the
device. control registers.

2.6

Serial Interface

The digital serial interface consists of the shift clock, the frame-synchronization signal, the ADC-channel
data output, and the DAC-channel data input. During the primary 16-bit frame-synchronization interval, the
SCLK transfers the ADC channel results from DOUT and transfers 16-bit DAC data into DIN.
During the secondary frame-synchronization interval, the SCLK transfers the register read data from DOUT
when the read bit is set to a 1. In addition, the SCLK transfers control and device parameter information into
DIN. The functional sequence is shown in Figure 2-1.

4-292

I+1

I+-

SCLK

1

Frame-Sync Interval -+1

j+- Frame-Sync Interval -+1

hfm:~~AA
1
1
I + - 16 SCLKs

FS

~I

[(8 register)/2] FCLK Periodst

1

1/)

1
1

1
1

~I

I

1
1
16 SCLKs ---+1

I~

1/)

I

IJr--r1

DOIIT

taM~

I

...,..........

1

DIN

t

~

I

DAC,"P"'*

>

1

1

~Co"OI'",~""~

The time between the primary and secondary frame sync is the time equal to filter clock (FCLK) period multiplied by the
B-register contents divided by two. The time interval is rounded to the nearest shift clock. The secondary frame-sync
signal goes from high to Iowan the next shift clock low-to-high transition after (B register/2) filter clock periods.

Figure 2-1. Functional Sequence for Primary and Secondary Communication

2.7

Number of Slaves

The maximum number of slaves is determined by the sum of the individual device delays from the
frame-sync (FS) input low to the frame-sync delayed (FSD) low for all slaves according to equation 1:
(n) 1 tp(FS-FSD) < 1/2 shift-clock period

(1 )

Where:
n is the number of slave devices.
Example:
From equation 1 above, the number of slaves is given by equation 2:
(n)

s ~ x (SCLK period) x tp(FS ~ FSD)

(2)

assuming the master clock is 10.368 MHz and the shift clock is 2.5965 MHz and tp(FS - FSD) is 40 ns, then
according to equation 3, the number of slaves is:
<
1
1
1
_ 1000 _
n - 2.5965 MHz x 2 x 40 ns - 192 - 4.8

(3)

The maximum number of slaves under these conditions is four.

4-293

2.8

Required Minimum Number of MCLK Periods

Master with slave operation is summarized in the following sections.

2.8.1

TLC320AC02 AIC Master-Slave Summary

After initial setup and the master and slave frame syncs are separated, when secondary communication is
needed for a slave device, a 11 must be placed in the 2 LSBs of each primary data word for all devices in
the system, master and slave, by the host processor. In other words, all AICs must receive secondary frame
requests.
The host processor must issue the command by setting 001 and 000 to a 1 in the primary frame sync data
word of all devices. Then the master generates the master primary frame sync and, after the number of shift
clocks set by the FSO register value, the slave primary frame sync intervals. Then, after (B register value/2)
FCLK periods, the master secondary frame sync occurs first, and then the slave secondary frame sync
occurs. These are also rippled through the slave devices.
In other words,when a secondary communications interval is requested by the host processor as described
above:
1.

The master outputs the master primary frame sync interval, and then the slave primary frame
sync intervals after the FSD register value number of shift clocks.

2.

After (B register value/2) FCLK periods, the master then outputs the master secondary frame
sync interval, and after the FSO register value number of shift clocks, the slave secondary frame
sync intervals.

This sequence is shown in Figure 2-2.
The host must keep track of whether the master or a slave is then being addressed and also the number
of slave devices. The master always outputs a 00 in the last 2 bits of the DOUT word, and a slave always
outputs a 1 in the LSB of the DOUT word. This information allows the system to recognize a starting point
by interrogating the least significant bit of the DOUT word. If the LSB is 0, then that device is the master,
and the system is at the starting point.
Note: This identification always happens except in 16-bit mode when the 2 LSBs are not available
for identification purposes.
11411111f-------------___..+I- (8 Register Value/2) FCLK Periods
I

1

1II1I

Sampling Period

.1

FSD Value 1II1I
in SCLKs---1It--~1
1

I

Frame Sync
Sequence
Period Symbol

MP

SP1

SP2

SPn

MS

SS1

SS2

SSn

Periods shown: Each period must be a minimum of 16 SCLKs plus 2 additional SCLKs
MP
SP1
SP2
SPn

= Master Primary Period
= 1st Slave Primary Period
= 2nd Slave Primary Period

= nth Slave Primary Period

MS
SS1
SS2
SSn

= Master Secondary Period
= 1st Slave Secondary Period
= 2nd Slave Secondary Period
= nth Slave Secondary Period

Figure 2-2. Timing Sequence
4-294

MP

2.8.2

Notes on TLC320AC01/02 AIC Master-Slave Operation

Master/slave operational detail is summarized in the following notes:

1.

The slave devices can be programmed independently of the master as long as the clock divide
register numbers are not changed. The gain settings, for example, can be changed
independently.

2.

The method that is used to program a slave independently is to request a secondary
communication of the master and all slaves and ripple the delayed frame sync to the desired slave
device to be programmed.

3.

Secondary frame syncs must be requested for all devices in the system or none. This is required
so that the master generates secondary frames for the slaves and allows the slaves to know that
the second frame syncs they receive are secondary frame syncs. Each device in the system must
receive a secondary frame request in its corresponding primary frame sync period (11 in the last
2 LS8s).

4.

Calculation of the sampling frequency in terms of the master clock and the shift clock and the
respective register ratios is (see equations 4-6):
.
FCLK
Sampling frequency = fs = 8
. t
I
regis er va ue
f(MCLK)

2 (A register value) x (8 register value)

(4)

Therefore,

f(M~LK)
s

= 2

x (A register value) x (8 register value)

(5)

and in terms of the shift clock frequency, since
f(MCLK) = 4 x f(SCLK)
then
f(SCLK)

(A register value) x (8 register value)

fs

2
Number of SCLK periods
Sampling period

5.

(6)

The minimum number of shift clocks between falling edges of any two frame syncs is 18 because
the frame sync delay register minimum number is 18.
When a secondary communication is requested by the host, the master secondary frame sync
begins at the middle of the sampling period (followed by the slave secondary frame syncs), so all
primary frame sync intervals (master and slave) must occur within one-half the sampling time.

4-295

The first secondary frame-sync falling edge, therefore, occurs at the following time (see
equation 7):
.
.
.
B register value
Time to first secondary frame sync =
2
(FCLK penods) =
A register value x B register value (number of MCLK periods) =
A register value x B register value
4
(number of SCLK periods)
6.

(7)

Number of frame sync intervals Lising equation 8.
All master and slave primary frame sync intervals must occur within the time of equation 7.
Since 18 shift Clocks are required for each frame sync interval, then the number of frame sync
intervals from equation 8 is:
.
A register value x B register value
Number of frame sync mtervals = 4 x 18 (SCLKs/frame sync interval)
A register value x B register value
72

7.

Number of devices, master and slave, in terms of f(MCLK) and fs.
Substituting the value from equation5 for the A x B register value product gives the total number
of devices, including the master and' all slaves that can be used, for a given master clock and
sampling frequency. Therefore, using equation 9:
.
Number of devices

8.

=

f(MCLK)
144 x fs

(9)

Number of devices, master and slave, if slave devices are reprogrammed.
Equation 9!does not include reprogramming the slave devices after the frame sync delay occurs.
So if programming is required after shifting the slave frame syncs by the FSD register, then the
total number of devices is given by equation 10 is:
.
_ f(MCLK)
Number of devices - 288 x fs

9.

Example of the maximum number of devices if the slave devices are reprogrammed assuming
the following values:

f(MCLK) = 10.368 MHz, f5

=

8 kHz

then from equation 10,
Maximum n'umber of devices = 10.368 MHz = 4 5
288 (8 kHz)
.
therefore, one master and three slaves can be used.

4-296

(10)

2.9

Operating Frequencies

2.9.1

Master and Stand-Alone Operating Frequencies

The sampling (conversion) frequency is derived from the master-clock (MCLK) input by equation 11:
fs

=

Sampling (conversion) frequency

=

(A register value)

~~~Kregister

value) x 2 (11)

The inverse is the time between the falling edges of two successive primary frame-synchronization signals.
The input and output data clock (SCLK) frequency is given in equation 12:
SCLK f requency = MCLK frequency
4

2.9.2

(12)

Slave and Codec Operating Frequencies

The slave operating frequencies are either the default values or programmed by the control data word from
the master and codec conversion and the data frequencies are determined by the externally applied SCLK
and FS signals.

2.10 Switched-Capacitor Filter Frequency (FCLK)
The filter clock (FCLK) is an internal clock signal that determines the filter band-pass frequency and is the
B counter clock. The frequency of the filter clock is derived by equation 13:
FCLK

=

MCLK
(A register value) x 2

(13)

2.11 Filter Bandwidths
The low-pass (LP) filter -3 dB corner is derived in equation 14:
f (LP)

=

FCLK
40

=

MCLK
40 x (A register value) x 2

(14)

The high-pass (HP) filter -3 dB corner is derived in equation 15:
f (HP)

=

Sampling frequency
200

=

MCLK
200 x 2 x (A register value) x (B register value)

(15)

2.12 Master and Stand-Alone Modes
The difference between the master and stand-alone modes is that in the stand-alone mode there are no
slave devices. Functionally these two modes are the same. In both, the AIC internally generates the shift
clock and frame-sync signal for the serial communications. These signals and tl;le filter clock (FCLK) are
derived from the input master clock.The master clock applied at the MCLK input determines the internal
device timing. The shift clock frequency is a divide-by-four of the master clock frequency and shifts both the
input and output data at DIN and DOUT, respectively, during the frame-sync interval (16 shift clocks long).
To begin the communication sequence, the device is reset (see Section 2.2.1), and the first frame sync
occurs approximately 648 master clocks after the reset condition disappears.

2.12.1

Register Programming

All register programming occurs during secondary communications, and data is latched and valid on the
sixteenth falling edge of SCLK. After a reset condition, eight primary and secondary communications cycles
are required to set up the eight programmable registers. Registers 1 through 8 are programmed in
secondary communications intervals 1 through 8, respectively. If the default value for a particular register
is desired, that register does not need to be addressed during the secondary communications. The no-op
command addresses the pseudo-register (register 0), and no register programming takes place during this
communications. The no-op command allows phase shifts of the sampling period without reprogramming
any register.
During the eight register programming cycles, DOUT is in the high-impedance state. DOUT is released on
the rising edge of the eighth primary internal frame-sync interval. In addition, each register can be read back

4-297

during DOUT secondary communications by setting the read bit to 1 in the appropriate register. Since the
register is in the read mode, no data can be written to the register during this cycle. To return this register
to the write mode requires a subsequent secondary communication (see Section 2.19 for detailed register
description).
.

2.12.2

Master and Stand-Alone Functional Sequence

The A counter counts according to the contents of the A register, and the A counter frequency is divided by
two to produce the filter clock (FCLK). The B counter is clocked by FCLK with the following functional
sequence:
1.

The B counter starts counting down from the B register value minus one. Each count remains in
the counter for one FCLK period including the zero count. This total counter time is referred to
as the B cycle. The end of the zero count is called the end of B cycle.

2.

When the B counter gets to a count of nine, the analog-to-digital (A-to-D) conversion starts.

3.

The A-to-D conversion is complete ten FCLK periods later.

4.

FS goes low on a riSing edge of SCLK after the A-to-D conversion is complete. That rising edge
of SCLK must be preceded by a falling edge of SCLK, which is the first falling edge to occur after
the end of B cycle.

5.

The D-to-A conversion cycle begins on the rising edge of the internal frame-sync interval and is
complete ten FCLK periods later.

2.13 Slave and Codec Modes
The only difference between the slave and codec modes is that the codec mode is controlled directly by the
host and does not use a delayed frame-sync signal. In both modes, the shift clock and the frame sync are
both externally generated and must be synchronous with MCLK. The conversion frequency is set by the time
interval of externally applied frame-sync falling edges except when the free-run function is selected by bit 5
of register 6 (see Section 2.15.4). The slave device or devices share the shift clock generated by the master
device but receive the frame sync from the previous slave in the chain. The Nth slave FS receives the
(N-1 }st slave FSD output and so on. The first slave device in the chain receives FSD from the master.

4-298

2.13.1

Slave and Codec Functional Sequence

The A counter counts according to the contents of the A register, and the A counter frequency is divided by
two to produce the FCLK. The device function in the slave or codec mode is the same as steps 1 through
3 of the B cycle description in the master mode but differs as follows:
1.

Same as master

2.

Same as master

3.

Same as master

4.

All internal clocks stop 1/2 FCLK before the end of count 0 in the B counter cycle.

5.

All internal clocks are restarted on the first rising edge of MCLK after the external FS input goes
low. This operation provides the synchronization necessary when using an external FS signal.

6.

The D-to-A conversion starts on the rising edge of the internally generated frame-sync interval
at the end of the 16-shift clock data transfer.

In the slave mode, the master controls the phase adjustments for itself and all slaves since all devices are
programmed in the same frame-sync interval. In the codec mode, the shift clock and frame sync are
externally generated and provide the timing for the ADC and DAC if the free-run function has not been
selected (see Subsection 2.15.4). In the codec mode, there is usually no need for phase adjustments;
however, any required phase adjustments must be made by adjusting the external frame-sync timing
(sampling time).

2.13.2

Slave Register Programming

When slave devices are used on power-up or reset, all slave frame-sync signals occur at the same time as
the master frame-sync signal and all slave devices are programmed during the master secondary framesync interval with the same data as the master. The last register programmed must be the frame-sync delay
(FSD) register because the delay starts immediately on the rising edge of the seventeenth shift clock of that
frame- sync interval. After the FSD register programming is completed for the master and slave, the slave
primary frame interval is shifted in time (time slot allocated) according to the data contained in the slave FSD
registers. The master then generates frame-sync intervals for itself and each slave to synchronize the host
serial port for data transfers for itself and all slave devices.
The number of slaves is specified in the FSN register (register 8); therefore, the number of frame-sync
intervals generated by the master is equal to the number of slaves plus one (see Section 2.7). These master
frame-sync intervals are separated in time by the delay time specified by the FSD register (register 7). These
master-generated intervals are the only frame-sync interval signals applied to the host serial port to provide
the data-transfer time slot for the slave devices.

2.14 Terminal Functions
2.14.1

Frame-Sync Function

The frame-sync signal indicates that the device is ready to send and receive data for both master and slave
modes. The data transfer begins on the falling edge of the frame-sync signal.

2.14.1.1 Frame Sync (FS), Master Mode
The frame sync is generated internally. FS goes low on the rising edge of SCLK and remains low for the
16-bit data transfer. In addition to generating its own frame-sync interval, the master also outputs a frame
. sync for each slave that is being used.

4-299

2.14.1.2 Frame-Sync Delayed (FSD), Master Mode
For the master, the frame-sync delayed output occurs 1/2 shift-clock period ahead of FS to compensate for
the time delay through the master and slave devices. The timing relationships are as follows:
1.

When the FSD register data is 0, then FSD goes low on the falling edge of SCLK prior to the rising
edge of SCLK when FS goes low (see Figure 4-4).

2.

When the FSD register data is greater than 17, then FSD goes low on a rising edge of SCLK that
is the FSD register number of SCLKs after the falling edge of FS.

Register data values from 1 to 17 should not be used.
2.14.1.3 Frame Sync (FS), Slave Mode
The frame-sync timing is generated externally, applied to FS, and controls the ADC and DAC timing (see
Subsection 2.15.4). The external frame-sync width must be a minimum of one shift clock to be recognized
and can remain low until the next data frame is required.
2.14.1.4 Frame-Sync Delayed (FSD); Slave Mode
This output is fed from the master to the first slave and the first slave FSD output to the second and so on
down the chain. The FSD timing sequence in the slave mode is as follows:
1.

When the FSD register data is 0, then FSD goes low after FS goes low (see Figure 4-5).

2.

When the FSD register data is greater than 17, FSD goes low on a rising edge of SCLK that is
the FSD register number of SCLKs after the falling edge of FS.

Data values from 1 to 17 should not be used.

2.14.2

Data Out (DOUT)

DOUT is placed in the high-impedance state on the seventeenth rising edge of SCLK (internal or external)
after the falling edge of frame sync. In the primary communication, the data word is the ADC conversion
result. In the secondary communication, the data is the register read results when requested by the
read/write (R/W) bit with the eight MSBs set to 0 (see Section 2.16). If.no register read is requested, the
secondary word is all zeroes.
2.14.2.1 Data Out, Master Mode
In the master mode, DOUT is taken from the high-impedance state by the falling edge of frame sync. The
most significant data bit then appears on DOUT.
2.14.2.2 Data Out, Slave Mode
In the slave mode, DOUT is taken from the high-impedance state by the falling edge of the external frame
sync or the rising edge of the external SCLK, whichever occurs first (see Figure 4-7). The falling edge of
frame sync can occur ±1/4 SCLK period around the SCLK rising edge (see Figure 4-3). The most
significant data bit then appears on DOUT.

2.14.3

Data In (DIN)

In the primary communication, the data word is the digital input signal to the DAC channel. In the secondary
communication, the data is the control and configuration data to set up the device for a particular function
(see Section 2.16).

2.14.4

Hardware Program Terminals (FC1 and FCO)

These inputs provide for hardware programming requests for secondary communication or phase
adjustment. These inputs work in conjunction with the control bits D01 and DOO of the primary data word
or control bits DS15 and DS14 of the secondary data word. The data on FC1 and FCO are latched on the
rising edge of the next internally generated primary or secondary frame-sync interval. These inputs should
be tied low if not used (see Section 2.17 and Table 2-3).

4-300

2.14.5

Midpoint Voltages (A DC VMIO and DAC VMIO)

Since the device operates at a single-supply voltage, two midpoint voltages are generated for internal signal
processing. AOC VMID is used for the AOC channel reference, and OAC VMID is used for the OAC channel
reference. Two references minimize channel-to-channel noise and crosstalk. AOC VMID and OAC VMID
must be buffered when used as a reference for external signal processing.

2.15 Device Functions
2.15.1

Phase Adjustment

In some applications, such as modems, the device sampling period may require an adjustment to
synchronize with the incoming bit stream to improve the signal-to-noise ratio. The TLC320AC02 can adjust
the sampling period through the use of the A' register and the control bits.

2.15.1.1 Phase-Adjustment Control
A phase adjustment is a programmed variation in the sampling period. A sampling period is adjusted
according to the data value in the A' register, and the phase adjustment is that number of master clocks
(MCLK). An adjustment is made during device operation with data bits 001 and 000 in the primary
communication, with data bits OS15 and OS14 in the secondary word or in combination with the hardware
terminals FC1 and FCO (see Table 2-3). This adjustment request is latched on the rising edge of the next
internal frame-sync interval and is only valid for the next sampling period. To repeat the phase adjustment,
another phase request must be initiated.

2.15.1.2 Use of the A' Register for Phase Adjustment
The A' register value makes slight timing adjustments to the sampling period. The sampling period
increases or decreases according to the sign of the programmed A' register value and the state of data bits
001 and 000 in the primary data word.
The general equation for the conversion frequency is given in equation 16:
f = conversion frequency =
MCLK
(16)
(2 x A register value x B register value) ± (A' register value)
s
Therefore, if A' = 0, the device conversion (sampling) frequency and period is constant.
If a nonzero A' value is programmed, the sampling frequency and period responds as shown in Table 2-2.

Table 2-2. Sampling Variation With A'
SIGN OF THE A' REGISTER VALUE

001

000

PLUS VALUE
(+)

NEGATIVE VALUE

0

1
(increase command)

Frequency decreases,
period increases

Frequency increases,
period decreases

0

Frequency increases,
period decreases

, Frequency decreases,
period increases

1

(decrease command)

H

An adjustment to the sampling period, which must be requested through 001 and 000 of the primary data
word to DIN, is valid for the following sampling period only. When the adjustment is required for the
subsequent sampling period, it must be requested again through 001 and 000 of the primary data word.'
For each request, only the sampling period occurring immediately after the primary data word request is
affected.

4-301

The amount of time shift in the entire sampling period (1/fs) is as follows:
When the sampling period is set to 125 !ls (8 kHz), the A' register is loaded with decimal 10 and the
TLC320AC02 master clock frequency is 10.386 MHz. The amount of time each sampling period is increased
or decreased, when requested, is given in equation 17:
Time shift = (A' register value) x (MCLK period)

(17)

The device changes the entire sampling period by only the MCLK period times the A' register value as given
in equation 18:
Change in sampling period = contents of A' register x master clock period
= 10 x 96.45 ns = 964 ns (less than 1% of the sampling period)

(18)

The sampling period changes by 964.5 ns each time the phase adjustment is requested by the primary data
word (Le., once per sampling period).
It is evident then that the change in sampling period is very small compared to the sampling period. To
observe this effect over a long period of time (> sampling period), this change must be continuously
requested by the primary data word. If the adjustment is not requested again, the sampling period changes
only once and it may appear that there was no execution of the command. This is especially true when bench
testing the device. Automatic test equipment can test for results within a single sampling period.
Internally, theA' register value only affects one cycle (period) of the A counter. The A and A' values are
additive, but only for one A-counter period. The A counter begins the first count at the default or programmed
A-register value and counts down to the A'-register value. As the A' value increases or decreases, the first
clock cycle from the A counter is lengthened or shortened. The initial A-counter period is the only counter
period affected by the A' register such that only this single period is increased or decreased.

2.15.2

Analog Loopback

This function allows the circuit to be tested remotely. In loopback, OUT+ and OUT-are internally connected
to IN + and IN-. The OAC data bits 015 to 002 that are applied to DIN can be compared with the AOC output
data bits 015 to 002 at OOUT. There are some differences due to the AOC and OAC channel offset. The
loopback function is implemented by setting OS01 and OSOO to zero in control register 5 (see Section 2.19).
When analog loopback is enabled, the external inputs to IN+ and IN- are disconnected, but the signals at
OUT+ and OUT- may still be read.

2.15.3

16-Bit Mode

In the 16-bit mode, the device ignores the last two control bits. (001 and 000) of the primary word and
requests continual secondary communications to occur. By ignoring the last two primary communication
bits, compatibility with existing 16-bit software can be maintained. This function is implemented by setting
bit DS03 to 1 in register 6. To return to normal operation, OS03 must be reprogrammed to O.

2.15.4

Free-Run Mode

With the free-run bit set in register 6, the external shift clock and frame sync control only the data transfer.
The AOC and OAC timing are controlled by the A and B register values, and the phase-shift adjustment must
be done as if the device is in stand-alone mode (by the software or the state of FC1 and FCO).
Phase adjustment cannot be made by adjustment of the frame-sync timing. The external frame sync must
occur within 1/2 FCLK period of the internal frame sync (FCLK as determined by the values of the A and
B registers).
When the external frame sync occurs simultaneously with the internal load, the data-transfer request by the
external frame sync takes precedence over an internal load command. The latching of the AOC conversion
data in the output register is inhibited until the current 16 bits are shifted out of the register by the shift clock.

2.15.5

Force Secondary Communication

With bit 2 in register 6 set to 1, secondary communication is requested continuously. It overrides all software
and hardware requests concerning secondary communication. Phase shifting, however, can still be
performed with the software and hardware.

4-302

2.15.6

Enable Analog Input Summing

By setting bits OS01 and OSOO to 11 in register 5, the normal analog input voltage is summed with the
auxiliary input voltage. The gain for the analog input amplifier is set by data bits OS03 and OS02 in register 4.

2.15.7

DAC Channel (sin x)/x Error Correction

The (sin x)/x compensation filter is designed for zero (sin x)/x error using a B-register value of 15. Since the
filter cannot be removed from the signal path, operation using another B-register value results in an error
in the reconstructed analog output. The error is given by equation 19. Any error compensation needed by
a given application can be performed in the software.
sin ( 2Jt x A x B x f)
f MCLK
OAC channel frequency response error = 20 x 10910 - - - ' - - - - - - - ' - x 1§.
sin

(~~~~:

x f)

(19)

B

where:
f
fMCLK
A
B

=
=
=
=

the
the
the
the

frequency of interest
TLC320AC02 master-ciock frequency
A-register value
B-register value

and the arguments of the sin functions are in radians.

2.16 Serial Communications
2.16.1 Stand-Alone and Master-Mode Word Sequence and Information Content During
Primary and Secondary Communications
For the stand-alone and master modes, the sequence in Figure 2-2 shows the relationship between the
primary and secondary communications interval, the data content into DIN, and the data content from
OOUT.
The TLC320AC02 can provide a phase-shift command or the next secondary communications interval by
decoding 1) the programmed state of the FC1 and FCO inputs and the 001 and 000 data bits in the primary
data word, or 2) the state of the FC1 and FCO inputs and the OS15 and OS14 data bits in the secondary
data word (see Table 2-3). When OS13 (the RIW bit) is the default value of 0, all 16 bits from OOUT are
o during secondary communication. However, when the R/W bit is set to 1 in the secondary communication
control word, the secondary transmission from OOUT still contains Os in the eight MSBs. The lower order
8 bits contain the data of the register currently being addressed. This function provides register status
information for the host.

4-303

1---- [

1:.....

(B register)/2] FCLK Periodst - - -•• 1

I

t

I
Primary Frame Sync
(16 SCLKs long)

Secondary Frame Sync
(16 SCLKs long)

2s-Complement ADC Output
(14 bits plus 00 for the two LSBs)

16 Bits All Os, Except When in
Read Mode (then least significant
8 bits are register data)

2s-Complement Input for the DAC
Channel (14 bits plus two
function bits). If the 2 LSBs Are
Set to 1, Secondary Frame Sync Is
Generated by the TLC320AC02

Input Data for the Internal Registers
(16 bits containing control,
address, and data information)

I
I

The time between the primary and secondary frame sync is the time equal to filter clock (FCLK) period multiplied by the
8-register contents divided by two. The time interval is rounded to the nearest shift clock. The secondary frame-sync
signal goes from high to Iowan the next shift clock low-to-high transition after (8 register/2) filter clock periods.

Figure 2-3. Master and Stand-Alone Functional Sequence

2.16.2 Slave and Codec-Mode Word Sequence and Information Content During
Primary and Secondary Communications
For the slave and codec modes, the sequence is basically the same as the stand-alone and master modes
with the exception that the frame sync and the shift clock are generated and controlled externally as shown
in Figure 2-3. For the codec mode, the frame-sync pulse width needs to be a minimum of one shift clock
long. The timing relationship between the frame sync and shift clock is shown in the timing diagrams. Phase
shifting is usually not required in the slave or codec mode because the frame-sync timing can be adjusted
externally if required .

....../

/+--

1 SCLK Minimum

Fill _f_f_E_t_J_J
Primary Frame Sync

~ 1 SCLK Minimum

L1_1_J_J_J_J_J
Secondary Frame Sync

16 Bits, All Os, Except When in
2s-Complement ADC Output
(14 bits plus 00 for the 2 LSBs in ' - - - - - -.... Read Mode (then least significant
8 bits are register data)
master and stand-alone mode and
01 in slave mode)

DOUT

DIN

~

Input Data for the Internal
2s-Complement Input for the DAC
'--_ _ _ _.... Registers (16 bits containing
Channel (14 bits plus two
I control, address, and data
I function bits)
I information)

I

NOTE A: The time between the primary and secondary frame syncs is determined by the application; however, enough
time must be provided so that the host can execute the required number of software instructions in the time
between the end of the primary data transfer (rising edge of the primary frame-sync interval) and the falling
edge of the secondary frame sync (start of secondary communications).

Figure 2-4. Slave and Co dec Functional Sequence

4-304

2.17 Request for Secondary Serial Communication and Phase Shift
The following paragraphs describe a request for secondary serial communication and phase shift using
hardware control inputs FC1 and FCO, primary data bits 001 and 000, and secondary data bits 0815 and
0814.

2.17.1

Initiating a Request

Combinations of FC1 and FCO input conditions, bits 001 and 000 in the primary serial data word, FC1 and
FCO, and bits 0815 and 0814 in the secondary serial data word can initiate a secondary serial
communication or request a phase shift according to the following rules (see Table 2-3).
1.

Primary word phase shifts can be requested by either the hardware or software when the other
set of signals are 11 or 00. If both hardware and software request phase shifts, the software
request is performed.

2.

8econdary words can be requested by either the software or hardware at the same time that the
other set of signals is requesting a phase shift.

3.

Hardware inputs FC1 and FCO are ignored during the secondary word unless 0815 and 0814
are 11. When 0815 and 0814 are 01 or 10, the corresponding phase shift is performed. When
0815 and 0814 are 00, no phase shift is performed even when the hardware requests a phase
shift.

2.17.2

Normal Combinations of Control

The normal combinations of control are as follows:
1.

Use 001 and 000 and 0815 and 0814 to request phase shifts and secondary words by holding
FC1 and FCO to 00.

2.

Use FC1 and FCO exclusively to request phase shifts and secondary words by holding 001 and
000 to 00 and 0815 and 0814 to 11.

3.

Use 001 and 000 only to request secondary words and FC1 and FCO to perform phase shifts
once per period by holding 0815 and 0814 to 00.

2.17.3

Additional Control Options

Additional control options are unusual and are rarely needed or used; however, they are as follows:
1.

Use 001 and 000 only to request secondary words and FC1 and FCO to perform phase shifts
twice per period by holding 0815 and D8 14 to 11.

2.

Use FC1 and FCO exclusively to request secondary words and 001 and 000 and D815 and 0814
to perform phase shifts twice per periOd.

3.

Use FC1 and FCO to perform the phase shift after the primary word and 0815 and 0814 to
perform a phase shift after the secondary word by holding 001 and DOD to 11.

4-305

Table 2-3. Software and Hardware Requests for
Secondary Serial-Communication and Phase-Shift Truth Table
WITHIN PRIMARY
OR SECONDARY
DATA WORD

Primary

Secondary

CONTROL
BITS

HARDWARE
TERMINALS

PHASE-SHIFT
ADJUSTMENT
(see Section 2.15.1)

001

000

FC1

FCO

EARLIER

LATER

0
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

0
0
1
0

0
1
0
0

0
0
0
1

0
0
0
0

1
1
1
1

0
0
1
1

0
1
0
1

0
0
0
0

1
1
1
1

0
0
0
1

1
1
1
1

0
0
0
0

0
0
1
1

0
1
0
1

1
1
1

0
0
0
0

0
0
0
1

1
1
1
1

1
1
1
1

0
0
1
1

0
1
0
1

0
0
1
0

0
1
0
0

1
1
1
1

DS15

DS14

FC1

FCO

EARLIER

LATER

0
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

0
0
0
0

0
0
0
0

0
0
0
0

1
1
1
1

0
0
1
1

0
1
0
1

0
0
0
0

1
1
1
1

1
1
1
1

0
0
0
0

0
0
1
1

0
1
0
1

1
1
1
1

0
·0
0
0

1
1
1
1

1
1
1
1

0
0
1
1

0
1
0
1

0
0
1
0

0
1
0
0

1

SECONDARY
REQUEST
(see Note 1)

No request can be made for
secondary communication
within the secondary word.

NOTE 1: The 0 state indicates that a secondary communication is not being requested. The 1 state indicates that a
secondary communication is being requested.

2.18 Primary Serial Communications
Primary serial communications transfer the 14-bit DAC input plus two control bits (001 and 000) to DIN of
the TLC320AC02.They simultaneously transfer the 14-bit ADC conversion result from DOUT to the
processor. The 2 LSBs are set to 0 in the ADC result.

4-306

2.18.1

Primary Serial Communications Data Format

\·------------------------~V~------------------------/~
14-bit OAC Conversion Resu It
2s-Complement Formatt

Control Bits

t Since the supply voltage is single ended, the reference for 2s-complement format is AOC VMIO. Voltages above
this reference have a 0 as the MSB, and voltages below this reference have a 1 as the MSB.

During primary serial communications, when 001 and 000 are both high in the OAC data word to DIN, a
subsequent 16 bits of control information is received by the device at DIN during a secondary
serial-communication interval. This secondary serial-communication interval begins at 1/2 the programmed
conversion time when the B register data value is even or 112 the programmed value minus one FCLK when
the B register data value is odd. The time between primary and secondary serial communication is
measured from the falling edge of the primary frame sync to the falling edge of the secondary frame sync
(see 8ection 2.19 for function and format of control words).

2.18.2

Data Format From DOUT During Primary Serial Communications

~--------------------------~v~------------------------~

14-Bit AOC Conversion Result
2s-Complement Format
015 is the Sign Bit

2.19 Secondary Serial Communications
2.19.1

Data Format to DIN During Secondary Serial Communications

There are nine 16-bit configuration and control registers numbered from zero to eight. All register data
contents are represented in 2s-complement format. The general format of the commands during secondary
serial communications is as follows.
OS1510S14 OS13 OS1210S111 OS101 OS091 0S08 OS071 OS061 OS051 OS0410S031 OS021 OS011 OSOO
Control Bits
(2 bits)

R/W

Register Address
(5 bits)

Bit

Register Oata Value
(8 bits)

All control register words are latched in the register and valid on the sixteenth falling edge of 8CLK.

2.19.2

Control Data-Bit Function in Secondary Serial Communication

2.19.2.1 OS15 and OS14
In the secondary data word, bits 0815 and 0814 perform the same control function as the primary control
bits 001 and 000 do in the primary data word.
OS1510S14 OS13 OS121 OS111 OS10 1 os091 OS08
Control Bits

RIW

Register Address

os071 os061 os051 os041 os031 os021 os011 OSOo
Register Oata

Hardware terminals FC1 and FCO are valid inputs when 0815 and 0814 are both high, and they are ignored
for all other conditions.

4-307

0813 (R/W Bit)

2.19.2.2

Reset and power-up procedures set this bit to a 0, placing the device in the write mode. When this bit is set
to 1, however, the previous data content of the register being addressed is read out to the host from OOUT
as the least significant 8 bits of the 16-bit secondary word. The first 8 bits remain set to O. Reading the data
out is nondestructive, and the contents of the register remain unchanged.

A. Write Mode (0813 = 0)
Data In. The data word to DIN has the following general format in the write mode.
OS1510S14 OS13 OS121 OS111 OS10 1OS091 OS08
Control Bits

OS071 OS061 OS051 OS041 OS031 OS021 OS011 OSOO

Register Address

0

Register Oata

Data Out. The shift clock shifts out all Os as the pattern to the host from DOUT.
OS15 OS14 OS13 OS12 OS11 OS10
0

0

0

0

0

0

OS09 OS08
0

0

OS07 OS06 OS05 OS04 OS03 OS02 OS01 OSOO
0

0

0

0

0

0

0

0

B. Read Mode (0813 = 1)
Data In. The data word to DIN has the following format to allow a register read. Phase shifts can
also be done in the read mode.
OS1510S14 OS13 OS121 OS111 OS10 1OS091 OS08
Control Bits

1

OS071 OS061 OS051 OS041 OS031 OS021 OS011 OSOO
Ignored

Register Address

Data Out. The shift clock clocks out the data of the register addressed from DOUT in the read mode in
the 8 L8Bs.
OS15 OS14 OS13 OS12 OS11 OS10 OS09 OS08
0

0

0

0

0

0

0

OS071 OS061 OS051 OS041 OS031 OS021 OS011 OSOO
Register Oata

0

2.20 Internal Register Format
2.20.1

Pseudo-Register 0 (No-Op Address)

This address represents a no-operation command. No register I/O operation takes place, so the device can
receive secondary commands for phase adjustment without reprogramming any register. A read of the
no-op is o. The format of the command word is as follows:
OS1510S14 OS13 OS12 OS11 OS10 OS09 OS08
Control Bits

2.20.2

X

0

0

0

0

0

OS07 OS06 OS05 OS04 OS03 OS02 OS01 OSOO

X

X

X

X

X

X

X

X

Register 1 (A Register)

The following command loads D807 (M8B) - D800 into the A register.
OS1510S14 OS13 OS12 OS11 OS10 OS09 OS08
Control Bits

R/W

0

0

0

0

OS07\ OS061 OS051 OS041 OS031 OS021 OS011 OSOO

1

Register Oata

The data in 0807 - D800 determines the division of the master clock to produce the internal FCLK.
FCLK frequency = MCLKJ(A register contents x 2)

4-308

The default value of the A-register data is decimal 18 as shown below.

2.20.3

OS07

OS06

0

0

OS05 OS04 OS03 OS02 OS01 OSOO
0

1

0

0

1

0

Register 2 (8 Register)

The following command loads 0807 (M8B) - 0800 into the B register.
OS1510S14 OS13 OS12
Control Bits

-

R/W

0

OS11

OS10

0

0

OS09 OS08 OS071 OS061 OS051 OS041 OS031 OS021 OS011 OSOO
1

Register Oata

0

The data in 0807 - 0800 controls the division of FCLK to generate the conversion clock as given in
equation 20:
Conversion frequency

= FCLK/(B register contents)

MCLK
2 x A register contents x B register contents

(20)

The default value of the B-register data is decimal 18 as shown below.
OS07 OS06
0

2.20.4

0

OS05 OS04 OS03 OS02 OS01 OSOO
0

1

0

0

1

0

Register 3 (A' Register)

The following command contains the A'-register address and loads 0807(M8B) - D800 into the A' register.
OS1510S14 OS13 OS12
Control Bits

R/W

0

OS11

OS10

0

0

OS09 OS08
1

OS071 OS061 OS051 OS041 OS031 OS021 OS01 1OSOO
Register Oata

'1

The data in 0807 - D800 is in 2s-complement format and controls the number of master-clock periods that
the sampling time is shifted.
The default value of the A'-register data is 0 as shown below.
OS07
0

OS06 OS05 OS04 OS03 OS02 OS01 OSOO

0

0

0

0

0

0

0

4-309

2.20.5

Register 4 (Amplifier Gain-Select Register)

The following command contains the amplifier gain-select register address with selection code for the
monitor output. ,(0805-0804), analog input (0803-0802), and analog output (0801-0800)
programmable gains.
OS11 OS10

OS1510S14 OS13 OS12

Control Bits

RIW

Monitor output gain
Monitor output gain
Monitor output gain
Monitor output gain

0

0

1

OS09 OS08 OS07 OS06
0

0

X

X

input gain
input gain
input gain
input gain

Analog
Analog
Analog
Analog

output gain
output gain
output gain
output gain

*

••
••

= squelch
= 0 dB
= -8 dB
= -18 dB

= squelch
= 0 dB
= 6 dB

Analog
Analog
Analog
Analog

OS05 OS04 OS03 OS02 OS01 OSOO

*

0
0
1
1

*

*

*

*

0
1
0
1

••
•
•

12 dB

= squelch
= 0 dB
= -6 dB

0
0
1
1

0
1
0
1

••
••

12 dB

0
0
1
1

0
1
0
1

The default value of the monitor output gain is squelch, which corresponds to data bits 0805 and 0804 equal
to 00 (binary).
The default value of the analog input gain is 0 dB, which corresponds to data bits 0803 and 0802 equal
to 01 (binary).
The default value of the analog output gain is 0 dB, which corresponds to data bits 0801 and 0800 equal
to 01 (binary).
The default data value is shown below.
OS07
0

2.20.6

OS06 OS05 OS04 OS03 OS02 OS01 OSOO
0

0

0

0

1

0

1

Register 5 (Analog Configuration Register)

The following command loads the analog configuration register with the individual bit functions described
below.
OS1510814 0813 OS12

Control Bits

RIW

OS11 0810

0

0

1

OS09 0808
0

1

Must be set to 0
High-pass filter disabled
High-pass filter enabled
Analog loopback enabled
Enables IN+ and IN- (disables AUXIN+ and AUXIN-)
Enables AUXIN+ and AUXIN- (disables IN+ and IN-)
Enable analog input summing

0807 OS06 0805 OS04 0803 0802 0801 OSOO

X

X

X

X

•

*

*

*

*

0

0

0

••

1
0

••
•
•

0

1

1

0

1

1

The default value of the high-pass-filter enable bit is 0, which places the high-pass filter in the signal path.
The default values 010801 and 0800 are 0 and 1 which enables IN+ and IN-.

4-310

The power-up and reset conditions are as shown below.
OS03
0

OS02 OS01 OSOO
0

1

0

In the read mode, eight bits are read but the 4 L8Bs are repeated as the 4 M8Bs.

2.20.7

Register 6 (Digital Configuration Register)

The following command loads the digital configuration register with the individual bit functions described
below.
OS15J OS14 OS13 OS12
Control Bits

-

R/W

OS11

OS10

0

1

0

OS09 OS08
1

OS07 OS06 OS05 OS04 OS03 OS02 OS01 OSOO

X

0

X

••

AOC and OAC conversion free run
Inactive
FSO output disable
Enable

*

*

*

*

*

*

1
0

••
••
••
1

0

16-Bit mode, ignore primary LSBs
Normal operation

1
0

Force secondary communications
Normal operation
Software reset
(upon reset, this bit is automatically reset to 0)
Inactive reset

1
0

•
• •
•
1

0

Software power-down active (automatically reset to 0
after PWR OWN is cycled high to low and back to high)
Power-down function external
(uses PWR OWN)

1
0

The default value of 0807-0800 is 0 as shown below.

2.20.8

OS07

OS06

0

0

OS05 OS04 OS03 OS02 OS01 OSOO
0

0

0

0

0

0

Register 7 (Frame-Sync Delay Register)

The following command contains the frame-sync delay (F80) register address and loads 0807
(M8B)-0800 into the F80 register. The data byte (0801-0800) determines the number of 8CLKs
between F8 and the delayed frame-sync signal, F80. The minimum data value for this register is
decimal 18.
OS1510S14 OS13 OS12
-

Control Bits RIW

0

OS11

OS10

0

1

OS09 OS08
1

OS071 OS061 OS051 OS041 OS031 OS021 OS011 OSOO
Register Oata

1

The default value of 0807 - 0800 is 0 as shown below.
OS07 OS06 OS05 OS04 OS03 OS02 OS01 OSOO
0

0

0

0

0

0

0

0

When using a slave device, register 7 must be the last register programmed.
4-311

2.20.9

Register 8 (Frame-Sync Number Register)

The following command contains the frame-sync number (FSN) register address and loads OS07
{MS8)-OSOO into the FSN register. The data byte determines the nurnber of frame-sync signals generated
by the TLC320AC02. This number is equal to the number of slaves plus one.
051510514 0513 0512 0511

Control Bits RfW

0

1

0510 0509 0508 050710506105051050410503105021050110500
0

0

Register Oata

0

The default value of OS07-0S00 is 1 as shown below.
0507 0506 0505 0504 0503 0502 0501 0500
0

4--312

0

0

0

0

0

0

1

3
Specifications
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)t
Supply voltage range, DGTL Voo (see Notes 1 and 2) ............... -0.3 V to 6.5 V
Supply voltage range, DAC Voo (see Notes 1 and 2) ................ -0.3 V to 6.5 V
Supply voltage range, ADC Voo (see Notes 1 and 2) ................ -0.3 V to 6.5 V
Differential supply voltage range, DGTL Voo to DAC Voo ............ -0.3 V to 6.5 V
Differential supply voltage range, all positive supply voltages to
ADC GND, [jAC GND, DGTL GND, SUBS .................... -0.3 V to 6.5 V
Output voltage range, DOUT ......................... -0.3 V to DGTL Voo + 0.3 V
Input voltage range, DIN ............................. -0.3 V to DGTL Voo + 0.3 V
Ground voltage range, ADC GND, DAC GND,
DGTL GND, SUBS ............................ -0.3 V to DGTL Voo + 0.3 V
Operating free-air temperature range, TA ............................ O°C to 70°C
Storage temperature range, Tstg ................................. -40°C to 125°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds .............. 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for
extended periods may affect device reliability.

3.2

Recommended Operating Conditions (see Note 2)

VDD

Positive supply voltage

MIN

NOM

MAX

4.5

5

5.5
0.1

Steady-state differential voltage between any two supplies

UNIT
V
V
V

VIH

High-level digital input voltage

VIL

Low-level digital input voltage

0.8

V

10

Load output current from ADC VMID and DAC

100

~A

Conversion time for the ADC and DAC channels
fMCLK.

Master-clock frequency

VID(PP)

Analog input voltage (differential, peak to peak)

RL
TA
NOTES:

I Differential output load resistance
I Single-ended to buffered DAC VMID voltage load resistance
Operating free-air temperature

2.2

10 FCLK periods
10.368

15

6

V

600

Q

300
0

MHz

70

°C

1. Voltage values for DGTL VDD are with respect to DGTL GND, voltage values for DAC VDD are with respect
to DAC GND, and voltage values for ADC VDD are with respect to ADC GND. For the subsequent electrical,
operating, and timing specifications, the symbol VDD denotes all positive supplies. DAC GND, ADC GND,
DGTL GND, and SUBS are at 0 V unless otherwise specified.
2. To avoid possible damage to these CMOS devices and associated operating parameters, the sequence
below should be followed when applying power:
(1) Connect SUBS, DGTL GND, ADC GND, and DAC GND to ground.
(2) Connect voltages ADC VDD,and DAC VDD.
(3) Connect voltage DGTL VDD.
(4) Connect the input signals.
When removing power, follow the steps above in reverse order.

4-313

3.3

Electrical Characteristics Over Recommended Range of Operating·
Free-Air Temperature, MCLK 5.184 MHz, Voo 5 V, Outputs
Unloaded, Total Device

=

PARAMETER

TEST CONDITIONS

MIN

PWR OWN = 1 and clock signals
present

Supply
current

100

=

UNIT

20

22

rnA

1

2

rnA

Power
dissipation

100

rnW

PWR OWN = 0 after 500 Jls and
clock signals present

5

rnW

Software power down, (bit 000,
register 6 set to 1)

15

20

rnW

AOCVMIO

Midpoint
voltage

No load

AOC VOO/2
-0.1

AOC VOO/2
+0.1

V

OACVMIO

Midpoint
voltage

No load

OAC VOO/2
-0.1

OAC VOO/2
+0.1

V

3.4

Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, Voo 5 V, Digital 1/0 Terminals (DIN, DOUT, EOC,
FCC, FC1, FS, FSD, MCLK, MIS, SCLK)

=

PARAMETER

t

MAX

PWR OWN = 0 after 500 JlS and
clock signals present
PWR OWN = 1 and clock signals
present

Po

TYPt

TEST CONDITIONS

MIN

TYPt

MAX

2.4

UNIT

VOH

High-level output voltage

IOH =-1.6 rnA

VOL

Low-level output voltage

IOL= 1.6 rnA

V

IIH

High-level input current, any digital input

IlL

Low-level input current, any digital input

Ci

Input capacitance

5

pF

Co

Output capacitance

5

pF

0.4

V

VI = 2.2 V to OGTL VOO

10

JlA

VI = 0 V to 0.8 V

10

JlA

All typical values are at VOO = 5 V and TA = 25°C.

3.5
3.5.1

Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, Voo 5 V, ADC and DAC Channels

=

AOC Channel Filter Transfer Function, FCLK
PARAMETER

=144 kHz, fs =8 kHz

TEST CONDITIONS

MIN

fi = 200 Hz

Gain relative to gain at fi = 1020 Hz (see Note 3)

MAX

UNIT

-2_

fi = 50 Hz
-1.8

-0.2

fi = 300 Hz to 3 kHz

-0.15

0.2

fi = 3.3 kHz

-0.35

0.03

fi = 3.4 kHz

-1

-0.1

fi = 4 kHz

-14

fi;:: 4.6 kHz

-32

dB

NOTE 3: The differential analog input signals are sine waves at 6 V peak to peak. The reference gain is at 1020 Hz.

4-314

3.5.2

ADC Channel Input, Voo
Noted)

=5 V, Input Amplifier Gain =0 dB (Unless Otherwise

PARAMETER
VI(PP)

Peak-Io-peak inpul voltage (see Nole 4)
ADC converter offset error

CMRR

Common-mode rejection ratio at IN+, IN-,
AUX IN +, AUX IN- (see Note 5)

q

Input resistance at IN+, IN-, AUX IN+,
AUX IN-

TEST CONDITIONS

MIN

Differential
Band-pass filter selected

MAX

UNIT

3

V

6

V

10

DS03, DS02 = 0 in
register 4

Squelch

TYPt

Single-ended

30

mV

55

dB

100

kQ

60

dB

t All typical values are at VDD = 5 V and TA = 25°C.
NOTES: 4. The differential range corresponds to the full-scale digital output.
5. Common-mode rejection ratio is the ratio of the ADC converter offset error with no signal and the ADC
converter offset error with a common-mode nonzero signal applied to either IN + and IN- together or
AUX IN + and AUX IN- together.

3.5.3

ADC Channel Signal-to-Distortion Ratio, Voo
Otherwise Noted)
PARAMETER

ADC channel signal-todistortion ratio
(see Note 6)

TEST CONDITIONS

=5 V, f5 =8 kHz (Unless

Av = 0 dB

AV= 6 dB

MIN

MIN

MAX

MAX

AV = 12 dB
MIN

VI = -6 dB to -1 dB

64

-

VI =-12dBto-6dB

59

64

VI = -18 dB to -12 dB

56

59

64

VI = -24 dB to -18 dB

50

56

59

VI = -30 dB to -24 dB

44

50

56

MAX

UNIT

-

VI = -36 dB to -30 dB

38

44

50

VI = -42 dB to -36 dB

32

38

44

VI = -48 dB to -42 dB

26

32

38

dB

NOTE 6: The analog-input test signal is a 1020-Hz sine wave with 0 dB = 6 V peak to peak as the reference level for
the analog-input signal.

3.5.4

DAC Channel Filter Transfer Function, FCLK
PARAMETER

=144 kHz, f5 =9.6 kHz, Voo =5 V

TEST CONDITIONS

MIN

fi = 200 Hz
Gain relative to gain at fi = 1020 Hz (see Note 7)

MAX

UNIT

0.15

fi < 200 Hz
-0.5

0.2

fi = 300 Hz to 3 kHz

-0.15

0.2

fi = 3.3 kHz

-0.35

0.03

fi = 3.4 kHz

-1

-0.1

fi = 4 kHz

-14

fi;::: 4.6 kHz

-32

dB

NOTE 7: The input signal is the digital equivalent of a 1020-Hz sine wave (digital full scale = 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak.

4-315

3.5.5

DAC Channel Signal-to-Distortion Ratio, Voo = 5 V, fs = 8kHz (Unless
Otherwise Noted)
PARAMETER

TEST CONDITIONS

DAC channel signal-todistortion' ratio
(see Note 8)

AV = 0 dB
MIN

MAX

Av: =-6dB
MIN

MAX

AV=-12dB
MIN

Vo = -6 dB to 0 dB

64

-

-

VO=-12dBto-6dB

59

64

-

Vo = -18 dB to -12 dB

56

59

64

Vo =-24 dBto-18 dB

50

56

59

Vo = -30 dB to -24 dB

44

50

56

Vo = -36 dB to -30 dB

38

44

50

Vo = -42 dB to -36 dB

32

38

44

Vo = -48 dB to -42 dB

26

32

38

MAX

UNIT

dB

NOTE 8: The input signal, VI, is the digital equivalent of a 1020-Hz sine wave (full-scale analog output at full-scale digital
input = 0 dB). The nominal differential DAC channel output with this input condition is 6 V peak to peak. The
load impedance for the DAC output buffer is 600 Q from OUT + to OUT -.

3.5.6

System Distortion, Voo
Noted)
PARAMETER
Second harmonic

ADC channel
attenuation

=5 V, fs =8 kHz, FCLK =144 kHz (Unless Otherwise
TEST CONDITIONS

Second harmonic
DAC channel
attenuation

UNIT

82

77
82

64

Single-ended output
(see Note 10)
Differential output (see Note 10)

t

MAX

77
64

Single-ended output
(buffered DAC VMID)
(see Note 10)
Differential output (see Note 10)

Third harmonic and
higher harmonics

64

Single-ended input (see Note 9)
Differential input (see Note 9)

TYPt
82

Single-ended input (see Note 9)
Differential input (see Note 9)

Third harmonic and
higher harmonics·

MIN

dB

82

77
64

77

All typical values are at VDD = 5 V and TA = 25°C.
NOTES: 9. The input signal is a 1020-Hz sine wave for the ADC channel. Harmonic distortion is defined for an input
level of -1 dB.
10. The input Signal is the digital equivalent of a 1020-Hz sine wave (digital full scale = 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the
DAC output buffer is 600 Q from OUT + to OUT -. Harmonic distortion is specified for a signal input level
of 0 dB.

4-316

3.5.7

Noise, Low-Pass and Band-Pass Switched-Capacitor Filters Included,
Voo 5 V (Unless Otherwise Noted)

=

PARAMETER

TEST CONDITIONS
Inputs tied to ADC VMID,
1s = 8 kHz, FCLK = 144 kHz,
(see Note 11)

ADC idle-channel noise
Broad-band noise
DAC idle-channel
noise

MIN

DIN INPUT = 00000000000000,
1s = 8 kHz, FCLK = 144 kHz,
(see Note 12)

Noise (0 to 7.2 kHz)
Noise (0 to 3.6 kHz)

TYPt

MAX

180

300

180

300

180

300

180

300

UNIT

,IlVrms

t

All typical values are at VDD = 5 V and TA = 25°C.
NOTES: 11. The ADC channel noise is calculated by taking the RMS value of the digital output codes of the ADC
channel and converting to microvolts.
12. The DAC channel noise is measured differentially from OUT + to OUT-across 600 Q.

3.5.8

Absolute Gain Error, Voo

=5 V, f5 =8 kHz (Unless Otherwise Noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

ADC channel absolute gain error (see Note 13)

-1-dB input signal

TA = -40 - 85°C

±1

DAC channel absolute gain error (see Note 14)

O-dB input signal,
RL= 600 Q

TA = -40 - 85°C

±1

UNIT
dB

NOTES: 13. ADC absolute gain error is the variation in gain from the ideal gain over the specified input signal levels.
The gain is measured with a -1-dB, 1020-Hz sine wave. The -1-dB input signal allows for any positive gain
or offset error that may affect gain measurements at or close to O-dB input signal levels.
14. The DAC input signal is the digital equivalent of a 1020-Hz sine wave (full-scale analog output at digital fullscale input = 0 dB). The nominal differential DAC channel output voltage with this input condition is 6 V peak
to peak. The load impedance for the DAC output buffer is 600 Q from OUT + to OUT -.

3.5.9

Relative Gain and Dynamic Range, Voo
Noted)
PARAMETER

=5 V, f5 =8 kHz (Unless Otherwise

TEST CONDITIONS

MIN

MAX

ADC channel relative gain tracking error
(see Note 15)

-48-dB to -1-dB input signal range

±0.2

DAC channel relative gain tracking error
(see Note 16)

-48-dB to O-dB input signal range
RL(diff) = 600 Q

±0.2

UNIT

dB

NOTES: 15. ADC gain tracking is the ratio of the measured gain at one ADC channel input level to the gain measured
at any other input level. The ADC channel input is a -1-dB 1020-Hz sine wave input signal. A -1-dB input
signal allows for any positive gain or offset error that may affect gain measurements at or close to O-dB ADC
input signal levels.
16. DAC gain tracking is the ratio of the measured gain at one DAC channel digital input level to the gain
measured at any other input level. The DAC-channel input signal is the digital equivalent of a 1020-Hz sine
wave (digital full scale = 0 dB). The nominal differential DAC channel output voltage with this input condition
is 6 V peak to peak. The load impedance for the DAC output buffer is 600 Q from OUT + to OUT -.

4-317

3.5.10

Power~Supply

Rejection, Voo

=5 V (Unless Otherwise Noted) (see Note 17)

PARAMETER
ADCVDD

TEST CONDITIONS

Supply-voltage rejection ratio, ADC channel

DAC VDD

Supply-voltage rejection ratio, DAC channel

DGTL VDD

Supply-voltage rejection ratio, ADC channel

MIN

= 0 to 30 kHz
Ii = 30 to 50 kHz
Ii = 0 to 30 kHz
Ii = 30 to 50 kHz
Ii = 0 to 30 kHz
Ii = 30 to 50 kHz

Supply-voltage rejection ratio, DAC channel

Ii

UNIT

55

45
50
55

dB

40

= 30 to 50 kHz

45

Differential,
Ii = 0 to 30 kHz
Ii

MAX

40

Single ended,
Ii = 0 to 30 kHz
DGTL VDD

TYPt
50

Ii

40

= 30 to 50 kHz

45

t

All typical values are at VDD = 5 V and TA = 25°C.
NOTE 17: Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200-mV
peak-to-peak signal applied to the appropriate supply.

3.5.11

Crosstalk Attenuation, Voo
PARAMETER

ADC channel crosstalk attenuation

DAC channel crosstalk attenuation

t

=5 V (Unless Otherwise Noted)
TEST CONDITIONS

MIN

TYPt

DAC channel idle with
DIN = 00000000000000,
ADC input = 0 dB,
1020-Hz sine wave,
Gain = 0 dB (see Note 18)

80

ADC channel idle with INP, INM,
AUX IN+, and AUX IN- at ADC VMID

80

DAC channel input = digital equivalent
01 a 1020-Hz sine wave (see Note 19)

80

MAX

UNIT

dB

dB

All typical values are at VDD = 5 V and TA = 25°C.
NOTES: 18. The test signal is a 1020-Hz sine wave with a 0 dB = 6-V peak-to-peak relerence level lor the analog input
signal.
19. The input signal is the digital equivalent 01 a 1020-Hz sine wave (digital lull scale = 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak. The load impedance lor the
DAC output buffer is 600 Q Irom OUT + to OUT -.

4-318

3.5.12

Monitor Output Characteristics, Voo = 5 V (Unless Otherwise Noted)
(see Note 20)
PARAMETER

TEST CONDITIONS

MIN

TYPt

1.3

1.5

VO(PP)

Peak-to-peak ac output
voltage

Quiescent level = ADC VMID
ZL = 10 kQ and 60 pF

VOO

Output offset voltage

No load, single ended
relative to ADC VMID

VOC

Output common-mode voltage

No load

ro

DC output resistance

Voltage gain (see Note 21)

0.4ADC
VDD

0.5ADC
VDD

-0.2

0

10
0.6ADC
VDD

mV
V

n
0.2

Gain 2 =-8 dB

-8.2

-8

-7.8

Gain 3 = -18 dB

-18.4

-18

-17.6

Squelch (see Note 22)

UNIT
V

50
Gain = OdB

AV

5

MAX

dB

-60

t

All typical values are at VDD = 5 V and TA = 25°C.
NOTES: 20. All monitor output tests are performed with a 10-kQ load resistance.
21. Monitor gains are measured with a 1020-Hz, 6-V peak-to-peak sine wave applied differentially between
IN + and IN-.The monitor output gains are nominally 0 dB, -8 dB, and -18 dB relative to its input; however,
the output gains are -6 dB relative to IN+ and IN- or AUX IN+ and AUX IN-.
22. Squelch is measured differentially with respect to ADC VMID.

4-319

3.6

Timing Requirements and Specifications in Master Mode

3.6.1

Recommended Input Timing Requirements for Master Mode, Voo
MIN

NOM

=5 V
MAX

UNIT

tr(MCLKl

Master clock rise time

5

ns

tf(MCLKJ

Master clock fall time

5

ns

Master clock duty cycle

40%

tw(RESET)

RESET pulse duration

1 MCLK

tsu(DIN)

DIN setup time before SCLK low (see Figure 4-2)

th(DIN)

DIN hold time after SCLK low (see Figure 4-2)

3.6.2

60%

25

ns
20

ns

Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, Voo = 5 V (Unless Otherwise Noted) (see Note 23)
TYPt

MAX

tf(SCLK)

Shift clock fall time (see Figure 4-2)

13

18

ns

tr(SCLK)

Shift clock rise time (see Figure 4-2)

13

18

ns

PARAMETER

Shift clock duty cycle

MIN

45%

UNIT

55%

td(CH-FL)

Delay time from SCLK high to FSD low
(see Figures 4-2 and 4-4 and Note 24)

5

20

ns

1d(CH-FH)

Delay time from SCLK high to FS high (see Figure 4-2)

5

20

ns

td(CH-DOUT)

Delay time from SCLK high to DOUT valid
(see Figures 4-2 and 4-7)

20

ns

1d(CH-DOUTZ)

Delay time from SCLKI to DOUT in high-impedance state
(see Figure 4-8)

20

ns

td(ML-ELl

Delay time from MCLK low to EOC low (see Figure 4-9)

40

ns

td(ML-EH)

Delay time from MCLK low to EOC high (see Figure 4-9)

40

ns

tf(EL)

EOC fall time (see Figure 4-9)

13

ns

tr(EH)

EOC rise time (see Figure 4-9)

13

1d(MH-CH)

Delay time from MCLK high to SCLK high

50

ns

1d(MH-CL)

Delay time from MCLK high to SCLK low

50

ns

t

ns

All typical values are at VDD = 5 V and TA = 25°C.
NOTES: 23. All timing specifications are valid with CL = 20 pF.
24. FSD occurs 1/2 shift-clock cycle ahead of FS when the device is operating in the master mode.

4-320

3.7

Timing Requirements and Specifications in Slave Mode and Codec
Emulation Mode

3.7.1

Recommended Input Timing Requirements for Slave Mode, Voo

=5 V
MAX

NOM

MIN

UNIT

tr(MCLK)

Master clock rise time

5

ns

tf(MCLK)

Master clock fall time

5

ns

Master clock duty cycle

40%

tw(RESET)

RESET pulse duration

1 MCLK

tsu{DIN)

DIN setup time before SCLK low (see Figure 4-3)

th(DIN)

DIN hold time after SCLK high (see Figure 4-3)

tsu(FL-CH)

Setup time from FS low to SCLK high

3.7.2

60%

ns

20
20

ns

±SCLK/4

ns

Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, Voo 5 V (Unless Otherwise Noted) (see Note 23)

=

PARAMETER
tc(SCLK)

Shift clock cycle time (see Figure 4-3)

MIN

TYPt

MAX

125

UNIT
ns

tf(SCLK)

Shift clock fall time (see Figure 4-3)

18

ns

tr(SCLK)

Shift clock rise time (see Figure 4-3)

18

ns

Shift clock duty cycle

45%

55%

td(CH-FDU

Delay time from SCLK high to FSD low (see Figure 4-6)

50

ns

td(CH-FDH)

Delay time from SCLK high to FSD high

40

ns

td(FL-FDL)

Delay time from FS low to FSD low (slave to slave)
(see Figure 4-5)

40

ns

td(CH-DOUT)

Delay time from SCLK high to DOUT valid
(see Figures 4-3 and 4-7)

40

ns

td(CH-DOUTZ)

Delay time from SCLKi to DOUT in high-impedance state
(see Figure 4-8)

20

ns

td(ML-EL)

Delay time from MCLK low to EOC low (see Figure 4-9)

40

ns

td(ML-EH)

Delay time from MCLK low to EOC high (see Figure 4-9)

40

ns

tf(EL)

EOC fall time (see Figure 4-9)

13

ns

tr(EH)

EOC rise time (see Figure 4-9)

13

ns

td(MH-CH)

Delay time from MCLK high to SCLK high

50

ns

td(MH-CL)

Delay time from MCLK high to SCLK low

50

ns

t All typical values are at VDD = 5 V and TA = 25°C.
NOTE 23: All timing specifications are valid with CL = 20 pF.

4-321

4-322

4

Parameter Measurement Information
Rfb

R
IN+orAUXIN+--~VV-~-~

R
IN- or AUX IN- - - - ' \ I \ I \ r - _ . - - - 1

I-+-......- - . } To Multlpl."",

Rfb

=

=

Rfb R for 0503 0 and 0502 = 1
Rfb 2R for 0503 1 and 0502 = 0
Rfb = 4R for 0503 = 1 and 0502 = 1
R 100 kQ nominal

=

=

=

Figure 4-1. IN + and IN- Gain-Control Circuitry
Table 4-1. Gain Control (Analog Input Signal Required for
Full-Scale Bipolar AID-Conversion 2s Complement)t
INPUT CONFIGURATION

Oifferential configuration
Analog input = IN + - IN=AUX IN+-AUX IN-

Single-ended configuration§
Analog input = IN + - VMID
= AUX IN+ - VMIO

CONTROL REGISTER 4
ANALOG INPUT:!:

A/O CONVERSION
RESULT

0503

0502

0

0

0

1

VID =±3 V

±Full scale

1

0

VIO=±1.5V

±Full scale
±Full scale

All

Squelch

1

1

VIO =±0.75 V

0

0

All

0

1

1

0

VI=±1.5V

±Full scale

1

1

VI = ±0.75 V

±Full scale

VI = ±1.5 V

Squelch
±Half scale

tVOO= 5 V
= differential input voltage, VI = input voltage referenced to AOC VMIO with IN- or AUX IN- connected to
AOC VMIO. In order to minimize distortion, it is recommended that the analog input not exceed 0.1 dB below full scale.
§ For single-ended inputs, the analog input voltage should not exceed the supply rails. All single-ended inputs should be
referenced to the internal reference voltage, AOC VMIO, for best common-mode performance.
:1= VIO

4-323

-.I 14-

tf(SCLK)

I+-

1 1

tr(SCLK)

1

SCLK 2V

~

I

0.8 V

1

r-"'e::10<
>e::10<

D2

X

D1

X

02

X

01

X 00

00

>>-

~

t The time between falling edges of two primary FS signals is the conversion period.
:1= The

data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling
edge of the shift clock.

Figure 4-2. AIC Stand-Alone and Master-Mode Timing

---.: I+-

tf(SCLK)

'4-----1~M-- tc(SCLK)

I+- tr(SCLK)

1

SCLK
1

lOl 1.1

§

FSt ~! ____________
~~~

~~

;-

________________________________- J

02

02

X

X

01

01

X

X

00

00

>>-

t The time between falling edges of two primary FS signals is the conversion period.
:1= The

data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling
edge of the shift clock.
§ The high-to-Iow transition of FS must must occur within ±1/4 of a shift-clock period around the 2-V level of the shift clock
for the codec mode.

Figure 4-3. AIC Slave and Codec Emulation Mode

4-324

SCLK

2.4/1
\
\--.....r
---I
1

14

0.8

:

~

SCLK Perlod/2

>i~--+:--+l-----1

-+i
0.8

1

14- td(CH-FL)

){""I_______

NOTE A: Timing shown is for the TLC320AC02 operating as the master or as a stand-alone device.

Figure 4-4. Master or Stand-Alone FS and FSD Timing

0.8

~110.

_ _ _ _ _ _ _ _ _ __

I

~

.:

td(FL-FDL)

---------0-.8~){1IO.1_________________
NOTE A: Timing shown is for the TLC320AC02 operating in the slave mode (FS and SCLK signals are generated
externally). The programmed data value in the FSD register is o.

Figure 4-5. Slave FS to FSD Timing

SCLK

2.4 V/'I

____--J/:

--+I

\

/

0.8 v\.....___..1.

~ td(CH-FDL)

-----0-.8~~1IO.1______________________________________
NOTE A: Timing shown is for the TLC320AC02 operating in the slave mode (FS and SCLK Signals are generated
externally). There is a data value in the FSD register greater than 18 (deCimal).

Figure 4 - 6. Slave SCLK to FSD Timing

4-325

SCLK

2(V
_ _~_.

HDOUT

\~

\
/
0.8 V\;1Iio _ _- J .
td(CH-DOUT)

X

.....;..;H.;..;i-Z;;....._-(~ 2.4 V

2.4 V
\~._~0.~4~V_ _ _ _ _ _ _-J. ~.~0.~4_V_____

Figure 4-7. DOUT Enable Timing From Hi-Z
SCLK

0.8~

2V;1

~

/

.1
1
0.8/

DOUT

td(CH-DOUTZ)
Hi-Z

Figure 4-8. DOUT Delay Timing to Hi-Z

~,

'...
,
MCLK

__

td(ML-EH)

-J;t~--0-.8~>l~~i_ _-J~~~0~.8.;..;V______________
--.:

I

,

: . - tr(EH)

~

11

r '_ _

EOC,
0.4 V

~

2.4 V

____

~r}(}

,

,...

N'

td(ML-EL)

,

~
Internal ADC
Conversion Time

Figure 4-9. EOC Frame Timing

4-326

2.4 V

,

--------------'~-. I

,I

,

.:

0.4 V

i+-

.,

,

tf(EL)

I.

.1

1

Delay Is m Shift Clockst

1

Master
FS
14------1-14

j
u

Master FSD,
Slave Device 1 FS

Delay Is m Shift Clockst

J:
___----I~'I--

I.

Delay Is m Shift Clockst
I

I

Slave Device 1 FSD,
Slave Device 2 FS
Slave Device 2 FSD,
Slave Device 3 FS

1

I

I
I

I
I

+-----------------IU

I

I

LJ

Slave Device
(n -1) FSD,
Slave Device n FS

t

The delay time from any FS signals to the corresponding FSD signals is m shift clocks with the value of m being the
numerical value of the data programmed into the FSD register. In the master mode with slaves, the same data word
programs the master and ali slave devices; therefore, master to slave 1, slave 1 to slave 2, slave 2 to slave 3, etc., have
the same delay time.

Figure 4-10. Master-Slave Frame-Sync Timing After a Delay Has Been
Programmed Into the FSD Registers

t=o

I

r-

Sampling
Period

.slr'

Master AIC
Only Primary
Frame Sync

14

I

~

t=1

t=2

I

I
I

':r----r'

~

1/2 Period I

I

1

~ ~~~ ~,

Master AIC
Only Primary
and Secondary
Frame Sync

FS
fMpfl
FSD
I
Value --+[ I

I
I I

~

Master and Slave
FS
AIC Primary
Frame Sync
Master and Slave
AIC Primary and
Secondary
Frame Sync

IMPI

I

1

~'

IMP!

I I
I I

I
I I

15P I I I

IMPI

)

"I-T--T----i II ~\
UUii
UU

',\-1 II
.

.--1

~

IMP!

IM51
I 1
k- I I
\I
II
15P I I

I

IMPI

15PI

FS----u-D1J-uiJiJiJ-uiJUtru

MP = Master Primary
MS = Master Secondary

MP

5P

M5

55

MP

5P

M5

55

MP

5P

MS

55

SP = Slave Primary
SS = Slave Secondary

Figure 4-11. Master and Slave Frame-Sync Sequence with One Slave
4-327

4-328

5

Typical Characteristics
ADC LOW·PASS RESPONSE

0

"

-10

a:I

TA = 25°C

-20

FCLK

= 144 kHz

"0

I
C

o

i:::J

-30

C

~

-40

{~

If

-50

-60

-

10-"'"

II
o

1

2

3

4

5

6

7

8

9

10

fi - Input Frequency - kHz

NOTE A : Absolute Frequency (kHz) = Normalized Frequency x FCLK (kHz)
144

Figure 5-1

4-329

ADC LOW-PASS RESPONSE

o.5
o.4

T

I

=

I

TA 25°C
FCLK 144 kHz

=

o.3
0.2
III
"C

I

c

o

~

0.1

-

0

::I

i

~

-0.1

"""""

......

,

. / '\

I'.....

JV
I'-

-0.2
":'0.3
-0.4

-0.5

o

0.5

1
1.5
2
2.5
3
fi - Input Frequency - kHz

3.5

4

NOTE A : Absolute Frequency (kHz) = Normalized Frequency x FCLK (kHz)
.
1M

Figure 5-2

4-330

-

ADC GROUP DELAY

1

=

TA 25°C
FCLK 144 kHz

o.9
o.8

=

0.7
III

0.6

I

0.5

E
CD

E

j::

0.4

J

0.3
0.2
~

J

V

~

0.1

o
o

"

r--.... r-..

2

3
fj -

4

5

6

7

8

9

10

Input Frequency - kHz

NOTE A : Absolute Frequency (kHz) = Normalized Frequency x FCLK (kHz)

144

Figure 5-3

4-331

,

ADC BAND-PASS RESPONSE

Or
-1 0

III

TA = 25°C
Is = 8 kHz
FCLK = 144 kHz

-20

"c
I

o

~c

~

-30
-40

( 1\

-50

-60

o

1/

~

~I
1

23456
fi - Input Frequency - kHz

7

8

NOTE A : Absolute Frequency (kHz) = Normalized Frequency x FCLK (kHz)

144

Figure 5-4

4-332

ADC BAND-PASS RESPONSE

o.5
o.4

TA = 25°C
f5 = 8 kHz
FCLK = 144 kHz

o. 3
ID

"c

o.2

I

0.1

.2
~

0

~

I

-0.1

V

t

-0.2

-

--"

~ r0-

,

/ '\

I

-0.3
-0.4
-0.5 I

o

0.5

1
1.5
2
2.5
3
fl - Input Frequency - kHz

3.5

4

NOTE A : Absolute Frequency (kHz) = Normalized Frequency x FCLK (kHz)
144

Figure 5-5

4-333

ADC HIGH·PASS RESPONSE

0

/

-5

III

/

-10

/
I

"c
I

o

i::J

-15

C

~

-20

~

I

-25

-30

TA = 25°C
fs = 8 kHz
FCLK = 144 kHz

o

50

100, 150
200
fi - Input Frequency - kHz

250

NOTE A : Absolute Frequency (kHz) = Normalized Frequency x FCLK (kHz)

144

Figure 5-6

4-334

ADC BAND·PASS GROUP DELAY
I

I

~

TA = 25°C
fs = 8 kHz
FCLK = 144 kHz

0.9
0.8
0.7
II)

E
I

I
I

0.6

GI

0.5

i=

0.4

II

E
0.3
0.2

'---'

0.1

o

/

\
~

"

..............

o

2
4
3
5
6
fi - Input Frequency - kHz

NOTE A : Absolute Frequency (kHz)

=

7

8

Normalized Frequency x FCLK (kHz)
144

Figure 5-7

4-335

DAC LOW·PASS RESPONSE

0

"

-10

III

=
=

-20

"

TA 25°C
fs 9.6 kHz
FCLK 144 kHz

=

I

a
i

-30

~

c
S

<

-40

'\

-50

-60

/'

V

r---.

\

\,
o

1

2

3

4

5

6

7

8

9

10

fl - Input Frequency - kHz
NOTE A : Absolute Frequency (kHz)

=

Normalized Frequency x FCLK (kHz)

Figure 5-8

4-336

144

DAC LOW-PASS RESPONSE

o.5

I

TA = 25°C
0.4 fs = 9.6 kHz
FCLK = 144 kHz
0.3
0.2
lD

"c
I

0.1

~

0

!

-0.1

:::I
C

.- ~

-

"'-h

-0.2
-0.3
-0.4
-0.5

o

0.5

1
1.5
2
2.5
3
fl - Input Frequency - kHz

NOTE A : Absolute Frequency (kHz)

=

3.5

4

Normalized Frequency x FCLK (kHz)
144

Figure 5-9

4-337

DAC LOW-PASS GROUP DELAY

t

~

0.9

I
TA 25 0
fs 9.6 kHz
FCLK 144 kHz

=

0.8

=

;

0.7
1/1

0.6

I

0.5

n

E
CD

E

j::

0.4
0.3
0.2
0.1
0

--

V

o

2

1

\

"-r--

3

4

5· 6

-

""'-

7

lr
8

9

10

fi - Input Frequency - kHz
NOTE A : Absolute Frequency (kHz) =

Normalized Frequency x FCLK (kHz)
144

Figure 5-10

4-338

DAC (sin x)/x CORRECTION FILTER RESPONSE

4

2

V

I

0

/

\

\

1\

",

In

"C

V

/

~

~

\

CII

"C
::::I

==CCI

as
:E

-2

~

\

-4

=

~

\

TA 25°C
Input ± 3-V Sine Wave

-6

o

=

I

I

I

I

I

2

4

6

8

10

12

14

16

18

20

Normalized Frequency

NOTE A : Absolute Frequency '(kHz)

=

Normalized Frequency x FCLK (kHz)
288

Figure 5-11

4-339

DAC (sinx)/x CORRECTION FILTER RESPONSE
500
TA 25°C
Input ± loV Sine Wave

=

=

400

( 1\

III

::1.

I

i;'

300

"i
Q
Co
::J
0

..

200

CJ

100

--

o
o

2

V

I

/ \

,./

4

6

8

10

12

14

1\
16

18

"
20

Normalized Frequency

NOTE A : Absolute Frequency (kHz) =

Normalized Frequency x FCLK (kHz)
288

Figure 5-12

4-340

DAC (sin x)/x CORRECTION ERROR
2

=

TA 25°C
Input ± 3-V Sine Wave

1.6

=

1.2

V (sin x) Ix Correction

0.8
m
~

0.4

-8:::J

o

:=

./

/

I'

c

fi - 0.4

:E

--...
-"'"

I
Error

,/

"-

-0.8

~

""- .......

""

-1.2

i\..

-1.6

-2

/
V
1

o

19.2-kHz (sin x)
Distortion

I~

"1\

\

2

3

4

5

6

7

8

9

10

Normalized Frequency

NOTE A : Absolute Frequency (kHz) =

Normalized Frequency x FCLK (kHz)
288

Figure 5-13

4-341

4-342

6

Application Information
TMS320C2x13x

TLC320AC02

......
.

CLKOUT
DX

FSR
CLKX
CLKR

14
10

.... 11

DR
FSX

DACVDD

12

....

W
W
....

MCLK

DACVMID

DIN

DACGND

DOUT

6
7
24

ADCVDD
FS
ADCVMID

13

5

23
22

ADCGND

SCLK

5V

+
1
+ ~F T
0.1

~F

;::: :::::: 0.1

5V

0.1

~F

0.1

9

5V

DGTL VDD
DGTLGND

~F

20

;::: :::::: 0.1

-=-

~F

-

NOTE A: Terminal numbers shown are for the FN package.

Figure 6-1. Stand-Alone Mode (to DSP Interface)

TMS320C2x/3x

TLC320AC02
14

CLKOUT

10

DX
DR
FSX
FSR
CLKX
CLKR

... 11
,
12

W
W

13

MCLK
DIN
DOUT
FS

SCLK

NOTE A: Terminal numbers shown are for the FN package.

Figure 6-2. Codec Mode (to DSP Interface)

4-343

TMS320C2x/3x

-

TLC320AC02
.. 14

CLKOUT

.. 10

DX
DR
FSX
FSR

11

....
....

12

~

CLKX

,13

....

MCLK
DIN
DOUT
Master Mode

FS
FSD
SCLK

CLKR -4-4.
TLC320AC02
.. 14
10
11

DIN
DOUT

,~

FS

,-

FSD

.. 13

1"

MCLK

Slave Mode

SCLK

j

NOTE A: Terminal numbers shown are for the FN package.

Figure 6-3. Master With Slave (to DSP Interface)

10 kQ
10kQ
IN+
10kQ
10kQ
ADCVMID

IN-

t The VI source must be capable of sinking a current equal to [ADe VrVIID + iVll(max)]/1 0 kQ.
Figure 6-4. Single-Ended Input (Ground Referenced)
4-344

IN+
10kn

10ka

10kn

10ka

Vlt --'V\I\r--__.--I

IN-

10 kn
1 - - - - - - - ADC VMID

10ka

tThe VI source must be capable of sinking a current equal to [(ADC VMloJ2) + IVII(max)]/10 ill.

Figure 6-5. Single-Ended to Differential Input (Ground Referenced)

OUT-

600-a
Load

OUT+

Figure 6-6. Differential Load

10kn

OUT- 1--J\I'\I'v---e""'---1
OUT+ t - 4 V v - - ' - - - I

TLE2062

600-a
Load

NOTE A: When a signal changes from a single supply with a nonzero reference system to a
grounded load, the operational amplifier must be powered from plus and minus supplies
or the load must be capacitively coupled.

Figure 6-7. Differential Output Drive (Ground Referenced)
4-345

OUT+~--------~

TLE2062·
600-Q
Load

OUT-~--------~

Figure

6-8~

Low-Impedance Output Drive

100 kQ
100 kQ
OUT+ 1--4VV----_---I
DAC VMID

~~V\r----_---I

100 kQ

600-Q
Load
TLE2062

NOTE A: When a signal changes from a single supply with a nonzero reference system to a
grounded load, the operational amplifier must be powered from plus and minus supplies
or the load must be capacitively coupled.

Figure 6-9. Singh:~-Ended Output Drive (Ground Referenced)

4-346

Appendix A
Primary Control Bits
The function of the primary-word control bits 001 and 000 and the hardware terminals FCO and FC1 are
shown below. Any combinational state of 001, 000, FC1, and FCO not shown is ignored.

CONTROL FUNCTION OF CONTROL BITS
BITS

TERMINALS

001

000

FC1

FCO

0

0

0

0

On the next falling edge of FS, the AIC receives DAC data D15-D02 to DIN and
transmits the ADC data D15-DOO from DOUT.

0

0

0

1

On the. next falling edge of FS, the AIC receives DAC data D15-D02 to DIN and
transmits the ADC data D15-DOO from DOUT.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of the next internal FS, the next ADC/DAC sampling time occurs later
by the number of MCLK periods equal to the value contained ~the A' register. When
the A' register value is negative, the internal falling edge of FS occurs earlier.

0

0

1

0

On the next falling edge of FS, the AIC receives DAC data D15-D02 at DIN and
transmits the ADC data D15-DOO from DOUT.
The phase adjustment is determined by the state of FC1 and FCO such that on the
rising edge of the next internal FS, the next ADC/DAC sample time occurs earlier by
the humber of MCLK periods determined by the value contained in the A' register.
When the A' register value is negative, the internal falling edge of FS occurs later.

0

0

1

1

On the next falling edge of the primary FS, the Ale receives DAC data D15- D02 at
DIN and transmits the ADC data D15-DOO from DOUT.
When FCO and FC1 are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync occurs at 1/2 the
sampling time as measured from the falling edge of the primary FS.

0

1

0

0

On the next falling edge of FS, the AIC receives DAC data D15-D02 to DIN and
transmits the ADC data D15-DOO from DOUT.
The phase adjustment is determined by the state of D01 and DOO such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, the falling edge of FS occurs earlier.

1

0

0

0

On the next falling edge of FS, the AIC receives DAC data D15-D02 at DIN and
transmits the ADC data D15-DOO from DOUT.
The phase adjustment is determined by the state of D01 and DOO. On the next rising
edge of FS, the next ADC/DAC sampling time occurs earlier by the number of MCLK
periods determined by the value contained in the A' register. When the A' register
value is negative, the internal falling edge of FS occurs later.

1

1

0

0

On the next falling edge of FS, the AIC receives DAC data D15-D02 to DIN and
transmits the ADC data D 15 - DOO from DOUT.
When DOO and D01 are both high, the AIC initiates a secondary FS to receive a
secondary control word at DIN. The secondary frame sync occurs at 1/2 the sampling
time as measured from the falling edge of the primary FS.

4-347

CONTROL FUNCTION OF CONTROL BITS (Continued)
BITS

TERMINALS

D01

DOO

FC1

FCO

0

1

1

1

On the next falling edge of FS, the AIC receives DAC data 015-002 to DIN and
transmits the ADC data 015-000 from DOUT.
The phase adjustment is determined by the state of 001 and 000 such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLKperiods determined by the value contained in the A' register. When the A'
register value is negative, FS occurs earlier.
When FCO and FCl are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync occurs at 1/2 the
sampling time as measured from the falling edge of the primary FS.

1

0

1

1

On the next falling edge of FS, theAIC receiveE DAC data 015-002 at DIN and
transmits the ADC data 015-000 from DOUT.
The phase adjustment is determined by the state of 001 and 000. On the next rising
edge of FS, the next ADC/DAC sample time occurs earlier by the number of MCLK
periods determined by the value contained in the A' register. When the A' register
value is negative, FS occurs later.
When FCO and FCl are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync occurs at 1/2 the
sampling time as measured from the falling edge of the primary FS.

1

1

1

1

On the next falling edge of the primary FS, the AIC receives DAC data 015- 002 at
DIN and transmits the ADC data 015-000 from DOUT.
When FCl and FCO are both high or 001 and 000 are both high, the AIC initiates a
secondary FS to receive a secondary control word at DIN. The secondary FS occurs
at 1/2 the sampling time measured from the falling edge of the primary FS.

1

1

0

1

On the next falling edge of FS, the AIC receives DAC data 015-002 to DIN and
the ADC data 015-000 from DOUT.

~ransmits

When 000 and 001 are high, the AIC initiates a secondary FS to receive a secondary
control word at DIN. The secondary frame sync occurs at 1/2 the sampling time as
measured from the falling edge of the primary FS.
The phase adjustment is determined by the state of FCl and FCO such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, FS occurs earlier.
1

1

1

0

On the next falling edge of FS, the AIC receives DAC data 015-002 to DIN and
transmits the ADC data 015-000 from DOUT.
When 000 and 001 are high, the AIC initiates a secondary FS to receive a secondary
control word at DIN. The secondary frame sync occurs at 1/2 the sampling time as
measured from the falling edge of the primary FS.
The phase adjustment is determined by the state of FCl and FCO such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, FS occurs earlier.

1

1

I

4-348

1

1

On the next falling edge of FS, the AIC receives DAC data 015-002 at DIN and
transmits the ADC data 015 - 000 from DOUT.
When FCl and FCO are both high or 001 and 000 are both high, the AIC initiates a
secondary FS to receive a secondary control word at DIN. The secondary FS occurs
at 1/2 the sampling time measured from the falling edge of the primary FS.

Appendix B
Secondary Communications
The function of the control bits 0815 and 0814 and the hardware terminals FCD and FC1 are shown below.
Any combinational state of D815, 0814, FC1, and FCD not shown is ignored.

CONTROL FUNCTION OF SECONDARY COMMUNICATION
BITS
OS15

TERMINALS

OS14

FC1

FCC

0

0

Ignored

0

1

Ignored

On the next falling edge of F8, the AIC receives OAC data 015-002 at DIN and
transmits the AOC data 015-000 from OOUT.
On the next falling edge of the F8, the AIC receives OAC data 015- 002 at OIN and
transmits the AOC data 015- 000 from OOUT.
The phase adjustment is determined by the state of 0815 and 0814 such that on the
next rising edge of F8, the next AOC/OAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, F8 occurs earlier.

1

0

Ignored

On the next falling edge of F8, the AIC receives OAC data 015-002 at OIN and
transmits the AOC data 015-000 from OOUT.
The phase adjustment is determined by the state of 001 and 000. On the next rising
edge of F8, the next AOC/OAC sampling time occurs earlier by the number of MCLK
periods determined by the value contained in the A' register. When the A' register
value is negative, F8 occurs later.

1

1

0

0

On the next falling edge of F8, the AIC receives OAC data 015-002 atDIN and
transmits the AOC data 015-000 from OOUT.

1

1

0

1

On the next falling edge of the FS, the AIC receives OAC data 015-002 at DIN and
transmits the AOC data 015-000 from OOUT.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of FS, the next AOC/OAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, F8 occurs earlier.

1

1

1

0

On the next falling edge of F8, the AIC receives OAC data 015-002 at OIN and
transmits the AOC data 015-000 from OOUT.
The phase adjustment is determined by the state of FC1 and FCO such that on the
next rising edge of FS, the next AOC/OAC sampling time occurs earlier by the number
of MCLK periods determined by the value contained in the A' register. When the A'
register value is negative, FS occurs later.

1

1

1

1

On the next falling edge of FS, the AIC receives OAC data 015-002 at OIN and
transmits the AOC data 015-000 from OOUT.

4-349

4-350

Appendix C
TLC320AC01 CITLC320AC02C Specification Comparisons
Texas Instruments manufactures the TLC320AC01 C and the TLC320AC02C specified for the O°C to 70°C
commercial temperature range and the TLC320AC021 specified for the -40°C to 85°C temperature range.
The TLC320AC02C and TLC320AC021 operate at a relaxed TLC320AC01 C specification. The differences
are listed in the following tables.

ADC Channel Signal-to-Distortion Ratio, Voo
Otherwise Noted) (see Note 1)
PARAMETER

TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02

TEST CONDITIONS

VI = -6 dB to -1 dB

VI =-12dBto-6dB
VI = -18 dB to -12 dB
VI =-24dBto-18dB
VI = -30 dB to -24 dB
VI = -36 dB to -30 dB
VI = -42 dB to -36 dB
VI = -48 dB to -42 dB

AV=OdB
MIN

68
64

MAX

=5 V, fs =8 kHz (Unless
Av=6dB
MIN

MAX

AV = 12 dB
MIN

-

-

63

68

59

64

-

57

63

68

56

59

64

51

57

63

50

56

59

45

51

57

44

50

56

39·

45

51

38

44

50

33

39

45

32

38

44

27

33

39

26

32

38

MAX

UNIT

dB

NOTE 1: The analog-input test signal is a 1020-Hz sine wave with 0 dB = 6 V peak to peak as the reference level for
the analog input signal.

4-351

DAC Channel Signal-to-Distortion Ratio, Voo
Otherwise Noted) (see Note 2)
PARAMETER
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02

TEST CONDITIONS
Vo =-6 dBto 0 dB

VO=-12dBto-6dB
Vo = -18 dB to -12 dB
Vo = -24 dB to -18 dB
Vo = -30 dB to -24 dB
Vo = -36 dB to -30 dB
Vo = -42 dB to -36 dB

Vo = -48 dB to -42 dB

Av=OdB
MIN
68
64

MAX

=5 V,fs =8 kHz (Unless
Av=-6dB
MIN

-

63

68

59

64

MAX

AV=-12dB
MIN

MAX

UNIT

-

57

63

68

56

59

64

51

57

63

50

56

59

45

51

57

44

50

56

39

45

51

38

44

50

33

·39

45

32

38

44

27

33

39

26

32

38

dB

NOTE 2: The input signal, VI, is the digital equivalent of a 1020-Hz sine wave (full-scale analog output at full-scale digital
input = 0 dB). The nominal differential DAC channel output with this input condition is 6 V peak to peak. The
load impedance for the DAC output buffer is 600 n from OUT + to OUT -.

4-352

System Distortion, ADC Channel Attenuation, Voo
FCLK 144 kHz (Unless Otherwise Noted)

=

PARAMETER
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02

=5 V, fs =8 kHz,

TEST CONDITIONS

Second harmonic
Differential input
(see Note 3)
Third harmonic and higher harmonics

MIN

MAX

UNIT

70

dB

64

dB

70

dB

64

dB

NOTE 3: The input signal is a 1020 Hz-sine wave for the ADC channel. Harmonic distortion is defined for an input level
of-1 dB.

System Distortion, DAC Channel Attenuation, VDO= 5 V, fs = 8 kHz,
FCLK 144 kHz (Unless Otherwise Noted)

=

PARAMETER
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02

TEST CONDITIONS

Second harmonic
Differential output
(see Note 4)
Third harmonic and higher harmonics

MIN

MAX

UNIT

70

dB

64

dB

70

dB

64

dB

NOT-£: 4: The input signal is the digital equivalent of a 1020-Hz sine wave (digital full scale = 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the DAC
output buffer is 600 n from OUT + to OUT -. Harmonic distortion is specified for a signal input level of 0 dB.

4-353

+-354

Appendix 0
Multiple TLC320AC01/02 Analog Interface Circuits on One
TMS320C5X DSP Serial Port
In many applications, digital signal processors (DSP) must obtain information from multiple analog-to-digital
(AID) channels and transmit digital data to multiple digital-to-analog (D/A) conversion channels. The
problem is how to do it easily and efficiently.
This application report addresses the issue of connecting two channels of an analog interface circuit (AIC)
to one TMS320C5X DSP serial port. In this application report, the AIC is the TLC320AC02.
The TLC320AC02 (and TLC320AC01) analog interface circuit contains both AID and D/A converters and
using the master/slave mode, it is possible to connect two of them to one TMS320C5X DSP serial port with
no additional logic. The hardware schematic is shown in Figure D-1.

4-355

TMS320C5x

TLC320AC02
14

CLKOUT

10

DX
DR

....

11

FSX

...

12

FSR
CLKX

W

r---

13

....

MCLK
DIN
DOUT
Master Mode

FS
FSD
SCLK

CLKR ~
TLC320AC02
14
10
11

MCLK
DIN
DOUT

~ FS
r---

..

.. 13

,

~,

FSD
SCLK

Slave Mode

~,

NOTE A: Terminal numbers shown are for the FN package.

Figure 0-1. Master With Slave (to OSP Interface)

HARDWARE AND SOFTWARE SOLUTION
Once the hardware connections are completed, the issue becomes distinguishing one channel from
another. Fortunately, this is very easy to do in software and adds very little overhead. The mode that the
AC02s run in is called master/slave mode. One AC02 is the master and all of the rest of the AC02s are
slaves. The master can be distinguished from all of the slaves by examining the least significant bit (LSB)
in the receive word coming from the AC02. The master has a 0 in the LSB and all of the slaves have a 1
in the LSB.
The AC02s in master/slave mode take turns communicating with the DSP serial port. They do this is a round
robin or circular fashion. Synchronizing the system involves looking for the master AC02 and then starting
the software associated with the first AC02. All other AC02s follow in order. It is possible to have different
software for each AC02.
A reference design was constructed using a TMS320C5X OSP starter kit (OSK). The AC02s were
connected to the TOM serial port which is available at the headers on the edge of the OSK.
A listing of the DSK assembly code for a simple stereo input/output program is included in the following
section.
4-356

SOFTWARE MODULE
*****************************************************************************

*
:*

MODULE NAME: INOUTB. ASM

*

*
*

In-out routine for C5X DSK with two TLC320AC02s on the
TDM serial port of the C5X in master/slave mode.

:*

**
:

:*

*
*

:*

*

:*
:

This version performs the in/out task for both the master
and slave TLC320AC02 in the receive interrupt service
routine.

:

*
*
**
*
******************************************************************************
.mmregs

*

.ds

OlOOOh

PRI

.word

0104h

;A register

PR2

.word

0219h

;B register

PR3

.word

0300h

;A prime register

PR4

. word

0405h

;amplifier gain register

PR5

.word

0501h

; analog configuration register

PR6

.word

0600h

;digital configuration register

PR7

.word

0730h

; frame synch delay register

PR8

.word

0802h

; frame synch number register

value

.word

0800h

value2

.word

OBOOh

val_add

.word

0200h

val_add2

.word

0400h

~***************************************************** ***********************

:*

:*

Set up the ISR vector

*~***************************************************** ************************
.ps

OBOah

rint:

B

RECEIVE

OA; Serial port receive interrupt RINT.

xint:

B

TRANSMIT

OC; Serial port transmit interrupt XINT.

trint:

B

TDMREC

txint:

B

TDMTX

;--------------------------*

t****************************************************************************
* . TMS320C5X INITIALIZATION
*:
.~
*******************************************************************************
.ps OaOOh
. entry
START:

SETC

INTM

Disable interrupts

LDP

#0

Set data page pointer

OPL

#OB34h,PMST

LACC

#0

SAMM

CWSR

SAMM

PDWSR

4-357

splk

#OOc8h

SPLK

082h,IMR

call

AC02INIT

CLRC

OVM

SPM

0

PM

SPLK

#042h,IMR

TDMA ser port rec interrupt

SPLK

#OC8h,TSPC

CLRC

INTM

loop

OVM

=0
=0

enable interrupts
main program here does nothing.

nop
b

a user program can be inserted.
loop

; - - - - - - - - - - end of main p r o g r a m - - . - - - - - - - TDM serial port receiver interrupt service routine
TDMREC:
This loop insures that the master AC02
ldp

#trcv

bit

trcv,15

is the first one that is written to in the
loop. the slave AC02(s) will follow in

bcnd

xxx,tc

sequential order. The master AC02 has a

o

in the Isb. the slave AC02(s) have a 1

in the Isb of the receive word.
ldp

#trcv

lacc

trcv

and

#Offfch
user code would go here for master AC02

sacl

tdxr

b

yyy

xxx
ldp

#trcv

lacc

trcv

and

#Offfch
user code would go here for slave AC02

sacl
yyy

rete

4-358

tdxr

TDM serial port transmit interrupt service routine
TDMTX:
rete
RECEIVER INTERRUPT SERVICE ROUTINE
RECEIVE:
rete
TRANSMIT:
RETE

4-359

AC02INIT
SPLK

#020h,TCR

SPLK

#Olh,PRD

MAR

* ,ARO

LACC

#0008h

SACL

TSPC

LACC

#00c8h

SACL

TSPC

SETC

SXM

i----------------------------LDP

#PRl

LACC

PRl

CALL

AC02_2ND

i----------------------------LDP

#PR2

LACC

PR2

CALL

AC02_2ND

;-----------------------~-----

LDP

#PR8

LACC

PR8

CALL

AC02_2ND

i---------------------~-------

LDP

#PR7

LACC

PR7

CALL

AC02_2ND

ret

AC02_2ND:
LDP

#0

SACH

TDXR

CLRC

INTM

IDLE
ADD

#6h, 15

SACH

TDXR

0000 0000 0000 0011 XXXX XXXX XXXX XXXX b

IDLE
SACL

TDXR

IDLE
LACL

#0

SACL

TDXR

IDLE
SETC
RET

4-360

INTM

make sure the word got sent

TLC320AD50C, TLC320AD52C
Data Manual

Sigma-Delta Analog Interface Circuits
With Master-Slave Function

SLAS131A
November 1997

•
TEXAS
INSTRUMENTS

Printed on Recycled Paper

IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.

Copyright © 1997, Texas Instruments Incorporated

Contents
Section

Title

1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.1 Features.............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.2 Functional Block Diagram ........................................... ,.
1.3 Terminal Assignments ................................................
1.4 Ordering Information .................................................
1.5 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.6 Definitions and Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.7 Register Functional Summary .........................................

2

Detailed Description .....................................................
2.1 Device Functions ....................................................
2.1.1 Operating Frequencies .........................................
2.1.2 ADC Signal Channel ...........................................
2.1.3 DAC Signal Channel ...........................................
2.1.4 Serial Interface ................................................
2.1.5 Register Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.1.6 Sigma-Delta ADC .............................................
2.1.7 Decimation Filter ...............................................
2.1.8 Sigma-Delta DAC .............................................
2.1.9 Interpolation Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.1 .10 Analog and Digital Loopback ....................................
2.1 .11 FI R Overflow Flag .............................................
2.2 Reset and Power-Down Functions .....................................
2.2.1 Software and Hardware Reset ...................................
2.2.2 Software and Hardware Power Down .............................
2.3 Master Clock Circuit. . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.4 Data Out (DOUT) ....................................................
2.4.1 Data Out, Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.4.2 Data Out, Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.5 Data In (DIN) ........................................................
2.6 FC (Hardware Secondary Communication Request) . . . . . . . . . . . . . . . . . . . . ..
2.7 Frame-Sync Function for TLC320AD50C ...............................
2.7.1 Frame Sync (FS) Function, Master Mode .........................
2.7.2 Frame Sync (FS) Function,Slave Mode ...........................
2.7.3 Frame-Sync Delayed (FSD) Function, Master Mode ................
2.7.4 Frame-Sync Delayed (FSD), Slave Mode ..........................
2.8 Frame-Sync Function For TLC320AD52C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.9 Multiplexed Analog Input and Output ...................................
2.9.1 Multiplexed Analog Input ........................................
2.9.2 Analog Output .................................................

3

Page

4-367
4-367
4-368
4-369
4-370
4-370
4-372
4-373

4-375
4-375
4-375
4-375
4-376
4-378
4-378
4-380
4-380
4-380
4-380
4-380
4-380
4-381
4-381
4-381
4-382
4-382
4-382
4-382
4-382
4-382
4-382
4-383
4-384
4-384
4-386
4-387
4-388
4-388
4-389
Serial Communications .................................................. 4-391
3.1 Primary Serial Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-391
4-363

4

3.2 Secondary Serial Communication ......................................
3.2.1 Hardware Secondary Serial Communication Request. . . . . . . . . . . . . ..
3.2.2 Software Secondary Serial Communication Request ...............
3.3 Conversion Rate Versus Serial Port ....................................
3.5 DIN and DOUT Data Format ..........................................
3.5.1 Primary Serial Communication DIN and DOUT Data Format .........
3.5.2 Secondary Serial Communication DIN and DOUT Data Format ......

4-392
4-393
4-393
4-394
4-395
4-395
4-395

Specificati~ns .......................................... , . . . . . . . . . . . . . . ..
4.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range ...
4.2 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.2.1 Recommended Operating Conditions, DVDD = 5 V . . . . . . . . . . . . . . . ..
4.2.2 Recommended Operating Conditions, DVDD = 3 V . . . . . . . . . . . . . . . ..
4.3 Electrical Characteristics Over Recommended

4-397
4-397
4-397
4-397
4-397

Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.3.1 Digital Inputs and Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.3.2 Digital Inputs and Outputs, DVDD = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.3.3 ADC Path Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.3.4 ADC Dynamic Performance .....................................
4.3.5 ADC Channel Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.3.6 DAC Path Filte ................................................
4.3.7 DAC Dynamic Performance .....................................
4.3.8 DAC Channel Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.3.9 Power Supply .................................................
4.3.10 Power-Supply Rejection ........................................
Timing Characteristics ................................................
4.4.1 Master Mode Timing Requirements ..............................
4.4.2 Slave Mode Timing Requirements ................................
4.4.3 Master Mode Switching Characteristics ...........................
4.4.4 Slave Mode Switching Characteristics ............................

4-398
4-398
4-398
4-398
4-398
4-399
4-399
4-400
4-401
4-401
4-401
4-402
4-402
4-402
4-402
4-402

4.4

5

Parameter Measurement Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-409

6

Register Set .............................................................
6.1 Control 1 Register ...................................................
6.2 Control 2 Register ...................................................
6.3 Control 3 Register ...................................................
6.4 Control 4 Register ...................................................

7

Application Information .................................................. 4-415

4-364

4-411
4-412
4-412
4-413
4-413

List of Illustrations
Figure

2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8

Title

Timing Sequence of ADC Channel (Primary Communication Only) .............
Timing Sequence of ADC Channel (Primary and Secondary Communication) ...
Timing Sequence of DAC Channel (Primary Communication Only) .............
Timing Sequence of DAC Channel (Primary and Secondary Communication) ...
Register 1 Read Operation Timing Diagram .................................
Register 1 Write Operation Timing Diagram .................................
Internal Power-Down Logic ...............................................
Master Device Frame-Sync Signal With Primary and Secondary Communications
(No Slaves) ..........................................................
2-9 Master Device Frame-Sync Signal With Primary and Secondary Communications
(With 1 Slave Device) .................................................
2-10 Master Device FS and FSD Output When FSD Register
(DO-D5, Control Register 3) is 0 ........... "............................
2-11 Master Device FS and FSD Output After Control Register 3 Is Programmed
(One Slave Device) ...................................................
2-12 Master With Slaves (To DSP Interface) ......................... " ......... "
2-13 Master-Slave Frame-Sync Timing After A Delay Has Been Programmed
Into The FSD Register (DO-D5 of Control Register 3) """"""""""""""""."" ..
2-14 Master Device FS and FSD Output After
Control Register 3 Is Programmed with 49H ..............................
2-15 RC Antialias Filter ......................................................
2-16 INP and INM Internal Self-Biased (2.5 V) Circuit ............................
2-17 Differential Output Drive (Ground Referenced) .............................
3-1 Primary Serial Communication Timing ......................................
3-2 Hardware and Software Methods to Make a Secondary Request ... "..........
3-3 FS Output When Hardware Secondary Serial Communication
Is Requested Only Once (No Slave) .... " ................................
3-4 FS Output When Hardware Secondary Serial Communication Is Requested
Only Once (Three Slaves) .............................................
3-5 FS Output During Software Secondary Serial Communication Request (No Slave)
3-6 Phone Mode Timing When Phone Mode is Enabled ..........................
3-7 Primary Communication DIN and DOUT Data Format .................... " ...
3-8 Secondary Communication DIN and DOUT Data Format ..................... ,
4-1 ADC Decimation Filter Response ..........................................
4-2 ADC Decimation Filter Passband Ripple ....................................
4-3 DAC Interpolation Filter Response .........................................
4-4 DAC Interpolation Filter Passband Ripple ...................................

Page

4-376
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4-383
4-384
4-385
4-386
4-386
4-387
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4-388
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4-365

List of Illustrations (continued)
Figure
5-1
5-2
5-3
5-4
5-5
7-1
7-2

Title

Master FS and FSD Timing ...............................................
Slave FS to FSD Timing ..................................................
Slave SCLK to FSD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Serial Communication Timing (Master Mode) ...............................
Serial Communication Timing (Slave Mode) .................................
Master Device and Slave Device Connections (to DSP Interface) ..............
Power Supply Decoupling .................................................

Page
4-409
4-409
4-409
4-410
4-410
4-415
4-416

List of Tables
Table
3-1
6-1
6-2
6-3
6-4
6-5

Title

Least Significant Bit Control Function ................................. : .....
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Control 1 Register. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Control 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Control 3 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Control 4 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

4-366

Page
4-392
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4-412
4-412
4-413
4-413

1 Introduction
The TLC320ADSOC and TLC320ADS2 provide high-resolution signal conversion from digital-to-analog
(D/A) and from analog-to-digital (ND) using oversampling sigma-delta technology. This device consists of
a pair of 16-bit synchronous serial conversion paths (one for each direction) and includes an interpolation
filter before the DAC and a decimation filter after the ADC. Other overhead functions on the chip include
timing (sample rate, FSD delay) and control (programmable gain amplifier, PLL, communication protocol,
etc.). The sigma-delta architecture produces high resolution AID and D/A conversion at a low system cost.
Programmable functions of this device can be selected through the serial interface. Options include reset,
power down, communications protocol, signal sampling rate, gain control, and system test modes (see
section 6). The TLC320ADSOC and TLC320AD52 are characterized for operation from ODC to 70 De.

1.1

Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

General-purpose analog interface circuit for V.34+ modem and business audio applications
16-bit oversampling sigma-delta ADC and DAC
Serial port interface
Typical 89-dB SNR (signal-to-noise ratio) for ADC and DAC
Typical 90-dB THD (signal to total harmonic distortion) for ADC and DAC
Typical 88-dB dynamic range
Test mode that includes a digital loopbacktest and analog loopback test
Programmable ND and D/A conversion rate
Programmable input and output gain control
Maximum conversion rate: 22.0S kHz
Single S-V power supply voltage or S-V analog and 3-V digital power supply voltage
Power dissipation (Po) of 120 mW rms typical in the operating mode
Hardware power-down mode to is mW
Internal reference voltage (Vref)
Differential architecture throughout device
TLC320ADSOC can support up to three slave devices; TLC320ADS2C can support one slave
2's complement data format
ALTDATA terminal provides data monitoring
Monitor amplifier to monitor input signals
On-chip phase locked loop (PLL)

4-367

1.2

Functional Block Diagram
27

INP --;5:--_-e-+-I
INM ....;6'--_*1--+-1

SigmaDelta
ADC

Decimation
Filter

PGA
AUXP .....:3'---+41---+-1
AUXM _4'--...._-+-1

Dt
~

Low
Pass
Filter

OUTM 24

11

~

DOUT

Digital
Loopback

Vref

OUTP

MONOUT

2

REFP
REFM

12

SigmaDelta
DAC

DIN

Interpolation
Filter

22
MIS
21
FSD
14

Buffer

ALTDATA

PWRDWN
RESET
FILT

MCLK

16
15
28

17
FC
20
FS
19 SCLK
13

~

~

III

PLL (x4)

DVSS

NOTE: Pin numbers shown are for the OW package.

4-368

FLAG

Internal
Clock
Circuit

DVDD

AVDD(PLL)

AVSS(PLL)

AVSS

AVDD

1.3

Terminal Assignments
OW PACKAGE
(TOP VIEW)

REFP
REFM
AUXP
AUXM
INP
INivl

FILT
MONOUT
AVSS
AVOO
OUTM
OUTP

AVOD(PLL)
AVSS(PLL)
DVOO
DVSS
DOUT
DIN
FLAG
ALTDATA

MIS
FSD
FS
SCLK
MCLK
FC
=PW~R=DW==""'N
-....--~

RESET

PTPACKAGE
(TOP VIEW)
I:::>

::2:a..::2:a..

0

(/)

0

xxu.u.
I-:
Z
(/)0 0
:::>:::>UJUJO:::!OOO ~Z~

««a::a::ZU.ZZ::2: ...........

INP
INM
NC

OUTM
OUTP
NC
NC
NC
NC
NC
MIS
FSD
FS
SCLK
MCLK

AVSS(PLL)
NC
NC
NC
DVOO
DVSS
13 141516 17 18 192021 22 2324

NC - No internal connection

4-369

1.4

Ordering Information
PACKAGE
TA

O°C to 70°C

1.5

SMALL OUTLINE
PLASTIC DIP
(OW)

QUAD FLAT PACK
(PT)

TLC320AD50CDW
TLC320AD52CDW

TLC320AD50CPT
TLC320AD52CPT

Terminal Functions
TERMINAL
NAME

I NO.
I PT lOW

I/O

DESCRIPTION

ALTDATA

17

14

I

Alternate data. ALTDATA signals are routed to DOUT during secondary
communication if phone mode is enabled using control 2 register.

AUXM

48

4

I

Inverting input to auxiliary analog input. AUXM requires an external single-pole
antialias filter with a low output impedance and should be tied to VSS if not used.

AUXP

47

3

I

Noninverting input to auxiliary analog input. AUXP requires an external
single-pole antialias filter with a low output impedance and should be tied to VSS
if not used.

AVDD

37

25

I

Analog ADC power supply (5 V only)

AVDD(PLL)

5

7

I

Analog power supply for the internal PLL (5 V only)

AVSS

39

26

I

Analog ground

AVSS(PLL)

7

8

I

Analog ground for the internal PLL

DIN

15

12

I

Data input. DIN receives the DAC input data and register data from the external
DSP (digital si';lnal processor) and is synchronized to SCLK and FS. Data is
latched at the falling edge of SCLK when FS is low. DIN is at high impedance
when FS is not active.

DOUT

14

11

0

Data output. DOUT transmits the ADC output bits and register data, and is
synchronized to SCLK. Data is sent out at the rising edge of SCLK when FS is
low. DOUT is at high impedance when FS is not activated.

DVDD

11

9

I

Digital power supply (5 V or 3 V)

DVSS

12

10

I

Digital ground

FC

23

17

I

Hardware secondary communication request. When FC is set to high, a
secondary communication, followed by the primary communication, will occur to
transfer AIC register data between AIC and DSP. FC is sampled and latched on
the rising edge of FS at the end of the primary serial communication. See section
3 for details.

FILT

43

28

0

Bandgap filter. FILT is provided for decoupling of the bandgap reference, and
provides 3.2 V. The optimal capacitor value is 0.1 !J.F (ceramic). This voltage node
should be loaded only with a high-impedance dc load.

FLAG

16

13

0

Output flag. During phone mode, FLAG contains the value set in control 2
register.

FS

27

20

I/O

Frame sync. When FS goes low, DIN begins receiving data bits and DOUT
begins transmitting data bits. In master mode, FS is internally generated and is
low during the data transmission into DIN and out from DOUT. In slave mode, FS
is externally generated.

4-370

1.5

Terminal Functions (Continued)
TERMINAL
NAME

I
I

NO.
PT

1/0

DESCRIPTION

I DW

FSD

28

21

0

Frame sync delayed output. The FSD (active-low) output synchronizes a slave
device to the frame sync of the master device. FSD is applied to the slave FS
input and is the same duration as the master FS signal but is delayed in time by
the number of shift clocks programmed in the control 3 register.

INM

2

6

I

Inverting input to analog modulator. INM requires an external single-pole
antialias filter with a low output impedance.

INP

1

5

I

Noninverting input to analog modulator. INP requires an external Single-pole
antialias filter with a low output impedance.

MIS

29

22

I

Masterlslave select input. When MIS is high, the device is the master, and when
it is low, it is a slave.

MCLK

25

18

I

Master clock. MCLK derives the internal clocks of the sigma-delta analog
interface circuit.

MONOUT

40

27

0

Monitor output. MONOUT allows for monitoring of the analog input and is a
high-impedance output. The gain or mute is selected using control 1 register.'

OUTM

36

24

0

Inverting output of the DAC. The OUTM output can be loaded with 600 n. OUTM
is functionally identical with and complementary to OUTP. OUTM can also be
used alone for single-ended operation.

OUTP

35

23

0

Noninverting output of the DAC. The OUTP output can be loaded with 600
OUTP can also be used alone for single~ended operation.

PWRDWN

22

16

I

Power down. When PWRDWN is pulled low, the device goes into a power-down
mode, the serial interface is disabled, and most of the high-speed clocks are
disabled. However, all the register values are sustained and the device resumes
full power operation without reinitialization when PWRDWN is pulled high again.
PWRDWN resets the counters only and preserves the programmed register
contents (see paragraph 2.2.2 for more information).

REFM

46

2

0

Voltage reference filter input. REFM is provided for low-pass filtering of the
internal bandgap reference. The optimal ceramic capacitor value is 0.1 J.lF and
should be connected between REFM and REFP. DC voltage at REFM is 0 V.

REFP

45

1

0

Voltage reference filter positive input. REFP is provided for low-pass filtering of
the internal bandgap reference. The optimal ceramic capacitor value is 0.1 J.lF
and should be connected between REFP and REFM. DC voltage at REFP is
3.2V.

RESET

21

15

I

Reset. RESET initializes all of the internal registers to their default values. The
serial port can be configured to the default state accordingly. See section 6 and
paragraph 2.2.1 for more information.

SCLK

26

19

I/O

Shift clock. The SCLK signal clocks serial data in through DIN and out through
DOUT during the frame-sync interval. When configured as an output (MiS high),
SCLK is generated internally by multiplying the frame-sync signal frequency by
256. When configured as an input (MIS low), SCLK is generated externally and
must be synchronous with the master clock and frame sync.

NOTE: All digital inputs and outputs are TTL compatible, unless otherwise noted (for DVDD

=

n.

5 V).

4-371

1.6

Definitions and Terminology

ADC Channel

ADC channel refers to all signal processing circuits between the analog input and
the digital conversion results at DOUT.

d

The alpha character d represents valid programmed or default data in the control
register format (see Section 3.2) when discussing other data bit portions of the
register.

Dxx

Dxx is the bit position in the primary data word (xx is the bit number).

DSxx

DSxx is the bit position in the secondary data word (xx is the bit number).

DAC Channel

DAC channel refers to all signal processing circuits between the digital data word
applied to DIN and the differential output analog signal available at OUTP and
OUTM.

Data Transfer Interval

The time during which data is transferred from DOUT and to DIN. The interval is
16 shift clocks and the data transfer is initiated by the falling edge of the frame-sync
signal.

FIR

Finite duration impulse response

f5
Frame Sync and
Sampling Period

The sampling frequency.

Frame Sync

Frame sync refers only to the falling edge of the signal that initiates the data transfer
interval. The primary frame sync starts the primary communications, and the
secondary frame sync starts the secondary communications.

Frame-Sync Interval

Frame-sync interval is the the time period occupied by 16 shift clocks. The
frame-sync signal goes high on the seventeenth rising edge of SCLK.

Host

A host is any processing system that interfaces to DIN, DOUT, SCLK, FS, and/or
MCLK.

PGA

Programmable gain amplifier

Primary
Communications

Primary cOl11munications refers to the digital data transfer interval. Since the device
is synchronous, the signal data words from the ADC channel and to the DAC
channel occur simultaneously.

Secondary
Communications

Secondary communications refers to the digital control and configuration data
transfer interval into DIN and the register read data cycle from DOUT. The data
transfer interval occurs when requested by hardware or software.

Signal Data

This refers to the input signal and all of the converted representations through the
ADC channel and the signal through the DAC channel to the analog output. This
is contrasted with the purely digital software control data.

x

The alpha character X represents a don't care bit-position within the control
register format.

4-372

Frame sync and sampling period is the time between falling edges of successive
primary frame-sync signals. It is always equal to 256 SCLK.

1.7

Register Functional Summary

There are seven control registers that are used as follows:
Register 0

The No-Op register. Addressing register 0 allows secondary communications requests
without altering any other register.

Register 1

The
•
•
•
•
•
•
•

Control 1 register. The data in this register controls:
Software reset
Software power down
Normal or auxiliary analog inputs enabling
Normal or auxiliary analog inputs monitoring
Selection of monitor amplifier output gain
Selection of digital loopback
Selection of16-bit or (15+ 1)-bit mode of DAC operation

Register 2

The
•
•
•
•
•

Control 2 register. The data in this register:
Contains the output value of FLAG
Selects phone mode
Contains the output flag indicating a decimator FIR filter overflow
Selects either 16-bit mode or (15+ 1)-bit mode of ADC operation
Enables analog loopback

Register 3

The Control 3 register. The data in this register:
•
Sets the number of SCLK delays between FS and FSD
•
Informs the master device of how many slaves are connected in the chain

Register 4

The Control 4 register. The data in this register:
•
Selects the amplifier gain for the input and output amplifiers
•
Sets the sample rate by choosing the value of N from 1 to 8
where fs = MCLKJ(128 x N) or MCLKJ(512 x N)
•
Selects the PLL. If the PLL is selected, the sampling rate is set to MCLKJ(128 x N). If
the PLL is bypassed, the sampling rate can be set to MCLKJ(512 x N).

Register 5

Reserved for factory test. Do not write to this register.

Register 6

Reserved for factory test. Do not write to this register.

4-373

4-374

2 Detailed Description
2.1 Device Functions
2.1.1

Operating Frequencies

If the sampling frequency is higher than 7 kHz, the sampling frequency is derived from the master clock
(MCLK) input by either equation 1 or 2.
fs

=

Sampling (conversion) frequency

= 12~C~K N

(when bit 07 of register 4 is set to 0) (1)

51~C~K N

(when bit 07 of register 4 is set to 1) (2)

fs = Sampling (conversion) frequency =

If the sampling frequency is lower than 7 kHz, the sampling frequency is derived from the master clock
(MCLK) using equation 2 only, which bypasses the PLL. Equation 2 must be used in this case because the
PLL input clock for sampling frequencies lower than 7 kHz is outside of the working range for the PLL input
clock.
The inverse of the sampling frequency is the time between the falling edges of two successive primary
frame-sync signals. This time is the conversion period.
For example, to set the conversion rate to 8 kHz,
•

when bit 07 of register 4 is set to 0, use equation 1 to determine MCLK (MCLK = 128 x N x 8000)

•

when bit 07 of register 4 is set to 1, use equation 2 to determine MCLK (MCLK = 512

x N x 8000)

To set the conversion rate to 4 kHz,
•

2.1.2

bit 07 of register 4 must be set to 1 to bypass the PLL, then use equation 2 to determine MCLK
(MCLK = 512 x N x 4000)

ADC Signal Channel

The input signal is amplified and applied to the AOC input. The AOC converts the signal into discrete output
digital words in 2's-complement data format, corresponding to the instantaneous analog-signal value at the
sampling time. These 16-bit (or 15-bit) digital words, representing sampled values of the analog input signal
after the PGA, are clocked out of the serial port (OOUT) at the positive edge of SCLK during the frame-sync
interval, one bit for each SCLK and one word for each primary communication interval (256 SCLKs).
Ouring secondary communication, the data previously programmed into the registers can be read out. This
read operation is accomplished by sending the appropriate register address (OS12 - OS8) with the read
bit (OS13) set to 1 in through OIN during present secondary communication. If a register read is not
requested, all 16 bits are cleared to 0 in the secondary communication. The timing sequence is shown in
figure 2-1 and figure 2-2.

4-375

2

15

16

17

SCLK

I
I
I

FS
DOUT
(16-Bit)

D15
MSB

DOUT
(15+ 1-Bit)

D15

~

~

I
I
I
D14

D14

>C ~
>C j<

I
I
I
D1

D1

~
~

DO
LSB

MIS

MSB
LSB
NOTES: A. Mis is used to indicate whether the 15·bit data comes from master device or slave device.
(Master: MIS = 1, Slave MIS = 0)
B. The MSB (D15) is stable (the host can latch the data in at this time) at the falling edging of SCLK #1, the
last bit (DO,M/S) is stable at the falling edging of SCLK #16.

Figure 2-1. Timing Sequence of ADC Channel (Primary Communication Only)

14-

DOUT
(16-Bit)

Primary
16 SCLKs

t

Secondary

-.I

t

. >----

k

i 16-Bit ADC Data

I

t

t

--ki

>---- --k

MIS + Register Address +

I

Register Datal

All Os (see Note)

>---- ---<

ik15-Bit ADC2 Data
I
J4

t

i MIS + Register Address +

I
I
DOUT
(15 +l-Bit)

Primary

M- 16 SCLKs -.I

+ MIS

128SCLKs

I

i

I
I
I
I

>---- --k

MIS + Register Datal
MIS + All 0 (see Note)

I
I
I
I
..I

~
256 SCLKs
NOTE: Mis bit (DS15) in the secondary communication is used to indicate whether the register data (address and
content) comes from the master device or the slave device if the read bit is set. During register read operations,
bits DS7 - DSO are the contents of the specified register. In register write operations, bits DS7 - DSO are all Os.

I..

Figure 2-2. Timing Sequence of ADC Channel (Primary and Secondary Communication)

2.1.3

DAC Signal Channel

DIN receives the 16-bit serial data word (2's complement) from the host during the primary communications
interval. These 16-bit digital words, representing the analog output signal before PGA, are clocked into the
serial port (DIN) at the falling edge of SCLK during the frame-sync interval, one bit for each SCLK and one
word for each primary communicatiol1 interval (256 SCLKs). The data are converted to a pulse train by the
sigma-delta DAC, which consists of a digital interpolation filter and a digital modulator. The output of the
modulator is then passed to an internal low-pass filter to complete the analog signal reconstruction. Finally,
the resulting analog signal is applied to the input of a programmable-gain amplifier, which is capable of
driving a 600-Q load differentially at OUTP and OUTM. The timing sequence is shown in figure 2-3.
4-376

1

15

2

17

16

SCLK
I
I
I

FS

I
I
I

~15 X

DIN
(16-Bit)

MSB .
DIN
(15+ 1-Bit)

d15
MSB

X

:014
I
d14

=x
=x

I

I

I

I

I

I

:01
I
d1

X
X

:00

>)-----

ILSBI

dO=O ) .....- - -

ILSB

I '-I
See Note

NOTE: dO = 0 means no secondary communication request (software secondary communication request control paragraph 3.2)

Figure 2-3. Timing Sequence of DAC Channel (Primary Communication Only)
During secondary communication, the digital control and configuration data (together with the register
address), are clocked in through DIN. These 16-bits of data are used either to initialize the register, or to
read the register content through DOUT. If a register initialization is not required, a no-operation word (DS15
- DS8 are all set to 0) can be used. If DS13 is set to 1, the content of the control register, specified by
DS12-DS8, will be sent out through DOUT during the same secondary communication (see section 2.1.5).
The timing sequence is shown in figure 2-4.
Primary

14-

t
DIN (16-Bit) _ _
(see Note A)
DIN
(15 +1-Bit)

-elK

i

.

----(K

16 SCLKs

r->-

-.I

.
16-Bit DAC Data

14

1

--ki

t

>- --k
>- -{,.---

Register Read/Write

>- -{

I 1S-Bit DAC Data
I
+ DO=1
I (see Note B)

Primary

Secondary
__ 16 SCLKs -.I

I Register Read/Write
I
I

128 SCLKs --~~

1'-'--I
I
I
I
I

~~----------------256SCLKs------------~~1

NOTES: A. FC has to be set high for a secondary communication request when 16-bit DAC data format is used
(paragraph 3.2).
B. DO = 1 means secondary communication request (software secondary communication request control paragraph 3.2).

Figure 2-4. Timing Sequence of DAC Channel (Primary and Secondary Communication)

4-377

2.1.4

Serial Interface

The digital serial interface consists of the shift clock (8CLK), the frame-sync signal (F8), the ADC-channel
data output (DOUT), and the DAC-channel data input (DIN). During the primary frame synchronization
interval, 8CLK clocks the ADC channel results out through DOUT and clocks 16-bitl(15+ 1)-bit DAC data
in through DIN.
During the secondary frame-sync interval, 8CLK clocks the register read data out through DOUT if the read
bit (D813) is set to 1 and transfers control and device parameter in through DIN. The timing sequence is
shown in Figures 2~2 and 2-4.

2.1.5

Register Programming

All register programming occurs during secondary communications through DIN, and data are latched and
valid on the falling edge of 8CLK during the frame-sync signal. If the default value for a particular register
is desired, that register does not need to be addressed during the secondary communications interval. The
no-op command (D815 - D88 all set to 0) addresses the pseudo-register (register 0), and no register
programming takes place during the communications.
In addition, each register can be read back through DOUT during secondary communications by setting the
read bit (D813) to 1. When the register is in the read mode, no data can be written to the register during this
cycle. D813 must be cleared to write to the register.
For example, if the contents of control register 1 is desired to be read out from DOUT, the following procedure
must be performed through DIN:
1.

Request secondary communication by setting either DO = 1 (software request) or FC
(hardware request) during the primary communication interval.

= high

2.

At the secondary communication interval (F8), send data in the following format in through DIN:

°lo1110101010111xlxlxlxlxlxlxlxl
D815

D80
3.

Then the following data is read from DOUT, with the last 8 bits containing the register 1 data.

a 1 a 1 1 '1 a 1 a 1 a 1 a 1 1

d

d

d

d

d

d

D815

D80

Figure 2-5 is a timing diagram of this procedure.

Low 8 Bits (D80-D87) are the
Content of Register 1

Figure 2-5. Register 1 Read Operation Timing Diagram

4-378

If control register 1 needs to be programmed, the following procedure must be performed through DIN:
1.

Request secondary communication by setting either DO = 1 (software request) or Fe = high
(hardware request) during the primary communication interval.

2.

At the secondary communication interval (FS), send data in the following format in through DIN:

Low 8 Bits (DSO-DS7)
are a" 0
Figure 2-6. Register 1 Write Operation Timing Diagram

4-379

2.1.6

Sigma-Delta ADC

The sigma-delta analog-to-digital converter in the device is a sigma-delta modulator with 64-X
oversampling. The ADC provides high-resolution, low-noise performance using oversampling techniques.
Due to the oversampling employed, only single-pole antialiasing filters are required on the analog inputs.

2.1.7

Decimation Filter

The decimation filters reduce the digital data rate to the sampling rate. This is accomplished by decimating
with a ratio of 1:64. The output of the decimation filter is a 16-bit 2's-complement data word clocking at the
sample rate selected for that particular data channel. The bandwidth of the filter is 0.439 x 'sample and scales
linearly with the sample rate.

2.1.8

Sigma-Delta DAC

The sigma-delta digital-to-analog converter in the device is a sigma-delta modulator with 256-X
oversampling. The DAC provides high-resolution, low-noise performance using oversampling techniques.

2.1.9

Interpolation Filter

The interpolation filter resamples the digital data at a rate of 256 times the incoming sample rate. The
high-speed data output from the interpolation filter is then used in the sigma-delta DAC. The bandwidth of
the filter is 0.439 x fsample and scales linearly with the sample rate.

2.1.10

Analog and Digital Loopback

The analog and digital loopbacks provide a means of testing the modem data ADC/DAC channels and can
be used for in-circuit system-level tests. The analog loopback routes the DAC low-pass filter output into the
analog input where it is then converted by the ADC into a digital word. The digitalloopback routes the ADC
output to the DAC input on the device and is enabled by setting bit D1 in control 1 register to 1. Analog
loopback is enabled by setting bit D3 in control 2 register to 1 (see section 6).

2.1.11

FIR Overflow Flag

The decimator FIR filter sets an overflow flag (bit D5) of control 2 register to indicate that the input analog
signal has exceeded the range of the internal decimation filter calculations. Once the FIR overflow flag has
been set in the register, it remains set until the register is read by the user. Reading this value resets the
overflow flag.
'
If FIR overflow occurs, the input signal must be attenuated either by the PGA or some other method.

4-380

2.2

Reset and Power-Down Functions

2.2.1

Software and Hardware Reset

The TLC320AD50C and TLC320AD52C reset the internal counters and registers in response to either of
two events:
1.

A low-going reset pulse is applied to terminal RESET

2.

A 1 is written to the programmable software reset bit (D7 of control register 1)

Either event resets the control registers and clears all the sequential circuits in the device. Reset signals
should be at least 6 master clock periods long.

2.2.2

Software and Hardware Power Down

Most of the device (all except the digital interface) enters the power-down mode when D6 in control register
1 is set to 1. When PWRDWN is taken low, the entire device is powered down. In either case, the register
contents are preserved and the output of the monitor amplifier is held at the midpoint voltage to minimize
pops and clicks.
The amount of power drawn during software power down is higher than it is during a hardware power down
because of the current required to keep the digital interface active. Additional differences between software
and hardware power-down modes are detailed in the following paragraphs. Figure 2-7 represents the
internal power-down logic .

.-------------------------,
I

PWRDWN

I
I
I
I
D6 is Programmed
Software Power Down
I
Through
a Secondary
(Control
Register
1,
D6)
I
Write Operation
I
I
IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~
I Internal TLC320AD50C
Figure 2-7. Internal Power-Down Logic

2.2.2.1

Software Power Down

When D6 of control register 1 is set to 1, the device enters the software power-down mode. In this state,
the digital interface circuit is still active while the internal ADC and DAC channels and differential outputs
OUTP and OUTM are disabled, and DOUT and FSD are inactive. Register data in the secondary serial
communications is still accepted but data in the primary serial communications is ignored. The device
returns to normal operation when D6 of control register 1 is reset to o.

2.2.2.2

Hardware Power Down

When PWRDWN is held low, the device enters the hardware power-down mode. In this state, the internal
clock control circuit and the differential outputs OUTP and OUTM are disabled. All other digital II0s either
are disabled or remain in the state they were in immediately before power down. DIN cannot accept any data
input. The device can only be returned to normal operation by taking and holding PWRDWN high. When
not holding the device in the hardware power-down mode, PWRDWN should be tied high.

4-381

2.3

Master Clock Circuit

MCLK is the external master clock input. The internal clock circuit gene~ates and distributes necessary
clocks throughout the device. An internal PLL circuit is used for upsampling to provide the appropriate clocks
for the digital filters and modulators.
When the device is in the master mode, SCLK and FS are derived from MCLK in order to provide clocking
of the serial communications between the device and a DSP (digital signal processor). When in the slave
mode, SCLK and FS are both inputs.

2.4

Data Out (DOUT)

DOUT is placed in the high-impedance state on the rising edge of the frame sync. In the primary
communication, the data word is the ADC conversion result. In the secondary communication, the data is
the register-read results when requested by the read/write (R/W) bit. If a register read is not requested, the
low eight bits of the secondary word is all zeroes. The state of the master/slave (MiS) terminal is reflected
by the MSB in secondary communication (DOUT, bit DS15) and the LSB in the primary communication
(DOUT, bit DO). When the device is in the slave mode, DOUT remains in a high-impedance state until a
nonzero value is written as a number of slaves in control register 3 (bits D7 and D6).

2.4.1

Data Out, Master Mode

In the master mode, DOUT is taken from the high-impedance state by the falling edge of the master frame
sync (FS). The most significant data bit then appears first on DOUT.

2.4.2

Data Out, Slave Mode

In the slave mode, DOUT is taken from the high-impedance state by the falling edge of the frame sync (FS).
The most significant data bit then appears on DOUT. When in the slave mode, DOUT is not enabled until
the control 3 register is programmed with the number of slaves. This must be done even if there is only one
slave device.

2.5

Data In (DIN)

In a primary communication, the data word is the input digital signal to the DAC channel. If the (15+ 1)-bit
data format is used, the LSB (DO) is used to request a secondary communication. In a secondary
communication, the data is the control and configuration data that sets the device for a particular function
(see Section 3, Secondary Serial Communication for details).

2.6

FC (Hardware Secondary Communication Request)

The FC input provides for hardware requests for secondary communications. FC works in conjunction with
the LSB of the primary data word. The signal on FC is latched on the rising edge of the primary frame sync
(FS). FC should be tied low if not used.

2.7

Frame-Sync Function for TLC320AD50C

The frame-sync signal (FS) indicates the device is ready to send and receive data. The data transfer out
of DOUT and into DIN begins on the falling edge of the frame-sync signal.

4-382

2.7.1

Frame Sync (FS) Function, Master Mode

The frame sync is generated internally and goes low on the rising edge of SCLK and remains low during
a 16-bit data transfer. In addition to generating its own frame-sync signal, the master also outputs a frame
sync for each slave that is being used (see figures 2-8 and 2-9).
SCLK

-ulfL
J..-

t

FS
(see Note A)

l

FS
(see Note 8)

Primary

I

Secondary I
l.-- 16 SCLKs -.I

r-

-.I

t

~

>-

~
256 SCLKs

J4

Primary

I
I

---K

128 SCLKs

Primary

1

I
I
I

>-

k

DIN/DOUT

-f1-I JlfUl rlflJ JlflJL
t l
i

Primary
16 SCLKs

--K
I
I

·1

NOTES: A. Primary and secondary serial communication.
B. Primary serial communication, only.

Figure 2-8. Master Device Frame-Sync Signal With Primary and Secondary Communications
(No Slaves)

seLK

lJlfl

FS
(see Note A)
FS
(see Note 8)
Delay is m Shift Clock
(see Note C)

I

-flr- ~ -fl n.r -fl ~-i -fl ~

IMP,

l

I MP

1-

14

l-::I
I

I

i

I

I

I

~

~~ ~

~

I-I_s_p......

I

~

I

r---

"
I
~

I

.1

I
-----------..~

128 SCLKs

..
~ - - - - - - - - 256 SCLKs

NOTE: MP: Master Primary (master device data is transferred in this period, DOUT of the slave device device is in high
impedance state).
SP: Slave Primary (slave device data is transferred in this period, DOUT of master device device is in high
impedance state).
MS: Master Secondary (master device control register information is transferred in this period, DOUT of the slave
device is in high impedance state).
SS: Slave Secondary(slave device control register information is transferred in this period, DOUT of the master
device is in high impedance state}.
NOTES: A. Primary and secondary serial communications
B. Primary serial communication only
C. m is the value programmed into the FSD register (control register 3: DO-D5)

Figure 2-9. Master Device Frame-Sync Signal With Primary and Secondary Communications
(With 1 Slave Device)

4-383

2.7.2

Frame Sync (FS) Function,Slave Mode

Frame-sync timing is generated externally by the master FSD and is applied to FS of the slave to control
the.ADC and DAC timing.

2.7.3

Frame-Sync Delayed (FSD) Function, Master Mode

For the master, the FSD (frame-sync delayed) output occurs 1/4 shift-clock period ahead of FS to
compensate for the time delay through the master and slave devices. The timing relationships are as follows:
•

When the FSD register (control 3 register) data is 0, then FSD goes low 1/4 SCLK prior to the
rising edge of SCLK when FS goes low (figure 2-10).

•

When the FSD register data is greater than 17, then FSD goes Iowan the rising edge of SCLK
that is the FSD register number of SCLKs after the falling edge of FS (figure 2-11).

Register data values from 1 to 17 result in a default register value of zero and should not be used.

SCLK

FS
(P and S)+
FSD
(P and S)+
FS (P)+

J1lflJl
tJ1JUW
JlJlJruL
nJlfL
II
I
II
I

I

!

-----II i
-----IIiI

MP and sPt

I
I

I
I
!

MS and sst

rI

(I,...---------

t The DIN of master and slave devices share the same DIN bus during first initialization. The DOUT is occupied by Master
device only until the control register 3 of master and slave device is programmed with slave devices number and number
of SCLKs between FS and FSD (m>17).
P&S: Primary and secondary communications P: Primary communication only

+

Figure 2-10. Master Device FS and FSO Output When FSO Register (00-05, Control Register 3)
isO

4-384.

NOTES: A. Since Master and slave share the same DIN bus during first initialization, they share the same input data
word. Only one write cycle is needed to program control register 3 of master device and slave device(s).
B. After the control register 3 is programmed, the DIN or DOUT bus of master and slave(s) are separated by
time, although they still physically connect to each other.

Figure 2-11. Master Device FS and FSD Output After Control Register 3 Is Programmed (One
Slave Device)

4-385

2.7.4

Frame-Sync Delayed (FSD), Slave Mode

The master FSD is output to the first slave and the first slave FSD is output to the second slave device and
so on (see figure 2-12). The FSD output of each device is input to the FS terminal of the succeeding device.
The FSD timing sequence in the slave mode is as follows:
•

When the FSD register data is 0, then FSD goes low 114 SCLK cycle before FS goes low.

•

When the FSD register data is greater than 17, then FSD goes low on the rising edge of SCLK
that is the FSD register number of SCLKs after the falling edge of FS (see figure 2-13).

Data values from 1 to 17 should not be used.
CLKOUT
OX
DR

......
CLKOUT

FSX
FSR

:=L

DIN
FS

...
...

,

..
r

DOUT

CLKX

4--4.4--4_

FS

-+

SCLK
Master

TMS320C5X
TMS320C2X
TMS320C54X

......

MCLK

---.-

~ DIN

DIN

DOUT

DOUT

FSD

CLKR

+-

MCLK

FS

FSD

SCLK

r-+

DIN
DOUT
FS

FSD

-+-

SCLK

SCLK
Slave 3

Slave 2

Slave 1

MCLK

Figure 2-12. Master With Slaves (To OSP Interface)
p

p

p

p

S

S

S

Master FS

u

Master FSD
Slave 1 FS

Slave 1 FSD
Slave 2 FS
Slave 2 FSD
Slave 3"FS

u

u

L

Slave 3 FSD
(see note)
128 SCLKs --------+~I
NOTE: Slave 3 FSD cannot be used.

Figure 2-13. Master-Slave Frame-Sync Timing After A Delay Has Been Programmed Into The
FSO Register (00-05 of Control Register 3)

4-386

2.8

Frame-Sync Function for TLC320AD52C

The frame-sync function for TLC320AD52C is very similar to that of the TLC320AD50C except the following:
1.

TLC320AD52C can support only one slave.

2.

The FSD terminal function can be disabled for TLC320AD52C by programming bit 02 in control
2 register.

3.

The FSD value need to be multiplied by 2 for actually number of SCLK delay.

For example, if FSD register (control register 3) is programmed with 49H, it means that the TLC320AD52C
has one slave and the FSD terminal has 18 SCLKs delay after master primary FS output. See figure 2-14.

FS

I

I

FSD
Delay is ~18
SCLKst

I
I
I

r-

U
I

~

~

~

128 SCLKs

I
I
I
I
I

~

I

U
I
I
I

I
I
I
I

I
I
I
I
I
I

L

256 SCLKs
~
t Minimum SCLK delay number in FSD register is 9. This means that a delay of at least 18 SCLKs is required for proper
operation of the TLC320AD52C.

Figure 2-14. Master Device FS and FSD Output After Control Register 31s Programmed with 49H

4-387

2.9

Multiplexed Analog Input and Output

The two differential analog inputs (INP and INM or AUXP and AUXM) are multiplexed into the sigma-delta
modulator. The performance of the AUX channel is similar to the normal input channel. A single-pole
antialias filter must be connected to INP and INM (also AUXP and AUXM, if used). If an RC is used for the
single"pole filter (Figure 2-1S) the value of R should not be grater that 1 kg. The gain of the input amplifiers
is set by through the control 4 register.
.
R
IN+
C
R
IN-

T-=

~~~~---.------~

INM

CT
NOTES: A. The bandwidth of this RC antialias is determined by: (fa
B. AUXP and AUXM need to connect to AVSS if not used.
C. Bandwidth of the anti-alias filter can be 4 x fs .

= 1/(21t RC))

Figure 2-15. RC Antialias Filter

2.9.1

Multiplexed Analog Input

To produce the best possible common-mode rejection of unwanted signal performance, the analog signal
is processed differentially until it is converted to digital data. The signal applied to the terminals INM and INP
should be differential to preserve the device specifications. As much as 6 dB of signal level will be lost if the
single-ended input is used directly. The signal source driving the analog inputs (INP and INM or AUXP and
AUXM) should have a low source impedance for best low-noise performance and accuracy.
To obtain maximum dynamic range, the signal should be AC coupled to the input terminal. The analog input
signal is self-biased to the mid-supply voltage if the monitor-amplifier input source is selected as the same
source for the AOC input. These input sources are selected by bits 04 and OS of control 1 register. The
default condition self-biases the input since the register default value selects INP and INM as the source
for both the AOC and monitor amplifier input (see figure 2-16). A simple single-pole anti alias filter with low
output impedance must be connected to INP and INM (also AUXP and AUXM, if used).
INP

VINP -t.~----\r-------t--e---.

2.SV
INM

VINM --I•..------If-----+_e-_..

Figure 2-16. INP and INM Internal Self-Biased (2.5 V) Circuit

4-388

2.9.2

Analog Output

The OUTP and OUTM are differential outputs and can drive a typical 600-Q load directly. Figure 2-17 shows
the circuit when load is ground referenced.
10 kQ

5V

OUTM

10 kQ

r---~NV----'_,

OUTP r-----I\NV----._--I
10 kQ

TLE2062
-5V

Load

10 kQ

-=
Figure 2-17. Differential Output Drive (Ground Referenced)

4-389

4-390

3 Serial Communications
DOUT, DIN, SCLK, FS, and FC are the serial communication signals. The digital output data from the ADC
is taken from DOUT. The digital input data for the DAC is applied to DIN. The synchronizing clock for the
serial communication data and the frame sync is taken from SCLK. The frame-sync pulse that encloses the
ADC and DAC data transfer interval is taken from FS. For signal data transmitted from the ADC or to the
DAC, primary serial communication is used. To read or write words that control both the options and the
circuit configurations of the device, secondary communication is used.
The purpose of the primary and secondary communications is to allow conversion data and control data to
be transferred across the same serial port. A primary transfer is always dedicated to conversion data. A
secondary transfer is used to set up and/or read the register values. A primary transfer occurs for every
conversion period. A secondary transfer occurs only when requested. Secondary serial communication can
be requested either by hardware (FC terminal) or by software (DO of primary data input to DIN).

3.1

Primary Serial Communication

Primary serial communication is used both to transmit and receive conversion signal data. The DAC word
length depends on the state of bit DO in control 1 register. After power up or reset, the device defaults to the
15-bit mode. When the DAC word length is 15 bits, the last bit of the primary 16-bit serial communication
word is a control bit used to request secondary serial communication. In the 16-bit mode, all 16 bits of the
primary communication word are used as data for the DAC and the hardware terminal FC must be used to
request secondary communication.
Figure 3-1 shows the timing relationship for SCLK, FS, DOUT and DIN in a primary communication. The
timing sequence for this operation is as follows:
1.

FS is brought low by the TLC320AD50C or TLC320AD52C.

2.

A 16-bit word is transmitted from the ADC (DOUT) and a 16-bit word is received from the DAC
(DIN).

3.

FS is brought high by the TLC320AD50C or TLC320AD52C, signaling the end of the data
transfer.

•••

SCLK

I--t.......,..--------~~----------T---T--I
DIN---(

DOUT--.J
Figure 3-1. Primary Serial Communication Timing

4-391

3.2

Secondary Serial Communication

Secondary serial communication is used to read or write 16-bit words that program both the options and the
circuit configurations of the device. Register programming always occurs during secondary communication.
Four primary and secondary communication cycles are required to program the four registers. If the default
value for. particular register is desired, then the register addressing can be omitted during secondary
communications. The NOOP command addresses a pseudo-register, register 0, and no register
programming takes place during this secondary communication. If secondary communication is desired for
any device (either master or slave), then a secondary communication must be requested for all devices,
starting with the master. This results in a secondary frame sync (FS) for all devices. The NOOP command
can be used for devices that do not need a secondary operation.
During a secondary communication, a register may be written to or read from. When writing a value to a
register, DIN contains the value to be written. When reading the value in a register, the data is stepped out
on DOUT.
There are two methods for initiating secondary communications:
1.

by asserting a high level on FC

2.

by asserting the LSB of the DIN 16-bit serial communication high while in the15-bit mode

Both methods are illustrated in figure 3-2.

,-------------------------,

FC ---II----------------'r-.......
Se~ondary
(Hardware)
,---,'--" >--- Request
(LSB of DIN)

-----I-~

16-Bit Mode

II
I
II

I
(Control 1 Register, Bit 0)
L
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_________ I
I Internal TLC320AD50C
~

~

Figure 3-2. Hardware and Software Methods to Make a Secondary Request

FC should be pulled high before the rising edge of the frame sync (FS). This causes the start of the
secondary communication, 128 SCLKs after the start of the primary communication frame. If slaves are
present, FC should remain high until the rising edge of the frame sync for the last slave.
The second method for secondary communication is by asserting the LSB high. A software request is
typically used when the request resolution of the DAC channel is less .16 bits. Then the least significant bit
(DO) can be used for the secondary requests as shown in table 3-1. The request is made by placing the
device. in the 15-bit DAC mode and making the LSB of DIN high. All devices should be in the 15-bit DAC
mode and secondary communication should be requested for all devices.
Table 3-1. Least Significant Bit Control Function
CONTROL BIT DO

CONTROL BIT FUNCTION

0

No operation (NOOP)

1

Secondary communication request

If a secondary communication request is made, FS goes low after 128 SCLKs after the beginning of the
primary frame.

4-392

3.2.1

Hardware Secondary Serial Communication Request

The FC requests a secondary communication when it is asserted. The FC terminal is latched at the rising
edge of FS (primary communication), so FC should be pulled high before the rising edge of the primary frame
sync (FS). FC needs to have a bounce from high to low and then back to high (1--70--71) if another secondary
serial communication is desired. Otherwise (FC kept high or low), there is no additional secondary
communication. Figures 3-3 and 3-4 show the FS output from a master device.
FS

~
I

~

I Secondary

I

~~p---!r

I

~ No Secondary

I

I Request
I

Request
FC
ADC Data Out

DOUT

DAC Data In

DIN

~

>---

DAC Data In

Figure 3-3. FS Output When Hardware Secondary Serial Communication Is Requested Only
Once (No Slave)

I

p

p

pi

S

S

S

S

MI

S1

S2

S3 1

M

S1

S2

S3

p
FS
(Master)
FC
(See Note)

~I
1

p

1

V

1

1
1
1

NOTE: Fe of master device and slave devices should connect together

Figure 3-4. FS Output When Hardware Secondary Serial Communication Is Requested Only
Once (Three Slaves)

3.2.2

Software Secondary Serial Communication Request

The LSB of the OAC data within a primary transfer can request a secondary communication when the device
is in the 15-bit mode.
For all serial communications, the most significant bit is transferred first. For a 16-bit AOC word and a 16-bit
DAC word, 015 is the most significant bit and DO is the least significant bit. For a 15-bit DAC data word in
a primary communication, 015 is the most significant bit and 01 is the least significant bit. Bit 00 is then used
for the secondary communication request control. All digital data values are in 2's complement data format
(figure 3-5).
If the data format is set to the 16-bit word mode, all 16 bits are either ADC or DAC data and secondary
communication can then be requested only by hardware (FC terminal).

4-393

FS

~ ~ t
I

I

DIN

~

Data (DO = 1)

~

I

I

I

~

Register
Read/Write

P

~ ~

I

Secondary Communication
Request

TI

I
Data (DO = 0)

I

~

No Secondary Communication
Request

NOTE: See figure 3-8 for secondary communication DIN data format

Figure 3-5. FS Output During Software Secondary Serial Communication Request (No Slave)

3.3

Conversion Rate Versus Serial Port

The SCLK frequency is set equal to the frequency of the frame-sync signal (FS) multiplied by 256. The
conversion rate or sample rate is equal to the frequency of FS.

3.4

Phone Mode Control

Phone mode control is provided for applications that need hardware control and monitoring of external
events. By allowing the device to drive the FLAG terminal (set through control 2 register), the host DSP is
capable of system control through the same serial port that connects the device. Along with this control is
the capability of monitoring the value of the ALTDATA terminal during a secondary communication cycle.
One application for this function is in monitoring RING DETECT or OFFHOOK DETECT from a phone
answering system. FLAG allows response to these incoming control signals. Figure 3-6 shows the timing
associated with this operating mode.
P

FS

~~__________~

S

Register Data
(8-Bits)
DOUT
(see Note A)
DOUT
(see Note B)

ALTDATA
NOTES: A. When DIN performs a read operation (set 013 to 1) during secondary communication.
B. When DIN perform a write operation (set 013 to 0) during secondary communication.

Figure 3-6. Phone Mode Timing When Phone Mode is Enabled

4-394

3.5

DIN and DOUr Data Format

3.5.1

Primary Serial Communication DIN and DOUr Data Format (Figure 3-7)

DIN
(15+ 1) Bit Mode

I

D15 - D1
\

v
/\

\

DOUT
(15+1) Bit Mode

D15 - 01

DIN
16-Bit Mode

D15- DO
\

I'
I
I

Secondary
Communication Request

AID and DfA Data
/

DO

I

DO

I

l'M/SBU

v
AID and DfA Data
A

/
\
DOUT
D15- DO
16-Bit Mode
Figure 3-7. Primary Communication DIN and DOUT Data Format

3.5.2

Secondary Serial Communication DIN and DOUr Data Format (Figure 3-8)
Don't Care
D813=1

A·

I

DIN (Read)

D87 - D80

\

I

V
Register Address

/

A

V

DIN (Write)

Data to the
Register
/\'---"""'\
D87- D80

D813=0

Register Data

D813=1

A

/

DOUT (Read)
(Phone Mode Disabled)

\

D87-D80

/

I

V
Register Address

M/8

~
DOUT (Write)

A

All 0
A

V

\

D87-D80

(Phone Mode Disabled)
D813=0

DOUT (Read)
(Phone Mode Enabled)

D815 - D88: ALTDATA

D815 - D88: Register Data

DOUT (Write)
D815 - D88: ALTDATA
(Phone Mode Enabled)
Figure 3-8. Secondary Communication DIN and DOUT Data Format
4-395

4-396

4 Specifications
4.1

Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)t
Supply voltage range, DVoo AVoo (see Note 1) ..................... -0.3 V to 7 V
Output voltage range, DOUr, FS, SCLK, FLAG ............. -0.3 V to DVoo + 0.3 V
Output voltage range, OUTP, OUTM ........................ -0.3 V to Voo + 0.3 V
Input voltage range, DIN, PWRDWN, RESET, ALT DATA ,
MCLK, FC ......................................... -0.3 V to DVOO + 0.3 V
Input voltage range, INP, INM, AUXP, AUXM ................ -0.3 V to VOO + 0.3 V
Case temperature for 10 seconds: OW package ............................ 260°C
Operating free-air temperature range, TA ............................ O°C to 70°C
Storage temperature range, Tstg ................................. -65°C to 150°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for
extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.

4.2

Recommended Operating Conditions
MIN

Supply voltage, AVDD (see Note 2)
Analog signal input voltage, VI (analog)

NOM

4.75

I

Differential (INP-INM) peak,
for full scale operation

Differential output load resistance, OUTP, OUTM, RL

MAX
5.5

V

6

V

15

pF

600

Differential output load capacitance, OUTP, OUTM, CL
ADC or DAC conversion rate

8

Operating free-air temperature, TA

0

UNIT

l.!

22.05

kHz

70

°C

NOTE 2: Voltages at analog inputs and outputs and VDD are with respect to the VSS terminal.

4.2.1

Recommended Operating Conditions, DVoo

=5 V
MIN

Supply voltage, DVDD (see Note 2)

NOM

4.5

High-level input voltage, VIH

MAX
5.5

V
V

2
0.8

Low-level input voltage, VIL
MCLK frequency

UNIT

8.192

V

11.290

MHz

UNIT

NOTE 2: Voltages at analog inputs and outputs and VDD are with respect to the VSS terminal.

4.2.2

Recommended Operating Conditions, DVoo

=3 V
MIN

NOM

MAX

Supply voltage, DVDD (see Note 2)

2.7

3

3.3

High-level input voltage, VIH

1.8

V
0.6

Low-level input voltage, VIL
MCLK frequency

V

8.192

11.290

V
MHz

NOTE 2: Voltages at analog inputs and outputs and VDD are with respect to the VSS terminal.
4-397

4.3

Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, DVDD 5 V, RL 600 n (Unless Otherwise Noted)

4.3.1

=

Digital Inputs and Outputs, MCLK

=

=8.192 MHz, fs =8 kHz, Outputs Not Loaded

PARAMETER

TEST CONDITIONS

VOH

High-level output voltage, DOUT

VOL

Low-level output voltage, DOUT

10= 2 mA

IIH

High-level input current, any digital input

VIH = 5 V
VIL = 0.8 V

10 = 360 I!A

MIN

rvp

2.4

4.6
0.2

MAX

UNIT
V

0.4

V

10

I!A

10

I!A

IlL

Low-level input current, any digital input

Cj

Input capacitance

5

pF

Co

Output capacitance

5

pF

4.3.2

Digital Inputs and Outputs, MCLK
DVoo 3 V

=

=8.192 MHz, fs =8 kHz, Outputs Not Loaded,

PARAMETER

TEST CONDITIONS

MIN

TVP

2.4

4.6

MAX

UNIT

VOH

High-level output voltage, DOUT

10 = 360 I!A

VOL

Low-level output voltage, DOUT

10 = 2 mA

IIH

High-level input current, any digital input

IlL

Low-level input current, any digital input

Cj

Input capacitance

5

pF

Co

Output capacitance

5

pF

',4.3.3

ADC Path Filter, MCLK

0.2

V
0.4

V

VIH = 3 V

10

I!A

VIL = 0.6 V

10

I!A

=8.192 MHz, fs =8 kHz (see Note 3)

PARAMETER

TEST CONDITIONS

o to 300 Hz
Filter gain relative to gain at 1020 Hz

MIN

TVP

MAX

-0.5

0.2

300 Hz to 3 kHz

-0.25

0.25

3.3 kHz

-0.35

0.3

3.6 kHz

-3

4 kHz

-40

~

-74

4.4 kHz

UNIT

.dB

NOTE 3: The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The analog input test
signal is a sine wave with 0 dB = 4 Vpp as the reference level for the analog input signal. The passband is 0
to 3600 Hz for an 8-kHz sample rate. This passband scales linearly with the sample rate.

4.3.4
4.3.4.1

ADC Dynamic Performance, MCLK

=8.192 MHz, fs =8 kHz

ADC Signal-to-Noise (see Note 4)
PARAMETER

Signal-to-noise ratio (SNR)

MIN

TVP

VI = -1 dB (5.35 V)

TEST CONDITIONS

85

89

VI = -9 dB (2.13 V)

77

81

VI = -40 dB (60 mY)

46

50

VI = -65 dB (3 mY)

21

25

VAUX =-9dB

77

81

MAX

UNIT

dB

NOTE 4: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output are referenced
to AVDO/2.
4-398

4.3.4.2

ADC Signal-to-Distortion (see Note 4)
PARAMETER

Signal-to-total harmonic distortion (THO)

MIN

TYP

VI = -3 dB (4.25 V)

TEST CONDITIONS

80

85

VI =-9 dB (2.13 V)

79

90

VI = -40 dB (60 mV)

67

72

VI = -65 dB (3 mV)

43

48

VAUX=-9dB

79

90

MAX

UNIT

dB

NOTE 4. The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output are referenced
to VDD/2.

4.3.4.3

ADC Signal-to-Distortion + Noise (see Note 4)
PARAMETER

Signal-to-total harmonic distortion + noise (THO + N)

MIN

TYP

VI = -3 dB (4.25 V)

TEST CONDITIONS

78

82

VI = -9 dB (2.13 V)

76

80

VI = -40 dB (60 mV)

45

49

VI = -65 dB (3 mV)

20

24

VAUX=-9dB

76

80

MAX

UNIT

dB

NOTE 4. The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output are referenced
to VDO/2.

4.3.5

ADC Channel Characteristics
PARAMETER

VI(PP)

TEST CONDITIONS

MIN

Peak-to-peak input voltage
Dynamic range

VI = -1 dB (5.35 V)

Interchannel isolation
EG

Gain error

EO~ADC)

AOC converter offset error

CMRR

Common-mode rejection ratio at INM,
INP or AUXM, AUXP

Rj

VI = -1 dB at 1020 kHz

VI = -1 dB at 1020 kHz

Idle channel noise (on-chip reference)

VINP, INM = 2.5 V

Input resistance

TA = 25°C

MAX

UNIT

6

V

88

dB

100

dB

±0.3

dB

5

mV

74

dB
75

/lVrms
k1"2

35

Channel delay

4.3.6

TYP

s

17/fs

DAC Path Filter, MCLK = 8.192 MHz, fs = 8 kHz (see Note 5)
PARAMETER

TEST CONDITIONS

oto 300 Hz
Filter gain relative to gain at 1020 Hz

MIN

TYP

MAX

-0.5

0.2

300 Hz to 3 kHz

-0.25

0.25

3.3 kHz

-0.35

0.3

3.6 kHz

-3

4 kHz

-40

2':4.4 kHz

-74

UNIT

dB

NOTE 5: The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The input signal is the
digital equivalent of a sine wave (digital full scale = 0 dB). The nominal differential OAC channel output with
this input condition is 6 VI(PP). The pass band is 0 to 3600 Hz for an 8-kHz sample rate. This pass band scales
linearly with the conversion rate.

4-399

4.3.7
4.3.7.1

DAC Dynamic Performance
DAC Signal-to-Noise when load is 600 n (see Note 6)
PARAMETER

MIN

TYP

85

89

VI =-9 dB

76

80

VI =-40 dB

45

49

VI =-65dB

20

24

TEST CONDITIONS

VI = 0 dB
Signal-to-noise ratio (SNR)

MAX

UNIT

dB

NOTE 6: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test
is measu~ed at output of application schematic low-pass filter. The test is conducted in 16-bit mode.

4.3.7.2

DAC Signal-to-Noise when load is 10 kn (see Note 6)
PARAMETER

Signal-to-noise ratio (SNR)

TEST CONDITIONS

MIN

TYP

VI = 0 dB

89

VI =-9 dB

80

VI =-40 dB

50

VI =-65dB

25

MAX

UNIT

dB

NOTE 6: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test
is measured at output of application schematic low-pass filter. The test is conducted in 16-bit mode.

4.3.7.3

DAC Signal-to-Distortion when load is 600 n (see Note 6)
, PARAMETER

Signal-to-total harmonic distortion (THO)

TEST CONDITIONS

MIN

TYP

VI =-3 dB

76

80

VI =-9 dB

84

90

VI =-40 dB

64

72

VI =-65 dB

42

48

MAX

UNIT

dB

NOTE 6: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test
is measured at output of application schematic low-pass filter. The test is conducted in 16-bit mode.

4.3.7.4

DAC Signal-to- Distortion when load is 10 kg (see Note 6)
PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

82

VI =-3 dB
Signal-to-total harmonic distortion (THO)

TYP

VI =-9 dB

91

VI =-40 dB

77

VI =-65 dB

49

dB

NOTE 6: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test
is measured at output of application schematic low-pass filter. The test is conducted in 16-bit mode.

4.3.7.5

DAC Signal-to-Distortion+Noise when load is'600 n (see Note 6)
PARAMETER

TEST CONDITIONS

VI =-3 dB
Signal-to-total harmonic distortion + noise (THO + N)

: .,~?I

MIN

TYP

75

79

VI =-9 dB

75

79

VI =-40 dB

45

49

VI =-65 dB

20

24

MAX

UNIT

dB

NOTE 6: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test
is measured at output of application schematic low-pass filter. The test is conducted in 16-bit mode.
4-400

4.3.8

DAC Channel Characteristics
PARAMETER

TEST CONDITIONS

MIN

Dynamic range
Interchannel isolation
EG

Gain error, 0 dB

Vo=OdBat1020Hz

Idle channel narrow band noise

0-4 kHz,

VOO

Output offset voltage at OUT (differential)

DIN = All Os

Analog output voltage, OUTP-OUTM

RL= 600 Qmax
(see Figure 3-8) with
internal reference and
full-scale digital input,
see Note 8, differential

Vo

TYP

MAX

dB

100

dB

±0.3

dB

See Note 7

125
30

Total out of band energy
(0.55 fs to 3 MHz)

IlVrms
mV

6

-45

Channel delay

UNIT

88

Vpp

dB

18/fs

NOTES:

7. The conversion rate is 8 kHz; the~out-of-band measurement is made from 4400 Hz to 3 MHz.
8. The digital input to the DAC channel at DIN is in 2's complement format. The TLC320AD50C/52C DAC is
of the current-type and requires a load resistor for current to voltage conversion.

4.3.9

Power Supply, AVOO

=DVOO =5 V, No Load

PARAMETER
IDD (analog)

Power supply current, ADC

100 (PLL)

Power supply current, PLL

100 (digital 1)

Power supply current, digital

100 (digital 2)

Po

4.3.10

Power supply current, digital,
OVOO =3 V
Power dissipation

TEST CONDITIONS

MIN

Operating
Power down

TYP

MAX

18

24

1
2

Operating

4

0.5

Power down

4

Operating
Power down
Operating
Power down

6

UNIT
mA

mA
mA

10

IlA

4

mA

10

IlA

Operating

120

170

H/W-power down

7.5

20

TYP

MAX

mW

Power-Supply Rejection, AVoo = DVoo = 5 V (see Note 9)
PARAMETER

TEST CONDITIONS

MIN

AVOO

Supply voltage rejection ratio, analog
supply

fj = 0 to fs/2

50

OVOO

Supply voltage rejection ratio, OAC
channel

fj = 0 to 30 kHz

40

OVOO

Supply voltage rejection ratio, AOC
channel

fj = 0 to 30 kHz

50

UNIT

dB

NOTE 9: Power supply rejection measurements are made with both the AOC and the OAC channels idle and a 200-mV
peak-to-peak signal applied to the appropriate supply.
4-401

4.4
41
4..

Timing Characteristics (see Parameter Measurement Information)
Master MdT"'
o e Immg Requirements
MIN

NOM

MAX

td1

Delay time, SCLKi to FSJ,

tsu1

Setup time, DIN, before SCLK low

th1

Hold time, DIN, after SCLK high

20

1et3

Delay time, MCLKJ, to SCLKi

50

Iet(CH-FDL)

Delay time, SCLK high to FSD low
(see Figure 5-1)

50

twH

Pulse duration, MCLK high

32

twL

Pulse duration, MCLK low

20

442
..

25

NOM

MAX

Delay time, SCLKi to FSJ,

tsu2

Setup time, DIN, before SCLK low

th2

Hold time, DIN, after SCLK high

20

td6

Delay time, MCLKJ, to SCLKi

50

td(FL-FDL)

Delay time, FS low to FSD low,
(see Figure 5-2)

40

td(CH-FDL)

Delay time, SCLK high to FSD low,
slave mode (see Figure 5-1)

50

twH

Pulse duration, MCLK high

32

twL

Pulse duration, MCLK low

20

PARAMETER
Delay time, SCLKi to DOUT

ten1

Enable time, FSJ, to DOUT

tdis1

Disable time, Fsi to DOUT hi-Z

TEST CONDITIONS

ns

Delay time, SCLKi to DOUT

ten2

Enable time, FSJ, to DOUT

~2

Disable time, Fsi to DOUT hi-Z

MIN

TYP

MAX

UNIT

20
CL = 20 pF

25

ns

20

Slave Mode Switching Characteristics
PARAMETER
TEST CONDITIONS

lets

4-402

20

Mas t er Mod e SWltC
. h'mg Ch aracterlstlcs

td2

4.4.4

UNIT

'0

td4

..

ns

SI ave MdT"'
o e Immg Requlrements
MIN

443

UNIT

0

MIN

TYP

MAX

UNIT

20
CL

=20 pF

25
20

ns

"\

-16
-32

-48
ID

"c
I

0

~
~
c

~

-64

, ,,

r r\j \t nf1 1f\(~I\ .. h

-80
-96

' I

-

-112

y

-128

nr,

-144

o

0.8

1.6

2.4

4
4.8
3.2
fl - Input Frequency - kHz

5.6

6.4

7.2

8

3.6

4

Figure 4 -1. ADC Decimation Filter. Response
0.5
0.4
0.3
0.2
ID

"
I

C

0

i

~

c

~

0.1 ~
0
-0.1

\
V

A

'/

\ /"
\j

....

/ \

\J

-0.2

\-

/\
I

\

r

~

I~

/ \V I '

-

-0.3
-0.4
-0.5

o

0.4

0.8

1.2

1.6
2
2.4
fl - Input Frequency - kHz

2.8

3.2

Figure 4 -2. ADC Decimation Filter Passband Ripple

4-403

"\

-16
-32
-48
III
'C

I

-64

0
;:

-80

c

,,

~A f\ \f\{\f rtf\ ~ A' ~A
' Wv ~ \ V V'
WW

111
~

c

~

-96
-112
-128
-144

o

0.8

1.6

2.4

4.8
3.2
4
fl - Input Frequency - kHz

5.6

6.4

7.2

8

Figure 4-1. DAC Interpolation Filter Response
0.5
0.4
0.3
0.2
III

'C

I

0.1

c
0

0
~
~
cQ) -0.1

~ -0.2

,J-

I \

I' / \ I1\, 1 i\ /"
\ .,1 \ 1 \ v
/ \/
...,
~

V'

-.03
-0.4
-0.5

o

0.4

0.8

1.2

1.6
2
2.4
fl - Input Frequency - kHz

2.8

3.2

Figure 4-2. DAC Interpolation Filter Passband Ripple

4-404

3.6

4

ADC SIGNAL-TO-NOISE RATIO

vs
INPUT SIGNAL
90

~

80
III

'0

I
0

~

a:

70
60

/

G)

UI

'0

50

{!.

40

ZI

..!.
I'll
C

CI

en

30

0
Q
CC

20

I

/

/

/

I

I
8 kHz Conversion Rate
MCLK 8.192 MHz
OSR 64

=
=

10

o

-40

-65

-9
-3
-2
Input Signal - dB

-1

-

o

Figure 4--3.
ADC SIGNAL-TO-DISTORTION RATIO

vs
INPUT SIGNAL
100

/ ~

90

/

III
'0

I
0

80

a:

70

:e0

0

60

UI

50

~
c

-

is

{:.
..!.

/
II

...........

i'--

/

40

I'll

c
.21

en
I

0
Q
CC

30
20

8 kHz Conversion Rate
MCLK 8.192 MHz
OSR 64

=
=

10

o

-65

-40

-9

-3

-2

-1

-

o

Input Signal - dB

Figure 4-4.

.4-405

ADC SIGNAL-TO-{NOISE AND DISTORTION) RATIO·

vs
INPUT SIGNAL
90
80
70
60
50
40
30

I

/

J

/

/

I

20
8 kHz Conversion Rate
MCLK = 8.192 MHz
OSR=64

10

o

I

-65

1

-3
-2
Input Signal ~dB

-40

-9

-

I

o

-1

Figure 4-5.
DAC SIGNAL-TO-NOISE RATIO

vs
INPUT SIGNAL
90
80
/XI

'0

I

70

.2
'&i

60

IX

CD

.!
0

z

{!.
....!.

50
40

IV

C

C)

(i)

30

I
(J

<
Q

.J

/

/

I

i"""-

/

If

20
8 kHz Conversion Rate
MCLK = 8.192 MHz
OSR .. 64

10

o

-65

-40

-3
-2
Input Signal- dB

-9

Figure 4-6.
4-406

-1

-

o

DAC SIGNAL-TO-DISTORTION RATIO

vs
INPUT SIGNAL
100
90
III

"tI

I
0

80

+=
111
a:

70

0

60

J

c::

-

E

C

{!.

40

Cl

30

en
I

0

r--.

20

8 kHz Conversion Rate
MCLK = 8.192 MHz
OSR= 64

C

)

(C

)

~
014

I
loll

~

Figure 5-4. Serial Communication Timing (Master Mode)

SCLK
twH

I
MCLK

ItI

\

-~
~+FS
I
~

I

~

(

DOUT

twL

ten2

015
tsu2

DIN

(

015

I
I
I
I
I

~14

X

~

X
th2

Ii I "-~
1"-

~

td5

I
I
I
I

~

j4I

>C

)

(C

)

~

I

014

I
loll

~

Figure 5-5. Serial Communication Timing (Slave Mode)

4-410

fiI I

tdis2

6 Register Set
Bits 012 through 08 in a secondary serial communication comprise the address of the register that is written
with data carried in 07 through ~O. 013 determines a read or write cycle to the addressed register. When
low, a write cycle is selected.
The following table shows the register map.

Table 6-1. Register Map
015

014

013

012

011

010

09

08

0

0

0

0

0

0

0

0

0

No operation

1

0

0

0

0

0

0

0

1

Control 1

1

0

Control 2

REGISTER NO.

REGISTER NAME

2

0

0

0

0

0

0

3

0

0

0

0

0

0

1

1

Control 3

4

0

0

0

0

0

1

0

0

Control 4

4-411

6.1

Control 1 Register
Table 6-2. Control 1 Register

D7

D6

D5

D4

D3

D2

D1

DO

1

-

-

-

-

-

-

-

1

-

-

-

-

-

Software power down (analog and filters)

-

0

-

-

-

-

-

Software power down (not asserted)

-

-

1

-

Software reset

0

-

-

Select AUXP and AUXM for ADC

-

-

-

-

Select INP and INM for ADC

-

-

Select INP and INM.for monitor

-

-

-

-

Monitor amplifier gain = 0 dB (see Note 1)

-

Monitor amp mute

1

Digital loopback asserted

-

-

-

-

-

0

-

-

0

-

-

1

-

-

-

1

1

1

0

-

0

1

-

-

-

DESCRIPTION
Software reset not asserted

Select AUXP and AUXM for monitor
Monitor amplifier gain = -18 dB (see Note 1)
Monitor amplifier gain = -8 dB (see Note 1)

-

0

0

-

-

0

-

-

-

-

-

1

16-bit DAC mode (hardware secondary requests)

-

-

-

-

0

Not 16-bit DAC mode (software secondary requests)

Digital loop back not asserted

Default value: 0 0 0 0 0 0 0 0
NOTE 1: These gains are for a single-ended input. The gain is 6 dB lower with a differential input.
A software reset is a one-shot operation and this bit is cleared toO after reset. It is not necessary to write
a 0 to end the master reset operation. Writing Os to the reserved bits is suggested.

6.2

Control 2 Register
Table 6-3. Control 2 Register

D7

D6

05

D4

D3

D2

D1

DO

X

-

-

-

-

-

-

FLAG output value

-

-

-

DESCRIPTION

-

-

-

-

Phone mode disable

-

Decimator FIR overflow flag (valid only during read cycle)

-

16-bit ADC mode
Not-16-bit ADC mode

-

1

-

-

0

-

-

-

-

X

-

-

-

-

1

-

-

-

0

-

-

-

-

-

-

-

X

0

0

Reserved (TLC320AD50C only)

-

-

-

0

0

0

FSD enable (TLC320AD52C only) .

-

-

1

-

-

1

-

-

-

Analog loopback enabled

-

-

0

-

-

-

Analog loopback disabled

-

Default value: 00000000
Writing Os to the reserved bits is suggested.
4-412

Phone mode enable

FSD disable (TLC320AD52C only)

6.3

Control 3 Register

The following command contains the frame-sync delay (FSO) register address and loads 07 (MSB)-OO into
the FSO register. The data byte (01-00) determines the number of SCLKs between FS and the delayed
frame-sync signal, FSO. The minimum data value for the register is decimal 18.

Table 6-4. Control 3 Register

07

06

05

04

03

02

01

DO

-

-

X

X

X

X

X

X

Number of SCLKs between FS and FSD

DESCRIPTION

X

X

-

-

-

-

-

-

Binary number of slave devices (3 maximum for
TLC320AC50C, 1 maximum for TLC320AC52C)

Default value: 00000000

Writing as to the reserved bits is suggested.

6.4

Control 4 Register
Table 6-5. Control 4 Register

D7

06

05

D4

D3

02

D1

DO

-

-

-

1

1

-

-

-

-

-

1

0

-

-

-

0

1

-

-

-

-

-

0

0

-

-

-

-

-

1

1

-

1

0

-

0

1

-

-

-

-

-

-

-

0

0

= mute
Analog input gain = 12 dB
Analog input gain = 6 dB
Analog input gain = 0 dB
Analog output gain = mute
Analog output gain = - 12 dB
Analog output gain = - 6 dB
Analog output gain = 0 dB

-

-

-

-

-

Sample frequency select (N): fs
MCLKI(512 x N)

-

-

-

External sample clock feature enabled

-

-

External sample clock feature disabled

-

-

X

X

X

1

-

-

-

-

-

0

-

-

-

DESCRIPTION
Analog input gain

= MCLKI(128 x

N) or

Default value: 00000000

The value of the sample frequency divisor, N, is determined by the octal respresentation of bits 04 - 06.
Hence, 001 = 1, 010 = 2, etc. By setting 04 - 06 to 000, N = 8 is selected.

4-413

4-414

7 Application Information

TMS320C2x/3x/Sx/2xx/S4x

..":'

XF

....
....

CLKOUT
DX
DR
FSX
FSR

....
....

....

CLKR

f---+-4

FC
MCLK
DIN
DOUT
Master Mode

FS

W

CLKX

TLC320ADSOC

~

FSD
SCLK

TLC320ADSOC

....

FC

...

MCLK
DIN
DOUT
-

L+- FS
Slave Mode
,--

...
~

FSD
SCLK

, ,

Figure 7-1. Master Device and Slave Device Connections (to DSP Inte..face)

4-415

TLC320AD50
INP

REFP

INM

REFM

0.1

~F

FILT
5V

AVDD(PLL)

0.1

AVSS(PLL)
5V
0.1 ~F

AVDD
OUTP

AVSS

OUTM

DVDD

3Vor5V
0.1 ~F

DVSS

DGND

Figure 7-2. Power Supply Oecoupllng

4-416

AGND

~F

· TLC320AD55C
Data Manual
Sigma-Delta Analog Interlace Circuit

SLAS085
July 1995

•

TEXAS

INSTRUMENTS

Printed on Recycled Paper

IMPQRTANT NOTICE

Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and adVises its customers to obtain the latest
version of relevant information to verify, before placing Orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with Tl's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
." .
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local. SC
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TI assumes no liability for applications assistance, customer product design, software
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Copyright © 1995, Texas Instruments Incorporated

Contents
Section

Title

Page

1

Introduction . ............................................................
1.1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.2
Functional Block Diagram ............................................
1.3
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.4
Ordering Information ................................................
1.5
Terminal Functions ..................................................
1.6
Definitions and Terminology ..........................................
1.7
Register Functional Summary ........................................

4-423
4-423
4-424
4-425
4-425
4-426
4-427
4-428

2

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.1
Device Functions ...................................................
2.1.1 Operating Frequencies .........................................
2.1.2 ADC Signal Channel ...........................................
2.1.3 DAC Signal Channel ...........................................
2.1.4 Serial Interface ................................................
2.1.5 Register Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.1.6 Sigma-Delta ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
2.1.7 Decimation Filter ...............................................
2.1.8 Sigma-Delta DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.1.9 Interpolation Filter .............................................
2.1.10 Switched-Capacitor Filter (SCF) .................................
2.1 .11 Analog/Digital Loopback .......................................
2.1 .12 DAC Voltage Reference Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ..
2.1.13 FIR Overflow Flag ......................................... ~ ...
2.2
Terminal Descriptions ...............................................
2.2.1 Reset and Power-Down ........................................
2.2.2 Master Clock Circuit ............................................
2.2.3 Data Out (DOUT) ..............................................
2.2.4 Data In (DIN) ..................................................
2.2.5 Hardware Program Terminal (FC) ................................
2.2.6 Frame-Sync ...................................................
2.2.7 Multiplexed Analog Input ........................................
2.2.8 Analog Input ..................................................

4-429
4-429
4-429
4-429
4-429
4-429
4-429
4-430
4-430
4-430
4-430
4-430
4-430
4-430
4-430
4-431
4-431
4-432
4-432
4-432
4-433
4-433
4-433
4-433

3

Serial Communications ..................................................
3.1 Primary Serial Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.2 Secondary Serial Communication ............................ . . . . . . . . ..
3.3 Conversion Rate Versus Serial Port ....................................
3.4 FIR Bypass Mode ....................................................
3.5 Phone Mode Control ..................................................

4-435
4-435
4-437
4-439
4-440
4-441
4-419

Contents (Continu~d)
Section

4

5

Title

Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range . ..
4.2 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.3 Recommended Operating Conditions, DVOO = 5 V .......................
4.4 Electrical Characteristics, TA = 25°C, Voo(ADC) = Voo(DAC) = DVOO = 5 V,
MCLK = 16.384 MHz, Fk = 8 ..........................................
4.4.1 Digital Inputs and Outputs, Outputs Not Loaded ....................
4.4.2 ADC Path Filter. . .. . .. .. . . . . . .. . . . . . . . . . .. . .. . . .. . .. . . .. . .. . ...
4.4.3 ADC Dynamic Performance .....................................
4.4.4 ADC Channel .................................................
4.4.5 DAC Path Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.4.6 DAC Dynamic Performance .....................................
4.4.7 DAC Channel .................................................
4.4.8 Power Supplies, Voo(ADC) = Voo(DAC) = DVoo = 5 V, No Load ....
4.4.9 Timing Requirements ...........................................

Page

4-443
4-443
4-443
4-443
4-444
4-444
4-444
4-444
4-445
4-445
4-446
4-446
4-447
4-447

Application Information .................................................. 4-449

Appendix A Register Set .................................., ................... 4·451

4-420

List of Illustrations
Figure

Title

Page

1-1 Functional Block Diagram ............................................... 4-424
1-2 Terminal Assignments .................................................. 4-425

2-1
2-2
2-3

Reset Function ......................................................... 4-431
Internal Power-Down Logic .............................................. 4-432
Differential Analog Input Configuration .................................... 4-433

3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8

Primary Serial Communication Timing ....................................
DAC and ADC Word Lengths ............................................
Hardware and Software Methods to Initiate a Secondary Request ............
Secondary DIN Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Hardware FC Secondary Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Software FC Secondary Request . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . ..
FIR Bypass Timing .....................................................
Phone Mode Timing ....................................................

4-436
4-436
4-437
4-437
4-438
4-439
4-440
4-441

5-1 TLC320AD55C Application Schematic .................................... 4-449
5-2 TLC320AD55C I/O Buffer and VMID Generator Schematic ................... 4-450

List of Tables
Table

Title

Page

3-1 Least-Significant-Bit Control Function ..................................... 4-438
3-2 Secondary Communication Data Format .................................. 4-439

4-421

4-422

1 Introduction
The TLC320AD55C provides high resolution low-speed signal conversion from digital-to-analog (D/A) and
from analog-to-digital (AID) using oversampling sigma-delta technology. This device consists of two, serial,
synchronous conversion paths (one for each data direction) and includes an interpolation filter before the
digital-to-analog converter (DAC) and a decimation filter after the analog-to-digital converter (ADC) (see
Figure 1-1). Other overhead functions provide analog filtering and on-chip timing and control. The
sigma-delta architecture produces high resolution, analog-to-digital and digital-to-analog conversion at low
system speeds and low cost.
The options and the circuit configurations of this device can be programmed through the serial interface.
The options include reset, power-down, communications protocol, serial clock rate, signal sampling rate,
and test mode as outlined in Appendix A. The circuit configurations could include a selection of input ports
to the ADC, al1alog loopback, digital loopback, decimator sinc filter output, decimator finite-duration
impulse-response (FIR) filter output, interpolator sinc filter output, and interpolator FIR filter output. The
TLC320AD55C is characterized for operation from O°C to 70°C.

1.1

Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Single 5-V power supply
Power dissipation (Po) of 150 mW maximum in the operating mode
Power-down mode to 1 mW
General-purpose 16-bit signal processing
2s-complement format
Serial port interface
Minimum BO-dB harmonic distortion plus noise
Differential architecture
Internal reference voltage (Vref)
Internal 64 x oversampling
Analog output with programmable gain of 1, 1/2, 1/4, and 0 (squelch)
Phone-mode output control
Variable conversion rate selected as MCLKI(Fk x 256), Fk = 1,2,3, ... ,256
System test mode:
Digital loopback test
Analog loopback test

4-423

1.2

Functional Block Diagram

INP
INM

---'---1

AUXP
AUXM

---tl>---~

MUX

1-+-4......- DOUT (28

---t--~

complement)

Analog

Enablet

loopback

REFCAPDAC
OUTP

SCF
OUTM

Filter

Sigma·
Delta

DAC

InterpolatIon Filter

H .........+- DIN (28

complement)

MClK
SClK

t See control 3 register in Appendix A.

Figure 1-1. Functional Block Diagram

4-424

1.3

Terminal Assignments
OW PACKAGE
(TOP VIEW)

NU
PWRDWN
OUTM
VOO(DAC)
REFCAPOAC
VSS(DAC)
RESET
DVOO
DIN
DOUT
FS
SCLK
MCLK

8
9
11

AUXP
AUXM
INP
INM
VOO(ADC)
REFCAPAOC
VA(SUB)
VSS(ADC)
DVSS
VO(SUB)
ALT DATA
FLAG 0
FLAG 1
FC

NU-Make no external connection

Figure 1-2. Terminal Assignments

1.4

Ordering Information
PACKAGE
TA

SMALL OUTLINE
(OW)

O°C to 70°C

TLC320A055COW

~25

1.5

Terminal Functions
TERMINALS
NAME

NO.

1/0

DESCRIPTION

AUXM

27

I

AUXP

28

I

Noninverting input to auxiliary analog input

ALTDATA

18

I

Signals on ALT DATA are rooted to DOUT during secondary communiction when phone
mode is enabled.

DIN

10

I

Data input. DIN receives the DAC input data and command information from the DSP
and is synchronized to SCLK.

DOUT

11

0

Data output. DOUT transmits the ADC output bits and is synchronized to SCLK. DOUT
is at Hi-Z when FS is not activated.

DVDD

9

I

Digital power supply

Inverting input to auxiliary analog input

DVSS

20

I

Digital ground

FC

15

I

Function control. FC is sampled and latched on the rising edge of FS for the primary serial
communication. Refer to Section 3 Serial Communications for more details.

FLAG 0

17

0

FLAG 1

16

0

During phone mode, FLAG 1 contains the value set in control 2 register.

FS

12

0

Frame sync. When FS goes low, the serial communication port is activated. In all serial
transmission modes, FS is held low during bit transmission. Refer to Section 3 Serial
Communications for a detailed description.

INM

25

I

Inverting input to analog input

During phone mode, FLAG 0 contains the value set in control 2 register.

INP

26

I

Noninverting input to analog input

MCLK

14

I

Master clock. MCLK derives the internal clocks of the sigma-delta analog interface
circuit.

OUTM

4

0

Inverting output of the DAC analog power amplifier. Functionally identical with and
complementary to OUTP. OUTM and OUTP can drive 600 n differentially. OUTM should
not be used alone for single-ended operation.

OUTP

3

0

Noninverting output of the DAC analog power amplifier. OUTM and OUTP can drive
600 n differentially. OUTP should not be used alone for single-ended operation.

PWRDWN

2

I

Power down. When PWRDWN is pulled low, the device goes into a power-down mode;
the serial interface is disabled and most of the high-speed clocks are disabled. However,
all of the registers' values are sustained and the device resumes full power operation
without reinitialization when PWRDWN is pulled high again. PWRDWN resets the
counters only and preserves the programmed register contents. Refer to Section 2.2.1.3
Software and Hardware Power-Down.

REFCAPADC

23

0

Analog-reference voltage connection for external capacitor for the ADC. The nominal
voltage on REFCAPADC is 3.4 V. A buffer must be used when this voltage is used
externally. REFCAPADC is not to be used as the mid-supply voltage reference for
single-ended operation.

REFCAPDAC

6

0

Analog-reference voltage connection for external capacitor for the DAC. The nominal
voltage on REFCAPDAC is 3.4 V. A buffer must be used when this voltage is used
externally.

RESET

8

I

Reset. The reset function initializes all of the internal registers to their default values. The
serial port can be configured to the default state accordingly. Refer to Appendix A Table
A-2 Control 1 Register and Section 2.2.1 Reset and Power-Down for more detailed
descriptions.

13

0

Shift clock. SCLK is derived from MCLK and clocks serial data into DIN and out of DOUT.

SCLK

NOTE 1: All digital inputs and outputs are TTL compatible unless otherwise noted.
4--426

1.5

Terminal Functions (Continued)
TERMINALS

NO.

NAME
VA(SUB)

DESCRIPTION

1/0

22

I

Analog substrate. VA(SUB) must be grounded.

VO(SUB)

19

I

Oigital substrate. VO(SUB) must be grounded.

VOO(AOC)

24

I

Analog AOC path supply

VOO(OAC)

I

Analog OAC path supply

VSS(AOC)

5
21

I

Analog AOC path ground

VSS(OAC)

7

I

Analog OAC path ground

..

NOTE 1: All digital Inputs and outputs are TTL compatible unless otherwise noted .

1.6

Definitions and Terminology

Data Transfer Interval

The time during which data is transferred from DOUT and to DIN. The interval is
16 shift clocks and this data transfer is initiated by the falling edge of the frame-sync
signal.

Signal Data

The input signal and all of the converted representations through the ADC channel
and return through the DAC channel to the analog output. This is contrasted with
the purely digital software control data.

Primary
Communications
Secondary
Communications

Frame Sync

Frame Sync and
Sampling Period
fs
Frame-Sync Interval

The digital data transfer interval. Since the device is synchronous, the signal data
words from the ADC channel and to the DAC channel occur simultaneously.
The digital control and configuration data transfer interval into DIN and the register
read data cycle from DOUT. The data transfer interval occurs when requested by
hardware or software.
The falling edge of the signal that initiates the data transfer interval. The primary
frame sync starts the primary communications, and the secondary frame sync
starts the secondary communications.
The time between falling edges of successive primary frame-sync signals.
The sampling frequency that is the reciprocal of the sampling period.
The time period occupied by 16 shift clocks. It goes high on the sixteenth rising
edge of SCLK after the falling edge of the frame sync.

ADC Channel

All signal processing circuits between the analog input and the digital conversion
results at DOUT.

DAC Channel
Host

All signal processing circuits between the digital data word applied to DIN and the
differential output analog signal available at OUTP and OUTM.
Any processing system that interfaces to DIN, DOUT, SCLK, or FS.

Dxx

A bit position in the primary data word (xx is the bit number).

DSxx

A bit position in the secondary data word (xx is the bit number).

d

The alpha character d is used to represent valid programmed or default data in the
control register format (see secondary serial communications) when discussing
other data bit portions of the register.

x

The alpha character X represents a don't-care bit position within the control register
format.

FIR

Finite-duration impulse response.

4-427

1.7

Register Functional Summary

There are six data and control registers that are used as follows:
Register 0

The No-op register. The 0 register allows secondary requests without altering any other
register.

Register 1

The control 1 register. The data in this register controls:

Register 2

Register 3

•

The software reset

•

The software power-down

•

Selection of the normal or auxiliary analog inputs

•

The output amplifier gain (1, 1/2, 1/4, or squelch)

•

Selection of the analog loopback

•

Selection of the digital loopback

•

16-bit or 15-bit mode of operation

The control 2 register. The data in this register:
•

Contains the output flag indicating a decimator FIR filter overflow

•

Contains Flag 0 and Flag 1 output values for use in the phone mode

•

Selects the phone mode

•

Selects or bypasses the decimation FIR filter

•

Selects or bypasses the interpolater FIR filter

The Fk divide register. This register controls the filter clock rate and the sample period.

Register 4

The Fsclk divide register. This register controls the shift (data) clock rate.

Register 5

The control 3 register. This register enables and disables the DAC reference.

4--428

2

Functional Description

2.1

Device Functions

The following sections describe the functions of the device.

2.1.1

Operating Frequencies

The sampling (conversion) frequency is derived from the master clock (MCLK) input by the following
equation:
fs

=

. .
Sampling (conversion) frequency

=

MCLK frequency
(Fk register value) x 256

The inverse is the time between the falling edges of two successive primary frame-synchronization signals
and it is the conversion period.
The input and output data clock (SCLK) is given by:
SCLK f
requency

2.1.2

=

MCLK frequency
(Fsclk register value) x 2

ADC Signal Channel

To produce excellent common-mode rejection of unwanted signals, the analog signal is processed
differentially until it is converted to digital data.
The ADC converts the signal into discrete output digital words in 2s-complement format, corresponding to
the analog-signal value at the sampling time. These 16-bit digital words, representing sampled values of
the analog input signal, are clocked out of the serial port, DOUT, during the frame-sync interval (one word
for each primary communication interval). During secondary communications, the data previously
programmed into the registers can be read out with the appropriate register address, and the read bit set
to 1. When a register read is not requested, all 16 bits are 0 in the secondary word.

2.1.3

DAC Signal Channel

DIN receives the 16-bit serial data word (2s complement) from the host during the primary communications
interval and latches the data on the seventeenth rising edge of SCLK. The data are converted to an analog
voltage by the DAC and then passed through a (sin x)/x correction circuit and a smoothing filter. An output
buffer with three software-programmable gains (0 dB, -6 dB, and -12 dB) drives the differential outputs
OUTP and OUTM. A squelch mode can also be programmed for the output buffer. During secondary
communications, the configuration program data are read into the device control registers.

2.1.4

Serial Interface

The digital serial interface consists of the shift clock, the frame synchronization signal, the ADC-channel
data output, and the DAC-channel data input. During the primary 16-bit frame synchronization interval,
SCLK transfers the ADC channel results from DOUT and transfers 16-bit DAC data into DIN.
During the secondary frame-synchronization interval, the SCLK transfers the register read data from DOUT
when the read bit is set to a one. In addition, SCLK transfers control and device parameter information into
DIN. The functional sequence is shown in Figure 3-1.
.

2.1.5

Register Programming

All register programming occurs during secondary communications, and data are latched and valid on the
rising edge of the frame-sync signal. When the default value for a particular register is desired, that register
does not need to be addressed during secondary communications. The no-op command addresses the
no-op register (register 0), and register programming does not take place during this communication.
4-429

DOUT is released from the high-impedance state on the falling edge of the primary or secondary frame-sync
interval. In addition, each register can be read back during DOUT secondary communications by setting the
read bit D13 to 1 in the addressed register (refer to Appendix A). When the register is in the read mode, no
data can be written to the register during this cycle. To return this register to the write mode requires a
subsequent secondary communication.

2.1.6

Sigma-Delta ADC

The sigma-delta ADC is a fourth-order, sigma-delta modulator with 64-times oversampling. The ADC
provides high-resolution, low-noise performance using oversampling techniques.

2.1.7

Decimation Filter

The decimation filter reduces the digital data rate to the sampling rate. This is accomplished by decimating
with a ratio of 1:64. The output of this filter is a sixteen-bit, 2s-complement data word clocking at the sample
rate.

NOTE
The sample rate is determined through a programmable relationship of
MCLK/(Fk x 256), Fk = 1,2,3, ... ,256

2.1.8

Sigma-Delta DAC

The sigma-delta DAC is a fourth-order, sigma-delta modulator with 64-times oversampling. The DAC
provides high-resolution, low-noise performance from a one-bit converter using oversampling techniques.

2.1.9

Interpolation Filter

The interpolation filter resamples the digital data at a rate of 64 times the incoming sample rate. The
high-speed data output from this filter is then used in the sigma-delta DAC.

2.1.10 Switched-Capacitor Filter (SCF)
A switched-capacitor filter network is implemented on the analog output to prQvide low-pass operation with
high rejection in the stop band.

2.1.11

Analog/Digital Loopback

The loopbacks provide a means of testing the ADC/DAC channels and can be used for in-circuit,
system-level tests. The loopbacks feed the appropriate output to the corresponding input on the device.
The test capabilities include an analog loopback between the two analog paths and a digital loopback
between the two digital paths. Each loopback is enabled by setting the D1 or D2 bit in control 1 register (see
Appendix A).

2.1.12

DAC Voltage Reference Enable

The DAC voltage reference can be disabled through the control 3 register. This allows the use of an external
voltage reference applied to the DAC channel modulator. By supplying an external reference, the user can
scale the output voltage range of this channel. The internal reference value is 3.6 V which provides a 6-V,
peak-to-peak, differential output. The ratio of an external reference to the internal reference determines the
output voltage range of the DAC channel as shown in the following equation:
V

- V(EXT REF)
O(PP) 3.6

x

6 V

NOTE
The distortion and noise specifications listed in Section 4 Specifications apply only
under the following condition:
V(EXT REF) < 1
3.6
4-430

2.1.13

FIR Overflow Flag

The decimator FIR filter provides an overflow flag to the control 2 register to indicate that the input to the
filter has exceeded the range of the internal filter calculations. When this bit is set in the register, it remains
set until the register is read by the user. Reading this value always resets the overflow flag.

2.2

Terminal Descriptions

The following sections describe the terminal functions.

2.2.1

Reset and Power-Down

2.2.1.1

Reset

As shown in Figure 2-1, the TLC320AD55C resets both the internal counters and registers, including the
programmed registers, in two ways:
•

By appling a low-going reset pulse to the RESET terminal

•

By writing to the programmable software reset bit (007 in control 1 register)

PWRDWN resets the counters only and preserves the programmed register contents. The DAC resets to
the 15-bit mode.

r---------------------------------,
I
14
.1·
TRESET

n.J

I

I
D RESETI-----....- .. To Circuitry
I
I
MCLK
I
I Software RESET Control
I
Register 1, Bit 7
I
I
________________________________
IL _
Internal TLC320AD55C

~

NOTE A: RESET to circuitry is at least 6 MCLK periods long and releases on the positive edge of MCLK.

Figure 2-1. Reset Function

2.2.1 .2

Conditions of Reset

The two internal reset signals used for the reset and synchronization functions are:
•

•

Counter reset

-This signal resets all flip-flops and latches that are not externally programmed,
with the exception of those generating the.reset pulse itself. Additionally, this
signal resets the software power-down bit..

Counter reset

=RESET terminal or reset bit or PWRDWN terminal

Register reset

- This signal resets all flip-flops and latches that are not reset by the counter
reset, except those generating the reset pulse itself.

Register reset

=RESET terminal or reset bit

Both reset signals are at least six MCLK periods long (TRESET) and release on the trailing edge of MCLK.
4-431

2.2.1.3

Software and Hardware Power-Down

Given the definitions above, the software-programmed power-down condition is cleared by programming
the software bit (control 1 register bit 6) to a 0 or is cleared by cycling the power to the device, bringing
PWRDWN low, or bringing RESET low (see Figure 2-2).
PWRDWN removes power to the entire chip. The software-programmable, power-down bit only removes
power from the analog section of the chip, which allows a software power-up function. Cycling the
power-down terminal from high to low and back to high resets all flip-flops and latches that are not externally
programmed, thereby preserving the register contents with the exception that the software power-down bit
is cleared.
When PWRDWN is not being used, it should be tied high [VDD{ADC) is preferred].

r-------------------------,
Digital Circuitry
Power-Down

Analog Circuitry
Power-Down

PWRDWN

Bit 6 is Programmed
Through a Secondary
Write Operation

LInternal
_________________________
~
TLC320AD55C
Figure 2-2. Internal Power-Down Logic

2.2.2

Master Clock Circuit

The clock circuit generates and distributes necessary clocks throughout the device. MCLK is the external
master clock input. SCLK is derived from MCLK [SCLK = MCLKJ{Fsclk x 2), Fsclk = 1,2,3, ... ,256] in order
to provide clocking of the serial communications between the device and a digital signal processor (DSP).
The sample rate of the data paths is set as MCLKI{Fk x256). Fk and Fsclk are programmable register values
used as divisors of MCLK. The default value for the Fk and Fsclk register is 8 (decimal).

2.2.3

Data Out (DOUT)

DOUT is taken from the high-impedance state by the falling edge of the frame-sync signal. The most
significant data bit then appears on DOUT.
DOUT is placed in a high-impedance state on the sixteenth rising edge of SCLK (internal or external) after
the falling edge of the frame-sync signal. In the primary communication, the data word is the ADC conversion
result. In the secondary communication, the data is the register read results when requested by the
read/write (R/W) bit with the eight MSBs set to zero (see the serial communications section). When a
register read is not requested, the secondary word is all zeroes.

2.2.4

Data In (DIN)

In the primary communication, the data word is the input digital signal to the DAC channel. In the secondary
communication, the data is the control and configuration data to set up the device for a particular function
(see Section 3 Serial Communications).
4-432

2.2.5

Hardware Program Terminal (FC)

This input provides for hardware programming requests for secondary communication. It works in
conjunction with the control bit 000 of the secondary data word. The signal on FC is latched 112 shift clock
after the rising edge of the next internally generated primary frame-sync interval. FC should be tied low when
not being used (see Section 3.2 Secondary Serial Communication).

2.2.6

Frame-Sync

The frame-sync signal indicates that the device is ready to send and receive data. The data transfer from
DOUT and into DIN begins on the falling edge of the frame-sync signal.
The frame sync is generated internally and goes low on the rising edge of SCLK and remains low during
the 16-bit data transfer.

2.2.7

Multiplexed Analog Input

The two differential analog inputs (INP and INM or AUXP and AUXM) are multiplexed into the sigma-delta
modulator. The performance of the AUX channel is similar to the normal input channel.

2.2.8

Analog Input

The signal applied to the terminals INM and INP should be differential to preserve the device specifications
(see Figure 2-3). A single-ended input signal should always be converted to a differential input signal prior
to being used by the TLC320AD55C. The signal source driving the analog inputs (INM, INP, AUXM, AUXP)
should have a low source-impedance for lowest noise performance and accuracy.
TLC320AD55C

INP

INM

Figure 2-3. Differential Analog Input Configuration

4-433

4-434

3 Serial Communications
DOUT, DIN, SCLK, FS, and FC are the serial communication signals. The digital output data from the ADC
is taken from DOUT. The digital input data for the DAC is applied to DIN. The synchronizing clock for the
serial communication data and the frame sync is taken from SCLK. The frame-synchronization pulse that
encloses the ADC/DAC data transfer interval is taken from FS. For signal (audio) data transmitted from the
ADC or to the DAC, primary serial communication is used. To read or write words that control both the
options and the circuit configurations of the device, secondary communication is used.
The purpose of the primary and secondary communications is to allow conversion data and control data to
be transferred across the same serial port. A primary transfer is always dedicated to conversion data. A
secondary transfer sets up and reads the register values described in Appendix A. A primary transfer occurs
for every conversion period. A secondary transfer occurs only when requested. Two methods exist for
requesting a secondary command. Terminal FC can request a secondary communication when it is
asserted, or the LSB of the DAC data within a primary transfer can request a secondary communication.
The selection of which method is enabled is provided in control 1 register (bit 0) as shown in Appendix A.
For all serial communications, the most significant bit is transferred first. For a 16-bit ADC word and a 16-bit
DAC word, D15 is the most significant bit and DO is the least significant bit. For a 15-bit DAC data word in
the 16-bit primary communication, D15is the most significant bit, D1 is the least significant bit, and DO is
used for the embedded function control. All digital data values are in 2s-complement format.
These logic signals are compatible with TTL-voltage levels and CMOS current levels.

3.1

Primary Serial Communication

Primary serial communication is used both to transmit and receive conversion signal data. The ADC word
length is always 16 bits. The DAC word length depends on the status of DO in the control 1 register. After
power-up or reset, the device defaults to the 15-bit mode (not 16-bit mode). The DAC word length is 15 bits
and the last bit of the primary 16-bit serial communication word is a function-control bit used to request
secondary serial communications. In the 16-bit mode, all 16 bits of the primary communications word are
used as data for the DAC and the hardware terminal FC must be used to request secondary
communications.

4--435

Figure 3-1 shows the timing relationship for SCLK, FS, DOUT and DIN in a primary communication. The
timing sequence for this operation is as follows:
1.

The TLC320AD55C takes FS low.

2.

One 16-bit word is transmitted from the ADC (DOUT) and one 16-bit word is received for the DAC
(DIN).

3.

The TLC320AD55C takes FS high.

---.I 14I I

td3
- VIH

MCLK

VIL
- - - - VOH

SCLK
1

VOL

0th

I
I
I
I
I

td1 ~ j4-

~ 14-

FS

len ~
OOUT

t

Isu

In 16-BII Mode:
DIN

015

WX

015
MSB

l4I
I

Isu
DIN

WX

015
MSB

Jtgtx

14

I

I

01

X

01

X

-.j

DO

VOL

j4~

DO
LSB

~

~

~

I

X I ~P<
014

Ih

tdis

VOH

~

Ih

In 16-BII Mode:

}j

X r ~tx
14
I,..

~-----

((

I

X r14

~

td2

tIIII

01
LSB

X

Fe

~.&

~

Figure 3-1. Primary Serial Communication Timing
When a secondary request is made through the LSB of the DAC data word (16-bit mode), the format shown
in Figure 3-2 is used:

...
...

015

D14

D13

D12 D11 010 D9 D8 D7 D6 D5 D4 D3 D2 D1
DO
15-bit DAC _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~....
..
2s-complement format
control
1t;>-bit ADC - - - - - - - - - - - - - - - - - - - -...
2s-complement format

Figure 3-2. DAC and ADC Word Lengths

4-436

3.2

Secondary Serial Communication

Secondary serial communication reads or writes 16-bit words that program both the options and the circuit
configurations of the device. All register programming occurs during secondary communications. Four
primary and secondary communication cycles are required to program the four registers. When the default
value for a particular register is desired, the user can omit addressing it during secondary communication.
A no-op command addresses the no-opregister (register 0), and no register programming takes place
during this secondary communication.
There are two methods for initiating secondary communications (see Figure 3-3):
1) by asserting a high level on FC, or 2) by asserting the LSB of DIN 16-bit serial communication high while
not in 16-bit mode (see control 1 register bit 0).

r--~--------------------,

FC - - + - - - - - - - - - - - - ' { "..........>-__ Secondary
(Hardware)
I
Request

I
I

I

I

I
I
16·Bit Mode
(Control 1 Register,
I
________________
_______
~~
ILInternal
TLC320AD55C
I

I
I
I
I

(LSB Of DIN)

~

Figure 3-3. Hardware and Software Methods to Initate a Secondary Request
1.

Figures 3-5 and 3-6 show the two different methods by which FC requests secondary
communication words as well as the timing for FS, DOUT, DIN, and SCLK. The examples span
two primary communication frames. Figure 3-5 shows the use of hardware function control.
During a secondary communication, a register can be written to or read from. When writing a
value to a register, DIN contains the value to be written (see Figure 3-7). The data returned on
DOUT is OO(hex). When performing a read function, DIN can still provide data to be written to an
addressed register; however, DOUT contains the most recent value contained in the register
addressed by DIN.
Don't Care
A

DIN
(Secondary
Read)

w/WA

I

8 Bits

~

I ~j I I I I I

8 Bits

~a

~J
\

RiW

v

/

Register Address
1\

DIN
(Secondary
Write)

~~

\

\

v
Data to the
Register

Figure 3-4. Secondary DIN Format
In Figure 3-5, FC clocks in and latches on the rising edge of frame sync (FS). This causes the
start of the secondary update 32 FCLKs (see Fk divide register, Appendix A) after the start of the
primary communication frame. Read and write examples are shown for DIN and DOUT.
2.

Figure 3-6 shows the use of software function control.
The software request for function control is typically used when the required resolution of the DAC
channel is less than 16 bits. Then the least significant bit (DO) can be used for the secondary
requests as shown in Table 3-1.
4-437

Table 3-1. Least-Significant-Bit Control Function
CONTROL BIT DO

CONTROL BIT FUNCTION

0

No operation (no-op)

1

Secondary communication request

On the falling edge of the next FS, D15 through D1 is input to DIN or D15 through DO is output to DOUr.
When a secondary communication request is made, FS goes low for 32 FCLKs (see Fk divide register,
Appendix A) after the beginning of the primary frame.

commun'''''o~ FT" 1 (CF1) ,

t\E'

Communication Frame 2 (CF2)

\'

:)}

Primary

1 Secondary

Primary

}

FC
1

DOUT
(Secondary
Read)

1

1

kADg~ata ~

1

I·
DOUT
(Secondary
Write)

k
.

1
1

:

1

1
1

L!.......l

1

1

1

1
1

1

)-""""'I'r-----

>WW~

1

------.

Secondary
~-....,

.

16 FCLKS

See Note A

I

3-0

PZIo/&;0WijlijI&

I

~

NOTE A: The number of clocks between primary cycles is a function of FCLK. When either FIR is bypassed, this period
is 16 FCLKs. See Fk divide register in Appendix A.

Figure 3-7. FIR Bypass Timing

4-440

3.5

Phone Mode Control

This function is provided for applications that need hardware control and monitor of external events. By
allowing the device to drive two FLAG terminals (set through the control 2 register), the host digital signal
processor (DSP) is capable of system control through the same serial port connection to the device. Along
with this control is the capability for monitoring the value of the ALT DATA terminal during a secondary
communication cycle. One application for this function is in monitoring ring detect or offhook detect from a
phone answering system. The two FLAG terminals allow response to these incoming control signals. Figure
3-8 shows the timing associated with this operating mode.

FS

l

.------,

Primary

Secondary

Primary

r------,

)

r------,

Primary

r

ro-=

ALT DATA
DOUT-'

Secondary

.------,

Register
0ata

_

(Secondary~"'_--J)----I
Read)

~

8SCLKs I·

.i

~

DIN

l---

1 SCLK MAX

-<'----...Wffi~~~___
~~~--'""W~~
....~--""""-W""""'://A~
______""'}
=
=
=
=
Set FLAG 0 FLAG 1 1

Set FLAG 0

FLAG 1 0

I

FFi~~01 W$ff~

Figure 3-8. Phone Mode Timing

4-441

4-442

4 Specifications
4.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(unless otherwise noted)t
Supply voltage range, DVoo Voo(ADC, DAC)(see Note 1) .......... -0.3 V to 6.5 V
Output voltage range, DOUr. FS, SCLK, FLAG 0, FLAG 1 ... -0.3 V to DVoo + 0.3 V
Output voltage range, OUTP, OUTM ........................ -0.3 V to Voo + 0.3 V
Input voltage range, DIN, PWRDWN, RESET, ALT DATA,
MCLK, FC ........................................... -0.3 V to DVoo + 0.3 V
Input voltage range, INP, INM, AUXP, AUXM ................ -0.3 V to Voo + 0.3 V
Case temperature for 10 seconds, T c: OW package ......................... 260°C
Operating free-air temperature range, TA ............................ O°C to 70°C
Storage temperature range, Tstg ................................. -65°C to 150°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for
extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS(DAC) for DAC channel measurements and VSS(ADC) for ADC
channel measurements.

4.2

Recommended Operating Conditions
MIN

Supply voltage, VDD(ADC, DAC)
Analog signal input voltage, VI

I

NOM

4.5

Differential, (lNP-INM) peak,
for full scale operation

Load resistance for OUTPand OUTM, RL

0.3

V

6

V
kQ

100

ADC or DAC conversion rate (Nyquist)

8
0

UNIT

5.5

10

Load capacitance for OUTP and OUTM, CL

Operating free-air temperature, TA

MAX

pF
kHz

70

°C

4.3. Recommended Operating Conditions, DVoo = 5 V
MIN
Supply voltage, DVDD
High-level input voltage, VIH

NOM

4.5

5.5

UNIT
V
V

2
0.8

Low-level input voltage, VIL
MCLK frequency (see Note 2), duty cycle = 50 ±10%

MAX

16.384

V
MHz

NOTE 2: The default state for an 8 kHz conversion rate requires a 16.384 MHz MCLK frequency.

4:-443

4.4

=

=

Electrical Characteristics, TA 25°C, VDD(ADC) VDD(DAC)
MCLK 16.384 MHz, Fk 8 (unless otherwise noted)

4.4.1

=

=

=DVDD =5 V,

Digital Inputs and Outputs, Outputs Not Loaded
TEST CONDITIONS

MIN

TYP

VOH

High-level output voltage, OOUT

PARAMETER

10 = 360!1A

2.4

4.6

VOL

Low-level output voltage, OOUT

10 = 2 mA

IIH

High-level input current, any digital input

MAX

UNIT
V

0.4

V

VIH = 5 V

10

IJ.A

VIL = O.S V

10

IJ.A

0.2

IlL

Low-level input current, any digital input

Ci

Input capacitance

5

pF

Co

Output capacitance

5

pF

4.4.2

ADC Path Filter (see Note 3)
PARAMETER

TEST CONDITIONS
20 Hz
200 Hz

MIN

TYP

MAX

-0.5

-0.15

0.2

-0.5

0.03

0.15

300 Hz to 3 kHz

-0.15

0

0.15

3.3 kHz

-0.35

-0.5

0.3

3.4 kHz

-1

-0.6

-0.1

Filter gain relative to gain at 1020 Hz

4kHz
~4.6

-20

UNIT

dB

-14
-40

kHz

NOTE 3: The filter gain outside of the passband IS measured with respect to the gain at 1020 Hz. The analog Input test
signal is a sine wave with 0 dB = 6 VI(PP) as the reference level for the analog input signal. The passband is
to 3400 Hz.

o

4.4.3
ADC Dynamic Performance
4.4.3.1 ADC Signal-to-Noise (see Note 4)
PAR~METER

MIN

TYP

VI=-1dB

SO

S5

VI =-9 dB

72

77

VI =-40 dB

40

45

TEST CONDITIONS

Signal-to-noise ratio (SNR)

14

21

72

7S

MIN

TYP

VI=-1dB

SO

92

VI =-9 dB

SO

94

VI =-40 dB

40

60

VI =-65 dB

15

40

VI(AUXM, AUXP) = -9 dB

SO

92

VI =-65 dB

MAX

UNIT

dB

VI(AUXM, AUXP) = -9 dB
..
..
NOTE 4: The test condition IS the digital equivalent of a 1020 Hz Input signal with an S kHz conversion rate. The load
impedance is 600 O. Input and output voltages are referred to VOO/2.

4.4.3.2

ADC Signal-to-Distortion (see Note 4)
PARAMETER

TEST CONDITIONS

Signal-to-total harmonic distortion (THO)

..

. .

MAX

UNIT

dB

.NOTE 4: The test condition IS the digital equivalent of a 1020 Hz Input signal with an S kHz conversion rate. The load
impedance is 600 o. Input and output voltages are referred to VOO/2.

4-444

4.4.3.3

ADC Signal-to-Distortion+Noise (see Note 5)
PARAMETER

Total harmonic distortion+noise (THO+N)

TEST CONDITIONS

MIN

TYP

VI =-9 dB

80

83

VI=-1dB

72

76

VI =-40 dB

40

45

VI =-65 dB

14

20

VI{AUXM, AUXP) = -9 dB

72

77

MAX

UNIT

dB

NOTE 5: The test condition is a 1020 Hz input signal with an 8 kHz conversion rate. Input and output voltages are
referred to VOO/2.

4.4.4

ADC Channel
PARAMETER

TEST CONDITIONS

MIN

Oynamic range

VI = -1 dB at 1020 Hz

dB

Gain error, dc

INP = 3 V, INM = 2 V

±0.5

Off-set error, AOC converter
VI = 0 dB at 1020 kHz

4.4.5

Input resistance

dB

8

mV

80

dB
50

70

100

MIN

TYP

MAX

20 Hz

-0.5

0.08

0.15

200 Hz

-0.5

0.08

0.15
0.15

TA = 25°C

dB

±0.6

Idle channel noise (on-chip reference)
Ri

UNIT
dB

80

Gain error

Common-mode rejection ratio INM, INP or
AUXM,AUXP

MAX

86

Interchannel isolation

CMRR

TYP

JlVrms
k.Q

DAC Path Filter (see Note 6)
PARAMETER

Filter gain relative to gain at 1020 Hz

TEST CONDITIONS

300 Hz to 3 kHz

-0.15

0.08

3.3 kHz

-0.35

0.11

0.3

3.4 kHz

-1

-.48

-0.1

4 kHz
~4.6

kHz

-20

UNIT

dB

-14
-40

NOTE 6: The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The input signal is the
digital equivalent of a sine wave (digital full scale = 0 dB). The nominal differential OAC channel peak-to-peak
output voltage with this input condition is 6 V. The pass band is 0 to 3600 Hz.

4-445

4.4.6
4.4.6.1

DAC Dynamic Performance
DAC Signal-to-Noise (see Note 4)
PARAMETER

TEST CONDITIONS

Signal-to-noise ratio (SNR)

MIN

TYP

VO=OdB

74

80

Vo =-9 dB

70

74

Vo =-40 dB

38

44

Vo =-65 dB

14

18

MAX

UNIT

dB

NOTE 4: The test condition is the digital equivalent of a 1020 Hz input signal with an 8 kHz conversion rate. The load
impedance is 600 n. Input and output voltages are referred to VOO/2.

4.4.6.2

DAC Signal-to- Distortion (see Note 4)
PARAMETER

TEST CONDITIONS

Signal-to-total harmonic distortion (THO)

MIN

TYP

Vo =0 dB

74

84

Vo =-9 dB

74

84

Vo =-40 dB

40

58

Vo =-65 dB

18

30

MAX

UNIT

dB

NOTE 4: The test condition is the digital equivalent of a 1020 Hz input signal with an 8 kHz conversion rate. The load
impedance is 600 n. Input and output voltages are referred to VOO/2.

4.4.6.3

DAC Signal-to-Distortion+Noise (see Note 4)
PARAMETER

TEST CONDITIONS
Vo = 0 dB

Total harmonic distortion+noise (THO+N)

MIN

TYP

72

78

VO=-9dB

68

74

Vo =-40 dB

38

44

Vo =-65dB

14

20

MAX

UNIT

dB

NOTE 4: The test condition is the digital equivalent of a 1020 Hz input signal with an 8 kHz conversion rate. The load
impedance is 600 n. Input and output voltages are referred to VOO/2.

4.4.7

DAC Channel
PARAMETER

TEST CONDITIONS

MIN

Dynamic range

dB
dB
±0.5

Vo = 0 dB at 1020 Hz
Digital input offset = 1 V dc

Idle channel broad-band noise

See Note 7

Idle channel narrow-band noise

0-4 kHz,

VOO

Output offset voltage at OUT
(differential)

DIN = All Os

Vo

Analog output voltage,
peak-to-peak, OUTP-OUTM
(differential)

RL = 600,
With internal reference and full-scale
digital input, (see Note 8)

4-446

UNIT

80

Gain error, dc

NOTES:

MAX

80

Interchannel isolation
Gain error, 0 dB

TYP

dB

±0.2

See Note 7

dB
100

~Vrms

40

~Vrms

mV

8

6

7. The conversion rate is 8 kHz; the out-of-band measurement is made from 4800 Hz to FMCLK/2.
8. The digital input to the OAC channel at DIN is in 2s complement.

V

4.4.8

Power Supplies, Voo(ADC)
otherewise noted)
PARAMETER

100 (ADC)
100 (DAC)
100 (Digital)
Po

4.4.9

Power supply current, ADC
Power supply current, DAC

Power supply current, digital

Power dissipation

=Voo(DAC) =DVoo =5 V, No Load (unless
TEST CONDITIONS

MIN

Operating
Power-down

TYP

MAX

12

20

mA

24

~
mA

400

Operating

16

Power-down

mA

2.5
2

Operating

6

mA
~

Power-down

300

Operating

150

250

16

30

TVP

MAX

10

15

6

20

Power-down

UNIT

mW

Timing Requirements (see Notes 9 and 10)
PARAMETER

TEST CONDITIONS

MIN

td1

Delay time, SCLKi to FS.i.

td2

Delay time, SCLKi to DOUT

tsu

Setup time, DIN before SCLK.i.

th

Hold time, DIN after SCLK.i.

ten

Enable time, FS.i. to DOUT

10

tdis

Disable time, Fsi to DOUT Hi-Z

20

td3

Delay time MCLK.i. to SCLKi

25

UNIT

20
CL = 20 pF

20

ns

25

50

NOTES: 9. Refer to Figure 3-1 for timing diagram.
10. When FS occurs after SCLK, it shortens the MSB (D15) duration.

4-447

4-448

5 Application Information
3.9kO

fe = 10.5 kHz
fe = 14.5 kHz
4.99 kn
OUT(+)

220pF
15kn

2210

fe = 19.56 kHz
10kO

3900

IN747B

Telephone
Line

IN747B

T

-=

220pF

0.0331lF
15kn

(+)

O.OlIlF
AGND

fe = 19.56 kHz

10kn
3900
VMID
2210

fe = 40.8 kHz

3900 pF

fe = 10.5 kHz

fe =40.8 kHz

TO.OlIlF
AGND

-=

t----,
3.9 kO

fe = 14.5 kHz
4.99 kn

4.99 kn

AGND

5 VA(ADC)

20kn
+

20kn

-= AGND
Figure 5-1. TLC320AD55C Application Schematic
4-449

5v

20

5VA(ADC)

+JV\Iv-+-'---<
22j.lFP·1j.lF
5VA(DAC)

5VA(ADC)
20

-=-AGND

5 VA(DAC)

0.1 j.lF AGND

IN(+)

26
25
28

IN(-)

24

21

VDD
(ADC)

VSS
(ADC)

0.1 j.lF
22

7

VA
Vss
VDD
(SUB) (OAC) (DAC)

INP

PWRDWN 2

INM
AUXP

20kO
AUXM
TLC320AD55C
23

+

P

AGND

-=-

REFCAPADC

O.1j.lF

22 j.lF

+

22j.lF~
AGND

1 kO
5

6 REFCAPDAC
FS

0.1 j.lF

-=- - -

8

~~~~'"'I RESET

OUT(-)

NC
DR
OX

CLKX
CLKR
FSX
FSR

12

FLAG 0 17
FLAG 1 16

RESET

1--_ _ _1_4... MCLK

OUT(+)

OUTP 3
4
OUTM
18
ALTDATA
11
DOUT
10
DIN
13
SCLK

}

Phone Mode
Programmable Bits (Latched)

15 FC
DVSS

VD(SUB)

VDD

20

19

9

NU

NC

0.1 j.lF

-=-

DGND
+

3V

Figure 5-2. TLC320AD55C 1/0 Buffer and VMID Generator Schematic

4-450

TMS320C5X
DSP
Serial Port

Appendix A
Register Set
Data bits D12 through D8 in the secondary serial communication contain the address of the register, and
data bits D7 through DO contain the data that is to be written to the register. Data bit D13 determines a read
or write cycle to the addressed register. When data bit D13 is low, a write cycle is selected.
The following table shows the register map:

Table A-1. Register Map
015

REGISTER NO.

014

013

012

011

010

09

08

REGISTER NAME

0

0

0

0

0

0

0

0

0

No operation

1

0

0

0

0

0

0

0

1

Control 1

2

0

0

1

0

Control 2

3

4
5

0

0

0

0

0

0

0

0

0

0

1

1

Fkdivide

0

0

0

0

0

1

0

0

Fsclk divide

0

0

0

0

0

1

0

1

Control 3

Table A-2. Control 1 Register
07

06

05

04

03

02

01

00

1

-

-

-

-

Software reset

-

Software reset not asserted

-

Software power down (analog and filters)

-

Select AUXP and AUXM

-

-

Select INP and INM

-

-

Analog output gain

0

-

1

-

0

-

-

1

-

-

0

-

-

-

-

0

0

0

1

-

1

0

-

1

1

-

-

-

1

-

-

-

-

-

-

-

-

-

-

-

-

0

-

-

1

-

0

OESCRIPTION

Software power down (not asserted)

=1
= 1/2
Analog output gain = 1/4
Analog output gain = 0 (squelch)
Analog output gain

Analog loopback asserted
Analog loop back not asserted
Digital loopback asserted
Digital loopback not asserted

1

16-bit mode (hardware secondary requests)

0

Not 16-bit mode (software secondary requests)

Default register value: 00000000

The software reset is a one-shot operation and this bit is cleared to zero after reset. It is not necessary to
write a zero to end the master reset operation.

4-451

Table A-3. Control 2 Register
07
X

06
X

05

04

03

02

01

DO

-

-

-

-

-

-

-

X

-

-

-

-

X

-

-

-

-

X

-

-

-

0

-

-

-

-

-

1

-

-

-

-

-

-

-

-

-

-

-

-

-

0

-

-

1

-

-

-

-

-

DESCRIPTION
Reserved
Decimator FIR overflow flag (valid only during read cycle)
FLAG 1 output value
FLAG 0 output value
Phone mode enabled
Phone mode disabled

-

Normal operation with decimatbr FIR filter

0

Normal operation with interpolator filter

1

Bypass interpolator FIR filter

Bypass decimator FIR filter

Default register value: 00000000

Writing zeros to the reserved bits is suggested.

Table A-4. Fk Divide Register
07

06

05

04

03

02

01

DO

1

1

1

1

1

1

1

1

255

0

0

128

0

0

32

••
•
••
•
••
•

••
•
••
•
••
•

DIVIDE VALUE

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

256

1

0

0

0

0

1

0

0

0

0

Default register value: 00001000

The oversampling clock (FCLK) is set as MCLK/(Fk x 4). MCLK/(Fk x 256) is the sample frequency
(conversion rate) for the converter. When Fk is programmed to zero, its value is interpreted as 256.

4-452

Table A-5. Fsclk Divide Register

D7

D6

D5

D4

D3

D2

D1

DO

1

1

1

1

1

1

1

1

255

0

0

128

0

0

32

1

0

0

0

0

1

0

0

0

0

••
•
••
•
••
•

••
•
••
•
•••

DIVIDE VALUE

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

256

Default register value: 00001000

SCLK is set by MCLKJ(2 x Fsclk). SCLK is for the serial transfer of data to and from the TLC320AD55C.
When Fsclk is programmed to zero, its value is interpreted as 256.

Table A-6. Control 3 Register

D7

D6

D5

D4

D3

D2

D1

DO

DESCRIPTION

0

0

0

0

1

0

0

0

DAC reference disabled

0

0

0

0

0

0

0

0

DAC reference enabled

4-453

4-454

TLC320AD56C
Data Manual
Sigma-Delta Analog Interface Circuit

SLAS101A
September 1996

•
TEXAS
INSTRUMENTS

Printed on Recycled Paper

IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related softWare to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this lNarranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability. for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.

Copyright © 1996, Texas Instruments Incorporated

Contents
Section

Title

Page

1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.1 Features ............................................................
1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.3 Terminal Assignments ............................ '. . . . . . . . . . . . . . . . . . ..
1.4 Ordering Information .................................................
1.5 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.6 Definitions and Terminology .......................................... ,
1.7 Register Functional Summary .........................................

4-461
4-461
4-462
4-463
4-464
4-465
4-466
4-467

2

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.1 Device Functions ....................................................
2.1.1
Operating Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ADC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.1.2
2.1.3
DAC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.1.4
Serial Interface ..............................................
2.1.5
Register Programming .......................................
Sigma-Delta ADC ...........................................
2.1.6
2.1 .7
Decimation Filter .................................... '. . . . . . ..
2.1.8
Sigma-Delta DAC ...........................................
2.1.9
Interpolation Filter ...........................................
2.1.10 Digital Loopback ............................................
2.1.11
FIR Overflow Flag ...........................................
2.2 Terminal Functions ...................................................
2.2.1
Reset and Power-Down Functions .............................
2.2.2
Master Clock Circuit .........................................
2.2.3
Data Out (DOUT) ............................................
2.2.4
Data In (DIN) ...............................................
2.2.5
Hardware Program Terminal (FC) ..............................
2.2.6
Frame-Sync Function ; .......................................
2.2.7
Multiplexed Analog Input .....................................
Analog Input ................................................
2.2.8
2.2.9
Analog Output ..............................................

4-469
4-469
4-469
4-469
4-469
4-469
4-469
4-470
4-470
4-470
4-470
4-470
4-470
4-470
4-470
4-471
4-471
4-471
4-471
4-472
4-472
4-472
4-472

3

Serial Communications ..................................................
3.1 Primary Serial Communication .........................................
3.2 Secondary Serial Communication ......................................
3.3 Conversion Rate vs Serial Port ........................................
3.4 Phone Mode Control .................................................

4-475
4-475
4-477
4-480
4-480

4

Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.1 Absolute Maximum Ratings Over Operating
Free-Air Temperature Range ..........................................
4.2 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.2.1
Recommended Operating Conditions, DVoo = 5 V, AVoo = 5 V ...
4.2.2
Recommended Operating Conditions, DVoo = 3 V, AVoo = 5 V '"

4-481
4-481
4-481
4-481
4-481
4-457

Contents (Continued)
Section

4.3

5

Title

Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, DVoo = 5 V, AVoo = 5 V ...........................
4.3.1
Digital Inputs and Outputs, MCLK = 4.096 MHz,
fs = 8 kHz, Outputs Not Loaded ...............................
4.3.2
Digital Inputs and Outputs, MCLK = 4.096 MHz,
fs = 8 kHz, Outputs Not Loaded, DVoo = 3 V ...................
ADC Path Filter, MCLK = 4.096 MHz, fs = 8 kHz ................
4.3.3
4.3.4
ADC Dynamic Performance, MCLK = 4.096 MHz, fs = 8 kHz ......
4.3.5
ADC Channel ........................ .' .................... "
4.3.6
DAC Path Filter, MCLK = 8.192 MHz, fs = 8.kHz ................
4.3.7
DAC Dynamic PerforlT!ance, DVoo = 5 V or 3 V . . . . . . . . . . . . . . . ..
DAC Channel, DVoo = 5 V or 3 V .............................
4.3.8
4.3.9
Power Supplies, No Load ....................................
4.3.10 Power-Supply Rejection . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . ..
4.3.11
Timing Requirements ........................................

Page

4-482
4-482
4-482
4-482
4-482
4-484
4-484
4-485
4-486
4-486
4-487
4-487

Application Information .................................................. 4-491

Appendix A Re.gister Set .................................................... 4-493

4-458

List of Illustrations
Figure

1-1.
1-2.
1-3.
2-1.
2-2.
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
4-1.
4-2.
4-3.
4-4.
5-1.
5-2.

Title

Functional Block Diagram ................................................
Terminal Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Terminal Assignments ....................................................
Internal Power-Down Logic ...............................................
Differential Analog-Input Configuration .....................................
Primary Serial Communication Timing ......................................
Hardware and Software Ways to Make a Secondary Request .................
Hardware FC Secondary Request
(Phone Mode Disabled) ................................................
Software FC Secondary Request (Phone Mode Disabled) ....................
Phone Mode Timing .....................................................
Secondary DIN Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ADC Decimation Filter Response ..........................................
ADC Decimation Filter Passband Ripple. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DAC Interpolation Filter Response .........................................
DAC Interpolation Passband Ripple ........................................
Application Schematic For Single-Ended Input/Output ........................
Application Schematic For Differential Input/Output ..........................

Page

4-462
4-463
4-464
4-472
4-473
4-476
4-477
4-478
4-479
4-480
4-480
4-488
4-488
4-489
4-489
4-491
4-492

List of Tables
Table

Title

Page

3-1. Secondary Request Format ............................................... 4-476
3-2. Least Significant Bit Control Function ...................................... 4-477
3-3. Secondary Communication Data Format ....................................4-479

4-459

4-460

1 Introduction
The TLC320AD56C provides high resolution low-speed signal conversion from digital-to-analog (D/A) and
from analog-to-digital (NO) using oversampling sigma-delta technology. This device consists of two serial
synchronous conversion paths (one for each data direction) and includes an interpolation filter before the
digital-to-analog converter (OAC) and a decimation filter after the analog-digital-converter (AOC) (see
Figure 1-1). Other overhead functions provide on-chip timing and control. The sigma-delta architecture
produces high resolution NO and D/A conversion at low system speeds and low cost.
The options and the circuit configurations of this device can be programmed through the serial interface.
The options include reset, power-down, communications protocol, serial clock rate, and test mode as
outlined in Appendix A. The TLC320AD56C is characterized for operation from O°C to 70°C.

1.1

Features

The TLC320AD56C includes the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Single 5-V power supply VOltage or 5 V analog and 3 V digital supply voltages
Power dissipation (PD) of 150 mW maximum in the operating mode
Power-down mode to 2.5 mW typical
General-purpose 16-bit signal processing
2's-complement data format
Typical dynamic range of 85 dB for the DAC and 87 dB for the ADC
Minimum 79-dB total signal-to-(noise + distortion) for the ADC
Minimum 80-dB total signal-to-(noise + distortion) for the DAC
Differential architecture throughout the device
Internal reference voltage (Vtef)
Internal 64X oversampling
Serial port interface
Phone-mode output control
System test mode, digitalloopback test mode
Capable of supporting all V.34 sample rates by varying MCLK frequency
Supports business audio applications
Variable conversion rate selected as MCLKl512

4-461

1.2

Functional Block Diagram
>--------------------------MONOUT

INP
INM

I---+~__..t~

MUX

DOUT (2'8complement)

AUXP
AUXM

FILT

----~~----~

Digital
Loopback

IGAIN-f-.........
OUTP-----~

yl---------------

~z

1-:0-

O::::! O~ 0

OZo..::E
00 0

xx

~:::>:::> 0

Zu..>~ZZZZ""",e(e(Z

OUTP

INM

OUTM

INP
NC

NC
VCOM(DAC)

AVDD
NC

NC

NC

PWRDWN
RESET

VSS(SUB)
NC

NC
DVDD
DIN

AVSS
NC

10

NC

11

DOUT

12

DVSS
ALTDATA

1(f)00~~00000~~
u..ZZ...J...JZZZu..Z""""

:S:S
u..u..

00

(f)::E

NC - No internal connection

Figure 1-3. Terminal Assignments

1.4

Ordering Information
PACKAGE

4-464

TA

CHIP CARRIER
(FN)

O°C to 70°C

TLC320AD56CFN

QUAD FLAT PACK
(PT)
TLC320AD56CPT

1.5

Terminal Functions
TERMINALS

I

NUMBER

I/O

DESCRIPTION

19

I

Signals on this terminal are routed to DOUT during secondary communication
if phone mode is enabled.

38

26

I

Inverting input to auxiliary analog input. AUXM requires an external RC antialias
filter.

AUXP

39

27

I

' Noninverting input to auxiliary analog input. Requires an external RC antialias
filter.

AVDD

33

23

I

Analog ADC path supply (5 V only)

DIN

10

11

I

Data input. DIN receives the DAC input data and command information from the
DSP and is synchronized to SCLK.

DOUT

12

12

0

Data output. DOUT transmits the ADC output bits and is synchronized to SCLK.
This terminal is at high-Z when FS is not activated.

NAME

I

PT

FN

ALT DATA

25

AUXM

DVDD

9

10

I

Digital power supply (5 V or 3 V)

DVSS

26

20

I

Digital ground

FC

21

16

I

Function code. FC is sampled and latched on the rising edge of FS for the primary
serial communication. Refer to the Serial Communications section for more
details.

FLAG 0

23

17

0

Output flag O. During phone mode, FLAG 0 contains the value set in Control 2
register.

FLAG 1

24

18

0

Output flag 1. During phone mode, FLAG 1 contains the value set in Control 2
register.

FILT

47

3

0

Bandgap filter. FILT is provided for decoupling of the bandgap reference, and
provides 2.5 V to which the analog inputs or outputs can be referenced. The
optimal capacitor value is 0.1 IlF (ceramic). This voltage node should be loaded
only with a high-impedance dc load.

FS

13

13

0

Frame sync. When FS goes low, the serial communication port is activated. In
all serial transmission modes, FS is h.eld low during bit transmission. Refer to
section 3 Serial Communications for detailed description.

INM

36

25

I

Inverting input to analog modulator. INM requires an external RC antialias filter.

INP

35

24

I

Noninverting input to analog modulator. INP requires an external RC antialias
filter.

IGAIN

45

1

0

Current gain reference scaling. IGAIN is provided for decoupling of the current
gain reference and provides il 1.35-V reference. The optimal load is a
27-K resistor.

MCLK

17

15

I

Master clock. The master clock derives the internal clocks of the sigma-delta
analog interface circuit.

MONOUT

40

28

0

Monitor output. MONOUT allows for monitoring of the analog input and is a
high-impedance output. The gain or mute is selected using Control 2 register.

0

Inverting current output of the DAC. OUTM is functionally identical with and
complementary to OUTP. OUTM and OUTP current outputs can be loaded with
5 kU differentially or single-ended. This signal can also be used alone for
single-ended operation.

OUTM

2

6

NOTE 1: All digital inputs and outputs are TTL-compatible, unless otherwise noted for DVDD

=5 V.
4-465

1.5

Terminal Functions (Continued)
TERMINALS

I
I

1/0

DESCRIPTION

5

0

Noninverting current output of the DAC. OUTM and OUTP current outputs can
be loaded with 5 kQ differentially or single ended. This signal can also be used
alone for single-ended operation.

6

8

I

Power down. When this terminal is pulled low, the device goes into a power-down
mode; the serial interface is disabled and most of the high-speed clocks are
disabled. However, all the register values are sustained and the device resumes
full power operation without reinitialization when this terminal is pulled high
again. PWRDWN resets the counters only and preserves the programmed
register contents. See subsection 2.21. Reset and Power-Down Functions.

7

9

I

Reset. The reset function is provided to initialize all the internal registers to their
default values. 'The serial port can be configured to the default state accordingly.
Refer to section 1.7 Register Functional Summary and SUbsection 2.2.1 Reset
and Power-Down Functions for more detailed descriptions.

SCLK

16

14

0

Shift clock. The shift clock signal is derived from MCLK and is used to clock serial
data into DIN and out of DOUT.

VSS(SUB)

30

22

I

Analog substrate. This terminal must be grounded.

VCOM(ADC)

46

2

0

Common mode filter. This terminal is provided for decoupling of the common
mode reference and provides a 2.5 V reference. The optimal capacitor value is
0.10 1lF. This node should be loaded only with a high-impedance dc load.

VCOM(DAC)

4

7

0

Common mode filter. This terminal is provided for decoupling of the common
mode reference and provides a 2.5 V reference. The optimal capacitor value is
0.10 1lF. This node should be loaded only with a high-impedance dc load.

28

21

I

NAME

NUMBER
PT

FN

OUTP

1

PWRDWN

RESET

AVSS

Analog ground

NOTE 1: All digital inputs and outputs are TTL-compatible, unless otherwise noted for DVDD = 5 V.

1.6

Definitions and Terminology

Data Transfer Interval

This is time during which data is transferred from DOUT and to DIN. This interval
is 16 shift clocks and this data transfer is initiated by the falling edge of the
frame-sync signal.

Signal Data

This refers to the input signal and all of the converted representations through the
ADC channel and return through the DAC channel to the analog output. This is
contrasted with the purely digital software control data.

Primary
Communications

Secondary
Communications

Frame Sync

4-466

This refers to the digital data transfer interval. Since the device is synchronous, the
signal data words from the ADC channel and to the DAC channel occur
simultaneously.
This refers to the digital control and configuration data transfer interval into DIN and
. the register read data cycle from DOUT. The data transfer interval occurs when
requested by hardware or software.
Frame sync refers only to the falling edge of the signal that initiates the data transfer
interval. The primary frame sync starts the primary communications, and the
secondary frame sync starts the secondary communications.

Frame Sync and'
Sampling Period

f5
Frame-Sync Interval

The time between the falling edges of successive primary frame-sync signals.
The sampling frequency that is the reciprocal of the sampling period.
The time period occupied by 16 shift clocks. It goes high on the sixteenth rising
edge of SCLK after the falling edge of the frame sync.

ADC Channel

This term refers to all signal processing circuits between the analog input and the
digital conversion results at DOUT.

DAC Channel

This term refers to all signal processing circuits between the digital data word
applied to DIN and the differential output analog signal available at OUTP and
OUTM.

Host

Any processing system that interfaces to DIN, DOUT, SCLK, or FS.

Dxx

Bit position in the primary data word (xx is the bit number).

DSxx

Bit position in the secondary data word (xx is the bit number).

d

The alpha character d represents valid programmed or default data in the control
register format (see section 3.2 Secondary Serial Communications) when
discussing other data bit portions of the register.

x

The alpha character X represents a do-not-care bit position within the control
register format.

FIR

Finite duration impulse response.

1.7

Register Functional Summary

There are three data and control registers that are used as follows:
Register 0

The No-Op register. The 0 address allows secondary requests without altering any other
register.

Register 1

The Control 1 register. The data in this register controls:

•

The software reset

•

The software power down

•

Selection of the normal or auxiliary analog inputs

•

Selection of the digital loopback

•

16-bit or 1S-bit mode of operation

•

Selection of monitor amp output

Register 2

The Control 2 register. The data in this register:

•

Contains the output flag indicating a decimator FIR filter overflow

•

Contains Flag 0 and Flag 1 output values for use in the phone mode

•

Selects the phone mode

4-467

4-468

2

Functional Description

2.1

Device Functions

The functions of the TLC320AD56C are described in the following sections.

2.1.1

Operating Frequencies

The sampling (conversion) frequency is derived from the master clock (MCLK) input by equation 1.
fs

=

Sampling (conversion) frequency

= M5~~K

(1)

The inverse is the time between the falling edges of two successive primary frame synchronization signals
and is the conversion period.

2.1.2

ADC Signal Channel

To produce excellent common-mode rejection of unwanted signals, the analog signal is processed
differentially until it is converted to digital data.
The input signal is filtered and applied to the ADC input. The ADC converts the signal into discrete output
digital words in 2s-complement format, corresponding to the analog signal value at the sampling time. These
16-bit digital words, representing sampled values of the analog input signal, are clocked out of the serial port
during the frame-sync interval, (DOUT), one word for each primary communication interval. During
secondary communications, the data previously programmed into the registers can be read out with the
appropriate register address, and the read bit set to 1. When no register read is requested, all 16 bits are
O"in the secondary word.

2.1.3

DAC Signal Channel

DIN receives the 16-bit serial data word (2's complement) from the host during the primary communications
interval and latches the data on the seventeenth rising edge of SCLK. The data are converted to an analog
current by the sigma-delta DAC comprised of a digital interpolation filter, and a digital 1-bit modulator. The
DACs differential outputs OUTP and OUTM are a current output-type, (which requires resistive loading 5kn
maximum). These outputs are then connected to the external low pass filter, as shown in the application
schematics in Figure 3-7 and Figure 3-8 to complete the signal reconstruction. This filter can be
incorporated in the data access arrangement (OM) for modem applications.

2.1.4

Serial Interface

The digital serial interface consists of the shift clock, the frame synchronization signal, the ADC-channel
data output, and the DAC-channel data input. During the primary 16-bit frame synchronization interval, the
SCLK transfers the ADC channel results from DOUT and transfers 16-bit DAC data into OIN.
During the secondary frame synchronization interval, the SCLK transfers the register read data from DOUT
when the read bit is set to a 1. In addition, the SCLK transfers control and device parameter information into
DIN. The functional sequence is shown in Figure 3-1.

2.1.5

Register Programming

All register programming occurs during secondary communications, and data is latched and valid on the
rising edge of the frame-sync signal. When the default value for a particular register is desired, that register
does not need to be addressed during the secondary communications. The no-op command addresses the
pseudo-register (register 0), and no register programming takes place during this communications.

4-469

DOUT is released from the high-impedance state on the falling edge of the primary or secondary frame-sync
interval. In addition, each register can be read back during DOUT secondary communications by setting the
read bit D13 to 1 in the appropriate register. When the register is in the read mode, no data can be written
to the register during this cycle. To return this register to the write mode requires a subsequent secondary
communication.

2.1.6

Sigma-Delta ADC

The sigma-delta ADC is a fourth-order sigma-delta modulator with 64 times oversampling. The ADC
provides high resolution and low noise performance using oversampling techniques.

2.1.7

Decimation Filter

The decimation filter reduces the digital data rate to the sampling rate. This is accomplished by decimating
with a ratio of 1:64. The output of this filter is a sixteen-bit 2's-complement data word clocking at the sample
rate selected.

NOTE
The sample rate is determined through a relationship of MCLKl512.

2.1.8

Sigma-Delta DAC

The sigma-delta DAC is a fourth-order sigma-delta modulator with 64 times oversampling. The DAC
provides high-resolution, low-noise performance from a 1-bit converter using oversampling techniques. The
TLC320AD56C is a current-output DAC and requires a load resistor for current-to-voltage conversion (see
Figures 3-7 and 3-8).

2.1.9

Interpolation Filter

The interpolation filter resamples the digital data at a rate of 64 times the incoming sample rate. The
high-speed data output from this filter is then used in the Sigma-delta DAC.

2.1.10

Digital Loopback

The digitalloopback provides a means of testing the ADC/DAC channels and can be used for in-circuit
system-level tests. The loopback feeds the ADC output to the DAC input on the IC.
Digitalloopback is enabled by setting the appropriate bit in Control 1 register (see Appendix A).

2.1.11

FIR Overflow Flag

The decimator FIR filter provides an overflow flag to the Control 2 register to indicate that the input to the
filter has exceeded the range of the internal filter calculations. When this bit is set in the register, it will remain
set until the register is read by the user. Reading this value will always reset the overflow flag.

2.2

Terminal Functions

The terminal functions are described in the following sections.

2.2.1

Reset and Power-Down Functions

2.2.1.1

Reset

The TLC320AD56C resets the internal counters and registers, including the programmed registers, in one
of two ways:
1.

By applying a low-going reset pulse to the reset terminal

2.

By writing to the programmable software reset bit (D07 in Control 1 register)

PWRDWN resets the counters only and preserves the programmed register contents. The PWRDWN
terminal must be kept low 20 ms after the power supplies have settled.
4-470

2.2.1.2

Conditions of Reset

The two internal reset signals used for the reset and synchronization functions are:
1.

Counter Reset -

This signal resets all flip-flops and latches that are not externally programmed,
with the exception of those generating the reset pulse itself. Additionally, this
signal resets the software power-down bit. A counter reset is initiated with the
RESET terminal or RESET bit or PWRDWN terminal.

2.

Register Reset - This signal resets all flip-flops and latches that are not reset by the counter
reset, except those generating the reset pulse itself. A register reset is initiated
with the RESET terminal or RESET bit.

Both reset signals should be at least six master clock periods long, T RESET, and should release on the trailing
edge of the master clock.

2.2.1 .3

Software and Hardware Power Down

Given the definitions above, the software programmed power-down condition is cleared by clearing the
software bit (Control 1 register, bit 6) to a or by cycling the power to the device or bringing RESET low.

a

The output of the monitor amplifier maintains its midpoint voltage during hardware and software power
downs to minimize pops and clicks.
PWRDWN powers down the entire chip. Cycling the power-down terminal from high to low and back high
resets all flip-flops and latches that are not externally programmed, thereby preserving the register contents.
When PWRDWN is not used, it should be tied high.

2.2.2

Master Clock Circuit

The clock circuit generates and distributes necessary clocks throughout the device. MCLK is the external
master clock input. SCLK is derived from MCLK in order to provide clocking of the serial communications
between the device and a digital signal processor (DSP). The sample rates of the data paths are set to
MCLKJ512.

2.2.3

Data Out (OOUT)

DOUT is taken from the high-impedance state by the falling edge of frame sync. The most significant data
bit then appears on DOUr.
DOUT is placed in a high-impedance state on the sixteenth rising edge of SCLK after the falling edge of
frame sync. In the primary communication, the data word is the ADC conversion result. In the secondary
communication, the data is the register read results when requested by the read/write (R/W) bit with the
eight MSBs set to (see Section 3 Serial Communications). If no register read is requested, the secondary
word is all zeroes.

a

2.2.4

Data In (DIN)

In the primary communication, the data word is the input digital signal to the DAC channel. In the secondary
communication, the data is the control and configuration data to set up the device for a particular function.
(see section 3 Serial Communications).

2.2.5

Hardware Program Terminal (FC)

FC provides for hardware programming requests for secondary communication. It works in conjunction with
the control bit DOO of the secondary data word. The signal on FC is latched 1/2 shift clock after the rising
edge of the next internally generated primary frame-sync interval. The FC terminal should be tied low when
not used (see Section 3.2 Secondary Serial Communication and Table 3-2).
4-471

2.2.6

Frame-Sync Function

The frame-sync signal indicates that the device is ready to send and receive data. The data transfer from
DOUT and into DIN begins on the falling edge of the frame-sync signal.
The frame sync is generated internally and goes low on the rising edge of SCLK and remains low during
the 16-bit data transfer.

2.2.7

Multiplexed Analog Input

The two differential analog inputs (INP and INM or AUXP and AUXM) are multiplexed into the sigma-delta
modulator. The performance of the AUX channel is similar to the normal input channel. A simple RC
antialiasing filter must be connected to AUXP and AUXM (also INP and INM when used) .

.------------------------,
1

1

1
PWRDWN -+1~--e---~..._{A~....'>.-__I~

1
1
1

Digital Circuitry
Power Down

Analog Circuitry
Power Down

Bit 6 is Programmed
Through a Secondary
Write Operation

1

1
1
1
1

L ___
____________________
1
Internal TLC320AD56C
~

~

Figure 2-1. Internal Power-Down Logic

2.2.8

Analog Input

The signal applied to the terminals INM and INP (shown in Figure 2-2) should be differential to preserve
the device specifications. A single-ended input signal should always be converted to a differential input
signal prior to being used by the TLC320AD56C (see section 5 Application Information). The signal source
driving the analog inputs (INM, INP, AUXM, AUXP) should have a low source impedance for lowest noise
performance and accuracy. To obtain maximum dynamic range, the input signal should be centered at
midsupply. A simple RC anti aliasing filter must be connected to INP and INM (also AUXP and AUXM if used).
A suitable tradeoff for the cutoff frequency (feol of the antialiasing filter is feo =3 x Is. With this cutoff frequency,
the attenuation within the band of interest (0 - fs/2) is less than 0.1 dB.

2.2.9

Analog Output

The analog output swing across the OUTP and OUTM terminals depends on the value of the resistor used
from the IGAIN terminal to analog ground and the resistor load across the OUTP and OUTM terminals. Both
resistors can be used to set the output voltage swing and then gained to the desired value in the external
DAC output filter as shown in Figure 5-1 and Figure 5-2. With this external filter, the gain of the DAC channel
is "-2.5 dB.
The resistor on the IGAIN terminal sets up the output current pumped and the resistor across OUTP and
OUTM is the load which converts the current output of the DAC to a voltage. Hence, the voltage swing across
OUTP and OUTM depends on the ratio of the load resistor to the value of the resistor from the IGAIN terminal
to analog ground. With 0 dB digital code applied to the DAC channel, the IGAIN resistor set at 27 kil, and
a load resistor of 5 kil, the output swing across OUTP and OUTM is -10.5 dB. The ratio of IGAIN resistance
to load resistance can be adjusted to get the desired voltage swing. For the best distortion performance,
it is recommended that the output swing be limited to -6 dB relative to 6 Vpp.
4--472

TLC320AD56C

~:: -?Sd-?i-;(

___

IN_M
_ _ _ _ __

Figure 2-2. Differential Analog-Input Configuration

4-473

4-474

3 Serial Communications
DOUT, DIN, SCLK, FS, and FC are the serial communication signals. The digital output data from the ADC
is taken from DOUT. The digital input datafor the DAC is applied to DIN. The synchronizing clock for the
serial communication data and the frame sync is taken from SCLK. The frame synchronization pulse that
encloses the ADC/DAC data transfer interval is taken from FS. For an audio signal data transmitted from
the ADC or to the DAC, primary serial communication is used. To read or write words that control both the
options and the circuit configurations of the device, secondary communication is used.
The purpose of the primary and secondary communications is to allow conversion data and control data to
be transferred across the same serial port. A primary transfer is always dedicated to conversion data. A
secondary transfer is used to set up and read the register values described in Appendix A. A primary transfer
occurs for every conversion period. A secondary transfer occurs only when requested. Two methods exist
for requesting a secondary command. The FC terminal can be used to request a secondary communication
by asserting it, or the least significant bit (LSB) of the DAC data within a primary transfer can request a
secondary communication. The selection of which method is enabled is provided in Control 1 register (bit
DO) as shown in Appendix A.
For all serial communications, the most significant bit (MSB) is transferred first. For a 16-bit ADC word and
a 16-bit DAC word, 015 is the MSB and DO is the LSB. For a 15-bit DAC data word in the 16-bit primary
communication, 015 is the MSB, 01 is the LSB, and DO is used for the embedded function control. All digital
data values are in 2s-complement format.
These logic signals are compatible with TTL-voltage levels and CMOS current levels (when VDD = 5 V dc).
These logic signals are also compatible with a 3-V supply.

3.1

Primary Serial Communication

A primary serial communication transmits and receives conversion signal data. The ADC word length is
always 16 bits. The DAC word length depends on the status of DO in the Control 1 register. After power up
or reset, the device defaults to a 15-bit mode (not 16-bit mode). The DAC word length is 15 bits and the last
bit of the primary 16-bit serial communication word is a function control bit used to request secondary serial
communications. In 16-bit mode, all 16 bits of the primary communications word are used as data for the
DAC and the hardware terminal FC must be used to request secondary communications.

4--475

Figure 3-1 shows the timing r,elationship for SCLK, FS, DOUT and DIN in a primary communication. The
timing sequence for this operation is as follows:
1.

FS is brought low by the TLC320AD56C.

2.

One 16-bitword is transmitted from the ADC (DOUT) and one 16~bit word is received for the DAC
(DIN),
.

3.

FS is brought high by the TLC320AD56C signaling the end of the conversion.

-.I 14I I

td3

MCLK

VIL
- - - - VOH

SCLK
1

td1

VOL

0th

-.Ii+--

I
I
14- td2
I
I
- - - - I - -I - - - r - -JJ- ' , ' T - - - - - - ' t I
I
14tdis --.j
I

--1F--1
ten

---.I

1

(

DOUT
In 16·Bit Mode:
DIN

wx

D15
tsu

~

D15
MSB

X r ~b<
14

~

I

14
1

D15

X

D14

th

~

MSB

D1

X

D1

X

DO

l+-

VOH
VOL

~

~

tsu
In 16·Bit Mode:

~X

t,·

X,-....,.__~b<

th

DIN

{-----

((

DO
LSB

~A

~

~

I

I

~b<

D1

X

FC

LSB

~A

~

Figure 3-1. Primary Serial Communication Timing
When a secondary request is made through the LSB of the DAC data word (16-bit mode), the format in
Table 3-1 is used.

Table 3-1. Secondary Request Format

..
..

4-476

15-bit DAC _ _ _ _ _ _ _ _ _'--_ _ _ _ _ _ _-I~~..
~
2's-complement format
control
16-bit ADC ----------------------I~~
2's-complement format

3.2

Secondary Serial Communication

Secondary serial communication is used to read or write 16-bit words that program both the options and the
circuit configurations of the device. All register programming occurs during secondary communications. Two
primary and secondary communication cycles are required to program the two registers. When the default
value for a particular register is desired, then the user could omit addressing it during secondary
communication. The NOOP command addresses a pseudo-register, register 0, and no register
programming takes place during this secondary communication.
There are two methods for initiating secondary communications. They are 1) by asserting a high signal level
on FC, or 2) by asserting the LSB of the DIN 16-bit serial communication high while not in 16-bit mode (see
Control 1 register, bit 0).
FC
(Hardware)

,------------------------,I

-ll--------------,---.....>--__
(LSB of DIN)

Secondary
Request

--~,-"""

I
I
I

I

16-Bit Mode
(Control 1 Register,
IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Bit 0)
I
_______ ~
I Internal TLC320AD56C
I

Figure 3-2. Hardware and Software Ways to Make a Secondary Request
1.

Figures 3-3 and 3-4 show the two different ways FC requests secondary communication words
as well as the timing for FS, DOUT, DIN, and SCLK. The examples span two primary
communication frames. Figure 3-3 shows the use of hardware function contro\.
, During a secondary communication, a register may be written to or read from. When writing a
value to a register, the DIN line contains the value to be written. The data returned on DOUT is
OOH. When performing a read function, the DIN line may still provide data to be written to an
addressed register; however, the DOUT line contains the most recent value in the register
addressed by DIN.
In Figure 3-3, FC is clocked in and latched on the rising edge of frame sync (FS). This causes
the start of the secondary information 32 FCLKs after the start of the primary communication
frame. Read and write examples are shown for DIN and DOUT.

2.

Figure 3-4 shows the use of software function contro\.
The software request is typically used when the required resolution of the DAC channel is less
than 16 bits. Then the least significant bit (DO) can be used for the secondary requests as shown
in Table 3-2.

Table 3-2. Least Significant Bit Control Function
Control Bit DO

Control Bit Function

0

No operation (NOOP)

1

Secondary communication request

On the falling edge of the next FS, D15-D1 is input to DIN or D15-DO is output to DOUT.
When a secondary communication request is made, FS goes low 32 FCLKs after the beginning of the
primary frame.
'

4-477

. Communication' Frame 1 (CF1)

(CF2)

~(J.

Primary

1

FC

1

DOUT

(Secondary
Read)

(Secondary
Write)

DIN
(Secondary
Read or Write)
16SCLKs

~I

8 SCLKs

kADg~ata ~~ ~(I
kADg~ata ~""(J
~ ~egister
k:
i\-----I
r
.

1

1

DOUT

I'" .

1

-----

1

I

1
ADC Data ~w. All Bits 0
.
Out
r-'I
1

Data

1
K-A":"':D":"':C~D~a"!'"ta"'~T-(_ _ _ __

----"

II

&4

kDACData,nW~ Setf:;!:ryw#
~
~
i...
~I 16 SCLKs

1

1

14-- 32 FCLKs ---+i
1

r-

64 FCLKs

J

Out

.

.

1

DAC Data I n W . # 0 2

I'"

~I

16 SCLKs

1

I.,..

64 FCLKs

I.

1

~I

Figure 3-3. Hardware Fe Secondary Request
(Phone Mode Disabled)
In Figure 3-4, FC hardware terminal 15 is left in its unasserted state (0). Fe is asserted through software
by embedding an asserted high level (1) in the LSB of the 16-bit primary word. This is possible when not
in 16-bit mode (Control 1 register, bit 2 = 0) because the user is using only 15 bits of DAC information.

4-478

t::t:

FS 1

Primary

~'

r----Sr--, _ . r'
~

T

)If

I
I

FC

(CF2)

Communication Frame 1 (CF1)

I
I

Primary ( '
..

)

I

o
I D15-D1

.

I
I

t;

DO = 1

~o Request
Secondary

'/,

/
I

015-01

=0

I
I

See Note A

I

DO

')\

(secon~~~y k
DAC Data~S-:f:~~:ryw
# ~ DAC Data~~I
I

Read or Write)
DOUT

(seco~::~

DOUT
(Secondary
Write)

16 SCLKs

I
I

Software FC Bit

K

AOC Data

~

~

~

8 SCLKs

I
I

.

\

(

~

I
I

I
I

~........

I

Register
Data

KADCData~~'j

IU
I.
I

U

~\

~

.:

16SCLKs

I
I
14-- 32 FCLKs ~

I~

I

kADCData~'j

I
I
I
I

I
I

I

I~·

I

Data~'j

ADC

I

I~

~

16SCLKs

:

:

I
I

I...

64 FCLKs

.1

64 FCLKs

.:

NOTE A: For a read cycle, the last 8 bits are do-not-care bits.

Figure 3-4. Software FC Secondary Request (Phone Mode Disabled)
Table 3-3 shows the secondary communications format. 013 is the read/not-write (R/W) bit.

012-08 are address bits. The register map is specified in the register set section in Appendix A. 07-00
are data bits. The data bits are the new values for the specified register addressed by 012-08.
Table 3-3. Secondary Communication Data Format

RIW

A

A

A

A

A

o

o

o

o

o

o

o

o

4-479

3.3

Conversion Rate vs Serial Port

The SCLK frequency is set by the frequency of MCLK. There is a 2-stage clock divider that sets the SCLK
frequency as MCLKJ4.

·3.4

Phone Mode Control

Phone mode control is provided for application$ that need hardware control and monitoring of external
events. By allowing the device to drive two FLAG terminals (set through the Control 2 register), the host
(DSP) is capable of system control through the same serial port that connects to the device. Along with this
control is the capability of monitoring the value of the ALT DATA terminal during a secondary communication
cycle. One application for this function is in monitoring RING DETECT or OFFHOOK DETECT from a phone
answering system. The two FLAG terminals allow response to these incoming control signals. Figure 3-6
shows the timing associated with this operating mode.

FS

l

Primary

Secondary

Primary

Secondary

Primary

r------.

r---""'"lI

r_

Register

ALT DATA

_
~
(secondary'''-_--J>----I
DOUTJ

Read)

-

Data

)

~

8SCLKs I·

-I

ALTDATA

:~~~/~r~

DIN

1 SCLK MAX

-<'--~10~@?{~____
~~~""'-'0f..~~·
..&'..~~~"*_"'@~---'-'-'}20"""""""'0(~--.c.)
=
=
=
=
Set FLAGO FLAG1

1

Set FLAGO FLAG1

0

I

FF'i.~~01·~g

Figure 3-5. Phone Mode Timing
Do Not Care

,--_~A,-

_ _-.

(seco~::~ ~W0"""'-"""'-""'~""'''''_'_~''''''''__..L-_. .~~1. .....'L..-L.-.''--~===::1L...(
__8_Bi_ts_.....LIW""-'~~~""'-'~~~
v
RIW

Register Address

(Seco~~:~ 0",",,~~'""'~"'""~'""'~.....I--'-r_jL.....&I-...L.I_A.&..1....I1L.......L1_ _B_lts_--"-~"'""~'""'~:.....:;~""""
...

8

"'-----.v,..----J'
Data to the
Register

Figure 3-6. Secondary DIN Format

4-480

.....

4 Specifications
4.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)t
Supply voltage range, DVoo AVoo (see Note 1) ...................... -0.3 V to 7 V
Output voltage range, DOUr, FS, SCLK, FLAGO, FLAG1 .... -0.3 V to DVoo + 0.3 V
Output voltage range, OUTP, OUTM ........................ -0.3 V to Voo + 0.3 V
Input voltage range, DIN, PWRDWN, RESET, ALT DATA,
MCLK, FC ......................................... -0.3 V to DVoo + 0.3 V
Input voltage range, INP, INM, AUXP, AUXM ................ -0.3 V to Voo + 0.3 V
Case temperature for 10 seconds, Tc: OW package ......................... 260°C
Operating free-air temperature range, TA ............................ O°C to 70°C
Storage temperature range, Tstg ................................. -65°C to 150°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.

4.2

Recommen~ed

Operating Conditions
MIN

Supply voltage, AVDD
(see Note 2)
Analog signal input voltage,
VI(analog)

I

NOM

4.75

Differential, (INP-INM) peak,
for full scale operation

Resistance, IGAIN, R(IGAIN)

27

20

Load resistance, OUTP, OUTM, RL

5/27

x

ADC or DAC conversion rate
(sample rate)
Operating free-air temperature, TA

4.2.1

Recommended Operating Conditions, DVoo

High-level input voltage, VIH

0

NOM

4.5

V

6

V

54

kn

22.05

kHz

70

°C

MAX
5.5

UNIT
V
V

0.8
4.096

V

11.29

MHz

UNIT

=3 V, AVoo =5 V
MIN

NOM

MAX

Supply vOltage, DVDD (see Note 2)

2.7

3

3.3

High-level input voltage, VIH

1.8

Low-level input voltage, VIL

"

kn

2

LOW-level input voltage, VIL

Recommended Operating Conditions, DVoo

5.25

=5 V, AVoo =5 V

MCLK frequency (see Note 3)

4.2.2

UNIT

R(lGAIN)
8

MIN
Supply voltage, DVDD (see Note 2)

MAX

V
V

0.6

MCLK frequency (see Note 3)
4.096
11.29
NOTES: 2. Voltages at analog inputs and outputs and VDD are with respect to the VSS terminal.
3. The default state for an 8-kHz conversion rate requires a 4.096-MHz MCLK frequency.

V
MHz

4-481

4.3

Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, DVDD = 5 V, AVDD = 5 V (Unless Otherwise Noted)

4.3.1

Digital Inputs and Outputs, MCLK = 4.096 MHz, fs =,8 kHz, Outputs Not Loaded
PARAMETER

TEST CONDITIONS

IJA

MIN

TYP

2.4

4.6

MAX

'UNIT

High-level output voltage, DOUT

10 = 360

VOL

Low-level output voltage, DOUT

10=2mA

IIH

High-level input current, any digital input

VIH =5 V

IlL

Low-level input current, any digital input

VIL = 0.8 V

Ci

Input capacitance

5

pF

Co

Output capacitance

5

pF

VOH

4.3.2

0.4

V

10

/lA

10

IJA

Digital Inputs and Outputs, MCLK = 4.096 MHz, fs =8 kHz, Outputs Not Loaded,
DVoo 3 V

=

PARAMETER
VOH

0.2

V

TEST CONDITIONS

High-level output voltage, DOUT

10 = 360 /lA

MIN

TYP

MAX

UNIT
V

2

VOL

Low-level output voltage, DOUT

10=2 rnA

0.4

V

IIH

High-level input current, any digital input

VIH = 3.3 V

10

IlL

Low-level input current, any digital input

VIL = 0.6 V

10

IJA
IJA

Ci

Input capacitance

5

pF

Co

Output capacitance

5

pF

4.3.3

ADC Path Filter, MCLK = 4.096 MHz, fs
PARAMETER

= 8 kHz (see Note 4)

TEST CONDITIONS

o to 300 Hz
300 Hz to 3 kHz
Filter gain relative to gain at 1020 Hz

3.3 kHz

MIN

TYP

MAX

-0.5

0.2

-0.35

0.2

-0.4

0.3
-3

3.6 kHz
4 kHz

-40

~4.4

-74

kHz

UNIT

dB

NOTE 4: The filter gain outside of the passband IS measured with respect to the gam at 1020 Hz. The analog Input test
signal is a sine wave with 0 dB = 6 VI(PP) as the reference level for the analog input signal. The -1 dB pass
band is 0 to 3400 Hz for an 8-kHz sample rate. This pass band scales linearly with the sample rate.

4.3.4
4.3.4.1

ADC Dynamic Performance, MCLK

=4.096 MHz, fs =8 kHz

ADC Signal-to-Noise (see Note 5)
PARAMETER

TEST CONDITIONS

MIN

TYP

VI =-3 dB

80

84

VI =-6 dB

76

81

UNIT

86

VI = -1 dB

Signal-to-noise ratio (SNR)

MAX

VI =-9 dB

73

78

VI =-40 dB

42

47

VI =-65dB

17

22

VAUX=-9dB

73

78

dB

NOTE 5: The test condition is a 1020-Hz input signal with an 8-kHzconverslon rate. Input and output voltages are
referred to AVDO/2.
.
4-482

4.3.4.2

ADC Signal-to-Distortion (see Note 5)
PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

78

VI =-1 dB

Signal-to-total harmonic distortion (THO)

TYP

VI =-3 dB

74

79

VI=-6dB

77

82

VI =-9 dB

80

85

VI =-40 dB

65

70

VI =-65 dB

42

47

VAUX =-9 dB

80

85

dB

NOTE 5: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output voltages are
referred to VOO/2.

4.3.4.3

ADC Signal-to-Distortion, DVDD
PARAMETER

= 3 V (see Note 5)
TEST CONDITIONS

MIN

MAX

UNIT

79

VI =-1 dB

Signal-to-total harmonic distortion (THO)

TYP

VI =-3 dB

90

95

VI = -6 dB

92

100

VI =-9 dB

94

103

VI =-40 dB

68

76

VI = -65 dB

42

52

VAUX=-9dB

94

103

dB

NOTE 5: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output voltages are
referred to VOO/2.

4344

ADC Signal-to-Distortion+Noise (see Note 5)
PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

77

VI =-1 dB

Total harmonic distortion + noise (THD+N)

TYP

VI =-3 dB

73

78

VI =-6 dB

73

78

VI =-9 dB

72

77

VI =-40 dB

41

46

VI =-65 dB

16

21

VAUX=-9dB

72

77

dB

NOTE 5: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output voltages are
referred to VOO/2.

4-483

4.3.4.5

ADC Signal-to-Distortion+Noise, DVoo = 3 V (see Note 5)
PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

78

VI =-1 dB

Total harmonic distortion + noise (THD+N)

TYP

VI =-3 dB

79

84

VI =-6 dB

76

81

VI =-9 dB

73

78

VI =-40 dB

42

47

VI =-65dB

17

22

VAUX=-9dB

73

78

dB

NOTE 5: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output voltages are
referred to VDD/2.

4.3.5

ADC Channel
PARAMETER

VI(PP)

TEST CONDITIONS

MIN

Peak-to-peak input voltage

Interchannel isolation
VI = -1 dB at 1020 Hz

Gain error

EO(ADC)

ADC converter offset error

CMRR

Common-mode rejection ratio at INM,
INP or AUXM, AUXP

VI = 0 dB at 1020 kHz

Idle channel noise (on-chip reference)

DAC Path Filter, MCLK
PARAMETER

dB

5

mV

80

dB
75

J.lVrms

100

k.Q

17/fs

s

=8.192 MHz, f8 =8 kHz (see Note 6)
TEST CONDITIONS

o to 300 Hz
Filter gain relative to gain at 1020 Hz

V

110
±0.3

30
TA = 25°C

Channel delay

4.3.6

UNIT

87

EG

Input resistance

MAX

6

Dynamic range

Ri

TYP

MIN

TYP

MAX

-0.5

0.2

300 Hz to 3 kHz

-0.25

0.25

3.3 kHz

-0.35

0.3

3.6 kHz

-3

4kHz

-40

;;:;-4.4 kHz

-74

UNIT

dB

NOTE 6: The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The input signal is the
digital equivalent of a sine wave (digital full scale = 0 dB). The nominal differential DAC channel output with
this input condition is 6 VI(PP). The -1 dB pass band is 0 to 3400Hz for an 8-kHz sample rate. This pass band
scales linearly with the sample rate.

4-484

4.3.7
4.3.7.1

DAC Dynamic Performance, DVoo = 5 V or 3 V
DAC Signal-to-Noise (see Note 7)
PARAMETER

TEST CONDITIONS

Signal-to-noise ratio (SNR)

MIN

TYP

Va = 0 dB

80

85

Va =-9 dB

72

77

Va =-40dB

41

46

Va =-65 dB

16

21

MAX

UNIT

dB

NOTE 7: .The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test
is measured at the output of a single pole RC filter with a cutoff frequency of 32 kHz. The test is conducted in
16-bit mode.

4.3.7.2

DAC Signal-to-Distortion (see Note 7)
PARAMETER

TEST CONDITIONS

Signal-to-total harmonic distortion (THD)

MIN

TYP

Va = OdB

86

92

Va =-9 dB

90

96

Va =-40 dB

60

66

Va =-65 dB

40

46

MAX

UNIT

dB

NOTE 7: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test
is measured at the output of a single pole RC filter with a cutoff frequency of 32 kHz. The test is conducted in
16-bit mode.

4.3.7.3

DAC Signal-to-Distortion+Noise (see Note 7)
PARAMETER

TEST CONDITIONS

Total harmonic distortion + noise (THD+N)

..

..

MIN

TYP

Va =OdB

80

84

Va =-9 dB

72

76

VO=-40dB

41

45

VO=-65dB

16

20

MAX

UNIT

dB

NOTE 7: The test condition IS the digital equivalent of a 1020-Hz Input signal with an 8-kHz conversion rate. The test
is measured at the output of a single pole RC filter with a cutoff frequency of 32 kHz. The test is conducted in
16-bit mode.

4-485

4.3.8

DAC Channel, DVoo
PARAMETER

= 5 V or 3 V
TEST CONDITIONS

MIN

Dynamic range

MAX

UNIT

85

Interchannel isolation
EG

TYP

108

Gain error, 0 dB

Vo = 0 dB at 1020 Hz

Idle channel
broad-band noise

See Note 8

Idle channel
narrow-band noise

0-4 kHz,

dB

±0.5
70

150

iJ.Vrms

2

20

iJ.Vrms

See Note 8

Channel delay

s

18/fs

VOO

Output offset voltage
at OUT (differential)

DIN = zero code

Vo

Analog output
voltage,
OUTP-OUTM

With internal
reference and
full-scale digital
input,
See Note 9

2

mV

9.6 x RLOAD
Differential

VPP

R(IGAIN)

NOTES:

8. The conversion rate is 8 kHz; the out-of-band measurement is made from 4400 Hz to 3 MHz.
9. The digital input to the DAG channel at DIN is in 2's complement format. The TLC320AD56C is a current
DAC and requires a load resistor for current-to-voltage conversion. This output voltage is across the load
resistor (see Figures 5-1 and 5-2).

4.3.9

Power Supplies, No Load (Unless Otherwise Noted)
PARAMETER

IDD (analog) . Power supply current, ADC

IDD (digltaI1)

IDD (digitaI2)
PD

4-486

Power supply current, digital
Power supply current, digital,
DVDD = 3.3 V
Power dissipation

TEST CONDITIONS
Operating
Power down

MIN

TYP

MAX

18

25

0.5

UNIT
rnA
rnA

Operating

2

Power down

3

iJ.A

Operating

1

rnA

Power down

5

3

rnA

iJ.A

Operating

100

150

Power down

2.5

5

mW

4.3.10

Power-Supply Rejection (see Note 10)
PARAMETER

TEST CONDITIONS

MIN

TYPt

MAX

UNIT

VDD1

Supply-voltage rejection ratio, ADC channel,
DVDD

fi

= 0 to 30 kHz

55

dB

VDD2

Supply-voltage rejection ratio, DAC channel,
DVDD

fi

= 0 to 30 kHz

55

dB

VDD3

Supply-voltage rejection ratio, ADC channel,
AVDD

fi

= 0 to 30 kHz

50

dB

Single ended,
fi = 0 to 30 kHz

50

dB

VDD4

Supply-voltage rejection ratio, DAC channel,
AVDD

Differential,
fi = 0 to 30 kHz

55

dB

t All typical values are at 25°C.
NOTE 10: Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200-mV
peak-to-peak Signal applied to the appropriate supply.

4.3.11

Timing Requirements (see Figure 3-1)
PARAMETER

td1

Delay time, SCLKi to FSJ.-

!d2

Delay time, SCLKi to DOUT valid

tsu

DIN setup time before SCLK low

th

DIN hold time after SCLK high

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0
20
20
CL

=20 pF

20

ten

Enable time, FSJ.- to DOUT valid

tdis

Disable time, FSi to DOUT Hi-Z

!d3

Delay time, MCLKJ.- to SCLKi

twH

Pulse duratio'n, MCLK high

32

twL

Pulse duration, MCLK low

20

25

ns

20
/

50

4-487

0

\

-20

\

-40
III

1:J

-60

I

c
0

-80

c

-100

i:::s

~

,

l) \f\{lf 1.f\f\Ji\ At ~I\
1,
il

'

'1

' ~

-120
-140
-160

o

0.8

1.6

2.4

4

3.2

4.8

5.6

6.4

7.2

8

3.6

4

fl - Input Frequency - kHz
Figure 4-1. ADC Decimation Filter Response

0.6
0.4
0.2
III

1:J
I

c

0

0

-0.2

c

-0.4

i:::s

~

"J

V"\

~

I

"-V 1'-1

,

i'"\ /\. r \ I 1\
\ ../ 'J V
,

-0.6
-0.8
-1

o

0.4

0.8

1.2

1.6

2

2.4

2.8

fl - Input Frequency - kHz
Figure 4-2. ADC Decimation Passband Ripple

4-488

3.2

0

"\

-20

\

-40

m
"0

-60

I
C

.2
'ii
:l

-80

!

-100

c

~~

'II

I

C(

-120

,

[\/"1 ~(\
V'I f\J, W
\
I'

-140
-160

o

0.8

1.6

2.4

3.2

4

4.8

5.6

6.4

7.2

8

3.6

4

fl - Input Frequency - kHz
Figure 4-3. DAC Interpolation Filter Response

0.3
0.2
0.1

m
"0

0

I

c

0
;:

-0.1

\ V\ (' Jr\ !\ ( ~ l'
V \ j \/ \ / 'J V
~

til

:l

c

!C(

-0.2
-0.3
-0.4
-0.5

o

0.4

0.8

1.2

1.6

2

2.4

2.8

3.2

fl - Input Frequency - kHz
Figure 4-4. DAC Interpolation Passband Ripple

4-489

4-490

5 Application Information

TLC320AD56C

+V

10kQ
.>-<.---l1-------"V\f'..---.-----4.-----1INP (+)

VI(_)
VI(+)

300 pF

20kQ

-v

'-++-----IINMH

-=- AGND

10kQ
2.5 V

38.4 kQ

.....- - - - - 1

T
0.39 nF

VCOM(ADC)

0.11lF

-=- AGND

t--+-'VV\r-e_e_-'\I\I\r--.-----I f---e--+---I

OUTM (-)

10kQ
OUTP(+)

-v

-=-

-

AGND

AGND

VCOM(DAC)

r

0.1 IlF

IGAIN

AGND -=27kQ
(1 %)
AGND

Figure 5-1. Application Schematic For Single-Ended Input/Output

4-491

TLC320AD56C
+V
20k!l

VI1(_)

INP(+)

VI1(GND)

-v

20k!l

AGND -::-

2.5 V
0.1 JlF
+V

T_

VCOM(ADC)
20k!l
150 pF

AGND

VI2(+)

INM(-')

VI2(GND)

20k!l
-V

AGND

-::-

38.4kn
0.39 nF

1--_._.A..N\r--4N--'VV'v-e-H__e_--_.------I OUTM (-)

10 kn
...---.-IVCOM(DAC)

0.1 JlF
0.39 nF

T

AGND

10 k!l

I--____..J\,/\Ar-. . .I--J\,f\i'\r-.......--H-----.-----~t_t

OUTP (+)

VO(-)
IGAIN

AGND

27kn
(1%)
AGND

Figure 5-2. Application Schematic For Differential Input/Output

4-492

Appendix A
Register Set
Bits 012 through 08 in a secondary serial communication comprise the address of the register that is written
with the data carried in 07 through DO. 013 determines a read or write cycle to the addressed register. When
low, a write cycle is selected.
Table A-1 shows the register map.

Table A-1. Data and Control Registers
BITS

REGISTER NO.

REGISTER NAME

015

014

D13

012

011

010

09

08

0

0

0

0

0

0

0

0

0

No operation

1

0

0

0

0

0

0

0

1

Control 1

2

0

0

0

0

0

0

1

0

Control 2

Table A-2. Control 1 Register
BITS

07

06

05

04

03

02

-

-

-

-

-

-

-

1

-

-

0

-

-

0

-

-

-

1

-

1

-

-

0

-

-

-

-

0

-

-

-

-

-

-

-

-

-

NOTES:

-

OESCRIPTION

01

00

-

-

Software reset

-

Software power down (analog and filters)

-

Select AUXP and AUXM

-

Software reset not asserted
Software power down (not asserted)

-

Select INP and INM

-

Select INP and INM for monitor

-

Monitor amp gain

-

Monitor amp gain

-

1

-

-

-

1

1

-

1

0

-

0

1

-

-

= -18 dB (see Note B)
= -8 dB (see Note B)
Monitor amp gain = 0 dB (see Note B)

-

0

0

-

-

Monitor amp mute

-

Digitalloopback asserted

0

-

Digital loopback not asserted

-

-

-

-

-

-

1

-

1

16-bit mode (hardware secondary requests)

0

Not 16-bit mode (software secondary requests)

-

-

-

-

Select AUXP and AUXM for monitor

A. Default value: 00000000
B. These gains are for a single-ended input. The gain is 6 dB lower with a differential input.

The software reset is a one-shot operation and this bit is cleared to 0 after reset. Itis not necessary to write
a zero to end the master reset operation. Writing Os to the reserved bits is suggested.

4-493

Table A-3. Control 2 Register
BITS

07

06

05

-

-

-

-

-

-

-

X

X

NOTES:

02

X

-

-

-

Decimator FIR overflow flag (valid only during read cycle)

-

-

-

X

-

FLAG 1 output value (valid only during read cycle)

-

-

X

-

-

-

-

-

0

-

FLAG 0 output value (valid only during read cycle)

-

-

Phone mode disabled

-

X

X

Reserved

A. Default value: 00000000
B. X = do not care

Writing Os to the reserved bits is suggested.

4-494

DESCRIPTION

03

1

01

DO

04

Phone mode enabled

TLC320AD75C
Data Manual
20-8it Sigma-Delta Stereo ADA Circuit

SLAS144
February 1997

•
TEXAS
INSTRUMENTS

Printed on Recycled Paper

IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.

Copyright © 1997, Texas Instruments Incorporated

Contents
Section

Title

Page

1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.1 Features ............................................................
1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.3 System Block Diagram ...............................................
1.4 Terminal Assignments ................................................
1.5 Ordering Information .................................................
1.6 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

4-501
4-501
4-502
4-503
4-504
4-504
4-505

2

Detailed Description .....................................................
2.1 Power-Down and Reset Functions .....................................
2.1 .1
ADC Power Down ...........................................
2.1 .2
Reset Function for ADC ......................................
2.1.3
Resetl Initialization for DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.2 Differential Input to the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.3 Sigma-Delta Modulator for the ADC ....................................
2.4 Decimation Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.5 High-Pass Filter .................................... ;................
2.6 Master Clock ........................................................
2.6.1
Master-Clock Circuit for ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.6.2
Master-Clock Circuit for DAC ..................................
2.7 T~st ................................................................
2.8 Master Mode for ADC ................................................
2.9 Slave Mode for ADC .................................................
2.10 Digital-Audio-Data Interface for DAC ...................................
2.11 Serial-Control Interface for DAC .......................................
2.11.1
Serial-Control-Datalnput .....................................
2.12 DAC De-emphasis Filter ..............................................
2.13 Digital Filter Mute for DAC ............................................
2.14 DAC Digital AttenuationiSoft Mute .....................................
2.15 Sigma-Delta DAC Modulator ..........................................
2.16 DAC Interpolation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.17 DAC PWM Output (L2-L1 and R2-R1) ................................
2.18 DAC Control Register Set .............................................
2.19 Auto-Resynchronization Functionality .............................. : ....

4-507
4-507
4-507
4-507
4-508
4-509
4-509
4-509
4-509
4-510
4-510
4-510
4-511
4-511
4-511
4-511
4-513
4-513
4-513
4-513
4-514
4-515
4-515
4-515
4-516
4-517

3

Specifications ...........................................................
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range ...
3.2 Recommended Operating Conditions ...................................
3.3 Electrical Characteristics, AVoo = LVoo = V001 = V002 = PVOOL =
PVOOR = XVOO = 5 V, V35A = V350 = 3.3 V, TA = 25°C ...................
3.3.1
Digital Interface .............................................
3.3.2
Analog Interface ... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.3.3
ADC Performance, fs = 44.1 kHz, Bandwidth = 22.05 kHz ........
3.3.4
DAC Performance, 20-Bit Mode, fs = 44.1 kHz,
Bandwidth = 22.05 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

4-519
4-519
4-519
4-520
4-520
4-520
4-521
4-521
4-497

Contents (Continued)
Section

Title

Page

ADC Inputs ..................................................
ADC High-Pass Filter, fs = 44.1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ADG Decimation Filter, fs = 44.1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . ..
DAC Filter Characteristics, fs = 44.1 kHz .......................
Power Supply Current, fs = 44.1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . ..
ADC Switching Characteristics ............ _ . . . . . . . . . . . . . . .. . . . . . . . . . ..
DAC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

4-521
4-521
4-521
4-522
4-522
4-522
4-523

3.3.5
3.3.6
3.3.7
3.3.81
3.3.9
3.4
3.5
4

Parameter Measurement Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-525

5

Application Information .................................................. 4-527
5.1 Circuit And Layout Considerations ..................................... 4-533
5.2 PCB Footprint ....................................................... 4-533

4-498

List of Illustrations
Figure

Title

Page

Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure

2-1 ADC Start-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-2 DAC-Reset Timing Relationships ....................................
2-3 Differential Analog-Input Configuration .................... ; ..........
2-4 ADC Audio-Data Serial Timing - Master Mode .........................
2-5 ADC Audio-Data Serial Timing - Slave Mode ..........................
2-6 Audio Data Serial Timing - ADC and All DAC Modes ...................
2-7 Control-Data Input Timing ...........................................
2-8 De-emphasis Filter Characteristics ...................................
2-9 Digital Attenuation Characteristics ...................................
2-10 DAC Digital Attenuation Operation With Tapered Gain Response .......
2-11 Oversampling Noise Power With and Without Noise Shaping ...........
4-1 ADC Audio-Data Serial Timing ......................................
4-2 DAC Control-Data Serial Timing .....................................
5-1 TLC320AD75C Application Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-2 A-Weighted Function ...............................................
5-3 Land Pattern for PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

4-508
4-508
4-509
4-511
4-511
4-512
4-513
4-513
4-514
4-514
4-515
4-525
4-525
4-530
4-532
4-533

List of Tables
Table
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 5-1
Table 5-2

Title

Page

ADC Master Clock to Sample-Rate Comparison ........................ 4-510
DAC Master Clock to Sample-Rate Comparison ........................ 4-510
Attenuation Mode Register ........................ : .................. 4-516
System Mode Register .............................................. 4-517
TLC320AD75C Schematic Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-527
A-Weighted Data ................................................... ' 4-532

4-499

4-500

1 Introduction
The TLC320AD75C is a high-performance stereo 20-bit analog-to-digital and digital-to-analog converter
(ADA) using sigma-delta technology to provide four concurrent 20-bit resolution conversions from both
analog-to-digital (AID) and digital-to-analog (D/A) signal paths. Additional functions provided are digital
attenuation, digital de-emphasis filtering, soft mute, and on-chip timing and control. Control words from a
host controller or processor are used to implement these functions.
The TLC320AD75C is characterized for operation from O°C to 70°C.

Features

1.1
•

Single 5-V (Analog/Digital) Power Level and 3.3-V to 5-V Digital Interface Level

•

Sample Rates up to 48 kHz

•

20-Bit Resolution Conversions.

•

Signal-to-Noise Ratio (EIAJ) of 100 dB for the ADC

•

Total Harmonic Distortion + Noise of 0.0017% for the ADC

•

Signal-to-Noise Ratio (EIAJ) of 104 dB for the DAC

•

Total Harmonic Distortion + Noise of 0.0013% for the DAC

•

Internal Voltage Reference (Vref)

•

Serial Port Interface

•

Differential Architecture

•

DAC Provides PWM Output

•

Digital De-emphasis Filtering for 32-, 44.1-, and 48-kHz Sample Rates for the DAC

•

Digital Attenuation/Soft Mute Function for the DAC

•

Small 56-Pin DL Plastic Small-Outline Package·

4-501

1.2

Functional Block Diagram
3 Vor5 V
V35A

---...,
r------------------------'.
Stereo ADC
I

I

...---.....

INLP
INLM

I

ADOUT
SCLKA

I
REFO~
REFI

LRCKA

Serial
INRP
INRM

MCLKI

I
I
I
IL

_____________________________

I

~

r-----------------------------...,
Stereo DAC
, I

I
I

256CK
512CK

L1
L2

XOUT
XIN

Serial
Interface

LRCKD
SCLKD
R1

DDATA

R2

CDIN
SHIFT
LATCH

I
I
I
I

I

L_________________________ __ II

- L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~

~

V35D
3 Vor5 V

4-502

~

1.3

System Block Diagram

Right ---J
Audio Input ~

Single to
Differential

TLC320AD75C
REFI .--.---,
.--......--1...... INRP
REFO

T-=-

r-ADC-

INRM I Serial Port
I
LRCKA
SCLKA
I ADOUT
1--+--+-1 INLP L _ _ _
1--......--1......

T

Left ---J
Audio Input ~

Single to
Differential

1---++--.

ADC Data Out

M_S I---+-+---,

T

MCLKI

-=- VSS1

1--+--+-1 INRM
256CK

T

XIN 1---t--f--e------4I....--It- XVSS
XOUT 1---t--f--e------4I""--It- XVSS
512CK 1---+-+--.

r---Right
Analog
Audio Output ....--1 Low-Pass Filter

Left ......_-1
Analog
Audio Output
Low-Pass Filter

R1
R2
L1
L2

I
I
I
I
I
I
I

DAC
Serial Ports

L_

~~-

SCLK
LRCK

LRCKD
SCLKD
DDATA 1----4-- DAC Data In
CDIN .....- - - - - ,
SHIFT ......- - ,
DAC
LATCH
Control Data

4-503

1.4

Terminal Assignments
DLPACKAGE
(TOP VIEW)

INRP
INRM
REFI
AVOO
AVss
APD
NU
NU
TEST1
LRCKA
SCLKA
ADOUT

INLP
INLM
REFO
LVss
LVOO
AVSSB
NU
NU
VSS1B
M_S
TEST2
VSS1
VOO1
VOO1
VOO2
L1

V35A
VSS1B
MCLKI
DPD

PVOOL
L2

VSS2B
INIT
CDIN
SHIFT
LATCH
256CK

PVSSL
XVSS
XIN
XOUT
XVOO
PVSSR
R2
PVOOR
R1

V350
VSS2
512CK
SCLKD
DDATA
LRCKD

1.5

VOO2

Ordering Information
PACKAGE

4-504

TA

SMALL OUTLINE
(DL)

O°C to 70°C

TLC320A075COL

1.6

Terminal Functions
TERMINAL

NAME

NO.

1/0

DESCRIPTION

ADOUT

12

0

20-bit ADC data output. ADOUT provides the MSB first in 2's-complement data format
and is left justified within the 32-bit packet for each channel. The output level is 3.3 V
for V35A = 3.3 V (see Figure 2-6).

APD

6

I

Analog power-down mode. APD disables the ADC analog modulators. The ADC
single-bit modulator outputs become invalid, rendering the outputs of the digital filters
invalid. When APD is pulled high, normal operation of the device is resumed.

AVDD

4

Analog power supply voltage for ADC modulators

AVSS

5

Analog ground for ADC modulators

AVSSB

51

Analog substrate ground for ADC modulators

COIN

19

I

DDATA

27

I

Attenuation mode and system control mode input for DAC. COIN is a 24-bit stream
with a 16-bit data word followed by an 8-bit device address. This stream is configured
with the MSB first (see Section 2.15, Sigma-Delta DAC Modulatory.
DAC input data in 2's-complement data format. MSB/LSB first and 20-bit/16-bit input
formats are selectable by using the DAC control registers (see Section 2.15,

Sigma-Delta DAC Modulatory.

DPD

16

I

Digital power-down mode. The DPD shuts down the ADC digital decimation filters and
clock generators, and provides a digital reset. All digital outputs of the ADC function,
are brought to unasserted states. When DPD is pulled high, normal operation of the
device is resumed. When in slave mode operation, after the rising edge of DPD, the
ADC system is synchronized.

INIT

18

I

Initial DAC reset signal. The DAC device is activated on the rising edge of INIT. When
INIT is brought low, the DAC is reset when LRCKD is present.

INLM

55

I

Inverting input for the left channel analog modulator

INLP

56

I

Noninverting input for the left channel analog modulator

INRM

2

I

Inverting input for the right channel analog modulator

INRP

1

I

Noninverting input for the right channel analog modulator

21

I

Latch signal for the DAC control serial data. Attenuation/system-control data loads
into the internal registers when LATCH is brought low.

LATCH

LRCKA

10

110

Left/right clock for ADC. LRCKA signifies whether the serial data is associated with
the left channel ADC (when LRCKA is high) or the right channel ADC (when LRCKA
is lOw). LRCKA is normally connected to LRCKD. LRCKA is output when configured
in master mode.

LRCKD

28

I

Left/right clock for DAC. LRCKD signifies whether the serial data is associated with
the left channel DAC (when LRCKD is high) or the right channel DAC (when LRCKD
is low). LRCKD is normally connected to LRCKA.

LVDD

52

Digital power supply for analog modulators. LVDD is normally connected to AVDD
through a 50-0 resistor.

LVSS

53

Digital ground for analog modulators. LVSS is normally connected to AVSS through a
50-0 resistor.

L1

41

0

Left channel DAC PWM output 1

L2

39

0

Left channel DAC PWM output 2

MCLKI

15

I

Master clock input for ADC. MCLKI operates at 256 times the sample rate (i.e. 256
times LRCKA). MCLKI is normally connected to 256CK through a 50-0 resistor.

4-505

Terminal Functions (Continued)
TERMINAL
NAME

M_S
NU

I/O

DESCRIPTION

47

I

Master/slave selection. The ADC serial port is 60nfigured as master mode when M_S
is pulled high. M_S is connected to VSS1 for slave mode.

7,8,
49,50

-

Not used

NO.

40

PWM power supply for left channel DAC

PVDDR

31

PWM power supply for right channel DAC

PVSSL

38

PWM ground for left channel DAC

PVSSR

33

PWM ground for right channel DAC

REFI

3

I

Input reference voltage. REFI provides reference voltage for the ADC modulator
(normally connected to REFO).

REFO

54

0

Internal ADC reference voltage (normally connected to REFI).

PVDDL

R1

30

0

Right channel DAC PWM output 1

R2

32

0

Right channel DAC PWM output 2

SCLKA

11

I/O

Shift clock for the ADC. The shift clock clocks serial data out of the ADC, and operates
at 64 times the sample rate (i.e. 64 times LRCKA). SCLKA is normally connected to
SCLKD. SCLKA is output when configured in master mode.

SCLKD

26

I

Shift clock for the DAC. The shift clock clocks serial audio data into the DAC, and
operates at 64 times the sample rate (i.e. 64 times LRCKD). SCLKD is normally
connected to SCLKA.

SHIFT

20

I

Shift data. SHIFT clocks the control data (CDIN) into the internal control registers for
the DAC.

TEST1

9

I

Factory test terminal1. TEST1 should be connected to VSS1 for normal operation.

TEST2

46

I

Factory test terminal2. TEST2 should be connected to VSS1 for normal operation.

XIN

36

I

Oscillator input terminal for 512 times the DAC sample rate. XIN derives all of the key
logiC signals of the DAC device. (XIN can also be driven by an external oscillator.)

XOUT

35

0

Oscillator output terminal for 512 times the DAC sample rate

VDD1

43,44\

Digital power supply for ADC

VDD2

29,42

Digital power supply voltage for DAC

VSS1

45

VSS1B

Digital ground for ADC digital flters

14,48

Digital substrate ground for ADC

VSS2

24

Digital ground for the DAC

VSS2B

17 .

Digital sustrate ground for DAC

V35A

13

Digital power supply for ADC interface logic. V35A is connected to 3 V or 5 V.

V35D

23

Digitalpower supply for DAC interface logic. V35D is connected to 3 V or 5 V.

XVDD

34

Oscillator power-supply voltage for DAC

XVSS

37

Oscillator circuit ground for DAC

256CK

22

0

256 times sample rate clock output. 256CK is normally connected to MCLKI through
a 50-Q resistor. 256CK is the XIN frequency divided by two.

512CK

25

0

512 times sample rate clock output (output level is 3.3 V for V35D '" 3.3 V). 512CK is
a buffered version of XIN (master clock input).

4-506

2 Detailed Description
The sigma-delta ADC converter consists of an oversampling analog modulator and digital decimation filter.
The sigma..delta DAC incorporates an interpolation finite impulse-response (FIR) filter and oversampled
modulator. The pulse-width-modulation (PWM) digital output feeds an external low-pass filter to recover the
analog audio signal.
Two control registers configure the DAC. The attenuation register controls the attenuation range,
de-emphasis enable, and mute selection. The system register controls the data format and de-emphasis
filter-sample rate.

2.1
2.1.1

Power-Down and Reset Functions
ADC Power Down

The power-down state is comprised of a separate digital and analog power down for the ADC. The power
consumption of each is detailed in the electrical characteristics section.
The digital power-down mode shuts down the digital filters and clock generators. When the digital
power-down terminal is pulled high, normal operation of the device is initiated. In slave mode, the conversion
process must synchronize to an input on LRCKA as well as SCLKA. Therefore, the conversion process is
not initiated until the first rising edges of both SCLKA and LRCKA are detected after DPD is pulled high. This
synchronizes the conversion cycle; all conversions are performed at a fixed LRCKA rate after the initial
synchronization. After DPD is brought high, the output of the digital filters remains invalid for 26 LRCKA
cycles which consists of group delays of the decimation and high-pass filter.
The analog power-down mode disables the analog modulators. The single-bit modulator outputs become
invalid, which renders the outputs of the digital filters invalid. When the APD terminal is brought high, the
modulators are brought back online; however, the settling time of the modulator stage is normally 100 ms.

2.1.2

Reset Function for ADC

The conversion process is not initiated until the first rising edges of both SCLKA and LRCKA are detected
after DPD is pulled high. This synchronizes the conversion cycle; all conversions are performed at a fixed
LRCKA rate after the initial synchronization.

4-507

During general operation of the ADC, APD is recommended to be pulled high (APD is not needed for a reset).
When using the analog power-down mode (APD low), the following timing procedure is required to start all
of the ADC since the analog modulator portion which includes the external portion needs to be settled after
APD is high.

APD

I

_---J

I

~~----~~f-DPD

LRCKA

ADOUT

> 100 msec

YI~-------------------------

-----'IfI
----~~rF\_----I.
I
~>26fS---:ff\

ff\

Figure 2-1. ADC Start-Up Timing

2.1.3

Reset/Initialization for DAC

When INIT is brought low, an internal reset signal becomes active approximately 120 cycles of the sampling
frequency (f8) after the falling edge of INIT. Under this condition, all internal circuits are initialized and the
PWM output is held at zero data (50% duty cycle). When INIT is brought high, the internal reset signal goes
inactive for a maximum of five LRCKD periods after the rising edge of INIT. At this point, internal clocks are
synchronous with LRCKD and the PWM output is valid (see Figure 2-2). LRCKD must be applied for proper
initialization.

14- 120 Cycles of fs --.I

j4--- 5 periods max ---.I

INIT----~~I____________rll____________~1
Internal _ _ _ _ _ _ _ _ _ _ _---,
Reset

I

III

L...-_ _ _ _ _ _ _ _ _ _ _ _ _ _.....J

LRCKO

Figure 2-2. DAC-Reset Timing Relationships

4-508

I
L-

2.2

Differential Input to the ADC

The input to the ADC is differential in order to provide common-mode noise rejection and increase the input
dynamic range. Figure 2-3 shows the analog input signals used in a differential configuration to achieve a
6.4 VI(PP) differential swing with a 3.2 VI(PP) swing per input line.
TLC320AD75C

4.1 V

INLP,INRP

2.5 V

0.9 V

4.1 V
2.5 V

0.9 V

-?\:-z-?\:-JL

INLM,INRM

Figure 2-3. Differential Analog-Input Configuration

2.3

Sigma-Delta Modulator for the ADC

The modulator is a fourth-order sigma-delta modulator with 64 times oversampling. The ADC provides
high-resolution, low-noise performance from a 1-bit converter using oversampling techniques.
\

2.4

Decimation Filter

The decimation filter after the sigma-delta ADC modulator reduces the digital data rate to the sampling rate
of LRCKA. This is accomplished by decimating with a ratio of 1:64.

2.5

High-Pass Filter

The high-pass filter removes dc from the input of the ADC. The output of this filter is a 2's-complement data
word of 20 bits serially clocked out. If the input value exceeds the full range of the converter, tt"le output of
the high-pass filter is held at the appropriate extreme until the input returns to the analog input range of the
TLC320AD75C.

4-509

2.6

2.6.1

Master Clock
Master-Clock Circuit for ADC

The master-clock circuit generates and distributes necessary clocks throughout the device. MCLKI is the
external master-clock input. The sample rate of the data paths is set as LRCKA = MCLKI/256. With a fixed
oversampling ratio of64x f5' the effect of changing MCLKI is shown in Table 2-1.

Table 2-1. ADC Master Clock to Sample-Rate Comparison
MCLKI
(MHz)

SCLKA
(MHz)

LRCKA
(kHz)

12.2880

3.0720

48

11.2896

2.8224

44.1

8.1920

2.0480

32

When the TLC320AD75C is in master mode (M_S is pulled high) SCLKA is derived from MCLKI in order
to provide clocking of the serial communications between the sigma-delta audio ADC and a digital signal
processor (DSP) or control logic. This is equivalent to a clock running at 64 x LRCKA.
When the TLC320AD75C is in slave mode (M_S is connected to VSS1), SCLKA is externally derived. For
SCLKA use of a clock running at 64 times LRCKA is recommended.

2.6.2

Master-Clock Circuit for DAC

The timing and control circuit generates and distributes necessary clocks throughout the TLC320AD75C.
XIN is the oscillator input terminal or can receive an external master-clock input. The sample rate of the data
paths is set as LRCKD = XIN/512. With a fixed oversampling ratio of 32x and each PWM output value
requiring 16 XIN cycles, the effect of changing XIN is shown in Table 2-2.

Table 2-2. DAC Master Clock to Sample-Rate Comparison
XIN
(MHz)

256CK
(MHz)

LRCKD
(kHz)

24.5760

12.2880

48.0

22.5792

11.2896

44.1

16.3840

8.1920

32.0

The DAC can be operated at any conversion rate between 48 kHz and 32 kHz by choosing the appropriate
master-clock frequency. Some of the functions of the converter, such as the deemphasis filter, operate only
at the frequencies shown in Table 2-2.

4-510

2.7

Test

TEST1 and TEST2 are reserved for factory test and are tied to digital ground (VSS1).

2.8

Master Mode for ADC

Configured as the master device (M_S is connected to VDD1), the TLC320AD75C generates LRCKA and
SCLKA from MCLKI. These signals are provided for synchronizing the serial port of a digital signal processor
(DSP) or other control devices.
LRCKA is generated internally from MCLKI. The frequency of LRCKA is fixed at the sampling frequency,
fs (MCLKI/256). During the high period of LRCKA, the left channel data is serially shifted to the output; during
the low period, the right channel data is shifted to the output (ADOUT). The conversion cycle is synchronized
with the rising edge of LRCKA.
Figure 2-4 (master mode) shows 20-bit data, MSB first, ADOUT data shifted out of the TLC320AD75 during
the first 20 SCLKA periods of the 32 SCLKA periods for both left and right channel data.
20-BIT MASTER MODE

Figure 2-4. ADC Audio-Data Serial Timing - Master Mode

2.9

Slave Mode for ADC

Configured as a slave device (M_S is connected to VSS1), the TLC320AD75C receives LRCKA and SCLKA
as inputs. The conversion cycle is synchronized to the rising edge of LRCKA, and the data is synchronized
to the falling edge of SCLKA. SCLKA must meet the setup requirements specified in the recommended
operating conditions section. Synchronization of the slave mode is accomplished with the rising edge of
DPD.
The slave mode is shown in Figure 2-5. SCLKA and LRCKA are externally generated and sourced. The
first rising edges of SCLKA and LRCKA after the rising edge of DPD initiate the conversion cycle (see
Section 2.8, Master Mode for ADC for signal functions).
Figure 2-5 (slave mode) shows 20-bit data, MSB first, and ADOUT data shifted out of the TLC320AD75
during the first 20 SCLKA periods of the 32 SCLKA periods for both left and right channel data.
20-BIT SLAVE MODE

input
SCLKA
ADOUT
LRCKA

f1\.-I1\../1\..

~
"I~SB
LSBII~SB~SB
output
I
1tL 18 . . 1
Jl
I I dlL 18 . 1 Jl _+--+____~

!

Input

I

I
I

I tf:
1.4 3,~E,E,~E,~,~E,J6~4~SC~LKS .'
I I
L ft
II
I
'\ Right
I 'Ie, I I I I I I I I I 'il I

I
I

I
•}
I I

Figure 2-5. ADC Audio-Data Serial Timing - Slave Mode

2.10 Digital-Audio Data Interface for DAC
The conversion cycle is synchronized to th€l rising edge of LRCKD, and the data must meet the setup
requirements specified in the timing requirements table. The input data is 16 or 20 bits with the MSB or LSB
first as selected in the system register. The recommended SCLKD frequency is 64 x fs. Figure 2-6
illustrates the input timing.
.
4-511

~

I\)

LRCKA and LRCKD

~

LEFT

RIGHT

I

SCLKA and SCLKD

ADOUT
MSB

LSB

DDOUT
(20-Bil, MSB Firsl)
LSB

MSB

LSB

DDOUT
(16-Bil, MSB Firsl)

I
MSB

LSB

I
LSB

MSB

DDOUT
(20-Bit, LSB Firsl)

LSB

I
MSB

DDOUT
(16-Bit, LSB Firsl)

Figure 2-6. Audio-Data Serial Timing - ADC and All DAC Modes

I

LSB

MSB

2.11 Serial-Controllntertace for DAC
The TLC320A075C uses the most-significant-bit-first format. Therefore, for a 16-bit data word, 016 is the
most significant bit (MSB) and 01 is the least significant bit (LSB).

2.11.1

Serial-Control-Data Input

The 16-bit control-data input implements the device-control functions. The TLC320A075C has two registers
for this data: the system register and the attenuation register. The system register contains most of the
system configuration information, and the attenuation register controls the audio output level and
deemphasis. Figure 2-7 illustrates the input timing for COIN, SHIFT, and LATCH. The data loads internally
during the low level of LATCH. The shift clock must be high or low for the LATCH setup time before LATCH
goes low.
As shown in Figure 2-7, COIN is a 24-bit data stream consisting of 16 bits of control data 016 through 01
followed by 8 bits of device, address A8 through A 1. When the TLC320AD75C receives address >E7h, the
control data is latched into the device by LATCH. For all other addresses, the data is ignored.

I"

~I"

Control Data

Control-Device Address ----.:

Figure 2-7. Control-Data Input Timing

2.12 DAC De-emphasis Filter
Three sets of de-emphasis-filter coefficients support the three sampling rates (f5): 32 kHz, 44.1 kHz, and
48 kHz. Internal system-register values select the filter coefficients. The internal register values enable or
disable the filter_ Figure 2-8 illustrates the de-emphasis filtering characteristics.
Many audio sources have been recorded with pre-emphasis characteristics that are the inverse of the
characteristics shown in Figure 2-8. This device provides reconstruction of the original frequency response.

10
III

"I

~

o

a..

Ol-----_~

:!

De-emphasis

-10
10.6

3.18
(50/is)

(15/is)
f - Frequency - kHz

Figure 2-8. De-emphasis Filter Characteristics

2.13 Digital Filter Mute for DAC
When the mute bit in the attenuation register is set to 1, the OAC digital filter mute is active. The output of
the digital filter is 0 + dc offset. Operation of the digital filter is normal during mute.

4-513

2.14 DAC Digital Attenuation/Soft Mute
A value selected in the internal attenuatio!1 register determines the attenuation of the digital-audio data input.
The attenuation value is 12 bits long with a valid range of hex values from 400h to OOOh. A data value of 001 h
corresponds t.o an attenuation value of -60 dB and a data value of 400h corresp,onds to 0 dB. The
attenuation function is nonlinear. Figure 2-9 illustrates the attenuation function. in dB. The default
attenuation value is 400h (refer to the attenuator mode register for more detailed description).

Attenuation

=

20 log (attenuation data)
1024

- r--. ,

0

............

-10

lEI
'C

..... ........

-20

~

I

c

0
;:
1\1

-30

::J
C

\

s

--VVV---JIf!-±1If-+--JVI.IV---{ ~

L2

AOUTL

15V
R46

..----~----.-~--~---+

PVSSR------------------4---+-. .---*~----~~-4--

R45

R2--+-------~~~¥r~

AOUTR
<:;43

R1

R36

C37

Figure 5-1. TLC320AD75C Application Schematic (Continued)

4-531

Table 5-2. A-Weighted Data
FREQUENCY

A WEIGHTING (dB)

FREQUENCY

A WEIGHTING (dB)

25

-44.6±2

800

-0.1 ±1

31.5

-39.2±2

1000

40

-34.5±2

1250

O±O
0.6±1

50

-30.2±2

1600

1.0 ±1

63

-26.1 ±2

2000

1.2 ±1

80
100

-22.3±2

2500

1.2 ±1

-19.1 ±1

3150

1.2 ±1

125

-16.1 ±1

4000

1.0 ±1

160

-13.2 ±1

5000

0.5±1

200

-10.8 ±1

6300

-0.1 ±1

250

-8.6 ±1

8000

-1.1 ±1

315

-6.5 ±1

10000

-2.4 ±1

400

-4.8 ±1

12500

-4.2 ±2

500

-3.2±1

16000

-6.5 ±2

630

-1.9±1

10

0
.100'

IX!

'tJ

/

-10

V

I

c
0

i

~

II

-20

~

c

!

-30

-40

I

V

/

-50
20

100

1k

10 k 20 k

f - Signal Frequency - Hz

Figure 5-2. A-Weighted Function

4-532

5.1

Circuit And Layout Considerations

The designer should follow these guidelines for the best device performance.

5.2

•

Separate digital and analog ground planes should be used. All digital device functions should be
over the digital ground plane, and all analog device functions should be over the analog ground
plane. The ground planes should be connected at only one point to the direct power supply, and
this is usually at the connector edge of the board.

•

A single crystal-controlled clock should synchronously generate all digital signals.

•

All power supply lines should include a O.1-IlF and a 1-IlF capacitor. When clock noise is
excessive, a toroidal inductance of 10 IlH should be placed in series with XVoo before connecting
to DVoo.

•

The digital input control signals should be buffered when they are generated off of the card.

•

Clock jitter should be minimized, and precautions taken to prevent clock overshoot. This
minimizes any high-frequency coupling to the analog output.

PCB Footprint

Figure 5-3 shows the printed-circuit-board (PCB) land pattern for the TLC320AD75C small-outline
package.

t W11 r-t

L1

fL

•t

P

DDD

f

L2

DD r
DD 1
S

L2

i
t
•
fL

f

DDD

L1
p

S

W

L

L1

L2

1.27

9.53

0.76

1.55

0.64

0.91

NOTE A: All linear dimensions are in millimeters.

Figure 5-3. Land Pattern for PCB Layout

4-533

4-534

TLC320ADBOC
Data Manual
Audio Processor Subsystem

SLAS141
November 1997

•
TEXAS
INSTRUMENTS

Printed on Recycled Paper

IMPORTANT NOTICE

Texas Instruments (TI) reserves the right to make changes to its products or to
discontinue any semiconductor product or service without notice, and advises its
customers to obtain the latest version of relevant information to verify, before placing
orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the
specifications applicable at the time of sale in accordance with TI's standard warranty.
Testing and other quality control techniques are utilized to the extent TI deems necessary
to support this warranty. Specific testing of all parameters of each device is not
necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT
APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the
customer. Use of TI products in such applications requires the written approval of an
appropriate TI officer. Questions concerning potential risk applications should be directed
to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design
and operating safeguards should be provided by the customer to minimize inherent or
procedural hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI
warrant or represent that any license,. either express or implied, is granted under any
patent right, copyright, mask work right, or other intellectual property right of TI covering
or relating to any combination, machine, or process in which such semiconductor
products or services might be or are used.

Copyright © 1997, Texas Instruments Incorporated

Contents
Section

Title

Page

1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.1 Features ..................................... '. . . . . . . . . . . . . . . . . . . . . ..
1.2 Applications.........................................................
1.3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.4 Terminal Assignments ................................................
1.5 Ordering Information .................................................
1.6 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . ..

4-541
4-541
4-542
4-543
4-544
4-544
4-545

2

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Audio Input Ports ....................... ; .... : .......................
2.1.1 Serial PCM Data Ports .........................................
2.1.2 Analog Audio Input Ports .......................................
2.1.3 Audio Source Selection Procedure ...............................
2.1.4 Audio Input Port Mute and Capacitor Precharge Mode ..............
2.2 Analog Audio Outputs ................................................
2.2.1 Variable Stereo Audio Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.2.2 External Stereo Audio Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.2.3 Wideband Multiplexer Output ................... , ..... , ... : ......
2.3 Volume/Balance/Mute Control .........................................
2.3.1 Volume Control ................................................
2.4 Sigma-Delta DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.4.1 Interpolator/Modulator..........................................
2.4.2 Continuous Time and Switched Capacitor Filters . . . . . . . . . . . . . . . . . ..
2.5 Serial Control Port ...................................................
2.5.1 Serial Control Port Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.5.2 Serial Control Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.5.3 Power-Down/Reset ............................................
2.6 Software Interface ...................................................

4-547
4-548
4-548
4-551
4-552
4-553
4-553
4-553
4-554
4-554
4-554
4-554
4-555
4-555
4-555
4-555
4-555
4-556
4-557
4-557

Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.1 Absolute maximum ratings over operating free-air temperature range . . . . . ..
3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.2.1 Static Digital Specifications, TA = 25°C, AVoo = DVoo = 5 V + 5% ...
3.2.2 Power Supplies, TA = 25°C, AVoo = DVoo = 5 V + 5% .............

4-559
4-559
4-559
4-559
4-560

2.1

3

4-537

Contents (Continued)
Section
3.3

3.4

4

Title

Page

Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.3.1 Analog Audio Channel Performance, TA = 25°C,
AVoo = DVOO = 5 V + 5% ......................................
3.3.2 Volume Control and Output Drivers Performance, TA =25 oC,
AVoo = DVoo = 5 V + 5% ......................................
3.3.3 Monaural Decoder Performance, TA = 25°C,
AVoo = DVoo = 5 V + 5%, 1s = 32 kHz ...........................
3.3.4 Wideband Multiplexer Performance, TA = 25°C,
AVoo = DVOO = 5 V + 5% ......................................
3.3.5 PCM Audio Channel Performance, TA= 25°C,
AVoo = DVOO = 5 V + 5%, 1s = 48 kHz ...........................
3.3.6 DAC Interpolation Filter, TA = 25°C,
AVoo = DVoo = 5 V + 5%, 1s = 48 kHz ...........................
Timing Requirements, TA = 25°C, AVoo = DVoo = 5 V + 5%, 1s = 48 kHz ...
3.4.1 Serial PCM Data Port ....... _. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.4.2 Serial Control Interface, TA = 25°C, AVoo = DVoo = 5 V + 5%, ......

4-560
4-560
4-561
4-561
4-562
4-562
4-562
4-563
4-563
4-563

Application Information .................................................. 4-565
4.1 Schematic ......................................' . . . . . . . . . . . . . . . . . . .. 4-567

Appendix A: Register Set .............................•..................... 4-569

4-538

List of Illustrations
Figure
2-1
2-2

2-3
2-4
2-5

3-1
3-2
4-1
4-2

Title

Page

Philips 12S Protocol Serial PCM Data Format .............................
Left-Justified Serial PCM Data Format ...................................
Right-Justified Serial PCM Data Format ..................................
Left-Justified DSP Serial PCM Data Format (Inverted BCLK) ...............
Serial Interface Timing .................................................
Serial Port Timing .....................................................
SPI Serial Control Port Timing ..........................................
De-Emphasis 75 Ils Low-Pass Filter, at 2.12 kHz ..........................
Application Schematic .................................................

4-549
4-550
4-551
4-551
4-546
4-564
4-566
4-565
4-566

List of Tables
Table
2-1
2-2
2-3
4-1

Title

Page

Serial Port Signals ................ ,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Control Register OOh Allowable Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Master Clock (MCLK) Rates Supported For Various Sample Rates (LRCLK) ..
Digital Interface Capacitive Loading, TA =25°C,
AVoo = DVoo = 5 V + 5%, fs = 48 kHz ..................................

4-549
4-550
4-551
4-565

4-539

4-540

1 Introduction
The TLC320AD80 is an audio processing subsystem designed to meet the audio needs of a broad range
of set-top box applications. This device includes a high-performance stereo audio DAC, analog volume and
balance control, analog TV monaural decoder, de-emphasis filter, and an analog wide-band multiplexer.
The sigma-delta DAC performs data conversion with 85-dB performance. The architecture provides much
flexibility, giving the user the option to use all or a subset of the functional blocks.
There are two serial digital interfaces for digital audio data and four analog audio inputs. The analog output
of the device can be selected to be the output of the DAC, the output of the TV baseband filter, or
pass-through of one of the analog inputs.
The digital interfaces enable ease of use by providing compatibility with the industry standard 12S digital
audio port, and with the SPITM serial control interface. In addition, the digital audio interface supports
additional interface protocols.

1.1

Features
•

Highly Integrated Analog Audio Functions

•

Flexible Architecture Allows Variable Interconnects Between Functions

•

Sigma-Delta DAC With 16-Bit Resolution and 82-dB Performance Typical

•

Internal Monaural Decoder for TV Baseband Audio

•

Four Analog Audio Inputs: Two Stereo and Two Mono

•

Volume and Balance Control: 69 Step at 1 dB per Step With Mute

•

Selectable 50/15 ms De-Emphasis Analog Filter

•

Uncommitted Wide-Band Analog 2:1 Multiplexer

•

Multiplexed Analog Output can Select the Output of the DAC or Analog Data Pass-Through From
One of the Analog Audio Inputs

•

Two Flexible Digital Serial Data Ports (Philips 12S Protocol, Left-Justified, and Right-Justified
Formats)

•

SPI Bus-Compatible Serial Control Port

•

Sample Rates Supported in DAC: 8 kHz to 48 kHz

•

Digital Serial Ports Support 16-Bit or 18-Bit PCM Digital Audio Data Format

•

Analog Stereo Inputs can be Configured as Mono Inputs Through the Left Channel

•

Analog Output With 600-0 Load Drive and Short Circuit Protection

•

Internal Voltage Reference

•

nUCMOS Compatible

•

Single 5-V Power Supply, 64-Pin TQFP Package

SPITM is a trademark of Motorola Inc.

4-541

1.2

4-542

Applications
•

Direct Broadcast Satellite (DBS) Set-Top Boxes

•

Digital Cable or Telco Set-Top Boxes

•

High Definition Television (HDTV), Digital Audio Broadcast Receivers

•

Video Laser Disks, Video CD, and CD-I Players

1.3

Functional Block Diagram

SDATA
BCLK
LRCLK

9

I

Bandgap

rr---------------.~~
~~

Ilr-:::

46 BGFLTR
48 REFF

~ ~

8
10

Low-Pass
and
De-Emphasis
SC Filters

11

ASDATA ABCLK ~
ALRCLK _13

REF

EXTOUTL

EXTOUTR

L

26 EXTINL

R

27 EXTINR

MCLK1

L
MCLK2

AUDIO LEFT

TV BASEBAND P
TV BASEBAND M

Volume
Balance
Control

53
54

AUXAUDI02M
(This Channel May Feed EXT OUT UR For Mono Mode)

L

AUX AUDI01L

~

r--------------~

NTSCAUDIO L
AUXAUDI01R

MUXIN1
MUX IN2

R
MUXOUT

NTSCAUDIOR

CS
SCLK
CD IN
CDOUT

t..,.
CAl

Control

1.4

Terminal Assignments
PM PACKAGE
TOP VIEW)

::Eo...
00

ZZ
Ul(»>CJ(»()
ZZ()()enIOOOC:::ZI-I-0.6 fs

kHz

74

dB

Group delay

30/fs

sec

Group delay variation versus frequency

0.1/fs

sec

4-562

3.4

Timing Requirements, TA = 25°C, AVoo = DVoo = 5 V ± 5%, Is = 48 kHz
PARAMETER

TEST CONDITIONS

Input frequency,
MCLK1, MCLK2

MIN

TYP

MAX

UNITS

4.096

18.432

MHz

8

fs

Audio sample rate

48

kHz

tsu1

Setup time, PCM data

Relative to the rising edge of BCLK

60

ns

th1

Hold time, PCM data

Relative to the rising edge of BCLK

0

ns

tsu2

Setup time, LRCLK

Relative to the rising edge of BCLK

60

ns

th2

Hold time, LRCLK

Relative to the rising edge of BCLK

0

ns

3.4.1

Serial PCM Data Port (see Figures 3-1 and 3-2)
PARAMETER

MIN

TYP

Cycle time, BCLK

tcJBCLK)

MAX

UNITS

60

ns

tr(BCLK)

Rise time, BCLK

0

ns

tf(BCLK)

Fall time, BCLK

0

ns

tsu(LRCLK)

Setup time, LRCLKJ, before BCLKi

0

ns

th(LRCLK)

Hold time, LRCLKi after BCLKi

0

ns

tsu(SDATA)

Setup time, SDATA before BCLKi

0

ns

th(SDATA)

Hold time, SDATA after BCLKi

0

ns

1d(SDATA)

Delay time, SDATA valid after BCLKJ,

0

ns

twL(BCLK)

Pulse duration, BCLK low

60

ns

twH(BCLK)

Pulse duration, BCLK high

60

ns

twUMCLK)

Pulse duration, MCLK low

60

ns

twH(MCLK)

Pulse duration, MCLK high

60

ns

tr(MCLK)

Rise time, MCLK

0

ns

tflMCLK)

Fall time, MCLK

0

ns

3.4.2

Serial Control Interface, TA = 25°C, AVoo = OVoo = 5 V ± 5%, (see Figure 3-3)
DESCRIPTION

MIN

TYP

MAX

UNITS

3

MHz

fSCLK

Input frequency, SCLK

Ic(SCLK)

Cycle time, SCLK

333

ns

twL(SCLK)

Pulse width, SCLK low

100

ns

twH(SCLK)

Pulse width, SCLK high

100

ns

tsu(CS)

Setup time, CSJ, before SCLKJ,

150

ns

th(CS)

Hold time, CSi after SCLKi

150

ns

tsu(CDIN)

Setup timo, CD IN before SCLKi

50

ns

th(CDIN)

Hold time, CDIN after SCLKi

50

ns

Delay time, CDOUT after SCLKJ,

th(CDOUT)

Hold time, CDOUT after SCLKJ,

tr(SCLK)

Rise time, SCLK

100

ns

Fall time, SCLK

100

ns

tf(SCLK)

•

30

ns

td(CDOUT)

ns

5

4-563

twH(BCLK)~
I

twL(BCLK)

1

-1++i

I

BCLK
tsu(LRCLK)

I

I

I

I

I

I

i4-

---.I

I

tr(BCLK) ~

I
I

'

I

I

I

I

1 I

~f{BCLK)i

-J.----.i
I,
l

"L______

LRCLK

r,' td(SDATA),

+.____

-

1

I

th(LRCLK).

~__~((

r).,..I__

___x__x
)j

.

1e----II.!1f- th(SDATA)

~_.

SDATA

tc{BCLK)

I

tsu(SDATA)

I
I
-j4---+J

Figure 3-1. Serial Port Timing
14

twH(SCLK)

~

SCLK

CS

'\

I
I
I

I
I
I

td(CDOUT) ~
CDOUT

:I j
: I
I ~
I
I

twL(SCLK) I
~

I
I
I
14

1
CDIN

I
I

<

~

<

·14

C(

IJ

tf(SCLK)

.~
I

th(CS)~

I

!

I
I

~

)

th(CDIN)

I

I

I
I
----III

(

>

~ th(CDOUT)

IX

Figure 3-2. SPI Serial Control Port Timing

4-564

14-

tr(SCLK) ~

~

1

I
tsu(CDIN)
I

14

I

~,

tsu(CS)

·1

.11
II

X'

: 14

14

~

tc(SCLK)

I
I

>

4 Application Information
O.331l F 1.1 k.Q
TV IF Detector
Referenced to Ground

)~TV+

•

n

3nF

1.1kn
.
~
TV-

O.331lF

Figure 4-1. De-Emphasis 75 Ils Low-Pass Filter at 2.12 kHz
Table 4-1. Digital Interface Capacitive Loading, TA
AVDD = DVDD 5 V ± 5%, fs 48 kHz

=

TERMINAL
NAME

NO.

1/0

=

TYPICAL CAPACITIVE LOAD

44

I

BCLK

1

I

5 pF

LRCLK

2

I

5 pF

ASOATA'

3

I

5 pF

ABCLK

4

I

5 pF

ABCLK

40

I

5 pF

ALRCLK

5

I

5 pF

ALRCLK

50

I

5 pF

MCLK

41

I

5 pF

AMCLK

40

I

5 pF

COOUT

39

0

5 pF

COIN

38

I

5 pF

SOATA

=25°C,

5 pF

SCLK

37

I

5pF

CS

36

I

TBO

RESET

33

I

TBO

NOTE 1: ALRCLK and ABCLK are programmable as either inputs or outputs.

4-565

5V

5V

5V

+

+

~.1 ~~0~~.1 ~B10~F
GND

5V

CDOUT

!-=-

COIN
CS
RESET
SCLK
8
9
10
11
12
13
4
3

E>--------1
E>--------1
E>--------1
E>--------1
E>--------1
E>--------1
E>--------1

1 ~F

53

1 ~F

54

1 ~F

24

1 ~F

23

1 ~F

21

1 ~F

20

1 ~F

19

AUDIO RIGHT

SDATA

AUDIO LEFT

BCLK
LRCLK

AUDIO MONO

ASDATA
ABCLK
ALRCLK

EXTINR
EXTINL

MCLK 1

EXTOUTR

MCLK2

EXTOUTL

TV BASEBAND P
TV BASEBAND M
AUXAUDI02M

MUXIN1
MUXIN2
MUXOUT

38
35
39

+ (
+ (

(

25~F
25~F

1 ~F

D
D
D

27
26
30
29
41
42
43

(1
(1
+ (

~F
~F

25~F

CJ
CJ

D

AUXAUDI01R
AUXAUDI01L

REFF

NTSCAUDIO R

REF

NTSCAUDIO L

BGFLTR

48
47
46

Figure 4-2. Application Schematic
NOTE: If the TLC320AD80 is to be used in applications where high voltage may be present, as with TV monitors or'sets,
it is recommended to add either external diodes (1 N5347A) or transient suppressors (Motorola SA5. OA) from
any input and/or output terminals (that connect directly to external TV monitors or sets) to the circuit board ground~

4-566

4.1

Schematic

Ir----------------------------------------,
Set-Top Box Stereo Audio Processing Subsystem
I
r-----~t;;:OA~_;;_A~Standar;;;;_---- 1
~
REF
I
I
BGFLTR
I
I

.C>--i

J

I

;

•

SDATA~II

BCLK
LRCLK

ASDATAb3
ABCLK
ALRCLK

2

EXTOUTR

2

Format

Type
Select 1
L

MCLK1

R
256/384/512
AUDIO LEFT

2

TV BASEBAND M
AUX AUDI02M

I

I

• AUDIO RIGHT

.---------il

L

MUX IN1

r - - - - - - ; . MUX IN2

I -_ _ _ _ _ _ _ _ _~R)

~

SCLK
CDIN

CDOUT

~
~

SPI Bus
Controller

I ~....

I .....
!
1---+-1 ~ MUX OUT

I
I
I
ISUB
I

~

Control

Select 2

~--------~----T--r-I--T--r-I--T--r-I--T-J
AVoo1

AGND1

DVOOl

DGND1

AV002

AGND2 DV 002

DGND2 AVo03

AGND3

4-568

Appendix A
Register Set
Control of the TLC320AD80 is accomplished by means of the SPI serial interface and the control registers
described in this section.
There are five control registers used to control the various functions of the device: volume control,
multiplexer selections, serial interface, modes of operation, etc.
Table A-1. Serial PCM Data Format Control Register (Control Register OOh)

07

06

05

04

03

02

01

00

0

0

0

1

-

-

-

-

0

0

-

0

1

-

-

1

0
1

-

-

-

1

-

Reserved

-

0

0

0

1

-

Bit clock
(BCLK) rate

1

0

-

-

-

1

1

-

Reserved

-

-

-

-

x

Reserved

1

0

-

1

1

-

-

-

0

-

-

1

-

-

-

-

-

-

-

-

FUNCTION
Philips 12S protocol
Serial PCM
data format

Right justified
Left justified
Left justified DSP (inverted BCLK)

Serial PCM
data precision

16 bits
18 bits
256 x LRCLK (22.05 kHz:s; LRCLK :s; 48 kHz)

MCLK rate

384 x LRCLK (22.05 kHz:s; LRCLK :s; 48 kHz)
512 x LRCLK (8 kHz :s; LRCLK :s; 16 kHz)

64x LRCLK
48 x LRCLK (384x mode only)
32 x LRCLK (16-bit mode only)

The default value at reset is OOh.

4-569

Table A-2. Source Selection Control Register (Control Register 01 h)

07

06

05

04

03

02

01

DO

0

0

0

0

-

-

NTSC AUDIO (stereo)

0

0

0

1

-

NTSC AUDIO (mono)

0

0

1

0

-

0

0

1

1

0

1

0

0

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

x

x

-

-

-

-

-

0

-

-

-

-

-

-

1

-

-

-

-

-

-

-

-

0

-

-

-

-

-

-

-

1

-

-

-

-

-

0

-

-

-

-

-

0

-

-

-

1

-

-

-

-

-

0

1

0

1

0

1

1

0

0

1

1

1

-

-

-

-

-

AUX AUDI01 (stereo)

-

AUX AUDI01 (mono)

-

Reserved

-

Main audio
input port
select

-

1

The default value at reset is OOh.
NOTE 1: All serial PCM data formats except DSP.

4-570

FUNCTION

AUX AUDI02 (mono)
Reserved
TV aural baseband multiplex (mono)
Main serial PCM data (slave mode)
Reserved
Aux serial PCM data (slave mode)
Aux serial PCM data (master mode) (see Note 1)
Reserved

Master
clock input
port
select
Wideband
mux input
port
select

MCLK 1
MCLK2
MUX IN1
MUX IN2

Capacitor
precharge
mode

Disabled

Audio
input port
mute

Enabled

Enabled

Disabled

Table A-3. Control Register 02h
07

06

05

04

03

02

01

DO

0

0

-

-

-

-

-

0

1

1

0

1

1

-

-

-

0

-

1

-

-

0

-

-

-

-

-

-

-

-

-

x

-

-

-

0

-

1

-

-

-

x

-

-

-

-

-

1

-

-

0
1

FUNCTION

= 48 kHz)
50/15 ~s (LRCLK = 44.1 kHz)
50/15 ~ (LRCLK = 32 kHz)
50/15

De-emphasis
mode

~s

(LRCLK

None
Wideband mux
output mute
Volume/mute
gating enabler

Enabled
Disabled
Zero crossing or time out
Zero crossing only

Reserved
Reserved
Reset
Power down
with ext out
mute

Normal mode
Clear DAC digital filter
Device enabled
Device powered down

The default value at resel is OOh.

Table A-4. Left Volume Control Register (Control Register 03h)
07

06

05

04

03

02

01

DO

0

-

-

-

-

-

-

-

-

-

-

0

0

0

0

0

0

0

-90 dB (mute)

0

0

0

0

0

0

1

-62 dB

0

0

0

0

0

1

0

0

1

1

1

1

1

0

0

1

1

1

1

1

1

1

0

0

0

0

0

0

1 dB

1

0

0

0

1

0

1

6dB

1

0

0

0

1

1

x

Reserved

1

1

1

1

x

x

x

Reserved

1

-

-

FUNCTION
Volume control
mode

Ganged lefVright control on left
Independent left/right control

-61 dB
Left volume
control

-1 dB
OdB

The default value at reset is OOh.

4-571

Table A-5. Right Volume Control Register (Control Register 04h)

07

06

05

04

03

02

01

00

x

-

-

-

-

-

-

-

0

0

0

0

0

0

0

-90 dB (mute)

0

0

0

0

0

0

1

-62 dB

0

0

0

0

0

1

0

0

1

1

1

1

1

0

-

FUNCTION

Reserved

-61 dB
Right volume
control

-1 dB

0

1

1

1

1

1

1

1

O·

0

0

0

0

0

1 d~

1

0

0

0

1

0

1

6dB

-

1

0

0

0

1

1

x

Reserved

-

1

1

1

1

x

x

x

Reserved

-

The default value at reset is OOh.

4-572

OdB

5-1

Contents
Page
TL7726: ................................... ·......... .......................... 5-3
TLC04, MF4A-50, TLC14, MF4A-100: ..................................... 5-7
TLC29.32 : ................................................................... 5-19
TLC2933 : .................................................................. 5-41
TL32088: ..................................................................... 5-61

II
en
"C
CD

_.

(')

-

Q)

."

c::

...o_.
::l

(')

::l
In

5-2

TL7726C, TL77261, TL7726Q
HEX CLAMPING CIRCUITS
D OR P PACKAGE
(TOP VIEW}

•

Protects Against Latch-Up

•

25-mA Current Sink in Active State

•

Less Than 1-mW Dissipation in Standby
Condition

•

Ideal for Applications in Environments
Where Large Transient Spikes Occur

•

Stable Operation for All Values of
Capacitive Load

•

No Output Overshoot

G N 0 [ j S REF

CLAMP
CLAMP
CLAMP

2
3
4

7
6
5

CLAMP
CLAMP
CLAMP

description
The TL7726C, TL77261, and TL7726Q each consist of six identical clamping circuits that monitor an input
voltage with respect to a reference value, REF. For an input voltage (VI) in the range of GND to < REF, the
clamping circuits present a very high impedance to ground, drawing current of less than 10 11A. The clamping
circuits are active for VI < GND or VI > REF when they have a very low impedance and can sink up to 25 mA.
These characteristics make the TL7726C, TL77261, and TL7726Q ideal as protection devices for CMOS
semiconductor devices in environments where there are large positive or negative transients to protect
analog-to-digital converters in automotive or industrial systems. The use of clamping circuits provides a
safeguard against potential latch-up.
The TL7726C is characterized for operation over the temperature range of O°C to 70°C. The TL77261 is
characterized for operation over the temperature range of -40°C to 85°C. The TL7726Q is characterized for
operation over the temperature range of -40°C to 125°C.
AVAILABLE OPTIONS

A.

~

OPERATING
TEMPERATURE
RANGE

DEVICE

PACKAGE

O°C -70°C

TL7726CD

S-pin SO

O°C-70°C

TL7726CP

S-pin DIP

-40°C-S5°C

TL7726ID

S-pin SO

-40°C-S5°C

TL7726IP

S-pin DIP

-40°C - 125°C

TL7726QD

S-pin SO

-40°C-125°C

TL7726QP

S-pin DIP

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

~~~~;n!~~:1: 8~r!~i:81;;,::~::: ,c=::m'!:i

standard warranty. Production processing does not necessarily Include
testing of all parameters.

~TEXAS

Copyright © 1996, Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5--3

TL7726C, TL77261, TL7726Q
HEX CLAMPING CIRCUITS
SLAS078B - SEPTEMBER 1993 - REVISED OCTOBER 1996

absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Reference voltage, Vref ....... ,.............................................................. 6 V
Clamping current, 11K .....•.......•...........•...........•..•.••••..••...••••••••••...•. ±50 mA
Junction temperature, TJ ....... :.......................................................... 150°C
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA: TL7726C .................................... O°C to 70°C
TL7726 I ................................... -40°C to 85°C
TL7726Q ........... ; ..................... -40°C to 125°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE

=

=

=

PACKAGE

TA';; 25°C
POWER RATING

DERATING FACTOR
ABOVE TA';; 25°C

TA 70°C
POWER RATING

TA 85°C
POWER RATING

TA 125°C
POWER RATING

D

72BmW

5.B mW/oC

467mW

3BOmW

148mW

P

900mW

BmW/oC

540mW

420mW

100mW

recommended operating conditions
MIN

MAX

4.5

5.5

Reference vo~age, Vref

IVI~Vref

Input clamping current. 11K

25
-25

IVI,;;GND

UNIT
V
mA

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS

PARAMETER

MIN

VIK+

Positive clamp voltage

11=20 mA

Vref

VIK-

Negative clamp voltage

11=20 mA

-200

IZ

Reference current

Vre f=5V

TYPt

MAX
Vref+200

25

Vref - 50 mV,;; VI ,;; Vref
II

GND ,;;VI ,;;50 mV

Input current

50 mV,;; VI';; Vref- 50 mV

mV

0

mV

60
10

I1A
I1A
I1A

1

IIA

MAX

UNIT

-10
-1

UNIT

t All typical values are at TA = 25°C.

switching characteristics specified at TA

=25°C

PARAMETER
ts

Settling time

TEST CONDITIONS
VI(system) = ±13 V,
Measured at 10% to 90%,

RI =6000, . tt < 1 lIS,
See Figure 1

~TEXAS

5-4

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

MIN

30

liS

TL7726C, TL77261, TL7726Q
HEX CLAMPING CIRCUITS
SLAS078B - SEPTEMBER 1993 - REVISED OCTOBER 1996

PARAMETER MEASUREMENT INFORMATION
VCC=SV

I
REF
JL.-""6ooN'.r
g- - - CLAMP TL7726
VI(system)
GND

1
TEST CIRCUIT

--------

I

---90%

VI(system)
-13V-

I
I
-r--------T
II
I I

~~tt

9S%

I
I
I

I

I
I
I
I
i+ltS

I
I

_L ________ L

--10%

~~tt

INPUT WAVEFORM

~

VIK_
I

I~ts

CLAMP WAVEFORM

Figure 1. Switching Characteristics
-

II

100mA

-

2SmA

f-

10 mA

i-

i

e-- 1 mA

i-

e-- 100!lA

i-

'- 10 j.lA
'- 1 j.lA

I

VIK-

Vref-SO mV

:r
~

-1 j.lA

1

SOmV ..!

r

VIK+

-

-10j.lA -

-

-100!lA -

-

-1 mA-

-

-10mA -

-

-2SmA

-100 mA _
GND

Vref

Figure 2. Tolerance Band for Clamping Circuit

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-5

TL7726C, TL77261, TL7726Q
HEX CLAMPING CIRCUITS
SLAS078B - SEPTEMBER 1993 - REVISED OCTOBER 1996

APPLICATION INFORMATION
VCC=5V

1
T
10kn

II(system)

VI

VI(system)
(Input signal)

-----

"tf
1/6
TL7726

f

Device to Be
Protected, e.g.,
AID Converter,
Microprocessor, etc.

IZ

400Vref

1

Example: II II » II(system), i.e., VI(system) > VrEiI + 200 mV
where:
II(system) = Input current to the device being protected
VI(system) = Input voltage to the device being protected
then the maximum input voltage
VI(system)max = Vrel + Ilmax(1 Okll)
= 5 V + 25 mA(10kll)
=5V+250V
=255 V

Figure 3. Typical Application

~TEXAS

INSTRUMENTS
5--6

POST OFFICE BOX 655303 '. DALLAS, TEXAS 75265

TLC04/MF4A-50, TLC14/MF4A-1 00
BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
•

•
•

•
•
•
•
•

Da

o OR P PACKAGE

Low Clock-to-Cutoff-Frequency Ratio Error
TLC04/MF4A-50 ... ±0.8%
TLC14/MF4A-100 ... ±1%
Filter Cutoff Frequency Dependent Only on
External-Clock Frequency Stability
Minimum Filter Response Deviation Due to
External CQmponent Variations Over Time
and Temperature
Cutoff Frequency Range From 0.1 Hz
to 30 kHz, Vcc± ±2.5 V
5-V to 12-V Operation
Self Clocking or TTL-Compatible and
CMOS-Compatible Clock Inputs
Low Supply-Voltage Sensitivity ,
Designed to be Interchangeable With
National MF4-50 and MF4-100

(TOP VIEW)

ClKIN
ClKR

lS
VCC-

FllTERIN

2

7

VCC+

3

6

AGND

4

5

FilTER OUT

=

description
The TLC04/MF4A-50 and TLC14/MF4A-1 00 are monolithic Butterworth low-pass switched-capacitor filters,
Each is designed as a low-cost, easy-to~use device providing accurate fourth-order low-pass filter functions in
circuit design configurations.
Each filter features cutoff frequency stability that is dependent only on the external-clock frequency stability. The
cutoff frequency is clock tunable and has a clock-to-cutoff frequency ratio of 50:1 with less than ±O. 8% error
for the TLC04/MF4A-50 and a clock-to-cutoff frequency ratio of 100:1 with less than ±1 % error for the
TLC 14/MF4A-1 00. The input clock features self-clocking or TTL- or CMOS-compatible options in conjunction
with the level shift (LS) terminal.
The TLC04C/MF4A-50C and TLC14C/MF4A-100C are characterized for operation from O°C to 70°C. The
TLC041!MF4A-501 and TLC141!MF4A-1001 are characterized for operation from ~40°C to 85°C. The
TLC04M/MF4A-50M and TLC14M/MF4A-100M are characterized over the full military temperature range of
-55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
TA

CLOCK-TO-CUTOFF
FREQUENCY RATIO

O°C to 70°C

50:1
100:1

TLC04CD/MF4A-50CD
TLC14CD/MF4A-100CD

TLC04CP/MF4A-50CP
TLC14CP/MF4A-100CP

-40°C to 65°C

50:1
100:1

TLC04ID/MF4A-50ID
TLC14ID/MF4A-100lD

TLC04IP/MF4A-50IP
TLC14IP/MF4A-100IP

-55°C to 125°C

50:1
100:1

SMALL OUTLINE
(0)

PLASTICOIP
(P)

TLC04MP/MF4A-50MP
TLC14MP/MF4A-100MP

The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLC04CDR/MF4A-50CDR).

~~~~~~~1: :e~~:~~~~'~~~:~~~:1 ,e:~~~~m:

standard warranty. Production processtng does not necessarily Include

testing of all parameters.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

Copyright © 1995, Texas Instruments Incorporated

5-7

TLC04/MF4A-50, TLC14/MF4A-1 00
BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
SLAS021A - NOVEMBER 1986 - REVISED MARCH 1995

functional block diagram
lS
ClKIN
ClKR

-=--~-------'

FilTER IN

Butterworth
Fourth-Order 1-----"-5 FilTER OUT
AGND ....:<...----------1 low-Pass Filter
6

Terminal Functions
TERMINAL
NAME

NO.

DESCRIPTION

1/0

AGND

6

I

Analog ground. The noninverting input to the operational amplifiers of the Butterworth fourth-order low-pass filter.

ClKIN

1

I

Clock in. ClKIN is the clock input termimil for CMOS-compatible clock or self-clocking options. For either option,
lS is at VCC-. For self-clocking, a resistor is connected between ClKIN and ClKR and a capacitor is connected
from ClKIN to ground.

ClKR

2

I

Clock R. ClKR is the clock input for a TIL-compatible clock. For a TIL clock, lS is connected to midsupply and
ClKIN can be left open, but it is recommended that it be connected to either VCC+ or VCC-.

FilTER IN

8

I

Filter input

FilTER OUT

5

0

Butterworth fourth-order low-pass filter output

lS

3

I

VCC+

7

I

Positive supply voltage terminal

VCC-

4

I

Negative supply voltage terminal

level shift. lS accommodates the various input clocking options. For CMOS-compatible clocks or self-clocking,
lS is at VCC- and for TIL-compatible clocks, lS is at midsupply.

~TEXAS

INSTRUMENTS
5-8

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC04/MF4A-50, TLC14/MF4A-100
BUTTERWORTH FOURTH~ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
SLAS021 A - NOVEMBER 1986 - REVISED MARCH 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, VCC± (see Note 1) ..................................................... ± 7 V
Operating free-air temperature range, TA: TLC04C/MF4A-50C, TLC14C/MF4A-1 OOC ...... O°C to 70°C
TLC041/MF4A-501, TLC141/MF4A-100l ........ -40°C to 85°C
TLC04M/MF4A-50M, TLC14M/MF4A-1 OOM ... -55°C to 125°C
Storage temperature range, Tstg , .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the AGND terminal.

recommended operating conditions
TLC04/MF4A-50
MIN
Positive supply voltage, VCC+
Negative supply voltage, VCe-

UNIT

6

2.25

6

V

-6

-2.25

-6

V

0.8

V

V

2

2
0.8
VCC±=±2.5 V

5

1.5x106

5

1.5x106

VCC±= ±5V

5

2x10 6

5

2x10 6

0.1

40x10 3

0.05

20x103

0

70

0

70

Cutoff frequency, fco (see Note 3)
TLC04C/MF4A-50C, TLC14C/MF4A-100C

NOTES:

MAX

2.25

Low-level input voltage, VIL

Operating free-air temperature, TA

MIN

-2.25

High-level input voltage, VIH

Clock frequency, fclock (see Note 2)

TLC14/MF4A-100

MAX

TLC04I!MF4A-501, TLC141!MF4A-1001

-40

85

-40

85

TLC04M/MF4A-50M, TLC14M/MF4A-100M

-55

125

-55

125

..

Hz
Hz

°C

2. Above 250 kHz, the Input clock duty cycle should be 50% to allow the operational amplifiers the maximum time to settle while
processing analog samples.
3. The cutoff frequency is defined as the frequency where the response is 3.01 dB less than the dc gain of the filter.

electrical characteristics over recommended operating free-air temperature range, Vcc+ = 2.5 V,
VCC- = -2.5 V, fclock $ 250 kHz (unless otherwise noted)
filter section
TLC04/MF4A-50
PARAMETER
VOO
YOM

TEST CONDITIONS

MIN

TYp:j:

Output offset voltage
Peak output voltage
Short-circuit output current

ICC

Supply current

TLC14/MF4A-100
MIN

25
VOM+

RL= 10kn

VOMlOS

MAX

Source
Sink

TA = 25°C,

TVP:j:

2

1.8

2

-1.25

-1.7

-1.25

-1.7

fclock = 250 kHz

-0.5

-0.5

4

4

1.2

2.25

1.2

UNIT
mV

50

1.8

See Note 4

MAX

V

mA
2.25

mA

:j: All tYPical values are at TA = 25°C.
NOTE 4: 10S(source) is measured by forcing the output to its maximum positive voltage and then shorting the output to the VCC- terminal
10S(sink) is measured by forcing the output to its maximum negative voltage and then shorting the output to the VCC+ terminal.

-!!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-9

TLC04/MF4A-50, TLC14/MF4A-1 00
BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
SLAS021 A - NOVEMBER 1986 - REVISED MARCH 1995

electrical characteristics over recommended operating free-air temperature range, VCC+
VCC- -5 V,fclock:::; 250 kHz (unless otherwise noted)

=

=5 V,

filter section

VOO

MIN

Output offset voltage

VOM

Peak output voltage

lOS

Short-circuit output current

TlC14/MF4A-100

TlC04/MF4A-50

TEST
CONDITIONS

PARAMETER

TYPt

MAX

MIN

150
VOM+

Rl= 10kn

VOMSource

ICC

Supply current

kSVS

Supply voltage sensitivity (see Figures 1 and 2)

4.3

3.75

4.5

-3.75

-4.1

-3.75

-4.1

-2

-2

5

5

1.8

fclock = 250 kHz

MAX

200

3.75

TA = 25°C,
See Note 4

Sink

TYPt

3

1.8

-30

UNIT
mV
V
rnA

3

-30

rnA
dB

•

t

All typical values are at TA = 25°C.
NOTE 4: 10S(source) is measured by forcing the output to its maximum positive voltage and then shorting the output to the VCC- terminaI.IOS(sink)
is measured by forcing the output to its maximum negative voltage and then shorting the output to the VCC+ terminal.

clocking section
MIN

TYPt

MAX

VCC+=10V,

VCC-=O

6.1

7

8.9

VCC+= 5 V,

VCC-= 0

3.1

3.5

4.4

VCC+;' 10V,

VCC-= 0

1.3

3

3.8

VCC+= 5 V,

VCC-= 0

0.6

1.5

1.9

VCC+= 10V,

VCC-= 0

2.3

4

7.6

VCC:..= 5 V,

VCC-= 0

1.2

2

3.8

PARAMETER
VIT+

Positive-going input threshold voltage

VIT-

Negative-going input threshold voltage

Vhys

Hysteresis voltage (VIT + - VIT-)

VOH

High-level output voltage

VOL

low-level output voltage

TEST CONDITIONS

ClKIN

VCC=10V
VCC =5 V

Input leakage current

VCC=10V
VCC =5V
ClKR

VCC = 10V
VCC = 5 V
VCC = 10V

10

Output current

VCC =5 V
VCC=10V
VCC = 5V

t

10=-10~

1
0.5
2

lS at midsupply,
TA = 25°C

2

ClKR and ClKIN
shortened to VCC-

-3

-7

-0.75

-2

ClKR and ClKIN
shortened to VCC+

3

7

0.75

2

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

V
V
V
V

4.5

10= lO11A

All typical values are at TA = 25°C.

5-10

9

UNIT

V

llA
rnA
rnA

TLC04/MF4A-50, TLC14/MF4A-1 00
BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
SLAS021 A - NOVEMBER 1986 - REVISED MARCH 1995

operating characteristics over recommended operating free-air temperature range, VCC+
VCC- -2.5 V (unless otherwise noted)

=

TLC04/MF4A·50
PARAMETER

TEST CONDITIONS

Maximum clock frequency, f max

See Note 2

Clock-Io-cutoff-frequency ralio (fclock/fco)

fclock " 250 kHz,

Temperature coefficient of clock-to-cutoff
frequency ratio

fclock " 250 kHz

Frequency response above and below
cutoff frequency (see Nole 5)

TA = 25°C

MIN

TYPt

1.5

3

49.27

50.07

MAX

50.87

TLC14/MF4A·100
MIN

TYPt

1.5

3

99

100

±25

MAX

-7.9

-7.57

-7.1

f= 4.5 kHz

-1.7

-1.46

-1.3

fco = 5 kHz,
fclock = 250 kHz,
TA = 25°C

f=3kHz

-7.9

-7.42

-7.1

f = 2.25 kHz

-1.7

-1.51

-1.3

TA=25°C
fclock " 250 kHz

Voltage amplification, dc

fclock " 250 kHz,

Peak-to-peak clock feedthrough voltage

TA = 25°C

Hz/Hz
ppm/oC

±25

f= 6 kHz

Dynamic range (see Nole 6)

UNIT
MHz

101

fco = 5 kHz,
fclock = 250 kHz,
TA = 25°C

Stop-band frequency allentuation at 2 fco

=2.5 V,

dB

dB
78

dB

24

25

dB

-0.15

0

80
RS,,2kn

24

25

-0.15

0

0.15

5

0.15

dB
mV

5

t

All typical values are at TA = 25°C.
NOTES: 2. Above 250 kHz, the input clock duty cycle should be 50% to allow the operational amplifiers the maximum time to sellie while
processing analog samples.
5. The frequency responses al f are referenced 10 a dc gain of 0 dB.
6.' The dynamic range is referenced to 1.06 V rms (1.5 V peak) where Ihe wideband noise over a 30-kHz bandwidlh is typically
106 ~V rms forlhe TLC04/MF4A-50 and 135 ~V rms for the TLC14/MF4A-l00.
'

operating characteristics over recommended operating free-air temperature range, Vcc+
VCe- -5 V (unless otherwise noted)

=

TLC04/MF4A·50
PARAMETER

TEST CONDITIONS

Maximum clock frequency, f max

See Nole 2

Clock-to-cutoff-frequency ralio (fclock/fco)

fclock " 250 kHz,

Temperalure coefficient of clock-to-cutoff
frequency ratio

fclock " 250 kHz

Frequency response above and below
cutoff frequency (see Nole 5)

fco = 5 kHz,
fclock = 250 kHz,
TA = 25°C
fco= 5 kHz,
fclock = 250 kHz,
TA = 25°C

Dynamic range (see Note 6)

TA = 25°C

Slop-band frequency allentualion at 2 fco

fclock " 250 kHz

Voltage amplification, dc

fclock " 250 kHz,

Peak-Io-peak clock feedthrough voltage

TA = 25°C

TA = 25°C

MIN

TYpt

2

4

49.58

49.98

TLC14/MF4A·100
TYPt

MAX

MIN
2

4

50.38

99

100

MAX

f=6kHz

-7.9

-7.57

-7.1

-1.7

-1.44

-1.3

UNIT
MHz

101

Hz/Hz
ppm/oC

±15

±15

f= 4.5 kHz

=5 V,

dB
f= 3 kHz

-7.9

-7.42

-7.1

f = 2.25 kHz

-1.7

-1.51

-1.3

dB
86
24
RS,,2kn

-0.15

25
0
7

24
0.15

-0.15

84

dB

25

dB

0
7

0.15

dB
mV

t AIlIYPlcal values are at TA = 25°C.
NOTES: 2. Above 250 kHz, the input clock duty cycle should be 50% 10 allow the operational amplifiers Ihe maximum time to sellie while
processing analog samples.
5. The frequency responses at f are referenced to a dc gain of 0 dB.
6. The dynamic range is referenced to 2.82 V rms (4 V peak) where Ihe wideband noise over a 30-kHz bandwidth is typically 142 ~ V rms
for Ihe TLC04/MF4A-50 and 178 ~V rms for Ihe TLC14/MF4A-l 00.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-11

TLC04/MF4A-50, TLC14/MF4A.. 100
BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
SLAS021A - NOVEMBER 1986 - REVISED MARCH 1995

TYPICAL CHARACTERISTICS
FILTER OUTPUT

vs
SUPPLY VOLTAGEVCC+ RIPPLE FREQUENCY

o

I'

. -10

III
'a
I

I

VCC+ = 5 V + 50-mV Sine Wave
(0 to 40 kHz)
VCC_=-5V
Filter in at 0 V
fclock = 250 kHz

-20

'5

o~
~

i!

-30

1\

-40

I

f

W

-50

-60

o

5
10
15
20
25
30
35
40
Supply Voltage VCC+. Ripple Frequency - kHz

Figure 1
FILTER OUTPUT

vs
SUPPLY VOLTAGE VCC- RIPPLE FREQUENCY

o

I

.1.

I

I

I

VCC+ =5 V
VCC- = -5 V + 50-mV Sine Wave
(0 to 40 kHz)
-10 I- Filter in at 0 V
fclock = 250 kHz.
-20
III

'a

I

'5

~ -30

o

Ii!

1/

-40

~~

-50

-60

o

5
10
15
20
25
30
35
40
Supply Voltage VCC- Ripple Frequency - kHz

Figure 2

~TEXAS

5-12

INSTRUMENTS
POST OFFICE BOX '655303 • DALLAS, TEXAS 75265

TLC04/MF4A-50, TLC14/MF4A-100
BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
SLAS021A- NOVEMBER 1986 - REVISED MARCH 1995

APPLICATION INFORMATION
5V - - - - - - - - - - - - - - - ,

ill-

CMOS

CL~N

5V

-5V

_~---+--~

2

6

AGND

I
L _________ _
I
VCC-

Butterworth
Fourth-Order
Low-Pass Filter

5
1---+-_

____________ .J

FILTER
OUT

4
-5V-~----------~

Figure 3. CMOS-Clock-Driven Dual-Supply Operation

5V

--+------------,

------------,
7

TTL

CLKR

I

n--

U L

-5 v

____+-________---'

ov

6

I
I
-5V

Butterworth
Fourth-order
Low-Pass Filter

AGND

1---+-----=-5 FILTER
OUT

L----------T4-----------.J
VCC-

Figure 4. TTL-Clock-Driven Dual-Supply Operation

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-13

TLC04/MF4A-50, TLC14/MF4A-1 00
BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
SLAS021 A - NOVEMBER 1986 - REVISED MARCH 1995

APPLICATION INFORMATION
5V

_-_-_-_-_-_-_-_-_-_--,lL ___________ ,

------r-·
3
1
R

Filter
Input

2

,
,
,,,
,,
,,
,

VCC+

lS

level Shift

ClKIN

_+-___..::.8....'--'F'-"IL::!T.!:E!!.R!!:IN'---_ _ _ _ _---1

FilTER
Butterworth
J--=0-=.UT-,---+--..::.5 Filter
Fourth·Order
Output
"'::-l,f---"'=~---------I low·Pass Filter
6

AGND

L__________ ____________
VCC-

,

~

4
-5V--~-----------~

ForVcc= 10V
fclock =

1.6~RC

Figure 5. Self·Clocking Through Schmitt·Trigger Oscillator Dual·Supply Operation

~TEXAS

5-14

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC04/MF4A-50, TLC14/MF4A-100
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWITCHED·CAPACITOR FILTERS
SLAS021 A - NOVEMBER 1986 - REVISED MARCH 1995

APPLICATION INFORMATION
10 V - - - - - - - - - - - - - - - - - - - ,

7
r----------------------,
I
VCC+

lS

3

CMOS
ClKIN

lJ[-lJ[--

See Note A

TTL
ClKR

0V

1_0_V-+-_ _ _

-+----'-+-=~___1

_-+___-t--=-2-+-=c::..:..._ _ _ _ _ _-'
-5V
10kO

OV
FilTER IN
(see Note B)

5VOC

8

FilTER IN

6

AGNO

I

IL _ _ _ _ _ _ _ _VCC__

10 kO

Butterworth
Fourth-Order
low-Pass Filter

FilTER
OUT

5

I

I

_____________ JI
4

See Note C

NOTES: A. The external clock used must be of CMOS level because the clock is input to a CMOS Schmitt trigger.
B. The filter input signal should be dc-biased to midsupply or ac-coupled to the terminal.
C. AGND must be biased to midsupply.

Figure 6. External-Clock-Driven Single-Supply Operation

"!!}. TEXAS

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-15

TLC04/MF4A-50, TLC14/MF4A-1 00
BUTTERWORTH FOURTH-ORDER LOW~PASS
SWITCHED-CAPACITOR FILTERS
SLAS021 A - NOVEMBER 1986 - REVISED MARCH 1995

APPLICATION INFORMATION
10V

7

3

R

2

r~-------------------------~
VCC+
LS

.

CLKR
Nonoverlapping
Clock Generator

10kQ

<\>1
8

FILTER IN

6

AGND

Butterworth
Fourth-Order
Low-Pass Filter

FILTER
OUT

VCC-

I
I
I
I

~------------ 4 ---------------~

10kQ
0.1

~F

See Note A

ForVCC=10V
1
'clock = 1.69 RC

NOTE A: AGND must be biased to midsupply.

Figure 7. Self Clocking Through Schmitt-Trigger Oscillator Single-Supply Operation

~TEXAS

5-16

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TLC04/MF4A-50, TLC14/MF4A-100
BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
SLAS021A- NOVEMBER 1986 - REVISED MARCH 1995

APPLICATION INFORMATION
5V

3

Clock Input

r-----------

I

VCC+

7

--------------~

lS

I
I ClKIN
~-+---='-+==-=----1
I

10kQ

1

2

ClKR

8

FilTER IN

I
I

Butterworth
Fourth..()rder
low·Pass Filter

'------------

VCC-

0.1 !IF

FilTER
OUT

5

______________ .J
4

-5 V ---41................1--------------'

Figure 8. DC Offset Adjustment

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-17

TLC29321
HIGH·PERFORMANCE PHASE·LOCKED LOOP
•

Voltage-Controlled Oscillator (VCO)
Section:
- Complete Oscillator Using Only One
External Bias Resistor (RBIAS)
- Lock Frequency:
22 MHz to 50 MHz (Voo 5 V ±5%,
TA -20°C to 75°C, x1 Output)
11 MHz to 25 MHz (Voo 5 V ±5%,
TA =-20°C to 75°C, x1/2 Output)
- Output Frequency •.. x1 and x1/2
Selectable
Phase-Frequency Detector (PFD) Section
Includes a High-Speed Edge-Triggered
Detector With Internal Charge Pump
Independent VCO, PFD Power-Down Mode
Thin Small-Outline Package (14 terminal)

=
=

=

•

•
•
•
•

CMOS Technology
Typical Applications:
- Frequency Synthesis
- Modulation/Demodulation
- Fractional Frequency Division

•
•

Application Report Availablet
CMOS Input Logic Level

PWPACKAGEt
(TOP VIEW)
LOGICVDD
SELECT'
VCOOUT
FIN-A
FIN-B
PFD OUT
LOGICGND

14
13
12
11
10
9

VCOVDD
BIAS
VCOIN
VCOGND
VCO INHIBIT
PFD INHIBIT
NC

8

t Available in tape and reel only and ordered as the
TLC2932IPWLE.
NC - No internal connection

description
The TLC29321 is designed for phase-locked-loop (PLL) systems and is composed of a voltage-controlled
oscillator (VCO) and an edge-triggered-type phase frequency detector (PFD). The oscillation frequency range
, of the VCO is set by an external bias resistor (RBIAS). The VCO has a 1/2 frequency divider at the output stage.
The high-speed PFD with internal charge pump detects the phase difference between the reference frequency
input and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions,
which can be used as a power-down mode. The TLC29321 is suitable for use as a high-performance PLL due
to the high speed and stable oscillation capability of the device.

functional block diagram
VCOIN
FIN-A
FIN-B
PFD INHIBIT

4
5
9

Phase
Frequency 6
Detector

BIAS
PFD OUT VCO INHIBIT

12
13
10
2

VoltageControlled
Oscillator

3

VCOOUT

SELECT

AVAILABLE OPTIONS
PACKAGE
TA

SMALL OUTLINE
(PW)

-20°C to 75°C

TLC29321PWLE

tTLC2932 Phase-locked-Loop Building Block With Analog Voltage-Controlled Oscillator and Phase Frequency Detector (SLAA011).

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright © 1997, Texas Instruments Incorporated

5-19

TLC29321
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS097E - SEPTEMBER 1994 - REVISED MAY 1997

Terminal Functions
TERMINAL
NAME

NO.

DESCRIPTION

1/0

FIN-A

4

I

Input referenc!l frequency f(REF IN) is applied to FIN-A.

FIN-B

5

I

Input for VCO external counter output frequency f(FIN-B). FIN-B is nominally provided from the external
counter.

LOGICGNO

7

GNO for the internal logic.

LOGICVOO

1

Power supply for the internal logic. This power supply should be separate from VCO vOO to reduce
cross·coupling between supplies.

NC

8

PFO INHIBIT

9

I

PFO OUT

6

a

PFO output. When the PFO INHIBIT is high, PFO output is in the high·impedance state.

13

I

Bias supply. An external resistor (RBIAS) between
oscillation frequency range.

SELECT

2

I

VCO output frequency select. When SELECT.is high, the VCO output frequency is x1/2 and when low, the
output frequency is xl, see Table 1.

VCOIN

12

I

VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
oscillation frequency.

VCO INHIBIT

10

I

VCOGNO

11

BIAS

VCOOUT

3

VCOVOO

14

No internal connection.
PFO inhibit control. When PFO INHIBIT is high, PFO output is in the high·impedance state, see Table 3.

veo VDO and

BIAS supplies bias for adjusting the

VCO inhibit control. When VCO INHIBIT is high, VCO OUT is low (see Table 2).
GNOforVCO.

a

VCO output. When the VCO INHIBIT is high, VCO output is low.
Power supply for VCO. This power supply should be separated from LOGIC VOO to reduce cross-coupling
between supplies.

detailed description

veo oscillation frequency
The veo oscillation frequency is determined by an external resistor (RSIAS) connected between the veo Voo
and the BIAS terminals. The oscillation frequency and range depends 6n this resistor value. The bias resistor
value for the minimum temperature coefficient is nominally 3.3kil with 3-V at the veo VOO terminal and
nominally 2.2 kQ with S-V at the veo Voo terminal. For the lock frequency range refer to the recommended
operating conditions. Figure 1 shows the typical frequency variation and veo control voltage.
VCO Oscillation Frequency Range

1/2VDD
VCO Control Voltage (VCO IN)

Figure 1. veo Oscillation Frequency

5-20

~TEXAS .'
INSTRUMENTS'
POST OFFICE BOX 655303. DALLAS, TEXAS 75265

TLC29321
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS097E - SEPTEMBER 1994 - REVISED MAY 1997

VCO output frequency 1/2 divider
The TLC29321 SELECT terminal sets the fosc or 1/2 fosc VCO output frequency as shown in Table 1 . The 1/2
fosc output should be used for minimum VCO output jitter.
Table 1.

veo Output 1/2 Divider Function
SELECT

VCOOUTPUT

Low

lose

High

1/2 lose

VCO inhibit function
The VCO has an externally controlled inhibit function which inhibits the VCO output. A high level on the VCO
INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during
the power-down mode, refer to Table 2.
Table 2.

veo Inhibit Function

VCOINHIBIT

VCO OSCILLATOR

VCOOUTPUT

Low

Active

Active

Normal

High

Stopped

Low leval

PowarDown

IDD(VCO)

PFD operation
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN-A and FIN-B as shown in Figure 2. Nominally the
reference is supplied to FIN-A, and the frequency from the external counter output is fed to FIN-B.

FIN-A

I
I

FIN-B

___ .L ___ -+l.. __ _
I
I

PFDOUT

I I
I

VOH

....---

Hi·Z
VOL

Figure 2. PFD Function Timing Chart
PFD output control
A high level on the PFD INHIBIT.terminal places the PFD output in the high-impedance state and the PFD stops
phase detection as shown in Table 3. A high level on the PFD INHIBIT terminal also can be used as the
power-down mode for the PFD.
Table 3.

veo Output Control Function

PFDINHIBIT

DETECTION

PFDOUTPUT

Low

Active

Active

Normal

High

Stopped

Hi-Z

PowarDown

IDD(PFD)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-21

TLC29321
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS097E-SEPTEMBER 1994- REVISED MAY 1997

schematics

veo block schematic
RBIAS

VCOOUT

VCOIN

VCOINHIBIT

PFD block schematic

r-ch,;g;i>u;;P-l.
I
I
FIN-A

FIN-B

voo I

I
I
I

I
I
I
I
I
I
I
IL _ _ _ _ _ __
_ .JI

PFOOUT

PFO INHIBIT

absolute maximum ratingst
Supply voltage (each supply), Voo (see Note 1) ................................................ 7 V
Input voltage range (each input), VI (see Note 1) ............................... -0.5 V to Voo + 0.5 V
Input current (each input), II ............................................................... ±20 mA
Output current (each output), 10 .......................................................... ±20 mA
Continuous total power dissipation, at (or below) TA = 25°C (see Note 2) ....................... 700 mW
Operating free-air temperature range, TA ............................................ -20°C to 75°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds .............. :................ 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute· maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network GND.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 5.6 mW/oC.

~TEXAS

5-22

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E - SEPTEMBER 1994 - REVISED MAY 1997

recommended operating conditions
PARAMETER

Supply voltage, VDD (each supply, see Note 3)

MIN

NOM

MAX

VDD= 3 V

2.85

3

3.15

VDD =5 V

4.75

5

5.25

Input voltage, VI (inputs except VCO IN)

0

VDD

Output current, 10 (each output)

0

±2

VCO control voltage at VCO IN
Lock frequency (xl output)

Lock frequency (xl/2 output)

Bias resistor, RBIAS

0.9

VDD

VDD = 3V

14

21

VDD= 5 V

22

50

VDD =3 V

7

10.5

VDD =5 V

11

25

VDD =3 V

2.2

3.3

4.3

VDD = 5V

1.5

2.2

3.3

UNIT

V
V
rnA
V
MHz

MHz
kQ

NOTE 3: It IS recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) should be at the same voltage
and separated from each other.

electrical characteristics over recommended operating free-air temperature range, Voo
(unless otherwise noted)

=3 V

veo section
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

IOH=-2mA

VOL

Low-level output voltage

IOL=2 rnA

VIT

Input threshold voltage at SELECT, VCO INHIBIT

II

Input current at SELECT, VCO INHIBIT

MIN

TYP

MAX

2.4

V
0.3

0.9

UNIT

1.5

VI = VDD or GND

V

2.1

V

±1

I!A
MQ

Zi(VCO IN)

Input impedance

VCO IN = 1/2 VDD

IDD(lNH)

VCO supply current (inhibit)

See Note 4

0.01

1

I!A

IDD(VCO)

VCO supply current

See Note 5

5

15

rnA

..

10

NOTES: 4. Current Into VCO VDD, when VCO INHIBIT = VDD, PFD IS tnhlbltE1d .
5. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 kQ, VCO INHIBIT = GND, and PFD is inhibited.

PFO section
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

IOH=-2mA

VOL

Low-level output voltage

10L= 2 rnA

0.2

V

10Z

High-impedance-state output current

PFD INHIBIT = high,
VI = VDD or GND

±1

IiA

VIH

High-level input voltage at FIN-A, FIN-B

VIL

Low-level input voltage at FIN-A, FIN-B

VIT

Input threshold voltage at PFD INHIBIT

Ci

Input capacitance at FIN-A, FIN-B

V

2.7

2.7

V
0.5

0.9

1.5

2.1

V
V
pF

5

Zi

Input impedance at FIN-A, FIN-B

IDD(Z)

High-impedance,state PFD supply current

See Note 6

0.01

1

I!A

IDD(PFD)

PFD supply current

See Note 7

0.1

1.5

rnA

NOTES:

10

MQ

. .

6. Current mto LOGIC VDD, when FIN-A, FIN-B = GND, PFD INHIBIT = VDD, no load, and VCO OUT IS Inhibited .
7. Current into LOGIC VDD, when FIN-A, FIN-B = 1 MHz (VI(PP) = 3 V, rectangular wave). NC = GND, no load, and VCO OUT is
inhibited.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-23

'FLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E - SEPTEMBER 1994 - REVISED MAY 1997

operating characteristics over recommended operating free-air temperature range, VDD = 3 V
(unless otherwise noted)
VCOsection
PARAMETER

TEST CONDITIONS

fosc

Operati ng oscillation frequency

RBIAS = 3.3 kil. VCO IN = 1/2 VDD

ts(fosc)

Time to stable oscillation (see Note 8)

Measured from VCO INHIBIT.j,

tr

Rise time

If

Fall time

MIN

TYP

MAX

UNIT

15

19

23

MHz

10

liS

CL = 15 pF.

See Figure 3

7

CL = 50 pF.

See Figure 3

14

CL = 15 pF.

See Figure 3

6

CL = 50 pF.

See Figure 3

10

14

12

ns

ns

Duty cycle at VCO OUT

RBIAS = 3.3 kil. VCO IN = 1/2 VDD.

a(fosc}

Temperature coefficient of oscillation frequency

RBIAS = 3.3 kil. VCO IN = 1/2 VDD.
TA = -20°C to .75°C

0.04

%IOC

kSVS(fosc}

Supply voltage coefficient of oscillation frequency

RBIAS = 3.3 kil. VCO IN = 1.5 V.
VDD = 2.85 V to 3.15 V

0.02

%/mV

Jitter absolute (see Note 9)

RBIAS = 3.3 kil

100

ps

NOTES:

45%

50%

55%

8. The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
9. The low-pass-filter (LPF) circuit is shown in Figure 28 with calculated values listed in Table 7. Jitter performance is highly dependent
on circuit layout and external device characteristics. The jitter specification was made with a carefully designed PCB with no device
socket.

PFD section
PARAMETER

TEST CONDITIONS

f max

Maximum operating frequency

tpLZ

PFD output disable time from low level

tPHZ

PFD output disable lime from high level

tpZL

PFD output enable time to low level

tpZH

PFD output enable time to high level

tr

Rise time

tf

Fall time

TVP

MAX

21

50

23

50

20

See Figures 4 and 5 and Table 4

CL= 15 pF.

See Figure 4

~TEXAS

INSTRUMENTS
5-24

MIN

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

UNIT
MHz
ns

11

30

10

30

2.3

10

ns

2.1

10

ns

ns

TLC29321
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS097E - SEPTEMBER 1994 - REVISED MAY 1997

electrical characteristics over recommended operating free-air temperature range, VDD
(unless otherwise noted)

=5 V

veo section
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

4

UNIT

VOH

High-level output voltage

'OH=-2mA

VOL

Low-level output voltage

'OL=2mA

V,T

Input threshold voltage at SELECT, VCO INHIBIT

I,

Input current at SELECT, VCO INHIBIT

V, = VDD or GND

Zi(VCO IN)

Input impedance

VCO IN = 1/2 VDD

IDD(lNH)

VCO supply current (inhibit)

See Note 4

0.01

1

~A

IDD(VCO)

VCO supply current

See Note 5

15

35

rnA

V

0.5
1.5

2.5

V

3.5

V

±1

~A

MQ

10

NOTES: 4. Current into VCO VDD, when VCO INHIBIT = VDD, and PFD is inhibited.
5. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 kQ, VCO INHIBIT = GND, and PFD is inhibited.

PFD section
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

. High-level output voltage

'OH=2mA

VOL

Low-level output voltage

IOL=2mA

0.2

V

10Z

High-impedance-state output current

PFD INHIBIT = high,
VI = VDD or GND

±1

~

VIH

High-level input voltage at FIN-A, FIN-B

VIL

Low-level input voltage at FIN-A, FIN-B

V,T

Input threshold voltage at PFD INHIBIT

Ci

Input capacitance at FIN-A, FIN-B

Zi

Input impedance at FIN-A, FIN-B

IDDm

High-impedance-state PFD supply current

See Note 6

0.01

1

~

IDD(PFD)

PFD supply current

See Note 7

0.15

3

rnA

4.5

V

V

4.5
1
1.5

2.5

3.5

5

V
V

pF
MQ

10

NOTES: 6. Current into LOGIC VDD, when FIN-A, FIN-B = GND, PFD INHIBIT = VDD, no load, and VCO OUT IS Inhibited.
7. Current into LOGIC VDD. when FIN-A, FIN-B = 1 MHz (V'(PP) = 5 V. rectangular wave). PFD INHIBIT = GND, no load, and
VCO OUT is inhibited.

~TEXAS

INSTRUMENTS
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TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E - SEPTEMBER 1994 - REVISED MAY 1997

operating characteristics over recommended operating free-air temperature range, VDD
(unless otherwise noted)

=5 V

VCOsection
PARAMETER

TEST CONDITIONS

fosc

Operating oscillation frequency

RBIAS = 2.2 kn, VCO IN = 1/2 VDD

ts(fosc)

Time to stable oscillation (see Note 8)

Measured from VCO INHIBIT.j.

tr

Rise time

tf

Fall time

TYP

MAX

UNIT

30

41

52

MHz

10

j.lS

CL = 15 pF,

See Figure 3

5.5

CL = 50 pF,

See Figure 3

8

CL = 15 pF,

See Figure 3

5

CL = 50 pF,

See Figure 3

6

Duty cycle at VCO OUT

RBIAS = 2.2 kn, VCO IN = 1/2 VDD,

Cl(fosc)

Temperature coefficient of oscillation frequency

RBIAS = 2.2 kn, VCO IN = 1/2 VDD,
TA = -20°C to 75°C

kSVS(fosc)

Supply voltage coefficient of oscillation frequency

RBIAS = 2.2 kf.!, VCO IN = 2.5 V,
VDD = 4.75 V to 5.25 V

Jitter absolute (see Note 9)·

RBIAS = 2.2 kn

NOTES:

MIN

45%

50%

10

10

ns

ns

55%

0.06

·/%C

0.006

o/o/mV

100

ps

8: The time period to the stable VCO oscill 9tion frequency after the VCO INHIBIT terminal is changed to a low level.
9. The LPF circuit is shown in Figure 28 with calculated values listed in Table 7. Jitter performance is highly dependent on circuit layout
and external device characteristics. The jitter specification was made with a carefully designed PCB with no device socket.

PFD section
PARAMETER

TEST CONDITIONS

f max

Maximum operating frequency

tpLZ

PFD output disable time from low level

tpHZ

PFD output disable time from high level

tpZL

PFD output enable time to low level

tpZH

PFD output enable time to high level

tr

Rise time

tf

Fall time

TYP

MAX

21

40

See Figures 4 and 5 and Table 4

20

40

7.3

20

6.5

20

CL = 15 pF,

See Figure 4

~TEXAS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT
MHz

40

INSTRUMENTS
5-26

MIN

ns

ns

2.3

10

ns

1.7

10

ns

TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E - SEPTEMBER 1994 - REVISED MAY 1997

PARAMETER MEASUREMENT INFORMATION

1)%

900Af1I

VCOOUT

_ _..:1:.;,0%;;...;,r

--+! J4- tr

I
I

~

10%

j4-tf

Figure 3. VCO Output Voltage Waveform

FIN-At

\

~I

PFOINHISIT

GNO

!

10%

-

50%jI

~

i4--t

I~ i4-- tr

PFOOUT

:::
VOO

I
I
I
I
I
I
I
I

FIN-st

--------

W;90%

-----------------

GNO

--.J

VOO
GNO

50%

\.=

10%

50%1

VOO

----

tpZL~

(a) OUTPUT PULLOOWN
(see Figure 5 and Table 4)

GNO

I

!~:0%
I

VOO

~tpLZ

90%

i

VOO
GNO

I

1-.1 J+- tf
VOH

--------

50%j

I

GNO

I
I
tpZH~

\

I
I
I
I

tPHZ

50%\.-----

VOO

VOL

(b) OUTPUT PULLUP
(see Figure 5 and Table 4)

t FIN-A and FIN-B are lor reference phase only, not for timing.

Figure 4. PFD Output Voltage Waveform

T

Table 4. PFD Output Test Conditions
PARAMETER

RL

CL

51

52

Open

Close

Test Point

tpZH
tPHZ
tr

1 kQ

RL
OUT

1SpF

~

VOO

51

PFOOUT

tpZL
tpLZ

Close

Open

-~

tf

Figure 5. PFD Output Test Conditions

~TEXAS

INSTRUMENTS
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5-27

TLC29321
HIGH·PERFORMANCE PHASE·LOCKED lOOP
SLAS097E SEPTEMBER 1994':' REVISED MAY 1997

TYPICAL CHARACTERISTICS
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE

VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE

40

100

VOO=3 V
RSIAS = 2.2 kn

N

J:

:£!

:;;

.

I

30

~
C

..

:I

~

I!!

"c

20

..
..

/
60

h

0

~

~/

'u

0
0

g

80

:I
0"

"c

~
'u

-2~

:;;

I

>c

u

-'

VOO=5 V
RSIAS = 1,5 kG

-20°C

~

40

(J

>

u

~

75°C

V

~

I

..

u

~

// /'

V./

~V

0

10

I

/~

20

0
0

.veo IN -

2
VCO Control Voltage - V

3

o

4
2
3
VCO IN - VCO Control Voltage - V

Figure 6

Figure 7

VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE

VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE

40

80
VOO=3 V
RSIAS = 3.3 kG

N

J:

:;;
>c

u

I

-20~C

30

>-

.
u

I!!

"c

20

0

~

~

..
I

~

:I
0"

40

.

'u

0

8>

60

C

I!!

:iii

0
0

g

10

20

.

u

I

r-----

V

~~
~~

V

75°C

25°C

u

~

o~

o

______

~

________

~

______

2
VCO IN - VCO Control Voltage - V

~
~

3

FigureS

2

~TEXAS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

4

VCO IN - VCO Control Voltage - V

Figure 9

INSTRUMENTS
5-28

L

-20~

J:

:;;

:I
0"

"c
,51

VOO=5 V
RSIAS = 2.2 kn

N

I

.

5

5

TLC29321
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS097E- SEPTEMBER 1994- REVISED MAY 1997

TYPICAL CHARACTERISTICS
VCOOSCILLATION FREQUENCY

VCO OSCILLATION FREQUENCY

vs

vs

VCO CONTROL VOLTAGE

VCO CONTROL VOLTAGE

~r---------r--------'r--------'

VOO=3 V
RBIAS = 4.3 kn

80

I

Voo=5V
I- RBIAS = 3.3 kn

:I:!

:E
30r---------r-------~r-------_;

I

~
c

60

g:

~

I
c

o

:i
10r-------~~~----_;--------_;

~o

g

25°C
20

I

O~

o

______

~

________

~

______

L

40

75°cl

J

~C

~

2
VCO IN - VCO Control Voltage - V

3

2
4
3
VCO IN - VCO Control Voltage - V

Figure 10

VCO OSCILLATION FREQUENCY

vs

vs

BIAS RESISTOR

BIAS RESISTOR

30

60
VOO=3 V
VCO IN = 1/2 Voo
TA = 25°C

N

:I:

:E

:I:

:E
I

>-

25

u
C

GI
::I

W

..............

C

20

!!!

t.........

~
0

IL

~

C

-.....

0

~

(,)

I

50

GI
::I
C'

IL

>

VOO=5V
VCO IN = 1/2 Voo
TA = 25°C

N

I

~

5

Figure 11

VCO OSCILLATION FREQUENCY

~
c

./~
~~

~

15

i

40

'13

~ f'..

II)

~

~~

0
0

'"

(,)

>
I

III
.P

30

U

II)

.P
10
2

2.5

3.5
4
RBIAS - Bias Resistor - kn

3

4.5

20
1.5

Figure 12

2.5
2
3
RBIAS - Bias Resistor - kn

3.5

Figure 13

~TEXAS

INSTRUMENTS
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5-29

TLC29321
HIGH-PERFORMANCE PHASE-LOCKED·LOOP
SLASQ97E - SEPTEMBER 1994 - REVJSED MAY 1997

TYPICAL CHARACTERISTICS
TEMPERATURE COEfFICIENT OF
OSCILLATION FREQUENCY

TEMPERATURE COEFfiCIENT OF
OSCILLATION FREQUENCY

vs

vs

BIAS RESISTOR

BIAS RESISTOR

0.4

0.4

VOO=3V
veo IN = 1/2 Voo
TA = -20 oe 10 75°e

VOO=5V
veo IN = 1/2 Voo
TA = -20°C to 75°e

i\.

"'-... ........
.............
........... 1 .....

V

'""

/"

i
2.5
3
3.3 3.5
4
RBIAS - Bias Resistor - kQ

4.5

vs

VCO SUPPLY VOLTAGE

VCO SUPPLY VOLTAGE

48r-----r-----r----,..----,
RBIAS = 2.2 kQ
veo IN = 1/2 VOO
TA=25°e

RBIAS = 3.3 kQ
veo IN= 1.5 V
TA = 25°e

I

>c
~

22

~

20

3.5

VCO OSCILLATION FREQUENCY

vs
24

u

I

Figure 15

VCO OSCILLATION FREQUENCY

:E

I

2 2.2
2.5
3
RBIAS - Bias Resistor - kQ

Figure 14

:!!

"'-J . . . . V

/

/

/

441-----+---+----+------i

1c
.~

0
0

~
I

18

~

fA

..E
16
3.05

----

36~----+---~----+-----~

32~----~------~------~----~

3.15

3

4.75

Figure 16

Figure 17

~TEXAS
5-30

5
Voo - veo Supply Voltage - V

Voo - veo Supply Voltage - V

INSTRUMENTS

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5.25

TLC29321
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS097E- SEPTEMBER 1994- REVISED MAY 1997

TYPICAL CHARACTERISTICS
SUPPLY VOLTAGE COEFFICIENT OF VCO
OSCILLATION FREQUENCY

0.05

SUPPLY VOLTAGE COEFFICIENT OF VCO
OSCILLATION FREQUENCY

vs

vs

BIAS RESISTOR

BIAS RESISTOR

Voo = 2.85 V to 3.15 V
veo IN = 1/2 VOO
TA=25°e

Voo = 4.75 V to 5.25 V
veo IN = 1/2 VOO
TA= 25°e

0.04

0.01

--

0.03

0.02

"0
->
c_

~

:§ ~
li r;

~ ........

..........

0.01

85i
.. :::I

E!

~ ...........

~

...

0.005

~

----

~

CI.
CI.
:::I

UI
I

o
2.5

2

3.5
3
4
RBIAS - Bias Resistor - kQ

4.5

!
tS

o

1.5

2
2.5
3
RBIAS - Bias Resistor - kn

Figure 18

3.5

Figure 19

RECOMMENDED LOCK FREQUENCY
(x10UTPUT)

RECOMMENDED LOCK FREQUENCY
(x10UTPUT)

vs

vs

BIAS RESISTOR

BIAS RESISTOR
60.-----~--~--,_------.-----_,

Voo = 2.85 V to 3.15 V
TA = -20oe to 75°e

30

Voo = 4.75 V to 5.25 V
TA = -20 oe to 75°e

25

20

15 r-----r-------ir---"
20r------+------~------r-----_i

10~--

2

__

~

2.5

__

~~

__

3
RBIAS - Bias

~

____

~

3.5

____

4

~esistor -

~

4.5

10~

____

1.5

k!J

Figure 20

~

______

~

______

~

2
2.5
3
RBIAS - Bias Resistor - k!J

____

~

3.5

Figure 21

~TEXAS

INSTRUMENTS
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TLC29321
HIGH·PERFORMANCE PHASE·LOCKED LOOP
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APPLICATION INFORMATION
RECOMMENDED LOCK FREQUENCY
{x1/2 OUTPUn

RECOMMENDED LOCK FREQUENCY
{x1/20UTPUn

vs

vs

BIAS RESISTOR

BIAS RESISTOR

15

i

I

f;' 12.5 1

I~
i
I

~~----~----~----~-----Voo = 4.75 V to 5.25 V
TA = -20°C to 75°C
SELECT=VOO

VOO = 2.85 V to 3.15 V .
TA = _20°C to 75°C
SELECT=VOO

---t---+--+---I---i

10

10r-----~----~----~----~

7.51-----if----+.::

5~-~--~~--~--~--~
2
2~
3
3~
4
4.5

5.~----~----L-----L---~
1.5

RBIAS - Bias Resistor - kn

2.5

Figure 23

Figure 22

="lExAs ..
5-32

2

INSTRUMENTS .

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

RBIAS - Bias Resistor - kn

3.5

TLC29321
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS097E - SEPTEMBER 1994 - REVISED MAY 1997

APPLICATION INFORMATION
gain of VCO and PFD
Figure 24 is a block diagram of the PLL. The
countdown N value depends on the input
frequency and the desired veo output frequency
according to the system application requirements.
The Kp and Kv values are obtained from the
operating characteristics of the device as shown
in Figure 24. Kp is defined from the phase detector
VOL and VOH specifications and the equation
shown in Figure 24(b). Kv is defined from
Figures 8, 9,10, and 11 as shown in Figure 24(c).

fREF

The parameters for the block diagram with the
units are as follows:
-2lt

Kv : veo gain (rad/sN)

0

-It

It

2lt

fMAX

~~~-+--+-~-VOH

Kp : PFD gain (V/rad)
Kf : LPF gain (VN)
KN : count down divider gain (1/N)

---'~+--+--+---¥~ VOL fMIN

external counter

~

When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.

Range of
Comparison

J

VOH-VOL
Kp=
4lt
(b)

:7T
I

VINMIN
KV =

VINMAX

2lt(fMAX - fMIN)
VIN MAX - VIN MIN
(e)

Figure 24. Example of a PLL Block Diagram

RBIAS
The external bias resistor sets the veo center frequency with 1/2 VDD applied to the veo IN terminal. However,
for optimum temperature performance, a resistor value of 3.3 kQ with a 3-V supply and a resistor value of 2.5
kQ for a 5-V supply is recommended. For the most accurate results, a metal-film resistor is the better choice
but a carbon-compositiion resistor can be used with excellent results also. A 0.22 /IF capacitor should be
connected from the BIAS terminal to ground as close to the device terminals as possible.

hold-in range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
configurations shown in Figure 25 is as follows:

Where
Kf (00) = the filter transfer function value at

0> =

00

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INSTRUMENTS
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TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E - SEPTEMBER 1994 - REVISED MAY 1997

APPLICATION INFORMATION
. low-pass-filter (LPF) configurations
Many excellent references are available that include detailed design information about LPFs and should be
consulted for additional information. Lag-lead filters or active filters are often used. Examples of LPFs are shown
in Figure 25. When the active filter of Figure 25(c) is used, the reference should be applied to FIN-8 because
of the amplifier inversion. Also, in practical filter implementations, C2 is used as additional filtering at the VCO
input. The value of C2 should be equal to or .Iess than one tenth the value of C1.
R1

VI

R1

-WIr-_..--._-

VI~VO
T1 =C1R1

I

T1 = C1R1
T2 = C1R2

C1

R2

Vo

C2

>-----vo
R1

(a) LAG FILTER

T1 =C1R1
T2 = C1R2

(b) LAG-LEAD FILTER
(c) ACTIVE FILTER

Figure 25. LPF Examples for PLL

the passive filter
The transfer function for the lag-lead filter shown in Figure 25(b) is;

1 + s • T2

Vo
V IN = 1

+s

• (T1

+ T2)

Where
T1 = R1 • C1 and T2 = R2 • C1
Using this filter makes the closed loop PLL system a second-order type 1 system. The response curves of this
system to a unit step are shown in Figure 26.

the active filter
When using the active integrator shown in Figure 25(c), the phase detector inputs must be reversed since the
integrator adds an additional inversion. Therefore, the input reference frequency should be applied to the FIN-8
terminal and the output of the VCO divider should be applied to the input reference terminal, FIN-A.
The transfer function for the active filter shown in Figure 25(c) is:
F(s) = 1

+s

• R2 • C1
s • R1 • C1

Using this filter makes the closed loop PLL system
system to a unit step are shown in Figure 27.

a second-order type 2 system. The response curves of this

basic design example
The following design example presupposes that the input reference frequency and the required frequency of
the VCO are within the respective ranges of the device.

~TEXAS

INSTRUMENTS
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TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E - SEPTEMBER 1994 - REVISED MAY 1997

APPLICATION INFORMATION
basic design example (continued)
Assume the loop has to have a 100 Ils settling time (ts) with a countdown N = 8. Using the Type 1, second order
response curves of Figure 26, a value of 4.5 radians is selected for conts with a damping factor of 0.7. This
selection gives a good combination for settling time, accuracy, and loop gain margin. The initial parameters are
summarized in Table 5. The loop constants, Kvand Kp, are calculated from the data sheet specifications and
Table 6 shows these values.
The natural loop frequency is calculated as follows:
Since

Then
COn = 1Oci5~s = 45 k-radians/sec
Table 5. Design Parameters
PARAMETER
Division factor
Lockup time
Radian value to selected lockup time
Damping factor

SYMBOL

VALUE

N

8

UNITS

t

100

JlS

Olnt

4.5

rad

;

0.7

Table 6. Device Specifications
PARAMETER

SYMBOL

VALUE

UNITS

76.6

MradNls

70

MHz

20

MHz

VIN MAX

5

V

VINMIN

0.9

V

0.342357

V/rad

VCOgain
fMAX
KV

fMIN

PFD gain

Kp

Table 7. Calculated Values
PARAMETER
Natural angular frequency

SYMBOL

VALUE

UNITS

Oln

45000

rad/sec

3.277

Mrad/sec
Q

K = (KV. Kp)/N
Lag-lead filter
Calculated value
Nearest standard value

R1

15870
16000

Calculated value
Nearest standard value

R2

308
300

Q,

Selected value

C1

0.1

JlF

~TEXAS

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5-35

TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E - SEPTEMBER 1994 - REVISED MAY 1997

APPLICATION INFORMATION
Using the low-pass filter in Figure 25(b) and divider ratio N, the transfer function for phase and frequency are
shown in equations 1 and 2. Note that the transfer function for phase differs from the transfer function for
frequency by only the divider value N. The difference arises from the fact that the feedback for phase is unity
while the feedback for frequency is 1/N.
Hence, transfer function of Figure 24 (a) for phase is

2(s) _
Kp • KV
<1>1 (s) - N • (T1 + T2)

1+s·T2
2
s

[
+ s

and the transfer function for frequency is

FOUT(s) _ Kp • Kv

1 + s • T2

FREF(S) - (T1 + T2)

2
s

[
+ s·

(1 )

Kp • KV • T2]
Kp • KV
1 + N. (T1 + T2) + N • (T1 + T2)

I

(2)

Kp. KV. T2]
Kp. KV
1 + N • (T1 + T2) + N • (T1 + T2)

The standard two-pole denominator is D =s2 + 2 ~ con S + con2 and comparing the coefficients of the denominator
of equation 1 and 2 with the standard two-pole denominator gives the following results.
Kp. KV
N· (T1 + T2)
Solving for T1 + T2
Kp. KV
T1 + T2 = -'---;:
N •W 2

(3)

n

and by using this value for T1 + T2 in equation 3 the damping factor is

t = wn •
2

(T2

+

N
)
Kp. Kv

solving for T2
T2=2t
W

N
Kp. KV

then by substituting for T2in equation 3
T1 = KV • Kp
N • wn2

_~ +
wn

N
Kp. KV

~TEXAS

INSlRUMENTS
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TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E - SEPTEMBER 1994 - REVISED MAY 1997

APPLICATION INFORMATION
From the circuit constants and the initial design parameters then

~

N]

R2 - [2
- ron - Kp • KV

R1

1
C1

N] 1
Kp • Kv 2 ~
• N - ron + Kp • Kv C1

= [ ron 2

The capacitor, C1, is usually chosen between 1 JlF and 0.1 JlF to allow for reasonable resistor values and
physical capacitor size. In this example, C1 is chosen to be 0.1 JlF and the corresponding R1 and R2 calculated
values are listed in Table 7.

~TEXAS

INSTRUMENTS
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5-37

TLC29321
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E - SEPTEMBER 1994 - REVISED MAY 1997

APPLICATION INFORMATION

1.8

1----+--+---+--+------1f----+I ---+---+--+----+---+---+------I

1.7

I~
~=~.1
I----+--+--j-H-+\+__----1f----+---+---+--+----+-__+_-_+_-----I

1.6

I----+--'--+-+-/_+__+_
X-:l"-----1f---+I --+---+--t---t--+---I---I

1.5

1----+-....,I'r+-I/--7I""f\;:.....;t~--T-r-+-~-=-+0;4--+---+--I----+--+--+-----1

1.4

1---~-=+-1\-6-#1/-' /M~:\-+l~r7/'-/--+---~-=-+0~5--+--I---,+-r\-+---+-+---I

/

~=Ot

-'" \ r

~ =0.3

/f-+-

I
II

1.3 ~=O'r ~ If jK~
~=~.8, ~K~\
~
f/~YY 7
1.2

I]

1
~
--

I
S =0.2

S =0.3

1.5

u

Y

s= I

V-

'~

J

\'-.V /

""~I1'1

0.2
0.1

o

o

2

3

4

5

6

7

8

9

10

11

12

13

conI

Figure 27. Type 2 Second-Order Step

Respon~e

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-39

TLC29321
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS097E - SEPTEMBER 1994 - REVISED MAY 1997

APPLICATION INFORMATION
AVDD

VDD
VCO
' - - - - - - - I LOGIC VDD (Digital)

2

14

VCOVDD

SELECT
BIAS

R1t

13

0.2211F
REF IN

DGND

3

VCOOUT

4

FIN-A

5

FIN-B

6

PFDOUT

7

VCOIN
VCOGND

R3

12
11

C2

R2

C1

10
AGND

LOGIC GND (Digital)

NC

8

DGND'---------------------------------~_+----------~

Divide
By
S4
N
L-__~ '--__________________________________~~--r_~~S~5~

S3~

R4
DVDD

t RSIAS resistor

R5

R6

DGND

----~-~--'

Figure 28. Evaluation and Operation Schematic

PCB layout considerations
The TLC2932I contains a high frequency analog oscillator; therefore, very careful breadboarding and
printed-circuit-board (PCB) layout is required for evaluation.
The following design recommendations benefit the TLC29321 user:
•

External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.

•

RF breadboarding or RF PCB techniques should be used throughout the evaluation and production
process.

•

Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.

•

LOGIC VDD and VCO VDD should be separate PCB traces and connected to the best filtered supply point
available in the system to minimize supply cross-coupling.

•

VCO VDD to GND and LOGIC VDD to GND should be decoupled with a O.1-J.1F capacitor placed as close
as possible to the appropriate device terminals.

•

The no-connection (NC) terminal on the package should be connected to GND.

~TEXAS

5-40

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2933
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS136A- APRIL 1996 - REVISED JUNE 1997

•

Voltage-Controlled Oscillator (VCO)
Section:
- Ring Oscillator Using Only One
External Bias Resistor (RaIAS)
- Lock Frequency:
43 MHz to 100 MHz (Voo = 5 V ±5%,
TA -20°C to 75°C, x1 Output)
37 MHz to 55 MHz (Voo = 3 V ±5%,
TA = -20°C to 75°C)
.

=

•

Phase-Frequency Detector (PFD) Section
Includes a High-Speed Edge-Triggered
Detector With Internal Charge Pump

•
•

Independent VCO, PFD Power-Down Mode
Thin Small-Outline Package (14 terminal)

•
•

CMOS Technology
Typical Applications:
- Frequency Synthesis
- Modulation/Demodulation
- Fractional Frequency Division

•

CMOS Input Logic Level

PWPACKAGEt
(TOP VIEW)

LOGIC Voo
TEST
VCOOUT
FIN-A
FIN-B
PFD OUT
LOGICGND

L...-_ _ _ _

....J~

VCOVDO
BIAS
VCOIN
VCOGND
VCO INHIBIT
PFD INHIBIT
NC

t Available in tape and reel only and ordered as the
TLC2933PWLE.
NC - No internal connection

description
The TLC2933 is deSigned for phase-locked-loop (PLL) systems and is composed of a voltage-controlled
oscillator (VCO) and an edge-triggered-type phase frequency detector (PFD). The oscillation frequency range
of the VCO is set by an external bias resistor (RBIAS). The high-speed PFD with internal charge pump detects
the phase difference between the reference frequency input and signal frequency input from the external
counter. Both the VCO and the PFD have inhibit functions that can be used as a power-down mode. With the
high-speed and stable VCO characteristics, the TLC2933 is well sUited for use in high~performance PLL
systems.

functional block diagram
FIN-A
FIN-B
PFDINHIBIT

4
5

9

VCOIN
Phase
Frequency
Detector

6

BIAS
PFDOUT VCOINHIBIT
TEST

12
13
10
2

VoltageControlled
Oscillator

3

VCOOUT

AVAILABLE OPTIONS
PACKAGE
TA

SMALL OUTLINE
(PW)

-20'C to 75'C

TLC2933PWLE

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright © 1997, Texas Instruments Incorporated

5-41

TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A-APRIL 1996- REVISED JUNE 1997

Terminal Functions
TERMINAL

I/O

DESCRIPTION

13

I

Bias supply. An external resistor (RBIAS) between veo VDD and BIAS supplies bias for adjusting the
oscillation frequency range.

FIN-A

4

I

Input reference frequency f(REF IN) is applied to FIN-A.

FIN-B

5

I

Input for veo external counter output frequency f(FIN-B). FIN-B is nominally provided from the external
counter.

NAME
BIAS

NO.

LOGleGND

7

Ground for the internal logic.

LOGICVDD

1

Power supply for the internal logic. This power supply should be separate from veo VDO to reduce
cross-coupling between supplies.

Ne

8

PFD INHIBIT

9

I

PFD inhibit control. When PFD INHIBIT is high, PFD OUT is in the high-impedance state, see Table 2.

PFDOUT

6

0

PFD output. When the PFD INHIBIT is high, PFD OUT is in the high-impedance state.

2

I

TEST
VeOGND

11

VeOIN

12

veo INHIBIT

No internal connection.

Test terminal. TEST connects to ground for normal operation.
Ground for veo.

I

VCO control voltage input. Nominally the external loop filter output connects to veo IN to control veo
oscillation frequency.

10

I

VCO inhibit control. When veo INHIBIT is high, veo OUT is low (see Table 1).

VeOOUT

3

0

veo output. When veo INHIBIT is high, veo OUT is low.

veOvDD

14

Power supply for veo. This power supply should be separated from LOGIC VDD to reduce cross-coupling
between supplies.

detailed description

veo oscillation frequency
The veo oscillation frequency is determined by an external resistor (RSIAS) connected between the veo VDD
and the BIAS terminals. The oscillation frequency and range depends on this resis.tor value. While all resistor
values within the specified range result in excellent low temperature coefficients, the bias resistor value for the
minimum temperature coefficient is nominally 2.2 k,Q with 3-V VDD and nominally 2.4 kQ with 5-V VDD. For the
lock frequency range refer to the recommended operating conditions. Figure 1 shows the typical frequency
variation and veo control voltage.
VCO Oscillation Frequency Range

1/2VDD
VCO Control Voltage (VCO IN)

Figure 1. veo Oscillation Frequency

~TEXAS
5-42

I

INSTRUMENTS
•

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2933
HIGH·PERFORMANCE PHASE·LOCKED·LOOP
SLAS136A-APRIL 1996 - REVISED JUNE 1997

VCO inhibit function
The veo has an externally controlled inhibit function which inhibits the veo output. A high level on the veo
INHIBIT terminal stops the veo oscillation and powers down the veo. The output maintains a low level during
the power-down mode as shown in Table 1.

Table 1. VCO Inhibit Function
VCOINHIBIT

VCO OSCILLATOR

VCOOUT

Low

Active

Active

IDD(VCO)
Normal

High

Stopped

Low level

Power Down

PFD operation
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN-A and FIN-B as shown in Figure 2. Nominally the
reference is supplied to FIN-A, and the frequency from the external counter output is fed to FIN-B. For clock
recovery PLL systems, other types of phase detectors should be used.
FIN-A

FIN-B

VOH
PFDOUT
Hi-Z
VOL

Figure 2. PFD Function Timing Chart
PFD inhibit control
A high level on the PFD INHIBIT terminal places PFD OUT in the high-impedance state and the PFD stops
phase detection as shown in Table 2. A high level on the PFD INHIBIT terminal can also be used as the
power-down mode for the PFD.

Table 2. VCO Output Control Function
PFDINHIBIT

DETECTION

PFDOUT

Low

Active

Active

IDDCPFDI
Normal

High

Stopped

Hi-Z

Power Down

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5--43

TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A - APRIL 1996 - REVISED JUNE 1997

schematics
VCO block schematic

VCOOUT

PFD block schematic

r-ch&rg;"p;;;p-,
I
I

VDD

FIN-A

I
I
I
I
PFDOUT

FIN-B

I
I
I
IL _ _ _ _ _ __
_ .JI

PFDINHIBIT

absolute maximum ratingst
Supply voltage (each supply), Voo (see Note 1) ................................................ 7 V
Input voltage range (each input), VI (see Note 1) ............................... -0.3, V to Voo + 0.3 V
Input current (each input), II .............................................................. ±20 mA
Output current (each output), 10 .......................................................... ±20 mA
Continuous total power dissipation at (or below) TA = 25°C (see Note 2) ....................... 700 mW
Operating free-air temperature range, TA ............................................ -20°C to 75°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network ground terminal.
2. For operation above 25°C free·air temperature, derate linearly at the rate of 5.6 mW/oC.

5-44

-!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC2933
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS136A- APRIL 1996 - REVISED JUNE 1997

recommended operating conditions

Supply voltage, VOO (each supply, see Note 3)

MIN

NOM

MAX

VOO=3V

2.85

3

3.15

VOO=5V

4.75

5

5.25

Input voltage, VI (inputs except vce IN)

0

eutput current, 10, (each output)

0

VCO control voltage at VCO IN

VOO
±2

1

Lock frequency
Bias resistor, RBIAS

VOO=3V

37

VOO
55

VOO= 5V

43

100

VOO=3 V

1.8

2.7

VOO=5V

2.2

3

NeTE 3: It is recommended that the logic supply terminal (LeGIC VOO) and the
separated from each other.

UNIT

V
V
rnA

V
MHz
kO

vce supply terminal (VCO VOO) be at the same voltage and

electrical characteristics over recommended operating free-air temperature range, VDD
(unless otherwise noted)

=3 V

VCOsectlon
TEST CONDITIONS

PARAMETER

VeH

High-level output voltage

IOH=-2mA

VOL

Low-level output voltage

leL=2mA

VIT+

Positive input threshold voltage at TEST, VCO INHIBIT

II

Input current at TEST, vce INHIBIT

VI = VOO or ground

Zi(VCeIN\

Input impedance at VCO IN

vco IN = 1/2 VOO

IOO(lNH)

vce supply current (inhibit)

See Note 4

MIN

TYP

MAX

0.9

UNIT

V

2.4
1.5

0.3

V

2.1

V

±1
10
0.01

I1A
MO

1

I1A

VCO supply current
5.1
15
mA
See Note 5
IOO(VCO)
NeTES: 4. The current Into vce VOO and LeGIC VOO when
INHIBIT = VOO and PFO INHIBIT IS high.
5. The current into VCO VOO and LOGIC VOO when VCO IN = 1/2 VOO, RBIAS = 2.4 kg, VCO INHIBIT = ground, and PFO INHIBIT
is high.

vce

PFD section
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

VeH

High-level output voltage

IOH =-2 mA

VOL

Low-level output voltage

IOL=2 mA

0.2

V

lez

High-impedance-state output current

PFO INHIBIT = high,
VI = VOO or ground

±1

I1A

0.9

V

VIH

High-level input voltage at FIN-A, FIN-B

VIL

Low-level input voltage at FIN-A, FIN-B

2.7

V

2.1

VIT+

Positive input threshold voltage at PFO INHIBIT

Ci

Input capacitance at FIN-A, FIN-B

0.9

1.5

2.1

5

Zi

Input impedance at FIN-A, FIN-B

IOO(~

High-impedance-state PFO supply current

MO

10
See Note 6

0.01

V
pF

1

I1A

mA
See Note 7
0.7
4
IOO(PFO) PFO supply current
..
NOTES: 6. The current Into LOGIC VOO when FIN-A and FIN-B = ground, PFO INHIBIT = VOO, PFO OUT open, and
OUT IS inhibited.
7. The current into LOGIC VOO when FIN-A and FIN-B = 30 MHz (VI(PP) = 3 V, rectangular wave), PFO INHIBIT = GNO, PFO OUT
open, and veo OUT is inhibited.

vce

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-45

TLC2933
HIGH-PERFORMANCE PHASE.LOCKED LOOP
SLAS136A - APFUL 1996 - REVISED JUNE 1997

operating characteristics over recommended operating free-air temperature range, VDD
(unless otherwise noted)

=3 V

VCOsection
PARAMETER

TEST CONDITIONS

fosc

Operating oscillation frequency

HBIAS = 2.4 kg, VCO IN = 1/2 VDD

ts(fosc)

Time to stable oscillation (see Note 8)

Measured from VCO INHIBITt

tr

Rise time, VCO OUTt

CL = 15 pF,

See Figure 3

tf

Fall time, VCO OUTt

CL = 15 pF,

See Figure 3

Duty cycle at

veo OUT

RBIAS = 2.4 kg, VCO IN = 1/2 VDD

MAX

UNIT

48

55

MHz

10

~s

3.3

10

ns

2

8

ns

50%

55%

45%

0.03

%JoC

Supply voltage coefficient of oscillation frequency

RBIAS = 2.4 kQ, VCO IN = 1.5 V,
VDD = 2.85 Vto 3.15 V

0.04

%/mV

Jitter absolute (see Note 9)

RBIAS = 2.4 kQ

100

ps

\

kSVS(fosc)

TYP

38

RBIAS = 2.4 kg, VCO IN = 1/2 VDD,
TA = -20°C to 75°C

Temperature coefficient of oscillation frequency

Ot(fosc)

MIN

NOTES: 8. The time period to stabilize the VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
9. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with
a carefully designed printed circuit board (PCB) with no device socket.

PFD section
PARAMETER

TEST CONDITIONS

f max

Maximum operating frequency

tpLZ

Disable time, PFD INHIBITI to PFD OUT Hi-Z

tPHZ

Disable time, PFD INHIBITt to PFD OUT Hi-Z

tPZL

Enable time, PFD INHIBITt to PFD OUT low

tpZH

Enable time, PFD INHIBITt to PFD OUT high

tr

Rise time, PFD OUTt

tf

Fall time, PFD OUTt

TVP

MAX

20

40

See Figures 4 and 5 and Table 3

18

40

CL = 15 pF,

See Figure 4

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT
MHz

30

~TEXAS

&-46

MIN

ns

4.1

18

4.8

18

3.1

9

ns

1.5

9

ns

ns

TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A - APRIL 1996 - REVISED JUNE 1997

electrical characteristics over recommended operating free-air temperature range, VDD = 5 V
(unless otherwise noted)

veo section
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

'OH=-2mA

VOL

Low-level output voltage

'OL= 2 mA

VIT+

Positive input threshold voltage at TEST, veo INHIBIT

MIN

TYP

MAX

4.5

1.5

UNIT

V

2.5

0.5

V

3.5

V

Input current at TEST, veo INHIBIT

V, = VDD or ground

Zi(VeO IN)

"

Input impedance at veo IN

veo IN = 1/2 VDD

IDD(INH)

veo supply current (inhibit)

See Note 4

0.01

1

I!A

IDD(VeO)

veo supply current

See Note 5

14

35

mA

NOTES:

±1

itA
MQ

10

4. The current into veo VDD and LOGIC VDD when veo INHIBIT = VDD, and PFD INHIBIT high.
5. The current into veo VDD and LOGIC VDD when veo IN = 1/2 VDD, RBIAS = 2.4 kQ, veo INHIBIT = ground, and PFD INHIBIT
high.

PFD section
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

IOH = 2 mA

VOL

LOW-level output voltage

'OL= 2 mA

0.2

V

IOZ

High-impedance-state output current

PFD INHIBIT = high,
V, = VDD or ground

±1

I!A

V,H

High-level input voltage at FIN-A, FIN-B

V,L

LOW-level input voltage at FIN-A, FIN-B

V'T+

Positive input threshold voltage at PFD INHIBIT

ei

Input capacitance at FIN-A, FIN-B

V

3.5
1.5
1.5

2.5

3.5

7

Zi

Input impedance at FIN-A, FIN-B

IDD(Z)

High-impedance-state PFD supply current

See Note 6

IDO(PFD)

PFD supply current

See Note 10

NOTES:

V

4.5

V
V
pF
MQ

10
0.Q1

1

I!A

2.6

8

mA

..

6. The current Into LOGIC VDD when FIN-A and FIN-B = ground, PFD INHIBIT = VDD, PFD OUT open, and veo OUT IS inhibited .
10. The current into LOGIC VDD when FIN-A and FIN-B = 50 MHz (VI(PP) = 3 V, rectangular wave), PFD INHIBIT = ground, PFD OUT
open, and veo OUT is inhibited.

~TEXAS'

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-47

TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A-APRIL 1996 - REVISED JUNE 1997

operating characteristics over recommended operating free-air temperature range, VDD
(unless otherwise noted)

=5 V

VCOsection
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

64

80

96

MHz

10

IlS

2.1

5

ns

1.5

4

ns

50%

55%

fosc

Operating oscillation frequency

RBIAS = 2.4 kil" VCO IN = 1/2 VDD

ts(fosc)

Time to stable oscillation (see Note 8)

Measured from VCO INHIBITi

tr

Rise time, VCO OUT!

CL= 15pF,

See Figure 3

tf

Fall time, VCO OUTi

CL= 15pF,

See Figure 3

Duty cycle at VCO OUT

RBIAS = 2.4 kQ, VCO IN = 1/2 VDD

ct(fosc)

Temperature coefficient of oscillation frequency

RBIAS = 2.4 kQ, VCO IN = 1/2 VDD,
TA = -20°C to 75°C

0.03

o/oI°C

kSVS(fosc)

Supply voltage coefficient of oscillation frequency

RBIAS = 2.4 kQ, VCO IN = 2.5 .V,
VDD ., 4.75 V to 5.25 V

0.02

O!oImV

Jitter absolute (see Note 9)

RBIAS = 2.4 kQ

100

ps

NOTES:

45%

"
8: The time penod to stabilize
the VCO oscillation frequency after the VCO INHIBIT terminal IS changed to a low level.
g. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with
a carefully designed printed circuit board (PCB) with no device socket.

PFD section
PARAMETER

TEST CONDITIONS

f max

Maximum operating frequency

tpLZ

Disable time, PFD INHIBIT! to PFD OUT Hi-Z

tpHZ

Disable time, PFD INHIBIT! to PFD OUT Hi-Z
Enable time, PFD INHIBITito PFD OUT low

tpZH

Enable time, PFD INHIBITito PFD OUT high

oun

Rise time, PFD

tf

Fall time, PFD OUT i

See Figures 4 and 5 and Table 3

CL = 15 pF, See Figure 4

~TEXAS

INSTRUMENTS
5-48

TYP

MAX

20

40

17

40

3.7

10

3.4

10

1.7

5

ns

1.3

5

ns

50

tPZL
tr

MIN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT
MHz
ns

ns

TLC2933
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS136A - APRIL 1996 - REVISED JUNE 1997

PARAMETER MEASUREMENT INFORMATION
VCOOUT

"1\:'0%

90{1
_ _..:1:.::,00:::.*,""I :
~

: tF-1:.:;0,*.:;.,--

J4-lr

~

j+--If

Figure 3. VCO Output Voltage Waveform

FIN-At

\

~

--------

:::

VDD

\

VbD
FIN-Bt

GND

--------

----------------GND

PFDINHIBIT

\.SO%

I

;..-.r

I

PFDOUT

:~ *- Ir
! } J 90%

GND
VDD

VDD
GND

I

I_I

IPHZ

I.....

r-

~ tpLZ

I

1f

...

\..,- - - - Hi·Z

I

GND

I
1_

90~' ~1<'o50-1Ti-%---S-0'l*'!-----------

S o % \ - - - - - VOH

__ ---:1:.::,0%:rt¥f SO%
I

\..=

SO%j

tpZL~

IpZH~

(a) PFD OUT Hi·Z Timing To and From a High Level
(see Figure S and Table 3)

VDD

Hi-Z
VOL

(b) PFD OUT Hi-Z Timing To and From a Low Level
(see Figure S and Table 3)

t FIN-A and FIN-B are for reference phase only, not for timing.

Figure 4. PFD Output Voltage Waveform
Table 3. PFD Output Test Conditions
PARAMETER

RL

CL

51

~

Open

Closed

Closed

Open

Test Point

T

VDD

51

IpZH
tpHZ
Ir
IpZL
tPLZ

f

1 kQ

DUT

PFDOUT

15 pF

tf

Figure 5. PFD Output Test Conditions

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-49

TLC2933
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS136A -APRIL 1996 - REVISED JUNE 1997

TYPICAL CHARACTERISTICS
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE

VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
90

v6 0 Jv

I

so I-R IAS=1.Sk!1

-20OC~

70

,..,......

90
:I:

:::;;
I

~~

40

to-- ~

./

~

70

:::J

60

..
[

~

LL

c

50

~

40

~

.(3

,~

III

o
o

30

I

20

~
~

.2

10
0.3 0.6 0.9 1.2 1.5 1.S 2.1 2.4 2.7
VCO IN - VCO Control Voltage - V

3

o

N

:I:

:::;;

70

RBIAS = 2.4 k!1

I

>-

..

60

C"

~

50

~

40

()

c

LL
C
0

III

0
0

c..>

>
I

:I:

~

I

:::;;

75°C

>c

=

A

RBIAS = 2.7 k!1

..

C"

50

~

.2

40

III

30

>

20

~
.(3

0
0
c..>

~20°C

I

~~

2sob-

A

~

~~'(

c

75°C

J ~

~

~

A

f-- I-""'"

()

III

.2

10

o
o

O.S 0.6 0.9 1.2 1.5 1.S 2.1 2.4 2.7
VCO IN - VCO Control Voltage - V

3

10

o
o

0.3

0.6 0.9

1.2

1.5

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

1.S 2.1

2.4

VCO IN - VCO Control Voltage - V

Figure 9

Figure 8

5-50

I

LL

()

III

.2

vo~Jv

70

:::J

V

:;;...-

80

60

()

V

30
20

N

-20°C

./

.(3

3

VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE

~v

:::J

~5'C

Figure 7

I~

I

25'C

0.3 0.6 0.9 1.2 1.5 1.S 2.1 2.4 2.7
VCO IN - VCO Control Voltage - V

VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE

vo1oJv

~

10

Figure 6

SO

~

~

V\

-20°C

r--

o

o

~

.2

25'C

20

o

-20~~

c

W

A

50

v6 Jv

I
0
so I- RBIAS = 2.2 k!1

N

/~V 75°C

60

30

V- I/-

2.7

3

TLC2933
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS136A- APRIL 1996 - REVISED JUNE 1997

TYPICAL CHARACTERISTICS
VCO OSCILLATION FREQUENCY

160
N

vs

VCO CONTROL VOLTAGE

VCO CONTROL VOLTAGE

V~O=~V

140 -

::t:
:ii

120

!

100

~~tr

RBIAS = 2.2 kQ

II..

~

80

~

60

0

75°C

(J

>

40

I

u

III

..P

20

,
/

~

C

'u

N

::t:
:ii

~

o
o

~

~
c

120

~
II..

100

0

~

80

0
0

60

>

40

'uIII

~

(J

I

u

.P
1

,

C

20

I I

0.5

1.5

2

2.5

3

3.5

4

4.5

~C
0.5

1

1.5

-2ioc./.

120

~

80

0

0

40

~

(J

>
I

~

..P

20

o

3

75°C

~

~

~

/

o

0.5

5

~'f'

120

20oc

I

~
c

~5°~

CD
:::I

100

0'

I!:!

II..

~

80

I:

0

~
~

60

III

0
0

(J

>

40

I

u

III

..P

I

20

5

~

~

~

/

,

~

~ \ I

75°C

P'

-20°C

o

1 1.5 2 2.5 3 3.5 4 4.5
VCO IN - VCO Control Voltage - V

J l....:::
A~

VOO=5V
RBIAS=3kQ

N

::t:
:ii

~C
I

4.5

3.5

VCO OSCILLATION FREQUENCY

~ ~2~oC
~

100

'i:i

2.5

140
VOO=5 V
RBIAS = 2.7 kQ

60

2

vs

C

~

4

1,1'

VCO CONTROL VOLTAGE

0'

I!:!

-

VCO CONTROL VOLTAGE

I

II..

75°C

vs
140

CD
:::I

~

Figure 11

VCO OSCILLATION FREQUENCY

N

«250C

VCO IN - VCO Control Voltage - V

Figure 10

:..
u
c

A

1==

I I

o
o

5

-20~

V

75 0C .....

VCO IN - VCO Control Voltage - V

::t:
::E

I

I
140 ~ RBIAS = 2.4 kQ

CD
:::I

75°C - I -

~

V~O=15 V

I

~~

CD
:::I

0

160

1_ 2001C / I--

I

I

~
c

VCO OSCILLATION FREQUENCY

vs

o

I
0.5

I
1 1.5 2 2.5 3 3.5 4 4.5
VCO IN - VCO Control Voltage - V

Figure 12

5

Figure 13

-!11
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-51

TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A-APRIL 1996 - REVISED JUNE 1997

TYPICAL CHARACTERISTICS
RECOMMENDED LOCK FREQUENCY
vs
BIAS RESISTOR

RECOMMENDED LOCK FREQUENCY
vs
BIAS RESISTOR

60.--------.--------~------__,

~
:;

VOO=3 V±5%
TA = -20°C to 75°C
55~~=--_+----_r----~

I

g

50~---_+------_+_-~~___;

~

,45 k : ; : - - - - _ + - - - - _ + _ - - - - - - ;

80

.9

I

I;

----

r---

-

'"-

35r------+------~------~

40

1.8

2.2

2.4

2.7

I;.;:;:x--

70

50

30~------~--------~------~

30
2.2

RBIAS - Bias Resistor - kg

2.4

MIN -

2.7

RBIAS - Bias Resistor - kO

Figure 14

Figure 15

~TEXAS

5-52

Voo = 5 V±5%
TA = -20°C to 75°C

60

~

J

100
90

!'l

1

110

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3

TLC2933
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS136A- APRIL 1996 - REVISED JUNE 1997

APPLICATION INFORMATION
gain of VCO and PFD
Figure 16 is a block diagram of the PLL. The
divider N value depends on the input frequency
and the desired veo output frequency according
to the system application requirements. The Kp
and Kv values are obtained from the operating
characteristics of the device as shown in
Figure 16. Kp is defined from the phase detector
VOL and VOH specifications and the equation
shown in Figure 16(b). Kv is defined from
Figures 8,9,10, and 11 as shown in Figure 16(c).
The parameters for the block diagram with the
units are as follows:

Kv : veo gain (rad/slV)

r-------------,I

I
f REF

(a)

-2lt

0

-It

2lt

It

fMAX

~--+-~_4~~VOH

Kp : PFD gain (V/rad)
Kf : LPF gain (VIV)
KN : countdown divider gain (1/N)

-ICC-+--t---t--f"'- VOL fMIN

external counter

~

When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.

Range of
Comparison

Kp =

J

VOH-VOL
4lt
(b)

/1
I

2lt(fMAX-fMIN)
KV = VIN MAX - VIN MIN
(c)

Figure 16. Example of a PLL Block Diagram

RBIAS
The external bias resistor sets the veo center frequency with 1/2 Voo applied to the veo IN terminal. For the
most accurate results, a metal-film resistor is the better choice but a carbon-composition resistor can also be
used with excellent results. A 0.22 J..lF capacitor should be connected from the BIAS terminal to ground as close
to the device terminals as possible.

hold-In range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
configurations shown in Figure 17 is as follows:
.
(1 )

Where
Kf (00) = the filter transfer function value at Ol =00

~TEXAS

INSTRUMENTS
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5-53

TLC2933
HIGH·PERFORMANCE PHASE-LOCKED LOOP
SLAS136A-APRIL 1996- REVISED JUNE 1997

APPLICATION INFORMATION

low-pass-filter (LPF) configurations
Many excellent references are available that include detailed design information about LPFs and should be
consulted for additional.information. Lag-lead filters or active filters are often used. Examples of LPFs are shown
in Figure 17. When the active filter of Figure 17(c) is used, the reference should be applied to FIN-8 because
of the amplifier inversion. Also, in practical filter implementations, C2 is used as additional filtering at the VCO
input. T~e value of C2 should be equal to or less than one tenth the value of C1.
R1
VI -A./V'v---.--_- Vo

R1

VI~VO
T1 =C1R1

I

T1 = C1R1
T2 = C1R2

C1

VI

~'vV'v_---t

R.1
(a) LAG FILTER

>----Vo
T1 = C1R1
T2=C1R2

(b) LAG-LEAD FILTER
(e) ACTIVE FILTER

Figure 17. LPF Examples for PLL

the passive filter
The transfer function for the low-pass filter shown in Figure 17(b) is;
Vo
V IN

=1+

1+s.T2
s • (T1 + T2)

= R1

• C1 and T2

(2)

where
T1

= R2

• C1

Using this filter makes the closed-loop PLL system a type 1 second-order system. The response curves of this
system to a unit step are shown in Figure 18.

the active filter
When using the active filter shown in Figure 17(c), the phase detector inputs must be reversed since the filter
adds an additional inversion. Therefore, the input reference frequency should be applied to the FIN-8 terminal
and the output of the VCO divider should be applied to the input reference terminal, FIN-A.
The transfer function for the active filter shown in Figure 17(c) is:
F(s) = 1 + s • R2 • C1
s • R1 • C1

(3)

Using this filter makes the closed-loop PLL system a type 2 second-order system. The response curves of this
system to a unit step are shown in Figure 19.

~TEXAS

5-54

INSTRUMENTS.
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A-APRIL 1996 - REVISED JUNE 1997

APPLICATION INFORMATION
Using the lag-lead filter in Figure 17(b) and divider N value, the transfer function for phase and frequency are
shown in equations 4 and 5. Note that the transfer function for phase differs from the transfer function for
frequency by only the divider N value. The difference arises from the fact that the feedback for phase is unity
while the feedback for frequency is 1/N.

I

1 + s • T2
[ K p. K V· T2]

s

1 + N • (T1 + T2)

Hence, the transfer function of Figure 17(a) for phase is

1I>2(s)
Kp • KV
1I>1(s) = N· (T1 +T2)

2

+ s

(4)

K.K
P
V
+ N • (T1 + T2)

and the transfer function for frequency is

F OUT(s)

Kp • KV

FREF(s)

= (T1 + T2)

1 + s • T2
2
s

I

(5)

[ . Kp. Kv· T2]
Kp. KV
+ s· 1 + N • (T1 + T2) + N • (T1 + T2)

The standard 2-pole denominator is D =s2 + 2 ~ ron s + o>n 2 and comparing the coefficients of the denominator
of equation (4) and (5) with the standard 2-pole denominator gives the following results.
(6)

N • (T1 +T2)
Solving for T1 + T2
T1 + T2

Kp. KV

= -'---...;,

N • ro 2

n

and by using this value for T1 + T2 in equation (6) the damping factor is

~=

(7)

ron • (T2 + .,.,---.!.!.N-;-;-)
2
Kp • KV

solving for T2
T2 = 2 ~
0>

(8)

N
Kp. KV

then by substituting for T2 in equation (6)
.
KV • Kp
2 ~
N
T1 =
--+ .,.,---'--'-;-,,N • o>n2
O>n
Kp. KV

(9)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-55

TLC2933
HIGH·PERFORMANCE PHASE·LOCKED LOOP
SLAS136A- APRIL 1996- REVISED JUNE 1997

APPLICATION INFORMATION
From the circuit constants and the initial design parameters then

R2 -- [2
~
. ron R1
.

= [K p

N]1C1

(10)

Kp • KV

~+

• Kv _
ron 2 • N
ron

]...L
C1

N
Kp' KV

(11 )

The capacitor, C1, is usually chosen between 1 JlF and 0.1 JlF to allo,w for reasonable resistor values and
physical capacitor size.

~TEXAS

5-56

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A - APRIL 1996 - REVISED JUNE 1997

APPLICATION INFORMATION
1.9
1.8

I

I"'f-

1.7
1.6
1.5
1.4
~=0.6

I"

1.3

OJ

c

/ \ IF
/ .)\ r
II / \; ~r
II I I M~/

~

"-

1.1

rh

fh ~

0

Q.

OJ

c

OJ
CI
"0

.~

OJ

E

6
z

I

I

~ =0.3

I

~ =0.4
I

I

~ =0.5

/
II

.........

,r\
\
V--

-b

0.7
0.6

I

0.5

0.4 I - 0.3
0.2

j

1/

o

/.
V/

=1.01
I
~ = 1.5

/

\

~

J~~

I

'1// ~ ~ [\\. ,......."71 ri"-"
'U/ I;A I..;'"K r;r ~

II

0.8

o

I

\y

~

i

~

F--'

\

V/V(

-

\~ =::-

I..--- "\

I

0.9

0.1

~ =0.2

~ =O'J -\: // J K ~~
I
K ~\
=0.8

1.2

.
.
a:

~ = 0.1
I

II

I

\ II

Vf=2.0i
1
1

i
I

V

1
1
1
1

:
2

3

41
Olnts

5

=4.5

7

6

8

9

10

11

12

13

Olnt

Figure 18. Type 1 Second-Order Step Response

~TEXAS

INSTRUMENTS
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5-57

TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A-APRIL 1996- REVISED JUNE 1997

APPLICATION INFORMATION
1.9
1.8

/ Y

1.7

\/
Ir (Jt I
'r< V y:
h :\\
s:: ~ K/

1.6

,/

•

1.2

~

0

Q.

~

'A~

c

·ii

~

0.9

V/Il

0.8

z

0.7
0.6

flll9

0.5

'1I1IJ

!.

IV,

1

1; =0 .6

I

/ ~
// , \

1; =0.7

~

-~

~-

711

\

"

= 1.0

-I

~

1/
/ /

I
~

~
~

\'-. /

~

I~"R

~

'0

1
\'- /

1; =

../

0.4 111111
0.3

1; =0.5

~
.... ~~

/7l

II:

iii
E

I
I

~

1.1

c

e

I

1; =0.3

/""""

1.3

...,
...,

I
1; =0.2

~1;=0.4

1.5
1.4

1;=1

~

1111

0.2
0.1

o

o

2

3

4

5

7

6

8

9

ron!

Figure 19. Type 2 Second-Order Step Response

~TEXAS

5-58

INSTRUMENTS

'

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10

11

12

13

TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A- APRIL 1996 - REVISED JUNE 1997

APPLICATION INFORMATION
AVDD

VDD
VCO
LOGIC VDD (Digital)

-=REF IN

DGND

2

TEST

3

VCOOUT

4

FIN-A

5

FIN-B

14

VCOVDDI--------t

BIASI-1::...:3'-----.~...I\RV\1I\t..--J
VCOINI-1~2,--~----~-~~~vy-,
VCO GNDI-1::...:1----.
VCO INHIBIT 10
AGND
PFD INHIBIT 9

6 PFDOUT
7

Divide
By
N

LOGIC GND (Digital)

NC

8

DGND

R5

t

9

52
51- {
.--t--

R6

DGND

DVDD
RBIA5 resistor

Figure 20. Evaluation and Operation Schematic

PCB layout considerations
The TLC2933 contains a high frequency oscillator; therefore, very careful breadboarding and PCB layout is
required for evaluation.
.
The following design recommendations benefit the TLC2933 user:
•

External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.

•

Radio frequency (RF) breadboarding or RF PCB techniques should be used throughout the evaluation and
production process.

•

Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.

•

LOGIC Voo and VCO Voo should be separate PCB traces and connected to the best filtered supply point
available in the system to minimize supply cross-coupling.

•

VCO Voo to ground and LOGIC VOO to ground should be decoupled with a O.1-JlF capacitor placed as close
as possible to the appropriate device terminals.

•

The no-connection (NC) terminal on the package should be connected to ground to prevent stray pickup.

~TEXAS

INSTRUMENTS
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5-59

5-60

TL32088
DIFFERENTIAL ANALOG BUFFER AMPLIFIER
FOR THE TLC320AD58
•

Analog Front-End Integrated Circuit for the
18-Bit Stereo Audio Sigma-Delta Analog-toDigital Converter TLC320AD58C

•

Low Distortion, Low Noise
- THD+N .•. 0.00056% Typ
- SNR ••• 108-dB Typ

•
•
•
•

NSPACKAGE
(TOP VIEW)
REF L1
AVss
IN L+
IN LOUTL

Adjustable Signal Gain
5-V Single Supply Operation
Internal Voltage Reference
Operating Temperature ••• O°C to 70°C

3

14
13
12
11

FLTL 1
FLTL2
AOUT L1
AOUT L2

description

REF R1
IN R+
IN ROUTR
REF R
FLTR 1
FLTR2
AOUTR1
AOUT R2
AVec

The TL32088 is an analog signal conditioning
AVAILABLE OPTIONS
integrated circuit built using a proprietary Texas
PACKAGE
Instruments bipolar process. This device is used
TA
SMALL
OUTLINE
for the analog signal input stage for the 18-bit,
(NS)
stereo audio, sigma-delta, analog-to-digital
TL32088CNS
O°C to 70°C
converter (AD C) TLC320AD58C exclusively. The
TL32088 can convert input signals from
single-ended to differential and differential to
single-ended. The TL32088 also implements a single-ended to single-ended and differential to differential
amplifier buffer. The differential output can be connected to the TLC320AD58C directly. The TLC32088 is
composed of high performance amplifiers that offer wide output swing with low distortion and low noise. The
reference voltage for the internal amplifier circuit is provided from an internal voltage reference circuit.
The TL32088 provides a wide output swing while maintaining 0.00056% THD+N and 108-dB SNR and,
therefore, is ideally suited for high-end audio system~.

functional block diagram
OUTR

REFR

FLTR1

FLTR2

5kn

INRINR+

ROUT
AOUTR1
ROUT
AOUTR2
REFR1

LOUT

REFL1

AOUTL2
LOUT
AOUTL1

-::-

-::-

INL+
INL-

5kn
OUTL

=,~CTJ!:O~T:.==:.~~ ::Ie~~r':~'::s

ltandarel warranty. Production procesalng does not necessarily Inetude
lOllIng of 811 por811IeterI.

REFL

FLTL 1

~TEXAS

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FLTL2

Copyright © 1995, Texas Instruments Incorporated

5-61

TL32088
DIFFERENTIAL ANALOG BUFFER AMPLIFIER
FOR THE TLC320AD58
SLAS123B - MARCH 1995 - REVISED NOVEMBER 1995

absolute maximum rating over operating free-air temperature range (unless otherwise noted)t
Supply voltage, AVec (see Note 1) ............................................................ 7 V
Differential input voltage, VIO (see Note 2) .......................... , ........................ AVec
Input voltage range, VI (any input) (see Notes 1 and 3) .................................. -0.3 to AVec
Output voltage, Vo ................................................... , ............. -0.3 to AVec
Output current, 10 ........................................................................ 20 rnA
Duration of short-circuit current at or below 25°C (output shorted to GND) ..................... unlimited
Continuous total power dissipation,
(TA:S; 25°C) (see Note 4) .............................. 625 mW
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg ............................................ , ...... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C

Po

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods rnay affect device reliability.
NOTES: 1. All voltage values, except differential voltage, are with respect to GND.
2. Differential voltage is at the non inverting input with respect to the inverting input.
3. All input voltage values must not exceed VCC.
4. Derating factor above TA = 25°C is 10 mW/oC.

recommended operating conditions
Supply voltage, AVCC
Input voltage range, V, (see Note 5)
Operating free-air temperature, TA

MIN

NOM

MAX

UNIT

4.75

5

5.25

V

1.1

3.9

V

0

70

°c

NOTE 5: The output voltage IS undetermined when the Input voltage exceeds recommended Input voltage range.

electrical characteristics over recommended operating free-air temperature range,
(unless otherwise noted)
PARAMETER

TEST CONDITIONS

Via

Input offset voltage

V'C =2.5V,
Va = 2.5 V (AMP Ll, Rl)

',0

Input offset current

V'C = 2.5 V,
Va = 2.5 V (AMP L1, Rl)

liB

Input bias current

V'C =2.5 V,
Vo = 2.5 V (AMP L1, Rl)

V'C

Common-mode input voltage

Va ~7.5 mV'(AMP Ll, Rl}

TA = O°C to 70°C

TA = O°C to 70°C

S
100
150

20

150
250

TA = O°C to 70°C
TA=25°C

0.9

4.1

TA = DoC to 70°C

1.1

3.9

Maximum positive-peak output voltage
Maximum negative-peak output voltage

AVd

Differential voltage amplification

VO= 2.5V± 1 V (AMP Ll, Rl)

TA = 25°C

CMRR

Common-mode rejection ratio

Va = 2.5 V± 1 V (AMP Ll, Rl)

TA=25°C

Vref

Reference voltage

EG

Gain error

ro

Output resistance

O.S
SO

2.5

nA

nA

V

V

dB
2.S

V

±3%

See Note S

VO= 2.5 V,

mV

dB

85
2.4

UNIT

V

4.4

No load

TA= 25°C

50

TA = 25°C

17

TA = DoC to 70°C

NOTE S: Gain error IS between OUT Land FLTL 1, OUT Rand FLTR 1.

~TEXAS

5-62

MAX

1

5

TA=25°C

VOM+

Supply current (both channels)

TYP

7.5

TA = 25°C

VOM-

ICC

MIN

TA = 25°C

Vee."= 5 V

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

g
20
25

mA

TL32088
DIFFERENTIAL ANALOG BUFFER AMPLIFIER
FOR THE TLC320AD58
SLAS123B - MARCH 1995 - REVISED NOVEMBER 1995

operating characteristics over recommended operating free-air temperature range, VCC
(unless otherwise noted)
TEST CONDITIONS

PARAMETER
SR

MIN

AV= 1,
VI = 2.5 V + 0.5 V (AMP Ll, Rl)

Slew rate

Bl

Unity-gain bandwidth

AMP Ll, Rl

SNR

Signal-lo-noise ratio (EIAJ)

·A-Weighted test circuit (see Figure 2)

Total harmonic distortion plus noise

VO(PP) = 3.2 V 1=1 kHz,
BW = 10Hz to 20 kHz test circuit

THD+N

Crosstalk

VO(PP) = 3.2 V,

104

TYP

UNIT

3

V/Jls

7

MHz

108
0.00056%
-125

1= 20 kHz

MAX

=5 V

dB
0.001%
dB

APPLICATION INFORMATION

AVcc

r--------- ---------,I

I
I
1 I REF Ll

I

REF Rll 20

T

T
200 pF

I

I

91AOUTLl

AOUT Rl113

OUT~4---------~----~Arl~~

(INLP)t

10 AOUT L2 50 0

OUTL-4-------~~----~~------~

(INLM)t

L-~~~----~--------------'OUTR+

500AOUTR2112
(INRP)t
L-______~~----+-------------~ OUTR(INRM)t

t TLC320AD58C input terminals.

Figure 1. TL32088 to TLC320AD58C Connections

·~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-63

TL32088
DIFFERENTIAL ANALOG BUFFER AMPLIFIER
FOR THE TLC320AD58
SLAS123B - MARCH 1995 - REVISED NOVEMBER 1995

APPLICATION INFORMATION
Table 1. A-Weighted Data
FREQUENCY

A WEIGHTING (dB)

FREQUENCY

A WEIGHTING (dB)

25

-44.6±2

BOO

31.5

-39.2±2

1000

-0.1 ±1

40

-34.5±2

1250

0.6±1

50
63

-30.2±2

1600

1.0±1

-26.1 ±2

2000

1.2±1

80

-22.3±2

2500

1;2±1

100

-19.1 ±1

3150

1.2±1

125

-16.1 ±1

4000

1.0±1

160

-13.2±1

5000

200

-10.B±1

6300

0.5±1
-0.1 ±1

250

-B.6±1

BOOO

-1.1 ±1

315

-6.5±1

10000

-2.4 ±1

400

-4.B±1

12500

-4.2±2

500

-3.2±1

16000

-6.5±2

630

-1.9±1

-

-

O±O'

10

0

/

m -10

V

"CI

I

c

!

r'\

I

-20

:::I

c

~

-30

-40

I

V

/

-50
20

100
1k
Signal Frequency - Hz

10 k 20 k

Figure 2. A-Weighted Function

~TEXAS
5-64.

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-1

Contents
Page

TVP3026 : . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3
TVP3030: ................. ,: ............................................ '; .... 6-7
TVP3033: ........,......................... ; ................................. 6-11
TVP3409: ........................... '......... .'.............................. 6-13
TVP3703: .. : ............................................................... 6-15

<

0:,
CD

o

,..

':::J
CD

:::L

Q)

(')

CD

"tJ

C-D
,..
,..
Q)

CD

tn

6-2

TVP3026
VIDEO INTERFACE PALETTE
- REVISEO NOVEMBER 1997

•

Supports System Resolutions up to
1600 x 1280 at 76-Hz Refresh Rate

•

•

Supports Color Depths of 4-, 8~, 16-, 24-,
and 32-Bit/Pixel

•

•
•

Versatile Direct-Color Modes:
24-Bit/Pixel with 8-Bit Overlay

•

On-Chip Hardware Cursor, 64 x 64 x 2
Cursor (XGA and X-WindowTM Functionally
Compatible)

•
•

Direct Interfacing to Video RAM
Supports Overscan For Creation of Custom
Screen Borders

•

Color-Keyed Switching of Direct Color and
and True Color or Overlay

•

Hardware Port Select Switching Between
Direct Color and True Color or Overlay

•
•

Triple 8-Bit D/A Converters
Analog-Output Comparators for Monitor
Detection

•
•
•
•
•

RS-343A-Compatible Outputs
Direct VGA Pass-Through Capability
Palette-Page Register
Horizontal Zooming Capability
Data Manual Availablet

(0, R, G, B)
•
•
•
•

24-Bit/Pixel (R, G, B)
16-Bit/Pixel (5, 6, 5) XGATM Configuration
16-Bit/Pixel (6, 6, 4) Configuration
15-Bit/Pixel With 1-Bit Overlay (1,5,5,5)
TARGATM Configuration

•
•
•

12-Bit/Pixel With 4-Bit Overlay (4, 4, 4, 4)
True-Color Gamma Correction
Supports Packed Pixel Formats for
24-BitlPixel Using a 32- or 64-Bit/Pixel Bus

•

50% Duty Cycle Reference Clock for Higher
Screen Refresh Rates in Packecl-24 Modes

•

Programmable Frequency Synthesis
Phase-Locked Loops (PLL) for Dot Clock
and Memory Clock
Loop Clock PLL Compensates for System
Delay and Ensures Reliable Data Latching

•

Versatile Pixel Bus Interface Supports
Little- and Big-Endian Data Formats
135-, 175-, 220-, 230-, 250-, and 270-MHz
Versions

description

The TVP3026 is an advanced video interface palette (VIP) from Texas Instruments implemented in EPICTM
0.8-micron CMOS process. The TVP3026 is a 64-bit VIP that supports packed-24 modes enabling 24-bit true
color and high resolution at the same time without excessive amounts of frame buffer memory. For example,
a 24-bit true color display with 1280 x 1024 resolution may be packed into 4 megabytes of VRAM. A
PLL-generated, 50% duty cycle reference clock is output in the packed-24 modes, maximizing VRAM cycle time
and screen refresh rate.
The TVP3026 supports all of the pixel formats of the TVP3020 VIP. Data can be split into 4- or 8-bit planes for
pseudo-colOr mode or split into 12", 16- or 24-bit true-color and direct-color modes. For the 24-bit direct color
modes, an 8-bit overlay plane is available. The 16-bit direct- and true-color modes can be configured to IBMTM
XGA (5,6,5), TARGA (1,5,5,5), or (6,6,4) as another existing format. An additional 12-bit mode (4, 4, 4, 4)
is supported with 4 bits for each color and overlay. All color modes support selection of little- or big-endian data
format for the pixel bus. Additionally, the device is also software compatible with the IMSG176/8 and 8t476/8
color palettes.

t For the complete data manual, refer to the Graphics and Imaging Data Book (SLAD002).
IBM is a trademark of International Business Machines Corporation.
EPIC is a trademark of Texas Instruments Incorporated.
XGA is a trademark of IBM.
TARGA is a trademark of Truevision Incorporated.
X-Windows is a trademark of Massachusetts Institute of Technology.

~TEXA.S

INSTRUMENTS
POST OFFICE' BOX 655303 • DALLAS. TEXAS 75265

Copyright © 1997, Texas Instruments Incorporated

6'-3

TVP3026
VIDEO INTERFACE PALETTE
XLAS098B - MAY 1995 ~ REVISED NOVEMBER 1997

description (continued)
Two fully programmable Plls for pixel clock and memory clock functions are provided, as weir as a simple
frequency doubler for dramatic improvemel\ts in graphics system cost and integration. A third loop clock Pll
is in90rporated, making pixel data latch timing much simpler than with other existing color palettes. In addition,
four digital clock inputs (two TIl- and two ECL/TIl-compatible) can be used and are software selectable. The
video clock provides a software-selected divide ratio of the chosen pixel clock. The shift clock output can be
used direCtly as the VRAM shift clock. The reference clock output is driven by the loop clock Pll and provides
a timing reference to the graphics accelerator.
Like the TVP3020, the TVP3026 also integrates a complete, IBM XGA-compatible hardware cursor on chip,
making significant graphics performance enhancements possible. Additionally, hardware port select and
color-keyed switching functiDns allow the user several options for producing graphical overlays on direct-color
backgrounds.
The TVP3026 has three 256-by-8 color lookup tables with triple, 8-bit video, digital-to-analog converters (DACs)
capable of directly driving a doubly terminated, 75-0 line. The lookup tables are designed with a dual-port RAM
architect!,Jre that enables ultra-high speed operation. Sync generation is incorporated on the green output
channel. Horizontal sync (HSYNC) and vertical sync (VSYNC) are pipeline delayed through the device and
optionally inverted to indicate screen resolution to the monitor. A palette-page register is available to select from
multiple color maps in RAM when 4 bit planes are used. This allows the screen colors to be changed with only
one microprocessor write cycle.
The device features a separate VGA bus that supports the integrated VGA modes in graphics accelerator
applications, allowing efficient support for VGA graphics and text modes. The separate bus also is useful for
accepting data from the feature connector of most VGA-supported personal computers, without the need for
external data multiplexing.
i

The TVP3026 is highly system integrated. It can be connected to the serial port of VRAM devices without
external buffer logic and connected to many graphics engines directly. It also supports the split shift-register
transfer function, which is common to many industry standard VRAM devices.
The system-integration concept is even carried further to manufacturing test and field diagnosis. To support
these, several highly integrated test functions have been designed to enable simplified testing of the palette and
the entire graphics system.
AIiAILABLE OPTIONS
PACKAGE
TA

O°C to 70°C

-55°C to 125°C

SPEED

DAC
RESOLUTION

CERAMIC
FLAT PACK
(HFG)

METAL QUAD
FLAT PACK
(MDN)

-

220 MHz

8 Bits

230 MHz

8 Bits

-

250 MHz

8 Bits

-

270 MHz

8 Bits

-

TVP3026-270MDN

-

175 MHz

8 Bits

TVP3026-175MHFG

-

-

135 MHz

8 Bits

175 MHz

8 Bits

~1ExAs

INSTRUMENTS
6-4

PLASTIC QUAD
FLAT PACK
(PCE)

POST OFFICE BOX 655303 • DALLAS. TEXAS· 75265

TVP3026-135PCE
TVP3026-175PCE
TVP3026-220PCE
TVP3026-230PCE
TVP3026-250PCE

TVP3026
VIDEO INTERFACE PALETTE
XLAS098B - MAY 1995 - REVISED NOVEMBER 1997

functional block diagram
REF
FSADJUST

'-11""<.,----

COMP2

....----11.-"""--,---

COMP1

P(63-0)

LCLK

lOR

lOG

VGA(7-0)

lOB

SENSE

I

Video-Signal
Control

HSYNCOUT
VSYNCOUT

~1ExAs

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-5

6-6

TVP3030
VIDEO INTERFACE PALETTE
XLASlllA-MAY

•
•
•
•

Supports System Resolutions up to
1600 x 1280 at 86-Hz Refresh Rate
Supports Color Depths of 4, 8, 16, 24, and
32 Bit/Pixel, All at Maximum Resolution
128-Bit-Wide Pixel Bus
Versatile Direct-Color Modes:
- 24-BitlPixel with 8-Bit Overlay

•
•
•

•

(0, R, G, B)

•
•

•
•
•

-

24-Bit/Pixel Packed-24 (R, G, B)
16-Bit/Pixel (5, 6, 5) XGA Configuration
16-Bit/Pixel (6, 6, 4) Configuration
15-Bit/Pixel With 1-Bit Overlay (1,5,5,5)
TARGA Configuration
- 12-Bit/Pixel With 4-Bit Overlay (4, 4, 4, 4)

•
•

True-Color Gamma Correction
Supports Packed Pixel Formats for 24
Bit/Pixel Using a 32-, 64-, or 128-Bit/Pixel
Bus
50% Duty Cycle Reference Clock for Higher
Screen Refresh Rates in Packed-24 Modes
Programmable Frequency Synthesis PLLs
for Dot Clock and Memory Clock
Loop Clock PLL Compensates for System
Delay and Ensures Reliable Data Latching

•

•

•
•
•
•
•
•
•

- REVISED NOVEMBER 1997

Versatile Pixel Bus Interface Supports
Little-Endian and Big-Endian Data Formats
175-,220- and 250-MHz Versions
On-Chip Hardware Cursor, 64 x 64 x 2
Cursor (XGA and X-Windows Functionally
Compatible)
Byte Router Allow.s Use of R, G, or B
Direct-Color Channels Individually
Direct Interfacing to Video RAM
Overscan for Creation of Custom Screen
Borders
Color-Keyed Switching of Direct Color and
True Color or Overlay
Triple 8-Bit Digital-to-Analog (D/A)
Converters
Analog Output Comparators for Monitor
Detection
RS-343A Compatible Outputs
Direct VGA Pass-Through,Capability
Palette-Page Register
Horizontal Zooming Capability
EPIC 0.8-llm CMOS Process
Data Manual Availablet

description
The TVP3030 is an advanced video interface palette (VIP) from Texas Instruments implemented in EPICTM
0.8-micron CMOS process. The TVP3030 is a 128-bit VIP that provides virtually all features of the 64-bit
TVP3026. The TVP3030 doubles the pixel bus bandwidth, enabling 24-bitlpixel displays at resolutions up to
1600 x 1280 at a 76-Hz refresh rate. Also, 24-bit/pixel graphics at 1280 x 1024 resolution may be implemented
at higher refresh rates with or without the use of pixel packing.
With the wider pixel bus comes additional 24-bitlpixel multiplexing modes: 4:1 (128-bit bus width for overlay and
red-green-blue (RGB)) and 5:1 (120-bit bus width for RGB). The byte router function allows pseudo-color or
monochrome image data to be taken from the red, green, or blue color channels. This enables high performance
24-bitlpixel architectures organized as red, green, and blue memory banks to provide 8-bitlpixel modes as well.
The TVP3030 extends the packed-24 modes to include 16:3 (pixels:load clocks) using a 128-bit pixel bus width.
For example, this enables 24-bitlpixel graphics at 220 MHz pixel rate with only a 40 MHz VRAM serial output.
With the 8:3 packed-24 mode (64-bit pixel bus width), a 24-bitlpixel display with 1280 x 1024 resolution may
be packed into 4 megabytes of VRAM. A PLL-generated, 50% duty cycle reference clock is output in the
packed-24 modes, maximizing VRAM cycle time.

t For the complete data manual, refer to the Graphics and Imaging Data Book (SLAD002).
EPIC is a trademark of Texas Instruments Incorporated.
XGA is a trademark of International Business Machines Corporation.
TARGA is a trademark of Truevision Incorporated.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

Copyright © 1997, Texas Instruments Incorporated

6-7

TVP3030
VIDEO INTERFACE PALETTE
XLASlllA- MAY 1995- REVISED NOVEMBER 1997

description (continued)
The TVP3030 supports all of the pixel formats of the TVP3026 VIP. Data can be split into 4-bit or 8-bit planes
for pseudo-color mode or split into 12-, 16- or 24-bit true-color and direct-color modes. For the 24-bit direct color
modes, an 8-bit overlay plane is available: The 16-bit direct- and true-color modes can be configured to IBM
XGA® (5, 6, 5), TARGA® (5, 5, 5, 1), or as another (6,6,4) existing format. An additional 12-bit mode (4, 4, 4,
4) is supported with 4 bits for each color and overlay. All color modes support selection of little-endian or
big-endian data format for the pixel bus. Additionally, the device is also software compatible with the INMOSTM
IMSG176/8 and Brooktree™ Bt476/8 color palettes.
Two fully programmable phase-locked loops (PLLs) for pixel clock and memory clock functions are provided
for dramatic improvements iri graphics system cost and integration. A third loop clock PLL is incorporated
'making pixel data latch timing much simpler than with other existing color palettes. In addition, an external digital
clock input is provided for VGA modes. The reference clock output is driven by the loop clock PLL and provides
a timing reference to the graphics accelerator. The shift clock output may be used directly as the VRAM shift
clock.
Like the TVP3026, the TVP3030 also integrates a complete, IBM XGA-compatible hardware cursor on chip,
making significant graphics performance enhancements possible. Additionally, color-keyed switching is
provided, giving the user an efficient means of combining graphic overlays and direct-color images on screen.
The TVP3030 has three 256 x 8 color look-up tables with triple 8-bit video digital-to-analog converters (DACs)
capable of directly driving a doubly terminated 75-0 line. The look-up tables are designed with a dual-ported
RAM architecture that enables ultra-high speed operation.
The device features a separate VGA bus that supports the integrated VGA modes in graphics accelerator
applications, allowing efficient support for VGA graphics and text modes. The separate bus is also useful for
accepting data from the feature connector of most VGA-supported personal computers, without the need for
external data mUltiplexing.
The TVP3030 is a highly integrated system. It can be connected to the serial port of VRAM devices without
external buffering and connected to many graphics engines directly. It also supports the split-shift register
transfer operation, which is common to many industry standard VRAM devices. To aid in manufacturing test and
field diagnosis, several highly integrated test functions have been designed to enable simplified testing of the
palette and the entire graphics' subsystem.
AVAILABLE OPTIONS
PACKAGE

TA

SPEED

DAC
RESOLUTION

175 MHz

8 Bits

TVP3030-1l5PPA

-

ooe to looe

220 MHz

8 Bits

TVP3030-220PPA

-

250 MHz

8 Bits

-

TVP3030-250MEP

FLAT PACK
(PPA)

~TEXAS

INSTRUMENTS
6-8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FLAT PACK
(MEP)

TVP3030
VIDEO INTERFACE PALETTE
XLAS111A-MAY 1995- REVISED NOVEMBER 1997

functional block diagram

P127·PO
LCLK

VGA7-VGAO

07·DO

RS3-RSO

liD
WR

MPU
Registers

and
Control
Logic

Internal
Dol Clock

Ii

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-9

TVP3030
VIDEO INTERFACE PALETTE
XLAS111A-MAY 1995- REVISED NOVEMBER 1997

functional block diagram (continued)
REF
FSADJUST

f--------- COMP2
I---~'----- COMP1

24

24

..........-+-1

DAC}-4II----- lOR

H ....- - - I O G

>-Ir+,,--IOB

Test Function
and
Sense Comparator

Video Signal
Control

and Control

I~ I~

II

~TEXAS

6-10

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

HSVNCOUT
VSVNCOUT

TVP3033
VIDEO INTERFACE PALETTE
•
•
•
•
•
•
•

•

Supports System Resolutions up to 1600 x
1280 at 86-Hz Refresh Rate
RGB Color Depths of 8,16,24, and 32
Bits/Pixel, All At Maximum .Resolution
Programmable Color Space Conversion
Supports Interpolation for VGA Modes
Supports RGB, YUV, and Mixed Modes
128-Bit Pixel Bus for Shared Frame Buffer
Applications
Supports Dual, Independent 64- or 32-Bit
Pixel Ports for Separate Frame Buffer
Applications
RGB modes:
- 24-Bit/Pixel With 8-Bit Overlay
- 24-BitlPixel Packed-24
, - 16-Bit/Pixel XGA Configuration (5-6-5)
- 15-Bit/Pixel With 1-Bit Overlay (1-5-5-5)
- 15-Bit/Pixel Double Buffered (5-5-5)
- 12-Bit/Pixel Double Buffered (4-4-4)

•

YUVModes:
- 24-Bit/Pixel 4:4:4 Format
- 16-Bit/PixeI4:2:2 Format

•

Mixed Modes:
- 24-Bit YUV 4:4:4 and 8-Bit Overlay
- 12-Blt YUV 4:1:1 and 4-Bit Overlay
- 24-Bit Tagged YUV/RGB
- 15-Bit Tagged YUV/RGB
- 16-Bit YUV and 8-Bit Overlay + Luma-Key

•
•
•

Gamma Correction for RGB or YUV Modes
Hardware Cursor
Programmable Window Output Controls
Pixel Data Flow From Second Frame Buffer

•
•
•

Supports WRAM Applications
175-, 220-, and 250-MHz Versions
Power-Saving 3.3-V Supply Operation With
5-V Tolerant I/O
Programmable Frequency Synthesis PLLs
for Dot Clock and Memory Clock
Two Sync PLLs to Compensate for System
Delay and Ensure Reliable Data Latching
Color and Luminance Keying
- 64 x 64 x 2 Cursor RAM
- XGA and X-Windows Functional
Compatible
Versatile Pixel Bus Interface Supports
Little- and Big-Endian Data Formats
Triple 8-Bit Monotonic D/A Converters
Analog Output Comparators for Monitor
Detection
RS-343A Compatible Outputs
Direct VGA Pass-Through Capability
Palette Page Register
Horizontal Zooming Capability
EPIC 0.72 mm CMOS Process

•
•
•

•
•
•
•
•
•
•
•

description
The TLV3033 128-bit RAMDAC is a performance-enhanced version of the TVP3026 64-bit RAMDAC. By
operating at high frequencies and integrating a wider pixel bus, the TVP3033 provides more colors at higher
resolutions. Intended for 4M-byte to· 8M-byte, VRAM-based high-end PC graphics systems, the TVP3033
supports speeds of 175-MHz, 220-MHz, and 250-MHz, enabling 24-bit true color (16.7 million colors) at 1600
x 1280 resolution at 86-Hz refresh rate. The TVP3033 is highly integrated with high-speed triple 8-bit DACs,
three 256-x-8 color lookup tables, a 64 x 64 x 2 hardware cursor, and a programmable pixel multiplexing
interface. The TVP is available in a 208-pin QFP package and is characterized from TA = O°C to 70°C.

t For the complete data manual (SLASI49). contact your local TI sales office.
EPIC is a trademark of Texas Instruments Incorporated.
XGA is a trademark of IBM.
X-Window is a trademark of the Massachusetts Institute of Technology

~=~~~: .';!:r="ns~e':U::':!r::: Ie=::~=s

standard warranty. Production processing does not necessarily include
testing of all parameters.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75265

Copyright © 1996, Texas Instruments Incorporated

6--11

0>

.!.. '

'"

I

-

5_

x
t;
~
...

ID

~

C

0" ':'Z
:::I

COMP2
COMP1

I..MU~. I" I

lClKB--++I>

P(127-o)

~

I:;:'~ I

I

:!l2
~-~
~ en !!!oO. I

!i~~
~~ .

........

lunDOCk.rl

lClKA~;;.

1"""'''''''1

A

I

1'-"Jl1C1

""

I

I

8

I~~I

24/-.1

0(7-0)

RS(~-4<+I~rsJ I

_---+I c;o~1

WR

RESET

/

1

Clock Select \.

ClKO ClK1

~-

.__.

I I;'

"I,

V

II....,....., I

~

AMUXCTl

--

~ ~DAC~

TPI

~

I '"

UaJ

IT I~ I 1+
tt
I ~ I.

RClKB

~

MAN<

I

lOR

~ 8. w.;.t../DAC~ lOG

~ ~Ac~IOB

RCLKA
MCLK

V.deo~~

t: ~~~gg~

T
I

T
I

Window Genemtor

OOOIEVEN

PSEl

HSYNCVS~NCBlANK

. WINDOW

C"'U
m--~

00
_c.,)
Z

~

:l:J

.."

)IIi

0

m
~
r-

:3

;~
~

Co

<0

~

- I D ;

~rn{ll

'"

n

~
III
:rJ

i"
co

~RGBI

.-~

a:0'

<-I
<

m

I

~

c.,)

TVP3409
VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC
XLAS092A - MAY 1995 - REVISED NOVEMBER 1

•
•

•

•
•
•

•

On-Chip PLL Clock Doubler
- 85 MHz Input
- 170 MHz Pixel Output

•
•

256 x 24 Color RAM
Software Compatible With the AT&T
ATT20C498/499/409

•

68-Terminal Plastic Leaded Chip Carrier
(PLCC) Package

•

Data Manual Availablet

Functionally Interchangeable With
ATT20C409
170/135 MHz (0.8 ~m CMOS)
- 170 MHz 2:1 Multiplex 8-Bit Pseudocolor
- 73 MHz True-Color
• 16-Bit Pixel Port, Usable as an 8-Bit Port
- Compatible With ATT20C490Using P(7-0)
- Compatible With ATT20C498 Using
P(15-0)

applications

9 Software-Selectable Color Modes
- 24-Bit Packed Pixels
- 24-Blt True Color
- 8-Bit Pseudocolor

•

2:1 and 1:1 Pixel Multiplexing
Power DisSipation of 1.19 Wat 135 MHz Typ
Dual Programmable Clock Synthesizers
- Pixel Clock and Memory Clock
- Reset to 28.322-MHz and 25.175 MHz
VGA Frequencies
- Strobe Input Latches Frequency Select
Lines

•

Screen Resolutions (non interlaced)
- 1600 x 1280, 8-Bit/Pixel, 60 Hz
- 1280 x 1024, 16-Bit/Pixel, 60 Hz
-1024 x 768, 16-Bit/Plxel, 100 Hz
- 1024 x 768, 24-Bit/Pixel, Packed, 67 Hz
,.. 800 x 600, 24-Bit/Plxel, Unpacked, 75 Hz
- 800 x 600, 24-Bit/Pixel, Packed, 110 Hz
True-Color Desktop, PC Add-in Card

•

X-Windows Terminals

•

Green PCs

description
The TVP3409 is intended to be a direct replacement for the ATT20C409 RAM digital-to-analog converter
(RAMDAC). The TVP3409 RAMDAC supports 8-bit multiplexed operation that can be input on 16 pixel
terminals. The TVP3409 retains register compatiblity with the ATI20C498 and ATI20C499 devices. The
TVP3409 features 24-bit packed pixel modes that provide 24-bit graphics at up to 1024 x 768 screen resolution.
Dual clock synthesizers offer two, programmable and two fixed frequencies in phase-locked-loop A (PLLA) and
one programmable and three fixed frequencies in phase-locked-loop B (PLLB). After reset, the frequencies are:
PLLA: 25.175, 28.322, 50, and 75 MHz
PLLB: 30, 40, 50, and 60 MHz
Easy identification of the RAMDAC allows the video BIOS to determine if a requested mode is available on the
hardware being used.
AVAILABLE OPTIONS

TA

DoC to 70°C

t

PACKAGE

SPEED

DAC
RESOLUTION

135 MHz

8 Bits

TVP3409-135CFN

170 MHz

8 Bits

TVP3409-170CFN

CHIP CARRIER
(FN)

For the complete data manual (SLAS092), contact the local TI sales office.

-!!1

Copyright © 1997, Texas Instruments Incorporated

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265

6-13

TVP3409
VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC
XLAS092A - MAY 1995 - REVISED NOVEMBER 1997

functional block diagram
REF RSET

~~--COMP

24116/8

P(l5-0)

RED

256 x 24/18
'RAMDAC
Color RAM

GREEN

PCLK -----'--I

BLUE

FS(l,O) - - - - I

t---,r----r--,
STROBE - - - - ' - /

OTCLKB

~TEXAS

6-14

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
FEBRUARY 1995 - REVISED NOVEMBER 1997

•

Fully Integrated Dual Clock Synthesizer
and 16-Bit Pixel Port True-Color RAMDAC

• 16-Bit Pixel Port Supports VGA High-Color
and True-Color Standards Up to 170 MHz

•

Two Phase-locked-Loop (PLL)
Synthesizers Provide Independently
Controlled Video and Memory Clock
Outputs

• Programmable Power-Down Features
• On-Chip Cyclic Redundancy Check (CRC)
Test

•

Functionally Interchangeable with STG1703

•

On-Chip PLL Clock Reference Requires
Single External Crystal

• Data Sheet Availablet

applications
• Screen Resolutions (Noninterlaced)
1600 x 1280, 8-bit/pixel, 60 Hz
1280 x 1024, 16-bitlpixel, 60 Hz
1024 x 768, 16-bit/pixel, 85 Hz
1024 x 768, 24-bitlpixel, packed, 70 Hz
-

800 x 600, 24-bitlpixel, unpacked, 72 Hz

• True-Color Desktop, PC Add-In Cards

description
The TVP3703 is a super video graphics array (SVGA) compatible, true-color CMOS RAMDAC with integrated
clock synthesizers that can provide the memory and pixel clock signals for a PC graphics subsystem. The video
clock can be one of two VGA base frequencies or fourteen Video Electronics Standards Association (VESA)
standard frequencies which can also be reprogrammed through the standard micro port interface.
The memory clock output is also user programmable at frequencies up to 80 MHz. The pixel modes supported
by the TVP3703 include:
•

Serializing 16-bit pixel port providing 170 MHz, 8-bit and 73 MHz, 24-bit packed pixel modes using an
internal PLL

•

16-bit pixel port providing faster, high-color/true-color operation up to the 110 MHz sampling rate

•

8-bit pixel port providing standard SVGA and high-color/true-color modes up to the. 110 MHz sampling rate

The 68 terminal FN package is designed to be interchangeable with the STG1703.
AVAILABLE OPTIONS
TA

O°C to 70°C

t

SPEED

PACKAGE

DAC
RESOLUTION

CHIP CARRIER
(FN)

135 MHz

8 Bits

TVP3703-135CFN

170 MHz

8 Bits

TVP3703-170CFN

For the complete data sheet (SLAS100), contact the local TI sales office.

~TEXAS

Copyright © 1997, Texas Instruments Incorporated

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-15

TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
XLAS100A- FEBRUARY 1995 - REVISED NOVEMBER 1997

functional block diagram
MCLK

XIN

XOUT

VCLK

00-07
RO

WR
RSO-RS2

MCLK
Registers

Micro Port

VSO-VS3
STROBE

24

256x8 Bit
Color Palette
PIXMIX
PO-P15

Pixel
Latches

Multiplexor

>---.....- - -

256x8 Bit
Color Palette
256x8 Bit
Color Palette

. . . - - - - GREEN

r---t-3

PCLK

~TEXAS

6-16

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75266

RED

BLUE

7-1

Contents
. Page
\

TLC8044 : ........................................... , ........................ 7-3
TLC8144 :' '.................................................................. 7-33
TLC8188 : .................................................................. 7-61

-ecn
"tJ

7-2

TLC8044
12·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 - JUNE

•
•
•
•

Color or Gray Scale Operation
Signals Processed in the Digital Domain
Differential RGB Input Multiplexer
Three 8-bit DACs for CCD Offset Level
Shifting With Bipolar Correction Range

•

Two Sampling Modes:
- DAC Referenced
- Correlated Double Sampling (CDS)
12·Bit ADC with 6 MSPS Operation
Digital dc Restoration
Pixel·By.Pixel Offset and Shading (Gain)
Compensation
Global Gain Adjust for Each Color
(Channel)

•
•
•
•

•
•
•
•
•
•

Compatible with 600 dpi CCD Image
Sensors
Global Offset Adjust for Each Color
(Channel)
Output Word Length Programmable to 8,
10,12, or 16 Bits
Programmable Threshold Detector for Each
Color (Channel)
Dual Internal Default Registers for
Even/Odd Pixel Offset Correction
68·Terminal PLCC Package

applications
•
•

Handy Scanners
Flatbed Scanners

description
The TLC8044 is a 12-bit analog-to-digital interface subsystem for charge-coupled device (CCD) image sensors
and scanners. An input multiplexer allows color operation with a single on-chip 12-bit ADC. The TLC8044 uses
OSP circuits to correct for non ideal CCO image sensor and scanning system characteristics. Cost effective gray
scale operation is obtained using a single multiplexer input. .The TLC8044 three-channel input multiplexer and
sampling function has two basic modes of operation: normal sampling' and correlated double sampling. The
internal sample and hold allows all three channels to be sampled simultaneously in color operation. Three DACs
(8 bits + sign) are provided to allow bipolar adjustment of the dc level of the signal at the ADC input. Digital dc
restoration is provided following the AOC. Variations in offset and luminance across a scan are dynamically
corrected on a pixel-by-pixel basis, using calibration data provided by an external data store. Provisions are
made for global adjustments of gain, contrast and color balance, and offset for brightness. The output word
length can be programmed to 8, 10, 12, or 16 bits, and a programmable threshold detector is provided for use
during calibration and OCR applications. The TLC8044 is characterized for operation from O°C to 70°C.

AVAILABLE OPTIONS
PACKAGE
TA

CHIP CARRIER
(FN)

DoC to 70°C

TLC8044FN

-!!1 TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

Copyright © 1997, Texas Instruments Incorporated

7-3

TLC8044
12·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128-JUNE 1997

FNPACKAGE
(TOP VIEW)
C\I

o

O~C\lC')vlt)

~~~~~~~~~~~~~~~~~
00000000000000000
CC1
CCO
ORNG
DETOP
DGND
PSC11
PSC10
PSC9
PSC8
PSC7
PSC6
PSC5
PSC4
PSC3
PSC2
PSC1
PSCO

9 8 7 6 5 4 3 2 1 6867 66 6564 636261
10
60
11
59
12
58
57
13
14
56
55
15
16
54
53
17
18
52
51
19
50
20
49
21
48
22
47
23
24
46
45
25
44
26
2728293031 32 333435363738394041 4243
~om~~wlt)vC')C\I~o~~m~~

U88888888888~~~~~
~Q..Q..Q..Q..Q..Q..Q..Q..Q..Q..Q..~

~T~s

7-4

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DVOO1
ONE
SDI
SCK
SEN
MCLK
VSMP
OE
RINP
RINN
GINP
GINN
AVOO
AGND
BINP
BINN
DAC

functional block diagram
RU

AT

AS

RL

OAC

ONE

POC

PSC

cc
OE
OP
ORNG

~

SINP
SINN

!!l

~-4r
rZ

:XI
DETOP

!!of.

~~d

n
::J:
l>
C)

m

n•

0
c:

~t:g
':~

SOl
SCK
SEN

~r!1

"0
,m .....

CN
C'
m!!!
<-I

~~
iii

-l>
n



Z

~

=:,-

~

l>0

C)C)

m.!.t
m'
zS!
(J)C)

(J)O

0-

:XI;!
(J)''TIO~
(I):XIm

~(J) ::D
Nn~

~l>n -I

~~mh
iiim'TI co

l'
(11

I

I~~g!

TLC8044
12·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 - JUNE 1997

Terminal Functions
TERMINAL
NAME

NO.

TYPE

I/O
I

DESCRIPTION

AGND

47

Analog

AVDD

48

Analog

BINN

45

Analog'

I

BINP

46

Analog

I

Positive blue channel input video

10,11

Digital

0

Color code outputs. CCO and CCI indicate Which channel the current output sample was taken
from (R = 00, G = 01, B = 10).

DAC

44

Analog

0

Buffered midpoint of ADC reference string. DACis used internally to set DAC reference voltages.

DETOP

13

Digital

0

Threshold detector output (active high). DETOP indicates that the current output pixel has
exceeded the internally programmed threshold for that channel.

CC1,0

-

DGND

Analog ground (0 V)
Positive analog supply (5 V)
Negative blue channel input video

Digital ground (0 V)

14

Digital

I

60,1

Digital

I

Positive digital supply (5 V)

GINN

49

Analog

I

Negative green channel input video

GINP

50

Analog

I

Positive green channel input video,

MCLK

55

Digital

I

Master clock. MCLK is applied at either six times or twice the input pixel rate for color and
monochrome operation, respectively. MCLK is divided by two internally to define the ADC sample
rate and to provide the clock source for the DSP section.

OE

53

Digital

I

Output 3-state control. Outputs are enabled when OE = O.

ONE

59

Digital

I

Odd not even. ONE defines the even and odd pixels when the internal pixel offset correction
registers are in use (even = 0, odd = 1).

61-68,
2-9

Digital

0

Digital 16-bit output (3-state). In 8-, 10-, and 12-bit output modes, OP15 is used to indicate that
the output pixel is negative; i.e., OP15 can 'be used as an' under range indicator. OP15 is active
high when indicating under range.

12

Digital

0

Over range signal (active high). In 8-,10-, and 12-bit output modes, this signal indicates that the
current output pixnl has exceeded the maximum achievable for the output word length in use.

POCI1-POCO

27-38

Digital

I

Pixel offset coefficient input. The POC II-POCO 12-bit word is applied at the multiplexed pixel rate
(i.e., three samples per pixel period in colqr mode) to correct offset errors in a pixel-by-pixel
fashion.

PSCI1-PSCO

15-26

Digital

I

Pixel shading coefficient input. The P~Cll-PSCO 12-bit quantity is applied at the multiplexed
pixel rate (i.e., three samples per pixel period in color mode) to correct shading effects in a
pixel-by-pixel fashion.
Reset input (active high). RESET forces a reset of all internal registers in the TLC8044.

DVDD1,2

OPI5-0PO

ORNG

RESET

39

Digital

I

RINN

51

Analog

I

Negative red channel input video

RINP

52

Analog

I

Positive red channel input video

42,40,
41,43

Analog

I

ADC reference terminals. The voltage applied between RT (full scale) and RB (zero level). define
the ADC reference range. RU and RL, upper and lower resistor terminals, are used to derive
optimum reference voltages from an external 5-V reference.

SCK

57

Digital

I

Serial clock. Serial interface clock signal.

SOl

58

Digital

I

Serial data in. Serial interface input data signal.

SEN

56

Digital

I

Serial enable

VSMP

54

Digital

I

Video sample synchronization pulse. VSMP applied synchronously with MCLK specifies the point
in time that the input is sampled. The timing of internal multiplexing between the R, G, and B
channels is derived from this signal.

RU, RT, RB,
RL

~TEXAS

INSTRUMENTS
7-6

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC8044
12·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 - JUNE 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, DVDD1, DVDD2, AVDD, VDD (see Note 1) ........................................ 7 V
Digital inputs (see Note 1) ................................................... - 0.3 V to VDD + 0.3 V
Analog inputs (see Note 1) .................................................. - 0.3 V to Vee + 0.3 V
Digital outputs, maximum external voltage applied (see Note 1) .................. - 0.3 V to Vee + 0.3 V
Reference input (see Note 1) ................................................ - 0.3 V to VDD + 0.3 V
Operating temperature range, TA ..................................................... DoC to 70°C
Storage temperature range, Tstg ................................................... -50°C to 150°C
Lead temperature, soldering, 10 sec ........................................................ 260°C

t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltages applied to DVDD1 and DVDD2 are measured with respect to the DGND terminal. AVDD is measured with respect to the AGND
terminal. For the following specifications, unless otherwise noted, AGND and DGND are tied togather (and represent 0 volts) and are
referred to simply as GND. When the voltages applied to DVDD1, DVDD2, and AVDD are equal, they are referred to simply as VDD, unless
otherwise noted.

recommended operating conditions
total device
MIN

NOM

4.75

Supply voltage, VCC

MAX
5.25

digital inputs
MIN
High-level input voltage, VIH

NOM

MAX

UNIT
V

0.9 VDD

LOW-level input voltage, VIL

0.1 VOO

V

input multiplexer
TEST CONDITIONS

MIN

NOM

MAX

UNIT

Setup time, input video before MCLKi, tsu(V)

10

ns

Hold time, input video after MCLKi, they)

25

ns

CDS mode only

10

ns

CDS mode only

25

ns

Setup time, reset video before MCLKi, tsu(R)
Hold time, reset video after MCLKi, th(R)

,

serial interface
MIN

NOM

MAX

UNIT

Cycle time. MCLK, tcye l

83.3

ns

Pulse duration, MCLK high, tw1 (MCLKH)

37.5

ns

Pulse duration, MCLK low, tw 2(MCLKL)

37.5

ns

Setup time, VSMPi to MCLKi, tsu(D)

10

ns

Hold time, MCLKi to VSMP.j., th(D)

10

ns

Setup time, POC/PCS to MCLK.j., tsu(P)

10

ns

Hold time, MCLK.j. to POC/PCS, th(P)

30

ns

Cycle time, SCK, lcyc2

83.3

ns

Pulse duration, SCK high, tw 3(SCKH)

37.5

ns

Pulse duration, SCK low, tw 4(SCKL)

37.5

ns

Setup time, SDI to MCLKi, tsu(S)

10

ns

Hold time, MCLKi to SDI change, thiS)

10

ns

Setup time, SCKi to SENi, tsu(SCE)

20

ns

Setup time, SEN.j. to SCKi, tsu(SEC)

20

ns

Pulse duration, SEN high, tw(SEN)

50

ns

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

7-7

TLC8044
12·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLASI28-JUNE 1997

electrical characteristics, VDD

=5 V, AGND =DGND =0 V, TA =full range (unless otherwise noted)

total device
PARAMETER
ICC

Supply current, active

~

Supply current, standby

MIN

TYP

MAX

UNIT

80

130

rnA

8

10

rnA

TYP

MAX

digital inputs
PARAMETER

MIN

UNIT

IIH

High-level input current

1

I!A

IlL

Low-level input current

1

I!A

Ci

Input capacitance

10

pF

digital outputs
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

IOH=-1 rnA

VOL

Low-level output voltage

IOL= 1 rnA

IOZ

High-impedance output current

MIN

TYP

MAX

UNIT
V

VDD -0.75
0.75
1

V

!!A

input multiplexer
MIN

PARAMETER
Channel-to-channel gain matching
VICR

Common mode input voltage

TYP

MAX

0.5%

5%

0.5

4.5

UNIT

V

reference string
MIN

TYP

MAX

UNIT

Z

Impedance, RT to RB

PARAMETER

TEST CONDITIONS

595

850

1105

Q

Z

Impedance, RU to RL

1190

1700

2210

Q

Vref(RT)

Reference voltage, top

VI(RU) =5V,

VI(RL) =OV

3.7125

3.75

3.7875

V

Vref{RB)

Reference voltage, bottom

VI(RU) = 5 V,

VI(RL) =0 V

1.2375

1.25

1.2625

V

Vref(DAC)

DAC reference voltage

VI(RU) = 5V,

VI(RL) =OV

2.475

2.5

2.525

V

8-bit DACs
PARAMETER

MIN

TYP

MAX

UNIT

Resolution

8

Zero-scale voltage

0

10

Full-scale voltage

Vref(DAC) -10

Vref(DAC) +10

mV

Bits
mV

Differential nonlinearity (DNL)

0.1

<1

LSB

Integral nonlinearity (INL)

0.4

1

LSB

~·TEXAS

7-8

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC8044
12·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 - JUNE 1997

electrical characteristics, VDD = 5 V, AGND = DGND = 0 V, TA = full range (unless otherwise noted)
(continued)
12-bit ADC
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

6

MSPS

12

Resolution

Bits

Sampling rate
Full-scale transition error voltage at xlNP (see Note 2)

Single-ended mode,
VI(xINN) = 2.5 V,
DAC code = OOOH

-100

100

mV

Zero-scale transition error voltage at xlNP (see Note 3)

Single-ended mode,
VI(xINN) = 2.5 V,
DAC code = OOOH

-100

100

mV

Full-scale transition error voltage, VI(xINP) - VI(xINN) (see Note 2)

Differential mode,
DAC code = OOOH

-25

25

mV

Zero-scale transition error voltage, VI(xINP) - VI (x INN) (see Note 3)

Differential mode,
DAC code = OOOH

-25

25

mV

Differential nonlinearity (DNL) (see Note 4)

1.5

a

Maximum number of missing codes
Integral nonlinearity (INL) (see Note 5)

±2

LSB

8

CODES

±5

LSB

NOTES: 2. The full-scale transition at xlNP is the difference between the signal input voltage that causes the 4094 to 4095 transition and the
measured reference voltage Vref(RT)'
3. The zero-scale transition at xlNP is the difference between the signal input voltage that causes the 0 to 1 transition and the reference
voltage Vref(RB).
.
4. Differential nonlinearity (DNL) is the difference between the measured value between any two adjacent codes and the ideal 1 LSB
value.
5. Integral nonlinearity (INL) is the maximum deviation of the output from the ideal straight line between zero and the full-scale value.

switching characteristics
PARAMETER

TYP

MAX

tpd(D)

Propagation delay time, MCLK! to output valid

MIN

50

75

UNIT
ns

ten(PZE)

Enable time, output, OE! to data valid

70

75

ns

tdis(PEZ)

Disable time, output, OEi to high impedance

70

25

ns

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-9

TLC8044
12·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE '~NSORS FOR SCANNERS
SLAS128 - JUNE 1997

PARAMETER MEASUREMENT INFORMATION
MCLK
tsu(D)

14

.',4

"I th(Dl

...J.r-4

VSMP _ _

R,G,B Video Inputs
(Normal Mode)

.14

I\. . --+1--

1

1

~. -'I'":...J/

\ ' tSU~V);4

\'-_ _ _ _ '1'"1

"~oj

\

~

tsu(V)

"l J/

they)

\

~

tsu(V)

-1-;

1

!.--

'------.,.I-.,.I...-JI

R,G,B Video Inputs
(CDSR1 = 1, CDSRO = 0)

-..!

.

~4

t

they)

~4 ~they)

y

Ir---....,...--'T"I~-'T'""'"

th(R(

tsu(R)

they)

1

1 '--..

'1'

tsu!V) 1:4

~ 1 .

1

--+I

j4-

tsu(R)

---tI

'1\

t su (V):4

th(R)
I
. tsu(V) 14

IN;

1

I-

!4

t

they)

they)

1

1

-OJ I--

y

+}
1

14- th(R!

1
• 4 .: they)

\!

R,G,B Video Inputs
(CDSR1 = 1, CDSRO = 1)

tsu;V) :14

'1\

-41 I.-

'-----"1-"'11
tsu(V) 14

th(D)

1

tsu(V) :14
they)
R,G,B Video Inputs
.
I;r
(CDSR1 = 0, CDSRO = 0) - - - - - - - - , -..Ir--'II' ~ tsu(R)
R,G,B Video Inputs
(CDSR1 = 0, CDSRO = 1)

~

-=:i

tsu(R)

~

1

1

.

~ 4 .~ they)

Y
th(R) ,

Figure 1. Detailed Video Input Timing - Color Mode
MCLK

I

~

~tsu(D)~

R,G,B Input Video

7

1

'\

!

\

VSMP

14- th(D)

tSU(V)'\tO"
Reset

\

Video

1
1
1
1

II
1
1

~.

Oyth(V)

\
tSU(V){

7

Figure 2. Detailed Video Input Timing - Monochrome Mode

~TEXAS

7-10

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1
1
1
1
1

1
1
1
~

/
Oyth(V)

TLC8044
12-81T ANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS

.
PARAMETER MEASUREMENT INFORMATION
MCLK

I

th(O)

SMP

~

I..

tSU(O)

i)

----+-1----J.
I
I I+--

I

I

1

I

\:I
-.I
=-.I

tsu(O)

r--

t.-

ONE_~:

OP1S-0PO

========,~=~
I

CCo

:

tpd(O)

Red

::

tsu(O)

.

~

I

I

r--

--.I t.-

~:

.

X

Green.

:1

:

:

I

I

*=========

;*'---_
:

1.--.1---- tpd(O)

.~,..

Blue:

I

I

~

,,:

I

CC1----+-~'i

Blue

X

I

\.

l+-

-.I

~ I

tsu(O)

I:~ tpd(O)

:Pd(O)

: !

I

th(O)

:

Green

! - - . i - :

I

th(O)

X

*
:
k
Red

I.

I
I

.

th(O)

:~~:: =:~: ========::>k

I

1-1

--..I

SLAS128-JUNE 1997

:

I

)

:

_ _ __

I
:

I

'-J

~---

Figure 3. Detailed Digital Timing - Color Mode

MCLK

I

th(O)

I

tsu(O)

SMP

I..

\LJ
:

14---

--..I
~I

I

1-:I

:I

1

\~:----JI
~ t.-

th(O)
tsu(O) - I

:---

:::::=:: ======:,.....""'>k'--__~....,....,r_oJX

\.L.I
th(O)
tsu(O)

-.J

~:

:

--l

th(O)
: - - - tsu(O) - I

1

I

:

i

I

-----..;1.. '""\X~I

OP1S-0PO

I·
tpd(O)

I" X~I

tpd(O)

I

i

1

I" ~

\.

I+I

)k========

.X

1

ONE======;)(

t.-

\: I

Ipd(O)

1

*=======

I
I" ~

tpd(O)

_ _ _ _- - J

Figure 4. Detailed Digital Timing - Monochrome Mode

~TEXAS

INSTRUMENTS .
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-11

TLC8044
12·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128-JUNE 1997

PARAMETER MEASUREMENT INFORMATION

SCK
thIS)

SOl

_---Ix

tsu(S)

14

X

-+I.•, IIt---

X----.X~__'X"-----li...JX~___f _ _

I
tsu(SCE)

I

tW(SEN)M

14

i+,4-...,~t- tsu(SEC)

.,

FIr""'\I,~---

SEN _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J

Figure 5. Detailed Digital Timing - Serial Interface

TYPICAL CHARACTERISTICS
III

~
I

0.8
0.6
0.4
c
==c 0.2
0
z
0
-0.2
I!! -0.4
~
c -0.6
I -0.8

€:g

~

...z

-1

c

2047

0

Input Code

Figure 6. Differential Linearity With Code
5
4

3
2
1

o I..la..
'!

-1

I

-3
-4

I

...

i!!:

c ....

I" 1IIf"P'''''''-'''''
r

'"'

--

-2

-5

o

1023

2047
Input Code

Figure 7. Integral Linearity With Code

~.TEXAS

7-12

....

...... ,., .....~~ ...............

......

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3071

4095

TLC8044
12·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS'28 - JUNE' 997

PRINCIPLES OF OPERATION
general CCO system operation

CCD image sensor array output summary
Figure 8 shows a simplified eeo image sensor linear array system with typical eeo array inputs and outputs.
The inputs for the shift gate (SH), reset, and two-phase clock drive the array. An electronic charge proportional
to the light input is generated by a photo diode for each pixel of the array. The charge for each pixel is transferred
in parallel into the analog eeD shift register using the shift gate input and then shifted out serially using a
two-phase clock. At the eeo output (OS terminal), the array converts the charge for each pixel into a voltage
using a capacitor and source follower MOS transistor. The charge on this capacitor is reset for each pixel by
the reset pulse input. A typical output signal then includes a reset period, a dark period, and a period containing
video output for each pixel, as shown in Figure 9. This signal sits on a varying dc offset of typically 5 V and is
negative going for an increase in video output. An output (OOS terminal) also provides only the dc level from
the eeo array:

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

7-13

I IGe~:~;or I

!..,.

cc

MCLK

os I--------f

r-"""'I I

VSMP

CCD
Image
Sensor

1--1

-=

I 1~

OS I--------f

1.

t

...
2GR

OP

RINN

1.

II

~-4r
~~.

GINP

TLC8044

DETOP

oS!
mG)
< .....
oj;!

G)m
m::C
(I)~
'mo
zm

oos

~'TI

::cO
(I)::C

os

'TI

~lTJ

~~

Signal
Processing

~Or

mr

!OO.

~t:~

~OJ:-

"'cO
"'tI'i>
r-l
mO
0,

• 3:Z
J:--I

r-"""'I I I I

~
m~mt
';~

16

ORNG

C3
~

Gate Array

DE

RINP

DOS

I~o~
CIl::::t:, r-I
;;)J:-m O
""::C- 00
~G)-Ig ,
em»
oI:>i '
~, Z

Ii

0
::c
(I)

DOS

0

»
en

J:Z
Z

Ui

al

Figure 8. System Diagram

m
::c
(I)

TLC8044
12-81T ANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128-JUNE 1997

PRINCIPLES OF OPERATION
CCO image sensor array output summary (continued)
Reset
Feedthrough

~

I I~::::I

Video
Level

I

~-""'r'"

Black

{

'-r

Amplitude

L-J~
_ _,.,1 +-- White

L

Period of
One Pixel

J

Period of
One Pixel

Figure 9. A Typical Charge-Coupled Display (CCO) Output Signal
CCO array analog-to-digital interface functions
The interface to the CCD array analog output and the conversion of the output into digital form involves the
following functions:
.
1.

The video output waveform first has to be removed from the varying dc level on which it sits and shifted in
level to be compatible with an interface device running from a single 5-V supply rail.

2.

Gain has to be applied to bring the signal up to the full-scale range of the analog-to-digital converter (ADC)
and a means provided to adjust static gain to compensate for variations between devices or multiple outputs
of color arrays. Once these static dc levels (offsets) and gain levels have been adjusted. dynamic
corrections are needed on a pixel-by-pixel basis.

3.

Dynamic gain adjustment is needed to compensate for the fall off in output from the center to the ends of
the array when used in scanner applications (see Figure 10). Dynamic offset adjustments are required to
compensate for the pixel-by-pixel variation in black dc levels obtained from different CCD array elements.

4.

DC restoration may optionally be required. Global adjustments of gain and offset across a whole scan are
respectively used to correct color balance and contrast and to change brightness.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-15

TLC8044
12·81T ANALOG..TO-DIGITAL INTERFACE FOR
CHARGE·COUPLEDDEVICEIMAGE SENSORS FOR SCANNERS
SLAS123 - JUNE 1997

PRINCIPLES OF OPERATION

CCO array analog-to-digital interface functions (continued)
Ideal Output
(As Corrected By Pixel
Shading Adjust Block)

/----

I
I

I
----'l

I

i

0,

I
I

/1
Scanning System
Output Error

~

PIxel Width

---.I

Scanner System Pixel Outputs

TIme

Figure 10. Scanner System Relative CCO Pixel Output

CCO scanner analog-to-dlgital interface subsystem
input dc level shift, output offset, and channel gain

The TLC8044 uses external operational amplifiers configu'red as differential amplifiers to remove the dc level
present in the CCO outputs by using the common mode voltages from the OS and DOS outputs for each channel
(see the functional block and system diagrams). OC bias is provided for the external differential amplifier from
the TLC8044 OAC output as shown in the system diagram in Figure a. Without any residual offset from the CCO,
the differential amplifier minimum output is (OAC result)/2 and is uneffected by the external differential amplifier
gain setting (G). The offset at the output of the external differential amplifiers, including residual offset from the
CCO, should be low enough to ensure the CCO amplified signal is within the input common mode range of the
TLC8044 and that the offset can be adjusted out by the TLC8044 internal OACs.
The external differential amplifiers also provide the system gain for each channel to ensure the output amplitude
of each channel is greater than one half the AOC full-scale range. Variations between the RGB channels of the
CCO can have a 10 to 1 ratio in output. To minimize the offset at the amplifier output with the highest gain, the
external amplifiers should be configured for gains in the range 1/3 to 3 rather than 1 to 10 to compensate for
this output variation. This is achieved by scaling the gain setting resistors shown in the system diagram by the
gain factor (G) over this 1/3 to 3 range.
RGB channel multiplexer and sampler

For color CCO image sensor arrays, a combined three-input multiplexer and sampler is used enabling the use
of a single fast 12-bit ADC and DSP channel.
The TLCa044 multiplexer has three differential inputs for each of the RGB channel outputs and a further internal
input for each channel which is used to compensate for the residual offset in the input signal. This internal offset
compensation is provided by the TLCa044 three a-bit plus sign OACs, which provide bipolar offset correction
with respect to the input reference levels. The OACs are updated through the serial interface.

~1ExAs

7-16

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC8044
12·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 - JUNE 1997

PRINCIPLES OF OPERATION
RGB channel multiplexer and sampler (continued)
The input structure can be set up for use in single-ended or fully differential mode, under control of the serial
interface data. The configuration shown in the system diagram is single ended, with the negative inputs tied to
the DAC, which is the buffered midpoint of the ADC reference chain. Differential mode can be used when an
amplifier with differential outputs is placed between the CCD image sensor and the TLC8044.
In color operation, the three-channel sampling system multiplexes the three channels to the ADC input in a
sequence defined by the VSMP input synchronization pulse. In monochrome operation, channel
synchronization between R, G, and B inputs is achieved through the serial interface.

analog-to-digital converter
The ADC is implemented using a 12-bit pipelined architecture which performs conversions at one half the MCLK
clock rate. The ADC full-scale range is defined by the voltages applied to terminals RT and RB, which should
be set to 3.75 V and 1.25 V respectively to give a full-scale range of 3.75 V -1.25 V = 2.5 V.
The ADC internal input is differential with an input signal of 2.5 V corresponding to full scale (output code FFF
hex) and -2.5 V corresponding to zero scale (output code 000 hex).
The RU and RL terminals are connected to extensions of the internal reference chain, which allow the 3.75-V
and 1.25-V levels to be derived irom a 5-V reference applied between RU and RL. All reference terminals should
be capacitively decoupled externally.
The combination of the input multiplexer structure with the internal offset correction DACs accomodates a wide
range of input voltages. The. relationships between input voltage levels (at the positive and negative inputs INP
and INN) and ADC full-scale and zero-scale results are shown in Tables 1 and 2 for a range of input offset
voltages for both single-ended and differential input modes. The tables also show the DAC correction voltage
and code required in each case.
The basic difference between single-ended and differential input modes is that a gain of 2 is applied to the input
signal between INP and INN in the single-ended case. Thus an input differential of 1.25 V is converted to a
full-scale ADC differential input of 2.5 V. Any residual offset present on the input signal is also gained by 2 in
the single-ended mode, resulting in the required DAC values shown in Table 1.
Table 1. Single-Ended Mode Input Voltage Ranges
INPUT
OFFSET
VOLTAGE

FULL-SCALE
INPUT
VOLTAGE

ZERO-SCALE
INPUT
VOLTAGE

DAC
VOLTAGE

DAC
CODE
(HEX)

17F

VI(INP)

VI(INN)

VI(INP)

VI(INN)

0.625

4.375

2.5

1.875

2.5

-1.25

0

3.75

2.5

1.25

2.5

0

000

-0.625

3.125

2.5

0.625

2.5

1.25

07F

Table 2. Differential Mode Input Voltage Ranges
DIFFERENTIAL
INPUT OFFSET
VOLTAGE

FULL-SCALE
INPUT
VOLTAGE

ZERO-SCALE
INPUT
VOLTAGE

DAC
VOLTAGE

DAC
CODE
(HEX)

VI(INP)

VI(INN)

VI(INP)

VI(INN)

1.25

4.375

0.625

1.875

3.125

-1.25

17F

0

3.75

1.25

1.25

3.75

0

000

-1.25

3.125

1.875

0.625

4.375

1.25

07F

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-17

TLC8044
'12-8IT ANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS12S-JUNE 1997

PRINCIPLES OF OPERATION
analog-to-digital converter (continued)
The examples in Tables 1 and 2 assume that the ADC reference terminals RT and RB are set to 3.75 V and
1.25 V, respectively. The signals shown in the tables cover the full-scale range of the ADC. In practice, a reduced
range is used to allow some headroom, accomodating a wider range of input offset voltages. The. ADC output
code can be inverted under control of the serial interface. When not in use, the ADC can also be put into standby
mode through the serial interface to reduce system power consumption.
sample modes
Two input sampling modes are provided, normal and correlated double sampling (CDS). Sampling mode
selection is made through the serial interface. All video input timing and sampling is performed relative to the
rising edge of the MCLK clock input signal. MCLK is applied to twice the required ADC conversion rate.
Synchronization of sampling and channel multiplexing to the incoming video signals is performed by the VSMP
input synchronization pulse. Table 3 is a summary of the device operating modes.
normal sampling mode
Figure 11 (a) and Figure 11 (b) show the timing of signals in normal sampling mode for both color and
monochrome operation.
In color operation, all three input channels are sampled at the same instant on the first rising edge of MCLK after
the VSMP pulse. An internal timing circuit then controls the multiplexing of the three channels to the ADC input
in the R,G,B sequence. In this mode, VSMP is applied at the input pixel rate, and ADC conversions are
performed at three times the input pixel rate.
For monochrome (single channel) operation, VSMPis again applied at the input pixel rate, however, for
monochrome, the ADC is supplied with a continuous stream of samples from a single input channel. Input
channel selection in this mode is achieved through the serial interface.
In both color and monochrome operation, a simple external delay circuit can be used to align the video data with
the sampling instant, provided that the CCD clocks are generated from MCLK. Detailed timings for both cases
are shown in Figures 3 and 4.

7-18

:II.
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

Table 3. Mode Summary

MODE

1

~

DESCRIPTION

Color

2

Monochrome

3

Fast
monochrome

4

MBl< speed
monochrome

CDS
AVAILABLE

Yes

Yes

MAX
SAMPLE
RATE

2 MSPS

The three input channels
(R, G, B) are sampled in
parallel at 2 MSPS
maximum. The sampled
data is multiplexed into a
single data stream before
the internal ADC, giving an
internal serial data rate of
maximum 6 MSPS.

2 MSPS

o_~

~Z
mrJ)

SENSOR INTERFACE
DESCRIPTION

TIMING REQUIREMENTS

Yes

4 MSPS

Setup register 1:
Word 1:00h
Word2:S1h

Setup register 1:
Word 1:00h
Word 2: SOh

One input channel is
continuously sampled. The
internal multiplexer is held
in one position under
control of the user.

Identical to mode 1

Setup register 1:
Word 1:00h
Word2:91h
Setup register 2:
Word 2: bits b(1,0) define
which channel to be
'sampled

Setup register 1:
Word 1: OOh
Word 2: 90h
Setup register 2:
Word 2: bits b(1,0) define
which channel to be
sampled

Identical to mode 2

MCLK max: 12 MHz
MCLK: VSMP ratio is 3:1

Identical to mode 2 plus
Setup register 2:
Word 1: bits b(1 ,0) must be
set to OOh

Identical to mode 2

c:
"'0
r-

ON

Not supported

Setup register 1: 5Dh
Setup register 2:
Word 2: bits b(1 ,0) define
which channel to be
sampled

~ ~
t::.
~~

~~z

i~
rJ)

~

No

t Only indicates relevant register bits.

6 MSPS

REGISTER CONTENTS
WITHOUT CDSt

MCLK max: 12 Mhz
MCLK: VSMP ratio is 6:1

~.

~ ~r;;f

REGISTER CONTENTS
WITHCDSt

Identical to mode 2

MCLK max: 12 MHz
MCLK: VSMP ratio is 2:1

o

:::E:

l>
::D
C)

6o
m .....

0'

m!!!

<-I

-l>

Oz
!!!l>

:s:r-

l>0
C)C)

m.!.t
m'
zS!

enO
enC)

0::D~
enr-nOZ

cn::D -I

~en~

j\)O~
~l>O -I

1: Z mrzZ

:r
<0

0
mm-nQ)

;;:)::DO C
!!len::D

:t

TLC8044
12·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128- JUNE 1997

PRINCIPLES OF OPERATION
. MCLK

I
I
I
1
I
I
I
I
I
I r2,g2,1,2
I
I
I r3,g3,b3
I
r1,~1, b1 I
I
I
I
I
I
I
I
I
I
I
I
I
_ _....._--10
_ _--10_--10_......._--1-_......._--1-_____-+________-----___I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
g1
b1
b2
bO ~_+_~
: g2

~""----+I---+---+---+---Io...J
I
I Ii\
I

VSMP

~~:~ W/27L7/J
Video
Sample

ADClnput

t

I

1

I

I
I
I

Ii\

:~~..Q

I~$

;X

~

t

1

i

i

I

t

~

i~

i

I
I
I
ADC
I
1- - -___
1- - -___
1- - - - -1- - - - -1- - - - Sample _ _...._ _ _......._ _ _.......


DESCRIPTION

DATA
WORD

000000

Setup
register 1

1
2

000001

Setup
register 2

1
2

000010

Reserved

1
2

000011

Software reset

1
2

1000xx

DAC values

1001xx

BIT
b7
ENADC

b6
BICLIP

b4

bS
ADCMX

MONO

b3
DEFPG

b2

b1

bO

DEFPO

DNS

INVADC
CDS
CDSREFO
CHAND

POSCL1

POSCLO

WLSEL1

WLSELO

THSEL1

THSELO

CDSREF1
CHAN1

1
2

D7

D6

D5

D4

D3

D2

D1

POL
DO(LSB)

DC restore
values

1
2

D7

D6

D5

D4

D11(MSB)
D3

D10
D2

D9
D1

D8
DO(LSB)

1010xx

Default even
pixel offsets

1
2

D7

D6

D5

D4

D11(MSB)
D3

D10
D2

D9
D1

D8
DO(LSB)

i011xx

Default odd
pixel offsets

1
2

D7

D6

D5

D4

D11(MSB)
D3

D10
D2

D9
D1

D8
DO(LSB)

1100xx

Default pixel
gains

1
2

D7

D6

D5

D4

D11(MSB)
D3

D10
D2

D9
D1

D8
DO(LSB)

1101xx

Global offsets

1
2

D15(MSB)
D7

D14
D6

D13
D5

D12
D4

D11
D3

D10
D2

D9
D1

D8
DO(LSB)

1110xx

Global gains

1 .
2

D15(MSB)
D7

D14
D6

D13
D5

D12
D4

D11
D3

D10
D2

D9
D1

D8
DO(LSB)

1111xx

Threshold
values

1
2

D7

D14(MSB)
D6

D13
D5

D12
D4

D11
D3

D10
D2

D9
D1

D8
DO(LSB)

xx
ADDRESS LSB DECODEt

DEFAULT PIXEL DECODE*

a1

aO

0

0

Red register

Blue register

0

1

Green register

Red register

1

0

Blue register

Green register

1

1

Red, green, and blue

Red, green, and blue

t

Default address
* The address decoding is applicable for default pixel gain in monochrome mode.

~TEXAS

7-26

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC8044
12·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS12B-JUNE 1997

PRINCIPLES OF OPERATION
Table 6. Control Bit Descriptions
REGISTER
Setup
Register 1

BITS

DEFAULT

DESCRIPTION

ENADC

1

ADC standby control:
0= standby
1 = active

BICLIP

0

Bipolar clip enable:
= unipolar clip
1 = bipolar clip

ADCMX

0

ADC MUX control:
= normal operation
1 = ADC output multiplexed to OP

MONO

0

Mono/color select:
= color operation
1 = monochrome operation

DEFPG

0

Select default pixel gain:
= external pixel gain
1 = defaLJlt (internal)

DEFPO

0

Select default pixel offsets:
= external pixel offsets
1 = default (internal)

DNS

0

Select differential/single-ended mode:
= single ended
1 = differential

INVADC

0

ADC output polarity:
= noninverted
1 = inverted

CDS

0

Select correlated double sampling mode:
= normal sampling
1 = CDS mode

00

Pixel offset scaling:
00 = ±O.5 fs
01 = ±0.25 fs
10 =±O.125 fs
11 =±0.0625 fs

10

Output word length select:
00 =8 bits (OPO - OP7 contains output word)
01 = 10 bits (OPO - OP9 contains output word)
10 = 12 bits (OPO - OP11 contains output word)
11 = 16 bits (OPO - OP15 contains output word)

11

Threshold detector operating mode:
00 =Operating on red channel only
01 =Operating on green channel only
10 =Operating on blue channel only
11 = Three channel

01

CDS mode reset timing adjust:
00 = Advance 1 MCLK period
01 =Normal
10 =Retard 1 MCLK period
11 = Retard 2 MCLK periods

00

Monochrome mode channel select:
00 = Red channel
01 =Green channel
10 = Blue channel
11 =Not used

Setup
Register 2
POSCL1,O

WLSEL1,O

THSEL1,O

CDSREF1,O

CHAN1,O

o
o
o

o
o
o
o
o

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-27

TLC8044
12·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 - JUNE 1997
PRINCIPLES OF OPERATION
2

3

4

5

6

7

8

10

9

11

12

13

14

15

16

17

18

19

20

21

22

23

24

MCLK

1\

Video Sample

R, G, B Input Video

I
I
!
!
!
!
--....l-----t---...l----_--...L..-----t----..I.----oH
P

CO;

n+1
/
\
/
\
/
\
I
===:::J--"'C~~==7--"'C~~==7-~C~:!!:==T-';::+l

Y

1\
I
m-2

PSC11-PSCO

n-

n 2

m 1

n-2

bn-2

14---

Pixel Period

-----.I

MCLK

R, G, B Input Video

V''-------,~

1-1_ - - - '

POC11-POCO l=!rn~CEJC::E::X=::>C==X:==:X=::X===C=::¥:
PSCll-PSCO pm~CE:JC::E:=*=::>c=x:=::t=::x===c===*=

OP1S-0PO

bmffi:-Da~XJa:Jt:E:D~:=:r:)oiE!Jt:::ffi:::X::::i~CE:Jt

cco

~----t-l_....Jr---'\..,-_-+:=Z=:::S::==+

I
I

CCl ~\ ___....J~~

~/r--t=~~=~===t

___

I
Figure 15. System Timing - Color Mode

~TEXAS

7-28

n-l

~

I
I
I
I
I
I
I m 3
n-3
bn-3
=::>C==)C==:Jk:=::x==:::C==x:=:x==::>C==*=m:;]X~D::E=:r::*l

CC1 ___"'--'

VSMP

n-l

rn-1
n 1
bn-l
=::>C=)C==:Jk:=::x=:::C==*=::r.i8DC:::ii:DO!~p:a::X~D<::::E:=:r:*l
m 2

n 2
ONE============*===========~====~~=====
~
~
~

OP1S-0PO
CCO

n-l

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC8044
12-81T ANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128-JUNE 1997

PRINCIPLES OF OPERATION
2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

OP1S-0PO

ccot

I
I
I

CClt

I
I
I

114
.. ---tf-~-

II
I';
Pixel Period

MCLK

I
I

VSMP

I

Video Sample

R, G, or B Input
Video

.t i!
I
I

I
I
I

I

I

I

! i

__4-~~~~~__~~~~~

I

I

I

I

I

I

I
I
I

I
I
I

I
I
I

I
I
I

I
I
I

I
I
I

I

I

I

pbbbbbbbb~
h

POCll-POCO

I

I
I

! i! i! i! i! i!

~;--~~~~--~

I

I
I

:1

I
I
I

PSC11-PSCO
ONE

OP1S-0PO

n-

n 1

~

n+

ccot
CClt

t The CC(10) output state is defined via the serial bus in monochrome mode.

Figure 16. System TIming - Monochrome Mode

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-29

TLC8044
12-81T ANALOG-TO"DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128-JUNE 1997

PRINCIPLES OF OPERATION
MCLK

DETOP In Normal Mode
DETOP In Single Channel Mode
(Red Channel Selected)
DETOP In Single Channel Mode
(Green Channel Selected)

--(I,-_.....J..._---l_---l
1

,-----,III..--.1---{
'-----'f---+---,'
~~f---+----,

---.,If---+---+---+---I'
1

1

\'1-1---.,--+---+
1

NOTE A: All thresholds are set to 10 hex.

Figure 17. Timing of Threshold Detector Output DETOP

~ThXAS

7-30

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC8044
12-81T ANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128-JUNE 1997

APPLICATION INFORMATION
running the TLC8044 at 4-megasamples/sec in CDS monochrome mode
The TLC8044 can be set up to provide a 4-megasample/sec throughput when in CDS monochrome mode;
however, the VSMP input must run continuously at 4 MHz.
The following paragraphs describe operation of the TLC8044 in monochrome mode (sampling one channel
only). The maximum sample rate in color CDS mode is 2-megasamples/channel/sec.
In CDS mode, the video signal is sampled both during the reset phase and when video information is present
with timing defined to a VSMP input. The difference between these two samples forms the input to the ADC.
In monochrome mode, all samples are taken from one input video channel. The device is set up as listed in Table
6. See Tables 4 and 5 for offset DAC values in CDS mode.
System timing is shown in Figure 18. MCLK clocks the device at 12 MHz (as normal). VSMP, which controls
the sample rate, is run at 4 MHz. A reset sample is taken on the rising edge of MCLK after VSMP is asserted.
The corresponding video sample is taken on the next MCLK rising edge. Compensation coefficients (pixel offset
and pixel shading) are sampled on the falling edge of MCLK 26.5 periods after the initial reset sample. The
processed digital outputs appear on OPO-OP15 41 .5 MCLK periods after the initial reset sample.
In Figure 18 the system timing diagram shows a negative-going video sample. The polarity of the ADC output
signal can be inverted under control of the serial interface. Setup and hold times are specified in the
recommended operating conditions table.
Table 7. Relevant Register Settings
REGISTER
Setup
register 1

Setup
re9ister 2

t

BITS

VALUEt

ENADC

U

ADC standby control

DESCRIPTION

BICLIP

U

Select unipolar clip

ADCMX

0

ADC MUX control

MONO

1

Monochrome operation

DEFPG

U

Select default pixel gain

DEFPO

U

Select default pixel offsets

DNS

0

Select single-ended mode

INVADC

U

ADC output polarity
Select correlated double sampling mode

CDS

1

POSCL1,O

UU

Pixel offset scaling

WLSEL1,O

UU

Select 12-bit output word

THSEL1,O

UU

Three channel

CDSREF1,O

00

Advance one MCLK period

CHAN1,O

UU

Select channel to be sampled

U = User defined

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-31

000 .........
>::::I:Nr-

~

~»mO

'"

Sl::xJ -

co
g

c'..e;) .....
cml>~
Reset Sample

r

Video Sample

!
T

T

Tit
T

T

T

T

T

T

I

,

1

I

T

T

T

T

z, Z
~Ol>

3l0r""C:::O

"tiC)

r-.=,..
mO
0,

:::;;§
2..t

~~

rrJ(I)

~

OP(l&-O)
CC(O)t

CC(l)t

!: !

i==::::x;
I

I
I
~

x;

g

!: !:

st===x;
~

x;

n ! : 1:: ! : ! : ! : ! §
x;

x;

Xt

I

x;

pI

Pixel Period

t CC(1 ,0) Output state defined via serial bus in monochrome mode
Figure 18. System Timing - CDS Mode at 4-Megasamples/Sec

x:

X

I

Iii

X

t

I
I
I

'$

02
me;)

::$;:;

0»
mr3:Z
l> .....
e;)m

m::xJ

en~

mO
Zm

en."

00
::xJ::xJ
en
."
o
::xJ
en
o

l>
Z
Z
m
::xJ

en

TLC8144
10·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
features

PTPACKAGE
(TOP VIEW)

•

Reset Level Clamp

•

Correlated Double Sampling (CDS)

...... O ...... NM

Clj5j5j5j5

"''<1"'''00 ..... 00 "'Z««««
a. a. a. a. a. a. a.c;I Cl Cl Cl Cl

•

Fine Offset Level Shifting

•

Programmable Gain Amplification

•
•

10-Bit ADC With Maximum 6 MSPS
Digital Post-Processing for Pixel-By-Pixel
Image

OOOOOOOCl()()()()

048 474645 44434241

•

Simple Clocking Scheme

•

Control by Serial or Parallel Interface

•

Hardware Compatible With Extended
Parallel Port (EPP)

•

48-Pin QFP Package

OP2
OP1
OPO
DVDD2
NU
NU

DV
CC2
CCI
CCO
ORNG
NRESET

applications

40393837

1
2
3
4
5

36
35
34
33
32
31
30
29
28
27
26
25

6

7
8
9
10
11
12

CDATA4
CDATA5
CDATA6
CDATA7
MCLK
VSMP

DVDD1
RLC
SCKlRNW
SDI/DNA
SEN/STB
OEB

13 1415 16 171819 20 21 22 2324

•

Document Scanners

•

CCO Sensor Interfaces

•

Contact Image Sensor (CIS) Interfaces

I-

CD:J....J EiCl () Cla.a. a.

rJ)

a:a:a:a:9~iI!:E~~~~

«

CDc;la:

NU - Make no external connection.

description
The TLC8144 integrates the analog signal conditioning required by CCD sensors with a 10-bit ADC and optional
pixel-by-pixel image compensation requiring minimal external circuitry and provides a cost effective,
sensor-to-digital domain system solution.
Each analog conditioning channel provides reset level clamp, CDS, fine offset level shifting, and gain
amplification. The three channels are multiplexed into the ADC. Output from the ADC can either be direct or
passed through a digital post-processing function. The post-processing provides compensation for variations
in offset and luminance on a pixel-by-pixel basis.
The flexible output architecture allows 1O-bit data to be accessed either on a 10-bit bus or a time-multiplexed
8-bit bus. The TLC8144 can be configured for pixel-by-pixel or line-by-line multiplexing operation. Reset level
clamp and/or CDS features can be optionally bypassed. Device configuration is either by a simple serial or 8-bit
parallel interface. The TLC8144 is characterized for operation from O°C to 70°C.
AVAILABLE OPTIONS
TA
O°C to 70°C

PACKAGE
QUAD FLATPACK
TLC8144CPT

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright © 1997, Texas Instruments Incorporated

7-33

\

TLC8144
10·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS158- MAY 1997

functional block diagram
RLC

MID

RINP

RU

RT

RB

RL

MID

VSMP MCLK

RLC

,----------------...L-...L-..%..-----------"1-__

CC(2-o)

~__L~~~_r~---~~-----TI-'m-in~g-co-n-tro-I--------------r---pDv

-+..---j-"""-+-r-HSiHIt-tl

I'<----""--v'

CDATA(7-0)

ORNG
OEB
GINP

-t-..-..,-+j-"""-+-r-HSiHIt-tl

BINP

-+"--+-"""--i--HSiHIt-tl

OP(9--0)

Configurable
Serial/Parallel
Control Interface

PNS
SDI/DNA
SCK/RNW
SEN/STB
NRESET

Terminal Functions
TERMINAL
NAME

NO.

I/O

DESCRIPTION

AGND

18

I
Analog
supply

Analog ground ( 0 V)

AVDD1

17

I
Analog
supply

Positive analog supply (5 V)

BINP

21

I
Analog

Blue channel input video

CC(2-O)

8,9,10

0
Digital

CDATA(7-0)
DGND1

DV

Color code outputs. These outputs indicate from which channel the current output sample was taken.
(R = OOX, G = 01 X, B = 1OX). Two codes are provided per channel.

33-40

I
Digital

Image compensation data read/write at twice the ADC conversion rate

41

I
Digital
supply

Digital ground ( 0 V)

7

0

Data valid output, active low

Digital
DVDD1,2

GINP

30,4

I
Digital
supply

Positive digital supply (5 V)

22

I
Analog

Green channel input video

~TEXAS

INSTRUMENTS
7-34

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC8144
10·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS158 - MAY 1997

Terminal Functions (Continued)
TERMINAL
NAME

NO.

MCLK

32

MID

20

1/0

DESCRIPTION

I
Digital

Master clock. This clock is applied at either six, four, or two times the input pixel rate depending on
the operational mode. MCLK is divided by two internally to define the ADC sample rate, and to provide
the clock source for the digital logic.

0

Buffered midpoint of ADC reference string. Used internally to set DAC reference voltages.

Analog
5,6

Unused

NRESET

NC

12

I
Digital

Reset input, active low. This signal forces a reset of all internal registers in the device.

OEB

25

I
Digital

Output 3-state control. All outputs enabled when OEB = O.

42-48,
1-3

I
Digital
I
Digital

3-state digital 10-bit bidirection bus. There are four modes:

OP(9-C)

ORNG

11

0
Digital

These terminals must be left unconnected.

3-state:
Output 10 bit:
Output 8-bit multiplexed:
Input 8 bit:

when OEB= 1
1O-bit data output from bus
data output on bits OP(9-2) at twice pixel rate
control data input on bits OP(9-2)

Over-range signal, active high. This signal indicates that the current output pixel has exceeded the
maximum or minimum achievable value somewhere within the pixel processing.

PNS

24

I
Digital

Control interface select, parallel (high) or serial (low, default)

RINP

23

I
Analog

Red channel input video

RLC

29

I
Digital

Selects whether reset level clamp is applied on a pixel-by-pixel basis. If RLC is required on each pixel,
then this terminal can be tied high.

15,13,
14,16

'1
Analog

ADC reference voltages. The ADC reference range is applied between VRT (full scale) and VRB (zero
level). VRU and VRL can be used to derive optimum reference voltages from an external 5-V reference.

SCKlRNW

28

I
Digital

Serial interface: serial inteface clock signal
Parallel interface: high = OP(9-2) is output, low = OP(9-2) is input bus

SDI/DNA

27

I
Digital

Serial interface: serial interface input data signal
Parallel interface: high = data, low = address

SEN/STB

26

I
Digital

Serial interface; enable, active high
Parallel interface: strobe, active low

VRLC

19

RU,RT, RB,
RL

0

Selectable analog output voltage for RLC

Analog
VSMP

31

I
Digital

Video sample synchronization pulse. This signal is applied synchronously with MCLK to specify the
point in time that the input is sampled. The timing of internal multiplexing between the R, G, and B
channels is derived from this signal.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265

7-35

TLC8144
10-BITANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS

SLAS158-MAY 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, from DV001, DV002, and AV001 (see Note 1) ................................... 7 V
Digital inputs (see Note 1) ................................................... - 0.3 V to VOO + 0.3 V
Analog inputs (see Note 1) .................................................. - 0.3 V to Vee + 0.3 V
Digital outputs, maximum external voltage applied (see Note 1) .................. - 0.3 V to Vee + 0.3 V
Reference input (see Note 1) ................... : ............................ - 0.3 V to VOO + 0.3 V
Operating temperature range, TA ..................................................... O°C to 70°C
Storage temperature range, Tstg ................................................... -50°C to 150°C
Lead temperature, soldering, 10 sec ................................................... ,.... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating cOnditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the corresponding DGND or AGND terminal.

recommended operating conditions
total device
MIN

Supply voltage, VCC

NOM

MAX

5.25

4.75

digital inputs
MIN

High-level input voltage, VIH

NOM

MAX

UNIT

V

0.8VDD

Low-level inputvoltage, VIL

0.2VOD

V

timing requirements.
input multiplexer
TEST CONDITIONS

MIN

NOM

MAX

UNIT

Setup time, input video before MCLKi, tsu(V)

10

ns

Hold time, input video after MCLKi, theY)

25

ns

Setup time, reset video before MCLKi, tsu(R)

CDS mode only

10

ns

Hold time, reset video after MCLKi, th(R)

COS mode only

25

ns

~TEXAS

7-36

INSTRUMENTS .
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC8144
10·81T ANAlOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLASl58-MAY 1997

timing requirements (continued)
serial interface
MIN

NOM

MAX

UNIT

Cycle time. MCLK. levcl

83.3

ns

Pulse duration. MCLK high. twl (MCLKH)

37.5

ns

Pulse duration. MCLK low. tw2IMCLKL)

37.5

ns

Setup time. CDATA to MCLK.!.

10

ns

Hold time. MCLK.!. to CDATA

30

ns

Setup time. VSMPi to MCLKi. tsulD)

10

ns

Hold time. MCLKi to VSMP.!.. th(D)

10

ns

Cycle time. SCK. Ievc2

83.3

ns

Pulse duration. SCK high. tw3(SCKH)

37.5

ns

Pulse duration. SCK low. tw41SCKLl

37.5

ns

Setup time. SDI to SCKi. tsu(S)

10

ns

Hold time. SCKi to SDI change. thiS)

10

ns

Setup time. SCKi to SENi. tsulSCE)

20

ns

Setup time. SEN.!. to SCKi. tsu(SEC)

20

ns

Pulse duration. SEN high. twISEN)

50

ns

electrical characteristics, Voo = 5 V, GND = 0 V, TA = full range (unless otherwise noted)
total device
MIN

PARAMETER
ICC

Supply current. active

ICC

Supply current. standby

TYP

MAX

110

140

UNIT
mA

10

15

mA

TYP

MAX

digital inputs
MIN

PARAMETER

UNIT

IIH

High-level input current

1

I1A

IlL

Low-level input current

1

!1A

Ci

Input capacitance

10

pF

digital outputs
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

IOH=-1 mA

VOL

Low-level output voltage

IOL=l mA

IOZ

High impedance output current

MIN

TYP

MAX

UNIT
V

VDD-0.75
0.75
1

V

!1A

Input multiplexer
PARAMETER

MIN

Channel-to-channel gain matching
VICR

Common mode input voltage

0.5

TYP

MAX

0.5%

5%
4.5

UNIT
V

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

7-37

TLC8144
10·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS

SLAS158-MAY 1997

=

electrical characteristics, VDD 5 V, GND

=0 V, TA =full range (unless otherwise noted) (continued)

reference string
MAX

UNIT

:?:

Impedance, RT to RB

595

1105

(1

Z

Impedance, RU to RL

1190

2200

(1

Vref(RT)

Reference voltage, top

Vref(RB)
Vref(DAC)

PARAMETER

MIN

TEST CONDITIONS

TYP

VI(RU) = 5 V,

VI(RL)= OV

3.4

3.5

3.6

V

Reference voltage, bottom

VI(RUJ_ = 5 V,

VICRLl = 0 V

VI(RU) = 5 V,

VI(RL) = OV

1.5
2.5

1.6
2.525

V

DAC reference voltage

1.4
2.475

.

V

a-bit DACs
P~RAMETER

MIN

Resolution

TYP

MAX

UNIT

Bits

8

Zero-scale voltage

mV

Vref(DAC) -10

Vref(DAC) +10

0

10

mV

Full-scale voltage error
Differential nonlinearity (DNL)

0.1

<1

LSB

Integral nonlinearity (INL)

0.4

1

LSB

10-bit ADC
TEST CONDITIONS

PARAMETER

fs

MIN

TYP

MAX

UNIT

6

MSPS

10

Resolution

Bits

Sampling rate
Full-scale transition voltage at xlNP

Single-ended mode,
VI(xINN) = 2.5 V,
DAC code = OOOH

3.5

V

Zero-scale transition voltage at xlNP

Single-ended mode,
VI(xINN) = 2.5 V,
DAC code = OOOH

1.5

V

Differential nonlinearity (DNL)

~

Integral nonlinearity (INL)

-1

1

LSB

-2

2

LSB

UNIT

switching characteristics
TYP

MAX

tpd(D) .

Propagation delay time, MCLK,!. to output valid

25

75

ten(PZE)

Enable time, output, OE,!. to data valid

25

75

ns

tdis(PEZ)

Disable time, output, OEito high impedance

10

25

ns

PARAMETER

~TEXAS

7-38

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MIN

ns

TLC8144
10-81T ANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS158 - MAY 1997

PARAMETER MEASUREMENT INFORMATION
MCLK
tsu(O)

VSMP, RLC

I'

.:. ·1 th(oj

_----J~

R,G,B Video Inputs
(COSR1 = 0, COSRO = 0)

.1 •• 1 t h(Ol

I

I

I

tsu(V) I:'

·1'

: \\...-+1--

.~th(V)

I

'1\

:

I+-- tsu(R) -I I

I

~ideo Inputs _"l"\____ts_u.;..(V.;..)....:._....:.-+p.,.-th.;,.(V.;,.)""'1_-O/__~_th_(R+-~1"IIr'K
=0, COSRO =1 ) ,
I I "
I
I
r.- tsu(R) ~ I

R,G,B

__

\

R,G,B Video Inputs
(COSR1 = 1, COSRO = 0)

i'

tsu(V)

I

I
I'

tsu(V)

·i·;

I

I

'1\ tSU(~)

---I~th(Rl

\\:v

R,G,B Video Inputs
(COSR1 = 1, COSRO = 1)

, l
I

~ tsu(R) -01 I

I

I I
•• ·1

th(V)

tsu{V)

I
I<---

·1· tth(V)

""--.-....;ts~U~(~I.:..).......1:. _:_._~+-:~th(V)

I -I 10- th(R~

th(V)

:1.

I

1

(COSR1

I

I

tsu(V)

tsu( R)

I

I
:.

I
I·

.

I

~.
l

I

I

~..~th(V)

N"'----__Y

----01 I -

-oj ~ th(R)

Figure 1. Detailed Video Input Timing - Modes 1 and 2

MCLK

VSMP,
RLC

I
I tsu(O) ill I
III I
I
I

t

~tSU(O)~
COATA
(7-0)

I
I
I\. I
I, I

I

~tSU(O)~

i4tSU(O~:

14tsU(O)~:

~tSU(O)~:

I

I~-.I......,.I ~_......... I,.-_'-\. ~_"""""

'X

I ~----~~------

tp(O)~

I

""---_oJ

l+-

'\1'---oJ

\~---------~I---------I
I

CC1

~

I
I
I
I

I

th(D)

Green

CC2

I
I
I

~ ~I

----;----+----+1-......1
,.-_'-\. ,.----i~1

I
~I

____~___~)r--------~~\...____
Figure 2. Detailed Digital Timing - Modes 1 and 2

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-39

TLC8144,
10-BIT ANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS158-MAY 1997

PARAMETER MEASUREMENT INFORMATION
MCLK

I
~tsU(D)~

!

VSMP, RLC

I
I
I
I
I
I
I

! 'K

th(D)~

=

t-

tsu(D)

!

tj4 tj

j4

tsu(V)

R,G,B Input Video
(CDSR1 0, CDSRO =0)

I
I

!'K

th(D)~

I
I tsu(V)
I
I

th(V)

}1

'\

I
I
I
I
I
I

-+j

~4

14

Nr

~~ "1

14-- tsu(R)

~I

th(V)

Y

th(R)

Figure 3. Detailed Video Input Timing - Mode 3

MCLK

I

~SU(D) 14

I

\

\ '------+1--'
i

VSMP, RLC

tsu(D)

I1

I
14 I

I
.,. .1

th(D)

1~li--\" - - - -

==x

tsu(D)

)K Word;2 X

Word 1

I

I

th(D) ~

tp(D)

---I

I+--

,,'--_ _----...II

I

Word 2

I I

jt"-tf-

th(D)

th(D)

r-

=><-------.:-t-P(D-)...Jj<

X

Word 1

I I

OP(9-{)

CC(O)

I
th(D)

I
tsu(D) I
I
I
----tI ~ i+--- tsu(D) ~ I+- tsu(D) -..I
....----.....1.'"""'\1
' I
I
' 1,..-----

* - - 1

CDATA(7-O)

.,..!

;
tp(D)

1

'\

--j-I

X

I 1"-----~ th(D)

""DJ

1)~

.

},..~---I I

'X'--__

Figure 4. Detailed Digital Timing - Mode 3
MCLK

1

~

j+- th(D)

14- tsu(D) -+I I

R,G,B Input Video

J

Reset

'\

!

\

VSMP, RLC

\

Video

7

tSU(V)~

I
I
I
I

II
I
I

1IJj4

}th(V)

Figure 5. Detailed Video Input Timing - Mode 4

~TEXAS

7-40

\

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

tsu(V){

I
I
I
I
I
I
I
I
IIJ/4

I

l/

h

(V)

TLC8144
10-81T ANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS158-MAY 1997

PARAMETER MEASUREMENT INFORMATION

MCLK
I

~SU(O) I..

VSMP, RLC

1

~:
1

I
tsu(O)

COATA(7-O)

th~O)

tSU(O)~
1
1

1
1
1

~

* --.jX*I

1
1
1

1
1

~
2

th(O)

-.I

tsu(O)

1

th(O) ~
tSU(O)
1

¥

2
I

~

I

1
1
1

~
I"

~

~

1

J1

I.-

tp(O)

tp(O)X*-

1
1

~

II

1 th(O) tt ~
1
1 14

~

::x:::x

1
1
1

"II·
~

th(O)..1

:..

1
1
~ 1-1
·1, 1
,

i

\

th(O) ~
tSU(O) 1

¥

JI

th(O)

1
1
1
1
1
1

r---

I

\.

~
1

~

>C

1

~

~

1

tSU(O)

tP(O)~-

tp(O)Xi+--

OP(9-0)

Figure 6. Detailed Digital Timing - Mode 4

SCK
th(S)
tSU(S):"
SOl

X

X

--+I
.,

,I,.1

X

X

X

X
:

tsu(SCE)

I..

tw(SEN)~
, ,

SEN

-n
.,

,..

1
1

tI

tsu(SEC)

Figure 7. Detailed Timing for Serial Interface

-!!1 TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-41

TLC8144
1O-SIT ANALOG~TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS15B- MAY 1997

PRINCIPLES OF OPERATION

sample and hold, offset DACs, and programmable gain amplifier
Each analog input (RINP, GINP, BINP) of the TLC8144 consists of a sample and hold (S/H), a programmable
gain amplifier (PGA), and a dc offset correction block. The operation of the red input stage is summarized in
Figure 8.
RINP --e----I
VADe

I

RS

vMID
Figure 8. Sample and Hold Amplifier

" The sample and hold block can operate in two modes of operation, CDS (correlated double sampling) or single
ended. In CDS operation, the video signal processed is the difference between the voltage applied at the RINP
input when the reset signal (RS) occurs, and the voltage at the RINP input when video signal (VS) occurs. This
is summarized in Figure 9.
.

+-

Vrs (Reset Voltage)
Vvs (Video Voltage)

RS

vs
Figure 9. Reset and Video

When using CDS, the actual dc value of the input signal is not important, as long as the signal extremes are
maintained within 0.5 volts of the chip power supplies. Since the signal processed is the difference between the
two sample voltages, the common dc voltage is rejected.
In single-ended operation, the VS and RS control signals occur simultaneously, and the voltage applied to the
reset switch is fixed at VMID. Therefore, the voltage processed is the difference between the voltage applied to
RINP when VS/RS occurs, and VMID. When using single-ended operation, the dc content of the video signal
is not rejected.
The programmable gain amplifier block multiplies the resulting input voltage by a value between 0.5 and 8.25
which can be programmed independently for each of the three input channels with the serial (or parallel)
interface. Table 1 gives the programmed code versus gain level. The dc value of the gained signal can then be
trimmed 'by the 8-bit plus sign DAC. The voltage output by this DAC is shown as Voffset in Figure 8. The range
of the DAC is (VMID/2).
The output from the offset DAC stage is referenced to the VMID voltage whitch allows the input to the ADC to
maximize the dynamic range, and is shown in Figure 8 by the final VMID addition.

~TEXAS

7-42

"
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265

TLC8144
10·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS158- MAY 1997

PRINCIPLES OF OPERATION
Table 1. PGA Gain Coding
CODE

GAIN

CODE

GAIN

CODE

GAIN

CODE

00000

0.5

01000

2.5

10000

4.5

11000

6.5

00001

0.75

01001

2.75

10001

4.75

11001

6.75

00010

1

01010

3

10010

5

11010

7

00011

1.25

01011

3.25

10011

5.25

11011

7.25

GAIN

00100

1.5

01100

3.5

10100

5.5

11100

7.5

00101

1.75

01101

3.75

10101

5..75

11101

7.75

00110

2

01110

4

10110

6

11110

8

00111

2.25

01111

4.25

10111

6.25

11111

8.25

For the input stage, the final analog voltage applied to the ADC can be expressed as:
VADC

V = G(vs

·
DAC CODE VMID]
VRS ) + [ (1 - 2 x SIgn) x
255
x 2
+ VMID

(7)

where:
VADC is the voltage applied to the ADC
G is the programmed gain
Vvs is the voltage of the video sample
Vrs is the voltage of the reset sample
Sign is the offset DAC sign bit
DAC_CODE is the offset DAC input value
VMID is the TLC8144 generated VMID voltage
clamping

The ADC has a lower reference of VRB (typically 1.25 V) and an upper reference of VRT (typically 3.75 V). When
an ADC input voltage is applied to the ADC equal to VRB, the resulting code is OOOh. When an ADC input voltage
is applied to the ADC equal to VRT, the resulting code is 3FFh.
Both CDS and single-ended operation can be used with reset level clamping. A typical input configuration is
shown in Figure 10.
.

I-,---------~--.

I TLC8144
I
I RINP
I
I
I
I
I
I
I vRLC VMID

RS

Figure 10. Video input

~TEXAS

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-43

TLC8144
10-BIT ANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS1.58 - MAY 1997

PRINCIP'LES OF OPERATION
The position of the clamp relative to the video sample is programmable by CDSREF (0,1) (see Table 6). By
default, the reset sample occurs on the fourth MCLK rising edge after VSMP. The relative timing between the
reset sample (and CL) and video sample can be altered as shown in Figure 11.
MCLK

VSMP -r1/ 11\. II
I II III--+: ' - I
I
I
+
I
I
I
I
VS~I__-+I___t~__I~~I__~I__-+I___'~I__~t

00

01 (DEFAULT)

{

CL

I.r--I\.
II
i\
I
I

I
I
I

I
I
I

I
I
I

RS~I____~I__--~----~I----+t----~I----~I----~I-----

nt

!I !I
I

I
I
{RScli-I!---t!---t----t-!
--~I
CL

10 {

11

II
I
I
I
I

RS

I

I

I

I

I

I

I

I

I

I

Vi\'---~I-----

I
I
I
I
I
I
I
I
I
I
I
I
I
-II~----I~----I~--~~----~----~-----~----~----I
I
I
I
I

+
rlJj\i '---

II
I II II
I
I
{ I
RS41----~I
__--~----~I----.I----~I----41----~t----I
I
I
I
I
I
I
CL

Figure 11. Reset Sample and Clamp Timing

When the clamp pulse is active, the voltage on the TLC8144 side of Cin, i.e. RINP, is forced to be equal to the
VRlC clamp voltage. The VRlC clamp voltage is programmable to three different levels with the serial interface.
The programming of the clamp voltage is dependent on the type of sampling selected and the polarity of the
input video Signal. For CDS operation, matching the clamp voltage to the amplitude and polarity of the video
signal is very important, allowing complete use of the wide input common-mode range of the TLC8144. If the
input video is positive going, it is advisable to clamp to VCl (lower clamp voltage). If the video is negative going,
it is advisable to clamp to Vcu (upper clamp voltage). Regardless of where the video is clamped, the offset DAC
is programmed to move the ADC output corresponding to the reset level to an appropriate value to maximize
the ADC dynamic range. For single-ended operation, it is recommended that the clamp voltage is set to Vern
(middle clamp voltage).
Video Input

Clamp Pulse

n

Figure 12. Video Input and Clamp

~1EXAS

7-44

n.

.....n' - - - - - - 'n' - - -

.'--_

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TLC8144
10·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS158 -

MAY 1997

PRINCIPLES OF OPERATION
A reset level clamp is activated when the RlC terminal is high on an MClK rising edge (see Figure 14). By
default, this initiates an internal clamp pulse three MClK pulses later (see Figure 11; Cl). The relationship
between Cl and RS is fixed; therefore, altering the RS position also alters the Cl position (see Figure 11).
Table 6 shows the three possible clamp voltages for the reset level.
EXAMPLE OF OPERATION
PARAMETERS

TEST CONDITIONS

Input video polarity

Positive

Input sampling

CDS

Input voltage amplitude (VvS - VRS)

2V

Programmable gain

x1

Clamping

Yes. VCl = 1.5 V

After the input capacitor, the input signal to the TlC8144 can be represented as shown in Figure 13.

RS

VS

Figure 13. Video and Reset Sampling
Then for a black pixel:
VRS= VCl
VVS= VCl

Assuming that the offset DAC is set to 00 (deCimal):
VADe

= 1 X (VCl - VCl) + [(1 - 2 x 0) x

VADC

= 0 + 0 + VMID

VADe

= VM1D

2~5 VM1D x V~ID] + VMID

(8)
(9)

(10)

An input voltage of VMID corresponds to a code of 512 (deCimal) from the ADC.
To maximize the dynamic range of the ADC input, it is necessary to program the offset DAC code to move the
ADC code corresponding to the black level toward code OOOh.
Hence, set the offset DAC to 204 (decimal) with the sign bit set.
VADC = 1 X (VCl - VCl)

VADC

+

[(1 - 2 x 1) X

~~~VMID X V~ID] + VMID

(11 )

102

= 0 - 255 VMID + VMID

(12)

153

VADC = 255 VMID

(13)

When the VMID is 2.5 V, the ADC input voltage is 1.5 volts, which results in an ADC code of 102 (decimal).

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

7-45

TLC8144
10-81T ANALOG-TO-DIGITAL INTERFACE FOR
p~~~_~~;~~UP~ED DEVICE IMAGE SENSORS FOR SCANNERS
PRINCIPLES OF OPERATION
For a white pixel:
VRS= VCl
VVS = VCl + 2

For a white pixel, using the same offset DAC value, the ADC .input can be expressed as:
VADC = 1 X (VCl

+2-

VCl)

+ [(1 - 2x 0)

X

~g~VMID X V~ID] + V MID

(14)
(15)

_
153
VADC - 2 + 255 VMID

(16)

When the VMID is 2.5 V, the ADC input voltage is 3.5 volts, which results in a code of 921 (decimal).
Therefore, the output codes from the ADC are between 102 (decimal) and 921 (decimal), which implies that the
ADC input has been set up to maximize the dynamic range available.
MCLK

I

VSMP

RLC

I

Ji\I

r1\I

~

~----

0

r,g,b

I

\

\

I'

r,g,b

I

RLC on this Pixel

Figure 14. RLC Timing

~TEXAS

7-46

r\

J.t_~ '-4t_~\ ~

_-----II'
Input Video

______________J

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

\

\

r,g,b

r

I

No RLC on this Pixel

TLC8144
10·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS158 - MAY 1997

PRINCIPLES OF OPERATION

video sampling options
TLC8144 can interface to CCD sensors using four basic modes of operation (summarized in Table 3). Mode
configurations are controlled by a combination of control bits and timing applied to the MCLK and VSMP
terminals. The default operational mode is color with CDS enabled (mode 1).

color mode definition (mode 1)
Figure 15 summarizes the timing relationships within the color mode. MCLK is applied at twice the required ADC
conversion rate. Synchronization of sampling and channel multiplexing to the incoming video signal is
performed by the VSMP pulse (active high). The three input channels (R, G, B) are sampled in parallel on the
rising edge of MCLK following a VSMP pulse. The sampled data is multiplexed into a single data stream at three
times the VSMP rate and passes through the internal pipeline and emerges on the OP(9-0) bus 20.5 MCLK
periods later.
When the digital post-processing stage is activated, compensation data is clocked into the device at twice the
ADC conversion rate (e.g., two reads per red pixel). The first of the two bytes is required on the CDATA bus 15.5
MCLK periods after the corresponding VSMP pulse. CC(2-0) can be used to control the three lower address
lines of an external RAM. Both correlated double sampling (CDS) and single sample modes of operation are
available.

monochrome mode definitions
One input channel is continuously sampled on the rising edge of MCLK following a VSMP pulse. The user can
specify which input channel (R, G, B) to be sampled by writing to TLC8144 internal control registers. There are
three separate monochrome modes with different maximum sample rates and CDS availability.

details of monochrome mode timing (mode 2)
Figure 16 summarizes the timing relationships. The timing in this mode is identical to mode 1 except for.the
CC(2-O) outputs. One input channel is sampled three times (due to the multiplexer being held in one position)
and passes through the device as three separate samples. Two of the samples can be ignored at the output.
The CC(1 ,2) output terminals reflect the input channel selected (R, G, or B).

details of fast monochrome mode timing (mode 3)
Figure 17 summarizes the timing relationships. This mode allows the maximum sample rate to be increased
to 4 MSPS. This is achieved by altering the MCLK:VSMP ratio to 3:1. In this mode, the timing of RS and CL must
be fixed (see Clamping section).
The sampled video data pass through the internal pipeline and emerge on the OP(9-0) bus 29.5 MCLK periods
later.

If the digital post-processing stage is activated, compensation data are clocked into the device at twice the
internal pixel rate (e.g., two reads per red pixel). The first of the two bytes is required on the CDATA bus 22.5
MCLK periods after the corresponding VSMP pulse.

details of maximum speed monochrome mode (mode 4)
Figure 18 summarizes the timing relationships. This mode allows the maximum sample rate to be increased
to 6 MSPS. This is achieved by altering the MCLK:VSMP ratio to 2:1. The latency through the device is identical
to modes 1 and 2. CDS is not available in this mode.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

7-47

Table 2. Mode Summary

1

cn(')~

~%cr

MODE

1

g
~Z..t

iid
~ c:~lT.I
~~

~rn

DESCRIPTION

Color

CDS
AVAILABLE

Yes

MAX
SAMPLE
RATE

2 MSPS

SENSOR INTERFACE
DESCRIPTION
The three input channels
(R, G, B) are sampled in
parallel at 2 MSPS
maximum. The sampled
data is multiplexed into a
single data stream before
the internal ADC, giving an
internal serial data rate of
maximum 6 MSPS.

I

MCLK max. 12 Mhz.
MCLK:VSMP ratio is 6:1.

Setup register 1: 1Bh

Setup register 1: 19h

!!lOrcO
"UG)
r-.!.t
mO
C,
CC

Monochrome

Yes

2 MSPS

3

Fast
monochrome

Yes

4 MSPS

Identical to mode 2

MCLK max. 12 MHz.
MCLK:VSMP ratio is 3:1.

4

Max Speed
monochrome

Identical to mode 2

MCLK max. 12 MHz.
MCLK:VSMP ratio is 2:1.

6 MSPS

REGISTER CONTENTS
WITHOUT COSt

m
::D

C')

m

o
o

~4r

c:

~r;;f

~~

('!HI)

"'C
r-

m ....

OUTPUT
SIGNALS

Co

10'
m!:!!
<-f
-l>

~

Oz

!!!l>
s:r-

l>0

C')C')

Figure 15. Default Timing in CDS Color Mode

m.!.t
m'

(1)0

z2

(l)C')

0-

::Di!

,,O~
(l)r-

w::Dm
>(1) ::D
wO"

~l>l>-f

IZOr-

S::ZmO

r
CD

?::J:

<:)

r

~:J> a, 0
':'::tI =i ~

s::G):J>

INPUT
SIGNALS

iOO :J>
~Or

c::0

"tiC)

r.!.t

mO
0,

02
mG)

INTERNAL

<-

o~

mr

3:Z

'~

:J>-:"I
G)m

~z'"
~ (I)~.

Zm

m::tl

ORNG

~~~

DV

~t::~
~~

OUTPUT
SIGNALS

~l'T1

~~

C2t

~

CC(2,1)

t

en,,"

00

III\~

H
I

CC(O)

C ()

en~
mo

-+--;---~-T--~--~~--;-~---r--*-~

CC(1)t

Iii

01:00

:!<
~~~
~tI1r.n

~~

~~
~

OUTPUT
SIGNALS

CC(l)t
CC(2)t
CC(2,1)t

l~_i--i-~~~~~+-+-+~~+-++~~~+-+-+-t-r-t-ti~-t-ttii-iti
j(
~
~
~
~
* ~ * * * * i
.

.

o.

0

. .

0

0

,

0

t This example shows function when red channel selected. CC(1) and CC(2) indicate the selected channel (R,G, or 8).
Figure 17. Default Timing in Fast CDS Color Mode

0

0

,

0

,

c:

"0

r-

m .....

Co

c'
m!!!
<-I

-»
Oz
~»

s:::r-

»0

G)G)

m.!.t

(1)0

m'

z2

(l)G')

0-

:xI~

(l)r-

..,,-

O~

(1)

~

"

DESCRIPTION

BIT

DEFAULT
(HEX)

b7

b6

b5

b4

b3

b2

b1

bO

DVMODE

VSMP6M

DEFDV

DEFPO

DEFPG

MONO

CDS

ENADC

CDATOUT

BYPASS

LATCHOP

INVOP

000000

Not used

000001

Setup
register 1

lB

000010

Setup
register 2

00

000011

Setup
register 3

II

000100

Software
reset

00

000101

Reserved

00

1000xx

DAC values

00

1001xx

DAC signs

00

1010xx

PGA gains

00

1011xx

Pixel offsets

00

1100xx

Pixel gain
MSB

80

1101xx

Pixel gain
LSB

00

1110xx

Data valid

01

MUXOP

CHAN[I]

CHAN[O]

CDSREF[I]

CDSREF[O]

PWP[I]

PWP[O]

RLC[I]

RLC[O]

DAC[7]

DAC[6]

DAC[5]

DAC[4]

DAC[3]

DAC[2]

DAC[I]

DAC[O]

PGA[4]

PGA[3]

PGA[2]

PGA[I]

PGA[O]

OFF[5]

OFF[4]

OFF[3]

OFF[2]

OFF[I]

OFF[O]

GAIN[9]

GAIN[8]

GAIN[7]

GAIN[6]

GAIN[5]

GAIN[4]

GAIN[3]

GAIN[2]

GAIN[I]

GAIN[O]

DSIGN

GAIN[II]

GAIN[10]

DV

NOTE 2: Blank entnes can be taken as don't care values.

xx

ADDRESS LSB DECODE

a1

aO

0

0

Red register

0

1

Green register

1

0

Blue register

1

1

Red, green, and blue registers

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-57

TLC8144
1O-BIT ANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS158- MAY1997

PRINCIPLES OF OPERATION
Table 6. Register Definitions
REGISTER

Setup
register 1

Setup
register.2

SIT NO.

SIT NAMES

DEFAULT

0

ENADC

1

ADC standby control: 0 = standby, 1 = active
Select correlated double sampling mode: 0 = normal sampling, 1 = CDS mode

PESCRIPTION

1

CDS

1

2

MONO

0

Mono/color select: 0 = color, 1 = monochrome operation

3

DEFPG

1

Select default pixel gain: 0 = external pixel gain, 1 = internal

4

DEFPO

1

Select default pixel offsets: 0 = external pixel offsets, 1 = internal

5

DEFDV

0

Select default internal data valid: 0 = external DV, 1 = internal

6

VSMP6M

0

Required when VSMP at 6 MSPS: 0 = other mode, 1 = VSMP at 6 MSPS

7

DVMODE

0

External data valid control (see Table 3)

0

MUXOP

0

8-bit output mode: 0 = 10-bit, 1 = 8-bit multiplexed

2

INVOP

0

Inverts ADC output: 0 = non-inverting, 1 = inverting

3

LATCHOP

0

OP bus updated on DV pulse; OP bus updated each sample, 1 = update only on DV
pulse

4

BYPASS

0

Bypass digital post-processing:.o = bypass, 1 = no bypass

5

CDATOUT

0

Data on OP terminals available on COAT terminals: 0 =no, 1 = yes

RLCL(l,O)

01

Reset level clamp voltage
00 = 1.5 V
01 = 2.5 V
10 = 3.5 V
11 = Not used

3,2

PWP(l,O)

00

Parallel word partitioning (see Table 3)

5,4

CDSREF(l,O)

01

CDS mode reset timing adjust
00 = Red channel
01 = Green channel
10 = Blue channel
11 = Not used

7,6

CHAN(l,O)

00

Monochrome mode channel select
00 = Red channel
01 = Green channel
10 = Blue channel
11 = Not used

1

6
7
Setup
register 3

7-58

1,0

-!11
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC8144
10·81T ANALOG·TO·DIGITAL INTERFACE FOR
CHARGE·COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS158-MAY1997

APPLICATION INFORMATION

Standard
SRAM

K==

MSB Address Lin es

~

0

3

CDATA(7--{)

CC(2--{)
OP(9-

w
a:

a..

I-

o

::J
C

oa:
a..

TLC8188
10·BIT, 4MSPS, CIS/LINEAR CCD SENSOR PROCESSOR

~TEXAS

7-62

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC8188
10-BIT, 4MSPS, CIS/LINEAR CCD SENSOR PROCESSOR
SLAS177 ~ DECEMBER 1997

Terminal Functions
TERMINAL
NAME

NO.

I/O
0

DESCRIPTION

OP[0:4]

1-5

DIVDD

6

DIGND

7

OP[5:9]

8-12

0

Three-state bi-directional data bus.

NRESET

13

I

Power-on reset and Interface mode control. If SEN/STB is logic "I" when NRESET goes high
then device is in parallel configuration data input mode. If SEN/STB is logic "0" when NRESET
goes high then device is in serial data input mode.

SOl/DNA

14

I

Serial interface: serial interface input data
Parallel interface: 1 - data, 0 - address

DGND

15

DVDD

16

SCKlRNW

17

I

ADCCLK

18

I

ADC conversion clock input.

OE

19

I

Three-state output enable, active low

SEN/STB

20

I

Serial interface: serial data transfer enable, active high.
Parallel interface: strobe, active low.

SV

21

I

CCD signal level sample pulse input

SR

22

I

CCD reset level sample pulse input, CIS sample pulse input

23

I

CCD input clamp signal

24,25

I

MAl and MAO select the color to which all internal MUX (input, gain, offset) will point. When in
auto-cycling mode, the input mux and internal registers are auto-cycled by the ACYC. The
ACYC is a control signal such as a line start pulse that defines the start of a current scanning
line.

CLAMP
MAl, MAO/ACYC

AGND

Three-state bi-directional data bus, OPO and OPI are output only.
Digital interface circuit supply voltage, +3 V to +5 V
Digital interface circuit ground

Digital ground
Digital supply voltage, +5 V
Serial interface: serial clock
Parallel interface: 1 - OP[9:2] is output bus, 0 - OP[9:2] is input bus

3=
w

:>
w
a:

Analog ground

26
27

BIN

28

I

Blue channel input

GIN

29

I

Green channel input

RIN

30

I

Red channel input

RMO

31

0

Ref- output for external decoupling

RPO

32

0

Ref+ output for external decoupling

D.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

o::)
c

oa:

Analog supply voltage, +5 V

AVDD

D.

I-

7-63

7-64

Mechanical Information

8-1

Contents
Page
Mechanical Information: .................................................. 8-3

-.....

::J

o

-t

3
Q)

...o_.
::J

8-2

MECHANICAL INFORMATION

MECHANICAL DATA
D (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

rr 1r-

14 PIN SHOWN

l 0.050 (1,27) 1

14

~

8

14

16

A MAX

0.197
(5,00)

0.344
(8,75)

0.394
(10,00)

A MIN

0.189
(4,80)

0.337
(8,55)

0.386
(9,80)

DIM

0 .-,-02...:,.0.!..:.(0'-',-,51~)
.c..:

1-$-1 0.010 (0,25)@ 1

0.014 (0,35).
8

.

.

-----a-j

---r
I

1

0.244 (6,20)
0.228 (5,80)

0.157 (4,00)
0.150 (3,81)

~7.+---1~rttLJiiUUUiirl~

t

0.069 (1,75) MAX

0.010 (0,2;J
0.004 (0,10)
4040047/ 0 10/96

NOTES: A.
B.
C.
D.

All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012

~TEXAS

INSTRUMENTS .
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-3

MECHANICAL INFORMATION

MECHANICAL DATA
PLASTIC SMALL-OUTLINE PACKAGE

DB (R·PPSO·G**)
28 PIN SHOWN

11

0,38

0,22

I-$-I

0,15

@I

'-'--'--'-----"="-'

15

nl
5,60
5,00-

8,20
7,40

0"T""l"T'T"..,...,...,..,.~ ~

...............

14

~

8

14

16

20

24

28

30

38

A MAX

3,30

6,50

6,50

7,50

8,50

10,50

10,50

12,90

A MIN

2,70

5,90'

5,90

6,90

7,90

9,90

9,90

12,30

DIM

40400651 C 10/95
NOTES: A.
B.
C.
D.

All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150

~TEXAS

INSTRUMENTS
8-4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL INFORMATION

MECHANICAL DATA
DL (R·PDSO·G**)

PLASTIC SMALL·OUTLINE PACKAGE

48 PIN SHOWN

.J

0.299 (7,59)
0.291 (7,39)

o
T"T "T "T "T T "TnT"T T "T "T ~~~~ ~ ~~~~ ~T"T "!"T" !t+- 1_~l

0.420(10,67)
~~~~

! - r' r m - l

A

~

0.020 (0,51)

~

[
t.110 (2,79) MAX

0.008 (0,20) MI.:-J'

Seating Plane

1c:,.1 0.004(0,10) 1-.1

~

28

48

56

A MAX

0.380
(9,65)

0.630
(16,00)

0.730 .
(18,54)

A MIN

0.370
(9,40)

0.620
(15,75)

0.720
(18,29)

DIM

--.l

~-+---hL
~

4040048/C 03/97
NOTES: A.
B.
C.
D.

All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-5

MECHANICAL INFORMATION

MECHANICAL DATA
OW (R-POSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

16 PIN SHOWN

~

16

20

24

28

A MAX

0.410
(10,41)

0.510
(12,95)

0.610
(15,49)

0.710
(18,03)

A MIN

0.400
(10,16)

0.500
(12,70)

0.600
(15,24)

0.700
(17,78)

DIM

~~=

1-$-1 0.010 (0,25) ® 1
9

1ll

0.419 (10,65)
0.400 (10,15)

0.299 (7,59)
0.293 (7,45)

I!------.lJ
8

rfuUilLUJiiUJl~

t

0.104 (2,65) MAX

0.012 (0,30J
0.004 (0,10)

4040000/803/95
NOTES: A.
B.
C.
D.

All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MS-013

~TEXAS

INSTRUMENTS
8-6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL INFORMATION

MECHANICAL DATA
OWB (R-POSO-G28)

2~

PLASTIC SMALL-OUTLINE PACKAGE

11

r-

0,51
0,35

1-$-1

0,25

®I

'--'--'---'----=..l

15

=rl
7,90
7,30

o

L~4

10,60
9,80

~

17,80
17,20

['DDDDDDDDDDDDDtcl ....

"'P....

2,80 MAX

0,05 MIN..1

,c:".

0,15
40402591 B 02195

NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusion.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-7

MECHANICAL INFORMATION

MECHANICAL DATA
FK (S-CQCC-N**)

LEAD LESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

18

17

16

15

14

13

NO. OF
TERMINALS

..

12

11

19

B

A
MIN

MAX

MIN

MAX

20

0.342
(8,69)

0.358
(9,09)

0.307
(7,80)

0.358
(9,09)

28

0.442
(11,23)

0.458
(11,63)

0.406
(10,31)

0:458
(11,63)

20
21

9

22

8

44

0.640
(16,26)

0.660
(16,76)

0.495
(12,58)

0,560
(14,22)

7

52

0.739
(18,78)

0.761
(19,32)

0.495
(12,58)

0.560
(14,22)

68

0.938
(23,83)

0.962
(24,43)

0:850
(21,6)

0.858
(21,8)

84

1.141
(28,99)

1.165
(29,59)

1.047
(26,6)

1.063
(27,0)

BSQ
ASQ

lU'-------<
26

27

28

6
5

234

~. 0.080 (2,03)
~
0.064 (1,63)

I .

0.020 (0,51)
0.010 (0,25)

4040140/0 10/96
NOTES: A.
B.
C.
D.
E.

All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004

~TEXAS

INSTRUMENTS
POST OFFICE ·BOX 655303 • DALLAS. TEXAS 75265

MECHANICAL INFORMATION

MECHANICAL DATA
FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN
Seating Plane

~ =10.004(0,10)
o

-----~

~

__""*_

01~
3

o

0.120 (3,05)
0.090 (2,29)
0.020 (0,51) MIN

~I
0.032 (0,81)
0.026 (0,66)

4

E

1

I + - - - - - - + f - 0.180 (4,57) MAX

18

02/E2

El

---i

9

02/E2

t-+-1==~:::J1d~1

14

13

0.013 (0,33)
1-$-1 0•007 (0,18)

DIE

NO. OF
PINS

**

MAX

MIN

0.385 (9,78)

0.395 (10,03)

0.350 (8,89)

28

0.485 (12,32)

0.495 (12,57)

0.450 (11,43)

44

0.685 (17,40)

0.695 (17,65)

0.650 (16,51)

20

MIN

01/El

@I

02/E2
MAX

MIN

MAX

0.141 (3,58)

0.169 (4,29)

0.456 (11,58)

0.191 (4,85)

0.219 (5,56)

0.656 (16,66)

0.291 (7,39)

0.319 (8,10)

0.356 (9,04)

52

0.785 (19,94)

0.795 (20,19)

0.750 (19,05)

0.756 (19,20)

0.341 (8,66)

0.369 (9,37)

68

0.985 (25,02)

0.995 (25,27)

0.950 (24,13)

0.958 (24,33)

0.441 (11,20)

0.469 (11,91)

84

1.185 (30,10)

1.195 (30,35)

1.150 (29,21)

1.158 (29,41)

0.541 (13,74)

0.569 (14,45)

4040005/803/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018

-!/}

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-9

MECHANICAL INFORMATION

MECHANICAL DATA
FR (S-PDFP-G44)

PLASTIC QUAD FLATPACK

11:

1-$-1

@I

0,40
0,16
0,20 '---'---'----'--"'''-'

23

34

44

22

o

12

10,10

1
4040052/C 11/96

NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. This may also be a thermally enhanced plastic package with leads conected to the die pads.

~TEXAS

INSTRUMENTS
8-20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL INFORMATION

MECHANICAL DATA
PW (R-POSO-G"·)

PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

11. ~:~~

11--$--,-,-1_0,-,10--"=@:...J1

~nl
4,50
4,30

6,60
6,20

..........~ @'--T---h,.

rbDDDDDDd~
~20

MAX

0,05

~

MI~

1~IO,10 ~

8

14

16

20

24

28

A MAX

3,10

5,10

5,10

6,60

7,90

9,80

A MIN

2,90

4,90

4,90

6,40

7,70

9,60

DIM

4040064/E 08/96
NOTES: A.
B.
C.
D.

All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-21

8-22

NOTES

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http://www.tLcom/sc

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Printed in the USA

~TEXAS

INSTRUMENTS

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A052297

•
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SLAD001 A



File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date                     : 2017:08:05 10:53:27-08:00
Modify Date                     : 2017:08:06 18:03:26-07:00
Metadata Date                   : 2017:08:06 18:03:26-07:00
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:b566fa4f-b171-534d-923f-851e3db5155e
Instance ID                     : uuid:10f9e547-1092-b044-975d-ff3ed65c228e
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 1482