1998_Xilinx_Programmable_Logic_Data_Book 1998 Xilinx Programmable Logic Data Book
User Manual: 1998_Xilinx_Programmable_Logic_Data_Book
Open the PDF directly: View PDF 
.
Page Count: 738
| Download | |
| Open PDF In Browser | View PDF |
--------
~XILINX®
The Programmable Logic
Data Book
Xilinx Home Page (WWW):
XDOCS E-mail Document SeNer:
Application SeNice Centers
North America Hotline:
Fax:
Email:
United Kingdom Hotline:
Fax:
Email:
France Hotline:
Fax:
Email:
http://www.xilinx.com/
("Answers" Database, File Download)
xdocs@xilinx.com
send E-mail with help in the header
1-408-879-5199 (USA, Xilinx headquarters)
1-800-255-7778 (North America)
1-408-879-4442
hotline@xilinx.com
(44) 1932-820821
(44) 1932-828522
ukhelp@xilinx.com
(33)1-3463-0100
(33) 1-3463-0959
frhelp@xilinx.com
Germany Hotline:
Fax:
Email:
(49) 89-93088-130
(49) 89-93088-188
dlhelp@xilinx.com
Japan Hotline:
Fax:
Email:
(81) 3-3297-9163
(81) 3-3297-0067
jhotline@xilinx.com
Korea Hotline:
Fax:
Email:
(82) 2-761-4277
(82) 2-761-4278
korea@xilinx.com
Hong Kong Hotline:
Fax:
Email:
Software Authorization and Licensing:
On-Line Authorization:
(85) 2-2424-5200
(85) 2-2424-7159
hongkong@xilinx.com
1-800-624-4782
www.xilinx.com
2100 Logic Drive
San Jose, California 95124
United States of America
Telephone: (408) 559-7778
Fax: (408) 559-7114
On behalf of the employees of Xilinx, our sales representatives, our distributors, and our
manufacturing partners, welcome to our 1998 Data Book, and thank you for your interest in
Xilinx products and services.
As the inventor of Field Programmable Gate Array technology and the world's leading
supplier of programmable logic, we would like to pledge our continuing commitment to
providing you, our users, with the best possible integrated circuit components, development
systems, and technical and sales support.
Over the past year, we have substantially enhanced our product line with the introduction of
the XC4000XL, XC4000XV, and Spartan series of FPGAs, as well as XH3 FpgASIC
Hardwire technology. We have continued to enhance our leading-edge products with new
speed grades and improved pricing. The Alliance and Foundation series products have set
a new standard for functionality and ease-of-use in programmable logic development
systems. You can expect this pace of innovation to continue, and even increase, as we
maintain our leadership role in bringing leading-edge programmable logic solutions to the
market.
We look forward to satisfying all of your programmable logic needs.
Sincerely,
Wim Roelandts
Chief Executive
Officer
Section Titles
1
Introduction
2
Development System Products and CORE Solutions Products
3
CPLD Products
4
FPGA Products
5
SPROM Products
6
3V Products
7
HardWire FpgASIC Products
8
High-Reliability and QML Military Products
9
Programming Support
10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support and Services
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors
Table of Contents
Introduction
An Introduction to Xilinx Products •.....................•...•................ 1·1
Development System Products and CORE Solutions Products
Development Systems: Products Overview ................................... 2-1
Development Systems: Product Descriptions ......•...•.•.•.................. 2-3
CORE Solutions Overview •...•...•....•..... , ..•........•................. 2-13
CPLD Products
XC9500 Series Table of Contents .•.......................................... 3-1
XC9500 In-System Programmable CPLD Family. . . . . . . . . . . . . . • . . . . . • . . . . . • . . . •• 3-5
XC9536 In-System Programmable CPLD. • . . . . . . .. . • . . . . . • . . . . . . . . . . . . . . . . . . . . 3-21
XC9572 In-System Programmable CPLD. . . . .. . . . . . . . . . . . .. . . . . . . . • . . . • . . • . . . . 3-29
XC95108 In-System Programmable CPLD. . . . . . . • . . • . . . . . . . • . . • . . . . • . . . . . . . . . . 3-37
XC95144 In-System Programmable CPLD ...........•.........•...••...•.....• 3-45
XC95216 In-System Programmable CPLD. . . . • . . . . . . • . . • . . . • . .. • . . . . . . . . . . . . .. 3-55
XC95288 In-System Programmable CPLD. .. . . . . . . . . • . . . . . . . . . . . . . . . . . • . . • . . .. 3-65
FPGA Products
XC4000E and XC4000X Series Table of Contents ....•..••.••..•.•.........•.... 4-1
XC4000E and XC4000X Series Field. Programmable Gate Arrays. . . . • . • . • • . . . . . . .• 4-5
XC4000XV Family Field Programmable Gate Arrays ............•.............•. 4-151
XC4000XLT FamilyField Programmable Gate Arrays .•........•....•.....•.•..• 4·159
Spartan and Spartan-XL Families Table of Contents •....•••...........•........ 4-171
Spartan and Spartan-XL Families Field Programmable Gate Arrays ............... 4-173
XC5200 Series Table of Contents. . . . . . . . . . . . . • . . . . . . . • . • . . . • . . . . . . . . . . . . . . .. 4-221
XC5200 Series Field Programmable Gate Arrays. . . • . . . . . . . . . . . . . . . • . . . . . . . . . . . 4-225
~XILINX
XC3000 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-297
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100A/L) ......... 4-299
SPROM Products
XC1701 L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs ... 5-1
XC1700D Family of Serial Configuration PROMs ............................... 5-11
3V Products
3.3 V and Mixed Voltage Compatible Products ................................. 6-1
HardWire FpgASIC Products
Xilinx HardWire™ FpgASIC Overview .......................•................ 7-1
High-Reliability and QML Military Products
High-Reliability and QML Military Products .......•........•.................. 8-1
XC4000X Series High-Reliability Field Programmable Gate Arrays ................ 8-7
XC4000E High-Reliability Series Table of Contents ............................. 8-9
XC4000E High-Reliability Field Programmable Gate Arrays ...................... 8-11
Programming Support
HW-130 Programmer ..........•...................................•.•..•.. 9-1
Packages and Thermal Characteristics
Packages and Thermal Characteristics ....................................... 10-1
Package Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-21
Testing, Quality, and Reliability
Quality Assurance and Reliability . . . . . • . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .. 11-1
Technical Support and Services
Technical Support And Services ............................................ 12-1
Product Technical Information
Product Technical Information Table of Contents .............................. 13-1
XC3000, XC4000, and XC5200: A Technical Overview for the First-Time User ....•.. 13-5
Choosing a Xilinx Product Family ..............................•......•..... 13-7
1/0 Characteristics of the 'XL FPGAs ..•................•.......•.....•....... 13-13
XC4000 Series Technical Information ..•... , ............•...................• 13-15
XC3000 Series Technical Information ........................................ 13-19
FPGA Configuration Guidelines ..........•...•.........•...•....•...•....... 13-31
Configuring Mixed FPGA Daisy Chains. . • . . • . . . . • . • . . . . . • . . . . . . . . • . . . . . . • . . .. 13-39
Configuration Issues: Power-up, Volatility, Security, Battery BaCk-up •............ 13-41
Dynamic Reconfiguration . . . . . . . . . . . . . . . . . . .• . . . . . . . . . • • . . . • • . . . . . . . . . . . . .. 13-45
Metastable Recovery. . . . . . . . . . . . . . • . . . . . . • . . . . . . • • . . . . . . • . . . . . . . . • . . . . . . .. 13-47
Set-up and Hold Times .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . • . . . . .. 13-50
Overshoot and Undershoot ...•.....•...............•..........•..........•. 13-51
Boundary Scan in XC4000 and XC5200 Series Devices ..•....................... 13-52
Index
Book Index .........................•..........•..................•...... 14-1
Sales Offices, Sales Representatives, and Distributors
Sales Offices, Sales Representatives, and Distributors.........................• 15-1
Introduction
1
Introduction
2
Development System Products and CORE Solutions Products
3
CPLD Products
4
FPGA Products
5
SPROM Products
6
3V Products
7
HardWire FpgASIC Products
8
High-Reliability and QML Military Products
9
Programming Support
10 Packages and Thermal Characteristics
11 Testing, Quality,and Reliability
12 Technical Support and Services
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors
Introduction Table of Contents
An Introduction to Xilinx Products
~".
About this Book ....................................................................
Data Sheet Categories .... ',' ........................... : ..........•.. , ...••...
Data Book Contents . : ...........•......... : '....... , ......•...... : .......< . . ..
About the Company . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . ..
Product Line Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . ....
Programmable Logic vs. Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Faster Design and Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Design Changes without Penalty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Shortest Time-to-Market. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Component Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Field Programmable Gate Arrays (FPGAs) ....................................
Complex Programmable Logic Devices (CPLDs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
HardWire devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Serial PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
High-Reliability Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Development System Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Technical Support and Service. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC3000 Series Product Selection Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000 Series Product Selection Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Spartan Series Product Selection Matrix ..........................................
XC5200 Series Product Selection Matrix ..........................................
XC9500 Series Product Selection Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1-1
1-1
1-1
1-2
1-2
1-3
1-3
1-3
1-3
1-3
1-4
1-4
1-4
1-4
1-5
1-5
1-5
1-6
1-6
1-7
1-7
1-8
An Introduction to Xilinx Products
November 10, 1997
About this Book
This Data Book provides a "snapshot in time" in its listing of
IC devices and development system software available
from Xilinx as of late 1997. New devices, speed grades,
package types and development system products are continually being added to .the Xilinx product portfolio. Users
are enco!Jraged to contact their local Xilinx sales representative and consult the WebLiNX World Wide Web site and
the quarterly XCELL newsletter for the latest information
regarding new product availability.
This book covers the current XC4000ElEXlXL, XC4000XV,
XC4000XLT, Spartan, XC5200, XC3000AlL, XC3100AlL,
XC9500, XC1700D/L and XC1701 L.
The product specifications for several older Xilinx. FPGA
families are not included in this Data Book. This does not
imply that these products are no longer available. However,
for new designs, users are encouraged to use the newer
products described in this book, which offer better performance at lower cost than the older technologies. Product
specifications for the older products are available at
WebLlNX, the Xilinx site on the World Wide Web, or
through yourlocal Xilinx sales representative.
Data$h~et Categories
In order to provide the most up-tO-date information, some
component prOducts included in this book may not have
been fully characterized at the time of publication; In these
cases, the AC and DC characteristics included in the data
sheets will be marked as. Advance or· Preliminary information. (Not withstanding the definitions of such terms, all
specifications are subject.to change withOut notice.) These
designations have thefoUowjng meaning:
• Advance -Initial estimates based.onsimulation
•
•
and/or extrapolation from otherspeed grades, devices,
or device families. Use as estimates, but not for final
production.
,
Preliminary - Based on preliminary characterization.
Changes .are possible, but not expected.
. ,.
Final (unmarked) - Specifications not identifiectas
either Advance or Preliminary are to be considered
final.
Data ,Book Contents
Chapter 1 is a general overview of the Xilinx product line,
and is .recommended reading for designers who are new to
the field of high-density programmable logic.
.
November 10,1997
Chapter 2 contains a discussion of the overall design
methodology when using Xilinx programmable logic and
descriptions of Xilinx development system products. This
chapter is placed at the beginning of the book since these
development tools are needed to design with any of the XiIinx programmable logic devices.
Chapter 3 contains the product descriptions for the Xilinx
Complex Programmable Logic Device (CPLD) products,
including the XC9000 series.
Chapter 4 includes the product descriptions for the Xilinx
static-memory-based Field Programmable Gate Array
(FPGA) products, including the XC3000, XC4000, XC5000,
and Spartan series.
Chapter 5 holds the product descriptions for the XC1701L
and XC1700D families of Serial PROM devices. These
Serial PROMs provide a convenient, low-cost means of
storing configuration programs for the' SRAM-based
FPGAs described in Chapter 4.
Chapter 6 is an overview of Xilinx components. appropriate
for 3.3 V and mixed-voltage systems. This chapter will refer
you back to the appropriate product descriptions in the earlier chapters•.,
.
a
Chapter 7 contains brief overview of the HardWire product line. Detailed product· specifications· are available in
separate Xilinx data sheets.
Chapter 8 is an overview of Xilinx High-Reliability/Military
products. Detailed product specifications are available in
separate Xilinl( data sheets.
Chapter 9 describes the HW130· device programmer for
the XC170X series of Serial PROMs and the XC9500
series of CPLDs.
Chapter 10 contains a description of all the physical packages for the various ICproducts, including information
about thethermal characteristics of those packages.
Chapter'11 discusses the testing, quality,.and reliability of
Xilinx component products.
.
Chapter 12. indud$$ a listing of an the technical support
facilities provide.d by Xilinx.
Chapter 13 contains.:additipnal information about Xilinx
components thatis· not .provided .in the. product'speyifications of the
w
..J
..J
..J
0
N
0
0
N
0
0
><
><
><
C')
C')
c
..J
< < < <
"" 0""
0
0
0
C')
10
0
C')
C')
><
~0
<
<
10
0)
""
M
N
0
M
0
><
0
<
<
""
M
0
><
M
0
><
0
C')
0
0
><
><
Ul
w
>11:
w::J
Low CosU
Low Power
::.:!;;c
N
It)
0)
,....
0
0)
Low Voltage
(3.3 V)
High
Performance
High Performance
w
LL
Max Logic Gates (K)
1.5
2
3
4.5
6
1.5
2
3
4.5
6
7.5
>
3
6
Max RAM Bits
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
iii
Typical Gate Range (K)
1-1.5
1.5-2
2-3
3.5-4.5
5-6
1-1.5
1.5-2
2-3
3.5-4.5
5-6
6.5-7.5
2-3
5-6
W
CLBs
64
100
144
224
320
64
100
144
224
320
484
144
320
Flip-Flops
928
I-
Z
C
256
360
480
688
928
256
360
480
688
928
1320
480
Output Drive (rnA)
4
4
4
4
4
8
8
8
8
8
8
4
4
w
JTAG (IEEE 1149.1)
N
N
N
N
N
N
N
N
N
N
N
N
N
!;;c
N
N
N
N
N
N
N
N
N
N
N
N
N
Quiescent Current (rnA)
8
8
8
8
8
8
1.5
1.5
-09
-09
-09
-09
-09
-09
-2
-2
Ul
II:
::J
W
LL
Dedicated Arithmetic
Fastest Speed Grade
0.5/0.02 0.5/0.02 0.5/0.02 0.5/0.02 0.5/0.02
-61-8
-61-8
-6/-8
-6/-8
-6/-8
XC4000 Series Product Selection Matrix
..J
W
Ul
w
(J
XC4000 Series
:>
w
c
g
~
..J
W
0
0
10
W
0
0
co
~
0
..J
..J
~0
~
..J
w
It)
..J
~W
~W
..J
N
0
C')
0
><
""
""0>< ""0 ""0>< 0"">< 0"" 0"" 0"" ""0>< 0 0 0""""><
"">< ""><
><
>< >< ><
0
It)
0
0
,....
0
C')
,....
N
0
0
N
0
co
10
0
..J
..J
..J
N
><
N
It)
0
0
0
><
It)
""><
0
><
10
co
""><
0
0
""><
Ul
w
High Density
High Performance
Select-RAMTM Memory
>11:
w::J
::.:!;;c
w
LL
System Gate Range' (Logic and RAM) (K)
2-5
3-9
4-12
6-15
7-20
10-30 13-40 15-45 18-50 22-65 27-80 33-100 40-130 55-180
>
Logic Celts
238
466
608
770
950
1368
1862
2432
2432
3078
3800
4598
5472
iii
Max Logic Gates, (no RAM) (K)
3
5
6
8
10
13
20
25
28
36
44
52
62
85
W
Max RAM Bits (no Logic)
CLBs - --_..-
3200
6272
61952
73728
100352
100
196
256
324
400
576
784
1024
1024
1296
1600
1936
2304
3136
Flip·Flops
360
616
768
936
1120
1536
2016
2560
2560
3168
3840
4576
5376
7168
Output Drive (rnA)
12
12
12
12
12
12
12
12
12
12
12
12
12
12
JTAG (IEEE 1149.1)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Dedicated Arithmetic
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Quiescent Current (rnA)
10
10
10
10
10
10
10
10
10
10
10
10
10
10
Fastest Speed Grade
-1
-09
-1
-1
-09
-09
-09
-1
-09
-09
-09
-09
-09
-09
I-
z
C
Ul
W
II:
::J
le(
W
LL
8192 10368 12800 18432 25088 32768 32768 41472 51200
7448
'Maximum System gates assume 20% of CLBs used as RAM
1-6
November 10, 1997
~XILINX
Spartan Series Product Selection Matrix
U)
w
0
Spartan Series
:;:
w
c
XCS05
XCS05-XL
XCS10
XCS10-XL
U)
I<:!;;:
w
"-
55
zw
C
XCS30
XCS30-XL
XCS40
XCS40-XL
High Density
High Performance
Select-RAMTM Memory
Low Cost
w
>11:
w=>
>
XCS20
XCS20-XL
System Gate Range' (Logic and RAM) (K)
2-5
3-10
7-20
10-30
13-40
Logic Cells
238
466
950
1368
1862
3
5
10
13
20
25088
Max Logic Gates, (no RAM) (K)
Max RAM Bits (no Logic)
3200
6272
12800
18432
CLBs
100
196
400
576
784
Flip-Flops
360
616
1120
1536
2016
Output Drive (rnA)
12
12
12
12
12
w
=>
l-
JTAG (IEEE 1149.1)
Y
y
Y
y
Y
y
Y
y
y
y
w
Quiescent Current (rnA)
3
3
Fastest Speed Grade
-4
-4
3
-4
3
-4
3
-4
XC5204
XC5206
XC5210
XC5215
U)
II:
e(
"-
Dedicated Arithmetic
,
I
Maximum System gates assume 20% of CLBs used as RAM
XC5200 Series Product Selection Matrix
U)
w
0
:;:
XC5200 Series
w
XC5202
C
U)
w
w=>
High Density
Low Cost
>11:
I<:!;;:
w
"-
Max Logic Gates (K)
Max RAM Bits
55
zw Typical Gate Range (K)
c CLBs/Logic Cells
Flip-Flops
Output Drive (mA)
U)
w
II:
JTAG (IEEE 1149.1)
::>
IDedicated Arithmetic
e(
w
"- Quiescent Current (mA)
Fastest Speed Grade
>
November 10, 1997
3
6
10
16
23
N/A
N/A
N/A
N/A
N/A
2-3
64
256
8
Y
Y
15
-3
4-6
120
480
8
Y
Y
15
-3
6-10
196
784
8
Y
Y
15
-3
10-16
324
1296
8
Y
15-23
484
1936
8
Y
y
y
15
-3
15
-3
1-7
An Introduction to Xilinx Products
XC9500 Series Product Selection Matrix
til
UJ
()
;;;
CPLD Families
XC9536
XC9572
XC95108
XC95144
XC95216
XC95288
4.8
216
216
24
Y
N
6.4
288
288
24
Y
N
UJ
C
til
JTAG
5V ISP
3 Vor5 V I/O
UJ
>0:
UJ::::l
I<:~
...
UJ
~
z
UJ
c
Ui
til
UJ
0:
::::l
~
...
UJ
1-8
Gates (K)
Macrocelis
Flip-Flops
Output Drive (rnA)
JTAG (IEEE 1149.1)
Dedicated Arithmetic
Quiescent Current (rnA)
Fastest Speed Grade
0.8
36
36
24
Y
N
1.6
72
72
24
Y
N
-
-
-5
-7
2.4
108
108
24
Y
N
140
-7
3.2
144
144
24
Y
N
-
-
-
-7
-10
-10
November 10, 1997
Development System Products and
CORE Solutions Products
1
Introduction
2
Development System Products and CORE Solutions Products
3
CPLD Products
4
FPGA Products
5
SPROM Products
6
3V Products
7
HardWire FpgASIC Products
8
High-Reliability and QML Military Products
9
Programming Support
10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support and Services
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors
Development System Products
Table of Contents
Development System Products
Development Systems Products Overview
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Product Overview ..................................................................
Flexible Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Foundation Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Alliance Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Alliance Series Options ........................................................
Xilinx M1 Software Technology ..................................................
Increased Design Performance .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
M1 Technical Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-1
2-1
2-1
2-1
2-1
2-2
2-2
2-2
2-2
Development Systems: Product Descriptions
Development Systems Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Foundation Series: Foundation Base System (PC) ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Foundation Series: Foundation Base-Express System with VHDUVerilog Synthesis(PC) ... . . . . . ..
Foundation Series: Foundation Standard System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Foundation Series: Foundation Express System (PC) ......................................
Alliance Series: Alliance Base (PC or Workstation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Alliance Series: Alliance Standard (PC or Workstation) .....................................
Alliance Series Options (PC) ..........................................................
2-3
2-4
2-5
2-6
2-7
2-8
2-10
2-12
CORE Solutions Overview
Background .......................................................................
CORE Solutions Products ............................................................
CORE Solutions Data Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ordering Information ..........................................................
LogiCORE Products ................................................................
Xilinx CORE Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Xilinx PCI Solutions ...........................................................
Xilinx DSP Solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . ..
Acquiring LogiCORE Products ..................................................
AliianceCORE Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AllianceCORE Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Acquiring AliianceCORE Products ...............................................
2-13
2-13
2-13
2-13
2-13
2-14
2-14
2-14
2-14
2-14
2-15
2-15
Development Systems Products
Overview
December 10, 1997 (Version 2.0)
Product Overview
Introduction
Leading-edge silicon products, state-of-the art software
solutions and world-class technical support make up the
total solution delivered by Xilinx. The software component
of this solution is critical to the success of every design
project. Xilinx Software Solutions provide powerful tools
which make designing with programmable logic simple.
Push button design flows, integrated on-line help, multimedia tutorials, plus high performance automatic and autointeractive tools, help designers achieve optimum results.
And the industry's broadest array of programmable logic
technology and EDA integration options deliver unparalleled design flexibility.
Product Overview
Xilinx Software Solutions are available in two different product series making it easy for designers to choose the right
system for their needs. These two series support the industry's broadest array of programmable logic IC families. This
allows users to standardize their design tools for all programmable logic applications and use these tools to realize
the benefits of the industry's highest performance and density FPGAs and CPLDs. It also makes it easy to migrate
designs to new technologies and re-use existing designs in
new applications.
The Xilinx Foundation Series provides designers with a
complete, ready-to-use solution for programmable logic
design.
The Xilinx Alliance Series provides designers powerful
integration of Xilinx design tools with their existing EDA
environment.
Flexible Configurations
Xilinx Software Solutions are available in two device configurations giving designers a cost-effective way to match
their tools to the design methodologies they require. These
configurations are available for both the Foundation and
Alliance Series.
•
Base configurations provide push button design flows
and support a broad array of FPGA and CPLD devices
targeted for low density and high volume applications.
• Standard configurations combine push button flows with
powerful auto-interactive tools. These tools give
designers more influence and control over
implementation while maintaining the benefits of design
automation. Standard configurations include support for
December 10, 1997 (Version 2.0)
all Xilinx programmable logic devices, featuring the
industry's largest FPGA devices.
Foundation Series
The Xilinx Foundation Series provides everything required
to design a programmable logic device in an easy-to-use
environment. This fully integrated tool set allows users to
access design entry, synthesis, implementation and simulation tools in a ready-to-use package. Every step in the
design process is accomplished using graphical tool bars,
icons and pop-up menus supported by interactive tutorials
and comprehensive on-line help.
The Xilinx Foundation Series features support for standards based HDL design. All configurations support the
popular ABEL language, with integrated compilers optimized for each target architecture. MOL configurations
include integrated VHDUVerilog synthesis from Synopsys
with tutorials and graphical HDL design entry tools to turn
new users into experts quickly and easily.
HDL Configurations
HDL configurations of the Foundation Series contain integrated VHDUVeriiog synthesis and graphical interactive
HDL entry tools with the following features:
•
•
On-line tutorial teaches the art of VHDL design.
Xilinx HDL Editor provides color coding, syntax
checking and single click error navigation making it
easy to create and debug VHDL, Verilog and ABEL
designs.
• Graphical State Machine editor makes the design of
simple or complex state machines simple and intuitive.
• HDL Language Assistant provides libraries of common
functions with optimized VHDL, Veri log and ABEL code.
• FPGA and CPLD specific synthesis and optimization
from Synopsys tools produce high-utilization, highperformance results
Alliance Series
The Alliance Series provides powerful and integrated
design tools for users who require a quality solution for their
chosen EDA design solution. With the Alliance Series,
users can choose from a wide range of design techniques
including schematic capture, module-based design and
HDL design solutions. With standard based design interfaces including EDlF, VITAL, VHDL, Verilog and SDF, this
series provides maximum flexibility, portability, mixed vendor support, and design reuse.
2-1
I
Development Systems Products Overview
Quality integration with leading EDA vendors such as
ALDEC, Exemplar, Cadence, Mentor Graphics, Model
Technology, OrCAD, Synopsys, Synplicity, Veribest and
VIEWlogic provide tightly-coupled environments that make
it easy to move through the design process and through a
mixed EDA vendor flow. The EDA vendors are supported
through the Xilinx Alliance Program, insuring high quality
tools and accuracy of results. Information on Xilinx Alliance
Program vendors can be found on the Xilinx WEB page
www.xilinx.com.
The Alliance Series includes an enhanced set of easy-touse features including, design manager, flow engine, installation, on-line documentation, and answer database. In
addition, the Alliance Series includes a powerful and complete implementation toolset, LogiBLOX (next generation
module generation), fully integrated EDA vendor support,
and a powerful gate-level optimizer. Also included are new
advanced place and route software that has incremental
design capabilities and SMARTspecs (a robust timing constraint language). Users can achieve up to 25% performance improvements with no additional elapse time
through the use of the Alliance Series Turns Engine. The
Turns Engine uses networked workstations to run multiple
place and route passes for a single design. This feature is
included with the Alliance Series BASE and Standard workstation development systems. The libraries and interface
provide Xilinx Unified Library schematic symbols, HDL synthesis libraries, VITAL(VHDL) and Verilog simulation models with timing information and translators through a
standard netlist format. All of these tools provide a complete spectrum of high density design methodologies from
fully-automatic to hand-crafted and close integration with
Xilinx LogiCores and AliianceCore partners.
Alliance Series Options
VIEWlogic Workview Office Development System options
as part of the Alliance Series are intended for users who
want the integration of a complete solution with the power
to access board and system level design tools. These products include VIEWlogic Workview Office schematic capture
and simulation tools.
Xilinx M1 Software Technology
Ml technology represents Xilinx's next generation software
technology. This advanced technology developed as a
result of the Xilinx merger with NeoCAD Inc., enables digital system designers to increase design performance,
leverage standards-based, high-level design methodologies and quickly receive new software features and device
support through Xilinx Foundation Series and Alliance
Series software solutions.
which delivers push-button design flows and incremental
design capabilities. These Xilinx-exclusive capabilities
leverage results from previous design iterations to reduce
runtimes and shorter design iterations to less than ten minutes. As engineers design complex circuits incrementally,
this technology allows them to work in their preferred methodology.
Ml Technology also delivers advanced timing driven placeand route capabilities to deliver maximum design performance through push-button flows.
M1 Technical Benefits
Maximum Design Performance
Ml technology enables the user to achieve maximum
design performance by providing a unique combination of
advanced algorithms and interactive tools. Designer productivity is greatly enhanced through use of simple, pushbutton flows and optional auto-interactive tools. Customer
testing has shown that Ml technology used with
XC4000XUXV devices results in 70 percent shorter run
times, up to a 25 percent performance improvement, and
the ability to place and route devices with up to 100 percent
utilization with a push-button flow.
Modular Software System
The modular architecture of the Xilinx Ml technology
allows rapid delivery of incremental technologies, new features, device support, and versions of its leading software
product families. New feature sets can now be released
independently resulting in users' ability to quickly complete
designs without having to re-Iearn new tools as enhancements are made. The investment Xilinx has made in the Ml
technology ensures that the continuous delivery of innovative device architectures and improved software solutions
can be done more rapidly, and predictably than previous
software versions.
Methodology Flexibility
High-level design methodologies are becoming the methodology choice for the design of complex programmable
logic. Ml technology delivers programmable logic specific
high-level flows. The flows provide high-quality, high performance optimized results, and afford fast, flexible design
changes and iterations to match the way engineers design.
Designers employ a mixture of graphical and languagebased design entry methods while providing an easy-tolearn environment for Hardware Description Language
(HDL) based design. Xilinx recognizes that design environments are variant and, therefore, has created a flexible system enabling the customer to choose the best methodology
for their environment or design challenge.
Increased Design Performance
The Ml technology provides dramatically improved design
performance through advanced place-and-route software
2-2
December 10, 1997 (Version 2.0)
Development Systems:
Product Descriptions
November 25, 1997 (Version 2.0)
Development Systems Descriptions
It's simple to order a Xilinx Development System. Just
choose a Foundation or Alliance Series and a few options.
Give your local Xilinx Sales Office a call for information
about our evaluation kits.
I
Foundation Series
•
•
•
Foundation
Foundation
Foundation
Foundation
Base System (PC)
Base-Express System (PC)
Standard System (PC)
Express System (PC)
Alliance Series
•
•
Alliance Base (PC or Workstation)
Alliance Standard (PC or Workstation)
Alliance Series Options
VIEWlogic Workview Office Standard Development
System Options (PC)
November 25, 1997 (Version 2.0)
2-3
Development Systems: Product Descriptions
Foundation Series: Foundation Base System (PC)
Overview
The Foundation Series provides a complete, ready-to-use
design system for the design of Xilinx programmable logic
devices. The Foundation Base System provides design
entry (schematic and Abel HDL), simulation, and device
implementation tools for a broad array of FPGA and CPLD
devices targeted for low density and high volume applications.
System Features
•
•
•
•
•
•
•
Project manager
Schematic editor
Integrated HDL editor with support for the Abel 6 HDL
Functional and timing simulator
EDIF, VHDL (VITAL compliant), and Verilog I SDF
design interfaces
Device Implementation software for Xilinx CPLDs and
FPGAs
Comprehensive on-line help, on-line documentation,
and software tutorials
Software maintenance, including hotline support and
software updates
Device Support
•
•
CPLDs:
- XC9500
FPGAs:
XC4000E/X up to XC401 OE/X
Spartan
XC3xOOAlL
XC5200 up to XC521 0 FPGAs
Package Features - Foundation Base
System
Feature
FND
FND
BSX
EXP
CPLD Devices
FPGA Devices
Libraries and Interface
Schematic Editor
HDL Editor
Graphical State Editor
ABEL 6 Entry I Synthesis
VHDL Entry I Synthesis
Verilog Entry I Synthesis
Schematic-centric Synthesis
HDL-centric Synthesis
Simulator
Device Implementation
Maintenance
11/12197
Notes:
1. Spartan, XC3xOONX, XC4000E/X up to
XC4010E/X, and XC5200 up to XC521 O.
2. A period of maintenance is included with new
design system licenses, after which annual
maintenance contracts may be purchased.
Contact your Xilinx sales representative for more
information.
Required Hardware Environment
•
•
•
Windows 95 and Windows NT 4.0 compatible PCs
Minimum memory requirements: 32 MB RAM, 32-64
MB Virtual Memory
CD-ROM drive
2-4
November 25, 1997 (Version 2.0)
~XILINX
Foundation Series: Foundation Base-Express System with VHDUVeriiog
Synthesis(PC)
Overview
The Foundation Series provides a complete, ready-to-use
design system for the design of Xilinx programmable logic
devices. The Foundation Express System incorporates
advanced synthesis technology from Synopsys, and provides design entry (schematic and HDL), VHDL and Verilog
synthesis, simulation, and device implementation tools for a
broad array of FPGA and CPLD devices targeted for low
density and high volume applications.
System Features
•
•
•
•
•
•
Project manager
Schematic editor
Integrated HDL editor with support for VHDL, Verilog,
and Abel 6 HDL
VHDL and Verilog synthesis, including compilation and
optimization
Functional and timing simulator
EDIF, VHDL (VITAL compliant), and Verilog I SDF
design interfaces
Device implementation software for Xilinx CPLDs and
FPGAs
Comprehensive on~line help, on-line docUmentation,
and software tutorials
Software maintenance, including hotline support and
software updates
Device Support
•
•
Package Features - Foundation
Base-Express System
Feature
CPLD Devices
FPGA Devices
Libraries and Interface
I
Schematic Editor
HDL Editor
Graphical State Editor
ABEL 6 Entry I Synthesis
VHDL Entry I Synthesis
Veri log Entry I Synthesis
Schematic-centric Synthesis
HDL-centric Synthesis
Simulator
Device Implementation
Maintenance
11/12/97
Notes:
1. Spartan, XC3xOOAlL, XC4000E/X up to
XC4010E/X, and XC5200 up to XC521 O.
2. A period of maintenance is included with new
design system licenses, after which annual
maintenance contracts may be purchased.
Contact your Xilinx sales representative for more
information.
CPLDs:
- XC9500
FPGAs:
XC4000E/X up to XC401 OE/X
-
Spartan
XC3xOONL
XC5200 up to XC521 0 FPGAs
Required Hardware Environment
•
•
•
Windows 95 and Windows NT 4.0 compatible PCs
Minimum memory requirements: 32 MB RAM, 32-64
MB Virtual Memory
CD-ROM drive
November 25, 1997 (Version 2.0)
2-5
Development Systems: Product Descriptions
Foundation Series: Foundation Standard System (PC)
Overview
The Foundation Series provides a complete, ready-to-use
design system for the design of Xilinx programmable logic
devices. The Foundation Standard System provides design
entry (schematic and Abel HDL), simulation, and device
implementation tools for all Xilinx CPLDs and Xilinx
FPGAs.
Package Features - Foundation Base
System
System Features
Project manager
Schematic editor
Integrated HDL editor with support for the Abel 6 HDL
Functional and timing simulator
EDIF, VHDL (VITAL compliant), and Verilog I SDF
design interfaces
• Device implementation software for Xilinx CPLDs and
FPGAs
• Comprehensive on-line help, on-line documentation,
and software tutorials
• Software maintenance, including hotline support and
software updates
•
•
•
•
Device Support
•
•
CPLDs:
- XC9500
FPGAs:
XC4000E/X
-
Notes:
1. Spartan, XC3xOOAlL, XC4000EIX up to
XC4010ElX, and XC5200 up to XC5210.
2. A period of maintenance is included with new
design system licenses, after which annual
maintenance contracts may be purchased.
Contact your Xilinx sales representative for more
information.
Spartan
XC3xOOAlL
XC5200
Required Hardware Environment
•
•
•
Windows 95 and Windows NT 4.0 compatible PCs
Minimum memory requirements
- Small Devices « 1OK gates): 32 MB RAM, 32-64
MB Virtual Memory
Medium Devices (10K to 30K gates): 64 MB RAM,
64-128 MB Virtual Memory
- Large Devices (> 30K gates): 128 MB RAM, 128-256
MB Virtual Memory
CD-ROM drive
2-6
November 25,1997 (Version 2.0)
~XILINX
Foundation Series: Foundation Express System (PC)
Overview
The Foundation Series provides a complete, ready-to-use
design system for the design of Xilinx programmable logic
devices. The Foundation Express System incorporates
advanced synthesis technology from Synopsys, and provides design entry (schematic and HDL), VHDL and Verilog
synthesis, simulation, and device implementation tools for
all Xilinx CPLDs and Xilinx FPGAs.
System Features
•
•
•
•
•
•
•
•
Project manager
Schematic editor
Integrated HDL editor with support for VHDL, Verilog,
and Abel 6 HDL
VHDL and Verilog synthesis, including compilation and
optimization
Functional and timing simulator
EDIF, VHDL (VITAL compliant), and Verilog / SDF
design interfaces
Device implementation software for Xilinx CPLDs and
FPGAs
Comprehensive on-line help, on-line documentation,
and software tutorials
Software maintenance, including hotiine support and
software updates
Device Support
•
•
Package Features - Foundation Base
System
Feature
CPLD Devices
FPGA Devices
FND
BAS
;/
;/1
Libraries and Interface
Schematic Editor
;/
;/
HDL Editor
;/
Graphical State Editor
;/
ABEL 6 Entry / Synthesis
;/
FND
STD
FND
BSX
..J
..J
..J
..J
;/
..J
;/1
..J
;/
..J
..J
..J
..J
..J
..J
..J
VHDL Entry I Synthesis
Verilog Entry / Synthesis
Schematic-centric Synthesis
;/
;/
;/
HDL-centric Synthesis
Simulator
;/
Device Implementation
Maintenance"
..J
..J
..J
..J
..J
..J
..J
..J
FrttPI
,el(P
"::,.j:
i"':";""
I::'" ..
,.:} ,:',
!'f,N:
1<;/,:
l<: ,':;i:
:';';:',.,.',
1',;,;:<:
:;::1
:~::
,,:;';0'
::;~,:
>'1/.:,
':1/,'
11/12/97
Notes:
I. Spartan, XC3xOOAlL, XC4000E/X up to
XC4010E/X, and XC5200 up to XC521 O.
2. A period of maintenance is included with new
design system licenses, after which annual
maintenance contracts may be purchased.
Contact your Xilinx sales representative for more
information.
CPLDs:
- XC9500
FPGAs:
XC4000E/X
- Spartan
- XC3xOOAlL
XC5200
Required Hardware Environment
•
•
•
Windows 95 and Windows NT 4.0 compatible PCs
Minimum memory requirements
Small Devices « 10K gates): 32 MB RAM, 32-64
MB Virtual Memory
Medium Devices (10K to 30K gates): 64 MB RAM,
64-128 MB Virtual Memory
Large Devices (> 30K gates): 128 MB RAM, 128-256
MB Virtual Memory
CD-ROM drive
November 25, 1997 (Version 2.0)
2-7
I
Development Systems: Product Descriptions
Alliance Series: Alliance Base (PC or Workstation)
Overview
Next generation FPGNCPLD design solutions leveraging
"Open Systems" integration with premier EDA partners for
devices up to 10,000 gates.
Base System Features:
•
•
•
•
•
•
•
•
•
•
•
•
EDA Libraries & Interfaces
Design Manager and Flow Engine
LogiBLOX Module Generator
Gate Optimizer
Complete HDL design methodology support
Incremental design capabilities
Place and route utilizing SMARTspecs
Re-entrant router
Multi-pass PAR
Timing Analyzer
Standard netlist and backannotation (EDIF, SDF, VITAL
VHDL and Verilog)
Xchecker Hardware Debugger (workstation only)
Package Includes:
•
•
•
•
•
•
•
•
Alliance Quick Start Guide
Alliance Release Document
Answer Database
Core Technology CD
CAE Libraries CD
On-line Documentation CD with DynaText browser
Hardware Cable
Demoboard
Device Support:
•
Libraries and Interfaces
Cadence
•
Mentor
•
-
Spartan
XC3xOONL
XC5200 up to XC521 0 FPGAs
•
•
HDL Design Solutions (VHDL and Verilog)
Design Compiler, FPGA Compiler II, FPGA Express,
VSS
Vital Simulation models
DesignWare arithmetic modules
• No libraries required to support FPGA Express
VIEWlogic
•
Workview Office schematic capture library and
functional and timing simulation interface
Exemplar
•
Leonardo and Galileo synthesis libraries and interfaces
are available from Exemplar Logic
Synplicity
•
Synplify synthesis libraries and interfaces are available
from Synplicity
Model Technology
•
ModelSim, V-System HDL simulation libraries and
interface
Contact your local EDA sales office to purchase these EDA
tools.
Support and Updates Include:
•
•
•
•
•
•
2-8
Falcon Framework schematic capture library and
ModelSim simulation models
Leonardo synthesis libraries and interfaces are
available from Mentor or Exemplar Logic
Synopsys
•
•
CPLDs:
- XC9500
FPGAs:
XC4000E/X up to XC401 OE/X
Concept schematic libraries and Veri log-XL simulation
models
Answers Database - http://www.xilinx.com or Answers
electronic book included.
Hotline Telephone Support
Apps FAX and E-Mail
Online Documentation
World Wide Web Access
Technical Newletter
Extensive Application Notes
Software Updates (for in-maintenance customers)
A period of maintenance is included with new design
system licenses, after which annual maintenance
contracts may be purchased. Contact your Xilinx
sales representative for more information
November 25, 1997 (Version 2.0)
~XILINX
Required Hardware Environment (PC)
•
•
•
•
•
•
•
•
•
Fully IBM compatible PC486/Pentium
- NEC98 supported
Windows 95, Windows NT 4.0
- Chinese, Korean and Japanese versions
Minimum 300 Mbytes hard-disk space
CD-ROM drive
VGA display
Serial port mouse
One parallel and two serial ports
32 MB RAM (Use additional RAM to increase
performance)
32 MB - 64 MB Virtual Memory
November 25, 1997 (Version 2.0)
Required Hardware Environment
(Workstation)
•
Ultra Sparc (or equivalent)
- Sun OS 4.1.3 and 4.1.4
- Solaris 2.5
• HP715 (or equivalent)
- HP-UX 10.2
• RS6000
- AIX 4.1.5 (no GUls)
• 64 MB RAM (Use additional to increase performance)
• 64MB min Swap Space
• Color Monitor
2-9
I
Development Systems: Product Descriptions
Alliance Series: Alliance Standard (PC or Workstation)
Overview
Libraries and Interfaces
Next generation FPGAlCPLD design solutions leveraging
"Open Systems" integration with premier EDA partners for
unlimited gate capacity.
•
Base System Features:
•
•
•
•
•
•
•
•
•
•
EDA Libraries & Interfaces
Design Manager and Flow Engine
LogiBLOX Module Generator
Gate Optimizer
Full HDL design methodology support
Incremental design capabilities
Place and route utilizing SMARTspecs
Re-entrant router
Multi-pass PAR
Timing Analyzer
Standard netlist and backannotation (EDIF, SDF, VITAL
VHDL and Verilog)
Xchecker Hardware Debugger (workstation only)
Package Includes:
•
•
•
•
•
•
•
Alliance Quick Start Guide
Alliance Release Document
Answer Database
Core Technology CD
CAE Libraries CD
On-line Documentation CD with DynaText browser
Hardware Cable
Demoboard
Cadence
Concept schematic libraries and Veri log-XL simulation
models
Mentor
•
Falcon Framework schematic capture library and
ModelSim simulation models
Leonardo synthesis libraries and interfaces are
available from Mentor or Exemplar Logic
Synopsys
•
•
HDL Design Solutions (VHDL and Verilog)
Design Compiler, FPGA Compiler II, FPGA Express,
VSS
• Vital Simulation models
• DesignWare arithmetic modules
• No libraries required to support FPGA Express
VIEWlogic
•
Workview Office schematic capture library and
functional and timing simulation interface
Exemplar
•
Leonardo and Galileo synthesis libraries and interfaces
are available from Exemplar Logic
Synplicity
•
Synplify synthesis libraries and interfaces are available
from Synplicity
Model Technology
Device Support:
•
•
CPLDs:
- XC9500
FPGAs:
XC4000E/X
-
Spartan
XC3xOOA/L
XC5200
•
Contact your local EDA sales office to purchase these EDA
tools.
Support and Updates Include:
•
•
•
•
•
•
•
•
2-10
ModelSim, V-System HDL simulation libraries and
interface
Answers Database - http://www.xilinx.com or Answers
electronic book included.
Hotline Telephone Support
Apps FAX and E-Mail
Online Documentation
World Wide Web Access
Technical Newletter
Extensive Application Notes
Software Updates (for in-maintenance customers)
A period of maintenance is included with new design
system licenses, after which annual maintenance
contracts may be purchased. Contact your Xilinx
sales representative for more information
November 25,1997 (Version 2.0)
~XILINX
Required Hardware Environment (PC)
•
•
•
•
•
•
•
•
•
•
Fully IBM compatible PC486/Pentium
- NEC98 supported
Windows 95, Windows NT 4.0
- Chinese, Korean and Japanese versions
Minimum 300 Mbytes hard-disk space
CD-ROM drive
VGA display
Serial port mouse
One parallel and two serial ports
Small Devices: (8K or <) XC9536 - XC95108;
XC4003E - XC4008E; XC4005XL - XC4008XL
- 32 MB RAM (Use additional RAM to increase
performance)
- 32 -64 MB Virtual Memory
Medium Devices: (10K- 28K) XC95144 - XC95216;
XC401 OE - XC4025E; XC4028EX - XC4036EX;
XC401 OXL - XC4028XL
- 64 MB RAM (Use additional RAM to increase
performance)
- 64-128 MB Virtual Memory
Large Devices: (36K or » XC4036XL - XC4062XL
- 1.28K RAM (Use additional RAM to increase
performance)
128 - 256 MB Virtual Memory
November 25, 1997 (Version 2.0)
Required Hardware Environment
(Workstation)
•
•
•
•
•
•
Ultra Sparc (or equivalent)
- Sun
4.1.3 and 4.1.4
- Solaris 2.5
HP715 (or equivalent)
- HP-UX 10.2
RS6000
- AIX 4.1.5 (no GUls)
Small Devices: (28K or <) XC4000E;
XC4028EX - XC4036EX; XC4005XL - XC4028XL
- 64 MB RAM (Use additional RAM to increase
performance)
- 64MB min Swap Space
Large Devices (36K or » XC4036XL - XC4062XL
- 128 MB RAM (Use additional RAM to increase
performance)
- 128 MB min Swap Space
Color Monitor
as
I
2-11
Development Systems: Product Descriptions
Alliance Series Options (PC)
Overview
Support and Updates Include:
VIEWlogic Workview Office schematic capture and gate
simulator development system with libraries and interfaces
for Xilinx FPGAs and CPLDs.
•
Workview Office Standard Features:
•
•
•
•
•
Workview Office schematic editor
Workview Office gate simulator
Libraries and interfaces
Hotline support
Software maintenance for 90-days
Libraries Support:
•
•
CPLDs:
- XC9500
FPGAs:
-
XC4000E/X
Spartan
XC3xOONL
XC5200
2-12
•
•
•
•
•
•
Answers Database - http://www.xilinx.com or Answers
electronic book included.
Hotline Telephone Support
Apps FAX and E-Mail
Software Updates (for in-maintenance customers)
Online Documentation
World Wide Web Access
Technical Newletter
Extensive Application Notes
Required Hardware Environment:
•
•
•
•
•
•
•
•
Fully IBM compatible PC486/Pentium
Windows 95, Windows NT 4.0
- Chinese, Korean and Japanese versions
Minimum 500 Mbytes hard-disk space
CD-ROM drive
VGA display
Serial port mouse
One parallel and two serial ports
64 Mbytes RAM recommended (increase to improve
performance)
November 25,1997 (Version 2.0)
CORE Solutions Overview
September 5, 1997 (Version 1.0)
Product Overview
Background
view) which lists all of the functions available today. This
table will be your best guide to locating a specific product. If
you don't see what you need, check the AllianceCORE
Partner Profiles, Areas of Expertise section, for each of our
AliianceCORE partners. Our partners will be more than
willing to discuss the possibility of producing a core specifically for your needs.
The ASIC core industry' has been developing for over a
decade. Today there exists a wealth of intellectual property
(IP) that is readily available from numerous sources. During
this time, however, programmable logic· did not have the
density or the performance needed to accommodate large
lP cores.
Today, things have changed considerably. Xilinx is shipping
FPGAs like the XL famity that have usable densities up to
125,000 gates. Now, not only is the use of pre-defined logic
functions in programmable logic a possibility, it is becoming
a requirement to meet ever-shrinking product development
cycles.
Data Book Contents
The contents of the data book are as follows:
•
•
As a result, many ASIC core vendors and system designers
are beginning to look at using cores for their programmable
logic designs. It is for this reason that Xilinx created the
CORE Solutions portfolio of products.
.
CORE Solutions Products
•
CORE Solutions products support four application areas.
The application areas are as follows:
•
o
•
•
Standard Bus Interfaces - such as PCI, PCMCIA,
USB and Plug-and-Play ISA.
DSP Functions - These range from small building
blocks such adders, registers and multipliers, to larger
system-level functions such as FIR filters and ReedSolomon coders.
.
Telecom and Networking - building blocks for popular
communications standards.
Base-Level Functions - a broad category of functions
used across many application segments. These include
the every small parameterizable LogiBLOX macros up
through larger functions such as UARTs and DMA
controllers.
CORE Solutions Data Book
The goal of the CORE Solutions portfolio of products is to
provide cores with the shortest .time-to-market and best
possible device utilization the programmable logic industry
has to offer. Xifinx has published a brand new data book
foc'used entirely on programmable logic cores and related
products. Now there is one definitive sourcebook with
detailed descriptions of all Xilinx CORE Solutions.
When you receive your copy of. the. CORE Solutions Data
Book;becomEHamtiiar with the Product Listing by Application Segmef}i ilwle, (reproduced at the ena of this over-
September 5,1997 (Version 1.0)
•
•
•
Introduction
- Program Overview
- Product Listing by Application Segment
LogiCORE Products, sold and supported by Xilinx
- Product Overview
- PCI
- DSP
- CORE Generator products
AliianceCORE Products, sold and supported by Xilinx'
Partners
- Program Overview
- Products
- AliianceCORE Partner Profiles
LogiBLOX, GUI-based small function generator
Reference Designs
Sales offices, Representatives and Distributors
Ordering Information
To order a copy, request the CORE Solutions Data Book
from the Xilinx Literature Department. In the US call 1-800231-3386. For international locations call 1-408-879-5617
or you can send an E-mail request to:
literature@xjlinx.com.
An electronic version of the CORE Solutions Data Book
(1.2M Adobe Acrobat .pdf format) can also be downloaded
from:
www.xilinx.com/productsllogicore/core_sol.pdf
LogiCORE Products
LogiCORE products are sold, licensed. and supported by
Xilinx. They are developed Internally by Xilinx or jointly with
a partner.
. ..
The cores that Xilinxprovides as LogiCORE products typicallyfaU into one Qf two categories. The first are I;ligh~perfor
mance. interface cores that .. require a thorough
understanding and control of the FPGA technology and
2-13
I
CORE Solutions Overview
implementation software in order to achieve the desired
performance and complexity. An example of a core in this
category is the LogiCORE PCI interface.
The second category are cores that benefit from a very
specialized implementation in the FPGA. An example is the
LogiCORE DSP modules that are implemented using a
unique algorithm, Distributed Arithmetic. This algorithm fits
the lookup-table-based architecture of the FPGA. The
result is outstanding performance and device utilization,
often more than 10 times better than generic HDL descriptions.
Xilinx CORE Generator
In addition to actual cores, Xilinx is committed to develop
enabling design tools and methodologies to facilitate usage
of cores with FPGAs. The first products available in this category are the web-based CORE Generator for PCI and the
CORE Generator for DSP (available on CD). This innovative methodology for acquiring and using cores combines
the benefits of
•
a firm core with predictable performance, and
the flexibility of system level design, facilitated by
behavioral languages such as VHDL and Verilog.
In addition, because Xilinx is using the web as a distribution
mechanism, you always have access to the latest versions
and enhancements of the cores at:
www.xilinx.com/products/logicore/logicore.htm
The LogiCORE products are customized to filyour specific
application using an intuitive graphical user interface.
Based on your inputs, the tool then generates a proven
core with highly predictable timing that can be integrated
using any VHDL-, Verilog- or schematic-based design flow.
As a result, you can integrate several individually proven
cores with given performance into one system on a single
FPGA. Because each core is already verified, the time-tomarket benefits are maintained for high-complexity FPGAs.
Xilinx PCI Solutions
Xilinx' PCI solution includes devices, tools and cores
needed to build a cost-effective single-chip PCI system in
record time.
•
•
•
•
•
LogiCORE PCI - the only proven PCI core with
predictable timing
XC4000EIXL - the industry's fastest FPGAs that allow
you to integrate the PCI interfayeplus 5 to 60 thousand
gates of user designed logic
HardWire- an~automatic migration path to a low-cost
chip for volume production .
CORE Generator - for easy configuration and
integration of the LogiCORE PCI module
3 rd party Design Centers- with PCI expertise available
for special applications and customization of the core
2-14
PCI is an extremely high-performance and complex specification that is challenging to meet ill· any technology. To
meet the stringent PCI specification the core is carefully
hand-tuned for the targeted architecture. Placement and
routing for the critical parts of the core is locked down to
ensure that timing can be met every time the core is used.
To achieve our goals, the LogiCORE development team is
working closely with both the IC and Software teams. As an
example of this teamwork, new methodologies for characterizing and modeling our FPGAs have been developed.
The result is access to state of the.· art technology and
expertise, that allows you to complete your PCI application
in record. time.
Xilinx has sold over 250 licenses of the.· LogiCORE PCI
interface and has built up solid knowledge about PCI. We
are committed, and will continuously develop oui" PCI products to remain state of the art.
Xilinx DSP Solutions
Using an FPGA to implement high performance DSP functions often allows a radical performance advantage over
fixed processors while maintaining maximum flexibility and
the shortest time-to-market. Until now, tools to automate
the design process have been lacking and most designs
have been completed manually by experienced FPGA
designers.
With the introduction of Xilinx' CORE Generator for DSp,
complex parameterized DSP building blocks can be implemented automatically with performance and density equal
to or better than a hand-tuned implementation. LogiCORE
DSP modules can be used with VHDL-, Verilog- or schematic based design methodologies.
Higher level DSP cores are available from our AIIianceCORE partners.
Acquiring LogiCORE Products
LogiCORE products are available from your local Xilinx
sales representative similar to other Xilinx software. products. Xilinx and your local sales. representative will also be
your primary source for support of. the core, the devices
and the design tools.
You can also send email questions to:
logicore@xilinx.com.
AliianceCORE Overview
The AllianceCOREprogram is a cooperative effort between
Xilinxand independent third~party COre developers..It is
designed to produce·a broad selection of industry-standard
solutions dedicated for use in Xilinx programmable logic ..
Xilinx takes an actiye role with its partners in the process of
productizing AllianceCOREs.This is unique to the AIIianceCORE program. Because the process is so involved,
September 5, 1997 (Version 1.0)
~XILINX
we work closely with our partners to select the right cores
first. This naturally limits the number of partners we can
work with at anyone time and subsequently the number of
available cores. At the same time it raises the quality and
usability of the cores that are offered.
AliianceCORE Criteria
A core must meet a minimum set of criteria before it can
receive the AliianceCORE label.
Core Selection
The AliianceCORE program looks at cores from a practical
point of view. A programmable logic version of a core must
have value over an ASIC or standard product version of the
same function. It must be cost effective and make sense for
use in a programmable device in a production system. If a
candidate core doeS not pass these simple tests, then it
does not make sense to invest the effort to convert it to an
AliianceCORE module.
Core Qualification
Generic, synthesizable cores offer maximum flexibility for
users with unique requirements. This is typically the format
for cores provided to the ASIC market. With programmable
logic, however, this flexibility can come at the expense of
efficiency and performance. It can take a considerable
amount of effort to get a specific core to synthesize in a way
that meets density and timing requirements. Time spent
trying to accomplish this can quickly reduce the time-tomarket advantage of using programmable logic and cores
in the first place.
Xilinx is not interested in promoting generic, synthesizable
functions as AliianceCOREs. Instead, AliianceCOREs are
generally provided as parameterizable black-boxes that
allow customization in critical areas. This guarantees that
the implementation is optimized for density while still meeting performance, preserving the time-to-market value of
programmable logic. Flexibility is provided by allowing you
to quickly implement your unique logic on the same device.
Source code versions of the cores are also available from
the partners at additional cost for those who need ultimate
flexibility.
Announced AliianceCOREs have been implemented and
verified in a Xilinx device. They are available immediately
for purchase in a Xilinx-specific format. Timing-critical
cores designed to adhere to an industry standard also
come with appropriate constraints files in order to guaran-
September 5, 1997 (Version 1.0)
tee functionality and compliance. AliianceCOREs originated from either schematic or HDL entry tools.
Core Integration
AliianceCOREs are not just cores, they are complete solutions for system designs. While cores by themselves have
value, in many cases it is often not enough to just supply a
generic core. You may need additional. tools such as system software and prototyping equipment to help you rapidly
integrate the core into your design, perform system debug
in a real-world environment, and then quickly convert the
prototype to a production unit. This is particularly true of
complex functions.
Many AliianceCORE functions are supported by Xilinxbased demonstration or prototyping boards. Some also
have system simulation models or debug software. All of
this allows you to evaluate and work with the function
befOre you have to layout your board. These tools are provided by the AliianceCORE partner, usually at additional·
cost. Descriptions of the support tools, available for each
core are included in the CORE Solutions Data Book.
Complete solutions like these help preserve the value of
using programmable logic while minimizing the support
burden for the core provider.
Acquiring AliianceCORE Products
AliianceCORE products are sold and sl=lrviced directly by
the AliianceCORE partners since they are the experts for
their particular products. They are responsible for pricing,
licensing terms, delivery and technical support. Contact
information for' each partner is included in the AIIianceCORE Partner Profiles section of the CORE Solutions
Data Book.
If you want additional information about the AliianceCORE
program or are interested in becoming a partner, contact
Xilinx directly.
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124'
Attn: Mark Bowlby, AliianceCQRE Product Manager
Phone: +1 408-879-5381
.
Fax:
+1 408-879~4780
E-mail: alliancecore@xilinx.com
www.xilinx.com/productsllogicore
URL:
·Ialliance/tblpart.htm
2-15
I
CORE Solutions Overview
Table 1: Product Listing by Application Segment
Check www.xilinx.com/products/logicoreltbls- cores.htm for the latest listing of available Cores
Function
Standard Bus Interfaces
IIC Two-Wire Serial Interface
ISA Plug and Play Interface
ISA Interface for JPEG Motion Codec
PCI Master/Slave Interfaces 1.2.0
PCI Master/Slave Interfaces 2.0.0
PCMCIA Fax/Modem
PCMCIA Library
USB - Low-Speed Function Controller
USB - Full-Speed Function Controller
USB - 3-Port Hub Controller
DSP Functions
1's Complement
Accumulator, Scaled by 1/2
Adder, Registered
Adder, Registered Loadable
Adder, Registered Scaled
Adder, Registered Serial
Adders, Subtractors, Accumulators
Comb Filter
Correlator, 1-D RAM Based
Correlator, 1-D ROM Based
Delay Element
FIR Filter, 16-Tap, 8-Bit
FIR Filter - Serial Distributed Arithmetic
FIR Filter - Dual Channel Serial Distributor Arithmetic
Integrator
Memory· 16·Word Deep Register Look-up Table
Memory • 32~Word Deep Register Look·up Table
Memory· 16·Word Deep Registered RAM
Memory· 32-Word Deep Registered RAM
Memory - Registered Synchronous RAM
Memory - Registered ROM
Multiplier, Constant Coefficient
Multiplier, Constant Coefficient (pipelined)
Multipliers, Parallel - Area Optimized
Multipliers, Parallel - Performance Optimized
Parallel to Serial Converter
Reed-Solomon Decoder
Reed-Solomon Encoder
SDA FIR Control Logic
Sine/Cosine
Square Root
Subtracter, Registered
Subtracter, Registered Loadable
2-16
.cORE Solution
AliianceCORE
Reference Design
Reference Design
LogiCORE
LogiCORE
AllianceCORE
AllianceCORE
AllianceCORE
AliianceCORE
AliianceCORE
LogiCORE
LogiCORE
LogiCORE
LogiCORE
LogiCORE
LogiCORE
Reference Design
LogiCORE
LogiCORE
LogiCORE
LogiCORE
Reference Design
LogiCORE
LogiCORE
LogiCORE
LogiCORE
LogiCORE
LogiCORE·
LogiCORE
LogiCORE
LogiCORE
LogiCORE
LogiCORE
LogiCORE
LogiCORE
LogiCORE
AliianceCORE
AliianceCORE
LogiCORE
LogiCORE
LogiCORE
LogiCORE
LogiCORE
September 5, 1997 (Version 1.0)
~XILINX
Table 1: Product Listing by Application Segment (Continued)
Check www.xilinx.com/productsllogicoreltbls_cores.htm for the latest listing of available Cores
Function
Time Skew Buffer - Non-Symmetric 16-Deep
Time Skew Buffer - Non-Symmetric 32-Deep
Time Skew Buffer - Symmetric 16-Deep
Transform, OFT
Transform, FFT
Base-Level Functions
16450 UART
16550A UART with RAM
8250 Asynchronous Communications
8254 Programmable Timer
M8255 Programmable Peripheral Interface
XF8255 Programmable Peripheral Interface
Accumulator
Adder/Subtracter
Clock Divider
Comparator
Constant
Constant
Counter
Counter, Loadable Binary
Counter, Ultra-Fast Synchronous
Counter, Accelerating Loadable
Data Register
Decoder
FIFOs in XC4000 RAM
FIFO, High-Performance RAM-Based
FIFO, Register-Based
Frequency/Phase Comparator for PLL
Gates, Simple
Harmonic Frequency Synthesizer and FSK Modulator
Input/Output
Microcontroller, Dynamic
Memory (ROM, RAM,Synch-RAM, Dual Port RAM)
Multiplexer
Multiplexers, Barrel Shifters
Multiplexer, Two Input
Multiplexer, Three Input
Multiplexer, Four Input
Pad
Pulse-Width Modulation
Register
Serial Code Conversion between BCD and Binary
Shift Register
Tristate
September 5, 1997 (Version 1.0)
CORE Solution
LogiCORE
LogiCORE
LogiCORE
LogiCORE
LogiCORE
AliianceCORE
AliianceCORE
AliianceCORE
AliianceCORE
AliianceCORE
AliianceCORE
LogiBLOX
LogiBLOX
LogiBLOX
LogiBLOX
LogiCORE
LogiBLOX
LogiBLOX
Reference Design
Reference Design
Reference Design
LogiBLOX
LogiBLOX
Reference Design
Reference Design
Reference Design
Reference Design
LogiBLOX
Reference Design
LogiBLOX
Reference Design
I
LogiBLOX
LogiBLOX
Reference Design
LogiCORE
LogiCORE
LogiCORE
LogiBLOX
Reference Design
LogiCORE
Reference Design
LogiBLOX
LogiBLOX
2-17
CORE Solutions Overview
2-18
September 5, 1997 (Version 1.0)
CPLD Products
1
Introduction
2
Development System Products and CORE Solutions Products
3
CPLD Products
4
FPGA Products
5
SPROM Products
6
3V Products
7
HardWire FpgASIC Products
8
High-Reliability and QML Military Products
9
Programming Support
10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support and Services
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors
CPLD Products Table of Contents
CPLD Products
XC9500 Series Table of Contents ..........................................•. 3-1
XC9500 In-System Programmable CPLD Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
XC9536 In-System Programmable CPLD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . .. 3-21
XC9572 In-System Programmable CPLD. • . .. . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . 3-29
XC95108 In-System Programmable CPLD. . . . . . . . . . . . . . . . . . . . . . . . . . • . . • . . . . . . . 3-37
XC95144 In-System Programmable CPLD. . • . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45
XC95216 In-System Programmable CPLD. . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . 3-55
XC95288 In-System Programmable CPLD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65
XC9500 Series Table of Contents
XC9500 In-System Programmable CPLD Family
Features ........................................................................ .
Family Overview .................................................................. .
Architecture Description ............................................................ .
Function Block.................................................................... .
Macrocell ........................................................................ .
Product Term Allocator ............................................................. .
FastCONNECT Switch Matrix ........................................................ .
I/O Block ........................................................................ .
Pin-Locking Capability .............................................................. .
In-System Programming ............................................................ .
External Programming ....................................................... .
Endurance ....................................................................... .
IEEE 1149.1 Boundary-Scan (JTAG) .................................................. .
Design Security ................................................................... .
Low Power Mode ................................................................. .
Timing Model. .................................................................... .
Power-Up Characteristics ........................................................... .
Development System Support ....................................................... .
FastFLASH Technology ............................................................ .
3-5
3-5
3-5
3-7
3-8
3-10
3-13
3-14
3-15
3-16
3-16
3-16
3-16
3-16
3-17
3-17
3-18
3-19
3-19
I
XC9536 In-System Programmable CPLD
Features ........................................................................ .
Description ...................................................................... .
Power Management ...........................................................•....
Absolute Maximum Ratings ......................................................... .
Recommended Operating Conditions 1 • • • • • • • • • • • , • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
Endurance Characteristics .......................................................... .
DC Characteristics Over Recommended Operating Conditions .............................. .
AC Characteristics ................................................................ .
Internal Timing Parameters .......................................................... .
XC9536 I/O Pins ............................................................ .
XC9536 Global, JTAG and Power Pins .......................................... .
Ordering Information ............................................................... .
Component Availability ............................................................. .
3-21
3-21
3-21
3-23
3-23
3-23
3-24
3-24
3-25
3-26
3-26
3-27
3-27
XC9572 In-System Programmable CPLD
Features ........................................................................ .
Description ...................................................................... .
Power Management ............................................................... .
Absolute Maximum Ratings ......................................................... .
Recommended Operation Conditions1 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • . • • • • • • • • •
Endurance Characteristics .......................................................... .
DC Characteristics Over Recommended Operating Conditions .............................. .
AC Characteristics ................................................................ .
Internal Timing Parameters .......................................................... .
XC9572 I/O Pins ............................................................ .
XC9572 Global, JTAG and Power Pins .......................................... .
3-29
3-29
3-29
3-31
3-31
3-31
3-32
3-32
3-33
3-34
3-35
3-1
XC9500 Series Table of Contents
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-36
Component Availability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-36
XC95108 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Recommended Operation Conditions' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Endurance Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AC Characteristics ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Internal Timing Parameters ...........................................................
XC95108 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC95108 I/O Pins (continued) ..................................................
XC95108 Global, JTAG and Power Pins ... " ..... " ..............................
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Component Availability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-37
3-37
3-37
3-39
3-39
3-39
3-40
3-40
3-41
3-42
3-43
3-43
3-44
3-44
XC95144 In-System Programmable CPLD
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Absolute Maximum Ratings .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Recommended Operation Conditions' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Endurance Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AC Characteristics .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Internal Timing Parameters ..................................................... , .....
XC95144 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC95144 I/O Pins (continued) ..................................................
XC95144 Global, JTAG and Power Pins ..........................................
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Component Availability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-45
3-45
3-45
3-47
3-47
3-47
3-48
3-48
3-49
3-50
3-51
3-52
3-53
3-53
XC95216 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . ..
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Absolute Maximum Ratings .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Recommended Operating Conditions' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Endurance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . .. . . . . . . . .. . . . . . . . . . ..
Internal Timing Parameters ...........................................................
XC95216 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC95216 110 Pins (continued) ..................................................
XC95216 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC95216 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Component Availability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-55
3-55
3-55
3-57
3-57
3-57
3-58
3-58
3-59
3-60
3-61
3-62
3-63
3-64
3-64
XC95288 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. 3-65
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . .. . . . . . . . .. 3-65
3-2
~XILINX
Power Management ............................................................... .
Absolute Maximum Ratings ......................................................... .
Recommended Operation Conditions' ................................................. .
Endurance Characteristics .......................................................... .
DC Characteristics Over Recommended Operating Conditions .............................. .
AC Characteristics ................................................................ .
Internal Timing Parameters .......................................................... .
XC95288 1/0 Pins ........................................................... .
XC95288 1/0 Pins (continued) ................................................. .
XC95288 110 Pins (continued) ................................................. .
XC95288 110 Pins (continued) " ............................................... .
XC95288 Global, JTAG and Power Pins ......................................... .
Ordering Information ............................................................... .
Component Availability ............................................................. .
3-65
3-67
3-67
3-67
3-68
3-68
3-69
3-70
3-71
3-72
3-73
3-74
3-75
3-75
I
3-3
XC9500 Series Table of Contents
3-4
XC9500 In-System
Programmable CPLD Family
November 10, 1997 (Version 2.0)
Product Information
Features
Family Overview
•
The XC9500 CPLD family provides advanced in-system
programming and test capabilities for high performance,
general purpose logic integration. All devices are in-system
programmable for a minimum of 10,000 program/erase
cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan support is also included on all family members.
•
•
•
•
•
•
•
•
•
•
•
High-performance
- 5 ns pin-to-pin logic delays on all pins
- feNT to 125 MHz
Large density range
- 36 to 288 macrocells with 800 to 6,400 usable gates
5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3 V or 5 V I/O capability
PCI compliant (-5, -7, -10 speed grades)
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of multiple XC9500
devices
As shown in Table 1, logic density of the XC9500 devices
ranges from 800 to over 6,400 usable gates with 36 to 288
registers, respectively. Multiple package options and associated I/O capacity are shown in Table 2. The XC9500 family is fully pin-compatible allowing easy design migration
across multiple density options in a given package footprint.
The XC9500 architectural features address the requirements of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. An expanded JTAG
instruction set allows version control of programming patterns and in-system debugging. In-system programming
throughout the full device operating range and a minimum
of 10,000 program/erase cycles provide worry-free reconfigurations and system field upgrades.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. I/Os may be configured for 3.3 V or 5 V operation. All
outputs provide 24 mA drive.
Architecture Description
Each XC9500 device is a sUbsystem consisting of multiple
Function Blocks (FBs) and I/O Blocks (lOBs) fully interconnected by the FastCONNECT switch matrix. The lOB provides buffering for device inputs and outputs. EaCh FB
provides programmable logic capability with 36 inputs and
18 outputs. The FastCONNECT switch matrix connects all
FB outputs and input signals to the FB inputs. For each FB,
12 to 18 outputs (depending on package pin-count) and
associated output enable signals drive directly to the lOBs.
See Figure 1.
November 10,1997 (Version 2.0)
3-5
I
XC9500 In-System Programmable CPLD Family
3
I
JTAG Port {
JTAG
Controller
~
I ..
I
.1
In-System Programming Controller
I
J-.
1/0
;
36
Function
Block 1
18
I
1/0
I[
M acrocells 1
1 to 18
t tt
1/0
36
x
-;::
1/0 ~
•
•
•
•
0;
::2:
I
..c
.8
-§:
1/0
Function
Block 2
18
II
Macrocells 1
1 to 18
(/)
Blocks
t tt
I-
1/0
0
1/0
z
z
UJ
0
0
36
I
Qi
1/0
Function
Block 3
18
==============~>
Setup Time = tsu
Propagation Delay", tpD
Clock to Out Time
=
teo
(b)
(a)
tpco
================>
Setup Time = tpsu
Clock to Out Time"" Ipeo
Internal System Cycle Time = lSYSTEM
(d)
(e)
D
Internal Cycle Time", teNT
'e)
Figure 15: Basic Timing Model
tOUT
Figure 16: Detailed Timing Model
Power-Up Characteristics
The XC9500 devices are well behaved under all operating
conditions. During power-up each XC9500 device employs
internal circuitry which keeps the device in the quiescent
state until the VCCINT supply voltage is at a safe level
(approximately 3.8 V). During this time, all device pins and
JTAG pins are disabled and all device outputs are disabled
with the lOB pull-up resistors (- 10K ohms) enabled, as
shown in Table 4. When the supply voltage reaches a safe
3-18
level, all user registers become initialized (typically within
100 I1s for 9536 - 95144, 200 I1s for 95216 and 300 I1s for
95288), and the device is immediately available for operation, as shown in Figure 17.
If the device is in the erased state (before any user pattern
is programmed), the device outputs remain disabled with
the lOB pull-up resistors enabled. The JTAG pins are
enabled to allow the device to be programmed at any time.
November 10, 1997 (Version 2.0)
~XILINX
FastFLASH Technology
If the device is programmed, the device inputs and outputs
take on their configured states for normal operation. The
JTAG pins are enabled to allow device erasure or boundary-scan tests at any time.
An advanced CMOS Flash process is used to fabricate all
XC9500 devices. Specifically developed for Xilinx in-system programmable CPLDs, the FastFLASH process provides high
performance logic capability, fast programming times, and
endurance of 10,000 program/erase cycles.
Development System Support
The XC9500 CPLD family is fully supported by the development systems available from Xilinx and the Xilinx Alliance
Program vendors.
VCCINT
The designer can create the design using ABEL, schematics, equations, VHDL, or Verilog in a variety of software
front-end tools. The development system can be used to
implement the design and generate a JEDEC bitmap which
can be used to program the XC9500 device. Each development system includes JTAG download software that can be
used to program the devices via the standard JTAG interface and a download cable.
3.8V
(Typ)
ov
No
Quiescent
Power
State
User Operation
QU~~!~eent
' - - Initialization of User Registers
No
Power
X5904
Figure 17: Device Behavior During Power-up
Table 3: Timing Model Parameters
Description
Parameter
Propagation Delay
Global Clock Setup Time
Global Clock-to-output
Product Term Clock Setup
Time
Product Term Clock-to-output
Internal System Cycle Period
tpo
Product Term
Allocator1
Macrocell
Low-Power Setting
Output Slew-Limited
Setting
+ tpTA * S
+ tpTA * S
+ tLP
+ tLP
+ tSLEW
-
-
+ tSLEW
+ tpTA * S
+ tLP
-
-
-
+ tSLEW
+ tpTA * S
+ tLP
-
tsu
tco
tpsu
tpco
tSYSTEM
-
Note: 1. S = the logic span of the function, as defined in the text.
Table 4: XC9500 Device Characteristics
Device
Circuitry
Quiescent
State
Erased Device
Operation
Valid User
Operation
lOB Pull-up Resistors
Device Outputs
Device Inputs and Clocks
Function Block
JTAG Controller
Enabled
Disabled
Disabled
Disabled
Disabled
Enabled
Disabled
Disabled
Disabled
Enabled
Disabled
As Configured
As Configured
As Configured
Enabled
November 10, 1997 (Version 2.0)
3-19
I
XC9500 In-System Programmable CPLD Family
3-20
November 10, 1997 (Version 2.0)
XC9536 In-System
Programmable CPLD
November 10, 1997 (Version 2.0)
Product Specification
Features
Power Management
•
•
•
•
•
Power dissipation can be reduced in the XC9536 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power
dissipation.
•
•
•
•
•
•
•
•
•
•
•
5 ns pin-to-pin logic delays on all pins
fCNT to 100 MHz
36 macro cells with 800 usable gates
Up to 34 user 1/0 pins
5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Programlerase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3 V or 5 V 1/0 capability
PCI compliant (-5, -6, -7, -10 speed grades)
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 44-pin PLCC and 44-pin VQFP packages
Operating current for each design can be approximated for
specific operating conditions using the following equation:
=
ICC (mA)
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC9536 device.
(83)
1
(50)
(50)
<.>
.2
1ii
.a.
"
,:':'
(30)
Description
The XC9536 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of two
36V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See Figure 2 for the architecture overview.
November 10, 1997 (Version 2.0)
o
50
Clock Frequency (MHz)
100
X5920
Figure 1: Typical IcC vs. Frequency For XC9536
3-21
I
XC9536 In-System Programmable CPLD
JTAG Port {
~~~~~1-~~~~~I~.--~~.~LI~~_I_n_-S_y_s_te_m~pr_o_g_ra_m_m_i_n_g_C_o_nt_ro_I~le_r__~
36
18
I/O
Function
Block 1
I/O
110
><
.;::
I/O
•
•
•
•
1il
::2:
18
.<::
I/O
Blocks
.~
~
I-
(.)
I/O
UJ
Z
Z
I/O
~
I/O
LL
I/O
3
I/O/GCK
I/O/GSR
I/O/GTS
2
X5919
Figure 2: XC9536 Architecture
Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly
3-22
November 10, 1997 (Version 2.0)
~XILINX
Absolute Maximum Ratings
Symbol
Warning:
Parameter
Supply voltage relative to GND
DC input voltage relative to GND
Voltage applied to 3-state output with respect to GND
Storage temperature
Max soldering temperature (10 s @ 1/16 in = 1.5 mm)
VCC
VIN
VTS
TSTG
TSOL
Value
Units
-0.5 to 7.0
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
-65 to + 150
+260
V
V
V
°C
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.
Recommended Operating Conditions 1
Symbol
Parameter
VCCINT
Supply voltage for internal logic and input buffer
VCCIO
Supply voltage for output drivers for 5 V operation
Supply voltage for output drivers for 3.3 V operation
Low-level input voltage
High-level input voltage
Output voltage
VIL
VIH
Vo
Min
Max
Units
4.75
(4.5)
4.75 (4.5)
3.0
0
2.0
0
5.25
(5.5)
5.25 (5.5)
3.6
0.80
V
VCCINT +0.5
VCCIO
V
V
V
V
V
Note 1. Numbers in parenthesis are for industrial-temperature range versions.
Endurance Characteristics
Symbol
tDR
NpE
Parameter
Data Retention
Program/Erase Cycles
November 10, 1997 (Version 2.0)
Min
Max
Units
20
-
Years
10,000
Cycles
3-23
I
XC9536 In-System Programmable CPLD
DC Characteristics Over Recommended Operating Conditions
Symbol
Parameter
Min
Test Conditions
Output high voltage for 5 V operation
10H = -4.0 mA
Vee = Min
Output high voltage for 3.3 V operation 10H = -3.2 mA
Vee = Min
Output low voltage for 5 V operation
10L = 24 mA
Vee = Min
Output low voltage for 3.3 V operation 10L= 10 mA
Vee = Min
Input leakage current
Vee = Max
VIN = GND or Vee
1/0 high-Z leakage current
Vee = Max
VIN = GND or Vee
1/0 capacitance
VIN = GND
f = 1.0 MHz
Operating Supply Current
VI = GND, No load
(low power mode, active)
f = 1.0 MHz
VOH
VOL
IlL
IIH
CIN
Icc
Max
Units
2.4
V
2.4
V
0.5
V
0.4
V
±10.0
IlA
±10.0
IlA
10.0
pF
mA
30 (Typ)
AC Characteristics
XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15
Parameter
Symbol
Min Max Min
1/0 to output valid
1/0 setup time before GCK
1/0 hold time after GCK
tpo
tsu
tH
teo
feNT1
fSYSTEM
tpsu
tpH
tpeo
tOE
too
tpOE
tpoo
tWLH
2
GCK to output valid
16-bit counter frequency
Multiple FB internal operating frequency
1/0 setup time before p-term clock input
1/0 hold time after p-term clock input
P-term clock to output valid
GTS to output valid
GTS to output disable
Product term OE to output enabled
Product term OE to output disabled
GCK pulse width (High or Low)
5.0
4.5
0.0
Max Min Max
6.0
4.5
0.0
4.5
100
100
0.5
4.0
8.5
6.0
6.0
10.5
10.5
4.0
7.5
4.5
Min
8.0
0.0
8.0
6.5
5.5
67
67
2.5
4.0
9.5
7.0
7.0
13.0
13.0
4.0
56
56
4.0
4.0
10.5
10.0
10.0
15.5
15.5
4.5
Units
Max
15.0
10.0
83
83
1.5
4.0
8.5
6.0
6.0
10.5
10.5
4.0
Max
6.5
0.0
5.5
0.0
100
100
0.5
4.0
Min
12.0
15.0
15.0
18.0
18.0
5.5
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Note: I. fCNT is the fastest 16-bit counter frequency available.
fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG .
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
3-24
November 10, 1997 (Version 2.0)
~XILINX
V TEST
Output Type
Device Output o-----.-----_-~
V CCIO
VTEST
R1
R2
CL
5.0V
5.0V
1600
1200
35 pF
3.3V
3.3V
2600
3600
35 pF
X5906
Figure 3: AC Load Circuit
I
Internal Timing Parameters
Symbol
Parameter
Buffer Delays
Input buffer delay
tiN
GCK buffer delay
tGCK
GSR buffer delay
tGSR
GTS buffer delay
tGTS
Output buffer delay
tOUT
Output buffer enable/disable delay
tEN
Product Term Control Delays
tpTCK Product term clock delay
Product term set/reset delay
tpTSR
Product term 3-state delay
tPTTS
Internal Register and Combinatorial delays
Combinatorial logic propagation delay
tpOl
Register setup time
tSUI
Register hold time
tHI
Register clock to output valid time
tCOI
Register
async. SIR to output delay
tAOI
Register async. SIR recovery before clock
tRAI
Internal logic delay
tLOGI
tLOGILP Internal low power logic delay
Feedback Delays
FastCONNECT matrix feedback delay
tF
Function Block local feeback delay
tLF
Time Adders
Incremental Product Term Allocator delay
tpTA3
tSLEW Slew-rate limited delay
XC9536·5 XC9536·6 XC9536·7 XC9536·10 XC9536-15
Min Max Min Max Min Max Min
Max
Min
Max
Units
1.5
2.0
4.0
6.0
2.0
0.0
1.5
2.0
4.0
6.0
2.0
0.0
2.5
2.5
4.5
7.0
2.5
0.0
3.5
3.0
6.0
10.0
3.0
0.0
4.5
3.0
7.5
15.0
4.5
0.0
ns
ns
ns
ns
ns
ns
4.5
1.0
9.0
4.5
1.0
9.0
4.0
2.0
10.5
3.5
2.5
12.0
2.5
3.0
13.5
ns
ns
ns
3.0
0.5
1.5
0.5
1.0
9.0
1.0
9.0
2.0
10.0
2.5
11.0
3.0
11.5
ns
ns
ns
ns
ns
ns
ns
ns
4.5
4.5
4.5
4.5
6.0
6.0
8.5
8.5
11.0
11.0
ns
ns
1.0
3.5
1.0
3.5
1.0
4.0
1.0
4.5
1.5
5.0
ns
ns
4.0
0.5
4.0
0.5
0.5
6.0
5.0
3.5
2.0
0.5
6.0
5.0
1.0
3.5
4.5
3.5
3.0
0.5
6.5
7.5
0.5
7.0
10.0
0.5
8.0
15.0
Note: 3. tpTA is multiplied by the span of the function as defined in the family data sheet.
November 10. 1997 (Version 2.0)
3-25
XC9536 In-System Programmable CPLD
XC9536 I/O Pins
Function
Block
Macrocell
PC44
VQ44
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
2
3
5
4
6
8
7
9
11
12
13
14
18
19
20
22
24
-
40
41
43
42
44
2
1
3
5
6
7
8
12
13
14
16
18
Note:
-
BScan
Notes
Order
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
Function
Block
Macrocell
PC44
VQ44
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
44
42
43
40
39
38
37
36
35
34
33
29
28
27
26
25
-
39
38
36
37
34
33
32
31
30
29
28
27
23
22
21
20
19
[1]
[1]
[1]
-
BScan
Notes
Order
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0
[1]
[1]
[1]
[1) Global control pin
XC9536 Global, JTAG and Power Pins
Pin Type
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GSR
TCK
TOI
TOO
TMS
VCCINT 5 V
VCCIO 3.3 V/5 V
GND
No Connects
3-26
PC44
VQ44
5
6
7
42
40
39
17
15
30
16
21,41
32
23,10,31
43
44
1
36
34
33
11
9
24
10
15,35
26
17,4,25
-
-
November 10, 1997 (Version 2.0)
~XILINX
Ordering Information
TTL
XC9536 -5 PC 44 C
Device Type
Speed
J T
~
Packaging Options
Speed Options
-15
-10
-7
-6
-5
Temperature Range
Number of Pins
Package Type
15ns
10ns
7.5ns
6ns
5ns
pin-to-pin
pin-to-pin
pin-to-pin
pin-to-pin
pin-to-pin
PC44 44-Pin Plastic Leaded Chip Carrier (PLCC)
VQ44 44-Pin Thin Quad Pack (VQFP)
delay
delay
delay
delay
delay
II
Temperature Options
C
I
Commercial
Industrial
e
O°C to 70 0
-40 o to 85°C
e
Component Availability
Pins
44
Plastic
PLCC
Plastic
VQFP
PC44
C,I
VQ44
-10
-7
C,I
C,I
e,1
C,I
-6
C
-5
C'
C
C
Type
Code
-15
XC9536
C = Commercial = 0° to +70°C,
I = Industrial
Note: 1.Contact factory for availability
November 10, 1997 (Version 2.0)
e,1
= -40° to 85°C
3-27
XC9536 In-System Programmable CPLD
3-28
November 10, 1997 (Version 2.0)
XC9572 In-System
Programmable CPLD
October 28, 1997 (Version 2.0)
Product Specification
Features
Operating current for each design can be approximated for
specific operating conditions using the following equation:
•
•
IcC (mA) =
•
•
•
•
•
•
•
•
•
•
•
•
•
7.5 ns pin-to-pin logic delays on all pins
fCNT to 125 MHz
72 macrocells with 1,600 usable gates
Up to 72 user I/O pins
5 V in-system programmable (ISP)
Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3 V or 5 V I/O capability
PCI compliant F, -10 speed grades)
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP
and 1OO-pin TQFP packages
Description
MCHP (1.7) + MC LP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
I
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
200.----------,----------,
o
50
100
Clock Frequency (MHz)
Figure 1: Typical Icc vs. Frequency for XC9572
The XC9572 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of four
36V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architecture overview.
Power Management
Power dissipation can be reduced in the XC9572 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power
dissipation.
October 28, 1997 (Version 2.0)
3-29
XC9572 In-System Programmable CPLD
JTAG Port {
36
18
1/0
Function
Block 1
1/0
1/0
.~
1/0
•
•
•
•
::iE
18
.r::
1/0
Blocks
·i
(f)
I()
LU
1/0
z
z
1/0
0
()
18
1ii
1/0
Ol
u..
1/0
I/O/GCK
3
18
I/O/GSR
I/O/GTS
2
X5921
Figure 2: XC9572 Architecture
Note: Function Block outputs (indicated by the bold line) drive the 1/0 Blocks directly
3-30
October 28, 1997 (Version 2.0)
~XILINX
Absolute Maximum Ratings
Symbol
Parameter
Supply voltage relative to GND
DC input voltage relative to GND
Voltage applied to 3-state output with respect to GND
Storage temperature
Max soldering temperature (10 s @ 1/16 in = 1.5 mm)
VCC
VIN
VTS
TSTG
TSOL
Value
Units
-0.5 to 7.0
V
V
V
DC
DC
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
-65 to + 150
+260
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.
Recommended Operation Conditions 1
Symbol
Parameter
VCCINT
Supply voltage for internal logic and input buffer
VCCIO
Supply voltage for output drivers for 5 V operation
Supply voltage for output drivers for 3.3 V operation
LOW-level input voltage
High-level input voltage
Output voltage
VIL
VIH
Vo
Min
Max
Units
4.75
(4.5)
4.75 (4.5)
3.0
0
2.0
0
5.25
(5.5)
5.25 (5.5)
3.6
0.80
V
VCCINT +0.5
VCCIO
Min
Max
I
V
V
V
V
V
Note: 1. Numbers in parenthesis are for industrial temperature range versions.
Endurance Characteristics
Symbol
tDR
NpE
Parameter
Data Retention
Program/Erase Cycles
October 28,1997 (Version 2.0)
Units
20
Years
10,000
Cycles
3-31
XC9572 In-System Programmable CPLD
DC Characteristics Over Recommended Operating Conditions
Symbol
VOH
Parameter
Test Conditions
Output high voltage for 5 V operation
Output low voltage for 5 V operation
Output low voltage for 3.3 V operation
IlL
Input leakage current
IIH
1/0 high-Z leakage current
CIN
1/0 capacitance
Icc
Operating Supply Current
(low power mode, active)
Max
2.4
IOH = -4.0 mA
Vee = Min
IOH = -3.2 mA
Vee = Min
IOL = 24 mA
Vee = Min
IOL = 10 mA
Vee = Min
Vee = Max
VIN = GND or Vee
Vee = Max
VIN = GND or Vee
VIN = GND
f = 1.0 MHz
VI = GND, No load
f = 1.0 MHz
Output high voltage for 3.3 V operation
VOL
Min
Units
V
V
2.4
0.5
V
0.4
V
±10.0
/!A
±10.0
/!A
10.0
pF
65 (Typ)
ma
AC Characteristics
Symbol
tpD
tsu
tH
teo
feNT1
fSYSTEM 2
tpsu
tpH
tpeo
tOE
too
tpOE
tpOD
tWLH
XC9572-7
XC9572-10
XC9572-15
Min
Min
Min
Parameter
1/0 to output valid
1/0 setup time before GCK
1/0 hold time after GCK
GCK to output valid
16-bit counter frequency
Multiple FB internal operating frequency
1/0 setup time before p-term clock input
1/0 hold time after p-term clock input
P-term clock to output valid
GTS to output valid
GTS to output disable
Product term OE to output enabled
Product term OE to output disabled
GCK pulse width (High or Low)
Units
Max
7.5
5.5
0.0
Max
10.0
6.5
5.5
111
67
2.5
4.0
9.5
7.0
7.0
13.0
13.0
4.0
15.0
8.0
0.0
6.5
0.0
125
83
1.5
4.0
Max
8.0
95
56
4.0
4.0
10.5
10.0
10.0
15.5
15.5
4.5
12.0
15.0
15.0
18.0
18.0
5.5
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Note: 1. fCNT is the fastst 16-bit counter frequency available. using the local feedback when applicable.
feNT is also the Export Control Maximum flip-flop toggle rate, froG'
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
3-32
October 28, 1997 (Version 2.0)
~XILINX
Output Type
Device Output
VCCIO
5.0V
3.3 V
o---~>---------.------{!
VTEST
5.0V
3.3V
R1
160n
260n
R2
120 n
360n
CL
35 pF
35 pF
X5906
II
Figure 3: AC Load Circuit
Internal Timing Parameters
Symbol
Parameter
Buffer Delays
Input buffer delay
tiN
GCK
buffer delay
tGCK
GSR buffer delay
tGSR
GTS buffer delay
tGTS
Output buffer delay
tOUT
Output buffer enable/disable delay
tEN
Product Term Control Delays
Product termciock delay
tpTCK
Product term set/reset delay
tpTSR
Product term 3-state delay
tpTTS
Internal Register and Combinatorial delays
Combinatorial logic propagation delay
tpDI
Register setup time
tSUI
Register hold time
tHI
Register clock to output valid time
tCOI
Registerasync. SIR to output delay
tAOI
Register async. SIR recovery before clock
tRAI
Internal
logic delay
tLOGI
Internal low power logic delay
tLOGILP
Feedback Delays
FastCONNECT matrix feedback.delay
tF
Function
Btock local feeback delay
tLF
Time Adders
Incremental Product Term Allocator delay
tPTA3
Slew-rate limited delay
tSLEW
XC9572·7
XC9572·10
XC9572·15
Min
Min
Min
Max
Max
Max
Units
2.5
2.5
4.5
7.0
2.5
0.0
3.5
3.0
6.0
10.0
3.0
0.0
4.5
3.0
7.5
15.0
4.5
0.0
ns
ns
ns
ns
ns
ns
4.0
2.0
10.5
3.5
2.5
3.0
13.5
ns
ns
ns
3.0
2.5
12.0
1.0
2.0
10.0
2.5
11.0
3.0
11.5
ns
ns
ns
ns
ns
ns
ns
ns
6.0
2.0
8.5
2.5
11.0
3.5
ns
ns
1.0
4.0
1.0
4.5
1.5
5.0
ns
ns
0.5
3.5
2.0
3.5
3.0
0.5
7.0
0.5
6.5
7.5
3.5
4.5
10.0
0.5
. 8.0
15.0
Note: 3. tpTA is multiplied by the span of the function as defined in the family data sheet.
October 28, 1997 (Version 2.0)
3-33
XC9572 In-System Programmable CPLD
XC9572 1/0 Pins
Function
Macrocell
Block
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PC
PC
44
84
1
2
3
4
1
6
7
2
3
11
5
9
13
10
18
20
12
14
23
15
24
63
69
67
68
70
71
76
4
5
6
-
7
8
9
35
36
37
38
39
72
40
42
43
44
74
75
77
79
80
81
83
82
84
-
-
-
PQ
100
TQ
100
BScan
Order
18
15
20
22
16
17
27
19
24
30
25
35
38
29
31
41
32
42
89
96
93
95
97
98
5
99
1
3
6
8
10
11
13
12
14
94
16
13
18
20
14
15
25
17
22
28
23
33
36
27
29
39
30
40
87
94
91
93
95
96
3
97
99
1
4
6
8
9
11
10
12
92
213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108
Notes
[1]
[1]
[1]
[2]
[1]
[1]
[3]
Function
Macrocell
Block
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PC
PC
44
84
-
25
17
31
32
19
34
35
21
26
40
33
41
43
36
37
45
39
11
12
13
14
18
19
20
22
24
25
26
27
28
29
33
34
-
46
44
51
52
47
54
55
48
50
57
53
58
61
56
65
62
66
-
PQ
100
TQ
100
BScan
Order
43
34
51
52
37
55
56
39
44
62
54
63
65
57
58
67
60
61
68
66
73
74
69
78
79
70
72
83
76
84
87
80
91
88
92
81
41
32
49
50
35
53
54
37
42
60
52
61
63
55
56
65
58
59
66
64
71
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0
72
67
76
77
68
70
81
74
82
85
78
89
86
90
79
Notes
Notes: [1] Global control pin
[2] Global control pin GTSl for PC84, PQ100, and TQ100
[3] Global control pin GTSl for PC44
3-34
October 28, 1997 (Version 2.0)
~XILINX
XC9572 Global, JTAG and Power Pins
Pin Type
PC44
PC84
PQ100
TQ100
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GSR
VCCINT5 V
V CC10 3.3 V/5 V
5
6
7
42
40
39
17
15
30
16
21,41
32
GNO
10,23,31
9
10
12
76
77
74
30
28
59
29
38,73,78
22,64
8,16,27,42,
49,60
No Connects
-
24
25
29
5
6
1
50
47
85
49
7,59,100
28,40,53,90
2,23,33,46,64,71,
77,86
4,9,21,26,36,45,48,
75,82
22
23
27
3
4
99
48
45
83
47
5,57,98
26,38,51,88
100,21,31,44,62,69,
75,84
2,7,19,24,34,43,46,
73,80
TCK
TOI
TOO
TMS
October 28, 1997 (Version 2.0)
-
3-35
II
XC9572 In-System Programmable CPLD
Ordering Information
J
XC9572 -7 PQ 100 C
Device TYpe]
Speed
I
T
Temperature Range
Number of Pins
'-------- Package Type
Packaging Options
Speed Options
PC44
PC84
PQ100
TQ100
-15 15 ns pin-to-pin delay
-10 10 ns pin-to-pin delay
-7 7.5 ns pin-to-pin delay
44-Pin Plastic Leaded Chip Carrier (PLCC)
84-Pin Plastic Leaded Chip Carrier (PLCC)
100-Pin Plastic Quad Flat Pack (PQFP)
1OO-Pin Very Thin Quad Flat Pack (TQFP)
Temperature Options
C
I
Commercial
Industrial
O°C to 70°C
-40°C to 85°C
Component Availability
Pins
Type
Code
XC9572
C = Commercial
3-36
-15
-10
-7
44
Plastic
PLCC
PC44
C,I
C,I
C
= 0° to +70°C
84
Plastic
PLCC
PC84
C,I
C,I
C
I = Industrial
100
Plastic
PQFP
PQ100
C,I
C,I
C
Plastic
TQFP
TQ100
C,I
C,I
C
= -40° to 85°C
October 28, 1997 (Version 2.0)
XC95108 In-System
Programmable CPLD
October 28, 1997 (Version 2.0)
Product Specification
Features
Power Management
• 7.5 ns pin-to-pin logic delays on all pins
• fCNT to 125 MHz
• 1DB macrocells with 2400 usable gates
• Up to 1DB user I/O pins
• 5 V in-system programmable (ISP)
Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
90 product terms drive any or all of 18 macrocells
within Function Block
Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
3.3 V or 5 V I/O capability
• PCI compliant (-7, -10 speed grades)
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in B4-pin PLCC, 1~O-pin PQFP, 1~O-pin TQFP
and 160-pin PQFP packages
Power dissipation can be reduced in the XC951 08 by configuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95108
device.
300,-------------.-------------~
(250)
~
l
200r---~~-=~--+-------------~
(180)
(170)
()
.2
!il
Description
The XC951 DB is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of six
36V18 Function Blocks, providing 2,400 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architecture overview.
"
'0.
~ 100~~----------+-------------~
o
50
Clock Frequency (MHz)
100
X5898
Figure 1: Typical Icc vs. Frequency for XC95108
October 28, 1997 (Version 2.0)
3-37
I
XC951 08 In-System Programmable CPLD
3
JTAG Port {
JTAG
Controller
1
t
I
I
I
I
In-System Programming Controller
t
t
36
Function
Block 1
18/
110
j
1/0 ~
II
t tt
1/0
36
x
1/0
•
•
•
•
~
:2
1/0
Blocks
1
1 to 18
t tt
t-
O
1/0
z
z
w
0
0
36
Function
Block 3
18 L
j
1ii
ctl
LL
II
1/0
I/O/GCK ~
36
1
1I0/GTS
Function
Block 4
18
1
2
II Macrocells
111t018
Function
Block 5
18 L
II Macrocells
111t018
Function
Block 6
18/
~
I
t tt
36
1
J
t tt
36
1
I
Macrocells
1 to 18
t tt
3
I/O/GSR
I
U Macrocells
CI)
1/0
1/0
Function
Block 2
18
.c
B
.§
I
Macrocells
1 to 18
II
Macrocells
1 to 18
tt
X5897
Figure 2: XC95108 Architecture
Note: Function Block outputs (indicated by the bold line) drive the 1/0 Blocks directly
3-38
October 28, 1997 (Version 2.0)
-~~~~.
-~~-
-------~~-
--~
~XILlNX
Absolute Maximum Ratings
Symbol
Parameter
Supply voltage relative to GND
DC input voltage relative to GND
Voltage applied to 3-state output with respect to GND
Storage temperature
Max soldering temperature (10 s @ 1/16 in = 1.5 mm)
VCC
VIN
VTS
TSTG
TSOL
Value
Units
-0.5 to 7.0
V
V
V
DC
DC
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
-65 to +150
+260
Warning: Stresses beyond those
listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.
Recommended Operation Conditions 1
Parameter
Symbol
VCCINT
Supply voltage for internal logic and input buffer
VCCIO
Supply voltage for output drivers for 5 V operation
Supply voltage for output drivers for 3.3 V operation
Low-level input voltage
High-level input voltage
Output voltage
VIL
VIH
Vo
Min
Max
Units
4.75
(4.5)
4.75 (4.5)
3.0
0
2.0
0
5.25
(5.5)
5.25 (5.5)
3.6
0.80
V
VCCINT +0.5
VCCIO
I
V
V
V
V
V
Note: 1. Numbers in parenthesis are for industrial-temperature range versions.
Endurance Characteristics
Symbol
Parameter
tDR
Data Retention
NpE
Program/Erase Cycles
October 28,1997 (Version 2.0)
Min
Max
Units
20
-
Years
10,000
-
Cycles
3-39
XC951 08 In-System Programmable CPLD
DC Characteristics Over Recommended Operating Conditions
Symbol
VOH
Parameter
Output high voltage for 5 V operation
Test Conditions
Output high voltage for 3.3 V operation
VOL
Output low voltage for 5 V operation
Output low voltage for 3.3 V operation
IlL
Input leakage current
IIH
I/O high-Z leakage current
CIN
I/O capacitance
Icc
Operating Supply Current
(low power mode, active)
Min
2.4
IOH = -4.0 mA
Vee = Min
IOH = -3.2 mA
Vee = Min
IOL =24 mA
Vee = Min
IOL = 10 mA
Vee = Min
Vee = Max
VIN = GND or Vec
Vec = Max
VIN = GND or Vee
VIN = GND
f = 1.0 MHz
VI = GND, No load
f = 1.0 MHz
Max
Units
V
V
2.4
0.5
V
0.4
V
±10.0
jlA
±10.0
!lA
10.0
pF
100 (Typ)
ma
AC Characteristics
Symbol
tpD
tsu
tH
tco
feNT1
fSYSTEM 2
tpsu
tpH
tpeo
tOE
too
tpOE
tpOD
tWLH
Parameter
I/O to output valid
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
16-bit counter frequency
Multiple FB internal operating frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock to output valid
GTS to output valid
GTS to output disable
Product term OE to output enabled
Product term OE to output disabled
GCK pulse width (High or Low)
XC951 08-7
Min
Max
7.5
5.5
0.0
XC951 08-1 0 XC951 08-15 XC951 08-20
Min
Max
10.0
6.5
0.0
5.5
9.5
7.0
7.0
13.0
13.0
4.0
Max
15.0
8.0
0.0
6.5
111
67
2.5
4.0
125
83
1.5
4.0
Min
Max
20.0
10.0
0.0
8.0
95
56
4.0
4.0
10.5
10.0
10.0
15.5
15.5
4.5
Min
10.0
83
50
4.0
6.0
12.0
15.0
15.0
18.0
18.0
5.5
16.0
20.0
20.0
22.0
22.0
5.5
Units
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Note: 1. tCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG .
2. tSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
3-40
October 28, 1997 (Version 2.0)
~XILINX
VTEST
Output Type
Device Output
o-------.>-----------.--~
VCCIO
VTEST
R1
R2
CL
5.0V
5.0V
160Q
120Q
35 pF
3.3V
3.3V
260Q
360Q
35 pF
X5906
I
Figure 3: AC Load Circuit
Internal Timing Parameters
Symbol
Parameter
XC951 08-7
Min
Max
XC95108-10
Min
Max
XC951 08-15
Min
Max
XC951 08-20
Min
Max
Units
Buffer Delays
Input buffer delay
tiN
GCK buffer delay
tGCK
GSR buffer delay
tGSR
GTS buffer delay
tGTS
Output buffer delay
tOUT
Output buffer enable/disable delay
tEN
ProductTerm Control Delays
Product term clock delay
tpTCK
Product term set/reset delay
tpTSR
Product term 3-state delay
tPTTS
Internal Register and Combinatorial delays
Combinatorial logic propagation delay
tpDI
Register setup time
tSUI
Register hold time
tHI
Register clock to output valid time
teol
Register async. SIR to output delay
tAO I
Register async. SIR recovery before clock
tRAI
Internal logic delay
tLOGI
Internal low power logic delay
tLOGILP
Feedback Delays
FastCONNECT matrix feedback delay
tF
Function Block local feeback delay
tLF
Time Adders
Incremental Product Term Allocator delay
tpTA3
Slew-rate limited delay
tSLEW
2.5
2.5
4.5
7.0
2.5
0.0
3.5
3.0
6.0
10.0
3.0
0.0
4.5
3.0
7.5
15.0
4.5
0.0
6.5
3.0
9.5
20.0
6.5
0.0
ns
ns
ns
ns
ns
ns
4.0
2.0
10.5
3.5
2.5
12.0
2.5
3.0
13.5
2.5
3.0
15.5
ns
ns
ns
4.0
1.0
3.0
2.0
10.0
2.5
11.0
3.0
11.5
3.0
11.5
ns
ns
ns
ns
ns
ns
ns
ns
6.0
2.0
8.5
2.5
11.0
3.5
13.0
5.0
ns
ns
1.0
4.0
1.0
4.5
1.5
5.0
1.5
5.5
ns
ns
0.5
3.5
2.0
3.5
4.5
3.5
3.0
0.5
7.0
0.5
6.5
7.5
10.0
3.5
6.5
0.5
8.0
15.0
0.5
9.0
20.0
Note: 3. IpTA is multiplied by the span of the function as defined in the family data sheet.
October 28, 1997 (Version 2.0)
3-41
XC951 08 In-System Programmable CPLD
XC951 08 1/0 Pins
Function
BScan
Function
BScan
Macrocell PC84 PQ100 TQ100 PQ160
Notes
Notes
Macrocell PC84 PQ100 TQ100 PQ160
Order
Block
Order
Block
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
15
16
21
17
18
-
13
14
19
15
16
17
18
24
20
22
23
25
27
28
-
74
75
19
20
26
22
24
25
27
29
30
98
99
4
1
3
-
-
76
77
5
6
9
8
10
96
97
2
99
1
3
4
7
6
8
7
9
10
11
12
13
71
72
-
79
80
-
-
-
-
81
82
83
84
11
12
13
14
9
10
11
12
-
-
-
25
21
22
29
23
24
27
26
28
36
30
33
34
35
37
42
44
43
158
154
156
4
159
2
9
6
8
12
11
13
14
15
17
18
19
16
321
318
315
312
309
306
303
300
297
294
291
288
285
282
279
276
273
270
267
264
261
258
255
252
249
246
243
240
237
234
231
228
225
222
219
216
[1]
[1]
[1]
[1]
[1]
[1]
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
14
15
-
17
18
29
30
34
32
33
31
32
36
34
35
-
-
-
19
20
35
36
43
37
39
24
25
26
31
-
37
38
45
39
41
42
43
44
51
-
-
-
57
58
61
62
83
84
82
87
88
81
82
80
85
86
87
89
21
23
-
40
41
42
49
-
-
-
63
65
89
91
92
93
66
67
68
69
70
-
90
91
-
-
95
96
94
97
93
94
92
95
-
-
45
47
49
57
54
56
50
58
59
69
60
62
52
63
64
68
77
74
123
134
135
133
138
139
128
140
142
147
143
144
153
146
148
145
152
155
213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108
Notes: [1] Global control pin
3-42
October 28, 1997 (Version 2.0)
~~-
----
~-"
--------------
~XlllNX
XC951 08 1/0 Pins (continued)
Function
BScan
Function
BScan
Macrocell PC84 P0100 T0100 P0160
Macrocell PC84 P0100 T0100 P0160
Notes
Notes
Block
Order
Block
Order
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
-
32
33
52
54
48
55
56
50
52
46
53
54
34
35
-
-
-
36
37
57
58
55
56
-
-
-
39
40
60
62
58
60
-
-
-
41
43
44
63
65
61
66
61
63
59
64
-
-
-
-
76
79
82
72
86
88
78
90
92
84
95
97
87
98
101
96
102
89
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
-
-
-
45
46
67
68
75
69
70
65
66
73
67
68
47
48
-
-
-
50
51
72
73
70
71
-
-
-
52
53
74
76
72
74
-
-
-
54
55
56
78
79
81
80
76
77
79
78
-
-
-
-
91
103
104
116
106
108
105
111
113
107
115
117
112
122
124
129
126
114
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0
I
XC95108 Global, JTAG and Power Pins
Pin Type
PC84
PQ100
TQ100
PQ160
I/O/GCK1
I/O/GCK2
I/O/GCK3
1I0/GTS1
I/O/GTS2
I/O/GSR
9
10
12
76
77
74
30
28
59
29
38,73,78
22,64
8,16,27,42,49,60
24
25
29
5
6
1
50
47
85
49
7,59,100
28,40,53,90
2,23,33,46,64,71,77,86
22
23
27
3
4
99
48
45
83
47
5,57,98
26,38,51,88
100,21,31,44,62,69,75,84
33
35
42
6
8
159
75
71
136
73
10,46,94,157
1,41,61,81,121,141
20,31,40,51,70,80,99
100,110,120,127,137
160
3,5,7,32,38,39,48,53,55,6
5,66,67,83,85,93,109,
118,119,125,130,131,
132,149,150,151
TCK
TOI
TOO
TMS
VCCINT 5 V
VCCIO 3.3 VIS V
GNO
GNO
GNO
No connects
-
-
-
-
-
-
October 28, 1997 (Version 2.0)
3-43
XC951 08 In-System Programmable CPLD
Ordering Information
XC95108 -7 PQ 160 C
J I 1;
Device Type ]
Speed
Package Type
Packaging Options
Speed Options
- 20
-15
-10
-7
Temperature Range
Number of Pins
PC84
PQ100
TQ100
PQ160
20 ns pin-to-pin delay
15 ns pin-to-pin delay
10 ns pin-to-pin delay
7 ns pin-to-pin delay
84-Pin Plastic Leaded Chip Carrier (PLCC)
1~O-Pin Plastic Quad Flat Pack (PQFP)
1~O-Pin Very Thin Quad Flat Pack (TQFP)
160-Pin Plastic Quad Flat Pack (PQFP)
Temperature Options
C
I
Commercial
Industrial
DOC to 70°C
-40°C to 85°C
Component Availability
Pins
Type
Code
XC95108
C ~ Commercial
3-44
-20
-15
-10
-7
~
84
Plastic
PLCC
PC84
C,I
C,I
C,I
Plastic
PQFP
PQ100
C,I
C,I
C,I
Plastic
TQFP
C
C
C
0° to +70°C
100
I ~ Industrial
~
TQ100
C,I
C,I
C,I
160
Plastic
PQFP
PQ160
C,I
C,I
C,I
C
-40° to 85°C
October 28, 1997 (Version 2.0)
XC95144 In-System
Programmable CPLD
November 21, 1997 (Version 3.0)
Preliminary Product Specification
Features
Operating current for each design can be approximated for
specific operating conditions using the following equation:
•
•
•
•
•
•
•
•
•
•
•
7.5 ns pin-to-pin logic delays on all pins
fCNT to 111 MHz
144 macrocells with 3,200 usable gates
Up to 133 user 110 pins
5 V in-system programmable
Endurance of 10,000 programlerase cycles
- Programlerase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3 V or 5 V 110 capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 100-pin PQFP, 1OO-pin TQFP, and 160-pin
PQFP packages
Description
The XC95144 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architecture overview.
Icc (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mNMHz) f
Where:
MCHP = Macrocells in high-performance mode
I
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95144
device.
600,-------------,--------------,
g<'
400
(320)
"
.£> (300)
0;
u
'0.
>.
f--
200
(160)
o
50
Clock Frequency (MHz)
100
X5898B
Figure 1: Typical Icc vs. Frequency for XC95144
Power Management
Power dissipation can be reduced in the XC95144 by configuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
November 21, 1997 (Version 3.0)
3-45
XC95144 In-System Programmable CPLD
3
JTAG Port {
JTAG
Controller
1/
t
I.,.
J
.1
In-System Programming Controller
1
{
t
36
Function
Block 1
18
I/O
1
1/0
II
t tt
I/O
36
x
.;:
1/0
•
•
•
•
Cii
~
1/0
Blocks
1
~
.~
(f)
z
z
1/0
0
a
Function
Block 3
18/
I
CIS
LL
II
1/0
36
1
I/O/GTS
Function
Block 4
18/
I/O/GSR
I
I
2
Macrocells
1 to 18
tt t
3
I/O/GCK
Macrocells
1 to 18
t tt
36
'lii
1/0
II
I-
aUJ
1/0
Function
Block 2
18/
.c
Macrocells
1 to 18 I
Macrocells
1 to 18
~
tt
•
•
•
~
36
18/
I
~
tt
Function
Block 8
I
Macrocells
1 to.18
I
tt
X5922
Figure 2: XC95144 Architecture
Function Block outputs (indicated by the bold line) drive the 1/0 Blocks directly.
3-46
November 21, 1997 (Version 3.0)
~XIUNX
Absolute Maximum Ratings
Symbol
VCC
VIN
VTS
TSTG
TSOL
Parameter
Supply voltage relative to GND
DC input voltage relative to GND
Voltage applied to 3-state output with respect to GND
Storage temperature
Max soldering temperature (10 s@ 1/16 in = 1.5 mm)
Value
-0.5 to 7.0
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
-65 to +150
+260
Units
V
V
V
°C
°C
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions tor extended periods
of time may affect device reliability.
Recommended Operation Conditions1
Symbol
VCCINT
VCCIO
VIL
VIH
Vo
Parameter
Supply voltage for internal logic and input buffer
Supply voltage for output drivers for 5 V operation
Supply voltage for output drivers for 3.3 V operation
Low-level input voltage
High-level input voltage
Output voltage.
Min
4.75
(4.5)
4.75 (4.5)
3.0
0
2.0
0
Max
5.25
(5.5)
5,25 (5.5)
3.6
0.80
VCCINT +0.5
VCCIO
Min
20
10,000
Max
I
Units
V
V
V
V
V
V
Note: 1. Numbers in parenthesis are lOr industrial-temperature range versions.
Endurance Characteristics
Symbol
tDR
NpE
Parameter
Data Retention
Program/Erase Cycles
November 21, 1997 (Version 3.0)
-
Units
Years
. Cycles
3-47
XC95144ln·System Programmable CPLD
DC Characteristics Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
Output high voltage for 5 V operation
VOH
Output high voltage for 3.3 V operation
Output low voltage for 5 V operation
VOL
Output low voltage for 3.3 V operatiqn
IlL
Input leakage current
IIH
liD high-Z leakage current
CIN
liD capacitance
Icc
Operating Supply Current
(low power mode, active)
Min
Max
2.4
10H = -4.0 mA
VCC= Min
10H = -3.2 mA
VCC= Min
10L = 24 mA
Vce= Min
10L = 10 mA
Vec= Min
Vee = Max
VIN = GND or Vce
VCC= Max
VIN = GND or Vec
VIN = GND
f = 1.0 MHz
VI = GND, No load
f = 1.0 MHz
Units
V
V
2.4
0.5
V
0.4
V
±10.0
~
±10.0
~
10.0
pF
160 (Typ)
ma
AC Characteristics
Symbol
Parameter
XC95144·7
Min
tpD
tsu
tH
liD to output valid
teo
feNT1
GCK to output valid
16-bit counter frequency
Multiple FB internal operating frequency
liD setup time before p-term clock input
liD hold time after p-term clock input
P-term clock to output valid
GTS to output valid
GTS to output disable
Product term DE to output enabled
Product term DE to output disabled
GCK pulse width (High or Low)
fSYSTEM
tpsu
tpH
tpco
tOE
too
tpOE
tpOD
tWLH
liD setup time before GCK
liD hold time after GCK
2
Max
XC95144·10
Min
7.5
5.5
0.0
Max
5.5
Max
Units
15.0
8.0
0.0
8.0
6.5
111
67
2.5
4.0
9.5
7.0
7.0
13.0
13.0
4.0
Min
10.0
6.5
0.0
125
83
1.5
4.0
XC95144·15
10.5
10.0
10.0
15.5
15.5
4.5
Preliminary
95
56
4.0
4.0
12.0
15.0
15.0
18.0
18.0
5.5
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Note: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum flip-flop toggle rate, fTOO.
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
3-48
November 21, 1997 (Version 3.0)
~XILINX
VTEST
Output Type
Device Output
CL
VCCIO
5.0V
VTEST
5.0V
R1
R2
160n
120n
35 pF
3.3V
3.3V
260n
360n
35 pF
o-----.--------<.._--{i
X5906
I
Figure 3: AC Load Circuit
Internal Timing Parameters
Symbol
Parameter
Buffer Delays
Input buffer delay
tiN
GGK buffer delay
tGCK
GSR buffer delay
tGSR
GTS buffer delay
tGTS
9utput buffer delay
tOUT
Output buffer enable/disabledelay
tEN
Product Term Control [)elays
Product term clock delay
tpTCK
Product term set/rese,t delay
tpTSR
Productterm3-state delay
tPTTS
Internal Register arid Combinatorial delays
Combinatorial logic propagation delay
tpOl
Register setup time
tSUI
Register hold time
tHI
Register clock to output valid time
tCOI
Register async. SIR to output delay
tAOI
Register async. SIR recovery before clock
tRAI
Internal logic delay
tLOGI
Internal low power logic delay
tLOGILP
Feedback Delays
FastCONNECT matrix feedback delay
tF
Function Block local feedback delay
tLF
Time Adders
Incremental Product Term Allocator delay
tpTA3
Slew-rate limited delay
tSLEW
XC95144-7
XC95144-10 XC95144-15
Min
Min
Max
2.5
2.5
4.5
7.0
2.5
0.0
4.0
2.0
10.5
Max
Min
3.5
3.0
Max
Units
10.0
3.0
0.0
4.5
3.0
7.5
15.0
4.5
0.0
ns
ns
ns
ns
ns
ns
3.5
2.5
12.0
2.5
3.0
13.5
ns
ns
ns
3.0
~~O
,
Note:
0.5
1.0
2.0
10.0
2.5
11.0
3.0
11.5
ns
ns
ns
ns
ns
ns
ns
ns
6.0
2.0
8.5
2.5
11.0
3.5
ns
ns
1.0
4.0
1.0
4.5
Preliminary
1.5
5.0
ns
ns
3.5
2.0
3.5
3.0
0.5
6.5
7.5
3.5
4.5
0.5
7.0
10.0
0.5
8.0
15.0
3. tpTA is multiplied by the span of the function as defined in the family data sheet.
November 21, 1997 (Version 3.0)
3-49
XC95144 In-System Programmable CPLD
XC95144 1/0 Pins
Function
Macrocell
Block
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TQ
100
PQ
100
-
-
11
12
13
14
15
16
17
18
13
14
15
16
17
18
19
20
-
-
19
20
21
22
-
-
22
24
-
-
99
1
2
1
3
4
-
-
3
4
5
6
-
-
6
7
8
9
-
-
8
9
10
11
-
-
10
12
-
-
PQ BScan
Notes
160 Order
25
429
18
426
19
423
27
420
21
417
22
414
32
411
23
408
24
405
34
402
26
399
28
396
38
393
29
390
387
30
384
39
381
33
[1]
378
158 375
159 372
[1]
3
369
5
366
363
2
[1]
360
4
[1]
7
357
354
6
[1]
351
8
[1]
348
9
11
345
12
342
14
339
13
336
15
333
16
330
327
17
- 324
Function
Macrocell
Block
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TQ
100
23
-
PQ
100
25
-
-
-
24
25
26
27
-
-
27
28
29
30
-
-
29
30
31
32
-
-
32
33
34
35
-
-
34
-
36
-
-
87
-
89
-
-
-
89
90
91
92
-
-
91
92
93
94
-
-
93
94
95
96
-
-
95
96
97
97
98
99
-
-
PQ BScan
Notes
160 Order
43
321
35
318
[1]
45
315
48
312
36
309
37
306
50
303
42
300
[1]
44
297
52
294
47
291
49
288
53
285
54
282
56
279
55
276
57
273
270
132
267
140
264
147
261
149
258
142
255
143
252
150
249
144
246
145
243
151
240
146
237
148
234
153
231
152
228
154
225
155
222
156
219
216
..
Notes: [1] Global control pin.
Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG.and Global
Signals are fixed.
3-50
November 21, 1997 (Version 3.0)
~XILINX
XC95144 1/0 Pins (continued)
TQ
Function
Macrocell
Block
100
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PQ
PQ
100
-
-
43
' 46
49
45
48
51
160
65
58
66
67
59
60
74
62
63
76
64
68
78
69
72
83
77
-
-
-
74
-
76
-
76
77
78
79
80
81
-
-
35
-
37
38
39
36
37
-
-
39
40
41
42
-
-
41
42
43
44
-
-
-
86
-
88
117
119
123
122
124
125
126
129
128
133
134
130
135
138
131
139
-
-
-
78
79
-
-'
-
80
81
82
83
-
-
82
85
84
87
November 21, 1997 (Version 3.0)
BScan
Notes
Order
213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108
Function
Macrocell
Block
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TQ
PQ
PQ
100
100
160
-
-
50
52
53
52
54
55
-
-
-
59
60
61
62
61
63
79
84
85
82
86
87
88
90
89
92
95
91
96
97
93
98
-
-
-
63
64
65
66
67
68
70
65
66
67
68
69
70
72
101
105
107
102
103
109
104
106
112
108
111
114
113
115
118
116
-
-
-
54
55
56
57
-
-
56
58
58
60
-
-
-
-
71
72
73
74
-
-
73
75
-
-
BScan
Notes
Order
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0
I
3-51
XC95144 In-System Programmable CPLD
XC95144 Global, JTAG and Power Pins
Pin Type
TQ100
PQ100
PQ160
1I0/GCK1
I/O/GCK2
1I0/GCK3
I/O/GTS1
I/O/GTS2
I/O/GTS3
I/O/GTS4
I/O/GSR
22
23
27
3
4
1
2
99
48
45
83
47
5,57,98
26,38,51,88
100,21,31,44,62,69,
75,84
24
25
29
5
6
3
4
1
50
47
85
49
7,59,100
28,40,53,90
2,23,33,46,64,71,
77,86
-
-
33
35
42
6
8
2
4
159
75
71
136
73
10,46,94,157
1,41,61,81,121,141
20,31,40,51,70,80,
99,100,110,120,127,
137,160
-
TCK
TDI
TOO
TMS
VCCINT5 V
VCCIO 3.3 V/5 V
GND
No Connects
3-52
November 21, 1997 (Version 3.0)
~XILINX
Ordering Information
XC95144 -7 PQ 160 C
Device Type]
JI
~
Temperature Range
Number of Pins
Speed
Package Type
Packaging Options
Speed Options
PQ100 1~O-Pin Plastic Quad Flat Pack (PQFP)
TQ100 1~O-Pin Very Thin Quad Flat Pack (TQFP)
PQ160 160-Pin Plastic Quad Flat Pack (PQFP)
-15 15 ns pin-to-pin delay
-10 10 ns pin-to-pin delay
-7
7 ns pin-to-pin delay
I
Temperature Options
C
I
Commercial
Industrial
DOC to 70°C
-40°C to 85°C
Component Availability
Pins
Type
100
Code
XC95144
-15
-10
-7
Plastic
PQFP
PQ100
C,I
C,I
C
C = Commercial = 0° to +70°C
Plastic
TQFP
TQ100
C,I
C,I
C
160
Plastic
PQFP
PQ160
C,I
C,I
C
I = Industrial = -40° to 85°C
November 21, 1997 (Version 3.0)
3-53
XC95144 In-System Programmable CPLD
3-54
November 21 , 1997 (Version 3.0)
XC95216 In-System
Programmable CPLD
October 28, 1997 (Version 2.0)
Product Specification
Features
Power Management
•
•
•
•
•
Power dissipation can be reduced in the XC95216 by configuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
•
•
•
•
•
•
•
•
•
•
•
•
•
iOns pin-to-pin logic delays on all pins
fCNT to 111 MHz
216 macrocells with 4800 usable gates
Up to 166 user 1/0 pins
5 V in-system programmable
- Endurance of 10,000 programlerase cycles
- Programlerase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
., Global and product term clocks, output enables, set
;;lnd reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3 V or 5 V 1/0 capability
PCI compliant (-10 speed grade)
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 160-pin PQFP, 352-pin BGA, and 208-pin
HQFP packaQes
Des(;ription
The XC95216 is a high-performance CPLD providing
advanced in~system programming and test capabilities for
general.purpose logic integration. It is comprised of twelve
36V18 Function Blocks, providing 4,800 usable gates with
propagation delays of 10 ns. See Figure 2 for the architecture overview.
.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
Icc (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP
=Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95216
device.
600.-------------.-------------~
(500)
400 I-----="'"""-""=---t---------------j
1 (360)
(340)
~
~
!
200 r--='=-----------t---------------j
o
50
Clock Frequency (MHz)
100
X5918
Figure 1: Typical Icc vs. Frequency For XC95216
October'28, 1997 (Version 2.0)
3-55
I
XC95216 In-System Programmable CPLD
3
JTAG Port {
JTAG
Controller
1
I ..
1
·1
t
36
Function
Block 1
18
1/0
1
1/0
II
"
36
><
"~
•
•
•
•
:2
1
.8
"3:
"
0
1/0
z
z
LlJ
0
0
36
1
1i5
-------..._---{"e1
VCCIO
5.0V
VTEST
5.0V
R1
R2
CL
160 (2
120(2
35 pF
3.3 V
3.3V
260(2
360(2
35 pF
X5906
I
Figure 3: AC Load Circuit
Internal Timing Parameters
Symbol
Parameter
..
Buffer Delays
Input buffer delay
tiN
GCK
buffer delay
tGCK
GSR buffer delay
tGSA
GTS buffer delay
tGTS
Output buffer delay
tOUT
Output buffer enable/disable delay
tEN
Product Term Control Delays
Product term clock delay
tpTCK
Product term set/reset delay
tpTSR
Product term 3-state delay
tpHS
Internal Register and Combinatorial delays
Combinatorial logic propagation delay
tpOI
Register setup time
tSUI
Registerhold time
tHI
Register clock to output valid time
tCOI
Register async. SIR to output delay
tAOI
Register async. SIR recovery before clock
tRAI
Internal
logic delay
tLOGI
Internal low power logic delay
tLOGILP
Feedback Delays
FastCONNECT matrix feedback delay
tF
Function Block local fee back delay
tLF
Time Adders
Incremental Product Term Allocator delay
tpTA 3
Slew-rate limited delay
tSLEW
XC95216-10
Min
Max
XC95216-15
Min
Max
XC95216-20
Min
Max
Units
3.5
3.0
6.0
10.0
3.0
0.0
4.5
3.0
7.5
15.0
4.5
0.0
6.5
3.0
9.5
20.0
6.5
0.0
ns
ns
ns
ns
ns
ns
3.5
2.5
12.0
2.5
3.0
13.5
2.5
3.0
15.5
ns
ns
ns
4.0
2.5
11.0
3.0
11.5
3.0
11.5
ns
ns
ns
ns
ns
ns
ns
ns
8.5
2.5
11.0
3.5
13.0
5.0
ns
ns
1.0
4.5
1.5
5.0
1.5
5.5
ns
ns
3.0
1.0
3.5
3.0
3.5
6.5
3.5
4.5
0.5
7.0
15.0
10.0
0.5
9.0
0.5
8.0
20.0
Note: 3. tpTA is multiplied by the span of the function as defined in the family data sheet.
October 28, 1997 (Version 2.0)
3-59
XC95216 In-System Programmable CPLD
XC95216 I/O Pins
Function
Macrocell PQ160
Block
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3-60
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
18
19
21
22
23
24
25
26
27
28
29
30
6
7
8
9
HQ208
BG352
22
23
28
25
30
31
32
12
33
34
M25
M26
N26
N25
P23
P24
R26
G26
R24
T26
T25
T23
V26
U24
E25
G24
P25
F26
H23
K23
K24
35
36
37
38
7
8
29
9
10
-
-
11
12
15
16
-
-
-
13
14
17
18
J25
L24
-
-
-
15
16
19
20
14
21
K25
L26
H25
M24
-
-
17
-
BScan
Order
645
642
639
636
633
630
627
624
621
618
615
612
609
606
603
600
597
594
591
588
585
582
579
576
573
570
567
564
561
558
555
552
549
546
543
540
Notes
[1]
[1]
Function
Macrocell PQ160
Block
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
32
33
34
35
36
37
38
39
42
43
44
152
153
154
155
HQ208
BG352
BScan
Order
-
AA26
Y24
U23
AB25
AA24
Y23
AA23
A018
AB24
A025
A023
AF24
AE12
AE23
018
A21
B19
B20
C20
B22
B24
C23
E23
C26
E24
020
F24
-
537
534
531
528
525
522
519
516
513
510
507
504
501
498
495
492
489
486
483
480
477
474
471
468
465
462
459
456
453
450
447
444
441
438
435
432
43
44
39
45
46
47
49
67
50
51
55
56
80
57
198
199
196
200
201
-
-
156
158
202
205
-
-
159
2
206
3
-
-
3
4
4
5
203
6
5
-
-
Notes
[1]
[1]
[1]
[1]
[1]
[1]
October 28, 1997 (Version 2.0)
~XILINX
XC95216 I/O Pins (continued)
Function
Macrocell PQ160 HQ208 BG352
Block
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
-
-
58
60
41
61
63
64
70
109
71
72
AE20
AF18
ADl
AE17
AE16
-
-
57
73
74
40
75
AF16
AE14
Y26
AF14
-
-
140
142
180
182
208
185
186
187
188
183
191
192
193
194
169
197
-
-
45
47
48
49
50
52
53
54
55
56
-
143
144
145
146
147
148
149
150
151
-
October 28, 1997 (Version 2.0)
AE22
AE21
W25
AF21
AD19
-
A12
A13
D22
C14
A15
815
C15
814
A16
C16
C17
818
D9
C19
-
BScan
Order
429
426
423
420
417
414
411
408
405
402
399
396
393
390
387
384
381
378
375
372
369
366
363
360
357
354
351
348
345
342
339
336
333
330
327
324
Notes
Function
Macrocell PQ160
Block
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
58
59
60
62
63
64
65
66
67
68
69
126
128
129
130
131
132
HQ208 BG352
76
77
54
78
82
83
84
91
85
86
87
88
48
89
-
-
133
134
135
138
139
162
164
143
166
167
170
171
195
173
174
175
178
189
179
-
-
-
AE13
AC13
AE24
AD13
AD12
AC12
AFll
AD8
AEll
AE9
AD9
AC10
AC26
AF7
85
86
Jl
D8
87
Cl0
89
A20
A9
Dl1
811
C12
D15
812
-
BScan
Order
Notes
321
318
315
312
309
306
303
300
297
294
291
288
285
282
279
276
273
270
267
264
261
258
255
252
249
246
243
240
237
234
231
228
225
222
219
216
I
3-61
XC95216 In-System Programmable CPLD
XC95216 1/0 Pins (continued)
Function
Macrocell PQ160
Block
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
3-62
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
HQ208
BG352
AD7
AE5
AD4
AC7
AE3
86
-
95
97
101
99
100
102
103
90
110
111
112
113
62
114
-
AC1
AA2
AC19
AA1
-
-
-
-
113
114
147
148
144
149
150
H3
J4
K3
G2
G3
72
74
76
77
78
79
82
83
84
85
-
115
116
AC5
AD3
AE8
AA4
AB2
-
-
-
-
117
118
119
122
123
124
125
152
154
168
155
158
E2
D2
A7
F4
B3
-
-
-
159
160
165
161
-
A3
D6
A6
C6
-
BScan
Order
213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108
Notes
Function
Macrocell PQ160
Block
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
87
88
89
90
91
92
93
95
HQ208 BG352
115
116
119
117
118
Vi
V4
U4
V3
W2
-
-
98
121
122
107
123
125
126
127
120
128
V2
U2
AC3
T2
R4
R3
R2
U3
R1
-
-
-
101
102
131
133
106
134
135
Pi
96
97
-
103
104
105
106
107
108
109
111
112
-
136
137
151
138
139
140
145
142
146
-
N2
AD2
N4
N3
M1
M3
F2
M4
L1
L2
G1
L3
H2
-
BScan
Order
Notes
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0
October 28, 1997 (Version 2.0)
~XILINX
XC95216 Global, JTAG and Power Pins
PQ160
Pin Type
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GTS3
I/O/GTS4
I/O/GSR
TCK
TDI
TOO
TMS
VCCINT 5 V
VCCIO 3.3 V/5 V
33
35
42
6
8
2
4
159
75
71
136
73
10,46,94,157
1,41,61,81,121,141
GNO
20,31,40,51,70,80,99,100,
110,120,127,137,160
No Connects
-
October 28, 1997 (Version 2.0)
HQ208
BG352
Y24
44
46
AA24
A023
55
7
E25
F26
9
E23
3
E24
5
206
C23
A06
98
94
AF6
012
176
AE6
96
11,59,124,153,204
H24,AF23,T1,G4,C22
1,26,53,65,79,92,105,132,
A10,A17,B2,B25, 07, 013,
157,172,181,184
019, G23, H4, K1, K26, N23, P4,
U1, U26, W23, Y4, AC8, AC14,
AC20,AE25,AF10,AF17
2,13,24,27,42,52,66,68,69, A1, A2, A5, A8, A14, A19, A22,
81,93,104,108,129,130,141, A25,A26,B1,B26,C7,E1,E26,
156,163,177,190,207
H1, H26, N1, P3, P26, V23, W1 ,
W26, AB1, AB4, AB26, AC9,
AC17, AE1, AE26, AF1, AF2,
AF5, AF8, AF13, AF19, AF20,
AF22, AF25, AF26
A4, A 11, A 18, A23, A24, B4, B8,
B10,B13, B16, B17,B21,B23,
C1, C2, C3, C4, C5, C8, C9, C11,
C13, C18, C21, C24, C25, 01,
03,04,05,010,014,016,017,
021,023,024,025,026, E3,
E4, F1, F3, F23, F25, G25, J2,
J3,J23,J24,J26, K2, K4, L4,
L23, L25, M2, M23, N24, P2,
R23, R25, T3, T4, T24, U25, V1,
V24, V25, W3, W4, W24, Y2, Y3,
Y25, AA3, AA25, AB3, AB23,
AC2, AC4, AC6, AC11, AC15,
AC16, AC18, AC21 , AC22,
AC23, AC24, AC25, A05, A01 0,
A011, A014, A015, A016,
A017, A020, A021, A022,
A024, A026, AE2, AE4, AE7,
AE1 0, AE15, AE18, AE19, AF3,
AF4,AF9,AF12,AF15
3-63
I
XC95216 In-System Programmable CPLD
Ordering Information
J:]
XC95216 -10 HQ 208 C
Device Type
TT
C
Speed
Temperature Range
Number of Pins
Package Type
Packaging Options
Speed Options
PQ160 160-Pin Plastic Quad Flat Pack (PQFP)
HQ208 208-Pin Heat Sink Quad Flat Pack (HQFP)
BG352 352-Pin Ball Grid Array (BGA)
- 20 20 ns pin-to-pin delay
-15 15 ns pin-to-pin delay
-10 10 ns pin-to-pin delay
Temperature Options
C
I
Commercial
Industrial
O°C to 70°C
-40°C to 85°C
Component Availability
Pins
Type
Code
XC95216
C = Commercial
3-64
-20
-15
-10
160
Plastic
PQFP
PQ160
C,I
C
C
= 0° to +70°C
160
Power
QFP
HQ208
C,I
C
C
I = Industrial
352
Plastic
BGA
BG352
C,I
C,I
C
= -40° to 85°C
October 28,1997 (Version 2.0)
XC95288 In-System
Programmable CPLD
November 12, 1997 (Version 2.0)
Preliminary Product Specification
Features
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
•
•
•
•
•
Where:
•
•
•
•
•
•
•
•
•
•
•
•
•
15 ns pin-to-pin logic delays on all pins
fCNT to 95 MHz
288 macrocells with 6,400 usable gates
Up to 192 user I/O pins
5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High7drive 24 mA outputs
3.3 V or 5 V I/O capability
PCI compliant (-10,speed grade)
Advanced CMOS 5V FastFLASH technology
Supports'parallel programming of more than one
XC9500 concurrently
Available in 352-pin BGA and 208-pin HQFP packages
MCHP
= Macrocells in high-performance mode
MCLP
=Macrocells in low-power mode
MC '" Total number of macrocells used
'" Clock frequency (MHz)
I
900,-------------,-------------,
(700)
<
~
600r-------~~--~----------~
(500)
(500)
,9
i
300~~~--------r-----------~
o
Figure 1: Typical
50
Clock Frequency (MHz)
100
X7131
Icc vs. Frequency For XC95288
Description
The XC95288 is a high-perforllJance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of sixteen
36V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 10 ns. See Figure'2 for the architecture overview.
Power Management
Power dissipation can be reduced in the XC95288 by configuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
November12, 1997 (Version 2:0)
3-65
XC95288 In-System Programmable CPLD
JTAG Port {
3/
1/ /
JTAG
Controller
/
I
I
I
In-System Programming Ccmtroller
I
36
18
1/0
I Macrocells I
1
1/0
Function
Block 1
1 to 18
tt
1/0
•
•
•
•
'lii
::i:
1/0
Blocks
+Function
36
.~
1/0
18/
Block 2
1
.c
.9
.§
I
en
w
z
z
1/0
0
~
1/0
+Function
36
18
Block 3
I Macrocells I
1
LL
L1 to 18
1/0
: tt
3
I/O/GCK
I/O/GSR
I/O/GTS ~
36
1
Function
Block 4
18/
/
1
2
I
tt
I-
()
1/0
Macrocells
1 to 18
I
/
Macrocells
1 to 18
~
I
tt
•
•
•
~
36
18 7
I
~
tt
Function
Block 16
I
Macrocells
1to 18
I
tt
X5924
Figure 2: XC95288 Architecture
Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly
3-66
November12, 1,997 (Version 2.0)
~XILINX
Absolute Maximum Ratings
Symbol
Parameter
Supply voltage relative to GND
DC input voltage relative to GND
Voltage applied to 3-state output with respect to GND
Storage temperature
Max soldering temperature (10 s @ 1/16 in = 1.5 mm)
Vee
VIN
VTS
TSTG
TSOL
Value
Units
-0.5 to 7.0
-0.5 to Vee + 0.5
-0.5 to Vee + 0.5
-65 to +150
+260
V
V
V
°C
°C
Warning: Stresses beyond those listed under Apsolute Maximum Ratings may cause. permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.
Recommended Operation Conditions
Symbol
1
Parameter
VeelNT
Supply voltage for internal logic and input buffer
Veelo
Supply voltage for output drivers for 5 V operation
Supply voltage for output drivers for 3.3 V operation
Low-level input voltage
High-level input voltage
Output voltage
.,
VIL
VIH
Vo
I
Min
Max
Units
4.75
(4.5)
4.75 (4.5)
3.0
0
2.0
0
5.25
(5.5)
5.25(5.5)
3.6
0.80
V
VeeINT+0.5
VeCJO
Min
Mal(
Units
20
-
Years
10,000
-
Cycles
V
V
V
V
V
Note: 1. Numbers in parenthesis are for industrial-terilperature range versions.
Endurance Characteristics
Symbol
tDR
NpE
Parameter
Data Retention
Program/EraseCycles
November 12, 199T(Version2.0)
3-67
XC95288 In-System Programmable CPLD
DC Characteristics Over Recommended Operating Conditions
Symbol
VOH
Parameter
Test Conditions
Output high voltage for 5 V operation
10H = -4.0mA
Vee = Min
10H = -3.2 mA
Vee = Min
IOL=24mA
Vee = Min
IOL=10mA
Vee = Min
Vee = Max
VIN = GND or Vee
Vee = Max
VIN = GND or Vee
VIN = GND
f = 1.0 MHz
Output high voltage for 3.3 V operation
VOL
Output low voltage for 5 V operation
Output low voltage for 3.3 V operation
IlL
Input leakage current
IIH
I/O high-Z leakage current
CIN
I/O capacitance
ICC
Operating Supply Current
(low power mode, active)
VI = GND, No load
f = 1.0 MHz
Min
Max
2.4
Units
V
V
2.4
0.5
V
0.4
V
±10.0
J.lA
±10.0
J.lA
10.0
pF
300 (Typ)
ma
AC Characteristics
Symbol
XC95288-15
Units
Min
tpD
tsu
tH
teo
feNT1
fSYSTEM 2
tpsu
tpH
tpeo
tOE
too
tpOE
tpOD
tWLH
XC95288-20
Parameter
I/O to output valid
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
16-bit counter frequency
Multiple FB internal operating frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock to output valid
GTS to output valid
GTS to output disable
Product term OE to output enabled
Product term OE to output disabled
GCK pulse width (High or Low)
Max
Min
15.0
8.0
0.0
Max
20.0
10.0
0.0
8.0
95
56
4.0
4.0
10.0
83
50
4.0
6.0
12.0
15.0
15.0
18.0
18.0
5.5
16.0
20.0
20.0
22.0
22.0
5.5
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Note: 1. fCNT is the fastest 16·bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG .
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
3-68
November 12,1997 (Version 2.0)
~XILINX
Output Type
Device Output
0 - - -_____- - - - -__- - ( . ,
VTEST
5.0 V
R1
1600
R2
1200
CL
5.0 V
3.3 V
3.3 V
2600
3600
35 pF
VCCIO
35 pF
X5906
Figure 3: AC Load Circuit
II
Internal Timing Parameters
Symbol
Parameter
Buffer Delays
Input buffer delay
tiN
GCK buffer delay
tGCK
GSR buffer delay
tGSR
GTS buffer delay
tGTS
Output buffer delay
tOUT
Output buffer enable/disable delay
tEN
Product Term Control Delays
Product term clock delay
tpTCK
Product term set/reset delay
tpTSR
Product term 3-state delay
tpTTS
Internal Register and Combinatorial delays
Combinatorial logic propagation delay
tpDI
Register setup time
tSUI
Register hold time
tHI
Register clock to output valid time
tCOI
Register async. SIR to output delay
tAO I
Register async. SIR recovery before clock
tRAI
Internal logic delay
tLOGI
Internal low power logic delay
tLOGILP
Feedback Delays
FastCONNECT matrix feedback delay
tF
Function Block local feeback delay
tLF
Time Adders
Incremental Product Term Allocator delay
tpTA3
Slew-rate limited delay
tSLEW
XC95288-15
XC95288-20
Min
Min
Max
Max
Units
4.5
3.0
7.5
15.0
4.5
0.0
6.5
3.0
9.5
20.0
6.5
0.0
ns
ns
ns
ns
ns
ns
2.5
3.0
13.5
2.5
3.0
15.5
ns
ns
ns
4.0
3.0
11.5
3.0
11.5
ns
ns
ns
ns
ns
ns
ns
ns
11.0
3.5
13.0
5.0
ns
ns
1.5
5.0
1.5
5.5
ns
ns
3.0
3.5
4.5
3.5
6.5
0.5
8.0
15.0
0.5
9.0
20.0
Note: 3. tpTA is multiplied by the span of the function as defined in the family data sheet.
November 12, 1997 (Version 2.0)
3-69
XC95288 In-System Programmable CPLD
XC95288 I/O Pins
Function
Block
Macrocell
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
HQ208 BG352
-
-
28
29
N26
P25
P23
P24
R26
R25
R24
R23
T26
T25
T23
V26
30
31
32
33
34
35
36
37
-
-
15
16
17
18
19
20
21
22
23
25
-
K23
K24
J25
L24
K25
L25
L26
M23
M24
M25
M26
N25
-
BScan
Notes
Order
861
858
855
852
849
846
843
840
837
834
831
828
825
822
819
816
813
810
807
804
801
798
795
792
789
786
783
780
777
774
771
768
765
762
759
756
Function
Block
Macrocell
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
HQ208 BG352
-
-
38
39
U24
U23
-
-
40
41
Y26
W25
-
-
43
AA26
Y25
Y24
AA25
AB25
44
45
-
-
46
47
48
AA24
Y23
AC26
E23
C26
E24
F24
E25
026
G24
F25
F26
H23
G26
H25
-
3
4
5
6
7
8
9
10
12
14
-
BScan
Notes
Order
753
750
747
744
741
738
735
732
729
726
723
720
717
714
711
708
705
702
699
696
693
690
687
684
681
678
675
672
669
666
663
660
657
654
651
648
[1]
[1]
[1]
[1]
[1]
[1]
Notes: [1] Global control pin
Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global
Signals are fixed.
3-70
November 12, 1997 (Version 2.0)
.-------------------
~XILINX
XC95288 1/0 Pins (continued)
Function
Block
Macrocell
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Note:
HQ208 BG352
49
50
51
54
55
56
57
58
60
61
197
198
199
200
201
202
203
AA23
AB24
A025
AE24
A023
AC22
AF24
A022
AE23
AE22
AE21
AF21
C19
018
A21
B20
C20
B21
B22
C21
020
-
-
205
206
B24
C23
022
-
208
-
BScan
Notes
Order
645
642
639
636
633
630
627
624
621
618
615
612
609
606
603
600
597
594
591
588
585
582
579
576
573
570
567
564
561
558
555
552
549
546
543
540
[1]
[1]
Function
Block
Macrocell
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
HQ208 BG352
62
63
64
66
67
69
70
71
72
73
186
187
188
189
191
192
193
194
195
196
-
AC19
A019
AE20
AC18
A018
AE19
A017
AE18
AF18
AE17
AE16
AF16
A15
B15
C15
015
A16
B16
C16
B17
C17
B18
A20
B19
-
BScan
Notes
Order
537
534
531
528
525
522
519
516
513
510
507
504
501
498
495
492
489
486
483
480
477
474
471
468
465
462
459
456
453
450
447
444
441
438
435
432
II
[1] Global control pin
November 12, 1997 (Version 2.0)
3-71
XC95288 In-System Programmable CPLD
XC95288 110 Pins (continued)
Function
Block
Macrocell
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
3-72
HQ208 BG352
74
75
76
77
78
80
82
83
84
85
86
170
171
173
174
175
178
179
180
182
183
185
-
AE14
AF14
AE13
AC13
A013
AF12
AE12
A012
AC12
AF11
AE11
AE9
C10
89
A9
011
811
A11
C12
812
A12
A13
814
C14
-
BScan
Notes
Order
429
426
423
420
417
414
411
408
405
402
399
396
393
390
387
384
381
378
375
372
369
366
363
360
357
354
351
348
345
342
339
336
333
330
327
324
Function
Block
Macrocell
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
HQ208 BG352
-
-
87
88
AD9
AC10
-
-
89
90
AF7
AE8
AD8
AE7
AD7
AE5
AC7
91
95
97
99
-
-
100
101
102
158
159
160
161
162
164
165
166
167
168
169
-
AE3
AD4
AC5
83
A3
06
C6
85
A4
86
A6
08
87
A7
09
-
BScan
Notes
Order
321
318
315
312
309
306
303
300
297
294
291
288
285
282
279
276
273
270
267
264
261
258
255
252
249
246
243
240
237
234
231
228
225
222
219
216
November 12, 1997 (Version 2.0)
~XILINX
XC95288 1/0 Pins (continued)
Function
Block
Macrocell
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
HQ208 BG352
103
106
110
AD3
AD2
AC3
AD1
AM
-
AA3
111
112
113
AB2
AC1
AA2
AA1
Y1
107
109
-
114
115
116
V4
-
-
144
145
146
147
148
149
150
151
152
154
155
-
K3
G1
H2
H3
November 12, 1997 (Version 2.0)
J4
F1
G2
G3
F2
E2
D2
F4
-
BScan
Notes
Order
213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108
Function
Block
Macrocell
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
HQ208 BG352
-
-
117
118
V3
W2
-
-
119
120
121
122
123
125
126
127
U4
U3
V2
V1
U2
T2
R4
R3
R2
R1
P1
N2
N4
N3
M1
M2
M3
M4
L1
L2
L3
J1
-
128
131
133
134
135
136
137
138
139
140
142
143
-
BScan
Notes
Order
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0
II
3-73
XC95288 In-System Programmable CPLD
XC95288 Global, JTAG and Power Pins
Pin Type
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GTS3
I/O/GTS4
I/O/GSR
TCK
TDI
TOO
TMS
VCCINT 5 V
VCCIO 3.3 VIS V
GND
No Connects
3-74
HQ208
BG352
44
46
55
7
9
3
5
206
98
94
176
96
11,59,124,153,204
Y24
AA24
AD23
E25
F26
E23
E24
C23
AD6
AF6
D12
AE6
J23, V24, AF23, AC15, AF15,
AD11, AD5, Y3, T1, J3, G4, D5,
D10,B13,D17,C22,H24
A10,A17,B2,B25, D7,D13,
1,26,53,65,79,92,105,132,
157,172,181,184
D19, G23, H4, K1, K26, N23, P4,
U1, U26, W23, Y4, AC8, AC14,
AC20,AE25,AF10,AF17
2,13,24,27,42,52,68,81,93, A1,A2,A5,A8,A14,A19,A22,
104,108,129,130,141,156, A25,A26,B1,B26,C7,C9,C13,
163,177,190,207
C18,D24,E1,E26,H1,H26,K4,
N1, N24, P3, P26, V23, W1, W4,
W26, AB1 , AB4, AB26, AC9,
AD10, AD14, AD15, AD20, AE1,
AE26, AF1, AF2, AF5, AF8,
AF13,AF19,AF22,AF25,AF26
A18,A23,A24,B4,B8,B10,B23,
C1, C2, C3, C4, C5, C8, C11,
C24,C25,D1,D3,D4,D14,D16,
D21,D23,D25,E3,E4,F3,F23,
G25,J2,J24,J26, K2, L4,L23,
P2, T3, T4, T24, U25, V25, W3,
W24, Y2, AB3, AB23, AC2, AC4,
AC6, AC11, AC16, AC17, AC2.1,
AC23, AC24, AC25, AD16,
AD21 , AD24, AD26, AE2, AE4,
AE10, AE15, AF3, AF4, AF9,
AF20
November 12, 1997 (Version 2.0)
~XILINX
Ordering Information
XC95288 -15 HQ 208 C
Device Type
~
I I
Speed
Number of Pins
L - -_ _ _
Speed Options
Temperature Range
Package Type
Packaging Options
- 20 20 ns pin-to-pin delay
-15 15 ns pin-to-pin delay
HQ208 208-Pin Heat Sink Quad Flat Pack (HQFP)
BG352 352-Pin Plastic Ball Grid Array (BGA)
II
Temperature Options
C
I
Commercial
Industrial
O°C to 70°C
-40°C to 85°C
Component Availability
Pins
Type
Code
XC95288
1-20
1-15
208
Plastic
HQFP
HQ
C,I
352
Plastic
BGA
BG
C,I
C
C
c = Commercial = 0° to +70°C
I = Industrial = --40° to 85°C
November 12,1997 (Version 2.0)
3-75
XC95288 In-System Programmable CPLD
3-76
November 12, 1997 (Version 2.0)
- - "
" " " - "---.-.~
---
FPGA Products
1
Introduction
2
Development System Products and CORE Solutions Products
3
CPLD Products
4
FPGA Products
5
SPROM Products
6
3V Products
7
HardWire FpgASIC Products
8
High-Reliability and QML Military Products
9
Programming Support
10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support and Services
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors
FPGA Products Table of Contents
FPGA Products
XC4000E and XC4000X Series Table of Contents ....•........•......•.•........ 4-1
XC4000E and XC4000X Series Field Programmable Gate Arrays •................• 4-5
XC4000E and XC4000X Series Field Programmable Gate Arrays ........•......... 4-71
XC4000E and XC4000X Series Field Programmable Gate Arrays .................. 4-111
XC4000E and XC4000X Series Field Programmable Gate Arrays .•..•.........•... 4-147
XC4000XV Family Field Programmable Gate Arrays .........•..•............... 4-151
XC4000XLT Family Field Programmable Gate Arrays ........................... 4-159
Spartan and Spartan-XL Families Table of Contents .•........................•. 4-171
Spartan and Spartan-XL Families Field Programmable Gate Arrays ............... 4-173
Spartan and Spartan-XL Families Field Programmable Gate Arrays . . • . . . . . . . . . . .. 4-200
Spartan and Spartan-XL Families Field Programmable Gate Arrays . . . . . . . . . . • . . .. 4-206
Spartan and Spartan-XL Families Field Programmable Gate Arrays ....•..•....... 4-218
XC5200 Series Table of Contents. . . . . . . . . . . • . . . . . . • • . . . . • . . • . . . . . . . . . . . . . • . . 4-221
XC5200 Series Field Programmable Gate Arrays. . . . . . • . . . . • . . • . . . • . . . . . . . . . • .. 4-225
XC3000 Series Table of Contents. • . . • . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . • . . 4-297
XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) ........ .4-299
XC4000E and XC4000X Series
Table of Contents
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000E and XC4000X Series Features ............................................... .
Low-Voltage Versions Available ...................................................... .
Additional XC4000X Series Features .................................................. .
Introduction ...................................................................... .
Description ................................................................ .
Taking Advantage of Reconfiguration ............................................ .
XC4000E and XC4000X Series Compared to the XC4000 ................................. .
Improvements in XC4000E and XC4000X ........................................ .
Additional Improvements in XC4000X Only ....................................... .
Detailed Functional Description ..............................................•........
Basic Building Blocks ...................................•.....................
Configurable Logic Blocks (CLBs) .............................................. .
Function Generators ..................................................... .
Flip-Flops ............................................................. .
Latches (XC4000X only) .................................................. .
Clock Input ............................................................ .
Clock Enable ........................................................... .
Set/Reset .................................................. , .......... .
Global Set/Reset. ....................................................... .
Data Inputs and Outputs .................................................. .
Control Signals ......................................................... .
Using FPGA Flip-Flops and Latches ......................................... .
Using Function Generators as RAM ......................................... .
Fast Carry Logic ........................................................ .
Input/Output Blocks (lOBs) .................................................... .
lOB Input Signals ....................................................... .
lOB Output Signals ...................................................... .
Other lOB Options ...................................................... .
Three-State Buffers .......................................................... .
Three-State Buffer Modes ................................................ .
Three-State Buffer Examples .............................................. .
Wide Edge Decoders ......................... , .............................. .
On-Chip Oscillator ........................................................... .
Programmable Interconnect ......................................................... .
Interconnect Overview ....................................................... .
CLB Routing Connections ..................................................... .
Programmable Switch Matrices ............................................ .
Single-Length Lines ..................................................... .
Double-Length Lines ..................................................... .
Quad Lines (XC4000X only) ................................................ .
Longlines ........................ , ...... " ..... , ...................... .
Direct Interconnect (XC4000X only) ......................... ; ............... .
1/0 Routing ................................................................ .
Octal 1/0 Routing (XC4000X only) .......................................... .
Global Nets and Buffers ...................................................... .
Global Nets and Buffers (XC4000E only) ..................................... .
Global Nets and Buffers (XC4000X only) ..................................... .
Power Distribution ................................................................. .
4-5
4-5
4-5
4-5
4-6
4-6
4-7
4-7
4-8
4-9
4-9
4-9
4-9
4-10
4-10
4-10
4-10
4-11
4-11
4-11
4-11
4-11
4-11
4-18
4-21
4-21
4-24
4-26
4-27
4-27
4-27
4-28
4-28
4-29
4-29
4-29
4-30
4-30
4-32
4-32
4-32
4-33
4-33
4-33
4-36
4-36
4-38
4-40
II
4-1
XC4000E and XC4000X Series Table of Contents
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Boundary Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Bit Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Including Boundary Scan in a Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Avoiding Inadvertent Boundary Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Special Purpose Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration Modes ..........................................................
Master Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional Address lines in XC4000 devices ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Peripheral Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Setting CCLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Data Stream Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Cyclic Redundancy Check (CRC) for Configuration and Readback ......................
Configuration Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration Memory Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . ..
Delaying Configuration After Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Start-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DONE Goes High to Signal End of Configuration ................................
Release of User 1/0 After DONE Goes High .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Release of Global Set/Reset After DONE Goes High ............................
Configuration Complete After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration Through the Boundary Scan Pins ....... , . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Readback Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . ..
Read Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Read Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Clock Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Violating the Maximum High and Low Time Specification for the Readback Clock . . . . . . . . ..
Readback with the XChecker Cable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E/EX/XL Program Readback Switching Characteristic Guidelines . . . . . . . . . . . . . . ..
Configuration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Slave Serial Mode ............................................................
Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Master Parallel Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . ..
Additional Address lines in XC4000 devices ...................................
Synchronous Peripheral Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Asynchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . ..
Write to FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration Switching Characteristics.. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . ..
Master Modes (XC4000E/EX) . ..................................................
Master Modes (XC4000XL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . . . . . . ..
Slave and Peripheral Modes(AII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000XL Switching Characteristics ...................................................
Additional Specifications. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000XL Absolute Maximum Ratings ........................................ ; ..
XC4000XL Recommended Operating Conditions ...................................
XC4000XL DC Characteristics Over Recommended Operating Conditions ................
XC4000XL Global Buffer Switching Characteristic Guidelines ..........................
XC4000XL CLB Switching Characteristic Guidelines .................................
XC4000XL CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines. . . . . . . . ..
4-2
4-40
4-43
4-43
4-45
4-45
4-45
4-46
4-46
4-46
4-47
4-47
4-47
4-47
4-47
4-49
4-49
4-50
4-51
4-51
4-52
4-52
4-52
4-55
4-55
4-55
4-55
4-55
4-56
4-57
4-57
4-57
4-57
4-57
4-57
4-58
4-61
4-61
4-62
4-63
4-63
4-65
4-67
4-67
4-67
4-69
4-69
4-69
4-69
4-71
4-71
4-71
4-71
4-72
4-73
4-74
4-75
~XILINX
CLB RAM Synchronous (Edge-Triggered) Write Timing ..............................
CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing ......................
XC4000XL Pin-to-Pin Output Parameter Guidelines .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Capacitive Load Factor. .......................................................
XC4000XL Pin-to-Pin Input Parameter Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000XL BUFGE #s 3.4,7, and 8 Global Early Clock, Set-Up and Hold for IFF and FCL ...
XC4000XL BUFGE #s 1,2,5, and 6 Global Early Clock, Set-Up and Hold for IFF and FCL ...
XC4000XL lOB Input Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000XL lOB Output Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000EX Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Definition of Terms ...........................................................
XC4000EX Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000EX Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000EX DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . ..
XC4000EX Longline and Wide Decoder Timing Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000EX Wide Decoder Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . ..
XC4000EX CLB Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000EX CLB RAM Synchronous (Edge-Triggered) Write Timing .....................
XC4000EX CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing .............
XC4000EX CLB RAM Asynchronous (Level-Sensitive) Write and Read Operation Guidelines.
XC4000EX CLB RAM Asynchronous (Level-Sensitive) Timing Characteristics. . . . . . . . . . . ..
XC4000EX Pin-to-Pin Output Parameter Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000EX Output MUX, Clock to Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000EX Output Level and Slew Rate Adjustments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000EX Pin-to-Pin Input Parameter Guidelines .........................................
XC4000EX Global Early Clock, Set-Up and Hold for IFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000EX Global Early Clock, Set-Up and Hold for FCL . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000EX Input Threshold Adjustments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000EX lOB Input Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000EX lOB Input Switching Characteristic Guidelines (Continued). . . . . . . . . . . . . . . . . ..
XC4000EX lOB Output Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Recommended Operating Conditions .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Global Buffer Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Horizontal Longline Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . ..
XC4000E Wide Decoder Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E CLB Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E CLB RAM Synchronous (Edge-Triggered) Write Timing ......................
XC4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing ..............
XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines .................
XC4000E CLB Level-Sensitive RAM Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL 1/0) ................
XC4000E lOB Input Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E lOB Output Switching Characteristic Guidelines ............................
XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . ..
Device-Specific PinoutTables ........................................................
Pin Locations for XC4003E Devices ..............................................
Additional XC4003E Package Pins ...............................................
Pin Locations for XC4005E/XL Devices ...........................................
Additional XC4005E/XL Package Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pin Locations for XC4006E Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional XC4006E Package Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pin Locations for XC4008E Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-76
4-76
4-77
4-77
4-78
4-79
4-79
4-80
4-81
4-82
4-82
4-82
4-82
4-83
4-84
4-84
4-85
4-87
4-87
4-88
4-89
4-90
4-90
4-90
4-91
4-91
4-91
4-91
4-92
4-93
4-94
4-95
4-95
4-95
4-95
4-96
4-96
4-97
4-98
4-99
4-102
4-102
4-103
4-104
4-105
4-106
4-108
4-109
4-111
4-111
4-111
4-112
4-113
4·113
4·114
4-115
I
4·3
XC4000E and XC4000X Series Table of Contents
Additional XC4008E Package Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pin Locations for XC401 OE/XL Devices ...........................................
Additional XC401 OE/XL Package Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pin Locations for XC4013E/XL Devices ...........................................
Additional XC4013E/XL Package Pins ............................................
Pin Locations for XC4020E/XL Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional XC4020E/XL Package Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pin Locations for XC4025E, XC4028EXlXL Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional XC4025E, XC4028EX/XL Package Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pin Locations for XC4036EX/XL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional XC4036EXlXL Package Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pin Locations for XC4044XL Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional XC4044XL Package Pins ..............................................
Pin Locations for XC4052XL Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional XC4052XL Package Pins ..............................................
Pin Locations for XC4062XL Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pin Locations for XC4085XL Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional XC4085XL Package Pins ..............................................
Product Availability .................................................................
User 1/0 Per Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ordering Information ................................................................
4-4
4-116
4-116
4-118
4-118
4-120
4-121
4-122
4-123
4-125
4-126
4-129
4-129
4-132
4-133
4-136
4-137
4-141
4-145
4-147
4-149
4-150
XC4000E and XC4000X Series
Field Programmable Gate Arrays
November 10, 1997 (Version 1.4)
Product Specification
XC4000E and XC4000X Series
Features
Low-Voltage Versions Available
Note: XC4000 Series devices described in this data sheet
include the XC4000E family and XC4000X Series.
XC4000X Series devices described in this data sheet
include the XC4000EX and XC4000XL families. This information does not apply to the older Xilinx families: XC4000,
XC4000A, XC4000D, XC4000H, or XC4000L. For information on these devices, see the Xilinx WEBLINX at http://
www.xilinx.com.
•
•
•
•
•
•
•
•
•
System featured Field-Programmable Gate Arrays
- Select-RAMTM memory: on-chip ultra-fast RAM with
- synchronous write option
- dual-port RAM option
Fully PCI compliant (speed grades -2 and faster)
Abundant flip-flops
Flexible function generators
Dedicated high-speed carry logic
- Wide edge decoders on each edge
Hierarchy of interconnect lines
Internal 3-state bus capability
8 global low-skew clock or signal distribution
networks
System Performance beyond 80 MHz
Flexible Array Architecture
Low Power Segmented Routing Architecture
Systems-Oriented Features
IEEE 1149.1-compatible boundary scan logic
support
Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12-mA sink current per XC4000E output
Configured by Loading Binary File
- Unlimited reprogrammability
Readback Capability
- Program verification
- Internal node observability
Backward Compatible with XC4000 Devices
XACTstep Development System runs on most common
computer platforms
- Interfaces to popular design environments
Fully automatic mapping, placement and routing
Interactive design editor for design optimization
November 10, 1997 (Version 1.4)
•
•
Low-Voltage Devices Function at 3.0 - 3.6 Volts
XC4000XL: High Performance Low-Voltage Versions of
XC4000EX devices
Additional XC4000X Series Features
•
•
•
•
•
•
•
•
•
•
•
•
Highest Performance - 3.3 V XC4000XL
Highest Capacity - Over 180,000 Usable Gates
5V tolerant II0s on XC4000XL
0.3511 SRAM process for XC4000XL
Additional Routing Over XC4000E
- almost twice the routing capacity for high-density
designs
Buffered Interconnect for Maximum Speed
New Latch Capability in Configurable Logic Blocks
Improved VersaRing™ 1/0 Interconnect for Better Fixed
Pinout Flexibility
12-mA Sink Current Per XC4000X Output
Flexible New High-Speed Clock Network
- 8 additional Early Buffers for shorter clock delays
- Virtually unlimited number of clock signals
Optional Multiplexer or 2-input Function Generator on
Device Outputs
4 Additional Address Bits in Master Parallel
Configuration Mode
Introduction
XC4000 Series high-performance, high-capacity Field Programmable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs combine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased
speed, abundant routing resources, and new, sophisticated
software to achieve fully automated implementation of
complex, high-density, high-performance designs.
The XC4000E and XC4000X Series currently have 20
members, as shown in Table 2.
Note: All functionality in low-voltage families is the same as
in the corresponding 5-Volt family, except where numerical
references are made to timing or power.
4-5
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 2: XC4000E and XC4000X Series Field Programmable Gate Arrays
Device
XC4003E
XC4005E/XL
XC4006E
XC4008E
XC4010E/XL
XC4013EIXL
XC4020E/XL
XC4025E
XC4028EXlXL
XC4036EXlXL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
Logic
Cells
238
466
608
770
950
1368
1862
2432
2432
3078
3800
4598
5472
7448
Max Logic Max. RAM
Gates
Bits
(No RAM) (No Logic)
3,000
3,200
5,000
6,272
8,192
6,000
8,000
10,368
10,000
12,800
13,000
18,432
20,000
25,088
25,000
32,768
28,000
32,768
36,000
41,472
44,000
51,200
52,000
61,952
62,000
73,728
85,000
100,352
Typical
Gate Range
(Logic and RAM)'
2,000 - 5,000
3,000 - 9,000
4,000 - 12,000
6,000 - 15,000
7,000 - 20,000
10,000 - 30,000
13,000 - 40,000
15,000 - 45,000
18,000 - 50,000
22,000 - 65,000
27,000 - 80,000
33,000 - 100,000
40,000 - 130,000
55,000 - 180,000
CLB
Matrix
10 x 10
14 x 14
16 x 16
18 x 18
20 x20
24x 24
28x28
32 x 32
32x 32
36x 36
40x 40
44x 44
48 x.48
56 x 56
Total
CLBs
100
196
256
324
400
576
784
1,024
1,024
1,296
1,600
1,936
2,304
3,136
Number
of
Max.
Flip-Flops User I/O
360
80
616
112
768
128
936
144
1,120
160
1,536
192
2,016
224
2,560
256
2,560
256
3,168
288
3,840
320
4,576
352
5,376
384
7,168
448
* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
Description
XC4000 Series devices are implemented with a regular,
flexible, programmable architecture of Configurable Logic
Blocks (CLBs), interconnected by a powerful hierarchy of
versatile routing resources, and surrounded by a perimeter
of programmable InpuVOutput Blocks (lOBs). They have
generous routing resources to accommodate the most
complex interconnect patterns.
The devices are customized by loading configuration data
into internal memory cells. The FPGA can either actively
read its configuration data from an external serial or byteparallel PROM (master modes), or the configuration data
can be written into the FPGA from an external device (slave
and peripheral modes).
XC4000 Series FPGAs are supported by powerful and
sophisticated software, covering every aspect of design
from schematic or behavioral entry, floorplanning, simulation, automatic block placement and routing of interconnects, to the creation, downloading, and rea:dback of the
configuration bit stream.
Because Xilinx FPGAs can be reprogrgmmed an unlimited
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hardware must be adapted to different user applications.
4-6
FPGAs are ideal for shortening design and development
cycles, and also offer a cost-effective solution for production rates well beyond 5,000 systems per month. For lowest
high-volume unit cost, a design can first be implemented in
the XC4000E or XC4000X, then migrated to one of Xilinx'
compatible HardWire mask-programmed devices.
Taking Advantage of Reconfiguration
FPGA devices can be reconfigured to change logic function
while resident in the system. This capability gives the system designer a new degree of freedom not available with
any other type of logic.
Hardware can be changed as easily as software. Design
updates or modifications are easy, and can be made to
products already in the field. An FPGA can even be reconfigured dynamically to perform different functions at different times.
Reconfigurable logic can be used to implement system
self-diagnostics, create systems capable of being reconfigured for different environments or operations, or implement
mUlti-purpose hardware for a given application. As an
added benefit, using reconfigurable FPGA devices simplifies hardware design and debugging and shortens product
time-to-market.
November 10, 1997 (Version 1.4)
~XILINX
XC4000E and XC4000X Series
Compared to the XC4000
much as 50% from XC4000 values. See "Fast Carry Logic"
on page 4-18 for more information.
For readers already familiar with the XC4000 family of Xilinx Field Programmable Gate Arrays, the major new features in the XC4000 Series devices are listed in this
section. The biggest advantages of XC4000E and
XC4000X devices are significantly increased system
speed, greater capacity, and new architectural features,
particularly Select-RAM memory. The XC4000X devices
also offer many new routing features, including special
high-speed clock buffers that can be used to capture input
data with minimal delay.
Select-RAM Memory: Edge-Triggered, Synchronous
RAM Modes
Any XC4000E device is pinout- and bitstream-compatible
with the corresponding XC4000 device. An existing
XC4000 bitstream can be used to program an XC4000E
device. However, since the XC4000E includes many new
features, an XC4000E bitstream cannot be loaded into an
XC4000 device.
XC4000X Series devices are not bitstream-compatible with
equivalent array size devices in the XC4000 or XC4000E
families. However, equivalent array size devices, such as
the XC4025, XC4025E, XC4028EX, and XC4028XL, are
pinout-compatible.
Improvements in XC4000E and XC4000X
Increased System Speed
XC4000E and XC4000X devices can run at synchronous
system clock rates of up to 80 MHz, and internal performance can exceed 150 MHz. This inCrease in performance
over the previous families stems from improvements in both
device processing and system architecture.
XC4000
Series devices use a sub-micron multi-layer metal process.
In addition, many architectural improvements have been
made, as described below.
The XC4000XL family is a high performance .3.3V family
based on 0.351l SRAM technology and supports system
speeds to 80 MHz.
PCI Compliance
XC4000 Series -2 and faster speed grades are fully PCI
compliant. XC4000E and XC4000X devices can be used to
implement a one-chip PCI solution.
Carry Logic
The speed of the carry logic chain has increased dramatically. Some parameters, such as the delay on the carry
chain through a single CLB (TBYp), have improved by as
November 10, 1997 (Version 1.4)
The RAM in any CLB can be configured for synchronous,
edge-triggered, write operation. The read operation is not
affected by this change to an edge-triggered write.
Dual-Port RAM
A separate option converts the 16x2 RAM in any CLB into a
16x1 dual-port RAM with simultaneous ReadlWrite.
The function generators in each CLB can be configured as
either level-sensitive (asynchronous) single-port RAM,
edge-triggered (synchronous) single-port RAM, edge-triggered (synchronous) dual-port RAM, or as combinatorial
logic.
Configurable RAM Content
The RAM content can now be loaded at configuration time,
so that the RAM starts up with user-defined data.
H Function Generator
In current XC4000 Series devices, the H function generator
is more versatile than in the original XC4000. Its inputs can
come nOt only from the F and G function generators but
also from up to three of the four control input lines. The H
function generator can thus be totally or partially independent of the other two function generators, increasing the
maximum capacity of the device.
lOB Clock Enable
The two flip-flops in each lOB have a common clock enable
input, which through configuration can be activated individually for the input or output flip-flop or both. This clock
enable operates exactly like the EC pin on the XC4000
CLB. This new feature makes the lOBs more versatile, and
avoids the need for clock gating.
Output Drivers
The output pull-up structure defaults to a TTL-like totempole. This driver is an n-channel pull-up transistor, pulling to
a voltage one transistor threshold below Vcc, just like the
XC4000 family outputs. Alternatively, XC4000 Series
devices can be globally configured with CMOS outputs,
with p-channel pull-up transistors pulling to Vcc. Also, the
configurable pull-up resistor in the XC4000 Series is a pchannel transistor that pulls to Vec, whereas in the original
XC4000 family it is an n-channel transistor that pulls to a
voltage one transistor threshold below Vcc.
4-7
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
Input Thresholds
The input thresholds of 5V devices can be globally configured for either TTL (1.2 V threshold) or CMOS (2.5 V
threshold), just like XC2000 and XC3000 inputs. The two
global adjustments of input threshold and output level are
independent of each other. The XC4000XL family has an
input threshold of 1.6V, compatible with both 3.3V CMOS
and TTL levels.
Additional Improvements in XC4000X Only
Increased Routing
New interconnect in the XC4000X includes twenty-two
additional vertical lines in each column of CLBs and twelve
new horizontal lines in each row of CLBs. The twelve "Quad
Lines" in each CLB row and column include optional repowering buffers for maximum speed. Additional high-performance routing near the lOBs enhances pin flexibility.
Global Signal Access to Logic
There is additional access from global clocks to the F and
G function generator inputs.
Configuration Pin Pull-Up Resistors
During configuration, the three mode pins, MO, M1, and
M2, have weak pull-up resistors. For the most popular configuration mode, Slave Serial, the mode pins can thus be
left unconnected.
The three mode inputs can be individually configured with
or without weak pull-up or pull-down resistors after configuration.
The PROGRAM input pin has a permanent weak pull-up.
Soft Start-up
Like the XC3000A, XC4000 Series devices have "Soft
Start-up." When the configuration process is finished and
the device starts up, the first activation of the outputs is
automatically slew-rate limited. This feature avoids potential ground bounce when all outputs are turned on simultaneously. Immediately after start-up, the slew rate of the
individual outputs is, as in the XC4000 family, determined
by the individual configuration option.
XC4000 and XC4000A Compatibility
Existing XC4000 bitstreams can be used to configure an
XC4000E device. XC4000A bitstreams must be recompiled
for use with the XC4000E due to improved routing
resources, although the devices are pin-for-pin compatible.
4-8
Faster Input and Output
A fast, dedicated early clock sourced by global clock buffers
is available for the lOBs. To ensure synchronization with the
regular global clocks, a Fast Capture iatch driven by the
early clock is available. The input data can be initially
loaded into the Fast Capture latch with the early clock, then
transferred to the input flip-flop or latch with the low-skew
global clock. A programmable delay on the input can be
used to avoid hold-time requirements. See "lOB Input
nals" on page 4-21 for more information.
Latch Capability in CLBs
Storage elements in the XC4000X CLB can be configured
as either flip-flops or latches. This capability makes the
FPGA highly synthesis-compatible.
lOB Output MUX From Output Clock
A multiplexer in the lOB allows the output clock to select
either the output data or the lOB clock enable as the output
to the pad. Thus, two different data signals can share a single output pad, effectively doubling the number of device
outputs without requiring a larger, more expensive package. This multiplexer can also be configured as an ANDgate to implement a very fast pin-to-pin path. See "lOB Output Signals" on page 4-24 for more information.
Additional Address Bits
Larger devices require more bits of configuration data. A
daisy chain of several large XC4000X devices may require
a PROM that cannot be addressed by the eighteen address
bits supported in the XC4000E. The XC4000X Series
therefore extends the addressing in Master Parallel configuration mode to 22 bits.
November 10, 1997 (Version 1.4)
-~------.---------
~XILINX
Detailed Functional Description
XC4000 Series devices achieve high speed through
advanced semiconductor technology and improved architecture. The XC4000E and XC4000X support system clock
rates of up to 80 MHz and internal performance in excess
of 150 MHz. Compared to older Xilinx FPGA families,
XC4000 Series devices are more powerful. They offer onchip edge-triggered and dual-port RAM, clock enables on II
flip-flops, and wide-input decoders. They are more versatile in many applications, especially those involving RAM.
Design cycles are faster due to a combination of increased
routing resources and more sophisticated software.
o
Basic Building Blocks
Xilinx user-programmable gate arrays include two major
configurable elements: configurable logic blocks (CLBs)
and input/output blocks (lOBs).
o
o
CLBs provide the functional elements for constructing
the user's logic.
lOBs provide the interface between the package pins
and internal signal lines.
Three other types of circuits are also available:
o
o
o
3-State buffers (TBUFs) driving horizontallonglines are
associated with each CLB.
Wide edge decoders are available around the periphery
of each device.
An on-chip oscillator is provided.
Programmable interconnect resources provide. routing
paths to connect the inputs and outputs of these configurable elements to the appropriate networks.
The functionality of each circuit block is customized during
configuration by programming internal static memory cells.
The values stored in these memory cells determine the
logic functions and interconnections implemented in the
FPGA. Each of these available circuits is described in this
section.
Configurable Logic Blocks (CLBs)
Configurable Logic Blocks implement most of the .Iogic in
an FPGA. The principal CLB elements are shown in
Figure 2. Two 4-input function generators (F and G) offer
unrestricted versatility. Most combinatorial logic functions
need four or fewer inputs. However, a third function generator (H) is provided. The H function generator has three
inputs. Either zero, one, or two of these inputs can be the
outputs of F and G; the other input(s) are from outside the
CLB. The CLB can, therefore, implement certain functions
of up to nine variables, like parity check or expandableidentity comparison of two sets of four inputs.
Each CLB contains two storage elements that can be used
to store the function generator outputs. However, the storage elements and function generators can also be used
independently. These storage elements can be configured
as flip-flops in both XC4000E and XC4000X devices; in the
XC4000X they can optionally be configured as latches. DIN
can be used as a direct input to either of the two storage
elements. H1 can drive the other through the H function
generator. Function generator outputs can also drive two
outputs independent of the storage element outputs. This
versatility increases logic capacity and simplifies routing.
Thirteen CLB inputs and four CLB outputs provide access
to the function generators and storage elements. These
inputs and outputs connect to the programmable interconnect resources outside the block.
Function Generators
Four independent inputs are provided to each of two function generators (F1 - F4 and G1 - G4). These function generators, with outputs labeled F' and G', are each capable of
implementing any arbitrarily defined Boolean function of
four inputs. The function generators are implemented as
memory look-up tables. The propagation delay is therefore
independent of the function implemented.
A third function generator, labeled H', can implement any
Boolean function of its three inputs. Two of these inputs can
optionally be the F' and G' functional generator outputs.
Alternatively, one or both of these inputs can come from
outside the CLB (H2, HO). The third input must come from
outside the block (H1).
Signals from the function generators can exit the CLB on
two outputs.F' or H' can be connected to the X output. G' or
H' can be connected to the Y output.
A CLB can be used to implement any of the following functions:
o
o
o
o
any function of up to four variables, plus any second
function of up to four unrelated variables, plus any third
function of up to three unrelated variables 1
any single function of five variables
any function of four variables together with some
functions of six variables
some functions of up to nine variables.
Implementing wide functions in a single block reduces both
the number of blocks required and the delay in the signal
path, achieving both increased capacity and speed.
The versatility of the CLB function generators significantly
improves system speed. In addition, the design-software
tools can deal with each function generator independently.
This flexibility improves cell usage.
1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two
unregistered function generator outputs are available from the CLB.
November 10, 1997 (Version . 1.4)
4-9
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
YO
LOGIC
FUNg;ION G ' I - + . . - + - - - I - - - - - - I - + - - 1
G1·G4
LOGIC
FUNCTION
OF
H'
F', G',
AND
H1
LOGIC
FUNg;ION F' I-~~
~--~=t~==========~~----Y
XO
_ _ _ _ _---+
F1-F4
K--------------~-+_--~
(CLOCK)
~-----------------------------X
D
Multiplexer Controlled
by Configuration Program
X6692
Figure 2: Simplified Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown)
Flip-Flops
Clock Enable
The CLB can pass the combinatorial output(s) to the interconnect network, but can also store the combinatorial
results or other incoming data in one or two flip-flops, and
connect their outputs to the interconnect network as well,
The clock enable signal (EC) is active High. The EC pin is
shared by both storage elements. If left unconnected for
either, the clock enable for that storage element defaults to
the active state. EC is not invertible within the CLB.
The two edge-triggered D-type flip-flops have common
clock (K) and clock enable (EC) inputs. Either or both clock
inputs can also be permanently enabled. Storage element
functionality is described in Table 3.
Table 3: CLB Storage Element Functionality
(active rising edge is shown)
Latches (XC4000X only)
The CLB storage elements can also be configured as
latches. The two latches have common clock (K) and clock
enable (EC) inputs. Storage element functionality is
described in Table 3.
Mode
Power-Up or
GSR
Flip-Flop
K
EC
SR
X
X
X
X
SR
X
X
SR
l'
1
A'
X
--.I
D
D
a
X
a'
Q
1
A'
X
X
D
X
Clock Input
Latch
Each flip-flop can be triggered on either the rising or falling
clock edge. The clock pin is shared by both storage elements. However, the clock is individually invertible for each
storage element. Any inverter placed on the clock input is
automatically absorbed into the CLB.
a
l'
l'
Both
X
a
o'
Q
D
Q
Legend.
X
---.l
SR
A·
1•
4-10
a'
Q
D
Don't care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
November 10, 1997 (Version 1.4)
~XILINX
Set/Reset
An asynchronous storage element input (SR) can be configured as either set or reset. This configuration option
determines the state in which each flip-flop becomes operational after configuration. It also determines the effect of a
Global Set/Reset pulse during normal operation, and the
effect of a pulse on the SR pin of the CLB. All three set/
reset functions for any single flip-flop are controlled by the
same configuration data bit.
The set/reset state can be independently specified for each
flip-flop. This input can also be independently disabled for
either flip-flop.
The set/reset state is specified by using the INIT attribute,
or by placing the appropriate set or reset flip-flop library
symbol.
Two fast feed-through paths are available, as shown in
Figure 2. A two-to-one multiplexer on each of the XO and
YO outputs selects between a storage element output and
any of the control inputs. This bypass is sometimes used by
the automated router to repower internal signals.
Control Signals
Multiplexers in the CLB map the four control inputs (C1 - C4
in Figure 2) into the four internal control signals (H1, DIN/
H2, SR/HO, and EG). Any of these inputs can drive any of
the four internal control signals.
When the logic function is enabled, the four inputs are:
•
•
EC - Enable Clock
SR/HO - Asynchronous Set/Reset or H function
generator Input 0
DIN/H2 - Direct In or H function generator Input 2
H1 - H function generator Input 1.
SR is active High. It is not invertible within the CLB.
•
•
Global Set/Reset
When the memory function is enabled, the four inputs are:
A separate Global Set/Reset line (not shown in Figure 2)
sets or clears each storage element during power-up,
reconfiguration, or when a dedicated Reset net is driven
active. This global net (GSR) does not compete with other
routing resources; it uses a dedicated distribution network.
•
•
•
•
Each flip-flop is configured as either globally set or reset in
the same way that the local set/reset (SR) is specified.
Therefore, if a flip-flop is set by SR, it is also set by GSR.
Similarly, a reset flip-flop is reset by both SR and GSR.
Using FPGA Flip-Flops and Latches
STARTUP
PAD >------j
>------1 GSR
GTS
IBUF
02
03
0104
elK DONEIN
X5260
Figure 3: Schematic Symbols for Global Set/Reset
GSR can be driven from any user-programmable pin as a
global reset input. To use this global net, place an input pad
and input buffer in the schematic or HDL code, driving the
GSR pin of the STARTUP symbol. (See Figure 3.) A specific pin location can be assigned to this input using a LOC
attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the
input buffer to invert the sense of the Global Set/Reset signal.
Alternatively, GSR can be driven from any internal node.
Data Inputs and Outputs
The source of a storage element data input is programmable. It is driven by any of the functions F', G', and H', or by
the Direct In (DIN) block input. The flip-flops or latches drive
the XO and YO CLB outputs.
November 10, 1997 (Version 1.4)
EC - Enable Clock
WE - Write Enable
DO - Data Input to F and/or G function generator
D1 - Data input to G function generator (16x1 and
16x2 modes) or 5th Address bit (32x1 mode).
The abundance of flip-flops in the XC4000 Series invites
pipelined designs. This is a powerrul way of increasing performance by breaking the function into smaller subfunctions and executing them in parallel, passing on the results
through pipeline flip-flops. This method should be seriously
considered wherever throughput is more important than
latency.
To include a CLB flip-flop, place the appropriate library
symbol. For example, FDCE is a D-type flip-flop with clock
enable and asynchronous clear. The corresponding latch
symbol (for the XC4000X only) is called LDCE.
In XC4000 Series devices, the flip flops can be used as registers or shift registers without blocking the function generators from performing a different, perhaps unrelated task.
This ability increases the functional capacity of the devices.
The CLB setup time is specified between the function generator inputs and the clock input K. Therefore, the specified
CLB flip-flop setup time includes the delay through the
function generator.
Using Function Generators as RAM
Optional modes for each CLB make the memory look-up
tables in the F' and G' function generators usable as an
array of ReadIWrite memory cells. Available modes are
level-sensitive (similar to the XC4000/A/Hfamilies), edgetriggered, and dual-port edge-triggered. Depending on the
selected mode, a single CLB can be configured as either a
16x2, 32x1, or 16x1 bit array.
4-11
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
Supported CLB memory configurations and timing modes
for single- and dual-port modes are shown in Table 4.
The selected timing mode applies to both function generators within a CLB when both are configured as RAM.
XC4000 Series devices are the first programmable logic
devices with edge-triggered (synchronous) and dual-port
RAM accessible to the user. Edge-triggered RAM simplifies system timing. Dual-port RAM doubles the effective
throughput of FIFO applications. These features can be
individually programmed in any XC4000 Series CLB.
The number of read ports is also programmable:
Advantages of On-Chip and Edge-Triggered RAM
The on-chip RAM is extremely fast. The read access time is
the same as the logic delay. The write access time is
slightly slower. Both access times are much faster than
any off-chip solution, because they avoid liD delays.
Edge-triggered RAM, also called synchronous RAM, is a
feature never before available in a Field Programmable
Gate Array. The simplicity of designing with edge-triggered
RAM, and the markedly higher achievable performance,
add up to a significant improvement over existing devices
with on-chip RAM.
Three application notes are available from Xilinx that discuss edge-triggered RAM: "XC4000E Edge-Triggered and
Dual-Port RAM CapabilitY,' "Implementing FIFOs in
XC4000E RAM;' and "Synchronous and Asynchronous
FIFO Designs:' All three application notes apply to both
XC4000E and XC4000X RAM.
Table 4: Supported RAM Modes
16
x
1
16
32
x
1
EdgeTriggered
Timing
LevelSensitive
Timing
Single-Port
Dual-Port
RAM Configuration Options
The function generators in any CLB can be configured as
RAM arrays in the following sizes:
•
•
Two 16x1 RAMs: two data inputs and two data outputs
with identical or, if preferred, different addressing for
each RAM
One 32x1 RAM: one data input and one data output.
One For G function generator can be configured as a 16x1
RAM while the other function generators are used to implement any function of up to 5 inputs.
Additionally, the XC4000 Series RAM may have either of
two timing modes:
•
•
Edge-Triggered (Synchronous): data written by the
designated edge of the CLB clock. WE acts as a true
clock enable.
Level-Sensitive (Asynchronous): an external WE signal
acts as the write strobe.
4-12
•
•
Single Port: each function generator has a common
read and write port
Dual Port: both function generators are configured
together as a single 16x1 dual-port RAM with one write
port and two read ports. Simultaneous read and write
operations to the same or different addresses are
supported.
RAM configuration options are selected by placing the
appropriate library symbol.
Choosing a RAM Configuration Mode
The appropriate choice of RAM mode for a given design
should be based on timing and resource requirements,
desired functionality, and the simplicity of the design process. Recommended usage is shown in Table 5.
The difference between level-sensitive, edge-triggered,
and dual-port RAM is only in the write operation. Read
operation and timing is identical for all modes of operation.
Table 5: RAM Mode Selection
Use for New
Designs?
Size (16x1,
Registered)
Simultaneous
Read/Write
Relative
Performance
LevelSensitive
EdgeTriggered
Dual-Port
EdgeTriggered
No
Yes
Yes
1/2 CLB
1/2 CLB
1 CLB
No
No
Yes
X
2X
2X(4X
effective)
RAM Inputs and Outputs
The F1-F4 and G 1-G4 inputs to the function generators act
as address lines, selecting a particular memory cell in each
look-up table.
The functionality of the CLB control signals changes when
the function generators are configured as RAM. The DINI
H2, H1, and SRIHO lines become the two data inputs (DO,
01) and the Write Enable (WE) input for the 16x2 memory.
When the 32x1 configuration is selected, 01 acts as the
fifth address bit and DO is the data input.
The contents of the memory cell(s) being addressed are
available at the F' and G' function-generator outputs. They
can exit the CLB through its X and Y outputs, or can be captured in the CLB flip-flop(s).
Configuring the CLB function generators as Read/Write
memory does not affect the functionality of the other por-
November 10, 1997 (Version 1.4)
~XILINX
tions of the CLB, with the exception of the redefinition of the
control signals. In 16x2 and 16x1 modes, the H' function
generator can be used to implement Boolean functions of
F', G', and D1, and the D flip-flops can latch the F', G', H', or
DO signals.
Single-Port Edge-Triggered Mode
Edge-triggered (synchronous) RAM simplifies timing
requirements. XC4000 Series edge-triggered RAM timing
operates like writing to a data register. Data and address
are presented. The register is enabled for writing by a logic
High on the write enable input, WE. Then a rising or falling
clock edge loads the data into the register, as shown in
Figure 4.
WCLK(K)
--------------~I'
nals. An internal write pulse is generated that performs the
write. See Figure 5 and Figure 6 for block diagrams of a
CLB configured as 16x2 and 32x1 edge-triggered, singleport RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port, edge-triggered mode are shown in
Table 5.
The Write Clock input (WCLK) can be configured as active
on either the rising edge (default) or the falling edge. It uses
the same CLB pin (K) used to clock the CLB flip-flops, but it
can be independently inverted. Consequently, the RAM
output can optionally be registered within the same CLB
either by the same clock edge as the RAM, or by the opposite edge of this clock. The sense of WCLK applies to both
function generators in the CLB when both are configured
as RAM.
The WE pin is active-High and is not invertible within the
CLB.
WE _ _-"I
Note: The pulse following the active edge of WCLK (TWPS
in
4) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
pOint in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are configured as edge-triggered RAM.
DATA IN
ADDRESS
Table 6: Single-Port Edge-Triggered RAM Signals
RAM Signal
D
DATA OUT
X6461
Figure 4:
Edge-Triggered RAM Write Timing
Complex timing relationships between address, data, and
write enable signals are not required, and the external write
enable pulse becomes a simple clock enable. The active
edge of WCLK latches the address, input data, and WE sig-
November 10,1997 (Version 1.4)
A[3:0]
A[4]
WE
WCLK
SPO
(Data Out)
CLB Pin
DO or D1 (15x2,
15x1), DO (32x1)
F1-F4 or G1-G4
D1 (32x1)
WE
K
F' or G'
Function
Data In
Address
Address
Write Enable
Clock
Single Port Out
(Data Out)
4-13
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
G'
F'
K
(CLOCK)
----,.-----1
X6752
Figure 5:
16x2 (or 16x1) Edge-Triggered Single-Port RAM
XI-+-.--G'
H'
J-+-~-F'
K-----r-----i
(CLOCK)
X6754
Figure 6: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical)
4-14
November 10, 1997 (Version 1.4)
~XILINX
Dual-Port Edge-Triggered Mode
Table 7: Dual-Port Edge-Triggered RAM Signals
In dual-port mode, both the F and G function generators
are used to create a single 16x1 RAM array with one write
port and two read ports. The resulting RAM array can be
read and written simultaneously at two independent
addresses. Simultaneous read and write operations at the
same address are also supported.
Dual-port mode always has edge-triggered write timing, as
shown in Figure 4.
Figure 7 shows a simple model of an XC4000 Series CLB
configured as dual-port RAM. One address port, labeled
A[3:0], supplies both the read and write address for the F
function generator. This function generator behaves the
same as a 16x1 single-port edge-triggered RAM array. The
RAM output, Single Port Out (SPO), appears at the F function generator output. SPO, therefore, reflects the data at
address A[3:0].
The other address port, labeled DPRA[3:0] for Dual Port
Read Address, supplies the read address for the G function
generator. The write address for the G function generator,
however, comes from the address A[3:0]. The output from
this 16x1 RAM array, Dual Port Out (DPO), appears at the
G function generator output. DPO, therefore, reflects the
data at address DPRA[3:0].
Therefore, by using A[3:0] for the write address and
DPRA[3:0] for the read address, and reading only the DPO
output, a FIFO that can read and write simultaneously is
easily generated. Simultaneous access doubles the effective throughput of the FIFO.
The relationships between CLB pins and RAM inputs and
outputs for dual-port, edge-triggered mode are shown in
Table 7. See Figure 8 on page 4-16 for a block diagram of a
CLB configured in this mode.
RAM16X1D Primitive
- - - - - - - - - - - - -,
~----
OPO (Dual Port Out)
WE~---1-WE
Registered OPO
DPRA[3:0]---;-_+-!_ AR[3:0]
AW[3:0]
RAM Signal
D
A[3:0]
CLB Pin
DO
F1-F4
DPRA[3:0]
WE
WCLK
SPO
G1-G4
WE
K
F'
DPO
G'
Function
Data In
Read Address for F,
Write Address for F and G
Read Address for G
Write Enable
Clock
Single Port Out
(addressed by A[3:0])
Dual Port Out
(addressed by DPRA[3:0])
Note: The pulse following the active edge of WCLK (Twps
in Figure 4) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are configured as edge-triggered RAM.
Single-Port Level-SensitiveTiming Mode
Note: Edge-triggered mode is recommended for all new
designs. Level-sensitive mode, also called asynchronous
mode, is still supported for XC4000 Series backward-compatibility with the XC4000 family.
Level-sensitive RAM timing is simple in concept but can be
complicated in execution. Data and address signals are
presented, then a positive pulse on the write enable pin
(WE) performS a write into the RAM at the designated
address. As indicated by the "level-sensitive" label, this
RAM acts like a latch. During the WE High pulse, changing
the data lines results in new data written to the old address.
Changing the address lines while WE is High results in spurious data written to the new address-and possibly at
other addresses as well, as the address lines inevitably do
not all change simultaneously.
The user must generate a carefully timed WE signal. The
delay on the WE signal and the address lines must be carefully verified to ensure that WE does not become active
until after the address lines have settled, and that WE goes
inactive before the address lines change again. The data
must be stable before and after the falling edge of WE.
~---- SPO (Single Port Out)
WE
Registered
spa
A[3:01-i--+---+-lAR[3:0]
AW[3:0]
WCLK---~------"
Figure 7: XC4000 Series Dual-Port RAM, Simple
Model
November 10, 1997 (Version 1.4)
In practical terms, WE is usually generated by a 2X clock. If
a 2X clock is not available, the falling edge of the system
clock can be used. However, there are inherent risks in this
approach, since the WE pulse must be guaranteed inactive
before the next rising edge of the system clock. Several
older application notes are available from Xilinx that discuss the design of level-sensitive RAMs. These application
notes include XAPP031, "Using the XC4000 RAM CapabilitY,' and XAPP042, "High-Speed RAM Design in XC4000:'
However, the edge-triggered RAM available in the XC4000
Series is superior to level-sensitive RAM for almost every
application.
4-15
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
I~+---G'
I~+---F"
K~~--_~---l
(CLOCK)
X6748
Figure 8: 16x1 Edge-Triggered Dual-Port RAM
Figure 9 shows the write timing for level-sensitive, singleport RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port level-sensitive mode are shown in
Table 8.
Figure 10 and Figure 11 show block diagrams of a CLB
configured as 16x2 and 32x1 level-sensitive, single-port
RAM.
Initializing RAM at Configuration
Both RAM and ROM implementations of the XC4000
Series devices are initialized during configuration. The initial contents are defined via an INIT attribute or property
4-16
attached to the RAM or ROM symbol, as described in the
schematic library guide. If not defined, all RAM contents
are initialized to all zeros, by default.
RAM initialization occurs only during configuration. The
RAM content is not affected by Global Set/Reset.
Table 8: Single-Port Level-Sensitive RAM Signals
RAM Signal
D
A[3:0]
WE
0
CLB Pin
DO or D1
F1-F4 or G1-G4
WE
F' or G'
Function
Data In
Address
Write Enable
Data Out
November 10, 1997 (Version 1.4)
~XILINX
TWC
X64S2
Figure 9: Level-Sensitive RAM Write Timing
q
~
0
EC
DO
DIN
Enable
WRITE
DECODER
4
16-LATCH
ARRAY
I
...........
MUX r-
~ G'
10116
I
READ ADDRESS
DIN
Enable
16-LATCH
ARRAY
WRITE
DECODER
4
--1
4
...........
MUX ~
~ F'
10116
1
X6746
4
--1
READ ADDRESS
Figure 10: 16x2 (or 16x1) Level-Sensitive Single-Port RAM
November 10,1997 (Version 1.4)
4-17
XC4000E and XC4000X Series Field Programmable Gate Arrays
6 Q 6 ~
WE
D1/A4
Do
I
t==n
Enable
~
WRITE
DECODER
4
DIN
I'---
16-LATCH
ARRAY
MUX
1 of 16
l--f
4
READ ADDRESS
I
=f).
~
WRITE
DECODER
4
16-LATCH
ARRAY
Dl~e-
D+
---.......
DIN
Enable
G'
UX
H'
~[YF'
1 of 16
I
l-J
4
READ ADDRESS
X6749
Figure 11: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical)
Fast Carry Logic
Each CLB F and G function generator contains dedicated
arithmetic logic for the fast generation of carry and borrow
signals. This extra output is passed on to the function generator in the adjacent CLB. The carry chain is independent
of normal routing resources.
Dedicated fast carry logic greatly increases the efficiency
and performance of adders, subtractors, accumulators,
comparators and counters. It also opens the door to many
new applications involving arithmetic operation, where the
previous generations of FPGAs were not fast enough or too
inefficient. High-speed address offset calculations in microprocessor or graphics systems, and high-speed addition in
digital signal processing are two typical applications.
The two 4-input function generators can be configured as a
2-bit adder with built-in hidden carry that can be expanded
to any length. This dedicated carry circuitry is so fast and
efficient that conventional speed-up methods like carry
generate/propagate are meaningless even at the 16-bit
level, and of marginal benefit at the 32-bit level.
This fast carry logic is one of the more significant features
of the XC4000 Series, speeding up arithmetic and counting
into the 70 MHz range.
4-18
The carry chain in XC4000E devices can run either up or
down. At the top and bottom of the columns where there
are no CLBs above or below, the carry is propagated to the
right. (See Figure 12.) In order to improve speed in the
high-capacity XC4000X devices, which can potentially
have very long carry chains, the carry chain travels upward
only, as shown in Figure 13. Additionally, standard interconnect can be used to route a carry signal in the downward
direction.
Figure 14 on page 4-20 shows an XC4000E CLB with dedicated fast carry logic. The carry logic in the XC4000X is
similar, except that COUT exits at the top only, and the signal CINDOWN does not exist. As shown in Figure 14, the
carry logic shares operand and control inputs with the function generators. The carry outputs connect to the function
generators, where they are combined with the operands to
form the sums.
Figure 15 on page 4-21 shows the details of the carry logic
for the XC4000E. This diagram shows the contents of the
box labeled "CARRY LOGIC" in Figure 14. The XC4000X
carry logic is very similar, but a multiplexer on the passthrough carry chain has been eliminated to reduce delay.
Additionally, in the XC4000X the multiplexer on the G4 path
has a memory-programmable 0 input, which permits G4 to
November 10, 1997 (Version 1.4)
~XILINX
directly connect to COUT. G4 thus becomes an additional
high-speed initialization path for carry-in.
The dedicated carry logic is discussed in detail in Xilinx
document XAPP 013: "Using the Dedicated Carry Logic in
XC4000." This discussion also applies to XC4000E
devices, and to XC4000X devices when the minor logic
changes are taken into account.
The fast carry logic can be accessed by placing special
library symbols, or by using Xilinx Relationally Placed Macros (RPMs) that already include these symbols.
~H~
j
CLB
d
~
j
CLB
CLB
EJ 8 EJ B
B:B:B:B
CLB
-::..
CLB
:
CLB
f:,.
-:: .• CLB
-::.
CLB
:.:
CLB
.~:,:..
CLB
::,'..
CLB
0 :0 :0 : 0
u lLJ l·u LLJ
.i'.i'.i'.i
Q
Q. Q ';'.LB
~ ~ ~ ~
Figure 13: Available XC4000X Carry Propagation
Paths (dotted lines use general interconnect)
CLB
B--8 EJ
CLB
X6687
Figure 12: Available XC4000E Carry Propagation
Paths
November 10, 1997 (Version 1.4)
4-19
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
CARRY
LOGIC
~---------Y
G4--~~-+----t---
G3--~~------t---
G
DIN
G2--~~------t---
SIR
Q
YQ
Q
XQ
G1--~-+------t---
EC
H
H1--~~------~---
DIN
SIR
EC
F4~~~~----+----
F3~-+-+-+----~~
F
F1~~--~----~--
I----------X
COUT
¢I
K
SIR
I
EC
X6699
Figure 14: Fast Carry Logic in XC4000E CLB (shaded area not present in XC4000X)
4-20
November 10, 1997 (Version 1.4)
~XILINX
C OUT
G1-----j
G2
G4----~----+_----~------~
G3
COUTO
TO
FUNCTION
GENERATORS
F2------t-i
F1----,~----t_---__i
F4
I
F3-----~----~~--------4
~
X2000
CI~UP
I
CIN DOWN
Figure 15: Detail of XC4000E Dedicated Carry Logic
Input/Output Blocks (lOBs)
User-configurable input/output blocks (lOBs) provide the
interface between external package pins and the internal
logic. Each lOB controls one package pin and can be configured for input, output, or bidirectional signals.
Figure 16 shows a simplified block diagram of the
XC4000E lOB. A more complete diagram which includes
the boundary scan logic of the XC4000E lOB can be found
in Figure 41 ofl page 4-44, in the "Boundary Scan" section.
The XC4000X lOB contains some special features not
included in the XC4000E lOB. These features are highlighted in a simplified block diagram found in Figure 17, and
discussed throughout this section. When XC4000X special
features are discussed, they are clearly identified in the
text. Any feature not so identified is present in both
XC4000E and XC4000X devices.
lOB Input Signals
Two paths, labeled 11 and 12 in Figure 16 and Figure 17,
bring input signals into the array. Inputs also connect to an
input register that can be programmed as either an edgetriggered flip-flop or a level-sensitive latch.
November 10, 1997 (Version 1.4)
The choice is made by placing the appropriate library symbol. For example, IFD is the basic input flip-flop (rising edge
triggered), and ILD is the basic input latch (transparentHigh). Variations with inverted clocks are available, and
some combinations of latches and flip-flops can be implemented in a single lOB, as described in the XACT Libraries
Guide.
The XC4000E inputs can be globally configured for either
TTL (1.2V) or 5.0 volt CMOS thresholds, using an option in
the bitstream generation software. There is a slight input
hysteresis of about 300mV. The XC4000E output levels are
also configurable; the two global adjustments of input
threshold and output level are independent.
Inputs on the XC4000XL are TTL compatible and 3.3V
CMOS compatible. Outputs on the XC4000XL are pulled to
the 3.3V positive supply.
The inputs of XC4000 Series 5-Volt devices can be driven
by the outputs of any 3.3-Volt device, if the 5-Volt inputs are
in TTL mode.
Supported sources for XC4000 Series device inputs are
shown in Table 9.
4-21
XC4000E and XC4000X Series Field Programmable Gate Arrays
\-
~
- - - -
- - -- - -- -
- - - - -- - -- -
--
- - -- - - -
-- - ---
- -
-- - -
- - -
--
~
I
T-i-4---j
Out -i----+---j
Output
Buffer
Output -;----+---1
Clock
Input
Buffer
Clock -+--------+--jCE
Enable
<
Input -+--*"---1
Clock
X6704
Figure 16: Simplified Block Diagram of XC4000E lOB
Out
Output Clock ---.--+----*---j
Clock Enable - - - ; - - * - - - - - - - - - - +....--1
Input Clock ---.-----_*---j
,
_ _ _ _ .J
X5984
Figure 17: Simplified Block Diagram of XC4000X lOB (shaded areas indicate differences from XC4000E)
4-22
November 10, 1997 (Version 1.4)
~XILINX
Table 9: Supported Sources for XC4000 Series Device
Inputs
XC4000ElEX XC4000XL
Series Inputs Series Inputs
5V,
3.3V
5V,
TTL CMOS
CMOS
Source
Any device, Vcc = 3.3 V,
CMOS outputs
XC4000 Series, Vcc = 5 V,
TTL outputs
Any device, Vee = 5 V,
TTL outputs (Voh S; 3.7 V)
Any device, Vcc = 5 V,
CMOS outputs
..J
..J
Unreli
-able
Data
..J
The input flip-flop setup time is defined between the data
measured at the device 110 pin and the clock input at the
lOB (not at the clock pin). Any routing delay from the device
clock pin to the clock input of the lOB must, therefore, be
subtracted from this setup time to arrive at the real setup
time requirement relative to the device pins. A short specified setup time might, therefore, result in a negative setup
time at the device pins, i.e., a positive hold-time requirement.
..J
..J
..J
..J
..J
..J
XC4000XL 5-VoltTolerant II0s
The •lIDs on the XC4000XL are fully 5-volt tolerant even
though the Vcc is 3.3 volts. This allows 5 V signals to
directly connect to the XC4000XL inputs without damage,
as shown in Table 9. In addition, the 3.3 volt Vcc can be
applied before or after 5 volt signals are applied to the lIDs.
This makes the XC4000XL immune to power supply
sequencing problems.
Registered Inputs
The 11 and 12sigrials that exit the block can each carry
eitherthe direct oNegistered input signal.
The input and output storage elements in each lOB hav~ a
common clock enable input, which, through configuration,
can bEi;;lctivated individually for the input or output flip-flop,
or both. This clock enable operates exactly like'the EC pin
on the XC4000 Series CLB. It cannot be inverted within the
lOB.
The storage element behavior is shown in Table 10.
Table 10: Input Register Functionality
(active rising edge is shown)
Mode
Clock
Power-Up or
GSR
Flip-FlOp
X
Latch
Both
legend:
X
_F
SR
0*
1*
Clock
Enable
X
D
Q
X
SR
l'
X
l'
l'
0
D
X
X
D
X
D
.....J
0
1
0
X
,
Don't care
Rising edge
Set or Reset value. Reset is default.
Input is low or unconnected (default value)
Input is High or unconnected (default value)
November 10,1997 (Version,1.4)
Optional Delay Guarantees Zero Hold Time
The data input to the register can optionally be delayed by
several nanoseconds. With the delay enabled, the setup
time of the input flip-flop is increased so that normal clock
routing does not result in a positive hold-time requirement.
A positive hold time requirement can lead to unreliable,
temperature- cir processing-dependent operation.
Q
Q
D
Q
When a delay is inserted on the data line, more clock delay
can be tolerated without causing a positive hold-time
requirement. SuffiCient delay elimiriatesthe possibility of a
data hold-time requirement at the external pin. The maximum delay is therefore inserted as the default.
Tile XC4000E lOB has a one-tap delay element: either the
delay is inserted (default), or it is not. The delay guarantees
a Zero h61dtime with respect to clocks routed through any
of the XC4000E global clock buffers. (Se~"Global Nets and
Buffers (XC4000E only)" on page 4-36 for a description of
the global clock buffers in the XC4000E.) For a shorter
input register setup time, with non-zero hold, attach ,a
NODELAY attribute or property to the, flip-flop.
The XC4000X lOB has ,a, two-tap delay element,. with
choices of a full delay, a partial delay, ,or no. delay. 11]e
attributes or properties used to select the desired delay are
shown, in Table 11. The choices ,are ho added, attribute,
MEDDELAY, and NODELAy. The default setting, with no
added attribute, ensures no hold time with respect to any of
the XC4000X clock buffers,including the Global Low-Skew
buffers. MEDDELAY ensures no hold time with respect to
the Global Early buffers. Inputs with NOD,ELAY may have a
positive hold time with respect to all clock buffers. For a
description of each of these buffers, see "Global Nets and
Buffers (XC4000X only)" on page 4-38.
Table 11: XC4000X lOB Input Delay Element
Value
full delay
(default, no
attribute added)
MEDDELAY
NODELAY
When to Use
Zero Holdwith respect to Global LowSkew Buffer, Global Early Buffer
Zero Hold with respect to Global Early
Buffer
Short Setup, positive Hold time
4-23
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
Additional Input Latch for Fast Capture (XC4000X only)
The XC4000X lOB has an additional optional latch on the
input. This latch, as shown in Figure 17, is clocked by the
output clock - the clock used for the output flip-flop rather than the input clock. Therefore, two different clocks
can be used to clock the two input storage elements. This
additional latch allows the very fast capture of input data,
which is then synchronized to the internal clock by the lOB
flip-flop or latch.
To use this Fast Capture technique, drive the output clock
pin (the Fast Capture latching signal) from the output of one
of the Global Early buffers supplied in the XC4000X. The
second storage element should be clocked by a Global
Low-Skew buffer, to synchronize the incoming data to the
internal logic. (See Figure 18.) These special buffers are
described in "Global Nets and Buffers (XC4000X only)" on
page 4-38.
The Fast Capture latch (FCL) is designed primarily for use
with a Global Early buffer. For Fast Capture, a single clock
signal is routed through both a Global Early buffer and a
Global Low-Skew buffer. (The two buffers share an input
pad.) The Fast Capture latch is clocked by the Global Early
buffer, and the standard lOB flip-flop or latch is clocked by
the Global Low-Skew buffer. This mode is the safest way to
use the Fast Capture latch, because the clock buffers on
both storage elements are driven by the same pad. There is
no external skew between clock pads to create potential
problems.
To place the Fast Capture latch in a design, use one of the
special library symbols, ILFFX or ILFLX. ILFFX is a transparent-Low Fast Capture latch followed by an active-High
input flip-flop. ILFLX is a transparent-Low Fast Capture
latch followed by a transparent-High input latch. Any of the
clock inputs can be inverted before driving the library element, and the inverter is absorbed into the lOB. If a single
BUFG output is used to drive both clock inputs, the software automatically runs the clock through both a Global
Low-Skew buffer and a Global Early buffer, and clocks the
Fast Capture latch appropriately.
17 on page 4-22 also shows a two-tap delay on the
input. By default, if the Fast Capture latch is used, the Xilinx
software assumes a Global Early buffer is driving the clock,
and selects MEDDELAY to ensure a zero hold time. Select
the desired delay based on the discussion in the previous
subsection.
lOB Output Signals
Output signals can be optionally inverted within the lOB,
and can pass directly to the pad or be stored in an edgetriggered flip-flop. The functionality of this flip-flop is shown
in Table 12.
An active-High 3-state signal can be used to place the output buffer in a high-impedance state, implementing 3-state
outputs or bidirectional 1/0. Under configuration control, the
output (OUT) and output 3-state (T) signals can be
inverted. The polarity of these signals is independently configured for each lOB.
The 4-mA maximum output current speCification of many
FPGAs often forces the user to add external buffers, which
are especially cumbersome on bidirectional 1/0 lines. The
XC4000E and XC4000EXlXL devices solve many of these
problems by providing a guaranteed output sink current of
12 mA. Two adjacent outputs can be interconnected externally to sink up to 24 mA. The XC4000E and XC4000EXlXL
FPGAs can thus directly drive buses on a printed circuit
board.
By default, the output pull-up structure is configured as a
TTL-like totem-pole. The High driver is an n-channel pull-up
transistor, pulling to a voltage one transistor threshold
below Vcc. Alternatively, the outputs can be globally configured as CMOS drivers, with p-channel pull-up transistors
pulling to Vcc. This option, applied using the bitstream generation software, applies to all outputs on the device. It is
not individually programmable. In the XC4000XL, all outputs are pulled to the positive supply rail.
Table 12: Output Flip-Flop Functionality (active rising
edge is shown)
Mode
Power-Up
orGSR
Clock
Clock
Enable
T
D
X
X
O'
X
Q
SR
X
Flip-Flop
.-I
0
l'
X
X
X
0
ILFFX
X
Q
0
1
X
X
0
Z
O'
Q
Legend:
X
IPAD>----- D
0'
O'
Q
to internal
logic
__F
SR
O·
l'
Z
Don't care
Rising edge
Set or Reset value. Reset is defaull.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
3-stale
BUFGLS
X9013
Figure 18: Examples USing XC4000X FCL
4-24
November 10, 1997 (Version 1.4)
~XILINX
Any XC4000 Series 5-Volt device with its outputs configured in TTL mode can drive the inputs of any typical 3.3Volt device. (For a detailed discussion of how to interface
between 5 V and 3.3 V devices, see the 3V Products section of The Programmable Logic Data Book.)
Supported destinations for XC4000 Series device outputs
are shown in Table 13.
An output can be configured as open-drain (open-collector)
by placing an OBUFT symbol in a schematic or HDL code,
then tying the 3-state pin (T) to the output signal, and the
input pin (I) to Ground. (See Figure 19.)
Table 13: Supported Destinations for XC4000 Series
Outputs
XC4000 Series
Outputs
Destination
3.3 V,
5V,
5V,
CMOS
TTL
CMOS
Any typical device, Vcc = 3.3 V,
CMOS-threshold inputs
..j
..j
some
Any device, Vcc =5 V,
TTL-threshold inputs
..j
..j
..j
Any device, Vcc =5 V,
CMOS-threshold inputs
Unreliable
Data
..j
1. Only if destination device has 5-V tolerant inputs
~--~~
HBUFT
X6702
Figure 19: Open-Drain Output
Output Slew Rate
The slew rate of each output buffer is, by default, reduced,
to minimize power bus transients when switching non-critical signals. For critical signals, attach a FAST attribute or
property to the output buffer or flip-flop.
For XC4000E devices, maximum total capacitive load for
simultaneous fast mode switching in the same direction is
200 pF for all package pins between each Power/Ground
November 10, 1997 (Version 1.4)
pin pair. For XC4000X devices, additional internal Power/
Ground pin pairs are connected to special Power and
Ground planes within the packages, to reduce ground
bounce. Therefore, the maximum total capacitive load is
300 pF between each external Power/Ground pin pair.
Maximum loading may vary for the low-voltage devices.
For slew-rate limited outputs this total is two times larger for
each device type: 400 pF for XC4000E devices and 600 pF
for XC4000X devices. This maximum capacitive load
should not be exceeded, as it can result in ground bounce
of greater than 1.5 V amplitude and more than 5 ns duration. This level of ground bounce may cause undesired
transient behavior on an output, or in the internal logic. This
restriction is common to all high-speed digital ICs, and is
not particular to Xilinx or the XC4000 Series.
XC4000 Series devices have a feature called "Soft Startup," designed to reduce ground bounce when all outputs
are turned on simultaneously at the end of configuration.
When the configuration process is finished and the device
starts up, the first activation of the outputs is automatically
slew-rate limited. Immediately following the initial activation
of the I/O, the slew rate of the individual outputs is determined by the individual configuration option for each lOB .
Global Three-State
A separate Global 3-State line (not shown in Figure 16 or
Figure 17) forces all FPGA outputs to the high-impedance
state, unless boundary scan is enabled and is executing an
EXTEST instruction. This global net (GTS) does not compete with other routing resources; it uses a dedicated distribution network.
GTS can be driven from any user-programmable pin as a
global 3-state input. To use this global net, place an input
pad and input buffer in the schematic or HDL code, driving
the GTS pin of the STARTUP symbol. A specific pin location can be assigned to this input using a LOC attribute or
property, just as with any other user-programmable pad. An
inverter can optionally be inserted after the input buffer to
invert the sense of the Global 3-State signal. Using GTS is
similar to GSR. See Figure 3 on page 4-1 i for details.
Alternatively, GTS can be driven from any internal node.
4-25
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
Other lOB Options
Output Multiplexer/2-lnput Function Generator
(XC4000X only)
As shown in Figure 17 on page 4-22, the output path in the
XC4000X lOB contains an additional multiplexer not available in the XC4000E lOB. The multiplexer can also be configured as a 2-input function generator, implementing a
pass-gate, AND-gate, OR-gate, or XOR-gate, with 0, 1, or 2
inverted inputs. The logic used to implement these functions is shown in the upper gray area of Figure 17.
When configured as a multiplexer, this feature allows two
output signals to time-share the same output pad; effectively doubling the number of device outputs without requiring a larger, more expensive package.
When the MUX is configured as a 2-input function generator, logic can be implemented within the lOB itself. Combined with a Global Early buffer, this arrangement allows
very high-speed gating of a single signal. For example, a
wide decoder can be implemented in CLBs, and its output
gated with a Read or Write Strobe Driven by a BUFGE
buffer, as shown in Figure 20. The critical-path pin-to-pin
delay of this circUit is less than 6 nanoseconds.
As shown in Figure 17, the lOB input pins Out, Output
Clock, and Clock Enable have different delays and different
flexibilities regarding polarity. Additionally, Output Clock
sources are more limited than the other inputs. Therefore,
the Xilinx software does not move logic into the lOB function generators unless explicitly directed to do so.
The user can specify that the lOB function generator be
used, by placing special library symbols beginning with the
letter "0." For example, a 2-input AND-gate in the lOB function generator is called OAND2. Use the symbol input pin
labelled "F" for the signal on the critical path. This signal is
placed on the OK pin - the lOB input with the shortest
delay to the function generator. Two examples are shown in
21.
There are a number of other programmable options in the
XC4000 Series lOB.
Pull-up and Pull-down Resistors
Programmable pull-up and pull-down resistors are useful
for tying unused pins to Vcc or Ground to. minimize power
consumption and reduce noise sensitivity. The configurable
pull-up resistor is a p-channel transistor that pulls to Vcc.
The configurable pull-down resistor is an n-channel transistor that pulls to Ground.
The value of these resistors is 50 kQ - 100 kn. This high
value makes them unsuitable as wired-AND pull-up resistors.
The pull-up resistors for most user-programmable lOBs are
active during the configuration process. See Table 23 on
page 4-59 for a list of pins with pull-ups active before and
during configuration.
After configuration, voltage levels of unused pads, bonded
or unbonded, must be valid logic levels, to reduce noise
sensitivity and avoid excess current. Therefore, by default,
unused pads are configured with the internal pull-up resistor active. Alternatively, they can be individually configured
with the pull-down resistor, or as a driven output, or to be
driven by an external source. To activate the internal pullup, attach the PULLUP library component to the net
attached to the pad. To activate the internal pull-down,
attach the PULLDOWN library component to the net
attached to the pad.
Independent Clocks
Separate clock signals are provided for the input and output
flip-flops. The clock can be independently inverted for each
flip-flop within the lOB, generating either falling-edge or rising-edge triggered. flip-flops. The clock inputs for each lOB
are independent, except that in the XC4000X, the Fast
Capture latch shares an lOB input with the output clock pin.
Early Clock for lOBs (XC4000X only)
internal
logic
OAND2
X9019
Figure 20: Fast Pin-to-Pin Path in XC4000X
=0OAND2
X£598
DO [520
01
~
Figure 21: AND & MUX Symbols in XC4000X lOB
4-26
Special early clocks are available for lOBs. These clocks
are sourced by the same sources as the Global Low-Skew
buffers, but are separately buffered. They have fewer loads
and therefore less delay. The early clock can drive either
the lOB output clock or the lOB input clock, or both. The
early clock allows fast capture of input data, and fast clockto-output on output data. The Global Early buffers that drive
these clocks are described in "Global Nets and Buffers
(XC4000X only)" on page 4-38.
Global Set/Reset
As with the CLB registers, the Global SeVReset signal
(GSR) can be used to set or clear the input and output registers, depending on the value of the INIT attribute or property. The two flip-flops can be individually configured to set
November 10, 1997 (Version 1.4)
~--~-
..
- - - - -
---~
---
- ----
--------~~~
..
---
~XILlNX
or clear on reset and after configuration. Other than the global GSR net, no user-controlled set/reset signal is available
to the 1/0 flip-flops. The choice of set or clear applies to
both the initial state of the flip-flop and the response to the
Global Set/Reset pulse. See "Global Set/Reset" on page 411 for a description of how to use GSA.
Standard 3-State Buffer
All three pins are used. Place the library element BUFT.
Connect the input to the I pin and the output to the 0 pin.
The T pin is an active-High 3-state (Le. an active-Low
enable). Tie the T pin to Ground to implement a standard
buffer.
JTAG Support
Wired-AND with Input on the I Pin
Embedded logic attached to the lOBs contains test structures compatible with IEEE Standard 1149.1 for boundary
scan testing, permitting easy chip and board-level testing.
More information is provided in "Boundary Scan" on
page 4-43.
The buffer can be used as a Wired-AND. Use the WAND1
library symbol, which is essentially an open-drain buffer.
WAND4, WANDS, and WAND16 are also available. See the
XACT Libraries Guide for further information.
Three-State Buffers
The T pin is internally tied to the I pin. Connect the input to
the I pin and the output to the 0 pin. Connect the outputs of
all the WAND1s together and attach a PULLUP symbol.
A pair of 3-state buffers is associated with each CLB in the
array. (See Figure 28 on page 4-31.) These 3-state buffers
can be used to drive signals onto the nearest horizontal
long lines above and below the CLB. They can therefore be
used to implement multiplexed or bidirectional buses on the
horizontal longlines, saving logic resources. Programmable
pull-up resistors attached to these longlines help to implement a wide wired-AND function.
The buffer enable is an active-High 3-state (Le. an activeLow enable), as shown in Table 14.
Another 3-state buffer with similar access is located near
each 1/0 block along the right and left edges of the array.
(See
34 on page 4-35.)
The horizontal long lines driven by the 3-state buffers have
a weak keeper at each end. This circuit prevents undefined
floating levels. However, it is overridden by any driver, even
a pull-up resistor.
Special longlines running along the perimeter of the array
can be used to wire-AND signals coming from nearby lOBs
or from internal longlines. These long lines form the wide
Decoders" on
edge decoders discussed in "Wide
page 4-28.
Wired OR-AND
The buffer can be configured as a Wired OR-AND. A High
level on either input turns off the output. Use the
WOR2AND library symbol, which is essentially an opendrain 2-input OR gate. The two input pins are functionally
equivalent. Attach the two inputs to the 10 and 11 pins and
tie the output to the 0 pin. Tie the outputs of all the
WOR2ANDs together and attach a PULLUP symbol.
Three-State Buffer Examples
22 shows how to use the 3-state buffers to implement a wired-AND function. When all the buffer inputs are
High, the pull-up resistor(s) provide the High output.
23 shows how to use the 3-state buffers to implement a multiplexer. The selection is accomplished by the
buffer 3-state signal.
Pay particular attention to the polarity of the T pin when
using these buffers in a design. Active-High 3-state (T) is
identical to an active-Low output enable, as shown in
Table 14.
Table 14: Three-State Buffer Functionality
Three-State Buffer Modes
IN
The 3-state buffers can be configured in three modes:
x
•
•
•
IN
Standard 3-state buffer
Wired-AND with input on the Ipin
Wired OR-AND
WOR2AND
T
OUT
o
IN
z
WOR2ANO
Figure 22: Open-Drain Buffers Implement a Wired-AND Function
November 10, 1997 (Version 1.4)
4-27
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
,--_._---------_._ .... _-----_ .... _---- ... .
.__ ... _-_ ... _--_ ....... _------_._-----_ ... .
"Weak Keeper"
Figure 23: 3-State Buffers Implement a Multiplexer
Wide Edge Decoders
Dedicated decoder circuitry boosts the performance of
wide decoding functions. When the address or data field is
wider than the function generator inputs, FPGAs need
mUlti-level decoding and are thus slower than PALs.
XC4000 Series CLBs have nine inputs. Any decoder of up
to nine inputs is, therefore, compact and fast. However,
there is also a need for much wider decoders, especially for
address decoding in large microprocessor systems.
An XC4000 Series FPGA has four programmable decoders
located on each edge of the device. The inputs to each
decoder are any of the lOB 11 signals on that edge plus one
local interconnect per CLB row or column. Each row or column of CLBs provides up to three variables or their compliments., as shown in Figure 24. Each decoder generates a
High output (resistor pull-up) when the AND condition of
the selected inputs, or their complements, is true. This is
analogous to a product term in typical PAL devices.
Each of these wired-AND gates is capable of accepting up
to 42 inputs on the XC4005E and 72 on the XC4013E.
There are up to 96 inputs for each decoder on the
XC4028X and 132 on the XC4052X. The decoders may
also be split in two when a larger number of narrower
decoders are required, for a maximum of 32 decoders per
device.
The decoder outputs can drive CLB inputs, so they can be
combined with other logic to form a PAL-like AND/OR structure. The decoder outputs can also be routed directly to the
chip outputs. For fastest speed, the output should be on the
same chip edge as the decoder. Very large PALs can be
emulated by ORing the decoder outputs in a CLB. This
decoding feature covers what has long been considered a
weakness of older FPGAs. Users often resorted to external
PALs for simple but fast decoding functions. Now, the dedicated decoders in the XC4000 Series device can implement these functions fast and efficiently.
To use the wide edge decoders, place one or more of the
WAND library symbols (WAND1, WAND4, WAND8,
WAND16). Attach a DECODE attribute or property to each
WAND symbol. Tie the outputs together and attach a PUL-
4-28
LUP symbol. Location attributes or properties such as L
(left edge) orTR (right half of top edge) should also be used
to ensure the correct placement of the decoder inputs.
INTERCONNECT
C) .... .
--.-t---t-+---+---+----.-t------<;--+----+--.-----+-t------<;--+---+---+---
(A·B·
C) .... .
(A· B· C) .... .
(A.B. C) .... .
X2627
Figure 24: XC4000 Series Edge Decoding Example
OSC4
F8M
F500K
F16K
F490
F15
X6703
Figure 25: XC4000 Series Oscillator Symbol
On-Chip Oscillator
XC4000 Series devices include an internal oscillator. This
oscillator is used to clock the power-on time-out, for configuration memory clearing, and as the source of CCLK in
Master configuration modes. The oscillator runs at a nominal 8 MHz frequency that varies with process, Vcc, and
temperature. The output frequency falls between 4 and 10
MHz.
November 10, 1997 (Version 1.4)
~XILINX
The oscillator output is optionally available after configuration. Any two of four resynchronized taps of a built-in divider
are also available. These taps are at the fourth, ninth, fourteenth and nineteenth bits of the divider. Therefore, if the
primary oscillator output is running at the nominal 8 MHz,
the user has access to an 8 MHz clock, plus any two of 500
kHz, 16kHz, 490Hz and 15Hz (up to 10% lower for low-voltage devices). These frequencies can vary by as much as 50% or +25%.
These signals can be accessed by placing the OSC4
library element in a schematic or in HDL code (see
Figure 25).
The oscillator is automatically disabled after configuration if
the OSC4 symbol is not used in the design.
•
Global routing consists of dedicated networks primarily
designed to distribute clocks throughout the device with
minimum delay and skew. Global routing can also be
used for other high-fanout signals.
Five interconnect types are distinguished by the relative
length of their segments: single-length lines, double-length
lines, quad and octal lines (XC4000X only), and longlines.
In the XC4000X, direct connects allow fast data flow
between adjacent CLBs, and between lOBs and CLBs.
Extra routing is included in the lOB pad ring. The XC4000X
also includes a ring of octal interconnect lines near the
lOBs to improve pin-swapping and routing to locked pins.
Programmable Interconnect
XC4000ElX devices include two types of global buffers.
These global buffers have different properties, and are
intended for different purposes. They are discussed in
detail later in this section.
All internal connections are composed of metal segments
with programmable switching points and switching matrices
to implement the desired routing. A structured, hierarchical
matrix of routing resources is provided to achieve efficient
automated routing.
A high-level diagram of the routing resources associated
with one CLB is shown in Figure 26. The shaded arrows
represent routing present only in XC4000X devices.
The XC4000E and XC4000X share a basic interconnect
structure. XC4000X devices, however, have additional routing not available in the XC4000E. The extra routing
resources allow high utilization in high-capacity devices. All
XC4000X-specific routing resources are clearly identified
throughout this section. Any resources not identified as
XC4000X-specific are present in all XC4000 Series
devices.
This section describes the varied routing resources available in XC4000 Series devices. The implementation software automatically assigns the appropriate resources
based on the density and timing requirements of the
design.
Interconnect Overview
There are several types of interconnect.
•
•
CLB routing is associated with each row and column of
the CLB array.
lOB routing forms a ring (called a VersaRing) around
the outside of the CLB array. It connects the I/O with the
internal logic blocks.
November 10, 1997 (VersiontA)
CLB Routing Connections
Table 15 shows how much routing of each type is available
in XC4000E and XC4000X CLB arrays. Clearly, very large
designs, or designs with a great deal of interconnect, will
route more easily in the XC4000X .. Smaller XC4000E
designs, typically requiring significantly less interconnect,
do not require the additional routing.
28 on page 4-31 is a detailed diagram of both the
XC4000E and the XC4000X CLB, with associated routing.
The shaded square is the programmable switch matrix,
present in both the XC4000E and the XC4000X. The lshaped shaded area is present only in XC4000X devices.
As shown in the figure, the XC4000X block is essentially an
XC4000E block with additional routing.
CLB inputs and outputs are distributed on all four sides,
providing maximum routing flexibility. In general, the entire
architecture is symmetrical and regular. It is well suited to
established placement~nd routing algorithms. Inputs, outputs, and function generators can freely swap positions
within a CLB to avoid routing congestion during the placement and routing operation.
4-29
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
~II"II"~IIIIII"~
Quad
Single
Double
Long
Direct
Connect
Long
Quad
Long
Global
Clock
Long
Double Single
Global
Clock
Carry Direct
Chain Connect
x5994
Figure 26: High-Level Routing Diagram of XC4000 Series CLB (shaded arrows indicate XC4000X only)
Table 15: Routing per CLB in XC4000 Series Devices
XC4000E
XC4000X
Vertical Horizontal Vertical
Singles
Doubles
Quads
Longlines
Direct
Connects
Globals
Carry Logic
Total
8
4
0
8
4
0
6
6
0
4
2
24
Horizontal
8
4
12
0
8
4
12
10
2
0
0
18
8
1
45
0
0
32
6
,,,-
Double
Singles
2
j
Double
Six Pass Transistors
Per Switch Matrix
Interconnect Point
X6600
Figure 27: Programmable Switch Matrix (PSM)
Programmable Switch Matrices
Single-Length Lines
The horizontal and vertical single- and double-length lines
intersect at a box called a programmable switch matrix
(PSM). Each switch matrix consists of programmable pass
transistors used to establish connections between the lines
(see Figure 27).
Single-length lines provide the greatest interconnect flexibility and offer fast routing between adjacent blocks. There
are eight vertical and eight horizontal single-length lines
associated with each CLB. These lines connect the switching matrices that are located in every row and a column of
CLBs.
For example, a single-length signal entering on the right
side of the switch matrix can be routed to a single-length
line on the top, left, or bottom sides, or any combination
thereof, if multiple branches are required. Similarly, a double-length signal can be routed to a double-length line on
any or all of the other three edges of the programmable
switch matrix.
4-30
Single-length lines are connected by way of the programmable switch matrices, as shown in Figure 29. Routing
connectivity is shown in Figure 28.
Single-length lines incur a delay whenever they go through
a switching matrix. Therefore, they are not suitable for routing signals for long distances. They are normally used to
conduct signals within a localized area and to provide the
branching for nets with fanout greater than one.
November 10, 1997 (Version 1.4)
- - -
---~--~-.-
..
~-------
~XILINX
DOUBLE
I
}"'GCE
DOUBLE
LONG
D
Common to XC4000E and XC4000X
D
XC4000X only
•
Programmable Switch Matrix
Figure 28: Detail of Programmable Interconnect .Associated with XC4000 Series CLB
November 10,1997 (Version 1:4)
4-31
XC4000E and XC4000X Series Field Programmable Gate Arrays
Doubles
ICLB I
ICLBI
ICLB I
ICLBI
ICLB I
ICLBI
Singles
Doubles
Figure 29: Single- and Double-Length Lines, with
Programmable Switch Matrices (PSMs)
Double-Length Lines
The double-length lines consist of a grid of metal segments,
each twice as long as the single-length lines: they run past
two CLBs before entering a switch matrix. Double-length
lines are grouped in pairs with the switch matrices staggered, so that each line goes through a switch matrix at
every other row or column of CLBs (see Figure 29).
There are four vertical and four horizontal double-length
lines associated with each CLB. These lines provide faster
signal routing over intermediate distances, while retaining
routing flexibility. Double-length lines are connected by way
of the programmable switch matrices. Routing connectivity
is shown in Figure 28.
Quad Lines (XC4000X only)
XC4000X devices also include twelve vertical and twelve
horizontal quad lines per CLB row and column. Quad lines
are four times as long as the single-length lines. They are
interconnected via buffered switch matrices (shown as diamonds in Figure 28 on page 4-31). Quad lines run past four
CLBs before entering a buffered switch matrix. They are
grouped in fours, with the buffered switch matrices staggered, so that each line goes through a buffered switch
matrix at every fourth CLB location in that row or column.
(See Figure 30.)
The buffered switch matrixes have four pins, one on each
edge. All of the pins are bidirectional. Any pin can drive any
or all of the other pins.
Each buffered switch matrix contains one buffer and six
pass transistors. It resembles the programmable switch
matrix shown in Figure 27, with the addition of a programmable buffer. There can be up to two independent inputs
4-32
X9014
Figure 30: Quad Lines (XC4000X only)
and up to two independent outputs. Only one of the independent inputs can be buffered.
The place and route software automatically uses the timing
requirements of the design to determine whether or not a
quad line signal should be buffered. A heavily loaded signal
is typically buffered, while a lightly loaded one is not. One
scenario is to alternate buffers and pass transistors. This
allows both vertical and horizontal quad lines to be buffered
at alternating buffered switch matrices.
Due to the buffered switch matrices, quad lines are very
fast. They provide the fastest available method of routing
heavily loaded signals for long distances across the device.
Longlines
Longlines form a grid of metal interconnect segments that
run the entire length or width of the array. Longlines are
intended for high fan-out, timeccritical signal nets, or nets
that are distributed over long distances. In XC4000X
devices, quad lines are preferred for critical nets, because
the buffered switch matrices make them faster for high fanout nets.
Two horizontal longlines per CLB can be driven by 3-state
or open-drain drivers (TBUFs). They can therefore implement unidirectional or bidirectional buses, wide multiplexers, or wired-AND functions. (See "Three-State Buffers" on
page 4-27 for more details.)
Each horizontal longline driven by TBUFs has either two
(XC4000E) or eight (XC4000X) pull-up resistors. To activate these resistors, attach a PULLUP symbol to the longline net. The software automatically activates the appropriate number of pull-ups. There is also a weak keeper at
each end of these two horizontal longlines. This circuit pre-
November 10, 1997 (Version 1.4)
--
~
~---
~~
- - -
~XILINX
vents undefined floating levels. However, it is overridden by
any driver, even a pull-up resistor.
Each XC4000E longline has a programmable splitter switch
at its center, as does each XC4000X long line driven by
TBUFs. This switch can separate the line into two independent routing channels, each running half the width or height
of the array.
Each XC4000X long line not driven by TBUFs has a buffered programmable splitter switch at the 1/4, 1/2, and 3/4
points of the array. Due to the buffering, XC4000X longline
performance does not deteriorate with the larger array
sizes. If the longline is split, the resulting partial longlines
are independent.
Routing connectivity of the longlines is shown in Figure 28
on page 4-31 .
Direct Interconnect (XC4000X only)
The XC4000X offers two direct, efficient and fast connections between adjacent CLBs. These nets facilitate a data
flow from the left to the right side of the device, or from the
top to the bottom, as shown in Figure 31. Signals routed on
the direct interconnect exhibit minimum interconnect propagation delay and use no general routing resources.
The direct interconnect is also present between CLBs and
adjacent lOBs. Each lOB on the left and top device edges
has a direct path to the nearest CLB. Each CLB on the right
and bottom edges of the array has a direct path to the nearest two lOBs, since there are two lOBs for each row or column of CLBs.
The place and route software uses direct interconnect
whenever possible, to maximize routing resources and minimize interconnect delays.
1/0 Routing
XC4000 Series devices have additional routing around the
lOB ring. This routing is called a VersaRing. The VersaRing
facilitates pin-swapping and redesign without affecting
board layout. Included are eight double-length lines spanning two CLBs (four lOBs), and four long lines. Global lines
and Wide Edge Decoder lines are provided. XC4000X
devices also include eight octal lines.
A high-level diagram of the VersaRing is shown in
32. The shaded arrows represent routing present
only in XC4000X devices.
Figure 34 on page 4-35 is a detailed diagram of the
XC4000E and XC4000X Versa Ring. The area shown
includes two lOBs. There are two lOBs per CLB row or column, therefore this diagram corresponds to the CLB routing
diagram shown in Figure 28 on page 4-31. The shaded
areas represent routing and routing connections present
only in XC4000X devices.
Octal 110 Routing (XC4000X only)
Between the XC4000X CLB array and the pad ring, eight
interconnect tracks provide for versatility in pin assignment
and fixed pinout flexibility. (See Figure 33 on page 4-34.)
These routing tracks are called octals, because they can be
broken every eight CLBs (sixteen lOBs) by a programmable buffer that also functions as a splitter switch. The buffers
are staggered, so each line goes through a buffer at every
eighth CLB location around the device edge.
The octal lines bend around the corners of the device. The
lines cross at the corners in such a way that the segment
most recently buffered before the turn has the farthest distance to travel before the next buffer, as shown in
Figure 33.
Figure 31: XC4000X Direct Interconnect
November 10,1997 (Version 1.4)
4-33
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
. . . . . . Quad
Single
Double
Long
• • • • • • Direct
Connect
Long
Direct
Connect
Edge Double Long Global Octal
Decode
Clock
X5995
Figure 32: High-Level Routing Diagram of XC4000 Series VersaRing (Left Edge)
WED Wide Edge Decoder, lOB 110 Block (shaded arrows indicate XC4000X only)
=
=
:~
,~
•••
lOB
lOB
Segment with nearest buffer
connects to segment with furthest buffer
I
~
•
•
•
•
•
•
X9015
Figure 33: XC4000X Octal 110 Routing
4-34
November 10, 1997 (Version 1.4)
~XILINX
rUAD
T
0
DOUBLE
}INGLE
~ I
DOUBLE
LONG
A
R
R
A
y
DIRECT
LONG
o
Common to XC4000E and XC4000X
•
XC4000X only
Figure 34: Detail of Programmable Interconnect Associated with XC4000 Series lOB (Left Edge)
November 10,1997 (Version 1.4)
4-35
XC4000E and XC4000X Series Field Programmable Gate Arrays
lOB inputs and outputs interface with the octal lines via the
single-length interconnect lines. Single-length lines are
also used for communication between the octals and double-length lines, quads, and longlines within the CLB array.
Two different types of clock buffers are available in the
XC4000E:
Segmentation into buffered octals was found to be optimal
for distributing signals over long distances around the
device.
Four Primary Global buffers offer the shortest delay and
negligible skew. Four Secondary Global buffers have
slightly longer delay and slightly more skew due to potentially heavier loading, but offer greater flexibility when used
to drive non-clock CLB inputs.
Global Nets and Buffers
Both the XC4000E and the XC4000X have dedicated global networks. These networks are designed to distribute
clocks and other high fanout control signals throughout the
devices with minimal skew. The global buffers are
described in detail in the following sections. The text
descriptions and diagrams are summarized in Table 16.
The table shows which CLB and lOB clock pins can be
sourced by which global buffers.
In both XC4000E and XC4000X devices, placement of a
library symbol called BUFG results in the software choosing the appropriate clock buffer, based on the timing
requirements of the design. The detailed information in
these sections is included only for reference.
Global Nets and Buffers (XC4000E only)
Four vertical longlines in each CLB column are driven
exclusively by special global buffers. These longlines are
in addition to the vertical longlines used for standard interconnect. The four global lines can be driven by either of two
types of global buffers. The clock pins of every CLB and
lOB can also be sourced from local interconnect.
•
•
Primary Global Buffers (BUFGP)
Secondary Global Buffers (BUFGS)
The Primary Global buffers must be driven by the semidedicated pads. The Secondary Global buffers can be
sourced by either semi-dedicated pads or internal nets.
Each CLB column has four dedicated vertical Global lines.
Each of these lines can be accessed by one particular Primary Global buffer, or by any of the Secondary Global buffers, as shown in Figure 35. Each corner of the device has
one Primary buffer and one Secondary buffer.
lOBs along the left and right edges have four vertical global
longlines. Top and bottom lOBs can be clocked from the
global lines in the adjacent CLB column.
A global buffer should be specified for all timing-sensitive
global signal distribution. To use a global buffer, place a
BUFGP (primary buffer), BUFGS (secondary buffer), or
BUFG (either primary or secondary buffer) element in a
schematic or in HDL code. If desired, attach a LOC
attribute or property to direct placement to the designated
location. For example, attach a LOC=L attribute or property
to a BUFGS symbol to direct that a buffer be placed in one
of the two Secondary Global buffers on the left edge of the
device, or a LOC=BL to indicate the Secondary Global
buffer on the bottom edge of the device, on the left.
Table 16: Clock Pin Access
BUFGP
L
BUFGS
BUFGLS
L&R
T&B
BUFGE
BUFGE
Local
Interconnect
=Left, R =Right, T =Top, B =Bottom
4-36
November 10, 1997 (Version 1.4)
~XILINX
lOB
lOB
lOB
lOB
BUFGS
BUFGP
~
PGCK4
lOB
lOB
1
Any BUFGS {
Any BUFGS
One BUFGP
One BUFGP
per Global Line
lOB
lOB
SGCK3
PGCK2
SGCK2
D--+-
--- - - - -
_ _ _ -_ _ _
To User
Logic
IBUF
BSCAN
' ) - -.....---1 TOI
TDO
')------1 TMS
DRCK
">------1 TCK
From {
User Logic
IDLE
TD01
SEl1
TD02
SEL2
To User
Logic
X2675
Figure 44: Boundary Scan Schematic Example
Configuration
Configuration is the process of loading design-specific programming data into one or more FPGAs to define the functional operation of the internal blocks and their
interconnections. This is somewhat like loading the command registers of a programmable peripheral chip. XC4000
Series devices use several hundred bits of configuration
data per CLB and its associated interconnects. Each configuration bit defines the state of a static memory cell that
controls either a function look-up table bit, a multiplexer
input, or an interconnect pass transistor. The XACTstep
development system translates the design into a netlist file.
It automatically partitions, places and routes the logic and
generates the configuration data in PROM format.
Special Purpose Pins
Three configuration mode pins (M2, M1, MO) are sampled
prior to configuration to determine the configuration mode.
After configuration, these pins can be used as auxiliary
connections. M2 and MO can be used as inputs, and M1
can be used as an output. The XACTstep development system does not use these resources unless they are explicitly
specified in the design entry. This is done by placing a special pad symbol called MD2, MD1, or MDO instead of the
input or output pad symbol.
In XC4000 Series devices, the mode pins have weak pullup resistors during configuration. With all three mode pins
High, Slave Serial mode is selected, which is the most popular configuration mode. Therefore, for the most common
configuration mode, the mode pins can be left unconnected. (Note, however, that the internal pull-up resistor
value can be as high as 100 kQ.) After configuration, these
pins can individually have weak pull-up or pull-down resistors, as specified in the design. Apull-down resistor value
of 4.7 kO is recommended.
These pins are located in the lower left chip corner and are
near the readback nets. This .location allows convenient
routing if compatibility with the XC2000 and XC3000 family
conventions of MO/RT, M1/RD is desired.
November 10, 1997 (Version 1.4)
~XILINX
Configuration Modes
Additional Address lines in XC4000 devices
XC4000E devices have six configuration modes. XC4000X
devices have the same six modes, plus an additional configuration mode. These modes are selected by a 3-bit input
code applied to the M2, M1, and MO inputs. There are three
self-loading Master modes, two Peripheral modes, and a
Serial Slave mode, which is used primarily for daisychained devices. The coding for mode selection is shown in
Table 9.
The XC4000X devices have additional address lines (A 18A21) allowing the additional address space required to
daisy-chain several large devices.
Table 19: Configuration Modes
Mode
Master Serial
Slave Serial
Master
Parallel Up
M2
M1
MO
0
1
1
0
1
0
1
0
0
CCLK
output
input
output
Master
Parallel Down
1
1
0
output
Peripheral
Synchronous'
Peripheral
Asynchronous
Reserved
Reserved
0
1
1
input
Data
Bit-Serial
Bit-Serial
Byte-Wide,
increment
from 00000
Byte-Wide,
decrement
from 3FFFF
Byte-Wide
1
0
1
output
Byte-Wide
0
0
1
0
0
1
Note:
•
-
-
Peripheral Synchronous can be considered bytewide Slave Parallel
A detailed description of each configuration mode, with timing information, is included later in this data sheet. During
configuration,some of the 110 pins are used temporarily for
the configuration process. All pins used during configuration are shown in Table 23 on page 4-59.
Master Modes
The three Master modes use an internal oscillator to generate a Configuration Clock (CCLK) for driving potential slave
devices. They also generate address and timing for external PROM(s) containing the configuration data.
Master Parallel (Up or Down) modes generate the CCLK
signal and PROM addresses and receive byte paraliel data.
The data is internally serialized into the FPGA data-frame
format. The up and down selection generates starting
addresses at either zero or 3FFFF (3FFFFF when 22
address lines are used), for compatibility with different
microprocessor addressing conventions. The Master Serial
mode generates CCLK and receives the configuration data
in serial form from a Xilinx serial-configuration PROM.
CCLK speed is selectable as either 1 MHz (default) or 8
MHz. Configuration always starts at the default slow frequency, then can switch to the higher frequency during the
first frame. Frequency tolerance is -50% to +25%.
November 10,1997 (Version 1.4)
The extra address lines are programmable in XC4000EX
devices. By default these address lines are not activated. In
the default mode, the devices are compatible with existing
XC4000 and XC4000E products. If desired, the extra
address lines can be used by specifying the address lines
option in bitgen as 22 (bitgen -g AddressLines:22). The
lines (A18-A21) are driven when a master device detects,
via the bitstream, that it should be using all 22 address
lines. Because these pins will initially be pulled high by
internal pull-ups, designers using Master Parallel Up mode
should use external pull down resistors on pins A 18-A21. If
Master Parallel Down mode is used external resistors are
not necessary.
All 22 address lines are always active in Master Parallel
modes with XC4000XL devices. The additional address
lines behave identically to the lower order address iines. If
the Address Lines option in bitgen is set to 18, it will be
ignored by the XC4000XL device.
The additional address lines (A 18-A21) are not available in
the PC84 package.
Peripheral Modes
The two Peripheral modes accept byte-wide data from a
bus. A RDY/BUSY status is available as a handshake sighal. In Asynchronous Peripheral mode, the internal oscillator generates a CCLK burst signal that serializes the bytewide data. CCLK can also drive slave devices. In the synchronous mode, an externally supplied clock input to CCLK
serializes the data.
Slave Serial Mode
In Slave Serial mode, the FPGA receives serial configuration data on the rising edge. of CCLK and, after loading its
configuration, passes additional data out, resynchronized
on the next falling edge ofCCLK.
Multiple slave devices with identical configurations can be
wired with parallel DIN inputs. In this way, multiple devices
can be configured simultaneously.
Serial Daisy Chain
Multiple devices with different configurations can be connected together in a "daisy chain," and a single combined
bitstream used.to configure the chain of slave devices.
To configure a daisy chain of devices, wire the CCLK pins
of all devices in parallel, as shown in Figure 52 on page
4-61. Connect the DOUT of each device to the DIN of the
next. The lead or master FPGA and following slaves each
passes resynchronized configuration data coming from a
single source. The header data, including the length count,
4-47
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
is passed through and is captured by each FPGA when it
recognizes the 0010 preamble. Following the length-count
data, each FPGA outputs a High on DOUT until it has
received its required number of data frames.
After an FPGA has received its configuration data, it
passes on any additional frame start bits and configuration
data on DOUT. When the total number of configuration
clocks applied after memory initialization equals the value
of the 24-bit length count, the FPGAs begin the start-up
sequence and become operational together. FPGA If0 are
normally released two CCLK cycles after the last configuration bit is received. Figure 48 on page 4-54 shows the startup timing for an XC4000 Series device.
The daisy-chained bitstream is not simply a concatenation
of the individual bitstreams. The PROM file formatter must
be used to combine the bitstreams for a daisy-chained configuration.
Multi-Family Daisy Chain
All Xilinx FPGAs of the XC2000, XC3000, and XC4000
Series use a compatible bitstream format and can, therefore, be connected in a daisy chain in an arbitrary
sequence. There is, however, one limitation. The lead
device must belong to the highest family in the chain. If the
chain contains XC4000 Series devices, the master normally cannot be an XC2000 or XC3000 device.
The reason for this rule is shown in Figure 48 on page 4-54.
Since all devices in the chain store the same length count
value and generate or receive one common sequence of
CCLK pulses, they all recognize length-count match on the
same CCLK edge, as indicated on the left edge of
48. The master device then generates additional
CCLK pulses until it reaches its finish point F. The different
families generate or require different numbers of additional
CCLK pulses until they reach F. Not reaching F means that
the device does not really finish its configuration, although
DONE may have gone High, the outputs became active,
and the internal reset was released. For the XC4000 Series
device, not reaching F means that readback cannot be in i-
4-48
tiated and most boundary scan instructions cannot be
used.
The user has some control over the relative timing of these
events and can, therefore, make sure that they occur at the
proper time and the finish point F is reached. Timing is controlled using options in the bitstream generation software.
XC3000 Master with an XC4000 Series Slave
Some designers want to use an inexpensive lead device in
peripheral mode and have the more precious If0 pins of the
XC4000 Series devices all available for user IfO. Figure 45
provides a solution for that case.
This solution requires one CLB, one lOB and pin, and an
internal oscillator with a frequency of up to 5 MHz as a
clock source. The XC3000 master device must be configured with late Internal Reset, which is the default option.
One CLB and one lOB in the lead XC3000-family device
are used to generate the additional CCLK pulse required by
the XC4000 Series devices. When the lead device removes
the internal RESET signal, the 2-bit shift register responds
to its clock input and generates an active Low output signal
for the duration of the subsequent clock period. An external
connection between this output and CCLK thus creates the
extra CCLK pulse.
Output
' - - - ' - - - Connected
to CCLK
Reset
o
0
6
1
0
~
o
1
Active Low Output
Active High Output
etc
X5223
Figure 45: CCLK Generation for XC3000 Master
Driving an XC4000 Series Slave
November 10, 1997 (Version 1.4)
~XILINX
Setting CCLK Frequency
Data Stream Format
For Master modes, CCLK can be generated in either of two
frequencies. In the default slow mode, the frequency
ranges from 0.5 MHz to 1.25 MHz for XC4000E and
XC4000EX devices and from 0.6 MHz to 1.8 MHz for
XC4000XL devices. In fast CCLK mode, the frequency
ranges from 4 MHz to 10 MHz for XC4000EX devices and
from 5 MHz to 15 MHz for XC4000XL devices. The frequency is selected by an option when running the bitstream
generation software. If an XC4000 Series Master is driving
an XC3000- or XC2000-family slave, slow CCLK mode
must be used. In addition, an XC4000XL device driving a
XC4000E or XC4000EX should use slow mode. Slow mode
is the default.
The data stream ("bitstream") format is identical for all configuration modes.
Table 20: XC4000 Series Data Stream Formats
All Other
Modes (DO ... )
11111111b
0010b
COUNT(23:0)
1iiib
Data Type
Fill Byte
Preamble Code
Length Count
Fill Bits
Start Field
Data Frame
CAC or Constant
Field Check
Extend Write Cycle
p;ost~~bl~:':
Ob
DATA(n'1:0)
)(xxx (CAe)
or 0110b
.><,.:,
Start-Up Bytes
O:t11111~~,
xxh
LEGEND:
Unshaded
Once per bitstream
Light
Once per data frame
November 10, 1997 (Version 1.4)
:~;,.:.
.......
The data stream formats are shown in Table 20. Bit-serial
data is read from left to right, and byte-parallel data is effectively assembled from this serial bitstream, with the first bit
in each byte assigned to DO.
The configuration data stream begins with a string of eight
ones, a preamble code, followed by a 24-bit length count
and a separator field of ones. This header is followed by the
actual configuration data in frames. The length and number
of frames depends on the device type (see Table 21 and
Table 22). Each frame begins with a start field and ends
with an error check. A postamble code is required to signal
the end of data for a single device. In all cases, additional
start-up bytes of data are required to provide four clocks for
the startup sequence at the end of configuration. Long
daisy chains require additional startup bytes to shift the last
data through the chain. All startup bytes are don't-cares;
these bytes are not included in bitstreams created by the
Xilinx software.
A selection of CAC or non-CAC error checking is allowed
by the bitstream generation software. The non-CRC error
checking tests for a designated end-of-frame field for each
frame. For CRC error checking, the software calculates a
running CRC and inserts a unique four-bit partial check at
the end of each frame. The ii-bit CRC check of the last
frame of an FPGA includes the last seven data bits.
Detection of an error results in the suspension of data loading and the pulling down of the INIT pin. In Master modes,
CCLK and address signals continue to operate externally.
The user must detect TNTf and initialize a new configuration
by pulsing the PROGRAM pin Low or cycling Vcc.
4-49
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 21: XC4000E Program Data
Device
Max Logic Gates
CLBs
(Row x Col.)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
3,000
5,000
6,000
8,000
10,000
13,000
20,000
25,000
100
(10 x 10)
196
(14x14)
256
(16 x 16)
324
(18 x 18)
400
(20 x 20)
576
(24 x 24)
784
(28 x 28)
1,024
(32 x 32)
lOBs
Flip-Flops
80
112
128
144
160
192
224
256
360
616
768
936
1,120
1,536
2,016
2,560
Bits per Frame
126
166
186
206
226
266
306
346
Frames
Program Data
428
572
644
716
788
932
1,076
1,220
53,936
94,960
119,792
147,504
178,096
247,920
329,264
422,128
53,984
95,008
119,840
147,552
178,144
247,968
329,312
422,176
PROM Size
(bits)
Notes:
-
1. Bits per Frame = (lOx number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits
Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40 (header) + 8
2. The user can add more "one" bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of
any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra "one"
bits, even for extra leading ones at the beginning of the header.
Table 22: XC4000EXlXL Program Data
Device
Max Logic Gates
CLBs
(Row x Column)
lOBs
Flip-Flops
XC4005 XC4010 XC4013 XC4020 XC4028 XC4036 XC4044
5,000
10,000 13,000 20,000 28,000 36,000
44,000
196
400
576
784
1,024
1,600
1,296
(14x14) (20 x 20) (24 x 24) (28 x 28) (32 x32) (36 x36) (40 x 40)
112
160
192
224
256
288
320
616
1,120
1,536
2,016
2,560
3,168
3,840
XC4052
XC4062
XC4085
52,000
62,000
85,000
1,936
(44 x 44)
2,304
(48 x 48)
3,136
(56 x 56)
352
384
448
4,576
5,376
7,168
Bits per Frame
205
277
325
373
421
469
517
565
613
709
Frames
741
1,023
1,211
1,399
1,587
1,775
1,963
2,151
2,339
2,715
Program Data
PROM Size (bits)
Notes:
151,910 283,376 393,580 521,832 668,132 832,480 1,014,876 1,215,320 1,433,812 1,924,940
151,960 283,424 393,632 521,880 668,184 832,528 1,014,928 1,215,368 1,433,864 1,924,992
1. Bits per frame = (12 x number of rows) + 8 for the top + 16 for the bottom + 8 + 1 start bit + 4 error check bits.
Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4.
Program data = (bits per frame x number of frames) + 5 postamble bits.
PROM size = (program data + 40 header bits + 8 start bits) rounded up to the nearest byte.
2. The user can add more "one" bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of
any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra "one" bits,
even for extra leading "ones" at the beginning of the header.t
Cyclic Redundancy Check (CRC) for
Configuration and Readback
performs an identical calculation on the bitstream and compares the result with the received checksum.
The Cyclic Redundancy Check is a method of error detection in data transmission applications. Generally, the transmitting system performs a calculation on the serial
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits. The receiving system
Each data frame of the configuration bitstream has four
error bits at the end, as shown in Table 20. If a frame data
error is detected during the loading of the FPGA, the configuration process with a potentially corrupted bitstream is
terminated. The FPGA pulls the INIT pin Low and goes into
a Wait state.
4-50
November 10, 1997 (Version 1.4)
~XILINX
During Readback, 11 bits of the 16-bit checksum are added
to the end of the Readback data stream. The checksum is
computed using the CRC-16 CCITT polynomial, as shown
in Figure 46. The checksum consists of the 11 most significant bits of the 16-bit code. A change inthe checksum indicates a change in the Readback bitstream. A comparison
to a previous checksum is meaningful only if the readback
data is independent of the current device state. CLB outputs should not be included (Read Capture option not
used), and if RAM is present, the RAM content must be
unchanged.
Boundary Scan
Instructions
Available:
Yes
Statistically, one error out of 2048 might go undetected.
Configuration Sequence
There are four major steps in the XC4000 Series power-up
configuration sequence.
•
•
•
EXTEsr
SAMPLE/PRELOAD
BYPASS
CONFIGURE"
(" if PROGRAM =High)
-1.3)lS per Frame
Configuration Memory Clear
Initialization
Configuration
Start-Up
I
Master Waits 50 to 250 ~s
Before Sampling Mode Lines
The full process is illustrated in Figure 47.
Configuration Memory Clear
When power is first applied or is reapplied to an FPGA, an
internal circuit forces initialization of the configuration logic.
When Vcc reaches an operational level, and the circuit
passes the write and read test of a sample pair of configuration bits, a time delay is started. This time delay is nominally 16 ms, and up to 10% longer in the low-voltage
devices. The delay is four times as long when in Master
Modes (MO Low), to allow ample time for all slaves to reach
a stable Vcc. When all INIT pins are tied together, as recommended, the longest delay takes precedence. Therefore, devices with different time delays can easily be mixed
and matched in a daisy chain.
:c
"
'5
~
g
:c
_f
PulllNIT Low
and Stop
No
SAMPLE/PRELOAD
BYPASS
Config·
uration
memory
Full
"
'5
g
19
No
Yesj~~--------,
This delay is applied only on power-up. It is not applied
when reconfiguring an FPGA by pulsing the PROGRAM pin
CCLK
Count Equals
Length
Count
2 3 4 5 6 7 8 9 10 1112 13 14
>N--'-O_ _--'
I
Polynomial: X16 + X15 + X2 + 1
:
I
r- - --- ------- ---------------1
I
t
···1 11·1
LAST DATA FRAME
CRG - CHECKSUM------
Readback Data Stream
X1789
EXTEST
SAMPLE PRELOAD
BYPASS
USER, '.1
USER 2
CONFIGURE
READBACK
}
Operalional
If Boundary Scan
is Selected
Figure 46: Circuit for Generating CRC.16
X6076
Figure 47: Power-up Configuration Sequence
November 10, 1997 (Version 1.4)
4-51
XC4000E and XC4000X Series Field Programmable Gate Arrays
Low. During this time delay, or as long as the PROGRAM
input is asserted, the configuration logic is held in a Configuration Memory Clear state. The configuration-memory
frames are consecutively initialized, using the internal oscillator.
At the end of each complete pass through the frame
addressing, the power-on time-out delay circuitry and the
level of the PROGRAM pin are tested. If neither is asserted,
the logic initiates one additional clearing of the configuration frames and then tests the INIT input.
Initialization
During initialization and configuration, user pins HDC, LDC,
INIT and DONE provide status outputs for the system interface. The outputs LDC, INIT and DONE are held Low and
HDC is held High starting at the initial application of power.
The open drain INIT pin is released after the final initialization pass through the frame addresses. There is a deliberate delay of 50 to 250 Ils (up to 10% longer for low-voltage
devices) before a Master-mode device recognizes an inactive INIT. Two internal clocks after the INIT pin is recognized
as High, the FPGA samples the three mode lines to determine the configuration mode. The appropriate interface
lines become active and the configuration preamble and
data can be loaded. Configuration
The 0010 preamble code indicates that the following 24 bits
represent the length count. The length count is the total
number of configuration clocks needed to load the complete configuration data. (Four additional configuration
clocks are required to complete the configuration process,
as discussed below.) After the preamble and the length
count have been passed through to all devices in the daisy
chain, DOUT is held High to prevent frame start bits from
reaching any daisy-chained devices.
A specific configuration bit, early in the first frame of a master device, controls the configuration-clock rate and can
increase it by a factor of eight. Therefore, if a fast configuration clock is selected by the bitstream, the slower clock
rate is used until this configuration bit is detected.
Each frame has a start field followed by the frame-configuration data bits and a frame error field. If a frame data error
is detected, the FPGA halts loading, and signals the error
by pulling the open-drain INIT pin Low. After all configuration frames have been loaded into an FPGA, DOUT again
follows the input data so that the remaining data is passed
on to the next device.
Delaying Configuration After Power-Up
There are two methods of delaying configuration after
power-up: put a logic Low on the PROGRAM input, or pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See Figure 47 on page 4-51.)
rise time is excessive or poorly defined. As long as PROGRAM is Low, the FPGA keeps clearing its configuration
memory. When PROGRAM goes High, the configuration
memory is cleared one more time, followed by the beginning of configuration, provided the INIT input is not externally held Low. Note that a Low on the PROGRAM input
automatically forces a Low on the INIT output. The XC4000
Series PROGRAM pin has a permanent weak pull-up.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration causes the
FPGA to wait after completing the configuration memory
clear operation. When INIT is no longer held Low externally, the device determines its configuration mode by capturing its mode pins, and is ready to start the configuration
process. A master device waits up to an additional 250 Ils
to make sure that any slaves in the optional daisy chain
have seen that INIT is High.
Start-Up
Start-up is the transition from the configuration process to
the intended user operation. This transition involves a
change from one clock source to another, and a change
from interfacing parallel or serial configuration data where
most outputs are 3-stated, to normal operation with I/O pins
active in the user-system. Start-up must make sure that the
user-logic 'wakes up' gracefully, that the outputs· become
active without causing contention with the configuration signals, and that the internal flip-flops are released from the
global Reset or Set at the right time.
Figure 48 describes start-up timing for the three Xilinx families in detail. The configuration modes can use any of the
four timing sequences.
To access the internal start-up signals, place the STARTUP
library symbol.
Start-up Timing
Different FPGA families have different start-up sequences.
The XC2000 family goes through a fixed sequence. DONE
goes High and the internal global Reset is de-activated one
CCLK period after the I/O become active.
The XC3000A family offers some flexibility. DONE can be
programmed to go High one CCLK period before or after
the 110 become active. Independent of DONE, the internal
global Reset is de-activated one CCLK period before or
after the I/O become active.
The XC4000 Series offers additional flexibility. The three
events - DONE going High, the internal Set/Reset being
de-activated, and the user I/O going active - can all occur
in any arbitrary sequence. Each of them can occur one
CCLK period before or after, or simultaneous with, any of
the others. This relative timing is selected by means of software options in the bitstream generation software.
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply
4-52
November 10, 1997 (Version 1.4)
~XILINX
The default option, and the most practical one, is for DONE
to go High first, disconnecting the configuration data source
and avoiding any contention when the II0s become active
one clock later. Reset/Set is then released another clock
period later to make sure that user-operation starts from
stable internal conditions. This is the most common
sequence, shown with heavy lines in Figure 48, but the
designer can modify it to meet particular requirements.
Normally, the start-up sequence is controlled by the internal
device oscillator output (CCLK), which is asynchronous to
the system clock.
received since INIT went High equals the loaded value of
the length count.
The next rising clock edge sets a flip-flop 00, shown in
Figure 49. 00 is the leading bit of a 5-bit shift register. The
outputs of this register can be programmed to control three
events.
•
•
•
The release of the open-drain DONE output
The change of configuration-related pins to the user
function, activating all lOBs.
The termination of the global Set/Reset initialization of
all CLB and lOB storage elements.
XC4000 Series offers another start-up clocking option,
UCLK NOSYNC. The three events described above need
not be- triggered by CCLK. They can, as a configuration
option, be triggered by a user clock. This means that the
device can wake up in synchronism with the user system.
The DONE pin can also be wire-ANDed with DONE pins of
other FPGAs or with other external signals, and can then
be used as input to bit 03 of the start-up register. This is
called "Start-up Timing Synchronous to Done In" and is
selected by either CCLK_SYNC or UCLK_SYNC.
When the UCLK_SYNC option is enabled, the user can
externally hold the open-drain DONE output Low, and thus
stall all further progress in the start-up sequence until
DONE is released and has gone High. This option can be
used to force synchronization of several FPGAs to a common user clock, or to guarantee that all devices are successfully configured before any I/Os go active.
When DONE is not used as an input, the operation is called
"Start-up Timing Not Synchronous to DONE In;' and is
selected by either CCLK_NOSYNC or UCLK_NOSYNC.
If either of these two options is selected, and no user clock
is specified in the design or attached to the device, the chip
could reach a point where the configuration of the device is
complete and the Done pin is asserted, but the outputs do
not become active. The solution is either to recreate the bitstream specifying the start-up clock as CCLK, or to supply
the appropriate user clock.
Start-up Sequence
As a configuration option, the start-up control register
beyond 00 can be clocked either by subsequent CCLK
pulses or from an on-chip user net called STARTUP.CLK.
These signals can be accessed by placing the STARTUP
library symbol.
Start-up from CCLK
If CCLK is used to drive the start-up, 00 through 03 provide the timing. Heavy lines in Figure 48 show the default
timing, which is compatible with XC2000 and XC3000
devices using early DONE and late Reset. The thin lines
indicate all other possible timing options.
The Start-up sequence begins when the configuration
memory is full, and the total number of configuration clocks
November 10, 1997 (Version 1.4)
4-53
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
CCLK
XC2000
F = Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
XC3000
Heavy lines describe
default timing
XC4000EIX
CCLK_NOSYNC
XC4000EIX
CCLK_SYNC
XC4000EIX
UCLK_NOSYNC
XC4000EIX
UCLK_SYNC
---'--~~~~=::~ UCLK Period
X9024
Figure 48: Start-up Timing
4-54
November 10,1997 (Version 1.4)
~XILINX
Start-up from a User Clock (STARTUP.ClK)
Release of User VO After DONE Goes High
When, instead of CCLK, a user-supplied start-up clock is
selected, Q1 is used to bridge the unknown phase relationship between CCLK and the user clock. This arbitration
causes an unavoidable one-cycle uncertainty in the timing
of the rest of the start-up sequence.
By default, the user I/O are released one CCLK cycle after
the DONE pin goes High. If CCLK is not clocked after
DONE goes High, the outputs remain in their initial state 3-stated, with a 50 kQ - 100 kQ pull-up. The delay from
DONE High to active user I/O is controlled by an option to
the bitstream generation software.
DONE Goes High to Signal End of Configuration
XC4000 Series devices read the expected length count
from the bitstream and store it in an internal register. The
length count varies according to the number of devices and
the composition of the daisy chain. Each device also counts
the number of CCLKs during configuration.
Two conditions have to be met in order for the DONE pin to
go high:
•
•
the chip's internal memory must be full, and
the configuration length count must be met, exactly.
This is important because the counter that determines
when the length count is met begins with the very first
CCLK, not the first one after the preamble.
Therefore, if a stray bit is inserted before the preamble, or
the data source is not ready at the time of the first CCLK,
the internal counter that holds the number of CCLKs will be
one ahead of the actual number of data bits read. At the
end of configuration, the configuration memory will be full,
but the number of bits in the internal counter will not match
the expected length count.
Release of Global Set/Reset After DONE Goes
High
By default, Global Set/Reset (GSR) is released two CCLK
cycles after the DONE pin goes High. If CCLK is not
clocked twice after DONE goes High, all flip-flops are held
in their initial set or reset state. The delay from DONE High
to GSR inactive is controlled by an option to the bitstream
generation software.
Configuration Complete After DONE Goes High
Three full CCLK cycles are required after the DONE pin
goes High, as shown in Figure 48 on page 4-54. If CCLK is
not clocked three times after DONE goes High, read back
cannot be initiated and most boundary scan instructions
cannot be used.
Configuration Through the Boundary Scan
Pins
XC4000 Series devices can be configured through the
boundary scan pins. The basic procedure is as follows:
As a consequence, a Master mode device will continue to
send out CCLKs until the internal counter turns over to
zero, and then reaches the correct length count a second
time. This will take several seconds [2 24 * CCLK period] which is sometimes interpreted as the device not configuring at all.
•
If it is not possible to have the data ready at the time of the
first CCLK, the problem can be avoided by increasing the
number in the length count by the appropriate value. The
XACT User Guide includes detailed information about manually altering the length count.
•
•
•
Note that DONE is an open-drain output and does not go
High unless an internal pull-up is activated or an external
pull-up is attached. The internal pull-up is activated as the
default by the bitstream generation software.
The user must account for all TCK clock cycles after INIT
goes High, as all of these cycles affect the Length Count
compare.
November 10, 1997 (Version 1.4)
•
Power up the FPGA with INIT held Low (or drive the
PROGRAM pin Low for more than 300 ns followed by a
High while holding INIT Low). Holding INIT Low allows
enough time to issue the CON FIG command to the
FPGA. The pin can be used as I/O after configuration if
a resistor is used to hold INIT Low.
Issue the CON FIG command to the TMS input
Wait for INIT to go High
Sequence the boundary scan Test Access Port to the
SHIFT-DR state
Toggle TCK to clock data into TDI pin.
For more detailed information, refer to the Xilinx application
note XAPP017, "Boundary Scan in XC4000 Devices:' This
application note also applies to XC4000E and XC4000X
devices.
4-55
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
03
STARTUP
02
01/04
,----------- ~ONE
IN
*
lOBs OPERATIONAL PER CONFIGURATION
"-
*
GLOBAL SET/RESET OF
ALL CL8 AND 108 FLIP-FLOP
~~
\A",,_m
GSR INVERT
STARTUP.GSA
CONTROLLED BY STARTUP SYMBOL
IN THE USER SCHEMATIC (SeE
STARTUP.GTS
LIBRARIES GUIDE)
: F"
GLOBAL 3-STATE OF ALL lOBs
I
a
I
S
<)-1
R
r--
*
L-
I:
k:t
~
00
FULL
LENGTH COUNT
01
r---
=o-~
D
r-~K
I>K
CLEAR MEMORY
1
CCLK
STARTup.elK
USER NET
DONE
1
02
o r-------
r--D
0
rr-
r-~K
"-r
0:
D
"FINISHED "
ENABLES BOUNDA RY
SCAN, READBACK AND
CONTROLS THE 0 SCILLATOR
04
03
or--o-- r
D or--
f>K
~
r- K
~
0,
V
~
*
CONFIGURATION BIT OPTIONS SELECTED BY USER IN 'MAKEBITS"
Figure 49: Start-up Logic
Readback
The user can read back the content of configuration memory and the level of certain internal nodes without interfering with the normal operation of the device.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs and lOBs, as well as the content of function generators used as RAMs.
Note that in XC4000 Series devices, configuration data is
not inverted with respect to configuration as it is in XC2000
and XC3000 families.
XC4000 Series Readback does not use any dedicated
pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA,
RDBK.RIP and RDBK.CLK) that can be routed to any lOB.
To access the internal Readback signals, place the READ-
4-56
BACK library symbol and attach the appropriate pad symbols, as shown in Figure 50.
After Readback has been initiated by a Low-to-High transition on RDBK.TRIG, the RDBK.RIP (Read In Progress)
output goes High on the next rising edge of RDBK.CLK.
Subsequent rising edges of this clock shift out Readback
data on the RDBK.DATA net.
Readback data does not include the preamble, but starts
with five dummy bits (all High) followed by the Start bit
(Low) of the first frame. The first two data bits of the first
frame are always High.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RDBK.RIP returns Low.
November 10,1997 (Version 1.4)
~XILINX
IF UNCONNECTED,
o~'"m"'~~
DATA
ClK
MDO)>------'R.:::E"'AD==-T:.c.R::.::IG::::GE:::.R'---l ~>--~T~RI=jG
READBACK
RIP
:>-_Rcc.:E;:.:A""D_""DAc::T.:..:A_ MD1
OBUF
IBUF
X1786
Figure 50: Readback Schematic Example
Readback Options
Readback options are: Read Capture, Read Abort, and
Clock Select. They are set with the bitstream generation
software.
~
/
PROGRAMMABLE
INTERCONNECT
Read Capture
When the Read Capture option is selected, the readback
data stream includes sampled values of CLB and lOB signals. The rising edge of RDBK.TRIG latches the inverted
values of the four CLB outputs, the lOB output flip-flops and
the input signals 11 and 12. Note that while the bits describing configuration (interconnect, function generators, and
RAM content) are not inverted, the CLB and lOB output signals are inverted.
When the Read Capture option is not selected, the values
of the capture bits reflect the configuration data originally
written to those memory locations.
If the RAM capability of the CLBs is used, RAM data are
available in readback, since they directly overwrite the F
and G function-table configuration of the CLB.
RDBK.TRIG is located in the lower-left corner of the device,
as shown in Figure 51.
Read Abort
When the Read Abort option is selected, a High-to-Low
transition on RDBK.TRIG terminates the read back operation and prepares the logic to accept another trigger.
After an aborted readback, additional clocks (up to one
readback clock per configuration frame) may be required to
re-initialize the control logic. The status of readback is indicated by the output control net RDBK.RIP. RDBK.RIP is
High whenever a read back is in progress.
Clock Select
CCLK is the default clock. However, the user can insert
another clock on RDBK.CLK. Readback control and data
are clocked on rising edges of RDBK.CLK. If readback
must be inhibited for security reasons, the readback control
nets are simply not connected.
RDBK.CLK is located in the lower right chip corner, as
shown in Figure 51.
November 10, 1997 (VerSion 1.4)
[i!QJ....
~
[i!QJ
1
X1787
Figure 51: READBACK Symbol in Graphical Editor
Violating the Maximum High and Low Time
Specification for the Readback Clock
The readback clock has a maximum High and Low time
specification. In some cases, this specification cannot be
met. For example, if a processor is controlling readback, an
interrupt may force it to stop in the middle of a readback.
This necessitates stopping the clock, and thus violating the
specification.
The specification is mandatory only on clocking data at the
end of a frame prior to the next start bit. The transfer mechanism will load the data to a shift register during the last six
clock cycles of the frame, prior to the start bit of the following frame. This loading process is dynamic, and is the
source of the maximum High and Low time requirements.
Therefore, the specification only applies to the six clock
cycles prior to and including any start bit, including the
clocks before the first start bit in the readback data stream.
At other times, the frame data is already in the register and
the register is not dynamic. Thus, it can be shifted out just
like a regular shift register.
The user must precisely calculate the location of the readback data relative to the frame. The system must keep
track of the position within a data frame, and disable interrupts before frame boundaries. Frame lengths and data
formats are listed in Table 20, Table 21 and Table 22.
Readback with the XChecker Cable
The XChecker Universal Download/Readback Cable and
Logic Probe uses the read back feature for bitstream verification. It can also display selected internal signals on the
PC or workstation screen, functioning as a low-cost in-circuit emulator.
4-57
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000ElEXlXL Program Readback Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements.
The following guidelines reflect worst-case values over the recommended operating conditions.
Finished
Internal Net
j r - - - - - - - - - - - - \ \ \-\-------~S
---f
\r----------
rdbk.TRIG
rdclk.1
rdbk.RIP
rdbk.DATA
~~
X1790
ElEX
rdbk.TRIG
rdclk.1
Note 1:
Note 2:
Description
rdbk.TRIG setup to initiate and abort Readback
rdbk.TRIG hold to initiate and abort Readback
rdbk.DATA delay
rdbk.RIP delay
High time
Low time
Symbol
1
2
7
6
5
4
TRTRC
T RCRT
T RCRD
TRCRR
T RCH
T RCL
Min
Max
200
50
-
-
250
250
500
500
250
250
Units
ns
ns
ns
ns
ns
ns
Timing parameters apply to all speed grades.
If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.
XL
rdbk.TRIG
rdclk.1
Note 1:
Note 2:
4-58
Description
rdbk.TRIG setup to initiate and abort Readback
rdbk.TRIG hold to initiate and abort Readback
rdbk.DATA delay
rdbk.RIP delay
High time
Low time
1
2
Symbol
T RTRC
T RCRT
7
6
5
4
TRCRD
T RCRR
T RCH
T RCL
Min
200
50
Max
-
250
250
500
500
250
250
-
Units
ns
ns
ns
ns
ns
ns
Timing parameters apply to all speed grades.
If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.
November 10, 1997 (Version 1.4)
~XILINX
Table 23: Pin Functions During Configuration
MASTER
PARALLEL UP
I
November 10, 1997 (Version 1.4)
4-59
XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 24: Pin Functions During Configuration
SLAVE
SERIAL
MASTER
PARALLEL UP
• XC4000X only
Notes 1. A shaded table cell represents a 50 kQ - 100 kQ pull-up before and during configuration.
2. (I) represents an input; (0) represents an output.
3. INIT is an open-drain output during configuration.
4-60
November 10, 1997 (Version 1.4)
~XILINX
Configuration Timing
There is an internal delay of 0.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge,
The seven configuration modes are discussed in detail in
this section. Timing specifications are included.
Figure 52 shows a full master/slave system. An XC4000
Series device in Slave Serial mode should be connected as
shown in the third device from the left.
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input of the FPGA. The serial configuration bitstream must
be available at the DIN input of the lead FPGA a short
setup time before each rising CCLK edge.
Slave Serial mode is selected by a <111> on the mode pins
(M2, M1, MO). Slave Serial is the default mode if the mode
pins are left unconnected, as they have weak pull-up resistors during configuration.
The lead FPGA then presents the preamble data-and all
data that overflows the lead device-on its DOUT pin.
NOTE:
NOTE:
M2, M1, MO can be shorted
t 0 Vee"fI not use d a s 1/0
M2, M1, MO can be shorted
t 0 Groun d'lI not used as I/O
Vee
47Kfl~~, ~
4.71<0
Nle
MO M1
'--M2
N/C~
4.7KU
C-
OONE
XC1700D
DIN
DATA
LDe
C>
-
-
+5 V
vpp~
eCK
Cell<
PROGRAM
~M2
eeo
-r---
RESET/OE
INIT
I
PWRDN
DIN
DOUT
celK
Vee
XC4000EIX
MASTER
SERIAL
'm'~~'m'l
MO Ml
MQ Ml
M2
DIN
DOUT
----..
4.71([1
II
4.7Kfl
DOUT
I--
celK
XC4000EIX,
XC5200
SLAVE
XC3100A
SLAVE
PROGFiAM
~I
DONE
(Low Reset Option Used)
~
r-
RESET
DIP
~il
I
PROGRAM
X9025
Figure 52: Master/Slave Serial Mode Circuit Diagram
DIN
OW<
---;K
--:t'
Bit n
Bitn+ 1
-l(i)k'r=@,~":J '~---J-~'----®-TC-C-L---}-~~=====
t
L@'w"?.--_______
(j)'orn
DOUT
~
Bitn-1
(Output)
Bitn
X5379
CCLK
Note:
Description
DIN setup
DIN hold
DIN to DOUT
High time
Low time
Frequency
1
2
3
4
5
Symbol
T DCC
TCCD
Tcco
TCCH
Tccl
Fcc
.
Min
20
0
Max
30
--
45
45
10
Units
ns
ns
ns
ns
ns
MHz
Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
Figure 53: Slave Serial Mode Programming Switching Characteristics
November 10, 1997 (Version 1.4)
4-61
XC4000E and XC4000X Series Field Programmable Gate Arrays
Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the FPGA DIN input.
Each rising edge of the CCLK output increments the Serial
PROM internal address counter. The next data bit is put on
the SPROM data output, connected to the FPGA DIN pin.
The lead FPGA accepts this data on the subsequent rising
CCLKedge.
The lead FPGA then presents the preamble data-and all
data that overflows the lead device-on its DOUT pin.
There is an internal pipeline delay of 1.5 CCLK periods,
which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
In the bitstream generation software, the user can specify
Fast ConfigRate, which, starting several bits into the first
frame, increases the CCLK frequency by a factor of eight.
For actual timing values please refer to "Configuration
Switching Characteristics" on page 4-69. Be sure that the
serial PROM and slaves are fast enough to support this
data rate. XC2000, XC3000/A, and XC3100A devices do
not support the Fast ConfigRate option.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output after configuration. Using DONE can also avoid contention on DIN,
provided the early DONE option is invoked.
Figure 52 on page 4-61 shows a full master/slave system.
The leftmost device is in Master Serial mode.
Master Serial mode is selected by a <000> on the mode
pins (M2, M1, MO).
CCLK
(Output)
o
TCKDS
Serial Data In
SerialDQUT
n+2
n-3
n-2
(Output) _ _ _ _ _~ ' - - _ _ _ _ _--J
n-1
'--_ _ _ _ _- - ' ' - _ _ _ _ _ _J
X3223
CCLK
Notes.
Description
DIN setup
DIN hold
Symbol
1
2
I
I
TDSCK
TcKDS
Min
20
0
Max
Units
ns
ns
1. At power-up, Vec must rise from 2.0 V to Vec min In less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until Vcc is valid.
2. Master Serial mode timing is based on testing in slave mode.
Figure 54: Master Serial Mode Programming Switching Characteristics
4-62
November 10, 1997 (Version 1.4)
~XILINX
Master Parallel Down mode is selected by a <110> on the
mode pins. The EPROM addresses start at 3FFFF and
decrement.
Master Parallel Modes
In the two Master Parallel modes, the lead FPGA directly
addresses an industry-standard byte-wide EPROM, and
accepts eight data bits just before incrementing or decrementing the address outputs.
Additional Address lines in XC4000 devices
The XC4000X devices have additional address lines (A 18A21) allowing the additional address space required to
daisy-chain several large devices.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data-and all data that overflows the lead device-on its DOUT pin. There is an internal delay of 1.5 CCLK periods, after the rising CCLK edge
that accepts a byte of data (and also changes the EPROM
address) until the falling CCLK edge that makes the LSB
(DO) of this byte appear at DOUT. This means that DOUT
changes on the falling CCLK edge, and the next FPGA in
the daisy chain accepts data on the subsequent rising
CCLK edge.
The extra address lines are programmable in XC4000EX
devices. By default these address lines are not activated. In
the default mode, the devices are compatible with existing
XC4000 and XC4000E products. If desired, the extra
address lines can be used by specifying the address lines
option in bitgen as 22 (bitgen -g AddressLines:22). The
lines (A18-A21) are driven when a master device detects,
via the bitstream, that it should be using all 22 address
lines. Because these pins will initially be pulled high by
internal pull-ups, designers using Master Parallel Up mode
should use external pull down resistors on pins A 18-A21. If
Master Parallel Down mode is used external resistors are
not necessary.
The PROM address pins can be incremented or decremented, depending on the mode pin settings. This option
allows the FPGA to share the PROM with a wide variety of
microprocessors and microcontrollers. Some processors
must boot from the bottom of memory (all zeros) while others must boot from the top. The FPGA is flexible and can
load its configurationbitstream from either end of the memory.
All 22 address lines are always active in Master Parallel
modes with XC4000XL devices. The additional address
lines behave identically to the lower order address lines. If
the Address Lines option in bitgen is set to 18, it will be
ignored by the XC4000XL deVice.
Master Parallel Up mode is selected by a <100> on the
mode pins (M2, M1, MO). The EPROM addresses start at
00000 and increment.
TO DIN OF OPTIONAL
DAISY·CHAINED FPGAS
HIGH
Li"W Nt
4.71<0
~
MO
M1
The additional address lines (A 18-A21) are not available in
the PC84 package.
Nle
M2
TO CCLK OF OPTIONAL
DAISY-CHAINED FPGAS
----"-
CCLK
canbes~
I M1I M2I
DOUT
NOTE:MO
to Ground if not used
rA16 r- .
A15 r-
MO
A17
as 1/0.
vee
4.7Kn
A1'
lNfj'
A13
I-
r-
~
A11
~
AlO ~
A12
r--"
PROGRAM
/
D7
V-
D6
V-
D5
/
D'
/
D3
/02
/D1
/
DO
~
EPROM
(SKx8)
(OR LARGER)
A9~
A8~
A7~
A6~
A5~
A'~
A3~
A2~
A1~
AO~
A12
~
USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT BETWEEN
ALTERNATIVE CONFIGURATIONS
A11
~
AlO
A9
r-
AS
A7
D7~
A6
D6i'
A5
D5~
A4
o,~
A3
D3~
A2
D2~
A1
D1~
AO
OO~
DIN
DQUT
r-----
CCLK
XC4000ElX
SLAVE
PROGRAM
DONE
fNif
~
DONEIf~
eE
DATA BUS
8
PROGRAM
26
Figure 55: Master Parallel Mode Circuit Diagram
November 10, 1997 (Version 1.4)
4-63
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
AO-A17
(output) _ _ _ _ _
..J~---------A-d-d-re-s-s-fO-r-B-yt-e-n------......)K'
--
Address for Byte n + 1
'I~CDTRAC
00-07
/
RCLK
(output)
CCLK
(output)
OOUT
(output)
Byte n - 1
RCLK
Notes.
Description
Delay to Address valid
Data setup time
Data hold time
Symbol
T RAC
T ORC
T RCO
3
1
2
Min
0
60
0
X6078
Max
200
Units
ns
ns
ns
1. At power-up, Vcc must rise from 2.0 V to Vcc min In less than 25 ms, otherwise delay configuratIOn by pulling PROGRAM
Low until Vcc is valid.
2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
Figure 56: Master Parallel Mode Programming Switching Characteristics
4-64
November 10, 1997 (Version 1.4)
E:XILINX
Synchronous Peripheral Mode
The lead FPGA serializes the data and presents the preamble data (and all data that overflows the lead device) on
its DOUT pin. There is an internal delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
Synchronous Peripheral mode can also be considered
Slave Parallel mode. An external signal drives the CCLK
input(s) of the FPGA(s). The first byte of parallel configuration data must be available at the Data inputs of the lead
FPGA a short setup time before the rising CCLK edge.
Subsequent data bytes are clocked in on every eighth consecutive rising CCLK edge.
In order to complete the serial shift operation, 10 additional
CCLK riSing edges are required after the last data byte has
been loaded, plus one more CCLK cycle for each daisychained device.
The same CCLK edge that accepts data, also causes the
RDY/BUSY output to go High for one CCLK period. The pin
name is a misnomer. In Synchronous Peripheral mode it is
really an ACKNOWLEDGE signal. Synchronous operation
does not require this response, but it is a meaningful signal
for test purposes. Note that RDY/BUSY is pulled High with
a high-impedance pullup prior to INIT going High.
Synchronous Peripheral mode is selected by a <011> on
the mode pins (M2, M1, MO).
NOTE:
M2 can be shorted to Ground
if not used as I/O
N/C
~
1 I
MO Ml
4.7 kQ
N/C
~
~
M2
CCLK
CLOCK
DIN
DOUT
-,-
4.7kQ
XC4000E/X
SYNCHRONOUS
PERIPHERAL
--RDY/BUSY
CO NTROL {
S IGNALS
INIT
L
M2
CCLK
DO•7
VCC
LI
MO Ml
OPTIONAL
DAISY-CHAINED
FPGAs
8/
DATABUS
I
DONE
DOUT
-
XC4000E/X
SLAVE
r---
INIT
DONE
-
4.7 kQ
PROGRAM
-=
PROGRAM
- - - > PROGRAM
X9027
Figure 57: Synchronous Peripheral Mode Circuit Diagram
November 10, 1997 (Version 1.4)
4-65
XC4000E and XC4000X Series Field Programmable Gate Arrays
CClK
I~""-----
I:
~
I
________~----~,~~O~~~.1~T
~
DOUT
__~Y--\~___________________________~r--\~_____
I
ROY/BUSY
X6096
Symbol
Min
TIC
5
Toc
Tco
60
0
/ls
ns
ns
CCLK High time
TCCH
50
ns
CCLK Low time
Tccl
Fcc
60
Description
INIT (High) setup time
CCLK
DO - D7 setup time
DO - D7 hold time
CCLK Frequency
Notes:
Max
Units
ns
8
MHz
1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the
first data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on every
eighth consecutive rising edge of CCLK.
2. The ROY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does
not require such a response.
3. The pin name ROY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.
4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,
additional CCLK pulses are clearly required after the last byte has been loaded.
Figure 58: Synchronous Peripheral Mode Programming Switching Characteristics
4-66
November 10, 1997 (Version 1.4)
~XILINX
Asynchronous Peripheral Mode
The REAOY/BUSY handshake can be ignored if the delay
from anyone Write to the end of the next Write is guaranteed to be longer than 10 CCLK periods.
Write to FPGA
Asynchronous Peripheral mode uses the trailing edge of
the logic ANO condition of WS and CSO being Low and RS
and CS1 being High to accept byte-wide data from a microprocessor bus. In the lead FPGA, this data is loaded into a
double-buffered UART-like parallel-to-serial converter and
is serially shifted into the internal logic.
Status Read
The logic ANO condition of the CSO, CS1 and RS inputs
puts the device status on the Oata bus.
•
•
•
The lead FPGA presents the preamble data (and all data
that overflows the lead device) on its OOUT pin. The ROY/
BUSY output from the lead FPGA acts as a handshake signal to the microprocessor. ROY/BUSY goes Low when a
byte has been received, and goes High again when the
byte-wide input buffer has transferred its information into
the shift register, and the buffer is ready to receive new
data. A new write may be started immediately, as soon as
the ROY/BUSY output has gone Low, acknowledging
receipt of the previous data. Write may not be terminated
until ROY/BUSY is High again for one CCLK period. Note
that ROY/BUSY is pulled High with a high-impedance pullup prior to INIT going High.
07 High indicates Ready
07 Low indicates Busy
00 through 06 go unconditionally High
It is mandatory that the whole start-up sequence be started
and completed by one byte-wide input. Otherwise, the pins
used as Write Strobe or Chip Enable might become active
outputs and interfere with the final byte transfer. If this
transfer does not occur, the start-up sequence is not completed all the way to the finish (point F in Figure 48 on page
4-54).
In this case, at worst, the internal reset is not released. At
best, Readback and Boundary Scan are inhibited. The
length-count value, as generated by the XACTstep software, ensures that these problems never occur.
Although ROY/BUSY is brought out as a separate signal,
microprocessors can more easily read this information on
one of the data lines. For this purpose, 07 represents the
ROY/BUSY status when RS is Low, WS is High, and the
two chip select lines are both active.
The length of the BUSY signal depends on the activity in
the UART. If the shift register was empty when the new
byte was received, the BUSY signal lasts for only two CCLK
periods. If the shift register was still full when the new byte
was received, the BUSY signal can be as long as nine
CCLK periods.
Asynchronous Peripheral mode is selected by a <101> on
the mode pins (M2, M1, MO).
Note that after the last byte has been entered, only seven of
its bits are shifted out. CCLK remains High with OOUT
equal to bit 6 (the next-to-Iast bit) of the last byte entered.
N/C
N
/C
-1- 4.7
k.nq
MO
8
DATA
BUS
Ml
00-7
ADDRESS
BUS
kn
4.7kf.!
~
MO
M2
CCLK
Ml
M2
GGLK
OPTIONAL
DAiSY-CHAINED
FPGAs
- VCC
Nrc
DOUT
ADDRESS
DECODE
r---
XC4000EIX
ASYNCHRONOUS
PERIPHERAL
~
CSO
LOGIC
-
DOUT
DIN
-
XC4000EIX
SLAVE
CSl
-
RS
Ws
-
CONTROL
SIGNALS
ROY/BUSY
-
-
INIT
JNIT
DONE
DONE
--
REPROGRAM
PROGRAM
~
PROGRAM
4.7 k11
~
X9028
Figure 59:
Asynchronous Peripheral Mode Circuit Diagram
November 10, 1997 (Version 1.4)
4-67
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
Write to LeA
Read Status
RS,CS1
WS,CS1
00,07
07
CCLK
ROY/BUSY
............................
OOUT
________
.
.
~)(~____________p_re_v_iO_U_S_BY_te__06____________J)(
07
x
X
DO
Dl
~
X6097
Description
Write
Effective Write time
(CSO, WS=Low; RS, CS1=High)
1
TeA
Min
100
DIN setup time
2
3
Toe
60
Teo
a
ROY/BUSY delay after end of
Write or Read
4
TWTRB
ROY/BUSY active after beginning
of Read
7
ROY/BUSY Low output (Note 4)
6
DIN hold time
ROY
Notes:
Symbol
T BUSY
Max
Units
ns
ns
ns
2
60
ns
60
ns
9
CCLK
periods
1, Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High,
2, The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte processing
and the phase of the internal timing generator for CCLK,
3. CCLK and DOUT timing is tested in slave mode,
4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data, The shortest
T BUSY occurs when a byte is loaded into an empty parallel-to-serial converter, The longest TBUSY occurs when a new word
is loaded into the input register before the second-level buffer has started shifting out data.
This timing diagram shows very relaxed requirements, Data need not be held beyond the rising edge of WS. ROY/BUSY will
go active within 60 ns after the end of WS, A new write may be asserted immediately after ROY/BUSY goes Low, but write
may not be terminated until ROY/BUSY has been High for one CCLK period,
Figure 60: Asynchronous Peripheral Mode Programming Switching Characteristics
4-68
November 10, 1997 (Version 1.4)
~XILINX
Configuration Switching Characteristics
Vee
yt--------
TpOR
----_1
RE-PROGRAM
PROGRAM
CCLK OUTPUT or INPUT
MO, M1, M2
(Required)
DONE RESPONSE
X1532
~I_ <300ns
I/O~
Master Modes (XC4000ElEX)
Description
I
I
Power-On Reset
Program Latency
MO = High
MO = Low
Symbol
Min
Max
Units
T pOR
10
40
1
40
130
4
ms
ms
250
2000
250
~s
TCCLK
40
640
80
Symbol
Min
Max
Units
T pOR
10
40
1
40
130
4
ms
ms
250
1600
200
~s
TCCLK
40
540
67
Symbol
Min
Max
Units
T pOR
10
1
33
4
T pOR
T p1
CCLK (output) Delay
CCLK (output) Period, slow
CCLK (output) Period, fast
T 1CCK
TCCLK
~s per
CLB column
ns
ns
Master Modes (XC4000XL)
Description
I
I
Power-On Reset
MO = High
MO = Low
Program Latency
T pOR
Tpi
CCLK (output) Delay
CCLK (output) Period, slow
CCLK (output) Period, fast
T 1CCK
TCCLK
~s per
CLBcolumn
ns
ns
Slave and Peripheral Modes(AII)
Description
Power-On Reset
Program Latency
CCLK (input) Delay (required)
CCLK (input) Period (required)
November 10,1997 (Version 1.4)
Tpi
T 1CCK
TCCLK
4
100
ms
per
CLB column
~s
~s
ns
4-69
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
4-70
November 10, 1997 (Version 1.4)
~XILINX
XC4000XL Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:
Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device
families. Values are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.
All specifications subject to change without notice.
Additional Specifications
Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are
derived from measuring internal test patterns.AII specifications are representative of worst- case supply voltage and junction
temperature conditions. The parameters included are common to popular designs and typical applications. For design
considerations requiring more detailed timing information, see the appropriate family a.c. supplements available on the
Xilinx WEBLINX at http://www.xilinx.com.
XC4000XL Absolute Maximum Ratings
Value
Units
Vee
Supply voltage relative to GND
Description
-0.5 to 4.0
V
VIN
Input voltage relative to GND (Note 1)
-0.5 to 5.5
V
Voltage applied to 3-state output (Note 1)
-0.5 to 5.5
V
50
ms
Symbol
VTS
Veet
Longest Supply Voltage Rise Time from 1V to 3V
TSTG
Storage temperature (ambient)
TSOL
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
TJ
Notes:
-65 to +150
°C
+260
°C
+150
°C
+125
°C
I Ceramic packages
I Plastic packages
Junction temperature
1. Maximum DC undershoot below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During
transitions, the device pins may undershoot to -2.0 V or overshoot to + 7.0 V, provided this over- or undershoot lasts less
than 10 ns and with the forcing current being limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
XC4000XL Recommended Operating Conditions
Min
Max
Units
Supply voltage relative to GND, TJ = O°C to +85°C
Commercial
3.0
3.6
V
Vee
Supply voltage relative to GND, TJ = -40°C to
+100°C
Industrial
3.0
3.6
V
V IH
High-level input voltage
50% of Vee
5.5
V
V IL
Low-level input voltage
0
30% of Vee
V
TIN
Input signal transition time
250
ns
Symbol
Notes:
Description
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per DC.
Input and output measurement threshold is -40% of Vcc.
November 10,1997 (Version 1.4)
4-71
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL DC Characteristics Over Recommended Operating Conditions
Symbol
VOH
VOL
Description
Min
= -4.0 mA, Vee min (LVTTL)
= -500 /lA, (LVGMOS)
1m = 12.0 mA, Vee min (LVTTL) (Note 1)
IOL = 1500 /lA, (L VCMOS)
Units
High-level output voltage @ IOH
2.4
V
High-level output voltage @ IOH
90% Vee
V
Low-level output voltage @
Low-level output voltage @
V OR
Data Retention Supply Voltage (below which configuration data may be lost)
leeo
Quiescent FPGA supply current (Note 2)
IL
Max
Input or output leakage current
0.4
V
10%Vee
V
5
mA
2.5
-10
Input capacitance (sample tested)
GIN
V
+10
/lA
BGA, SBGA, PQ, HQ, MQ
packages
10
pF
PGA packages
16
pF
= OV (sample tested)
= 3.6V (sample tested)
IRPU
Pad pull-up (when selected) @ Yin
0.02
0.25
mA
IRPO
Pad pull-down (when selected) @ Yin
0.02
0.15
mA
IRLL
Horizontal Longline pull-up (when selected) @ logic Low
0.3
2.0
mA
Note 1:
Note 2:
4-72
With up to 64 pins simultaneously sinking 12 mA.
With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and floating.
November 10, 1997 (Version 1.4)
~:XILINX
XC4000XL Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible lOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature).
Description
From pad through Global Low Skew buffer,
to any clock K
Symbol
T GLS
From pad through Global Early buffer,
TGE
to any clock K in same quadrant
Values are for BUFGE #s 1,2,5 and 6. Add 1
- 2 ns for BUFGE #s 3, 4, 7 and 8 or consult
TRCE.
Speed Grade
·3
·2
-1
-09
Device
Max
Max
Max
Max
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
2.7
3.2
3.6
4.0
4.4
4.8
5.3
5.7
6.3
7.2
2.3
2.8
3.1
3.5
3.8
4.2
4.6
5.0
5.4
6.2
2.0
2.4
2.7
3.0
3.3
3.6
4.0
4.5
4.7
5.7
1.9
2.3
2.6
2.9
3.2
3.5
3.9
4.4
4.6
5.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
1.9
2.2
2.4
2.6
2.8
3.1
3.5
4.0
4.9
5.8
1.8
1.9
2.1
2.2
2.4
2.7
3.0
3.5
4.3
5.1
1.7
1.7
1.8
2.1
2.1
2.3
2.6
3.0
3.7
4.7
1.6
1.7
1.7
2.0
2.0
2.2
2.4
3.0
3.4
4.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10,;';,", .. \:;'pr.El!im!nary ,\, <
November 10, 1997 (Version 1.4)
"••....•
Units
>
4-73
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38S10/60S. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and expressed in nanoseconds unless otherwise noted.
-3
Speed Grade
-2
-1
-09
f-------=------:---,---------''--r--=----,-II--:-=--,--,.."---I---:-:,---,.....,-=--I-.,,..,,-~=__I__=____,""'''__I
Description
Symbol
Min
Max
Min
Max
Min
Max
FIG inputs to XIY outputs
T llO
1.6
1.5
FIG inputs via H' to XIV outputs
T IHO
2.7
2.4
FIG inputs via transparent latch to outputs
TITO
2.9
2.6
C inputs via SR/HO via H to XIY outputs
THHOO
2.5
2.2
THHlO
2.4
2.1
C inputs via H1 via H to X!Y outputs
C inputs via DIN/H2 via H to XIY outputs
THH20
2.5
2.2
C inputs via EC, DIN/H2 to YO, xa output (bypass)
TCBYP
1.5
1.3
CLB Fast Carry L o g i c " , ! > ; ' . : ; ; : ; ; •...: " : " ; . . , ; '.'> .: .....;. ;:'.:;.' .':.. '"
1.3
2.2
2.2
2.0
1.9
2.0
1.1
a
Operand inputs (F1, F2, G1, G4) to COUT
AddlSubtract input (F3) to COUT
Initialization inputs (F1 , F3) to COUT
CIN through function generators to XIV outputs
CIN to COUT, bypass function generators
Carry Net Delay, CauTto CIN
T OPCY
TASCY
T INCY
TSUM
T BYP
TNET
2.7
3.3
2.0
2.8
0.26
0.32
a
a
TCKO
TCKLO
FIG inputs
FIG inputs via H
C inputs via HO through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
C inputs via EC
C inputs via SIR, going Low (inactive)
CIN input via FIG
CIN input via FIG and H
Hold Time after Clock K
FIG inputs
FIG inputs via H
C inputs via SR/HO through H
C inputs via H1 through H
C inputs via DIN/H2 through H
C inputs via DIN/H2
C inputs via EC
C inputs via SR, gOing Low (inactive)
TICK
T IHCK
THHOCK
T HH1CK
T HH2CK
T DICK
T ECCK
T RCK
TCCK
TCHCK
.• :'.': ..!.
1.1
2.2
2.0
1.9
2.0
0.9
1.0
0.6
2.3
3.4
'::
ns
ns
ns
ns
ns
ns
ns
I· ..• : '.
1.6
1.8
1.0
1.7
0.14
0.24
";:'" :...•.. '., ..L::.:
1.9
1.9
1.6
1.6
'.:';;' '.
Clock
TCH
TCl
1.0
1.9
1.7
1.6
1.7
0.8
0.9
0.5
2.1
3.0
0.9
1.7
1.6
1.4
1.6
0.7
0.8
0.5
1.9
2.7
.;<;\::.:..... .. • J .•
,:......>'. :";.'
..
1.5
1.5
;'
..
ns
ns
a
TRPW
TRIO
Toggle Frequency (MHz) (for export control purposes)
2.8
3.7
3.2
. '.\ ···.'·i·;;; .. ;:.
Global Sel/Reset
Minimum GSR Pulse Width
Delay from GSR input to any Q
3.0
TMRW
19.8
17.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
.•.... i •.••• ·
0
0
0
0
0
0
0
0
';:
2.8
2.8
................;. I; ...•... ';. •......:.;~...•....•..•. :
Sel/Reset Direct
'.•<;.":; •.. ;.;.: .....:•.
0
0
0
0
0
0
0
0
:.. ' : : . : " : . : . "
3.0
3.0
0.8
1.6
1.4
1.2
1.4
0.6
0.7
0.4
1.7
2.5
:.••....•••~
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TCKI
TCKIH
T CKHHO
TCKHHl
T CKHH2
TCKDI
T CKEC
TCKR
Clock High time
Clock Low time
4-74
....:. ::.
2.0
2.5
1.5
2.4
0.20
0.25
Units
':.;:.;; .;;:. •·i. ;: ... ; ••. ;.. : : : : ; : ; . ' ; ; :••... ;.; .• :.' •.•• ;:;; •.•.;;.::.:i'
Setup Time before Clock K
Width (High)
Delay from C inputs via SIR, going High to
2.1
2.1
Max
1.2
2.0
2.0
1.8
1.6
1.8
1.0
· i ••. ;. ' ; : : i'::
2.3
2.9
1.8
2.6
0.23
0.28
Sequential D e l a y s / · " : . ; . . ::; ...': ..•••••••.. :,:.;: •• :'.
Clock K to Flip-Flop outputs
Clock K to Latch outputs
Min
,:'"
2.5
2.5
2.3
2.3
2.5
2.3
ns
ns
ns
ns
ns
ns
ns
ns
..•.:.: ....•. ;:
;
:;;
'.' ..........: ... ;. ·.i.<
2.8
;':..
ns
ns
.';> I.;;.'
2.7
ns
ns
. , . ' ...•.•.....:.;.:....;.:. I: •••.
15.0
14.0
ns
217
MHz
See page 4-80 for T RRI values per device
166
179
200
November 10, 1997 (Version 1.4)
-
---------
~XILINX
XC4000XL CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation nellis!. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
Single Port RAM
Write Operation
Address write cycle time (clock K period)
16x2
32x1
Twcs
T WCTS
9.0
9.0
8.4
8.4
7.7
7.7
7.4
7.4
ns
ns
Clock K pulse width (active edge)
16x2
32x1
TwPS
TWPTS
4.5
4.5
4.2
4.2
3.9
3.9
3.7
3.7
ns
ns
Address setup time before clock K
16x2
32x1
TASS
TASTS
2.2
2.2
2.0
2.0
1.7
1.7
1.7
1.7
ns
ns
Address hold time after clock K
16x2
32x1
TAHS
TAHTS
0
0
0
0
0
0
0
0
ns
ns
DIN setup time before clock K
16x2
32x1
Toss
T OSTS
2.0
2.5
1.9
2.3
1.7
2.1
1.7
2.1
ns
ns
DIN hold time after clock K
16x2
32x1
T OHS
T OHTS
0
0
0
0
0
0
0
0
ns
ns
WE setup time before clock K
16x2
32x1
Twss
TWSTS
2.0
1.8
1.8
1.7
1.6
1.5
1.6
1.5
ns
ns
WE hold time after clock K
16x2
32x1
TWHS
TWHTS
0
0
0
0
0
0
0
0
ns
ns
Data valid after clock K
16x2
32x1
Twos
TWOTS
16x1
16x1
16x1
16x1
16x1
16x1
16x1
Twcos
Twpos
TAsos
TAHOS
Tosos
TOHos
Twsos
TWHOS
Twoos
6.8
8.1
6.3
7.5
5.8
6.9
5.8
6.9
ns
ns
6.7
ns
ns
ns
ns
ns
ns
ns
ns
Dual Port RAM
Write Operation
Address write cycle time (clock K
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
Note:
2.5
0
1.8
0
2.0
0
1.6
0
7.8
7.3
2.0
0
1.6
0
6.7
Timing for the 16 x1 RAM option is identical to 16 x 2 RAM timing_
November 10, 1997 (Version 1.4)
4-75
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
CLB RAM Synchronous (Edge-Triggered) Write Timing
---- - -----------------, ,.----.;;;;...::..---.
WCLK(K) ____________________________________JI
TWSS
T WHS
WE
DATA IN
ADDRESS
DATA OUT
X6461
CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing
WCLK(K)
- - - - - - - - - - - - - - - - - - - - - - , ~-..;,.;;..:...:;..-""""\I
________________________________- - J
T WSDS
WE
T DSDS
DATA IN
ADDRESS
DATA OUT
X6474
4-76
November 10, 1997 (Version 1.4)
~XILINX
XC4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation nellist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report.
XC4000XL Output Flip-Flop, Clock to Out
Units
Global Early Clock to Output using OFF
Values are for BUFGE #s 1, 2, 5 and 6. Add
1 - 2 ns for BUFGE #s 3,4, 7 and 8, or consultTRCE
For output SLOW option add
OFF
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
9.0
9.4
9.8
10.3
10.7
11.3
12.2
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
6.9
7.2
7.4
7.6
7.8
8.1
8.5
9.0
9.9
10.8
TICKEOF
T SLOW
7.9
8.2
8.5
9.0
9.3
9.7
10.5
5.8
6.2
6.5
6.8
7.1
7.4
7.8
8.3
8.5
9.5
6.1
6.4
6.7
7.0
7.4
7.9
8.1
9.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.1
6.2
6.4
6.5
6.7
7.0
7.3
7.8
8.6
9.4
5.5
5.5
5.6
5.9
5.9
6.1
6.4
6.8
7.5
8.5
5.1
5.2
5.2
5.5
5.5
5.7
5.9
6.5
6.9
7.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
All Devices
= Output Flip Flop
Notes: Listed above are representative values where one global clock input drives one
and where all accessible lOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at -50% Vee threshold with 50 pF external capacitive load. For different loads, see graph below.
Capacitive Load Factor
Figure 1 shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the specified output delay if the load capacitance is different than
50 pF. For example, if the actual load capacitance is
120 pF, add 2.5 ns to the specified delay. If the load capacitance is 20 pF, subtract 0.8 ns from the specified output
delay.
Figure 1 is usable over the specified operating conditions of
voltage and temperature and is independent of the output
slew rate control.
3
(j) 2
.s
>- 1
IV
(j)
C
0
IV
.~
~ -1
~
,...
.oiI~
~
." ~
~
•
~ P""
-2
o
40
60
80 100 120 140
Capacitance (pF)
Figure 61: Additional Delay VS Capacitive LoadS"?"
November 10, 1997 (Version 1.4)
20
4-77
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL Pin-ta-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested .. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and. are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report.
XC4000XL Global Low Skew Clock, Set-Up and Hold
Units
TpHD
XC4005XL
XC4010XL
XC4013XL*
XC4020XL
XC4028XL
XC4036XL*
XC4044XL
XC4052XL
XC4062XL*
XC4085XL
All Devices
6.4
8.8
9.3
6.6
10.6
11.2
6.8
12.7
0
7.6
8.1
6.2
9.2
9.7
6.4
11.0
0
6.6
7.0
5.8
8.0
8.4
6.0
9.6
0
5.6
5.8
4.8
6.2
6.4
5.3
6.8
7.0
5.5
8.4
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
Setup time is measured with the fastest route and the lightest load. Use the
I I
setup time
load of one clock pin per
under given design conditions. Hold time is measured using the furthest distance and a
two lOBs. Use the static timing analyzer to determine the setup and hold times under given design conditions.
For Setup and Hold parameter adjustments related to Voltage and Temperature, check the latest XC4000XL data sheet
supplement on the Xilinx website, WEBLINX at http://www.xilinx.com. or contact your local sales representative.
For partial and no delay input path parameters, check the latest XC4000XL data sheet supplement on the Xilinx website,
WEBLINX at http://www.xilinx.com. or contact your local sales representative.
* The XC4013XL, XC4036XL, and 4062XL have significantly faster setup times than other family members.
4-78
November 10, 1997 (Version 1.4)
-
--~~~~~
- - -
F.:XILINX
XC4000XL BUFGE #s 3, 4, 7, and 8 Global Early Clock, Set-Up and Hold for IFF and FCL
Description
Input Setup Time
Global Early clock and IFF (partial delay)
Global Early clock and FCL (partial delay)
T pSEP
TpFSEP
Input Hold Time
Global Early clock and IFF (partial delay)
Global Early clock and FCL (partial delay)
T pHEP
T PFHEP
Symbol
Speed Grade
Device
XC4005XL
XC4010XL
XC4013XL*
XC4020XL
XC4028XL
XC4036XL*
XC4044XL
XC4052XL
XC4062XL*
XC4085XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
-3
Min
8.4
10.3
5.4
9.8
12.7
6.4
13.8
14.5
8.4
14.5
0
0
0
0
0
0.8
0
0
1.5
0
-2
Min
7.9
9.0
4.9
9.3
11.0
5.9
12.0
12.7
7.9
12.7
0
0
0
0
0
0.8
0
0
1.5
0
-1
Min
7.4
7.8
4.4
8.8
9.6
5.4
10.4
11.0
7.4
11.0
0
0
0
0
0
0.8
0
0
1.5
0
;:: :: .': •. Pr~hm~:atr· •.
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
-09
Min
7.2
7.4
4.3
8.5
9.3
5.0
10.2
10.7
6.8
10.8
0
0
0
0
0
0.8
0
0
1.5
0
. : ..:;;
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC4000XL BUFGE #s 1,2,5, and 6 Global Early Clock, Set-Up and Hold for IFF and FCL
Description
Input Setup Time
Global Early clock and IFF (partial delay)
Global Early clock and FCL (partial delay)
Input Hold Time
Global Early clock and IFF (partial delay)
Global Early clock and FCL (partial dela:y)
Symbol
T pSEP
TpFSEP
T pHEP
TpFHEP
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
Speed Grade
Device
XC4005XL
XC4010XL
XC4013XL*
XC4020XL
XC4028XL
XC4036XL*
XC4044XL
XC4052XL
XC4062XL*
XC4085XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
-3
Min
9.0
11.9
6.4
10.8
14.0
7.0
14.6
16.4
9.0
16.7
0
0
0
0
0
0
0
0
0.8
0
-2
Min
8.5
10.4
5.9
10.3
12.2
6.6
12.7
14.3
8.6
14.5
0
0
0
0
0
0
0
0
0.8
0
-1
Min
8.0
9.0
5.4
9.8
10.6
6.2
11.0
12.4
8.2
12.6
0
0
0
0
0
0
0
0
0.8
0
.;:~:~f::')~.:~ .. .pl1i\BmlFlliltr
-09
Min
7.5
8.0
4.9
9.0
9.8
5.2
10.8
11.4
7.0
11.6
0
0
0
0
0
0
0
0
0.8
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
;:) .. :~'):
Notes. Setup time IS measured With the fastest route and the lightest load. Hold time IS measured uSing the farthest distance and a reference
load of one clock pin per two lOBs. Use the static timing analyzer to determine the setup and hold times under given design conditions.
* The XC4013XL, XC4036XL, and 4062XL have significantly faster setup times than other family members.
November 10, 1997 (Version 1.4)
4-79
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL lOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlis!. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature).
Description
Clocks
Clock Enable (EC) to Clock (IK)
Delay from FCL enable (OK) active edge to IFF
clock (IK) active edge
Setup Times
Pad to Clock (IK), no delay
Pad to Clock (IK), via transparent Fast Capture
Latch, no delay
Pad to Fast Capture Latch Enable (OK), no delay
Hold Times
All Hold Times
Propagation Delays
Pad to 11, 12
Pad to 11, 12 via transparent input latch, no delay
Pad to 11, 12 via transparent FCL and input latch,
no delay
Clock (IK) to 11, 12 (flip-flop)
Clock (IK) to 11, 12 (latch enable, active Low)
FCL Enable (OK) active edge to 11, 12
(via transparent standard input latCh)
Global Set/Reset
Minimum GSR Pulse Width
Delay from GSR input to any Q
Speed Grade
Device
Symbol
-3
-2
Min
Min
-1
Min
-09
Min
Units
I.,;;:,;;;;:,;;:::;:!'!,.,; I~l~:'::;;,:;;i;!;;i,!;;;;t:: li;l::;:l~;.:i::j;i;, :::i,i:,;;:;:;.I;',';'i;li;~,;:,:'I,;;::I ;,;':;;;:;,:,!,:I:;;::,::: ;;:;,i,::ji';:i;;'
T ECIK
TOKIK
1,:i::;';,:::;:;:[1
T plCK
T PICKF
All devices
All devices
0.3
1.7
0.2
1.5
0.1
1.3
0.0
1.2
l>q;:;'n;,.;i:il::':;I,';~;:;'::i~:I:I';;:I;:i:::::::1:;,;lli,I:!I::;:::I':::'@::
1':<::;1';:>;<11:::;;::":::'
All devices
1.7
1.5
1.3
1.3
All devices
2.3
1.8
2.1
1.7
T pOCK
All devices
I::i:,i~i~i;:':ii};i::"
;:<,;:;;
All devices
0.7
0.6
l:i:;i;:i;;:r;Oi;i/,;;II;;::i':;f;;':
0.5
iC;;;;';,';:,;:';:;:;';IF,:'
0.5
ns
ns
'.I;:!,::::;::::'::,
ns
ns
ns
"',1:1::;,,'1;1 il':";".::;'::;::;'
0
Max
1.2
1.9
2.4
III!I;I:;';;';,
T PFLI
0
Max
1.4
2.2
2.7
0
Max
All devices
All devices
All devices
0
Max
1.6
2.6
3.1
1.1
1.8
22
ns
ns
ns
TIKRI
TIKLI
TOKLI
All devices
All devices
All devices
1.8
1.9
3.6
1.5
1.7
3.1
1.3
1.4
2.7
1.2
1.3
2.6
ns
ns
ns
;,;;",:;,,:;:;;';':'
T plD
TpLi
,;i:',:';;;;;;!';;!:;;;,;';;;;
ns
1:;lil::~;:jl;O::I,~;' ~i;;I:; ;i;W';I;~;E:;;f;: : 1; ~~~li;;::;t;i:': i:;;:,:~: ~"J;i:;i :;~:;~':::; ::;:;;,!,:I,; :::;:;;.11;; J:;J;;::I;;:.I:~;i;.
T MRW
TRRI
All devices
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
19.8
11.3
13.9
15.9
18.6
20.5
22.5
25.1
27.2
29.1
34.4
17.3
9.8
12.1
13.8
16.1
17.9
19.6
21.9
23.6
25.3
29.9
1;:;;;:·;,1::;::::;,,:,';;;1(:'
15.0
8.5
10.5
12.0
14.0
15.5
17.0
19.0
20.5
22.0
26.0
iii::
14,0
8.1
10.0
11.4
13.3
14.3
16.2
18.1
19.5
20.9
24.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t·;;:>
IFF - Input Flip-Flop or Latch, FCL - Fast Capture Latch
4-80
November 10,1997 (Version 1.4)
~XILINX
XC4000XL lOB Output SWitching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlis!. These path
delays, provided as a guideline, have been extracted from the static timing analyzer repor!. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless
otherwise noted. Values are expressed in nanoseconds unless otherwise noted.
-2
-3
Description
Symbol
Min
Max
I:· ) . . • .• · • . . 1..... , .., . . ; ' ;
Clocks
Clock High
Clock Low
TCH
TCL
Propagation Delays
Clock (OK) to Pad
Output (0) to Pad
3-state to Pad hi-Z (slew-rate independent)
3-state to Pad active and valid
Output (0) to Pad via Fast Output MUX
Select (OK) to Pad via Fast MUX
.
::.....<
Min
••• :.:
3.0
3.0
I::;·. . ;s·:...
Global Set/Reset
Minimum GSR pulse width
Delay from GSR input to any Pad
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
T MRW
TRPO
i ..•
2.8
2.8
Min
Max
Min
Max
Units
:>.:.:.!....·;,::»::: :".:'.
2.5
2.5
2.3
2.3
ns
ns
n: . . :}:. ..':;',: ;.•.•. i,....;:.• ·. :.•.:::'.,.:•.. <.:\:...::::;:;,; ..: .
TOKPOF
TOPF
TT8HZ
TT80NF
TOFPF
TOKFPF
TOOK
TOKO
T ECOK
TOKEC
Max
"c.' • • . .
5.0
4.1
4.4
4.1
5.5
5.1
4.4
3.6
3.8
3.6
4.8
4.5
Setup and Hold T i m e s l ; , ( " : : i : : ; . : } .'
Output (0) to clock (OK) setup time
Output (0) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
-09
-1
0.5
0.0
0.0
0.3
3.8
3.1
3.3
3.1
4.2
3.9
3.5
3.0
3.3
3.0
4.0
3.7
ns
ns
ns
ns
ns
ns
.:.?:.:.,;:.[.:::. .:i;:.::
0.4
0.0
0.0
0.2
0.3
0.0
0.0
0.1
·:'i,:.:···· ;,;:..... ?~);
.:~::
0.3
0.0
0.0
0.0
ns
ns
ns
ns
.. ::' .•.•. :. ;.:::. "::.•:;:,:;: .. ::,>:
19.8
17.3
15.0
14.0
ns
15.9
18.5
20.5
23.2
25.1
27.1
29.7
31.7
33.7
39.0
13.8
16.1
17.8
20.1
21.9
23.6
25.9
27.6
29.3
33.9
12.0
14.0
15.5
17.5
19.0
20.5
22.5
24.0
25.5
29.5
11.4
13.3
14.7
16.6
17.6
19.4
21.4
22.8
24.2
28.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Slew Rate Adjustment
For output SLOW option add
Note: Output timing
IS
T8LOW
3.0
I
2.5
2.0
1.7
ns
measured at -50% Vee threshold, with 50 pF external capacitive loads.
November 10, 1997 (Version 1.4)
4-81
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000EX Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:
Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device
families. Values are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.
All specifications subject to change without notice.
XC4000EX Absolute Maximum Ratings
Symbol
Description
Value
Units
-0.5 to +7.0
V
Input voltage relative to GND (Note 1)
-0.5 to Vee +0.5
V
VTs
Voltage applied to 3-state output (Note 1)
-0.5 to Vee +0.5
V
Vee
Supply voltage relative to GND
V IN
Vee!
Longest Supply Voltage Rise Time from 1 V to 4 V
T STG
Storage temperature (ambient)
TSOL
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
TJ
Notes:
50
ms
-65 to + 150
°C
+260
°C
+150
°C
+125
°C
l Ceramic packages
Junction temperature
I
Plastic packages
1. Maximum DC overshoot or undershoot above Vee or below GND must be limited to either 0.5 V or 10 mA, whichever is
easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this
over- or undershoot lasts less than 20 ns.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
XC4000EX Recommended Operating Conditions
Symbol
Vee
V IH
V IL
TIN
Notes:
4-82
Description
Min
Max
Units
Supply voltage relative to GND, TJ = 0 °C to +85°C
Commercial
4.75
5.25
V
Supply voltage relative to GND, TJ = -40°C to + 100°C
Industrial
4.5
5.5
V
High-level input voltage
TIL inputs
CMOS inputs
Low-level input voltage
Input signal transition time
2.0
Vee
V
70%
100%
Vee
TIL inputs
0
0.8
V
CMOS inputs
0
20%
Vee
250
ns
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
Input and output measurement thresholds for TTL are 1.5 V. Input and output measurement thresholds for CMOS are 2.5 V.
All timing parameters are specified for Commercial temperature range only.
November 10, 1997 (Version 1.4)
~XILINX
XC4000EX DC Characteristics Over Recommended Operating Conditions
Symbol
VOH
Description
Min
= -4.0 mA, Vee min
High-level output voltage @ IOH = -1.0 mA
TTL outputs
= 12.0 mA, Vee min
TTL outputs
High-level output voltage @ IOH
CMOS outputs
VOL
Low-level output voltage @ IOL
(Note 1)
V DR
Data Retention Supply Voltage (below which configuration data may be lost)
leeo
Quiescent FPGA supply current (Note 2)
IL
-10
BGA, SBGA, PQ,
HQ, MQ packages
CIN
PGA packages
IRPD
= 0 V (sample tested)
Pad pull-down (when selected) @ Yin = 5.5 V (sample tested)
IRLL
Horizontal Longline pull-up (when selected) @ logic Low
IRPU
Note 1:
Note 2:
V
0.4
V
0.4
V
3.0
Input or output leakage current
Pad pull-up (when selected) @ Yin
Units
V
Vee-0.5
CMOS outputs
Input capacitance (sample tested)
Max
2.4
V
25
mA
+10
IlA
10
pF
16
pF
0.02
0.25
mA
0.02
0.25
mA
0.3
2.0
mA
With up to 64 pins simultaneously sinking 12 rnA.
With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND.
XC4000EX Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible lOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation nellist. These path delays, provided as a guideline, have been extracted from the static
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature).
-4
-3
-2
-1
Device
Max
Max
Max
Max
From pad through Global Low Skew buffer, T GLS
to any clock K
XC4028EX
XC4036EX
9.2
9.8
7.5
7.9
6.4
7.1
ns
ns
From pad through Global Early buffer,
to any clock K in same quadrant
XC4028EX
XC4036EX
5.7
5.9
4.4
4.6
4.2
4.4
ns
ns
Speed Grade
Description
Symbol
TGE
h":;,';;'::,,'.
November 10, 1997 (Version 1.4)
>,~:
Units
;;;::ii~:
4-83
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000EX Longline and Wide Decoder Timing Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devices unless
otherwise noted. Fewer than the specified number of pullup resistors can be used, if desired. Using fewer pullups reduces
power consumption but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used.
XC4000EX Horizontal Longline Switching Characteristic Guidelines
·4
·3
·2
·1
Max
Max
Max
Max
Speed Grade
Description
Symbol
Device
Units
••:;' .: •.•: .::U.·•.::;>: >:',:.,;","::
',:'
TBUF driving a Horizontal Longline
·,· . ···::··:.:::,·······:······:;.:',.·1;·.·' •.:,·.:···.i:: ii':.:".";;:,
I going High or Low to Horizontal Longline going High
or Low, while T is Low. Buffer is constantly active.
T I01
XC4028EX
XC4036EX
13.7
16.5
11.3
13.6
10.9
13.2
ns
ns
T going Low to Horizontal Longline going from resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low.
TON
XC4028EX
XC4036EX
14.7
17.4
12.1
14.4
11.7
14.0
ns
ns
T going High to Horizontal Longline going from Low to
High, pulled up by two resistors. (Note 1)
T pU2
XC4028EX
XC4036EX
TBUF driving Half a Horizontal Longline
ns
ns
:::~·• ···r. !~::::::.::.·. . . ·.,>:i.:.·•. :·• :·:·;:."'.'.::' >.,::;::,:.'.: . ::;:,: ....:·:·:: •.•·X,:··· . •.:.•'. . . .•.•
I going High or Low to half of a Horizontal Longline go- THI0 1
ing High or Low, while T is Low. Buffer is constantly
active.
XC4028EX
XC4036EX
6.3
7.3
5.6
6.0
4.6
5.7
ns
ns
T going Low to half of a Horizontal Longline going from
resistive pull-up or floating High to active Low. TBUF
configured as open-drain or active buffer with I = Low.
XC4028EX
XC4036EX
7.2
8.2
6.4
6.8
5.4
6.5
ns
ns
THON
T going High to half of a Horizontal Longline going
T HPU4
from Low to High, pulled up by four resistors. (Note 1)
ns
ns
XC4028EX
XC4036EX
· '·>:·:• • ,:i •.•·i~~I!""'!i~..,.:.;:.::: .• '.·>.·
Note:
These values include a minimum load of one output, spaced as far as possible from the activated puliup(s). Use the static
timing analyzer to determine the delay for each destination.
XC4000EX Wide Decoder Switching Characteristic Guidelines
Speed Grade
Description
Symbol
Device
·4
·3
·2
·1
Max
Max
Max
Max
Units
Full length, two pull-ups, inputs from lOB I-pins
TWAF2
XC4028EX
XC4036EX
ns
ns
Full length, two pull-ups, inputs from internal logic
TWAF2L
XC4028EX
XC4036EX
ns
ns
Half length, two pull-ups, inputs from lOB I-pins
TWA02
XC4028EX
XC4036EX
ns
ns
Half length, two pull-ups, inputs from internal logic
TWA02L
XC4028EX
XC4036EX
ns
ns
.. L·~:~:i~r~li""'Jn~:·.
Notes:
4-84
:
These delays are specified from the decoder input to the decoder output.
November 10, 1997 (Version 1.4)
~:XILINX
XC4000EX CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation nellis!. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000EX devices unless otherwise noted.
Speed Grade
-4
-3
Symbol
Min
Max
Min
Max
"''''''''''I'''V''
'"'' Delays
.·:~iW~::t:"r. l',l:H:::]'ti[,1:,) . •• ':'. .':.:'.
FIG inputs to XIV outputs
T ILO
2.2
1.8
FIG inputs via H' to XIV outputs
TIHO
3.8
3.2
FIG inputs via transparent latch to outputs
TITO
3.2
2.7
3.6
3.0
C inputs via SR/HO via H' to XIV outputs
T HHOO
3.0
2.5
C inputs via HI via H' to XIV outputs
THH10
C inputs via. DIN/H2 via H' to XIV outputs
T~H20
3.6
3.0
2.0
1.6
C inputs via EC, DIN/H2 to YO, XO output (bypass) TCBYP
-2
Min
-1
Max
Min
·'::.;:<1: ,·•. •'··';1:1,• ·:.·...:: .,;~::>';',·.·.:i •.••,. •'.,:.....••••
'.' l',·:: " .• 'i,::::· ,JiG::. . : L.·.··;ii:'·· .• ....:'::!' :. ,:":.·r:~'·x :.:',
Clock K to Flip-Flop outputs
Clock K to Latch outputs
a
T OPCY
TASCY
T INCY
TSUM
TBYP
TNET
a
FIG inputs
FIG inputs via H'
C inputs via HO through H'
C inputs via HI through H'
C inputs via H2 through H'
C inputs via DIN
C inputs via EC
C inputs via SIR, going Low (inactive)
CIN input via FIG'
CINinEut via FIG' and H'
FIG inputs
FIG inputs via H'
C inputs via SR/HO through H'
C inputs via HI through H'
C inputs via DIN/H2 through H'
C inputs via DIN/H2
C inputs via EC
I C inputs via SR,going Low (inactive)
Clock High time
Clock Low time
2.2
3.6
1.6
2.6
0.50
0.15
1.9
3.1
1.4
2.2
0.40
0.15
ns
ns
ns
ns
ns
ns
2.2
22
1.9
lB
1.7
lJ
ns
ns
TICK
TIHCK
THHOCK
THH1CK
THH2CK
TDICK
TECCK
TRCK
TCCK
TCHCK
1.3
3.0
2.8
2.2
2.8
1.2
1.2
0.8
2.2
3.9
1.1
2.5
2.3
1.8
2.3
0.9
1.0
0.7
1.8
3.2
1.1
2.2
2.0
1.8
2.0
0.9
0.9
0.6
2.1
3.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCKI
TCKIH
TCKHHO
TCKHH1
TCKHH2
T CKDI
TCKEC
TCKR
a
a
a
a
a
a
a
a
0
0
0
a
ns
ns
ns
ns
ns
ns
ns
ns
3.5
3.5
3.0
3.0
3.0
3.0
ns
ns
TCH
T CL
..,,,,u ,.."',,"', Direct
Width (High)
Delay from C inputs via SIR, going High to
Global ~..., -~Minimum GSR Pulse Width
Delay fromGSR input to any
Delay from GSR input to any
.• •.•:.,...:: ;.l.';,' ,.,ii:' • :' '.:••'.i:
2.5
4.1
1.9
3.0
0.60
0.18
••.~:•.;-,::::......:::;:Tr:.;:,::.;.·L:·r}::.·{n:: ::.·: •.:···.·.·,> • ·.·Li.··; :·;··;·YL:.: .• :. :::!:: ••••
Setup Time before Clock K
i
ns
ns
ns
ns
ns
ns
ns
1 .5
2.7
2.5
2.5
2.3
2.5
1.4
a
Operand inputs (Fl, F2, Gl, G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (Fl, F3) to COUT
CIN through function generators to XIV outputs
CIN to COUT, bypass function generators
Carry Net Delay, COUT to CIN
.., 'd,
Delays
Units
Max
a
a
a
a
0
a
a
f:'.:." •. :):'.'~;';':';XG'E .:·:.i::
a
I :!:RPW
I TRIO
a (XC4028EX)
a iXr.4n~RFX\
I TI
I T~RQ
I TMRQ
0
0
.•:l';" • '
3.0
3.5
a
a
a
••••;:;•• ·.:.,.:...jj~:·::·::.·:·~j:·.f.:·.;·:
3.0
.• .•. •;• :. •. ::.;~.•.
ns
4.5
F:.ij·::.,:,:e:ri·:;::::;;:·::
November 10, 1997 (Version 1.4)
13.0
22.8
24.0
4-85
II
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000EX CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 01605. All devices are 100% functionally tested.
Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more
precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation nellist. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature). Values apply to all XC4000EX devices unless otherwise noted.
Single Port RAM
Write Operation
Address write cycle time (clock K period)
~~
Speed Grade
·4
Units
Min
Max
Min
Max
Min
Max
16x2
32x1
Twcs
TWCTS
11.0
11.0
9.0
9.0
9.0
9.0
ns
ns
Clock K pulse width (active edge)
16x2
32x1
TwPS
TWPTS
5.5
5.5
4.5
4.5
4.5
4.5
ns
ns
Address setup time before clock K
16x2
32x1
TASS
T ASTS
2.7
2.6
2.3
2.2
2.2
2.2
ns
ns
Address hold time after clock K
16x2
32x1
TAHS
TAHTS
0
0
0
0
0
0
ns
ns
DIN setup time before clock K
16x2
32x1
Toss
T OSTS
2.4
2.9
2.0
2.5
2.0
2.5
ns
ns
DIN hold time after clock K
16x2
32x1
T OHS
T OHTS
0
0
0
0
0
0
ns
ns
WE setup time before clock K
16x2
32x1
Twss
TWSTS
2.3
2.1
2.0
1.8
2.0
1.8
ns
ns
WE hold time after clock K
16x2
32x1
TWHS
TWHTS
0
0
0
0
a
a
ns
ns
16x2
32x1
Twos
TwOTS
Data valid after clock K
8.2
10.1
!;';[1L,i(i,ij2",i:/,,,[r
Notes:
6.8
8.4
c;;m:
",
"",,~/
6.8
8.2
ns
ns
ri,'.)'.,··.'·,,···. . :iu..··
Timing for the 16xl RAM option is identical to 16x2 RAM timing,
Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Dual-Port RAM
·4
Speed Grade
·2
·3
·1
Write Operation
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE .setup time before clock K
WE hold time after clock K
Data valid after clock K
Note:
4-86
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
Twcos
Twpos
TASOS
TAHOS
Tosos
T OHOS
Twsos
TWHOS
Twoos
11.0
5.5
3.1
9.0
4.5
2.6
9.0
4.5
2.5
a
a
a
2.9
2.5
2.5
a
a
a
2.1
0
1.8
0
1.8
9.4
a
7.8
7.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
Applicable Read timing specifications are identical to Level-Sensitive Read timing.
November 10, 1997 (Version 1.4)
~XILINX
XC4000EX CLB RAM Synchronous (Edge-Triggered) Write Timing
WCLK(K)
- - - - - - - - - - - - - - - - - - - - - -, I,--""":";;c...::.....-,
WE
TDSS
TDHS
DATA IN
ADDRESS
II
DATA OUT
X6461
XC4000EX CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing
WCLK(K)
- - - - - - - - - - - - - - - - - - - - - -, r - - - - ' - - - , I
TwSOS
WE
Tosos
TOHOS
DATA IN
ADDRESS
DATA OUT
X6474
November 10, 1997 (Version 1.4)
4-87
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000EX CLB RAM Asynchronous (Level-Sensitive) Write and Read Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simUlation netlis!. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000EX devices unless otherwise noted.
Speed Grade
-4
-2
-3
-1
Description
Write Operation
Address write cycle time
16x2
32x1
Twc
TWCT
10.6
10.6
9.2
9.2
8.0
8.0
ns
ns
Write Enable pulse width (High)
16x2
32x1
Twp
TWPT
5.3
5.3
4.6
4.6
4.0
4.0
ns
ns
Address setup time before WE
16x2
32x1
TAS
TAST
2.8
2.9
2.4
2.5
2.0
2.0
ns
ns
Address hold time after end of WE
16x2
32x1
TAH
TAHT
1.7
1.7
1.4
1.4
1.4
1.4
ns
ns
DIN setup time before end of WE
16x2
32x1
Tos
TOST
1.1
1.1
0.9
0.9
0.8
0.8
ns
ns
DIN hold time after end of WE
16x2
32x1
TOH
TOHT
6.6
6.6
5.7
5.7
5.0
5.0
ns
ns
Address read cycle time
16x2
32x1
T RC
TRCT
Data valid after address change
(no Write Enable)
16x2
32x1
TILO
T 1HO
Data valid after WE goes active
(DIN stable before WE)
16x2
32x1
Two
TWOT
Data valid after DIN
(DIN changes during WE)
16x2
32x1
Too
TOOT
Read Operation
Address setup time before clock K
Read During Write
Read During Write, Clocking Data into Flip-Flop
WE setup time before clock K
16x2
32x1
Data setup time before clock K
16x2
32x1
Note:
4-88
TOCK
TOCKT
Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
November 10, 1997 (Version 1.4)
~XILINX
XC4000EX CLB RAM Asynchronous (Level-Sensitive) Timing Characteristics
TWC
ADDRESS
WRITE
WRITE ENABLE
DATA IN
READ WITHOUT WRITE
X,YOUTPUTS
VALID
VALID
READ, CLOCKING DATA INTO FLlP·FLOP
"11 - - - - - - TICK -----cJ·-t1~.0
CLOCK
I
TCH -----I
XQ, YQ OUTPUTS
READ DURING WRITE
~--------TWp---------~
WRITE ENABLE
DATA IN
(stable during WE)
X, YOUTPUTS
DATA IN
(changing during WE)
X, YOUTPUTS
READ
D:R~:~:N:~~TE' CLOCKING DATA INTO It:L~IP=.F=L=O=P=T=W=C=K=_=_=_=_=~=- ;=~~TW~P':.-=:========4.~~____
DATA IN
CLOCK
XQ, YQ OUTPUTS
X2640
November 10,1997 (Version 1.4)
4·89
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000EX Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38S10/60S. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation nellist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all XC4000EX devices unless otherwise noted.
XC4000EX Output Flip-Flop, Clock to Out
Units
Global Low Skew Clock to TTL
Output (fast) using OFF
ns
ns
Global Early Clock to TTL Output (fast) using
OFF
ns
ns
OFF = Output Flip Flop
XC4000EX Output MUX, Clock to Out
Units
Global Low Skew Clock to TTL
Output (fast) using OMUX
Global Early Clock to TTL Output (fast) using OMUX
ns
ns
TPEFPF
XC4028EX
XC4036EX
12.4
12.6
10.0
10.2
ns
ns
OMUX = Output MUX
Notes:
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible lOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at TTL threshold with 35 pF external capacitive load.
Set-up time is measured with the fastest route and the lightest load. Hold time is measured using the farthest distance and a
reference load of one clock pin per two lOBs. Use the static timing analyzer to determine the setup and hold times under given
design conditions.
XC4000EX Output Level and Slew Rate Adjustments
The following table must be used to adjust output parameters and output switching characteristics.
4-90
November 10, 1997 (Version 1.4)
~XILINX
XC4000EX Pin-ta-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all XC4000EX devices unless otherwise noted
XC4000EX Global Low Skew Clock, Set-Up and Hold
Description
Input Setup Time, using Global Low Skew
clock and IFF (full delay)
Input Hold Time, using Global Low Skew
clock and IFF (full delay)
IFF - Flip-Flop or Latch
Symbol
TpSD
TpHD
-2
Min
6.8
6.8
0
0
•.•. '. f'~elj(l1~nary ....
Speed Grade
Device
XC4028EX
XC4036EX
XC4028EX
XC4036EX
-4
Min
8.0
8.0
0
0
-3
Min
6.8
6.8
0
0
-4
Min
6.5
6.5
0
0
-3
Min
5.4
5.4
0
0
-1
Min
Units
ns
ns
ns
ns
XC4000EX Global Early Clock, Set-Up and Hold for IFF
Description
Input Setup Time, using Global Early clock
and IFF (partial delay)
Input Hold Time, using Global Early clock
and IFF (partial delay)
IFF - Flip-Flop or Latch
Note:
Symbol
T psEP
T pHEP
Speed Grade
Device
XC4028EX
XC4036EX
XC4028EX
XC4036EX
-2
Min
5.4
5.4
0
0
-1
Min
Units
ns
ns
ns
ns
•• .•>J.t~!i:mi1JatY:} .
Set-up parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.6 ns for BUFGE #s 1, 2, 5 and 6.
XC4000EX Global Early Clock, Set-Up and Hold for FCL
Description
Input Setup Time, using Global Early clock
and FCL (partial delay)
Input Hold Time, using Global Early clock
and FCL (partial delay)
FCL = Fast Capture Latch
Notes:
Speed Grade
Device
XC4028EX
TpFSEP
XC4036EX
XC4028EX
TpFHEP
XC4036EX
Symbol
-4
Min
3.4
4.4
0
0
...
-3
Min
3.4
4.2
0
0
••, .f'relimii1ary
-2
Min
3.4
4.2
0
0
-1
Min
Units
ns
ns
ns
ns
.......
For CMOS input levels, see the "XC4000EX Input Threshold Adjustments" on page 4·91.
Setup time is measured with the fastest route and the lightest load. Use the static timing analyzer to determine the setup time
under given design conditions. Hold time is measured using the farthest distance and a reference load of one clock pin per two
lOBs. Use the static timing analyzer to determine the setup and hold times under given design conditions.
Note:Set-up parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.2 ns for BUFGE #s 1,2,5 and 6.
XC4000EX Input Threshold Adjustments
The following table must be used to adjust input parameters and input switching characteristics.
-4
-3
-2
-1
Max
Max
Max
Max
TTTU
Device
All Devices
0
0
0
ns
TCMOSI
All Devices
0.3
0.2
0.2
ns
Speed Grade
Description
For TTL input add
For CMOS input add
November 10, 1997 (Version 1.4)
Symbol
........
Units
Pr~li(l1matY: : . . )
4-91
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000EX lOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devices unless
otherwise noted.
Delay from FCL enable (OK) active edge to IFF
clock (IK) active edge
Propagation Delays
Pad to 11, 12
Pad to 11, 12 via transparent input latch, no delay
Pad to 11, 12 via transparent input latch,
partial delay
Pad to 11, 12 via transparent input latch, full delay
All devices
3.2
2.6
2.6
TPID
T PLI
TPPLI
All devices
All devices
XC4028EX
XC4036EX
XC4028EX
XC4036EX
All devices
Max
2.2
3.8
13.3
14.5
18.2
19.4
5.3
Max
1.9
3.2
11.1
12.1
15.2
16.2
4.4
Max
1.8
3.0
10.9
11.9
14.9
15.9
4.2
XC4028EX
XC4036EX
13.6
14.8
11.3
12.3
11.1
12.1
ns
ns
All devices
All devices
All devices
3.0
3.2
6.2
2.5
2.7
5.2
2.4
2.6
5.0
ns
ns
ns
All devices
XC4028EX
XC4036EX
13.0
22.8
24.0
11.5
19.0
21.0
11 .5
19.0
21.0
ns
ns
ns
TpDLI
Pad to 11, 12 via transparent FCL and input latch, T PFLI
no delay
Pad to 11, 12 via transparent FCL and input latch, T PPFLI
partial delay
Propagation Delays
Clock (IK) to 11, 12 (flip-flop)
TIKRI
Clock (IK) to 11, 12 (latch enable, active Low)
TIKLI
FCL Enable (OK) active edge to 11, 12
T OKLI
(via transparent standard input latch)
Global Set/Reset
Minimum GSR Pulse Width
T MRW
Delay from GSR input to any Q
T RRI
Delay from GSR input to any Q
T RRI
FCL Fast Capture Latch, IFF - Input Flip-Flop or Latch
Notes:
4-92
ns
TOKIK
Max
ns
ns
ns
ns
ns
ns
ns
Ii;::;;::.::::':'::;;;'
For CMOS input levels, see the "XC4000EX Input Threshold Adjustments" on page 4-91.
For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Set-up and
Hold tables on page 4-91.
November 10, 1997 (Version 1.4)
~XILINX
XC4000EX lOB Input Switching Characteristic Guidelines (Continued)
Testing of switching parameters is modeled aftertesting methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devices unless
otherwise noted.
10.2
11.2
0.7
3.3
ns
ns
ns
ns
ns
10.2
11.2
0.7
ns
ns
ns
ns
ns
All devices
All devices
All devices
0
0
0
0
0
0
0
0
0
ns
ns
ns
All devices
All devices
All devices
0
0
0
0
0
0
0
0
0
ns
ns
ns
All devices
All devices
All devices
0
0
0
0
0
0
0
ns
ns
ns
All devices
All devices
0
0
0
0
0
ns
ns
0
0
0
Notes: For CMOS input levels, see the "XC4000EX Input Threshold Adjustments" on page 4-91.
For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Set-up and
Hold tables on page 4-91.
November 10, 1997 (Version 1.4)
4-93
II
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000EX lOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters .assume
worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless
otherwise noted. Values apply to all XC4000EX devices unless otherwise noted.
Units
Clock (OK) to Pad
Output (0) to Pad
3-state to Pad hi-Z (slew-rate independent)
3-state to Pad active and valid
Output MUX Select (OK) to Pad
Fast Path Output MUX Input (EC) to Pad
Slowest Path Output MUX Input (0) to Pad
TOKPOF
TOPF
TTSHZ
TTSONF
TOKFPF
TCEFPF
TOFPF
7.4
6.2
4.9
6.2
6.7
6.2
7.3
6.2
5.2
4.1
5.2
5.6
5.1
6.0
6.0
5.0
4.1
5.0
5.4
5.0
5.9
ns
ns
ns
ns
ns
ns
ns
Minimum GSR pulse width
Delay from GSR input to any Pad (XC4028EX)
Delay from GSR input to any Pad (XC4036EX)
Notes:
4-94
Output timing is measured at TTL threshold, with 35pF external capacitive loads.
For CMOS output levels, see the "XC4000EX Output Level and Slew Rate Adjustments" on page 4-90.
November 10, 1997 (Version 1.4)
~XILINX
XC4000E Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:
Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device
families. Use as estimates, not for production.
Preliminary:
Based on preliminary characterization. Further changes are not expected.
Unmarked:
Specifications not identified as either Advance or Preliminary are to be considered Final. 1
XC4000E Absolute Maximum Ratings
Symbol
Description
Value
Vee
V IN
Supply voltage relative to GND
VTS
Voltage applied to 3-state output (Note 1)
TSTG
Storage temperature (ambient)
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
Input voltage relative to GND (Note 1)
TSOL
TJ
Note 1:
Note 2:
-0.5 to +7.0
Junction temperature
-0.5 to Vee +0.5
-0.5 to Vee +0.5
-65 to +150
Units
V
V
V
°C
+260
°C
ICeramic packages
+150
°C
I Plastic packages
+125
°C
Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is
easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this
over- or undershoot lasts less than 20 ns.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
XC4000E Recommended Operating Conditions
Vee
Symbol
Supply voltage relative to GND, TJ = -0 °C to +85°C
Commercial
Min
4.75
Industrial
4.5
Military
4.5
5.5
V IH
Supply voltage relative to GND, TJ = -40°C to + 100°C
Supply voltage relative to GND, Te = -55°C to + 125°C
High-level input voltage
Max
5.25
5.5
TTL inputs
2.0
Low-level input voltage
70%
0
Vee
100%
V IL
CMOS inputs
TTL inputs
CMOS inputs
0
TIN
Input signal transition time
Note:
Description
0.8
20%
250
Units
V
V
V
V
Vee
V
Vee
ns
At junction temperatures above those listed as Recommended Operating Conditions, all delay parameters increase by
0.35% per DC.
Input and output Measurement thresholds are: 1.5V for TTL and 2.5V for CMOS.
1. Notwithstanding the definition of the above terms, all specifications are subject to change without notice.
November 10, 1997 (Version 1.4)
4-95
II
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000E DC Characteristics Over Operating Conditions
Symbol
VOH
VOL
Description
High-level output voltage @ IOH = -4.0mA, Vee min
High-level output voltage @ IOH = -1.0mA, Vee min
Low-level output voltage @ IOL = 12.0mA, Vee min
(Note 1)
leeo
Quiescent FPGA supply current (Note 2)
IL
CIN
Input or output leakage current
Input capacitance (sample tested)
IRIN"
IRLL"
Pad pull-up (when selected) @ V IN = OV (sample tested)
Horizontal Longline pull-up (when selected) @ logic Low
Note 1:
Note 2:
Min
2.4
TTL outputs
CMOS outputs
TTL outputs
CMOS outputs
Commercial
Industrial
Military
Max
Vee-0.5
0.4
0.4
3.0
6.0
6.0
-10
PQFP and MQFP
packages
Other packages
-0.02
0.2
Units
V
V
V
V
mA
mA
mA
+10
10
!!A
16
-0.25
2.5
pF
mA
mA
pF
With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins.
With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA
configured with a Development system Tie option.
Characterized Only.
XC4000E Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible lOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature)
Description
From pad through
Primary buffer,
to any clock K
From pad through
Secondary buffer,
to any clock K
Symbol
TpG
TSG
Speed Grade
Device
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
·4
Max
7.0
7.0
7.5
8.0
11.0
11.5
12.0
12.5
7.5
7.5
8.0
8.5
11.5
12.0
12.5
13.0
·3
·2
·1
Max
4.7
4.7
5.3
6.1
6.3
6.8
7.0
7.2
5.2
5.2
5.8
6.6
6.8
7.3
7.5
7.7
Max
4.0
4.3
5.2
5.2
5.4
5.8
6.4
6.9
4.4
4.7
5.6
5.6
5.8
6.2
6.7
7.2
Max
3.5
3.8
4.6
4.6
4.8
5.2
6.0
4.0
4.3
5.1
5.1
5.3
5.7
6.5
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
:'Btic'~Ji,lil!'~]:
4-96
November 10, 1997 (Version 1.4)
~XILINX
XC4000E Horizontal Longline Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
The following guidelines reflect worst-case values over the recommended operating conditions.
Description
TBUF driving a Horizontal Longline (LL):
I going High or Low to LL going High or
Low, while T is Low.
Buffer is constantly active.
(Note1 )
I going Low to LL going from resistive
pull-up High to active Low.
TBUF configured as open-drain.
Speed Grade
Symbol Device
;>}:'">;> :.........:?
(Note1 )
Units
::.....
4.2
5.0
5.9
6.3
6.4
7.2
8.2
9.1
3.4
4.0
4.7
5.0
5.1
5.7
7.3
7.3
2.9
3.4
4.0
4.3
4.4
4.9
5.6
T I02
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
5.0
6.0
7.8
8.1
10.5
11.0
12.0
12.0
4.2
5.3
6.4
6.8
6.9
7.7
8.7
9.6
3.6
4.5
5.4
5.8
5.9
6.5
8.7
9.6
3.1
3.8
4.6
4.9
5.0
5.5
7.4
TON
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
5.5
7.0
7.5
8.0
8.5
8.7
11.0
11.0
4.6
6.0
6.7
7.1
7.3
7.5
8.4
8.4
3.9
5.7
5.7
6.0
6.2
7.0
7.1
7.1
3.5
4.7
4.9
5.2
5.4
6.2
6.3
-
ns
ns
ns
ns
ns
ns
ns
ns
TOFF
All devices
1.8
1.5
1.3
1.1
ns
Tpus
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
20.0
23.0
25.0
27.0
29.0
32.0
35.0
42.0
14.0
16.0
18.0
20.0
22.0
26.0
32.5
39.1
14.0
16.0
18.0
20.0
22.0
26.0
32.5
39.1
12.0
14.0
16.0
16.0
18.0
21.0
26.0
ns
ns
ns
ns
ns
ns
ns
ns
T pUF
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC40.13E
XC4020E
XC4025E
9.0
10.0
11.5
12.5
13.5
15.0
16.0
18.0
7.0
8.0
9.0
10.0
11.0
13.0
14.8
16.5
6.0
6.8
7.7
8.5
9.4
11.7
14.8
16.5
5.4
5.8
6.5
7.5
8.0
9.4
10.5
(Note 1)
T going High to LL going from Low to
High, pulled up by two resistors.
..
I
5.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
(Note1)
T going High to TBUF going inactive,
not driving LL
T going High to LL going from Low to
High, pulled up by a single resistor.
-1
Max
.....:/<
:.
I
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
T I01
(Note1)
T going Low to LL going from resistive
pull-up or floating High to active Low.
TBUF configured as open-drain or active
buffer with I = Low.
-4
-2
-3
Max
Max
Max
' : : " . .:::::::'
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
.E'r~lilP"fl\a!'Y .
Note 1:
These values include a minimum load. Use the static timing analyzer to determine the delay for each destination.
November 10, 1997 (Version 1.4)
4-97
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000E Wide Decoder Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation nellis!. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
The following guidelines reflect worst-case values over the recommended operating conditions.
Description
Symbol
Full length, both pull-ups,
inputs from lOB I-pins
TWAF
Full length, both pull-ups,
inputs from internal logic
TWAFL
Half length, one pull-up,
inputs from lOB I-pins
TWAO
Half length, one pull-up,
inputs from internal logic
TWAOL
-
Notes:
4-98
Speed Grade
Device
-3
Max
-2
-1
Max
Max
Max
Units
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
9.2
9.5
12.0
12.5
15.0
16.0
17.0
18.0
12.0
12.5
14.0
16.0
18.0
19.0
20.0
21.0
10.5
10.5
13.5
14.0
16.0
17.0
18.0
19.0
12.0
12.5
14.0
16.0
18.0
19.0
20.0
21.0
5.0
6.0
7.0
8.0
9.0
11.0
13.9
16.9
7.0
8.0
9.0
10.0
11.0
13.0
15.5
18.9
6.0
7.0
8.0
9.0
10.0
12.0
15.0
17.6
8.0
9.0
10.0
11.0
12.0
14.0
16.8
19.6
5.0
6.0
7.0
8.0
9.0
11.0
13.9
16.9
7.0
8.0
9.0
10.0
11.0
13.0
15.5
18.9
6.0
7.0
8.0
9.0
10.0
12.0
15.0
17.6
8.0
9.0
10.0
11.0
12.0
14.0
16.8
19.6
4.3
5.1
6.0
6.5
7.5
8.6
10.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-4
5.5
6.4
7.0
7.5
8.5
10.0
11.8
5.1
6.0
6.5
7.0
7.5
10.0
11.8
6.0
7.0
7.6
8.4
9.2
10.8
12.6
:,~~J~~~~:
These delays are specified from the decoder input to the decoder output.
Fewer than the specified number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption
but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used.
November 10, 1997 (Version 1.4)
~XILINX
XC4000E CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRGE in the Xilinx Development System) and back-annotated to the simulation nellis!. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XG4000E devices unless
otherwise noted.
ns
ns
ns
ns
Operand inputs (F1,
G1, G4) to
AddlSubtract input (F3) to GOUT
Initialization inputs (F1, F3) to GOUT
GIN through function generators to
XIY outputs
GIN to GOUT, bypass function generators
FIG inputs
FIG inputs via H
G inputs via HO through H
G inputsvia H1 through H
G inputs. via H2 throughH
G inputs via DIN
G inputs via EG
G inputs via SIR, going Low (inactive)
GIN input via FIG
GIN input via FIG and H
November 10, 1997 (Version 1.4)
2.6
4.4
1.7
3.3
2.1
3.7
1.4
2.6
1.7
2.5
1.2
1.8
ns
ns
ns
ns
0.7
TICK
T IHCK
THHOCK
THH1CK
THH2CK
T OICK
T ECCK
T RCK
TCCK
T CHCK
4.0
6.1
4.5
5.0
4.8
3.0
4.0
4.2
2.5
4.2
4.6
3.6
4.1
3.8
2.4
3.0
4.0
2.1
3.5
2.4
3.9
3.5
3.3
3.7
2.0
2.6
4.0
1.8
2.8
2.4
2.1
2.5
1.0
2.0
1.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4-99
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000E CLB Switching Characteristic Guidelines (continued)
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
FIG inputs
FIG inputs via H
C inputs via HO through H
C inputs via H1 through H
inputs via H2 through H
C inputs via DIN
C inputs via EC
inputs via SR, going Low (inactive)
TCKI
TCKIH
TCKHHO
TCKHHI
TCKHH2
TCKDI
T CKEC
T
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
3.0
3.0
ns
ns
3.0
3.0
Note 1:
Note 2:
4-100
ns
ns
Timing is based on the XC4005E. For other devices see the static timing analyzer.
Export Control Max. flip-flop toggle rate.
November 10, 1997 (Version 1.4)
l::XILINX
XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100% functionally tested.
Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more
precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature). Values apply to all XC4000E devices unless otherwise noted.
Single Port RAM
Write Operation
Address write cycle time (clock K period)
16x2 Twcs
32x1 T WCTS
15.0
15.0
Clock K pulse width (active edge)
16x2 TwPS
32x1 T WPTS
7.5
7.5
Address setup time before clock K
16x2 TASS
32x1 TASTS
2.8
2.8
Address hold time after clock K
16x2 TAHS
32x1 TAHTS
DIN setup time before clock K
11.6
11.6
8.0
8.0
ns
ns
5.8 1 ms
5.8 ·1 ms
4.0
4.0
ns
ns
2.4
2.4
2.0
2.0
1.5
1.5
ns
ns
0
0
0
0
0
0
0
0
ns
ns
16x2 T DSS
32x1 TDSTS
3.5
2.5
3.2
1.9
2.7
1.7
1.5
1.5
ns
ns
DIN hold time after clock K
16x2 T DHS
32x1 TDHTS
0
0
0
0
0
0
0
0
ns
ns
WE setup time before clock K
16x2 Twss
32x1 T WSTS
2.2
2.2
2.0
2.0
1.6
1.6
1.5
1.5
ns
ns
WE hold time after clock K
16x2 T WHS
32x1 T WHTS
0
0
0
0
o.
0
0
0
ns
ns
Data valid after clock K
Notes:
16x2 Twos
32x1 T WOTS
14.4
14.4
1 ms
1 ms
7.2
7.2
1 ms
1 ms
8.8
10.3
10.3
11.6
7.9
9.3
6.5
7.0
ns
ns
6.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing for the 16xl RAM option is identical to 16x2 RAM timing.
Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Dual-Port RAM
Write Operation
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
Note:
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
TWCDS
T WPDS
T ASDS
T AHDS
T DSDS
T DHDS
T WSDS
T WHDS
T WODS
15.0
1 ms
7.5
2.8
0
2.2
0
2.2
0.3
9.0
4.5
2.5
0
2.5
0
1.8
0
10.0
1 ms
7.8
11.6
5.8 1 ms
2.1
0
1.6
0
1.6
0
7.0
8.0
4.0
1.5
0
1.5
0
1.5
0
Applicable Read timing specifications are identical to Level-Sensitive Read timing.
November
10, 1997 (Version 1.4)
4-101
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000E CLB RAM Synchronous (Edge-Triggered) Write Timing
--- - --- ------ - - ------ -\Ir--"':':;~-"'"\
WCLK(K} __________-JI
WE
DATA IN
ADDRESS
DATA OUT
X6461
XC4000E CLBDual-Port RAM Synchronous (Edge-Triggered) Write Timing
WCLK (K) - - - - - - - - - - - - - - - - - - - - - - \
TWSDS
WE
TDSDS
DATA IN
ADDRESS
DATA OUT
X6474
4-102
November 10, 1997 (Version 1.4)
~XILINX
XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000E devices unless otherwise noted.
Speed Grade
-2
-3
-4
-1
Description
Write Operation
Address write cycle time
16x2
32x1
Twc
TWCT
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
ns
ns
Write Enable pulse width (High)
16x2
32x1
Twp
TWPT
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
ns
ns
Address setup time before WE
16x2
32x1
TAS
TAST
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
Address hold time after end of WE
16x2
32x1
TAH
TAHT
2.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
DIN setup time before end of WE
16x2
32x1
Tos
TOST
4.0
5.0
2.2
2.2
0.8
0.8
0.8
0.8
ns
ns
DIN hold time after end of WE
16x2
32x1
T OH
TOHT
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
Address read cycle time
16x2
32x1
T RC
T RCT
Data valid after address change
(no Write Enable)
16x2
32x1
T llO
TIHO
Data valid after WE goes active (DIN
stable before WE)
16x2
32x1
Two
TWOT
Data valid after DIN
(DIN changes during WE)
16x2
32x1
Too
TOOT
7.0
8.0
5.2
6.2
4.4
5.3
Read Operation
Address setup time before clock K
Read During Write
Read During Write, Clocking Data into J=lip,Flop
WE setup time. before clock K
16x2
32x1
TWCK
TWCKT
Data setup time before clock K
16x2
32x1
T OCK
T OCKT
Note:
Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
November 10, 1997 (Version 1.4)
4-103
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000E CLB Level-Sensitive RAM Timing Characteristics
ADDRESS
WRITE
WRITE ENABLE
DATA IN
READ WITHOUT WRITE
X,YOUTPUTS
VALID
VALID
READ, CLOCKING DATA INTO FLIP-FLOP
i"'1-0----CLOCK
XQ, YQ OUTPUTS
READ DURING WRITE
-1-1...-
TICK - - - -....
TCH--+I
~I___________
------------1
iiiii
TCKO
VALID
__~_~(O~L~D)_______
VALID
~_ _ _~(N_E_W~)_ _ __
~--------TWp---------~
WRITE ENABLE
DATA IN
(stable during WE)
X, YOUTPUTS
DATA IN
(changing during WE)
NEW
VALID
(NEW)
X, YOUTPUTS
READ
D:::~:N:~~TE' CLOCKING DATA INTO ll.L1:::P=-F=L~O:P=T=W=C=K=_=_=_=_=_= ~~TW~P========~.~~
_=
_ ___
DATA IN
CLOCK
XQ, YQ OUTPUTS
X2640
4-104
November 10, 1997 (Version 1.4)
~XILINX
XC4000E Guaranteed Input and Output Parameters (Pin-ta-Pin, TTL I/O)
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted.
-4
-3
-2
-1
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
12.5
14.0
14.5
15.0
16.0
16.5
17.0
17.0
10.2
10.7
10.7
10.8
10.9
11.0
11.0
12.6
8.7
9.1
9.1
9.2
9.3
9.4
10.2
10.8
5.8
6.2
6.4
6.6
6.8
7.2
7.4
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
16.5
18.0
18.5
19.0
20.0
20.5
21.0
21.0
14.0
14.7
14.7
14.8
14.9
15.0
15.1
15.3
11.5
12.0
12.0
12.1
12.2
12.8
12.8
13.0
7.8
8.2
8.4
8.6
8.8
9.2
9.4
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
2.5
2.0
1.9
1.4
1.0
0.5
0
0
2.3
1.2
1.0
0.6
0.2
0
0
0
2.3
1.2
1.0
0.6
0.2
0
0
0
1.5
0.8
0.6
0.2
0
0
0
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
4.0
4.6
5.0
6.0
6.0
7.0
7.5
8.0
4.0
4.5
4.7
5.1
5.5
6.5
6.7
7.0
4.0
4.5
4.7
5.1
5.5
5.5
5.7
5.9
1.5
2.0
2.0
2.5
2.5
3.0
3.5
Speed Grade
Description
Global Clock to Output
(fast) using OFF
~
G;obal Clock-to-Output Delay
Symbol
Device
TICKOF
(Max)
:
X3202
Global Clock to Output
(slew-limited) using OFF
T 1CKO
~
Global Clock-tO-Output Delay
(Max)
:
X3202
Input Setup Time, using IFF
(no delay)
Input
set, uf
Hold
Time
TpSUF
=0
1 -
T
(Min)
- IFF
PG
~
,=,
Input Hold Time, using IFF
(no delay)
Input
set,uf
1
Hold
TpHF
~
T
_
(Min)
IFF
PG
Time
Input Setup Time, using IFF
(with delay)
Input
Set,Uf
Hold
Time
=0-,
=0
1-
T
Tpsu
(Min)
- IFF
PG
Input Hold Time, using IFF
(with delay)
Input
set, uf
Hold
Time
1
TpH
(Min)
T'FF
PG
X3:l01
OFF = Output Flip-Flop
-
-
-
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
8.5
8.5
8.5
8.5
8.5
8.5
9.5
9.5
7.0
7.0
7.0
7.0
7.0
7.0
7.0
7.6
6.0
6.0
6.0
6.0
6.0
6.0
6.8
6.8
5.0
5.0
5.0
5.0
5.0
5.0
5.0
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IFF = Input Flip-Flop or Latch
November 10, 1997 (Version 1.4)
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f:?t~!"'ij~9~
4-105
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000E lOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted.
Pad to 11, 12
Pad to 11 , 12 via transparent
latch, no delay
with delay
Pad to 11,12
Pad to 11, 12 via transparent
latch, no delay
with delay
Clock (IK) to 11, 12 (flip-flop)
Clock (IK) to 11, 12
(latch enable, active Low)
Note 1:
Note 2:
4-106
TplD
All devices
3.0
2.5
2.0
1.4
ns
T pLi
T pDLI
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
4.8
10.4
10.8
10.8
10.8
11.0
11.4
13.8
13.8
3.6
9.3
9.6
10.2
10.6
10.8
11.2
12.4
13.7
3.6
6.9
7.4
8.1
8.2
8.3
9.8
11.5
12.4
2.8
6.4
6.5
6.9
7.0
7.3
8.4
9.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.5
4.1
1.9
ns
8.8
16.5
16.5
16.8
17.3
17.5
18.0
20.8
20.8
6.8
12.4
13.2
13.4
13.8
14.0
14.4
15.6
15.6
3.3
6.9
7.0
7.4
7.4
7.8
9.0
9.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
T pLiC
T pDLlC
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
6.2
11.0
11.9
12.1
12.4
12.6
13.0
14.0
14.0
2.8
TIKRI
TIKLI
All devices
6.2
4.0
3.9
T IKPI
TIKPID
All devices
All devices
0
0
0
0
0
0
0
0
ns
ns
TIKEC
TIKECD
All devices
All devices
1.5
0
1.5
0
0.9
0
0
0
ns
ns
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pullup (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
November 10, 1997 (Version 1.4)
~XlllNX
XC4000E lOB Input Switching Characteristic Guidelines (continued)
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation nellist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
Description
Setup Times (TTL Inputs)
Pad to Clock (IK),
no delay
with delay
Speed Grade
Symbol
Device
T plCK
T PICKD
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
Min
4.0
10.9
10.9
10.9
11.1
11.3
11.8
14.0
14.0
Max
::;.;': .;
-1
Max
.:;: .... ::
Min
Max
I
T ECIK
TECIKD
I: . .
Delay from GSR net
through Q to 11, 12
GSR width
GSR inactive to first active
Clock (IK) edge
i
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
•• : : :
1.5
4.8
5.1
5.8
5.8
6.0
7.6
8.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
"".: .: . :i""';: ....::' . .
'
6.0
12.0
12.0
12.3
12.8
13.0
13.5
16.0
16.0
3.3
8.8
9.7
9.9
10.3
10.5
10.9
12.1
12.1
2.4
6.9
8.0
8.1
8.2
8.3
10.0
12.1
12.1
2.4
5.3
5.6
6.3
6.3
6.5
7.9
8.1
3.5
10.4
10.4
10.4
10.4
10.7
11.1
14.0
14.0
2.5
8.1
8.5
9.1
9.5
9.7
10.1
11.3
11.3
2.1
4.3
5.6
6.7
6.9
7.1
9.0
10.6
11.0
1.5
4.3
5.0
6.0
6.0
6.5
8.0
9.0
...
-
TRRI
T MRW
TMRI
13.0
7.8
11.5
11.5
:. ..
:
ns
ns
ns
ns
ns
ns
ns
ns
ns
.::.;,:- ...•.
'.' >':':
6.8
6.8
I
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
i;:: :~: :::.;.::':.•• :. ........•.. : i.: ..; . , i::: .:.;
12.0
Units
.'i;:ii·;:::::• .':.;::,.
2.0
6.0
6.1
6.2
6.3
6.4
7.9
9.4
10.0
2.6
8.2
8.7
9.2
9.6
9.8
10.2
11.4
11.4
<.;::::':;{i: • •• :
Min
I'·;::i><::':';:·"; .::; :'i:' :. }i.::·:i;i; .....i.: ...·.. ": :::..' '. .'.'.... :" . .,:;';'):.:'::. ii·.·.
Clock Enable (EC) to Clock
(IK), no delay
with delay
Global SetlReset (Note 3)
-2
-3
Max
I·::i'.i'
Setup Time (CMOS Inputs) ·'::;.i·;> ·.;:.;:i:i:·::
1---- Pad to Clock (IK), no delay
TplCKC All devices
with delay T PICKDC XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
(TTL or CMOS)
-4
Min
10.0
..
ns
ns
Prejifjlilia.",
Note 1:
Note 2:
Note 3:
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the ciock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pullup (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Timing is based on the XC4005E. For other devices see the XACT timing calculator.
November 10, 1997 (Version 1.4)
4-107
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000E lOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlis!. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
Units
Description
Propagation Delays
(TTL Output Levels)
Clock (OK) to Pad, fast
slew-rate limited
Output (0) to Pad, fast
slew-rate limited
3-state to Pad hi-Z
(slew-rate independent)
3-state to Pad active
and valid, fast
slew-rate limited
Propagation Delays
(CMOS Output Levels)
Clock (OK) to Pad, fast
slew-rate limited
Output (0) to Pad, fast
slew-rate limited
3-state to Pad hi-Z
(slew-rate independent)
3-state to Pad active
and valid, fast
slew-rate limited
Note 1:
Note 2:
4-108
TOKPOF
TOKPOS
TOPF
Tops
TrsHz
12.0
5.0
B.5
4.2
9.7
13.7
8.1
11.1
4.8
7.3
3.8
3.2
5.2
3.0
ns
ns
ns
ns
ns
6.8
8.8
ns
ns
TOKPOFC
TOKPOSC
T OPFC
Topsc
TrSHZC
10.0
14.0
5.2
9.7
13.4
4.3
12.1
3.9
6.0
3.9
ns
ns
ns
ns
ns
TrsoNFc
TrsoNsc
9.1
13.1
7.6
11.4
6.8
10.2
6.8
8.8
ns
ns
Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
riselfall times are approximately two times longer than fast output riselfall times. For the effect of capacitive loads on ground
bounce, see the "Additional XC4000 Data" section of the Programmable Logic Data Book.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pullup (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
November 10, 1997 (Version 1.4)
~XILINX
XC4000E lOB Output Switching Characteristic Guidelines (continued)
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation nellist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless
otherwise noted. Values apply to all XC4000E devices unless otherwise noted.
Output (0) to clock (OK)
setup time
Output (0) to clock (OK)
hold time
Clock Enable (EC) to
clock (OK) setup
Clock Enable (EC) to
clock
hold
ns
ToKO
a
a
a
a
ns
TECOK
4.8
3.5
2.7
2.0
ns
TOKEC
1.2
1.2
0.5
a
ns
13.0
11.5
11.5
ns
GSR inactive to first active
clock (OK) edge
Note 1:
Note 2:
Note 3:
Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground
bounce, see the "Additional XC4000 Data" section of the Programmable Logic Data Book.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the .internal pullup (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Timing is based on the XC4005E. For other devices see the XACT timing calculator.
November 10, 1997 (Version 1.4)
4-109
I
XC401l0E and XC4000X Series Field Programmable Gate Arrays
4-110
November 10, 1997 (Version 1.4)
~XILINX
Device-Specific Pinout Tables
Device-specific tables include all packages for each XC4000 and XC4000X Series device. They follow the pad locations
around the die, and include boundary scan register locations ..
Pin Locations for XC4003E Devices
XC4003E
Pad Name
VCC
1/0 (A8)
1/0 (A9)
110
1/0
1/0 (Ala)
1/0 (All)
1/0 (A12)
1/0 (A13)
1/0 (A14)
1/0, SGCKl (A15)
VCC
GNO
110, PGCKl (A16)
1/0 (A17)
I/O,TDI
I/O,TCK
I/O,TMS
I/O
1/0
I/O
1/0
1/0
GNO
VCC
110
1/0
1/0
I/O
1/0
VO
1/0
110
1/0
1/0, SGCK2
O(Ml)
GND
I (MQ)
VCC
I (M2)
VO, PGCK2
1/0 (HOC)
1/0
I/O(LDC)
1/0
1/0
I/O
1/0
1/0
1/0 (lNTI')
PC84
PQ100
VQ100
PG120
P2
P3
P4
P92
P93
P94
P95
P96
P97
P98
P99
Pl00
Pl
P2
P3
P4
P5
P6
P7
P8
P9
Pl0
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
Pl00
Pl
P2
P3
P4
P5
P6
P7
G3
Gl
Fl
El
F2
F3
01
Cl
02
C2
OS
C3
C4
82
83
C5
84
B5
Pll
P12
P13
P14
P1S
P1S
P17
P18
P8
P9
Pl0
Pl1
P12
P13
P14
P15
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P3S
P36
P37
P38
PS9
P40
P41
P42
P43
P44
P45
P46
P1B
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P3S
P37
pa8
P39
P40
P41
P42
P43
P5
P6
P7
P8
P9
Pl0
Pl1
P12
P13
P14
P15
P16
P17
P18
M
P19
P20
P21
P22
P23
P24
-
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
vcc
P42
GNO
1/0
1/0
VO
1/0
VO
P43
P44
P45
-
P46
..
November 10; 1997 (Version 1.4)
1
C6
A5
B6
A6
B7
C7
A7
A8
A9
B8
C8
Ala
B9
All
C9
A12
Bl1
Cl0
Cll
011
812
C12
A13
012
C13
E12
013
Fll
E13
F12
F13
G12
Gll
G13
H13
J13
H12
Hll
BndryScan
32
35
38
41
44
47
50
53
56
59
62
65
68
71
74
77
80
83
86
89
92
95
98
101
104
107
110
113
116
119
122
125
126
127
130
133
136
139
142
1,45
148
151
154
XC4003E
Pad Name
1/0
1/0
1/0
1/0
VO,SGCK3
GNO
OONE
VCC
PROGRAM
1/0(07)
VO, PGCK3
1/0(06)
VO
1/0(05)
I/O(CSO)
1/0
1/0
1/0 (04)
1/0
VCC
GNO
1/0(03)
1/0 l'TS)
1/0
1/0
1/0 (02)
VO
VO(Ol)
PC84
PQ100
VQ100
PG120
BndryScan
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P47
P48
P49
P50
PSl
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
PS6
P67
P68
P69
P70
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
PBl
P62
P63
P64
P65
P66
P67
172
175
178
181
184
P67
P68
PB9
P70
P71
P72
P73
P74
P68
P69
P70
P7l
K13
J12
L13
M13
L12
Kll
Lll
Ll0
M12
Ml1
N13
Ml0
Nll
M9
Nl0
L8
N9
M8
N8
M7
L7
N7
N6
N5
MB
L6
N4
M5
N3
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P75
P76
pn
P78
P79
PBO
PSl
P82
P83
P84
pe5
P86
P87
P88
P89
'P90
P91
P72
P73
P74
P75
P76
P77
P78
P79
P80
PSl
P82
PB3
P84
P8S
P86
P87
P88
PS9
P60
PBl
P62
PS3
P64
PB5
P66
-
I/O(R~
ROY/lIDSY}
1/0 (DO, DIN)
1/0, SGCK4 (OOUT)
CCLK
VCC
O,TOO
GNO
1/0 (AO,WS)
1/0, PGCK4 (Al)
1/0 (CS1, A2)
1/0 (AS)
1/0(A4)
1/0 (AS)
1/0
1/0
1/0 (A6)
1/0 (A7)
GNO
5/5/97
P83
P84
Pl
-
187
190
193
196
199
202
205
208
211
214
217
220
223
226
229
232
235
238
N2
M3
L4
241
244
L3
M2
K3
L2
Nl
K2
' Ll
J2
Kl
H3
Jl
H2
Hl
G2
a
2
5
8
11
14
17
20
23
26
29
Additional XC4003E Package Pins
PG120
157
160
163
166
169
Al
E2
L5
5/5/97
I
I
I
A2
E3
L9
I
I
I
Not Connected Pins
A3
I 81
Ell
I J3
Ml
1 M4
I
I
I
Bl0
Jll
N12
I
I
I
B13
K12
4-111
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
Pin Locations for XC4005EIXL Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the availability
charts elsewhere in the XC4000 Series data sheet for availability information.
XC4005EIXL
Pad Name
VCC
1/0 (A8)
I/O (A9)
1/0 (A19) tt
I/O (A18)tt
1/0 (Al0)
1/0 (A11)
1/0
1/0
GNO
1/0 (A12)
1/0 (A13)
1/0
1/0
1/0 (A14)
1/0. SGCK1 t.
GCK8 tt (A 15)
VCC
GNO
1/0. PGCK1t.
GCK1tt (A16)
1/0 (A17)
pc
PQ
VQ
TQ
100 100tt 144
P2
P92
P89 P128
P3
P93
P90 P129
P4 P94
P91
P130
P95
P92 P131
P96
P93 P132
P5
P97
P94 P133
P6
P98
P9S P134
P13S
P136
P137
P7 P99
P96 P138
P8 Pl00 P97 P139
P140
P141
P9
Pl
P98 P142
Pl0
P2
P99 P143
84
Pl1
P12
P13
P3
P4
P5
P100
P1
P2
P144
Pl
P2
C3
P14
P6
P3
Al
P17
P18
P9
P10
P6
P7
P19
P20
P21
P22
P23
P24
P11
P12
P13
P14
P15
P16
P17
P1S
P8
P9
P10
P11
P12
P13
P14
P15
P25
P26
P19
P20
P16
P17
P27
P21
P22
P18
P19
P28
P29
P23
P24
P20
P21
P30
P31
P32
P33
P34
P35
P25
P26
P27
P28
P29
P30
P22
P23
P24
P25
P26
P27
P34
P35
P36
P37
P38
P39
P1S
P16
P7
P8
P4
PS
1/0
1/0
I/O.TMS
1/0
1/0
1/0
1/0
1/0
GNO
VCC
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
GNO
1/0
1/0
1/0
1/0
1/0
1/0. SGCK2 t.
GCK2tt
O(Ml)
GNO
I (MO)
VCC
I (M2)
1/0. PGCK2 t.
GCK3tt
1/0 (HOC)
1/0
1/0
1/0
I/O(LDC)
4-112
C4
B3
PQ
160
P142
P143
P144
P14S
P146
P147
P148
P149
P150
P151
P154
P15S
P156
P157
P158
P159
PQ
208
P183
P184
P18S
P186
P187
P190
P191
P192
P193
P194
P199
P200
P201
P202
P203
P204
P160 P205
P1
P2
P2
P4
Bndry
Scan
44
47
50
53
56
59
62
65
68
71
74
77
80
83
86
XC4oo5E1XL
Pad Name
GNO
P46
P47
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
I/O
P48
P49
P48
P49
1/0
1/0
1/0
1/0. SGCK3 t.
PSO
P51
PSO
PS1
TQ
144
P45
P46
P47
P31
P4S
P32
P49
P33
P50
P34
P51
P52
P3S
P36
P53
P37
P54
P38
P55
P39
P56
P40
P57
P41 ' P58
P42
P59
P43
P60
P44
P61
P62
P63
P64
P45
P65
P46
P66
P67
P68
P47
P69
P48
P70
P52
P53
P54
P5S
P56
P57
P52
P53
P54
P55
P56
P57
P49
P50
P51
P52
P53
P54
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0 (INIT)
VCC
GNO
I/O
1/0
1/0
1/0
1/0
1/0
1/0
1/0
-
P36
P37
P31
P32
P33
P28
P29
P30
P40
P41
P42
P43
P44
C5
B4
A3
C6
B5
B6
A5
C7
B7
A6
A7
A8
C8
B8
C9
B9
A9
B10
Cl0
Al0
All
Bl1
Cl1
B12
A13
A14
C12
B13
B14
P3
P4
P5
P6
P7
P10
Pl1
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P32
P33
P34
P35
P36
P37
P5
P6
P7
P8
P9
P14
P15
P16
P17
P18
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P33
P34
P35
P36
P37
P42
P43
P44
P45
P46
P47
A15
C13
A16
C14
B15
B16
P38
P39
P40
P41
P42
P43
P48
P49
PSO
P55
P56
P57
A2
014
C15
015
E14
C16
P44
P45
P46
P47
P48
P58
P59
P60
P61
P62
89
92
95
98
101
104
107
110
113
116
119
122
125
128
131
134
137
140
143
146
149
152
155
158
161
164
167
170
173
PC
84
P38
P39
P40
P41
P42
P43
P44
P4S
PQ
100
GNO
1/0
P3
P4
P5
P6
P7
P8
P9
P10
Pl1
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
1/0
1/0
I/O.TOI
I/O.TCK
GNO
PG
156t
H3
Hl
G1
G2
G3
F1
F2
E1
E2
F3
E3
Cl
C2
03
B1
B2
GCK4tt
GNO
OONE
VCC
1/0(07)
1/0. PGCK3t.
VQ
100ft
PG
156t
F14
F15
E16
F16
G14
G15
G16
H16
H15
H14
J14
J1S
J16
K16
K15
K14
L16
M16
L15
L14
P16
M14
N15
P15
N14
R16
PQ
160
P51
P52
PS3
P54
P5S
P56
PS7
P58
PS9
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P73
P74
P75
P76
P77
P78
PQ
P67
P68
P69
P70
P71
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P86
P87
P8S
P89
P90
P9S
P96
P97
P98
P99
Pl00
P71
P72
P73
P74
P75
P76
P14
R15
P13
R14
T16
T15
P79
P80
P81
P82
P83
P84
P101
Pl03
Pl06
Pl08
Pl09
P110
R13
P12
T14
T13
Pll
R11
Tll
Tl0
P10
R10
T9
R9
P9
R8
P8
T8
T6
R7
P7
T5
R6
T4
P6
T3
P5
P8S
P86
P87
P88
P91
P92
P93
P94
P9S
P96
P97
P98
P99
P100
P101
Pl02
P103
Pl04
P105
P106
P107
P10a
Pl09
Pll0
Pl13
Pl14
P111
P112
Pl13
Pl14
P119
P120
P121
P122
P123
P126
P127
P128
P129
P130
P131
P132
P133
Pl34
P135
P138
P139
P140
P141
P142
P147
P148
R4
R3
P4
Pl15 P149
P116 P150
P117 P151
208
Bndry
Scan
193
196
199
202
205
208
211
214
217
220
223
226
229
232
235
238
241
244
247
250
253
256
259
262
GCK5tt
1/0
1/0
1/0(06)
1/0
-
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70·
P57
PS8
P59
P60
P61
P62
P63
P64
P65
P66
P67
P67
P68
P71
P72
P68
P69
P69
P70
P73
P74
P70
P71
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P9S
P96
P97
P98
P99
P100
Pl0l
Pl02
P72
P103
P104
Pl05
P58
P58
P59
P55
P56
GNO
1/0
1/0
1/0 (05)
110 (-esc)
1/0
1/0
1/0(04)
1/0
VCC
GNO
1/0 (03)
I/O(J!!'S}
1/0
1/0
1/0(02)
1/0
1/0
1/0
174
175
GNO
178
181
184
187
190
ROY/BUSy)
1/0(01)
1/0 (RCLK.
1/0
1/0
1/0 (00. OIN)
P59
P60
P61
P62
P63
P64
P65
P66
P71
P75
T7
265
268
271
274
-
277
280
283
286
289
292
295
298
301
304
307
310
313
316
319
322
325
328
331
334
337
November 10. 1997 (Version 1.4)
~XILINX
XC4005E/XL
Pad Name
1/0, SGCK4 t,
GCK6 tt (OOUT)
CCLK
VCC
0, TOO
GNO
1/0 (AO,WS)
1/0, PGCK4 t,
GCK? tt (AI)
1/0
1/0
1/0 (CS1, A2)
1/0 (A3)
GNO
1/0
1/0
1/0 (A4)
1/0 (A5)
1/0 (A21) tt
1/0 (A20) tt
1/0 (A6)
110 (A?)
GNO
PC
84
P72
P?3
P?4
P?5
P?6
P77
P?8
P?9
P80
P81
P82
P83
P84
PI
PO
100
P?6
P77
P?8
P?9
P80
P81
P82
P83
P84
P85
P86
P8?
P88
P89
P90
P91
va TO
100tt 144
P?3 Pl06
P?4
P?5
P?6
P77
P?8
P?9
P80
P81
P82
P83
P84
P85
P86
P8?
P88
PG
156t
T2
PO Bndry
PO
160
208 Scan
P118 P152 340
Pl0?
Pl08
Pl09
PlIO
PIlI
P112
R2
P3
Tl
N3
Rl
P2
P119
P120
P12l
P122
P123
P124
P153
P154
P159
P160
P161
P162
P113
P114
P115
P116
P118
P119
P120
P12l
P122
P123
P124
P125
P126
P12?
N2
M3
PI
Nl
L3
L2
Ll
K3
K2
Kl
Jl
J2
J3
H2
P125
P126
P12?
P128
P131
P132
P133
P134
P135
P13?
P138
P139
P140
P141
P163
P164
P165
P166
Pl?1
Pl?2
Pl?3
Pl?4
Pl?5
P178
Pl?9
P18G
P181
P182
PG156
A4
Ml
T12
5/5/9?
I
I
I
A12
M2
I
I
I
P9
P?2
P130
I
I
1
Not Connected Pins
01
I 02 I
M15
I N16 I
016
R5
I
I
I
E15
R12
P49
PIlI
P153
I
I
I
P50
P112
I
I
0
2
5
8
11
14
I?
20
23
26
29
32
35
38
41
6/10/9?
t = E only
tt = XL only
Additional XC4005E/XL Package Pins
P0160
P8
P?1
P129
6/16/9?
I
I
I
Not Connected Pins
P30
I P31 I
P89
I P90 I
P136 I P152 I
P0208
PI
P19
P40
P63
P84
Pl02
Pl1?
P143
P15?
Pl?6
P19?
6/5/9?
Not Connected Pins
Pl0
Pll
P31
P32
P51
P52
P65
P66
P91
P92
Pl05
Pl0?
P124
P125
P145
P146
P1S8
P16?
P188
P189
P206
P20?
P3
P20
P41
P64
P85
Pl04
P118
P144
P158
PI??
P198
P12
P38
P53
P?2
P93
P115
P136
PISS
P169
P195
P208
P13
P39
P54
P?3
P94
P116
P13?
P156
Pl?O
P196
T0144
Not Connected Pins
I
I
Pll?
5/5/9?
I
Pin Locations for XC4006E Devices
XC4006E
Pad Name
VCC
1/0 (A8)
110 (A9)
1/0
1/0
1/0 (Al0)
1/0 (All)
110
1/0
GNO
1/0
1/0
1/0 (AI2)
1/0 (AI3)
1/0
1/0
1/0 (AI4)
110, SGCKI (AI5)
VCC
GNO
110, PGCKI (AI6)
1/0 (AI?)
110
110
1/0, TOI
1/0, TCK
110
110
GNO
PC
84
P2
P3
P4
P5
P6
P?
P8
P9
Pl0
Pll
P12
P13
P14
P15
P16
TO
144
P128
P129
P130
P131
P132
P133
P134
P135
P136
P13?
P138
P139
P140
P141
P142
P143
P144
PI
P2
P3
P4
P5
P6
P?
PG
156
H3
HI
Gl
G2
G3
Fl
F2
El
E2
F3
01
02
E3
Cl
C2
03
Bl
B2
C3
C4
B3
AI
A2
G5
B4
A3
A4
P8
C6
November 10, 1997 (Version 1.4)
PO
160
P142
P143
P144
P145
P146
P14?
P148
P149
P150
P151
P152
P153
P154
P155
P156
P15?
P158
P159
P160
PI
P2
P3
P4
P5
P6
P?
P8
P9
Pl0
PO
208
P183
P184
P185
P1B6
P18?
P190
P191
P192
P193
P194
P19?
P198
P199
P200
P20l
P202
P203
P204
P205
P2
P4
P5
P6
P?
P8
P9
Pl0
Pl1
P14
XC4006E
Pad Name
Bndry
Scan
50
53
56
59
62
65
68
?1
?4
77
80
83
86
89
92
95
98
101
104
10?
110
113
116
119
110
110
1/0, TMS
1/0
1/0
1/0
1/0
110
GNO
VCG
1/0
1/0
1/0
1/0
c"0
1/0
1/0
1/0
GNO
1/0
1/0
1/0
1/0
110
110
110
1/0, SGGK2
O(Ml)
GNO
PC
84
P17
P18
PI9
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
TO
144
P9
Pl0
Pll
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
PG
156
B5
B6
A5
C7
B7
A6
A7
A8
C8
B8
C9
B9
A9
Bl0
Gl0
Al0
All
Bll
GIl
A12
B12
A13
A14
G12
B13
B14
A15
C13
PO
160
Pll
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P3?
P38
P39
PO
208
P15
P16
P17
P18
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P33
P34
P35
P36
P37
P40
P41
P42
P43
P44
P45
P46
P4?
P48
P49
Bndry
Scan
122
125
128
131
134
137
140
143
146
149
152
155
158
161
164
167
170
173
1?6
1?9
182
185
188
191
194
4-113
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4006E
Pad Name
I (MO)
VCC
I (M2)
liD, PGCK2
110 (HDC)
liD
liD
liD
110 (LDC)
liD
liD
GND
liD
liD
liD
I/O
liD
liD
liD
110 (INIT)
VCC
GND
liD
liD
I/O
liD
liD
liD
liD
liD
GND
liD
liD
liD
liD
liD
liD
I/O
1/0,SGCK3
GND
DONE
VCC
PROGRAM
1/0(07)
liD, PGCK3
liD
liD
1/0(06)
liD
I/O
liD
GND
liD
liD
1/0(05)
110 (CSO)
liD
liD
1/0(04)
liD
VCC
GNO
1/0(03)
liD (FIS)
4-114
PC
84
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
TO
144
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
PG
156
A16
C14
B15
B16
D14
C15
D15
E14
C16
E15
D16
F14
F15
E16
F16
G14
G15
G16
H16
H15
H14
J14
J15
J16
K16
K15
K14
L16
M16
L15
L14
N16
M15
P16
M14
N15
P15
N14
R16
P14
R15
P13
R14
T16
T15
R13
P12
T14
T13
R12
T12
P11
R11
T11
T10
P10
R10
T9
R9
P9
R8
P8
T8
T7
PO
160
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100
P101
P102
P103
PO
208
P50
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P67
P68
P69
P70
P71
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
Bndry
Scan
197
PC
84
liD (02)
liD
liD
liD
GNO
liD
liD
110 (D1)
110 (RCLK,
RDY/BUSY)
liD
liD
liD (00, DIN)
liD, SGCK4 (OOUT)
CCLK
VCC
0, TOO
GNO
110 (AO, WS)
liD, PGCK4 (A1)
liD
liD
liD (CS1 , A2)
110 (A3)
liD
liD
GNO
liD
liD
I/O(M)
110 (A5)
liD
liD
110 (A6)
I/O (A7)
GNO
P67
P68
liD
198
199
202
205
208
211
214
217
220
223
226
229
232
235
238
241
244
247
250
253
256
262
265
268
271
274
277
280
283
286
289
292
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P101
P102
T3
P5
P103
P104
P105
P106
P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
P117
R4
R3
P4
T2
R2
P3
T1
N3
R1
P2
N2
M3
P1
N1
M2
M1
L3
L2
L1
K3
K2
K1
J1
J2
J3
H2
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P137
P138
P139
P140
P141
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
P81
P82
P83
P84
P1
PG
156
T6
R7
P7
T5
R6
T4
P6
R5
PO
160
P104
P105
P106
P107
P108
P109
P110
P111
P112
P113
P114
TO
144
P94
P95
P96
P97
P98
P99
P100
I/O
.~ _~5~
P87
P88
P89
P90
P93
P94
P95
P96
P97
P98
P99
P100
P101
P103
P106
P108
P109
P110
P111
P112
P113
P114
P115
P116
P119
P120
P121
P122
P123
P126
P127
P128
P129
P130
P131
P132
P133
XC4006E
Pad Name
PO
208
P134
P135
P138
P139
P140
P141
P142
P145
P146
P147
P148
Bndry
Scan
349
352
355
358
361
364
P149
P150
P151
P152
P153
P154
P159
P160
P161
P162
P163
P164
P165
P166
P167
P168
P171
P172
P173
P174
P175
P178
P179
P180
P181
P182
379
382
385
388
367
370
373
376
a
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
5/5/97
Additional XC4006E Package Pins
295
298
P0160
301
304
307
310
313
316
P136
5/5/97
319
322
325
328
331
334
337
340
Not Connected Pins
I
I
P0208
P1
P20
P51
P66
P91
P107
P136
P156
P176
P196
6/5/97
P3
P31
P52
P72
P92
P117
P137
P157
P177
P206
Not Connected Pins
P12
P32
P53
P73
P102
P118
P143
P158
P188
P207
P13
P38
P54
P84
P104
P124
P144
P169
P189
P208
P19
P39
P65
P85
P105
·P125
~~
P155
P170
P195
343
346
November 10, 1997 (Version 1.4)
~XILINX
Pin Locations for XC4008E Devices
XC4008E Pad Name
VCC
1/0 (A8)
1/0 (A9)
1/0
1/0
1/0
1/0
1/0 (Al0)
1/0 (All)
1/0
1/0
PC84
P2
P3
P4
P5
P6
GNO
1/0
1/0
1/0 (A12)
1/0 (A13)
1/0
1/0
1/0 (A14)
1/0, SGCK1 (A15)
VCC
GNO
110, PGCKl (A16)
1/0 (A17)
1/0
1/0
1/0, TOI
1/0, TCK
1/0
1/0
P7
P8
P9
Pl0
P11
P12
P13
P14
P15
P16
GNO
1/0
1/0
I/O,TMS
1/0
1/0
1/0
P17
P18
110
1/0
1/0
1/0
GNO
VCC
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
P19
P20
P21
P22
P23
P24
P25
P26
GNO
1/0
1/0
1/0
1/0
1/0
110
110
I/O, SGCK2
Q{Ml)
GNP
I (MO)
VCC
I (M2)
1/0, PGCK2
P27
P28
P29
P30
P31
P32
P33"
P34
P35
PQ160 PG191 PQ208 Bndry Scan
P142
J4
P183
P143
J3
Pl84
56
P144
J2
Pl85
59
P145
Jl
P186
62
P146
H1
P187
65
H2
P188
68
H3
P189
71
P147
Gl
P190
74
Pl48
G2
P191
77
P149
Fl
P192
80
P150
E1
P193
83
P151
G3
P194
P152
Cl
P197
86
P153
E2
P198
89
P154
F3
P199
92
P155
02
P200
95
P156
B1
P201
98
P157
E3
P202
101
P158
P203
C2
104
P159
B2
P204
107
P160
03
P205
Pl
04
P2
P4
110
P2
C3
P3
C4
P5
113
P4
B3
P6
116
P5
P7
119
C5
P6
A2
P8
122
P7
B4
P9
125
P8
Pl0
128
C6
P9
A3
Pl1
131
Pl0
C7
P14
Pll
P15
134
A4
P12
137
AS
P16
140
B7
P13
P17
P14
P18
143
A6
C8
P19
146
A7
P20
149
P15
88
P21
152
P16
A8
P22
155
P17
B9
P23
158
P18
C9
P24
161
P19
09
P25
P20
010
P26
P21
Cl0
P27
164
P22
Bl0
P28
167
P23
A9
P29
170
P24
Al0
P30
173
All
P31
176
Cll
P32
179
P25
Bll
P33
182
P26
A12
P34
185
P27
B12
P35
188
P28
A13
191
P36
P29
C12
P37
P30
A15
P40
194
P31
C13
P41
197
P32
B14
P42
200
P33
A16
P43
203
P34
B15
P44
206
P35
C14
P45
209
1'36
P46
212
A17
P37
P47
215
P38
C15
P48
218
P39
P49
015
P40
A18
P50
221
P41
016
P55
P42
P56
222
C16
P43
817
P57
223
all,
XC4008E Pad Name
I/O (UX:;)
P37
1/0
1/0
GNO
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0 (INIT)
P38
P39
P40
P41
P42
P43
P44
P45
VCC
GNO
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
P46
P47
GNO
110
1/0
1/0
1/0
1/0
1/0
1/0
1/0, SGCK3
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
GNO
OONE
vec
PROGRAM
1/0(07)
1/0, PGCK3
-
1/0
110
110(06)
P58
1/0
1/0
1/0
GNO
1/0
1/0
1/0(05)
P59
P60
,1/0 (eSO)
1/0
-
110
I/O
I/O
110(04)
1/0
VCC
GNO
1/0(03),
1/0 (AS)
1/0
1/0
110
November 10, 1991 (Version 1.4)
PC84
P36
1/0 (HOC)
1/0
1/0
1/0
"
',P61
P62
P63
1'64
P65
P66
PQ160 PG191 PQ208 BndryScan
P44
E16
P58
226
C17
P59
P45
229
P46
017
P60
232
P47
B18
P61
235
P46
E17
P62
238
P49
F16
P63
241
P50
C18
P64
244
P51
G16
P67
P52
E18
P68
247
P53
F18
P69
250
P54
P70
G17
253
P55
G18
P71
256
H16
P72
259
H17
P73
262
P56
H18
P74
265
P57
J18
P75
268
P58
J17
P76
271
P59
J16
P77
274
P60
J15
P78
P61
K15
P79
K16
P80
277
P62
P63
K17
P81
280
P64
K18
P82
283
P65
L18
P83
286
L17
P84
289
L16
P85
292
P66
M18
295
P86
P67
M17
P87
298
P68
N18
P88
301
P18
P89
304
P69
P70
M16
P90
P71
T18
P93
307
P72
P17
P94
310
P73
N16
P95
313
P74
T17
P96
316
R17,
P75
P97
319
P76
P16
P98
322
P77
U18
325
P99
T16
Pl00
P78
328,
P79
R16
Pl01
P80
U17
Pl03
P81
R15
Pl06
P82
V18
Pl08
T15
Pl09
331
P83
P84
U16
Pll0
334
P85
T14
Plll
337
P86
U15
Pl12
340
P87
V17
P113
343
P114
346
P88
V16
P89
T13
P115
349
P90
U14
Pl16
352
P91
T12
Pl19
P92
U13
1'120
355
P93
V13
P121
358
1'94
U12
P122
361
P95
V12
P123
384
367
TIl
P124
Ul1
1'125
370
P96
Vll
Pl26
373
P97
Vl0
P127
376
P128
379
PSa ' Ul0
P99
Tl0
P129
382
Pl00
Rl0
P130
'Pl0l
R9
P131
Pl02
T9
P132
385
Pl03
Pl33
U9
388
Pl04
V9
P134
391
P105
V8
P135
394
U8'
P136
397
4-115
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4008E Pad Name
PC84
1/0
1/0 (D2)
1/0
1/0
1/0
P67
P68
GND
VO
1/0
1/0 (Dl)
1/0 (RCLK, ROYilroSY)
1/0
1/0
1/0 (DO, DIN)
1/0, SGCK4 (OOUT)
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
CCLK
VCC
O,TOO
GNO
110 (AO,WS)
1/0, PGCK4 (Al)
1/0
1/0
1/0 (CSl , A2)
1/0 (A3)
1/0
1/0
P79
P80
GNO
1/0
1/0
1/0(A4}
P81
P82
1/0 (A5)
PQ160 PG191 PQ208 Bndry Scan
T8
P137
400
Pl06
V7
P138
403
Pl07
U7
P139
406
Pl08
V6
P140
409
Pl09
P141
U6
412
Pll0
T7
P142
Plll
P145
415
U5
Pl12
T6
Pl46
418
Pl13
V3
P147
421
Pl14
V2
P148
424
Pl15
U4
P149
427
Pl16
T5
P150
430
Pl17
U3
P151
433
Pl18
T4
P152
436
Pl19
Vl
P153
P120
R4
P154
P121
U2
P159
0
P122
R3
P160
P123
T3
P161
2
P124
Ul
P162
5
P125
P3
P163
8
P126
R2
P164
11
P127
T2
P165
14
P128
N3
P166
17
P129
P2
P167
20
P130
Tl
P168
23
P131
M3
P171
P132
Pl
P172
26
P133
Nl
P173
29
P134
M2
P174
32
P135
Ml
P175
35
XC4008E Pad Name
PC84
1/0
1/0
1/0
1/0
1/0 (A6)
1/0 (A7)
P83
P84
Pl
GNO
PQ160 PG191 PQ208 BndryScan
L3
P176
38
P136
L2
P177
41
P137
Ll
P178
44
P138
Kl
P179
47
P139
K2
P180
50
P140
K3
P181
53
P141
K4
P182
5/5/97
Additional XC4008E Package Pins
PG191
A14
F2
V4
I
I
I
I
I
I
B5
F17
V5
Not Connected Pins
B6
I B13
N2
I N17
V14
I V15
I
I
I
I
I
I
01
Rl
018
R18
6/3/97
PQ208
Pl
P51
P91
Pl17
P157
P206
P3
P52
P92
Pl18
P158
P207
Not Connected Pins
P12
P13
P53
P54
Pl02
Pl04
P143
P144
P169
P170
P208
P38
P65
Pl05
P155
P195
P39
P66
Pl07
P156
P196
6/3/97
Pin Locations for XC401 OE/XL Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the availability
charts elsewhere in the XC4000 Series data sheet for availability information.
XC4010E/XL
Pad Name
PC
B4
PO
TO
PO
TO
PG
l00tt 144tt 160 17&tt 191t
PQJ
HO
BG
209 225t
VCC
P2 P92 P128 PI42 PISS VCC" PI83 VCC"
110 (AS)
P3 P93 Pl29 Pl43 P1S6 J3
Pl84 E8
110 (A9)
P4 P94 P130 Pl44 P1S7 J2
P1SS B7
I/O (19)
P9S P131 Pl45 P1S8 Jl
P186 A7
110 (18)
P96 P132 Pl46 P1S9 Hl
P187 07
110
P160 H2 Pl68 07
110
P161
H3 P189
E7
I/O (Al0)
PS P97 Pf33 P147 P162 Gl
Pl90 A6
I/O (All)
P6 P98 Pl34 Pl46 P163 G2 P191
B6
VOO
VOO"
VOO"
,
I/O
P1SS P149 Pl64 Fl
Pl92 AS
I/O
P136 Pl50 P16S El
Pl93 B6
GNO
P137 P151 P166 GNO" Pl94 GNO"
110
F2 Pl95 06
I/O
P1S7 01
P196 05
I/O
P1S2 P168 01
P197 A4
110
Pl53 P169 E2 Pl96
E6
I/O (A12)
P7 P99 Pl36 Pl54 P170 F3 P199 B4
I/O (A13)
P8 Pl00 P139 Pl55 P171 D2 P200 05
I/O
Pl40 Pl56 P172 Bl
P201
B3
110
P141 P1S7 P173 E3 P202
F6
110 (A14)
P9
Pl P142 Pl56 P174 02 P203 A2
1/0,SGOKl t, Pl0 P2 Pl43 P1S9 P17S B2 P204 03
GOK8tt
(A15)
VOO
Pll
P3 Pl44 Pl60 P176 VOO" P205 vee"
GNO
P12 P4
Pl
Pl
Pl GNO" P2 GNO"
I/O, PGOKlt, P13 P5
P2
P2
P2
C3
P4
04
GOKltt
(A16)
110 (A17)
P14 P6
P3
PS
P3
Bl
P3
C4
-
4-116
BG
Bndry
256tt
Scan
VCC"
Cl0
010
A9
B9
09
09
AS
B8
VOO"
B6
AS
GNO"
06
BS
A4
05
B4
62
65
68
71
74
77
90
83
86
89
A2
C3
92
95
96
101
104
107
110
113
116
119
vee"
GNO"
Bl
122
02
125
A3
B3
B2
XC4010E/XL
Pad Nama
110
I/O
I/O,TOI
I/O,TOK
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O,TMS
I/O
VOO
110
I/O
110
I/O
110
I/O
GNO.
veo
110
110
110
I/O
110
110
VOO
I/O
VO
PC
B4
P15
P16
P17
P18
PO
TO
100ft 144tt
P7
P8
P9
Pl0
P4
PS
P6
P7
P8
P9
Pl0
Pll
P12
PO
160
P4
PS
P6
P7
P8
P9
Pl0
Pll
P12
P13
P14
P19
P20
P21
P22
P23
P24
Pll
P12
P13
P14
P1S
P16
P17
P18
P13
P14
P1S
P16
P17
P18
P19
P20
P21
P22
P1S
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P19
P20
P23
P24
P25
P26
TO
PG
17&tt 191t
P4
PS
P6
P7
P8
P9
B3
OS
A2
B4
06
A3
BS
B6
Pl0 GNO"
Pll
A4
P12
AS
P13
B7
P14
A6
VOO"
P1S
08
P16
A7
P17
B6
P18
AS
P19
B9
P20
09
P21 GND"
P22 VOO"
P23 010
P24 Bl0
P2S
A9
P26 Al0
P27 All
P28 011
VOO"
P29 Bll
P30 A12
PQJ
HO
208
P6
P7
P8
P9
Pl0
Pll
P12
P13
P14
P1S
P16
P17
P18
P19
P20
P21
P22
P23
P24
P2S
P26
P27
P28
P29
P30
P31
P32
P33
P34
BG
225t
02
E5
03
01
02
G6
E4
01
GNO"
FS
El
F4
F3
VOO"
G4
G3
G2
Gl
GS
H3
GNO"
VOO"
H4
HS
J2
Jl
J3
J4
VOO"
K2
K3
BG
Bndry
256ft Scan
02
03
E4
01
01
E3
E2
El
GNO"
G3
G2
Gl
H3
VOO"
J2
Jl
K2
K3
Kl
L1
GNO"
VOO"
L2
L3
L4
Ml
M2
M3
Vee"
Pl
P2
128
131
134
137
140
143
146
149
152
155
156
161
164
167
170
173
176
179
182
185
188
191
194
197
200
203
November 10, 1997 (Version 1.4)
~XILINX
XC4010EIXL
Pad Name
PC
84
PQ
TQ
100tt 144tt
1/0
1/0
P25
P26
P27
GNO
1/0
1/0
1/0
VO
1/0
1/0
P27
P21
P22
GCK2tt
0(M1)
GNO
I (MO)
VCC
I (M2)
1/0, PGCK2 t.
GCK3tt
1/0 (HOC)
1/0
1/0
1/0
1/0 (LOC)
1/0
1/0
1/0
P30
P31
P32
P33
P34
P35
P36
P37
P34
P35
P36
P37
P38
P39
P40
P41
B12
A13
GNO'
B13
A14
A15
C13
B14
A16
815
C14
A17
816
C15
GNO'
A18
VCC'
C16
B17
P27
P28
P29
P23
P24
P30
P31
P32
P33
P34
P35
P25
P26
P27
P28
P29
P30
P34
P35
P36
P37
P38
P39
P38
P39
P40
P41
P42
P43
P42
P43
P44
P45
P46
P47
P36
P31
P37
P32
P33
P40
P41
P42
P43
P44
P44
P45
P46
P47
P48
P49
P50
P48
P49
P50
P51
P52
P53
P54
P38
P39
1/0
1/0
1/0
1/0
1/0
1/0
P46
P47
110
110
P50
1/0, SGCK3 t, P51
GCK4 tt
GNO
P52
OONE
P53
VCC
PS4
PROGRAM
P55
1/0(07)
P56
110, PGCK3 t, PS7
GCKS tt
P3
L5
N4
R3
P4
K7
M5
R4
N5
GNO'
R5
M6
N6
P6
VCC'
R6
M7
R7
L7
N8
P8
VCC'
GNO'
L8
P9
R9
N9
M9
L9
VCC'
NI0
K9
Rl1
Pl1
GNO'
R12
L10
P12
Mll
R13
N12
P13
KI0
R14
N13
250
253
256
259
262
265
268
271
274
P71
P72
P73
P74
P?5
P76
P79
P80
P81
P82
P83
P84
P87
P88
P89
P90
P91
P92
110
1/0
P48
P49
242
P52
P53
PS4
P55
PS6
P57
P46
P47
GNO
1/0
1/0
1/0
1/0
1/0
1/0
1/0
N3
W2
GNO' GNO'
P2
Y1
VCC' VCC'
M4
W3
R2
Y2
P50
P51
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
VCC
1/0
1/0
P48
P49
P50
P55
P56
P57
P65
P66
P67
P68
P69
P70
P51
P52
P53
P54
P55
VO
VO
VCC
GNO
J6
R1
L1
P3
GNO' GNO'
L3
T2
M1
U1
K5
T3
M2
U2
L4
Vl
N1
T4
M3
U3
N2
V2
K6
W1
P1
V3
P71
P72
P73
P74
P75
P76
P77
P78
P34
P35
P45
P46
P47
P48
P49
VCC
P40
P41
P42
P43
P44
P45
PQI
HQ
208
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
E16
P58
C17
P59
017
P60
B18
P61
E17
P62
F16
P63
C18
P64
018
P65
F17
P66
P55 GNO' P67
P56
E18
P6S
P57
F18
P69
P58 G17 P70
P59 G18 P71
VCC'
P60
H16
P72
P61
H17
P73
P62
H18
P74
P63
J18
P75
J17
P64
P76
P65
J16
P77
P66 VCC' P78
P67 GNO' P79
K16
P68
P80
P69
K17
P81
P70
K18
P82
P71
L18
P83
P72
L17
P84
P73
L16
P85
VCC'
P74 M18 P86
P75 M17 P87
P76 N18 P88
P18
P77
P89
P78 GNO' P90
N17 P91
R18
P92
P79 T18
P93
P80
P17
P94
P81
NI6 P95
P82 T17
P96
P83 R17
P97
P84
P16
P98
P85
U18 P99
PB6 T16 PI00
VO
1/0
1/0
1/0
1/0 (INIT)
P31
P32
P33
P28
P29
GNO
1/0
1/0
1/0
1/0
TQ
PG
176tt 191t
P28
P29
P30
P31
P32
P33
VO
1/0
1/0
1/0, SGCK2 t,
PQ
160
P48
P49
P60
P61
P62
P63
P64
P66
P67
P68
P69
P70
November 10, 1997 (Version 1.4)
GNO'
U17
VCC'
V18
T15
U16
BG
225t
BG
256tt
W4
V4
U5
Y3
Y4
V5
W5
YS
V6
GNO'
W7
Y7
V8
W8
VCC'
Y8
U9
VI0
YI0
Yll
Wll
VCC'
GNO'
Vl1
Ull
Y12
W12
V12
U12
VCC'
Y15
V14
W15
Y16
GNO'
Y17
V16
W17
Y18
U16
V17
W18
Y19
V18
W19
PI0l GNO' GNO'
PI03 P14
Y20
PI06 VCC' VCC'
PI08 M12
V19
P109 P1S
U19
P110 N14
U18
Bndry
Scan
206
209
212
215
218
221
224
227
230
233
236
239
245
XC4010EIXL
Pad Name
1/0
1/0
1/0 (06)
1/0
1/0
1/0
1/0
1/0
PC
84
PS8
P73
P74
'pill
Pl12
PI01 P113
PI02 P114
P75
P76
PI03
P104
PI05
PI06
P115
Pl16
P117
Pl18
P127
P128
P129
P130
P77
P78
P79
P80
P81
P82
PI07
PI08
PI09
PI10
Pl11
P112
P119
P120
P121
P122
P123
P124
P131
Vl
P153 C13
A20
P132 VCC' P154 VCC' VCC'
P133
U2 P159 A15
A19
P134 GNO' P160 GNO' GNO'
P135
T3
P161 A14
818
P136 Ul
P162 813
817
Pl13
Pl14
P115
Pl16
P117
P125
P126
P127
P128
P129
P130
P137
P138
P139
P140
P141
P142
P8S
P86
P87
P88
P89
P90
P81
P82
P83
P91
P92
P93
P60
P61
P84
P85
P94
P95
P62
P63
P64
P65
P66
P67
P68
P69
P70
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
PI00
PI0l
PI02
PI03
PI04
PI05
P7I
P72
P96
P97
PI06
PI07
P58
P59
1/0
1/0
VCC
1/0(05)
~O)
P59
P60
1/0
1/0
1/0
1/0(04)
1/0
VCC
GNO
1/0(03)
VO(RS)
P61
P62
P63
P64
P65
P66
VO
VO
VO
PQ
160
P77
P78
P79
P80
GNO
VO
246
247
PQI
BG
HQ
225t
208
P93 T14 Pl11
Lll
P94 U15 Pl12 M13
P95 V17 P113 JI0
P96 V16 P114 L12
P97 T13 Pl15 M15
P98
U14 Pl16 L13
V15 Pl17 L14
V14 Pl18 Kll
P99 GNO' Pl19 GNO'
PI00 U13 P120 K13
PI01 V13 P121
K14
VCC'
VCC'
PI02 U12 P122 K1S
PI03 V12 P123 J12
PI04 Tll P124 J13
PI05 Ull P12S J14
PI06 Vll P126 J15
PI07 VI0 P127 Jl1
PI08 UI0 P128 H13
PI09 TI0 P129 H14
PII0 VCC' P130 VCC'
Pl11 GNO' P131 GNO'
P112 T9
P132 H12
Pl13
U9 P133 Hl1
P134 G14
P114 V9
P115 V8
P135 G15
P116 U8 P136 G13
Pl17 T8
P137 G12
Pl18 V7
P138 Gll
Pl19
U7 P139 F15
VCC'
VCC'
P120 V6
P140 F14
P121
F13
U6 P141
P122 GNO' P142 GNO'
V5
P143 E13
V4
P144 015
P123 U5 P145 Fll
P124 T6
P146 014
V3
P147 E12
P125
P126
V2
P148 C15
PQ
TQ
100tt 144tt
1/0
1/0(02)
1/0
P67
P68
VCC
277
280
283
286
289
292
295
298
301
304
307
310
313
316
319
322
325
328
331
334
337
340
343
346
349
352
355
358
361
364
367
370
1/0
1/0
P98 PI08
P99 PI09
PI00 PI10
GNO
VO
1/0
1/0
1/0
1/0(01)
1/0 (RCLK,
ROY/8USY)
~
P69
P70
1/0
1/0
1/0 (00, OIN) P71
1/0, SGCK4 t, P72
GCK6tt
(OOUT)
CCLK
VCC
O,TOO
GNO
I/O (AO,VilS)
1/0, PGCK4 t,
GCK7tt (Al)
P73
P74
P75
P76
P77
P78
VO
1/0
1/0 (CS1, A2)
1/0 (A3)
P79
P80
P83
P84
VO
I/O
I/O
TO
PG
176tt 191t
1/0
Pl18 P131 P143
Pl19 P132 P144
P120 P133 P145
GNO
1/0
I{O
VCC
1/0(A4)
1/0 (A5)
1/0
1/0
1/0 (A21)tt
1/0 (A20)tt
1/0 (A6)
1/0 (A7)
P81
P82
P85
P86
PB3
P84
P87
P88
P89
P90
P121 P134 P146
P122 P13S P147
P148
P136 P149
P123 P137 P150
P124 P13S P151
P125 P139 P152
P126 P140 PI53
U4
TS
U3
T4
P3
R2
T2
N3
P2
Tl
Rl
N2
GNO'
Pl
Nl
VCC'
M2
Ml
L3
L2
Ll
Kl
K2
K3
P149
P150
P151
P152
013
C14
FlO
815
BG
Bndry
256tt Scan
T17
V20
T19
T20
R18
R19
R20
P18
GNO'
N19
N20
VCC'
M17
M18
M20
L19
L18
L20
K20
K19
VCC'
GNO'
K18
K17
J20
J19
J18
J17
H19
H18
VCC'
G19
F20
GNO'
020
E18
019
C20
Ell
018
457
460
463
466
469
472
C19
820
C18
819
475
478
481
484
P163 Ell
C17
P164 C12
016
P165 A13
A18
P166 812
A17
P167 A12
A16
P168 Cll
C15
Pl69 811
815
P170 El0
A15
P171 GNO' GNO'
P172 All
814
P173 010
A14
VCC' VCC'
P174 AI0
C12
P175
812
09
P176
A12
C9
Pl77
89
Bl1
P178
Cll
A9
P179
E9
All
P180
MO
C8
P181
810
88
373
376
379
382
385
388
391
394
397
400
403
406
409
412
415
418
421
424
427
430
433
436
439
442
445
448
451
454
0
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
4-117
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
8G225
vec Pins
6/19/97
, Pads labelled GND' or vee' are internally bonded to Ground or
vee planes within the package. They have no direct connection to
any specific package pin.
t = E only
tt = XL only
Additional XC4010E/XL Package Pins
PQ/HQ208
PI
PI04
P206
I
1
I
P3 I
Plosl
P207 I
Not Connected Pins
P51
I P52 I P53
PI07
PI5S
PI56
P208
I
I
I
I
I
I
I
P54
PI57
I
I
I
PI02
PI58
PGI91
vee Pins
I
I
010
C7
K4
T7
1
CI2
KI5
TI2
I
I
I
I
016
I
I
I
04
M3
I
I
I
J4
GNO Pins
09
I MI6
I
I
I
JI5
I
015
R3
I
I
I
I
I
I
I
R4
I
I
RIO
G3
R9
J
GI6
RI6
I
I
814
I
I
AI
H2
J8
A8
H6
J9
I
A3
E3
FI2
L6
P5
810
EI4
GIO
LI5
P7
08
HI
HI5
GNO Pins
012
F8
G7
H7
H8
H9
K8
M8
Not Connected Pins
C4
CIO
C6
EI5
FI
F2
J5
KI
K4
MI4
N7
MIO
PIO
RIO
I
RI
R8
I
G8
HIO
G9
J7
OIl
F7
KI2
NIl
E2
F9
L2
NI5
015
K4
RI7
W20
E20
LI7
U6
017
U4
G20
U8
C4
EI9
H2
N2
C7
F2
H2O
NI8
V9
VI3
WI6
Y6
6/16/97
8G256
5/27/97
03
RI5
82
RI5
5/27/97
VCC Pins
OIl
G4
R2
UI5
GNO Pins
08
N4
CI4
FI
P4
U7
06
F4
PI7
UIO
07
FI7
PI9
UI4
AI
H4
UI3
B7
HI7
UI7
A6
C8
F3
J3
P20
A7
CI3
FI8
J4
R3
W6
YI3
04
013
N3
NI7
WI4
Not Connected Pins
AI3
813
816
CI6
05
012
FI9
GI8
HI
NI
M4
MI9
TI
TI8
U20
W9
WIO
WI3
YI4
VI5
Y9
014
GI7
R4
V7
5/27/97
Pin Locations for XC4013E/XL Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the availability
charts elsewhere in the XC4000 Series data sheet for availability information.
XC4013E
HT
Pad Name 144tt
VCC
PI28
1/0 (A8)
P129
1/0 (A9)
P130
1/0
P131
(A19)tt
110
P132
(A18)tt
IXL
PQ
160
P142
P143
P144
P145
P155
P156
P157
P158
P183
P184
P185
P186
P146
P159
P187
P147
P148
P160
P161
P162
P163
P188
P189
P190
P191
1/0
110
1/0 (Al0)
1/0 (All)
VCC
1/0
110
110
1/0
GNO
P133
P134
P135
P136
P137
P149
P150
P151
P164
P165
P166
P138
P139
P152
PI53
P154
P155
P167
P168
P169
P170
P171
P192
P193
P194
P195
P196
P197
P198
P199
P200
P140
P141
P156
P157
P172
P173
P201
P202
1/0
1/0
1/0
110
1/0 (A12)
1/0 (A13)
1/0
1/0
1/0
1/0
4-118
PQ/HQ PG
HT
208
223t
176tt
BG
225t
VCC' VCC'
J3
E8
J2
B7
Jl
A7
Hl
C7
H2
07
H3
E7
Gl
A6
G2
B6
VCC' VCC'
H4
C6
G4
F7
A5
Fl
El
B5
GNO' GNO'
F2
06
01
C5
Cl
A4
E2
E6
F3
B4
02
05
F4
A3
E4
C4
Bl
B3
E3
F6
PQI
HQ
240
P212
P213
P214
P215
BG
Bndry
256tt Scan
VCC'
Cl0
010
A9
74
77
80
P216
B9
83
P217
P218
P220
P221
P222
P223
P224
P225
P226
P227
P228
P229
P230
P231
P232
P233
P234
P235
P236
P237
C9
09
A8
B8
VCC'
A6
C7
B6
A5
GNO'
C6
B5
86
89
92
95
A4
C5
B4
A3
05
C4
B3
B2
98
101
104
107
1'0
'13
116
119
122
125
128
131
134
137
XC4013E
PQ
PQ/HQ PG
HT
HT
BG
IXL
160 I 76tt
208
223t 225t
Pad Name 144tt
1/0 (A14)
C2
A2
P203
P142 P158 P174
1/0,
P143 P159 P175
P204
B2
C3
SGCKI t,
GCK8 tt
(A15)
P205 VCC' VCC'
VCC
P144 P160 P176
GNO' GNO'
GNO
Pl
Pl
Pl
P2
1/0,
P2
P2
P2
P4
C3
04
PGCKl t,
GCKI tt
(AI6)
P3
P3
P5
1/0 (A17)
C4
Bl
P3
1/0
P4
P4
P4
P6
B3
C2
1/0
P5
P5
P5
P7
C5
E5
A2
110, TOI
P6
P6
P6
P8
03
110, TCK
B4
P7
P7
P7
P9
Cl
P8
P8
Pl0
C6
02
110
A3
1/0
P9
P9
Pl1
G6
P12
B5
E4
1/0
P13
B6
01
110
05
E3
110
06
1/0
E2
Pl0
Pl0
P14 GNO' GNO'
GNO
P8
A4
1/0
P9
Pl1
Pl1
P15
F5
P12
P12
P16
A5
El
1/0
Pl0
I/O,TMS
Pl1
P13
P13
P17
B7
F4
A6
1/0
P12
P14
P14
P18
F3
VCC' VCC'
VCC
PQI
HQ
240
P238
P239
BG
Bndry
256tt Scan
P240
Pl
P2
VCC'
GNO'
Bl
P3
P4
P5
P6
P7
P8
P9
Pl0
Pl1
P12
P13
P14
P15
P16
P17
P18
P19
C2
02
03
E4
Cl
01
E3
E2
El
F3
F2
GNO'
G3
G2
Gl
H3
VCC'
A2
C3
140
143
:146
149
152
155
158
161
164
167
170
173
176
179
182
185
188
191
November 10, 1997 (Version 1.4)
~XILINX
rxc4013E.
-,-PQ
HT
160
Pad Name 144tt
110
110
110
110
P13
110
P15
P14
P16
110
110
P15
P17
110
P16
P18
P17
P19
GNO
VCC
P18
P20
110
P19
P21
P20
P22
110
P21
110
P23
110
P22
P24
110
110
110
110
VCC
110
P23
P25
P24
P26
liD
liD
P25
P27
P26
P28
110
GNO
P27
P29
110
liD
liD
110
110
P30
110
P31
P28
P32
liD
110
P29
P33
P34
110
P30
liD
P31
P35
liD
P32
P36
liD,
P33
P37
SGCK2 t,
GCK2tt
O(Ml)
P34
P38
GNO
P39
P35
I (MO)
P36
P40
VCC
P37
P41
P38
P42
I (M2)
liD,
P39
P43
PGCK2t,
GCK3 tt
110 (HOC)
P40
P44
liD
P41
P45
P42
P46
liD
P43
P47
liD
1/0(rnc)
P44
P48
liD
P49
liD
P50
liD
liD
liD
liD
P45
GNO
P51
liD
P46
P52
liD
P47
P53
110
P48
P54
liD
P49
P55
VCC
liD
liD
liD
liD
liD
PSO
P56
liD
P51
P57
liD
P52
P58
110 (INIT)
P53
PS9
P54
P60
VCC
GNO
P61
P55
liD
P56
P62
IXL
PQ/HQ PG
HT
208
176tt
223t
BG
225t
F2
Fl
G4
G3
G2
Gl
G5
H3
GNO'
VCC'
H4
H5
J2
Jl
J3
J4
J5
Kl
VCC'
PQI
BG
Bndry
256tt Scan
P34
P35
P36
P37
P38
P39
P40
P41
K3
J6
L1
GNO'
L2
K4
L3
Ml
K5
M2
L4
Nl
M3
N2
K6
Pl
H2
Hl
J2
Jl
K2
K3
Kl
Ll
GNo'
VCC'
L2
L3
L4
Ml
M2
M3
Nl
N2
VCC'
Pl
P2
Rl
P3
GNo'
Tl
R3
T2
Ul
T3
U2
Vl
T4
U3
V2
Wl
V3
194
197
200
203
206
209
212
215
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
07
08
C8
A7
B8
A8
B9
C9
GNO'
VCC'
Cl0
Bl0
A9
Al0
All
Cll
011
012
VCC'
Bll
A12
B12
A13
GNO'
013
014
B13
A14
A15
C13
B14
A16
B15
C14
A17
B16
HQ
240
P20
P21
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P42
P43
P44
P45
P46
P47
P48
P49
P50
P55
P56
P57
C15
N3
GNO' GNO'
A18
P2
VCC' VCC'
C16
M4
B17
R2
P58
PS9
P60
P61
P62
P63
W2
GNO'
Yl
VCC'
W3
Y2
290
P48
P49
P50
P51
P52
P53
P54
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P60
P61
P72
P73
P62
P63
P64
P65
P66
P67
P68
P74
P75
P76
P77
P78
P79
P80
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P84
P85
P86
P87
P88
P89
P90
P91
P92
W4
V4
U5
Y3
Y4
V5
W5
Y5
V6
W6
Y6
GNO'
W7
Y7
V8
W8
VCC'
Y8
U9
Y9
Wl0
Vl0
Yl0
Yll
Wl1
VCC'
GNO'
Vll
298
301
304
307
310
313
316
319
322
325
328
P55
P56
P57
P58
P59
E16
C17
017
B18
E17
F16
C18
018
F17
E15
F15
GNO'
E18
F18
G17
G18
VCC'
H16
H17
G15
H15
H18
J18
J17
J16
VCC'
GNo'
K16
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P29
P30
P31
P32
P33
P33
P34
P35
P36
P37
November 10, 1997 (Version 1.4)
K2
P3
L5
N4
R3
P4
K7
M5
R4
N5
P5
L6
GNO'
R5
M6
N6
P6
VCC'
R6
M7
N7
P7
R7
L7
N8
P8
VCC'
GNO'
L8
218
221
224
227
230
233
236
239
242
245
248
251
254
257
260
263
266
269
272
275
278
281
284
287
293
294
295
331
334
337
340
343
346
349
352
355
358
361
364
367
XC4013E
PQ
PQ/HQ PG
HT
HT
BG
!XL
160 176tt
208
223t 225t
Pad Name 144tt
110
P57
P63
P69
P81
K17
P9
K18
liD
P58
P64
P70
P82
R9
liD
P71
L18
N9
P65
P59
P83
liD
P72
P84
L17
M9
L16
liD
P73
P85
L9
liD
L15
Rl0
liD
M15
Pl0
VCC' VCC'
VCC
M18 Nl0
liD
P60
P66
P74
P86
P61
P67
P75
P87
M17
K9
liD
110
P62
P68
P76
P88
N18
Rll
P18
liD
P63
P69
P77
P89
Pll
GNO
P64
P70
P78
P90 GNO' GNO'
liD
N15
Ml0
liD
P15
Nll
N17
R12
liD
P91
liD
P92
R18
Ll0
liD
P71
P79
P93
T18
P12
liD
P72
P17
Mll
P80
P94
P73
P81
P95
N16
R13
liD
P65
liD
T17
N12
P74
P82
P96
P66
liD
P67
P75
P83
P97
R17
P13
P76
P84
P16
liD
P68
P98
Kl0
P77
P85
P99
U18
R14
liD
P69
P70
P78
P86
Pl00
T16
N13
liD,
SGCK3 t,
GCK4 tt
GNO
P71
P79
P87
Pl0l GNO' GNO'
DONE
P72
P80
P88
Pl03
U17
P14
VCC
P81
P73
P89
Pl06 VCC' VCC'
PROP74
P82
P90
Pl08
V18
M12
GRAM
T15
liD (07)
P75
P83
P91
Pl09
P15
U16
N14
P84
P110
liD,
P76
P92
PGCK3 t,
GCK5 tt
liD
P77
P85
P93
Pl11
T14
L11
Pl12
U15 M13
liD
P78
P86
P94
liD
R14
N15
liD
R13 M14
1/0(06)
Pl13
V17
Jl0
P87
P79
P95
liD
Pl14
V16
L12
P88
P96
P80
Pl15
liD
P89
P97
T13
M15
Pl16
U14
L13
liD
P90
P98
liD
Pl17
V15
L14
liD
Pl18
V14
Kll
GNO
P81
P91
P99
Pl19 GNo' GNO'
R12
liD
L15
liD
Rll
K12
U13
liD
P82
P92 Pl00
P120
K13
liD
V13
K14
P83
P93 Pl0l
P121
VCC
VCC' vec'
1/0(05)
P84
P94 Pl02
P122
U12
K15
V12
I/O(CSO)
P85
P95 Pl03
P123
J12
liD
Pl04
P124
Tll
J13
liD
Pl05
P125
Ull
J14
P126
Vll
liD
P86
P9S Pl06
J15
P97 Pl07
liD
P127
Vl0
Jll
P87
1/0(04)
P88
P98 Pl08
P128
Ul0 H13
liD
P89
P99 Pl09
P129
Tl0
H14
P130 VCC' VCC'
VCC
P90 Pl00 Pll0
P91
Pl0l Plll
P131 GNO' GNo'
GNO
1/0(03)
P92 Pl02 Pl12
P132
T9
H12
P133
Hll
1I0(RS)
P93 Pl03 Pl13
U9
liD
P94 Pl04 Pl14
P134
V9
G14
P135
liD
P95 Pl05 Pl15
V8
G15
liD
Pl16
P136
G13
U8
P137
T8
G12
110
Pl17
liD (02)
P138
V7
Gll
P96 Pl06 Pl18
U7
110
P97 Pl07 Pl19
P139
F15
VCC
VCC' VCC'
110
P98 Pl08 P120
P140
V6
F14
P141
U6
F13
liD
P99 Pl09 P121
110
R8
Gl0
-
PQI
HQ
240
P93
P94
P95
P96
P97
P99
Pl00
Pl0l
Pl02
Pl03
Pl04
Pl05
Pl06
Pl07
Pl08
Pl09
Pll0
Plll
Pl12
Pl13
Pl14
Pl15
Pl16
Pl17
Pl18
BG
Bndry
256tt Scan
Pl19
P120
P121
P122
GNO'
Y20
VCC'
V19
P123
P124
U19
U18
439
442
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P13?
P138
P139
P140
P141
P142
P144
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
P155
P156
P157
P159
P160
P161
P162
P163
P164
T17
V20
U20
T18
T19
T20
R18
R19
R20
P18
GNO'
P20
N18
N19
N20
VCC'
M17
M18
M20
L19
L18
L20
K20
K19
VCC'
GNo'
K18
K17
J20
J19
J18
J17
H19
H18
VCC'
G19
F20
G18
445
448
451
454
457
460
463
466
469
472
Ull
Y12
W12
V12
U12
V13
Y14
VCC'
Y15
V14
W15
Y16
GNO'
V15
W16
Y17
V16
W17
Y18
U16
V17
W18
Y19
V18
W19
370
373
376
379
382
385
388
391
394
397
400
403
406
409
412
415
418
421
424
427
430
433
436
475
478
481
484
487
490
493
496
499
502
505
508
511
514
517
520
523
526
529
532
535
538
541
4-119
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4013E
PQ
PQJHQ PG
HT
HT
BG
/XL
208
160 176tt
223t 225t
Pad Name 144tt
1/0
R7
E15
GND
Pl00 Pll0 P122
P142 GND' GND'
1/0
R6
E14
1/0
R5
F12
1/0
P143
E13
V5
1/0
P144
V4
015
1/0
Plll P123
P145
U5
Fll
1/0
Pl12 P124
P146
T6
014
110(01)
Pl0l P113 P125
P147
E12
V3
1/0 (RCI:K, Pl02 P114 P126
P148
V2
C15
RDYI
PQI
HQ
240
P165
P166
P167
P168
P169
P170
P171
P172
P173
P174
Bndry
BG
256tt Scan
F19
GND'
18
E19
020
E18
019
C20
E17
018
c
547
550
553
556
559
562
565
568
Pl03
Pl04
Pl05
Pl15
P116
Pl17
P127
P128
P129
P149
P150
P151
U4
T5
U3
013
C14
FlO
P175
P176
Pl77
C19
B20
C18
571
574
577
Pl06
Pl18
P130
P152
T4
B15
P178
819
580
Pl07
Pl08
Pl09
Pll0
Plll
Pl19
P120
P121
P122
P123
P131
P132
P133
P134
P135
P153
P154
P159
P160
P161
P179
P180
P181
P182
P183
A20
VCC'
A19
GND'
B18
0
Pl12
P124
P136
P162
Ul
B13
P184
B17
5
Pl13
Pl14
Pl15
P125
P126
P127
P137
P138
P139
P163
P164
P165
P3
R2
T2
Ell
C12
A13
P185
P186
P187
C17
016
A18
8
11
14
Pl16
P128
P140
P166
Pl17
P129
P130
P141
P142
P167
P168
P169
P170
P171
P172
P173
P188
P189
P190
P191
P192
Pl.93
P194
P196
P197
P198
P199
P200
P201
P202
P203
P205
P206
P207
A17
C16
B16
A16
C15
B15
A15
GND'
B14
A14
C13
B13
VCC'
C12
B12
A12
Bll
Cl1
17
20
23
26
29
32
35
50
53
56
59
62
P208
All
65
P209
P210
P211
Al0
Bl0
GND'
68
71
Vl
C13
VCC' VCC'
U2
A15
GND' GND'
T3
A14
PQ/HQ208
544
BOSY)
1/0
1/0
110(00,
DIN)
110,
SGCK4 t,
GCK6 tt
(DOUT)
CCLK
VCC
O,TDO
GND
110 (AO,
Additional XC4013E/XL Package Pins
I
I
I
P3
P104
P158
I
I
I
D3
Rl0
I
I
D10
R15
I
I
C7
G16
R9
5/5/97
I
I
I
C12
K4
R16
I
I
I
Pl
P102
P157
5/5/97
Pl18
Pl19
P120
P131
P132
P133
P121
P122
P134
P135
P123
P143
P144
P145
P136
P137
P146
P147
P148
P149
P150
P174
P175
P176
Pl77
P178
P124
P138
P151
P179
P125
P126
P127
P139
P140
P141
P152
P153
P154
P180
P181
P182
N3
B12
P4
F9
N4
011
P2
A12
Tl
Cll
Rl
Bll
N2
El0
GND' GND'
Pl
All
Nl
010
M4
Cl0
L4
Bl0
VCC' VCC'
M2
Al0
Ml
09
L3
C9
L2
B9
Ll
A9
Kl
E9
K2
C8
K3
B8
GND' GND'
P53
P155
P208
I
I
J15
I
GND Pins
D4
I D9
K15
I M3
T7
I T12
I
I
I
D15
M16
I
I
I
P54
P156
VCC Pins
D16
I J4
I
R4
I
I
I
G3
R3
I
BG225
2
B2
Rl
B14
R8
A1
G8
H8
J9
5/5/97
A8
G9
H9
K8
VCC Pins
D8
R15
GND Pins
D12
H2
Hl0
M8
H1
1
H15
I
G7
H7
J8
F8
H6
J7
The BG225 package pins in this table are bonded to an internal
Ground plane on the XC4013E die. They must all be externally connected to Ground.
PQIHQ240
P22*
P204*
I
I
P37*
P219*
I
I
GND Pins
P83*
P98*
I
I
I
P143*
I
I
P158*
I
Not Connected Pins
38
41
44
47
, Pads labelled GNO' or VCC' are internally bonded to Ground or
VCC planes within the package. They have no direct connection to
any specific package pin.
t = E only, tt = XL only
4-120
I
I
I
PG223
INS)
1/0,
PGCK4t,
GCK7 tt
(Al)
1/0
1/0
110 (CS1,
A2)
1/0 (A3)
1/0
1/0
1/0
1/0
1/0
1/0
GND
110
1/0
1/0
1/0
VCC
1/0(A4)
1/0 (A5)
1/0
110
1/0
(A21) tt
1/0
(A20) tt
1/0(A6)
1/0 (A7)
GND
6/9/97
Not Connected Pins
P51
I P52
Pl05
I Pl07
P206
I P207
P195
6/9197
I
I
I
I
I
:t: Pins marked with this symbol are used for Ground connections on
some revisions of the device. These pins may not physically connect to anything on the current device revision. However. they
should be externally connected to Ground. if possible.
BG256
~
E20
K4
R4
U15
D6
Fl
L17
R17
V7
Al
G20
U4
B7
H4
U8
I
A7
J4
Y13
6/4/97
A13
M4
I
VCC Pins
D7
Dll
F4
F17
P4
P17
U6
U7
W20
GND Pins
D4
D8
H17
N3
U17
U13
Not Connected Pins
D12
C8
M19
V9
D14
G4
P19
U10
D15
G17
R2
U14
D13
N4
W14
D17
N17
H2O
W9
J3
W13
November 10, 1997 (Version 1.4)
~XILINX
Pin Locations for XC4020E/XL Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the availability
charts elsewhere in the XC4000 Series data sheet for availability information.
XC4020EIXL
Pad Name
vee
I/O (AS)
I/O (A9)
I/O (A19) tt
I/O (A18) tt
I/O
I/O
I/O (Al0)
I/O (All)
I/O
I/O
VOC
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O (A12)
I/O (A13)
I/O
I/O
I/O
I/O
I/O M4
I/O,SGCKl t,
GCKBtt (A15)
VCC
GNO
I/O, PGCKl t,
GCKl tt (A16)
I/O (All)
I/O
I/O
I/O, TDI
I/O, TCK
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O, lMS
I/O
vee
HT
144ft
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
PQ
HT
176ft
P155
P156
P157
P158
P159
P160
P161
P147 P162
P148' Pl63
l60tt
Pl42
Pl43
Pl44
PI45
Pl46
HQ208t
PQ208tt
P183
P184
P185
P186
P187
P188
P189
P190
P191
VOC'
H4
G4
Fl
El
GNO'
F2
01
Cl
E2
F3
,02
F4
E4
81
HQ240t
PQ240tt
P212
P213
P214
P215
P216
P217
P218
P220
P221
as
09
09
AS
88
C8
A7
VOO'
A6
07
GNO'
06
85
A4
05
84
A3
05
C2
B2
B6
A5
P164
PI65
Pl66
P13S
P139
P152
Pl53
PI54
P155
P167
Pl68
Pl69
P170
P171
P192
P193'
P194
P195
P196
P197
P198
P199
'P200
P140
P141
P142
PI43
P156
P157
P158
P159
P172
P173
P174'
P175
P201
P202
P203
P204
P144
Pl
P2
P160
PI
P2
P176
Pl
P2
P205
P2
P4
VCC'
GNO'
C3
P240
Pl
P2
VCC'
GNO'
Bl
P3
P4
PS
P6
P7
P3
P4
P5
P6
P7
P8
P9
P3
P4
P5
P6
P7
P8
P9
P5
.P6
P7
P8
C4
B3
C5
A2
P3
P4
P5
P6
P7
P8'
P9
Pl0
Pll
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
02
02
03
E4
01
01
E3
E2
El
F3
F2
GNO'
G3
G2'
Gl
H3
VOC'
H2
Hl
J4
J3
J2
Jl
K2
P8
P9
Pl0
Pl1
P12
P13
P14
P15
P16
P17
Pr8
~19
P20
P21
P22
Pl0
Pl1
P12
P13
P14
P1S
P16
P17
P18
P19
P20
P21
P22
P23
P24
-c
P23
I/O
VOO'
010
010
A9
P222
P223
P224
P225
P226
P227
P228
P229
P230
P231
P232
P233
P234
P235
P236
P237
P238
P239
Pl0
Pl1
P12
P13
P14
E3
/'9,
B4
Pl0
Pl1
P12
P13
C6
A3
P14
P15
P16
P17
P18
B5
B6
05
06
GNO'
A4
A5
B7
AS
VCO"
07
08
,-
vee
BG Bndry
256ft Scan
Pl49
P150
P151
.;,
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PG
223t
VOO'
J3
J2
Jl
Hl
H2
H3
Gl
G2
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28.
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P3j
P32
,C8
A7
B8
A8
B9
C9
GNO'
VCC'
010
Bl0
A9
,Al0
All
011
P23
P24
P25
P26
P27
P28
P29
P30
P31
P33
011
012
VOO·
811
P38
P39
P40
P41
~2
P33
P34
P3S
P36
~'
P25
P29
"
November 10, 1997 (Version 1.4)
C4
B3
B2
A2
C3
K3
Kl
U
GNO'
VCC'
L2
L3
L4
Ml
M2
M3
M4
Nl
N2
VOO'
Pl
86
89
92
95
98
101
104
107
110
113
116
119
122
125
128
131
134
137
140
143,
152
155
158
161
164
167
170
'173
176
179
182
185
194
19,
200
203
206
209
212
215
218
221
224
227
230
233
236
239
242
245
248
'251
254
257
260
263
266
269
272
278
281
284
XC4020ElXL
Pad Name
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O
liD
I/O
I/O
liD
liD
1i0,SGOK2t,
GOK2tt
O(Ml)
GNO
I (MO)
VOO
I (M2)
IiOPGOK2t,
GCK3tt
liD (HOO)
liD
liD
liD
1i0(mG)
PQ
HT
HT
144tt l60tt 176ft
P24
P26
P30
P25
P27
P31
P26
P28
P32
P27
P29
P33
HQ208t
PQ208tt
P34
P35
P36
P37
P28
P29
P30
P31
P32
P33
P30
P31
P32
P33
P34
P3S
P36
P37
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
liD
liD
liD
liD
liD
liD
.p45
liD
liD
P46
P47
P48
P49
liD
HQ240t
PQ240tt
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P38
P39
P40
P41
P42
P43
P42
P43
P44
P45
P46
P47
P48
P49
P50
P55
P56
P57
015
GNO'
A18
VOO'
016
B17
P58
P59
P60
P61
P62
P63
W2
GNO'
Yl
VOO'
W3
Y2
338
P44
P45
P46
P47
P46
P49
P5D
P48
P49
P50
P51
P52
P53
P54
P58
P59
P60
- P61
P62
P63
P64
P65
PB6
P67
P68
P69
P70
Pl1
W4
V4
U5
Y3
Y4
V5
W5
Y5
VB
W6
Y6
GNO'
W7
Y7
385
388
391
394
P60
P61
P72
P73
P64
PB5
PB6
pe7
PB8
PB9
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
346
349
352
355
358
367
370
373
376
379
382
P55
P56
P57
P58
P59
E16
017
017
B18
El7
F1B
018
018
F17
E15
F15
GNO'
E18
F18
<317
G18
VCO'
H16
H17
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
G15
H15
H18
J18
J17
J16
VOO'
GNO'
K16
K17
K18
US
L17
US
Pa4
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
L15
M15
VOO'
M18
M17
N18,
P18
GND'
N1S
P15
N17
R18
T18
P17
P99
Pl00
Pl01
Pl02
Pl03
Pl04
Pl05
Pl06
Pl07
Pl08
Pl0S
,Pl10
Pll1
P112
'-
GNO
1(0
P34
P35
P36
P37
P38
P39
P40
P41
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
PG
223t
A12
B12
A13
GNO'
013
014
B13
A14
A15
013
B14
A16
B15
014
A17
B16
P51
P52
P53
P54
P56
VOO
1(0
liD
liD
liD
liD
liD
liD
liD
1(0
liD (lRlT)
VOO
GNO
liD
liD
I/O
liD
I/O
I/O
I/O
I/O
I/O
I/O
VOO
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
P50
P51
P52
P53
P54
P55
PS6
P57
PS8
P59
P56
P57
P58
PS9
P60
P61
P62
P63
P64
P65
..
'-,
P60
P6l
P62
P63
P64
pell
P67
P68
P69
P70
P74
P75
P76
-P77
P78
P86
P87,
P88
P89
P90
P79
P80
P91
P92
P93
P94
I/O
I/O
I/O
pao
P81
P82 '
P8S
P84
P85
P71
P72
BG
Bndry
256tt Scan
P2
287
290
Rl
P3
293
GNO'
Tl
296
R3
299
T2
302
Ul
305
T3
308
U2
311
Vl
320
T4
323
U3
326
V2
329
WI
332
V3
335
V8
W8
VOO'
Y8
U9
V9
W9
Y9
Wl0
Vl0
Yl0
Yll
Wl1
VCO'
GNO'
Vl1
Ul1
Y12
W12
V12
U12
Y1S
W13
V13
Y14
VCC'
Y1S
V14
W15
Y16
GND'
V15
W16
Y17
V16
Wt7
Y18
341
342
343
397
400
403
406
409
412
415
418
421
424
427
430
433
436
439
442
445
448
451
454
457
460
463
466
469
472
475
478
481
484
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
1~
P68
P69
P70
P73
P74
P75
P76
P77
P78
lIT
17&tt
P81
P82
PB3
P84
PBS
P86
HQ208t
PQ20Btt
P95
P96
P97
P98
P99
Pl00
223t
N16
T17
R17
P16
U18
T16
HQ24(}f
PQ24(}ft
P113
P114
P115
P116
Pl17
P118
P71
P72
P73
P74
P75
P76
P79
Peo
P81
P82
P83
P84
P87
PBB
P89
P90
P91
P92
Pl0l
Pl03
Pl06
Pl08
Pl09
PlIO
GNO'
U17
VCC'
V18
TIS
U16
P119
P120
P121
P122
P123
P124
GNO'
Y20
VCC'
V19
UI9
U18
I/O
I/O
I/O
I/O
P77
P7a
PBS
pa6
P93
P94
PIlI
P112
1/0(06)
P79
Pao
P125
P126
P127
P12a
P129
P130
P131
P132
P133
P13'
P135
P136
P137
P138
P139
PI40
P141
PI42
T17
V20
U20
Tla
Tl9
XC4020E/XL
Pad Name
I/O
I/O
I/O
I/O
I/O
1/0, SGCK3 t,
GCK4tt
GNO
DONE
VCC
I'l'iOGRAIiiI
1/00
1/0, PGCK3 t,
GCKStt
I/O
I/O
I/O
I/O
110
GNO
110
I/O
I/O
110
vee
110(05)
1/0 (CSO)
110
110
I/O
I/O
110
1/0(04)
I/O
vee
GNO
1/0(03)
1/0 (RS)
110
lIT
144tt
P65
P65
P67
Pl00
PIOI
P120
P121
P84
P85
P94
P95
Pl02
Pl03
P122
PI23
Pl04
Pl05
Pl06
PI07
Pl08
PI09
PlIO
PIlI
P112
P113
P114
PIIS
P116
P117
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
PI34
P13S
P136
P137
TIl
Ull
VII
Vl0
Ul0
Tl0
VCC'
GNO'
T9
U9
V9
V8
U8
T8
PI44
P14S
PI46
PI47
PI48
PI49
PISO
P1S1
P1S2
PIS3
PIS4
PISS
P1S6
PIS7
V7
U7
VCC'
V6
U6
R8
R7
GNO'
R6
RS
VS
V4
US
T6
V3
V2
P1S9
PI60
P161
P162
P163
P164
P16S
PI66
P167
P168
P169
P170
P171
P172
P173
P174
P86
pa7
P8e
P89
P90
P91
P92
P83
P94
P99
P96
P97
P96
poo
Pl00
Pl0l
PI02
Pl03
Pl04
Pl0S
Pl06
Pl07
P118
P119
P138
P139
P96
P99
PI08
Pl09
P120
P121
P140
P141
Pl00
PlIO
PI22
P142
I/O
vo
I/O
VO(OO, DIN)
1/0, SGCK4 t,
GCK6 tt (DOUT)
CCLK
VCC
O,TOO
GNO
VO (AO, WS
VO, PGCK4t,
GCK7 tt (AI)
110
110
1/0 CS1,A2)
1/0 (AS)
4-122
U16
V17
W18
Y19
V18
Wl9
P92
P93
P91
P113
P114
P115
P116
P117
P118
P119
P96
P97
VO(RCLK,
ROYIBUSy)
Scan
493
496
499
502
505
508
P82
P83
P81
P95
P96
P97
P98
1/0(02)
110
VCC
VO
VO
I/O
I/O
I/O
I/O
I/O
I/O.
I/O 01)
Bndry
RIa
R19
R20
PIB
GNO'
P20
N18
N19
N20
VCC'
M17
M18
MI9
M20
L19
L18
L20
K20
K19
VCC'
GNO'
K18
K17
J20
J19
J18
J17
H2O
H19
H18
VCC'
G19
F20
G18
F19
GNO'
F18
E19
020
E18
019
C20
E17
018
Pa7
P88
pa9
P90
P95
GNO
BG
256tI
TI4
U15
R14
R13
V17
V16
Tl3
U14
VIS
V14
GNO'
R12
Rll
U13
V13
VCC'
U12
V12
I/O
I/O
I/O
I/O
vo
PG
T20
Pl0l
Pl02
PIlI
P112
PI13
P114
P123
PI24
P12S
PI26
PI43
PI44
P14S
P146
P147
PI48
Pl03
PI04
Pl0S
Pl06
Pl1S
P116
PI17
P118
P127
PI28
PI29
P130
P149
P1S0
P1Sl
P1S2
U4
TS
U3
T4
P17S
P176
PI77
PI78
C19
B20
C18
B19
PI07
Pl08
PI09
PlIO
PIlI
PI12
P119
P120
P121
P122
P123
P124
P131
P132
P133
P134
P13S
P136
P1S3
P1S4
P1S9
P160
P161
P162
VI
VCC'
U2
GNO'
T3
Ul
P179
P180
P181
P182
P183
P184
A20
VCC'
A19
GNO'
B18
B17
P113
P114
PllS
PI16
PI25
PI26
P127
P128
P137
P138
PI39
P140
P163
P164
P16S
P166
P3
R2
T2
N3
P185
P186
P187
P1S8
C17
016
A18
A17
XC402OE1XL
Pad Name
110
110
PQ
lIT
lIT
144tt 16(}ft 176tt
I/O
I/O
P117
P129
P130
Pl.l
P142
Pl1B
P119
P120
PI31
P132
P133
P143
P144
P14S
P167
P168
P169
P170
P171
P172
P173
P121
P122
PI34
P135
P123
P124
P12S
P126
P127
P136
PI37
PI38
PI39
P140
P141
P146
P147
P14B
P149
P1S0
P1Sl
P1S2
P153
P154
PI74
P175
P176
PI77
PI78
PI79
PIBO
PIBI
P1B2
110
110
GNO
I/O
110
I/O
I/O
511
514
VCC
517
520
523
526
535
53a
541
544
547
550
1/0 A4
1/0 (AS
553
556
559
562
565
568
574
577
580
583
586
589
592
PO
HQ20Bt
PQ206tt
22~
P4
N4
P2
Tl
Rl
N2
GNO'
PI
Nl
M4
L4
VCC'
I/O
I/O
110
VO
I/O (A21) tt
I/O (A20)tt
VO(A6)
VO(A7)
GNO
M2
Ml
L3
L2
Ll
Kl
K2
K3
GNO'
HQ24(}f
BG Bndry
PQ24C1J:t ~ Scan
P189
C16
26
PI90
B16
29
P191
A16
32
PI92
CI5
35
PI93
BIS
38
P194
41
AIS
P196
GNO'
P197
814 ·44
P198
AI.
47
PI99
C13
50
P200
813
53
P201
VCC'
A13
56
012
59
P202
C12
62
P203
812
65
P205
A12
68
P206
Bl1
71
P207
Cll
74
P208
All
77
P209
Al0
BO
P210
810
83
P211
GNO'
6/24/97
t = E only
tt =XLonly
Additional XC4020E/XL Package Pins
PQ/HQ208
PI
Pl02
P157
J
I
I
P3
Pl04
P158
J
J
010
R15
I
I
I
Not Connected Pins
P51
I P52
Pl05
I Pl07
P206
I P207
J
J
P53
P155
P208
J
I
P54
P156
J
J
J15
J
J
R4
I
J
015
M16
I
J
J
G3
R3
J
J
P143*
J
J
P158*
J
I
J
5/5/97
PG223
595
598
601
604
607
610
613
619
622
625
628
631
834
637
640
543
546
649
652
655
658
667
670
673
676
0
2
5
8
11
14
17
03
Rl0
I
C7
G16
R9
C12
K4
R16
J
J
I
VCCPlns
016 J
J4
J
GNDPins
04
I 09
K15
M3
T7
T12
5/5/97
J
PQ/HQ240
P22*
P204*
P195
J
J
P37*
P219*
I
J
J
I
GNDPins
P83* J
P98*
Not Connected Pins
J
6/9/97
:j: Pins marked with this symbol are used for Ground connections on
some revisions of the device. These pins may not physically connect to anything on the current device revision. However, they
should be externally connected to Ground, if possible.
8G256
C14
E20
K4
R4
U15
06
Fl
LI?
R17
Al
G20
U4
B7
H4
U8
V7
VCCPins
07
011
F4
F17
P4
P17
U7
U6
W20
GNDPlns.
04
08
HI?
N3
U13
U17
.1
.1
014
G4
P19
Ul0
015
G17
R2
U14
013
N4
W14
017
N17
6/17/97
November 10, 1997 (Version 1-4)
~XILINX
Pin Locations for XC4025E, XC4028EX/XL Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the availability
charts elsewhere in the XC4000 Series data sheet for availability information.
XC4025E,
XC4028
EX/XL
Pad Name
VCC
I/O (A8)
I/O (A9)
I/O (A19)t
I/O (A18)t
I/O
I/O
I/O (A10)
I/O (A11)
GNO
I/O
I/O
I/O
HQ
HQ
PG
160tt 208* 223t
HQ
240
P142
P143
P144
P145
P146
P183 VCC' P212
P184
P213
J3
P185
J2
P214
P186
J1
P215
P187 H1
P216
P188 H2 P217
P189 H3 P218
P147 P190 G1
P220
P148 P191
G2 P221
110
VCC
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
110
I/O (A12)
I/O (A13)
GNO
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O (A14)
I/O.
SGCK1 t,
GCK8:j:
(A15)
VCC
GNO
I/O,
PGCK1 t,
GCK1:j:
(A16)
I/O (A17)
I/O
I/O
I/O, TOI
I/O, TCK
I/O
I/O
VCC
GNO
I/O
I/O
I/O
I/O
I/O
110
I/O
P149
P15.0
P151
VCC'
H4
G4
P192
F1
P193 E1
P194 GNO'
P195
P196
P152 P197
P153 P198
P154 P199
P155 P200
F2
01
C1
E2
F3
02
P222
P223
P224
P225
P226
P227
P228
P229
P230
P231
P232
P233
-
P1S6 ~P157 P202
P158 P203
P159 P204
P160
P1
P2
P3
P4
P5
P6
P7
P8
P9
F4
E4
B1
E3
C2
B2
P234
P235
P236
P237
P238
P239
BG
256tt
PG
299
VCC' VCC'
C10
K2
010
K3
A9
K5
69
K4
C9
J1
09
J2
A8
H1
68
J3
GNO' GNO'
J4
J5
C8
H2
A?
G1
VCC' VCC'
A6
H3
C7
G2
66
H4
A5
F2
GNO' GNO'
H5
G3
01
C6
B5
G4
A4
E2
C5
F3
B4
G5
A3
C1
GNO' GNO'
VCC' VCC'
F4
E3
05
02
C4
C2
B3
F5
B2
E4
A2
03
C3
C3
HQ
304
P38
P37
P36
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
P25
P23
P22
P21
P2Q
P19
P18
P17
P16
P15
P14
P13
P12
P10
P9
P8
P7
P6
P5
P4
P3
P2
BG Bndry
352* Scan
VCC'
014
C14
A15
615
C15
015
A16
616
GNO'
C16
617
C17
618
VCC'
C18
017
A20
B19
GNO'
C19
018
A21
B20
C20
B21
B22
C21
GNO'
VCC'
020
A23
021
C22
B24
C23
022
C24
P1
P205 VCC' P240 VCC' VCC'
VCC'
P2 GNO' P1
GNO' GNO' P304 GNO'
P4
P2
61
04
P303 023
C3
P5
P6
P7
P8
P9
P10
P11
P12
P13
C4
63
C5
A2
64
C6
A3
65
66
05
06
P3
P~-
P5
P6
P7
P8
P9
P10
P11
P12
P13
C2
02
62
63
l---O3
E6
E4
05
C1
C4
A3
06
VCC' VCC'
GNO' GNO'
0.1
E7
E3
64
E2
C5
E1
A4
F3
07
F2
C6
E8
November 10, 1997 (Version 1.4)
P302
P301
P300
P299
P298
P297
P296
P295
P294
P293
P292
P291
P290
P289
C25
024
E23
C26
E24
F24
E25
VCC'
GNO'
026
G24
F25
F26
H23
H24
G25
98
101
104
107
110
113
116
119
122
125
128
131
134
137
140
143
146
149
152
155
158
161
164
167
170
173
176
179
182
185
188
191
194
197
200
203
206
209
212
215
-
218
221
224
227
230
233
236
XC4025E,
HQ
HQ
XC4028
EX/XL
160tt 208*
Pad Name
I/O
P14
GNO
P10
I/O
P11
P15
I/O
P12
P16
I/O, TMS
P13
P17
I/O
P14
P18
VCC
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
P19
I/O
P20
I/O
P15
P21
P22
I/O
P16
I/O
P23
P17
I/O
P18
P24
P25
GNO
P19
VCC
P20
P26
I/O
P21
P27
I/O
P28
P22
I/O
P29
P23
I/O
P24
P30
P31
VO
I/O
P32
I/O
I/O
GNO
I/O
I/O
I/O
I/O
VCC
I/O
P33
P25
P26
P34
I/O
I/O
P27
P35
I/O
P2B
P36
GNO
P29
P37
I/O
I/O
I/O
I/O
I/O
P38
I/O
P39
I/O
P40
P30
I/O
P31
P41
GNO
VCC
I/O
I/O
P32
P42
110
I/O
P33
P43
I/O
P34
P44
I/O
P35
P45
I/O
P36
P46
P47
I/O,
P37
SGCK2t,
GCK2:j:
o (M1)
P38
P48
P49
GNO
P39
PG
223t
HQ
240
BG
256tt
PG
299
HQ
304
BG Bndry
352* Scan
B14
A16
B15
C14
A17
B16
P52
P53
P54
P55
P56
P57
P288 G26
65
GNO' GNO' P287 GNO'
P286
G3
66
J23
P285 J24
G2
08
G1
P284 H25
C7
H3
B7
P283 K23
VCC' VCe' P282 VCC'
H2
P280 K24
C8
H1
E9
P279 J25
P278 L24
A7
P277 K25
09
GNO'
GNO' GNO'
J4
B8
P276 L25
J3
A8
P275 L26
J2
C9
P274 M23
J1
P273 M24
B9
K2
E10 P272 M25
K3
A9
P271 M26
K1
010 P270 N24
L1
C10 P269 N25
GNO' GNO' P268 GNO'
VCC' VCC' P267 VCC'
L2
B10 P266 N26
L3
B11 P265 P25
L4
C11 P264 P23
M1
E11 P263 P24
M2
011 P262 R26
M3
A12 P261 R25
M4
B12 P260 R24
A13 P259 R23
GNO' GNO'
GNO'
C12 P258 T26
012 P257 T25
N1
E12 P256 T23
N2
B13 P255 V26
VCC' VCC' P253 VCC'
P1
A14 P252 U24
P2
C13 P251 V25
Rl
614 P250 V24
P3
013 P249 U23
GND' GNO' P248 GNO'
615 P247 Y26
E13 P246 W25
T1
C14 P245 W24
R3
A17 P244 V23
T2
014 P243 AA26
U1
B16 P242 Y25
T3
C15 P241 Y24
U2
E14 P240 AA25
GNO'
GNO' GNO'
VCC'
VCC' VCC'
A18 P239 AB25
015 P238 AA24
V1
C16 P237 Y23
T4
B17 P236 AC2.6
U3
B18 P235 AA23
V2
E15 P234 AB24
W1
016 P233 A025
V3
C17 P232 AC24
C15
GNO'
P58
P59
W2
A20 P231 AB23
GNO' GNO' P230 GNO'
GNO'
A4
A5
67
A6
VCC'
07
08
P14
P15
P16
P17
P18
P19
P20
P21
P22
C8
A7
B8
A8
B9
C9
GNO'
VCC'
C10
B10
A9
A10
A11
C11
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
011
012
VCC'
B11
A12
B12
A13
GNO'
013
014
B13
A14
A15
C13
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
239
242
245
248
251
254
257
260
263
266
269
272
275
278
281
284
287
290
293
296
299
302
305
308
311
314
317
320
323
326
329
332
335
338
341
344
347
350
353
356
359
362
365
368
371
374
377
380
383
386
4-123
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4025E,
HQ
HQ
XC4028
PG
EXlXL 160tt 208* 223t
Pad Name
I (MO)
VCC
I (M2)
1/0,
PGCK2t,
GCK3:j:
1/0 (HOC)
110
1/0
1/0
1/0 (LOC)
1/0
1/0
VCC
GNO
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
GNO
1/0
1/0
1/0
1/0
VCC
1/0
1/0
1/0
1/0
GNO
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0 (INIT)
VCC
GNO
110
1/0
1/0
1/0
1/0
1/0
1/0
1/0
GNO
110
1/0
1/0
1/0
VCC
1/0
1/0
1/0
1/0
GNO
1/0
110
1/0
1/0
1/0
4-124
HQ
240
BG
PG
256tt
299
HQ
304
BG
Bndry
352* Scan
XC4025E,
HQ
HQ
XC4028
PG
EX/XL 160tt 208* 223t
HQ
240
BG
PG
256tt
299
HQ
304
BG
Bndry
352* Scan
Pad Name
P40
P41
P42
P43
P50
P55
P56
P57
A18
VCC'
C16
B17
P60
P61
P62
P63
P44
P45
P46
P47
P48
P58
P59
P60
P61
P62
E16
C17
017
B18
E17
P64
P65
P66
P67
P68
W4
V4
U5
Y3
Y4
F16
C18
018
F17
E15
F15
P69
P70
P71
P72
P73
P74
VCC'
GNO'
V5
W5
Y5
V6
W6
Y6
GNO'
E18
F18
G17
G18
VCC'
H16
H17
P75
P76
P77
P78
P79
P80
P81
P82
GNO'
W7
Y7
V8
W8
VCC'
Y8
U9
P83
GNO'
V9
W9
Y9
W10
V10
Y10
Y11
W11
VCC'
GNO'
V11
U11
Y12
W12
V12
U12
Y13
W13
GNO'
P49
P50
P51
P52
P53
P54
P55
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
G15
H15
H18
J18
J17
J16
VCC'
GNO'
K16
K17
K18
L18
L17
L16
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P66
P67
PS8
P69
P70
P86
P87
P88
P89
P90
P91
L15
M15
VCC'
M18
M17
N18
P18
GNO'
N15
P15
N17
Y1
C18 P229 A024
VCC' VCC' P228 VCC'
W3
017 P227 AC23
Y2
B19 P226 AE24
P99
V13
P100 Y14
P101 VCC'
P102 Y15
P103 V14
P104 W15
P105 Y16
P106 GNO'
P107
P108
P109
V15
W16
Y17
C19
F16
E17
018
C20
F17
G16
VCC'
GNO'
019
E18
020
G17
F18
H16
E19
F19
GNO'
H17
G18
G19
H18
VCC'
J16
G20
J17
H19
GNO'
H2O
J18
J19
K16
J20
K17
K18
K19
VCC'
GNO'
L19
L18
L16
L17
M20
M19
N20
M18
GNO'
M17
M16
N19
P20
VCC'
N18
P19
N17
R19
GNO'
N16
P18
U20
P17
T19
P225
P224
P223
P222
P221
P220
P219
P218
P217
P216
P215
P214
P213
P212
P211
P210
P209.
P208
P207
P206
P204
P203
P202
P201
P200
P199
P198
P197
P196
P195
P194
P193
P192
P191
P190
P189
P188
P187
P186
P185
P184
P183
P182
P181
P180
P179
P178
P177
P175
P174
P173
P172
P171
P170
P169
P168
P167
P166
A023
AC22
AF24
A022
AE23
AE22
AF23
VCC'
GNO'
A020
AE21
AF21
AC19
A019
AE20
AF20
AC18
GNO'
A018
AE19
AC17
A017
VCC'
AE18
AF18
AE17
AE16
GNO'
AF16
AC15
A015
AE15
AF15
A014
AE14
AF14
VCC'
GNO'
AE13
AC13
A013
AF12
AE12
A012
AC12
AF11
GNO'
AE11
A011
AF9
A010
VCC'
AE9
A09
AC10
AF7
GNO'
AE8
A08
AC9
AF6
AE7
389
390
391
394
397
400
403
406
409
412
415
418
421
424
427
430
433
436
439
442
445
448
451
454
457
460
463
466
469
472
475
478
481
484
487
490
493
496
499
502
505
508
511
514
517
520
523
526
529
532
535
538
541
544
547
1/0
1/0
1/0
GNO
VCC
1/0
1/0
110
110
1/0
110
1/0
110,
SGCK3 t.
GCK4:j:
GNO
DONE
VCC
PROGRAM
110 (07)
110,
PGCK3 t,
GCK5:j:
110
1/0
1/0
1/0
110
1/0
VCC
GNO
1/0(06)
1/0
1/0
1/0
1/0
1/0
110
110
GNO
1/0
1/0
1/0
110
VCC
1/0 (05)
1/0 (CSO)
110
1/0
GNO
110
110
1/0
1/0
110
110
1/0(04)
1/0
VCC
GNO
1/0(03)
1/0 (RS)
110
1/0
1/0
110
110
P71
P72
P92
P93
P94
R18
T18
P17
N16
T17
R17
P16
U18
T16
P110
P111
P112
P165
P164
P163
A07
AE6
AE5
GNO'
550
553
556
vcc'
P162
P161
P160
P159
P158
P157
P156
P155
A06
AC7
AF4
AF3
A05
AE3
A04
AC5
559
562
565
568
571
574
577
580
P73
P74
P75
P76
P77
P78
P95
P96
P97
P98
P99
P100
P79
P80
P81
P82
P101 GNO' P119 GNO' GNO' P154 GNO'
P103 U17 P120 Y20
V18 P153 A03
P106 VCC' P121 VCC' VCC' P152 VCC'
P108 V18 P122 V19
U17 P151 AC4
P83
P84
P109
P110
T15
U16
P123
P124
U19
U18
W19
W18
P150
P149
A02
AC3
583
586
P85
P86
P111
P112
T14
U15
R14
R13
P125
P126
P127
P128
T17
V20
U20
T18
P148
P147
P146
P145
P144
P143
P129
P130
P131
P132
P133
P134
AB4
A01
AA4
AA3
AB2
AC1
VCC'
GNO'
Y3
AA2
AA1
W4
W3
Y2
Y1
V4
GNO'
V3
W2
U4
U3
VCC'
V2
V1
U2
T2
GNO'
T1
R4
R3
R2
R1
P3
P2
P1
VCC'
GNO'
N2
N4
N3
M1
M2
M3
M4
589
592
595
598
601
604
VCC'
GNO'
T19
T20
R18
R19
R20
P18
T15
U16
V17
X18
U15
T14
VCC'
GNO'
W17
V16
X17
U14
V15
T13
W16
W15
GNO'
U13
V14
W14
V13
VCC'
T12
X14
U12
W13
GNO'
X13
V12
W12
T11
X12
U11
V11
W11
VCC'
GNO'
W10
V10
T10
U10
X9
W9
X8
V17
V16
T13
U14
V15
V14
P87
P88
P89
P90
P113
P114
P115
P116
P117
P118
P91
P119 GNO'
R12
R11
P120 U13
P121 V13
VCC'
P122 U12
P123 V12
P92
P93
P94
P95
P113
P114
P115
P116
P117
P118
V16
R18
W17
P16
Y18
V20
GNO' GNO'
VCC' vce'
R17
T18
U16
U19
V17
V19
W18
R16
Y19
T17
V18
U18
W19
X20
P135 GNO'
P136 P20
P137 N18
P138 N19
P139 N20
P140 VCC'
P141 M17
P142 M18
P143 GNO'
P96
P97
P98
P99
P100
P101
P102
P103
P104
P105
P124 T11 P144
P125 U11 P145
P126 V11 P146
P127 V10 P147
P128 U10 P148
P129 T10 P149
P130 VCC' P150
P131 GNO' P151
P132 T9
P152
P133 U9 P153
P134 V9
P154
P135 V8
P155
P136 U8 P156
P137 T8
P157
M19
M20
L19
L18
L20
K20
K19
VCC'
GNO'
K18
K17
J20
J19
J18
J17
H2O
P142
P141
P140
P139
P138
P137
P136
P135
P134
P133
P132
P131
P130
P129
P127
P126
P125
P124
P123
P122
P121
P120
P119
P118
P117
P116
P115
P114
P113
P112
P111
P110
P109
P108
P107
607
610
613
616
619
622
625
628
631
634
637
640
643
646
649
652
655
658
661
664
667
670
673
676
679
682
685
688
691
694
697
November 10, 1997 (Version 1.4)
~XILINX
XC4025E,
XC4028
EX/XL
Pad Name
110
GNO
110
110
110(02)
110
VCC
110
110
110
110
GNO
110
110
110
110
110
110
110
110
GNO
VCC
110 (01)
110 (RCLK,
ROYI
BUSY)
110
110
110
110
110 (~O,
DIN)
110,
SGCK4t,
GCK6*
(OOUT)
CCLK
VCC
0, TOO
GNO
110 (AO,
WS)
110,
PGCK4t,
GCK7*
(Al)
110
110
110 (CS1,
A2)
110 (A3)
110
110
VCC
GNO
110
110
110
110
110
110
110
110
GNO
110
110
110
110
VCC
HQ
HQ
160tt 208*
Pl06
P107
Pl08
Pl09
P110
P111
P112
P113
Pl14
PG
223t
HQ
240
BG
256tt
PG
299
V9
P158 GNO' GNO'
U9
T9
P138
V7 P159 H19
W8
P139
U7 P160 H18
X7
VCC' P161 VCC' VCC'
P140
V6 P162 G19
V8
P141
U6 P163 F20
W7
R8 P164 G18
U8
R7 P165 F19
W6
P142 GNO' P166 GNO' GNO'
T8
V7
R6 P167 F18
X4
R5 P168 E19
U7
P143
V5 P169 020
W5
P144
V4 P170 E18
V6
P145
T7
U5 P171
019
P146
T6 P172 C20
X3
GNO' GNO'
VCC' VCC'
P147
V3 P173 E17
U6
P148
V2 P174 018
V5
P115
Pl16
P117
P149
P150
P151
U4
T5
U3
P175
P176
P177
C19
B20
C1S
W4
W3
T6
U5
V4
Pl18
P152
T4
P178
B19
X1
HQ
304
P106
BG Bndry
352* Scan
700
PS6
P85
Ll
GNO'
L2
L3
Jl
K3
VCC'
J2
J3
K4
G1
GNO'
H2
H3
J4
F1
G2
G3
F2
E2
GNO'
VCC'
F3
G4
PS4
P83
PS2
P81
PSO
02
F4
E3
C2
03
757
760
763
766
769
P79
E4
772
Pl05
Pl04
Pl03
Pl02
Pl01
P99
P98
P97
P96
P95
P94
P93
P92
P91
P90
PS9
PS8
P87
703
706
709
712
715
718
721
724
727
730
733
736
739
742
745
748
XC4025E,
XC4028
EX/XL
Pad Name
110
110
110
110
GNO
IIO(M)
110 (A5)
110
110
110 (A21)t
110 (A20) *
110 (A6)
110 (A7)
GNO
6119197
HQ
HQ
160tt 208*
PG
223t
HQ
240
BG
256tt
PG
299
HQ
304
BG Bndry
352* Scan
P51
P50
P49
P48
A9
011
B11
A11
GNO'
012
C12
B12
A12
C13
B13
A13
B14
GNO'
A13
012
P134
P135
P174
P175
P176
P136 P177
P137 P178
P138 P179
P139 P180
P140 P181
P141 P182
M5
P1
M4
N2
GNO' GNO'
M2 P202 C12
Nl
M1
P203 B12
M3
L3 P205 A12
M2
L2 P206 B11
L5
L1
P207 Cl1
Ml
Kl
P208 A11
L4
K2 P209 Al0
L3
K3 P210 B10
L2
GNO' P211 GNO' GNO'
P47
P46
P45
P44
P43
P42
P41
P40
P39
62
65
68
71
74
77
80
83
86
89
92
95
, Pads labelled GND' or VCC' are internally bonded to Ground or
VCC planes within the associated package. They have no direct
connection to any specific package pin.
t
= E only
tt = XL only
:j: = EX, XL only
751
754
Additional XC4025E, XC4028EXlXL Package
Pins
HQ208
Pl
P3
P51
519197
I
I
I
P52
P53
P54
I
I
I
Not Connected Pins
Pl02
P107
P104
I P155
P105
I P156
I
I
I
I
P157
P158
P206
I
I
I
P207
P208
PG223
P119 Pi53
V1
P179 A20
V3
P120 P154 VCC' P180 VCC' VCC'
P121 P159
U2 P181
A19
U4
P122 P160 GNO' P182 GNO' GNO'
P123 P161
T3 P183 B18
W2
P78
C3
P77 VCC'
P76
04
P75 GNO'
P74
B3
0
P124
P73
5
P162
U1
P184
B17
V2
C4
vee Pins
03
J15
I
016
R10
010
R4
I
J4
R15
GND Pins
2
C12
G3
M3
R16
C7
015
K15
R9
04
G16
M16
09
K4
R3
T12
T7
519197
P125
P126
P127
P163
P164
P165
P3
R2
T2
P185
P186
P187
C17
016
A18
R5
T4
U3
P72
P71
P70
05
A3
06
8
11
14
P128
P166
N3
P188
A17
V1
R4
P5
VCC'
GNO'
U2
T3
U1
P4
R3
N5
T2
R2
GNO'
N4
P3
P2
N3
VCC'
P69
P68
P67
C6
B5
M
VCC'
GNO'
C7
B6
A6
08
B7
A7
09
C9
GNO'
B8
010
C10
B9
VCC'
17
20
23
HQ240
GND Pins
P129 P167
P130 P168
P169
P170
P131
P132
P133
P4
N4
P2
T1
R1
N2
P189
P190
P191
P192
P193
P194
P195
VCC'
GNO'
C16
B16
A16
C15
B15
A15
P171 GNO' P196 GNO'
P172
P1
P19? B14
P173
Nl
P198 A14
M4 P199 C13
L4 P200 B13
VCC' P201 VCC'
November 10, 1997 (Version 1.4)
P66
P65
P64
P63
P62
P61
P60
P59
P58
P57
P56
P55
P54
P52
26
29
32
35
38
41
44
47
P204
P219
519197
Note: These pins may be Not Connected for this device revision,
however for compatability with other devices in this package, these
pins should be tied to GND.
50
53
56
59
4-125
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
8G256
VCC Pins
C14
014
F4
K4
P19
U6
U15
06
015
F17
L17
R2
U7
V7
AI
013
H17
U4
W14
B7
017
N3
U8
07
E20
G4
011
Fl
G17
P17
R17
U14
P4
R4
Ul0
W20
Note: In XC4025 (no extension) devices in the HQ304 package,
PtOt is a No Connect (N.C.) pin. PtOt is Vcc in XC4025E and
XC4028EXlXL devices. Where necessary for compatibility, this pin
can be left unconnected.
GND Pins
G20
N4
U13
04
08
H4
N17
U17
All
E5
Rl
X5
A16
F20
T16
Xl0
A15
E20
R20
X2
A19
Fl
Tl
X6
8G352
5/9/97
PG299
VCC Pins
A2
B20
Kl
T20
X15
A6
El
L20
WI
X19
A5
Bl
Al0
E16
Ll
W20
X16
GND Pins
K20
T5
XII
6/18/97
Al0
019
P4
AC14
A17
G23
Ul
AC20
AI
A22
E26
W26
AF2
AF25
A2
A25
HI
ABI
AF5
AF26
A18
A24
C8
J26
T24
AC16
AE4
C5
F23
T4
ACll
AD26
5/9/97
VCC Pins
B25
B2
H4
Kl
W23
U26
AE25
AE2
GND Pins
A5
A8
Bl
A26
Nl
H26
AEI
AB26
AF8
AF13
07
K26
Y4
AF10
013
N23
AC8
AF17
A14
B26
P26
AE26
AF19
A19
El
WI
AFI
AF22
Not Connected Pins
Bl0
B4
Cll
01
K2
L4
U25
AB3
AC25
AC21
B23
016
L23
AC2
A016
Cl
025
T3
AC6
A021
AE10
Pin Locations for XC4036EX/XL
The following table may contain pinout information for unsupported device/package combinations. Please see the availability
charts elsewhere in the XC4000 Series data sheet for availability information.
XC4036EXlXL
Pad Name
VCC
1/0(A8)
I/O (A9)
I/O (AI9)
110 (AI8)
I/O
I/O
1/0 (Al0)
110 (All)
VCC
GNO
110
I/O
110
110
110
110
VCC
110
I/O
I/O
I/O
GNO
I/O
110
110
I/O
110
1/0
110 (AI2)
4-126
PQ
160ft
P142
P143
P144
P145
P146
HQ
208tt
P183
P184
P185
P186
P187
P188
P189
P147 P190
P148 P191
HQ
240
P212
P213
P214
P215
P216
P217
P218
P220
P221
HQ
304
P38
P37
P36
P35
P34
P33
P32
P31
P30
P29
P28
P149
P150
P151
P152
P153
P154
P192
P193
P194
P195
P196
P197
P198
P199
P222
P223
P224
P225
P226
P227
P228
P229
P230
P231
P232
P27
P26
P25
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
BG
352
VCC'
014
C14
A15
B15
C15
015
A16
B16
VCC'
GNO'
C16
B17
016
A18
C17
B18
VCC'
C18
017
A20
B19
GNO'
C19
018
A21
B20
C20
B21
822
PG
411
VCC'
W3
Y2
V4
T2
Ul
V6
U3
Rl
VCC'
GNO'
U5
T4
P2
Nl
R5
M2
VCC'
L3
T6
N5
M4
GNO'
K2
K4
P6
M6
J3
H2
H4
BG
432
VCC'
017
A17
C18
018
B18
A19
B19
C19
VCC'
GNO'
019
A20
B20
C20
C21
A22
VCC'
B22
C22
B23
A24
GNO'
022
C23
B24
C24
A26
C25
024
Bndry
Scan
110
113
116
119
122
125
128
131
134
137
140
143
146
149
152
155
158
161
164
167
170
173
176
179
182
XC4036EXlXL
Pad Name
1/0 (AI3)
GNO
VCC
I/O
110
1/0
I/O
110
1/0
110
1/0
1/0 (AI4)
I/O, GCK8 (AI5)
VCC
GNO
1/0, GCKI (A 16)
110 (AI7)
110
110
I/O,TOI
I/O, TCK
110
110
110
110
VCC
GNO
I/O
1/0
110
PQ
HQ
160tt 208tt
P155 P200
HQ
240
P233
HQ
304
Pl0
P9
P8
P156
P157
P158
P159
P160
PI
P2
P3
P4
P5
P6
P7
P201
P202
P203
P204
P205
P2
P4
P5
P6
P7
P8
P9
P234
P235
P236
P237
P238
P239
P240
PI
P2
P3
P4
P5
P6
P7
P7
P6
P5
P4
P3
P2
PI
P304
P303
P302
P301
P300
P299
P298
P297
P296
P8
P9
Pl0
Pll
P12
P8
P9
Pl0
P295
P294
P293
BG
352
C21
GNO'
VCC'
020
A23
A24
B23
021
C22
824
C23
022
C24
VCC'
GNO'
023
C25
024
E23
C26
E24
025
F23
F24
E25
VCC'
GNO'
026
G24
F25
PG
411
G3
GNO'
VCC'
K6
Gl
El
E3
J7
H6
C3
02
E5
G7
BG
432
826
GNO'
VCC'
A27
025
C26
827
C27
828
027
829
C28
028
Bndry
Scan
185
188
191
194
197
200
203
206
209
212
215
vce'
VCC'
GNO' GNO'
H8
029
F6
C30
84
E28
D4
E29
82
030
G9
D31
F8
E30
E31
C5
A7
G28
A5
G29
VCC' VCC'
GNO' GNO'
88
H28
C9
H29
E9
G30
2{a
221
224
227
230
233
236
239
242
245
248
251
254
November 10, 1997 (Version 1.4)
~:XILINX
XC4036EX/XL
Pad Name
1/0
1/0
PQ
HQ
160tt 208tt
P13
110
HQ
240
Pll
P12
P13
1/0
1/0
GNO
1/0
1/0
I/O,TMS
1/0
Pl0
Pll
P12
P13
P14
P14
P15
P16
P17
P18
VCC
110
1/0
P14
P15
P16
P17
P18
P19
P20
P21
HQ
304
P292
P291
P290
P289
P288
P287
P286
P285
P284
P283
P282
P280
P279
110
1/0
1/0
1/0
P278
P277
GNO
VCC
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
GNO
VCC
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
P22
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
VCC
GNO
P258
P257
VCC
110
1/0
GNO
P25
P26
P27
P28
P29
1/0
1/0
1/0
1/0
1/0
1/0
110
110
GNO
VCC
1/0
1/0
1/0
1/0
1/0
1/0
110
1/0
1/0
I/O,GCK2
o (Ml)
GNO
I (MO)
VCC
P276
P275
P274
P273
P272
P271
P270
P269
P268
P267
P266
P265
P264
P263
P262
P261
P260
P259
P37
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P30
P31
P33
P34
P35
P36
P37
P38
P39
P40
P41
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P256
P255
P253
P252
P251
P250
P249
P248
P247
P246
P245
P244
P243
P242
P241
P240
P32
P33
P42
P43
P52
P53
P239
P238
P237
P236
P34
P35
P36
P37
P38
P39
P40
P41
P44
P45
P46
P47
P4B
P49
P50
P55
P54
P55
P56
P57
P58
P59
P60
P61
P235
P234
P233
P232
P231
P230
P229
P228
November 10, 1997 (Version 1 A)
BG
352
F26
H23
H24
G25
G26
GNO'
J23
J24
H25
K23
VCC'
K24
J25
J26
L23
L24
K25
GNO'
VCC'
L25
L26
M23
M24
M25
M26
N24
N25
GNO'
VCC'
N26
P25
P23
P24
R26
R25
R24
R23
VCC'
GNO'
T26
T25
T24
U25
T23
V26
VCC'
U24
V25
V24
U23
GNO'
Y26
W25
W24
V2:i
AA26
Y25
Y24
AA25
GNO'
VCC'
AB25
AA24
Y23
AC26
A026
AC25
AA23
AB24
A025
AC24
AB23
GNO'
A024
VCC'
PG
411
F12
010
Bl0
FlO
F14
GNO'
Cll
B12
Ell
E15
VCC'
F16
C13
B14
E17
E13
A15
GNO'
VCC'
B16
016
018
A17
E19
B18
C17
C19
GNO'
VCC'
F20
B20
C21
B22
E21
022
A23
B24
VCC'
GNO'
A25
024
B26
A27
C27
F24
VCC'
E25
E27
B28
C29
GNO'
F26
028
B30
E29
F28
F30
C31
E31
GNO'
VCC'
B32
A33
A35
F32
C35
B38
E33
G31
H32
B36
A39
GNO'
E35
VCC'
BG
432
H30
J28
J29
H31
J30
GNO'
K28
K29
K30
K31
VCC'
L29
L30
M29
M31
N31
N28
GNO'
VCC'
P30
P28
P29
R31
R30
R28
R29
T31
GNO'
VCC'
T30
T29
U31
U30
U28
U29
V30
V29
VCC'
GNO'
W30
W29
Y30
Y29
Y28
AA30
VCC'
AA29
AB31
AB30
AB29
GNO'
AB28
AC30
AC29
AC28
A029
A028
AE30
AE29
GNO'
VCC'
AF31
AE28
AG31
AF28
AG30
AG29
AH31
AG28
AH30
AJ30
AH29
GNO'
AH28
VCC'
Bndry
Scan
257
260
263
266
269
272
275
278
281
284
287
290
293
296
299
XC4036EXlXL
Pad Name
I (M2)
1/0,GCK3
1/0 (HOC)
1/0
1/0
1/0
1/0 (LDC)
1/0
1/0
1/0
1/0
PQ
HQ
160tt 208tt
P42
P56
P43
P57
P44
P58
P45
P59
P46
P60
P47
P61
P48
P62
326
329
332
335
338
341
344
347
350
353
356
359
362
365
368
371
374
377
380
383
386
389
392
395
398
401
VCC
GNO
1/0
1/0
1/0
1/0
P49
P50
P63
P64
P65
P66
P69
P70
P71
P72
P73
P74
P5l
P52
P53
P54
P55
P67
P68
P69
P70
P7l
P75
P76
P77
P78
P79
P80
P8l
P82
1/0
1/0
1/0
GNO
1/0
1/0
1/0
1/0
VCC
1/0
1/0
1/0
1/0
1/0
P72
P73
1/0
1/0
1/0
1/0
1/0
1/0 (INIT)
VCC
GNO
1/0
1/0
1/0
1/0
P83
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
110
1/0
1/0
1/0
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P98
P181
P180
1/0
1/0
1/0
1/0
437
P84
PB5
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
VCC
1/0
1/0
1/0
GNO
P66
P67
P68
P69
P70
P86
P87
P88
P89
P90
1/0
1/0
1/0
110
1/0
1/0
1/0
1/0
P199
P198
P197
P196
P195
P194
P193
P192
P191
P190
P189
P188
P187
P186
P185
P184
P183
P182
-
VCC
GNO
110
110
P218
P217
P216
P215
P214
P213
P212
P211
P2l0
P209
P208
P207
P206
P204
P203
P202
P201
P200
110
GNO
VCC
110
110
110
404
407
410
413
416
419
422
425
428
431
434
HQ
304
P227
P226
P225
P224
P223
P222
P221
P220
P219
110
302
305
308
311
314
317
320
323
HQ
240
P62
P63
P64
P65
P66
P67
P68
P71
P72
P9l
P92
P93
P94
P99
Pl00
Pl0l
Pl02
Pl03
Pl04
Pl05
Pl06
Pl07
Pl08
Pl09
Pll0
Pl1l
Pl12
P179
P178
Pl77
P175
P174
P173
P172
P171
P170
P169
P168
P167
P166
P165
P164
P163
BG
352
AC23
AE24
A023
AC22
AF24
A022
AE23
AC21
A021
AE22
AF23
VCC'
GNO'
A020
AE21
AF21
AC19
A019
AE20
AF20
AC18
GNO'
A018
AE19
AC17
A017
VCC'
AE1B
AF18
AC16
A016
AE17
AE16
GNO'
VCC'
AF16
AC15
A015
AE15
AF15
A014
AE14
AF14
VCC'
GNO'
AE13
AC13
A013
AF12
AE12
A012
AC12
AFll
VCC'
GNO'
AEll
AOll
AE10
ACll
AF9
A010
VCC'
AE9
A09
AC10
AF7
GNO'
AE8
A08
AC9
AF6
AE7
A07
AE6
AE5
PG
411
G33
036
C37
F34
J33
038
G35
E39
K34
F38
G37
VCC'
GNO'
H38
J37
G39
M34
N35
P34
J35
L37
GNO'
M38
R35
H36
T34
VCC'
N37
N39
U35
R39
M36
V34
GNO'
VCC'
R37
T38
T36
V36
U37
U39
V38
W37
VCC'
GNO'
Y34
AC37
AB38
A036
AA35
AE37
AB36
A038
VCC'
GNO'
AB34
AE39
AM36
AC35
AG39
AG37
VCC'
A034
AN39
AE35
AH38
GNO'
AJ37
AG35
AF34
AH36
AK36
AM34
AH34
AJ35
BG
432
AJ28
AK29
AH27
AK28
AJ27
AL28
AH26
AL27
AH25
AK26
AL26
VCC'
GNO'
AH24
AJ25
AK25
AJ24
AL24
AH22
AJ23
AK23
GNO'
AJ22
AK22
AL22
AJ2l
VCC'
AH20
AK21
AK20
AJ19
AL20
AH18
GNO'
VCC'
AK19
AJ18
AL19
AK18
AH17
AJ17
AJ16
AK16
VCC'
GNO'
AL16
AH15
AK15
AJ14
AH14
AK14
AL13
AK13
VCC'
GNO'
AJ13
AH13
AL12
AK12
AH12
AJll
VCC'
AL10
AK10
AJ10
AK9
GNO'
AL8
AH10
AJ9
AK8
AK7
AL6
AJ7
AH8
Bndry
Scan
438
439
442
445
448
451
454
457
460
463
466
469
472
475
478
481
484
487
490
493
496
499
502
505
508
511
514
517
520
523
526
529
532
535
538
541
544
547
550
553
556
559
562
565
568
571
574
577
580
583
586
589
592
595
598
601
604
607
610
613
616
619
622
4-127
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4036EXlXL
Pad Name
GNO
VCC
I/O
1/0
1/0
1/0
1/0
I/O
I/O
1/0
1/0
1/0, GCK4
GNO
OONE
VCC
PROGRAM
1/0(07)
1/0, GCK5
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
VCC
GNO
1/0(06)
1/0
1/0
I/O
HO
PO
160tt 208tt
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
1/0
1/0
1/0
1/0
GNO
P91
P95
P96
P97
P98
P99
Pl00
Pl0l
Pl03
Pl06
Pl08
Pl09
Pll0
Plll
Pl12
Pl13
Pl14
Pl15
Pl16
Pl17
Pl18
Pl19
1/0
1/0
1/0
1/0
P92
P93
P120
P121
VCC
1/0(05)
1/0 (CSO)
P94
P95
P122
P123
HO
240
Pl13
Pl14
HO
304
P162
P161
P160
P159
Pl15
Pl16
Pl17
Pl18
Pl19
P120
P121
P122
P123
P124
P125
P126
P158
P157
P156
P155
P154
P153
P152
P151
P150
P149
P148
P147
P127
P128
P146
P145
P144
P143
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
P142
P141
P140
P139
P138
P137
P136
P135
P134
P133
P132
P131
P130
P129
P127
P126
1/0
I/O
I/O
P125
P124
1/0
GNO
VCC
1/0
1/0
1/0
1/0
1/0
I/O
1/0(04)
1/0
VCC
GNO
1/0(03)
1/0 (RS)
1/0
I/O
P143
P96
P97
P98
P99
Pl00
Pl0l
Pl02
Pl03
Pl04
Pl05
1/0
1/0
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
I/O
I/O
VCC
GNO
P144
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
P155
P156
P157
P158
1/0
1/0
1/0
1/0
I/O (02)
4-128
P123
P122
P121
P120
Pl19
Pl18
Pl17
Pl16
Pl15
Pl14
Pl13
Pl12
Plll
Pll0
Pl09
Pl08
Pl07
Pl06
Pl05
Pl04
Pl06
P138
P159
Pl03
BG
352
GNO'
VCC'
A06
AC7
AF4
AF3
AE4
AC6
A05
AE3
A04
AC5
GNO'
A03
VCC'
AC4
A02
AC3
AB4
AOl
AB3
AC2
AA4
AA3
AB2
ACl
VCC'
GNO'
Y3
AA2
AAl
W4
W3
Y2
Yl
V4
GNO'
V3
W2
U4
U3
VCC'
V2
Vl
T4
T3
U2
T2
GNO'
VCC'
T1
R4
R3
R2
Rl
P3
P2
Pl
VCC'
GNO'
N2
N4
N3
Ml
M2
M3
M4
Ll
VCC'
GNO'
L2
L3
K2
L4
Jl
PG
411
GNO'
VCC'
AL37
AT38
AM38
AN37
AK34
AR39
AN35
AL33
AV38
AT36
GNO'
AR35
VCC'
AN33
AM32
AP34
AW39
AN31
AV36
AR33
AP32
AU35
AW33
AU33
VCC'
GNO'
AV32
AU31
AR31
AP28
AT32
AV30
AR29
AP26
GNO'
AU29
AV28
AT28
AR25
VCC'
AP24
AU27
AR27
AW27
AT24
AR23
GNO'
VCC'
AP22
AV24
AU23
AT22
AR21
AV22
AP20
AU21
VCC'
GNO'
AU19
AV20
AV18
AR19
AT18
AW17
AV16
AP18
VCC'
GNO'
AR17
AT16
AV14
AW13
AR15
BG
432
GNO'
VCC'
AK6
AL5
AH7
AJ6
AK5
AL4
AK4
AH5
AK3
AJ4
GNO'
AH4
VCC'
AH3
AJ2
AG4
AG3
AH2
AHl
AF4
AF3
AG2
AE3
AF2
VCC'
GNO'
AFl
A04
A03
AE2
AC3
AOl
AC2
AB4
GNO'
AB3
AB2
ASl
AA3
VCC'
AA2
Y2
Y4
Y3
W4
W3
GNO'
VCC'
V4
V3
Ul
U2
U4
U3
Tl
T2
VCC'
GNO'
T3
Rl
R2
R4
R3
P2
P3
P4
VCC'
GNO'
N3
N4
Ml
M2
L2
Bndry
Scan
XC4036EXlXL
Pad Name
1/0
PO
HO
160tt 208tt
Pl07 P139
Plll
Pl12
P143
P144
P145
P146
P167
P168
P169
P170
P171
P172
HO
304
Pl02
Pl0l
P99
P98
P97
P96
P95
P94
P93
P92
P91
P90
P89
P88
P87
Pl13
Pl14
P147
P148
P173
P174
P86
P85
BG
352
K3
VCC'
J2
J3
K4
Gl
GNO'
H2
H3
J4
Fl
G2
G3
F2
E2
GNO'
VCC'
F3
G4
01
Cl
02
F4
E3
C2
03
E4
AW5
AV6
AR7
AV4
AN9
AWl
AP6
AU3
F3
El
E3
01
E4
02
C2
03
C3
VCC'
04
GNO'
B3
C4
05
A3
C5
B4
06
C6
B5
AR5
VCC'
AN7
GNO'
AT4
AV2
AM8
AL7
AR3
ARl
AK6
AN3
AM6
AM2
VCC'
GNO'
AL3
AH6
AP2
AK4
AG5
AF6
AL5
AJ3
GNO'
AH2
AE5
AM4
A06
VCC'
AG3
AGl
AC5
AEl
AH4
AB6
GNO'
VCC'
A02
AB4
AE3
ACl
A04
AA5
AA3
Y6
04
VCC'
C4
GNO'
B3
05
B4
C5
B5
C6
A5
07
B6
A6
VCC'
GNO'
08
C7
B7
09
010
C9
B9
Cl0
GNO'
Bl0
Al0
Cll
012
VCC'
Bll
C12
C13
A12
014
B13
GNO'
VCC
625
628
631
634
637
640
643
646
649
652
1/0
1/0
1/0
1/0
Pl08
Pl09
P140
P141
GNO
Pll0
P142
1/0
1/0
I/O
I/O
I/O
1/0
1/0
1/0
655
658
661
664
667
670
673
676
679
682
685
688
691
694
697
700
703
706
709
712
715
718
721
724
727
730
733
736
GNO
VCC
1/0(01)
1/0 (RCLK, ROYI
BUSY)
1/0
1/0
1/0
1/0
1/0
1/0
1/0 (00, OIN)
1/0, GCK6
(OOUT)
CCLK
VCC
O,TOO
GNO
1/0 (AO, WS)
1/0, GCK7 (Al)
1/0
1/0
1/0
1/0
1/0 (CS1, A2)
1/0 (A3)
1/0
1/0
Pl15
Pl16
Pl17
Pl18
P149
P150
P151
P152
P175
P176
Pl77
P178
P84
P83
P82
P81
P80
P79
Pl19
P120
P121
P122
P123
P124
P125
P126
P153
P154
P159
P160
P161
P162
P163
P164
P179
P180
P181
P182
P183
P184
P185
P186
P78
P77
P76
P75
P74
P73
P72
P71
P127
P128
P165
P166
P187
P188
P70
P69
P68
P67
VCC
GNO
1/0
1/0
1/0
1/0
I/O
P66
P65
P64
P63
P62
P61
P60
P59
P58
P57
P56
P55
P54
P52
P51
P50
1/0
1/0
1/0
1/0
P49
P48
P129
P130
P167
P168
P169
P170
P131
P132
P133
P171
P172
P173
I/O
739
742
745
748
751
754
757
760
HO
240
P160
P161
P162
P163
P164
P165
P166
1/0
1/0
1/0
GNO
1/0
1/0
1/0
1/0
VCC
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
P199
P200
P201
~763
766
769
772
775
778
781
784
GNO
VCC
110 (A4)
1/0 (A5)
P134
P135
1/0
787
110
790
1/0
1/0
1/0
1/0
793
796
799
(A21)
(A20)
(A6)
(A7)
P136
P137
P138
P139
P140
P174
P175
P176
Pl77
P178
P179
P180
P181
P202
P203
P205
P206
P207
P208
P209
P210
P47
P46
P45
P44
P43
P42
P41
P40
A4
VCC'
GNO'
C7
B6
A6
08
B7
A7
09
C9
GNO'
B8
010
Cl0
B9
VCC'
A9
011
Cll
Bl0
Bll
All
GNO'
VCC'
012
C12
B12
A12
C13
B13
A13
B14
PG
411
AP16
VCC'
AV12
AR13
AUll
AT12
GNO'
AP14
ARll
AV10
AT8
AT10
AP10
AP12
AR9
GNO'
VCC'
AU7
AW7
BG
432
L3
VCC'
Kl
K2
K3
K4
GNO'
J2
J3
J4
Hl
H2
H3
H4
G2
GNO'
VCC'
G4
F2
Bndry
Scan
802
847
850
853
856
859
862
865
868
805
808
811
814
817
820
823
826
829
832
835
838
841
844
0
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
65
68
71
74
77
80
83
vcc'
C14
A13
B14
015
C15
B15
B16
A16
86
89
92
95
98
101
104
107
November 10, 1997 (Version 1.4)
__
~~
_____________
___, _ _
~~_'
__
~,_-,~
~~~_~~_
_c~
____-_-_ _
-
~"
~
__
~~
~XILINX
PG411
6/17/97
, Pads labelled GND' or vee' are internally bonded to Ground or vee
planes within the associated package. They have no direct connection to
any specific package pin.
tt = XL only
Additional XC4036EX/XL Package Pins
A3
F36
AL39
AW29
All
Jl
AP4
AW37
A9
020
P4
AF4
AT14
AW21
A19
026
P36
AF36
AT20
AW31
A13
C25
E7
G5
L35
W35
AF2
ANl
AT2
AU17
AW15
86
C33
E23
H34
N3
Y38
AF38
AN5
AT30
AU25
AW23
HQ208
Pl
P54
P155
P207
P3
Pl02
P156
P208
Not Connected Pins
P51
Pl04
P157
P52
Pl05
P158
P53
Pl07
P206
5/15/97
HQ240
I
GND Pins
P219
P204
The Ground (GNO) package pins in the above table should be
externally connected to Ground if possible; however, they can be
left unconnected if necessary for compatibility with other devices.
Al
A22
E26
W26
AF2
AF25
A2
A25
Hl
ABl
AF5
AF26
06
AJl
AW19
GND Pins
A29
A37
F4
034
W39
Y4
AJ39
ALl
AT26
AU39
Cl
J39
Y36
AP36
AW3
014
Ll
AAl
AT6
AWll
C15
030
F18
K38
V2
AC3
AK38
AP38
AU13
AV26
C23
032
F22
L5
W5
AC39
AL35
AR37
AU15
AV34
Not Connected Pins
B34
C7
012
08
F2
E37
J5
K36
P38
R3
AA37
AB2
AK2
AJ5
AP8
AP30
AU5
AU9
AU37
AV8
AW35
AW25
BG432
BG352
A17
G23
Ul
AC20
C39
AA39
AW9
6/16/97
6/17/97
Al0
019
P4
AC14
VCC Pins
A21
A31
L39
Wl
AUl
AT34
vcc Pins
B2
825
Kl
H4
U26
W23
AE2
AE25
GND Pins
A5
A8
Bl
A26
H26
Nl
AB26
AEl
AF8
AF13
07
K26
Y4
AF10
013
N23
AC8
AF17
A14
B26
P26
AE26
AF19
A19
El
Wl
AFl
AF22
Al
011
AAl
AJ3
All
021
AA4
AJ29
A2
A23
B30
G31
T28
AE31
AK30
ALl4
A3
A25
831
Jl
Vl
AH16
AK31
AL18
A4
A8
821
013
F4
M3
N29
W28
A030
AH6
AJ12
AK24
B17
06
Fl
G3
N2
W2
AD2
AGl
AJ8
AK17
Not Connected Pins
C8
VCC Pins
A21
A31
Ll
L4
AA31
AA28
AL1
ALll
GND Pins
A7
A9
A30
A29
Cl
C31
J31
Pl
ACl
V31
AJl
AJ31
AL2
AL3
AL25
AL23
Not Connected Pins
A15
A28
B25
C8
020
023
F28
F29
M4
M28
V2
N30
W31
Yl
AE4
A031
AH9
AH19
AJ20
AJ15
AK27
AL15
I
I
C3
L28
AH11
AL21
I
I
C29
L31
AH21
AL31
A14
Bl
016
P31
AC31
AKl
AL7
AL29
A18
82
Gl
T4
AEl
AK2
AL9
AL30
88
C16
D26
F30
M30
V28
Y31
AF29
AH23
AJ26
AL17
812
C17
E2
F31
Nl
Wl
AC4
AF30
AJ5
AKll
5/15/97
6/16/97
Pin Locations for XC4044XL Devices
(Note: XC4044XL is also available in the HQ304 package.
The pinout is identical to the XC4036XL in the HQ304. )
HQ
HQ
HQ
VCC
1/0 (A8)
1/0 (A9)
160
P142
P143
P144
208
P183
P184
P185
240
P212
P213
P214
1/0
1/0
1/0 (A19)
P145
P186
P215.L~
XC4044XL
Pad Name
November 10, 1997 (Version 1.4)
BG
352
VCC'
014
C14
PG
411
VCC'
W3
Y2
V2
W5
V4
BG
432
VCC'
017
A17
C17
817
C18
XC4044XL
Pad Name
110 (A18)
HQ
HQ
HQ
160
P146
208
P187
P188
P189
P190
P191
240
P216
P217
P218
P220
P221
1/0
1/0
110 (Al0)
110 (All)
VCC
GNO
110
1/0
P147
P148
BG
352
815
C15
015
A16
816
VCC'
GNO'
C16
B17
PG
411
T2
Ul
V6
U3
Rl
VCC'
GNO'
U5
T4
BG
432
018
818
A19
819
C19
VCC'
GNO'
019
A20
4-129
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4044XL
Pad Name
HQ
HQ
HQ
160
208
240
1/0
1/0
1/0
1/0
VCC
110
1/0
1/0
1/0
GND
110
1/0
1/0
1/0
110
1/0
1/0
1/0
1/0 (A12)
1/0 (A13)
P149
P150
P151
P152
P153
P154
P155
P192
P193
P194
P222
P223
P224
P225
P226
P227
P195
P196
P228
P229
P197
P198
P199
P200
P230
p231
P232
P233
GND
VCC
110
1/0
1/0
1/0
110
1/0
1/0
1/0
110 (A14)
110, GCK8 (A15)
VCC
GND
1/0, GCKl (A16)
110 (A17)
1/0
1/0
1/0, TDI
1/0, TCK
1/0
110
1/0
1/0
P156
P157
P158
P159
P160
Pl
P2
P3
P4
P5
P6
P7
P201
P202
P203
P204
P205
P2
P4
P5
P6
P7
P8
P9
P234
P235
P236
P237
P238
P239
P240
Pl
P2
P3
P4
P5
P6
P7
VCC
GNO
110
1/0
1/0
1/0
1/0
1/0
1/0
110
1/0
1/0
GNO
1/0
110
1/0, TMS
1/0
P8
P9
Pl0
Pll
P12
P13
P14
Pl0
Pll
P12
P13
P14
P15
P16
P17
P18
VCC
110
110
110
110
110
1/0
GNO
VCC
1/0
1/0
110
110
1/0
4-130
P8
P9
Pl0
Pll
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P19
P23
BG
352
D16
A18
C17
B18
VCC'
C18
D17
A20
819
GND'
C19
D18
A21
B20
C20
821
822
C21
GND'
VCC'
D20
A23
A24
B23
D21
C22
B24
C23
D22
C24
VCC'
GND'
D23
C25
D24
E23
C26
E24
D25
F23
F24
E25
VCC'
GND'
D26
G24
F25
F26
H23
H24
G25
G26
GND'
J23
J24
H25
K23
VCC'
K24
J25
J26
L23
L24
K25
GNO'
VCC'
L25
L26
M23
PG
411
P2
Nl
R5
M2
VCC'
L3
T6
N5
M4
GND'
K2
K4
P6
M6
L5
J5
J3
H2
H4
G3
GND'
VCC'
K6
Gl
El
E3
J7
H6
C3
D2
E5
G7
VCC'
GND'
H8
F6
B4
D4
B2
G9
F8
C5
A7
A5
VCC'
GNO'
C7
D8
B8
C9
E9
F12
Dl0
B10
FlO
F14
GND'
Cll
812
Ell
E15
VCC'
F16
C13
B14
E17
E13
A15
GND'
VCC'
F18
C15
B16
016
D18
BG
432
B20
C20
C21
A22
VCC'
B22
C22
B23
A24
GND'
D22
C23
824
C24
D23
825
A26
C25
D24
B26
GND'
VCC'
A27
D25
C26
B27
C27
B28
D27
829
C28
D28
VCC'
GND'
D29
C30
E28
E29
D30
D31
E30
E31
G28
G29
VCC'
GNO'
F30
F31
H28
H29
G30
H30
J28
J29
H31
J30
GND'
K28
K29
K30
K31
VCC'
L29
L30
M29
M31
N31
N28
GNO'
VCC'
N29
N30
P30
P28
P29
XC4044XL
Pad Name
1/0
1/0
1/0
1/0
1/0
GND
VCC
1/0
1/0
1/0
1/0
1/0
1/0
110
110
1/0
1/0
HQ
160
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
HQ
240
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
VCC
GND
P37
110
1/0
1/0
110
1/0
1/0
VCC
1/0
110
1/0
1/0
GND
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
HQ
208
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P25
P26
P27
P28
P29
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P30
P31
P38
P39
P40
P41
P48
P49
P50
P51
P32
P33
P42
P43
P52
P53
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P44
P45
P46
P47
P48
P49
P50
P55
P56
P57
P58
P59
P60
P61
P62
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P49
P50
P63
P64
P65
P66
P69
P70
P71
P72
GND
VCC
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
110
fjjQ,GcK-2--O(Ml)
GND
I (MO)
VCC
I (M2)
1/0, GCK3
1/0 (HDC)
110
110
1/0
1/0 (LDC)
110
1/0
1/0
1/0
VCC
GND
1/0
1/0
110
110
1/0
BG
352
M24
M25
M26
N24
N25
GNO'
VCC'
N26
P25
P23
P24
R26
R25
R24
R23
VCC'
GND'
T26
T25
T24
U25
T23
V26
VCC'
U24
V25
V24
U23
GND'
Y26
W25
W24
V23
AA26
Y25
Y24
AA25
GNO'
VCC'
AB25
AA24
Y23
AC26
AD26
AC25
AA23
AB24
AD25
AC24
A823
GND'
AD24
VCC'
AC23
AE24
AD23
AC22
AF24
AD22
AE23
AC21
AD21
AE22
AF23
VCC'
GND'
AD20
AE21
AF21
AC19
PG
411
A17
E19
818
C17
C19
GND'
VCC'
F20
B20
C21
822
E21
022
A23
824
C23
F22
VCC'
GND'
A25
024
826
A27
C27
F24
VCC'
E25
E27
B28
C29
GND'
F26
D28
B30
E29
030
D32
F28
F30
C31
E31
GNO'
VCC'
832
A33
A35
F32
C35
838
E33
G31
H32
836
A39
GND'
E35
VCC'
G33
036
C37
F34
J33
D38
G35
E39
K34
F38
G37
VCC'
GND'
H38
J37
G39
M34
K36
BG
432
R31
R30
R28
R29
T31
GNO'
VCC'
T30
T29
U31
U30
U28
U29
V30
V29
V28
W31
VCC'
GND'
W30
W29
Y30
Y29
Y28
AA30
VCC'
AA29
A831
A830
A829
GND'
A828
AC30
AC29
AC28
A031
AD30
AD29
A028
AE30
AE29
GND'
VCC'
AF31
AE28
AG31
AF28
AG30
AG29
AH31
AG28
AH30
AJ30
AH29
GND'
AH28
VCC'
AJ28
AK29
AH27
AK28
AJ27
AL28
AH26
AL27
AH25
AK26
AL26
VCC'
GND'
AH24
AJ25
AK25
AJ24
AH23
November 10, 1997 (Version 1.4)
~XILINX
XC4044XL
Pad Name
HQ
HQ
HQ
160
208
240
BG
352
1/0
110
P73
P74
1/0
1/0
1/0
GNO
P51
P52
P53
P54
P55
1/0
1/0
1/0
1/0
P67
P68
P69
P70
P71
VCC
1/0
1/0
1/0
1/0
1/0
1/0
P72
P73
GNO
VCC
P75
P76
P77
P78
P79
P80
P81
P82
P83
1/0
~-
..
1/0
1/0
110
1/0
1/0
1/0
1/0
110 (INIT)
VCC
GNO
110
1/0
1/0
1/0
1/0
1/0
1/0
1/0
P56
P57
P74
P75
P84
P85
P86
P87
P58
P59
P60
P61
P62
P63
P76
P77
P78
P79
P80
P81
P88
P89
P90
P91
P92
P93
AE14
AF14
VCC'
GNO'
AE13
AC13
P64
P65
P82
P83
P84
pa5
P94
P95
P96
P97
A013
AF12
AE12
A012
AC12
AF11
VCC'
GNO'
AE11
AOll
AE10
AC11
AF9
A010
VCC'
AE9
A09
AC10
AF7
GNO'
AE8
A08
AC9
AF6
110
1/0
VCC
GNO
P98
1/0
110
1/0
1/0
110
1/0
VCC
1/0
1/0
1/0
1/0
GNO
A019
AE20
AF20
AC18
GNO'
A018
AE19
AC17
A017
VCC'
AE18
AF18
AC16
A016
AE17
AE16
GNO'
VCC'
AF16
AC15
A015
AE15
AF15
A014
P66
P67
P68
P69
P70
P86
P87
P88
PS9
P90
P99
Pl00
Pl0l
Pl02
Pl03
Pl04
Pl05
Pl06
1/0
110
1/0
Pl07
Pl08
110
1/0
110
1/0
1/0
1/0
1/0
P71
P72
GNO
VCC
P91
P92
P93
P94
Pl09
PlIO
PIlI
P112
--
1/0
1/0
1/0
1/0
1/0
1/0
P73
P74
110
110
P75
P76
P95
P9G
P97
P98
November 10, 1997 (Version 1.4)
P113
P114
P115
P116
AE7
A07
AE6
AE5
GNO'
VCC'
A06
AC7
AF4
AF3
AE4
AC6
A05
AE3
PG
411
K38
N35
P34
J35
L37
GNO'
M38
R35
H36
T34
VCC'
N37
N39
U35
R39
M36
V34
GNO'
VCC'
R37
T38
T36
V36
U37
U39
W35
AC39
V38
W37
VCC'
GNO'
Y34
AC37
Y38
AA37
AB38
A036
AA35
AE37
AB36
A038
VCC'
GNO'
AB34
AE39
AM36
AC35
AG39
AG37
VCC'
A034
AN39
AE35
AH38
GNO'
AJ37
AG35
AF34
AH36
AK38
AP38
AK36
AM34
AH34
AJ35
GNO'
VCC'
AL37
AT38
AM38
AN37
AK34
AR39
AN35
AL33
BG
432
AK24
AL24
AH22
AJ23
AK23
GNO'
AJ22
AK22
AL22
AJ21
VCC'
AH20
AK21
AK20
AJ19
AL20
AH18
GNO'
VCC'
AK19
AJ18
AL19
AK18
AH17
AJ17
AK17
AL17
AJ16
AK16
VCC'
GNO'
AL16
AH15
AL15
AJ15
AK15
AJ14
AH14
AK14
AL13
AK13
VCC'
GNO'
AJ13
AH13
AL12
AK12
AH12
AJll
VCC'
AL10
AK10
AJ10
AK9
GNO'
AL8
AH10
AJ9
AK8
AJ8
AH9
AK7
AL6
AJ7
AH8
GNO'
VCC'
AK6
AL5
AH7
AJ6
AK5
AL4
AK4
AH5
XC4044XL
Pad Name
1/0
1/0, GCK4
GNO
OONE
VCC
PROGRAM
110 (07)
1/0, GCK5
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
VCC
GNO
1/0(06)
1/0
I/O
1/0
1/0
1/0
1/0
1/0
1/0
1/0
HQ
HQ
HQ
160
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
208
P99
Pl00
Pl0l
Pl03
Pl06
Pl08
Pl09
PlIO
PIlI
P112
240
P117
P118
P119
P120
P121
+~~22
P123
P124
P125
P126
P127
P128
P87
P88
P89
P90
P113
P114
P115
P116
P129
P130
P131
P132
P117
P118
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
GNO
P91
P119
1/0
1/0
1/0
1/0
P92
P93
P120
P121
VCC
1/0(05)
1/0 (CSO)
P94
P95
P122
P123
1/0
1/0
1/0
1/0
GNO
VCC
P143
1/0
1/0
1/0
1/0
110
1/0
1/0
1/0
1/0(04)
1/0
VCC
GNO
1/0(03)
I/O(RS)
1/0
1/0
1/0
P96
P97
P98
P99
Pl00
Pl01
Pl02
Pl03
Pl04
Pl0S
110
P124
P125
P126
P127
P128
P129
P13G
P131
P132
P133
P134
P135
P136
P137
P144
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
P155
P156
P157
1/0
110
BG
352
A04
AC5
GNO'
A03
VCC'
AC4
A02
AC3
AB4
AOI
AB3
AC2
AA4
AA3
AB2
ACI
VCC'
GNO'
Y3
AA2
AAI
W4
W3
Y2
Yl
V4
GNO'
V3
W2
U4
U3
VCC'
V2
VI
T4
T3
U2
T2
GNO'
VCC'
Tl
R4
R3
R2
Rl
P3
P2
PI
VCC'
GNO'
N2
N4
N3
Ml
M2
M3
M4
Ll
1/0
I/O
VCC
GNO
P158
1/0
1/0
1/0
1/0
1/0(02)
1/0
VCC
I/O
1/0
Pl06
Pl07
P138
P13S
Pl08
Pl0S
P140
P141
P159
P160
P161
P162
P163
VCC'
GNO'
L2
L3
K2
L4
Jl
K3
VCC'
J2
J3
PG
411
AV38
AT36
GNO'
AR35
VCC'
AN33
AM32
AP34
AW39
AN31
AV36
AR33
AP32
AU35
AW33
AU33
VCC'
GNO'
AV32
AU31
AR31
AP28
AP30
AT30
AT32
AV30
AR29
AP26
GNO'
AU2(}
AV28
AT28
AR25
VCC'
AP24
AU27
AR27
AW27
AT24
AR23
GNO'
VCC'
AW25
AW23
AP22
AV24
AU23
AT22
AR21
AV22
AP20
AU21
VCC'
GNO'
AU19
AV20
AV18
AR19
AT18
AW17
AV16
AP18
AU17
AWlS
VCC'
GNO'
AR17
AT16
AV14
AW13
AR15
AP16
VCC'
AV12
AR13
BG
432
AK3
AJ4
GNO'
AH4
VCC'
AH3
AJ2
AG4
AG3
AH2
AHI
AF4
AF3
AG2
AE3
AF2
VCC'
GNO'
AFI
A04
A03
AE2
A02
AC4
AC3
AOI
AC2
AB4
GNO'
AB3
AB2
ABI
AA3
VCC'
AA2
Y2
Y4
Y3
W4
W3
GNO'
VCC'
W2
V2
V4
V3
Ul
U2
U4
U3
T1
T2
VCC'
GNO'
T3
Rl
R2
R4
R3
P2
P3
P4
Nl
N2
VCC'
GNO'
N3
N4
Ml
M2
L2
L3
VCC'
Kl
K2
4-131
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4044XL
Pad Name
HQ
160
HQ
208
Pll0
P142
HQ
240
P164
P165
P166
Plll
Pl12
P143
P144
P145
P146
P167
P168
P169
PHO
P171
P172
110
110
GNO
110
110
110
110
110
110
110
110
110
110
GNO
VCC
110 (Dl)
110 (RCLK, RDY/BUSY)
Pl13
Pl14
P147
P148
P173
P174
110
110
110
110
1/0
110
110 (DO, DIN)
110, GCK6 (DOUT)
CCLK
VCC
O,TOO
GND
110 (AO,WS)
110, GCK7 (Al)
110
110
110
110
110 (CSl ,A2)
110 (A3)
110
110
Pl15
Pl16
Pl17
Pl18
Pl19
P120
P121
P122
P123
P124
P125
P126
P149
P150
P151
P152
P153
P154
P159
P160
P161
P162
P163
P164
P175
P176
P177
P178
P179
P180
P181
P182
P183
P184
P185
P186
P127
P128
P165
P166
P187
P188
P167
P168
P189
P190
P191
P192
VCC
GND
110
110
110
110
110
110
110
110
110
110
GND
110
110
P129
P130
P193
P194
P195
P171
P172
P173
P196
P197
P198
P199
P200
P201
P136
P137
P138
P174
P175
PH6
Pl77
P178
P179
P202
P203
P205
P206
P207
P208
P139
P14D
P18D
P181
P209
P21D
A13
B14
110
110
VCC
110
110
110
1/0
110
110
GND
VCC
110 (A4)
110 (AS)
110
110
110 (A21)
110 (A20)
110
110
110 (A6)
110 (A7)
4-132
GNO'
VCC'
F3
G4
Dl
Cl
D2
F4
E3
C2
D3
E4
C3
VCC'
D4
GND'
B3
C4
D5
A3
C5
B4
D6
C6
B5
A4
VCC'
GND'
C7
B6
A6
08
C8
B7
A7
D9
C9
GND'
B8
Dl0
Cl0
B9
VCC'
A9
Dll
Cll
Bl0
Bll
All
GND'
VCC'
D12
C12
B12
A12
C13
B13
P131
P132
P133
P169
P170
BG
352
K4
Gl
GNO'
H2
H3
J4
Fl
G2
G3
F2
E2
P134
P135
PG
411
AU11
AT12
GNO'
AP14
ARll
AVlO
AT8
AT10
AP10
AP12
AR9
AU9
AV8
GND'
VCC'
AU7
AW7
AW5
AV6
AR7
AV4
AN9
AWl
AP6
AU3
AR5
VCC'
AN7
GND'
AT4
AV2
AM8
AL7
AR3
ARl
AK6
AN3
AM6
AM2
VCC'
GND'
AL3
AH6
AP2
AK4
ANl
AK2
AG5
AF6
AL5
AJ3
GND'
AH2
AE5
AM4
AD6
VCC'
AG3
AGl
AC5
AEl
AH4
AB6
GND'
VCC'
A02
AB4
AE3
ACl
A04
AA5
AB2
AC3
AA3
Y6
BG
432
K3
K4
GNO'
J2
J3
J4
Hl
H2
H3
H4
G2
G3
Fl
GND'
VCC'
G4
F2
F3
El
E3
Dl
E4
D2
C2
D3
D4
VCC'
C4
GND'
B3
D5
B4
C5
B5
C6
A5
D7
B6
A6
VCC'
GND'
D8
C7
B7
D9
B8
A8
Dl0
C9
B9
Cl0
GND'
Bl0
Al0
Cll
D12
VCC'
Bll
C12
C13
A12
D14
B13
GND'
VCC'
C14
A13
B14
D15
C15
B15
A15
C16
B16
A16
XC4044XL
Pad Name
GND
6/181197
• Pads labelled GND* or VCC* are internally bonded to Ground or
VCC planes within the associated package, They have no direct
connection to any specific package pin,
Additional XC4044XL Package Pins
HQ208
Pl
Pl04
P206
I
I
I
P3
P1D5
P2D7
J
P219
I
Not Connected Pins
P51
I P52 I P53
P156
Pl07 J P155
P2D8
I
P54
P157
I
I
P1D2
P158
I
5/29197
HQ240
I
P2D4
GND Pins
I
5/29/97
I
Note: These pins may be Not Connected for this device revision,
however for compatability with other devices in this package, these
pins should be tied to GND.
BG352
A1D
G23
U26
AE25
A17
H4
W23
AF10
B2
Kl
Y4
AF17
Al
A25
H26
AEl
AF19
A2
A26
Nl
AE26
AF22
A5
Bl
P26
AFl
AF25
VCC Pins
B25
K26
AC8
GND Pins
A8
B26
Wl
AF2
AF26
D7
N23
AC14
D13
P4
AC20
D19
Ul
AE2
A14
El
W26
AF5
A19
E26
ABl
AF8
A22
Hl
AB26
AF13
D6
AL39
AW37
F36
AP4
D14
P4
AF36
A 26
D20
P36
AJ39
AU39
D12
L35
AL35
AU15
E7
N3
AN5
AU25
6/13/97
PG411
A3
Jl
AT34
All
L39
AUl
A9
D26
W39
ALl
AW3
A19
D34
Y4
AP36
AWll
A13
E23
P38
AP8
AU37
B6
E37
R3
AR37
AV26
VCC Pins
A31
C39
AJl
AA39
AW19
AW29
GND Pins
Cl
A29
A37
F4
Ll
J39
Y36
AAl
AF4
AT20
AT6
AT14
AW21
AW31
Not Connected Pins
B34
C25
C33
F2
H34
G5
AF2
AF38
AJ5
AU5
AU13
AT2
AV34
AW35
A21
Wl
AW9
6/2/97
November 1D, 1997 (Version 1.4)
~XILINX
BG432
vee Pins
A1
021
AA28
AL11
A11
L1
AA31
AL21
A21
L4
AH11
AL31
A2
A25
C1
P1
AC31
AK2
AL14
A3
A29
C31
P31
AE1
AK30
AL18
A7
A30
016
T4
AE31
AK31
AL23
A4
D20
M4
AE4
AJ12
A28
D26
M28
AF29
AJ20
812
E2
M30
AF30
AJ26
A31
L28
AH21
C3
L31
AJ3
C29
AA1
AJ29
D11
AA4
AL1
GND Pins
A9
81
G1
T28
AH16
AL2
AL25
A14
82
G31
V1
AJ1
AL3
AL29
A18
830
J1
V31
AJ31
AL7
AL30
A23
831
J31
AC1
AK1
AL9
D6
F29
Y1
AH19
D13
M3
Y31
AJ5
-
Not Connected Pins
821
F4
W1
AG1
AK11
C8
F28
W28
AH6
AK27
5/29/97
Pin Locations for XC4052XL Devices
(Note: XC4052XL is also available in the HQ304 package.
The pinout is identical to the XC4036XL in HQ304.)
XC4052XL
Pad Name
HQ
240
GNO
VCC
1/0
XC4052XL
Pad Name
VCC
1/0 (A8)
1/0 (A9)
1/0
1/0
GNO
1/0 (A19)
110 (A18)
1/0
1/0
1/0 (Al0)
1/0 (All)
HQ
240
P212
P213
P214
P215
P216
P217
P218
P220
P221
VCC
GNO
1/0
1/0
110
1/0
1/0
1/0
GNO
1/0
1/0
vec
1/0
1/0
1/0
1/0
GNO
1/0
1/0
1/0
1/0
P222
P223
P224
P225
P226
P2:<7
P228
P229
GNO
1/0
1/0
I/O
1/0
1I0.(A12)
110 (A13)
P230
P231
P232
P233
November 10,1997 (Version 1.4)
PG
411
VCC'
W3
Y2
V2
W5
GNO'
V4
T2
Ul
V6
U3
Rl
VCC'
GNO'
U5
T4
P2
Nl
R3
N3
GNO'
R5
M2
VCC'
L3
T6
N5
M4
GNO'
K2
K4
P6
M6
GNO'
L5
J5
J3
H2
H4
G3
BG
432
VCC'
017
A17
C17
817
GNO'
C18
018
818
A19
819
C19
VCC'
GNO'
019
A20
820
C20
821
020
GNO'
C21
A22
VCC'
822
C22
823
A24
GNO'
022
C23
824
C24
GNO'
023
825
A26
C25
024
826
BG
560
VCC'
A17
818
C18
E18
GNO'
C19
019
E19
820
C20
020
VCC'
GNO'
A21
E20
821
C21
021
822
GNO'
C23
E22
VCC'
824
023
C24
A25
GNO'
E23
825
024
C25
GNO'
E25
C27
026
828
829
E26
110
110
1/0
1/0
1/0
GNO
1/0
1/0
1/0
110
1/0 (A14)
1/0, GCK8 (A15)
VCC
GNO
1/0, GCKl (A16)
110 (A17)
1/0
1/0
1/0, TOI
110, TCK
GNO
P234
P235
P236
P237
P238
P239
P240
Pl
P2
P3
P4
P5
P6
P7
1/0
1/0
110
1/0
1/0
1/0
VCC
GNO
1/0
1/0
1/0
1/0
1/0
1/0
P8
P9
Pl0
Pll
GNO
1/0
1/0
1/0
1/0
P12
P13
GNO
P14
P15
1/0
PG
411
GNO'
VCC'
K6
Gl
El
E3
F2
G5
GNO'
J7
H6
C3
02
E5
G7
VCC'
GNO'
H8
F6
84
04
82
G9
GNO'
E7
86
F8
C5
A7
A5
VCe'
GNO'
C7
08
88
C9
E9
F12
GNO'
010
810
FlO
F14
GNO'
C11
BG
432
GNO'
VCC'
A27
025
C26
827
A28
026
GNO'
C27
828
027
829
C28
028
VCC'
GNO'
029
C30
E28
E29
030
031
GNO'
F28
F29
E30
E31
G28
G29
VCC'
GNO'
F30
F31
H28
H29
G30
H30
GNO'
J28
J29
H31
J30
GNO'
K28
BG
560
GNO'
VCC'
C28
027
830
C29
E27
A31
GNO'
028
C30
029
E28
030
E29
VCC'
GNO'
833
F29
E30
031
F30
C33
GNO'
G29
E31
032
G30
F31
H29
VCC'
GNO'
H30
G31
J29
F33
G32
J30
GNO'
K30
H33
L29
K31
GNO'
L30
4-133
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4052XL
Pad Name
110
I/O, TMS
I/O
VCC
I/O
110
GNO
I/O
I/O
I/O
I/O
110
I/O
GNO
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
GNO
VCC
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GNO
I/O
I/O
I/O
110
I/O
I/O
GNO
110
110
VCC
I/O
I/O
I/O
110
GNO
I/O
110
I/O
I/O
GNO
110
I/O
I/O
110
110
I/O
GNO
VCC
I/O
4-134
HQ
240
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
PG
411
B12
E11
E15
VCC'
F16
C13
GNO'
A13
012
B14
E17
E13
A15
GNO'
VCC'
F18
C15
B16
016
018
A17
GNO'
E19
B18
C17
C19
GNO'
VCC'
F20
B20
C21
B22
GNO'
E21
022
A23
B24
C23
F22
VCC'
GNO'
A25
024
E23
C25
B26
A27
GNO'
C27
F24
VCC'
E25
E27
B28
C29
GNO'
F26
028
B30
E29
GNO'
030
032
F28
F30
C31
E31
GNO'
VCC'
B32
BG
432
K29
K30
K31
VCC'
L29
L30
GNO'
M30
M28
M29
M31
N31
N28
GNO'
VCC'
N29
N30
P30
P28
P29
R31
GNO'
R30
R28
R29
T31
GNO'
VCC'
T30
T29
U31
U30
GNO'
U28
U29
V30
V29
V28
W31
VCC'
GNO'
W30
W29
W28
Y31
Y30
Y29
GNO'
Y28
AA30
VCC'
AA29
AB31
AB30
AB29
GNO'
AB28
AC30
AC29
AC28
GNO'
A031
A030
A029
A028
AE30
AE29
GNO'
VCC'
AF31
BG
560
K32
J33
M29
VCC'
L32
M31
GNO'
N29
L33
M32
P29
P30
N33
GNO'
VCC'
P31
P32
R29
R30
R31
R33
GNO'
T31
T29
U32
U31
GNO'
VCC'
U29
U30
V31
V29
GNO'
V30
W33
W31
W30
W29
Y32
VCC'
GNO'
Y31
Y30
AA32
AA31
AA30
AB32
GNO'
AA29
AB31
VCC'
AC31
AB29
A032
AC30
GNO'
A031
AE33
AC29
AE32
GNO'
AG33
AH33
AE29
AG31
AF30
AH32
GNO'
VCC'
AJ32
XC4052XL
Pad Name
I/O
I/O
I/O
I/O
110
GNO
I/O
I/O
110
110
110
1/0,GCK2
0(M1)
GNO
I (MO)
VCC
I (M2)
I/O, GCK3
I/O (HOC)
I/O
I/O
I/O
I/O (LOC)
GNO
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GNO
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
110
110
I/O
GNO
110
I/O
110
I/O
VCC
I/O
110
GNO
I/O
I/O
I/O
I/O
I/O
I/O
GNO
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
HQ
240
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
PG
411
A33
C33
B34
A35
F32
GNO'
C35
B38
E33
G31
H32
B36
A39
GNO'
E35
VCC'
G33
036
C37
F34
J33
038
G35
GNO'
E37
H34
E39
K34
F38
G37
VCC'
GNO'
H38
J37
G39
M34
K36
K38
GNO'
N35
P34
J35
L37
GNO'
M38
R35
H36
T34
VCC'
N37
N39
GNO'
P38
L35
U35
R39
M36
V34
GNO'
VCC'
R37
T38
T36
V36
U37
U39
GNO'
W35
AC39
V38
BG
432
AE28
AF30
AF29
AG31
AF28
GNO'
AG30
AG29
AH31
AG28
AH30
AJ30
AH29
GNO'
AH28
VCC'
AJ28
AK29
AH27
AK28
AJ27
AL28
AH26
GNO'
AK27
AJ26
AL27
AH25
AK26
AL26
VCC'
GNO'
AH24
AJ25
AK25
AJ24
AH23
AK24
GNO'
AL24
AH22
AJ23
AK23
GNO'
AJ22
AK22
AL22
AJ21
VCC'
AH20
AK21
GNO'
AJ20
AH19
AK20
AJ19
AL20
AH18
GNO'
VCC'
AK19
AJ18
AL19
AK18
AH17
AJ17
GNO'
AK17
AL17
AJ16
BG
560
AF29
AH31
AG30
AK32
AJ31
GNO'
AG29
AL33
AH30
AK31
AJ30
AH29
AK30
GNO'
AJ29
VCC'
AN32
AJ28
AK29
AL30
AK28
AM31
AJ27
GNO'
AN31
AL29
AK27
AL28
AJ26
AM30
VCC'
GNO'
AM29
AK26
AL27
AJ25
AN29
AN28
GNO'
AL25
AJ23
AN26
AL24
GNO'
AK23
AN25
AJ22
AL23
VCC'
AM24
AK22
GNO'
AK21
AM22
AJ20
AL21
AN21
AK20
GNO'
VCC'
AL20
AJ19
AM20
AK19
AL19
AN19
GNO'
AL18
AM18
AK17
November 10, 1997 (Version 1.4)
~XILINX
XC4052XL
Pad Name
1/0 (INIT)
VCC
GNO
VO
VO
HQ
240
PB9
P90
P91
P92
P93
1/0
1/0
GNO
1/0
1/0
1/0
1/0
1/0
1/0
VCC
GNO
P94
P9S
P96
P97
P98
1/0
VO
1/0
1/0
1/0
1/0
GNO
1/0
1/0
VCC
1/0
1/0
1/0
1/0
GNO
P99
Pl00
Pl0l
Pl02
Pl03
Pl04
Pl0S
Pl06
VO,
1/0
1/0
1/0
Pl07
Pl0B
GNO
VO
1/0
1/0
1/0
1/0
1/0
Pl09
PlIO
~111
P112
GNO
VCC
VO
1/0
1/0
VO
Pl13
P114
1/0
1/0
GNO,
VO
1/0
1/0
1/0
1/0
1/0, GCK4
GNp
~ONE
VCC
PROGRAM
1/0(07)
1/0, GCKS
1/0
1/0
1/0
1/0
Pl1S
Pl16
Pl17
Pl18
Pl19
Pl20
P121
P122
'P123
P124
P125
P126
GNO~
GNO
1/0
1/0
PG
411
W37
VCC"
GNO"
Y34
AC37
Y3B
M37
GNO"
AB3B
A036
M3S
AE37
AB36
A03B
VCC"
GNO"
AB34
AE39
AM36
AC35
AL3S
AF38
GNO"
AG39
AG37
VCC"
A034
AN39
AE3S
AH3B
GNO"
AJ37
AG3S
AF34
AH36
GNO"
AK38
AP38
AK36
AM34
AH34
AJ35
GNO'
VCC"
AL37
AT3B
AM38
AN37
AK34
AR39
GNO"
AR37
AU37
AN3S
AL33
AV38
AT3S
GNO'
AR35
VCC"
AN33
AM32
AP34
AW39
AN31
AV36
AR33
P127
P128
November 10, 1997,(Version 1.4)
AP32
AU3S
BG
432
AK16
VCC"
GNO"
AL16
AH15
AL15
AJ15
GNO"
AKIS
AJ14
AH14
AK14
AL13
AK13
VCC"
GNO"
AJ13
AH13
AL12
AK12
AJ12
AKll
GNO"
AH12
AJll
VCC"
AL10
AK10
AJl0
AK9
GNO"
ALB
AH10
AJ9
AK8
GNO"
AJ8
AH9
AK7
AL6
AJ7
AHB
GNO"
VCC"
AKB
AL5
AH?
AJ6
AKS
AL4
GNO'
AH6
AJS
AK4
AHS
AK3
AJ4
GNO"
AI-I4
VCC"
AH3
AJ2
AG4
AG3
AH2
AHI
AF4
GNO"
AF3
AG2
BG
560
AJ17
VCC"
GNO"
AL17
AM17
AN17
AK16
GNO"
AM16
ALIS
AK15
AJ15
ANIS
AM14
VCC"
GNO"
AL14
AK14
AJ14
AN13
AM13
AL13
GNO"
AK12
ANll
VCC"
AJ12
ALII
AKll
AM10
GNO*
AL10
AJll
AN9,
AK10
GNO"
AN?
AJ9
AL7
AK8
AN6
AM6
GNO'
VCC"
AJ8
AL6
AK7
AM5
AM4
AJ7
GNO'
AL5
AK6
AN3
AKS
AJ6
AL4
GNP"
AJ5
VCC'
AMI
AH5
AJ4
AK3'
AH4
ALI
AG5
GNO"
AJ3
AK2
XC40S2XL
Pad Name
HQ
240
1/0
1/0
1/0
1/0
VCC
GNO
VO(06)
P129
P130
P131
P132
1/0
1/0
1/0
1/0
1/0
-
GNO
1/0
1/0
1/0
1/0
P133
P134
GNO
P135
P136
P137
P138
P139
P140
P141
P142
-
1/0
1/0
VO
1/0
VCC
1/0(05)
1/0 (CSO)
GNO
1/0
1/0
1/0
1/0
1/0
1/0
GNO
VCC
P143
-
1/0
1/0
1/0
,-
VO
VO
VO
-,
P144
P145
GNO
1/0
P146
P147
P148
P149
P1S0
P151
P152
P1S3
Pl54
PISS
VO
1/0(04)
VO
VCC
GNO
1/0(03)
I/O(RS)
1/0,
1/0
GNO
va
P1S6
P157
1/0
1/0
1/0
1/0
1/0
vce
GNO
P158
1/0
1/0
.'
VO
VO
-
1/0
1/0
GNO
VO(02)
1/0"
vec
,
"
'
P159
P160
P161
PG
411
AV34
AW35
AW33
AU33
VCC'
GNO"
AV32
AU31
AR31
AP28
AP30
AT30
GNO"
AT32
AV30
AR29
AP26
GNO'
AU29
AV28
AT28
AR25
VCC"
AP24
AU27
GNO'
AR27
AW27
AU25
AV26
AT24
AR23
GNO"
VCC'
AW25
AW23
AP22
AV24
AU23
AT22
GNO"
AR21
AV22
AP20
AU21
VCC'
GNO"
AU19
AV20
AVIS
AR19
GNO"
AT18
AW17
AV16
AP18
AU17
AW15
vec'
GNO"
AR17
AT16
AV14
AW13
AU15
AU13
GNP"
ARIS
AP16
VCe"
BG
432
AGI
AE4
AE3
AF2
VCC"
GNO"
AFI
A04
A03
AE2
A02
AC4
GNO"
AC3
AOI
AC2
AB4
GNO"
AB3
AB2
ABI
M3
VCC"
M2
Y2
GNO'
Y4
Y3
Yl
WI
W4
W3
GNO"
VCC"
W2
V2
V4
V3
Ul
U2
GNO'
U4
U3
Tl
T2
VCC"
GNO"
T3
Rl
R2
R4
GNO"
R3
P2
P3
P4
Nl
N2
VeC"
GNO"
N3
N4
Ml
M2
M3
M4
GNO"
L2
L3
VCC'
BG
560
AG4
AH3
AFS
AJ2
VCC"
GNO"
AJI
AF4
AG3
AE5
AHI
AF3
GNO"
AE3
ACS
AEI
A03
GNO'
AC4
AD2
ABS
AC3
VCC"
AA5
AB3
GNO'
AB2
AA4
AA3
YS
Y3
Y2
GNO"
VCC"
W5
W4
W3
WI
V3
VS
GNO"
V4
V2
US
U4
VCC'
GNO"
U3
T2
T4
Rl
GNO"
RS
R4
R5
P2
P3
P4
VCC"
GNO"
Nl
PS
N2
N3
N5
M3
GNO"
M4
Ll
VCC"
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4052XL
Pad Name
1/0
1/0
1/0
1/0
GNO
1/0
1/0
1/0
1/0
HQ
240
P162
P163
P164
P165
P166
·
P167
P168
GNO
1/0
1/0
1/0
1/0
1/0
I/O
GNO
VCC
1/0 (Ol)
1/0 (RCLK, ROY/BUSY)
P169
P170
P171
P172
P173
P174
1/0
1/0
1/0
1/0
GNO
1/0
1/0
1/0
1/0
1/0 (OO, OIN)
1/0, GCK6 (OOUT)
CCLK
VCC
O,TOO
GNO
1/0 (AO,WS)
1/0, GCK7 (Al)
1/0
1/0
1/0
1/0
P175
P176
Pl77
P178
P179
P180
P181
P182
P183
P184
P185
P186
·
GNO
1/0
1/0
1/0 (CS1, A2)
1/0 (A3)
1/0
1/0
VCC
GNO
1/0
1/0
1/0
1/0
1/0
1/0
·
·
P187
P188
·
·
·
-
P189
P190
P191
P192
-
GNO
1/0
1/0
1/0
1/0
P193
P194
P195
GNO
P196
P197
P198
P199
P200
P201
1/0
1/0
1/0
1/0
VCC
1/0
1/0
GNO
4-136
-
PG
411
AV12
AR13
AUll
AT12
GNO"
AP14
ARll
AV10
AT8
GNO"
AT10
AP10
AP12
AR9
AU9
AV8
GNO"
VCC"
AU7
AWl
AW5
AV6
AU5
AP8
GNO"
AR7
AV4
AN9
AWl
AP6
AU3
AR5
VCC"
AN7
GNO"
AT4
AV2
AM8
AL7
AT2
AN5
GNO"
AR3
ARl
AK6
AN3
AM6
AM2
VCC"
GNO"
AL3
AH6
AP2
AK4
ANl
AK2
GNO"
AG5
AF6
AL5
AJ3
GNO"
AH2
AE5
AM4
A06
VCC"
AG3
AGl
GNO"
BG
432
Kl
K2
K3
K4
GNO"
J2
J3
J4
Hl
GNO"
H2
H3
H4
G2
G3
Fl
GNO"
VCC"
G4
F2
F3
El
F4
E2
GNO"
E3
01
E4
02
C2
03
04
VCC"
C4
GNO"
B3
05
B4
C5
A4
06
GNO"
B5
C6
A5
07
B6
A6
VCC"
GNO"
08
C7
B7
09
B8
A8
GNO"
010
C9
B9
CiO
GNO"
Bl0
Al0
Cll
012
VCC"
Bll
C12
GNO"
BG
560
K2
L4
Jl
K3
GNO"
L5
J2
K4
J3
GNO"
Gl
Fl
J5
G3
H4
F2
GNO"
VCC"
F3
G4
02
E3
G5
Cl
GNO"
F4
03
B3
F5
E4
04
C4
VCC"
E6
GNO"
05
A2
06
A3
E7
C5
GNO"
B4
07
C6
E8
B5
A5
VCC"
GNO"
08
C7
E9
A6
B7
09
GNO"
Ell
A9
Cl0
011
GNO"
Bl0
E12
Cll
Bll
VCC"
012
All
GNO"
HQ
240
XC4052XL
Pad Name
I/O
PG
411
AF2
AJ5
AC5
AEl
AH4
A86
GNO"
VCC"
A02
AB4
AE3
ACl
A04
AA5
GNO"
AB2
AC3
AA3
Y6
GNO"
-
1/0
I/O
1/0
1/0
1/0
-
GNO
VCC
1/0 (A4)
1/0{A5)
P202
P203
P205
P206
P207
P208
1/0
1/0
1/0 (A21)
1/0 (A20)
GNO
1/0
1/0
1/0 (A6)
1/0 (A7)
P209
P210
P211
GNO
BG
432
013
B12
C13
A12
014
813
GNO"
VCC"
C14
A13
B14
015
C15
B15
GNO"
A15
C16
B16
A16
GNO"
BG.
560
C13
E14
A13
014
C14
814
GNO"
VCC"
E15
015
C15
A15
C16
E16
GNO"
B17
C17
E17
017
GNO"
6/20197
" Pads labelled GND" or VCC" are internally bonded to Ground or
VCC planes within the associated package. They have no direct
connection to any specific package pin.
Additional XC4052XL Package Pins
HQ240
I
P204
I
P219
GND Pins
I
I
6/3/97
I
Note: These pins may be Not Connected for this device revision,
however for compatability with other devices in this package, these
pins should be tied to GND.
PG411
I
A3
Jl
AT34
All
L39
AUl
A9
026
W39
ALl
AW3
A19
034
Y4
AP36
AWll
A29
F4
Y36
AT6
AW21
All
L1
AA31
AL21
A21
L4
AHll
AL31
I
A21
Wl
AW9
VCC Pins
A31
AA39
AW19
GNDPlns
A37
J39
AAl
AT14
AW31
C39
AJl
AW29
06
AL39
AW37
F36
AP4
Cl
AF4
AT20
014
P4
AF36
AT26
020
P36
AJ39
AU39
C3
L31
AJ3
C29
AAl
AJ29
011
AA4
ALl
A18
B30
Jl
V31
AJ31
AL7
AL30
A23
B3.1
J31
ACl
AKl
AL9
LI
6/3197
BG432
Al
021
AA28
ALll
A2
A25
Cl
Pl
AC31
AK2
AL14
A3
A29
C31
P31
AEl
AK30
AL18
A7
A30
016
T4
AE31
AK31
AL23
VCCPins
A31
L28
AH21
GND Pins
A9
Bl
Gl
T28
AH16
AL2
AL25
A14
B2
G31
Vl
AJl
AL3
AL29
Not Connected Pins
C8
6/3/97
I
-
I
November 10, 1997 (Version 1.4)
----~------------
~XILINX
PG560
A4
813
033
T33
AK1
AM15
AN24
A10
819
E5
V1
AK4
AM21
AN30
A7
A32
B31
K1
V33
AE2
AM7
AN5
A12
81
C2
L2
W2
AG1
AM11
AN10
A1
88
C22
025
E33
J31
M30
T32
AA1
A04
AF1
AJ16
AK24
AL26
AN1
6/20/97
A8
B12
C26
E2
H2
K5
N4
U1
M33
A05
AF2
AJ18
AK25
AM8
AN23
A16
832
H1
W32
AK33
AM32
VCC Pins
A22
C3
K33
AA2
AL2
AN4
A26
C31
M1
A833
AL3
AN8
GND Pins
A14
A18
A20
86
89
815
E1
F32
G2
M33
P33
P1
Y1
AB1
Y33
AG32
AH2
AJ33
AM19
AM25
AM28
AN14
AN16
AN20
Not Connected Pins
A19
A23
A27
B16
826
C8
010
013
016
E10
E13
E21
H3
H5
H31
L31
K29
L3
N30
T3
N31
U2
V32
U33
AB4
AB30
AC1
A029
AE4
A030
AF31
AF32
AG2
AJ21
AK9
AJ24
AL8
AL9
AL12
AM9
AM12
AM23
AN33
A30
C32
N32
A01
AL31
AN12
82
01
R2
AF33
AM2
AN18
A24
823
G33
R32
AC32
AL32
AM33
AN22
A29
827
J32
T1
A033
AM3
AN2
AN27
A28
C9
018
E24
H32
M2
T5
Y4
AC2
AE30
AJ10
AK13
AL16
AM26
A33
C12
022
E32
J4
M5
T30
Y29
AC33
AE31
AJ13
AK18
AL22
AM27
I
Pin Locations for XC4062XL Devices
(Note: XC4062XL is also available in the HQ304 package.
The pinout is identical to the XC4036XL in HQ304.)
XC4062XL
Pad Name
VCC
I/O (A8)
I/O (A9)
HQ240
BG432
PG475
BG560
P212
P213
P214
VCC'
017
A17
C17
B17
VCC'
Y2
Y4
W5
Y6
U3
W3
GNO'
W1
U5
W7
U7
V2
V4
VCC'
GNO'
V6
R1
T6
R3
R5
T4
GNO'
P2
N1
VCC'
N3
VCC'
A17
B18
C18
E18
018
A19
GNO'
C19
019
E19
B20
C20
020
VCC'
GNO'
A21
E20
B21
C21
021
822
GNO'
C23
E22
VCC'
824
110
I/O
I/O
I/O
GNO
I/O (A19)
I/O (A18)
I/O
I/O
I/O (A10)
I/O (A11)
VCC
GNO
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
VCC
I/O
P215
P216
P217
P218
P220
P221
P222
P223
GNO'
C18
018
B18
A19
B19
C19
VCC'
GNO'
019
A20
B20
C20
821
020
GNO'
C21
A22
VCC'
822
November 10, 1997 (Version 1.4)
XC4062XL
Pad Name
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O (A12)
I/O (A13)
GNO
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
VO
I/O
HQ240
BG432
PG475
BG560
P224
P225
P226
P227
C22
B23
A24
GNO'
022
C23
824
C24
P4
R7
M2
GNO'
M4
L3
N5
K2
L5
J1
GNO'
M6
K4
J3
J5
H2
G1
GNO'
VCC'
L7
K6
E1
H4
G5
F2
GNO'
H6
C3
F4
C5
023
C24
A25
GNO'
E23
825
024
C25
B26
E24
GNO'
E25
C27
026
828
B29
E26
GNO'
VCC'
C28
027
B30
C29
E27
A31
GNO'
028
C30
029
E28
P228
P229
P230
P231
P232
P233
P234
P235
P236
P237
GNO'
023
B25
A26
C25
024
B26
GNO'
VCC'
A27
025
C26
B27
A28
026
GNO'
C27
B28
027
B29
4-137
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4062XL
Pad Name
110 (A14)
1/0 GCK8 (A15)
VCC
GNO
1/0, GCK1 (A16)
1/0 (A17)
1/0
1/0
I/O,TOI
I/O,TCK
GNO
HQ240
BG432
PG475
BG560
P238
P239
P240
P1
P2
P3
P4
P5
P6
P7
C28
028
VCC'
GNO'
029
C30
E28
E29
030
031
GNO'
F28
F29
E30
E31
G28
G29
VCC'
GNO'
F30
F31
H28
H29
G30
H30
GNO'
E3
E5
VCC'
GNO'
G7
04
A5
B4
06
F8
GNO'
030
E29
VCC'
GNO'
B33
F29
E30
031
F30
C33
GNO'
G29
E31
032
G30
F31
H29
VCC'
GNO'
H30
G31
J29
F33
G32
J30
GNO'
H32
J31
K30
H33
L29
K31
GNO'
L30
K32
J33
M29
VCC'
L32
M31
GNO'
N29
L33
M32
P29
P30
N33
GNO'
VCC'
P31
P32
R29
R30
R31
R33
GND'
T31
T29
T30
T32
U32
U31
GNO'
VCC'
U29
uao
U33
V32
V31
V29
-
1/0
VO
1/0
1/0
1/0
1/0
VCC
GNO
1/0
1/0
1/0
1/0
1/0
1/0
P8
P9
P10
P11
GNO
1/0
1/0
1/0
1/0
1/0
1/0
P12
P13
GNO
P25
P26
J28
J29
H31
J30
GNO'
K28
K29
K30
K31
VCC'
L29
L30
GNO'
M30
M28
M29
M31
N31
N28
GNO'
VCC'
N29
N30
P30
P28
P29
R31
GNO'
R30
R28
P27
P28
P29
P30
P31
P32
R29
T31
GNO'
VCC'
T30
T29
P14
P15
P16
P17
P18
P19
P20
P21
1/0
1/0
1/0, TMS
1/0
VCC
1/0
1/0
GNO
VO
VO
1/0
1/0
1/0
1/0
GNO
VCC
1/0
1/0
1/0
1/0
1/0
1/0
P22
,
P23
P24
GNO
1/0
1/0
1/0
1/0
1/0
1/0
GNO
VCC
1/0
1/0
1/0
1/0
1/0
1/0
4-138
-
' P33
P34
-
Ua1
U30
B6
E7
08
G9
E9
A7
VCC'
GNO'
B8
C9
G11
010
E11
A9
GNO'
B10
C11
F12
012
A11
G15
GNO'
B12
E13
C13
A13
VCC'
B14
C15
GNO'
G17
F14
016
014
A15
C17
GNO'
VCC'
018
B18
F16
G19
E17
E19
GNO'
A19
F18
C19
020
F20
B20
GNO'
VCC'
C21
A21
022
B22
E23
F22
XC4062XL
Pad Name
HQ240
GNO
1/0
1/0
1/0
1/0
1/0
1/0
VCC
GNO
P35
P36
-
P37
1/0
1/0
1/0
1/0
1/0
1/0
GNO
1/0
1/0
VCC
1/0
1/0
1/0
1/0
GNO
P38
P39
P40
P41
P42
P43
P44
P45
1/0
1/0
VO
1/0
1/0
1/0
P46
P47
VO
P48
P49
P50
P51
GNO
VCC
1/0
1/0
1/0
1/0
1/0
1/0
P52
P53
GNO
1/0
1/0
1/0
VO
VO
1/0, GCK2
0(M1)
GNO
I (MO)
VCC
I (M2)
VO,GCK3
1/0 (HOC)
1/0
1/0
1/0
1/0 (LOC)
P54
P55
P56
P57
P58
P59
P60
P61
P62
pa3
P64
P65
P66
.P67
P68
GNO
1/0
1/0
1/0
1/0
1/0
1/0
PG475
BG560
GNO'
U28
U29
V30
V29
V28
W31
VCC'
GNO'
W30
W29
W28
V31
V30
V29
GNO'
V28
AA30
VCC'
AA29
AB31
AB30
AB29
GNO'
AB28
AC30
AC29
AC28
GNO'
C23
F24
A23
E25
G23
B24
VCC'
GNO'
024
C25
028
A27
E29
C27
GNO'
G25
026
VCC'
F26
B28
030
A29
GNO'
C29
G27
F30
B30
E31
C31
GNO'
F28
032
B32
G31
A33
C33
GNO'
VCC'
B34
A35
E33
034
036
B36
GNO'
F34
038
C37
G37
B38
F38
A39
GNO'
E35
VCC'
G33
J37
G35
K36
C39
K38
C41
GNO'
040
L37
H36
M36
J35
E41
GNO'
V30
W33
W31
W30
W29
V32
VCC'
GNO'
V31
V30
AA32
AA31
AA30
AB32
GNO'
AA29
AB31
VCC'
AC31
AB29
A032
AC30
GNO'
A031
AE33
AC29
AE32
A030
AE31
GNO'
AG33
AH33
AE29
AG31
AF30
AH32
GNO'
VCC'
AJ32
AF29
AH31
AG30
AK32
AJ31
GNO'
AG29
AL33
AH30
AK31
AJ30
AH29
AK30
GNO'
AJ29
VCC'
AN32
AJ28
AK29
AL30
AK28
AM31
AJ27
GNO'
AN3,
AL29
AK27
AL28
AJ26
AM30
-
GNO
1/0
1/0
1/0
1/0
1/0
BG432
-
-
GNO'
AD31
A030
A029
A028
AE30
AE29
GNO'
VCC'
AF31
AE28
AF30
AF29
AG31
AF28
GNO'
AG30
AG29
AH31
AG28
AH30
AJ30
AH29
GNO'
AH28
VCC'
AJ28
AK29
AH27
AK28
AJ27
AL28
AH26
GNO'
AK27
AJ26
AL27
AH25
AK26
AL26
November 10, 1997 (Version 1.4)
~XILINX
XC4062XL
Pad Name
VCC
GNO
I/O
HQ240
P69
P70
P71
P72
1/0
1/0
1/0
1/0
1/0
GNO
I/O
1/0
1/0
1/0
1/0
1/0
P73
P74
GNO
P75
P76
P77
P78
P79
P80
P81
P82
1/0
VO
1/0
1/0
VCC
1/0
1/0
GNO
1/0
1/0
1/0
1/0
1/0
1/0
-
GNO
VCC
P83
1/0
VlO
1/0
P84
P85
P86
pa7
I/O
I/O
1/0
GNO
1/0
1/0
1/0
1/0
1/0
1/0 (INlT)
VCC
GNO
I/O
1/0
1/0
1/0
1/0
1/0
"
VCC
GNO
I/O
I/O
PB8
P89
P90
P91
P92
P93
P94
P95
P96
P97
-
P98
-
1/0
1/0
1/0
1/0
GNO
1/0
PG475
BG560
VCC'
GNO'
AH24
AJ25
AK25
AJ24
AH23
AK24
GNO'
VCC'
GNO'
F40
H38
N37
L35
R35
G41
GNO'
H40
P38
J39
R37
J41
K40
GNO'
L39
M38
T36
M40
VCC'
N39
N41
GNO*
P40
T38
U35
U37
R39
R41
GNO'
VCC'
V36
U39
V3B
V40
W37
W35
GNO'
W41
Y36
W39
AB36
Y40
Y38
VCC'
GNO'
M39
AB38
AB40
AC37
AC39
AC41
GNO'
A036
AC35
AE37
A040
A038
AE39
vCC'
GNO'
AG41
AG39
AG37
AE35
AH38
AF38
GNO'
AF36
VCC'
GNO'
AM29
AK26
AL27
AJ25
AN29
AN28
GNO'
AM26
AK24
AL25
AJ23
AN26
AL24
GNO'
AK23
AN25
AJ22
AL23
VCC'
AM24
AK22
GNO'
AK21 '
AM22
AJ20
AL21
AN21
AK20
GNO'
VCC'
AL20
AJ19
AM20
AK19
AL19
AN19
GNO'
AJ18
AK18
AL18
AM18
AK17
AJ17
vec'
GNO'
AL17
AM17
AN17
AK16
AJ16
AL16
GNO'
AM16
AL15
AK15
AJ15
AN15
AM14
VCC',
GNO'
AL14
AK14
AJ14
AN13
AM13
AL13
GNO'
AK12
AL24
AH22
AJ23
AK23
GNO'
AJ22
AK22
AL22
AJ21
VCC'
AH20
AK21
GNO'
AJ20
AH19
AK20
A.,i19
AL20
AH18
GNO'
VCC'
AK19
AJ18
AL19
AK18
AH17
AJ17
GNO'
-
GNO
1/0
1/0
1/0
1/9
1/0
1/0
BG432
P99
AK17
AL17
AJ16
AK16
VCC'
GNO'
AL16
AH15
AL15
AJ15
GNO'
AK15
AJ14
AH14
AK14
AL13
AK13
vCC'
GNO'
AJ13
AH13
AL12
AK12
A.,i12
AK11
GNO'
AH12
November 10, 1997 (Version 1.4)
XC4062XL
Pad Name
VO
VCC
1/0
1/0
1/0
1/0
GNO
1/0
1/0
1/0
1/0
1/0
1/0
HQ240
BG432
PG475
BG560
P100
P101
P102
P103
P104
P105
P106
AJ11
VCC'
AL10
AK10
AJ10
AK9
GNO'
AL8
AH10
AJ9
AK8
AH40
VCC'
AJ41
AJ39
AJ37
AG35
GNO'
AK40
AK38
AL37
AL39
AM38
AM40
GNO'
AN41
AM36
AK36
AU41
AN39
AP40
GNO'
VCC'
AR41
AL35
AV40
AN37
AT38
AP38
GNO'
AT40
AW39
AP36
AU37
AR37
AU39
GNP'
AR35
VCC'
AN35
AU35
AV38
AT34
BA39
AU33
AY38
GNO'
AV36
AR31
AR33
AV32
BA37
AY36
VCC'
GNO'
AV34
BA35
AU31
AY34
AT3O,
AW33
GNO'
BA33
AV30
AY32
AU29
AW31
BA31
GNO*
AR27
AT28
AN11
VCC·
AJ12
AL11
AK11
AM10
GNO'
AL10
AJ11
AN9
AK10
AM9
AL9
GNO'
AN7
AJ9
AL7
AK8
AN6
AM6
GNO'
VCC'
AJ8
AL6
AK7
AM5
AM4
AJ7
GNO'
AL5
AK6
AN3
AK5
AJ6
AL4
GNO'
AJ5
VCC'
AM1
AH5
AJ4
AK3
AH4
AL1
AG5
GNO'
AJ3
P107
P108
GNO
1/0
1/0
1/0
1/0
1/0
1/0
P109
P110
P111
P112
GNO
VCC
1/0
1/0
1/0
1/0
P113
P114
I/O
1/0
-
GNO
1/0
1/0
1/0
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
VO
I/O
1/0, GCK4
GNO
OONE
VCC
PROGRAM
1/0(07
1/0, GCK5
1/0
1/0
1/0
1/0
GNO
1/0
1/0
1/0
1/0
1/0
1/0
P127
P128
,
VCC
GNO
1/0(06)
-
P129
P130
P131
P132
1/0
I/O
1/0
1/0
1/0
GNO
1/0
1/0
1/0
1/0
1/0
1/0
GNO
1/0
1/0
P133
P134
','
P135
P1:%
P137
GNO'
AJ8
AH9
AK7
AL6
AJ7
AH8
GNO'
VCC'
AK6
AL5
AH7
AJ6
AK5
AL4
GNO'
AH6
AJ5
AK4
AH5
AK3
AJ4
GNO'
AH4
vec'
AH3,
AJ2
AG4
AG3
AH2
AH1
AF4
GNO'
AF3
AG2
AG1
AE4
AE3
1\F2
VCC'
GNO'
AF1
A04
A03
AE2
A02
AC4
GNO'
AC3
A01
AC2
AB4
GNO'
/'.B3
AB2
AK2
AG4
AH3
AF5
AJ2
VCC'
GNO'
AJ1
AF4
AG3
AE5
AH1
AF3
GNO'
AF1
A04
AE3
AC5
AE1
A03
GNO'
AC4
A02
4-139
I
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4D62XL
Pad Name
1/0
1/0
VCC
1/0 (DS)
1/0 (CSO)
GND
1/0
1/0
1/0
1/0
1/0
1/0
HQ240
BG432
PG475
BG560
'P138
P139
P140
P141
P142
P143
AB1
AA3
VCC"
AA2
Y2
GND"
Y4
Y3
Y1
W1
W4
W3
GND"
VCC"
W2
V2
V4
V3
U1
U2
GND"
U4
U3
AY30
AW29
VCC"
BA29
AY28
GND"
AR2S
AV28
AW27
AT26
AV26
BA27
GND"
VCC"
AW2S
AV24
AU2S
AR23
AT24
AY24
GND"
BA23
AU23
AW23
AV20
AY22
AV22
VCC"
GND"
AW21
BA21
AU19
AY20
AU17
AW19
GND"
BA19
AT16
AR19
AV14
AY18
AV1S
VCC"
GND"
AT18
AW17
AR15
BA1S
AT14
AR17
GND"
AW1S
AV16
VCC"
AY14
BA13
AU13
AW13
GND"
AY12
BA11
AV12
AT12
AW11
AY10
GND"
BA9
AU11
AW9
AV10
ABS
AC3
VCC"
AAS
AB3
GND"
AB2
AA4
AA3
YS
Y3
Y2
GND"
VCC"
WS
W4
W3
W1
V3
VS
GND"
V4
V2
U2
U1
US
U4
VCC"
GND"
U3
T2
T3
TS
T4
R1
GND"
R3
R4
RS
P2
P3
P4
VCC"
GND"
N1
PS
N2
N3
N5
M3
GND"
M4
L1
VCC"
-
-
GND
VCC
-
1/0
-
I/O
I/O
I/O
1/0
1/0
P144
P14S
GND
1/0
1/0
1/0
1/0
1/0 (D4)
1/0
VCC
GND
1/0 (D3)
1/0 (RS)
1/0
1/0
1/0
1/0
P146
P147
-
P148
P149
P1S0
P1S1
P1S2
P1S3
P1S4
P1S5
GND
1/0
1/0
1/0
1/0
1/0
1/0
VCC
GND
P1S6
P157
P1S8
1/0
1/0
1/0
1/0
1/0
1/0
GND
1/0 (D2)
1/0
VCC
1/0
1/0
1/0
1/0
GND
1/0
1/0
1/0
1/0
T1
T2
VCC"
GND"
T3
R1
PiS9
P160
P161
P162
P163
P164
P16S
P166
R2
R4
GND"
R3
P2
P3
P4
N1
N2
VCC"
GND"
N3
N4
M1
M2
M3
M4
GND"
L2
L3
VCC"
Kl
P167
P168
K2
K3
K4
GND"
J2
J3
J4
H1
P169
P170
P171
P172
GND"
H2
H3
H4
G2
,
I/O
1/0
GND
1/0
1/0
I/O
1/0
4-140
K2
L4
J1
K3
GND"
L5
J2
K4
J3
H2
K5
GND"
G1
F1
J5
G3
XC4062XL
Pad Name
HQ240
1/0
1/0
GND
VCC
1/0 (D1)
1/0 (RCLK, RDY/BUSY)
I/O
I/O
1/0
1/0
GND
1/0
1/0
1/0
1/0
1/0 (DO, DIN)
1/0, GCK6 (DOUT)
CCLK
VCC
O,TOO
GND
1/0 (AO, WS)
1/0, GCK7 (A1)
1/0
1/0
1/0
I/O
GND
1/0
1/0
1/0 (CS1, A2)
1/0 (A3)
1/0
P173
P174
-
P17S
P176
P1n
P178
P179
P180
P181
P182
P163
Pl84
P18S
P186
P187
P188
I/O
1/0
I/O
P189
P190
P191
P192
1/0
1/0
GND
1/0
1/0
1/0
1/0
I/O
P193
P194
P19S
1/0
GND
1/0
1/0
1/0
1/0
VCC
I/O
1/0
P196
P197
P198
P199
P200
P201
-
GND
1/0
1/0
1/0
1/0
1/0
1/0
GND
VCC
1/0 (A4)
1/0 (AS)
1/0
1/0
PG475
BG560
G3
F1
GND"
VCC"
G4
F2
F3
E1
F4
E2
GND"
E3
D1
E4
D2
C2
D3
D4
VCC"
C4
GND"
B3
DS
B4
CS
AY8
BA7
GND"
VCC"
AV8
AY6
AR11
AT8
AU9
AWS
GND"
AY4
BAS
AV4
AR9
AU5
AV6
ARS
VCC"
AN7
GND"
AR7
AW3
AU3
AW1
AP6
AV2
GND"
AT4
ANS
AU1
AM6
AT2
AL7
VCC"
GND"
ARI
AP2
AM4
AN3
ALS
AK6
GND"
ANI
AJS
AM2
AH4
AL3
AK4
GND"
AG7
AGS
AK2
AJ3
VCC"
AJ1
AF6
GND"
AH2
AF4
AE7
AES
AG3
AG1
GND"
VCC"
AD6
AD4
AE3
AC5
H4
F2
GND"
VCC"
F3
G4
D2
E3
GS
C1
GND"
F4
D3
B3
FS
E4
D4
C4
VCC"
E6
GND"
DS
A2
D6
A3
E7
CS
GND"
B4
D7
C6
E8
BS
AS
VCC"
GND"
D8
C7
E9
A6
B7
D9
GND"
D10
C9
El1
A9
C10
D11
GND"
Bl0
E12
C11
B11
VCC"
D12
A11
GND"
C13
E14
A13
D14
C14
B14
GND"
VCC'
E1S
D15
C1S
A1S
A4
VCC
GND
I/O
I/O
BG432
-
P202
P203
P20S
P206
D6
GND"
BS
C6
AS
D7
B6
A6
VCC"
GND"
D8
C7
B7
D9
B8
AS
GND"
D10
C9
B9
C10
GND"
B10
Al0
C11
D12
VCC"
B11
C12
GND"
D13
B12'
C13
A12
D14
B13
GND"
VCC"
C14
A13
B14
D1S
November 10, 1997 (Version 1.4)
~XILINX
XC4062XL
Pad Name
I/O (A21)
I/O (A20)
GNO
1/0
1/0
1/0
1/0
1/0 (A6)
1/0 (A7)
GNO
6/16/97
HQ240
BG432
PG475
BG560
P207
P208
C15
B15
GNO'
A02
AC7
GNO'
AC1
AC3
AB6
AB2
AB4
AA3
GNO'
C16
E16
GNO'
016
B16
B17
C17
E17
017
GNO'
A15
C16
B16
A16
GNO'
P209
P210
P211
, Pads labelled GND' or VCC' are internally bonded to Ground or
VCC planes within the package. They have no direct connection to
any specific package pin.
Additional XC4062XL Package Pins
PG475
A37
E21
N35
AA41
AR29
AW41
B2
F6
T2
AF2
AT6
AY2
A3
U1
AH6
E15
L41
AL41
AU15
E37
C1
A17
AL1
E27
P36
AR21
AU27
E39
vee Pins
B16
B26
F36
G13
T40
AA1
AF40
AJ7
AT22
AT36
AY16
AY26
GNO Pins
C7
G3
A41
A25
AR3
AW7
F10
F32
U41
M35
AR39
AT10
AW35
BA17
A31
J7
B40
G29
M5
AJ35
AU21
AY40
02
N7
AA37
AR13
AW37
BA3
L1
AA7
BA1
G21
AE41
AT20
BA25
AP4
P6
AE1
C35
G39
AH36
AT32
BA41
AU7
5/5/97
HQ240
GND Pins
I
P204
BG560
P219
vee Pins
5/5/97
Note: These pins may be Not Connected for this device revision,
however for compatability with other devices in this package, these
pins should be tied to GND.
BG432
A4
B13
033
T33
AK1
AM15
AN24
A10
B19
E5
V1
AK4
AM21
AN30
A7
A32
831
K1
V33
AE2
AM11
AN5
A12
B1
C2
L2
W2
AG1
AM19
AN10
A1
B12
025
H3
M2
Y29
AC33
AF32
AK13
AM12
A8
C8
E2
H5
M5
M1
A05
AG2
AK25
AM23
vce Pins
A1
021
AA28
AL11
A11
L1
M31
AL21
A21
L4
AH11
AL31
A31
L28
AH21
A2
A25
C1
P1
AC31
AK2
AL14
A3
A29
C31
P31
AE1
AK30
AL18
GND Pins
A7
A9
A14
A30
B1
B2
016
G1
G31
T4
T28
V1
AE31
AJ1
AH16
AK31
AL2
AL3
AL23
AL25
AL29
Not Connected Pins
C3
L31
AJ3
C29
AA1
AJ29
011
AA4
AL1
A18
B30
J1
V31
AJ31
AL7
AL30
A23
B31
J31
AC1
AK1
AL9
C8
5/5/97
A16
B32
H1
W32
AK33
AM32
A22
C3
K33
M2
AL2
AN4
A26
C31
M1
AB33
AL3
AN8
GND Pins
A14
A18
A20
B9
B15
B6
E1
F32
G2
P1
P33
M33
Y1
Y33
AB1
AG32
AH2
AJ33
AM25
AM28
AM33
AN14
AN16
AN20
Not Connected Pins
A23
A27
A28
C12
C22
C26
E10
E13
E21
H31
J4
K29
N4
N30
M30
AB4
AB30
M33
A029
AE4
AE30
AJ10
AJ13
AJ21
AL22
AL8
AL12
AM27
AN1
AN23
A30
C32
N32
A01
AL31
AN12
B2
01
R2
AF33
AM2
AN18
A24
B23
G33
R32
AC32
AL32
AM7
AN22
A29
B27
J32
T1
A033
AM3
AN2
AN27
A33
013
E32
L3
N31
AC1
AF2
AJ24
AL26
AN33
B8
022
E33
L31
Y4
AC2
AF31
AK9
AM8
5/5/97
Pin Locations for XC4085XL Devices
XC4085XL
Pad Name
VCC
1/0 (A8)
1/0 (A9)
1/0
1/0
1/0
1/0
GNO
1/0 (A19)
1/0 (A18)
1/0
1/0
I/O (A10)
1/0 (A11)
VCC
BG56Q
VCC'
A17
818
C18
E18
018
A19
GNO'
C19
019
E19
820
C20
020
VCC'
November 10, 1997 (Version 1.4)
XC4085XL
Pad Name
PG559
VCC'
AB6
A84
AA7
AC1
AA5
M3
GNO'
Y8
AB2
Y6
AA1
Y4
W7
vec'
GNO
I/O
I/O
I/O
I/O
I/O
I/O
1/0
1/0
GNO
I/O
1/0
I/O
I/O
VCC
BG560
PG559
GNO'
A21
E20
821
C21
021
822
E21
C22
GNO'
022
A23
C23
E22
VCe'
GNO'
W5
V6
V4
Y2
U3
U7
V2
US
GNO'
T4
U1
R3
R5
VCC'
4-141
II
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4085XL
Pad Name
1/0
1/0
110
1/0
GND
1/0
1/0
1/0
1/0
1/0
1/0
1/0
110
GND
VCC
1/0
110
1/0
110
1/0
1/0
1/0 (A12)
1/0 (A13)
GND
VCC
110
1/0
1/0
1/0
1/0
1/0
GND
110
1/0
1/0
1/0
1/0 (A14)
110, GCK8 (A15)
VCC
GND
110, GCK1 (A16)
110 (A17)
110
1/0
1/0 (TDI)
1/0 (TCK)
GND
1/0
1/0
1/0
110
110
1/0
VCC
GND
1/0
1/0
1/0
110
110
1/0
110
110
VCC
GND
1/0
1/0
1/0
1/0
1/0
4-142
BG560
PG559
B24
D23
C24
A25
GND'
E23
B25
D24
C25
B26
E24
C26
D25
GND'
VCC'
A27
A28
E25
C27
D26
B28
B29
E26
GND'
VCC'
C28
D27
B30
C29
E27
A31
GND'
D28
C30
D29
E28
D30
E29
VCC'
GND'
B33
F29
E30
D31
F30
C33
GND'
G29
E31
D32
G30
F31
H29
VCC'
GND'
E32
E33
H30
G31
J29
F33
G32
J30
VCC'
GND'
H31
K29
H32
J31
K30
T8
T2
P4
R7
GND'
N3
R1
N5
P2
M4
L1
L3
P8
GND'
VCC'
N7
K2
M6
J1
L5
H2
K4
J3
GND'
VCeL7
J5
G1
H4
F2
G5
GND'
H6
K8
D2
J7
F4
E3
VCC'
GND'
C1
C3
F6
A3
H8
D4
GND'
D6
C5
E7
B4
H10
G9
VCC'
GND'
F8
D8
B6
E9
A7
G11
H14
F12
VCC'
GND'
G13
E11
B8
D10
A9
XC4085XL
Pad Name
1/0
110
1/0
GND
1/0
1/0
1/0 (TMS)
1/0
VCC
1/0
1/0
1/0
1/0
GND
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
GND
VCC
1/0
1/0
1/0
1/0
1/0
1/0
GND
1/0
1/0
1/0
1/0
1/0
1/0
GND
VCC
1/0
1/0
1/0
1/0
1/0
1/0
GND
1/0
1/0
1/0
1/0
1/0
1/0
VCC
GND
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
GND
1/0
1/0
1/0
1/0
VCC
1/0
1/0
BG560
PG559
H33
L29
K31
GND'
L30
K32
J33
M29
VCC'
L31
M30
L32
M31
GND'
N29
L33
N30
N31
M32
P29
P30
N33
GND'
VCC'
P31
P32
R29
R30
R31
R33
GND'
T31
T29
T30
T32
U32
U31
GND'
VCC'
U29
U30
U33
V32
V31
V29
GND'
V30
W33
W31
W30
W29
Y32
VCC'
GND'
Y31
Y30
AA33
Y29
AA32
AA31
AA30
AB32
GND'
AA29
AB31
AB30
AC33
VCC'
AC31
AB29
G15
B10
H16
GND'
C9
E13
A11
D12
VCC'
C11
B14
G17
E15
GND'
D14
A15
C13
B16
E17
F18
A17
G19
GND'
VCC'
D16
C15
B18
H2O
B20
E19
GND'
D18
F20
G21
C17
D20
E21
GND'
VCC'
C21
F22
A21
D22
B22
G23
GND'
E23
C23
A23
D24
B24
H24
VCC'
GND'
F24
E25
B26
D26
A27
G25
B28
C27
GND'
F26
E27
A29
D28
VCC'
G27
B30
November 10, 1997 (Version 1.4)
~XILINX
XC4085XL
Pad Name
- -
------
--
..
BG560
PG559
I/O
I/O
GNO
110
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
A032
AC30
GNO'
A031
AE33
AC29
AE32
A030
AE31
AF32
A029
GNO'
C29
E29
GNO'
030
A33
C31
B34
H28
A35
G29
E31
GNO'
VCC
VCC'
VCC'
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
AF31
AE30
AG33
AH33
AE29
AG31
AF30
AH32
GNO'
032
C35
C33
B36
H30
A37
G31
F32
GNO'
VCC
VCe'
VCC'
110
I/O
I/O
I/O
I/O
110
GNO
I/O
I/O
110
110
110
I/O, GCK2
0(M1)
GNO
I (MO)
AJ32
AF29
AH31
AG30
AK32
AJ31
GNO'
AG29
AL33
AH30
AK31
AJ30
AH29
AK30
GNO'
AJ29
E33
034
B38
G33
A41
E35
GNO'
036
F36
G35
H34
B40
E37
038
GNO'
C39
VCC
VCC'
VCC'
I (M2)
I/O, GCK3
I/O (HOC)
I/O
110
I/O
110 (LOC)
GNO
I/O
I/O
I/O
I/O
I/O
I/O
AN32
AJ28
AK29
AL30
AK28
AM31
AJ27
GNO'
AN31
AL29
AK27
AL28
AJ26
AM30
H36
F38
C41
040
B42
J37
K36
GNO'
H38
042
G39
C43
F40
E41
VCC
VCC'
VCC'
GNO
110
110
I/O
I/O
I/O
I/O
I/O
I/O
GNO'
AM29
AK26
AL27
AJ25
AN29
AN28
AK25
AL26
GNO'
L37
J39
F42
H40
G43
J41
H42
N37
VCC
VCC'
VCC'
GNO
I/O
I/O
I/O
I/O
GNO'
AJ24
AM27
AM26
AK24
GNO'
P36
M38
J43
L39
November 10, 1997 (Version 1.4)
XC4085XL
Pad Name
BG560
PG559
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
AL25
AJ23
AN26
AL24
GNO'
AK23
AN25
AJ22
AL23
K42
K40
L43
L41
GNO'
R37
P42
T36
N39
VCC
VCe'
VCC'
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
AM24
AK22
AM23
AJ21
GNO'
AL22
AN23
AK21
AM22
AJ20
AL21
AN21
AK20
GNO'
M40
R43
N41
R39
GNO'
U37
T42
P40
U43
R41
VCC
VCC'
VCC'
I/O
I/O
I/O
110
110
110
GNO
I/O
110
110
I/O
I/O
I/O (INIT)
AL20
AJ19
AM20
AK19
AL19
AN19
GNO'
AJ18
AK18
AL18
AM18
AK17
AJ17
W37
T40
Y42
U41
Y36
GNO'
W39
AA43
Y38
Y40
AA37
AA39
VCC
vee'
VCC'
GNO
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O
GNO'
AL17
AM17
AN17
AK16
AJ16
AL16
GNO'
AM16
AL15
AK15
AJ15
AN15
AM14
GNO'
AA41
II
V42
U39
V38
GNO'
V40
,6,838
--
AB42
AB40
AC37
AC39
GNO'
A036
AC41
A038
AC43
A040
AE39
VCC
vCC'
VCC'
GNO
I/O
I/O
I/O
I/O
110
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
GNO'
AL14
AK14
AJ14
AN13
AM13
AL13
AK13
AJ13
GNO'
AM12
AL12
AK12
AN11
GNO'
AE37
AF40
A042
AF42
AF38
AG39
AG43
AG37
GNO'
AH40
AJ41
AG41
AK40
vcc
vec'
VCC'
I/O
AJ12
AJ39
4-143
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4085XL
Pad Name
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
VCC
I/O
1.0
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O, GCK4
GNO
OONE
VCC
PROGRAM
1/0(07)
I/O, GCK5
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GNO
1/0(06)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
4-144
BG560
PG559
AL11
AK11
AM10
GNO'
AL10
AJ11
AN9
AK10
AM9
AL9
AJ10
AM8
GNO'
VCC'
AK9
AL8
AN7
AJ9
AL7
AK8
AN6
AM6
GNO'
VCC'
AJ8
AL6
AK7
AM5
AM4
AJ7
GNO'
AL5
AK6
AN3
AK5
AJ6
AL4
GNO'
AJ5
VCC'
AM1
AH5
AJ4
AK3
AH4
AL1
AG5
GNO'
AJ3
AK2
AG4
AH3
AF5
AJ2
VCC'
GNO'
AJ1
AF4
AG3
AE5
AH1
AF3
AE4
AG2
VCC'
GNO'
A05
AF2
AF1
A04
AH42
AH36
AL39
GNO'
AJ37
AJ43
AM40
AK42
AN41
AL41
AR41
AK36
GNO'
VCC'
AL37
AN43
AM38
AP42
AN39
AR43
AP40
AT40
GNO'
VCC'
AN37
AR39
AT42
8A43
AU43
AU39
GNO'
AT38
AP36
AR37
AV42
AV40
AW41
GNO'
AY42
VCC'
BB42
BC41
AV38
BA39
AT36
BB40
AY40
GNO'
BA41
BB38
AY38
BC37
AW37
AT34
VCC'
GNO'
AU35
AV36
BB36
AY36
BC35
AW35
AU33
AT30
VCC'
GNO'
AV32
AU31
AW33
BB34
XC4085XL
Pad Name
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O (OS)
I/O (CSO)
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
1/0(04)
I/O
VCC
GNO
1/0(03)
I/O(RS)
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
1/0(02)
I/O
I/O
I/O
VCC
I/O
BG560
PG559
AE3
AC5
AE1
A03
GNO'
AC4
A02
AB5
AC3
VCC'
AB4
AC1
AAS
AB3
GNO'
AB2
AA4
AA3
Y5
AA1
Y4
Y3
Y2
GNO'
VCC'
W5
W4
W3
W1
V3
V5
GNO'
V4
V2
U2
U1
U5
U4
VCC'
GNO'
U3
T2
T3
T5
T4
R1
GNO'
R3
R4
R5
P2
P3
P4
VCC'
GNO'
N1
P5
N2
N3
N4
M2
N5
M3
GNO'
M4
L1
L3
MS
VCC'
K2
AY34
BC33
AU29
AT28
GNO'
BA35
BB30
AW31
AY32
VCC'
BA33
AU27
BC29
AW29
GNO'
AY30
BA31
BB28
AW27
BC27
AV26
AU2S
AY28
GNO'
VCC'
BA29
AT24
BB26
AW25
BB24
AY26
GNO'
AV24
AU23
BA27
BC23
AY24
AW23
VCC'
GNO'
BA23
AV22
AY22
BB22
AU21
AW21
GNO'
BA21
BC21
AY20
BB20
AT20
AV20
VCC'
GNO'
AW19
AY18
BB18
AU19
BC17
BA17
AV18
AW17
GNO'
AY16
BB16
AU17
BA15
VCC'
AW15
November 10, 1997 (Version 1.4)
~XILINX
XC4085XL
Pad Name
1/0
1/0
1/0
GNO
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
GNO
VCC
1/0
1/0
1/0
110
1/0
110
1/0
110
GNO
VCC
1/0(01)
110 (RCLK
ROY/BUSY)
1/0
1/0
1/0
1/0
GNO
110
1/0
W----
110
1/0 (00, DIN)
1/0, GCK6 (OOUT)
CCLK
VCC
O,TOO
GNO
1/0 (AO, WS)
1/0, GCK7 (A1)
1/0
1/0
1/0
1/0
GNO
1/0
1/0
110 (CS1, A2)
110 (A3)
110
1/0
VCC
GNO
1/0
1/0
110
110
1/0
1/0
110
1/0
VCC
GNO
110
110
I/O
BG560
PG559
L4
J1
K3
GNO'
L5
J2
K4
J3
H2
K5
H3
J4
GNO'
VCC'
G1
F1
J5
G3
H4
F2
E2
H5
GNO'
VCC'
F3
G4
BC15
AY14
BA13
GNO'
AT16
BB14
AU15
BC11
AW13
BB10
AY12
BA11
GNO'
VCC'
AT14
AU13
AV12
BC9
AW11
BB8
AY10
AU11
GNO'
VCC'
BA9
AW9
02
E3
G5
C1
GNO'
F4
03
B3
F5
E4
04
C4
VCC'
E6
GNO'
05
A2
06
A3
E7
C5
GNO'
B4
07
C6
E8
B5
AS
VCC'
GNO'
08
C7
E9
A6
B7
09
C8
E10
VCC'
GNO'
B8
A8
010
BC7
AY8
AV8
AT10
GNO'
AU9
BB6
AW7
BC3
AY6
BB4
BAS
VCC'
BA3
GNO'
AT8
AV6
BB2
AY4
AR7
AP8
GNO'
AT6
AY2
AU5
BA1
AV4
AW3
VCC'
GNO'
AN7
AR5
AV2
AT4
AU1
AR3
AT2
AL7
VCC'
GNO'
AK8
AM6
AN5
November 10, 1997 (Version 1.4)
XC4085XL
Pad Name
1/0
110
1/0
1/0
110
GNO
1/0
I/O
110
1/0
VCC
1/0
1/0
I/O
1/0
GNO
110
1/0
I/O
1/0
110
1/0
1/0
110
GNO
VCC
1/0 (A4)
110 (A5)
1/0
1/0
I/O (A21)
1/0 (A20)
GNO
1/0
1/0
1/0
1/0
I/O (A6)
1/0 (A7)
GNO
6/13/97
BG560
PG559
C9
E11
A9
C10
011
GNO'
810
E12
C11
811
VCC'
012
A11
E13
C12
GNO'
B12
013
C13
E14
A13
014
C14
B14
GNO'
VCeE15
015
C15
A15
C16
E16
GNO'
016
B16
B17
C17
E17
017
GNO'
AR1
AP4
AN3
AP2
AJ7
GNO'
AH8
AL5
AN1
AM4
VCC'
AL3
AJ5
AK2
AG7
GNO'
AK4
AJ3
AG5
AJ1
AF6
AH2
AE7
AH4
GNO'
VCC'
AG3
A08
AG1
AF4
AE5
A06
GNO'
A04
AF2
AC7
A02
AC5
AC3
GNO'
II
Additional XC4085XL Package Pins
BGS60
A4
813
033
T33
AK1
AM15
AN24
A10
819
E5
V1
AK4
AM21
AN30
A7
A32
B31
K1
V33
AE2
AM11
AN5
A12
B1
C2
L2
W2
AG1
AM19
AN10
A1
6/4/97
A33
A16
832
H1
W32
AK33
AM32
VCC Pins
A22
C3
K33
AA2
AL2
AN4
A26
C31
M1
AB33
AL3
AN8
GND Pins
A14
A18
A20
B6
B9
B15
E1
F32
G2
P1
M33
P33
Y1
AB1
Y33
AG32
AH2
AJ33
AM25
AM28
AM33
AN14
AN16
AN20
Not Connected Pins
AN33
AC2 I AN1
A30
C32
N32
A01
AL31
AN12
B2
01
R2
AF33
AM2
AN18
A24
823
G33
R32
AC32
AL32
AM7
AN22
A29
827
J32
T1
A033
AM3
AN2
AN27
4-145
XC4000E and XC4000X Series Field Programmable Gate Arrays
PG559
vee Pins
A13
C37
H12
N43
AE3
AL43
AU3
8A19
A31
F14
H18
P6
AE41
AM8
AU7
8A25
A43
F30
H26
P38
AF8
AM36
AU37
8A37
A5
E5
H22
W1
AH38
AV16
8812
A19
E39
K6
W43
AM2
AV28
8832
A25
E43
K38
AB8
AM42
AV34
BC5
82
G3
H32
V8
AF36
AT12
AU41
BC1
GND Pins
A39
F10
M2
AB36
AP6
AW1
8C19
C7
G7
M8
V36
AK6
AT18
AV14
BC13
C19
G37
M36
W3
AK38
AT26
AV30
BC31
C25
G41
N1
W41
AL1
AT32
8A7
8C43
812
F16
M42
AE1
AP38
AW5
8C25
832
F28
T6
AE43
AT22
AW39
BC39
E1
F34
T38
AH6
AV10
AW43
5/8/97
, Pads labelled GND' or vee' are internally bonded to Ground or
vee planes within the package. They have no direct connection to
any specific package pin.
t =E only, tt =XL only
4-146
November 10. 1997 (Version 1.4)
~XIUNX
Product Availability
Table 25 - Table 27 show the planned packages and speed grades for XC4000-Series devices. Call your local sales office for
the latest availability information, or see the Xilinx WEBLINX at http://www.xilinx.com for the latest revision of the
specifications.
Table 25: Component Availability Chart for XC4000XL FPGAs
PINS
84
~a
TYPE
~~
o.a.
"a a
l-
a.u.
160
-gc..
'\-u.
.co -g,o
"'f-
J:
"
CODE
XC4003E
100
aa.
C\I
C\I
C}
a.
225
~c5
iLOO
240
t
~fl:
~o
I
en
C\I
C\I
C}
a:J
0
' a
f-
a
'
CJ
77
80
~
Cl...
'
~~JJ.lmlm~>
'-v--'
'-v--'
2 Doubles
3 Longs
'--v----"
8 Singles
'-v--'
3 Longs
'-v--'
2 Doubles
3 Longs
2 Doubles
Rev 1.1
Figure 7: Spartan Series CLB Routing Channels and Interface Block Diagram
4-180
November 25,1997 (Version 0.6)
~XILINX
CLB Routing Channels
The routing channels around the CLB are derived from
three types of interconnects; single-length, double-length,
and longlines. At the intersection of each vertical and horizontal routing channel is a Signal steering matrix called a
Programmable Switch Matrix (PSM). Figure 7 shows the
basic routing channel configuration showing single-length
lines, double-length lines and longlines as well as the CLBs
and PSMs. The CLB to routing channel interface is shown
as well as how the PSMs interface at the channel intersections.
CLB Interface
A block diagram of the CLB interface signals is shown in
Figure 8. The input signals to the CLB are distributed
y
GIN
GOUT
G1
G3
G3
CLB
G1
K
F3
F1
><
C\I
u..
~
Programmable Switch Matrices
The horizontal and vertical single- and double-length lines
intersect at a box called a programmable switch matrix
(PSM). Each PSM consists of programmable pass transistors used to establish connections between the lines (see
Figure 9).
For example, a single-length signal entering on the right
side of the switch matrix can be routed to a single-length
line on the top, left, or bottom sides, or any combination
thereof, if multiple branches are required. Similarly, a double-length signal can be routed to a double-length line on
any or all of the other three edges of the programmable
switch matrix.
Single-Length Lines
Single-length lines provide the greatest interconnect flexibility and offer fast routing between adjacent blocks. There
are eight vertical and eight horizontal single-length lines
associated with each CLB. These lines connect the switching matrices that are located in every row and column of
CLBs.
X
0
evenly on all four sides providing maximum routing flexibility. In general, the entire architecture is symmetrical and
regular. It is well suited to established placement and routing algorithms. Inputs, outputs, and function generators can
freely swap positions within a CLB to avoid routing congestion during the placement and routing operation. The
Jexceptions'are the clock (K) input and CIN/COUT signals.
The K input is routed to dedicated global vertical lines as
well as 4 single-length lines and is on the left side of the
CLB. The CIN/COUT signals are routed through dedicated
interconnects which do. not interfere with the general routing structure. The output signals from the CLB are available
to drive both vertical and horizontal channels.
C\I
(!j
Figure 8: CLB Interconnect Signals
r
r-
-
fo-
t-I-
tl
I
I
I
I
I
L.::
-l- I""'"
~I-
I
t-
-
I
I
I-
t-I-
~
Six Pass Transistors Per
Switch Matrix Interconnect Point
Figure 9: Programmable Switch Matrix
November 25,1997 (Version 0.6)
4-181
I
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Single-length lines are connected by way of the programmable switch matrices, as shown in Figure 9" Routing connectivity is shown in Figure 7"
Single-length lines incur a delay whenever they go through
a PSM" Therefore, they are not suitable for routing signals
for long distances" They are normally used to conduct signals within a localized area and to provide the branching for
nets with fanout greater than one"
Double-Length Lines
The double-length lines consist of a grid of metal segments,
each twice as long as the single-length lines: they run past
two CLBs before entering a PSM" Double-length lines are
grouped in pairs with the PSMs staggered, so that each line
goes through a PSM at every other row or column of CLBs
(see Figure 7)"
There are four vertical and four horizontal double-length
lines associated with each CLB. These lines provide faster
signal routing over intermediate distances, while retaining
routing flexibility"
Longlines
Longlines form a grid of metal interconnect segments that
run the entire length or width of the array" Longlines are
intended for high fan-out, time-critical signal nets, or nets
that are distributed over long distances"
Each Spartan series longline has a programmable splitter
switch at its center. This switch can separate the line into
lOB
lOB
two independent routing channels, each running half the
width or height of the array"
Routing connectivity of the longlines is shown in Figure 7"
The longlines also interface to some 3-state buffers which
is described later in "3-Stale Long
Drivers" on
page 4-188"
1/0 Routing
Spartan series devices have additional routing around the
lOB ring" This routing is called a VersaRing" The VersaRing
facilitates pin-swapping and redesign without affecting
board layout Included are eight double-length lines, and
four longlines"
Global Nets and Buffers
The Spartan series devices have dedicated global networks" These networks are designed to distribute clocks
and other high fanout control signals throughout the
devices with minimal skew"
Four vertical longlines in each CLB column are driven
exclusively by special global buffers" These longlines are in
addition to the verticallonglines used for standard interconnect The four global lines can be driven by either of two
types of global buffers; Primary Global buffers (BUFGP) or
Secondary Global buffers (BUFGS)" Each of these lines
can be accessed by one particular Primary Global buffer, or
by any of the Secondary Global buffers, as shown in
Figure 10" The clock pins of every CLB and lOB can also be
sourced from local interconnect
lOB
lOB
BUFGS
BUFGP
--+D
PGCK4
SGCK1
lOB
lOB
Any BUFGS
1
One BUFGP
per Global Line
One BUFGP
lOB
lOB
SGCK3
PGCK2
SGCK2
D-+-
-----<}--O
PGCK3
BUFGS
BUFGP
lOB
lOB
lOB
lOB
Figure 10: Spartan Series Global Net Distribution
4-182
November 25, 1997 (Version 0"6)
~XILINX
The four Primary Global buffers offer the shortest delay and
negligible skew. Four Secondary Global buffers have
slightly longer delay and slightly more skew due to potentially heavier loading, but offer greater flexibility when used
to drive non-clock CLB inputs.
The Primary Global buffers must be driven by the semidedicated pads (PGCK1-4). The Secondary Global buffers
can be sourced by either semi-dedicated pads (SGCK1-4)
or internal nets. Each corner of the device has one Primary
buffer and one Secondary buffer.
Using the library symbol called BUFG results in the software choosing the appropriate clock buffer, based on the
timing requirements of the design. A global buffer should be
specified for all timing-sensitive global signal distribution.
To use a global buffer, place a BUFGP (primary buffer),
BUFGS (secondary buffer), or BUFG (either primary or
secondary buffer) element in a schematic or in HDL code.
Advanced Features Description
Distributed RAM
Optional modes for each CLB allow the function generators
(F-LUT and G-LUT) to be used as Random Access Memory (RAM).
Read and write operations are significantly faster for this
on-chip RAM than for off-chip implementations. This speed
advantage is due to the relatively short signal propagation
delays within the, FPGA.
Memory Configuration Overview
There are two available memory configuration modes: single-port RAM and dual-port RAM. For both these modes,
write operations are synchronous (edge-triggered), while
read operations are asynchronous. In the Single-Port
Mode, a single CLB can be configured as either a 16 x 1,
(16 x 1) x 2 or 32 x 1 RAM array. In the Dual-Port mode, a
single CLB can be configured only as one 16 x 1 RAM
array. The different CLB memory configurations are summarized in Table 7. Any of these possibilities can be individually programmed into a Spartan Series CLB.
• The 16 x 1 Single-Port configuration contains a RAM
array with 16 locations, each one-bit wide. One 4-bit
address decoder determines the RAM location for write
and read operations. There is one input for writing data
and one output for reading data, all at the selected
address.
• The (16 x 1) x 2 Single-Port configuration combines two
16 x 1 Single Port configurations (each according to the
preceding description). There is one data input, one
data output and one address decoder for each array.
These arrays can be addressed independently.
November 25, 1997 (Version 0.6)
•
The 32 x 1 Single-Port configuration contains a RAM
array with 32 locations, each one-bit wide. There is one
data input, one data output, and one 5-bit address
decoder.
• The Dual Port mode 16 x 1 configuration contains a
RAM array with 16 locations, each one-bit wide. There
are two 4-bit address decoders, one for each port. One
port consists of an input for writing and an output for
reading, all at a selected address. The other port
consists of one output for reading from an
independently selected address.
Table 7: CLB Memory Configurations
16 x 1
..,j
..,j
Mode
Single-Port
Dual-Port
(16 x 1) x 2
..,j
32x 1
..,j
i':;'iii,.
ii;
I-----.~
0..
Do or 0 1
spa
~
WCLK
Figure 11: Logic Diagram for the Single-Port RAM
NOTE:
1. The (16 x 1) x 2 configuration combines two 16 x 1 Single Port RAMs, each with its own independent address bus and
data input. The same WE,and WCLK signals are connected to both RAMs.
2. n = 4 for the 16 x 1 and (16 x 1) x 2 configurations. n = 5 for the 32 x 1 configuration
Writing data to the Single-Port RAM is essentially the same
as writing to a data register. It is an edge-triggered (synchronous) operation periormed by applying an address to
the A inputs and data to the D input during the active edge
of WCLK while WE is High.
The timing relationships are shown in Figure 12. The High
logic level on WE enables the input data register for writing.
The active edge of WCLK latches the address, input data,
and WE signals. Then, an internal write pulse is generated
that loads the data into the memory cell.
- - - - - - - - - - - - - - - - - - - - - -,1,----"';.;..;;..-____ 1
WCLK(K)
------------'1
WE
WCLK can be configured as active on either the rising edge
(default) or the falling edge. While the WCLK input to the
RAM accepts the same signal as the clock input to the
associated CLB's flip-flops, the sense of this WCLK input
can be inverted with respect to the sense of the flip-flop
clock inputs. Consequently, within the same CLB, data at
the RAM's SPO line can be stored in a flip-flop with either
the same or the inverse clock polarity used to write data to
the RAM.
The WE input is active-High and cannot be inverted within
the CLB.
Allowing for settling time, the data on the SPO output
reflects the contents of the RAM location currently
addressed. When the address changes, following the asynchronous delay T ILO, the data stored at the new address
location will appear on SPO. If the data at a particular RAM
address is overwritten, after the delay Twos, the new data
will appear on SPO.
Dual-Port Mode
In dual-port mode, the function generators (F-LUT and GLUT) are used to create a 16 x 1 Dual-Port memory. Of the
two data ports available, one permits read and write operations at the address specified by A[3:0j while the second
provides only for read operations at the address specified
independently by DPRA[3:0j. As a result, simultaneous
read/write operations at different addresses (or even at the
same address) are supported.
X6461
The functional organization of the 16 x 1 Dual-Port RAM is
shown in Figure 13.
Figure 12: Data Write and Access Timing for RAM
4-184
November 25, 1997 (Version 0.6)
~XILINX
4
5f-
A[3:0]
c:r:&3
16x 1
f-W
RAM
w-'
c:r:
4
W
f-
a: co
4
5
co
(5
W
c:r:
WE
~
f-
::;)
SPO
a.
~
D
WCLK
I
16x 1
RAM
DPRA[3:0]
~----+DPO
Figure 13: Logic Diagram for the Dual-Port RAM
The Dual-Port RAM signals and the CLB signals from
which they are originally derived are shown in Table 9.
Table 9: Dual-Port RAM Signals
RAM Signal
D
A[3:0]
DPRA[3:0]
WE
WCLK
SPO
DPO
Function
Data In
Read Address for Single-Port.
Write Address for Single-Port
and Dual-Port.
Read Address for Dual-Port
Write Enable
Clock
Single Port Out
(addressed by A[3:0])
Dual Port Out
(addressed by DPRA[3:0])
CLB
Signal
DIN
F1 -F 4
G 1 -G 4
SR
K
FOUT
GOUT
The RAM16X1 D primitive used to instantiate the Dual-Port
consists of an upper and a lower 16 x 1 memory array. The
address port labeled A[3:0] supplies both the read and
write addresses for the lower memory array, which behaves
the same as the 16 x 1 Single-Port RAM array described
November 25, 1997 (Version 0.6)
previously. Single Port Out (SPO) serves as the data output
for the lower memory. Therefore, SPO reflects the data at
address A[3:0].
The other address port, labeled DPRA[3:0] for Dual Port
Read Address, supplies the read address for the upper
memory. The write address for this memory, however,
comes from the address A[3:0]. Dual Port Out (DPO)
serves as the data output for the upper memory. Therefore,
DPO reflects the data at address DPRA[3:0].
By using A[3:0] for the write address and DPRA[3:0] for the
read address, and reading only the DPO output, a FIFO
that can read and write simultaneously is easily generated.
The simultaneous read/write capability possible with the
Dual-Port RAM can provide twice the effective data
throughput of a Single-Port RAM alternating read and write
operations.
The timing relationships for the Dual-Port RAM mode are
shown in Figure 12.
Note that write operations to RAM are synchronous (edgetriggered); however, data access is asynchronous.
4-185
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Initializing RAM at FPGA Configuration
Both RAM and ROM implementations of the Spartan series
are initialized during device configuration. The initial contents are defined via an INIT attribute or property attached
to the RAM or ROM symbol, as described in the schematic
library guide. If not defined, all RAM contents are initialized
to zeros, by default.
RAM initialization occurs only during device configuration.
The RAM content is not affected by GSR.
More Information on using RAM inside CLBs
Three application notes are available from Xilinx that discuss synchronous (edge-triggered) RAM: "Xilinx Edge-Trig-
gered and Dual-Port RAM CapabilitY;' "Implementing
FIFOs in Xilinx RAM;' and "Synchronous and Asynchronous FIFO Designs:' All three application notes apply to
both the Spartan and the Spartan-XL series.
The carry chain in Spartan devices can run either up or
down. At the top and bottom of the columns where there
are no CLBs above and below, the carry is propagated to
the right. (See Figure 14.)
EJ
EJ EJ
r--C-L~Bc..., B B
J
Dedicated fast carry logic greatly increases the efficiency
and performance of adders, subtractors, accumulators,
comparators and counters. It also opens the door to many
new applications involving arithmetic operation, where the
previous generations of FPGAs were not fast enough or too
inefficient. High-speed address offset calculations in microprocessor or graphics systems, and high-speed addition in
digital signal processing are two typical applications.
The two 4-input function generators can be configured as a
2-bit adder with built-in hidden carry that can be expanded
to any length. This dedicated carry circuitry is so fast and
efficient that conventional speed-up methods like carry
generate/propagate are meaningless even at the 16-bit
level, and of marginal benefit at the 32-bit level. This fast
carry logic is one of the more significant features of the
Spartan series, speeding up arithmetic and counting functions.
4-186
~
J
J
CLe
Fast Carry Logic
Each CLB F-LUT and G-LUT contains dedicated arithmetic
logic for the fast generation of carry and borrow signals.
This extra output is passed on to the function generator in
the adjacent CLB. The carry chain is independent of normal routing resources.
CLe
~ J
CLB
~~&CLe
X6687
Figure 14: Available Spartan Carry Propagation
Paths
Figure 15 on page 4-187 shows a Spartan series CLB with
dedicated fast carry logic. The carry logic shares operand
and control inputs with the function generators. The carry
outputs connect to the function generators, where they are
combined with the operands to form the sums.
Figure 16 on page 4-188 shows the details of the carry
logic for the Spartan. This diagram shows the contents of
the box labeled "CARRY LOGIC" in Figure 15.
The fast carry logic can be accessed by placing special
library symbols, or by using Xilinx Relationally Placed Macros (RPMs) that already include these symbols.
November 25,1997 (Version 0.6)
~XILINX
CARRY
LOGIC
G
1----------..... Y
H
G4--~-+~--~---
G3--~-+----~--~
G
G2--~-+----~---
YO
G1--~-+----~---
H
H1--~------~---
XO
F3~~-r-r---+---
F
F1~~--~---+--~-----.....
COUT
X
¢II
K
SIR
EC
X6699
Figure 15: Fast Carry Logic in Spartan CLB
November 25, 1997 (Version 0.6)
4-187
I
Spartan and Spartan-XL Families Field Programmable Gate Arrays
COUT
G1 ---------1
G2
G4--------r----------r---------4--------------~
G3
COUTO
TO
FUNCTION
GENERATORS
F2
F1
F4
F3----~--t-~===-----+-----------------__q
)(2000
GIN DOWN
Figure 16: Detail of Spartan Dedicated Carry Logic
3-State Long Line Drivers
Three-State Buffer Examples
A pair of 3-state buffers is associated with each CLB in the
array. These 3-state buffers (BUFT) can be used to drive
signals onto the nearest horizontal long lines above and
below the CLB. They can therefore be used to implement
multiplexed or bidirectional buses on the horizontal longlines, saving logic resources.
Figure 17 shows how to use the 3-state buffers to implement a multiplexer. The selection is accomplished by the
buffer 3-state signal.
There is a weak keeper at each end of these two horizontal
longlines. This circuit prevents undefined floating levels.
However, it is overridden by any driver.
The buffer enable is an active-High 3-state (i.e. an activeLow enable), as shown in Table 10.
Pay particular attention to the polarity of the T pin when
uSing these buffers in a design. Active-High 3-state (T) is
identical to an active-Low output enable, as shown in
Table 10.
Table 10: Three-State Buffer Functionality
IN
T
OUT
o
IN
x
IN
z
-100 kQ
Weak Keeper"
Figure 17: 3-State Buffers Implement a Multiplexer
4-188
November 25, 1997 (Version 0.6)
~XlllNX
On-Chip Oscillator
Global3-State
Spartan series devices include an internal oscillator. This
oscillator is used to clock the power-on time-out, for configuration memory clearing, and as the source of CClK in
Master configuration modes. The oscillator runs at a nominal 8 MHz frequency that varies with process, Vcc, and
temperature. The output frequency falls between 4 MHz
and 10 MHz.
A separate Global 3-State line (GTS) as shown in Figure 5
on page 4-177 forces all FPGA outputs to the high-impedance state, unless boundary scan is enabled and is executing an EXTEST instruction. GTS does not compete with
other routing resources; it uses a dedicated distribution network.
The oscillator output is optionally available after configuration. Any two of four resynchronized taps of a built-in divider
are also available. These taps are at the fourth, ninth, fourteenth and nineteenth bits of the divider. Therefore, if the
primary oscillator output is running at the nominal 8 MHz,
the user has access to an 8 MHz clock, plus any two of
500 kHz, 16 kHz, 490 Hz and 15 Hz (up to 10% lower for
low-voltage devices). These frequencies can vary by as
much as -50% or +25%.
These signals can be accessed by placing the OSC library
element in a schematic or in HDl code. The oscillator is
automatically disabled after configuration if the OSC symbol is not used in the design.
Global Signals: GSR and GTS
Global Set/Reset
A separate Global Set/Reset line, as shown in Figure 3 on
page 4-176 for the ClB and Figure 6 on page 4-178 for the
lOB, sets or clears each flip-flop during power-up, reconfiguration, or when a dedicated Reset net is driven active.
This global net (GSR) does not compete with other routing
resources; it uses a dedicated distribution network.
Each flip-flop is configured as either globally set or reset in
the same way that the local set/reset (SR) is specified.
Therefore, if a flip-flop is set by SR, it is also set by GSR.
Similarly, if in reset mode, it is reset by both SR and GSR.
STARTUP
PAD >-----1 >------'----J GSR
IBUF
GTS
02
03
0104
ClK DONEIN
X5260
Figure 18: Schematic Symbols for Global Set/Reset
GSR can be driven from any user-programmable pin as a
global reset input. To use this global net, place an input pad
and input buffer in the schematic or HDl code, driving the
GSR pin of the STARTUP symbol. (See Figure 18.) A specific pin location can be assigned to this input using a lOC
attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the
input buffer to invert the sense of the GSR signal. Alternatively, GSR can be driven from any internal node.
November 25, 1997 (Version 0.6)
GTS can be driven from any user-programmable pin as a
global 3-state input. To use this global net, place an input
pad and input buffer in the schematic or HDl code, driving
the GTS pin of the STARTUP symbol. This is similar to what
is shown in Figure 18 for GSR except the IBUF would be
connected to GTS. A specific pin location can be assigned
to this input using a lOC attribute or property, just as with
any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of
the Global 3-State signal. Alternatively, GTS can be driven
from any internal node.
Boundary Scan
The 'bed of nails' has been the traditional method of testing
electronic assemblies. This approach has become less
appropriate, due to closer pin spacing and more sophisticated assembly methods like surface-mount technology
and mUlti-layer boards. The IEEE Boundary Scan Standard
1149.1 was developed to facilitate board-level testing of
electronic assemblies. Design and test engineers can
imbed a standard test logic structure in their device to
achieve high fault coverage for 110 and internal logic. This
structure is easily implemented with a four-pin interface on
any boundary scan-compatible IC. IEEE 1149.1-compatible devices may be serial daisy-chained together, connected in parallel, or a combination of the two.
The Spartan Series implements IEEE 1149.1-compatible
BYPASS, PRELOAD/SAMPLE and EXTEST boundary
scan instructions. When the boundary scan configuration
option is selected, three normal user I/O pins become dedicated inputs for these functions. Another user output pin
becomes the dedicated boundary scan output. The details
of how to enable this circuitry are covered later in this section.
By exercising these input signals, the user can serially load
commands and data into these devices to control the driving of their outputs and to examine their inputs. This
method is an improvement over bed-of-nails testing. It
avoids the need to over-drive device outputs, and it reduces
the user interface to four pins. An optional fifth pin, a reset
for the control logic, is described in the standard but is not
implemented in Xilinx devices.
The dedicated on-chip logic implementing the IEEE 1149.1
functions includes a 16-state machine, an instruction register and a number of data registers. The functional details
can be found in the IEEE 1149.1 specification and are also
4-189
II
Spartan and Spartan-XL Families Field Programmable Gate Arrays
discussed in the Xilinx application note: "Boundary Scan in
FPGA Devices."
Figure 19 on page 4-190 is a diagram of the Spartan Series
boundary scan logic. It includes three bits of Data Register
per lOB, the IEEE 1149.1 Test Access Port controller, and
the Instruction Register with decodes.
Spartan Series devices can also be configured through the
boundary scan logic. See "Configuration Through the
Boundary Scan Pins" on page 4-197.
Data Registers
The primary data register is the boundary scan register. For
each lOB pin in the FPGA, bonded or not, it includes three
bits for In, Out and 3-State Control. Non-lOB pins have
appropriate partial bit population for In or Out only. PROGRAM, CCLK and DONE are not included in the boundary
scan register. Each EXTEST CAPTURE-DR state captures
all In, Out, and 3-state pins.
The data register also includes the following non-pin bits:
TDO.T, and TDO.O, which are always bits 0 and 1 of the
data register, respectively, and BSCANT.UPD, which is
always the last bit of the data register. These three boundary scan bits are special-purpose Xilinx test signals.
The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.
The FPGA provides two additional data registers that can
be specified using the BSCAN macro. The FPGA provides
two user pins (BSCAN.SEL 1 and BSCAN.SEL2) which are
the decodes of two user instructions. For these instructions,
two
corresponding
pins
(BSCAN.TD01
and
BSCAN.TD02) allow user scan data to be shifted out on
TDO. The data register clock (BSCAN.DRCK) is available
for control of test logic which the user may wish to implement with CLBs. The NAND of TCK and RUN-TEST-IDLE
is also provided (BSCAN.IDLE).
Instruction Set
The Spartan Series boundary scan instruction set also
includes instructions to configure the device and read back
the configuration data. The instruction set is coded as
shown in Table 11.
DATA IN
o
TDI
lOB.I +-~--+-----+-----1
DATAOUT
UPDATE
SHIFT!
CLOCK DATA
CAPTURE
REGISTER
o--~-~
EXTEST
Figure 19: Spartan Series Boundary Scan Logic
4-190
November 25, 1997 (Version 0.6)
~XILINX
Bit Sequence
TOO.T
Bit 0 ( TOO end)
Bit 1
Bit 2
The bit sequence within each lOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the boundary
scan 1/0 data register, while the output-only pins contributes all three bits.
TDO.o
{ Top-edge lOBs (Right to Left)
The first two bits in the 1/0 data register are TDO.T and
TDO.O, which can be used for the capture of internal signals. The final bit is BSCANT.UPD, which can be used to
drive an internal net. These locations are primarily used by
Xilinx for internal testing.
{ Left-edge lOBs (Top to Bottom)
From a cavity-up view of the chip (as shown in EPIC), starting in the upper right chip corner, the boundary scan dataregister bits are ordered as shown in Figure 20. The devicespecific pinout tables for the Spartan Series include the
boundary scan locations for each lOB pin.
{ Bottom-edge lOBs (Left to Right)
MODE.I
{ Right-edge lOBs (Bottom to Top)
BSCANT.UPD
(TOI end)
Figure 20:
BSDL (Boundary Scan Description Language) files for
Spartan Series devices are available on the Xilinx FTP site.
Boundary Scan Bit Sequences075_ 01
Including Boundary Scan in a Schematic
Avoiding Inadvertent Boundary Scan
If boundary scan is only to be used during configuration, no
special schematic elements need be included in the schematic or HDL code. In this case, the special boundary scan
pins TDI, TMS, TCK and TDO can be used for user functions after configuration.
If TMS or TCK is used as user 1/0, care must be taken to
ensure that at least one of these pins is held constant during .configuration. In some applications, a situation may
occur where TMS or TCK is driven during configuration.
This may cause the device to go into boundary scan mode
and disrupt the configuration process.
To indicate that boundary scan remain enabled after configuration, place the BSCAN library symbol and connect the
TD!, TMS, TCK and TDO pad symbols to the appropriate
pins, as shown in Figure 21.
Even if the boundary scan symbol is used in a schematic,
the input pins TMS, TCK, and TDI can still be used as
inputs to be routed to internal logic. Care must be taken not
to force the chip into an undesired boundary scan state by
inadvertently applying boundary scan input patterns to
these pins. The simplest way to prevent this is to keep TMS
High, and then apply whatever signal is desired to TDI and
TCK.
To prevent activation of boundary scan during configuration, do either of the following:
•
•
TMS: Tie High to put th.e Test Access Port controller
in a benign RESET state
TCK: Tie High or LOW-don't toggle this clock input.
For more information regarding boundary scan, refer to the
Xilinx Application Note,"Boundary Scan in FPGA Devices."
Table 11: Boundary Scan Instructions
Instruction
12
0
0
11
0
0
0
1
0
1
1
1
1
1
0
0
1
1
10
0
1
Test
Selected
EXTEST
SAMPLEI
PRELOAD
USER 1
TOO Source
1/0 Data
Source
DR
DR
DR
PinlLogic
BSCAN.
User Logic
TD01
1
USER2
BSCAN.
User Logic
TD02
0 READ BACK Readback Data PinlLogic
1 CONFIGURE
DOUT
Disabled
Reserved
0
1
BYPASS Bypass Register
-
0
November 25,1997 (Version 0.6)
Optional
To User
Logic
IBUF
BSCAN
TOI
TMS
From {
User Logic
TDO
TOO
DACK
TCK
IDLE
TOO1
SEL1
TD02
SEL2
To User
Logic
)(2675
Figure 21: Boundary Scan Schematic Example
I
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Configuration and Test
Configuration is the process of loading design-specific programming data into one or more FPGAs to define the functional operation of the internal blocks and their
interconnections. This is somewhat like loading the command registers of a programmable peripheral chip. Spartan
Series devices use several hundred bits of configuration
data per CLB and its associated interconnects. Each configuration bit defines the state of a static memory cell that
controls either a function look-up table bit, a multiplexer
input, or an interconnect pass transistor. The Xilinx development system translates the design into a netlist file. It
automatically partitions, places and routes the logic and
generates the configuration data in PROM format.
Table 12: Pin Functions During Configuration
CONFIGURATION MODE
SLAVE
MASTER
SERIAL
SERIAL
Configuration Mode Control
Spartan series devices have two configuration modes.
•
•
=
MODE 1 sets Slave Serial mode
MODE =0 sets Master Serial mode
The. control pin (MODE) is sampled prior to starting configuration to determine the configuration mode. After configuration, this pin is unused. The MODE pin has a weak pullup resistor turned on during configuration. With MODE
High, Slave Serial mode is selected, which is the most popular configuration mode used primarily for daisy-chained
devices. Therefore, for the most common configuration
mode, the MODE pin can be left unconnected. (Note, however, that the internal pull-up resistor value can be as high
as 100 kQ.) If the Master Serial mode is desired, an external pull-down resistor value of 4.7 kn, connected to the
MODE pin, is recommended.
During configuration, some of the I/O pins are used temporarily for the configuration process. All pins used during
configuration are shown in Table 12 on page 4-192.
Master Serial Mode
The Master serial mode uses an internal oscillator to generate a Configuration Clock (CCLK) for driving potential
slave devices and the Xilinx serial-configuration PROM
(SPROM). The CCLK speed is selectable as either 1 MHz
(default) or 8 MHz. Configuration always starts at the
default slow frequency, then can switch to the higher frequency during the first frame. Frequency tolerance is -50%
to +25%.
In Master Serial mode, the CCLKoutput of the device
drives a Xilinx SPROM that feeds the FPGA DIN input.
Each rising edge of the,CCLK output increments the Serial
PROM internal address counter. The next data bit is put on
the SPROM data output, connected to the FPGA DIN pin.
The FPGA accepts this data on the subsequent rising
CCLK edge.
4-192
1. A shaded table cell represents the internal pull-up
used before and during configuration.
2. ~presents an input; (0) represents an output.
3. INIT is an open-drain output during configuration.
When used in a daisy-chain configuration the Master Serial
FPGA is placed as the first device in the chain and is
referred to as the lead FPGA. The lead FPGA presents the
preamble data, and all data that overflows the lead device,
on its DOUT pin. There is an internal pipeline delay of 1.5
CCLK periods, which means that DOUT changes on the
falling CCLK edge, and the next FPGA in the daisy chain
accepts data on the subsequent rising CCLK edge. See the
timing diagram in Figure 22.
In the bitstream generation software, the user can specify
Fast Configuration Rate, which, starting several bits into the
first frame, increases the CCLK frequency by a factor of
eight. For actual timing values please refer to the specification section. Be sure that the serial PROM and slaves are
fast enough to support this data rate. Devices such as
XC3000A and XC31 OOA do not support the Fast Configuration Rate option.
The SPROM CE input can be driven from either LDCor
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output after configuration. Using DONE can also avoid contention on DIN,
provided the early DONE option is invoked.
Figure 23 shows a full master/slave system. The leftmost
device is in Master Serial mode, all other devices in the
chain are in Slave Serial mode.
Master Serial mode is selected by a Low on the MODE pin.
November 25, 1997 (Version 0.6)
----.---.
__....._ _. - - - - ..
-
~XILlNX
CCLK
(Output)
o
TCKDS
Serial Data In
Serial DOUT
n+1
n-3
n+2
n-2
n-1
(Output) _ _ _ _ _~ ' - -_ _ _ _ _- - ' ' - -_ _ _ _ _~ ' - - _ _ _ _ _ _J
X3223
I
I
CCLK
Description
DIN setup
DIN hold
1
2
Symbol
I T DSCK
I T..cKDS
,~
Min
20
0
Max
Units
ns
ns
..
I
Notes: 1. At power-up, Vee must rise from 2.0 V to Vec min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until Vee is valid.
2. Master Serial mode timing is based on testing in slave mode.
Figure 22: Master Serial Mode Programming Switching Characteristics
Slave Serial Mode
Serial Daisy Chain
In Slave Serial mode, the FPGA receives serial configuration data on the rising edge of CCLK and, after loading its
configuration, passes additional data out, resynchronized
on the next falling edge of CCLK.
Multiple devices with different configurations can be connected together in a "daisy chain," and a single combined
bitstream used to configure the chain of slave devices.
In this mode, an external signal drives the CCLK input of
the FPGA (most often from a Master Serial device). The
serial configuration bitstream must be available at the DIN
input of the lead FPGA a short setup time before each rising CCLK edge.
The lead FPGA then presents the preamble data-and all
data that overflows the lead device-on its DOUT pin.
There is an internal delay of 0.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge.
Figure 23 shows a full master/slave system. A Spartan
series device in Slave Serial mode should be connected as
shown in the third device from the left.
Slave Serial mode is selected by a high on the MODE pin.
Slave Serial is the default mode if the MODE pin is left
unconnected, as it has a weak pull-up resistors during configuration.
Multiple slave devices with identical configurations can be
wired with parallel DIN inputs. In this way, rnultiple devices
can be configured simultaneously.
November 25, 1997 (Version 0.6)
To configure a daisy chain of devices, wire the CCLK pins
of all devices in parallel, as shown in Figure 23 on
page 4-194. Connect the DOUT of each device to the DIN
of the next. The lead or master FPGA and following slaves
each passes resynchronized configuration data coming
from a single source. The header data, including the length
count, is passed through and is captured by each FPGA
when it recognizes the 0010 preamble. Following the
length-count data, each FPGA outputs a High on DOUT
until it has received its required number of data frames.
After an FPGA has received its configuration data, it
passes on any additional frame· start bits and configuration
data on DOUT. When the total number of configuration
clocks applied after memory initialization equals the value
of the 24-bit length count, the FPGAs begin the start-up
sequence and become operational together. FPGA I/O are
normally released two CCLK cycles after the last configuration bit is received.
The daisy-chained bitstream is not simply a concatenation
of the indiVidual bitstreams. The PROM file formatter must
be used to combine the bitstreams for a daisy-chained configuration.
4-193
Spartan and Spartan-XL Families Field Programmable Gate Arrays
NOTE:
M2, M1, MO can be shorted
to Vee if not used as 1/0
Vee
47KJ ~.7K
4.7K
MO Ml
~
MODE
DONE
DIN
XC1700D
4.7K
DIN
DATA
U5C
GE
iNiT
RESET/DE
I
Spartan
+5V
CEO
r- ,-.
-
XC3100A
SLAVE
SLAVE
vppW-
elK
DOUT
CCLK
CCLK
cce<
r-
Dour
DIN
'{£c
Spartan
MASTER
SERIAL
~ PR'6GRAM
' - - - M2
N/C- MODE
DOUT
I
PWRDN
PROGRAM
DONE
(Low Reset Option Used)
iNiTil
~ RESET
~'l
DIP
PROGRAM
89025_01
Figure 23: Master/Slave Serial Mode Circuit Diagram
---r
~
~" CCD"":!=®,oo,:r'-----J--.---0-5
DIN
Bitn+ 1
Bltn
:====~~
-T-CC-L----}-,
-------1DOUT
(Output)
0',~
L®,=?r--_______
=x
Bitn-1
Bitn
X5379
Description
Symbol
Min
DIN setup
20
1
TDCC
DIN hold
2
0
TCCD
DIN to DOUT
3
Tcco
CCLK
High time
4
45
TCCH
Low time
5
45
TccL
Frequency
Fcc
Note: Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
Max
30
10
Units
ns
ns
ns
ns
ns
MHz
Figure 24: Slave Serial Mode Programming Switching Characteristics
Setting CCLK Frequency
Data Stream Format
In Master mode, CCLK can be generated in either of two
frequencies. In the default slow mode, the frequency
ranges from 0.5 MHz to 1.25 MHz for Spartan series
devices. In fast CCLK mode, the frequency ranges from
4 MHz to 10 MHz for Spartan series devices. The frequency is selected by an option when running the bitstream
generation software. Slow mode is the default.
The data stream ("bitstream") format is identical for both
configuration modes. The data stream format is shown in
Table 13. Bit-serial data is read from left to right.
4-194
The configuration data stream begins with a string of eight
ones, a preamble code, followed by a 24-bit length count
and a separator field of ones. This header is followed by the
actual configuration data in frames. The length and number
of frames depends on the device type (see Table 14).
Each frame begins with a start field and ends with an error
check. A postamble code is required to signal the end of
November 25, 1997 (Version 0.6)
--- - - -
---
-------.~.
_.
---'-'~---~-~
~XILINX
data for a single device. In all cases, additional start-up
bytes of data are required to provide four clocks for the startup sequence at the end of configuration. Long daisy
chains require additional startup bytes to shift the last data
through the chajn. All startup bytes are don't-cares; these
bytes are not included in bitstreams created by the Xilinx
software.
A selection of CRC or non-CRG error checking is allowed
by the bitstream generation software. The non-CRC error
checking tests for a deSignated end-of-frame field for each
frame. For CRC error checking, the software calculates a
running CRC and inserts a unique four-bit partial check at
the end of each frame. The 11-bit CRC check of the last
frame of an FPGA includes the last seven data bits.
Table 13: Spartan Series Data Stream Formats
Detection of an error results in the suspension of data loading and the pulling down of the INIT pin. In Master serial
mode, CCLK and address signals continue to operate
externally. The user must detect TNIT and initialize a new
configuration by pulsing the PROGRAM pin Low or cycling
Vcc.
Data Type
Fill Byte
11111111b
Preamble Code
0010b
Length Count
COUNT(23:0)
Fill Bits
1111b
Start Field
Ob
Data Frame
DATA(n-1 :0)
CRC or Constant
Field Check
•Extend Write Cycle
xxxx (CRe)
or 0110b
-
xX·~.f...;:i .•.L:n.:."" • '. ."" ••ti::"·" [l"".';.'~.•J".';;'•..'l"...>.
liT
Cyclic Redundancy Check (CRC) for
Configuration and Readback
Start-Up Bytes
•••••••
xxh
LEGEND:
Unshaded
The Cyclic Redundancy Check is a method of error detection in data transmission applications. Generally, the transmitting system performs a calculation on the serial
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits. The receiving system
performs an identical calculation on the bitstream and compares the result with the received checksum.
Each data frame of the configuration bitstream has four
error bits at the end, as shown in Table 13. If a frame data
error is detected during the loading of the FPGA, the configuration process with a potentially corrupted bitstream is
terminated. The FPGA pulls the INIT pin Low and goes into
a Wait state.
Once per bitstream
Once per data frame
Table 14: Spartan Program Data
Device
Max System Gates
CLBs
(Row x Col.)
XCS05IXL
XCS10IXL
XCS20IXL
XCS30IXL
XCS40IXL
5,000
10,000
20,000
30,000
40,000
100
(10 x 10)
196
(14x 14)
400
(20 x 20)
576
(24 x 24)
784
(28 x 28)
lOBs
Flip-Flops
80
112
160
192
224
360
616
1,120
1,536
2,016
56
Horizontal Longlines
20
28
40
48
TBUFs per Longline
12
16
22
26
30
Bits per Frame
126
166
226
266
306
428
572
788
932
1,076
53,936
94,960
178,096
247,920
329,264
53,984
95,008
178,144
247,968
329,312
Frames
Program Data
PROM Size (bits)
Notes:
1. Bits per Frame = (lOx number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits
Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40 (header) + 8
2. The user can add more "one" bits as leading dummy bits in the header, or, if CRC '= off, as trailing dummy bits at the end of
any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra "one"
bits, even for extra leading ones at the beginning of the header.
November 25, 1997 (Version 0.6)
4-195
I
Spartan and Spartan-XL Families Field Programmable Gate Arrays
During Readback, 11 bits of the 16-bit checksum are added
to the end of the Readback data stream. The checksum is
computed using the CRC-16 CCITT polynomial, as shown
in Figure 25. The checksum consists of the 11 most significant bits of the 16-bit code. A change in the checksum indicates a change in the Readback bitstream. A comparison
to a previous checksum is meaningful only if the readback
data is independent of the current device state. CLB outputs should not be included (Readback Capture option not
used), and if RAM is present, the RAM content must be
unchanged.
Boundary Scan
Instructions
Available:
Statistically, one error out of 2048 might go undetected.
Configuration Sequence
There are four major steps in the Spartan Series power-up
configuration sequence.
•
•
•
EXTEST'
SAMPLE/PRELOAD
BYPASS
CONFIGURE'
(' if f'R1JGR1\M = High)
-1.31JS per Frame
Configuration Memory Clear
Initialization
Configuration
Start-Up
Master Delays Before
Sampling Mode Lines
The full process is illustrated in Figure 26.
Configuration Memory Clear
MasterCCLK
When power is first applied or is reapplied to an FPGA, an
internal circuit forces initialization of the configuration logic.
When Vcc reaches an operational level, and the circuit
passes the write and read test of a sample pair of configuration bits, a time delay is started. This time delay is nominally 16 ms, and up to 10% longer in the Spartan-XL
devices. The delay is four times as long when in Master
Serial Mode (MODE is Low), to allow ample time for all
slaves to reach a stable Vcc. When all INIT pins are tied
together, as recommended, the longest delay takes precedence. Therefore, devices with different time delays can
easily be mixed and matched in a daisy chain.
Goes Active --J~------------,
I
II
"5
!g
I
_f
II
"5
!
19
SAMPLE/PRELOAD
BYPASS
Configuration
No
memory
Full
Yesi----------,
This delay is applied only on power-up. It is not applied
when reconfiguring an FPGA by pulsing the PROGRAM pin
Pass
Configuration
Data to DOUT
CCLK
Count Equals
)N:.:co_ _---'
Length
Count
,,
,,
,,
SERIAL DATA IN :
Polynomial: X16 +X15 + X2 + 1
r - - - - - - - - - - - - - - - - - - - - - ___ - - - J
,
,··1
1
1 1
I
LAST DATA FRAME
Readback Data Stream
EXTEST
SAMPLE PRELOAD
BYPASS
USER 1
USER 2
}
Operational
If Boundary Scan
is Selected
CONFIGURE
READBACK
Figure 25: Circuit for Generating CRC-16
Figure 26: Power-up Configuration Sequence
4-196
November 25, 1997 (Version 0.6)
~XIUNX
Low. During this time delay, or as long as the PROGRAM
input is asserted, the configuration logic is held in a Configuration Memory Clear state. The configuration-memory
frames are consecutively initialized, using the internal oscillator.
At the end of each complete pass through the frame
addressing, the power-on time-out delay circuitry and the
level of the PROGRAM pin are tested. If neither is asserted,
the logic initiates one additional clearing of the configuration frames and then tests the INIT input.
Initialization
During initialization and configuration, user pins HOC, LDC,
INIT and DONE provide status outputs for the system interface. The outputs LDC, INIT and DONE are held Low and
HOC is held High starting at the initial application of power.
The open drain INIT pin is released after the final initialization pass through the frame addresses. There is a deliberate delay before a Master-mode device recognizes an
inactive INIT. Two internal clocks after the INIT pin is recognized as High, the device samples the MODE pin to determine the configuration mode. The appropriate interface
lines become active and the configuration preamble and
data can be loaded.
Configuration
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply
rise time is excessive or poorly defined. As long as PROGRAM is Low, the FPGA keeps clearing its configuration
memory. When PROGRAM goes High, the configuration
memory is cleared one more time, followed by the beginning of configuration, provided the INIT input is not externally held Low. Note that a Low on the PROGRAM input
automatically forces.a Low on the INIT output. The Spartan
Series PROGRAM pin has a permanent weak pull-up.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration causes the
FPGA to wait after completing the configuration memory
clear operation. When INIT is no longer held Low externally, the device determines its configuration mode by capturing the state of the MODE pin, and is ready to start the
configuration process. A master device waits up to an additional 300 its to make sure that any slaves in the optional
daisy chain have seen that INIT is High.
Configuration Through the Boundary Scan
Pins
Spartan Series devices can be configured through the
boundary scan pins. The basic procedure is as follows:
•
Power up the FPGA with INIT held Low (or drive the
PROGRAM pin Low for more than 300 ns followed by a
High while holding INIT Low). Holding INIT Low allows
enough time to issue theCONFIG command to the
FPGA. The pin can be used as 1/0 after configuration if
a resistor is used to hold INIT Low.
Issue the CONFIG command to the TMS input
Wait for IN IT to go High
Sequence the boundary scan Test Access Port to the
SHIFT-DR state
Toggle TCK to clock data into TDI pin.
The 0010 preamble code indicates that the following 24 bits
represent the length count. The length count is the total
number of configuration clocks needed to load the complete configuration data .. (Four additional configuration
clocks are required to complete the configuration process,
as discussed below.) After the preamble and the length
count have been passed through to any device in the daisy
chain, its DOUT is held High to prevent frame start bits from
reaching any daisy-chained devices.
•
•
•
A specific configuration bit, early in the first frame of a master device, controls the configuration-clock rate and Can
increase it by a factor of eight. Therefore, if a fast configuration clock is selected by the bitstream, the slower clock
rate is used until this configuration bit is detected.
The user must account for all TCK clock cycles after INIT
goes High, as all of these cycles affect the Length Count
compare.
Each frame has a start field followed by the frame'configuration data bits and a frame error field. If a frame data error
is detected, the FPGA halts loading, and signals the error
by pulling the open-drain INIT pin Low. After all configuration frames have been loaded into an FPGA, DOUT again
follows the input data so that the remaining data is passed
on to the next device.
Delaying Configuration After Power-Up
There are· two methods of delaying configuration after
power-up: put a logic Low on the PROGRAM input, or pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See Figure 26 on page 4-196.)
November 25, 1997 (Version 0.6)
•
For more detailed information, refer to the Xilinx application
note, "Boundary Scan in FPGA Devices." This application
note also applies to Spartan and Spartan-XL devices.
Readback
The user can read back the content of configuration memory and the level of certain internal nodes without interfering with the normal operation olthe device.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs and lOBs, as well as the content of function generators used as RAMs.
4-197
I
Spartan and Spartan-XL Families Field Programmable Gate Arrays
IF UNCONNECTED,
~'''''''=, ~
ClK
>-_R",E",A~D_"-,T",RI-=-GG=E,,,R'-------l /~--"TR""IG"l
READBACK
RIP
OBUF
IBUF
Figure 27: Readback Schematic Example
Spartan Series Readback does not use any dedicated pins,
but uses four internal nets (RDBKTRIG, RDBK,DATA,
RDBK,RIP and RDBKCLK) that can be routed to any lOB,
To access the internal Readback signals, place the READBACK library symbol and attach the appropriate pad symbols, as shown in Figure 27,
After Readback has been initiated by a Low-to-High transition on RDBKTRIG, the RDBK,RIP (Read In Progress)
output goes High on the next rising edge of RDBK,CLK,
Subsequent rising edges of this clock shift out Readback
data on the RDBK,DATA net.
Readback data does not include the preamble, but starts
with five dummy bits (all High) followed by the Start bit
(Low) of the first frame, The first two data bits of the first
frame are always High,
Each frame· ends with four error check bits, They are read
back as High, The last seven bits of the last frame are also
read back as High, An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RDBK,RIP returns Low,
Readback Options
Readback options are: Readback Capture, Readback
Abort, and Clock Select. They are set with the. bitstream
generation software,
Readback Capture
When the Readback Capture option is selected, the readback data stream includes sampled values of CLB and lOB
signals, The rising edge of RDBK,TRIG latches the
inverted values of the four CLB outputs, the lOB output flipflops and the input signals 11 and 12, Note that while the
bits describing configuration (interconnect, function generators, and RAM content) are not inverted, the CLB and lOB
output signals are inverted,
When the Readback Capture option is not selected, the values of the capture bits reflect the configuration data originally written to those memory locations,
Readback Abort
When the Readback Abort option is selected, a High-toLow transition on RDBKTRIG terminates the readback
operation and prepares the logic to accept another trigger,
After an aborted readback, additional clocks (up to one
read back clock per configuration frame) may be required to
re-initialize the control logic, The status of read back is indicated by the output control net RDBK,RIP, RDBK,RIP is
High whenever a readback is in progress,
Clock Select
CCLK is the default clock, However, the user can insert
another clock on RDBKCLK, Readback control and data
are clocked on rising edges of RDBKCLK If readback
must be inhibited for security reasons, the readback control
nets are simply not connected,
RDBKCLK is located in the lower right chip corner, as
shown in Figure 28,
Violating the Maximum High and Low Time
Specification for the Readback Clock
The readback clock has a maximum High and Low time
specification, In some cases, this specification cannot be
met. For example, if a processor is controlling readback, an
interrupt may force it to stop in the middle of a read back,
This necessitates stopping the clock, and thus violating the
specification,
The specification is mandatory only on clocking data at the
end of a frame prior to the next start bit. The transfer mechanism will load the data to a shift register during the last six
clock cycles of the frame, prior to the start bit of the following frame, This loading process is dynamic, and is the
source of the maximum High and Low time requirements,
/
PROGRAMMABLE
INTERCONNECT
If the RAM capability of the CLBs is used, RAM data are
available in read back, since they directly overwrite the F
and G function-table configuration of the CLB,
RDBKTRIG is located in the lower-left corner of the device,
as shown in Figure 28,
X1787
Figure 28: READBACK Symbol in Graphical Editor
4-198
November 25, 1997 (Version 0,6)
~XILINX
Therefore, the specification only applies to the six clock
cycles prior to and including any start bit, including the
clocks before the first start bit in the read back data stream.
At other times, the frame data is already in the register and
the register is not dynamic. Thus, it can be shifted out just
like a regular shift register.
The user must precisely calculate the location of the readback data relative to the frame. The system must keep track
of the position within a data frame, and disable interrupts
before frame boundaries. Frame lengths and data formats
are listed in Table 13 and Table 14.
Spartan Program Readback Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-3851 0/605. All devices are
100% functionally tested. Internal timing parameters are
not measured directly. They are derived from benchmark
timing patterns that are taken at device introduction, prior to
any process improvements.
The following guidelines reflect worst-case values over the
recommended operating conditions.
Readback with the XChecker Cable
The XChecker Universal Download/Readback Cable and
Logic Probe uses the read back feature for bitStream verification.1t can also display selected internal signals on the
PC or workstation screen, functioning as a low-cost in-circuit emulator.
Finished
Internal Net
I
/r-----------\\ rl- - - - - - - - - j \ I
---I
rdbkTRIG
rdclk.1
rdbk.RIP
rdbk.DATA
----t'
~~.
X1790
Spartan and Spartan-XL
Description
rdbk.TRIG
rdbk.TRIG setup to initiate and abort Readback
rdbk.TRIG hold to initiate and abort Readback
rdclk.1
rdbk.DATA delay
rdbk.RIP delay
High time
Low time
Note 1:
Note 2:
1
2
7
6
5
4
Symbol
T RTRC
T RCRT
T RCRD
T RCRR
T RCH
T RCL
Min
200
50
Max
-
250
250
500
500
250
250
-
-
Units
ns
ns
ns
ns
ns
ns
Timing parameters apply to all speed grades.
If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.
November 25,1997 (Version 0.6)
4-199
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan Detailed Specification
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:
Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device
families. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. 1
Spartan Absolute Maximum Ratings
Symbol
Description
Value
Supply voltage relative to GND
Vee
-0.5 to +7.0
Input voltage relative to GND (Note 1)
-0.5 to Vee +0.5
TSTG
Voltage applied to 3-state output (Note 1)
Storage temperature (ambient)
-0.5 to Vee +0.5
-65 to +150
TSOL
TJ
Junction temperature
VIN
VTS
Note 1:
Note 2:
Maximum soldering temperature (10 s @ 1/16 in.
= 1.5 mm)
+260
+125
IPlastic packages
Units
V
V
V
°C
°C
°C
Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is
easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this
over- or undershoot lasts less than 20 ns.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
Spartan Recommended Operating Conditions
Symbol
Min
Description
Max
5.25
5.5
Vee
Supply voltage relative to GND, T J = -0 °C to +85°C
Commercial
4.75
V IH
Supply voltage relative to GND, TJ = -40°C to + 100°C
High-level input voltage
Industrial
TTL inputs
4.5
2.0
CMOS inputs
70%
Vee
100%
TTL inputs
0
0.8
CMOS inputs
0
20%
V IL
Low-level input voltage
TIN
Input signal transition time
Note:
250
Units
V
V
V
Vee
V
Vee
ns
At junction temperatures above tho$e listed as Recommended Operating Conditions, all delay parameters increase by
0.35% per °C.
Input and output Measurement thresholds are: 1.5V for TTL and 2.5V for CMOS.
1. Notwithstanding the definition of the above terms, all specifications are subject to change without notice.
4-200
November 25, 1997 (Version 0.6)
~XILINX
Spartan DC Characteristics Over Operating Conditions
Symbol
Description
Min
TTL outputs
VOL
= -4.0mA, Vee min
High-level output voltage @ IOH = -1.0mA, Vee min
Low-level output voltage @ IOL = 12.0mA, Vee min
(Note 1)
leeo
Quiescent FPGA supply current (Note 2)
CMOS outputs
Commercial
IL
C IN
Input or output leakage current
Input capacitance (sample tested)
IRPU
Pad pull-up (when selected) @ VIN = OV (sample tested)
Pad pull-down (when selected) @ V IN = 5V (sample tested)
VOH
High-level output voltage @ IOH
CMOS outputs
TTL outputs
Note 1:
Note 2:
Units
V
Vee-0.5
0.4
V
V
0.4
V
3.0
6.0
mA
mA
-10
+10
10
MA
pF
-0.02
-0.25
mA
Industrial
IRPD
Max
2.4
PC, VQ, TQ, PQ,
SG packages
0.02
mA
With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins.
With no output current loads, no active input pull-up resistors, all package pins at Vcc or GND, and the FPGA configured with
the Tie option.
November 25, 1997 (Version 0.6)
4-201
I
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan Guaranteed Input and Output Parameters (Pin-to-Pin, TTL 1/0)
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all Spartan devices unless otherwise noted.
uescrll·lUUII
Global Clock to Output
(fast) using OFF
~
Global Clock-to-Output Delay
Speed Grade
Symbol
Device
XCS05
TICKOF
XCS10
XCS20
XCS30
(Max)
XCS40
-3
-4
Units
8.7
9.1
9.3
9.4
10.2
6.0
6.4
7.0
7.4
7.6
ns
ns
ns
ns
XCS05
XCS10
XCS20
XCS30
XCS40
11.5
12.0
12.2
12.8
12.8
8.0
8.4
9.0
9.4
9.6
ns
ns
ns
ns
XCS05
XCS10
XCS20
XCS30
XCS40
2.3
1.2
0.2
0
0
1.7
1.0
0
0
0
ns
ns
ns
ns
XCS05
XCS10
XCS20
XCS30
XCS40
4.0
4.5
5.5
5.5
5.7
1.7
2.2
2.7
3.2
3.7
ns
ns
ns
ns
XCS05
XCS10
XCS20
XCS30
XCS40
6.0
6.0
6.0
6.0
6.8
5.2
5.2
5.2
5.2
5.2
ns
ns
ns
ns
XCS05
XCS10
XCS20
XCS30
XCS40
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
:
X3202
Global Clock to Output
(slew-limited) using OFF
T1CKO
~
Global Clock-Io-Output Delay
(Max)
:
X3202
Input Setup Time, using IFF
(no delay)
Input
Set.UE
Hold
Time
1
:,~
[
(Min)
T'FF
PG
Input Hold Time, using IFF
(no delay)
Input
Set.UE
Hold
Time
1
TpSUF
T pHF
:,~
(Min)
T'FF
PG
X8~1
Input Setup Time, using IFF
(with delay)
Input
set.uE
Hold
Time
1
~
Input
Hold
Time
(Min)
T'FF
PG
Input Hold Time, using IFF
(with delay)
Set- UE
TpSU
~
1
T
PG
T pH
(Min)
IFF
xn01
OFF = Output Flip-Flop
4-202
IFF = Input Flip-Flop/Latch
~
November 25, 1997 (Version 0.6)
~XILINX
Spartan-XL Detailed Specification
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:
Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device
families. Values are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.
All specifications subject to change without notice.
Spartan-XL Absolute Maximum Ratings
Symbol
Value
Units
Vee
V IN
Supply voltage relative to GND
Description
-0.5 to 4.0
V
Input voltage relative to GND (Note 1)
-0.5 to 5.5
V
VTS
Veet
Voltage applied to 3-state output (Note 1)
-0.5 to 5.5
V
50
ms
-65 to +150
°C
+260
°C
+125
°C
Longest Supply Voltage Rise Time from 1V to 3V
TSTG
Storage temperature (ambient)
TSOL
TJ
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
Notes:
I Plastic packages
Junction temperature
1. Maximum DC undershoot below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During
transitions, the device pins may undershoot to -2.0 V or overshoot to + 7.0 V, provided this over- or undershoot lasts less
than IOns and with the forcing current being limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
Spartan-XL Recommended Operating Conditions
Symbol
Min
Max
Units
Supply voltage relative to GND, TJ = DoC to +85°C
Commercial
3.0
3.6
V
Vee
Supply voltage relative to GND, TJ = -40°C to
+100°C
Industrial
3.0
3.6
V
V IH
High-level input voltage
50% of Vee
5.5
V
V IL
Low-level input voltage
0
30% of Vee
V
TIN
Input signal transition time
250
ns
Notes:
Description
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
Input and output measurement threshold is -40% of Vcc.
November 25, 1997 (Version 0.6)
4-203
I
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL DC Characteristics Over Recommended Operating Conditions
Symbol
V OH
VOL
Description
High-level output voltage @ IOH = -4.0 mA, Vee min (L VTTL)
High-level output voltage @ IOH = -500 ~A, (L VCMOS)
Min
2.4
V
V
Low-level output voltage @ IOL = 12.0 mA, Vee min (L VTTL) (Note 1)
Data Retention Supply Voltage (below which configuration data may be lost)
leeo
Quiescent FPGA supply current (Note 2)
IL
I PC, VQ, TQ, PQ, BG packages
CIN
Input capacitance (sample tested)
IRPU
Pad pull-up (when selected) @ Vin = OV (sample tested)
0.02
IRPD
Pad pull-down (when selected) @ V in = 3.3V (sample tested)
0.02
Note 1:
Note 2:
4-204
0.4
V
10% Vee
V
5
mA
+10
~A
10
pF
0.25
mA
2.5
-10
Input or output leakage current
Units
90% Vee
Low-level output voltage @ IOL = 1500 ~A, (LVCMOS)
V DR
Max
V
mA
With up to 64 pins simultaneously sinking 12 rnA.
With no output current loads, no active input pull-up resistors, all package pins at Vcc or GND, and the FPGA configured with
the Tie option.
November 25, 1997 (Version 0.6)
~XILINX
Spartan-XL Guaranteed Input and Output Parameters (Pin-to-Pin)
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all Spartan-XL devices unless otherwise noted.
-3
-4
Units
8.7
9.1
9.3
9.4
6.0
6.4
7.0
7.4
7.6
ns
ns
ns
ns
ns
11.5
12.0
12.2
12.8
12.8
8.0
ns
ns
ns
ns
ns
2.3
1.2
'0.2
1,7
4.5
5.5
5.5
2.2
3.2
5.7
3.7
ns
ns
ns
ns
ns
(Min)
XCS10XL
XCS20XL
XCS30XL
XCS40XL
6.0
6.0
6.0
6.0
6.8
5.2
5.2
5.2
5.2
5.2
ns
ns
ns
ns
ns
(Min)
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
o
o
o
o
o
o
o
o
o
o
ns
ns
ns
ns
ns
Global Clock to Output
(fast) using OFF
~
Global Clock-to-Outpul Delay
10.2
•
""'"
Global Clock to Output
(slew-limited) using OFF
, ICKO
~
.
Global Clock-tQ-OIilput Delay
Input Setup i
(no delay)
(Max)
XCS10XL
XCS20XL
XCS30XL
XCS40XL
8.4
9.0
9.4
9.6
•
TpSUF
using IFF
S"I~~g),=4J'
IFF
(Min)
XC$05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
o
o
1.0
o
o
o
ns
ns
ns
ns
ns
D
Hold
PG
-,
Time
1.7
Input Hold Time, using IFF
(no delay)
Setln~KI ~T
IFF
(Min)
2.7
D
Hold
PG
Time
X3201
Input Setup Time, using IFF
(with delay)
In ut ,
~.~)
Hold
Time
PSU
==D
.
"r
.. PG
OFF = Output Flip-Flop
.
~,',
-,
IFF = Input Flip-Flop/Latch
November 25, 1997 (Version 0.6)
I
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Pin Descriptions
There are three types of pins in the Spartan Series devices:
• Permanently dedicated pins
• User 1/0 pins that can have special functions
• Unrestricted user~programmable 1/0 pins.
Before and during configuration, all outputs not used for the
configuration process are 3-stated with the 1/0 pull-up
resistor nelwork activated. After configuration, . if an lOB is
unused it is configured as an input with the I/O pull-up
resistor network remaining activated.
Spartan Series devices have no dedicated Reset input. Any
user 1/0 can be configured to drive the Global SeVReset
net, GSA.
See "Global Signals: GSR and GTS" on
page 4-189 for more information on GSA.
Spartan Series devices have no dedicated 3-state pin, they
use the global 3-state net, GTS, instead. This net 3-states
all outputs. See "Global Signals: GSR and GTS'!on
page 4-189 for more information on GTS.
Device pins for Spartan Series devices are described in
Table 15.
Table 15: Pin Descriptions
I/O
I/O
During After
Pin Name
Config. Config.
Permanently Dedicated Pins
Pin Description
l~i9ht or
more (depending on package) connections to the nominal +5 V supply voltage
(+3.3 V for low-voltage devices). All must be connected, and each must be decoupled
with a 0.01 - 0.1 j.lF capacitor to Ground.
Eight or more (depending on package type) connections to Ground. All must be conGND
X
X
nected.
During configuration, Configuration Clock (CCLK) is an output in Master mode and is an
input in Slave mode. After configuration, CCLK has a weak pull-up resistor and can be
selected as the Readback Clock. There is no CCLK High or Low time restriction on
CCLK
10rO
I
Spartan Series devices, except during Readback. See "Violating the Maximum High
and Low Time Specification for the Readback Clock" on page 4-198 for an explanation
of this exception .
.DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it
indicates the completion of the configuration process. As an input, a Low level on DONE
can be configured to delay the global logic initialization and the enabling of outputs.
DONE
1/0
0
The optional pull-up resistor is selected as an option in the program that creates the
configuration bitstream. The resistor is included by default.
PROGRAM is an active Low input that forces the FPGA to clear its configuration memory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA
finishes the current clear cycle and executes another complete clear cycle, before it
PROGRAM
I
I
goes into a WAIT state and releases TNii.
The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled
up to Vcc.
The Mode input is sampled after TNii goes High to determine the configuration mode to
be used.
MODE
I
I
During configuration, this pin has a weak pull-up resistor. For the most popular configuration mode, Slave Serial, the mode pin can be left unconnected. A pull-down resistor
value of 4.7 kn is recommended for Master Serial mode.
Pins reserved for factory testing and possible future enhancements. Pins must be left
Don't Connect
X
X
floating.
.,
User I/O Pins That Can Have Special Functions
If boundary scan is used, thispin.is the Test Data Output. If boundary scan is not used,
this pin is a 3-state output without a register, after configuration is completed.
This pin can be user output only when called out by special schematic definitions. To
0
0
TOO
use this pin, place the library component TOO instead of the usual pad symbol. An output buffer must still be used.
VCC
4-206
X
X
November 25, 1997 (Version 0.6)
~XILINX
Table 15: Pin Descriptions (Continued)
1/0
Pin Name
1/0
During
After
Config. Config.
Pin Description
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select
inputs respectively. They come directly from the pads, bypassing the lOBs. These pins
can also be used as inputs to the CLB logic after configuration is completed.
I/O
If the BSCAN symbol is not placed in the design, all boundary scan functions are inhiborl
ited once configuration is completed, and these pins become user-programmable I/O.
(JTAG)
In this case, they must be called out by special library elements. To use these pins,
place the library components TDI, TCK, and TMS instead of the usual pad symbols. Input or output buffers must still be used.
TDI, TCK,
TMS
I
HOC
0
110
High During Configuration (HOC) is driven High until the I/O go active. It is available as
a control output indicating that configuration is not yet completed. After configuration,
HOC is a user-programmable I/O pin.
LDC
0
I/O
Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a
control output indicating that configuration is not yet completed. After configuration,
LDC is a user-programmable I/O pin.
I/O
Before and during configuration, INIT is a bidirectional signal. A 1 kQ - 10 kQ external
pull-up resistor is recommended.
As an active-Low open-drain output, INIT is held Low during the power stabilization and
internal clearing of the configuration memory. As an active-Low input, it can be used
to hold the FPGA in the internal WAIT state before the start of configuration. Master
mode devices stay in a WAIT state an additional 30 to 300 ~s after INIT has gone High.
During configuration, a Low on this output indicates that a configuration data error has
occurred. After the I/O go active, INIT is a user-programmable I/O pin.
INIT
PGCK1PGCK4
I/O
Weak
Pull-up
SGCK1SGCK4
Weak
Pull-up
DIN
I
DOUT
0
Four Primary Global inputs each drive a dedicated internal global net with short delay
and minimal skew. If not used to drive a global buffer, any of these pins is a user-programmable I/O.
lor I/O
The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol
connected directly to the input of a BUFGP symbol is automatically placed on one of
these pins.
Four Secondary Global inputs each drive a dedicated internal global net with short delay
and minimal skew. These internal global nets can also be driven from internal logic. If
not used to drive a global net, any of these pins is a user-programmable I/O pin.
lor I/O
The SGCK1-SGCK4 pins providethe shortest path to the four Secondary Global Buffers. Any input pad symbol connected directly to the input of a BUFGS symbol is automatically placed on one of these pins.
During Slave Serial or Master Serial configuration, DIN is the serial configuration data
I/O
input receiving data on the rising edge of CCLK. After configuration, DIN is a user-programmable I/O pin.
I/O
During configuration, DOUT is the serial configuration data output that can drive the DIN
of daisy-chained slave FPGAs. DOUT data changes on the falling edge of CCLK, oneand-a-half CCLK periods after it was received at the DIN input.
After configuration, DOUT is a user-programmable I/O pin.
Unrestricted User-Programmable VO Pins
I/O
Weak
Pull-up
I/O
November 25, 1997 (Version 0.6)
These pins can be configured to be input and/or output after configuration is completed.
Before configuration is completed, these pins have an internal high-value pull-up resistor network that defines the logic level as High.
4-207
I
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Device-Specific Pinout Tables
Device-specific tables include all packages for each Spartan and Spartan-XL device. They follow the pad locations around
the die. and include boundary scan register locations.
Pin Locations for XCS05 & XCS05XL Devices
XCS05 & XCS05XL
Pad Name
XCS05 & XCS05XL
Pad Name
Bndry Scan
PC84
VQ100
GND
P43
P38
32
I/O
P44
P39
157
35
I/O
P45
P40
160
P92
38
I/O
P41
163
P93
41
I/O
P42
166
169
PC84
VQ100
VCC
P2
P89
I/O
P3
P90
I/O
P4
P91
I/O
I/O
Bndry Scan
I/O
P5
P94
44
110
P46
P43
I/O
P6
P95
47
I/O
P47
P44
172
I/O
P7
P96
50
I/O
P48
P45
175
I/O
P8
P97
53
I/O
P49
P46
178
I/O
P9
P98
56
I/O
P50
P47
181
I/O, SGCKl
Pl0
P99
59
110, SGCK3
P51
P48
184
VCC
Pll
Pl00
GND
P12
Pl
GND
P52
P49
DONE
P53
P50
I/O, PGCKl
P13
P2
62
VCC
P54
P51
I/O
P14
P3
65
PROGRAM
P55
P52
I/O, TOI
P15
P4
68
P53
P16
P5
71
P57
P54
190
110, TMS
110
P17
P6
74
110
110, PGCK3
110
P56
I/O, TCK
P58
P55
193
P18
I/O
187
P7
77
I/O
P56
196
P8
83
I/O
P59
P57
199
P60
I/O
P19
P9
86
I/O
P58
202
I/O
P20
Pl0
89
I/O
P59
205
GND
P21
Pll
P60
208
VCC
P22
P12
110
110
P61
P61
211
I/O
P23
P13
92
I/O
P62
P62
214
I/O
P24
P14
95
VCC
P63
P63
P15
98
GND
P64
P64
I/O
P25
P16
104
I/O
P65
P65
217
110
P26
P17
107
I/O
P66
P66
220
I/O
P27
P18
110
I/O
P67
223
P19
113
I/O
P67
P68
229
I/O
I/O
I/O
P28
P20
116
I/O
P68
P69
232
I/O, SGCK2
P29
P21
119
I/O
P69
P70
235
122
110
P70
P71
238
I/O (DIN)
P71
P72
241
125
I/O, SGCK4 (DOUT)
P72
P73
244
P74
Don't Connect
P30
P22
GND
P31
P23
MODE
P32
P24
VCC
P33
P25
CCLK
P73
Don't Connect
P34
P26
126
VCC
P74
P75
I/O, PGCK2
P35
P27
127
0, TOO
P75
P76
I/O (HDC)
P36
P28
130
GND
P76
P77
P29
133
I/O
P77
P78
2
I/O (LDC)
P37
P30
136
I/O, PGCK4
P78
P79
5
I/O
P38
P31
139
I/O
P79
P80
8
I/O
P39
P32
142
I/O
P80
P81
11
I/O
P33
145
110
P81
P82
14
I/O
P34
148
I/O
P82
P83
17
P35
151
I/O
P84
20
154
P85
23
P86
26
I/O
I/O
P40
I/O (INIT)
P41
P36
VCC
P42
P37
4-208
I/O
I/O
P83
0
November 25. 1997 (Version 0.6)
~XILINX
XCS05 & XCS05XL
Pad Name
PC84
VQ100
Bndry Scan
1/0
P84
P87
29
GND
Pl
P88
9/24/97
Pin Locations for XCS1 0 & XCS10XL Devices
XCS1D & XCS1DXL
Pad Name
VQ1DD
PC84
TQl44
Bndry
Scan
XCS1D & XCS1DXL
Pad Name
PC84
VQ1DD
TQl44
Bndry
Scan
P20
P32
164
VCC
P2
P89
P128
1/0
P28
1/0
P3
P90
P129
44
1/0, SGCK2
P29
P21
P33
167
1/0
P4
P91
P130
47
Don't Connect
P30
P22
P34
170
P35
---
-
1/0
P92
P131
50
GND
P31
P23
1/0
P93
P132
53
MODE
P32
P24
P36
1/0
P5
P94
P133
56
VCC
P33
P25
P37
1/0
P6
P95
173
P134
59
Don't Connect
P34
P26
P38
174
1/0
P135
62
P35
P27
P39
175
1/0
P136
65
110, PGCK2
110 (HDC)
P36
P28
P40
178
GND
P137
1/0
P7
P97
P138
68
P41
181
110
P42
184
P29
P43
187
P30
P44
190
1/0
P139
71
1/0
P140
74
1/0 (LDC)
1/0
P141
77
GND
P45
1/0
P8
P96
1/0
P37
1/0
P9
P98
P142
80
1/0
P46
193
110, SGCKl
Pl0
P99
P143
83
1/0
P47
196
VCC
Pll
Pl00
P144
1/0
P38
P31
P48
199
GND
P12
Pl
Pl
1/0
P39
P32
P49
202
1/0, PGCKl
P13
P2
P2
86
1/0
P33
P50
205
1/0
P14
P3
P3
89
1/0
P34
P51
208
1/0
P4
92
1/0
P40
P35
P52
211
1/0
P5
95
1/0 (INIT)
P41
P36
P53
214
1/0, TOI
P15
P4
P6
98
VCC
P42
P37
P54
110, TCK
P16
P5
P7
101
GND
P43
P38
P55
1/0
P44
P39
P56
P45
P40
P57
220
P41
P58
223
GND
P8
1/0
P9
104
1/0
Pl0
107
217
I/O,TMS
P17
P6
Pll
110
110
110
110
P42
P59
226
1/0
P18
P7
P12
113
1/0
P46
P43
P60
229
P13
116
1/0
P47
P44
P61
232
P8
P14
119
1/0
P62
235
238
1/0
1/0
1/0
P19
P9
P15
122
1/0
P63
110
P20
Pl0
P16
125
GND
P64
GND
P21
Pll
P17
VCC
P22
P12
P18
P48
P45
P65
241
P49
P46
P66
244
I/O
P23
P13
P19
128
110
110
110
1/0
P24
P14
P20
131
1/0
P15
P21
134
1/0
P50
P22
137
1/0, SGCK3
P51
P23
140
GND
P52
P49
P71
1/0
1/0
1/0
P25
P16
1/0
P26
P17
P67
247
P68
250
P47
P69
253
P48
P70
256
P24
143
DONE
P53
P50
P72
1/0
P25
146
VCC
P54
P51
P73
1/0
P26
149
PROGRAM
P55
P52
P74
GND
P27
1/0
P56
P53
P75
259
P57
P54
P76
262
P18
P28
152
1/0, PGCK3
P19
P29
155
1/0
P77
265
1/0
P30
158
1/0
P78
268
1/0
P31
161
1/0
P79
271
110
110
P27
NDvember 25, 1997 (VersiDn 0,6)
P58
P55
4-209
I
Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS10 & XCS10XL
Pad Name
-~--
PC84
I/O
VQ100
TQ144
PS6
P80
XCS10 & XCS10XL
Bndry
Pad Name
Scan
PC84
VQ100
TQl44
P74
P107
P108
274
CCLK
P73
GND
P81
VCC
P74
P75
1/0
P82
277
O,TDO
P75
P76
P109
I/O
P83
280
GND
P76
P77
P110
Bndry
Scan
0
1/0
PS9
P57
P84
283
1/0
P77
P78
P111
2
1/0
P60
P58
P8S
286
1/0, PGCK4
P78
P79
P112
5
1/0
PS9
P86
289
1/0
P113
8
1/0
P60
P87
292
I/O
P114
11
1/0
P61
P61
P88
295
1/0
P79
P80
P115
14
1/0
P62
P62
P89
298
I/O
P80
P81
P116
17
VCC
P63
P63
P90
GND
P118
GND
P64
P64
P91
I/O
P119
I/O
P6S
P6S
P92
301
I/O
P120
23
1/0
P66
P66
P93
304
1/0
P81
P82
P121
26
P67
P94
307
1/0
P82
P83
P122
29
P9S
310
1/0
P84
P123
32
1/0
1/0
20
I/O
P67
P68
P96
313
1/0
P85
P124
35
1/0
P68
P69
P97
316
1/0
P83
P86
P125
38
I/O
P98
319
I/O
P84
P87
P126
41
1/0
P99
322
GND
P1
P88
P127
P100
GND
9/24197
1/0
P69
P70
Pl01
325
1/0
P70
P71
P102
328
1/0
P103
331
Additional XCS10IXL Package Pins
1/0
P104
334
TQ144
1/0 (DIN)
P71
P72
P105
337
1/0, SGCK4
(DOUT)
P72
P73
P106
340
I
Not Connected Pins
I
P117
I
5/5197
Pin Locations for XCS20 & XCS20XL Devices
XCS20 & XCS20XL
Pad Name
VQ1DO
TQ144
PQ208
Bndry
XCS20 & XCS20XL
Pad Name
Scan
VQ100
Bndry
TQ144
PQ208
P141
P205
113
Scan
VCC
P89
P128
P183
1/0
P90
P129
P184
62
1/0
P98
P142
P206
116
1/0
P91
P130
P185
65
1/0, SGCK1
P99
P143
P207
119
1/0
P92
P131
P186
68
VCC
P100
P144
P208
1/0
P93
P132
1/0
P187
71
GND
P1
P1
Pl
1/0
P188
74
1/0, PGCK1
P2
P2
P2
122
1/0
P189
77
1/0
P3
P3
P3
125
128
1/0
P94
P133
P190
80
1/0
P4
P4
1/0
P95
P134
P191
83
1/0
P5
P5
131
P6
134
P192
VCC
1/0, TDI
P4
P6
P5
P7
1/0
P135
P193
86
I/O, TCK
P7
137
1/0
P136
P194
89
1/0
P8
140
GND
P137
P195
I/O
Pl0
143
1/0
P196
92
I/O
Pl1
143
1/0
P197
95
1/0
Pll
146
1/0
P198
98
1/0
P12
149
1/0
P199
101
GND
P8
P13
1/0
P96
P138
P200
104
1/0
P9
P14
152
1/0
P97
P139
P201
107
I/O
P10
P15
155
1/0
P202
110
I/O, TMS
P6
Pl1
P16
158
I/O
P203
113
1/0
P7
P12
P17
161
P204
110
VCC
1/0
4-210
P140
P18
November 25, 1997 (Version 0.6)
~XILINX
XCS20 & XCS20XL
Bndry
XCS20 & XCS20XL
1/0
Scan
164
Pad Name
P19
1/0
P20
167
Pad Name
VQ100
TQ144
PQ208
Bndry
Scan
VQ100
TQ144
PQ208
1/0
P34
P51
P75
298
1/0
P35
P52
P76
301
304
P13
P21
170
1/0 (INIT)
P36
P53
P77
P8
P14
P22
173
VCC
P37
P54
P78
1/0
P9
P15
P23
176
GND
P38
P5S
P79
1/0
PtO
P16
P24
179
1/0
P39
PS6
P80
GND
Ptt
P17
P25
1/0
P40
P57
P81
310
VCC
Pt2
P18
P26
110
P4t
PS8
P82
313
P42
P59
P83
316
1/0
1/0
307
1/0
Pt3
P19
P27
182
110
110
Pt4
P20
P28
185
1/0
P84
1/0
Pt5
P21
P29
188
1/0
P85
P22
P30
191
VCC
P86
1/0
P31
194
1/0
P43
P60
P87
325
1/0
P32
197
1/0
P44
P61
P88
328
VCC
P33
1/0
P62
P89
331
334
1/0
319
------
322
1/0
Pt6
P23
P34
200
1/0
P63
P90
1/0
Pt?
P24
P35
203
GND
P64
P91
1/0
P25
P36
206
1/0
P92
337
1/0
P26
P3?
209
1/0
P93
340
GND
P27
P38
110
P94
343
1/0
P39
212
110
P9S
343
1/0
P40
215
1/0
P96
346
1/0
P41
218
1/0
P45
P6S
P97
349
1/0
P42
221
1/0
P46
P66
P98
352
1/0
P43
221
110
P67
P99
355
P68
P100
358
1/0
Pt8
P28
P44
224
1/0
1/0
Pt9
P29
P45
227
1/0
P4?
P69
P101
361
1/0
P30
P46
230
1/0, SGCK3
P48
P70
P102
364
1/0
P31
P47
233
GND
P49
P71
P103
1/0
P20
P32
P48
236
DONE
P50
P72
P104
1/0, SGCK2
P2t
P33
P49
239
VCC
P5t
P73
P105
Don't Connect
P22
P34
P50
242
PROGRAM
P52
P74
P106
GND
P23
P35
P51
1/0
P53
P75
P107
367
MODE
P24
P36
P52
1/0, PGCK3
P54
P76
P108
370
VCC
P25
P37
P53
1/0
P77
P109
373
Don't Connect
P26
P38
P54
246
1/0
P78
P110
376
1/0, PGCK2
P27
P39
P55
247
1/0
110 (HDC)
P28
P40
P56
250
1/0
P55
P79
P112
379
1/0
P41
P57
253
1/0
P56
P80
P113
382
1/0
P42
P58
256
110
P114
385
245
P111
1/0
P29
P43
P59
259
110
P115
388
1/0 (LDC)
P30
P44
P60
262
1/0
P116
391
P117
394
1/0
P61
265
1/0
1/0
P62
265
GND
P81
P118
110
P63
268
1/0
P82
P119
397
1/0
P64
271
1/0
P83
P120
400
1/0
P65
274
VCC
P121
GND
P45
P66
1/0
P57
P84
P122
403
1/0
P46
P67
277
1/0
P58
P85
P123
406
1/0
P47
P68
280
1/0
P124
409
1/0
Pt25
4~
415
1/0
P3t
P48
P69
283
1/0
P32
P49
P70
286
110
P59
P86
P126
1/0
P60
P87
P127
418
1/0
P6t
P88
P128
421
292
110
P62
P89
P129
424
295
VCC
P63
P90
P130
VCC
P71
1/0
P72
289
P73
P74
1/0
1/0
P33
P50
November 25, 1997 (Version 0.6)
4-211
I
Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20 & XCS20XL
-----VQ100
TQ144
PQ208
Bndry
O,TDO
P76
Pl09
P157
0
427
GND
P77
Pll0
P158
P133
430
1/0
P78
Plll
P159
2
P134
433
1/0, PGCK4
P79
Pl12
P160
5
VQ100
TQ144
PQ208
GND
P64
P91
P131
1/0
P65
P92
P132
1/0
P66
P93
1/0
P67
P94
Pad Name
Bndry
XCS20 & XCS20XL
Scan
Pad Name
Scan
P135
436
1/0
Pl13
P161
8
1/0
P136
439
110
Pl14
P162
11
1/0
P137
442
1/0
P80
Pl15
P163
14
P81
Pl16
P164
17
P165
20
P95
1/0
1/0
P68
P96
P138
445
110
1/0
P69
P97
P139
448
1/0
P166
20
1/0
P98
P141
451
1/0
P167
23
1/0
P99
P142
454
1/0
P168
26
GND
Pl00
P143
1/0
P169
29
P140
VCC
P117
1/0
1/0
P144
457
GND
P118
P170
1/0
P145
460
1/0
Pl19
P171
32
1/0
P146
463
1/0
P120
P172
35
1/0
P147
463
VCC
P173
P148
466
1/0
P82
P121
P174
38
1/0
P70
Pl0l
P149
469
1/0
P83
P122
P175
41
1/0
P71
Pl02
P150
472
110
P176
44
1/0
Pl03
P151
475
1/0
P177
47
1/0
P104
P152
478
1/0
P84
P123
P178
50
1/0
1/0 (DIN)
P72
Pl05
P153
481
1/0
P85
P124
P179
53
110, SGCK4
P73
Pl06
P154
484
1/0
P86
P125
P180
56
110
P87
P126
P181
59
GND
P88
P127
P182
(DOUT)
CCLK
P74
P107
P155
VCC
P75
Pl08
P156
10/22197
Pin Locations for XCS30 & XCS30XL Devices
XCS30 & XCS30XL
XCS30 & XCS30XL
PQ240
BG256
1/0
P140
P204
P236
83
134
74
1/0
P141
P205
P237
82
137
010
77
1/0
P98
P142
P206
P238
A2
140
P215
A9
80
1/0, SGCKl
P99
P143
P207
P239
C3
143
P187
P216
89
83
VCC
Pl00
P144
P208
P240
VCC'
P188
P217
C9
86
GND
Pl
Pl
Pl
Pl
GNO'
P189
P218
09
89
1/0, PGCKl
P2
P2
P2
P2
81
P3
P3
P3
P3
C2
149
P4
P4
P4
02
152
PQ208
PQ240
BG256
VCC
P89
P128
P183
P212
VCe-
1/0
P90
P129
P184
P213
Cl0
1/0
P91
P130
P185
P214
1/0
P92
P131
P186
1/0
P93
P132
Pad Name
---
1/0
1/0
P94
P133
P190
P220
A8
92
1/0
1/0
P95
P134
P191
P221
88
95
1/0
P192
VQ100
Bndry
PQ208
TQl44
1/0
Bndry
Scan
TQ144
VQ100
Pad Name
Scan
146
P222
VCC'
P5
P5
P5
03
155
110
P223
A6
98
1/0, TDI
P4
P6
P6
P6
E4
158
1/0
P224
C7
101
1/0, TCK
P5
P7
P7
P7
Cl
161
86
104
P8
P8
01
164
107
110
110
110
P9
P9
E3
167
Pl0
Pl0
E2
170
VCC
110
1/0
P135
P193
P225
1/0
P136
P194
P226
A5
GND
P137
P195
P227
GNO'
1/0
P196
P228
C6
110
1/0
Pll
Pll
El
173
1/0
P197
P229
85
113
110
P12
P12
F3
176
1/0
P198
P230
A4
116
1/0
P13
F2
179
1/0
P199
P231
C5
119
GND
P8
P13
P14
GNO'
1/0
P96
P138
P200
P232
84
122
110
P9
P14
P15
G3
110
P97
P139
P201
P233
A3
125
1/0
Pl0
P15
P16
G2
185
1/0
P202
P234
05
128
1/0, TMS
P6
Pl1
P16
P17
Gl
188
1/0
P203
P235
C4
131
110
P7
P12
P17
P18
H3
191
4-212
182
November 25, 1997 (Version 0.6)
~XILINX
XCS30 & XCS3DXL
TQI44
PQ2DB
PQ24D
BG256
P47
P68
P77
V7
Bndry
Scan
334
P31
P48
P69
P78
V8
337
P32
P49
P70
P79
W8
340
VCC
P71
P80
vee'
XCS3D & XCS30XL
PQ24D
BG256
PI8
PI9
vee'
1/0
P20
H2
194
1/0
1/0
P21
HI
197
1/0
PI9
P23
J2
200
VQIDD
TQI44
Bndry
Scan
PQ208
Pad Name
VCC
1/0
VQIDD
1/0
P20
P24
JI
203
1/0
P72
P81
VB
343
PI3
P21
P25
K2
206
1/0
P73
P82
U9
346
349
1/0
1/0
Pad Name
1/0
P8
PI4
P22
P26
K3
209
1/0
P84
V9
1/0
P9
PI5
P23
P27
KI
212
1/0
P85
WIO
352
1/0
Pl0
PI6
P24
P28
L1
215
1/0
P33
GND
Pll
PI7
P25
P29
GND'
1/0
VCC
P12
PI8
P26
P30
vee'
1/0
1/0
P13
PI9
P27
P31
L2
218
1/0
P14
P20
P28
P32
L3
1/0
PIS
P21
P29
P33
P22
P30
P34
1/0
P31
P35
1/0
P32
P50
P74
P8S
VIO
355
P34
PSI
P7S
P87
VIO
358
P35
P52
P76
PBS
VII
361
1/0(lI'JIT)
P36
P53
P77
P89
WII
364
221
vec
P37
P54
P78
P90
vee'
L4
224
GND
P38
P55
P79
P91
GND'
MI
227
1/0
P39
P56
PSO
P92
VII
367
M2
230
1/0
P40
P57
P81
P93
UII
370
P36
M3
233
1/0
P41
P58
P82
P94
VI2
373
1/0
P38
Nl
236
1/0
P42
PS9
P83
P95
WI2
376
1/0
P39
N2
239
1/0
P84
P9S
VI2
379
1/0
P85
P97
UI2
,382
P99
VI3
385
-
PIOO
VI4
388
P86
PIOI
vee'
1/0
P33
P40
vee'
1/0
P16
P23
P34
P4I
PI
242
1/0
1/0
P17
P24
P35
P42
P2
245
1/0
1/0
P25
P36
P43
Rl
248
VCC
1/0
P26
P37
P44
P3
251
1/0
P43
P60
P87
PI02
VI5
391
GND
P27
P38
P45
GND'
1/0
P44
P61
PB8
PI03
VI4
394
P46
TI
254
1/0
" P62
P89
1'104
WI5
397
1/0
P39
P47
R3
257
1/0
P63
1'90
PI05
VI6
40p
1/0
P40
P48
T2
260
GND
1'64
P91
PI06
GND'
-,
1/0
P41
P49
Ul
?63
1/0
1'107
VI5
403
1/0
P42
P50
T3
266
1/0
-
Ploa
WI6
406
1/0
1"43
P51
U2
269
1/0
P93
1'109
VI7
409
VCC
1/0
1/0
P18
P28
,P44
P52
VI
272
1/0
P94
PlIO
VI6
412
1/0
P19
1"29
P45
P53
T4
275
1/0
P95
PIlI
WI7
415
1/0
P30
P46
P54
U3
278
1/0
P96
PI12
VI8
418
1/0
P31
P47
P55
V2
281
1/0
1'45
' P65
P97
1'113
UI6
421
P46
P66
P98
PI14
VI7
424
1/0
P20
P32
1'48
P56
WI
284
1/0
1/0,SGCK2
P21
P33
P49
P57
V3
287
1/0
P67
1'99
PllS
WI8
427
Don't Connect
P22
P34
P50
P58
W2
290
1/0
1'68
PIOO
PI16
VI9
430
GND
P23
P35
P51
P59
GND'
1/0
1'47
1'69
PIOI
PI17
VIS
433
MODE
P24
P36
P52
P60
VI
293
1/0,SGCK3
P48
P70
PI02
PIIS
WI9
436
VCe;
P25
P37
PS3
P61
vee'
GND
P49
P71
PI03
P119
GND'
Donl,Connect
P26
1'38
1'54
P62
Y"3
294
DONE
P50
P72
PI04
P120
V2(}
1/0,PGCK2
P27
P39
P55
P63
V2
295
VCC
1"51
P73
PI05
P121
vee'
1/0 (HDC)
P28
1'40
P56
P64
W4
298
PROGRAM'
P52
P74
PI06
PI22
V19
1/0
P41
1'57
1'65
V4
301
1/0
P53
P75
1'107
PI23
UI9
439
1/0
P42
P58
P66
U5
304
1/0, paCK3
P54
P76
PI08
1'124
UI8
442·
1/0 "
P29
P43
P59
P67
V3
307
1/0
1'77
Pl09
PI25
TI7
445
1/0 (LDC)
P30
P44
P60
P68
V4
310
1/0
1'78
PlIO
PI26
V20
448
110
P61
P69
V5
313
1/0
1'127
U20
451
1/0
P62
P70
W5
316
1/0
P12B
T18
454
P111
P63
P71
V5
319
1/0
1"55
1"79
PI12
PI29
TI9
457
1/0
P64
P72
V6
322
1/0
1"56
PSO
P113
1"130
T20
460
1/0
P65
P73
W6
325
1/0
1'114
1"131
RIB
463
P74
V6
328
1/0
P115
PI32
RI9
466
1/0
PH6
P133
R20
469
110
PI17
1"134
1"18
472
1/0
,-
1/0
GND
1'45
P6S
'P75
GND'
1/0
P46
P67
P76'
W?
Novemoer25, 1997 (Version 0.6)
331
4-213
I
Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS30 & XCS30XL
Pad Name
VOl 00
GNO
T0144
P0208
P0240
BG256
P81
Pl18
P135
GNO'
Bndry
XCS30 & XCS30XL
Scan
Pad Name
V0100
T0144
1/0
1/0
P136
P20
475
1/0
1/0
P137
N18
478
1/0
Pl17
P0208
P0240
BG256
P165
P189
C16
Bndry
Scan
20
P190
816
23
P166
P191
A16
26
1/0
P82
Pl19
P138
N19
481
1/0
P167
P192
C15
29
1/0
P83
P120
P139
N20
484
1/0
P168
P193
815
32
35
P121
P140
VCC'
P169
P194
A15
1/0
P57
P84
P122
P141
M17
487
GNO
Pl18
P170
P196
GNO'
110
P58
P85
VCC
1/0
P123
P142
M18
490
1/0
P119
P171
P197
814
1/0
P124
P144
M20
493
1/0
P120
P172
P198
A14
41
1/0
P125
P145
L19
496
1/0
P199
C13
44
47
1/0
P59
P86
P126
P146
L18
499
1/0
1/0
P60
P87
P127
P147
L20
502
VCC
1/0
P61
P88
P128
P148
K20
505
1/0
P82
1/0
P62
P89
P129
P149
K19
508
110
P83
VCC
P63
P90
P130
P150
VCC'
GNO
P64
P91
P131
P151
GNO'
~-
38
P200
813
P173
P201
VCC'
P121
P174
P202
C12
50
P122
P175
P203
812
53
1/0
P176
P205
A12
56
110
Pl77
P206
811
59
P65
P92
P132
P152
K18
511
110
P84
P123
PH8
P207
Cll
62
1/0
P66
P93
P133
P153
K17
514
110
P85
P124
P179
P208
All
65
1/0
P67
P94
P134
P154
J20
517
110
P86
P125
P180
P209
Al0
68
P95
P135
P155
J19
520
1/0
P87
P126
P181
P210
810
71
P136
P156
J18
523
GNO
P88
P127
P182
P211
GNO'
1/0
1/0
P137
P157
J17
526
1/0
P68
P96
P138
P159
H19
529
1/0
P69
P97
P139
P160
H18
532
P140
P161
VCC'
1/0
VCC
110
P98
P141
P162
G19
535
110
P99
P142
P163
F20
538
P164
G18
541
544
110
P165
F19
P166
GNO'
P167
F18
547
1/0
P144
P168
E19
1/0
P145
P169
1/0
P146
P170
1/0
P147
P171
019
559
110
P148
Pl72
C20
562
110
PlOO
GNO
P143
1/0
I
I
020
553
P195
E18
I
556
Pl01
P149
P173
E17
565
1/0
P71
Pl02
P150
P174
018
568
1/0
Pl03
P151
P175
C19
571
1/0
Pl04
P152
P176
820
574
1/0 (OIN)
P72
Pl05
P153
Pl77
C18
577
1/0, SGCK4
(OOUT)
P73
Pl06
P154
P178
819
580
CCLK
P74
Pl07
P155
P179
A20
VCC
P75
P108
P156
P180
VCC'
0, TOO
P76
P109
P157
P181
A19
GNO
P77
Pl10
P158
P182
GNO'
1/0
P78
Pl11
P159
P183
818
2
1/0, PGCK4
P79
P112
P160
P184
817
5
P113
P161
P185
C17
8
0
P114
P162
P186
016
11
1/0
P80
P115
P163
P187
A18
14
1/0
P81
Pl16
P164
P188
A17
17
4-214
PQ240
550
P70
1/0
Additional XCS30IXL Package Pins
P22;
P204*
110
1/0
10/22/97
* Pads labelled GND* or vee* are internally bonded to Ground or
vee planes within the package. They have no direct connection to
any specific package pin.
P37;
P219*
I
GNP Pins
P83;
I P98;
I
I
I P143;
I P158*
T
T
I
I
Not Connected Pins
I
I
9/24197
:j: Pins marked with this symbol are used for Ground connections on
some revisions of the device. These pins may not physically connect to anything on the current device revision. However, they
should be externally connected to Ground, if possible.
6G256
C14
E20
K4
R4
U15
Al
G20
U4
A7
J4
Y13
06
Fl
L17
R17
V7
I
B7
H4
U8
A13
M4
VCC Pins
011
07
F17
F4
P4
P17
U6
U7
W20
GNP Pins
08
04
N3
H17
U13
U17
Not Connected Pins
012
C8
M19
V9
014
G4
P19
Ul0
015
G17
R2
U14
013
N4
W14
017
N17
H2O
W9
J3
W13
6/4197
November 25, 1997 (Version 0.6)
~XIUNX
Pin Locations for XCS40 & XCS40XL Devices
XCS40 & XCS40XL
Bndry
Scan
XCS40 & XCS40XL
Bndry
PQ208
PQ240
BG256
1/0
P20
P24
Jl
239
86
1/0
P21
P25
K2
242
010
89
1/0
P22
P26
K3
245
P215
N3
92
1/0
P23
P27
Kl
248
1/0
P187
P216
B9
95
1/0
P24
P28
Ll
251
1/0
P188
P217
C9.
98
GND
P25
P29
GNO'
1/0
P189
P218
D9
101
VCC
P26
P30
VCC'
1/0
P190
P220
Ml
104
1/0
P27
P31
L2
254
1/0
P191
P221
B8
107
1/0
P28
P32
L3
257
1/0
C9
110
1/0
P29
P33
L4
260
1/0
A7
113
1/0
P30
P34
Ml
263
1/0
P31
P35
M2
266
P32
P36
M3
269
M4
272
PQ208
PQ240
BG256
VCC
P183
P212
VCC'
1/0
P184
P213
Clo
1/0
P185
P214
1/0
P186
Pad Name
Pad Name
P222
VCC'
1/0
P223
AS
116
1/0
1/0
P224
C7
119
1/0
VCC
P192
Scan
1/0
P193
P225
B6
122
1/0
P38
Nl
278
1/0
P194
P226
AS
125
1/0
P39
N2
281
GND
P195
P227
GNO'
VCC.
P33
P40
VCC'
1/0
P196
P228
C9
128
1/0
P34
P41
Pl
284
1/0
P197
P229
B5
131
1/0
P35
P42
P2
287
1/0
P198
P230
M
134
110
P36
,P43
Rl
290
1/0
Ple9
P231
C5
137
1/0
P37
P44
P3
293
1/0
P200
P232
B4
140
GND
P38
P45
GND'
1/0
P201
P233
A3
143
1/0
1/0
P202
P234
05
152
1/0
P39
P46
Tl
296
P47
R3
299
1/0
P203
P235
C4
155
1/0
P40
P48
T2
302
1/0
P204
P236
B3
158
1/0
P41
P49
Ul
305
110
P205
P237
B2
181
1/0
P42
P50
T3
308
110
P206
P238
A2
164
110
P43
P51
U2
311
1/0,SGCKl
P207
P239
C9
167
110
P44
P52
Vl
320
VCC
P208
P240
VCC'
1/0
P45
P53
T4
323
GND
Pl
Pl
GNO'
110
P46
P54
U3
326
110, PGCKl
P2
P2
Bl
170
110
P47
P55
V2
329
110
P3
P3
C2
173
1/0
P48
P56
Wl
332
1/0
P4
P4
D2
176
1/0,SGCK2
P49
P57
V3
335
1/0
P5
P5
D3
179
Don't Connect
PSO
P58
W2
338
1I0,TDI
P6
P6
E4
182
GND
P51
P59
GND'
I/O,TCK
P7
P7
Cl
185
MODE
P52
P50
Yl
1/0
P8
P8
01
194
VCC
P53
P61
VCC'
341
1/0
P9
P9
E3
197
Don't Connect
P54
P62
W3
342
110
Pl0
Pl0
E2
200
I/OPGCK2
P55
P63
Y2
343
1/0
Pll
Pl1
E1
203
1/0 (HDC)
P56
P64
W4
346
1/0
P12
P12
F3
206
1/0
PS7
P55
V4,
849
P13
F2
209
1/0
P58
P56
US
352
GND
P13
P14
GNO'
1/0
P59
P67
Y3
355
1/0
P14
P15
G3
212
110 ([DC)
P60
P58
Y4
358
110
P15
P16
<32
215
1/0
P61
PS9
V5
367
1/0, TMS
Pl~
P17
Gl
218
1/0
P62
P70
WS
370
1/0
P17
P18
H3
221
1/0
P63
P71
YS
373
VCC
P18
376
1/0
P19
VCe"
-,
1/0
P64
,P72
V6
1/0
P20
H2
224
1/0
P6S
P73
W6
1/0
P21
Hl
227
1/0
P74
Y6
1/0
J4
230
GND
P66
P75
GND'
1/0
J3
233
1/0
P67
P76
W7
385
J2
236
1/0
P68
P77
Y1
388 '.
1/0
P19
P23
November 25, 1997 (Version 0_6)
,
I
379
.'
<
382
4-215
Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS4D & XCS4DXL
Pad Name
PQ2D8
PQ24D
BG256
1/0
P69
P78
V8
Bndry
Scan
391
1/0
P70
P79
W8
394
VCC
P71
P80
VCC'
1/0
P72
P81
Y8
1/0
P73
P82
XCS4D & XCS40XL
Pad Name
Bndry
PQ20S
PQ240
BG256
1/0
Pl15
Pl32
R19
544
110
Pl16
Pl33
R20
547
1/0
Pl17
Pl34
P18
550
397
GND
Pl18
P135
GNO'
U9
400
1/0
Pl36
P20
1/0
V9
403
1/0
P137
N18
556
1/0
W9
406
1/0
Pl19
Pl36
N19
559
562
1/0
P84
Y9
409
1/0
P120
P139
N20
1/0
P8S
Wl0
412
VCC
P121
P140
VCC'
Scan
553
1/0
P74
P86
Vl0
415
1/0
Pl22
P141
M17
565
1/0
P7S
pa7
Yl0
418
1/0
P123
P142
M18
568
1/0
P76
P88
Yll
421
1/0
M19
574
(INIT)
VCC
GND
P77
P89
Wll
424
P78
P90
VCC'
P79
P91
GNO'
1/0
P80
P92
Vll
1/0
P81
P93
1/0
P82
1/0
P83
1/0
1/0
1/0
P124
P144
M20
577
1/0
P125
P145
L19
580
1/0
P126
P146
Lla
583
427
1/0
P127
P147
l20
586
Ull
430
1/0
P128
P148
K20
589
P94
Y12
433
1/0
P129
P149
K19
592
P9S
W12
436
P130
P150
VCC'
P84
P96
V12
439
VCC
GND
P131
P151
GNO'
pas
P97
U12
442
1/0
P132
P152
K18
595
1/0
Y13
445
1/0
P133
P153
K17
598
1/0
W13
448
1/0
Pl34
P154
J20
601
1/0
1/0
P99
V13
451
1/0
P135
P155
J19
604
1/0
Pl00
Y14
454
1/0
P136
P156
J18
607
1/0
P137
P157
J17
610
H2O
613
VCC
P86
Pl0l
VCC'
1/0
P87
Pl02
Y15
457
1/0
1/0
PB8
Pl03
V14
460
1/0
P138
P159
H19
619
1/0
P89
Pl04
W15
463
1/0
P139
P160
H18
622
1/0
P90
Pl05
Y16
466
VCC
P140
P161
VCC'
GND
P91
Pl06
GNO'
1/0
P141
P162
G19
625
Pl07
V15
469
1/0
P142
P163
F20
628
1/0
1/0
P92
Pl0a
W16
472
1/0
P164
G18
631
1/0
P93
Pl09
Y17
475
1/0
P165
F19
634
1/0
P94
Pll0
V16
478
GND
P166
GNO'
1/0
P95
P111
W17
481
1/0
1/0
P96
Pl12
Y18
484
1/0
P97
Pl13
U16
493
1/0
P98
Pl14
V17
496
1/0
P99
Pl15
W18
1/0
Pl00
Pl16
1/0
Pl0l
P117
1/0,SGCK3
GND
DONE
VCC
Pl02
P143
P167
F18
637
1/0
P144
P168
E19
640
1/0
P145
P169
020
643
1/0
P146
P170
E18
646
499
1/0
P147
P171
019
649
Y19
502
1/0
P148
P172
C20
652
V18
505
1/0
P149
P173
E17
655
Pl18
W19
508
1/0
P150
P174
018
658
Pl03
Pl19
GNO'
1/0
P151
P175
C19
667
P104
P120
Y20
1/0
P152
P176
B20
670
P1Q5
P121
VCC'
1/0 (DIN)
P153
Pl77
C18
673
PRoGRAM
Pl06
P122
V19
P154
P178
B19
676
1/0
Pl07
P123
U19
P155
P179
A20
P156
Plao
VCC'
P157
P181
A19
P158
P182
GNO'
P159
Pl83
B18
2
P160
P184
B17
5
Pl0a
P124
U18
514
110
Pl09
P125
T17
517
1/0
Pll0
P126
V20
.520
P127
U20
523
1/0,SGCK4
(DOUr)
CCLK
VCC
O,TOO
GND
1/0,
PGCK3
1/0
511
0
1/0
Plll
P128
T18
526
1/0
1/0
Pl12
P129
T19
596
1/0,
1/0
Pl13
P130
T20
538
1/0
P161
Pl65
C17
8
1/0
Pl14
P131
R18
541
1/0
P162
Pl96
016
11
4-216
PGCK4
November 25,1997 (Version 0.6)
~XILINX
XCS40 & XCS40XL
PQ208
PQ240
BG256
Bndry
Scan
110
P163
P187
A18
14
110
P164
P188
A17
H
110
P165
P189
C16
26
P190
B16
29
Pad Name
110
32-
110
P166
P191
A16
110
P167
P192
C15
35
110
P168
P193
815
38
110
P169
P194
A15
41
GNO
PHO
P196
GNO'
110
P171
P197
814
110
P172
P198
A14
47
110
P199
C13
50
110
P200
813
53
P201
VCC'
VCC
P173
110
110
PQ240
P22*
P204*
I
I
P195
I
P37*
P219*
I
I
GND Pins
P98t
P83*
I
I
I
P143t
I
I
P158*
I
Not Connected Pins
I
I
I
I
6/9/97
:j: Pins marked with this symbol are used for Ground connections on
some revisions of the device. These pins may not physically connect to anything on the current device revision. However. they
should be externally connected to Ground. if possible.
44
A13
56
012
59
110
P174
P202
C12
62
110
P175
P203
812
65
110
PH6
P205
A12
68
110
PH7
P206
811
71
110
PH8
P207
C11
74
110
PH9
P208
A11
77
110
P180
P209
A10
80
110
P181
P210
810
83
P182
P211
GNO'
GNO
Additional XCS40/XL Package Pins
BG256
C14
E20
K4
R4
U15
06
F1
L17
R17
V7
A1
G20
U4
B7
H4
U8
I
VCC Pins
07
011
F4
F17
P4
P17
U7
U6
W20
GND Pins
04
08
H17
N3
U13
U17
014
G4
P19
U10
015
G17
R2
U14
013
N4
W14
017
N17
6/17/97
10/23/97
November 25, 1997 (Version 0.6)
4-217
I
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Product Availability
Table 16 shows the packages and speed grades for Spartan Series devices. Table 17 shows the number of user lOs
avalable for each device/package combination.
Table 16: Component Availability Chart for Spartan Series FPGAs
Device
XCS05
XCS10
XCS20
XCS30
PINS
84
100
144
208
240
256
TYPE
Plast. PLCC
Plast. VQFP
Plast.TQFP
Plast. PQFP
Plast. PQFP
Plast. BGA
CODE
PC84
VQ100
TQ144
PQ208
PQ240
BG256
-3
C(I)
C(I)
C(I)
-4
C
C
-3
C(I)
C(I)
-4
C
C
C
-3
C(I)
C(I)
-4
C
C
C
-3
C(I)
C(I)
C(I)
C(I)
-4
C
C
C
C
C
C(I)
C(I)
C(I)
C
C
C
C(I)
C(I)
-3
XCS40
-4
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
-3
C(I)
C(I)
C(I)
-4
C
C
-3
C(I)
C(I)
-4
C
C
C
-3
C(I)
C(I)
-4
C
C
C
-3
C(I)
C(I)
C(I)
C(I)
-4
C
C
C
C
C
-3
C(I)
C(I)
C(I)
-4
C
C
C
PQ240
BG256
C(I)
C(I)
9/24/97
C
= Commercial
TJ
= 0° to +85°C
1= Industrial TJ = -40°C to + 100°C
Table 17: User I/O Chart for Spartan Series FPGAs
Package Type
Device
Max
I/O
PC84
VQ100
XCS05
80
61
XCS10
112
61
XCS20
160
XCS30
192
77
77
77
77
XCS40
224
XCS05XL
80
61
XCS10XL
112
61
XCS20XL
160
XCS30XL
192
XCS40XL
224
77
77
77
77
TQ144
PQ208
112
113
113
160
169
192
192
169
193
205
112
113
160
113
169
192
192
169
193
205
9/24/97
4-218
November 25, 1997 (Version 0.6)
~XILINX
Ordering Information
Example:
Dev;oe Typ'
JI
XCS20XL-3 PQ208C
=-:J
T
T,mpe"""" AM"
C = Commercial (TJ = 0 to +85°C)
I = Industrial (TJ = -40 to +100°C)
Speed Grade
-3
-4
Number of Pins
Package Type
BG = Ball Grid Array
VQ = Very Thin Quad Flat Pack
TQ = Thin Quad Flat Pack
PC = Plastic Lead Chip Carrier
PQ = Plastic Quad Flat Pack
I
November 25, 1997 (Version 0.6)
4-219
Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-220
November 25, 1997 (Version 0.6)
XC5200 Series Table of Contents
XC5200 Field Programmable Gate Arrays
Features ........................................... >. • • • • • • • • • • • • • • • • • • • • • • • • • • • ••
Description ...................... >' • • • . . • . . • . . . . . . . . . . . . . . . . . . . . . >. . . . . . . . . . . . • . " . . •
XC5200 Family Compared to XC4000 and XC3000 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configurable Logic Block (CLB) Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Input/Output Block (lOB) Resources. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Routing Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration and Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
VersaBlock: Abundant Local Routing Plus Versatile Logic ............ , . . . . . . . . . . . . . ..
VersaRing I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
General Routing Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Performance Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Taking Advantage of Reconfiguration ....................... ; .....................
Detailed Functional Description ...........................................•...........
Configurable Logic Blocks (CLBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-lnput Functions . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Carry Function . . .. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Cascade Function. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CLB Flip-Flops and Latches •............................................. , . . . ..
Data Inputs and Outputs. . .. . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . ..
Clock Input •................................................•... i . . . . . ..
Clock Enable ....
Clear ............ : ......... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Global Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . .. . ..
Using FPGA Flip-Flops and Latches .................... ,.. . . . .. . .. . . . . . . . .. . . . . ..
Three-State Buffers ........................ '. . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . ..
Input/Output Blocks ...........................................................
lOB Input Signals .......... ; .................. '.............. , . ; . . . . . . . . ..
Optional Delay Guarantees Zero Hold Time ....................... , ............
lOB Output Signals .....•........... , . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Other lOB Options .. . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Oscillator ............................................................... ',' " ..
VersaBlock Routing ............. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Local Interconnect Matrix .................................................... ,.
Direct Connects ....................................................... . . . . ..
General Routing Matrix ............. , ...•........................... ; ................
,
Single- and Double-Length Lines ...... : ....................... ; . . . . . . . . . . . . . . . ..
Longlines ..................................... : .............. '; ..............
Global Lines ................................. ~ i . . . . . . . . . . ; . . . . . . . . . . . . . . . . . .
VersaRing Input/Output Interface .... , ......... ; ... , .. .. . . . . . . . . . . . . . .. . . . . . . . . . ..
Boundary Scan ...•....... ; .............•............... ', . . . . . . . . . . . . . . . . . . . . . . . ...
Data Registers ...........' .......... ; ..........•.... , .. : ........... , . . . . . . . ..
Instruction Set: .. , , .................• ;: .... " ... ':", .. '... , ............. : . . . . . . . . ..
Bit Sequence ......•...... '.......... ( . '...........•..... ',' .',' . . . . . . . . . . . . . . . . ..
Including Boundary Scan ................ , ..................................' ...
Avoiding Inadvertent Boundary Scan ..• , ............. , ....... ; ....... , ; . . . . . . . . ..
Power Distribution ....................... ; ...................... ;; .. : ..... : " . . . . . . ..
Pin Descriptions ..........•.................... : ........ : .................... : ... '..
>• • • • •
>• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • > • • • • • • •
4-225
4-225
4-226
4-226
4-226
4-226
4-226
4-227
4-227
4-228
4-228
4-229
4-229
4-229
4-229
4-229
4-230
4-231
4-231
4-231
4-231
4-231
4-231
4-232
4-232
4-232
4-233
4-233
4-233
4-234
4-234
4-235
4-235
4-235
4-236
4-236
4-238
4-238
4-238
4-240
4-240
4-242
4-242
4-242
4c242
4-243
4-243
4-243
I
4-221
XC5200 Series Table of Contents
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Special Purpose Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration Modes ..........................................................
Master Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Peripheral Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Slave Serial Mode ........................................................
Express Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Setting CCLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Data Stream Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Cyclic Redundancy Check (CRC) for Configuration and Readback ......................
Configuration Sequence .................•................................... "
Power-On Time-Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration ................................................................
Delaying Configuration After Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Start-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DONE Goes High to Signal End of Configuration ................................
Release of User I/O After DONE Goes High . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . ..
Release of Global Reset After DONE Goes High. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration Complete After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration Through the Boundary Scan Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Readback Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Read Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Read Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Violating the Maximum High and Low Time Specification for the Readback Clock. . . . . . . . ..
Readback with the XChecker Cable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Master Parallel Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Synchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ..
Asynchronous Peripheral Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Write to FPGA ...........................................................
Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Express Mode .............................................. ',' . . . . . . . . . . . . . ..
Configuration Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Master Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Slave and Peripheral Modes. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . ..
XC5200 Program Readback Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . ..
XC5200 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ..
Definition of Terms ...........................................................
XC5200 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . ..
XC5200 DC Characteristics Over Operating Conditions .......................... i • • •
XC5200 Absolute Maximum Ratings ................................. , . . . . . . . . ...
XC5200 Global Buffer Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC5200 Longline Switching Characteristic Guidelines. . . . . . . . . . . .. . .. . . . .. . . . . . . . . . ..
XC5200 CLB Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . ... . . . . . •. . .. ..
XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin) ..... . . . . . . . . . . . . . . . . . ..
XC5200 lOB Switching Characteristic Guidelines ........................ ,..........
XC5200 Boundary Scan (JTAG) Switching Characteristic GlJidelines .....................
Device-Specific Pinout Tables .......................................... , ..... " ......
Pin Locations for XC5202 Devices. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional No Connect (N.C.) C9nnections on TQ144 Package ................. , .......
Pin Locations for XC5204 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-222
4-246
4-246
4-246
4-246
4-247
4-247
4-248
4-248
4-249
4-249
4-250
4-250
4-250
4-252
4-252
4-252
4-253
4-253
4-254
4-254
4-254
4-254
4-255
4-255
4-255
4-255
4-255
4-255
4-256
4-256
4-257
4-258
4-260
4-262
4-262
4-262
4-264
4-267
4-267
4-267
4-268
4-269
4-269
4-269
4-269
4c269
4-270
4-270
4-271
4-272
4-273
4-274
4-275
4-275
4-277
4-277
~XILINX
Additional No Connect (N.C.) Connections for PQ160 Package . . . . . . . . . . . . . . . . . . . . . . ..
Pin Locations for XC5206 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional No Connect (N.C.) Connections for PQ208 and TQ176 Packages ..............
Pin Locations for XC521 0 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional No Connect (N.C.) Connections for PQ208 and PQ240 Packages. . . . . . . . . . . . ..
Pin Locations for XC5215 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional No Connect (N.C.) Connections for HQ208, HQ240, and HQ304 Packages .. . . ..
Product Availability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
User 110 Per Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ordering Information ................................................................
4-280
4-281
4-284
4-284
4-289
4-289
4-295
4-296
4-296
4-296
I
4-223
XC5200 Series Table of Contents
4-224
XC5200 Series
Field Programmable Gate Arrays
December 10, 1997 (Version 5.0)
Product Specification
Features
•
• Low-cost, process-optimized, registerllatch rich, SRAM
based reprogram mabie architecture
0.511m three-layer metal CMOS process technology
- 256 to 1936 logic cells (3,000 to 23,000 "gates")
- Price competitive with Gate Arrays
• System Level Features
System performance beyond 50 MHz
- 6 levels of interconnect hierarchy
- VersaRing™ 110 Interface for pin-locking
- Dedicated carry logic for high-speed arithmetic
functions
Cascade chain for wide input functions
Built-in IEEE 1149.1 JTAG boundary scan test
circuitry on all 1/0 pins
- Internal 3-state bussing capability
Four dedicated low-skew clock or signal distribution
nets
• Versatile 1/0 and Packaging
- Innovative VersaRing™ 110 interface provides a high
logic cell to 110 ratio, with up to 244 1/0 signals
- Programmable output slew-rate control maximizes
performance and reduces noise
- Zero Flip-Flop hold time for input registers simplifies
system timing
- Independent Output Enables for external bussing
Footprint compatibility in common packages within
the XC5200 Series and with the XC4000 Series
Over 150 devicelpackage combinations, including
advanced BGA, TO, and VO packaging available
Fully Supported by XACTstepTM Development System
Automatic place and route software
Wide selection of PC and Workstation platforms
- Over 100 3rd-party Alliance interfaces
Supported by shrink-wrap Foundation software
Description
The XC5200 Field-Programmable Gate Array Family is
engineered to deliver the lowest cost of any FPGA family.
By optimizing the new XC5200 architecture for three-layer
metal (TLM) technology and a 0.5-l1m CMOS SRAM process, dramatic advances have been made in silicon efficiency. These advances position the XC5200 family as a
cost-effective, high-volume alternative. to gate arrays
Building on experiences gained with three previous successful SRAM FPGA families, the XC5200 family brings a
robust feature set to high-density programmable logic
design. The VersaBlock™ logic module, the VersaRing 110
interface, and a rich hierarchy of interconnect resources
combine to enhance design flexibility and reduce time-tomarket.Complete support for the XC5200 family is delivered through the familiar XACTstepsoftware environment.
The XC5200 family is fully supported on .popular workstation and PC platforms. Popular design entry methods are
fully supported, including ABEL, schematic capture, VHDL,
and Verilog HDL synthesis.Designers utilizing logic synthesis can use their existing tools to design with the XC5200
devices.
Table 2: XC5200 Field-Programmable Gate Array Family Members
Device
Logic Cells
Max Logic Gates
XC5202
XC5204
XC5206
XC5210
XC5215
256
480
784
1,296
1,936
3,000
6,000
10,000
16,000
23,000
-
Typical Gate Range
-
2,000 - 3,000
4,000 - 6,000
6,000 - 10,000
8x8
10 x 12
14 x 14
18 x 18
22 x22
64
120
196
324
484
Flip-Flops
256
480
784
1,296
1,936
1I0s
84
124
148
196
244
TBUFs per Longline
10
14
16
20
24
VersaBlock Array
CLBs
December 10, 1997 (Version 5.0)
10,000 - 16,000 15,000 - 23,000
4-225
I
XC5200 Series Field Programmable Gate Arrays
XC5200 Family Compared to XC4000
and XC3000 Series
For readers already familiar with the XC4000 and XC3000
FPGA Families, this section describes significant differences between them and the XC5200 family. Unless otherwise indicated, c()mparisons refer to both XC4000 and
XC3000 devices.
Table 3: Xilinx Field-Programmable Gate Array
Families
XC5200 XC4000 XC3000
Parameter
Function generators per CLB
4
3
2
Logic inputs per CLB
20
9
5
Logic outputs per CLB
12
4
2
Low-skew global buffers
4
a
2
User RAM
no
yes
no
Dedicated decoders
no
yes
no
Cascade chain
yes
no
no
Fast carry logic
yes
yes
no
Intemal 3-state drivers
yes
yes
yes
IEEE boundary scan
yes
yes
no
Output slew-rate control
yes
yes
yes
Configurable Logic Block (CLB) Resources
Each XC5200 CLB contains four independent 4-input function generators and four registers, which are configured as
four independent Logic Cells™ (LCs). The registers in each
XC5200 LC are optionally configurable as edge-triggered
D-type flip-flops or as transparent level-sensitive latches.
The XC5200 CLB includes dedicated carry logic that provides fast arithmetic carry capability. The dedicated carry
logic may also be used to cascade function generators for
implementing wide arithmetic functions.
XC4000 family: XC5200 devices have no wide edge
decoders. Wide decoders are implemented using cascade
logic. Although sacrificing speed for some designs, lack of
wide edge decoders reduces the die area and hence cost
of the XC5200.
XC4000 family: XC5200 dedicated carry logic differs from
that of the XC4000 family in that the sum is generated in an
additional function generator in the adjacent column. This
design reduces XC5200 die size and hence cost for many
applications. Note, however, that a loadable up/down
counter requires the same number of function generators in
both families. XC3000 has no dedicated carry.
XC4000 family: XC5200 lookup tables are optimized for
cost and hence cannot implement RAM.
Input/Output Block (lOB) Resources
The XC5200 family maintains footprint compatibility with
the XC4000 family, but not with the XC3000 family.
To minimize cost and maximize the number of I/O per Logic
Cell, the XC5200 110 does not include flip-flops or latches.
For high performance paths, the XC5200 family provides
direct connections from each lOB to the registers in the
adjacent CLB in order to emulate lOB registers.
Routing Resources
The XC5200 family provides a flexible coupling of logic and
local routing resources called the VersaBlock. The XC5200
VersaBlock element includes the CLB, a Local Interconnect
Matrix (LIM), and direct connects to neighboring VersaBlocks.
The XC5200 provides four global buffers for clocking or
high-fanout control signals. Each buffer may be sourced by
means of its dedicated pad or from any internal source.
Each XC5200 TBUF can drive up to two horizontal and two
vertical Longlines. There are no internal pull-ups for
XC5200 Longlines.
Configuration and Readback
The XC5200 supports a new configuration mode called
Express mode, not available in XC4000/E or XC3000 Families.
XC4000 family: The XC5200 family provides a global
reset but not a global set.
Each XC5200 I/O Pin provides a programmable delay element to control input set-up time. This element can be used
to avoid potential hold-time problems. Each XC5200 I/O Pin
is capable of a-mA source and sink currents.
XC5200 devices use a different configuration process than
that of the XC3000 family, but use the same process as the
XC4000 family.
IEEE 1149.1-type boundary scan is supported in each
XC5200 I/O.
XC3000 family: Although their configuration processes differ, XC5200 devices may be used in daisy chains with
XC3000 devices.
XC3000 family: The XC5200 PROGRAM pin is a singlefunction input pin that overrides all other inputs. The program pin does not exist in XC3000.
4-226
December 10, 1997 (Version 5.0)
~XILINX
XC3000 family: XC5200 devices support an additional programming mode: Peripheral Synchronous.
XC3000 family: The XC5200 family does not support
Power-down, but offers a Global 3-state input that does not
reset any flip-flops.
XC3000 family:The XC5200 family does not provide an onchip crystal oscillator amplifier, but it does provide an internal oscillator from which a variety of frequencies up to 12
MHz are available.
ArchitecturalOverview
Figure 2 presents a simplified, conceptual overview of the
XC5200 architecture. Similar to conventional FPGAs, the
XC5200 family consists of programmable lOBs, programmable logic blocks, and programmable interconnect. Unlike
other FPGAs, however, the logic and local routing
resources of the XC5200 family are combined in flexible
VersaBlocks (Figure 3). General-purpose routing connects
to the VersaBlock through the General Routing Matrix
(GRM).
InpuVOutput Blocks (lOBs)
c1C1DDDDDDD
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
I
X4955
Figure 2: XC5200 Architectural Overview
VersaBlock: Abundant Local Routing Plus
Versatile Logic
The basic logic element in each VersaBlock structure is the
Logic Cell, shown in Figure 4. Each LC contains a 4-input
function generator (F), a storage device (FD), and control
logic. There are five independent inputs and three outputs
to each LC. The independence of the inputs and outputs
allows the software to maximize the resource utilization
within each LC. Each Logic Cell also contains a direct
feedthrough path that does not sacrifice the use of either
the function generator or the register; this feature is a first
for FPGAs. The storage device is configurable as either a D
flip-flop or a latch. The control logic consists of carry logic
for fast implementation of arithmetic functions, which can
also be configured as a cascade chain allowing decode of
very wide input functions.
Figure 3: VersaBlock
co
F1
x
CI
CE CK
CLR
X4956
Figure 4: XC5200 Logic Cell (Four LCs per CLB)
December 10, 1997 (Version 5.0)
4-227
XC5200 Series Field Programmable Gate Arrays
The XC5200 CLB consists of four LCs, as shown in
Figure 5. Each CLB has 20 independent inputs and 12
independent outputs. The top and bottom pairs of LCs can
be configured to implement 5-input functions. The challenge of FPGA implementation software has always been
to maximize the usage of logic resources. The XC5200
family addresses this issue by surrounding each CLB with
two types of local interconnect - the Local Interconnect
Matrix (LIM) and direct connects. These two interconnect
resources, combined with the CLB, form the VersaBlock,
represented in Figure 3.
LC3
DI
~,.-----
P.
rflr£l
D
>-- I--
~
P.
rfl-
~r-fl~
F
LC1
DI
~-
P.
rfl-
~r-fl~
F
LCO
DI
~-
P.
rfl-
~ril~
x
VersaRing 1/0 Interface
~
The interface between the lOBs and core logic has been
redesigned in the XC5200 family. The lOBs are completely
decoupled from the core logic. The XC5200 lOBs contain
dedicated boundary-scan logic for added board-level testability, but do not include input or output registers. This
approach allows a maximum number of lOBs to be placed
around the device, improving the I/O-to-gate ratio and
decreasing the cost per liD. A ''freeway'' of interconnect
cells surrounding the device forms the VersaRing, which
provides connections from the lOBs to the internal logic.
These incremental routing resources provide abundant
connections from each lOB to the nearest VersaBlock, in
addition to Longline connections surrounding the device.
The VersaRing eliminates the historic trade-off between
high logic utilization and pin placement flexibility. These
incremental edge resources give users increased flexibility
in preassigning (i.e., locking) liD pins before completing
their logic designs. This ability accelerates time-to-market,
since PCBs and other system components can be manufactured concurrent with the logic design.
FD
~
r--x
DO
r---
c-9-
D
-:l
FD
>-- I x
DO
r---
~
D
FD
~
CE CK
X
CLR
X4957
Figure 5: Configurable.Logic Block
4-228
The direct connects allow immediate connections to neighboring CLBs, once again without using any of the general
interconnect. These two layers of local routing resource
improve the granularity of the architecture, effectively making the XC5200 family a "sea of logic cells." Each VersaBlock has four 3-state buffers that share a common enable
line and directly drive horizontal and vertical Longlines, creating robust on-chip bussing capability. The VersaBlock
allows fast, local implementation of logic functions, effectively implementing user designs in a hierarchical fashion.
These resources also minimize local routing congestion
and improve the efficiency of the general interconnect,
which is used for connecting larger groups of logic. It is this
combination of both fine-grain and coarse-grain architecture attributes that maximize logic utilization in the XC5200
family. This symmetrical structure takes full advantage of
the third metal layer, freeing the placement software to
pack user logic optimally with minimal routing restrictions.
DO
~I -
F
-
D
~
-
-
,---
~
-
-
~
FD
-
~-
r£l
DO
r---
-
DI
r£l
~r-fl~
F
LC2
r£l
co
The LIM provides 100% connectivity of the inputs and outputs of each LC in a given CLB. The benefit of the LIM is
that no general routing resources are required to connect
feedback paths within a CLB. The LIM connects to the
GRM via 24 bidirectional nodes.
General Routing Matrix
The GRM is functionally similar to the switch matrices
found in other architectures, but it is novel in its tight coupling to the logic resources contained in the VersaBlocks.
Advanced simulation tools were used during the development of the XC5200 architecture to determine the optimal
level of routing resources required. The XC5200 family contains six levels of interconnect hierarchy - a series of single-length lines, double-length lines, and Longlines all
December 10, 1997 (Version 5.0)
~XILINX
routed through the GRM. The direct connects, LIM, and
logic-cell feedthrough are contained within each VersaBlock. Throughout the XCS200 interconnect, an efficient
multiplexing scheme, in combination with three layer metal
(TLM), was used to improve the overall efficiency of silicon
usage.
Performance Overview
Detailed Functional Description
Configurable Logic Blocks (CLBs)
Figure 5 shows the logic in the XC5200 CLB, which consists of four Logic Cells (LC[3:0]). Each Logic Cell consists
of an independent 4-input Lookup Table (LUT), and a DType flip-flop or latch with common clock, clock enable, and
clear, but individually selectable clock polarity. Additional
logic features provided in the CLB are:
The XCS200 family has been bench marked with many
designs running synchronous clock rates beyond 66 MHz.
The performance of any design depends on the circuit to be
implemented, and the delay through the combinatorial and
sequential logic elements, plus the delay in the interconnect routing. A rough estimate of timing can be made by
assuming 3-6 ns per logic level, which includes direct-connect routing delays, depending on speed grade. More
accurate estimations can be made using the information in
the Switching Characteristic Guideline section.
• An independent S-input LUT by combining two 4-input
LUTs.
• High-speed carry propagate logic.
• High-speed pattern decoding.
• High-speed direct connection to flip-flop D-inputs.
• Individual selection of either a transparent, levelsensitive latch or a D flip-flop.
• Four 3-state buffers with a shared Output Enable.
Taking Advantage of Reconfiguration
S-Input Functions
FPGA devices can be reconfigured to change logic function
while resident in the system. This capability gives the system designer a ne.w degree of freedom not available with
any other type of logic.
Figure 6 illustrates how the outputs from the LUTs from
LCO and LC1 can be combined .with a 2:1 multiplexer
(FS_MUX) to provide a S-input function. The outputs from
the LUTs of LC2 and LC3 can be similarly combined.
Hardware can be changed as easily as software. Design
updates or modifications are easy, and can be made to
products already in the field. An FPGA can even be reconfigured dynamically to perform different functions at different times.
Reconfigurable logic can be used to implement system
self-diagnostics, create systems capable of being reconfigured for different environments or operations, or implement
mUlti-purpose hardware for a given application. As an
added benefit, using reconfigurable FPGA devices simplifies hardware design and debugging and shortens product
time-to-market.
5-lnput Function
Figure 6: Two LUTs in Parallel Combined to Create a
5-input Function
December 10, 1997 (Version 5.0)
4-229
I
XC5200 Series Field Programmable Gate Arrays
A3 and 83
to any two
A2
or
B2
A2 and B2
to any two
A1
or
B1
A1 and 81
to any two
AO
or
BO
AO and BO
to any two
X
Initialization of
carry chain (One Logic Cell)
X5709
Figure 7: XC5200 CY_MUX Used for Adder Carry Propagate
Carry Function
The XC5200 family supports a carry-logic feature that
enhances the performance of arithmetic functions such as
counters, adders, etc. A carry multiplexer (CY_MUX) symbol is used to indicate the XC5200 carry logic. This symbol
represents the dedicated 2:1 multiplexer in each LC that
performs the one-bit high-speed carry propagate per logic
cell (four bits per CLB).
While the carry propagate is performed inside the LC, an
adjacent LC must be used to complete the arithmetic function. Figure 7 represents an example of an adder function.
The carry propagate is performed on the CLB shown,
which also generates the half-sum for the four-bit adder. An
adjacent CLB is responsible for XORing the half-sum with
the corresponding carry-out. Thus an adder or counter
4-230
requires two LCs per bit. Notice that the carry chain
requires an initialization stage, which the XC5200 family
accomplishes using the carry initialize (CY_INIT) macro
and one additional LC. The carry chain can propagate vertically up a column of CLBs.
The XC5200 library contains a set of Relationally-Placed
Macros (RPMs) and arithmetic functions designed to take
advantage of the dedicated carry logic. Using and modifying these macros makes it much easier to implement customized RPMs, freeing the designer from the need to
become an expert on architectures.
December 10, 1997 (Version 5.0)
~XIUNX
cascade out
Table 4: CLB Storage Element Functionality
(active rising edge is shown)
Mode
Power-Up or
GR
CK
CE
CLR
X
X
X
X
0
X
---1
X
1*
1
Flip-Flop
X
D
0
D
X
X
D
X
Q
Latch
0
1
0
X
Both
X
1*
l'
O'
O'
O'
O'
0
0*
D
Q
Q
D
Q
Legend:
X
-.l-
A9
A8
0*
1*
Don't care
Rising edge
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
I
Data Inputs and Outputs
The source of a storage element data input is programmable. It is driven by the function F, or by the Direct In (DI)
block input. The flip-flops or latches drive the Q CLB outputs.
1
Four fast feed-through paths from 01 to DO are available,
as shown in
5. This bypass is sometimes used by
the automated router to repower internal signals. In addition to the storage element (Q) and direct (DO) outputs,
there is a combinatorial output.(X) that is always sourced by
the Lookup Table.
Initialization of
carry chain (One Logic Cell)
Figure 8: XC5200 CY_MUX Used for Decoder Cascade
Logic
The four edge-triggered O-type flip-flops or level-sensitive
latches have common clock (CK) and clock enable (CE)
inputs. Any of the clock inputs can also be permanently
enabled. Storage element functionality is described in
Table 4.
Cascade Function
Clock Input
Each CY_MUX can be connected to the CY_MUX in the
adjacent LC to provide cascadable decode logic. Figure 8
illustrates how the 4-input function generators can be configured to take advantage of these four cascaded
CY_MUXes. Note that AND and OR cascading are specific
cases of a general decode. In AND cascading all bits are
decoded equal to logic one, while in OR cascading all bits
are decoded equal to. logic zero. The flexibility of the LUT
achieves this result. The XC5200 library contains gate
macros designed to take advantage of this function.
The flip-flops can be triggered on either the rising or falling
clock edge. The clock pin is shared by all four storage elements with individual polarity control. Any inverter placed
on the clock input is automatically absorbed into the CLB.
Clock Enable
The clock enable signal (CE) is active High. The CE pin is
shared by the four storage elements. If left unconnected for
any, the clock enable for that storage element defaults to
the active state. CE is not invertible within the CLB.
CLB Flip-Flops and Latches
Clear
The CLB can pass the combinatorial output(s) to the interconnect network, but can also store the combinatorial
results or other incoming data in flip-flops, and connect
their outputs to the interconnect network as well. The CLB
storage elements can also be configured as latches.
An asynchronous storage element input (CLR) can be used
to reset all four flip-flops or latches in the CLB. This input
can also be independently disabled for any flip-flop. CLR is
active High. It is not invertible within the CLB.
December 10, 1997 (Version 5.0)
4-231
XC5200 Series Field Programmable Gate Arrays
STARTUP
PAD ) - - - -
>-------1
IBUF
GR
GTS
02
03
0104
elK DONEIN
X9009
Figure 9: Schematic Symbols for Global Reset
Global Reset
A separate Global Reset line clears each storage element
during power-up, reconfiguration, or when a dedicated
Reset net is driven active. This global net (GR) does not
compete with other routing resources; it uses a dedicated
distribution network.
GR can be driven from any user-programmable pin as a
global reset input. To use this global net, place an input
pad and input buffer in the schematic or HOL code, driving
the GR pin of the STARTUP symbol. (See Figure 9.) A
specific pin location can be assigned to this input using a
LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted
after the input buffer to invert the sense of the Global Reset
signal. Alternatively, GR can be driven from any internal
node.
Using FPGA Flip-Flops and Latches
The abundance of flip-flops in the XC5200 Series invites
pipelined designs. This is a powerful way of increasing performance by breaking the function into smaller subfunctions and executing them in parallel, passing on the results
through pipeline flip-flops. This method should be seriously
considered wherever throughput is more important than
latency.
To include a CLB flip-flop, place the appropriate library
symbol. For example, FOCE is a Ootype flip-flop with clock
enable and asynchronous clear. The corresponding latch
symbol is called LOCE.
In XC5200-Series devices, the flip-flops can be used as
registers or shift registers without blocking the function generators from performing a different, perhaps unrelated task.
This ability increases the functional capacity of the devices.
The CLB setup time is specified between the function generator inputs and the clock input CK. Therefore, the specified CLB flip-flop setup time includes the delay through the
function generator.
Three-State Buffers
The XC5200 family has four dedicated Three-State Buffers
(TBUFs, or BUFTs in the schematic library) per CLB (see
Figure 10). The four buffers are individually configurable
through four configuration bits to operate as simple noninverting buffers or in 3-state mode. When in 3-state mode
the CLB output enable (TS) control signal drives the enable
to all four buffers. Each TBUF can drive up to two horizontal
andlor two vertical Longlines. These 3-state buffers can be
used to implement multiplexed or bidirectional buses on the
horizontal or vertical long lines, saving logic resources.
TS
CLB
LC3
---LC2
---LC1
----
')
v
LCO
Horizontal
Longlines
X9Q30
Figure 10: XC5200 3-State Buffers
The 3-state buffer enable is an active-High 3-state (I.e. an
active-Low enable), as shown in Table 5.
Another 3-state buffer with similar access is located near
each 1/0 block along the right and left edges of the array.
The longlines driven by the 3-state buffers have a weak
keeper at each end. This circuit prevents undefined floating levels. .However, it is overridden by any driver. To
ensure the longline goes high when no buffers are on, add
an additional BUn to drive the output High during all of the
previously undefined states.
11 shows how to use the 3-state buffers to implement a multiplexer. The selection is accomplished by the
buffer 3-state signal.
Table 5: Three-State Buffer Functionality
IN
T
OUT
o
IN
x
IN
4-232
z
December 10, 1997 (Version 5.0)
~XILINX
, ___ ° ______________________________________ _
··
·
·
i
..
..
.1
-100kQ
r-~----------~----------~~----------~----------_.---
·------------------------------------------_..
"Weak Keeper"
A
Figure 11: 3-State Buffers Implement a Multiplexer
Input/Output Blocks
User-configurable input/output blocks (lOBs) provide the
interface between external package pins and the internal
logic. Each lOB controls one package pin and can be configured for input, output, or bidirectional signals.
The I/O block, shown in Figure 12, consists of an input
buffer and an output buffer. The output driver is an SomA
full-rail CMOS buffer with 3-state control. Two slew-rate
control modes are supported to minimize bus transients.
Both the output buffer and the 3-state control are invertible.
The input buffer has globally selected CMOS or TTL input
thresholds. The input buffer is invertible and also provides a
programmable delay line to assure reliable chip-to-chip setup and hold times. Minimum ESD protection is 3 KV using
the Human Body Model.
Vee
Delay
I--~--~--O
I--~------------_
T
Figure 12: XC52001/0 Block
lOB. Input Signals
The XC5200 inputs can be globally configured for either
TTL (1.2V) or CMOS thresholds, using an option in the bitstream generation software. There is a slight hysteresis of
about 300mV.
The inputs of XC5200-Series 5-Volt devices can be driven
by the outputs of any 3.3-Volt device, if the 5-Volt inputs are
in TTL mode.
Supported sources for XC5200-Series device inputs are
shown in Table 6.
December 10, 1997 (Version 5.0)
Table 6: Supported Sources for XC5200-Series Device
Inputs
Source
Vcc
=3.3 V,
I
Optional Delay Guarantees Zero Hold Time
XC5200 devices do not have storage elements in the lOBs.
However, XC5200 lOBs can be efficiently routed to CLB
flip-flops or latches to store the 1/0 signals.
The data input to the register can optionally be delayed by
several nanoseconds. With the delay enabled, the setup
time of the input flip-flop is increased so that normal clock
routing does not result in a positive hold-time requirement.
A positive hold time requirement can lead to unreliable,
temperature- or processing-dependent operation.
The input flip-flop setup time is defined between the data
measured at the device I/O pin and the clock input at the
CLB (not at the ciock pin). Any routing delay from the
device clock pin to the clock input of the CLB must, therefore, be subtracted from this setup time to arrive at the real
setup time requirement relative to the device pins. A short
specified setup time might, therefore, result in a negative
setup time at the device pins, i.e., a positive hold-time
requirement.
When a delay is inserted on the data line, more clock delay
can be tolerated without causing a positive hold-time
requirement. Sufficient delay eliminates the possibility of.a
data hold-time requirement at the external pin. The maximum delay is therefore inserted as the software default.
The XC5200 lOB has a one-tap delay element either the
delay is inserted (default), or it is not. The delay guarantees a zero hold time with respect to clocks routed through
any of the XC5200 global clock buffers. (See "Global
Lines" on page 238 for a description of the global clock
buffers in the XC5200.) For a shorter input register setup
time, with non-zero hold, attach a NODELAYattribute or
property to the flip-flop or input buffer.
4-233
XC5200 Series Field Programmable Gate Arrays
lOB Output Signals
Output signals can be optionally inverted within the lOB,
and pass directly to the pad. As with the inputs, a CLB flipflop or latch can be used to store the output signal.
An active-High 3-state signal can be used to place the output buffer in a high-impedance state, implementing 3-state
outputs or bidirectional I/O. Under configuration control,
the output (OUT) and output 3-state (T) signals can be
inverted. The polarity of these signals is independently
configured for each lOB.
The XC5200 devices provide a guaranteed output sink current of 8 mAo
Supported destinations for XC5200-Series device outputs
are shown in Table 7.(For a detailed discussion of how to
interface between 5 V and 3.3 V devices, see the 3V Products section of The Programmable Logic Data Book.)
An output can be configured as open-drain (open-collector)
by placing an OBUFT symbol in a schematic or HDL code,
then tying the 3-state pin (T) to the output signal, and the
i 3.)
input pin (I) to Ground. (See
Table 7: Supported Destinations for XCS200-Series
Outputs
XCS200 Output Mode
Destination
XC5200 device, V ee=3.3 V,
CMOS-threshold inputs
Any typical device, Vee = 3.3 V,
CMOS-threshold inputs
SV,
CMOS
..j
some 1
Any device, Vee = 5 V,
TTL-threshold inputs
..j
Any device, Vee =5 V,
CMOS-threshold inputs
..j
1. Only if destination device has 5-V tolerant inputs
J~~~~
~BUFT
X6702
Figure 13: Open-Drain Output
200 pF for all package pins between each Power/Ground
pin pair. For some XC5200 devices, additional internal
Power/Ground pin pairs are connected to special Power
and Ground planes within the packages, to reduce ground
bounce.
For slew-rate limited outputs this total is two times larger for
each device type: 400 pF for XC5200 devices. This maximum capacitive load should not be exceeded, as it can
result in ground bounce of greater than 1.5 V amplitude and
more than 5 ns duration. This level of ground bounce may
cause undesired transient behavior on an output, or in the
internal logic. This restriction is common to all high-speed
digital ICs, and is not particular to Xilinx or the XC5200
Series.
XC5200-Series devices have a feature called "Soft Startup;' designed to reduce ground bounce when all outputs
are turned on simultaneously at the end of configuration.
When the configuration process is finished and the device
starts up, the first activation of the outputs is automatically
slew-rate limited. Immediately following the initial activation
of the I/O, the slew rate of the individual outputs is determined by the individual configuration option for each lOB.
Global Three-State
A separate Global 3-State line (not shown in Figure 12)
forces all FPGA outputs to the high-impedance state,
unless boundary scan is enabled and is executing an
EXTEST instruction. This global net (GTS) does not compete with other routing resources; it uses a dedicated distribution network.
GTS can be driven from any user-programmable pin as a
global 3-state input. To use this global net, place an input
pad and input buffer in the schematic or HDL code, driving
the GTS pin of the STARTUP symbol. A specific pin location can be assigned to this input using a LOC attribute or
property, just as with any other user-programmable pad.
An inverter can optionally be inserted after the input buffer
to invert the sense of the Global 3-State signal. Using GTS
is similar to Global Reset. See Figure 9 on page 232 for
details .. Alternatively, GTS can be driven from any internal
node.
Other lOB Options
There are a number of other programmable options in the
XC5200-Series lOB.
Pull-up and Pull-down Resistors
Output Slew Rate
The slew rate of each output buffer is, by default, reduced,
to minimize power bus transients when switching non-critical signals. For critical signals, attach a FAST attribute or
property to the output buffer or flip-flop.
For XC5200 devices, maximum total capacitive load for
simultaneous fast mode switching in the same direction is
4-234
Programmable lOB pull-up and pull-down resistors are
useful for tying unused pins to Vcc or Ground to minimize
power consumption and reduce noise sensitivity. The configurable pull-up resistor is a p-channel transistor that pulls
to Vcc. The configurable pull-down resistor is an n-channel
transistor that pulls to Ground.
December 10, 1997 (Version 5.0)
~XIUNX
D:
The value of these resistors is 20 kn - 100 kn. This high
value makes them unsuitable as wired-AND pull-up resistors.
SC1
OSC5
OSC2
The pull-up resistors for most user-programmable lOBs are
active during the configuration process; See Table 14 on
page 266 for a list of pins with pull-ups active before and
during configuration.
After configuration, voltage levels of unused pads, bonded
or unbonded, must be valid logic levels, to reduce noise
sensitivity and avoid excess current. Therefore, by defal,llt,
unused pads are configured with the internal pull-up resistor active. Alternatively, they can be individually configured
with the pull-down resistor, or as a driven output, or to be
driven by an external source. To activate the internal pullup, attach the PUlLUP library component to the net
attached to the pad. To activate the internal pull-down,
attach the PUllDOWN library component to the net
attached to the pad.
JTAG Support
Embedded logic attached to the lOBs contains test structures compatible with IEEE Standard 1149.1 for boundary
scan testing, simplifying board-level testing. More information is provided in "Boundary Scan" on page 240.
Oscillator
XC5200 devices include an internal oscillator. This oscillator is used to clock the power-on time-out, clear configuration memory, and source CClK ,in Master configuration
modes. The oscillator runs at a nominal 12 MHz frequency
that varies with process, Vcc, and temperature. The output
CClK frequency is selectable as 1 MHz (default), 6 MHz, or
12 MHz.
The XC5200 oscillator divides the internal 12-MHz clock or
a user clock. ihe user then has the choice ofdividing by4,
16, 64, or 256 for the "OS01" output and dividing by 2,13,
32,128, 1024,4096, 16384, or 65536 for the "08C2"out~
put. The division is specified via. a "OIVIDErCBY=x"
attribute on the symbol, where n=1 for O~C1 or 0=2 for
08C2. These frequenCies canvaiy byas mUCh' as -50% or
+50%.·
.
"
,:~
,
The OSC5 macro is used where an internal oscillator is
required. Ihe CK-,-DIV macro is applicable when a user
cl51P< input ill spe~ified (see Figure 14).
" .
December 10, 199T(Version 5.0)
.-------. OSC1
ClK
OSC2
Figure 14: XC5200 Oscillator Macros
VersaBlock Routing
The General Routing Matrix (GRM) connects to the Versa. Block via 24 bidirectional ports (MO-M23). Excluding direct
connec~ions, global nets, and 3-statable longlines, all VersaBlock Inputs and outputs connect to the GRM via these 24
ports. Four 3-statable unidirectional signals (TQO-TQ3)
drive out of the VersaBlock directly onto the horizontal and
vertical longlines. Two horizontal global nets and two verti,cal global nets connect directly to every ClB clock pin; they
can connect to other ClB inputs via the GRM. Each ClB
also has four unidirectional direct connects to each of its
four neighboring ClBs. These direct connects. can also
feed dire-____ T~O~~:r
Ground pins of the package will provide adequate decoupiing.
Output buffers capable of driving/sinking the specified 8 mA
loads under specified worst-case conditions may be capable of driving/sinking up to 10 times as much current under
best case conditions.
IBUF
BseAN
RESET
UPDATE
SHIFT
>---*---1 TOI
>-----jTMS
TDO ~---1
DRCK
>----~TCK
From
User Logic
j
1
IDLE
TD01
SEL1
TD02
SEL2
1
J
To User
Logic
X9000
Figure 21: Boundary Scan Schematic Example
Noise can be reduced by minimizing external load capacitance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the Ground pads. The I/O Block
output buffers have a slew-rate limited mode (default) which
should be used where output rise and fall times are not
speed-critical.
Even if the boundary scan symbol is used in a schematic,
the input pins TMS, TCK, and TDI can still be used as
inputs to be routed to internal logic. Care must be taken not
to force the chip into an undesired boundary scan state by
inadvertently applying boundary scan input patterns to
these pins. The simplest way to prevent this is to keep TMS
High, and then apply whatever signal is desired to TDI and
TCK.
GND
rr.==:=:::;:=;:::~~=;::::;==;:::;:]~--:: Ground and
_+ __ + __ +__ +__ +__ -t--- +_
Vee Ring for
+__
Vee
Avoiding Inadvertent Boundary Scan
If TMS or TCK is used as user I/O, care must be taken to
ensure that at least one of these pins is held constant during configuration. In some applications, a situation may
occur where TMS or TCK is driven during configuration.
This may cause the device to go into boundary scan mode
and disrupt the configuration process.
•
TMS: Tie High to put the Test Access Port controller
in a benign RESET state
TCK: Tie High or Low-do not toggle this clock input.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I!
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-+-- +--+-- +-+-- +-- +--+J
I
I
I
I
I
I
I
I
-+-+-+--+-+-+-+--+I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-+-+-+-+-+-+-+--+I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-+-+-+-+--+-+-- +--+I
I
I
I
I
I
I
,_-r-1rn--,
I
I
I
I
I
-+--+-+-+-+-+--+I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
t
-+-- +-- +-- +-- +-- +-- +--+I
I
I/O Drivers
Logie
Power Grid
-+-+-- +-- +--+-- +-- +--+I
I
GND
X5422
Figure 22: XCS200-Series Power Distribution
To prevent activation of boundary scan during configuration, do either of the following:
•
I
I
Pin Descriptions
There are three types of pins in the XC5200-Series
devices:
For more information regarding boundary scan, refer to the
Xilinx Application Note XAPP 017, "Boundary Scan in
XC4000 and XC5200 Devices."
•
•
•
Power Distribution
Before and during configuration, all outputs not used for the
configuration process are 3-stated and pulled high with a
20 kQ - 100 kQ pull-up resistor.
Power for the FPGA is distributed through a grid to achieve
high noise immunity and isolation between logic and 110.
Inside the FPGA, a dedicated Vcc and Ground ring surrounding the logic array provides power to the 110 drivers,
as shown in Figure 22. An independent matrix of Vcc and
Ground lines supplies the interior logic of the device.
This power distribution grid provides a stable supply and
ground for all internal logic, providing the external package
power pins are all connected and appropriately decoupled.
Typically, a 0.1 I-lF capacitor connected near the Vcc and
December 10, 1997 (Version 5.0)
Permanently dedicated pins
User I/O pins that can have special functions
Unrestricted user-programmable I/O pins.
After configuration, if an lOB is unused it is configured as
an input with a 20 kQ - 100 kQ pull-up resistor.
Device pins for XC5200-Series devices are described in
Table 10. Pin functions during configuration for each of the
seven configuration modes are summarized in "Pin Functions During Configuration" on page 266, in the "Configuration Timing" section.
4-243
I
XC5200 Series Field Programmable Gate Arrays
Table 10: Pin Descriptions
Pin Name
1/0
1/0
During
After
Config. Config.
Pin Description
Permanently Dedicated Pins
VCC
I
I
GND
I
I
CCLK
10rO
I
DONE
PROGRAM
I/O
I
Five or more (depending on package) connections to the nominal +5 V supply voltage.
All must be connected, and each must be decoupled with a 0.01 - 0.1 ~F capacitor to
Ground.
Four or more (depending on package type) connections to Ground. All must be connected.
During configuration, Configuration Clock (CCLK) is an output in Master modes or Asynchronous Peripheral mode, but is an input in Slave mode, Synchronous Peripheral
mode, and Express mode. After configuration, CCLK has a weak pull-up resistor and
can be selected as the Readback Clock. There is no CCLK High time restriction on
XC5200-Series devices, except during Readback. See "Violating the Maximum High
and Low Time Specification lor the Readback Clock" on page 255 for an explanation of
this exception.
0
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it
indicates the completion of the configuration process. As an input, a Low level on
DONE can be configured to delay the global logic initialization and the enabling of outputs.
The exact timing, the clock source for the Low-to-High transition, and the optional pullup resistor are selected as options in the XACTstep program that creates the configuration bitstream. The resistor is included by default.
I
PROGRAM is an active Low input that forces the FPGA to clear its configuration memory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA
executes a complete clear cycle, before it goes into a WAIT state and releases INIT.
The PROGRAM pin has an optional weak pull-up after configuration.
User 110 Pins That Can Have Special Functions
ROY/BUSY
RCLK
MO,M1,M2
TOO
4-244
0
0
I
0
I/O
During Peripheral mode configuration, this pin indicates when it is appropriate to write
another byte of data into the FPGA. The same status is also available on 07 in Asynchronous Peripheral mode, if a read operation is performed when the device is selected.
After configuration, ROY/BUSY is a user-programmable I/O pin.
ROY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High.
I/O
During Master Parallel configuration, each change on the AO-A 17 outputs is preceded
by a rising edge on RCLK, a redundant output signal. RCLK is useful for clocked
PROMs. It is rarely used during configuration. After configuration, RCLK is a user-programmable I/O pin.
I/O
As Mode inputs, these pins are sampled before the start of configuration to determine
the configuration mode to be used. After configuration, MO, M1, and M2 become userprogrammable I/O.
During configuration, these pins have weak pull-up resistors. For the most popular configuration mode, Slave Serial, the mode pins can thus be left unconnected. A pull-down
resistor value of 4.7 kQ is recommended for other modes.
0
If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used,
this pin is a 3-state output, after configuration is completed.
This pin can be user output only when called out by special schematic definitions. To
use this pin, place the library component TOO instead of the usual pad symbol. An output buffer must still be used.
December 10, 1997 (Version 5.0)
~XILINX
Table 10: Pin Descriptions (Continued)
Pin Name
1/0
1/0
During
After
Config. Config.
TDI, TCK,
TMS
I
HDC
0
LDC
0
INIT
110
Four Global inputs each drive a dedicated intemal global net with short delay and minimal skew. These internal global nets can also be driven from internal logic. If not used
to drive a global net, any of these pins is a user-programmable 110 pin.
lor 110
The GCK1-GCK4 pins provide the shortest path to the four Global Buffers. Any input
pad symbol connected directly to the input of a BUFG symbol is automatically placed
on one of these pins.
These four inputs are used in Asynchronous Peripheral mode. The chip is selected
when CSO is Low and CSl is High. While the chip is selected, a Low on Write Strobe
(WS) loads the data present on the DO - D7 inputs into the internal data buffer. A Low
on Read Strobe (RS) changes D7 into a status output - High if Ready, Low if Busy110
and drives DO - D6 High.
In Express mode, CSl is used as a serial-enable signal for daisy-chaining.
WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write
Strobe overrides. After configuration, these are user-programmable 110 pins.
GCKl GCK4
Weak
Pull-up
CSO, CS1,
WS,RS
I
AO - A17
0
110
DO - D7
I
.1/0
DIN
I
110
DOUT
0
Pin Description
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select
inputs respectively. They come directly from the pads, bypassing the lOBs. These pins
can also be used as inputs to the CLB logic after configuration is completed.
110
If the BSCAN symbol is not placed in the design, all boundary scan functions are inhiborl
ited once configuration is completed, and these pins become user-programmable 110.
(JTAG)
In this case, they must be called out by special schematic definitions. To use these pins,
place the library components TDI, TCK, and TMS instead of the usual pad symbols. Input or output buffers must still be used.
High During Configuration (HDC) is driven High until the liD go active. It is available as
a control output indicating that configuration is not yet completed. After configuration,
liD
HDC is a user-programmable 110 pin.
Low During Configuration (LDC) is driven Low until the 110 go active. It is available as a
control output indicating that configuration is not yet completed. After configuration,
110
LDC is a user-programmable 110 pin.
Before and during configuration, INIT is a bidirectional signal. A 1 kQ - 10 kQ external
pull-up resistor is recommended.
As an active-Low open-drain output, INIT is held Low during the power stabilization and
internal clearing of the configuration memory. As an active-Low input, it can be used
I/O
to hold the FPGA in the internal WAIT state before the start of configuration. Master
mode devices stay in a WAIT state an additional 50 to 250 I1s after INIT has gone High.
During configuration, a Low on this output indicates that a configuration data error has
occurred. After the 110 go active, INIT is a user-programmable 110 pin.
110
December 10, 1997 (Version 5.0)
During Master Parallel configuration, these 18 output pins address the configuration
EPROM. After configuration, they are user-programmable 110 pins.
During Master Parallel, Peripheral, and Express configuration, these eight input pins receive configuration data. After configuration, they are user-programmable 110 pins.
During Slave Serial or Master Serial configuration, DIN is the serial configuration data
input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is
the DO input. After configuration, DIN is a user-programmable 110 pin.
During configuration in any mode but Express mode, DOUT is the serial configuration
data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes
on the falling edge of CCLK.
In Express mode, DOUT is the status output that can drive the CSl of daisy-chained
FPGAs, to enable and disable downstream devices.
After configuration, DOUT is a user-programmable 110 pin.
4-245
I
XC5200 Series Field Programmable Gate Arrays
Table 10: Pin Descriptions (Continued)
1/0
1/0
During
After
Pin Name
Config. Config.
Pin Description
Unrestricted User-Programmable 1/0 Pins
These pins can be configured to be input andlor output after configuration is completed.
Weak
Before configuration is completed, these pins have an internal high-value pull-up resis1/0
I/O
Pull-up
tor (20 kQ - 100 kQ) that defines the logic level as High.
Configuration
Table 11: Configuration Modes
Configuration is the process of loading design-specific programming data into one or more FPGAs to define the functional operation of the internal blocks and their
interconnections. This is somewhat like loading the command registers of a programmable peripheral chip.
XC5200-Series devices use several hundred bits of configuration data per CLB and its associated interconnects.
Each configuration bit defines the state of a static memory
cell that controls either a function look-up table bit, a multiplexer input, or an interconnect pass transistor. The XACTstep development system translates the design into a
netlist file. It automatically partitions, places and routes the
logic and generates the configuration data in PROM format.
Mode
Master Serial
Slave Serial
Master
Parallel Up
M2
M1
0
1
1
0
1
Master
Parallel Down
Peripheral
Synchronous'
Peripheral
Asynchronous
Express
Reserved
Special Purpose Pins
Three configuration mode pins (M2, M1, MO) are sampled
prior to configuration to determine the configuration mode.
After configuration, these pins can be used as auxiliary 1/0
connections. The XACTstep development system does not
use these resources unless they are explicitly specified in
the design entry. This is done by placing a special pad
symbol called MD2, MD1, or MDO instead of the input or
output pad symbol.
In XC5200-Series devices, the mode pins have weak pullup resistors during configuration. With all three mode pins
High, Slave Serial mode is selected, which is the most popular configuration mode. Therefore, for the most common
configuration mode, the mode pins can be left unconnected. (Note, however, that the internal pull-up resistor
value can be as high as 100 kQ.) After configuration, these
pins can individually have weak pull-up or pull-down resistors, as specified in the design. A pull-down resistor value
of 4.7 kQ is recommended.
These pins are located in the lower left chip corner and are
near the readback nets. This location allows convenient
routing if compatibility with the XC2000 and XC3000 family
conventions of MO/RT, M1/RD is desired.
Configuration Modes
XC5200 devices have seven configuration modes. These
modes are selected by a 3-bit input code applied to the M2,
M1, and MO inputs. There are three self-loading Master
modes, two Peripheral modes, and a Serial Slave mode,
4-246
0
MO
0
1
0
CCLK
output
input
output
1
1
0
output
0
1
1
input
Data
Bit-Serial
Bit-Serial
Byte-Wide,
increment
from 00000
Byte-Wide,
decrement
from 3FFFF
Byte-Wide
1
0
1
output
Byte-Wide
0
0
1
0
0
1
input
-
Byte-Wide
-
Note :*Peripheral Synchronous can be considered byte-wide
Slave Parallel
which is used primarily for daisy-chained devices. The seventh mode, called Express mode, is an additional slave
mode that allows high-speed parallel configuration. The
coding for mode selection is shown in Table 11.
Note that the smallest package, VQ64, only supports the
Master Serial, Slave Serial, and Express modes.A detailed
description of each configuration mode, with timing information, is included later in this data sheet. During configuration, some of the 1/0 pins are used temporarily for the
configuration process. All pins used during configuration
are shown in Table 14 on page 266.
Master Modes
The three Master modes use an internal oscillator to generate a Configuration Clock (CCLK) for driving potential slave
devices. They also generate address and timing for external PROM(s) containing the configuration data.
Master Parallel (Up or Down) modes generate the CCLK
signal and PROM addresses and receive byte parallel data.
The data is internally serialized into the FPGA data-frame
format. The up and down selection generates starting
addresses at either zero or 3FFFF, for compatibility with different microprocessor addressing conventions. The Master
Serial mode generates CCLK and receives the configura-
December 10, 1997 (Version 5.0)
- - -
------
~XILlNX
tion data in serial form from a Xilinx serial-configuration
PROM.
CCLK speed is selectable as 1 MHz (default), 6 MHz, or 12
MHz. Configuration always starts at the default slow frequency, then can switch to the higher frequency during the
first frame. Frequency tolerance is -50% to +50%.
Peripheral Modes
The two Peripheral modes accept byte-wide data from a
bus. A RDY/BUSY status is available as a handshake signal. In Asynchronous Peripheral mode, the internal oscillator generates a CCLK burst signal that serializes the bytewide data. CCLK can also drive slave devices. In the synchronous mode, an externally supplied clock input to CCLK
serializes the data.
Slave Serial Mode
In Slave Serial mode, the FPGA receives serial configuration data on the rising edge of CCLK and, after loading its
configuration, passes additional data out, resynchronized
on the. next falling edge of CCLK.
Multiple slave devices with identical configurations can be
wired with parallel DIN inputs. In this way, multiple devices
can be configured simultaneously.
Serial Daisy Chain
Multiple devices with different configurations can be connected together in a "daisy chain," and a single combined
bitstream used to configure the chain of slave devices.
To configure a daisy chain of devices, wire the CCLK pins
of all devices in parallel, as shown in Figure 29 on page
256. Connect the DOUT of each device to the DIN of the
next. The lead or master FPGA and following slaves each
passes resynchronized configuration data coming from a
single source. The header data, including the length count,
is passed through and is captured by each FPGA when it
recognizes the 0010 preamble. Following the length-count
data, each FPGA outputs a High on DOUT until it has
received its required number of data frames.
After an FPGA· has received its configuration data, it
passes on any additional frame start bits and configuration
data on DOUT. When the total number of configuration
clocks applied after memory initialization equals the value
of the 24-bit length count, the FPGAsbegin the start-up
sequence and become operational together. FPGA I/O are
normally released two CCLK cycles after the last configuration bit is received. Figure 26 on page 251 shows the startup timing for an XC5200-Series device.
The daisy-chained bitstream is not simply a concatenation
of the individual bitstreams. The PROM file formatter must
be used to combine the bitstreams for a daisy-chained configuration.
December 10, 1997 (Version 5.0)
Multi-Family Daisy Chain
All Xilinx FPGAs of the XC2000, XC3000, XC4000, and
XC5200 Series use a compatible bitstream format and can,
therefore, be connected in a daisy chain in an arbitrary
sequence. There is, however, one limitation. If the chain
contains XC5200-Series devices, the master normally cannot be an XC2000 or XC3000 device.
The reason for this rule is shown in Figure 26 on page 251.
Since all devices in the chain store the same length count
value and generate or receive one common sequence of
CCLK pulses, they all recognize length-count match on the
same CCLK edge, as indicated on the left edge of
Figure 26. The master device then generates additional
CCLK pulses until it reaches its finish point F. The different
families generate or require different numbers of additional
CCLK pulses until they reach F. Not reaching F means that
the device does not really finish its configuration, although
DONE may have gone High, the outputs became active,
and the internal reset was released. For the XC5200Series device, not reaching F means that readback cannot
be initiated and most boundary scan instructions cannot be
used.
The user has some control over the relative timing of these
events and can, therefore, make sure that they occur at the
proper time and the finish point F is reached. Timing is
controlled using options in the bitstream generation software.
XC5200 devices always have the same number of CCLKs
in the power up delay, independent of the configuration
mode, unlike the XC3000/XC4000 Series devices. To guarantee all devices in a daisy chain have finished the powerup delay, tie the INIT pins together, as shown in Figure 28.
XC3000 Master with an XCS200-Series Slave
Some designers want to use an XC3000 lead device· in
peripheral mode and have the I/O pins of the XC5200Series devices all available for user I/O. Figure 23 provides
a solution for that case.
This solution requires one CLB, one lOB and pin, and an
internal oscillator with a frequency of up to 5 MHz as a
clock source. The XC3000 master device must be configured with late Internal Reset, which is the default option.
One CLB and one lOB in the lead XC3000-family device
are used to generate the additional CCLK pulse required by
the XC5200-Series devices. When the lead device
removes the internal RESET signal, the 2-bit shift register
responds to its clock input and generates an active Low
output Signal for the duration of the subsequent clock
period. An external connection between this output and
CCLK thus creates the extra CCLK pulse.
-
4-247
I
XC5200 Series Field Programmable Gate Arrays
Pseudo Daisy Chain
Output
...,-~_
Reset
o 0
1
0
1
1
o 1
o 1
-' Connected
toCCLK
Active Low Output
Active High Output
etc
X5223
Figure 23: CCLK Generation for XC3000 Master
Driving an XC5200-Series Slave
Express Mode
Express mode is similar to Slave Serial mode, except the
data is presented in parallel format, and is clocked into the
target device a byte at a time rather than a bit at a time.
The data is loaded in parallel into eight different columns: it
is not internally serialized. Eight bits of configuration data
are loaded with every CCLK cycle, therefore this configuration mode runs at eight times the data rate of the other six
modes. In this mode the XCS200 family is capable of supporting a CCLK frequency of 10 MHz, which is equivalent to
an 80 MHz serial rate, because eight bits of configuration
data are being loaded per CCLK cycle. An XCS210 in the
Express mode, for instance, can be configured in about 2
ms. The Express mode does not support CRC error checking, but does support constant-field error checking. A
length count is not used in Express mode.
In the Express configuration mode, an external signal
drives the CCLK input(s). The first byte of parallel configuration data must be available at the 0 inputs of the FPGA
devices a short set-up time before the second rising CCLK
edge. Subsequent data bytes are clocked in on each consecutive rising CCLK edge. See Figure 39 on page 265.
Bitstream generation currently generates a bitstream sufficient to program in all configuration modes except Express.
Extra CCLK cycles are necessary to complete the configuration, since in this mode data is read at a rate of eight bits
per CCLK cycle instead of one bit per cycle. Normally the
entire start-up sequence requires a number of bits that is
equal to the number of CCLK cycles needed. An additional
five CCLKs (equivalent to 40 extra bits) will guarantee completion of configuration, regardless of the start-up options
chosen.
Multiple devices with different configurations can be connected together in a pseudo daisy chain, provided that all of
the devices are in Express mode. A single combined bitstream is used to configure the chain of Express mode
devices, but the input data bus must drive 00-07 of each
device. Tie High the CS1 pin of the first device to be configured, or leave it floating in the XC5200 since it has an
internal pull-up. Connect the OOUT pin of each FPGA to
the CS1 pin of the next device in the chain. The 00-07
inputs are wired to each device in parallel. The DONE pins
are wired together, with one or more internal DONE pullups activated. Alternatively, a 4.7 kQ external resistor can
be used, if desired. (See Figure 38 on page 264.) CCLK
pins are tied together.
The requirement that all DONE pins in a daisy chain be
wired together applies only to Express mode, and only if all
devices in the chain are to become active simultaneously.
All devices in Express mode are synchronized to the DONE
pin. User I/O for each device become active after the
DONE pin for that device goes High. (The exact timing is
determined by options to the bitstream generation software.) Since the DONE pin is open-drain and does not
drive a High value, tying the DONE pins of all devices
together prevents all devices in the chain from going High
until the last device in the chain has completed its configuration cycle.
The status pin OOUT is pulled LOW two internal-oscillator
cycles (nominally 1 MHz) after INIT is recognized as High,
and remains Low until the device's configuration memory is
full. Then OOUT is pulled High to signal the next device in
the chain to accept the configuration data on the 07-00
bus. All devices receive and recognize the six bytes of preamble and length count, irrespective of the level on CS1;
but subsequent frame data is accepted only when CS1 is
High and the device's configuration memory is not already
full.
Setting CCLK Frequency
For Master modes, CCLK can be generated in one of three
frequencies. In the default slow mode, the frequency is
nominally 1 MHz. In fast CCLK mode, the frequency is
nominally 12 MHz. In medium CCLK mode, the frequency
is nominally 6 MHz. The frequency range is -SO% to +SO%.
The frequency is selected by an option when running the
bitstream generation software. If an XCS200-Series Master is driving an XC3000- or XC2000-family slave, slow
CCLK mode must be used. Slow mode is the default.
Multiple slave devices with identical configurations can be
wired with parallel 00-07 inputs. In this way, multiple
devices can be configured Simultaneously.
4-248
December 10, 1997 (Version S.O)
~-~--------------
- - - -
~XILINX
Table 12: XC5200 Bitstream Format
Data Type
Fill Byte
Preamble
Length Counter
Fill Byte
Start Byte
Data Frame'
Cyclic Redundancy Check or
Constant Field Check
Fill Nibble
Extend Write Cycle
Postamble
Fill Bytes (30)
Start-Up Byte
Value
11111111
11110010
COUNT(23:0)
11111111
11111110
DATA(N-1:0)
CRC(3:0) or
0110
1111
FFFFFF
11111110
FFFF ... FF
FF
Occurrences
Once per bitstream
Once per data
frame
Table 13: Internal Configuration Data Structure
Device
Once per device
Once per bitstream
*Bits per Frame (N) depends on device size, as described for
table 11.
Data Stream Format
The data stream ("bitstream") format is identical for all configuration modes, with the exception of Express mode. In
Express mode, the device becomes active when DONE
goes High, therefore no length count is required. Additionally, CRC error checking is not supported in Express mode.
The data stream formats are shown in Table 12. Express
mode data is shown with DO at the left and 07 at the right.
For all other modes, bit-serial data is read from left to right,
and byte-parallel data is effectively assembled from this
serial bitstream, with the first bit in each byte assigned to
DO.
The configuration data'stream begins with a string of eight
ones, a preamble code, followed by a 24-bit length count
and a separator field of ones (or 24 fill bits, in Express
mode). This header is followed by the actual configuration
data in frames. The length and number of frames depends
on the device type (see Table 13). Each frame begins with
a start field and ends with an error check. In all modes
except Express mode, a postamble code is required to signal the end of data for a single device. In all cases, additional start-up bytes of data are required to provide four
clocks for the startup sequence at the end of configuration.
Long daisy chains require additional startup bytes to shift
the last data through the chain. All startup bytes are don'tcares; these bytes are not included in bitstreams created by
the Xilinx software.
In Express mode, only non-CRC error checking is supported. In all other modes, a selection of CRC or non-CRC
error checking is allowed by the bitstream generation software. The non-CRC error checking tests for a designated
end-of-frame field for each frame. For CRC error checking,
the software calculates a running CRC and inserts a
unique four-bit partial check at the end of each frame. The
11-bit CRC check of the last frame of an FPGA includes the
last seven data bits.
December 10,1997 (Version 5.0)
Detection of an error results in the suspension of data loading and the pulling down of the INIT pin. In Master modes,
CCLK and address signals continue to operate externally.
The user must detect TNTf and initialize a new configuration
by pulsing the PROGRAM pin Low or cycling Vcc.
VersaBlock
Array
PROM
Size
(bits)
Xilinx
Serial PROM
Needed
XC5202
8x8
42,416
XC1765D
XC5204
10 x 12
70,704
XC17128D
14 x 14
XC5206
106,288
XC17128D
18 x 18
165,488
XC17256D
XC521 0
237,744
XC17256D
XC5215
22 x22
Bits per Frame = (34 x number of Rows) + 28 for the top + 28 for
the bottom + 4 splitter bits + 8 start bits + 4 error check bits + 4 fill
bits * + 24 extended write bits
= (34 x number of Rows) + 100
* In the XC5202 (8 x 8), there are 8 fill bits per frame, not 4
Number of Frames = (12 x number of Columns) + 7 for the left
edge + 8 for the right edge + 1 splitter bit
= (12 x number of Columns) + 16
Program Data = (Bits per Frame x Number of Frames) + 48
header bits + 8 postamble bits + 240 fill bits + 8 start-up bits
= (Bits per Frame x Number of Frames) + 304
PROM Size = Program Data
Cyclic Redundancy Check (CRC) for
Configuration and Readback
The Cyclic Redundancy Check is a method of error detection in data transmission applications. Generally, the transmitting system performs a calculation on the serial
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits. The receiving system
performs an identical calculation on the bitstream and compares the result with the received checksum.
Each data frame of the configuration bitstream has four
error bits at the end, as shown in Table 12. If a frame data
error is detected during the loading of the FPGA, the configuration process with a potentially corrupted bitstream is
terminated. The FPGA pulls the INIT pin Low and goes into
a Wait state.
During Readback, 11 bits of the 16-bit checksum are added
to the end of the Readback data stream. The checksum is
computed using the CRC-16 CCITT polynomial, as shown
in Figure 24. The checksum consists of the 11 most significant bits of the 16-bit code. A change in the checksum
indicates a change in the Readback bitstream. A comparison to a previous checksum is meaningful only if the readback data is independent of the current device state. CLB
outputs should not be included (Read Capture option not
used). Statistically, one error out of 2048 might go undetected.
4-249
I
XC5200 Series Field Programmable Gate Arrays
Initialization
This phase clears the configuration memory and establishes the configuration mode.
2 3 4 5 6 7 8 9 10 11 12 13 14
I
I
SERIAL DATA IN
Polynomial: X16 + X15
+ X2 + 1
i
I
I
I
I
r- - --- -- ----- ---- ---- ---- ___ I
I
Readback Data Stream
Figure 24: Circuit for Generating CRC-16
Configuration Sequence
There are four major steps in the XC5200-Series power-up
configuration sequence.
•
•
•
•
Power-On Time-Out
Initialization
Configuration·
Start-Up
The full process is illustrated in Figure 25.
Power-On Time-Out
An internal power-on reset circuit is triggered when power
is applied. When Vee reaches the voltage at which portions
of the FPGA begin to operate (i.e., performs a write-andread test of a sample pair of configuration memory bits), the
programmable I/O buffers are 3-stated with active highimpedance pull-up resistors. A time-out delay - nominally
4 ms - is ini.tiated to allow the power-supply voltage to stabilize. For correct operation the power supply must reach
Vedmin) by the end of the time-out, and must not dip below
it thereafter.
The configuration memory is cleared at the rate of one
frame per internal clock cycle (nominally 1 MHz). An opendrain bidirectional signal, INIT, is released when the configuration memory is completely cleared. The device then
tests for the absence of an external active-low level on INIT.
The mode lines are sampled two internal clock cycles later
(nominally 2 I!s).
The master device waits an additional 32 I!s to 256 I!s
(nominally 64-128I!s) to provide adequate time for all of the
slave devices to recognize the release of INIT as well. Then
the master device enters the Configuration phase.
n
Boundary Scan
Instructions
Available:
:::erate
One Time-Out Pulse
of4ms
1--------'
EXTEST*
SAMPLE/PRELOAD·
BYPASS
CONFIGURE·
("only when PROGRAM _ High)
"'5"
~
o
MasterCCLK
Goes Active after
50 to 250j..ls
g
"J
"
i
19
No
There is no distinction between master and slave modes
with regard to the time-out delay. Instead, the INIT line is
used to ensure that all daisy-chained devices have completed initialization. Since XC2000 devices do not have this
signal, extra care must be taken to guarantee proper operation when daisy-chaining them with XC5200 devices. For
proper operation with XC3000 devices, the RESET signal,
which is used in XC3000 to delay configuration, should be
connected to INIT.
If the time-out delay is insufficient, configuration should be
delayed by holding the INIT pin Low until the power supply
has reached operating levels.
This delay is applied only on power-up. It is not applied
when reconfiguring an FPGA by pulsing the PROGRAM pin
Low. During all three phases - Power-on, Initialization,
and Configuration - DONE is held Low; HDC, LDC, and
INIT are active; DOUT is driven; and all I/O buffers are disabled.
4-250
SAMPLEfPRELOAD
BYPASS
Conflg-
uration
memory
No
Full
y"
Pass
Configuration
Datata DQUT
CCLK
CO~~n~iha's
No
Count
EXTEST
SAMPLE PRELOAD
BYPASS
USER 1
If Boundary Scan
USER 2
is Seleoted
CONFIGURE
READBACK
Figure 25: Configuration Sequence
December 10, 1997 (Version 5.0)
~XILINX
CCLK
XC2000
F == Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
XC3000
Heavy lines describe
default timing
I
XC4000E/EX
XC52001
CCLK_NOSYNC
XC4000ElEX
XC52001
CCLK_SYNC
XC4000ElEX
XC52001
UCLK_NOSYNC
XC4000ElEX
XC52001
UCLK_SYNC
--'------l~I:~=-~+-
UCLK Period
X6700
Figure 26: Start-up Timing
December 10. 1997 (Version 5.0)
4-251
XC5200 Series Field Programmable Gate Arrays
Configuration
Start-Up
The length counter begins counting immediately upon
entry into the configuration state. In slave-mode operation it
is important to wait at least two cycles of the internal 1-MHz
clock oscillator after INIT is recognized before toggling
CCLK and feeding the serial bitstream. Configuration will
not begin until the internal configuration logic reset is
released, which happens two cycles after INIT goes High.
A master device's configuration is delayed from 32 to 256
Ils to ensure proper operation with any slave devices driven
by the master device.
Start-up is the transition from the configuration process to
the intended user operation. This transition involves a
change from one clock source to another, and a change
from interfacing parallel or serial configuration data where
most outputs are 3-stated, to normal operation with 1/0 pins
active in the user-system. Start-up must make sure that
the user-logic 'wakes up' gracefully, that the outputs
become active without causing contention with the configuration signals, and that the internal flip-flops are released
from the global Reset at the right time.
The 0010 preamble code, included for all modes except
Express mode, indicates that the following 24 bits represent the length count. The length count is the total number
of configuration clocks needed to load the complete configuration data. (Four additional configuration clocks are
required to complete the configuration process, as discussed below.) After the preamble and the length count
have been passed through to all devices in the daisy chain,
DOUT is held High to prevent frame start bits from reaching
any daisy-chained devices. In Express mode, the length
count bits are ignored, and DOUT is held Low, to disable
the next device in the pseudo daisy chain.
Figure 26 describes start-up timing for the three Xilinx families in detail. Express mode configuration always uses
either CCLK_SYNC or UCLK_SYNC timing, the other configuration modes can use any of the four timing sequences.
A specific configuration bit, early in the first frame of a master device, controls the configuration-clock rate and can
increase it by a factor of eight. Therefore, if a fast configuration clock is selected by the bitstream, the slower clock
rate is used until this configuration bit is detected.
Each frame has a start field followed by the frame-configuration data bits and a frame error field. If a frame data error
is detected, the FPGA halts loading, and signals the error
by pulling the open-drain INIT pin Low. After all configuration frames have been loaded into an FPGA, DOUT again
follows the input data so that the remaining data is passed
on to the next device. In Express mode, when the first
device is fully programmed, DOUT goes High to enable the
next device in the chain.
Delaying Configuration After Power-Up
To delay master mode configuration after power-up, pull the
bidirectional INIT pin Low, using an open-collector (opendrain) driver. (See Figure 13.)
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of master mode configuration
causes the FPGA to wait after completing the configuration
memory clear operation. When INIT is no longer held Low
externally, the device determines its configuration mode by
capturing its mode pins, and is ready to start the configuration process. A master device waits up to an additional 250
Ils to make sure that any slaves in the optional daisy chain
have seen that INIT is High.
4-252
To access the internal start-up signals, place the STARTUP
library symbol.
Start-up Timing
Different FPGA families have different start-up sequences.
The XC2000 family goes through a fixed sequence. DONE
goes High and the internal global Reset is de-activated one
CCLK period after the 1/0 become active.
The XC3000A family offers some flexibility. DONE can be
programmed to go High one CCLK period before or after
the 1/0 become active. Independent of DONE, the internal
global Reset is de-activated one CCLK period before or
after the 1/0 become active.
The XC4000IXC5200 Series offers additional flexibility.
The three events - DONE going High, the internal Reset
being de-activated, and the user 1/0 going active - can all
occur in any arbitrary sequence. Each of them can occur
one CCLK period before or after, or simultaneous with, any
of the others. This relative timing is selected by means of
software options in the bitstream generation software.
The default option, and the most practical one, is for DONE
to go High first, disconnecting the configuration data source
and avoiding any contention when the lias become active
one clock later. Reset is then released another clock
period later to make sure that user-operation starts from
stable internal conditions. This is the most common
sequence, shown with heavy lines in Figure 26, but the
designer can modify it to meet particular requirements.
Normally, the start-up sequence is controlled by the internal
device oscillator output (CCLK), which is asynchronous to
the system clock.
XC4000IXC5200 Series offers another start-up clocking
option, UCLK_NOSYNC. The three events described
above need not be triggered by CCLK. They can, as a configuration option, be triggered by a user clo.ck. This means
that the device can wake up in synchronism with the user
system.
December 10, 1997 (Version 5.0)
~XILINX
When the UCLK_SYNC option is enabled, the user can
externally hold the open-drain DONE output Low, and thus
stall all further progress in the start-up sequence until
DONE is released and has gone High. This option can be
used to force synchronization of several FPGAs to a common user clock, or to guarantee that all devices are successfully configured before any I/Os go active.
If either of these two options is selected, and no user clock
is specified in the design or attached to the device, the chip
could reach a point where the configuration of the device is
complete and the Done pin is asserted, but the outputs do
not become active. The solution is either to recreate the
bitstream specifying the start-up clock as CCLK, or to supply the appropriate user clock.
ship between CCLK and the user clock. This arbitration
causes an unavoidable one-cycle uncertainty in the timing
of the rest of the start-up sequence.
DONE Goes High to Signal End of Configuration
In all configuration modes except Express mode, XC5200Series devices read the expected length count from the bitstream and store it in an internal register. The length count
varies according to the number of devices and the composition of the daisy chain. Each device also counts the number of CCLKs during configuration.
Two conditions have to be met in order for the DONE pin to
go high:
o
the chip's internal memory must be full, and
the configuration length count must be met, exactly.
Start-up Sequence
o
The Start-up sequence begins when the configuration
memory is full, and the total number of configuration clocks
received since INIT went High equals the loaded value of
the length count.
This is important because the counter that determines
when the length count is met begins with the very first
CCLK, not the first one after the preamble.
The next rising clock edge sets a flip-flop QO, shown in
Figure 27. QO is the leading bit of a 5-bit shift register. The
outputs of this register can be programmed to control three
events.
•
o
o
The release of the open-drain DONE output
The change of configuration-related pins to the user
function, activating all lOBs.
The termination of the global SeVReset initialization of
all CLB and lOB storage elements.
The DONE pin can also be wire-ANDed with DONE pins of
other FPGAs or with other external signals, and can then
be used as input to bit Q3 of the start-up register. This is
called "Start-up Timing Synchronous to Done In" and is
selected by either CCLK_SYNC or UCLK_SYNC.
When DONE is not used as an input, the operation is called
"Start-up Timing Not Synchronous to DONE In," and is
selected by either CCLK_NOSYNC or UCLK_NOSYNC.
As a configuration option, the start-up control register
beyond QO can be clocked either by subsequent CCLK
pulses or from an on-chip user net called STARTUP.CLK.
These signals can be accessed by placing the STARTUP
library symbol.
Start-up from CClK
If CCLK is used to drive the start-up, QO through Q3 provide the timing. Heavy lines in Figure 26 show the default
timing, which is compatible with XC2000 and XC3000
devices using early DONE and late Reset. The thin lines
indicate all other possible timing options.
Start-up from a User Clock (STARTUP.ClK)
When, instead of CCLK, a user-supplied start-up clock is
selected, Q1 is used to bridge the unknown phase relation-
December 10, 1997 (Version 5.0)
Therefore, if a stray bit is inserted before the preamble, or
the data source is not ready at the time of the first CCLK,
the internal counter that holds the number of CCLKs will be
one ahead of the actual number of data bits read. At the
end of configuration, the configuration memory will be full,
but the number of bits in the internal counter will not match
the expected length count.
As a consequence, a Master mode device will continue to
send out CCLKs until the internal counter turns over to
zero, and then reaches the correct length count a second
time. This will take several seconds [2 24 * CCLK periodjwhich is sometimes interpreted as the device not configuring at all.
If it is not possible to have the data ready at the time of the
first CCLK, the problem can be avoided by increasing the
number in the length count by the appropriate value.
In Express mode, there is no length count. The DONE pin
for each device goes High when the device has received its
quota of configuration data. Wiring the DONE pins of several devices together delays start-up of all devices until all
are fully configured.
Note that DONE is an open-drain output and does not go
High unless an internal pull-up is activated or an external
pull-up is attached. The internal pull-up is activated as the
default by the bitstream generation software.
Release of User VO After DONE Goes High
By default, the user I/O are released one CCLK cycle after
the DONE pin goes High. If CCLK is not clocked after
DONE goes High, the outputs remain in their initial state3-stated, with a 20 kf.l - 100 kQ pull-up. The delay from
DONE High to active user I/O is controlled by an option to
the bitstream generation software.
4-253
I
XC5200 Series Field Programmable Gate Arrays
03---,
STARTUP
,----01/Q4
Q2-
~~ONE
* hhhi'--------------------
lOBs QPERATIONAL PEA CONFIGURATION
* rt-t-'~----~-i>V>--"=I
~)---------- ~~~~~~~~~~;Lg~S/LATCHES
L---_ _ _ STARTUP.GR
~
~O;:~3~~~DS~~~~~~T~~s~~MBOL
, - - - - STARTUP.GTS
LlBAARIESGUIDE)
GTSINVERT
~
~}-,A-Bl-E--.--------1___
0,
,--------------J
0
GLOBAL 3-STATE OF ALL lOB,
~ II-------------<~
Rr--------,
*+-~r_~--------~t,,>_-~------------~---~~DONE
"FINISHED"
ENABLES BOUNDARY
SCAN, AEADBACK AND
CONTROLS THE OSCILLATOR
00
FUll f " " l - 'S- - -Q,I
----L-I
LENGTH COUNT
01
.-+---1'--D
Q f----n-- D
Q
~~,--D
O~_D
,
*
CLEAR MEMORY
04
03
02
r-[>K
0-
_>K
--t--~I_--r--If__--y-~o---_+--r-~>__----+_--eI>---+_----r-_---'
CClK - -......--~O')
STARTUP.ClK _ _ _ _ _
--1X".)H-....- - - -....- - - - - - -....- - -.....
USER NET
CONFIGURATION BIT OPTIONS SELECTED BY USER
Figure 27: Start-up Logic
Release of Global Reset After DONE Goes High
By default, Global Reset (GR) is released two CCLK cycles
after the DONE pin goes High. If CCLK is not clocked twice
after DONE goes High, all flip-flops are held in their initial
reset state. The delay from DONE High to GR inactive is
controlled by an option to the bitstream generation software.
Configuration Complete After DONE Goes High
Three full CCLK cycles are required after the DONE pin
goes High, as shown in Figure 26 on page 251. If CCLK is
not clocked three times after DONE goes High, readback
cannot be initiated and most boundary scan instructions
cannot be used.
Configuration Through the Boundary Scan
Pins
XC5200-Series devices can be configured through the
boundary scan pins.
4-254
For detailed information, refer to the Xilinx application note
XAPP017, "Boundary Scan in XC4000 and XC5200
Devices:'
Readback
The user can read back the content of configuration memory and the level of certain internal nodes without interfering with the normal operation of the device.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs.
Note that in XC5200-Series devices, configuration data is
not inverted with respect to configuration as it is in XC2000
and XC3000 families.
Readback of Express. mode bitstreams results in data that
does not resemble the original bitstream, because the bitstream format differs from other modes.
December 10, 1997 (Version 5.0)
~XILINX
XC5200-Series Readback does not use any dedicated
pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA,
RDBK.RIP and RDBK.CLK) that can be routed to any lOB.
To access the internal Readback signals, place the READBACK library symbol and attach the appropriate pad symbols, as shown in Figure 28.
After Readback has been initiated by a Low-to-High transition on RDBK.TRIG, the RDBK.RIP (Read In Progress)
output goes High on the next rising edge of RDBK.CLK.
Subsequent rising edges of this clock shift out Readback
data on the RDBK.DATA net.
Readback data does not include the preamble, but starts
with five dummy bits (all High) followed by the Start bit
(Low) of the first frame. The first two data bits of the first
frame are always High.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RDBK.RIP returns Low.
IF UNCONNECTED.
DEFAULT IS CClK
~
ClK
MDOl'r----"':RE"'AD:o.:-T",RIG""G""ER'---I
Figure 28: Readback Schematic Example
Readback Options
Readback options are: Read Capture, Read Abort, and
Clock Select. They are set with the bitstream generation
software.
Read Capture
When the Read Capture option is selected, the read back
data stream includes sampled values of CLB and lOB signals. The rising edge of RDBK.TRIG latches the inverted
values of the CLB outputs and the lOB output and input sigNote that while the bits describing configuration
nals.
(interconnect and function generators) are not inverted, the
CLB and lOB output signals are inverted.
When the Read Capture option is not selected, the values
of the capture bits reflect the configuration data originally
written to those memory locations.
The readback signals are located in the lower-left corner of
the device.
December 10, 1997 (Version 5.0)
Read Abort
When the Read Abort option is selected, a High-to-Low
transition on RDBK.TRIG terminates the read back operation and prepares the logic to accept another trigger.
After an aborted readback, additional clocks (up to one
read back clock per configuration frame) may be required to
re-initialize the control logic. The status of readback is indicated by the output control net RDBK.RIP. RDBK.RIP is
High whenever a readback is in progress.
Clock Select
CCLK is the default clock. However, the user can insert
another clock on RDBK.CLK. Readback control and data
are clocked on rising edges of RDBK.CLK. If readback
must be inhibited for security reasons, the read back control
nets are simply not connected.
Violating the Maximum High and LowTime
Specification for the Readback Clock
The readback clock has a maximum High and Low time
specification. In some cases, this specification cannot be
met. For example, if a processor is controlling readback, an
interrupt may force it to stop in the middle of a read back.
This necessitates stopping the clock, and thus violating the
specification.
The specification is mandatory only on clocking data at the
end of a frame prior to the next start bit. The transfer mechanism will load the data to a shift register during the last six
clock cycles of the frame, prior to the start bit of the following frame. This loading process is dynamic, and is the
source of the maximum High and Low time requirements.
Therefore, the specification only applies to the six clock
cycles prior to and including any start bit, including the
clocks before the first start bit in the readback data stream.
At other times, the frame data is already in the register and
the register is not dynamic. Thus, it can be shifted out just
like a regular shift register.
The user must precisely calculate the location of the readback data relative to the frame. The system must keep
track of the position within a data frame, and disable interrupts before frame boundaries. Frame lengths and data
formats are listed in Table 12 and Table 13.
Readback with the XChecker Cable
The XChecker Universal Download/Readback Cable and
Logic Probe uses the read back feature for bitstream verification. It can also display selected internal signals on the
PC or workstation screen, functioning as a low-cost in-circuit emulator.
4-255
I
XC5200 Series Field Programmable Gate Arrays
Configuration Timing
There is an internal delay of 0.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge.
The seven configuration modes are discussed in detail in
this section. Timing specifications are included.
Slave Serial Mode
Figure 29 shows a full master/slave system. An XC5200Series device in Slave Serial mode should be connected as
shown in the third device from the left.
In Slave Serial mode, an external signal drives the CCLK
input of the FPGA. The serial configuration bitstream must
be available at the DIN input of the lead FPGA a short
setup time before each rising CCLK edge.
Slave Serial mode is selected by a <111> on the mode pins
(M2, M1, MO). Slave Serial is the default mode if the mode
pins are left unconnected, as they have weak pull-up resistors during configuration.
The lead FPGA then presents the preamble data-and all
data that overflows the lead device-on its DOUT pin.
NOTE:
M2, M1, MO can be shorted
t 0 VCC'f
I no t used as 110
NOTE:
M2, M1, MO can be shorted
to G roun d if not used as I/O
VCC
N/C
'.7 Kat Kof f•.7t
II
DIN
MASTER
XC1700D
4.7 KQ
SERIAL
ClK
DATA
CCLK
DIN
PROGRAM
Mi O IVII
-
CEO
RESET/DE
INIT
+5 V
I
-,---.
DONE
I (low Resel Opllon Used)
CCLK
XC3100A
SLAVE
PROGRAM
DONE
PWRDN
Dour -
DIN
XC4000EIEX,
XC5200
SLAVE
vpp~
CE
lDC
DOUT
CCLK
VCC
XC5200
I
t Kaf f'·7 K1
N/C- M2
DOUT
,---..
'.7Kn
MOM1
MOM1
M2
I
,---.. RESET
~~
1
I",T~
DIP
I
PROGRAM
X9003
Figure 29: Master/Slave Serial Mode Circuit Diagram
DIN~
"'" -
Bltn
~
Bitn + 1
LCi)'OC'1=@,=:i '----~--.---®-5-T-C-CL----}-==~~~--~
-------~t
DOUT
(Output)
@,~,
l=®,~,?_------==>K
Bit n - 1
Bit n
X5379
CCLK
Note:
Description
DIN setup
DIN hold
DIN to DOUT
High time
Low time
Frequency
1
2
3
4
5
Symbol
T DCC
TCCD
Tcco
TCCH
TCCL
Fcc
Min
20
Max
0
30
45
45
10
Units
ns
ns
ns
ns
ns
MHz
Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
Figure 30: Slave Serial Mode Programming Switching Characteristics
4-256
December 10,1997 (Version 5.0)
~XILINX
The value increases from a nominal 1 MHz, to a nominal 12
MHz. Be sure that the serial PROM and slaves are fast
enough to support this data rate. The Medium ConfigRate
option changes the frequency to a nominal 6 MHz.
XC2000, XC3000/A, and XC3100A devices do not support
the Fast or Medium ConfigRate options.
Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the FPGA DIN input.
Each rising edge of the CCLK output increments the Serial
PROM internal address counter. The next data bit is put on
the SPROM data output, connected to the FPGA DIN pin.
The lead FPGA accepts this data on the subsequent rising
CCLK edge.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output after configuration. Using DONE can also avoid contention on DIN,
provided the early DONE option is invoked.
The lead FPGA then presents the preamble data-and all
data that overflows the lead device-on its DOUT pin.
There is an internal pipeline delay of 1.5 CCLK periods,
which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
Figure 29 on page 256 shows a full master/slave system.
The leftmost device is in Master Serial mode.
Master Serial mode is selected by a <000> on the mode
pins (M2, M1 , MO).
In the bitstream generation software, the user can specify
Fast ConfigRate, which, starting several bits into the first
frame, increases the CCLK frequency by a factor of twelve.
I
eeLK
(Output)
o
Serial Data In
Serial DOUT
TCKDS
n+2
n+1
n-3
(Output) _ _ _ _ _ _J
n-2
n-1
'-_ _ _ _ _ _- - ' '--_ _ _ _ _ _-J \._ _ _ _ _ _ _J
X3223
CCLK
Notes.
Description
DIN setup
DIN hold
1
2
Symbol
I T DSCK
I TcKDs
Min
20
0
Max
Units
ns
ns
1. At power-up, Vee must nse from 2.0 V to Vee min In less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until Vee is valid.
2. Master Serial mode timing is based on testing in slave mode.
Figure 31 : Master Serial Mode Programming Switching Characteristics
December 10, 1997 (Version 5.0)
4-257
XC5200 Series Field Programmable Gate Arrays
The PROM address pins can be incremented or decremented, depending on the mode pin settings. This option
allows the FPGA to share the PROM with a wide variety of
microprocessors and microcontrollers. Some processors
must boot from the bottom of memory (all zeros) while others must boot from the top. The FPGA is flexible and can
load its configuration bitstream from either end of the memory.
Master Parallel Modes
In the two Master Parallel modes, the lead FPGA directly
addresses an industry-standard byte-wide EPROM, and
accepts eight data bits just before incrementing or decrementing the address outputs.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data-and all data that overflows the lead device-on its DOUT pin. There is an internal delay of 1.5 CCLK periods, after the rising CCLK edge
that accepts a byte of data (and also changes the EPROM
address) until the falling CCLK edge that makes the LSB
(DO) of this byte appear at DOUT. This means that DOUT
changes on the falling CCLK edge, and the next FPGA in
the daisy chain accepts data on the subsequent rising
CCLKedge.
or
LI
W
~
MO
M1
Master Parallel Down mode is selected by a <110> on the
mode pins. The EPROM addresses start at 3FFFF and
decrement.
TO DIN OF OPTIONAL
DAISY-CHAINED FPGAS
HIGH
4.7Kn
Master Parallel Up mode is selected by a <100> on the
mode pins (M2, M1, MO). The EPROM addresses start at
00000 and increment.
Nt
N/C
M2
TO CCLK OF OPTIONAL
DAISY-CHAINED FPGAS
~
1
CCLK
-
NOTEMO can be shorted
to Ground if not used
DOUT
as 1/0.
VCC
4.7K0
INIT
A17
f---- .
A16
f---- .
A15
f----
A14
f---- .
A13
I-- .
~
A11 ~
A10 ~
A12
~
MO
4
EPROM
(8Kx 8)
(OR LARGER)
A12
I
M2
DOUT
DIN
-
CCLK
USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT BETWEEN
ALTERNATIVE CONFIGURATIONS
XC5200/
XC4000ElEX
SLAVE
---
A11
PROGRAM
A10
PROGRAM
A9r----- A9
r
V-V--
07
A8r----- A8
06
A7r----- A7
05
A6r----- A6
06 " "
V--
04
A5r----- A5
05 " "
V-V--
03
A4r----- A4
02
A3r----- A3
V--
01
A 2 _ A2
V--
DO
A 1 _ A1
A O - AD
DATA BUS
I
M1
DONE -~
DE
~
CE
,--- DONE
INIT
~
07 " "
04 " "
03 " "
02 " "
01 " "
DO " "
8
PROGRAM
X9004
Figure 32: Master Parallel Mode Circuit Diagram
4-258
December 10, 1997 (Version 5.0)
- - - - - -
-~--~-~-~
~XIUNX
)K'
AO-A17
(output)
_ _ _ _ _ _ _ _ _A_d_d_re_ss_f_o_rB_y_te_n_ _ _ _ _ _ _
00-07
Address for Byte n + 1
l'-CDTRAC
Byte
®TDRC-RCLK
(output)
/
1
CCLK
(output)
OOUT
(output)
Byten-l
Description
CCLK
Note.
Symbol
X6078
Min
Max
Delay to Address valid
1
T RAC
0
200
Data setup time
2
ns
3
T DRC
T RcD
60
Data hold time
0
ns
Units
ns
1. At power-up, Vcc must rise from 2.0 V to Vcc min In less then 25 ms, otherwise delay configuration by pulling PROGRAM
Low until Vcc is Valid.
2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
Figure 33: Master Parallel Mode Programming Switching Characteristics
December 10, 1997 (Version 5.0)
4-259
I
XC5200 Series Field Programmable Gate Arrays
Synchronous Peripheral Mode
Synchronous Peripheral mode can also be considered
Slave Parallel mode. An external signal drives the CCLK
input(s) of the FPGA(s). The first byte of parallel configuration data must be available at the Data inputs of the lead
FPGA a short setup time before the rising CCLK edge.
Subsequent data bytes are clocked in on every eighth consecutive rising CCLK edge.
The same CCLK edge that accepts data, also causes the
ROY/BUSY output to go High for one CCLK period. The pin
name is a misnomer. In Synchronous Peripheral mode it is
really an ACKNOWLEDGE signal. Synchronous operation
does not require this response, but it is a meaningful signal
for test purposes. Note that ROY/BUSY is pulled High with
a high-impedance pullup prior to INIT going High.
The lead FPGA serializes the data and presents the preamble data (and all data that overflows the lead device) on
its DOUT pin. There is an internal delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
In order to complete the serial shift operation, 10 additional
CCLK rising edges are required after the last data byte has
been loaded, plus one more CCLK cycle for each daisychained device.
Synchronous Peripheral mode is selected by a <011> on
the mode pins (M2, M1, MO).
NOTE:
M2 can be shorted to Ground
if not used as I/O
N/C
r-'---.
I
CLOCK
DATA BUS
I
I MO M1
, CCLK
~=
DIN
XC5200
SYNCHRONOUS
PERIPHERAL
--RDY/BUSY
CO NTROL {
S IGNALS
I
M2
• CCLK
DOUT
4.7kQ
I I
MO M1
OPTIONAL
DAISY-CHAINED
FPGAs
DO•7
~
~
M2
8
"7
N/C
4.7 k£l
INIT
DONE I - -
DOUT
~
XC5200
SLAVE
-
INIT
DONE f - -
4.7kQ
PROGRAM
PROGRAM
, - - ' PROGRAM
X9005
Figure 34: Synchronous Peripheral Mode Circuit Diagram
4-260
December 10, 1997 (Version 5.0)
~XILINX
CCLK
I~r-----
·1
,
•
~
________~--~~.~~O~~~.1~T
~
OOUT
I
ROY/BUSY
----~y--\~---------------~---------~;--\~---X6096
Description
CCLK
Min
Max
Units
1
TIc
5
DO - D7 setup time
2
3
Toc
60
J.!s
ns
TCD
0
ns
CCLK High time
TCCH
50
ns
CCLK Low time
TCCL
60
DO - D7 hold time
CCLK Frequency
Notes:
Symbol
INIT (High) setup time
~~~
Fcc
ns
8
MHz
1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the
first data byte on the second rising edge of CCLK after INIT goes high. Subsequent data bytes are clocked in on every
eighth consecutive rising edge of CCLK..
2. The ROY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does
not require such a response.
3. The pin name ROY/BUSY is a misnomer. In synchronous peripheral mode this is really an ACKNOWLEDGE signal.
4.Note that data starts to shift out serially on the DOUT pin 0.5 CCLK. periods after it was loaded in parallel. Therefore,
additional CCLK pulses are clearly required after the last byte has been loaded.
Figure 35: Synchronous Peripheral Mode Programming Switching Characteristics
December 10, 1997 (Version 5.0)
4-261
I
XC5200 Series Field Programmable Gate Arrays
Asynchronous Peripheral Mode
The READY/BUSY handshake can be ignored if the delay
from anyone Write to the end of the next Write is guaranteed to be longer than 10 CCLK periods.
Write to FPGA
Asynchronous Peripheral mode uses the trailing edge of
the logic AND condition of WS and CSO being Low and RS
and CS1 being High to accept byte-wide data from a microprocessor bus. In the lead FPGA, this data is loaded into a
double-buffered UART-like parallel-to-serial converter and
is serially shifted into the internal logic.
Status Read
The logic AND condition of the CSO, CS1 and RS inputs
puts the device status on the Data bus.
•
•
•
The lead FPGA presents the preamble data (and all data
that overflows the lead device) on its OOUT pin. The ROY/
BUSY output from the lead FPGA acts as a handshake signal to the microprocessor. ROY/BUSY goes Low when a
byte has been received, and goes High again when the
byte-wide input buffer has transferred its information into
the shift register, and the buffer is ready to receive new
data. A new write may be started immediately, as soon as
the ROY/BUSY output has gone Low, acknowledging
receipt of the previous data. Write may not be terminated
until ROY/BUSY is High again for one CCLK period. Note
that ROY/BUSY is pulled High with a high-impedance pullup prior to INIT going High.
07 High indicates Ready
07 Low indicates Busy
DO through 06 go unconditionally High
It is mandatory that the whole start-up sequence be started
and completed by one byte-wide input. Otherwise, the pins
used as Write Strobe or Chip Enable might become active
outputs and interfere with the final byte transfer. If this
transfer does not occur, the start-up sequence is not completed all the way to the finish (point F in Figure 26 on page
251).
In this case, at worst, the internal reset is not released. At
best, Readback and Boundary Scan are inhibited. The
length-count value, as generated by the XACT step software, ensures that these problems never occur.
Although ROY/BUSY is brought out as a separate signal,
microprocessors can more easily read this information on
one of the data lines. For this purpose, 07 represents the
ROY/BUSY status when RS is Low, WS is High, and the
two chip select lines are both active.
The length of the BUSY signal depends on the activity in
the UART. If the shift register was empty when the new
byte was received, the BUSY signal lasts for only two CCLK
periods. If the shift register was still full when the new byte
was received, the BUSY signal can be as long as nine
CCLK periods.
Asynchronous Peripheral mode is selected by a <101> on
the mode pins (M2, M1, MO).
Note that after the last byte has been entered, only seven of
its bits are shifted out. CCLK remains High with OOUT
equal to bit 6 (the next-to-Iast bit) of the last byte entered.
NIC
!
NIC,;Q
4.7ko.
MO
8
DATA
BUS
ADDRESS
BUS
4.7ko'
1
M2
M1
MO
CGLK
[)o-7
M2
CCLK
1-
DAISY·CHAINED
,--ADDRESS
DECODE
LOGIC
Dour
r
FPGAs
DOUT
DIN
r-
CSO
XC5200
ASYNCHRONOUS
PERIPHERAL
1.7kn
JJj
OPTIONAL
1VCC
M1
NIC
XC52001
XC4000ElEX
SLAVE
CS1
AS
Ws
-
CONTROL
SIGNALS
RDY/BUSY
-
-
DONE
DONE
INIT
PROGRAM
REPROGRAM
INIT
~
PROGRAM
4.7kU
~
X9006
Figure 36:
4-262
Asynchronous Peripheral Mode Circuit Diagram
December 10, 1997 (Version 5.0)
~XlllNX
Wrileto LCA
Read Status
RS,CS1
WS,CS1
D7
DO·D7
CCLK
--'
_ _ _ _ _ _-:-_ _ _ _ _" " " " ' 1 - - - - - -
0
TBUSy---\l~1
r-------------
RDY/BUSY
. . . . . . . . . . __ • • __ .ot
DOUT
____J)(~______p_re_~~·O-US-B-~-e-o-6------J)(
07
x
00
)(
E
01
X6097
Description
Write
RDY
Notes:
Symbol
Min
Max
Effective Write time
(CSa, WS=Low; RS, CS1=High
1
TeA
100
Units
ns
DIN setup time
DIN hold time
RDY/BUSY delay after end of
Write or Read
RDY/BUSY active after beginning
of Read
RDY/BUSY Low output (Note 4)
2
3
Toe
60
ns
TeD
0
4
TWTRB
7
6
T BUSY
2
ns
60
ns
60
ns
9
CCLK
periods
1, Configuration must be delayed untillNIT pins of all daisy-chained FPGAs are high.
2. The time from the end of WS to CCLK cycle for the new by1e of data depends on the completion of previous by1e processing
and the phase of internal timing generator for CCLK.
3, CCLK and DOUT timing is tested in slave mode.
4. T BUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY
occurs when a by1e is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is
loaded into the input register before the second-level buffer has started shifting out data,
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will
go active within 60 ns after the end of WS, A new write may be asserted immediately after RDY/BUSY goes Low, but write
may not be terminated until RDY/BUSY has been High for one CCLK period.
Figure 37: Asynchronous Peripheral Mode Programming Switching Characteristics
December 10, 1997 (Version 5.0)
4-263
I
XC5200 Series Field Programmable Gate Arrays
Express Mode
Express mode is similar to Slave Serial mode, except that
data is processed one byte per CCLK cycle instead of one
bit per CCLK cycle. An external source is used to drive
CCLK, while byte-wide data is loaded directly into the configuration data shift registers. A CCLK frequency of 10
MHz is equivalent to an 80 MHz serial rate, because eight
bits of configuration data are loaded per CCLK cycle.
Express mode does not support CRC error checking, but
does support constant-field error checking.
In Express mode, an external signal drives theCCLK input
of the FPGA device. The first byte of parallel configuration
data must be available at the D inputs of the FPGA a short
setup time before the second rising CCLK edge. Subsequent data bytes are clocked in on each consecutive rising
CCLKedge.
Express mode is only supported by the XC4000EX and
XC5200 families. It may not be used, therefore, when an
XC4000EX or XC5200 device is daisy-chained with
devices from other Xilinx families.
If the first device is configured in Express mode, additional
devices may be daisy-chained only if every device in the
chain is also configured in Express mode. CCLK pins are
tied together and DO-D7 pins are tied together for all
devices along the chain. A status signal is passed from
DOUT to CS1 of successive devices along the chain. The
lead device in the chain has its CS1 input tied High (or floating, since there is an internal pullup). Frame data is
accepted only when CS1 is High and the device's configu-
ration memory is not already full. The status pin DOUT is
pulled Low two internal-oscillator cycles after INIT is recognized as High, and remains Low until the device's configuration memory is full. DOUT is then pulled High to signal
the next device in the chain to accept the configuration data
on the DO-D7 bus.
The DONE pins of all devices in the chain should be tied
together, with one or more active internal pull-ups. If a
large number of devices are included in the chain, deactivate some of the internal pull-ups, since the Low-driving
DONE pin of the last device in the chain must sink the current from all pull-ups in the chain. The DONE pull-up is
activated by default. It can be deactivated using an option
in the bitstream generation software.
XC5200 devices in Express mode are always synchronized
to DONE. The device becomes active after DONE goes
High. DONE is an open-drain output. With the DONE pins
tied together, therefore, the external DONE signal stays low
until all devices are configured, then all devices in the daisy
chain become active simultaneously. If the DONE pin of a
device is left unconnected, the device becomes active as
soon as that device has been configured. XC4000EX
devices in the chain should be configured as synchronized
to DONE (either CCLK_SYNC or UCLK_SYNC), and their
DONE pins wired together with those of the XC5200
devices.
Express mode is selected by a <010> on the mode pins
(M2, M1, MO).
vee
47Kn
8
~
.,[,-
M1
MO
'-DATA BUS
8
eSl
M2
MO
eS1
DOUT
~
00·07
V.;.C
INIT
--r'N'T
PROGRAM
-
CCLK
DOUT
XC5200
PROGRAM
CCLK
To AddiUo",'
Optional
) Daisy-Chained
Devices
Optional
Daisy-Chained
XC4000EXI
-INIT
M2
00-07
XC4000EX!
XC5200
4.7Kn
PROGRAM
M1
NOTE:
M2, M1, MO can be shorted
1o Ground if not used as 1/0
DONE
-
DONE
~
CCLK
To Additional
} Optional
Daisy-Chained
Devices
X6611
Figure 38: Express Mode Circuit Diagram
4-264
December 10, 1997 (Version 5.0)
~XlllNX
CCLK
INIT
DO-D7
l~
L
Serial Data Out
(DOUT)
"",moo ""
FPGA Filled
RDYIBUSY
I
CS1
X5087
Description
CCLK
Symbol
INIT (High) Setup time required
1
DIN Setup time required
2
D.IN hold time required
3
TIC
T Dc
Min
Max
5
Units
Ils
ns
30
TCD
0
ns
CCLK High time
TCCH
30
ns
CCLK Low time
TCCL
30
CCLK frequency
Fcc
ns
10
MHz
Note: If not driven by the preceding DOUT, CS1 must remain high until the device is fully configured.
Figure 39: Express Mode Programming Switching Characteristics
December 10, 1997 (Version 5.0)
4-265
XC5200 Series Field Programmable Gate Arrays
Table 14.
Pin Functions During Configuration
USER
OPERATION
Notes 1. A shaded table cell represents a 20-kQ to 100-kQ pull-up resistor before and during configuration.
2. (I) represents an input (0) represents an output.
3. INIT is an open-drain output during configuration.
4-266
December 10, 1997 (Version 5.0)
~XILINX
Configuration Switching Characteristics
Vee
y~------
TpOR - - - - -••1
RE-PROGRAM
PROGRAM
~_~
_ _- f
~
_ _ _ _ Tpi _ _ _ _+/
CCLK OUTPUT or INPUT
MO, M1,M2
(Required)
DONE RESPONSE
X1532
~.r- <
<33,00n8
I/O~
I
Master Modes
Description
Power-On-Reset
Program Latency
CCLK (output) Delay
period (slow)
period (fast)
Symbol
Min
Max
Units
TpOR
T pi
TCCLK
TCCLK
2
6
40
640
100
15
70
375
3000
375
ms
J.ls per CLB column
J.ls
ns
ns
Symbol
Min
Max
Units
T ICCK
Slave and Peripheral Modes
Description
Power-On-Reset
15
ms
T pOR
2
70
Program Latency
T pi
J.lS per CLB column
6
CCLK (input) Delay (required)
5
J.ls
TICCK
ns
period (required)
100
TCCLK
,
,
Note.
At power-up, Vcc must rise from 2,0 to Vcc min In less than 15 ms, otherwise delay configuration uSing PROGRAM until
Vcc is valid,
December 10, 1997 (Version 5,0)
4-267
XC5200 Series Field Programmable Gate Arrays
XC5200 Program Readback Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements.
The following guidelines reflect worst-case values over the recommended operating conditions.
Finished
Internal Net
~r----------~--~\\~----------~\)~---------------
rdbk.TRIG
rdclk.1
rdbk.RIP
rdbk.DATA
X1790
rdbk.TRIG
rdclk.1
Description
rdbk.TRIG setup to initiate and abort Readback
rdbk.TRIG hold to initiate and abort Readback
rdbk.DATA delay
rdbk.RIP delay
High time
Low time
1
2
7
6
5
4
Symbol
T RTRC
T RCRT
T RCRD
T RCRR
T RCH
T RCL
Min
Max
200
50
-
-
250
250
500
500
250
250
Units
ns
ns
ns
ns
ns
ns
Note 1: Timing parameters apply to all speed grades.
Note 2: rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback
4-268
December 10, 1997 (Version 5.0)
~XILINX
XC5200 Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:
Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device
families. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. 1
XC5200 Operating Conditions
Symbol
Description
Supply voltage relative to GND Commercial:O°C to 85°C junction
Vcc
Supply voltage relative to GND Industrial:-40°C to 100°C junction
High-level input voltage - TTL configuration
V IHT
V ILT
Min
Max
Units
4.75
4.5
5.25
V
5.5
2.0
V
V
Low-level input voltage -
TTL configuration
0
Vcc
0.8
V IHC
High-level input voltage -
CMOS configuration
70%
100%
VILC
Low-level input voltage -
CMOS configuration
0
20%
TIN
Input signal transition time
V
250
Vcc
Vcc
ns
Max
Units
0.4
V
V
15
mA
+10
15
!-LA
pF
XC5200 DC Characteristics Over Operating Conditions
Symbol
VOH
VOL
Iceo
IlL
Min
3.86
Leakage current
-10
Input capacitance (sample tested)
CIN
IRIN
Note.
Description
High-level output voltage @ IOH = -8.0 mA, Vcc min
Low-level output voltage @ IOL =8.0 mA,. V cc max
Quiescent FPGA supply current (Note 1)
Pad pull-up (when selected) @ VIN = OV (sample tested)
0.02
0.30
mA
1. With no output current loads, all package pins at Vcc or GND, either TTL or CMOS Inputs, and the FPGA configured with a
tie option.
XC5200 Absolute Maximum Ratings
Symbol
Description
Units
Vcc
Supply voltage relative to GND
-0.5 to +7.0
V
VIN
VTS
Input voltage with respect to GND
-0.5 to V cc +0.5
V
TSTG
Voltage applied to 3-state output
Storage temperature (ambient)
-0.5 to V cc +0.5
-65 to + 150
TSOL
TJ
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
+260
Junction temperature in plastic packages
+125
V
°C
°C
°C
Junction temperature in ceramic packages
+150
°C
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
1. Notwithstanding the definition of the above terms, all specifications are subject to change without notice.
December 10, 1997 (VerSion 5.0)
4-269
I
XC5200 Series Field Programmable Gate Arrays
XC5200 Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACTstep timing calculator
and used in the simulator.
Description
From pad through global buffer, to any clock (CK)
XC5200 Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACTstep timing calculator
and used in the simulator.
Description
I to Longline, while TS is Low; i.e., buffer is constantly active
going Low to Longline going from floating High or Low
to active Low or High
TS going High to TBUF going inactive, not driving
Longline
Note: 1. Die-size-dependent parameters are based upon XC5215 characterization. Production specifications will vary with array
size.
4-270
December 10, 1997 (Version 5.0)
~XILINX
XC5200 CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case. values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACTstep timing calculator
and used in the simulator.
Speed Grade
Description
l'-'OmLJII'i:llUIli:l' Delays
F inputs to X output
F inputs via transparent latch to Q
01 inputs to DO output (Logic-Cell
Feedthrough)
F inputs via F5_MUX to DO output
Carry Delays
Incremental delay per bit
Carry-in overhead from 01
Carry-in overhead from F
Ca(ry-out overhead to DO
! Sequential Delays
Clock (CK) to out (Q) (Flip-Flop)
Gate (Latch enable) going aCtive to out (Q)
Set-up Time Before Clock (CK)
F inputs
F inputs via F5_MUX
01 input
CE input
Hold Times After Clock (CK)
F inputs
F inputs via F5_MUX
01 input
CE input
Clock Widths
Clock High Time
Clock Low Time
Toggle Frequency (MHz) (Note 3)
Reset Delays
Width (High)
Delay from CLR to Q (Flip-Flop)
Delay from CLR to Q (Latch)
Global Reset Delays
Width (High)
Delay from internal GR to Q
Symbol
-5
Min
(ns)
Max
(ns)
Min
(ns)
-3
-4
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
T ,lO
T ,TO
T ,oo
5.6
8.0
4.3
4.6
6.6
3.5
3.8
5.4
2.8
3.0
4.3
2.4
T ,MO
7.2
5.8
5.0
4.3
Tcv
0.7
1.8
3.7
4.0
0.6
1.6
3.2
3.2
0.5
1.5
2.9
2.5
0.5
1.4
2.4
2.1
5.8
9.2
4.9
7.4
4.0
5.9
4.0
5.5
Tcvol
TCVl
Tc;vo
T cKO
TGO
T'CK
T MICK
T DicK
T EICK
2.3
3.8
0.8
1.6
1.8
3.0
0.5
1.2
1.4
2.5
0.4
TCKI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TCH
TCl
FTOG
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
T ClRW
6.0
TCKMI
T CKOI
TCKEI
T GClRW
T GClR
6.0
7.7
6.5
TClR
TClRl
0.9
6.0
6.0
6.3
5.2
6.0
14.7
0
0
83
83
83
1.3
2.4
0.4
0.9
83
6.0
5.1
4.2
6.0
4.0
3.0
6.0
9--1
12.1
8~
';"/,:/'"
Note: 1. The CLB K to Q output delay (TCKO) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold-time requirement (TCKDI) of any CLB on the same die.
2. Timing is based upon the XC5215 device. For other devices, see XACTstepTimingCalculator.
3. Maximum flip-flop toggle rate for export control purposes.
December 10, 1997 (Version 5.0)
4-271
I
XC5200 Series Field Programmable Gate Arrays
XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be
derived indirectly from the Global Buffer specifications. The XACTstep delay calculator uses this indirect method, and may
overestimate because of worst-case assumptions. When there is a discrepancy between these two methods, the values
listed below should be used, and the derived values should be considered conservative overestimates.
Description
Input
Time (no
Flip-Flop
IOB(NODELAY) Direct CLB
In ut ~ Connect
sef-u
_---F,DI
&
HoloR
Time
l]
I
BUFG
Input Hold Time (no delay) to CLB Flip-Flop
IOB(NODELAY) Direct CLB
In ut ~ Connect ~
~e&~j§tF,DI
Time I
.
BUFG
Input Hold Time
i
CLB
----1~
Note:
4-272
(Min)
1. These measurements assume that the CLB flip-flop uses a direct interconnect to or from the lOB. The XACTstep M1
INREG/ OUTREG properties, or XACT-Performance, can be. used to assure that direct connects are used. tpsu applies
only to the CLB input DI that bypasses the look-up table, which only offers direct connects to lOBs on the left and right
edges of the die. tpSUL applies to the CLB inputs F that feed the look-up table, which offers direct connect to lOBs on all
four edges, as do the CLB Q outputs.
2. When testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching.
December 10, 1997 (Version 5.0)
~XILINX
XC5200 lOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACTstep timing calculator
and used in the simulator.
-6
-5
-4
-3
Max
(ns)
Max
(ns)
Max
(ns)
Max
(ns)
5.7
11.4
5.0
10.2
4.8
10.2
3.3
9.5
TOKPOF
4.6
9.5
10.1
4.5
8.4
9.3
4.5
8.0
8.3
3.5
5.0
7.5
TOKPOS
14.9
13.1
11.8
10.0
TTSONF
TTSONS
TGTS
5.6
10.4
17.7
5.2
9.0
15.9
4.9
8.3
14.7
4.6
6.0
13.5
Speed Grade
Description
Input
Propagation Delays from CMOS or TTL Levels
Pad to I (no delay)
Pad to I (with delay)
Output
Propagation Delays to CMOS or TTL Levels
Output (0) to Pad (fast)
Output (0) to Pad (slew-limited)
From clock (CK) to output pad (fast), using direct connect between Q
and output (0)
From clock (CK) to output pad (slew-limited), using direct connect between Q and output (0)
3-state to Pad active (fast)
3-state to Pad active (slew-limited)
Internal GTS to Pad active
Symbol
Tpi
~
T OPF
Tops
I
,:::,
Note:
1. Timing is measured at pin threshold, with 50-pF external capacitance loads. Slew-limited output rise/fall times are
approximately two times longer than fast output rise/fall times.
2. Unused and un bonded lOBs are configured by default as inputs with internal pull-up resistors.
3. Timing is based upon the XC5215 device. For other devices, see XACTstepTiming Calculator.
December 10, 1997 (Version 5.0)
4-273
XC5200 Series Field Programmable Gate Arrays
XC5200 Boundary Scan (JTAG) Switching Characteristic Guidelines
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC5200 devices unless otherwise noted.
Setup and Hold
Input (TOI) to clock (TCK)
setup time
Input (TOI) to clock (TCK)
hold time
Input (TMS) to clock (TCK)
setup time
Input (TMS) to clock (TCK)
hold time
Propagation Delay
Clock (TCK) to Pad (TOO)
TTDITCK
30.0
30.0
30.0
30.0
TTCKTDI
0
0
0
0
TTMSTCK
15.0
15.0
15.0
15.0
TTCKTMS
0
0
0
0
T
30.0
30.0
30.0
Note 1:
4-274
30.0
30.0
30.0
30.0
30.0
30.0
30.0
30.0
30.0
Input pad setup and hold times are specified with respect to the internal clock.
December 10, 1997 (Version 5.0)
~XILINX
Device-Specific Pinout Tables
Device-specific tables include all packages for each XC5200-Series device. They follow the pad locations around the die,
and include boundary scan register locations.
Pin Locations for XC5202 Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the availability
charts elsewhere in the XC5200 Series data sheet for availability information.
Pin
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
Description
VQ64*
PC84
PQ100
VQ100
TQ144
PG156
57
58
2
3
4
-
-
92
93
94
95
96
97
98
89
90
91
92
93
94
95
99
100
1
2
3
4
5
6
7
8
96
97
98
99
100
1
2
3
4
5
9
10
6
7
128
129
130
131
132
133
134
137
138
139
142
143
144
1
2
3
6
7
8
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
32
33
34
35
36
37
38
39
H3
H1
G1
G2
G3
F1
F2
F3
E3
C1
B1
B2
C3
C4
B3
A1
B4
A3
C6
A5
C7
B7
A6
A7
A8
C8
B8
C9
B9
A9
B10
C10
A10
C11
B12
A13
B13
B14
A15
C13
A16
C14
B15
B16.
VCC
I/O (A8)
I/O (A9)
I/O
I/O
I/O (A10)
-
I/O (A11)
59
GND
I/O (A12)
I/O (A13)
I/O (A14)
I/O (A15)
VCC
GND
GGK1 (A16, I/O)
I/O (A17)
I/O (TDI)
I/O (TCK)
GND
I/O (TMS)
I/O
I/O
I/O
I/O
I/O
GND
VCC
21.
22.
23.
24.
25.
26.
60
61
62
63
64
1
2
3
4
32.
33.
34.
7
8
9
10
11
12
13
14
15
16
-
-
5
6
17
18
-
-
7
8
9
I/O
-
I/O
10
I/O
I/O
19
20
21
22
23
24
-
-
-
11
12
13
14
15
16
--17
18
8
9
10
11
12
13
14
15
19
20
16
17
-
I/O
-
I/O
11
25
26
-
-
12
27
13
14
15
28
29
30
31
32
33
34
35
21
22
23
24
25
26
27
28
29
30
GND
27.
28.
29.
30.
31.
5
6
I/O
-
I/O
I/O
I/O
M1 (I/O)
GND
MO (I/O)
VCC
M2 (I/O)
GCK2 (I/O)
December 10, 1997 (Version 5.0)
16
17
18
18
19
20
21
22
23
24
25
26
27
Boundary Scan Order
51
54
57
63
66
69
-
I
78
81
90
93
102
105
111
114
117
123
126
129
135
138
141
147
150
153
159
162
165
171
174
177
186
189
--
192
195
4-275
XC5200 Series Field Programmable Gate Arrays
- - -
Pin
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
57.
58.
59.
60.
61.
62.
63.
64.
65.
66.
67.
68.
69.
70.
71.
72.
73.
4-276
Description
I/O (HOC)
I/O
I/O (LOC)
GNO
I/O
I/O
I/O
I/O
I/O
I/O (ERR, INIT)
VCC
GNO
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
GNO
OONE
vce
PROG
1/0 (07)
GCK3 (I/O)
I/O (06)
I/O
GNO
I/O (05)
I/O (eSO)
I/O
I/O
I/O (04)
I/O
vce
GNO
I/O (03)
I/O (RS)
I/O
I/O
I/O (02)
I/O
GNO
I/O (01)
I/O (RCLK-BUSY/
ROY)
I/O (00, OIN)
I/O (OOUT)
VQ64*
PC84
PQ100
VQ100
TQ144
PG156
Boundary Scan Order
19
36
31
32
33
28
29
30
204
207
210
34
35
36
37
38
39
40
41
42
43
44
45
46
47
31
32
33
34
35
36
37
38
39
40
41
42
43
44
014
E14
C16
F14
F16
G14
G15
G16
H16
H15
H14
J14
J15
J16
K16
K15
K14
L16
L14
P16
M14
N14
R16
P14
R15
P13
R14
T16
T15
T14
T13
Pll
Tl0
Pl0
Rl0
T9
R9
P9
R8
P8
T8
T7
T6
R7
P7
T5
P6
T3
P5
P4
T2
372
375
-
-
45
-
69
70
73
74
70
71
40
43
44
45
48
49
50
51
52
53
54
55
56
57
58
59
60
61
64
65
66
69
70
71
72
73
74
75
76
79
80
81
84
85
86
87
88
89
90
91
92
93
94
95
96
97
100
101
102
46
47
71
72
75
76
72
73
105
106
20
37
-
38
39
21
22
23
24
25
26
27
40
41
42
43
44
45
-
-
28
29
46
47
30
31
32
33
34
35
36
37
48
49
50
51
52
53
54
55
56
57
58
38
39
40
41
42
43
44
-
48
49
50
51
52
53
54
55
56
57
58
59
45
46
47
48
49
50
51
52
53
54
55
56
-
-
59
60
60
61
62
63
64
65
66
67
68
69
70
57
58
59
60
61
62
63
64
65
66
67
71
72
68
69
61
62
63
64
65
66
-
67
68
-
216
219
222
228
231
234
240
243
246
252
255
258
264
267
276
279
-
288
291
300
303
306
312
315
318
324
327
336
339
342
348
351
360
363
366
December 10, 1997 (Version 5.0)
~XILINX
Description
Pin
VQ64*
PC84
PQ100
VQ100
TQ144
PG156
48
73
77
78
79
80
81
82
83
84
74
107
75
108
R2
P3
-
76
109
Tl
0
77
78
110
111
N3
Rl
79
112
115
P2
Pl
116
Nl
21
L3
K3
27
CCLK
VCC
74.
-
74
49
75
-
76
77
78
79
75.
I/O (TDO)
GNO
I/O (AO, WS)
76.
GCK4 (A 1, I/O)
50
51
77.
78.
I/O (A2, CS1)
52
79.
80.
I/O (A3)
GNO
I/O (A4)
I/O (A5)
80
-
9
15
18
-
-
-
81
85
82
118
121
53
82
122
K2
30
-
86
87
83
-
84
Kl
33
-
88
85
123
124
89
90
91
86
87
125
126
Jl
J2
39
42
45
88
127
8182.
I/O
83.
84.
I/O (A6)
I/O (A7)
54
55
83
84
GNO
56
1
I/O
80
81
Boundary Scan Order
J3
H2
I
-
• VQ64 package supports Master Serial, Slave Serial, and Express configuration modes only.
Additional No Connect (N.C.) Connections on TQ144 Package
Notes: Boundary Scan Bit 0 = TOO.T
Boundary Scan Bit 1. = TOO.O
Boundary Scan Bit 1056 = BSCAN.UPO
Pin Locations for XC5204 Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the availability
charts elsewhere in the XC5200 Series data sheet for availability information.
Pin
Description
PC84
PQ100
VQ100
TQ144
PG156
PQ160
VCC
2
92
89
128
H3
142
-
1.
I/O (A8)
90
91
Hl
3.
4.
5.
I/O
I/O
I/O (Al0)
92
Gl
G2
5
95
96
97
93
94
130
131
132
143
144
78
I/O (A9)
93
94
129
2.
3
4
6.
I/O (All)
6
98
7.
I/O
-
8.
I/O
GNO
9.
10.
- -
-
-
I/O
-
11.
I/O
I/O (A12)
7
12.
I/O (A13)
8
13.
I/O
December 10, 1997 (Version 5.0)
133
G3
Fl
95
134
-
135
136
99
100
-
-
96
97
137
-
145
146
Boundary Scan Order
81
87
90
147
93
F2
148
El
149
150
99
102
E2
F3
01
138
02
E3
139
140
Cl
C2
105
151
-
152
153
111
114
154
117
155
156
123
126
..
4-277
XC5200 Series Field Programmable Gate Arrays
----
Pin
Description
14.
15.
16.
I/O
I/O (A14)
I/O (A15)
VCC
GNO
GCKl (A16, I/O)
I/O (A17)
I/O
I/O
I/O (TOI)
I/O (TCK)
GNO
I/O
I/O
I/O (TMS)
I/O
I/O
I/O
I/O
I/O
GNO
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O
Ml (I/O)
GNO
MO(l/O)
VCC
M2 (I/O)
GCK2 (I/O)
I/O (HOC)
I/O
I/O
I/O
I/O (LOC)
I/O
I/O
GNO
I/O
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
4-278
PQ100
VQ100
TQ144
PG156
PQ160
Boundary Scan Order
-
-
9
10
11
12
13
14
1
2
3
4
5
6
98
99
100
1
2
3
-
-
15
16
7
8
4
5
-
-
03
Bl
B2
C3
C4
B3
Al
A2
C5
B4
A3
C6
B5
B6
A5
C7
B7
A6
A7
A8
C8
B8
C9
B9
A9
Bl0
Cl0
Al0
Al1
Bll
Cll
B12
A13
A14
C12
B13
B14
A15
C13
A16
C14
B15
B16
014
C15
015
E14
C16
E15
016
F14
F15
157
158
159
160
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
129
138
141
-
141
142
143
144
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PC84
-
-
-
17
18
9
10
6
7
-
-
-
11
12
13
14
15
16
17
18
8
9
10
11
12
13
14
15
19
20
21
22
23
24
-
-
-
25
26
19
20
16
17
-
-
27
-
-
-
21
22
18
19
-
-
23
24
25
26
27
28
29
30
31
20
21
22
23
24
25
26
27
28
28
29
30
31
32
33
34
35
36
-
32
33
29
30
-
-
-
-
-
37
--
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
150
153
159
162
165
171
174
177
180
183
186
189
195
198
201
207
210
213
219
222
225
231
-
234
237
240
243
246
249
258
261
264
267
276
279
282
288
291
294
300
303
December 10, 1997 (Version 5.0)
---~----------
----
~XILINX
Pin
57.
58.
59.
60.
61.
62.
63.
64.
65.
66.
67.
68.
69.
70.
71.
72.
73.
74.
75.
76.
77.
78.
79.
80.
81.
82.
83.
84.
85.
86.
87.
88.
89.
90.
91.
92.
93.
94.
95.
96.
97.
98.
Description
I/O
I/O
I/O
I/O
I/O
I/O
I/O (ERR, INIT)
VCC
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
OONE
VCC
PROG
I/O (07)
GCK3(1/0)
I/O
I/O
1/0(06)
I/O
GNO
I/O
I/O
I/O (05)
I/O (CSO)
I/O
I/O
I/O (04)
I/O
VCC
GNO
I/O (03)
I/O (RS)
I/O
I/O
1/0(02)
December 10, 1997 (Version 5.0)
PC84
PQ100
-
-
38
39
34
35
36
37
38
39
40
41
42
43
44
45
46
47
VQ100
TQ144
PG156
PQ160
E16
F16
G14
G15
G16
H16
H15
H14
J14
J15
J16
K16
K15
K14
L16
M16
L15
L14
N16
M15
P16
M14
N15
P15
N14
R16
P14
R15
P13
R14
T16
T15
R13
P12
T14
T13
P11
R11
T11
T10
P10
Rl0
T9
R9
P9
R8
P8
T8
T7
T6
R7
P7
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
-
-
-
-
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
-
-
-
-
48
49
48
49
45
46
-
-
50
51
52
53
54
55
56
57
50
51
52
53
54
55
56
57
47
48
49
50
51
52
53
54
65
66
67
68
69
70
71
72
73
74
75
76
-
-
-
58
59
55
56
-
40
41
42
43
44
45
46
47
-
-
58
-
31
32
33
34
35
36
37
38
39
40
41
42
43
44
-
-
-
-
-
-
-
59
60
-
60
61
62
63
64
65
66
67
68
69
70
57
58
59
60
61
62
63
64
65
66
67
67
71
61
62
63
64
65
66
68
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
77
78
79
80
81
82
83
84
85
86
87
88
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
Boundary Scan Order
306
. 312
315
318
324
327
330
336
339
348
351
354
360
363
366
I
372
375
378
384
387
390
396
399
408
411
420
423
426
432
435
438
444
447
450
456
459
462
468
471
474
480
483
4-279
XC5200 Series Field Programmable Gate Arrays
Description
Pin
100.
110
110
101.
I/O
99.
PC84
PQ100
VQ100
TQ144
PG156
PQ160
Boundary Scan Order
68
72
69
97
T5
107
486
98
R6
108
492
99
T4
109
495
100
P6
110
-
GND
-
-
102.
I/O (D1)
69
73
70
101
T3
113
498
103.
I/O (RCLK-BUSY/
RDY)
70
74
71
102
P5
114
504
104.
I/O
507
I/O
-
-
105.
106.
I/O (DO, DIN)
71
107.
108.
-
103
R4
115
-
104
R3
116
510
75
72
105
P4
117
516
I/O (DOUT)
72
76
73
106
T2
118
519
CCLK
73
77
74
107
R2
119
-
VCC
74
78
75
108
P3
120
I/O (TDO)
75
79
76
109
T1
121
GND
76
80
77
110
N3
122
-
109.
I/O (AO, WS)
77
81
78
111
R1
123
9
110.
GCK4 (A1, I/O)
78
82
79
112
P2
124
15
111.
I/O
113
N2
125
18
112.
I/O
-
-
-
114
M3
126
21
113.
I/O (A2, CS1)
79
83
80
115
P1
127
27
114.
I/O (A3)
80
84
81
116
N1
128
30
115.
I/O
-
-
-
117
M2
129
33
116.
I/O
M1
130
39
118
L3
131
-
-
-
119
L2
132
42
45
GND
0
117.
110
118.
I/O
120
L1
133
119.
I/O (A4)
81
85
82
121
K3
134
51
120.
I/O (A5)
82
86
83
122
K2
135
54
121.
I/O
87
84
123
K1
137
57
122.
I/O
88
85
124
J1
138
63
123.
I/O (A6)
83
89
86
125
J2
139
66
I/O (A7)
84
90
87
126
J3
140
69
1
91
88
127
H2
141
124.
GND
-
Additional No Connect (N.C.) Connections for PQ160 Package
Notes: Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 1056 = BSCAN.UPD
4-280
December 10, 1997 (Version 5.0)
~XILINX
Pin Locations for XC5206 Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the availability
charts elsewhere in the XC5200 Series data sheet for availability information.
Pin
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
PC84
PQ100
VQ100
TQ144
PQ160
TQ176
PG19l
PQ208
VCC
1/0 (A8)
1/0 (A9)
Description
2
3
4
1/0
1/0
1/0
-
92
93
94
95
96
89
90
91
92
93
128
129
130
131
132
142
143
144
145
146
I/O
-
-
-
-
1/0 (A10)
1/0 (A11)
1/0
5
6
97
98
94
95
-
-
-
133
134
135
136
137
155
156
157
158
159
160
161
162
163
164
165
166
168
169
170
171
172
173
174
175
176
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
J4
J3
J2
J1
H1
H2
H3
G1
G2
F1
E1
G3
C1
E2
F3
D2
B1
E3
C2
B2
D3
D4
C3
C4
B3
C5
A2
B4
C6
A3
C7
A4
A5
B7
A6
C8
A7
B8
A8
B9
C9
D9
D10
C10
B10
A9
A10
A11
183
184
185
186
187
188
189
190
191
192
193
194
197
198
199
200
201
202
203
204
205
2
4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
I/O
GND
-
-
1/0
I/O
-
-
1/0 (A12)
1/0 (A13)
1/0
1/0
7
8
99
100
96
97
-
-
-
I/O (A14)
9
10
11
12
13
14
1
2
3
4
5
6
98
99
100
1
2
3
-
-
-
15
16
7
8
4
5
-
-
-
-
-
-
17
18
9
10
6
7
8
9
10
11
12
-
-
-
-
1/0 (A15)
VCC
GND
GCK1 (A16, 1/0)
1/0 (A17)
110
1/0
1/0 (TDI)
1/0 (TCK)
I/O
1/0
GND
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
1/0
1/0
1/0 (TMS)
1/0
1/0
1/0
1/0
1/0
1/0
1/0
GND
VCC
37.
38.
39.
40.
41.
1/0
1/0
1/0
19
20
21
22
23
24
-
-
11
12
13
14
15
16
17
18
8
9
10
11
12
13
14
15
-
I/O
1/0
December 10, 1997 (Version 5.0.)
-
-
147
148
149
150 .
151
152
153
154
155
156
157
158
159
160
1
2
3
4
5
6
7
8
9
10
11
12
13
14
138
139
140
141
142
143
144
1
2
3
4
5
6
7
-
13
14
15
16
17
18
19-20
21
22
~
15
16
17
18
19
20..
21
22
23
24
Boundary Scan Order
87
90
93
99
102
105
111
114
117
123
I
126
129
138
141
150
153
162
165
.'
174
177
183
186
189
195
198
201
207
210
213
219
222
225
234
237
246
249
255
258
261
267
270
4-281
XC5200 Series Field Programmable Gate Arrays
~~-
Pin
Description
42.
43.
44.
45.
46.
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M1 (I/O)
GNO
MO (I/O)
VCC
M2 (I/O)
GCK2 (I/O)
I/O (HOC)
I/O
I/O
I/O
I/O (LOC)
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (ERR, INID
VCC
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
57.
58.
59.
60.
61.
62.
63.
64.
65.
66.
67.
68.
69.
70.
71.
72.
73.
74.
75.
76.
77.
78.
79.
80.
81.
82.
83.
84.
85.
86.
4-282
PC84
PQ100
-
-
25
26
19
20
16
17
-
-
-
23
24
25
26
27
-
-
21
22
18
19
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
27
-
-
28
29
30
31
32
33
34
35
36
23
24
25
26
27
28
29
30
31
-
37
32
33
-
20
21
22
23
24
25
26
27
28
-
-
VQ100
29
30
TQ144
-
-
-
45
46
47
48
49
PQ160
TQ176
PG191
PQ208
Boundary Scan Order
-
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
C11
B11
A12
B12
A13
C12
A15
C13
B14
A16
B15
C14
A17
B16
C15
015
A18
016
C16
B17
E16
C17
017
B18
E17
F16
C18
G16
E18
F18
G17
G18
H16
H17
H18
J18
J17
J16
J15
K15
K16
K17
K18
L18
L17
L16
M18
M17
N18
P18
M16
T18
32
33
34
35
36
37
40
41
42
43
273
279
282
285
291
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
-
-
38
39
34
35
-
-
-
36
37
38
39
40
41
42
43
44
45
33
34
35
36
37
38
39
40
41
42
50
51
52
53
54
55
56
57
58
59
56
57
58
59
60
61
62
63
64
65
-
-
-
-
46
47
43
44
-
-
-
-
60
61
62
63
64
-
-
66
67
68
69
70
71
-
40
41
42
43
44
45
46
47
-
31
32
-
-
-
77
78
79
44
45
46
47
48
49
50
55
56
57
58
59
60
61
62
63
64
67
68
69
70
71
72
73
74
75
76
294
297
303
306
309
315
318
321
330
333
336
339
348
351
354
360
363
372
375
378
384
387
390
396
399
402
408
411
414
77
78
79
80
81
82
83
84
85
86
87
88
89
90
93
-
---
420
423
426
432
435
438
444
447
450
456
459
December 10, 1997 (Version 5.0)
-~--------
----
~XILINX
Pin
87.
88.
89.
90.
91.
92.
93.
PC84
PQ100
1/0
-
-
1/0
1/0
48
49
48
49
1/0
-
Description
1/0
1/0
1/0 (07)
GCK3 {l/0)
1/0 (06)
58
1/0
-
1/0
-
58
59
PQ160
TQ176
PG191
PQ208
Boundary Scan Order
72
101
102
P17
N16
T17
R17
P16
U18
T16
R16
U17
R15
V18
T15
U16
T14
U15
V17
V16
T13
U14
T12
U13
V13
U12
V12
Tll
Ull
Vll
Vl0
Ul0
Tl0
Rl0
R9
T9
U9
V9
V8
U8
T8
V7
U7
V6
U6
T7
U5
T6
V3
V2
94
95
96
97
98
99
100
101
103
106
108
109
110
111
112
113
114
115
116
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
145
146
147
148
468
471
480
483
486
492
495
106
107
108
109
110
111
112
113
114
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
103
104
105
106
115
116
117
118
127
128
129
130
U4
T5
U3
T4
149
150
151
152
55
56
-
-
-
50
51
52
53
54
55
56
57
TQ144
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
47
48
49
50
51
52
53
54
-
1/0
1/0
1/0
1/0
1/0 (05)
1/0
(CSO)
1/0
1/0
1/0
59
60
60
61
57
58
81
82
83
84
85
-
-
-
-
62
63
64
65
66
67
68
69
70
59
60
61
62
63
64
65
66
67
-
-
-
71
68
69
96
97
98
99
100
1/0
1/0 (04)
1/0
VCC
GNO
112.
113.
114.
115.
116.
117.
118.
119.
120.
121.
50
51
52
53
54
55
56
57
1/0
GNO
102.
103.
104.
105.
106.
107.
108.
109.
110.
111.
45
46
1/0
GNO
DONE
VCC
PROG
94.
95.
96.
97.
98.
99.
100.
101.
VQ100
1/0 (03)
1/0
(RS)
61
62
63
64
65
66
-
1/0
1/0
I/O
1/0
I/O
67
68
1/0
-
1/0 (02)
1/0
GNO
122.
123.
124.
125.
1/0
126.
127.
128.
129.
1/0
-
-
-
-
1/0
1/0 (01)
(RCLKBUSY/ROY)
1/0
69
70
73
74
-
1/0
DIN)
(OOUT)
1/0(00.
1/0
72
86
87
88
89
90
91
92
93
94
95
71
72
December 10, 1997 (Version 5.0)
70
71
75
76
72
73
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
-
-
504
507
516
519
522
528
531
534
I
540
543
552
555
558
564
567
570
576
579
588
591
600
603
612
615
618
624
627
630
636
639
642
648
651
654
660
663
4-283
XC5200 Series Field Programmable Gate Arrays
.
__
..
PC84
PQ100
VQ100
TQ144
PQ160
TQ176
PG191
PQ208
CCLK
73
77
74
107
119
131
Vl
153
VCC
74
78
75
108
120
132
R4
154
-
I/O (TDO)
75
79
76
109
121
133
U2
159
GND
76
80
77
110
122
134
R3
160
-
131.
I/O (AO, WS)
77
81
78
111
123
135
T3
161
9
132.
GCK4 (A 1, I/O)
78
82
79
112
124
136
Ul
162
15
133.
I/O
113
125
137
P3
163
18
134.
I/O
114
126
138
R2
164
21
135.
I/O (A2, CS1)
79
83
80
115
127
139
T2
165
27
136.
I/O (A3)
80
84
81
116
128
140
N3
166
30
Pin
Description
130.
-
Boundary Scan Order
137.
I/O
-
-
117
129
141
P2
167
33
138.
I/O
-
-
130
142
Tl
168
42
GND
-
118
131
143
M3
171
-
139.
I/O
119
132
144
Pl
172
45
140.
120
133
145
Nl
173
51
141.
I/O
1/0(A4)
-
-
81
85
82
121
134
146
M2
174
54
82
86
83
122
135
147
Ml
175
57
-
148
L3
176
63
66
142.
I/O (A5)
143.
I/O
-
-
136
149
L2
177
87
84
123
137
150
Ll
178
69
88
85
124
138
151
Kl
179
75
83
89
86
125
139
152
K2
180
78
84
90
87
126
140
153
K3
181
81
1
91
88
127
141
154
K4
182
-
144.
I/O
-
145.
I/O
-
146.
I/O
147.
I/O (A6)
148.
I/O (A7)
GND
Additional No Connect (N.C.) Connections for PQ208 and TQ176 Packages
PQ208
195
1
196
206
3
12
207
13
208
38
TQ176
39
51
52
65
104
144
169
66
91
107
117
155
156
170
53
54
92
102
118
143
158
157
167
,,};
..,:(
"".""
..
,"
')',:<':'::;:::' 1:" • '•.<:<",·,.,,::,.,,:
:i·;,::.:':,:; . . :,:,.;:
1':.'·.,-.':',':• ,• ,· .'.••• • ','.·"
Notes: Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 1056 = BSCAN.UPD
Pin Locations for XC5210 Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the availability
charts elsewhere in the XC5200 Series data sheet for availability information.
Pin
Description
PC84
TQ144
PQ160
TQ176
PQ208
PG223
BG225
PQ240
212
Boundary Scan
Order
VCC
2
128
142
155
183
J4
VCC'
1.
I/O (A8)
129
143
156
184
J3
E8
213
111
2.
I/O (A9)
3
4
130
144
157
185
J2
B7
214
114
3.
I/O
131
145
158
186
Jl
A7
215
117
4.
I/O
132
146
159
187
Hl
C7
216
123
5.
I/O
-
188
H2
D7
217
126
I/O
-
160
6.
161
189
H3
E7
218
129
4-284
-
December 10, 1997 (Version 5.0)
~XILINX
Pin
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
Oeseri ption
I/O (Al0)
I/O (All)
VCC
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O (A12)
I/O (A13)
I/O
I/O
I/O
I/O
I/O (A14)
I/O (A15)
VCC
GNO
GCKl (A16, I/O)
I/O (A17)
I/O
I/O
I/O (TOI)
I/O (TCK)
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O (TMS)
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
VCC
I/O
December 10, 1997 (Version 5.0)
PC84
TQ144
PQ160
TQ176
PQ208
PG223
BG225
PQ240
5
6
133
134
147
148
162
163
190
191
Gl
G2
-
-
-
H4
G4
Fl
El
G3
F2
01
Cl
E2
F3
02
F4
E4
Bl
E3
C2
B2
03
04
C3
C4
B3
C5
A2
B4
C6
A3
B5
86
05
06
C7
A6
B6
VCC*
C6
F7
A5
B5
GNO*
06
C5
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
23
24
25
26
27
28
29
30
31
-
-
-
-
-
135
136
137
149
150
151
164
165
166
-
-
-
-
-
167
168
169
170
171
-
-
7
8
138
139
152
153
154
155
-
-
-
-
156
157
158
159
160
1
2
3
4
5
6
7
8
9
172
173
174
175
176
1
2
3
4
5
6
7
8
9
-
-
9
10
11
12
13
14
15
16
-
17
18
140
141
142
143
144
1
2
3
4
5
6
7
-
~~
8
9
10
11
12
-
~
10
11
12
13
14
-
19
20
21
22
23
201
202
203
204
205
2
4
5
6
7
8
9
10
11
12
13
-
10
11
12
13
14
14
15
16
17
18
-
-
15
16
17
18
19
20
21
22
23
19
20
21
22
23
24
25
26
27
A4
A5
B7
A6
-
-
-
192
193
194
195
196
197
198
199
200
13
14
15
16
17
18
19
15
16
17
18
19
20
21
07
08
C8
A7
B8
A8
B9
C9
09
010
Cl0
A4
E6
B4
05
A3
C4
B3
F6
A2
C3
VCC*
GNO*
04
Bl
C2
E5
03
Cl
02
G6
E4
01
E3
E2
GNO*
F5
El
F4
F3
VCC*
F2
Fl
G4
G3
G2
Gl
G5
H3
GNO*
VCC*
H4
Boundary Sean
Order
135
138
141
150
153
162
165
171
174
177
183
186
189
195
198
201
210
213
I
222
225
231
234
237
243
246
249
255
258
261
267
270
273
279
282
285
291
294
297
306
309
318
321
-~-
~
~
327
4-285
XC5200 Series Field Programmable Gate Arrays
Pin
50.
51.
52.
53.
54.
55.
56.
Description
1/0
74.
75.
76.
77.
78.
79.
80.
81.
82.
83.
84.
85.
86.
87.
88.
89.
90.
91.
92.
93.
94.
4-286
PQ160
TQ176
PQ208
PG223
BG225
PQ240
24
20
21
22
22
23
24
24
25
26
27
28
28
29
30
31
32
Bl0
A9
Al0
All
Cll
011
012
H5
J2
Jl
J3
J4
J5
Kl
VCC*
K2
K3
J6
Ll
GNO*
L2
K4
L3
Ml
K5
M2
L4
Nl
M3
N2
K6
32
33
34
35
36
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
84
1/0
1/0
1/0
1/0
-
-
-
1/0
1/0
1/0
1/0
1/0
GNO
61.
62.
63.
64.
65.
66.
67.
68.
69.
70.
71.
72.
73.
TQ144
1/0
VCC
57.
58.
59.
60.
PC84
1/0
1/0
-
-
25
26
23
24
25
26
27
-
-
-
1/0
1/0
1/0
1/0
1/0
1/0
Ml (1/0)
GNO
MO (1/0)
VCC
M2 (1/0)
GCK2 (1/0)
1/0 (HOC)
110
1/0
1/0
1/0 (LOC)
27
28
29
30
31
32
33
34
35
36
37
1/0
1/0
-
1/0
1/0
-
GNO
-
1/0
1/0
1/0
1/0
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
-
1/0
1/0
38
39
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
-
33
34
35
36
37
-
-
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
38
39
40
41
42
43
44
45
46
47
48
49
50
55
56
57
58
59
60
61
62
63
64
65
66
Bll
A12
B12
A13
C12
013
014
B13
A14
A15
C13
B14
A16
B15
C14
A17
B16
C15
015
A18
016
C16
B17
E16
C17
017
B18
E17
F16
C18
018
F17
E15
F15
G16
E18
F18
G17
G18
-
-
45
46
47
48
49
VCC
-
1/0
-
1/0
1/0
29
30
31
32
33
-
1/0
1/0
1/0
1/0
25
26
27
28
29
-
-
51
52
53
54
55
55
56
57
58
59
67
68
69
70
71
-
60
61
72
73
-
-
H16
H17
G15
Pl
N3
GNO*
P2
VCC*
M4
R2
P3
L5
N4
R3
P4
K7
M5
R4
N5
P5
L6
GNO*
R5
M6
N6
P6
VCC*
R6
M7
N7
Boundary Scan
Order
330
333
339
342
345
351
354
357
363
366
369
375
378
381
387
390
393
399
402
405
411
414
417
426
429
432
435
444
447
450
456
459
462
468
471
474
480
483
486
492
495
504
507
510
516
December 10, 1997 (Version 5.0)
~XILINX
Pin
95.
96.
97.
98.
99.
100.
101.
102.
103.
104.
105.
106.
107.
108.
109.
110.
111.
112.
113.
114.
115.
116.
117.
118.
119.
120.
121.
122.
123.
124.
125.
126.
127.
128.
129.
130.
131.
132.
133.
134.
135.
136.
Description
I/O
I/O
I/O
I/O
I/O (ERR, INIT)
VCC
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
110
I/O
I/O
I/O
I/O
GNO
OONE
VCC
PROG
I/O (07)
GCK3 (I/O)
I/O
I/O
I/O
I/O
I/O (06)
I/O
I/O
I/O
110
I/O
GNO
I/O
December 10, 1997 (Version 5.0)
PC84
-
PQ160
TQ176
PQ208
PG223
BG225
PQ240
-
50
51
52
53
54
55
56
57
58
59
56
57
58
59
60
61
62
63
64
65
-
-
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
-
-
H15
H18
J18
J17
J16
J15
K15
K16
K17
K18
L18
L17
L16
L15
M15
P7
R7
L7
N8
P8
VCC*
GNO*
L8
P9
R9
N9
M9
L9
Rl0
Pl0
VCC*
Nl0
K9
Rll
Pll
GNO*
Ml0
Nll
R12
L10
P12
Mll
R13
N12
P13
Kl0
R14
N13
GNO*
P14
VCC*
M12
P15
N14
L11
M13
N15
M14
Jl0
L12
M15
L13
L14
Kll
GNO*
L15
85
86
87
88
89
90
91
92
93
94
95
96
97
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
TQ144
-
40
41
42
43
44
45
-
-
-
-
-
46
47
60
61
62
63
64
66
67
68
69
70
74
75
76
86
87
88
89
90
-
-
-
-
-
48
49
-
65
66
67
-
~
50
51
52
53
54
55
56
57
69
70
71
72
73
74
75
76
-
77
58
-
71
72
73
74
75
76
77
77
78
-
-
-
-
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
78
78
79
80
81
82
83
84
85
86
-
-
79
80
87
88
89
90
95
96
97
98
81
91
99
-
-
-
91
92
93
94
95
96
97
98
99
100
101
103
106
108
109
110
111
112
113
114
115
116
117
118
119
-
M18
M17
N18
P18
M16
N15
P15
N17
R18
T18
P17
N16
T17
R17
P16
U18
T16
R16
U17
R15
V18
T15
U16
T14
U15
R14
R13
V17
V16
T13
U14
V15
V14
T12
R12
Boundary Scan
Order
519
522
528
531
534
540
543
546
552
555
558
564
567
I
570
576
579
588
591
600
603
606
612
615
618
624
627
630
636
639
-
648
651
660
663
666
672
675
678
684
687
690
696
699
4-287
XC5200 Series Field Programmable Gate Arrays
Pin
Description
137.
I/O
138.
I/O
139.
I/O
BG225
PQ240
Boundary Scan
Order
-
R11
K12
137
708
120
U13
K13
138
711
V13
K14
139
714
VCC*
140
TQ176
PQ208
82
92
100
83
93
101
121
-
-
TQ144
-
VCC
PG223
PQ160
PC84
-
-
140.
I/O (D5)
59
84
94
102
122
U12
K15
141
141.
I/O (CSO)
60
85
95
103
123
V12
J12
142
723
142.
I/O
-
124
T11
J13
144
726
I/O
-
-
104
143.
-
105
125
U11
J14
145
732
144.
I/O
86
96
106
126
V11
J15
146
735
145.
I/O
-
87
97
107
127
V10
J11
147
738
146.
I/O (D4)
61
88
98
108
128
U10
H13
148
744
747
147.
I/O
62
89
99
109
129
T10
H14
149
VCC
63
90
100
110
130
R10
VCC*
150
720
GND
64
91
101
111
131
R9
GND*
151
148.
I/O (D3)
65
92
102
112
132
T9
H12
152
756
149.
I/O (RS)
66
93
103
113
133
U9
H11
153
759
-
94
104
114
134
V9
G14
154
768
95
105
115
135
V8
G15
155
771
-
-
-
116
136
U8
G13
156
780
117
137
T8
G12
157
783
G11
159
786
792
150.
I/O
151.
I/O
152.
I/O
153.
I/O
154.
I/O (D2)
67
96
106
118
138
V7
I/O
68
97
107
119
139
U7
-
-
-
155.
VCC
156.
I/O
157.
I/O
158.
I/O
159.
I/O
GND
-
F15
160
VCC*
161
98
108
120
140
V6
F14
162
795
-
99
109
121
141
U6
F13
163
798
-
-
-
R8
G10
164
804
R7
E15
165
807
-
100
110
T7
GND*
166
R6
E14
167
810
-
-
R5
F12
168
816
819
142
-
160.
I/O
161.
I/O
162.
I/O
163.
I/O
164.
I/O
165.
I/O
166.
I/O (D1)
69
101
167.
I/O (RCLK-BUSY/RDY)
70
-
122
-
143
V5
E13
169
144
V4
D15
170
822
111
123
145
U5
F11
171
828
112
124
146
T6
D14
172
831
113
125
147
V3
E12
173
834
102
114
126
148
V2
C15
174
840
843
168.
I/O
-
103
115
127
149
U4
D13
175
169.
I/O
-
104
116
128
150
T5
C14
176
846
170.
I/O (DO, DIN)
71
105
117
129
151
U3
F10
177
855
171.
172.
I/O (DOUT)
72
106
118
130
152
T4
B15
178
858
CCLK
73
107
119
131
153
V1
C13
179
VCC
74
108
120
132
154
R4
VCC*
180
-
I/O (TDO)
75
109
121
133
159
U2
A15
181
GND
76
110
122
134
160
R3
GND*
182
173.
I/O (AO, WS)
77
111
123
135
161
T3
A14
183
9
174.
GCK4 (A1, I/O)
78
112
124
136
162
U1
B13
184
15
175.
I/O
113
125
137
163
P3
E11
185
18
176.
110
114
126
138
164
R2
C12
186
21
177.
I/O (CS1, A2)
79
115
127
139
165
T2
A13
187
27
178.
I/O (A3)
80
116
128
140
166
N3
B12
188
30
179.
I/O
P4
F9
189
33
4-288
December 10, 1997 (Version 5.0)
~XILINX
,------
-------
Pin
Description
180.
I/O
181.
I/O
182.
I/O
183.
1/0
184.
I/O
PC84
TQ144
-
PQ160
TQ176
PQ208
PG223
Boundary Scan
Order
BG225
PQ240
N4
011
190
39
P2
A12
191
42
-
-
117
129
141
167
-
130
142
168
T1
C11
192
45
169
R1
B11
193
51
170
N2
E10
194
54
-
-
GNO*
171
M3
196
57
-
-
-
GNO
118
131
143
185.
I/O
119
132
144
172
P1
A11
197
186.
I/O
120
133
145
173
N1
010
198
66
187.
I/O
M4
C10
199
69
75
L4
B10
200
-
-
-
VCC*
201
-
146
174
M2
A10
202
78
147
175
M1
09
203
81
148
176
L3
C9
205
87
I/O
188.
-
VCC
189.
I/O(A4)
81
121
134
190.
I/O (A5)
82
122
135
191.
I/O
192.
I/O
193.
I/O
194.
I/O
195.
196.
-
136
149
177
L2
B9
206
90
-
123
137
150
178
L1
A9
207
93
124
138
151
179
K1
E9
208
99
I/O (A6)
83
125
139
152
180
K2
C8
209
102
I/O (A7)
84
126
140
153
181
K3
B8
210
105
1
127
141
154
182
K4
GNO*
211
GNO
I
Additional No Connect (N.C.) Connections for PQ208 and PQ240 Packages
PQ240
PQ208
53
107
158
22
143
155
206
37
158
51
54
102
83
195
104
156
157
207
52
208
98
204
3
Notes: * Pins labeled VCC* are internally bonded to a VCC plane within the BG225 package. The external pins are: B2, 08, H15, R8,
B14, R1, H1, and R15.
Pins labeled GNO* are internally bonded to a ground plane within the BG225 package. The external pins are: A1, 012, G7,
G9, H6, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9, J7, J9, M8.
Boundary Scan Bit 0 = TOO.T
Boundary Scan Bit 1 = TOO.O
Boundary Scan Bit 1056 = BSCAN.UPO
Pin Locations for XC5215 Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the availability
charts elsewhere in the XC5200 Series data sheet for availability information.
Pin
Descri ption
VCC
PQ160
HQ208
HQ240
PG299
HQ304
BG225
BG352
142
183
212
K1
38
VCC*
VCC*
Boundary Scan Order
1.
I/O (A8)
143
184
213
K2
37
E8
014
2.
I/O (A9)
144
185
214
K3
36
B7
C14
138
141
3.
I/O
145
186
215
K5
35
A7
A15
147
150
4.
I/O
146
187
216
K4
34
C7
B15
5.
I/O
188
217
J1
33
07
C15
153
6.
I/O
-
189
218
J2
32
E7
015
159
7.
I/O (A10)
147
190
220
H1
31
A6
A16
162
December 10, 1997 (Version 5.0)
4-289
XC5200 Series Field Programmable Gate Arrays
Pin
8.
9.
10.
Description
1/0 (A11)
1/0
1/0
PQ160
148
1/0
1/0
1/0
1/0
GNO
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
1/0
1/0
1/0
1/0
110
1/0
1/0 (A12)
110 (A13)
1/0
1/0
1/0
I/O
110
1/0
1/0 (A14)
1/0 (A15)
VCC
GNO
GCK1 (A16, 1/0)
1/0 (A17)
1/0
1/0
1/0 (TOI)
1/0 (TCK)
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
GNO
47.
48.
49.
50.
51.
52.
53.
4"290
1/0
1/0
1/0 (TMS)
110
VCC
1/0
1/0
1/0
HQ240
221
"
"
VCC
11.
12.
13.
14.
HQ208
191
"
"
"
149
150
151
192
193
194
222
223
224
225
226
227
"
"
"
"
152
153
154
155
"
195
196
197
198
199
200
228
229
230
231
232
233
"
"
"
"
"
156
157
158
159
160
1
2
3
4
5
6
7
"
8
9
"
201
202
203
204
205
2
4
5
6
7
8
9
234
235
236
237
238
239
240
1
2
3
4
5
6
7
"
"
"
10
11
12
13
"
8
9
10
11
12
13
"
"
"
"
"
10
11
12
13
14
"
"
14
15
16
17
18
"
"
"
"
"
14
15
16
17
18
19
20
21
"
PG299
J3
H2
G1
E1
H3
G2
H4
F2
F1
H5
G3
01
G4
E2
F3
G5
C1
F4
E3
02
C2
F5
E4
03
C3
A2
61
04
62
63
E6
05
C4
A3
06
E7
64
C5
A4
07
C6
E8
65
A5
66
08
C7
67
A6
C8
E9
68
HQ304
30
27
26
25
23
22
21
20
19
18
17
16
15
14
13
12
10
9
8
7
6
5
4
3
2
1
304
303
302
301
300
299
298
297
296
295
294
293
292
291
290
289
288
287
286
285
284
283
282
280
279
276
BG225
66
"
"
VCC*
C6
F7
A5
65
GNO*
06
C5
A4
E6
64
05
"
"
A3
C4
63
F6
A2
C3
VCC'
GNO'
04
61
C2
E5
03
C1
"
02
G6
E4
01
E3
E2
"
"
GNO*
F5
E1
F4
F3
VCC'
F2
F1
BG352
616
C17
618
VCC*
C18
017
A20
619
GNO'
C19
018
A21
620
C20
621
622
C21
020
A23
021
C22
624
C23
022
C24
VCC'
GNO*
023
C25
024
E23
C26
E24
F24
E25
026
G24
F25
F26
H23
H24
G25
G26
GNO*
J23
J24
H25
K23
VCC'
L24
K25
L25
Boundary Scan Order
165
171
174
"
177
183
186
189
195
198
201
207
210
213
219
222
225
234
237
243
246
249
258
261
270
273
279
282
285
294
297
303
306
309
315
318
321
327
330
333
"
339
342
345
351
354
357
363
December 10, 1997 (Version 5.0)
~XILINX
Pin
54.
55.
56.
57.
---=58.59.
60.
Description
I/O
I/O
-
I/O
I/O
15
16
17
18
19
20
21
22
23
24
I/O
I/O
GNO
VCC
61.
62.
63.
64.
65.
66.
67.
68.
69.
70.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
75.
76.
77.
78.
79.
80.
81.
82.
83.
84.
85.
86.
87.
88.
89.
90.
91.
92.
93.
94.
95.
96.
97.
98.
99.
HQ208
HQ240
-
19
20
21
22
23
24
25
26
27
28
29
30
31
32
23
24
25
26
27
28
29
30
31
32
33
34
35
36
-
-
I/O
VCC
71.
72.
73.
74.
PQ160
I/O
-
-
25
26
27
28
29
33
34
35
36
37
38
39
40
41
42
43
44
45
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
30
31
38
39
40
41
46
47
48
49
50
51
I/O
I/O
-
I/O
I/O
I/O
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I/O
I/O
I/O
Ml (I/O)
GNO
MO (110)
VCC
M2 (I/O)
GCK2 (110)
I/O (HOC)
I/O
I/O
I/O
I/O (LOC)
December 10, 1997 (Version 5.0)
42
43
44
45
46
47
48
49
50
55
56
57
58
59
60
61
62
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
PG299
HQ304
A8
C9
89
El0
A9
010
Cl0
Al0
All
810
811
Cll
Ell
011
A12
812
A13
E12
813
A16
A14
C13
814
013
A15
815
E13
C14
A17
014
816
C15
E14
A18
015
C16
817
818
E15
016
C17
A20
A19
C18
820
017
819
C19
F16
E17
018
C20
275
274
273
272
271
270
269
268
267
266
265
264
263
262
261
260
259
256
255
253
252
251
250
249
248
247
246
245
244
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
BG225
G4
G3
G2
Gl
G5
H3
GNO*
VCC*
H4
H5
J2
Jl
J3
J4
J5
Kl
VCC*
K2
K3
J6
L1
GNO'
L2
K4
L3
Ml
K5
M2
L4
Nl
M3
N2
K6
Pl
N3
GNO'
P2
VCC'
M4
R2
P3
L5
N4
R3
P4
BG352
Boundary Scan Order
L26
M23
M24
M25
M26
N24
N25
GNO*
VCC*
N26
P25
P23
P24
R26
R25
R24
R23
T26
T25
VCC'
-f---U24
V25
V24
U23
GNO*
Y26
W25
W24
V23
AA26
Y25
Y24
AA25
A825
AA24
Y23
AC26
AA23
A824
A025
AC24
A823
GNO*
A024
VCC'
AC23
AE24
A023
AC22
AF24
A022
AE23
366
369
375
378
381
390
393
399
402
405
411
414
417
423
426
429
435
I
438
441
447
450
453
459
462
465
471
474
477
483
486
489
495
498
501
507
510
513
522
525
528
531
540
543
546
552
555
4-291
XC5200 Series Field Programmable Gate Arrays
Pin
100.
101.
102.
103.
104.
105.
106.
107.
108.
109.
110.
111.
112.
113.
114.
115.
116.
117.
118.
119.
120.
121.
122.
123.
124.
125.
126.
127.
128.
129.
130.
131.
132.
133.
Description
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
110
110
110
I/O
I/O (ERR, INIT)
VCC
GND
110
110
I/O
I/O
138.
139.
140.
141.
142.
143.
144.
145.
4-292
HQ208
-
-
49
50
63
64
65
66
-
-
72
73
-
56
57
58
59
60
61
62
63
64
65
-
I/O
-
110
110
-
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
69
70
71
72
73
74
67
68
69
70
71
-
HQ240
-
51
52
53
54
55
-
110
-
-
110
110
110
VCC
134.
135.
136.
137.
PQ160
74
75
76
77
78
79
80
81
82
83
84
85
75
76
77
78
79
80
81
82
84
85
86
87
88
89
90
91
92
93
94
95
96
97
-
66
67
68
69
70
86
87
88
89
90
99
100
101
102
103
104
105
106
-
-
-
-
-
107
108
109
110
111
112
-
71
72
91
92
93
94
PG299
HQ304
F17
G16
D19
E18
D20
G17
F18
H16
E19
F19
E20
H17
G18
G19
H18
F20
J16
G20
H2O
J18
J19
K16
J20
K17
K18
K19
L20
K20
L19
L18
L16
L17
M20
M19
N20
M18
N19
P20
T20
N18
P19
N17
R19
R20
N16
P18
U20
P17
T19
R18
P16
'V20
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
204
203
202
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
179
178
177
175
174
173
172
171
170
169
168
167
166
165
164
163
BG225
K7
M5
R4
N5
P5
L6
GND*
R5
M6
N6
P6
VCC*
R6
M7
N7
P7
R7
L7
N8
P8
VCC*
GND*
L8
P9
R9
N9
M9
L9
R10
P10
VCC*
N10
K9
R11
P11
GND*
M10
N11
R12
L10
P12
M11
BG352
Boundary Scan Order
AE22
AF23
AD20
AE21
AF21
AC19
AD19
AE20
AF20
AC18
GND*
AD18
AE19
AC17
AD17
VCC*
AE17
AE16
AF16
AC15
AD15
AE15
AF15
AD14
AE14
AF14
VCC*
GND*
AE13
AC13
AD13
AF12
AE12
AD12
AC12
AF11
AE11
AD11
VCC*
AE9
AD9
AC10
AF7
GND*
AE8
AD8
AC9
AF6
AE7
AD7
AE6
AE5
558
564
567
570
576
579
582
588
591
594
600
603
606
612
615
618
624
627
630
636
639
642
648
651
660
663
672
675
678
684
687
690
696
699
702
708
711
714
720
723
726
732
735
738
744
747
December 10, 1997 (Version 5.0)
~XILINX
Pin
Description
PQ160
HQ208
HQ240
PG299
HQ304
BG352
Boundary Scan Order
-
-
R17
162
A06
750
I/O
-
T18
161
AC7
756
I/O
I/O
73
74
95
113
114
U19
160
R13
AF4
759
115
V19
R16
159
158
N12
P13
AF3
A05
116
117
T17
U18
157
156
K10
R14
AE3
A04
768
771
774
118
X20
155
N13
AC5
146.
I/O
147.
148.
149.
150.
-
151.
I/O
I/O
152.
I/O
153.
I/O
GNO
--
75
76
77
96
97
98
BG225
780
78
99
100
OONE
79
80
101
103
119
120
W20
V18
154
153
GNO'
P14
GNO'
A03
VCC
81
106
X19
152
VCC'
VCC'
-
82
108
154.
PROG
1/0(07)
121
122
U17
W19
151
150
M12
P15
AC4
A02
792
GCK3 (I/O)
109
110
123
155.
83
84
156.
157.
I/O
I/O
85
W18
T15
149
148
N14
L11
AC3
AB4
795
804
86
111
112
124
125
126
U16
147
M13
A01
807
158.
159.
I/O
-
-
127
V17
146
N15
AA4
810
128
X18
M14
U15
T14
W17
AA3
AB2
816
-
145
144
160.
I/O
I/O
161.
162.
I/O
I/O (06)
163.
164.
I/O
1/0
165.
I/O
I/O
166.
167.
-
-
I/O
169.
I/O
GNO
-
87
113
129
88
114
V16
89
90
115
130
131
116
132
117
118
133
134
I/O
168.
-
91
143
142
783
AC1
819
828
-----
141
J10
L12
Y3
AA2
831
834
X17
140
M15
AA1
840
U14
139
L13
W4
843
V15
T13
138
137
L14
K11
W3
Y2
846
852
-
W16
W15
136
135
Y1
V4
855
119
135
X16
134
GNO'
GNO'
-
U13
133
L15
V3
V14
W14
132
131
K12
K13
W2
U4
864
867
U3
VCC'
876
V2
879
882
858
170.
171.
172.
I/O
-
I/O
I/O
92
120
136
137
138
173.
I/O
93
121
139
V13
130
K14
-
-
140
X15
94
122
123
T12
X14
VCC'
K15
95
141
142
129
127
J12
-
X13
V12
126
123
-
Vi
T1
122
-
R4
888
891
-
870
174.
VCC
1/0(05)
175.
176.
I/O (CSO)
I/O
177.
I/O
I/O
-
-
-
124
144
W12
121
J13
R3
894
I/O
-
125
145
T11
120
J14
R2
900
96
97
126
127
146
147
X12
U11
119
118
J15
J11
R1
P3
182.
I/O
I/O
1/0(04)
98
183.
I/O
99
100
128
129
148
149
Vii
W11
117
116
H13
H14
P2
Pi
903
906
912
130
150
151
X10
115
VCC'
VCC'
Xii
114
GNO'
GNO'
-
WiD
V10
113
112
H12
H11
N2
N4
924
927
178.
179.
180.
181.
VCC
184.
185.
186.
187.
188.
189.
GNO
1/0(03)
-
915
101
131
102
103
132
133
I/O
I/O
104
134
153
154
T10
111
G14
N3
936
105
135
155
U10
-
136
137
156
157
X9
W9
G15
G13
M1
M2
939
I/O
I/O
110
109
108
G12
M3
I/O (RS)
December 10, 1997 (Version 5;0)
152
I
942
948
4-293
XC5200 Series Field Programmable Gate Arrays
---
Description
PQ160
HQ208
HQ240
138
139
159
160
161
162
163
164
165
166
Pin
190.
191.
192.
193.
1/0
1/0
1/0 (02)
1/0
-
-
194.
195.
196.
197.
1/0
1/0
1/0
1/0
108
109
140
141
-
-
GNO
110
142
VCC
198.
199.
200.
201.
202.
203.
204.
205.
206.
207.
208.
209.
210.
211.
212.
213.
214.
215.
216.
217.
218.
219.
220.
221.
222.
223.
224.
225.
226.
227.
228.
229.
230.
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0 (01)
1/0 (RCLK-BUSY/ROY)
CCLK
VCC
1/0 (TOO)
GNO
1/0 (AO, WS)
GCK4 (Ai, 1/0)
1/0
1/0
1/0 (A2, CS1)
1/0 (A3)
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
VCC
4-294
-
-
-
167
168
169
170
171
172
173
174
111
112
113
114
143
144
145
146
147
148
-
-
115
116
117
118
119
120
121
122
123
124
125
126
127
128
149
150
151
152
153
154
159
160
161
162
163
164
165
166
175
176
177
178
179
180
181
182
183
184
185
186
187
188
-
189
190
191
192
193
194
195
-
110
1/0
1/0
1/0
1/0 (DO, DIN)
1/0 (OOUT)
GNO
231.
232.
233.
234.
106
107
129
130
-
167
168
169
170
131
132
133
171
172
173
-
-
196
197
198
199
200
201
PG299
X8
V9
W8
X7
X5
V8
W7
U8
W6
X6
T8
V7
X4
U7
W5
V6
T7
X3
U6
V5
W4
W3
T6
U5
V4
Xi
V3
Wi
U4
X2
W2
V2
R5
T4
U3
Vi
R4
P5
U2
T3
U1
P4
R3
N5
T2
R2
T1
N4
P3
P2
N3
R1
HQ304
107
106
103
102
101
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
52
BG225
G11
F15
VCC*
F14
F13
G10
E15
GNO*
E14
F12
E13
015
F11
014
E12
CiS
013
C14
F10
B15
C13
VCC*
A15
GNO*
A14
B13
E11
C12
A13
B12
BG352
M4
L1
J1
K3
VCC*
J2
J3
K4
G1
GNO*
H2
H3
J4
F1
G2
G3
F2
E2
F3
G4
02
F4
E3
C2
03
E4
C3
VCC*
04
GNO*
B3
C4
05
A3
06
C6
B5
-
A4
F9
011
A12
C11
B11
E10
C7
B6
A6
08
B7
A7
09
C9
GNO*
B8
010
C10
B9
VCC*
GNO*
A11
010
C10
B10
VCC*
Boundary Scan Order
951
954
960
963
966
972
975
978
984
987
990
996
999
1002
1008
1011
1014
1020
1023
1032
1035
1038
1044
1047
0
9
15
18
21
27
30
33
39
42
45
51
54
57
63
66
69
75
78
81
87
-
December 10, 1997 (Version 5.0)
~XILINX
Pin
Description
PQ160
HQ208
HQ240
PG299
HQ304
M5
51
Pl
50
-
All
93
Nl
47
Al0
012
99
46
09
C12
102
45
C9
B12
105
44
B9
A12
111
Ml
43
A9
C13
114
208
L4
42
E9
B13
117
209
L3
41
C8
A13
126
181
210
L2
40
B8
B14
129
182
211
L1
39
GNO'
GNO'
-
235.
I/O
-
236.
I/O
-
-
237.
I/O (A4)
134
174
202
238.
I/O (A5)
135
175
203
M3
239.
I/O
-
176
205
M2
240.
I/O
136
177
206
L5
241.
I/O
137
178
207
242.
I/O
138
179
243.
I/O (A6)
139
180
I/O (A7)
140
GNO
141
244.
BG225
BG352
Boundary Scan Order
Bll
90
Additional No Connect (N.C.) Connections for HQ208, HQ240, and HQ304 Packages
HQ240
HQ208
206
207
208
1
3
51
52
53
54
102
104
105
107
155
156
157
158
219
22
37
83
98
143
158
204
-
-
HQ304
29
28
24
11
281
278
277
258
257
254
205
201
200
181
180
176
128
125
I
124
105
104
100
53
49
48
-
-
Notes:' Pins labeled VCC' are internally bonded to a VCC plane within the BG225 and BG352 packages. The external pins for the
BG225are:B2, 08, H15, R8, B14, Rl, Hl,and R15.Theexternal pins for the BG352 are:Al0, A17, B2, B25, 013, 019, 07,
G23, H4, Kl, K26, N23, P4, Ul, U26, W23, Y4, AC14, AC20, AC8, AE2, AE25, AF10, and AF17.
Pins labeled GNO' are internally bonded to a ground plane within the BG225 and BG352 packages. The external pins for
the BG225 are: Al, 012, G7, G9, H6, H8, Hl0, J8, K8, A8, F8, G8, H2, H7, H9, J7,J9, M8. The external pins for the BG352
are: A 1, A2, A5, A8, A 14, A 19, A22, A25, A26, Bl, B26, El, E26, Hl, H26, Nl, P26, Wl, W26, AB1, AB26, AE1, AE26, AF1,
AF13, AF19, AF2, AF22, AF25, AF26, AF5, AF8.
Boundary Scan Bit 0 = TOO.T
Boundary Scan Bit 1 = TOO.O
Boundary Scan Bit 1056 = BSCAN.UPO
December 10, 1997 (Version 5.0)
4-295
XC5200 Series Field Programmable Gate Arrays
Product Availability
64
PINS
84
.ca.
IDU.
TYPE
~§
-'10
~
"
XC5202
XC5204
XC5206
XC521 0
XC5215
.ca.
IDU.
.ca.
IDU.
.ca.
IDU.
a.>
a.>-
-'10
0
0
co
a..
co
CODE
156
144
a. a.
-'10
a. a.
a.>
100
100
-'10
0
0
E<
~'"
IDa.
0
.ca.
IDU.
-'10
a. a.
176
191
.ca.
IDU.
E<
~'"
c3a.
-'10
a.>-
208
'to
~a:
~o
208
.ca.
IDU.
-'10
a. a.
223
E<
~'"
c3a.
225
co
0
co
U1
Oi
I"-
a
a
a a.. a
a "a..
a..
a..
I> I- "
~
~
240
'to
~<3
0:00
:J:
co
"V is a PIP that drives from a horizontal to a vertical line.
D:V->H is a PIP that drives from a verticai.to a horizontal line.
D:C->T is a "T" PIP that drives from a cross of a T to the tail.
D:CW is a corner PIP that drives in the clockwise direction.
PO indicates the PIP is non-conducting, P1 is on.
4-308
November 20, 1997 (Version 3.0)
~XILINX
·:.··Et';-
...
':"0
..
'::C
\:~
:: .·:--et t
~.:.:.
'. :.::.:: 0:·:-- :.::.:: 0·:· :" :.: .: :
.
:
I
··El j
t·
·:.·e
1
I
j
..
t·.~.
.. '
~
. t·.;.
:
..
..'
.~'.;.
:
.. +
. t
.<:: ~O:. :" :.: : :+0,:,:-- :.: : :
+
'\
··El
..
I
'
.
a
:
.
·:.·a
.
SWITCHING
MATRIX
...
..
GRID OF GENERAL INTERCONNECT
METAL SEGMENTS
Figure 10: FPGA General-Purpose Interconnect.
Composed of a grid of metal segments that may be interconnected through switch matrices to form networks for
CLB and lOB inputs and outputs.
.
.
..
...~:.
.
I
Figure 12: CLB X andY Outputs.
The X and Y outputs of each CLB .have single contact,
direct access to inputs of adjacent CLBs
~~~~~
~~ ~ ~
-", ,; ~ g
QI'l~ ~
="l~ ,~ ~ ~
1~1I = =
~~ ~ ~
D
::
1
2
6
7
I
III
3
I
4
5
II g I
8
::
:: I
II. I
17
;"
11-
18
1111
10
e
'1'5
e
l'gll
"
::
:: 1111::
20
383 16
Figure 11: SWitch Matrix Interconnection Options for
Each Pin.
Switch matrices on the edges are different. Use Show
Matrix menu option in the XACT Design Editor.
November 20, 1997 (Version 3.0)
4-309
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
Global Buffer Inerconnect
:.:,
~.
.
ot6;,./0\·??to";·"?to':'??,o'';'>,?,o'';'. . ?t6.:?t6'i't. :6~'
'. t~"., o':;':?to';:'>,?to';:"?to";",?to"::?'o':::?to':':'.•.'? t"W ·
'1--"
"'4-
"4-
"4-
"4-
"4-
"4-
"4-
"4-"
P 4-'"
. "4-
.. 4-
.. 4-
.. 4-
•. 4-
" 4-
.• 4-
•. '-:
.
·tbi,'/ 0";':£to';:':?'o';:':?to';;:?to'.'". :?to'.':':?to';:'.'?t."'f
'4-'"
"'4-
"4-
"4-
"4-
"4-
"4-
"4-
"4-"
::6':~. :?:~:?:b:P:~:P:~:P:~:P:~.:?:"~·
o
* Unbonded lOBs (6 Places)
Figure 13:
4-310
Alternate Buffer Direct Input
XC3020A Die-Edge lOBs. The XC3020A die-edge lOBs are provided with direct access to adjacent CLBs.
November 20,1997 (Version 3.0)
~XIUNX
Longlines
The Longlines bypass the switch matrices and are intended
primarily for signals that must travel a long distance, or
must have minimum skew among multiple destinations.
Longlines, shown in Figure 14, run vertically and horizontally the height or width of the interconnect area. Each interconnection column has three vertical Longlines, and each
interconnection row has two horizontal Longlines. Two
additional Longlines are located adjacent to the outer sets
of switching matrices. In devices larger than the XC3020N
Land XC3120A FPGAs, two vertical Longlines in each col-
umn are connectable half-length lines. On the XC3020NL
and XC3120A FPGAs, only the outer Longlines are connectable half-length lines.
Longlines can be driven by a logic block or lOB output on a
column-by-column basis. This capability provides a common low skew control or clock line within each column of
logic blocks. Interconnections of these Longlines are
shown in Figure 15. Isolation buffers are provided at each
input to a Longline and are enabled automatically by the
development system when a connection is made.
I
GLOBAL
BUFFER~"
.' :" ••:.:... :.::
.:g . . . . ;. ;. ::. :
•
•
•
•
... .,
I.
1
•
I'
~
•• 1 .
••
.. ..
....
: .'
ON-CHIP
3-STATE
BUFFERS
p 't,:':'.
:
..
::.15.
.. ..
:
:
t.:·
't.:'
1"..
:
..
PULL-UP
RESISTORS
FOR ON-CHIP
OPEN DRAIN
SIGNALS
::0
::f9f .. .
EI .':'
p
t<
2 HORIZONTAL LONG LINES
"
, rsAl :-:':
'U'"
.t- ,;
..,
:
'::E}. t-·.;..
·a
.. .
..
·a····:
.' t-.:
X1243
Figure 14: Horizontal and Vertical Longlines. These Longlines provide high fan-out, low-skew signal distribution in
each row and column. The global buffer in the upper left die corner drives a common line throughout the FPGA.
November 20, 1997 (Version 3.0)
4-311
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
• FOUR OUTER LONG LINES ARE
CONNECTABLE H~LF-LENGTH LINES
o ..:,' .:.
:P.? o . .~ '7:90.:' '7:90 . :' ~o..:: '7:90. :' '7:]
0";·:,'
o :;:;
o[
.... ,
..
.. .. ,
_ 1 / 0 BLOCK CLOCK NETS
(2 PERDIE EDGE)
.... ,
... E1 \' ·eJ .\'eJ \:15. );:eJ .\;'
....,.
.. ..,
....,
.··a :(, -e.J \;' \'O.. \:eJ,.\'
+-".
a..
.
..
.
..
.
X1244 seAN
Figure 15: Programmable Interconnection of Longlines. This is provided at the edges of the routing area. Threestate buffers allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left two nonclock vertical Longlines per column (except XC3020A) and the outer perimeter Longlines may be programmed as
connectable half-length lines.
Vee
Vee
DB _+-----'
De _+-----'
Figure 16: 3-State Buffers Implement a Wired-AND Function. When all the buffer 3-state lines are High, (high
impedance), the pull-up resistor(s) provide the High output. The buffer inputs are driven by the control signals or a Low.
KEEPER CIRCUIT
Figure 17: 3-State Buffers Implement a Multiplexer. The selection is accomplished by the buffer 3-state signal.
4-312
November 20, 1997 (Version 3.0)
~XILINX
A buffer in the upper left corner of the FPGA chip drives a
global net which is available to all K inputs of logic blocks.
Using the global buffer for a clock signal provides a skewfree, high fan-out, synchronized clock for use at any or all of
the lOBs and CLBs. Configuration bits for the K input to
each logic block can select this global line or another routing resource as the clock source for its flip-flops. This net
may also be programmed to drive the die edge clock lines
for lOB use. An enhanced speed, CMOS threshold, direct
access to this buffer is available at the second pad from the
top of the left die edge.
of the 3-state buffer controls allows them to implement wide
multiplexing functions. Any 3-state buffer input can be
selected as drive for the horizontal long-line bus by applying a Low logic level on its 3-state control line. See
Figure 16. The user is required to avoid contention which
can result from multiple drivers with opposing logic levels.
Control of the 3-state input by the same signal that drives
the buffer input, creates an open-drain wired-AND function.
A logic High on both buffer inputs creates a high impedance, which represents no contention. A logic Low enables
the buffer to drive the Longline Low. See Figure 17. Pull-up
resistors are available at each end of the Longline to provide a High output when all connected buffers are non-conducting. This forms fast, wide gating functions. When data
drives the inputs, and separate signals drive the 3-state
control lines, these buffers form multiplexers (3-state busses). In this case, care must be used to prevent contention
through multiple active buffers of conflicting levels on a
common line. Each horizontal Longline is also driven by a
weak keeper circuit that prevents undefined floating levels
by maintaining the previous logic level when the line is not
driven by an active buffer or a pull-up resistor. Figure 18
shows 3-state buffers, Longlines and pull-up resistors.
A buffer in the lower right corner of the array drives a horizontal Longline that can drive programmed connections to
a vertical Longline in each interconnection column. This
alternate buffer also has low skew and high fan-out. The
network formed by this alternate buffer's Longlines can be
selected to drive the K inputs of the CLBs. CMOS threshold, high speed access to this buffer is available from the
third pad from the bottom of the right die edge.
Internal Busses
A pair of 3-state buffers, located adjacent to each CLB, permits logic to drive the horizontal Longlines. Logic operation
BIDIRECTIONAL
INTERCONNECT
BUFFERS
.II
~
I
10 CLOCKS
}1
dJ t
I--
", I
I
01
~
Of
if
0
ir
~
I
I
HG
I -'-'-
r-
I
r-"""
HH
r
II
iiCL
KIN
I
..,..,....-
-
J
)
~
:!
CJe;
~
0 1 l1
e;JeJ
~
"---- -P~
..
~
~
r----;0
0
1
HORIZONTAL LONG LINE
V
OSCILLATOR
AMPLIFIER OUTPUT
V'
DIRECTINPUT OF P47
TO AUXILIARY BUFFER
CRYSTAL OSCILLATOR
~;BUFFER
3·ST ATE INPUT
~fi
Ls
-
I;J
P47
-rr-
1
I=tf---------'
v
I~II
~~~
-t-
+
.L
,t
~
-
,
II I
I
GG
3 VERTICAL LONG
LINES PER COLUMN
GLOBAL NET
0
"
r-------.
~~
3·STATE CONTROL
1.lk
6"Ck
n
3·STATE BUFFER
~ ALTERNATE BUFFER
EJ
X1245
Figure 18: XACT Design Editor.
An extra large view of possible interconnections in the lower right corner of the XC3020A.
November 20, 1997 (Version 3.0)
4-313
I
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlLl
Crystal Oscillator
Pierce oscillator. A series resistor R2 may be included to
add to the amplifier output impedance when needed for
phase-shift control, crystal resistance matching, or to limit
the amplifier input swing to control clipping at large amplitudes. Excess feedback voltage may be corrected by the
ratio of C2/C1. The amplifier is designed to be used from 1
MHz to about one-half the specified CLB toggle frequency.
Use at frequencies below 1 MHz may require individual
characterization with respect to a series resistance. Crystal
oscillators above 20 MHz generally require a crystal which
operates in a third overtone mode, where the fundamental
frequency must be suppressed by an inductor across C2,
turning this parallel resonant circuit to double the fundamental crystal frequency, i.e., 2/3 of the desired third harmonic frequency network. When the oscillator inverter is
not used, these lOBs and their package pins are available
for general user I/O.
Figure 18 also shows the location of an internal high speed
inverting amplifier that may be used to implement an onchip crystal oscillator. It is associated with the auxiliary
buffer in the lower right corner of the die. When the oscillator is configured by MakeBits and connected as a signal
source, two special user lOBs are also configured to connect the oscillator amplifier with external crystal oscillator
components as shown in Figure 19. A divide by two option
is available to assure symmetry. The oscillator circuit
becomes active early in the configuration process to allow
the oscillator to stabilize. Actual internal connection is
delayed until completion of configuration. In Figure 19 the
feedback resistor R1, between the output and input, biases
the amplifier at threshold. The inversion of the amplifier,
together with the R-C networks and an AT-cut series resonant crystal, produce the 360-degree phase shift of the
Internal
Alternate
Clock Buffer
External
XTALI
D
D
XTAL2
(IN)
Rl
Suggested Component Values
Rl 0.5-1 MQ
R20-1kQ
(may be required for low frequency. phase
shift and/or compensation level for crystal Q)
Cl.C210-40pF
Yl 1 - 20 MHz AT-cut parallel resonant
44 PIN
I XTAL 1 (OUT)
l
XTAL2 (IN)
PLCC
30
26
68 PIN
PLCC
47
43
84PIN
PLCC
PGA
57
Jll
53
L11
R2
D
Yl
ICI
100 PIN
IC2
132 PIN
160 PIN
CQFP
PQFP
PGA
PQFP
67
61
82
P13
M13
82
76
76
164 PIN
CQFP
175 PIN
176 PIN 208 PIN
105
PGA
T14
TQFP
91
PQFP
110
99
P15
85
100
X7064
Figure 19: Crystal Oscillator Inverter. When activated in th.e MakeBits program and by selecting an ou~put network for
its buffer. the crystal oscillator inverter uses two unconfigured package pins and external components to Implement an
oscillator. An optional divide-by-two mode is available to assure symmetry.
4-314
November 20, 1997 (Version 3.0)
~XILINX
Configuration
Initialization Phase
An internal power-on-reset circuit is triggered when power
is applied. When Vee reaches the voltage at which portions
of the FPGA device begin to operate (nominally 2.5 to 3 V),
the programmable I/O output buffers are 3-stated and a
high-impedance pull-up resistor is provided for the user
I/O pins. A time-out delay is initiated to allow the power supply voltage to stabilize. During this time the power-down
mode is inhibited. The Initialization state time-out (about 11
to 33 ms) is determined by a 14-bit counter driven by a selfgenerated internal timer. This nominal 1-MHz timer is subject to variations with process, temperature and power supply. As shown in Table 1, five configuration mode choices
are available as determined by the input levels of three
mode pins; MO, M1 and M2.
Table 1: Configuration Mode Choices
CCLK
MO M1 M2
0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
1
0
1
Data
Mode
output
Master
Bit Serial
output
Master
reserved
Byte Wide Addr. = 0000 up
Byte Wide Addr.
0
1
-
0
-
Master
reserved
1
output
Peripheral Byte Wide
0
1
-
reserved
Slave
output
input
Bit Serial
FFFFdown
In Master configuration modes, the device becomes the
source of the Configuration Clock (CCLK). The beginning
of configuration of devices using Peripheral or Slave modes
must be delayed long enough for their initialization to be
completed. An FPGA with mode lines selecting a Master
configuration mode extends its initialization state using four
times the delay (43 to 130 ms) to assure that all daisychained slave devices, which it may be driving, will be
ready even if the master is very fast, and the slave(s) very
slow. Figure 20 shows the state sequences. At the end of
Initialization, the device enters the Clear state where it
clears the configuration memory. The active Low, opendrain initialization signal INIT indicates when the Initialization and Clear states are complete. The FPGA tests for the
absence of an external active Low RESET before it makes
a final sample of the mode lines and enters the Configuration state. An external wired-AND of one or more INIT pins
can be used to control configuration by the assertion of the
active-Low RESET of a master mode device or to signal a
processor that the FPGAs are not yet initialized.
If a configuration has begun, a re-assertion of RESET for a
minimum of three internal timer cycles will be recognized
and the FPGA will initiate an abort, returning to the Clear
state to clear the partially loaded configuration memory
words. The FPGA will then resample RESET and the mode
lines before re-entering the Configuration state.
During configuration, the XC3000A, XC3000L, XC3100A,
and XC3100L devices check the bit-stream format for stop
bits in the appropriate positions. Any error terminates the
configuration and pulls INIT Low.
All User 110 Pins 3-Stated with High Impedance Pull-Up, HDC=High, LDC=Low
1,-______
I_N_IT_O_utPLm_=_L_oW
________
PWRDWN
Inactive
PWRDWN
Active
I
Operates on
User Logic
Low on DONE/PROGRAM and RESET
Power-On Delay is
214 Cycles for Non-Master Mode-11 to 33 ms
2 16 Cycles for Master Mode-43 to 130 ms
Clear Is
- 200 Cycles for the
- 250 Cycles for the
- 290 Cycles for the
- 330 Cycles for the
- 375 Cycles for the
XC3020A-130 to 400 iJS
XC3030A-165 to 500 ~s
XC3042A-195 to 580 ~s
XC3064A-220 to 660 ~s
XC3090A-250 to 750 iJS
X3399
Figure 20: A State Diagram of the Configuration Process for Power-up and Reprogram.
November 20, 1997 (Version 3.0)
4-315
I
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
A re-program is initiated. when a configured XC3000 series
device senses a High-to-Low transition and subsequent >6
I1s Low level on the DONE/PROG package pin, or, if this pin
is externally held permanently Low, a High-to-Low transition and subsequent >6 I1s Low time on the RESET package pin.
The device returns to the Clear state where the configuration memory is cleared and mode lines re-sampled, as for
an aborted configuration. The complete configuration program is cleared and loaded during each configuration program cycle.
Length count control allows a system of multiple Field Programmable Gate Arrays, of assorted sizes, to begin operation in a synchronized fashion. The configuration program
11111111
0010
< 24-Bit Length Count>
1111
generated by the MakePROM program of the XACTstep
development system begins with a preamble of
111111110010 followed by a 24-bit length count representing the total number of configuration clocks needed to complete loading of the configuration program(s). The data
framing is shown in Figure 21. All FPGAs connected in
series read and shift preamble and length count in on positive and out on negative configuration clock edges. A
device which has received the preamble and length count
then presents a High Data Out until it has intercepted the
appropriate number of data frames. When the configuration
program memory of an FPGA is full and the length count
does not yet compare, the device shifts any additional data
through, as it did for preamble and length count. When the
F{GA configuration memory is full and the length count
-Dummy Bits'
]
-Preamble Code
-Configuration Program Length
-Dummy Bits (4 Bits Minimum)
o 111
o 111
o 111
I
.
.
.
o 111
o 111
1111
Header
ForXC3120
197 Configuration Data Frames
Program Data
(Each Frame Consists of:
A Start Bit (0)
A 71-Bit Data Field
Three Stop Bits
Repeated for Each Logic
Cell Array in a Daisy Chain
Postamble Code (4 Bits Minimum)
'The LCA Device Require Four Dummy Bits Min; XACT Software Generates Eight Dummy Bits
Device
Gates
CLBs
Row x Col
X5300
XC3020A
XC3020L
XC3120A
XC3030A
XC3030L
XC3130A
XC3042A
XC3042L
XC3142A
XC3142L
XC3064A
XC3064L
XC3164A
XC3090A
XC3090L
XC3190A
XC3190L
XC3195A
1,000 to 1,500
1,500 to 2,000
2,000 to 3,000
3,500 to 4,500
5,000 to 6,000
6,500 to 7,500
64
100
144
224
320
484
(8 x8)
(10 x 10)
(12 x 12)
(16 x 14)
(20 x 16)
(22 x 22)
lOBs
64
80
96
120
144
176
Flip-flops
256
360
480
688
928
1,320
Horizontal Longlines
16
20
24
32
40
44
TBUFs/Horizontal LL
9
11
13
15
17
23
75
92
108
140
172
188
Bits per Frame
(including1 start and 3 stop bits)
197
241
285
329
373
505
Program Data =
Bits x Frames + 4 bits
(excludes header)
14,779
22,176
30,784
46,064
64,160
94,944
PROM size (bits) =
Program Data
+ 40-bit Header
14,819
22,216
30,824
46,104
64,200
94,984
Frames
Figure 21: Internal Configuration Data Structure for an FPGA. This shows the preamble, length count and data
frames generated by the XACTstep Development System.
The Length Count produced by the MakeBits program = [(40-bit preamble + sum of program data + 1 per daisy chain
device) rounded up to multiple of 8]- (2 s K s 4) where K is a function of DONE and RESET timing selected. An additional
8 is added if roundup increment is less than K. K additional clocks are needed to complete start-up after length count is
reached.
4-316
November 20, 1997 (Version 3.0)
~XILINX
compares, the device will execute a synchronous start-up
sequence and become operational. See Figure 22. Two
CCLK cycles after the completion of loading configuration
data, the user I/O pins are enabled as configured. As
selected in MakeBits, the internal user-logic RESET is
released either one clock cycle before or after the I/O pins
become active. A similar timing selection is programmable
for the DONE/PROG output signal. DONE/PROG may also
be programmed to be an open drain or include a pull-up
resistor to accommodate wired ANDing. The High During
Configuration (HDC) and Low During Configuration (LDG)
are two user I/O pins which are driven active while an
FPGA is in its Initialization, Clear or Configure states. They
and DONE/PROG provide signals for control of external
logic signals such as RESET, bus enable or PROM enable
during configuration. For parallel Master configuration
modes, these signals provide PROM enable control and
allow the data pins to be shared with user logic signals.
User I/O inputs can be programmed to be either TTL or
CMOS compatible thresholds. At power-up, all inputs have
TTL thresholds and can change to CMOS thresholds at the
completion of configuration if the user has selected CMOS
thresholds. The threshold of PWRDWN and the direct clock
inputs are fixed at a CMOS level.
If the crystal oscillator is used, it will begin operation before
configuration is complete to allow time for stabilization
before it is connected to the internal circuitry.
Configuration Data
Configuration data to define the function and interconnection within a Field Programmable Gate Array is loaded from
an external storage at power-up and after a re-program signal. Several methods of automatic and controlled loading of
the required data are available. Logic levels applied to
mode selection pins at the start of configuration time determine the method to be used. See Table 1. The data may be
either bit-serial or byte-parallel, depending on the configuration mode. The different FPGAs have different sizes and
numbers of data frames. To maintain compatibility between
various device types, the Xilinx product families use compatible configuration formats. For the XC3020A, configuration requires 14779 bits for each device, arranged in 197
data frames. An additional 40 bits are used in the header.
See Figure 22. The specific data format for each device is
produced by the MakeBits command of the development
system and one or more of these files can then be combined and appended to a length count preamble and be
transformed into a PROM format file by the MakePROM
command of the XACTstep development system. A compatibility exception precludes the use of an XC2000-series
device as the master for XC3000-series devices if their
DONE or RESET are programmed to occur after their outputs become active. The Tie Option of the MakeBits program.defines output levels of unused blocks of a design
and connects these to unused routing resources. This prevents indeterminate levels that might produce parasitic
Postamble
.--12 _ _ _ _ _ 2 4 _
Last Frame
Data Frame
I~------------•• ~;~\------------.I
4
1
DIN
Preamble
Length Count
Data
Start
Bit
Length Count'
Start
Bit
The configuration data consists of a composite
• 40·bit preamble/length count, followed by one or
more concatenated FPGA programs, separated by
4-bit postambles. An additional final postamble bit
is added for each slave device and the result rounded
up to a byte boundary. The length count is two less
than the number of resulting bits.
Timing of the assertion of DONE and
termination of the INTERNAL RESET
may each be programmed to occur
one cycle before or after the I/O outputs
become active.
Heavy lines indicate the default condition
Weak Pull-Up
iii
DONE
Internal Reset
X5988
Figure 22: Configuration and Start-up of One or More FPGAs.
November 20, 1997 (Version 3.0)
4-317
I
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
supply currents. If unused blocks are not sufficient to complete the tie, the Flagnet command of EditLCA can be used
to indicate nets which must not be used to drive the remaining unused routing, as that might affect timing of user nets.
Norestore will retain the results of tie for timing analysis
with Querynet before Restore returns the design to the
untied condition. Tie can be omitted for quick breadboard
iterations where a few additional milliamps of Icc are
acceptable.
The configuration bitstream begins with eight High preamble bits, a 4-bit preamble code and a 24-bit length count.
When configuration is initiated, a counter in the FPGA is set
to zero and begins to count the total number of configuration clock cycles applied to the device. As each configuration data frame is supplied to the device, it is internally
assembled into a data word, which is then loaded in parallel
into one word of the internal configuration memory array.
The configuration loading process is complete when the
current length count equals the loaded length count and the
required configuration program data frames have been
written. Internal user flip-flops are held Reset during configuration.
Two user-programmable pins are defined in the unconfigured Field Programmable Gate Array. High During Configuration (HOC) and Low During Configuration (LDC) as well
as DONE/PROG may be used as external control signals
during configuration. In Master mode configurations it is
convenient to use LDC as an active-Low EPROM Chip
Enable. After the last configuration data bit is loaded and
the length count compares, the user 1/0 pins become
active. Options in the MakeBits program allow timing
choices of one clock earlier or later for the timing of the end
of the internal logic RESET and the assertion of the DONE
signal. The open-drain DONE/PROG output can be ANDtied with multiple devices and used as an active-High
READY, an active-Low PROM enable or a RESET to other
portions of the system. The state diagram of Figure 20 illustrates the configuration process.
Configuration Modes
Master Mode
In Master mode, the FPGA automatically loads configuration data from an external memory device. There are three
Master modes that use the internal timing source to supply
the configuration clock (CCLK) to time the incoming data.
Master Serial mode uses serial configuration data supplied
to Data-in (DIN) from a synchronous serial source such as
the Xilinx Serial Configuration PROM shown in Figure 23.
Master Parallel Low and High modes automatically use
parallel data supplied to the 00-07 pins in response to the
16-bit address generated by the FPGA. Figure 25 shows
an example of the parallel Master mode connections
required. The HEX starting address is 0000 and increments for Master Low mode and it is FFFF and decrements
4-318
for Master High mode. These two modes provide address
compatibility with microprocessors which begin execution
from opposite ends of memory.
Peripheral Mode
Peripheral mode provides a simplified interface through
which the device may be loaded byte-wide, as a processor
peripheral.
27 shows the peripheral mode connections. Processor write cycles are decoded from the common assertion of the active low Write Strobe (WS), and two
active low and one active high Chip Selects (CSO, CS1,
CS2). The FPGA generates a configuration clock from the
internal timing generator and serializes the parallel input
data for internal framing or for succeeding slaves on Data
Out (DOUT). A output High on READY/BUSY pin indicates
the completion of loading for each byte when the input register is ready for a new byte. As with Master modes, Peripheral mode may also be used as a lead device for a daisychain of slave devices.
Slave Serial Mode
Slave Serial mode provides a simple interface for loading
the Field Programmable Gate Array configuration as shown
in Figure 29. Serial data is supplied in conjunction with a
synchronizing input clock. Most Slave mode applications
are in daisy-chain configurations in which the data input is
driven from the previous FPGA's data out, while the clock is
supplied by a lead device in Master or Peripheral mode.
Data may also be supplied by a processor or other special
circuits.
Daisy Chain
The XACTstep development system is used to create a
composite configuration for selected FPGAs including: a
preamble, a length count for the total bitstream, multiple
concatenated data programs and a postamble plus an
additional fill bit per device in the serial chain. After loading
and passing-on the preamble and length count to a possible daisy-chain, a lead device will load its configuration
data frames while providing a High DOUT to possible
down-stream devices as shown in Figure 25. Loading continues while the lead device has received its configuration
program and the current length count has not reached the
full value. The additional data is passed through the lead
device and appears on the Data Out (DOUT) pin in serial
form. The lead device also generates the Configuration
Clock (CCLK) to synchronize the serial output data and
data in of down-stream FPGAs. Data is read in on DIN of
slave devices by the positive edge of CCLK and shifted out
the DOUT on the negative edge of CCLK. A parallel Master
mode device uses its internal timing generator to produce
an internal CCLK of 8 times its EPROM address rate, while
a Peripheral mode device produces a burst of 8 CCLKs for
each chip select and write-strobe cycle. The internal timing
generator continues to operate for general timing and synchronization of inputs in all modes.
November 20, 1997 (Version 3.0)
~XILINX
Special Configuration Functions
The configuration data includes control over several special
functions in addition to the normal user logic functions and
interconnect.
•
•
•
•
•
•
Input thresholds
Readback disable
DONE pull-up resistor
DONE timing
RESET timing
Oscillator frequency divided by two
Each of these functions is controlled by configuration data
bits which are selected as part of the normal XACTstep
development system bitstream generation process.
Input Thresholds
Prior to the completion of configuration all FPGA input
thresholds are TTL compatible. Upon completion of configuration, the input thresholds become either TTL or CMOS
compatible as programmed. The use of the TTL threshold
option requires some additional supply current for threshold
shifting. The exception is the threshold of the PWRDWN
input and direct clocks which always have a CMOS input.
Prior to the completion of configuration the user 1/0 pins
each have a high impedance pull-up. The configuration program can be used to enable the lOB pull-up resistors in the
Operational mode to act either as an input load or to avoid
a floating input on an otherwise unused pin.
Readback
The contents of a Field Programmable Gate Array may be
read back if it has been programmed with a bitstream in
which the Readback option has been enabled. Readback
may be used for verification of configuration and as a
method of determining the state of internal logic nodes during debugging. There are three options in generating the
configuration bitstream.
•
•
•
"Never" inhibits the Readback capability.
"One-time," inhibits Readback after one Readback has
been executed to verify the configuration.
"On-command" allows unrestricted use of Readback.
Readback is accomplished without the use of any of the
user 1/0 pins; only MO, M1 and CCLK are used. The initiation of Readback is produced by a Low to High transition of
the MO/RTRIG (Read Trigger) pin. The CCLK input must
then be driven by external logic to read back the configuration data. The first three Low-to-High CCLK transitions
clock out dummy data. The subsequent Low-to-High CCLK
transitions shift the data frame information out on the M11
RDATA (Read Data) pin. Note that the logic polarity is
always inverted, a zero in configuration becomes a one in
Readback, and vice versa. Note also that each Readback
frame has one Start bit (read back as a one) but, unlike in
configuration, each Readback frame has only one Stop bit
(read back as a zero). The third leading dummy bit men-
November 20, 1997 (Version 3.0)
tioned above can be considered the Start bit of the first
frame. All data frames must be read back to complete the
process and return the Mode Select and CCLK pins to their
normal functions.
Readback data includes the current state of each CLB flipflop, each input flip-flop or latch, and each device pad.
These data are imbedded into unused configuration bit
positions during Readback. This state information is used
by the XACTstep development system In-Circuit Verifier to
provide visibility into the internal operation of the logic while
the system is operating. To read back a uniform time-sample of all storage elements, it may be necessary to inhibit
the system clock.
Reprogram
To initiate a re-programming cycle, the dual-function pin
DONE/PROG must be given a High-to-Low transition. To
reduce sensitivity to noise, the input signal is filtered for two
cycles of the FPGA internal timing generator. When reprogram begins, the user-programmable 1/0 output buffers are
disabled and high-impedance pull-ups are provided for the
package pins. The device returns to the Clear state and
clears the configuration memory before it indicates 'initialized'. Since this Clear operation uses chip-individual internal timing, the master might complete the Clear operation
and then start configuration before the slave has completed
the Clear operation. To avoid this problem, the slave INIT
pins must be AND-wired and used to force a RESET on the
master (see Figure 25). Reprogram control is often implemented using an external open-collector driver which pulls
DONE/PROG Low. Once a stable request is recognized,
the DONE/PROG pin is held Low until the new configuration has been completed. Even if the re-program request is
externally held Low beyond the configuration period, the
FPGA will begin operation upon completion of configuration.
DONE Pull-up
DONE/PROG is an open-drain I/O pin that indicates the
FPGA is in the operational state. An optional internal pullup resistor can be enabled by the user of the XACT development system when MakeBits is executed. The DONEI
PROG pins of multiple FPGAs in a daisy-chain may be connected together to indicate all are DONE or to direct them
all to reprogram.
DONE Timing
The timing of the DONE status signal can be controlled by
a selection in the MakeBits program to occur either a CCLK
cycle before, or after, the outputs going active. See
Figure 22. This facilitates control of external functions such
as a PROM enable or holding a system in a wait state.
4-319
I
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
RESET Timing
As with DONE timing, the timing of the release of the internal reset can be controlled by a selection in the MakeBits
program to occur either a CClK cycle before, or after, the
outputs going active. See Figure 22. This reset keeps all
user programmable flip-flops and latches in a zero state
during configuration.
Crystal Oscillator Division
A selection in the MakeBits program allows the user to
incorporate a dedicated divide-by-two flip-flop between the
crystal oscillator and the alternate clock line. This guarantees a symmetrical clock signal. Although the frequency
stability of a crystal oscillator is very good, the symmetry of
its waveform can be affected by bias or feedback drive.
Bitstream Error Checking
Bitstream error checking protects against erroneous configuration.
Each Xilinx FPGA bitstream consists of a 40-bit preamble,
followed by a device-specific number of data frames. The
number of bits per frame is also device-specific; however,
each frame ends with three stop bits (111) followed by a
start bit for the next frame (0).
All devices in all XC3000 families start reading in a new
frame when they find the first 0 after the end of the previous
frame. XC3000 device does not check for the correct stop
bits, but XC3000A/XC3100A/XC3000l and XC3100l
devices check that the last three bits of any frame are actually 111.
Under normal circumstances, all these FPGAs behave the
same way; however, if the bitstream is corrupted, an
XC3000 device will always start a new frame as soon as it
finds the first 0 after the end of the previous frame, even if
the data is completely wrong or out-of-sync. Given sufficient zeros in the data stream, the device will also go Done,
4-320
but with incorrect configuration and the possibility of internal contention.
An XC3000A/XC3100A/XC3000UXC3100l device starts
any new frame only if the three preceding bits are all ones.
If this check fails, it pulls INIT low and stops the internal
configuration, although the Master CClK keeps running.
The user must then start a new configuration by applying a
>6 !!S low level on RESET.
This simple check does not protect against random bit
errors, but it offers almost 100 percent protection against
erroneous configuration files, defective configuration data
sources, synchronization errors between configuration
source and FPGA, or PC-board level defects, such as broken lines or solder-bridges.
Reset Spike Protection
A separate modification slows down the RESET input
before configuration by using a two-stage shift register
driven from the internal clock. It tolerates submicrosecond
High spikes on RESET before configuration. The XC3000
master can be connected like an XC4000 master, but with
its RESET input used instead of INIT. (On XC3000, INIT is
output only).
Soft Start-up
After configuration, the outputs of all FPGAs in a daisychain become active simultaneously, as a result of the
same CCLK edge. In the original XC3000/3100 devices,
each output becomes active in either fast or slew-rate limited mode, depending on the way it is configured. This can
lead to large ground-bounce signals. In XC3000A/
all outputs
XC3000UXC31000A/XC3100l devices,
become active first in slew-rate limited mode, reducing the
ground bounce. After this soft start-up, each individual output slew rate is again controlled by the respective configuration bit.
November 20, 1997 (Version 3.0)
~XILINX
Configuration Timing
This section describes the configuration modes in detail.
Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the DIN input. Each
rising edge of the CCLK output increments the Serial
PROM internal address counter. This puts the next data bit
on the SPROM data output, connected to the DIN pin. The
lead FPGA accepts this data on the subsequent rising
CCLKedge.
The lead FPGA then presents the preamble data (and all
data that overflows the lead device) on its DOUT pin. There
is an internal delay of 1.5 CCLK periods, which means that
• IF READBACK IS
ACTIVATED, A
5-kQ RESISTOR IS
REQUIRED IN
SERIES WITH M1
~
l
~~~I~~~~~~~~L~~6~~ ~
RESISTOR OVERCOMES THE
INTERNAL PULL-UP,
BUT IT ALLOWS M2 TO
~
BE USER I/O.
GENERALPURPOSE
USERJiO
PINS
-
DOUT
-
M2
M1
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output. Using
DONE also avoids contention on DIN, provided the early
DONE option is invoked.
T
I I
MO
DOUT changes on the falling CCLK edge, and the next
device in the daisy-chain accepts data on the subsequent
rising CCLK edge.
I
PWRDWN
___ TO DIN OF OPTIONAL
DAISY-CHAINED LeAs WITH
DIFFERENT CONFIGURATIONS
- - - TO CCLK OF OPTIONAL
DAISY-CHAINED LeAs WITH
-
HOC
--C
lDC
--C
INIT
DIFFERENT CONFIGURATIONS
-
·· )~ffi
··
-·
[/0 PINS
.-- ~~~~Ltc~= ~~J~~~~~TICAL
CONFIGURATIONS
XC3000
FPGA
---
DEVICE
~~~~ ~;~~~:I~~NTICAL
CONFIGURATIONS
+5 V
RESET
----<
II
RESET
DIN
CCLK
ClK
r------------------,
-1
Vpp
VCC
DATA
~!
SCP
Dip
CE
INIT
bE/RESET
CEO
XC17xx
(LOW RESETS THE XC17xxADDRESS POINTER)
:~:A C~~~!::I
,,
CE/RESET
,,L..__________________
.J
,:1,
X5989
Figure 23: Master Serial Mode Circuit Diagram
November 20, 1997 (Version 3.0)
4-321
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
eeLK
(Output)
Serial Data In
Serial DOUT
n-3
n-2
n-1
(Output) _ _ _ _ _ _---J ' -_ _ _ _ _ _ _- ' '- _ _ _ _ _ _ _- - J
' - _ _ _ _ _ _ _...J
X3223
Description
CCLK
Notes:
Symbol
Data In setup
1
Data In hold
2
ITDSCK
ICKDs
Min
60
°
Max
Units
ns
ns
1. At power-up, Vee must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until Vee has reached 4.0 V (2.5 V for the XC3000L). A very long Vee rise time of >100 ms, or a nonmonotonically rising Vee may require >6-~s High level on RESET, followed by a >6-~s Low level on RESET and DfP after
VCC has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is
High.
3. Master-serial-mode timing is based on slave-mode testing.
Figure 24: Master Serial Mode Programming Switching Characteristics
4-322
November 20, 1997 (Version 3.0)
~XIUNX
Master Parallel Mode
In Master Parallel mode, the lead FPGA directly addresses
an industry-standard byte-wide EPROM and accepts eight
data bits right before incrementing (or decrementing) the
address outputs.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data (and all data that overflows the lead device) on the DOUT pin. There is an inter-
*If Read.baCk is
Activated, a
5-kD: Resistor is
Required in
Series With M1
l
+5 V
+5 V.
nal delay of 1.5 CCLK periods, after the rising CCLK edge
that accepts a byte of data, and also changes the EPROM
address, until the falling CCLK edge that makes the LSB
(DO) of this byte appear at DOUT. This means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy chain accepts data on the subsequent rising
CCLK edge.
+5V
+5V
MO M1PWRDWN
5 kQ
CCLK
CCLK
5kQ
DOUT~----------------------~ DIN
DOUT
DIN
FPGA
M2
Slave #1
HDC
RCLK
GeneralPurpose
User 1/0
Pins
Other
1/0 Pins
FPGA
Slave #n
M2
A15
A15
HDC
A14
A14
LDC
A13
A13
A12 EPROM
A12
Other {
M2
HDC
GeneralPurpose
User I/O
Pins
LDC
Other {
1/0 Pins
GeneralPurpose
User 1/0
Pins
1/0 Pins
All
All
Al0
A9
Al0
A9
DIP
DIP
D7
A8
A8
RESET
Reset
D6
A7
05
A6
FPGA
Master
5kQ
CCLK
DOUT
INIT
INIT
Note: XC2000 Devices Do Not
Have INIT to HOld Off a Master
Device. Reset of a Master Device
Should be Asserted by an- External
Timing Circuit to Alrow for LeA CCLK
Variations in Clear State Time.
+5V
5 kn Each
System Reset
X5990
Figure 25: Master Parallel Mode Circuit Diagram
November 20, 1997 (Version 3.0)
4-323
I
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
AO-AI5
(output)
'>K'
_ _ _ _ _ _ _ _ _A_dd_r_es_s_fo_r_B_yt_e_n_ _ _ _ _ _.....
00-07
Address for Byte n + 1
l-CDTRAe
Byte
®TDReRCLK
(output)
/
CCLK
(output)
OOUT
(output)
X5380
RCLK
Notes:
Description
To address valid
To data setup
To data hold
RCLK High
RCLK Low
1
2
3
Symbol
T RAC
T ORC
T Rco
T RCH
T RCL
Min
0
60
0
600
4.0
Max
200
Units
ns
ns
ns
ns
)1s
1. At power-up, Vee must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long Vee rise time of> 100 ms, or a nonmonotonically rising Vee may require a >6-)1s High level on RESET, followed by a >6-)1s Low level on RESET and DIP after
Vee has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is
High.
This timing diagram shows that the EPROM requirements are extremely relaxed:
EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.
Figure 26: Master Parallel Mode Programming Switching Characteristics
4-324
November 20,1997 (Version 3.0)
~XILINX
Peripheral Mode
Peripheral mode uses the trailing edge of the logic AND
condition of the CSO, CS1, CS2, and WS inputs to accept
byte-wide data from a microprocessor bus. In the lead
FPGA, this data is loaded into a double-buffered UART-like
parallel-to-serial converter and is serially shifted into the
internal logic. The lead FPGA presents the preamble data
(and all data that overflows the lead device) on the OOUT
pin.
when the byte-wide input buffer has transferred its information into the shift register, and the buffer is ready to receive
new data. The length of the BUSY signal depends on the
activity in the UART. If the shift register had been empty
when the new byte was received, the BUSY signal lasts for
only two CCLK periods. If the shift register was still full
when the new byte was received, the BUSY signal can be
as long as nine CCLK periods.
The Ready/Busy output from the lead device acts as a
handshake signal to the microprocessor. ROY/BUSY goes
Low when a byte has been received, and goes High again
Note that after the last byte has been entered, only seven of
its bits are shifted out. CCLK remains High with OOUT
equal to bit 6 (the next-to-Iast bit) of the last byte entered.
+5V
CON TROL
SIG NALS
ADDRESS
BUS
DATA
BUS
Jl
8
MO
/
"-
"'-"'-+5V
~
DO-7
5
M1 PWR
DWN
DD-7
CCLK
ADDRESS
DECODE ~ CSO
LOGIC
FPGA
DOUT
-
-
M2
-
-
HDC
-
LDC 0--
CS1
"-
CS2
"-
WS
0,","\
~
V
f---.
I
OPTIONAL
DAISY-CHAINED
FPGAs WITH DIFFERENT
CONFIGURATIONS
GENERA LPURPOS E
USER 1/0
PINS
-
1/0 PINS
RDYIBUSY
REPROGRAM
* IF READBACK IS
ACTIVATED, A
5-kQ RESISTOR IS
REQUIRED IN SERIES
WITH M1
-
INIT
DIP
RESET
X5991
Figure 27: Peripheral Mode Circuit Diagram
November 20, 1997 (Version 3.0)
4-325
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
WRITE TO FPGA
WS,
csa, CSt
CS2
00-07
CCLK
I
.-,.,'
I
,
I
,
,
I
I
,
'", .... -'
I
'..... ",'
I
ROY/BUSY
OOUT
I
--_ ...... ----_ .....
,{ '
I'
I
I
I
,
t
"n
I
,;
,
,
I
,".-,
""
,
I
X5992
WRITE
RDY
Notes:
Description
Effective Write time required
(Assertion of eso, eS1, eS2, WS)
DIN Setup time required
DIN Hold time required
ROY/BUSY delay after end of WS
Symbol
Min
100
1
TCA
2
3
60
0
4
Toc
Tco
TWTRB
Earliest next WS after end of BUSY
5
TRBWT
0
BUSY Low time generated
6
T BUSY
2.5
Max
60
Units
ns
ns
ns
ns
ns
9
eeLK
periods
1. At power-up, Vee must rise from 2.0 V to Vee min in less than 25 ms.1f this is not possible, configuration can be delayed by
holding RESET Low until Vee has reached 4.0 V (2.5 V for the XC3000L). A very long Vce rise time of > 100 ms, or a nonmonotonically rising Vee may require a >6-l.1s High level on RESET, followed by a >6-l.1s Low level on RESET and Dip after
Vee has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration must be delayed until the INIT of all FPGAs is High.
3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and the
phase of the internal timing generator for CCLK.
4. CCLK and DOUT timing is tested in slave mode.
5. T BUSY indicates that the double-buffered parallel-la-serial converter is not yel ready 10 receive new data. The shortest TBUSY
occurs when a byte is loaded into an emply parallel-to-serial converter. The longest TBUSY occurs when a new word is
loaded into the input register before the second-level buffer has starled shifting out dala.
Note: This timing diagram shows very relaxed requirements: Data need not be held beyond the rising edge of WS. BUSY
will go active within 60 ns after the end of WS. BUSY will stay active for several microseconds. WS may be asserted
immediately after the end of BUSY.
Figure 28: Peripheral Mode Programming Switching Characteristics
November 20, 1997 (Version 3.0)
~XILINX
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input(s) of the FPGA(s). The serial configuration bitstream
must be available at the DIN input of the lead FPGA a short
set-up time before each rising CCLK edge. The lead device
then presents the preamble data (and all data that over-
flows the lead device) on its DOUT pin. There is an internal
delay of 0.5 CCLK periods, which means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy-chain accepts data on the subsequent rising
CCLKedge.
If Readback is
Activated, a
5~kQ Resistor is
Required in
Series with M 1
+5V
I
MO
M1
1
PWRDWN
Micro
Computer
5kQ
STRB
CCLK
DO
01
DIN
04
05
t--
D3
-
-
'---
-
Optional
Daisy-Chained
LeAs with
Different
Configurations
I
HOC
LDC
07
RESET
GeneralPurpose
User 1/o
Pins
+5V
FPGA
~,{
I/O Pins
06
,..-c
DOUT
-
-
02
I/O
Port
M2
O/P
INIT
RESET
X5993
Figure 29: Slave Serial Mode Circuit Diagram
November 20, 1997 (Version 3.0)
4-327
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC31 OOAlL)
DIN
Bit n + 1
CCLK
DOUT _ _ _ _ _ _ _ _ _ _ _ _ _ _
Bit _
n-l_ _ _ _ _ _ _ _ _ _---'
(Output)
Bitn
X5379
Description
CCLK
Symbol
To DOUT
3
TCCO
DIN setup
DIN hold
High time
Low time (Note 1)
Frequency
1
2
TDCC
TCCD
TCCH
TCCL
Fcc
4
5
Min
60
0
0.05
0.05
Max
Units
100
ns
ns
ns
5.0
10
/.ls
/.ls
MHz
Notes:
1. The max limit of CCLK Low time is caused by dynamic circuitry inside the FPGA.
2. Configuration must be delayed until the INIT of all FPGAs is High.
3. At power-up, Vee must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long Vee rise time of >100 ms, or a nonmonotonically rising Vee may require a >6-/.ls High level on RESET, followed by a >6-/.ls Low level on RESET and Dip after
Vee has reached 4.0 V (2.5 V for the XC3000L).
Figure
30: Slave Serial Mode Programming Switching Characteristics
4-328
November 20, 1997 (Version 3.0)
~XILINX
Program Readback Switching Characteristics
DONE/PROG
(OUTPUT)
RTRIG (MO)
_----'I ______________________________________ _
__ r-0T~1,---____
j
®TRTCC
CCLK(1)
®
__
M1Input!
RDATA Output
HI-Z
I
VALID
READBACK OUTPUT
VALID
READBACK OUTPUT
X6116
Description
Symbol
RTRIG
RTRIG High
1
TRTH
CCLK
RTRIG setup
RDATAdelay
High time
Low time
2
3
4
5
TRTCC
TCCRD
TCCHR
TCCLR
Notes:
1.
2.
3.
4.
Min
Max
250
200
0.5
0.5
Units
ns
100
ns
ns
5
Ils
Ils
During Readback, CCLK frequency may not exceed 1 MHz.
RETRIG (MO positive transition) shall not be done until after one clock following active I/O pins.
Readback should not be initiated until configuration is complete.
TCCLR is 5 Ils min to 15 Ils max for XC3000L.
November 20, 1997 (Version 3.0)
4-329
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
General XC3000 Series Switching Characteristics
DONE/PROG
/
elearState
Configuration State
\'--_---'r-
PWRDWN
c ~ote31Ui-:-----
Vcc (Valid) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ _
\ _________ .~ VCCPD
X5387
Description
Symbol
MO, M1, M2 setup time required
MO, M1, M2 hold time required
RESET Width (Low) req. for Abort
2
3
4
TMR
TRM
T MRW
DONE/PROG
Width (Low) required for Re-eonfig.
INIT response after DIP is pulled Low
5
6
T pGW
T pG1
PWRDWN (3)
Power Down V CC
RESET (2)
Notes:
4-330
V CCPD
Min
Max
1
4.5
j.ts
j.ts
j.ts
6
6
7
2.3
Units
j.ts
j.ts
V
1. At power-up, Vee must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until Vcc has reached 4.0 V (2.5 V for XC3000L). A very long Vcc rise time of >100 ms, or a nonmonotonically riSing Vee may require a >1-j.ts High level on RESET, followed by a >6-j.ts Low level on RESET and Dip after
Vcc has reached 4.0 V (2.5 V for XC3000L).
2. RESET timing relative to valid mode lines (MO, M1, M2) is relevant when RESET is used to delay configuration. The
specified hold time is caused by a shift-register filter slowing down the response to RESET during configuration.
3. PWRDWN transitions must occur while Vee >4.0 V(2.5 V for XC3000L).
November 20, 1997 (Version 3.0)
~XILINX
Device Performance
The XC3000 families of FPGAs can achieve very high performance. This is the result of
•
•
•
A sub-micron manufacturing process, developed and
continuously being enhanced for the production of
state-of-the-art CMOS SRAMs.
Careful optimization of transistor geometries, circuit
design, and lay-out, based on years of experience with
the XC3000 family.
A look-up table based, coarse-grained architecture that
can collapse multiple-layer combinatorial logic into a
single function generator. One CLB can implement up
to four layers of conventional logic in as little as 1.5 ns.
Actual system performance is determined by the timing of
critical paths, including the delay through the combinatorial
and sequential logic elements within CLBs and lOBs, plus
the delay in the interconnect routing. The AC-timing specifications state the worst-case timing parameters for the various logic resources available in the XC3000-families
architecture. Figure 31 shows a variety of elements
involved in determining system performance.
Logic block performance is expressed as the propagation
time from the interconnect point at the input to the block to
the output of the block in the interconnect area. Since combinatorial logic is implemented with a memory lookup table
within a CLB, the combinatorial delay through the CLB,
called T ILO, is always the same, regardless of the function
being implemented. For the combinatorial logic function
driving the data input of the storage element, the critical
timing is data set-up relative to the clock edge provided to
the flip-flop element. The delay from the clock source to the
output of the logic block is critical in the timing signals pro-
Clock to Output
duced by storage elements. Loading of a logic-block output
is limited only by the resulting propagation delay of the
larger interconnect network. Speed performance of the
logic block is a function of supply voltage and temperature.
See Figure 32.
Interconnect performance depends on the routing
resources used to implement the signal path. Direct interconnects to the neighboring CLB provide an extremely fast
path. Local interconnects go through switch matrices
(magic boxes) and suffer an RC delay, equal to the resistance of the pass transistor multiplied by the capacitance of
the driven metal line. Longlines carry the signal across the
length or breadth of the chip with only one access delay.
Generous on-chip signal buffering makes performance relatively insensitive to signal fan-out; increasing fan-out from
1 to 8 changes the CLB delay by only 10%. Clocks can be
distributed with two low-skew clock distribution networks.
The tools in the XACTstep Development System used to
place and route a design in an XC3000 FPGA automatically calculate the actual maximum worst-case delays
along each signal path. This timing information can be
back-annotated to the design's nellist for use in timing simulation or examined with X-Delay, a static timing analyzer.
Actual system performance is applications dependent. The
maximum clock rate that can be used in a system is determined by the critical path delays within that system. These
delays are combinations of incremental logic and routing
delays, and vary from design to design. In a synchronous
system"the maximum clock rate depends on the number of
combinatorial logic layers between re-synchronizing flipflops. Figure 33 shows the achievable clock rate as a function of the number of CLB layers.
Combinatorial
Setup
I - T C K O - - - I - T I L O - - . I . - · - - - - TICK
CLB
t-
1-+1'---TOp
Logic
!
PAD
-p
(K)
(K)
CLOC K
1-
T CKO
lOB
----.1
PAD
1..-.- ---.1
TplD
---'I
lOB
CLB
Logic
-I>
----'1
CLB
I·
TOKPO
H>,I
X3178
Figure 31: Primary Block Speed Factors. Actual timing is a function of various block fact~rs co~bine~ with routing.
factors. Overall performance can be evaluated with the XDelay timing calculator or by an optional simulation.
November 20, 1997 (Version 3.0)
4-331
I
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
..
SPECIFIED WORST-CASE VALUES
~
1'8 ~AF!) - --
1.00
0.80
~
W
D
D
~ 0.60
:J
:1cr:
oz
... .. .. ... .. ...
--- ---
__ -
.
TYPICAL COMMERCIAL
(+ 5.0 V, 25°C)
TYPICAL MILITARY
•
0.40
MIN
0.20
---
--- ---
--- ---
.,\\.\1f-",p;i,":' ...............
.. ---------- -------_ ..
r--
L _____ _
-55
-40
cg~~~~g:~~
_______
:~; ~ _
-20
25
_!JI1.tlJ.lJI.J1i'f\:! 1.4_S_V) - ..
... -----
40
70
-
i
MIN MILll}.!l:< 5"5_VJ - - - -
-----
80
100
125
TEMPERATURE (0C)
X6094
Figure 32: Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations
Power
Power Distribution
300
250
1200
~ 150
()
i
i!i
100
50
XC3000A-6
ClB levels:
Gate levels:
4 ClBs
3ClBs
2ClBs
1 ClB
(4-16)
(3-12)
(2-8)
(1-4)
Toggle
Rate
X7065
Figure 33: Clock Rate as a Function of Logic
Complexity (Number of Combinational Levels between
Flip-Flops)
4-332
Power for the FPGA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated Vee and ground ring surrounding the logic array provides power to the I/O drivers.
An independent matrix of Vee and groundlines supplies the
interior logic of the device. This power distribution grid provides a stable supply and ground for all internal logic, providing the external package power pins are all connected
and appropriately decoupled. Typically a 0.1-~F capacitor
connected near the Vee and ground pins will provide adequate decoupling.
Output buffers capable of driving the specified 4- or 8-mA
loads under worst-case conditions may be capable of driving as much as 25 to 30 times that current in a best case.
Noise can be reduced by minimizing external load capacitance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the ground pads. The I/O Block
output buffers have a slew-limited mode which should be
used where output rise and fall times are not speed critical.
Slew-limited outputs maintain their dc drive capability, but
generate less external reflections and internal noise.
November 20, 1997 (Version 3.0)
------
~~
~
~--~
~XILINX
Dynamic Power Consumption
One CLB driving three local interconnects
One global clock buffer and clock line
One device output with a 50 pF load
XC3042A
XC3042L
XC3142A
0.25
2.25
1.25
0.17
1.40
1.25
0.25
1.70
1.25
mW per MHz
mW per MHz
mW per MHz
Power Consumption
The Field Programmable Gate Array exhibits the low power
consumption characteristic of CMOS ICs. For any design,
the configuration option of TTL chip input threshold
requires power for the threshold reference. The power
required by the static memory cells that hold the configuration data is very low and may be maintained in a powerdown mode.
Typically, most of power dissipation is produced by external
capacitive loads on the output buffers. This load and frequency dependent power is 25 llW/pF/MHz per output.
Another component of 110 power is the external dc loading
on all output pins.
Internal power dissipation is a function of the number and
size of the nodes, and the frequency at which they change.
In an FPGA, the fraction of nodes changing on a given
clock is typically low (10-20%). For example, in a long
binary counter, the total activity of all counter flip-flops is
equivalent to that of only two CLB outputs toggling at the
clock frequency. Typical global clock-buffer power is
between 2.0 mW/MHz for the XC3020A and 3.5 mW/MHz
for the XC3090A. The internal capacitive load is more a
function of interconnect than fan-out. With a typical load of
three general interconnect segments, each CLB output
requires about 0.25 mW per MHz of its output frequency.
Because the control storage of the FPGA is CMOS static
memory, its cells require a very low standby current for data
retention. In some systems, this low data retention current
characteristic can be used as a method of preserving configurations in the event of a primary power loss. The FPGA
November 20,1997 (Version 3.0)
has built in powerdown logic which, when activated, will disable normal operation of the device and retain only the configuration data. All internal operation is suspended and
output buffers are placed in their high-impedance state with
no pull-ups. Different from the XC3000 family which can be
powered down to a current consumption of a few microamps, the XC31 OOA draws 5 mA, even in power-down. This
makes power-down operation less meaningful. In contrast,
leePD for the XC3000L is only 10 !lA.
To force the FPGA into the Powerdown state, the user must
pull the PWRDWN pin Low and continue to supply a retention voltage to the Vee pins. When normal power is
restored, Vee is elevated to its normal operating voltage
and PWRDWN is returned to a High. The FPGA resumes
operation with the same internal sequence that occurs at
the conclusion of configuration. Internal-I/O and logic-block
storage elements will be reset, the outputs will become
enabled and the DONE/PROG pin will be released.
When Vee is shut down or disconnected, some power
might unintentionally be supplied from an incoming signal
driving an I/O pin. The conventional electrostatic input protection is implemented with diodes to the supply and
ground. A positive voltage applied to an input (or output)
will cause the positive protection diode to conduct and drive
the Vee connection. This condition can produce invalid
power conditions and should be avoided. A large series
resistor might be used to limit the current or a bipolar buffer
may be used to isolate the input signal.
4-333
I
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
Pin Descriptions
Permanently Dedicated Pins
Once configuration is ·done, a High-to-Low transition of this
pin will cause an initialization of the FPGA and start a
reconfiguration.
vee
MOIRTRIG
Two to eight (depending on package type) connections to
the positive V supply voltage. All must be connected.
As Mode 0, this input is sampled on power-on to determine
the power-on delay (214 cycles if MO is High, 2 16 cycles if MO
is Low). Before the start of configuration, this input is again
sampled together with M1, M2 to determine the configuration mode to be used.
GND
Two to eight (depending on package type) connections to
ground. All must be connected.
PWRDWN
A Low on this CMOS-compatible input stops all internal
activity, but retains configuration. All flip-flops and latches
are reset, all outputs are 3-stated, and all inputs are interpreted as High, independent of their actual level. When
PWDWN returns High, the FPGA becomes operational with
DONE Low for two cycles of the internal 1-MHz clock.
Before and during configuration, PWRDWN must be High.
If not used, PWRDWN must be tied to Vee.
RESET
This is an active Low input which has three functions.
Prior to the start of configuration, a Low input will delay the
start of the configuration process. An internal circuit senses
the application of power and begins a minimal time-out
cycle. When the time-out and RESET are complete, the
levels of the M lines are sampled and configuration begins.
If RESET is asserted during a configuration, the FPGA is
re-initialized and restarts the configuration at the termination of RESET.
If RESET is asserted after configuration is complete, it provides a global asynchronous RESET of all lOB and CLB
storage elements of the FPGA.
CCLK
M1IRDATA
As Mode 1, this input and MO, M2 are sampled before the
start of configuration to establish the configuration mode to
be used. If Readback is never used, M1 can be tied directly
to ground or Vee. If Readback is ever used, M1 must use a
5-kn resistor to ground or Vee, to accommodate the
RDATA output.
As an active-Low Read Data, after configuration is complete, this pin is the output of the Readback data.
User I/O Pins That Can Have Special
Functions
M2
During configuration, this input has a weak pull-up resistor.
Together with MO and M1, it is sampled before the start of
configuration to establish the configuration mode to be
used. After configuration, this pin is a user-programmable
I/O pin.
HOC
During configuration, Configuration Clock is an output of an
FPGA in Master mode or Peripheral mode, but an input in
Slave mode. During Readback, CCLK is a clock input for
shifting configuration data out of the FPGA.
CCLK drives dynamic circuitry inside the FPGA. The Low
time may, therefore, not exceed a few microseconds. When
used as an input, CCLK must be "parked High". An internal
pull-up resistor maintains High when the pin is not being
driven.
DONE/pROO (DIP)
DONE is an .open-drain output, configurable with or without
an internal pull-up resistor of 2 to 8 k At the completion of
configuration, the FPGA circuitry becomes active in a synchronous order; DONE is programmed to go active High
one cycle either before or after the outputs go active.
n.
4-334
A Low-to-High input transition, after configuration is complete, acts as a Read Trigger and initiates a Readback of
configuration and storage-element data clocked by CCLK.
By selecting the appropriate Readback option when generating the bitstream, this operation may be limited to a single
Readback, or be inhibited altogether.
During configuration, this output is held at a High level to
indicate that configuration is not yet complete. After configuration, this pin is a user-programmable 1/0 pin.
LDC
During Configuration, this output is held at a Low level to
indicate that the configuration is not yet complete. After
configuration, this pin is a user-programmable 1/0 pin. LDC
is particularly useful in Master mode as a Low enable for an
EPROM, but it must then be programmed as a High after
configuration.
INIT
This is an active Low open-drain output with a weak pull-up
and is held Low during the power stabilization and internal
clearing of the configuration memory. It can be used to indicate status to a configuring microprocessor or, as a wired
November 20, 1997 (Version 3.0)
-----------~-
---
~XILlNX
AND of several slave mode devices, a hold-off signal for a
master mode device. After configuration this pin becomes a
user-programmable 110 pin.
BClKIN
This is a direct CMOS level input to the alternate clock
buffer (Auxiliary Buffer) in the lower right corner.
XTl1
This user 110 pin can be used to operate as the output of an
amplifier driving an external crystal and bias circuitry.
XTl2
This user 110 pin can be used as the input of an amplifier
connected to an external crystal and bias circuitry. The I/O
Block is left unconfigured. The oscillator configuration is
activated by routing a net from the oscillator buffer symbol
output and by the MakeBits program.
CSO, CS1, CS2, WS
These four inputs represent a set of signals, three active
low and one active High, that are used to control configuration-data entry in the Peripheral mode. Simultaneous
assertion of all four inputs generates· a Write to the internal
data buffer. The removal of any assertion clocks in the 0007 data. In Master-Parallel mode, WS and CS2 are the AO
and A 1 outputs. After configuration, these pins are userprogrammable I/O pins.
ROY/BUSY
During Peripheral Parallel mode configuration this pin indicates when the chip is ready for another byte of data to be
written to it. After configuration is complete, this pin
becomes a user-programmed I/O pin.
RClK
During Master Parallel mode configuration, each change
on the AO-15 outputs is preceded by a rising edge on
RClK, a redundant output signal. After configuration is
complete, this pin becomes a user-programmed 110 pin.
00-07
This set of eight pins represents the parallel configuration
byte for the parallel Master and Peripheral modes. After
configuration is complete, they are user-programmed I/O
pins.
AO-A1S
During Master Parallel mode, these 16 pins present an
address output for a configuration EPROM. After configuration, they are user-programmable I/O pins.
DIN
During Slave or Master Serial configuration, this pin is used
as a serial-data input. In the Master or Peripheral configuration, this is the Data 0 input. After configuration is complete, this pin becomes a user-programmed I/O pin.
OOUT
During configuration this pin is used to output serial-configuration data to the DIN pin of a daisy-chained slave. After
configuration is complete, this pin becomes a user-programmed 110 pin.
TClKIN
This is a direct CMOS-level input to the global clock buffer.
This pin can also be configured as a user programmable
I/O pin. However, since TCLKIN is the preferred input to the
global clock net, and the global clock net should be used as
the primary clock source, this pin is usually the clock input
to the chip.
Unrestricted User 1/0 Pins
110
An I/O pin may be programmed by the user to be an Input
or an Output pin following configuration. All unrestricted 110
pins, plus the special pins mentioned on the following page,
have a weak pull-up resistor of 50 kQ to 100 kQ that
becomes active as soon as the device powers up, and
stays active until the end of configuration.
Note: Before and during configuration, all outputs that are not used for the configuration process are 3-stated with
to 100 kQ pull-up resistor.
November 20, 1997 (Version 3.0)
a 50 kQ
4-335
I
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
Pin Functions During Configuration
SLAVE
SERIAL
<1:1:1>
MASTERSERIAL
<0:0:0>
PERIPH
<1:0:1>
MASTERHIGH
User
Function
<1:1:0>
Notes:
_
(I)
Note:
4-336
Generic 1/0 pins are not shown.
For a detailed description of the configuration modes, see page 321 through page 330.
For pinout details, see page 361 through page 372.
Represents a 50-kQ to 100-kQ pull-up before and during configuration.
INIT is an open drain output during configuration.
Represents an input.
Pin assignment for the XC3064A1XC3090A and XC3195A differ from those shown.
Peripheral mode and master parallel mode are not supported in the PC44 package.
Pin assignments for the XC3195A PQ208 differ from those shown.
Pin assignments of PGA Footprint PlCC sockets and PGA packages are not indentical.
The information on this page is provided as a convenient summary. For detailed pin descriptions, see the preceding two pages.
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a 50-kW to 100-kW pull-up
resistor.
November 20, 1997 (Version 3.0)
~XILINX
XC3000A Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3000A Operating Conditions
Symbol
VCC
Description
Min
Max
Units
Supply voltage relative to GND Commercial O°C to +85°C junction
4.75
5.25
V
Supply voltage relative to GND Industrial -40°C to + 100°C junction
4.5
5.5
V
V IHT
High-level input voltage -
TTL configuration
2.0
V ILT
Low-level input voltage -
TTL configuration
0
VCC
0.8
V
V IHC
High-level input voltage -
CMOS configuration
70%
100%
VCC
VILC
Low-level input voltage -
CMOS configuration
0
20%
TIN
Input signal transition time
VCC
ns
Note:
250
V
II
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C.
XC3000A DC Characteristics Over Operating Conditions
Symbol
Description
V OH
High-level output voltage (@ IOH = -4.0 mA, Vcc min)
VOL
V OH
Low-level output voltage (@ IOL = 4.0 mA, VCC min)
VOL
V CCPD
Low-level output voltage (@ IOL = 4.0 mA, V cc min)
ICCPD
Power-down supply current
High-level output voltage (@ IOH = -4.0 mA, Vcc min)
IlL
C IN
Commercial
Industrial
Power-down supply voltage (PWRDWN must be Low)
(V CC(MAX) @ T MAX)
Icco
Min
3.76
2.30
-10
V
V
0.40
3020A
3030A
3042A
3064A
3090A
Units
V
0.40
Quiescent FPGA supply current in addition to ICCPD
Chip thresholds programmed as CMOS levels
Chip thresholds programmed as TTL levels
Input Leakage Current
Max
3.86
V
V
100
160
240
340
500
flA
flA
flA
flA
flA
500
10
flA
flA
+10
flA
Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2
10
15
pF
pF
Input capacitance, PGA 175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2
16
20
pF
pF
0.17
mA
3.4
mA
IRIN
Pad pull-up (when selected) @ VIN = 0 V (sample tested)
IRLL
Horizontal Longline pull-up (when selected) @ logic Low
0.02
Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA
device configured with a MakeBits tie option.
2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed
100 mA per Vcc pin. The number of ground pins varies from the XC3020A to the XC3090A.
November 20, 1997 (Version 3.0)
4-337
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
XC3000A Absolute Maximum Ratings
Symbol
Description
Vee
V IN
Supply voltage relative to GND
VTs
TSTG
TSOL
TJ
Note:
Units
-0.5 to +7.0
V
Input voltage with respect to GND
-0.5 to Vee +0.5
V
Voltage applied to 3-state output
-0.5 to Vee +0.5
V
-65 to +150
°C
Storage temperature (ambient)
Maximum soldering temperature (10 s @ 1/16 in.)
+260
°C
Junction temperature plastic
+125
°C
Junction temperature ceramic
+150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
XC3000A Global Buffer Switching Characteristics Guidelines
Description
Speed Grade
-7
-6
Symbol
Max
Max
Units
Global and Alternate Clock Distribution 1
Either: Normal lOB input pad through clock buffer
to any CLB or lOB clock input
Or: Fast (CMOS only) input pad through clock
buffer to any CLB or lOB clock input
T plD
7.5
7.0
ns
T plDe
6.0
5.7
ns
TBUF driving a Horizontal Longline (L.L.)1
I to L.L. while T is Low (buffer active)
T J, to L.L. active and valid with single pull-up resistor
T J, to L.L. active and valid with pair of pull-up resistors
Tt to L.L. High with single pull-up resistor
Tt to L.L. High with pair of pull-up resistors
T IO
TON
TON
Tpus
TpUF
4.5
9.0
11.0
16.0
10.0
4.0
8.0
10.0
14.0
8.0
ns
ns
ns
ns
ns
TBIDI
1.7
1.5
ns
BIOI
Bidirectional buffer delay
Note: 1. Timing is based on the XC3042A, for other devices see XACT timing calculator.
4-338
November 20, 1997 (Version 3.0)
~XILINX
XC3000A CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.
Speed Grade
Symbol
Description
Combinatorial Delay
Logic Variables
A, S, C, 0, E, to outputs X or Y
FG Mode
F and FGM Mode
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
FG Mode
F and FGM Mode
Set-up time before clock K
A,S,C,D,E
Logic Variables
FG Mode
F and FGM Mode
01
Data In
Enable Clock
EC
Hold Time after clock K
A,S,C,D,E
Logic Variables
01 2
Data In
Enable Clock
EC
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Reset Direct (RD)
RDwidth
delay from RD to outputs X or Y
Global Reset (RESET Pad)1
RESET width (Low)
delay from RESET pad to outputs X or Y
-7
Min
-6
Max
Min
Max
Units
1
T llO
5.1
5.6
4.1
4.6
ns
ns
8
TCKO
4.5
4.0
ns
TOLO
9.5
10.0
8.0
8.5
ns
ns
2
TICK
TDICK
TECCK
4.5
5.0
4.0
4.5
3.5
4.0
3.0
4.0
ns
ns
ns
ns
4
6
3
5
TCKI
TCKDI
TCKEC
0
1.0
2.0
0
1.0
2.0
ns
ns
ns
11
12
TCH
TCl
FClK
4.0
4.0
113.0
3.5
3.5
135.0
ns
ns
MHz
13
9
T RPW
6.0
7
T MRW
16.0
TMRO
5.0
ns
ns
17.0
ns
ns
5.0
6.0
TRIO
14.0
19.0
Notes: 1. Timing is based on the XC3042A, for other devices see XACT timing calculator.
2. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold time requirement (TCKDI, #5) of any ClB on the same die.
November 20,1997 (Version 3.0)
4-339
II
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC31 OOAlL)
XC3000A CLB Switching Characteristics Guidelines (continued)
CLB Output (X, Y)
(Combinatorial)
CLB Input (A.B,C,D,E)
CLB Clock
I-----@ TCL ----l.~I_@ T C H - - - - - - . I
---0
CLB Input
(Direct In)
TOICK _ _
® TCKOI---J
------------~
~--------
r.---@ T ECCK _ _ Q) T CKEC
CLB Input
(Enable Clock)
----------~
CLB Output
(Flip-Flop)
CLB Input
(Reset Direct)
@ T RIO -~--+i
CLBOutput
(Flip-Flop)
X5424
4-340
November 20, 1997 (Version 3.0)
- - - - - -
----------
~XILlNX
XC3000A lOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.
Speed Grade
Symbol
Description
-7
Min
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
4
TplD
T pTG
TIKRI
Set-up Time (Input)
Pad to Clock (IK) set-up time
1
T plCK
7
T OKPO
7
10
10
9
9
8
8
ToKPo
TOPF
Tops
TTSHZ
TTSHZ
TTSON
TTSON
5
6
TOOK
T OKO
8.0
0
11
12
TIOH
T IOl
FClK
4.0
4.0
113.0
13
15
15
TRRI
T RPO
T RPO
Propagation Delays (Output)
Clock (OK) to Pad
same
Output (0) to Pad
same
3-state to Pad begin hi-Z
same
3-state to Pad active and valid
same
(fast)
(slew rate limited)
(fast)
(slew-rate limited)
(fast)
(slew-rate limited)
(fast)
(slew -rate limited)
Set-up and Hold Times (Output)
Output (0) to clock (OK) set-up time
Output (0) to clock (OK) hold time
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Global Reset Delays (based on XC3042A)
RESET Pad to Registered In
(Q)
(fast)
RESET Pad to output pad
(slew-rate limited)
Notes:
3
-6
Max
Min
4.0
15.0
3.0
14.0
Max
Units
3.0
14.0
2.5
ns
ns
ns
12.0
ns
8.0
18.0
6.0
16.0
10.0
20.0
11.0
21.0
7.0
15.0
5.0
13.0
9.0
12.0
10.0
18.0
ns
ns
ns
ns
ns
ns
ns
ns
7.0
0
ns
ns
-
-
3.5
3.5
135.0
24.0
33.0
43.0
ns
ns
MHz
23.0
29.0
37.0
ns
ns
ns
1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is
negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized.
4. T PID, T PTG, and T PICK are 3 ns higher for XTL2 when the pin is configures as a user input.
November 20,1997 (Version 3.0)
4-341
I
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
XC3000A lOB Switching Characteristics Guidelines (continued)
--.-~~--+-t---"--"'"\X
1/0 Block (I)
pID
---,.::®---T
1/0 Pad Input
__ 1 TpICK __
0)
. ._ _ _ _ _ _ _ _ _ _ _ _ _ _- J
i
1/0 Clock (IKlOK)
========
~
~@TIOL-.
1'--
@T1OH - - - . .
X
1/0 Block (RI)
_G)T1KR1:I'
_ @TOK0..::::j
I--@TOOK _
r
I/O Pad Output
(Direct)
...1@TRPol_
X
110 Block (0)
@Top ....
.I----I-@
1
....
"-0
1
I
--------------~~~---
1/0 Pad Output
(Registered)
1/0 PadTS
ToKPO
....t--t;:-®-TTSO-N----:::®:--TT-j 1----------~(~----------~~
I/O Pad Output
X5425
{OUTPUT
~NS;:~E~ ~-L'-----f-----~)L./--I-'
OUT
DIRECT IN
REGISTERED IN
~+'-----IL./
--'-'----+-----_
-+'----+---1 Q 0 f--+-+-----<
FLIP
FLOP
=D4-342
TIL or
CMOS
0'
INPUT
LATCH
THRESHOLD
PROGRAM
CONTROLLED
MULTIPLEXER
o
= PROGRAMMABLE INTERCONNECTION POINT or PIP
X3029
November 20, 1997 (Version 3.0)
~XILINX
XC3000L Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3000L Operating Conditions
Min
Max
Units
Vee
V IH
Supply voltage relative to GND Commercial O°C to +85°C junction
3.0
3.6
V
High-level input voltage -
TTL configuration
2.0
V il
Low-level input voltage -
TTL configuration
-0.3
Vee+0.3
0.8
V
TIN
Input signal transition time
250
ns
Description
Symbol
V
Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per DC.
2. Although the present (1996) devices operate over the full supply voltage range from 3.0 to 5.25 V, Xilinx reserves the right to
restrict operation to the 3.0 to 6.0 V range later, when smaller device geometries might preclude operation at 5V Operating
conditions are guaranteed in the 3.0 - 3.6 V Vee range.
I
XC3000L DC Characteristics Over Operating Conditions
Symbol
V OH
VOL
V OH
VOL
V eepo
Description
=-4.0 mA, Vee min)
Low-level output voltage (@ IOl =4.0 mA, Vee min)
High-level output voltage (@ IOH =-4.0 mA, Vee min)
Low-level output voltage (@ IOl =4.0 mA, Vee min)
High-level output voltage (@ IOH
V
V
""
V
Vee -0.2
IlA
20
+10
IlA
IlA
Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2
10
15
pF
pF
Input capacitance, PGA 175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2
15
20
pF
pF
0.17
mA
2.50
mA
Quiescent FPGA supply current in addition to leepo1
Chip thresholds programmed as CMOS levels
IRIN
0.40
10
leeo
IRll
Units
V
Power-down supply current (Vee(MAX) @ T MAX)
C IN
Max
0.2
Power-down supply voltage (PWRDWN must be Low)
leepo
III
Min
2.40
Input Leakage Current
Pad pull-up (when selected) @ V IN =0 V (sample tested)
Horizontal Longline pull-up (when selected) @ logic Low
2.30
-10
0.02
--".
V
Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA
device configured with a MakeBits tie option. Icco is in addition to IcCPD'
2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed
100 mA per Vee pin. The number of ground pins varies from the XC3020L to the XC3090L.
November 20, 1997 (Version 3.0)
4-343
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
XC3000L Absolute Maximum Ratings
Symbol
Vee
V IN
VTS
T STG
TSOL
TJ
Note:
Description
Units
Supply voltage relative to GND
Input voltage with respect to GND
Voltage applied to 3-state output
Storage temperature (ambient)
-0.5 to +7.0
V
-0.5 to Vee +0.5
-0.5 to Vee +0.5
-65 to +150
V
°C
V
Maximum soldering temperature (10 s @ 1/16 in.)
+260
°C
Junction temperature plastic
+125
Junction temperature ceramic
+150
°C
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
XC3000L Global Buffer Switching Characteristics Guidelines
Speed Grade
Description
Global and Alternate Clock Distribution'
Either: Normal lOB input pad through clock buffer
to any CLB or lOB clock input
Or: Fast (CMOS only) input pad through clock
buffer to any CLB or lOB clock input
TBUF driving a Horizontal Longline (L.L.)'
I to L.L. while T is Low (buffer active)
T t to L.L. active and valid with single pull-up resistor
Tt to L.L. High with single pull-up resistor
-8
Symbol
Max
Units
T plD
9.0
ns
T plDe
7.0
ns
T IO
TON
Tpus
5.0
12.0
24.0
ns
ns
ns
TBIDI
2.0
ns
BIOI
Bidirectional buffer delay
1. Timing is based on the XC3042A, for other devices see XACT timing calculator.
2. The use of two pull-up resistors per Longline, available on other XC3000 devices, is not a valid option for XC3000L devices.
4-344
November 20, 1997 (Version 3.0)
-----
--~--
------
~XILlNX
XC3000L CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.
-8
Speed Grade
Symbol
Description
Combinatorial Delay
Logic Variables
A, B, C, D, E, to outputs X or Y
FG Mode
F and FGM Mode
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
FG Mode
F and FGM Mode
Units
T llO
6.7
7.5
ns
ns
8
T CKO
7.5
ns
TOLO
14.0
14.8
ns
ns
2
TICK
4
6
Hold Time after clock K
A,B,C,D,E
Logic Variables
DI2
Data In
Enable Clock
EC
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
Max
1
Set-up time before clock K
A,B,C,D,E
Logic Variables
FG Mode
F and FGM Mode
DI
Data In
Enable Clock
EC
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Min
T DICK
T ECCK
5.0
5.8
5.0
6.0
ns
ns
ns
ns
3
5
7
TCKI
TCKDI
T CKEC
0
2.0
2.0
ns
ns
ns
11
12
TCH
TCl
FClK
5.0
5.0
80.0
ns
ns
MHz
13
9
T RPW
7.0
7.0
ns
ns
Global Reset (RESET Pad)1
RESET width (Low)
delay from RESET pad to outputs X or Y
TRIO
T MRW
T MRO
16.0
23.0
ns
ns
Notes: 1. Timing is based on the XC3042L, for other devices see XACT timing calculator.
2. The CLB K to Q output delay (TeKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold time requirement (TeKDI, #5) of any CLB on the same die.
November 20, 1997 (Version 3.0)
4-345
I
XC3000 Series Field Programmable Gate Arrays (XC3000AIL, XC3100AlL)
XC3000L CLB SWitching Characteristics Guidelines (continued)
CLB Output (X, y)
(Combinatorial)
CLB Input (A,B,C,D,E)
CLBClock
I-+----@ TCl - - -......_@
-0
CLB Input
(Direct In)
T01CK _ _
TCH--------1~
® TCKOI---..J
----------~
r-----~
I-+---@ T E C C K _ - 0 TCKEC
CLB Input
(Enable Clock)
----~I
CLBOutput
(Flip-Flop)
CLB Input
(Reset Direct)
-'\
~@TRPW __
~------------------------
®TRIO-t-_~
CLB Output
(Flip-Flop)
i
X5424
4-346
November 20, 1997 (Version 3.0)
"--------"-
- - - - - - - -
~XILlNX
XC3000L lOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.
-8
Speed Grade
Description
Symbol
Min
Max
Units
5.0
24.0
6.0
ns
ns
ns
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
4
T plD
T pTG
TIKRI
Set-up Time (Input)
Pad to Clock (IK) set-up time
1
T PICK
7
7
10
10
9
9
8
8
T OKPO
T OKPO
T OPF
Tops
TTSHZ
TTSHZ
TTSON
TTSON
5
6
TOOK
T OKO
12.0
0
ns
ns
11
12
T IOH
5.0
5.0
80.0
ns
ns
MHz
Propagation Delays (Output)
Clock (OK) to Pad
same
Output (0) to Pad
same
3-state to Pad begin hi-Z
same
3-state to Pad active and valid
same
(fast)
(slew rate limited)
(fast)
(slew-rate limited)
(fast)
(slew-rate limited)
(fast)
(slew -rate limited)
Set-up and Hold Times (Output)
Output (0) to clock (OK) set-up time
Output (0) to clock (OK) hold time
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Global Reset Delays (based on XC3042A)
(Q)
RESET Pad to Registered In
(fast)
RESET Pad to output pad
(slew-rate limited)
3
13
15
15
TIOl
FClK
TRRI
T RPO
T RPO
22.0
ns
12.0
28.0
9.0
25.0
12.0
28.0
16.0
32.0
ns
ns
ns
ns
ns
ns
ns
ns
25.0
35.0
51.0
ns
ns
ns
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fix1ure). Typical slew rate limited output
rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an ex1ernal source.
3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is
negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized.
4. T PID, T PTG, and T PICK are 3 ns higher for XTl2 when the pin is configures as a user input.
November 20, 1997 (Version 3.0)
4-347
I
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
XC3000L lOB Switching Characteristics Guidelines (continued)
Tp~'D
-~=-+--l-------,
.. __________
_____
110 Block (I)
---=-=-0
1/0 Pad Input
i
110 Clock (IKlOK)
~
~X~
CD
..-- 1
T PICK ----....
~
!==="@TIOL _ .
@T,OH _ _
f\--
)(
110 Block (RI)
.-0 TIKRI~I
..--0
TOOK - - . . .
-r@
-0 TOKO..:j
.... @)TRPol'-
l
110 Block (0)
@Top .....
x=-
1/0 Pad Output
(Direct)
....
I
"-0 ToKPO
--------------~*~----
1/0 Pad Output
(Registered)
j---1r-0-~-SON--~®-TTS-~J
110 PadTS
----------~(~
1/0 Pad Output
1____________~r__
X5425
OUT
DIRECT IN
REGISTERED IN
=04-348
~-";":"----I,'--.I
_+----+---------,
--""-------+---1
PROGRAM
CONTROLLED
MULTIPLEXER
o
= PROGRAMMABLE INTERCONNECTION POINT or PIP
X$029
November 20, 1997 (Version 3.0)
~XILINX
XC3100A Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3100A Operating Conditions
Symbol
Min
Max
Units
Supply voltage relative to GND Commercial O°C to +85°C junction
4.25
5.25
V
Supply voltage relative to GND Industrial-40°C to +100°C junction
4.5
5.5
V
V IHT
High-level input voltage -
TTL configuration
2.0
V
V ILT
V IHe
Low-level input voltage -
TTL configuration
0
Vee
0.8
High-level input voltage -
CMOS configuration
70%
100%
Vee
VILe
Low-level input voltage -
CMOS configuration
0
20%
TIN
Input signal transition time
Vee
ns
Vee
Note:
Description
250
V
I
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per DC.
XC3100A DC Characteristics Over Operating Conditions
Symbol
Description
V OH
High-level output voltage (@ IOH = -8.0 mA, Vee min)
VOL
V OH
Low-level output voltage (@ IOL = 8.0 mA, Vee min)
VOL
V eePD
leeo
IlL
C IN
IRIN
IRLL
High-level output voltage (@ IOH = -8.0 mA, Vee min)
Low-level output voltage (@ IOL = 8.0 mA, Vee min)
Power-down supply voltage (PWRDWN must be Low)
Min
Commercial
Industrial
V
V
0.40
v--
V
2.30
-10
Units
0.40
3.76
Quiescent LCA supply current in addition to leePD 1
Chip thresholds programmed as CMOS levels
Chip thresholds programmed as TTL levels
Input Leakage Current
Max
3.86
V
8
14
mA
mA
+10
JlA
Input capacitance, all packages except PGA 175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2
10
15
pF
pF
Input capacitance, PGA 175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2
15
20
pF
pF
Pad pull-up (when selected) @ V IN = 0 V (sample tested)
Horizontal Longline pull-up (when selected) @ logic Low
0.02
0.17
mA
0.20
2.80
mA
Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the LCA
device configured with a MakeBits tie option.
2. Total continuous output sink current may not exceed 100 mA per ground pin. The number of ground pins varies from two for
the XC3120A in the PC84 package, to eight for the XC3195A in the PQ208 or PG223 package.
November 20, 1997 (Version 3.0)
4-349
XC3000 Series Field Programmable Gate Arrays (XC3000AIL, XC31 OOAlL)
XC3100A Absolute Maximum Ratings
Symbol
Vee
V IN
VTS
TSTG
TSOL
TJ
Note:
Description
Units
Supply voltage relative to GND
Input voltage with respect to GND
Voltage applied to 3-state output
Storage temperature (ambient)
Maximum soldering temperature (10 s @ 1/16 in.)
Junction temperature plastic
Junction temperature ceramic
-0.5 to +7.0
V
V
V
-0.5 to Vee +0.5
-0.5 to Vcc +0.5
-65 to +150
°C
°C
°C
°C
+260
+125
+150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
XC3100A Global Buffer Switching Characteristics Guidelines
Description
Global and Alternate Clock Distribution 1
Either: Normal lOB input pad through clock buffer
Speed Grade ·5
Symbol Max
to any CLB or lOB clock input
Or: Fast (CMOS only) input pad through clock
buffer to any CLB or lOB clock input
TBUF driving a Horizontal Longline (L.L.)1
I to L.L. while T is Low (buffer active)
(XC31 00)
(XC3100A)
T,l, to L.L. active and valid with single pull-up resistor
T,l, to L.L. active and valid with pair of pull-up resistors
Ti to L.L. High with single pull-up resistor
Ti to L.L. High with pair of pull-up resistors
BIOI
Bidirectional buffer delay
·4
Max
·3
Max
·2
Max
·1
Max
·09
Max
Units
T plD
6.8
6.5
5.6
4.7
4.3
3.9
ns
T plDC
5.4
5.1
4.3
3.7
3.5
3.1
ns
TIO
T IO
TON
TON
Tpus
T pUF
4.1
3.6
5.6
7.1
15.6
12.0
3.7
3.6
5.0
6.5
13.5
10.5
3.1
3.1
4.2
5.7
11.4
8.8
3.1
4.2
5.7
11.4
8.1
2.9
4.0
5.5
10.4
7.1
2.1
3.1
4.6
8.9
5.9
ns
ns
ns
ns
ns
ns
TSIDI
1.4
1.2
1.0
0.9
0.85
0.75
ns
~
Note:
4-350
1. Timing is based on the XC3142A, for other devices see XACT timing calculator.
The use of two pull-up resistors per longline, available on other XC300D devices, is not a valid design option for XC31 DDA
devices.
November 20, 1997 (Version 3.0)
-----
- - - - - - - - -
~XILlNX
XC3100A CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.
-5
Speed Grade
Description
Combinatorial Delay
Logic Variables
to outputs X or Y
A, B, C, D, E,
Symbol
1
Sequential delay
Clock k to outputs X or Y
8
Clock k to outputs X or Y when Q is returned through function generators F
or G to drive X or Y
Set-up time before clock K
A,B,C,D,E
Logic Variables
DI
Data In
Enable Clock
EC
Reset Direct inactive RD
Hold Time after clock K
Logic Variables
A,B,C,D,E
DI
Data In
Enable Clock
EC
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
Global Reset (RESET Pad) 1
RESET width (Low)
(XC3142A)
delay from RESET pad to outputs X or Y
Min
-4
Max
Min
-2
-3
Max
Min
Max
Min
-1
Max
Min
-09
Max
Min
Max
Units
T ILO
4.1
3.3
2.7
2.2
1.75
1.5
ns
TCKO
3.1
2.5
2.1
1.7
1.4
1.25
ns
TOLO
6.3
5.2
4.3
3.5
3.1
2.7
ns
2 TICK
4 T DICK
6 T ECCK
3.1
2.0
3.8
1.0
2.5
1.6
3.2
1.0
2.1
1.4
2.7
1.0
1.8
1.3
2.5
1.0
1.7
1.2
2.3
1.0
1.5
1.0
2.05
1.0
ns
ns
ns
ns
3 TCKI
5 TCKDI
7 TCKEC
0
1.0
1.0
0
1.0
0.8
0
0.9
0.7
0
0.9
0.7
0
0.8
0.6
0
0.7
0.55
ns
ns
ns
11
12
TCH
TCL
FCLK
2.4
2.4
188
2.0
2.0
227
1.6
1.6
270
1.3
1.3
323
1.3
1.3
323
1.3
1.3
370
ns
ns
MHz
13 T RPW
9 TRIO
3.8
3.2
2.7
ns
ns
12.0
12.0
12.0
12.0
14.0
TMRW 14.0
12.0
12.0
12.0
T MRO
17.0
14.0
12.0
ns
ns
3.7
2.3
2.05
2.15
4.4
3.1
2.3
2.7
2.4
;:;~I',E !I,!!,,:
Notes: 1. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold time requirement (TCKDI, #5) of any CLB on the same die.
2. T ILO' TOLO and TICK are specified for 4-input functions. For 5-input functions or base FGM functions, each of these
specifications for the XC3100A family increases by 0.50 ns (-5),0.42 ns (-4) and 0.35 ns (-3), 0.35 ns (-2), 0.30 ns (-1), and
0.30 ns (-09).
November 20, 1997 (Version 3.0)
4-351
I
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC31 OOAlL)
XC3100A CLB Switching Characteristics Guidelines (continued)
CLB Output (X, Y)
(Combinatorial)
CLB Input (A,B,C,D,E)
CLB Clock
o
T
,CK
__
T
CK1
1,-
__
..,
~
@TCL
.1-- 0
•
• _@TCH
TDICK _
I
CLB Input
(Direct In)
0
_@TECCK ___
_0
TCKDI
-0
TCKEC.:j
'--
i
CLB Input
(Enable Clock)
1-----0
T CKO _ _
CLB Output
(Flip-Flop)
CLB Input
(Reset Direct)
®
T RIO _+---;~
CLB Output
(Flip-Flop)
X5424
4-352
November 20, 1997 (Version 3.0)
~XILINX
XC3100A lOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (a)
with latch transparent (XC3100A)
Clock (IK) to Registered In (a)
Set-up Time (Input)
Pad to Clock (lK) set-up time
XC3120A, XC3130A
XC3142A
XC3164A
XC3190A
XC3195A
Propagation Delays (Output)
Clock (OK) to Pad (fast)
(slew rate limited)
same
Output (0) to Pad (fast)
(slew-rate limited)
same
(XG3100A)
3-state to Pad
begin hi-Z
(fast)
same
(slew-rate limited)
3-state to Pad
active and valid (fast) (XC3100A)
(slew -rate limited)
same
Symbol
-4
-5
Speed Grade
Description
Min
Max
Min
Min
Max
Min
-1
Max
Min
-09
Max
Min
Max
Units
3
T plD
2.8
2.5
2.2
2.0
1.7
1.55
ns
4
T pTG
TIKRI
14.0
2.8
12.0
2.5
11.0
2.2
11.0
1.9
10.0
1.7
9.2
1.55
ns
ns
1 T plCK 10.9
11.0
11.2
11.5
12.0
9.4
9.5
9.7
9.9
10.3
10.6
10.7
11.0
11.2
11.6
8.9
9.0
9.2
9.4
9.8
8.0
8.1
8.3
8.5
8.9
7.2
7.3
7.5
7.7
8.1
ns
ns
ns
ns
ns
7 T OKPO
7 T OKPO
10 T OPF
5.5
14.0
4.1
5.0
12.0
3.7
4.4
10.0
3.3
3.7
9.7
3.0
3.4
8.4
3.0
3.3
6.9
2.9
10 Tops
12.1
11.0
9.0
8.7
8.0
6.5
ns
ns
ns
ns
ns
9 TTSHZ
9 TTSHZ
6.9
6.9
6.2
6.2
5.5
5.5
5.0
5.0
4.5
4.5
4.05
4.05
ns
ns
8 TTSON
8 TTSON
10.0
18.0
10.0
17.0
9.0
15.0
8.5
14.2
6.5
11.5
5.0
8.6
ns
ns
Set-up and Hold Times (Output)
Output (0) to clock (OK) set-up time
(XC3100A)
Output (0) to clock (OK) hold time
5
6
TOOK
T OKO
5.0
0
4.5
0
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11 T IOH
12 T IOl
FClK
2.4
2.4
188
2.0
2.0
227
Global Reset Delays
(a)
RESET Pad to Registered In
(XC3142A)
(XC3190A)
(fast)
RESET Pad to output pad
(Slew-rate limited)
-2
-3
Max
13 TRRI
15 T RPO
15 T RPO
18.0
29.5
24.0
32.0
1.6
1.6
270
15.0
25.5
20.0
27.0
13.0
21.0
17.0
23.0
3.6
0
3.2
0
2.9
ns
ns
1.3
1.3
323
1.3
1.3
323
1.3
1.3
370
ns
ns
MHz
13.0
21.0
17.0
23.0
13.0
21.0
17.0
22.0
14.4
21.0
17.0
21.0
ns
ns
ns
ns
P,t.t!l\1in~
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads, see
page XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is
negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized.
4. T PID, TPTG, and T PICK are 3 ns higher for XTL2 when the pin is configures as a user input.
November 20, 1997 (Version 3.0)
4-353
I
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
XC3100A lOB Switching Characteristics Guidelines (continued)
-~~-+--f.-------.
1/0 Block (I)
--=-0T p - ' D
liD Pad Input
~
1/0 Clock (iK/OK)
..______________
jX========
CD
~1
TpICK~
@T1OL
,
@T1OH - - - . .
'--
1/0 Block (RI)
,r--
_0T'KR,~1
...-0
ToOK - - - . .
___ 0
TOK'::j
\
...1@)TRPol-
I
1/0 Block (0)
@To p -....
@
1
I
.1---
110 Pad Output
I
...
"'-0
______________
~i~ __
(Direct)
TOKPO
110 Pad Output
(Registered)
110 Pad TS
...1---ir-0-TTS-ON----=®=--TT-j 1--------~(
110 Pad Output
~
X5425
(OUTPUT
~NS;:~E~ -~~-+------)L'/--I-'
OUT --::c"----1.L/
DIRECT IN
REGISTERED IN
n4-354
_--'----+---------,
--+-''-------+---1
PROGRAM
CONTROLLED
MULTIPLEXER
o
== PROGRAMMABLE INTERCONNECTION POINT or PIP
X3029
November 20, 1997 (Version 3.0)
~XILINX
XC3100L Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3100L Operating Conditions
Min
Max
Units
Vee
V IH
Supply voltage relative to GND Commercial O°C to +85°C junction
Description
3.0
3.6
V
High-level input voltage
2.0
Vee + 0.3
V
V IL
Low-level input voltage
-0.3
0.8
V
TIN
Input signal transition time
250
ns
Symbol
Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per DC.
2. Although the present (1996) devices operate over the full supply voltage range from 3.0 V to 5.25 V, Xilinx reserves the right
to restrict operation to the 3.0 and 3.6 V range later, when smaller device geometries might preclude operation @ 5 V.
Operating conditions are guaranteed in the 3.0 - 3.6 V Vee range.
I
XC3100L DC Characteristics Over Operating Conditions
Symbol
V OH
VOL
V eePD
leeo
IlL
C IN
Description
= -4.0 mA, Vee min)
High-level output voltage (@ IOH = -100.0 /lA, Vee min)
Low-level output voltage (@ IOH = 4.0 mA, Vee min)
Low-level output voltage (@ IOH =+100.0 /lA, Vee min)
High-level output voltage (@ IOH
Power-down supply voltage (PWRDWN must be Low)
Min
Units
V
Vee -0.2
V
0.40
0.2
2.30
Quiescent FPGA supply current
Chip thresholds programmed as CMOS levels1
-10
Input Leakage Current
Max
2.4
V
V
1.5
V
mA-
+10
/lA
Input capacitance, all packages except PGA175
(sample tested)
All pins except XTL 1 and XTL2
XTL 1 and XTL2
10
15
pF
pF
Input capacitance, PGA175
(sample tested)
All pins except XTL 1 and XTL2
XTL 1 and XTL2
15
20
pF
pF
0.02
0.17
mA
0.20
2.80
mA
= 0 V (sample tested)
IRIN
Pad pull-up (when selected) @ VIN
IRLL
Horizontal long line pull-up (when selected) @ logic Low
Notes: 1. With no output current loads, no active input or long line pull-up resistors, all package pins at Vee or GND, and the FPGA
configured with a MakeBits tie option.
2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source current may not
exceed 100 mA per Vee pin. The number of ground pins varies from the XC3142L to the XC3190L.
November 20, 1997 (Version 3.0)
4-355
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
XC3100L Absolute Maximum Ratings
Symbol
Vee
V IN
VTS
T STG
TsOL
TJ
Note:
Description
Supply voltage relative to GND
Input voltage with respect to GND
Voltage applied to 3-state output
Storage temperature (ambient)
Maximum soldering temperature (10 s @ 1/16 in.)
Junction temperature plastic
Junction temperature ceramic
-0.5 to +7.0
-0.5 to Vee +0.5
-0.5 to Vee +0.5
-65 to +150
+260
+125
+150
Units
V
V
V
DC
DC
DC
DC
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
XC3100L Global Buffer Switching Characteristics Guidelines
Description
Global and Alternate Clock Distribution'
Either:Normal lOB input pad through clock buffer
to any CLB or lOB clock input
Or: Fast (CMOS only) input pad through clock
buffer to any CLB or lOB clock input
TBUF driving a Horizontal Longline (L.L.)'
I to L.L. while T is Low (buffer active)
T J, to L.L. active and valid with single pull-up resistor
Ti to L.L. High with single pull-up resistor
BIOI
Bidirectional buffer delay
-3
Max
-2
Max
Units
T plD
5.6
4.7
ns
T plDe
4.3
3.7
ns
T IO
TON
Tpus
3.1
4.2
11.4
3.1
4.2
11.4
ns
ns
ns
0.9
ns
Speed Grade
Symbol
1.0
TBIDI
I;;:;,:
i';i><
Notes: 1. Timing is based on the XC3142L, for other devices see XACT timing calculator.
2. The use of two pull-up resistors per longline, available on other XC3000 devices, is not a valid option for XC31 OOL devices.
4-356
November 20, 1997 (Version 3.0)
~XILINX
XC3100L CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.
Speed Grade
Symbol
U"';Ov"I'''V'
Combinatorial Delay
Logic Variables A, B, C, D, E, to outputs X or Y
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
Max
Units
2.7
2.2
ns
8
T CKO
2.1
1.7
ns
T OlO
4.3
3.5
ns
2
4
6
TICK
T DICK
T ECCK
Hold Time after clock K
Logic Variables
Data In
Enable Clock
A,B,C,D,E
DI
EC
3
5
7
TCKI
TCKDI
T CKEC
11
12
13
9
(RESET
Min
T llO
A,B,C,D,E
DI
EC
RD
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
Max
1
Set-up time before clock K
Logic Variables
Data In
Enable Clock
Reset Direct Inactive
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
-2
-3
Min
2.1
1.4
2.7
1.0
1.8
1.3
2.5
1.0
ns
ns
ns
ns
0
0.9
0.7
0
0.9
0.7
ns
ns
ns
TCH
TCl
FClK
1.6
1.6
270
1.3
1.3
325
ns
ns
MHz
T RPW
2.7
2.3
3.1
TRIO
2.7
Global Reset
Pad)
RESET width (Low)
(XC3142L)
delay from RESET pad to outputs X or Y
T MRW
12.0
ns
ns
12.0
12.0
TMRO
ns
ns
12.0
I;::;;:::.:.:"::::
Notes:
1. The CLB K to Q delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data
In hold time requirement (TCKDI, #5) of any CLB on the same die.
2. TllO, TOlO and TICK are specified for 4-input functions. For 5-input functions or base FGM functions, each of these
specifications for the XC31 DOL family increase by 0.35 ns (-3) and 0.29 ns (-2).
November 20, 1997 (Version 3.0)
4-357
I
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
XC3100L CLB Switching Characteristics Guidelines (continued)
CLB Output (X, Y)
(Combinatorial)
CLB Input (A,B,C,D,E)
CLB Clock
----@ TCl ----;.~I_@ T cH-----~~1
CLB Input
(Direct In)
CLB Input
(Enable Clock)
CLB Output
(Flip-Flop)
CLB Input
(Reset Direct)
®
TRIO -f+--P-I
CLB Output
(Flip-Flop)
X5424
4-358
November 20, 1997 (Version 3.0)
~XILINX
XC3100L lOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.
~~~~,
Speed Grade
Symbol
't"'U'
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (0) with latch (XC3100L)
transparent
Clock (IK) to Registered In (0)
3
TplD
TpTG
4
TIKRI
Set-up Time (Input)
Pad to Clock (IK) set-up time
1
T plCK
-2
-3
Min
Max
Max
Units
2.2
11.0
2.0
11.0
ns
ns
2.2
1.9
ns
9.5
9.9
XC3142L
XC3190L
Min
9.0
9.4
ns
ns
Propagation Delays (Output)
Clock (OK) to Pad
(fast)
same
(slew rate limited)
Output (0) to Pad
(fast)
same
(slew-rate limited)(XC3100L)
(fast)
3-state to Pad begin hi-Z
(slew-rate limited)
same
3-state to Pad active and valid (fast)(XC31 OOL)
same
(slew -rate limited)
7
7
10
10
9
9
8
8
TOKPoTOK
PO
T OPF
T OPF
TTSHZ
TTSHZ
TTSON
TTSON
Set-up and Hold Times (Output)
Output (0) to clock (OK) set-up time (XC3100L)
Output (0) to clock (OK) hold time
5
6
TOOK
T_QKO
4.0
0
3.6
0
ns
ns
11
12
T IOH
T IOl
1.6
1.6
270
1.3
1.3
325
ns
ns
MHz
Clock
Clock High time
Clock Low time
Export Control Maximum flip-flop toggle rate
Global Reset Delays
RESET Pad to Registered In (0)
(XC3142L)
(XC3190L)
(fast)
RESET Pad to output pad
(slew-rate limited)
FTOG
13
TRRI
15
15
TRPO
T RPO
4.0
9.7
3.0
8.7
5.0
5.0
8.5
14.2
4.4
10.0
3.3
9.0
5.5
5.5
9.0
15.0
16.0
21.0
17.0
23.0
ns
ns
ns
ns
ns
ns
ns
ns
16.0
21.0
17.0
~-
ns
ns
ns
ns
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (lK). In order to calculate system set-up time, subtract
ciock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is
negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized.
November 20, 1997 (Version 3.0)
4-359
I
XC3000 Series· Field I;'rogrammable Gate Arrays (XC3000AlL, XC3100AlL)
XC3100L lOB Switching Characteristics Guidelines (continued)
1/0 Block (I)
---=-""'"®T'D
p
-
1/0 Pad Input
i
-~=-+--l-~
.. __________
~
~X~
______
CD Tp1CK_
_1
.
I/O Clock (lKlOK)
!=="@T,OL
@TIOH~
)(
I/O Block (RI)
1-0 TOOK _
.... 0
TIKRI~I
Cr-@
_0
TOK0..:j
-.I@TRPOI-
J,
I/O Block (0)
@Top -+--
f-
I/O Pad Output
(Direct)
I
.....
"-0
--------------~*~---
1/0 Pad Output
(Registered)
I/O
~
T OKPO
j---1r-0-~-SON--~®-TTS-.J
__________
PadTS
----------~(~
1/0 Pad Output
1-
~r-X5425
(OUTPUT
~N~::E~ --+:r......-l------)L../--i-,
OUT
DIRECT IN
REGISTERED IN
---c-"----1L./
_-+'----+_____- .
--+'''------+---1
TTL or
CMOS
or
LATCH
j)-
PROGRAM
CONTROLLED
MULTIPLEXER
4-360
INPUT
THRESHOLD
o=
PROGRAMMABLE INTERCONNECTION POINT or PIP
X3029
November 20, 1997 (Version 3.0)
~XILINX
XC3000 Series Pin Assignments
Xilinx offers the six different array sizes in the XC3000 families in a variety of surface-mount and through-hole package
types, with pin counts from 44 to 223.
Each chip is offered in several package types to accommodate the available PC board space and manufacturing technology.
Most package types are also offered with different chips to accommodate design changes without the need for PC board
changes.
Note that there is no perfect match between the number of bonding pads on the chip and the number of pins on a package.
In some cases, the chip has more pads than there are pins on the package, as indicated by the information ("unused" pads)
below the line in the following table. The lOBs of the unconnected pads can still be used as storage elements if the specified
propagation delays and set-up times are acceptable.
In other cases, the chip has fewer pads than there are
pins on the package; therefore, some package pins are
connected (n.c.), as shown above the line in the following table.
not
I
XC3000 Series 44-Pin PLCC Pinouts
XC3000A, XC3000L, and XC31 OOA families have identical pinouts
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
XC3030A
GND
I/O
I/O
I/O
I/O
I/O
PWRDWN
TCLKIN-I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
M1-RDATA
MO-RTRIG
M2-1/0
HOC-I/O
LDC-I/O
I/O
INIT-I/O
Pin No.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
XC3030A
GND
I/O
I/O
XTL2(IN)-1/0
RESET
DONE-PGM
I/O
XTL 1(OUT)-BCLK-I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
DIN-I/O
DOUT-I/O
CCLK
I/O
I/O
I/O
I/O
Peripheral mode and Master Parallel mode are not supported in the PC44 package
November 20,1997 (Version 3.0)
4-361
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
XC3000 Series 64-Pin Plastic VQFP Pinouts
XC3000A, XC3000L, and XC3100A families have identical pinouts
Pin No.
1
2
3
4
5
6
7
A1-CS2-1/0
A2-1/0
A3-1/0
A4-1/0
A14-1/0
Pin No.
XC3030A
33
34
M2-1/0
HOC-liD
35
liD
36
37
LOC-I/O
liD
liD
liD
8
GND
38
39
40
9
10
A13-1/0
41
GND
A6-1/0
42
11
12
A12-1/0
43
A7-1/0
44
13
A11-1/0
45
14
A8-1/0
46
liD
liD
liD
liD
liD
15
16
A10-1/0
47
XTAL2(IN)-1/0
A9-1/0
17
PWRON
48
49
RESET
OONE-PG
18
TCLKIN-I/O
50
19
I/O
51
07-1/0
XTAL 1(OUT)-BCLKIN-I/O
20
21
52
23
liD
liD
liD
liD
24
VCC
25
26
liD
liD
56
57
58
03-1/0
CS1-1/0
27
I/O
59
02-1/0
28
29
liD
liD
60
61
ROY/BUSY-RCLK-I/O
30
31
I/O
M1-ROATA
63
OO-OIN-I/O
OOUT-I/O
32
MO-RTRIG
64
CCLK
22
4-362
-
XC3030A
AO-WS-I/O
A5-1/0
INIT-I/O
06-1/0
05-1/0
53
54
CSO-I/O
55
04-110
62
VCC
01-110
November 20, 1997 (Version 3.0)
- - -
~~----~-~-~
~XILINX
XC3000 Series 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
68PLCC
XC3030A XC3020A
68 PLCC
XC3020A, XC3030A,
XC3042A
84 PLCC
84PGA
XC3030A XC3020A
XC3020A, XC3030A,
XC3042A
84 PLCC
84PGA
10
10
PWRON
12
82
44
44
RESET
54
Kl0
11
11
TCLKIN~I/O
13
C2
45
45
OONE-PG
55
Jl0
12
-
110'
14
81
46
46
07-1/0
56
Kl1
13
12
110
15
C1
47
47
XTL 1(OUT)-BCLKIN-I/O
57
Jl1
14
13
110
16
02
48
48
06-1/0
58
Hl0
-
-
110
17
01
-
-
110
59
H11
15
14
110
18
E3
49
49
05-1/0
60
FlO
16
15
110
19
E2
50
50
CSO-I/O
61
Gl0
-
16
110
20
E1
51
51
04~1I0
62
Gl1
17
17
110
21
F2
-
-
110
63
G9
18
18
VCC
22
F3
52
52
VCC
64
F9
19
19
110
23
G3
53
53
03-1/0
65
Fll
-
-
110
24
G1
54
54
CSH/O
66
El1
20
20
110
25
G2
55
55
02-1/0
67
E10
-
21
110
26
F1
-
-
21
22
110
27
H1
-
22
-
110
28
H2
56
23
23
110
29
J1
57
24
24
110
30
Kl
58
25
25
Ml~ROATA
31
J2
59
26
26
MO~RTRIG
32
L1
60
27
27
M2-1I0
33
K2
61
28
28
HOC-liD
34
K3
29
29
110
35
30
30
LOC-I/O
-
31
110
-
110
68
E9
110'
69
011
56
OHIO
70
010
57
ROY/8USY-RCLK-1/0
71
C11
58
OO-OIN~IIO
72
811
59
OOUT-IIO
73
Cl0
60
CCLK
74
A11
61
AO-WS-IIO
75
810
62
62
A1-CS2-1I0
76
B9
L2
63
63
A2-1I0
77
A10
36
L3
64
64
A3-1I0
78
A9
37
K4
-
110'
79
B8
110'
38
L4
-
-
110'
80
A8
86
-
31
32
110
39
J5
65
65
A15-1I0
81
32
33
110
40
K5
66
66
A4-1I0
82
B7
33
-
110'
41
L5
67
67
A14-1I0
83
A7
34
34
INIT-I/O
42
K6
68
68
A5-1I0
84
C7
35
35
GNO
43
J6
1
1
GNO
1
C6
36
36
110
44
J7
2
2
A13-1I0
2
A6
37
37
110
45
L7
3
3
A6-1I0
3
A5
38
38
110
46
K7
4
4
A12-1I0
4
85
39
39
I/O
47
L6
5
5
A7-1I0
5
C5
-
40
110
48
L8
-
41
110
49
K8
-
-
40
110'
50
L9
6
41
110'
51
L10
~~-------
------.
lID'
6
A4
110'
7
84
6
All-liD
8
A3
7
7
A8-1I0
9
A2
42
42
110
52
K9
8
8
A10-1I0
10
B3
43
43
XTL2(IN)-1I0
53
L11
9
9
A9-110
11
Al
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.
This table describes the pinouts of three different chips in three different packages. The pin-description column lists 84 of the
118 pads on the XC3042A (and 84 of the 98 pads on the XC3030A) that are connected to the 84 package pins. Ten pads,
indicated by an asterisk, do not exist on the XC3020A, which has 74 pads; therefore the corresponding pins on the 84-pin
packages have no connections to an XC3020A. Six pads on the XC3020A and 16 pads on the XC3030A, indicated by a
dash (-) in the 68 PLCCcolumn, have no connection to the 68 PLCC, but are connected to the 84-pin packages.
November 20, 1997 (Version 3.0)
4-363
I
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
XC3064A1XC3090AIXC3195A 84-Pin PLCC Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
PLCC Pin Number
XC3064A,XC3090A,XC3195A
PLCC Pin Number
XC3064A,XC3090A,XC3195A
12
PWRDN
54
RESET
13
TCLKIN-I/O
55
DONE-PG
14
I/O
56
D7-1/0
15
I/O
57
XTL 1(OUT)-BCLKIN-I/O
16
I/O
58
D6-1/0
17
I/O
59
I/O
18
I/O
60
D5-1/0
19
I/O
61
CSO-I/O
20
I/O
62
D4-1/0
21
GND'
63
I/O
22
VCC
64
VCC
23
I/O
65
GND'
24
I/O
66
D3-1/0'
25
I/O
67
CS1-1/0'
26
I/O
68
D2-1/0'
27
I/O
69
I/O
28
I/O
70
DH/O
29
I/O
71
RDY/BUSY-RCLK-I/O
30
I/O
72
DO-DIN-I/O
31
Ml-RDATA
73
DOUT-I/O
32
MO-RTRIG
74
CCLK
33
M2-1/0
75
AO-WS-I/O
34
HDC-I/O
76
Al-CS2-1/0
35
I/O
77
A2-1/0
36
LDC-I/O
78
A3-1/0
37
I/O
79
I/O
38
I/O
80
I/O
39
I/O
81
A15-1/0
40
I/O
82
A4-1/0
41
INIT/I/O'
83
A14-1/0
42
VCC'
84
AS-I/O
43
GND
1
GND
44
I/O
2
VCC'
45
I/O
3
A13-1/0'
46
I/O
4
AG-I/O'
47
I/O
5
A12-1/0'
48
I/O
6
A7-1/0'
49
I/O
7
I/O
50
I/O
8
All-I/O
51
I/O
9
AS-I/O
52
I/O
10
Al0-1/0
53
XTL2(IN)-1/0
11
A9-1/0
._.-
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.
, In the PC84 package, XC3064A, XC3090A and XC3195A have additional VCC and GND pins and thus a different pin
definition than XC3020AIXC3030AIXC3042A.
4-364
November 20, 1997 (Version 3.0)
~XILINX
XC3000 Series 100-Pin QFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Pin No.
TQFP
CQFP PQFP VQFP
XC3020A
XC3030A
XC3042A
Pin No.
TQFP
CQFP PQFP VQFP
XC3020A
XC3030A
XC3042A
Pin No.
TQFP
CQFP PQFP VQFP
XC3020A
XC3030A
XC3042A
1
16
13
GND
35
50
47
I/O'
69
84
81
1/0'
2
17
14
A13-1/0
36
51
48
I/O'
70
85
82
I/O'
3
18
15
AS-I/O
37
52
49
M1-RD
71
86
83
I/O
4
19
16
A12-1/0
38
53
50
GND'
72
87
84
D5-1/0
5
20
17
39
54
51
MO-RT
73
88
85
CSO-I/O
6
21
18
I/O'
40
55
52
VCC'
74
89
86
D4-1/0
7
22
19
I/O'
41
56
53
M2·1/0
75
90
87
I/O
8
23
20
A11-1/0
42
57
54
HDC·I/O
76
91
88
VCC
A7-1/0
~
~~---
9
24
21
A8-1/0
43
58
55
I/O
77
92
89
D3-1/0
10
25
22
A10-1/0
44
59
56
LOC-I/O
78
93
90
CST-I/O
D2-1/0
11
26
23
A9-1/0
45
60
57
I/O'
79
94
91
12
27
24
VCC'
46
61
58
I/O'
80
95
92
I/O
13
28
25
GND'
47
62
59
I/O
81
96
93
I/O'
14
29
26
PWRDN
48
63
60
I/O
82
97
94
I/O'
15
30
27
TCLKIN·I/O
49
64
61
I/O
83
98
95
D1-1/0
16
31
28
I/O"
50
65
62
INIT-I/O
84
99
96
RDY/BUSY-RCLK·I/O
I
17
32
29
I/O'
51
66
63
GND
85
100
97
DO-DIN-I/O
18
33
30
I/O'
52
67
64
I/O
86
1
98
DOUT-I/O
19
34
31
I/O
53
68
65
I/O
87
2
99
CCLK
20
35
32
I/O
54
69
66
I/O
88
3
100
VCC'
21
36
33
I/O
55
70
67
I/O
89
4
1
GND'
22
37
34
I/O
56
71
68
I/O
90
5
2
AO-WS-I/O
23
38
35
I/O
57
72
69
I/O
91
6
3
A1-CS2-1/0
24
39
36
I/O
58
73
70
I/O
92
7
4
I/O"
25
40
37
I/O
59
74
71
I/O'
93
8
5
A2-1/0
----=c,~~-
26
41
38
VCC
60
75
72
I/O'
94
9
6
A3-1/0
27
42
39
1/0
61
76
73
XTL2-1/0
95
10
7
I/O'
28
43
40
I/O
62
77
74
GND'
96
11
8
I/O'
29
44
41
I/O
63
78
75
RESET
97
12
9
A15-1/0
30
45
42
I/O
64
79
76
VCC'
98
13
10
A4-1/0
31
46
43
I/O
65
80
77
DONE-PG
99
14
11
A14-1/0
100
15
12
A5-1/0
32
47
44
I/O
66
81
78
D7-1/0
33
48
45
I/O
67
82
79
BCLKIN-XTL1-I/O
34
49
46
I/O
68
83
80
D6-1/0
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited .
• This table describes the pinouts of three different chips in three different packages. The pin-description column lists 100 of
the 118 pads on the XC3042A that are connected to the 100 package pins. Two pads, indicated by double asterisks, do not
exist on the XC3030A, which has 98 pads; therefore the corresponding pins have no connections. Twenty-six pads,
indicated by single or double asterisks, do not exist on the XC3020A, which has 74 pads; therefore, the corresponding pins
have no connections. (See table on page 361.)
November 20, 1997 (Version 3.0)
4-365
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
PGA
Pin
Number
C4
A1
C3
B2
B3
A2
B4
CS
A3
A4
BS
C6
AS
B6
A6
B7
C7
C8
A7
B8
A8
A9
B9
C9
A10
B10
A11
C10
B11
A12
B12
A13
C12
XC3042A
XC3064A
GND
PWRDN
I/O-TCLKIN
I/O
I/O
I/O'
I/O
I/O
I/O'
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O'
I/O
I/O
I/O'
I/O
I/O'
I/O
PGA
Pin
Number
B13
C11
A14
D12
C13
B14
C14
E12
D13
D14
E13
F12
E14
F13
F14
G13
G14
G12
H12
H14
H13
J14
J13
K14
J12
K13
L14
L13
K12
M14
N14
M13
L12
XC3042A
XC3064A
M1-RD
GND
MO-RT
PGA
Pin
Number
P14
M11
VCC
M2-1/0
HDC-I/O
I/O
I/O
I/O
LDC-I/O
I/O'
I/O
I/O
I/O
I/O
I/O
INIT-I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O'
I/O
I/O
I/O
I/O
XTL2(IN)-1/0
GND
N13
M12
P13
N12
P12
N11
M10
P11
N10
P10
M9
N9
P9
P8
N8
P7
M8
M7
N7
P6
N6
PS
M6
NS
P4
P3
MS
N4
P2
N3
N2
XC3042A
XC3064A
RESET
VCC
DONE-PG
D7-1/0
XTL 1-1/0-BCLKIN
I/O
I/O
D6-1/0
K3
L2
L1
K2
J3
K1
J2
J1
H1
H2
H3
G3
G2
G1
I/O
I/O'
I/O
I/O
DS-I/O
CSO-I/O
I/O'
I/O'
D4-1/0
I/O
VCC
GND
D3-1/0
CS1-I/0
I/O'
I/O'
D2-1/0
I/O
I/O
I/O
D1-1/0
RDY/BUSY -RCLK-I/O
I/O
I/O
DO-DIN-I/O
PGA
Pin
Number
M3
P1
M4
L3
M2
N1
M1
F1
F2
E1
F3
E2
D1
D2
E3
C1
B1
C2
D3
XC3042A
XC3064A
DOUT-I/O
CCLK
VCC
GND
AO-WS-I/O
A1-CS2-1/0
I/O
I/O
A2-1/0
A3-1/0
I/O
I/O
A1S-I/0
A4-1/0
I/O'
A14-1/0
AS-I/O
GND
VCC
A13-1/0
A6-1/0
I/O'
A12-1/0
A7-1/0
I/O
I/O
A11-1/0
A8-1/0
I/O
I/O
A10-1/0
A9-1/0
VCC
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.
'Indicates unconnected package pins (14) for the XC3042A.
4-366
November 20, 1997 (Version 3.0)
~XILINX
XC3000 Series 144-Pin Plastic TQFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Pin
Number
XC3042A
XC3064A
XC3090A
XC3042A
XC3064A
XC3090A
Pin
Number
Pin
Number
XC3042A
XC3064A
XC3090A
1
PWRDN
49
1/0
97
I/O
2
1/0-TClKIN
50
1/0'
98
I/O
3
1/0'
51
1/0
99
I/O'
4
1/0
52
1/0
100
I/O
5
1/0
53
INIT-I/O
101
I/O'
6
1/0'
54
VCC
102
Dl-I/O
7
1/0
55
GNO
103
RDY/BUSY-RClK-I/O
8
1/0
56
1/0
104
I/O
9
I/O'
57
1/0
105
I/O
10
1/0
58
1/0
106
DO-DIN-I/O
11
I/O
59
1/0
107
DOUT-I/O
12
1/0
60
1/0
108
CClK
13
I/O
61
1/0
109
VCC
14
1/0
62
I/O
110
GND
15
1/0'
63
1/0'
111
AO-WSI/O
16
1/0
64
1/0'
112
Al-CS2-1/0
17
1/0
65
1/0
113
I/O
18
GND
66
1/0
114
I/O
19
VCC
67
1/0
115
A2-1/0
20
1/0
68
1/0
116
A3-1/0
21
1/0
69
XTL2(IN)-I/O
117
I/O
22
I/O
70
GND
118
I/O
23
I/O
71
RESET
119
A15-1/0
24
1/0
72
VCC
120
A4-1/0
25
I/O
73
DONE-PG
121
1/0'
26
I/O
74
D7-1/0
122
I/O'
27
1/0
75
XTll (OUT)-BClKIN-I/O
123
A14-1/0
28
1/0'
76
I/O
124
AS-I/O
29
I/O
77
1/0
125
I/O (XC3090 only)
GND
I
-~
30
1/0
78
D6-1/0
126
31
1/0'
79
I/O
127
VCC
32
I/O'
80
I/O'
128
A13-1/0
33
I/O
81
I/O
129
A6-1/0
34
1/0'
82
1/0
130
I/O'
35
I/O
83
I/O'
131
1/0 (XC3090 only)
36
Ml-RD
84
05-1/0
132
I/O'
37
GND
85
CSO-I/O
133
A12-1/0
38
MO-RT
86
1/0'
134
A7-1/0
39
VCC
87
I/O'
135
I/O
40
M2-1/0
88
04-1/0
136
I/O
41
HDC-I/O
89
I/O
137
All-I/O
42
1/0
90
VCC
138
AS-I/O
43
I/O
91
GNO
139
I/O
44
1/0
92
03-1/0
140
1/0
45
[DC-I/O
93
CS1-1/0
141
Al0-1/0
46
1/0'
94
1/0'
142
A9-1/0
47
1/0
95
1/0'
143
VCC
48
I/O
96
D2-1/0
144
GND
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.
* Indicates unconnected package pins (24) for the XC3042A.
November 20, 1997 (Version 3.0)
4-367
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC31 OOAlL)
XC3000 Series 160-Pin PQFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
PQFP Pin
XC3064A, XC3090A,
XC3195A
PQFP Pin
Number
Number
XC3064A, XC3090A,
XC3195A
PQFP Pin
Number
XC3064A, XC3090A,
XC3195A
PQFP Pin
Number
XC3064A, XC3090A,
XC3195A
CCLK
1
1/0'
41
GND
81
07-1/0
121
2
1/0'
42
MO-RTRIG
82
XTL1-1/0-BCLKIN
122
VCC
3
1/0'
43
VCC
83
110'
123
GND
4
1/0
44
M2-1/0
84
1/0
124
AO-WS-I/O
5
110
45
HDC-I/O
85
1/0
125
Al-CS2-1/0
1/0
6
1/0
46
1/0
86
06-1/0
126
7
1/0
47
1/0
87
1/0
127
1/0
8
1/0
48
1/0
88
1/0
128
A2-1/0
9
1/0
49
LDC-I/O
89
1/0
129
A3-1I0
10
1/0
50
1/0'
90
110
130
1/0
11
1/0
51
1/0'
91
1/0
131
1/0
12
1/0
52
110
92
D5-1/0
132
A15-1/0
13
1/0
53
1/0
93
CSO-I/O
133
A4-1/0
14
1/0
54
1/0
94
1/0'
134
1/0
15
1/0
55
1/0
95
1/0'
135
1/0
16
1/0
56
1/0
96
1/0
136
A14-1/0
17
1/0
57
1/0
97
1/0
137
A5-1/0
18
1/0
58
1/0
98
04-1/0
138
1/0'
19
GND
59
INIT-I/O
99
1/0
139
GNO
20
VCC
60
VCC
100
VCC
140
VCC
21
1/0'
61
GND
101
GND
141
A13-1/0
22
1/0
62
1/0
102
D3-1/0
142
A6-1/0
23
110
63
1/0
103
CST-I/O
143
1/0'
24
1/0
64
1/0
104
1/0
144
25
110
65
1/0
105
110
145
1/0'
1/0
26
110
66
1/0
106
1/0'
146
1/0
27
1/0
67
1/0
107
1/0'
147
A12-1/0
28
1/0
68
1/0
108
D2-1/0
148
A7-1/0
29
1/0
69
1/0
109
1/0
149
1/0
30
1/0
70
1/0
110
1/0
150
1/0
110
151
A11-I/O
-~
31
1/0
71
110
111
32
1/0
72
1/0
112
1/0
152
A8-1/0
33
1/0
73
1/0
113
1/0
153
1/0
34
1/0
74
1/0
114
D1-I/0
154
110
35
1/0
75
1/0'
115
RDY/BUSY-RCLK-I/O
155
Al0-1/0
36
1/0
76
XTL2-1/0
116
1/0
156
A9-1I0
37
1/0
77
GND
117
1/0
157
VCC
38
1/0'
78
RESET
118
1/0'
158
GND
39
110'
79
VCC
119
DO-DIN-I/O
159
PWRDWN
40
Ml-RDATA
80
DONElPG
120
DOUT-I/O
160
TCLKIN-I/O
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed lOBs are default slew-rate limited.
'Indicates unconnected package pins (18) for the XC3064A.
4-368
November 20, 1997 (Version 3.0)
~XILINX
XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
PGAPin
Number
XC3090A, XC3195A
PGAPin
Number
XC3090A, XC3195A
PGAPin
Number
XC3090A, XC3195A
PGAPin
Number
XC3090A, XC3195A
62
PWRDN
D13
1/0
R14
DONE-PG
N4
DOUT-I/O
D4
TCLKIN-I/O
614
Ml-RDATA
N13
D7-1/0
R2
CCLK
63
1/0
C14
GND
T14
XTL 1(OUT)-6CLKIN-1/0
P3
VCC
C4
1/0
615
MO-RTRIG
P13
I/O
N3
GND
64
1/0
A4
D5
1/0
--1-10-
D14
VCC
R13
1/0
P2
AO-WS-I/O
C15
M2-1/0
T13
I/O
M3
A1-CS2-1/0
E14
HDC-I/O
N12
1/0
R1
1/0
C5
1/0
616
1/0
P12
D6-1/0
N2
I/O
65
1/0
D15
1/0
R12
1/0
P1
A2-1/0
A5
1/0
C16
1/0
T12
1/0
N1
A3-1/0
C6
1/0
D16
LDC-I/O
P11
1/0
L3
1/0
D6
1/0
F14
I/O
N11
1/0
M2
1/0
66
1/0
E15
1/0
R11
1/0
M1
A15-1/0
A6
I/O
E16
I/O
T11
D5-1/0
L2
A4-1/0
67
I/O
F15
1/0
R10
CSO-I/O
L1
1/0
C7
1/0
F16
I/O
P10
1/0
K3
1/0
D7
1/0
G14
1/0
N10
1/0
K2
A14-1/0
A7
1/0
G15
1/0
T10
1/0
K1
A5-1/0
A8
1/0
G16
1/0
T9
1/0
J1
1/0
6S
I/O
H16
1/0
R9
D4-1/0
J2
1/0
C8
1/0
H15
INIT-I/O
P9
1/0
J3
GND
DS
GND
H14
VCC
N9
VCC
H3
VCC
D9
VCC
J14
GND
NS
GND
H2
A13-1/0
C9
1/0
J15
1/0
PS
D3-1/0
H1
A6-1/0
69
1/0
J16
1/0
RS
CS1-1/0
G1
1/0
A9
1/0
K16
1/0
TS
I/O
G2
I/O
A10
1/0
K15
1/0
T7
1/0
G3
I/O
D10
I/O
K14
I/O
N7
1/0
F1
1/0
C10
1/0
L16
I/O
P7
1/0
F2
A12-1/0
610
I/O
L15
1/0
R7
D2-1/0
E1
A7-1/0
A11
I/O
M16
1/0
T6
1/0
E2
1/0
611
1/0
M15
I/O
R6
1/0
F3
1/0
D11
1/0
L14
1/0
N6
1/0
D1
A11-1/0
C11
I/O
N16
1/0
P6
1/0
C1
AS-I/O
A12
1/0
P16
1/0
T5
1/0
D2
1/0
612
1/0
N15
1/0
R5
01-1/0
B1
1/0
C12
I/O
R16
1/0
P5
RDY16USY-RCLK-I/O
E3
A10-1/0
D12
1/0
M14
1/0
N5
1/0
C2
A9-1/0
A13
I/O
P15
XTL2(IN)-1/0
T4
1/0
D3
VCC
613
1/0
N14
GND
R4
1/0
C3
GND
C13
1/0
R15
RESET
P4
I/O
A14
1/0
P14
VCC
R3
DO-DIN-I/O
I
Unprogrammed lOBs have a default pull-up_ This prevents an undefined pad level for unbonded or unused 10Bs_
Programmed outputs are default slew-rate limited_
Pins A2, A3, A 15, A 16, T1 , T2, T3, T15 and T16 are not connected_ Pin A 1 does not exist
November 20, 1997 (Version 3_0)
4-369
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
XC3000 Series 176-Pin TQFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Pin
Number
XC3090A
Pin
Number
Pin
XC3090A
Number
Pin
XC3090A
Number
XC3090A
1
PWROWN
45
M1-ROATA
89
OONE-PG
133
VCC
2
TCLKIN-I/O
46
GNO
90
07-1/0
134
GNO
3
1/0
47
MO-RTRIG
91
XTAL 1(OUT)-BCLKIN-I/O
135
AO-WS-I/O
4
1/0
48
VCC
92
1/0
136
A1-CS2-1/0
5
1/0
49
M2-1/0
93
I/O
137
-
6
f---:c7
1/0
50
HOC-I/O
94
1/0
138
1/0
1/0
51
I/O
95
I/O
139
1/0
8
1/0
52
1/0
96
06-1/0
140
A2-1/0
9
1/0
53
1/0
97
1/0
141
A3-1/0
10
1/0
54
LOC-I/O
98
1/0
142
-
11
1/0
55
-
99
1/0
143
-
12
1/0
56
100
1/0
144
1/0
1/0
.~-.---~
~--
13
1/0
57
1/0
101
1/0
145
1/0
14
1/0
58
1/0
102
05-1/0
146
A15-1/0
15
1/0
59
1/0
103
CSO-I/O
147
A4-1/0
16
1/0
60
1/0
104
1/0
148
I/O
17
1/0
61
1/0
105
1/0
149
1/0
18
I/O
62
1/0
106
1/0
150
A14-1/0
19
1/0
63
1/0
107
1/0
151
A5-1/0
20
1/0
64
1/0
108
04-110
152
1/0
21
I/O
65
INIT-I/O
109
1/0
153
1/0
22
GNO
66
VCC
110
VCC
154
GNO
23
vce
67
GNO
111
GNO
155
VCC
24
1/0
68
1/0
112
03-1/0
156
A13-1/0
25
1/0
69
1/0
113
CS1-1/0
157
A6-1/0
26
1/0
70
1/0
114
1/0
158
1/0
27
1/0
71
1/0
115
1/0
159
28
1/0
72
1/0
116
1/0
160
1/0
-
29
1/0
73
1/0
117
1/0
161
-
30
1/0
74
1/0
118
02-1/0
162
1/0
31
1/0
75
1/0
119
1/0
163
1/0
32
1/0
76
1/0
120
1/0
164
A12-1/0
.-
33
1/0
77
1/0
121
1/0
165
A7-1/0
34
1/0
78
1/0
122
I/O
166
1/0
35
1/0
79
1/0
123
1/0
167
36
1/0
80
1/0
124
01-1/0
168
1/0
-
37
1/0
81
1/0
125
ROY/BUSY-RCLK-I/O
169
A11-1/0
38
I/O
82
126
1/0
170
A8-1/0
39
1/0
83
-
127
1/0
171
I/O
40
1/0
84
1/0
128
1/0
172
1/0
41
I/O
85
XT AL2(IN)-I/O
129
1/0
173
A10-1/0
42
1/0
86
GNO
130
OO-OIN-I/O
174
A9-1/0
43
I/O
87
RESET
131
OOUT-I/O
175
VCC
44
-
88
vce
132
CCLK
176
GND
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.
4-370
November 20, 1997 (Version 3.0)
~XILINX
XC3000 Series 208-Pin PQFP Pinouts
XC3000A, and XC3000L families have identical pinouts
Pin Number
XC3090A
Pin Number
XC3090A
Pin Number
XC3090A
Pin Number
XC3090A
1
-
53
105
-
157
-
2
GND
54
-
106
VCC
158
-
3
PWRDWN
55
VCC
107
DIP
159
-
4
TCLKIN-I/O
56
M2-1/0
108
-
160
GND
5
1/0
57
HDC-I/O
109
D7-1/0
161
WS·AO·I/O
6
1/0
58
1/0
110
XTL l-BCLKIN·I/O
162
CS2-AH/0
7
1/0
59
1/0
111
1/0
163
1/0
8
1/0
60
1/0
112
1/0
164
1/0
9
1/0
61
LOC-I/O
113
1/0
165
A2-1/0
10
110
62
1/0
114
110
166
A3-1/0
11
1/0
63
1/0
115
D6-1/0
167
1/0
12
110
64
-
116
1/0
168
1/0
13
110
65
-
117
110
169
1/0
66
118
1/0
170
15
-
67
-
-
14
119
-
171
-
16
1/0
68
1/0
120
1/0
172
A15-1/0
17
1/0
69
1/0
121
1/0
173
A4-1/0
18
1/0
70
1/0
122
D5-1/0
174
I/O
19
1/0
71
1/0
123
CSO·I/O
175
110
1/0
72
-
124
1/0
176
110
73
-
125
1/0
177
-
22
1/0
74
1/0
126
1/0
178
A14-1/0
23
1/0
75
1/0
127
1/0
179
A5-1/0
24
110
76
110
128
D4-1/0
180
1/0
25
GND
77
INIT-I/O
129
1/0
181
110
26
VCC
78
VCC
130
VCC
182
GND
20
~
----
27
110
79
GND
131
GND
183
VCC
28
1/0
80
1/0
132
D3-1I0
184
A13-1/0
29
1/0
81
1/0
133
CSf·I/O
185
A6-1/0
30
1/0
82
1/0
134
1/0
186
1/0
31
1/0
83
-
135
110
187
1/0
32
1/0
84
-
136
1/0
188
33
1/0
85
1/0
137
1/0
189
-
34
1/0
86
1/0
138
D2-1/0
190
I/O
35
1/0
87
110
139
1/0
191
1/0
36
1/0
88
1/0
140
110
192
A12-J/0
A7-1/0
37
-
89
1/0
141
110
193
38
110
90
-
142
-
194
-
39
1/0
91
143
110
195
40
1/0
92
-
144
110
196
-
41
1/0
93
1/0
145
DH/O
197
I/O
42
1/0
94
1/0
146
RDY/BUSY-RCLK·I/O
198
1/0
43
1/0
95
1/0
147
110
199
All-I/O
44
110
96
1/0
148
I/O
200
A8-1/0
1/0
97
1/0
149
1/0
201
1/0
98
1/0
150
I/O
202
I/O
45
---
46
I/O-~
47
110
99
1/0
151
DIN·DO·I/O
203
Al0·1/0
48
Ml-RDATA
100
XTL2-I/O
152
DOUT·I/O
204
A9-1/0
49
GND
101
GND
153
CCLK
205
VCC
50
MO-RTRIG
102
RESET
154
VCC
206
51
-
103
-
155
-
207
-
52
104
156
208
I
--
Unprogrammed lOBs have a default pull-up. This prevents an -undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.
'In PQ208, XC3090A and XC3195A have different pinouts.
November 20, 1997 (Version 3.0)
4-371
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
XC3195A PQ208 and PG223 Pinouts
Pin Description
PG223 PQ208
Pin Description
PG223 PQ208
133
T9
132
R9
131
Rl0
130
J15
78
Tl0
129
lNTf
J16
77
Ul0
128
110
liD
liD
liD
liD
I/O
110
liD
110
110
liD
liD
liD
liD
110
LOC-I/O
liD
liD
liD
HDC-I/O
M2-1/0
VCC
MO-RTIG
GND
Ml/RDATA
liD
J17
76
Vl0
J18
202
V4
150
D2
201
ROY/BUSY·RCLK·I/O
U4
149
E2
F4
200
US
148
R6
147
F3
198
T5
146
Dl
197
F2
196
G2
194
P4
162
Dl-I/O
liD
110
110
110
110
110
liD
D2-1/0
110
liD
110
I/O
CSH/O
D3-1/0
GND
VCC
liD
D4-1/0
liD
liD
I/O
liD
CSO-I/O
D5-1/0
liD
110
110
liD
liD
110
liD
D6-1/0
110
liD
liD
liD
V16
110
Ul
161
XTLX1 (OUT)BCLKN-I/O
U16
109
D7-1/0
DIP
VCC
RESET
GND
XTL2(IN)-1/0
T16
108
V17
107
R15
106
U17
105
R16
104
V18
103
Jl
185
184
J4
183
K4
182
K2
181
Kl
180
L2
179
L4
178
L3
177
L1
176
Ml
175
M2
174
M4
173
N2
172
N3
171
P2
169
Rl
168
N4
167
Tl
166
R2
165
P3
164
T2
163
Vl
160
T3
159
R3
158
R4
157
U2
156
V2
155
49
134
U9
Cl
K3
B16
V9
151
186
51
135
T4
187
50
R8
203
J3
J2
C16
136
C2
188
D15
137
T8
152
H4
52
U8
R5
189
B17
138
204
190
53
V8
E4
H3
54
139
153
Hl
D16
140
U7
V3
1/0
1/0
1/0
1/0
A8-1/0
A11·I/O
1/0
1/0
1/0
1/0
A7-1/0
A12-1/0
1/0
1/0
1/0
I/O
1/0
1/0
A6-1/0
A13-1/0
VCC
GND
1/0
1/0
AS-liD
A14·1/0
1/0
1/0
1/0
1/0
A4-1/0
A15·1/0
1/0
1/0
1/0
1/0
A3-1/0
A2-1/0
1/0
1/0
1/0
1/0
Al-CS2-1/0
AO-WS-I/O
GND
VCC
CCLK
DOUT-I/O
liD
110
liD
liD
191
A17
R7
205
H2
56
141
E3
192
55
V7
154
193
E15
144
U3
G4
A18
145
DO-DIN-I/O
Rl1
127
126
Tll
125
Ul1
124
Vll
123
U12
122
R12
121
V12
120
T13
119
U13
118
T14
117
R13
116
U14
U15
115
V15
113
114
T15
112
R14
111
Pin Description
110
110
liD
110
liD
liD
liD
liD
liD
liD
liD
liD
liD
110
I/O
110
110
liD
110
110
I/O
VCC
GND
liD
110
liD
liD
110
I/O
liD
110
liD
110
110
I/O
110
liD
liD
liD
liD
liD
110
liD
I/O
TCLKIN-I/O
PWRDN
U6
206
Gl
PG223 PQ208
T6
Bl
199
Pin Description
110
110
liD
110
liD
liD
liD
liD
liD
liD
liD
liD
110
110
liD
110
liD
110
liD
liD
I/O
GND
VCC
A9-1/0
Al0-1/0
U18
102
P15
101
T17
100
T18
99
P16
98
R17
97
N15
96
R18
95
P17
94
N17
93
N16
92
M15
89
M18
88
M17
87
L18
86
L17
85
L15
84
L16
83
K18
82
K17
81
K16
80
K15
79
H16
75
74
H15
73
H17
72
H18
71
G17
70
G18
69
G15
68
F16
67
F17
66
E17
63
C18
62
F15
61
D17
60
E16
59
C17
58
B18
57
PG223 PQ208
A16
48
D14
47
C15
46
B15
45
A15
44
C14
43
D13
42
614
41
C13
40
B13
39
B12
38
D12
37
A12
36
Bll
35
Cl1
34
All
33
Dll
32
Al0
31
Bl0
30
Cl0
29
C9
28
Dl0
27
D9
26
B9
25
A9
24
C8
23
D8
22
B8
21
A8
20
B7
19
A7
18
D7
17
B6
14
C6
13
65
12
A4
11
D6
10
C5
9
64
8
63
7
C4
6
D5
5
C3
4
A3
3
A2
2
62
1
GNO
04
vcc
03
208
207
Unprogrammed lOBs have a default pUll-up. This prevents an undefined pad level for unbonded or unused lOBs. Programmed outputs are
default slew-rate limited.
In the PQ208 package, pins 15,16,64,65,90,91,142,143,170 and 195 are not connected.
In the PG223 package, the following pins are not connected: A5, A6, A13, A14, D18, E1, E18, F1, F18, N1, N18, P1, P18, V5, V6, V13, and
V14.
*In PQ208, XC3090A and XC3195A have different pinouts.
4-372
November 20, 1997 (Version 3.0)
~XILINX
Product Availability
Pins
44
Type
68
84
100
132
Plast.
Plast.
Plast.
Plast.
Cer.
Plast.P
Plast.
Plast.
TopBrazed
PLCC
VQFP
PLCC
PLCC
PGA
QFP
TQFP
VQFP
CQFP
PC44
VQ64
PC68
PC84
PG84
-7
CI
CI
CI
-6
C
C
C
C
Code
XC3020A
64
144
Plast.
Cer.
PGA
PGA
160
164
Plast.
Plast.
TopBrazed
Plast.
Cer.
Plast.
Plast.
Cer.
TQFP
PQFP
CQFP
PGA
PGA
TQFP
PQFP
PGA
175
176
208
PQ100 TQ100 VQ100 CB100 PP132 PG132 TQ144 PQ160 CB164 PP175 PG175 TQ176 PQ208 PG223
CI
-7
CI
CI
CI
CI
CI
CI
-6
C
C
C
C
C
C
C
-7
CI
CI
CI
CI
CI
CI
-6
C
C
C
C
C
C
C
-7
CI
CI
CI
CI
-6
C
C
C
C
C
-7
CI
CI
CI
CI
CI
CI
CI
-6
C
C
C
C
C
C
C
XC3020L
-8
CI
XC3030L
-8
CI
CI
XC3042L
-8
CI
CI
XC3064L
-8
CI
CI
XC3090L
-8
CI
CI
XC3030A
XC3042A
XC3064A
XC3090A
XC3120A
XC3130A
XC3142A
XC3164A
XC3190A
XC3195A
CI
223
-5
CI
CI
CI
CI
-4
CI
CI
CI
CI
-3
CI
CI
CI
CI
-2
CI
CI
CI
CI
-1
C
C
C
C
-09
C
C
C
C
CI
-5
CI
CI
CI
CI
CI
CI
-4
CI
CI
CI
CI
CI
CI
CI
-3
CI
CI
CI
CI
CI
CI
CI
CI
CI
I
CI
CI
CI
-2
CI
CI
CI
CI
CI
CI
CI
-1
C
C
C
C
C
C
C
-09
C
C
C
C
C
C
C
-5
CI
CIMS
CI
C
C
CIMS
CI
-4
CI
CI
CI
C
C
CI
CI
-3
CI
CI
CI
CI
CI
CI
CI
-2
CI
CI
CI
CI
CI
CI
CI
-1
C
C
C
C
C
C
C
-09
C
C
C
C
C
C
C
MS
-5
CI
CI
CI
CI
-4
CI
CI
CI
CI
CI
-3
CI
CI
CI
CI
CI
-2
CI
CI
CI
CI
CI
-1
C
C
C
C
C
-09
C
C
C
C
C
-5
CI
CI
CI
CI
CIMS
CI
-4
CI
CI
CI
CI
CI
CI
CI
-3
CI
CI
CI
CI
CI
CI
CI
-2
CI
CI
CI
CI
CI
CI
CI
-1
C
C
C
C
C
C
C
-09
C
C
C
C
C
C
-5
CI
CI
CI
CIMS
CI
CIMS
-4
CI
CI
CI
CI
CI
CI
-3
CI
CI
CI
CI
CI
CI
-2
CI
CI
CI
CI
CI
CI
CI
MS
MS
CI
C
---
-1
C
C
C
C
C
C
-09
C
C
C
C
C
C
November 20, 1997 (Version 3.0)
4-373
XC3000 Series Field Programmable Gate Arrays (XC3000AlL, XC3100AlL)
Pins
44
Type
Code
XC3142L
XC3190L
Notes:
64
100
84
68
132
Plast.
Plast.
Plast.
Plast.
PLCC
VQFP
PLCC
PLCC
Cer.
PGA
Plast.P
QFP
Plast.
TQFP
VQFP
TopBrazed
CQFP
PC44
VQ64
PC68
PC84
PG84
PQ100
TQ100
VQ100
CB100
Plast.
144
160
164
175
176
208
223
Plast.
Plast.
TQFP
PQFP
Cer.
PGA
PQ208
PG223
Top-
Plast.
Cer.
Plast.
Plast. Brazed Plast.
PGA
PGA
TQFP
PQFP
CQFP
PGA
Cer.
PGA
PP132
PG132
TQ144
PQ160
CB164
PP175
PG175
TQ176
-3'
C
C
C
-2'
C
C
C
-3'
C
C
C
-2'
C
C
C
' Advance Information
C = Commercial, T J= 0" to +S5"C
M=Military Temp, T c= -55" to +125"C
I = Industrial, TJ = -40" to + 1OO"C
B = MIL-8TD-SS3C Class B
Number of Available I/O Pins
Number of Package Pins
MaxVO
XC3020AIXC3120A
XC3030AIXC3130A
XC3042AIXC3142A
XC3064A1XC3164A
XC3090AlXC3190A
XC3195A
64
80
96
120
144
176
44
64
68
84
100 120 132 144 156 160 164 175 176 191 196 208 223 240
34
54
58
58
64
74
74
70
70
70
64
80
82
96 96
110 120
120
120
138 144 144 144
138
144
144
176 176
X7067
Ordering Information
Example:
IT~
TL
XC3030A-3 PC44C
Device Type---.l'
Speed Grade------'-
Temperature Range
Number of Pins
Package Type
4-374
November 20, 1997 (Version 3.0)
---
~~--~~~-~
SPROM Products
1
Introduction
2
Development System Products and CORE Solutions Products
3
CPLD Products
4
FPGA Products
5
SPROM Products
6
3V Products
7
HardWire FpgASIC Products
8
High-Reliability and QML Military Products
9
Programming Support
10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support and Services
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors
SPROM Products
Table of Contents
XC1701 L (3.3V), XC1701 (5.0V) and XC17512L (3.3V)
Serial Configuration PROMs
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DATA .....................................................................
ClK .......................................................................
RESET/OE .................................................................
CEo .......................................................................
CEO ......................................................................
VPP .......................................................................
VCC ......................................................................
GND ......................................................................
Serial PROM Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Number of Configuration Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Controlling Serial PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . ..
FPGA Master Serial Mode Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Cascading Serial Configuration PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Standby Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC1701 ..........................................................................
Absolute Maximum Ratings .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DC Characteristics Over Operating Condition .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC1701UXC17512l ................................................................
Absolute Maximum Ratings ..........................................................
Operating Conditions ...............................................................
DC Characteristics Over Operating Condition ............................................
AC Characteristics Over Operating Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Marking Information ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-1
5-1
5-2
5-2
5-2
5-2
5-2
5-2
5-2
5-2
5-2
5-2
5-2
5-2
5-3
5-3
5-3
5-5
5-5
5-6
5-6
5-6
5-6
5-7
5-7
5-7
5-7
5-8
5-10
5-10
XC1700D Family of Serial Configuration PROMs
Features .........................................................................
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DATA .....................................................................
ClK .......................................................................
RESET/OE .................................................................
CE ........................................................................
CEO ......................................................................
VPP .......................................................................
VCC and GND ..............................................................
Serial PROM Pinouts .........................................................
Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Number of Configuration Bits ...................................................
Controlling Serial PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
FPGA Master Serial Mode Summary ...................................................
5-11
5-11
5-12
5-12
5-12
5-12
5-12
5-12
5-12
5-12
5-12
5-12
5-13
5-13
5-13
~XILINX
Programming the FPGA With Counters Unchanged Upon Completion ...................
Cascading Serial Configuration PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Standby Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Programming the XC1700 Family Serial PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC1718D, XC1736D, XC1765D, XC17128D and XC17256D ................................
Absolute Maximum Ratings ..........................................................
Operating Conditions .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DC Characteristics Over Operating Condition .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC1718L, XC1765L, XC17128L and XC17256L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Absolute Maximum Ratings ..........................................................
Operating Conditions .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DC Characteristics Over Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AC Characteristics Over Operating Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Marking Information ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-13
5-14
5-16
5-16
5-17
5-17
5-17
5-17
5-18
5-18
5-18
5-18
5-19
5-21
5-21
XC1701 L (3.3V), XC1701 (5.0V) and
XC17512L (3.3V)
Serial Configuration PROMs
December 10, 1997(Version 1.1)
Product Specification
Features
Description
•
The XC1701 L, XC1701 and XC17512L serial configuration
PROMs (SCPs) provide an easy-to-use, cost-effective
method for storing Xilinx FPGA configuration bitstreams.
•
•
•
•
•
•
•
•
•
On-chip address counter, incremented by each rising
edge on the clock input
Simple interface to the FPGA; requires only one user
1/0 pin
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active Low)
for compatibility with different FPGA solutions
Supports XC4000EXlXL fast configuration mode (15.0
MHz)
Low-power CMOS Floating Gate process
Available in 5 V and 3.3 V versions
Available in compact plastic packages: 8-pin PDIP,
20-pin SOIC, and 20-pin PLCC.
Programming support by leading programmer
manufacturers.
Design support using the Xilinx Alliance and
Foundation series software packages.
When the FPGA is in master serial mode, it generates a
configuration clock that drives the SCPo A short access time
after the rising clock edge, data appears on the SCP DATA
output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
SCPo When the FPGA is in slave mode, the SCP and the
FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all SCPs in this chain
are interconnected. All devices are compatible and can be
cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA
design file into a standard Hex format, which is then transferred to the programmer.
Vee
Vpp
GND
cEC>1I------------~==========~~L_JP---~JCEO
RESETI D - I - - - - ' \ ,.....
OEor
)-------~
OEI
RESET
.----+-------.
CLKD-I-----L-J
EPROM
Cell
Matrix
Output
DATA
X3185
Figure 1: Simplified Block Diagram (does not show programming circuit)
December 10, 1997(Version 1.1)
5-1
I
XC1701 L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs
Pin Description
Serial PROM Pinouts
DATA
Pin Name
a-Pin
PDIP
20-Pin
SOIC
20-Pin
PLCC
Data output, 3-stated when either CE or OE are inactive.
During programming, the DATA pin is I/O. Note that OE can
be programmed to be either active High or active low.
DATA
1
1
2
CLK
RESET/OE (OE/RESET)
2
3
4
ClK
CE
GND
3
4
8
10
6
8
10
Each rising edge on the ClK input increments the internal
address counter, if both CE and OE are active.
5
11
V pp
6
7
13
18
Vcc
8
20
CEO
14
17
20
RESET/OE
When High, this input holds the address counter reset and
3-states the DATA output. The polarity of this input pin is
programmable as either RESET/OE or OE/RESET. To
avoid confusion, this document describes the pin as
RESET/OE, although the opposite polarity is possible on all
devices. When RESET is active, the address counter is
held at zero, and the DATA output is 3-stated. The polarity
of this input is programmable. The default is active High
RESET, but the preferred option is active low RESET,
because it can be driven by the FPGA's INIT pin.
The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW130 Programmer. Third-party programmers have different
methods to invert this pin.
When High, this pin disables the internal address counter,
3-states the DATA output, and forces the device into low-Icc
standby mode.
CEO
Chip Enable output, to be connected to the CE input of the
next SCP in the daisy chain. This output is low when the
CE and OE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value. In other words: when the PROM has been read,
CEO will follow CE as long as OE is active. When OE goes
inactive, CEO stays High until the PROM is reset. Note that
OE can be programmed to be either active High or active
low.
Capacity
Device
Configuration Bits
XC1701 L
1,048,576
XC1701
XC17512L
1,048,576
524,288
Number of Configuration Bits, Including
Header for all Xilinx FPGAs and Compatible
SCPType
Device
Configuration Bits
SPROM
XC4010XL
283,424
XC17512L
XC4013XL
393,623
XC17512L
XC4020E
329,312
XC1701
XC4020XL
521,880
XC17512L
XC4025E
422,176
XC1701
XC4028XL
668,184
XC1701L
XC1701
XC4028EX
668,184
XC4036EX
832,528
XC1701
XC4036XL
832,528
XC1701L
XC4044XL
1,014,928
XC1701 L
XC4052XL
1,215,368
XC1701 L +
XC17256L
XC4062XL
1,433,864
XC1701 L +
XC17512L
XC4085XL
1,924,992
2 x XC1701L
Vpp
Programming Voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read operation, this pin must be connected to Vee. Failure to do so
may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Do not leave
VPP floating!
Vee and GND
Positive supply and ground pins.
5-2
December 10, 1997(Version 1.1)
~XILINX
Controlling Serial PROMs
Most connections between the FPGA device and the Serial
PROM are simple and self-explanatory.
•
The DATA output(s) of the of the Serial PROM(s) drives
the DIN input of the lead FPGA device.
The master FPGA CCLK output drives the CLK input(s)
of the Serial PROM(s).
The CEO output of a Serial PROM drives the CE input
of the next Serial PROM in a daisy chain (if any).
The RESET/OE input of all Serial PROMs is best driven
by the INIT output of the XC3000 or XC4000 lead
FPGA device. This connection assures that the Serial
PROM address counter is reset before the start of any
(re)configuration, even when a reconfiguration is
initiated by a Vee glitch. Other methods - such as
driving RESET/OE from LDC or system reset - assume
that the Serial PROM internal power-on-reset is always
in step with the FPGA's internal power-on-reset, which
may not be a safe assumption.
The CE input of the lead (or only) Serial PROM is driven
by the DONE/PRGM or DONE output of the lead FPGA
device, provided that DONE/PRGM is not permanently
grounded. Otherwise, LDC can be used to drive CE, but
must then be unconditionally High during user
operation. CE can also be permanently tied Low, but
this keeps the DATA output active and causes an
unnecessary supply current of 10 mA maximum.
FPGA Master Serial Mode Summary
The 1/0 and logic functions of the Logic Cell Array and their
associated interconnections are established by a configuration program. The program is loaded either automatically
upon power up, or on command, depending on the state of
the three FPGA mode pins. In Master Mode, the FPGA
automatically loads the configuration program from an
external memory. The Serial Configuration PROM has
been designed for compatibility with the Master Serial
Mode.
internal address and bit counters which are incremented on
every valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the
FPGA is used only for configuration, it must still be held at
a defined level during normal operation. The XC3000 and
XC4000 families take care of this automatically with an onchip default pull-up resistor.
Programming the FPGA With Counters
Unchanged Upon Completion
When multiple FPGA-configurations for a single FPGA are
stored in a Serial Configuration PROM, the OE pin should
be tied Low. Upon power-up, the internal address counters
are reset and configuration begins with the first program
stored in memory. Since the OE pin is held Low, the
address counters are left unchanged after configuration is
complete. Therefore, to reprogram the FPGA with another
program, the Dip line is pulled Low and configuration
begins at the last value of the address counters.
This method fails if a user applies RESET during the FPGA
configuration process. The FPGA aborts the configuration
and then restarts a new configuration, as intended, but the
Serial PROM does not reset its address counter, since it
never saw a High level on its OE input. The new configuration, therefore, reads the remaining data in the PROM and
interprets it as preamble, length count etc. Since the FPGA
is the master, it issues the necessary number of CCLK
pulses, up to 16 million (24) and DIP goes High. However,
the FPGA configuration will be completely wrong, with
potential contentions inside the FPGA and on its output
pins. This method must, therefore, never be used when
there is any chance of external reset during configuration.
Cascading Serial Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configurati,on memories, cascaded SCPs provide additional memory. After the last bit
from the first SCP is read, the next clock signal to the SCP
asserts its CEO output Low and disables its DATA line. The
second SCP recognizes the Low level on its CE input and
enables its DATA output. See Figure 2.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial Mode whenever all three of the FPGA modeselect pins are Low (MO=O, M1 =0, M2=0). Data is read from
the Serial Configuration PROM sequentially on a single
data line. Synchronization is provided by the rising edge of
the temporary signal CCLK, which is generated during configuration.
After configuration is complete, the address counters of all
cascaded SCPs are reset if the FPGA RESET pin goes
Low, assuming the SCP reset polarity option has been
inverted.
Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are
required to configure an FPGA. Data from the Serial Configuration PROM is read sequentially, accessed via the
To reprogram the FPGA with another program, the DIP line
goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention
between DATA and the configured 1/0 use of DIN.
December 10, 1997(Version 1.1)
5-3
II
XC1701 L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs
* If Readback is
Activated, a
3.3-kQ Resistor is
Required in
Series With M1
During Configuration
the 3.3 kQ M2 Pull-Down
Resistor Overcomes the
Internal Pull-Up,
but it Allows M2 to
be UserVO.
*
J.
Vcc
I I
!
MO M1 PWRDWN
'---
GeneralPurpose
UserVO
Pins
-
DOUT
HOC
--()
lDC
-- TC: don't change
Held reset
Not changing
Held reset
active
3-state
3-state
3-state
3-state
CEO
High
Low
High
High
High
Icc
active
reduced
active
standby
standby
Notes: 1. The XC1700 RESET input has programmable polarity
2. TC
=Terminal Count =highest address value. TC+ 1 =address O.
II
IMPORTANT: Always tie the V pp pin to Vee in your application. Never leave V pp floating.
December 10, 1997(Version 1.1)
5-5
XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs
XC1701
Absolute Maximum Ratings
Units
Description
Symbol
Vee
Supply voltage relative to GND
-0.5 to +7.0
V
V pp
Supply voltage relative to GND
-0.5 to + 12.5
V
V 1N
Input voltage relative to GND
-0.5 to Vee +0.5
V
V TS
Voltage applied to 3-state output
-0.5 to Vee +0.5
V
TSTG
Storage temperature (ambient)
-65 to +150
°C
TSOL
Maximum soldering temperature (10 s @ 1/16 in.)
+260
°C
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
Operating Conditions
Symbol
Vee
Description
Min
Max
Units
Commercial
Supply voltage relative to GND O°C to +70°C junction
4.75
5.25
V
Industrial
Supply voltage relative to GND -40°C to +85°C junction
4.50
5.50
V
Military
Supply voltage relative to GND -55°C to + 125°C case
4.50
5.50
V
DC Characteristics Over Operating Condition
Symbol
Description
V 1H
High-level input voltage
V 1L
Low-level input voltage
V OH
VOL
=-4 mA)
Low-level output voltage (lOL =+4 mA)
High-level output voltage (lOH =-4 mA)
Low-level output voltage (lOL =+4 mA)
leeA
Ices
VOL
V OH
IL
High-level output voltage (lOH
Commercial
Min
Max
Units
2.0
Vee
V
0
0.8
3.86
0.32
Industrial
V
V
3.76
V
V
0.37
V
Supply current, active mode
10.0
mA
Supply current, standby mode
50.0
IlA
10.0
IlA
Input or output leakage current
-10.0
Note: During normal read operation Vpp must be connected to Vcc
5-6
December 10, 1997(Version 1.1)
~XILINX
XC1701 UXC17512L
Absolute Maximum Ratings
Symbol
Description
Units
Vee
Supply voltage relative to GND
-0.5 to +6.0
V
Vpp
Supply voltage relative to GND
-0.5 to + 12.5
V
V IN
Input voltage with respect to GND
-0.5 to Vee +0.5
V
VTS
Voltage applied to 3-state output
-0.5 to Vee +0.5
V
TSTG
Storage temperature (ambient)
-65 to +150
°C
TSOL
Maximum soldering temperature (10 s
+260
°C
@
1/16 in.)
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating
Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device
reliability.
Operating Conditions
Symbol
Vee
Description
Commercial
Supply voltage relative to GND O°C to +70°C junction
Min
Max
Units
3.0
3.6
V
DC Characteristics Over Operating Condition
Symbol
Description
Min
Max
Units
2.0
Vee
V
0
0.8
V
V IH
High-level input voltage
V IL
Low-level input voltage
VOH
High-level output voltage (lOH = -4 rnA)
VOL
Low-level output voltage (lOL = +4 rnA)
0.4
V
leeA
Supply current, active mode
5.0
rnA
Ices
Supply current, standby mode
50.0
I1A
IL
Input or output leakage current
10.0
I1A
,
2.4
-10.0
V
Note: During normal read operation V pp must be connected to Vcc
December 10, 1997(Version 1.1)
5-7
I
XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs
AC Characteristics Over Operating Condition
\
/
®
--
TSCE
\
RESET/OE
/
r- @THC
..- TLc-
CD
elK
...
DATA
- ®
TOE
-CD
TCE
\
1'--
J-®
®
TSCE
THCE --
\
I
....- @
THOE-
@TCYC-
\
--
®
TCAC
)
-
...
0
TOH
~
....
r-
@TDF
N
rn
.... r-
0ToH
X2634
Symbol
Min
1
2
3
4
5
6
7
8
TOE
TCE
TCAC
TOH
TOF
TCYC
Tlc
THC
TSCE
OE to Data Delay
CE to Data Delay
ClK to Data Delay
Data Hold From CE, OE, or ClK
CE or OE to Data Float Delay2
Clock Periods
ClK low Time 3
ClK High Time3
CE Setup Time to ClK (to guarantee proper counting)
CE Hold Time to ClK (to guarantee proper counting)
OE Hold Time (guarantees counters are reset)
9
10
THeE
11
T HOE
Notes: 1. AC test load = 50 pF
XC1701L
XC17512L
XC1701
Description
Max
Min
25
45
45
0
30
60
60
0
50
67
20
20
20
0
20
50
100
25
25
25
0
25
Units
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2. Float delays are measured with minimum tester ae load and maximum de load.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V1l = 0.0 V and V1H = 3.0 V.
5·8
December 10, 1997(Version 1..1)
"""""
---"""~--"
"---~-"
-----~
~XILlNX
AC Characteristics Over Operating Condition (continued)
7
RESET/DE
f\
7
elK
7
@TCDF last Bit
DATA
@ToCK
--I
r
~<-
r
~r
\
@ToCE-+
Symbol
Description
/
\
,f-
-+
~
7
-
-+
TCDF
TOCK
TOCE
TOOE
_@ToOE
7
_@ToCE
II
X318
XC1701L
XC17512L
XC1701
Min
12
13
14
15
FirstBit
Max
ClK to Data Float Delay2
ClK to CEO Delay
CE to CEO Delay
RESET/OE to CEO Delay
50
30
35
30
Min
Units
Max
50
30
35
30
ns
ns
ns
ns
Notes: 1. AC test load = 50 pF
2. Float delays are measured with minimum tester ae load and maximum de load.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V1l =0.0 V and V1H =3.0 V.
December 10, 1997(Version 1.1)
5-9
XC1701 L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs
Ordering Information
XC1701 L - PC20 C
Device Number
XC1701L
XC1701
XC17512L
______-'I~ TL-_____
Package Type
Operating Range/Processing
C = Commercial (0° to +70°C)
I = Industrial (-40° to +85°C)
PD8
= 8-Pin Plastic DIP
S020 = 20-Pin Plastic Small-Outline Package
PC20 = 20-Pin Plastic Leaded Chip Carrier
Marking Information
Due to the small size of the serial PROM package, the complete ordering part number cannot be marked on the package.
The XC prefix is deleted and the package code is simplified. Device marking is as follows.
J
1701L
Device Number
XC1701L
XC1701
XC17512L
--------II
C
T,------
Package Type
P
S
J
5-10
P
Operating Range/Processing
C = Commercial (0° to +70°C)
I = Industrial (-40° to +85°C)
8-Pin Plastic DIP
20-Pin Plastic Small-Outline Package
20-Pin Plastic Leaded Chip Carrier
December 10, 1997(Version 1.1)
XC1700D Family of
Serial Configuration PROMs
November 25, 1997 (Version 1.1)
Product Specification
Features
Description
•
The XC1700 family of serial configuration PROMs (SCPs)
provides an easy-to-use, cost-effective method for storing
Xilinx FPGA configuration bitstreams.
•
•
•
•
•
•
•
•
•
•
Extended family of one-time programmable (OTP)
bit-serial read-only memories used for storing the
configuration bitstreams of Xilinx FPGAs
On-chip address counter, incremented by each rising
edge on the clock input
Simple interface to the FPGA requires only one user
1/0 pin
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active Low)
for compatibility with different FPGA solutions
XC17128D or XC17256D supports XC4000 fast
configuration mode (12.5 MHz)
Low-power CMOS EPROM process
Available in 5 V and 3.3 V versions
Available in plastic and ceramic packages, and
commercial, industrial and military temperature ranges
Space efficient 8-pin DIP, 8-pin SOIC, 8-pin VOIC, or
20-pin surface-mount packages.
Programming support by leading programmer
manufacturers.
Vee
Vpp
When the FPGA is in master serial mode, it generates a
configuration clock that drives the SCPo A short access time
after the rising clock edge, data appears on the SCP DATA
output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
SCPo When the FPGA is in slave mode, the SCP and the
FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all SCPs in this chain
are interconnected. All devices are compatible and can be
cascaded with other members of the family.
For device programming, the XACT development system
compiles the FPGA design file into a standard Hex format,
which is then transferred to the programmer.
GND
cEC>II------------~==========~~~~--~~CEO
RESETI
OE or
OEi
RESET
CLK~~--------L-J
EPROM
Cell
Matrix
Output
DATA
X3185
Figure 1: Simplified Block Diagram (does not show programming circuit)
November 25, 1997 (Version 1.1)
5-11
II
XC1700D Family of Serial Configuration PROMs
Pin Description
DATA
Data output, 3-stated when either CE or OE are inactive.
During programming, the DATA pin is I/O. Note that OE can
be programmed to be either active High or active low.
ClK
Serial PROM Pinouts
Pin Name
DATA
ClK
RESET/OE (OE/RESET)
CE
GND
CEO
8-Pin
20-Pin
1
2
3
4
5
6
2
4
6
8
10
14
17
20
Each rising edge on the ClK input increments the internal
address counter, if both CE and OE are active.
Vpp
7
Vec
8
RESET/OE
Capacity
When High, this input holds the address counter reset and
3-states the DATA output. The polarity of this input pin is
programmable as either RESET/OE or OE/RESET. To
avoid confusion, this document describes the pin as
RESET/OE, although the opposite polarity is possible on all
devices. When RESET is active, the address counter is
held at zero, and the DATA output is 3-stated. The polarity
of this input is programmable. The default is active High
RESET, but the preferred option is active low RESET,
because it can be driven by the FPGA's INIT pin.
XC1718D or l
XC1736D
XC1765D or l
XC17128D or l
XC17256D or l
XC17512l
XC1701 or l
Device
Configuration Bits
18,144
36,288
65,536
131,072
262,144
524,288
1,048,576
The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW130 programmer software. Third-party programmers have
different methods to invert this pin.
When High, this pin disables the internal address counter,
3-states the DATA output, and forces the device into low-Icc
standby mode.
CEO
Chip Enable output, to be connected to the CE input of the
next SCP in the daisy chain. This output is low when the
CE and OE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value. In other words: when the PROM has been read,
CEO will follow CE as long as OE is active. When OE goes
inactive, CEO stays High until the PROM is reset. Note that
OE can be programmed to be either active High or active
low.
Vpp
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read operation, this pin must be connected to Vee. Failure to do so
may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Do not leave
VPP floating!
Vee and GND
vee is positive supply pin and GND is ground pin.
5-12
November 25, 1997 (Version 1.1)
~XILINX
Number of Configuration Bits, Including Header
for all Xilinx FPGAs and Compatible SCP Type
Device
Configuration Bits
SCP
XC3x20AlL
14,819
XC1718D
XC3x30AlL
22,216
XC1736D
XC3x42A1L
30,824
XC1736D
XC3x64A1L
46,104
XC1765D
XC3x90AlL
64,200
XC1765D
XC3195A
94,984
XC17128D
XC4003E
53,984
XC1765D
XC4005E
95,008
XC17128D/L
XC4006E
119,840
XC17128D
XC4008E
147,552
XC17256D
XC4010E
178,144
XC17256D/L
XC4013E
247,968
XC17256D/L
XC4020E
329,312
XC1701
XC4025E
422,176
XC1701
XC4005XL
151,960
XC17256L
XC4010XL
283,424
XC17512L
XC4013XL
393,623
XC17512L
XC4020XL
521,880
XC17512L
XC4028EXlXL
668,184
XC1701L
832,528
XC1701L
XC4036EXlXL
-_.
XC4044XL
1,014,928
XC1701L
XC4052XL
1,215,368
XC1701L+
XC17256L
XC4062XL
1,433,864
XC1701 L +
XC17512L
XC4085XL
1,924,992
2XC1701L
42,416
XC1765D
XC5202
XC5204
70,704
XC17128D
XC5206
106,288
XC17128D
XC5210
165,488
XC17256D
XC5215
237,744
XC17256D
Controlling Serial PROMs
Most connections between the FPGA device and the Serial
PROM are simple and self-explanatory.
The DATA output(s) of the of the Serial PROM(s) drives
the DIN input of the lead FPGA device.
The master FPGA CCLK output drives the CLK input(s)
of the Serial PROM(s).
The CEO output of a Serial PROM drives the CE input
of the next Serial PROM in a daisy chain (if any).
The RESET/OE input of all Serial PROMs is best driven
by the INIT output of the XC3000 or XC4000 lead
FPGA device. This connection assures that the Serial
PROM address counter is reset before the start of any
(re)configuration, even when a reconfiguration is
initiated by a Vee glitch. Other methods - such as
driving RESET/OE from LDC or system reset - assume
that the Serial PROM internal power-on-reset is always
November 25, 1997 (Version 1.1)
•
in step with the FPGA's internal power-on-reset, which
may not be a safe assumption.
The CE input of the lead (or only) Serial PROM is driven
by the DONE/PRGM or DONE output of the lead FPGA
device, provided that DONEJPRGM is not permanently
grounded. Otherwise, LDC can be used to drive CE, but
must then be unconditionally High during user
operation. CE can also be permanently tied Low, but
this keeps the DATA output active and causes an
unnecessary supply current of 10 mA maximum.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Logic Cell Array and their
associated interconnections are established by a configuration program. The program is loaded either automatically
upon power up, or on command, depending on the state of
the three FPGA mode pins. In Master Mode, the FPGA
automatically loads the configuration program from an
external memory. The Serial Configuration PROM has
been designed for compatibility with the Master Serial
Mode.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial Mode whenever all three of the FPGA modeselect pins are Low (MO=O, M1 =0, M2=0). Data is read from
the Serial Configuration PROM sequentially on a single
data line. Synchronization is provided by the rising edge of
the temporary signal CCLK, which is generated during configuration.
Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are
required to configure an FPGA. Data from the Serial Configuration PROM is read sequentially, accessed via the
internal address and bit counters which are incremented on
every valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the
FPGA is used only for configuration, it must still be held at
a defined level during normal operation. The XC3000 and
XC4000 families take care of this automatically with an onchip default pull-up resistor. With XC2000-family devices,
the user must either configure DIN as an active output, or
provide a defined level, e.g., by using an external pull-up
resistor, if DIN is configured as an input.
Programming the FPGA With Counters
Unchanged Upon Completion
When multiple FPGA-configurations for a single FPGA are
stored in a Serial Configuration PROM, the OE pin should
be tied Low. Upon power-up, the internal address counters
are reset and configuration begins with the first program
stored in memory. Since the OE pin is held Low, the
address counters are left unchanged after configuration is
complete. Therefore, to reprogram the FPGA with another
program, the Dip line is pulled Low and configuration
begins at the last value of the address counters.
I
XC1700D Family of Serial Configuration PROMs
This method fails if a user applies RESET during the FPGA
configuration process. The FPGA aborts the configuration
and then restarts a new configuration, as intended, but the
Serial PROM does not reset its address counter, since it
never saw a High level on its OE input. The new configuration, therefore, reads the remaining data in the PROM and
interprets it as preamble, length count etc. Since the FPGA
is the master, it issues the necessary number of CCLK
pulses, up to 16 million (224) and Dip goes High. However,
the FPGA configuration will be completely wrong, with
potential contentions inside the FPGA and on its output
pins. This method must, therefore, never be used when
there is any chance of external reset during configuration.
caded SCPs provide additional memory. After the last bit
from the first SCP is read, the next clock signal to. the SCP
asserts its CEO output Low and disables its DATA line. The
second SCP recognizes the Low level on its CE input and
enables its DATA output. See Figure 2.
After configuration is complete, the address counters of all
cascaded SCPs are reset if the FPGA RESET pin goes
Low, assuming the SCP reset polarity option has been
inverted.
To reprogram the FPGA with another program, the Dip line
goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention
between DATA and the configured 1/0 use of DIN.
Cascading Serial Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
5-14
November 25, 1997 (Version 1.1)
~XILINX
* If Readback is
Activated, a
5-kQ Resistor is
Required in
Series With M1
During Configuration
the 5 kQ M2 Pull-Down
Resistor Overcomes the
Internal Pull-Up,
but it Allows M2 to
be UserI/O.
'-
-
GeneralPurpose -<
UserI/O
Pins
!
I I
MO
'-----
+5V
*
~
M1
PWRDWN
DOUT
-
M2
-
HDC
~OPTIONAl
Daisy-chained
FPGAswith
. - - Different
Configurations
----< lDC
--<: INIT
-
····
-
·
Other
I/O Pins
OPTIONAL
r---- Slave FPGAs
XC3000
FPGA
Device
, - with Identical
Configurations
I
+5V
RESET
----<
I
RESET
Vpp
Vcc
DIN
CClK
DATA
--------,
W
I
ClK
SCP
D/P
CE
INIT
OE/RESET
CEO
I
I
DATA
~ CE
ClK
Cascaded
Serial
Memory
I
I
I
I
I OE/RESET
I
:
1- - ______ 1
(low Resets the Address Pointer)
CClK
(OUTPUT)
DIN
DOUT
(OUTPUT)
X5090
Figure 2: Master Serial Mode. The one-time-programmable Serial Configuration PROM supports automatic loading of
configuration programs. Multiple devices can be cascaded to support additional FPGA. An early Dip inhibits the
PROM data output one CCLK cycle before the FPGA II0s become active.
November 25, 1997 (Version 1.1)
5-15
XC1700D Family of Serial Configuration PROMs
Standby Mode
The PROM enters a low-power standby mode whenever
CE is asserted High. The output remains in a high impedance state regardless of the state of the DE input.
Programming the XC1700 Family
Serial PROMs
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
Table 1: Truth Table for XC1700 Control Inputs
Control Inputs
RESET
CE
Inactive
Low
Active
Inactive
Active
Low
High
High
Outputs
Internal Address
DATA
if address s; TC: increment
if address> TC: don't change
Held reset
Not changing
Held reset
active
3-state
3-state
3-state
3-state
CEO
High
Low
High
High
High
Icc
active
reduced
active
standby
standby
Notes: 1. The XC1700 RESET input has programmable polarity
2. TC =Terminal Count = highest address value. TC+ 1 =address O.
5-16
November 25, 1997 (Version 1.1)
~XILINX
XC1718D, XC1736D, XC1765D, XC17128D and XC17256D
Absolute Maximum Ratings
Symbol
Description
Units
Vee
Supply voltage relative to GND
-0.5 to +7.0
V
Vpp
Supply voltage relative to GND
-0.5 to + 12.5
V
Y,N
Input voltage relative to GND
-0.5 to Vee +0.5
V
VTS
Voltage applied to 3-state output
-0.5 to Vee +0.5
V
TSTG
Storage temperature (ambient)
-65 to +150
°C
TSOL
Maximum soldering temperature (10 s @ 1/16 in.)
+260
°C
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
Operating Conditions
Symbol
Vee
Description
Min
Max
Units
Commercial
Supply voltage relative to GND O°C to +70°C junction
4.75
5.25
V
Industrial
Supply voltage relative to GND -40°C to +85°C junction
4.50
5.50
V
Military
Supply voltage relative to GND -55°C to + 125°C case
4.50
5.50
V
DC Characteristics Over Operating Condition
Symbol
Description
Min
Max
Units
V ,H
High-level input voltage
2.0
Vcc
V
V ,L
Low-level input voltage
0
0.8
V
V OH
High-level output voltage (loH = -4 mAl
VOL
Low-level output voltage (IOL = +4 mAl
VOH
High-level output voltage (IOH = -4 mAl
VOL
Low-level output voltage (IOL = +4 mAl
V OH
High-level output voltage (IOH = -4 mAl
VOL
Low-level output voltage (IOL = +4 mAl
0.4
V
ICCA
Supply current, active mode
10.0
mA
Iccs
Supply current, standby mode, XC17128D, XC17256D
50.0
)lA
1.5
mA
10.0
)lA
Commercial
0.32
Industrial
3.76
Military
Input or output leakage current
3.7
-10.0
V
V
0.37
Supply current, standby mode, XC1718D, XC1736D, XC1765D
'L
V
3.86
V
V
Note: During normal read operation Vpp must be connected to Vcc
November 25, 1997 (Version 1.1)
5-17
I
XC1700D Family of Serial Configuration PROMs
XC1718L, XC1765L, XC17128L and XC17256L
Absolute Maximum Ratings
Symbol
Description
Units
Vcc
Supply voltage relative to GND
-0.5 to +6.0
V
V pp
Supply voltage relative to GND
-0.5 to + 12.5
V
VIN
Input voltage with respect to GND
-0.5 to Vcc +0.5
V
VTS
Voltage applied to 3-state output
-0.5 to Vcc +0.5
V
TSTG
Storage temperature (ambient)
-65 to +150
°C
TSOL
Maximum soldering temperature (10 s @ 1/16 in.)
+260
°C
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating
Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device
reliability.
Operating Conditions
Symbol
Vcc
Description
Commercial
Min
Max
Units
3.0
3.6
V
Supply voltage relative to GND O°C to +70°C junction
DC Characteristics Over Operating Condition
Symbol
Description
Min
Max
Units
V IH
High-level input voltage
2.0
Vcc
V
V IL
Low-level input voltage
0
0.8
V
V OH
High-level output voltage (IOH
VOL
=-4 mAl
Low-level output voltage (l0L =+4 mAl
ICCA
Iccs
IL
2.4
V
0.4
V
Supply current, active mode
5.0
mA
Supply current, standby mode, XC1718L, XC1765L
Supply current, standby mode, XC17128L, XC17265L
1.5
50.0
mA
10.0
~A
Input or output leakage current
-10.0
~A
Note: During normal read operation V pp must be connected to V cc
5-18
November 25, 1997 (Version 1.1)
~XILINX
AC Characteristics Over Operating Condition
®
"
- ® ~@J L
TSCE
RESET/DE
t--
- - TLc----
\
ClK
-+
t--
®
TOE
T HCE
TSCE
\
t--G)
TCE
;~,
e--- @
@THC
@TCYC-
i
0
-
®
-
t--
TCAC
)
DATA
0
TOH
t--
t--
-+
@TDF
N
Vi
K
t--
-+
0TOH
X2634
Symbol
Description
XC1718D
XC1736D
XC1765D
Min
1
2
3
4
5
6
TOE
TCE
T CAC
TOH
TOF
OE to Data Delay
CE to Data Delay
ClK to Data Delay
Data Hold From CE, OE, or ClK
CE or OE to Data Float Delay2
TCYC
7
hc
8
THC
TSCE
Clock Periods
ClK low Time3
ClK High Time3
CE Setup Time to ClK (to guarantee
proper counting)
CE Hold Time to ClK (to guarantee
proper counting)
OE Hold Time (guarantees counters are
reset)
9
10 T HCE
11 T HOE
Max
XC1718l
XC1765l
Min
45
60
150
Max
XC17128D
XC17256D
XC17128l
XC17256l
Min
Min
45
60
200
Max
25
45
50
I
Units
Max
30
60
60
200
100
100
25
400
100
100
40
80
20
20
20
100
25
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
ns
100
100
20
25
ns
0
0
50
0
50
0
50
50
Notes: 1. AC test load = 50 pF
2. Float delays are measured with minimum tester ac load and maximum dc load.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V1l = 0.0 V and V1H = 3.0 V.
November 25, 1997 (Version
1,1)
5-19
XC1700D Family of Serial Configuration PROMs
AC Characteristics Over Operating Condition (continued)
v:
RESET/QE
7
~
elK
7~
@TCDF-
I+/
~r
DATA
last Bitl
@ToCK
-I
,f-
I+-J-
-'~
I+-
@ToCE -
Symbol
Description
XC1718D
XC1736D
XC1765D
Min
12
13
14
15
TCDF
TOCK
TOCE
TOOE
ClK to Data Float Delay2
ClK to CEO Delay
CE to CEO Delay
RESET/OE to CEO Delay
~t-
Max
50
65
45
40
-
I+-@TooE
,'-
I+-@ToCE
X3183
XC1718L
XC1765L
Min
-
First Bit
Max
50
65
45
40
XC17128D
XC17256D
XC17128L
XC17256L
Min
Min
Max
50
30
35
30
Units
Max
50
30
35
30
ns
ns
ns
ns
Notes: 1. AC test load = 50 pF
2. Float delays are measured with minimum tester ae load and maximum dc load.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V.
5-20
November 25, 1997 (Version 1.1)
~XILINX
Ordering Information
XC17360 - PC20 C
Device Number
XC1718D
XC1718L
XC1736D
XC1765D
XC1765L
XC17128D
XC17128L
XC17256D
XC17256L
______---'I~ TL______
Package Type
= 8-Pin Plastic DIP
= 8-Pin CerDIP
= 8-Pin Plastic Small-Outline Package
= 8-Pin Plastic Small-Outline Thin Package
= 20-Pin Plastic Leaded Chip Carrier
PD8
DD8
S08
V08
PC20
Operating Range/Processing
C = Commercial (0° to +70°C)
I = Industrial (-40° to +85°C)
M = Military (-55° to + 125°C)
B = Military (-55° to + 125°C)
MIL-STD-883 Level B compliant
Valid Ordering Combinations
XC17128DPD8C
XC17128DV08C
XC17128DPC20C
XC17128DPD81
XC17128DV081
XC17128DPC201
XC17128DDD8M
XC1718DPD8C
XC1718DS08C
XC1718DV08C
XC1718DPC20C
XC1718DPD81
XC1718DS081
XC1718DV081
XC1718DPC201
XC17256DPD8C
XC17256DV08C
xc 17256DPC20C
XC17256DPD81
xc 17256DV081
xc 17256DPC201
xc 17256DDD8M
xc 17256DDD88
XC17128LPD8C
XC17128LV08C
XC17128LPC20C
XC17128LPD81
XC17128LV081
XC17128LPC201
XC1718LPD8C
XC1718LS08C
XC1718LV08C
XC1718LPC20C
XC1718LPD81
XC1718LS081
XC1718LV081
XC1718LPC201
XC17256LPD8C
XC17256LV08C
xc 17256LPC20C
XC17256LPD81
XC17256LV081
XC17256LPC201
XC1736DPD8C
XC1736DS08C
XC1736DV08C
XC1736DPC20C
XC1736DPD81
XC1736DS081
XC1736DV081
XC1736DPC201
XC1736DDD8M
XC1765DPD8C
XC1765DS08C
XC1765DV08C
XC1765DPC20C
XC1765DPD81
XC1765DS081
XC1765DV081
XC1765DPC201
XC1765DDD8M
XC1765DDD8B
XC1765LPD8C
XC1765LS08C
XC1765LV08C
XC1765LPC20C
XC1765LPD81
XC1765LS081
XC1765LV081
XC1765LPC201
I
Marking Information
Due to the small size of the serial PROM package, the complete ordering part number cannot be marked on the package.
The XC prefix is deleted and the package code is simplified. Device marking is as follows.
J
17360
Device Number
XC1718D
XC1718L
XC1736D
XC1765D
XC1765L
XC17128D
XC17128L
XC17256D
XC17256L
------,I
P
C
T~
Package Type
P
D
S
V
J
8-Pin Plastic DIP
8-Pin CerDIP
8-Pin Plastic Small-Outline Package
8-Pin Plastic Small-Outline Thin Package
20-Pin Plastic Leaded Chip Carrier
November 25, 1997 (Version 1.1)
Operating Range/Processing
C
I
M
B
=
=
=
=
Commercial (0° to +70°C)
Industrial (-40° to +85°C)
Military (-55° to + 125'C)
Military (-55° to + 125°C)
MIL-STD-883 Level B compliant
5-21
XC1700D Family of Serial Configuration PROMs
5-22
November 25, 1997 (Version 1.1)
3V Products
1
Introduction
2
Development System Products and CORE Solutions Products
3
CPLD Products
4
FPGA Products
5
SPROM Products
6
3V Products
7
HardWire FpgASIC Products
8
High-Reliability and QML Military Products
9
Programming Support
10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support and Services
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors
3V Products
Table of Contents
3.3 V and Mixed Voltage Compatible Products
FPGAs ........................... '" ..... " ......................................
3.3 V High-Density FPGAs with On-Chip RAM: XC4000XL ...........................
3.3 V FPGAs Without On-Chip RAM: XC5200XL and XC3100L. .. , ....................
3.3 V Zero+ Family of Ultra-Low Power FPGAs: XC3000L ............................
5 V FPGAs for Mixed-Voltage Systems: XC4000E and XC4000EX ......................
CPLDs ............................ " .............................................
5 V CPLDs for Mixed-Voltage Systems: XC9500 ....................................
Interfacing Between 5 V and 3.3 V Devices ..............................................
3.3 V Devices Driving Inputs on 5 V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5 V Devices Driving Inputs on 3.3 V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Using the XC4000E/EX FPGAs in Mixed-Voltage Systems ............................
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
6-1
6-1
6-1
6-1
6-1
6-1
6-1
6-2
6-2
6-2
6-3
6-4
3.3 V and Mixed Voltage
Compatible Products
November 20, 1997 (Version 2.1)
The use of advanced deep-submicron IC fabrication processes is resulting in rapidly increasing density and performance for programmable logic devices, as evidenced by
the XC4000XL FPGA family. However, as device geometries shrink below 0.5 microns, the smallest transistors cannot withstand 5 volts without damage. Thus, the largest and
fastest new devices are based on lower supply voltages,
such as the 3.3 V standard.
To reap the benefits of advanced process technology including increased performance, increased density, lower
power consumption, and lower price - many programmable
logic users are making the transition from the 5.0 V stan'
dard to lower voltages. This transition affects not only the
supply voltage, but also 110 signaling levels. Xilinx is taking
an active lead in working with programmable logic users to
plan an orderly transition from one voltage standard to the
next.
Xilinx introduced the Zero+ ™ product line, the industry's
first 3.3 V FPGAs, in 1993. Since then, the number of 3.3 V
product offerings has increased dramatically. For example,
the new XC4000XL FPGA family, featuring the industry's
highest-capacity high-performance FPGAs, is based on the
3.3 V standard.
However, many other system components remain available
in 5.0 V versions only. Thus, mixed'voltage systems (Le.,
systems employing a mix of 5.0 V and 3.3 V components)
are likely to be the rule rather than the exception in the
immediate future. Xilinx products have been designed with
this in mind (see Table 1).5.0 V input tolerance has been
designed into many Xilinx 3.3 V devices; these devices
accept 5.0 V signals on all liDs and can drive TTL levels
into any 5.0 V device, eliminating any interface issues.
Many Xilinx 5.0 V components can directly interface with
3.3 V devices. Future devices will feature multi-voltage liDs
capable of interfacing between a variety of liD standards.
All Xilinx device inputs maintain their excellent protection
against Electro-Static Discharge (ESD), even in mixed-voltage applications.
The following is a.brief description of Xilinx devices suitable
for use in 3.3 V and mixed 3.3/5.0 V systems. Complete
data sheets for the products mentioned below can be found
in Chapters 3 and 4 of this Data Book. 3.3 V versions of the
Serial PROM devices also are available (see Chapter 6).
November 20, 1997 (Version 2. t)
FPGAs
3.3 V FPGAs with On-Chip RAM: XC4000XL
and Spartan-XL
The XC4000XL family is the broadest and highest-capacity
3.3 V FPGA product line in the industry, with ten devices
ranging from 465 to 7,448 logic cells (about 5,000 to 85,000
logic gates). The Spartan Series of high-performance, lowcost FPGAs offers five devices ranging from 238 to 1,862
logic cells. The XC4000XL and Spartan-XL devices meet
the specifications of 3.3 V PCI applications. See Chapter 4
for complete product descriptions.
3.3 V FPGAs Without On-Chip RAM:
XC3100L
The two members of the XC3100L FPGA family are fast
3.3 V FPGAs. See Chapter 4 for complete product descriptions.
3.3 V Zero+ Family of Ultra-Low Power
FPGAs: XC3000L
TheXC3000L FPGA devices have quiescent supply currents below 1 mA, with some below 50 !lA. See Chapter 4
for complete product descriptions.
5.0 V FPGAs for Mixed-Voltage Systems:
XC4000E/EX and Spartan Series
The 5.0 V XC4000E/EX and Spartan FPGA families feature a unique output structure that makes them suitable for
mixed-voltage system applications. When configured in
TIL mode, the XC4000E/EX and Spartan devices can be
directly mixed with 3.3 V devices, as described below. See
Chapter 4 for complete product descriptions.
CPLDs
5.0 V CPLDsfor Mixed-Voltage Systems:
XC9500
Xilinx CPLDs are an excellent fit for mixed-voltage systems.
The Input/Output (110) ring can be powered by either a
5.0 V VCC10 or a 3.3 V VCCIO' Independent of the VCCIO
voltage level, the inputs can accept 5.0 V and 3.3 V inputs.
The rail-to-rail output level is defined by VCCIO These single-chip solutions function extremely well in mixed-voltage
systems without any performance penalty. See Chapter 3
for complete product descriptions.
6-1
I
3.3 V and Mixed Voltage Compatible Products
Table
1: Supply Voltage Options
Device
Family
Single
Supply
Vee S.OV
=
Single
Supply
Vee 3.3V
=
Dual
Supply
Vee S.OV
V eelO 3.3V
=
=
Notes:
XC3000A
XC3100A
XC4000E/EX
Spartan
XC5200
XC9500
Device
Family
XC3000L
XC3100L
XC4000XL
Spartan-XL
Device
Family
XC9500
Accepts 3.3 V
Availability Device Outputs 1
Now
Now
Now
Now
Now
Now
Yes
Yes
Yes
Yes
Yes
Yes
Accepts 5.0 V
Availability Device Outputs
Now
Now
Now
3098
With limiting resistor
With limiting resistor
Yes
Yes
Accepts 5.0 V
Availability Device Outputs
Yes
Now
Key Features
With limiting resistor
With limiting resistor
Yes
Yes
With limiting resistor
With limiting resistor
Low quiescent current
High performance
Highest density and performance
High performance, low cost
Most cost-effective
5.0 V in-system-programmable, pin locking
DrivesS.OV
Device Inputs
Key Features
Yes
Yes
Yes
Yes
Very low powerdown & quiescent current
High performance
Highest Density & performance
Cost-effective, high performance
Drives S.OV
Device Inputs
Key Features
Yes
Mixed-voltage system capable
1. Device Inputs must be configured for TTL thresholds.
Interfacing Between 5.0 V and 3.3 V
Devices
Today, many designs must accommodate both 3.3 V and
5 V components on the same board. Since both types of
supply share a common ground, there are no problems
interfacing logic Low levels in either direction, but there are
compatibility issues for the logic High levels.
3.3 V Devices Driving Inputs on 5.0 V
Devices
The lowest output High voltage (VOH ) of the 3.3 V device
must exceed the V IH requirements of the 5.0 V device. Minimum VOH for all Xilinx 3.3 V devices is 2.4 V, well above
the 2.0 V minimum High level for TTL signaling. (This
includes the XC3000L, XC3100L, XC4000XL, and Spartan-XL FPGA families and the XC9500 CPLD family when
Vee10 = 3.3V.) Thus, all Xilinx 3.3 V devices can drive
inputs to devices with TTL-compatible input thresholds,
including all 5.0 V Xilinx devices. (Note: Some Xilinx 5.0 V
devices can be programmed for TTL or CMOS input thresholds; these devices must be configured for TTL-compatible
inputs to be directly driven from a 3.3 V device.)
5.0 V Devices Driving Inputs on 3.3 V
Devices
The highest 5.0 V device output .voltage must not force
excessive current into the input of the 3.3 V device. The
input structures of Xilinx 3.3 V FPGAs include input protection circuits. These protection circuits in the XC3000L and
XC3100L devices are designed for 3.3 V inputs. However,
6-2
Drives 3.3V
Device Inputs
the protection circuits in the XC4000XL and Spartan-XL
devices are designed to withstand 5.0 V inputs.
Most 5.0 V devices have complementary CMOS outputs
where VOH can reach the 5.0 V rail. (All Xilinx 5.0 V FPGAs
and CPLDs, except the XC4000E/EX and Spartan series
devices in default TTL mode, have complementary CMOS
outputs. The XC4000E/EX and Spartan devices can be set
to CMOS outputs with the design software.) When driving
XC3000L and XC3100L inputs (and most other 3.3 V
devices) from such a 5.0 V device, the input current must
be limited by a series resistor of no less than 150Q. This
guarantees an input current below 10 mA, flowing through
the ESD input protection diode backwards into the 3.3 V
supply. That amount of input current is generally considered safe, causing neither metal migration nor latch-up
problems. Care must be taken to avoid forcing the nominally 3.3 V supply voltage above its 3.6 V maximum whenever a large number of active High inputs drive the 3.3 V
device, potentially causing the 3.3 V supply current to
reverse direction. The 3.3 V Vee power should be on
before driving the device inputs from a 5.0 V device.
The 1/0 structures of the XC4000XL and Spartan-XL
FPGAs have been designed to tolerate being driven to a
5.0 V rail by a low-impedance source. These 3.3 V FPGAs
can be directly driven by 5.0 V devices with either TTL or
CMOS outputs. Power supply sequencing is not a problem;
the inputs can be driven to 5.0 V either before or after the
3.3 V Vee power is supplied without risking damage to the
devices.
In mixed voltage systems, the XC9500 CPLD family can be
driven directly by 5.0 V inputs when set up for 3.3 V 110
November 20, 1997 (Version 2.1)
~XILINX
operation (i.e., Veelo = 3.3 V). The input protection circuits
in these CPLDs are always connected to the 5.0 V Vee
power line, allowing them to tolerate 5.0 V inputs without
the need for current-limiting resistors.
istic of a typical 3.3 V device input. Both supply voltages
are at their nominal value, but the die temperatures are at
their worst-case. value of 85 degrees C, and worst-case
processing is assumed.
If the 5.0 V device has "totem-pole" n-channel-only outputs
(as in the default setting of the XC4000E/EX and Spartan
FPGA series), VOH is reduced by one threshold and the
series resistor can be eliminated, provided the nominally
5.0 V supply does not exceed 5.25 V (as described in detail
in the following section). Thus, the XC4000E/EX and Spartan FPGAs can directly drive any 3.3 V device without the
need for current-limiting resistors.
2 shows the same curves, but with 5.25 V and 3.0 V
Vee respectively. The intersection of the two curves defines
the worst-case operating point of 3.8 V and 6 mA. That
means that the XC4000E/Spartan output drives 6 mA into
the forward-biased ESD protection diode, raising the input
voltage 0.8 V above 3.0 V, the assumed lowest value of the
nominally 3.3 V supply Voltage.
USing the XC4000E/EX and Spartan FPGAs
in Mixed-Voltage Systems
As a default option, all XC4000E/EX and Spartan devices
have a TIL-like input threshold (compatible with 3.3 V output levels) and an n-channel-only "totem-pole" or TTL-like
output structure, with an n-channel transistor pulling the
output to a VO H level that is one threshold below Vee.
At a nominal 5.0 V Vee, the unloaded output High voltage
VOH is less than 3.7 V. When applied to the input of a device
with a nominal 3.3 V Vee, there is no additional input current, and the input level does not violate the conventional
specification that prohibits input voltages more than 0.5 V
above Vee. See Figure i.
liN
mA
10
Nominal
Supply Voltages
lOUT
85°C
8
7
6
5
4
I
2
Y,-L--1""...I.~-""'--...,j---t-_---.J
3.0
3.3 3.5
4.0
4.5
5.0
Vee
5.5
X5969
If both 5.0 V and 3.3 V supply voltages track reasonably
between their maximum and minimum values, there will
never be any additional input current in excess of 1 mA at
any commercial or industrial operating temperature.
A worst-case analysis of the interface might assume the
(unrealistic) condition where the 5.0 V supply is at its maximum value (5.25 V for commercial applications), while the
3.3 V supply is at its minimum value of 3.0 V. Under these
conditions, the interface violates the conventional specification, and drives current into the input of the 3.3 V device, as
shown in Figure 2. However, as explained below, this interface is reliable.
For protection against electro-static discharge (ESD), most
CMOS inputs and 1/0 pins usually have a diode between
the pin and the nearest Vee connection. This diode prevents the input from going substantially more positive than
Vee, which might destroy the input transistor by rupturing
its gate oxide. At room temperature, this ESD protection
diode conducts negligible current at < 0.6 V forward bias,
and conducts -1 mA at -0.7 V forward bias, typical for any
silicon junction diode. These voltages have a predictable
negative temperature coefficient of -2 mV per degree C. At
85 degrees C, these voltages are, therefore, 120 mV lower.
Figure 1: XC4000E/Spartan Output in "TTL-Mode"
driving 3.3 V Device Input with Both Supplies at
Nominal Voltage (5.0 V and 3.3 V)
mA
10
8
6
5
4
3
2
~-+---*~-~---...I.--~-~~
vee
3.0
3.5
4.0
4.5
5.0
5.5
XS970
Figure 2: XC4000E/Spartan Output in "TTL-Mode"
driving 3.3 V Device Input with Both Supplies at
Extreme Values (5.25 V and 3.0 V)
1 superimposes the output characteristic of the
XC4000E/EX and Spartan, and the input current character-
November 20, 1997 (Version 2.1)
6-3
3.3 V and Mixed Voltage Compatible Products
Although this input condition is not covered by the conventional specification, it does not cause any harm and does
not affect reliability. ESD protection diodes are designed to
conduct hundreds of mA, and the absolute value of the
input voltage with respect to ground will never exceed 3.9 V.
If the input pin is part of an 1/0 structure, there is a theoretical possibility of causing latch-up, but all reputable IC manufacturers design .their circuits such that latch-up does not
occur below 100 mA of input current per pin.
The system designer must estimate the sum of all maximum input currents, and calculate the impact of this current
flowing backwards towards the 3.3 V supply. But even if the
total 3.3 V supply current goes to zero, Vee for the 3.3 V
device is still limited to < 3.6 V (the highest output voltage of
the 5 V device minus the forward voltage drop of the ESD
diode).
6-4
Conclusion
5 V XC4000E/EX and Spartan devices can be freely mixed
with 3.3 V devices, without any current or voltage limiting
interface resistors, if the following conditions are met:
• The 5.0 V XC4000E/EX and Spartan devices are in
their default "TTL mode" with respect to input
thresholds and output levels.
• The upper limit on the 5 V Vee is 5.25 V and the lower
limit on the 3.3 V supply is 3.0 V, as per standard
commercial specifications.
• For industrial operating conditions with higher Vee max,
the user must make sure that the absolute difference
between the two supply voltages does not exceed 2.20 V.
Specifically, if the nominally 5 V Vee is at its max value of
5.50 V, the nominally 3.3 V Vee must not be lower than
3.30 v.
November 20, 1997 (Version 2.1 )
HardWire FpgASIC Products
1
Introduction
2
Development System Products and CORE Solutions Products
3
CPLD Products
4
FPGA Products
5
SPROM Products
6
3V Products
7
HardWire FpgASIC Products
8
High..;Reliability and QML Military Products
9
Programming Support
10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support and Services
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors
HardWire Products
Table of Contents
Xilinx HardWire ™ FpgASIC Overview
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Technology Overview .............................................................. ,
Advantages of the Xilinx HardWire Methodology ..........................................
Re-verifying the Design ..............................................................
Fault Coverage and Test Vectors ......................................................
Packaging and Silicon Considerations ..................................................
Support for the entire Product Life Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
HardWire Designl Production Interface ..................................................
Design Submittal Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Summary of the Conversion Process ...................................................
HardWire Product Families ...........................................................
Xilinx HardWire Product Descriptions ...................................................
XC23xx, XC33xx and XC43xx Product Description ..................................
XC23xx, XC33xx and XC43xx Summary ..........................................
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC44xxE/EXlXL and XC54xx Product Description ...................................
XC44xx/E/EX/XL and XC54XX Summary..........................................
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XH3 Product Description .......................................................
XH3 Summary ...............................................................
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
HardWire Summary ..........................................................
7-1
7-1
7-1
7-1
7-2
7-2
7-2
7-3
7-3
7-3
7-5
7-5
7-5
7-5
7-5
7-5
7-5
7-6
7-6
7-6
7-6
7-6
7-6
7-6
7-6
Xilinx HardWire™ FpgASIC
Overview
November 4, 1997 (Version 2.0)
Introduction
When a system incorporating Xilinx FPGA's moves to high
volume production, HardWire FpgASIC products should be
the first consideration for cost reduction. HardWire products are the only devices developed specifically for Xilinx
FPGA's which provide 100% pin compatible replacements.
The HardWire conversion flow coupled with the HardWire
test methodology provides a no risk path for customers to
achieve dramatic cost reductions. Using Xilinx FPGA's and
HardWire technology provides the customer with a single
source for systems, software and silicon. This combination
provides the fastest method for prototype development and
production of systems based on leading edge programmable logic technology. Each HardWire product family is
developed to match the performance and features of specific Xilinx FPGA's including the popular XC2xxx, XC3xxx,
XC4xxx and XC5xxx series families. The newest family of
HardWire FpgASIC's are designed to provide a cost
reduced device incorporating the latest features of Xilinx
FPGA's including E, EX and XL technology.
Technology Overview
Xilinx Hardwire ASIC products are FPGA specific ASIC's
(FpgASIC's). They are a family of devices ranging from
1.011 single mask mapped ASIC's to state-of-the-art sea-ofgates 0.511 and 0.3511 multi-mask ASIC devices. The HardWire product families have been developed to match the
performance and features of each generation of Xilinx
FPGA's.
The HardWire flow is the simplest method for cost reducing
an FPGA based system. The Xilinx "Design Once" methodology offers Xilinx customers the advantages of developing
prototypes, building pre-production and initial production
volumes using Xilinx FPGAs. Once the designis stable and
cost reduction is critical, customers can convert the FPGA
to a HardWire device developed especially for the features
and performance of that FPGA.
The turnkey conversion process allows production quality
HardWire prototypes to be developed in half the time of traditional gate arrays. The HardWire methodology provides
this without using customers' engineering resources. HardWire FpgASIC's provide a cost - effective alternative to gate
arrays.
path that is 100% guaranteed to perform in the user's application.
Advantages of the Xilinx HardWire
Methodology
Converting a device from programmable logic to a HardWire FpgASIC has many advantages over standard gate
array redesign. The most important is that HardWire
devices are developed using a fully turnkey process. No
additional customer engineering is required to convert the
programmable logic design into a fully tested, completely
verified HardWire device. This ease of conversion is available only from Xilinx. HardWire devices. are developed
using the actual physical database previously created and
verified in the process of developing the FPGA design. The
HardWire conversion methodology preserves all the
attributes of the original physical database file. If the design
is mapped to a third party library at the schematic level for
conversion to another technology, the design must be verified and prototyped. Third party implementations will
change the placement and routing, thereby changing the
design's performance characteristics. This means the new
device must be re-verified andre-tested in the system to be
certain that the performance and functionality still meet the
applications requirements. A comparison of the activities
required to convert a HardWire. FpgASIC versus a generic
gate array is shown in Figure i.
Re-verifying the Design
In conventional gate array conversion (redesign), the
design must be re-verified after the schematic is translated
or recaptured. The process of re-verifying a design is rigorous and time consuming. Functional simulation vectors
need to be created, and the device must be exhaustively
simulated before and after place and route. A suitable test
methodology must be considered and implemented. All this
is usually done by the customer, at the customers' expense
and risk.
In contrast, no additional effort is required when converting
to a HardWire FpgASIC. The HardWire design is self-verifying because the actual FPGA database files are used for
the conversion. This makes the HardWire conversion process the only guaranteed, fully turnkey FpgASIC conversion.
Xilinx HardWire product families use a combination of
industry standard andXilinx patented test generation methods to achieve the most complete fault coverage possible.
This testing strategy allows Xilinx to offer a cost reduction
November 4,1997 (Version 2.0)
7-1
I
Xilinx HardWire™ FpgASIC Overview
Working Xilinx FPGA Design
G.".," Gate "'''' /
•
•
•
•
•
•
•
~xm""
Convert netlist to G/A format
Logic changes for design compatibility
Logic changes for pin compatibility
Logic changes for configuration emulation
Logic changes for Boundary Scan
Design Check
Functional Simulation
Place and Route
• Back-Annotation
• Timing simulation and new models
• Test Vector generation
• Create custom masks
Ha_',. FpgASIC
•
Design Check/Evaluation
•
Design Conversion
•
Create Custom Masks
Figure 1: Steps Involved in Converting a PLD Design to a Gate Array as Compared to a HardWire FpgASIC
Fault Coverage and Test Vectors
All designs need to be testable. In a traditional gate array,
the designer is required to build in testability and generate
test vectors to verify chip performance by exercising as
much of the device circuitry as possible. Most designers
strive for greater than 90% fault coverage. However, they
often settle for significantly less because the iterative process is time consuming and increases exponentially as
fault coverage is increased. A third party conversion from a
Xilinx FPGA to a generic gate array or other similar technology will require test vector generation. Typically, the original
designers create test vectors, since they are most familiar
with the FPGA's design. This method misuses valuable
design resources and reverses the value of the decision to
use programmable logic for their ease of design and timeto-market advantage. Another method is to contract with
the conversion or gate array vendor to create the test vectors. This method is both expensive and time consuming. In
some cases, conversion or gate array vendors will accept a
design without test vectors, but the customer accepts the
liability of determining whether the resulting device is production worthy. In today's competitive market, most projects
can not afford the risk of possible re-spins if the design
doesn't work.
Converting from a Xilinx FPGA to a HardWire FpgASIC
requires no test vector generation by. the customer. HardWire devices use a combination of industry standard and
Xilinx patented test generation methods to achieve the
most complete fault coverage possible. Xilinx guarantees
greater than 95% fault coverage for most designs. All HardWire FpgASIC's are tested using a full scan test methodology. The HardWire conversion and test methodology
provides a cost reduction path that is guaranteed to work in
the customer'S application.
7-2
Packaging and Silicon
Considerations
All of the physical attributes of HardWire FpgASIC's are virtually identical to the Xilinx FPGA. HardWire devices are
manufactured in the same fabrication facilities used by XiIinx for the production of FPGA's. The same design rules, IC
process, as well as packaging, assembly, and test facilities
are used. This allows a significant reduction in the time and
cost associated with qualifying HardWire devices.
Converting from a Xilinx programmable logic device to any
third party device means a change in silicon, packaging,
assembly and test. Each of these changes adds an element of risk into the qualification process.
Support for the entire Product Life
Cycle
2 shows the typical life cycle of a high-volume product. It illustrates the optimal way of using the programmable
and HardWire devices. During development, prototyping
and initial production cycles, the programmable device is
the best choice. As the system moves into higher volume
production and no additional modifications are being made
to the design, a HardWire FpgASIC can be used in place of
the original programmable logic device.
Since the HardWire device and the programmable logic
device are functionally and physically identical, production
can be switched back to the programmable device if the situation warrants. For example, if the demand for the customer's product increases dramatically, production can be
increased immediately by full-filling the additional demand
with programmable devices. The change can be made
immediately since there is virtually no lead-time for an off-
November 4, 1997 (Version 2.0)
~XILINX
Programmable Logic Volume
HardWire FpgASIC Volume
Unplanned Upside
Production
Ramp-Up
v
o
L
U
M
E
HardWire
FpgASIC
X5946
Figure 2: Typical High Volume Product Life Cycle
the-shelf programmable device. Production can also be
switched to the programmable device as the product ends
its life cycle and volume decreases. This eliminates the
need for end-of-life buys and the risk of obsolescence.
Furthermore, designs implemented with multiple static
RAM based programmable devices can be cost reduced
incrementally, converting one or more of the programmable
devices to a HardWire FpgASIC with the balance remaining
as FPGAs. As each FPGA is converted to a HardWire
device, the user benefits by having a lower cost for that
device. This also allows the user to maintain the ease of
use of off-the-shelf programmable logic in the other sockets. When all of the devices are converted, the storage element (PROM) can be removed, giving even further cost
reductions. This flexibility is unique to Xilinx, and allows
customers to achieve cost reduction quickly with minimal
effort.
HardWire Designl Production
Interface
3 illustrates how the design, development and production activities for both Programmable Logic devices and
HardWire FpgASICs are sequenced. Notice that by using
the Xilinx "Design Once" methodology, no additional customer activity is needed to develop the HardWire FpgASIC.
If design simulation is done in the programmable logic
device during development, special HardWire speed files
may be also be used for design verification. This allows XiIinxto perform a very simple design check procedure prior
to generating the HardWire device. After the design check
is complete the H.ardWire prototypes can be manufactured.
The customer then performs in-system verification of the
prototypes. Once this verification is complete the HardWire
FpgASIC can be released to production. Since the func-
November 4, 1997 (Version 2.0)
tionality of the FPGA and HardWire device are identical, virtually no customer engineering resources are needed to
move from the programmable to the HardWire devices or
vice versa. By comparison, using a traditional gate array to
reproduce functions implemented in the FPGA would
require extensive simulation and test development.
I
Design Submittal Process
Once the complete design submittal kit is received the
HardWire conversion process takes from 3 to 8 weeks. The
conversion time will vary with the addition of features such
as Select-RAM, Configuration Emulation and JTAG. A complete design submittal kit contains the following:
1. Files: .LCA (or .NGD for M1 designs), .MBO, and .BIT
files on disk.
2. Hard copy of a board level schematic showing how the
FPGA interfaces with other components on the board (if
possible).
3. A detailed explanation of any special requirements for
the conversion.
4. A design submittal form and NRE PO.
All forms can be found in the HardWire data book and on
the Xilinx web page under HardWire products.
Summary of the Conversion
Process
The HardWire FpgASIC conversion process is the simplest
way to cost reduce systems designed using FPGAs. The
customer is involved in tracking and approving milestones.
Xilinx handles the day-to-day activities of converting the
design to a HardWire device. Once Xilinx receives a complete design submittal kit the conversion process begins.
7-3
Xilinx HardWire™ FpgASIC Overview
Customer
Design
Functions
Xilinx
Manufacturing
Functions
Xilinx
Development
Interface
Design Concept
t
Production
FPGA HardWire
Design Considerations
and Verification
,
XACTstep-M1
XACTstep
Development
System
Programmable FPGA
• Design Entry
• Logic Simulation
~
Programmable
FPGAFlow
• Schematic Capture
• Simulation
• Design Libraries
• Automatic Design
Implementation
Xilinx Netlist Format
Programmable FPGA
• Design
Implementation
~
Array and Bitstream
Production
EPROM/PROM
Programming
t
Inventory of
Programmable
Array Devices
Initial Production with
Programmable FPGA
t
High Volume
Production Achieved
---
-~-
--------
~-----------------------------
Purchase Order
HardWire FpgASIC
Design
Review
• DRC Analysis/Report
.LCA(.NGD for M1)
.MBO
.BIT
.RBT
Design File
Final HardWire
FpgASIC
Design Verification
Xilinx Design
Analysis
HardWire FpgASIC Design Verification
NRE Invoiced
System Verification
HardWire FpgASIC
Production
HardWire
FpgASIC Flow
Initial Design
Submittal
I
r.
Prototypes Delivered
HardWire FpgASIC P
rotoptye Approval Signoff
Volume Units
--
Automatic
Test Generation
Custom
Masks Made
I--
Prototypes
Built
-
HardWire FpgASIC
Production Builds
X708
Figure 3: Programmable/HardWire DesignlProduction Interface
7-4
November 4, 1997 (Version 2.0)
~XILINX
Table 1: HardWire Products
Device Family
XC2xxx
XC3xxx
XC4xxx
XC4xxxE/EXlXL
XC4xxxE/EXlXL
XC5xxx
Speed Grade
All
All
-4 and slower
-3 and slower
-3 and faster
All
Features Supported
All
All
No E features
E,EX,XL
E,EX,XL
Non XL
Hardwire FpgASIC
Family
XC2318
XC33xx
XC43xx
XC44xx
XH3xx
XC54xx
Notes
1
1
1
Note 1: Some devices require re-routlng before conversion. Refer to the HardWlre Data Book
Xilinx first reviews the design to determine any items that
could impact the performance of the HardWire device. A
conversion evaluation report is sent to the customer. After
the report has been reviewed and the customer is satisfied,
conversion begins. At the completion of the conversion a
Design Verification Report and DeSign Verification Form
(DVF) are sent to the customer. Once the DVF is completed
the HardWire files are sent to the mask shop for prototyping. If any custom markings are required they must be submitted to Xilinx with the Design Verification Form (DVF).
Prototypes are produced, tested and shipped to the customer for in-system testing. The customer signs the prototype approval form and returns it to Xilinx. Production can
begin.
technology, the memory celis and programmable interconnect logic they control are replaced by metal connections.
All other circuitry in the resulting HardWire device is identical to the corresponding FPGA internal circuitry. The resulting HardWire FpgASIC is a semi-custom device
manufactured to provide a specific function, yet it is completely compatible with the FPGA. This product family is the
fastest and most simple method of converting first generation Xilinx FPGA's. For more details on XC23xx, XC33xx
and XC43xx products please see the Xilinx HardWire Data
Book.
HardWire Product Families
•
Each HardWire product family is developed to support the
features, density and performance of a specific generation
of Xilinx FPGA's.See Table 1 for product family details. For
designs developed using Xilinx XC2xxx, XC3xxx or
XC4xxx (no E features) FPGAs, the XC23xx, XC33xx and
43xx product families provide a fast and simple cost reduction path. For designs developed using Xilinx XC4xxx (E,
EX and XL) and XC5xxx FPGAs, the XC44xx and XC54xx
product families provide the most effective technology, cost
and performance. For customers using fast, dense Xilinx
XC4xxxE, EX and XL or XC5xxx FPGA's the XH3 product
family provides the most efficient and cost effective solution
available. Most HardWire FpgASIC's are available in 3.3v
versions. All HardWire devices support commercial and
industrial temperature ranges.
•
•
Xilinx HardWire Product
Descriptions
The second generation HardWire FpgASIC product family
was developed to match the performance, density and features of Xilinx XC4xxxE, EX,· XL and XC5xxx family of
FPGA's. This HardWire FpgASIC product family supports
all the features of Xilinx second generation FPGAs. This
includes-3 speed grades, Configuration Emulation (CE),
JTAG and Select-RAM. The XC44xx and XC54xx product
family follows a more traditional sea-of-gates approach to
rnapping used CLBs of the FPGA. The used memory cells
and programmable interconnect logic of the FPGA are
mapped into a corresponding area of a traditional gate
XC23xx,XC33xx and XC43xx Product
Description
The initial HardWire product family was developed to
match the performance of Xilinx XC2xxx, XC3xxx and
slower XC4xxx family FPGA's. This family is stili in production today. In standard programmable logic, the functions
and interconnections are determined by configuration data
stored in memory cells. In the first generation HardWire
November 4, 1997 (Version 2.0)
XC23xx, XC33xx and XC43xx Summary
I
Features
•
•
Designed for conversion of XC2xxx, XC3xxx and
XC4xxx (no E features) FPGAs.
Single Mask
Direct Mapped - Turnkey conversion from FPGA
device.
Oncchip scan path test latches.
Fully pin-for-pin compatible.
Benefits
Simple and efficient conversion process.
Very fast conversion completion time.
Conversion success rate over 95%.
Nocustomer developed test vectors needed, 99% fault
coverage.
• Drop-in replacement for Xilinx FPGAs.
•
•
•
XC44xxElEXlXL and XC54xx Product
Description
7-5
Xilinx HardWire™ FpgASIC Overview
mum efficiency. The XH3 architecture implements SelectRAM 3D% more efficiently than generic gate arrays.
array base. The FPGA's unused CLBs are not mapped into
the resulting HardWire device. The HardWire device uses
the smallest base array possible while maintaining the performance and functionality of the corresponding FPGA.
These devices support most 3.3 volt and 5 volt FPGAs. The
feature sizes of the arrays used in the XC44xx and XC54xx
product family (1.D!! through .45!!) are highly competitive
with traditional gate arrays. The wide range of base array
feature sizes available allows Xilinx to provide a HardWire
device with the smallest possible die size. The same guaranteed turnkey conversion methodology is used. XC44xx
and XC54xx devices provide the most cost-effective
method for converting XC4xxxE, XC4xxxEX, XC4xxxXL
and XC52xx FPGA's to a low cost HardWire FpgASIC.
In generic gate array methodologies, features such as Configuration Emulation, JTAG and Select-RAM usually require
additional silicon area. The result is a larger, more expensive die and changes to the FPGA netlist throughout the
conversion process. In many cases implementing Xilinx
Select-RAM in a third party gate array may require substantially more gates than the Xilinx XH3 device. XH3 devices
incorporate these features without silicon overhead or
changes to the nellist.
XC44xx/E/EXlXL and XC54XX Summary
•
XH3 Summary
Features
Features
Designed for conversion of XC4xxxE, EX, XL and
XC5xxx FPGAs.
Only used CLBs are mapped.
Multiple mask, state-of-the-art, gate array process.
On-chip scan path test latches.
Fully pin-for-pin compatible.
Smallest possible die size.
Benefits
•
•
•
•
All Xilinx FPGA features supported, including CE, JTAG
and Select-RAM.
Smallest possible die size used to achieve the lowest
possible cost.
Technology feature size matched to performance
requirements.
No customer developed test vectors needed. Greater
than 95% fault coverage (design dependent).
Drop in replacement for Xilinx FPGAs.
XH3 Product Description
The third generation HardWire FpgASIC product family,
known as XH3, was developed to match the density, performance and features of the fastest, most fully featured Xilinx
XC4xxxEX, XL and XC5xxx family of FPGAs. Initial XH3
products are based on D.5!!, 5-volt process technology, followed by D.35!!, 3.3-volt XH3L technology. XH3 technology
was developed specifically for Xilinx FPGA conversions. It
uses a dense sea-of-gates CMOS gate array technology.
At D.5!! and D.35!!, the process geometry is small enough
that die sizes are driven by pad count and not gate count.
Important features used in Xilinx FPGAs such as Configuration Emulation, JTAG, and Select-RAM are easily implemented in XH3 technology. The control logic for
Configuration Emulation, Power on Reset (POR), Oscillators and full JTAG are built into the XH3 base array. These
features can usually be implemented with no additional silicon overhead. RAM blocks are incorporated with maxi-
7-6
•
•
•
•
Designed for conversion of XC4xxxE, EX, XL and
XC5xxx FPGAs.
Xilinx FPGA features built in to the base array.
Multiple Mask, state-of-the-art D.5!! and D.35!! process
technology.
Pad counts and gate counts available for the densest
FPGA devices.
On chip scan path test latches.
Fully pin for pin compatible.
Package flexibility available.
Benefits
•
All Xilinx FPGA features supported, including CE, JTAG
and Select-RAM.
Patented, turnkey conversion flow.
• Pads and package required determine device used.
• No customer developed test vectors needed. Greater
than 95% fault coverage (design dependent).
• Drop in replacement for Xilinx FPGAs.
• Conversions to smaller packages available.
HardWire Summary
Xilinx Hardwire ASIC products are FPGA specific ASIC's
(FpgASIC's). They are a family of devices ranging from
1.D!! single mask mapped ASIC's to state-of-the-art sea-ofgates D.5!! and D.35!! multi-mask ASIC devices. The HardWire flow is the most simple method of cost reduction for
FPGA based systems. They are developed using the
FPGA's design files. This guarantees the HardWire
FpgASIC will be functionally equivalent to the FPGA. No
customer generated test vectors are required with HardWire. Each HardWire device is tested using a combination
of industry standard and Xilinx patented test methods in a
full scan methodology. The full scan test methodology provides greater than 95% fault coverage depending on the
design. HardWire prototypes can be developed in half the
time of traditional gate array prototypes. HardWire process
technologies, conversion methods and testing procedures
provide the most cost - effective alternative to traditional
gate arrays.
November 4, 1997 (Version 2.D)
High-Reliability and
QML Military Products
I
1
Introduction
2
Development System Products and CORE Solutions Products
3
CPLD Products
4
FPGA Products
5
SPROM Products
6
3V Products
7
HardWire FpgASIC Products
8
High-Reliability and QML Military Products
9
Programming Support
10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support and Services
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors
High-Reliability and
QML Military Products
Table of Contents
High-Reliability and QML Military Products
QML Certification Part of Overall Quality Platform .........................................
Unmatched Hi-Rei Product Offering ....................................................
Committed to the Hi-Rei Market. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Die Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Xilinx Hi-Rei Products ...............................................................
MiI-PRF-38535 QML, Xilinx M Grade and Plastic Commercial Flows ..... . . . . . . . . . . . . . . . . . . . ..
8-1
8-1
8-1
8-1
8-1
8-6
XC4000X Series High-Reliability Field Programmable Gate Arrays
XC4000X Series Features .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Low-Voltage Versions Available .......................................................
Additional XC4000X Series Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8-7
8-7
8-7
8-7
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E High-Reliability Features .....................................................
Xilinx High-Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Switching Characteristics ....................................................
XC4000E Absolute Maximum Ratings ............................................
XC4000E Recommended Operating Conditions ....................................
XC4000E DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Global Buffer Switching Characteristic Guidelines ...........................
XC4000E Horizontal Longline Switching Characteristic Guidelines ......................
XC4000E Wide Decoder Switching Characteristic Guidelines ..........................
XC4000E CLB Switching Characteristic Guidelines ..................................
XC4000E CLB RAM Synchronous (Edge-Triggered) Write Timing ......................
XC4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing ..............
XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines .................
XC4000E CLB Level-Sensitive RAM Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL 110) . . . . . . . . . . . . . . ..
XC4000E lOB Input Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E lOB Output Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Device-Specific Pinout Tables ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pin Locations for XC4005E Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional XC4005E Package Pins ...........................................
8-11
8-11
8-12
8-12
8-12
8-13
8-13
8-14
8-15
8-16
8-19
8-19
8-20
8-21
8-22
8-23
8-25
8-27
8-27
8-27
XC4000E High-Reliability Field Programmable Gate Arrays
Pin Locations for XC401 OE Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional XC4010E Package Pins ...........................................
Pin Locations for XC4013E Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pin Locations for XC4025E Devices. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Example for SMD Part:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Example for Military Tempeture Only Part: .........................................
8-28
8-29
8-29
8-30
8-33
8-33
8-33
- - - - - ------------------
High-Reliability and QML Military
Products
August 25, 1997 (version 1.1)
Xilinx is the world's leading supplier of High-Reliability Programmable Logic Devices (Hi-REL PLDs) to the aerospace, military, defense electronics, and related markets.
These devices are being used in a wide variety of programs, including applications such as electronic warfare,
missile guidance and targeting, RADARISONAR, communications, signal processing, aerospace and avionics.
QML Certification Part of Overall
Quality Platform
Being certified to MIL-PRF-38535 QML (Qualified Manufacturer List), complemented by ISO-9000 Certification,
results in an overall product quality platform that truly
makes Xilinx a world-class supplier of programmable logic.
Designers can confidently design with Xilinx for Hi-Rei systems knowing there is unsurpassed quality and reliability,
and long-term commitment to the Hi-Rei market.
Unmatched Hi-Rei Product Offering
Xilinx offers a wide variety of devices, delivering the fastest
and biggest Hi-Rei devices available. Products up to
62,000 gates are available today, with even higher densities
to come. Xilinx offers multiple product families to allow you
to select the right device to meet your design requirements.
This broad range of devices is available in a wide variety of
speed and package options. Both military temperature and
full MIL-PRF-38535 QMUSMD versions are available as
standard, off-the-shelf products, in through-hole and surface mount packages.
Committed to the Hi-Rei Market
Xilinx understands that you need to be able to count on
your Hi-Rei supplier. Xilinx is committed to our customers
and the Hi-Rei market for the long-term, and we are continually expanding our Hi-Rei support and product portfolio.
The unique capabilities of the Xilinx FPGA solution provide
increased design flexibility, field-upgradability and system
feature integration, while eliminating the NREs, lead-time
and inventory problems of custom logic and gate arrays.
Now more than ever, Xilinx is your Hi-Rei logic solution.
Die Products
Xilinx also provides select products in die form. Working
with our partner, Chip Supply of Orlando, Florida, many
Xilinx products are available in die form, providing all the
advantages of Xilinx FPGAs to designers of hybrids and
multi-chip modules. For more information about Xilinx die
products, contact the nearest Xilinx Sales office or Sales
Representative, or Chip Supply direct at (407)298-7100.
Xilinx Hi-Rei Products
Table 1 summarizes Xilinx high density and high performance product offerings. The -following pages contain a
complete listing of current Xilinx QMUSMD (Standard
Microcircuit Drawings) devices and "B" grade equivalents.
Architectural descriptions for these FPGA products can be
found in Chapter 4. For additional information, contact the
nearest Xilinx Sales Office or Sales Representative.
Table 1: High Density and High Performance Products
Family
XC4000/E/XL
XC3100A
August 25, 1997 (version 1.1)
Devices
XC4003A
XC4005/E
XC4010/E
XC4013/E
XC4025E
XC4036XL
XC4062XL
XC3142A
XC3190A
XC3195A
Features
Highest Density/Most Features Family
3,000-25,000+ gates
Up to 256 user-definable 1I0s
Extensive system features include on-chip user RAM, built-in 1149.1
test support and fast carry logic
Most Advanced Family
62,000 + gates, 3.3 V, 5V-compatible 1/0
Highest Performance Family
2,500-7,500 gates
Up to 144 user-definable II0s
··
·
·
·
·
8-1
I
High-Reliability and QML Military Products
Table 2: Xilinx SMD (Standard Microcircuit Drawing)
XC1700 Products
XC2000 Products'
XC3000 Products
~.
8-2
August 25, 1997 (version 1.1)
~XILINX
I
August 25,1997 (version 1.1)
8-3
High-Reliability and QML Military Products
XC3100A Products
XC4000 Products
8-4
August 25, 1997 (version 1 .1)
~XILINX
--_£
XC4000 Products (continued)
I
August 25, 1997 (version 1.1)
8-5
High-Reliability and QML Military Products
MiI-PRF-38535 QML, Xilinx M Grade and Plastic Commercial Flows
1. Wafer Fab
Operation
Manufacture
QML
8838 Compliant Facility
M Grade (Hermetic)
883B Compliant or noncompliant facilities
Plastic Commercial
Jedec-26 Compliant or noncompliant facilities
2. Assembly and Inspection
Operation
2nd Op Inspection
3rd Optical Inspection
Final visual/mech. Inspection
Mark Permanancy
QML
M Grade (Hermetic)
100% per Method 2010 100% / Commercial standard
100% per Method 2010 100% / Commercial standard
100% per 5004
100% / Commercial standard
see below
Sample / commercial standard
C Grade
100% / Commercial standard
100% / Commercial standard
100% / Commercial standard
Sample / Commercial standard
3. Test
Screen
QML
Temperature Cycling
100% per Method 1010
Constant Acceleration
100% per Method 2001
Fine/Gross Leak Test
100% per Method 1014
Pre Burn-in Electrical Test @ 25°C 100% per part drawing
Burn-in
100% per Method 1015
+25°C Electrical Test
100% per part drawing
PDA
per 5004
+ 125°C Electrical Test
100% per part drawing
-55°C Electrical Test
100% per part drawing
Mark Permanency
per Method 2015
QC Sampling Plan
per 5005; Group A
External Visual Inspection
per Method 2009
QCI Qualification Plan
per 5005; Groups S, C, D
M Grade (Hermetic)
per method 1010
NONE
per Method 1014
NONE
NONE
NONE
N/A
100% per part drawing
NONE
see above
Test @ + 125°C only, LTPD 2
100% / Commercial standard
N/A
C Grade
NONE
NONE
NONE
NONE
NONE
NONE
N/A
+73°C 100% per part drawing
NONE
see above
+70°C for only LTPD 2
100% / Commercial standard
N/A
4. Qualification (Characterization)
QML
Characterization every six months per
MiI-I-38535 Appendix A
8-6
M Grade (Hermetic)
Characterization at product
introduction or major change
C Grade
Characterization at product
introduction or major change
August 25, 1997 (version 1.1)
XC4000X Series High-Reliability
Field Programmable Gate Arrays
November 12, 1997 (Version 1.0)
Advance Product Specification
XC4000X Series Features
Low-Voltage Versions Available
Available in military temperature range (-55°C to
•
•
•
•
•
•
•
•
•
•
•
•
•
•
125°C, T cl
XC4036XL and XC4062XL available in -3 speed
XC4028EX available in -4 speed
System featured Field-Programmable Gate Arrays
- Select-RAMTM memory: on-chip ultra-fast RAM with
- synchronous write option
- dual-port RAM option
Abundant flip-flops
Flexible function generators
- Dedicated high-speed carry logic
Wide edge decoders on each edge
- Hierarchy of interconnect lines
Internal 3-state bus capability
- 8 global low-skew clock or signal distribution
networks
System Performance beyond 50 MHz
Flexible Array Architecture
Low Power Segmented Routing Architecture
Systems-Oriented Features
IEEE 1149.1-compatible boundary scan logic
support
Individually programmable output slew rate
Programmable input pull-up or pull-down resistors
12-mA Sink Current Per XC4000X Output
Configured by Loading Binary File
- Unlimited reprogrammability
Readback Capability
- Program verification
- Internal node observability
Development System runs on most common computer
platforms
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
Highest Capacity - Over 130,000 Usable Gates
Additional Routing Over XC4000E
- almost twice the routing capacity for high-density
designs
Buffered Interconnect for Maximum Speed
New Latch Capability in Configurable Logic Blocks
Improved VersaRing™ I/O Interconnect for Better Fixed
Pinout Flexibility
- Virtually unlimited number of clock signals
Optional Multiplexer or 2-input Function Generator on
Device Outputs
November 12, 1997 (Version 1.0)
•
•
•
•
Low-Voltage Devices Function at 3.0 - 3.6 Volts
XC4000XL: High Performance Low-Voltage Versions of
XC4000EX devices
5V tolerant 1I0s on XC4000XL
0.35~ SRAM process for XC4000XL
Introduction
XC4000X Series high-performance, high-capacity Field
Programmable Gate Arrays (FPGAs) provide the benefits
of custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs combine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased
speed, abundant routing resources, and new, sophisticated
software to achieve fully automated implementation of
complex, high-density, high-performance designs.
Refer to the complete Commercial XC4000E and XC4000X
Series Field Programmable Gate Arrays Data Sheet for
more information on device architecture and timing.
8-7
I
XC4000X Series High-Reliability Field Programmable Gate Arrays
Table 1 : XC4000X Series High Reliability Field Programmable Gate Arrays
Logic
Cells
Device
XC4028EX 2432
XC4036XL 3078
XC4062XL 5472
Max
Max_RAM
Typical
Logic
Gates
Bits
Gate Range
CLB
(No RAM) (No Logic) (Logic and RAM)" Matrix
28,000
32,768
18,000 - 50,000
32 x 32
36,000
41,472
22,000 - 65,000
36 x 36
62,000
73,728
40,000 - 130,000 48 x 48
Total
CLBs
1,024
1,296
2,304
Number
of
Max.
Flip-Flops User 1/0
Packages
2,560
256
PG299, CB228
3,168
288
PG411, CB228
5,376
384
PG475, CB228
8/15/97
• Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
Ordering Information
Example:
XC4062XL-3PG475M
-,T
Device Type _ _ _ _ _ _
1 __
I
TL...._ _ Temperature Range
M = Military (Tc = -55 to + 125 DC)
Speed Grade
-4
-3
Number of Pins
Package Type
CB = Top Brazed Ceramic Quad Flat Pack
PG = Ceramic Pin Grid Array
8-8
November 12, 1997 (Version 1.0)
---~-~-~-
XC4000E High-Reliability Series
Table of Contents
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E High-Reliability Features .....................................................
Xilinx High-Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Absolute Maximum Ratings ................................. , ..........
XC4000E Recommended Operating Conditions .......... . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Global Buffer Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Horizontal Longline Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . ..
XC4000E Wide Decoder Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E CLB Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E CLB RAM Synchronous (Edge-Triggered) Write Timing ......................
XC4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing ..............
XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines. . . . . . . . . . . . . . . ..
XC4000E CLB Level-Sensitive RAM Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O) . . . . . . . . . . . . . . ..
XC4000E lOB Input Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E lOB Output Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Device-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pin Locations for XC4005E Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional XC4005E Package Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pin Locations for XC401 OE Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional XC4010E Package Pins ...........................................
Pin Locations for XC4013E Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pin Locations for XC4025E Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Example for SMD Part: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Example for Military Tempeture Only Part:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8-11
8-11
8-12
8-12
8-12
8-13
8-13
8-14
8-15
8-16
8-19
8-19
8-20
8-21
8-22
8-23
8-25
8-27
8-27
8-27
8-28
8-29
8-29
8-30
8-33
8-33
8-33
I
8-9
XC4000E High-Reliability Series Table of Contents
8-10
XC4000E High-Reliability
Field Programmable Gate Arrays
November 21, 1997 (Version 1.3)
Product Specification
XC4000E High-Reliability Features
•
•
•
•
•
•
System featured Field-Programmable Gate Arrays
- Select-RAMTM memory: on-chip ultra-fast RAM with
- synchronous write option
- dual-port RAM option
Abundant flip-flops
- Flexible function generators
Dedicated high-speed carry logic
Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
8 global low-skew clock or signal distribution
networks
System Performance beyond 60 MHz
Flexible Array Architecture
Low Power Segmented Routing Architecture
Systems-Oriented Features
IEEE 1149.1.-compatible boundary scan logic
support
Individually programmable output slew rate
Programmable input pull-up or pull-down resistors
- 12-mA sink current per XC4000E output
Configured by Loading Binary File
- Unlimited reprogrammability
Readback Capability
•
•
•
- Program verification
- Internal node observability
Backward Compatible with XC4000 Devices
Development System runs on most common computer
platforms
Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive deSign editor for design optimization
Available in class Q fully compliant QML and Military
temperature range only
Certified to MIL-PRF-38535, appendix A QML
(Qualified Manufacturers Listing)
Xilinx High-Reliability
XC4000E family is supplied under the following standard
microcircuit drawings (SMDs):
XC4005E 5962-97522
XC4010E 5962-97523
XC4013E 5962-97524
XC4025E 5962-97525
For more information contact DSeC (Defense Supply Center Columbus) Columbus, Ohio.
Table 1: XC4000E Field Programmable Gate Arrays
Max.
Logic
Max. RAM
Bits
Gates
(No RAM) (No Logic)
5,000
6,272
Typical
Gate Range
(Logic and
RAM)'
3,000 - 9,000
XC4010E
10,000
12,800
7,000 - 20,000 20 x 20
XC4013E
13,000
18,432
XC4025E
25,000
32,768
Device
XC4005E
*
10,000 30,000
15,000 45,000
Total
CLBs
196
Number
of
Flip-Flops
616
Max.
Decode
Inputs
per side
42
Max.
User 1/0
112
400
1,120
60
160
PG191,
CB196
24 x 24
576
1,536
72
192
PG223,
CB228
32 x 32
1,024
2,560
96
256
PG299,
CB228
CLB
Matrix
14 x 14
Packages
PG156,
CB164
Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
November 21, 1997 (Version 1.3)
8-11
I
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E Switching Characteristics
XC4000E Absolute Maximum Ratings
Symbol
Vee
VIN
VTS
TSTG
TSOL
TJ
Note 1:
Note 2:
Description
Supply voltage relative to GND
Input voltage relative to GND (Note 1)
Voltage applied to 3-state output (Note 1)
Storage temperature (ambient)
Maximum soldering temperature (10 s@ 1/16 in. = 1.5 mm)
Junction temperature
ICeramic packages
Value
-0.5 to +7.0
-0.5 to Vee +0.5
-0.5 to Vee +0.5
-65 to +150
+260
+150
Units
V
V
V
°C
°C
°C
Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is
easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this
over- or undershoot lasts less than 20 ns.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
XC4000E Recommended Operating Conditions
Symbol
Vee
V IH
VIL
TIN
Note:
8-12
Description
Supply voltage relative to GND, Te = -55°C to + 125°C
High-level input voltage
Low-level input voltage
Input signal transition time
ITTL inputs
ITTL inputs
Min
4.5
2.0
0
Max
5.5
Vee
0.8
250
Units
V
V
V
ns
At case temperatures above those listed as Recommended Operating Conditions, all delay parameters increase by 0.35%
per °e.
Input and output Measurement thresholds are: 1.5V for TTL and 2.5V for CMOS.
All specifications are subject to change without notice.
November 21, 1997 (Version 1.3)
~XILINX
XC4000E DC Characteristics Over Operating Conditions
Description
Symbol
VOH
VOL
leeo
IL
Min
Max
ITTL outputs
Low-level output voltage @ IOL = 12.0mA, Vee min (Note 1) ITTL outputs
Quiescent FPGA supply current (Note 2)
2.4
Input or output leakage current
-10
+10
16
High-level output voltage @ IOH = -4.0mA, Vee min
Units
V
0.4
V
mA
SO
IRIN"
Pad pull-up (when selected) @ VIN = OV (sample tested)
-0.02
-0.2S
J..lA
pF
mA
IRLL'
Horizontal Longline pull-up (when selected) @ logic Low
0.2
2.S
mA
CIN
Note 1:
Note 2:
Input capacitance (sample tested)
With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins.
With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA
configured with the development system Tie option.
Characterized Only.
XC4000E Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38S1 0/60S. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible lOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation nellist. These path delays, provided as a guideline, have been extracted from the static
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature)
Description
Symbol
Speed Grade
Device
From pad through
Primary buffer,
to any clock K
TpG
XC400SE
XC4010E
XC4013E
XC402SE
From pad through
Secondary buffer,
to any clock K
TSG
XC400SE
XC4010E
XC4013E
XC402SE
November 21, 1997 (Version 1.3)
-4
Max
Units
7.0
11.0
11.S
12.S
7.5
11.S
12.0
13.0
ns
ns
ns
ns
ns
ns
ns
ns
8-13
II
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E Horizontal Longline Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
The following guidelines reflect worst-case values over the recommended operating conditions.
Description
reUF driving a Horizontal Longline (LL):
Symbol
"""~"~'",,,,;;;',;'
Speed Grade
Device
·4
Max
Units
:r'::!:II:i::!i!!:iii:i:i;i:
t~'::;::':;i:i::::,
I going High or Low to LL going High or Low, while T is Low.
Buffer is constantly active. (Note1)
T 101
XC400SE
XC4010E
XC4013E
XC402SE
S.O
8.0
9.0
11.0
ns
ns
ns
ns
I going Low to LL going from resistive pull-up High to active Low.
TBUF configured as open-drain. (Note1)
T 102
XC400SE
XC4010E
XC4013E
XC402SE
6.0
10.S
11.0
12.0
ns
ns
ns
ns
T going Low to LL going from resistive pull-up or floating High to active Low.
TBUF configured as open-drain or active buffer with I = Low.
(Note1)
TON
XC400SE
XC4010E
XC4013E
XC402SE
7.0
8.S
8.7
11.0
ns
ns
ns
ns
T going High to TBUF going inactive, not driving LL
TOFF
XC400SE
XC4010E
XC4013E
XC402SE
1.8
3.0
3.S
4.0
ns
ns
ns
ns
T going High to LL going from Low to High, pulled up by a single resistor.
(Note 1)
Tpus
XC400SE
XC4010E
XC4013E
XC402SE
23.0
29.0
32.0
42.0
ns
ns
ns
ns
T going High to LL going from Low to High, pulled up by two resistors.
(Note1 )
TpUF
XC400SE
XC4010E
XC4013E
XC402SE
10.0
13.S
1S.0
18.0
ns
ns
ns
ns
Note 1:
8-14
These values include a minimum load. Use the static timing analyzer to determine the delay for each destination.
November 21 , 1997 (Version 1.3)
~XILINX
XC4000E Wide Decoder Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605, All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in. the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
The following guidelines reflect worst-case values over the recommended operating conditions.
Description
Symbol
Full length, both pull-ups,
inputs from lOB I-pins
TWAF
Full length, both pull-ups,
inputs from internal logic
TWAFL
Half length, one pull-up,
inputs from lOB I-pins
TWAO
Half length, one pull-up,
inputs from internal logic
TWAOL
Speed Grade
Device
XC4005E
XC4010E
XC4013E
XC4025E
XC4005E
XC4010E
XC4013E
XC4025E
XC4005E
XC4010E
XC4013E
XC4025E
XC4005E
XC4010E
XC4013E
XC4025E
-4
Max
Units
9.5
15.0
16.0
1M
12.5
18.0
19.0
21.0
10.5
16.0
17.0
19,0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12.5
18.0
19.0
21.0
II
Notes: These delays are specified from the decoder input to the decoder output.
. Fewer than the specified number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption
but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used.
November 21, 1997 (Version 1.3)
8-15
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
FIG inputs to XN outputs
FIG inputs via H to XN outputs
C inputs via H to XN outputs
FIG inputs
FIG inputs via H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
C inputs via EC
Cin
via SIR,
8-16
TICK
TIHCK
THH1CK
THH2CK
TDICK
TECCK
T
6.1
5.0
4.8
3.0
4.0
4.2
ns
ns
ns
ns
ns
ns
November 21, 1997 (Version 1.3)
l::XIUNX
XC4000E CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the static timing analyzer and used in the simulator.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
ns
ns
ns
ns
1
55.0
70.0
112.0
Delay from Global Set/Reset net to Q
~ovember 21,
1997 (Version 1;3)
TMRQ
23.0
60.0
77.0
134.0
ns
ns
ns
ns
ns
ns
ns
8-17
I
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100% functionally tested.
Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more
precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation nellis!. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature). Values apply to all XC4000E devices unless otherwise noted.
Single Port RAM
Speed Grade
-4
Write nn.. r~'lln,n
ns
ns
Address write cycle time (clock K period)
16x2
32xl
Twcs
T WCTS
15.0
15.0
Clock K pulse width (active edge)
16x2
32xl
TwPS
T WPTS
7.5
7.5
Address setup time before clock K
16x2
32xl
TASS
T ASTS
2.8
2.8
ns
ns
Address hold time after clock K
16x2
32xl
T AHS
TAHTS
0
0
ns
ns
DIN setup time before clock K
16x2
32xl
T DSS
T DSTS
3.5
2.5
ns
ns
DIN hold time after clock K
16x2
32xl
T DHS
0
0
ns
ns
16x2
32xl
Twss
2.2
2.2
ns
ns
16x2
32xl
T WHS
0
0
ns
ns
16x2
32xl
Twos
T WOTS
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
Notes:
TDHTS
TWSTS
T WHTS
1 ms
1 ms
10.3
11.6
ns
ns
ns
ns
Timing for the 16xl RAM option is identical to 16x2 RAM timing.
Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Dual-Port RAM
Speed Grade
-4
Write Operation
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
Note:
8-18
16xl
16xl
16xl
16xl
16xl
16xl
16xl
16xl
16xl
TWCDS
T WPDS
TASDS
T AHDS
T DSDS
TDHDS
T WSDS
T WHDS
T WODS
15.0
7.5
2.8
0
2.2
0
2.2
0.3
1 ms
10.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Applicable Read timing specifications are identical to Level-Sensitive Read timing.
November 21, 1997 (Version 1.3)
~XILINX
XC4000E CLB RAM Synchronous (Edge-Triggered) Write Timing
WCLK(K)
- - - - - • - - - - • - - - - - - - - - - -, r'--"';';';";:'--"""""I
-----------'1'
TWSS
TWHS
WE
DATA IN
ADDRESS
DATA OUT
X6461
XC4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing
WCLK(K)
II
- - - - - -- - - - - - -- -- - - - - - -,1,------"'\1
TWSDS
TWHDS
T DSDS
TDHDS
WE
DATA IN
ADDRESS
DATA OUT
X6474
November 21, 1997 (Version 1.3)
8-19
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/S05. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netiist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000E devices unless otherwise noted.
Speed Grade
Description
-4
Symbol
Write Operation
Address write cycle time
1Sx2
32x1
Twc
TWCT
8.0
8.0
ns
ns
Write Enable pulse width (High)
1Sx2
32x1
Twp
TWPT
4.0
4.0
ns
ns
Address setup time before WE
1Sx2
32x1
TAS
TAST
2.0
2.0
ns
ns
Address hold time after end of WE
1Sx2
32x1
TAH
TAHT
2.5
2.0
ns
ns
DIN setup time before end of WE
1Sx2
32x1
Tos
TOST
4.0
5.0
ns
ns
DIN hold time after end of WE
1Sx2
32x1
OH
TOHT
2.0
2.0
ns
ns
Address read cycle time
1Sx2
32x1
TRC
T RCT
Data valid after address change
(no Write Enable)
1Sx2
32x1
T ILO
T IHO
8.0
Read Operation
Read Operation, Clocking Data into Flip-Flop
Address setup time before clock K
TICK
T IHCK
Read During Write
Data valid after WE goes active (DIN stable before WE)
1Sx2
32x1
Two
TWOT
Data valid after DIN
(DIN changes during WE)
1Sx2
32x1
Too
TOOT
1Sx2
32x1
TWCK
TWCKT
9.S
ns
ns
1Sx2
32x1
TOCK
TOCKT
7.0
8.0
ns
ns
Read During Write, Clocking Data Into Flip-Flop
WE setup time before clockK
Data setup time before clock K
Note:
8-20
Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
November 21, 1997 (Version 1.3)
.1:XILINX
XC4000E CLB Level-Sensitive RAM Timing Characteristics
ADDRESS
WRITE
WRITE ENABLE
DATA IN
READ WITHOUT WRITE
X,YOUTPUTS
VALID
READ, CLOCKING DATA INTO FLlP·FLOP
---t
CLOCK
i""1"<--~-- TICK -~---l·~I"·- TCH
r-------~-----------------
XQ, YQ OUTPUTS
READ DURING WRITE
~--------TWp--------~
I
WRITE ENABLE
DATA IN
(stable during WE)
X, YOUTPUTS
DATA IN
(ch""ging dunng WE)
X, YOUTPUTS
RI:AD DURING WRITE, CLOCKING DATA INTO FLlP·FLOP
WRITE ENABLE
. '
~~~.=======~TW~P~=======~·l
;I:.
TWCK -----<"I
I\~~__
DATA IN
CLOCK
XQ, YQ OUTPUTS
X2640
November 21, 1997 (Versiont ,3)
8-.21
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL 1/0)
Testing of switching parameters is modeled after testing methods specified by MIL-M-38S10/60S. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted.
Description
Global Clock to Output
(fast) using OFF
Symbol
TICKOF
~
Global Clock-to-Output Delay
(Max)
Speed Grade
Device
XC4005E
XC4010E
XC4013E
XC4025E
14.0
16.0
16.5
17.0
ns
ns
ns
ns
XC4005E
XC4010E
XC4013E
XC4025E
18.0
20.0
20.5
21.0
ns
ns
ns
ns
XC4005E
XC4010E
XC4013E
XC4025E
2.0
1.9
1.6
1.5
ns
ns
ns
ns
XC4005E
XC4010E
XC4013E
XC4025E
4.6
6.0
7.0
8.0
ns
ns
ns
ns
XC4005E
XC4010E
XC4013E
XC4025E
8.5
8.5
8.5
9.5
ns
ns
ns
ns
ns
ns
ns
ns
XC4005E
XC4010E
XC4013E
XC4025E
0
0
0
ns
ns
ns
ns
-4
Units
:
X3202
Global Clock to Output
(slew-limited) using OFF
T1CKO
~
Global Clock.-to·Qulpui Delay
(Max)
•
><3202
Input Setup Time, using IFF
(no delay)
Input
set-UKl
Hold
Time
TpSUF
:~;[]
(Min)
T'FF
PG
~,
Input Hold Time, using IFF
(no delay)
Input
~
Set-uK 1
Hold
TIme
TpHF
T
PG
(Min)
',FF
~,
Input Setup Time, using IFF
(with delay)
Input
~
Sot-UK 1
Hold
lime
Tpsu
(Min)
T'FF
PG
~,
Input Hold Time, using IFF
(with, delay)
Input
Hold
Time
(Min)
b
T'FF
OFF = Output Flip-Flop
8-22
,"
~
sot. UK 1
TpH
PG
""',
IFF = Input Flip-Flop or Latch
November 21, 1997 (Version 1.3)
~XILINX
XC4000E lOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted.
-4
Description
Propagation Delays (TTL Inputs)
Pad to 11, 12
Pad to 11, 12 via transparent latch, no delay
with delay
TplD
TpLi
TpDLI
All devices
All devices
XC4005E
XC4010E
XC4013E
XC4025E
3.0
6.0
12.0
12.2
12.6
15.0
ns
ns
ns
ns
ns
ns
Propagation Delays
Clock (IK) to 11, 12 (flip-flop)
Clock (IK) to 11, 12 (latch enable, active Low)
Hold Times (Note 1)
Pad to Clock (IK), no delay
with delay
Note 1:
Note 2:
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pullup (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
November 21, 1997 (Version 1.3)
8-23
II
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E lOB Input Switching Characteristic Guidelines (continued)
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation nellis!. These path
delays, provided as a guideline, have been extracted from the static timing analyzt;lr repor!. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
no delay
with delay
TplCK
TplCKD
All devices
XC4005E
XC4010E
XC4013E
XC4025E
4.0
10.9
11.3
11.8
14.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
TECIK
TECIKD
All devices
XC4005E
XC4010E
XC4013E
XC4025E
3.5
10.4
10.7
11.1
14.0
ns
ns
ns
ns
ns
GSR inactive to first active Clock (IK) edge
TMRW
TRPO
Note 1:
Note 2:
Note 3:
8-24
XC4010E
XC4013E
XC4025E
XC4005E
XC4010E
XC4013E
XC4025E
XC4005E
XC4010E
XC4013E
XC4025E
1
21.0
23.0
29.0
13.0
55.0
70.0
112.0
15.0
20.3
22.0
28.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pullup (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Timing is based on the XC4005E. For other devices see the static timing analyzer.
November 21, 1997 (Version 1.3)
~XILINX
XC4000E lOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
Description
Propagation Delays (TTL Output Levels)
Clock (OK) to Pad, fast
slew-rate limited
Output (0) to Pad, fast
slew-rate limited
3-state to Pad hi-Z
(slew-rate independent)
3-state to Pad active
and valid, fast
slew-rate limited
Note 1:
Note 2:
TOKPOF
To KPOS
T OPF
Tops
TTSHZ
11.5
8.0
12.0
10.0
ns
ns
ns
ns
ns
TTSONF
TTSONS
10.0
13.7
ns
ns
Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground
bounce, see the "Additional XC4000 Data" section of the Programmable Logic Data Book.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pullup (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
I
November 21, 1997 (Version 1.3)
8-25
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E lOB Output Switching Characteristic Guidelines (continued)
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless
otherwise noted. Values apply to all XC4000E devices unless otherwise noted.
Description
Setup and Hold
Output (0) to clock (OK) setup time
Output (0) to clock (OK) hold time
Clock
Note 2:
Note 3:
8-26
P~:i i: ;!':~!1:;i!! ~~~:il::i::;:::::;i:
i
OKO
I::; ,;:::ii:"i!:i':, i::tl:;;:;,:d':": ,
Clock High
Clock Low
Note 1:
Symbol
TCH
TCl
Speed Grade
Device
::::;!:'
-4
Min
Max
Units
:,:!i'~::;:,i!i
;:j~:j'j;'::\i:~::;:2i~~::
5.0
0
ns
ns
'i"'!!::::;,:j:!:~;l!!i!i;;~;; ~j::'i:il::;';i::;:l;:;:::il:::,i;ii :,:~:ii:i!t"i,
4.5
4.5
ns
ns
',i""i,'
Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
riselfall times are approximately two times longer than fast output riselfall times. For the effect of capacitive loads on ground
bounce, see the "Additional XC4000 Data" section of the Programmable Logic Data Book.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pullup (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Timing is based on the XC4005E. For other devices see the static timing analyzer.
November 21 , 1997 (VerSion 1.3)
~XILINX
Device-Specific Pinout Tables
Pin Locations for XC4005E Devices
XC4005E
Pad Name
VCC
I/O (A8)
I/O (A9)
I/O
I/O
I/O (Al0)
I/O (All)
I/O
I/O
GNO
I/O (A12)
I/O (A13)
I/O
I/O
I/O (A14)
I/O, SGCKl (A15)
VCC
GNO
I/O, PGCKl (A16)
I/O (A17)
I/O
I/O
I/O, TOI
I/O, TCK
GNO
I/O
I/O
I/O, TMS
I/O
I/O
I/O
I/O
I/O
GNO
VCC
110
110
I/O
I/O
I/O
I/O
110
I/O
GNO
110
I/O
I/O
I/O
I/O
110, SGCK2
O(Ml)
GNO
I (MO)
VCC
I (M2)
I/O, PGCK2
PG
156t
H3
Hl
Gl
G2
G3
Fl
F2
El
E2
F3
E3
Cl
C2
03
Bl
B2
C3
C4
B3
Al
A2
C5
B4
A3
C6
B5
B6
A5
C7
B7
A6
A7
A8
C8
B8
C9
B9
A9
Bl0
Cl0
Al0
All
Bll
Cll
B12
A13
A14
C12
B13
814
A15
C13
A16
C14
815
816
CB
164
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
P157
P158
P160
P161
P162
P163
P164
Pl
P2
P3
P4
P5
P7
P8
Pl0
Pll
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P26
P27
P28
P29
P30
P32
P33
P34
P35
P37
P38
P39
P40
P41
P42
P43
P44
November 21, 1997 (Version 1.3)
Bndry
Scan
44
47
50
53
56
59
62
65
68
71
74
77
80
83
86
89
92
95
98
101
104
107
110
113
116
119
122
125
128
131
134
137
140
143
146
149
152
155
158
161
164
167
170
173
174
175
XC4005E
Pad Name
I/O (HOC)
I/O
I/O
I/O
I/O (LOC)
GNO
I/O
110
I/O
I/O
I/O
I/O
110
110 (INIT)
VCC
GNO
110
110
I/O
I/O
I/O
I/O
I/O
110
GNO
I/O
I/O
I/O
I/O
I/O
1/0,SGCK3
GNO
OONE
VCC
PROGRAI\il
1/0(07)
110, PGCK3
I/O
I/O
1/0(06)
I/O
GNO
110
110
110(05)
110 (CSO)
110
I/O
110(04)
110
VCC
GNO
1/0(03)
I/O (RS)
I/O
I/O
PG
156t
014
C15
015
E14
C16
F14
F15
E16
F16
G14
G15
G16
H16
H1S
H14
J14
J1S
J16
K16
K1S
K14
L16
M16
L15
L14
P16
M14
N15
P15
N14
R16
P14
R15
P13
R14
T16
T1S
R13
P12
T14
T13
Pll
Rll
Tll
Tl0
Pl0
Rl0
T9
R9
P9
R8
P8
T8
T7
T6
R7
CB
164
P45
P46
P48
P49
P50
P53
P54
P55
P56
P57
P58
PS9
P60
P61
P62
P63
P64
P6S
P66
P67
P68
P69
P70
P71
P72
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P8S
P86
P87
--_ P89
.. _P90
P91
P94
P9S
P96
P97
P98
P99
Pl00
Pl0l
Pl02
Pl03
Pl04
Pl05
Pl06
Pl07
Pl08
Bndry
Scan
178
181
184
187
190
193
196
199
202
205
208
211
214
217
220
223
226
229
232
235
238
241
244
247
250
253
256
259
262
265
268
271
274
277
280
283
286
289
292
295
298
301
304
307
310
XC4005E
Pad Name
1/0(02)
I/O
I/O
I/O
GNO
1/0(01)
I/O (RCLK,
ROY/BUSY)
I/O
I/O
I/O (00, OIN)
I/O, SGCK4
(OOUT)
CCLK
VCC
0, TOO
GNO
I/O (AO, WS)
I/O, PGCK4 (Al)
I/O
I/O
110 (CS1,A2)
110 (A3)
GND
I/O
I/O
1/0(A4)
I/O (A5)
110
I/O
I/O (A6)
110 (A7)
GNO
8/13/97
PG
156t
P7
T5
R6
T4
P6
T3
P5
CB
164
Pl09
Pll0
Plll
Pl12
Pl13
Pl15
Pl16
Bndry
Scan
313
316
319
322
R4
R3
P4
T2
Pl17
Pl19
P120
P121
331
334
337
340
R2
P3
Tl
N3
Rl
P2
N2
M3
Pl
Nl
L3
L2
Ll
K3
K2
Kl
Jl
J2
J3
H2
P122
P123
P124
P125
P126
P127
P128
P130
P131
P132
P135
P136
P137
P138
P139
P140
P141
P142
P143
P144
325
328
0
2
5
8
11
14
17
20
23
26
29
32
35
38
41
Additional XC4005E Package
Pins
PG156
A4
016
M15
T12
8/14/97
N.C. Pins
A12
01
E15
M1
N16
R5
02
M2
R12
N.C. Pins
P25
P9
P47
P51
P74
P88
Pl18
P114
P134
P155
P31
P52
P92
P129
P156
CB164
P6
P36
P73
P93
P133
P159
8/14/97
8-27
I
XC4000E High-Reliability Field Programmable Gate Arrays
Pin Locations for XC4010E Devices
XC4010E
Pad Name
PG
191t
CB
196
VGC
J4
P183
1/0 (A8)
1/0 (A9)
1/0(19)
1/0(18)
1/0
1/0
1/0 (A10)
1/0 (A11)
1/0
J3
J2
P184
P185
62
65
J1
H1
P186
P187
68
H2
P188
H3
G1
P189
P190
G2
P191
P192
110
F1
E1
GND
G3
P194
1/0
1/0
1/0
F2
D1
P195
P196
C1
E2
P197
110
1/0 (A12)
1/0 (A13)
1/0
1/0
1/0 (A14)
1/0, SGCK1 (A15)
VCC
GND
1/0, PGCK1 (A16)
1/0 (A17)
1/0
1/0
1/0, TOI
1/0, TCK
1/0
1/0
1/0
1/0
GND
1/0
1/0
1/0, TMS
1/0
1/0
1/0
1/0
1/0
1/0
1/0
F3
D2
B1
P193
XC4010E
Pad Name
Bndry
Scan
71
74
77
80
83
86
89
110
110
1/0
1/0
1/0
1/0,SGGK2
0(M1)
P51
246
P52
247
P53
250
C17
P55
P56
253
256
P198
P199
95
98
101
P57
259
104
110 (LDC)
E17
P58
262
P200
P201
107
110
1/0
F16
P59
110
C18
D18
P60
P61
265
268
F17
G16
P62
P63
274
E18
F18
P64
110
P65
P66
P67
110
1/0
P204
P205
119
GND
C3
C4
P2
122
110
G17
P3
125
110
1/0
1/0
1/0
G18
H16
1/0
P1
K17
110
K18
L18
P77
P78
152
P15
P16
155
158
A6
P17
161
G8
A7
P18
164
167
1/0
1/0
1/0
1/0
1/0
GND
GND
VCC
D9
D10
P24
1/0
G10
B10
B13
A14
A15
C13
P25
P26
182
P27
P28
185
188
P29
191
P30
P31
194
197
P32
P33
P34
200
203
206
P35
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0, SGGK3
301
304
P75
307
310
313
406
T11
P117
P118
U11
V11
P119
1/0
1/0
1/0
1/0
1/0 (D1)
1/0 (RCLK,
V9
V8
P126
P127
436
439
442
V7
P131
445
U7
P132
P133
P134
448
454
457
460
U5
T6
V3
P139
P140
466
V2
P141
469
472
U4
P142
475
T5
P143
478
U3
T4
P144
P145
481
484
CCLK
VCC
V1
R4
P146
RDY/lffiSY')
319
322
1/0
1/0
1/0 (DO, DIN)
M17
P83
328
N18
P18
P84
P85
331
334
M16
N17
PB6
PB7
337
0, TOO
U2
P148
R18
PBB
340
GND
T1B
P89
P90
343
346
R3
T3
P149
P150
U1
P151
P16
451
P137
P138
316
V4
P135
P136
325
U18
T16
433
P129
P130
P81
P82
R17
427
430
U8
T8
L16
M18
T17
421
P128
P79
P80
P17
N16
409
412
415
P124
P125
L17
110, SGCK4
(DOUT)
463
P147
0
P91
349
1/0 (AO,WS)
1/0, PGCK4 (A1)
1/0
P3
P153
P92
P93
352
110
R2
P154
11
355
1/0 (GS1, A2)
P94
P95
358
361
110 (A3)
T2
N3
P155
P156
14
17
P2
P157
20
364
T1
P158
P159
P160
23
209
GND
DONE
R16
U17
P36
P37
R15
212
VCG
PROGRAM
P96
P97
P98
P99
V1B
P100
P38
P39
215
218
T15
U16
P101
P102
367
370
P40
221
T14
P104
373
1/0 (D7)
1/0, PGCK3
1/0
403
P116
U6
T7
V5
P76
P14
P115
110
GND
K16
A5
B7
U12
V12
V6
110
110
GND
397
400
110
P74
149
P113
P114
1/0
1/0
1/0 (D2)
1/0
P73
P12
P13
P112
U13
V13
283
286
J15
K15
B6
C7
A4
T12
1/0
1/0
1/0 (D5)
I/O(CSO)
1/0
1/0
1/0
1/0
1/0 (D4)
1/0
110
J16
143
146
GND
391
394
280
1/0 (iNIT)
P10
P11
P111
277
VCC
A3
B5
V14
T9
U9
110
140
P109
P110
1/0 (D3)
1/0 (RS)
1/0
271
P71
P72
P9
U14
V15
424
J18
J17
C6
382
3B5
388
P123
295
298
110
P107
P108
R10
R9
P70
134
137
V16
T13
376
379
VCC
GND
H18
P7
P8
P106
P122
289
A2
B4
U15
V17
Bndry
Scan
T10
292
131
1/0 (D6)
1/0
1/0
1/0
1/0
1/0
CB
196
P105
418
P68
128
110
PG
191t
P120
P121
P69
P4
P6
XC4010E
Pad Name
V10
U10
H17
B3
C5
179
8-28
D17
B18
116
P23
1/0
1/0
1/0
1/0
P48
E16
92
113
A13
C12
242
C16
B17
P202
A12
B12
239
I (M2)
P203
G11
B11
236
P46
P47
1/0, PGCK2
1/0 (HDC)
1/0
1/0
1/0
E3
A9
P45
245
C2
B2
D3
D4
A10
A11
230
233
P49
P50
C9
GND
B16
P43
P44
227
A18
D16
110
1/0
P41
P42
I (MO)
VGG
170
173
176
110
B14
A16
B15
C14
A17
Bndry
Scan
224
GND
B8
A8
B9
1/0
1/0
1/0
1/0
1/0
1/0
CB
196
C15
D15
P19
P20
P21
P22
110
PG
191t
1/0
1/0
1/0
110
GND
1/0
1/0
I/O(M)
1/0 (A5)
1/0
R1
N2
M3
P1
P161
P162
2
5
8
26
29
32
N1
M2
P163
P164
M1
P165
38
41
L3
P166
44
35
November 21, 1997 (Version 1.3)
~XILINX
XC4010E
Pad Name
PG
191t
L2
Ll
Kl
K2
K3
K4
1/0
1/0
1/0
1/0 (A6)
1/0 (A7)
GND
Bndry
Scan
47
50
53
56
59
CB
196
P167
P168
P169
P170
P171
P172
Additional XC4010E Package
Pins
8/14/97
Pin Locations for XC4013E Devices
XC4013E
Pad Name
VCC
1/0 (A8)
1/0 (A9)
I/O
PG
223t
J4
J3
J2
Jl
Hl
H2
H3
Gl
G2
1/0
1/0
1/0
1/0 (Al0)
1/0 (All)
VCC
1/0
1/0
1/0
1/0
H4
G4
GND
G3
F2
Fl
El
1/0
1/0
1/0
1/0
1/0 (A12)
1/0 (A13)
Dl
Cl
E2
F3
D2
F4
I/O
1/0
1/0
1/0
E4
61
I/O (A14)
I/O, SGCK1(A15)
E3
C2
62
VCC
GND
D3
D4
1/0, PGCK1(A16)
1/0 (A17)
1/0
I/O
1/0, TDI
1/0, TCK
1/0
1/0
1/0
1/0
1/0
1/0
-
C3
- C4
63
C5
A2
64
C6
A3
65
66
D5
GND
D6
C7
I/O
A4
1/0
1/0, TMS
1/0
1/0
1/0
1/0
1/0
1/0
A5
67
A6
D7
D8
C8
A7
68
CB
228
P201
P202
P203
P204
P205
P206
P207
P208
P209
P210
P211
P212
P213
P214
P215
P216
P217
P218
P219
P220
P221
P222
P223
P224
P225
P226
P227
P228
Pl
P2
P3
P4
P5
P6
P7
P8
P9
Pl0
Pll
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
XC4013E
Pad Name
Bndry
Scan
1/0
74
77
80
83
86
89
92
95
98
101
104
107
1/0
GND
VCC
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
VCC
I/O
Bll
110
I/O
113
116
119
1/0
1/0
A12
612
122
125
128
131
134
137
140
143
GND
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
152
I/O
1/0,SGCK2
O(Ml)
155
158
GND
I (MO)
161
164
VCC
I (M2)
167
170
173
1/0, PGCK2
1/0 (HDC)
1/0
1/0
1/0
1/0 (LDC)
1/0
1/0
1/0
1/0
1/0
1/0
146
-~
November 21, 1997 (Version 1,3)
I/O
PG
223t
AB
69
C9
D9
Dl0
Cl0
610
A9
Al0
All
Cll
Dll
D12
176
179
182
185
188
191
194
197
200
GND
203
206
1/0
1/0
A13
C12
D13
D14
B13
A14
A15
C13
614
A16
615
C14
A17
616
C15
D15
A18
D16
C16
B17
E16
C17
D17
618
E17
F16
C18
D18
F17
E15
F15
G16
E18
F18
CB
228
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
PS8
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
Bndry
Scan
209
212
215
218
221
224
227
230
233
236
239
-
242
245
248
251
254
257
260
263
266
269
272
275
278
281
284
287
290
293
294
295
298
301
304
307
310
313
316
319
322
325
328
331
334
XC4013E
Pad Name
1/0
1/0
I/O
I/O
1/0
1/0
1/0
1/0
1/0
1/0 (TNJT)
VCC
GND
1/0
I/O
I/O
1/0
1/0
1/0
1/0
1/0
PG
223t
G17
G18
H16
H17
G15
H15
H18
J18
J17
J16
J15
K15
K16
K17
K18
L18
L17
L16
L15
M1S
VCC
1/0
1/0
1/0
1/0
GND
M18
M17
N18
P18
M16
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
N15
P1S
I/O
U18
T16
R16
1/0, SGCK3
GND
DONE
VCC
PROGRAM
I/O (D7)
1/0, PGCK3
1/0
1/0
1/0
1/0
1/0 (D6)
1/0
1/0
N17
R1S
T18
P17
N16
T17
R17
P16
U17
R15
V18
T15
U16
T14
U15
R14
R13
V17
V16
T13
CB
228
P75
P76
P77
P78
P79
P80
P81
P82
PB3
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
Pl00
Pl0l
Pl02
Pl03
Pl04
P1D5
Pl06
Pl07
Pl08
Pl09
Pl10
Plll
Pl12
Pl13
Pl14
Pl15
Pl16
Pl17
Pl18
Pl19
P120
P121
P122
P123
P124
P125
Bndry
Scan
337
340
343
346
349
352
355
358
361
364
367
370
373
376
379
382
385
388
391
394
397
400
403
406
409
412
415
418
421
424
427
430
433
436
439
442
445
448
451
454
457
460
463
8-29
I
XC4000E High-Reliability Field Programmable Gate Arrays
XC4013E
Pad Name
1/0
1/0
1/0
GNO
1/0
1/0
1/0
1/0
1/0(05)
1/0 (C80)
1/0
1/0
1/0
1/0
1/0(04)
1/0
VCC
GNO
1/0(03)
1/0 (RS)
1/0
1/0
1/0
1/0
1/0(02)
1/0
VCC
PG
223t
U14
V15
V14
T12
R12
R11
U13
V13
U12
V12
T11
U11
V11
V10
U10
T10
R10
R9
T9
U9
V9
V8
U8
T8
V7
U7
CB
228
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
P143
P144
P145
P146
P147
P148
P149
P150
P151
P152
Bndry
Scan
466
469
472
475
478
481
484
487
490
493
496
499
502
505
508
511
514
517
520
523
526
529
532
XC4013E
Pad Name
1/0
I/O
I/O
I/O
GNO
1/0
1/0
1/0
1/0
1/0
1/0
1/0(01)
1/0 (RCLK,
ROY/BUSY)
I/O
1/0
I/O (00, OIN)
1/0, SGCK4
(OOUT)
CCLK
VCC
O,TOO
GNO
I/O (AO,WS)
I/O, PGCK4 (A1)
1/0
1/0
PG
223t
V6
U6
R8
R7
T7
R6
R5
V5
V4
U5
T6
V3
V2
CB
228
P153
P154
P155
P156
P157
P158
P159
P160
P161
P162
P163
P164
P165
Bndry
Scan
535
538
541
544
U4
T5
U3
T4
P166
P167
P168
P169
571
574
577
580
V1
R4
U2
R3
T3
U1
P3
R2
P170
P171
P172
P173
P174
P175
P176
P177
2
5
8
11
CB
228
P223
P224
P225
P226
P227
P228
P1
P2
P3
P4
P5
P6
P7
PG
299
C2
F5
E4
03
C3
Bndry
Scan
179
182
185
188
191
547
550
553
556
559
562
565
568
0
XC4013E
Pad Name
1/0 (CS1, A2)
1/0 (A3)
1/0
1/0
1/0
1/0
1/0
1/0
GNO
1/0
1/0
1/0
1/0
VCC
1/0(A4)
1/0 (A5)
I/O
I/O
1/0
1/0
1/0 (A6)
1/0 (A7)
GNO
PG
223t
T2
N3
P4
N4
P2
T1
R1
N2
M3
P1
N1
M4
L4
M2
M1
L3
L2
L1
K1
K2
K3
K4
CB
228
P178
P179
P180
P181
P182
P183
P184
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
P199
P200
Bndry
Scan
14
17
20
23
26
29
32
35
PG
299
E9
A7
09
B8
A8
C9
B9
El0
A9
010
C10
A10
Al1
Bl0
B11
C11
E11
011
A12
B12
A13
C12
012
E12
B13
A16
A14
C13
B14
013
Bndry
Scan
257
260
263
266
269
272
275
278
281
284
287
38
41
44
47
50
53
56
59
62
65
68
71
8/14/97
Pin Locations for XC4025E Devices
XC4025E
Pad Name
VCC
1/0 (A8)
1/0 (AS)
1/0
I/O
1/0
1/0
1/0 (A10)
1/0 (A11)
I/O
1/0
1/0
1/0
VCC
1/0
1/0
1/0
1/0
GNO
1/0
1/0
1/0
1/0
I/O
1/0
1/0 (A12)
1/0 (A13)
1/0
1/0
I/O
8-30
CB
228
P201
P202
P203
P204
P205
P206
P207
P208
P20S
P210
P211
P212
P213
P214
P215
P216
P217
P218
P219
P220
P221
P222
PG
299
K1
K2
K3
K5
K4
J1
J2
H1
J3
J4
J5
H2
G1
E1
H3
G2
H4
F2
F1
H5
G3
01
G4
E2
F3
G5
C1
F4
E3
02
Bndry
Scan
98
101
104
107
110
113
116
119
122
125
128
131
134
137
140
143
146
14S
152
155
158
161
164
167
170
173
176
XC4025E
Pad Name
1/0
1/0
1/0
1/0 (A14)
I/O, SGCK1 (A15)
VCC
GNO
1/0, PGCK1 (A16)
I/O (A17)
I/O
1/0
1/0, TOI
1/0, TCK
1/0
I/O
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
GNO
1/0
1/0
I/O, TMS
1/0
VCC
1/0
P8
PS
P10
P11
P12
P13
P14
P15
P16
P17
P18
A2
B1
04
B2
B3
E6
05
C4
A3
06
E7
B4
C5
A4
07
C6
E8
B5
A5
B6
08
C7
B7
A6
C8
194
197
200
203
206
20S
212
215
218
221
224
227
230
233
236
239
242
245
248
251
254
XC4025E
Pad Name
1/0
1/0
1/0
I/O
1/0
1/0
1/0
1/0
1/0
1/0
1/0
GNO
VCC
1/0
1/0
1/0
I/O
1/0
1/0
1/0
I/O
I/O
1/0
1/0
I/O
VCC
1/0
1/0
1/0
1/0
CB
228
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
290
293
296
299
302
305
308
311
314
317
320
323
326
329
332
335
November 21, 1997 (Version 1.3)
~XILINX
XC4025E
Pad Name
GNO
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0, SGCK2
o
(M1)
GNO
I (MO)
VCC
I (M2)
CB
228
299
PG
P42
A15
1/0
N20
Bndry
Scan
505
815
338
110
M18
508
1/0
341
344
110
P43
E13
C14
M17
M16
511
514
VCC
GND
P143
X10
X11
P44
P45
A17
014
347
1/0
1/0
N19
P20
517
520
110(03)
I/O(RS)
P144
P145
W10
V10
679
682
P46
P47
P48
816
C15
T20
N18
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
P146
T10
U10
685
523
1/0(02)
P150
1/0
P151
P152
P153
E14
A18
Bndry
Scan
350
353
356
359
362
P49
015
C16
P50
P51
817
818
P52
E15
016
377
C17
A20
383
386
P53
P54
P55
P56
P57
A19
C18
P58
P59
820
017
365
368
371
374
380
XC4025E
Pad Name
110
VCC
110
110
1/0
1/0
GNO
1/0
1/0
1/0
1/0
1/0
1/0
110
389
CB
228
1/0
1/0
1/0
P93
P94
P95
P96
P97
P98
P99
P100
PG
299
P19
N17
R19
526
529
532
R20
N16
P18
535
P101
P102
U20
P17
538
541
544
P103
P104
T19
R18
547
550
P105
P106
P16
V20
553
R17
T18
559
562
556
1/0, PGCK2
P60
819
390
391
110
P107
U19
565
110 (HOC)
P61
P62
C19
F16
394
397
1/0
P108
P109
V19
R16
568
571
1/0
1/0
1/0, SGCK3
P110
T17
574
P111
U18
577
580
1/0
1/0
1/0
1/0 (LOC)
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
110
P63
E17
400
P64
018
403
P65
C20
406
P112
X20
F17
GNO
P113
G16
409
412
DONE
P114
W20
V18
019
E18
415
418
VCC
PROGRAM
P115
P116
X19
U17
P68
020
421
P117
W19
P69
G17
424
W18
P70
P71
F18
427
430
P118
P119
P66
P67
P72
F19
E20
436
GNO
110
P73
H17
439
1/0 (07)
1/0, PGCK3
1/0
1/0
1/0
1/0
1/0
1/0
110
P74
P75
G18
442
445
1/0(06)
P123
110
448
110
P124
P125
1/0
1/0
P76
VCC
1/0
1/0
1/0
1/0
1/0
1/0
P??
P78
110
P79
P80
451
454
457
H19
H2O
460
J18
J19
463
466
110
GNO
110
472
J20
475
P83
K17
K18
478
481
VCC
1/0(05)
P84
K19
484
P85
P86
L20
K20
L19
I/O(CSO)
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
P87
110
P88
P89
P90
1/0
J16
G20
J17
1/0
1/0
1/0
1/0
K16
VCC
GNO
1/0
G19
H18
VCC'
433
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0 (lNlT)
110
110
H16
E19
P81
P82
L18
L16
P91
L17
M20
P92
M19
November 21, 1997 (Version 1.3)
469
487
490
493
496
499
502
P120
P121
P122
P126
P127
P128
P130
P131
P141
P142
VCC
1/0
1/0
1/0
1/0
GNO
1/0
1/0
1/0
1/0
1/0
If0
1/0
1/0
1/0 (01)
I/O(RCD<,
P147
P148
P149
299
PG
Bndry
Scan
V11
673
W11
676
X9
W9
700
703
706
W8
X7
709
X5
V8
P156
P157
W6
X6
724
T8
727
P158
V7
X4
730
733
P159
U7
P160
W5
736
739
P161
P162
US
V6
742
745
P163
P164
P165
U6
V5
751
754
757
760
110
X18
U15
1/0
1/0 (DO, OIN)
T14
604
110, SGCK4
(OOUT)
W17
V16
607
610
613
616
W15
X16
U13
628
631
634
P132
W14
637
P133
V13
X15
640
P134
T12
643
X14
646
649
652
U12
W13
X13
P136
V12
W12
655
658
661
P137
P138
T11
X12
664
667
P139
U11
670
748
ROY/8USY)
595
598
601
619
718
721
T7
X3
592
622
625
715
W7
W3
V15
T13
712
P154
P155
W4
X17
U14
694
697
U9
T9
1/0
V17
688
691
X8
V9
110
T15
U16
V14
P135
CB
228
P140
583
586
589
W16
P129
XC4025E
Pad Name
1/0(04)
P166
P167
P168
U5
V4
763
766
769
P169
X1
772
CCLK
P170
VCC
0, TOO
P171
P172
V3
VCC'
GNO
1/0 (AO,WS)
110, PGCK4 (A1)
P173
P174
110
P175
P176
110
110 (CS1,A2)
P177
P178
1/0 (A3)
1/0
1/0
1/0
P179
P180
110
P183
1/0
1/0
1/0
1/0
P184
P181
P182
P185
110
1/0
T6
U4
GNO'
W2
V2
R5
T4
U3
V1
R4
PS
U2
T3
0
2
5
8
11
14
17
20
23
26
29
32
U1
P4
R3
N5
38
41
T2
R2
44
47
35
GNO
P186
1/0
1/0
1/0
P187
T1
N4
50
P188
P189
P3
P2
53
56
8-31
I
XC4000E High-Reliability Field Programmable Gate Arrays
XC4025E
Pad Name
I/O
vee
I/O
I/O
I/O
I/O
I/O(M)
I/O (A5)
I/O
I/O
I/O
I/O
I/O (A6)
I/O (A7)
GND
8/14/97
8-32
CB
PG
228
299
P190
P191
N3
R1
M5
P1
M4
P192
P193
P194
P195
P196
P197
P198
P199
P200
N2
N1
M3
M2
L5
M1
L4
L3
L2
L1
Bndry
Scan
59
62
65
68
71
74
77
80
83
86
89
92
95
November 21, 1997 (Version 1.3)
-~----~-~
- - -
~XILINX
Ordering Information
Example for SMD Part:
r-97523 01 Q
Generic Standard
Microcircuit Drawing
(SMD) Prefix
it
Lead Finish
C = Gold
Package Type
X = Pin Grid
Y = Quad Flatpack
(Base Mark)
Z = Quad Flatpack
(Lid Mark)
Device Type
XC4005E = 97522
XC401 OE =97523
XC4013E = 97524
XC4025E = 97525
L -_ _ _
'--_ _ _-
QML Certified
Speed Grade
01 =-4
I
Example for
XC4010E
Military Tempeture Only P~
Device Type
XC4005E
XC4010E
XC4013E
XC4025E
Speed Grade
November 21, 1997 (Version 1.3)
~
·4 PG 1 1M
-
L
Temperature Range
M = Military (Tc = -550 C to + 1250 C)
Number of Pins
Package Type
CB =Top Braxed Ceramic Quad Flat Pack
PG = Ceramic Pin Grid Array
8-33
XC4000E High-Reliability Field Programmable Gate Arrays
8-34
November 21, 1997 (Version 1.3)
Programming Support
1
Introduction
2
Development System Products and CORE Solutions Products
3
CPLD Products
4
FPGA Products
5
SPROM Products
6
3V Products
7
HardWire FpgASIC Products
8
High-Reliability and QML Military Products
9
Programming Support
10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support and Services
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors
Programming Support
Table of Contents
HW-130 Programmer
HW-130 Programmer ..................................... '" .......................
Device and Package Support ...................................................
Programmer Accessories ......................................................
Interface Software and System Requirements ......................................
Programmer Functional Specifications ............................................
Programming Socket Adapters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Electrical Requirements and Physical Specifications .................................
New Programming Algorithm Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Adapter Selection Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
9-1
9-1
9-1
9-1
9-1
9-1
9-1
9-1
9-2
HW-130 Programmer
November 12, 1997 (Version 1.2)
Device and Package Support
•
•
Programming Socket Adapters
XC1700 Serial PROMs
XC9500 CPLDs
Supports all Xilinx package types
•
Electrical Requirements and Physical
Specifications
Programmer Accessories
•
•
•
•
•
Universal power supply
Power cord options for US/Asia, UK, European and
Japanese standards.
Serial download cable and adapters
Users manual
Programmer interface software
Vacuum handling tool
•
•
•
New Programming Algorithm Support
The programmer software operates on a variety of different
platforms. Table 1 indicates the minimum system requirements for each. In all cases, a CD-ROM drive and an RS232 serial port are required. The DOS driver software is
also available on 3.5" disk. A mouse is recommended.
•
Programmer Functional Specifications
•
•
•
•
•
•
•
Operating voltage: 100-250 VAC, 50-60 Hz
Power consumption: 1.0 Amp
Dimensions: 6" x 7.75" x 2"
Weight: 1 lb.
Safety standards: approved by UL, CSA, TUV
The new programmer algorithms are available via the Xilinx
WEB site, and FTP site:
Interface Software and System
Requirements
•
Supports all package styles: PLCC, PQFP, TQFP,
VQFP, HQFP, BGA, SOIC, VOIC, PGA and DIP
Device programming, erasing and verification
CPLD security control
PROM reset polarity control
Checksum calculation and comparison
Blank check and signature ID tests
Master device upload
File transfer and comparison
Self check and auto calibration
•
To access programmer software from the Xilinx WEB
site, go to www.xilinx.comand enter the "Answer" or
"Technical Support" section. Select the "file downlQad"
area. Within "Software Help", select "Programmer".
To access programmer software from the Xilinx FTP
site, use an FTP client to access ftp.xilinx.com. Login as
"Anonymous". Enter the /pub/swhelp/programmer
directory.
To view all programmer related files from the Xilinx
bulletin board (BBS), select "File Manager" and
"Software Help", then select "Programmer Suppor!."
Table 1: Interface Software and System Requirements
Requirements
DOS
Windows 3.1
Memory Needed
500KB
4MB
8MB
16MB
Hard Disk Space
2MB
2MB
2MB
2MB
System Software
3.3 or
greater
3.1.x.
4.00
or greater
November 12, 1997 (Version 1.2)
Windows 95 Windows NT
Sun OS
6MB
Solaris
6MB
HP9000/700
6MB
3.1 or greater SunOS 4.1.3 or SunOS 5.3 or HP-UXA09.05
greater
greater,
or greater
(Solaris 2.3 or
higher)
IBM RS6000
6MB
AIX 3.2.5 or
greater
9-1
I
HW-130 Programmer
Adapter Selection Table
Product Family
Package Types
Adapter PIN
XC7300' IXC9500
PLCC/CLCC 44
HW-133-PC44
XC7300'
XC7300 IXC9500
PQFP 44
VQFP 44
HW-133-PQ44
HW-133-VQ44
HW-133-PC68
XC7300
PLCC/CLCC 68
XC7300 IXC9500
PLCC/CLCC B4
HW-133-PC84
XC7300 IXC9500
PQFP 100
TQFP 100
HW-133-PQ100
XC7300 IXC9500
XC7300'
XC7300', 2
PGA 144
HW-133-TQ1 00
HW-133-PG144
PQFP 160
HW-133-PQ160
CPLD (XC7300'/XC9500)2
PQFP 160
HW-133-PQ160
XC7300'
XC9500
BGA225
HQFP 208
HW-133-BG225
HW-133-HQ20B
XC9500
BGA352
HW-133-BG352
XC1700
DIP 8
HW-137-DIP8
XC1700
PLCC20/S08/vOB
S020
HW-137-PC20/S08
HW-137-S020
XC1700
Calibration Adapter
HW-130-CAL
1) XC7300 devices are not recommended for new designs.
2) Xilinx manufactures two versions of the HW-133-PQ160 adapter. The correct adapter for programming XC9500 devices
has "CPLD" written on the front label, at the top left side, under the Xilinx logo.
9-2
November 12, 1997 (Version 1.2)
Packages and Thermal
Characteristics
1
Introduction
2
Development System Products and CORE Solutions Products
3
CPLD Products
4
FPGA Products
5
SPROM Products
6
3V Products
7
HardWire FpgASIC Products
8
High-Reliability and QML Military Products
9
Programming Support
10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support and Services
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors
Packages and Thermal
Characteristics
Table of Contents
Packages and Thermal Characteristics
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Thermal Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Package Thermal Characterization Methods & Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Some Power Management Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Package Electrical Characterization. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Component Mass (Weight) by Package Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Xilinx Thermally Enhanced Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Moisture Sensitivity of PSMCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Tape and ReeL ....................................................................
Reflow Soldering Process Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Sockets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
10-1
10-3
10-3
10-9
10-1 0
10-12
10-13
10-14
10-16
10-18
10-20
Package Drawings
Ceramic DIP Package - DD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Plastic DIP Package - PD8 .....................................................
SOIC and TSOP Packages - S08, V08. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SOIC Package - S020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PLCC Packages - PC20, PC28, PC44, PC68, PC84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
VQFP Packages - VQ44, VQ64, VQ100 ...........................................
TQFP/HTQFP Packages - TQ100, TQ144, TQ176, HT100, HT144, HT176 ...............
PQ/HQFP Packages - PQ100, HQ100 ........................ ; . . . . . . . . . . . . . . . . . ..
PQ/HQFP Packages - PQ44, PQ160, PQ208, PQ240, HQ160, HQ208, HQ240 ............
PQ/HQFP Packages - PQ304, HQ304 ............................................
BGA Packages - BG225. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
BGA Packages - BG256. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
BGA Packages - BG352,BG432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
BGA Packages - BG560. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ceramic PGA Packages - PG68, PG84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ceramic PGA Packages - PG120, PG132, PG156 ..................................
Ceramic PGA Packages - PG175 ................................................
Ceramic PGA Packages - PG191 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ceramic PGA Packages - PG223, PG299 . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . .. . . ..
Ceramic PGA Packages - PG411 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ceramic PGA Packages - PG475 ............. " .................................
Ceramic PGA Packages - PG559. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ceramic Brazed QFP Packages - CB100 (XC3000 Version) ........................ '"
Ceramic Brazed Packages - CB164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ceramic Brazed QFP Packages - CB100, CB164, CB196 (XC4000 Version) ..............
Ceramic Brazed QFP Packages - CB228 ....... " .................................
10-22
10-23
10-24
10-25
10-26
10-27
10-28
10-29
10-30
10-31
10-32
10-33
10-34
10-35
10-36
10-37
10-38
10-39
10-40
10-41
10-42
10-43
10-44
10-45
10-46
10-47
Packages and Thermal
Characteristics
November 20, 1997 (Version 2.0)
Package Information
Inches
VS.
packages have a lead spacing of 0.5 mm, 0.65 mm, or 0.8
mm.
Millimeters
The JEDEC standards for PLCC, CQFP, and PGA packages define package dimensions in inches. The lead spacing is specified as 25, 50, or 100 mils (0.025", 0.050" or
0.100").
Because of the potential for measurement discrepancies,
this Data Book provides measurements in the controlling
standard only, either inches or millimeters. (See Table i for
package dimensions.)
The JEDEC standards for PQFP, HQFP, TQFP, and VQFP
packages define package dimensions in millimeters. These
EIA Standard Board Layout of Soldered Pads for QFP Devices
+
I
I
.
MIE
I
bd
Table 1: Dimensions for Xilinx Quad Flat Packs 1
Dim.
MID
MIE
e
b2
12
Notes:
VQ44
VQ64
PQ100
HQ160
PQ160
9.80
9.80
20.40
28.40
9.80
9.80
14.40
28.40
0.80
0.50
0.65
0.65
0.4 - 0.6 0.3 - 0.4 0.3 - 0.5 0.3 - 0.5
1.60
1.60
1.802
1.80
HQ208
PQ208
VQ100
TQ100
TQ144
28.20
28.20
0.50
13.80
13.80
0.50
0.3 - 0.4
19.80
23.80
19.80
23.80
0.50
0.50
0.3 - 0.4 0.3 - 0.4
0.3 - 0.4
1.60
1.60
1.60
TQ176
1.60
HQ240
PQ240
HQ304
32.20
32.20
0.50
0.3 - 0.4
1.60
40.20
40.20
0.50
0.3 - 0.4
1.60
1. Dimensions in millimeters
2. For 3.2 mm footprint per MS022, JEDEC Publication 95.
November 20, 1997 (Version 2.0)
10-1
Packages and Thermal Characteristics
Suggested Board Layout of Soldered Pads for BGA
TYPICAL DOG BONE
VIA ARRANGEMENT
VL
VIA
VM
VH
LAND
BG225
BG256
BG352
BG432
Solder Land (L) diameter
0.89
0.79
0.79
0.79
BG560
0.79
Opening in Solder Mask (M) diameter
0.65
0.58
0.58
0.58
0.58
Solder (Ball) Land Pitch (e)
1.5
1.27
1.27
1.27
1.27
Land Width between Via and Land (D)
Distance between Via and Land (D)
0.3
0.3
0.9
0.3
0.3
0.9
0.3
Via Land (VL) diameter
1.06
0.65
0.65
0.9
0.65
0.65
0.9
0.65
0.4
Solder Mask Opening on Via (VM) diameter
0.4
0.4
0.4
0.4
Through Hole (VH), plated diameter
0.3
0.3
0.3
0.3
0.3
Pad Array
Matrix or External Row
Full
Periphery
26 x 26
Periphery
31 x 31
Perihpery
15 x 15
Periphery
20 x 20
-
4
4
4
5
Periphery rows
33 x 33
Notes:
1.
2.
3.
10-2
Dimensions in millimeters.
6 x 4 matrix for illustration only, one land pad shown with via connection.
Reference J-STD-013, use 'dog-bone' design via connection to land pad.
November 20, 1997 (Version 2.0)
~XILINX
Cavity Up or Cavity Down
Most Xilinx devices attach the die against the inside bottom
of the package (the side that does not carry the Xilinx logo).
This is called cavity-up, and has been the standard IC
assembly method for over 25 years. This method does not
provide the best thermal characteristics. Pin Grid Arrays
(greater than 130 pins) and Ceramic Quad Flat Packs are
assembled "Cavity Down", with the die attached to the
inside top of the package, for optimal heat transfer to the
ambient air.
For most packages this information does not affect how the
package is used because the user has no choice in how the
package is mounted on a board. For Ceramic Quad Flat
Pack (CQFP) packages however, the leads can be formed
to either side. Therefore, for best heat transfer to the surrounding air, CQFP packages should be mounted with the
logo up, facing away from the PC board.
Clockwise or Counterclockwise
The orientation of the die in the package and the orientation
of the package on the PC board affect the PC board layout.
PLCC and PQFP packages specify pins in a counterclockwise direction, when viewed from the top of the package
(the surface with the Xilinx logo). PLCCs have pin 1 in the
center of the beveled edge while all other packages have
pin 1 in one corner, with one exception: The 100- and 165pin CQFPs (CB100 and CB164) for the XC3000 devices
have pin 1 in the center of one edge.
CQFP packages specify pins in a clockwise direction, when
viewed from the top of the package. The user can make the
pins run counterclockwise by forming the leads .such that
the logo mounts against the PC board. However, heat flow
to the surrounding air is impaired if the logo is mounted
down.
Thermal Management
Modern high speed logic devices consume an appreciable
amount of electrical energy. This energy invariably turns
into heat. Higher device integration drives technologies to
produce smaller device geometry and interconnections.
With smaller chip sizes and higher circuit densities, heat
generation on a fast switching CMOS circuit can be very
significant. The heat removal needs for these modern
devices must be addressed.
Managing heat generation in a modern CMOS logic device
is an industry-wide pursuit. However, unlike the power
needs of a typical Application Specific Integrated Circuit
(ASIC) gate array, the power requirements for FPGAs are
not determined as the device leaves the factory. Designs
vary in power needs.
There is no way of anticipating the power needs of an
FPGA device short of depending on compiled data from
previous designs. For each device type, primary packages
November 20, 1997 (Version 2.0)
are chosen to handle 'typical' designs and gate utilization
requirements. For the most part the choice of a package as
the primary heat removal casing works well.
Occasionally designers exercise an FPGA device, particularly the high gate count variety, beyond "typical" designs.
The use of the primary package without enhancement may
not adequately address the device's heat removal needs.
Heat removal management through external means or an
alternative enhanced package should be considered.
Removing heat ensures the functional and maximum
design temperature limits are maintained. The device may
go outside the temperature limits if heat build up becomes
excessive. As a consequence, the device may fail to meet
electrical performance specifications. It is also necessary
to satisfy reliability objectives by operating at a lower temperature. Failure mechanisms and the failure rate of
devices depend on device operating temperature. Control
of the package and the device temperature ensures product reliability.
Package Thermal Characterization
Methods & Conditions
Method and Calibration
Xilinx uses the indirect electrical method for package thermal resistance characterization. The forward-voltage drop
of an isolated diode residing on a special test die is calibrated at constant forcing current of 0.520mA with respect
to temperature over a correlation temperature range of
22°C to 125°C (degree Celsius). The calibrated device is
then mounted in an appropriate environment (still air,
forced convection, circulating FC-40, etc.) Depending on
the package, between 0.5 to 4 watts of power (Pd) is
applied. Power (Pd) is applied to the device through diffused resistors on the same thermal die. The resulting rise
in junction temperature is monitored with the forward-voltage drop of the precalibrated diode. Typically, three identical samples are tested at each data pOint. The
reproducibility error in the set-up is within 6%.
Definition of Terms
TJ
Junction Temperature - the maximum temperature
on the die, expressed in °C (degree Celsius)
TA
Ambient Temperature - expressed in °C.
Tc
The temperature of .the package body taken at a
defined location on the body. This is taken at the primary heat flow path on the package and represents
the hottest part on the package - expressed in °C.
T1
The isothermal fluid temperature when junction to
case temperature is taken - expressed in °C.
Pd
The total device power dissipation watts.
expressed in
10-3
I
Packages and Thermal Characteristics
Junction-to-Reference General Setup
Type I, 2UOP board, is single layer with 2 signal planes
(one on each surface) and no internal Power/GND planes.
The trace density on this board is less than 10% per side.
Type II, the 4U2P board, has 2 internal copper planes (one
power, one ground) and 2 signal trace layers on both surfaces.
Data may be taken with the package mounted in a socket or
with the package mounted directly on the board. Socket
measurements typically use the 2UOP boards. SMT
devices may use either board. Published data always
reflects the board and mount conditions used.
DATA ACQUISITION AND
CONTROL COMPUTER
Figure 1: Thermal Measurement Set-Up (Schematic
for Junction to Reference)
Junction-to-Case Measurement - 8 J C
8JC is measured in a 3M Flourinert (FC-40) isothermal circulating fluid stabilized at 25°C. The Device Under Test
(OUT) is completely immersed in the fluid and initial stable
conditions are recorded. Pd is then applied. Case temperature (T is measured at the primary heat-flow path of the
particular package. Junction temperature (TJ) is calculated
from the diode forward-voltage drop from the initial stable
condition before power was applied.
c>
8 JC = (TJ - T cl/Pd
The junction-to-isothermal-fluid measurement (8J1) is also
calculated from the same data.
8JL = (TJ - T1)/Pd
The latter data is considered as the ideal 8 JA data for the
package that can be obtained with the most efficient heat
removal scheme. Other schemes such as airflow, heatsinks, use of copper clad board, or some combination of all
these will tend towards this ideal figure. Since this is not a
widely used parameter in the industry, and it is not very
realistic for normal application of Xilinx packages, the 8 J1
data is not published. The thermal lab keeps such data for
package comparisons.
Junction-to-Ambient Measurement - 8 JA
8 JA is measured on FR4 based PC boards measuring 4.5"
x 6.0" x .0625" (114.3mm x 152.4mm x 1.6mm) with edge
connectors. There are two main board types.
10-4
Data is taken at the prevailing temperature and pressure
conditions (22°C to 25°C ambient). The board with the OUT
is mounted in a cylindrical enclosure. The power application and signal monitoring are the same as 8 JC measurements. The enclosure (ambient) thermocouple is
substituted for the fluid thermocouple and two extra thermocouples brought in to monitor room and board temperatures. The junction to ambient thermal resistance is
calculated as follows:
8 JA = (TJ - TA)/Pd
The setup described herein lends itself to the application of
various airflow velocities from 0 - 800 Linear Feet per
Minute (LFM), i.e., 0 - 4.06 m/s. Since the board selection
(copper trace density, absence or presence of ground
planes, etc.) affects the results of the thermal resistance,
the data from these tests shall always be qualified with the
board mounting information.
Data Acquisition and Package Thermal
Database
Xilinx gathers data for a package type in die sizes, power
levels and cooling modes (air flow and sometimes heatsink
effects) with a Data Acquisition and Control system (DAS).
The DAS controls the power supplies and other ancillary
equipment for hands-free data taking. Different setups
within the DAS software are used to run calibration, 8 JA ,
8JC, fan tests, as well as the power effect characteristics of
a package.
A package is characterized with respect to the major variables that influence the thermal resistance. The results are
stored in a database. Thermal resistance data is interpolated as typical values for the individual Xilinx devices that
are assembled in the characterized package. Table 2
shows the typical values for different packages. Specific
device data may not be the same as the typical data. However, the data will fall within the given minimum and maximum ranges. The more widely used packages will have a
wider range. Customers may contact the Xilinx application
group for specific device data.
November 20, 1997 (Version 2.0)
~XILINX
Table 2: Summary of Thermal Resistance for Packages
PKG-CODE
BG225
BG256
BG352
BG432
BG560
CB100
CB164
CB196
CB228
008
HQ160
HQ208
HQ240
HQ304
HT144
HT176
PC20
PC44
PC68
PC84
P08
PG84
PG120
PG132
PG156
PG175
PG191
PG223
PG299
PG411
PG475
PG559
PP132
PP175
PQ100
PQ160
PQ208
PQ240
S08
TQ100
TQ144
TQ176
V08
8 JA
still air
(Max)
°C/Walt
37
32
14
13
10
44
29
25
19
114
14
15
13
11
86
51
46
41
82
37
32
32
25
25
24
24
18
16
14
35
29
35
37
35
28
147
37
35
29
162
8 JA
still air
(Typ)
°C/Walt
30
29
12
11
9
41
26
24
18
109
14
14
12
11
10.9
16.0
84
46
42
33
79
34
27
28
23
23
21
20
17
15
13
12.00
34
29
33
32
32
23
147
31
32
28
162
8 JA
still air
(Min)
°C/Walt
24
24
10
9
8
38
25
24
17
97
14
14
12
10
-
8 JA
250 LFM
(Typ)
°C/Walt
19
19
8
8 JA
500 LFM
(Typ)
°C/Watt
17
17
7
8
6
6
19
12
11
8
73
7
25
17
15
11
90
10
10
8
8
7
5
5.7
9
7
7.3
8 JA
750 LFM
(Typ)
°C/Watt
16
16
6
6
5
17
11
10
7
60
7
7
6
5
5.0
-
-
-
-
76
63
35
31
25
56
31
28
21
54
18
15
17
11
11
12
12
9
8
8
53
29
26
17
42
38
28
73
31
25
24
21
20
18
18
16
14
12
60
24
19
20
15
14
15
15
10
9
9
50
16
13
15
10
10
11
11
8
7
7
8 JC
(Typ)
°C/Watt
3.3
3.2
0.8
0.8
0.8
5.1
3.6
1.8
1.3
8.2
1.0
1.7
1.5
0.9
0.9
2.0
25.8
13.7
9.3
5.3
22.2
5.8
3.6
2.8
2.6
2.6
1.5
1.5
1.9
1.2
1.2
-
-
-
-
-
33
28
32
22
26
19
147
23
19
29
24
23
17
112
26
25
21
123
17
13
27
20
19
14
98
23
20
17
108
6.0
2.5
5.5
4.6
4.3
2.8
48.3
31
30
27
162
18
15
28
21
21
15
105
24
21
...
18
116
7.5
5.3
5.3
48.3
Comments
Various
4U2P-SMT
4U2P-SMT
4U2P-SMT
Estimated
Socketed
Socketed
Socketed
Socketed
Socketed
4U2P-SMT
4U2P-SMT
4U2P-SMT
4U2P-SMT
4U2P-SMT
Estimated
2UOP-SMT
2UOP-SMT
2UOP-SMT
2UOP-SMT
Socketed
Socketed
Socketed
Socketed
Socketed
Socketed
Socketed
Socketed
Socketed
Socketed
Socketed
Estimated
Socketed
Socketed
4U2P-SMT
2UOP-SMT
2UOP-SMT
2UOP-SMT
IEEE-(Ref)
4U2P-SMT
4L/2P-SMT
4U2P-SMT
Estimated
-~.
November 20, 1997 (Version 2.0)
10-5
I
Packages and Thermal Characteristics
Table 2: Summary of Thermal Resistance for Packages (Continued)
8 JA
still air
(Max)
PKG-CODE
8 JA
still air
(Typ)
V044
°CfWatt
44
V064
44
41
V0100
47
38
Notes:
°CfWatt
44
8 JA
still air
(Min)
DC/Watt
8 JA
250 LFM
(Typ)
8 JA
500 LFM
(Typ)
°CfWatt
34
39
°CfWatt
36
34
32
32
44
8 JA
750 LFM
(Typ)
DC/Watt
8 JC
(Typ)
Comments
DC/Watt
33
8.2
32
31
8.2
4U2P-SMT
30
29
9.0
4L/2P-SMT
4U2P-SMT
1. Maximum, typical and minimum numbers are based on numbers for all the devices in the specific package at the time of
compilation. The numbers do not necessarily reflect the absolute limits of that packages. Specific device data should lie
within the limits. Packages used for a broader spectrum of devices have a wider range in the table. Specific device data in a
package may be obtained from the factory.
2. Package configurations and drawings are in the package section of the data book.
3. 2UOP - SMT: the data is from a surface mount type I board -- no internal planes on the board.
4. 4U2P - SMT: the data is from a 4 layer SMT board incorporating 2 internal planes. Socketed data is taken in socket.
5. Air flow is given Linear Feet per Minute (LFM). 500 LFM = 2.5 Meters per Second
Application of Thermal Resistance Data
Thermal resistance data gauges the IC package thermal
performance. 8 JC measures the internal package resistance to heat conduction from the die surface, through the
die mount material to the package exterior. 8 JC strongly
depends on the package's heat conductivity, architecture
and geometrical considerations.
8JA measures the total package thermal resistance including 8 Jc. 8JA depends on the package material properties
and such external conditions as convective efficiency and
board mount conditions. For example, a package mounted
on a socket may have a 8 JA value 20% higher than the
same package mounted on a 4 layer board with power and
ground planes.
Example 1:
The manufacturer's goal is TJ (max) < 100°C
A module is designed for a TA = 45°C max.
A XC3042 in a PLCC 84 has a 8 JA = 32°C/watt.
Given a XC3042 with a logic design with a rated power
Pd of 0.75watt.
With this information, the maximum die temperature
can be calculated as:
TJ = 45 + (32 x .75) ==> 69°C.
The system manufacturer's goal of TJ < 100°C is met.
Example 2:
A module has a TA
By specifying a few constraints, devices are ensured to
operate within the intended temperature range. This also
ensures device reliability and functionality. The system
ambient temperature needs to be specified. A maximum TJ
also needs to be established for the system. The following
inequality will hold.
= 55°C max.
The Xilinx XC4013E is in a P0240 package (H0240 is
also considered).
A XC4013E, in an example logic design, has a rated
power of 2.50 watts. The module manufacturers goal is
TJ(max.) < 100°C.
Table 3 shows the package and thermal enhancement
combinations required to meet the goal of TJ < 100°C.
TJ(max) > 8 JA* Pd +TA
The following two examples illustrates the use of this inequality.
Table 3: Thermal Resistance for XC4013E in PQ240 and HQ240 Packages
DevName
Package
8 JA
still air
8 JA
(250 LFM)
8 JA
(500 LFM)
8 JA
(750 LFM)
8 JC
XC4013E
P0240
23.7
17.5
15.4
14.3
2.7
Cu, SMT2UOP
XC4013E
H0240
12.5
8.6
6.9
6.2
1.5
4 Layer Board data
Comments
Notes: Possible Solutions to meet the module requirements of 100°C:
1a.Using the standard PQ240;TJ = 55 + (23.7x 2.50) ==> 114.25 DC.
1b.Using standard PQ240 with 250LFM forced airTJ = 55 + (17.5 x 2.50) ==> 98.75 °C
2a.Using standard HQ240TJ = 55 + (12.5 x 2.50) ==> 86.25 °C
2b.Using HQ240 with 250 LFM forced airTJ = 55 + (8.6 x 2.50) ==> 76.5 °C
10-6
November 20, 1997 (Version 2.0)
~XILINX
For all solutions, the junction temperature is calculated as:
TJ = Power x 8JA + TA. All solutions meet the module
requirement of less than 100°C, with the exception of the
P0240 package in still air. In general, depending on ambi-
ent and board temperatures conditions, and most importantly the total power dissipation, thermal enhancements -such as forced air cooling, heat sinking, etc. may be necessary to meet the TJ{max) conditions set.
PQ/HQ Thermal Data Comparison
HO/PO Thermal Data
Size effect on ElJA
35
30
25
-<>-
12
~
'"
20
<0,20
0,95
L
---- ----
MAX,
0,95
A2
e
NOM,
1.00 1.05
12,00 BSC,
0,05
c
1.20
MILLIMETERS
MIN,
0,95
0,15
0,37
MAX,
0,05
0,05
b
NOM,
0.15
Ai
DIE
D,IE,
VQ100
VQ64
0,45
0.10
0,50 BSC,
0,60
0,75
----1-------1----
0,08
0,08
64
JEDEC MS-026-ACD
0.15
1.00 1.05
16,00 BSC,
----
0,50 BSC,
0.45
0,60
---- -------
""><-
0,75
NOTES:
1, ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14,5M-1982,
2, DIMENSIONS 01 AND E1 DO NOT INCLUDE MOLD
PROTRUSION, ALLOWABLE MOLD PROTRUSION SHALL
NOT EXCEED O,25mm PER SIDE.
3. THE TOP OF PACKAGE MAY BE SMALLER THAN THE
BOTTOM OF PACKAGE BY 0.15mm.
0,08
0,08
100
JEDEC MS-026-AED
44, 64, 100-PIN PLASTIC VERY THIN QFP (VQ44, VQ64, VQ100)
November 13, 1997 (Version 1.2)
10-27
Package Drawings
TQFP/HTQFP Packages - TQ1 00, TQ144, TQ176, HT1 00, HT144, HT176
TOP VIEW
BonOM VIEW
c
-=
rf[3l
-
L
GAGE PLANE
r-r-----r-;<---.--~======~_+~-:=r===j=-.L 0°- r
1.00 RE F, -1---'---1
DETAIL 'A'
TQ/HTlOO
s
TQ/HTl76
TQ/HTl44
MILLIMETERS
MILLIMETERS
MILLIMETERS
i
P
MIN,
NOM,
MAX,
MIN,
NOM,
MAX,
MIN,
NOM,
MAX,
A
'"""-
1.60
~
~
1.60
~
~
1.60
AI
0,05
'"""'"""-
0,05
0.10
0,15
0,05
0.10
0,15
A2
1.35
1.35
1.40
1.45
1.35
1.40
1.45
lAO
DIE
16,00 BSC
14,00 BSC
DIIEI
L
0,15
1,45
0045
22,00 BSC
20,00 BSC
I 0,60 I 0,75
0,50 BSC
e
26,00 BSC
0.451
0,60
24,00 BSC
I 0,75
0,50 BSC
b
0.17
0,22
0,27
c
ccc
0,09
0,20
0,17
0,09
'"""-
'"""'"""-
0,08
~
clocl
N
'"""-
'"""-
0,08
~
100
REF, JEDEC MS-026-BED
0,22
0.451
I 0,75
0,22
0,27
'""'--
0,20
~
~
0,08
~
"""-
0,08
0,27
0,20
0,17
0,09
~
0,08
~
0,08
,..........
0,60
0,50 BSC
144
176
JEDEC MS-026-BFB
JEDEC MS-026-BGA
NOTE:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5-1982
2. DIMENSION 01 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE MOLD PROTRUSION SHALL
NOT EXCEED 0.25mm PER SIDE.
3, PACKAGE TOP DIMENSION MAY BE SMALLER THAN
THE BOTTOM DIMENSION BY 0.15mm.
,&,. THE SAME PACKAGE DIMENSIONS APPLY FOR
THERMALLY ENHANCED PRODUCTS. HEAT SINK IS
ADDED. THE PACKAGE CODE IS "HT".
100, 144, 176-PIN TQFP /HEAT SINK TQFP (TQ/HT100, 144, 176)
10-28
November 13, 1997 (Version 1,2)
~XILINX
PQ/HQFP Packages - PQ100, HQ100
TOP VIEW
BonOM VIEW
~------D2------~
s
~
B
0
L
A
AI
A2
D
DI
D2
MILLIMETERS
NOM,
MIN,
~
~
0,25
~
2,50
MAX,
3.40
0,50
2,70
2,90
23,20 ESC
20,00 BSC
18,85 REF,
E
17,20 ESC
El
14,00 ESC
12,35 REF,
E2
L
I
DETAIL 'A'
0,73
e
0,88
1.03
0,65 ESC
b
0,22
~
0.40
c
0.13
~
0,23
0,25
0.0.0.
~
~
bbb
~
~
ccc
~
~
0,20
0.10
dcld
~
~
0.13
NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM TO ANSI Y14,5M-1994.
2. DIMENSIONS '01' AND 'E1' DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION IS O.25mm PER SIDE.
3. THE TOP OF PACKAGE MAY BE EQUAL TO OR SMALLER THAN
THE BOTTOM OF PACKAGE BY 0.15 MILLIMETERS.
4. PACKAGE CONFORMS TO JEDEC OUTLINE MS-022-GC1
~ THE SAME PACKAGE DIMENSIONS APPLY FOR THERMALLY ENHANCED
PRODUCTS. HEAT SINK IS ADDED. THE PACKAGE CODE IS 'HQ'.
100-PIN PQFP (PQ100)
100-PIN HEAT SINK PQFP (HQ100)
November 13, 1997 (Version 1,2)
10-29
Package Drawings
PQ/HQFP Packages - PQ44, PQ160, PQ208, PQ240, HQ160, HQ208, HQ240
BOTTOM VIEW
PIN 1 LD,
SEE DETAIL 'A'
~==="-"-'---==
~~)!rp
0,20 MIN'lIl--
cp
f
I.A"- O~:IN'
t-~l--JJ,~ ~t f~;~f;;
__
IQlccciCI
PQ44
~
~
PQ/HQ160
MILLIMETERS
MIN,
NOM,
2.15
MAX,
2,35
0,25
2,10
~
A
~
0,05
Al
2,00
1.95
A2
13,20 BSC
DIE
Dl/El
10,00 BSC
D2/E2
8,00 REF,
0,73
0,88
L
1.03
0,80 BSC,
I:>
0,30
~
0.45
c
0.13
0.23
~
0.0.0.
~
0,25
~
~
1:>1:>1:>
0,20
~
ccc ~
~
0.10
~
eIeIeI ~
0,20
N
44
REF, JEDEC MS-022-AB
"
NOTES:
MILLIMETERS
MIN,
NOM, MAX,
3,70
4.10
'""*-'
0,25
0,33
0,50
3,20
3.40
3,60
31.20 BSC
28,00 BSC
25,35 REF,
0,88 I 1.03
0,73
0,65 BSC,
0,22
0.40
'""'-'
0.13
0,23
'""'-'
0,25
~
"'*-'
"'>f<.0,20
'""'-'
"'>f<.0.10
"'>f<."'>f<.0,13
'""*-'
160
JEDEC MS-022-DDI
PQ/HQ208
MIN,
NOM, MAX,
3,70
4,10
'""*-'
0,25
0,33
0,50
3,20
3,60
3.40
30,60 BSC
28,00 BSC
25,50 REF,
0,75
0,50
0,60
0,50 BSC,
0,27
0,17
0,22
"'*-'
"'*-'
'""*-'
"'>f<."'>f<.-
DETAIL 'A'
PQ/HQ240
MILLIMETERS
0,09
"'*-'
"'*-'
"'*-'
'""*-'
J
1.60 REF,
0,20
0,25
0,20
0,08
0,08
208
JEDEC MO-143-FA-I
MILLIMETERS
MIN,
MAX,
4,10
0,25
0,50
3,60
3,20
3.40
34,60 BSC
32,00 BSC
29,50 REF,
0,50 I 0,60 I 0,75
0,50 BSC,
0,17
0,27
->I<-->I<-0,09
0,20
0,25
"'*-'
'""'-'
->I<--
"'*-'
'""*-'
'""*-'
NOM,
3,78
0,38
"'*-'
'""*-'
'""*-'
0,20
0,08
0,08
240
JEDEC MO-143-GA
1. ALL DIMENSIONS AND TOLERANCES CONFORM TO ANSI Y14.5M-1994.
2. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION SHALL NOT EXCEED 0.25mm PER SIDE.
3. PACKAGE TOP DIMENSIONS MAY BE SMALLER THAN THE BOTTOM DIMENSIONS BY 0.20mm.
4. THE SAME PACKAGE DIMENSIONS APPLY FOR THERMALLY ENHANCED
PRODUCTS. HEAT SINK IS ADDED. THE PACKAGE CODE IS "HQ".
44, 160, 208, 240-PIN PQFP /HEAT SINK PQFP (PQ44, PQ/HQ160, 208, 240)
10-30
November 13, 1997 (Version 1.2)
~XILINX
PQ/HQFP Packages - PQ304, HQ304
TOP VIEW
BOTTOM VIEW
1~~-9--------Dl---------3~;~
22
228
r-------+----.,.
228
1
0
+
+
E1
o '--------IL...--f---"
153
76
IS'
b~I~11~~2__~.-__~-.____~~7~7
152
1$lddd (fDlclA - B cs>IDcs>1
5·-16·
L".,::',~') J ~
LEAD FINISH: SOLDER PLATE
0,20
~--,/
A
s
y
M
MILLIMETERS
B
0
L
MIN.
NOM.
MAX.
A
~
4.23
4.50
Al
0.25
0.43
~
A2
3.60
3.80
4.00
DIE
42.35
42.60
42.85
DI/E1
39.90
40.00
40.10
D2/E2
L
37.50 REF.
0.45
e
0.60
0.75
0.50 ESC.
b
0.17
~
0.27
bl
~
0.20
~
C
0.09
~
ccc
0.08
ddd
0.07
0.20
I
REF,;---+----~
NOTES:
DETAIL 'A'
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1994
2. DIMENSIONS 'Dr AND 'E1' DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE MOLD PROTRUSION SHALL NOT EXCEED
O.25mm PER SIDE.
3. PACKAGE TOP DIMENSIONS MAY BE SMALLER THAN BonOM
DIMENSIONS BY O.15mm.
4. CONFORMS TO JEDEC OUTLINE MO-143-JA
& THE
SAME PACKAGE DIMENSIONS APPLY FOR THERMALLY ENHANCED
PRODUCTS. HEAT SINK IS ADDED. THE PACKAGE CODE IS 'HQ'.
304-PIN PQFP (PQ304)
304-PIN HEAT SINK PQFP (HQ304)
November 13, 1997 (Version 1.2)
10-31
Package Drawings
BGA Packages - BG225
TOP VIEW
BOTTOM VIEW
Q10,201 (4X)
Dl
+
14 13 12 11
10
9
B
765432~
loooooo
l-
000000
~
B
0000000
0000000
c
0000000
0000000
D
0000000
0000000
0000000
E
0000000
000000000000000
f
G
000000*000000
o
0
E1
J
0000000
0000000
000000000000000
K
L
0000000
0000000
0000000
0000000
M
0000000
0000000
N
p
0000000
0000000
0000000
000000$-
,fl
R ,050 TYP,
r
A
"\
+
E
r.--
/
D
P1N 1 I.D,
~
24,70 MAX,
II/Ieee lei
s
M
MILLIMETERS
B
D
L
MIN,
A
Al
Y
NOM,
MAX,
~
2,15
3,50
0,50
0,60
0,70
DIE
27,00 BSC
DliEI
21.00 REF,
1.50 BSC
e
Ob
0,60
0,75
0,90
ccc
~
~
0,35
cldcJ
~
~
0,30
eee
~
~
0,15
M
NOTES:
1. ALL DIMENSIONING AND TOLERANCING CONFORM
TO ANSI Y14.5M-1994
2. SYMBOL "M" IS THE PIN MATRIX SIZE.
3. CONFORMS TO JEDEC MO-151-CAL (DEPOPULATED)
15
225-BALL PLASTIC BGA (BG225)
10-32
November 13, 1997 (Version 1.2)
~XILINX
BGA Packages - BG256
BG256
BonOM VIEW
TOP VIEW
A1 BALL PAD CORNER
I
D1
20.
19
18
17
16
16
14
13
12
1
10
9
8
7
6
5
4
3
2
B
1
:"-
I
$000000000000000000$
00000000000000000000
00000000000000000000
00000000000000000000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
'0000
000
0000
o 0
0000
0000000000000000000
00000000000000000000
00000000000000000000
0000000000000000000$
R 0.50 TYP. 3 PLACES
1'6
11
~
!J
P1N 1 LD.
'\
+
E
E1
/
r
J\
~
24.70 MAX.
I
s
y
M
B
0
MILLIMETERS
L
MIN.
A
~
Al
0.50
DIE
DliEI
e
(lib
NOM.
MAX.
2.33
3.50
0.60
0.70
27.00 BSC
24.14 REF
1.27 BSC
0.75
0.60
0.90
0.0.0.
~
~
ccc
~
~
eIeIeI
~
~
0.20
0.35
0.30
eee
~
~
0.15
M
NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1994
2. SYMBOL 'M' IS THE BALL MATRIX SIZE.
3. CONFORMS TO JEDECMO-151-BAL-2
A116 EXTRA BALLS (GROUNDED) - APPLICABLE TO DEVICES
WITH 28K GATES OR MORE.
20
November 13, 1997 (Version 1.2)
10-33
Package Drawings
BGA Packages - BG352, BG432
BOTTOM VIEW
Q10.201 4X
B
~------~~r-------~·T~~
PIN 1 LD.
~~
r-__~-----------r--------------~
D1
l302S2726252423222120291918171b15141312UlO 9 8 7 6 5" 3 2
I--
$00000000000000
000000000000000
000000000000000
000000000000000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
i
00000000000000$
000000000000000 •
000000000000000 c
OOOOOOOOOOOOOOOD
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
-t
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
000005?000000000
OOOOO~~OOOOOOOO
gggggoggggggggg
J
TOP VIEW
£
F
G
H
J
•
L
M
N
P
R
T
0000 u
0000 v
E1
1-+----+
E
0000 \I
0000 y
I
I
0000 AA
0000 AS
0000 AC
0000 AD
0000 A£
0000 A.
0000 AG
OOOOOOOOO~OOOOO AH
OOOOOOOO~~OOOOO AJ
A.
gggggggggc:gggg~
A
(EXTENT OF ENCAPSULATION)
f.oc-
Lo.5o
MIN.( 4X)
A2
SEATING
BG352
sy
M
B
0
L
A
Al
A2
A3
DIE
DliEI
SOLDER BALLS
BG432
MILLIMETERS
MILLIMETERS
MIN,
NOM,
MAX,
MIN,
NOM,
MAX,
1.10
0,50
0,60
0,20
1.40
0,60
~
1.70
0,70
1.00
~
~
1.10
0,50
0,60
0,20
1.40
0,60
~
1.70
0,70
1.00
~
~
35,00 BSC
31.75 REF,
1.27 BSC
e
9l1o
0,60
0,75
Q••
~
40,00 BSC
38.10 REF,
1.27 BSC
0.60
0.75
~
0,90
0.20
~
~
bbb
~
~
0,25
~
~
ccc
~
~
~
~
ddd
~
~
0.15
0,30
~
..",...
0.90
0,20
0.25
0.15
0,30
M
26
31
REF. JEDEC MO-192-BAR-2 JEDEC MO-192-BAU-l
SECTION A-A
(NOT TO SCALE)
NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1994
2. SYMBOL "M" IS THE PIN MATRIX SIZE.
3. CONFORMS TO JEDEC MO-192 (DEPOPULATED)
4. 31 X31 MATRIX SIZE IS SHOWN FOR ILLUSTRATION ONLY.
5. BOTH PACKAGES HAS 3 ROWS OF PINS ON EACH SIDE.
6. CONTACT XILINX FOR CLARIFICATION.
352, 432-BALL PLASTIC BGA (BG352, BG432)
CAVITY DOWN
10-34
November 13, 1997 (Version 1.2)
~XILINX
4Xr
BGA Packages - BG560
BOnOM VIEW
TOP VIEW
PIN 1 LD.
Dl
3~23?'kilkl~i~i'k12019181~6151413121110 9 8 7 6 5 4 3; J
!
$000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
000000000000000$
0000000000000000
0000000000000000
0000000009000000
0000000000000000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
+
I
I
000000000
0
T
E
A
AI
A2
1.10
0.50
0.60
0.20
1.38
0.60
1.70
0.60
ccc
bbb
...,..,.,..
ddd
...,..,.,..
M
MIN. (4X)
...,..,.,..
...,..,.,..
...,..,.,..
...,..,.,..
I
'~--1
SECTION A-A
A3 ]
0.70
1.00
...,..,.,..
...,..,.,..
0.75
(GRDUNDED>~
(NOT TO SCAL£)
...,..,.,..
NOTES:
42.50 BSC
40.64 REF.
1.27 BSC
...,..,.,..
...,..,.,..
aaa
~~
METAL HEATSINK
MAX.
e
!lito
E-I-----+
OOOOO$~
.... I-- 0.50
NOM.
DIIEI
Y
AA
AB
AC
AD
AE
AF
AG
AH
000000 AM
MIN.
As
v
IJ
gggggg
L
DIE
T
U-El
oooooooo~c
N
0
C
D
E
F
G
H
J
K
L
M
N
P
R
~-~-------------+------------~
oooooooo~~ 000000 AL
MILLIMETERS
Y
M
B
rt-
ggggggggg~
A
s
.r--m
~--------------D
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14,5M-1994
2. SYMBOL 'M' IS THE PIN MATRIX SIZE.
3. CONFORMS TO JEDEC MO-192-BAV-l (DEPOPULATED)
0.90
0.20
0.15
0.25
0.30
33
2
560 BALL PLASTIC BGA (BG560)
November 13, 1997 (Version 1.2)
10-35
Package Drawings
Ceramic PGA Packages - PG68, PG84
BOnOM .VIEW
TOP VIEW
~------D1------~
L~0000
0000~
K00000
J00
0
H00
G000
00000
0
00
00
000
~ 000
0
0
0
1
2 3
+
0
0
0
INDEX PINLf?00
D00 f
00
c 000 0
0
00
800000 00000
A@0000 0000~
E
E1
-+------It---
+
---li---t-
4 5 6 7 8 9 10 11
LID
PIN 1 INDEX
PG68 DR PG84
(2).050 TYP.
sy
INCHES
M
B
0
L
MIN.
A
~
NOM.
MAX.
.145
1.090 1.100 1.115
1.000 REF.
DI/EI
~
DIE
L
.120
Q
.045
M
REF.
.140
.060
.100 BSC
e
!Ilk>
.130
~
.016
.020
.018
11
JEDEC MO-66 AC
NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL 'M' IS THE PIN MATRIX SIZE .
&. PIN C3 MAY OR MAY NOT BE ELECTRICALLY CONNECTED.
4. PG68 DOES NOT HAVE THIRD ROW ON EACH SIDE
EXCEPT THE INDEX PIN .
5. LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICROINCHES MIN.)
- MILITARY (50 MICROINCHES MIN.)
& THIS FEATURE IS OPTIONAL, MAYBE AT DIFFERENT LOCATION.
68, 84-PIN CERAMIC PGA (PG68, PG84)
10-36
November 13, 1997 (Version 1.2)
~XILINX
Ceramic PGA Packages - PG120, PG132, PG156
BOnOM VIEW
TOP VIEW
1$00000000000000$
c=J
R0~000000000000~0
,0000000000000000
.000
000
.000
000
l000
000
K 000
000
J 000
000
H 000
000
G 000
000
F 000
000
E 000
000
0000
000
c00000·0000000000
E
+
B0~00
E1
+
E
000000000~0
.0000·0000000000$
11
13 14 I
,/
16
.P
PIN 1 INDEX
LID
c=-==~~t-~II
:'ifiFrniliffl'lFiFili1'lFH1~11 ::;:r
QJ f j~ ~ ~ mmm Htr LJ r
,r=c=J=-
SEA TING PLANE -
::I::i
J
I--
(2),050 TYP,
PG120
sy
INCHES
M
B
c
L
A
DIE
DIIEI
PGI32
MIN,
NOM,
.145
1.340 1.360 1.380
1.200 BSC
~
~
MIN,
L
PG156
INCHES
MAX,
INCHES
MAX,
NOM,
MIN,
NOM,
1.440 1.460
1.300 BSC
.145
1.640 1.660 1.680
1.500 BSC
~
~
~
L
.120
,130
,140
.120
.130
.140
,120
,130
.140
Q
,045
~
,060
,045
~
,060
,045
~
,060
QI
,025
~
~
,025
~
~
,025
~
~
.100 BSC
e
Illb
,016
,018
M
.100 BSC
,020
13
REF, JEDEC MO-067-AE
,016
,018
I
MAX,
.145
1.480
~
Q1
.100 BSC
,020
14
JEDEC MO-067-AF
,016
,018
,020
16
JEDEC MO-067-AH
NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL 'M' IS THE PIN MATRIX SIZE.
3. LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICROINCHES MIN.)
- MILITARY (50 MICROINCHES MIN.)
120,132, 156-PIN CERAMIC PGA (PG120, PG132, PG156)
November 13, 1997 (Version 1.2)
10-37
Package Drawings
Ceramic PGA Packages - PG175
BOnOM VIEW
TOP VIEW
It-----Dl----t
l
r---
C:=J
IT
E
L'I ~
J
'----5
6
7
8
9
'0
11
'2
13 14 '5 16
+
jj
.~.
PIN 1 INDEX
1~=-C~-~~~~~rMn;~TT~~JQl
SEA TING PLANE --...:
s
y
M
B
0
L
A
INCHES
MIN,
NOM,
~
MAX,
,145
~
DIE 1.640
1.660
1.680
1.500 BSC
DJlEI
L
.120
.130
.140
Q
,045
,025
~
,060
~
~
Ql
.100 BSC
e
(Zjb
M
,016
,018
,020
NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL 'M' IS THE PIN MATRIX SIZE.
3. CONFORMS TO JEDEC MO-067-AH
4. LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICROINCHES MIN.)
- MILITARY (50 MICROINCHES MIN.)
16
175-PIN CERAMIC PGA (PG175)
10-38
November 13, 1997 (Version 1.2)
~~-------------------
~XILINX
Ceramic PGA Packages - PG191
BOnOM VIEW
TOP VIEW
~------~D1~----~~
r--'
v@@@@@@@@@@@@@@@@@@
c::=:::::J
"') [vee
u@~@@@@@@@@@@@@@@@@
r@@@@@@@@@@@@@@@@@@
@@
@@@@
R@@@@
p@@@
@@@
N@@@
@@@
M@@@
@@@
L@@@
@@@
K@@@@
@@@@
J@@@@
@@@@
H@@@
@@@
G@@@
@@@
f@@@
@@@
E@@@
@@@
D@@@@
@@
@@@@
c@@@@@@@o@@@@@@@@@@
E
+
@@@@@
@@@@@@@@@@@
BYP ASS
PADS
ill CAPACITOR
LID
SEA TING PLANE -
,
vee, [v..
·@e@@@@o@@@@@@@@@~@
A
+
E
PIN 1 INDEX
~
===~~~~TTTr~nnnn~~~~rQ1
f
I
s
y
M
INCHES
B
0
L
MIN,
NOM,
MAX,
,115
.145
1.860 1.880
1.700 BSC
DI/EI
L
,130 .140
.120
A
~
DIE 1.840
Q
QI
,045
,025
M
,060
~
~
.100 BSC
e
¢b
~
,016
,018
18
,020
NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982 .
2. SYMBOL 'M' IS THE PIN MATRIX SIZE.
3. CONFORMS TO JEDEC MO-067-AK
BYPASS CAPACITOR PADS - GOLD PLATED.
MAY OR MAY NOT BE PRESENT ON ALL PACKAGES .
5. LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICROINCHES MIN.)
- MILITARY (50 MICROINCHES MIN,)
&.
191-PIN CERAMIC PGA (PG191)
November 13, 1997 (Version 1.2)
10-39
Package Drawings
Ceramic PGA Packages - PG223, PG299
BOTTOM VIEW
TOP VIEW
1------1 Dll--------i
=
x@@@@@@@@@@@@@@@@@@@@
w@@@@@@@@@@@@@@@@@@@@
v@@@@@@@@@@@@@@@@@@@@
u @@@@@@@@@@@@@@@@@@@@
T @@@@@@@@@@@@@@@@@@@@
@@@@@
@@@@@
@@@@@
@@@@@
N @@@@@
@@@@@
@@@@@
@@@@@
@@@@@
@@@@@
K @@@@@
@@@@@
@@@@@
@@@@@
@@@@@
@@@@@
@@@@@
@@@@@
@@@@@
@@@@@
@@@@@@@ @@@@@@@@@@@@
D @@@@@@o@@@@®®®®®®®®®
c ®®@®®® ®®®®®®®®®@®®®
B @@@@@o®@®@@@®®@@®@@@
A
®@@®o@@@®®@@@@@@@®@
+
E -+----If----
5
+
6 7 8 9 10 11 12 1314 15 16 17 1819 20
PIN 1 INDEX
LID
1~~;n:n:rn~~W[Ql
r
SEATING PLANE --'=
,050
sy
M
B
PG223
PG299
INCHES
INCHES
0
MIN,
NOM,
A
~
,115
L
DIE 1.840
DI/EI
L
.120
1.860
,016
NOM,
~
~
2,040
2,060
MAX,
.145
2,080
1.900 BSC
,140
.120
~
,060
,045
~
,060
~
~
,025
~
~
.130
,100 BSC
e
M
.145
1.880
MIN,
1.700 BSC
Q ,045
QI ,025
i1Jb
MAX,
,018
.130
.140
.100 ESC
,020
18
,016
,018
,020
20
REF, JEDEC MO-067-AK
NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL 'M' IS THE PIN MATRIX SIZE.
3. FOR PG223, ONLY 4 ROWS OF PINS ON EACH SIDE .
4. LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICROINCHES MIN.)
- MILITARY (50 MICROINCHES MIN.)
&, OPTION - HEAT SINK MAY BE ADOED FOR HIGH POWER
DEVICES BUT DIMENSION 'A' REMAINS .145" MAX.
6. PG299 20X20 MATRIX SHOWN FOR ILLUSTRATION ONLY.
7. CONTACT XILINX FOR CLARIFICATION.
JEDEC MO-067-AM
223, 299-PIN CERAMIC PGA (PG223, PG299)
10-40
November 13, 1997 (Version 1.2)
~XILINX
Ceramic PGA Packages - PG411
BOnOM VIEW
TOP VIEW
B
.
D
c=::::J
vss vee
]
~.
E
l-
W~
+
~~
ffi~
/t I
p
vss
LID
.050X45°CHAM. TYP.
BYPASS - . /
LSiCAPACITDR PADS
r
A3
SEATING
PLANE
.~
PIN 1 INDEX
'.
HEATSINK
I
oJ [~~~~i~~~~m~ll~mm~mm~" j
.050X.025 TYP.
¢b
-l
L
I
s
y
M
B
0
INCHES
L
MIN,
A
~
A3
,015
NOM,
~
,020
DIE 2.040 2,060
MAX,
.165
,025
2,080
1.900 BSC
DJ/EJ
L
.110
~
.150
QJ
,015
~
,045
MJ
wb
,016
39
.018
.020
NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1994
2. SYMBOL 'M' IS THE PIN MATRIX SIZE.
&
BYPASS CAPACITOR PADS - GOLD PLATED
MAY OR MAY NOT BE PRESENT ON ALL PACKAGES.
4. CONFORMS TO JEDEC MO-128- AM.
5. LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICROINCHES MIN.)
- MILITARY (50 MICROINCHES MIN.)
411-PIN CERAMIC PGA (PG411)
November 13, 1997 (Version 1.2)
10-41
Package Drawings
Ceramic PGA Packages - PG475
PG475
BonOM VIEW
TOP VIEW
~--------D1
.................. .............. ...
'"
•.•.•.•..............•...•.•............
.... .............
............
.
.......
.
.....•
:.... .••....
.•.•.•.
......
..
.
.....
.....•.
.......
:. ....... + .......
,. .•.....
.......
.......
.......
~
"
c::::J
e••••••••••••••••••••••••••••••••••s••
M",
D
B
••
l-
]
"'",
"",..
'"
","
N>
•••••••
• ••••••
.y •••••••
• ••••••
"
•
"
•
E1
E
......
+
...
II!'
•••••••
•••••••
•••••••
•••••••
.:.:.:.
.:.:.:.
•••••••••••••••• •• ••••••••••••••••••••
•••••••••••••••••••
. ·s·.·.·.·.·.·.·.......................
,
J I
••••••••••••••••••••••••••••••••••••
PIN 1 INDEX
J
.050X45· CHAM.
LID
I
1
A3
HEAT SINK
j
[
------=~=*-l J4i;)(J~I~u~~I~~m~m~m~;mmm=~;;~;~~;m;;f¥WQ
•
SEATING PLANE
s
y
M
B
0
L
.050X.025 TYP.
INCHES
MIN.
NOM.
;;;;;;L
N
0
MAX.
~
~
.165
.015
.020 .025
DIE 2.140 2.160 2.180
2.000 Bse
D1/E1
~
L
.110
.150
Q1 .015
~
.045
-II-
¢b
1
--lI 11--.--.---,-,--,-,---.---.
-+
9!.030@ c@ A@ B@
9!.010@ C
T
E
A
A3
M
¢b
10-42
.016
41
.018
.020
NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM TO
ANSI Y14.5M-1994
2. SYMBOL "M" IS THE PIN MATRIX SIZE.
3. CONFORMS TO JEDEC MO-128-AN
4. LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICROINCHES MIN.)
- MILITARY (50 MICROINCHES MIN.)
November 13, 1997 (Version 1.2)
~XILINX
Ceramic PGA Packages - PG559
PG559
BODOM VIEW
TOP VIEW
~---------Dl-----------1
••••• • ••••••••••••• •••••••••••••• •••••
•••••••••••••••••••••
•••e••••••••••••••••••••••••••••••••••••••
»
D
B
c::::::J
••••••••••••••••••••• •••••••••••••••••••••
•••••••• •••••• •••••• ••••••••
••••••••
••••••••
••••••••
•
•••••••
••••••••
•
•••••••
••••••••
••••••••
••••••••
••••••••
••••••••
••••••••
••••••••
••••••••
••••••••
••••••••
••••••••
•
•••••••
••••••••
•
•••••••
••••••••
••••••••
••••••••••••
• •••••• ••••••••
•••••••••••••••••• •• •••••••••••••••••••••
.................. .. ·.·.·.·.·.·.·.·.·e·.·
•••••••••••••••••• • •••••••••••••••••••••
•••••••• ••••••••••••
........
+
........
----it---6,OOOv
XC2000
XC3000A
XC3100A
1,500-2,500v
4,500-7,OOOv
1,750-5,OOOv
500-900v
250-325v
>2,OOOv
325-600v
700-800v
>2,OOOv
>2,OOOv
>l,OOOv
>2,OOOv
XC4000
4,OOO-8,OOOv
800-900v
XC4000E
4,OOO-8,OOOv
XC4000E
XC5200
4,OOO-6,OOOv
3,OOO-5,OOOv
XC7000
2,OOO-4,OOOv
2,OOO-5,OOOv
pend
pend
pend
250-300v
pend
XC9000
pend
>2,OOOv
At elevated temperatures, 100 mA will not cause latch up. At
room temperature, the FPGA can withstand more than 300
mA without latchup; the EPLD device can withstand more
than 200 mA without latchup. However, to avoid metalmigration problems, continuous currents in excess of 10
mA are not recommended.
>2,OOOv
>2,OOOv
High Temperature Performance
>2,OOOv
Whenever the voltage on a pad approaches a dangerous
level, current flows through the protective structures to or
from a power supply rail (Vee or ground). In addition, the
capacitances in these structures integrate the pulse to provide sufficient time for the protection networks to clamp the
input, avoiding damage to the circuit being protected.
Geometries and doping levels are chosen to provide ESD
protection on all pads for both positive and negative voltages.
11-8
X1825
Figure 4: SCR Model
Although Xilinx guarantees parts.to perform only within the
specifications of the data sheet, extensive high temperature life testing has been done at 145°C with excellent
results.
November 21, 1997 (Version 2.0)
Technical Support and Services
1
Introduction
2
Development System Products and CORE Solutions Products
3
CPLD Products
4
FPGA Products
5
SPROM Products
6
3V Products
7
HardWire FpgASIC Products
8
High-Reliability and QML Military Products
9
Programming Support
10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support and Services
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors
Technical Support Table of Contents
Technical Support And Services
WebLiNX Web Site (www.xilinx.com) ...................................................
Technical and Applications Information ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
File Access and Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Hotline Telephone Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Technical Literature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AppLiNX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XCell Newsletter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Programmable Logic Training Courses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
What You Will Learn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Prerequisites. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Time and Cost Savings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Course Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
M1 Tools Course Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
M1 Update Course. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
M1 Update Course Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
VHDL Seminar (Esperan-Based) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Training Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
International Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
On-Site Courses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
On-Site Courses Provide Additional Benefits: ......................................
Registration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Money-back Guarantee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Enrollment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Cancellations ...............................................................
12-2
12-2
12-2
12-2
12-3
12-3
12-3
12-3
12-3
12-3
12-4
12-4
12-4
12-5
12-5
12-5
12-5
12-6
12-6
12-6
12-6
12-6
12-7
12-7
12-7
Technical Support And Services
November 24,1997 (Version 2.0)
A complete and uniquely accessible offering of worldwide
technical support services is available to Xilinx users.
problems and answer questions right on the spot, and are
contributors to, as well as, users of the Answers database,
accessible at WebLiNX (www.xilinx.com).
Xilinx Field Application Engineers, located at sales offices
and technical support centers worldwide, provide local
engineering support, including design evaluation of new
projects, close consultation throughout the design process,
special training assignments, and new product presentations. Because their role as advisors and troubleshooters
keeps them constantly on the go, they are best used not for
general questions, but for more targeted queries such as
those related to architectural recommendations. The worldwide network of Xilinx sales representatives and distributors also provide local technical support for Xilinx users.
Many different publications assist users in completing
designs quickly and efficiently, including technical manuals,
data sheets, application notes, the AppLiNX CD-ROM (a
regularly-updated collection of the latest application notes
and design hints), and the quarterly XCell newsletter. Most
of these publications are available on the WebLiNX web
site.
For more in-depth support and instruction, a dedicated
training organization conducts technical training classes
worldwide. Courses geared for both novice and experienced users are available.
Technical and applications queries can be directed to
WebLlNX, the Xilinx world wide web site, or the telephone
"hotlines". Xilinx provides 24-hour access to the expert
Answers database, product and applications information,
and a variety of files and utilities via WebLiNX and the file
download areas. Hotline telephone support provides
access to permanent teams of expert Application Engineers located in the United States, United Kingdom,
France, Germany, and Japan. These engineers can handle
The following Technical Support Services are discussed in
more detail in this chapter:
• WebLiNX World Wide Web site
• Internet File Download area
• Hotline telephone support
• Technical literature
• Training Courses
Search the Industry Sites
Search Page
Switch to Xili.rtx Site Search
Currently searching Industry-Wide Sites
Sw:itch to Technical PJlSWEt'"S Search
Finil text
SIww resulJs as
€ Anyv.1here
C In Titles Only
€ Titles and Summaries
C, Titles Only
I
lIP.
Powered by
I{ Verity
Search Tips
Focus Sma..rtSean:h
Select 'Where To Search (Leaving all unchecked searches everything)
EPA _ "
r: Cadence
n Data 110
n Exemplar
CMentor
n OrCAD
n Synano
n Synopsys
r
r
Synplicity
Viewlogic
Milgatbt£s
n EDA Today Newsletter
n EDN
[1 EE Times
D Electronic News
r: IEEE Spectrum
DInt Sys Design
nRTC
O~ltS
r: ecs
r: PREP
n IEEE
n EDAC
n PCI SIG
n DAC
Xilbtx, e/<.
n Xilmx
r: Hamilton
n Insight
nMarslJall
o NuHorizons
C Test & Msrmnt World
r: Others
WebLlNX - The Homepage for Programmable Logic (www.xilinx.com)
November 24, 1997 (Version 2.0)
12-1
Technical Support And Services
WebLiNX Web Site (www.xilinx.com)
•
WebLlNX, the Xilinx World Wide Web site, provides instant
access to the latest information, ranging from Product Overviews, Application Notes, and Data Sheets to investor information and employment opportunities. Designed to provide
users with quick, easy, and intuitive access to the desired
information.
•
•
WebLlNX holds a wealth of Xilinx information, readily available at your fingertips. What's more, SmartSearch, our industry-wide search engine, is the definitive resource for all
Programmable Logic information on the web. SmartSearch
searches over 50 different web sites rich in Programmable
Logic content, providing central access to a vast amount of
data. SmartSearch Agents will watch the Web for you and
inform you via e-mail when new or updated information is
added to any of the sites served by SmartSearch. SmartSearch Agents allow you to stay up-to-date in the rapidly
changing world of Programmable Logic.
New information is constantly being added to the Xilinx site.
The following is a list of some of the technical information now
available on WebLlNX (as of July, 1997):
•
•
•
•
•
•
•
Over 60 Application Notes organized by system type (e.g.,
PCI, DSP, and PCMCIA), function (e.g., memory
functions, arithmetic functions, and busses), component
product family, and application.
Complete and detailed data sheets on all Xilinx products.
Over 1900 records in our Technical Answers database
that contains answers to frequently-asked technical
questions.
Xilinx Product Change Notices and Xilinx Customer
Updates
Access to XCell, our quarterly journal for programmable
logic users.
Software updates and patches.
Links to technical Xilinx presentations via Marshall
Electronics' NetSeminar™ archives.
Expert Journals that provide flow-specific collections of
information including FAQs, Tips, and Hot Topics.
Documents and applications material.
Information about Worldwide Hotline access and
training course availability.
File Access and Transfer
Through the file download areas, users have on-line access to
a variety of useful files, including user manuals, automated
tutorials, design examples, and utilities. Data files can be
exchanged with Application Engineers through a secure area
of the file download area.
Hotline Telephone Support
A network of Technical Support Hotlines provides Xilinx
users with direct telephone access to Xilinx Application
Engineers dedicated to providing resolutions to problems
that may arise during the design process. Xilinx Application
Engineers use many of the same resources and databases
that are now directly available to users via the WebLlNX
web site. Technical questions also can be submitted via fax
or E-mail.
All regions of the world {WebLlNX}:
web site:
North American support:
Hours:
Mon. - Wed., Fri. 6:30 AM - 5:00 PM
Thur. 6:30 AM - 4:00 PM Pacific Time
Hotline:
800-255-7778 or 408-879-5199
Fax:
408-879-4442
hotline@xilinx.com
E-mail:
United Kingdom support:
Hours:
Mon. - Thur.
9:00 AM - 12:00 PM, 1:00 PM - 5:30 PM
Fri.
9:00 AM - 12:00 PM, 1:00 PM - 3:30 PM
Hotline:
(44) 1932-820821
Fax:
(44) 1932-828522
ukhelp@xilinx.com
Technical and Applications
Information
The Answers area of WebLlNX provides access to technical and applications information that assists design engineers in solving problems. The Answers area is accessible
from the Xilinx home page either through the "Answers"
icon or by selecting the "Support" topic. Further, this collection of technical and applications information is immediately accessible through the button bar that is located at the
bottom of every Web page.
www.xilinx.com
E-mail:
France support:
Hours:
Mon. - Fri.
9:30 AM -12:30 PM, 2:00 PM - 5:30 PM
The Answers area provides access to a variety of technical
and applications resources including:
Hotline:
Fax:
•
E-mail:
(33) 1-3463-0100
(33) 1-3463-0959
frhelp@xilinx.com
•
Over 1900 technical solutions and frequently asked
questions.
The File Download Area for access to patches, utilities,
and updates.
12-2
November 24, 1997 (Version 2.0)
----
~~-~-~--
~XIUNX
Germany support:
Hours:
Hotline:
Fax:
E-mail:
Mon. - Thur.
8:00 AM - 12:00 PM, 1:OOPM - 5:00 PM
Fri.
8:00 AM - 12:00 PM, 1:00 PM - 3:00 PM
(49) 89-93088-130
(49) 89-93088-188
dlhelp@xilinx.com
Japan support:
Hours:
Hotline:
Fax:
E-mail:
Mon., Tue., Thur., Fri.
9:00 AM - 5:00 PM
Wed.
9:00 AM - 4:00 PM
(81) 3-3297-9163
(81) 3-3297-0067
jhotline@xilinx.com
Korea support:
Hotline:
Fax:
E-mail:
(82) 2-761-4277
(82) 2-761-4278
korea@xilinx.com
Hong Kong support:
Hotline:
Fax:
E-mail:
(85) 2-2424-5200
(85) 2-2424-7159
hong kong @xilinx.com
Technical Literature
Xilinx offers many different publications to assist users in
completing designs quickly and efficiently. These include
technical manuals, Data Books, data sheets, application
notes, the AppLiNX CD, the XCell newsletter, and The
Answers Database. Most of these publications are available on-line at the WebLiNX web site.
As part of the development system products, Xilinx provides manuals and supporting documents for the development system tools, libraries, CAE tool interfaces, and
related software tools. Many of these manuals are available
on the CD that holds the software as well as in hardcopy
format. On-line help facilities also are an integral part of the
development system products.
AppLiNX
AppLiNX is a collection of current application notes and
other new technical documentation provided on a CD-ROM
for easy reference by the design engineer. All the material
on the CD is provided in Adobe Acrobat format for easy
viewing and printing. The AppLiNX CD is updated regularly
as new material becomes available.
November 24, 1997 (Version 2.0)
XCell Newsletter
XCell, the quarterly journal for Xilinx programmable logic
users, is dedicated to supplying up-tO-date information for
system designers. A typical issue includes descriptions of
new products, updates on component and software availability and revision levels, application ideas, design hints
and techniques, and answers to frequently-asked questions.
To add your name to the XC ell subscription list, please
send your name, company affiliation, and mailing address
to XCell editor, via FAX at 408-879-4676.
Programmable Logic Training
Courses
All users of Xilinx products should attend one of our training
courses. Attending a Xilinx training course is one of the
fastest and most efficient ways to learn how to design with
FPGA devices from Xilinx. Hands-on expert instruction with
the latest information and software will allow you to implement your own designs in less time with more effective use
of the devices. Not only design engineers, but also test
engineers, component engineers, CAD engineers, techniCians, and engineering managers may want to attend the
course in order to understand the Xilinx products.
A variety of courses are offered to meet your specific
needs. Courses are held regularly in centers around the
world, and can even be brought to your own facility.
What You Will Learn
Not only will you learn about our products, but we will recommend the best ways to use the software based on our
years of experience with thousands of designs. You will
learn how to efficiently enter, implement, and verify your
design. You can use the Xilinx automatic mode, or take a
power-user approach and guide the automatic tools to the
best implementation of your design.
12-3
I
Technical Support And Services
Prerequisites
Students need only have a background in digital logic
design. Basic familiarity with the PC or workstation is helpful, but not required. It will benefit you to learn your design
entry tool of choice before attending the Xilinx course.
If you would like to prepare for the training course to maximize your learning, you should complete the tutorials available in the development system.
Benefits
Start or Complete Your Design During the Training Course
Bring your design to the course and consult with the
instructor. Course size is limited to allow more interaction.
You can spend extra time getting your design completed
before returning home. Call to see if your design entry tool
will be available at the course.
Reduce Your Learning Time
Extensive Xilinx documentation and tutorials provide the
information you need to complete your design. But attending the training course for focused, interactive learning is
faster than a question-and-answer approach on your own.
Instead of interruptions and piecemeal self-education, you
will quickly become your company's expert in Xilinx
designs.
tenance and repair costs, and improved customer satisfaction.
Time and Cost Savings
Attending a Xilinx training course is an investment that will
pay for itself with the first Xilinx design that you begin. The
courses are fast-paced, each providing as much information as possible in the short time available. Hands-on experiences throughout the courses make sure that the
information is retained and applied to practical applications.
Just as Xilinx products reduce your development time,
attending a training course can reduce your design time.
The person attending the course will be an in-house expert
who can be utilized by other members of your company.
You can reduce your travel costs by attending a course
scheduled in your area, or having the class brought right to
your facility. The tuition pays for the course notes and
expert, in-person instruction, which can be priceless when
trying to meet a schedule.
Course Descriptions
Hands-On Experience
Each course includes over two hours each day for handson labs. There is at least one computer for every two people in the course.
Platforms
Make Fewer Design Iterations
PC systems using Win95 and NT operational systems.
By learning the proper approach, you will save time and
expense in prototyping and debugging designs. However, if
you do need to make changes to your design, you will learn
how to do this quickly and efficiently.
Instructors
Get to Market Faster
Getting your product to market faster is probably one of the
key reasons you are using Xilinx products. Studies have
shown that time-to-market often has a greater effect on
profits than development costs. Training will allow you to
get your product to market on schedule, allowing your company to reap the rewards that follow.
Lower Production Costs
By learning how to use the device effectively, you may be
able to get more logic into a smaller device, or operate at a
higher speed. As a result, you may be able to save on the
cost of the device itself, and the surrounding logic on your
board.
Increase Quality
Effective verification techniques will prove the quality of
your Xilinx-based design. Higher quality leads to less main-
12-4
Xilinx training courses have been successfully held worldwide for over seven years. The instructors are Xilinx experts
who are skilled at passing that knowledge on to fellow engineers. A dedicated Education organization at Xilinx works
closely with the Applications and Engineering groups to
keep the courses up-to-date with the latest improvements
to Xilinx and third-party tools.
Course Materials
All course materials are supplied by Xilinx. The course
notes are bound for easy use and include additional reference material beyond what is covered in the course.
Most courses include a full lunch, with morning and afternoon snacks. Let the education registrar know if you have
any special dietary needs when registering for a course.
Product Coverage
Xilinx courses cover the latest released versions of our
devices and development systems. New products are
added to the class as they become available. If you have
any questions on coverage of a particular product, please
call Xilinx Customer Education.
November 24, 1997 (Version 2.0)
~XIUNX
FPGA Tools Course Outline
M1 Update Course Outline
This Xilinx training course is two and one-half days in
length. All North American training sites, and most international locations, teach the same course.
•
•
This course is heavily focused on the labs, which feature
Xilinx' Foundation Software.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Introduction
Basic XC4000X Architecture
CPLD Design
- 9500 Architecture/Features
Design Entry
- Design Flow
- Xilinx Libraries/ LogiBLOX Components
Design Manager
- Implementing the design
- Design Flow
Simulation
- Xilinx SimulationNerification
- LogiBLOX Simulation
Configuration
- Options/Methods/Debugging
FPGA Combinatorial Logic Resources
Designing for FPGA Registers
Designing for FPGA Memory
Designing for FPGA I/O
Low Cost FPGA Families
Constraining the Design
- Location/lmplementation
- Timing
Flow Engine Overview
- New Terminology
Custom Options
- MAp, PAR, and Timing Report Options
- Flow Options
- Advanced Operations
M1 Update Course
The. one day course is focused on the latest released products from Xilinx. An update course is available describing
the new features of the M1 release. The course will be
offered for a limited time at regional sites, or can be brought
to your facility. Those customers who have already
attended a Xilinx course or have experience using Xilinx
products should consider attending the one-day M1 Update
training session. These sessions will be most useful if you
have the latest software. Browse the Xilinx Web site for
scheduled courses, orcontact the Xilinx Education Registrar to hold an Update training session at your site.
November24, 1997 (Version 2.0)
•
•
•
•
•
•
Introduction
M1 Release
- Changes
- Future Updates
FPGA Architecture
- Features
- Size
- Power
Tool Usage
- Design Flow
- Options
- Software Strategies
New Features
- Checkpoint Verification
- Constraints
LogiBLOX
LogiCORE/AliianceCORE
Conversion Guidelines
VHDL Seminar (Esperan-Based)
This one day seminar consists of one-half day of presentation and one-half day of hands-on training using the Foundation tools. The seminar is designed to be an introduction,
providing the students with enough training so that they are
conversant with the language and can write simple VHDL
functions.
This course is presented on an as needed basis. Please
contact your local Xilinx or distributor sales office for additional course and schedule information.
The one-day VHDL seminar includes the following
topics:
VHDL Application Introduction
VHDL Language Introduction
Signals and DataTypes
VHDL Operators
Concurrent and Sequential Statements
Writing VHDL for Synthesis
I
The lab exercises presented during the one-day VHDL
seminar consist of:
Familiarization with Xilinx Foundation Series
Synthesis Tool
Familiarization with the DecoderDesign
Writing Your First VHDL Code
Adding the Alarm Signal
Adding a Seven Segment Display Driver
The Alarm Register
A Counter
The Alarm Clock Controller (a State Machine)
12-5
Technical Support And Services
Future Foundation and Synopsys Courses
With the release of the XACTstep version Ml software, the
Xilinx education organization is poised to provide additional
training courses to our customers. A Foundation schematic-entry course and a Synopsys synthesis course will
be offered in the winter 1997 time period. Customers
should call the Xilinx Education Registrar for up-to-date
course schedules and locations.
Training Locations
Xilinx Headquarters
Courses are held regularly at Xilinx headquarters in San
Jose, California. During the class, you may elect to meet
one-on-one with Xilinx Applications engineers to discuss
specific issues not covered in the course. Topics may
include using a specific third-party tool, optimizing your particular design, or more advanced issues beyond the coverage of the course.
On-Site Courses Provide Additional
Benefits:
No Travel Costs
On-site Xilinx training courses eliminate travel time and
expenses:
-
No airfare
No hotel bills
No car rental
Courses Tailored To Your Needs
On-site courses can be tailored to meet the specific needs
of your company:
Convenient course time and location
Projects of a proprietary nature can be discussed
openly
Students can use their own equipment and begin an
actual design right in course
North American Distributor Locations
Costs: North America
Xilinx distributors sponsor training courses jointly with Xiiinx, using the same material as the headquarters courses.
Since the distributor sponsors the course, the tuition cost is
often reduced for customers of the sponsoring distributor.
Check with the distributor when registering. Locations
include over seventy cities across North America. Contact
your local distributor or Xilinx headquarters for information
on courses in your area.
Prices start at $4,500 for a minimum course size of six students. (Prices are subject to change without notice.)
International Locations
Xilinx courses are held! throughout Europe, Japan, Asia,
India, Israel, South Africa, South America, and other international locations. Courses vary in length and tuition, but
are based on the same material used in North America.
Contact your local Xilinx sales office or representative for
information about courses in your area.
On-Site Courses
Xilinx can bring the training course to your own facility for
the greatest convenience to your company. To schedule a
training course at your facility and determine pricing, call
the Xilinx sales office nearest you, or your local Xilinx sales
representative. On-site training courses are popular, so the
more advanced notice we have, the better our ability to
schedule your course exactly when you want it.
12-6
Costs: International
Prices vary; contact your local Xilinx sales
representative. (prices are subject to change without
notice.)
Included in class fees:
-
A Xilinx-certified instructor
Training materials for each student
PC for every two students (or if you prefer, the
training labs can be performed on your PCs or
workstations)
Registration
Tuition
Course tuition in North America is $1,000 per student for
the two and one-half day courses at Xilinx headquarters.
The distributor-sponsored courses are offered at a reduced
rate of $495 for customers of the sponsoring distributor.
Check with the distributor when registering. On-site
courses start at $4,500 per class, and vary according to the
course and the number of students. For specific pricing of
on-site courses, call the Xilinx Education Registrar or your
local sales office. For international locations, call the local
registrar for pricing. (Prices and course schedules are subject to change without notice.)
November 24,1997 (Version 2.0)
- -
-------
~XILlNX
Location
Course Title
Xilinx Headquarters FPGA Tools
M1 Update
Xilinx Sales Office
VHDL Course
North America Distributor Locations FPGA Tools
M1 Update
International
On-Site
Intemational Locations
On-Site
Money-back Guarantee
We are so confident you will be satisfied with the benefits of a
Xilinx training course that we offer the following guarantee:
Full refund of the course cost if you are not completely satisfied.
Enrollment
To enroll in a Xilinx training course, several enrollment
methods are available. The fastest and easiest enrollment
mechanism is the on-line registration via the Xilinx web site
at ..www.xilinx.com ... An alternate method for enrollment is
to contact the registrar at the course location, or for Xilinx
headquarters courses, call (408) 879-5090 or FAX (408)
879-4676 the Education Registrar for additional course
information.
Course size is limited, so early enrollment is recommended. Students are considered enrolled only after a
check, money order, or purchase order for the course
tuition has been received. Please mail your payment to
the registrar of the location of your training class. For Xilinxsponsored courses, make checks/P.O. payable to Xilinx,
Inc.
November 24,1997 (Version 2.0)
Tuition
$1,000
$99
$99
$495
$99
Starts at $4,500
Varies
Varies
··
···
··
·
···
·
Benefits
Can meet with applications engineers
Courses held frequently
All class types available
One-day introduction to VHDL
Courses held frequently; locally
available
Lower cost for Distributor's customers
One-day focus on M1 software release
Convenience; focus on specific issues
Offered in over 21 countries
Native language
Convenience
Can focus on specific issues
Enrollments will be acknowledged with a confirmation letter. We encourage you to sign up early, as courses may fill
up quickly.
Cancellations
Course tuition is fully refundable up to two weeks before the
scheduled course starts. Cancellations within two weeks of
the scheduled course will incur a 25% cancellation fee.
Cancellations within one week of the scheduled course
date may only be applied toward a future course date.
Rescheduling is allowed until three working days before the
start of class. Student substitutions may be made at any
time.
Xilinx Customer Education Registrar
Customer Education Registrar
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
Phone: (408) 879-5090
Fax: (408) 879-4676,
- aUn: Customer Education Registrar
E-mail: customer.training@xilinx.com
Register on-line: hUp://www.xilinx.com
II
12-7
Technical Support And Services
12-8
November 24, 1997 (Version 2.0)
Product Technical Information
1
Introduction
2
Development System Products and CORE Solutions Products
3
CPLD Products
4
FPGA Products
5
SPROM Products
6
3V Products
7
HardWire FpgASIC Products
8
High-Reliability and QML Military Products
9
Programming Support
10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support and Services
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors
Product Technical Information
Table of Contents
Product Technical Information
Product Technical Information Table of Contents .............................. 13-1
XC3000, XC4000, and XC5200: A Technical Overview for the First-Time User ....... 13-5
Choosing a Xilinx Product Family .....•........................••......•.... 13-7
1/0 Characteristics of the 'XL FPGAs. . . . . . . . • . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . .. 13-13
XC4000 Series Technical Information .......•..•.•.........•.........•....... 13-15
XC3000 Series Technical Information .......•................................ 13-19
FPGA Configuration Guidelines .......•..................................... 13-31
Configuring Mixed FPGA Daisy Chains ....................................... 13-39
Configuration Issues: Power-up, Volatility, Security, Battery Back-up ......•...... 13-41
Dynamic Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . .. 13-45
Metastable Recovery ................................•..................... 13-47
Set-up and Hold Times .•.. . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . • • . . . . . . . • . .. 13-50
Overshoot and Undershoot ............................•.................... 13-51
Boundary Scan in XC4000 and XC5200 Series Devices .•......................•. 13-52
Product Technical Information
Table of Contents
XC3000, XC4000, and XC5200: A Technical Overview for the First-Time User
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
User Logic ........................................................................
Logic Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Special Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Inputs/Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Global Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Programming or Configuring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Design Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Design Implementation ....................................................... .
Configuring the FPGA ........................................................ .
Power-up Sequence ....................................................•.
Bit-Serial Configuration ................................................... .
Byte~Paraliel Configuration ................................................ .
Reconfiguration ......................................................... .
Readback of Configuration Data ............................................ .
Quality and Reliability ........................................................ .
13-5
13-5
13-5
13-5
13-5
13-5
13-5
13-5
13-6
13-6
13-6
13-6
13-6
13-6
13-6
13-6
13-6
13-6
Choosing a Xilinx Product Family
Introduction ...........................................................•...........
SRAM-Based FPGAs ...............................................•...............
SRAM-Based FPGAs(XC3000, XC31 00, XC4000, XC5200) ......................... .
Overview of SRAM-Based FPGA Families ........................................ .
Partially-Reconfigurable SRAM-Based FPGA with Bus Interface (XC6200) ............... '
FLASH-Based CPLDs (XC9500) ..................................................... .
Overview of CPLD Families ................................................... .
Selecting the Appropriate Xilinx Family ................................................. .
Type of Logic .......................................................' ....... .
Special Features Required .................................................... .
Further Information .......... '.' ..................................................•..
13-7
13-7
13-7
13-8
13-9
13-9
13-9
13-10
13-10
13-10
13-12
I/O Characteristics of the 'XL FPGAs
Summary ................................................•.......................•
Xilinx Families ....................... " ........................... '........... .
Inputs ................................. '.' .............................. ; ........ .
5-V Tolerant Inputs ...... " .............................................•......
PC I-Compliance ............................................................•
Outputs .................................................................... ; .... .
Sink and Source Capability ......................................... ; .......... .
13-13
13-13
13-13
13-13
13-13
13-14
13-14
13-14
Effect of Additional Capacitive Load ....................... ; ...... , ................•.... 13-14
Transition Time .......... ; .......... '.............. ' ...................... . 13-14
Delay ................................•..........................•..' .... . 13-14
II
13-1
Product Technical Information Table of Contents
XC4000 Series Technical Information.
Introduction .................. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Voltage/Current Characteristics of XC4000-Family Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional Output Delays When Driving Capacitive Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ground Bounce in XC4000 Devices ....................................................
Test Method ................................................................
Interpretation of the Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Guidelines for Reducing Ground-Bounce Effects ....................................
Ground-Bounce vs Delay Trade-Off ....................................................
XC4000 and XC4000E Power Consumption .............................................
13-15
13-15
13-16
13-16
13-16
13-17
13-17
13-17
13-18
XC3000 Series Technical Information
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configurable Logic Blocks............................................................
Function Generator Avoids Glitches. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Input/Output Blocks .................................................................
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
I/O Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Horizontal Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Internal Bus Contention ............ . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Vertical Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Clock Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Power Dissipation. . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Crystal-Oscillator Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Practical Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Series Resonant or Parallel Resonant? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CCLK Frequency Variation. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . ..
CCLK Low-Time Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Battery Back-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Powerdown Operation ............................. . . . . . . . . . . . . . . . . . . . . . . . . . ..
Things to Remember . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Things to Watch Out For ...................................................
Configuration and Start-up ...........................................................
Start-Up. . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Beware of a Slow-Rising XC3000 Series RESET Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
13-19
13-19
13-19
13-20
13-21
13-21
13-22
13-23
13-23
13-23
13-23
13-24
13-24
13-24
13-25
13-25
13-26
13-27
13-27
13-27
13-27
13-28
13-28
13-28
13-28
13-28
13-29
FPGA Configuration Guidelines
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ..
Protection Against Data or Format Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
. Daisy-Chain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Start-Up Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ..
Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Selecting the Best Configuration Mode ............................................
When Configuration Fails. . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
General Debugging Hints for all Families. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
General Debugging Hints for the XC2000 and XC3000 Families. . . . . . . . . . . . . . . . . . . . . . ..
General Debugging Hints for the XC4000 and XC5000 Families. . . . . . . . . . . . . . . . . . . . . . ..
Additional Mode-Specific Debugging Hints for All Families . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Master Parallel Up and Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Master Serial Mode .......................................................
Do Not Let the VPP Pin Float. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Asynchronous Peripheral Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
13-2
13-31
13-32
13-32
13-32
13-34
13-35
13-35
13-35
13-36
13-36
13-36
13-36
13-36
13-36
13-37
~XILINX
Slave Serial Mode ....................................................... .
Daisy Chain Debugging Hints .................................................. .
Potential Length-Count Problem in Parallel or Peripheral Modes ....................... .
Miscellaneous Notes ............................................................... .
13-37
13-37
13-38
13-38
Configuring Mixed FPGA Daisy Chains
Overview ........................................................................ . 13-39
Configuration Issues: Power-up, Volatility, Security, Battery Back-up
Power-Up .................................................................. , .... .
Sensitivity to Vee Glitches .......................................................... .
Design Security ................................................................... .
Design Security when Configuration Data is Accessible ............................. .
Design Security by Hiding the Configuration Data .................................. .
Battery Back-up and Powerdown ..................................................... .
Powerdown Operation ....................................................... .
Things to Remember: .................................................... .
Things to Watch Out for: .................................................. .
13-41
13-41
13-42
13-42
13-43
13-43
13-44
13-44
13-44
Dynamic Reconfiguration
Introduction ...................................................................... .
Important Considerations ........................................................... .
Reconfiguration Time .............................................................. .
Initiating Reconfiguration in Different Xilinx Device Families ................................ .
XC3000 Series ............................................................. .
XC4000 Series and XC5200 Family ............................................. .
FPGAs Can Control Their Own Reconfiguration .......................................... .
13-45
13-45
13-46
13-46
13-46
13-46
13-46
Metastable Recovery
Introduction ...................................................................... . 13-47
Metastability Measurements ......................................................... . 13-48
Metastability Calculations ........................................................... . 13-48
Set-up and Hold Times
Introduction ...................................................................... . 13-50
Overshoot and Undershoot
Introduction ...................................................................... . 13-51
Boundary Scan in XC4000 and XC5200 Series Devices
Introduction ...................................................................... .
Overview of XC4000/XC5200 Boundary-Scan Features ................................... .
Deviations from the IEEE Standard ................................................... .
Boundary-Scan Hardware ........................................................... .
Test Access Port. ........................................................... .
TAP Controller ............................................................. .
The Boundary-Scan Data Register .............................................. .
Bit Sequence ............................................................... .
The Bypass Register ......................................................... .
User Registers ............................................................. .
Using Boundary Scan .............................................................. .
Boundary Scan Instructions ......................................................... .
EXTEST .................................................................. .
SAMPLE/PRELOAD ......................................................... .
ByPASS .................................................................. .
13-52
13-52
13-53
13-54
13-54
13-54
13-54
13-55
13-56
13-56
13-57
13-58
13-58
13-59
13-59
II
13-3
Product Technical Information Table of Contents
USER1, USER2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CONFIGURE ...............................................................
Additional Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
READBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Boundary Scan Description Language Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . ..
13-4
13-59
13-59
13-60
13-61
13-62
13-62
APPLICATION NOTE
XC3000, XC4000, and XC5200:
A Technical Overview for the
First-Time User
XAPP 097 September 12, 1997 (Version 1.1)
Application Note by Peter Alfke
Introduction
There are eight such global low-skew clock. lines in
XC4000, four in XC5200, and two in XC3000 devices.
In the XC3000, XC4000, and XC5200 device families, XiI~
inx offers three evolutionary and compatible generations of
Field Programmable Gate Arrays (FPGAs). Here is a short
description of their common features.
Every Xilinx FPGA performs the function of a custom LSI
circuit, such as a gate array, but the FPGA is user-programmable and even reprogram mabie in the system. Xilinx sells
standard off-the-shelf devices in three families, and many
different sizes, speeds, operating-temperature ranges, and
packages. The user selects the appropriate device and
then converts the schematic or High-Level-Language
description into a configuration data file, using the Xilinx
development system software running on a PC or workstation, and then loads this file into the Xilinx FPGA.
This overview describes two aspects of Xilinx FPGAs:
• what logic resources are available to the user
• how the devices are programmed.
User Logic
Different in structure from traoitional logic circuits, or PALs,
EPLDs and even gate arrays, the Xilinx FPGAs implement
combinatorial logic in smalll09k-uP tables (16 x 1 ~OMs);
each such table either feeds the D-input of a flip-flQP or
drives other logic or 1/0. Each FPGA contains a matrix of
identical logic blocks, usually square, from 8 x 8 in the
XC3020 to 56 x 56 in the XC4085XL. Metal lines of various
lengths run horizontally and vertically in-between these
logic blocks, selectively interconnecting them or connecting
them to the inpuVoutput blocks.
Logic Blocks
This modular architecture is rich in registers and powerful
function generators that can implement any function of up
to five variables. For wider inputs,function generators are
easily concatenated. Generous on-chip buffering makes
logic block delays insensitive to loading by the interconnect
structure, but interconnect delays are layout-dependent
and must be analyzed if they, are performance-critical.
Clocks
Clock lines are well-buffered and can drive all flip-flops with
< 2 ns skew from chip corner to carner, even throughout the
biggest device. The ussr need not ~orry about clock loading or clock~delay balancing, or aboutnold-time issues on
the chip, if the designated global clock lines are used.
XAPP 097 September 12, 1997 (Version 1.1)
Special Features
All devices can implement internal bidirectional busses.
The XC4000- and XC5200-tamily devices have dedicated
fast carry circuits that improve the efficiency and speed of
adders, subtractors, comparators, accumulators and synchronous counters. These families also support boundary
scan on every pin.
XC4000-series devices can use any of their logic-block
look-up tables as distributed RAM, with synchronous write
and dual-port options. This makes FIFOs, shift registers
and DSP distributed multipliers very fast and efficient.
Inputs/Outputs .
All device pins are available as bidirectional user 1/0, with
the exception of the supply connections and three.dedicated configuration pins. All inputs and outputs within each
family have identical electrical. characteristics, but output
current capability varies among families. The outputs on
XC3000 and XC5200 devices always swing rail-to-rail.
XC4000E/EX outputs have a global choice between "TTL =
totem pale" or "CMOS. rail-to-rail" output swing.
=
The original families operate from a5-Vsupply, but have
added 3.3-V variants. These 3.3-V devices, designated by
an "t.:' in their product name, have rail-to-rail outputs.
Inputs of all 5-Vdevices can be globally configured for
either TTL-like input thresholds or mid-rail CMOS thresholds. All 3.3-V devices have CMOS input thresholds (50%
of Vcc). All inputs have hysteresis (Schmitt-trigger action)
of 100 to 200 mV. XC4000XL inputs are unconditionally 5-V
tolerant, even while their supply voltage is as low as 0 V.
This eliminates all power-supply sequencing problems.
Global Reset
All XilinxFPGAs have a global asynchronous reset input
affecting all device flip-flops. In theXC4000- and XC5200farnily devices, any pin can be configured asa reset input;
in XC3000-families, RESeT is adedicated pin.
Power Consumption
Since all Xilinx FPGAs use CMOS-SRAM. technology, their
quiescent or stand-by ~ower consumption is very low, microwatts for XC3000 devices, max 25 mW to 75 mW for the
other 5-V families. The operational power consumption is
totally dynamic, proportional to the transition frequency of
I
XC3000, XC4000, and XC5200: A Technical Overview for the First-Time User
inputs, outputs, and internal nodes: Typical power consumption is between 100 mW and 5 W, depending on device size,
clock rate, and the internal logic structure.
XC3000-family devices can be powered-down, and in this
state their configuration can be maintained by a >2.3 V battery. Current consumption is only a few microamps. The
device 3-states all outputs, ignores all inputs, and resets its
flip-flops, but retains its configuration.
All devices monitor Vee continuously and shut down when
Vee drops to 3 V (2 V for 3.3-V devices). The device then 3states all outputs and prepares for reconfiguration.
Programming or Configuring
Design Entry
A design usually starts as a schematic, drawn with one of
the popular CAE tools, or as a High-Level Language textual
description. Most CAE tools have an interface to the Xilinx
development system, running on PCs or workstations.
Power-up Sequence
Upon power-up, the device waits for Vee to reach an
acceptable level, then clears the configuration memory,
holds all internal flip-flops reset, and 3-states the outputs
but activates their weak pull-up resistors. The device then
initiates configuration, either as a master, (clocking a serial
PROM to receive the serial bitstream or addressing a byteparallel EPROM), or as a slave, (accepting a clock and bitserial or 8-bit parallel data from an external source).
Bit-Serial Configuration
The Xilinx serial PROM is the simplest way to configure the
FPGA, using only three or four device pins. Typical configuration time is around one microsecond per bit, but this can
be reduced by a factor of eight. Configuration thus takes
from a few milliseconds to a several hundred milliseconds.
Xilinx serial PROMs come in sizes from 18,144 to 262,144
bits, and megabit versions are in development. Serial
PROMs can also be daisy-chained to store a longer bitstream.
Design Implementation
Byte-Parallel Configuration
After schematic- or HLL design entry, the logic is automatically converted to a Xilinx Netlist Format (XNF) or EDIF.
The Xilinx software first partitions the design into logic
blocks, then finds a near-optimal placement for each block,
and finally selects the interconnect routing. This process of
partitioning the logic, placing it on the chip, and routing the
interconnects runs automatically, but the user may also
affect the outcome by imposing specific timing constraints,
or selectively editing critical portions of the design, using
the graphic design editor. The user thus has a wide range
of choices between a fully automatic implementation and
detailed involvement in the layout process.
Xilinx FPGA devices can also be configured with byte-wide
data, either from an industry-standard PROM or from a
microprocessor. The FPGA drives the PROM addresses
directly, or it handshakes with the microprocessor like a typical peripheral. The byte-wide data is immediately converted into an internal serial bitstream, clocked by the
internal Configuration Clock (CCLK). Parallel configuration
modes are, therefore, not faster than serial modes. XC5200
devices, however, can also be configured in Express mode,
with byte-wide data at 10 MHz. The largest device,
XC5215, can thus be configured in only 3 ms.
Once the design is complete, a detailed timing report is
generated and a serial bitstream can be downloaded into
the FPGA, into a PROM programmer, or made available as
a computer file.
Configuring the FPGA
The user then exercises one of several options to load this
file into the Xilinx FPGA device, where it is stored in
latches, arranged to resemble one long shift register. The
data content of these latches customizes the FPGA to perform the intended digital function. The number of configuration bits varies with device type, from 14,819 bits for the
smallest device (XC3020) to 1,924,992 bits for the largest
device presently available (XC4085XL). Multiple FPGA
devices can be daisy-chained and configured with a common concatenated bitstream. Device utilizatton does not
change the number of configuration bits. Inside the device,
these configuration bits control or define the combinatorial
circuitry, flip-flops, interconnect structure, and the 1/0 buffers, as well as their pull-up or pull-down resistors, input
threshold and output slew rate.
13-6
Reconfiguration
The user can reconfigure the device at any time by pulling
the PROGRAM pin Low, to initiate a new configuration
sequence. During this process, outputs not used for configuration are 3-stated. Partial reconfiguration is not possible.
For high-volume applications, Xilinx offers lower-cost, fixedprogrammed HardWire versions of these FPGAs.
Readback of Configuration Data
After the device has been programmed, the content of the
configuration "shift register" can be read back serially, without interfering with device operation. XC4000- and
XC5200-family devices include a synchronized simultaneous transfer of all user-register information into the configuration registers.
Quality and Reliability
Since 1985, Xilinx has shipped over 70 million FPGA
devices. Industry-leading quality and reliability (ESD protection, AQL and FIT) and aggressive price reductions have
undoubtedly contributed to this success.
XAPP 097 September 12, 1997 (Version 1.1)
APPLICATION NOTE
Choosing a Xilinx Product Family
XAPP 100 November 10, 1997 (Version 1.2)
Application Note by Peter Alfke
Summary
This Application Note describes the various Xilinx product families. Differences between the families are highlighted. The
focus of the discussion is how to choose the appropriate family for a particular application.
Xilinx Families
XC3000, XC4000, XC5000, XC6000, XC9000
Table of Contents
SRAM-Based FPGAs
SRAM-Based FPGAs
Xilinx SRAM-based FPGAs fall into two distinct categories.
All are reconfigurable and can be programmed in-system;
only the XC6200 family can be partially reconfigured and
offers a built-in microprocessor interface. The two categories of devices are separately described below.
FLASH-Based CPLDs
Selecting the Appropriate Xilinx Family
Introduction
Xilinx offers Field-Programmable Logic circuits, mass-produced standard integrated circuits that the user can customize for the specific application.
Xilinx products offer the following advantages:
•
•
•
•
High integration (less space, lower power, higher
reliability, lower cost) than solutions based on existing
standard devices like MSI and PALs.
No non-recurring engineering charges and associated
risk, typically required for mask-programmed gate array
solutions.
Fast design time and easy design modification,
important for early time-to-market.
Designs can be upgraded in the field for added
functionality.
Some potential users might be confused by the wide diversity of Xilinx product offerings. This application note provides a broad overview from the user's perspective.
Xilinx offers programmable logic circuits in two distinctly different technologies.
•
SRAM-based FPGAs, the original Xilinx offering, now
encompassing the XC3000, XC4000, XC5200, and
XC6200 series and their sub-families, like the
XC3000A, XC3000L, XC3100A, XC4000E, XC4000EX,
and XC4000XL.
Flash-based complex PLDs, the XC9500 family.
XAPP 100 November 10, 1997 (Version 1.2)
SRAM-Based FPGAs (XC3000, XC31 00,
XC4000, XC5200)
These families represent an ongoing evolution of the original Xilinx FPGA architecture, characterized by structural
flexibility and an abundance of flip-flops. Logic is implemented in look-up tables, and is interconnected by a hierarchy of metal lines controlled by pass transistors.
Attractive systems features include on-chip bidirectional
busses and individual output 3-state and slew-rate control,
common reset for all flip-flops, and multiple global low-skew
clock networks.
The configuration can be loaded while the devices are connected into a system, and can be changed an unlimited
number of times by reloading the "bitstream," the series of
bits used to program the device. Configuration must be
reloaded whenever Vcc is re-applied. Reconfiguration
takes 20 to 200 ms, during which time all outputs are inactive.
Static power consumption is very low, down to microwatts
for some of the families. Dynamic power consumption is
proportional to the clock frequency, and depends on the
logic activity inside the device and on the outputs.
The description "SRAM-based" refers primarily to the standard high-volume manufacturing process, and secondarily
to the fact that configuration data is stored in latches. Different from typical SRAMs, these latches use low-impedance
active pull-up and pull-down transistors. An on-Chip voltage
monitor 3-states the outputs and initiates reconfiguration
when Vcc drops significantly (to 3.2 V in a 5V system).
13-7
I
Choosing a Xilinx Product Family
These FPGAs are available in different sizes and many different packages. Usually each device type is available in
many package types. Any package can accommodate different sized devices with compatible pinouts, so the user
can migrate to a larger or smaller device without changing
the PC-board layout.
Overview of SRAM-Based FPGA Families
XC3100A devices are functionally and bitstream identical
with the XC3000A, and are available in the same packages
with the same pinouts. The only difference is the higher
speed of the XC31 OOA, with a look-up table delay of 1.5 to
4 ns, and the slightly higher standby current of 8 to 14 mAo
One additional high-end family member, the XC3195A, can
implement up to 9,000 gates and 1,320 flip-flops.
•
XC2000: Soon to be obsoleted, do not use for new designs.
The XC3000 or XC5200 FPGA families or the XC9500
CPLD family, may be an alternative.
XC2000L: 3.3V version of XC2000; soon to be obsoleted,
do not use for new designs. Use the XC3000L instead.
XC3000: Superseded
Don't use this venerable family for new designs, since it has
been superseded by the improved, but fully backwards
compatible, XC3000A family.
•
Use for high performance design with system clock
rates up to 100 MHz.
Accept lack of dedicated carry circuits, resulting in less
efficient and possibly slower arithmetic and counters
than in XC4000E. No on-chip RAM; data storage is thus
limited to the available 256 to 1,320 flip-flops.
XC3100L: 3.3V version of XC3100A
•
•
Use for 3.3V applications.
Accept significantly slower speed at 3.3V, compared to
XC3100A at 5V, as well as higher quiescent power and
much higher powerdown current than XC3000L at 3.3V.
XC3000A: Newest version of the popular XC3000 family
XC4000: Superseded
Five device types cover a complexity range from 1,300 to
7,500 gates, with 256 to 928 flip-flops. Logic is implemented in 4-input look-up tables; two tables can be combined to implement any logic function of five variables with
only one combinatorial delay of 4 or 5 ns. Flip-flop toggle
rate is over 110 MHz.
Don't use this family for new designs, since it has been
superseded by the improved, but fully backwards compatible XC4000E family.
Global choice of input thresholds (1.2 V or 2.5V), output
slew-rate control, and an on-chip crystal oscillator circuit
are attractive system features.
•
Use for medium-speed, medium-complexity
applications.
Accept lack of dedicated carry circuits, resulting in less
efficient and slower arithmetic and counters than in
XC4000E families. No on-chip RAM; data storage is
thus limited to the available 256 to 928 flip flops.
XC3000L: 3.3V version of XC3000A
•
Use for battery-operated applications.
Accept significantly slower speed at 3.3V, compared to
XC3000A at 5V.
XC31 00: Superseded
Don't use this family for new designs, since it has been
superseded by the improved, but fully backwards compatible XC31 OOA family.
XC4000A: Superseded
Don't use this family for new designs, since it has been
superseded by the improved, faster, less expensive, and
pinout-compatible - but not bitstream-compatible XC4000E family.
XC4000E: Enhanced superset of the XC4000 family
The XC4000E family is recommended for new designs.
The ten devices in this family stretch from 2,000 to 25,000
gate complexity. The emphasis is on systems features and
speed. The function generators are more versatile than in
the XC3000-Series parts, and there is a dedicated carry
network to speed up arithmetic and counters and make
them more efficient. Most importantly, the function generators can be used as user RAM with asynchronous or synchronous write addressing, even as dual-port RAMs. This
capability makes register files, shift registers and especially
FIFOs faster and much more efficient than in any other
FPGA. Dedicated carry logic can speed up wide arithmetic
and long counters.
•
XC3100A: Newest version of the popular high-speed
XC31 00 family
•
13-8
Use for general-purpose logic and data-path logic that
can take advantage of internal busses and fast
arithmetic carry logic. Use for on-chip distributed RAMs,
e.g. >50-MHz FIFOs up to 64 deep, 32 bits wide.
Accept lack of crystal oscillator circuitry and lack of
Powerdown feature.
XAPP 100 November 10, 1997 (Version 1 .2)
---------
~XILlNX
XC4000EX: Larger version of the XC4000E family.
Extension of the XC4000E family from 28k to 36k gates,
with greatly increased routing resources, faster clocking
options and more versatile output logic.
o
Use for designs beyond 20,000 gate complexity.
XC4000H: High 1/0 - count version of XC4000. Soon to be
obsoleted, do not use for new designs.
o
Consider XC5200 as a lower-cost alternative when
internal RAM is not required.
Partially-Reconfigurable SRAM-Based
FPGA with Bus Interface (XC6200)
This new fine-grained architecture is very different from the
other Xilinx families. It offers partial and very fast reconfigurability, supported by an 8/16/32 bit wide microprocessor
bus interface. This interface can directly write to and read
from any internal cell, and can even treat part of the internal
configuration as user RAM.
o
XC4000XL: 3.3V FPGA
Complete family stretching from 5000 gates to > 100,000
gates. Basic features are identical to the XC4000E but with
additional routing resources and 5V tolerant input, even
when Vcc is <3.0V.
o
Use for 3.3V designs.
XC5200: Low-cost FPGA
New architecture optimized for low cost, good routability,
and the ability to lock pinout while internal logic is being
modified. Dedicated carry structure similar to XC4000, but
no RAM. Four-input function generators avoid the XC3000
input constraints. lOBs are less rigidly coupled to the internal matrix of CLBs and interconnects, which greatly
improves the flexibility of pin-locked designs. lOBs have no
flip-flops.
The XC5200 family offers the lowest cost per gate of all Xilinx FPGAs, wheneveJ RAM is not required.
Performance is similar to XC3000A, but dedicated carry
logic can speed up wide arithmetic and long counters.
o
o
Use for medium-speed general-purpose logic, and for
data-path logic that can take advantage of internal
busses and fast arithmetic carry logic. Alternative to
XC3000A at lower cost, and with additional benefits,
such as dedicated carry for arithmetic and counters,
improved routing, and ability to cope with locked pinout.
High 1/0 count. Package pinout compatible with
XC4000.
Accept lack of internal RAM and lack of crystal
oscillator circuitry.
FLASH-Based CPLDs (XC9500)
These devices are extensions of the popular PAL architecture, implementing logic as wide AND gates, ORed
together, driving either a flip-flop or an output directly. The
simple logic structure makes these devices easy to understand, and results in both fast design compilation and short
pin-to-pin delays. Wide input gating and fast system clock
rates up to 150 MHz are attractive features for state
machines and complex synchronous counters.
The XC9500 in-system programmable family, based on
FLASH technology, .eliminates the need for a separate programmer. These new devices also offer boundary scan
(JTAG) to simplify board testing.
Overview of CPLD Families
XC7300: Superseded
Do not use for new designs. Use XC9500 instead,
XC9500: FLASH-Based CPLD
Six devices cover the range from 36 to 288 macrocells.
The new XC9500 family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration.
o
o
o
XAPP 100 November 10, 1997 (Version 1.2)
Use for innovative reconfigurable-processor solutions,
and for general purpose solutions where fast
{re)configuration is an advantage, or for registerintensive, datapalh-oriented, highly structured designs.
Delays are deterministic, and compile times are very
short.
Use for high-speed logic, short pin-to-pin delays, for
state machines and flexible address decoding, and as
PAL replacement.
Accept higher power consumption and fewer available
flip-flops compared to SRAM FPGA.
13-9
I
Choosing a Xilinx Product Family
Selecting the Appropriate Xilinx Family
It is not always obvious which Xilinx family is the "right"
choice for a particular application. To make a decision, start
with the known data, the target application. Then address
the following questions:
•
•
What type of logic is used in the application?
What special features are required?
Type of Logic
All Xilinx devices are general-purpose. Any family can
implement any type of logic. There are, however, some features that make certain families more appropriate than others. The following items should be interpreted as "soft"
suggestions, not as absolute, unequivocal choices.
1. For shortest pin-to-pin delays and fastest flip-flops:
Use XC9500, or, if fan-in is sufficient, XC31 OOA, XC4000E/
EX/XL.
XC9500 CPLDs have a PAL-like AND/OR structure that is
inherently very fast. XC3100 has extremely fast logic
blocks, but the single-level fan-in is limited to five.
XC4000E/EXlXL have slower logic blocks, but a wider fanin of nine. XC4000EX/XL FPGAs offer a very fast pin-to-pin
path using a fast buffer and a 2-input function generator in
the lOB.
2. For fastest state machines:
For encoded state machines, use XC9500.
For "one-hot" state machines, use XC3100A, XC4000E/
EX/XL, XC5200.
3. For fast counters/adders/subtractors/accumulators/
comparators:
Use XC4000E/EX/XL, XC5200 or XC9500 for wide functions.
Use XC31 OOA for very fast, but short or simple counters.
XC4000E/EXlXL and XC5200 have dedicated carry-logic
that is most effective over the range of 8 to 32 bits.
XC3100A achieves high speed for short word-length and
simple operations (such as non-Ioadable counters) through
its extremely fast logic blocks.
4. For I/O-intensive applications with a high ratio of I/O
to gates:
XC6200 achieves fast compilation through its ASIC-like
small granularity, which requires no logic partitioning effort.
6. For lowest cost per gate, when on-chip RAM is not
required:
Use XC5200, XC3000A.
7. For pinout compatibility within and between families:
Use XC4000E/EXlXL, XC5200.
These families are carefully designed to fit the same pinout
in any given available package. This allows easy migration
to different device sizes or families in the same package.
The user can add logic or streamline the design or even
use a less costly or faster family without any need to
change the existing PC-board layout.
8. For Digital Signal Processing (multiply-accumulate)
applications:
Use XC4000E/EX/XL.
The look-up-table architecture and the dedicated carry
structure are very efficient for distributed arithmetic, a fast
and effective way to implement fixed-point multiplication in
digital filters.
Special Features Required
The sixteen items below describe specific features and
characteristics available only in the listed families. These
are, therefore, "hard" selection criteria.
9. For on-chip RAM:
Use XC4000E, XC4000EX, XC4000XL, or XC6200.
XC4000E/EXlXL has many 16x1 or 32x1 RAMs with synchronous or asynchronous write and dual-port capability.
XC6200 can implement an arbitrary portion of the configuration-memory space as user RAM.
10. For on-chip (bidirectional) bussing:
Use XC3000A, XC3100A,
XC4000XL, XC5200, XC9500.
XC4000E,
XC4000EX,
XC3000A, XC3100A, XC4000, and XC5200 families have
horizontal Longlines that can be driven by internal 3-state
drivers.
Use XC5200.
XC9500 devices implement busses indirectly using the
wired-AND capability in the switch matrix.
5. For shortest design compilation time:
11. For on-chip crystal oscillator circuitry:
Use XC9500, or XC6200.
Use XC3000AlL, XC3100AlL.
XC9500 achieves fast compilation through the simplicity of
its PAL-like architecture.
The on-chip circuit is just a dedicated single-stage inverting
amplifier that can be configured between two dedicated
pins. It is not recommended for designs requiring very low
power consumption or crystal frequencies below 1 MHz.
13-10
XAPP 100 November 10, 1997 (Version 1.2)
- - - - - -
---------
~XILlNX
12. For very fast or partial reconfiguration, and for a
dedicated microprocessor interface:
XC4000E/EX/XL can be configured with a global choice of
either totem-pole or rail-to-rail outputs.
Use XC6200.
18. For 3.3V operation:
All other SRAM-based families must be completely reconfigured.
Use XC3000L, XC4000L, XC4000XL.
19. For 5V operation Interfacing with 3.3V devices:
13. For non-volatile single-chip solutions:
Use XC9500 or XC4000E/EX.
Use XC9500 or any HardWire device.
The SRAM-based devices require an external configuration
source, which may be contained in the microprocessor's
memory. XC3000A and XC3000L devices can be used with
a battery-backed-up supply, thus eliminating the need for
external configuration storage.
14. For lowest possible static power consumption at 5V:
Use XC3000A and, to a lesser extent, XC5200, XC4000E,
XC4000EX.
For Icc down to a few microamps, use XC3000AlL in powerdown. The other families consume a few milliamps.
Configurations for CMOS input thresholds on all inputs
reduce supply current significantly.
15. For avoiding pin-locking problems with routingintensive designs:
Use XC9500, XC4000EX, XC4000XL, XC5200.
XC9500 devices have special architectural features to
enable pin locking.
XC4000EX, XC4000XL, and XC5200 provide additional
routing channels, called VersaRing, between the core logic
and the I/O.
16. For Boundary-Scan support:
Any XC4000E/EXlXL "totem-pole" output drives 3.3V
inputs safely, and the TTL-like input threshold can be driven
from 3.3V logic.
20. For In-system programmability:
Use all Xilinx families.
21. For PCI compatibility:
Use XC4000E/EXlXL and XC9500.
Target and Initiator designs are available for the XC4000E.
22. For Hi-Rei, military, or mil temperature-range
applications:
Use XC3000, XC3100A, XC4003A, XC4005, XC4010,
XC4013.
23. For battery-operated applications requiring low
stand-by current:
Use XC3000AlL, XC4000E/EX, XC5200, XC6200.
XC3000L devices have inherently very low static power
consumption.
XC3000A devices can use powerdown to ignore all input
activity and tolerate Vcc down to 2.3V, while maintaining
configuration.
17. For rail-to-rail output voltage swing at 5V Vcc:
XC4000E/EX must be configured for CMOS input thresholds, and the user must shut down clock and logic activities
externally.
Use XC3000A, XC3100A,
XC4000XL, XC5200, XC6200.
24. For best protection against Illegal copying of a
design (design security):
Use XC4000E, XC4000EX, XC4000XL, XC5200, XC9500.
XC4000E,
XC4000EX,
(In XC4000/E/EXlXL, rail-to-rail is a user-option.)
Use XC9500 with security bit activated.
XC4000 and XC9500 have a "totem-pole" output structure
with lower Voh.
Use XC3000A or XC3000L with powerdown battery-backup configuration.
XAPP 100 November 10, 1997 (Version 1.2)
13-11
I
Choosing a Xilinx Product Family
Further Information
For further information on any of the Xilinx products discussed in this application note, see the Xilinx WEBLINX at
http://www.xilinx.com. or call your local sales office.
Table 1: Selecting a Xilinx Family
Feature
c(
0
0
0
....I
0
0
(')
><
c(
0
0
....I
0
0
,..
,..
(')
(')
(')
~
0
0
8
><
><
W
><
W
....I
><
0
0
0
....I
0
0
0
0
0
0
0
0
0
"'"
><
0
"'"
><
0
"'"
><
0
0
"'><"
0
0
0
0
N
N
0
0
It)
><
1. Shortest pin-to-pin
X
X
X
X
2. Fastest state machines
X
X
X
X
X
3. Fastest arithmetic counters
X
X
X
X
\I)
><
X
6. Lowest cost, no RAM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
9. RAM
10. Bidirectional busses
X
X
X
X
11. Crystal oscillator
X
X
X
X
X
X
X
X
X
15. Tolerates pin-locking
X
X
18. 3.3V operation
19. 5V out drives 3.3V
20. In-system programmable
X
X
X
X
23. Low standby current
X
X
24. Design security
X
X
13-12
X
X
X
X
X
X
X
X
X
option
X
X
X
X
option
X
21. PCI-compatible
22. Hi-rei, mil, mil-temp
X
X
X
13. Non-volatile/single chip
16. Boundary scan
17. Full-swing 5V output
><
X
12. FasVpartial configuration
14. Low power @ 5V
01
X
X
8. DSP (multiply/accumulate)
It)
0
X
4. High I/O to gate ratio
5. Fastest compilation
7. Footprint compatible families
0
0
option
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
option
X
X
X
X
X
X
X
X
X
X
X
XAPP 100 November 10, 1997 (Version 1.2)
APPLICATION NOTE
1/0 Characteristics of the 'Xl FPGAs
XAPP 088 November 24, 1997 (Version 1.0)
Application Note by PETER ALFKE and BOB CONN
Summary
Data sheets describe I/O parameters in digital terms, providing tested and guaranteed worst-case values. This application
note describes I/O parameters in analog terms, giving the designer a better understanding of the circuit behavior. Such
parameters are, however, not production-tested and are, therefore, not guaranteed.
Xilinx Families
XC4000XL, XC4000XV, and Spartan-XL
Inputs
Input threshold, the voltage where a 0 changes to a 1 and
vice versa, is stable over temperature, but proportional to
Vee:
37 to 38% of Vee for the falling threshold, 39 to 42% for the
rising threshold. There is 50 mV to 150 mV of hysteresis,
smallest at hot and high Vee, largest at cold and low Vee.
5-V Tolerant Inputs
Currently, many systems use a mixture of older 5-V devices
and newer 3.3-V devices. This can pose a problem when a 5V logic High drives a 3.3-V input. See Figure 1.
Oil most CMOS ICs each signal pin has a clamp diode tQ Vee,
to protect the circuit against electrostatic discharge (ESD).
This diode starts conducting when the pin is driven more than
0.7 V positive with respect to its Vee. In mixed-voltage sys~
tems, this diode presents a problem since it might conduct
tens of milliamps whenever a 5-V logic High is connected to a
3.3Vinput.
In the XC4000XLlXV and SpartanXL devices, Xilinx has overcome this difficulty by eliminating the clamp diode between the
device pins and Vee. The pins can thus be driven as High as
5.5 V, irrespective of the actual supplyvoltage on the receiving
input. These devices are, therefore, unconditionally 5-V tolerC
ant, and the user can ignore all interface precautions, and
need not worry about power sequencing.
Excellent ESD protection (up to several thousand volts) is
achieved by means of a patented diode-transistor structure
that connects to ground, and not to Vee. The structure
behaves like a Zener diode; it becomes conductive at >6 V
and diverts the charge or current directly to ground. It can handle current spikes of several hundred milliamps, but continuous current must be kept below 20 mA to avoid reliability
problems caused by on-Chip metal migration.
See also the application note "Supply-Voltage Migration, 5 V
to 3.3 V', XAPP080, available at www.xilinx.com.
PCI-Compliance
The 'XL-I/O is designed to be PCI compliant and also to be
5-V tolerant.
.
• 3.3-V PCI compliance requires a clamping diode to Vee.
• 5-V PCI compliance does not explicitly require such a
diode, but requires passing the specified PCI overshoot
'test.
• 5-V tolerance does not permit such a diode.
To satisfy these conflicting requirements, an internal diode
is added to each output, with its cathode connected to an
internal VTT rail. See Figure 2.
-----------
M
0
S
3.8
T
VOH
VOH
T
L
2.4
~
S.VDevlce
VOL
0.4
)(7167
Figure 2: Interface Levels
XAPP 088 November 24, 1997 (Version 1.0)
Figure 3: Simplified 'XL:-UO Structure
13-13
I
VO Characteristics of the 'XL FPGAs
In the PC I-compliant XC4000XLT devices, this rail is internally bonded to eight device pins which externally must be
connected to the appropriate Vee supply (5 V or 3.3 V).
Effect of Additional Capacitive Load
In all other 'XL devices, the Vn rail is internally left unconnected, thus assuring 5-V tolerance.
At the specified 50 pF external load, the rise time is 2.4 ns,
and the fall time is 2.0 ns. For additional capacitive loads,
add 60 ps/pF to the rise time, and 40 ps/pF to the fall time.
Outputs
Transition Time
Delay
Sink and Source Capability
The IBIS files describe the strength of the CMOS output
drivers as black boxes, giving only voltage/current values
without revealing proprietary circuit details. IBIS gives an
unnecessarily large set of numbers, when most users just
want to know the strength of the pull-down transistor (sink
capability) and the pull-up transistor (source capability).
Close to either rail, the outputs are resistive, i.e. voltage is
proportional to current.
Table 1 condenses the information and expresses it as output resistance in Ohm for a sink voltage less than 1 V above
ground, and a source voltage less than 1 V below Vee.
(Data based on SPICE simulation).
Table 2: Sink and Source Capability
Device Family
XC4000E
XC4000EX
XC4000XL/XV
Spartan-XL
Optional on all
XC4000XV'
Source
Sink
Resistance to Resistance to
GND
VCC
22.1-27.7
Ohm
53.3 - 90.5
Ohm
14.4 - 18.8
48.0 - 58.7
14.4 - 20.5
28.0 - 41.0
Ohm
8.0 - 12.0'
20.0 - 30.0'
Ohm
Add 30 ps/pF to the rising-edge delay at 3.0 V.
Add 23 ps/pF to the riSing-edge delay at 3.6 V.
Add 25 ps/pF to the falling-edge delay at any voltage.
The values were derived from XC4028XL measurements
using the fast output option, but the slew-rate limited output
option behaves almost identically.
These results are consistent with the IBIS-derived output
impedance, since the delay increases with approximately
one RC time constant, and the rise and fall times increase
each with approximately two time constants.
These are not guaranteed and tested parameters; they are
established by measuring a few devices. Xilinx, therefore,
suggests that the user add a 20% guardband (multiply by
1.20) when calculating additional delay due to capacitive
load above the guaranteed test limit of 50 pF.
For the same reason, subtract 20% (multiply by 0.80) when
calculating the delay reduction due to a capacitive load that
is less than 50 pF external. See Figure 4.
When comparing Xilinx numbers to those from other vendors
who use 35 pF as a standard load, reduce the Xilinx-specified
delay by 0.4 ns. Reduce the Xilinx-specified rise time by 1.0
ns and the fall time by 0.6 ns, thus changing both to 1.4 ns.
Example:
For an external lumped capacitive load of 200 pF, the risingedge delay at 3.0 V increases by 1.2 • 150 • 30 = 5.4 ns
over the guaranteed data sheet value.
• This per-pin option will also be available on all XC4000XL
and Spartan-XL devices later in 1998.
The rising-edge transition time increases by an amount of
1.2 • 150 pF • 60 ps/pF = 10.8 ns over the 50-pF transition
time of 2.4 ns. The rise time is thus 13.2 ns.
200
180
160
3
140
120
~ 100
80
/
40
o/
-
,..
/~
./
60
20
/
2
~
..........
2
.......
Volts
,
.........
3
4
Figure 4: Output VoltageJ
Current Characteristics (default for XC4000XL,
5
...... " ,
1/
~"
V
-1
X7166
-2
o
20
~
W
00
100
Capacitance (pF)
1~
1~
X7169
Figure 5: Additional Delay at Various Capactive Loads
13-14
XAPP 088 November 24, 1997 (Version 1.0)
APPLICATION NOTE
XC4000 Series
Technical Information
XAPP 045 November 24, 1997 (Version 1.1)
Application Note
Summary
This Application Note contains additional information that may be of use when designing with XC4000 Series devices. This
information supplements the product descriptions and specifications, and is provided for guidance only.
Xilinx Family
XC4000/XC4000E/XC4000EXlXC4000L
Introduction
This application note describes the electrical characteristics of the output drivers, their static output characteristics
or IIV curves, the additional delay caused by capacitive
loading, and the ground bounce created when many outputs switch simultaneously.
Voltage/Current Characteristics of
XC4000-Family Outputs
Figures 1 and 2 show the output source and sink currents,
both drawn as absolute values. Note that the XC4000E/EX
families offer a configuration choice between an n-channel
only, totem~pole like output structure that pulls a High output
to a voltage level that is one threshold drop lower than Vee,
and a conventional complementary output with a p-channel
transistor pulling to the positive supply rail. When driving
inputs that have a 1.4-V threshold, the lower VOH of the
totem-pole ("TTL.:') output offers faster speed and more symmetrical switching delays.
These curves represent typical devices. Measurements
were taken at nominal Vee, TA = 25°C. These characteristics vary by manufacturing lot, and will be affected by future
changes in minimum device geometries. These characteristics are not production-tested as part of the normal device
test procedure; they can, therefore, not be guaranteed.
Although these measurements show that the output sink
and source capability far exceeds the guaranteed data
sheet limits, continuous high-current operation beyond the
data sheet limits can cause metal migration of the on-chip
metal traces, permanently damaging the device. Output
currents in excess of the data-sheet limits are, therefore,
not recommended for continuous operation. These output
characteristics can, however, be used to calculate or model
output transient behavior, especially when driving transmission lines or large capacitive loads.
I
Volts
Figure 1: Output Voltage/Current
Characteristics
for XC4000E
XAPP 045 November 24, 1997 (Version 1.1)
X5292
X5291
Figure 2: Output Voltage/Current Characteristics
for XC4000XL
13-15
XC4000 Series Technical Information
Ground Bounce in XC4000 Devices
Additional Output Delays When
Driving Capacitive Load
Xilinx Product Specifications in chapter 4 give guaranteed
worst-case output delays with a 50-pF load.
The values below are based on actual measurements on a
small number of mid-93 production XC4005-5, all in PQ208
packages, measured at room temperature and Vee = 5.5 V.
Listed is the additional output delay, measured crossing 1.5
V, relative to the delays specified in this Data Book.
These parameters are not part of the normal production
test flow, and can, therefore, not be guaranteed.
Table 1 : Increase in Output Delay When Driving Light
Capacitive Loads «150 pF)
High-to-Low
Low-to-High
10
50
100
10
50
100 pF
Slow
-1.6
1.4 -1.4
1.2 -1.2
O'
O'
ns
-1.6
O'
O'
1.4
Fast
1.1
ns
Slew
Mode
XC4000
Note:
'Zero by definition
Table 2: Increase in Output Delay When Driving Heavy
Capacitive Loads (> 150 pF)
XC4000
High-toLow
Low-toHigh
Slow
1.7
1.2
ns/l00 pF
Fast
1.5
1.2
ns/l00 pF
Example:
~T
High-to-Low for XC4005-5 with Fast-mode output driving 250 pF:
1.2 ns (from Table 1) plus (250-100) pF • 1.5 ns/l00 pF
Total propagation delay, clock to pad:
TOKPO F + 3.45 ns = 7.0 ns + 3.45 ns = 10.45 ns
Vee bounce is not as important as ground bounce,
because it is of lower magnitude due to the weaker pull-up
transistors. Also, the noise immunity in the High state is
usually better than in the Low state, and input levels are referenced to ground, not Vee. All this is the result of our
industry's TTL heritage.
Test Method
Slew Mode
= 1.2 ns + 2.25 ns = 3.45 ns
Ground-bounce is a problem with high-speed digital ICs,
when multiple outputs change state simultaneously causing undesired transient behavior on an output, or in the
internal logic. This is also referred to as the Simultaneous
Switching Output (SSO) problem. Ground bounce is primarily due to current changes in the combined inductance of
ground pins, bond wires, and ground metallization. The ICinternal ground level deviates from the external system
ground level for a short duration (a few nanoseconds) after
multiple outputs change state simultaneously. Ground
bounce affects outputs that are supposed to be stable Low,
and it also affects all inputs since they interpret the incoming level by referencing it to the internal ground. If the
ground bounce amplitude exceeds the actual instantaneous noise margin, then a non-changing input will be
interpreted as a short pulse with a polarity opposite to the
ground bounce.
Data was taken on XC4005-5, devices in the PQ208 package, soldered to the Xilinx Ground Bounce Test Board. Pin
82, two pins away from the nearest ground pin, was configured as a permanently Low output driver, effectively monitoring the internal ground level. The simultaneously
switching outputs were on pins 80 and 83, for two outputs
switching; additionally, pins 80 and 86 were used for four
outputs switching. The closest ground pins are 79 and 90.
Four ground-bounce parameters were measured at room
temperature, with Vcc set at 5.5 V as shown in Figure 3.
•
VOLP-HLPeak ground noise when switching High-to-Low
•
•
VOLV-HLValley ground noise when switching High-to-Low
VOLP-LHPeak ground noise switching Low-to-High
•
VOLV-LHValley ground noise switching Low-to-High
All four parameters can affect system reliability.
~~------V~",\~____________________________~~r-----------VOH
'------- VOL
VOLV-LH
X5299
Figure 3: Ground Bounce
13-16
XAPP 045 November 24, 1997 (Version 1.1)
-------~~~~
~XILlNX
The two positive peak values can cause problems with a
signal leaving the ground bounce chip, driving another chip.
The positive ground bounce voltage is added to the VOL,
and may exceed the receiving input's noise margin. A continuously logic Low input may thus be interpreted as a
short-duration High pulse.
the slew-rate mode of these outputs. Switching outputs
closer to the monitoring output also cause larger peaks and
valleys than outputs further away.
The two negative valley parameters can cause problems
with a signal arriving at the ground-bounce chip, reducing
the Low-level noise immunity. The incoming voltage may
not be Low enough, and may, therefore, be interpreted as a
short-duration High input pulse.
•
Table 3: Ground Bounce, 16 Outputs Switching, Each
With 50 or 150 pF Load, Vee = 5.5 V
Load
16x50pF
16 x 150 pF
Slew
Rate
Slow
Fast
Slow
Fast
High-to-Low
VOLP VOLV
670
480
1,170 710
740
330
1,180 420
Low-to-High
Unit
VOLP VOLV
240
240 mV
480
660 mV
210
280 mV
710 mV
350
Interpretation of the Results
Ground bounce is a linear phenomenon. When multiple outputs switch, the total ground bounce is the sum of the
ground-bounce values caused by individual outputs switching. Since the actual switching of multiple outputs is usually
not quite simultaneous, small timing differences between the
switching outputs, caused by routing delays, can indirectly
affect the amplitude. With low capacitive loading, < 50 pF, the
peaks and valleys might even partially cancel each other.
With larger capacitive loads, the tendency is for valleys to
combine with valleys and peaks to combine with peaks.
Guidelines for Reducing Ground-Bounce
Effects
Minimize the impedance of the system ground
distribution network and its connection to the IC pins.
PQFPs are best suited, PGAs are worst, and PLCCs are
in-between.
• Use PC-boards with ground- and Vee-planes, connected
directly to the ICs' supply pins. Place decoupling
capacitors very close to these ground and Vee pins.
Keep the ground plane as undisturbed as possible. A row
of vias can easily cause a dynamic ground-voltage drop.
• Keep the clock inputs physically away from the outputs
that create ground bounce, and connect clocks to input
pins that are close to a ground pin. Make sure that all
clock and asynchronous inputs have ample noise
margin, especially in the Low state.
• If possible, avoid simultaneous switching by staggering
output delays, e.g. through additional local routing of
signals or clocks.
• Spread simultaneously switching outputs around the IC
periphery. For a 16-bit bus, use two outputs each on
either side of four ground pins.
Ground-Bounce vs Delay Trade-Off
After the external sources of ground bounce have been
reduced or eliminated. the designer can trade .reduced
ground bounce for additional delay by selecting between
families and slew-rate options. Figure 4 shows the trade-off
for 16 outputs switching simultaneously High-to-Low.
In most devices tested, the load capacitance does not
directly affect the ground-bounce amplitude, but it does
affect the duration of the ground-bounce signals.
1800
1600
On the fastest outputs, minimal load capacitance created a
ground-bounce resonant frequency of 340 MHz, with a
half-cycle time of 1.5 ns. Such a signal exceeds 90% of its
peak amplitude for about 0.4 ns.
~
~
1000
With a 50 pF load on the switching outputs, the ground
bounce resonant frequency is 90 MHz, with a half-cycle
time of 5 ns, staying 1.7 ns above 90% of peak amplitude.
.g
800
te
600
With a 150 pF load on the switching outputs, the ground
bounce resonant frequency is 40 to 60 MHz, with a halfcycle time of 8 to 12 ns, staying 3 ns above 90% of peak
amplitude.
The main problem with large load capacitances is not an
increase in amplitude, but rather an increase in duration of
the ground-bounce signal. The amplitude is mainly affected
by the number of outputs switching simultaneously, and by
XAPP 045 November 24, 1997 (Version 1.1)
~
FAST SLEW RATE
1400
"
~ 1200
16x50pF
•
16x150pF
•
•
SLOW SLEW RATE
16x50pF
16x150pF
•
400
200
I
4
I
I
5 Additional 6
Delay (ns)
X5981
Figure 4: Ground-Bounce vs. Delay Trade-off for 16
Outputs Switching 50 and 150 pF Each
13-17
I
XC4000 Series Technical Information
XC4000 and XC4000E Power
Consumption
Below are the dynamic power consumption values for typical design elements in XC4000 and XC4000E.
The following elements are obviously device-size dependent:
•
One Global Clock driving all CLB flip-flops, but no flipflop changing:
in XC4005: 4 mW/MTps = 8 mW/MHz
in XC401 0: 8 mW/MTps = 16 mW/MHz
in XC4013: 12 mW/MTps = 24 mW/MHz
in XC4020: 16 mW/MTps = 32 mW/MHz
in XC4025: 20 mW/MTps = 40 mW/MHz
•
One full-length horizontal or vertical Longline with one
driving CLB source and one driven CLB load:
in XC4005: 0.10 mW/MHz = 0.20 mW/MHz
in XC401 0: 0.15 mW/MTps = 0.30 mW/MHz
in XC4013: 0.18 mW/MTps = 0.36 mW/MHz
in XC4020: 0.20 mW/MTps = 0040 mW/MHz
in XC4025: 0.24 mW/MTps = 0048 mW/MHz
The differences between XC4000 and XC4000E are too
small to be statistically relevant:
Global clocks in XC4000E are 3% higher, and Longlines
and unloaded outputs in XC4000E are 5 to 10% lower than
in XC4000.
Power consumption is given at nominal 5.0-V supply and
25"C.
Power is proportional to the square of the supply voltage,
but is almost constant over temperature changes. Power is
given as "mW per million transitions per second", since the
more commonly used "MHz" can be ambiguous. When a
1O-MHz clock toggles a flip-flop, the clock line obviously
makes 20 MTps, the flip-flop output only 10 MTps.
The first six elements are device-size independent, i.e. they
are applicable to all XC4000 or XC4000E devices operating
at 5-VVcc.
One CLB flip-flop driving nothing but a neighboring flipflop in the same or adjacent CLB (a typical shift register
design):
0.1 mW per million transitions per second =
0.1 mW/MTps
•
One CLB flip-flop driving its neighbor plus 9 lines of
interconnect:
0.2 mW per million transitions per second =
0.2 mW/MTps
•
One unloaded or unbonded TTL-level output:
0.25 mW per million transitions per second =
0.25 mW/MTps
These numbers do not account for the 10 mA of static
power consumption when all device inputs are configured
in TTL mode, which is always the default mode, and in
XC4000 is actually the only user-accessible mode.
These numbers assume short rise and fall times on all
inputs, avoiding the cross-current when both the n-channel
pull-down and the p-channel pull-up transistor in the input
buffer might conduct simultaneously.
Tutorial Comments:
In its pure form, a CMOS output driving a capacitive load
has a power consumption that is independent of drive
impedance or rise and fall time. For a full-swing signal, the
power consumed when charging the capacitor is C x V2 X f
where f is the frequency of charge operations. In each
charge operation, half the total energy consumed ends up
on the capacitor, and the other half of the energy is dissipated in the current-limiting resistor or transistor, whatever
its value may be.
50 pF on a TTL-level output: add 0.5 mW/MTps = 1.0
mW/MHz
The subsequent discharge cycle does not take any new
energy from the power supply, but dissipates in the currentlimiting resistor/transistor all the energy that was formerly
stored in the capacitor.
•
One unloaded or unbonded XC4000E CMOS-level
output:
0.31 mW per million transitions per second =
0.31 mW/MTps
It is assumed here that the frequency is low enough so that
the capacitors are completely charged and discharged in
each half-cycle.
•
50 pF on a CMOS-level output: add 0.625 rnW/MTps =
1.25 mW/MHz
13-18
XAPP 045 November 24, 1997 (Version 1.1)
APPLICATION NOTE
XC3000 Series
Technical Information
XAPP 024 November 24, 1997 (Version 1.0)
Application Note By Peter Alfke and Bernie New
Summary
This Application Note contains additional information that may be of use when designing with the XC3000 series of FPGA
devices. This information supplements the data sheets, and is provided for guidance only.
Xilinx Family
XC3000/XC3000NXC3000UXC31 00/XC31 00NXC31 OOL
Contents
Configurable Logic Blocks
CLBs
Function Generators
Flip-flops
Longline Access
lOBs
Inputs
Outputs
Routing
Horizontal Longlines
Bus contention
Vertical Longlines
Vertical Longlines
Clock Buffers
Vertical Longlines
Clock Buffers
Power Dissipation
Crystal Oscillator
CCLK Frequency Stability and Low-time restriction
Powerdown and Battery-Backup
Configuration and Start-Up
Reset
Beware of slow rise-time
The XC3000/XC3100 CLB, shown in Figure 1, contains a
combinatorial function generator and two D-type flip-flops.
Two output pins may be driven by either the function generators or the flip-flops. The flip-flop outputs may be routed
directly back to the function generator inputs without going
outside of the CLB.
Introduction
The background information provided in this Application
Note supplements the XC3000, XC3000A, XC3000L,
XC3100A and XC3100L data sheets. It covers a wide
range of topics, including a number of electrical parameters
not specified in the data sheets, and unless otherwise
noted, applies to all six families. These additional parameters are sufficiently accurate for most design purposes;
unlike the parameters specified in the data sheets, however, they are not worst-case values over temperature and
voltage, and are not 100% production tested. They can,
therefore, not be guaranteed.
XAPP 024 November 24, 1997 (VerSion 1.0)
The function generator consists of two 4-input look-up
tables that may be used separately or combined into a single function. Figure 2 shows the three available options.
Since the CLB only has five inputs to the function generator, inputs must be shared between the two look-up tables.
In the FG mode, the function generator provides any two 4input functions of A, Band C plus D or E; the choice
between D and E is made separately for each function. In
the F mode, all five inputs are combined into a single 5input function of A, B, C, D and E. Any 5-input function may
be emulated. The FGM mode is a superset of the F mode,
where two 4-input functions of A, B, C and D are multiplexed together according to the fifth variable, E.
In all modes, either of the Band C inputs may be selectively
replaced by QX and QY, the flip-flop outputs. In the FG
mode, this selection is made separately for the two look-up
tables, extending the functionality to any two functions of
four variables chosen from seven, provided two of the variables are stored in the flip-flops. This is particularly useful
in state-machine-like applications.
In the F mode, the function generators implement a single
function of five variables that may be chosen from seven, as
described above. The selection of QX and QY is constrained to be the same for both look-up tables. The FGM
mode differs from the F mode in that QX and QY may be
selected separately for the two look-up tables, as in the FG
mode. This added flexibility permits the emulation of
selected functions that can include all seven possible
inputs.
13-19
I
XC3000 Series Technical Information
Data In -r=DI--~====+-___lj
CLBOutputs
EnablecIOCk-+-=-_ _ _ _ _ _ _ _ _----j
Clock
Reset
Direct
-+-~-------i
RD
Figure 1: Configurable Logic
Block (CLB)
Function Generator Avoids Glitches
The combinatorial logic in all CLBs is implemented as a
function generator in the form of a multiplexer, built out
of transfer gates. The logic inputs form the select inputs
to this multiplexer, while the configuration bits drive the
data inputs to the multiplexer.
The Xilinx circuit designers were very careful to achieve
a balanced design with similar (almost equal) propagation delays from the various select inputs to the data
output.
The delay from the data inputs to the output is, of
course, immaterial, since the data inputs do not change
dynamically. They are only affected by configuration.
This balanced design minimizes the duration of possible decoding glitches when more than one select input
changes. Note that there can never be a decoding glitch
when only one select input changes. Even a non-overlapping decoder cannot generate a glitch problem,
since the node capacitance will retain the previous logic
level until the new transfer gate is activated about a
nanosecond later.
When more than one input changes "simultaneously;'
the user should analyze the logic output for any possible intermediate code. If any such code permutation
produces a different result, the user must assume that
such a glitch might occur and must make the system
design immune to it. The glitch might be only a few
nanoseconds long, but that is long enough to upset an
asynchronous design.
If none of the possible address sequences produces a
different result, the user can be sure that there will be
no glitch.
The designer of synchronous systems generally
doesn't worry about such glitches, since synchronous
designs are fundamentally immune to glitches on all
signals except clocks or direct SET/RESET inputs.
13-20
A
B
OX
Any Function
ofUpTo4
Variables
C
D
A
B
OX
Any Function
of UpTo4
Variables
G
C
D
2.
FG
Mode
A
B
OX
Any Function
of 5 Variables
G
C
D
E
2b
F
Mode
A
B
OX
C
D
A
G
B
:OX
C
D
X321B
Figure 2: CLB Logie Options
XAPP 024 November 24, 1997 (Version 1.0)
~XILINX
The automatic logic-partitioning software in the XACTstep
development system only uses the FG and F modes. However, all three modes are available with manual partitioning,
which may be performed in the schematic. If FG or F
modes are required, it is simply a matter of including in the
schematic CLBMAP symbols that define the inputs and
outputs of the CLB.
The XC3000/XC3100 lOB, shown in Figure 3, includes a 3state output driver that may be driven directly or registered.
The polarities of both the output data and the 3-state control are determined by configuration bits. Each output buffer
may be configured to have either a fast or a slow slew rate.
The FGM mode is only slightly more complicated. Again, a
CLBMAP must be used, with the signal that multiplexes
between the two 4-input functions locked onto the E pin.
The CLB will be configured in the FGM mode if the logic is
drawn such that the gates forming the multiplexer are
shown explicitly with no additional logic merged into them.
The lOB input may also be direct or registered. Additionally,
the input flip-flop may be configured as a latch. When an
lOB is used exclusively as an input, an optional pull-up
resistor is available, the value of which is 40-150 kQ. This
resistor cannot be used when the lOB is configured as an
output or as a bidirectional pin.
The two D-type flip-flops share a common clock, a common
clock enable, and a common asynchronous reset signal.
An asynchronous preset can be achieved using the asynchronous reset if data is stored in active-low form; the Low
created by reset corresponds to the bit being asserted. The
flip-flops cannot be used as latches.
Unused lOBs should be left unconfigured. They default to
inputs pulled High with the internal resistor.
If input data to a CLB flip-flop is derived directly from an
input pad, without an intervening flip-flop, the data-pad-toclock-pad hold time will typically be non-zero. This hold
time is equal the delay from the clock pad to the CLB, but
may be reduced according to the 70% rule, described later
in the lOB Input section of this Application Note. Under this
rule, the hold time is reduced by 70% of the delay from the
data pad to the CLB, excluding the CLB set-up time. The
minimum hold time is zero, even when applying the 70%
rule results in a negative number.
The CLB pins to which Longlines have direct access are
shown in Table 1. Note that the clock enabl.e pin (EC) and
the TBUF control pin are both driven from to the same vertical Long Line. Consequently, EC cannot easily be used to
enable a register that must be 3-stated onto a bus. Similarly, EC cannot easily be used in a register that uses the
Reset Direct pin (RD).
Table 1: Longline to CLB Direct Access
CLB
Longline
Left Most Vertical
(GCLK)
Left Middle Vertical
Right Middle Vertical.
Right Most Vertical
(ACLK)
Upper Horizontal
Lower Horizontal
A
B C 0
TBUF
E K EC RD
X
X
X
X
X
X
X
X
X
XAPP 024 November 24, 1997 (VerSion 1.0)
X
T
X
Input/Output Blocks
Inputs
All inputs have limited hysteresis, typically in excess of 200
mV for TTL input thresholds and in excess of 100 mV for
CMOS thresholds. Exceptions to this are the PWRDWN
pin, and the XTL2 pin when it is configured as the crystal
oscillator input.
Experiments show that the input rise and fall times should
not exceed 250 ns. This value was established through a
worst·case test using internal ring oscillators to drive all I/O
pins except two, thus generating a maximum of on-chip
noise. One of the remaining I/O pins was configured as an
input, and tested for single-edge response; the other I/O
was used as an output to monitor the response.
These test conditions are, perhaps, overly demanding,
although it was assumed that the PC board had negligible
ground noise and good power-supply decoupling. While
conservative, the resulting speCification is, in most
instances, easily. satisfied.
lOB input flip-flops are guaranteed to operate correctly
without data hold times (with respect to the device clockinput pad) provided that the dedicated CMOS clock input
pad and the GCLK buffer are used. The use of a TTL clock
or a different clock pad will result in a data-hold-time
requirement. The length of this hold time is equal to the
delay from the actual clock pad to the GCLK buffer minus
the delay from the dedicated CMOS clock pad to the GCLK
buffer.
To ensure that the input flip-flop has a zero hold time, delay
is incorporated in the 0 input of the flip.flop, causing it to
have a relatively long set-up time. However, the set-up time
specified in the data sheet is with respect to the clock
reaching the lOB. Since there is an unavoidable delay
between the clock pad and the lOB, the input-pad-to-clockpad set-up time is actually less than the data sheet number.
13-21
I
XC3000 Series Technical Information
program·Control~ed
Out
Memory Cells
---¥-"O---JL/
Direct In ~!-,----+---------,
Registered In -1-'°"-----+---10
01--+--1---<1--------+
FlipFlop
or
Latch
OK
IK
TTL or
CMOS
Input
Threshold
'-----<~------ (Global Reset)
CKt
=D-
Program
Controlled
Multiplexer
CK2
o
== Programmable Interconnection Point Of PIP
X3216
Figure 3: Input/Output Block (lOB)
Part of the clock delay can be subtracted from the internal
set-up time. Ideally, all of the clock delay could be subtracted, but it is possible for the clock delay to be less than
its maximum while the internal set-up time is at its maximum value. Consequently, it is recommended that, in a
worst-case design, only 70% of the clock delay is subtracted.
The clock delay can only be less than 70% of its maximum
if the internal set-up time requirement is also less than its
maximum. In this case, the pad-to-pad set-up time actually
required will be less than that calculated.
For example, in the XC3000-125, the input set-up time with
respect to the clock reaching the lOB is 16 ns. If the delay
from the clock pad to the lOB is 6 ns, then 70% of this delay,
4.2 ns, can be subtracted to arrive at a maximum pad-topad set-up time of -12 ns.
The 70% rule must be applied whenever one delay is subtracted from another. However, it is recommended that
delay compensation only be used routinely in connection
with input hold times. Delay compensation in asynchronous
circuits is specifically not recommended. In any case, the
compensated delay must not become negative. If 70% of
the compensating delay is greater than the delay from
which it is deducted, the resulting delay is zero.
13-22
The 70% rule in no way defines the absolute minimum values delays that might be encountered from chip to chip,
and with temperature and power-supply variations. It simply indicates the relative variations that might be found
within a specific chip over the range of operating conditions.
Typically, all delays will be less than their maximum, with
some delays being disproportionately faster than others.
The 70% rule describes the spread in the scaling factors;
the delay that decreases the most will be no less than 70%
of what it would have been if it had scaled in proportion to
the delay that decreased the least. In particular, in a worstcase design where it is assumed that any delay might not
have scaled at all, and remains at its maximum value, other
delays will be no less than 70% of their maximum.
Outputs
All XC3000/XC31 00 FPGA outputs are true CMOS with nchannel transistors pulling down and p-channel transistors
pulling up. Unloaded, these outputs pull rail-to-rail. Some
additional ac characteristics of the output are listed in
Table 2. Figure 4 and Figure 5 show output current/voltage
curves for typical XC3000 and XC31 00 devices.
XAPP 024 November 24, 1997 (Version 1.0)
~XILINX
200.---r~,,~,,-,~--
180
1-~~-I---~f-~---i------1~~--
160
1-------, -----!----i-- ---,,------
140 I~~------+--+----I ~--120
1-------I---1---+----I----t---:=1:==+==t:==f==1
80~~--~~~t-~i-~~~~~~r~1
lOB latches have active-Low Latch Enables; they are transparent when the clock input is Low and are closed when it is
High. The latch captures data on what would otherwise be
the active clock edge, and is transparent in the half clock
period before the active clock edge.
Routing
60~-~~~--+I'~--+~~~~--r--t----I~
Horizontal Longlines
401-----I~--t-------------r---'-----
As shown in Table 3, there are two horizontal Longlines
(HLLs) per row of CLBs. Each HLL is driven by one TBUF
for each column of CLBs, plus an additional TBUF at the
left end of the Longline. This additional TBUF is convenient
for driving lOB data onto the Longline. In general, the routing resources to the T and I pins of TBUFs are somewhat
limited.
20~~-~-+---,~~~~
O~~--~~--~~--~--~~--~~
Volts
X5294
Figure 4: Output Current/Voltage Characteristics for
XC3000, XC3000A, XC31 00 and XC3100A Devices
Table 3: Number of Horizontal Longlines
Output-short-circuit-current values are given only to indicate the capability to charge and discharge capacitive
loads_ In accordance with common industry practice for
other logic devices, only one output at a time may be short
circuited, and the duration of this short circuit to Vee or
ground may notexceed one second. Xilinx does not recommend a continuous output or clamp current in excess of 20
mA on anyone output pin. The data sheet guarantees the
outputs for no more than 4 mA at 320 mV to avoid problems
when many outputs are sinking current simultaneously.
The active-High 3-state control (T) is the same as an
active-Low output enable (OE). In other words, a High on
the T-pin of an OBUFZ places the output in a high impedance state, and a Low enabl_es the output. The same namingconventionis used for TBUFs within the FPGA device_
I/O Clocks
Internally, up to eight distinct I/O clocks can be used, two on
each of the four edges of the die. While the lOB does not
provide programmable clock polarity, the two clock lines
serving an lOB can be used for true and inverted clock, and
the appropriate polarity connected to the lOB. This does,
however, limit all lOBs on that edge of the die to using only
the two edges of the one clock.
Table 2: Additional AC Output Characteristics
AC Parameters
Unloaded Output Slew Rate
Unloaded Transition Time
Additional rise time for 812 pF
normalized
Additional fall time for 812 pF
normalized
Fast*
2.8 V/ns
1.45 ns
100ns
0.12 ns/pF
50 ns
0_06 ns/pF
Slow*
0_5 V/ns
7.9 ns
100ns
0.12 ns/pF
64 ns
0.08 ns/pF
* Fast and Slow refer to the output programming option.
XAPP 024 November 24, 1997 (Version 1.0)
Part
Name
XC3020
XC3030
XC3042
XC3064
XC3090
XC3195
Rows x
Columns
8x8
10 x 10
12 x 12
16 x 14
20 x 16
22x22
CLBs
64
100
144
224
320
484
Horizontal
Longlines
16
20
24
32
40
44
TBUFs
per HLL
9
11
13
15
17
23
Optionally, HLLs can be pulled up at either end, or at both
ends. The value of each pull-up resistor is 3-10 kQ.
In addition, HLLs are permanently driven by low-powered
latches that are easily overridden by active outputs or pullup resistors. These latches maintain the logic levels on
HLLs that are not pulled up and temporarily are not driven.
The logic level maintained is the last level actively driven
onto the line.
When using 3-state HLLs for multiplexing, the use of fewer
than four TBUFs can waste resources. Multiplexers with
four or fewer inputs can be implemented more efficiently
using CLBs.
Internal Bus Contention
XC3000 and XC4000 Series devices have internal 3-state
bus drivers (TBUFs). As in any other bus design, such bus
drivers must be enabled carefully in order to avoid, or at
least minimize, bus contention_ (Bus contention means that
one driver tries to drive the bus High while a second driver
tries to drive it Low).
Since the potential overlap of the enable signals is lay-out
dependent, bus contention is the responsibility of the FPGA
user. We can only supply the following information:
While two internal buffers drive conflicting data, they create
a current path of typically 6 mAo This current is tolerable,
but should not last indefinitely, since it exceeds our (conser13-23
I
XC3000 Series Technical Information
vative) current density rules. A continuous contention
could, after thousands of hours, lead to metal migration
problems.
In a typical system, 10 ns of internal bus contention at 5
MHz would just result in a slight increase in Icc.
16 bits x 6 mA x 10 ns x 5 MHz x 50% probability =2.5 mA
There is a special use of the 3-state control input: When it is
directly driven by the same signal that drives the data input
of the buffer, Le. when D and T are effectively tied together,
the 3-state buffer becomes an "open collector" driver. Multiple drivers of this type can be used to implement the "wiredAND" function, using resistive pull-up.
In this situation there cannot be any contention, since the 3state control input is designed to be slow in activating and
fast in deactivating the driver. Connecting D to ground is an
obvious alternative, but may be more difficult to route.
Vertical Longlines
There are four vertical longlines per routing channel: two
general purpose, one for the global clock net and one for
the alternate clock net.
Clock Buffers
XC3000IXC3100 devices each contain two high-fan-out,
low-skew clock-distribution networks. The global-clock net
originates from the GClK buffer in the upper left corner of
the die, while the alternate clock net originates from the
AClK buffer in the lower right corner of the die.
The global and alternate clock networks each have optional
fast CMOS inputs, called TClKIN and BClKIN, respectively. Using these inputs provides the fastest path from the
PC board to the internal flip-flops and latches. Since the
signal bypasses the input buffer, well-defined CMOS levels
must be guaranteed on these clock pins.
To specify the use of TClKIN or BClKIN in a schematic,
connect an IPAD symbol directly to the GClK or AClK
symbol. Placing an IBUF between the IPAD and the clock
buffer will prevent TClKIN or BClKIN from being used.
The clock buffer output nets only drive ClB and lOB clock
pins. They do not drive any other CLB inputs. In rare cases
where a clock needs to be connected to a logic input or a
device output, a signal should be tapped off the clock buffer
input, and routed to the logic input. This is not possible with
clocks using TClKIN or BClKIN.
The clock skew created by routing clocks through local
interconnect makes safe designs very difficult to achieve,
and this practice is not recommended. In general, the fewer
clocks that are used, the safer the design. High fan-out
clocks should always use GClK or AClK. If more than two
clocks are required, the AClK net can be segmented into
individual vertical lines that can be driven by PIPs at the top
and bottom of each column. Clock signals routed through
13-24
local interconnect should only be considered for individual
flip-flops.
Power Dissipation
As in most CMOS ICs, almost all FPGA power dissipation
is dynamic, and is caused by the charging and discharging
of internal capacitances. Each node in the device dissipates power according to the capacitance in the node,
which is fixed for each type of node, and the frequency at
which the particular node is switching, which can be different from the clock frequency. The total dynamiC power is
the sum of the power dissipated in the individual nodes.
While the clock line frequency is easy to specify, it is usually
more difficult to estimate the average frequency of other
nodes. Two extreme cases are binary counters, where half
the total power is dissipated in the first flip-flop, and shift
registers with alternating zeros and ones, where the whole
circuit is exercised at the clocking speed.
A popular assumption is that, on average, each node is exercised at 20% of the clock rate; a major EPlD vendor uses a
16-bit counter as a model, where the effective percentage is
only 12%. Undoubtedly, there are extreme cases, where the
ratio is much lower or much higher, but 15 to 20% may be a
valid approximation for most normal designs. Note that global clock lines must always be entered with their real, and
obviously well-known, frequency.
Consequently, most power consumption estimates only
serve as guidelines based on gross approximations. Table
4 shows the dynamic power dissipation, in mW per MHz,
for different types of XC3000 nodes. While not precise,
these numbers are sufficiently accurate for the calculations
in which they are used, and may be used for any XC3000/
XC31 00 device. Table 5 shows a sample power calculation.
Table 4: Dynamic Power Dissipation
One CLB driving three local interconnects
One device output with a
50
pFload
One Global Clock Buffer and line
One Longline without driver
XC3020 XC3090
0.25
mW/MHz
0.25
1.25
1.25
mW/MHz
2.00
0.10
3.50
0.15
mW/MHz
mW/MHz
Table 5: Sample Power Calculation for XC3020
Quantity
1
5
10
40
8
20
Node
Clock Buffer
CLBs
CLBs
CLBs
Longlines
Outputs
mW
MHz mW/MHz
40
2.00
80
0.25
40
50
0.25
50
20
10
0.25
100
20
0.10
16
20
1.25
500
Total Power -800
XAPP 024 November 24, 1997 (Version 1.0)
~XILINX
Crystal Oscillator
XC3000 and XC3100 devices contain an on-chip crystal
oscillator circuit that connects to the ACLK buffer. This circuit, Figure 5, comprises a high-speed, high-gain inverting
amplifier with its input connected to the dedicated XTL2
pin, and its output connected to the XTL 1 pin. An external
biasing resistor, R1, with a value of 0.5 to 1 MQ is required.
A crystal, Y1, and additional phase-shifting components,
R2, C1 and C2, complete the circuit. The capacitors, C1
and C2, in series form the load on the crystal. This load is
specified by the crystal manufacturer, and is typically 20 pF.
The capacitors should be approximately equal: 40 pF each
for a 20 pF crystal.
Either series- or parallel-resonant crystals may be used,
since they differ only in their specification. Crystals constrain oscillation to a narrow band of frequencies, the width
of which is «1 % of the oscillating frequency; the exact frequency of oscillation within this band depends on the components surrounding the crystal. Series-resonant crystals
are specified by their manufacturers according to the lower
edge of the frequency band, parallel-resonant crystals
according to the upper edge.
The resistor R2 controls the loop gain and its value must be
established by experimentation. If it is too small, the oscillation will be distorted; if it is too large, the oscillation will fail
to start, or only start slowly. In most cases, the value of R2
is non-critical, and typically is 0 to 1 kQ.
Once the component values have been chosen, it is good
practice to test the oscillator with a resistor (-1 kQ) in series
with the crystal. If the oscillator still starts reliably, independent of whether the power supply turns on quickly or slowly,
it will always work without the resistor.
For operation above 20 to 25 MHz, the crystal must be
operated at its third harmonic. The capacitor C2 is replaced
by a parallel-resonant LC tank circuit tuned to -2/3 of the
desired frequency, i.e., twice the fundamental frequency of
the crystal. Table 6 shows typical component values for the
tank circuit.
Crystal operation below 1 MHz is not supported. Low-frequency crystals have a high resonant impedance and
require more gain than provided by the single stage inverter
in the XC3000 devices. Low-frequency applications are
usually also more power-conscious and would not accept
the power consumption of the fast general-purpose Xilinx
oscillator circuit. Inexpensive complete oscillator packages
are often a better choice.
R1
R2
~----~D~--~--~~~
Y1
----I
r
C2
T
r----==
~
I
I
L
3RD
Overtone
Only
X6128
Figure 5: Crystal Oscillator
Table 6: Third-Harmonic Crystal Oscillator Tank-Circuit
Frequency
LCTank
(MHz)
L (JlH) C2 (pF) Freq (MHz) R2(Q) C1 (pF)
60
20.6
430
23
32
1
35
1
44
24.0
310
23
49
1
31
28.6
190
23
72
18
1
37.5
150
12
Crystal-Oscillator Considerations
There is nothing Xilinx-specific about the oscillator circuit.
It's a wide-band inverting amplifier, as used in all popular
microcontrollers. When a crystal and some passive components close the feedback path, this circuit becomes a reliable and stable clock source.
The path from XTAL2 to XTAL 1 inside the LCA device is a
single-stage inverting amplifier, which means it has a lowfrequency phase response of 180°, increasing by 45° at the
3-dB frequency.
Input impedance is 10-15 pF, input threshold is CMOS, but
dc bias must be supplied externally through a megohm
resistor from XTAL 1 to XTAL2.
Low-frequency gain is about 10, rolling off 3dB at 125 MHz.
Output impedance is between 50 and 100 Q and the
capacitance on the output pin is 10 to 15 pF.
Pulse response is a delay of about 1.5 ns and a rise/fall
time of about 1.5 ns.
XAPP 024 November 24, 1997 (Version 1.0)
13-25
I
XC3000 Series Technical Information
For stable oscillation,
•
•
the loop gain must be exactly one, i.e., the internal gain
must be matched by external attenuation, and
the phase shift around the loop must be 360° or an
integer multiple thereof. The external network must,
therefore, provide 180° of phase shift.
A crystal is a piezoelectric mechanical resonator that can
be modeled by a very high-Q series LC circuit with a small
resistor representing the energy loss. In parallel with this
series-resonant circuit is unavoidable parasitic capacitance
inside and outside the crystal package, and usually also
discrete capacitors on the board.
circuit equals the gain in the FPGA device, and where the
total phase shift, internal plus external, equals 360°.
Figure 7 explains the function. At the frequency of oscillation, the series-resonant circuit is effectively an inductor,
and the two capacitors act as a capacitive voltage divider,
with the center-point grounded. This puts a virtual ground
somewhere along the inductor and causes the non-driven
end of the crystal to be 180° out of phase with the driven
end, which is the external phase shift required for oscillation. This circuit is commonly known as a Pierce oscillator.
XC2000/xC3000
The impedance as a function of frequency of this whole
array starts as a small capacitor at low frequencies
(Figure 6). As the frequency increases, this capacitive
reactance decreases rapidly, until it reaches zero at the
series resonant frequency.
Inductiv,e
jmL
Series:
:Parallel
Reson:ance
:Resonance
I
XTAL
X5321
f----;;;o,....,,'----+----_Frequency
jmC
~p~hlw
Practical Considerations
•
(
rc~
--------.r--- -----,
X2818
Figure 6: Reactance as a Function of Frequency
At slightly higher frequencies, the reactance is inductive,
starting with a zero at series resonance, and increasing
very rapidly with frequency. It reaches infinity when the
effective inductive impedance of the series LC circuit
equals the reactance of the parallel capacitor. The parallel
resonance frequency is a fraction of a percent above the
series-resonance frequency.
Over this very narrow frequency range between series and
parallel resonance, the crystal impedance is inductive and
changes all the way from zero to infinity. The energy loss
represented by the series resistor prevents the impedance
from actually reaching zero and infinity, but it comes very
close.
Microprocessor- and FPGA-based crystal oscillators all
operate in this narrow frequency band, where the crystal
impedance can be any inductive value. The circuit oscillates at a frequency where the attenuation in the external
13-26
Figure 7: Pierce Oscillator
The series resonance resistor is a critical parameter. To
assure reliable operation with worst-case crystals, the
user should experiment with a discrete series resistor
roughly equal to the max internal resistance specified
by the crystal vendor. If the circuit tolerates this
additional loss, it should operate reliably with a worstcase crystal without the additional resistor.
• The two capacitors affect the frequency of oscillation
and the start-up conditions. The series connection of
the two capacitors is the effective capacitive load seen
by the crystal, usually specified by the crystal vendor.
• The two capacitors also determine the minimum gain
required for oscillation. If the capacitors are too small,
more gain is needed, and the oscillator may be
unstable. If the capacitors are too large, oscillation is
stable but the required gain may again be higher. There
is an optimum capacitor value, where oscillation is
stable, and the required gain is at a minimum. For most
crystals, this capacitive load is around 20 pF, i.e., each
of the two capacitors should be around 40 pF.
• Crystal dissipation is usually around 1 mW, and thus of
no concern. Beware of crystals with "drive-level
dependence" of the series resistor. They may not start
up. Proper drive level can be checked by varying Vcc.
The frequency should increase slightly with an increase
in Vcc. A decreasing frequency or unstable amplitude
indicate an over-driven crystal. Excessive swing at the
XAPP 024 November 24, 1997 (Version 1.0)
~XILINX
•
•
XTAL2 input results in clipping near Vcc and ground. An
additional 1 to 2 kO series resistor at the XTAL 1 output
usually cures that distortion problem. It increases the
amplifier output impedance and assures additional
phase margin, but results in slower start-up.
Be especially careful when designing an oscillator that
must operate near the specified max frequency. The
circuit needs excess gain at small signal amplitudes to
supply enough energy into the crystal for rapid start-up.
High-frequency gain may be marginal, and start-up may
be impaired.
Keep the whole oscillator circuit physically as compact
as possible, and provide a single ground connection.
Grounding the crystal can is not mandatory but may
improve stability.
and fastest Xilinx FPGA is compatible with the oldest and
slowest device ever manufactured. The CCLK frequency is
fairly insensitive to changes in Vee, varying only 0.6% for a
10% change in Vee. It is, however, very temperature
dependent, increasing 40% as the temperature drops from
25°C to -30°C, (Table 7.)
Table 7: Typical CCLK Frequency Variation
Vee
4.5V
5.0V
5.5V
4.5V
4.5V
Temp
25°C
25°C
25°C
-30°C
+130°C
Frequency
687 kHz
691 kHz
695 kHz
966 kHz
457 kHz
CCLK Low-Time Restriction
Series Resonant or Parallel Resonant?
Crystal manufacturers label some crystals as seriesresonant, others as parallel-resonant, but there really is
no difference between these two types of crystals, they
all operate in the same way. Every crystal has a series
resonance, where the impedance of the crystal is
extremely low, much lower than at any other frequency.
At a slightly higher frequency, the crystal is inductive
and in parallel resonance with the unavoidable stray
capacitance or the deliberate capacitance between its
pins,
The only difference between the two types of crystal is
the manufacturer's choice of specifying either of the two
frequencies. If series resonance is specified, the actual
frequency of oscillation is a little higher than the specified value. If parallel resonance is specified, the frequency of oscillation is a little lower. In most cases,
these small deviations are irrelevant.
CCLK Frequency Variation
The on-chip R-C oscillator that is brought out as CCLK also
performs several other internal functions. It generates the
power-on delay, 2 16 = 65,536 periods for a master,
214 =16,384 periods for a slave or peripheral device. It generates the shift pulses for clearing the configuration array,
using one clock period per frame, and it is the clock source
for several small shift registers acting as low-pass filters for
a variety of input signals.
The nominal frequency of this oscillator is 1 MHz with a
max deviation of +25% to -10%. The clock frequency,
therefore, is between 1.25 MHz and 0.5 MHz. In the
XC4000 family, the 1-MHz clock is derived from an internal
8-MHz clock that also can be used as CCLK source.
Xilinx circuit designers make sure that the internal clock frequency does not get faster as devices are migrated to
smaller geometries and faster processes. Even the newest
XAPP 024 November 24, 1997 (Version 1.0)
When used as an input in Slave Serial and Readback
modes, CCLK does not tolerate a Low time in excess of 5
Ils. For very low speed operation, the CCLK High time can
be stretched to any value, but the Low time must be kept
short. XC4000 and XC5200 devices do not have this
restriction.
Battery Back-up
Since SRAM-based FPGAs are manufactured using a
high-performance low-power CMOS process, they can preserve the configuration data stored in the internal static
memory cells even during a loss of primary power. This is
accomplished by forcing the device into a low-power nonoperational state, while supplying the minimal current
requirement of Vee from a battery.
Circuit techniques used in XC3100, XC4000 and XC5200
devices prevent Icc from being reduced to the level need
for battery back-up. Consequently, battery back-up should
only be used for XC2000, XC2000L, XC3000, XC3000A
and XC3000L devices.
There are two primary considerations for battery backup
which must be accomplished by external circuits.
•
•
Control of the Power-Down (PWRDWN) pin
Switching between the primary Vee supply and the
battery.
Important considerations include the following.
•
•
•
Insure that PWRDWN is asserted logic Low priorto Vee
falling, is held Low while the primary Vee is absent, and
returned High after Vee has returned to a normal level.
PWRDWN edges must not rise or fall slowly.
Insure "glitch-free" switching of the power connections
to the FPGA device from the primary Vee to the battery
and back.
Insure that, during normal operation, the FPGA Vee is
maintained at an acceptable level, 5.0 V ± 5% (±1 0% for
Industrial and Military).
13-27
I
XC3000 Series Technical Information
Figure 8 shows a power-down circuit developed by Shel
Epstein of Epstein Associates, Wilmette, IL. Two Schottky
diodes power the FPGA from either the 5.2 V primary supply or a 3 V Lithium battery. A Seiko S8054 3-terminal
power
monitor circuit monitors Vcc and pulls PWRDWN Low
whenever V cc falls below 4 V.
vee
IN58t?
Seiko S8054 Specifications
Detect Voltage 3.995 V min
4.305 V max
208 mV typ
Hysteresis
Temp. Coeff. 0.52 mV/oC
2.61lA typ
lee @ + 6V
During powerdown, the Vcc monitoring circuit is disabled. It
is then up to the user to prevent Vcc dips below 2.3 V, which
would corrupt the stored configuration.
IN58t?
B35
Lithium
Battery
X5997
Figure 8: Battery Back-up Circuit
Powerdown Operation
A Low level on the PWRDWN input, while Vcc remains
higher than 2.3 V, stops all internal activity, thus reducing
Icc to a very low level:
•
•
•
•
•
•
•
All internal pull-ups (on Long lines as well as on the I/O
pads) are turned off.
The crystal oscillator is turned off
All package outputs are three-stated.
All package inputs ignore the actual input level, and
present a High to the internal logic.
All internal flip-flops or latches are permanently reset.
The internal configuration is retained.
When PWRDWN is returned High, afterV cc is at its
nominal value, the device returns to operation with the
same sequence of buffer enable and Dip as at the
completion of configuration.
Things to Remember
Powerdown retains the configuration, but loses all data
stored in the device. Powerdown three-states all outputs
and ignores all inputs. No clock signal will be recognized,
and the crystal oscillator is stopped. All internal flip-flops
and latches are permanently reset and all inputs are interpreted as High, but the internal combinatorial logic is fully
functional.
Things to Watch aut For
Make sure that the combination of all inputs High and all
internal flip-flop outputs Low in your design will not generate internal oscillations or create permanent bus contention
13-28
by activating internal bus drivers with conflicting data onto
the same Longline. These two situations are farfetched, but
they are possible and will result in considerable power consumption. It is quite easy to simulate these conditions since
all inputs are stable and the internal logic is entirely combinatorial, unless latches have been made out of function
generators.
During configuration, the PWRDWN pin must be High,
since configuration uses the internal oscillator. Whenever
Vcc goes below 4 V, PWRDWN must already be Low in
order to prevent automatic reconfiguration at low Vcc. For
the same reason, Vcc must first be restored to 4 V or more,
before PWRDWN can be made High.
PWRDWN has no pull-up resistor. A pull-up resistor would
draw supply current when the pin is Low, which would
defeat the idea of powerdown, where Icc is only microamperes.
Configuration and Start-up
Start-Up
Start-up is the transition from the configuration process to
the intended user operation. This means a change from
one clock source to another, and a change from interfacing
parallel or serial configuration data where most outputs are
3-stated, to normal operation with I/O pins active in the
user-system. Start-up must make sure that the user-logic
"wakes up" gracefully, that the outputs become active without causing contention with the configuration signals, and
that the internal flip-flops are released from the global
Reset or Set at the right time.
Figure 10 describes Start-up timing for the XC3000 families
in detail.
DONE can be programmed to go High one CCLK period
before or after the I/O become active. Independent of
DONE, the internal global Reset is de-activated one CCLK
period before or after the I/O become active.
The default option, and the most practical one, is for DONE
to go High first, disconnecting the configuration data source
and avoiding any contention when the I/Os become active
one clock later. Reset is then released another clock period
later to make sure that user-operation starts from stable
internal conditions. This is the most common sequence,
shown with heavy lines in Figure 11, but the designer can
modify it to meet particular requirements.
Until the chip goes active after configuration, all I/O pins not
involved in the configuration process remain in a highimpedance state with weak pull-up resistors; all internal
flip-flops and latches are held reset. Multiple FPGA devices
hooked up in a daisy chain will all go active simultaneously
XAPP 024 November 24, 1997 (Version 1.0)
~XILINX
CCLK
unasserted, but D remains High since the function generator acts as an R-S latch; Q stays Low, and RESET is still
pulled High by the external resistor. On the first system
clock after configuration ends, Q is clocked High, resetting
the latch and enabling the output driver. which forces
RESET Low. This resets the whole chip until the Low on Q
permits RESET to be pulled High again.
The whole chip has thus been reset by a short pulse instigated by the system clock. No further pulses are generated, since the High on LDC prevents the R-S latch from
becoming set.
Figure 9: Start-up Timing
on the same CCLK edge. This is well documented in the
data sheets.
Not documented, however, is how the internal combinatorial logic comes alive during configuration: As configuration
data is shifted in and reaches its destination, it activates the
logic and also "looks at" the lOB inputs. Even the crystal
oscillator starts operating as soon as it receives its configuration data. Since all flip-flops and latches are being held
reset, and all outputs are being held in their high-impedance state, there is no danger in this "staggered awakening" of the internal logic. The operation of the logic prior to
the end of configuration is even useful; it ensures that clock
enables and output enables are correctly defined before
the elements they control become active.
Once configuration is complete, the FPGA device is activated. This occurs on a rising edge of tCLK, when all outputs and clocks that are enabled become active
simultaneously. Since the activation is triggered by CCLK, it
is an asynchronous event with respect to the system clock.
To avoid start-up problems caused by this asynchronism,
some designs might require a reset pulse that is synchronized to the system clock.
The circuit shown in Figure 10 generates a short Global
Reset pulse in response to the first system clock after the
end of configuration. It uses one CLB and one lOB, and
also precludes the. use of the LDC pin as 1/0.
During Configuration, [DC is asserted Low and holds the
D-input of the flip-flop High, whileQ is held Low by the internal reset, and RESET is kept High by internal and external
pull-up resistors. At the end of configuration, the LDC pin is
Beware of a Slow-Rising XC3000
Series RESET Input
It is a wide-spread habit to drive asynchronous RESET
inputs with a resistor-capacitor network to lengthen the
reset time after power-on. This can also be done with Xilinx
FPGAs, but the user should question the need, and should
beware of certain avoidable problems.
Xilinx FPGAs contain an internal voltage-monitoring circuit,
and start their internal housekeeping operation only after
Vee has reached -3.5 V. The internal housekeeping and
configuration memory clearing operation then takes
between about 10 and 100 ms, depending on configuration
mode and processing variations. Any RC delay shorter
than 40 ms for a device in master configuration mode, or
shorter than 10 ms for a device in slave configuration mode,
is clearly redundant.
A significantly longer RC delay can be used to hold off configuration. Without the use of an external Schmitt trigger circuit, the rise time.on the RESET input will be very slow, and
is likely to cross the threshold of -1.4 V several times, due
to external or internal noise. This can cause the FPGA to
start configuration, then immediately abort it, then start it
again, after having automatically cleared the configuration
memory once more.
This is no problem for the FPGA, but it requires that the
source of configuration data, especially an XC1700 serial
PROM, be reset accordingly. This is another reason to use
the iNii output of the lead FPGA, instead of [DC, to drive
the RESET input of the XC1700 serial PROMs.
Figure 10: Synchronous Reset
XAPP 024 November 24, 1997 (Version 1.0)
13-29
I
XC3000 Series Technical Information
13-30
XAPP024 November 24, 1997 (Version 1.0)
APPLICATION NOTE
FPGA Configuration Guidelines
XAPP 090 November 24, 1997 (Version 1.1)
Application Note By Peter Alfke
Summary
These guidelines describe the configuration process for all members of the XC2000, XC3000, XC4000 and XC5200 FPGA
devices and their derivatives. The average user need not understand or remember all these details, but should refer to the
debugging hints when problems occur.
The XC2000-, XC3000-, XC4000- and XC5200-family
FPGAs share a basic configuration concept, and can be
combined in a common configuration bitstream, but there
are also small differences among the four families as
described below.
Following their initial power-on configuration-memory initialization, these Xilinx FPGAs are configured by a serial
configuration bitstream. The byte-parallel configuration
modes just activate an internal parallel-to-serial converter,
and then use the serial bitstream internally. (Express mode
in the XC5200 configures eight bits in parallel, but this
mode is not covered in this application note.) The software
generates a bitstream that starts with a 40-bit header (48bit header for XC5200), see Figure 1.
Each device uses a few of the leading "ones".to prepare for
configuration, then detects the 0010 pattern and stores the
following 24 bits as a length-count value in an internal register. The content of this register is continuously compared
against a running counter that increments on every rising
CCLK edge. CCLK is either an output (in Master and Asynchronous Peripheral modes) or an input (in Slave Serial
and Synchronous Peripheral modes). In all modes, even in
Master Serial, it is the externally observable Low-to-High
transition on the CCLK pin that causes the internal action.
Every CCLK rising edge that occurs while INIT and RESET
are High is counted, even during the preamble, Note that
XC2000 and XC3000 use quasi-static circuitry which
imposes a 5 ms max limit on the CCLK Low time, while
XC4000 and XC5200 are completely static and have no
max CCLK time limit. This is, of course, only of interest in
XC2000 and XC3000 Slave Serial mode, where CCLK is
generated by the user.
While it is permissible, although not meaningful, to modify
the. number of leading ones by adding additional ones, or
subtracting up to four ones, this would inevitably affect the
number of CCLK pulses received by the counter, and thus
change the moment when the internal counter is equal to
the value stored in the length-count register. Don't add or
delete preamble-leading ones!
Each device passes the incoming header, including the
length-count value, on to the DOUT pin, delayed by half a
CCLK period, i.e. the bits are clocked out on a falling CCLK
edge. In this way, the header is passed on to all devices
that might.be connected in a daisy-chain. After the lengthcount data has been passed on, DOUT goes active High
and stays High until the device has been filled with the
appropriate number of configuration frames. After that,
DOUT again passes all incoming configuration data on to
other devices that might be part of the daisy chain.
DOUT is thus the best observation point to see whether the
configuration process has started properly.
Immediately following the header, configuration data is
received, formatted in a device-specific sequence of
frames. Each frame starts with a single "zero" as start bit
(XC5200 starts with a byte of seven leading "ones" and a
single trailing "zero"), followed by a device-specific number
of configuration bits per frame, followed by three "ones" as
stop bits (XC2000, XC3000) or, in XC4000 and XC5200, by
four bits that are either 0110, or four bits of a running 16-bit
CRC error-checking code. The choice is made in the bitstream generator, where the default is "CRC disabled". The
header is excluded from the CRC calculation.
Each frame is physically shifted into a serial shift register
that had been preset to all ones. When the zero start bithits
the ·far end of this shift register, the data frame is transferred
in parallel into the configuration memory, as addressed by
the position of an internal token or pointer. The three stop
or four error-check bits provide ample time for this transfer,
even at a 10 MHz CCLK rate. After this transfer, the shift-in
procedure continues with the following frame. Note that
there is no counter for the number of bits in the frame nor
for. the number of frames. The operation is self-synchronized by detecting the presence of a start bit at the far end
of the shift register, and by moving the frame pointer.
111111111 1 0010 1 (MSB) 24-Bit Length Count (LSB) 111111 Data
X5553
Figure 1: 40-Bit Header
XAPP090 November 24, 1997 (Version 1.1)
13-31
I
FPGA Configuration Guidelines
Each Xilinx FPGA requires a number of configuration bits
that is device-dependent, but independent of the configuration content, and independent of the configuration mode.
The number of configuration bits per device ranges from
12,038 for the XC2064 to 1,924,992 for the XC4085XL,
approximately 20 bits per available user gate. Exact values
are listed in the specific family data sheets.
Protection Against Data or Format
Errors
The serial configuration scheme has proven reliable in
thousands of designs and millions of devices, but there
have been cases where an erroneous bitstream was
loaded accidentally. The original XC2000 and XC3000
devices provide no effective protection against this type of
error. If long enough, any random sequence of Os and 1s
will configure such a device. This inevitably takes additional
CCLK pulses, more than specified in the length-count
value. This means that the CCLK counter already matches
the length-count value before the last FPGA in the chain is
filled. This comparison is, therefore, ignored, and an additional-16 million CCLK pulses are required to roll the 24-bit
length counter and finish the configuration. Such a configuration will, of course, be wrong and might result in excessive power consumption due tol contentions.
XC3000A, XC3100A, XC3000L and XC3100L devices use
a simple and effective method to protect against erroneous
configuration files or against loss (or gain) of CCLK pulses:
All Xilinx FPGA devices recognize a new frame when its
leading zero reaches the end of the shift register. XC2000,
XC3000, and XC3100 devices do not check for the presence of valid stop bits, but XC3000AlXC3100AIXC3000U
XC3100L devices always check whether the three bits at
the end of the defined frame length are 111. If this check
fails, INIT is pulled Low and the internal configuration is
stopped, although a master CCLK keeps running. The user
must recognize this state and start a new configuration by
applying a >6 lls Low level on RESET.
This simple check does not protect against single-bit random errors, but it offers almost 100% protection against
erroneous configuration files, defective configuration data
sources, synchronization errors between configuration
source and FPGA, as well as PC-board defects, such as
broken lines or solder bridges.
The XC4000 and XC5200 devices use, optionally, four bits
of a running 16-bit cyclic redundancy check code at the end
of each frame, combined with additional CRC bits at the
end of the bit stream. These error-detecting CRC codes
provide excellent protection against errors, even those that
do not change the frame structure. When an error is
detected, INIT goes Low and stays Low until the user initiates a reconfiguration. A master device does, however,
continue generating CCLK pulses and even incrementing
or decrementing the parallel PROM address.
13-32
Daisy-Chain Operation
Multiple FPGAs can be configured by a single concatenated bitstream. The device daisy chain is formed by connecting DOUT to the next device's DIN, and connecting all
CCLK pins in parallel. DOUT goes active on a falling clock
edge, and DIN accepts data on the subsequent rising clock
edge. Each DOUT-to-DIN connection adds one extra bit of
delay to the bitstream. Since the header is passed through
all devices, they all receive the same header information
delayed by one bit per device, but all devices maintain perfect synchronism between their CCLK counters, since all
receive the same CCLK.
Xilinx recognizes the need for all devices in a daisy chain to
finish configuration and begin user operation simultaneously, as a result of one common CCLK edge. Therefore,
all devices in a daisy-chain need a common timing reference. They cannot rely on the start pattern received
through the pipelined chain, but must all count the common
CCLK pulses exactly the same way. This explains the
importance of precise configuration clocking, and the danger of reflections·and ringing on the CCLK line.
Start-Up Procedure
During configuration, all outputs that are not involved in the
configuration process are 3-stated, although the crystal
oscillator circuit is activated as soon as possible. All internal
flip-flops and latches are held reset (set or reset in
XC4000), and the DONE output is held Low.
At the end of configuration, these three conditions must
change: As shown in detail in Figure 2, the various families
offer different options:
XC2000 has no options; the II0s go active one CCLK
period after length-count match. One CCLK period later,
DONE goes active and the global reset is released.
XC3000 makes the II0s go active two CCLK periods after
length-count match; but DONE and the release of the global reset can each occur either one CCLK period before or
after the II0s go active. The default is "early DONE and late
release of the global reset". This makes the outputs go
active while the internal logic is still held reset. The other
option, "early release of global reset", lets the internal logic
be clocked out of its reset state before the outputs go
active.
Normally, there is no defined timing relationship between
the last configuration events triggered by the rising edge of
CCLK, and the subsequent events that are controlled by
the system clock. The user must be aware of the potential
timing problems of this asynchronous relationship between
the two clocks. See the XC4000/XC5200 solution
described below.
XC4000 and XC5200 have more options for the relative
timing of I10s, DONE and GSR, the release of the global
set or reset.
XAPP 090 November 24, 1997 (Version 1.1)
~XILINX
I
Note: Thick lines are default option
F::= Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
Heavy lines describe
default timing
X5972
Figure 2: Start-up Timing
XAPP 090 November 24, 1997 (Version 1.1)
13-33
FPGA Configuration Guidelines
These families can also use DONE as an input to hold off
the activation of the lias and the release of GSR, until
DONE is no longer pulled Low. The change then takes
place either immediately upon the release of DONE, or as a
result of the next CCLK rising edge. When all DONE pins in
a daisy chain are interconnected, this start-up mode guarantees that all devices in the chain go active only when all
of them have reached the DONE state, an additional protection against potential configuration errors.
XC4000 and XC5200 can also be configured to employ the
system (user) clock instead of CCLK, again either using
DONE as an output, or as a bidirectional pin.
Output
Connected
Reset
toCCLK
o
0
1
1
0
Active Low Output
1
1
1
Active High Output
3-Stated Output
3·Stated Output
o
o
etc
X5552
The user clock provides a properly synchronized and racefree transition from the end of configuration to the beginning of user operation. The unspecified on-chip delay in the
release of GSR (about 100 as in XC4013E) requires some
caution, however, when using a high clock frequency for
configuration.
While devices from different families can be arbitrarily interspersed in a daisy-chain, there is one restriction: the lead
device must belong to the highest-numbered family in the
chain. If the chain contains XC5200 devices, the lead
device cannot be XC4000, XC3000 or XC2000; if the chain
contains XC4000 devices, the lead device cannot be
XC3000 or XC2000; if the chain contains XC3000, then the
lead device cannot be XC2000. The reason is shown in Figure 2. Since all devices in the chain store the same lengthcount value and generate or receive one common
sequence of CCLK pulses, they all recognize length-count
match on the same CCLK edge. The master device then
generates additional CCLK pulses until it reaches its finish
point F. As shown in Figure 2, the different families generate and require different numbers of additional CCLK
pulses until they reach F. Not reaching F means that the
device has not really finished its configuration process,
although DONE may have gone High, the outputs have
become active, and the internal reset has been released.
For XC4000 and XC5200, not reaching F means that
READBACK cannot be initiated, and most boundary scan
instructions cannot be used. The limitation in daisy-chain
order has been criticized by designers who want to use an
inexpensive lead device in Peripheral Mode, and save the
more precious XC4000 1/0 pins. Here is a solution for that
case (Figure 3):
One CLB and one lOB in the lead XC3000 device are used
to generate the additional CCLK pulse required by the
XC4000 devices. When the lead device releases its internal
reset signal, the 2-bit shift register starts responding to its
clock input, and it generates an active Low output signal for
the duration of one clock period. An external connection
between this lOB pin and the CCLK pin thus creates the
extra CCLK pulse. This solution requires one CLB, one lOB
and pin, and an internal clock source with a frequency of up
to 5 MHz. Obviously, the XC3000 lead device must be con-
13-34
Figure 3: Additional CCLK-Pulse Generator
figured with late internal reset, which happens to be the
default option.
Configuration Modes
There are six different configuration modes, hardwareselected by applying logic levels to the three mode inputs,
MO, M1, and M2. The six modes are: Master Serial, Master
Parallel Up, Master Parallel Down, Synchronous Peripheral
(XC4000 and XC5200 only), Asynchronous Peripheral, and
Slave Serial. A seventh mode, Express Mode, is only available in XC5200 devices, and is not described here.
In Master modes, the FPGA addresses an external PROM
or EPROM storage device, and reads data from it. No additional timing or control signals are used.
In Peripheral mode, the FPGA accepts byte-wide data (bitserial in XC2000), and interacts with the source of data,
usually a microprocessor, with a ReadylBusy handshake.
In Slave mode, the FPGA receives bit-serial data and a
clock from an external data and timing source, either from a
microprocessor, or from the lead device in an FPGA-daisy
chain.
The modes are selected by putting the appropriate logic
levels on the three mode inputs, MO, M1, and M2 prior to
the beginning of configuration. These three pins can be
hardwired to Vee or Ground, but they can then never be
used as user 1/0. It is better to force a mode pin Low with a
3 kQ pull-down resistor to ground, acting against the 20 to
100 kQ internal pull-up reSistor, and to rely on the built-in
pull-up resistor to establish a High level on the M1, M2
mode pins, but use a 50 kQ external pull-up resistor on MO.
This eliminates the restrictions on using mode pins for user
logic or readback.
When mode pin levels are driven by external logic, these
levels must be established very soon after power-up.
Establishing a mode level too late might eliminate the extra
master power-on delay that makes a master wait for slave
devices to be ready after power-on. Delaying mode levels
until the beginning of configuration will obviously cause the
XAPP 090 November 24, 1997 (Version 1.1)
~XILINX
configuration to fail. Note that some CPLD devices have
surprisingly long power-up delays. Be very careful when
controlling mode levels in any creative way.
o
o
Selecting the Best Configuration Mode
The selection of the most appropriate configuration mode is
influenced by many factors, like
o
o
o
o
the need for interface simplicity,
the need for rapid configuration,
the need for multiple configuration sources,
the availability of a microprocessor-based configuration
driver.
o
o
The simplest interface is Master Serial, using only two
FPGA pins, CCLK and DIN, and no external timing or control signals.
The fastest configuration mode is Slave Serial or XC4000/
XC5200 Synchronous Peripheral. In these modes, the user
can supply a well-defined CCLK frequency of up to 10 MHz
for 5-Volt devices. Only Express mode can be faster than
that. For prototyping and rapid configuration change, the
PC can configure the FPGA directly in Slave Serial mode,
using the Xilinx-provided Download Cable or XChecker.
o
Multiple configuration codes are most conveniently stored
in a microprocessor memory, using Peripheral mode to
configure the FPGA. Peripheral mode also offers the greatest flexibility for field upgrades. New files can be supplied
via diskette or modem, and can be downloaded by the
microprocessor.
When Configuration Fails
General Debugging Hints for all Families
o
o
If the DONE output does not go High, there are several
things to check.
o
Checking all supply and configuration-related pins with
an oscilloscope or logic analyzer can reveal wiring
errors, bad socket pins, noisy ground, noisy CCLK, a
serial configuration PROM's V pp pin not connected to
Vee, PWRDWN not pulled High, poor or noisy RESET,
o
missing pull-up resistors on DONE (or INIT in the
XC3000), bad levels on mode pins, etc. Check all pins:
Any dc voltage between 0.5 V and 3.0 V is a sign of
serious trouble.
Monitor the DOUT pin of the lead device, i.e. the FPGA
that is either configured alone, or forms the beginning of
a daisy chain. At the start of configuration, you should
see the 40 (or 48)-bit header shown in Figure 1. After
this sequence, the DOUr pin remains High until the
device has received all its data. Then, the device
becomes transparent and passes additional data
(provided there is a daisy chain) through the DOUT pin
to the Slave devices. If you don't see this pattern, you
have a gross error somewhere. Check the following
XAPP 090 November 24, 1997 (Version 1.1)
o
items:
INIT going Low again after configuration start indicates
a configuration bitstream or framing error.
If RESET is used to delay configuration, make sure it
has a rise time of <100 ns and that it is glitch-free.
Ringing on the CCLK line, caused by pc-board
reflections, can result in spurious double- clocking and
loss of frame synchronization in the FPGA.
Configuration functions can be disrupted by signal
contention between configuration inputs and the FPGA
user outputs which become active at the end of
configuration. This change is indicated by I/O pins
going active and HDC/LDC no longer at their
configuration levels. Contention can be avoided by
rearranging pin-outs, maintaining additional 3-state
control of user-I/O outputs, or matching start-up output
levels to the configuration input levels on inputs other
than chip-select. As a last resort, it is also possible to
use a series resistor (1-10 kQ) to provide isolation
between conflicting signal sources that could occur
after configuration is complete.
If an FPGA heats up significantly, this is usually the
result of applying the wrong bitstream, e.g. the
bitstream for a different device, causing contention.
Legitimate bitstreams have been screened by the
Design Rule Checker software, and are guaranteed free
of inherent contention problems, provided the
configuration is loaded into the designated device. The
user can obviously still cause contention on internal
Longlines and on connections outside the device.
During reprogramming, user logic must generate a
time-out that insures all devices have completed the
Clear cycle before any configuration data is sent.
Removing the FPGA supply voltage while externally
powered signals continue to drive input pins, might
keep the FPGA Vee pins at a 0.5-to-2.0 V level, which
can leave the FPGA in an invalid state. The FPGA
input-protection diodes are there to clamp input-voltage
excursions to the two supply connections, When the
FPGAsupply voltage falls more than 0.5 V below an
active input signal, this input signal will supply
degenerate Vee levels. If the input signals are not
current-limited, the FPGA inputs can even be damaged
by the excessive input current.
If extraneous CCLK pulses are applied after Clear but
before the beginning of the header, they are counted
internally, and the internal clock count will then become
. equal to the stored length-count value before the
configuration data is completely loaded. In this case,
the DONE output does not become active until the clock
counter equals length count a second time. This
requires 224 extra clocks, about 20 s at the typical rate of
0.7 MHz, or about 2 seconds at the nominally 8-MHz
fastest CCLK rate. Whenever configuration takes
several or many seconds, this is due to. a mismatch
between length count and the number of CCLK pulses
13-35
I
FPGA Configuration Guidelines
•
•
received.
XChecker or the XACT Download Cable provide an
alternate method of configuration to verify configuration
data and to isolate wiring errors, such as interchanged
or inverted configuration data or control signals.
Try a different device. Although the chips are 100%
factory-tested, an individual device might have been
damaged after the test.
General Debugging Hints for the XC2000
and XC3000 Families
•
•
•
•
An undefined (floating) or active low PWRDWN during
configuration can disturb the operation. A low level on
PWRDWN immediately before the start of configuration
causes problems in XC2000, forces XC3000 into Slave
mode, but is acceptable in XC3000A and L.
In the XC2000 and XC3000 families, the configurationclock input signal drives quasi-static circuitry that does
not function correctly with a low time of more than 5
ms.
At power-up, make sure Vee rises in 25 ms or less. If
this cannot be guaranteed, hold RESET active on the
FPGAs and on the serial PROMs until Vee has reached
4.5V.
A slowly rising or noisy RESET can cause multiple
FPGAs to get out of synchronization. Always debounce
reset switches.
General Debugging Hints for the XC4000
and XC5000 Families
•
•
At power-up, make sure Vee rises in 25 ms or less. If
this cannot be guaranteed, hold PROGRAM or INIT
active low on the FPGAs and hold the serial PROMs
reset until Vee has reached 4.5 V.
The boundary scan input pins are active during
configuration, even if boundary scan is not used in the
design. Toggling TCK, TMS and TDI during
configuration might send the device into EXTEST
mode, which interferes with configuration. Keeping at
least one of these three inputs continuously High during
configuration avoids this problem.
•
FPGA output.
Verify that the FPGA is sending addresses to the
PROM. If it is not, check the FPGA mode pins.
MO
MO
=0, M1 =0, M2 = 1 for Master Parallel Up
=0, M1 =1, M2 = 1 for Master Parallel Down
Make sure Vee, RESET and PWRDWN are close to
Vee and all ground pins are at 0 V.
•
•
•
•
•
Check that the PROM is receiving addresses and is
sending out data. If it is not, check that the PROM is
enabled and has Vee and ground connected, and verify
that the PROM is programmed with the correct data.
Check for contention between the PROM address or
data pins and other signals on the board.
Check that the FPGA is addressing the correct memory
segment. In Master Parallel Up mode, the FPGA starts
at address 0000 hex and counts up; in Master Parallel
Down mode it starts at address FFFF hex (3FFFF hex
in XC4000) and counts down. If the PROM requires
different addressing, that must be taken care of by
external hardware.
Check for ringing and noise on address and data lines.
Make sure the data in the PROM is correct. You can
check it against the Rawbits file.
Master Serial Mode
•
•
Review the general debugging hints.
Verify that the FPGA is generating a clock signal on its
CClK pin and that this signal is reaching the ClK pin of
the XC1700-series Serial-Configuration PROM. If it is
not, check the mode pins.
MO = 0, M1 = 0, M2 = 0 for Master Serial mode
•
Verify that the XC1700-series Serial Configuration
PROM is sending data. If it is not, check that power and
ground are applied to the Serial PROM, and Vpp is
connected to Vee.
Do Not Let the Vpp Pin Float
Additional Mode-Specific Debugging Hints
for All Families
A floating Vpp pin results in temperature-dependent
operation, the most notorious cause of unreliable configuration.
Master Parallel Up and Down Mode
•
•
•
•
Review the general debugging hints.
Check that the PROM data pins are connected to the
FPGA input pins DO-D7. Check that the PROM address
pins are connected to the FPGA output pins AO-A 15.
Verify that all these connections are in the right order.
Monitor the FPGA pins, not the socket pins. Make sure
the socket is good.
If the PROM is dedicated to the FPGA, the CS and OE
PROM inputs should be driven from the DONE or lDC
13-36
•
•
Check that the DATA pin of the Serial PROM is
connected to the DIN pin of the FPGA, and that the
PROM is enabled with CE low and OE active. Note that
the OE/RESET pin is programmable for either polarity.
Check whether this pin is driven from the INIT output.
This is the preferred method of guaranteeing SPROM
reset.
Verify that the PROM is programmed with the correct
data.
At power-up, make sure Vee rises from 2.0 V to 4.5 V in
XAPP 090 November 24, 1997 (Version 1.1)
-----
---~---~
~XILINX
signals on the board. Except in XC2000, data is
received as eight bits in parallel. Make sure bit 0 is
connected to the DO pin, bit 1 to D1 pin, etc. (In XC2000
family, data is received serially. If a PROM
file is used as a data source, check that data is properly
serialized LSB first. Data must be LSB first, although
length count is MSB first. This is not intuitively obvious.)
less than 25 ms. If it does not, hold the FPGA RESET
and the PROM RESET active until Vee reaches 4.5 V.
A typical result of a slow Vee rise time is that the FPGA
•
sends out CCLK continuously, the CEO pin on the
PROM(s) goes Low, but the DONE pin never goes
High.
If you abort configuration by asserting XC3000 RESET
or by pulling XC4000/XC5000 PROGRAM Low, you
must also reset the serial PROM by asserting its
RESET. This occurs automatically if the SROM is reset
from INIT.
Slave Serial Mode
•
•
MO =1, M1 = 1, M2 = 1 for Slave Serial mode
Asynchronous Peripheral Mode
•
•
Review the general debugging hints.
Check the mode pin levels.
MO = 1, M1 = 0, M2 = 1 for Peripheral mode
•
•
•
•
•
Use an external 1 kilohm resistor from READY/BUSY
pin to ground. On power-up, before the FPGA has
interrogated the mode lines, this prevents the pin
from being pulled High by its internal pull-up, which
would give an early erroneous READY signal.
Verify that the FPGA is receiving data at its input pints)
and that it is receiving valid Write-Strobe and ChipSelect signals. If not, check the device driving the
FPGA. Make sure that these signals meet the timing
requirements listed in the product family
documentation. XC3000 Family: Check that the
minimum Write-Strobe active time (TeA min = 100 ns) is
met and observe the RDY/BUSY signal. XC2000
Family: Be sure maximum and minimum Write-Strobe
active times (TeA max = 5.0 ms, min = 0.25 ms) are
met.
Make sure that the FPGA is ready to receive data.
XC3000 Family: On power up, make sure that the INIT
pin has gone High, or wait at least 34 ms before you
begin sending data to the FPGA. Make sure that the
RDY/BUSY signal is High before sending each data
byte. XC2000 Family: On power up, make sure that the
FPGA has had time to "wake up," at least 34 ms, before
sending it data.
Check for contention between the Chip Select and
Write Strobe signals and monitor the levels on those
pins after configuration. It is safest to use the Chip
Select pins only as inputs after configuration. Avoid
contention if they are used as outputs. With XC2000
family devices, the lias become active before the FPGA
receives its final data bits and clocks, and also before
the DONE pin goes High. In other families, this relative
timing is programmable. If the user function for any of
the Chip Selects or the Write Strobe become outputs
after configuration, they might contend and, in ellect,
de-select the FPGA so that it never receives its final
data bits. Beware of contention!
Check for contention between the FPGA pins and other
XAPP 090 November 24, 1997 (Version 1.1)
Review the general debugging hints.
Check the mode pin levels.
•
•
•
•
•
See schematics in the data sheet for the FPGA family.
Make sure Vcc, RESET, and PWRDWN are at 5 V, and
ground pins are at 0 V.
Verify that the FPGA is receiving data on DIN and that it
is receiving a valid clock signal on CCLK. Check the
device sending the data. Check the device sending the
clock signal, and make sure the clock meets the timing
requirements specified in the product family
documentation. Don't violate the XC3000 and XC2000
CCLK Low time specification of 5.0 Ils. A CCLK
generated by a Master FPGA automatically meets the
timing requirements.
Make sure the FPGA is ready to receive data.
XC3000 Family: On power up, make sure the TNft pin
is High or wait at least 34 ms before you begin sending
data to the FPGA.
XC2000 Family: On power up, make surEl that the
FPGA has had time to "wake up" at least 34 ms, before
sending it data.
At power up, make sure Vee rises from 2.0 V to 4.5 V in
less than 25 ms. If it does not, hold RESET Low until
the Vee pins reach 4.5 V.
Daisy Chain Debugging Hints
•
•
•
•
•
The key to debugging daisy-chain configurations is to
isolate the problem and attempt to configure a single
FPGA. Remove all but the first device from the board
and configure it. Then insert the second device and
configure both. Repeat as you add one device at a time
until they all configure.
The first device in the chain can be in any of the
configuration modes. Debug it first, using the hints
provided for the appropriate mode.
All devices after the first one are in Slave Serial mode,
so refer to the Slave Serial mode debugging hints
above to solve any problems with Slave device.
Monitor the DOUT pin of each device in the chain and
verify that the 40-bit header (48-bit with XC5200 as the
lead device) appears at the beginning of configuration,
staggered by one CCLK period per device.
If the Master device in the chain is an XC2000-family
device and the Slaves are XC3000-family, make sure
13-37
I
FPGA Configuration Guidelines
the XC3000-family devices are configured with early
DONE.
Potential Length-Count Problem in Parallel
or Peripheral Modes
It is highly desirable that the complete change from configuration to user operation occur as the result of one single
byte-wide input. The activation of outputs and DONE, the
de-activation of the global reset (set/reset in XC4000), and
the progression to the "finished" state F (see Figure 2)
should all occur as a result of one common byte input.
Under normal circumstances, the software achieves this by
manipulating the length-count value appropriately, taking
into account the additional bits between devices, and
adjusting for the fact that byte-wide interfaces always leave
the last bit sitting in the P-S converter, shifting it out at the
beginning of the next byte. These complexities, combined
with the many possible daisy-chain arrangements have
occasionally led to problems, where the device outputs go
active before the last required byte had been received. This
has sometimes lead to contention on the address outputs
or data inputs and might prevent the device from going
DONE, or reaching the real end of its configuration
sequence. Not reaching this ''finished'' state limits the use
of read back and boundary scan. A new option solves this
problem:
The default option is "Length-Count aligned" which adjusts
the length-count value such that length-count match occurs
during the first bit in the last configuration byte. This
assures sufficient CCLK pulses to complete any selected
type of start-up sequence. The other option is "DONEaligned", which adjusts the length count value to make
DONE go active at the end of a configuration data byte,
which can cause problems in Peripheral mode.
Only Peripheral modes seem to be sensitive to the difference between these two options.
Miscellaneous Notes
CCLK is the most important configuration signal. Once the
INIT output is High, each device counts every Low-to-High
transition of this configuration clock. In all modes except
Slave Serial and Synchronous Peripheral, CCLK is a very
fast output that cannot be made slew-rate limited. (it is now
slew-rate limited in the newest XC4000X and XC5200
devices). When distributing this clock, the user should pay
special attention to glitches, overshoots, and undershoots.
In severe cases, a 33 n resistor in series with the CCLK
output might improve the signal integrity. In other cases, it
might be better to provide a pull-up resistor at the far end of
the CCLK net. Since the clock net has a transmission-line
characteristic impedance of always less than 100 n, the
limited output drive capability of the CCLK output precludes
proper parallel termination.
DOUT is an excellent observation point, since every device
must output the preamble on this pin, irrespective of the
selected configuration mode, and irrespective of the position in, or the existence of, a daisy chain.
INIT of all devices in a daisy chain. should be interconnected to prevent the configuration from starting before all
devices are ready. A 10 kQ pull-up resistor is recommended. The parallel INIT of the daisy-chained devices
must be connected to the INIT of the lead XC4000IXC5200
device, or to the RESET input of the lead XC3000 device.
This is especially important for re-configuration, where the
master does not have a four-times longer wait period.
The DONE output indicates the end of the configuration
process. In XC2000 and XC3000 systems, it makes sense
to ground DONE permanently. The RESET input then
becomes the reconfiguration input, and cannot be used as
the dedicated asynchronous user RESET input. LDC can
be used to indicate end of configuration.
PWRDWN(on XC2000 and XC3000 devices) must be High
before and during. the configuration process.
Don't let PWRDWN float!
13-38
XAPP 090 November 24, 1997 (Version 1.1)
APPLICATION NOTE
Configuring Mixed FPGA
Daisy Chains
XAPP 091 November 24, 1997 (Version 1.0)
Application Note by Peter Alfke
Overview
Xilinx FPGAs can be configured in a common daisy-chain
structure, where the lead device generates CCLK pulses
and feeds serial configuration information into the next
downstream device, which in turn feeds data into the next
downstream device, etc. There is no limit to the number of
devices in a daisy chain, and XC2000, XC3000, XC4000,
and XC5200 series devices can be mixed freely with only
one constraint: the lead device must be a member of the
highest-order family used in the chain. (For the purposes of
this discussion, there is no difference between the XC4000
series and the XC5200 family, when XC5200 is used in any
configuration mode except Express Mode). The lead
device must generate a sufficient number of CCLK pulses
after length-count-match was achieved, but XC3000-series
devices generate fewer CCLK pulses than XC4000-series
or XC5200-family devices require, and XC2000 devices
generate even fewer CCLK pulses after length-count
match. See Figure 1.
In a daisy-chain, all CCLK pins are interconnected, and
DOUT of any upstream device feeds the DIN input of its
downstream neighbor. Those are the basic connections.
For control purposes, it is advisable to interconnect all the
slave INIT pins (the XC2000 does not have this pin) and
connect them to the INIT pin of the lead XC4000/XC5200
device or the RESET input of the lead XC3000 device.
Interconnected INIT pins prevent the master from starting
the configuration process until all slaves are ready. For
power-up this is assured automatically, since the master
uses four times as many internal clocks for the power-up as
any slave does, but, when re-configuring, master and slave
devices consume the same number of clocks to clear a
frame, and a fast master might be ready before a slow slave
is. Interconnecting INITs solves this problem.
I
The DONE/PROG (DIP) and RESEf pins (XC2000,
XC3000) and the XC4000/XC5200 PROGRAM pins can be
used in different ways, depending on the designer's preferences regarding reconfiguration, pin utilization, and need
for a global RESET input.
If there is no need for a global logic RESET input, then it is
best to permanently ground the XC2000/3000 DIP pin,
which means that the RESET input functions as the Reconfigure input, and should be connected to all XC40001
XC5200 PROGRAM inputs.
Note: Thick lines are default option
F"", Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
Heavy lines describe
default timing
X5972
Figure 1: Start-up Timing
XAPP 091 November 24, 1997 (Version 1.0)
13-39
Configuring Mixed FPGA Daisy Chains
REPROGRAM
put) and that, if Serial mode is chosen for the lead device,
the XC1700 device(s) store only one configuration for the
whole daisy chain. The serial PROM(s) must, therefore, be
reset before the daisy chain is to be (re)programmed.
All DIP
>---.--4----. To
Wired Together
)o-+--~ To All RESET, Except
Lead Device
From AIlINIT
Pins Wired
Together
------<:J
)o---~
To RESET of
Lead Device
X5982
There are three possible types of daisy chains using
XC3000 and XC4000IXC5200 devices. Here are the recommended connections for the configuration control pins.
Case 1:
Daisy chain consists of nothing but XC3000-series
devices:
Figure 2:
Use lead device's LDC to drive XC1700 CEo
If there is a need for a global logic RESET input that can
reset all flip-flops in the user logic without causing reconfiguration, then external logic must combine RESET and Dip
in such a way, that pulling Low RESET does not affect DiP,
but pulling Low DIP also pulls down RESET. See Figure 2.
Use lead device's INIT to drive XC1700 RESET.
The following simple recommendations guarantee a welldefined beginning for any FPGA configuration or reconfiguration process, after the initialization and clearing of the
configuration memory in all FPGAs has been completed,
and the address counter in the serial PROM(s) has been
reset.
The connections described below guarantee reliable operation even under adverse operating conditions such as Vee
glitches.
The lead device can use any configuration mode available.
In all modes except Slave Serial, its CCLK pin is the output
that clocks all other devices.
Obviously, all CCLK and XC1700 CLK pins must be interconnected, the DATA outputs from multiple XC1700 serial
PROMs must be interconnected and connected to the DIN
input of the lead device, and the daisy-chain must be established by connecting each DOUT output to the downstream
DIN input.
Interconnect all slave INITs and connect them to the lead
RESET input.
Interconnect all DONE pins.
Interconnect all slave RESET inputs
Instigate Reprogram by pulling the slave RESET net Low
for at least 6 its while all DONE pins are Low.
(DONE can be permanently wired Low, but that sacrifices
the use of RESET as a global reset of the user logic. If
DONE is not wired Low, reprogram must pull DONE Low
with an open-collector or open-drain driver).
Case 2:
Lead device is XC4000-series or XC5200 family, driving
any mixture of XC3000, XC4000 and XC5200 devices:
Use lead device's LDC to drive XC1700 CE.
Use lead device's INIT to drive XC1700 RESET.
Interconnect all INIT pins.
Interconnect all DONE pins.
Interconnect all XC4000/XC5200 PROGRAM inputs.
Interconnect all XC3000RESET inputs.
Configuration control pins are:
Combine these two nets into one PROGRAM/RESET net
XC3000A, XC3000L, XC31 00, XC3100A:
Instigate Reprogram by pulling the combined PROGRAM/
RESET Low.
DONE/PROGRAM (open-drain output/input)
RESET (input)
INIT (open-drain output)
XC4000 Series (XC4000E, XC4000X) and XC5200 family:
DONE (open-drain output / input)
PROGRAM (input)
INIT (open-drain output / input)
XC1700:
RESET (input with programmable polarity)
The following recommendations assume that there are no
XC2000 devices in the daisy chain (they lack the INIT out-
13-40
Case 3:
Daisy chain consists of nothing but XC40001 and
XC5200-type devices:
Use lead device's LDC to drive XC1700 CE.
Use lead device's INIT to drive XC1700 RESET.
Interconnect alilNIT pins.
Interconnect all DONE pins (only required for UCLK-SYNC
option).
Interconnect all XC4000/XC5200 PROGRAM inputs.
Instigate Reprogram by pulling PROGRAM Low.
XAPP 091 November 24, 1997 (Version 1.0)
APPLICATION NOTE
Configuration Issues:
Power-up, Volatility, Security,
Battery Back-up
XAPP 092 November 24, 1997 (Version 1.1)
Application Note by Peter Alfke
Summary
This application note covers several related subjects: How does a Xilinx FPGA .powe~ up, and how does it react to P?we.rsupply glitches? Is there any danger of picking up erroneous data and co~flguratl?n? .What can be don.e to .m~ntaln
configuration during loss of primary power? What can be done to secure a design against Illegal reverse-engineering.
Xilinx Families
XC2000, XC3000, XC4000, XC5200
Power-Up
Here is a detailed description of XC3000 Series, XC4000
Series and XC5200 device behavior during supply ramp-up
and ramp-down.
When Vee is first applied and is still below about 3 V, the
device wakes up in the pre-initialization mode. HOC is High;
INIT, LDC and DONE or DONE/PROG (DIP) are Low, and
all other outputs are 3-stated with a weak pull-up resistor.
When Vee has risen to a value above -3 V, and a 1 and a
into two special cells in
the configuration memory, the initialization power-on time
delay is started. This delay compensates for differences in
Vee detect threshold and internal CCLK oscillator frequency between different devices in a daiSy chain. The in itializationdelay counts clock periods of an on-chip
oscillator (CCLK) which has a 3:1 frequency uncertainty
depending on processing, voltage and temperature. Timeout, therefore, takes between 11 and 33 ms for a slave
device, four times longer for a master device.
o have been successfully written
This factor of four makes sure that eventhe fastest master
will always take longer than any slave. We assume that the
worst- case difference between 33 ms .and 4 x 11 ms is
enough to compensate for the Vee rise time spent between
threshold differences (max 2 V) of.devices in a daisy chain.
Only in cases of very slow Vee rise time (>25 ms), must the
user hold RESET Low until Vee has reached a proper level.
Interconnecting the iNfT'pins of all devices in a daisy-chain
is a better method of synchronizing start-up, but cannot be
used with XC2000 devices, since they lack an INIT pin.
After the end of the initialization time-out, .each device
clears its configuration memory in a fraction. of a millisecond, then tests for inactive RESET or PROGRAM, stores
the MODE value and starts the configuration process, as
described in the Data Sheet. After the device is configured,
the 5-V Vee may dip to about 3.5 V without any significant
consequences beyond an increase in delays (circuit speed
XAPP 092 November 24, 1997 (Version 1.1)
is proportional to Vee), and a reduction in output drive. If Vee
drops into the 3-V range, ittriggers a sensor that forces the
device back to the pre-initialization mode described above.
All flip-flops are reset, HOC goes High; iNfT', LDC and DIP
or DONE go Low, and all other outputs are 3-stated with a
weak resistive pull-up. If Vee dips substantially lower, the
active outputs become weaker, but the device stays in this
preinitialization mode. When Vee rises again, a normal
configuration process is initiated, as described above.
Sensitivity to Vee Glitches
The user need not be concerned about power supply dips:
The XC3000/XC4000/XC5200 devices stay configured for
small dips and they are "smart enough" to reconfigure
themselves (if a master) or to ask for reconfiguration by
pulling INIT and DIP or DONE Low (if a slave). The devices
will not lock up; the user can initiate re-configuration at any
time just by pulling DIP or PROGRAM Low or, if DIP is Low,
by forcing a High-to-Low transition on RESET.
Any digital logic device with internal data storage in latches
or flip,flops is sensitive to power glitches. This includes
every RAM, microprocessor, microcontroller, and peripheral circuit. Only purely combinatorial circuits can be guaranteed to survive a severe power glitch without any
problem.
Xilinx SRAM-based FPGAs store their configuration in
latches that lose their data when the supply voltage drops
below a critical value (which is substantially below 3 V for
the 5c V devices), but configuration data is extremely robust
and reliable while Vee stays above 3 V. All Xilinx configuration latches are implemented as cross-coupled. complementary inverters with active pull-down n-channel
transistors and active pull-up p-channel transistors. Both
High and Low logic levels have an impedance of less than
5kQ with respect to their respective supply rail.
Typical SRAM memory devices use passive poly-silicon
pull-up resistors with an impedance of about 5,000 MQ A
13-41
I
Configuration Issues: Power-up, Volatility, Security, Battery Back-up
current of one nanoamp (!) is sufficient to upset the typical
SRAM cell, whereas it takes a million times more current to
upset the Xilinx configuration latch.
This does not mean that SRAMs are unreliable, it just
shows that the levels in Xilinx configuration latches are six
orders of magnitude more resistant to upsets caused by
external events, like cosmic rays or alpha particles. Xilinx
has never heard about any occurrence of a spontaneous
change in the configuration store in any of its -50 million
FPGA devices sold over the past twelve years.
Whereas most digital circuits rely on Vee staying within
specification, Xilinx FPGAs have an internal voltage monitoring circuit. For example, in the 5-Volt devices, whenever
the supply voltage dips below 3 V, the internal monitoring
circuit causes the Xilinx FPGA to stop normal operation. All
outputs go 3-state, and the device waits for the supply voltage to rise closer to 4 V, when it either demands (slave or
peripheral mode) or initiates (master mode) a reconfiguration. In the range between 5.5 and 3 V, all typical CMOS
devices maintain their functionality and their data storage,
they just get slower as the voltage goes down.
Xilinx has made sure that the FPGA cannot be corrupted by
a power glitch. The most sensitive circuit is the low-voltage
detector. It kicks in while all other configuration storage and
user logic is still guaranteed to be functional. The voltagemonitoring feature in the Xilinx device can even be used to
protect other circuitry, or it can be coordinated with external
monitoring circuits.
There is no possibility of a Vee dip causing the device to
malfunction, i.e., to operate with erroneous configuration
information.
•
•
If Vce stays above the trip point, the device functions
normally, albeit at reduced speed, like any other CMOS
device.
If Vee dips below the trip point, the device 3-states all
outputs and waits for reconfiguration.
Xilinx production-tests the Vee-dip tolerance of all XC3000
devices in the following way.
After the device is configured, Vee is reduced to 3.5 V, and
then raised back to 5.0 V. Configuration data is then read
back and compared against the original configuration bit
stream. Any discrepancy results in rejection of the device.
Subsequently, Vee is reduced to 1.5 V and then raised to
5.0 V. The device must first go 3-state, then respond with a
request for reconfiguration.
Both these tests are performed at high temperature (>85°C
for commercial parts, >100°C for military). Any part failing
any of these tests is rejected as a functional failure.
tor or other control register due to an undetected power
glitch, with disastrous consequences to the subsequent
operation. A Xilinx FPGA detects the power glitch and
always plays it safe by flagging the problem.
No complex system of any kind can function reliably when
Vee is unreliable. Xilinx FPGAs do the safest thing possible,
whenever such problems occur.
Design Security
Some Xilinx customers are concerned about the security of
their designs. How can they protect their designs against
unauthorized copying or reverse-engineering?
We must distinguish between two very different situations:
•
Configuration data in accessible from a serial or parallel
EPROM or in a microprocessor's memory. This is the
normal case.
• Configuration data is hidden from the user, since the
design does not permanently store a source of
configuration data. After the FPGA was configured, the
EPROM or other source was removed from the system,
and configuration is kept alive in the FPGA through
battery-back-up.
Design Security when Configuration Data is
Accessible
In the first case, it is obviously very easy to make an identical replica of the design by copying the configuration data
and the pc-board interconnect pattern of the standard
devices, but it is virtually impossible to interpret the bitstream in order to understand the design or make intelligent modifications to it. Xilinx keeps the interpretation of
the bitstream a closely guarded secret. Reverse-engineering an FPGA would require an enormously tedious analysis
of each individual configuration bit, which would still only
generate an XACT view of the FPGA, not a usable schematic.
The best protection against a mindless copy is legal. The
bitstream is easily protected by copyright laws that have
proven to be more successfully enforced than the intellectual property rights of circuit designs.
The combination of copyright protection, and the almost
insurmountable difficulty of creating any design variation for
the intended function, provides good design security. The
recent successes of small companies in reverse-engineering microprocessors and microprocessor support circuits
show that a non-programmable device can actually be
more vulnerable than an FPGA. For advice on legal protection of the configuration bitstream, see the following paragraphs.
As a result of these careful precautions, we contend that
Xilinx FPGAs are safer than all other types of circuitry
(except purely combinatorial circuits). A microprocessor
can loose the content of its address register, its accumula-
13-42
XAPP 092 November 24, 1997 (Version 1.1)
~XIUNX
Legal Protection of Configuration Bit-Stream Programs
The bit-stream program loaded into the FPGA may
qualify as a "computer program" as defined in Section
101, Title 17 of the United States Code, and as such
may be protectable under the copyright law. It may also
be protectable as a trade secret if it is identified as
such. We suggest that a user wishing to claim copyright and/or trade secret protection in the bit stream
program consider taking the following steps.
Place an appropriate copyright notice on the FPGA
device or adjacent to it on the PC board to give notice
to third parties of the copyright. For example, because
of space limitations, this notice on the FPGA device
could read "©1996 XYZ Company" or, if on the PC
board, could read "Bit Stream ©)1996 XYZ Company".
File an application to register the copyright claim for the
bit-stream program with the U.S. Copyright Office.
If practicable, given the size of the PC board, notice
should also be given that the user is claimingthat the
bit- stream program is the user's trade secret. A statement could be added to the PC board such as: "Bitstream proprietary to XYZ Company. Copying or other
use of the bitstream program except as expressly authorized by XYZ Company is prohibited."
To the extent that documentation, data books, or other
literature accompanies the FPGA-based design, appropriate wording should be added to this literature provid'
ing third parties with notice of the user's claim of
copyright and trade secret in th.e bit-stream program.
For example, this notice could read: "Bit-Stream©) 1996
XYZ Company. All rights reserved. The bit-stream program is proprietary to XYZ Company and copying or
other use of the bit- stream program except as expressly authorized by XYZ Company is expressly prohibited."
To help prove unauthorized copying by a third party, additional nonfunctional code should be included at the
end ofthe bit-stream program. Therefore, should a third
party copy the bit-stream program without proper authorization, if the non-functional code is present in the
copy, the copier cannot claim that the bit-stream program was independently developed.
These are only suggestions, and Xilinx makes no representations or warranties with respect to the legal
effect or consequences of the above suggestions.
Each user is advised to consult legal counsel with
respect to seeking protection of a bit-stream program
and to determine the applicability of these suggestions
to the specific circumstances.
If the user has any questions, contact the Xilinx legal
department at 408-879-4984.
XAPP 092 November 24, 1997 (Version 1 .1)
Design Security by Hiding the
Configuration Data
If the design does not contain the source of configuration
data, but relies on battery-back-up of the FPGA configuration, then there is no conceivable way of copying this
design. Opening up the package and probing thousands of
latches in undocumented positions to read out their data
without ever disturbing the configuration is impossible.
This mode of operation offers the ultimate design security.
It is being used by several Xilinx customers who have reason to be concerned about illegal pirating of their designs.
Battery Back-up and Powerdown
Since SRAM-based FPGAs are manufactured using a
high-performance low-power CMOS process, they can preserve the configuration data stored in the internal static
memory cells even during a loss of primary power. This is
accomplished by forcing the device into a low-power nonoperational state, while supplying the minimal current
requirement of Vee from a battery.
Circuit techniques used in XC31 00, XC4000 and XC5200
devices prevent lee from being reduced to the level needed
for battery back-up. Consequently, battery back-up should
only be used for XC2000, XC2000L, XC3000, XC3000A
and XC3000L devices.
There. are two primary considerations for battery backup
which must be accomplished by external circuits.
•
•
Control of the Power-Down (PWRDWN) pin
Switching between the primary Vee supply and the
battery,
Important considerations include the following.
•
•
•
Insure that PWRDWN is asserted logic Low prior to Vee
falling, is held Low while the primary Vee is absent, and
returned High after Vee has returned to a normal level.
PWRDWN edges must not rise or fall slowly.
Insure "glitch-free" switching of the power connections
to the FPGA device from the primary Vee to the battery
and back.
Insure that, during normal operation, the FPGA Vee is
maintained at an acceptable level, 5.0 V ± 5% (±1 0% for
Industrial and Military).
Figure 1 shows a. power-down circuit developed by Shel
Epstein of Epstein Associates, Wilmette, IL. Two Schottky
diodes power the FPGA from either the 5.2 V primary supply or a 3 V Lithium battery. A Seiko S8054 3-terminal
power monitor circuit monitors Vee and pulls PWRDWN
Low whenever Vee falls below 4 V.
13-43
I
Configuration Issues: Power-up, Volatility, Security, Battery Back-up
Things to Remember:
Vee
IN5817
Seiko S8054 Specifications
Detect Voltage 3.995 V min
4.305 V max
Hysteresis
208 mV typ
Temp. Coell. 0.52 mVrC
lee @ + 6V
2.6 flA typ
IN5817
B35
Lithium
Battery
X5997
Figure 1: Battery Back-up Circuit
Powerdown Operation
A Low level on the PWRDWN input, while Vcc remains
higher than 2.3 V, stops all internal activity, thus reducing
lee to a very low level:
o
o
o
o
o
o
All internal pull-ups (on Long lines as well as on the lID
pads) are turned off.
The crystal oscillator is turned off
All package outputs are three-stated.
All package inputs ignore the actual input level, and
present a High to the internal logic.
All internal flip-flops or latches are permanently reset.
The internal configuration is retained.
When PWRDWN is returned High, after Vee is at its
nominal value, the device returns to operation with the
same sequence of buffer enable and Dfp as at the
completion of configuration.
13-44
Powerdown retains the configuration, but loses all data
stored in the device. Powerdown three-states all outputs
and ignores all inputs. No clock signal will be recognized,
and the crystal oscillator is stopped. All internal flip- flops
and latches are permanently reset and all inputs are interpreted as High, but the internal combinatorial logic is fully
functional.
Things to Watch Out for:
Make sure that the combination of all inputs High and all
internal flip-flop outputs Low in your design will not generate internal oscillations or create permanent bus contention
by activating internal bus drivers with conflicting data onto
the same long line. These two situations are farfetched, but
they are possible and will result in considerable power consumption. It is quite easy to simulate these conditions since
all inputs are stable and the internal logic is entirely combinatorial, unless latches have been made out of function
generators.
During powerdown, the Vee monitoring circuit is disabled. It
is then up to the user to prevent Vee dips below 2.3 V,
which might corrupt the stored configuration.
During configuration, the PWRDWN pin must be High,
since configuration uses the internal oscillator. Whenever
Vee goes below 4 V, PWRDWN must already be Low in
order to prevent automatic reconfiguration at low Vee. For
the same reason, Vee must first be restored to 4 V or more,
before PWRDWN can be made High.
PWRDWN has no pull-up resistor. A pull-up resistor would
draw supply current when the pin is Low, which would
defeat the idea of powerdown, where lee is only microamperes.
XAPP 092 November 24, 1997 (Version 1.1)
APPLICATION NOTE
, ~XllINX®
i
Dynamic Reconfiguration
XAPP 093 November 10, 1997 (Version 1.1)
Application Note by Peter Alfke
Introduction
Important Considerations
All Xilinx SRAM-based FPGAs can be in-system configured and re-configured an unlimited number of times. The
XC6200 family has additional features that allow partial and
very fast (re-)configuration from a microprocessor bus. See
the XC62000 product documentation for details.
•
This application note describes the procedures for reconfiguring the more traditional Xilinx FPGAs of the XC3000,
XC4000, and XC5200 families.
All configuration information is stored in latches that are
loaded serially, conceptually like a shift register. There are
several different bit-serial or byte-parallel configuration data
interfaces, selected by logic levels on three mode inputs,
but - with the exception of the XC5200 Express mode they all result in the bit-serial loading of the configuration
latches. The byte-parallel interfaces in Master Parallel and
Peripheral modes act just as an 8-bit parallel-to-serial converter. Between devices in a daisy-chain, the configuration
information is transmitted bit-serially with a common Configuration Clock (CCLK). In Master and Peripheral modes,
CCLK is generated by the lei\l.d FPGA device, in Slave
Serial mode, CCLK comes from an external source.
Reconfiguration of an operational device, or a daisy-chain
of devices, goes through the following sequence of events:
Reconfiguration is initiated by pulling a specific device
pin Low.
• First, all outputs are 3-stated, except HOC = High, LDC
and DONE = Low
• Then, all internal registers, flip-flops and latches, as
well. as the configuration storage latches are cleared.
During this time, the TNif output is being pulled Low.
• Then, the Mode inputs and RESET or PROGRAM
inputs are sampled to determine the selected
configuration mode and whether to startthe new
configuration process, or to wait.
• Then configuration data is accepted and loaded into the
internal latches and distributed through the daisy-chain.
• When all configuration information has been entered,
the user outputs are activated,DONE goes High and
the internal reset is released, all in the order specified in
the configuration bitstream. All devices in a daisy-chain
perform each of these operations in synchronism.
XAPP 093 November 10, 1997 (Version 1.1 )
Reconfiguration is "all or nothing". There is no way to
restrict reconfiguration to a part of the chip (Note that
XC6200 devices do not have this limitation).
• Reconfiguration takes a specific time, determined only
by device type, size and clock speed, independent of
the particular configuration pattern. Configuration takes
from tens to hundreds of milliseconds. During that time,
all user-outputs of the device, or the whole daisy-chain
of devices, are 3-stated with weak internal pull-ups,
except for HOC and LOC, which are active High or Low
respectively.
• All user-data stored in registers, flip-flops or latches is
erased. There is no way to retain data inside the device
from one configuration to the next.
These limitations are absolute. If they are not acceptable,
the user must resort to creative solutions, like piggy-backing multiple devices.
The designer of reconfigurable applications should be
familiar with the normal configuration process of each
device, as described in the individual product descriptions.
There is also pertinent information about daisy-chain operation, especially about mixed daisy chains, in other application notes.
Interconnecting the TNif pins of all devices in a daisy-chain
is mandatory for reconfiguration, since this is the only way
to guarantee that the master device does wait for the rest of
the daisy-chain to be cleared, before starting the reconfiguration. Only the first configuration after power-up makes the
master device spend four times as many clock periods as
any slave during the initial clear operation, so that the master cannot possibly get ahead of the slaves. Reconfiguration, however,does not slow down the master this way, so
the interconnection of all INIT pins must serve tha.t same
purpose.
In Master Serial mode, it is highly recommended that the
active Low level of INIT be used to reset the XC1700-family
Serial PROM.
13-45
I
Dynamic Reconfiguration
Reconfiguration Time
Reconfiguration time is usually more critical than the original power-on configuration time, which is often masked by
the general power-on delays.
Here are some suggestions to reduce reconfiguration time.
•
A daisy-chain is obviously not conducive to fast
configuration, it should be broken up into shorter blocks,
perhaps single devices. Multiple devices can be
configured in parallel, but can still use a common
CCLK, and can also be made to start up together. If the
devices differ in size or family, they should all be given
the same length count as the largest device in the
group.
Configuration Mode
Parallel and Peripheral modes are not any faster than
Master Serial mode, since all modes (with the exception
of XC5200 Express mode) internally operate on serial
data. The internally generated CCLK frequency is
guard-banded to never approach the upper limit of what
the device can tolerate. Therefore, the fastest possible
configuration mode for XC3000 and XC4000-series
devices is Slave Serial, with an external well-controlled
source for CCLK. Its frequency can be up to 10 MHz for
all 5-V devices, and there are ways to increase the
average clock rate well beyond that, but they require
dynamic clock frequency changes and an intimate
understanding of the configuration frame structure.
At 10 MHz, configuration time per device ranges from
1.5 ms for the XC3020A to 42 ms for the XC4025E and
192 ms for the XC4085XL.
• Possible Contention Problems:
Certain user outputs become active during the configuration process:
Address outputs during Master Parallel mode, Chip
Select and Ready/Busy during Peripheral modes.
The designer must make sure that these active outputs
do not cause contention with other logic that might use
the same pins as device inputs.
Initiating Reconfiguration in
Different Xilinx Device Families
XC3000 Series
There are three alternatives:
1. Pull RESET Low while DONE is permanently grounded
externally.
13-46
This is the simplest scheme, but it precludes the use of
RESET to clear the flip-flops and latches in the operating
user-design. RESET must be pulled Low for more than six
microseconds to overcome its internal low-pass filtering.
Configuration starts when RESET has gone High again.
2. Pull DONE Low with an open-drain ("open-collector")
output. This assumes that DONE was High, i.e. that the
previous configuration was successful. Reconfiguration
starts as soon as the internal memory has been cleared.
DONE can be released anytime.
3. Pull DONE Low with an open-drain ("open-collector")
output and pull RESET Low. Keep RESET Low for at least
six microseconds while DONE is Low. DONE can be
released anytime after that, or not released at all. See alternative 1.
XC4000 Series and XC5200 Family
Pull the PROGRAM input Low for at leastO.3 microseconds
to initiate clearing the configuration memory, then pull
PROGRAM up to start the new configuration process.
While PROGRAM is held Low, a Low level on INIT indicates
that the device is continuously clearing the configuration
memory. When PROGRAM has been pulled up, INIT stays
Low during one more clear operation, then goes High.
All device families, except the original XC4000, have a continuously active pull-up resistor on the PROGRAM pin.
FPGAs Can Control Their Own
Reconfiguration
Pulling PROGRAM, RESET or DONE low can trigger a
reconfiguration, as described above. When a user output is
connected to drive the reconfiguration pin, the FPGA can
trigger its own reconfiguration. Although the triggering output will go 3-state once reconfiguration is initiated, this trigger operation is reliable.
Such auto-reconfiguration offers interesting opportunities
for small systems using a single FPGA in Master Parallel
configuration mode. A manually operated switch selects
the most significant address bits olthe PROM, and the
FPGA compares the switch settings against a stored value.
Upon detecting a difference, it can trigger reconfiguration
that is loaded from the newly selected PROM address
range. Or an external CMOS register can be loaded with
the intended reconfiguration address range and then control the upper bits of the PROM address
XAPP 093 November 10, 1997 (Version 1.1)
'
APPLICATION NOTE
I
i
~XllINX®
Metastable Recovery
XAPP 094 November 24, 1997 (Version 2.1)
Application Note By Peter Alike and Brian Philolsky
Introduction
tination might clock in the final data state while the other
does not.
Whenever a clocked flip-flop synchronizes an asynchronous input, there is a small probability that the flip-flop output will exhibit an unpredictable delay. This happens when
the input transition not only violates the setup and hold-time
specifications, but actually occurs within the tiny timing window where the flip-flop accepts the new input. Under these
circumstances, the flip-flop can enter a symmetrically balanced transitory state, called metastable (meta = between).
While the slightest deviation from perfect balance will
cause the output to revert to one of its two stable states, the
delay in doing so depends not only on the gain-bandwidth
product of the circuit, but also on how perfect the balance
is, and on the noise level within the circuit; the delay can,
therefore, only be described in statistical terms.
The problem for the system designer is not the illegal logic
level in the balanced state (it's easy enough to translate
that to either a 0 or a 1), but the unpredictable timing of the
final change to a valid logic state. If the metastable flip-flop
drives two destinations with differing path delays, one des-
With the help of a self-contained circuit, Xilinx evaluated the
XC4000 and XC3000-series flip-flops. The result of this
evaluation shows the Xilinx flip-flop to be superior in metastable performance to many popular MSI and PLD devices.
Since metastability can only be measured statistically, this
data was obtained by configuring several different Xilinx
FPGAs with a detector circuit shown in Figure 1. The flipflop under test receives the asynchronous -1-MHz signal
on its 0 input, and is clocked by a much higher manually
adjustable frequency. The output OA feeds two flip-flops in
parallel, one (OB) being clocked by the same clock edge,
the other (OC) being clocked by the opposite clock edge.
When clocked at a low frequency, each input change gets
captured by the rising clock edge and appears first on OA,
then, after the falling clock edge, on OC, and finally, after
the subsequent rising clock edge, on OB.
If a metastable event in the first flip-flop increases the settling time on OA so much that OC misses the change, but
OB still captures it on the next rising clock edge, this error
Asynchr, Input - - - - 1
Clock----<>-------e-----~--------.-...l
Clock
Asynchr, Input
I
-.ll
////
OB
NO ERROR
Oc
ERROR
ERROR
OD
NO ERROR
X5985
Figure 1: Test Circuit and Timing Diagram
XAPP 094 November 24,1997 (Version 2,1)
13-47
Metastable Recovery
can be detected by feeding the XOR of QB and QC into a
falling-edge triggered flip-flop. Its output (QD) is normally
Low, but goes High for one clock period each time the asynchronous input transition caused such a metastable delay
in QA. The frequency of metastable events can be
observed with a i6-bit counter driven by QD.
By changing the clock frequency, and thus the clock halfperiod, the amount of acceptable metastable delay on the
QA output can be varied, and the resulting frequency of
metastable events can be observed on the counter outputs.
As expected, no metastable events were observed at clock
rates below 70 MHz for the XC400S-6, or below 100 MHz
for the XC400SE-3, since a half clock period at those frequencies is adequate for almost any metastability-resolution delay. Increasing the clock rate slightly brought a
sudden burst of metastable events. Careful adjustment of
the clock frequency gave repeatable, reliable measurements.
Metastability Measurements
The circuit of Figure 1 was implemented in five different Xilinx devices: two cutting-edge devices using O.S micron, 3layer-metal technology, the XC400SE-3 and the XC3i42A09, one device, the XCS206 using 0.6 micron, 3-layermetal, and, for comparison purposes, also in two oldertechnology devices, the XC400S-6 and the XC3042-70.
In each device two different implementations put QA, the
flip-flop under test, into an lOB and a CLB (Except for the
XC5200 family which has no flip-flops in the lOB). The
XC4000-series devices showed little difference between
lOB and CLB behavior, but in the XC3000-series devices,
the lOB flip-flops showed dramatically better metastable
performance than the CLB flip-flops. This difference can be
traced to subtle differences in circuit design and layout, and
will guide us to further improvements in metastable performance in future designs.
Metastable measurement results are listed in Table 1, and
are plotted in Figure 2. The results for XC4000E-3 (lOB and
CLB) and for XC3100A-09 lOB flip-flops are outstanding,
far superior to most metastable data published anywhere
else. When granted 2 or 3 ns of extra settling delay, these
devices come close to eliminating the problems caused by
metastability, since their MTBF exceeds millions of years.
K2 is derived by dividing In 64,000 by the half-period difference.
Table 1: Metastable Measurement Results
Device
XC400SE-3 lOB
XC400SE-3 CLB
XC4005-6 lOB
XC400S-6 CLB
XCS206-S CLB
XC3142A-09 lOB
XC3142A-09 CLB
XC3042-70 lOB
XC3042-70 CLB
FL
(MHz)
111.S
109.0
73.0
71.2
70.8
152.2
107.4
46.6
41.9
FH
Half-period
K2
(MHz) Difference (ns) (11 ns)
131.6
0.685
16.1
124.4
19.4
0.S68
1.294
8.S
90.0
88.8
1.392
7.9
79.8
0.80
13.7
206.6
0.87
12.7
211.3
2.29
4.8
61.S
2.60
4.2
64.8
4.22
2.6
Metastability Calculations
The Mean Time Between Failures (MTBF) can only be
defined statistically. It is inversely proportional to the product of the two frequencies involved, the clock frequency and
the average frequency of the asynchronous data changes,
provided that these two frequencies are independent and
have no correlation.
The generally accepted equation for MTBF is
eK2 *1
MTBF=
F1 * F2 * K1
K1 represents the metastability-catching set-up time window, which describes the likelihood of going metastable.
K2 is an exponent that describes the speed with which the
metastable condition is being resolved. K2 is an indication
of the gain-bandwidth product in the feedback path of the
master latch of the master-slave flip-flop. A small increase
in K2 results in an enormous improvement in MTBF.
With F1 = 1 MHz, F2 = 10 MHz and K1 = 0.1 ns = 10.10 s:
MTBF (in seconds)
= 10-3 •
eK2*1
Experimentally derived (see Table 1):
K2 = 16.1 per ns, for the XC400SE-3 lOB flip-flops
The older-technology devices are obviously less impressive, but they still show acceptable performance, especially
in the lOB input flip-flops that are normally used to synchronize asynchronous input signals.
K2 = 19.4 per ns, for the XC400SE-3 CLB flip-flops
Table 1 lists the experimental results from which the exponential factor K2 was derived. The clock frequency was
adjusted manually, while observing the LSB and the MSB
of the 16-bit error counter. FL is the clock frequency that
generated a -1 Hz error rate, FH generated a -64,000 Hz
error rate.
K2 = 13.7 per ns, for the XC5206-S CLB flip-flops
13-48
K2 = 8.5 per ns, for the XC400S-6 lOB flip-flops
K2 = 7.9 per ns, for the XC4005-6 CLB flip-flops
K2 = 12.7 per ns, for the XC3142A-09 lOB flip-flops
K2 = 4.8 per ns, for the XC3142A-09 CLB flip-flops
K2 = 4.2 per ns, for the XC3042-70 lOB flip-flops
K2 = 2.6 per ns, for the XC3042-70 CLBflip-flops
XAPP 094 November 24, 1997 (Version 2.1)
----------------
---.-~---~---
~XILINX
XC4005E-3 XC4005E-3
CLB
lOB
MTBF
XC5206-5
CLB
XC3142A-09
lOB
XC4005-6
lOB
XC4005-6
CLB
1 Million Years
13
12
11
1,000 Years
10
(/)
9
"0
C
0
0
'"
8
1 Year
(/)
OJ
0
-'
7
6
5
4
1 Day
1 Hour
3
2
0
-1
3
-2
Acceptable Extra Delay (ns)
-3
4
5
6
X5986
Figure 2: Mean Time Between Failure for various lOB and CLB flip-flop outputs when synchronizing a -1 MHz
asynchronous input with a 10 MHz clock_
For other operating conditions, divide MTBF by the product
of the two frequencies. For a -10 MHz asynchronous input
synchronized by a 40 MHz clock, the MTBF is 40 times
XAPP 094 November 24, 1997 (Version 2.1)
shorter than plotted; for a -50 kHz signal synchronized by a
1 MHz clock, the MTBF is 200 times longer than plotted
here.
13-49
II
APPLICATION NOTE
Set-up and Hold Times
XAPP 095 November 24, 1997 (Version 1.0)
Application Brief by Peter Alfke
Introduction
If the receiving device has a hold time requirement, the
source of data must guarantee an equivalent minimum
value for its clock-to-output delay. Almost no IC manufacturer is willing to do this, and in the few cases where it is
done, the minimum value is usually a token 1 ns. Any input
hold time requirement is, therefore, an invitation to system
failure. Any clock distribution skew on the PC-board can
compound this issue and wipe out even the specified short
minimum delay.
Beware of hold-time problems, because they can lead to
unreliable, temperature-sensitive designs that can fail even
at low clock rates.
"Set-up time" and "hold time" describe the timing requirements on the data input of a flip-flop or register with respect
to the clock input. The set-up and hold times describe a
window of time during which data must be stable in order to
guarantee predictable performance over the full range of
operating conditions and manufacturing tolerances.
A positive set-up time describes the length of time that the
data must be available and stable before the active clock
edge. A positive hold time, on the other hand, describes the
length of time that the data to be clocked into the flip-flop
must remain available and stable after the active clock
edge. A positive set-up time limits the maximum clock rate
of a system, but a positive hold time can cause malfunction
at any clock rate. Thus, chip designers and system designers strive to eliminate hold-time requirements.
The IC design usually guarantees that any individual flipflop does not require a positive hold time with respect to the
clock signal at this flip-flop.
Hold-time requirements between flip-flops or registers on
the same chip can be avoided by careful design of the onchip clock distribution network. If the worst-case clock-skew
value is shorter than the sum of minimum clock-to-Q plus
minimum interconnect delays, there is never anyon-chip
hold-time problem.
Xilinx has addressed this problem by adding a deliberate
delay to every FPGA data input. In XC3000, and XC3100
FPGAs, this delay is fixed and always present; in XC4000
and XC5200 FPGAs, this delay is optional, and its value is
tailored to the clock distribution delay (i.e. it is larger for bigger devices). As a result we can claim that no Xilinx FPGA
Data input has a hold-time problem (i.e., none has a positive hold time with respect to the externally applied clock),
when the design uses the internal global clock distribution
network (and, in XC4000 and XC5200, uses the delayed
input option). Most competitive devices do not offer this feature.
External Clock
Internal Clock
II~ternal Clock D~ay
!
r-
ConventionallnputPin _ _ _ SET-wr- ~
Set-up and Hold Time _ _ ~
H!J!!!!!!!!!!!
~;;~ ~
Time
Delay _
_ _ _ _ _ _..11_ _ _ _ _ _ _ _ _
_
Input With
Pin Set·up
X5971
It is, however, far more difficult to avoid a hold time problem
in the device input flip-flops, with respect to the device clock
input pin. When specifying the data pin-to-clock pin set-up
and hold times, the chip-internal clock distribution delay
must be taken into consideration. It effectively moves the
timing window to the right (see figure), thus subtracting
from the specified internal set-up time (which is good), but
adding to the hold time (which is very bad). If the clock distribution delay is any longer than the data input delay - and
it easily might be - the device data input has a hold-time
requirement with respect to the clock input.
This means that the data source, usually another IC driven
by the same clock, must guarantee to maintain data beyond
the clock edge. In other words, the data source is not
allowed to be very fast. If it is, the receiver might erroneously input the new data instead of the data created by the
previous clock, as it should. This is called a race condition,
and can be a fatal system failure.
13-50
XAPP 095 November 24, 1997 (Version 1.0)
APPLICATION NOTE
I
~XllINX®
Overshoot and Undershoot
XAPP 096 September 9, 1997 (Version 1.0)
Application Note By Peter AlIke
Introduction
The "Absolute Maximum Ratings" table in the Xilinx Data
Book restricts the signal-pin voltage to a maximum 500 mV
excursion above Vee and below ground. The reason for
this tight specification is to prevent uncontrolled current in
the input-clamping ESD-protection diodes. Such tight specifications are common in the industry; some manufacturers
limit the excursion to 300 mV.
This specification seems to be clean and simple, but it is
violated in almost every practical design. When users put
modern CMOS devices on PC boards, and interconnect
them with unterminated traces, there are reflections, commonly called "ringing", that cause overshoots and undershoots of substantial amplitude (2 V and more). The recent
migration to smaller device geometries has made the IC
outputs even faster and increased the slew-rate, caUSing
more reflections even on short PC-board traces.
Fortunately, this problem has an easy solution:
The concern is not the input voltage, but rather the current
through the input protection diode and other input· structures. Excessive current can cause latch-Up if it exceeds
hundreds of milliamps AND if it lasts. for microseconds
(shorter duration current spikes do not activate the SCRlike latch-Up mechanism).
PC-board reflections, on the other hand, usually have a
short duration of just a few nanoseconds, and have an
impedance of 40 to 100 0, which makes them incapable of
causing latch-Up. They don't drive enough current and they
don't last long enough to cause any harm.
Here is the new Xilinx specification:
"Maximum DC overshoot or undershoot above Vee or
below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins
may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this over- or undershoot lasts less than 20 ns".
XAPP 096 September 9, 1997 (Version 1.0)
II
13-51
APPLICATION NOTE
Boundary Scan in XC4000 and
XC5200 Series Devices
XAPP017 December 10, 1997 (Version 2.1)
Application Note
Summary
X~4000
and ~C5200 Series FPGA devices contain boundary-scan facilities that are compatible with IEEE Standard 1149.1.
Application Note describes those facilities in detail, and explains how boundary scan is incorporated into an FPGA
design.
Thl~
Xilinx Family
XC4000 Series, XC5200
Introd uction
In production, boards must be tested to assure the integrity
of the components and the interconnections. However, as
integrated circuits have become more complex and multilayer PC-boards have become more dense, it has become
increasingly difficult to test assembled boards.
Originally, manufacturers used functional tests, applying
input stimuli to the input connectors of the board, and
observing the results at the output. Later, "bed-of-nails"
testing became popular, where a customized fixture
presses sharp, nail-like stimulus- and test-probes into the
exposed traces on the board. These probes were used to
force signals onto the traces and observe the response.
However, increasingly dense multi-layer PC boards with
ICs surface-mounted on both sides have stretched the
capability of bed-of-nail testing to its limit, and the industry
is forced to look for a better solution. Boundary-scan techniques provide that solution.
The inclusion of boundary-scan registers in ICs greatly
improves the testability of boards. Boundary scan provides
a mechanism for testing component I/Os and inter-connections, while requiring as few as four additional pins and a
minimum of additional logic in each IC. Component testing
may also be supported in ICs with self-test capability.
Devices containing boundary scan have the capability of
driving or observing the logic levels on I/O pins. To test the
external interconnect, devices drive values onto their outputs and observe input values received from other devices.
A central test controller compares the received data with
expected results. Data to be driven onto outputs is distributed through a chain of shift registers, and observed input
data is returned through the same shift-register path.
Data is passed serially from one device to the next, thus
forming a boundary-scan path or loop that originates at the
test controller and returns there. Any device can be temporarily removed from the boundary-scan path by bypassing
13-52
its internal shift registers, and passing the serial data
directly to the next device.
XC4000IXC5200 FPGA devices contain boundary-scan
registers that are compatible with the IEEE Standard
1149.1, that was derived from a proposal by the Joint Test
Action Group (JTAG). External (I/O and interconnect) testing is supported; there is also limited support for internal
self-test.
Overview of XC4000IXC5200
Boundary-Scan Features
XC4000/XC5200 devices support all the mandatory boundary-scan instructions specified in the IEEE Standard
1149.1. A Test Access Port (TAP) and registers are provided that implement the EXTEST, SAMPLE/PRELOAD
and BYPASS instructions. The TAP can also support two
USERCODE instructions.
Note: If boundary scan is not used after the device is configured, the user can use the special boundary scan pads
as input or output pins. During configuration, be sure not to
toggle the TAP pins, since inadvertent toggling of the TAP
pins can turn the boundary scan circuitry 'on.' The TDI,
TMS, and TCK pads can be used as unrestricted I/O. The
TOO pad can be used as an output pad. In the XC5200
family, all four pins have full I/O capability. And like the regular lOBs, these input and output pins have pullups and
pulldowns available.
Boundary-scan operation is independent of individual lOB
configuration and package type. All lOBs are treated as
independently controlled bidirectional pins, including any
unbonded lOBs. Retaining the bidirectional test capability
even after configuration affords tremendous flexibility for
interconnect testing.
Additionally, internal Signals can be captured during
EXTEST by connecting them to unbonded lOBs, or to the
unused outputs in lOBs used as unidirectional input pins.
This partially compensates for the lack of INTEST support.
XAPP017 December 10, 1997 (Version 2.1)
~XILINX
!
The public boundary-scan instructions are always available
prior to configuration. After configuration, the public instructions and any USER1/USER2 instructions are only available if boundary scan specified in the schematic/HDL code.
While SAMPLE and BYPASS are available during configuration, it is recommended that boundary-scan operations
not be performed during this transitory period.
It should also be noted that the Test Data Register contains
three Xilinx test bits (BSCANT.UPD, TDO.O and TDO.T)
and that bits of the register may correspond to unbonded or
unused pins.
Additionally, the EXTEST instruction incorporates INTESTlike functionality that is not specified in the standard, and
system clock inputs are not disabled during EXTEST, as
recommended in the standard.
In addition to the test instructions outlined above, the
boundary-scan circuitry can also be used to configure the
FPGA device, and read back the configuration data.
The TAP pins (TMS, TCK, TDI and TOO) are scanned, but
connections to the TAP controller are made before the
boundary-scan logic. Consequently, the operation of the
TAP controller cannot be affected by boundary-scan test
data.
The following description assumes that the reader is familiar with boundary-scan testing and the IEEE Standard.
Only issues specific to the XC4000/xC5200 implementation are discussed in detail. For general information on
boundary scan, please refer to the bibliography.
When the TAP is in the shift-DR state the contents of all
data registers are shifted; if you are in the middle of shifting
out data from the data register, complete shifting out of all
data first, before switching to the instruction or bypass register.
Deviations from the IEEE Standard
The XC4000/XC5200 boundary scan implementation deviates from the IEEE standard in that three dedicated pins
(CCLK, PROGRAM and DONE) are not scanned.
1
C]
TEST·LOGIC-RESET
~
o
0
R_U_N_.T_E.S_TI_ID_L_E_;--~--~(
,---,_ _
SELECT-DR·SCAN
o
JI-l-----~I'-
D
(...._ _P_A_U..,SE_-_D_R_____
11
0
NOTE: The value shown adjacent to each state transition in this figure
represents the signal present at TMS at the time of a rising edge at TCK.
_ _ __ , _ - - - /
-'D
( ...._ _P_A_U,S_E._IR_ _
0
II
X2680
Figure 1: State Diagram for the TAP Controller
XAPP017 December 10, 1997 (Version 2.1)
13-53
Boundary Scan in XC4000 and XC5200 Series Devices
Boundary-Scan Hardware
Test Access Port
The boundary-scan logic is accessed through the Test
Access Port (TAP), which comprises four semi-dedicated
pins: Test Mode Select (TMS), Test Clock (TCK), Test Data
Input (TDI) and Test Data Output (TOO), as defined in the
IEEE specification.
The TAP pins are permanently connected to the boundaryscan circuitry. However, once the device is configured, the
connections may be ignored unless the use of boundary
scan is specified in the design. See "Using Boundary Scan"
on page 13-57.
If the use of boundary scan is specified, the TAP input pins
(TMS, TCK and TDI) may still be shared with other logic,
subject to limitations imposed by external connections and
the operation of the TAP Controller. In designs that do not
use boundary scan after configuration, the TAP pins can be
used as inputs or outputs from the user logic in the FPGA
device. TMS, TCK and TDI are available as unrestricted
I/Os, while TOO only provides a 3-state output. In the
XC5200 family, all four pins are available as I/O.
Before the FPGA is configured, it is important not to toggle
the TAP pins (TDI, TMS, TCK), since these pins 'turn-on'
boundary scan. Before an FPGA is configured, at a minimum, do not toggle TCK. Similarly, if boundary scan is
enabled in a design after the FPGA is configured, care
must be taken not to toggle the TAP pins (TDI, TMS, TCK)
to prevent turning 'on' boundary scan by accident.
TAP Controller
The TAP Controller is a 16-state machine that controls the
operation of the boundary-scan circuitry in response to
TMS. This state machine implements the state diagram
1) and is clocked by
specified by the I EEE standard
TCK.
Upon power-on, or if the boundary scan logic is not used in
the application, the TAP controller is forced into the TestLogic-Reset state. After configuration, the controller
remains disabled, unless its use is explicitly specified in the
user design. PROGRAM resets the latched decodes for
EXTEST, CONFIGURE, and READBACK instructions.
Loading a 3-bit instruction into the Instruction Register (IR)
determines the subsequent operation of the boundaryscan logic, Table 1. The instruction selects the source of the
TOO pin, and selects the source of device input and output
data (boundary-scan register or input pin/user logic).
13-54
Table 1: Boundary Scan Instructions
Instruction
12 11
0
0
0
0
0
1
1
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
1
1
10
Test
Selected
EXT EST
SAMPLE/
PRELOAD
USER 1
USER2
READBACK
CONFIGURE
RESERVED
BYPASS
TOO
Source
DR
DR
1/0 Data
Source
DR
Pin/Logic
BSCAN.TD01
BSCAN.TD02
Readback Data
DOUT
User Logic
User Logic
Pin/Logic
Disabled
-
-
--
Bypass Register
10 IS closest to TDO
Note: Whenever the TAP Controller is in the Shift-DR state,
all data registers are shifted, regardless of the instruction.
DR data is modified even if a BYPASS instruction is executed.
The instruction register is used not only to hold the current
instruction. If the TAP is in the capture-IR state and TCK
goes high, the instruction register captures the current
boundary-scan state of the device. 10 is 1 by default. 11 is 0
by default. 12 is 0 if the device is in configure by boundary
scan mode. Before and after configure by boundary scan
mode, 12 will capture 1. Note that 10 is shifted out of TOO
first, then 11 , and then 12 .
The Boundary-Scan Data Register
The Data Register (DR) is a serial shift register implemented in the lOBs of the FPGA device, (Figure 2). Potentially, each lOB can be configured as an independently
controlled bidirectional pin. Therefore, three data register
bits are provided per lOB: for input data, output data and 3state control. In practice, many of these bits are redundant,
but they are not removed from the scan chain.
An update latch accompanies each bit of the DR, and is
used to hold injected test data stable during shifting. The
update latch is opened during the Update-DR state of the
TAP Controller when TCK is Low.
In a typical DR instruction, the DR captures data during the
Capture-DR state (on the rising edge of TCK). This data is
then shifted out and replaced with new test data. Subsequently, the update latch opens, and the new test data
becomes available for injection into the logic or the interconnect. The injection of data occurs only if an EXTEST
instruction is in progress.
Note: The update latch is opened whenever the TAP Controller is in the Update-DR state, regardless of the instruction. Care must be exercised to ensure that appropriate
data is contained in the update latch prior to initiating an
EXT EST. Any DR instruction, including BYPASS, that is
executed after the test data is loaded, but before the
EXTEST commences, changes the test data.
XAPP017 December 10, 1997 (Version 2.1)
~XILINX
sd
Q f-ff----H 0
Q
To Global
Clock Buffer
+----HlE
(ClK Pad Only)
10B.1
(To FPGA Interconnect)
Qf-ff----H
Qf-ff----H
+----HlE
DRCK
Update
Test logic
Reset
EXTEST
X5998
Figure 2: Boundary Scan logic in a Typical lOB
The IEEE Standard does not require the ability to inject
data into the on-chip system logic and observe the results
during EXTEST. However, this capability helps compensate
for the lack of INTEST. Logic inputs may be set to specific
levels by a SAMPLE/PRELOAD or EXTEST instruction and
the resulting logic outputs captured during a subsequent
EXTEST. It must be recognized, however, that all DR bits
are captured during an EXTEST and, therefore, may
change.
Pull-up and pull-down resistors remain active during
boundary scan. Before and during configuration, all pins
are pulled up. After configuration, the lOB can be configured with a pull-up resistor, a pull-down resistor or neither.
Note: Internal pull-up/pull-down resistors must be taken
into account when designing test vectors to detect open circuit PC traces.
The primary and secondary global clock inputs (PGCK1-4
and SGCK1 -4 in XC4000, GCK1 -4 in XC5200) are taken
directly from the pins, and cannot be overwritten with
XAPP017 December 10, 1997 (Version 2.1)
boundary-scan data. However, if necessary, it is possible to
drive the clock input from boundary scan. The external
clock source is 3-stated, and the clock net is driven with
boundary scan data through the output driver in the clockpad lOB. If the clock-pad lOBs are used for non-clock signals, the data may be overwritten normally.
Figure 3 shows the data-register cell for a TAP pin. An ORgate permanently disables the output buffer if boundaryscan operation is selected. Consequently, it is impossible
for the outputs in lOBs used by TAP inputs to conflict with
TAP operation. TAP data is taken directly from the pin, and
cannot be overwritten by injected boundary-scan data.
Bit Sequence
Table 2 lists, in data-stream order, the boundary-scan cells
that make up the DR for the XC4000 Series. The cell closest to TOO corresponds to the first bit of the data-stream,
and is at the top of the table. This order is consistent with
the BSDL description.
13-55
I
Boundary Scan in XC4000 and XC5200 Series Devices
From TDI
sd
Q i-tl----j'--f D
Q
t-----HLE
To Tap
Controller
108.1 --+-+-+----+------+---+------1
(To FPGA Interconnect)
ShiIVCapture
D
Qi-tl---H
D
Q
DRCK
Update
Device Not
Configured
Test Logic
Reset
EXTEST
X5999
Figure 3: Boundary Scan Logic in a TAP Input (TMS, TCK, and TOI Only)
Each lOB corresponds to three bits in the DR. The 3-state
control is first (closest to TOO), the output is next, and the
input is last. Other signals correspond to individual register
bits. lOB locations assume that the die is viewed from the
top, as in the device-level editors XOE or EPIC. In the
XC4000, the input-only MO and M2 mode pins contribute
only the In bit to the boundary scan I/O register.
Table 2: XC4000 Boundary Scan Order
Bit 0 ( TOO end)
Bit 1
Bit 2
TOO.T
TDO.O
{ Left-edge lOBs (Top to Bottom)
This is a 1-bit shift register that passes the serial data
directly to TOO when a BYPASS instruction is executed.
User Registers
MD1.T
MD1.0
MD1.1
MDO.I
MD2.1
{ Bottom-edge lOBs (Left to Right)
{ Right-edge lOBs (Bottom to Top)
BSCANT.UPD
X2674
13-56
Tables in the data sheets show the DR order for all XC4000/
XC5200 family devices. The DR also includes the following
non-pin bits: TOO.T and TOO.I, which are always bits 0 and
1 of the DR, respectively, and BSCANT.UPO which is
always the last bit of the DR.
The Bypass Register
{ Top·edge lOBs (Right to Left)
(TDI end)
Note: All lOBs remain in the DR, independent of whether
they are actually used, or even bonded. Three bits,
BSCANT.UPO, TOO.O and TOO.T, are included for Xilinx
test purposes, and may be ignored by other users. CCLK,
PROGRAM and DONE are not included in the boundary
scan.
The XC4000 and XC5200 boundary-scan instruction set
includes two USERCOOE instructions, USER1 and
USER2. Connections are provided to the TAP and TAP controller that, together with direct connections to the TAP pins,
permit the user to include boundary-scan self-test features
in the design.
The XC4000 boundary scan symbol has six connections
for user registers: SEL 1, SEL2, T001, T002, ORCK and
IDLE. TOI is available directly from the lOB that provides
the TOI pin. The XC5200 boundary scan symbol has three
XAPP017 December 10, 1997 (Version 2.1)
~XILINX
additional pins which make the creation of a user register
easier: RESET, UPDATE, and SHIFT.
Note: The TDI signal supplied to user test logic is overwritten by boundary-scan test data during EXTEST. During
user tests, it is not altered.
Figure 4 is a flow chart of the XC4000 FPGA start-up
sequence that shows when the boundary-scan instructions
are available. Since PROGRAM resets the TAP controller,
boundary-scan operations cannot commence until PROGRAM has been taken High.
SEL 1, SEL2 - SEL 1 and SEL2 enable user logic. They are
asserted (High) when the instruction register contains
instructions USER1 and USER2, respectively.
TD01, TD02 - TD01 and TD02 are inputs to the TOO output multiplexer, permitting user access to the serial boundary-scan output. They are selected when executing the
instructions USER1 and USER2, respectively. Input to user
data registers can be derived directly from the TDI pin, thus
completing the boundary-scan chain.
There is a one flip-flop delay between TD01ITD02 and the
TOO output. This flip-flop is clocked on the falling edge of
TCK.
DRCK - Data register clock (DRCK) is a gated and uninverted version of TCK. It is provided to clock user test-data
registers. TDI data should be sampled with the falling edge
of DRCK (rising edge of TCK). The TOO output flip-flop
accepts data on the rising edge of DRCK (falling edge of
TCK). DRCK is active only during the Capture-DR and
Shift-DR states of the TAP controller. When not active in the
XC4000, DRCK is Low. In the XC5200, when DRCK is not
active, it is High.
Boundary Scan
Instructions
Available:
Yes
EXTEST*
SAMPLE/PRELOAD
BYPASS
CONFIGURE*
(* jf PROGRAM", High)
Master Waits 50 to 250 f,.lS
Beiore Sampling Mode Lines
Master CCLK - - - - Goes Active
1----------.
IDLE - IDLE is a second gated and inverted version of
TCK. It is active during the RUN-TEST/IDLE state of the
TAP controller, and may be used to clock user test logic a
set number of times, determined through TMS by the central test controller.
RESET - This pin is only available on the XC5200 boundary
scan symbol. Whenever the TAP is in the TEST-LOGICRESET state, the RESET pin is High, in all other cases the
RESET pin is Low.
SAMPLE/PRELOAD
BYPASS
Configuration
memory
Full
No
Yesj-----,
UPDATE - This pin is only available in the XC5200 boundary scan symbol. Whenever the USER1 or USER2 instructions are used, UPDATE is an inverted version of TCK. In all
other cases, UPDATE is Low.
CCLK
Count Equals
Length
Count
SHIFT - This pin is only available in the XC5200 boundary
scan symbol. When the USER1 or USER2 instructions are
used, SHIFT is High, in all other cases SHIFT is Low.
II
"N:::.o_---'
Using Boundary Scan
Full access to the built-in boundary-scan logic is always
available between power-up and the start of configuration.
Optionally, the built-in logic is fully available after configuration if boundary scan is specified in the design. At this time,
user test logic is also available, and may be accessed
through the boundary-scan port. During configuration, a
reduced boundary-scan capability remains available: the
SAMPLE/PRELOAD and BYPASS instructions only.
XAPP017 December 10, 1997 (Version 2.1)
EXTEST}
SAMPLE PRELOAD
BYPASS
USER 1
USER 2
CONFIGURE
READBACK
Operational
If Boundary Scan
is Selected
Figure 4: XC4000 Start-up Sequence
13-57
Boundary Scan in XC4000 and XC5200 Series Devices
Full boundary-scan capabilities are available until INIT is
High. Without external intervention, INIT automatically
goes High after -1 ms. If more time is required for boundary-scan testing, INIT may be held Low beyond this period
by applying an external Low signal to the INIT pin until testing is complete. Once INIT has gone High, all clocks on the
TCK pin are counted as configuration clocks for data and
length count. See "CONFIGURE" on page 13-59. for more
details.
Boundary scan can be accessed before the FPGA is configured and after the FPGA is configured. If you want to
access boundary scan before the device is configured, then
when you power-up the device, hold the INIT pin Low until
Vee has risen to Vec(min).
If you have already started configuring the device, and data
frames are already being sent to the FPGA, then you have
two choices. You can either access full-boundary scan
mode, or limited boundary scan mode. If you want to
access full-boundary scan mode, then both INIT and PROGRAM must be brought Low (Hold fNTf and PROG Low for
over 300 ns and then release PROGRAM.) After releasing
PROGRAM, continue to hold INIT Low while sending signals to the TAP. If you can use the limited boundary scan
mode (which means you only can use the SAMPLE/PRELOAD and BYPASS instructions), then just bring INIT Low.
Accessing boundary scan after the device is configured
has one requirement. The BSCAN symbol must be instantiated/inserted into your design with the correct syntax (see
Figure 5). In this case, activating boundary scan after configuration amounts to toggling the TAP pins.
BSCAN
>-~~---, TOI
TOO
;>-~~-----' TMS
~--~
ORCK
(>-~~---1 TCK
IOLE
TD01
SEL1
T002
SEL2
BSCAN
T001
SEL1
T002
SEL2
5k BSCAN Syntax for BSCAN after configure symbol
OBUF ~
X5966
Figure 5: Boundary-Scan Schematic Symbols
If the BSCAN symbol is not included, boundary scan is not
selected, and the lOBs used by the TAP input pins are
freely available as general purpose lOBs. The TOO output
pin may be used as a logic output by explicitly connecting
13-58
From~
User
Logic
~
OBUFT
X2676
Figure 6: Typical Non-Boundary-Scan TOO
Connection
Boundary Scan Instructions
The XC4000/XC5200 boundary scan supports three IEEEdefined instructions (EXTEST, SAMPLE/PRELOAD and
BYPASS), two user-definable instructions (USER1 and
USER2), and two FPGA-specific instructions (CONFIGURE and READ BACK). The instruction codes are shown in
See Table 1 on page 13-54.
EXTEST
While the EXTEST instruction is present in the IR, the data
presented to the device output buffers is replaced by data
previously loaded through the boundary-scan DR and
stored in the update latch (Figure 7). Similarly, the output 3state controls are replaced, and the data passed to internal
system logic from input pins is replaced.
When a DR instruction cycle is executed, data arriving at
the device input pins is loaded into the DR. The data from
the system logic that drives output buffers and their 3-state
controls is also loaded. This action occurs during the CAPTURE-DR state of the TAP controller (Figure 1 on page 1353). Data is serially shifted out of the DR during the SHIFTDR state; simultaneously, new data is shifted in. In the
UPDATE-DR state, the new data is transferred into the
update latch for use as replacement data, as described
above.
The replacement of system data with update latch data
starts a$ soon as the EXTEST instruction is loaded into the
IR. For this data to be valid, it must have been loaded by a
previous EXTEST or SAMPLE/PRELOAD operation.
4k BSCAN Syntax for BSCAN after configure symbol
TOO
the TOO pad primitive to an OBUF or OBUFT as required
(see Figure 6.)
Since the DR and update latch are modified during any DR
instruction cycle, including BYPASS, the data in the update
latch is only valid if it was loaded in the last DR instruction
cycle executed before EXTEST is asserted.
The IEEE definition of EXTEST only requires that test data
be driven onto outputs, that 3-state output controls be overridden, and that input data be captured. The capture of output data and 3-state controls and the forcing of test data
into the system logic is normally performed during INTEST.
The XC4000/XC5200 effectively performs EXTEST and
INTEST simultaneously. This added functionality permits
the testing of internal logic, and compensates for the
absence of a separate INTEST instruction. However, when
performing an EXTEST, care must be taken as to what sig-
XAPP017 December 10, 1997 (Version 2.1)
~:XILINX
To
Next
From
Previous --+-r--+---~
Cell
Cell
DRCK
T ------+--+--+----------+--~------~
System
Logic
o
--------~--~--------+---------~
Pad
X2677
Figure 7: EXTEST Data Flow
nals are driven into the system logic. Data captured from
internal system logic must be masked out of the test-data
stream before performing check-sum analysis.
Test clocks and paths to TOO are provided, together with
two signals that indicate that user instructions have been
loaded. See "User Registers" on page 13-56.
SAMPLE/PRELOAD
User tests depend upon CLBs and interconnect that must
be configured to operate. Consequently, they may only be
performed after configuration.
The SAMPLE/PRELOAD instruction permits visibility into
system operation by capturing the state of the I/O. It also
permits valid data to be loaded into the update register
before commencing an EXTEST.
The DR and update latch operate exactly as in EXTEST
(see above). However, data flows through the 1/0 unmodified.
BYPASS
The BYPASS instruction permits data to be passed synchronously to the next device in the boundary-scan path.
There is a 1-bit shift register between the TDI and TOO flipflop.
CONFIGURE
Steps to follow to configure a Xilinx XC4000 or XC5200
device via JTAG:
The bitstream format is identical for all configuration
modes. A user can use a design.BIT file or a design.RBT
file, depending on whether the user wants to read a binary
file (.BIT) or an ASCII file (.RBT).
1. Enable the boundary scan circuitry.
This can be done one of three ways, either during
power-up, or by configuring the device with boundary
scan enabled, or by pulling the PROGRAM pin low.
USER1, USER2
These instructions permit test logic, designed by the user
and implemented in CLBs, to be accessed through the TAP.
XAPP017 December 10, 1997 (Version 2.1)
To enable boundary scan during power-up, hold the
INIT pin Low when power is turned on. When Vee has
13-59
I
Boundary Scan in XC4000 and XC5200 Series Devices
reached Vcc(min), the TAP inputs can be toggled to
enter JTAG instructions. The INIT pin can be held Low
one of two ways, either manually or with a pulldown. If
you choose to manually hold the INIT low, then the INIT
pin must be held low until the CONFIGURE instruction
is the current instruction. If you choose a pulldown, use
a pulldown which pulls the INIT pin down to approximately 0.5V. The pulldown has the merit of holding INIT
low whenever the FPGA is powered-up, and letting the
user observe the INIT pin during configuration.
After the FPGA has been configured, if you want to
reconfigure a configured device that has boundary scan
enabled after configuration, then just start toggling the
boundary scan TAP pins.
2. Load the Xilinx CONFIGURE instruction into the Instruction Register (IR).
The Xilinx CONFIGURE instruction is 101 (12 11 10)· 10 is
the bit shifted first into the IR.
3. After shifting in the Xilinx CONFIGURE instruction,
make the CONFIGURE instruction the current JTAG
instruction by going to the UPDATE-IR state. When TCK
goes low in the UPDATE-IR state, the FPGA is now in
the JTAG configuration mode and will start clearing the
configuration memory. The CONFIGURE instruction is
now the current instruction, which must be followed by a
rising edge on TCK. If you chose to manually hold the
INIT pin Low, then the INIT pin must be held Low until
the CONFIGURE instruction is the current instruction.
4. Once the Xilinx CONFIGURE instruction has been
made the current instruction, the user must go to the
RUN-TEST/IDLE state, and remain in the RUN-TEST/
IDLE state until the FPGA has finished clearing its configuration memory.
The approximate time it takes to clear the FPGA configuration memory is: 2 * 1 us * (number of frames per
device bitstream).
When the FPGA has finished clearing its configuration
memory, the open-collector INIT has gone high impedance. At this point, the user should advance to the
SHIFT-DR state. Once the TAP is in the SHIFT-DR state
and the INIT pin has been released, clocks on the TCK
pin will be .considered configuration clocks for data and
length count.
5. In the SHIFT-DR state, start shifting in the bitstream.
Continue shifting in the bitstream until DONE has gone
High and the startup sequence has finished.
During the time you are shifting in the bitstream via the
TAP, the configuration pins LDC, HOC, INIT, PROGRAM, DOUT, and DONE all function as they normally
do during non-JTAG configuration. These pins can be
probed by the user. After completion of configuration, or
13-60
if configuration failed, the SAMPLE/PRELOAD instruction can be used to view these lOBs (except PROGRAM and DONE.)
LDC is Low during configuration. HOC is High during
configuration. INIT will be high impedance during configuration, but if a CRC error or frame error is detected
INIT will go Low. If a pulldown is present on INIT the~
the user must probe INIT with a meter or scope. With a
pulldown (as in step 1) attached to the INIT pin, the user
will see a drop from approximately 0.5V to OV if INIT
drops Low to indicate a data error. PROGRAM can still
be used to abort the configuration process. DOUT and
TOO will echo TDI until the preamble and length count
are shifted into TDI. After the preamble and length
count have been shifted into the FPGA, DOUT will
remain High. DONE will go High when configuration is
finished. Until configuration is finished, DONE will
remain Low.
Additional Notes
(a) It is possible to configure several XC4000/XC5200
devices in a JTAG chain. But unlike non-JTAG daisy-chain
configuration, this does not necessarily mean merging all
the bitstreams into one bitstream. In the case of JTAG configuration of Xilinx devices in a JTAG chain, all devices,
except the one being configured, will be placed in BYPASS
mode. The one device in CONFIGURE mode will have its
bitstream downloaded to it. After configuring this device it
will be placed in BYPASS, and another device will be taken
out of BYPASS into CONFIGURE.
(b) If you are configuring a long daisy-chain of JTAG
devices (TDI connected to TOO of the previous device), the
bitstream for the device with the CONFIGURE instruction
may need to have its bitstream modified.
For example, assume that the a user has the following
daisy-chain of devices:
source
-----> device1 -----> device2 -----> device3
Device1's TOO pin is connected to device2's TDI pin, and
device2's TOO pin is connected to device3's TDI pin.
The way to configure this chain is to place one device in
CONFIGURE; and the other two in BYPASS. Further
assume that device1 and device2 configure in this way, but
device3 never configures. Specifically, device3's DONE pin
never goes High. The problem is the bitstream length count.
A possible cause, aside from bitstream corruption, is that
the final value of the length count computed by the user/
software was reached before the loading was complete.
There are two solutions. One solution involves just continually clocking TCK (for about 15 seconds) until DONE goes
High. The other solution is to modify the bitstream;
increase the length count by the number of devices ahead
of the device under configuration.
XAPP017 December 10, 1997 (Version 2.1)
~XILINX
In the preceding example, the user would increase the
length count value by 2. (In a daisy-chain of devices configuring via boundary scan, devices in BYPASS will supply
the extra 1s needed at the head of the bitstream.)
(c) In general for the XC4000 and XC5200, if you are configuring these devices via JTAG, finish configuring the
device first before executing any other JTAG instructions.
Once configuration through boundary scan is started, the
configuration operation must be finished.
(d) If boundary scan is not included in the design being configured, then make sure that the release of II0s is the last
event in the startup sequence.
If boundary scan is not available, the FPGA is configured,
and the II0s are released before the startup sequence is
finished, the FPGA will not respond to input signals and
outputs will not respond at all.
(e) Re-issuing a boundary scan CONFIGURE instruction
after the clearing of configuration memory will cancel the
CONFIGURE instruction.
The proper method of re-issuing a CONFIGURE instruction
after the configuration memory is cleared is to issue
another boundary scan instruction, and follow it by the
CONFIGURE instruction.
(f) If configuration through boundary scan fails, there are
only two boundary scan instructions available: SAMPlEI
PRELOAD and BYPASS. If another reconfiguration is to be
attempted, then the PROGRAM pin must be pulled low, or
the FPGA must be repowered.
(g) When the CONFIGURE instruction is the current
instruction, clocks on the TCK pin are not considered configuration clocks until the INIT pin has gone high impedance, and the TAP is in the SHIFT-DR state.
(h) If the user is attempting to configure a chain of devices,
it is recommended that the user only configure the chain in
all boundary scan mode, or use the non-boundary scan
configuration modes. It is possible to configure a daisychain of devices, some in boundary scan and some in nonboundary scan configuration. Configuring in a mixed mode
will not necessarily give the user a continuous boundary
scan chain, which mayor may not be a problem for a particular user's applications.
(j) Currently, there is no software to configure a Xilinx FPGA
via the boundary scan pins. The user must provide this.
(k) Configuring a chain of Xilinx FPGAs via boundary scan
does not require merging all the bitstreams into one bitstream, as in non-boundary scan configuration daisychains. When the FPGA is in boundary scan configuration,
the same configuration circuitry used for non-boundary
scan configuration is used. So, if a user would like, it is possible to merge all bitstreams into one bitstream, using the
PROM File Formatter or MakePROM/promgen. In a case
where the user wants to merge the bitstreams into one bit-
XAPP017 December 10, 1997 (Version 2.1)
stream, the user should configure as in note (a) above.
Additionally, the user will have to tie all INIT pins together.
All DONE pins will also have to be tied together.
NOTE: The intention of configuration for a daisy-chain was
to use either all the devices in boundary scan, or all the
devices in non-boundary scan configuration.
READ BACK
Readback through boundary scan allows the user to
access the readback features of the device, which would
normally need to be accessed through user-specified pins.
All limits of 'normal' readback are the same with readback
through the TAP. Like regular readback, readback through
the TAP is at a minimum of 100 KHz and at a maximum of
2 MHz. Like regular read back, the read back bitstream
through boundary scan has the same format.
Unlike regular read back, which can be done repeatedly,
readback through the TAP requires the following circuit:
1. In your schematic, or top-level synthesis design, instantiate the BSCAN and READBACK symbols.
2. Connect the BSCAN symbol pins TDI, TMS, TCK, and
TDO to the boundary scan pads TDI, TMS, TCK, and
TDO, respectively.
3. Next, connect the net between the TCK pad and TCK
pin on the BSCAN symbol to an IBUF. Take the output of
the IBUF and connect it to the ClK pin of the READBACK symbol. See Figure 8.
BSCAN
~------J;TD~I~~~T~DO~------~TDO
"'-----ITMS
DRCK
">--_---1 TCK
TO01
TD02
• 4k BSeAN Symbol setup for multiple REAOBACKS through TAP
• For the 5k, add IBUFs to TDI, TMS, and TCK. For TDO, add an OBUF.
(see figure 5)
X5968
Figure 8: Symbol Setup for Multiple Readbacks
For the XC5200, the equivalent circuit must be implemented using the XACT Design Editor (XDE) program
EditlCA, or EPIC in the M1-based tools. After placing
and routing your XC5200 design, load the design.lCA
file into EditlCA, and follow the procedures below:
«ENTER> means hit the enter key on your keyboard)
(a) Once EditlCA has displayed the design.lCA file,
type the following:
eb bscan
This will bring up the Editblock window for the XC5200
BSCAN symbol.
13-61
I
Boundary Scan in XC4000 and XC5200 Series Devices
(b) In the Editblock window, select the 'used' option,
which is in the upper left corner of the screen.
(c) Now type:
endb
This brings you back to the EditLCA screen.
(d) Next type the following:
add net username tckpin.i rdbk.ck
where tckpin is the pin number of the TCK pin of your
XC5200 device. 'username' is a net name of your choice.
For example, if your design used an XC5202PC84, then
the above command line would be:
add net mynet p16.i rdbk.ck
(e) At this point you should see a net go from the TCK pin
to the CK pin of the Readback symbol.
(f) Save your changes to the LCA file and exit XDE.
4. After entering the above circuit, compile the design to an
LCA file.
5. Make the bitstream file for the LCA file by using the following option with makebits, or use the M1 Bitstream
Generator:
-f readclk:rdbk
For example, at a unix prompt:
% makebits -f readclk:rdbk design
6. Now the FPGA is ready to perform consecutive readbacks.
Readback is performed by loading the IR with the
READBACK instruction and then shifting out the captured data from the SHIFT-DR state in the TAP. Readback data is captured when READBACK is made the
current instruction in the TAP.
Alternatively, if you do not want to go back to the TESTLOGIC-RESET state, realize that after shifting out the readback bitstream, a minimum of three additional clocks are
needed on the readback register. So, after doing a readback, instead of going back to TEST-LOGIC-RESET, a user
can opt to execute some other JTAG instruction, and then
perform another readback.
Also, this procedure is only needed if you intend to do more
than one readback. If you intend only do a read back once,
then the connection between the BSCAN symbol and the
READBACK symbol is not needed. In that case, all that is
needed is the BSCAN symbol instantiated with the boundary scan pads (TDI, TMS, TCK, & TOO) on the top level of
the design.
Boundary Scan Description
Language Files
Boundary Scan Description Language (BSDL) files
describe boundary-scan-capable parts in a standard format used by automated test-generation software. The order
and function of bits in the boundary-scan data register are
included in this description.
BSDL files are available in the Xilinx File Download area via
the Xilinx WebLiNX web site (www.xilinx.com).
Bibliography
The following publications contain information about the
IEEE Standard 1149.1, and should be consulted for general boundary-scan information beyond the scope of this
application note.
Colin M. Maunder & Rodham E. Tulloss. The Test Access
Port and Boundary Scan Architecture. IEEE Computer
Society Press, 10662 Los Vaqueros Circle, P.O. Box 3014,
Los Alamitos, CA 90720-1264. See www.computer.org/
cspress/catalog/st01096.htm
Perform the first readback by loading the IR with the
READ BACK instruction. This first read back must be finished, which means shifting out the *entire* readback
bitstream. To be safe, shift out the entire bitstream and
then send three additional TCKs.
John Fluke Mfg. Co. Inc. The ABC of Boundary Scan Test.
John Fluke Mfg. Co. Inc., P.O. Box 9090, Everett, WA
98206.
7. After performing the first readback, another readback
can be performed by going to the TEST-LOGIC-RESET
state, and re-Ioading the READ BACK instruction and
performing the Readback as described in the previous
paragraph.
Ken Parker. The Boundary Scan Handbook. Kluwer Academic Publications, (617) 871-6600.
In summary, consecutive readbacks are performed by
starting from TEST-LOGIC-RESET, loading the IR with
the READBACK instruction, shifting out the readback
bitstream plus three additional TCKs, and then going
back to the TEST-LOGIC-RESET state.
13-62
GenRad Inc. Meeting the Challenge of Boundary Scan.
GenRad Inc., 300 Baker Ave., Concord, MA 01742-2174.
IEEE Standards, standards.ieee.org
Texas Instruments, www.tLcom/sc/docs/jtag/jtaghome.htm
XAPP017 December 10, 1997 (Version 2.1)
!
~XllINX®
Index
1
Introduction
2
Development System Products and CORE Solutions Products
3
CPLD Products
4
FPGA Products
5
SPROM Products
6
3V Products
7
HardWire FpgASIC Products
8
High-Reliability and QML Military Products
9
Programming Support
10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support and Services
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors
Book Index
1 13-13
3-state buffer
Spartan Series 4-188
XC3000 Series 4-304,4-313,13-23
XC4000 Series 4-27
XC5200 4-232
3-state net, global. See Global 3-State
5-input function
XC3000 Series 13-19
XC5200 4-229
70% rule 13-22
asynchronous RAM 4-15
attribute
DECODE 4-28
INIT 4-16,4-186
laC 4-36, 4-38, 4-40
MEDDElAY 4-23,4-24
NODElAY 4-23,4-178,4-233
available products
high-reliability 8-1
XC1700D 5-21
XC3000 Series 4-373
XC4000 Series 4-147
XC9500 3-6
A
B
A Simple Method of Estimating Power in XC4000XUEXlE
FPGAs 13-13
absolute maximum ratings
overshoot and undershoot 13-51
specifications
Spartan 4-200
XC1700D 5-6,5-17
XC3000A 4-338
XC3000l 4-344
XC3100A 4-350
XC3100l 4-356
XC4000E 4-95, 8-12
XC5200 4-269
AClK symbol 13-24
adaptor selector for programmer 9-2
address pins
pin descriptions
XC3000 Series 4-335
XC4000 Series 4-42, 4-245
advance specifications, definition of 1-1, 4-95, 4-200,
4-269
algorithms, programmer 9-1
Answers database 12-2
applications Information 12-2
AppLiNX CD 12-3
asynchronous peripheral configuration mode
debugging hints 13-37
specifications
XC3000 Series 4-326
XC4000 Series 4-68
XC3000 Series 4-325
XC4000 Series 4-42,4-67,4-245,4-262
bar code 10-17
Base System
Foundation Series (PC) 2-4,2-5,2-6,2-7
basic moisture life test 11-2
battery backup in XC3000 Series 13-27, 13-43
BClKIN 13-24
pin description
XC3000 Series 4-335
BGA packages
BG225 package drawings 10-32
BG256 package drawings 10-33
BG352, BG432 package drawings 10-34
BG560 package drawings 10-35
bidirectional (bidi) buffer
XC3000 Series 4-307
bitstream
combining for daisy chain 4-48,4-193,4-247
combining with MakePROM 4-316
copyrighting 13-43
format for conffguration
Spartan Series 4-194
XC4000 Series 4-49, 4-249
boundary scan
access to 13-57
avoiding inadvertent activation 4-46, 4-191, 4-243
bypass register 13-56
configuration with 4-55,4-197,4-254
daisy chain configuration 13-60
data register 13-54
effect on GTS 4-25, 4-189, 4-234
implementing in schematic 4-45, 4-191, 4-242
Spartan Series 4-191
Numerics
14-1
I
Book Index
XC4000 Series 4-45, 4-242
library symbol 4-42, 4-45, 4-191, 4-207, 4-242, 4-245
pin descriptions
Spartan Series 4-206
XC4000 Series 4-41, 4-244
Spartan Series 4-189
specifications
XC4000E 4-109,4-274
TAP controller 13-54
test access port (TAP) 13-54
user registers 13-56
XC4000 Series 4-27, 4-43, 4-235, 13-52
XC5200 4-240,13-52
XC9500 3-16
Boundary Scan Description Language. See BSDL
BSCAN symbol 4-42,4-45,4-191,4-207,4-242,4-245
BSDL files
Spartan Series 4-191
XC4000 Series 4-45, 4-242, 13-62
XC5200 13-62
XC9500 Series 3-16
buffer, 3-state
Spartan Series 4-188
XC3000 Series 4-304, 4-313, 13-23
XC4000 Series 4-27
XC5200 4-232
buffer, bidirectional
XC3000 Series 4-307
buffered switch matrix 4-32
BUFG symbol 4-238
BUFGE symbol 4-40, 4-42
BUFGLS symbol 4-38, 4-42
BUFGP symbol 4-36,4-183
BUFGS symbol 4-36,4-183
BUFT symbol 4-27
bus contention, internal 13-23
bypass register 13-56
c
carry logic
Spartan Series 4-186
XC4000 Series 4-18
XC5200 4-230
cascade logic
XC5200 4-231
CBQFP packages
CB100 package drawings 10-44
CB100, CB164, CB196 package drawings 10-46
CB164 package drawings 10-45
CB228 package drawings 10-47
CCLK
frequency variation
XC3000 Series 13-27
in configuration debug 13-38
low-time restriction in XC3000 Series 13-27
14-2
pin description
Spartan Series 4-206
XC3000 Series 4-334
XC4000 Series 4-41, 4-244
setting frequency
Spartan Series 4-194
XC4000 Series 4-49, 4-248
use as configuration clock
Spartan Series 4-192
XC3000 Series 4-318
XC4000 Series 4-47,4-246
ceramic packages
DIP
008 package drawings 10-22
class, customer training 12-3
CLB. See configurable logic block
clock diagram
Spartan 4-182
XC4000E 4-37
XC4000EX 4-37
CMOS input
Spartan Series 4-178
XC3000 Series 4-304
XC4000 Series 4-21, 4-233
XC5200 4-233
CMOS output
Spartan Series 4-179
XC3000 Series 4-304, 13-22
XC4000 Series 4-24, 13-18
XC5200 4-233
configurable logic block (CLB)
block diagram
XC3000 Series 4-305
XC4000 Series 4-10
XC5200 4-229
carry logic
Spartan Series 4-186
XC4000 Series 4-18
XC5200 4-230
cascade logic
XC5200 4-231
flip-flop
XC3000 Series 4-305, 13-21
XC4000 Series 4-10, 4-231
XC5200 4-229
function generator
XC3000 Series 4-306, 13-19
XC4000 Series 4-9
XC5200 4-229
latch
XC4000EX 4-10,4-231
XC5200 4-229
RAM 4-12
routing associated with
XC3000 Series 13-21
XC4000 Series 4-29
~XILINX
Spartan Series 4-175
specifications
XC3000A 4-339
XC3000L 4-345
XC3100A 4-351
XC3100L 4-357
XC5200 4-271
XC3000 Series 4-305, 13-19
XC4000 Series 4-9
XC5200 4-228, 4-229
differences from XC4000 and XC3000 4-226
configuration 13-45
asynchronous peripheral mode
debugging hints 13-37
XC3000 Series 4-325
XC3000 Series specifications 4-326
XC4000 Series 4-42, 4-67, 4-245, 4-262
XC4000 Series specifications 4-68
bitstream copyrighting 13-43
bitstream format
Spartan Series 4-194
XC4000 Series 4-49, 4-249
boundary scan pins, using 4-55, 4-197, 4-254, 13-60
clock. See CCLK
configuration sequence
Spartan Series 4-196
XC4000 Series 4-51, 4-250
control pins 13-40
daisy chain
debugging hints 13-37
mixed family 4-48,4-247,13-39
Spartan Series 4-193
XC3000 Series 4-318
XC4000 Series 4-47,4-247
debugging 13-35
express mode
daisy chain 4-248
XC4000EX 4-244, 4-248, 4-249, 4-253, 4-264
initiating reconfiguration 13-46
length count 4-49,4-55,4-194,4-249,4-253,4-316
master modes, general
Spartan Series 4-192
XC3000 Series 4-315,4-318
XC4000 Series 4-47, 4-55, 4-246, 4-253
XC4000 Series specifications 4-69
XC5200 specifications 4-267
master parallel mode
debugging hints 13-36
XC3000 Series 4-323
XC3000 Series specifications 4-324
XC4000 Series 4-41, 4-63, 4-244, 4-258
XC4000 Series specifications 4-64, 4-259
master serial mode
debugging hints 13-36
Spartan Series 4-192
Spartan Series specifications 4-193
XC3000 Series 4-321
XC3000 Series speCifications 4-322
XC4000 Series 4-62, 4-257
XC4000 Series specifications 4-62, 4-257
memory cell 4-302, 13-41
mode
selection of 13-35
modes, table of
XC3000 Series 4-315
XC4000 Series 4-47, 4-246
peripheral mode
XC3000 Series 4-325
XC3000 Series specifications 4-326
peripheral modes, general
debugging hints 13-38
XC3000 Series 4-318
XC4000 Series 4-41,4-47,4-244,4-247
pin descriptions
Spartan Series 4-206
XC3000 4-334
XC4000 Series 4-41, 4-244
pin functions during
Spartan Series 4-192
XC3000 Series 4-336
XC4000 Series 4-59, 4-60
XC5200 4-266
power-on reset
XC3000 Series 4-315
reducing time 13-46
slave serial mode
debugging hints 13-37
Spartan Series 4-193, 4-206
Spartan Series specifications 4-194
XC3000 Series 4-318,4-327
XC3000 Series specifications 4-328
XC4000 Series 4-41,4-47,4-61,4-244,4-247,
4-256
XC4000 Series specifications 4-61
Spartan Series 4-192
speCifications
XC3000 Series 4-321
XC4000 Series 4-61, 4-256
start-up sequence
XC3000 Series 13-28
XC4000 Series 4-52, 4-252
switching characteristics
XC5200 4-267
synchronous peripheral mode
XC4000 Series 4-41, 4-65, 4-244, 4-260
XC4000 Series specifications 4-66
XC3000 Series 4-315, 13-28
XC4000 Series 4-46, 4-246
XC5200
differences from XC4000 and XC3000 4-226
copyrighting bitstream 13-43
CPLD
14-3
I
Book Index
overview 1-2, 1-4, 13-9
product selection guide 13-7,13-10
CQ100 package
pinout table
XC3000 Series 4-365
CRC error checking
Spartan Series 4-195
XC4000 Series 4-50, 4-249
crystal oscillator
XC3000 Series 4-314, 4-320, 13-25
CS
in configuration debug 13-36
CSO, CS1
pin descriptions
XC4000 Series 4-42, 4-245
CSO, CS1, CS2
pin descriptions
XC3000 Series 4-335
customer training 12-3
cyclic redundancy check (CRC)
Spartan Series 4-195
XC4000 Series 4-50, 4-249
o
daisy chain
creating bitstream 4-316
debugging hints 13-37
express mode
XC4000EX 4-248
mixed family 4-48,4-247, 13-39
Spartan Series 4-193
XC3000 Series 4-318
XC4000 Series 4-47,4-247
data integrity 11-7
data pins
pin descriptions
XC3000 Series 4-335
XC4000 Series 4-43, 4-245
data register 13-54
data retention, XC9500 3-23,3-31,3-39,3-47,3-57,3-67
data stream. See bitstream
DC characteristics
specifications
Spartan 4-201
XC3000A 4-337
XC3000L 4-343
XC31 OOA 4-349
XC3100L 4-355
XC4000E 4-96, 8-13
XC5200 4-269
DD8 package
package drawing 10-22
debugging
configuration 13-35
DECODE attribute 4-28
14-4
decode logic. See cascade logic, edge decoder
delay
input delay 13-50
XC3000 Series 13-21
of configuration after power-up
Spartan Series 4-197
XC4000 Series 4-52, 4-252
optional input delay
XC4000 Series 4-23, 4-233
output
XC4000 Series 13-16
with fast capture latch 4-24
design security
XC9500 3-16
device literature 12-3
DIN
in daisy chain
Spartan Series 4-193
XC3000 Series 4-318
XC4000 Series 4-47,4-247
pin description
Spartan Series 4-207
XC3000 Series 4-335
XC4000 Series 4-43, 4-245
DIP package
ceramic 10-22
plastic 10-23
direct interconnect
XC3000 Series 4-307
XC4000EX 4-33
XC5200 4-228, 4-236
disk space requirements
programmer 9-1
DONE
during power-up 13-41
express mode configuration 4-248
going High after configuration
XC3000 Series 4-319
XC4000 Series 4-55, 4-253
in configuration debug 13-36
not going High after configuration 13-35
pin description
Spartan Series 4-206
XC4000 Series 4-41, 4-244
DONE/PROG
during power-up 13-41
pin description
XC3000 Series 4-334
double-length routing
Spartan Series 4-182
XC4000 Series 4-32
XC5200 4-238
DOUT
in daisy chain
express mode 4-248
Spartan Series 4-193
~XILINX
XC3000 Series 4-318
XC4000 Series 4-47,4-247
pin description
Spartan Series 4-207
XC3000 Series 4-335
XC4000 Series 4-43, 4-245
dry bag 10-15
dry bake 10-15
dual-port RAM 4-15,4-184
E
edge decoder 4-28
edge-triggered RAM 4-13
advantages of 4-12, 4-186
EIAJ standards 10-1
electrical parameters
programmer 9-1
electrostatic discharge (ESD) 11-8
endurance, XC9500 3-16
error checking, bitstream 4-50,4-195,4-249,4-320
Spartan Series 4-195
XC3000 Series 4-320
XC4000 Series 4-50, 4-249
express configuration mode
CRC not supported 4-249
synchronized to DONE
XC4000EX 4-253
XC4000EX 4-244, 4-248, 4-249, 4-253, 4-264
F
factory floor life 10-15
failure analysis 11-3, 11-6
failures in time 11-2
fast capture latch 4-24
fast carry logic. See carry logic
FastCONNECT switch matrix 3-13
FastFlash technology
XC9500 3-19
FeLK1 - FCLK4
clock diagram 4-37
FDCE symbol 4-11, 4-232
FIFO
implementing in XC4000 Series RAM 4-12
FITs 11-2
flip-flop
in CLB
XC3000 Series 4-305, 13-21
XC4000 Series 4-10,4-11,4-231, 4-232
XC5200 4-229
in lOB
metastability 13-47
none in XC5200 4-233
Spartan Series 4-179, 4-180
XC3000 Series 4-304,13-21
XC4000 Series 4-23, 4-24
in macrocell 3-8
forced air cooling vendors 10-10
Foundation Series 2-3
Base System (PC) 2-4,2-5,2-6, 2-7
FPGA
advantages of 13-7
data integrity 11-7
overview 1-2, 1-4
product selection guide 1-6,1-7,1-8,13-7,13-10
security 13-42
function block
XC9500 3-7
function generator
in CLB
XC3000 Series 4-306, 13-19
XC4000 Series 4-9
XC5200 4-229
in lOB
XC4000EX 4-26
using as RAM 4-12
G
gate array
advantages of FPGAs 1-3
GCK1 - GCK8
clock diagram 4-37
pin descriptions
XC4000EX 4-42
GCLK symbol 13-24
general routing matrix (GRM)
XC5200 4-227, 4-228, 4-235, 4-236
glitch
avoidance in XC3000 Series 13-20
power supply 13-41
Global 3-State (GTS)
Spartan Series 4-189,4-206
XC4000 Series 4-25, 4-40, 4-234
global buffer
Spartan 4-182
specifications
XC3000A 4-338
XC3000L 4-344
XC3100A 4-350
XC3100L 4-356
XC5200 4-270
XC3000 Series 4-313,13-24
XC4000 Series 4-36
XC4000E 4-36
XC4000EX 4-38
XC5200 4-238
Global Early buffer (BUFGE) 4-26, 4-39, 4-42
fast pin-to-pin path 4-26
with fast capture latch 4-24
I
14-5
Book Index
Global Low-Skew buffer (BUFGLS) 4-38, 4-42
Global Set/Reset (GSR)
in CLB
Spartan Series 4-189
XC4000 Series 4-11,4-232
in lOB
Spartan Series 4-179
XC4000 Series 4-26
GRM. See general routing matrix
ground bounce
XC4000 Series 13-16
GSR. See Global Set/Reset
GTS. See Global 3-state
H
HardWire
overview 1-4
HOC
during power-up 13-41
pin description
Spartan Series 4-207
XC3000 Series 4-318, 4-334
XC4000 Series 4-42, 4-245
heatsink vendors 10-10
hermeticity test 11-3
high temperature life test 11-2, 11-8
high-reliability (Hi-Rei) 8-1
overview 1-5
product availability 8-1
hold time on data input 13-50
XC4000 Series 4-23, 4-233
hotline support 12-2
HQ packages 10-13
thermal data 10-7
HQFP packages
HQ100 package drawings 10-29
HQ160, HQ208, HQ240 package drawings 10-30
HQ304 package drawings 10-31
HTQFP packages
HT100, HT144, HT176 package drawings 10-28
HW-130 programmer 9-1
hysteresis
XC3000 Series 13-21
I/O block
see also input/output block
see also input/output cell
XC9500 3-14
I/O count
XC3000 Series 4-361
XC5200 4-296
IN characteristics. See V/I characteristics
14-6
IEEE Standard 1149.1 13-62
IFO symbol 4-21, 4-178
ILO symbol 4-21, 4-178
ILFFX symbol 4-24
ILFLX symbol 4-24
INIT
during power-up 13-41
in configuration debug 13-38
in daisy chain 13-39
pin description
Spartan Series 4-207
XC3000 Series 4-334
XC4000 Series 4-42, 4-245
INIT attribute 4-16, 4-186
initializing RAM 4-16,4-186
input/output block (lOB)
clock
XC3000 Series 13-23
CMOS input
Spartan Series 4-178
XC3000 Series 4-304
XC4000 Series 4-21, 4-233
XC5200 4-233
CMOS output
Spartan Series 4-179
XC3000 Series 4-304, 13-22
XC4000 Series 4-24, 13-18
XC5200 4-233
delay on input 13-50
XC3000 Series 13-21
XC4000 Series 4-23, 4-233
during configuration
Spartan Series 4-206
XC3000 Series 4-319
XC4000 Series 4-40, 4-243
fast capture latch 4-24
flip-flop
metastability 13-47
function generator on output 4-26
maximum available I/O
XC3000 Series 4-361
XC5200 4-296
multiplexer on output 4-26
optional delay with fast capture latch 4-24
pull-down resistor
Spartan Series 4-179
XC4000 Series 4-26, 4-234
pull-up resistor
Spartan Series 4-179
XC3000 Series 4-304, 4-335
XC4000 Series 4-26, 4-234
rise/fall time
XC3000 Series 13-21
routing associated with
Spartan Series 4-182
XC4000 Series 4-33
~XILINX
XC5200 4-228, 4-240
slew rate control
Spartan Series 4-179
XC3000 Series 4-304
XC4000 Series 4-25, 4-234
XC5200 4-233
Spartan Series 4-177
specifications
XC3000A 4-341
XC3000L 4-347
XC3100A 4-353
XC3100L 4-359
XC5200 4-273
TTL input
Spartan Series 4-178
XC3000 Series 4-304
XC4000 Series 4-21, 4-233
XC5200 4-233
TTL output
none in XC5200 4-233
Spartan Series 4-179
XC3000 Series 4-304
XC4000 Series 4-24
unused 110
Spartan Series 4-206
XC4000 Series 4-40, 4-243
VersaRing
Spartan Series 4-182
XC4000 Series 4-33
XC5200 4-228, 4-240
XC3000 Series 4-303, 13-21
clock 13-23
XC4000 Series 4-21, 4-233
XC5200 4-233
XC9500 3-14
in-system programming
XC9500 3-16
interconnect. See routing
IS09002 1-5,11-1
J
JEDEC standards 10-1
JTAG. See boundary scan
junction temperature
junction-to-ambient 10-4
junction-to-case 10-4
L
latch
fast capture latch 4-24
in CLB
XC4000EX 4-10,4-11,4-231,4-232
XC5200 4-229
in lOB
none in XC5200 4-233
Spartan Series 4-178
XC3000 Series 4-304
XC4000 Series 4-21
latch up 11-8
LC. See logic cell
LDC
during power-up 13-41
in configuration debug 13-36
pin description
Spartan Series 4-207
XC3000 Series 4-318, 4-334
XC4000 Series 4-42, 4-245
LDCE symbol 4-11, 4-232
lead fatigue test 11-3
length count
configuration debugging hints 13-38
Spartan Series 4-194
XC3000 Series 4-316
XC4000 Series 4-49, 4-55, 4-67, 4-249, 4-253, 4-262
level-sensitive RAM 4-15
library symbol
3-state buffer
BUFT, XC4000 Series 4-27
WAND1 4-27
WOR2AND 4-27
AND-gate in lOB
OAND2 4-26
boundary scan
BSCAN 4-42, 4-45, 4-191, 4-207, 4-242, 4-245
TCK, TDI, TDO, TMS 4-42,4-45,4-191,4-207,
4-242, 4-245
fast capture latch
ILFFX 4-24
ILFLX 4-24
flip-flop
FDCE, XC4000 Series CLB 4-11,4-232
IFD, Spartan Series lOB 4-178
IFD, XC4000 Series lOB 4-21
Global 3-State
STARTUP 4-25,4-189,4-234
global buffer
ACLK, XC3000 Series 13-24
BUFG, XC5200 4-238
BUFGE, XC4000EX 4-40, 4-42
BUFGLS, XC4000EX 4-38, 4-42
BUFGP, Spartan 4-183
BUFGP, XC4000E 4-36
BUFGS, Spartan 4-183
BUFGS, XC4000E 4-36
GCLK, XC3000 Series 13-24
Global Set/Reset
STARTUP 4-11,4-189,4-232
latch
ILD, Spartan Series lOB 4-178
14-7
I
Book Index
ILD, XC4000 Series lOB 4-21
LDCE, XC4000EX CLB 4-11,4-232
mode pins
MDO, MD1, MD2 4-46, 4-246
oscillator
OSC, Spartan Series 4-189
OSC4, XC4000 Series 4-28
OSC52, XC5200 4-235
output multiplexer
OMUX24-26
readback
READBACK 4-56, 4-198, 4-255
resistor
PULLDOWN 4-26,4-179,4-235
PULLUP 4-26,4-179,4-235
wide decoder
WAND1 4-28
LIM. See local interconnect matrix
literature, technical 12-3
LOC attribute 4-36, 4-38, 4-40
local interconnect matrix (LIM)
XC5200 4-228, 4-235
local phone support 12-2
logic cell (LC)
XC5200 4-226, 4-227
longline
Spartan Series 4-182
specifications
XC5200 4-270
XC3000Series 4-311,13-21,13-23
XC4000 Series 4-32
XC5200 4-238
lookup table (LUT). See function generator
low voltage device
XC4000 Series 4-5, 8-7
XC4000XLT Family 4-159
XC4000XV Family 4-151
M
MO, M1, M2. See mode pins
MO/RTRIG
pin description
XC3000 Series 4-334
M1/RDATA
pin description
XC3000 Series 4-334
M2
pin description
XC3000 Series 4-334
macrocell
XC9500 3-8
MakeBits program
bitstream generation
XC3000 Series 4-317
14-8
crystal oscillator selection 4-320
start-up timing
XC3000 Series 4-317
tie option 4-317
MakePROM program
combining bitstreams 4-316, 4-317
manufacturers. See vendors
mass, package 10-12
master configuration modes, general
Spartan Series 4-192
XC3000 Series 4-315,4-318
XC4000 Series 4-47,4-55,4-246,4-253
XC4000 Series specifications 4-69
XC5200 specifications 4-267
master parallel configuration mode
debugging hints 13-36
specifications
XC3000 Series 4-324
XC4000 Series 4-64, 4-259
XC3000 Series 4-323
XC4000 Series 4-41, 4-63, 4-244, 4-258
master serial configuration mode
debugging hints 13-36
Spartan Series 4-192
specifications
Spartan Series 4-193
XC3000 Series 4-322
XC4000 Series 4-62, 4-257
XC3000 Series 4-321
XC4000 Series 4-62, 4-257
maximum I/O
XC3000 Series 4-361
XC5200 4-296
MDO, MD1, MD2 symbols 4-46, 4-246
Mean Time Between Failures (MTBF)
metastability 13-48
MEDDELAYattribute 4-23,4-24
memory cell, configuration 4-302, 11-7, 13-41
memory requirements
programmer 9-1
metastability 13-47
MIL-STD-883B 1-5
mode pins
pin descriptions
XC4000 Series 4-41, 4-244
XC3000 Series 4-315
XC4000 Series 4-46,4-246
moisture sensitivity in surface mount packages 10-14
multiplexer
XC4000EX lOB 4-26
N
newsletter, XCell 12-3
NODELAY attribute 4-23, 4-178, 4-233
~XILINX
o
OAND2 symbol 4-26
octal routing 4-33
OE
in configuration debug 13-36
OMUX2 symbol 4-26
on-chip oscillator. See oscillator, on-chip
open-drain output 4-25, 4-234
operating conditions
specifications
Spartan 4-200
XC1700D 5-6,5-17
XC3000A 4-337
XC3000L 4-343
XC3100A 4-349
XC3100L 4-355
XC4000E 4-95, 8-12
XC5200 4-269
ordering information
Spartan Series 4-219
XC1700D 5-10,5-21
XC4000 Series 4-111,4-147
XC5200 4-296
OSC symbol 4-189
OSC4 symbol 4-28
OSC52 symbol 4-235
oscillator
crystal
XC3000 Series 4-314,4-320,13-25
on-chip 13-41
Spartan Series 4-189
XC3000 Series 13-27
XC4000 Series 4-28
XC5200 4-227,4-235
output current
XC3000 Series 13-23
XC4000 Series 4-24, 4-40, 4-234, 4-243, 13-15
XC5200 4-233
output multiplexer in XC4000EX lOB 4-26
output slew rate
Spartan Series 4-179
XC3000 Series 4-304
XC4000 Series 4-25, 4-234
XC5200 4-233
overshoot 13-51
p
package availability
high-reliability 8-1
XC3000 Series 4-373
XC4000 Series 4-147
XC9500 3-7
package drawing
BG225 package 10-32
BG256 package 10-33
BG352, BG432 package 10-34
BG560 package 10-35
CB100 package 10-44
CB100, CB164, CB196 package 10-46
CB164 package 10-45
CB228 package 10-47
DD8 package 10-22
HQ100 package 10-29
HQ160, HQ208, HQ240 package 10-30
HQ304 package 10-31
HT100, HT144, HT176 package 10-28
PC20, PC28, PC44, PC68, PC84 package 10-26
PD8 package 10-23
PG120, PG132, PG156 package 10-37
PG175 package 10-38
PG191 package 10-39
PG223, PG299 package 10-40
PG411 package 10-41
PG475 package 10-42
PG559 package 10-43
PG68, PG84 package 10-36
PQ100 package 10-29
PQ304 package 10-31
PQ44, PQ160, PQ208, PQ240 package 10-30
S020 package 10-25
S08 package 10-24
TQ100, TQ144, TQ176 package 10-28
V08 package 10-24
VQ44, VQ64, VQ1 00 package 10-27
packaging
bar code 10-17
data acquisition 10-4
dimensions 10-1
dry bag 10-15
dry bake 10-15
EIAJ standards 10-1
EIJ standard board layout 10-3
factory floor life 10-15
handling and storage 10-15
JEDEC standards 10-1
mass 10-12
moisture sensitivity 10-14
orientation 10-3
reflow soldering 10-18
tape & reel packing 10-16
thermal characteristics 10-3
thermal database 10-4
thermal management 10-3
thermal resistance
applying data 10-6
table of 10-5
thermally enhanced 10-13
vendors 10-10, 10-20
weight 10-12
PC44 package
14-9
II
Book Index
pinout table
XC3000 Series 4-361
PC68 package
pinout table
XC3000 Series 4-363
PC84 package
pinout table
XC3000 Series 4-364
PCI compatibility
XC4000 Series 4-7
P08 package
package drawing 10-23
performance
XC3000 Series 4-331
XC5200 4-229
peripheral configuration mode
specifications
XC3000 Series 4-326
XC3000 Series 4-325
peripheral configuration modes, general
debugging hints 13-38
specifications
XC4000 Series 4-69
XC5200 4-267
XC3000 Series 4-318
XC4000 Series 4-41, 4-47, 4-244, 4-247
peripheral configuration modes. See also asynchronous
peripheral, synchronous peripheral
PG 132 package
pinout table
XC3000 Series 4-366
PG175 package
pinout table
XC3000 Series 4-369
PG84 package
pinout table
XC3000 Series 4-363
PGA packages
PG120, PG132, PG156 package drawings 10-37
PG 175 package drawings 10-38
PG191 package drawings 10-39
PG223, PG299 package drawings 10-40
PG411 package drawings 10-41
PG475 package drawings 10-42
PG559 package drawings 10-43
PG68, PG84 package drawings 10-36
PGCK1 - PGCK4
clock diagram 4-37,4-182
pin descriptions 4-42, 4-207
phone support 12-2
pin description
Spartan Series 4-206
pin descriptions
functions during configuration
Spartan Series 4-192
XC3000 Series 4-336
14-10
XC4000 Series 4-59, 4-60
XC5200 4-266
XC3000 Series 4-334
XC4000 Series 4-40, 4-243
pin locking
XC9500 3-15
pinout table
CQ100 package
XC3000 Series 4-365
device-specific
Spartan Series 4-208
XC3000 Series 4-372
XC4000 Series 4-111
package-specific
XC3000 Series 4-361
PC44 package
XC3000 Series 4-361
PC68 package
XC3000 Series 4-363
PC84 package
XC3000 Series 4-364
PG132 package
XC3000 Series 4-366
PG175 package
XC3000 Series 4-369
PG84 package
XC3000 Series 4-363
PQ100 package
XC3000 Series 4-365
PQ160 package
XC3000 Series 4-368
PQ208 package
XC3000 Series 4-371
Spartan Series 4-208
TQ100 package
XC3000 Series 4-365
TQ144 package
XC3000 Series 4-367
TQ176 package
XC3000 Series 4-370
VQ100 package
XC3000 Series 4-365
VQ64 package
XC3000 Series 4-362
XC3000 Series 4-361
XC3195 4-372
XC4000 Series 4-111
XC4003E 4-111
XC4005E/L 4-112
XC4006E 4-113
XC4008E 4-115
XC4010E/L 4-116
XC4013E/L 4-118
XC4013XLT 4-162
XC4020E 4-121
XC4025E 4-123,4-126
----
-
~-----
~XILINX
XC4028EXlXL 4-123, 4-126
XC4028XLT 4-164
XC4044EXlXL 4-129
XC4052XL 4-133
XC5202 4-275
XC5204 4-277
XC5206 4-281
XC5210 4-284
XC5215 4-289
XC95108 3-42
XC95144 3-50
XC95216 3-60
XC95288 3-70
XC9536 3-26
XC9572 3-34
XCS05 4-208
XCS10 4-209
XCS20 4-210
XCS30 4-212
XCS40 4-215
pin-to-pin specifications
XC5200 4-272
plastic packages
DIP
PD8 package drawings 10-23
PLCC packages
PC20, PC28, PC44, PC68, PC84 package
drawings 10-26
power consumption
reduction of 10-9
XC3000 Series 4-333, 13-24
XC4000 Series 13-18
power distribution
XC3000 Series 4-332
XC4000 Series 4-40, 4-243
power-down mode
none in XC4000 Series 4-40
none in XC5200 4-227
XC3000 Series 4-315, 4-333, 13-27, 13-43
power-on reset
XC3000 Series 4-315
power-up 13-41
power-up. See also start-up after configuration
PQ packages
thermal data 10-7
PQ100 package
pinout table
XC3000 Series 4-365
PQ160 package
pinout table
XC3000 Series 4-368
PQ208 package
pinout table
XC3000 Series 4-371
PQFP packages
PQ100 package drawings 10-29
PQ304 package drawings 10-31
PQ44, PQ160, PQ208, PQ240 package
drawings 10-30
preliminary specifications, definition of 1-1,4-95,4-200,
4-269
Primary Global Buffer (BUFGP) 4-36,4-42,4-182,4-207
product availability
high-reliability 8-1
Spartan Series 4-218
XC3000 Series 4-373
XC4000 Series 4-147
XC9500 3-6
product qualification requirements 11-4
product selection guide
CPLD 13-7,13-10
FPGA 1-6,1-7,1-8,13-7,13-10
product term allocator
XC9500 3-10
PROGRAM
during power-up 13-41
inititating reconfiguration 13-46
pin description
Spartan Series 4-206
XC4000 Series 4-41, 4-244
program cycles, XC9500 3-23,3-31,3-39,3-47,3-57,3-67
programmable switch matrix (PSM)
Spartan Series 4-181
XC3000 Series 4-307
XC4000 Series 4-30
programmer 9-1
algorithms 9-1
software 9-1
specifications 9-1
programming, in-system
XC9500 3-16
programming. See configuration
PROM
bitstream generation
Spartan Series 4-193
XC4000 Series 4-48, 4-247
configuration
Spartan Series
4-174
XC3000 Series 4-321, 4-323
XC4000 Series 4-6, 4-62, 4-63, 4-257, 4-258
in configuration debug 13-36
overview 1-4
programmer 9-1
size
Spartan 4-195
XC4000E 4-50
pseudo daisy chain for express mode
XC4000EX 4-248
pull-down resistor
lOB
Spartan Series 4-179
14-11
I
Book Index
XC4000 Series 4-26, 4-234
PULLOOWN symbol 4-26, 4-179, 4-235
pull-up resistor
lOB
Spartan Series 4-179, 4-206
XC3000 Series 4-304, 4-335
XC4000 Series 4-26, 4-41, 4-234, 4-244
long line
none in XC5200 4-238
XC3000 Series 4-313
XC4000 Series 4-32
PULLUP symbol 4-26, 4-179, 4-235
PWROWN 13-27
battery backup mode 13-43
in configuration debug 13-38
pin description
XC3000 Series 4-334
Q
quad routing 4-32
qualification requirements 11-4
quality assurance 11-1
R
RAM
asynchronous 4-15
configuration options
XC4000 Series 4-12
dual-port 4-15, 4-184
edge-triggered 4-13
in CLB 4-12
initialization of 4-16, 4-186
level-sensitive 4-15
read back of contents 4-57, 4-198
setting mode 4-12
synchronous 4-13
RCLK
pin description
XC3000 Series 4-335
XC4000 Series 4-41, 4-244
ROY/BUSY
pin description
XC3000 Series 4-335
XC4000 Series 4-41, 4-244
readback
CRC error checking
Spartan Series 4-195
XC4000 Series 4-50, 4-249
Spartan Series 4-197,4-206
specifications
Spartan 4-199
XC3000 Series 4-329
XC4000E 4-58, 4-268
14-12
XC3000 Series 4-319
XC4000 Series 4-41, 4-56, 4-244, 4-254
XChecker cable 4-57,4-199,4-255
REAOBACK symbol 4-56,4-198,4-255
reconfiguration
XC4000 Series 4-6
reconfiguration. See also configuration
reflow soldering 10-18
reliability 11-2
RESET
during power-up 13-41
in configuration debug 13-38
in daisy chain 13-39
inititating reconfiguration 13-46
pin description
XC3000 Series 4-334
rise time requirement in XC3000 Series 13-29
reset
Spartan Series 4-206
See also Global Set/Reset
XC3000 Series 4-320
XC4000 Series 4-40
See also Global Set/Reset
resistance to solvents test 11-3
resistor
lOB
Spartan Series 4-179
XC3000 Series 4-304, 4-335
XC4000 Series 4-26, 4-234
pull-up on longline
none in XC5200 4-238
XC3000 Series 4-313
XC4000 Series 4-32
with crystal oscillator 13-26
rise/fall time on input
XC3000 Series 13-21
routing
bidirectional (bidi) buffer 4-307
buffered switch matrix 4-32
direct interconnect
XC3000 Series 4-307
XC4000EX 4-33
XC5200 4-228, 4-236
double-length
Spartan Series 4-182
XC4000 Series 4-32
XC5200 4-238
global buffer
Spartan 4-182
XC4000E 4-36
XC4000EX 4-38
longline
Spartan Series 4-182
XC3000 Series 4-311, 13-21, 13-23
XC4000 Series 4-32
XC5200 4-238
~XILINX
octal 4-33
programmable switch matrix (PSM)
Spartan Series 4-181
XC3000 Series 4-307
XC4000 Series 4-30
quad 4-32
single-length
Spartan Series 4-181
XC4000 Series 4-30
XC5200 4-238
Spartan Series 4-180
VersaRing (lOB routing)
Spartan Series 4-182
XC4000 Series 4-33
XC5200 4-228, 4-240
XC3000 Series 4-306, 13-21
XC4000 Series 4-29
XC5200 4-228, 4-236
differences from XC4000 and XC3000 4-226
RS
pin description
XC4000 Series 4-42, 4-245
s
salt atmosphere test 11-3
Secondary Global Buffer (BUFGS) 4-36,4-42,4-182,4207,4-245
security 3-16, 13-42
selection guide
FPGA 1-6, 1-7, 1-8
service
overview 1-5
setup time on data input 13-48, 13-50
XC3000 Series 13-21
SGCK1 - SGCK4
clock diagram 4-37, 4-182
pin description 4-42, 4-207, 4-245
single-length routing
Spartan Series 4-181
XC4000 Series 4-30
XC5200 4-238
sink current. See output current
slave serial configuration mode
debugging hints 13-37
Spartan Series 4-193,4-206
specifications
Spartan Series 4-194
XC3000 Series 4-328
XC4000 Series 4-61, 4-69
XC5200 4-267
XC3000 Series 4-318, 4-327
XC4000 Series 4-41,4-47,4-61,4-244,4-247,4-256
slew rate
Spartan Series 4-179
XC3000 Series 4-304
XC4000 Series 4-25, 4-234
XC5200 4-233
SmartSearch 12-2
SMD. See Standard Microcircuit Drawing
S08 package
package drawing 10-24
socket vendors 10-20
soft startup
Spartan Series 4-179
XC3000 Series 4-320
XC4000 Series 4-25, 4-234
software
Foundation Series 2-3
Base System (PC) 2-4,2-5,2-6,2-7
programmer 9-1
SOIC packages
package drawings 10-24
S020 package drawings 10-25
solderability test 11-3
Spartan
clock diagram 4-182
global buffer 4-182
Primary Global Buffer (BUFGP) 4-182
Secondary Global Buffer (BUFGS) 4-182
specifications 4-200
Spartan Series 4-195
3-state buffer 4-188
bitstream format 4-194
boundary scan 4-189
BSDl files 4-191
carry logic 4-186
CMOS input 4-178
CMOS output 4-179
configurable logic block (ClB) 4-175
configuration 4-192
input/output block (lOB) 4-177
interconnect 4-180
on-chip oscillator 4-189
ordering information 4-219
pin description 4-206
pinout tables 4-208
product availability 4-218
read back 4-197
routing 4-180
soft startup 4-179
TTL input 4-178
TTL output 4-179
specifications
absolute maximum ratings
Spartan 4-200
XC1700D5-6,5-17
XC3000A 4-338
XC3000l 4-344
XC3100A 4-350
XC3100l 4-356
XC4000E 4-95, 8-12
I
14-13
Book Index
XC5200E 4-269
XC9500 3-23,3-31,3-39,3-47,3-57, 3-67
advance, definition of 1-1, 4-95, 4-200, 4-269
boundary scan
XC4000E 4-109,4-274
CLB
XC3000A 4-339
XC3000L 4-345
XC3100A 4-351
XC3100L 4-357
XC5200 4-271
configuration
XC3000 Series 4-321
XC4000 Series 4-61, 4-256
DC characteristics
Spartan 4-201
XC1700D 5-6,5-17
XC3000A 4-337
XC3000L 4-343
XC3100A 4-349
XC3100L 4-355
XC4000E 4-96, 8-13
XC5200 4-269
global buffer
XC3000A 4-338
XC3000L 4-344
XC3100A 4-350
XC3100L 4-356
XC5200 4-270
lOB
XC3000A 4-341
XC3000L 4-347
XC3100A 4-353
XC3100L 4-359
XC5200 4-273
longline
XC5200 4-270
operating conditions
Spartan 4-200
XC1700D 5-6,5-17
XC3000A 4-337
XC3000L 4-343
XC3100A 4-349
XC3100L 4-355
XC4000E 4-95, 8-12
XC5200 4-269
XC9500 3-23,3-31,3-39,3-47,3-57,3-67
pin-to-pin
XC5200 4-272
XC9500 3-24, 3-32, 3-40, 3-48, 3-58, 3-68
preliminary, definition of 1-1,4-95,4-200,4-269
programmer 9-1
readback
Spartan 4-199
XC3000 Series 4-329
XC4000E 4-58, 4-268
14-14
Spartan 4-200
wide edge decoder
XC4000E 4-98,4-99,8-15,8-16
XC3000A 4-337
XC3000L 4-343
XC31 OOA 4-349
XC3100L 4-355
XC4000E 4-95
XC5200 4-269
speed grades available
high-reliability 8-1
XC3000 Series 4-373
XC4000 Series 4-147
SRAM. See FPGA
Standard Microcircuit Drawing (SMD) 1-5,8-1
start-up after configuration
XC3000 Series 13-28
XC4000 Series 4-52, 4-252
STARTUP symbol
implementing Global 3-State 4-25, 4-189, 4-234
implementing Global Set/Reset 4-11,4-189,4-232
support 12-1
technical support hotline 12-2
surface mount packages
moisture sensitivity 10-14
switch matrix, programmable (PSM)
Spartan Series 4-181
XC3000 Series 4-307
XC4000 Series 4-30
synchronous peripheral configuration mode
specifications
XC4000 Series 4-66
XC4000 Series 4-41, 4-65, 4-244, 4-260
synchronous RAM 4-13
advantages of 4-12,4-186
T
TAP controller 13-54
tape & reel packing 10-16
TCK,TDI,TDO,TMS. See boundary scan
TCLKIN 13-24
pin description
XC3000 Series 4-335
technical Information 12-2
technical literature 12-3
technical support 12-1
hotline 12-2
overview 1-5
telephone support 12-2
temperature cycling test 11-3
test access port (TAP) 13-54
testing 11-2
thermal characteristics 10-3
thermal data
PQ/HQ packages 10-7
~XILINX
thermal management 10-3
thermal resistance
applying data 10-6
table of 10-5
thermal shock test 11-3
theta-JA 10-4
theta-JC 10-4
time-to-market 1-3
timing model
XC9500 3-17
T0100 package
pinout table
XC3000 Series 4-365
T0144 package
pinout table
XC3000 Series 4-367
T0176 package
pinout table
XC3000 Series 4-370
TOFP packages
T01 00, T0144, T0176 package drawings 10-28
training 1-5, 12-3
TSOP packages
package drawings 10-24
TTL input
Spartan Series 4-178
XC3000 Series 4-304, 4-319
XC4000 Series 4-21, 4-233
XC5200 4-233
TTL output
none in XC5200 4-233
Spartan Series 4c 179
XC3000 Series 4-304
XC4000 Series 4-24
u
unbiased pressure pot test 11-2
undershoot 13-51
unused 110
Spartan Series 4-206
XC4000 Series 4-40, 4-243
user registers in boundary scan 13-56
v
VII characteristics
XC3000 Series 13-22
XC4000 Series 13-15
vendors
forced air cooling 10-10
heatsink 10-10
socket 10-20
VersaBlock 4-227
VersaRing
Spartan Series 4-182
XC4000 Series 4-33
XC5200 4-228, 4-240
V08 package
package drawing 10-24
VPP
in configuration debug 13-36
V0100 package
pinout table
XC3000 Series 4-365
V064 package
pinout table
XC3000 Series 4-362
VOFP packages
V044, V064, V01 00 package drawings 10-27
w
WAND1 symbol 4-27, 4-28
Web site for Xilinx 1-1, 1-5, 12-2
WebLiNX 1-1, 1-5, 12-2
Answers database 12-2
SmartSearch 12-2
weight, package 10-12
wide edge decoder 4-28
specifications
XC4000E 4-98,4-99,8-15,8-16
WOR2AND symbol 4-27
World Wide Web site for Xilinx 1-1, 1-5, 12-2
WS
pin description
XC3000 Series 4-335
XC4000 Series 4-42, 4-245
x
XC1700
programmer 9-1
XC1700D data sheet 5-11
XC2000 13-7
overview 13-8
XC3000 13-7
overview 13-8
XC3000 Series 4-299,4-320,13-7,13-19
3-state buffer 4-304, 4-313, 13-23
5-input function 13-19
available 1/0 4-361
battery backup 13-27, 13-43
CCLK frequency variation 13-27
CMOS input 4-304
CMOS output 4-304, 13-22
configurable logic block (CLB) 4-305, 13-19
configuration 4-315, 13-28
specifications 4-321
crystal oscillator 4-314,4-320,13-25
I
14-15
Book Index
feature summary 4-299
glitch avoidance 13-20
global buffer 4-313, 13-24
hysteresis 13-21
input/output block (lOB) 4-303, 13-21
internal bus contention 13-23
on-chip oscillator 13-27
output current 13-23
overview 13-8
performance 4-331
pin descriptions 4-334
pinout tables 4-361
power consumption 4-333, 13-24
power distribution 4-332
power-down mode 4-315, 4-333
product availability 4-373
read back 4-319
rise/fall time 13-21
routing 4-306
soft startup 4-320
specifications
configuration 4-321
XC3000A 4-337
XC3000L 4-343
XC3100A 4-349
XC3100L 4-355
TTL input 4-304
TTL output 4-304
V/1 characteristics 13-22
XC3000A
overview 4-300
specifications 4-337
XC3000L
overview 4-300
specifications 4-343
XC3100 13-7
overview 13-8
XC3100A
overview 4-300, 13-8
specifications 4-349
XC3100L
overview 4-300,13-8
specifications 4-355
XC3195
pinout table 4-372
XC4000
overview 13-8
XC4000 Series 4-5, 4-50, 4-249, 13'7
3-state buffer 4-27
bitstream format 4-49, 4-249
boundary scan 4-43, 13-52
BSDL files 13-62
carry logic 4-18
CMOS input 4-21, 4-233
CMOS output 4-24,13-18
configurable logic block (CLB) 4-9
14-16
configuration 4-46, 4-246
speCifications 4-61, 4-256
CRC error checking 4-249
edge decoder 4-28
feature summary 4-5
global buffer 4-36
ground bounce 13-16
input/output block (lOB) 4-21, 4-233
interconnect 4-29
internal bus contention 13-23
low voltage device 4-5, 8-7
on-chip oscillator 4-28
ordering information 4-111,4-147
output current 4-24,4-234,13-15
output delay 13-16
pin descriptions 4-40, 4-243
pinout tables 4-111
power consumption 13-18
power distribution 4-40, 4-243
product availability 4-147
RAM 4-12
readback 4-56, 4-254
routing 4-29
soft startup 4-25, 4-234
speCifications
configuration 4-61, 4-256
XC4000E 4-95
TTL input 4-21, 4-233
TTL output 4-24
V/1 characteristics 13-15
wide edge decoder 4-28
XC4000A
overview 13-8
XC4000E
clock diagram 4-37
compared to XC4000 4-7
global buffer 4-36
overview 13-8
Primary Global Buffer (BUFGP) 4-36
Secondary Global Buffer (BUFGS) 4-36
specifications 4-95
XC4000EX
buffered switch matrix 4-32
clock diagram 4-37
compared to XC4000 4-7,4-8
fast capture latch on inputs 4-24
function generator in lOB 4-26
global buffer 4-38
Global Early buffer (BUFGE) 4-24, 4-39
Global Low-Skew buffer (BUFGLS) 4,38
interconnect 4-29
latch in CLB 4-10, 4-231
multiplexer in lOB 4-26
octal routing 4-33
overview 13-9
quad routing 4-32
---~---
--~--
~XILINX
I
routing 4-29
VersaRing (lOB routing) 4-33,4-182
XC4000H
overview 13-9
XC4000XL 4-5,8-7
XC4000XLT Family 4-159
feature summary 4-159
low voltage device 4-159
XC4000XV Family 4-151
feature summary 4-151
low voltage device 4-151
XC4003E
pinout table 4-111
XC4005E/L
pinout table 4-112
XC4006E
pinout table 4-113
XC4008E
pinout table 4-115
XC4010E/L
pinout table 4-116
XC4013E/L
pinout table 4-118
XC4013XLT
pinout table 4-162
XC4020E
pinout table 4-121
XC4025E
pinout table 4-123,4-126
XC4028EXIXL
pinout table 4-123, 4-126
XC4028XLT
pinout table 4-164
XC4044EX/XL
pinout table 4-129
XC4052XL
pinout table 4-133
XC5200 13-7
3-state buffer 4-232
5-input function 4-229
available 1/0 4-296
boundary scan 4-240, 13-52
BSDL files 13-62
carry logic 4-230
cascade logic 4-231
CMOS input 4-233
CMOS output 4-233
compared to XC4000 and XC3000 4-226
configurable logic block (CLB) 4-228, 4-229
differences from XC4000 and XC3000 4-226
configuration
differences from XC4000 and XC3000 4-226
general routing matrix (GRM) 4-227,4-228,4-235,
4-236
global buffer 4-238
input/output block (lOB) 4-233
interconnect 4-228, 4-236
latch in CLB 4-229
local interconnect matrix (LIM) 4-228, 4-235
logic cell (LC) 4-226, 4-227
on-chip oscillator 4-235
ordering information 4-296
output current 4-233
overview 13-9
performance 4-229
routing 4-228, 4-236
differences from XC4000 and XC3000 4-226
specifications 4-267,4-269
XC5200 4-269
TTL input 4-233
TTL output not supported 4-233
VersaBlock 4-227
VersaRing (lOB routing) 4-228, 4-240
XC5202
pinout table 4-275
XC5204
pinout table 4-277
XC5206
pinout table 4-281
XC521 0
pinout table 4-284
XC5215
pinout table 4-289
XC6200
overview 13-9
XC7200A
overview 13-9
XC7300
overview 13-9
XC9500
BSDL files 3-16
design security 3-16
endurance 3-16
FastCONNECT switch matrix 3-13
function block 3-7
I/O block 3-14
in-system programming 3-16
overview 3-5, 13-9
packag? availability and device 1/0 pins 3-7
pin locking capability 3-15
product availability 3-6
product term allocator 3-1 0
timing model 3-17
XC95108
pinout table 3-42
XC95144
pinout table 3-50
XC95216
pinout table 3-60
XC95288
pinout table 3-70
XC9536
14-17
I
Book Index
pinout table 3-26
XC9572
pinout table 3-34
XCELL newsletter 1-1
XCell newsletter 12-3
XC hecker cable
readback
Spartan Series 4-199
XC4000 Series 4-57, 4-255
XCS05
pinout table 4-208
XCS10
pinout table 4-209
XCS20
pinout table 4-210
XCS30
pinout table 4-212
14-18
XCS40
pinout table 4-215
Xilinx
about the company 1-2
quality assurance and reliability 11-1
technical support 1-5
Web site 1-1, 1-5, 12-2
XCELL newsletter 1-1
XCell newsletter 12-3
xtal oscillator. See crystal oscillator
XTL1
pin description
XC3000 Series 4-335
XTL2
pin description
XC3000 Series 4-335
Sales Offices, Sales
Representatives, and Distributors
1
Introduction
2
Development System Products and CORE Solutions Products
3
CPLD Products
4
FPGA Products
5
SPROM Products
6
3V Products
7
HardWire FpgASIC Products
8
High-Reliability and QML Military Products
9
Programming Support
10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support and·Services
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors
Sales Offices, Sales
Representatives, and Distributors
Table of Contents
Sales Offices, Sales Representatives, and Distributors
Headquarters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Xilinx Sales Offices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
North American Distributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
U.S. Sales Representatives ..........................................................
15-1
15-1
15-1
15-1
Sales Offices, Sales
Representatives, and Distributors
November 19, 1997 (Version 1.1)
Headquarters
XILlNX, Inc.
2100 Logic Drive
San Jose, CA 95124
Tel: (408) 559-7778
TWX: (510) 600-8750
FAX: (408) 559-7114
Xilinx Sales
Offices
NORTH AMERICA
XILlNX, Inc.
1281 Oakmead Pkwy.
Suite 202
Sunnyvale, CA 94086
Tel: (408) 245-9850
FAX: (408) 245-9865
XILlNX, Inc.
5690 DTC Blvd.
Suite 490W
Englewood, CO 80111
Tel: (303) 220-7541
FAX: (303) 220-8641
XILlNX, Inc.
15615 Alton Parkway
Suite 280
Irvine, CA 92618
Tel: (714) 727-0780
FAX: (714) 727-3128
XILlNX, Inc.
61 Spit Brook Rd.
Suite 403
Nashua, NH 03060
Tel: (603) 891-1098
FAX: (603) 891-0890
XILlNX, Inc.
905 Airport Rd.
Suite 200
West Chester, PA 19380
Tel: (610) 430-3300
FAX: (610) 430-0470
XILlNX, Inc.
939 North Plum Grove Road
Suite H
Schaumburg, IL 60173
Tel: (847) 605-1972
FAX: (847) 605-1976
XILlNX, Inc.
601 O-C Six Forks Road
Raleigh, NC 27609
Tel: (919) 846-3922
FAX: (919) 846-8316
XILlNX, Inc.
4100 McEwen, Suite 237
Dallas, TX 75244
Tel: (972) 960-1043
FAX: (972) 960-0927
XILlNX, Inc.
2910 South Sheridan Way,
Suite 203
Oakville, Ontario
Canada L6J7L9
Tel: (905) 829-9095
FAX: (905) 829-3045
EUROPE
XILlNX, Ltd.
Benchmark House
203 Brooklands Road
Weybridge, Surrey
KT130RH
United Kingdom
Tel: (44) 1932-349401
FAX: (44) 1932-349499
XILlNX, Ltd.
(Northern European Sales)
Suite 1 B Cobb House
Oyster Lane
Byfleet, Surrey
KT147DU
United Kingdom
Tel: (44) 1932-349403
FAX: (44) 1932-345519
XILINX SARL
Espace Jouy Technology
21, rue Albert Calmette, BI. C
78353 Jouy En Josas, Cedex
France
Tel: (33) 1 346301 01
FAX: (33) 1 34 63 01 09
XILINX GmbH
Suskindstr.4
0-81929 Munchen
Germany
Tel: (49) 89-93088-0
Tech Support Tel:
(49) 89-93088-130
FAX: (49) 89-93088-188
XILlNXAB
Box 1230
Torshamnsgatan 35
S-164 28 Kista
Sweden
Tel: (46) 8-752-2470
FAX: (46) 8-750-6260
E-mail: xilinx-nordic@xilinx.com
November 19, 1997 (Version 1.1)
JAPAN
XILINX K. K.
Daini-Nagaoka Bldg. 2F
2-8-5, Hatchobori, Chuo-ku
Tokyo 104
Japan
Tel: (81) 3-3297-9191
FAX: (81) 3-3297-9189
ASIA PACIFIC
XILINX Asia Pacific
Unit 4312, Tower"
Metroplaza
Hing Fong Road
Kwai Fong, N.T.
Hong Kong
Tel: (852) 2-424-5200
FAX: (852) 2-494-7159
E-mail: hongkong@xilinx.com
XILINX Korea
Room #901
Sambo-Hojung Bldg.,
14-24, Yoido-Dong
Youngdeungpo-Ku
Seoul, South Korea
Tel: (82) 2-761-4279
FAX: (82) 2-761-4278
XILINX Taiwan
Rm. 1006, 10F, No.2, Lane 150
Sec. 5, Hsin Yin Rd.
Taipei, Taiwan, R.O.C.
Tel: (886) 2-758-8373
FAX: (886) 2-758-8367
North American
Distributors
Hamilton Hallmark
Locations throughout
the U.S. and Canada.
Tel: (800) 332-8638
FAX: (800) 257-0568
Insight Electronics
(Locations throughout the U.S.)
Tel: (800) 677-7716
FAX: (619) 587-1380
Marshall Industries
(Locations throughout
the U.S. and Canada)
Tel: (800) 522-0084
FAX: (818) 307-6297
Nu Horizons
Electronics Corp.
Locations throughout the U.S.
Tel: (516) 396-5000
FAX: (516) 396-7576
U.S. Sales
Representatives
ALABAMA
Electro Source, Southeast
4825 University Sq., Ste.12
Huntsville, AL 35816
Tel: (205) 830-2533
FAX: (205) 830-5567
ARIZONA
Quatra Associates
10235 S. 51st SI. Suite #160
Phoenix, AZ 85044
Tel: (602) 753-5544
FAX: (602) 753-0640
E-mail: quatra@earthlink.net
ARKANSAS
Bonser-Philhower Sales
689 W. Renner Road
Suite 101
Richardson, TX 75080
Tel: (972) 234-8438
FAX: (972) 437-0897
CALIFORNIA
Norcomp
1267 Oakmead Pkwy
Sunnyvale, CA 94086
Tel: (408) 733-7707
FAX: (408) 774-1947
Norcomp
8880 Wagon Way
Granite Bay, CA 95746
Tel: (916) 791-7776
FAX: (916) 791-2223
Norcomp
30101 Agoura CI. #234
Agoura, CA 91301
Tel: (818) 865-8330
FAX: (818) 865-2167
I
Norcomp
30 Corporate Park #200
Irvine, CA 92714
Tel: (714) 260-9868
FAX: (714) 260-9659
15-1
Sales Offices, Sales Representatives, and Distributors
Quest-Rep Inc.
6494 Weathers PI, Suite 200
San Diego, CA 92121
Tel: (619) 622-5040
FAX: (619) 622-9007
E-mail: questrep@questrep.com
IDAHO (Southwest)
LOUISIANA (Southern)
MONTANA
Luscombe Engineering, Inc.
6901 Emerald, Suite 206
Boise, 10 83704
Tel: (208) 377-1444
FAX: (208) 377-0282
Bonser-Philhower Sales
10700 Richmond, Suite 150
Houston, TX 77042
Tel: (713) 782-4144
FAX: (713) 789-3072
Luscombe Engineering, Inc.
670 East 3900 South #103
Salt Lake City, UT 84107
Tel: (801) 268-3434
FAX: (801) 266-9021
COLORADO
Luscombe Engineering, Inc.
1500 Kansas Ave. Suite 1B
Longmont, CO 80501
Tel: (303) 772-3342
FAX: (303) 772-8783
CONNECTICUT
John E. Boeing, Co., Inc.
101 Harvest Park, Bldg.1A
No. Plains Industrial Road
Wallingford, CT 06492
Tel: (203) 265-1318
FAX: 203-265-0235
DELAWARE
Delta Technical Sales, Inc.
122 N. York Rd., Suite 9
Hatboro, PA 19040
Tel: (215) 957-0600
FAX: (215) 957-0920
FLORIDA
Semtronic Assoc., Inc.
(Disti Office)
600 S. Northlake Blvd. #270
Altamonte Springs, FL 32701
Tel: (407) 831-0451
FAX: (407) 831-6055
Semtronic Assoc., Inc.
657 Maitland Avenue
Altamonte, Springs, FL 32701
Tel: (407) 831-8233
FAX: (407) 831-2844
Semtronic Assoc., Inc.
3471 NW 55th Street
Ft. Lauderdale, FL 33309
Tel: (954) 731-2384
FAX: (954) 731-1019
Semtronic Assoc., Inc.
1467 South Missouri Avenue
Clearwater, FL 33756
Tel: (813) 461-4675
FAX: (813) 442-2234
Thorson Pacific, Inc.
14575 Bel-Red Road #102
Bellevue, WA 98007
Tel: (425) 603-9393
FAX: (425) 603-9380
ILLINOIS
Advanced Technical Sales
13755 St. Charles Rock Rd.
Bridgeton, MO 63044
Tel: (314) 291-5003
FAX: (314) 291-7958
Beta Technology Sales, Inc.
1009 Hawthorn Drive
Itasca, IL 60143
Tel: (708) 250-9586
FAX: (708) 250-9592
INDIANA
Gen II Marketing,lnc.
31 E. Main St.
Carmel, IN 46032
Tel: (317) 848-3083
FAX: (317-848-1264
Gen II Marketing, Inc.
1415 Magnavox Way
Suite 130
Ft. Wayne, IN 46804
Tel: (219) 436-4485
FAX: (219) 436-1977
IOWA
Advanced Technical Sales
375 Collins Road NE
Cedar Rapids, IA 52402
Tel: (319) 393-8280
FAX: (319) 393-7258
KANSAS
Advanced Technical Sales
2012 Prairie Cir. Suite A
Olathe, KS 66062
Tel: (913) 782-8702
FAX: (913) 782-8641
GEORGIA
KENTUCKY
Electro Source, Southeast
3280 Pointe Parkway,
Suite 1500
Norcross, GA 30092
Tel: (770) 734-9898
FAX: (770) 734-9977
Gen II Marketing, Inc.
861 Corporate Dr. #210
Lexington, KY 40503
Tel: (606) 223-9181
FAX: (606) 223-2864
LOUISIANA (Northern)
Bonser-Philhower Sales
689W. Renner Rd., Suite 101
Richardson, TX 75080
Tel: (972) 234-8438
FAX: (972) 437-0897
15-2
MAINE
NEBRASKA
Genesis Associates
128 Wheeler Road
Burlington, MA 01803
Tel: (617) 270-9540
FAX: (617) 229-8913
Advanced Technical Sales
375 Collins Road NE
Cedar Rapids, IA 52402
Tel: (319) 393-8280
FAX: (319) 393-7258
MARYLAND
NEVADA
Micro Comp, Inc.
1421 S. Caton Avenue
Baltimore, MD 21227-1082
Tel: (410) 644-5700
FAX: (410) 644-5707
Norcomp
8880 Wagon Way
Granite Bay, CA 95748
Tel: (916) 393-8280
FAX: (916) 393-7258
MASSACHUSETTS
Quatra Associates
(Las Vegas)
4645 S. Lakeshore Dr., Suite 1
Tempe, AZ 85282
Tel: (602) 820-7050
FAX: (602) 820-7054
Genesis Associates
128 Wheeler Road
Burlington, MA 01803
Tel: (617) 270-9540
FAX: (617) 229-8913
MICHIGAN
NEW HAMPSHIRE
Miltimore Sales Inc.
22765 Heslip Drive
Novi, MI 48375
Tel: (248) 349-0260
FAX: (248) 349-0756
Genesis Associates
128 Wheeler Road
Burlington, MA 01803
Tel: (617) 270-9540
FAX: (617) 229-8913
Miltimore Sales Inc.
3680 44th St., Suite 100-J
Kentwood,Ml49512
Tel: (616) 554-9292
FAX: (616) 554-9210
MINNESOTA
Beta Technology
18283 Minnetonka Blvd.
SuiteC
Deephaven, MN 55391
Tel: (612) 473-2680
FAX: (612) 473-2690
NEW JERSEY (Northern)
Parallax
734 Walt Whitman Road
Melville, NY 11747
Tel: (516) 351-1000
FAX: (516) 351-1606
NEW JERSEY (Southern)
Delta Technical Sales, Inc.
122 N. York Road, Suite 9
Hatboro, PA 19040
Tel: (215) 957-0600
FAX: (215) 957-0920
MISSISSIPPI
NEW MEXICO
Electro Source, Southeast
4835 University Sq., Ste.ll
Huntsville, AL 35816
Tel: ( 205)-830-2533
FAX: (205) 830-5567
Quatra Associates
600 Autumnwood Place, SE
Albuquerque, NM 87123
Tel: (505) 296-6781
FAX: (505) 292-2092
MISSOURI
NEW YORK (Metro)
Advanced Technical Sales
2012 Prairie Cir. Suite A
Olathe, KS 66062
Tel: (913) 782-8702
FAX: (913) 782-8641
Parallax
734 Walt Whitman Road
Melville, NY 11747
Tel: (516) 351-1000
FAX: (516) 351-1606
Advanced Technical Sales
13755 St. Charles Rock Rd.
Bridgeton, MO 63044
Tel: (314) 291-5003
FAX: (314) 291-7958
November 19, 1997 (Version 1.1)
-----------~
~~----
~XILlNX
NEW YORK
Electra Sales Corp.
333 Metro Park
Suite M103
Rochester, NY 14623
Tel: (716) 427-7860
FAX: (716) 427-0614
Electra Sales Corp.
6700 Old Collamer Rd.
E. Syracuse, NY 13057
Tel: (315) 463-1248
FAX: (315) 463-1717
NORTH CAROLINA
Electro Source, Southeast
5964-A Six Forks Rd.
Raleigh, NC 27609
Tel: (919) 846-5888
FAX: (919) 846-0408
NORTH DAKOTA
Beta Technology
18283 Minnetonka Blvd,
SuiteC
Deephaven, MN 55391
Tel: (612) 473-2680
FAX: (612) 473-2690
OHIO
Bear Marketing, Inc.
3554 Brecksville Road
PO Box 427
Richfield, OH 44286-0427
Tel: (216) 659-3131
FAX: (216) 659-4823
Bear Marketing, Inc.
270 Regency Ridge Drive
Suite 115
Dayton, OH 45459
Tel: (513) 436-2061
FAX: (513) 436-9137
OKLAHOMA
Bonser-Philhower Sales
689 W. Renner Rd., Suite 101
Richardson, TX 75080
Tel: (972) 234-8438
FAX: (972) 437-0897
OREGON
Thorson Pacific, Inc.
9600 SW Oak Street,
Suite 320
Portland, OR 97223
Tel: (503) 293-9001
FAX: (503) 293-9007
PENNSYLVANIA
Bear Marketing, Inc.
4284 Rt. 8, Suite 211
Allison Park, PA 15101
Tel: (412) 492-1150
FAX: (412) 492-1155
Delta Technical Sales, Inc.
122 N. York Rd., Suite 9
Hatboro, PA 19040
Tel: (215) 957-0600
FAX: 215-957-0920
PUERTO RICO
Semtronic Assoc., Inc
Crown Hills
125 Carite St.
Esq. Avenue Parana
Rio Piedras, P. R. 00926
Tel: (787) 766-070010701
FAX: (787) 763-8071
TEXAS (EI Paso County)
WISCONSIN (Eastern)
Quatra Associates
600 Autumnwood Place SE
Albuquerque, NM 87123
Tel: (505) 296-6781
FAX: (505) 292-2092
Beta Technology Sales, Inc.
9401 N. Beloit, Suite 409
Milwaukee, WI 53227
Tel: (414) 543-6609
FAX: (414) 543-9288
UTAH
WYOMING
Luscombe Engineering Co.
670 East 3900 South #103
Salt Lake City, UT 84107
Tel: (801) 268-3434
FAX: (801) 266-9021
Luscombe Engineering, Inc.
1500 Kansas Ave. Suite 1B
Longmont, CO 80501
Tel: (303) 772-3342
FAX: (303) 772-8783
RHODE ISLAND
VERMONT
Genesis Associates
128 Wheeler Road
Burlington, MA 01803
Tel: (617) 270-9540
FAX: (617) 229-8913
Genesis Associates
128 Wheeler Road
Burlington, MA 01803
Tel: (617) 270-9540
FAX: (617) 229-8913
SOUTH CAROLINA
VIRGINIA
Electro Source, Southeast
5964-A Six Forks Rd.
Raleigh NC 27609
Tel: (919) 846-5888
FAX: (919) 846-0408
Microcomp, Inc.
1421 S. Caton Avenue
Baltimore, MD 21227
Tel: (410) 644-5700
FAX: (410) 644-5707
Development Centre of
Advanced Technologies
128 Chemin Mohamed GACEM
16075 EI-Madania
Algiers
Algeria
Tel: (213) 2-67-73-25
FAX: (213) 2-66-26-89
SOUTH DAKOTA
WASHINGTON
AUSTRALIA
Beta Technology
18283 Minnetonka Blvd.
SuiteC
Deephaven, MN 55391
Tel: (612) 473-2680
FAX: (612) 473-2690
Thorson Pacific, Inc.
14575 Bel-Red Rd.
Suite 102
Bellevue, WA 98007
Tel: (206) 603-9393
FAX: (206) 603-9380
Advanced Component Dist.
Suite 5, Level 1, "Metro Centre"
124 Forest Rd.
P.O. Box 574, Hurstville 2220
Australia
Tel: (61) 2-9585-5030
FAX: (61) 2-9590-1095
TENNESSEE
WASHINGTON
(Vancouver, WA only)
Electro Source, Southeast
4825 University Square,
Suite 12
Huntsville, AL 35816
Tel: (205) 830-2533
FAX: (205)-830-5567
TEXAS
Bonser-Philhower Sales
8240 MoPac Expwy.
Suite 295
Austin, TX 78759
Tel: (512) 346-9186
FAX: (512) 346-2393
Bonser -Philhower Sales
10700 Richmond, Suite 150
Houston, TX 77042
Tel: (713) 782-4144
FAX: (713) 789-3072
Bonser-Philhower Sales
689 W. Renner Rd., Suite 101
Richardson, TX 75080
Tel: (972) 234-8438
FAX: (972) 437-0897
November 19, 1997 (Version 1.1)
Thorson Pacific, Inc.
9600 SW Oak Street
Suite 320
Portland, OR 97223
Tel: (503) 293-9001
FAX: (503) 993-9007
WASHINGTON D.C.
Micro Comp, Inc.
1421 S. Caton Avenue
Baltimore, MD 21227-1082
Tel: (410) 644-5700
FAX: (410) 644-5707
WEST VIRGINIA
Bear Marketing, Inc.
4284 Rt. 8 Suite 211
Allison Park, PA 15101
Tel: (412) 492-1150
FAX: (412) 492-1155
WISCONSIN (Western)
Beta Technology
18283 Minnetonka Blvd.
Suite C
Deephaven, MN 55391
Tel: (612) 473-2680
FAX: (612) 473-2690
International Sales
Representatives
ALGERIA
Advanced Component Dist.
Unit 2,17-19 Melrich Road
Bayswater VIC 3153
Melbourne, Australia
Tel: (61) 3-9762-4244
FAX: (61) 3-9761-1754
Advanced Component Dist.
20D William Street
Norwood SA 5067
Australia
Tel: (61) 8-364-2844
FAX: (61) 8-364-2811
Advanced Component Dist.
Ste. 1, 1048 Beaudesert Rd.
Cooper Plains
Queensland 4108
Australia
Tel: (61) 7-246-5214
FAX: (61) 7-275-3662
Advanced Component Dis!.
Ste. 8, 328 Albany Highway
Victoria Park
W.A.6100
Australia
Tel: (61) 9-9472-3232
FAX: (61) 9-9470-9632
15-3
I
Sales Offices, Sales Representatives, and Distributors
AUSTRIA
SEI Elbatex GmbH
Eitnergasse 6
1230 Vienna
Austria
Tel: (43) 1-866-4220
FAX: (43) 1-866-42201
BELGIUM & LUXEMBURG
SEI Rodelco NV
Limburg Stirum 243
1780Wemmel
Belgium
Tel: (32) 2-456-0757
FAX: (32) 2-460-0271
BULGARIA
Elbatex BUL d.o.o.
1 Philip Kutev Str.
BG-1474 Sofia
Bulgaria
Tel: (35) 92-962-5649
FAX: (35) 92-962-5252
CANADA (ALBERTA)
Electro Source
2635 37th Ave NE #245
Calgary, Alberta Tl Y 5Z6
Canada
Tel: (403) 735-6230
FAX: (403) 735-0599
CANADA
(BRITISH COLUMBIA)
Thorson Pacific, Inc.
4170 Still Creek Dr. #200
Burnaby BC V5C 6C6
Canada
Tel: (604) 294-3999
FAX: (604) 473-7755
CANADA (OnAWA)
Electro Source, Inc.
300 March Road, Suite 203
Kanata, Ontario K2K 2E4
Canada
Tel: (613) 592-3214
FAX: (613) 592-4256
CANADA (QUEBEC)
Electro Source
6600 TransCanada Hwy
Suite 420
Pointe Claire, Quebec H9R 4S2
Canada
Tel: (514) 630-7486
FAX: (514) 630-7421
CANADA (TORONTO)
Electro Source, Inc.
230 Galaxy Blvd.
Rexdale Ontario M9W 5R8
Canada
Tel: (416) 675-4490
FAX: (416)-675-6871
15-4
CHINA PEOPLE'S
REPUBLIC
MEMEC (Beijing Rep. Office)
Rm. 410, Xuhai Bldg.
No. 85 Haidian Rd.
Beijing, 10086
P.R. China
Tel: (86) 10-6253-5475
FAX: (86) 10-6263-0183
MEMEC (Chengdu Rep. Office)
Rm. 1808, Tong Mei Mansion,
No. 76, Section 1,
Jianshe North Rd.,
Chengdu, Sichuan 610051
P.R. China
Tel: (86) 28-3399-629
FAX: (86) 28-3398-829
MEMEC (Shenzhen Rep. Office)
Rm. 715, Bao Hua Bldg.,
Hua Oiang North Rd.,
Shenzhen 518031
P.R. China
Tel: (86) 755-3241-548
FAX: (86) 755-3233-026
MEMEC Asia Pacific Ltd.
Shanghai Rep. Office
Rm. 2363, West Building
Jim Jiang Hotel
59 Mao Ming Rd. S.,
Shanghai 200020
P.R. China
Tel: (86) 21-6258-2582
FAX: (86) 21-6415-1116
CZECH REPUBLIC
Elbatex Praha S.R.O.
Novodvorska 994
CZ-14221 Praha
Czech Republic
Tel: (42) 2--476-3707
FAX: (42) 2-476-3708
elbaprag@elbatex.cz
DENMARK
Micronor AlS
P.O. Box 929
Torvet 1
DK-8600 Silkeborg
Denmark
Tel: (45) 8681-6522
FAX: (45) 8681-2827
E-Mail: e-mail@micronor.dk
WWW: http://www.micronor.dk
EGYPT
Guide System Integrators
27 Mokhles AI-Alfi St.
First - Zone Nasr City
Cairo
Egypt
Tel: (20) 2-401-4085
FAX: (20) 2-401-4997
E-Mail: obadr@idsc.gov.eg
AVNET Composants
Nantes
Le Sillon de Bretagne
23e etage-Aile C
8 Av. des Thebaudieres
44802 Saint Herblain
France
Tel: (33) 240169850
FAX: (33) 2 40 63 22 88
FINLAND
Memec Finland Oy
Vernissakatu 6
01300
Vantaa
Finland
Tel: (358) 9-836-2600
FAX: (358) 9-8362-6027
FRANCE
REP'TRONIC
1 Bis, rue Marcel Paul
Z.1. La Bonde
91742 Massy
France
Tel: (33) 1 69536720
FAX: (33) 1 601391 98
E-Mail:
100745.605@compuserve.com
AVNET/EMG.
79 Rue Pierre Semard
92320 Chatillon
France
Tel: (33) 1 49 65 27 00
FAX: (33) 1 49 65 27 39
AXESS Technology
Agence: Bretagne
3 Square du Chene Germain
35510 Cesson-Sevigne
France
Tel: (33) 2 99 36 83 83
FAX: (33) 2 99 36 53 92
AXESS Technology
Agence: Sud-ouest
7, Impasse de la Marjerine
31240 L:Union
France
Tel: (33) 561 099944
FAX: (33) 5 61091979
AVNET Compos ants
Sud-Ouest
Technoparc
Bat.4, Voie 5, BP 404
31314 Labege Cedex
France
Tel: (33) 5 61 3921 12
FAX: (33) 5 61 3921 40
AXESS Technology
Agence: Rhone-Alpes
23 Ie Grand FranQois
La Courtbatiere
38140 Rives
France
Tel: (33) 4 76 91 4530
FAX: (33) 4 76 91 45 34
AVNET Composants
Rhone-Auvergne
Parc Club du Moulin Vent
Bat 32-33, rue du Dr. G. Levy
69693 Venissieux Cedex
France
Tel: (33) 4 78 001280
FAX: (33) 4 78 75 95 97
a
GERMANY
AVNET Composants
Ouest
Technoparc-Bat. E
4 Av. des Peupliers, BP 43
35511 Cesson Sevigne Cedex
France
Tel: (33) 2 99 83 84 85
FAX: (33) 2 99 83 80 83
AVNET Composants
RhOne-Alpes
Zac des Bealieres
23 Av. de Granier
38240 Meylan
France
Tel: (33) 4 76 90 11 88
FAX: (33) 4 76 41 04 90
AXESS Technology
49 rue de l'Esterel
Silic 600
94663 Rungis Cedex
France
Tel: (33) 1 49789494
Fax: (33) 1 49 78 03 24
Avnet EMG GmbH
Stahlgruberring 12
81829 MOnchen
Germany
Tel: (49) 89-45110-01
FAX: (49) 89-45110-129
Avnet EMG GmbH
KurfOrstenstr. 130
10785 Berlin
Germany
Tel: (49) 30-214882-0
FAX: (49) 30-2141728
Avnet EMG GmbH
Friedrich-Ebert-Damm 145
22047 Hamburg
Germany
Tel: (49) 40-696952-0
FAX: (49) 40-6962787
November 19, 1997 (Version 1.1)
-----'"'----
---------,-----~--
----------------------
~XILlNX
Avnet EMG GmbH
Benzstr.l
70839 Gerlingen
Stuttgart, Germany
Tel: (49) 7156-4390
FAX: (49) 7156-4390-111
Avnet EMG GmbH
Heinrich-Hertz-Str.52
40699 Erkrath
Ousseldorf, Germany
Tel: (49) 211-92003-0
FAX: (49) 211-9200399
Avnet EMG GmbH
Schmidtstr. 49
60326 FrankfurtlM.
Germany
Tel: (49) 69-973804-0
FAX: (49) 69-7380712
Avnet EMG GmbH
Further Str. 212
90429 Nurnberg
Germany
Tel: (49) 911-93149-0
FAX: (49) 911-320821
Intercomp
Am Hochwald 42
0-82319
Starnberg, Germany
Tel: (49) 8151-16044
FAX: (49) 8151-79270
E-Mail:
intercomp.tiefenthaler@tonline.de
Intercomp
Kniebisstr. 40/1
78628 Rottweil
Stuttgart, Germany
Tel: (49) 741-14845
FAX: (49) 741-15220
E-Mail:
intercomp.klink@t-online.de
Intercomp
Schustergasse 35
55278 Kongernheim
Frankfurt, Germany
Tel: (49) 6737-9881
FAX: (49) 6737-9882
E-Mail:
intercomp.hakam@t-online.de
Metronik GmbH
Leonhardsweg 2
82008 Unterhaching
Munchen, Germany
Tel: (49) 89-611-080
FAX: (49) 89-611-08110
Metronik GmbH
Zum Lonnenhohl 40
0-44319 Oortmund
Germany
Tel: (49) 231-9271-10-0
FAX: (49) 231-9271-10-99
E-Mail:
10063.44@compuserve.com
Metronik GmbH
Carl-Zeiss Str.6
0-25421 Quickborn
Hamburg Germany
Tel: (49) 4106-77-30-50
FAX: (49) 4106-77-30-52
Metronik GmbH
Osmiastrasse 9
0-69221 Oossenheim
Mannheim, Germany
Tel: (49) 6221-8-70-44
FAX: (49) 6221-8-70-46
Metronik GmbH
Pilotystr. 27/29
90408 Nurnberg
Germany
Tel: (49) 89-611-08-145
FAX: (49) 89-611-08-144
Metronik GmbH
L6wenstrasse 37
70597 Stuttgart
Germany
Tel: (49) 711-764-033
FAX: (49) 711-765-5181
E-Mail:
100751.334@compuserve.com
Metronik GmbH
Franz-Schubert-Str.41
0-16548 Glienicke
Berlin, Germany
Tel: (49) 33056-845-0
FAX: (49) 33056-845-50
Metronik GmbH
Sch6nauer Strasse 113
0-04207 Leipzig
Germany
Tel: (49) 341-423-9413
FAX: (49) 341-423-9424
Metronik GmbH
Bahnstrasse 9
0-65205 Wiesbaden
Germany
Tel: (49)611-973-84-0
FAX: (49) 611-973-8418
GREECE
Semicon
104 Aeolou Str.
10564 Athens
Greece
Tel: (30) 1-32-536-26
Fax: (30) 1-32-160-63
E-Mail: semicon@hellas.eu.net
November 19, 1997 (Version 1.1)
HONG KONG
MEMEC Asia Pacific Ltd.
Units 3601-02 & 07-25, Tower I,
Metroplaza, Hing Fong Road,
Kwai Fong, N.T.
Hong Kong
Tel: (852) 2410-2780
FAX: (852) 2401-2518
HUNGARY
Elbatex HUN Kr
GF-NN
Szigetvari U.5
H-l083 Budapest
Hungary
Tel: (36) 1-269-9093/95
FAX: (36) 1-269-9096
INDIA
CG-CoreEI Logic System Ltd.
First Floor, Surya Bhavan
1181 Fergusson College Rd.
Pune 411 005 Maharashtra
India
Tel: (91) 212-323982, 328074,
328362
FAX: (91) 212-323985
Email: xsupport@cromp.ernet.in
CG-CoreEL Logic System Ltd.
961 Main
HAL 2nd Stage
Bangalore 560 008
India
Tel: (91) 80-527-9726
FAX: (91) 80-527-9726
E-Mail:
vishwa@giasbgOl.vsnLnet.in
Acsis Sri
Via B. Battista Spagnoli, 61
00144 Roma
Tel: (39) 6-529-6589
FAX: (39) 6-529-6588
Avnet EMG
Centro Oirezionale
Via Novara, 570
CAP 20153 Milan
Italy
Tel: (39) 2-381-901
FAX: (39) 2-380-02988
Avnet EMG
Ancona
Via Adriatica, 13
60022 Castelfidardo
Tel: (39) 71-781-9644
FAX: (39) 71-781-9699
Avnet EMG
Firenze
Via Panciatichi, 40
50127 Firenze
Tel: (39) 55-436-0392
FAX: (39) 55-431-035
AvnetEMG
Modena
Via Scaglia Est, 144
41100 Modena
Tel: (39) 59-351-300
FAX: (39) 59-344993
IRELAND
AvnetEMG
Napoli
Via Ferrante Imparato, 27
80146 Napoli
Tel: (39) 81-55-91477
FAX: (39) 81-55-91580
Memec Ireland Ltd.
Gardner House
Bank Place
Limerick
Ireland
Tel: (353) 61-411842
FAX: (353) 61-411888
E-Mail: memec@iol.ie
Avnet EMG
Roma
Via Zoe Fontana, 220
Technocitta
00131 Roma
Tel: (39) 64-13-1151
FAX: (39) 64-13-1161
ISRAEL
E.I.M. International Ltd.
9 Hashiioach.Street
P.O. Box 4000
Kiryat Arye
Petach Tikva 49130
Israel
Tel: (972) 3-926-4666
FAX: (972) 3-924-4857
ITALY
Acsis Sri
Via Alberto Mario, 26
20149 Milano, Italy
Tel: (39) 2-480-22522
FAX: (39) 2-480-12289
WWW: http://www.acsis.it
AvnetEMG
Torino
Corso Orbassano, 336
10137 Torino
Tel: (39) 11-311-2347
FAX: (39) 11-308-2138
Avnet EMG
Treviso
Via Oelle Querce, 7
31033 Castelfranco Veneto
Tel: (39) 423-722-675
FAX: (39) 423-722-671
I
Silverstar-Celdis
Viale Fulvio Testi, 280
20126 Milano, Italy
Tel: (39) 2-661-251
FAX: (39) 2-661-01-359
15-5
Sales Offices, Sales Representatives, and Distributors
Silverstar-Celdis
Via Collamarini, 22
40138 Bologna, Italy
Tel: (39) 51-53-8500
FAX: (39) 51 '53-8831
Silverstar-Celdis
Via G. Antonio Resti, 63
00143 Roma, Italy
Tel: (39) 6-519-57527
FAX: (39) 6-504-3330
Silverstar-Celdis
Centro Piero Della Francesca
Corso Svizzera, 185 Bis
10149 Torino, Italy
Tel: (39)11-77-10082
FAX: (39) 11-77-64921
Silverstar-Celdis
Centro Direzionale Benelli
Via Degli Abeti, 346
6100 Pesaro, Italy
Tel: (39) 721-26-560
FAX: (39) 721-400896
Silverstar-Celdis
Via A.da Noli, 6
50127 Firenze, Italy
Tel: (39) 55-43-5125
FAX: (39) 55-43-77184
Silverstar-Celdis
Via. delle Indus, 13
35010 Umena
Padova, Italy
Tel: (39) 49-88-40044
FAX: (39) 49-88-41079
Silverstar-Celdis
Via Famagosta, 1/5
17100 Savona, Italy
Tel: (39) 19-81-5090
FAX: (39) 19-81-5091
JAPAN
Kaga Electronics Co., Ltd.
1-26-1 Otowa
Bunkyo-ku
Tokyo 112, Japan
Tel: (81) 3-3942-6224
FAX: (81) 3-3942-6215
Marubun Corporation
8-1 Odenma-cho
Nihonbashi
Chuo-ku
Tokyo, 103 Japan
Tel: (81) 3-3639-9851
FAX: (81) 3-3639-9925
Okura Electronics Co., Ltd.
3-6, Ginza 2-chome,
Chuo-ku,
Tokyo, 104 Japan
Tel: (81) 3-3564-6871
FAX: (81) 3-3564-6870
15-6
Okura Electronics
Service Co., Ltd.
Yokota Bldg.
Ginza 2-11-5
Chuo-Ku
Tokyo, 104 Japan
Tel: (81) 3-3545-2360
FAX: (81) 3-3545-2351
Tokyo Electron Ltd.
TBS Broadcasting Center
5-3-6- Akasaka, Minato-Ku
Tokyo, 163 Japan
Tel: (81) 3-5561-7212
FAX: (81) 3-5561-7389
Towa Elex Co., Ltd.
Genbe Bldg.
5-4 Nihonbashi Tomisawa-cho
Chuo-Ku, Tokyo 103
Japan
Tel: (81) 3-5640-1241
FAX: (81) 3-5640-1240
THE NETHERLANDS
Rodelco BV
P.O. Box 6824
Takkebijsters 2
4802 HV Breda
The Netherlands
Tel: (31) 76-5722700
FAX: (31) 76-5710029
NEW ZEALAND
POLAND
Elbatex POL s.z.o
Wilcza 50/52
PL-00-879 Warszawa
Poland
Tel: (48) 22-621-7122
FAX: (48) 22-623-0605
Email: elbatex@ikp.atm.com.pl
Eljapex 0.0.0.
Stenge 25
SLO-81 000 Lalbach
Tel: (38) 661-159-7198
FAX: (38) 661-159-2398
Scan
10/32 "B" Druzhby SI.
117330 Moscow
Russia
Tel: (7) 095-232-2343
FAX: (7) 095-938-2247
SOUTH AFRICA
Avnet - ASD
Avnet Kopp (Pty) Ltd.
PO Box 3853
Rivonia 2128
South Africa
Tel: (27) 11 4442333
FAX: (27) 11 4447778
Scan
42 Ordjonikidze
196143 SI. Petersburg
Russia
Tel: (7) 812-299-7028
FAX: (7) 812-264-6000
Scan Pulsar
9 Rogaliova SI.
Dniepropetrovsk 320030
Ukrain
Tel: (7) 0562-472870
FAX: (7) 0562-451115
BIT Elektronikk AS
Smedsvingen 4
P.O. Box 194
1360 Nesbru
Norway
Tel: (47) 66-77-65-00
FAX: (47) 66-77-65-01
SLOVENIA/CROATIA
RUSSIA
Advanced Component Dis!.
Worchester Chambers
69 Worcester SI.
Christchurch
New Zealand
Tel: (64) 3-379-3889
FAX: (64) 3-379-3072
NORWAY
Elbatex SK S.R.O.
Kasmirska 7
SK-821 04 Bratislava
Tel: (42) 7-295007
FAX: (42) 7-5220600
Email: ek.elbatex@netlab.sk
ADM Electronica SA
en 107, No 743
Aguas Santas
4445 Ermesinde
Portugal
Tel: (35) 1-297-36957
FAX: (35) 1-297-36958
Scan
14 Plekhanova SI.
Voronezh 394000
Russia
Tel: (7) 0732-718189
FAX: same
MEMEC EBV (NZ) Ltd.
Suite 5a, Level 4,
North City Plaza,
Titahi Bay Rd., Porirua,
Wellington, New Zealand
Tel: (64) 4-237-9711
FAX: (64) 4-237-9718
SLOVAK REPUBLIC
PORTUGAL
Advanced Component Dis!.
Unit 7, 110 Mays Rd.
Penrose, Auckland
New Zealand
Tel: (64) 9-636-5984
FAX: (64) 9-636-5985
MEMEC Asia Pacific Ltd.
Singapore Representative
Office
10 Anson Road #23-08
International Plaza
Singapore 079903
Tel: (65)-222-4962
FAX: (65)-222-4939
SOUTH AMERICA
DTS Ltda.
Rosas 1444
Santiago
Chile
Tel: (56) 2-6970991
FAX: (56) 2-6993316
Hitech
Rua Branco de Moraes 489
Ch. Santo Antonio
Sao Paulo
04718-010 - SP - Brazil
Tel: (55) 11-882-4000
FAX: (55) 11-882-4100
Scan-West
217, 32 Asanbaljieva SI.
Minsk 220024
Belorussia
Tel: (7) 0172-269792
FAX: same
SINGAPORE
Frontline Technologies Ptc. Ltd
2 Science Park Drive #57
The Faraday
Singapore Science Park
Singapore 118222
Tel: (65)-779111
FAX: (65) 779-4455
Reycom Electronica SA
Bdo. de Irigoyen
972 Piso 2do "B"
1304 Buenos Aires
Argentina
Tel: (54) 1-304-2018
FAX: (54) 1-304-2010
SOUTH KOREA
Hyunmyung Electronics Co. Ltd.
3 FI, Dukwha Bldg.,
444-1 7, Seokyo-Dong,
Mapo-Ku, Seoul
South Korea
Tel: (82) 2-3141-0147
FAX: (82) 2-3141-0149
November 19, 1997 (VerSion 1.1)
~XIUNX
MEMEC Asia Pacific Ltd.
Rm. 501, Dae Ha Bldg.
14-11 Yoido-Dong
Youngdeungpo-Ku
Seoul,150-715
South Korea
Tel: (82) 2-786-8180
FAX: (82) 2-761-4121
Seodu Inchip
4 FI, Myoungi Bldg.,
142-21, Samsung-Dong,
Kangnam-Ku, Seoul
South Korea
Tel: (82) 2-563-8008
FAX: (82) 2- 563-8411
SOUTHEAST ASIA
MEMEC Asia Pacific Ltd.
Units 3601-02 & 07-25, Tower I,
Metroplaza, Hing Fang Road,
Kwai Fang, N.T.
Hong Kong
Tel: (852) 2410-2780
FAX: (852) 2401-2518
SPAIN
ADM Electronica SA
Calle Tomas Breton,
No 50, 3-2
28045 Madrid
Spain
Tel: (34) 1-530-4121
FAX: (34) 1-530-164
ADM Electronica, SA
Herriko Gudarien, 8-1 B
48200 Durango (Vizcaya)
Spain
Tel: (34) 4-620-1572
FAX: (34) 4- 620-2331
SWEDEN
DipCom Electronics AB
Torshamnsgatan 35
P.O. Box 1230
S-164 28 Kista
Sweden
Tel: (46) 8 752 24 80
FAX: (46) 8 751 3649
UNITED ARAB EMIRATES
Culato
P.O. Box 51973
Dubai
United Arab Emirates
Tel: (971)-4-284031
FAX: (971 )-4-284934
SWITZERLAND
UNITED KINGDOM
Fenner Elektronik AG
Abteilung Bauteile
Gewerbestrasse 10
CH-4450 Sissach
Switzerland
Tel: (41) 619750000
FAX: (41) 619715608
Avnet EMG Ltd.
TAIWAN
MEMEC Asia Pacific Ltd.
Rm. 1005, 10F, No.2, Lane 150
Sec.5, HSin Yin Rd.
Taipei, Taiwan R.O.C.
Tel: (886) 2-8780-1216
FAX: (886) 2-8780-1220
TURKEY
ADM Electronica SA
Calle Mallorca 1
08014 Barcelona
Spain
Tel: (34) 3-426-6892
FAX: (34) 3-425-0544
Eltronik Inc.
8427 Kennedy Boulevard
North Bergen
New Jersey 07047
USA
Tel: (201) 453-0410
FAX: (201) 453-0959
Eltronik Elektronik Sanayii Ve
Ticaret Ltd. SII.
Farabi Sokak No. 44/4
06690 Cankaya
Ankara, Turkey
Tel: (90) 312-467-9952
Fax: (90) 312-467-9828
Jubilee House
Jubilee Road
Letchworth
Hertfordshire SG6 1QH
England
Tel: (44) 1462-488500
FAX: (44) 1462-488567
Cedar Technologies
Unit One Old Barns
Rycote Lane Farm
Milton Common
Oxfordshire
OX92NZ
England
Tel: (44) 1844-278278
FAX: (44) 1844-278378
Memec Pic
17, Thame Park Road
Thame
Oxfordshire
OX93XD
England
Tel: (44) 1844-261919
FAX: (44) 1844-1683
Memec Ireland Ltd.
Garden House
Bank Place
Limerick
Eire
Tel: (353) 61-411842
FAX: (353) 61-411888
Email: memec@iol.ie
M icrocall Ltd.
The Gate House
Alton House Business Park
Gatehouse Way
Aylesbury, Bucks
HP193DL
England
Tel: (44) 1296-330061
FAX: (44) 1296-330065
Cedar Technologies
32 Enterprise House
Sprinkerse Business Park
Striling SK7 7UF
England
Tel: (44) 1786-446220
FAX: (44) 1786-446223
I
November 19, 1997 (Version 1.1)
15-7
Sales Offices, Sales Representatives, and Distributors
15-8
November 19, 1997 (Version 1 .1)
The Programmable Log ic CompanySM
2100 Logic Drive
San Jose, CA 95124-3400
Tel : 1-408-559-7778
Fax: 1-408-559-7114
e-mail: hotline@xilinx.com
web: www.xilinx.com
Printed in USA.
PN 00 10323
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:11:01 17:11:27-08:00 Modify Date : 2017:11:01 17:47:34-07:00 Metadata Date : 2017:11:01 17:47:34-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:1d9dd72e-9195-6a43-b5b2-bb0b20f46986 Instance ID : uuid:a6ad914a-f8bb-f54a-ae98-7ae9f0667414 Page Layout : SinglePage Page Mode : UseNone Page Count : 738EXIF Metadata provided by EXIF.tools