2000_TI_Interface_Products_Data_Book 2000 TI Interface Products Data Book

User Manual: 2000_TI_Interface_Products_Data_Book

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~TEXAS

[1JJ IUnitrode Products

.

_

INSTRUMENTS

from Texas Instruments

Interface Products (IF)

-

2000

Analog and Mixed-Signal
~==================

On October 15, 1999, Texas Instruments strengthened its ability to provide you with truly
premier Power Management solutions. We are proud to announce the acquisition of Power
Management expert Unitrode and Battery Management expert Benchmarq.
As you may know, Unitrode has a 40-year history of designing and supplying Power
Management components and subsystems. Benchmarq, based in Dallas and acquired by
Unitrode last year, has won multiple awards for its industry-leading Battery Management
solutions.
TI's commitment to the Power Management marketplace is already evident in its growing
portfoliO of industry-leading low dropout regulators, supply voltage supervisors, low-power
DC-DC converters, power distribution switches and processor power products. Now, with the
combination of TI's and Unitrode's high-performance products and TI's leading-edge process
technologies and packaging expertise, we are positioned to provide you with easy-to-use,
high-performance Power Management solutions.
Unitrode brings a family of products that complements TI's existing portfolio. TI's worldwide
network of service and support increases access to and support for the Unitrode and
Benchmarq portfolios. Most important, Unitrode brings to this union hundreds of experienced
employees dedicated to the Power Management market.
What's in this for you? TI and Unitrode designers are working together right now to develop
next-generation Power and Battery Management solutions. Maybe you're looking for
easy-to-design-in, turn-key solutions. Or perhaps you need high-performance products, and
complete systems and applications knowledge so you can put a power system together
yourself. Either way, TI is dedicated to satisfying all of your Power Management needs today
and in the future.
The combined TI and Unitrode Power Management offering comprises a rich portfolio that we
intend to build upon together. To find out more, including ordering samples, you can visit our
website at www.ti.comlsc/powerleader. complete the enclosed reply card, or call us for more
information, using the TI contact information found on the back cover of this book.

[11J

Introduction

Using Unitrode Data Books

Data sheets and other information about Unitrode's products are organized, by business line, into
four volumes: Interface (IF), Portable Power (PP), Power Supply Control (PP), and Nonvolatile
SRAMs and Real-Time Clocks (NV).
Each book contains general information as well as sections devoted to the specific business line.
Information in these books is referenced in several ways.

Data Sheet Types

v

v

v

v

Table of Contents

vi

vi

vi

vi

1-1

1-1

1-1

1-1

Master Application Note Index by Part Number

1-19

1-19

1-19

1-20

Master Application Note Index by Publication Number

1-24

1-24

1-24

1-25

Master Application Note Index

1-28

1-28

1-28

1-29

7-1

10-1

6-1

10-1

2-1

2-1

Master Part Number Index

Subject

Unitrode Product Portfolio

3-2
4-2
5-2

Product Cross-Reference Tables (NV Book Only)
Ordering Information

2-1

2-1

Reading the Indices
The master indices, contained in all four data books, list the location of all data sheets. Each entry is preceded by one of the following 2-letter abbreviations:
• IF
Interface
• NV
Nonvolatile SRAMs and Real-Time Clocks
• PP
Portable Power
• PS
Power Supply Control

[1JJ

Introd uction

Unitrode's Products

UnitrodeCorporatien is a world leader in the design and manufacture of. innovative,
high-performance linear and mixed~signal ICs and modules. This data book introduces the
Company's products designed for commercial, industrial, consumer, and military/aerospace applications.
Focused on power management, battery management, and· high-speed data communications,
products include:
• Off-line power management
• DC/DC power management
• Protection/supervisory circuits
• Portable power management
• Motion/motor qontrols
• High-speed interface
• Nonvolatile controllers and NVSRAMs
• Real-time clocks
Unitrode also offers an assortment of special function ICs, including fiber-to-curb ringers, CAN
transceivers, IrDA transceivers, cellular power-management products and pager/PDA power controllers.
All Unitrode products are backed by design and applications teams that understand tt:le interaction between the Company's products and rest of the power systemlsubsystem .. Unitrode designs
technically advanced products in response to customer needs and in anticipation of market
trends.
Whatever the application-Power Management, Battery Management, or Ultrafast Data Communications-Unitrode is an innovative, dependable and customer-driven source for catalog,
semi-custom, and custom Iinear/mixed-signaIICs and modules.

ii

-

[1JJ

Introduction
Worldwide Service
Unitrode serves its customers around the world from many locations:
• Design centers in New Hampshire, Texas, California, and North Carolina
• A facility in Dallas for assembly and manufacturing
• A facility in Singapore for testing, assembly subcontractor coordination, and customer
service
• A worldwide network of manufacturers' representatives and distributors

Process Capabilities
Unitrode's bipolar process, optimized for both precision-analog and power functions, is constantly
updated with the latest process options, such as:
• Operating-voltage ranges from 4-65V
• Schottky and integrated injection logic
• Ion implant
• Thin-film resistors for high accuracy
• Double-level metallization for high-density, high-current layouts and buried zener reference
The Company's BiCMOS process is ideal for high-density linear and mixed-mode designs, especially where speed and low power-consumption are of primary importance.
Options include:
• 3-, 2.5-, and 1-micron processes
• Up to 15V operation
• High-current, double-level metallization
• 125 fully isolated, vertical NPN transistors
• Thin-film resistors
This year, a new BCDMOS process offers all the options available with BiCMOS, as well as a lateral DMOS device with up to 35V operation for added power-handling capability.

An 1509001 and 9002 Firm
Unitrode was one of the first U.S. linear/analog manufacturers to achieve IS/ISO 9001/EN29001
registration, and in 1998, the registrars completed recertification of the Merrimack and Singapore
facilities and renewed the Company's registration to ISO 9001/9002-1994, respectively.
To be registered, the Company passed a rigorous examination of its quality systems-from product design through shipment. These registrations thus assure customers all over the world that
Unitrode is adhering to very high, precisely defined standards.

Listening To Customers
To develop custom and semi-custom parts, Unitrode design engineers work very closely with
customers, so all requirements are accurately understood, all possibilities are fully explored, and
all products meet or exceed specified needs.
Unitrode also pays careful attention to customers and markets to help guide its development of
catalog parts. Continuing close contact makes it possible to anticipate industry requirements, and
to create devices that satisfy them.

iii

-

G::JJ

Introduction
Important Notice

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or
to discontinue any product or service without notice,and advise customers to obtain the latest
version of relevant information to verify, before placing orders, that. information being relied on is
current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time
of sale in accordance with TI's standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL
RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL
DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT
DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S
RISK.
In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is grantE;ld under any patent right,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
combination, machine, or process in which such semiconductor products or services might be or
are used. TI's publication of information regarding any third party's products or services does not
constitute TI's approval, warranty or endorsement thereof.

Copyright © 1999, Unitrode Corporation
BENCHMARQ® is a registered trademark, and AutoCompTM, Hot Swap Power Manager™ IC, Miller Kilier™,
Power GaugeTM, Power MinderTM, and UTRTM are trademarks of Unitrode Corporation.

Printed in U.S.A.
by Banta Book Group
Harrisonburg, Virginia

iv

-

(1[]

Introduction

Product Production Status

First Production

v

This document contains the design specifications for product under development.
Specifications may be changed in any manner
Supplementary data may be published at a
later date. Unitrode reserves the right to
make changes at any time without notice, in
order to improve design and supply the best

[1JJ UNITRODE

vi

Table of Contents
Using Unitrode Data Books ............................................. i
Unitrode Products ..................................................... ii
Product Production Status .............................................. v

-QJ]

1

Indices

Master Part Number Index .............................................. 1-1
Master Application Note Index by Part Number .............................. 1-19
Master Application Note Index by Publication Number......................... 1-24
Master Application Note Index by Subject .................................. 1-28

General Information

2

Ordering Information ................................................... 2-1
Quality .............................................................. 2-2
Die and Wafer. ....................................................... 2-9
New Products ........................................................ 2-10

3

SCSI

SCSI Selection Guides ............................................... 3-1
UCC5510 Low Voltage Differential (LVD/SE) SCSI 9 Line Terminator ........... 3-5
UC5601 SCSI Active Terminator ........................................ 3-9
UC5602 SCSI Active Terminator ........................................ 3-13
UC5603 9-Line SCSI Active Terminator ................................... 3-18
UC5604 9-Line Low Capacitance SCSI Active Terminator .................... 3-22
UC5605 9-Line Low Capacitance SCSI Active Terminator .................... 3-26
UCC5606 9-Line 3-5 Volt SCSI Active Terminator, Reverse Disconnect .......... 3-30
UC5607 Plug and Play, 18-Line SCSI Active Terminator ...................... 3-34
UC5608 18-Line Low Capacitance SCSI Active Terminator ................... 3-37
UC5609 18-Line Low Capacitance SCSI Active Terminator ................... 3-40
UC5612 9-Line Low Capacitance SCSI Active Terminator .................... 3-43
UC5613 9-Line Low Capacitance SCSI Active Terminator .................... 3-47
UCC5614 9-Line 3-5 Volt Low Capacitance SCSI Active Terminator ............ 3-51
UCC5617 18-Line SCSI Terminator (Reverse Disconnect) .................... 3-55
UCC5618 18-Line SCSI Terminator ...................................... 3-59
UCC5619 27-Line SCSI Terminator With Reverse Disconnect ................. 3-63
UCC5620 27-Line SCSI Terminator ...................................... 3-66
UCC5621 27-Line SCSI Terminator With Split Reverse Disconnect ............. 3-70
UCC5622 27-Line SCSI Terminator With Split Disconnect .................... 3-74
UCC5628 Multimode SCSI 14 Line Terminator ............................. 3-78
UCC5630 Low Voltage Differential (LVD/SE) SCSI 9 Line Terminator ........... 3-83
UCC5630A Multimode SCSI 9 Line Terminator ............................. 3-87
UCC5632 Multimode (LVD/SE) SCSI 9 Line Terminator
wi 2.85V Regulator ................................................. 3-93
UCC5638 Multimode SCSI 15 Line Terminator ............................. 3-94
UCC5639 Miltimode SCSI 15 Line Terminator with Reverse Disconnect ......... 3-99
UCC5640 Low Voltage Differential (LVD) SCSI 9 Line Terminator .............. 3-104
UCC5641 Low Voltage Differential (LVD/SE) SCSI 9 Line Terminator Reverse
Disconnect ....................................................... 3-108

vii

-

[1JJ

Table of Contents (cont.)

UCC5646 27-Line SCSI Terminator ...................................... 3-112
UC5661 Ethernet Coaxial Impedance Monitor .............................. 3-116
UCC5672 Multimode (LVD/SE) SCSI 9 Line Terminator ...................... 3-120
UCC5680 Low Voltage Differential (LVD) SCSI 9 Line Terminator ............... 3-121
DN- 92 UCC5630 SCSI Multimode (LVD/SE) Evaluation Board
and List of Materials ................................................ 3-122

Bus Bias Generators

4

Bus Bias Generators Selection Guides .................................... 4-1
UC560 27-Line SCSI Source/Sink Regulator ............................... 4-3
UC561 Low Voltage Differential SCSI (LVD) 27 Line Regulator Set .............. 4-7
UC563 32 Line VME Bus Bias Generator .................................. 4-10

Hot Swap Power Manager™ ICs

5

Hot Swap Power Manager Selection Guides
.............................. 5-1
UCC3831 Universal Serial Bus Power Controller ............................ 5-3
UCC38531 Universal Serial Bus Power Controller ....................... '.... 5-6
UCC3912 Programmable Hot Swap Power Manager ......................... 5-9
UCC3913 Negative Voltage Hot Swap Power Manager ....................... 5-15
UC3914 5V to 35V Hot Swap Power Manager .............................. 5-23
UCC3915 15V Programmable Hot Swap Power Manager ..................... 5-37
UCC39151 15V Programmable Hot Swap Power Manager .................... 5-42
UCC3916 SCSI Termpower Manager ..................................... 5-47
UCC39161 Low Current Hot Swap Power Manager .......................... 5-50
UCC3917 Positive Floating Hot Swap Power Manager ....................... 5-53
UCC3918 Low On Resistance Hot Swap Power Manager ..................... 5-61
UCC3919 3V to 8V Hot Swap Power Manager .............................. 5-68
UCC3921 Latchable Negative Floating Hot Swap Power Manager .............. 5-78
UCC3981 Universal Serial Bus Hot Swap Power Controller .................... 5-88
UCC39811 Universal Serjal Bus Hot Swap Power Controller ................... 5-91
UCC3985 Programmable CompactPCI Hot Swap Power Manager .............. 5-94
UCC3995 Simple Single Channel External N-FET Hot Swap Manager ........... 5-98
UCC3996 Dual Sequencing Hot Swap Power Manager ......•................ 5-100
DN- 58 UCC3912 Programmable Hot Swap Power Manager Performance Evaluation and Programming Information ..................... 5-102
DN- 67 UCC3913 Hot Swap Pow~r Manager for Negative Voltage Applications
Evaluation Kit List of Materials for a -48V11 A Test Circuit .................... 5-105
DN- 68 UCC3831 USB Power Controller IC, Evaluation Board ...,.
Schematic and List of Materials ....................... ................ 5-1 06
DN- 85 UCC3831 USB Power Controller IC, Evaluation Board Schematic and List of Materials .......... ;............ ................ 5-11 0
DN- 87 UCC3918 Low On-Resistance Hot Swap Power Manager Performance
Evaluation Kit - Schematic and List of Materials .......................... 5-113
DN- 95 UCC3919 Hot Swap Power Manager Evaluation Board
and Bill of Materials ................................................ 5-116

viii

-

[1JJ

Table of Contents (cont.)

DN- 98 UCC3917 Positive Floating Hot Swap Power Manager Evaluation Kit,
Schematic and Bill of Materials ........................................ 5-120
U- 151 UCC3912 Integrated Hot Swap Power Manager IC for Hot-Swap and
Power Management Applications ...................................... 5-124

Drivers/Receiver Transceivers

6

Drivers/Receiver Transceivers Selection Guides ............................. 6-1
UC5170C Octal Line Driver ............................................. 6-3
UC5171 Octal Line Driver ............................................... 6-7
UC5172 Octal Line Driver. . . . . . . . . . . . . .................................. 6-11
UC5180C Octal Line Receiver ........................................... 6-15
UC5181C Octal Line Receiver ........................................... 6-18
UC5350 CAN Transceiver .............................................. 6-21
UC5351 CAN Transceiver with Voltage Regulator ............................ 6-27

Unitrode Product Portfolio

7

Interface Product Selection Guides ....................................... 7-1
Nonvolatile and Real Time Clock Product Selection Guides .................... 7-9
Portable Product Selection Guides ........................................ 7-7
Power Supply Control Product Selection Guides ............................. 7-25

Military/Aerospace Products

8

Capabilities .......................................................... 8-1
Standardized Military Drawings .......................................... 8-2

Packaging Information

9

Recommended Profile Limits ............................................ 9-3
Device Temp Management. ............................................. 9-5
Package Thermal Resistance Data ....................................... 9-9
Typical Materials Used for Assembly ...................................... 9-14
Thermal Characteristics of Surface Mount Packages .......................... 9-15
Package Diagrams .................................................... 9-19

ix

Master Part Number and Application Indices
General Information

SCSI
Bus Bias Generators

Hot Swap Power ManagerTM ICs
DriverslReceivers Transceivers

e Product Portfolio
rospace Products
Packaging Information

-

[1JJ

Numeric Master Part Index
Part No. Description

Volume/Page

UC1517 Stepper Motor Drive Circuit. ...................................... PS/8-30
UC1524 Advanced Regulating Pulse Width Modulators ........................ PS/3-43
UC1524A Advanced Regulating Pulse Width Modulators ....................... PS/3-48
UC1525A Regulating Pulse Width Modulators ............................... PS/3-54
UC1525B Regulating Pulse Width Modulators ............................... PS/3-61
UC1526 Regulating Pulse Width Modulator ................................. PS/3-68
UC1526A Regulating Pulse Width Modulator ................................ PS/3-75
UC1527A Regulating Pulse Width Modulators ............................... PS/3-54
UC1527B Regulating Pulse Width Modulators ............................... PS/3-61
UC1543 Power Supply Supervisory Circuit. ................................. PSI7-5
UC1544 Power Supply Supervisory Circuit. ................................. PS/7-5
UC1548 Primary Side PWM Controller ..................................... PS/3-83
UCC1570 Low Power Pulse Width Modulator. ............................... PS/3-91
UCC15701 Advanced Voltage Mode Pulse Width Modulator .................... PS/3-99
UC1572 Negative Output Flyback Pulse Width Modulator ...................... PS/3-108
UC1573 Buck Pulse Width Modulator Stepdown Voltage Regulator .............. PS/3-112
UCC1580-1 Single Ended Active Clamp/Reset PWM .......................... PS/3-122
UCC1580-2 Single Ended Active Clamp/Reset PWM .......................... PS/3-122
UCC1580-3 Single Ended Active Clamp/Reset PWM .......................... PS/3-122
UCC1580-4 Single Ended Active Clamp/Reset PWM .......................... PS/3-122
UCC1581 Micropower Voltage Mode PWM ................................. PS/3-131
UCC1583 Switch Mode Secondary Side Post Regulator ....................... PS/3-139
UC1584 Secondary Side Synchronous Post Regulator ........................ PS/3-148
UCC1585 Low Voltage Synchronous Buck Controller ......................... PS/3-154
UCC1588 5-Bit Programmable Output BiCMOS Power Supply Controller .......... PS/3-163
UC1610 Dual Schottky Diode Bridge ...................................... PSI7-10
UC1611 Quad Schottky Diode Array ....................................... PS/7-12
UC1612 Dual Schottky Diode ............................................ PSI7-15
UC1625 Brushless DC Motor Controller .................................... PS/8-37
UC1633 Phase Locked Frequency Controller ................................ PS/8-63
UC1634 Phase Locked Frequency Controller. ............................... PS/8-70
UC1635 Phase Locked Frequency Controller ................................ PS/8-74
UC1637 Switched Mode Controller for DC Motor Drive ........................ PS/8-78
UC1638 Advanced PWM Motor Controller .................................. PS/8-84
UC1702 Quad PWM Relay Driver. ........................................ PS/6-12
UC1705 High Speed Power Driver ........................................ PS/6-16
UC1706 Dual Output Driver ............................................. PS/6-19
UC1707 Dual Channel Power Driver ....................................... PS/6-24
UC1708 Dual Non-Inverting Power Driver................................... PS/6-31
UC1709 Dual High-Speed FET Driver ..................................... PS/6-35
UC1710 High Current FET Driver ......................................... PS/6-38
UC1711 Dual Ultra High-Speed FET Driver ................................. PS/6-41
UC17131 Smart Power Switch ........................................... PS/9-13
UC17132 Smart Power Switch ........................................... PS/9-13
UC17133 Smart Power Switch ........................................... PS/9-13
Part numbers are listed numerically, not by prefix (bq, Oil, Ell, VC, VCC).
Products included in this book are listed in bold.

1-1

-

Numeric Master Part Index
Part No. Description

VolumeJPage

UC1714 Complementary Switch FET Drivers ................................ PS/6-43
UC1715 Complementary Switch FET Drivers .......................•........ PS/6-43
UC1717 Stepper Motor Drive Circuit. ...................................... PS/8-92
UC1724 Isolated Drive Transmitter ........................................ PS/6 50
UC1725 Isolated High Side FET Driver .................................... PS/6-53
UC1726 Isolated Drive Transmitter ........................................ PS/6-57
UC1727 Isolated High Side IGST Driver .................................... PS/6-62
UC1730 Thermal Monitor ............................................... PSI7-17
UCC17423 Dual 3A MOSFET Driver ...................................... PS/6-68
UCC17424 Dual3A MOSFET Driver ....................................... PS/6-68
UCC17425 Dual3A MOSFET Driver ...................................... PS/6-68
UCC17523 Dual3A MOSFET Driver With Adaptive LES ....................... PS/6-73
UCC17524 Dual3A MOSFET Driver With Adaptive LES ....................... PS/6-73
UCC17525 Dual 3A MOSFET Driver With Adaptive LES ........................ PS/6-73
UCC1776 Quad FET Driver ............................................. PS/6-79
UCC1800 Low-Power SiCMOS Current-Mode PWM ........ " ................ PS/3-173
UCC1801 Low-Power SiCMOS Current-Mode PWM .......................... PS/3-173
UCC1802 Low-Power SiCMOS Current-Mode PWM .......................... PS/3-173
UCC1803 Low-Power SiCMOS Current-Mode PWM ..... , .. , ....... ; ......... PS/3-173
UCC1804 Low-Power SiCMOS Current-Mode PWM .......................... PS/3-173
UCC1805 Low-Power SiCMOS Current-Mode PWM ..................... ;' .... PS/3-173
UCC1806 Low Power, Dual Output, Current Mode PWM Controller•.............. PS/3-180
UCC1807-1 Programmable Maximum Duty CyclePWM Controller ............... PS/3-187
UCC1807-2 Programmable Maximum Duty Cycle PWM Controller ............... PS/3~187
UCC1807-3 Programmable Maximum Duty CyclePWM Controller •.............. PS/3-187
UCC1808-1 Low Power Current Mode Push-Pull PWM .............. ; ......... PS/3-192
UCC1808-2 Low Power Current Mode Push-Pull PWM ...•.................... PS/3-192
UCC1809-1 Economy Primary Side Controller. .............................. PS/3-198
UCC1809-2 Economy Primary Side Controller. .............................. PS/3-198
UCC1810 Dual Channel Synchronized Current Mode PWM ................... , PS/3-205
UCC1817 SiCMOS Power Factor Preregulator. .............................. PS/4-5
UCC1818 SiCMOS Power Factor Preregulator ............................... PS/4-5
UC182-1 Fast LDO Linear Regulator ...................................... PS/5-5
UC182-2 Fast LDO Linear Regulator ...................................... PS/5-5
UC1823 High Speed PWM Controller ...................................... PS/3-219
UC1823A High Speed PWM Controller .................................... PS/3-225
UC1823S High Speed PWM Controller .................................... PS/3-225
UC182-3 Fast LDO Linear Regulator ...................................... PS/5-5
UC1824 High Speed PWM Controller. ..................................... PS/3-233
UC1825 High Speed PWM Controller ...................................... PS/3-240
UC1825A High Speed PWM Controller .................................... PS/3-225
UC1825S High Speed PWM Controller .................................... PS/3-225
UC1826 Secondary Side Average Current Mode Controller ..................... PS/3-247
UC1827-1 Suck CurrenWoltage Fed Push-Pull PWM Controllers ................ PS/3-257
UC1827-2 Buck CurrenWoltage Fed Push-Pull PWM Controllers ................ PS/3-257
J

Part numbers are listed numerically, not by prefix (bq, DII, Ell, VC, VCC).
Products included in this book are listed in bold.

1-2

[1d]

Numeric Master Part Index
Part No. Description

VolumelPage

UC182-ADJ Fast LOa Linear Regulator .................................... PS/5-5
UC1832 High Speed PWM Controller ...................................... PS/5-11
UC1833 Precision Low Dropout Linear Controller ............................ PS/5-11
UC1834 High Efficiency Linear Regulator ................................... PS/5-18
UC1835 High Efficiency Regulator Controller ................................ PS/5-24
UC1836 High Efficiency Regulator Controller ................................ PS/5-24
UCC1837 8-Pin N-FET Linear Regulator Controller ........................... PS/5-28
UC1838A Magnetic Amplifier Controller .................................... PS/3-272
UCC1839 Secondary Side Average Current Mode Controller ................... PS/3-276
UC1841 Programmable, Off-Line, PWM Controller ........................... PS/3-281
UC1842 Current Mode PWM Controller .................................... PS/3-289
UC1842A Current Mode PWM Controller ................................... PS/3-296
UC1843 Current Mode PWM Controller .................................... PS/3-289
UC1843A Current Mode PWM Controller ................................... PS/3-296
UC1844 Current Mode PWM Controller .................................... PS/3-289
UC1844A Current Mode PWM Controller ................................... PS/3-296
UC1845 Current Mode PWM Controller .................................... PS/3-289
UC1845A Current Mode PWM Controller ................................... PS/3-296
UC1846 Current Mode PWM Controller .................................... PS/3-302
UC1847 Current Mode PWM Controller .................................... PS/3-302
UC1848 Average Current Mode PWM Controller ............................. PS/3-309
UC1849 Secondary Side Average Current Mode Controller. .................... PS/3-317
UCC18500 Combined PFC/PWM Controller ................................ PS/4-15
UCC18501 Combined PFC/PWM Controller ................................ PS/4-15
UCC18502 Combined PFC/PWM Controller ................................ PS/4-15
UCC18503 Combined PFC/PWM Controller ................................ PS/4-15
UC1851 Programmable, Off-Line, PWM Controller ........................... PS/3-327
UC185-1 Fast LDO Linear Regulator . .................................... IF/5-35
UC1852 High Power-Factor Preregulator ................................... PS/4-22
UC185-2 Fast LDO Linear Regulator . .................................... IF/5-35
UC1853 High Power Factor Preregulator ................................... PS/4-27
UC185-3 Fast LDO Linear Regulator . .................................... IF/5-35
UC1854 High Power Factor Preregulator ................................... PS/4-32
UC1854A Enhanced High Power Factor Preregulator ......................... PS/4-42
UC1854B Enhanced High Power Factor Preregulator ......................... PS/4-42
UC1855A High Performance Power Factor Preregulator ....................... PS/4-48
UC1855B High Performance Power Factor Preregulator ....................... PS/4-48
UC1856 Improved Current Mode PWM Controller ............................ PS/3-333
UCC1857 Isolated Boost PFC Preregulator Controller ......................... PS/4-56
UCC1858 High Efficiency, High Power Factor Preregulator ..................... PS/4-65
UC185-ADJ Fast LDO Linear Regulator .................................. IF/S-35
UC1860 Resonant Mode Power Supply Controller ............................ PS/3-341
UC1861 Resonant-Mode Power Supply Controllers ........................... PS/3-349
UC1862 Resonant-Mode Power Supply Controllers ........................... PS/3-349
Part numbers are listed numerically, not by prefix (bq, DV, EV, VC, VCC).
Products included in this book are listed in bold.

1-3

-Ddl

Numeric Master Part Index
Part No. Description

Volume/Page

UC1863 Resonant-Mode Power Supply Controllers ........................... PS/3-349
UC1864 Resonant-Mode Power Supply Controllers ........................... PS/3-349
UC1865 Resonant-Mode Power Supply Controllers ...................... '...... PS/3-349
UC1866 Resonant-Mode Power Supply Controllers ........................... PS/3-349
UC1867 Resonant-Mode Power Supply Controllers ........................... PS/3-349
UC1868 Resonant-Mode Power Supply Controllers ........................... PS/3-349
UC1871 Resonant Fluorescent Lamp Driver ................................ PP/8-2
UC1872 Resonant Lamp Ballast Controller ................................. PP/8-8
UC1875 Phase Shift Resonant Controller................................... PS/3-357
UC1876 Phase Shift Resonant Controller. .................................. PS/3-357
UC1877 Phase Shift Resonant Controller. .................................. PS/3-357
UC1878 Phase Shift Resonant Controller................................... PS/3-357
UC1879 Phase Shift Resonant Controller ................................... PS/3-367
UCC1884 Frequency Foldback Current Mode PWM Controller .................. PS/3-393
UC1886 Average Current Mode PWM Controller IC ........................... PS/3-400
UCC1888 Off-line Power Supply Controller ................................. PS/3-407
UCC1889 Off-line Power Supply Controller ................................. PS/3-412
UCC1890 Off-Line Battery Charger Circuit. ................................. PS/3-418
UCC1895 BiCMOS Advanced Phase Shift PWM Controller ..................... PS/3-425
UC1901 Isolated Feedback Generator ..................................... PS/7-21
UC1902 Load Share Controller ................. , ......................... PS/7-27
UC1903 Quad Supply and Line Monitor ........... : ........................ PS/7-32
UC1904 Precision Quad Supply and Line Monitor ............................ PS/7-39
UC1907 Load Share Controller. .......................................... PS/7-44
UC1910 A-Bit DAC and Voltage Monitor .................................... PS/3-437
UCC1913 Negative Voltage Hot Swap Power Manager ..................•... IF/5-15
UC1914 5V to 35V Hot Swap Power Manager .....................•........ IF/5-23
UCC1919 3V to SV Hot Swap Power Manager ............................. IF/5-6S
UCC1921 Latchable Negative Floating Hot Swap Power Manager ............. IF/5-1S
UCC1926 ±20A Integrated Current Sensor ................................. PS/9-43
UCC19411 Low Power Synchronous Boost Converter ......................... PP/7-58
UCC19412 Low Power Synchronous Boost Converter ......................... PP/7.58
UCC19413 Low Power Synchronous Boost Converter ......................... PP/7-58
UC19431 Precision Adjustable Shunt Regulator ...........•................. PS/7-50
UC19432 Precision Analog Controller ..................................... PS/7-56
UCC1946 Microprocessor Supervisor with Watchdog Timer .................... PP/7-88
UCC1960 Primary-Side Startup Controller .................................. PS/3-442
UCC1961 Advanced Primary-Side Startup Controller ......................... PS/3-450
UC1965 Precision Reference with Low Offset Error Amplifier ................... PS/7-60
UCC1972 BiCMOS Cold Cathode Fluorescent Lamp Driver Controller ............ PP/8-13
bq2000 Programmable Multi-Chemistry Fast-Charge-Management IC ............ PP/3-7
DV2000S1 Multi-Chemistry Switching Charger Development System ............. PP/3-33
bq2000T Programmable Multi-Chemistry Fast-Charge Management IC ........... PP/3-20
bq2002/F Fast-Charge ICs .............................................. PP/3-35
Part numbers are listed numerically, not by prefix (bq, DV, EV, UC, UCC).
Products included in this book are listed in bold.

1-4

-

Numeric Master Part Index
Part No. Description

Volume/Page

bq2002C Fast-Charge IC ............................................... PP/3-43
bq2002DfT Fast-Charge ICs ............................................. PP/3-51
bq2002E/G Fast-Charge ICs ............................................. PP/3-61
DV2002L2fTL2 Fast-Charge Development Systems ........................... PP/3-70
bq2003 Fast-Charge IC ................................................. PP/3-73
DV2003L 1 Fast-Charge Development System ............................... PP/3-85
DV2003S1 Fast-Charge Development System ............................... PP/3-87
DV2003S2 Fast-Charge Development System ............................... PP/3-89
bq2004 Fast-Charge IC ................................................. PP/3-91
bq2004E1H Fast-Charge ICs ............................................. PP/3-105
DV2004L 1 Fast-Charge Development System ............................... PP/3-103
DV2004S1/ES1/HS1 Fast-Charge Development Systems ...................... PP/3-117
bq2005 Fast-Charge IC for Dual-Battery Packs .............................. PP/3-119
DV2005L 1 Fast-Charge Development System ............................... PP/3-131
DV2005S1 Fast-Charge Development System ............................... PP/3-134
bq2007 Fast-Charge IC ................................................. PP/3-137
DV2007S1 Fast-Charge Development System ............................... PP/3-151
bq2010 Gas Gauge IC .......................... : ...................... PP/4-3
EV2010 bq2010 Evaluation System ....................................... PP/4-21
bq2011 Gas Gauge IC for High Discharge Rates ............................. PP/4-24
EV2011 bq2011 Evaluation System ....................................... PP/4-42
bq2011 J Gas Gauge IC for High Discharge Rates ............................ PP/4-45
bq2011 K Gas Gauge IC for High Discharge Rates ............................ PP/4-63
bq2012 Gas Gauge with Slow-Charge Control ............................... PP/4-81
EV2012 bq2012 Evaluation System ....................................... PP/4-100
bq2013H Gas Gauge IC for Power-Assist Applications ........................ PP/4-103
bq2014 Gas Gauge IC with External Charge Control .......................... PP/4-123
EV2014 bq2014 Evaluation Board ........................................ PP/4-142
bq2014H Gas Gauge IC with External Charge Control. ........................ PP/4-149
EV2014x Gas-Gauge and Fast-Charge Evaluation System ..................... PP14-145
bq2018 Power Minder IC ................................................ PP14-170
bq2031 Lead-Acid Fast-Charge IC ........................................ PP/3-154
DV2031 S2 Lead-Acid Charger Development System .......................... PP/3-168
bq2040 Gas-Gauge IC with 5MBus Interface ................................ PP/4-185
bq2050 Li-Ion Power Gauge IC ........................................... PP/4-215
EV2050 Power Gauge Evaluation Board ................................... PP/4-234
bq2050H Low-Cost Li-Ion Power Gauge IC ................................. PP/4-237
bq2052 Gas Gauge IC for Lithium Primary Cells ............................. PP/4-259
bq2054 Li-Ion Fast-Charge IC ............................................ PP/3-170
DV2054S2 Li-Ion Charger Development System ............................. PP/3-184
bq2056fTN Low-Dropout Li-Ion Fast-Charge ICs ............................. PP/3-186
bq2058 Li-Ion Pack Supervisor for 3- and 4-Cell Packs ........................ PP/6-2
bq2058T Li-Ion Pack Supervisor for 2-Cell Packs ............................. PP/6-14
bq2060 SBS v1.1-Compliant Gas-Gauge IC ................................. PP/4-276
bq2092 Gas Gauge IC with 5MBus-Like Interface ............................ PP/4-314
Part numbers are listed numerically, not by prefix (bq, DII, Ell,
Products included in this book are listed in bold.

ue, Uee).

1-5

-

Numeric Master Part Index
Part No. Description

Volume/Page

bq2110 NiCd or NiMH Gas Gauge Module .................................. PP/5-2
bq2111 L NiCd Gas Gauge Module with LEDs for High Discharge Rates ........... PP/5-8
bq2112 NiCd or NiMH Gas Gauge Module with Slow-Charge Control .............. PP/5-14
bq2113H Gas Gauge Module for Power Assist Applications .................... PP/5-20
bq2114 NiCd or NiMH Gas-Gauge Module with Charge-Control Output ........... PP/5-24
bq2118 Power Minder Mini-Board ......................................... PP/5-30
bq2145 Smart Battery Module with LEDs ................................... PP/5-34
bq2148 Smart Battery Module with LEDs and Pack Supervisor .................. PP/5-40
bq2150 Li-Ion Power Gauge Module ....................................... PP/5-47
bq2150H Li-Ion Power Gauge Module ..................................... PP/5-53
bq2158 3 or 4 Series Cell Li-Ion Pack Supervisor Module ...................... PP/5-57
bq2158T Two Series Cell Li-Ion Pack Supervisor Module ...................... PP/5-64
bq2164 NiCd or NiMH Gas Gauge Module with Fast-Charge Control ............. PP/5-71
bq2167 Li-Ion Power Gauge Module with Pack Supervisor ..................... PP/5-77
bq2168 Li-Ion Power Gauge Module with Pack Supervisor ..................... PP/5-85
bq219XL Smart Battery Module with LEDs .................................. PP/5-93
EV2200 EV2200 PC Interface Board for Gas Gauge Evaluation ................. PP/4-370
bq2201 Nonvolatile Controller (by one) .................................... NV/3-3
bq2202 SRAM Nonvolatile Controller with Reset. ............................ NV/3-11
bq2203A Nonvolatile Controller with Battery Monitor .......................... NV/3-19
bq2204A Nonvolatile Controller (by four) ................................... NV/3-27
UCC2305 HID Lamp Controller ........................................... PS/9-1
bq2502 Integrated Backup Unit .......................................... NV/3-35
UC2524 Advanced Regulating Pulse Width Modulators ........................ PS/3-43
UC2524A Advanced Regulating Pulse Width Modulators ....................... PS/3-48
UC2525A Regulating Pulse Width Modulators ............................... PS/3-54
UC2525B Regulating Pulse Width Modulators ............................... PS/3-61
UC2526 Regulating Pulse Width Modulator ................................. PS/3-68
UC2526A Regulating Pulse Width Modulator ................................ PS/3-75
UC2527A Regulating Pulse Width Modulators ............................... PS/3-54
UC2527B Regulating Pulse Width Modulators ............................... PS/3-61
UC2543 Power Supply Supervisory Circuit. ................................. PSI7-5
UC2544 Power Supply Supervisory Circuit. ................................. PSI7-5
UC2548 Primary Side PWM Controller ..................................... PS/3-83
UCC2570 Low Power Pulse Width Modulator ................•............... PS/3-91
UCC25701 Advanced Voltage Mode Pulse Width Modulator .................... PS/3-99
UC2572 Negative Output Flyback Pulse Width Modulator ...................... ·PS/3-108
UC2573 Buck Pulse Width Modulator Stepdown Voltage Regulator .............. PS/3-112
UC2577-12 Simple Step-Up Fixed Voltage Regulators ......................... PS/3-31
UC2577-13 Simple Step-Up Fixed Voltage Regulators ......................... PS/3-31
UC2577-14 Simple Step-Up Fixed Voltage Regulators ......................... PS/3-31
UC2577-15 Simple Step-Up Fixed Voltage Regulators ......................... PS/3-31
UC2577-ADJ Simple Step-Up Voltage Regulator ............................. PS/3-36
UC2578 Buck Pulse Width Modulator Stepdown Voltage Regulator .............. PS/3-116
UCC2580-1 Single Ended Active Clamp/Reset PWM .......................... PS/3-122
Part numbers are listed numerically, not by prefix (bq, DII, Ell, ue, Uee).
Products included in this book are listed in bold.

1-6

-

~

Numeric Master Part Index
Part No. Description

Volume/Page

UCC2580-2 Single Ended Active Clamp/Reset PWM .......................... PS/3-122
UCC2580-3 Single Ended Active Clamp/Reset PWM .......................... PS/3-122
UCC2580-4 Single Ended Active Clamp/Reset PWM .......................... PS/3-122
UCC2581 Micropower Voltage Mode PWM ................................. PS/3-131
UCC2583 Switch Mode Secondary Side Post Regulator ....................... PS/3-139
UC2584 Secondary Side Synchronous Post Regulator ........................ PS/3-14S
UCC2585 Low Voltage Synchronous Buck Controller ......................... PS/3-154
UCC2588 5-Bit Programmable Output BiCMOS Power Supply Controller .......... PS/3-163
UC2610 Dual Schottky Diode Bridge ...................................... PS/7-10
UC2625 Brushless DC Motor Controller .................................... PS/S-37
UCC2626 Brushless DC Motor Controller ................................... PS/8-50
UC2633 Phase Locked Frequency Controller ................................ PS/S-63
UC2634 Phase Locked Frequency Controller ................................ PS/S-70
UC2635 Phase Locked Frequency Controller ................................ PS/8-74
UC2637 Switched Mode Controller for DC Motor Drive ........................ PS/S-7S
UC2638 Advanced PWM Motor Controller .................................. PS/8-84
UC2702 Quad PWM Relay Driver. ...........................•............ PS/6-12
UC2705 High Speed Power Driver ........................................ PS/6-16
UC2706 Dual Output Driver ............................................. PS/6-19
UC2707 Dual Channel Power Driver ....................................... PS/6-24
UC2708 Dual Non-Inverting Power Driver. .................................. PS/6-31
UC2709 Dual High-Speed FET Driver ..................................... PS/6-35
UC2710 High Current FET Driver ......................................... PS/6-3S
UC2717 Stepper Motor Drive Circuit. ...................................... PS/S-92
UC27131 Smart Power Switch ........................................... PS/9-13
UC27132 Smart Power Switch ........................................... PS/9-13
UC27133 Smart Power Switch ........................................... PS/9-13
UC2714 Complementary Switch FET Drivers ................................ PS/6-43
UC3717 Stepper Motor Drive Circuit. ...................................... PS/S-92
UC3715 Complementary Switch FET Drivers ......................•......... PS/6-43
UC2724 Isolated Drive Transmitter ........................................ PS/6-50
UC2725 Isolated High Side FET Driver .................................... PS/6-53
UC2726 Isolated Drive Transmitter ........................................ PS/6-57
UC2727 Isolated High Side IGBT Driver .................................... PS/6-62
UC2730 Thermal Monitor ............................................... PS/7-17
UCC27423 Dual3A MOSFET Driver ...................................... PS/6-68
UCC27424 Dual3A MOSFET Driver ...................................... PS/6-68
UCC27425 Dual3A MOSFET Driver ...................................... PS/6-68
UCC2750 Source Ringer Controller ....................................... PS/9-22
UCC2751 Single Line Ring Generator Controller ............................. PS/9-32
UCC2752 Resonant Ring Generator Controller .............................. PS/9-38
UCC27523 Dual3A MOSFET Driver With Adaptive LEB ....................... PS/6-73
UCC27524 Dual3A MOSFET Driver With Adaptive LEB ....................... PS/6-73
UCC27525 Dual3A MOSFET Driver With Adaptive LEB ....................... PS/6-73
UCC2776 Quad FET Driver ............................................. PS/6-79
Part numbers are listed numerically, not by prefix (bq, DV, EV,
Products included in this book are listed in bold.

ue, Uee).

1-7

-

Numeric Master Part Index
Part No. Description

VolumeIPage

UCC2800 Low-Power BiCMOS Current-Mode PWM .......................... PS/3-173
UCC2801 Low-Power BiCMOS Current-Mode PWM ........................... PS/3-173
UCC2802 Low-Power BiCMOS Current-Mode PWM .......................... PS/3-173
UCC2803Low-Power BiCMOS Current-Mode PWM .................... , ..... PS/3-173
UCC2804 Low-Power BiCMOS Current-Mode PWM .......... ; ............... PS/3-173
UCC2805 Low-Power BiCMOS Current-Mode PWM .......................... PS/3-173
UCC2806 Low-Power BiCMOS Current-Mode PWM ......... :_ ................ PS/3-173
UCC2806 Low Power, Dual Output, Current Mode PWM Controller............... PS/3-180
UCC2807-1 Programmable Maximum Duty Cycle PWM Controller ............... PS/3-187
UCC2807-2 Programmable Maximum Duty Cycle PWM Controller ............... PS/3-187
UCC2807-3 Programmable Maximum Duty Cycle PWM Controller; .............. PS/3-187
UCC2808-1 Low Power Current Mode Push-Pull PWM ........................ PS/3-192
UCC2808-2 Low Power Current Mode Push-Pull PWM ........................ PS/3-192
UCC2809-1 Economy Primary Side Controller ............................... PS/3-198
UCC2809-2 Economy Primary Side Controller ............................... PS/3-198
UCC2810 Dual Channel Synchronized Current Mode PWM .................... PS/3-205
UCC281-3 Low Dropout 1 Ampere Linear Regulator Family .................... PPI7-5
UCC2813-0 Low Power Economy BiCMOS Current Mode PWM ................. PS/3-212
UCC2813-1 Low Power Economy BiCMOS Current Mode PWM ................. PS/3~212
UCC2813-2 Low Power Economy BiCMOS Current Mode PWM ................. PS/3-212
UCC2813-3 Low Power Economy BiCMOS Current Mode PWM ................. PS/3-212
UCC2813-4 Low Power Economy BiCMOS Current Mode PWM ................. PS/3-212
UCC2813-5 Low Power Economy BiCMOS Current Mode PWM ................. PS/3-212
UCC281-5 Low Dropout 1 Ampere Linear Regulator Family .................... PP/7-5
UCC2817 BiCMOS Power Factor Preregulator ....................•.......... PS/4-5
UCC2818 BiCMOS Power Factor Preregulator ............................... PS/4-5
UCC281-ADJ Low Dropout 1 Ampere Linear Regulator Family .................. PPI7-5
UC282-1 Fast LDO Linear Regulator ...................................... PS/5-5
UC282-2 Fast LDO Linear Regulator ...................................... PS/5-5
UC2823 High Speed PWM Controller ...................................... PS/3-219
UC282-3 Fast LDO Linear Regulator ...................................... PS/5-5
UC2823A High Speed PWM Controller .................................... PS/3-225
UC2823B High Speed PWM Controller .................................... PS/3-225
UC2824 High Speed PWM Controller ...................................... PS/3-233
UC2825 High Speed PWM Controller ...................................... PS/3-240
UC2825A High Speed PWM Controller .................................... PS/3-225
UC2825B High Speed PWM Controller .................................... PS/3-225
UC2826 Secondary Side Average Current Mode Controller ..................... PS/3-247
UC2827-1 Buck CurrenWoltage Fed Push-Pull PWM Controllers ................ PS/3-257
UC2827-2 Buck CurrenWoltage Fed Push-Pull PWM Controllers ................ PS/3-257
UC282-ADJ Fast LOO Linear Regulator .................................... PS/5-5
UC2832 Precision Low Dropout Linear Controllers ............................ PS/5-11
UC2833 Precision Low Dropout Linear Controllers ........................... PS/5-11
UCC283-3 Low Dropout 3 Ampere Linear Regulator Family .................... PPI7-12
UC2834 High Efficiency Linear Regulator ................................... PS/5-18
Part numbers are listed numerically, not by prefix (bq, 01/, EI/, VC, VCC).
Products included in this book are listed in bold.

1-8

-

Numeric Master Part Index
Part No. Description

VolumelPage

UC2835 High Efficiency Regulator Controller ................................ PS/5-24
UCC283-5 Low Dropout 3 Ampere Linear Regulator Family .................... PP/7-12
UC2836 High Efficiency Regulator Controller ................................ PS/5-24
UCC2837 8-Pin N-FET Linear Regulator Controller ........................... PS/5-28
UC2838A Magnetic Amplifier Controller .................................... PS/3-272
UCC2839 Secondary Side Average Current Mode Controller ................... PS/3-276
UCC283-ADJ Low Dropout 3 Ampere Linear Regulator Family, ................. PP/7-12
UC2841 Programmable, Off-Line, PWM Controller ........................... PS/3-281
UCC284-12 Low Dropout O.5A Negative Linear Regulator ...................... PP/7-19
UC2842 Current Mode PWM Controller .................................... PS/3-289
UC2842A Current Mode PWM Controller ................................... PS/3-296
UC2843 Current Mode PWM Controller .................................... PS/3-289
UC2843A Current Mode PWM Controller ................................... PS/3-296
UC2844 Current Mode PWM Controller .................................... PS/3-289
UC2844A Current Mode PWM Controller ................................... PS/3-296
UC2845 Current Mode PWM Controller .................................... PS/3-289
UCC284-5 Low Dropout O.5A Negative Linear Regulator ....................... PP/7-19
UC2845A Current Mode PWM Controller ................................... PS/3-296
UC2846 Current Mode PWM Controller .................................... PS/3-302
UC2847 Current Mode PWM Controller .................................... PS/3-302
UC2848 Average Current Mode PWM Controller ............................. PS/3-309
UC2849 Secondary Side Average Current Mode Controller..................... PS/3-317
UCC284·ADJ Low Dropout O.5A Negative Linear Regulator .................... PP/7-19
UCC28500 Combined PFC/PWM Controller ................................ PS/4-15
UCC28501 Combined PFC/PWM Controller ................................ PS/4-15
UCC28502 Combined PFC/PWM Controller ................................ PS/4-15
UCC28503 Combined PFC/PWM Controller ................................ PS/4-15
UC2851 Programmable, Off-Line, PWM Controller ........................•.. PS/3-327
UC285-1 Fast LDO Linear Regulator ....•................................ IF/5-35
UC2852 High Power-Factor Preregulator ................................... PS/4-22
UC285-2 Fast LDO Linear Regulator ....•................................ IF/5-35
UC2853 High Power Factor Preregulator ................................... PS/4-27
UC285~3Fast LDO Linear Regulator ......•.••........................... IF/5-35
UC2854 High Power Factor Preregulator ................................... PS/4-32
UC2854A Enhanced High Power Factor Preregulator ......................... PS/4-42
UC2854BEI'lhanced High Power Factor Preregulator ......................... PS/4-42
UC2855A High Performance Power Factor Pre regulator ....................... PS/4-48
UC2855B High Performance Power Factor Preregulator ........................ PS/4-48
UC2856 Improved Current Mode PWM Controller ............................ PS/3-333
UCC2857 Isolated Boost PFC Preregulator Controller ......................... PS/4-56
UCC2858 High Efficiency, High Power Factor Preregulator ..................... PS/4-65
UC285-ADJ Fast LDO Linear Regulator .................................. IF/5-35
UCC286 Low Dropout 200mA Linear Regulator .............................. PP/7-29
UC2860 Resonant Mode Power Supply Controller ............................ PS/3-341
Part numbers are listed numerically, not by prefix (bq, DV, EV,
Products included in this book are listed in bold.

ve, Vee).

1-9

G::O

Numeric Master Part Index
Part No. Description

VolumelPage

UC2861 . Resonant-Mode Power Supply Controllers ........................... PS/3-349
UC2862 Resonant-Mode Power Supply Controllers ........................... PS/3~349
UC2863 Resonant-Mode Power Supply Controllers ... : ....................... PS/3-349
UC2864 Resonant-Mode Power Supply Controllers ........................... PS/3-349
UC2865 Resonant-Mode Power Supply Controllers ........................... PS/3-349
UC2866 Resonant~Mode Power Supply Controllers............................ PS/3-349
UC2867 Resonant-Mode Power Supply Controllers ........................... PS/3-349
UC2868 Resonant-Mode Power Supply Controllers ............................ PS/3-349
UCC287 Low Dropout 200mA Linear Regulator .............................. ppn-29
UC2871 Resonant Fluorescent Lamp Driver ................................ PP/8-2
UC2872 Resonant Lamp Ballast Controller .............•................... PP/8-8
UC2875 Phase Shift Resonant Controller................................... PS/S-357
UC2876 Phase Shift Resonant Controller................................... PS/3-357
UC2877 Phase Shift Resonant Controller................................... PS/3-357··
UC2878 Phase Shift Resonant Controller.................. , ................ PS/3-357
UC2879 Phase Shift Resonant Controller................................... PS/3-367
UCC288 Low Dropout 200mA Linear Regulator .............................. ppn-29
UCC2880-4 Pentium@ Pro Controller ...................................... PS/3-373
UCC2880-5 Pentium® Pro Controller ...................................... PS/3-373
UCC2880-6 Pentium® Pro Controller ...................................... PS/3-373
UCC2882-1 Average Current Mode Synchronous Controller with 5-Bit DAC ........ PS/3-380
UCC2884 Frequency Foldback Current Mode PWM Controller .................. PS/3-393
UC2886 Average Current Mode PWM Controller IC ........................... PS/3-400
UCC2888 Off-line Power Supply Controller ................................. PS/3-407
UCC2889 Off-line Power Supply Controller ................................. PS/3-412
UCC2890 Off-Line Battery Charger Circuit. ................................. PS/3-418"
UCC2895 BiCMOS Advanced Phase Shift PWM Controller ..................... PS/3-425
UC2901 Isolated Feedback Generator ..................................... PSn-21
UC2902 Load Share Controller ........................................... PSn-27
bq2902 Rechargeable Alkaline Charge/Discharge Controller IC ................. PP/3-194
DV2902 Rechargeable Alkaline Development System ......................... PP/3-202
UC2903 Quad Supply and Line Monitor .................................... PSn-32
bq2903 Rechargeable Alkaline Charge/Discharge Controller IC· ................. PP/3-204·
EV2903 bq2903 Evaluation System ....................................... PP/3-214
UC2904 Precision Quad Supply and Line Monitor ............................ PSn-39
UC2906 Sealed Lead-Acid Battery Charger ................................. PP/3-237
UC2907 Load Share Controller ........................................... PSn-44
UC2909 Switchmode Lead-Acid Battery Charger ............................. PP/3-244
UC2910 4-Bit DAC and Voltage Monitor .................................... PS/3-437

UCC2913 Negative Voltage Hot Swap Power Manager •••••...•.••••...•.••• IFI5-15
UC2914 5V to 35V Hot Swap Power Manager ..•.••.•••••••.•.••.•••..••••• IFI5-23
UCC2915 15V Programmable Hot Swap Power Manager ••.........••.•••.•. IFI5-37
UCC2918 Low On Resistance Hot Swap Power Manager ••.•.......•..•.•... IFI5-61
UCC2919 3V to 8V Hot Swap Power Manager •.••••.•..•.••..••••••••••••• IF/5-68
Part numbers are listed numerically. not by prefix (bq, DII, Ell, UCi UCC).
Products included in this book are listed in bold.

1-10

-0dJ

Numeric Master Part Index
Part No. Description

VolumelPage

UCC2921 Latchable Negative Floating Hot Swap Power Manager ............. IF/5-78
UCC2926 ±20A Integrated Current Sensor ................................. PS/9-43
L293/D Push-Pull Four Channel Driver ..................................... PS/6-5
UCC29401 Advanced Low Voltage Boost Controller .......................... PP/7-34
UCC29411 Low Power Synchronous Boost Converter ......................... PP/7-58
UCC29412 Low Power Synchronous Boost Converter ......................... PP/7-58
UCC29413 Low Power Synchronous Boost Converter ......................... PP/7-58
UCC29421 High Power Synchronous Boost Controller ........................ PP/7-66
UCC29422 High Power Synchronous Boost Controller ........................ PP/7-66
UC29431 Precision Adjustable Shunt Regulator ............................. PS/7-50
UC29432 Precision Analog Controller ..................................... PS/7-56
bq2945 Gas Gauge IC with 5MBus-Like Interface ............................ PP/4-340
UCC2946 Microprocessor Supervisor with Watchdog Timer .................... PP/7-88
UC2950 Half-Bridge Bipolar Switch ....................................... PS/6-10
bq2954 Li-Ion Fast-Charge IC ............................................ PP/3-217
DV2954S1 H Li-Ion Charger Development System ............................ PP/3-235
DV2954S1 L Li-Ion Charger Development System ............................ PP/3-233
UCC2956 Switch Mode Lithium-Ion Battery Charger Controller .................. PP/3-253
UCC2960 Primary-Side Startup Controller .................................. PS/3-442
UCC2961 Advanced Primary-Side Startup Controller ......................... PS/3-450
UC2965 Precision Reference with Low Offset Error Amplifier ................... PS/7-60
UCC2972 BiCMOS Cold Cathode Fluorescent Lamp Driver Controller ............ PP/8-13
UC3173A Full Bridge Power Amplifier ..................................... PS/8-5
UC3175B Full Bridge Power Amplifier ..................................... PS/8-16
UC3176 Full Bridge Power Amplifier. ...................................... PS/8-21
UC3177 Full Bridge Power Amplifier ....................................... PS/8-21
UC3178 Full Bridge Power Amplifier ....................................... PS/8-25
bq3285 Real-Time Clock IC (RTC) ....................................... NV/4-3
bq3285E/L Real-Time Clock ICs (RTC) .................................... NV/4-22
bq3285EC/LC Real-Time Clock ICs (RTC) ................................. NV/4-46
bq3285ED/LD Real-Time Clock ICs (RTC) ................................. NV/4-69
bq3285LF ACPI-Compliant Real-Time Clock IC ............................. NV/4-92
bq3287Ibq3287A Real-Time Clock Module ................................ NV14-111
bq3287E1bq3287EA Real-Time Clock Module .............................. NV14-115
bq3287LD Real-Time Clock Module ...................................... NV14-119
UCC3305 HID Lamp Controller. .......................................... PS/9-5
UC3517 Stepper Motor Drive Circuit. ...................................... PS/8-30
UC3524 Advanced Regulating Pulse Width Modulators ........................ PS/3-43
UC3524A Advanced Regulating Pulse Width Modulators ....................... PS/3-48
UC3525A Regulating Pulse Width Modulators ............................... PS/3-54
UC3525B Regulating Pulse Width Modulators ............................... PS/3-61
UC3526 Regulating Pulse Width Modulator ................................. PS/3-68
UC3526A Regulating Pulse Width Modulator ................................ PS/3-75
UC3527A Regulating Pulse Width Modulators ............................... PS/3-54
UC3527B Regulating Pulse Width Modulators ............................... PS/3-61
Part numbers are listed numerically, not by prefix (bq, 011, Ell,
Products included in this book are listed in bold.

ve, Vee).

1-11

Qd]

Numeric Master Part Index
Part No; Description

Volume/Page

UC3543 Power Supply Supervisory Circuit ................. , .. !• • • • • • • • • • • • • • PSI7-5
UC3544 Power Supply Supervisory Circuit. ................................. PSI7-5
UC3548 -Primary Side PWM Controller ................... : ................. PS/3-83
UCC3570 Low Power Pulse Width Modulator ................................ PS/3-S1
UCC35701 Advanced Voltage Mode Pulse Width Modulator ... ; •............... PS/3~SS
UC3572 Negative Output Flyback Pulse Width Modulator ...................... PS/3-108
UC3573 Buck Pulse Width Modulator Stepdown Voltage Regulator .............. PS/3-112
UC3578 Buck Pulse Width Modulator Stepdown Voltage Regulator ........ "...... PS/3-116
UCC3580-1 Single Ended Active Clamp/Reset PWM ........•................. PS/3-122
UCC3580-2 Single Ended Active Clamp/Reset PWM .......................... PS/3-122
UCC3580-3 Single Ended Active Clamp/Reset PWM .......................... PS/3-122
UCC3580-4 Single Ended Active Clamp/Reset PWM .......................... PS/3-122
UCC3581 Micropower Voltage Mode PWM .........................•....... PS/3-131
UCC3583 Switch Mode Secondary Side Post Regulator ....................... PS/3-13S
UC3584 Secondary Side Synchronous Post Regulator ........................ PS/3-148
UCC3585 Low Voltage Synchronous Buck Controller ......................... PS/3-154
UCC3588 5-Bit Programmable Output BiCMOS Power Supply Controller .......... PS/3-163
UC3610 Dual Schottky Diode Bridge .... , ................................. PSI7-10
UC3611 Quad Schottky Diode Array ...................................... ; PSI7-12
UC3612 Dual Schottky Diode ............................................ PSI7-15
UC3625 Brushless DC Motor Controller .. : .' ................................ PS/8-37
UCC3626 Brushless DC Motor Controller............. , ..................... PS/8-50
UC3633 Phase Locked Frequency Controller ........................... • J • •• PS/8-63
UC3634 Phase Locked Frequency Controller .................. "............. .' PS/8-70
UC3635 Phase Locked Frequency Controller ................................ PS/8-74
UC3637 Switched Mode Controller for DC Motor Drive ........................ PS/8-78
UC3638 Advanced PWM Motor Controller .................................. PS/8-84
UC3702 Quad PWM Relay Driver ...................................... ~ .. PS/6-12
UC3705 High Speed Power Driver ........................................ PS/6-16
UC3706 Dual Output Driver ............................... , ............. PS/6-1S
UC3707 Dual Channel Power Driver ... , ............... '.................... PS/6.-24
UC3708 Dual Non-Inverting Power Driver................................... PS/6-31
UC370S Dual High-Speed FET Driver ........................ , ............ PS/6~35
UC3710 High Current FET Driver ..................... , ................... PS/6-38
UC3711 Dual Ultra High-Speed FET Driver ................................. PS/6-41
UC37131 Smart Power Switch ..............................•............ PS/S-13
UC37132 Smart Power Switch .......... "................................. PS/S-13
UC37133 Smart PowerSwitch ........................................... PS/S-13
UC3714 Complementary Switch FETDrivers ................................ PS/6-43
UC3715 Complementary Switch FET Drivers ................................ PS/6-43
UC3717 Stepper Motor Drive Circuit ....................................... PS/8-S2
UC3717A Stepper Motor Drive Circuit ..................................... PS/8-100
UC3724 Isolated Drive Transmitter ........................................ PS/6-50
UC3725 Isolated High Side FET Driver ........................ ; ........... PS/6-53
UC3726 Isolated Drive Transmitter ........................................ PS/6-57
Part numbers are listed numerically, not by prefix (bq, DII, Ell,
Products included in this book are listed in bold.

ve, Vee).

1-12

-

Numeric Master Part Index
Part No. Description

Volume/Page

UC3727 Isolated High Side IGBT Driver .................................... PS/6-62
UC3730 Thermal Monitor ............................................... PS/7-17
UCC37423 Dual3A MOSFET Driver ...................................... PS/6-68
UCC37424 Dual3A MOSFET Driver ...................................... PS/6-68
UCC37425 Dual3A MOSFET Driver ...................................... PS/6-68
UCC3750 Source Ringer Controller ....................................... PS/9-22
UCC3751 Single Line Ring Generator Controller ............................. PS/9-32
UCC3752 Resonant Ring Generator Controller .............................. PS/9-38
UCC37523 Dual 3A MOSFET Driver With Adaptive LEB ....................... PS/6-73
UCC37524 Dual3A MOSFET Driver With Adaptive LEB ....................... PS/6-73
UCC37525 Dual3A MOSFET Driver With Adaptive LEB ....................... PS/6-73
UC3770A High Performance Stepper Motor Drive Circuit ...................... PS/8-108
UC3770B High Performance Stepper Motor Drive Circuit ...................... PS/8-108
UCC3776 Quad FET Driver ............................................. PS/6-79
UCC3800 Low-Power BiCMOS Current-Mode PWM .......................... PS/3-173
UCC3801 Low-Power BiCMOS Current-Mode PWM .......................... PS/3-173
UCC3802 Low-Power BiCMOS Current-Mode PWM .......................... PS/3-173
UCC3803 Low-Power BiCMOS Current-Mode PWM .......................... PS/3-173
UCC3804 Low-Power BiCMOS Current-Mode PWM .......................... PS/3-173
UCC3805 Low-Power BiCMOS Current-Mode PWM .......................... PS/3-173
UCC3806 Low Power, Dual Output, Current Mode PWM Controller ............... PS/3-180
UCC3807-1 Programmable Maximum Duty Cycle PWM Controller ............... PS/3-187
UCC3807-2 Programmable Maximum Duty Cycle PWM Controller ............... PS/3-187
UCC3807-3 Programmable Maximum Duty Cycle PWM Controller ............... PS/3-187
UCC3808-1 Low Power Current Mode Push-Pull PWM ........................ PS/3-192
UCC3808-2 Low Power Current Mode Push-Pull PWM ........................ PS/3-192
UCC3809-1 Economy Primary Side Controller. .............................. PS/3-198
UCC3809-2 Economy Primary Side Controller. .............................. PS/3-198
UCC3810 Dual Channel Synchronized Current Mode PWM .................... PS/3-205
UCC381-3 Low Dropout 1 Ampere Linear Regulator Family .................... PP/7-5
UCC3813-0 Low Power Economy BiCMOS Current Mode PWM ................. PS/3-212
UCC3813-1 Low Power Economy BiCMOS Current Mode PWM ................. PS/3-212
UCC3813-2 Low Power Economy BiCMOS Current Mode PWM ................. PS/3-212
UCC3813-3 Low Power Economy BiCMOS Current Mode PWM ................. PS/3-212
UCC3813-4 Low Power Economy BiCMOS Current Mode PWM ................. PS/3-212
UCC3813-5 Low Power Economy BiCMOS Current Mode PWM ................. PS/3-212
UCC381-5 Low Dropout 1 Ampere Linear Regulator Family .................... PP/7-5
UCC3817 BiCMOS Power Factor Preregulator. .............................. PS/4-5
UCC3818 BiCMOS Power Factor Preregulator. .............................. PS/4-5
UCC381-ADJ Low Dropout 1 Ampere Linear Regulator Family .................. PP/7-5
UC382-1 Fast LDO Linear Regulator ...................................... PS/5-5
UC382-2 Fast LDO Linear Regulator ...................................... PS/5-5
UC3823 High Speed PWM Controller ...................................... PS/3-219
UC382-3 Fast LDO Linear Regulator ...................................... PS/5-5
UC3823A High Speed PWM Controller .................................... PS/3-225
Part numbers are listed numerically, not by prefix (bq, Ov, EV,
Products included in this book are listed in bold.

ue, Uee).

1-13

-

Numeric Master Part Index
Part No. Description

Volume/Page

UC3823B High Speed PWM Controller .................................... PS/3-225.
UC3824 High Speed PWM Controller ...................................... PS/3-233
UC3825 High Speed PWM Controller .........•............ '................ PS/3-240
UC3825A High Speed PWM Controller ............................... ~ .... PS/3-225
UC3825B High Speed PWM Controller .................................... PS/3~225
UC3826 Secondary Side Average Current Mode Controller............•........ PS/3-247
UC3827-1 Buck CurrenWoltage Fed Push-Pull PWM Controllers ................ PS/3-257
UC3827-2 Buck CurrenWoltage Fed Push-Pull PWM Controllers .......... ; ..... PS/3-257
UC382-ADJ Fast LDO Linear Regulator .................................. ; . PS/5~5
UCC3830-4 5-Bit Microprocessor Power Supply Controller ..................... PS/3-263
UCC3830-5 5-Bit Microprocessor Power Supply Controller ..................... PS/3-263
UCC3830-6 5-Bit Microprocessor Power Supply Controller ...." .. ; .............. PS/3-263

UCC3831 Universal Serial Bus Power Controller........•...•........••.... IF/5-3
UC3832 Precision Low Dropout Linear Controllers .......................... ; PS/5-n
UC3833 Precision Low Dropout Linear Controllers ........................... PS/5-11
UCC383-3 Low Dropout 3 Ampere Linear Regulator Family ........ : ........... PP17-12
UC3834 High Efficiency Linear Regulator................................... PS/5-18
UC3835 High Efficiency Regulator Controller ....................•........... PS/5-24
UCC383-5 Low Dropout 3 Ampere Linear Regulator Family .................... PPI7-12
UC3836 High Efficiency Regulator Controller ................................ PS/5-24
UCC3837 8-Pin N-FET Linear Regulator Controller ........................... PS/5-28
UC3838A Magnetic Amplifier Controller .............................•...... PS/3-272
UCC3839 Secondary Side Average Current Mode Controller ................... PS/3-276
UCC383-ADJ Low Dropout 3 Ampere Linear Regulator Family .................. PP17-12
UC3841 Programmable, Off-Line, PWM Controller ........................... PS/3-281
UCC384-12 Low Dropout O.5A Negative Linear Regulator...................... PPI7-19
UC3842 Current Mode PWM Controller .................................... PS/3-289
UC3842A Current Mode PWM Controller ................................... PS/3-296
UC3843 Current Mode PWM Controller .................................... PS/3-289
UC3843A Current Mode PWM Controller ................................... PS/3-296
UC3844 Current Mode PWM Controller .................................... PS/3-289
UC3844A Current Mode PWM Controller ..............•.................... PS/3-296
UC3845 Current Mode PWM Controller .................................... PS/3-289
UCC384-5 Low Dropout O.5A Negative Linear Regulator....................... PPI7-19
UC3845A Current Mode PWM Controller ................................... PS/3-296
UC3846 CUrrent Mode PWM Controller ... " ................................ PS/3-302
UC3847 Current Mode PWM Controller .............................' ....... PS/3-302
UC3848 Average Current Mode PWM Controller ............................. PS/3-309
UC3849 Secondary Side Average Current Mode Controller: .................•.. PS/3-317
UCC384-ADJ Low Dropout O.5A Negative Linear Regulator .................... PP17-19
UCC38500 Combined PFC/PWM Controller ...................... ; ....•.... PS/4-15
UCC38501 Combined PFC/PWM Controller ................................ PS/4-15
UCC38502 Combined PFC/PWM Controller ................................ PS/4-15
UCC38503 Combined PFC/PWM Controller ................................ PS/4-15
UC3851 Programmable, Off-Line, PWM Controller ........................... PS/3-327
Part numbers are listed numerically, not by prefix (bq, D\I, EV, UC, UCC).
Products included in this book are listed in bold.

1-14

-

Numeric Master Part Index
Part No. Description

Volume/Page

UC385-1 Fast LDO Linear Regulator . .................................... IF/5-35
UC3852 High Power-Factor Preregulator ................................... PS/4-22
UC385-2 Fast LDO Linear Regulator . .................................... IF/5-35
UC3853 High Power Factor Preregulator ................................... PS/4-27
UC385-3 Fast LDO Linear Regulator . .................................... IF/5-35
UCC38531 Universal Serial Bus Power Controller . ......................... IF/5-S
UC3854 High Power Factor Preregulator ................................... PS/4-32
UC3854A Enhanced High Power Factor Preregulator ......................... PS/4-42
UC3854B Enhanced High Power Factor Preregulator ......................... PS/4-42
UC3855A High Performance Power Factor Preregulator ....................... PS/4-48
UC3855B High Performance Power Factor Preregulator ....................... PS/4-48
UC3856 Improved Current Mode PWM Controller ............................ PS/3-333
UCC3857 Isolated Boost PFC Preregulator Controller ......................... PS/4-56
UCC3858 High Efficiency. High Power Factor Preregulator ..................... PS/4-65
UC385-ADJ Fast LDO Linear Regulator .................................. IF/5-35
UCC386 Low Dropout 200mA Linear Regulator .............................. PP/7-29
UC3860 Resonant Mode Power Supply Controller ............................ PS/3-341
UC3861 Resonant-Mode Power Supply Controllers ........................... PS/3-349
UC3862 Resonant-Mode Power Supply Controllers ........................... PS/3-349
- UC3863 Resonant-Mode Power Supply Controllers ........................... PS/3-349
UC3864 Resonant-Mode Power Supply Controllers ........................... PS/3-349
UC3865 Resonant-Mode Power Supply Controllers ........................... PS/3-349
UC3866 Resonant-Mode Power Supply Controllers ........................... PS/3-349
UC3867 Resonant-Mode Power Supply Controllers ........................... PS/3-349
UC3868 Resonant-Mode Power Supply Controllers ........................... PS/3-349
UCC387 Low Dropout 200mA Linear Regulator .............................. PP!7-29
UC3871 Resonant Fluorescent Lamp Driver ................................ PP/8-2
UC3872 Resonant Lamp Ballast Controller ................................. PP/8-8
UC3875 Phase Shift Resonant Controller ................................... PS/3-357
UC3876 Phase Shift Resonant Controller ................................... PS/3-357
UC3877 Phase Shift Resonant Controller. .................................. PS/3-357
UC3878 Phase Shift Resonant Controller. .................................. PS/3-357
UC3879 Phase Shift Resonant Controller. .................................. PS/3-367
UCC388 Low Dropout 200mA Linear Regulator .............................. PP!7-29
UCC3880-4 Pentium® Pro Controller ...................................... PS/3-373
UCC3880-5 Pentium® Pro Controller ...................................... PS/3-373
UCC3880-6 Pentium® Pro Controller ............................ ; ......... PS/3-373
UCC3882-1 Average Current Mode Synchronous Controller with 5-Bit DAC ........ PS/3-380
UCC3884 Frequency Foldback Current Mode PWM Controller .................. PS/3-393
UC3886 Average Current Mode PWM Controller IC ........................... PS/3-400
UCC3888 Off-line Power Supply Controller ................................. PS/3-407
UCC3889 Off-line Power Supply Controller ................................. PS/3-412
UCC3890 Off-Line Battery Charger Circuit. ................................. PS/3-418
UCC3895 BiCMOS Advanced Phase Shift PWM Controller ..................... PS/3-425
Part numbers are listed numerically, not by prefix (bq, Oil, Ell, UC, UCC).
Products included in this book are listed in bold.

1-15

-

QdJ

Numeric Master Part Index
Part No. Description

Volume/Page

UC3901 Isolated Feedback Generator ..................•.................. PS/7-21
UC3902 Load Share Controller .....•..................................... PS/7-27
UC3903 Quad Supply and Line Monitor ..................................... PS/7-32
UC3904 Precision Quad Supply and Line Monitor ........ , ................... PS/7-39
UC3906 Sealed Lead-Acid Battery Charger ................................. PP/3-237
UC3907 Load Share Controller ......................•.................... PS/7-44
UC3909 Switch mode Lead-Acid Battery Charger ............................. PP/3-244
UCC391 5-Bit Programmable Output BiCMOS Precision Voltage Reference ........ PS/3-434
UC3910 4-Bit DAC and Voltage Monitor .................................... PS/3-437
UCC3911 Lithium-Ion Battery Protector .................................... PP/6-26
UCC3912 Programmable Hot Swap Power Manager .••.••.•.••.••••••••••.• IF/S-9
UCC3913 Negative Voltage Hot Swap Power Manager •..•...•...•.•••••••.. IF/S-1S
UC3914 SV to 3SV Hot Swap Power Manager .............................. IF/S-23
UCC391S 1SV Programmable Hot Swap Power Manager •••.•..••.••.....•.. IF/S-37
UCC391S1 1SV Programmable Hot Swap Power Manager •••••••••••••.•.... IF/S-42
UCC3916 SCSI Termpower Manager ..................................... IF/S-47
UCC39161 Low Current Hot Swap Power Manager ••••••••••••••.••••••••.• IF/S-SO
UCC3917· Positive Floating Hot Swap Power Manager •••••••••••.••••••••.• IF/S-S3
UCC3918> Low On Resistance Hot Swap Power Manager ••••••.•.•••••..•..• IF/S-61
UCC3919 3V to 8V Hot Swap Power Manager ............................. IF/S-68
UCC3921 Latchable Negative Floating Hot Swap Power Manager ••.•••••••.•• IF/S-78
UCC3926 ±20A Integrated Current Sensor ................................. PS/9-4:3
UCC39401Advanced Low Voltage Boost Controller .......................... PP/7-34
UCC39411 Low Power Synchronous Boost Converter ......................... PP/7-58
UCC39412 Low Power Synchronous Boost Converter ......................... PP/7-58
UCC39413· Low Power Synchronous Boost Converter ...•..................... PP/7~58
UCC3941-31 V Synchronous Boost Converter ............................... PP/7-48
UCC3941-5 1V Synchronous Boost Converter ............................... PP/7-48
UCC3941-ADJ 1V Synchronous Boost Converter ............................ PP/7-48
UCC39421 High Power Synchronous Boost Controller ........................ PP/7-66
UCC39422 High Power Synchronous Boost Controller ........................ PP/7-66
UC39431 Precision Adjustable Shunt Regulator ............................. PS/7-50
UC39431 B Precision Adjustable Shunt Regulator ............................ PS/7-50
UC39432 Precision Analog Controller ..................................... PS/7-56
UC39432B Precision Analog Controller .................................... PS/7-56
UCC3946 Microprocessor Supervisor with Watchdog Timer .................... PP/7-88
UCC3952-1 Enhanced Single Cell Lithium-Ion Battery Protection IC .............. PP/6-32
UCC3952-2 Enhanced Single Cell Lithium~lon Battery Protection IC .............. PP/6-32
UCC3952-3 Enhanced Single Cell Lithium-Ion Battery Protection IC .............. PP/6-32
UCC3952~4 Enhanced Single Cell Lithium-Ion Battery Protection IC .............. PP/6-32
UCC3954 Single Cell Lithium-Ion to +3.3V Converter ......................... PP/7-93
UCC3956 Switch Mode Lithium-Ion Battery Charger Controller .................. PP/3-253
UCC3957-1Three - Four Cell Lithium-Ion Protector Circuit ..................... PP/6-37
UCC3957-2 Three - Four Cell Lithium-Ion Protector Circuit ..................... PP/6-37
Part numbers are listed numerically, not by prefix (bq, DV, EV, UC, UCC).
Products included in this book are listed in bold.

1-16

-

Numeric Master Part Index
Part No. Description

Volume/Page

UCC3957-3 Three - Four Cell Lithium-Ion Protector Circuit ..................... PP/6-37
UCC3957-4 Three - Four Cell Lithium-Ion Protector Circuit ..................... PP/6-37
UCC3958-1 Single Cell Lithium-Ion Battery Protection IC ...................... PP/6-44
UCC3958-2 Single Cell Lithium-Ion Battery Protection IC ...................... PP/6-44
UCC3958-3 Single Cell Lithium-Ion Battery Protection IC ...................... PP/6-44
UCC3958-4 Single Cell Lithium-Ion Battery Protection IC ...................... PP/6-44
UCC3960 Primary-Side Startup Controller .................................. PS/3-442
UCC3961 Advanced Primary-Side Startup Controller ......................... PS/3-450
UC3965 Precision Reference with Low Offset Error Amplifier ................... PSI7-60
UCC3972 BiCMOS Cold Cathode Fluorescent Lamp Driver Controller ............ PP/8-13
UCC3981 Universal Serial Bus Hot Swap Power Controller ••••....•.••••..•. IF/S-88
UCC39811 Universal Serial Bus Hot Swap Power Controller •......•••••...•. IF/S-91
UCC3985 Programmable CompactPCI Hot Swap Power Manager ....•........ IF/S-94
UCC399S Simple Single Channel External N-FET Hot Swap Power Manager .... IF/S-98
UCC399S Dual Sequencing Hot Swap Power Manager ...........•........•. IF/S-100
bq40101Y 8Kx8 Nonvolatile SRAM ........................................ NV/5-3
bq40111Y 32Kx8 Nonvolatile SRAM ....................................... NV/5-13
bq40131Y 128Kx8 Nonvolatile SRAM ...................................... NV/5-23
bq40141Y 256Kx8 Nonvolatile SRAM ...................................... NV/5-33
bq40151Y 512Kx8 Nonvolatile SRAM ...................................... NV/5-42
bq40161Y 1024Kx8 Nonvolatile SRAM ..................................... NV/5-52
bq40171Y 2048Kx8 Nonvolatile SRAM ..................................... NV/5-61
bq4285 Real-Time Clock Module with NVRAM Control. ....................... NV/4-123
bq4285E1L Enhanced RTC Module with NVRAM Control ...................... NV/4-143
bq4287 Real-Time Clock Module with NVRAM Control ........................ NV/4-168
bq43101Y 8Kx8 ZEROPOWER NonvolatileSRAM ............................ NV/5-70
bq4311Y/L 32Kx8 ZEROPOWER Nonvolatile SRAM .......................... NV/5-81
bq4802 Y2K-Compliant Parallel RTC with CPU Supervisor. .................... NV/4-174
bq4822Y RTC Module with 8Kx8 NVSRAM ................................. NV/4-176
bq4823Y TIMEKEEPER Module with 8Kx8 NVSRAM ......................... NV/4-191
bq4830Y RTC Module with 32Kx8 NVSRAM ................................ NV/4-205
bq4832Y RTC Module with 32Kx8 NVSRAM ................................ NV/4-218
bq4833Y TIMEKEEPER Module with 32Kx8 NVSRAM ........................ NV/4-233
bq4842Y RTC Module with 128Kx8 NVSRAM ............................... NV/4-247
bq48451Y Parallel RTC Module with CPU Supervisor ......................... NV/4-262
bq48471Y RTC Module with CPU Supervisor ............................... NV/4-279
bq4850Y RTC Module with 512Kx8 NVSRAM ............................... NV/4-282,
bq4852Y RTC Module with 512Kx8 NVSRAM ............................... NV/4-295
UC494A1ACAdvanced Regulating Pulse Width Modulators ..................... PS/3-460
UC495A1AC Advanced Regulating Pulse Width Modulators ..................... PS/3-460
UCS170A Octal Line Driver ••••........•.•••......••••••........•••..... IF/S-2
UC5171 Octal Line Driver ..............•............................... IF/S-S
UC5172 Octal Line Driver .......................•.......•..••....•..••• IF/6-10
UC5180C Octal Line Receiver ........................................•• IF/6-14
Part numbers are listed numerically, not by prefix (bq, Oil, Ell, VG, VGG).
Products included in this book are listed in bold.

1-17

-

~

Numeric Master Part Index
Part No. Description

Volume/Page

UC5181C Octal Line Receiver •...•••••••..•.•••••••....•••••••......••• IF/6~17
UCC5341 IrDA 2.4kbps to 115.2kbps Receiver ............................... PP/9·2
UCC5342 IrDA 2.4kbps to 115.2kbps Transceiver ............................ PP/9-6
UCC53431rDA Transceiver with Encoder/Decoder ............................ PP/9"10
UC5350 CAN Transceiver .....•..........•••.•....••••.....•.••••••••.. IF/6~20
UC5351 CAN Transceiver with Voltage Regulator ••.....•..•.......••••..•. IF/6~26
UCC5510 Low Voltage Differential (LVD/SE) SCSI 9 Line Terminator••••••••••• IF/3~5
UC560' 27~Line SCSI Source/Sink Regulator .••••..•••••••••••••••••••••.• IF/4~3
UC5601 SCSI Active Terminator •••.•.....•••••••••..•••.•••.••••.•••••• IF/3~9
UC5602 SCSI Active Terminator .••.••••.•....•••••••..•. ; •...••...••••• IF/3~13
UC5603 9~Line SCSI Active Terminator •••.•.....•••••...••••.•.••...••••• IF/3~18
UC5604 9~Line Low Capacitance SCSI Active Terminator ..••••••••••....•.• IF/3-22
UC5605 9~Line Low Capacitance SCSI Active Terminator ••......•.•••.•.... IF/3~26
UCC5606 9-Line 3-5 Volt SCSI Active Terminator, Reverse Disconnect ••...... IF/3~30
UC5607 Plug and Play, 18~Line SCSI Active Terminator ..•••.••••...•••••..• IF/3~34
UC5608 18~Line Low Capacitance SCSI Active Terminator •••••••••••••••••• IF/3~40
UC5609 18-Line Low Capacitance SCSI Active Terminator .•••••••••....•••• IF/3-40
UCC561 Low Voltage Differential SCSI (LVD) 27 Line Regulator Set •.........• IF/4-7
UC5612 9~Line Low Capacitance SCSI Active Terminator ..•••••••.•••••.••• IF/3~43
UC5613 9~Line Low Capacitance SCSI Active Terminator ..•••••••.•..•.••.• IF/3-47
UCC5614 9-Line 3-5 Volt Low Capacitance SCSI Active Terminator •••.• , ••••• IF/3-51
UCC5617 18-Line SCSI Terminator With Reverse Disconnect ••...•••.....••• IF/~-55
UCC5618 18-Line SCSI Terminator ........•••••••....•.••......••.•••.•• IF/3-59
UCC5619 27-Line SCSI Terminator With Reverse Disconnect .•...•••••...... IF/3-63
UCC5620 27-Line SCSI Terminator ........••••......••.......••.••...... IF/3-66
UCC5621 27-Line SCSI Terminator With Split Reverse Disconnect •••.•••••.•• IF/3-70
UCC5622 27-Line SCSI Terminator With Split Disconnect •.••••••••.•••••••• IF/3-74
UCC5628 Multimode SCSI 14 Line Terminator .........................•... IF/3-78
UCC563 32 Line VME Bus Bias Generator ., .•.••.••••..•••••••...••••••••• IF/4-10
UCC5630 Low Voltage Differential (LVD/SE) SCSI 9 Line Terminator•••••••••.• IF/3-83
UCC5630A Multimode SCSI 9 Line Terminator ..•••••••.••••.•••••.••••••• IF/3-87
UCC5632 Multimode (LVD/SE) SCSI 9 Line Terminator w/2.85V Regulator ••••• IF/3-93
UCC5638 Multimode SCSI 15 Line Terminator .....•••••...••.•••••...••••• IF/3-94
UCC5639 Miltimode SCSI 15 Line Terminator with Reverse Disconnect •...•..• IF/3-99
UCC5640 Low Voltage Differential (LVD) SCSI 9 Line Terminator .••••••.....• IF/3-104
UCC5641 Low Voltage Differential (LVD) SCSI 9 Line Terminator Reverse
Disconnect ..•.••••••••••••........•.••••...•..•••.•.•....••••• IF/3-108
UCC564627-Line SCSI Terminator ........••.•.....••..........••....... IF/3-112
UCC5647 27-Line SCSI Terminator •.•.....•••••••.•.••...••....•••.••••• IF/3-112
UC5661 Ethernet Coaxial Impedance Monitor ••••.•••.••••.•.•.•.•••••••.• IF/3-116
UCC5672 Multimode (LVD/SE) SCSI 9 Line Terminator .••..•••••••..•..••••• IF/3-120
UCC5680 Low Voltage Differential (LVD) SCSI 9 Line Terminator ...•.••.•••.. IF/3-121
UCC5950 10-Bit Serial D/A Converter ..................................... PS/9-48

Part numbers are listed numerically, not by prefix (bq, Oil, Ell, ue, UeG).
Products included in this book are listed in bold.

1-18

Application/Design Notes by Part Number

-

[1::JJ

IC Featured

Pub. Title

bq2000fT
bq2003
bq2003

U-504 Using the bq2000fT to Control Fast Charge ......................... PP/3-262
U-505 Using the bq2003 to Control Fast Charge .......................... PP/3-273
U-506 Step-Down Switching Current Regulation Using the bq2003 Fast-Charge
IC ............................................................... PP/3-291
U-507 Using the bq2005 to Control Fast Charge .......................... PP/3-309
U-508 Using the bq2007 Display Mode Options ........................... PP/3-327
U-509 Using the bq2007 Enhanced Features for Fast Charge ................ PP/3-332
U-514 Using the bq201 0: A Tutorial for Gas Gauging ....................... PP/4-390
U-510 Using the bq2031 to Charge Lead-Acid Batteries .................... PP/3-346
U-511 Switch-Mode Power Conversion Using the bq2031 ................... PP/3-360
U-513 Using the bq2040: Smart Battery System Gas Gauge IC .............. PP/4-372
DN-49 Easy Switcher Controls SEPIC Converter for Automotive Applications .... PP/3-487
U-512 Using the bq2902/3 Rechargeable Alkaline ICs ...................... PP/3-376
U-503 Using the bq3285/7E in a Green or Portable Environment ............. NV/4-331
DN-501 Using RAM Clear Function with bq3285/bq3287A RTCs ............. NV/4-321
DN-72 Lamp Ignitor Circuit ............................................ PS/9-52
U-161 Powering a 35W DC Metal Halide High Intensity Discharge (HID) Lamp
using the UCC3305 HID Lamp Controller ................................. PS/9-61
DN-36 UC1525B/1527B Devices - Comparison Summary to UC1525A11527A
Devices ........................................................... PS/3-470
U-150 Applying the UCC3570 Voltage-Mode PWM Controller to Both Off-Line
and DC/DC Converter Designs ........................................ PS/3-696
DN-62 Switching Power Supply Topology: Voltage Mode vs. Current Mode ...... PS/3-496
DN-70 UC3573 Buck Regulator PWM Control IC .......................... PS/3-508
U-167 UC3578 Telecom Buck Converter Evaluation Board .................. PS/3-818
DN-64 Inductorless Bias Supply for Synchronous Rectification and High Side
Drive Applications ..................... _ ............................ PS/3-502
DN-83 UC3584 DW Secondary Side Post Regulator, Evaluation Board,
Schematic, and List of Materials ....................................... PS/3-511
DN-50 Simple Techniques for Isolating and Correcting Common Application
Problems with UC3625 Brushless DC Motor Drives ........................ PS/8-111
U-115 New Integrated Circuit Produces Robust, Noise Immune System for
Brushless DC Motors ................................................ PS/8-155
U-130 Dedicated ICs Simplify Brushless DC Servo Amplifier Design ........... PS/8-166
U-113 Design Notes on Precision Phase Locked Speed Control for DC Motors .. PS/8-145
DN-53A Design Considerations for Synchronizing Multiple UC3637 PWMs ..... PS/8-115
U-102 UC1637/2637/3637 Switched Mode Controller for DC Motor Drive ....... PS/8-126
U-112 A High Precision PWM Transconductance Amplifier for Microstepping
using Unitrode's UC3637 ............................................. PS/8-137
DN-76 Closed Loop Temperature Regulation Using the UC3638 H-Bridge
Motor Controller and a Thermoelectric Cooler ............................. PS/8-118
U-120 A Simplified Approach to DC Motor Modeling for Dynamic Stability
Analysis .......................................................... PS/8-162
DN-35 IGBT Drive Using MOSFET Gate Drivers ........................... PS/6-85
U-111 Practical Considerations in Current Mode Power Supplies ............. PS/3-558
U-118 New Driver ICs Optimize High Speed Power MOSFET Switching
Characterisitics ...................................................... PS/6-92
U-137 Practical Considerations in High Performance MOSFET, IGBT & MCT
Gate Drive Circuits .................................................. PS/6-122
U-99 UC3717 and L-C Filter Reduce EMI and Chopping Losses in Step Motor .. PS/8-118

bq2005
bq2007
bq2007
bq2010
bq2031
bq2031
bq2040
UC2577
bq2902/3
bq3285/7E
bq3285/bq3287
UCC3305
UCC3305
UC3525A/27A
UCC3570
UCC35701
UC3573
UC3578
UCC3583
UC3584
UC3625
UC3625
UC3625
UC3634
UC3637
UC3637
UC3637
UC3638
UC3638
UC3708
UC3709
UC3709
UC3709
UC3717

VolumelPage

Part numbers are listed numerically, not by prefix (bq, Ov, EV, UG, VGG).
Publications included in this book are listed in bold.

1-19

Application/Design Notes by Part Number
IC Featured

Pub. Title

-

Volume/Page

UC3725
UC3726

U-127 Unique Chip Pair Simplifies High Side Switch Drive .................. PS/6-107
DN-57 Power Dissipation Considerations for the UC3726N/UC3727N IGBT
Driver Pair ......................................................... PS/6-87
UC3726
DN-60 UC3726/UC3727 IGBT Driver Pair Evaluation Kit Testing Procedure ...... PS/6-90
UC3727
U-143C New Chip Pair Provides Isolated Drive for High Voltage IGBTs ......... PS/6-137
DN-79 UCC3750 Demonstration Board Operating Guidelines ................. PS/9-55
UCC3750
UCC3750
U-169 The New UCC3750 Source Ringer Controller Provides A Complete
Control Solution for a Four-Quadrant Flyback Converter ...................... PS/9-76
DN-42A Design Considerations for Transitioning from UC3842 to the New
UCC3800/1-/5
UCC3802 Family ................................................... PS/3-476
UCC3800/1-/5
DN-43 Simple Techniques to Generate a Negative Voltage Bias Supply from
a Positive Input Voltage .............................................. PS/3-479
DN-56A Single Switch Flyback Circuit Converts +5VDC to +/-12VDC for
UCC3800/1-/5
RS-232 and RS-422 Applications ...................................... PS/3-492
UCC3800/1-/5
U-133A UCC3800/1/2/3/4/5 BiCMOS Current Mode ControllCs .............. PS/3-594
DN-45 UC3846, UC3856 and UCC3806 Push-Pull PWM Current Mode
UCC3806
Control ICs ......................................................... PS/3-480
DN-51 Programming the UCC3806 Features ............................. PS/3-489
UCC3806
U-144 UCC3806 BiCMOS Current Mode ControllC ..................... '.. PS/3-678
UCC3806
DN-48 Versatile Low Power SEPIC Converter Accepts Wide Input Voltage Range PS/3-484
UCC3807
DN~65 Considerations in Powering BiCMOS ICs .......................... PS/3-S05
UCC3809-1,-2
U-168 Implementing an Off-Line Lithium-Ion Charger Using the UCC3809
UCC3809-1,-2
Primary Side Controller and the UCC3956 Battery Charger Controller .......... PS/3-455
DN-46 Highly Efficient Low Power DC to DC Inverter Converts +5V Input to -3V
UCC3813
Output ........................................................... PS/3-482
DN-48 Versatile Low Power SEPIC Converter Accepts Wide Input Voltage Range PS/3-484
UCC3813
DN-54 Innovative Buck Regulator Uses High Side N-Channel Switch without
UCC3813
Complex Gate Drive ................................................. PS/3-492
U-97 Modeling, Analysis and Compensation of the Current Mode Converter .... PS/3-S26
UCC3813
U-128 The UC3823A,B & UC3825A,B Enhanced Generation of
UC3823A,B/
PWM Controllers .. , ........................•....................... PS/3-S85
UC3825A,B
U-110 1.5MHz Current Mode IC Controlled 50W Power Supply ............... PS/3-S46
UC3825
ON-8S UCC3831 USB Power Controller IC, Evaluation Board - Schematic and
UCC3831
List of Materials .....' ................................................ IF/5-106
DN-32 Optocoupler Feedback Drive Techniques ........................... PS/5-41
UC3832/3
DN-61 A High Performance Linear Regulator for Low Dropout Applications ...... PS/5-42
UC383213
U-152 A High Performance Linear Regulator for Low Dropout Applications ....... PS/5-71
UC383213
U-95 Versatile UC1834 Optimizes Linear Regulator Efficiency ................. PS/5-49
UC3834
DN-28 UC3840/UC3841/UC3851 PWM Controllers - Summary of Functional
UC3841
Differences ........................................................ PS/3-467
DN-27 UC1842/UC1842A Summary of Functional Differences ............... PS/3-466
UC3842/3/4/5
DN-40 The Effects of Oscillator Discharge Current Variations on Maximum Duty
UC3842/3/4/5
Cycle and Frequency in UC3842 and UC3842A PWM ICs ................... PS/3-473
DN-89 Comparing the UC3842, UCC3802, and UCC3809 Primary-Side PWM
UC3842/3/4/5
Controllers ... , .................................................... PS/3-514
UC384213/4/5
U-100A UC384213/4/5 Provides Low-Cost Current-Mode Control ............. PS/3-S32
UC3842A13A14A15A DN-26 UC3842A - .Low Cost Startup and Fault Protection Circuit ............. PS/3-464
UC3842A13A14A15A DN-29 UC3842A Family Frequency Foldback Technique Provides Protection .... PS/3-468
UC3842A13A14A15A DN-30 Programmable Electronic Circuit Breaker .......................... PS/3-469
UC384617
U-93 A New Integrated Circuit for Current Mode Control .................... PS/3-518
Part numbers are listed numerically, not by prefix (bq, Oil, £11, UC, UCC).
Publications included in this book are listed in bold.

1-20

Application/Design Notes by Part Number

-

Ie Featured

Pub. Title

UC3848

U-135 The UC3848 Average Current Mode Controller Squeezes Maximum
Performance from Single Switch Converters .............................. PS/3-612
U-140 Average Current Mode Control of Switching Power Supplies ............ PS/3-664
U-132 Power Factor Correction Using the UC3852 Controlled ON-Time Zero
Current Switching Technique ........................................... PS/4-98
DN-77 Overcurrent Shutdown with the UC3853 ............................ PS/4-91
DN-78 High Power Factor Preregulator IC, Evaluation Board, Schematic and
List of Materials ..................................................... PS/4-92
U-159 Boost Power Factor Corrector Design with the UC3853 ............... PS/4-154
DN-41 Extend Current Transformer Range ................................ PS/4-81
U-134 UC3854 Controlled Power Factor Correction Circuit Design ............ PS/4-114
DN-44 UC3854A and UC3854B Advanced Power Factor Correction Control ICs .. PS/4-83
DN-66 Unitrode - UC3854A1B and UC3855A1B Provide Power Limiting with
Sinusoidal Input Current for PFC Front Ends ............................... PS/4-86
U-153 UC3855A1B High Performance Power Factor Preregulator ............. PS/4-134
DN-45 UC3846, UC3856 and UCC3806 Push-Pull PWM Current Mode
Control ICs ........................................................ PS/3-480
DN-39E Optimizing Performance in UC3854 Power Factor Correction
Applications ........................................................ PS/4-76
DN-90 UCC3858 "Energy Star" PFC Evaluation Board, Schematic and List of
Materials ........................................................... PS/4-94
U-122 A New Family of Integrated Circuits Controls Resonant Mode Power
Converters ........................................................ PS/3-576
U-138 Zero Voltage Switching Resonant Power Conversion ................. PS/3-637
U-141 Resonant Fluorescent Lamp Converter Provides Efficient and Compact
Solution ........................................................... PP/8-27
U-148 Dimmable Cold-Cathode Fluorescent Lamp Bal.last Design Using the
UC3871 ........................................................... PP/8-35
DN-75 Using the UC3871 and UC3872 Resonant Fluorescent Lamp Drivers in
Floating Lamp Applications ............................................ PP/8-50
DN-63 The Current-Doubler Rectifier: An Alternative Rectification Technique for
Push-Pull and Bridge Converters ....................................... PS/3-499
U-136A Phase Shifted, Zero Voltage Transition Design Considerations and
the UC3875 PWM Controller .......................................... PS/3-623
U-154 The New UC3879 Phase Shifted PWM Controller Simplifies the Design
of Zero Voltage Transition Full-Bridge Converters .......................... PS/3-709
U-164 The UCC3884 Frequency Foldback Pulse Width Modulator ............ PS/3-783
U-156 The UC3886 PWM Controller Uses Average Current Mode Control to
Meet the Transient Regulation Performance of High End Processors ........... PS/3-717
U-157 Fueling the Megaprocessor - A DC/DC Converter Design Review
Featuring the UC3886 and UC3910 ..................................... PS/3-741
DN-59A UCC3889 Bias Supply Controller Evaluation Kit - Schematic and
Lists of Materials . , ................................................. PS/3-494
U-149A Simple Off-Line Bias Supply for Very Low Power Applications ......... PS/3-685
DN-19 A Simple Isolation Amplifier using the UC1901 ....................... PS/7-64
U-94 The UC1901 Simplifies the Problem of Isolated Feedback in Switching
Regulators ................................. '.' ..... '.' ............... PS/7-72
U-163 The UC3902 Load Share Controller and Its Performance in Distributed
Power Systems .................................................... PS/7-100
DN-33 Optocoupler Feedback Drive Techniques Using the UC3901 and UC3903 . PS/7-65

UC3849
UC3852
UC3853
UC3853
UC3853
UC3854
UC3854
UC3854A1B
UC3854A1B
UC3855A1B
UC3856
UCC3857
UCC3858
UC3861-8
UC3861-8
UC3871
UC3871
UC3872
UC3875/6/7/8
UC3875/6/7/8
UC3879
UCC3884
UC3886
UC3886
UCC3888
UCC3888
UC3901
UC3~01

UC3902
UC3903

Volume/Page

Part numbers are listed numerically, not by prefix (bq, DII, Ell,
Publications included in this book are listed in bold.

ue, Uee).

1-21

Application/Design Notes by Part Number

-Odl

Ie Featured

Pub. Title

UC3906
UC3906
UC3907
UC3909

U-104 Improved Charging Mettiods for Lead-Acid Batteries using the UC3906 ... PP/3-388
U-131 Simple Switch mode Lead-Acid Battery Charger ..................... PP/3-417
U-129 UC3907,Load Share IC Simplifies Parallels Power Supply Design ........ PSn-84
U-155 Implementing Multi-State Charge Algorithm with the UC3909
Switch mode Lead-Acid Battery Charger Controller ......................... PP/3-426
U-166 An Off-Line Lead-Acid Charger Based on the UC3909 ................ PP/3-399
U-158 The UC391 0 Combines Programmability, Accuracy and Integrated
Functions to Control and Monitor High End Processor Power Supplies ......... PS/3-771
DN-81 UCC3911 Demo Board Information ................................ PP/6-51
ON-58 UCC3912 Programmable Electronic Circuit Breaker - Performance
Evaluation and Programming Information ................................. IF/5-102
ON-68 Parelling UCC3912 Electronic Circuit Breaker Ics ..................... IF/5-106
U-151 UCC3912 Integrated Hot Swap Power Managerr IC for Hot-Swap and
Power Management Applications ....................................... IF/5-124
ON-67 UCC3913 Electronic Circuit Breaker for Negative Voltage Applications
Evaluation Kit List of Materials for a -48V11A Test Circuit ..................... IF/5-105
ON-98 UCC3917 Positive Floating Hot Swap Power Manager Evaluation Kit,
Schematic and Bill of Materials ......................................... IF/5-120
ON-87 UCC3918 Low On-Resistance Hot Swap Power Manager Performance
Evaluation Kit, Schematic and List of Materials ............................ IF/5-113
ON-95 UCC3919 Hot Swap Power Manager Evaluation Circuit Board and
Bill of Materials ..................................................... IF/5-116
DN-91 UCC3926DS ± 20A Integrated Current Sensor Evaluation Board Schematic and List 'of Materials. , ....................................... PS/9-58
DN-97 UCC39411 Low Power Synchronous Boost Converter Evaluation Kit,
Schematic and Bill of Materials ........................................ ppn-106
DN-73 UCC3941 One Volt Boost Converter Demonstration Kit - Schematic
and List of Materials ................................................. ppn-101
DN-52 Adjustable Electronic Load for Low Voltage DC Applications ............ PSn-76
DN-96 UCC3952 Evaluation Board and List of Materials ..................... PP/6-61
DN-86 UCC3954 Single Cell Lithium-Ion to +3.3V Converter Performance
Evaluation Kit - Schematic and List of Materials ........................... ppn-103
DN-84 UCC3956 Switch Mode Lithium-Ion Battery Charger Controller
Evaluation Board, Schematic and List of Materials .... ; .................... PP/3-413
DN-93 UCC3957,Three - Four Cell Lithium-Ion Protector Circuit, Evaluation
Board and List of Materials ............................................ PP/6-57
DN-82 UCC3958 Demonstration Board Schematic and Bill of Materials ......... PP/6-55
DN-99 Pulse Edge Transmission (PET) circuit ............................ PS/8-102
U-165 Design Review: Isolated 50W Flyback with the UCC3809 Primary
Side Controller and the UC3965 Precision Reference and Error Amplifier ....... PS/3-800
U-500 Using the bq4845 for a Low-Cost RTC/NVSRAM Subsystem ........... NVl4-310
DN-38 Unique Converter for Low Power Bias Supplies ..................... PS/3-471
DN-88 UCC5342 IrDA 115.2kbps Transceiver Performance Evaluation
Board - Schematic and List of Materials .................................. PP/9-15
DN-94 UCC5343, IrDA Transceiver with Encoder/Decoder, Evaluation
Board and List of Materials ............................................ PP/9-19
ON-92 UCC5630 SCSI Multimode (LVD/SE) Evaluation Board and List of
Materials .......................................................... IF/3-122
DN-502 High-Side Current Sensing with Benchmarq Portable Power
Fast-Charge ControllC .............................................. PP/3-307

UC3909
UC3910
UCC3911
UCC3912
UCC3912
UCC3912
UCC3913
UCC3917
UCC3918
UCC3919
UCC3926
UCC39411/2/3
UCC3941-3/5/ADJ
UC39432
UCC3952
UCC3954
UCC3956
UCC3957
UCC3958
UCC3961
UC3965
bq4845
UC494/5A&C
UCC5342
UCC5343
UCC5630
General

VolumelPage

Part numbers are listed numerically, not by prefix (bq, DII, Ell, UC, UCC).
Publications included in this book are listed in bold.

1-22

Application/Design Notes by Part Number

-0dJ

Ie Featured

. Pub. Title

General

U-502 Time-Base Oscillator for RTC ICs ................................ NV/4-322

VolumelPage

Part numbers are listed numerically, not by prefix (bq, 011, Ell, UC, UCC).
Publications included in this book are listed in bold.

1-23

Application/Design Notes by Publication Number

Ie Featured

-0dJ

Pub.

Title

DN·19
DN-26
DN-27
DN-28

A Simple Isolation Amplifier using the UC1901 ......•............... UC3901 ......... PSn-64
UC3842A - Low Cost Startup and Fault Protection Circuit ............. UC3842A13A14A15A PS/3-464
UC18421UC1842A Summary of Functional Differences ............... UC38421314/5 ..... PS/3-466
UC3840/UC3841/UC3851 PWM Controllers - Summary of Functional
Differences .................................................. UC3841 ......... PS/3-467
UC3842A Family Frequency Foldback Technique Provides Protection .... UC3842A13A14A15A PS/3-468
Programmable Electronic Circuit Breaker .......................... UC3842A13A14A15A PS/3-469
Optocoupler Feedback Drive Techniques .......................... UC383213 ........ PS/5-41
Optocoupler Feedback Drive Techniques Using the UC3901 and UC3903 UC3903 ......... PSn-65
IGBT Drive Using MOSFET Gate Drivers .......................... UC3708 ......... PS/6-85
UC1525B/1527B Devices - Comparison Summary to UC1525A11527A
Devices .................................................... UC3525A127A .... PS/3-470
Unique Converter for Low Power Bias Supplies ..................... UC494/5A&C ..... PS/3-471
Optimizing Performance in UC3854 Power Factor Correction Applications UCC3857 ........ PS/4-76
The Effects of Oscillator Discharge Current Variations on Maximum Duty
Cycle and Frequency in UC3842 and UC3842A PWM ICs ............. UC384213/4/5 ..... PS/3-473
Extend Current Transformer Range ............................... UC3854 ......... PS/4-81
Design Considerations for Transitioning from UC3842 to the New
UCC3802 Family ............................................. UCC3800/1/213/4/5 PS/3-476
Simple Techniques to Generate a Negative Voltage Bias Supply from a
Positive Input Voltage ......................................... UCC3800/1/21314/5 PS/3-479
UC3854A and UC3854B Advanced Power Factor Correction Control ICs . UC3854AIB ...... PS/4-83
UC3846, UC3856 and UCC3806 Push-Pull PWM Current Mode Control
ICs ........................................................ UCC3806 ........ PS/3-480
UC3846, UC3856 and UCC3806 Push-Pull PWM Current Mode
ControllCs .................................................. UC3856 ......... PS/3-480
Highly Efficient Low Power DC to DC Inverter Converts +5V Input to -3V
Output ..................................................... UCC3813 ........ PS/3-482
Versatile Low Power SEPIC Converter Accepts Wide Input Voltage
Range ..................................................... UCC3813 ........ PS/3-484
Easy Switcher Controls SEPIC Converter for Automotive Applications .... UC2577 ......... PS/3-487
Simple Techniques for Isolating and Correcting Common Application
Problems with UC3625 Brushless DC Motor Drives .................. UC3625 ......... PS/8-111
Programming the UCC3806 Features ............................. UCC3806 ........ PS/3-489
Adjustable Electronic Load for Low Voltage DC Applications ........... UC39432 ........ PSn-76
Design Considerations for Synchronizing Multiple UC3637 PWMs ....... UC3637 ......... PS/8-115
Innovative Buck Regulator Uses High Side N-Channel Switch without
Complex Gate Drive .......................................... UCC3813 ........ PS/3-492
Single Switch Flyback Circuit Converts +5VDC to +/-12VDC for RS-232
and RS-422 Applications ....................................... UCC3800/1/213/4/5 PS/3-492
Power Dissipation Considerations for the UC3726N/UC3727N IGBT
Driver Pair .................................................. UC3726 ......... PS/6-87
UCC3912 Programmable Electronic Circuit Breaker - Performance
Evaluation and Programming Information .......................... UCC3912 ........ IF/5-102
UCC3889 Bias Supply Controller Evaluation Kit - Schematic and List of
Materials ................................................... UCC3888 ........ PS/3-494
UC3726IUC3727 IGBT Driver Pair Evaluation Kit Testing Procedure ..... UC3726 ......... PS/6-90
A High Performance Linear Regulator for Low Dropout Applications ..... UC3832/3 ........ PS/5-42
Switching Power Supply Topology: Voltage Mode vs. Current Mode ...... UCC35701 ....... PS/3-496
The Current-Doubler Rectifier: An Alternative Rectification Technique for
Push-Pull and Bridge Converters ................................ UC3875/6nt8 ..... PS/3-499

DN-29
DN-30
DN-32
DN-33
DN-35
DN-36
DN-38
DN-39E
DN-40
DN-41
DN-42A
DN-43
DN-44
DN-45
DN-45
DN-46
DN-48
DN-49
DN-50
DN-51
DN-52
DN-53A
DN-54
DN-56A
DN-57
DN-58
DN-59A
DN-60
DN-61
DN-62
DN-63

Publications included in this book are listed in bold.

1-24

Volume/Page

Application/Design Notes by Publication Number
Title

DN·64

Inductorless Bias Supply for Synchronous Rectification and High Side
Drive Applications ............................................ UCC3583 ........
Considerations in Powering BiCMOS ICs .......................... UCC3809-1 ,-2 ....
Unitrode - UC3854NB and UC3855NB Provide Power Limiting with
Sinusoidal Input Current for PFC Front Ends ....................... UC3854NB ......
UCC3913 Electronic Circuit Breaker for Negative Voltage Applications
Evaluation Kit List of Materials for a -48V/1A Test Circuit .............. UCC3913 ........
Parelling UCC3912 Electronic Circuit Breaker ICs ................... UCC3912 ........
UC3573 Buck Regulator PWM Control IC .......................... UC3573 .........
Lamp Ignitor Circuit ........................................... UCC3305 ........
UCC3941 One Volt Boost Converter Demonstration Kit - Schematic and
List of Materials .............................................. UCC3941-3/5/ADJ.
Using the UC3871 and UC3872 Resonant Fluorescent Lamp Drivers in
Floating Lamp Applications ..................................... UC3872 .........
Closed Loop Temperature Regulation Using the UC3638 H-Bridge Motor
Controller and a Thermoelectric Cooler............................ UC3638 .........
Overcurrent Shutdown with the UC3853 ........................... UC3853 .........
High Power Factor Preregulator IC, Evaluation Board, Schematic and
List of Materials .............................................. UC3853 .........
UCC3750 Demonstration Board Operating Guidelines ................ UCC3750 ........
UCC3911 Demo Board Information ............................... UCC3911 ........
UCC3958 Demonstration Board Schematic and Bill of Materials ........ UCC3958 ........
UC3584 DW Secondary Side Post Regulator, Evaluation Board,
Schematic, and List of Materials ................................. UC3584 .........
UCC3956 Switch Mode Lithium-Ion Battery Charger Controller
Evaluation Board, Schematic and List of Materials ................... UCC3956 ........
UCC3831 USB Power Controller IC, Evaluation Board - Schematic and
List of Materials .............................................. UCC3831 ........
UCC3954 Single Cell Lithium-Ion to +3.3V Converter Performance
Evaluation Kit - Schematic and List of Materials ..................... UCC3954 ........
UCC3918 Low On-Resistance Hot Swap Power Manager Performance
Evaluation Kit, Schematic and List of Materials ..................... UCC3918 ........
UCC5342 IrDA 115.2kbps Tranceiver Performance Evaluation BoardSchematic and List of Materials .................................. UCC5342 ........
Comparing the UC3842, UCC3802, and UCC3809 Primary-Side PWM
Controllers .................................................. UC3842/3/4/5 . ....
UCC3858 "Energy Star" PFC Evaluation Board, Schematic and List of
Materials ................................................... UCC3858 ........
UCC3926DS ±20A Integrated Current Sensor Evaluation Board Schematic and List of Materials .................................. UCC3926 ........
UCC5630 SCSI Multimode (LVD/SE) Evaluation Board and List of
Materials ................................................... UCC5630 ........
UCC3957, Three - Four Cell Lithium-Ion Protector Circuit, Evaluation
Board and List of Materials ..................................... UCC3957 ........
UCC5343, IrDA Transceiver with Encoder/Decoder, Evaluation Board and
List of Materials .............................................. UCC5343 ........
UCC3919 Hot Swap Power Manager Evaluation Circuit Board and Bill of
Materials ................................................... UCC3919 ........
UCC3952 Evaluation Board and List of Materials .................... UCC3952 ........

DN-65
DN-66
ON-67
ON-68
DN-70
DN-72
DN-73

DN-75
DN-76
DN-77
DN-78
DN-79
DN-81
DN-82
DN-83
DN-84
ON-85

DN-86
ON-87

DN-88
DN-89
DN-90
DN-91
DN-92

DN-93
DN-94
ON-95

DN-96

-

IC Featured Volume/Page

Pub.

Publications included in this book are listed in bold.

1-25

PS/3-502
PS/3-505
PS/4-86

IF/5-105
IF/5-106
PS/3-508
PS/9-52
PP17-101
PP/8-50
PS/8-118
PS/4-91
PS/4-92
PS/9-55
PP/6-51
PP/6-55
PS/3-511

PP/3-413
IF/5-106
PP17 -103
IF/5-113
PP/9-15
PS/3-514
PS/4-94

PS/9-58
IF/3-122
PP/6-57
PP/9-19
IF/5-116
PP/6-61

Application/Design Notes by Publication Number

Ie Featured

0:dJ

Pub.

Title

DN-97

UCC39411 Low Power Synchronous Boost Converter Evaluation Kit,
Schematic and Bill of Materials .................................. UCC39411/2/3 .... PP17-106
UCC3917 Positive Floating Hot Swap Power Manager Evaluation Kit,
Schematic and Bill of Materials .................................. UCC3917 ........ IF/5-120
Pulse Edge Transmission (PET) circuit ............................ UCC3961 ........ PS/8-102
Using RAM Clear Function with bq3285/bq3287A RTCs .............. bq3285/bq3287 ... NV/4-321
High-Side Current Sensing with Benchmarq Portable Power Fast-Charge
Control IC .................................•............... ; ........ ,......... PP/3-307
UC3842/3/4/5 Provides Low-Cost Current-Mode Control .............. UC3842/3/4/5 ..... PS/3-532
UC1637/2637/3637 Switched Mode Controller for DC Motor Drive ...... UC3637 ......... PS/8-126
Improved Charging Methods for Lead-Acid Batteries using the UC3906 .. UC3906 ......... PP/3-388
1.5MHz Current Mode IC Controlled 50W Power Supply .............. UC3825 ......... PS/3-546
Practical Considerations in Current Mode Power Supplies ............. UC3709 ......... PS/3-558
A High Precision PWM Transconductance Amplifier for Microstepping
using Unitrode's UC3637 ....................................... UC3637 ......... PS/8-137
Design Notes on Precision Phase Locked Speed Control for DC Motors .. UC3634 ......... PS/8-145
New Integrated Circuit Produces Robust, Noise Immune System for
Brushless DC Motors .......................................... UC3625 ......... PS/8-155
New Driver ICs Optimize High Speed Power MOSFET Switching
Characterisitics ............................................... UC3709 ......... PS/6-92
A Simplified Approach to DC Motor Modeling for Dynamic Stability
Analysis ..................................•................. UC3638 ......... PS/8-162
A New Family of Integrated Circuits Controls Resonant Mode Power
Converters .................................................. UC3861-8 ....... PS/3-576
Unique Chip Pair Simplifies High Side Switch Drive .................. UC3725 ......... PS/6-107
The UC3823A,B & UC3825A,B Enhanced Generation of PWM
Controllers .................................................. UC382315A1B/3 ... PS/3-585
UC3907 Load Share IC Simplifies Parallels Power Supply Design ....... UC3907 ......... PS17-84
Dedicated ICs Simplify Brushless DC Servo Amplifier Design .......... UC3625 ......... PS/8-166
Simple Switch mode Lead-Acid Battery Charger ..................... UC3906 ......... PP/3-417
Power Factor Correction Using the UC3852 Controlled ON-Time Zero
Current Switching Technique .................................... UC3852 ......... PS/4-98
UCC3800/1/2/3/4/5 BiCMOS Current Mode ControIICs •.............. UCC3800/1/2/3/4/5 PS/3-594
UC3854 Controlled Power Factor Correction Circuit Design ............ UC3854 ......... PS/4-114
The UC3848 Average Current Mode Controller Squeezes Maximum
Performance from Single Switch Converters ........................ UC3848 ......... PS/3-612
Phase Shifted, Zero Voltage Transition Design Considerations and the
UC3875 PWM Controller .......................... '............. UC3875/6/7/8 ..... PS/3-623
Practical Considerations in High Performance MOSFET, IGBT & MCT
Gate Drive Circuits ............................................ UC3709 ......... PS/6-122
Zero Voltage Switching Resonant Power Conversion ................. Ue3861-8 ....... PS/3-637
Average Current Mode Control of Switching Power Supplies ........... UC3849 ......... PS/3-664
Resonant Fluorescent Lamp Converter Provides Efficient and Compact
Solution .................................................... UC3871 ......... PP/8-27
New Chip Pair Provides Isolated Drive for High Voltage IGBTs ......... UC3727 ......... PS/6-137
UCC3806 BiCMOS Current Mode ControIIC ....................... UCC3806 ........ PS/3-678
Dimmable Cold-Cathode Fluorescent Lamp Ballast Design Using the
UC3871 ..............................................•..... UC3871 ......... PP/8-35
Simple Off-Line Bias Supply for Very Low Power Applications .......... UCC3888 ........ PS/3-685

DN-98
DN-99
DN-501
DN-502
U-100A
U-102
U-104
U-110
U-111
U-112
U-113
U~115

U-118
U-120
U-122
U-127
U-128
U-129
U-130
U-131
U-132
U-133A
U-134
U-135
U-136A
U-137
U-138
U-140
U-141
U-143C
U-144
U-148
U-149A

Publications included in this book are listed in bold.

1-26

VolumelPage,

Pub_
U-150
U-1S1
U-152
U-153
U-154
U-155
U-156
U-157
U-158
U-1S9
U-161
U-163
U-164
U-165
U-166
U-167
U-168
U-169
U-500
U-502
U-503
U-504
U-S05
U-506
U-S07
U-S08
U-S09
U-510
U-S11
U-512
U-513
U-514
U-93
U-94
U-95
U-97
U-99

Application/Design Notes by Publication Number
Title
Ie Featured

-

Volume/Page

Applying the UCC3570 Voltage-Mode PWM Controller to Both Off-Line
and DC/DC Converter Designs .................................. UCC3570 ........ PS/3-696
UCC3912 Integrated Hot Swap Power ManagerTM IC for Hot-Swap and
Power Management Applications ................................ UCC3912 ........ IF/5-124
A High Performance Linear Regulator for Low Dropout Applications ..... UC3832/3 ........ PS/5-71
UC3855A/B High Performance Power Factor Preregulator ............. UC3855A/B ...... PS/4-134
The New UC3879 Phase Shifted PWM Controller Simplifies the Design
of Zero Voltage Transition Full-Bridge Converters .................... UC3879 ......... PS/3-709
Implementing Multi-State Charge Algorithm with the UC3909
Switchmode Lead-Acid Battery Charger Controller ................... UC3909 ......... PP/3-426
The UC3886 PWM Controller Uses Average Current Mode Control to
Meet the Transient Regulation Performance of High End Processors ..... UC3886 ......... PS/3-717
Fueling the Megaprocessor - A DC/DC Converter Design Review
Featuring the UC3886 and UC3910 ......... ; .................... UC3886 ......... PS/3-741
The UC3910 Combines Programmability, Accuracy and Integrated
Functions to Control and Monitor High End Processor Power Supplies ... UC3910 ......... PS/3-771
Boost Power Factor Corrector Design with the UC3853 ............... UC3853 ......... PS/4-154
Powering a 35W DC Metal Halide High Intensity Discharge (HID)
Lamp using the UCC3305 HID Lamp Controller ..................... UCC3305 ........ PS/9-61
The UC3902 Load Share Controller and Its Performance in Distributed
Power Systems .............................................. UC3902 ......... PSI7-100
The UCC3884 Frequency Foldback Pulse Width Modulator ............ UCC3884 ........ PS/3-783
Design Review: Isolated SOW Flyback with the UCC3809 Primary Side
Controller and the UC3965 Precision Reference and Error Amplifier ..... UC396S ......... PS/3-800
An Off-Line Lead-Acid Charger Based on the UC3909 ................ UC3909 ......... PP/3-399
UC3578 Telecom Buck Converter Evaluation Board .................. UC3578 ......... PS/3-818
Implementing an Off-Line Lithium-Ion Charger Using the UCC3809
Primary Side Controller and the UCC3956 Battery Charger Controller ... UCC3809-1,-2 .... PS/3-455
The New UCC3750 Source Ringer Controller Provides A Complete
Control Solution for a Four-Quadrant Fluback Converter .............. UCC3750 ........ PS/9-76
Using the bq484S for a Low-Cost RTC/NVSRAM Subsystem ........... bq4845 .......... NV/4-310
Time-Base Oscillator for RTC ICs ................................................ NV/4-322
Using the bq328517E in a Green or Portable Environment ............. bq328517E ....... NV/4-331
Using the bq2000/T to Control Fast Charge ........................ bq2000/T ........ PP/3-262
Using the bq2003 to Control Fast Charge .......................... bq2003 .......... PP/3-273
Step-Down Switching Current Regulation Using the bq2003
Fast-Charge IC .............................................. bq2003 .......... PP/3-291
Using the bq2005 to Control Fast Charge .......................... bq200S .......... PP/3-309
Using the bq2007 Display Mode Options .......................... bq2007 .......... PP/3-327
Using the bq2007 Enhanced Features for Fast Charge ............... bq2007 .......... PP/3-332
Using the bq2031 to Charge Lead-Acid Batteries .................... bq2031 .......... PP/3-346
Switch-Mode Power Conversion Using the bq2031 ................... bq2031 .......... PP/3-360
Using the bq2902/3 Rechargeable Alkaline ICs ..................... bq2902/3 ........ PP/3-376
Using the bq2040: Smart Battery System Gas Gauge IC .............. bq2040 .......... PP/4-372
Using the bq201 0: A Tutorial for Gas Gauging ...................... bq201 O.......... PP/4-390
A New Integrated Circuit for Current Mode Control ................... UC384617 ........ PS/3-518
The UC1901 Simplifies the Problem of Isolated Feedback in Switching
Regulators .................................................. UC3901 ......... PSI7-72
Versatile UC1834 Optimizes Linear Regulator Efficiency .............. UC3834 ......... PS/S-49
Modeling, Analysis and Compensation of the Current Mode Converter ... UCC3813 ........ PS/3-526
UC3717 and L-C Filter Reduce EMI and Chopping Losses in Step Motor. UC3717 ......... PS/8-118

Publications included in this book are listed in bold.

1-27

Application/Design Notes by Subject
INTERFACE (IF)
HQt Swap Power Managers
.

Discrete Electronic Hot Swap Power Manager Design .................... ON-30
Hot Swap Protection ............................................... U-151
Integrated Hot Swap Power Manager .................................. U-151
Paralleling Multiple UCC3912s ...................................... ON-68
UCC3912 Programming and Demo Kit ................................ ON-58
UCC3913121 Negative Floating Hot Swap Power Manager Evaluation Kit,
Schematic and List of Materials . . . . . . . . . .. . . . . . . . ................ ON-67
UCC3917 Positive Floating Hot Swap Power Manager Evaluation Kit,
Schematic and Bill of Materials .................................. ON-98
UCC3918 Low On-Resistance Hot Swap Power Manager Demo Board ....... ON-87
UCC3919 Hot Swap Power Manager Evaluation Circuit and List of Materials .. ON-95

SCSI
UCC5630 SCSI Multimode (LVD/SE) Evaluation Board and List of Materials .. . ON-92

NONVOLATILE SRAMS AND REAL-TIME CLOCKS (NV)
Real-Time Clocks
Low-Cost RTC/NVSRAM Subsystem .................................. U-500
Typical PC Hookups for Real-Time Clocks .............................. U-501
Time-Base Oscillator tor Real-Time Clock ICs .......................... U-502
Real-Time Clocks in a Green Environment ............................. U-503
Using the RAM Clear Function ..................................... DN-50t·

PORTABLE POWER (PP)
Battery Charging
Battery Charger Basics ............................................ U-155
Current Sense Considerations ....................................... U-155
Lead Acid Battery Charger .............................. U-104, U-131, U510
Lead Acid Charging Algorithms ...................................... U-131
Switchmode Lead-Acid Battery Charger ............. , ........... U-131, U-155
Off-Line Lead Acid Battery Charger ................................... U-166
Off-Line Lithium Ion Battery Charger ............................ DN-S4, U-168
High-Side Current Sensing with Fast-ChargelCs ....................... DN-502
NiMH and NiCd Switch-Mode Battery Charger .......................... U-506
NiMH and NiCd Battery Charger with tJ.T/tJ.t and -tJ.V Termination ...... U-505, U-50?
Fast-Charge IC with LCD and LED and Other Advanced Features ..... U-50S, U-509
Fast-Charge IC for Switch-Mode Power Conversion ...................... U-511

Publications included in this book are listed in bold.

1-28

-

QdJ

Application/Design Notes by Subject
Rechargeable Alkaline Battery Charger ................................ U-512
Multi-Chemistry Battery Charger ..................................... U-504

Battery Capacity Monitoring
Smart Battery System Gas Gauge .................................... U-513
Tutorial for Gas Gauging ............................................ U-514

Cold Cathode Fluorescent Lamp Driver (CCFL)
ZVS Resonant Converter Drive ...................................... U-141
CCFL and LCD Bias Circuit ......................................... U-148
Floating Lamp Driver .............................................. DN-75

Lighting Circuits
CCFL and LCD Bias Circuit ......................................... U-148

Reference Designs
CCFLDrives

zvs Converters

............................................ U-141, U-148

Battery Protection
2-Cell Lithium Ion Battery Protection .................................. DN-81
Single Cell Lithium Ion Battery Protection .............................. DN-82
3 or 4 Cell Lithium Ion Battery Protection .............................. DN-93
Enhanced Single Cell Lithium Ion Battery Protection ..................... DN-96

Battery Charging
Lead Acid Battery Charger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-131
Off-Line Lead Acid Battery Charger ................................... U-166
Off-Line Lithium Ion Battery Charger ............................ DN-84, U-168

POWER SUPPLY CONTROL (PS)
Bias Supplies
Buck-Boost Supply ............................................... DN-38
High Efficiency Startup / Bootstrap Circuits.................... U-111 (fig. 38, 39)
Inductorless Bias Supply ........................................... DN-64
Negative Bias Supply .............................................. DN-43
Novel Regulated Bias Supply for PFC Applications ................ DN-39E (fig. 5)
Self-Generating High Side Gate Bias Supply ........................... DN-54
Simple Off-Line Bias Supply ................................. DN-65, U-149A
UCC3889 Demo Kit. ....................... , ..................... DN-59A

Bootstrap Circuits
High Efficiency Startup / Bootstrap Circuits ................... U-111 (figs. 38,39)
Startup / Bootstrapping ..................................... U-128, U-133A

Publications included in this book are listed in bold.

1-29

-

[1JJ

Application/Design Notes by Subject

Charge Pumps
Inverting Charge Pump ........................................... U-100A
Non-Inverting Charge Pump ....................................... U-100A
Simple Inverting and Non-Inverting Circuits ..................... U-133A (fig. 26)

Class-D Amplifiers
Class-D Amplifier for Thermoelectric Devices ........................... DN-76

Control Techniques
Current / Voltage Mode Tradeoffs .................................... DN-62

Average Current Mode
Average Current Control ............ U-131, U-135, U-140, U-156, U-157, U-159
Average Current Sensing ..................................... U-140, DN-41

Peak Current Mode
BiMOS Controller Advantages ...................................... DN-42A
Comparison of Economy Primary Side Controllers ....................... DN-89
Frequency Foldback ......................................... DN-29, U-164
Low Power Controller .............................................. U-144
Peak Current Mode Control ... U-93, U-100A, U-133A, U-144, U-164, U-165, U-170
Practical Considerations ..................................... U-111, U 133A
Programming the UCC3806 ......................................... DN-51
Slope Compensation ................................... U-97, U-11 0, U-111
Soft Start ........................ : .............................. U-133
Using Current Mode ICs in Voltage Mode Applications .................... U-111

Voltage Mode
Primary Side Controller ...................................... U-150, U-167
Voltage Feedforward ............................................... U-150
Using Current Mode ICs in Voltage Mode Applications .................... U-111

Current Sensing
Average Current Sensing ......................... U-135, U-140, U-156, U-157
Current Sense Amplifiers ..................................... U-156, U" 157
Using PCB Traces to Sense Current .................................. DN-71
UCC3926 +/- 20 Amp Integrated Circuit for Current Sensing ............... DN-91

Distributed Power
Load Sharing .............................................. U-129, U-163

Electronic Loads
Adjustable Load for Low Voltage DC Applications ........................ DN-52

Feedback Techniques
Average Current Sensing ..................................... U-135, U-140
Optocoupler Feedback ........................... DN-32, DN-33, U-160, U-165
Transformer Isolation ......................................... U-94, DN-41
Publications included in this book are listed in bold.

1-30

-

[1:JJ

Application/Design Notes by Subject

Frequency Foldback
Simple Frequency Foldback Circuit ................................... DN-29
UCC3884 Frequency Foldback PWM .................................. U-164

Gate Drives
Gate Drive Considerations .......................................... U-137
Gate Drive Pulse Transformer Design ................................. U-127
General Gate Drive Information ...................................... U-111
Integrated Drivers ......................................... U-143C, DN-35
UC3726 / UC3727 Demo Kit Testing .................................. DN-60
UC3726 / UC3727 Power Considerations .............................. DN-57

Isolation Amplifier
Discrete Iso-Amp Design ........................................... DN-19

Leading Edge Blanking
Current Sense Noise .............................................. U-128
LEB Implementation ........................................ U-128, U-133A

Lighting Circuits
Driving Floating Fluorescent Lamps .................................. DN-75
HID Lamp Controller. .............................................. U-161
Lamp Ignitor Circuits .............................................. DN-72
ZVS Resonant Converter Drive ...................................... U-141

Linear Voltage Regulators
External Power Device Configurations ............................ U-95, U-104
Linear Regulator Controllers .............................. U-95, U-116, U-152
l.:.badsharing ..................................................... U-129
Microprocessor Regulator Design .............................. U-152, DN-61
Multiple LDO Regulator Demo Kit .................................... DN-74
Small Signal Analysis ......................................... U-95, U-152

Load Sharing
Application Circuits .......................................... U-129, U-163
Load Sharing Control Techniques .............................. U-129, U-163
Startup Considerations ............................................. U-129

Magnetics Design
1.5MHz Forward Converter Main Transformer ........................... U-110
225KHz Off-Line Transformer ........................................ U-150
Gate Drive Pulse Transformer Design ................................. U-127
SEPIC Converter Inductor Design .................................... U-161

Publications included in this book are listed in bold.

1-31

-

[1JJ

Application/Design Notes by Subject
Microprocessor Voltage Regulators
Linear Regulators
High Performance LDO Controller .............................. U-152, DN-61

Switching Regulators
4Bit DAC and Voltage Monitor for Pentium®Pro .......................... U-158
Average I-Mode Controller for Pentium®Pro ............................ U-156
Fueling the MegaProcessor - A DC/DC Converter Design Review ........... U-157

Motor Control
Brush DC Motors
PWM DC Motor Controller .......................................... U-102
Synchronizing Multiple UC3637 Oscillators ........................... DN-53A

Brushless DC Motors
3-Phase Controller .......................................... U-115, U-130
Current Loop Design .............................................. U-130
Four Quadrant Control ............................................. U-130
Fixed Off-Time Modulation .......................................... U-106
Integrated 3-Phase Control/Driver ................................... U-106
Power Supply Bus Clamp ..................................• " ...... U-130
Trouble Shooting UC3625 Applications ................................ ON-50

Phase Locked Loops
Loop Filter Design ................................................ U-113
Small Signal Analysis .............................................. U-113

Power H~Bridge Design
H-Bridge Power Amplifier ..................................... U-102, U-112

SmalJ.Signal Modeling
Current Loop, Small Signal Analysis .................................. U-112
Motor Modeling ....................................... U-102, U-113, U-120
Velocity Loop, Small Signal Analysis ............................ U-102, U-113

Stepper Motors
Microstepping Transconductance Amplifier ............................. U-112
Reducing EMI in Stepper Motor Drives ................................. U-99

Optocoupler Isolation
Optocoupler Feedback Drive Techniques ........................ DN-32, DN-33
Simple Circuit Modifications Enhance Optocoupler Performance ............ U-160

Post Regulation
UC3584 Evaluation Board ............... ; ..... ; .................... DN-83

Power Device Drivers
Calculating Average Gate Drive Current ............................... U-156
Determining Gate Charge ..................................... U-118, U-137
Direct Coupled Drivers ....................................... U-118, U-137

Publications included in this book are listed in bold.

1-32

-

0::lJ

Application/Design Notes by Subject
Gate Drive Considerations ...................•............... U-137, U143C
General Gate Drive Information ...................................... U-111
Isolated High Side Switch Drive ...................................... U-127
Modeling the Power MOSFET ....................................... U-118
Power Dissipation Analysis .......................................... U-137
Transformer Coupled Drivers ........................................ U-118
UC3726 / UC3727 Power Considerations .............................. DN-57

Power .Factor Correction
Active Power Factor Correction Description ....................... U-134, U-159
Controlled On-Time, Zero Current Switched PFC ........................ U-132
Controlled On-Time, Zero Current Switching ............................ U-132
Current Sensing ............................................ U-134, U-153
Current Synthesizer ............................................... U-153
Distortion Sources ................................................ U-134
Effects of Discharge Current on Maximum Duty Cycle .................... DN-40
Fault Protection Circuits ............................................ DN-77
Novel Regulated Bias Supply for PFC Applications ................ DN-39E (fig. 5)
Optimizing Circuit Performance ..................................... DN-39E
Power Limiting Features ........................................... DN-66
UC3853 Evaluation Board ......... '.' ........... , ................... DN-78
UC3854 Demo Board ............................................. DN-44
UC3855 Design Example ........................................... U-153
UCC3858 Evaluation Board ......................................... DN-90
Voltage Feedforward Circuitry .................................. U-132, U-134
ZVT Techniques .................................................. U-153

PWM Oscillators
Noise Sensitivity ................................................. U-100A
Universal Synchronization Techniques .................. U-100A, U-111, U-133A
Voltage Feedforward Oscillators ....................................... U-94

Rectification
Alternative Full-Wave Rectifier Topology ............................... DN-63

Resonant Converters
Resonant Tank Considerations ...................................... U-136
Transformer Coupled Equations ...................................... U-138
Zero-Voltage Switching ....................................... U-122, U-136
Zero-Current Switching ............................................ U-122

Ring Generator Controllers
Design Procedure and Circuit Analysis ..... : .......................... U-169
UCC3750 Demo Board ............................................ DN-79

Publications included in this book are listed in bold.

1-33

[1JJ

-

-

[1!J

Application/Design Notes by Subject

Secondary Side Regulation
Secondary Side Regulator .......................................... U-139
UC3584 Switching Post Regulator Evaluation Board ..................... DN-83

Small Signal Analysis
Average Current Mode ................................. U-135, U-140, U-157
Average Current Mode PFC ............................. U-134, U-153, U-159
Buck Regulator .................................................... U-97
CCFL Ballast .................................................... U-148
Error Amplifier Response ..................................... U-95, U-100A
Load Models ................•..................................... U-95
Push-Pull Forward Converter ........................................ U-11 0

Subharmonic Oscillation
Slope Compensation ......................................... U-95, U-11 0

Supervisory Functions
Overvoltage Protection ............................................. U-158
Startup and Fault Protection ........................................ ON-26

SWitching Regulators - Reference Designs
Flyback Converters
1W, 5VIN, +/-12VOUT, RS-232/ RS-422 Converter ..................... ON-56A
25W, Off-Line, 5V, +/-12VOUT, Flyback ............................... U-100A
50W, -48VIN, 5V, Flyback ........................................... U-165
60W, Off-Line, 5V, 12VOUT, Flyback ................................... U-94

Forward Converters
20W, 48VIN, 5VOUT Voltage Mode Forward Converter ............. ".......
50W, 18-26VIN, 5VOUT, ZVS Forward Converter ........................
50W, Off-Line, 12VOUT, Voltage Mode Converter ........................
200W, Off-Line, 5V, +/-15VOUT, Average I-Mode Forward Converter .........

U-150
U-138
U-150
U-135

Non-Isolated Buck, Boost, Flyback and SEPIC Converters
5VIN, 3.3VOUT, Buck Regulator ..................................... ON-54
200mW, 5VIN, -3VOUT, Flyback Converter ............................. ON-46
500mW, WIN, Adjustable Output Voltage, Boost ........................ ON-73
5W, 12VIN, 5VOUT, Buck Regulator .................................. ON-70
35W, +48VIN, 5VOUT, Buck ......................................... U-167
HID Lamp Controller, SEPIC ........................................ U-161
Low Power Synchronous Boost Converter Evaluation Kit ................. ON-97
Peak Current Mode, Buck / Boost Designs ............................ U-133A
Pentium®Pro Converter with Adjustable Output, Buck..................... U-157
Single Cell Lithium Ion to +3.3V Converter Evaluation Kit .................. DN-86
Versatile Low Power SEPIC Converter ................................ ON-48

Publications included in this book are listed in bold.

1-34

Application/Design Notes by Subject
Push-Pull Converters
SOW, -48VIN, SVOUT, 1.SMHz Peak I Mode ............................ U-110
7SW, 48VIN, SVOUT, Isolated Push-Pull ............................... U-170
SOOW, -48 VIN, SVOUT Push-Pull ................................... U-100A
Push-Pull Forward Converter ......................................... U-93

Full Bridge
SOOW, 400VIN, 48VOUT, ZVT Converter ............................... U-136

Post Regulation
1S0KHz, 3.3VOUT, Switching Post Regulator ........................... DN-83

Power Factor Correction
8SW, 3S0VOUT, Zero Current Switched PFC ............................ U-132
250W, 400VOUT, Average Current Mode PFC ........................... U-134
2S0W, 385VOUT, Average I-Mode PFC ................................ DN-44
100W, 7SKHz, 38SVOUT, Average Current Mode PFC .................... DN-78
250W, 385VOUT, Average Current Mode PFC .......................... DN-90
SOOW, 410VOUT, Average Current Mode, ZVT, PFC ...................... U-1S3
Controlled, On-Time, Zero Current Switched PFC ........................ U-132

Soft Switching ZVT Converters
SOOW, 400VIN, 48VOUT, ZVT Converter .............................. U-136

Ring Generator Controllers
8SV, 15 REN, Ring Generator ................................. DN-79, U-169

Synchronization
Universal Synchonization Techniques ................... U-100A, U-111, U-133A

Thermoelectric Drivers
Class-D Amplifier for Thermoelectric Devices ........................... DN-76

Zero Current Switching
Controlled, On-Time, Zero Current Switched PFC ........................ U-132
Resonant Mode Control ............................................ U-122

Zero Voltage Switching
Design Examples ................................................. U-138
Phase Shifted Full-Bridge Controller .................................. U-1S4
Resonant Mode ZVS .................................. U-122, U-136, U-138
Transformer Coupled Design Equations ................................ U-138
ZVS Topologies .................................................. U-138

Publications included in this book are listed in bold.

1-3S

-

[1::JJ

-

[1JJ

Ordering Information

(see Benchmarq ordering information page for "bq" prefix products)

§JI XXxxx IIXXI@][§J

J

17131
27131
37131

example

PREFIX
"UC" - Linear Integrated Circuits
"UCC" - BiCMOS

PART NUMBER
First digit "1" - Military Temperature Range*
First digit "2" - Industrial Temperature Range*
First digit "3" - Commercial Temperature Range*
(*consult individual data sheets for specific
temperature ranges on each part)

;?~•

.,.Sl.9nator

'.'

general syntax

SCREEN/PROCESSING OPTIONS
"883" - MIL-STO-883
Class Q of MIL-PRF-38535
PACKAGE OPTIONS

OPTIONAL GRADES
A or B - Improved Version

....... :';, ,>;./,1 P,4Ckage Type

Plastic Narrow Body (150 mil) SOIC

•. Q

······,·.·ow

Plastic Wide Body (300 mil) SOIC

·,;.;~:;.~P· ....... Plastic Narrow Body Power SOIC

".~:>p~:"

Plastic Narrow Body (150 mil) SOIC with Shunt Current Sense

i;;'Cf.\!>Wf?: .

Plastic Wide Body Power SOIC

.• . ;: . ~.•,'=~< .
:/.~;,

iFtr· .

",F~

»J
. '.
;.1,

...

Power Plastic Metric Quad Flatpack (MQFP)
Power Low Profile Quad Flatpack (LQFP)
Power Plastic Low Profile Quad Flatpack (LQFP)
Ceramic Dual-in-Line (300 mil and 600 mil)
Ceramic Leadless Chip Carrier

i:i:i:J,.FiI·,
·::M

Quasi Shrink Small Outline (150 mil body, 0.635mm pitch)

;:.:NJWP,:

Power Quasi Shrink Small Outline (300 mil body, O.88mm pitch)

.·V' . ''';

",''lI'"

Ui4'''\f'· .

""

2.9

a:

c.. ·21.15
t-

:::J

0
X

vs. Temperature

2.85

·21.3

2.8

<
::;; ·21.45

2.75
·21.6

2.7

·21.75

2.65

o

·55

25

80

125

·55

TEMPERATURE

0

25

80

125

TEMPERATURE

Output Impedance VS. Temperature

VREFVS. VIN
3

135
132
129
w

()

z
<
0

0.5V

2

...w

w

c..
~

a:

>

...J

123
120
117

z<

114

z

111

~
0

·1

126

108
105
102

0
0

1.5

4.5

3

6

·55

7.5

0

25

80

TEMPERATURE

VIN

UNITRODE CORPORATION
7 CONTINENTAL BLVD.• MERRIMACK, NH 03054
TEL (603) 424-2410. FAX (603) 424-3460

3·17

125

~UNITRODE

UC5603

9-Line SCSI Active Terminator
FEATURES

DESCRIPTION

•

Complies with SCSI, SCSI-2 and
SPI-2 Standards

•

6pF Channel Capacitance during
Disconnect

The UC5603 provides 9 lines of active termination for a SCSI (Small Computers Systems Interface) parallel bus. The SCSI standard recommends active
termination at both ends of the cable segment.

•

100IJA Supply Current in
Disconnect Mode

•
•

Meets SCSI Hot Plugging
-400mA Sourcing Current for
Termination

•

+400mA Sinking Current for
Active Negation Drivers

•

Logic Command Disconnects all
Termination Lines

•

Trimmed Termination Current to
3%

•
•

Trimmed Impedance to 3%

•

Current Limit and Thermal
Shutdown Protection

Negative Clamping on all Signal
Lines

The UC5603 provides a disconnect feature which, when opened or driven
high, will disconnect all terminating resistors, and disables the regulator;
greatly reducing standby power. The output channels remain high impedance
even without Termpwr applied. A low channel capacitance of 6pF allows units
at interim pOints of the bus to have little to no effect on the signal integrity.
Functionally the UC5603 is similar to its predecessor, the UC5601 - 18 line
Active Terminator. Several electrical enhancements were incorporated in the
UC5603, such as a sink/source regulator output stage to ?ccommodate all
signal lines at +5V, while the regulator remains at its nominal value, reduced
channel capacitanc~ to 6pF typical, and as with the UC5601, custom power
packages are utilized to allow normal operation at full power conditions (1.2
watts).
.
Internal circuit trimming is utilized, first to trim the impedance to a 3% tolerance, and then ·most importantly, to trim the output current to a 3% tolerance,
as close to the max SCSI spec as possible, which maximizes noise margin in
fast SCSI operation.
Other features include negative clamping on all signal lines to protect exter,
nal circuitry from latch-up, thermal shutdown and current limit.
This device is offered in low thermal resistance versions of the industry standard 16 pin narrow body SOIC, 16 pin ZIP (zig-zag in line package) and 24 pin
TSSOP.

BLOCK DIAGRAM
TRMPWR

REG

4.0V-S.2SV

Termpwr

r -.....................-Q...-.Jvvv----iI--........--lJ LlNE1

1.S/1.3V

+--+--fi'--...
LlNE2

I
I
I

I
I
I
I

~_'IIv.--t-___*--r

LlNE9

Switch
Control

GND

3197

DISCNCT
(Low=Connect)

UDG-94049

Circuit Design Patented

3-18

UC5603
ABSOLUTE MAXIMUM RATINGS
Tennpwr Voltage ................................................... +7V
Signal Line Voltage ............................................. OV to +7V
Regulator Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O.5A
Storage Temperature ..................................... -65°C to +150°C
Operating Temperature .......... . . . . . . . . . . . . . . . . . . . . . . . .. -55°C to + 150°C
Lead Temperature (Soldering, 10 Sec.) ............................... +300°C
Unless otherwise specified aI/ voltages are with respect to Ground. Gurrents are positive into, negative out of the specified terminal.
Gonsu" Packaging Section of Unitrode Integrated Gircuits databook for thermallimitations and considerations of packages.

RECOMMENDED OPERATING CONDITIONS
Tennpwr Voltage ........................................... 3.BV to 5.25V
Signal Line Voltage ............................................. OV to +5V
Disconnect Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OV to Termpwr

CONNECTION DIAGRAMS
DIL-16 (Top View)
N or J Package

TSSOP-24 (Top View)
PWPPackage
LINES
LlNE5

REG
N/C
N/C

• PWP package pin 5 serves as signal ground; pins 6, 7, 8, 9,
17, 18, 19, and 20 serve as heatsinklground.

ZIP-16 (Top View)
Z Package

SOIC-16 (Top View)
r-T-.-.---"
DP Package
LINE7

1

LlNE6

TRMPWR
LlNE4
LINE3
LlNE2
LlNE1

LlNE5

REG

DISCNCT
SGND
SGND
SGND
SGND

GND"
SGND"

GND"
11 TRMPWR

LlNE9
LINES
LlNE7
LINES
LINES
REG

LINE4

• DP package pin 5 serves as signal ground; pins 4, 12, 13
serve as heatsinklground.

Note: Drawings are not to scale.

3-19

UC5603

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA= O°C to 70°C.
TRMPWR = 4.75V DISCNCT = OV. TA = TJ.
PARAMETER
Supply Current Section
Termpwr Supply Current

TEST CONDITIONS

MIN

All termination lines = Open
All termination lines = 0.5V
DISCNCT = Open

Power Down Mode
Output Section (Terminator Lines
Terminator Impedance
AluNE = -5mA to -15mA
VTRMPWR = 4V (Note 1)
Output HiQh VoltaQe
Max Output Current
VUNE= 0.5V
Max Output Current

Output Clamp Level
Output Leakage

Output Capacitance
Reaulator Section
Regulator Output Voltage
Reaulator Output VoltaQe
Line Regulation
Load Reaulation
Drop Out Voltage
Short Circuit Current
Sinking Current Capability
Thermal Shutdown
Thermal Shutdown Hysteresis
Disconnect Section
Disconnect Threshold
Threshold Hysteresis

107
2.7
-21.1
TJ= 25°C
O°C < TJ < 70°C -20.5
VUNE = 0.5V, TRMPWR = 4V (Note 1)
-20.3
TJ = 25°C
O°C < TJ < 70°C -19.8
VLINE = 0.2V, TRMPWR = 4.0V to 5.25V O°C < TJ < 70°C -22.0
ILiNE = -30mA
-0.2
TRMPWR = OV to 5.25V VUNE = 0 to 4V
REG=OV
VUNE = 5.25V
DISCNCT=4V
TRMPWR = OV to 5.25V, REG = Open
VUNE = OV to 5.25V
DISCNCT = Open (Note 2) (DP Package)
2.8
2.8

All Termination Lines = 5V
TRMPWR = 4V to 6V
IREG = +100mA to -100mA
All Termination Lines = 0.5V
VREG = OV
VREG = 3.5V

-200
200

I

Note 1: Measuring each termination line while other 8 are low (0.5V).
Note 2: Guaranteed by design. Not 100% tested in production.

3-20

1.3
100

TYP

MAX IUNITS

12
200
100

18
220
150

mA
mA

110
2.9
-21.9
-21.9
-21.9
-21.9
-24.0
-0.05
10

113

Ohms
V
mA
mA
mA
mA
mA
V
nA

/.1A

10

-22.4
-22.4
-22.4
-22.4
-25.4
0.1
400
100
400

6

8

pF

2.9
2.9
10
20
0.7
-400
400
170
10

3
3
20
50
1
-600
600

V
V
mV
mV
V
mA
mA
°C
°C

1.5
160

1.7
250

V
mV

~
nA

UC5603
APPLICATION INFORMATION
Termpwr

Termpwr

"*4.71'F

DISCNCT

DISCNCT

TRMPWR

TRMPWR

UC5601

UC5603
REG

L1

=
To Drivers
and Receivers

REG

12.21'F

................

14.71'F

=

.............................

To SCSI Bus
UDG-94050

Figure 1 : Typical Wide SCSI Bus Configurations Utilizing 1 UC5601 and 1 UC5603 Device

Termpwr

r-_~I"--lDISCNCT

l,r-

DlSCNCT

REG - - ,

...

TRMPWR

UC5603

1 1

Control Bits

!~d D~~:;~vers

L,-------,

TRMPWR '--

UC5603

Lit

Termpwr

9

22
. 1'F

I"'"

TRMPWR-

1

REG - - , .

~'--':'L1'--_ _---=L:':9-'1r-'

I

Data Bits

22
. 1'F

UC5603

~

REG - - ,

Lit

.. .L19
Data Bits

1

22
. 1'F

."..

I:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:":·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:· :1

~

To SCSI Bus

UDG-94051

Figure 2: "TYpical Wide SCSI Bus Configurations Utilizing 3 UC5603 Devices.

UNITRODE CORPORATION
7 CONTINENTAL BLVD.• MERRIMACK, NH 03054

TEL (603) 424-24tO. FAX (603) 424-3460

3-21

~UNITRCDE

UC5604

9-Line Low Capacitance SCSI Active Terminator
FEATURES

DESCRIPTION

•

Complies with SCSI, SCSI-2
Standards

•

9pF Channel Capacitance during
Disconnect

The UC5604 provides 9 lines of a-ctive tennination for a SCSI (Small Computer Systems Interface) parallel bus. The SCSI standard recommends active tennination at both ends of the cable segment.

•

1001lA Supply Current in
Disconnect Mode

•

Meets SCSI Hot Plugging Capability

•

-300mA Sourcing Current for
Termination

•

+40mA Sinking Current for Active
Negation

•

Logic Command Disconnects all
Termination Lines

•

Trimmed Termination Current to 7%

•

Trimmed Impedance to 7%

•

Current Limit and Thermal
Shutdown Protection

The UC5604 provides a disconnect feature which, when opened or driven
high, will disconnect all terminating resistors and disable the regulator,
greatly reducing standby power. The output channels remain high impedance even without Termpwr applied.
The UC5604 is pin-for-pin compatible with its predecessor, the UC5603 - 9
line Active Terminator. The only functional difference between the UC5604
and UC5603 is the absence of the negative clamps. Parametrically, the
UC5604 has a 7% tolerance on impedance and current compared to a 3%
tolerance on the UC5603 and the sink current is reduced from 300mA to
40mA. Custom power packages are utilized to allow nonnal operation at
full power conditions (1.2 watts).
Internal circuit trimming is utilized, first to trim the impedance to a 7% toler~
ance, and then most importantly, to trim the output current to a 7% tolerance, as close to the max SCSI spec as possible, which maximizes noise
margin in fast SCSI operation.
Other features include thermal shutdown and current limit.
This device is offered in low thermal resistance versions of the industry
standard 16 pin narrow body Sale, 16 pin ZIP (zig-zag in line package)
and 24 pin TSSOP.

BLOCK DIAGRAM
TRMPWR
4.0V-S.2SV

REG
110n
LlNE1

1.4/1.3V

110n
LlNE2
Disconnect
Comparator

I
I
I
I
I

I
I

I
I
I
I
I

I

lIon

L....,..--O--"I/II'v---I
Switch
Control

GND

DISCNCT
(Low = Connect)

LlNE9

UDG·94064

Circuit Design Patented

3/97
3-22

UC5604
ABSOLUTE MAXIMUM RATINGS
Termpwr Voltage ................................................... +7V
Signal Line Voltage ............................................. OV to +7V
Regulator Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O.5A
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°C to + 150°C
Operating Temperature ................................... -55°C to +150°C
Lead Temperature (Soldering, 10 Sec.) ............................... +300°C
Unless otherwise specified all voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of Unitrode Integrated Circuits databook for thermallimitations and considerations of packages.

RECOMMENDED OPERATING CONDITIONS
Terrnpwr Voltage .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3.8V to 5.25V
Signal Line Voltage ............................................. OV to +5V
Disconnect Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OV to Termpwr

CONNECTION DIAGRAMS
TSSOP-24 (Top View)
PWPPackage

DIL-16 (Top View)
N or J Package

LINE? 1

LlNE6

0

LINES 2
LINES

REG
N/C

N/C

LlNE4

• PWP package pin 5 serves as signal ground; pins 6, 7, 8, 9,
17, 18, 19, and 20 serve as heatsinklground

ZIP-16 (Top View)
Z Package

SOIC-16 (Top View)
DP Package

TRMPWR
LlNE4
LlNE3
LlNE2
LlNE1

DISCNCT
SGND
SGND
SGND
SGND
LlNE9
LlNE8
LlNE7
LINES
LlNE5
REG

• DP package pin 5 serves as signal ground; pins 4, 12, 13
serve as heatsinklground.
Note: Drawings are not to scale.

3-23

UC5604
ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = O°C to 70°C.
TRMPWR = 4.75V, DISCNCT = OV. TA = TJ.
PARAMETER
Supply Current Section
Termpwr Supply Current

TEST CONDITIONS

MIN

All termination lines = O~n
All termination lines = 0.5V
DISCNCT = Open

Power Down Mode
Output Section (Terminator Lines
Terminator Impedance
~ILlNE = -5mA to -15mA
Output High Voltage
TRMPWR = 4V (Note 1)

O°C < TJ < 70°C
TJ = 25°C
TJ = 25°C
O°C < TJ < 70°C
TJ=25°C
O°C < TJ < 70°C

Max Output Current

VLlNE = 0.5V

Max Output Current

VLlNE = 0.5V, TRMPWR = 4V (Note 1)

Output Clamp Level
Output Leakage

ILiNE = -30mA
DISCNCT=4V TRMPWR = OV to 5.25V VLlNE = 0 to 4V
REG=OV
VLlNE = 5.25V
TRMPWR = OV to 5.25V, REG = Open
VLlNE = OV to 5.25V
DISCNCT = Open (Note 2)

Output Capacitance
ReQulator Section
Regulator Output Voltage
Reaulator Output Voltaae
Line Regulation
Load Regulation
Drop Out Voltage
Short Circuit Current
Sinking Current Capability
Thermal Shutdown
Thermal Shutdown Hysteresis
Disconnect Section
Disconnect Threshold
Threshold Hvsteresis
Input Current

97
2.55
2.6
-19.5
-18.5
-18.0
-17.0
-0.2

MAX

UNITS

14
200
100

20
220
150

mA
mA

110

129
3.2
3.1
-22.4
-22.4
-22.4
-22.4
0.1
400
100
400

Ohms
V
V
mA
mA
mA
rnA
V
nA

9

12

pF

2.9
2.9
10
20
1.0
-400
40
170
10

3.2
3.1
20
50
1.2
-600

V
V
mV
mV
V
mA
mA
°C
°C

1.4
100
150

1.7

V
mV

200

I1A

2.9
-21.9
-21.9
-21.9
-21.9
-0.05
10
10.

2.5
2.55

All Termination Lines = 5V
TRMPWR = 4V to 6V
IREG = +1 OOmA to -100mA
All Termination Lines = 0.5V
VREG=OV
VREG=3.5V

TYP

-200
20

1.1
DISCNCT=OV

~

~.
nA

Note 1: Measurmg each termmatlon Ime while other 8 are low (0.5V).
Note 2: Guaranteed by design. Not 100% tested in production.

APPLICATION INFORMATION
Termpwr

,...--_+-----!DISCNCT

Termpwr

DISCNCT

TRMPWR

UC5604

TRMPWR

UC5604
REG

To Drivers

and Receivers

. . .

.

. . . . .

.

REG

. . . . . . . . . . . . . . . . . . . . . . . .

.

. . . . .

To SCSI Bus

Figure 1: Typical SCSI Bus Configurations Utilizing 2 UC5604 Devices

3-24

.

. . . .

.

UDG·94065

UC5604

APPLICATION INFORMATION (cant.)
Termpwr

r---_j~~D-IS-C-N-C-T---T-R-M-P-W-R~r_

l~ ···, I
I I

Termpwr

L

DISCNCT

UC5604

TRMPWR

L9

Control Bits

!~d D~i::~~vers

I ,kU)1F.r~

TRMPWRr_

UC5604

REGh

L1

r-

UC5604

=

REGh.
L1

L9

I ,k2.2)1F.r-

I···II
Data Bits

-=-

=

REGh

L1

L9

1···1
Data Bits

I ,k2.2)1F

I

-=

I:::::·:::::·:·:::::::':':::':::::':':::::::::':':::::::':':':':':':':':':::':':':':::::::':':::::::':':':':::::':':::::::::1

~

To SCSI Bus
UDG-94066

Figure 2: Typical Wide SCSI Bus Configurations Utilizing 3 UC5604 Devices.

UNITRODE CORPORATION
7 CONTINENTAL BLVD.• MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460

3-25

~UNITRODE

UC5605

9-Line Low Capacitance SCSI Active Terminator
FEATURES

DESCRIPTION

•
•

The UC5605 provides 9 lines of active termination for a SCSI (Small Computer
Systems Interface) parallel bus. The SCSI standard recommends active termination at both ends of the cable segment.

•
•
•

Reverse Disconnect
Complies with SCSI, SCSI-2
and SPI-2 Standards

The only functional differences between the UC5603 and UC5605 is the absence of the negative clamps on the output lines and the disconnect input must
be at a logic-low for the terminating resistors to· be disconnected. Parametrically, the UC5605 has a 5% tolerance on impedance and current compared to
a 3% tolerance on the UC5603. Custom power packages are utilized to allow
normal operation at full power (2 Watts).

5pF Channel Capacitance
during Disconnect
Hot Plugging Capability
-400mA Sourcing Current for
Termination

•

+1OOmA Sinking Current for

•
•

1V Dropout Voltage Regulator

The UC5605 provides a disconnect feature which, when driven low, disconnects all terminating resistors, disables the regulator and greatly reduces
standby power consumption. The output channels remain high impedance even
without Termpwr applied. A low channel capacitance of 5pF allows interim
points of the bus to have little to no effect on the signal integrity.

Active Negation

100ILA Supply Current in
Disconnect Mode

•

Trimmed Termination Current
to 5%

•
•

Trimmed Impedance to 5%

Internal circuit trimming is utilized, first to trim the impedance to a 5% tolerance,
and then most importantly, to trim the output current to a 5% tolerance, as close
to the maximum SCSI specification as possible. This maximizes the noise margin in fast SCSI operation. Other features include thermal shutdown and current limit.
This device is offered in low thermal resistance versions of the industry standard 16 pin narrow body SOIC, 16 pin ZIP (zig-zag in line package) and 24 pin
TSSOP.

Low Thermal Resistance
Surface Mount Packages

BLOCK DIAGRAM
TRMPWR
4.0V·5.25V

,-----

REG

---------------------

--------1
110n

1
1

1

,...+-~~.....~

1

LINE!

1
1

I
1

1.4V ....- - - I

1

~~?~
-v~~LlNE2

Disconnect
Comparator

1
1
1

I
I
I
I

1
1
1
1

I

I

1

~~LINE9

1£61

Switch
Control

~

L__

GND

_ __

:
1
1

-----------------------------~

DISCNCT
(High = Connect)
UDG·94122

Circuit Design Patented

3197

UC5605

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

Termpwr Voltage ................................. +7V
Signal Line Voltage ........................... OV to +7\;
Regulator Output Current .......................... 0.6A
Storage Temperature ................... -65°C to + 150°C
Operating Temperature ................. -55°C to + 150°C
Lead Temperature (Soldering, 10 Sec.) ............. +300°C
Unless otherwise specified al/ voltages are with respect to
Ground. Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of Unitrode Integrated Circuits databook for thermal limitations and considerations of packages.

Termpwr Voltage ......................... 3.8V to S.25V
Signal Line Voltage ........................... OV to +5V
Disconnect Input Voltage .................. OV to Termpwr

CONNECTION DIAGRAMS
DIL-16 (Top View)
N or J Package

ZIP-16 (Top View)
Z Package
TRMPWR
LlNE4
LlNE3
LlNE2
LlNEl
DISCNCT
GND
GND
GND
GND
LlNE9
LINES
LlNE7
LlNE6
LlNE5
REG

LINE6
LINES
REG

N/C
N/C

LlNE4

SOIC-16 (Top View)
DPPackage

TSSOP-24 (Top View)
PWPPackage
LINE6
LlNE7 1

0

LINES
REG
GNO·
GNO·
11

TRMPWR
LlNE4

• DP package pin 5 serves as Signal ground; pins 4, 12, 13
serve as heatsinkiground.

• PWP package pin 9 serves as signal ground; pins 5, 6, 7, 8,
11, 18, 19, and 20 serve as heatsinkiground.

Note: Drawings are not to scale.

3-27

UC5605

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = O°C to 70°C.
TRMPWR = 4.75V; DISCNCT = 2.4V, TA = TJ.
.
PARAMETER
Supplv Current Section
Termpwr Supply Current

TEST CONDITIONS

MIN

All termination lines = Open
All termination lines = 0.5V
Power Down Mode
DISCNCT=OV
Output Section (Termination Lines)
Terminator Impedance
AluNE = -5mA to -15mA
Output High Voltage
TRMPWR=4V
Max Output Current
VUNE = 0.5V

TJ = 25°C
O°C < TJ < 70°C
VUNE = 0.5V, TRMPWR = 4V (Note 1)
TJ=25°C
O°C < TJ < 70°C
VUNE = 0.2V, TRMPWR = 4.0V to 5.25V O°C < TJ < 70°C
DISCNCT=OV
REG=OV
VUNE = 0 to 4V
TRMPWR = OV to 5.25V
VUNE = 5.25V
REG = Open VUNE = OV to 5.25V
DISCNCT = OV (Note 2) (DP Package)

Max Output Current

Output Leakage

Output Capacitance
Regulator Section
Regulator Output Voltage
Une Regulation
Drop Out Voltaoe
Short Circuit Current
Sin kino Current Capability
Thermal Shutdown
Thermal Shutdown Hysteresis
Disconnect Section
Disconnect Threshold

104.5
2.65
-20.3
-19.8
-19.5
-19.0
-21.6

MAX

UNITS

17
200
100

23
225
150

mA
mA

110
2.9
-21.5
-21.5
-21.5
-21.5
-24.0
10

115.5
3.1
-22.4
-22.4
-22.4
-22.4
-25.4
400
100
400
6

Ohms
V
mA
mA
mA
mA
mA
nA

2.9
2.9
10
1.0
-400
100
170
10

3.1
3.1
20
1.2
-600
400

V
V
mV
V
mA
mA
°C
°C

1.4

1.7

V

10
5
2.7
2.7

All Termination Unes = 4V
TRMPWR = 4V to 6V
All Termination Unes = 0.5V
REG=OV
REG=3.5V

TVP

-200
75

1.1

uA

IlA
nA
pF

Note 1: Measuring each termination line while other 8 are low.
Note 2: Guaranteed by design. Not 100% tested in production.

APPLICATION INFORMATION
Termpwr

(

DISCNCT

TRMPWR

Termpwr

DISCNCT

GND
L1

TRMPWR

UC5605

UC5605
REG

12.2

GND
J1 F

To Drivers
and Receivers "--'-~~~~~~~~~~~~.;-.-;---o~~~~~~~~~~.~.~.~.~.~.~.~.-,

To SCSI Bus

Figure 1: Typical SCSI Bus Configurations Utilizing 2 UC5605 Devices

3-28

UDG·94123

UC5605

APPLICATION INFORMATION (cont.)
Termpwr

( ",1
~

DISCNCT

LOiScNCT

UC5605

TRMPWR

L1

L9

I···'I
Control Bits

TRMPWR-

UC5605

UC5605

REG ---,

.r--

=

;~d D~i::~~vers

TRMPWR-

Termpwr

::!:2.2~F.r--

I=-

=

REG ---,

L1

L9

1 ... 11
Data Bits

REG

::!:2. 2I1F . r - -

~

L1

L9

1···1
Data Bits

h
i

::!:2.2I1F

I

r:·:·:·:·:·:::::::·:·:·:·:::::·:·:·:·:::::::·:·:::·:::::·:·:·:::·:::·:·:·:::::::·:·:·:::·:·:·:·:::·:·:·:·:·:::::·:·:·:·:·:· :1

~

To SCSI Bus
UDG-94129

Figure 2: Typical Wide SCSI Bus Configurations Utilizing 3 UC5605 Devices.

UNITRODE CORPORATION
7 CONTINENTAL BLVD.• MERRIMACK, NH 03054

TEL (603) 424-2410. FAX (603) 424-3460

3-29

~UNITRODE

UCC5606

9-Line 3-5 Volt SCSI Active Terminator, Reverse Disconnect
FEATURES

DESCRIPTION

•

Complies with SCSI, SCSI-2 and
SCSI-3 Standards

•

2.7V to 7V Operation

The UCC5606 provides 9 lines of active termination for a SCSI (Small
Computer Systems Interface) parallel bus. The SCSI standard recommends active termination at both ends of the cable segment.

•

1.8pF Channel Capacitance during
Disconnect

•

1!lA Supply Current in Disconnect
Mode

•

110 Ohm/2.5k Programmable
Termination

•
•

Completely Meets SCSI Hot Plugging

The UCC5606 is ideal for high performance 3.3V SCSI systems. The key
features contributing to such low operating voltage are the 0.1 V drop out
regulator and the 2.7V reference. The reduced reference voltage was
necessary to accommodate the lower termination current dictated in the
SCSI-3 specification. During disconnect the supply current is typically
only 1!lA, which makes the IC attractive for battery powered systems.

-400mA Sourcing Current for
Termination

•

+400mA Sinking Current for Active
Negation Drivers

•
•
•

Trimmed Termination Current to 4%
Trimmed Impedance to 7%
Current Limit and Thermal Shutdown
Protection

The UCC5606 is designed with an ultra low channel capacitance of
1.8pF, which eliminates effects on signal integrity from disconnected terminators at interim points on the bus.
The UCC5606 can be programmed for either a 110 ohm or 2.5k ohm termination. The 110 ohm termination is used for standard SCSI bus lengths
and the 2.5k ohm termination is typically used in short bus applications.
When driving the TTL compatible DISCNCT pin directly, the 110 ohm termination is connected when the DISCNCT pin is driven high, and disconnected when low. When the DISCNCT pin is driven through an
impedance between 80k and 150k, the 2.5k ohm termination is connected when the DISCNCT pin is driven high, and disconnected when
driven low.
continued

BLOCK DIAGRAM
TRMPWR
2.7V·S.2SV

REG

r--------{}---------------------I
I
I
I
I
I
I

O.2V Dropout
Source/Sink
Power Driver

----------l

+-_-o-+<~

LINE1

I
I
I

$-6u,,,
Logic Level
0

I
I
I

1

Rd TRMPWR > 3V

Drop Out Voltage

All Termination Lines = 0.2V

3-32

2.5

UCC5606

ELECTRICAL CHARACTERISTICS (cont") Unless otherwise stated, these specifications apply for TA=O°C to 70·C.
TRMPWR = 3 3V, DISCNCT = 3 3V, RDISCNCT = 0 ohms TA = TJ
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX IUNITS

Regulator Section (cont.)
Short Circuit Current

VREG=OV

-200

-400

-800

mA

Sinking Current Capability

VREG = 3V

200

400

800

mA

Thermal Shutdown

(Note 2)

170

°C

Thermal Shutdown Hysteresis

(Note 2)

10

°C

Disconnect Section
Disconnect Threshold

RDISCNCT = 0 & 80k

Input Current

DISCNCT = 3.3V

0.8

1.5

2.0

30

50

V

I~

Note 1: Measuring each termination line while other 8 are low (0.2V).
Note 2: Guaranteed by design. Not 100% tested in production.

APPLICATION INFORMATION
Termpwr

.JGND for
Rd
Interim Points _-+--+-J\NV-l DISCNCT
TRMPWR
on the Bus
(Disconnect)
UCC5606
REG

To Drivers
and Receivers

,,-.~'.~.~.

Termpwr
4.7~F

TRMPWR
UCC5606

REG

_..~.~._.~
..~._.~
..~._.~
..~._.~
..~._.~.~
..~.~.~
..~.~._..~.~._.~
..;._.j-'.~._.~
••~._.~
••~._.~.~
••~.~.~
••~.~._••~.~._.~
••~._.~
••~._.~
••~._.~.~
••~.~.~
••~'~.--,'

To SCSI Bus

UDG-94066

Figure 1: Typical SCSI Bus Configurations Utilizing 2 UCC5606 Devices

Termpwr

I

GND for
Rd
_
Interim Points _ " ' -.......WV-lDISCNCT
on the Bus
(Disconnect)
UCC5606

L1

I

con;r:1

!~d D~i::~~yers

Termpwr

I
REG - - ,
L9

~,ts I

Rd

l4-

TRMPWR -

,k4.7I'F

1

.r=

I

_
DISCNCT

TRMPWR

r-

REG

h

UCC5606
L1

I

L9
D:ta" :its

I

Rd

l4-

,k4.7I'F

I1

.r=

_
DISCNCT

UCC5606
L1

I

TRMPWR
REG
L9

Da"ta"

:itS I

f--

h
I

,k4.7I'F

1

I:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:1

~

To SCSI Bus
UDG-94069

Figure 2: Typical Wide SCSI Bus Configurations Utilizing 3 UCC5606 Devices"
UNITRODE CORPORATION
7 CONTINENTAL BLVD. " MERRIMACK, NH 03054
TEL. (603) 424-2410" FAX (603) 424-3460

3-33

~UNITRDDE

UC5607

Plug and Play, 18-Line SCSI Active Terminator
FEATURES

DESCRIPTION

• Complies with SCSI and SCSI-2
Standards

The UC5607 provides 18 lines of active termination for a SCSI (Small
Computer Systems Interface} parallel bus. The SCSI standard recommends active termination at both ends of the cable segment.

• 8pF Channel Capacitance during
Disconnect

The UC5607 provides a low disconnect feature which will disconnect all
terminating resistors, and will disable the regulator, greatly reducing
standby power. The output channels remain high impedance even without
Termpwr applied.

• SCSI Plug and Play, Dual Low
Disconnect, Logic Low Command
Disconnects All Termination Lines
• Meets SCSI Hot Plugging Capability

The UC5607 terminator is specially designed with two disconnect pins for
full SCSI Plug and Play (PnP) applications.

• -650mA Sourcing Current for
Termination

Custom power packages are utilized to allow normal operation at full
power conditions (2 Watts).

• +200mA Sinking Current for Active
Negation
• 200~ Supply Current in Disconnect
Mode

Internal circuit trimming is utilized, first to trim the impedance to a 7% tolerance, and then most importantly, to trim the output current to a 7% tolerance, as close to the max SCSI spec as possible, which maximizes noise
margin in fast SCSI operation.

• Trimmed Termination Current to 7%

Other features include thermal shutdown and current limit.

• Trimmed Impedance to 7%

This device is offered in low thermal resistance versions of the industry
standard 28 pin wide body SOIC, and 28 pin PLCC, as well as 24 pin DIP.

• Provides Active Termination for 18
Lines

BLOCK DIAGRAM
TRMPWR
4.0V-5.25V

,----

REG

------------------------

I
I
I
I
I
I
I

------,

1100
I
.--................~~ LINE1

I
I
I
I
I

I

I

~~~~
-v~-r-y

DISCNCT2
(High=
Connect)

I
I
I
I
I
I
I
I
I
I
I
I
I
I
'00
L....c,..--;;~ LlNE18

TRMPWR

1.5V/1.4Vot--+--I

DISCNCTI
(High=
Connect)

LlNE2

Switch
Control

Disconnect
Comparator

L ____________________________________

I
:

~J
GND

Circuit Design Patented

7/98

DISCNCT1
DISCNCT2

Connect Connect Connect
1
0
1
0

3-34

Disc
0
0

UDG·94124

UC5607

CONNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS
Termpwr Voltage ................................. +7V
Signal Line Voltage .......................... OV to +7V
Regulator Output Current ........................... 1A
Storage Temperature ................... -65°C to + 150°C
Operating Temperature .............•... -55°C to +150°C
Lead Temperature (Soldering, 10 Sec.) ............. +300°C

PLCC-28 (Top View)
QP Package
TRMPWR----~
REG---~

LlNE9
LlNE8

LlNE10
LlNE11

Unless otherwise specified all voltages are with respect to
Ground. Currents are positive into, negative out of the specified
terminal. Consult Packaging Section of Unitrode Integrated
Circuits databook for thermal limitations and considerations of
packages.

RECOMMENDED OPERATING CONDITIONS
Termpwr Voltage ......................... 3.8V to 5.25V
Signal Line Voltage .......................... OV to +5V
Disconnect Input Voltage .................. OV to Termpwr

LlNE7

LlNE12

5

25

LlNE6

LlNE13

6

24

LlNE5

LlNE14

7

23

LlNE4

LlNE15

8

22

LlNE3

LlNE16

9

21

LlNE2

LlNE17

10

20

LlNE1

LlNE18

11

OlSCNCT1"

GNO'

GNO'

GNO'
GNO'-----'

GNO'
GNO'
GNO'

• QP package pins 12 - 18 seNe as both heatsink and signal
ground.

SOIC-28 (Top View)
DWP Package

•• DISCNCT2 is internally tied to ground.

DIL-24 (Top View)
N or J Package

• DWP package pin 8 seNes as signal ground; pins 7, 8, 9, 20,
21,22 seNe as heatsink/ground.

Note: Drawings are not to scale.

3-35

UC5607

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications applyforTA = O·Cto 70·C:
TRMPWR = 4 75V, DISCNCT1 = DISCNCT2 = 2 2V. TIA= T
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Supply Current Section
Termpwr Supply Current

All termination lines = Open
All termination lines = 0.5V
DISCNCT1 = DISCNCT2 = OV

Power Down Mode
Output Section (Terminator Lines
Terminator Impedance
alLINE = -5mA to -15mA

TJ.=25·C
O·C -lil--:D-I-SC-N-'C-T-,-T-R-M-P-W-R"r-

'="

.r-

UC5612

.

/1 ...

"L

r

~h

Control Blts,l

!~d D~~:~~yars

I

Termpwr

L

DlSCNCT

TRMPWR

UC5612

r-L

~h.

.1. 4.7~F
:SCNCT

12.2~F ~L.........T-111_--=L9.,.-J
II f·2~F ~L1
=

Data Bits

=

TRMPWRr-

UC5612

~h

.. .L19 I 12.2~F
Data Bits

=

I:,:,:,:,:,:,:,:,:,:,:, ~ .:.:.:.:.:.:.:.:.:.:.:.:.:.:::::::.:::.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.~ .:.:.:.:.:.:.:.:.:1

~

To SCSI Bus
UDG·94135

Figure 2: Typical Wide SCSI Bus Configurations Utilizing 3 UC5612 Devices.

UNITRODE CORPORATION
7 CONTINENTAL BLVD, • MERRIMACK. NH 03054
TEL, (603) 424-2410. FAX (603) 424-3460

3-46

~UNITRODE

UC5613

9-Line Low Capacitance SCSI Active Terminator
FEATURES

DESCRIPTION

•

Complies with SCSI, SCSI-2 and
SPI-2 Standards

•

3pF Channel Capacitance during
Disconnect

The UC5613 provides 9 lines of active termination for a SCSI (Small Computer Systems Interface) parallel bus. The SCSI standard recommends active termination at both ends of the cable segment.

•

1OO~ Supply Current in
Disconnect Mode

•
•

Meets SCSI Hot Plugging Capability
-400mA Sourcing Current for
Termination

•

+400mA Sinking Current for Active
Negation

•

Logic Command Disconnects all
Termination Lines

•
•
•

Trimmed Termination Current to 5%
Trimmed Impedance to 5%
Current Limit and Thermal
Shutdown Protection

The UC5613 provides a disconnect feature which, when opened or driven
high, disconnects all terminating resistors and disables the regulator
greatly reducing standby power. The output channels remain high impedance even without Termpwr applied. A low channel capacitance of 3pF allows units at interim points of the bus to have little or no effect on the signal
integrity.
The UC5613 is pin-for-pin compatible with its predecessor, the UC5603 - 9
line Active Terminator. The only functional difference between the UC5613
and UC5603 is the absence of the negative clamps. Parametrically, the
UC5613 has a 5% tolerance on impedance and current compared to a 3%
tolerance on the UC5603. Custom power packages are utilized to allow
normal operation at full power (1.2 watts).
Internal circuit trimming is utilized, first to trim the impedance to a 5% tolerance; then, the output current is trimmed to a 5% tolerance. The output
current trim is set as close as possible to the maximum value of the SCSI
specification which maximizes the noise margin for fast SCSI operation.
Other features include thermal shutdown and current limit.
This device is offered in low thermal resistance versions of the industry
standard 16 pin narrow body SOIC, 16 pin ZIP (zig-zag in line package),
and 24 pin TSSOP.

BLOCK DIAGRAM
TRMPWR
4.0V-S.2SV

REG

lion
LlNEI

l.S/1.3V

lion
LlNE2
Disconnect
Comparator

I
I
I
I
I
I

I

lion

L.".--C;o.----JI/II',----l
Switch
Control

GND

3197

DISCNCT
(Low = Connect)

LlNE9

UDG-94003-1

Circuit Design Patented

3-47

UC5613
ABSOLUTE MAXIMUM RATINGS
Tennpwr Voltage ................................................... +7V
Signal Line Voltage ...................................... ',' ..... OV to +7V
Regulator Output Current ...................................... : . . . .. O.5A
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°C to +150°C
Operating Temperature ................................... -55OC to +150°C
Lead Temperature (Soldering, 10 Sec.) ............................... +300°C
Unless otherwise specified all voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of Unitrode Integrated Circuits databook for thermallimitations and considerations of packages.
'

RECOMMENDED OPERATING CONDITIONS
Tennpwr Voltage ................... , ....................... 3.BV to S.25V
Signal Line Voltage, , ...................................... , .... OV to +5V
Disconnect Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OV to Termpwr

CONNECTION DIAGRAMS
TSSOP·24 (Top View)
PWPPackage

DIL·16 (Top View)
N or J Package
LlNE6
LlNE5

REG
N/C
N/C

LINE4

• PWP package pin 5 serves as signal ground; pins 6, 7,8, 9,
17, 18, 19, and 20 serve as heatsinklground.

SOIC-16 (Top View)
DP Package

Zlp·16 (Top View)
Z Package

TRMPWR
L1NE4
L1NE3
L1NE2
L1NE1

DISCNCT
SGND
SGND
SGND
SGND
L1NE9
LINES
L1NE7
L1NE6
L1NE5

u-____~~_----REG
• DP package pin 5 serves as signal ground; pins 4, 12, 13
serve as heatsinklground.
Note: Drawings are not to scale.

3-48

UC5613
ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply forTA =O°C to 70°C.
TRMPWR = 4.75V, DISCNCT = OV. TA = TJ.
PARAMETER
Supply Current Section
Termpwr Supply Current

TEST CONDITIONS

MIN

All termination lines = Open
All termination lines = 0.5V
DISCNCT = Open

Power Down Mode
Output Section (Terminator Lines
Terminator Impedance
illLiNE = -5mA to -15mA
Output High Voltage
TRMPWR = 4V (Note 1)
Max Output Current
VLINE = 0.5V
Max Output Current

Output Leakage

Output Capacitance
Regulator Section
Regulator Output Voltage
Regulator Output Voltage
Line Regulation
Load Regulation
Drop Out Voltage
Short Circuit Current
Sinking Current Capability
Thermal Shutdown
Thermal Shutdown Hysteresis
Disconnect Section
Disconnect Threshold
Threshold Hysteresis

TJ = 25°C
O°C < TJ < 70°C
VLlNE = 0.5V, TRMPWR = 4V (Note 1)
TJ = 25°C
O°C < TJ < 70°C
VLlNE = 0.2V, TRMPWR = 4V to 5.25V
O°C < TJ < 70°C
TRMPWR
=
OV
to
5.25V
VLlNE
= 0 to 4V
DISCNCT=4V
REG =OV
VLlNE = 5.25V
TRMPWR = OV to 5.25V, REG = Open
VLlNE = OV to 5.25V
DISCNCT = Open, DP Package (Note 2)

104.5
2.7
-20.3
-19.8
-19.5
-19.0
-21.6

2.8
2.8

All Termination Lines = 5V
TRMPWR = 4V to 6V
IREG = +100mA to -100mA
All Termination Lines = 0.5V
VREG =OV
VREG =3.5V

-200
200

1.3
100

TYP

MAX IUNITS

17
200
100

23
225
150

mA
mA

110
2.9
-21.5
-21.5
-21.5
-21.5
-24.0
10

115.5

Ohms
V
mA
mA
mA
mA
mA
nA

uA

10

-22.4
-22.4
-22.4
-22.4
-25.4
400
100
400

3

4.5

pF

2.9
2.9
10
20
0.7
-400
400
170
10

3
3
20
50
1
-600
600

V
V
mV
mV
V
mA
mA
°C
°C

1.5
160

1.7
250

V
mV

ItA
nA

Note 1: Measuring each termination line while other 8 are low (0.5V).
Note 2: Guaranteed by deSign. Not 100% tested in production.

APPLICATION INFORMATION
Termpwr

Termpwr
*4.7 JLF

r---~-i DISCNCT

DISCNCT

TRMPWR

UC5613

UC5613
REG

To Drivers
and Receivers

TRMPWR

REG

-l-

2.2JLF

"--'-~~~~~~~~~~~~;-r~~~~~~~~~~'~
..~.~
.. ~
..~.~,'~,'-"-',

To SCSI Bus

Figure 1: Typical SCSI Bus Configurations Utilizing 2 UC5613 DeYices

3-49

UDG-94007-1

UC5613

APPLICATION INFORMATION (cont.)

,
Termpwr

.-_. . 11---1 DISCNCT

l,f'

TRMPWR-

UC5613
REG ---,

I ...

L1 '

L9.

I

Conl,ol" Biisl

,k2.2I'F

I

=

Termpwr

L~
DISCNCT

..r:=

L

TRMPWR

REG ---,
L9.

,k2.2I'F

I ... I I
Data Bits

4.71lF

:SCNCT

UC5613
Ll

.1:

-=

..r:=

TRMPWR-

I ... r .1

UC5613

REG ---,

L1

22
. 1'F

Dala Bits

=

:~d ~~~:~~vers ~:.: '. : . : . : . : . : .,: : : : : : : . : . : . : . : . : . : . : . : . : : : . : . : . : . : . : . : . : . : : : : : : : . : . : . : . : . : . : . : . : . : . : . : . : . : . : . : . : . : . : . : . : . : . : . : ": . : . : : : . : . : . :1

~

To SCSI Bus
UDG-94008-1

Figure 2: Typical Wide SCSI Bus Configurations Utilizing 3 UC5613 Devices.

UNITRODE CORPORATION
7 CONTINENTAL BLVD .• MERRIMACK, NH 03054
TEL. (603) 424-2410. FAX (603) 424-3400

3-50

~UNITRODE

UCC5614

9-Line 3-5 Volt Low Capacitance SCSI Active Terminator
FEATURES

DESCRIPTION

•

Complies with SCSI, SCSI-2 and
SCSI-3 Standards

•
•

2.7V to 7V Operation

The UCC5614 provides 9 lines of active termination for a SCSI (Small
Computer Systems Interface) parallel bus. The SCSI standard recommends active termination at both ends of the cable.

•

0.5!JA Supply Current in Disconnect
Mode

•

110 Ohm/2.5k Programmable
Termination

•
•

Completely Meets SCSI Hot Plugging

The UCC5614 is ideal for high performance 3.3V SCSI systems. The key
features contributing to such low operating voltage are the 0.1 V drop out
regulator and the 2.7V reference. The reduced reference voltage was
necessary to accommodate the lower termination. current dictated in the
SCSI-3 specification. During disconnect the supply current is typically
only 0.5!JA, which makes the IC attractive for battery powered systems.

1.8pF Channel Capacitance during
Disconnect

-400mA Sourcing Current for
Termination

•

+400mA Sinking Current for Active
Negation Drivers

•

Trimmed Termination Current to 4%

•

Trimmed Impedance to 7%

•

Current Limit and Thermal Shutdown
Protection

The UCC5614 is designed with an ultra low channel capacitance of
1.8pF, which eliminates effects on signal integrity from disconnected terminators at interim points on the bus.
The UCC5614 can be programmed for either a 110 ohm or 2.5k ohm termination. The 110 ohm termination is used for standard SCSI bus lengths
and the 2.5k ohm termination is typically used in short bus applications.
When driving the TTL compatible DISCNCT pin directly, the 110 ohm termination is connected when the DISCNCT pin is driven low, and disconnected when driven high. When the DISCNCT pin is driven through an
impedance between 80k and 150k, the 2.5k ohm termination is connected when the DISCNCT pin is driven low, and disconnected when
continued
driven high.

BLOCK DIAGRAM
TRMPWR
2.7V·S.2SV

REG

110

LlNE1

O.2V Dropout
Source/Sink
Power Driver
DISCNCT

LlNE2

I
I
I

logic Level 1
0

1

Rd TRMPWR > 3V

Drop Out Voltage

All Termination Lines = 0.2V

Short Circuit Current

VREG=OV

2.5
-200

3-53

2.7

3.0

0.1

0.2

V

-400

-800

mA

UCC5614
ELECTRICAL CHARACTERISTICS (cont.) Unless otherwise stated, these specifications apply for TA = O°C to 70°C.
TRMPWR = 3.3V, DISCNCT = OV, ROISCNCT= 0 ohms. TA = TJ.
PARAMETER
Regulator Section (cont.)

TEST CONDITIONS

MIN

TYP

MAX UNITS

200

400

BOO

Sinking Current Capability

VREG = 3V

Thermal Shutdown

(Note 2)

170

°C

Thermal Shutdown Hysteresis

(Note 2)

10

°C

Disconnect SeCtion
Disconnect Threshold

ROISCNCT = 0 & BOk
Input Current
DISCNCT=OV
Note 1: Measuring each termination line while other 8 are low (O.2V).
Note 2: Guaranteed by design. Not 100% tested in production.

O.B

rnA

1.5

2.0

V

30

50

ItA

APPLICATION INFORMATION
Termpwr

Termpwr

.f. 4.71LF
Rd

.--~-'IIItv-I

OISCNCT

TRMPWR

UCC5614

TRMPWR
UCC5614

REG

REG

J-

4.71L F

To Drivers
and Receivers ....~
..-.~
..~.~
..~.~
..~.~
..~.~
..~.-.~
..~.~
..~.~
..~...~.~.~
..-.~
..~.~
..~.;..-t.~
..~.~.~
.._.~
..~.~
..~.~
..~.~
..~.~..~._.~
..~.~
..~.~
..~._..~.~.~
.._.~
..~.~
..~.",-,
..

To SCSI Bus
Figure 1: ~pical SCSI Bus Configurations Utilizing 2 UCC5614 Devices

Termpwr

I

Rd

.J..

DISCNCT

~

TRMPWR _

DISCNCT

TRMPWR

REG 1 4
UCC5614
REG
••• L9
4.7j.LF ~
L1
• • • L9

UCC5614

Ll

I

Control Bit·l.....

!~d D~~:~~vers

k

Termpwr

I

Data Bits

I

14

4.7j.L F

=

k
.r
-

14

DISCNCT

TRMPWR _

UCC5614

REG
L9

L1

I

D:t:

~ts

I ...

4.7j.LF

I:··:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:".:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:. :1

~

To SCSI Bus
Figure 2: Typical Wide SCSI Bus Configurations Utilizing 3 UCC5614 Devices.
UNITRODE CORPORATION

7 CONTINENTAL BLVD.• MERRIMACK, NH 03054
TEL. (603) 424·2410. FAX (603) 424-3460

3-54

~UNITROOE

UCC5617

18-Line SCSI Terminator (Reverse Disconnect)
FEATURES

DESCRIPTION

• Complies with SCSI, SCSI-2, SCSI-3,
SPI and FAST-20 Standards

The UCC5617 provides 18 lines of active termination for a SCSI (Small
Computers Systems Interface) parallel bus. The SCSI standard recommends and Fast-20 (Ultra) requires active termination at both ends of the
cable.

• 2pF Channel Capacitance During
Disconnect
• 50mA Supply Current in Disconnect
Mode
• 110n Termination
• SCSI Hot Plugging Compliant, 10nA
Typical
• +400mA Sinking Current for Active
Negation
• -650mA Sourcing Current for
Termination
• Trimmed Impedance to 5%
• Thermal Shutdown

Pin for pin compatible with the UC5609, the UCC5617 is ideal for high performance 5V SCSI systems, Termpwr 4.0-5.25V. During disconnect the
supply current is only 50~A typical, which makes the IC attractive for lower
powered systems.
The UCC5617 is designed with a low channel capacitance of 2pF, which
eliminates effects on signal integrity from disconnected terminators at interim points on the bus.
The power amplifier output stage allows the UCC5617 to source full termination current and sink active negation current when all termination lines
are actively negated.
The UCC5617, as with all Unitrode terminators, is completely hot pluggable
and appears as high impedance at the terminating channels with
TRMPWR=OV or open.
Internal circuit trimming is utilized, first to trim the 110n impedance, and
then most importantly, to trim the output current as close to the maximum
SCSI-3 specification as possible, which maximizes noise margin in fast
SCSI operation.

• Current Limit

This device is offered in low thermal resistance versions of the industry
standard 28 pin wide body SOIC, TSSOP and PLCC.

BLOCK DIAGRAM

REG

r-------------------------------

TRMPWR

Q

--------l
1
1
1

1

1

. 1~~? ,-l,
r--,......+-~~~ LINE1

1
1

GND~

1

I

1"'=

1

SOURCE/SINK
POWER DRIVER

1
1

1

1

1

1

1

110n

DISCNCT
(HIGH=CONNECT)

1

0-9LINE2

1
1

DISCONNECT
COMPARATOR

1
1

1

:

1

1

1

1

1

I:

I
~~?~
!......"..--~vvv---y
SWITCH
~______________________
C_O_NT_R_O~L

LlNE18

:
1

_________________________________________ J

UDG·96073

Patented Circuit Design

4197
3-55

UCC5617

ABSOLUTE MAXIMUM RATINGS
TEMPWR. ...................................... +7V
Signal Line Voltage .......................... OV to +7V
Regulator Output Current ........................... 1A
Storage Temperature ................... -65°C to +150°C
Operating Junction Temperature .......... -55°C to +150°C
Lead Temperature (Soldering, 10 Seconds) .......... 300°C
All currents are positive into, negative out of the specified
terminal. Consult Packaging Section of Databook for thermal
limitations and considerations of packages.

CONNECTION DIAGRAMS
PLCC-28 (Top View)
QP Package

TSSOP-28 (Top View)
PWP Package

TRMPWR---------,
REGi--------,

LINES 1

LlNE9
LINE8
LlNE7

LlNE10
LINE11

0

LlNE8 4
LINE12
LINE13
LlNE14
LINE15
LlNE16
LINE17
LlNE18

5
6
7
8
9
10
11

25
24
23
22
21
20

LlNE9 5

LINE6
LlNE5
LINE4
LlNE3
LlNE2
LlNE1
DISCNCT

TRMPWR 6
GND' 7

LlNE18
LlNE17

GND"
GND'
GND'

GND"
GND"
GND"
GND"

LlNE16
LlNE1S
LlNE14

• DWP package pins 12 - 18 serve as both heatsink and signal
ground.

• PWP package pin 23 serves as signal ground; pins 7, 8, 9,
20,21, and 22 serve as heatsink ground.

DIL-24 (Top View)
N Package

Note: Drawings are not to scale.

SOIC-28 (Top View)
DWP Package

• DWP package pin 28 serves as signal ground; pins 7, 8, 9,
20,21,22 serve as heatsinklground.

3-56

UCC5617

ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications apply for TA = O°C to 70°C,
TRMPWR - 4 75V DISCNCT - OV TA - TJ
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Supply Current Section
TERMPWR Supply Current
Power Down Mode

All Termination Lines = Open

1

2

rnA

All Termination Lines = 0.2V

420

440

rnA

DISCNCT=OV

50

100

/.LA

0

Output Section (Termination Lines)
Termination Impedance

(Note 3)

104.5

110

115.5

Output High Voltage

VTRMPWR = 4V (Note 1)

2.6

2.8

3

V

Max Output Current

VUNE = 0.2V, TJ = 25°C

-22.1

-23.3

-24

rnA

VUNE=0.2V

-20.7

-23.3

-24

rnA

VUNE = 0.2V, TERMPWR = 4V, TJ = 25°C
(Note 1)

-21

-23.3

-24

rnA

VLINE = 0.2V, TRMPWR = 4V (Note 1)

-20

-23

VUNE = 0.5V

-24

rnA

-22.4

rnA

Output Leakage

DISCNCT = 2.4V, TRMPWR = OV to 5.25V,
REG = 0.2V, VUNE = 5.25V

10

400

nA

Output Capacitance

DISCNCT = 2.4V (Note 2)

2

3.5

pF

2.8

3

V

0.4

0.8

V

-475

-650

-850

rnA

200

400

800

rnA

Regulator Section
2.6

Regulator Output Voltage
Drop Out Voltage

All Termination Lines = 0.2V

Short Circuit Current

VREG= OV

Sinking Current Capability

VREG= 3.5V

Thermal Shutdown

170

°C

Thermal Shutdown Hysteresis

10

°C

Disconnect Section
0.8

Disconnect Threshold
Input Current

DISCNCT=OV

1.5

2

V

-10

-30

/.LA

Note 1: Measuring each termination line while other 17 are low (0.2V).
Note 2: Guaranteed by design. Not 100% tested in production.
Note 3: Tested by measuring lOUT with VOUT= 0.2Vand VOUTwith no load, then calculating: Z = VOUT N.L-0.2V
IOuTatO.2V

PIN DESCRIPTIONS
DISCNCT: Taking this pin low causes the 18 channels to
become high impedance and the chip to go into
low-power mode; a high or open state allows the
channels to provide normal termination.

GND: Ground reference for the IC.

LINE1-LlNE18: 1100 termination channels.
REG: Output of the internal 2.8V regulator.
TRMPWR: Power for the IC.

3-57

UCC5617

Procedure:

1) Measure VREG N.L.
2) Set VL

=O.2V

3) Measure IMAX at O.2V
4)

Impedance

VREG N.L-02V

r-----------l

J,

.f.4.711F
I

14.75V

"'='"

IMAX

UCC5617

l:r-+-~----""1I,","·------i~. TERMPWR
+0
VREG

14.711F

--b.

$

!::i.

VL

I

i

DSCNCT

-=-2.4V I

-J-

~ ...
i"'='"

REG

I

~

"'='"

LfNEl

I

TYPICAL TERMLINE
CONNECTION
.
IMAX

GND

L ____

I

~-----1

UDG-96108

Figure 1. Termline Impedance Measurement Circuit

APPLICATION INFORMATION

Termpwr
DISCNCT

TRMPWR

.f. 4.711F

UCC5617
GND
Ll

REG

...

L18

J.

4.711 F

CONTROL BITS
DATA BITS
TO DRIVERS
AND RECEIVERS ,,--'.~.~._
..~.~._.~
..~._.~
..~._.~
..~._.~
..~._.~
..~._."".:~._.~
..""._.~.~
.._';-'-;''r-'~.~'.~.~.~
..~.~.~..~.~.~.~.~.~.~. ....J.

TO SCSI BUS

UNITRODE CORPORATION
7 CONTINENTAL BLVD.• MERRIMACK, NH 03054
TEL. (603) 424-2410' FAX (603) 424-3460

3-58

UDG·96074

~UNITROCE

UCC5618

18-Line SCSI Terminator
FEATURES

DESCRIPTION

• Complies with SCSI, SCSI-2, SCSI-3,
SPI and FAST-20 Standards

The UCC5618 provides 18 lines of active termination for a SCSI (Small
Computers Systems Interface) parallel bus. The SCSI standard recommends and Fast-20 (Ultra) requires active termination at both ends of the
cable.

• 2pF Channel Capacitance During
Disconnect
• 50llA Supply Current in Disconnect
Mode
• 110n Termination
• SCSI Hot Plugging Compliant, 10nA
Typical
• +400mA Sinking Current for Active
Negation
• -650mA Sourcing Current for
Termination

Pin for pin compatible with the UC5601 and UC5608, the UCC5618 is ideal
for high performance 5V SCSI systems, Termpwr 4.0-5.25V. During disconnect the supply current is only 50llA typical, which makes the IC attractive for lower powered systems.
The UCC5618 is designed with a low channel capacitance of 2pF, which
eliminates effects on signal integrity from disconnected terminators at interim points on the bus.
The power amplifier output stage allows the UCC5618 to source full termination current and sink active negation current when all termination lines
are actively negated.
The UCC5618, as with all Unitrode terminators, is completely hot pluggable
and appears as high impedance at the terminating channels with
TRMPWR=OV or open.

• Trimmed Impedance to 5%
• Thermal Shutdown

Internal circuit trimming is utilized, first to trim the 110n impedance, and
then most importantly, to trim the output current as close to the max
SCSI-3 spec as possible, which maximizes noise margin in fast SCSI operation.

• Current Limit

This device is offered in low thermal resistance versions of the industry
standard 28 pin wide body SOIC, TSSOP and PLCC.

BLOCK DIAGRAM

REG

r-------------------------------

TRMPWR

Q

I
I
I
I
I
I

I
I
I
I
I

GND

110!l

,-L,

.-.-->--...-0-- <>--'INIr--1.., LINE 1

¢-=L
I
I
I
I
I

--------l

""""

I
I
I
I
I

SOURCE/SINK
POWER DRIVER

I
110!l

I

I
I

I
I

:
I

I
I

~LINE2

DISCNCT
(LOW=CONNECT)
DISCONNECT
COMPARATOR

I
I

I
I

I:

~1~~?~ LlNE18

~ ~vvv--c.r
SWITCH

~____________________C_O_N_T_RO_L~

:

I

L _________________________________________ J

UDG·96005·1

Patented Circuit Design

6/98

3-59

UCC5618

ABSOLUTE MAXIMUM RATINGS
TEMPWR. ...................................... +7V
Signal Line Voltage .......................... OV to +7V
Regulator Output Current ........................... 1A
Storage Temperature ................... -65°C to + 150°C
Operating Junction Temperature ....... , .. -55°C to +150°C
Lead Temperature (Soldering, 10 Seconds) .......... 300°C

All currents are positive into, negative out of the specified
terminal. Consult Packaging Section of Databook for thermal
limitations and considerations of packages.

CONNECTION DIAGRAMS
PLCC-28 (Top View)
QP Package

TSSOP-28 (Top View)
PWP Package

TRMPWR;-----,
REGi------,

LlNE5 1

LINE9
LlNE8
LINE7

LlNE10
LINE11

0

LlNE8 4
LlNE12
LlNE13
LlNE14
LINE15
LlNE16
LINE17
LlNE18

5
6
7
8
9
10
11

25
24
23
22
21
20

LlNE9 5

LlNE6
LINES
LINE4
LlNE3
LINE2
LlNE1
OISCNCT

TRMPWR 6

GNO'

7

LlNE18
LlNE17

GNO'
GNO'
GNO'

GNO'
GNO'
GNO'
GNO'

• DWP package pins 12-18 serve as both heatsink and signal
ground.

LlNE16
LlNE15
LlNE14'

• PWP package pin 23 serves as signal ground; pins 7, 8, 9,
20, 21, and 22 serve as heatsink ground.

DIL-24 (Top View)
N Package

Note: Drawings are not to scale.

SOIC-28 (Top View)
DWP Package

• DWP package pin 28 serves as signal ground; pins 7, 8, 9,
20, 21, 22 serve as heatsink/ground.

3-60

UCC5618

ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications apply for TA = O°C to 70°C,
TRMPWR - 475V, DISCNCT - OV, TA - TJ
PARAMETER

TEST CONDITIONS

MIN

TVP

MAX

UNITS

Supply Current Section
TERMPWR Supply Current
Power Down Mode

All Termination Lines = Open

1

2

mA

All Termination Lines = 0.2V

420

440

mA

DISCNCT = TRMPWR

50

100

J.I.A

n

Output Section (Termination Lines)
Termination Impedance

See Figure 1

104.5

110

115.5

Output High Voltage

VTRMPWR = 4V (Note 1)

2.6

2.8

3

V

Max Output Current

VUNE = 0.2V, TJ = 25°C

-22.1

-23.3

-24

rnA

VUNE = 0.2V

-20.7

-23.3

-24

mA

VUNE = 0.2V, TERMPWR = 4V, TJ = 25°C
(Note 1)

-21

-23.3

-24

mA

VUNE = 0.2V, TRMPWR = 4V (Note 1)

-20

-23

VUNE = 0.5V

-24

mA

-22.4

mA

Output Leakage

DISCNCT = 2.4V, TRMPWR = OV to 5.25V,
REG = 0.2V, VUNE = 5.25V

10

400

nA

Output Capacitance

DISCNCT = 2.4V (Note 2)

2

3.5

pF
V

Regulator Section
Regulator Output Voltage

2.6

Drop Out Voltage

All Termination Lines = 0.2V

Short Circuit Current

VREG= OV

Sinking Current Capability

VREG= 3.5V

2.8

3

0.4

0.8

V

-475

--650

-950

mA

200

400

800

mA

Thermal Shutdown

170

°C

Thermal Shutdown Hysteresis

10

°C

Disconnect Section
Disconnect Threshold
Input Current

0.8
DISCNCT=OV

1.5

2

V

-10

-30

J.I.A

Note 1: Measuring each termination line while other 17 are low (0.2V).
Note 2: Guaranteed by design. Not 100% tested in production.

Procedure:
1) Measure VREG N.L.

2) Set VL = O.2V
3) Measure IMAX at O.2V

VREG N.L.-02V
4) Impe dance = --'-'=-:----I MAX

n·

, - ----------l

$

UCC5618

r----------1Ir-----I12 TERMPWR

1+

14.75v

~

+0
VREG

--%-

.f-4.711F
I
I4.711F

~

~

I MAX

LlNE1

I

I

i

$REG
I

rl
I

TYPICAL TERMLINE
CONNECTION

VL

~

I
DSCNCT

L ____

-y ____
GND

i
I

-.l

UDG·96102-1

Figure 1. Termline Impedance Measurement Circuit

3-61

UCC5618

PIN DESCRIPTIONS
DISCNCT: Taking this pin high or leaving it open causes
the 18 channels to become high impedance and the chip
to go into low-power mode; a low state allows the
channels to provide normal termination.

GND: Ground reference for the IC.
LINE1-LINE18: 11 on termination channels.
REG:

Outpu~

of the internal 2.8V regulator.

TRMPWR: Power for the IC.

APPLICATION INFORMATION
UCC5618

....-----1 DISCNCT

r--

TRMPWR I--_T_e_rm_p_w_r_ _~_---...,

GND

REG

I

.lL....=L,;.1_ _ _ _.,L..;c18:.......J

i

i

4.71l F

4.71lF

Control Bits
Data Bits

:~d D~~:~~vers

I::::::::::::::::::::::' :::::::::::::::::::.:.:::::::::::::.::::::::::l .

JJ

To SCSI Bus

UNITRODE CORPORATION

7 CONTINENTAL BLVD.• MERRIMACK, NH 03054
TEL. (603) 424-2410' FAX (603) 424-3460

3-62

UDG-96012-1

~UNITRODE

UCC5619

27-Line SCSI Terminator With Reverse Disconnect
FEATURES

DESCRIPTION

• Complies with SCSI, SCSI-2, SCSI-3,
SPI and FAST-20 (Ultra) Standards

UCC5619 provides 27 lines of active termination for a SCSI (Small Computer Systems Interface) parallel bus. The SCSI standard recommends active termination at both ends of the cable.

• 2.5pF Channel Capacitance during
Disconnect

The UCC5619 is ideal for high performance 5V SCSI systems. During disconnect the supply current is typically only 100IlA, which makes the IC attractive for lower powered systems.

• 100llA Supply Current in Disconnect
Mode

The UCC5619 is designed with a low channel capacitance of 2.5pF, which
eliminates effects on signal integrity from disconnected terminators at interim points on the bus.

• 4V To 7V Operation
• 110n Termination
• Completely Meets SCSI Hot Plugging
• -900mA Sourcing Current for
Termination
• +500mA Sinking Current for Active
Negation
• Logic Command Disconnects all
Termination Lines
• Trimmed Impedance to 5%
• Current Limit and Thermal Shutdown
Protection

The power amplifier output stage allows the UCC5619 to source full termination current and sink active negation current when all termination lines
are actively negated.
The UCC5619, as with all Unitrode terminators, is completely hot pluggable
and appears as high impedance at the teminating channels with VTRMPWR
= OVoropen.
Internal circuit trimming is utilized, first to trim the 110n impedance, and
then most importantly, to trim the output current as close to the maximum
SCSI-3 specification as possible, which maximizes noise margin in fast
SCSI operation.
Other features include thermal shutdown and current limit. This device is
offered in low thermal resistance versions of the industry standard 36 pin
wide body OSSOP (MWP) and 48 pin LOFP (FOP).
Consult SSOP-36 (MWP OSSOP-36) and FOP-48 Packaging Diagram for
exact dimensions.

BLOCK DIAGRAM

REG

r-------------------------------

TRMPWR

9

--------l

I
I
I

I

I

I

I
I

I
I

110n ,.l,
r-,.......I--r--<'...-~ LlNEl

I

GND~

I
I

I"'='"
I

I

I
I
I

I

I
I

DISCNCT
(HIGH.CONNECT)

110n

I

I
I
:

I
I
I

I

I

~LlNE2
DISCONNECT
COMPARATOR

I

I
I

I:

I
~~?~
L...,...--vv~LlNE27

SWITCH
CONTROL

I

:

:

I

L _________________________________________ J

UDG·96108

Circuit Design Patented

10198

3-63

UCC5619

CONNECTION DIAGRAM

ABSOLUTE MAXIMUM RATINGS
TRMPWR Voltage ................................ +7V
Signal Line Voltage .......................... OV to +7V
Regulator Output Current. ......................... 1.5A
Storage Temperature ................... --65°C to + 150°C
Junction Temperature ................... -55°C to +150°C
Lead Temperature (Soldering, 10 Sec.) ............. +300°C
Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thelmallimitations and considerations of packages.

LFQP-48 (Top View)
FQP Package
HSfGND - - - - - - - - - ,
HSlGND - - - - - - - - - ,
LlNE9-------,
LlNE23----,
LlNE24---..,

HSlGND
,.-------LlNE8
,------LlNE7
,-----LlNE6
,----LlNE5
LINE 22

r-------~<

NIC

QSSOP-36 (Top View)
MWP Package
LINEa

1

LlNE7

LINES
LlNE5
UNE22
UNE21

LlNE27

7

UNE19

REG
GND*

NIC

GND*

LINE 13

LINE 15

LINE 4
LINE 3

LINE 12

DISCNCT

11

GND*
TRMPWR

LINE 14

LINE 2

HSfGND
HSfGND

HS/GND

LINE 1

LlNE18

LlNE17
LlNE16

LlNE1

LlNE4

• MWP package pins 8 - 10 and 26 - 28 serve as heatsinkl
ground.

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = O°C to 70°C,
TRMPWR = 475V , DISCNCT = 4 75V , T A = TJ
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Supply Current Section
TRMPWR Supply Current
Power Down Mode

All Termination Lines = Open

1

2

mA

All Termination Lines = 0.2V

630

650

mA

DISCNCT= OV

100

200

!!A

110

115.5

Q

Output Section (Termination Lines)
Termination Impedance

(Note 3)

104.5

Output High Voltage

(Note 1)

2.6

2.8

3.0

V

Max Output Current

VUNE = 0.2V, TJ = 25°C

-22.1

-23.3

-24

mA

VUNE= 0.2V

-20.7

-23.3

-24

mA

VUNE = 0.2V,TRMPWR = 4V, TJ = 25°C (Note 1)

-21

-23

-24

mA

VUNE = 0.2V, TRMPWR = 4V (Note 1)

-20

-23

-24

mA

UCC5619

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = O°C to 70°C,
TRMPWR - 475V , DISCNCT - 4 75V, TA -- TJ

-

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Output Section (CONT.)
22.4

mA

Output Leakage

DISCNCT = OV, TRMPWR = OV to 5.25V

10

400

nA

Output Capacitance

DISCNCT = OV (Note 2)

2.5

4

pF
V

VUNE= 0.5V

Regulator Section
Regulator Output Voltage

2.6

Drop Out Voltage

All Termination Lines = 0.2V

Short Circuit Current

VREG=OV

Sinking Current Capability

VREG= 3.5V

2.8

3.0

0.4

0.8

V

-650

-900

-1300

mA

300

500

900

mA

Thermal Shutdown

170

°C

Thermal Shutdown Hysteresis

10

°C

Disconnect Section
Disconnect Threshold

0.8

Input Current

DISCNCT=OV

1.5

2.0

V

-20

-60

!1A

PIN DESCRIPTIONS
DISCNCT: Taking this pin low causes all channels to
become high impedance, and the chip to go into
low-power mode; a high state or leaving it open allows
the channels to provide normal termination.

LlNE1 - LlNE27: 11 on termination channels.
REG: Output of the internal2.7V regulator; bypass with a
4.71lF capacitor to GND.
TRMPWR: Power for the IC; bypass with a 4.71lF
capacitor to GND.

GND: Ground reference for the IC.

r--------------------------,

:

11

UCC5619

DISCNCT

:

TERMPWR

TO SCSI BUS

Figure 1. Typical wide SCSI bus configuration using the UCC5619
UNITRODE CORPORATION
7 CONTINENTAL BLVD.' MERRIMACK. NH 03054
TEL. (603) 424·2410 FAX (603) 424·3460

3-65

UDG·98072

~UNITRODE

UCC5620
PRELIMINARY

27-Line SCSI Terminator
FEATURES

DESCRIPTION

• Complies with SCSI, SCSI-2, SCSI-3,
SPI and FAST-20 (Ultra) Standards

UCC5620 provides 27 lines of active termination for a SCSI (Small Computer Systems Interface) parallel bus. The SCSI standard recommends
active termination at both ends of the cable.

• 2.5pF Channel Capacitance during
Disconnect

The UCC5620 is ideal for high performance 5V SCSI systems. During
disconnect the supply current is typically only 100J.1A, which makes the IC
attractive for lower powered systems.

• 100mA Supply Current in Disconnect
Mode

The UCC5620 is designed with a low channel capacitance of 2.5pF,
which eliminates effects on signal integrity from disconnected terminators
at interim points on the bus.

• 4V To 7V Operation
• 1100 Termination
• Completely Meets SCSI Hot Plugging
• -900mA Sourcing Current for
Termination
• +500mA Sinking Current for Active
Negation
• Logic Command Disconnects all
Termination Lines
• Trimmed Impedance to 5%
• Current Limit and Thermal Shutdown
Protection

The power amplifier output stage allows the UCC5620 to source full termination current and sink active negation current when all termination
lines are actively negated.
The UCC5620, as with all Unitrode terminators, is completely hot pluggable and appears as high impedance at the teminating channels with
VTRMPWR = OV or open.
Internal circuit trimming is utilized, first to trim the 1100 impedance, and
then most importantly, to trim the output current as close to the maximum
SCSI-3 specification as possible, which maximizes noise margin in fast
SCSI operation.
Other features include thermal shutdown and current limit. This device is
offered in low thermal resistance versions of the industry standard 36-Pin
Wide Body OSOP (MWP) and 48-Pin LOFP (FOP).
Consult OSOP-36 or LOFP-48 packaging diagram for exact dimensions.

BLOCK DIAGRAM
REG

r-------------------------------

TRMPWR

Q

--------,
I

I
I

I

I

I

I
I

I

I

lIon

,.l,

,---,...........,..---<>--'IIII'r-1.. LlNEl

I

GND~

I
I

I"='"

I

I

I

I

lIon

I
I
I

I

I

I

I
DlSCNCT
(LOW=CONNECT)

~LlNE2
DISCONNECT
COMPARATOR

I

I

II
I

i

I
I

I:
-.21~?y.,
I

I

I......,..---_"v-y
_
I

iL ____________

~

__

.

~~

________________________

LlNE27

i
I

J

UDG·96109

Circuit Design Patented

10198

SWITCH
CONTROL

3-66

UCC5620

ABSOLUTE MAXIMUM RATINGS

CONNECTION DIAGRAM

Termpwr Voltage ................................. +7V
Signal Line Voltage .......................... OV to +7V
Regulator Output Current .......................... 1.5A
Storage Temperature ................... -65°C to + 150°C
Junction Temperature ................... -55°C to + 150°C
Lead Temperature (Soldering, 10 Sec.) ............. +300°C

Currents are positive into, negative out of the specified termi·
nal. Consult Packaging Section of Databook for thermallimita·
tions and considerations of packages.

LFQP-48 (Top View)
FQP Package
HSlGND---------,
HSlGND--------,
LINE 9 - - - - - - . . . ,
LINE 23 - - - - - - ,
LlNE24---..,

r---------HS/GND
r - - - - - - - LlNES
r - - - - - - LlNE7
r - - - - - LlNE6
r - - - - LlNE5

Nle

SSOP-36 (Top View)
MWP Package

LINES

LlNE7

LlNE9

LlNE6

LlNE23

LlNE5

LlNE24

LlNE22

LlNE25

LlNE21

LlNE26

LlNE20

LlNE27

LlNE19

LINE 22

GND

REG

GND

GND

GND

GND
GND

NiC

LlNE10

TRMPWR

LlNE11

LlNE1S

LlNE12

LlNE17

LlNE13

LlNE16

LlNE1.

LlNE15

LlNE1

LINE.

LlNE2

LlNE3

LINE 15

LINE 1 2 - - - . . J
LINE 13 - - - - - - - '
LINE 1 4 - - - - - - - '
HSlGND---------'
HSlGND--------...J

"----LlNE4
L-----LlNE3
L-_ _ _ _ _ LlNE2
L-------LlNE 1
L---------HSlGND

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = O°C to 70°C, TRMPWR
= 475V , DISCNCT=OV , TA=TJ
PARAMETER

TEST CONDITIONS

MIN

TVP

MAX

UNITS

Supply Current Section
TRMPWR Supply Current
Power Down Mode

All Termination Lines = Open

1

2

rnA

All Termination Lines = 0.2V

630

650

rnA

DISCNCT = TRMPWR

100

200

ItA

3·67

UCC5620

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = O°C to 70°C, TRMPWR
= 475V , DISCNCT - OV TA -- TJ
PARAMETER

TEST CONDITIONS

MIN

TYP

110 . 115.5

MAX

UNITS

Output Section (Termination Lines)

n

Termination Impedance

(Note 3)

104.5

Output High Voltage

(Note 1)

2.6

2.8

3.0

V

Max Output Current

VUNE = 0.2V, TJ = 25°C

-22.1

-23.3

-24

mA-

VUNE= 0.2V

-20.7

-23.3

-24

mA

VUNE = 0.2V, TRMPWR = 4V, TJ = 25°C (Note 1)

-21

-23

-24

mA

VLINE = 0.2V, TRMPWR = 4V (Note 1)

-20

-23

-24

mA

-22.4

mA

Output Leakage

VLINE= 0.5V
DISCNCT = 2.4V, TRMPWR = OV to 5.25V

10

400

nA

Output Capacitance

DISCNCT = 2.4V (Note 2)

2.5

4

pF
V

Regulator Section
Regulator Output Voltage

2.6

Drop Out Voltage

All Termination Lines = 0.2V

Short Circuit Current

VREG= OV

Sinking Current Capability

VREG = 3.5V

2.8

3.0

0.4

0.8

V

-650

-900

-1300

mA

300

500

900

Thermal Shutdown

170

mA
Co

Thermal Shutdown Hysteresis

10

Co

Disconnect Section
Disconnect Threshold
I nput Current

0.8
DISCNCT=OV

1.5

2.0

V

-20

-60

!LA

Note1:Measuring each termination line while other 26 are low (0.2V).
Note 2:Guaranteed by design. Not 100% tested in production.
Note 3: Tested by measuring lOUT with VOUT = 0.2V and VOUT with no load, then calculate:

z = -,-(II.-"o-,,-uT,--N_._L_-_0_.2_V-,-)
IOuTatO.2V

PIN DESCRIPTIONS
DISCNCT: Taking this pin high or leaving it open causes
all channels to become high impedance, and the chip to
go into low-power mode; a low state allows the channels
to provide normal termination.

GND: Ground reference for the IC.
LlNE1 - LlNE27: 11 on termination channels.
REG: Output of the internal 2.7V regulator.
TRMPWR: Power for the IC.

3-68

UCC5620

APPLICATION INFORMATION

r-------------------------------------l
I

UCC5620

I
I

r-Q

TRMPWR

DISCNCT

L1

TO DRIVERS
AND RECEIVERS

TO SCSI BUS

Figure 1. Typical Wide SCSI Bus Configuration Using the UCC5620

UNITRODE CORPORATION
7 CONTINENTAL BLVD.· MERRIMACK, NH 03054
TEL. (603) 424-2410 FAX (603) 424-3460

3-69

UDG-98188

~UNITRCDE

UCC5621

27 - Line SCSI Terminator With Split Reverse Disconnect
FEATURES

DESCRIPTION

• Complies with SCSI, SCSI-2, SCSI-3,
SPI and FAST-20 (Ultra) Standards

UCCS621 provides 27 lines of active termination for a SCSI (Small Computer Systems Interface) parallel bus. The SCSI standard recommends active termination at both ends of the cable.

• 2.SpF Channel Capacitance During
Disconnect
• 10011A Supply Current in Disconnect
Mode

The UCCS621 is ideal for high performance SV SCSI systems. During disconnect the supply current is typically only 100llA, which makes the IC attractive for lower powered systems.
The UCCS621 features a split reverse disconnect allowing the user to control termination lines 10 to 27 with disconnect one, DISCNCT1, and control
terminiation lines 1 to 9 with disconnect two, DISCNCT2.

• 4V To 7V Operation
• 1100 Termination
• Completely Meets SCSI Hot Plugging
• -900mA Sourcing Current for
Termination
• +SOOmA Sinking Current for Active
Negation
• Logic Command Disconnects all
Termination Lines
• Split Reverse Controls Lines 1 to 9
and 10 to 27 Separately
• Trimmed Impedance to S%
• Current Limit and Thermal Shutdown
Protection

The UCCS621 is designed with a low channel capacitance of 2.SpF, which
eliminates effects on signal integrity from disconnected terminators at interim points on the bus.
The power amplifier output stage allows the UCCS621 to source full termination current and sink active negation current when all. termination lines
are actively negated.
The UCCS621, as with all Unitrode terminators, is completely hot pluggable and appears as high impedance at the teminating channels with
VTRMPWR = OV or open.
Internal circuit trimming is utilized, first to trim the 1100 impedance, and
then most importantly, to trim the output current as close to the maximum
SCSI-3 specification as possible, which maximizes noise margin in FAST20 SCSI operation.
(continued)

BLOCK DIAGRAM
REG

r-------------------------------

TRMPWR

9

-----------,
I
I
I
I
I
I

I
I
I
I
I

1100
).,
'---r--'~r-<'"~~ L1NE1

GND~

I
I
I
I
I
I

l~

I
I

SOURCE/SINK
POWER DRIVER

I

I

1100

I

I
I
:
I

I
I
I
I

~LINE2

DISCNcn
(HIGH=CONNECT)
DISCONNECT
COMPARATOR

I
I

I

DISCNCT2
(HIGH=CONNECT)

I

_ 1~~~

I

:

,.L,

~~LINE27
DISCONNECT
COMPARATOR

C~~~~~L

C~~~~~L

(LINES 10-27)

L -______________________

~

(LINES 1-9)

I
:

I
I

L ___________________________________________ I
~

Circuit Design Patented

10198

3-70

UDG·96111

UCC5621

CONNECTION DIAGRAM

ABSOLUTE MAXIMUM RATINGS
TRMPWR Voltage ................................ +7V
Signal Line Voltage .......................... OV to +7V
Regulator Output Current. ......................... 1.5A
Storage Temperature ................... -65°C to +150°C
Junction Temperature ................... -55°C to + 150°C
Lead Temperature (Soldering, 10 Sec.) ............. +300°C

QSOP-44 (Top View)
MWP Package
L8
L9
123

Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.

124

N/C
N/C

LQFP-48 (Top View)
FQP Package

126

HSiGNo - - - - - - - - - ,

HS/GND

HSiGNo - - - - - - - - ,

L8

L9-------,
[23-----,

L27

L7

GND

L8
15
L22

L24---....,
NIC

GND
GND
GND
DISCNCT1
DISCNCT2

17 18
NIC
L12---.J

L13-------'
L14 - - - - - - - '
HSIGNo - - - - - - - - - - '
HSiGNo - - - - - - - - - '

19

15
L----L4
L-----L3
'----------L2
'-----------L1
L--------HSIGNo

DESCRIPTION (cont.)
Other features include thermal shutdown and current
limit. This device is offered in low thermal resistance versions of the industry standard 44 pin wide body OSOP
(MWP) and 48 pin LOFP. Consult OSOP-44 and FOP48 Packaging Diagrams for exact dimensions.

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = O°C to 70°C,
TRMPWR - 475V, DISCNCT1 - DSCNCT2 - 4 75V, TA -- TJ

-

PARAMETER

-

-

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Supply Current Section

TRMPWR Supply Current
Power Down Mode

=Open
=0.2V
DISCNCT1 =DSCNCT2 =OV

All Termination Lines

1

2

rnA

All Termination Lines

630
100

650

rnA

200

IlA

3-71

UCC5621

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA'= o·e to 70·e,
TRMPWR - 4 75V, DISCNCT1 -- DSCNCT2 - 4 75V , TA - TJ
MIN
TYpl MAX
PARAMETER
tEST CONDITIONS

-

-

-

Termination Impedance
Output High Voltage
Max Output Current

(Note 3)

104.5

(Note 1)

2.6
-22.1

110
2.8
-23.3

-20.7
-21
-20

-23.3
-23
-23

VUNE = 0.2V, TJ = 25·C
VLINE=0.2V
VLINE = 0.2V, TRMPWR = 4V, Tj = 25·C (Note 1)
VUNE = 0.2V, TRMPWR = 4V (Note 1)

Output Leakage
Output Capacitance
Regulator Section

VUNE= 0.5V
DISCNCT1 = DISCNCT2 = OV, TRMPWR = OV to 5.25V

10

DISCNCT1 = DISCNCT2 = OV (Note 2)

2.5

Regulator Output Voltage
Drop Out Voltage

All Termination Lines = 0.2V

Short Circuit Current
Sinking Current Capability

VREG=OV
VREG=3.5V

2.6

2.8

-650

0.4
-900

300

Thermal Shutdown
Thermal Shutdown Hysteresis
Disconnect Section
Disconnect Threshold DISCNCT1
Input Current DISCNCT1
Disconnect Threshold DISCNCT2

UNITS

.-

Output Section (Termination Lines)

500
170

V

-24
-24
-24
-24

mA
mA
mA
mA

-22.4

mA
nA

400
4.

0.8
0.8

Input Current DISCNCT2
DISCNCT2 = OV
Note 1: Measuring each termination line while other 26 are low (0.2V).
Note 2: Guaranteed by design. Not 100% tested in production.
Note 3: Tested by measuring lOUT with VOUT = 0.2Vand VOUT with no load, then calculate:

1.5
-10
1.5
-10

Z= VOUTN.L-0.2V
louratO.2V

PIN DESCRIPTIONS
DISCNCT1: Disconnect one controls termination lines
L10 - L27. Taking this pin low causes termination lines
L10 - L27 to become high impedence, taking this pin
high or leaving it open allows the channels to provide
normal termination.

GND: Ground reference for the IC.
L 1 - L27: 11

on termination channels.

REG: Output of the internal2.7V regulator.
TRMPWR: Power for the IC.

DISCNCT2 : Disconnect two controls termination lines
L 1 - L9. Taking this pin low causes termination lines L 1 L9 to become high impedence. Taking this pin high or
leaving it open allows the channels to provide normal terminiation. Taking both disconnect pins low will put the
chip in to sleep mode where it will be in low-power mode.

3-72

pF

3.0
0.8
-1300

V
V
mA

900

mA
·C
·C

10
Controls Lines 10 to 27
DISCNCT1 = OV
Controls Lines 1 to 9

n

1.15,5
3:0

2.0

V

-30
2

!1A

-30

!1A

V

UCC5621

~---------------------------------------------I

I

UC5621
TRMPWR

DISCNCT1

TO DRIVERS
AND RECEIVERS

DISCNCT1 CONTROLS LINES L 10 THRU L27
DISCNCT2 CONTROLS LINES L 1 THRU L9
TO SCSI BUS
UDG-98168

Figure 1. Typical Wide SCSI Bus Configuration Using the UCC5621

UNITRODE CORPORATION
7 CONTINENTAL BOULEVARD. MERRIMACK, NH 03054
TEL (603) 424-2410. FAX (603) 424-3460

3-73

[1JJ

UCC5622

_UNITRDDE

27 - Line SCSI TerminatorWith Split Disconnect
FEATURES

DESCRIPTION

• Complies with SCSI, SCSI-2, SCSI-3,
SPI and FAST-20 (Ultra) Standards

The UCC5622 provides 27 lines of active termination for a SCSI (Small
Computer Systems Interface) parallel bus. The SCSI standard recommends active termination at both ends of the cable.

• 2.5pF Channel Capacitance During
Disconnect
• 100llA Supply Current in Disconnect
Mode

The UCC5622 is ideal for high performance 5V SCSI systems. During disconnect the supply current is typically only 100f,tA, which makes the IC attractive for lower powered systems.
The UCC5622 features a split disconnect allowing the user to control termination lines 10 to 27 with disconnect one, DISCNCT1, and control terminiation lines 1 to 9 with disconnect two, DISCNCT2.

• 4V To 7V Operation
• 110n Termination
• Completely Meets SCSI Hot Plugging
• -900mA Sourcing Current for
Termination
• +500mA Sinking Current for Active
Negation
• Logic Command Disconnects all
Termination Lines
• Split Disconnect Controls Lines 1 to 9
and 10 to 27 Separately
• Trimmed Impedance to 5%
• Current Limit and Thermal Shutdown
Protection

The UCC5622 is designed with a low channel capacitance of 2.5pF, which
eliminates effects on signal integrity from disconnected terminators at interim points on the bus.
The power amplifier output stage allows the UCC5622 to source full termination current and sink active negation current when all termination lines
are actively negated.
The UCC5622, as with all Unitrode terminators, is completely. hot pluggable and appears as high impedance at the teminating channels with
VTRMPWR = OV or open.
Internal circuit trimming is utilized, first to trim the 110n impedance, and
then most importantly, to trim the output current as close to the maximum
SCSI-3 specification as possible, which maximizes noise margin in FAST20 SCSI operation.
(continued)

BLOCK DIAGRAM
REG

r-------------------------------

TRMPWR

Q

-----------,
I
I
I
I
I
I

I
I
I
I
I

lIon

,l,

lIon

I
I
I
I
I
I
I

I

I

I

I
:

I
I

I

I

I

I

I

:

r-,.-'--t-<>""'~ LINEI

GND~
I"'"
I
I
I
I

SOURCE/SINK
POWER DRIVER

DlSCNCT1
(LOW-CONNECT)

~LINE2
DISCONNECT
COMPARATOR

DISCNCT2
(LOW-CONNECT)

I

.

1!~~

=
-

SWITCH
CONTROL
(LINES 10·27)

L -____________________

SWITCH
CONTROL
(LINES 1-9)

I
I
I
:

~

L _______________________________________

~

___ I
~

UDG·96113

Circuit Design Patented

10198

,-L,

~~LlNE27

DISCONNECT
COMPARATOR

3-74

UCC5622

CONNECTION DIAGRAM

ABSOLUTE MAXIMUM RATINGS
TRMPWR Voltage ................................ +7V
Signal Line Voltage .......................... OV to +7V
Regulator Output Current. ......................... 1.5A
Storage Temperature ................... -65°C to +150°C
Junction Temperature ................... -55°C to +150°C
Lead Temperature (Soldering, 10 Sec.) ............. +300°C

QSOP-44 (Top View)
MWP Package
La
L9

Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermallimitations and considerations of packages.

L23

L24
NlC
N/C

LQFP-48 (Top View)
MWP Package
H~ND-------------,

H~ND

-----------,

L9 - - - - - - - - - - - - - ,
L23 - - - - - - - - - - ,

l24 - - - - - - - - ,

L25
L26

,--------------H~ND

r - - - - - - - - - - LB

L27

,---------L7

...---------18

GND

...-------l.5
L22

NIC

GND
GND
GND
DISCNCT1
DISCNCT2
L11
L12

NlC
N/C

L15

Nle

l.5

L12 - - - - - - - '
L13 - - - - - - - - - - '

L14 - - - - - - - - - - - - '
~ND - - - - - - - - - - - - - - '
H~ND---------------'

~----L4
~------L3

"---------L2
'-------------L1
'---------------H~ND

DESCRIPTION (cont.)
Other features include thermal shutdown and current
limit. This device is offered in low thermal resistance versions of the industry standard 44 pin wide body OSOP
(MWP) and 48 pin LOFP (FOP). Consult OSOP-44 and
LOFP-48 Packaging Diagram for exact dimensions.

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for T A
TRMPWR - 4 75V DISCNCT1 -- DSCNCT2 - OV TA -- TJ

-

PARAMETER

-

TEST CONDITIONS

MIN

=O°C to 70°C,
TYP

MAX

UNITS

Supply Current SectIon
TRMPWR Supply Current
Power Down Mode

All Termination Lines = Open

1

2

rnA

All Termination Lines = 0.2V

630

650

rnA

DISCNCT1 = DSCNCT2 = TRMPWR

100

200

j.iA

3-75

UCC5622

=

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA O°C to 70°C,
TRMPWR = 4.75V, DISCNCT1 = DSCNCT2 = OV TA= TJ.
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

Output Section (Termination Lines)

UNITS
...

n

Termination Impedance

(Note 3)

104.5

110

115.5

Output High Voltage

(Note 1)

2.6

2.8

3.0

V

Max Output Current

VUNE = 0.2V, TJ = 25°C

-22.1

-23.3

-24

mA

VLINE= 0.2V

-20.7

-23.3

-24

mA

VUNE = 0.2V, TRMPWR = 4V, TJ = 25°C (Note 1)

-21

-23

-24

mA

VUNE = 0.2V, TRMPWR = 4V (Note 1)

-20

-23

VUNE= 0.5V

-24

mA

-22.4

mA

Output Leakage

DISCNCT1 = DISCNCT2 = 2.4V, TRMPWR = OV to
5.25V

10

400

nA

Output Capacitance

DISCNCT1 = DISCNCT2 = 2.4V (Note 2)

2.5

4

pF

2.8

3.0

V

0.4

0.8

V

Regulator Section
Regulator Output Voltage

2.6

Drop Out Voltage

All Termination Lines = 0.2V

Short Circuit Current

VREG= OV

-650

-900

-1300

mA

Sinking Current Capability

VREG= 3.5V

300

500

900

mA

Thermal Shutdown

170

°C

Thermal Shutdown Hysteresis

10

°C

Disconnect Section
Disconnect Threshold DISCNCT1

Controls Lines 10 to 27

Input Current DISCNCT1

DISCNCT1 = OV

Disconnect Threshold DISCNCT2

Controls Lines 1 to 9

Input Current DISCNCT2

DISCNCT2 = OV

1.5

2.0

V

-10

-30

!lA

0.8
0.8

1.5

2

V

-10

-30

,..A

Note 1: Measuring each termination line while other 26 are low (0.2V).
Note 2: Guaranteed by design. Not 100% tested in production.
Note 3: Tested by measuring lOUT with VOUT = 0.2V and VOUT with no load, then calculate:

z= VOUTN.L-0.2V
'ouTat2.0V

PIN DESCRIPTIONS
DISCNCT1: Disconnect one controls termination lines
10 - 27. Taking this pin high or leaving it open causes
termination lines 10 - 27 to become high impedence, taking this pin low allows the channels to provide normaltermination.
DISCNCT2: Disconnect two controls termination lines
1 - 9. Taking this pin high or leaving it open causes
termination lines 1 - 9 to become high impedence. Taking
this pin low allows the channels to provide normal
terminiation. Taking both disconnect pins high or leaving

them open will put the chip in to sleep mode where it will
be in low-power mode.
GND: Ground reference for the IC.
L 1 - L27: 11 on termination channels.

REG: Output of the internaI2.7V regulator.
TRMPWR: Power for the IC.

3-76

UCC5622

r--------------------------------------------- I

r-Q

..r-9
-=-

UC5622
DISCNCT1

I
TRMPWR
I

I

Yl I4.7I!F
:

DISCNCT2

REG

:

-=-

--: f"

TO DRIVERS
AND RECEIVERS

DISCNCT1 CONTROLS BITS 10 THRU 27
DISCNCT2 CONTROLS BITS 1 THRU 9
roSCSI BUS

UDG-9B172

Figure 1. Typical Wide SCSI Bus Configuration Using the UCC5622

UNITRODE CORPORATION
7 CONTINENTAL BLVD. MERRIMACK, NH 03054
TEL (603) 424-2410. FAX (603) 424-3460

3-77

~UNITRODE

UCC5628
PRELIMINARY

Multimode SCSI 14 Line Terminator
FEATURES

DESCRIPTION

• Auto Selection Single Ended (SE) or
Low Voltage Differential (LVD)
Termination

The UCC5628 Multimode SCSI Terminator provides a smooth transition
into the next generation of the SCSI Parallel Interface (SPI-2). It automatically senses the bus, via DIFFB, and switches the termination to either single ended (SE) or low voltage differential (LVD) SCSI, dependent on which
type of devices are connected to the bus. The UCC5628 can not be used
on a HVD, EIA485, differential SCSI bus. If the UCC5628 detects a HVD
SCSI device, it switches to a high impedance state.

• Meets SCSI-1, SCSI-2, SCSI-3, SPI,
Ultra (Fast-20), Ultra2 (SPI-2 LVD)
and Ultra3 Standards
• 2.7V to 5.25V Operation
• Differential Failsafe Bias
• Thermal packaging for low junction
temperature and better MTBF.

The Multimode terminator contains all functions required to terminate and
auto detect and switch modes for SPI-2 bus architectures. Single Ended
and Differential impedances and currents are trimmed for maximum effectiveness. Fail Safe biasing is provided to insure signal integrity. Device/Bus
type detection circuitry is integrated into the terminator to provide automatic
switching of termination between single ended and LVD SCSI and a high
impedance for HVD SCSI. The multimode function provides all the per~
formance analog functions necessary to implement SPI-2 termination in a
single monolithic device.
The UCC5628 is offered in a 48 pin LQFP package for a temperature
range of O°C to 70°C.

BLOCK DIAGRAM
r----------------------------------------------------------I

(NOISE LOAD)

I:
I

HPD

- 15mA ,; ISOURCE ,; --5mA
5011A ,; ISINK ,,20011A

:

~EF
1.3V
I
35

1.3V

:

DIFFB

DIFFSEN

I

LVD

34

SE
I

~ SOURCE/SINK REGULATOR

110

:
:

~

~ --<>--[>----:-~124 o--JVV\
56mV

REF
1.25V

MODE
ALL SWITCHES
SE
UP
DOWN
LVD
DISCNCT
OPEN

110

0-0--

DISCNCT

I
I
I

I
I

o
I

ow.
~o
124

52.5

I

1

~ o--JVV\~---8

~
r---<' -----l

J..
=

HS/GND

I

0

SE GND SWITCH
HS/GND

:

~ L1-

:""'"~
I ~ ,,.
J..
~m~

I

TRMPWR

52.5

0

- +

0

L14-

L14+

:
I

I
I

·-~----T---1213 fn----14.;~jGn------n------n-nn----'

UOG-98099

6/98
3-78

UCC5628

CONNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS
TRMPWR Voltage ................................ +6V
Signal Line Voltage ..................... OV to TRMPWR
Package Dissipation ............................... 2W
Storage Temperature ................... -65°C to +150°C
Junction Temperature ................... -55°C to + 150°C
Lead Temperature (Soldering, 10 sec.) ............. +300°C
Recommended Operating Conditions ......... 2.7V to 5.25V

(TOP VIEW)
FQP Package
HSiGNO ------~
HSlGND - - - - - - - ,

~------HS/GND

, - - - - - - HSlGND
, - - - - - HS/GND

HSlGND----~

,-----TRMPWR
,----L14-

AEG------,
L1+--~

L14+

L1-

Currents are positive into negative out of the specified terminal.
Note: Consult Packaging Section of Databook for thermallimitations and considerations of package.

RECOMMENDED OPERATING CONDITIONS
TRMPWR Voltage ........................ 2.7V to 5.25V
Temperature Ranges ...................... O°C to +70°C

OISCNCT
DIFFSENS
OIFFB

GND
SE

LVD
HSlGND
HSlGND
HS/GND

HSiGNO

HSlGND
HSlGND

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = TJ = O°C to 70°C,

-

TRMPWR-33V
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

TRMPWR Supply Current Section
TRMPWR Supply Current

LVD Mode

20

25

mA

SE Mode

1.6

10

mA

Disabled Terminator

250

400

itA

Regulator Section
1.25V Regulator

LVD Mode

1.15

1.25

1.35

V

1.25V Regulator Source Current

VREG= OV

-375

-700

-1000

mA

1.25V Regulator Sink Current

VREG=3.3V

170

300

700

mA

1.3V Regulator

Diff Sense

1.2

1.3

1.4

V

1.3V Regulator Source Current

VREG=OV

-15

-5

mA

200

1.3V Regulator Sink Current

VREG= 3.3V

50

2.7V Regulator

SE Mode

2.5

2.7

3.0

itA
V

2.7V Regulator Source Current

VREG= OV

-375

-700

-1000

mA

2.7V Regulator Sink Current

VREG= 3.3V

170

300

700

mA

100

105

110

Q

(Note 2)

110

150

165

Q

125

mV

Differential Termination Section
Differential Impedance
Common Mode Impedence

100

Differential Bias Voltage

1.15

Common Mode Bias
Output Capacitance

Single Ended Measurement to Ground (Note 1)

3-79

1.25

1.35

V

3

pF

UCC5628

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for T A = TJ = O°C to 70°C,
TRMPWR=33V
MIN

TYP

MAX, UNITS

102.3

110.

117.7

n

Signal Level 0.2V, All Lines Low

-21

-24

-25.4

mA

Signal Level 0.5V

-t8

-22.4

mA

TEST CONDITIONS

PARAMETER
Single Ended Termination Section
Impedance
Z = (VLx
Termination Current

-O·2V,Xx, (Note 3)

Output Leakage
Output Capacitance

Single Ended Measurement to Ground (Note 1)

Single Ended GND SE Impedance

1= 10mA

20

400

nA

3

pF

80

n

Disconnect and Diff Buffer Input Section
0.8

DISCNCT Threshold

10

DISCNCT Input Current

2.0

V

30

u,A
V

Diff Buffer Single Ended to LVD Threshold

0.5

0.7

Diff Buffer LVD to HPD Threshold

1.9

2.2

V

DIFFB Input Current

-10

10

uA

Status Bits (SE, LVD) Output Section
ISOURCE

VLOAD = 2.4V

-4

-8

mA

ISINK

VLOAD =O.4V

2

5

mA

Note 1: Guaranteed by design. Not 100% tested in production.
Note 2: ZCM

=[

1. 2V

] where VCM=voltage measured with L+ tied to L- and zero current applied

I(VCM+O.6V) -1(VCM-O.6V)

Note 3: VLx= Output voltage for each terminator minus output pin (L 1- through L 14-) with each pin unloaded.
ILx = Output current for each terminator minus output pin (L 1- through L 14-) with the minus output pin forced to 0.2V.

PIN DESCRIPTIONS
OIFFB: Diff sense filter pin should be connected at a
0.1 ~F capacitor.

LlNEI1+: Ground line for single ended or positive line for
differential applications for the SCSI bus.

OIFFSENS: The SCSI bus Diff Sense line to detect what
types of devices are connected to the SCSI bus.

L VO: TTL Compatible status bit indicating that the device
has detected the bus in LVD mode. If the terminator is
conected it is in LVD mode.

OISCNCT: Disconnect pin shuts down the terminator
when it is not at the end of the bus. The disconnect pin
low enables the terminator.
LINEn-: Signal line active line for single ended or negative line in differential a~plications for the SCSI bus.

REG: Regulator bypass pin, must be connected to a
4.7j.lF capacitor.

SE: TTL Compatible status bit indicating that the device
has detected the bus in single ended mode. If the termi~
nator is conected it is in single ended mode.
TRMPWR: VIN 2.7V to 5.25V supply.

3-80

UCC5628

APPLICATION INFORMATION
The UCC5628 is a Multi-mode active terminator with selectable single ended (SE) and low voltage differential
(LVD) SCSI termination integrated into a monolithic component. Mode selection is accomplished with the "diff
sense" signal.
The diff sense signal is a three level signal, which is
driven at each end of the bus by one active terminator. A
LVD or multi-mode terminator drives the diff sense line to
1.3 V. If diff sense is at 1.3 V, then bus is in LVD mode. If
a single ended SCSI device is plugged into the bus, the
diff sense line is shorted to ground. With diff sense
shorted to ground, the terminator changes to single
ended mode to accommodate the SE device. If a HVD
device is plugged in to the bus, the diff sense line is
pulled high and the terminator shuts down.
The diff sense line is driven and monitored by the terminator through a 50Hz noise filter at the DIFFB input pin.
A set of comparators, that allow for ground shifts, determine the bus status as follows. Any diff sense signal below 0.5V is single ended, between 0.7V and 1.9V is LVD
and above 2.2V is HVD.
In the single ended mode, a multi-mode terminator has a
110n terminating resistor connected to a 2.7V termination voltage regulator. The 2.7V regulator is used on all
Unitrode terminators designed for 3.3V systems. This requires the terminator to operate in specification down to
2.7V TRMPWR voltage to allow for the 3.3V supply tolerance, an unidirectional fusing device and cable drop. At
each L+ pin, a ground driver drives the pin to ground,
while in single ended mode. The ground driver is specially designed so it will not effect the capacitive balance
of the bus when the device is in LVD or disconnect
mode. The device requirements call for 1.5pF balance on
the lines of a differential pair. The terminator capacitance
has to be a small part of the capacitance imbalance.
Layout is very critical for Ultra2 and Ultra3 systems.
Multi-layer boards need to adhere to the 120n imped,ance standard, including connector and feed-through.
This is normally done on the outer layers with 4 mil etch

and 4 mil spacing between the runs within a pair, and a
minimum of 8 mil spacing to the next pair. This spacing
between the pairs reduces potential crosstalk. Beware of
feed-throughs and each through hole connection adds a
lot of capacitance. Standard power and ground plane
spacing yields about 1pF to each plane. Each feedthrough will add about 2.5pF to 3.5pF. Enlarging the
clearance holes on both power and ground planes can
reduce the capacitance and opening up the power and
ground planes under the connector can reduce the capacitance for through hole connector applications. Microstrip technology is normally too low of impedance and
should not be used. It is designed for 50n rather than
120n differential systems.
Capacitance balance is critical for Ultra2 and Ultra3. The
balance capacitance standard is 0.5pF per line with the
balance between pairs of 2pF. The components are designed with very tight balance, typically 0.1 pF between
pins in a pair and 0.3pF between pairs. Layout balance is
critical, feed-throughs and etch length must be balanced,
preferably no feed-throughs would be used. Capacitance
for devices should be measured in the typical application, material and components above and below the circuit board effect the capacitance.
Multi-mode terminators need to consider power dissipation; the UCC5628 is offered in a power package with
heat sink ground pins. These heat sink/ground pins are
directly connected to the die mount paddle under the die
and conduct heat from the die to reduce the junction
temperature. These pins need to be connected to etch
area or a feed-through per pin connecting to the ground
plane layer on a multi-layer board.
In 3.3V TRMPWR systems, the UCC3912 should be
used to replace the fuse and diode. This reduces the
voltage drop, allowing for cable drop to the far end terminator. 3.3V battery systems normally have a 10% tolerance. The UCC3912 is 150mV drop under LVD loads,
allowing 150mV drop in the cable system. All Unitrode
LVD and multi-mode terminators are designed for 3.3V
systems, operating down to 2.7V.

3-81

UCC5628

TYPICAL APPLICATION

i-----------~~-.::~8-f---..,,~---------.------iB~:.

TERMPWR

------------1

,
,
:
CONTROL LINES (9)
, •
TRMPWR 3
.
,
'
O'L9+:'
~+c=Jf---~'---------L---~:

3 TRMPWR

~O

D~:

I,

I :

,

"
"

~:: Bf---~--------.------i8 ~.::
•

I

i

:

::

: 4 BITS OF THE HIGH BYTE

:

:

:

:

:

L1~B
8' ~13+
-f---------------___i-

L13-

!

L13-

,

rfil, D I S C N C T '

J.- i
-=-

,DISCNCT
351-------.--------.--------135 DIFFSENSE

DIFFSENSE
I

I

1
I

REG

L__ ~_____

DIFFB

4.7~F

0.1~F

:

20k

201<

,,,
,,
,,

I

L1+

.
:

LON BYTE 8+ PARITY

DAtHINES (15)

L9TRMPWR

L10+

L10+

L10-

L10HIGH BYTE 4 BITS
PLUS PARITY

DISCNCT

L14+

L14+

L14-

L14-

,

,

:

'REG

L__ ~_____

I

I

~
-

-

4.7~F

,,:
,,
,,,
,,
,

L9+

L9+

I

-

I

0.1~F

L1-

DATA LINES (15)

T

r--------------l
I-+--------------H

L1-

,,
,,
,,
,,
,,
,

-

REG

L_~ 34 ----~-1-1

,

rr

DIFFB

220k

r--------------~

L1+

f3'sh:
I

I

34 __

I I

,,
,
,,,

TRMPWR

:

:

34 __ 1

,

DISCNCT

f3'sh
:

------1-1
I

DIFFB

L_ 34

4.7~F

3

T~

I

DlFFB,

,,
,,
,
,,,
,,,
-=-

REG,

4.7~F

SCSI CONTROLLER
DIFFSENS
UDG-98100

Note: A 220k resistor is added to ground to insure the transceivers will come up in single-ended mode when no terminator is enabled. The controller DIFFSENS ties to the DIFFB pin on the terminators, only one RC network should be on a device.
UNITRODE CORPORATION
7 CONTINENTAL BLVD.• MERRIMACK, NH 03054
TEL. (603) 424-2410. FAX (603) 424-3460

3-82

~UNITRODE

UCC5630

Low Voltage Differential (LVD/SE) SCSI 9 Line Terminator
FEATURES

DESCRIPTION

• Auto Selection Multi-Mode Single
Ended or Low Voltage Differential
Termination

The UCC5630 Multi-Mode Low Voltage Differential and Single Ended Terminator is both a single ended terminator and a low voltage differential terminator for the transition to the next generation SCSI Parallel Interface
(SPI-2). The low voltage differential is a requirement for the higher speeds
at a reasonable cost and is the only way to have adequate skew budgets.
The transceivers can be incorporated into the controller, unlike SCSI high
power differential (EIA485) which requires external transceivers. Low Voltage differential is specified for Fast-40 and Fast-80, but has the potential of
speeds up to Fast-320. The UCC5630 is SPI-2, SPI and Fast-20
compliant. Consult OSOP-36 and LOFP-48 Package Diagram for exact dimensions.

• 2.7V to 5.25V Operation
• Differential Failsafe Bias
• Thermal Packaging for Low Junction
Temperature and Better MTBF
• Master/Slave Inputs
• Supports Active Negation

The UCC5630 can not be used with SCSI high voltage differential (HVD)
EIA485. It will shut down when it sees high power differential to protect the
bus. The pinning for high power differential is not the same as LVD or single ended and the bias voltage, current and power are also different for
EIA485 differential.

• Standby (Disable Mode) 51lA
• 3pF Channel Capacitance

BLOCK DIAGRAM
SOURCE ONLY FROM TRMPWR AND THE ENABLED TERMINATORS
,------------------------------------------------------------------~

I
I

TRMPWR

SOURCE 5 < 1SmA

§---

SINK 200~ MAXIMUM (NOISE LOAD)
+VDD

I
I

MSTRlSLV

19l-----------~====-_l

OPEN CIRCUIT ON POWER OFF
OR
OPEN CIRCUIT IN A DISABLED
TERMINATOR MODE

~------------~20

1.3V. -Q.1V
HIPD

2.2> 1.9V
DIFFB

LVD
SE
110

SOURCE/SINK
REGULATOR

REF2.7V

f--o ~

REF 1.25V

~-

V"

I
i
i

O-"'V\/\r~-o---<>"""-

~~~~~~D:~~~

52:

~ L1+

WITH POWER OFF

:

l

110

~-c-~

l

i

~~

52

I

~L9+
:

r:':;,

SWITCHES UP ARE SINGLE
ENDED SWITCHES DOWN ARE
LOW VOLTAGE DIFFERENTIAL

~

DISCNCT~
I

~-------------------------

REG

1

b

:

i
I

_

I

-------------------------------~------~
MWP 36 PINOUT

UDG·9B049

Circuit Design Patented

01199

. ..
SE GND
SWITCH

3-83

UCC5630

ABSOLUTE MAXIMUM RATINGS

CONNECTION DIAGRAM

TRMPWR Voltage ................................. 6V
Signal Line Voltage ..................... OV to TRMPWR
Package Power Dissipation ......................... 2W
Storage Temperature ................... -65°C to +150°C
Junction Temperature ................... -55°C to +150°C
Lead Temperature (Soldering, 10sec.) ............. +300°C

QSOP-36 (Top View)
MWP Package
TRMPWR
HIPD

All voltages are with respect to PINt. Currents are positive into,
negative out of the specified terminal. Consult Packaging Section of the Databook fot thermal limitations and considerations
of packages.

LVD

SE

L9-

LQFP-48 (Top View)
FQP Package
HSiGNO - - - - - - - - - ,
HSlGND - - - - - - - - ,
L6+--~-__,

L6-------,
L7+--__,
L7-

L9+

La,...-------HSGNO
,------HSGNO
,...-----NIC
,...----0IFF8
,---DIFSENS

L8+
HSIGND
HSIGND

MSTR/$LV

HSIGND

L7+

L6L6+
DIFFB
DIFSENS
MSTRISLV

NC
REG----'
NC---........l
NC----.......J
HSiGNO-------'
HSiGNO---------'

L2'----L2+

RECOMMENDED OPERATING CONDITIONS
TRMPWR Voltage ....................... 2.7V TO 5.25V

L----L1_
L -_ _-'--_L1+"
'-------HSIGNO
L-------HSlGND

ELECTRICAL CHARACTERISTICS: Unless otherwise specified , TA =O°C to 70°C , TRMPWR =3 3V
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

20

rnA
!LA

TRMPWR Supply Current Section
TRMPWR Supply Current
Disable Terminator, in DISCNCT mode.

35

Regulator Section
1.25V Regulator

LVD Mode

1.15

1.25

1.25V Regulator Source Current

LVD Mode, Differential Sense Floating

-80

-100

1.35

V

rnA
rnA

1.25V Regulator Sink Current

LVD Mode, Differential Sense Floating

80

100

1.3V Regulator

DIFSENS

1.2

1.3

1.4

V

1.3V Regulator Source Current

DIFSENS

-5

-15

1.3V Regulator Sink Current

DIFSENS

50

200

rnA
!LA

3-84

UCC5630

ELECTRICAL CHARACTERISTICS: Unless otherwise specified TA = O°C to 70°C , TRMPWR = 3 3V
PARAMETER
TEST CONDITIONS
MIN
TYP
2.7V Regulator
Single Ended Mode
2.5
2.7
Single Ended Mode
2.7V Regulator Source Current
-200 -400
2.7V Regulator Sink Current
Single Ended Mode
100
200
2.7V Regulator Dropout Voltage
VTRMPWR - (VREG - 2.7 Min)
Differential Termination Section
Differential Impedance
100
105
Common Mode Impedance
110
125
Differential Bias Voltage
Drivers Tri-stated
100
Common Mode Bias
1.25
Output Capacitance
Single Ended Measurement to Ground (Note 1)
Single Ended Termination Section
Impedance
102.3
110
Termination Current
Signal Level 0.2V
-21
-23
Signal Level 0.5V
Output Leakage
Disabled, TRMPWR = OV to 5.25V
Output Capacitance
Single Ended Measurement to Ground (Note 1)
Single Ended GND SW Impedance
Disconnect (DISCNCT) Input Section
DISCNCT Threshold
0.8
DISCNCT Input Current
-30
VOISCNCT = OV and 3.3V
Differential Sense (DIFFB) Input Sections
DIFFB Single Ended Threshold
0.6
DIFFB Sense LVDS Threshold
1.9
DIFFB Input Current
VOIFFB = OV and 3.3V
-30
MasterlSlave (MSTRlSLV) Input Section
MSTRlSLV Threshold
0.8
MSTRlSLV Input Current
-30
Status Bits (SE, LVD, HIPD) Output Section
-8.7
VLOAO=2.4V
-4
ISOURCE
VLOAO= 0.5V
6
ISINK
3
2
5
VLOAO= O.4V
Note 1: Guaranteed by deSign. Not 100% tested in production.

MAX UNITS
V
3
-800
mA
400
mA
200
mV
110
165
125
3.5
117.7
-25.4
-22.4
400
3
60
2.0
30
0.7
2.2
30
2
30

Q
Q

mV
V
pF
Q

mA
mA
nA
pF
Q

V
IlA
V
V
IlA
V

JlA
mA
mA
mA

PIN DESCRIPTIONS
DIFFB: DIFSENS filter pin should be connected to a
0.1 J.1F capacitor to GND and 20k resistor to SCSI/Bus
DIFSENS Line.
DIFSENS: The SCSI bus DIFSENS line is driven to 1.3V
to detect what type of devices are connected to the SCSI
bus.

is in shutdown. (Not valid in disconnect mode.)
HS/GND: Heat Sink GND. Connect to large area PC
board traces to increase power dissipation capability.
GND: Power Supply Return.
L 1- thru L9-: Signal line/active line for single ended or
negative line in differential applications for the SCSI bus.

DISCNCT: Disconnect shuts down the terminator when it
is not at the ended of the bus. The disconnect pin low
enables the terminator.

L 1 + thru L9+: Ground line for single ended or positive
line for differential applications for the SCSI bus.

HIPD: TTL compatible status bit indicating high voltage
differential has been detected on DIFFB. The terminator

LVD: TTL compatible status bit indicating low voltage differential level on DIFFB. The terminator is in LVD
mode.(Not valid in disconnect mode.)

3-85

UCC5630

PIN DESCRIPTIONS (cont.)
MSTRlSLV: Mode select for the non-controlling terminator. MSTR enables the 1.3V regulator, when the terminator is enabled. Note: Theis function will be removed on
further generations of the multimode terminators.
REG: Regulator bypass, must be connected to a 4.7!lF

capacitor.

SE: TTL compatible status bit indicating single ended device has been detected on DIFFB. The terminator is in
single ended mode.
TRMPWR: VIN 2.7V to 5.25V supply.

APPLICATION INFORMATION

r--------------l
TERMPWR ---1~_-I36 TERMPWR
CONTROL LINES
19 MSTRlSLV

U

I
7 DISCNCT
I
REG

r--------------~

I

D=~~~~~~~~~~~~O
I

I

DIFFSENSE 20

= ~--:c-----

DIFFB

I

C.~~~~~~~~~~~.O
I

I

'

4.7~F

DATA LINES (9)

I

MSTRlSLV~9

:

~

I

:

_____ DI:~B J

L••~~~~~~~~~~.C
I

:

17 D I S C N C T :

DIFFB

L--:c-----

21

=

4.7~F

r--------------~

:

~I :
REG

_____ ~_J

I

4.7~F

DATA LINES (9)
19 MSTRlSLV

I

DISCNCT 17

L_~':;~

__

I

=

I

0.1~F

"

r~-------------l

:

I

:

17 D I S C N C T :

=

~

r--------------~

I

DATA LINES (9)
19 MSTRlSLV

r:':;]
DISCNCT
REG

L--21------:J:-~

r--------------l

I ~l__

CONTROL LINES
I
. MSTRlSLV 19

20 DIFFSENSE
I
:
DIFF B

14.7~F

4.7~F

TERMPWR 36 H~-t"- TERMPWR

:

TERMPWR 36
DATA LINES (9)
MSTRISLV

:

I

:

--~

DISCNCT 17

DIFFB

L __ 21

4.7~F

I

~9

REG

I

------:J:-~

I

=

4.7~F
UDG·96211

Balancing capacitor is very important in high speed operation. The typical balance between the positive (+) and
negative (-) signals is 0.1 pF except for L8 and L9,
0.23pF and O.4pF respecitvely on the MWP package.
The negative (-) signal has higher capacitance than the
positive (+) signal. The FQP package is typically 0.2pF
less than the MWP. Typical balance is 0.1pF except for
1.,8 and L3, where it is O.4pF.

The master is selected by placing TRMPWR on
MSTRISLV and the terminator enabled by grounding
DISCNCT, enabling the 1.3V regulator. The master is the
only terminator connected directly to DIFSENS bus line,
all the other te,minators receive the mode signal by connecting the DIFFB pins together.
Note: The Master/Slave function will not be on future terminators.

UNITRODE CORPORATION
7 CONTINENTAL BLVD .• MERRIMACK, NH 03054

TEL. (603) 424-2410. FAX (603) 424·3460

3-86

~UNITRDDE

UCC5630A
ADVANCE INFORMATION

Multimode SCSI 9 Line Terminator
FEATURES

DESCRIPTION

• Auto Selection Single Ended (SE) or
Low Voltage Differential (LVD)
Termination

The UCC5630A Multimode SCSI Terminator provides a smooth transition
into the next generation of the SCSI Parallel Interface (SPI-2). It automatically senses the bus, via DIFFB, and switches the termination to either single ended (SE) or low voltage differential (LVD) SCSI, dependent on which
type of devices are connected to the bus. The UCC5630A can not be used
on a HVD, EIA485, differential SCSI bus. If the UCC5630A detects a HVD
SCSI device, it switches to a high impedance state.

• Meets SCSI-1, SCSI-2, SCSI-3, SPI,
Ultra (Fast-20), Ultra2 (SPI-2 LVD)
and Ultra3 Standards
• 2.7V to 5.25V Operation

The Multimode terminator contains all functions required to terminate and
auto detect and switch modes for SPI-2 bus architectures. Single Ended
and Differential impedances and currents are trimmed for maximum effectiveness. Fail Safe biasing is provided to insure signal integrity. Device/Bus
type detection circuitry is integrated into the terminator to provide automatic
switching of termination between single ended and LVD SCSI and a high
impedance for HVD SCSI. The multimode function provides all the performance analog functions necessary to implement SPI-2 termination in a single monolithic device.

• Differential Failsafe Bias
• Thermal packaging for low junction
temperature and better MTBF
• Master/Slave Input
• Supports Active Negation
• 3pF Channel Capacitance

The UCC5630A is offered in a 36 pin SSOP package, as well as a 48 pin
LQFP package for a temperature range of O°C to 70°C.

BLOCK DIAGRAM

HIPD

LVD

I
I
I
I

DIFFB

SE

--------------------------------,
(NOISE LOAD)
,:
>-+----11--+-. HIPD

,,----------------------------211-------+

~

L...:,R=E:..F1.:.;:.3:;:V='-_!;>-"1.=.;3V'------i 20

>------<>---+-.

LVD

>-------+-.

SE

-1 SmA :5:; ISOURCE S -SmA

:

501lA s IS'NK

,

< 2001lA

I

MSTRlSLV
I SE REF 2.7V

~ElSINK REGULATOR

~

ILVDREF1.25V~

I

110

~
124

56mV

+-

DISCNCT

'-""----~

7

ENABLE
SWITCHES

0

~~
~o

MODE

ALL
SWITCHES

SE

UP

LVD

DOWN

HIPD

OPEN

DISCNCT

OPEN

110

+---0--- o--Wv
124

52.5

,
I

'

i
I

0

L1-

I

~L1+

SE GND SWITCH

I"" ----l

....L
~

0

i:

I·
I
•

:

~o

525

~ o----W.

m.~ ~I Tn TT

DIFSENS

I

I
•
I·

§] ~

,::,-~ ~

l-~-~-0-0-B--§J@~--------- ----------------------PATEN~ED-C'jRCUn_DESiGj
GND

' - - - - - HSlGND - - . /

1
REG

UDG-98192

Note: Indicated pinout is for 36 pin SSOP package.

12198
3-87

UCC5630A

CONNECTION DIAGRAM

ABSOLUTE MAXIMUM RATINGS
TRMPWR Voltage . ................................ 6V
Signal Line Voltage ..................... OV to TRMPWR
Package Power Dissipation ......................... 2W
Storage Temperature ................... --65°C to + 150°C
Junction Temperature ................... -55°C to + 150°C
Lead Temperature (Soldering, 10sec.) ............. +300°C

QSOP-36 (Top View)
MWP Package

TRMPWR
HIPD

All voltages are with respect to pin 18. Currents are positive
into, negative out of the specified terminal. Consult Packaging
Section of the Databook for thermal limitations and considerations of packages.

LVD
SE

RECOMMENDED OPERATING CONDITIONS
TRMPWR Voltage ........................ 2.7V to 5.25V

HSlGND
HSlGND

LQFP-48 (Top View)
FQP Package

HSlGND

H~ND--------------,

H~ND

HSiGND - - - - - - - - - - - - ,

LA-

1.5+------,

LA+
L.3L3+

l.5-----....,

DISCNCT - - - ,

GND

L3-

L7-

L4+

L7+

L4--

L6-

L5+

L6+

L5-

DIFFB

NC

DISCNCT
GND

'-'"

NC

L8-

TEAMPWR

L9+
LaHSlGND
HS/GND

HIPD
LVD

SE
HSlGND

3-88

OIFSENS
MSTRlSLV

UCC5630A

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = TJ = O°C to 70°C,
TRMPWR=33V
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

LVD Mode

13

20

mA

SE Mode

1.6

10

mA

Disabled Terminator

250

400

IIA

TRMPWR Supply Current Section
TRMPWR Supply Current

Regulator Section
1.25V Regulator

LVD Mode

1.15

1.25

1.35

V

1.25V Regulator Source Current

VREG=OV

-600

-420

-225

mA

1.25V Regulator Sink Current

VREG= 3.3V
SE Mode

100

180

420

mA

2.7V Regulator

2.5

2.7

3.0

V

2.7V Regulator Source Current

VREG= OV

-600

-420

-225

mA

2.7V Regulator Sink Current

VREG= 3.3V

100

180

420

IIA

1.3

Diff Sense Driver (DIFSENS) Section
1.3V DIFSENS Output

DIFSENS

1.2

1.4

V

1.3V DIFSENS Source Current

VOIFSENS = OV

-15

-5

mA

1.3V DIFSENS Sink Current

VOIFSENS = 2.75V

50

200

mA

Differential Termination Section
Differential Impedance
Common Mode Impedence

(Note 2)

100

105

110

110

150

165

n
n

125

mV

1.25

1.35

V

3

pF

117.7

n

Differential Bias Voltage

100

Com[Tlon Mode Bias

1.15

Output Capacitance

Single Ended Measurement to Ground (Note 1)

Single Ended Termination Section
Impedance

Termination Current

X

102.3

110

Signal Level 0.2V, All Lines Low

-25.4

-24

Signal Level 0.5V

-22.4

Z = (VLx -0· 2II

x ,(Note 3)

Output Leakage
Output Capacitance

Sin.gle Ended Measurement to Ground (Note 1)

Single Ended GND SE Impedance

1= 10mA

20

-21

mA

-18

mA

400

nA

3

pF

60

n

2.0

V

Disconnect (DISCNCT) and Diff Buffer (DIFFB) Input Section
DISCNCT Threshold

0.8

DISCNCT Input Current

-30
.

DIFFB Single Ended to LVD Threshold

!1A

10

0.5

0.7

DIFFB LVD to HPD Threshold

1.9

2.4

V

DIFFB Input Current

-10

10

IIA

3-89

V

UCC5630A

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for T A = TJ = O°C to ,70°C,
TRMPWR = 3.3V
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

MasterlSlave (MSTRlSLV) Input Section
MSTRlSLV Threshold

0.8

2

V

MSTRISLV Inpilt Current

-30

30

IIA

-4

rnA

Status Bits (SE, LVD, HIPD) Output Section
-8.7

ISOURCE

VLOAO= 2.4V

ISINK

VLOAO= 0.5V

3

6

rnA

VLOAO= O.4V

2

5

rnA

Note 1: Guaranteed by design. Not 100% tested in production.

Note2:ZCM =

1.2V

;

I(VcM +o.6V) -1(VCM-o.6V )

Where VCM = Voltage measured with L+ tied to L- and zero current applied;

Note 3: VLx= Output voltage for each terminator minus output pin (L 1- through L9'-) with each pin unloaded.
ILx= Output current for each terminator minus output pin (L 1- through L9'-) with the minus output pin forced to 0.2V.

PIN DESCRIPTIONS
DIFFB: Input pin for the comparators that select SE,
LVO, or HIPO modes of operation. This pin should be decoupled with a 0.11lF capacitor to ground and then coupled to the OIFSENS pin through a 20kQ resistor.
DIFSENS: Connects to the Oiff Sense line of the SCSI
bus. The bus mode is controlled by the voltage level on
this pin.
DISCNCT: Input pin used to shut down the terminator if
the terminator is not connected at the end of the bus.
Connect this pin to ground to activate the terminator or
open pin to disable the terminator.
HIPD: TTL compatible status bit. This output pin is high
when a high voltage differential device is detected on the
bus.
HS/GND: Heat sink ground pins. These should be connected to large area PC board traces to increase the
power dissipation capability.
GND: Power Supply return.

L 1- thru L9-: Termination lines. These are the active
lines in SE mode and are the negative lines for LVO
mode. In HIPO mode, these lines are high impedance.
L 1+ thru L9+: Termination lines. These lines switch to
ground in SE mode and are the positive lines for L VO
mode. In HIPO mode, these lines are high impedance.
MSTRlSLV: If the terminator is enabled, this input pin
enables / disables the OIFSENS driver, when connected
to TRMPWR or ground respectively. When the terminator
is disabled, the OIFSENS driver is off, independent of
this input.
LVD: TTL compatible status bit. This output pin is high
when the SCSI bus is in LVO mode.
REG: Regulator output bypass pin. This pin must be
connected to a 4.71lF capaCitor to ground.
SE: TTL compatible status bit. This output pin is high
when the SCSI bus is in SE mode.
TRMPWR: 2.7V to S.2SV power input pin.

3-90

UCC5630A

APPLICATION INFORMATION

r--------------l
TERMPWR---1.9V

I
20k

DIFF B

LVD
LOW
FREQUENCYTo.1I1F I

FILTER

-.L

50Hz-60Hz -===-

I
I
I
I
I
I
I

O.7V>O.SV

-

C::>---l>-----liSE

L-....

I
I
I
I
I
I
I
I
I

I
I
I
I

I
I

D'SCNCT

¢-----{:>-I
I

I
I

IL

____________ _

UDG-97092

Circuit Design Patented

UNITRODE CORPORATIoN
7 CONTINENTAL BLVD.• MERRIMACK. NH 03054
TEL. (603) 424-2410. FAX (603) 424-3460

3197
3-93

~·UNITRCDE

UCC5638

Multimode SCSI 15 Line Terminator
FEATURES

DESCRIPTION

• Auto Selection Single Ended (SE) or
Low Voltage Differential (LVD)
Termination

The UCC5638 Multimode SCSI Terminator provides a smooth transition
into the next generation of the SCSI Parallel Interface (SPI-2). It automatically senses the bus, via DIFFB,and switches the termination to either single ended (SE) or low voltage differential (LVD) SCSI, dependent on which
type of devices are connected to the bus. The UCC5638 can not be used
on a HVD, EIA485, differential SCSI bus. If the UCC5638 detects a HVD
SCSI device, it switches to a high impedance state.

• Meets SCSI-1, SCSI-2, SCSI-3, SPI,
Ultra (Fast-20), Ultra 2 (SPI-2 LVD)
and Ultra 3 Standards
• 2.7V to 5.25V Operation

The Multimode terminator contains all function~ required to terminate and
auto detect and switch modes for SPI-2 bus architectures. Single Ended
and Differential impedances and currents are trimmed for maximum effectiveness. Fail Safe biasing is provided to insure signal integrity. Device/Bus
type detection circuitry is integrated into the terminator to provide automatic
switching of termination between single ended and LVD SCSI and a high
impedance for HVD SCSI. The multi mode function provides all the performance analog functions necessary to implement SPI-2 termination in a
single monolithic device.

• Differential Failsafe Bias
• Thermal packaging for low junction
temperature and better MTBF.

The UCC5638 is offered in a 48 pin LQFP package for a temperature
range of O°C to 70°C.

BLOCK DIAGRAM

r----------------------------------------------------------I

(NOISE lOAD)
HIGH POWER

I

I ~;~

DIFFERENTIAL

:
34

lOW VOLTAGE
DIFFERENTIAL

DIFFB

.

I

1.3V

V

r-::::

~

REF
1.25V

-

+

110

t-o---

DISCNCT

:

0

52.S

~

o-VV'v
124

:

6mv

~~

cb
I

o

52.S

0

~

HS/GND

~-@}-----0---12T
-=-

f------

•

I

I

li5-

SE+G:DSWIT~
1..

115+

0

1

ll-

CD

~

:

GND

:

@]

:~i0I :~'"
- +

HS/GND

DIFFSEN

I
I
I
I
I
I
I

I

MODE
All SWITCHES
SE
UP
lVD
DOWN
DISCNCT
OPEN

:

~
Y

:

110

L---o SOURCE/SINK REGULATOR
---<>----f>----~124
56mV

~

TRMPWR

I

~

-lSmA';; 'SOURCE ';;-SmA
SOIlA,;; 'SINK ,;; 20011A

SINGLE ENDED

~

:

I

:
10

-REG---------------------------1

14.7

11F

03/99
3-94

UDG.98063

UCC5638

CONNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS
TRMPWR Voltage ................................ +6V
Signal Line Voltage ..................... OV to TRMPWR
Package Dissipation ............................... 2W
Storage Temperature ................... -65°C to +150°C
Junction Temperature ................... -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ............. +300°C
Recommended Operating Conditions ......... 2.7V to 5.25V

(TOP VIEW)
FQP Package
HSlGND - - - - - - - . ,
HSlGND - - - - - - - ,
HSlGND - - - - - . ,
REG - - - - - - - ,

L1+---.,
L1-

,--------HS/GND
,---------HSIGND
,------HS/GNO
,-------TRMPWR
,..-----L15L1S+

Currents are positive into negative out of the specified terminal.
Note: Consult Packaging Section of Databook for thermallimitations and considerations of package.

RECOMMENDED OPERATING CONDITIONS
TRMPWR Voltage ........................ 2.7V to 5.25V
Temperature Ranges ...................... O°C to +70°C

DISCNCT

LB+
LaGND
HS/GND
HS/GND

OIFFSENS
DIFFB

HSlGND
HSlGND
HSlGND

HS/GND

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = TJ = O°C to 70°C,
TRMPWR=33V
PARAMETER

TEST CONDITIONS

MIN

UNITS

TYP

MAX

LVD Mode

20

25

mA

SE Mode

1.6

10

mA

Disabled Terminator

250

400

IIA

TRMPWR Supply Current Section
TRMPWR Supply Current

Regulator Section
1.25V Regulator

LVD Mode

1.15

1.25

1.35

V

1.25V Regulator Source Current

VREG=OV

-375

-700

-1000

mA

1.25V Regulator Sink Current

VREG=3.3V

170

300

700

mA

1.3V Regulator

Diff Sense

1.2

1.3

1.4

V

1.3V Regulator Source Current

VREG=OV

-15

-5

mA

200

IIA

1.3V Regulator Sink Current

VREG= 3.3V

50

2.7V Regulator

SE Mode

2.5

2.7

3.0

V

2.7V Regulator Source Current

VREG=OV

-375

-700

-1000

mA

2.7V Regulator Sink Curren

VREG=3.3V

170

300

700

mA

100

105

110

110

150

165

g
g

125

mV

1.25

1.35

V

3

pF

Differential Termination Section
Differential Impedance
Common Mode Impedence

(Note 2)

Differential Bias Voltage

100

Common Mode Bias

1.15

Output Capacitance

Single Ended Measurement to Ground (Note 1)

3-95

UCC5638

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA·'" TJ = O°C to 70°C,
TRMPWR=33V
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

102.3

110

117.7

Q

Signal Level 0.2V, All Lines Low

-21

-24

-25.4

mA

Signal Level 0.5V

-18

-22.4
400

mA
nA'

3

pF

60

Q

Single Ended Termination Section

X

Impedance

Z = (VLx -O· 2V
Termination Current

ILx

,(Note 3)
.

Output Leakage
Output Capacitance

Single Ended Measurement to Ground (Note 1)

Single Ended GND SE Impedance

1= 10mA

20
..

Disconnect and Diff Buffer Input Section
DISCNCT Threshold

0.8

DISCNCT Input Current

10

2.0

V

30

IlA
V

Diff Buffer Single Ended to LVD Threshold

0.5

0.7

Diff Buffer LVD to HPD Threshold

1.9

2.2

V

DIFFB Input Current

-10

10

IlA

Note 1: Guaranteed by design. Not 100% tested in production.
Note 2: Line+ (positive) tied to Line- (negative); I(VCMm~~;JvCMmin)
Note 3: VLx= Output voltage for each terminator minus output pin (L 1- through L 15-) with each pin unloaded.
ILx= Output current for each terminator minus output pin (L 1- through L15-) with the minus output pin forced to 0.2V.

PIN DESCRIPTIONS
DIFFB: Diff sense filter pin should be connected at a
0.1 JlF capacitor.

LINEn-: Signal line active line for single ended or negative line in differential applications for the SCSI bus.

DIFFSENS: The SCSI bus Diff Sense line to detect what
types of devices are connected to the SCSI bus.

LINEI1+: Ground line for single ended or positive line for
differential applications for the SCSI bus.

DISCNCT: Disconnect pin shuts down the terminator
when it is not at the end of the bus. The disconnect pin
low enables the terminator.

REG: Regulator bypass pin, must be connected to a
4.7JlF capacitor.
TRMPWR: VIN 2.7V to 5.25V supply.

Note: In Disconnect Mode, the comparitor set powers down for low idle current.

3-96

UCC5638

APPLICATION INFORMATION
The UCC5638 is a Multi-mode active terminator with selectable single ended (SE) and low voltage differential
(LVD) SCSI termination integrated into a monolithic component. Mode selection is accomplished with the "diff
sense" signal.
The diff sense signal is a three level signal, which is
driven at each end of the bus by one active terminator. A
LVD or multi-mode terminator drives the diff sense line to
1.3 V. If diff sense is at 1.3 V, then bus is in LVD mode. If
a single ended SCSI device is plugged into the bus, the
diff sense line is shorted to ground. With diff sense
shorted to ground, the terminator changes to single
ended mode to accommodate the SE device. If a HVD
device is plugged in to the bus, the diff sense line is
pulled high and the terminator shuts down.
The diff sense line is driven and monitored by the terminator through a 50Hz noise filter at the DIFFB input pin.
A set of comparators, that allow for ground shifts, determine the bus status as follows. Any diff sense signal below 0.5V is single ended, between 0.7V and 1.9V is LVD
and above 2.2V is HVD.
In the single ended mode, a multi-mode terminator has a
110Q terminating resistor connected to a 2.7V termination voltage regulator. The 2.7V regulator is used on all
Unitrode terminators designed for 3.3V systems. This requires the terminator to operate in specification down to
2.7V TRMPWR voltage to allow for the 3.3V supply tolerance, an unidirectional fusing device and cable drop. At
each L+ pin, a ground driver drives the pin to ground,
while in single ended mode. The ground driver is specially designed so it will not effect the capacitive balance
of the bus when the device is in LVD or disconnect
mode. The device requirements call for 0.5pF balance on
the lines of a differential pair. The terminator capacitance
has to be a small part of the capacitance imbalance.
Layout is very critical for Ultra 2 and Ultra 3 systems.
Multi-layer boards need to adhere to the 120Q impedance standard, including connector and feed-through.
This is normally done on the outer layers with 4 mil etch

and 4 mil spacing between the runs within a pair, and a
minimum of 8 mil spacing to the next pair. This spacing
between the pairs reduces potential crosstalk. Beware of
feed-throughs and each through hole connection adds a
lot of capacitance. Standard power and ground plane
spacing yields about 1pF to each plane. Each feedthrough will add about 2.5pF to 3.5pF. Enlarging the
clearance holes on both power and ground planes can
reduce the capacitance and opening up the power and
ground planes under the connector can reduce the capacitance for through hole connector applications. Microstrip technology is normally too low of impedance and
should not be used. It is designed for 50Q rather than
120Q differential systems.
Capacitance balance is critical for Ultra 2 and Ultra 3.
The balance capacitance standard is 0.5pF per line with
the balance between pairs of 2pF. The components are
designed with very tight balance, typically 0.1 pF between
pins in a pair and 0.3pF between pairs. Layout balance is
critical, feed-throughs and etch length must be balanced,
preferably no feed-throughs would be used. Capacitance
for devices should be measured in the typical application, material and components above and below the circuit board effect the capacitance.
Multi-mode terminators need to consider power dissipation; the UCC5638 is offered in a power package with
heat sink ground pins. These heat sink/ground pins are
directly connected to the die mount paddle under the die
and conduct heat from the die to reduce the junction
temperature. These pins need to be connected to etch
area or a feed-through per pin connecting to the ground
plane layer on a multi-layer board.
In 3.3V TRMPWR systems, the UCC3912 should be
used to replace the fuse and diode. This reduces the
voltage drop, allowing for cable drop to the far end terminator. 3.3V battery systems normally have a 10% tolerance. The UCC3912 is 150mV drop under LVD loads,
allowing 150mV drop in the cable system. All Unitrode
LVD and multi-mode terminators are designed for 3.3V
systems, operating down to 2.7V.

3-97

UCC5638

TYPICAL APPLICATION

i------------~-.::8---,-----,--------.---~,B~::. --------- ---i

TERMPWR

-.--"'-__1 3 TRMPWR

:

,,

CONTROL LINES (9)

• ,
0'
~+[]~--~~--------~----1.

8
·
B
,

,.f36l, DISCNCT

J... i
-=-

.----------------1.

REG

DIFFB

4.7~F

•

L15+
L15OISCNCT

DIFFSENSE

~:
T
~
I

0.1~F

:

20k

20k

L __ 34

I

REG

------I-~

I

O.1~F

L1+

L1-

L1-

.

HIGH BYTE 4 BITS
PLUS PARITY

:

1.9+

L9-

LI>-

L10+

L10+
L10-

L15+

L15+

I

,

,

:

~-"'I-----

L15-

DISCNCT

I

DIFFB,
34

4.7~F

,,
,,
,
,,,
,,

LCYN BYTE 8+ PARITY

'REG

-

DATA LINES (15)

L9+

L15-

-

I

L10-

DISCNCT

I

r--------------

L1+

DATA LINES (15)

,,
,,
,,
,,
,,,

DIFFB

270k

f--------------~

-

:

I

I

--~

34

I I

-

.

I

~--I-----

IT

"8
I

35 f-----...,.----'"------...----I35

DIFFSENSE

,,
,,
,,
,
,,,
,,
,,

:

I

I

I

4 BITS OF THE HIGH BYTE

I

L15+
L15-

1------...-

Buo+
L10-

.---,------------.----1.

I

•

3

''
'

,,,

:

TRMPWR

[]L9-

LI>-O

L10+
L10-

•

1.9+:

:

--~

:

DIFFB

L __ 34

REG

-=-

,.:

------I-~

I

14.7~F

~
T~

4.7~F

SCSI CONTROLLER
DIFFSENS
UDG-98064

Note: A 220k resistor is added to ground to insure the transceivers will come up in single-ended mode when no terminator is enabled. The controller DIFFSENS ties to the DIFFB pin on the terminators, only one RC network should be on a device.
UNITRODE CORPORATION
7 CONTINENTAL BLVD .• MERRIMACK, NH 03054
TEL. (803) 424-2410' FAX (803) 424-3480

3-98

~UNITRCDE

UCC5639

Multimode SCSI 15 Line Terminator with Reverse Disconnect
FEATURES

DESCRIPTION

., Auto Selection Single Ended (SE) or
Low Voltage Differential (LVD)
Termination

The UCC5639 Multimode SCSI Terminator provides a smooth transition
into the next generation of the SCSI Parallel Interface (SPI-2). It automatically senses the bus, via DIFFB, and switches the termination to either single ended (SE) or low voltage differential (LVD) SCSI, dependent on which
type of devices are connected to the bus. The UCC5639 can not be used
on a HVD, EIA485, differential SCSI bus. If the UCC5639 detects a HVD
SCSI device, it switches to a high impedance state.

• Meets SCSI-1, SCSI-2, SCSI-3, SPI,
Ultra (Fast-20), Ultra2 (SPI-2 LVD)
and Ultra3 Standards
• 2.7V to 5.25V Operation

The Multimode terminator contains all functions required to terminate and
auto detect and switch modes for SPI-2 bus architectures. Single Ended
and Differential impedances and currents are trimmed for maximum effectiveness. Fail Safe biasing is provided to insure signal integrity. Device/Bus
type detection cirCUitry is integrated into the terminator to provide automatic
switching of termination between single ended and LVD SCSI and a high
impedance for HVD SCSI. The multimode function provides all the performance analog functions necessary to implement SPI-2 termination in a
single monolithic device.

• Differential Failsafe Bias
• Thermal packaging for low junction
temperature and better MTBF.

The UCC5639 is offered in a 48 pin LQFP package for a temperature
range of O°C to 70°C.

BLOCK DIAGRAM

r----------------------------------------------------------(NOISE LOAD)

I

I

HIGH POWER

:
34

DIFFERENTIAL

I ~~~

LOW VOLTAGE
DIFFERENTIAL

DIFFB

.

~

ilv.

~

ALL SWITCHES
UP
DOWN
OPEN

...

o--AiV'v
~

--DISCNCT 36

TRMPWR

I

56mV

0

52.5

I
I

~L1:

124

~mv 0
- +

:

~

52.5

~

0

CD

HS/GND

HS/GND

REG

L15-

~

-L

~_~u __1i=-9

•

I
I

SE+G:DSWITC~

I

:

I
I
I
I
I
I

:~::0I :~ '"

:

cb

DIFFSENS

I
:

~~
110

~

Y

110

~124

MODE
SE
LVD
DISCNCT

1.3V

V

~

L-o SOURCE/SINK REGULATOR

~

~
I

-15mA'; ISOURCE ';-5mA
50I'A'; ISINK ,; 2001LA

SINGLE ENDED
~

:
I

0

Ll5+

I

:

1_04.;1';----------------------------1
lu--1 2i=-33 [__ uu 1

UDG-98110

03199
3-99

UCC5639

CONNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS
TRMPWR Voltage ................................ +6V
Signal Line Voltage ..................... OV to TRMPWR
Package Dissipation ............................... 2W
Storage Temperature ................... -65°C to +150°C
Junction Temperature ................... -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ............. +300°C
Recommended Operating Conditions .. '.' ..... 2.7V to 5.25V

(TOP VIEW)
FQP Package
H~ND-------------,

H~ND~---------,
H~ND

, - - - - - - - - - - - - ~ND
, - - - - - - - - - - HSlGND

--'--------------,

, - - - - - - - - HSIGND

REG~---,

,-----mMPWR
,----Ll5L1S.

Ll+--------,
Ll-

Currents are positive into negative out of the specified terminal.
Note: Consult Packaging Section of Databook forthermallimitations and considerations of package.

Ll ....
Ll4+
L13-

.RECOMMENDED OPERATING CONDITIONS

L13+

Lll!-

TRMPWR Voltage ........................ 2.7V to 5.25V
Temperature Ranges ............... , ...... O°C to +70°C

L12+
L11L11+

L10L10+

L9l.9+

DISCNCT
'-------DIFSENS
L----DlFFB
' - - ' - - - - - - ' - - - - HSlGND

lB+
LB- - - - - - - - '

GND--------'
HSlGND - - - - - - - - - - - '

' - , - - - - - - - - - - H~ND

H~ND-------------'

H~ND

--------------'

L------------H~

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = TJ = O°C to 70°C,
TRMPWR-33V
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

TRMPWR Supply Current Section
TRMPWR Supply Current

LVD Mode

20

25

mA

SE Mode

1.6

10

mA

Disabled Terminator

250

400

!lA

Regulator Section
1.25V Regulator

LVD Mode

1.15

1.25

1.35

V

1.25V Regulator Source Current

VREG=OV

-375

-700

-1000

mA

1.25V Regulator Sink Current

VREG=3.3V

170

300

700

mA

1.3V Regulator

DIFSENS

1.2

1.3

1.4

V

1.3V Regulator Source Current

VREG= OV

-15

-5

mA

200

!lA

1.3V Regulator Sink Current

VREG= 3.3V

50

2.7V Regulator

SE Mode

2.5

2.7

3.0

V

2.7V Regulator Source Current

VREG=OV

-375

-700

-1000

mA

2.7V Regulator Sink Curren

VREG=3.3V

170

300

700

mA

100

105

110

Q

110

150

165

Q

125

mV

1.25

1.35

V

3

pF

Differential Termination Section
Differential Impedance
Common Mode Impedence

(Note 2)

Differential Bias Voltage

100

Common Mode Bias

1.15

Output Capacitance

Single Ended Measurement to Ground (Note 1)

3-100

UCC5639

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = TJ = O°C to 70°C,
TRMPWR=33V
MIN

TYP

MAX

UNITS

102.3

110

117.7

n

Signal Level 0.2V, All Lines Low

-21

-24

-25.4

mA

Signal Level 0.5V

-18

-22.4

mA

400

nA

3

pF

60

n

PARAMETER

TEST CONDITIONS

Single Ended Termination Section

X

Impedance

Z = (VLx -0· 2II

Termination Current

x ' (Note 3)

Output Leakage
Output Capacitance

Single Ended Measurement to Ground (Note 1)

Single Ended GND SE Impedance

1= 10mA

20

Disconnect and Diff Buffer Input Section
DISCNCT Threshold

0.8

DISCNCT Input Current

10

2.0

V

30

I1A
V

Dill Buller Single Ended to LVD Threshold

0.5

0.7

Dill Bufler LVD to HPD Threshold

1.9

2.2

V

DIFFB Input Current

-10

10

I1A

Note 1: Guaranteed by design. Not 100% tested in production.

Note 2: ZCM

=[

1. 2V

] where VCM=voltage measured with L+ tied to L- and zero current applied

'(VCM+O.6V) -1(VCM-O.6V)

Note 3: VLx= Output voltage for each terminator minus output pin (L 1- through L 15-) with each pin unloaded.
ILx= Output current for each terminator minus output pin (L1- through L 15-) with the minus output pin forced to 0.2V.

PIN DESCRIPTIONS
0.1~F

DIFFB: Diff sense filter pin should be connected at a
capacitor.

LINEn-: Signal line active line for single ended or negative line in differential applications for the SCSI bus.

DIFFSENS: The SCSI bus Diff Sense line to detect what
types of devices are connected to the SCSI bus.

LlNEIJ+: Ground line for single ended or positive line for
differential applications for the SCSI bus.

DISCNCT: Disconnect pin shuts down the terminator
when it is not at the end of the bus. The disconnect pin
high.enables the terminator.

4.7~F

REG: Regulator bypass pin, must be connected to a
capacitor.

TRMPWR: VIN 2.7V to 5.25V supply.

3-101

UCC5639

APPLICATION INFORMATION
The UCCS639 is a Multi-mode active terminator with se- and 4 mil spacing between the runs within a pair, and a
lectable single ended (SE) and low voltage differential . minimum of 8 mil spacing to the next pair. This spacing
(LVO) SCSI termination integrated into a monolithic com- between the pairs reduces potential crosstalk. Beware of
ponent. Mode selection is accomplished with the "diff feed-throughs and each through hole connection adds a
sense" signal.
lot of capacitance. Standard power and ground plane
The diff sense signal is a three level signal, which is spacing yields about 1pF to each plane. Each feeddriven at each end of the bus by one active terminator. A through wiU add about 2.SpF to 3.SpF. Enlarging the
LVO or multi-mode terminator drives the diff sense line to clearance holes on both power and ground planes can
1.3 V. If diff sense is at 1.3 V, then bus is in LVO mode. If reduce the capacitance and opening up the power and
a single ended SCSI device is plugged into the bus, the ground planes under the connector can reduce the cadiff sense line is shorted to ground. With diff sense pacitance for through hole connector applications. Mishorted to ground, the terminator changes to single crostrip technology is normally too low of impedance and
ended mode to accommodate the SE device. If a HVO should not be used. It is designed for son rather than
device is plugged in to the bus, the diff sense line is 120n differential systems.
pulled high and the terminator shuts down.
The diff sense line is driven and monitored by the terminator through a SOHz noise filter at the OIFFB input pin.
A set of comparators, that allow for ground shifts, determine the bus status as follows. Any diff sense signal below O.SV is single ended, between 0.7V and 1.9V is LVO
and above 2.2V is HVO.
In the Single ended mode, a multi-mode terminator has a
110n terminating resistor connected to a 2.7V termination voltage regulator. The 2.7V regulator is used on all
Unitrode terminators designed for 3.3V systems. This requires the terminator to operate in specification down to
2.7V TRMPWR voltage to allow for the 3.3V supply tolerance, an unidirectional fusing device and cable drop. At
each L+ pin, a ground driver drives the pin to ground,
while in single ended mode. The ground driver is specially designed so it wiU not effect the capacitive. balance
of the bus when the device is in LVO or disconnect
mode. The device requirements call for O.SpF balance on
the lines of a differential pair. The terminator capacitance
has to be a small part of the capacitance imbalance.
Layout is very critical for Ultra2 and Ultra3 systems.
Multi-layer boards need to adhere to the 120n impedance standard, including connector and feed-through.
This is normally done on the outer layers with 4 mil etch

Capacitance balance is critical for Ultra2 and Ultra3. The
balance capacitance standard is O.SpF per line with the
balance between pairs of 2pF. The components are designed with very tight balance, typically 0.1pF between
pins in a pair and 0.3pF between pairs. Layout balance is
critical, feed-throughs and etch length must be balanced,
preferably no feed-throughs would be used. CapaCitance
for devices should be measured in the typical application, material and components above and below the circuit board effect the capacitance.
Multi-mode terminators need to consider power dissipation; the UCCS639 is offered in a power package with
heat sink ground pins. These heat sink/ground pins are
Qirectly connected to the die mount paddle under the die
and conduct heat from the die to reduce the junction
temperature. These pins need to be connected to etch
area or a feed-through per pin connecting to the ground
plane layer on a multi-layer board.
In 3.3V TRMPWR systems, the UCC3912 should be
used to replace the fuse and diode. This reduces the
voltage drop, allowing for cable drop to the far end terminator. 3.3V battery systems normally have a1 0% tolerance. The UCC3912 is 1S0mV drop under LVO loads,
allowing 1S0mV drop in the cable system. All Unitrode
LVO and multi-mode terminators are designed for 3.3V
systems, operating down to 2.7V.

3-102

UCC5639

TYPICAL APPLICATION

i------------~::8-r----.----------.---B ~:: ------------i

Termpower

I
-.----1 3 TAMPWR

.

CONTROL LINES (9)

I
•

:

L9+D

I

I
I

I
I

U~

REG

~--I-----

I

I
I

I
: 4 BITS OF THE HIGH BYTE

•

I

I

4'7~FI

•

:

:

8

L13+

.

DIFF SENSE

U~

I

DIFFB

DISCNCT
DIFSENS

:

:

DIFFB

I

220k

I -~
REG:

v----.-__L_-_---+34 - - - -

Ok
'-''\i2'\i

- -

0.1~F

I

I-t--------------H

L1+

.

:
I
I
I
I
I
I
I

L1-

L1HIGH BYTE 4 BITS
PLUS PARITY

DATA LINES (15)

4.7~F

r--------------l

~--------------~

U+

1-----.--

•

I

351----......------~------135

4.7~F

3

U~

•
•

I

Termpower

TRMPWR

8~10+

I

L1;'B
U~
.

I

•

I

L1IHB

DIFSENS

•
•

I

0;9+
DL!>-

L9-0

I
I

I
I

:

DATA LINES (15)

lb+
L5-

I
I
I

L5-

I
I

L8+

LB+

L8-

L8-

LON BYTE 8+ PARITY
L14+

U4+

L14-

L14-

I

I

I

I

REG

OIFFB

I

34

~--I-----

I

I

:

I

I

:

--~

I

DIFFB

L __ 34

REG:

------I-~

I

4.7~F

4_7~F

SCSI CONTROLLER
DIFFSENS
UDG-98111

Note: A 220k resistor is added to ground to insure the transceivers will come up in single-ended mode when no terminator is enabled_ The controller DIFFSENS ties to the DIFFB pin on the terminators, only one RC network should be on a device_
UNITRODE CORPORATION
7 CONTINENTAL BLVD .• MERRIMACK, NH 03054

TEL (603) 424-2410. FAX (803) 424-3480

3-103

~UNITRODE

UCC5640

Low Voltage Differential (LVD) SCSI 9 Line Terminator
FEATURES

DESCRIPTION

• First LVD only Active Terminator

The UCC5640 is an active terminator for Low Voltage Differential (LVD)
SCSI networks. This LVD only design allows the user to reach peak bus
performance while reducing system cost. The device is designed as an active V-terminator to improve the frequency response of the LVD Bus. Designed with a 1.5pF channel capacitance, the UCC5640 allows for minimal
bus loading for a maximum number of peripherals. With the UCC5640, the
designer will be able to comply with the Fast-40 SPI-2 and Fast-80 SPI-3
specifications. The UCC5640 also provides a much-needed system migration path for ever improving SCSI system standards. This device is available in the 24 pin TSSOP and 28 pin TSSOP for ease of layout use.

• Meets SCSI SPI-2 Ultra2 (Fast-40)
and Ultra3 (Fast-80) Standards
• 2.7V to 5.25V Operation
• Differential Failsafe Bias

The UCC5640 is not designed for use in single ended or high voltage differential systems.

BLOCK DIAGRAM
SOURCE ONLY FROM TRMPWR AND THE ENABLED TERMINATIONS

,----------------------------------------------------------TRMPWR

~

2.7V to 5.25V

EJ

OPEN CIRCUIT ON POWER OFF
OR OPEN CIRCUIT IN A
DISABLED TERMINATOR MODE
~--------------------------------~12

1.3V±O.lV
HIGH POWER
DIFFERENTIAL
DIFFB

20k

O.l1'F

r

LVO*
HIGH IMPEDANCE RECEIVER
EVEN WITH POWER OFF

SOURCE/SINK REGULATOR

124

LOW
FREQUENCY
FILTER
50Hz -60Hz

56mV

+

...

56mV

04199

"'''''ge ~ ---

r.

•

I:
~A-A~L9vvv

y

52·

--1-~,.?-

Ll+

52

-

1

• 28 pin

• ~2.

4
Q----JVV~
Ll-

1

+
5 f---.........--{
1

..

1
1
1
1
1
1

52
31
~

101lA

124
OISCNCT

1 DIFSENS
1
1
1
1
1
1
1

1

~L9+

- -- --

----1•.~~~- ---------------------------- ~'"
J

3-104

UCC5640

CONNECTION DIAGRAMS
TSSOP-28 (Top View)
PW28 Package

TSSOP-24 (Top View)
PW24 Package
REG

TRMPWR
REG

L1+

L9-

L1-

L9+

TRMPWR
LVD
L9-

L6--

L9+

l2-

L8+

L3+

L7-

L9+

L3--

L7+

L7-

L4+

L6-

L7+

L6+

L6--

DIFFB

L5--

DIFSENS

L5+

GND

L6--

L4--

L6+

DIFSENS

L5+

NlC

N/C

L5--

DISCNCT

GND

DISCNCT

ABSOLUTE MAXIMUM RATINGS
TERMPWR Voltage ............................... +6V
Signal Line Voltage .......................... OV to 3.6V
Package Dissipation ............................... 1W
Storage Temperature ................... -65°C to +150°C
Junction Temperature ................... -55°C to + 150°C
Lead Temperature (Soldering, 10 sec.) ............. +300°C
Currents are positive into negative out of the specified terminal.
consult Packaging Section of Databook for thermal limitations
and considerations of package.

RECOMMENDED OPERATING CONDITIONS
TERMPWR Voltage ....................... 2.7V to 5.25V

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, specifications apply for TA =O°C to 70°C,

TRMPWR - 3 .3V TA -TJ
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

TRMPWR Supply Current Section
TRMPWR Supply Current

No Load

25

rnA

Disabled Terminator

400

~

5.25

V

TRMPWR Voltage

2.7

3-105

UCC5640

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, specifications apply for T A = O°C to 70°C,

-

-

TRMPWR - 3 3V TA - TJ
TEST CONDITIONS

PARAMETER

MIN

TYP

MAX

UNITS

1.25

1.35

V

-100

-80

rnA

Regulator Section
1.25V Regulator

DIFSENS connected to DIFFB

1.25V Regulator Source Current

DIFSENS connected to DIFFB

1.15

1.25V Regulator Sink Current

DIFSENS connected to DIFFB

80

100

1.3V Regulator

DIFFB connected to GND

1.2

1.3

1.3V Regulator Source Current

DIFSENS to GND

1.3V Sink Current

rnA
1.4

V

-15

-5

rnA

DIFSENS to 3.3V

50

200

IIA

Differential Termination Section
Differential Impedance

-2.5mA to 4.5mA

100

105

110

Common Mode Impedance

L+ connected to L-

110

150

165

n
n

Differential Bias Voltage

No load, L+ or L-

125

mV

1.25

1.35

V

10

400

nA

3

pF

-4

rnA

100
1.15

Common Mode Bias
Output Leakage, Disconnect

DISCNCT, TRMPWR = 0 to 5.25V,
VLINE = 0.2 to 5.25V

Output CapaCitance

Single ended measurement to ground (Note 1)

Low Voltage Differential (LVD) Status Bit Section
ISOURCE

VLOAD= 2.4V

ISINK

VLOAD= O.4V

-6
2

rnA

5

Disconnect & Differential Sense Input Section
0.8

DISCNCT Threshold
Input Current

-30

At OV and 3.3V

2

V

IIA

-10

Differential Sense Signal Ended to LVD
Threshold

0.5

0.7

V

Differential Sense LVD to HPD Threshold

1.9

2.4

V

Note 1: Guaranteed by design. Not 100% tested in production.

PIN DESCRIPTION
DIFFB: Differential sense filter pin should be connected
to a 0.1 /IF capacitor and 20kn resistor to Diff Sense.
DIFSENS: The SCSI bus differential sense line to detect
what type of devices are connected to the SCSI Bus.
DISCNCT: Disconnect pin shuts down the terminator
when it is not at the end of the bus.

in differential applications for the SCSI Bus.
Ln +: Ground line for single ended or positive line for
differential applications for the SCSI Bus.
LVD: (28 pin package only) Indicates that the bus is in
LVD mode.

GND: Ground.

REG: Regulator bypass; must be connected to a 4.7/lF
capacitor to ground.

Ln -: Signal active line for single ended or negative line

TRMPWR: VIN 2.7V to 5.25V supply.

3-106

UCC5640

APPLICATION INFORMATION
Termpower

1---- - -- - - - - - - - -,

1- - - - - - - - - - - - - - - I

,

,

,

I

I

----~-------i 2'8

~

:c

JL=

UCC5640PW28

I

15

,,
,,,
,

LVD

L1-

DISCNCT

L9+
L9-

REG

4.7~F

I

,,,
,,

L--.1I,JVV__..-___
!..._-_----+10

I

01 F

l'~

Termpower

DISCNCT 13

DIFFB

DIFFB

,

TRMPWR 2'4

~

!...--~-----

1_

UCC5640PW24

~3 L1+
[!J
,, f----,------C-O-N-T-R-O-L-L-IN-E-S--(9-)------:------1: L1~r---~------------------~--~~
E.I ~+
f----------------------------------1~ L9~
,,

TRMPWR

3
L1+ °4

-----

0.1~F

-"2 -~
REG

I

,

4.7~F

1-- - - - - - - - - - - - - - I

,,
,

TRMPWR

L1+

.

I-+------------------------------i-l

2

L1-

,,

DISCNCT

,REG

UCC5640PW24

L1+

TRMPWR

.

,,
,

2~

L1DATA LINES (9)

L9+

L9+

L9-

L9-

DISCNCT 13

,DIFFB

DIFFB

!...--~-----

REG

,
,

!...-- 10 ------"2-~

14.7~F

14.7~F

1-- - - - - - - - - - - - - - I

,,
,

TRMPWR

L1+

1-+------------------------------i-l2

L1-

UCC5640PW24

L1+

TRMPWR

,,
,

d4

L1DATA LINES (9)

,
,

DISCNCT

1

L9+

,

L9-

'REG
S1' \

L9+

!...--~-----

,DIFFB

DIFFB
11

L9-

--~

DISCNCT 13

,

REG,

!...-- 10 -----"2--~

14.7~F

14.7~F
UDG-98180

• CLOSE S1 AND S2 TO CONNECT TERMINATORS

Figure 1. Application diagram.

UNITRODE CORPORATION
7 CONTINENTAL BLVD.· MERRIMACK, NH 03054
TEL. (603) 424-2410· FAX (603) 424-3460

3-107

~UNITRODE

UCC5641
ADVANCE INFORMATION

Low Voltage Differential (LVD) SCSI 9 Line Terminator
FEATURES

DESCRIPTION

• SCSI SPI-2 LVD SCSI 9 Line Low
Voltage Differential Termination

The UCC5641 Low Voltage differential terminator is a low voltage differential terminator only for SCSI Parallel interface (SPI-2). The low voltage differential is a requirement for the higher speeds at a reasonable cost and is
the only way to have adequate skew budgets. The transceivers can be in~
corporated into the controller, unlike SCSI high power differential (EIA485)
which requires external transceivers.

• Meets SCSI SPI-2 Ultra2 (Fast-40)
and Ultra3 (Fast-80) Standby
• 2.7V to 5.25V Operation

Low Voltage differential is specified for FAST-40 and FAST-80, but has the
potential of speeds up to FAST-320.

• Differential Failsafe Bias

The UCC5641 can not be used with SCSI differential EIA485, it will shut
down when it sees high power differential to protect the bus. The pinning
for high power differential is not the same as LVD SCSI or single-ended
and the bias voltage, current and power are also different for EIA485 differential.

BLOCK DIAGRAM
r--------------------------------------------------------~--

1

~

TRMPWR

~
I
1
1
1
1
1
1
1
1

1

OO~~_

:

SINK 200 A MAXIMUM (NOISE LOAD)

"

1

>-------------------------------~11

OPEN CIRCUIT ON
POWER OFF OR OPEN
CIRCUIT IN A DISABLED
TERMINATOR MODE

1 DIFSENS

1.3V±O.1V

1

1
1
1
1

1
1

: DIFFB

1
1
1
1
1
1

LOW
FREQUENCY
FILTER
50Hz-60Hz
HIGH IMPEDANCE RECIEVER
EVEN WITH POWER OFF

SOURCE/SINK
REGULATOR
125

+50mV TO +62.5mV

>-~--~~~--~~---c--

t

1

1
1
1

~
52

~

10"A
125

+50mV TO +62.5mV

1

LlNE1+

1

52

1

52

1

~
~

~-----------------------

LlNE1-

1

LlNE~

LlNE9+

~~~_ - ____ - __________ - - _______ - ___ I

'LVD PIN ON 28 PIN PACKAGE ONLY

UDG·98037

10/98
3-108

UCC5641

CONNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS
TRMPWR Voltage ................................ +6V
Signal Line Voltage .................... OV to TERMPWR
Package Dissipation ............................... 1W
Storage Temperature ................... --65°C to +150°C
Junction Temperature ................... -55°C to + 150°C
Lead Temperature (Soldering, 10 sec.) ............. +300°C

TSSOP-28 (Top View)
PW Package
REG

TRMPWR

LVD

RECOMMENDED OPERATING CONDITIONS

LlNE9-

TERMPWR Voltage ....................... 2.7V to 5.25V

LlNE9+
LINES-

Currents are positive into negative out of the specified terminal.
consult Packaging Section of Databook for thermal limitations
and considerations of package.

LlNES+
LlNE7LlNE?+
LINES-

TSSOP-24 (Top View)
PW Package
REG

1

LlNE4-

LlNE6+

DIFSENS

LlNES+

TRMPWR

LlNE5LlNE9LlNE9+

NlC

NlC

GND

LlNE9+
LlNE7-

LlNE7+
LINES-

LlNE6+
LINESLINES!-

GND

DISCNCT

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, specifications apply for TA =O°C to 70°C, TRMPWR =
33V TA-TJ
PARAMETER

TEST CONDITIONS

MIN

TVP

MAX

UNITS

No Load

25

mA

Disabled Terminator

200

itA
V

TRMPWR Supply Current Section
TRMPWR Supply Current
TRMPWR Voltage

2.7

5.25

Regulator Section
1.25V Regulator

DIFSENS connected to DIFFB

1.15

1.25

1.25V Regulator Source Current

DIFSENS connected to DIFFB

-80

-100

mA

100

mA

1.25V Regulator Sink Current

DIFSENS connected to DIFFB

80

1.25V Current Limit

DIFSENS connected to DIFFB

300

1.3V Regulator

DIFFB connected to GND

1.2

1.3V Regulator Source Current

DIFFBtoGND

1.3V Sink Current

DIFFBtoGND

3-109

1.35

V

mA
1.3

1.4

V

-5

-15

mA

50

200

ItA

UCC5641

ELECTRICAL CHARACTERISTICS:

-

33V TA-TJ

Unl~ss otherwise stated, specifications apply for T A
.

PARAMETER

TEST CONDITIONS

=O°C to 70°C, TRMPWR =
MIN

TYP

MAX

UNITS

Differential Termination Section
Differential Impedance

-2.5mA to 4.5mA

100

105

110

Common Mode Impedance

LlNE+ connected to LlNE-

110

150

165

n
n

Differential Bias Voltage

Drivers Tristated

100

125

mV

400

nA

3

pF

Common Mode Bias

1.25

=0 to 5.25V, VUNE =0.2

Output Leakage, Disconnect

DISCNCT, TRMPWR
t02.5V

Output Capacitance

Single ended measurement to ground (Note 1)

10

V

Disconnect & Differential Sense Input Section
0.8

DISCNCT Threshold
Input Current

At OV and 3.3V

10

2

V

30

IlA

Differential Sense Signal Ended Threshold

0.6

0.7

V

Differential Sense LVD Threshold

1.9

2.2

V

Differential HP Differential Threshold

2.2

V

Note 1: Guaranteed by design. Not 100% tested in production.

TRMPWR: VIN 2.7 to 5.25 Volts supply.

4.7(.1F Capacitor.

DIFSENS: The SCSI bus diff sense line to detect what
type of devices are connected to the SCSI bus.

LINEn-: Signal line Active line for single ended or nega~
tive line in differential applications for the SCSI Bus.

DISCNCT: Disconnect pin shuts down the terminator
when it is not at the end of the bus.

LINEn+: Ground line for single ended or positive line for
differential applications for the SCSI Bus.

DIFFB: Diff Sense filter pin should be connected to a
0.1 (.1F Capacitor.

LVD: Indicates that the bus is in LVD mode regardless of
the terminator's connection mode.

REG: Regulator bypass pin, must be connected to a

3-110

UCC5641

APPLICATION INFORMATION
Diff Sense is drivien by only one terminator at each end
of the bus. All other terminators receive the mode signal

Termpower

by connecting the DIFFB pins together.

~--------------l

r--------------~

- -.....---124 T R M P W R '
CONTROL LINES

i5iScNCT

13

,,

:

D=~~~~~~~~~~~~~~=Q
DIFF SENSE

'REG

DIFFB,

:

0_-_-_~_

I I

-

- - - -

1..

r--------------l

~--~-----

:

--~

:
I

DIFFB

L __ 10

= 4.7~F

TRMPWR
DATA LINES (9)

~--~-----

I

:

[~.~~~~~~~~~~~~.~J DATA LINES (9)

,,,
,

'

DIFSENS

'REG

r--------------~

I

DISCNCT

=

REG,

------I-~

I

r--------------l
,

4.7~F

,DISCNCT

I_ ~

'
l

I

~

TRMPWR 24

:
I

DIFFB,
10

I-

[~.~~~~~~~~~~~~.~J DATA LINES (9)

I
:

'REG

O.I~F

:

DISCNCT:
I
I

'

REG:

r--------------~

TRMPWR'
DATA LINES (9)

'
,

DIFFB

I

O.I~F

Termpower

DISCNCT

'-..IIj2OkIlv-_p--L----~10 - - - - - -

......--'V20Vklr_...J

4.7~F

4.7~I

CONTROLLlNE_S__

'
11 DIFSENS

, f-----r---'--....,.-----j ,

DIFSENS 11

~ -~-

TRMPWR 24

6,

:

DIFFB'
10

--~

DISCNCT

,

,,
DIFFB

REG,

L--l0------I-~

I

4.7~F

4.7~F

Figure 1. Application Diagram

UDG·97181

UNITRODE CORPORATION
7 CONTINENTAL BLVD.• MERRIMACK, NH 03054
TEL. (603) 424·2410. FAX (603) 424·3460

3-111

~UNITRODE

UCC5646
UCC5647

27 Line LVD SCSI Terminator

ADVANCE INFORMATION

FEATURES

DESCRIPTION

• SCSI SPI-2, SPI-3, 160m Compliance

The UCC5646 is a twenty-seven line active terminator for Low Voltage Differential (LVD) SCSI networks. This LVD SCSI only design allows the user
to reach peak bus performance, while reducing system cost. The device is
designed as an active Y-terminator to improve the frequency response of
the LVD SCSI Bus. Designed with a 2pF typlical channel capacitance, the
UCC5646 allows for minimal bus loading for a maximum number of peripherals. With the UCC5646, the designer will be able to comply with the UItra2 and Ultra3, 160m specifications. The UCC5646 also provides a
much-needed system migration path for the ever improving SCSI system
standards .

• Smallest Footprint
• Lowest Channel Capacitance, 2pF
• Less than O.5pF Capacitance
Differential Between Pairs
• 2.7V to 5.25V Operation
• Differential Failsafe Bias
• 64 Pin LQFP

This device is available in the 64 pin LQF package for ease of layout use.
The UCC5646 is not designed for single ended or high volume differential
systems.

BLOCK DIAGRAM
DIFSENS
in n_ --- n

:I I

REF 1.3V

nnn_~-

~

••.
1.3V +/- O.1V

n n n_ n_ n

n_n n

n_n n n n n n n

n

'FOR THE UCC5647 PIN 47 IS DISCNCT1 AND PIN 48 IS DISCNCT2.

I
I

I
I

DIFFB
>-----------------~

I
I

I

ral

+50mV TO +62.5mV

PTRMPWR ~

t
~
48

:

O~2
22L1-

I
I

0

52

:

125

~
47

+50mVTO +62.5mV

+--'I/II'v----1---<>----O-- 0

52

0

52

;1+

I

•

:

•
•

o----Wv----UJ l27o----Wv----UJ

t

I

'DISCNCT2

I

~

L10 . . . . l27

I

:

LVD

:

~~~

'DISCNCT1

2
I

L1 •••• L9

I

l27+

~-----------------~-----~---SGND

PGND

9 _______________________ J
REG
UDG-S8203

01199

3-112

UCC5646

CONNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS
TRMPWR ................................. -0.3V to 6V
Signal Line Voltage ................... -Q.3V to TRMPWR
Package Dissipation ............................... 1W
Regulator Output Current. ........................ 0.75A
Storage Temperature.................... -55°C to +150°C
Junction Temperature ................... -55°C to +150°C
Lead Temperature (Soldering, 10Sec.) .............. +300°C

LQFP-64 (TOP VIEW)
Q Packages
L24+

L23+

L9+

LB+

L7+

LB+

L5+

I
64

I
62

I
60

I
58

I
56

I
54

I
52

63
L.24-

61
L.23-

59

57

LB-

L9-

55

53

L22+

49

L.22·DISCNCT1

L.25-0

Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermallimitations and considerations of packages. All voltages are
referenced to GND.

50

LS-

LB-

L7-

I

51

L.2s.

47

L.21-

48

L.26-

RECOMMENDED OPERATING CONDITIONS

48

·DISCNCT2

L.26+

L.21+

45

L.27-

L.2O-

44

L.27+

L.21l+

43

STERMPWR

TRMPWR ............................... 2.7V to 5.25V

L19+

41

DIFSENS

40

PTERMPWR

REG
10

SGND

DIFFB

39

11

PGND

L18-

38

12

LVD

L18+

37

13

L10-

L17-

38

14

L10+

L17+

35

15

111-

L16-

34

16

L11+

L16+

33

L12+

17

L13+

18

19

Ll+

20

21

L3+

L.2+

22

23

24

25

L4+

26

27

L14+

28

29

L1s.

30

31

32

I

I

I

I

I

I

I

I

L12-

L13-

L1-

L2-

L3-

l4-

L14-

l1S-

'For the UCC5647, Pin 47 Is DISCNCTt and Pin 48 is
DISCNCT2.

ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications are for TRMPWR = 2.7V to 5.25V, TA

-

- O°C to +70°C , DISCNCTl - DISCNCT2 - OV for UCC5646 DISCNCTl - DISCNCT2 - open for UCC5647 , TA - TJ
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

LVD Mode

65

mA

Disabled Terminator

200

I1A

5.25

V

TRMPWR Supply Current Section
TRMPWR Supply Current
TRMPWR Voltage

2.7

1_25V Regulator Section
~

1.25V Regulator

-240mA

Regulator Source Current

VREG=OV

Regulator Sink Current

~

1.15

1.25

-240

-300

mA

VREG=3.3V

240

300

mA

IREG

240mA

1.35

V

1_3V (DIFSENS) Regulator Section
1.3V Regulator

-5mA ~ IOIFSENS ~ 50llA

1.2

1.3

1.4

V

Source Current

VDlFSENS = OV

-5

-8

-15

mA

Sink Current

VDlFSENS = 3.3V

50

200

I1A

3-113

UCC5646

ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications are for TRMPWR = 2.7V to 5.25V, TA
= O°C to +70°C , DISCNCT1 = DISCNCT2 = OV for UCC5646 DISCNCT1 = DISCNCT2 = open for UCC5647 TA = TJ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Differential Termination Section (Applies to each line pair 1-27)
Differential Bias Voltage
IDlFFBlmaxl
IOIFFBlminl
Differential Impedance

VOIFFB = +1 V; TA = 25°C (Note1)
VDlFFB = -1V; TA = 25°C (Note1)

100

125
9
-11.25
110

V
mA
mA

1.25

1.35

V
mA
mA

140

8.75
-8.75
165

10

400

20

3
60

7.955
-10
100

105

1.15

ZOIFF = (VDIFF1-VDIFF2 )

n

7mA

Common Mode Bias Voltage
ICM(max)
ICM(min)
Common Mode Impedance

Output Leakage in Disconnect
Output Capacitance
Single Ended GND SE Impedance

L+ and L- shorted together
VCM = 2V (Note 3)
VCM = 0.5V (Note 3)
ICM =

2.083
-2.083
110

1.5V
(/CM(max) -/CM(min»)

TRMPWR = OV to 5.25V, VLINE = 0.2V to 2.5V
Single Ended measurement to GND (Note 1)
1=10mA

Disconnect Control (DISCNCT1) or (DISNCNT2) Section
DISCNCT Threshold
DISCNCT Input Current
DIFFB Input Section
DIFFB SE to LVD Threshold
DIFFB LVD Range
DIFFB LVD to HPD Threshold

0.8
-10

1.5

0.5
0.7
1.9

DIFFB Input Current

-10

n
nA
pF

n

2.0

V

-30

itA

0.6

0.7

V

2.05

1.9
2.2

V
V

10

ItA

Note 1: IOIFF = Current into L-, with VOIFF applied to L-with respect to L+.
Note 2: VOIFFI = (VL-) - (VL+) with 2.SmA current sourced applied across L- and L+ (current into L-.)
VOIFF2= (VL-) - (VL+) with 4.SmA current sourced applied across L+ and L- (current into L+.)
Note 3: ICM = Sum of currents into L+ and L-, with VCM applied to both terminals with respect to ground.
Note 4: Guaranteed by design. Not 100% tested in production.

PIN DESCRIPTIONS
STRMPWR: 2.7 to 5.25 Volts power supply for all circuitry except the 1.25V regulator.
SGND: Ground reference for all circuitry except the
1.25V regulator.
PTRMPWR: 2.7 to 5.25 Volts power supply for the 1.25V
regulator.
PGND: Ground reference for the 1.25V regulator.
REG: Output of the internal 1.25V regulator; must be
connected to a 4.71lF bypass capacitor.
DIFSENS: Drives the SCSI bus DIFF SENSE line to 1.3V
to detect what types of devices are tied to the bus.

DIFFB: DIFF SENSE filter pin. Should be connected to
a 0.1 uF capacitor to GND and to a 20k resistor to the
SCSI bus.DIFF SENSE line.
DISCNCT1: Disconnect one controls termination lines
10-27 (control and low byte.)
DISCNCT2: Disconnect two controls termination lines
1-9 (high byte.)
LVD: TTL compatible status bit indicating when Low Voltage Differential voltage is present on DIFFB.
L 1- thru L27-: Negative lines for the SCSI bus.
L 1+ thru L27+: Positive lines for the SCSI bus.

3-114

UCC5646

APPLICATION INFORMATION

---------------,
~ L1+ UCC5646
:

~--------------'

I
Termpower

UCC5646

i

~

L1+

@

------1~ :1-

STRMPWR

::
•
•

S PTRMPWR

L9+

S
I

:

CONTROL LINES ( 9 ) :

I
I
I

I
I
I

L~~

I4.7I1F

=

I
r-f4ilI DISCNCT1

-

CONTROL AND
LOW BYTE

I

i

•

I

I

I

I

L1S+

~7

DATA (S) + PARITY LINES

i

L1B- 38

r@]

DISCNCT2

I
I

I
I
:

I
I

,,;. 0 :

1 PGND

L27-m

J-. !

HIGH SIDE

M
-

•
:

10 SGND
I

= :

REG

I
I

DATA (S) + PARITY LINES

DIFFB

I4.711F

=

I :
S
®
I

:

::
I

n
:

L1o-

DISCNCT1

•

s

I

~37 L1S+

CONTROL AND
LOW BYTE

=

:

:

@] L19+
@] L1~
I
I

•
•

DISCNCT2
HIGH SIDE

I

:

I

DIFSENS
DlFFB

L_-_-_r3
..9-- - - - - -

L.JVV20Vkv-_____

1"" ·

I

~

J-.
PGND~11
=

ciJ ;".

40 f - - - - ; - - - - - - ; - - - - - - 1 4 0

L--][-----~~9------J----~2A~AAk~

r~'

S

i

~L27-

I

DIFSENS

~

I
I

6

L1~~

Termpower

3S L1B-

I
I

L19+

PTRMPWR

L10+

I

::
I

STRMPWR

•
•

I

L10+B

L1o-~

I
I

I
•
[§]
L9+

~L~

I

.l. :-

i

L1- [ § J - - - - r l - - - - - - - - - - r l

O.lI1F

SGND

;

10
I
I

IREG

I

=

J

4.711F
UDG-98202

Figure 1. Application drawmg.

UNITRODE CORPORATION
7 CONTINENTAL BLVD.• MERRIMACK. NH 03054
TEL. (6031424-2410' FAX (603) 424-3460

3-115

~·UNITROCE

UC5661

Ethernet Coaxial Impedance Monitor
FEATURES

DESCRIPTION

• Compatible with IEEE 802.3 10Base5,
10Base2, and 10BaseT

The UC5661 is a monolithic integrated circuit which functions as an Ethernet Coaxial Impedance Monitor (CIM). This IC is intended to augment the
receive (RX) function of IEEE 802.3 Coaxial Transceiver Interface (CTI) circuits. The UC5661 implements a hardware algorithm to detect reflections
on the Ethernet coaxial cable or twisted pair which are caused by improper
network termination or physical medium damage. If a physical problem is
detected, the UC5661, whose receiver outputs operate in parallel with the
CTI, immediately squelches the receive data, preventing the propagation of
invalid network packets. During ordinary operation, the CIM RX outputs
enable at the beginning of the data packet preamble, making it transparent
to normal CTI functions. The valid data threshold, although preset for thick
and thin-wire Ethernets, may be adjusted with the addition of one or two
external resistors to meet 10BaseT requirements.

• Preset and Adjustable Data
Thresholds
• Protects DTE from Spurious Data
• Prevents Erroneous Transmission
Through Repeaters
• Detects Cable Termination Errors
• Detects Cable Impedance Errors

A secondary system design feature is provided by the UC5661. At the
completion of a normal data transmission, the CIM Squelch activates much
faster than typical transceiver ICs. The receiver outputs of the UC5661
have been designed to properly terminate the data packet, even with RX
data transformers as small as 16J.!H, possibly allowing for smaller and less
expensive system implementations. In these cases, end-of-packet squelch
overshoot will be held to less than 100mV.
'

BLOCK DIAGRAM

1-----------------------1
I
I

I
I

I
I
I

PGND
RX-

RXI

-=-230mV
RX+
PVEE

VNEG

VEE

I

L _______________________ J

I
I
I
I
I
UDG·95050

5/95

3-116

UC5661

CONNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS
Supply Voltage (PVEE,VEE) ....................... -15V
Input Voltage (RXI) ......................... +2V to -10V
Operating Temperature Range ............... O°C to +70°C
Junction Temperature (Note 1) ................... +125°C
Storage Temperature Range ............. -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ............. +300°C

OIL-8, (Top View)
J or N, Package

All currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermallimitations and considerations of packages.
Note 1: The devices are guaranteed by design to be
functional up to the absolute maximum junction
temperature.

PVEE

VEE

PGND

VNEG

RX+

GND

RX-

RXI

DC ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = O°C to 70°C,
VEE = PVEE = -9 OV and RL = 500 ohms , TA = TJ
PARAMETER

TYP

MAX

UNITS

Supply Current

Outputs Locked or Unlocked, Unloaded

TEST CONDITIONS

10

20

mA

Input Bias Current

RXI = OV

2

5

Input Shunt Resistance

RXI = -2V to OV

Input Shunt Capacitance

(Note 1)

VNEG (Valid Data Reference)

VNEG = open

RX Output Voltage High (Squelch)
RX Output Voltage Low (Enable)
Output Short Circuit

MIN

!IA

0.200

45

MD

3

4

pF

-980

-900

-830

mV

-1.2

-0.9

0

V

-6

-3.7

-3.2

V

-980

-900

-830

mV

200

230

300

mV

-150

RX+= RX-=9V

Valid Data Threshold
Data Reflection Threshold

mA

Note 1: Guaranteed by design. Not 100% tested in production.

AC ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = O°C to 70°C,
VEE = PVEE = -9 OV and RL= 500 ohms , TA = TJ
PARAMETER

TEST CONDITIONS

TEN RX Enable Delay

See Figures 1, 2

TDis RX Disable Delay

See Figures 1, 2

MIN
250

TYP

MAX

100

400

UNITS
ns

340

475

ns

TFS RX+ to RX- Falling Edge Skew

See Figures 1, 2

5

20

ns

TFR RX+ to RX- Rising Edge Skew

See Figures 1, 2

5

20

ns

TSOL RX Squelch Delay

See Figures 1, 3

230

2000

ns

TREL RX Release Delay

See Figures 1, 3

1150

1500

ns

500

-9V

Figure 1. Switching Test Circuit
3-117

UDG·95051

UC5661

r-----------------OV

RXI (SMHz)

----~~--~~------1.1V
R X + ----jf---------,
VOH(-1.2V)

------

VOL (-3.2V) - - -

-------

-------------------- --------- 10%
----90%

RX- -----------+,

TRS

TFS

UDG·95052

Figure 2. Input/Output Timing Diagram

- - - - - - - - - - - - - - - - - - - - O.4V

RXI (OV)

.....---.--OV
- - VNEG

-2.6V
5MHz

3.3MHz

1 '

TSQL

RX+/RX-

TREL - ,

-\1

-1. 2 vt"'-----VOH
\

-3.. 2V --\'-V_O_L_ _ _ _ ___

'-._ _ _ _ _-J.

UDG-95053

Figure 3. Short Detect Timing Diagram

3-118

UC5661

-9V

UT VOLTAGE
j INP
FR OM AUI

DC TO DC
CONVERTER

-

VEE

8

RX+

CA BlE

I
RX DATA
TO AUI
CABLE

RXI

~

CTI

1>1-

TXO

1

GND

x
o

<

-

RX-

---,---------,

u

~

II:

o

1kn

:1:

IUJ
Z

I
I
I

YRXI
1 PVEE
f-

I
I
I

UC5661
CIM

RX+

$-

RX- 4

I
I
I
I
2 PGND
I
I
6 _
GND
_ _ _ _ _ _ _ ---1I

a VEE

soon

50 on

"$"
UDG·95054

Figure 4. Typical Application

Figure 4 shows the UC5661 (SOl) being used with a Coaxial Transceiver Interface (CTI) device. The primary
function of the SOl is to detect LAN cable shorts (or other
impedance matching problems) and appropriately
squelch the RX outputs of the CTI device to prevent the
transmission of corrupted network data. The secondary
function of the SOl is to provide improved RX squelching
at the completion of a normal data transmission.
To perform the two functions, SOl uses two threshold
voltages, Oata Reflection Threshold (ORT), and the Valid

Oata Threshold (VOT). Ouring transmission SOl looks
for signal activity above ground and below ground. In
the event that the magnitude of the input voltage exceeds ORT the outputs will be locked within 2~s and will
remain locked for 0.5 to 1.5~s after the last edge below
ORT (see Figure 3). Ouring signal activity below ground
when the signal goes below VOT the outputs will unlock
within 400ns. While unlocked, if the input exceeds VOT
the outputs will lock within 250 to 475ns relative to the
last positive going edge (Figure 2).

UNITRODE CORPORATION
7 CONTINENTAL BLVD .• MERRIMACK, NH 03054
TEL. (603) 424-2410' FAX (603) 424·3460

3-119

~UNITRDDE

UCC5672
ADVANCE INFORMATION

Multimode (LVO/SE) SCSI 9 Line Terminator
FEATURES

DESCRIPTION

• Auto Selection Multi-Mode Single
Ended or Low Voltage Differential
Termination

The UCCS672 Multi-Mode Low Voltage Differential and Single Ended Terminator is both a single ended terminator and a low voltage differential terminator for the transition to the next generation SCSI Parallel Interface
(SPI-3). The low voltage differential is a requirement for the higher speeds
at a reasonable cost and is the only way to have adequate skew budgets.

• 2.7V to S.2SV Operation
• Differential Failsafe Bias

The UCCS672 is SPI-3, SPI-2, SPI and Fast-20 compliant. This device co~
mes in a TSSOP package to minimize the footprint.

• Built-in SPI-3 Mode Change Filter
Delay
• Master/Slave Inputs
• Supports Active Negation
• Standby (Disable Mode) SI1A
• 3pF Channel Capacitance

BLOCK DIAGRAM
SOURCE ONLY FROM TRMPWR AND THE ENABLED TERMINATORS

,,

I-----------------------------------------------~------------------~

TRMPWR

0--,

SOURCE 5 < 15mA
SINK 200~ MAXIMUM (NOISE LOAD)

OPEN CIRCUIT ON POWER OFF
OR
OPEN CIRCUIT IN A DISABLED
TERMINATOR MODE

+Voo

,

MSTR/SLV

1.3V ± -C.1V

,, DIFFSENS

DIGITAL FILTER

HIPD
LVD

1O.1~F:

-.l

LOW
FREQUENCY-=FILTER
50Hz-60Hz

':

SOURCE/SINK

,,
,,
,,
,,
,,
,
HS/GND~
,

.
REF 2,7V

REF 1.25V

.

,,

REGU~LATOR
•
~.--------------,

f---o

125

56mV

1----0
,
,
:

HIGH IMPEDANCE
RECEIVER EVEN
WITH POWER OFF

'

~
~

. __

.'.-o_~o--A.Nv------------'j t
'110

~

1

9~

SWITCHESUPA:ES~NGLE ~
1 :

10

DISCNCT~
,

ENDED SWITCHES DOWN ARE
LOW VOLTAGE DIFFERENTIAL

,,

REG

1

l1+

\

~~

,

=

SE

,,

~L1-

:

HS/GND
GND

110

L9+

i

SE GND
SWITCH

_

,

-------------------------------~------~
UDG·99093

04199

3-120

~UNITRODE

UCC5680
ADVANCE INFORMATION

Low Voltage Differential (LVD) SCSI 9 Line Terminator
FEATURES

DESCRIPTION

• Low Voltage Differential Termination

The UCC5680 Low Voltage Differential Terminator is a low voltage differential terminator for the next generation SCSI Parallel Interface (SPI-3).
The low voltage differential is a requirement for the higher speeds at a
reasonable cost and is the only way to have adequate skew budgets. The
UCC5680 is backwards compliant with SPI-2 (Ultra2) and compliant with
SPI-3 (Ultra3), (Ultra160/m).

• 2.7V to 5.25V Operation
• Differential Failsafe Bias
• Built-in SPI-3 Mode Change Filter
Delay

This device comes in a TSSOP package to minimize the footprint and with
a unique pin out that eliminate feed through requirements.

• Supports Active Negation
• Standby (Disable Mode) 5!lA
• 3pF Cha.nnel Capacitance

BLOCK DIAGRAM
SOURCE ONLY FROM TRMPWR AND THE ENABLED TERMINATIONS

1----------------------------------------------------------r-,
OPEN CIRCUIT ON POWER OFF

TRMPWR ~

2.7V to 5.25V

OR OPEN CIRCUIT IN A DISABLED
TERMINATOR MODE

I
I

I
I
I
I
I

I
I

1.3V±O.lV
HIGH POWER
DIFFERENTIAL

I

I

20k

DIFSENS

I
I
I

I
I
I

: DIFFB

LVD'
HIGH IMPEDANCE RECEIVER
EVEN WITH POWER OFF
O.7V>O.5V
SOURCE/SINK REGULATOR

I

SINGLE
ENDED

124

LOW
FREQUENCY
FILTER
50Hz-60Hz

56mV

+

...

04199

~:-----l-~---

r-,

52

I

•

I:
"--------...A;-" ------.rI
52

-

I

• ~2,

o---------'VV~ L1-

I

56mV

+
DISCNCT
I

I
I
I
I

~~1+

1011A

124

• 28 pin " , , , -

~

I

vvv

L,J

o--------WV---52

L9-

I

----- --1':----------------------------- ~_,
_c

3-121

L9+

[1JJ

DN-92

_UNITROCE

Design Note
UCC5630 SCSI Multimode (LVD/SE) Evaluation Board and List of Materials
By Paul Aloisi

a

The UCCS630 is high performance 9 line Multimode terminator designed to provide the lowest
capacitance and the lowest possible temperature
drift. It is designed for 3.3V or SV systems and will
operate over the range of 2.7V to S.2SV.
The demo board should be used at the end of the
bus, between the last device and the cable or as a
plug terminator at the end of the cable. Active terminators should be used at both ends of the cable.
Generally, they will be used between the controller
and the cable and the last device and the cable. If
they are used as a plug terminator, the second
connector becomes a stub effecting the capacitance load on the bus. The termination can be disabled on the demo card allowing the demo board
to be part of the bus path.
The demo board can be used to test the Unitrode
terminator versus drive or controller termination.
The demo board demonstrates how Unitrode termination can clean up problems on the bus.
The demo board layout below shows the UCCS630
9 line multimode SCSI termination with a separate
disconnect for the high byte (Switch 2) and the
control lines and the low byte (Switch 1). Termination should be disabled on all devices but the device at the ends of the cable.

The multi mode terminators automatically detect
the bus mode by placing 1.3V on the diff sense
line, then monitoring the diff sense line through an
R-C filter,(R1) 20k and (CS) O.1/lF, to filter out
noise down to SOHz on the bus. If the diff sense
line is below O.SV, the terminators are in single
ended mode (SE). If the diff sense line is between
O.7V and 1.9V, the terminators are in Low voltage
differential (LVD) mode. If the diff sense line is
above 2.1V, the terminator is in high impedance
mode. The demo board can not be used on a high
voltage differential (HVD) system. The terminator
mode can be monitored on pin 33 for single ended
mode, pin 34 for low voltage differential mode, and
pin 3S for when high impedance high voltage differential devices are detected. The outputs are not
valid when the terminators are in disconnect mode.
The connector pinning is defined in SCSI~3 SPI-2
P cable LVD.
The layout of the demo board is an attempt to
match the length and loading of the lines. Every
line has a feedthrough connection to the terminator, but the surface mount connector requires a
feedthrough on one side of every line. This is not
as critical on this 2 sided board since there is no
inner layer capacitance on the feedthroughs. On a

U1

SWITCH 2

SWITCH 1

HIGH BYTE ANO
PARITY

LOW BYTE AND
CONTROL

OFF
DISCONNECT

OFF
DISCONNECT

TERMINATION
ENABLED

TERMINATION
ENABLED

rnL..I__B_:_SE_1_---l
UDG·98167

Figure 1. Demonstration board layout
11198
3-122

DN-92

I-----~

~}1E(12)!

,
'
~-IE(ISJ!
,,
''
§-IEI141:
,
'

~~1~!
,
'
,

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'
~-DB(Pl):

OND 'n OND

~~
~+DB(1)

~,-

H'
'''
~+DB(4}
~'~.'

~''""''i

CP'~"'i
~'~'"'i
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$-0800

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cb+DB~ t

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""." "
.....
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[jj'~'·i

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~-DB(5)

:
:
,
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~-OB(7J!
,,
''

$'~I·i

~-DB(EI):

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®~"i

,,

''
~ONDl

:,. :
-$
WOND!

~.

:

~:i
T'
~FESV

HOND

~4N
~GND

$$~~

~-M9G
~-SEL

~-C/D

$-REQ
$~
$~

$,
'

§-DB(
, IOI:,
,
'
~-o&(111!
,
'
1... _____1

$-i

J:i
~TEFIMPI

®

~
~

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r$

$
$

~::!

$.o"i
$'''"i

$,"0 i

$'-i
$'-i
$~l~i

$_:~1~!

UDG-98166

Figure 1. UCC5630 Evaluation Board Schematic

3-123

DN-92
multilayer board, one extra feedthrough is more capacitance imbalance than allowed unless the clearance holes on the inner layers are enlargered.
Note the heat sink area for the UCC5630 terminators to dissipate heat. If a multilayer layout is used,
one feedthrough from each heat sink pin should be
connected to the ground plane instead of the heat
sink area on the outside layer.
The key indicators of signal integrity are the rising
and falling edges of the signals. The REO and
ACK signals are the highest speed signals until
Fast-800T. Reflections on lower speed signals up
to Fast-40 normally occur within the bit time. LVO
Fast-40 and beyond reflections can be 4 or more
bit times from the switch point.
For single ended signals, the rising edge should be
over 2.0V on the first step to guarantee data integrity and high speed operation or the bus should be
shortened to allow the reflected wave within the set
up time. If the falling edge of a signal overshoots
and returns to a higher level this is normally a sign
that the frequency response of the terminator is not
fast enough. This. is typical of a problem seen on
current mode terminators or terminators with the

disconnect switch in the wrong position. Some terminators look good when the signal is observed at
the end of the cable, but in the center of the bus
the signals can have serious problems.
LVO signals must transition at least 60mV beyond
the zero crossing, some receivers will require at
least 14 the signal in the opposite polarity to switch
at high speeds. If the signals do not reach the correct amplitude check the system impedance, it
should be above 85£1 differential when all the devices are installed on the bus.
Reflections can be isolated by the reflection time.
Signal round trip time is normally 10 nanoseconds
per meter on cables with standard PVC insulation.
Reflections from older devices or bad cables can
cause major problems, older designs paid little attention to capacitance and balancing stub lengths.
The long stubs and high capacitance will cause reflection problems.
For more information refer to the Unitrode L VD Design
Guide or the Single Ended Active Termination Design
Guide. Additional support help is available from Unitrode
local applications or 408-246-3100 extension 41 or 603-

429-8687.

Table 1. UCC5630 Evaluation Board List of Materials
Reference
Designator

Manufacturer

Description

C1, C2, C3, C4 Tantalum Capacitor 4.7.uF
C5
Ceramic Capacitor O.1.uF
R1
20.0K small Resistor
SW1
2 position dip switch
U1, U2, U3
IC

Panasonic
Panasonic
Panasonic
C+KComp.
Unitrode

UNITRODE CORPORATION
7 CONTINENTAL BLVD .• MERRIMACK, NH 03054
TEL. (503) 424-2410' FAX (503) 424-3450

3-124

Part Number
ECS-TICY4755
ECJ-3YFIA106Z
ERJ-SENF2002
SD02HOSK
UCC5630MWP

Selection Guides - Bus Bias Generators
Bus Bias Generators
SpecIal Functions
Bus Standard
Sink I Source Current
Page Number
+New Product

UC382
GTLlBTL

UNITRODE PART NUMBER
UC560
UCC561+
UC385
SCSI-1,2,3
SPI-2,3
GTLlBTL

Pgm/3A
PSl5-5

Pgm/5A
PSl5-35

4-1

-

~

UC563+

VME/VME64
300mA 1-750mA 200mA /-200mA 475mA 1-575mA
IF/4-3
IF/4-7
IF/4-1 0

-

[1JJ

[1J] UNITRDDE

4-2

~UNITRODE

UC560

27-Line SCSI Source/Sink Regulator
FEATURES

DESCRIPTION

• Complies with SCSI, SCSI-2, SCSI-3
SPI and Ultra SCSI (Fast-20)

The UC560 provides current for up to 27 lines of active termination for a
SCSI (Small Computers Systems Interface) parallel bus. The SCSI
standard requires active termination at both ends of the cable. The
UC560 is based on the UC5603 and UC5613 SCSI Active Terminators.
It uses the voltage regulator and internal logic circuits of those parts,
but has no termination circuits. The UC560 provides greater source current drive capability compared to the UC5603 and UC5613.

• 2.85V Regulated Output Voltage With
1.4% Tolerance
• Provides Current for up to 27 Lines of
Active Termination for SCSI Buses
• -750mA Sourcing Current for
Termination

The UC560 sink current maintains regulation with all active-negation
drivers negated. It provides a disconnect feature which disables the
regulator to greatly reduce standby power. Internal circuit trimming is
utilized for a 1.4% tolerance output voltage. Other features include thermal shutdown and current limit for short circuit conditions.

• +300mA Sinking Current for Active
Negation Drivers
• O.9V Dropout Voltage Regulator at
750mA and 2.75V Output

The UC560 is available in low thermal resistance versions of the industry standard 8-pin power SOIC, 5-pin TO-220 and 5-pin TO-263.

• 100flA Supply Current in Disconnect
Mode
• Current Limit and Thermal Shutdown
Protection
• Low Thermal Resistance Surface Mount
Packages

BLOCK DIAGRAM

,-------------------------------------,
I
I
I
I

I
I
I
I

I

I

I
I

I
I
I
I

TERMPWR
4.0V TO 6.0V 8
(4.75V NOMINAL)

OUT
2.85V

I
I
I
I
I
I
I
I
I
I
I
I
I

L____

+

4

2.85V REFERENCE

-------------~------------GND

ENBL

Pin Numbers refer to 8-pin DP package.
UDG·95136-1

4/98

4-3

UC560

~ONNECTION

ABSOLUTE MAXIMUM RATINGS
TERMPWR Voltage ................................ 7V
ENBL Voltage ............... , -O.3V to TERMPWR + 0.3V
Regulator Output Current. ...............•......... 1.4A
Power Dissipation ..................... : ... , ..... 2.5W
Storage Temperature .. ,:.......... , . ; . : .. -65·Cto +150·C
Junction Temperature .....•.... , ........ -55·C to +150·C
Lead Temperature (Soldering,,1 0 sec.) ........•..... +300·C

DIAGRAMS

$OIC-S (Top View)
DPPackage
TERMPWR
HS/GND

Cum:mts are positive into, negative out of the specified termi~
nsl. Consult Packaging Section of Databook for thermallimitations and considerations of packages.

HS/GND

N/e

RECOMMENDED OPERATING CONDITIONS

Note: Pins 2,3,6, and 7 are heat sinking pins. Pin 2 is the
connect point for electrical ground.

TERMPWR Voltage ........................ 4.0V to 6.0V
ENBL Voltage .; ....................... OV to TERMPWR

5-Pin TO-220 (Top View)
TPackage

5-Pin TO-263 (Top View)
TD Package

'. 4
[ )
3
2
.1

ENBL
N/C
GND
OUT,
TERMPWR

Note: TAB is ground.

Note: TAB is ground.

ELECTRICAL CHARACTERISTICS Unless otherwise specified, TA = O·C to 70·C, TERMPWR = 4.75V, ENBL = OV,
COUT = 47FC
.'!.Lt , TERMPWR = 47FT
. '!.Lt , A= TJ.
PARAMETER

TEST CONDITIONS '"

MIN

TYP

MAX UNITS

Supply Current Section
TERMPWR Supply Current
Power Down Mode

No Load

16

22

mA

lOUT = -700mA

710

750

mA

ENBL= 2.0V

100

140

!.LA

2.85

2.89

V

25

30

mV

Regulator Section
Regulator Output Voltage

25·C, No Load

Load Regulation

lOUT = 300mA to -750mA (Note 2)

2.81

Line Regulation

TERMPWR = 4.0V to 6.0V, No Load (Note 2)

10

20

mV

Dropout Voltage

lOUT = -750mA, VOUT = 2.75V

0.9

1.2

V

Short Circuit Current

VOUT=O.OV

Sinking Current

Vour=3.5V

500

600

mA

1

2

mA

-0.85

ENBL = 2.0V, VOUT = 3.0V
Thermal Shutdown
Thermal Shutdown Hysteresis

-1.3

A

1)

170

·C

(Note 1)

10

·C

I (Note

Shutdown Section
ENBL Threshold

1.1

1.4

Threshold Hysteresis

100

ENBL Output Current

-10

Note 1: Guaranteed by design. Not 100% tested in production.
Note 2: Tested at a constant junction temperature by low duty cycle pulse testing.

4-4

1.7

V
mV

-15

IlA

UC560

PIN DESCRIPTIONS
ENBL: Enable Bar pin. The ENBL function is active low,
and the pin will source 101lA typically when at ground
and TERMPWR is between 4V and 6V. The part will go
into disable mode if ENBL is above 1.4V typical, and will
turn back on when ENBL drops below 1.3V typical. The
part also greatly reduces TERMPWR current when disabled (100IlA typical).

rent to prevent damage. When the part is in disabled
mode (ENBL ~ 1.4V typical), the output goes to OV with
no external supply source on OUT. The part will sink current, though, if there is an external supply voltage applied to OUT when in disabled mode. For best
perfomance, a 4.71lF low ESR capacitor is recommended.

GND: Ground pin.

TERMPWR: Supply voltage pin. The pin should be decoupled with at least a 2.21lF low ESR output capacitor.
For best perfomance, a 4.71lF low ESR capaCitor is recommended. Lead lengths should be kept at a minimum.

OUT: 2.85V regulated output voltage pin. The part is internally current limited for both sinking and sourcing cur-

APPLICATIONS INFORMATION
1100

27 TERMINATION LINES

t-'VYV--

1100

18 TERMINATION LINES +--'v'Vlr-TERMPWR 8
TERMPWR 8

GND

UDG·96034

UDG·96033

Figure 1. Typical SCSI Bus Configuration Utilizing
UC560 Device

Figure 2. Typical Wide SCSI Bus Configuration
Utilizing UC560 Device

4-5

UC560

TYPICAL CHARACTERISTICS
--lOUT = -750mA - - - NO LOAD -lOUT = 300mA'

2.87
~ 2.86
:::t 2.85

I-

g

.'

+~--'-=----=---"'-~---__.;_;!_-=----+--_I
- ••• _

40

60

80

TEMPERATURE ee)

1.3

4

1.2

2

~ 1.1

S

.s

5

~

~

""-

20

-r----40

TEMPERATURE ee)

60

80

Figure 5. Load Regulation vs. Temperature
(lOUT = 300mA to -750mA)

Figure 3. VOUT vs Temperature

~,

.

,i

§

2.84 t=:j~:::t:::~~~j
2.83
2.82. +-----t--,----+----if-------1
2.81 + - - - - + - - - 1 - - - - - 1 - - - - - - 1
2.8 + - - - - + - - - \ - - - - - \ - - - - - - 1
20

,

.

.s

t~~~*;;;;::=t==~~;~

o

30
2!l
I
28
S 27
~
CJ'. :26
w
II: 25
c 24
23
22
21
20
0

;.

2.9 -,--------,-------'--.-----~---,--------,
2.89 +--~-+---,-\--~--\-~---'--j
2.88 +-----t---,---+--,-,----if-------1

0.9

-4

W

-6

z

0.7

-2

faII:
::::i

0.8

0

-8

-10

-

-12

0.6
0

20

40

60

o

80

TEMPERATURE ee)

Figure 4. Dropout Voltage vs. Temperature
(lOUT = -750mA, VOUT = 2.75V)

20

40

60

TEMPERATURE ee)

Figure 6. Line Regulation vs Temperature
(TERMPWR 4.0V to 6.0V)

=

UNITRODE CORPORATION
7 CONTINENTAL BLVD .• MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460

4-6

80

~UNITRODE

UCC561

Low Voltage Differential SCSI (LVD) 27 Line Regulator Set
FEATURES

DESCRIPTION

• SCSI SPI-2 LVD SCSI 27 Line Low
Voltage Differential Regulator

The UCC561 LVD Regulator set is designed to provide the correct references voltages and bias currents for LVD termination resistor networks
(475Q, 12Hl, and 475Q). The device also provides a 1.3V output for Diff
Sense signaling. With the proper resistor network, the UCC561 solution will
meet the common mode bias impedance, differential bias, and termination
impedance requirements of SPI-2 (Ultra2) and SPI-3 (Ultra3).

• 2.7V to 5.25V Operation
• Integrated Regulator Set for LVD
SCSI
• Differential Failsafe Bias

This device incorporates into a single monolith, two sink/source reference
voltage regulators, a 1.3V buffered output and protection features. The protection features include thermal shut down and active current limiting circuitry. The UCC561 is offered in 16-pin SOIC(DP) package.

BLOCK DIAGRAM

1------------------------------------- 1

,

I.

II

TRMPWR

o

I

REF1.3V

~
I----v

,

1.3V +/- O.1V

~

Y,

,,

~>---------~
,
1.7SV +/-SOmV

2.7V 

RPL=500k
RPL=200k

2

,Jl

+ m,..

In order to estimate the minimum timing capacitor, CT,
several things must be taken into account. For .example,
given the schematic below as a possible (and at this
point, a standard) application, certain external component values must be known in order to estimate CT(min).
Now, given the values of COUT, Load, RSENSE, VSS, and
the resistors determining the voltage on the IMAX pin,
the user can calculate the approximate startup time of
the node VOUT. This startup time must be faster than the
time it takes for CT to charge to 2.5V (relative to VSS),
and is the basis for estimating the minimum value of CT.
In order to determine the value of the s~nseresistor,
RSENSE, assuming the user has determined the fault current, RSENSE can be calculated by:
RSENSE

50mV
=-'FAULT

Figure 5. Possible level shift circuitry to interface to
the UCC1913.
5-20

UCC1913
UCC2913
UCC3913
APPLICATION INFORMATION (cont.)
Next, the variable IMAX must be calculated. IMAX is the
maximum current that the UCC1913 will allow through
the transistor, M1, and it can be shown that during
startup with an output capacitor the power MOSFET, M1,
can be modeled as a constant current source of value
IMAXwhere:
_ V1MAX
I
MAX---RSENSE

where VIMAX =voltage on pin IMAX.
Given this information, calculation of the startup time is
now possible via the following:
Current Source Load:

-Ivssl

GOUT
TSTART = --=:.::.:..---'.-.!I MAX -IWAD

Resistive Load:
TSTART

= GOUT - ROUT -

o (
-c,n
I

I I

IMAX - ROUT
)
MAX -ROUT - VSS

Once T START is calculated, the power limit feature of the
UCC1913 must be addressed and component values derived. Assuming the user chooses to limit the maximum
allowable average power that will be associated with the
circuit breaker, the power limiting resistor, RpL, can be
easily determined by the following:

VSS

OUTPUT
--------------------~

I

LOGIC
SUPPLY

SDIFLT
I
I
I
I

I
I

I
~

2011A

I
I
I
r

I
I
I
I
I

~--------------------------------------------------------~

VSS
UDG·99002

Figure 6. Typical application diagram.

5-21

UCC1913
UCC2913
UCC3913
APPLICATION INFORMATION (cont.)
R

Resistive Load:

_ PFET(avg)
PL -1J,1A e /MAX

CT(mln) =

IVSSI
SmA

3 e TSTART (31 J,1A e RpL

+ IVSSI- SV -IMAX e Rour)

where a minimum RpL exists defined by RpL(min) = - -

--~~~~----~~--~----~~--~~+

Finally, after computing the aforementioned variables,
the minimum timing capacitor can be derived as such:

3 e ROUT elVSSle C OUT

, SeR pL

.

SeR pL

Current Source Load:
CT(min) =

(3eTSTART e62l1AeRpL
10 e R pL

+ IVSSI...,. 10V)

SAFETY RECOMENDATION
Although the UCC3913 is designed to provide system
protection for all fault conditions, all integrated circuits
can ultimately fail short. For this reason, if the UCC3913
is intended for use in safety critical applications where
UL or some other safety rating is required, a redundant

safety device such as a fuse should be placed in series
with the device. The UCC3913 will prevent the fuse from
blowing for virtually all fault conditions, increasing system
reliability and reducing maintenance cost, in addition to
providing the hot swap benefits of the device.

UNITRODE CORPORATION
7 CONTINENTAL BLVD .• MERRIMACK. NH 03054

TEL. (603) 424-2410 FAX (603) 424-3460

5-22

~UNITROCE

UC1914
UC2914
UC3914

5V to 35V Hot Swap Power Manager
FEATURES

DESCRIPTION

• 5V to 35V Operation

The UC3914 family of Hot Swap Power Managers provides complete
power management, hot swap and fault handling capability. Integrating this
part and a few external components, allows a board to be swapped in or
out upon failure or system modification without removing power to the hardware, while maintaining the integrity of the powered system. Complementary output drivers and diodes have been integrated for use with external
capacitors as a charge pump to ensure sufficient gate drive to the external
NMOS transistor for low ROSON. All control and housekeeping functions
are integrated. and externally programmable and include the fault current
level, maximum output sourcing current, maximum fault time and average
power limiting of the extemal FET. The UC3914 features a duty ratio current limiting technique, which provides peak load capability while limiting
the average power dissipation of the external pass transistor during fault
conditions. The fault level is fixed at 50mV with respect to VCC to minimize
total dropout. The fault current level is set with an extemal current sense resistor. The maximum allowable sourcing current is programmed by using a
resistor divider from VCC to REF to set the voltage on IMAX. The maximum
current level, when the output appears as a current source is
(VCC - VIMAX)/RsENSE.

• Precision Maximum Current Control
• Precision Fault Threshold
• Programmable Average Power
Limiting
• Programmable Overcurrent Limit
• Shutdown Control
• Charge Pump for Low ROSON
High-Side Drive
• Latch Reset Function Available
• Output Drive VGS Clamping
• Fault Output Indication
• 18 Pin OIL and SOIC Packages

(continued)

BLOCK .DIAGRAM
REF

OSC

IMAX
~

--------------~

I
I
I

50,,:V.

r!,

_11~v'cc

CHARGE PUMP
(VOL TAGE TRIPLER)

I
I
I

VPUMP
TO LINEAR
AMPLIFIER
VPUMP
iFAULT 1 0 1 - - - - - 0 < 1 - - - - - - - - - ,

UNOERVOL TAGE
LOCKOUT 4V/3.8V

so 4 1 - - - - - - - - - - - '
I
I
I
I

. GN,O

"i

I
I
I

rh--., .

i 1

AVERAGE
POWER LIMITING

I
IL _______________________ _

-------------------------~
LR

02199

I
:

5-23

UDG-95134-2

UC1914
UC2914
UC3914
ABSOLUTE MAXIMUM RATINGS

CONNECTION DIAGRAM

Input Supply Voltage, VCC ......................... 40V
Maximum Forced Voltage
SO .......................................... 12V
IMAX ....................................... VCC
LR .........•, .......................•....' ... ,.12V
Maximum Current
FAULT .•.................•....•............ 20mA
PLiM .............•.•...................... 10mA
Maximum Voltage, FAULT ......•.................. 40V
Reference Output Current ............... Internally Limited
Storage Temperature ...•............... -65·C to +150·C
Junction Temperature ................... -55·C to +150·C
Lead Temperature (Soldering, 10 sec.) ............. +300·C

DIL·18, SOIC-18 (Top View)
N or J Package, OW Package

Unless otherwise indicated, voltages are referenced to ground.
Currents are positive into, negative out of specified terminal.
Consult Packaging Section of Databook for thermal limitations
and considerations of package.

DESCRIPTION (cont.)
When the output current is le~s than the fault level, the
external output transistor remains switched on. When the
output current exceeds the fault level, but is less than the
maximum sourcing level programmed by IMAX, the output remains switched on, and the fault timer starts to
charge CT, a timing capacitor. Once CT charges to 2.5V,
the output device is turned off and CT is slowly discharged. Once CT is discharged to O.5V, the IC performs
a retry and the output transistor is switched on again.
The UCag14 offers two distinct reset modes. In one

mode with LR left floating or held low, the IC will repeatedly try to reset itself if a fault occurs as described
above. In the second mode with LR held high, once a
fault occurs, the output is latched off until either LR is
!Q.ggled low, the part is shutdown then re-enabled using
SO, or the power to the part is turned off and then on
again.
This part is offered in both 18 pin OW Wide-Body (SOl C)
and Oual-In-Line (OIL) packages.

ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = O·C to 70·C for the UC3914, -40·C to 85·C for
the UC2914, and -55·C to 125·C for the UC1914. VCC = 12V, VPUMP = VpUMP(max), SO = 5V, CP1 = CP2 = CPUMP = 0.01I1F.
,

~=~

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VCCSectlon
Icc

(Note 2)

8

15

mA

VCC = 35V, (Note 2)

12

20

mA

500

900

ItA

4

4.4

V

100

200

350

mV

TJ = 25·C, with respect to VCC

-55

-SO

-45

mV

Over operating temperature, with respect to VCC

-57

-50

-42

mV

1

3

-100

-60

Shutdown Icc

SD=OV

UVLO

Turn on threshold

UVLO Hysteresis
Fault Timing Section
Overcurrent Threshold
IMAX Input Bias

2

3

4.5

ItA
ItA
ItA

-6

-3

-1.5

mA

CT Fault Threshold

2.25

2.5

2.75

V

CT Reset Threshold

0.45

0.5

0.55

V

1.5

3

4.5

%

CT Charge Current

CT= 1V

CT Discharge Current

CT=1V

CT Charge Current

CT = 1V, Overload condition

Output Duty Cycle

-140

Fault condition, IPL = 0

5-24

UC1914
UC2914
UC3914
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = O°C to 70°C for the UC3914, -40°C to 85°C for the
UC2914, and -55°C to 125°C for the UC1914. VCC = 12V, VPUMP = VpUMP(max), SD = 5V, CPl = CP2 = CPUMP = O.OIIlF.
TA=TJ
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Output Section
OUT High Voltage

VOUTS = VCC, VPUMP = VPUMP max, with respect to
VPUMP

-1.5

-1

V

OUT High Voltage

VOUTS = VCC, VPUMP = VPUMP max, lOUT = -2mA,
with respect to VPUMP

-2

-1.5

V

OUT Low Voltage

lOUT = 0
IOUT=5mA
lOUT = 25mA, Overload Condition, VOUTS = OV
11.5

0.8

1.3

1

2

V
V

1.2

1.8

V

OUT Clamp Voltage

VOUTS=OV

13

14.5

V

Rise Time

COUT = 1nF (Note 1)

750

1250

ns

Fall Time

COUT= lnF (Note 1)

250

500

ns

Charge Pump Section
OSC, OSCB Frequency
OSC, OSCB Output High

losc=-5mA

60

150

250

kHz

10

11

11.6

V

0.2

0.5

V

22.5

V

OSC, OSCB Output Low

losc=5mA
OSC, OSCB Output Clamp Voltage VCC =25

18.5

20.5

OSC, OSCB Output Current Limit

High Side Only

-20

-10

-3

mA

Pump Diode Voltage Drop

IDIODE = 10mA, Measured from PMP to PMPB, PMPB to
VPUMP

0.5

0.9

1.3

V

PMP Clamp Voltage

VCC =25

18.5

20.5

22.5

V

VPUMP Maximum Voltage

VCC = 12, VOUTS = VCC, Voltage Where Charge Pump
Disabled

20

22

24

V

VCC = 35V, VOUTS = VCC, Voltage Where Charge
Pump Disabled

42

45

48

V

VCC = 12, VOUTS = VCC, Voltage Where Charge Pump
Re-enabled

0.3

0.7

1.4

V

0.25

0.7

1.4

V

-15

0

15

mV

60

80

IMAX = OUT, SENSE = VCC, with respect to VCC

-20

0

20

mV

IMAX = OUT, SENSE = REF, with respect to REF

-20

VPUMP Hysteresis

VCC = 35V, VOUTS = VCC, Charge Pump Re-enabled
Linear Current Section
Input Offset Voltage
Voltage Gain
IMAX Control Voltage

dB

0

20

mV

1.5

3.5

IlA

-2.25

-2

-1.75

V

12.5

20

50

mA

SENSE Input Bias
Reference Section
REF Output Voltage

With respect to VCC

REF Current Limit
Load Regulation

IVREF = 1mA to 5mA

25

60

mV

Line Regulation

VCC = 5V to 35V

25

100

mV

Shutdown Section
Shutdown Threshold

1.5

2

V

Input Current

SD=5V

0.6

150

300

IlA

Delay to Output

(Note 1)

0.5

2

/lS

100

200

mV

10

500

nA

Fault Section
Fault Output Low

IFAULT = lmA

Fault Output Leakage

VFAULT= 35V

I
5-25

UC1914
UC2914
UC3914
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = O°C to 70°C for the UC3914, -40°C to 8SoC for the
UC2914, and -SSOCto 12SoC for the UC1914. VCC= 12V, VPUMP=VpUMP(max), SD = SV, CP1 = CP2 = CPUMP= 0.01I1F.
TA-TJ

-

'PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

Latch Section
LR threshold

High to Low

Input Current

LR=SV

0.6

1.4

2

V

SOO

7S0

I1A

Power Limiting Section
Duty Cycle Control

In Fault, IpLIM = 200/.IA
In Fault, IpLiM = 3mA

I

%
%

0.6

1.3

2.0

O.OS

0.12

0.2

SOO

12S0

ns

-2S0

""200

-1S0

mV

Overload Section
Delay to Output

(Note 1)

Threshold

Respect to IMAX

Note 1: Guaranteed by design. f!Jot 100% tested in production.
Note 2: A mathematical averaging is used to determine this value. See Application Section for more information.

PIN DESCRIPTIONS
CT: A capacitor is connected to this pin in order to set
the maximum fault time. The minimum fault time must be
more than the time to charge external load capacitance.
The fault time is defined as:

2-CT

TFAULT=-ICH

where ICH = 100/1A + IpL, where IpL is the current into the
power limit pin. Once the fault time is reached the output
'will shutdown for a time given by:

_2-CT
Tso --,-lOIS

where lOIS is nominally 3/1A.
FAULT: Open collector output which pulls low upon any
of the following conditions: Timer fault, Shutdown, UVLO.
This pin MUST be pulled up to VCC or another supply
throligh a suitable impedance.
'
,
GNO: Ground reference for the IC.
IMAX: This pin programs the maximum allowable
sourcing current. ,Since REF is a -2V reference (with respect to YCC), a voltage divider can be derived from
VCC to REF in order to gen,erate the program level for
the IMAX pin. The current level at which the output appears as a current source is equal to the voltage on the
'IMAX pin, with respect to VCC, divided by the current
sense resistor. If desired, a controlled current startup can
be programmed with a capacitor on IMAX to vce.
LR: If this pin is held high afld a fault occurs, the timer
will be prevented from resetting the fault latch when CT is
discharged below the reseCcomparator threshold. The
part will not retry until this pin is brought to a logic low or

a power-on-reset occurs. Pulling this pin low before the
reset time is reached will not clear the fault until the reset
time is reached. Floating or holding this pin low will result
in the part repeatedly trying to reset itself if' a fault occurs.
OUT: Output drive to the MOSFET pass element. Internal clamping ensures that the maximum VGS drive is
15V.
OSC, OSCB: Complementary output drivers for intermediate charge pump stages. A 0.0111F capacitor should be
placed between OSC and PMP, and OSCB and PMPB.
PLIM: This feature ensures that the average MOSFET
power dissipation is controlled. A resistor is connected
from this pin to VCC. Current will flow into PLiM which
adds to the fault timer charge current, reducing the duty
cycle from the typical 3% level. When IPL» 100l1A then
the average MOSFET power dissipation is given by:
PFET_AVG = IMAX - 3· 10-6 -RpL.
PMP, PMPB: Complementary pins which couple charge
pump capacitors to internal diodes and are used to provide charge to the reservoir capacitor tied to VPUMP.
Typical capacitor values used are 0.01I1F.
REF: -2V reference with respect to VCC used to program the IMAX pin voltage. A 0.111F ceramic or tantalUm
capacitor MUST be tied between this pin and VCC to ensure proper operation of the Chip.
so: When this TIL compatible input is brought to a logic
low, the output of the linear amplifier is driven low,
FAULT is pLilied low and the IC is put into a low power
mode. The ABSOLUTE maximum voltage that can be
placed on this pin is 12V.

5-26

UC1914
UC2914
UC3914
PIN DESCRIPTIONS (cont.)
SENSE: Input voltage from current sense resistor. When
there is greater than 50mV across this pin with respect to
VCC, a fault is sensed and CT begins to charge.
VCC: Input voltage to the IC. Typical voltages are 4.5V to
35V. The minimum input voltage required for operation is
4.5V.

VOUTS: Source connection of external N-channel MOSFET and sensed output voltage of load.
VPUMP: Charge pump output voltage. A capacitor
should be tied between this pin and VOUTS with a typical value being 0.01~F.

TYPICAL CHARACTERISTIC CURVES
Linear Amp VIO VS. Temperature

Fault Threshold

3.5 , - - - - - - - - - - - - - - -

~

3 +------------,~---"'------~
2.5 + - - - - -______
-~~------

0'
...J

~ 2+-~-----,~~~~--------

o

I

-50
II: -50.5
j!: -51
~
~ -51.5
u: -52

1+------------0.5 + - - - - - - - - - - - - +--,--.--,-~-,--,--,

-55 -40 0
25 70 85
TEMPERATURE (0C)

VCC - REF vs Temperature

2.04 - , - - - - - - - - - - -

t)

+------r-~...__---

2.03

+-------;;~----~--

~2.025

+---------+---

>

~

l-

2.035

-96 + - - - - - - - - - - - -

1 -100 + - - - - - - - - - - - ~

w

-104 +------'....-------------,_

c::: 2.02 + - - - - - - - - - - + - -

-108 +-_ _~----____::::*_--

2.015 + - - - - - - - - - 2.01 +--,-------,-,-----.-,----,---,

-112 +-----,--r---==r---,--r--,-----,
-55 -40 0 25 70 85 125
TEMPERATURE (OC)

-55 -40 0 25 70 85 125
TEMPERATURE (DC)

IMAX & SENSE Input Bias VS. Temperature
..... SENSE INPUT BIAS -IMAX INPUT BIAS

CT IDISCHARGE VS. Temperature

3.7 - , - - - - - - - - - - - -

13.6 +-------:~"",......,-----­

2 ,--------------

1V +VCT

\tOUTS) -IMAX _

..

RPL + 3J,IA

. (vce - VOUTS)

= IMAX - RPL - 3J,IA

where VCT is the voltage on the CT pin. For VOUTS < 1V
+ VCT the common mode range of the power limiting cir-

The average power is limited by the programmed IMAX
current and the appropriate value for RpL.

5-30

UC1914
UC2914
UC3914

APPLICATION INFORMATION (cont.)
lOUT

OUTPUT
CURRENT

IMAX
IFAULT

-

I I
I I

OA
sv

LR
VOLTAGE
OV
VeT
CT
VOLTAGE

:...j

I I
1--1

IO(NOM)

I

I I I

I

I
I
I
I
I

I
I
I
I
I

I
I
I
I
I

I
I
I
I
I

I
I
I
I
I

I

I

I

I

II

I
I
I
I
I

II
II
II
II
II

2.SV

O.SV
OV
VCC
OUTPUT
VOLTAGE
VOUTS

I

I

I

II
II

I---r----r-II-~---

I
I
I
II
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
II
I
I ______~
OV ~~_L~_ _~I_ _ _ _ _ _- L__~~~
10

14

11 1213

15

Ie

17

UDG-97055

1819

to: Normal conditions - output current is nominal, output
voltage is at positive rail, VCC

t4: Reset comparator threshold reached but no retry

t1: Fault control reached - output current rises above the

t5: LR toggled low, NMOS turned on and sources cur-

programmed fault value, CT begins to charge with ==

rent to load.

100llA + IPL.

t6 = t3

t2: Maximum current reached - output current reaches

t7: LR toggled low before VCT reaches reset comparator threshold, causing retry.

the programmed maximum level and becomes a constant current with value IMAX.
b: Fault occurs - CT has charged to 2.5V, fault output
goes low, the FET turns off allowing no output current to
flow, VOUT discharge to GND.

since LR pin held high.

ta: Since LR toggled low during present cycle, NMOS
turned on and sources current to load.

t9 = to: Fault released, normal condition - return to normal operation of the hot swap power manager.

Figure 3b. Typical timing diagram utilizing LR (Latch Reset) function.

5-31

UC1914
UC2914
UC3914
APPLICATION INFORMATION (cont.)
Overload Comparator
The linear amplifier in the UC3914 ensures that the external NMOS does not source more than the current
IMAX, defined above as:
I

_ VCC - VIMAX'
MAX' -

capacitor, M1 can be modeled as a constant current
source of value IMAX where:
I

_ VCC - VIMAX'
MAX' -

RSENSE

Given this information, calculation of startup time is now
possible via the following:

RSENSE

In the event that output current exceeds the programmed
IMAX by more than 200mV/RSENSE, the output of the linear amplifier will immediately be pulled low (with respect
to VOUTS) providing no gate drive to the NMOS, and
preventing current from being delivered to the load. This
situation could occur if the extemal NMOS is not responding to a command from the IC or output load conditions change quickly to cause an overload condition
before the linear amplifier can respond. For example, if
the NMOS is sourcing current into a load and the load
suddenly becomes short circuited, an overload condition
may occur. The short circuit will cause the VGS of the
NMOS to immediately increase, resulting in increased
load current and voltage drop across RSENSE. If this drop
exceeds the overload comparator threshold, the amplifier
output will be quickly pulled low. It will also cause the CT
pin to begin charging with 13, a 3mA current source (refer
to Figure 2) and continue to charge until approximately
one volt below VCC, where it is clamped. This allows a
constant fault to show up on FAULT and since the voltage on CT will only charge past 2.5V in an overload fault
condition, it can be used for detection of output NMOS
failure or to build redundancy into the system.

Current Source Load:
T

_ C LOAD e VCC
START - I MAX -I LOAD

Resistive Load:
TSTART =-RLOAD eCLOAD e£ne(1-

VCC
)
1MAX' eRLOAD

The only remaining external component which may affect the minimum timing capacitor is the optional power
limiting resistor, RpL. If the addition of RpL is desirable,
its value can be determined from the "Fault Timing" section above. The minimum timing capacitor values are
now given by
Current Source Load:
10 -4 'eR pL +VCC]
-CTmin=2eTSTART e [

Estimating Minimum Timing Capacitance

2eRpL

R2

R1

The startup time of the IC may not exceed the fault time
for the application. Since the timing capacitor, CT, determines the fault time, its minimum value can be determined by calculating the startup time of the IC. The
startup time is dependent upon several external components. A load capacitor, CLOAD, should be tied between
VOUTS and GND. Its value should be greater than that
of CPUMP, the reservoir capacitor tied from VPUMP to
VOUTS (see Figure 4). Given values of CLOAD, Load,
RSENSE, VCC and the resistors determining the voltage
on IMAX, the user can calculate the approximate startup
time of the node VOUT. Thistime must be less than the
time it takes for CT to charge to 2.5V. Assuming the user
has determined the fault current, RSENSE can' be calculated by:

2

vcc

2~----4
RSENSE

SENSE 1 7 " - - -.....

ourd!ll-------lle-. M1
I
I

-rr---; --

YOurs

VPUMP
L.. - - -

~prM~

VOUT

121---~---4

I

---'

CLOAD

50mV
RSENSE = - IFAULT
UDG-97056

IMAX is the maximum current the UC3914 will allow
through the transistor M1. During startup with an output

Figure 4. Estimating minimum timing capacitor.

5-32

UC1914
UC2914
UC3914
APPLICATION INFORMATION (cont.)
Resistive Load:

output current of the FET, will exponentially decay from
VCC to the desired value set by R1 and R2. The output
current of the MOSFET will be controlled via soft start as
long as the soft start time constant ('Css) is much greater
than the charge pump time constant 'Ccp, given by

CTmin=

(10-4. R pL + Vcc -

(lMAX • R WAD ))· TSTART

2.R pL

[
-TsTART
+ I MAX· (R LOAD )2 • CLOAD.1_eRLOADoCwAD
2.R pL

1

'Css =(R11IR2).Css

.

Minimizing Total Dropout Under Low Voltage
Operation

Output Curr!!nt Softstart

The external MOSFET output current can be increased
at a user·defined rate to ensure that the output voltage
comes up in a controlled fashion by adding capacitor
Css, as sAown in Figure 5. The chip does place one con·
straint on the soft start time and that is that the charge
pump time constant has to be much less than the softstart time constant to ensure proper soft start operation.
The time constant determining the startup time of the
charge pump is given by:

In a typical application, the UC3914 will be used to control the output current of an external NMOS during hot
swapping situations. Once the load has been fully
charged, the desired output voltage on the load, VOUT,
will be required to be as close to VCC as possible to
minimize total dropout. For a resistive load, RLOAD, the
output voltage is given by:

V.OUT

R LOAD

=

RWAD +RSENSE
'Ccp = ROUT •

CPUMP

ROUT is the output impedance of the charge pump given
by:
'
1

ROUT = ------,,fpUMP • CP

where fpUMP is the charge pump frequency (125kHz) and
CP = CP1 = CP2 are the charge pump flying capacitors.
For typical values. of CP1, CP2 and CPUMP (O.01IlF) and
a switching frequency of 125kHz, the output impedance
is 800Q and the charge pump time constant is 81ls. The
charge pump should be close to being fully charged in 3
time constants or 241ls. By placing a capacitor from VCC
toIMAX, the voltage at IMAX, which sets the maximum

"cc

, . v'

+ RdsON

RSENSE was picked to set the fault current, IFAULT.
RdsON, the on-resistance of the NMOS, should be made
as small as possible to ensure VOUT is as close to VCC
as possible. For a given NMOS, the manufacturer will
specify the RdsONfor a certain VGS (maybe 7V to 10V).
The source potential of the NMOS is VOUT. In order to
ensure sufficient VGS, this requires the gate of the
NMOS, which is the output of the linear amplifier, to be
many vo.lts higher than VCC. The UC3914 provides the
capability to generate this voltage through the addition of
3 capacitors, CP1, CP2 and CPUMP as shown in Figure
6. These capacitors should be used in conjunction with
the complementary output drivers and internal diodes included on-chip to create a charge pump or voltage

C1

OSC
6

I

:

REF

~OSC
CP1 ,.i..,
T'-------1!J
PMP

IMAX

I

VOUTS

I

7

~OSCB
CP2 ,l-,
T~

PMPB

--------,
I
I
I
I
I
I
I
I
I
I
I

____________________ J

VPUMP

~------------------~
Figure 5. MOSFET soft start diagram.

UDG-97058

UDG-98160

Figure 6. Charge pump block diagram.
5-33

UC1914
UC2914
UC3914
APPLICATION INFORMATION (cont.)
tripler. The circuit boosts VCC by utilizing capacitors
CP1, CP2 and CPUMP in such a way that the voltage at
VPUMP approximately equals (3· Vee) - (5· VOIOOE), almost tripling the input supply voltage to the chip.
On each complete cycle, CP1 is charged to approximately Vee - VDlOOE (unless Vee is greater than 15V
causing internal clamping to limit this charging voltage to
about 13V) ~hen the output Q of the toggle flip flop is
low. When Q is transitioned low (and Q correspondingly
is brought high), the negative side of CP2 is pulled to
ground, and CP1 charges CP2 up to about (2 • Vee - 3 •
VOIOOE). When
is toggled high, the· negatjve side of
CP2 is brought to (Vee -VOIOOE). Since the voltage
across a capacitor cannot change instantaneously with
time, the. positive side of the capaCitor swings up to (3 •
Vee - 4 • VOIOOE). This charges CPUMP up to (3 • Vee 5· VOIOOE).

a

The maximum output voltage of the linear amplifier is actually less than this because of the ability of the amplifier
to swing to within approximately 1V of VPUMP. Due to inefficiencies of the charge pump, the UC3914 may not
have sufficient gate drive to fully enhance a standard
power MOSFET when operating at input voltages below
7V. Logic Level MOSFETs could be used depending on
the application but are limited by their lower current capability. For applications requiring operation below 7V there
are two ways to increase the charge pump output volt-

age. Figure 7 shows the typical tripler of figure 6 enhanced with three external schottky diodes. Placing the
schottky diodes in parallel with the internal charge pump
diodes decreases the voltage drop across each diode
thereby increasing the overall efficiency and output voltage of the charge pump.
Figure 8 shows a way to use the existing drivers with external diodes (or Schottky diodes for even higher pump
voltages but with additional cost) and capaCitors to make
a voltage quadrupler. The additional charge pump stage
will provide a sufficient pump voltage (VPUMP = 4 • Vee7 • VOIOOE) to generate the maximum VGs. Operation is
similar to the case described above. This additional. circuitry is not necessary for higher input voltages because
the UC3914 has internal clamping which only allows
V PUMP to be 10V greater than Yours.
Input
Voltage
{'LCC)
4.5
5
5.5
6
6.5
7
9
10

Internal
Diodes
(vosl
4.57
5.8
6.6
7.6
8.7
8.8
9.2
9.3

External
Quadrupler
Schottky
Diodes (Vos) iVos)
6.8
8.7
7.9
8.8
8.6
8.9
8.8
9
8.8
9
9
9
9.4
9.1
9.4
9.3

Table 1. UC3914 charge pump characteristics.
Table 1 characterizes the UC3914 charge pump in its
standard configuration, with external schottky diodes,
and configured as a voltage quadrupler. Please note:
The voltage quadrupler is unnecessary for input voltages
above 7.0V due the internal clamping action.

ICC Specification

UDG·98204

Figure 7. Charge pump block diagram.

The ICC operating measurement is actually a mathematical calculation. The charge pump voltage is constantly being monitored with respect to both Vee and
Yours to determine whether the pump requires servicing. If there is insufficient voltage on this pin, the charge
pump drivers are alternately switched to raise the voltage of the pump (see Fig. 9). Once the voltage on the
pump is high enough, the drivers and other charge pump
related circuitry are shutdown to conserve current. The
pump voltage will decay due to internal loading until it
reaches a low enough level to tum the drivers back on.
The chip requires significantly different amounts of curJent during these two modes of operation and the following mathematical calculation is used to figure out the
average current:
5-34

UC1914
UC2914
UC3914
APPLICATION INFORMATION (cont.)
ICCORIVERS(on) • TON

+ ICCORIVERS(off)
+ TOFF

• TOFF

ICC=--~--~~~--~----~~----

TON

CP2

02

Since the charge pump does not always require servicing, the ,user may think that the charge pump frequency
is much less than the datasheet specification. This is not
the case as the free-running frequency is guaranteed to
be within the datasheet limits. The charge pump servicing frequency can make it appear as though the drivers
'are operating at a much lower frequency.

CP1

CP3

01

r-

2

--VCC

I
I

6

----0::---,
PMPB I

OSC

TOGGLE
FLIP FLOP

I
I

~PMP

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _

~

I

7 VPUMP
TCPUMP

I

I
I
I
I
I
I
I
I
I
I

IL _______________________ I
~

TO VOUT

UDG-97059

Figure 8. Low voltage operation to produce higher
pump voltage

PUMP
PUM1 LOWER LEVEL

L
i "PUMP"
___•.L~
: -SE~ CING FREQUENCY ----rl0SCILLATOR FREQUENCY
:

:

,

OSC

,

:

'r-

-,-

-

OSCB

~ TON-~1~4----TOFF-----+l~1

....
TIME

UDG-98144

Figure 9. Charge pump waveforms.

SAFETY RECOMMENDATIONS
Although the UC3914 is designed to provide system protection for all fault conditions, all integrated circuits can
ultimately fail short. For this reason, if the UC3914 is intended for use in safety critical applications where UL or
some other safety rating is required, a redundant safety
5-35

device such as a fuse should be placed in series with
the device. The UC3914 will prevent the fuse from blowing in virtually all fault conditions, increasing system reliability and reducing maintainence cost, in addition to
providing the hot swap benefits of the device.

UC1914
UC2914
UC3914
APPLICATION INFORMATION (cont.)

vee

FAULT=

SOmV

RFAULT:

I
TO

vee

I
I
I
I
I

fu
-=-=I

~---------------~-------VO\lT
UDG-98194

Figure 10. Typical application.

UNITRODE CORPORATION
7 CONTINENTAl BLVD.• MERRIMACK, NH 03050\
TEL. (603) 424-2410@ FAX (603) 424-3460

5·36

~UNITRDDE

UCC2915
UCC3915

15V Programmable Hot Swap Power Manager

PRELIMINARY

FEATURES

DESCRIPTION

• Integrated 0.15 Ohm Power
MOSFET

The UCC3915 Programmable Hot Swap Power Manager provides complete power management, hot swap capability, and circuit breaker functions. The only external component required to operate the device, other
than power supply bypassing, is the fault timing capacitor, CT. All control
and housekeeping functions are integrated, and externally programmable.
These include the fault current level, maximum output sourcing current,
maximum fault time, and startup delay. In the event of a constant fault, the
Internal fixed 2% duty cycle ratio limits average output power.

• 7V to 15V Operation
• Digital Programmable Current Limit
from OA to 3A
• 100j.lA Icc when Disabled
• Programmable ON Time

The internal 4 bit DAC allows programming of the fault level current from 0
to 3A with 0.25A resolution. The IMAX control pin sets the maximum
sourcing current to 1A above the trip level or to a full 4A of output current
for fast output capacitor charging.

• Programmable Start Delay
• Fixed 2% Duty Cycle
• Thermal Shutdown

When the output current is below the fault level, the output MOSFET is
switchid ON with a nominal ON resistance of 0.15Q. When the output cur~
rent exceeds the fault level, but is less than the maximum sourcing level,
the output remains switched ON, but the fault timer starts, charging CT.
Once CT charges to a preset threshold, the switch is turned OFF, and remains OFF for 50 times the programmed fault time. When the output current reaches the maximum sourcing level, the MOSFET transitions from a
switch to a constant current source.

• Fault Output Indicator
• Maximum Output Current can be set
to 1A above the Programmed Fault
Level or to a full 4A
• Power SOIC and TSSOP, Low
Thermal Resistance Packaging

BLOCK DIAGRAM

,---------------------------------------------,
I
I
v~

I
H=4A
IMAX 101--------,

Current Sense
4A+-o.

~O

Max Current
Level

_J

Power
FET

2% Duty
Cycle
VOUT

Over Current
Comparator

.....;:}-----l1 SHTDWN

---~
B3 B2 Bl BO
4 BIT DAC

GND Heatsink
GND Pins

CT

Note: Pin numbers refer to DIL-16 and SOIC-16 packages.

12/98

FAUL T

°Body Diode

UDG·94 136·3

5-37

UCC2915
UCC3915

ABSOLUTE MAXIMUM RATINGS

(continued)

VIN ...................................... +15.5 Volts
VOUT - VIN •................•...................0.3V
FAULT Sink Current. .......................... ".. 50mA
FAULT Voltage ............................. -0.3 to 8V
Output Current ........... : ........... ; .... Self Limiting
TTL InpUt Voltage ...................... ; ... -O.310VIN
StdrageTemperature ................. ; . -65°C>to +150°C
Junction Temperature., .................. -5,5°C to +150°C
Lead Temperature (Soldering, 10 sec.) ............. +300°C

DESCRIPTION (cont.)
The UCC3915 can be put into sleep'mode, drawing only
100llA of supply current. Other features include an open
drain Fault Output Indicator, Thermal Shutdown, Under7

'"

Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermallimitations and considerations of packages.
'

CONNECTION DIAGRAMS
DIL-16, SOIC-16 (Top View)
N, DP Package

PWP-24 (Top View)
TSSOP Package
r------.

o

FAULT
VOUT
VOUT
N/C

GNO"
,GNQ",
GNO"
GNO"

N/C
B3

CT

B1

BO

IMAX

'Pin 5 serves as lowest impedance to the electrical ground;
Pins 4, 12, and 13 serve as heat sink/ground. These pins
should be connected to large etch areas to help dissipate heat.
For N Package, pins 4, 12, and 13 are NIC.

'Pin 9 serves as lowest impepance to the electrical ground;
other GND pins serve as heat sink/ground. These pins should
be connected to large etch areas to help dissipate heat.

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = -40°C to +85°C for the
UCC2915 and O°C to 70°C for the UCC3915 , VIN = 12V, IMAX = 0,4V , SHTDWN = 2 4V , TA= TJ
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Supply Section
Voltage Input Range

7.0

Supply Current
Sleep Mode Current

SHTDWN = 0.2V, No load

Output Leakage

SHTDWN = 0.2V

15.0

V

1.0

2.0

mA

100

150
20

ItA
ItA

Output Section
Voltage Drop

iOUT= 1A (10V to 12V)

0.15

0.3

V

lOUT = 2A (10V to 12V)

0.3

0.6

V

lOUT = 3A (10V to 12V)

0.45

0.9

V

UCC2915
UCC3915
ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = -40°C to +85°C for the
UCC2915andO°Ct070°CfortheUCC3915 , VIN=12V , IMAX=04V, SHTDWN=24V, TA=TJ
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

lOUT = 1A, VIN = 7V and 15V

0.2

0.4

V

lOUT = 2A, VIN = 7V and 15V

0.4

0.8

V

lOUT = 3A, VIN = 7V, 12V Max.

0.6

1.2

Initial Startup Time

Note 2

100

Output Section (cont.)
Voltage Drop (cont).

V

Short Circuit Response

Note 2

100

J.ls
ns

Thermal Shutdown

Note 2

165

°C

Thermal Hysteresis

Note 2

10

°C

DACSection
Trip Current

Code = 0000-0011 (Device Off)
Code = 0100

0.07

0.25

0.45

A

Code = 0101

0.32

0.50

0.70

A

Code = 0110

0.50

0.75

0.98

A

Code = 0111

0.75

1.00

1.3

A

Code = 1000

1.0

1.25

1.6

A

Code = 1001

1.25

1.50

1.85

A

Code = 1010

1.5

1.75

2.15

A

Code = 1011

1.70

2.00

2.4

A

Code = 1100

1.90

2.25

2.7

A

Code = 1101

2.1

2.50

2.95

A

Code = 1110

2.30

2.75

3.25

A

Code = 1111

2.50

3.0

3.50

A

Max Output Current Over Trip (Current Source Mode) Code = 0100 to 1111, IMAX = OV

0.35

1.0

1.65

A

Max Output Current (Current Source Mode)

Code = 0100 to 1111, IMAX = 2.4V

3.0

4.0

5.2

A

Fault Output Section
CT Charge Current

VeT = 1.0V

-83

-62

-47

J.lA

CT Discharge Current

Vcr = 1.0V

0.8

1.2

1.8

Output Duty Cycle

Vour=OV

1.0

1.9

3.3

J.lA
%

CT Fault Threshold

1.2

1.5

1.7

V

CT Reset Threshold

0.4

0.5

0.6

V

1.5

1.9

Shutdown Section
Shutdown Threshold

1.1

Shutdown Hysteresis

150

Input Current

100

V
mV

500

nA

250

I1A

0.8

V

Open Drain Output Section
High Level Output Current

FAULT=5V

Low Level Output Voltage

IOUT=5mA

0.2

TTL Input DC Characteristics Section
TTL Input Voltage High

2.0

V

TTL Input Voltage Low
TTL Input High Current

VIH= 2.4V

TTL Input Low Current

VIL= O.4V

3

Note 1: All voltages are with respect to GND. Current is positive into and negative out of the specified terminal.
Note 2: Guaranteed by design. Not 100% tested in production.

5-39

0.8

V

10

J.lA

1

J.lA

UCC2915
UCC3915
PIN DESCRIPTIONS
SBO - B3: These pins provide digital input to the DAC,
which sets the fault current threshold. They can be'used
to provide a digital soft-start and adaptive current limiting.
'CT: A capacitor connected to ground sets the maximum

fault time. The maximum fault time must be more than
the time required to charge the external capacitance in
one cycle. The maximum fault time is defined as T FAULT
= 16.1 • 103 • CT. Once the fault time is reached the output will shutdown for a time given by TSD = 833 • 103 •
CT, this equates to a 1.9% duty cycle.
FAULT: Open drain output, which pulls low upon any
fault or interrupt condition, Fault, or Thermal Shutdown.
IMAX: When this pin is set to a,logic low, the maximum
sourcing current will always be 1A above the programmed fault level. When set to a logic high, the maximum sourcing current will be a constant 4A for
applications which require fast charging of load capacitance.

SHTDWN: When this pin is brought to a logic low; the IC
is put into a sleep mode drawing typically less than
100llA of Icc.The input threshold is hysteretic,allowing
the user to program a startup delay with an external RC
circuit.
VIN: Input voltage to the UCC3915. The recommended
voltage range is 7 to 15 volts. Both VIN pins should be
connected together and connected to power source.
VOUT: Output voltage from the UCC3915. Both V6UT
pins should be connected together and connected to the
load. When switched the output voltage will be approximately VIN - (0.150. lOUT). VOUT must not exceed VIN
by greater than 0.3V.

APPLICATIONS INFORMATION
'Heatsink
GND Pins

,~
--fVIN'

+5V

------~
~ ~

14h....,...-...--+
VIN

VOUT

3

15

LED
' L - - - - - - - i 1 6 FAULT

ri1l

CT~

VOUT'

.

2

CIN

R1

GND

UCC3915

Rso

SHTDWN~N,
CT

1

l

Cso

--f- ~-W~-qJ--GJ-~J

=

\r ~ ~ ~ -y ~ l

S1

r

82

I

83

Figure 1. Evaluation circuit

5-40

I

8.

I

85

I

~

__

VIN

~

5

=
Dip 8witch

UDG·94137·1

UCC2915
UCC3915
APPLICATION INFORMATION (cont.)
Overload

,----------.......
Output
Current

/

IMAX~ /
ITRIP

...
...

10 (nom) I----J

CT
Voltage

1.5 V ---t+---"7k:-----t-*--+--O.5V

---th~-+-~<---+---¥-~-

Vo (nom) I-----+-l
Output Rol ICL--r-~--r----t~~--~~----­
V 0 It age '--_ _----'_ _----''''"-'' fr-J'----I>oo~
11.5 TON 150TON ITON 150TON I

Estimating Maximum Load Capacitance
For hot swap applications, the rate at which the total
output capacitance can be charged depends on the
maximum output current available and the nature of the
load. For a constant-current, current-limited application,
the output will come up if the load asks for less than the
maximum available short-circuit current.
To guarantee recovery of a duty-cycle from a shortcircuited load condition, there is a maximum total output
capacitance which can be charged for a given unit ON
time (Fault time). The design value of ON or Fault time
can be adjusted by changing the timing capacitor CT.

COUT(max)

IMAX -I LOAD

UDG·94138

e

16.1e10 3 eCT

VOUT

Where VOUT is the output voltage.
For a resistive load of value R" the value of COUT(max)
can be estimated from:

C

OUT(max)

For worst-case constant-current load of value just less
than the trip limit; COUT(max) can be estimated from:

Figure 2. Load current, timing capacitor voltage, and output voltage of the UCC3915 under fault conditions.

SAFETY RECOMMENDATIONS
Although the UCC3915 is designed to provide system
protection for all fault conditions, all integrated circuits
can ultimately fail short. For this reason, if the UCC3915
is intended for use in safety critical applications where
UL or some other safety rating is required, a redundant
UNITRODE CORPORATION
7 CONTINENTAL BLVD ( MERRIMACK. NH 03054
TEL (603) 424·2410 ( FAX (603) 424-3460

5-41

safety device such as a fuse should be placed in series
with the device. The UCC3915 will prevent the fuse from
blowing for virtually all fault conditions, increasing system reliability and reducing maintenance cost, in addition
to providing the hot swap benefits of the device.

UCC39151

[ldJ UNITRDDE
15V Programmable Hot Swap Power,Manager
FEATURES

DESCRIPTION

• Integrated 0.15n Power MOSFET

The UCC39151 Programmable Hot Swap Power Manager provides com~
plete power managemf)nt, hot swap capability, and circuit breaker func~
tions. The only external component required to operate the device, other
than power supply bypassing, is the fault timing capacitor, CT. All control
and housekeeping functions are integrated, and externally programmable.
These include the fault· current level, maximum output sourcing current,
maximum fault time, and startup delay. In the event of a constant fault, the
Internal fixed 2% duty cycle ratio limits average output power.

• 7V to 15V Operation
• Digital Programmable Current Limit
from OA to 3A
• Programmable ON Time
• Programmable Start Delay

The internal 4 bit DAC allows programming of the fault level current from
OAto 3A with 0.25A resolution. The IMAX control pin sets the maximum
sourcing current to 1A above the trip level or to a full 4A of output current
for fast output capacitor charging.

• Fixed 2% Duty Cycle
• Thermal Shutdown
• Fault Output Indicator

When the output current is below the fault level, the output MOSFET is
switched ON with a nominal ON resistance of 0.15n. When the output current exceeds the fault level, but is less than the maximum sourcing level,
the output remains switched ON, but the fault timer starts, charging CT.
Once CT charges to a preset threshold, the switch is turned OFF, and remains OFF for 50 times the programmed fault time. When the output current reaches the maximum sourcing level, the MOSFET transitions from a
switch to a constant current source.

• Maximum Output Current can be set
to 1A above the Programmed Fault
Level or to a full 4A
• Power SOIC and TSSOP, Low
Thermal Resistance Packaging

(continued)

BLOCK DIAGRAM

,---------------------------------------------,
I
I
I
H=4A
IMAX 1 0 1 - - - - - - - ,

VIN'

I
I

I
I

Current Sense

I
I

4A--.o.

-,

I

~"Power :I

Max Current
Level

_J

FET

I

I
I
I
I
VOUT

Over Current
Comparator

-.--~11
B3 B2 Bl

BO

4 BIT DAC

GND Heatsink
GND Pins

CT

Note: Pin numbers refer to DIL-16 and SOIC-16 packages.

02/99

I - - - - - - - l l SHTDWN

"Body Diode

UDG'94136-3

5-42

UCC39151

ABSOLUTE MAXIMUM RATINGS

DESCRIPTION (cont.)

VIN ...................................... +15.5 Volts
VOUT - VIN .....................................0.3V
FAULT Sink Current ............................. 50mA
FAULT Voltage ............................. -0.3 to SV
Output Current ............................ Self Limiting
TTL Input Voltage .......................... -0.3 to VIN
Storage Temperature ................... -65 DC to +150DC
Junction Temperature ................... -55 DC to +150DC
Lead Temperature (Soldering, 10 sec.) ............. +300DC

The UCC39151 can be put into sleep mode, drawing
only 20mA of supply current. Other features include an
open drain Fault Output Indicator, Thermal Shutdown,
Undervoltage Lockout, 7V to 15V operation, and low
thermal resistance SOIC and TSSOP Power Packages.

Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermallimitations and considerations of packages.

CONNECTION DIAGRAMS
DIL-16, SOIC-16 (Top View)
N, DP Package

PWP-24 (Top View)
TSSOP Package

o

FAULT
VOUT
VOUT

N/C
GNO"
GNO"
GNO"
GNO"

N/C

CT
IMAX

BO

'Pin 5 serves as lowest impedance to the electrical ground;
Pins 4, 12, and 13 serve as heat sink/ground. These pins
should be connected to large etch areas to help dissipate heat.
For N Package, pins 4, 12, and 13 are N/e.

'Pin 9 serves as lowest impedance to the electrical ground;
other GND pins serve as heat sink/ground. These pins should
be connected to large etch areas to help dissipate heat.

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = ODC to 70DC for the
UCC39151 , VIN=12V , IMAX=04V , SHTDWN=24V , TA=TJ
PARAMETER

TEST CONDITIONS

MIN

TVP

MAX

UNITS

Supply Section
Voltage Input Range

7.0

Supply Current
Sleep Mode Current

SHTDWN = 0.2V, No load

Output Leakage

SHTDWN = 0.2V

15.0

V

1.0

2.0

rnA

100

150

!IA

20

rnA

Output Section
Voltage Drop

lOUT = 1A (10Vto 12V)

0.15

0.3

V

lOUT = 2A (10V to 12V)

0.3

0.6

V

lOUT = 3A (10V to 12V)

0.45

0.9

V

lOUT = 1A, VIN = 7V and 15V

0.2

0.4

V

lOUT = 2A, VIN = 7V and 15V

0.4

O.S

V

lOUT = 3A, VIN = 7V, 12V Max.

0.6

1.2

V

5-43

UCC39151

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = O°C to 10°C for the
UCC39151 , VIN-12V
SHTDWN-24V
- , IMAX-04V
- , TA-TJ
"

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Output Section (continued)
Initial Startup Time

(Note 2)

100

Short Circuit Response

(Note 2)

100

I

!Ls
ns

DACSection
Trip Current

Code = 0000-0011 (Device Off)
Code = 0100

0.07

0.25

0.45

A

Code = 0101

0.32

0.50

0.7

A

Code = 0110

0.50

0.75

0.98

A

Code = 0111

0.75

1.00

1.3

A

Code = 1000

1.0

1.25

1.6

A

Code = 1001

1.25

1.50

1.85

A

Code = 1010

1.5

1.75

2.15

A

Code = 1011

1.70

2.00

2.4

A

Code = 1100

1.90

2.25

2.7

A

Code = 1101

2.1

2.50

2.95

A

Code = 1110

2.30

2.75

3.25

A

Code=1111

2.50

3.0

3.5

A

Max Output Current Over Trip (Current Source
Mode)

Code = 0100 to 1111, IMAX = OV

0.35

1.0

1.65

A

Max Output Current (Current Source Mode)

Code = 0100 to 1111, IMAX= 2.4V

3.0

4.0

5.2

A

CT Charge Current

Vcr= 1.0V

-83

-62

-47

CT Discharge Current

VeT = 1.0V

0.8

1.2

1.8

!LA
!LA

Output Duty Cycle

VOUT=OV

Fault Output Section

1.0

1.9

3.3

CT Fault Threshold

1.2

1.5

1.7

%
V

CT Reset Threshold

0.4

0.5

0.6

V

1.5

1.9

Shutdown Section
1.1

Shutdown Threshold
Shutdown Hysteresis

150

Input Current

100

V
mV

500

nA

250

!LA

0.8

V

Open Drain Output Section
High Level Output Current

FAULT=5V

Low Level Output Voltage

IOUT=5mA

0.2

TTL Input DC Characteristics Section
TTL Input Voltage High

V

2.0

TTL Input Voltage Low
TTL Input High Current

VIH=2.4V

TTL Input Low Current

VIL= O.4V

3

Note 1: All voltages are with respect to Ground. Current is positive into and negative out of the specified terminal.
Note 2: Guaranteed by design. Not 100% tested in production.

5-44

0.8

V

10

!LA

1

!LA

UCC39151

PIN DESCRIPTIONS
80, 81, 82, 83: These pins provide digital input to the
DAC, which sets the fault current threshold. They can be
used to provide a digital soft-start and adaptive current
limiting.
CT: A capacitor connected to ground sets the maximum
fault time. The maximum fault time must be more than
the time required to charge the external capacitance in
one cycle. The maximum fault time is defined as:
TFAULT =16.1_10 3 -CT·
Once the fault time is reached the output will shutdown
for a time given by:
TSD

=833_10 3 -CT ,

this equates to a 1.9% duty cycle.
FAULT: Open drain output, which pulls low upon any
fault or interrupt condition, Fault, or Thermal Shutdown.

IMAX: When this pin is set to a logic low, the maximum
sourcing current will always be 1A above the programmed fault level. When set to a logic high, the maximum sourcing current will be a constant 4A for
applications which require fast charging of load capacitance.
SHTDWN: When this pin is brought to a logic low, the IC
is put into a sleep mode drawing typically less than
10011A of Icc (with VOUT unloaded). The input threshold
is hysteretic, allowing the user to program a startup delay
with an external RC circuit.
VIN: Input voltage to the UCC39151. The recommended
voltage range is 7V to 15V. Both VIN pins should be connected together and connected to power source.
VOUT: Output voltage from the UCC39151. Both VOUT
pins should be connected together and connected to the
load. When switched:

VOUT ",V'N -(0.15n-'OUT)
VOUT must not exceed VIN by more than 0.3V.

APPLICATIONS INFORMATION
HEATSINK GROUND PINS

,----clJ----aJ---J}---ct}-------1 1

V
ImN
+5V

r

eiN

R1

-

2

VIN

3

VIN

GND

GND

GND

:
I

VOUT

:

14 h~.......-

....

I

I
I
I

UCC39151

I

LED

GND

I
I

'-------116

FAULT

UDG·98176

Figure 1. Evaluation circuit.

5-45

UCC39151

APPLICATION INFORMATION (cont.)
Overload
~----------".:

Output
Current

.,

I

IMAX----;.,

,.

I

,

ITRIP

10 (nom) I - - - - J

CT
Voltage

1.5V"""""'--I+---7Io;:---1I--*--+---

0.5 V --I+-:.r.--+----"If---+----"I"-....,.".-

Vo (noin) t-----H..
Output Rol I CL.......jI-~-II___-_!?-j_-_hf_--­
VO Itag e L -_ _......J._ _-..D~ r-'---.D.ooA}
UDG·94138

11.5 TON 150TON ITON 150TON 1

Estimating Maximum Load Capacitance
For hot swap applications, the rate at which the total
output capacitance can be charged depends on the
maximum output current available and the nature of the
load. For a constant-current, current-limited application,
the output will come up if the load asks for less than the
maximum available short-circuit current.
To guarantee recovery of a duty-cycle from a shortcircuited load condition, there is a maximum total output
capacitance which can be charged for a given unit ON
time (Fault time). The design value of ON or Fault time
can be adjusted by changing the timing capacitor CT.

Where VOUT is the output voltage,
For a resistive load of value RI, the value of COUT(max)
can be estimated from:

COUT(max) '"

RL

For worst-case constant-current load of value just less
than the trip limit; COUT(max) can be estimated from:
COUT(max) '"

(I MAX

-

I LOAD) • (

16.1.10 3 .CT
VOUT

.,en[1

~ 1
OUT

IMAX

.RL

Long CT times must consider the maximum temperature. Thermal shutdown protection may be the limiting
Fault time.

)

Figure 2. Load current, timing capacitor voltage, and output voltage of the UCC39151 under fault conditions.

SAFETY RECOMMENDATIONS
Although the UCC39151 is designed to provide system
protection for all fault conditions, all integrated circuits
can ultimately fail short. For this reason, if the
UCC39151 is intended for use in safety critical applications where UL or some other safety rating is required, a
redundant safety device such as a fuse should be placed
UNITROOE CORPORATION
7 CONTINENTAL BLVD ( MERRIMACK, NH 03054
TEL (803) 424-2410 ( FAX (603) 424-3460

5-46

in series with the device. The UCC39151 will prevent the
fuse from blowing for virtually all fault conditions, increasing system reliability and reducing maintenance
cost, in addition to providing the hot swap benefits of the
device.

~UNITRDDE

UCC3916

SCSI Termpower Manager
FEATURES

DESCRIPTION

• Integrated Circuit Breaker Function

The UCC3916 SCSI term power manager provides complete power management, hot swap capability, and circuit breaker functions with mihimal external components. For most applications, the only external component
required to operate the. device, other than supply bypassing, is a timing capacitor which sets the fault time.

• Integrated 0.20 Power FET
• SCSI, SCSI-2, SCSI-3 Compliant
• 11JA ICC When Disabled
• Programmable On Time
• Accurate 1.65A Trip Current!
2.1A Max Current
• Fixed 3% Duty Cycle
• Un i-Directional Switch
• Thermal Shutdown

The current trip level is internally set at 1.65A, and the maximum current
level is also internally programmed for 2A. While the output current is below
the trip level of 1.65A, the internal power MOSFET is switched on at a nominal 220mO. When the output current exceeds the trip level but remains
less than the maximum current level, the MOSFET remains switched on,
but the fault timer starts charging CT. Once the fault time is reached, the
circuit will shut off for a time which equates to a 3% duty cycle. Finally,
when the output current reaches the maximum current level, the MOSFET
transitions from a switch to a constant current source.
The UCC3916 is designed for un i-directional current flow, emulating a diode in series with the power MOSFET.
The UCC3916 can be put in a sleep mode, drawing only 11JA of supply current.
Other features include thermal shutdown and low thermal resistance Small
Outline Power package.

BLOCK DIAGRAM
r-~-~----------------------------------

VIN
4V to 6V .
Reverse Voltage
Comparator

Current Sense
Max Current
Level
Power
FET

2 Amps

Current Trip
Level

1.65 Amps
Over Current L-----._---'
Comparator

I

L ______

..L~
=
-= 2 3 6 7

I
I
I
I
I
I
I

4

_---1

GND
CT
4 Heatsink Pins

07199

SHTDWN

5-47

UDG-96011-1

UCC3916

ABSOLUTE MAXIMUM RATINGS

CONNECTION DIAGRAM

VIN ........................................... +6V
Output Current
DC ......... ; ......................... -Self Limiting,
Pulse (Less than 1OOns) ......................... 20A
Storage Temperature ................... -65°C to +150°C
Junction Temperature ................... -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ............. .f.300°C

,SOIC.8 (Top View)
DP Package
","

.

Currents are positive into, negative out of the specified termina/. Consult Packaging Section of DatabOOk fortherma/limitations and considerations of packages.

ELECTRICAL CHARACTERISTICS: Unless otherwise stated; these parameters apply for TJ = O°C to +70°C; VIN = 5V,
SHTDWN = 2 4V TA = TJ

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Supply Current Section
ICC
ICC - Sleep Mode

1.00

2.00

rnA

SHTDWN = 0.2V

0.50

5

~

lOUT = 1A

0.22

0.33

V

lOUT = 1.5A

0.33

0.50

V

lOUT = 1.8A

0.40

0.60

V
A

Output Section
Voltage Drop

Trip Current

-1.8

-1.65

-1.5

Max Current

-2.4

-2

-1.8

A

6

20

~

0.50

9

~

Reverse Leakage

VIN = 4.5V, VOUT = 5V
VIN = OV, VOUT = 5V

Soft Start Time

Initial Startup

Short Circuit Response

50

j.lS

100

ns

Fault Section
CT Charge Current

VeT = 1.0V

-45

-36.0

-27

IlA

CT Discharge Current

VCT= 1.0V

0.90

1.0

1.50

~

Output Duty Cycle

VOUT=OV

2.00

3.00

6.00

%

CT Charge Threshold

0.4

0.5

0.6

V

CT Discharge Threshold

1.2

1.4

1.8

V

Thermal Shutdown

170

°C

Thermal Hysteresis

10

°C

Shutdown Section
Shutdown Threshold

1.5

3.0

V

Shutdown Hysteresis

150

300

mV

100

500

nA

Shutdown Bias Current

SHTDWN = 1.0V

Note 1: All voltages are with respect to ground.

5-48

UCC3916

PIN DESCRIPTIONS
CT: A capacitor is applied between this pin and ground
to set the maximum fault time. The maximum fault time
must be more than the time to charge external capacitance. The maximum fault time is defined as:
TFAUlT= 28 • 103 • CT.
Once the fault time is reached the output will shutdown
for a time given by:

SHTDWN: The IC enters a low-power sleep mode when
this pin is low and exits the sleep mode when this pin is
high.
VIN: Input voltage to the circuit breaker, ranging from 4V
t06V.
VOUT: Output voltage of the circuit breaker. When
switched, the output voltage is approximately:

TSD = 1 .106 • CT

VOUT = VIN - (220mfl) • lOUT.

this results in a 3% duty cycle. 0.1!J,F is recommended
for SCSI applications to achieve the normal maximum
capacitance on the Termpwr line.

m

TYPICAL APPLICATION

1- - - - - - - - - - - - - - - - - - -I
I
I

V
IN

I

VIN

I

CIN

TERMPOWER
BUS O

I

5

SHTDWN

I

GND

I

I

r!;-,
OUTPUT ~

UCC3916

~--

~

GND

2 -- 3 -

CT 4
GND
I

GND
6

-

7

--~

r-

rClOAD

~

UDG-99135

SAFETY RECOMMENDATIONS
Although the UCC3916 is designed to provide system
protection for all fault conditions, all integrated circuits
can ultimately fail short. For this reason, if the UCC3916
is intended for use in safety critical applications where
UL or some other safety rating is required, a redundant

safety device such as a fuse should be placed in series
with the device. The UCC3916 will prevent the fuse from
blowing virtually all fault conditions, increasing system
reliability and reducing maintainence cost, in addition to
providing the hot swap benefits of the device.

UNITRODE CORPORATION
7 CONTINENTAL BLVD .• MERRIMACK. NH 03054
TEL. (603) '424-2410 FAX (603) 424-3460

5-49

[1JJ

UCC39161

_UNITROCE

ADVANCE INFORMATION

Low Current Hot Swap Power Manager
.J"

.'

FEATURES..

DESCRlPTION

• Integrated Circuit Breaker Function

The UCC39161 low current hot swap power manager provides complete
power management, hot swap capability, and circuit breaker functions with
minimal external components. For most applications, the only external
component required to operate the device, other then supply bypa~ing, is
a timing capacitor which sets the fault time.

• Integrated 0.20 Power FET
• 11JA ICC When Disabled
• Programmable On Time
• Accurate 0.8A Mal< Current
• Fixed 3% Duty Cycle
• Uni-Directional Switch
• Thermal Shutdown

The 'maximum current level is internally programmed for 0.8A. While the
output current is below 0.8A, the internal power MOSTFET is switched on
at a nominal 220mO. When the output current exceeds 0.8A, the MOSFET
transitions from a switch to a constant current sourpe and the fault timer
starts charging CT. Once the fault time is reached, the curre!'lt will shut off
for a time, which equates to a 3% duty cycle.
The UCC39161 also provides unidirectional current flow, emulating a diode in series with the power MOSFET.
The UCC39161 can be put into sleep mode by grounding theSHTDWN
pin. In sleep mode, the UCC39161 draws under 51JA of supply current.
Other features include thermal shutdown and a low thermal resistance
Small Outline Power package.

BLOCK DIAGRAM AND TYPICAL APPLICATION

REVERSE VOLTAGE
COMPARATOR

CURRENT SENSE

MAXIMUM
CURRENT
LEVEL
O.BA ~~f--t

oH=OPEN

-

>---------<:>--;- 0

POWER

~ I~ FEr.•

1
~

r

[!J.O.

~

~OAD

I~

4 HEATSINK PINS
GND GND GND GND

SHTDWN

UOG·99069

07199

5-50

UCC39161

ABSOLUTE MAXIMUM RATINGS

CONNECTION DIAGRAM

VIN ........................................... +6V
Output Current
DC ................................... Self Limiting
Pulse (Less than 100ns) ......................... 20A
Storage Temperature ................... -6SoC to +1S0°C
Junction Temperature ................... -5SoC to +1S0°C
Lead Temperature (Soldering, 10 sec.) ............. +300°C

SOIC-B (Top View)
DP Package

Currents are positive into, negative out of the specified terminat. Consu" Packaging Section of Databook for thermal/imitations and considerations of packages.

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these parameters apply for TJ = O°C to +70°C; VIN = SV,
SHTDWN =24V, TA=TJ
TEST CONDITIONS

PARAMETER

MIN

TYP

MAX

UNITS

1.00

2.00

mA

O.SO

S

!1A

Supply Current Section
ICC
ICC - Sleep Mode

SHTDWN = 0.2V

Output Section
Voltage Drop

lOUT = O.SA
-1.0

Max Current
Reverse Leakage

VIN = 4.SV, VOUT= SV
VIN = OV, VOUT= SV

Soft Start Time

Initial

Start~

0.10

0.16

V

-0.8

-0.6

A

6

20

0.50

9

l1A
l1A

SO

Short Circuit Response

l1S
ns

100

Fault Section
CT Charge Current

VCT= 1.0V

-4S

-36.0

-27

CT Discharge Current

VCP 1.0V

0.90

1.0

1.S0

Output Duty Cycle

VoupOV

2.00

3.00

6.00

CT Charge Threshold

0.4

O.S

0.6

CT Discharge Threshold

1.2

1.4

1.8

l1A
l1A
%
V
V

Thermal Shutdown

170

°C

Thermal Hysteresis

10

°C

Shutdown Section
Shutdown Threshold

1.S

3.0

V

Shutdown Hysteresis

1S0

300

mV

100

SOO

nA

Shutdown Bias Current

Note

1:

SHTDWN = 1.0V

All voltages are with respect to ground.

S-51

UCC39161

PIN DESCRIPTIONS
CT: A capacitor is applied between this pin· and ground
to set the maximum fault time. The maximum fault time
must be more than the time to charge extemal capacitance. The maximum fault time is defined as:
TFAULT =28_10 3 -CT.

Once the fault time is reached the output will shutdown
for a time given by:

SHTDWN: The IC enters a low-power sleep mode whEln
this pin is low and exits the sleep mode when this pin is
high.
VIN: Input voltage to the circuit breaker, ranging from 4V
t06V.
VOUT: Output voltage of the circuit, breaker. When
switched, the output voltage is approximately:
VOUT = VIN - 220mD. -lOUT'

TSD =1_10 6 -CT

this results in a 3% duty cycle.

VIN

1-- - - - - - - - - - - - - - - - - - I
I
I

TERMPOWER

UCC3916

BUS

>-W?
1 Lc!J
C

IN

~

OUTPUT 9r------I----- 20kn (Current limit out of VREF)

Where IpL is defined as:

I PL =- (VIN - VOUT
RpL

-

Lastly, the external capacitors used for the charge pump
are required and need to equal O.1J..lF, I.e. CIN CH
C1 = C2 =O.1J..lF.

=

Vpd

(S)

LEVEL Shift Circuitry (Optional)

The average IpL current for the interval (0, T START) from
Fig. 4 is defined as:

IpL(AVG)"" (VIN-Vpd 2
2 eRpL eVIN

(6)

Equation 4 can now be simplified to:

. )_ICH+lpdAVG) T
CT( min
=
e START
dVCT

(7)

Please note that the actual on-time in hiccup mode when
operating into a short is defined by:

T(on)= CTedVCT seconds
ICH +Ipdpk)

=

(8)

S-S9

The level shift circuitry shown in Fig. Sand Fig.6 represents a way of interfacing to LATCH, SHTDWN, and
FLTOUT. These pins provide functionality that is not
necessary for normal operation of the IC but may prove
useful to the application. The resistor, R, shown in both
figures is used for the current limiting and follows RMAX
=VsoIISD' The capacitor, C, shown in both figures is operational to the level shift circuitry and keeps spurious
signals from occurring during transients. It's recommended value is CMIN = 0.1 nF. It should be noted that
the use of the capacitor, C, will cause delays into and
out of these pins.

UCC1917
UCC2917
UCC3917
APPLICATION INFORMATION (cont.)

~
3

TO UCC3917

R

LOCAL

SHUTDOWNI~
Jb
'I'
OR
LATCH

~

Voo

=-Lt
:"" . 1

l -

VOUT

r- 1.~ f~
FAULT

R2

UDG-96267-1

Figure 6. Potential level shift circuitry to interface
to FL TOUT on the UCC3917.

Figure 5. Potential level shift circuitry to interface to
LA TCH and SHTDWN on the UCC3917.

SAFETY RECOMMENDATIONS
Although the UCC3917 is designed to provide system
protection for all fault conditions, all integrated circuits can
ultimately fail short. For this reason, if the UCC3917 is intended for use in safety critical applications where UL or
some other safety rating is required, a redundant safety

device such as a fuse should be placed in series with
the power device. The UCC3917 will prevent the fuse
from blowing for virtually all fault conditions, increasing
system reliability and reducing maintenance cost, in addition to providing the hot swap benefits of the device.'
V,N
D1

R3

1---------:

Veo

I

I
I
I
I

SHTDWN 12r-~-+----_r------~--~

10VSHUNT
REGULATOR

C2P~ -~~---+-------1

~' -~

SENSE

5VSHUNT

~.,.......R_EG-IU~LA_T_O-,R_____________-+-+__--:---+-,
~--------~

I
I
I
I

R2

OUTPUT
UDG-99056

Figure 7. Positive floating hot swap power manager UCC1917, UCC2917 and UCC3917.
UNITRODE CORPORATION
7 CONTINENTAL BLVD.• MERRIMACK, NH 03054
TEL (603) 424·2410 FAX (603) 424-3460

5-60

~UNITRODE

UCC2918
UCC3918

Low On Resistance Hot Swap Power Manager
FEATURES

DESCRIPTION

• Integrated 0.06n Power
MOSFET

The UCC3918 Low on Resistance Hot Swap Power Manager provides complete
power management, hot swap capability, and circuit breaker functions. The only
components needed to operate the device, other than supply bypassing, are a timing capacitor, and 2 programming resistors. All control and housekeeping functions
are integrated, and externally programmable. These include the fault current level,
maximum output sourcing current, maximum fault time, and startup delay. In the
event of a constant fault, the internal fixed 3% duty cycle ratio limits the average
output power. The IFAULT pin allows linear programming of the fault level current
from OA to 4A.

• 3V to 6V Operation
• External Analog control of
Fault Current from OA to 4A
• Independent Analog Control
of Current Limit up to 5A
• Fast Overload Protection
• Minimal Extemal Components
• 111A Icc when Disabled
• Programmable On Time

Fast overload protection is accomplished by an additional overload comparator. Its
threshold is internally set above the maximum sourcing current limit setting. In the
event of a short circuit or extreme current condition, this comparator is tripped,
shutting down the output. This function is needed since the maximum sourcing current limit loop has a finite bandwidth.
When the output current is below the fault level, the output MOSFET is switched on
with a nominal resistance of 0.06n. When the output current exceeds the fault level
or the maximum sourcing level, the output remains on, but the fault timer starts
charging CT. Once CT charges to a preset threshold, the switch is turned off, and
remains off for 30 times the programmed fault time. When the output current
reaches the maximum sourcing level, the MOSFET transitions form a switch to a
constant current source.

• Programmable Start Delay
• Fixed 3% Duty Cycle

(continued)

BLOCK DIAGRAM

r---------------------------------------------,

I
I
I

20mV

OVERLOAD
COMPARATOR '--"""'T--'

CURRENT SENSE

MAXIMUM
CURRENT
LEVEL

CURRENT FAULT LEVEL

IFAULT

I
I
I
I
I

.L~
= 5 4 13 12 - -

- Q - - - - - - i 7 SHTDWN

I
L _________

GND HEATSINK
GND PINS

CT

FAUL T
UOG-97069-2

6198
5-61

UCC2918
,.uCC3918
CONNE(:TION DIAGRAM

DESCRIPTION (continued)
The UCC39i8 is designed for unidirectional current flow,
emulating an ideal diode in series with the power switch.
This feature is particularly attractive in applications where
many devices are powering, a common bus, such as with
SCSI Termpwr. The UCC39i8 can also be put into the
sleep mode, drawing only 1j.tA of supply current.

Oll-i6, SOIC-16(TQP View)
N Package,OPPackage
Qil Packages

Other features include an open drain fault output indica·
tor, thermal shutdown, undervoltage lockout, 3Vto 6V '
operation, and a low thermal resistance small outline
power package.

ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (VIN) .......................... BV
SOIC Power Dissipation .......................... 2;5W
Fault Output Sink Current ................ '......... 50mA
Fault Output Voltage .............................. VIN
Output Current (DC) .................... Internally Limited
TTL Input Voltage ...................... ;' .. --O.3V to VIN
Storage Temperature ................... -65°(; to +150°C '
Junction Temperature ............ ; .'..... -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) .. , ......... : +300°C
Unless otherwise inpicated, voltages are reference to ground
and currents are positive into, negative out of the specified
terminal. Pulsed is defined as a less than 10% duty cycle with a
maximum duration of 50DllS. Consult Packaging Section of
Databook for thermal limitations and considerations of package.

VIN

VOUT

VIN

YOUr

\lIN

VOUT

GND*

GNO*

GNO*

GNO* ,

FAULT

N/C

SHTDWN

CT','

IFAUL T

IMAX

• Pin 5 serves as the lowest impedance to the electrical
ground. Pins 4, 12, and 13 serve as heat sink/ground.
These pins shoiJld be connected to large etch PCB areas
to help diSSipate heat. For N Package, pins 4, 12, and 13
areNIC.

"

TSSOP-24 (Top View)
PWP Package
VIN

vour

VIN

VOUT

VIN

vour

VIN

vour

GNO·

GNO·

GNO·

GNO·

GNO·

GNO·

GNO·

GNO·

GNO·

GNO·

FAULT
,\

"

NlC

.

SHTi5WN
IFAULT

CT
IMAX

• Pin ,9 servesss the lowest impedance to the electrical
ground. Pins 5, 6,7, 8, 16, 17, 18, 19 and 20 serve as heat
sink/ground.

5-62

UCC2918
UCC3918
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = O·C to 70·C for the UCC3918, -40·C to 85· for the
, SHTDWN=24
.. TA-TJ
UCC2918 , VIN-5V
RIFAULT-523k
- RIMAX-422k
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

3

5

6

V

1

2

mA

0.5

5

!IA

n
n
n
n

UNITS

Supply Section
Voltage Input Range, VIN
Voo Supply Current

No Load

Sleep Mode Current

SHTDWN = 0.2V

Output Section
lOUT = 1Ato4A, VIN =5V, TA=25·C

0.075

0.095

lOUT = 1A to 4A, VIN = 3V, TA = 25·C

0.09

0.116

lOUT = 1A to 4A, VIN = 5V

0.75

0.125

lOUT = 1A to 4A, VIN = 3V

0.09

0.154

Initial Startup Time

(Note 1)

100

Thermal Shutdown

(Note 1)

170

Thermal Hysteresis

(Note 1)

10

Output Leakage

SHTDWN = 0.2V

Trip Current

RIFAULT= 105k

ROSON

itS
DEG

Output Section (cont)

Maximum Output Current

DEG
20

0.75

1

1.25

itA
A

RIFAULT = 52.3k

1.7

2

2.3

A

RIFAULT= 34.8k

2.5

3

3.5

A
A

RIFAULT = 25.5k

3.3

4

4.7

RIMAX= 118k

0.3

1

1.7

A

RIMAX = 60.4k

1

2

3

A
A

RIMAX = 42.2k

2

3

4

RIMAX = 33.2k

2.5

3.8

5.1

A

RIMAX = 27.4k

3.0

4.6

6.2

A

CT Charge Current

Vrrr= 1V

-50

-36

-22

itA

CT Dischal"Re Current

VeT = 1V

0.5

1.2

2.0

itA

%
V
V

Fault Section

Fault Section (cont.)
Output Duty Cycle

1.5

3

6

CT Fault Threshold

0.8

1.3

1.8

CT Reset Threshold

0.25

0.5

0.75

1.5

2.0

VOUT=OV

Shutdown Section
Shutdown Threshold

1.1

Shutdown Hysteresis

100

Input Low Current

SHTDWN=OV

-500

Input High Current

SHTDWN=2V

-2

V
mV

0
-1

500

nA

-0.5

itA

1
0.4

0.9

itA
V

Open Drain Fault Output
High Level Output Current
Low Level Output Voltage

lOUT = 1mA

Note 1: Guaranteed by design. Not 100% tested in production.

5-63

UCC2918
UCC3918
PIN DESCRIPTIONS.
CT: A capacitor connected to this pin sets the maximum
fault time. The maximum must be more than the time tCt
charge external load capacitance. The maximum fault
time is defined as
TFAULT

=27.8e10 3 eCT

105k

RFAULT = - [TRIP

IMAX: A resistor connected from this pin to ground sets
the maximum sourcing current. The resistorvs'the output
sourcing current is set by the formula,

Once the fault time is reached the output will shutdown
for a time given by
TSD

R

=
FAULT

126k
MaximumSourcing Current

= 0.833 e10 6 e CT ,

this equates to a 3% duty cycle.
FAULT: Open drain output, which pulls low upon any
condition which causes the output to open; Fault, Thermal Shutdown, Shutdown, and maximum sourcing current greater than the fault time.
GND: This is the most negative voltage in the circuit. All
4 ground pins should be used, and properly heat sunk on
the PCB.
IFAULT: A resistor connected from this pin to ground
sets the fault threshold. The resistor vs fault current is
set by the formula

SHTDWN: When this pin is brought low, the IC is put into
sleep mode. The input threshold is hysteretic, allowing
the user to program a startup delay with an external RC
circuit.
VIN: This is the input voltage to the UCC3918. The recommended operating voltage range is 3V to 6V. AIIVIN
pins should be connected together and to the power
source.
VOUT: Output voltage for the circuit breaker. When
switched the output voltage will be approximately VIN 0.060 • lOUT. All VOUT pins should be connected together and to the load.

APPLICATION INFORMATION
HEAT SINK
GND PINS GND

~l

r------~r~

I
I

VIN
VIN

>--.._--.._--......-1

VIN

R1

VOUT

1--1.-.----<.__--. V OUT

VIN
FAULT

Rso
.

Y :b;"'n~·.

ISHTDWN
CT
I .I.cso
I
IFAUL T
IMAX I

r-l$
CT.I.

~VIN

..l:.
-=-

~ L----!":A~'~-t·~,
UDG·97070·1

Figure 1. Evaluation Circuit

5-64

UCC2918
UCC3918
than the maximum available short-circuit current.

APPLICATION INFORMATION (cont.)

To guarantee recovery of a duty-cycle of the currentlimited circuit breaker from a short-circuited load condition,
there is a maximum total output capacitance which can be
charged for a given unit ON time (Fault time). The design
value of ON or Fault time can be adjusted by changing the
timing capacitor CT.

Overload
Output
Current

/

r--------~

,

I MAX-.;. /

,

ITRIP""'-

10 (nom)

CT

Voltage

1.5V -f+--*--+--,k--+---0.5 V

-ft-7<--+--+-+---"'i''---""",,-

For worst-case constant-current load of value just less
than the trip limit; COUT(max) can be estimated from:
COUT(max)", (IMAX - IWAD ) (

28 e 10 3 eCTJ
VOUT

Where VOUT is the output voltage and IMAX is the maximum, sourcing current.

VO (nom)

For a resistive load of value RI, the value of COUT(max) can
be estimated from:

Output Rol ICL
Voltage
11.5 TON 130TON ITON 130TON I

UDG·97071

Figure 2. Load Current, Timing Capacitor Voltage
and Output Voltage of the UCC3918 Under Fault

COUT(max)",

Estimating Maximum Load Capacitance
For circuit breaker applications, the rate at which the total output capacitance can be charged depends on the
maximum output current available and the nature of the
load. For a constant-current current-limited circuit
breaker, the output will come up if the load asks for less
Tek liliiii 50.0MS/s

2 Acqs

f+T . . --·............·. -

....._}-........- . ._ ......._ . .!

VIN

I:'"
.................................... 4A

FAULT OUT

2

.+

3A

+-i-I-np

.................... 'Ht..

. . . .f .

. ..... 2A

. . :. ·. . :. . . . :· . . 1.

···1A
IVIN:

4

OA

t

100 (vO~ SHORTED~

.7 V
.•

Ch4 IO.OmV
COUT

RL

2211F

50

C!N

511F

RIFAULT

R!MAX

VOUT

RL

52.3k

42.0k

OV

SHORT

2A

CIN

511F

RIFAULT

RIMAX

52.3k

42.2k

Input driven with a pulse generator, shows GOUT discharging through RL and conducting through UGG3918 FET in
the reverse direction.

Figure 3.

Figure 4. UCC3918 in Shorted Condition

5-65

UCC2918
UCC3918
APPLICATION INFORMATION

.

:Or

..

,','

:i,

··1

..

2

.,

.

: FAULTOUT.

....

3

:t
..J...

p.;.~..-w-..~:...
IO"'U!....(.,.RLNj
..=,.;.",50;-.;.l",.~;;;.:..;." .................... ..

t

t
.....l···:····:····:····:····: ----i

1

I - - - + - - - - - - - - - - - - - +.....--:H-----'
+

I

IBIAS

cb--rJ
,:
,
,

UVBIAS

i F~:
PL

CT

1.5v

Jcrd

t

1X

t

t

3611A

1X

SET
DOMINANT

S

g:::vJ9

Q

~I--------'-

,
,
,
,

GNDh

,

=
LR

UDG·98123

Note: Pins shown for 14- in

11/98

5-68

UCC1919
UCC2919
UCC3919
CONNECTION DIAGRAMS
ABSOLUTE MAXIMUM RATINGS

DIL-14, (Top View)
N, J Packages

VDD .................................... -Q.3V to 10V
Pin Voltage
(All pins except CAP and GATE) ...... -Q.3V to VDD + 0.3V
Pin Voltage
(CAP and GATE) ........................ -Q.3V to 15V
PL Current ............................ 0.5mA to -10mA
IBIAS Current. ............................ OmA to 3mA
Storage Temperature ................... -65°C to +150°C
Junction Temperature ................... -55°C to +150°C
Lead Temperature (Soldering, 10sec.) ............. +300°C

esp
VOO

eSN
GNO
GATE

Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermallimitations and considerations of package.

PL
CT

SOIC-16, TSSOP-16 (Top
View)
DorPWPacka

esp

IMAX

voo
CSN
GNO
GATE
PL

Nle
FLT

CT

ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD = 5V, TA = O°C to 70°C for the UCC3919, -40°C
to 85° fort he UCC2919 and - 55°C to 125°C fort he UCC1919 All vo Itages are Wit. h respect t0 GND T A= TJ.
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Input Supply
Supply Current
Shutdown Current

VDD=3V

0.5

1

rnA

VDD=8V

1

1.5

rnA

SD=0.2V

1

5

!1A
V

Undervoltage Lockout
Minimum Voltage to Start

2.5

2.75

3

2

2.25

2.5

V

0.25

0.5

0.75

V

25°C, referred to CSP

1.47

1.5

1.53

V

Over Temperature Range, referred to CSP

1.44

1.5

1.56

1

2

Minimum Voltage after Start
Hysteresis
IBIAS
Output Voltage, (01lA < lOUT < 15J.1A)
Maximum Output Current

5-69

V
rnA

UCC1919
UCC2919
UCC3919
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD = 5V, TA = O°C to 70°C for the UCC3919, -40°C
to B5° for the UCC2919 and -55°C to 125°C for the UCC1919 All voltages are with respect to GND TA -- TJ
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Current Sense
Over Current Comparator Offset

Referred to CSP, 3V ~ VDD

BV

-55

-50

-45

mV

Linear Current Amplifier Offset

VIMAX = 1OOmV, Referred to CSP,
3V~VDD~ BV

~

-110

-100

-90

mV

VIMAX = 400mV, Referred to CSP,
3V~VDD~ BV

-410

-400

-390

mV

Overload Comparator Offset

VIMAX = 100mV, Referred to CSP,
3V~VDD~ BV

-360

-300

-240

mV

CSN Input Common Mode Voltage Range

Referred to VDD, 3V ~ VDD

-1.5

0.2

V

CSP Input Common Mode Voltage Range

Referred to VDD, 3V < VDD < BV, (Note 1)

0

0.2

V

~

BV, (Note 1)

Input Bias Current CSN

1

5

IlA

Input Bias Current CSP

100

200

l1A

Current Fault Timer
CT Charge Current

Vcr = 1V

-56

-35

-16

CT Discharge Current

Vcr= 1V

0.5

1.2

1.9

IlA
IlA

On Time Duty Cycle in Fault

IpL=O

1.5

3

6

%

CT Fault Threshold

1.0

1.5

1.7

V

CT Reset Threshold

0.25

0.5

0.75

V

-1

0

1

l1A

IpL = -2501lA, Referred to VDD

-1.0

-1.4

-1.9

V

IpL = -1.5mA, Referred to VDD

-0.5

-1.B

-2.2

V

IpL = -2501lA

0.25

0.5

1

IpL=-1.5mA

0.05

0.1

0.2

%
%

O.B

V

IMAX
Input Bias Current

VIMAX= 100mV, Referred to CSP

Power Limiting Section
Voltage on PL
On Time Duty Cycle in Fault
SD and UR Inputs
Input Voltage Low
Input Voltage High

2

UR Input Current

1

3

6

mA

100

270

50b

kO

10

IlA

1

V

-0.25

mA

SO Internal Pulldown Impedance

V

FLTOutput
Output Leakage Current

VDD=5V

Output Low Voltage

lOUT = 10mA

FET GATE Driver and Charge Pump
Peak Output Current

VCAP = +15V, VGATE = 10V

Peak Sink Current

VGATE = 5V

-3

mA

20

Fault Delay
Maximum Output Voltage

-1
100

300

nS

VDD = 3V, Average lOUT = 11lA

B

10

12

V

VDD = BV, Average lOUT = 111A

12

14

16

V

Charge Pump UVLO Minimum Voltage to
Start

VDD=3V

6.5

7.5

VDD=BV

6.5

B

Charge Pump Source Impedance

VDD = 5V, Average lOUT = 11lA

50

100

Note 1: Guaranteed by design. Not 100% tested in production.

5-70

V
V
150

kQ

UCC1919
UCC2919
UCC3919
PIN DESCRIPTIONS
CAP: A capacitor is placed from this pin to ground to filter the output of the on board charge pump. A .011lF to
0.11lF capacitor is recommended.
CSN: The negative current sense input signal.
CSP: The positive current sense input signal.
CT: Input to the duty cycle timer. A capacitor is connected from this pin to ground, setting the off time and
the maximum on time of the overcurrent protection circuits.

FLT: Fault indicator. This open drain output will pull low
under any fault condition where the output driver is disabled. This output is disabled when the IC is in low current standby mode.
GATE: The output of the linear current amplifier. This pin
drives the gate of an external N-channel MOSFET pass
transistor. The linear current amplifier control loop is internally compensated, and guaranteed stable, for output
load (gate) capacitance between 100pF and.01IlF. In
applications where the GATE voltage (or charge pump
voltage) exceeds the maximum Gate-to-Source voltage
ratings (VGs) for the external N-channel MOSFET, a
Zener clamp may be added to the gate of the MOSFET.
No, additional series resistance is required since the internal charge pump has a finite output impedance of
100kn typical.
GNO: The ground reference for the device.
IBIAS: Output of the on board bias generator internally
regulated to 1.5V below CSP. A resistor divider between
this pin and CSP can be used to generate the IMAX voltage. The bias circuit is internally compensated, and requires no bypass capacitance. If an external bypass is
required due to a noisy environment, the circuit will be

stable with up to .OO1IlF of capacitance. The bypass
must be to CSP, since the bias voltage is generated with
respect to CSP. Resistor R2 (Figure 4) should be greater
than 50kn to minimize the effect of the finite input impedance of the IBIAS pin on the IMAX threshold.
IMAX: Used to program the maximum allowable sourcing
current. The voltage on this pin is with respect to CSP. If
the voltage across the shunt resistor exceeds this voltage the linear current amplifier lowers the voltage at
GATE to limitthe output current to this level. If the voltage across the shunt resistor goes, more than 200mV beyond this voltage, the gate drive pin GATE is
immediately driven low and kept low for one full off time
interval.

UR: Latch/Reset. This pin sets the reset mode. If UR is
low and a fault occurs the device will begin duty ratio current limiting. If UR is high and a fault occurs, GATE will
go low and stay low until UR is set low. This pin is internally pulled low by a 3flA nominal pulldown.
PL: Power Limit. This pin is used to control average
power dissipation in the external MOSFET. If a resistor is
connected from this pin to the source of the external
MOSFET, the current in the resistor will be roughly proportional to the voltage across the FET. As the voltage
across the FET increases, this current is added to the
fault timer charge current, reducing the on time duty cycle from its nominal value of 3% and limiting the average
power dissipation in the FET.
SO: Shutdown pin. If this pin is taken low, GATE will go
low, and the IC will go into a low current standby mode
and CT will be discharged. This TTL compatible input
must be driven high to turn on.
VOO: The power connection for the device.

APPLICATION INFORMATION
The UCC3919 monitors the voltage drop across a high
side sense resistor and compares it against three different voltage thresholds. These are discussed below. Figure 1 shows the UCC3919 waveforms under fault
conditions.

Fault Threshold
The first threshold is fixed at 50mV. If the current is high
enough such that the voltage on, CSN is 50mV below
CSP, the timing capaCitor Cr begins to charge at about
35flA if the PL pin is open. (Power limiting will be discussed later). If this threshold is exceeded long enough
for Cr to charge to 1.5V, a fault is declared and the ex-

ternal MOSFET will be turned off. It will either be latched
off (until the power to the circuit is cycled, the UR pin is
taken low, or the SO pin is toggled), or will retry after a
fixed off time (when Cr has discharged to 0.5V), depending on whether the UR pin is set high or low by the user.
The equation for this current threshold is simply:
I FAULT = -0.05
'-'-

(1 )

RSENSE

The first time a fault occurs, Cr is at ground, and must
charge 1.5V. Therefore:

5-71

tFAULT

= tON (sec) =

CT (IlF)-1.5
35

(2)

UCC1919
UCC2919
UCC3919
APPLICATION INFORMATION
In the retry mode, the timing capacitor ~iII already be
charged to 0.5V at the end of the off time: so all subsequent cycles will have a shorter ton time, given by:

. _
tFAULT

CT (~F)

(3)

=toN(sec)=gs

reduces the voltage on GATE to control the external
MOSFET in a constant current mode.
During this time CT is charging, as described above, If
this condition lasts long enough for CT to charge to 1.5V,
a fault will be declared and the MOSFET will be turned
off. The IMAX current is calculated as follows:

Note that these equations for ton. are without the power
limiting feature (RPL pin open). The effec~s of power limiting on ton will be discussed later.
.
The off time in the retry mode is· set by CT and an internal 1.21lA sink current. It is the time it takes CT to discharge from 1.5V to 0.5V. The equation for the off time is
therefore:
(4)
CT~F
tOFF (sec) = - 1.2
Shutdown Characteristics
When the SD pin is set to TTL high (above~V) the
UCC3919 is guaranteed to be enabled. When SD is set
to a low TTL (below 0.8V) the UCC3919 is guaranteed to
be disabled, but may not be in ultra low current sleep
mode. When SD is set to 0.2V or less, the UCC3919 is
guaranteed to be disabled and in ultra low current sleep
mode. See Fig. 1.

1.e·02
1.e·03
1.e.()4

l- t-

~ 1.e'()5

I MAX --

RSENSE

Note that if the voltage on the IMAX pin is programmed
to be less than 50mV below CSP, then the UC3919 will
control the MOSFET in a constant current mode all the
time. No fault will be declared and the MOSFET will remain on because IMAX is less than IFAULT·
Overload Threshold
There is a third threshold which, if exceeded, will declare
a fault and shutdown the external MOSFET immediately,
without waiting for CT to charge. This "Overload" threshold is 200mV greater than the IMAX threshold (again,
this is with respect to CSP). This feature protects the circuit in the event that the external MOSFET is on, with a
load current below IMAX, and a short is quickly applied
across the output. This allows hot-swapping in cases
where the UCC3919 is already powered up (on the backplane) and capacitors are added across "the output bus.
In this case, the load current could rise too quickly for the
linear amplifier to reduce the voltage on GATE and limit
the current to IMAX. If the overload threshold is reached,
the MOSFETwili be turned off quickly and a fault declared. A latch is set so that CT can be charged, guaranteeing that the MOSFET will remain off for the same
period as defined above before retrying. The overload
current is:

1.e·06

IOVERLOAD -_ VCSP

-VIMAX
RSENSE

1.e·07

1
VOLTAGE ON SO

+0.2 _I
-

MAX

0.2 (6)

+--RSENSE

Note that lOVER LOAD may be much greater than IMAX,
depending on the value of RSENSE.

1.e·08
0

(5)

Vcsp -:- V IMAX

2

.

PowE!r Limiting

Figure 1. Typical Shutdown Current
IMAX Threshold
The second threshold is programmed by the voltage on
IMAX (measured with respect to the CSP pin). This controls the maximum current, IMAX, that the i.JCC3919 will
allow to flow into the load during the MOSFET on time. A
resistive divider connected between IBIAS and CSP generates the programming voltage. When the drop across
the sense resistor reaches this voltage, a linear amplifier

A power limiting feature is included which allows the
power dissipated in the external MOSFET to be held
relatively constant during a short, for different values of
input Voltage. This is accomplished by connecting a resistor from the output (source of the external MOSFET)
to PL. When the output voltage drops due to a short or
overload, an internal bias current is generated which is
equal to:

5-72

I

- (V/N
PL =

-VO~T
RpL

-Vpd

(7)

UCC1919
UCC2919
UCC3919
APPLICATION INFORMATION (cont.)
This current is used to help charge the timing capacitor
in the event that the load current exceeds IFAULT. (A simplified schematic of the circuit internal to the UCC3919 is
shown in Figure 2.) The result is that the on time of the
MOSFET during current limit is reduced as the input voltage is increased. This reduces the effective duty cycle,
holding the average power dissipated constant.

r-----------------------

VDD

:

UCC3919

I ~'~

VDD

'111 I Id I"
I

L_______________________ !

I

It can be seen that power limiting will only occur when IpL
is > 0 (it cannot be negative). For power limiting to begin
to occur, the voltage drop across the MOSFET must be
greater than VDD-VPL or 1.4V(typ).
(8)

The on time using RPL is defined as:

CT

-~V

IpL +35-10

-6

where ~V = 1V

(12)

For a resistive load of value RL and an output cap COUT,
CTmin can be smaller than in the constant current case,
and can be estimated from:

Figure 2. Power limiting circuit.

tON =

To guarantee recovery from an overload when operating
in the retry mode, there is a maximum total output capacitance which can be charged for a given toN (fault
time) before causing a fault. For a worst case situation of
a constant current load below the fault threshold, CT(min)
for a given output load capacitance (without power limiting) can be calculated from:

A larger load capacitance or a smaller CT will cause a
fault when recovering from an overload, causing the circuit to get stuck in a continuous hiccup mode. To handle
larger capacitive loads, increase the value of CT. The
equation can be easily re-written, if desired, to solve for
COUT(max) for a given value of CT.

UGD·99124

V1N - VOUT ;;:: 1.4V

Calculating Cnm1n) for a Given Load Capacitance
without Power Limiting

IMAX -I LOAD

I

TO
LOAD

(11 )

.) V1N -COUT _35_10-6
CT (min
=--"-'----"':::..:....----

imb-J
RPL PL1

PDlSS =I MAX -VIN -0.033

(9)

-COUT -

RL -

R. n(1-

C (min)=

V1N

)

(13)

IMAX -RL

28_10 3

T

Note that in the latch mode (or when first tuming on in
the retry mode), since the timing capacitor is not recovering from a previous fault, it is charging from OV rather
than 0.5V. This allows up to 50% more load capacitance
without causing a fault.

Estimating Cnmin) When Using Power Limiting

The graph in Figure 4 illustrates the effect of RpL on the
average MOSFET power dissipation into a short. The
equation for the average power dissipation during a short
is:
(10)

,..,
_IMAX - V1N -tON
'DISS tON +tOFF

If power limiting is used, the calculation of CTmin for a
given COUT becomes considerably more complex, especially with a resistive load. This is because the CT charge
current becomes a function of VOUT, which is changing
with time. The amount of capacitance that can be
charged (without causing a fault) when using power limiting will be significantly reduced for the same value CT,
due to the shorter ton time.
The charge current contribution from the power limiting
circuit is defined as:

If PL is left unconnected, the power limiting feature will
not be exercised. In the retry mode, the duty cycle during
a fault will be nominally 3%, independent of input voltage. The average power dissipation in the extemal MOSFET with a shorted output will be proportional to input
voltage, as shown by the equation:
5-73

IpL == (VIN -VOUT -Vpd
RpL

(14)

UCC1919
UCC2919
UCC3919
APPLICATION INFORMATION (cont.)

(VDD - VIMAX)

lOUT

RSENSE
OUTPUT
CURRENT

IMAX
IFAULT
IO(NOM)

OA

VCT
1.5V
CT
VOL TAGE
O.5V

OV

------------- -

50mV

I
__ I_-

-------I

I
I
I

I
I
I
I
I

I
I
I
I
I

--T--I-I
I
I
I
I

RSENSE

-------- -- -------- --1--------

I
I
I
I
I
I
I
I
I

-----1-I
I
I
I
I
I
I

-'---.-rI
I
I
I
I

VOUT
VCC
OUTPUT
VOLTAGE

UDG-97073

to: Normal condition - Output current is nominal, outPl,lt
voltage is at positive rail, Vee.
" '

goes low, the FET turns off allowing no
output current toJlow, \(OUT discharg,es to GND.

t1: Fault control r~ached - Output current rises abQve
the programmed, fault value, CT begins 'lo ,charge with
351lA + IpL·
..

t4: Retry - CT has discharged to O.5V, but fault current
is still exceeded, CT begins charging again, FET is on,
VOUT increases.

t2: Maximum current reached - Output current reaches
the programmed maxilTlum level and beco,mes a constant current with value IMAX.

t3 to ts: Illustrates <3% duty cycle depending upon
RPL selected.

t6 =t4
,t3: Fault occurs - CT has charged to 1.5V, fault output ,t7: Fault released, normal condition - return to normal
bperath:>n of the circuit breaker

Figure 3. Typical Timing Diagram

'1. ,",

5-74

UCC1919
UCC2919
UCC3919
APPLICATION INFORMATION (cont.)
Constant Current Load
0.3

I 0.251:::::::~_"""",,=:::::====RPL=

For a constant current load, the output capacitor will
charge linearly. During that time:
I pdavg) ==

(V

V)2

_
~
;::;

(15)

IN - PL
2 e R pL eV/N

if
_
~
15
a:

Modifying equation (12) yields:

CT(mln)

0.15

t----;;;;::---:::::::::=---~=- 15K
;

i

0.1 t - - - - - = = = = = " " " " - - - 1 0 K

~ 0.05 t - - - - - - - - - - - - - - i

2

.

24.9K

0.2t---;;;;;;;=--=""'"""-......===::::-::-:!
20K

Y,N e COUT e [(VIN - V p d + 35e10-6(]6)
2 e R pL eV,N

a.

== -----'=--------~

O+--.---.--r-~-_-__i

I MAX -IWAD

2

3

4

5

6

VDD (Volts)

Resistive Load
Determining CT(min) for a resistive load is more complex. First, the expression for the output voltage as a
function of time is:
(17)

Figure 4. MOSFET average short circuit power
dissipation vs. V,N for values of RpL'

Assuming that the device is operating in the retry mode,
where CT is charging from 0.5V to just below 1.5V in time
t, CT is defined as:
leT edt
CT =~=leT edt Where

Solving for TSTART when VOUT = VIN yields:

-RWAD e COUT e.en

(1-(

Y,N

'MAX

eRLOAD

(19)

leT = (' pL +35 e 10-6)

(18)

TSTART =

))

IMAX

CSP

O.OH}

VDO
'---_.....I 2

ISlAS

CSN

I

0.0111F

~

GNO

NlC

1 '(ffi""
5

-=-

UR

GATE
PL

I

+------~ 6

I

SO

FLT

CT

o---_-n

9 t---JOV\!Ior-......___
I
I
I

CT

I

O.0111F

VOUT

~ f---__-+.---l

L __________ ...!
UDG·98137

Figure 5. Application Circuit

5-75

UCC1919
UCC2919
UCC3919
APPLICATION INFORMATION (cont.)
Substituting equation (15) irito (19) yields:
2

CT(min) = [(VIN -Vpd +35_ 10 c-6)_dt .
2- RpL - VIN

(20)

This yields the following expression for CT(min) for a resistive load with power limiting. By substituting the value
calculated for TSTART in equation (18) for dt,.CT(min) is
determined.
2
C (min) = [(VIN _Vpd +35_10--6]_T
T
2 R
V
START
- PL - IN

(21)

For a worst case 5A constant current load: COUT(max) ==
27IlF.,
With UR grounded, the part will operate in the retry or
"hiccup" mode. The values shown for CT and RpL will
yield a nominal duty cycle of 0.32% and an off time of
8.3ms. With a shorted output, the average steady state
power dissipation in 01 will be less than 1OOmW over the
full input voltage range.
.
If powerlimlting is disabled by opening RpL, then:
tFAULT=toNsec=

Example
The example in Figure 5 shows the UCC3919 in a typical
application. A low value sense resistor arid N~channel
MOSFET minimize losses. With the values shown for R1,
R2, and Rs, the overcurrent fault will be SA nominal. Linear current limiting (I MAX) will occur at 7.14A and the
overload comparator will trip at 27A. The calculations are
shown below.
I

- 0.05 _ 0.05 - 5A
FAULT - Rs - 0.01 -

(22)

I

_ Vcsp - VIMAX
MAX Rs

(23)

CTIlF -1

.35

2871ls

PDlSS (shorted) = IMAX - VIN - tON
tOFF + tON
'.
--6
".
7.14 - 5 - 287 -10
=1.2W (with V/N
287_10--6 +8.33_10-3

(29)

(30)

= 5V)

For a worst case 10 resistive load: COUT(max) == 220IlF.
For a worst case 5A constant current load: COUT(max) ==
120IlF.
THERMAL CONSIDERATIONS
Steady State Conditions

1.5-R1
=7.14A
(R1+R2)-Rs

0.2

0.2

IOVERLOAD =IMAX +-=7.14A+-=27.14A
Rs
0.01
CTIlF 0.01
TOFF (sec)=--=-=8.33ms

1.2

(24)

(25)

1.2

In normal operation; with a steady state load current below IFAULT, the power dissipation in the external MOSFETwili be:
(31)
The junction temperature of the MOSFET can be calcu-.
lated from:
T J =TA + (PDlSS

-e JA )

(32)

With the value shown for RpL:
I PL(typ) (output shorted) =
( VIN - VPL ) =
RpL

(5

(26)

-1.6) = 340llA
10k

tON (shorted) =

Where TA is the ambient temperature and eJA is the
MOSFET's thermal resistance from junction to ambient.
If the device is on a heatsink, then the following equa. tion:
(33)

(27)

CT

PDI55 (shorted) = I MAX- V IN - tON

(28)

tON +tOFF

7.14 - 5- 271ls =0.12W
271ls + 8.33 _10-3

Where eJC is the MOSFET's thermal resistance from
junction to case, ecs is the thermal resistance from case
to sink,. and eSA is the thermal resistance of the heatsink
to ambient.
.
The calculated TJ must be lower than the MOSFET's
maximum junction temperature rating, therefore:
TJ(max)-TA
eJA<----=-'--::----'---'-'-

PDISS

Fora worst case 10 resistive load: COUT(m81<) == 471lF.
5-76

(34)

UCC1919
UCC2919
UCC3919
APPLICATION INFORMATION
Transient Thermal Impedance
During a fault condition in the retry mode, the average
MOSFET power dissipation will generally be quite low
due to the low duty cycle, as defined by:
PO/55 (avg) = I MAX • V/N • tON
tON +tOFF

(w/output shorted) (35)

is normalized, it must first be multiplied by 9JC before using in the equation above.
This effective transient thermal impedance, when multiplied by the pulse power, will give the transient temperature rise of the die. To keep the junction temperature
below the maximum rating, the following must be true:

T J (max) - T.c
p o/ss (pulse)

9 JC (trans) = --=--"---:-'--':'-

(In the latch mode, tOFF will be the time between a fault
and the time the device is reset.)
However, the pulse power in the MOSFET during toN,
with the output shorted, is:
PO/55

(pulse) = I MAX

•

V/N (w/output shorted)

(36)

In choosing toN for a given VIN, IMAX' and duty cycle it is
important to consult the manufacturer's transient thermal
impedance curves for the MOSFET to make sure the device is within its safe operating area. These curves provide the user with the effective thermal impedance of the
device for a given time duration pulse and duty cycle.
Note that some of the impedance curves are normalized
to one, in which case the transient impedance values
must be multiplied by the DC (steady state) thermal resistance, 9Jc.
For duty cycles not shown in the manufacturer's curves,
the transient thermal impedance for any duty cycle and
ton time (given a square pulse) can be estimated from
[1]:

9 JC (trans) = (D. 9JC) + (1- D). 9 sp
where D is the duty cycle:

(37)

(38)

If necessary, the junction temperature rise can be reduced by reducing ton (using a smaller value for CT), or
by reducing the duty cycle using the power limiting feature already discussed. Note that in either case, the
amount of load capacitance, COUT, that can be charged
before causing a fault, will also be reduced.

Safety Recommendations
Although the UCC3919 is designed to provide system
protection for all fault conditions, all integrated circuits
can ultimately fail short. for this reason, if the UCC3919
is intended for use in safety critical applications where
UL or some other safety rating is required, a redundant
safety device such as a fuse should be placed in series
with the device. The UCC3919 will prevent the fuse from
blowing for virtually all fault conditions, increasing system
reliability and reducing maintenance cost, in addition to
providing the hot swap benefits of the device.

References
[1]

International Rectifier, HEXFET Power MOSFET Designer's Manual, Application Note 949B, Current Ratings, Safe
Operating Area, and High Frequency SWitching Performance of Power HEXFETs, pp.1553-1565, September 1993.

tON
tON +tOFF

and 9sp is the single pulse thermal impedance given in
the transient thermal impedance curves for the time duration of interest (tON). Note that these are absolute numbers, not normalized. If the given single pulse impedance

UNITRODE CORPORATION
7 CONTINENTAL BLVD.• MERRIMACK, NH 03054
TEL. (603) 424-2410 FAX (603) 424-3460

5-77

~UNITRODE

UCC1921
UCC2921
UCC3921

Latchable Negatiye Floating Hot Swap Power Manager
FEATURES

, DESCRIPTION

• Precision Fault Threshold

The UCC3921 family of negative floating hot swap power managers provides complete power management, hot swap, and fault handling capa"
bility. The IC is referenced to the negative input voltage and is powered
.through ,an external resistor connected to ground, which is essentially a
current drive as opposed to the traditional voltage drive. The onboard
10V shunt regulator protects the IC from excess voltage and serves as a
reference for programming the maximum allowable output sourcing current during a fault. All control and housekeeping functions are integrated
and externally programmable. These include the fault current level, maxi'. mum output sourcing current, maximum fault time, selection of Retry or
Latched mode, soft start time, and average power limiting. Inthe event of
a constant fault, the internal timer will limit the on time from less than
0.1 % to a maximum of 3% duty cycle. The duty cycle modulation depends on the current into PL, which is a function of the voltage across
the FET,thus limiting average power dissipation in the FET. The fault
level is fixed at 50mV across the current sense amplifier to minimize total

• Programmable: Average Power
Limiting, Linear CUrrent Control,
Overcurrent Limit and Fault Time
• Fault Output Indication Signal
• Automatic Retry Mode or Latched
Operation Mode
• Shutdown Control

~ Undervoltage Lockout
• 250llS Glitch Filter on the SOFLTCH
pin
• a-Pin OIL and SOIC

(continued)

BLOCK DIAGRAM
IMAX

r---------I'

----------------

2

------------------,

~
J;....T 1
-

LOGIC

s.ov

+

..

voo
LINEAR CURRENT
AMPLIFIER

voo

SDFL TCH

1

'

I
I
I

>------....,I---i 7

OUT

DISABLE

I-~E=~F~IL~TE~R~}=======~~
R DTECT

PL

voo

'-----t----t-----j
AVG POWER LIMITING
SOmV

+

- +

COMPARATOR

Vss

L __________________________________________________

~

UDG·99052

3/98

5-78

UCC1921
UCC2921
UCC3921
DESCRIPTION (continued)
dropout. The fault current level is set with an external
current sense resistor, while the maximum allowable
sourcing current is programmed with a voltage divider
from VDD to generate a fixed voltage on IMAX. The current level, when the output acts as a current source, is
equal to VIMAxlRsENSE. If desired, a controlled current
start up can be programmed with a capacitor on IMAX.
When the output current is below the fault level, the output device is switched on. When the output current exceeds the fault level, but is less than the maximum
sourcing level programmed by IMAX, the output remains
switched on, and the fault timer starts charging CT. Once

CT charges to 2.5V, the output device is turned off and
performs a' retry some time later (provided that the selected mode of operation is Automatic Retry Mode).
When the output current reaches the maximum sourcing
current level, the output acts as a current source, limiting
the output current to the set value defined by IMAX.
Other features of the UCC3921 include undervoltage
lockout, S-pin Small Outline (SOl C) and Dual-In-Line
(DIL) packages, and a Latched Operation Mode option,
in which the output is latched off once CT charges to
2.5V and stays off until either SDFLTCH is toggled (for
greater than 1ms) or the IC is powered down and then
back up.

CONNECTION DIAGRAM

ABSOLUTE MAXIMUM RATINGS
IVDD .......................................... 50mA
SDFLTCH Current .............................. 10mA
PL Current .................................... 10mA
IMAX Input Voltage .............................. VDD
Storage Temperature ................... -65°C to +150°C
Junction Temperature ................... -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ............. +300°C
All voltages are with respect to Vss (the most negative voltage).
Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of Databook for thermal limitations and
considerations of packages.

DIL-8 , SOIC-8 (Top View)

N or J, 0 Packages

SDFLTCH

PL

IMAX

OUT

VDD

SENSE

CT

VSS

ELECTRICAL CHARACTERISTICS Unless otherwise specified, TA = O°C to 70°C for the UCC3921 and -40°C to 85°C
for the UCC2921, and -55°C to 125°C for the UCC1921; IVDD = 2mA, CT = 1nF (the minimum allowable value), there is no
resistor connected between the SDFLTCH and VSS pins TA= TJ
TVP
MAX UNITS
TEST CONDITIONS
MIN
PARAMETER
VDDSection
1
2
rnA
IDD
10.0
V
Regulator Voltage
9
9.5
ISOURCE = 2mA
9.15
9.6
10.15
V
ISOURCE = 10mA
V
6
7
8
UVLO Off VoltaRe
Fault Timing Section
mV
Overcurn:int Threshold
47.5
50
53.5
TJ= 25°C
Over Operating Temperature
46
50
53.5
mV
nA
Overcurrent Input Bias
50
500
CT Charge Current
-50
-22
-36
VCT=1V,lpL=0
I!A
-{J.7
-1.7
-1.2
rnA
Overload Condition, VSENSE - VIMAX = 300mV
CT Discharge Current
0.6
1
1.5
VCT=1V,lpL=0
I!A
CT Fault Threshold
2.2
2.45
2.6
V
0.41
0.57
V
CT Reset Threshold
0.49
Output Duty Cycle
Fault Condition, IpL = 0
1.7
2.7
3.7
%
5-79

UCC1921
UCC2921
UCC3921
ELECTRICAL CHARACTERISTICS Unless otherwise specified, T A = O°C to 70°C for the UCC3921 and -40°C to 85°C
for the UCC2921, and -55°C to 125°C for the UCC1921; IVDD = 2mA, CT = 1 nF (the minimum allowable value), there is no
resistor connected between the SDFLTCH and VSS pins T A = T J
PARAMETER

TEST CONDITIONS

MIN

TYP

10UT=OmA

8.5

10

IOUT=-1mA

6

8

MAX

UNITS.

Output Section
Output High Voltage
Output Low Voltage

0

lOUT = OmA, VSENSE- VIMAX= 100mV

200·

lOUT = 2mA, VSENSE- VIMAX= 100mV

V
V
10

mV

600

mV

Linear Amplifier Section
Sense Control Voltage

VIMAX= 100mV

85

100

115

mV

VIMAX = 400mV

370

400

430

mV

50

500

nA

Input Bias
Power Limiting Section
VSENSE Regulator Voltage

IpL= 641JA

4.35

4.85

5.35

V

Duty Cycle Control

IpL= 641lA

0.6

1.2

1.7

IpL= 1mA

0.045

0.1

0.17

%
%

300

500

Overload Section
Delay to Output

Note 1

Output Sink Current

V SENSE - VIMAX = 300mV

40

100

Threshold

Relative to IMAX

140

200

260

mV

3

5

VD.D+1

V

VSDFLTCH = 5V

50

110

250

250

500

6

9.5

5

8.5

ns
rnA

Shutdown/FaultiLatch Section
Shutdown Threshold
Input Current
Filter Delay Time (Delay to Output)
Fault Output High
ISDFLTCH = -1001JA
Fault Output Low
Output Duty Cycle

Fault Condition, IpL = 0

1.7

ISDFLTCH = -1001JA, Fault Condition, IpL = 0

IlA
1000 \ IlS
V
V

0

10

mV

2.7

3.7

%

0

%

Note 1: Guaranteed by design. Not 100% tested in production.

PIN DESCRIPTIONS
CT: A capacitor is connected to this pin in order to set
the fault time. The fault time must be longer than the time
to charge external load capacitance. The fault time is
defined as:
TFAULT

2 e CT

=-ICH

where ICH = 36JlA + IPL, and IPL is the current into the
power limit pin. Once the maximum fault time is reached
the output will shutdown for a time given by:
TSD

=2e10 6 eCT

voltage on IMAX over the current sense resistor. If
desired, a controlled current start up can be programmed
with a capacitor on IMAX, and a programmed start delay
can be achieved by driving the shutdown with an open
collector/drain device into an RC network.
OUT: This pin provides gate output drive to the MOSFET
pass element.

PL: This feature ensures that the average MOSFET
power dissipation is controlled. A resistor is connected
from this· pin to the drain of the NMOS pass element.
When the voltage across the NMOS exceeds 5V, current
will flow into the PL pin which adds to the fault timer
charge current, reducing the duty cycle from the 3%
level. When IPL»36JlA, then the average MOSFET
power dissipation is given by:

IMAX: This pin programs the maximum allowable
sourcing current. Since VDD is a regulated voltage, a
voltage divider can be derived from VDD to generate the
program level for IMAX. The current level at which the
output appears as a current source is equal to the
5-80

UCC1921
UCC2921
UCC3921
PIN DESCRIPTIONS (continued)
SENSE: Input voltage from the current sense resistor.
When there is greater than SOmV across this pin with
respect to VSS, then a fault is sensed, and CT starts to
charge.

If an Sk < RLATCH < 2S0k.Q resistor is placed from this pin
to VSS, then the latched operating mode will be invoked.
Upon the occurrence of a fault, under the latched mode
of operation, once the CT capacitor charges up to 2.SV
the NMOS pass element latches off. A retry will not
periodically occur. To reset the latched off device, either
SDFLTCH is toggled high for a duration greater than
1ms or the IC is powered down and then up.

SOFLTCH: This pin provides fault output indication,
shutdown control, and operating mode selection.
Interface into and out of this pin is usually performed
through level shift transistors. When open, and under a
non-fault condition, this pin pulls to a low state with
respect to VSS. When a fault is detected by the fault
timer, or undervoltage lockout, this pin will drive to a high
state with respect fo VSS, indicating the NMOS pass
element is OFF. When> 2S0llA is sourced into this pin
for> 1ms, it drives high causing the output to disable the
NMOS pass device.

VOO: Current driven with a resistor to a voltage approximately 10V more positive than VSS. Typically a resistor
is connected to ground. The 10V shunt regulator clamps
VDD approximately 10V above VSS, and is also used as
an output reference to program the maximum allowable
sourcing current.
VSS: Ground reference for the IC and the most negative
voltage available.

APPLICATION INFORMATION

r-----------------------------------------------,

I

TO LOAD

OVERLOAD
COMPARATOR

PL
VOUT

TO
OUT

~~N--

t

-1

13

+

lmA

--

Rs
VSS
(INPUT VOLTAGE)

V~D

I
I
I
I
I
I
IL ______________ _

2.5V

O.2V

I
I
I
I
TO IMAX PIN
I
I
I
I
I
I
TO OUTPUT I
DRIVE
H-OFF

FAUL T TIMING CIRCUITRY

4

CT

CT - - - - - - - - - - - - - - - - - - - - - - - - - - - -

T

vss

Figure 1. Fault Timing Circuitry for the UCC3921, Including Power Limit Overload
S-81

UDG·96275-1

UCC1921
UCC2921
UCC3921

APPLICATION INFORMATION (continued)
Figure 1 shows the detailed circuitry for the fault timing
function of the UCC3921. For the time being, we will discuss a typical fault mode, therefore, the overload comparator, and current source 13 does not work into the
operation. Once the voltage across the current sense resistor, Rs, exceeds SOmV, a fault has occurred. This
causes the timing capacitor to charge with a combination
of 361JA plus the current from the power limiting amplifier.
The PL amplifier is designed to only source. current into
the CT pin and to begin sourcing current once the voltage across the output FET exceeds SV. The current IpL
is related to the voltage across the FET with the following

OUTPUT
CURRENT
(los OF EXT FET)

CT
VOLTAGE
(W/RESPECT TO Vss)

expression:
I PL = VFET-SV
RpL

where VFET is the voltage across the NMOS pass de~
vice. Later it will be shown how this feature will limit average power dissipation. in the pass device. Note that
under a condition where the output current is more than
the fault level, but less than the max level, VOUT "" VSS
(input voltage), IpL = 0, the CT charging current is 361JA.
During a fault, CT will charge at a rate determined by the

::~:a--~L [b

1FlT
1
()
OUT nom
OA

--

VeT

1
1

2.SV

o.sv
ov
VOUT

1

1
11
11

1
1
1

1
11
11

1
1

1
1

1
1

(

r.,.____

l '

.,.,--I---T-------. I

111
111

-+-H- ---'---t~~--tik~--i-~
_1_: :__i----~-~--~~~---J-~-~-~-I

I
1
1

I I
I I
I I

I
I
I

I
I
I

I
I
I

III
III
III

I
1
1

I
I
I

OUTPUT VOLTAGE
ov _.j...J...l_...l_
~~
I
(VORAIN OF EXT FET)
: ::
:
1
:
(W/RESPECT TO SYSTEM GND)
I 1
.I
I I
VSS~~~L--L---~~~---~+I~----L~-~~S~--__
• I
10 11 12 13
14
15
16 17 18
19 110

I:

I

UDG-96276

to: Safe condition. Output current is nominal, output
voltage is at the negative rail, VSS.
t1: Fault control reached. Output current rises above
the programmed fault value, CT begins to charge at
-361JA.

t2: Maximum current reached. Output current reaches
the programmed maximum level and becomes a constant current with value IMAX.
t3: Fault occurs. CT has charged to 2.SV, fault output
goes high, the FET turns off allowing no output current
to flow, VOUT floats up to ground.
t4: Retry. CT has discharged to O.5V, but fault current
is still exceeded, CT begins charging again, FET is on,
VOUT pulled down towards VSS.
Figure 2. Retry Operation Mode

t5

=t3: Illustrates 3% duty cycle.

t6 = t4: Retry. CT has discharged to O.SV, but fault is
still exceeded, CT begins charging again, FET is on,
VOUT pulled down towards VSS.
t7: Output short circuit. If VOUT is short circuited to
ground, CT charges at a higher rate depending upon
the values for VSS and RpL.
t8: Fault occurs. Output is still short circuited,but the
occurrence of a fault turns the FET off so no current is
conducted.

t9

=t4: Output short circuit released, still in fault mode.

t10 = to: Fault released, safe condition. Return to normal operation of the hot swap power manager.

UCC1921
UCC2921
UCC3921
APPLICATION INFORMATION (cont.)
OUTPUT

,'T-----tD~----'elh'T

CURRE~T

(los OF EXT FET)

_+r=:_r.,--_.

e,
-----')')SS'r

CT
VOLTAGE
(W/RESPECT TO Vss)

O.SV
OV ~~~~7---------~I--~I--------~~--~

sse,

VOUT
OUTPUT VOLTAGE
OV
(VORAIN OF EXT FET)
(WI RESPECT TO SYSTEM GNO)

~e,

SV

LATCHSET
VOLTAGE
(INTERNAL SIGNAL)

OV
VSDFLTCH

10V
S.SV

'/r-~ I

')SS

VSS
VLATCHSET

SOFL TCH
VOLTAGE
(W/RESPECT TO Vss)

I

VCT
2.SV

c,...-.. I
I
I

I I
I I

I
I
I
I
I

I I
I I
I I

--rrr-

I I

I
I

I

e)ss
I I

--+-1-1--1---

--,-t-t--

I I I
I I I
OV ~~~~L---~~--L--'---------19L--IL10------~ll~1~112-ILI3--~c,...-..1
10 1112 13
141S16
17
IS
UDG-96277

to: Safe condition. Output current is nominal, output
voltage is at the negative rail, VSS.
t1: Fault control reached. Output current rises above
the programmed fault. value, CT begins to charge at
-361JA.
12: Maximum current reached. Output current reaches
the programmed maximum level and becomes a constant current with value IMAX.
t3: Fault occurs. CT has charged to 2.5V, fault output
goes high as indicated by the SDFLTCH voltage. The
FET turns off allowing no output current to flow, V6UT
floats up to ground, and since there is an 82kn resistor
from the SDFLTCH pin to VSS, the intemal latchset
signal goes high.
t4: Since the user does not want the chip to LATCH off
during this cycle, he toggles SDFLTCH high for greater
than 1ms {t6 - t4 > 1ms}.
t5: The latchset signal is reset.
t6: Forcing of SDFLTCH is released after having been
applied for> 1ms.
t7: Retry (since the latchset signal has been reset to its'
low state) - CT has discharged to O.5V, but fault current
is still exceeded, CT begins charging again, FET is on,

VOUT pulled down towards VSS.
t8 = t3: Fault occurs. CT has charged to 2.5V, fault output goes high as indicated by the SDFLTCH voltage,
the FET turns off allowing no output current to flow,
VOUT floats up to ground. and since there is an 82kn
resistor from SDFLTCH to VSS, the internal latchset
signal goes high.
t9: Output is latched off. Even though CT has discharged to O.5V, there will not be a retry since the
latch set signal was allowed to remain high.
t10: Output remains latched off. CT has discharged all
the way to OV.
t11: The output has been latched off for quite some
time. The user now wishes to reset the latched off output, thus toggling SDFLTCH high for greater than 1 ms
{t13-t11}.
t12

=t5: The latchset signal is reset.

t13: ForCing of SDFLTCH is released after having been
applied for > 1ms. The fault had also been released
during the time the output was latched off, safe condition, return to normal operation of the hot swap power
manager.
.

Figure 3. Latched Operation Mode: RLATCH = 82k
5-83

UCC1921
UCC2921
UCC3921
APPLICATION INFORMATION (continued)
internal charging current and the external ti'ming capacitor. Once CT charges to 2.SV, the fault comparator
switches and sets the fault latch. Setting of the fault latch
causes both the output to switch off and the charging
switch to open. CT must now discharge with the 1IJ.A current source, 12, until O.SV is reached. Once the voltage at
CT reaches O.SV, the fault latch resets, which re-enables
the output and allows the fault circuitry to regain control
of the charging switch. If a fault is still present, the fault
comparator will close the charging switch causing the cycle to repeat. Under a constant fault, the duty cycle is
given by:
Duty Cycle =
IpL

tem.

Determining External Component Values
To set RVDD (see Fig. 4) the following must be achieved:
V min
RVDD

R1

,-

1~ A
+ IJ.

R2

I

I
I
I
I
I
I

=V""Te/M"ve
,-'"

""

for
currant
source load

I LOAD

_ [

ROUT for
resistive load

I

FET,va

2 A

2 IMAX

Average power dissipation in the pass element is given
by:

R

10V
R1+R2

-1N- - > - - - + m

V55 5

~U~~3!22 __ J

1IJ.A

I PL + 361J.A

UDG-96278

Where VFET»SV IpL can be approximated as:

Figure 4.

VFET
RpL

and where IpL»36IJ.A, the duty cycle can be approximated as:
1IJ.AeR pL

VFET
Therefore, the maximum average power dissipation in
the MOSFET can be approximated by:

PFET AVG = VFET

11J.A e RpL

el MAX e ---'V:-:-~=

FET

= IMAX e1IJ.A e R pL

Notice that in the approximation, VFET cancels, thereby
limiting the average power dissipation in the NMOS pass
element.

Overload Comparator
The linear amplifier in the UCC3921 ensures that the
output NMOS does not pass more than IMAX (which is
V1MAX/RsENSE). In the event 'the output current exceeds
the programmed IMAX by O.2V1RsENSE, which can only
occur if the output FET is not responding to. a command
from the IC, CT will begin charging with 13, 1mA, and
continue to charge to approximately 8V. This allows a
constant fault to show up on the SDFLTCH pin, and also
since the voltage on CT will continue charging past 2.SV
in an overload fault mode, it can be used for detec~ion of
output FET failure or to build redundancy into the sys-

In order to estimate the minimum timing capacitor, CT,
several things must be taken into account. For example,
given the schematic in Figure 4 as a possibl.e (and at this
pOint, a standard) application, certain external component values must be known in order to estimate CTMIN.
Now, given the values of COUT, Load, RSENSE, Vss, and
the resistors determining the voltage on the IMAX pin,
the user can calculate the approximate startup time of
the node VOUT. This startup time must be faster than the
time it takes for CT to charge to 2.SV (relative to Vss),
and is the ba~is for estimating the minimum value of CT.
In order to determine the value of the sense resistor,
RSENSE, assuming the user has determined the fault current, RSENSE can be calculated by:
.
SOmV
. RSENSE = - IFAULT

Next, the variable IMAX must be calculated. IMAX is the
maximum· current that the UCC3921 will allow through
the transistor, M1, and it can be shown that during
startup with an output capacitor the power MOSFET, M1,
can be modeled as a constant current source of value
IMAXwhere

I MAX

=

V1MAX

where VIMAX =voltage on pin IMAX.

RSENSE

Given this information, calculation of the startup time is
now possible via the following:

S-84

UCC1921
UCC2921
UCC3921

APPLICATION INFORMATION (continued)
Grmin=

Current Source Load:

3-TsTART -(72 11A- R pL +lVss [-10V)
10-RpL

I

GOUT -IVss
TSTART = -:------:----'
/MAX -/WAD

Resistive Load:

Resistive Load:

GTmin=

TSTART =
G
-R
OUT
OUT

3 - TSTART - (3611A - RpL + IVss [- 5V -/MAX - ROUT)
5-R pL

-fn( /MAX/MAX
-ROUT
J
- ROUT -IV
SS [

Once TSTART is calculated, the power limit feature of the
UCC3921 must be addressed and component values derived. Assuming the user chooses to limit the maximum

/

IMAX=4A
20

/

15
Cl

/

:( 12.5
11.

/ / V,..... .......--

7.5

~V

~V
:::::&.

00

./

V ,/"

/

10

2.5

00

/

17.5

5

RPL, =

r-

/

RPL=10M

-

Level Shift Circuitry to Interface with SDFLTCH

1) When open, and under a non-fault condition,
SDFLTCH is pulled to a low state. In Figure 6, the
N-channel level shift transistor is off, and the
FAULT OUT signal is pulled to LOCAL VDD through
R3. This indicates that the HSPM is not faulted.

RPL=5M

RPL=2M

~

RPL=1M

2) When a fault is detected by the fault timer or undervoltage lockout, this pin will drive to a high state, indicating that the external power FET is off. In Figure 6,
the N-channel level shift transistor will conduct, and
the FAULT OUT signal will be pulled to a Schottky
Diode voltage drop below LOCAL GND. This indi-

RPL=500k
RPL=200k

~ w ~ 1001~ 1W1~ ~o
VFET

Figure 5. Plot Average Power vs FET Voltage for
Increasing Values of RPL
allowable average power that will be associated with the
hot swap power manager, the power limiting resistor,
RPL, can be easily determined by the following:
RpL = PFET avg
111A -/MAX

[- GOUT

5-R pL

Some type of circuit is needed to interface with the
UCC3921 via SDFLTCH, such as opto-couplers or level
shift circuitry. Figure 6 depicts one implementation of
level shift circuitry that could be used, showing component values selected for a typical -48V telecommunications application. There are three communication
conditions which could occur; two of which are Hot Swap
Power Manager (HSPM) state output indications, and the
third being an External Shutdown.

25
22.5

3 - ROUT - [ VSS

+--~~~~~--~~

PMOS
200V
SHUTDOWN
FAULT OUT

R5
l60k

where a minimum RpL exists

FROM

defined by RpL min = [Vss [ (Refer to Figure 5).
5mA

'----+-.... SDFL TCH

LOCAL
GND

PIN
RLATCH
82k
(OPTION)

Finally, after computing the aforementioned variables,
the minimum timing capacitor can be derived as such:
Current Source Load:

VSS

UDG·96279

Figure 6. Possible Level Shift Circuitry to
Interface to the UCC3921, showing component
values selected for a typical telecom application.
5-85

UCC1921
UCC2921
UCC3921
APPLICATION INFORMATION (continued)
cates that the HSPM is faulted. The Schottky Diode
is necessary to ensure that the FAULT OUT signal
does not traverse too far below LOCAL GND, making fault detection difficult.

be disabled. The current sourced into SDFLTCH
must be limited to 10mA or less: ISDFLTCHMAX <
10mA.

SAFETY RECOMMENDATIONS

If a 5k < RLATCH < 250kO resistor is tied betWeen
SDFLTCH & VSS, as optionally shown in Figure 6,
then the latched operating mode (described earlier)
will be invoked upon the occurrence of a fault.

Although the UCC3921 is designed to provide system
protection for all fault conditions, all integrated circuits
can ultimately fail short. For this reason, if the UCC3921
is intended for use in safety critical applications where
UL® or some other safety rating is required, a redundant
safety device such as a fuse should be placed in series
with the external power FET. The UCC3921 will prevent
the fuse from blowing for virtually all fault conditions, increasing system reliability and reducing maintenance
cost, in addition to providing the hot swap benefits of the
device.

-=-:-:-:=:::--::-:-:-:::-:

3) To externally shutdown the HSPM, the SHUTDOWN
signal (typically held at LOCAL VDD) must be pulled
to LOCAL GND. Assuming SHUTDOWN is tied to
LOCAL GND, the P-channel level shift transistor will
conduct, driving SDFLTCH high (to roughly VDD
plus diode). By sourcing> 2501lA into SDFLTCH
for > 1ms the output to. the external power FET will

a

LOCAL
GND

"O~"

RvoO
12.7k

R1

R2
1k

97.6k

+----+-..JIJVIr......-'l/VIr--+-_

LOCAL VDD

---

SHUTDOWN

VSS

Cvss

'5V"

- - 3 --..:..----PMOS:

'5V"

200V

FAULT OUT
'5V"

VOO

2

-,

IMAX

OV

:

I
I
I

I
I
I

'I LOAO FOR A CURRENT SOURCE LOAD
ROUT FOR A RESISTIVE LOAD

I
I
I

LOCALGND
'OV'

f-OiIL--......--J 1
NMOS
200V

SDFLTCH

I
I
I
I
I
I

I
I
I
I

L - -- - - - - -

VSS
CT

5
I
I

1-----;
CT

~L_-_-_-_-_._-I1InJ_F_~

VSS
(-48V POWER BUS)

VSS
(-48V POWER BUS)
UDG·9S053

Figure 7, Typical Telecommuicati.ons Application
(The "Negative Magnitude-Side" of the Supply is Switched in)

5-86

UCC1921
UCC2921
UCC3921
APPLICATION INFORMATION (continued)
VBUS~__~~~~~~~~~____>VBUS
-,
POSITIVE VOLTAGE BUS

C VDD

WHERE VBUS > '2V
RS
33k

VRB > ,2V

VSS
VBUS

"SV"

1!4=

4

NMOS
200V

-------

SHUTDOWN

COUT

,-

"OV'

LOCALGND

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

~

"SV'
LOCALVDD

?-,:6k
'SV'

-------

FAULT OUT

~I

NMOS
200V

,
RLATCH
82k
(LATCHED
OPERATING
MODE
SELECTED)

-A

VSS

VSS

I
I
I
I
I

L

VDD

IMAX
PL

OUT

SENSE
SDFLTCH

VSS
CT

--------If---~~~F------~

_______________________________________>
POWER GROUND BUS

Figure 8. Floating Positive Application
The "Ground-side" of the Supply is Switched In

UNITRODE CORPORATION
7 CONTINENTAL BLVD.' MERRIMACK, NH 03054
TEL. (603) 424-2410' FAX (603) 424-3460

I

5-87

.

VSS
UDG-98054

~UNITRODE

UCC3981
PRELIMINARY

Universal Serial Bus Hot Swap Power Controller
FEATURES

DESCRIPTION

• Fully USB Compliant

The UCC3981 Hot Swap Power Controller is designed to provide a self
powered USB hub with a local 3.3V regulated voltage and four 5V regulated voltages for USB ports. Each of the 5V outputports is individually
enabled for optimal port control. Each port also provides an overcurrent
fault signal indicating that the port has exceeded a 500mA current limit.
The 3.3V linear regulator is used to power the local USB microcontroller.
This regulator is protected with a 100mA current limit and has a logic
level enable input.

• Support Four 5V Peripherals and One
USB 3.3V Controller
• Separate Power Enables
• 500mA Current Limiting per Channel
• Separate Open Drain Fault Indicator
for Each Channel

The UCC3981 can be configured to provide USB port power from a
loosely regulated voltage such as a Filament voltage internal to a monitor. Pre-regulation is provided by an internal linear regulator controller
and one external logic level N-channel MOSFET. The UCC3981 can
also be configured without using the pre-regulator stage by connecting
the VREG pins to a regulated 5.5V 2A source.

• 3.3V Output for USB Controller
• Available in 28 Pin Wide Surface
Mount and DIP

The UCC3981 comes in a 28-pin wide SOIC power package optimized
for power dissipation, and is protected by internal over-temperature shutdown mechanism, which disables the outputs should the internal junction
temperature exceed 150°C.

APPLICATION AND BLOCK DIAGRAM

.I.

I

-===-v~

r-:::o'-.--=-0.......L-,

~:~
:

~

ENA

DCA

USB HUB
CONTROLLER

ENB
OCB

ENC
OCC

END

oco
I
I

I

UCC3981 USB HUB POWER CONTROLLER

:

~--------------~ND--------------~
"'iF

11198
5-88

UDG·97101

UCC3981

ABSOLUTE MAXIMUM RATINGS

CONNECTION DIAGRAM

VFIL ............................................ 9V
VCON Supply Votage .............................. 9V
Logic Inputs (ENA-D, ENHUB)
Maximum Forced Voltage ................. -o.3V to 7V
Maximum Forced Current ...................... ±lmA
V33
Maximum Forced Voltage ......................... 5V
Maximum Current ........................... 200mA
V5A-D
Maximum Voltage ............................... 9V
Maximum Current ........................... 750mA
Storage Temperature ................... -65°C to +150°C
Junction Temperature ................... -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ............. +300°C

SOIC-28 (Top View)
DWP Package

DRIVE

N/C

occ
ENC
V5C
VREG
V5D

Unless otherwise indicated, voltages are reference to ground.
Pulsed is defined as a less than 10% duty cycle with a maximum
duration of 500!J,S. Currents are positive into, negative out of the
specified terminal. All voltages are with respect to ground. Consult Packaging Section of Databook for thermal limitations and
considerations of packages.

GND'

GND'
OCB

OCD
END
VREF

V33

VHUB

VFIL

ENHUB

GATE

• DWP package pin 28 serves as signal ground;
Pins 7, 8, 9,20,21,22 serve as heatsinklground.

ELECTRICAL CHARACTERISTICS Unless otherwise specified, TJ = O°C to 125°C for the UCC3981. VFIL = 6.5V,
VHUB=5V TA=TJ
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

1

3

rnA

1

3

rnA

2.5

2.65

V

3

10

mV
V

Input Supply Currents
VHUB Supply Current

No External Load on V33

VFIL Supply Current
Reference
VREF Voltage

Over Temperature

Line Regulation

VHUB = 4.5V to 9V

2.35

3.3V Regulator
V33Voitage

TJ = 25°C, ILOAD = lOrnA

3.2

3.3

3.4

3.165

3.3

3.435

V

VHUB = 6V, Output shorted to Ground

100

120

150

rnA

OA to 2A, O°C to 125°C, VFIL = 6V to 9V

5.25

5.5

5.7

V
V

OmA to 100mA, O°C to 125°C, VHUB = 4.5V to 9V
Short Circuit Current Limit
Pre-Regulator
VREG Voltage
5V Regulator
V5A-D Voltage
Short Circuit Current Limit

TJ = 25°C, ILOAD = 250mA, VREG = 5.5V

4.85

5

5.15

OmA to 500mA, O°C to 125°C

4.8

5

5.2

V

VREG = 5.5V, Output Shorted to Ground

500

600

750

rnA
V

Charge Pump
Quiescent Output Voltage

TJ = 25°C, VFIL = 6V, ENA-D = 5V, ENHUB = 5V
O°C to 125°C, VFIL = 6V

Output Impedance

5-89

11

11.45

12

10.5

11.45

12

V

9

15

kn

UCC3981

ELECTRICAL CHARACTERISTICS Unless otherwise specified, TJ = O°C to 125°C for the UCC3981. VFIL = 6.5V,

-

VHUB-5V
TA-TJ
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

Enable Inputs
ENA-O Inputs - Guaranteed Low

0.7

ENA-O Inputs - Guaranteed High

3

V

ENHUB Input - Guaranteed Low

0.7

ENHUB Input - Guaranteed High

V

3

V
V

Overcurrent Signals
Active Sink Current

140

locx =100!tA

500

mV

PIN DESCRIPTIONS
mum) current limit, and overcurrent indicator.

ENA-D: Separate enables pins for each of the four SV
supplies.

V33: 3.3V regulator output. Enable when ENHUB is high.
Current limit is 100mA minimum.

ENHUB: Enables the 3.3V output V33. Pulling this pin
low disables V33.

VDRIVE: Internal charge pump voltage is brought out for
external decoupling. Nominal voltage is between 11 V
and 13V. No external loading permitting. Decouple with
at least 0.001 ~F capaCitor.

GATE: Gate drive for an external NMOS used to regulate the S.SV VREG supply. Minimum available drive is

11V.

VFIL: Bias supply for all four of the 5V regulators. VFIL
voltage must be between 6V and 9V.

GND: All 6 GND pins must be tied to the system ground.
In addition to serving as electrical conductors, these 6
pins are heat sinks. Refer to the Packaging Device Temperature Management guide in the Packaging section of
the Unitrode Databook.

VHUB: Supply for the 3.3V USB controller power supply
and bandgap reference.

OCA-D: Open drain overcurrent indicator. OCA-D can be
wire OR'ed by the user to create a single overcurrent indicator.
V5A-D: SV regulated output with enable, SOOmA (mini-

VREF: Internal 2.5V reference is brought out for external
decoupling only. Decouple with 0.01 ~F capacitor.
VREG: Regulated to S.SV by means of an external
NMOS. Two pins supply up to a total of 2.5A to the four
SV bus voltages (VSA, V5B, V5C, VSD).

UNITRODE CORPORATION
7 CONTINENTAL BLVD .• MERRIMACK, NH 03054
TEL. (603) 424-2410' FAX (603) 424-3460

S-90

~UNITROCE

UCC39811
PRELIMINARY

Universal Serial Bus Hot Swap Power Controller
FEATURES

DESCRIPTION

• Support Four SV Peripherals and One
USB 3.3V Controller

The UCC39811 Hot Swap Power Controller is designed to provide a self
powered USB hub with a local 3.3V regulated voltage and four SV regulated voltages for USB ports. Each of the SV output ports is individually
enabled for optimal port control. Each port also provides an overcurrent
fault signal indicating that the port has exceeded a 6S0mA current limit.
The 3.3V linear regulator is used to power the local USB microcontroller.
This regulator is protected with a 100mA current limit and has a logic
level enable input.

• Separate Power Enables
• 6S0mA Current Limiting per Channel
• Separate Open Drain Fault Indicator
for Each Channel
• 3.3V Output for USB Controller

The UCC39811 can be configured to provide USB port power from a
loosely regulated voltage such as a Filament voltage internal to a monitor. Pre-regulation is provided by an internal linear regulator controller
and one external logic level N-channel MOSFET. The UCC39811 can
also be configured without using the pre-regulator stage by connecting
the VREG pins to a regulated S.SV 2A source.

• Available in 20 Pin DIP

The UCC39811 comes in a 20-pin DIP package and is protected by internal over-temperature shutdown mechanism, which disables the outputs
should the internal junction temperature exceed 1S0°C.

APPLICATION AND BLOCK DIAGRAM

VFIL

VREG

----------

I

3.3V
REGULATOR

r-''--...l..-......L..-,
0+ D-

~
I
= ~

IENA :

181-------f--l~1

-

OCA

ENB
OCB
USB HUB
CONTROLLER
ENC

occ
END

OCD
I
I

UCC39811 USB HUB POWER CONTROLLER

I

L-------- -- -0 -----------------:

-1

03/99

S-91

GND

UDG-98199-1

UCC39811

ABSOLUTE MAXIMUM RATINGS

CONNECTION DIAGRAM

VFIL. ........................................... 9V
VHUB Supply Voltage .............................. 9V
Logic Inputs (ENA-D, ENHUB)
Maximum Forced Voltage ................. -0.3V to 7V
Maximum Forced Current. . . . . . . . . . . . . . . . . . . . .. 1mA
V33
Maximum Forced Voltage ......................... 5V
Maximum Current ........................... 200mA
V5A-D
Maximum Voltage ............................... 9V
Maximum Current ........................... 900mA
Storage Temperature ................... 65°C to +150°C
Junction Temperature ................... -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ............. +300°C

DIP 20 (Top View)
N Package

Unless otherwise indicated, voltages are reference to ground.
Pulsed is defined as a less than 10% duty cycle with a maximum
duration of 500IlS. Currents are positive into, negative out of the
specified terminal. All voltages are with respect to ground. Consult Packaging Section of Databook for thermal limitations and
considerations of packages.

V5B

VREG

GND

V5A

OCB

ENA
OCA
VDRIVE

V33

VHUB

oce

VFIL

ENC

VREF

V5C

VREG

END
OCD

ELECTRICAL CHARACTERISTICS Unless otherwise specified, TJ = O°C to 125°C for the UCC39811. VFIL = 6.5V,
VHUB = 5V TA= TJ
PARAMETER

TEST CONDITIONS

MIN

TVP

MAX

UNITS

Input Supply Currents
VHUB Supply Current

No External Load on V33

VFIL Supply Current

1

3

mA

1

3

mA

2.5

2.65

V

3

10

mV
V

Reference
VREF Voltage

Over Temperature

Line Regulation

VHUB = 4.5V to 9V

2.35

3.3V Regulator
V33Voitage

3.2

3.3

3.4

3.165

3.3

3.435

V

VHUB = 6V, Output shorted to Ground

100

120

150

mA

OA to 2A, O°C to 125°C, VFIL = 6V to 9V

5.25

5.5

5.7

V

TJ = 25°C, ILOAD = 250mA, VREG = 5.5V

4.85

5

5.15

V

OmA to 500mA, O°C to 125°C

4.8

5

5.2

V

VREG = 5.5V, Output Shorted to Ground

650

750

900

mA

11

11.45

12

V

10.5

11.45

12

V

9

15

k

0.7

V

0.7

V

T J = 25°C, ILOAD = 10mA
OmA to 100mA, O°C to 125°C, VHUB = 4.5V to 9V

Short Circuit Current Limit
Pre-Regulator
VREG Voltage
5V Regulator
V5A-D Voltage
Short Circuit Current Limit
Charge Pump
Quiescent Output Voltage

TJ = 25°C, VFIL = 6V, ENA-D = 5V, EN HUB = 5V
O°C to 125°C, VFIL = 6V

Output Impedance
Enable Inputs
ENA-D Inputs - Guaranteed Low
ENA-D Inputs - Guaranteed High

V

3

ENHUB Input - Guaranteed Low
ENHUB Input - Guaranteed High

3

V

Overcurrent Signals
Active Sink Current

140

locx =1 001lA

5-92

500

mV

UCC39811

PIN DESCRIPTIONS
ENA-D: Separate enables pins for each of the four SV
supplies.
ENHUB: Enables the 3.3V output V33. Pulling this pin

low disables V33.
GATE: Gate drive for an external NMOS used to regu-

late the S.SV VREG supply. Minimum available drive is
11V.
GND: All 6 GND pins must be tied to the system ground.

In addition to serving as electrical conductors, these 6
pins are heat sinks. Refer to the Packaging Device Temperature Management guide in the Packaging section of
the Unitrode Databook.
OCA-D: Open drain overcurrent indicator. OCA-D can be
wire OR'ed by the user to create a single overcurrent indicator.
V5A-D: SV regulated output with enable, SOOmA (mini-

mum) current limit, and overcurrent indicator.
V33: 3.3V regulator output. Enable when ENHUB is high.

Current limit is 100mA minimum.
VDRIVE: Internal charge pump voltage is brought out for
external decoupling. Nominal voltage is between 11 V
and 13V. No external loading permitting. Decouple with
at least 0.001 j.lF capacitor.
VFIL: Bias supply for all four of the SV regulators. VFIL
voltage must be between S.SV and 9V Can be tied to
VRE.
VHUB: Supply for the 3.3V USB controller power supply
and bandgap reference.
VREF: Internal 2.SV reference is brought out for external
decoupling only. Decouple with 0.01 j.lF capacitor.
VREG: Regulated to S.SV by means of an external

NMOS. Two pins supply up to a total of 2.SA to the four
SV bus voltages (V5A, VSB, VSC, V5D).

UNITRODE CORPORATION
7 CONTINENTAL BLVD.· MERRIMACK, NH 03054
TEL. (603) 424-2410· FAX (603) 424-3460

S-93

~UNITROCE

UCC3985
ADVANCE INFORMATION

Programmable CompactPCITM Hot Swap Manager
FEATURES

TYPICAL APPLICATION

• Fully CompactPCFM compliant

1--------------,

• Features and ranges programmable
using internal non-volatile memory
• Four Channels for individual control of
4 supplies
• Minimal external parts count
• Precise Linear Current Amplifier for
controlled current ramping
• True ramp-up and ramp-down current
slew control
• Precision 2X over-current detection
• High voltage charge pump permits
design with lower cost external NFET
devices
• Shutdown control with low sleep mode
quiescent current

~

PUMPIN

20mn"

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I

~

PUMPGND

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I

,--------I1sl

CPUMP

-.lC1 i

I'"
d

VIN~

2.5mn

i
CRMP

lo,o01~F

I

i
2mn

• Input under-voltage lockout (UVLO)

I

• Wide input operating range: -15V to
15V

~

;, Easily programmable for other
applications

BACKPLANE POWER BUS

I

I

I

~GND
I

• Windows 95/98 programming
interface and utilities

~GND
I

• 24 Pin SOIC and TSSOP package

I

I

I

L _ _ _ _ _ _~------"

HEALTHY

BACK-END POWER BUS
UOG-99060

DESCRIPTION
The UCC3985 family of Compact PCI Hot Swap Power • Independent Linear Current Limit and Under-voltage
detection
Managers (HSPM) provides fully programmable supply
management using an absolute minimum of external
• Supply sequencing order
support components_ The UCC3985 provides full man• Fault event behavior
agement of 3 positive supplies and 1 negative power raiL
The UCC3985 is the first HSPM to offer on-Chip
• Common Voltage fault filter time
non-volatile memory, which allows the user to customize
Like other Unitrode Hot Swap Power Managers the
the performance of the part to the application. This feaUCC3985 utilizes a Linear Current Amplifier (LCA) in
ture enables interactive programming during the circuit
each of its 4 channels to provide closed loop control of
development phase, leading to rapid product deployment
the inrush current profile during start-up. The LCA conProgramming during development is supported with an
cept allows the designer to program the startup current
easy to use PC parallel port interface and a Windows
95/98 based Graphical User Interface (GUI). UCC3985 slew rate and steady state leveL The  cs -'?> 0.-'?> ~\~J-csJ-

0._z.

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CH4
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CONTROL CONTROL CONTROL

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>-

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DOWN

CH1
CONTROL

UP

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VOLTAGE FAULTFILTER
STATE
OPTIONS

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STATE MACHINE

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VREF •

032-047

048-055

Il56-D63

SINGLE PIN, RJW SERIAL INTERFACE

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UCC3985

DESCRIPTION (cont.)
cations. Current limit range and fine adjust for each
channel are fully programmable to allow for an easy
match of desired current limit and standard, low value,
current sense resistors. Low input offset and set-point
voltages make board copper trace resistors feasible for
high current applications.

over-current threshold set to precisely 2 times the programmed current limit value. Detection of an over-current
condition on any rail(s) can be set to cause the corresponding external N-channel MOSFET(s) device(s) to be
latched off immediately with the remaining supplies being
ramped down per the pre-programmed schedule.

A versatile programmable state machine defines how the
supplies are sequenced and how the device responds to
a fault or over-current condition. A programmable Voltage
Fault Delay Filter can be set to enable compatibility with
the longer voltage ramps associated with large bus filter
capacitance. To protect the host system power bus, the
UCC3985 can provide fault protection in the form of an
electronic circuit breaker with a programmable

The UCC3985 is designed to work with supplies ranging
from -15V to +15V. A 24V onboard charge pump multiplier ensures maximum external N-channel MOSFET
gate overdrive offering the use of lower cost devices for
the equivalent insertion loss. A separate PUMPIN pin allows for pump connection to the highest input supply for
maximum pump efficiency.
The UCC3985 is available in 24 pin SOIC (OW) and 24
pin TSSOP packages.

ABSOLUTE MAXIMUM RATINGS

CONNECTION DIAGRAM

VIN_1, VIN_2, VIN_3 ....................... 0.3Vto 15V
VS_1, VS_2, VS_3 ...... -0.3 to VIN (corresponding channel)
CS_1, CS_2, CS_3 ..... -0.3 to VIN (corresponding channel)
VIN_4,VS_4 ............................... -15 to 0.3V
BD_SEL. ................................. -0.3 to 20V
PUMPIN .................................. -0.3 to 15V
HEALTHY ................................ -0.3 to 12V
Storage Temperature .................... -65°C to 150°C
Junction Temperature .................... -55°C to 150°C
Lead Temperature (Soldering, 10 seconds) .......... 300°C

SOIC-24 or TSSOP-24 (Top View)
OW Package

Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermalJimitations and considerations of packages. All voltages are
referenced to GND.

PUMPIN
PUMPGND
CPUMP

HEALTHY
V8_4
G.J?

G_4
C8_4

VIN_2

VIN_4

PIN DESCRIPTIONS
BO_SEL: A logic low on this pin enables the UCC3985 to
supply power to the Back-End Bus. The logic threshold
for this pin is 1.5 Volts. When disabled, the UCC3985 enters a low current sleep mode. This pin also serves as
the input to the UCC3985 serial interface to read and
write memory data. This unique interface employs
multi-threshold voltage/current mode methods to enable
simUltaneous Data In, Data Out and Clock on a single
pin.
CRMP: A capacitor tied to this pin sets the linear ramp
up/down of the LCA current limit for each supply during
supply sequencing.

CS_1, CS_2, CS_3: These pins tie to the low end of the
external current sense resistor and are used along with
the VI N_1-3 pins as the input to the LCA.
CS3: This pin ties to the more positive end of the current sense resistor of the negative supply rail. It is used
with VIN_4 as the input to the LCA.
G_1, G_2, G_3: The Gate drive for the external NFETs
for the positive rail switches. The gate drive is controlled
as a function of sequencing and current to a value between 0 and 24 volts. The LCA is internally compensated
and guaranteed stable for a wide range of gate capacitance.

5-96

UCC3985

PIN DESCRIPTIONS
G_4: Gate drive for the negative rail switch. This pin is
driven in response to sequencing and load current to a
voltage between VIN_4 and ground. An external
pull-down resistor should be used between G_4 and
CS_4.
GND: Analog grounds for the device.
HEALTHY: In the CompactPC/™ application, this pin is
driven low to indicate the board's suitability to be connected to the bus. This is an open drain output which is
driven false if the Back End power is not within the tolerances programmed into the under-voltage comparators,
the result of an over-current on either supply controller or
a fault time-out on either supply during linear ramp-up.
PUMPC: Charge Pump output. A 11lF capacitor should
be connected from this pin to ground. This capacitor provides charge storage to drive the gate of the external
NFET device for each channel.

PUMPGND: Ground for internal charge pump multiplier.
PUMPIN: This is the input to the charge pump multiplier.
It should be connected to the highest input supply voltage to ensure sufficient gate overdrive for the NFET of
the highest supply rail. It is recommended to place a
0.11lF de-coupling capacitor from this pin to PUMPGNO
to minimize board level noise due to internal charge
pump switching.
VIN_1, VIN_2, VIN_3: These pins tie to the positive
backplane supplies.
VIN_4: This pin ties to the negative backplane supply.
VS_1, VS_2, VS_3: These are the voltage sense pins for
the positive Back-End power bus.
VS_4: This is the voltage sense pin for the negative
Back-End power bus.

APPLICATION INFORMATION
Programmability:
The UCC3985 has 64 bits of user settable non-volatile
memory. These bits are programmed through the
BO_SEL pin and the self-clocking, multilevel, read-able
and writ-able serial interface of the UCC3985. The
UCC3985 PC Parallel Port Interface Kit and Windows
95/98 Drivers provides the user with a quick and easy
means to customize the UCC3985 to the specific application. A "LOCK" bit can be set to disable the serial interface
and prevent any future modification of memory contents.
Once the customization is developed, high volume delivery can be fully preprogrammed at the factory.
Non-Volatile Memory Bits:
00-07, UV RANGE: These bits (2 per channel) set the
coarse range of the under-voltage detection comparators.
The positive and negative supplies can be individually set
to 2.7V, 3.3V, 5.0V or 12V. The "UP" and ''~OWN'' comparison information is used to detect an output fault or to
determine the completion of an individual supply ramp sequence.
08-023, UV RANGE TRIM: These bit positions provide
additional resolution in the trim of the UV RANGE of each
channel.

UNITRODE CORPORATION
7 CONTINENTAL BLVD.• MERRIMACK. NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460

5-97

024-031, IMAX RANGE: The coarse range of the IMAX
current limit can be set with 2 bits of resolution per channel. These bits allow a range adjustment of the equivalent voltage drop across the external current sense
resistor while in closed loop linear current control. This
value can be set from 10mV to 80mV.
032-047, IMAX RANGE TRIM: The current limit range
set by IMAX RANGE can be fine tuned with an additional 4 bits of resolution per channel with these bits.
048-062, STATE MACHINE: Bits 48-55 set the amount
of time that the UCC3985 is allowed to operate in the
constant current mode during supply sequencing. This
time can be set from 0 and 150 mSec and is common to
all 4 channels. Bits 56-58 set the supply up/down sequence. Bits 59-63 determine how the state machine responds to a fault condition.
063, LOCK: Once set, this bit permanently disables the
serial interface and disconnects it from the BO_SEL pin,
preventing any further change of memory contents.
064-080, FACTORY PRETRIM: These readable positions are permanently written at the factory. They contain
customer specific and product version information as
well as parametriC pre-trim information.

~UNITRDDE
Simple Single

UCC3995
ADVANCE INFORMATION

ChanneIE~<:ternal

N-FET Hot Swap Manager

FEATURES

DESCRIPTION .

• Preci$e Linear Current Amplifier for
precision inrush current profile
programming

TheUCC3995 family of Hot Swap Power Managers provides the most
functions available in the industry in a simple 8 pin package requiring minimal·external parts count. The UCC3995 needs few external components
to operate, producing the lowest total system cost.

• Programmable over-current detection
threshold
• Internal Charge Pump for control of
external NMOS devices
• Shutdown Control with low sleep
mode quiescent current
• Input undervoltage lockout (UVLO)
• Input operating range: 2.75V to 5.5V
• Simple 8-pin part

Like other Unitrode Hot Swap Power Managers (HSPM) the UCC3995 utilizes a Linear Current Amplifier (LCA)to provide closed loop control and direct programming of the inrush current profile during start-up. The LCA
allows the designer to program the maximum inrush current level and the
slew rate of the inrush current. In addition, the <1mV input offset voltage of
the LCA allows for low value sense resistors while not compromising low
current applications and minimizing insertion loss across the hot swap interface.
To maintain the integrity of the host system power bus, the UCC3995 provides fault protection in the form of an electronic circuit breaker with a programmable over-current threshold. Detection of an over-current condition
will result in the external NMOS device being immediately latched off.
The UCC3995 allows the designer to program how long the HSPM can operate in the current control mode to satisfy system specific load current requirements.

BLOCK AND SIMPLIFIED APPLICATION DIAGRAM
RS

RMAX

r----------------I
I
I

I
I
I

IMAX

C2

I
ISC

+

:

'"' ~-------~------- ----------------------- -~G~-~j

UDG·99058

04199

5-98

UCC3995

CONNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS
VcdCS .................................. -o.3V to 7V
Pin Voltage ( Except CP Gate) .......... -o.3V to VCC+O.3V
Pin Voltage ( CP and Gate) .................. -O.3V to 24V
ISET current. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OmA to 1mA
Storage Temperature .................... -65°C to 150°C
Junction Temperature .................... -55°C to 150°C
Lead Temperature ............................. 300°C

SOIC-8 (Top View)

D Package
8

VCC/CS

2

7

GATE

CT 3

6

CP

5

GND

IMAX

Currents are positive into, negative out of the specified terminal. Consult packaging section of Databook for thermal limitations and package considerations.

EN

ISC

4

PIN DESCRIPTIONS
IMAX: This pin programs the constant current threshold
level. The voltage across the resistor (RIMAX connected
between IMAX and the input voltage rail) will be equal to
the voltage across Rs in constant current mode. The
current sink on IMAX is determined by the resistor connected from the ISET pin to ground. The inrush current
slew rate can be controlled by placing a capacitor in parallel with RIMAX.

/

_(VReRMAX)
MAX (Rs eRes)

/se -V
- R
_/

e

/se - MAX

(RMAX +R,NT )
Rs eRes
e

(1+R'NT)
-'---,::---"-'-'--'RMAX

ISET: Output used to set the precision current sink on
the IMAX pin as well as the Over-current threshold. A resistor should be connected from ISET to ground.
GND: Ground connection for the IC.
GATE: Output of the Linear Current Amplifier. This pin is
used to drive the gate of the external NMOS device.
VCC/CS: This dual function pin is used for input power to
the chip as well as current sense input for the LCA. The
VCC current should have little effect on the accuracy of
the constant current threshold due to the small valued
sense resistor and the low supply current demands.
HVEN: Pulling this pin below O.BV will disable the external NMOS device and put the IC in sleep mode. Allowing
this pin to float or driving to VIN will enable the
UCC399S.

UNITRODE CORPORATION
7 CONTINENTAL BLVD.· MERRIMACK. NH 03054
TEL. (603) 424-2410· FAX (603) 424-3460

5-99

~UNITRDDE

UCC3996
ADVANCE INFORMATION

Dual Sequencing Hot Swap Power Manager
FEATURES

DESCRIPTION

• Precise Linear Current Amplifier for
high efficiency and low voltage drop

The UCC3996 family of Hot Swap Power Managers provides hot swap
control, fault handling and power supply sequencing of two positive supplies. The UCC3996 operates over a wide supply range allowing single
part inventory for a variety of output voltages.

• Controls inrush current and supply
voltage ramp; ramp up sequence and
slope and ramp down sequence

Like other Unitrode Hot Swap Power Managers the UCC3996 utilizes a
Linear Current Amplifier (LCA) to provide closed loop control arid direct
• Easily expandable to three or more
programming of the inrush current profile during start-up. The LCA allows
supplies
the designer to program the maximum inrush current level and the slew
• Programmable over-current detection
rate of the inrush current. In addition, the <1 mV input offset voltage of the
threshold
LCA allows for low value sense resistors while not compromising low cur• High voltage charge pump to drive low rent applications and minimizing insertion loss across the hot swap interface.
cost external NMOS devices
To maintain the integrity of the host system power bus, the UCC3996 pro• Programmable soft start capability and
vides fault protection in the form of an electronic circuit breaker with a profault timer
grammable overcurrent threshold. Detection of an overcurrent condition will
• Fault output indicator
result in the external NMOS device being immediately latched off.
.
• Shutdown Control with low sleep
mode current «1pA)

The UCC3996 allows the designer to program,how long the HSPM can operate in the current control· mode to satisfy system specific load requirements.

• Input undervoltage lockout
• Wide input operating range: 2.75V to
13.6V
• 16 pin SOIC and DIP packages

BLOCK DIAGRAM
VCClCS1

IMAX1

1

GATE1

DOWN1

UP1

UP2 DOWN2

GATE2

CS2

H---I---------j

RAMPOFF

RAMP·UP
COMPARATOR

ENABLE

3

,

S

a

>-----lR

Q

RAMP·UP
COMPARATOR

SHUlDOWN

L________________ ~-GND

TIME1~

VCP

TIME2

13

FAULT

~CT
,

,

12 - - - - - - - - - - - - - - - - - - - - 4 - - - - - - - - - - - - - - - - - - - - - - ,
CPUMP

IREF
UDG·99059

04199

5-100

UCC3996

CONNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS
Vcc!CS1 ................................ -O.3V to 15V
Pin Voltage
(Except Vcc!CS1, CP Gate1, Gate2) .. -D.3V to VCC +O.3V
IREF Current ............................... 0 to -1 mA
Storage Temperature .................... -65°C to 150°C
Junction Temperature .................... -55°C to 150°C
Lead Temperature .............................. 300°C

DIP·16, SOlC·16 (Top View)
Packages
IMAX1
UP1

Currents are positive into, negative out of the specified terminal. Consult packaging section of databook for thermal limitations and package considerations.

VCC/CS1
DOWN1

ENABLE

GATE1

IREF

FAULT

CT

CPUMP

CPUMP: Charge pump output. A 0.11lF capacitor should
be connected from this pin to ground. The capacitor provides charge storage to drive the gate of the external
NMOS devices.

GND

GATE2

UP2

DOWN2

CS2: Current sense input 2. This pin is used as the current sense for the LCA on the second supply controller.
This must be connected to the sense resistor on the input supply with the lowest voltage.

IMAX2

PIN DESCRIPTIONS

CT: Fault timer capacitor. A capacitor connected from
this pin to ground determines the amount of time that the
UCC3996 is allowed to operate in the constant current
mode. The capacitance value must be selected to ensure that the load capacitance has adequate time to
charge.
Note: Connecting a scope probe or other metering device will
alter the fault time.

DOWN1, DOWN2: Ramp-down comparator inputs 1 and
2. These inputs are used to sequence the turn-off of the
two supplies. The supply will start its turn-off when the
voltage on the DOWN1, DOWN2 input pin falls below
0.5V.
ENABLE: Device enable input. Pulling this pin below
O.BV will disable both external NMOS devices and put
the IC in sleep mode. Allowing this pin to float above
O.BV or driving to VIN will enable the UCC3996.
FAULT: Fault output. This pin will be active high when a
latched fault occurs. The fault can be the result of an
overcurrent on either supply controller or a fault time-out
on either supply during linear ramp-up.
GATE1, GATE2: Outputs of the Linear Current Amplifiers. These pins are used to drive the gates of the external NMOS devices. The LCA is internally compensated
and guaranteed stable for gate capacitance between
TBD and TBD.

CS2

GND: Ground connection for the IC.
IMAX1, IMAX2: Maximum source current. These pins
program the constant current threshold level. The voltage across the resistor (RIMAX connected between
IMAX1, IMAX2 and the input voltage rail) will be equal to
the voltage across RSENSE in constant current mode.
The current sink on IMAX1, IMAX2 is determined by the
resistor connected from the IREF pin to ground. Placing
a capacitor in parallel with R1MAX controls the inrush current slew rate.
IREF: Reference current. This pin sets the precision current sink on the IMAX1, IMAX2 pins as well as the
Overcurrent threshold. A resistor should be connected
from IREF to ground.
UP1, UP2: Ramp-up comparator inputs 1 and 2. These
inputs are used to sequence the ramp-up of the two supplies. The supply will ramp-up when the voltage on the
UP1/UP2 input pin exceeds 1.5V.
VCC/CS1: Supply input and current sense1. This dual
function pin is used for input power to the chip as well as
current sense input for the LCA. VCC must be connected
to the sense resistor on the input supply with the highest
Voltage. The VCC current should have little effect on the
accuracy of thte constant current threshold due to the
small valued sense resistor and the low supply current
demands.

UNITRODE CORPORATION
7 CONTINENTAL BLVD .• MERRIMACK, NH 03054
TEL. (603) 424·2410' FAX (603) 424-3460

5-101

~UNITRODE

ON-58

Design Note

UCC3912 Programmable Electronic Circuit Breaker
- Performance Evaluation and Programming Information
by Bill Andreycak
The UCC3912 Demonstration Kit will enable designers to evaluate the performance of The UCC3912
Electronic Circuit Breaker in a typical application circuit. This kit features a number of _programming
options which include: individual "Hot Swap" of input
and output connections, maximum current, Fault cur-

rent level, and Shutdown. Each of _these is programmed via switches located on the board. An LED
indicates when the Current Fault Level comparator
has been triggered and the device is in a low duty cycle mode.

List of switches, connections and functions:
CONNECTION (IC pin #)

SWITCH

FUNCTION

SW1

VIN(2,3)

SW2

VOUT (14,15)

"Hot Swapping" of the output supply

SW3-1

IMAX(10)

Sets maximum current level

SW3-3

83(6)

Current Limit DAC Bit#3 input

SW3-4

B2(7)

Current Limit DAC Bit#2 input

SW3-5

B1 (8)

Current Limit DAC Bit#1 input

SW3-6

Bo(9)

Current Limit DAC Bit#O input

SW3-8

Shutdown (1)

Shutdown input to disable IC

+VIN

SW1

r-------------l

- - 0 .""'
TB1
GNO

~

"Hot Swapping" of the input supply

~+
+1

C1

l~~:

II
L

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--- I--

-

-

R7
1.8k

___ JI
RP1
#I<

r---------,

7~~o

I

VIN 2

8

BI

VIN$-

7

Bo

6

Bo

10 IMA.X

16 Fault
Out
OFF
SW3

l

-~-- -

r

!

(1)

-

(0) (.). (5) (6)

l 
---...--ri

f---,-_VOUT

To provide the circuit breaker function, the
UCC3912 uses an internal FET switch having a
typical on resistance of 0.150 ohms and 3 Amp
continuous current rating. The positive temperature characteristics of MaS devices are beneficial in parallel applications to help divide the total
load current evenly amongst all of the devices
used. The UCC3912 with the lowest on resistance will pass slightly more of the current than
the others, but its forward voltage drop will increase accordingly. This causes the load current
to steer towards the other devices (in parallel)
which were previously passing less current. With
this configuration, equilibrium will be reached
quickly as the total load current is distributed
amongst all of the slaves.
One feature of the UCC3912 is its digitally programmable threshold for overcurrent. limiting.
When this current level is reached, the UCC3912
control circuitry regulates current to the programmed IMAX amplitude. To facilitate this, the
gate drive to its internal MOS pass device is reduced, causing its on resistance and corresponding voltage drop to increase. As in the
previous example for paralleled devices, this
steers current to the other UCC3912s in parallel,
forcing load sharing.
The duration of this allowable overcurrent condition is also programmable by selecting the appropriate timing capacitor value to the IC's fault
timing (CT) pin. When the overcurrent condition
is detected, two protection functions begin operation. First, the UCC3912 goes into a constant
current mode to regulate current to the pro-

GND

>-------~~>---4

_ _I___ _ GND
UOO-9S1DD

Figure 1. Paralleling UCC3912 Electronic
Circuit Breakers

6/9SA

5-106

Design Note

ON-S8

grammed value of IMAX. Simultaneously, the device begins charging the fault timing capacitor
and provides a digital indication at the open collector FAULT pin of the IC. The overcurrent duration concludes when the timing capacitor
charges to a preset voltage and the MOS pass
transistor is turned off. The off time is internally
controlled to thirty times the programmed fault
duration (tOFF '" 30 • tFAULT), resulting in an approximate three percent (3%) effective duty cycle
to safely limit power dissipation into a short circuit. Note that the UCC3912 also features internal overtemperature shutdown protection should
the timer be incorrectly programmed for too long
of a fault duration or inadequate heatsinking provided. Consult the UCC3912 datasheet for complete details of the timing and fault protection
circuitry operation into single and repetitive overcurrent conditions.
Circuit Operation
In this paralleled application of UCC3912 devices, a master/slave arrangement will be incorporated and the fault timing control will be
governed entirely by the master. Slave devices
are configured to give a digital representation of
the overcurrent condition, and their individual CT
outputs are "NOR"ed together as an input to the
master. A generic CMOS '4002 digital IC is used
for its low current and 3V operational characteristics. Note that each input requires a 2N2222
NPN signal level transistor with a 10k ohm pull
up resistor from the input supply (VIN) to its collector to complete the interface. This arrangement is necessary to achieve the proper digital
inputs to the NOR gate while clamping the
UCC3912 CT pin voltages to just a base-emitter
diode drop (VBE) above ground. This will override the internal timing circuits of the individual
slaves which are being controlled by the master's fault timer.

In normal operation (prior to any overcurrent
condition) the CT pin of each slave UCC3912 is
low and the corresponding NPN transistor is off.
The 10k ohm collector resistors place a digital
high on the NOR gate's four inputs, and the output of this gate is low. When any of the slave
UCC3912 devices goes into overcurrent protec-

5-107

tion its CT pin is pulled high by an internal current source. Normally, this would start charging
the fault timing capacitor, but in this paralleled
application, it forward biases the base-emitter
junction of the respective 2N2222 transistor. This
turns on the NPN device and forces a digital low
input to the NOR gate. When all four of the NOR
inputs go low, the output of the NOR gate goes
high. This indicates that all four of the slaves are
limiting current to their programmed maximum
level and that an overcurrent condition exists.
The output of this NOR gate is used to digitally
program one bit (BIT2) of the master UCC3912's
overcurrent limit. The master was previously
"off", not providing any load current since it's four
overcurrent inputs (BITs 0 through 3) were all
low. Any digital input below "0100" programs its
output current to zero by turning off the power
switch. But triggered by the overcurrent conditions of the slaves, the NOR gate output
switches BIT2 of the master high. This turns the
master on and programs its output current to
0.25A by the "0100" code at BITS 0 through 3.
The master now allows 0.25 amps in addition to
the slaves 12 amps to the load for a system total
of 12.25A. This is the sum of the master (0.2SA)
and the four slave overcurrent programming
thresholds of three amps each (4 • 3.0A). Provided that the demanded load current is in excess of 12.25 amps, as would be the case with a
short circuited load, the master then provides
two functions. First, it regulates the current
through the master to the programmed 0.25 amp
level. Additionally, it begins a fault timing sequence, the duration of which is programmed by
the value of the fault timing capacitor, CT. This
capacitor charges during the overcurrent condition until it reaches the internal 1.5 volt fault
threshold. Once triggered, the fault latch turns off
the UCC3912's internal MOSFET switch (to provide the circuit breaker function) while also indicating the fault condition by providing a "low" on
the IC's FAULT pin. Note that the master's
FAULT out~ut is connected to the slaved
UCC3912s' SHTDWN pin which turns off all of
the slaved devices at the same time that the
master turns off.

Design Note
The duration of the overcurrent event is programmed entirely by the master's CT timing capacitor value according to the UCC3912
datasheet information and design equations. The
timing circuitry will deliver a current limited,
pulsed mode fault protection and retry with a
three percent (3%) duty cycle. While the timing
capacitor is charging, each IC regulates and
compares its load current to the programmed
fault overcurrent level. Providing that the fault
condition does exist, all UCC3912 ICs are turned
off for the remaining ninety-seven percent (97%)
of the programmed fault timing period. The resulting three percent duty cycle fault mode facilitates safe operation into a continuous overload
or short circuited condition. It safely limits input
power consumption and power dissipation in the
circuit breaker switches. Additionally, no costly
system downtime or manual replacement of a
fuse or resetting of a circuit breaker is required.
Once the abnormal load condition has been removed, the circuit goes back into normal operation. The master's FAULT output returns to a
"high" along with each of the slaves' SHTDWN
inputs. If the load has not been removed, the
master is retriggered by the NOR gate once
each slave has detected an overcurrent condition, and the system goes back to the three percent duty cycle protection mode.
Note that the entire system is nominally triggered
at 12.25A which is programmed by the four
UCC3912 slaves' individual 3A thresholds and
the O.25A contribution of the master. However,
this is unlikely to occur in a typical application
because of two of the device's other ratings.
First, is the· maximum specified "trip" current of
3.5A for each slave switch and 0.45A for the
master with the programmed overcurrent inputs
(Bits 0 - 3). This would raise the highest trigger
threshold to 14.45A. However, the more dominant factor is the high current capability of the
UCC3912's switch which - is rated at four amps
(4A) typical. In fact, each device can safely provide 5.2A (worst case) over all rated temperature
and manufacturing conditions. One possible scenario should be reviewed using an instantaneous
short circuit on the outputs. Even though all of

ON-68
the slaves properly triggered their internal fault
logic at 3.5A (worst case), all four of the slaves
could be delivering as much as 5.2 amps maximum (within the device's ratings) to the load.
This would correspond to a maximum load current of 21.25 amps. And while unlikely to repetitively occur in a typical application, it does
represent the worst case sum of the four
slaves'(4 • 5.2A) plus the master's (O.45A) maximum current ratings. However, it's advised to
evaluate this figure to that of other fault protection and overcurrent techniques, for example
fuses, which can be significantly higher for short
durations. More specific details and comparisons
can be found in Unitrode Application Note U-151.
Other Applications
This design example utilized the UCC3912 device's rated current capability of 3A, but can be
scaled for other applications with higher or lower
requirements. Each slave can be individually
programmed for a maximum current between
O.25A and 3A in O.25A increments using the 4 bit
digital inputs to the fault circuitry. This is beneficial in many low voltage supply applications
which require a low headroom or dropout voltage
(the voltage drop between the input and output
connections of the circuit breaker) to meet the
load's power supply specifications. In these, the
UCC3912's could be paralleled to minimize the
series voltage drop - and not to obtain the higher
current capability of the system. This is one application where it is desirable to program the
slave's overcurrent thresholds toa lower value
than 3A each.

The O.25A example of additional load current
provided by the master can also be raised to deliver higher total system current to accommodate
a transient load condition. Examples of this can
be found in many battery powered energy management systems where only the required active
circuitry is enabled and all others are switched
off. When supplying power to these types of
loads, often high inrush currents are needed to
quickly charge up any local bypassing and filtering capacitors. This brief condition can be accommodated by programming the master
UCC3912's overcurrent bits accordingly.

5-108

Design Note

ON-60

Although switching of only the master
UCC3912's BIT2 is shown, its BIT3 input can
also be switched for higher current capability. Additionally, BITO and BIT1 are shown grounded in
the example circuit but can be programmed or
switched with digital "1 "s as well. Active digital
programming of the master and all slave overcurrent BITs is also possible for the more demanding overcurrent protection applications.
Each UCC3912 Electronic Circuit Breaker IC
also features internal overtemperature protection
with shutdown for complete system protection.

UNITRODE CORPORATION
7 ODNTINENTAL BLVD.• MERRIMACK. NH 03054
TEL. (603) 424-2410. FAX (603) 424-3460

5-109

Additional Reference Material:
[1] UCC3912 Data Sheet

[2] Application Note U-151: "UCC3912 Programmable Electronic Circuit Breaker - Performance
Evaluation and Programming Information"
[3] UCC3912 Evaluation Kit
[4] Design Note ON-58: ·UCC3912 Programmable
Electronic Circuit Breaker - Performance Evaluation and Programming Information"

.~ UNITRODE,

ON-8S

Design Note
UCC3981 USB Power Controller IC, Evaluation Board, Schematic, and List of Materials
By Chuck Melchin
jack. Connect grounds for both supplies to the
demonstration kit ground, Ensure the maximum voltage of 9V is not exceeded on either
theVFIL or VHUB pins.

Introduction
The UCC3981 Power Controller is designed to provide a self powered USB hub with a local 3.3V regulated voltage as well as four SV regulated
voltages for USB ports. The 3.3V linear regulator
is used to provide power to a local USB
microcontroller. The SV outputs are current limited
to SOOmA and the 3.3V output to 100mA in full
compliance with USB specifications.
This demonstration kit provides all the circuitry
necessary to evaluate the performance of the
UCC3981 in a typical application. Each of the SV
outputs, as well as the 3.3V microcontroller voltage, can be individually enabled for optimal port
control. Output enable is accomplished by the use
of a five-position dipswitch and overcurrent signals
are pulled up to the input voltage through 10KO resistors. Both enable and overcurrent Signals are
available at a 10 position in line SIP for easy scope
probe access. The demo kit utilizes an external
NMOS switch in a low dropout linear regulator for
pre-regulating a rough DC voltage, such as a filament voltage, to provide the S.SV input to the four
SV linear regulators.

3.

Connect a voltmeter to the VREG output. The
voltage should read approximately S.SV.

4. Connect the voltmeter to the VSA output. The
output voltage should read approximately OV.
S.

Set the enable switch (ENA) for VSA to the
"on" position. The output voltage should read
approximately SV. The corresponding enable
pin of the 10 position SIP should transition
from a low to a high.

6.

Repeat steps 4 and S for outputs VSB - VSD
and the 3.3V output.

7.

Apply variable resistive loads to all outputs. Increase the loads sequentially to approximately
SOOmA on the SV outputs, and 100mA on the
3.3V output. The appropriate overcurrent flags
on the 10 position SIP should transition from a
high to a low as each output reaches its
overcurrent condition. Reset each load to its
nominal value after observing each output's
overcurrent flag to prevent thermal problems
with the device. The overcurrent flags would
normally signal the USB controller of the
overcurrent condition and the controller would
shut down the appropriate output in an actual
application. The overcurrent flags should return to a logic high once the load is reset to its
nominal value.

This kit can also provide a valid means of evaluating the UCC39811 in a typical application circuit.
The UCC39811 is intended to perform the same
tasks as the UCC3981 with the exception of providing the gate drive and control circuitry for the
S.SV preregulator. The preregulator function can
be bypassed by providing S.SV externally at
VREG, removing Q1 and replacing C09 with a
0.11LF ceramic capacitor. In this case VFIL and
VHUB should also be connected to the S.SV supply
providing DC bias for the 3.3V regulator and the
gate drive for the internal SV regulators.

8.

Reset the enable switch for each output. The
corresponding output voltages should read approximately OV.

9.

Power down the input supplies.

TESTING PROCEDURE
1. Set all enable switches to the "off' position.
SW1 switches 1-4 correspond to outputs
ENA-D respectively. Switch S controls ENHUB.

If the testing procedure is successfully completed
the demonstration kit is verified to be functional
and is ready for more rigorous and application specific evaluation to be performed.

2. Supply a minimum of 6V, maximum of 9V, from
a 2A minimum supply to the VFIL banana jack.
Apply a SV, SOOmA supply to the VHUB banana

For more complete information, pin descriptions and
specifications for the UCC3981 USB power controller IC,
please refer to the UCC3981 data sheet or contact your
Unitrode Field Applications Engineer.

01199
S-110

•

•~

~ri--------------------------------------------------------------------------------------------------

l II
~

~----------r-----rI-=C09:--lHI

~rY2 VFIL

:""

o~~

1~g~F

C10

1~~F

0

1

J04 VREG

J03GND

....

-r

R10
0.0

J04 VHUB

AA
vvv-

CD

i§

I

c:

C01

4.7~F

10V

III

g
tr

@
Q.

~
~

III

~

~

~
b

10k

5

R07
10k

~

J,.

R09

Ros$1Ok

....
I

10k

:::3 I I I I I f~I I I

GATE ~

~

VHUB

VREG

~

OCA

VREG

[I

i

-I

2J

ENA

VSC

25

i ~~.

;11

ENB

VSD

23

JOB 5VD

3m=

1I1I

·

I

261 ENC

VSB

6

~

..L1~:Fl

VREF 1171------,

141 ENHUB

NIC 12BI

GND

GND

GND

GND

~1
20

~_~~D______ ~~_~,O

J06 5VB
J07 5VC

VDRIVE I 1 I

1s1 END

~

I

-'

~ OCD

l!J

TB1
ED7210

UCC3981

~ VFIL

!J

T~~c ••,I~I--+__1--1-~r_------~--+_--~

w~~J

-------------,

I

I

..L C021
001~F

=

I O~!F
=

C05

i

63V1150~F
I
63V..L

J093.3V

C06

150~F I
s 3V
. i..L

1~~:
~
.T
C07

COB

150~F
6.3V

c

~

~

TP10GND.

I

~

0

J10GND

~

~

U1

ON-85
Notes:
1) Absolute Maximum voltage for VHUB is9.0V
2) Absolute Maximum voltage for VFIL is 9.0V
3) VHUB and VFIL can be connected together
4) Pregulator can be bypassed by providing 5.5V at
VREG and VFIL, removing 01 and replacing C09
with a O. 1J.lF Ceramic capacitor.

Reference
Designator
R01-R09
R10, R11
TB1
SW1
C01
C02 C03
C04-C08
C09 C10
J01-J10
U1
01

5)

ENABLE and OVERCURRENT signals are pulled
up to VHUB. Qjumpers R10and R11 can be removed to wire pullups to a different voltage
Capacitors C04 through C10 can be replaced with
size "0" Tantalum SMO capacitors.
Capacitor C01 can be replaced with size "B" Tantalum SMO capacitors.

a

6)
7)

Description
10k, 5%, 1/8W, Metai Film Resistor
O.OW 5% Jumper Metal Film Resistor
Pin Header, 10 position
DIP Switch, 5 Position, SPST
4.7uF, 10V, Tantalum Capacitor
O.01uF Z5U Ceramic Capacitor
150!1F, 6.3V, Electrolytic Capacitor
100uF 10V, Electrolvtic Capacitor
Binding Post
USB Power Controller IC
60V 17A, N-Channel MOSFET

Manufacturer

Mill-Max
AMP

ED721 0
A5205

Unitrode
International Rectifier

UCC3981
IRFZ24

Table 1. UCC3981 evaluation board list of materials.
Note: UCC3981 is also the UCC3831. UCC39811 was formerly UCC38531.

UNITRODE CORPORATION
7 CONTINENTAL BLVD.' MERRIMACK, NH 03054
TEL. (603) 424·2410' FAX (603) 424·3460

Part Number

~UNITRODE

DN-87

Design Note

.

UCC3918 "Low On-Resistance Hot Swap Power Manager", Evaluation Board, Schematic,
and List of Materials
By Dave Olson
INTRODUCTION

ABSOLUTE MAXIMUM RATINGS

The UCC3918 evaluation kit allows the designer to
evaluate the performance of the UCC3918 Low
On-Resistance Hot Swap Power Manager in a typical application circuit. The schematic for the evaluation kit is shown in Figure 1.

Input Supply Voltage ......................... BV
SOIC Power Dissipation ..................... 2.5W
Fault Output Sink Current. .................. 50mA
Fault Output Voltage ......................... VIN
Output Current (DC) .............. Internally Limited
TTL Input Voltage .....................--D.3V to VIN

FEATURES

Functions of SW1, SW2 and SW3

• Integrated 0.06n Power MOSFET
• 3V to 6V Operation
• External Analog Control of Fault Current
OA to 4A
• Independent Analog Control of Current Limit
up to 5A
• Overload Protection
• 1!lA ICC when Disabled
• Programmable On Time
• Programmable Start Delay
• Fixed 3% Duty Cycle During Fault Conditions

SW1 and SW2 provide the designer with the flexibility of evaluating the performance of the
UCC3918 when residing on either the system
backplane or on an adapter card. Closing SW1
after SW2 simulates an application where the
UCC3918 resides on a plug-in adapter card.
Closing SW1 prior to SW2 simulates an application
where the UCC3918 resides on the system
backplane.
SW3 provides a shutdown input to
disable the IC.

TB2

+ ;-;TBl
SW1

-@
Y'N

=

OPTIONAL SOURCING
DELAY COMPONENTS

UOG-98046

Figure 1. UCC3918 Evaluation Board Schematic

03199
5-113

DN-87
Calculating Maximum Sourcing Current (IMAX)
The maximum sourcing current is programmed by
selection of R3; connected from pin 9 (IMAX) to
GND. R3 can be calculated as:

R3 = 126k Q
I MAX

For a constant current load, the maximum capacitance can be estimated from:

GOUT =
(I MAX -I LOAD) • [

(1)

For the UCC3918 evaluation kit R3 is set to
42.2kQ for IMAX = 3A typical. Please refer to the
UCC3918 data sheet for further discussion of IMAX.

27.8X10 3 •
VOUT

C2] Farads.

For a resistive load of value RL, COUT can be
mated from:

GOUT = .

27'8[xlO'

:C2

Calculating the Fault Current (IFAULT)
The IFAULT pin allows linear programming of the
fault level current from 0 to SA. When operating below the fault current the internal FET will be fully
enhanced providing lowon resistance. When output currents exceed IFAULT the output remains on
but the fault timer starts charging CT. R2 sets the
current fault level. R2 can be calculated as:

(2)

R2= 105k Q
IFAULT

For the UCC3918 evaluation kit R2 is set to
52.3kQ for IFAULT= 2A typical.
Calculating the Fault and Shutdown Times
The UCC3918 evaluation kit incorporates a 0.1 J.lF
timing capacitor, C2 (CT) to set the fault time. The
fault and shutdown times can be found by using
the following equations.

TFAULT =27.8keG2
TSHUTDOWN

=0.833X10 6

(3)

.G2

(4)

Where C2 is in Farads and T is in Seconds.
For the evaluation board TFAULT = 2.78mSec and
TSHUTDOWN=83.3mSec.

1Farads

(5)

esti~

(6)

v:

RL.£n
1-

OUT
I MAx .RL

SAFETY RECCOMMENDATIONS
Although the UCC3918 is designed to provide system protection for all fault conditions, all integrated
circuits can ultimately fail short. For this reason, if
the UCC3918 is intended for use in safety critical
applications where UL or some other safety
agency rating is required, a redundant safety device such as a fuse should be placed in series with
the power MOSFET device. The UCC3918 will prevent the fuse from blowing for virtually all fault conditions, increasing system reliability and reducing
maintenance cost, in addition to providing the hot
swap benefits of the device.
Note: Capacitor C1 is located on the component side of
the input switch and will contribute to the inrush current.
For more complete information, pin descriptions and
specifications for the UCC3918 Low On-Resistance Hot
Swap Power Manager, please refer to the UCC3918
data sheet or contact your Unitrode Field Applications
Engineer at (603) 424-2410.

Estimating Maximum Load CapaCitance
The maximum load capacitance that can be
charged depends on several factors; the nature of
the load (constant current or resistive), the maximum sourcing current, and the allowed fault time.

5-114

DN-87
Reference
Designator
C1
C2
C3
C4
C5
01
R1
R2
R3
R4
R5
SW1
SW2
SW3
TB1
TB2
U1

Description

Manufacturer

22uF, 25V Tantalum Capacitor
O.1I-1F, 50V Ceramic Capacitor
221-1F, 25V Tantalum Capacitor
Not Populated
Not Populated
LED
300n, O.25W Resistor
52.3kn, O.25W Resistor
42.2kn, O.25W Resistor
Not Populated
10kn, O.25W Resistor
Slide Switch
Slide Switch
Dip Switch
Terminal Block
Terminal Block
Low On-Resistance Hot Swap Power Manager

Table 1. UCC3918 Evaluation board list of materials.

UNITRODE CORPORATION
7 CONTINENTAL BLVD.· MERRIMACK. NH 03054
TEL. (603) 424-2410· FAX (603) 424·3460

5-115

Part Number

Sprague

199D226X0025DA 1

Sprague

199D226X0025DA 1

Unitrode

UCC3918

Unitrode Corporation

Design Note 0-95

Design Note
UCC3919 Hot Swap Power Manager Evaluation Circuit and List of Materials
By Robert B. Diener

INTRODUCTION
The UCC3919 evaluation board is designed to allow the user to fully test the capabilities of the
UCC3919 Hot Swap Power Manager.
Overcurrent protection circuitry can be added to either a
plug in adapter card that is being hot swapped or
to the backplane circuit itself. This circuit can be
used to test the capabilities of the UCC3919 Hot
Swap Power Manager for either application.

EVALUATION BOARD FEATURES
•
•
•
•
•
•

3V to 8V operation
Fault current threshold of 5A
Maximum output current of 7A during fault
Overload shutdown (Electronic Circuit Breaker)
On-board fault indicator
On-board N-channel MOSFET with 0.0110

CONTROL SWITCHES
The UCC3919 Hot Swap Power Manager
Evaluation Circuit has several switches enabling
the user to evaluate its operation in different configurations.
SW1 and SW2 can be used to mimic the connections between a back plane and a plug in adapter
card. The order of operation for these switches will
determine whether the protection circuitry is located on the plug in adapter card or on the backplane. By closing SW1 prior to SW2, the circuit will

RDS(on)

VIN

• On-board 0.010, 1Wsense resistor
• Choice of manual or automatic reset modes
• Choice of 3% duty cycle current limiting or
average power limiting during fault
• Shutdown function
• Optional provision for soft-start delay

SW1

I---ucc~wpw----i
1

IMAX

CSP

VDD
TP2

CSN
I

TP13

J

-=-

GND~
GATE

I

PL
TP6
R3
1000

o

~ D1
L--'lf\I'v--+l----.,.--j

I

I

I

8

FLT
U1

Q2J
CT ~
Y

~--------------"

TP8
·OPTIONAL COMPONENT

VOUT

SW2

SW3POWER
LIMIT
"'<>--'\fV\r-+U TP17

~
11

N/C

N/C

TP12

~f---'i*---,!--+-...,...,,-.
TP11

TP9

J~CT

lo.Q1~F

I I
UDG-98197

Figure 1. Schematic diagram.
11/98
5-116

Unitrode Corporation

Design Note DN-95

simulate a situation where the protection circuitry is
located on the back plane. Closing SW2 prior to
SW1 simulates a situation where the protection circuitry is located on the adapter card that is being
hot swapped.
SW3 controls the Power Limit function. In the PLiM
position, the PL pin is connected to the output via a
10k resistor. During a fault condition, as the input
voltage is increased the duty cycle will decrease
and the average power will be held relatively constant. In the HCCP position, a fault condition will
cause the output to be limited to a 3% duty cycle
independent of input voltage.
SW4 controls the shutdown pin. In the SD position
the UCC3919 will be put into a low current standby
mode and the external MOSFET will be turned off.
SW5 controls the UR pin. While in the LATCH position, a detection of a fault condition will cause the
external MOSFET to be turned off and remain off
until SW5 is set to the RESET position or the
power is cycled. With SW5 in the RESET pOSition,
a fault condition will cause the circuit to be in hiccup mode until the output current falls below
IFAULT.

CURRENT THRESHOLDS
IFAULT is the output current threshold that starts the
fault timer. For this circuit, IFAULT has been set to
5A. The fault timer will run until either the output
current falls below IFAULT or until it times out. If
the fault timer times out, the external MOSFET will
turn off and the circuit will enter a fault condition.
IMAX is the maximum output current the circuit will
supply. For this circuit IMAX has been set to 7A.
During a fault, if SW5 is in RESET mode the output
will be duty cycle limited and the current supplied
during TON will be limited to IMAX. If IMAX is set below IFAULT, the external MOSFET will be in a high
power dissipation mode limiting the output current
to IMAX and the circuit will never enter a fault condition.
IOVERLOAD is the threshold that will activate the circuit breaker function. For this circuit IOVERLOAD has
been set to 27A. This threshold could be reached if
the circuit is already powered up and a heavy load
or a direct short is applied to the output. In this
case the overload comparator will take over, the
external MOSFET will turn off immediately, and the
fault timer will be started.

OPERATION
Fault Timer
During normal operation the external MOSFET is
fully on and current is supplied to the output. If the
output current rises above IFAULT, the fault timer
will be started. IFAULT is calculated as:

0.05V

IFAULT = - - RSENSE

(1)

The fault timer is controlled by the CT capacitor.
When the fault timer is started, the CT capacitor
will charge up to 1.5V as long as the output current
is above IFAULT. If the voltage across CT reaches
1.5V the external MOSFET will turn off and the circuit will enter a fault condition. The time required
for CT to charge from OV to 1.5V is referred to as
TON (IN IT)· With SW3 in the HCCP position,
TON (INIT) for this circuit is approximately 430IlS.
TON (INIT) is calculated as:

CT(1l F) -1.5
351lA+lpL

TON UNIT) (sec) = ----"-~--,---

(2)

If SW5 is in the LATCH position, the output will
stay off until switched back to RESET or the power
is cycled. If SW5 is in the RESET position the CT
capacitor will then discharge to 0.5V at which point
the external MOSFET will turn back on. If the output current is above IFAULT, the process will repeat
with the external MOSFET on during the charge
time of the CT capacitor and the external MOSFET
off during the discharge time of the CT capacitor.
The charge and discharge times are referred to as
TON and TOFF respectively. With SW3 in the HCCP
pOSition, TON and T OFF are calculated as:

T.ON (sec )

CT (Il F )
351lA+lpL

(3)

(4)

IpL will be zero if SW3 is set to HCCP. If the circuit
enters a fault condition with SW3 set to HCCP, the
output current will be duty cycle limited to 3%. For
this circuit, TON =280llS and TOFF =8.3ms.
If the circuit is in fault and SW3 is set to PLiM the
circuit will be in the power limit mode. In this mode
IpL is calculated as:

5-117

(5)

Unitrode Corporation

Design Note DN-95

VPL is measured with respect to the CSP pin as
listed in the UCC3919 data sheet.

With VIN=5V and an output current of 3.3A, the
maximum value of COUT is approximately 71JlF.

While in power limit mode, as the input voltage is
increased, the duty cycle of the output will decrease, thus keeping the power dissipation relatively constant. For this circuit, with VIN=5V and
the output shorted, IpL will be approximately
320~. The circuit will have T ON=25Jls for an average power dissipation of approximately 68mW. If
the input voltage is raised to 8v, TON will decrease
to 14Jls and the average power dissipation will be
approximately 57mW. T OFF will remain the same
independent of SW3.

IMAX
Once the output current has risen above IFAULT,
the internal linear amplifier will limit this current to a
maximum of IMAX. IMAX is determined as:

1.5V-R1
'MAX

(8)

(R1 + R2) - RSENSE

If IMAX is set to a level lower than IFAULT, the
UCC3919 will limit the output current to a maximum of IMAX' while never entering a fault condition. This leaves the external MOSFET in a high
power dissipation region.

Timing Capacitor
The CT capacitor must be selected to ensure that
the UCC3919 will not enter fault mode during the
initial start-up or when recovering from a fault in
the hiccup mode. The selection of CT is dependent
upon the type of load and the size of the load capacitor. If CT is too small or COUT is too large, the
CT capacitor will charge up to 1.5V and the circuit
will enter a fault mode before COUT is allowed to
fully charge. Refer to the UCC3919 data sheet
when changing the value of the CT capacitor.

'OVERLOAD

With the circuit powered up, a heavy load or a direct short suddenly applied to the output will cause
the output current to spike. If this current reaches
IOVERLOAD, the external MOSFET will immediately
turn off and the fault timer will start. IOVEROAD is
calculated as:
'OVERLOAD = 'MAX

For this circuit, the CT capacitor has been selected
to be O.01JlF. When operating in the hiccup mode
with a duty cycle of 3%, COUT (MAX) is shown in
Equation (6).

O.2V
+-R-SENSE

(9)

This .condition occurs only if SW2 is closed after
SW1. For cases where SW2 is closed before SW1 ,
an optional capacitor, CSS can be added to the circuit to provide for a soft start. In .this case CSS will
limit the slew rate of the output current

where ICH' the charging current of the CT capacitor
is approximately 35JlA. With VIN=5V and an output
current of 3.3A, the maximum value for COUT is
approximately 290JlF.

If the circuit is operating in a noisy environment, an
optional capacitor, CBIAS can be added to bypass
the internal 1.5V bias generator. CBIAS should be
limited to a maximum of O.001JlF.

When operating in the power limit mode, the maximum value for COUT can be calculated in Equation (7).

CT

(6)

COUT(MAX)=------~(~--~-IN--~)
'CH -RL-.e n 1----=-:'MAX -RL

COUT (MAX) =

(7)

CT
[ (VIN -Vpd2 +'CH]-[-RL-.e
2- RpL - V/N

J 1-

"l

5-118

V/N
'MAX -

)]
RL

Unitrode Corporation

Design Note DN-95
Table I: List of Materials

Designator
C1, C2
CBIAS
CINA, CINB
COUTA
COUTB
CSS
CT
01
R1
R2
R3
RPL
RSENSE
SW1, SW2
SW3, SW4, SW5
TB1, TB2
U1
U2

Description
0.1J.!F, Ceramic capacitor, 1206 SMD
'optional
100J.!F, 16V, Tantalum capacitor, 7343 SMD
101lF, 20V, Tantalum capacitor, 3528 SMD
'optional
'optional
0.01uF, Ceramic capacitor, 1206 SMD
LED, red, 1206 SMD
5k, Metal film resistor, 1206 SMD
100k, Metal film resistor, 1206 SMD
1500, Metal film resistor, 1206 SMD
10k, Metal film resistor, 1206 SMD
0.010, 1W, Metal film resistor, 2512 SMD
Riahl. anale, SPOT slide switch
Miniature SPOT slide switch
Terminal block
Hot Swap Power Manaaer
N-channel MOSFET

SAFETY RECOMMENDATIONS
The UCC3919 is designed to provide protection
against over current situations, but since semiconductors can ultimately fail short, this circuit may require a fuse or electro-mechanical circuit breaker in
series as back-up protection.

Manufacturer/Dist.
Digikey

Part Number
PCC104BCT-ND

AVX
AVX

TAJD107M016
TAJB106K020

Diaikev
Digikey
Digikey
Diaikev
Digikey
Diaikev
IRC
Djgikey_
Newark
Mouser
Unitrode
International Rectifier

PCC103BCT·ND
LU60351CT·ND
P4.99KFCT·ND
P100KFCT·ND
P150FCT·ND
P10.0KFCT-ND
LR2512-01-FTR
CKN5006
52F516 switch
506·2SV·02
UCC3919PW
IRF7413

For complete details about the operation of the
UCC3919 Hot Swap Power Manager, please refer to
the UCC3919 Data Sheet and UCC3919 Hot Swap
Power Manager Application Note.

UNITRODE CORPORATION
7 CONTINENTAL BLVO.' MERRIMACK. NH 03054
TEL. (603) 424-2410' FAX (603) 424-3460

5-119

~UNITRODE

DN-98

Design Note
UCC3917 Positive Floating Hot Swap Power Manager Evaluation Kit, Schematic and List
of Materials
By Dave Olson

INTRODUCTION

UCC3917 Features

The UCC3917 evaluation kit allows the designer to
evaluate the performance of the UCC3917 Positive
Floating Hot Swap Power Manager (HSPM) in a
typical application setting. Component selection for
the UCC3917 Evaluation Kit is for operation at
28Vdc, 1A. Operation at other voltages/currents
may be accomplished by proper component selection and replacement. The schematic for the evaluation kit is shown in Fig. 1. The Bill of Materials
with component ratings is specified in Table 1.

•
•
•
•
•
•
•
•
•
•
•

Programmable Linear Current Control
Programmable Overcurrent Limit
Precision Fault Threshold
Internal Charge Pump for Driving External
NMOS Device
Programmable Average Power Limiting
Fault Output
Programmable Fault Mode - Latch or Retry
Programmable Fault Timer
Shutdown Control
Undervoltage Lockout
No maximum voltage limitation

VIN

TBl

ll+
SW1

C2

Cl

Dl

R3

1_~~_~_~_1r--3~
___ ,

:
I

~

C2N

__

C2P

C1N

C1P

VDD

I

I

H-~IVIr---4

FLOUT

I

j
SW3-1

rr~=- ~,

01

R7

I
I

I

SW3-2 :

~--- 9 - - - - -

UDG-980S1

Figure 1. UCC3917 evaluation kit schematic 28v/1A.

04199

5-120

ON-98

Switch Functions

where

SW1: Switch SW1 allows the designer to evaluate
the performance of the UCC3917 when residing on
an adapter card. Closing SW1 after input power is
applied to the board simulates hot insertion into a
backplane.
SW2: Omitted
SW3: Switch SW3-1 controls the SHTDWN pin of
the UCC3917. In the OFF position, the switch pulls
the SHTDWN pin to VOUT. In the ON position, the
SHTDWN pin is left open. SW3-2 is used to program the fault-handling mode of the UCC3917. In
the OFF position, the LATCH pin will be pulled low
to VOUT, placing the UCC3917 in the latch mode
of operation during a fault. In the ON position,
SW3-2 allows LATCH to float high, thus putting the
UCC3917 in the hiccup mode during a fault condition.

Programming the Maximum Sourcing Current
Pin, MAXI
The maximum sourcing current level, the current
level at which the output looks like a constant current source, is equal to the voltage at the MAXI pin
divided by the sense resistor R7. MAXI is derived
using a voltage divider from the internally regulated
voltage VREF/CATFLT to VOUT. If desired, placing a capacitor on MAXI with respect to VOUT can
program a controlled current slew rate (soft start).
The evaluation kit is designed for a maximum sourcing current of 2A. Please see the Bill of Materials
for respective resistor values. There is also a spare
footprint for an optional soft start capacitor. The
maximum sourcing capability is defined by:

(1 )

VREF

voltage at VREF/CATFLT

R1 = Resistance from VREF/CATFLT to MAXI
(Q)
R2 = Resistance from MAXI to VOUT (Q)

Programming the Fault Timer
The fault timer starts when the load current increases beyond the fault current, IFAULT, threshold.
The IFAULT threshold is defined as:
'FAULT

50mV
=-----m-

IFAULT =The fault current threshold (A)
R7

=The sense resistor value (Q)

The fault current threshold for the UCC3917 evaluation board is set for 1A (R7 = O.05Q). Once the
load current increases beyond the fault current
threshold, the fault timer starts. The fault timer consists of a internal constant current source charging
an external cap C4. Once the voltage on C4
reaches the 2.5V, an internal comparator trips and
signals a fault condition. The gate drive to the extemal FET is disabled and the IC either latches off
or enters its hiccup mode of operation (refer to the
Switch Functions section for more details on programming latch mode versus hiccup mode). The
internal current source charges C4 at a nominal
rate of 50p.A. C4 must be selected to allow enough
time for the output capacitance to charge. The fault
time, the time required to charge C4 to the fault
comparator's threshold, is defined as:
C4 -LlV
TFAULT

R7 = sense resistor (Q)

(3)

where

where
IMAX = maximum sourcing current desired (A)

(4)

where

VMAXI = voltage at MAXI with respect to VOUT

(V)
The voltage at MAXI with respect to VOUT is defined by:

R2
VMAX1 =----VREF
R2+R1

= Regulated

(V)

(2)

TFAULT = time required to charge C4 to the
fault threshold (sec)

=the external capacitor on the CT pin (F)
LlV = the fault comparator threshold (2.5V for
C4

latch mode: 2.0V for hiccup mode)
ICH =internal charge current (A)

5-121

DN-98
The rate at which the total output capacitance can
be charged is dependent on the maximum output
current' available and the nature of the load. The
fault time, TFAULT, must be greater than the time
required to charge any load capacitance. Please
refer to the UCC3917 data sheet, Selecting Minimum Timing Capacitance, for more detailed information.

Programming the Average Power Dissipation of
the External FET, PLIM
During the hiccup mode of operation, mentioned in
the previous section on programming the fault
timer, it is necessary to limit the average power
dissipated in the external MOSFET. The hiccup
mode of operation typically retries the output at a
3% duty cycle. The MOSFET will be turned on for
the duration of the programmed fault time and if
the fault is still present will shut down for an extended period of time. The duty cycle is defined as:

DutyCycle=
,

1.S~

(S)

IpL +SO~

PFET(avg) =IMAX .1.S~.R6

R6 =

PFET(avg)

The UCC3917 evaluation board is populated with
R6=200K. The average power dissipated in the
FET, PFET(avg), during a fault condition should be
-0.3W. 'Please refer to the UCC3917 for more detailed information on R6 and controlling PFET(avg).

Selection 'Criteria for Other External Components
Because the UCC3917 derives its own operating
voltage through a charge pump supplied by 100, it
is necessary for 100 to provide -SmA 6f current to
keep the charge pump' operating. During startup,
this current will be provided by input (VIN) through
R3, but once the IC is up and running on its own,
100 is supplied by the output (VOUT). The current
is returned through RS. Therefore, R3 and RS can
be determined by:

R3=V1N -10V g

(9)

SmA

1.StJA = CT discharge current

RS= V 1N -SV g
SmA

IPL = charge current provided by R6 (A)
Under normal operatio)'l IpL=O, however, even operation at 3% duty cycle can result in substantial
power dissipation in the external MOSFET. The
power dissipated in the MOSFET is defined as:

DutyCycle W

(6)

where
VFET = the voltage
VINV-oUT, (V)

(8)

'MAX .1.S~

SOtJA = CT charging current

•

(7)

or, solving ,for R6,

where,

PD1SS = VFET .1MAX

W

(10)

For applications that require wide input ranges it
may be difficult to size R3 and RS to provide adequate current over the whole operating range. For
the wide input ranges, R3 and RS can be replaced
with constant current regulator diodes (1 NS314).
Please Note: 100 should not be allowed to ex-

ceed10mA.
across

the'

FET,

IMAX = the maximum sourcing current (A)
DutyCycle = operating duty cycle
The average power dissipation in the FET when incorporating the power limit function is defined as:

Extemallnput Capacitors: Excess source impedance may adversely affect operation of the Linear
Current Amplifier control loop, resulting in oscillation when operating at the maximum sourcing current. Decoupling the evaluation board's input from
the source impedance using low ESR tantalum or
aluminum electrolytic capacitors can eliminate this
oscillation. The capacitors should be placed at the
input connector of the board.

S-122

ON-98
Table 1. UCC3917 evaluation kit bill of materials.
Designator

Description

C1, C2, C3, CS X7R Ceramic, 1206
C4
Tantalum, SOY, Case El1206
Case El1206 Dual Footprint
C6
D1
100V, 1A Rectifier
Q1
IRFS30NS
R1
0.1W, 1%, 080S
R2
0.1W, 1%, 080S
0.2SW, S%, 1210
R3
RS
0.2SW, S%, 1210
0.1W, 1%, 080S
R6
1W 1%,2S12
R7
SW1
Slide Switch
Dip Switch 2 pos
SW3
Terminal Block, 2 pole
TB1,TB2
HSPM, SOIC-16
U1

Part Value
0.1uF
1.0uF

1001<0
2.01<0
3.61<0
4.71<0
2001<0
O.OSO
28Vdc,3A

Safety Considerations

Although the UCC3917 is designed to provide system protection for all fault conditions, all integrated
circuits can ultimately fail short. For this reason, if
the UCC3917 is intended for use in safety critical
applications where UL or some other safety
agency requires a redundant safety device such as

Manufacturer

Part Number

Panasonic/Diai-Kev
Spraaue

PCC104BCT-ND
194D10SXOOSOE2
Provisional
DL4002DICT-ND
IRFS30NS
P100KDCT-ND
P2.0KDCT-ND
P3.6KVCT-ND
P4.7KVCT-ND
P200KDCT-ND
01 F1SS1
CKNS006-ND
CKN3001-ND
S06-2SV-02
UCC3917D

Diai-Kev
IR/Newark
Panasonic/Diai-kev
Panasonic/Diai-kev
PanasoniclDigi-key
Panasonic/Diai-kev
Panasonic/Diai-key
DaleINewark
C&KlDiai-kev
C&KlDigi-key
AUGAT/RDI/Mouser
Unitrode

a fuse, it should be placed in series with the power
MOSFET device. In addition to providing the hot
swap benefits of the device, the UCC3917 will prevent the fuse from blowing for virtually all fault conditions increasing system reliability and reducing
maintenance cost.
For further information, consult the UCC3917 Data
Sheet or contact a local Unitrode Representative or
Field Applications Engineer at (603) 424-2410.

UNITRODE CORPORATION

7 CONTINENTAL BLVD.' MERRIMACK, NH 03054
TEL. (603) 424-2410. FAX (603) 424·3460

5-123

APPLICATION NOTE U-1S1

UNITRODE CORPORATION

UCC3912 INTEGRATED ELECTRONIC CIRCUIT BREAKER IC FOR HOT-SWAp·
AND POWER MANAGEMENT APPLICATIONS
by Dave Zendzian
Applications Engineer

ABSTRACT
This application note describes the design and performance characteristics of the UCC3912 Electronic Circuit Breaker. The practical aspects of applying the circuit breaker are disclissed as well as its performance
compared to existing technologies. The UCC3912 integrates a power MOSFET with all of the necessary
control and housekeeping functions including current limiting, short circuit protection, and auto recovery
capabilities. The performance of the circuit breaker is compared to PolySwitcheS® and conventional fuses
in both hot swap and short circuit applications.

INTRODUCTION
1000%

Today's design engineers are faced with a variety
of choices when selecting protection devices to
meet their circuit or system's design requirements.
Fuses, positive temperature coefficient (PTC) resistors, and electromechanical circuit breakers represent only a sampling of the technologies
available to meet their needs. Each of these devices provides a different degree of security, ranging from simple short circuit protection to devices
which offer active current limiting and remotely resettable operation.
Fuses, while providing an inexpensive solution, fall
short of many of the protection requirements imposed on modern electronic equipment. Figure 1
illustrates the protection capability of two general
fuse categories; fast-acting and slow-blow. Although both devices provide gross short circuit protection, even the fastest devices react on the order
of milliseconds, passing currents up to 500% of
their rated value. In addition, fuses, by their very
nature, have to be physically replaced following an
overload condition. This increases the equipment's
down time along with the chance of an incorrect
device being installed, thereby reducing overall
system reliability.

-

1:

1

~::J

Slow-Blow Fuse

CJ

Ia:

\

k

"0

.

1:

I!

,/

.!!

100%
0.01

FITi~irrli

r-

"-

0.1

10

100

1000

Tlmefsecl

Figure 1. Relation of Percent of Rated Current to Fuse
Blowing Time.

10000%

1:

~

CJ

Ia:

1000%

"0
1:

PTC resistors, on the other hand, eliminate the
need for human intervention by providing resettable
overcurrent protection. However, because they are
actuated by the heating effect of an overcurrent
load, their reaction time is limited to several milliseconds. This results in output currents several
times their steady state rating. Figure 2 illustrates
typical "time to trip" data for polymeric PTC resistors.

"

"

I!

:.

I'-100%
0.1

10

100

1000

Time to Trip (sec)

Figure 2. Relation of Percent of Rated Current to BlowingTime.
.'

5-124

U-1S1

APPLICATION NOTE
The UCC3912 Electronic Circuit Breaker offers a
new, integrated solution to the problem of circuit
protection and power management. Each of the
drawbacks associated with existing technologies
are addressed in the UCC3912 design. In addition,
the UCC3912 provides logic level load control for
power management applications. This note describes the features and performance of the
UCC3912 as compared to other available protection techniques. In particular, hot swap, power
management, and short circuit protection applications are addressed in detail.

The potential for glitching the power bus exists
whenever an unpowered module is inserted into an
operational system. Virtually all modules possess
some amount of onboard bus capacitance which
serves to filter and maintain power quality once the
board becomes operational. However, these very
same capaCitors require an initial charging current
in order to bring their voltage up to the same level
as the system's power supply. The only factors limiting the magnitude of this current is the equivalent
series resistance (ESR) of the capacitors themselves and the impedance of the interconnect between the module and the rest of the system.
Unfortunately, the better the capacitors are at serving their purpose of filtering the bus, the lower their
ESR. As a result, the initial inrush current during
the hot swap can become excessively high.

HOT SWAPPING

The term hot swap refers to the system requirement that submodules be swapped out upon failure
or system modification without removing power to
the hardware. Design of modern computer systems, disk arrays, network hubs and communication switches require modules to be hot swapped
while maintaining the integrity of the powered and
operating system. This requirement allows the
hardware to maintain operation, increasing the system's performance and reliability.

Figure 3 illustrates the inrush current and corresponding voltage glitch when a load of 2A and
120llF is switched onto a 5V power bus. The 120llF
of load capacitance consisted of a solid tantalum,
surface
mount
style
capaCitor
(Sprague
#595D127X9020R2T) with a typical ESR of O.25Q
at 100kHz. The power bus was bypassed with
240llF of the same style capacitor, As the figure illustrates, the inrush current reaches a maximum
value of approximately 27A, resulting in a 1V glitch
on the power bus. This exceeds the 4.5V limit by
500mV causing the supply to drop to 4.0V! In addition to causing the voltage glitch, the excessive inrush current can also result in arcing between
connector pins and excessive heating of the load
capacitance. Each of these effects shortens the life
of the component, ultimately reducing system reliability.

Implementing the hot swap requirement imposes
several design constraints upon the equipment's
power system. In order for the hardware to maintain error free operation during the installation or
removal of a submodule, the 5 volt power bus must
not drop below a minimum voltage of 4.5V. Voltages below 4.5V can disrupt logic levels, causing
an indeterminate number of failures including data
corruption and logic lockups. This ultimately reduces system reliability and data integrity.

Tek Stop: Single Seq 1.00MS/s

INPUT VOLTAGE
500mvIDIV
(AC COUPLED)

[TI~I=ctIJ-=-J~J
'I! i
'I

I

I i '

I

I

.

I

i

!,

I l'
f----: - -~--+---t---t------- !----- i-----------

i

i',

---r---- - - -~- --~

+
--+--

L_--Ji - J-----L--J-L
. ""J.-.1--__
!
!
! ""L __ ""J,"" ""--l
I!
i
i
!
I
1i --- ----r-r'
1------I----r--I'--r-"--l
j

i

I

----T --+--tI

OUTPUT CURRENT
10A1DIV

,

i

!

!

I .

~

i

i

-~I'---r--r---~
,

I

-"",---1",---", i-"'-" i'-----t---T ----r-""---t----l---""1
j
i l __L_ L___J

L....L_J ____i.._. _L

t=5O~seC/DIV

Figure 3. Inrush Current and Corresponding Voltage Glitch for a 2A, 120llF Load.

5-125

APPLICATION NOTE

U-1S1

r--------------------------------------------,
I
I
I

VIN
H=4A

Power

Max Current

Fet

Level

Over Current

Comparator

---~11--16
B3 B2 Bl

BO

4 BIT DAC

GND Hes tsink
GND Pins

CT

F AUL T
UDG-93021-4

Figure 4. UCC3912 Electronic Circuit Breaker Block Diagram
THE UCC3912 ELECTRONIC CIRCUIT
BREAKER

In its most rudimentary form, a circuit breaker,
whether electromechanical or electronic, protects a
circuit from excessive current flow. Electromechanical devices accomplish this by opening a set of
contacts when the current exceeds a specified
level. These types of breakers usually latch off during a fault and therefore need to be manually reset
once the current falls below a reasonable value. An
electronic circuit breaker, on the other hand, provides protection through the use of a power transistor. By monitoring the output current through a
current shunt, the transistor can be biased "on" or
"off" based upon whether or not a predetermined
trip current has been exceeded.
The UCC3912 is an electronic circuit breaker IC
designed to provide power management and hot
swap capability in addition to its basic circuit
breaker function. Performance features of the
UCC3912 include:
•
•
•
•

Integrated 0.150 power MOSFET
Switchmode short circuit protection
Automatic short circuit recovery
Digitally programmable 4-bit maximum current limit
• Unidirectional current flow
• SMT power package
• Fault indicator output

• Low power "sleep" mode
• Thermal shutdown
• Low part count implementation
The block diagram of the UCC3912 is shown in
Figure 4. Under normal operating conditions the integrated N-channel MOSFET is biased "on" using
the internal charge pump to drive the gate. Output
current is sensed using a mirrored MOSFET and is
compared to an adjustable trip level set by the 4-bit
DAC input. When the output current exceeds the
trip level, the fault timer begins to charge the timing
capacitor, CT, with a current of 36J.IA. If the output
current does not fall below the trip level by the time
the capacitor charges to 1.5V, the output is
switched off and the capacitor is discharged with a
current of 1.2J.IA. Once the capacitor's voltage has
reached 500mV, the circuit breaker attempts to return power to the load. At this pOint the timer cycle
will repeat as long as the fault is present, resulting
in an output duty cycle of 3%.
Figure 5 illustrates the cyclical retry of the
UCC3912 under fault conditions. Note that the initial fault time is longer than subsequent cycles due
to the fact that the capacitor is completely discharged and must initially charge to the reset
threshold of 0.5V. If at any time the output current
reaches IMAX, the MOSFET transitions into linear
mode, providing constant output current until the
fault time expires. The discrete IMAX input is used
to set the maximum output current to either a fixed

5-126

U-1S1

APPLICATION NOTE

will then repeat, preventing the output from turning
on.

Overload
Output
Current

I
I

10 (nom)1

flJL

IMAX
IFAULT I'i
,!

I

::

I

II'

.

'#1
i

I:

I

,:

i

I

1

!

i

i~.5V
VOlt~ge!
I
'.
c

To determine the minimum fault time, assume a
maximum load current just less than the trip limit.
This leaves the difference between the IMAX and
ITRIP values as the current available to charge the
output capacitance. The minimum required fault
time can then be calculated as follows:

.0.5V

I
I

!

,

I

Va (nom)1

.

I

Output Rol ICL
Voltage I

i

~
,
~

(2)

i

iii
I

I
I

I

H

s-J

Jli
I

The minimum timing capacitor can be calculated by
substituting equation (1) for tFAULT in equation (2)
and solving for CT.

i

,

~

ITON 130ToN I

(3)

Figure 5. Load Current, Timing Capacitor Voltage and
Output Voltage of the UCC3912 under Fault
Conditions.
value of 4A, (logic level high), or to a value 1A
above the trip current as set by the DAC inputs,
(logic level low). The 4 bit DAC allows the fault current level to be programmed from to 3A in 250mA
increments.

°

Fault time duration is controlled by the value of the
timing capacitor, CT, according to the following
equation:
tFAULT = CT. Bv = CT • _1_.5_-_0,-._5
I
36E-6
= 27.8E3 • CT

(1 )

Figure 6 provides a plot of fault time vs timing capacitance. The fault time duration is set based
upon the load capacitance, load current, and the
maximum output current. The "on" or fault time
must be of sufficient duration to charge the load
capacitance during a normal startup sequence or
when recovering from a fault. If not, the charge accumulated on the output capacitance will be depleted by the load during the "off" time. The cycle
Fault Time vs Timing Capacitance
30

./""

"0 25

.-/

120

... V

~ 15
LL

5

o ~
o

y/
0.2

0.4

0.6

Figure 6. Fault Time vs Timing Capacitance

COUT. VOUT

CT .
min

=

27.8E3. (lMAX -

ITRIP)

In addition to the IMAX and DAC inputs, the
UCC3912 provides a fault indicator output and
shutdown command. The FAULT signal is an open
drain output which is active low under any condition which turns the output MOSFET "off". These
conditions include under voltage lockout (UVLO),
over current faults, thermal shutdown, and active
shutdown as commanded by the SHTDWN input.
Note that FAULT is asserted (low) during power up
while the UCC3912 is in a UVLO state.
The SHTDWN command is an active low input
which turns the MOSFET "off" and puts the IC into
sleep mode, reducing the quiescent current to less
than 51lA. The shutdown command can be used to
extend the life of battery powered systems by powering down subsystems when not in use.
Unidirectional current flow is another attractive feature of UCC3912. The reverse voltage comparator
senses the output voltage and turns the MOSFET
"off" whenever the output voltage is less than
30mV below the input. Under light loads, the
UCC3912 regulates the voltage drop until
(4)

(lOUT) •

(RDSan) ~

30mV,

thus preventing false shutdowns. This effectively
prevents current flow from output to input, eliminating the need for series diode protection and the associated voltage drop and power losses incurred
with its use .
PRACTICAL CONSIDERATIONS

V

i=

~ 10

./"

COUT·VOUT
tFAULTmin = IMAX _ ITRIP

0.8

The UCC3912 is supplied in 16-pin power surface
mount packages. Four ground leads are provided
in order to effectively transfer heat out of the package. These pins should always be terminated to as
large an area of copper as possible. Although the
3% duty cycle switchmode protection drastically
minimizes power dissipation, thermal analysis
5-127

U-151

APPLICATION NOTE
should still be performed in order to insure reliable
circuit operation.
When interfacing with larger values of load capacitance, the UCC3912 fault time must be increased
accordingly. While the average power remains low
due to the 3% duty cycle, the power dissipation
during the fault time will result in a junction temperature rise based on the thermal time constant of
the system. A simplified thermal model of the system is comprised of the die, leadframe and PC
board. However, for fault times less than 30msec,
the effect of the leadframe and PC board can be
considered negligible as their thermal time constants are on the order of 2 and 300sec respectively. A rough estimate of the transient junction
temperature can then be calculated based on the
following equation:
(S)

Tj(t) = PDISS [ElDIE (1 - e-J4

Where

)J + TL

PDISS = transient power dissipation
ElDIE = thermal resistivity between die
and leadframe '" 4°/W
=fault time
1:
= thermal time constant of the die
'" 30msec
TL
= steady state lead temperature

As the fault time is increased beyond 30msec, a
more thorough transient thermal analysis is required. For additional information regarding thermal
analysis and transient response, the reader is directed to reference (1).
In applications requiring minimum voltage losses, it
is important to take the effects of PCB trace resistance into account. When passing two to three
amps of current, minimum trace widths can result
in enough I • R voltage drop to effect system performance. By increasing either the trace width or
copper weight, these effects can be made negligible. Table I provides resistance/inch values for
various trace widths of 1, 1 .S, and 2 oz. copper.

Copper
WI.
1.0 oz.
1.5 oz.
2.0 oz.

Table I
PCB Trace Resistance (mnlinch)
Trace Width (inches)
0.01
0.02 0.03 0.05 0.07
48.5 24.23 16.2
9.7
6.9
7.8
5.5
38.8 19.4 12.9
24
12
4.8
3.4
8

0.1
4.9
3.9
2.4

A TYPICAL APPLICATION

In order to evaluate the performance of the
UCC3912, consider a typical application consisting
of a 2A maximum load current in parallel with
120~F of load capacitance. The 2A output current

is accommodated by setting the UCC3912 trip current to 2.2SA, using the DAC inputs. Bits. BO and
B1 are grounded while bits B2 and B3 are tied to
VIN. The maximum output current is configured to
1A above the trip current (3.2SA) by grounding the
IMAX input. The timing capacitor value must then
be selected to accommodate the 120~F load capacitance:
(6)

CTmin =

COUT • VOUT
27.8E3. (IMAX - ITRIP)
120E-6.5
27.8E3 • (3.25 - 2.2S)

21.6nF

A 47nF capacitor was chosen in order to provide
adequate margin for component and parameter tolerances. Lastly, the SHTDWN input to· the
UCC3912 is connected to VIN since it is not used
in this example.
In actual hot swap applications, the circuit breaker
function may reside on the system's backplane
servicing one or more submodules, or be distributed throughout the individual submodules depending on system requirements. In order to test
both of these application scenarios, a MOSFET
was used to simulate a hot swap on the input and
output of the UCC3912. A test load was constructed using a 120~F low ESR tantalum capacitor in parallel with a carbon power resistor, while
240~F was used to simulate the system's input bus
capacitance. Output current was monitored using a
noninductive 10mU current shunt in series with the
load. Figure 7 illustrates the test setup including the
UCC3912 circuit configuration.
HOT SWAP PERFORMANCE

Figure 8 illustrates the load current and input voltage waveforms, measured at points A and B in Figure 7, with and without the UCC3912. In Figure
8(a) , transistor 02 was used to perform the hot
swap on the output of the UCC3912, simulating an
application with the circuit breaker resident on the
system backplane. In this situation the UCC3912
limits the load current to approximately 4A as compared to the 24A peak seen without the breaker!
Consequently, the voltage glitch seen at the input
bus capacitor is reduced from approximately 1V to
less than 1S0mV!
Figure 8(b) illustrates the results when 02 is used
to simulate the hot swap on the input of the
UCC3912. Again, the output current is controlled
as both the circuit breaker and submodule receive
power, providing very similar results to those of
Figure 8(a).

S-128

APPLICATION NOTE

U-151

,--JJl1J}±,
I

UCC3912

I

~
r

2

VOUT 14

2.30

VOUT 15

(A)

I

0.010

CT~

1 SHTDWN

I
L

0. 047 11 F =

IMAX I
10 ..J

Figure 7. Typical UCC3912 Configuration and Hot Swap Test Circuit Setup.

Tek Stop: Single Seq 1.00MS/S

1---'--- - - - ( ] - - - -I

--~ ~-]--~-- -

--

.

---.

- ....
r---

INPUT VOLTAGE
500mv/DIV

.
(AC COUPLED) 0,

I

OUTPUT

CURREN~ I~~

10NDIV

o

~-

__ ~l __ J_

I

L.-

t=50~sec/DIV

(A)

1.00~. .lS/s

Tek Stop: Single Seq

f--·---·--·--·---HJ··
r-;-r---'-"!'
'. "'"'! -

J

'

..

_-,

INPUT VOLTAGE

SOOmv/DIV
(AC COUPLED)

o -----

!

,

I

---- -1·-----1---

I

i

r

i

~

LJ__---.l____ l_ . _~__l _____L._ .__ i_ .___ L__.
- ~O~seciDIV ---

(8)

Figure 8. Hot Swap Results With and Without the UCC3912 Circuit Breaker. A) Hot Swap Performed on UCC3912
Output. B) Hot Swap Performed on UCC3912 Input.

5-129

APPLICATION NOTE

lJ-IOl

Tek Stop: 1.00MS/s

11 AcqS

I

A
INPUT VOLTAGE

500mvIDIV
(AC COUPLED)

[

A..

~I

Vc

A.) UCC3912
B.) 2AFUSE

C.) RXE250

C

~
A
OUTPUT CURRENT
10AIDIV

~

q.

1=5O~.eclDIV

Figure 9. Hot Swap Performance Comparison Between a Fuse, PolySwitch® and the UCC3912.

.

_-_._---,
33.2ms
I ~'..:
@: 33.1ms

__ oj
V~

Or

5V1DIV

VOLTAGE

2V/DIV

Figure 10. Short Circuit Performance of the UCC3912 Illustrating the 3% Duty Cycle Protection Technique.

Not shown in this figure is a delay of approximately
100llsec as the internal charge pump builds up
gate charge for the MOSFET.
The hot swap performance of the UCC3912 was
also compared to that of a fuse and PolySwitch®,
two industry standard protection devices. A 2.5A
PolySwitch® (RXE250) and a 2A slow-blow fuse
(Littelfuse 313.002) were each substituted for the
UCC3912 during a hot swap test. Figure 9 illustrates the results using the three different protection devices. Comparing the results of Figures 8
and 9, it is evident that both the fuse and
PolySwitch® offer virtually no protection for tran-

sients of this speed; the current magnitudes are
very close to those seen without any protection device at all. The circuit breaker, on the other hand,
provides a fast transient response, keeping the current and the associated voltage transient within
specification.
SHORT CIRCUIT PROTECTION

As previously described, the UCC3912 provides
overcurrent and short circuit protection by modulating the output at a 3% duty cycle. During the "on"
time, output current is limited to the value set by
the IMAX and DAC inputs. Figure 10 illustrates the
performance of the UCC3912 test circuit when a

5-130

U-1S1

APPLICATION NOTE

A.)
B.)
C.)
D.)

UCC3912
3A Fast Blow
2A Slow Blow
RXE250

OUTPUT VOLTAGE
2V/DIV

o
OUTPUT CURRENT
5A1DIV

200mslDIV
Figure 11. Short Circuit Performance Comparison of a Fuse, PolySwitch® and the UCC3912.

short-circuit is applied in place of the load. The bottom trace is the output current, modulated at a 3%
duty cycle, while the center trace is the voltage
across the timing capacitor. Note that the first current pulse is approximately 50% longer than subsequent pulses due to the timing capacitor initially
charging from OV.
The short circuit test was also conducted on the
2.5A PolySwitch®, 2A slow-blow fuse, and a 3A
fast-acting fuse (Littelfuse 312.003). Figure 11
compares the performance of the 4 different protection techniques. The peak currents incurred with
each of the fuses and the PolySwitch® reach approximately 17.5A and are limited only by the output capability of the 5V power supply. The
PolySwitch® takes approximately 1.25sec before it
begins to limit the current and eventually latches
into high impedance mode. At this point it will remain in a high impedance state due to a sustained
self heating current and will only reset after it has
cooled and the fault condition has been corrected.
As a result, the device requires that the input voltage be removed from the system in order to insure
a circuit reset. The fuses on the other hand, respond faster than the PolySwitch®, but once blown
require manual replacement before the hardware
can resume operation. Table II compares the I - T
and peak current characteristics of the four techniques.
Table /I
Protection Device

Peak Current
(Amps)

PolySwitch® RXE250

17.5

17.5

Fuse 312.003

17.5
17.5

9.75
0.875

3.25

0.098

Fuse 313.002
UCC3912

..

I-T
(Amp-sec)

Note: 1) Peak currents are limited by power supply.
2) I- T estimated for first second of short circuit.

When compared to any of the other commonly
used technologies, the performance of the
UCC3912 is superior. The electronic circuit breaker
responds almost immediately to a short circuit, limiting the current to 3.25A before turning off the output. The breaker then attempts to reapply power at
a 3% duty cycle until the fault has been corrected.
The low duty cycle, coupled with the current limiting feature keeps the power dissipation at a reasonable level, eliminating the need for extensive
heating sinking. In this example the UCC3912 dissipates only 5V - 3.25A - 3% = 488mW of power
during the short circuit.
POWER MANAGEMENT APPLICATIONS

In an effort to save energy, the federal government
is working to impose regulations that will require
electronic equipment and appliances to operate
more efficiently. As an example, consider the personal computer (PC). PCs typically dissipate 100 to
200W, with an additional 150 to 350W consumed
by the monitor. In order to limit the power dissipation to a recommended 30W during periods of
nonusage, circuitry must be added to shutdown
key components such as the monitor, high powered cache circuits and bus interfaces. The
UCC3912 offers a simple solution to these types of
power management applications.
The UCC3912 can be configured as a low current
«5!1A) standby power switch, as shown in Figure
12. The shutdown input, SHTDWN, is utilized to
turn off the internal MOSFET, removing power from
the load and reducing the UCC3912 quiescent current to <5IlA. When reactivated by the logic command, the current limiting features of the UCC3912
allow the load circuits to resume operation without
disrupting the rest of the system.

5-131

APPLICATION NOTE

Input Supply
+3.3V. or +5.0V

0

U-1S1

r--------,
I

UCC3912

Q~

J--

I SHTDWN

L-

Shutdown

0

I

VOUTQ---+GND

LOAD

I
...J

GND

"$"

UDG·94028·1

Figure 12. Low Current Standby Power Switch

Vee
3.3V
4.7~F

SCSI
BUS

UDG-94077

Figure 13. Typical 3.3V SCSI Application
APPLICATION CIRCUITS

The 3.3V power bus has quickly become the standard for laptop computers and other battery operated equipment. Unfortunately, SCSI standards
specify an active termination voltage of 2.7V. In addition, standards require that the Termpwr source
be fused and provide for unidirectional current flow.
These requirements have typically forced designers to include a 5V supply in 3.3V systems - a 5%,

3.3V bus leaves only 130mV of headroom for a di. ode, fuse, and regulator overhead. Replacing the
diode and fuse with the UCC3912 limits the voltage
drop to less than 60mV while still meeting SCSI requirements. Combining the UCC3912 with a low
dropout active terminator such as the UCC5614 results in a complete design. Figure 13 illustrates a
typical 3.3V SCSI application.

APPLICATION NOTE

U-1S1
Tek stop: Single Seq 500kS/s
,---

5V/DIV

f-----IT---------- ----------------1

I

[::

'

i

B2

B3

OUTPUT CURRENT

lNDIV

IL_ _
Figure 14. Controlled Current Slew Rate Using the UCC3912 4-8it DAC.

ON IOFF

>-1-4------

elK ' > - - - - - - - - - - - - '

Figure 15. UCC3912 Current Control Circuit Implementation.

The UCC3912 lends itself well to more sophisticated current limiting schemes through the use of
the DAC inputs. Greater control of output current
slew rate can be obtained by stepping the DAC
through a series of its input codes. Figure 14 illustrates the output current as the DAC inputs are
controlled using the output of a 4-bit counter as
shown in Figure 15. Similarly, loads such as motors
often require inrush currents several time~ th~ir
normal running value. By using the counter In Figure 15 to count down rather than up, the motor can
be quickly accelerated to speed using maximum

current and then closely protected against overload.
The duty cycle protection capability of the
UCC3912 can be disabled by grounding the timing
capacitor input, CT. This causes the UCC3912 to
remain in constant current mode during a fault condition. When operating in this manner the
UCC3912 is in linear mode and will dissipate
power as function of the maximum o~tput current
and differential input/output voltage. It IS extremely
important that adequate heatsinking is provided
when operating in this configuration.

5-133

APPLICATION NOTE

U·151

SUMMARY

REFERENCES

As demonstrated throughout this application note,
the UCC3912 provides a level of protection far superior to that offered by existing technologies. Integrating a high speed, programmable current
amplifier, power MOSFET, and charge pump allows
for precise control of both inrush and short circuit
currents. Fast, accurate transient control helps to
maintain power supply tolerance, enabling reliable
hot swap implementation. In addition, preventing
destructive current transients during connector
mating prolongs the life of the hardware. By integrating each of these features, the UCC3912 electronic circuit breaker offers a new and complete
solution to power management, hot swap, and
short circuit requirements.

[ 1 ] J. O'Connor, "Thermal Characteristics of Surface Mount Packages", Unitrode Product and
Applications Handbook, 1993-94.
[2] Raychem, PolySwitch® R-Line Circuit Protectors, RXE Product Family, Manufacturers
Data Sheet, Raychem Corporation, Menlo
Park, CA, 1993.
[3] Littelfuse, Electromechanical Devices and Circuit Protection Components, Manufacturers ,
Catalog No. 20, Littelfuse Tracor, Des Plaines,
IL,1985.

UNITRODE CORPORATION
7 CONTINENTAL BLVD.• MERRIMACK, NH 03054
TEL. (603) 424-2410. FAX (603) 424-3460

5-134

Selection Guides - Drivers I Receivers I Transceivers
Drivers I Receivers I Transceivers
Interface
Drivers, Receivers
Drivers
Receivers
Power
EIA232/V.28
EIA423/V.10
EIA422/V.11
V.35
Appletalk
Page Number

Interface Transceivers
Drivers
Receivers
Power
Control Area Network
Device Net
SDS
Page Number

UC5170C

UNITRODE PART NUMBER
UC5171
UC5172
UC5180C

a

a

a

±10V
y
y
N
N
N
IF/6·3

±10V
y
y
N
N
N
IF/6-7

±10V
y
y
N
N
N
IF/6-11

UC5350
1
1
+5V
y
y
y
IF/6-21

a
+5V
y
y
Y
Y
N
IF/6·15

UNITRODE PART NUMBER
UC5351+
1
1
+5Vlo24V
y
y
y
IF/6-27

+ New Product

6-1

-

OJ]

UC5181C
a
+5V
y
y
Y
Y
Y
IF/6-1a

-

[1JJ

~UNITRODE

6-2

~UNITROOE

UC5170C

Octal Line Driver
FEATURES

DESCRIPTION

•

Eight Single Ended Line Drivers in
One Package

•

Meets EIA Standards
EIA232EN.28, EIA423A and
CCITT V.101X.26

The UC5170C is a single-ended octal line driver designed to meet both
standard modem control applications (EIA232EN.28), and long line drive
applications (EIA423AN.1 01X.26). The slew rate for all eight drivers is controlled by a single external resistor. The slew rate and output levels in Low
Mode are independent of the power variations.

•

Single External Resistor Controls
Slew Rate

•

Wide Supply Voltage Range

•

Tri-State Outputs

•

Output Short-Circuit Protection

Mode selection is easily accomplished by taking the select pins (Ms+ and
Ms-) to ground for low output mode (EIA232EN.28 and EIA423AN.10) or
to their respective supplies for high mode (EIA232EN.28). High mode
should only by used to drive adapters that take power from the control
lines, or applications using high threshold receivers.

ABSOLUTE MAXIMUM RATINGS (Note 1)

FUNCTIONAL TABLE

V+ (Pin 20) ...................................... 15V
V- (Pin 11) ...................................... -15V
PLCC Power Dissipation, TA =25°C (Note 2) . . . . .. 1000 mW
DIP Power Dissipation, TA =25°C (Note 2) ........ 1250 mW
Input Voltage ............................. -1.5Vto+7V
Output Voltage ........................... -12V to +12V
Slew Rate Resistor. . . . . . . . . . . . . . . . . . . . . . . . .. 2k to 10kn
Storage Temperature. . . . . . . . . . . . . . . . . .. -65°C to +150°C
Note 1: All voltages are with respect to ground, pin 18.
Note 2: Consult Packaging Section of Databook for thermallimi-

INPUTS

OUTPUTS
HIGH
EIA-232E(2)
(V+)-3V
(V-)-3V
HighZ

EN
DATA
0
0
1
0
1
X
Note 2: Minimum output swings.

LOW
EIA423A+EIA232E
5Vt06V
-5Vto -6V
HighZ

tations and considerations of packages.

CONNECTION DIAGRAMS
Q PACKAGE (TOP VIEW)

N PACKAGE (TOP VIEW)
NC 1
2

BI AI AoNC Ho HI GI

Ho
HI
GI
Go

Bo

Go

CI

FI

Fo

Do 9

FI
EI
Eo

DI

EI

Do

Eo

V+

ENABLE

ENABLE
V- 11

Ms+

SRA

MsNC

NC
NC

V-

V+
MS+

11

GND
SRA NC NC NC NC MS-GND

NC

7/95
6-3

UC5170C

DC ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications hold for 1V+ 1= 1V -I = 10V,
0< TA < +70°C, Ms+ = Ms-= OV, RSRA = +10k, TA=TJ.

PARAMETERS

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS
V

POWER SUPPLY REQUIREMENTS
V+Range

9

15

V- Range

-9

-15

V

V+ Supply Current

1+

RL = Infinite En = OV

25

42

mA

V- Supply Current

1-

RL = Infinite En = OV

-23

-42

mA

INPUTS
2.0

V

High Level Input Voltage

VIH

Low Level Input Voltage

VIL

Input Clamp Voltage

VIK

II =-15 mA

-1.1

-1.B

V

High Level Input Current

IIH

VIH=2.4V

0.25

40

Low Level Input Current

IlL

VIL= O.4V

ItA
ItA

VOH

VIN=O.BV
En=O.BV

O.B

V

-200

-B.O

RL= Inf.

5.0

5.3

6.0

V

RL=3k

5.0

5.3

6.0

V

4.5

5.2

6.0

V

OUTPUTS
High Level (Low Mode) Output Voltage
(EIA423AN.l0, EIA232E1V.2B)

RL = 450
Low Level (Low Mode) Output Voltage

VOL

(EIA423AN.l0,EIA232E1V.2B)

VIN =2.0V

RL= Inf.

-5.0

-5.3

-6.0

V

En=O.BV

RL=3k

-5.0

-5.3

-6.0

V

-4.5

-5.2

-6.0

V

0.2

0.4

V
V

RL=450
Output Balance (EIA423AN.l 0)

VBAL

RL = 450 VOH - VOL = VBAL

High Level (High Mode) Output Voltage

VOH

VIN=O.BV

RL = Inf., Ms+ = V+, Ms- = V-

7.0

7.6

10

En = 0.8V

RL = 3k, MSt = V+, Ms- = V-

7.0

7.6

10

V

VIN=2.0V RL = Inf., Ms+ = V+, Ms- =V-

-7.0

-7.7

-10

V

-7.0

-7.7

-10

V

(EIA232E1V.2B)
Low Level (High Mode) Output Voltage

VOL

(EIA232E, V.28)

RL = 3k, Ms+ = V+, Ms- = V-

En=0.8V

-100

100

ItA

Off-State Output Current

loz

En = 2.0V, vo = ±6V, V+ = 15V, V- = -15V

Short-Circuit Current

los

VIN = OV, En = OV

25

50

mA

VIN = 5V, En = OV

25

40

mA

AC ELECTRICAL CHARACTERISTICS:

at 1V+ 1= 1V -I = 10V, 0 < TA < +70°C, Ms+ = Ms- = OV, TA =TJ.

MIN

TYP

MAX

UNITS

tR

RSRA=2k

6.65

9.5

12.3

V/IJS

tF

RL = 450, CL = 50pF

6.65

10

12.3

V/IJS

Output Slew Rate

tR

RSRA = 10k

1.33

1.9

2.45

V/lls

tF

RL = 450, CL = 50pF

1.33

2.2

2.45

V/IJS

Propagation Output to

tHz

RSRA= 10k

0.3

1.0

Ils

High Impedance

tLz

RL = 450, CL = 50pF

0.5

1.0

IJS

Propagation High Impedance to

tzH

RSRA= 10k

6.0

15

IJS

Output

tzL

RL = 450, CL = 50pF

7.0

15

IJS

PARAMETERS
Output Slew Rate

SYMBOL

TEST CONDITIONS

6-4

UC5170C
AC PARAMETER TEST CIRCUIT AND WAVEFORMS

r-----------------------------------,

+10V
INPUT

VEti
.------l ENABLE

V+
fo---.-----1>--O OUTPUT
OUTPUT
VIN ~ OV

CL

VEN
OUTPUT
VIN ~ 5V

AC CHARACTERISTICS
Low Output Driver tR & tF (10-90%)
EIA232E + EIA423A Mode

Driver Slew Rate
12.50
Ul

~

>

Q)

5.00

10.00

Ul

~
~

7.50

-:;;
II:

;:

5.00

Q)

ii5

1.50
0

o

::I.

/

4.00

/" /

Q)

E
i= 3.00

IF

~~

2.00

~V

'iii
c:

os

r--

i=-

1.00
0

2.00 4.00 6.00 8.00 10.00
RSRA

~~

c:

.g

kn

APPLICATION INFORMATION
Slew Rate Programming

o

2.00 4.00 6.00 8.00 10.00
RSRA kn

Max. Data Rate = 300ft (For data rates 1k to 100k bitls)

Slew rate for the UC5170C is set up by a single external
resistor connected between the SRA pin and ground.
Slew rate adjustments can be approximated by using
the following formula:

Max. Cable Length (feet) = 100 x t (Max. length 4000 feet)
where t is the transition time from 10% to 90% of the
output swing in microseconds. For data rates below 1k
bitls t may be up to 300 microseconds.

V/Ils= R20 (RsRA in k Q)

Output Voltage Programming

SRA

The UC5170C has two programmable output modes,
either a low voltage mode which meets EIA423A,
E IA232EN.28N.1 0 specifications, or the high output
mode which meets the EIA232E, V.28 specifications.

The slew rate resistor can vary between 2k and 10k
which allows slew rates between 10 to 2.2V/llS, respectively. The relationship between slew rate and RSRA is
shown in the typical characteristics.

The high output mode provides greater output swings,
minimum of 3V below and supply rails for driving higher,
attenuated lines. This mode is selected by connecting
the mode select pins to their respected supplies, Ms+ to
V+ and Ms- to V-.

Waveshaping of the output lets the user control the
level of interference (near-end crosstalk) that may be
coupled to adjacent circuits in an interconnection. The
recommended output characteristics for cable length
and data rates can be found in EIA standard EIA423A
+V.10. Approximations of these standards are given by
the following equations:

The low output mode provides a controlled output swing
and is accomplished by connecting both mode select
pins to ground.

6-5

UC5170C

APPLICATIONS

I

I
I
I
I
I
I
I
I

L

VH -

-

-

-

VLTI

V+

-I

I
I

EIA232EIV.28 EIA423AIV.10

1- - - - - - ,

I
+V 'I
I"
VH 'I
I" I
~~_____-V~~~
________-+__~
VL
~ I
I
I
I :*
I
* TIE TO
TWISTED PAIR
I GROUND
I
I
OR
I FOR EIA232EIV.28 I
DATA TRANSMISSION

I
I

----1-

_
V-

-------~

FLAT CABLE

SPECIFIC LAYOUT NOTES
The UCS170C layout must have bulk bypassing close to
the device. Peak slew current is greater than SOOmA
when all eight drivers slew at once in the same direction.
Some applications mount the UCS170C on a bulkhead or
isolated plane for RFI/FCCNDE reasons. If bulk bypassing is not used, the -10V supply may go above -8.S volts,
causing the slew rate control circuit to become unstable.
The UCS170C can have output oscillation at 100kHz if
the +10V supply is applied before the -10V supply. This
has been a problem in some terminal designs where the
+ 1OV was developed from the flyback, which can result in
a SOOms difference in the application of the supplies at
power up.

L

______

~

Filter connectors or transzorbs should be used to reduce
the RFI/EMI, protecting the system from static (ESD), and
electrical overstress (EOS). A filter connector or capacitor
will reduce the ESD pulse by 90% typically. A cable
dragged across a carpet and connected to a system can
easily be charged to over 2S,OO volts. This is a metal to
metal contact when the cable is connected to the system
(no resistance), currents exceed 80 amps with less than a
nanosecond rise time. A transzorb provides two functions,
the device capacitance inherently acts as a filtercapacitor, and the device clamps the ESD and EOS pulses
which would pass through the capacitor and destroy the
devices. The recommended transzorb for the UCS170C is
P6KEIOCA.

GENERAL LAYOUT NOTES
The drivers and receivers should be mounted close to the
system common ground point, with the ground reference
tied to the common point to reduce RFI/EMI.

*Transzorb is a trademark of General Semiconductor
Industries.

UNITRODE CORPORATION
7 CONTINENTAL BLVD .• MERRIMACK. NH 03054
TEL. (603) 424·2410. FAX (603) 424-3460

6-6

~UNITRODE

UC5171

Octal Line Driver
FEATURES

DESCRIPTION

•

Eight Single-Ended Line Drivers in One
Package

•

Digital Selection of High Mode
EIA232E/CCITT V.28 only, and Low
Mode EIA232EN.28 & EIA423A1CCITT
V.101X.26

The UC5171 is a single-ended octal line driver designed to meet both
standard modem control applications (EIA232EN.28), and long line
drive applications (EIA423AN.101X.26). The slew rate for all 8 drivers
is controlled by a single external resistor. The slew rate and output levels in Low Mode are independent of the power variations.

•

Single External Resistor Controls Slew
Rate

•

Wide Supply Voltage Range

•

Tri-State Outputs

•

Output Short-Circuit Protection

•

Low Power Consumption

•

2kV ESD Protection on all Pins

Mode selection is accomplished by the select pin Ms logic "low" for low
output mode (EIA232EN.28 & EIA423AN.1 0) or pin Ms logic "high" for
high mode (EIA232EN.28). High mode should only be used to drive
adapters that take power from the control lines, or applications using
high threshold receivers.

ABSOLUTE MAXIMUM RATINGS (Note 1)
V+ (Pin 20) .................................................. 15V
V- (Pin 11) .................................................. -15V
PLCC Power Dissipation, TA = 25°C (Note 2) ... . . . . . . . . . . . . . .. 1000 mW
DIP Power Dissipation, TA =25°C (Note 2) .................... 1250 mW
Input Voltage .......................................... -1.5V to +7V
Output Voltage .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -12V to +12V
Slew Rate Resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2k to 10kn
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°C to +150°C
Note 1: All voltages are with respect to ground, pin 18.
Note 2: Consult Packaging section of Databook for thermal limitations and
considerations of package.

FUNCTIONAL TABLE
INPUTS
OUTPUTS
EIA-232E(3)
EN
DATA
EIA-232E1EIA-423A
(V+)-3V
5V to 6V
0
0
0
1
(V-)+3V
-5Vto-6V
1
HighZ
HighZ
X
..
Note 3. MInimum output swmgs.

CONNECTION DIAGRAMS
Q PACKAGE (TOP VIEW)

N PACKAGE (TOP VIEW)

r-----,

BI AI AoNC Ho HI GI

NC 1

Ho

Go

Do 9
ENABLE
VSRA
NC
NC

2

V+
Ms
GND
NC
NC
NC

Bo

Go

Co

Fo

CI

FI

01

EI

Do

Eo

ENABLE

V+

V-

MS

SRA NC NC NC NC NC GND

7195
6-7

UC5171

DC ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications hold for I v+1 = I V -I'" +10V,
0

OUTPUT
OUTPUT
VIN = OV

CL

1HZ

IZH

OUTPUT
VIN = 5V

-10V

ILZ

IZL

AC CHARACTERISTICS
Driver tR & tF (10-90%) EIA-423A Mode

Driver Slew Rate
12.50
!J)

:::i.

5.00

10.00

!J)

~
~ r-...t

;;
(J)

iU
a:
;:

7.50
5.00
1.50
0

o

/

4.00

/ V

E
i= 3.00
c:

F

I~ :::::-

(J)

Ci5

:::i.
(J)

0
:;::;

2.00

~

·iii

-

c:

as

~

1.00
0

2.00 4.00 6.00 8.00 10.00

o

/: ~

,/

2.00 4.00 6.00 8.00 10.00
RSRA kn

RSRA kn

APPLICATIONS INFORMATION
Slew Rate Programming
Slew rate for the UC5171 is set up by a single external resistor connected between the SRA pin and ground. Slew
rate adjustments can be approximated by using the following formula:

~~S=R20 (Rs~inkQ)
SRA

The slew rate resistor can vary between 2k and 10kn
which allows slew rates between 10 to 2.2V/~s, respectively. The relationship between slew rate and RSRA is
shown in the typical characteristics.
Waveshaping of the output lets the user control the level
of interference (near-end crosstalk) that may be coupled
to adjacent circuits in an interconnection. The recommended output characteristics for cable length and data
rates can be found in EIA standard EIA-423A. Approximations of these standards are given by the following equations:
Max. Data

Rate=300lt (For data rates 1k to 100k bills)

Max. Cable Length (feet)=100 x t (Max. length 4000
feet)

where t is the transition time from 10% to 90% of the output swing in microseconds. For data rates below 1k bills,
t may be up to 300 microseconds.
Output Voltage Programming
The UC5171 has two programmable output modes, either
a low voltage mode which meets EIA-423A operational
specifications, or the high output voltage mode which
meets the EIA-232E specifications.

The high output mode provides greater output swings,
minimum of 3V below the supply rails, for driving higher,
attenuated lines. This mode is selected by connecting the
modes select pin, (Ms), to a TTL "high" level. The low output mode provides a controlled output swing and is accomplished by connecting the mode select pin, (MS), to a
TTL "low level."
EIA Standards
The UC5171 meets or exceeds the EIA Standards for
EIA-232E and EIA-423A modes of operation except under
power down conditions. When powered down with the
output attached to an active buss, the UC5171 has the
potential to load the bus under transient conditions.

6-9

UC5171

APPLICATIONS

I" VH

I
I
I
I
I
I
I
I

L

-

-

VLTI

-

-

V+

_
V-

-

I

EIA232E I EIA423A

I
I

I - - - - - - I

I
+ V -,
r
VH -,
r I
>r~____-~V_~
~~------~--~
~ ~ I
I
I
I
I i*
I' _'
* TIE TO
I
TWISTED PAIR
GROUND
I
OR
I
FOR EIA232E
I

-------~

DATA TRANSMISSION

FLAT CABLE

UC5171 Specific Layout Notes

The UC5171 layout must have bulk bypassing close to
the device. Peak slew current is greater than 500mA
when all eight drivers slew at once in the same direction.
Some applications mount the UC5171 on a bulkhead or
isolated plane for RFIIFCCNDE reasons. If bulk bypassing is not used, the -10V supply may go above -8.5 volts,
causing the slew rate control circuit to become unstable.
The UC5171 can have output oscillation at 100kHz if the
+ 1OV supply is applied before the -10V supply. This has
been a problem in some terminal designs where the +1 OV
was developed from the flyback, which can result in a
500ms difference in the application of the supplies at
power up.

I
I

L

______

~

Filter connectors or transzorbs should be used to reduce
the RFIIEMI, protecting the system from static (ESD), and
electrical overstress (EOS). A filter connector or capacitor
will reduce the ESD pulse by 90% typically. A cable
dragged across a carpet and connected to a system can
easily be charged to over 25,000 volts. This is a metal-tometal contact when the cable is connected to the system
(no resistance), currents exceed 80 amps with less than a
nanosecond rise time. A transzorb provides two functions,
the device capacitance inherently acts as a filter capacitor, and the device clamps the ESD and EOS pulses
which would pass through the capacitor and destroy the
devices. The recommended transzorb for the UC5171 is
P6KEIOCA

General Layout Notes

The drivers and receivers should be mounted close to the
system common ground point, with the ground reference
tied to the common point to reduce RFIIEMI. .

*Transzorb is a trademark of General Semiconductor
Industries.

UNITRODE CORPORATION
7 CONTINENTAL BLVD .• MERRIMACK, NH 03054
TEL. (603) 424-2410. FAX (603) 424-3460

6-10

~UNITRODE

UC5172

Octal Line Driver
FEATURES

DESCRIPTION

•

Eight Single-Ended Line Drivers in One
Package

•

Meets Standards EIA232E/CCITT V.28,
and EIA423A1CCITT V.1 O/X.26

The UC5172 is a single-ended octal line driver designed to meet both
standard modem control applications (EIA232EN.28), and long line
drive applications (EIA423A1V.10/X.26). The slew rate for all 8 drivers
is controlled by a single external resistor. The slew rate and output levels are independent of the power variations.

•

Single External Resistor Controls Slew
Rate

•
•
•
•
•
•

Wide Supply Voltage Range

•

The UC5172 has high output current, and current balance for long line
drive applications. EOS - Output parasitic SCRs powered on and off
are 35V, well above signal levels, allowing protection devices to work.
Inputs are compatible TTL+MOS logic families and are diode protected
against negative transients.

Tri-State Outputs
Output Short-Circuit Protection

FUNCTIONAL TABLE

Low Power Consumption

INPUTS

2kV ESD Protection on all Pins
EOS on all Output Pins 35V under all
Output Conditions
High Current Output for Long Line
Drive, Exceeds Standards

EN

DATA

0
0

0

..1
Note 2: Mmlmum output swmgs.

OUTPUT
EIA232E1EIA423A

1
X

5V to 6V
-5V to -6V
HighZ

ABSOLUTE MAXIMUM RATINGS (Note 1)
V+ (Pin 20) .................................................. 15V
V-(Pin 11) .................................................. -15V
PLCC Power Dissipation, TA=25°C (Note 3) ................... 1000 mW
DIP Power Dissipation, TA=25°C (Note 3) ..................... 1250 mW
Input Voltage .......................................... -1.5V to +7V
Output Voltage .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -6V to +6V
Slew Rate Resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2k to 10kn
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°C to +150°C
Note 1: All voltages are with respect to ground, pin 18.
Note 3: Consult Packaging section of Databook for therma/limitations and
considerations of package.

CONNECTION DIAGRAMS
N PACKAGE (TOP VIEW)
NC

Q PACKAGE (TOP VIEW)

BI AI AoNC Ho HI GI
1

Ho
HI
GI
Go
Fo
FI
EI

NC
NC

11

Go
Fo

CI

FI

01

EI

Do

Eo

ENABLE

V+

V-

NC

Do 9
ENABLE
VSRA

Bo
Co

GND
NC
NC
NC

SRA NC NC NC NC NC GND

9/96
6-11

UC5172

DC ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications hold for IV+I = IV-I = 10V,
O°C < TA < +70°C, RSRA= +10k, TA=TJ.

PARAMETER

SYMBOL

TEST CONDITIONS

I

MIN

TYP

MAX

UNITS
V

POWER SUPPLY REQUIREMENTS
V+ Range

9

15

V- Range

-9

-15

V

V+ Supply Current
V- Supply Current

1+
1-

RL = Infinite En = OV

15

25

mA

RL = Infinite En = OV

-17

-25

mA

INPUTS
High-Level Input Voltage

VIH

Low-Level Input Voltage
Input Clamp Voltage

VIL
VIK

11= -15mA

High Level Input Current

IIH

VIH =2.4V

Low Level Input Current

ilL

VIL=O.4V

VOH

VIN= 0.8V
En = 0.8V

2.0

V
0.8

V

-1.1

-18

V

-2

0.25

40

j.lA

-200

-8.0

RL= Inf.

5.0

5.3

6.0

V

RL=3k

5.0

5.3

6.0

V

RL=450

4.5

5.2

6.0

V

VIN= 2.0V

RL= Inf.

-5.0

-5.3

-6.0

V

En = 0.8V

RL=3k

-5.0

-5.6

-6.0

V

RL = 450

-4.5

-5.4

-6.0

V

0.2

0.4

V

100

j.lA

j.lA

OUTPUTS
High Level Output Voltage
EIA232E
(EIA-423A)
Low Level Output Voltage

VOL

EIA232E

-

(EIA-423A)
Output Balance (EIA-423A)

VBAL

RL = 450, VOH - VOL = VBAL

Off-State Output Current

loz

En=2.0V, Vo=±6V, V+= 15V, V-=-15V

Short-Circuit Current

los

En=OV

Power Off Output Current

Ipo

-100

VIN=OV

25

65

VIN=5V

25

70

Vo=±6V, V+=V-=OV

-100

mA
mA
100

mA

AC ELECTRICAL CHARACTERISTICS: at IV+I = IV-I = +10V, O°C < TA < +70°C, TA = TJ.
PARAMETER

TYP

RSRA=2k

7.6

8.5

9.4

tF

RL = 450, CL = 50pF

7.6

8.5

9.4

tR

RSRA= 10k

1.5

1.7

1.9

VJlS

tF

RL = 450, CL = 50pF

1.5

1.7

1.9

V/JlS

Propagation Output
to High Impedance

1Hz

RSRA= 10k

0.8

2.0

Ils

ILz

RL = 450, CL = 50pF

0.5

2.0

Propagation High
Impedance to Output

tzH

RSRA= 10k

2.0

7.0

JlS
ms

tzL

RL = 450, CL = 50pF

1.0

7.0

JlS

Output Slew Rate

SYMBOL

TEST CONDITIONS

MAX UNITS

MIN

tR

Output Slew Rate

6-12

V/JlS
V/IlS

UC5172
AC PARAMETER TEST CIRCUIT AND WAVEFORMS
~--------------------------------~

+10V

INPUT
VEN

,--------i ENABLE
i---f-----11--O

OUTPUT

OUTPUT

CL

VIN

=

OV

VEN

OUTPUT
VIN = 5V

AC CHARACTERISTICS
Driver Slew Rate

Driver tR & tF (10-90%) EIA-423A Mode

12.50

'"

~

>

Q)

5.00

10.00

~
~

7.50

a;
II:

;:

5.00

Q)

en

1.50
0

o

'"::!.

/

4.00

/ V

Q)

E 3.00
i=
,IF

c::

~~

:;::

0

2.00

~

'iii
c::

as

I--

~

1.00

o

2.00 4.00 6.00 8.00 10.00
RSRA kn

o

I~ ~

,/

2.00 4.00 6.00 8.00 10.00
RSRA kn

APPLICATIONS
Slew Rate Programming
Slew rate for the UC5172 is set up by a single external resistor connected between the SRA pin and ground. Slew
rate adjustments can be approximated by using the following formula:

to adjacent circuits in an interconnection. The recommended output characteristics for cable length and data
rates can be found in EIA standard EIA-423A. Approximations of these standards are given by the following equations:
Max. Data Rate = 300ft (For data rates 1k to 100k bitls)
Max. Cable Length (feet) = 100 x t (Max. length 4000
feet)

Vlj.Ls= R20 (RSRA in kQ)
SRA

The slew rate resistor can vary between 2k and 10ka
which allows slew rates between 10 to 2.2V/~s, respectively. The relationship between slew rate and RSRA is
shown in the typical characteristics.
Waveshaping of the output lets the user control the level
of interference (near-end crosstalk) that may be coupled

where t is the transition time from 10% to 90% of the output swing in microseconds. For data rates below 1k bitls,
t may be up to 300 microseconds.
The UC5172 has been used in applications up to
460KBPS.

6-13

UC5172

APPLICATIONS

I

VH -

-

-

I VLn
I
I
I
I
I
I
I

-

-

-

I

EIA232EIV.28 EIA423AIV.10

I
I

I - - - - - - I

I
+V"I
r
VH"I
r I
;xr-l-_ _-_V_~
LJ.__---~---I
VL
LJ I
I
I
I :•
I
TIE TO
I GROUND
I
TWISTED PAIR
_
I
OR
I FOR EIA232EIV.28 I
L _____ V~ _ --1
FLAT CABLE
L ______ .-J
V+

DATA TRANSMISSION

I
I

----1.-

Specific Layout Notes
The UC5172 layout must have bulk bypassing close to
the device. Peak slew current is greater than 500mA
when all eight drivers slew at once in the same direction.
Some applications mount the UC5172 on a bulkhead or
isolated plane for RFIIFCCNDE reasons. If bulk bypassing is not used, the -10V supply may go above -8.5 volts,
causing the slew rate control circuit to become unstable.
The UC5172 can have output oscillation at 100kHz if the
+ 1OV supply is applied before the -10V supply. This has
been a problem in some terminal designs where the + 1OV
was developed from the flyback, which can result in a
500ms difference in the application of the supplies at
power up.

•

Filter connectors or transzorbs should be used. to reduce
the RFI/EMI, protecting the system from static (ESD), and
electrical overstress (EOS). A filter connector or capacitor
will reduce the ESD pulse by 90% typically. A cable
dragged across a carpet and connected to a system can
easily be charged to over 25,000 volts. This is a metal to
metal contact when the cable is connected to the system
(no resistance), currents exceed 80 amps with less than a
nanosecond rise time. A transzorb provides two functions,
the device capacitance inherently acts as a filter capacitor, and the device clamps the ESD and EOS pulses
which would pass through the capacitor and destroy the
devices. The recommended transzorb for the UC5172 is
P6KEIOCA.

General Layout Notes
The drivers and receivers should be mounted close to the
system common ground point, with the ground reference
tied to the common point to reduce RFI/EMI.

*Transzorb is a trademark of General Semiconductor
Industries.

UNITRODE CORPORATION
7 CONTINENTAL BLVD .• MERRIMACK, NH 03054
TEL. (603) 424·2410 • FAX (603) 424-3460

6-14

~UNITROCE

UC5180C

Octal Line Receiver
FEATURES

DESCRIPTION

•

Meets EIA 232E/423A1422A and CCITT
V.10,V.11, V.28, X.26, X.27

•

Single +5V Supply--TTL Compatible
Outputs

•
•

Differential Inputs Withstand ± 25V

The UC5180C is an octal line receiver designed to meet a wide range
of digital communications requirements as outlined in EIA standards
EIA232E, EIA423A, EIA422A, and CCITT V.10, V.11, V.28, X.26, and
X.27. The UC5180C includes an input noise filter and is intended for
applications employing data rates up to 200 KBPS. A failsafe function
allows these devices to "fail" to a known state under a wide variety of
fault conditions at the inputs.

Low Open Circuit Voltage for Improved
Failsafe Characteristic

•

Reduced Supply Current--35 rnA Max

•
•

Input Noise Filter

ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, Vee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7V
Output Sink Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50 mA
Output Short Circuit Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 Sec
Common Mode Input Range .................................... 15V
Differential Input Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25V
Failsafe Voltage ......................................... -0.3 to Vee
PLCC Power Dissipation, TA =25°C (Note 2) ................... 1000 mW
DIP Power Dissipation, TA = 25°C (Note 2) .................... 1200 mW
Storage Temperature Range .......................... -65°C to +150°C
Lead Temperature (Soldering, 10 Seconds) ...................... -300°C
Note 1: All voltages are with respect to ground, pin 14. Currents are positive

Internal Hysteresis

into, negative out of the specified terminal
Note 2: Consult Packaging Section of Databook for thermal limitations and
considerations of package.

CONNECTION DIAGRAMS
DIL-28 (TOP VIEW)

PLCC-28 (TOP VIEW)
8- Ao A+ A- Vee Ho H+
Vee
Ho
H+
HGo
G+
GFS2
Fo

0+
Do
GND

F+
FEo

B+

H-

Bo

Go

FS1

G+

C-

G-

C+

FS2

Co

Fo

D-

F+

E+
E-

D+ Do GND E- E+ Eo F-

1/94
6-15

UC5180C

DC ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications apply for TA = O°C to +70°C, Vee
= 5V + 5"1c0, Input C ammon Made Range+ 7V , T A=T J
PARAMETERS

SYMBOL

DC Input Resistance
Failsafe Output Voltage

RIN
VOFS

TEST CONDITIONS

UC5180C
MAX
MIN
7
3
0.45
2.7

3V <; I VIN I < 25V
Inputs Open or Shorted
Together, or One Input
Open and One Grounded

O:S; 10UT:S; 8mA, VFAILSAFE = OV
o ~ loun: - 400 IJA,
VFAILSAFE = Vee
Rs = 0 (Note 2)
VOUT = 2.7V, lOUT = 440 IJA
(See Figure 1)
Rs = 500 (Note 2)
Rs = 0 (Note 2)
VOUT = 0.45V,loUT = 440 rnA
(See Figure 1)
Rs = 500 (Note 2)
Fs = OV or Vee (See Figure 1)

Differential Input High
Threshold

VTH

Differential Input Low
Threshold

VTL

Hysteresis
Open Circuit Input Voltage
Input Capacitance

VH
Vlee
CI

High Level Output Voltage
Low Level Output Voltage

VeH
VOL

VID = 1V, lOUT = - 440uA
VID = -1V
(Note 3)

Short Circuit Output
Current
Supply Current
Input Current

los

Note 4

lee
liN

4.75V < Vee < 5.25V
Other Inputs Grounded

50
-200
-400
50

UNITS
k.Q

V

200
400
-50

mV

140
75
20

mV
mV
pF

mV

2.7
IOUT=4 rnA
IOUT=8 rnA
20

VIN = +10V
VIN= -10V

35
3.25

rnA
rnA

VOUT
Fs=GND

Fs=Vcc

- - VtL1 VtH1

rnA

-3.25

Note 2: Rs is a resistor in series with each input.
Note 3: Measured after 100ms wann up (at O°C)
Note 4: Only 1 output may be shorted at one time
and then only for a maximum of 1 sec.

VH1

V
V

0.4
0.45
100

o

Vt L2

-VH 2

VtH2

VIN

Figure 1. VtL, VtH, VH Definition

AC ELECTRICAL CHARACTERISTICS: Vee = 5V ± 5%, TA = O°Ctd + 70°C, Figure 2, TA = TJ.
PARAMETERS
Propagation Delay - Low to High
Propagation Delay - High to Low
Acceptance Input Frequency
Rejectable Input Frequency

SYMBOL
tPLH
tPHL
fA
fR

TEST CONDITIONS
CL = 50pF, VIN = ± 500mV
CL = 50pF VIN = ± 500mV
Unused Input Grounded, VIN = + 200mV
Unused Input Grounded, VIN = ± 500mV

6-16

UC5180C
MAX
MIN
550
550
0.1
5.5

UNITS
ns
ns
MHz
MHz

UC5180C

IL

Vee

+0.5V
-0.5V

SL

VFAILSAFE

Figure 2. AC Test Circuit

APPLICATIONS INFORMATION
under fault conditions, while a connection to ground
provides a logic "0". There are two failsafe pins (FS1
and FS2) on the UC5180C where each provides common failsafe control for four receivers.

Failsafe Operation
These devices provide a failsafe operating mode to
guard against input fault conditions as defined in
EIA422A and EIA423A standards. These fault conditions are (1) drive in power-off condition, (2) receiver not
interconnected with driver, (3) open-circuited interconnecting cable, and (4) short-circuited interconnecting
cable. If one of these four fault conditions occurs at the
inputs of a receiver, then the output of that receiver is
driven to a known logic level. The receiver is programmed by connecting the failsafe input to Vee or
ground. A connection to Vee provides a logic "1" output

Input Filtering (UC5180C)
The UC5180C has input filtering for additional noise rejection. This filtering is a function of both signal level
and frequency. For the specified input (5.5 MHz at ±500
mY) the input stage filter attenuates the signal such that
the output stage threshold levels are not exceeded and
no change of state occurs at the output.

EIA232E1V.28! EIA423AN.10 DATA TRANSMISSION

Vcc

VH

II
1/8

L

VL..J

ue5170e:;>a-+------+--I

VHLS
"TIE TO
GROUND
FOR EIA232EIV.28
V FAILSAFE

EIA422AN.11 DATA TRANSMISSION

I

VH

n

VL..J

L

EIA422AIV.11

LINE
DRIVER

I
I
I
I
I
I
I

+V

-V

JL

Vee

VH

JL

VL

~

+
V

~

~V Lf

UNITRODE CORPORATION
7 CONTINENTAL BLVD .• MERRIMACK, NH 03054
TEL. (603) 424·2410 • FAX (603) 424-3460

6-17

VFAILSAFE

~UNITRODE

UC5181C

Octal Line Receiver
FEATURES

DESCRIPTION

•

Meets EIA232E1423A1422A and CCITT
V.10, V.11, V.28, X.26, X.27

•

Single +5V Supply-TTL Compatible
Outputs

•

Differential Inputs withstand ±25V

•

Low Open Circuit Voltage for Improved
Failsafe Characteristic

The UC5181C is an octal line receiver designed to meet a wide range
of digital communications requirements as outlined in EIA standards
EIA232E, EIA422A, EIA423A and CCITT V.10, V.11, V.28, X.26, and
X.27. The UC5181C is similar to the UC5180C, but without the input
filtering. Thus, it covers the entire range of data rates up to 10MBPS. A
failsafe function allows these devices to ''fail'' to a known state under a
wide variety of fault conditions at the inputs.

•

Reduced Supply Current-35mA Max

•

Internal Hysteresis

ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, vcc ............................................ 7V
Output Sink Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Output Short Circuit Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 Sec
Common Mode Input Range ..................................... 15V
Differential Input Range ........................................ 25V
Failsafe Voltage ......................................... -0.3 to Vee
PLCC Power Dissipation, TA=25° C (Note 2) ................... 1000 mW
DIP Power Dissipation, TA=25° C (Note 2) ..................... 1200 mW
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . .. -65° C to +150° C
Lead Temperature (Soldering, 10 seconds) ...................... -300° C
Note 1: All voltages are with respect to ground, pin 14. Currents are positive in,
negative out of the specified terminal.
Note 2: Consult packaging section of Databook for thermal limitations and
considerations of package.

CONNECTION DIAGRAMS
DIL-28 (TOP VIEW)

PLCC-28 (TOP VIEW)
B- Ao A+ A- Vee Ho H+
Vee
Ho
H+
HGo
G+
G-

D+
Do
GND

B+

H-

Bo

Go

FS1

G+

C-

G-

FS2
Fo

C+

FS2

F+

Co

Fo

F-

D-

F+

Eo
E+
E-

D+ Do GND E- E+ Eo F-

1/94
6-18

UC5181C
DC ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = O°C to +70°C; Vee
= 5V ±S%,lnput Common Mode Range ±7V, TA=TJ.

PARAMETER

SYMBOL

DC Input Resistance
Failsafe Output Voltage

RIN
VOFS

TEST CONDITIONS
3V S IVINI<25V
Inputs Open or Shorted
Together, or One Input Open
and One Grounded

0>louT<8mAVFAILSAFE=OV
0~lou'Q-400jlA,

VFAILSAFE=Vee

Differential Input High
Threshold

VTL

VOUT= 0,45V,loUT= -440jlA (See Figure
1)

Differential Input Low
Threshold

VTL

VOUT = 0,45V, lOUT = 8 rnA (See Figure
1)

Hysteresis
Open Circuit Input Voltage
Input Capacitance
High Level Output Voltage
Low Level Output Voltage

VH
VIOC
CI

Fs=OV or Vee (See Figure 1)

45

VOH
VOL

VID = 1V, lOUT = -440 ~

2.7

los

Note 5

Icc
liN

4.75V SVeCS5.25V

Short Circuit Output
Current
Supply current
Input Current

Rs = 0 (Note3)
Rs = 500 Note 3)
Rs = 0 (Note 3)
Rs = 500 (Note 3)

UC5181C
MAX
MIN
7
3
0,45
2.7
50
-200
-400

lOUT = 4 mA
lOUT = 8 mA

VID = -1V (Note 4)

20

Other Inputs Grounded

VIN = +10V
VIH = -10V

Note 3: Rs is a resistor in series with each input.
Note 4: Measure after 100 ms wann up (at (J'C).
Note 5: Only 1 output may be shorted at a time and then only for a
maximum of 1 sec.
Note 6: The delays, either tPLH or tpHL, shall not val}' from receiver to
receiver by more than 35ns.

V

200
400
-50

mV
mV

140
75
20

mV
mV

IJF

0,4

V
V

0.45
100

rnA

35
3.25

rnA
rnA

VOUT
Fs=GND

- -

VIL 1 VI HI

k.Q

-3.25

Fs=Vcc

VH1_

UNITS

0

VIL2

I-- VH2
VIH2

VIN

Figure 1. VTL, VTH,VH Definition

AC ELECTRICAL CHARACTERISTICS:
PARAMETER

SYMBOL

Propagation Delay-Low to High
Propagation Delay-High to Low
Acceptable Input frequency

Vec
+O.5V
-O.SV

Vee=5V ±S%. TA=O°C to +70°C, Figure 2 TA=TJ.

tPLH
tPHL
fA

TEST CONDmONS
CL=50pF, VIN= ±SOO mV (Note 6)
CL=50pF, VIN= ±SOO mV (Note 6)
Unused Input Grounded, VIN= ±200 mV

IL

n
VFAllSAFE

Figure 2. AC Test Circuit

6·19

UC5181C
MIN
MAX
120
120
5.0

UNITS
ns
ns
MHz

UC5181C

APPLICATIONS INFORMATION
Failsafe Operation
These devices provide a failsafe operating mode to guard
against input fault conditions as defined in EIA422A and
EIA423A standardS. These fault conditions are (1) driver
in power-off condition, (2) receiver not interconnected
with driver, (3) open-circuited interconnecting cable, and
(4) short-circuited interconnecting cable. If one of these
four fault conditions occurs at the inputs of a receiver,

then the output of that receiver is driven to a known logic
level. The receiver is programmed by connecting the failsafe input to vee or ground. A connection to Vee provides
logic "1" output under fault conditions, while a connection to ground provides a logic "0". There are two failsafe
pins (FS1 and FS2) .on the UC5181C where each provides
common failsafe control for four receivers.

a

EIA232EN.28 I EIA423AN.10 DATA TRANSMISSION
EIA423AN.10

VH

Vcc

n
L

VL..J

VH-U
VL

1/8

UC5170C>e-+--------1I----l

'TIE TO
GROUND
FOR EIA232E!V:28
V FAILSAFE

EIA422AN.11 DATA TRANSMISSION

I

VH
VL

n
-.J

L

EIA422AIV .11
LINE
DRIVER

JL

I
I
I

+V
-V

I
I

+V --,
-V LJ

I

Vee

VH

JL

VL

~

+

!

VFAILSAFE

GENERAL LAYOUT NOTES
The drivers and receivers should be mounted close to the
system common ground point, with the ground reference
tied to the common point to reduce RFI/EMI.
Filter connectors or transzorbs should be used to reduce
the RFI/EMI, and protecting the system from static (ESD),
and electrical overstress (EOS). A filter connector or capacitor will reduce the ESD pulse by 90% typically. A cable dragged across a carpet and connected to a system
can easily be charged to over 25,000 volts. This is a metal to metal contact when the cable is connected to the

system (no reSistance), currents exceed 80 amps with
less than a nanosecond rise time. A transzorb provides
two functions, the device capacitance inherently acts as a
filter capacitor, and the device clamps the ESD and EOS
pulses which would pass through the capacitor and destroy the devices. The recommended transzorb for the
UC5180C and the UC5181C is P6KE22CA.
, Transzorb is a trademark of General Semiconductor
Industries.

UNITRODE CORPORATION
7 CONTINENTAL BLVD .• MERRIMACK, NH 03054
TEL. (603) 424-2410. FAX (603) 424-3460

6-20

~UNITROCE

UC5350
PRELIMINARY

CAN Transceiver
FEATURES

DESCRIPTION

•

Pin Compatible with PCA82C250
and DeviceNet, SDS, IS011898
Compatible

•

High Speed, up to 1Mbps

•

Differential Transmit to the Bus and
Receive from the Bus to the CAN
Controller

The UC5350 Control Area Network Transceiver is designed for industrial
applications employing the CAN serial communications physical layer
per ISO 11898 standard. The device is a high speed transceiver designed for use up to 1Mbps. Especially designed for hostile environments, this device features cross wire, loss of ground, over voltage, and
over temperature protections well as a wide common mode range.

•

At Least 110 Nodes Can Be
Connected

•

100V Transient Protection on the
Transmit Output

•

24V Supply Cross Wire Protection
on CANH and CANL

•

No Bus Loading When Powered
Down

•

Operates over -40°C to + 125°C

•

Unitrode DeviceNet 10#107

The transceiver interfaces the single ended CAN controller with the differential CAN bus found in industrial and automotive applications. It operates over the -7V to +12V common mode range of the bus and will
withstand common mode transients of -25V to + 18V as well as Schaffner tests. Performance features include high differential input impedance, a symmetrical differential signal driver and very low propogation
delay that improves bus bandwidth and length by reducing reflection and
distortion.
The transceiver operates over a wide temperature range, -40°C to
+125°C and is available in 8-pin SOIC and Dual-in-Line packages.

FUNCTIONAL TABLE (VCC = 4.5V to 5.5V)
Injluts
TXD
RS
0
0
1
0
HighZ
0
X
1

System Mode

Out!)uts

Output Mode

High Speed
High Speed
High Speed
Standby

VCANH - VCANL
1.SV to 3V
-120mV to +12mV
-120mV to +12mV
High Z

Dominant
Recessive
Recessive

RXD
0
1
1
o at Bus = Dominant
1 at Bus = Recessive

BLOCK DIAGRAM

r-----------

CANH

CANL

I
I

RS4J

I
I
TXD¢
I

4 RXD
TRANSMITTER

RECEIVER

I

I
I
L ___________ ~-~--------J
GND

VCC
UDG-96202

3/98

6-21

UC5350
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ............................ -{J.3V to 9V
TXD, RXD, VREF, RS ............... -{J.3V to VCC + 0.3V
CANL,CANH
OV < VCC < 5.5V........................ -8V to +36V
Non-Destructive, Non-Operative ............ -8V to +32V
Transient, Schaffner Test (Fig. 1) ......... -150 to +100V
Operating Temperature ................. -40°C to +125°C
Storage Temperature ................... -65°C to +150°C
Junction Temperature ................... -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ............. +300°C
Crosswire Protection Maximum VBLis ................ 30V
Bus Differential Voltage' ........................... 30V
Cross Wire Protection TA ................. -40°C to 125°C

Currents are positive into, negative out of the specified
terminal.
Consult Packaging Section of the Databook for thermal
limitations and considerations of packages.
"Refers to Figures 9, 10, 11, 12 and 13.

CONNECTION DIAGRAM
DIL-S, SOIC-S (Top View)
5V

N, D Package

r-0----,

~nF

TXD

RS

GND

CANH

I

VCC

CANL

I
CANL 6
I
I GND RS
I

RXD

VREF

II VCC
I

CANH 7

620

Lp_..J

lnF

See Figure 7 for Pulse Timin

UDG·96203-1

Figure 1. Schaffner Test

ELECTRICAL CHARACTERISTICS (Total Device) Unless otherwise stated, the device is disconnected from the bus
line·, VCC -- 4 5V to 5 5V·, 60il in parallel with 100pF load between CANH and CANL·, TA - -40°C to +125°C, TA - TJ

-

PARAMETER

TEST CONDITIONS

Supply Voltage
Supply Current

-

MIN

TYP

4.5
Dominant, TXD = 1V

MAX

UNITS

5.5

V

70

mA

Recessive, TXD = 4V

9

13

mA

Standby, RS = 4V

1

1.5

mA

5

ItA

-10

RS Input Current
RS Voltage Input = Logic 1

Standby

RS Voltage Input = Logic 0

High Speed

Transmitter Voltage Input = Logic 1

Transmitter Output Recessive

Transmitter Voltage Input = Logic 0

Transmitter Output Dominant

Transmitter Current Input at Logic 1

TXD=4V

Transmitter Current Input at Logic 0

TXD= lV

Receiver Voltage Output = Logic 1

RXD = -1001lA, TXD = 4V

Receiver Voltage Output = Logic 0

RXD = lmA, TXD = lV

0.75

1.0

RXD = 10mA, TXD = lV

1.2

1.5

V

0.75VCC

V
0.3VCC

O.7VCC

V
V

-30

0.3VCC

V

30

ItA

30

IlA

VCC-l.0

V
V

CANH, CANL Input Resistance

No Load, TXD = 4V

30

43

54

k.Q

60

86

Differential Input Resistance

No Load, TXD = 4V

108

k.Q

CANH, CANL Input Capacitance

(Note 1)

20

pF

Differential Input CapaCitance

(Note 1)

10

pF

Reference Output Voltage

VREF = ±501lA

0.55VCC

V

Note 1: Guaranteed by design. Not .100% tested in production.

6-22

0.45VCC

UC5350
ELECTRICAL CHARACTERISTICS (DC Parameters For Recessive State) Unless otherwise stated, the
device is disconnected from the bus line; 60n in parallel with 100pF load between CANH and CANL.
PARAMETER

TEST CONDITIONS
No Load, TXD = 4V (Figure 2)

VCANH,VCANL
Differential Output Transmitter
(VCANH - VCANL)

No Load, TXD = 4V (Figure 2)
Common Mode Range = -7V to +12V,
TXD = 4V, CANH, CANL Externally Driven
I(Figure 3)

Differential Input Receiver

Differential Input Resistance

No Load

CANH, CANL Input Resistance

3V,------------------------,~

MIN

MAX

UNITS

3
50

mV

-1

0.40

V

60
15

50

kn

2
-500

TYP
2.5
0

V

k.Q

12V,----------------.+---------r~

11V

BUS CMR
(MAX)

2.5V
VCANH

"
BUS CMR
-6.6V

2.05V

-7 V

2V~--~---------L----------~

UDG·96204

VCANH

(MIN)

+

UDG.96205

Valid voltage range of VCANH for sensing dominant bus state
as VCANL varies over bus common range mode.

Valid output of CANH, CANL during recessive state transmission. TXD = LOGIC 1

TXD=LOGIC1

Figure 2. Recessive State Voltage Diagram

Figure 3. Recessive State Voltage Diagram

6-23

UC5350

ELECTRICAL CHARACTERISTICS (DC Parameters For Dominant State) Unless otherwise stated, the device
is disconnected from the bus line; 60n in parallel with 100pF load between CANH and CANL. VCC = 4.75V to 5.5V
PARAMETER
CANH Output Voltage (VCANH)

TEST CONDITIONS
TXD = 1V (Figure 4)

2.75

CANL Output Voltage (VCANL)

TXD = 1V (Figure 4)

0.50

Differential Output Transmitter (VCANH - VCANL) TXD = 1V (Figure 4)

1.5

Differential Input Receiver (VOIFF(O»

MIN

TYP

UNITS

1.1

MAX
4.5
2.25

2

3

V

V
V

Common Mode Range = -2 to +7V, TXD = 4V,
CANH, CANL Externally Driven (Figure 5)

0.9

5

V

Common Mode Range = -7 to +12V, TXD = 4V,
CANH, CANL Externally Driven (Figure 5)

1.0

5

V

12V

sv
4.SV

3.SV

2.7SV

SV

~4~r1i]~~~~-~- - - - ~ -t. V3.6 =1.SV (MIN)

2.2SV

1.SV

-------------i--I
t. vr =
3V (MAX)

OV
-2V

VCANL (MAX)

BUS CMR (MIN)
o.SV

+

--6.1V
-7V - ' < - - - - - - - - - - - - - - - - - - ' ' - - - - - '

VCANL(MAX)
.......... veANL (MIN)

UDG-97161
UDG·97160

Valid voltage range of VCANH for sensing recessive bus
state as VCANL varies over bus common mode range.
TXD=LOGIC 1

Valid voltage range of VCANH for sensing dominant bus
state as VCANL varies over bus common range mode.
TDX=LOGICO

Figure 4. Dominant State Voltage Diagram

Figure 5. Dominant State Voltage Diagram

6-24

UC5350

Unless otherwise stated, the device is disconnected from the bus line; 60n in

TRANSMITTER CHARACTERISTICS parallel with 100pF load between CANH and CANL

MIN

TVP

MAX

UNITS

Dominant Mode

TEST CONDITIONS

1.5

2

3

V

Recessive Mode

-500

50

mV

PARAMETER
Differential Output Transmitter
(VCANH - VCANL)
Delay From TXD to Bus Active TON (TXD)

(Figure 6)

45

65

ns

Delay From TXD to Bus Inactive TOFF (TXD)

60n Across CANH and CANL (Figure 6)

40

80

ns

Unless otherwise stated, the device is disconnected from the bus line; 60n in
parallel with 100pF load between CANH and CANL

RECEIVER CHARACTERISTICS

TEST CONDITIONS

PARAMETER
Differential Input Receiver (VCANH - VCANL)

MIN

Dominant Mode, TXD = 4V

TVP

MAX

UNITS

0.4

V

V

0.9

Recessive Mode, TXD = 4V
Differential Input Hysteresis

TXD =4V

Delay From Bus to RXD (TON)

Inactive to Active Bus (Figure 6)

55

ns

Delay From Bus to RXD (TOFF)

Active to Inactive Bus, 60n Across CANH and
CANL (Figure 6)

145

ns

Delay From Bus to RXD (TOFF)

TA = -25°C to 85°C Active to Inactive Bus,
60n Across CANH and CANL (Figure 6)

75

ns

0.7 VCC

TXD\

0.3 VCC (MAX)

.... [TON (TXD)['"
VOIFF

to.

~I

TXD

.... TOFF(TXD)

9V

~ ~ ~ ~~ ~

(MIN)

25n •

.... 1

--1----

TOFF (RXD)I'"

0.3VCC

mV

0.9VSf\

JVVLJ V~_J ~Y_~C jL___\vs

I'"
\0.5V

.

..:...::.c-'--------'
.... ITON (RXD)'"
RXD

TR_TF_

150

0.7VCC

__ I- ,,§!,!D

~
5ns

100

I1S

10ms

90ms

100ns

~----~~-~

UDG·9620B

Figure 6. Transceiver AC Response

Figure 7. Timing Diagram for Schaffner Tests

MaQn itud e SiPeCI"f"Icat"Ions f or
ISO
DP7637/1
Up to 150V

6-25

DIN 40839-1
(Draft)
Up to 150V

VS
Schaffner
NSG500C/506C
40Vto 200V

UC5350

+V8US

CANH

600

60n
CANL
I
I

GND

I

GND

----~::--~

GND

f----+-

6
I

----..!

---- 2

CANL

Figure 8. Normal Connection

Figure 9. Crosswire No.1

INPUT

INPUT
CANH

CANL

----- 3

I

CANH 7

r----I-

CANL

r----I-

I
I
I
I
I
I

60n
6

vee

I
I

GND

+VBUS

GND

CANH 7

r----I-

CANL

1----1-

600

I
I

6

+VBUS

I

:

GND

L ____ 2

:

----..!
CANH

Figure 10. Crosswire No.2

Figure 11. Crosswire No.3

INPUT

I

78L05

II-C_A_N_L_ _ _~

I

_____-W-!_~~T:~T

I
I

I

CANH 7

+VBUS

vee

I
I

f------i-

CANH 7

I
I

6

60n

CANH

f----

I
I

I

I-C::A.::.N=L,--~

>

I

I

I

CANL

:>

I

CD.f---'-'---I

I

I

CANL

6

+VBUS

I

:

GND

:

L----T~:D--~
Figure 12. Crosswire No.4

Figure 13. Crosswire No.5

UNITRODE CORPORATION
7 CONTINENTAL BLVD .• MERRIMACK, NH 03054
TEL (603) 424-2410. FAX (603) 424-3460

6-26

~UNITRODE

UC5351
ADVANCE INFORMATION

CAN Transceiver with Voltage Regulator
FEATURES

•

DeviceNet, SDS, ISO 11898
Compatible

•
•

High Speed, up to 1Mbps

•

- 25V to + 18V Protection on
CANH and CANL

•
•

Loss of Ground Protection

•
•
•

DESCRIPTION
The UC5351 Control Area Network (CAN) Transceiver is designed for industrial applications employing the CAN serial communications physical
layer per the ISO 11898 standard. The device is a high speed transceiver
plus voltage regulator designed for use up to 1Mbps. Especially designed
for hostile environments, this device features cross-wire and over voltage
protection, thermal shutdown, a wide common mode range, and loss of
ground protection.

Differential Transmitter and
Receiver bus interface

The UC5351 CAN Transceiver interfaces the single ended CAN Controller
with the differential CAN Bus found in industrial and automotive applications. Performance features include high input impedance, a symmetrical
differential signal driver, and low propagation delay that improve bus bandwidth and length, while reducing reflection and distortion. Reduced reflection and distortion results in increases of effective bus length and
bandwidth.

High Differential Input
Impedance
Supports 110 nodes or more
Operates over -25°C to +85°C

The on-board regulator permits direct connection to a +8V to 24V power
bus and supply power to the transceiver with 40mA of reserve ouput current to power external components.

Unitrode DeviceNet 10#107

The transceiver operates over a wide temperature range, -25°C to 85°C,
and is available in a16-pin power SOIC package.

FUNCTIONAL TABLE (VLlNE = 8V TO 28Vl
In uts
Sytem Mode
TxD
0
1
High Z

X

Rs
0
0
0
1

Outputs

Output Mode

High Speed
Hiah Soeed
High Speed
Standby

VCANH - VCANL
1.5Vto 3V
-120mV to +12mV
-120mV to +12mV
high Z

Dominant
Recessive
Recessive

RxD
0
1
1
A & "0" @ Bus = Dominant
A & "0" @ Bus = Recessive

BLOCK DIAGRAM
AXC

TxO

BYPASS

HIS

HIS VREG_OUT

NfC

VLlNE

----I
I

I

IN

I
I
I
I
I
I
I
I
I

I

+5VOUT

I
I
I

I

_A

-- 1 --- 2 ---- 3
AS
VREF
CANL

--@--0--HIS

HIS

llll

I

i

--------=----+-ch-*-cb-----1

6
CANH

GND

REG_GND

UDG-97194

1/98

6-27

UC5351
-',

ABSOLUTE MAXIMUM RATINGS
Supply Voltage .......................... -o.3V to +36V
TXD, RXD, VREF, RS ............... -0.3V to VCC +0.3V
CANL, CANH BV < VLlNE< 2BV .............. -BV to +36V
Non-Destructive, N<;m-Operative .............. -BV to +32V
Transient, Schaffner Test (Figure 1) ........ -150V to + 1OOV
Operating Temperature .................. -25°C to +B5°C
Storage Temperature ................... -65°C to +150°C
Junction Temperature ................... -55°C to +150°C
Lead Temperature (Soldering, 10 sec) ............. +300°C
Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of the Databook for thermallimitations and consideration of packages.

CONNECTION DIAGRAM
SOIC-16 (TOP VIEW)
DP Package

,-CE-----,
VLlNE C A N H : E :lnF
I

62W

I

CANL
REG

3
I

lnF

: GND GND RS :

'F

See Figure 7 for pulse timing.
'Warning: HIS pins are connected to the substrate which must
float, attach al/ four pins to at least 0.5 square inch of etch.
DO NOT ATTACH TO GROUND!

ELECTRICAL CHARACTERISTICS (Total Device) Unless otherwise stated, the device is disconnected from the bus
line; VLlNE = 10V; 10(VREG_OUT) = --40mA; CVLlNE=0.33I1F; CVREG_OUT = 0.1I1F; CSYPASS = 0.1I1F; 60n in parallel with 100pF
between CANH and CANL; TJ =--25°C to + 150°C. VR = VREG OUT Voltage.
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Section
Supply Voltage (VLlNE)
Supply Current (VLlNE)

Output Voltage (VREG_OUT)

B
Dominant, TXD = 1V; 10(VREG OUT) = 0

Load Regulation (VREG OUT)
Ripple Rejection (VREG OUT)

V
mA

Recessive, TXD = 4V; 10 (VREG OUT) = 0

12

17

mA

Standby, RS = 4V; 10 (VREG OUT) = 0

6.5

9

mA

5

5.2

V

5.25

V

90

mV

60

mV

4.B

TJ = 25°C
1 mA < 10 (VREG_OUT) < 40mA;
BV < VLlNE < 2BV

Line Regulation (VREG OUT)

2B
75

4.75

TJ =.25°C, BV < VLlNE < 2BV
. T J = 25°C, 1mA < 10 (VREG OUT) < 40mA
f=120Hz, BV < VLlNE < 16V

RS Input Current

47
-5

RS Input Voltage = Logic 1

Standby

RS Input Voltage = Logic 0

High Speed

dB
5

(0.75 )eVR

V
(0.3)eVR

6-28

!1A
V

UC5351

ELECTRICAL CHARACTERISTICS (Total Device) Unless otherwise stated, the device is disconnected from the bus
line; VLlNE = 10V; lo(VREG_OUT) = -40mA; CVLlNE=0.33IlF; CVREG_OUT = 0.1IlF; CBVPASS = 0.1IlF; 60n in parallel with 100pF
between CANH and CANL' TJ -25°C
to + 150°C VR - VREG OUT Voltage
PARAMETER

TEST CONDITIONS

MAX

UNITS

0.3

V

30

IlA

30

IlA
V

RXD= 1mA

(0.2)-VR

V

RXD = 10mA

1.5

V

Transmitter Voltage Input = Logic 1

Transmitter Output Recessive

Transmitter Voltage Input = Logic 0

Transmitter Output Dominant

Transmitter Current Input at Logic 1

TXD=4V

Transmitter Current Input at Logic 0

TXD= 1V

Receiver Voltage Output = Logic 1

RXD = -1 OOIlA

Receiver Voltage Output = Logic 0

MIN

TVP

(0.7)-VR

V

-30
(0.8)-VR

CANH, CANL Input Resistance

No Load

34

43

54

kn

68

86

Differential Input Resistance

No Load

108

kn

CANH, CANL Input Capacitance

(Note 1)

20

pF

Differential Input Capacitance

(Note 1)

10

pF

Reference Output Voltage

I (VREF) = ±5OIlA

(0.55)-VR

V

(0.45)-VR

Note: Guaranteed by design. Not 100% tested in production.

ELECTRICAL CHARACTERISTICS (DC Parameters for Recessive State) Unless otherwise stated, the device
is disconnected form the bus line', 60n in parallel with 100pF load between CANH nad CANL
MIN

TVP

MAX

VCANH, VCANL

PARAMETER

No Load, TXD = 4V (Figure 2)

TEST CONDITIONS

2

2.5

3

V

Differential Output Transmitter
(VCANH, VCANL)

No Load, TXD = 4V (Figure 2)

-500

0

50

mV

Differential Input Receiver

UNITS

-1

0.4

V

Differential Input Resistance

No Load

68

108

kn

Differential Input Receiver

Common Mode Range =-7 V to +12V,
TXD = 4V, CANH, CANL Externally Driven
(Figure 3)

-1

0.40

V

Differential Input Resistance

No Load

68

108

kn

3V,-------------------------~~--_,

12V .,-----,.--------------------,-,.

VCANH
(V6)

""

11V

(MAX)
"

-1

VCANL
(V3)

---1

VCANH

VDIFF(R) = 1V

------1------------d V3.6 = -SOOmV
. ""
d V3.6= SOmV
2.0SV

--7'-7'

VDIFF(R) = "'0.4';.V____
(MAX)

2.SV

~---. (MAX)

BUstMR

T

(MIN)

BUSCMR

-6.6V

(MIN)

~~~----------~!~

2V~-----------------L------------~

Valid voltage range of VCANH for sensing recessive bus
state as VCANL varies over bus common mode range.
TXD = LOGIC 1

Valid output of CANH, CANL during recessive state transmission. TXD = LOGIC 1

Figure 2. Recessive State Voltage Diagram

Figure 3. Recessive State Voltage Diagram
6-29

UC5351

ELECTRICAL CHARACTERISTICS
(DC Parameters for Dominant State)

Unless otherwise stated,the device is disconnected from the bus line; 60n
in parallel with 100pF load between CANH and CANL.

MIN

TVP

MAX

UNITS

CANH Output Voltage (VCANH)

PARAMETER

TXD = 1V (Figure 4)

TEST CONDITIONS

2.75

3.5

4.5

V

CANL Output Voltage (VCANL)

TXD = 1V (Figure 4)

0.5

1.5

2.25

V

Differential Output Transmitter (VCANH - VCANL)

TXD = 1V (Figure 4)

1.5

2

3

V

Differential Input Transmitter (VOIFF(O»

Common Mode Range = -7V to +12V;
TXD = 4V, CANH, CANL Externally Driv~n
(Figure 5)

0.9

5

V

12V

SV
4.5V

3.5V

5V

3.0V

2.25V

OV
-2V

1.5V
BUS CMR (MIN)

O.SV

-7V~------------------------~~

........... VCANL (MIN)

Valid output of CANH, CANL during dominant state transmission as CANL is varied over its minimum to maximum
range. TXD = LOG/CO.

Valid voltage range of VCANH for sensing recessive bus
state as VCANL varies over bus common mode range.
TXD = LOG/CO.

Figure 4. Dominant State Voltage Diagram

TRANSMITTER CHARACTERISTICS

Figure 5. Dominant State Voltage Diagram

Unless otherwise stated, the device is disconnected form the bus line; 60n
in parallel with 100pF load between CANH and CANL

PARAMETER
Differential Output Transmitter (VCANH - VCANL)

-7V

-6.1V

VCANL(MAX}

MIN

TVP

MAX

Dominant Mode

TEST CONDITIONS

1.5

2

3

V

Recessive Mode

-500

50

mV

UNITS

Delay From TXD to Bus Active TON (TXD)

(Figure 6)

75

nS

Delay From TXD to Bus Active TOFF (TXD)

60n Across CANH and CANL (Figure 6)

75

nS

RECEIVER CHARACTERISTICS

Unless otherwise stated, the device is disconnected form the bus line; 60n
in parallel with 100pF load between CANH and CANL

PARAMETER
Differential Input Transmitter (VCANH - VCANL)

TEST CONDITIONS
Dominant Mode, TXD = 4V

MIN

TVP

MAX

0.9

UNITS
V

Recessive Mode, TXD = 4V

150

Differential Input Hysteresis

TXD =4V

150

Delay from Bus to RXD (TON)

Inactive to Active Bus (Figure 6)

150

nS

Delay from Bus to RXD (TOFF)

Active to Inactive Bus; 60n Across CANH
and CANL (Figure 6)

150

nS

6-30

mV
mV

UC5351

~ ~ ~ ~~ ~

0.7 vee (MIN)

TXil\

0.3 vee (MAX)

....ITON (TXD)I'"

VOIFF

~I
.... TOFF (TXD)

fO.9V

--t----

....1 TOFF (RXD)I'"
0.7vee

0.3vee

- - r-

100
I1s

10ms

90ms

I+-----~-~

Figure 6. Tranceiver AC Response
Magnitude Specifications for Vs
ISO
DIN-40839-1
(Draft)
DP7637/1
Up to 150V
Up to 150V

0.9VSf\

JVVl_J Vl_J lY~c jL__ ~vs

I'"
\0.5V

.=:.:.....---....J
....ITON (RXD) ...
RXD

TXD TR_TF_ 25ns

-..9!'i D ~
5ns
100ns

Figure 7. Timing Diagram for Schaffner Tests

Schaffner
NSG500C/506C
40Vto 200V

UNITRODE CORPORATION
7 CONTINENTAL BLVD.· MERRIMACK. NH 03054
TEL. (603) 424-2410· FAX (603) 424-3460

6-31

Selection Guides - Table of Contents

-

[1:JJ

Interface Products
SCSI
Multimode / LVD SCSI Active Terminators ....................................... 7-3
Single Ended SCSI Active Terminators .......................................... 7-4
Special Functions Circuit. .................................................... 7-6
Bus Bias Generators
Special Functions .......................................................... 7-6
Hot Swap Power Manager
Hot Swap Power Managers ................................................... 7-7
Special Functions .......................................................... 7-8
Drivers / Receivers
Interface Drivers, Receivers ................................................. 7-10
Transceivers
Interface Transceivers ...................................................... 7-10

Nonvolatile Products
Static-RAM Nonvolatile Controllers ............................................ 7-11
Real-Time Clocks ......................................................... 7-12
Real-Time Clock Cross-Reference ............................................ 7-13
Nonvolatile Static RAM ..................................................... 7-14
Nonvolatile Static RAM Cross Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 7-15

Portable Power Products
Battery Charge Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............. 7-16
bq2002 Family ............................................................ 7-18
bq2004 Family ............................................................ 7-20
Li-Ion PWM Charge IC ..................................................... 7-21
Battery Capacity-Monitoring ................................................. 7-22
bq2011 Family ............................................................ 7-23
Battery Management Modules ............................................... 7-24
Pack-Protection and Supervisory ............................................. 7-25
Power Management ....................................................... 7-26
Linear Regulation ......................................................... 7-27
Back-Light Controller ....................................................... 7-30
IrDA .................................................................... 7-31

7-1

Selection Guides - Table of Contents

-

[1JJ

Power Supply Control Products
PWMControl
Current Mode Controllers ................................................... 7-31
Dedicated DC/DC Controllers ...........................•.................... 7-43
Power Controllers . . . ...................................................... 7-46
Power Support ............................................................ 7-48
Post Regulation Controllers .................................................. 7-49
Secondary Side Control .................................................... 7-50
Soft Switching Controllers ................................................... 7-51
Voltage Mode Controllers ................................................... 7-55
Power Factor Correction
Power Factor Correction Products ............................................. 7-61
Linear Regulation
Linear Controllers ......................................................... 7-64
Low Dropout Linear Regulators ............................................... 7-65
Special Function .......................................................... 7-66
Power Drivers
Power and FET Drivers ..................................................... 7-67
Power Supply Support
Feedback Signal Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-70
Load Share Controllers ..................................................... 7-71
Diode Array/Bridges ....................................................... 7-71
Supervisory and Monitor Circuits' ............................................. 7-72
Motion Control
Motor Products ........................................................... 7-73
DC Motor Controllers ....................................................... 7-73
Linear Power Amplifier Products .............................................. 7-74
Phase Locked Frequency Controllers .......................................... 7-74
Stepper Motor Controllers ................................................... 7-75
Special Functions
Current Sensors .......................................................... 7-76
Lighting Controllers ........................................................ 7-76
Ring Generator Controllers .................................................. 7-77
Sensor Drivers ............................................................ 7-78
Serial DACs .............................................................. 7-78

7-2

-

[1JJ

Interface (IF) Selection Guides
SCSI
Multimode / LVD SCSI
Active Terminators
Channels
Channel Capacitance
Termination Impedance
Disconnect High or Low
Termpwr Voltage Range
Supports Active Negation
SCSI Hot Plug Current
Type LVD or SE I LVD
Page Number

Mullimode / LVD SCSI
Active Terminators
Channels
Channel Capacitance
Termination Impedance
Disconnect High or Low
Termpwr Voltage Range
SCSI Hot Plug Current
Type LVD or SE I LVD
Page Number

UCC5628+
14
4
singlell0,
Differential 105,
Common Mode
150

UNITRODE PART NUMBER
UCC5630
UCC5632
UCC5638+
9
4
singlell0,
Differential 105,
Common Mode
150

9
4
Single 110,
Differential 105,
Common Mode 150

15
4
Single 110,
Differential 105,
Common Mode
150

H

H

H

H

2.7 - 5.25

2.7 - 5.25

2.7 - 5.25

2.7 - 5.25

UCC5639+
15
4
Single 110,
Differential 105,
Common Mode
150
L
2.7 - 5.25

Y

Y

Y

Y

Y

<10nA
LVD/sE
IF/3-7S

<10nA
LVD / sE
IF/3-S3

<10nA
LVD/sE
IF/3-93

<10nA
LVD/SE
IF/3-94

<10nA
LVD/sE
IF/3-99

UNITRODE PART NUMBER
UCC5646

UCC5640+

UCC5641+

9
3
Differential 105,
Common
Mode 150
H
2.7 - 5.25
<10nA
LVD
IF/3-104

9
3
Differential 105,
Common
Mode 150
L
2.7 - 5.25
<10nA
LVD
IF/3-10S

+ New Product

7-3

27
3
Differential 105,
Common
Mode 150
H
2.7 - 5.25
<10nA
LVD
IF/3-112

-Odl

Interface (IF) Selection Guides
SCSI (cont.)
Multimode / LVD SCSI
Active Terminators
Channels
Channel Capacitance
Termination Impedance
Diff B Input filter
Disconnect High or Low
Termpwr Voltage Range
Supports Active Negation
SCSI Hot Plug Current
Type LVD or SEI LVD
Page Number

Single Ended SCSI
Active Terminators
Channels
Channel Capacitance
Termination Impedance
Disconnect High or Low
Termpwr Voltage Range
Supports Active Negation
SCSI Hot Plug Current
Type SE, LVD or SE I LVD
Page Number

UCC5510+
9
4
Single110,
Differential 105,
Common Mode
150
N
NlA
2.7 - 5.25
Y
<10nA
LVD/SE
IF/3-5

UC5601
18
10
110
H
4-5.25
N
<10nA
SE
IF/3-9

UNITRODEPARTNUMBER
UCC5630A
UCC5680
UCC5672+
9
4
Single110,
Differential 105,
Common Mode
150
N
H
2.7 - 5.25
Y
<10nA
LVD/SE
IF/3-87

9
4
Single110,
Differential 105,
.Common Mode
150
Y
H
2.7 - 5.25
Y
<10nA
LVD / SE
IF/3-120

9
4
Single 110,
Differential 105,
Common Mode
150
Y
H
2.7 - 5.25
Y
<10nA
LVD
IF/3-121

UNITRODE PART NUMBER
UC5602
UC5604
UC5603
18
11
110
H
4-5.25
N
<10nA
SE
IF/3-13

+ New Product

7-4

9
6
110
H
4-5.25

Y
<10nA
SE
IF/3-18

9
9
110
H
4- 5.25
N
<10nA
SE
IF/3-22

UC5605
9
4
110
L
4-5.25

Y
<10nA
SE
IF/3-26

[1:JJ

-

Interface (IF) Selection Guides
SCSI (cont.)
Single Ended SCSI
Active Terminators
Channels
Channel Capacitance
Termination Impedance
Disconnect High or Low
Termpwr Voltage Range
Supports Active Negation
SCSI Hot Plug Current
Type SE, LVD or SE I LVD
Page Number

Single Ended SCSI
Active Terminators
Channels
Channel Capacitance
Termination Impedance
Disconnect High or Low
Termpwr Voltage Range
Supports Active Negation
SCSI Hot Plug Current
Type SE, LVD or SE I LVD
Page Number

UNITRODE PART NUMBER
UCC5606

UC5607

UC5608

UC5609

UC5612

9
1.8
110&2500
L
2.7 - 5.25

18
8
110
2L
4- 5.25

18
6
110
H
4-5.25

18
6
110
L
4-5.25

9
4
110
H
4-5.25

Y

Y

Y

Y

Y

<10nA
SE
IF/3-30

<10nA
SE
IF/3-34

<10nA
SE
IF/3-37

<10nA
SE
IF/3-40

<10nA
SE
IF/3-43

UC5613
9
3
110
H
4-5.25

UNITRODEPARTNUMBER
UCC5614
UCC5617
UCC5618

UCC5619

18
2.5
110
L
4-5.25

27
3
110
L
4-5.25

9
1.8
110&2500
H
2.7 - 5.25

18
2.5
110
H
4-5.25

Y

Y

Y

Y

Y

<10nA
SE
IF/3-47

<10nA
SE
IF/3-51

<10nA
SE
IF/3-55

<10nA
SE
IF/3-59

<10nA
SE
IF/3-63

+ New Product

7-5

-

[1JJ

Interface (IF) Selection Guides
SCSI (cont.)
Single Ended SCSI
Active Terminators
Channels
Channel Capacitance
Termination Impedance
Disconnect High or Low
Termpwr Voltage Range
Supports Active Negation
SCSI Hot Plug Current
Type SE, LVD or SE I LVD
Page Number

Special Functions Circuit
Part Name

Description

Page Number

UCC5620
27
3
110
H
4-5.25
Y
<10nA
SE
IF/3-66

UNITRODE PART NUMBER
UCC5621
UCC5622
27
3
110
Split Low
4-5.25
Y
<10nA
SE
IF/3-70

27
3
110
Split High
4-5.25
Y
<10nA
SE
IF/3-74

UNITRODE PART NUMBER
UCC5661
Ethernet Coaxial Impedance
Monitor
Contains all the Functions
Required to Monitor Ethernet
Coaxial Systems and is
Compatible with IEEE 802.3,
10Base5,10Base2,and
10BaseT
IF/3-112

+ New Product

Bus Bias Generators
Special Functions
Bus Standard
Sink / Source Current
Page Number
+ New Product

UC382
GTL/BTL
Pgm/3A
PS/4-2

UNITRODEPARTNUMBER
UC385
UC560
UCC561+
GTL/ BTL
Pgm/5A
PS/4-8

7-6

UC563+

VME/VME64
SCSI-1,2,3
SPI-2,3
300mA / -750mA 200mA / -200mA 475mA / -575mA
IF/4-3
IF/4-7
IF/4-10

-

[1D

Interface (IF) Selection Guides
Hot Swap Power Managers
Hot Swap
Power Managers
Voltage Range
Current Range
Integrated Power FET
RDSon
Programmable Fault Threshold
Programmable Time Delay
Latched Fault Mode
Average Power Limiting
Application / Design Note
Available Package
Page Number

Hot Swap
Power Managers
Voltage Range
Current Range
Integrated Power FET
RDSon
Programmable Fault Threshold
Programmable Time Delays
Latched FauH Mode
Average Power Limiting
Application I Oesign Note
Available Package
Page Number
+ New Product

UNITRODE PART NUMBER
UCC3912
3V to 8V
OAt03A
Y
1S0mQ
Y
Y
N
N/A
ON-S8, ON-S8,
U-1S1
TSSOP, SOIC or
POIP
IF/S-9

UCC3916

UCC3913

UC3914

-10.SVto
External
SVto35V
Limitation
Externally LimHed Externally Limited
N
N
N/A
N/A
Y
Y
Y
Y
Y
Y
Y
Y
ON-S7
SOICor POIP

SOICor POIP

IF/S-1S

IF/S-23

UCC3915

UCC39151

7Vto 1SV

7V to 1SV

OA to 3A
OAt03A
Y
Y
1S0mQ
1S0mQ
Y
Y
Y
Y
N
N
N/A
N/A
ON-S8, ON-68,
ON-S8, ON-S8,
U-1S1
U-1S1
TSSOP, SOIC or TSSOP, SOIC or
POIP
POIP
IF/S-37
IF/S-42

UNITRODEPARTNUMBER
UCC3918
UCC3917+

UCC39161

4VtoSV

4VtoSV

-1.8A to -1.SA
Y
220mQ
N
Y
N
NlA

-1Ato-O.7A
Y
220mQ
N
Y
N
N/A

SOICor POIP
IF/S-47

SOICor POIP
IF/S-SO

7-7

10V to External
Limitation
Externally Limited
N
N/A
y
Y
Y
Y
ON-98
SOICorPOIP
IF/S-S3

UCC3919

3VtoSV

3V to 8V

OA to 4A
Y
SOmQ
y

Externally Limited
N
N/A
y

Y
N
N/A
ON-87
SOICor POIP
IF/S-S1

Y
y
Y
DN-9S
SOICor PDIP
IF/S-S8

-

0:dJ

Interface (IF) Selection Guides
Hot Swap Power Managers {cant.}
Hot Swap
Power Managers
Voltage Range
Current Range
Integrated Power FET
ROSon
Programmable Fault Threshold
Programmable Time Delay
Latched Fault Mode
Average Power Limiting
Application I Design Note
Available Package
Page Number

Special Functions

UNITRODE PART NUMBER
UCC3921

UCC3995+

UCC3996+

-10.5Vto
2.75V to 13.6V
External
2.75V to 5.5V
Two Supplies
Limitation
Sequenced
Extemally Limited Externally Limited Externally Limited
N
N
N
NlA
N/A
NlA

Y
y
Y
y

Y
y

SOICor PDIP

TSSOP or SOIC

IF/5·78

IF/5·98

UCC3831

N
y

Y
y
Y
y
TSSOP, SOIC or
PDIP
IF/5·100

UNITRODE PART NUMBER
UCC38531
UCC39811 +
UCC3981+

Part Name

Universal Serial
Bus Power
Controller

Universal Serial
Bus Power
Controller

Universal Serial
Bus Power
Controller

Description

Powers Four 5V
Peripherals and
One 3.3V USB
Controller

Powers Four 5V
Peripherals and
One3.3V USB
Controller

Powers Four 5V
Peripherals and
One 3.3V USB
Controller

SOICor PDIP

SOIC orPDIP

SOICorPDIP

SOICorPDIP

IF/5·3

IF/5·6

IF/5·88

IF/5·91

UCC3985+

Universal Serial
Bus Power
Controller

CompactPCI
Hot Swap Power
Manager
Fully CompactPCI
Compliant. Four
Powers Four 5V
Channels for
Peripherals and
Individual Control
One 3.3V USB of Four Supplies
Controller
12V, -12V, 5V,
and3.3V

Application I Design Note
Available Package
Page Number
+ New Product

7-8

TSSOP, SOIC or
PDIP
IF/5·94

-Odl

Interface (IF) Selection Guides
Drivers I Receivers Transceivers
Interface
Drivers, Receivers
Drivers
Receivers
Power
EIA232/ V.28
EIA423/V.10
EIA422/ V.11
V.35
Appletalk
Page Number
+ New Product

UNITRODE PART NUMBER
UC5170C
8

UC5171
8

UC5172
8

±10V
Y
Y
N
N
N
IF/6·3

±10V
Y
Y
N
N
N
IF/6·7

±10V
Y
Y
N
N
N
IF/6·11

UC5350
1
1
+5V
Y
y
y

UC5351+
1
1
+5Vto24V
Y
y
y

IF/6-21

IF/6·27

UC5181C

8
+5V
Y
Y
Y
Y
N
IF/6·15

8
+5V
Y
Y
Y
Y
Y
IF/6·18

UNITRODE PART NUMBER

Interface Transceivers
Drivers
Receivers
Power
Control Area Network
Device Net
SDS
Page Number
+ New Product

UC5180C

7-9

-

Nonvolatile SRAMs and RTCs (NV) Selection Guides

Unitrode nonvolatile controllers provide power monitoring, write-protection, and 'supply switching to convert standard
SRAM and a backup battery into a reliable, predictable. nonvolatile memory. The nonvolatile ccmtroller modules are
complete battery-backup solutions including an encapsulated,130mAh lithium cell that is i~olated until power is applied.
~

Power monitoring and switching for 3V
battery-backup applications

~

5V Vee operation

~

Automatic write-protection during
power-up/power-down cycles

~

Automatic switching from Vee to first backup
battery and from first backup battery to second
backup battery

~

Battery interhally isolated until power is first
supplied

~

Industrial temperature range available

Static-RAM Nonvolatile Controller Selection Guide
SRAM
Banks
Controlled

Battery
Monitor
Outputs

Reset
Output

2

.,I

81 NDIp, NSOIC
16/NSOIC

bq2201

NV/3-3

160mA

161 NDIP, NSOIC

bq2202

NV/3-11

160mA

161 NDIp, NSOIC

bq2203A

NV/3~19

160mA

16 I NDIP, NSOIC

bq2204A

NV/3-27

160mA

12 1 DIP module

bq2502

NV/3-35

160mA
.,I
.,I

4
2

Page
Number

Pins I Package

1
2

Part
Number

lOUT

(Typ,)

.,I

7-10

Nonvolatile SRAMs and RTCs (NV) Selection Guides

Static-RAM Nonvolatile Controller Cross-Reference
Unitrode

Dallas Semiconductor

Notes:

OS1210

bq2201 PN 1, 2

OS1210S

bq2201S 1,2

OS1218

bq2201 PN 1,2

OS1218S

bq2201SN 1,2

OS1221

bq2204APN 1,3

OS1221S

bq2204ASN 1,3,4

1.

Unitrode's bq2201 and bq2204A do not incorporate a "check battery status" function.

2.

Unitrode's bq2201 pins THS and BC2 should be tied to Vss.

3.

Optional "security feature" OS1221 pins are no-connect on the bq2204A.

4.

Unitrode's bq2204ASN is a small 16-pin, 150-mil SOIC, compared to the OS1221S, which is a
16-pin, 300-mil sOle.
o.soo'

0.300"

NC

NC
Vee

VOUT

NC

NC

Vour

Vee

NC

NC

NC

NC

BC,

BC2

BC,

BC2

NC

NC

NC

NC

CEroN

THS

CE,

NC

NC

NC

NC

Vss

CE

Vss

CE

THS

DalIas_

Unilrode

0.300"

0.150"
Vee

VOUT

BC2

BC,

BL2

BC,

'RST

CE

NC

CE

VOUT

Vee

DSl221S

A

CE,

A

CE,

B

CE2

B

CE2

'Ali

CE,

NC

CE3

'WE

CE.,

THS

BE.

Vss

DO

VSS

NC

Unilrode

Dallas SenioonductDr
''These pairs must be connected
to ground if the security option
is not used.

7-11

-

[UJ

-

~

Nonvolatile SRAMs and RTCs (NV) Selection Guides

Unitrode's NVSRAMs integrate extremely low standby power SRAM, nonvolatile control circuitry, and a long-life lithium cell in either a single DIP package.. or a two-piece LIFETIME LITHIUM SMT module. The NVSRAMs combine secure long-term nonvolatility (more than~ 0 y~ars ·withoutpower) with standard SRAM pinouts and fast, unlimited
read/write operation.
.
.., .

>>>>-

Data retention without power

>-

Automatic write-protection during
power-up/power-down cycles

10 or 5 years minimum data retention in the
absence of power

>-

Battery internally isolated until power is first
supplied

>-

Industrial temperature range available

Industry-standard pinout
Conventional SRAM operation; unlimited write cycles

Nonvolatile Static RAM Selection Guide

Density

Configuration

Access
Time (ns)

Minimum DataRetention Time

Pins I
Package

Part
Number 1

Page
Number

64Kb

8Kbx8

70,85·, 150·,200

10 years

281 DIP

bq40101Y

NV/5-3

256Kb

32Kb x8

70·, 100, 150·,200

10 years

281 DIP

bq40111Y

NV/5-13

1Mb

128Kb x 8

70·,85·, 120

10 years

32/DIP
321 SMT

bq40131Y

NV/5-23

2Mb

256Kbx8

85, 120

10 years

32/DIP

bq40141Y

NV/5-33

4Mb

512Kb x 8

70,85,120

10 years

321 DIP
321 SMT

bq40151Y

NV/5-42

8Mb

1024Kb x 8

70

10 years

361 DIP

bq4016Y

NV/5-52

16Mb

2048Kbx8

70

5 years

361 DIP

bq4017Y

NV/5-61

64Kb

8kBx8

70

10 years

281
SNAPHAT

bq43101Y+

NV/5-70

256Kb

32kBx8

70 3 , 100·

10 years

281
bq4311Y/L4+
SNAPHAT

Notes:

1_ "Y" version denotes 10% Vee tolerance.
2_ ''Y'' version available in -40°C to +85°C industrial temperature range_
3_ ''Y'' version only_
4_ "I..:' version denotes 3_2V typical Vcc operation_

5_ "I..:' version only_
+ New Product

7-12

NV/5-81

-

Nonvolatile SRAMs and RTCs (NV) Selection Guides
Nonvolatile Static RAM Cross-Reference
Density

Dallas Semiconductor

STM icroelectron ics

Unitrode

DS1225AB

M48Z08

bq4010

DS1225AD

M48Z18

bq4010Y

-

M48Z58

bq4010/4823Y

DS1225Y

M48Z58Y

bq4010Y

"'

64Kb

256Kb

1M

2M

4M

8M

16M

DS1230AB

M48Z35

bq4011

DS1230Y

M48Z35Y

bq4011Y/4833Y

DS1245AB

M48Z128

bq4013

DS1245Y

M48128Y

bq4013Y

DS1258AB

-

bq4014

DS1258Y

bq4014Y

DS1250AB

M48Z512A

bq4015

DS1250Y

M48Z512AY

bq4015Y

DS1265AB
DS1265Y

-

bq4016Y

DS1270AB

M48Z2M1

bq4017

DS1270Y

M48Z2M1Y

bq4017Y

7-13

bq4016

-

[1JJ

Nonvolatile SRAMs and RTCs (NV) Selection Guides

Unitrode's real-time clocks (RTCs) provide highly integrated clock/calendar solutions for microcomputer-based designs. Each module is a completely self-contained unit; inc;luding IC, crys~al,and a battElry ensuring operation for 10
years in the absence of power. The Very compact, low-power ICs need onIY.,a battery and a crystal for operation.
NVSRAM controller versions allow users to make inexpe'nsive SRAM nonvolatile for data and configuration storage in
computers, portable equipment, office machines, and other applications.

~

Clock/calendar counts seconds through years with
daylight savings and leap-year adjustments

~

IBM PC AT-compatible clocks include:

~

SRAM-based clocks feature:
SRAM interface
Up to 512 kilobytes of NVSRAM

5- or 3-Volt operation

CPU supervisor

114,240, or 242 bytes of user nonvolatile RAM
storage
~

32kHz output for power management

~

Nonvolatile control for an external SRAM

~

One minute per month clock accuracy in modules

~

IC versions require only a crystal and battery

242

Muxed

5V

./

NVl4-22

242

Muxed

5V

./

24/SS0P

242

Muxed

3V

./

241 DIP, SOIC, SSOP

bq3285L

NV/4-22

242

Muxed

3V

./

241 SSOP

bq3285LC/LD

NV/4-46, NVl4-69

240

Muxed

3V

24 1 SSOP

NVl4-92

114

Muxed

5V

241 DIP module

NV/4-111

242

Muxed

5V

242

Muxed

NV/4-46, NV/4-69

241 DIP module

bq3287E1EA

NV/4-115

3V

241 DIP Module

bq3287LD+

NV/4-119

241 DIP, SOIC

bq4285

NVl4-123

./

114

./

Muxed

5V

114

./

Muxed

5V

./

241 DIP, SOIC, SSOP,

114

./

Muxed

3V

./

241 DIP, SOIC, SSOP

bq4285L

NV/4-143

114

./

Muxed

5V

241 DIP module

bq4287

NV/4-168

SRAM

3V

./

281 DIP, SOIC
28/SNAPHAT

bq4802+

NV/4-174

SRAM

5V

./

281 DIP module

bq4822Y

NV/4-176

SRAM

5V

28/SNAPHAT

bq4823Y+

NV/4-191

0
8K

./

8K
+ New Product

7-14

NV/4-143

-

Nonvolatile SRAMs and RTCs (NV) Selection Guides

Real-Time Clock Selection Guide (Continued)
Onboard
RAM
(bytes)

NVRAM
Control

Bus
Interface

Voltage

32K

SRAM

5V

32K

SRAM

5V

32K

SRAM

5V

128K

SRAM

5V

Pins I
Package

Part
Number

Page
Number

281 DIP module

bq4830Y

NV/4-205

321 DIP module

bq4832Y

NV/4-218

28 1 SNAPHAT

bq4833Y+

NV/4-233

./

321 DIP module

bq4842Y

NV/4-247

CPU
Supervisor

./

0

./

SRAM

5V

./

281 DIP, sOle

bq4845/Y

NV/4-262

0

./

SRAM

5V

./

281 DIP module

bq4847/Y

NV/4-279

512K

SRAM

5V

./

321 DIP module

bq4850Y

NV/4-282

512K

SRAM

5V

./

361 DIP module

bq4852Y

NV/4-295

+ New Product

Real-Time Clock Cross-Reference
Dallas Semiconductor
OS1285/885
OS1285S/885S
OS1287/887
OS1287A1887A

M48T86

Unitrode
bq3285P
bq3285S
bq3287MT
bq3287A

OS14285

-

bq4285

OS14285

-

bq4285P

OS14285S
OS14287

Notes:

STMicroelectronics

bq4285S
bq4287

OS1643

M48T081T18
M48T58Y159Y

bq4822Y

OS1644

M48T35

bq4830y 1

OS1646

-

bq4842y2

1.

Memory upgrade.

2.

Additional bq4842 features: microprocessor reset, watchdog monitor, clock alarm, and
periodic interrupt.

7-15

-

0:::0

Portable Power (PP) Selection Guides

Unitrode battery chargecmanagementlCs provide full-function, safe charge control for all types of rechargeable
chemistries. Functions include pre-charge qualification and conditioning, charge regulation, and termination.
~

Fast charging and conditioning of nickel cadmium,
nickel metal hydride,lead acid, lithium ion, or
rechargeable alkaline batteries

~

Flexible charge regulation support:

~

Fast, safe, and reliable chemistry-specific
charge-termination methods, including rate of
temperature rise (~T/~t), negative delta voltage
(-~V), peak voltage detect (PVD), minimum
current, maximum temperature, maximum
voltage, and maximum time

~

Optional top-off and maintenance charging

~

Discharge-before-charge option for NiCd

~

Complete set of development tools available for
quick product-desig

Linear
Switch-mode
Gating control (external regulator)
~

Easily integrated into systems or as a stand-alone
charger

~

Direct LED outputs display battery and charge status

Battery Charge-Management Selection Guide
Battery
Technology

Key
Features

MultiChemistry

Complete change
management with
integrated switching
controller

Pins /
Package

Part
Number

Page
Number

8/0.300" DIP,
8/0.150" SOIC

bq2000+

PP/3-7

minimum current,
maximum temperature,
maximum time

8/0.300" DIP,
810.150" SOIC

bq2000T+

PP/3-20

-~V, PVD, maximum
temperature maximum time

8/0.300" DIP,
810.150" SOIC

bq2002/C/E/F/G

PP/3-3

~T/~t,

maximum temperature,
maximum time

8/0.300" DIP,
810.150" SOIC

bq2002DIT

PP/3-3

PWM Controller

-~v, ~T/~t, maximum temperature maximum time

16/0.300" DIP,
16/0.300" SOIC

bq2003

PP/3-73

PWM controller,
enhanced display
mode

-~V, PVD, ~T/~t, maximum
temperature, maximum time

16/0.300" DIP,
16/0.150" SOIC

bq2004/E1H

PP/3-5

Dual sequential
charge-controller for
2-bav charaers

-~V, ~TIM., maximum
temperature, maximum time

2010.300" DIP,
2010.300" SOIC

bq2005

PP/3-119

PWM controller

Minimum current, maximum
time

16/0.300" DIP,
16/0.150" SOIC

bq2054

PP/3-6

8/0.150" SOIC

bq2056ITN

PP/3-186

Gating control of an
external regulator

\
NiMH,
NiCd

Low-dropout linear
with AutoCompTM
feature
Lithium Ion

Fast-Charge
Termination Method

PVD, minimum current,
maximum temperature,
maximum time
~T/~,

-

PWM controller,
enhanced display
mode

Minimum current, maximum
time

16/0.300" DIP,
16/0.150" SOIC

bq2954+

PP/3-6

PWM controller,
differential current
sense

Minimum current, maximum
time

2010.300" DIP,
2010.300" SOIC

UCC3956

PP/3-6

+ New Product
Continued on next page

7-16

-

[UJ

Portable Power (PP) Selection Guides

Battery Charge-Management Selection Guide (Continued)
Battery
Technology

Lead Acid

Key Featu res

Fast·Charge
Termination Method

-!:J.2v,

Pins/
Package

Part
Number

Page
Number

16/0.300" DIP,
16/0.150" SOIC

bq2031

PP/3-154

PWM controller, 3 charge
algorithms

Maximum voltage,
minimum current,
maximum time

Linear controller

Maximum voltage,
minimum current

16/0.300" DIP
16/0.300"SOIC

UC3906

PP/3-237

PWM controller, differential
current sense

Maximum voltage,
minimum current

20/0.300" DIP
20/0.300"SOIC

UC3909

PP/3-244

2-cell charging

Maximum voltage

8/0.300"DIP,
8/0.150" SOIC

bq2902

PP/3-194

3- or 4-cell charging

Maximum voltage

14/0.300" DIP,
14/0.150" SOIC

bq2903

PP/3-204

Rechargeable
Alkaline

7-17

-

Portable Power (PP) Selection Guides

The bq2002 fast-charge control ICs are low-cost CMOS battery charge-control ICs providing reliable charge terminati0r for both NICd and NiMH battery applications. Controlling a current-limited or constant-current supply allows the
ICs to be the ba$is for a cost-effective st.anGhal.one or system-integrated charger. The bq2002 family includes options
that integrate fast charge, top~Qff, andpufse-trickle charge control in a single IC for charging one or more NiCd or
NiMH batteries.
A new charge cycle is started by the application of a charging supply or by replacement of the battery. For safety,
fast charge is inhibited if the battery voltage or temperature is outside of configured limits. Fast charge may be inhibited using the INH input. In some versions, this input may be used to synchronize voltage sampling. A low-power
standby mode reduces system power consumption.

~

Fast-charge control of nickel cadmium or
nickel-metal hydride batteries

~

Backup safety termination on maximum voltage,
maximum temperature, and maximum time

~

Fast-charge terminations available:

~

Top-off and pulse-trickle charge rates available

~

Synchronized voltage sampling available

~

Low-power mode

~

8-pin 300-mil DIP or 150-mil SOIC packaging

-eN
Peak Voltage Detection (PVD)
~T/~t
~

Direct LED output displays charge status

160/80/40

200/80/40

160/80/40

600/300/10 300/150175 300/150175

300/150175

none

none

none

C/16,O

C/16,O

C/64,C/16,O

none

160/100/40 160/80/40

Hold-off period
options
(seconds)

600/300/10

Top-off

C/32,C/16,O C/32,C/1

Top-off period

4.6ms

4.6ms

n/a

1.17s

1.17s

4.6ms

n/a

Pulse-trickle options

C/64,C/32

C/64,C/32

C/32

C/32

C/32

C/256,C/128

none

Pulse-trickle period

9 or 18ms

9 or 18ms

1.17s

1.17s

1.17s

18 or 73ms

n/a

no

no

yes

yes

yes

no

no

no

no

yes

yes

yes

no

no

Synchronized
Minimum voltage
pre-charge
qualification
Continued on next page

7-18

-

Portable Power (PP) Selection Guides

bq2002 Family Selection Guide (Continued)
Part Number

-"v or PVD Termination

:';T/"t Termination

Feature

bq2002

bq2002F

bq2002C

bq2002E

bq2002G

bq2002T

bq2002D

Hysteresis on
high-temperature
cut-off

no

no

no

no

no

yes

yes

LED in "charge
pending" phase

n/a

n/a

flashes

flashes

flashes

on

off

PP/3-35

PP/3-35

PP/3-43

PP/3-61

PP/3-61

PP/3-51

PP/3-51

Page number

7-19

-

[UJ

Portable Power (PP) Selection Guides

The bq2004 fast-charge control ICs are low-cost CMOS battery charge contrql ICs providing reliable charge termination for both NiCd and NiMH battery applications. Integration ofPWM curren(control circuitry allows thelCs to be the
basis for a cost-effective stand-alone or system-integrated charger'. The bq2004 family includes options that integrate
fast charge, top-off, and pulse-trickle charge control in a single IC for charging one or more NiCd or NiMH batteri~s.'
A new charge cycle is started by the application of a charging st,ipply, replacement of the battery, or ,a logic-level
pulse. For safety, fast charge is inhibited if the battery voltage or temperature is outside of configured limits. Fast
charge may be inhibited using the INH input,which also puts the IC into a low-power standby mode, reduCing system
power consumption.

.
..
...

.

Fast-charge control of nickel cadmium or
nickel-metal hydride batteries

Fast-charge terminations available:

-IN

Integrated PWM closed-loop current control

Peak Voltage Detection (PVD)

Configurable, direct LED output displays charge
status

.
.

Low-power mode
Top-off and pulse-trickle charging available

8T/8t
Backup safety termination on maximum voltage,
maximum temperature, and maximum time
16-pin 300-mil DIP or 150-mil SOIC packaging

bq2004 Family Selection Guide
Part Number
Feature

bq2004

bq2004E

bq2004H

360/1S0/90/45/23

325/154177/39/19

650/325/154177/39

137/S20/41 0/200/1 00

137/546/273/137/6S

27315461546/273/137

Charge rate during hold-off period

full fast-charge rate

1/S*fast-charge rate

1/S*fast-charge rate

Top-off options

C/2,C/4,C/S,C/16,0

C/2,C/4,C/S,C/16,0

C/4,C/S,C/16,C/32,0

260/20S0

260/20S0

260/20S0

MTO

0.235*MTO

0.235*MTO

C/32,C/64,0

C/512,0

C/512,0

4.17IS.3/16. 7/33.3/66.7

66.7/133/267/532

33.3/66.7/133/267

Pulse-trickle pulse width (seconds)

260

260

260

DSEL floating disables pulse-trickle

no

yes

yes

VSEL high disables low-temperature
fault threshold

yes

no

no

1/4LTF + 3/4 TCO

1/3LTF + 2/3 TCO

1/3LTF + 2/3 TCO

PP/3-91

PP/3-105

PP/3-105

Maximum time-out selections (minutes)
Hold-off period selections (seconds)

Top-off pulse width/period (seconds)
Top-off duration
Pulse-trickle selections
Pulse-trickle period (ms)

High-temperature fault threshold
Page number

7-20

-

Portable Power (PP) Selection Guides
Li-Ion PWM Charge IC Selection Guide
Part Number
Feature

Charge
algorithm

bq2054

bq2954

UCC395lr

During pre-qualification, the
bq2054 charges using a low
trickle current if the battery
voltage is low. Then it charges
using constant current followed
by constant volatge. After
fast-charge termination, charge
is re-initiated by resetting the
power to the IC or by inserting
a new batterv.

Performs similar to the bq2054,
but the bq2954 also re-initiates a
recharge if the battery voltage
falls below a threshold level. This
allows the bq2954 to maintain a
full charge in the battery at all
times.

Uses a 4-step charge
algorithm: low-current trickle
charge (when the cell voltage
is below a user- programmabie level); high- current
bulk charge; constant-voltage overcharge;
optional top-off with
user-programmable timer

Fully differential high-side
current sensing can be used
Current-sensing
Low-side and high-side current
Low-side current sensing
up to 20V common mode
sensing
technique
without the need for external
level shiftina.
One-shot charge initiates
Application of power or detection Application of power or detection charging, or a simple
Charge initiation
of battery insertion
of battery insertion
comparator initiates charging
on batterY insertion.
Minimum cell voltage required
User-programmable threshold
Detection of
Minimum cell voltage required
for fast charge: 3V/cell
limits charge current when
deeply disfor fast charge: 2V/cell
battery cells are deeply
Trickle-charge period: 0.25 *
charged (bad)
Trickle-charge period: 1 * MTO
MTO (for faster detection of bad discharged and provides
cells
cells)
short-circuit protection.
User-programmable minimum
User-programmable minimum
User-programmable minimum
Charge termina- current is a ratio of the charging current is a ratio of the charging
current or
tion based on
current: 1/10, 1/20, 1/30. A
current: 1/10,1/15, 1/20. A
user-programmable
minimum curren safety charge timer is also avail- safety charge timer is also availovercharge timer
able.
able.
Measured using an external
Measured using an external
Temperature
thermistor. Fast charge is inhib- thermistor. Fast charge is inhibNo
monitoring
ited if the battery temperature is ited if the battery temperature is
outside user-confiaured limits.
outside user-confiaured limits.
2 LEDs for state of charge
2 LEDs or one bi-color LED
3
LEDs
for
state
of
charge
Status display
optimize state of charae
includina end of charae
Full-charge
LEDs indicate full charge after
LEDs indicate full charge just
LEDs indicate full charge on
indication
charoe termination
before charoe termination
charoe termination
Input voltage
4.5Vto 5.5V
4.5V to 5.5V
6.5Vto 20V
ranae
Typical supply
2mA
2mA
5mA
current
Voltage regula±1% at 25°C
±1% at 25°C
±1% at 25°C
tion accuracv
Wakeup feature
for battery pack No
Yes
No
protectors
Integrated PWM
Yes
Yes
Yes
controller
Pins/oackaae
16-oin narrow PDIP or SOIC
16-oin narrow PDIP or SOIC
20-oin SOIC or DIP
PP/3-170
PP/3-217
PP/3-253
Paoe number

7-21

-

[UJ

Portable Power (PP) Selection Guides

Unitrode's Gas Gauge les measure the available charge, calculate self-discharge, and communicate the qvailable
charge of a battery pack over a serial port or by directly driving an LED display.

Accurate measurement of available charge for nickel
cadmium, nickel metal-hydride, lithium ion, lead-acid
batteries, and primary lithium

~

Available capacity is compensated for
charge/discharge rate and temperature

Designed for battery-pack integration
~

~

15Q1A or less typical operating current

1-wire DO
NiCdlNiMH

Serial port or direct LED display for remaining
battery capacity indication

Accurately measures across a wide range of
currents

control

16/S0lC

PP/4-81

800-5000
External charge-control support

16/S0lC

bq2014

PP/4-123

1-wire HDO

Register-compatible with bq2050H

16/S0lC

bq2014H+

PP/4-149

NiCd

800-2000

1-wire DO

See bq2011 Family Selection
Guide

16/S0lC

bq2011
bq2011J
bq2011K

PP/4-24,
PP/4-45,
PP/4-63

NiCd/NiMHI
Lead Acid

200010,000

1-wire HDO

Programmable offset and load
compensation

16/S0lC

bq2013H

PP/4-103

1-wire DO

Remaining power (Wh) indication

16/S0lC

bq2050

PP/4-215

Li-Ion

800-5000
1-wire HDO

Register-compatible with bq2014H

16/S0lC

bq2050H

PP/4-237

1-wire HDO

Programmable discharge
efficiency compensation

16/S0lC

bq2052+

PP/4-259

SBS rev. 1.0-compliant

16/S0lC

bq2040

PP/4-185

SBS rev. 0.95-compliant

161 SOIC

bq2092

PP/4-314

SBS rev. 1.0-compliant with 5
LEDs

16/S0lC

bq2945

PP/4-340

2-wire
5MBus or
1-wire
HD016

SBS rev. 1.1-compliant

28/SS0P

bq2060+

PP/4-276

1-wire HDO

Analog peripheral for IlC

8/S0lC or
TSSOP

bq2018

PP/4-170

Primary
Lithium

80015,000

2-wire
5MBus
NiCd/NiMH
Lead Acidl
Li-Ion

Any

80010,000

Any

+ New Product

7-22

-

Portable Power (PP) Selection Guides

The bq2011 Gas Gauge ICs provide accurate capacity monitoring of rechargeable batteries in high discharge rate
environments. The ICs can monitor a wide range of charge/discharge currents using the onboard V-to-F converter
and a low-value sense resistor. The ICs track remaining capacity (NAC) and compensate it for battery self-discharge,
charge/discharge rate, and temperature. Five LEOs can communicate remaining capacity in 20% increments. A serial
port allows a host microcontroller to access the nonvolatile memory registers containing battery capacity, voltage,
temperature, and other critical parameters.

>-

Accurate measurement of available charge in
rechargeable batteries

>-

>>-

Designed for NiCd high discharge rate applications

>>-

Drives 5 LEOs for capacity indication

Automatic charge self-discharge and discharge
compensation
Low operating current
16-pin narrow SOlt

,

bq2011 Family Selection Guide
Part Number
Feature

bq2011

bq2011J

bq2011 K

Relative or absolute

Absolute

Absolute

4.5-10.5mVh

2.21-3.S1mVh

2.21-3.S1mVh

Nominal Available Capacity
(NAC) on reset

NAC=O

NAC = PFC orO

NAC = PFC orO

Self-discharge rate

NAC/SO

NAC/SO or disabled

NAC/SO or disabled

Display
Programmed Full Count
(PFC) range

65-95% based on rate and 70-95% based on rate and
temperature
temperature

Charge compensation

75-95% based on rate
and temperature

Discharge compensation

75-100% plus temperature compensation

75-100% plus temperature compensation

100%

End-of-discharge voltage

0.9V/cell

0.9V/cell

0.96-1.16V/cell

Page number

PP/4-24

PP/4-45

PP/4-63

7-23

-

[U]

Portable Power (PP) Selection Guides

Unitrode's battery management module products provide true turn-key solutions for capacity monitoring and charge
control of NiCd, NiMH, Li-Ion, or Rechargeable Alkaline battery packs. Designed for battery pack integration, the
small boards contain all necessary components to easily implement intelligent or smart battery packs in a portable
system. The wide selection of boards offers battery monitoring, capacity tracking, charge control, and remaining capacity communication to the host system or user. The boards are fully tested and provide direct cell connections for
simple battery packs.
Turnkey solutions for intelligent or smart batteries for
portable equipment
Computers, cellular phones, and camcorders

Capacity monitoring and charge control
Pushbutton-activated LED capacity indication

>

Handheld terminals

Designed for battery pack integration
Small size

Communication radios

Low power

Medical and test equipment

Direct cell connections

Power tools

Battery-Management Modules Selection Guide
Battery
Technology

Key Features

Part
Number

Page
Number

Capacity monitoring, LED indication, serial communications port

bq2110

PP/5-2

Capacity monitoring, slow-charge control, LED indication, serial communications port

bq2112

PP/5-14·

Capacity monitoring, charge control output, LED indication, serial communications port

bq2114

PP/5-24

Capacity monitoring and fast charge control

bq2164

PP/5-71

NiCd

Capacity monitoring for high discharge rates, LED indication

bq2111L

PP/5-8

NiCd/NiMH,
Lead Acid

Capacity monitoring, LED indication, single-wire serial communications port

bq2113H+

PP/5-20

Capacity monitoring, Smart Battery data set and interface, LED indication, pack supervision, 4-segment LED indication

bq2148

PP/5-40

Capacity monitoring, LED indication, serial communications port

bq2150
bq2150/H

PP/5-47
PP/5-53

Pack supervision: overvoltage, undervoltage, and overcurrent control

bq2158
bq2158T

PP/5-57
PP/5-64

Capacity monitoring, 3- or 4-cell pack supervision, and LED
indication

bq2167+
bq2168+

PP/5-77
PP/5-85

Capacity monitoring, Smart Battery data set and interface,
5-segment LED indication

bq2145

PP/5-34

Capacity monitoring, Smart Battery data set and interface, 4-segment
LED indication

bq219XL

PP/5-93

Charge and discharge counting, serial communication port, single-wire
interface

bq2118

PP/5-30

NiCd/NiMH

Li-Ion

NiCdlNiMHI
Lead Acidl
Li-Ion

Any
+ New Product

7-24

-

Portable Power (PP) Selection Guides

Unitrode Lithium Ion Pack-Protection ICs provide reversible overvoltage, undervoltage, and overcurrent protection for
lithium ion battery packs.
~

Protects one to four Lithium Ion series cells from
overvoltage, undervoltage, and overcurrent

~

~

User-selectable thresholds mask-programmable by
Unitrode

Designed for battery-pack integration
Small outline package, minimal external
components and space, and low cost

Pack-Protection and Supervisory ICs Selection Guide
Battery
Technology

Number of Cells
Protected

30r4

Protection Types

Overvoltage,
overcurrent, and
undervoltage

2

Lithium Ion

Overcharge,
overdischarge,
overcurrent
1

Key
Features

Pins I
Package

Part
Number

bq2058
Very low power
Internal
MOSFET
(80mO total)

16/0.150"
SOIC

Page
Number

PP/6-2

bq2058T

PP/6-14

UCC3911

PP/6-26

Internal
MOSFET
(50mO total)

16/0.150"
TSSOP

UCC3952+

PP/6-32

30r4

Overvoltage,
undervoltage,
overcurrent

Smart-discharge
circuitry

16/0.150"
SSOP

UCC3957

PP/6-37

1

Overcharge,
overdischarge,
overcurrent

Internal
MOSFETS
(50mO total)

16/0.150"
SOIC

UCC3958

PP/6-44

+ New Product

7-25

-

[UJ

Portable Power (PP) Selection Guides
Power-Management ICs Selection Guide
Part Number
Features

UCC3809
-1/2

UCC3581

UCC38130/1/2/3/4/5

UCC3800/
1/2/3/4/5

Forward, flyback

Forward, flyback,
buck boost

Off-line AC

Off-line AC

Off-line AC, battery

NA

NA

NA

NA

Operating mode

Fixed/variable
freauencv

Fixed frequency
(1 MHz maximum)

Fixed frequency
(1 MHz maximum)

Fixed frequency
(1 MHz maximum)

Output

1A FET drives

Topology
Input voltaQe
Output voltaQe

Forward, flyback, buck, Forward, flyback, buck,
boost
boost
Off-line AC, battery

1A FET drives

0_8A FET drives

1A FET drives

Output power

N/A

N/A

N/A

N/A

Supply current

300uA

SOOuA

SOOuA

SOOuA

Yes

No

Yes

Yes

Power limit
Application/design
note

ON-48, ON-6S

Pin count +
PaQe number

ON-6S, ON-89,
U-16S, U-168

ON-42A, ON-43,
ON-42A, ON-43,
ON-46, ON-48, ON-S4, ON-46, ON-48, ON-S4,
ON-S6A, ON-6S,
ON-S6A, ON-6S,
ON-89 U-133A U-97 ON-89 U-133A U-97

14

8

8

8

PS/8-128

PS/8-192

PS/8-169

PS/8-206

+The smallest available pin count for thru-hole and surface-mount packages.

Power-Management ICs Selection Guide (Continued)
Part Number
Features

UCC39401

UCC3941
-3/-5/-ADJ

UCC39411
/2/3+

Topology

Boost 1 battery
charger

Input voltage

0.8V to (VOUT + 0.8V to (VOUT + 1.1Vto (VOUT +
O.SV)
O.SV)

Output voltage

Boost

Boost

o.svf

AOJ to S.OV

3.3V, SV, AOJ

3.3V, SV, AOJ

UCC39421/2+

UCC3946

UCC3954

BoostlSEPICI
flyback

Watchdog!
reset

Flyback

1.8V-8V

2.1V-S.SV

2.SV-4.2V

AOJ

V II•J-O.3V

3.3V

Variable
frequency

Variable
frequency

Variable

Fixed/variable
frequency

Watchdog!
reset

Fixed
frequency
(200kHz)

Internal power
FETs

Internal power
FETs

Internal power
FETs

FET Orives

NA

Internal power
FETs

Output power

200mW

SOOmW (1 cell)
1W (2 cells)

200mW

NA

NA

2W

Supply current

Operating
mode
Output

SSIlA

801lA

481lA

63SIlA

101lA

1mA

Power limit

Yes

Yes

Yes

Yes

NA

Yes

Application/
desiQn note

-

ON-73

ON-97

-

-

ON-86

Pin count +
PaQe number

20

8

8

16/20

8

8

PPI7-34

PPI7-48

PPI7-S8

PPI7-66

PPI7-88

PPI7-93

+ New Product

+ The smallest available pin count for thru-hole and surface-mount packages.

7-26

-

0:::0

Portable Power (PP) Selection Guides
Linear Controller ICs Selection Guide
Part Number
Features

UC3832

UC3833

UC3834

UC3835

UC3836

UCC3837

SV fixed

Positive
adjustable

Positive
adjustable

40V

40V

12V

2.SV

1.SV

Type of output

Positive
adjustable

Positive
adjustable

Positive/
negative
adiustable

Maximum input
voltage

36V

36V

40V

Minimum output
voltaae

2.0V

2.0V

+1.SV / -2.0V

Output drive

300mA

300mA

3S0mA

SOOmA

SOOmA

1.SmA

Type of short
circuit limit

Duty cycle

Duty cycle

Foldback

Foldback

Foldback

Duty cycle

Reference
voltaae accuracv

2%

2%

3%/4%

2%

2%

2%

Special features

Multiple pins
accessible

Built-in Rsense

Built-in
Rsense

Internal
charge pump;
Direct N-FET
drive

Application/
design note

DN-32,
DN-32,
DN-61, U-1S2 DN-61 U-1S2

Pin count .:.
Page number

-

-

-

U-9S

14 16

8 16

16

8 16

8 16

8

PS/3-11

PS/3-11

PS/3-18

PS/3-24

PS/3-24

PS/3-28

+The smallest available pin count for thru-hole and surface-mount packages.
Low-Dropout Linear Regulator ICs Selection Guide
Part Number
Features

Output voltage
Dropout voltage
Output voltaae accuracy
Maximum input voltage

UCC381

UC382-1

UC382-2

UC382-3

UC382·ADJ

3.3V, SV, ADJ

1.SV

2.1V

2.SV

1.2V1
adiustable

O.SVat 1A

4S0mVat 3A

4S0mVat 3A

4S0mVat3A

4S0mVat 3A

2.S%

1%

1%

1%

1%

9V

7.SV

7.SV

7.SV

7.SV

Shutdown current

10uA

Operating current

400iJ,A

-

-

-

-

-

Line reaulation

0.01%/V

Load regulation

0.1%, lOUT = 0
to 1A

Special features

Power limit

Fast transient
response

Fast transient
re~onse

Fast transient
resP9nse

8

S

S

S

S

PP/7-S

PS/3-S

PS/3-S

PS/3-S

PS/3-S

Pin count .:Page number

-:.The smallest available pin count for thru-hole and surface-mount packages.

7-27

Fast transient
re~onse

-

Portable Power (PP) Selection Guides
Low-Dropout Linear Regulator ICs Selection Guide (Continued)
Part Number
UCC383

UCC384

UC385-1

UC385-2

UC385-3

3_3V, 5V, ADJ

5V, 12V, ADJ

1_5V

2.1V

2.5V

0.45Vat 3A

0.2Vat
500mA

450mVat 5A

450mVat 5A

450mVat 5A

Features

Output voltage
Dropout voltage
Output voltage accuracy

2.5%

2.5%

1%

1%

1%

Maximum input voltage

9V

-16V

7.5V

7.5V

7.5V

Shutdown current

40~A

17~

-

Operating current

400~A

240~A

-

0.01%/V

0.01%/V

-

Line regulation
Load regulation
Special features

0.1%, lOUT = 0 0.1%, lOUT =0
to 1A
to 500mA

-

Power limit

Power limit

Fast transient
response

Fast transient
response

Fast transient
response

3

8

5

5

5

PPI7-12

PPI7-19

PS/3-35

PS/3-35

PS/3-35

Pin count .:Page number

-:-The smallest available pin count for thru-hole and surface-mount packages.

Low-Dropout Linear Regulator ICs Selection Guide (Continued)
Part Number
Features

Output voltage
Dropout voltage

UC385-ADJ

UC386+

UC387+

UC388+

1.2V/adjustable

3.3V

5V

Adjustable down to
1.25V

450mVat5A

0.2V at 200mA

O.2V at 200mA

O.2V at 200mA

Output voltage accuracy

1%

1.5%

1.5%

1.5%

Maximum input voltage

7.5V

9V

9V

9V

-

2uA

2~

2uA

Shutdown current
Operating current

-

10UA

10~

10uA

Line regulation

-

25mV max

25mVmax

25mV max

Load regulation

-

10mV max

10mV max

10mV max

Special features

Fast transient
response

TSSOP

TSSOP

TSSOP

Pin count .:Page number

5

8

8

PS/3-35

PPI7-29

PPI7-29

.:-The smallest available pin count for thru-hole and surface-mount packages.

+ New product.

7-28

8 ,
PPI7-29

-

Portable Power (PP) Selection Guides

Special Function Linear Regulation ICs Selection Guide
Part number
Features

Type of output

UC560

UCC561+

UC563+

Positive

Positive

Positive

Source/sink regulator for
the 18- and 27-line SCSI
termination

LVD SCSI regulator for the
18- and 27-line termination

32-line VME bus bias
generator

4V-6V

2.7V- 5.25V

4.875V-5.25V

Output voltage

2.85V

1.3V, 1.75V, O.75V

2.94V

Dropout voltage

O.9V at 750mA

-

-

SCSI-1,2,3

SPI-2,3

VME/VME64

300mA / -750mA

200mA / -200mA

475mA / -575mA

Application
Input voltage

Bus standard
Sink/source current
Application/design note
Pin count .:.
Page number

-

-

-

5,8

16

3,8

IF/4-3

IF/4-7

IF/4-10

.:.The smallest available pin count for thru-hole and surface-mount packages.
+ New product.

7-29

-

[1:JJ

Portable Power (PP) Selection Guides

Back-Light Controller ICs Selection Guide
Part Number
Features

UC3871

UC3872

UCC3972+

Fluorescent lamp driver
with LCD Bias

Fluorescent lamp driver

Fluorescent lamp driver

4.5V-20V

4.5V-24V

4.5V-25V

Reference tolerance

1.2%

1.2

NA

Open lamp detect

Yes

Yes

Yes

PWM synchronization

Yes

Yes

Yes

Programmable

Programmable

SOkH-1S0kH

I

Application
Voltage range

PWM frequency
Analog dimming

Yes

Yes

Yes

Low-frequency dimming

Yes

Yes

Yes

Operating current

SmA

SmA

1mA

Package

1S-pin SOIC

1S-pin SSOP

S-pin TSSOP

Application/design note

U-141, U-14S

DN-75, U-141, U-14S

-

PP/S-2

PP/S-S

PP/S-13

Page number

+ New Product

7-30

-

[1JJ

Portable Power (PP) Selection Guides
IrDA Selection Guide
Device Type

Supply
Dynamic Quiescent Encoder!
IrDA
Voltage Data Rate Range
Current Decoder Compliant LED Driver

Part
Number

Page
Number

Receiver

3.3V
or5V

2.4kbps
115.2kbps

150nA
100mA

2501lA

N

Y

N/A

UCC5341

PP/9-2

Transceive

3.3V
or5V

2.4kbps
150nA
115.2kbps 100m A

2501lA

N

Y

500mA

UCC5342

PP/9-6

Transceive

3.3V
or5V

2.4kbps
115.2kbps

2801lA

y

Y

500mA

UCC5343 PP/9-10

150nA
100mA

7-31

-

[1JJ

Power Supply Control (PS) Selection Guides
PWMControl

Current Mode Controllers ................................................... 7-32
Dedicated DCfDC Controllers ................................................ 7-44
MicroProcessor Power Controllers ...................................... , ..... 7-47
MicroProcessor Power Support. .............................................. 7-49
Post Regulation Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 7-50
Secondary Side PWM Control ............................................... 7-51
Soft Switching Controllers ................................................... 7-52
Voltage Mode Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-56

PWM Control
Current Mode Controllers
Application
Topology
Voltage Reference Tolerance
Peak Output Current
Under Voltage Lockout
Maximum Practical Operating
Frequency
Outputs
Startup Current
Leading Edge Blanking
Soft Start
Maximum Duty Cycle
Separate Oscillator I
Synchronization Terminal
Application I Design Note
Pin Count .:.
Page Number

UCC3800

UNITRODEPARTNUMBER
UCC3801
UCC3802
UCC3803

OC·OCand
Battery
Buck, Boost
1.5%
1A
7.2V /6.9V

OC-OCand
Battery
Buck, Boost
1.5%
1A
9.4V/7.4V

1MHz

UCC3804

Forward, Flyback
1.5%
1A
12.5V /8.3V

OC-OCand
Battery
Buck, Boost
1.5%
1A
4.1V / 3.6V

Forward, Flyback
1.5%
1A
12.5V / 8.3V

1MHz

1MHz

1MHz

1MHz

Single, Totem
Pole
100!lA
Y
y

Single, Totem
Pole
100IJA
Y
y

Single, Totem
Pole
100!lA
y
y

Single, Totem
Pole
100IJA
y
y

Single, Totem
Pole
100!lA
y
y

100%

50%

100%

100%

50%

ON-42A, ON-48,
ON-54, ON·65,
ON-89, U-97,
U-133A

ON-42A, ON-48,
ON-54, ON-65,
ON-a9, U-97,
U-133A

ON-42A, ON-48,
ON-54, ON-65,
ON-a9, U-97,
U-133A

a
PS/3-173

a
PS/3·173

a
PS/3-173

Off·line

All products feature Pulse-by-Pulse Current Limiting and UVLO unless otherwise noted.
•:. The smallest available pin count for thru-hole and surface mount packages.
+ New Product

7-32

ON-42A, ON-43,
ON-46, ON-48,
ON-54, ON-56A,
ON-65, ON-a9,
U-97, U-133A
a
PS/3-173

Off-line

ON·42A, ON·48,
ON-54, ON·55,
ON-a9, U-97,
U-133A
a
PS/3-173

-0dJ

Power Supply Control (PS) Selection Guides
PWM Control (cont.)
Current Mode Controllers
Application

Topology
Voltage Reference Tolerance
Peak Output Current
Under Voltage Lockout
Maximum Practical Operating
Frequency
Outputs
Startup Current
Leading Edge Blanking
Soft Start
Maximum Duty Cycle
Separate Oscillator I
Synchronization Terminal

Application I Design Note
Pin Count .:.
Page Number

UCC3805

UNITRODE PART NUMBER
UCC3807-1
UCC3807-2
UCC3806

1.S%
1A
4.1V 13.6V

Isolated Output,
Push-pull
Controller
Push-pull, Full
Bridge, Half
Bridge
1%
O.SA
7.5V 16.75V

1MHz

DC-DC and
Battery
Forward, Flyback

DC-DC

Off-line

UCC3807-3
DC-DC and
Battery

Forward, Flyback Forward, Flyback Forward, Flyback
Buck, Boost
Buck, Boost
Buck, Boost
1.S%
1A
7.2V 16.9V

1.S%
1A
12.SV 18.3V

1.S%
1A
4.3V 14.1V

1MHz

1MHz

1MHz

1MHz

Single, Totem
Pole
100j.iA
y
y

Dual Alternating,
Totem Pole
100j.iA

Single, Totem
Pole

Single, Totem
Pole

Single, Totem
Pole

y

100j.iA
y
y

100j.iA
y
y

100j.iA
y
y

SO%

SO%/SO%

Programmable

Programmable

Programmable

DN-4S, DN-S1,
DN-6S, U-97,
u-no, U-144

DN-48, DN-65,
U-97, U-133A

DN-48, DN-6S,
U-97, U-133A

DN-48, DN-65,
U-97, U-133A

16
PS/3-180

8
PS/3-187

8
PS/3-187

8
PS/3-187

y
DN-42A, DN-43,
DN-46, DN-48,
DN-S4, DN-S6A,
DN-6S, DN-89,
U-97, U-133A
8
PS/3-173

All products feature Pulse-by-Pulse Current Umiting and UVLO unless otherwise noted.
•:. The smallest available pin count for thTU-hole and surface mount packages.
+ New Product

7-33

-

Qd]

Power Supply Control (PS) Selection Guides
PWM Control (cont.)
Current Mode Controllers
Application

Topology
Voltage Reference Tolerance
Peak Output Current
Under Voltage Lockout
Maximum Practical Operating
Frequency
Outputs
Startup Current
Leading Edge Blanking
Soft Start
Maximum Duty Cycle
Separate Oscillator I
Synchronization Terminal
Application I Design Note
Pin Count .:.
Page Number

UCC3808-1
Off-line
Push-pull, Full
Bridge, Half
Bridge
2%
0.5A Source, 1A
Sink
12.5V 18.3V

UNITRODE PART NUMBER
UCC3808-2
UCC3809-1
UCC3809-2
DC·DCand
Battery

DC-DC

Off-line

UCC3810
DualPWM
Controller,
Off-line, DC-DC

Push-pull, Full
Forward, Flyback, Forward, Flyback, Forward, Flyback
Bridge, Half
Buck, Boost
Buck, Boost
Buck, Boost
Bridge
2%
1.5%
5%
5%
0.5A Source, 1A
0.4A Source,
O.4A Source,
1A
Sink
0.8A Sink
0.8A Sink
4.3V 14.1V
10V 18V
15V 18V
11.3V 18.3V

1MHz

1MHz

1MHz

1MHz

1MHz

Dual Alternating,
Totem Pole
1301-1A

Dual Alternating,
Totem Pole
1301-1A

Single, Totem
Pole
1001-1A

Single, Totem
Pole
1001-1A

y

y

y

y

50%/50%

50%/50%

90%

90%

N/A

N/A

Y

ON-65, U-97,
U-110,U-170
8
PS/3-192

ON-65, U-97,
U-110, U-170
8
PS/3-192

ON-65, ON-89,
U-165, U-168
8
PS/3-198

ON-65, ON-89,
U-165, U-168
8
PS/3-198

ON-65, U-97,
U-110, U-133A
16
PS/3-205

Dual, Totem Pole
1501-1A

Y

All products feature Pulse-by-Pulse Current Limiting and UVLO unless othelWise noted•
•:. The smallest available pin count for thru-hole and surface mount packages.
+ New Product

7-34

50%

[1:JJ

-

Power Supply Control (PS) Selection Guides
PWM Control (cont.)
Current Mode Controllers
Application
Topology
Voltage Reference Tolerance
Peak Output Current
Under Voltage Lockout
Maximum Practical Operating
Frequency
Outputs
Startup Current
Leading Edge Blanking
Soft Start
Maximum Duty Cycle
Separate Oscillator /
Synchronization Terminal
Application / Design Note
Pin Count .:.
Page Number

UCC3813-0

UNITRODE PART NUMBER
UCC3813-1
UCC3813-2
UCC3813-3

OC-OCand
Battery
Buck, Boost
1.5%
1A
7.2V /6.9V

OC-OCand
Battery
Buck, Boost
1.5%
1A
9.4V /7.4V

1MHz

UCC3813-4

Forward, Flyback
1.5%
1A
12.5V /8.3V

OC-OCand
Battery
Buck, Boost
1.5%
1A
4.1V/3.6V

Forward, Flyback
1.5%
1A
12.5V /8.3V

1MHz

1MHz

1MHz

1MHz

Single, Totem
Pole
1001JA
Y
y

Single, Totem
Pole
1001JA
Y
y

Single, Totem
Pole

Single, Totem
Pole

1001JA
Y
y

1001JA
Y
y

Single, Totem
Pole
1001JA
Y
y

100%

50%

100%

100%

50%

ON-42A, ON-48,
ON-54, ON-65,
ON-89, U-97,
U-133A

ON-42A, ON-48,
ON-54, ON-65,
ON-89, U-97,
U-133A

ON-42A, ON-48,
ON-54, ON-65,
ON-89, U-97,
U-133A

8
PS/3-212

8
PS/3-212

8
PS/3-212

Off-line

All products feature Pulse-by-Pulse Current Limiting and UVLO unless otherwise noted.
•:. The smallest available pin count for thru-hole and surface mount packages.
+ New Product

7-35

ON-42A, ON-43,
ON-46, ON-48,
ON-54, ON-56A,
ON-65, ON-89,
U-97, U-133A
8
PS/3-212

Off-line

ON-42A, ON-48,
ON-54, ON-65,
ON-89, U-97,
U-133A
8
PS/3-212

[1JJ

Power Supply Control (PS) Selection Guides
PWM Control (cont.)
Current Mode Controllers
Application
Topology
Voltage Reference Tolerance
Peak Output Current
Under Voltage Lockout
Maximum Practical Operating
Frequency
Outputs
Startup Current
Leading Edge Blanking
Soft Start
Maximum Duty Cycle

UCC3813-5

Pin Count .:.
Page Number

UC3824

DC-DC and
Battery

DC-DC

DC-DC

Off-line

Forward, Flyback
1.5%
lA
4.1V /3.6V

Buck, Boost
1%
1.5A
9.2V /8.4V

Buck, Boost
1%
2A
9.2V /8.4V

Buck, Boost
1%
2A
l6V /10V

Synchronous
RectHier, Forward
Converter
Forward, Flyback
1%
1.5A
9.2V /8.4V

1MHz

lMHz

lMHz

lMHz

lMHz

Single, Totem
Pole

Single, Totem
Pole

. Single, Totem
Pole

Single, Totem
Pole

100j.iA

1.1mA

O.lmA

O.lmA

Dual
Complementary,
Totem Pole
1.lmA

y

Y
y

Y
y

y

100%

Programmable,
<100%

Programmable,
<100%

100%

y

y

y

y

U-97, U-lll,
U-131

U-97, U-ll0,
U-ll1,U-128,
U-131

U-97, U-l10,
U-lll, U-128,
U-131

U-ll1

16
PS/3-219

16
PS/3-225

16
PS/3-225

16
PS/3-233

Y
y
50%

Separate Oscillator I
Synchronization Terminal
Application I Design Note

UNITRODE PART NUMBER
UC3823
UC3823A
UC38238

DN-42A, DN-43,
DN-46, DN-48,
DN-54, DN-56A,
DN-65, DN-89,
U-97, U-133A
8
PS/3-212

All products feature Pulse-by-Pulse Current Limiting and UVLO unless otherwise noted•
•:. The smallest available pin count for thru-hole and surface mount packages.
+ New Product

7-36

-

Power Supply Control (PS) Selection Guides
PWM Control (cont.)
Current Mode Controllers

Application

Topology
Voltage Reference Tolerance
Peak Output Current
Under Voltage Lockout
Maximum Practical Operating
Frequency
Outputs
Startup Current
Leading Edge Blanking
Soft Start

UC3825

UNITRODE PART NUMBER
UC3826 )
UC3825B

UC3825A

DC-DC

DC-DC

Off-line

Push-pull, Full
Bridge, Half
Bridge
1%

Push-pull, Full
Bridge, Half
Bridge
1%

Push-pull, Full
Bridge, Half
Bridge
1%

l.SA

2A

2A

0.2SA

9.2V IB.4V

9.2V IB.4V

16V 110V

1MHz

1MHz

1MHz

Dual Alternating,
Totem Pole
1.1mA

Dual Alternating,
Totem Pole
0.1mA
Y
y

Dual Alternating,
Totem Pole
0.1mA
Y
y

y

UC3827-1

Multiple Output or
Secondary Side,
High Voltage
Average Current
Output DC-DC
Mode
Converters
Forward, Flyback,
Buck, Boost

Buck Current
Fed Push-pull

1%

B.4V 1B.OV

4%
Floating 1A for
Buck Stage, O.SA
for Push-pull
Drivers
9V 1B.4V

1MHz

SOOkHz

Single, Totem
Pole

Floating Buck,
Push-pull
1mA

N/A
y

y

SO%/SO%

Programmable

Programmable,
-- VOUT

AT- AVo

Tc
PDISP

= VOUT (Vee-VoUT) +Vee Ice

RL
VAEF

Figure 3. Typical Thermal Test Circuit

9-15

-

[1J]

Thermal Characteristics of Surface Mount Packages

sient thermal behavior is critical beyond 10 seconds
then additional curves must be taken. The 'thermal
time constant of the PC board can go out to several
minutes, so a strip chart recorder or computer
based data acquisition system will be required. For
most systems, this additional data is unnecessary.

Some parameters are measured directly while others are derived by curve fitting. Junction to PC
board, and PC board to ambient thermal resistance
are measured by dissipating a constant power.
Allow 15 minutes for the temperature to stabilize.
The change in diode forward voltage and PC board
temperature give the junction to ambient and board
to ambient thermal resistance:
RO-a) = dVO' (TC POISP)
R(b-a) = dTB' POISP
Note that these resistances are based on change in
temperature - ambient is assumed constant for the
duration of the test. These values correlate to R1,
R2, and R3 by:
R1 + R2 = RO-a) - R(b-a)

(1)

R3 = R(b-a)

(2)

T(t) ='POISP [R1(1-e-V't1) + R2(1-e-V't2)

Oata presented in the following section will help in
estimating initial values. This procedure is iterated
until an acceptable curve fit is achieved. C3's value
is iterated only if the measured curve goes out to
several minutes. Figure 5 is a typical measured and
calculated junction temperature versus time curve.
A logarithmic time axis aids in curve fitting by
spreading data points evenly.
40

35
30

iJ

(3)

~

.

."111

~

~~

JI. IW"

4T(maas)
4T(calc)

15
10

5
0

Iici

"vo

f'.....

I"

...t

T

.,.~

25

'e2D

'"
1-"""""

(4)

+ R3(1-e-Vt'3)]

The thermal capacitance of the die is measured by
applying a pulsed load and recording the junction
temperature waveform. Varying the dissipation
pulse width allows observation of each capacitance's effect, although only the die's thermal
capacitance can be measured directly. A typical
1Oms transient dissipation waveform is. shown in figure 4. The thermal time constant of the die is on the
order of 30ms. To minimize exponential decay error,
the slope of the waveform is measured at (t) = 3ms.
The die's thermal capacitance is then:
C1 = POISP dtTC' dVO

The remaining parameters are determined by curve
fitting. Visual comparison of measured versus calculated curves is easily done with a spread sheet
program. Measured junction temperature versus
time data (4 points per decade is sufficient) is
entered into the spread sheet. Junction temperature
is then calculated at each point with estimated values for R2 and C2 and C3 using:

d

::l

51

limo (sec.)

Figure 5. Juction Tempereture versus Time for FQP48
Package Dissipating 1W•

.........

......
2

Typical Data

L

VERTICAL: (l)Vo.lmVIDIV
(2) POISP' lW
HORIZONTAL: 2msIDIV

Figure 4: 1Oms Trensient Dissipation Waveform

Transient waveforms should also be taken for
100ms, 1s, and 10s dissipation intervals to generate
an accurate temperature versus time curve. If tran-

The preceding technique was used to characterize
two devices in nine different packages. Five different
PC board types were also tested to provide relative
comparison. This information should be used to help
initially determine package, PC board type, and layout. It must be stressed that this typical data should
not substitute for a rigorous thermal analysis of the
actual application.

9-16

-

O::D

Thermal Characteristics of Surface Mount Packages

Figure 6 shows model values and time constants
versus package type, mounted on an aluminum PC
board [1]. Junction to ambient thermal resistance is
also shown to indicate overall steady state thermal
performance. All data was taken with one watt dissipated. The values that were determined by curve fitting result in a fairly conservative model. Values
were chosen which tended to predict higher temperature than actually measured where errors could
not be eliminated. As indicated, two devices were
used for testing. At 7,500 square mils, the UC3730
is representative of the smaller dies typically packaged in 08, 014,.and DW16 packages. The UC3173
is 16,500 square mils, and is typical of the dies packaged in the other larger packages.
Both devices were packaged in the OW16 to isolate
the effect of die size. The UC1730's smaller die
increased R2 by about 30%. Interpolating between
these two data points is difficult since the relationship between die size and thermal resistance is nonlinear. Curves are available which account for this
dimensional difference [2], although the actual conditions differ and are more complicated than the
configuration used to generate the curves.
Fortunately, the resulting error will be small in most
applications. Conservatively estimating R2 will minimally impact system size, but if a more accurate
value is required the actual device can be characterized on a test PC board.

Figure 7 illustrates the power lead frame's dramatic
improvement in thermal performance over standard
lead frames by comparing the junction to ambient
thermal resistances of the QP28 to the Q28, and the
FQP48 to the FQ48. Standard lead frames connect
the die to the leads thermally through the epoxy
molding compound. Power lead frame packages
incorporate a single piece for die attachment and
ground leads. This uninterrupted, high thermal conductivity path offers a significant improvement over
standard lead frames. Occasionally a stiffer but less
conductive alloy is used for standard lead frames.
The FQ48's poorer thermal performance is partially
caused by the lower conductivity alloy.
Printed circuit board design significantly affects the
overall thermal performance of the system, particularly with the power lead frame packages. The
UC3173 in the DWP28 package was used to

:~ IJ-------------~

B
Ji

-m
~

IA------------

60

11-------

50
40
30

J:
028

FQ48

OP28

FOP48

Package

Figure 7. Power lead frames significantly reduce thermal
resistance.

9-17

Thermal Characteristics of Surface Mount Packages
compare PC board thermal performance. Five difPC board types were evaluated with one watt
dissipated:

~rent

-

[1[J

unconnected. The inner ground plane is connected
to the small component side ground plane through
16 feed-throughs.

1. Single side 1 oz. copper, 0.062 aluminum
.As expected, the aluminum PC board's significantly
2. Single side 1 oz. copper, 0.062· FR4 epoxy fiber- higher specific heat results in nearly an order of
magnitude increase in thermal capacitance.
glass
Surprisingly the four layer 0.062 board's thermal
3. Single side 2 oz. copper, 0.062 FR4 epoxy fiber- resistance is nearly as low as the aluminum board's,
glass
indicating good heat distribution through the inner
4. Four layer (signal, ground, Vcc, signal) 1 oz. cop- , planes. Note that although the Vcc plane is unconper, 0.031 FR4 epoxy fiberglass
nected, it does help distribute the heat acro~ .the
6. Four layer (signal, ground, Vcc, signal) 1 oz. cop~ board. Conduction or forced air COOling is necessary
to fully exploit the aluminum board's capability.
per, 0.062 FR4 epoxy fiberglass
. Summary
A method for accurately modeling the the~mal
behavior of a surface mounted IC has been presented. The model relies on measured data, insuring excellent correlation to the physical system.
Typical thermal behavior of nine different packages
and five different PC boards were also presented,
indicating relative thermal performance differences.
Optimum thermal system design is achievable using
the techniques and data presented.

8. Board to ambient thermal resistance and .
capacitance versus PC board type for DWP28 package
dissipating 1W.
.

The thermal resistance, capacitance, and time constants for the five PC boards are shown in figure 8.
The PC board layouts used for test/ngare shown in
figure 9. Only the component side is shown for the
four layer boards. The baCk side, whiCh has 10 mil
traces on 60 mH centers to provide a typical amount
of interconnect copPer, and the Vcc plane were

References
1. Thermal Clad insulated metal substrates, The
Bergquist Company, 6300 Edina Industrial
Blvd., Minneapolis, MN 66439, 612-835-2322
2. R. Tummala, E. Rymaszewski, "Microelectronics Packaging Handbook", Van
Nostrand Reinhold, 1989, pp173-179

4 Layer-Component Side

Single Sided

II-----~-

2.0"

Figure 9. Test PC Board Layouts (SOIC 28DWP)

9-18

2.5"--------1

-

0

P ac ka ge 0 rawmgs

1-

8-PIN PLASTIC DIP - N PACKAGE SUFFIX
PIN 1

DIMENSIONS
INCHES

MILUMETERS

MIN

MAX

MIN

A

.245

.260

6.22

6.60

1

8

.320

AOO

9.40

10.16

1

C

-

Cl
C2
D
E

MAX

.210

-

.125

.150

3.18

.015

.055

0.38

lAO

2

.300

.325

7.62

8.26

3

.1008SC

d1'~

NOTES

5.33
3.81

2.548SC

F

.014

.022

0.35

0.5&

F1

.070

1.14

1.78

F2

.045
.008

.014

0.20

0.35

G

.300

.400

10.16

H

.005

-

7.62

L

.115

.160

0.13

-

2.92

4.06

L8J

4

5

~mHH #=

-~j

SEATING PLANE

"
NOlES:
1. 'A' AND '8' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.

t

I~

~.'~

Fl

-

F

-

[DJ

'

~
LG~

2. 'C2' SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.
3 'D' SHALL BE MEASURED WITH THE LEADS CONSTRAINED TO BE PERPENDICULAR
TO THE BASE PLANE.

4. THE BASIC LEAD SPACING IS 0.100 IN. BETWEEN CENlERLINES. EACH LEAD
CENlERLINE SHALL BE LOCATED WITHIN ±O.010 IN. OF ITS EXACT TRUE POsmON.
5. 'G' SHALL BE MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED.
6. CONTRQLUNG DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.

14-PIN PLASTIC DIP - N PACKAGE SUFFIX
PIN 1

DIMENSIONS
INCHES
MIN MAX

MILLIMETERS
MIN

MAX

A

.245

.260

6.22

6.60

1

B

.745

.775

18.92

19.68

1

C

-

.210

-

Cl

.125

.150

3.18

3.81

C2

.015

lAO

2

.300

.055
.325

0.38

D

7.62

8.26

3

E

.100 BSC

c::::)f~~

NOTES

5.33

2.548SC

F

.014

.022

0.35

0.5&

F1

.070

1.14

1.78

F2

.045
.008

.014

0.20

0.35

G

.300

.400

7.62

10.16

H

.005

-

0.13

-

L

.115

.160

2.92

4.06

C83

4

5

t

l-fl1#
~
"__ L
_,_I
ll-D-O:[]-{ 1-[

BASE PLANE - SEATING PLANE

U~

-

NOTES:
1. 'A' AND 'B' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.

U'

Fl
-

2. 'C2' SHALL BE MEASURED FROM THE SEATING ~LANE TO THE BASE PLANE.
3 'D' SHALL BE MEASURED
TO THE BASE PLANE.

[DJ

wmt THE LEADZRAlNED TO BE PERPENDICULAR

4. THE BASIC LEAD SPACING IS 0.100 IN. BE
EN CENTERLINES. EACH LEAD
CENTERLINE SHALL BE LOCAlED WITHIN ±O.OlD IN. OF ITS EXACT TRUE POSIT10N.
5. 'G' SHALL BE MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED.
6. CONTROLLING DIMENSION: INCHES. MILLIMElERS SHOWN FOR REFERENCE ONLY.

9-19

F

LG~

-

O::D-

Pac k age D rawmgs

16-PIN PLASTIC DIP - N PACKAGE SUFFIX
DIMENSIONS

A
B
C
C1
C2
D
E
F
F1
F2
G
H
L

INCHES
IIIN MAX
.245 .280
.745 .775
.210
.125 .150
.015 .055
.300 .325
.IOUBSC
.014 .022
.045 .07U
.ooa .014
.300 .400
.005
.115 .150

MILLIMETERS
MIN MAX
8.22 8.80
18.82 19.88
5.33
3.18 3.81
0.38 1.40
7.82 8.26
2.54SSC
0.35 0.58
1.14 1.78
0.20 0.35
7.62 10.18
0.13
2.82 4.08

NOTES

4

NOle!:
1. 'A' AND'S' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.

2. 'C2' SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.
3 'D' SHALL BE MEASURED WITH THE LEADS CONSTRAINED TO BE PERPENDICULAR
TO THE BASE PLANE.
4. THE BASIC LEAD SPACING IS 0.100 IN. BETWEEN CENTERLINES. EACH LEAD
CENTERLINE SHALL BE LOCATED WITHIN ±G.Ol0 IN. OF ITS EXACT TRUE POSmON.
5. 'G' SHALL BE MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED.
6. CONTROLLING DIMENSION: INCHES. MIWMETERS SHOWN FOR REFERENCE ONLY.

18-PIN PLASTIC DIP - N PACKAGE SUFFIX

e:::::: )i'~
PIN 1

DIMENSIONS

A
B
C
Cl
C2
D
E
F
F1
F2
G
H
L

INCHES
MIN MAX
.245 .280
.880 .1120
.210
.125 .150
.015 .055
.300 .325
.IOUBSC
.014 .022
.045 •070
.008 .014
.300 .400

-

.00&
.11&

-

.160

MILLIMETERS NOTES
MIN MAX
8.22 8.60
1
22.81 23.38
1
5.33
3.81
3.18
Q.38
1.40
2
7.62 8.26
3
2.54BSC
4
0.35 0.68
1.14 1.78
0.20 0.35
7.82 10.18
&
0.13
2.92 4.0&

-

-

CB~

.~
se!~::~:~-, l j~' i ~ ,

NOTES:
1. 'A' AND 'B' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.

2. 'C2' SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.
3. 'D' SHALL BE MEASURED WITH THE LEADS CONSTRAINED TO BE PERPENDICULAR
TO THE BASE PLANE.
4. THE BASIC LEAD SPACING IS 0.100 IN. BETWEEN CENTERLINES. EACH LEAD
CENTERLINE SHALL BE LOCATED WITHIN ±G.Ol0 IN. OF ITS EXACT TRUE POSITION.
5. 'G' SHALL BE MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED.
6. CONTROWNG DIMENSION: INCHES. MIWMETERS SHOWN FOR REFERENCE ONLY.

9-20

,;

,

~DJ

~

LG~

.

-Odl

Package Drawings

20-PIN PLASTIC DIP - N PACKAGE SUFFIX
DIMENSIONS
INCHES
MIN

MAX

MILLIMETERS
MIN

NOTES

MAX

A

.245

.260

6.22

6.60

1

B

1.010

1.030

25.65

26.16

1

C

-

-

5.33

Cl

.125

.150

3.18

3.81

C2

.015

.055

0.38

1.40

2

D

.300

.325

7.62

8.26

3

E

.210

.100BSC

2.54BSC
0.35

4

0.56

F

.014

.022

Fl

.045

.070

1.14

1.78

F2

.008

.014

0.20

0.35

G

.300

.400

10.16

.005

-

7.62

H
L

.115

.160

0.13

-

2.92

4.06

5

NOTES:
1. 'A' AND 'B' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.
2. 'C2' SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.
3. 'D' SHALL BE MEASURED WITH THE LEADS CONSTRAINED TO BE PERPENDICULAR
TO THE BASE PLANE.
4. THE BASIC LEAD SPACING IS 0.100 IN. BETWEEN CENTERLINES. EACH LEAD
CENTERLINE SHALL BE LOCATED WITHIN ±O.010 IN. OF ITS EXACT TRUE POSmON.
5. 'G' SHALL BE MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED.
6. CONTROLLING DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.

24-PIN PLASTIC DIP - N PACKAGE SUFFIX
DIMENSIONS
INCHES
A
B

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

.500

.550

12.70

13.97

1

1.230 1.270

31.24

32.26

1

C

-

Cl

.125

.150

C2

.015

.055

0.38

1.40

2

.625
.100BSC

15.24

15.87

3

D
E

.210

.800

3.18

5.33
3.81

2.S4BSC

F

.014

.022

Fl

.045
.008

G

.800

.675

H

.005

-

0.13

-

L

.115

.160

2.92

4.06

F2

0.35

0.56

.070

1.14

1.78

.014

0.20

0.35

15.24 17.15

4

5

C:::::::::)1~! , r.= :=:,;
-~~1~ r t.J
I.

•

-:1

I

NOTES:
1. 'N AND 'B' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.
2. 'C2' SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.
3 'D' SHALL BE MEASURED WITH THE LEADS CONSTRAINED TO BE PERPENDICULAR
TO THE BASE PLANE.
4. THE BASIC LEAD SPACING IS 0.100 IN. BETWEEN CENTERLINES. EACH LEAD
CENTERLINE SHALL BE LOCATED WITHIN ±O.010 IN. OF ITS EXACT TRUE POSITION.
5. 'G' SHALL BE MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED.
6. CONTROLLING DIMENSIONS: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.

9-21

j

Package Drawings

0

28-PIN PLASTIC DIP - N PACKAGE SUFFIX
1

DIMENSlDNS

A
B
C
Cl
C2
D
E
F
F1
F2
G
H
L

INCHES
MILLIMETERS NOTES
MIN MAX MIN MAX
.500 .560 12.70 13.97
1
1.380 1.470 35.10 37.34
1
.210
5.33
.125 .150 3.18 3.81
.015 .055
0.38 lAO
2
.800 .525 15.24 15.87
3
.100 BSC
2.54BSC
4
.G14 .022
0.35 0.55
.045 .1170
1.14 1.78
.008 .014
0.20 0.35
.&00 .675 15.24 17.15
5
.DOS
0.13
.115 .160 2.82 4.05

-

-

-

-

j

2. 'C2' SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.

4 THE BASIC LEAD SPACING IS 0.100 IN. BETWEEN CENTERLINES. EACH LEAD
CENTERLINE SHALL BE LDCATED WITHIN ~.010 IN. OF ITS EXACT TRUE POSITIDN.
5. 'G' SHALL BE MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED.
6. CONTROLLING DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.

20-PIN PLASTIC PLCC SURFACE MOUNT - Q PACKAGE SUFFIX
PIN NO.1

DIMENSIONS

-

C'=:1

~~~rnt~J

3. 'D' SHALL BE MEASURED WITH THE LEADS CONSTRAINED TO BE PERPENDICULAR
TO THE BASE PLANE.

A
Al
B
C
Cl
D
E
F
G

PIN 1

c:::::::::::~I.
·
~I

NOTES:
1. 'A' AND 'B' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.00& IN. PER SIDE.

INCHES
MIN MAX
.385 .385
.350 .355
.013 .021
.170 .160
.100 .110
.000BSC
.025 I .D32
.020
.290 .330

-

~

MILLIMETERS NOTES
MIN
MAX
9.78 10.03
8.89
9.D4
1
0.33
0.53
4.32
4.57
2.54
2.79
1.27BSC
2
0.81
0.66
3,4
0.51 I
7.37
8.38

PIN NO.1 INDEX

-

NOTES:
1. 'AI' DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.
2. THE BASIC LEAD SPACING IS 0.050 IN. BETWEEN CENTERLINE$. EACH LEAD
"
CENTERLINE SHALL BE LOCATED WITHIN ~.OO4IN. OF ITS EXACT TRUE POSITION.
3. 'P IS MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.
4. LEADS SHALL BE COPLANAR WITHIN 0.004 IN. AT THE SEATING PLANE.
5. CONTROLLING DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.

9-22

28-PIN PLASTIC PlCC SURFACE MOUNT - 0, OP PACKAGE SUFFIX
PIN NO. 1

DIMENSIONS
INCHES
MAX

MIN

MAX

.485
.450

.495
.456

12.32

12.57

Al

11.43

11.58

B

.013

.021

0.33

0.53

C

.170

.180

4.32

4.57

Cl

.100

.110

2.54

2.79

A

D

.050BSC

1.27BSC

.02G
.020

.032

0.88

F

-

0.51

G

.390

.430

9.91

E

PIN NO.1 INDEX

MILLIMETERS NOTES

MIN

I

1

2

0.81

-

3,4

10.92

NOTES:
1. 'AI' DOES NOTINCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.
2. THE BASIC LEAD SPACING IS 0.050 IN. BETWEEN CENTERLINES. EACH LEAD
CENTERLINE SHALL BE LOCATED WITHIN ±D.OO4IN. OF ITS EXACT TRUE POSITION.
3. 'F'IS MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.
4. LEADS SHALL BE COPLANAR WITHIN 0.004 IN. AT THE SEATING PLANE.
5. CONTROLLING DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.

44-PIN PLASTIC PlCC SURFACE MOUNT - 0, OP PACKAGE SUFFIX
DIMENSIONS

A
Al
B
C
Cl
D
E
F
G

INCHES
MIN MAX
.685 .695

MILLIMETER
MIN MAX
17.40 17.65
.650 .656 16.51 16.88
0.53
.013
.021
0.33
.165 .180
4.19 4.57
.095
.110
2.41
2.79
.000BSC
1.27BSC
.026
.032 0.66 0.81
.020
0.51
.590 .630 14.99 16.00

-

-

[1JJ

Package Drawings

NOTES
PIN 1 INDEX
BASE PLANE

1

2
3,4

EJL
NOTES:
1. 'Al' DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.
2. THE BASIC LEAD SPACING IS 0.050 IN. BETWEEN CENTERLINES. EACH LEAD
CENTERLINE SHALL BE LOCATED WITHIN ±D.OO4IN. OF ITS EXACT TRUE POSITION.
3. 'P IS MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.
4. LEADS SHALL BE COPLANAR WITHIN 0.004 IN. AT THE SEATING PLANE.
5. CONTROLLING DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.

9-23

I I
I I
I-D

--I

-

P ac k age Drawmgs
a-PIN SOIC SURFACE MOUNT - 0, OP PACKAGE SUFFIX
1

DIMENSIONS
INCHES
MIN MAX
A
A1

.244
.150
.168
.189
.196
.D53
.069
.004 .oD9
.000BSC
.014 .019
.OD7 .010
.016
.035
0"
.228

B
C
C1
E
F
G
H
8

••

MILLIMETERS
MIN MAX
5.80
6.20
3.80

4.00

4.80
1.35
0.10

4.98
1.75
0.23

1.27 BSC
0.35
0.48
0.19
0.41
0"

0.25
0.89

••

~

~ ~nl

~

~~

::Y~tJj
CI

~CI~~&~.

~
. .ul
~~~ b: &~L
!

--;\

BEATING

1

NOTES:

II

PLANE

,&, 'A1' AND 'B' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS
SHALL NOT EXCEED 0.008 IN. PER SIDE.

LEADS SI1ALL BE COPLANAR WITHIN 0.004 IN. AT THE SEA11NG PLANE.
THE BASIC LEAD SPACING IS 0.060 IN. BETWEEN CENTERLINE&. EACH LEAD CENTERLINE SHALL
BE LOCATED WlFHIN >0.004 IN. OF ITS EXACT TRUE POSITION.
4. CONTROLLING DIMENSION: INCHes. MIWMETERS SHOWN FOR REFERENCE ONLY.
DIMENSION 'P DOES NOT INCLUDE DAMSAR PROTRUSION. THE DAMSAR PROTRUSION(S) SHALL
NOT CAUSE THE LEAD WIDTH 10 EXCEED 'F' MAXIMUM BY MORE THAN 0.003 IN. DAMBAR CAN
NOT BE LDCATED ON THE LOWER RADIUS OR THE LEAD FOOT.

2.

&
,&,.

~

THESE DIMENSIONS APPLY 10 THE FLAT SECTION OF THE LEAD BETWEEN 0.004 IN. AND 11.010 IN. FROM THE LEAD np.
'C1' IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE 10 THE LOWEST POINT OF THE PACKAGE BODY (BASE PLANE).

14-PIN SOIC SURFACE MOUNT - 0 PACKAGE SUFFIX
DIMENSIONS
INCHES
MIN
MAX
.228
.244
.160
.158
.336
.344
.063
.069
.004
.009
.G5OBSC
.014
.019
.007
.010
.016
.035
8·
II"

A
A1
B
C
C1
E
F
.G
H
9

MILLIMETERS
MIN
MAX
5.80
6.20
3.80
4.00
8.56
8.75
1.75
1.35
0.10
0.22
1.27BSC
0.38
0.49
0.19
0.25
OA1
0.99
o·
8"

'1

PIN 1
INDEX AREA

c:: ::~
14

&-.

&

_ E ....

j
'I

i
I

III UU

-t-"F

u: lr1[

f

t

t

B~ ~1&

NOTES:

~

&bt. k7

SEAllNG PLANE

~ 'A1' AND 'B' DO NOT INCWDE MOLD FLASH OR PROTRUSIONS, MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED o.oos IN. PER SIDE.
2.

&
4.

&
~
7

LEADS SHALL BE COPLANAR WITHIN 0.004 IN. AT THE SEAllNG PLANE.
THE BASIC LEAD SPACING IS 0.050 IN. BETWEEN CENTERLINE&. EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN ±O.D04IN.
OF ITS EXACT TRUE POSmON.
CONTROLLING DIMENSION: INCHES, MILLIMETERS SHOWN FOR REFERENCE ONLY.
DIMENSION 'P DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE LEAD WIDTH TO
EXCEED 'P MAXIMUM BY MORE THAN 0,003 IN. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.004 IN. AND 0.010 IN. FROM THE LEAD TIP.
'C1' IS DEFINED AS THE DISTANCE FROM THE SEAllNG PLANE TO THE LOWEST POINT OF THE PACKAGE BODY (BASE PLANE).

9-24

-

1·-

-

Package Drawings

16-PIN SOIC SURFACE MOUNT - D, DP, DS PACKAGE SUFFIX

'1

DIMENSIONS
INCHES
MIN

MAX

MIN

MAX

A

.228

.244

5.80

6.20

AI

.150

.158

3.80

4.00
9.98

B

.386

.393

9.80

C

.053

1.35

1.75

Cl

.004

.089
.009

0.10

0.22

16

E

.000BSC

F

.014

.019

0.36

0.48

&,

G

.007

.010

0.19

0.25

-E--

H

.016

.035

0.41

0.69

e

0°

8°

0°

8°

1.27BSC

&:,.
..... IJ--F

::

W ILU

1

If [lfJf 1Jj
B

1
~,
&.

&

&t(" 11.7

SEATING PLANE

NOTES:

&

PIN'
INDEX AREA

I~::::: :~j

MILLIMETERS

'AI' AND 'B' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.

2.

LEADS SHALL BE COPLANAR WITHIN 0.004 IN. AT THE SEATING PLANE.

~ THE BASIC LEAD SPACING IS 0.050 IN. BETWEEN CENTERLINES.

EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN ±D.OO4IN.

OF ITS EXACT TRUE POSmON.

4. CONTROLLING DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.

&

DIMENSION 'F' DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
'F' MAXIMUM BY MORE THAN 0.003 IN. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS. OR THE LEAD FOOT.

~

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.004 IN. AND 0.010 IN. FROM THE LEAD TIP.
'Cl'lS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY (BASE PLANE).

16-PIN SOIC SURFACE MOUNT - DW PACKAGE SUFFIX
1

DIMENSIONS
INCHES
MIN
MAX

MILLIMETERS
MIN

MAX

10.00

10.64

A

.394

AI

.292

.299

7.42

7.59

B

A13

10.24

10.49

C

A03
.097

.104

2M

2.64

Cl

.004

.011

0.10

0.28

A19

E

.050 BSC

F

.014

.019

0.36

0.48

G

.009

.012

0.23

1.27BSC
0.30

H

.018

.035

0.46

0.69

e

0°

8°

0"

8°

~

t:0

UUUUUUUU
&,

&:,.

,'r ~5'

NOTES:

2.

~
4.

~

t

&A.

f..---

PIN.
INDEX AREA

A

jj

16

,

--Effi~&bt
&.~
&

&

k+-

RRRRRRRR

SEATING PLANE

)~

7

H

'AI' AND 'B' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.
LEADS SHALL BE COPLANAR WITHIN 0.004 IN. AT THE SEATING PLANE.
THE BASIC LEAD SPACING IS 0.050 IN. BETWEEN CENTERLINES. EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN ±D.OO4IN.
OF ITS EXACT TRUE posmON.
CONTROWNG DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.
DIMENSION 'F' DOES-NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
'F' MAXIMUM BY MORE THAN 0.003 IN. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT.
THESE DIMENSIONS APPLY TO THE FLAT SEenON OF THE LEAD BETWEEN 0.004 IN. AND 0.010 IN. FROM THE LEAD TIP.
'Cl' IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY (BASE PLANE~

9-25

1-

-

[1!J

Package Drawings

18-PIN SOIC SURFACE MOUNT - DW PACKAGE SUFFIX
DIMENSiONS
INCHES
MIN
MAX
A
AI
B
C
C1
E

.394

A19

.292
AS3
IW1

.299
.482

.104
.D04
.011
.000BSC
.014
.019
.D09
.012
.01.
.035

F

G
H
9

0"

••

MIWMETERS
MIN
MAX
10.00
10.114
7.42
7.58
11.51
11.73
2AS
2.64
0.10
0.28
I.27BSC
0.36
OAS
0.23
0.30
OAS
0.89
O·

PIN.

"'DEX .....

,.

..

NOTES:

SEATING PLANE

.&. 'AI' AND 'B' DO NOT INCLUOE MOLD FLABH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.
2. LEADS SHALL BE COPLANAR WITHIN 0.004 IN. AT THE SEATING PLANE.
it THE
BASIC LEAD SPACING IS 0.050 IN. BETWEEN CENTERLINES. EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN flI.OO4IN.
OF ITS EXACT TRUE POSITION.
.
CONTROLLING DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.

4.

&
&

DIMENSION 'F' DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE LEAD WIOTH TO EXCEED
'F' MAXIMUM BY MORE THAN 0.003 IN. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.004 IN. AND 0.010 IN. FROM THE LEAD TIP.

~

'Cl'1S DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY (BABE PLANE).

20-PIN SOIC SURFACE MOUNT - DW PACKAGE SUFFIX
DIMENSIONS
INCHES
MIN
MAX
.394
.419
.292
.299
.504
.511
.097
.104
.004
.011
.000BSC
.014
.019
.009
.012
.018
.035
0"
a-

A
AI
B
C
Cl
E
F

G
H
9

MILLIMETERS
MIN
MAX
10.00
10.94
7.42
7.58
12.80
12.98
2AS
2.94
0.10
0.28
1.27BSC
OAS
0.36
0.30
G.23
0.41
0.89
li"
a-

PIN 1
INDEX_

20

c

~-------8------~

&.
SEATING PLANE

NOTES:

.&. 'AI' AND 'B' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.
2. LEADS SHALL BE COPLANAR WITHIN 0.004 IN. AT THE SEATING PLANE.
& THE BASIC LEAD SPACING IS O.OSO IN. BETWEEN CENTERLINES. EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN flI.OO4IN.
OF ITS EXACT TRUE POSITION.

4. CONTROLLING DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.

&

DIMENSION 'F' DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSlON(S) SHALL NOT CAUSE THE LEAD WIOTH TO EXCEED
'F' MAXIMUM BY MORE THAN 0.003 IN. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT.

& THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.004 IN. AND 0.010 IN. FROM THE LEAD TIP.

Ii;;. 'C1' IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY (BASE PLANE).

9-26

-

Qd]

Package Drawings

24-PIN SOIC SURFACE MOUNT - OW PACKAGE SUFFIX
DIMENSIONS
INCHES

MILLIMETERS

MIN

MAX

MIN

MAX

.394

.419

10.00

10.64

A1

.292

.299

7.42

7.59

B

.598

15.20

15AO

C

.097

.606
.104

2.46

2.64

C1

.004
.011
.050 BSC

0.10

0.28

E

A

PIN 1

INDEX AREA

1.27BSC

F

.014

.019

0.36

G

.009

.012

0.23

0.30

H

.019

.035

0.46

0.89

8

0°

8°

0°

8°

0.48

~~--------a----------~

ill

NOTES:

&
&

SEAnNG PLANE

'A1' AND 'B' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.

2.

LEADS SHALL BE COPLANAR WITHIN 0.004 IN. AT THE SEATING PLANE.
THE BASIC LEAD SPACING IS 0.050 IN. BETWEEN CENTERLINES. EACH LEAD CENTERLINE SHALL liE LOCATED WITHIN ±O.OO4IN.
OF ITS EXACT TRUE POSITION.

4.

CONTROLLING DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.

~

DIMENSION 'F' DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
'F' MAXIMUM BY MORE THAN 0.003 IN. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT.

&

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.004 IN. AND 0.010 IN. FROM THE LEAD TIP.

~

'C1'IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY (BASE PLANE).

28-PIN SOIC SURFACE MOUNT - OW, OWP PACKAGE SUFFIX
DIMENSIONS
INCHES

MILUMETERS

MIN

MAX

MIN

MAX

A

.394

.419

10.00

10.64

A1

.292

.299

7.42

7.59

B

.698

.712

17.73

18.08

C

.097

.104

2.46

2.64

C1

.004
.011
.050 asc

0.10

0.28

E

PIN 1

INDEX AREA

1.27BSC

F

.014

.019

0.36

0.48

G

.009

.012

0.23

0.30

H

.018

.035

0.46

0.89

9

0"

8°

0"

8°

~~--------B----------~

ill
NOTES:

ill
2.
Lt

'A1' AND 'B' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.
LEADS SHALL BE COPLANAR WITHIN 0.004 IN. AT THE SEATING PLANE.
THE BASIC LEAD SPACING IS 0.050 IN. BETWEEN CENTERLINES. EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN ±O.OO4IN.
OF ITS EXACT TRUE POSITION.

4. CONTROLUNG DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.

&
ffi

DIMENSION 'F' DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSlON(S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
'F' MAXIMUM BY MORE THAN 0.003 IN. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.004 IN. AND 0.0'0 IN. FROM THE LEAD TIP.

I!::, 'C"

IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY (BASE PLANE).

9-27

-

[1JJ-

Package Drawings

8-PIN CERAMIC DIP - J PACKAGE SUFFIX
BASE-

DIMENSIONS
INCHES
MIN
MAX

PLANE

MIWMETERS
MIN MAX

A1

0.290 D.320
0.220 0.310

B

OAOS

10.29

C

5.08

o

0.200
0.015 0._

0.38

E

0.014 0.038

0.38

E1

0.045 0.0&5

1.14

F

0.008 0.018

0.20

A

G
H

0.100Bse

O.oos 1 0.125

Q.200

7.37
5.59

NOTES

8.13

7

7$1

4

.....

C

I--

___ J > - -

-

-r- D

E

;r-J
~211l
- '-

1.52
0.88
1.85
0.41

2.54 BSC
0.131 3.18
&.08

El

8EA~PLANE

NOTES:
1. INDEX AREA: A NOTCH OR A PIN ONE IDENTIFlCAnON MARK SHALL BE LOCATED ADJACENT TO PIN ONE.
TitE MANUFAClURER'S IDENTIFICATION SHALL NOT BE USED AS A PIN ONE IDENTIFICAnON MARK.
2. THE MINIMUM LIMIT FOR DIMENSION "E1" MAY BE 0.023 (D.58mm) FOR LEADS NUIIBER 1,4, 5 AND 8 ONLY.
3. DIMENSION "0" SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.
4. THIS DIMENSION ALLOWS FOR OFF-CENTER LID, MENISCUS AND GLASS OVERRUN.
5. THE BASIC PIN SPACING IS 0.1OU (2.54mm) BETWEEN CENTERLINES. EACH PIN CENTERLINE SHALL BE LOCATED
WITHIN ±G.010 (O.25mm) OF ITS EXACT TRUE PosmoN.

I. APPLIES TO ALL FOUR CORNERS (LEADS NUMBER " 4, 5 AND 8).
7. DIMENSION "A" SHALL BE MEASURED AT THE CENTERLINE OF THE LEADS WHEN" =11".
8. THE MAXIMUM LIMITS OF DIMENSIONS "E" AND "F" SHALL BE MEASURED AT THE CENTER OF THE FLAT WHEN SOLDER DIP IS APPLIED.
9. CONTROLLING DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.
10 THE SEATING PLANE IS LOCATED AT THE LOWEST POINT ON THE LEAD AT WHICH THE LEAD WIDTH EXCEEDS
0.040 (1.02mm) MINIMUM, EXCLUDING ANY HALF LEADS AT THE PACKAGE ENDS.

14-PIN CERAMIC DIP - J PACKAGE SUFFIX

.[}~

DIMENSIONS
INCHES
MILLIMETERS
MIN
MAX MIN MAX
A

0.290 0.320

7Z7

A1

0.220 0.310

5.59

B
C

0.785
Q.200

0

0.015 0.060

0.38

1.52

E
E1

0.014 0.G2S
0.045 O.OIS

0.39
1.14

0.66

F

0.008 0.018

0.20

Q.48

G
H

0.1OUBse

"

0.005 1 0.125 1 0.200
II" 1 15'

NOTES

8.13

7.87
19.94

4

5.08
8

1.65

2.S4Bse
0.13
3.18

5.08

II"

15'

'J
~
El

SEA~LANE

I

3-P~lINDD

A~l~,

NOTES:
1. INDEX AREA: A NOTCH OR A PIN ONE IDENnFICAnON MARK SHALL BE LOCATED ADJACENT TO PIN ONE.
THE MANUFACTURER'S IDENTIFICAnON SHALL NOT BE USED AS A PIN ONE IDENnFlCAnON MARK.
2. THE MINIMUM LIMIT FOR DIMENSION "E1" MAY BE 0.023 (0.58mm) FOR LEADS NUMBER " 4, 5 AND 8 ONLY.
3. DIMENSION "D" SHALL BE MEASURED FROM THE SEAnNG PLANE TO THE BASE PLANE.
4. THIS DIMENSION ALLOWS FOR OFF-CENTER LID, MENISCUS AND GLASS OVERRUN.
5. THE BASIC PIN SPACING IS 0.100 (2.54mm) BETWEEN CENTERLINES. EACH PIN CENTERLINE SHALL BE LOCATED
WITHIN ±G.o10 (O.25mm) OF ITS EXACT TRUE POSlnON.
6. APPLIES TO ALL FOUR CORNERS (LEADS NUMBER " 4, 5 AND 8).
7. DIMENSION "A" SHALL BE MEASURED AT THE CENTERLINE OF THE LEADS WHEN" _II"..
6. THE MAXIMUM LIMITS OF DIMENSIONS "E" AND "F" SHALL BE MEASURED AT THE CENTER OF THE FLAT WHEN SOLDER DIP IS APPLIED.
9. CONTROLLING DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE oNLY.
10 THE SEATING PLANE IS LOCATED AT THE LOWEST POINT ON THE LEAD AT WHICH THE LEAD WIDTH EXCEEDS
0.040 (1.02mm) MINIMUM, EXCLUDING ANY HALF LEADS AT THE PACKAGE ENDS.

-0dJ

Package Drawings

16-PIN CERAMIC DIP - J PACKAGE SUFFIX
BASE

DIMENSIONS

A
Al
B
C
D
E
El
F
Cl
H
J
a

INCHES
MILLIMETERS
MIN MAX MIN MAX
0.290 0.320 7.~ 8.13
0.220 0.310 5.59 7.87
0.840
21.34
O.ZOO
5.08
0.015 O.DBD 0.38 1.52
0.014 0.D28 0.38 0.68
0.045 0.D85 1.14 1.66
0.0D8 0.018 0.20 OAB
2.54BSC
0.100 BSC
0._
0.131 0.125 0.200 3.18 1 5.08
0"
15"
0" 1 15"

-

-

-

NDTES

PLANE

7
4
4

3
8
2
8
5
B

NOTES:
1. INDEX AREA: A NOTCH OR A PIN ONE IDENTIFICATION MARK SHALL BE LOCATED ADJACENT TO PIN ONE.
THE MANUFACTURER'S IDENTIFICATION SHALL NOT BE USED AS A PIN ONE IDENTIFICATION MARK.
2. THE MINIMUM LIMIT FOR DIMENSION "El" MAY BE 0.G23 (0.58mm) FOR LEADS NUMBER 1, 8, 9 AND 18 ONLY.
3. DIMENSION "D" SHALL BE MEASURED FROM THE SEATIN(\ PLANE TO THE BASE PLANE,
4. THIS DIMENSION ALLOWS FOR OFF-CENTER LID, MENISCUS AND GLASS OVERRUN.
S. THE BASIC PIN SPACING IS 0.100 (2.54mm) BETWEEN CENTERUNES. EACH PIN CENTERLINE SHALL BE LOCATED
WITHIN ±a.Ol0 (O.25mm) OF ITS EXACT TRUE POSITION.
6. APPLIES TO ALL FOUR CORNERS (LEADS NUMBER I, 8, 9 AND 18).
7. DIMENSION "A" SHALL BE MEASURED AT THE CENTERLINE OF THE LEADS WHEN a = 0".
B. THE MAXIMUM LIMITS OF DIMENSIONS "E" AND "F" SHALL BE MEASURED AT THE CENTER OF THE FLAT
WHEN SOLDER DIP IS APPLIED.
9. CONTROLLING DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.

&

THE SEATING PLANE IS LOCATED AT THE LOWEST POINT ON THE LEAD AT WHICH THE LEAD WIDTH EXCEEDS
0.040 (l.G2mm) MINIMUM, EXCLUDING ANY HALF LEADS AT THE PACKAGE ENDS.

9·29

-

[1[]

Package Drawings

18-PIN CERAMIC DlP-J PACKAGE SUFFIX
BASE
PLANE

DIMENSIONS

A
AI
B
C
0
E
El
F
G
H
J
IX

INCHES
MIWMETERS
MIN MAX MIN MAX
8.13
0.290 0.320 7.37
0.220 0.310 5.59
7.87
0.980
24.38
&.08
0.200
0.015 0.0&0 0.38
1.52
0.014 0.026 0.38
0.&&
0.045 0.08& 1.14
1.65
0.008 0.018 0.20
0.46
0.100 BBC
2.&4BSC
0.005
0.13
0.125 0.200 3.18
&.0&
0"
IS"
0" I IS"

-

-

NOTES
7
4
4

D

3
8
2
8
5
8

1

J

B

J

El

J

SEATING PLANE

M

NOTES:
1. INDEX AREA: A NOTCH OR A PIN ONE IDENTIFICATION MARK SHALL BE LOCATED ADJACEN"rTC) PIN ONE.
THE MANUFACTURER'S IDENTIFICATION SHALL NOT BE USED AS A PIN ONE IDENTIFICATION MARK. '
THE MINIMUM UMIT FOR DIMENSION "El" MAY BE 0.023 (O.58mm) FOR LEADS NUMBER 1, 9, 10 AND 18 ONLY.
DIMENSION "D" SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.
THIS DIMENSION ALLOWS FOR OFF-CENTER LID, MENISCUS AND GLASS OVERRUN.
THE BASIC PIN SPACING IS 0.100 (2.54mm) BETWEEN CENTERUNES. EACH PIN CENTERUNE SHALL BE,LOCATED
WITHIN ±D.Ol0 (O.25mm) OF ITS EXACT TRUE POSmDN.
&. APPLIES TO ALL FOUR CORNERS (LEADS NUMBER 1, 9, 10 AND 18).
7. DIMENSION "A" SHALL BE MEASURED AT THE CENTERLINE OF THE LEADS WHEN IX = 0".
8. THE MAXIMUM LIMITS OF DIMENSIONS "E" AND "F" SHALL BE MEASURED AT THE CENTER OF THE FLAT WHEN
SOLDER DIP IS APPLIED.
9. CONTROLUNG DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.
,
2.
3.
4.
5.

~ THE SEATING PLANE IS LOCATED AT THE LOWEST POINT ON THE LEAD AT WHICH THE LEAD WIDTH EXCEEDS
0.040 (1.02mm) MINIMUM, EXCLUDING ANY HALF LEADS AT THE PACKAGE ENDS.

9-30

-

[1JJ

Package Drawings

20-PIN CERAMIC DIP - J PACKAGE SUFFIX
BASE
PLANE

DIMENSIONS

A
Al
B
C
D
E
El
F
G
H
J
a

INCHES
MILLIMET1SRS
MIN MAX MIN MAX
0.:190 0.320 7.37 8.13
0.220 0.310 5.58 7m
28.82
1.080
0.:100
5.08
0.015 0.080 0.38
1.52
0.014 0.028 0.36 0.86
0.04& 0.086 1.14 1.8&
0.008 0.018 0.20
0.48
O.I00BSC
2.54BSC
0.00&
0.131 0.125 0.200 3.18
5.0&
15"
0'
0' 1 IS"

-

-

-

NOTES
7
4
4

D

3
8
2
8
5
6

1
J
B

t

f

El

~_J
A

NOTES:
1. INDEX AREA: A NOTCH OR A PIN ONE IDENTIFICATION MARK SHALL BE LOCATED ADJACENT TO PIN ONE.
THE MANUFACTURER'S IDENnFlCATION SHALL NOT BE USED AS A PIN ONE IDENnFICAnON MARK.
2. THE MINIMUM LIMIT FOR DlMENBION 'El' MAY BE 0.023 (O.58mm) FOR LEADS NUMBER 1, 10, 11 AND 20 ONLY.
3. DIMENSION 'D' SHALL BE MEASURED FROM THE SEAnNG PLANE TO THE BASE PLANE.
4. THIS DIMENSION ALLOWS FOR OFF-CENTER LID, MENISCUS AND GLASS OVERRUN.
5. THE BASIC PIN SPACING IS 0.100 (2.54mm) BETWEEN CENTERLINES. EACH PIN CENTERLINE SHALL BE LOCATED
WITHIN :10.010 (O.25mm) OF ITS EXACT TRUE POSITION.
8. APPLIES TO ALL FOUR CORNERS (LEADS NUMBER 1, 10, 11 AND 20~
7. DIMENSION 'A' SHALL BE MEASURED AT THE CENTERLINE OF THE LEADS WHEN a = 0".
8. THE MAXIMUM LIMITS OF DIMENSIONS 'E' AND "F' SHALL BE MEASURED AT THE CENTER OF THE FLAT WHEN
SOLDER DIP IS APPLIED.
9. CONTROLLING DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY,

~ THE SEAnNG PLANE IS LOCATED AT THE LOWEST POINT ON THE LEAD AT WHICH THE LEAD WIDTH EXCEEDS
0.040 (1.02mm) MINIMUM, EXCLUDING ANY HALF LEADS AT THE PACKAGE ENDS.

9,31

H

-

Package Drawings

O:::!J

24-PIN CERAMIC DIP - J PACKAGE SUFFIX
BASE

DIMENSIONS
INCHES

PLANE

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

A

0.590

0.625

14.99

15.88

7

Al

0.515

0.605

13.08

15.37

4

B

1.180

1.260

29.97

32.00

4

-

0.225

-

D

0.015

0.055

0.38

lAO

3

E

0.014

0.026

0.38

0.66

8

El

0.045

0.066

1.14

1.95

2

F

0.008

0.018

0.20

0.48

8

2.54BSC

5

C

G

0.100 BSC

H

0.005

0.066

0.127

J

0.125

0.200

3.18

a

0"

15"

0"

D

5.72

I
I
I

1.95

1

6

5.08

B

15"

J

El

NOTES:
1. INDEX AREA: A NOTCH OR A PIN ONE IDENTIFICATION MARK SHALL BE LOCATED ADJACENT TO PIN ONE.
THE MANUFACllIRER'S IDENTIFICATION SHALL NOT BE USED AS A PIN ONE IDENTIFICATION MARK.
2. THE MINIMUM LIMIT FOR DIMENSION "El" MAY BE 0.023 (O.58mm) FOR LEADS NUMBER 1, 12, 13 AND 24 ONLY.
3. DIMENSION "D" SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.
4. THIS DIMENSION ALLOWS FOR OFF-CENTER LID, MENISCUS AND GLASS OVERRUN.
5. THE BASIC PIN SPACING IS 0.100 (2.54mm) BElWEEN CENTERLINES. EACH PIN CENTERLINE SHALL BE LOCATED
WITHIN fO.Ol0 (0.25mm) OF ITS EXACT TRUE POsmON.
6. APPLIES TO ALL FOUR CORNERS (LEADS NUMBER 1,12,13 AND 24).
7. DIMENSION "A" SHALL BE MEASURED AT THE CENTERLINE OF THE LEADS WHEN a

= 0".

8. THE MAXIMUM LIMITS OF DIMENSIONS "E" AND "F" SHALL BE MEASURED AT THE CENTER OF THE FLAT WHEN
SOLDER DIP IS APPLIED.
9. CONTROLLING DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.
10 THE SEATING PLANE IS LOCATED AT THE LOWEST POINT ON THE LEAD AT WHICH THE LEAD WIDTH EXCEEDS
0.040 (l.02mm) MINIMUM, EXCLUDING ANY HALF LEADS AT THE PACKAGE ENDS.

-

[1f]

Package Drawings

28-PIN CERAMIC DIP - J PACKAGE SUFFIX
BASE
PLANE

DIMENSIONS

A
A1
B
C
D
E
E1
F
G
H
J

a

INCHES
MlLUMETERS
MIN MAX MIN MAX
0.580 0.825 14.89 15.88
0.570 0.805 14.48 15.37
1.380 1'- 35.05 37.08
5.72
0.225
0.015 0.050
0.38 1.52
0.36 0.68
0.014 D.026
1.14 1.85
0.D45 G.085
0._ 0.018
G.20 0.48
2.54BSC
0.1OOBSC
0.127
0.005
3.18
0.126 10.200
5.08
0"
15"
0" I 15"

-

-

-

-

NOTES

7
4
4

D

3
8
2
8
5
6

B

f

E1

SEATING PLANE

~

J

NOTES:
1. INDEX AREA: A NOTCH OR A PIN ONE IDENTIFICATION MARK SHALL BE LOCATED ADJACENT TO PIN ONE. THE
MANUFACTURER'S IDENT IFICATION SHALL NOT BE USED AS A PIN ONE IDENTIFICATION MARK.
2. THE MINIMUM LIMIT FOR DIMENSION "El" MAY BE 0.023 (O.58mm) FOR LEADS NUMBER 1, 14, 15 AND 2B ONLY.
3. DIMENSION "D" SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.
4. THIS DIMENSION ALLOWS FOR OFI<-CENTER LID, MENISCUS AND GLASS OVERRUN.
S. THE BASIC PIN SPACING IS 0.100 (2.54mm) BETWI!EN CENTERLINES. EACH PIN CENTERLINE SHALL BE LOCATED
WITHIN ±G.Ol0 (O.25mm) OF ITS EXACT TRUE POSITION.
6. APPLIES TO ALL FOUR CORNERS (LEADS NUMBER 1, 14, 15 AND 2B).
7. DIMENSION 'A" SHALL BE MEASURED AT THE CENTERLINE OF THE LEADS WHEN a .. 0".
B. THE MAXIMUM LIMITS OF DIMENSIONS 'E" AND "F" SHALL BE MEASURED AT THE CENTER OF THE FLAT WHEN
SOLDER DIP IS APPLIED.
9. CONTROLLING DIMENSION INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.
10 THE SEATING PLANE IS LOCATED AT THE LOWEST POINT ON THE LEAD AT WHICH THE LEAD WIDTH EXCEEDS
0.040 (l.02mm) MINIMUM, EXCLUDING ANY HALF LEADS AT THE PACKAGE ENDS.

9-33

-0dJ-

P ac k age D rawmgs

3-PIN TO-220 PLASTIC - T PACKAGE SUFFIX
DIMENSIONS
INCHES
MIN
MAX

A
Al
8
C
Cl

o
01

E
El
F

G
H
H1

I

.500
.380
.580
.230
.140
.CI45
.020
.045
.139
.014

.oso
.180

.090

MILUMETERS
MIN
MAX

.562

12.70

14.27

.250
.420
.625
.270
.190
.055
.0411
.070
.161
.022
.110
.210
.115

9.66
14.23
5.85
3.58

6.35
10.66
15.87
6.85
4.82
1.38

1.14

u.sl

1.14

1.14

1.77

3.53

4.os

0.36

0.56
2.71
5.33

2.28

4.83
2.04

:1-1

2.82

_II+--G

NOTES:
1. CONTROWNG DIMENSION: INCHES, MILUMETERS SHOWN FOR REFERENCE ONLY.

&
&

'8' AND 'C' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.005 IN. PER SIDE.
THE BASIC LEAD SPACING IS 0.100 IN. BETWEEN CENTERUNES.
EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN :Ill.Ol0 IN. OF ITS EXACT TRUE POSITION.

9-34

-0dJ

Package Drawings

5-PIN TO-220 PLASTIC - T PACKAGE SUFFIX
DIMENSIONS

A
B
C
C,
D
Dl
E
F
G
H
H'
I

INCHES
MIN
MAX
.500
.&80
.420
.380
.560
.S60
.230
.270
.,40
.190
.045
.055
.045
.D2O
.,38
.181
.014
.022
.0&7
.077
.2&1
.271
.,15
.OID

MILUMETERS
MIN
MAX
,2.70
14.73
9.6&

14.22

'0.67
18.&1

&.64

6.lII

3.58

4.63
1.40

'.'4
0.5'
3.53
0.36
1.46
6.5&
2.03

1.'4
4.08
0.56
1.1111
7.06
2.92

......i ...- - G

NOTI!S:
1. CONTROLLING DIMENSION: INCHES. MILUMETERS SHOWN FOR REFERENCE ONLY.

&

£

'B' AND 'C' 00 NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.
THE BASIC LEAD SPACING IS 0.067 IN. BETWEEN CENTERLlNE8.
EACH LEAD CENTERUNE SHALL BE LOCATED WITHIN ±O.D10 IN. OF ITS EXACT TRUE POSITION.

20-PIN CERAMIC LEAD LESS SURFACE MOUNT - L PACKAGE SUFFIX
DIMENSIONS
INCHES

....
....
MIN

A
A'
B'

B2
B3

DIE
D1/El
D2IE2
D3/E3

L
Ll
L2
La
N
NDINE

•

MAX

.•,GO

.oas

.D22
.D72REF.
.006
.D22
.342
.368
.200 BBC

.IGOBSC
.368
.045
JIll!

-

.0411

.055

.075
.OD3

.015

20
5

.000BSC

ND .... 8NC!DAT[!]
IIQUAL TO @!]

IIILLIMETERS

....

IIIN
1.&2
1.27
0.68

MAX

NOTES

2.24
0.71

1,3

•

I-- _ .... 8PACl!DAT[!]

i .......... I!ll
!

1.83 REF •
0.15

0.68
9JI8
&.08BBC
UoIBSC
8.00

8

8.88

-

lAO
lAO
2.41
0.31

1.14
1.14
1.90
0.0&

4

5

20
5

2
2

1.27BBC

'0

NOTES:
1. A MI_UM CLEARANCE OF 0.D15 INCH (0.38 mm) SHALL BE MAINTAINED BETWEEN ADJACENT TERMINALs.
2. 'N' IS THE MAXIMUM QUANTITY OF TERMINAL posmONS. 'ND' AND 'NE' ARE THE NUMBERS OF TERMINALS ALONG THE SIDES OF LENGTH '0' AND 'E' RESPECTIYELY.
3. ELECTRICAL CONNECTION TERMINALS ARE REQUIRED ON PLANE 1 AND OPTIONAL ON PLANE 2. HOWEVER, IF PLANE 2 HAS SUCH TERMINALS THEY
SHALL BE ELECTRICALLY CONNECTED TO OPPOSING TERMINALS ON PLANE 1.
4. A MINIMUM CLEARANCE OR 0.015 INCH (0.38 mm) SHALL BE MAINTAINED BETWEEN A METAL UD AND OTHER METAL FEATURES (E.G., PLANE 2 TER~,
METAWZED CASTELLATIONS, ETC.) THE UD SHALL NOT EXTEND BEYOND THE EDGES OF THE BODY.
S. THE INDEX FEATURE FOR NUMBER 1 TERMINAL IDENTIFICATION, OPTIONAL ORIENTATION OR HANDUNG PURPOSES SHALL BE WITHIN THE AREA DEFINED BY
DIMENSIONS 'B2' AND 'U' ON PLANE ,.
8. DIMENSION 'A' CONTROLS THE OVERALL PACKAGE THICKNESS.
7. CONTROWNG DIMENSION: INCHE&. MlWMETERS SHOWN FOR REFERENCE ONLY.
8. CASTELLATIONS ARE REQUIRED ON BOTTOM TWO LAYERS. CASTELLATIONS IN THE TOP LAYER ARE OPTIONAL
9. WHEN SOLDER DIP LEAD FINISH APPUES, BOLDER BUMP HEIGHT SHALL NOT EXCEED II.OO7INCH!S AND SOLDER BUMP
COPLANARITY SHALL NOT EXCEED 0.006 INCHES.
10. THE BASIC TERMINAL SPACING IS 0.050 INCHES BETWEEN CENTERUNE&. EACH TERMINAL CENTERUNE SHALL BE
LOCATED WITHIN ±O.OO4INCHES OF ITS EXACT TRUE POSmON.

9-35

Package Drawings

-

O=:!J

28-PIN CERAMIC lEADlESS SURFACE MOUNT - L PACKAGE SUFFIX
DIMENSIONS

A
A1
B1
B2
B3

DIE
D11E1
D21E2
D3/E3

L
L1
L2
L3

N
NDINE

•

INCHES
MIN
MAX
.100
•060
.060
.D88
.028
.022
•072 REF.
.008
.022
.442
.480
.300BSC
.150BSC
.480
.065
.055
.075
.095
.015
.003
28
7
.060BSC

.046
.046

.

MILUMETERS
MIN
MAX
1.52
2.54
2.24
1.27
0.56
0.71
1.83 REF•
0.15
0.56
11.68
11.23

NOTES
8

"

1,3

ND fl." 8PACED AT [!]

......... Iii!
INDEX CORNER-

V

8

7.62BSC

3.81 BSC
11.88
1.14
1.40
1.14
1.40
2A1
1.90
0.08
0.38
28
7
1.27BSC

-

UD

D

4

U

5
2
2
10

NOTES:
1. A MINIMUM CLEARANCE OF 0.015 INCH (0.38 mm) SHALL BE MAINTAINED BETWEEN ADJACENT TERMINALS.
2. 'N' IS lHE MAXIMUM QUANTITY OF TERMINAL POSITIONS. 'ND' AND 'NE' ARE THE NUMBERS OF TERMINALS ALONG THE SIDES OF LENGTH 'D' AND 'E' RESPEClWELY.
3. ELECTRICAL CONNECTION TERMINALS ARE REQUIRED ON PLANE 1 AND OPTIONAL ON PLANE 2. HOWEVER, IF PLANE 2 HAS SUCH TERMINALS lHEY SHALL
BE ELECTRICALLY CONNECTED TO OPPOSING TERMINALS ON PLANE 1.
4. A MINIMUM CLEARANCE OR 0.015 INCH (0.38 mm) SHALL BE MAINTAINED BETWEEN A METAL LID AND OTHER METAL FEATURES (E.G., PLANe 2 TERMINALS,
METAWZED CASTELLATIONS, ETC.) lHE UD SHALL NOT EXTEND BEYOND THE EDGES OF lHE BODY.
5. THE INDEX FEATURE FOR NUMBER 1 TERMINAL IDENTIFICATION, OPTIONAL ORIENTATION OR HANDUNG PURPOSES SHALL BE WITHIN lHE AREA DEFINED
BY DIMENSIONS 'B2' AND 'U' ON PLANE 1.
6. DIMENSION 'A' CONTRDLS lHE OVERALL PACKAGE lHICKNESS.
7. CONTROLLING DIMENSION: INCHES. MILUMETERS SHOWN FOR REFERENCE ONLY.
8. CASTELLATIONS ARE REQUIRED ON BOTTOM TWO LAYERS. CASTELLATIONS IN lHE TOP LAYER ARE OPTIONAL.
9. WHEN SOLDER DIP LEAD FINISH APPUES, SOLDER BUMP HEIGHT SHALL NOT EXCEED O.G07INCHES AND SOLDER BUMP COPLANARITY SHALL NOT EXCEED G.OO8INCHES.
10. THE BASIC TERMINAL SPACING IS 0.050 INCHES BETWEEN CENTERUNES. EACH TERMINAL CENTERLINE SHALL BELOCATED WITHIN ±G.OO4INCHES OF
ITS EXACT TRUE POsmON.

28-PIN CERAMIC LEADLESS SURFACE MOUNT - LP PACKAGE SUFFIX
DIMENSIONS

A
A1
B1
B3

DIE
D11E1
D2IE2
D31E3
L
L1
L3

N
NDINE
0
P
Q

•

INCHES
MIN
MAX
.100
.060
.050
.088
.028
.022
.006
.022
.442
AS8
.300BSC
.150BSC
ABO
.075 REF

.0461
.003

.055
.013

28
7
.006 REF
.040 REF
.020 REF
.000BSC

.. ,.......... -4

MILLIMETERS
MAX
MIN
1.52
2.54
2.24
1.27
0.71
0.56
0.58
0.15
11.83
11.23
7.B2BSC
3.81 BSC

&,

t7
,..,o

-

11.88
1.905 REF
1.14
0.08

1

1.40
0.33

28
7
G.152REF
1.018 REF
0.508 REF
1.27BSC

D

UD

U

NOTES:
1. A MINIMUM CLEARANCE OF 0.015 INCH (0.38 mm) SHALL BE MAINTAINED BETWEEN ADJACENT TERMINALS.
2. 'N' IS THE MAXIMUM QUANTITY OF TERMINAL POSmONS. 'ND' AND 'NE' ARE THE NUMBERS OF TERMINALS ALONG THE SIDES OF LENGTH 'D' AND 'E' RESPEClWELY.
3. ELECTRICAL CONNECTION TERMINALS ARE REQUIRED ON PLANE 1 AND OPTIONAL ON PLANE 2. HOWEVER, IF PLANE 2 HAS SUCH TERMINALS lHEV SHALL BE
ELECTRICALLY CONNECTED TO OPPOSING TERMINALS ON PLANE 1.
4. A MINIMUM CLEARANCE OR 0.015 INCH (0.38 mm) SHALL BE MAINTAINED BETWEEN A METAL LID AND OlHER METAL FEATURES (E.G., PLANE 2 TERMINALS.
METALLIZED CASTELLATIONS, ETC.) lHE UD SHALL NOT EXTEND BEYOND THE EDGES OF lHE BODY.
5. THE INDEX FEATURE FOR NUMBER 1 TERMINAL IDENTIFICATION, OPTIONAL ORIENTATION OR HANDUNG PURPOSES
SHALL BE WllHlN THE AREA DEFINED BY DIMENSIONS 'B2' AND 'U' ON PLANE 1.
6. DIMENSION 'A' CONTROLS THE OVERALL PACKAGE lHICKNESS.
7. CONTROLLING DIMENSION: INCHES. MIWMETERS SHOWN FOR REFERENCE ONLY.
8. CASTELLATIONS ARE REQUIRED ON BOTTOM TWO LAYERS. CASTELLATIONS IN THE TOP LAYER ARE OPTIONAL.
9. WHEN SOLDER DIP LEAD FINISH APPLIES, SOLDER BUMP HEIGHT SHALL NOT EXCEED G.007INCHES AND SOLDER BUMP COPLANARITY SHALL NOT EXCEED G.006INCHES.
10. THE BASIC TERMINAL SPACING IS 0.050 INCHES BETWEEN CENTERUNES. EACH TERMINAL CENTERUNE SHALL BE
LOCATED WITHIN ±G.004INCHES OF ITS EXACT TRUE POSITION.

9-36

-

QdJ

Package Drawings

48-PIN LOFP - FO PACKAGE SUFFIX
DIMENSIONS

A
Al
AI

b
bl
C
C1

D
Dl
E
El

•

L
Rl
RZ
S

MIWMETERS
MIN MAX
1.60
0.05
0.15
1.35 1.46
0.17
D.27
0.17
0.23
0.09
0.20
0.09
0.18
9.00SSC
7.00SSC
B.OOBSC
7.ooBSC
o.50BSC
0.45
0.7&
0.08
0.08
0.20
0.20

9

-

-

-

0"

7"

INCHES
MIN MAX

-

.CI63

.002 .006
.053 .057
.007 .011
.007 .008
.003 .008
.003 .006
.3&4 BSC
.278 BBC
.3&4BBC
.278 BSC
.D2O BSC
.000
.018
.003
.003 .008
.008
7'
0'

E

c-JL

-

.&.

t t

A

R1

A2

i !

J

~
__====!==,5jI~~=+,t:j.-t::I-t:I-_d...._ _

BASE PLANE
SEATING
PLANE

~:

1. CONTROLUNG DIMENSION: MILLIMETERS. INCHES SHOWN FOR REFERENCE ONLY.
'Dl'AND 'El' 00 NOT INCLUOE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED O.25mm PER SIDE.
'Dl'AND 'El'lNCWDE MOLD MISMATCH.
~ THE BASIC LEAD SPACING IS O.5Omm BETWEEN CENTERLiNES. EACH LEAD CENTERUNE SHALL BE LOCATED WITHIN ±o'lDmm
OF ITS EXACT TRUE POSITION.
4. LEADS SHALL BE COPLANAR WITHIN O.08mm AT THE SEATING PLANE.
DIMENSION 'b' ooES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAA PROTRUSlON(S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
'b' MAXIMUM BY MORE THAN o.08mm.
DAMBAR CAN NOT BE LOCATED ON THI! LOWER RADIUS OR THE LEAD FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN
ADJACENT LEAD IS O.D7mm.
&. DETAILS OF PINllDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WrrHIN THE ZONE INDICATED.
,&, EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.
&. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN O.lDmm AND O.25mm FROM THE LEAD TIP.
&. 'Al'lS OEFiNEO AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY (BASE PLANE).
THE TOP PACKAGE BODY MAY BE SMALLER THAN THE BOTTOM PACKAGE BODY SIZE BY AS MUCH AS O.l5mm.

£

£

&

9-37

-

[1[J

Package Drawings

64-PIN LQFP - FQ PACKAGE SUFFIX
D
DIMENSIONS

A
Al
A2

b
bl
C
Cl
D
D1
E
El

e
L

Rl
R2
S
8

MIWMETERS
MIN Io!AX
1.40
1.60
0.05
0.16
1.35
1.45
0.17
0.27
0.17
0.23
0.20
0.1J9
0.09
0.16
12.00BSC
10.00BSC
12.00BSC
10.00BSC
O.50BSC
0.45
0.75
0.08
0.08
0.20
0.20
0°

-.,.

INCHES
MAX
MIN
0.055 0.083
0.002 0.006
0.57
0.53
0.1107 0.011
0.007 O.oou
0.004 0.008
0.004 O.lJ06
OAnBSC
O.31l3BSC
OAnBSC
O.31l3BSC
O.02OBSC
0.03
0.18
0.003
0.006
O.ooa
0.006
0°

L--,........-.-=

r

11-13°

E

-.,.

~

c-JL

TYP(4X)

NOTES:
1. CONTROLUNG DIMENSION: MIWMETERS.INCHES SHOWN FOR REFERENCE ONLY.
'Dl'AND 'El' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED O.25mm PER SIDE.
'Dl'AND 'El'lNCLUDE MOLD MISMATCH.
THE BASIC LEAD SPACING IS O.50mm BETWEEN CENTERLINES. EACH LEAD CENTERUNE SHALL BE LOCATED WITHIN ±G.1Omm
OF ITS EXACT TRUE POSmON.
4. LEADS SHALL BE COPLANAR WITHIN O.09mm AT THE SEAliNG PLANE.
DIMENSION 'b' DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
'b' MAXIMUM BY MORE THAN O.08mm.
DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN
ADJACENT LEAD IS O.D7mm.
DETAILS OF PlNl IDENTIFIER ARE OPllONAL BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
&,. EXACT SHAPE AND SIZE OF THIS FEATURE IS OPnoNAL.
~ THESE DIMENSIONS APPLY TO THE FLAT SECllON OF THE LEAD IIETWEEN 0.1Omm AND 0.25mm FROM THE LEAD liP.
&. 'Al'lS DEFINED AS THE DISTANCE FROM THE SEAliNG PLANE TO THE LOWEST POINT OF THE PACKAGE IIOpY (BASE PLANE).
THE TOP PACKAGE IIODY MAY liE SMALLER THAN THE BOTTOM PACKAGE IIODY SIZE IIY AS MUCH AS 0. 1&mm.

£

A:.
£

&.

&

9-38

-

[1[J

Package Drawings

1DO-PIN LQFP - FQ PACKAGE SUFFIX
D

DIMENSIONS
MILl.IMETERS
MIN MAX

INCHES
MAX
MIN
0.1183

A

1.40

1.60

0.056

A1

0.115

0.15

A2

1AS

b

1.35
0.17

0.002 O.lJ06
0.57
0.53
0.007 0.011

b1

0.17

Cl.23

C

0.D9

0.20

C1
D

0.09

0.18

18.00BSC

O.830BSC

D1

14.00BSC

0.551 BSC

0.27

0.007 0.008
0.004 o.ooa
0.004 0.008

E

18.00BSC

E1

14.ooBSC

0.551 BSC

•L

O.50BSC
OAS
0.75

O.D20BSC
0.03
0.18

R1

R2
S

e

0.08
0.08
0.20

O'

&

o.830BSC

-

0.003

0.20

0.003

-.,.

E

O.ooa
0'

-.,.

O.ooa

t A2t

A

JBASEPLANE

:-E~+==l~"*'t::l-.t::j..~...!.-- SEATING
PLANE

NOTES:
1. CDNTROWNG DIMENSION: MILUMETER8.INCHES SHOWN FOR REFERENCE ONLY.
'D1 'AND 'E1' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHAll. NOT EXCEED O.25mm PER SIDE.
'D1'AND 'E1'INCLUDE MOLD MISMATCH.
THE BASIC LEAD SPACING IS O.5Omm BETWEEN CENTERLlNE8. EACH LEAD CENTERUNE SHAll. BE LOCATED WITHIN ~.1Omm
OF ITS EXACT TRUE POSITION.
4. LEADS SHAll. BE COPLANAR WITHIN o.08mm AT THE SEATING PLANE.
DIMENSION 'b' DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE LEAD WIOTH TO EXCEED
'b' MAXIMUM BY MORE THAN O.08mm.
DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN
ADJACENT LEAD IS O.o7mm.
DETAILS OF PIN11DENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.
THESE DIMENSIONS APPLY TO THE FLAT SEcnON OF THE LEAD BETWEEN 0.10mm AND O.25mm FROM THE LEAD TIP.
'A1'IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY (BASE PLANE).
THE TOP PACKAGE BODY MAY BE SMALLER THAN THE BOTTOM PACKAGE BODY SIZE BY AS MUCH AS 0.15mm.

h.

;t

£

&.
,t
&.

L£

11

9-39

-

OJJ-

Package Dra WI n g s

16-PIN SIDEBRAZE DIP - SP PACKAGE SUFFIX
DIMENSIONS

A
B
B,
C
D
E
El
F
L
Ll
Q

SI

82

INCHES
MIN
MAX

MILLIMETERS
MAX
MIN

.200
.023
.085
.015

5.08
0.58
0.36
1.14
1.65
0.38
0.20
21.34
7.78
5.59
8.13
7.37
2.54 BBC
5.08
3.18
3.81
0.38
1.52
0.13
0.13

-

.014

.045
.008

-

.840

.220
.310
.290
.320
.100BSC
.125
.200
.150
.015
.060
.005
.005

-

-

-

NOTES
8
2,8
8
4
4
7
5,9

3

BASE PLANE

6

SEATING PLANE

' - HEATSINK
NOTES:
1. INDEX AREA; A NOTCH OR A PIN ONE IDENTIFICATION MARK SHALL BE
LOCATED ADJACENT TO ONE AND SHALL BE LOCATED WITHIN THE SHADED
AREA SHOWN.THE MANUFACTURER'S IDENTIFICATION SHALL NOT BE USED AS
A PIN ONE IDENTIFICATION MARK.

2.

THE MINIMUM LIMIT FOR DIMENSION ·Bl' MAY BE 0.023 IN. (O.58mm) FOR CORNER
LEADS.

3.

DIMENSION 'Q' SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE
PLANE.

4.

THIS DIMENSION ALLOWS FOR OFF-CENTER LID, MENISCUS, AND GLASS
OVERRUN.

5.

THE BASIC LEAD SPACING IS 0.100 IN. (2.54mm) BETWEEN CENTERLINES. EACH
LEAD CENTERLINE SHALL BE LOCATED WITHIN ±G.Ol0 IN. (O.25mm) OF ITS
EXACT TRUE POSmON.

6.

MEASURE ALL FOUR CORNERS.

7.

El SHALL BE MEASURED AT THE CENTERLINE OF THE LEADS.

8.

ALL LEADS - INCREASE MAXIMUM LIMIT BY 0.003 IN~o.oamm) MEASURED AT THE
CENTER OF THE FLAT, WHEN SOLDER DIP IS APPLIED.

9.

14SPACES

10.

BRA2E FILLET SHALL BE CONCAVE.

11.

CONTROLLING DIMENSIONS: INCHES. MILLIMETERS SHOWN FOR REFERENCE
ONLY.

9·40

-

[1[J

Package Drawings

24-PIN SIDEBRAZE DIP - SP PACKAGE SUFFIX
DIMENSlDNS
INCHES
MIN
MAX

MILLIMETERS
MAX
MIN

A

-

.225

-

5.72

B

.014

.D23

0.36

0.58

B1
C

.045

.065

1.14

1.85

.008

-

.015

0.20

0.38

D

1.220

-

30.99

E

.580

.610

E1
F

.615
.585
.1OOBSC

L

.125

L1

.150

0

.015

S1
S2

.ODS
.ODS

14.73

15.49

14.36
15.62
2.54BSC

.200

3.18
3.61

&.08

.080

0.38

1.52

-

0.13
0.13

-

NOTES
8
2,8
8
4
4
7
&,9

NDTE1

1"1-------

D

------+1
BASE PLANE

3

SEA1INQ PLANE

6
I

I

-IF!-

HEAT SINK
NOTES:
1. INDEX AREA; A NOTCH OR A PIN ONE IDENTIFICATION MARK SHALL BE LOCATED ADJACENT TO PIN ONE AND SHAll BE LOCATED WITHIN THE
SHADED AREA SHOWN. THE MANUFACTURER'S IDENTIFICATION SHALL NOT BE USED AS A PIN ONE IDENTIFICATION MARK.
2. THE MINIMUM LIMIT FOR DIMENSION 'B1' MAY BE O.023IN.(O.58mm) FOR CORNER LEADS.
3. DIMENSION "0" SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.
4. THIS DIMENSION ALLOWS FOR OFF.cENTER LID, MENISCUS, AND GLASS OVERRUN.
5. THE BASIC LEAD SPACING IS 0.100 IN.(2.&4mm) BETWEEN CENTERLINES. EACH LEAD CENTERLINE SHAll BE LOCATED WITHIN ±O.010 IN. (0.25mm)
OF ITS EXACT TRUE POSITION.
6. MEASURE ALL FOUR CORNERS.
7. E1 SHAll BE MEASURED AT THE CENTERLINE OF THE LEAOS.
8. ALL LEADS • INCREASE MAXIMUM LIMIT BY 0.003 IN. (O.08mm) MEASURED AT THE CENTER OF THE FLAT, WHEN SOLDER DIP IS APPLIED.
9. 22SPACES
10. BRA2E FILLET SHALL BE CONCAVE.
11. CONTROLLING DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.

16-PIN ZIG-ZAG INLINE - Z PACKAGE SUFFIX
DIMENSIONS

A

MILLIMETERS
INCHES
MIN MAX MIN
MAX
19.40 19.60
.764
.772

-

A1
B

5.70

B1

9.40
6.50

B2

2.70

-

5.90
10.40

.224

.079
.232

.370

.409

7.50

.256

.295

2.90
19.35

.105

.114

1.47

.738
.042

2.00

C
D
E

18.75
1.07

F

0.45

0.65

.018

.782
.OS8
.026

G
H

2.50

3.00

0.23

0.35

.098
.009

.014

NOTES

.118

J

1.ooBSC

.039BSC

RAD.

K

1.00BSC

.039BSC

CHAM.

---<~--F

r-----

.,!

D - - -.........

NOTES:

A

DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15mm (0.005 IN.) PER SIDE.

9-41

-

[1[]

Package Drawings

36-PIN asop - MWP PACKAGE SUFFIX
....

DIMENSiONS

51

INCHES
MAX
MIN
A .093
.104
AI .004
.012
.092TYP
A2
B .011
.015
C .005
.0125
D .599
.614
E .291
.299
.D31 BSC
H .394
.419
L .016
.050
9
8"
0"

~

•

MILLIMETERS
MIN L MAX
2.35 L 2.85
0.10 L 0.30
2.34TYP
0.39
D.2B
0.32
0.15
15.20 15.50
7.50
7AO

PIN"

IN...

O.60BSC
10.00 110.65
OAO 1 1.27
8"
0"1

DETAIL "A"

A

A2

S~~~ ~ruuuuuuuuuuuuuuuuuul
~

{=Jf
•

AI&.

DETAIL "A"

NOTES:
1. CONTROLLING DIMENSION: INCHES. MILLIMETERS CONTROL LEAD PITCH·ONLY.

~ 'D' AND 'E' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15mm PER SIDE.
~ THE BASIC LEAD SPACING IS O.8Omm BETWEEN CENTERLINES. EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN ±O.10mm OF ITS EXACT TRUE POSInON.
4. LEADS SHALL BE COPLANAR WITHIN 0.10mm AT THE SEAnNG PLANE.

& DIMENSION 'B' DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
'B' MAXIMUM BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT.
& THESE DIMENSIONS APPLY TO THE FLAT SEenON OF THE LEAD BETWEEN 0.10mm AND ~.25mm FROM THE LEAD np.
In. 'Al'lS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY (BASE PLANE).
44-PIN

.
....
0

asop - MWP PACKAGE SUFFIX
DIMENSIONS

INCHES
MAX
MIN
A .093
.104
AI .004
.012
A2
.062TYP
B ••11
.oi5
C .005
.0125
D .687
.712
E .291
.299
.D31 BSC
H .394
.419
L .018
.050
9
8"
0"

~

•

MILLIMETERS
MIN 1 MAX
2.35 1 2.85
0.10 1 0.30
2.34TYP
0.39
0.28
0.32
0.15
1&.10
17.70
7.80
7.40

PIN'1
INDEX

O.60BSC
10.00 10.65
1.27
0.40
8"
0"

DETAIL "A"
1 2 3

PlANE

~nnnnnnnnnnnnnnnnnnnnnN

NOTES:
1. CONTROWNG DIMENSION: INCHES. MILLIMETERS CONTROL LEAD PITCH ONLY.

~

'D' AND 'E' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED O.I5mm PER SIDE.

DETAIL "A"

& THE BASIC LEAD SPACING IS O.8Omm BETWEEN CENTERLINES. EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN ±O.10mm OF ITS EXACT TRUE POSmON.
4. LEADS SHALL BE COPLANAR WITHIN 0.10mm AT THE SEAnNG PLANE.
& BY
DIMENSION 'B' DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 'B' MAXIMUM
MORE THAN O.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT.

& THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN O.IOmm AND O.25mm FROM THE LEAD np.
ffi 'Al'lS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY (BASE PLANE).

9-42

-

[ldJ

Package Drawings

16-PIN asop - M PACKAGE SUFFIX
DIMENSIONS

A
Al
A2
b

C
D
E
El

•K
L

INCHES
MAX
MIN
.088
.053
.010
.004
.058
.012
.ooa
.010
.007
.197
.188
.244
.228
.157
.150
.025SSC
.OD9 REF
.050
.018

-

..

0"

a

MILLIMETERS
MIN
MAX
1.35
1.75
.10
.25
1.50
.20
.30
.18
.25
5.00
4.80
8.20
5.78
3.81
3.88
.835 BSC
.23 REF
.41
1.27

K

-

0"

INDEX
AREA

i&bJL

..

~ijjj,,4nw

SEATING

~-

PLANE

~

Q

Q

Q

~Al

NOTES:
1.

DETAIL-A

CONTROLLING DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.

&,

~

'D' AND 'E,. DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.
THE BASIC LEAD SPACING IS 0.025 IN. BETWEEN CENTERLINES. EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN ±O.OO4 IN.
OF ITS EXACT TRUE posmON.
.

4.

&
&

fA

LEADS SHALL BE COPLANAR WITHIN 0.004 IN. AT THE SEATING PLANE.
DIMENSION 'b' DOES NOT INCLUDE DAM BAR PROTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE LEAD WIDTH TO
EXCEED 'b' MAXIMUM BY MORE THAN 0.003 IN. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.004 IN. AND 0.010 IN. FROM THE LEAD np.
'Al' IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY (BASE PLANE).

20-PIN asop - M PACKAGE SUFFIX
DIMENSIONS

A
Al
A2
b

C
D
E
El

•
K
L

a

INCHES
MIN
MAX
.088
.0&3
.004
.010
.059
.008
.012
.007
.010
.337
.344
.244
.228
.150
.157
.025SSC
.058 REF
.016
.D5O
8'

-

I
0" I

MILLIMETERS
MIN
MAX
1.35
1.75
.10
.25
1.&0
.20
.30
.18
.25
8.58
8.74
5.78
8.20
3.81
3.88
.1135 BSC
1A7REF
.41
1.27
8'

-

INDEX
AREA

DETAIL-A

1 2 3

I
0"1

I

I

!

+

I

NOTES:
1. CONTROLLING DIMENSION: INCHES. MILLIMETERS SHOWN FOR REFERENCE ONLY.

&

~
4.

&
&
~

~SEEDET~L-A

I

,,--,<,c&
~
I\.

9

I

l-L,~

'D' AND 'El' DO NOT INCLUDE MOLO FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.
THE BASIC LEAD SPACING IS 0.025 IN. BETWEEN CENTERLINES. EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN ±O.OO4 IN. OF ITS EXACT TRUE PosmON.
LEADS SHALL BE COPLANAR WITHIN O.D04IN. AT THE SEAnNG PLANE.
DIMENSION 'b' DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSlON(S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
"b" MAXIMUM BY MORE THAN 0.003 IN. DAMBAII CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FDOT.
THESE DIMENSIONS APPLY TO THE FLAT SEcnON OF THE LEAD BETWEEN D.OO4IN. AND 0.D10 IN. FROM THE LEAD TIP,
'Al'lS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY (BASE PLANE).

9·43

-

[1d]

Package Drawings

a-PIN TSSOP - PW PACKAGE SUFFIX
DIMENSIONS

A
B
C
C1

C2
D
E
F
Fl
L
9

MILLIMETERS
MIN
MAX
4.3
4.5
2.9
3.1
1.10
0.90 REF.
0.05
0.15
6.4BSC
O.65BSC
0.18
0.30
0.09
0.18
0.50
0.70
00
70

-

INCHES
MIN
MAX
0.170
O.ln
0.114
0.122
0.G43
O.03SREF.
0.006
0.002
O.252BSC
0.0256BSC
0.012
0.007
0.007
0.004
0.028
0.020
70
II"

,h

-

SEATING
PLANE

NOTES:
1. CONTROLLING DIMENSION: MILLIMETER8.INCHES,SHOWN FOR REFERENCE ONLY.

, '

.& 'A' AND 'B' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15mm PER SIDE.
'
Lt THE BASIC LEAD SPACING IS 0.65mm BE~EEN CENTERLINES. EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN +O.ll1mm OF ITS EXACT TRUE POsmON.
4. LEADS SHALL BE COPLANAR WITHIN O.08mm AT THE SEATING PLANE.
,
,
£ DIMENSION
'F' DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE LEAD WIDTH 'TO EXCEED 'F' MAXIMUM
BY MORE THAN O.08mm. DAMBAR CAN,NOT BE LDCATED ON THE LOWER RADIUS OR THE LEAD FOOT.
~ THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10mm AND 0.25mm FROM THE LEAD TIP.

& 'C2'IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LDWEST POINT OF THE PACKAGE BODY (BASE PLANE).
14-PIN TSSOP - PW PACKAGE SUFFIX
DIMENSIONS

A
B
C
Cl
C2
D
E
F
F1
L
9

MILLIMETERS
MIN
MAX
4.5
4.3
5.1
4.9
1.10
0.90 REF.
0.05 I 0.15
6.4BSC
O.65BSC
0.18
0.30
0.09
0.18
0.50
0.70
70
II"

-

INCHES
MIN

MAX

0.170
0.193

'O.ln

0.200
0.043
0.035 REF.
0.002 I 0.008
O.252BSC
0,0256 BSC
0.007
0.012
0.004
0.D07
0.020
0.028
70
II"

-

INDEX

AREA

NOTES:
1. CONTROLLING DIMENSION: MILLIMETERS; INCHES SHOWN FOR REFERENCE ONLY•

.& 'A' AND 'B' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED O.15mm PER SIDE.
~ THE BASIC LEAD SPACING IS O.65mm BETWEEN CENTERLINES;

EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN ±O.ll1mm OF ITS EXACT TRUE POSITION.

4. LEADS SHALL BE COPLANAR WITHIN O;08nUn AT THE SEATING PLANE.

'

'

&DlMENSlON 'P DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSlON(S) SHALl. NOT CAUSE Tit'E LEAD WIDTH TO EXCEED
'F' MAXIMUM BY'MORE TI1AN O.08mm.
'
,
,
DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT,',

~ THESE DIMENSIONS APPLY TO THE FLAT SEcnON OF THE LEAD BETWEEN O:I'Omm AND

o.25mm FROM THE LEAD TIP.

& 'C2'IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THEI..OWEST POINT OF THE PACKAGE BODY (BASE PLANE).
9-44

-0dJ

Package Drawings

16-PIN TSSOP - PW PACKAGE SUFFIX
DIMENSIONS

A
B
C
Cl
C2

MWMETERS
MIN
MAX
4.3
4.5
5.1
4.9
1.10
0.90 REF.
0.05
0.15

-

0

II.4BSC

E
F
Fl
L
9

O.66BSC
0.30
0.18
0.18
0.09
0.50
0.70
7·
D·

INCHES
MAX
MIN
0.177
0.170
0.200
0.193
0.043
0.1135 REF.
0.006
0.002
O.252BSC
O.0258BSC
0.012
0.007
0.004
0.007
0.028
0.D2D
7·
II"

-

INDEX
AREA

SEATING
PLANE

NOTES:
1. CONTROLUNG DIMENSION: MILLIMETERS. INCHES SHOWN FOR REFERENCE ONLY.

& 'A' AND 'B' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15mm PER SIDE.
~ THE BASIC LEAD SPACING IS O.65mm BEfY!EEN CENTERLINES.

EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN +O.10mm OF ITS EXACT TRUE POSITION.

4. LEADS SHALL BE COPLANAR WITHIN O.D8mm AT THE SEATING PLANE.

& DIMENSION 'F' DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 'F' MAXIMUM
BY MORE THAN O.OBmm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT.

&THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN O.lDmm AND 0.25mm FROM THE LEAD TIP.

In. 'C2' IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY (BASE PLANE).
20-PIN TSSOP - PW PACKAGE SUFFIX
20

DIMENSIONS

A
B
C
Cl
C2
0
E
F
Fl
L
9

MILLIMETERS
MIN
MAX
4.30
4.48
6.40
6.60
1.10
•90 REF.
.051 .15

-

8.2518.50
.85BSC
.18
.30
.09
.18
.70
.so
II"
8"

INCHES
MAX
MIN
.189
.176
.280
.252
.043
.11354 REF•
.006
.002
.258
.241

-

INDEX
AREA

.0258BSC

.007
.003
.020
II"

.012
.007
.D28
6·

SEATING
PLANE

NOTES:

1. CONTROWNG DIMENSION: MILLIMETERS. INCHES SHOWN FOR REFERENCE ONLY.

& 'A' AND 'B' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED O.lSmm PER SIDE.
~ THE BASIC LEAO SPACING IS O.85mm BETWEEN CENTERLlNE8.

EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN ±D.l0mm OF ITS EXACT TRUE POSITION.

4. LEADS SHALL BE COPLANAR WITHIN O.08mm AT THE SEATING PLANE.

&, DIMENSION 'F' DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
'F' MAXIMUM BY MORE THAN O.08mm.
DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT.

& THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN O.lDmm AND O.25mm FROM THE LEAD TIP.
In. 'C2'IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY (BASE PLANE).
9-45

QdJ

Package Drawings

24-PIN TSSOP - PW, PWP PACKAGE SUFFIX
24

DIMENSIONS

A
B
C
Cl
C2

D
E
F
F1

L

e

MlWIIETERS
MIN
MAX
4.30
4.48
7.70
7.80
1.10
.90 REF.
.15
.os
8.25
8.50
.II6BSC
.30
.18
.18
.09
.50
.70
8·
0"

-

INCHES
MIN
MAX
.169
.176
.311
.303
.043
.D354 REF.
.002 I .006
.248 I .256
.0256BSC
.012
.tJ07
.003
.11117
.028
.020
8·
0"

-

SEATING
PLANE

NOTES:
1. CONTROWNG DIMENSION: MIWMEYERS.INCHES SHOWN FOR REFERENCE ONLY.

&

'A' AND'S' 00 NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED O.l5mm PER SIDE.

~ THE BASIC LEAD SPACING IS 0.65 MM BETWEEN CENTERUNES.

EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN ±O.1Dmm OF
ITS EXACT TRUE POSI11ON.

4. LEADS SHALL BE COPLANAR WITHIN O.08mm AT THE SEATING PLANE

.£ DIMENSION 'F' DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSlON(S)
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 'P MAXIMUM BY IIORE THAN O.08mm
DAMBAR CANNOT BE LOCAYED ON THE LOWER RADIUS OR THE LEAD FOOT.

& THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN O.lOmm AND
O.25mm FROM THE LEAD TIP.
IA 'C2'IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT
OF THE PACKAGE BODY (BASE PLANE).

9-46

-

[!dJ

Package Drawings

28-PIN TSSOP - PWP PACKAGE SUFFIX
28

DIMENSIONS

A
B
C
Cl
C2
D
E
F
F1
L
6

MWMETERS
MIN
MAX
4.30
4A8
9.10
9.80
1.10
.90 REF.
.15
6.25 I 6.50
.88BSC
.18
.30
.18
.09

-

.0&1

.50

.70

0'

8'

INCHES
MIN
MAX
.189
.178
.378
.388
.043
.0364 REF.
.006
.002

-

.246

.-

.0258BSC
.012
.007
.003
.007
.020
.028
8'
0'

SEATING
PLANE

NOTES:
1. CONTROLLING DIMENSION: MILLIMETERS. INCHES SHOWN FOR REFERENCE ONLY.

&::. 'A' AND 'B' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED o.15mm PER SIDE.

£ THE
BASIC LEAD SPACING IS 0.65
BETWEEN CENTERLINES.
EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN ±O.10mm OF
MM

ITS EXACT TRUE POSITION.
4. LEADS SHALL BE COPLANAR WITHIN O.OBmm AT THE SEATING PLANE.

& DIMENSION 'P DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSlON(S)
£

SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 'P MAXIMUM BY MORE THAN O.oamm
DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT.

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN O.IOmm AND
o.25mm FROM THE LEAD TIP.

Ii::, 'C2' IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT
OF THE PACKAGE BODY (BASE PLANE).

9-47

Package Drawings

3-PIN PLASTIC TO-263 POWER SURFACE MOUNT - TO PACKAGE SUFFIX
DIMENSIONS
INCHES

MILLIMETERS

MIN

NOM

MAX

MIN

NOM

MAX

A

.170

.175

.180

4.31

4.44

AI
B

.000

.010

0.00

-

4.57
Q.25

.039

0.51

0.81

0.99

B2

.045

.020

.032
.050

.055

1.14

1.27

1.40

C

.018

.029

0.48

C2
D

.045

.050

.055

1.14

1.27

1.40

.326

.331

.336

8.28

8Al

8.53

Dl
E

.305 REF.
.396

•401

0.74

7.75 REF•

J

.405

10.05

10.18 10.31

El

.258 REF.

8.50 REF.

e

.100 asc

2.54BSC

L

.580

.600 1 .620

14.73

Ll

.090

.100 1 .110

L2

.055

.061 1 .068

2.29 1 2.54 1 2.711
1.40
1.54 1.68

SEE DETAIL HAil

15.24 115.75

NOTES:
1.

ffi
ffi
3.

CONTROLLING DIMENSION: INCHES. MILUMETERS SHOWN FOR REFERENCE ONLY.

DETAIL -A" ROTATED 90"

Dl AND El ESTABLISH A MINIMUM MOUNTING SURFACE FOR TERMINAL 4.
TAB CONTOUR OPTIONAL WITHIN DIMENSION E AND ZONE L2.
THE BASIC LEAD SPACING IS 0.100 INCHES BETWEEN CENTERUNES. EACH LEAD CENTERLINE SHALL BE LOCATED WlTHIN.fll.010 INCHES
OF ITS EXACT TRUE POSITION.

~
~

AI IS MEASURED FROM THE LEAD TIP TO THE BASE PLANE.
D AND E DO NOT INCLUDE MOLD FLASH ON PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.

?J;, LEAD TIPS SHALL BE COPLANAR WITHIN 0.004 INCHES.

5-PIN PLASTIC TO-263 POWER SURFACE MOUNT - TO PACKAGE SUFFIX
DIMENSIONS
INCHES

MILLIMETERS

MIN

NOM

MAX

MIN

NOM

A

.170

.175

.180

4.31

4A4

AI
a

.000

.010

0.00

.039

0.51

C

.018

.029

0.48

C2
D

.045

.050

.055

1.14

1.27

1.40

.328

.331

.336

8.28

8.41

8.53

.020

-

.032

•305 REF•

0.81

4.57
0.25
0.99
0.74

7.75 REF•

Dl
E

.398 1 .401 1 .405

El

•256 REF•

10.05

10.18 10.31
6.60 REF•

•067BSC

8

-

MAX

1.70aSC

L

.580

.600

.620

14.73

15.24 15.75

Ll

.090

.100

.110

2.29

2.54

2.711

l2

.055

.061

.066

1.40

1.54

1.68

NOTES:
1.

CONTROLLING DIMENSION: INCHES. MILUMETERS SHOWN FOR REFERENCE ONLY.

3.

TAB CONTOUR OPTIONAL WITHIN DIMENSION E AND ZONE L2.

&

ffi
ffi
&
&

Dl AND El ESTABLISH A MINIMUM MOUNTING SURFACE FOR TERMINAL 6.

THE BASIC LEAD SPACING IS 0.067 INCHES BETWEEN CENTERLINES. EACH LEAD CENTERUNE SHALL BE LOCATED WITHIN fll.010 INCHES
OF ITS EXACT TRUE POSITION.
AI IS MEASURED FROM THE LEAD TIP TO THE BASE PLANE.
D AND E DO NOT INCLUDE MOLD FLASH ON PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 IN. PER SIDE.
LEAD TIPS SHALL BE COPLANAR WITHIN 0.004 INCHES.

9-48

-0::1l

-

0dJ

Package Drawings

a-PIN MINI SO - P PACKAGE SUFFIX
DIMENSIONS
M/LUMETERS
MIN
MAX

INCHES
MAX
MIN
.124

A

2.84

a15

.112

B

2.84

3.15

.112

C
Cl
CZ
D

-

0.80 REF.
0.05

4.9 BSC
0.20

F

F1

0.08

L
Ll

0.41
0.71
0.94 REF.

e

0.29

0"'

0.002
0.00&
0.193 BSC
o.02Ii8BSC

0.48

I
I

CJ.043

0.035 REF.

0.15

O.85BSC

E

.124

-

1.10

DETAlL-A

0.018

0.009
0.003

INDEX
AREA

0.1111

0.018
0.028
0.037 REF.

8°

2
_DETAIL-A

*..<,

8°

0°

F1~1,.-----7'(.
-;

f~
\

Ld'
T
.--

\

, __ ,,/I

NOTES:
1. CONTl'lOLLING DIMENSION: MlLUMETERS.INCHES SHOWN FOR REFERENCE ONLY.

it 'A' AND 'B' DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED O.2Omm PER SIDE.
~ 11IE BASIC LEAD SPACING IS o.85mm BETWEEN CENTERUNEs.

EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN +O.lDmm

OF ITS EXACT TRUE POSITION.
4. LEADS SHALL BE COPLANAR WITHIN O.oamm AT 11IE SEATING PLANE.

ffi DIMENSION 'F' DOES NOT INCLUDE DAMBAR PROTRUSION. 11IE DAMBAR PROTRUS/ON(S) SHALL NOT CAUSE 11IE LEAD WIDTH TO
EXCEED 'P MAXIMUM BY MORE THAN o.oamm. DAMBAR CAN NOT BE LOCATED ON 11IE LOWER RADIUS OR 11IE LEAD FOOT.

&, THESE DIMENSIONS APPLY TO 11IE FLAT SECTION OF 11IE LEAD BETWEEN o.lOmm AND O.25mm FROM 11IE LEAD TIP.
?:t; 'CZ'IS DEFINED AS 11IE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF 11IE PACKAGE BODY (BASE PLANE).

10-PIN MINI SO - P PACKAGE SUFFIX
DIMENSIONS

A
B

MILLIMETERS
MIN
MAX

INCHES
MIN
MAX

2.84
2.84

.112

3.15
3.15

C

-

C1

O.BIIREF.

CZ
D

0.05

1.10
0.15

.112

-

0.002
0.008
0.193 BSC

F

F1

o.oa

0.29

o.ooa

L

0.41

0.71

0.016
0._
0.037 REF.

Ll

e

0.94 REF.
0°

6°

~.

0.043
0.035 REF.

4.8BSC
O.50BSC
0.15
0.41

E

DETAlL-A

.124
.124

O.Ol87BSC
0.016

0.00&

0"'

INDEX
AREA

0.011

I

2
BEE DETAIL - A

6

,..<,

,.-----7'(.

eJ
.--

T

NOTES:
1. CONTl'lOWNG DIMENSION: MILLIMETERS. INCHES SHOWN FOR REFERENCE ONLY.

it 'A' AND 'B' DO NOT INCWDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED D.2IImm PER SIDE.
~ 11IE BASIC LEAD SPACING IS 0.50mm BETWEEN CENTERLINES.

EACH LEAD CENTERLINE SHALL BE LOCATED WITHIN +0.1_

OF ITS EXACT TRUE PDSITION.
4. LEADS SHALL BE COPLANAR WITHIN O.08mm AT 11IE SEATING PLANE.

ffi DIMENSION 'P DOES NOT INCLUDE DAMBAR PROTRUSION, 11iE DAMBAR PROTRUSION(S) SHALL NOT CAUSE 11IE LEAD WIDTH TO
EXCEED 'F' MAXIMUM BY MORE THAN O.08mm. DAMBAR CAN NOT BE LOCATED ON 11IE LOWER RADIUS OR THE LEAD FOOT.

& 11IESE DIMENSIONS APPLY TO THE FLAT SECTION OF 11IE LEAD BETWEEN 0.10mm AND O.25mm FROM THE LEAD TIP.
&. 'C2' IS DEFINED AS 11IE DISTANCE FROM 11IE SEATING PLANE TO THE LOWEST POINT OF 11IE PACKAGE BODY (BASE PLANE).
9-49

(~\
\

. . . __ "'1I

NOTES

NOTES

NOTES

NOTES

~TEXAS

INSTRUMENTS
Printed in U.S.A.

11 /99

SLUD002



---

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