2000_TI_Power_Management_Products_Vol_2 2000 TI Power Management Products Vol 2
User Manual: 2000_TI_Power_Management_Products_Vol_2
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~TEXAS
INSTRUMENTS
Power Management
Products
2000
Analog and Mixed Signal
===================
General Information (Vol. 1)
Linear Voltage Regulators
Shunt Regulators
Precision Virtual Grounds
Mechanical Data
General Information (Vol. 2)
Processor PS Controllers
Switching PS and DC/DC Converters
MOSFET Drivers
Supervisors
Mechanical Data
General Information (Vol. 3)
Power Distribution Switches
LED Drivers
Voltage Rail Splitters
Special Functions
Mechanical Data
Power Management Products
Data Book
Volume 2
Literature Number: SLVD004
~TEXAS
INSTRUMENTS
Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify, before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgement, including those pertaining to warranty, patent
infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the
time of sale in accordance with TI's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing
of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY. OR
ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR
PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
AT THE CUSTOMER'S RISK.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
combination, machine, or process in which such semiconductor products or services might be
or are used. TI's publication of information regarding any third party's products or services does
not constitute TI's approval, warranty or endorsement thereof.
Copyright © 1999, Texas Instruments Incorporated
Printed in U.S.A. by
Von Hoffmann Graphics
Owensville, Missouri
INTRODUCTION
The Texas Instruments 1999 Power Management Products Data Book Set showcases Tl's broad
portfolio of analog components for power supply designs. Featured in this set are most of the
components previously found in the 1996 Power Supply Circuits Data Book, the new and exciting power
management products introduced since then, and other components useful for power supply designs.
The set consists of three product area specific volumes:
•
Power Management Products, Volume 1:
-
Linear voltage regulators
-
Shunt regulators
-
Voltage references
Precision virtual grounds
•
Power Management Products, Volume 2:
-
•
Processor power supply controllers (DSP and CPU)
-
Switching power supply controllers and DC/DC charge pump converters
-
MOSFET drivers
-
Supervisory circuits
Power Management Products, Volume 3:
-
Power distribution switches
-
LED drivers
-
Voltage Rail splitters
-
Special Functions
More than a collection of data sheets, this data book set is a tool for locating the best power management
components for a successful deSign effort. It is structured to help you quickly find the devices best suited
to your application. The set contains:
•
An alphanumeric index at the beginning of each book to make finding known part numbers simple.
•
Product selection guides with a condensed view of parametric information organized to help you
choose the devices that most closely fit your needs.
•
Key specifications and features presented for easy comparison.
•
A section on mechanical specifications for all packages used with Texas Instruments power
management devices.
While this data book offers design and specification data only for power management products,
complete technical data for any TI semiconductor product is available from your nearest TI Field Sales
Office, local authorized TI distributor, or from the TI web site at:
http://www.ti.comlsc
We believe you will find the 1999 Power Management Data Book set to be a valuable addition to your
collection of technical literature.
v
vi
General Information (Vol. 1)
Linear Voltage Regulators
III
Shunt Regulators
•
Precision Virtual Grounds
•
Mechanical Data
•
General Information (Vol. 2)
..
Processor PS Controllers
•
Switching PS and DC/DC Converters.
MOSFET Drivers
•
Supervisors
Mechanical Data
General Information (Vol. 3)
Power Distribution Switches
LED Drivers
Voltage Rail Splitters
Special Functions
Mechanical Data
6-1
-.....
:::J
o...
3
a
_.
o
:::J
•
6-2
ALPHANUMERIC INDEX
LM237 ............................. 2-409
LM337 ............................. 2-409
LT1054 ............................ 8-171
SG2524 ............................ 8-97
SG3524 ............................ 8-97
TL317 ............................. 2-415
TL430 ............................... 3-3
TL431 ............................... 3-9
TL431A .............................. 3-9
TL494 .............................. 8-111
TL494A ............................ 8-121
TL499A ............................ 8-129
TL594 ............................. 8-137
TL598 ............................. 8-149
TL1431 ............................. 3-27
TL750L05 .......................... 2-421
TL750L08 .......................... 2-421
TL750L10 .......................... 2-421
TL750L12 .......................... 2-421
TL750M05 ......................... 2-429
TL750M08 ......................... 2-429
TL750M10 ......................... 2-429
TL750M12 ......................... 2-429
TL751 L05 .......................... 2-421
TL751L08 .......................... 2-421
TL751L10 .......................... 2-421
TL751L12 .......................... 2-421
TL751M05 ......................... 2-429
TL751M08 ......................... 2-429
TL751M10 ......................... 2-429
TL751M12 ......................... 2-429
TL78Q-05 .......................... 2-441
TL780-12 .......................... 2-441
TL780-15 .......................... 2-441
TL783 ............................. 2-449
TL2217-285 ....................... 2-533
TL2218-285 ........................ 16-7
TL2218-285Y ....................... 16-7
TL5001 ............................. 8-79
TL5001A ............................ 8-79
TL5001Y ............................ 8-79
TL7700 ........................... 10-101
TL7702A ........................... 10-91
TL77028 .......................... 10-113
TL7705A ........................... 10-91
TL77058 .......................... 10-113
TL7709A ........................... 10-91
TL7712A ........................... 10-91
TL7715A ........................... 10-91
TL7726 ............................. 16-3
TL7757 ........................... 10-123
TL7759 ........................... 10-133
TL7770-5 ......................... 10-139
TL7770-12 ........................ 10-139
TL-SCSI285 ....................... 2-527
TLC5904 ........................... 14-3
TLC7701 .. .. . . .. . .. . . .. .. . . .. .. . ... 10-9
TLC7725 ........................... 10-9
TLC7703 ........................... 10-9
TLC7733 ........................... 10-9
TLC7705 ........................... 10-9
TLE2425 ............................. 4-3
TLE2425Y ........................... 4-3
TLE2426 ............................ 15-3
TLE2426Y .......................... 15-3
TLV431 ............................. 3-45
TLV431A ........................... 3-45
TLV2217-33 ....................... 2-461
TPS1100 ........................... 13-3
TPS1100Y .......................... 13-3
TPS1101 .......................... 13-13
TPS1101Y ......................... 13-13
TPS1120 .......................... 13-23
TPS1120Y ......................... 13-23
TPS2010 .......................... 13-35
TPS2010A ......................... 13-53
TPS2010Y ......................... 13-35
TPS2011 .......... . .. . .. .. . .. . .... 13-35
TPS2011A ......................... 13-53
TPS2012 .......................... 13-35
TPS2012A ......................... 13-53
TPS2013 .......................... 13-35
TPS2013A ......................... 13-53
TPS2014 .......................... 13-73
TPS2015 .......................... 13-73
TPS2020 .......................... 13-93
TPS2021 .......................... 13-93
TPS2022 .......................... 13-93
TPS2023 .......................... 13-93
TPS2024 .......................... 13-93
TPS2030 ......................... 13-115
TPS2031 ......................... 13-115
TPS2032 ......................... 13-115
TPS2033 ......................... 13-115
TPS2034 ......................... 13-115
TPS2041 ......................... 13-137
TPS2042 ......................... 13-157
TPS2043 ......................... 13-179
TPS2044 ......................... 13-203
TPS2045 ......................... 13-227
TPS2046 ......................... 13-247
TPS2047 ......................... 13-267
TPS2048 ......................... 13-289
TPS2051 ......................... 13-137
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ALPHANUMERIC INDEX
TPS2052 ......................... 13-157
TPS2053 ...... ............ ....... 13-179
....... ...... ...... 13-203
TPS2054
.............. ...... 13-227
TPS2055
............. ....... 13-247
TPS2056
TPS2057 .... .............. ....... 13-267
TPS2058 .... ......... ..... ....... 13-289
TPS2100 ... .......... ..... ....... 13-311
TPS2101 ............. ..... ....... 13-311
TPS2205 ... ...... .... ..... ....... 13-325
TPS2206 ......... ......... ....... 13-349
TPS2211 ... ...... .... ..... ....... 13-375
TPS2212
13-395
TPS2214 ......... ..... .... ....... 13-413
TPS2216 .... ......... ..... ....... 13-437
TPS2811 ........ .... ........... ..... 9-3
TPS2812 .... .... .... .......... ...... 9-3
TPS2813
9-3
TPS2814 ..... ... .... ......... ....... 9-3
TPS2815 ....... ..... ......... ....... 9-3
9-31
TPS2816
TPS2817
9-31
TPS2818
................ .... ... 9-31
TPS2819 ........................... 9-31
TPS2828 ... ............... ......... 9-31
TPS2829 ........................... 9-31
TPS2830 ... ...... ......... ......... 9-49
TPS2831 ... ...... .... ..... ......... 9-49
TPS2832 ......... ... ...... ......... 9-61
TPS2833 .... ........ ......... ...... 9-61
TPS3123J12 .
...... ... ..... 10-21
TPS3123G15 ..... ... .......... ..... 10-21
TPS3123J18 ..... ............ ...... 10-21
TPS3124J12
10-21
TPS3124G15 ............... ........ 10-21
TPS3124J18 ...... ......... ........ 10-21
TPS3125J12 ...... ......... ........ 10-21
TPS3125G15 ...... .... ..... ........ 10-21
TPS3125J18 .......... ..... .... .... 10-21
TPS3125L30 ......... ......... ..... 10-21
TPS3305-18
10-33
TPS3305-25
10-33
TPS3305-33 ............... ........ 10-33
TPS3307-18 ............... ........ 10-43
TPS3307-25 ...... ......... ..... ... 10-43
TPS3307-33 .......... .......... ... 10-43
TPS3705-30 ..... ............. ..... 10-53
TPS3705-33 ..... ............ ...... 10-53
TPS3705-50 ................ ....... 10-53
TPS3707-25 ........... .... ........ 10-53
TPS3707-30 ...... ......... ..... ... 10-53
TPS3707-33 ..... .... ........... ... 10-53
......
.....
.....
•••••••••
••••
0
•••••
••••••
0
0
••••••••••
••••••••••••••••
••
0
••••••••••••••••••••••
••
0
•••
....
0
00
••••••••••••••••••••
........
••
•
0
••••••••••••••••••••
0.0
•••••••••••••••••••
0, • • • • • • • • • • • • • • • • • • • • •
TPS3707-50 . ...................... 10-53
TPS3801J25 ....................... 10-63
TPS3801L30 ....................... 10-63
TPS3801K33 ....................... 10-63
TPS3801150 ........................ 10-63
TPS3809J25 ........................ 10-3
TPS3809L30 ........................ 10-3
TPS3809K33 ........................ 10-3
TPS3809150 ......................... 10-3
TPS3820-25 ....................... 10-71
TPS3820-30 ....................... 10-71
TPS3820-33 ....................... 10-71
TPS3820-50 ....................... 10-71
10-71
TPS3823-25
TPS3823-30 ....................... 10-71
TPS3823-33 ....................... 10-71
TPS3823-50 ....................... 10-71
TPS3824-25
10-71
TPS3824-30 ....................... 10-71
TPS3824-33 ....................... 10-71
TPS3824-50 ....................... 10-71
TPS3825-25
10-71
TPS3825-30
10-71
TPS3825-33 ...................... 10-71
TPS3825-50 ....................... 10-71
TPS3828-25 . ...................... 10-71
TPS3828-30
10-71
TPS3828-33 ....................... 10-71
TPS3828-50 ....................... 10-71
TPS5102 ............................ 7-3
TPS5103 ........................... 7-33
TPS5211 ........................... 7-69
TPS5510 ................... ....... 10-79
TPS5511 .......................... 10-85
TPS5615 ........................... 7-99
TPS5618 ........................... 7-99
TPS5625 ........................... 7-99
TPS5633 ...................... , .... 7-99
TPS5210 .......................... 7-123
TPS5602 .......................... 7-149
TPS5e100 ......................... 7-171
TPS60100
8-3
TPS60101
8-23
TPS60110 .................... ...... 8-43
TPS60111 .......................... 8-61
TPS7101Q .......................... 2-29
TPS7101Y .......................... 2-29
TPS71 025 .......................... 2-59
TPS7133Q .......................... 2-29
2-29
TPS7133Y
TPS7133QPWP ...................... 2-3
TPS7148Q .......................... 2-29
~1ExAs
6-4
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
0
••••••••••••••••••••••
••••••••••••••••••
••••••••••
0
•••••••••
••
.
,
0
0
••••
•••••••••••
0
••••••••••
o ••••••••••••••••••••••
,
•••••
0
•••••••••••••••••••••
••••••••••••••••••••
o •••••
'
•••••••••••••••
0
••••••••••
ALPHANUMERIC INDEX
TPS7148Y ..........................
TPS7150Q ..........................
TPS7150Y ..........................
TPS71H01Q ........................
TPS71H33Q ........................
TPS71 H48Q ........................
TPS71H50Q ........................
TPS7201Q .........................
TPS7201Y .........................
TPS7225Q .........................
TPS7225Y .........................
TPS7228Q .........................
TPS7228Y .........................
TPS7230Q .........................
TPS7230Y .........................
TPS7233Q .........................
TPS7233Y .........................
TPS7248Q .........................
TPS7248Y .........................
TPS7250Q .........................
TPS7250Y .........................
TPS7301Q .........................
TPS7325Q .........................
TPS7330Q .........................
TPS7333Q .........................
TPS7348Q .........................
TPS7350Q .........................
TPS73HD301 ......................
TPS73HD318 ......................
TPS73HD325 ......................
TPS76030 .........................
TPS76032 .........................
TPS76033 .........................
TPS76038 .........................
TPS76050 .........................
TPS76130 .........................
TPS76132 .........................
TPS76133 .........................
TPS76138 .........................
TPS76150 .........................
TPS76301 .........................
TPS76316 .........................
TPS76318 .........................
TPS76325 .........................
TPS76327 .........................
TPS76328 .........................
TPS76330 .........................
TPS76333 .........................
TPS76338 .........................
TPS76350 .........................
TPS76425 .........................
TPS76427 .........................
2-29
2-29
2-29
2-75
2-75
2-75
2-75
2-113
2-113
2-113
2-113
2-113
2-113
2-113
2-113
2-113
2-113
2-113
2-113
2-113
2-113
2-145
2-145
2-145
2-145
2-145
2-145
2-185
2-185
2-185
2-211
2-211
2-211
2-211
2-211
2-221
2-221
2-221
2-221
2-221
2-231
2-231
2-231
2-231
2-231
2-231
2-231
2-231
2-231
2-231
2-247
2-247
TPS76428 .........................
TPS76430 .........................
TPS76433 .........................
TPS76501 .........................
TPS76515 .........................
TPS76518 .........................
TPS76525 .........................
TPS76527 .........................
TPS76528 .........................
TPS76530 .........................
TPS76533 .........................
TPS76550 .........................
TPS76601 .........................
TPS76615 .........................
TPS76618 .........................
TPS76625 .........................
TPS76627 .........................
TPS76628 .........................
TPS76630 .........................
TPS76633 .........................
TPS76650 .........................
TPS76701 Q ........................
TPS76715Q ........................
TPS76718Q ........................
TPS76725Q ........................
TPS76727Q ........................
TPS76728Q ........................
TPS76730Q ........................
TPS16733Q ........................
TPS76750Q ........................
TPS767D301 .......................
TPS767D318 .......................
TPS767D325 .......................
TPS76801Q ........................
TPS76815Q ........................
TPS76818Q ........................
TPS76825Q ........................
TPS76827Q ........................
TPS76828Q ........................
TPS76830Q ........................
TPS76833Q ........................
TPS76850Q ........................
TPS76901 .........................
TPS76912 .........................
TPS76915 .........................
TPS76918 .........................
TPS76925 .........................
TPS76927 .........................
TPS76928 .........................
TPS76930 .........................
TPS76933 .........................
TPS76950 .........................
~TEXAS
INSTRUMENTS
POST OFFICE BOX 1l5S303. DALLAS. TEXAS 75285
2-247
2-247
2-247
2-261
2-261
2-261
2-261
2-261
2-261
2-261
2-261
2-261
2-277
2-277
2-277
2-277
2-277
2-277
2-277
2-277
2-277
2-293
2-293
2-293
2-293
2-293
2-293
2-293
2-293
2-293
2-311
2-311
2-311
2-329
2-329
2-329
2-329
2-329
2-329
2-329
2-329
2-329
2-345
2-345
2-345
2-345
2-345
2-345
2-345
2-345
2-345
2-345
ALPHANUMERIC INDEX
TPS77001 .........................
TPS77012 ...................... ...
TPS77015 .........................
TPS77018 .........................
TPS77025 .........................
TPS77027 .........................
TPS77028 .........................
TPS77030 .........................
TPS77033 .........................
TPS77050 .........................
TPS77501 .........................
TPS77515 .........................
TPS77518 .........................
TPS77525 .........................
TPS77533 .........................
TPS77601 .........................
TPS77615 .........................
TPS77618 .........................
TPS77625 .........................
TPS77633 .........................
TPS77701 .........................
TPS77715 .........................
TPS77718 .........................
TPS77725 .........................
TPS77733 .........................
TPS77801 .........................
TPS77815 .........................
TPS77818 .........................
TPS77825 .........................
TPS77833 .........................
1lA723 .............................
1lA7805 ............................
1lA7806 ............................
2-359
2-359
2-359
2-359
2-359
2-359
2-359
2-359
2-359
2-359
2-373
2-373
2-373
2-373
2-373
2-373
2-373
2-373
2-373
2-373
2-391
2-391
2-391
2-391
2-391
2-391
2-391
2-391
2-391
2-391
2-467
2-479
2-479
1lA7808 ............................
1lA7810 ............................
1lA7812 ............................
1lA7815 ............................
1lA7818 ............................
1lA7824 ............................
1lA78L02 ...........................
1lA78L05 ...........................
1lA78L06 ...........................
1lA78L08 ...........................
1lA78L09 ...........................
1lA78L10 ...........................
1lA78L12 ...........................
1lA78L15 ........ ,..................
1lA78M05 ..........................
1lA78M06 ..........................
1lA78M08 ..........................
1lA78M09 ..........................
1lA78M10 ..........................
1lA78M12 ..........................
1lA79M05 ..........................
1lA79M06 ..........................
1lA79M08 ..........................
1lA79M12 ..........................
1lA79M15 ..........................
UC2842 ...........................
UC2843 ...........................
UC2844 ...........................
UC2845 ...........................
UC3842 ...........................
UC3843 ...........................
UC3844 ...........................
UC3845 ...........................
~TEXAS
6-6
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-479
2-479
2-479
2-479
2-479
2-479
2-493
2-493
2-493
2-493
2-493
2-493
2-493
2-493
2-505
2-505
2-505
2-505
2-505
2-505
2-517
2-517
2-517
2-517
2-517
8-159
8-159
8-159
8-159
8-159
8-159
8-159
8-159
FIXED·VOLTAGE LOW DROPOUT (LDO) VOLTAGE REGULATORS
Tolerance
(%)
(max)
0.245
0.017
3
0.125
0.017
3
0.33
0.038
0.54
0.5
0.5
0.122
0.06
500
1.5
TPS77715
(typ)
(V)
TPS76912
1.224
100
0.122
TPS77012
1.224
50
0.06
TPS76515
1.5
150
0.19
TPS76615
1.5
250
0.31
TPS76715
1.5
1000
TPS76815
1.5
1000
TPS76915
1.5
100
TPS77015
1.5
50
TPS77515
1.5
• TPS77615
~~~
;~~
!~
'"
~
t
Vdo
(max)
(mA)
!il-
~e~
~~
10
(typ)
(V)
I
~
Vo
I
(tYI»)
(mA)
Device
,
Vdo
(max)
(V)
VIN
SVS
13.5
Yes
No
Fixed, LDO, Positive Output, SOT-23
2-345
13.5
Yes
No
Fixed, LDO, Positive Output, SOT-23
2-359
3
13.5
Yes
No
Rxed, LOO, PosHive Output
2-261
0.036
3
13.5
Yes
No
Fixed, LOO, PosHive Output
2-277
0.825
0.085
2
10
Yes
Yes
Fixed, LOO, Positive Output
2-{!93
. 0.825
0.085
2
10
Yes
No
Fixed, LDO, Positive Output
2-329
0.245
0.017
3
13.5
Yes
No
Rxed, LDO, Positive Output, SOT-23
2-345
0.125
0.017
3
13.5
Yes
No
Fixed, LDO, PosHive Output, SOT-23
2-359
0.169
0.287
0.085
2
13.5
Yes
Yes
Fixed, LDO, Positive Output
2-373
500
0.169
0.287
0.085
2
13.5
Yes
No
Fixed, LDO, Positive Output
2-373
1.5
750
0.26
0.427
0.085
2
13.5
Yes
Yes
Rxed, LDO, Positive Output
2-391
TPS77815
1.5
750
0.26
0.427
0.085
2
13.5
Yes
No
Fixed, LDO, Posnive Output
2-391
TPS76316
1.6
150
0.36
0.6
0.085
4
10
Yes
No
Fixed, LOO, PosHive Output, SOT-23
2-231
TPS76318
1.8
150
0.3
0.5
0.085
3.7
10
Yes
No
Fixed, LOO, Positive Output, SOT-23
2-231
TPS73H0318
1.8
750
0.353
0.55
2
10
Yes
Yes
Adjustable, Oual, Fixed, LDO, Positive Output
2-185
TPS76518
1.8
150
0.19
0.33
0.038
3
13.5
Yes
No
Fixed, LDO, Positive Output
2-{!61
TPS76618
1.8
250
0.31
0.54
0.036
3
13.5
Yes
No
Fixed, LDO, Posnive Output
2-277
TPS76718
1.8
1000
0.5
0.825
0.085
2
10
Yes
Yes
Fixed, LOO, PosHive Output
2-293
TPS767D318
1.8
1000
0.35
0.825
0.085
2
10
Yes
Yes
Oual, FIXed, LOO, PosHive Output
2-311
TPS76818
1.8
1000
0.5
0.825
0.085
2
10
Yes
No
Fixed, LOO, Positive Output
2-329
TPS76918
1.8
100
0.122
0.245
0.017
3
13.5
Yes
No
Fixed, LDO, Positive OutPut, SOT-23
2-345
TPS77018
1.8
50
0.06
0.125
0.017
3
13.5
Yes
No
Fixed, LDO, Posftive Output, SOT-23
2-359
TPS77518
1.8
500
0.169
0.287
0.085
2
13.5
Yes
Yes
FIXed, LDO, Posftive Output
2-373
TPS77718
1.8
750
0.26
0.427
0.085
2
13.5
Yes
Yes
Axed, LOO, Posftive Output
2-391
TPS77618
1.8
500
0.169
0.287
0.085
2
13.5
Yes
No
FIXed, LOO, Posftive Output
2-373
TPS77818
1.8
750
0.26
0.427
0.085
2
13.5
Yes
No
FIXed, LOO, Posftive Output
2-391
TPS76325
2.5
150
0.36
0.6
0.085
3.7
10
Yes
No
FIXed, LDO, Posftive Output, SOT-23
2-231
TPS71025
2.5
500
0.33
0.5
TPS7225
2.5
250
TPS7325
2.5
500
0.27
TPS73H0325
2.5
750
0.353
TPS76425
2.5
150
0.36
~TPS76525
2.5
-----
150
0.19
0.6
0.6
0.33
Description
Page No.
Shutdown
(V)
r-
Z
~
o<
:a
~
0.29
2
10
Yes
No
FIXed, LDO, Posftive Output
2-59
CI):J>
me;)
r-m
0.18
2
10
Yes
No
FIXed, LDO, Posftive Output
2-113
Om
oc:
Zr-
0.34
2
10
Yes
Yes
FIXed, LOO, Posftive Output
2-145
0.55
2
10
Yes
Yes
Adjustable, Oual, Fixed, LOO, Posftive Output
2-185
0.085
3.7
10
Yes
No
Rxed, LDO, Positive Output, SOT-23
2-247
Rxed, LDO, Posftive Output
2-261
0.038
3
13.5
Yes
No
m:a
:::Ie;)
e;)~
So
c:a
mCl)
Device
g
o_~
!!:z:
~(I)
So
~~t:~~!::I
.~
~~
~;
10
~
uumr-Z
FIXED-VOLTAGE LOW DROPOUT (LDO) VOLTAGE REGULATORS (continued)
%
Vo
(typ)
(V)
10
(max)
(rnA)
Vdo
(typ)
(V)
Vdo
(max)
I
(ty\)
(V)
(rnA)
Tolerance
(%)
VIN
(max)
Shutdown
SVS
Description
Page No.
(V)
TPS76625
2.5
250
0.31
0.54
0.038
3
13.5
Yes
No
FIXed, LDO, PosHive Output
2-277
TPS76725
2.5
1000
0.5
0.825
0.065
2
10
Yes
Yes
Fixed, LDO, Positive Output
2-293
TPS767D325
2.5
1000
0.35
0.825
0.065
2
10
Yes
Yes
Dual, FIXed, LDO, Positive Output
2~11
TPS76B25
2.5
1000
0.5
0.625
0.065
2
10
Yes
No
Fixed, LDO, Positive Output
2-329
TPS76925
2.5
100
0.122
0.245
0.017
3
13.5
Yes
No
Rxed, LDO, PosHive Output, SOT-23
2~
TPSn025
2.5
50
0.06
0.125
0.017
3
13.5
Yes
No
FIXed, LDO, PosHive Output, SOT43
2~9
TPSn525
2.5
500
0.169
0.287
0.065
2
13.5
Yes
Yes
FIXed, LDO, PosHive Output
2~73
TPSn625
2.5
500
0.169
0.287
0.065
2
13.5
Yes
No
Fixed, LDO, Positive Output
~73
TPSm25
2.5
750
0.26
0.427
0.065
2
13.5
Yes
Yes
Rxed, LDO, Positive Output
2~91
TPSn825
2.5
750
0.26
0.427
0.065
2
13.5
Yes
No
Rxed, LDO, Positive Output
2~1
TPS76327
2.7
150
0.36
0.6
0.065
3.75
10
Yes
No
Rxed, LDO, Positive Output, SOT43
2-231
TPS76427
2.7
150
0.36
0.6
0.065
3.7
10
Yes
No
Rxed, LDO, Positive Output, SOT-23
2,-247
TPS76527
2.7
150
0.19
0.33
0.036
3
13.5
Yes
No
Rxed, LDO, Positive Output
2-261
TPS76627
2.7
250
0.31
0.54
0.036
3
13.5
Yes
No
Rxed, LDO, Positive Output
2-277
TPS76727
2.7
1000
0.5
0.625
0.065
2
10
Yes
Yes
FIXed, LDO, Positive Output
2-293
TPS76B27
2.7
1000
0.5
0.825
0.065
2
10
Yes
No
Rxed, LDO, Positive Output
2~29
TPS76927
2.7
100
0.122
0.245
0.017
3
13.5
Yes
No
Fixed; LDO, Positive Output, SOT-23
2~
TPSn027
2.7
50
0.06
0.125
0.017
3
13.5
Yes
No
Rxed, LDO, Positive Output, SOT43
2~9
TPS76928
2.764
100
0.122
0.245
0.017
3
13.5
Yes
No
Rxed, LDO, Positive Output, SOT-23
2~
TPSn028
0.06
0.125
0.017
3
13.5
Yes
No
Rxed, LDO, Positive Output, SOT-23
2,-359
0.18
2
10
Yes
No
Fixed, LDO, Positive Output
2,-113
0.065
3.75
10
Yes
No
Fixed, LDO, Positive Output, SOT43
2-231
2.764
50
TPS7228
2.8
250
TPS76328
2.8
150
0.35
0.55
TPS76428
2.8
150
0.36
0.6
0.065
3.8
10
Yes
No
FIXed, LDO, Positive Output, SOT 23
2247
TPS76528
2.8
150
0.19
0.33
0.036
3
13.5
Yes
No
Rxed, LDO, PosHive Output
2-261
TPS76B28
2.8
250
0.31
0.54
0.036
3
13.5
Yes
No
Rxed, LDO, PosHive Output
22n
TPS76728
2.8
1000
0.5
0.625
0.065
2
10
Yes
Yes
Rxed, LDO, Positive Output
2-293
TPS76B28
2-329
2.8
1000
0.5
0.625
0.065
2
10
Yes
No
Rxed, LDO, Positive Output
TPS7230
3
250
0.39
0.9
0.18
2
10
Yes
No
Rxed, LDO, Positive Output
2,-113
TPS7330
3
500
0.052
0.075
0.34
2
10
Yes
Yes
Rxed, LDO, PosHive Output
2-145
TPS76030
3
50
0.12
0.18
0.65
3
16
Yes
No
Rxed, LDO, Positive Output, SOT43
2-211
TPS76130
3
100
0.17
0.28
2.6
3.6
16
Yes
No
Fixed, LDO, Positive Output, SOT-23
2-221
TPS76330
3
150
0.35
0.55
0.065
3.75
10
Yes
No
Rxed, LDO, PosHive Output, SOT43
2,-231
TPS76430
3
150
0.36
0.6
0.065
3.8
10
Yes
No
Rxed, LDO, Positive Output, SOT 23
2447
m!:
5l::D
5<
zO
C)~
c:l>
-C)
iCm
m::D
m
C)
c:
r-
o~
~
FIXED-VOLTAGE LOW DROPOUT (LDO) VOLTAGE REGULATORS (continued)
Device
Vo
(typ)
(V)
10
(max)
(mA)
I
Vdo
(typ)
(max)
(V)
(ty~)
Tolerance
(V)
(mA)
Vdo
(%)
VIN
(max)
Shutdown
SVS
Description
Page No.
(V)
TPS76530
3
lSO
0.16
0.28
0.038
3
13.5
Yes
No
FIXed, LDO, Positive Output
2261
TPS76630
3
2SO
0.31
0.54
0.038
3
13.5
Yes
No
FIXed, LDO, Positive Output
2-277
TPS76730
3
1000
0.45
0.675
0.085
2
10
Yes
Yes
FIXed, LDO, Positive Output
2-293
TPS76830
3
1000
0.45
0.675
0.085
2
10
Yes
No
FIXed, LDO, Positive Output
2~9
TPS77030
3
50
0.048
0.1
0.017
3
13.5
Yes
No
Fixed, LOO, Positive Output, SOT-23
2-359
TPS76930
3.09
100
0.115
0.23
0.017
3
13.5
Yes
No
FIXed, LOO, PosHive Output, SOT-23
2-345
TPS76032
3.2
50
0.12
0.18
0.85
3.1
16
Yes
No
FIXed, LOO, Positive Output, SOT 23
2211
TPS76132
3.2
100
0.17
0.28
2.6
3
16
Yes
No
Fixed, LOO, PosHive Output, SOT-23
2-221
TPS7133QPWP
3.3
SOO
0.047
0.06
0.285
2
10
Yes
No
Fixed, LOO, PosHive Output
2-3
TPS7133
3.3
500
0.047
0.06
0.285
2
10
Yes
No
Fixed, LOO, PosHive Output
2-29
@
TPS71H33
3.3
500
0.047
0.06
0.285
2
10
Yes
No
Fixed, LOO, Positive Output
275
~-
TPS7233
3.3
2SO
0.14
0.18
0.155
2
10
Yes
No
Fixed, LDO, Positive Output
2-113
TPS7333
3.3
500
0.044
0.06
0.34
2
10
Yes
Yes
Rxed, LDO, Positive Output
2-145
TPS76033
3.3
SO
0.12
0.18
0.85
3
16
Yes
No
Fixed, LDO, PosHive Output, SOT-23
2-211
TPS76133
3.3
100
0.17
0.28
2.6
3
16
Yes
No
Fixed, LDO, Positive Output, SOT-23
2-221
TPS76333
3.3
150
0.3
0.5
0.085
3.7
10
Yes
No
Fixed, LDO, PosHive Output, SOT 23
2-231
TPS76433
3.3
150
0.3
0.5
0.085
3.7
10
Yes
No
Fixed, LDO, Positive Output, SOT-23
2-247
TPS76533
3.3
150
0.14
0.24
0.038
3
13.5
Yes
No
Rxed, LDO, Positive Output
2-,261
TPS76633
3.3
250
0.23
0.4
0.038
3
13.5
Yes
No
Fixed, LDO, Positive Output
2-277
TPS76733
3.3
1000
0.35
0.575
0.085
2
10
Yes
Yes
Rxed, LDO, Positive Output
2-293
TPS76833
3.3
1000
0.35
0.575
0.085
2
10
Yes
No
Rxed, LDO, PosHive Output
2~9
TPS76933
3.3
100
0.098
0.2
0.017
3
13.5
Yes
No
Rxed, LDO, PosHive Output, SOT-23
2-345
Z
TPS77033
3.3
SO
0.048
0.1
0.017
3
13.5
Yes
No
Rxed, LDO, Positive Output, SOT-23
2-359
:J>
TPS77533
3.3
500
0.169
0.287
0.085
2
13.5
Yes
Yes
Rxed, LDO, Positive Output
2-373
TPS77633
3.3
500
0.169
0.287
0.085
2
13.5
Yes
No
Rxed, LDO, Positive Output
2-373
TPS77733
3.3
750
0.26
0.427
0.085
2
13.5
Yes
Yes
Rxed, LDO, Positive Output
2-391
TPS77833
3.3
750
0.26
0.427
0.085
2
13.5
Yes
No
Rxed, LDO, Positive Output
2-391
TLV2217-33
3.3
500
0.4
0.5
19
1
12
No
No
LDO
2-461
enl>
mC)
.... m
TPS76038
3.8
SO
0.12
0.18
0.85
2.6
16
Yes
No
Rxed, LDO, PosHive Output, SOT-23
2-211
Om
TPS76138
3.8
100
0.17
0.28
2.6
3
16
Yes
No
Rxed, LDO, Positive Output SOT-23
2221
TPS76338
3.8
150
0.38
0.6
0.085
3.5
10
Yes
No
Rxed, LDO, PosHive Output SOT-23
2-231
oc
z ....
TPS7148
4.85
500
0.03
0.037
0.285
2
10
Yes
No
Rxed, LDO, Positive Output
2-29
TPS71H48
4.85
500
0.03
0.047
0.285
2
10
Yes
No
Rxed, LDO, PosHive Output
275
~z~
i~~~
!:it:
.~
~rr.I
~?i
~CIi
"j
%
....
m
::D
~
~
m::D
::!C)
C)~
SO
C::D
men
(I)!::
FIXED-VOLTAGE LOW DROPOUT (LDO) VOLTAGE REGULATORS (continued)
~
o
I
(typ)
Vdo
(max)
M
M
(ty1.)
(mA)
0.09
0.1
0.155
2
10
0.037
0.34
2
0.033
0.285
2
0.033
0.285
0.76
0.85
0.027
M
10
(max)
(rnA)
TPS7248
4.85
250
TPS7348
4.85
SOO
0.028
TPS7150
5
SOO
0.027
TPS71H50
5
SOO
0.027
TPS7250
5
250
TPS7350
5
500
Vo
Device
(typ)
Vdo
Tolerance
VIN
Description
Page No.
~:o
Fixed, LDO, Positive Output
2-113
00
Yes
Fixed, LDO, Positive Output
2-145
No
Fixed, LDO, Positive Output
2-29
C)~
Yes
No
Rxed, LDO, Positive Output
2-75
10
Yes
No
Fixed, LDO, Positive Output
2-113
m:o
10
Yes
Yes
Rxed, LOO, PosRive Output
2-145
C)
Shutdown
SVS
Yes
No
10
Yes
10
Yes
2
10
0.155
2
0.035
0.34
2
(%)
(max)
M
TPS76050
5
SO
0.12
0.18
0.85
2
16
Yes
No
Rxed, LDO, Positive Output, SOT-23
2-211
• TPS76150
5
100
0.17
0.28
2.6
2.8
16
Yes
No
Rxed, LDO, PosRive Output, SOT-23
2-221
;
TPS76350
5
1SO
0.18
0.3
0.085
4
10
Yes
No
Rxed, LDO, PosRive Output, SOT-23
2-231
• TPS76550
5
1SO
0.085
0.15
0.038
3
13.5
Yes
No
Rxed, LDO, PosRive Output
2-261
§
TPS76850
5
250
0.14
0.25
0.038
3
13.5
Yes
No
Fixed, LDO, Positive Output
2-277
~-
TPS767SO
5
1000
0.23
0.38
0.085
2
10
Yes
Yes
Fixed, LDO, PosRive Output
2-293
TPS76850
5
1000
0.23
0.38
0.085
2
10
Yes
No
FIXed, LDO, Positive Output
2-329
TPS78950
5
100
0.071
0.17
0.017
3
13.5
Yes
No
Rxed, LDO, PosRive Output, SOT-23
2-345
TPS77050
5
SO
0.035
0.085
0.017
3
13.5
Yes
No
Rxed, LDO, PosRive Output, SOT-23
2-359
TL7SOL05
5
1SO
0.2
0.6
10
4
26
No
No
FIXed, LDO, PosRive Output
2-421
TL7SOM05
5
7SO
0.5
0.6
60
2
26
No
No
FIXed, LDO, Positive Output
2-429
~z~
!Ir
;~
iil
III
mZ
r-m
ml>
TL751L05
5
1SO
0.2
0.6
10
4
26
Yes
No
Fixed, LDO, Positive Output
2-421
TL751M05
5
7SO
0.5
0.6
60
2
26
Yes
No
Fixed, LDO, Positive Output
2-429
TL7SOL08
8
1SO
0.2
0.7
10
4
26
No
No
Fixed, LDO, PosRive Output
2-421
TL7SOM06
8
7SO
0.5
0.7
60
2
26
No
No
Rxed, LDO, PosRive Output
2-429
TL751L06
8
1SO
0.2
0.7
10
4
26
Yes
No
FIXed, LDO, Positive Output
2-421
TL751M08
8
7SO
0.5
0.7
60
2
26
Yes
No
FIXed, LDO, Positive Output
2-429
TL7SOL10
10
1SO
0.2
0.8
10
4
26
No
No
Fixed, LDO, Positive Output
2-421
TL7SOM10
10
7SO
0.5
0.8
60
2
26
No
No
FIXed, LDO, Positive Output
2-429
TL751L10
10
1SO
0.2
0.8
10
4
26
Yes
No
Fixed, LDO, Positive Output
2-421
TL751M10
10
7SO
0.5
0.8
60
2
26
Yes
No
Fixed, LDO, Positive Output
2-429
TL7SOL12
12
1SO
0.2
0.9
10
4
26
No
No
Rxed, LDO, PosRive Output
2-421
TL7SOM12
12
7SO
0.5
0.9
60
2
26
No
No
Rxed, LDO, Positive Output
2-429
TL751L12
12
1SO
0.2
0.9
10
4
26
Yes
No
FIXed, LDO, Positive Output
2-421
TL751M12
12
750
0.5
0.9
60
2
26
Yes
No
Rxed, LDO, PosHive Output
2-429
-<
Zr"'"
SC)
em
m
c:
r-
!4
o
~
ADJUSTABLE OUTPUT-VOLTAGE REGULATORS
Device
Vo
Adjustable
(nom)
(V)
~
~z4r
ji~d
~~
~l'!1
i~
'"
~
10
(max)
(mA)
Vdo
(typ)
(V)
Vdo
(max)
(V)
(~)
Tolerance
(mA)
(%)
VIN
(max)
Shutdown
SVS
Description
Page No.
(V)
TPS76501
1.2-5.5
150
0.16
0.33
0.038
3
13.5
Yes
No
Adjustable, LOO, Positive Output
2-261
TPS76601
1.2-5.5
250
0.23
0.54
0.038
3
13.5
Yes
No
Adjustable, LDO, Positive Output
2-277
TPS76701
2-293
1.5-5.5
1000
0.5
0.625
0.065
2
10
Yes
Yes
Adjustable, LOO, Positive Output
TPS767D301
1.2-5.5
1000
0.35
0.625
0.065
2
10
Yes
Yes
Adjustable, Dual, Axed, LOO, Positive Output
2-311
TPS76601
1.5-5.5
1000
0.5
0.825
0.065
2
10
Yes
No
Adjustable, LDO, Positive Output
2-329
TPS76901
1.2-5.5
100
0.071
0.245
0.017
3
13.5
Yes
No
Adjustable, LDO, Positive Output. SOT-23
2-345
TPS77oo1
1.2-5.5
50
0.035
0.125
0.017
3
13.5
Yes
No
Adjustable, LDO, Positive Output, SOT-23
2-359
TPS77501
1.2-5.5
500
0.169
0.287
0.065
2
13.5
Yes
Yes
Adjustable, LOO, Positive Output
2-373
TPS77601
1.2-5.5
500
0.169
0.287
0.065
2
13.5
Yes
No
Adjustable, LOO, Positive Output
2-373
TPS77701
1.2-5.5
750
0.26
0.427
0.085
2
13.5
Yes
Yes
Adjustable, LOO, Positive Output
2-391
TPS77601
1.2-5.5
750
0.26
0.427
0.065
2
13.5
Yes
No
Adjustable, LDO, Positive Output
2-391
TPS76301
1.5-6.5
150
0.6
0.6
0.065
3
10
Yes
No
Adjustable, LDO, Positive Output, SOT-23
2-231
TPS71 01
1.2-9.75
500
0.052
0.065
0.265
3
10
Yes
No
Adjustable, LDO
2-29
TPS71H01
1.2-9.75
500
0.052
0.085
0.265
3
10
Yes
No
Adjustable, LDO
2-75
TPS7201
1.2-9.75
250
0.16
0.27
0.155
3
10
Yes
No
Adjustable, LDO
2-113
TPS7301
1.2-9.75
500
0.052
0.065
0.34
3
10
Yes
Yes
Adjustable, LDO
2-145
TPS73H0301
1.2-9.75
750
0.353
0.6
1.1
3
10
Yes
Yes
Adjustable, Dual, Fixed, LDO, Positive Output
2-165
TL317
1.2-32
100
2.5
3
1.5
4
35
No
No
Adjustable
2-415
pA723
2-37
150
3
2.3
1
40
No
No
Adjustable
2-467
TL783
1.25-125
700
15
15
6
125
No
No
Adjustable
2-449
LM237
-1.2--37
1500
2.2
No
No
3-Terminal Adjustable Regulator
2-409
LM337
-1.2--37
1500
2.2
No
NO
3·Terminal Adjustable Regulator
2-409
10
r-
Z
!:
:u
~
~
en)li
mG)
r-m
m:u
Om
::tG)
oc:
ZrG)!i
!
~
So
c:u
men
r-Z
(max)
(mA)
Vdo
(typ)
(V)
Vdo
(max)
2
100
1.7
TL-5CSI285
2.85
TL2217-285
2.85
!'A7805
5
1500
!'A78L05
5
100
!'A78L05A
5
!'A78M05
TL78!Hl5
...
~~~
It:~
~3:~
i~
~
I
(ty~)
SVS
(mA)
VIN
(max)
(V)
Shutdown
(V)
Tolerance
(%)
3
3.6
5
20
No
No
500
0.7
26
1
5.5
500
1
26
1.5
5.5
2
3
4.2
4
25
No
2
3
3.8
10
20
No
100
1.7
3
3.8
5
20
5
500
2
3
4.5
4
5
1500
2
3
5
1
!'A7806
6
1500
2
3
4.3
!'A78LOS
6
100
1.7
3
!'A78L06A
6
100
1.7
!'A78MOS
6
500
2
!'A7808
8
1500
2.5
!'A7885
8
1500
!'A78L08
8
100
!'A78LOBA
8
!'A78M08
8
!'A78L09
9
!'A78L09A
9
!'A78L02A
@
lll-.....
10
Vo
(typ)
(V)
Device
~~
enrm-
FIXED POSITIVE-OUTPUT VOLTAGE VOLTAGE REGULATORS
!
'"
mm
Description
PagaNo.
0:1>
..... :11
-<
go
Fixed, Postlive Output
2-493
No
Fixed Reg. for SCSI Active Termination
2-527
No
Fixed Reg. for SCSI Active Termination
2-533
No
Fixed, Positive Output
2-479
No
Fixed, Positive Output
2-493
m:ll
No
No
Fixed, Positive Output
2-493
Ci)
25
No
No
Fixed, PosHive Output
2-505
25
No
No
Fixed, Positive Output
2-441
4
25
No
No
Fixed, Positive Output
2-479
3.9
10
20
No
No
Fixed, Posijive Output
2-493
3
3.9
5
20
No
No
Fixed, Positive Output
2-493
3
4.5
4
25
No
No
Fixed, Positive Output
2-505
3
4.3
4
25
No
No
Fixed, Positive Output
2-479
2
3
4.3
4
25
No
No
Fixed, Positive Output
2-479
1.7
3
4
10
23
No
No
Fixed. PosHive Output
2-493
100
1.7
3
4
5
23
No
No
Fixed, PosHive Output
2-493
500
2.5
3
4.6
4
25
No
No
Fixed, PosHlve Output
2-505
100
1.7
3
4.1
10
24
No
No
Fixed, Positive Output
2-493
100
1.7
3
4.1
5
24
No
No
Fixed, Positive Output
2-493
!'A78M09
9
500
2.5
3
4.6
4
26
No
No
Fixed, PosHive Output
2-505
!'A7810
10
1500
2.5
3
4.3
4
28
No
No
FIXed, Positive Output
2-479
!'A78Ll0
10
100
1.7
3
4.2
10
25
No
No
Fixed, Positive Output
2-493
!'A78Ll0A
10
100
1.7
3
4.2
5
25
No
No
Fixed, Postllve Output
2-493
!'A78Ml0
10
500
2.5
3
4.6
4
28
No
No
Fixed, PosHive Output
2-505
TL780-12
12
1500
2.5
3
5.5
1
30
No
No
Fixed, PosHive Output
2-441
!'A7812
12
1500
2.5
3
4.3
4
30
No
No
FIXed, Positive Output
2-479
!'A78L12
12
100
1.7
3
4.3
10
27
No
No
Fixed, Positive Output
2-493
!'A78LI2A
12
100
1.7
3
4.3
5
27
No
No
Fixed, PosHlve Output
2-493
!'A78MI2
12
500
2.5
3
4.8
4
30
No
No
FIXed, PosHive Output
2-505
TL780-15
15
1500
2.5
3
5.5
1
30
No
No
Fixed, Positive Output
2-441
!'A7815
15
1500
2.5
3
4.4
4
30
No
No
Fixed, PosHlve Output
2-479
!'A78L15
15
100
1.7
3
4.6
10
30
No
No
Fixed, Postllve Output
2-493
!'A78LI5A
15
100
1.7
3
4.6
5
30
No
No
Fixed, PosHlve Output
2-493
-~-
Ci)~
c:::l>
-Ci)
Om
m
c:::
r-
~
o
:II
en
FIXED POSITIVE-OUTPUT VOLTAGE VOLTAGE REGULATORS (continued)
Device
Vo
(typ)
M
10
(max)
(mA)
Vdo
(typ)
Vdo
(max)
M
M
I
(tylj,)
(mA)
Tolerance
(%)
VIN
(max)
Shutdown
SVS
Description
Page No.
M
11A78M15
15
500
2.5
3
4.8
4
30
No
No
FIXed. PosHive Output
2-505
11A7818
18
1500
3
3
4.5
4
33
No
No
Fixed. Positive Output
2-479
11A78M20
20
500
3
3
4.9
4
35
No
No
Fixed. Positive Output
2-505
11A7824
24
1500
3
3
4.6
4
38
No
No
Fixed. Positive Output
2-479
11A78M24
24
500
3
3
5
4
38
No
No
Fixed. PosHive Output
2-505
FIXED NEGATIVE-OUTPUT VOLTAGE VOLTAGE REGULATORS
~
(V)
Vdo
(max)
(V)
I
(tylj,)
(mA)
z...
3l
~cn~·
500
2
3
1
4
-25
No
No
Fixed. Negative Output
2-517
500
2
3
1
4
-25
No
No
Fixed. Negative Output
2-517
-8
500
2.5
3
1
4
-25
No
No
Fixed. Negative Output
2-517
11A79M12
-12
500
2.5
3
1.5
4
-30
No
No
Fixed. Negative Output
i:a~d
~~
"'t:
2-517
11A79M15
-15
500
2.5
3
1.5
4
-30
No
No
Fixed. Negative Output
2-517
11A79M20
-20
500
3
3
1.5
4
-35
No
No
Fixed. Negative Output
2-517
11A79M24
-24
500
3
3
1.5
4
-J8
No
No
Rxed. Negative Output
!~
2-517
10
Vo
(typ)
(V)
(max)
(mA)
11A79M05
-5
11A79M06
-5
11A79M08
Device
Vdo
(typ)
Tolerance
(%)
VIN
(max)
Shutdown
SVS
Description
Page No.
M
~
j
r-
Z
m
l>
::0
~
~
J«l;
r-m
m::o
Om
::::!ei)
Zrei):!i
oc:
!:c.>
So
c::o
men
en en
SHUNT REGULATORS
l...
Device
Vref
(V)
IZ
(min)
IZ
(max)
(mA)
UtA}
Vo
(min)
Vo
(max)
(V)
(V)
Tolerance
(%)
VI
(max)
(V)
Temp
Coeff
m::E:
Description
Page No.
0 .....
::!::o
(typ)
Om
(ppm/oC)
TLV431A
1.24
100
15
Vref
6
1
6
46
Adjustable Shunt
3-45
TL1431
2.5
1000
100
Vref
36
0.4
36
30
Adjustable Shunt
3-27
TL431
2.5
1000
100
Vref
36
2
36
30
Adjustable Shunt
3-9
TL431 A
2.5
1000
100
Vref
36
1
36
30
Adjustable Shunt
3-9
TLV431
2.5
1000
100
Vref
36
2
36
30
Adjustable Shunt
3-45
TL430
2.75
2000
100
Vref
30
9
30
120
Adjustable Shunt
3-3
g
o_~
3l:z:
~ (I)
!OO.
~~d
!f~
n~~
jUl
'"
~
Device
TL.E2425
10
(typ)
(mA)
Output Regulation
(typ)
Vo
(min)
Vo
(max)
VI
(max)
UtA}
(V)
(V)
(V)
20
-45-15
2.48
2.52
40
(typ)
c:re~
mo
::0
S»
a
-a
m
o
en
Description
Page No.
(ppm/oC)
20
ZG)
G)C:
::0
PRECISION VIRTUAL GROUNDS
Temp
Coeff
r-c:
mZ
Precision Virtual Ground
4-3
oZ
<
~
§;
r-
G)
::0
o
c:
Z
c
PROCESSOR POWER SUPPLY CONTROLLERS
Device
~
0_...
~~~.
;~~
~~~
i~
~
Droop
Comp
OCP
Output
Drive
Current
(A)
Outputs
OVP
Power
Good
Soft
Start
UVLO
VIN
(V)
Vo
(typ)
(V)
Vref
(tol)
(±%)
Description
Page No.
TPS5102
No
Yes
1.5
2
No
No
Yes
Yes
4.5-25
1.2 - Vee
1.5
Notebook
7-3
TPS5103
No
Yes
1.5
1
No
No
Yes
Yes
4.5-25
1.2-Vee
1.5
Multipurpose
7-33
7-123
TPS521 0
Yes
Yes
2
1
Yes
Yes
Yes
Yes
5, 12
pgm 1.3 to 3.5
1
Pentium class
TPS5211
Yes
Yes
2.4
1
Yes
Yes
Yes
Yes
5, 12
pgm 1.3 to 3.5
1.5
Pentium class
7-69
TPS5602
No
Yes
1
2
No
No
Yes
Yes
4.5-25
1.2- Vee
2
DSP
7-149
TPS56100
No
Yes
2
1
Yes
Yes
Yes
Yes
5
O.9- Vee
1.5
DSP
7-171
TPS5615
No
Yes
2
1
Yes
Yes
Yes
Yes
5,12
1.5
1
DSP
7-99
TPS5618
No
Yes
2
1
Yes
Yes
Yes
Yes
5,12
1.8
1
DSP
7-99
TPS5625
No
Yes
2
1
Yes
Yes
Yes
Yes
5, 12
2.8
1
DSP
7-99
~5633
No
Yes
2.4
1
Yes
Yes
Yes
Yes
5, 12
3.3
1
DSP
7-99
""0
~
o
m
~
:D
~m
:D
en
c:
en::g
mrr-<
mO
00
:::!Z
0-1
Z:D
C)O
!
C)
C):D"'U
CC)O
SG2524
Yes
No
8-40
Single Switch
100
SOO
NAt8
5
4
90
No
Voltage-Mode
PWM
8-97
SG3524
Yes
No
8-40
Single Switch
100
500
NAt8
5
8
90
No
Voltage-Mode
PWM
8-97
TL494
No
No
7-40
Single Switch
200
300
7.5/6
5
5
90
No
Voltage-Mode
PWM
8-111
8-121
8-129
mO
8-137
mZ
_m:e
~"'Um
C:D
1:(1)
"'U
C
O"'U
O"'U
TL497A
Yes
No
4.5-12
Single Switch
500
SO
11/6
1.2
5
No
Fixed On-Time
Voltage-Mode
TL499A
No
No
1.1~
Single Switch
500
40
1.81NA
1.26
5
No
FIXed On-Time
Voltage-Mode
TL594
No
No
7-40
Single Switch
200
300
12.419
5
1
90
Yes
TL598
No
No
7-40
Totem Pole
-2SO
300
151NA
5
1
90
Yes
Voltage-Mode
PWM
8-149
oI"""
UC2842
No
Yes
30
Totem Pole
-200
500
ll/NA
5
1
97
Yes
Current-Mode
PWM
8-159
m
UC2843
No
Yes
30
Totem Pole
-200
500
liINA
5
1
97
Yes
Current-Mode
PWM
8-159
UC2844
No
Yes
30
Totem Pole
-200
SOO
liINA
5
1
97
Yes
Current-Mode
PWM
8-159
UC2845
No
Yes
30
Totem Pole
-200
500
liINA
5
1
97
Yes
Current-Mode
PWM
8-159
UC3842
No
Yes
30
Totem Pole
-200
SOO
liINA
5
2
97
Yes
Current-Mode
PWM
8-159
UC3843
No
Yes
30
Totem Pole
-200
500
liINA
5
2
97
Yes
Current-Mode
PWM
8-159
UC3844
No
Yes
30
Totem Pole
-200
500
ll/NA
5
2
97
Yes
Current-Mode
PWM
8-159
UC3845
No
Yes
30
Totem Pole
-200
500
ll/NA
5
2
97
Yes
Current-Mode
PWM
8-159
TL5OO1
No
No
3.8-40
Single Switch
20
400
1.111
1
5
100
Yes
TL500IA
No
No
3.8-40
Single Switch
20
400
1.1/1
1
3
100
Yes
Voltage-Mode
PWM
8-79
Yes
Dual ChannelModePWM
8-171
.
LT1054
---
No
No
3.6-15
Totem Pole
±loo
2000
3.513.1
1.25
2.5
100
------ - -
Voltage-Mode
PWM
Voltage-Mode
PWM
~!:(
~O
:D~
I"""
:D
D)
8-79
::::lI
a..
DC/DC CHARGE PUMP CONVERTERS
Device
SHDN
VO
(typ)
(V)
Tolerance
(%)
VIN
Range
(VDC)
Output
Current
(mA)
Freq
(max)
(kHz)
Quiescent
Currant
(1lA)
Shutdown
Current
UVLO
Description
Page No.
(IlA)
TPS60100
Yes
3.3
±4
1.8-3.6
200
300
50
0.05
Yes
Charge Pump DCIOC Converter, 3.3-V
8-3
TPS60101
Yes
3.3
±4
1.8--3.6
100
300
50
0.05
Yes
Charge Pump DCIOC Converter, 3.3-V
8-23
TPS60110
Yes
5
±4
2.7--5.4
300
300
60
0.05
Yes
Charge Pump DCIOC Converter, 5-V
8-43
TPS60111
Yes
5
±4
2.7--5.4
150
300
60
0.05
Yes
Charge Pump DC/DC Converter, 5-V
8-61
"
0
~
o_~
I~i
~~
~
6:::e
z)
G'
C"V
Qo
c=:
Om
o::D
:::ecn
~c
::D"V
G')"V
m!<
cn"Vo
mCo
r-!:!i
m"V
~
m
~O::D
-00
OZrZ
em
men
PMOS DISTRIBUTION SWITCHES
~
Device
Number
ofFETs
rO~on)
(typ)
(mO)
VOS
(max)
(V)
100
(max)
(A)
ESO
Circuitry
Description
Page No.
en."
mo
r-:e
mm
~XJ
TPS1100
1
180
15
1.6
Yes
High-Side PMOS
13-3
OC
zci)
TPS1101
1
90
15
2.3
Yes
High-Side PMOS
13-13
Q-I
TPS1120
2
180
15
1.17
Yes
High-Side PMOS
13-23
c::!!
-UJ
Cc:
m-l
oz
~
=i
o
C3
~
~Z'"
i~~::·
~t::
-1:
~l"r1
~~
~
j
:x
m
en
LED DRIVERS
Device
Vref
(V)
TLC5904
2.5
IZ
(min)
Vo
(min)
Vo
(max)
UtA)
IZ
(max)
(mA)
(V)
(V)
1000
100
Vref
36
Tolerance
(%)
VI
(max)
(V)
Temp
Coeff
(typ)
(ppmI"C)
Description
Page No.
30
LED Driver
14-3
36
0.4
VOLTAGE RAIL SPLITTERS
Device
TLE2426
ICC
!llA)
VCC
(V)
10
(mA)
280
4-40
20
Vo
(min)
Vo
(max)
(V)
(V)
Temp
Coeff
(typ)
(ppm/°C)
1.98
20.2
25
Description
Rail Splitter Precision Virtual Ground
Page No.
15-3
SPECIAL FUNCTIONS
g ....
0_
2~~·
~~d
~t:~
':~tii
~~
~CJ)
'"
~
Device
TL7726
TL2218--285
Vref
(V)
IZ
(min)
(1lA)
4.5
IZ
(max)
(1lA)
Vo
(min)
(V)
60
-20.5
2.5
Input
Clamp
Current
(mA)
Settling
Time
(1lS)
25
30
Description
Page No.
Hex Clamping Circuit
16-3
Excalibur Current-Mode SCSI Terminator
16-7
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6-26
:II
1ExAs
INSTRUMENTS
POST OFFICE BOX 6553030 DAUAS. TEXAS 75265
General Information (Vol. 1)
I Linear Voltage Regulators
I Shunt Regulators
I Precision Virtual Grounds
Mechanical Data
I General Information (Vol. 2)
Processor PS Controllers
Switching PS and DC/DC Converters
MOSFET Drivers
Supervisors
Mechanical Data
General Information (Vol. 3)
Power Distribution Switches
LED Drivers
Voltage Rail Splitters
Special Functions
Mechanical Data
7-1
•a
"'tJ
(')
CD
tn
tn
o
...
"'tJ
en
oo
...o...::s
CD
Ul
7-2
TPS5102
DUAL, HIGH·EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
DBTPACKAGE
(TOP VIEW)
• Dual, Step-Down for Notebook System
Power
• 4.5 V to 25 V Input Voltage Range
• Adjustable Output Voltage
• 95% Efficiency Achievable
• PWM/Skip Mode Control Maintains High
Efficiency Under Light Load Conditions
• Fixed-Frequency Operation
• Resistorless Current Protection
• Fixed High-Side Driver Voltage
• Low Quiescent Current (0.6 rnA, <1 J.IA for
Standby)
• Small 3D-Pin TSSOP
• EVM Available (TPS5102EVM-135)
INV1
FB1
SOFTSTART1
PWM_SKIP
LH1
OUT1 _u
LL1
OUT1_d
OUTGND1
TRIP1
VCC_CNTP
TRIP2
VREF5
REG5V_IN
OUTGND2
OUT2_d
LL2
OUT2_u
LH2
4
CT
RT
GND
REF
STBY1
STBY2
Vee
COMP
SOFTSTART2
FB2
INV2
description
The TPS51 02 is a dual, high efficiency controller designed for notebook system power requirements. Under light
load conditions, high efficiency is maintained as the controller switches from the PWM mode to the lower
frequency Skip mode.
These two operating modes, along with the synchronous-rectifier drivers, dead-time, and very low quiescent
current, allow power to be conserved and the battery life extended, under all load conditions.
The resistor-less current protection and fixed high-side driver voltage simplify the system design and reduce
the external parts count. The wide input voltage range and adjustable output voltages allow flexibility for using
the TPS5102 in notebook power supply applications.
5V-~
1.~r---~R3~--------------------~r-------~
T
CI
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R7
GN0"""1
C,,, C7
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:+<- -'-
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TPS51020BT w
OUTID
1-'"'--____
1-''"'---____-+---'
-+__--'\j'l'r-:R.::9'--+
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~TEXAS
Copyright © 1999, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-3
TPS5102
DUAL, HIGH·EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
functional block diagram
Vee
r-----~---------
I
I
STNBY2
--+----+-----,.......
S~BY1
-+----+-----i--'
VREF5
REF
--+---+--.----------411--+-0-(
1.185 V
-+....:..:..:.=-:.-+-+-------1
--------------~
------l~--------;- REG5V_IN
r-----------~r ~
.------------~- ~
eOMP-t----~~
,-------!-
LH
'------.-----t-
LL
-=-1.1 V
if,
PWMlSKIP - + - - - - - - - ;
SOFTSTA~ j-.. . . ----ISiOFi~~11
'---__--q,,?I10----+--+-
To
ehannel2
INV -f---t---t----i
FB-+---t---t-----~----+_~
I
I
I
I
-=-1.185V
if,
l,f
~
______________________________ J
~TEXAS
INSTRUMENTS
7--4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
OUT_D
'-------I----Ir- OUTGND
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
AVAILABLE OPTIONS
EVM
PACKAGE
TA
TSSOP(DBT)
-40°C to 85°C
TPS51021DBT
TPS5102EVM-135
TPS51021DBTR
Terminal Functions
TERMINAL
NAME
NO_
DESCRIPTION
I/O
COMP
12
I/O
CT
5
I/O
Voltage monitor comparator input
External capacitor connection for switching frequency adjustment
FB1
2
0
0
CH1 error amp output
CH2 error amp output
FB2
14
GND
7
INV1
1
I
CH1 inverting input
INV2
15
I
CH2 inverting input
LH1
30
I/O
CH1 boost capacitor connection
LH2
16
I/O
CH2 boost capacitor connection
ControlGND
LL1
28
I/O
CH1 boost circuit connection
LL2
18
I/O
CH2 boost circuit connection
OUTCd
27
I/O
CH1 low-side gate-drive output
OUT2 d
19
CH2 low-side gate-drive output
OUTCu
29
OUT2 u
17
0
0
0
OUTGND1
26
OUTGND2
20
PWM_SKIP
4
I
PWM/SKIP mode select
H:SKIPmode
L:PWMmode
REF
8
0
1.185-V reference voltage output
REG5V_IN
21
I
External 5-V Input
RT
6
I/O
External resistor connection for switching frequency adjustment
SOFTSTART1
3
I/O
External capacitor connection for CH1 soft start timing.
SOFTSTART2
13
I/O
STBY1
9
I
CH1 stand-by control
CH1 high-side drive output
CH2 high-side drive output
OutputGND 1
OutputGND2
External capacitor connection for CH2 soft start timing.
STBY2
10
I
CH2 stand-by control
TRIP2
23
I
External resistor connection for CH2 over current protection.
TRIP1
25
I
VCC
11
Vref5
22
0
5-V internal regulator output
VCC CNTP
24
I
Supply voHage sense input
External resistor connection for CH1 over current protection.
Supply voltage input
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-5
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239· SEPTEMBER 1999
detailed description
Vref (1.185 V)
The reference voltage is used to set the output voltage and the overvoltage protection (COMP).
Vref5 (5 V)
The internal linear voltage regulator is used for the high-side driver bootstrap voltage. Since the input voltage
range Is from 4.S V to 2S V, this feature offers a fixed voltage for the bootstrap voltage greatly simplifying the
drive design. It is also used for powering the low side driver. The tolerance is 6%.
5-VSwltch
If the internal S V switch senses a S-V input from REGSV_IN pin, the internal S-V linear regulator will be
disconnected from the MOSFET drivers. The external S V will be used for both the low-side driver and the high
side bootstrap, thus increasing the efficiency.
PWM/SKIP
This pin is used to change between PWM and Skip mode. If the pin is lower than O.S-V, the IC is in regular PWM
mode; if a minimum 2-V is applied to this pin, the IC works in Skip mode. In light load condition «0.2 A), the
skip mode gives a short pulse to the low-side FET instead of a full pulse. By this control, switching frequency
is lowered, reducing switching loss; also the output capaCitor energy discharging through the output inductor
and the low-side FET is prevented. Therefore, the IC can achieve high efficiency at light load conditions
« 0.2 A).
err-amp
Each channel has its own error amplifier to regulate the output voltage of the synchronous-buck converter. It
is used in the PWM mode for the high output current condition (>0.2A). Voltage mode control is applied.
skip comparator
In Skip mode, each channel has its own hysteretic comparator to regulate the output voltage of the
synchronous-buck converter. The hysteresis is set internally and typically at 8.S mY. The. delay from the
comparator input to the driver output is typically 1.2 118.
low-side driver
The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The maximum drive voltage is S V
from VrefS. The current rating of the driver is typically 1 A, source and sink.
high-side driver
The high side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
1 A, source and sink. When configured as a floating driver, the bias voltage to the driver is developed from VrefS,
limiting the maximum drive voltage between OUT_u and LL to S V. The maximum voltage that can be applied
between LHx and OUTGND is 30 V.
deadtlme control
Deadtime prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the tum-on time of the MOSFETs drivers. The typical deadtime from
low-side-driver-off to high-side-driver-on is 70 ns, and 8S ns from high-side-driver-off to low-side-driver-on.
~TEXAS
7-6
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239· SEPTEMBER 1999
detailed description (continued)
current protection
Current protection is achieved by sensing the high·side power MOSFET drain-to-source voltage drop during
on-time at VCC_CNTP and LL. An external resistor between Yin and TRIP pin in serial with the internal current
source adjusts the current limit. When the voltage drop during the on-time is high enough, the current
comparator triggers the current protection and the circuit is reset. The reset repeats until the over-current
condition is removed.
COMP
COMP is an internal comparator used for any voltage protection such as the output under-voltage protection
for notebook power applications. If the core voltage is lower than the setpoint, the comparator turns off both
channels to prevent the notebook from damage.
SOFT1, SOFT2
Separate soflstart terminals make it possible to set the start-up time of each output for any possibility.
STBY1, STBY2
Both channels can be switched into standby mode separately by grounding the STBY pin. The standby current
is as low as 1 J.IA.
ULVO
When the input voltage goes up to about 4 V, the IC is turned on, ready to function. When the input voltage is
lower than the turn-on value, the IC is turned off. The typical hysteresis is 40 mY.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-7
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
absolute maximum ratings over operating free-air temperature {unless otherwise noted)t
Supply voltage, Vcc (see Note 1) ................................................... -0.3 V to 27 V
Input voltage, INV ................................................................. -0.3 V to 7 V
SOFTSTART ......................................................... -0.3 V to 7 V
COMP .............................................................. -0.3 V to 6 V
REG5_IN ............................................................ -0.3 V to 6 V
STBY .............................................................. -0.3 V to 15 V
Driver ,current ................................................................ 3 A
TRIP ............................................................... -0.3 V to 27 V
CT .................................................................. -0.3 V to 7 'Ii
RT .................................................................. -0.3 V to 7 V
LL ................................................................. -0.3 V to 27 V
LH ................................................................. -0.3 V to 32 V
OUT_u ............................................................. -0.3 V to 32 V
OUT_d .............................................................. -0.3 V to 7 V
PWM/SKIP .......................................................... -0.3 V to 7 V
VCC_Sense ......................................................... -0.3 V to 27V
Power dissipation (TA 25°C) ........................................................... 874 mW
Operating temperature (TA) ........................................................ -40°C to 85°C
Operating temperature (TJ) ....................................................... -40°C to 125°C
Storage temperature (TSTG) ..................... \ ................................ -55°C to 150°C
=
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These ara stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. This rating is specified at duty S 10% on output rise and fall each pulse. Each pulse width (rise and fall) for the peak current should
not exceed 2 lIS.
3. See Dissipation Rating Table for free-air temperature range above 25°C.
DISSIPATION RATING TABLE
PACKAGE
TAs25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA=85°C
POWER RATING
DBT
874mW
6.993mWloC
454mW
recommended operating conditions
PARAMETERS
MIN
Supply voltage, Vee
INV1/2 CT RT,
PWM/SKIP,
-0.1
V
-0.1
V
25
CT
100
pF
AT
82
kn
fose
PWM
200
Operation temperature range, TA
-40
~TEXAS
7-8
5.5
12
VCC SENSE
UNIT
6
STBY1, STBY2
TRIP1/2
MAX
25
SOFTSTART
5 V_IN
Input voltage, VI
Oscillator frequency
NOM
4.5
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
KHz
85
°C
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, Vee
(unless otherwise noted)
=7 V
reference voltage
PARAMETER
Vref
TEST CONDITIONS
TA = 25°C,
Reference voltage
Ivref = 50 /lA
MIN
TYP
MAX
U67
1.185
1.203
1.155
Ivref = 50 /lA
Regin
Line regulation
Vcc = 4.5, 25V,
Regl
Load regulation
I = 0.1 /lA to 1 mA
1=50/lA
1.215
UNIT
V
0.2
12
mV
0.5
10
mV
TYP
MAX
quiescent current
PARAMETER
TEST CONDITIONS
lee
Operating current without switching
Both STBY > 2.5 V,
No switching,
Yin = 4.5-25 V
Ices
Stand-by current
Both STBY < 0.5 V, Vin = 4.5 - 25 V
MIN
UNIT
0.6
1.5
mA
1
1000
nA
TYP
MAX
UNIT
500
kHz
oscillator
PARAMETER
fose
Frequency
RT
TIming resistor
MIN
56
fdv
felt
TEST CONDITIONS
PWM operation
Vee = 4.5 V to 25 V
: fosc change
2%
TA = -40°C to 85°C
VoscH
H-Ievel output voltage
VoscL
L-Ievel output voltage
k.Q
0.1%
DC, Includes internal comparator error
1
Fose = 200 kHz, Includes internal comparator error
Includes intemal comparator error
1.1
1.2
1.17
0.4
Fose = 200 kHz, Includes internal comparator error
0.5
0.6
0.43
V
V
error amp
PARAMETER
TEST CONDITIONS
Vio
Input offset voltage
Av
Open-loop voltage gain
GB
Unity-gain bandwidth
Isnk
Output sink current
Vo =0.4 V
Isrc
Output source current
Vo=1 V
MIN
TA = 25°C
TYP
MAX
UNIT
±2
±10
mV
dB
50
30
0.8
MHz
45
/lA
300
/lA
skip comparator
PARAMETER
TEST CONDITIONS
Vhyst
Hysteresis window
Vhoff
Offset voltage
Ihbias
Bias current
TLHT
Propagation delay:f: from INV to OUTxU
TLH
t Vhys Is assured by design.
:f: The total delay in the table includes the driver delay.
MIN
TYP
MAX
6
9.5
13
UNIT
mV
2
mV
10
pA
TTL input signal
0.7
f1S
10 mVoverdrive on hysteresis band signal
1.2
f1S
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
7--fJ
TPS5102
DUAL, HIGH·EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range,
(unless otherwise noted) (continued)
vee
=7 V
MAX
UNrr
driver deadtime
PARAMETER
TEST CONDITIONS
MIN
TYP
TORVLH
Low side to high side
70
nS
TORVHL
High side to low side
85
nS
standby
PARAMETER
VIH
H-Ievel input voltage
VIL
L-level input voltage
Ttumon'
Propagation delay
Ttumoff
Propagation delay
TEST CONDITIONS
MIN
TYP
MAX
2.5
STBY1, STBY2
0.5
UNrr
V
1.5
STBY to driver Ou1put
Jl.S
1.8
5Y regulator
TEST CONDITIONS
PARAMETER
Va
Output voltage
1=10mA
Regin
Une regulation
Vee = 5.5 V, 25 V,
1=10mA
Vcc=5.5V
MIN
TYP
4.7
Regl
Load regulation
1=1 V,10mA,
los
Short-circuit output current
Vref= OV
MAX
UNIT
5.3
V
20
mV
40
mV
80
mA
5-Y internal switch
PARAMETER
VTLH
TEST CONDITIONS
: Threshold voltage
VTHL
Vhvs
Hysteresis
MIN
TYP
MAX
UNIT
4.2
4.8
4.1
4.7
V
V
30
150
mV
UYLO
PARAMETER
VTLH
TEST CONDITIONS
: Threshold voltage
VTHL
Vhys
Hysteresis
MIN
TYP
MAX
UNIT
3.7
4.2
3.6
4.1
V
150
mV
10
40
V
current limit
PARAMETER
Internal current source
TEST CONDITIONS
MIN
TYP . MAX
PWMmode
10
15
20
Skip mode
3
5
7
Input offset voltage
2.5
UNIT
ItA
mV
driver output
PARAMETER
OUT_u sink current
OUT_d sink current
OUT_u source current
OUT_d source current
TEST CONDITIONS
Vo=3V
Vo=3V
~TEXAS
INSTRUMENTS
7-10
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
MIN
TYP
0.5
1.2
0.5
1.2
-1
-1.7
-1
-1.5
MAX
UNIT
A
A
TPS5102
DUAL, HIGH·EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, Vcc
(unless otherwise noted) (continued)
=7 V
softstart
TEST CONDITIONS
PARAMETER
ICTRL
Soft-start current
MIN
TYP
MAX
1.8
2.5
3
0.92
Maximum discharge current
VTLH
: Threshold voltage (skip mode)
VTHL
UNIT
I1A
rnA
3.4
3.9
4.7
1.8
2.6
3.4
MIN
TYP
MAX
0.9
1.1
1.3
V
output voltage protection (COMP)
PARAMETER
TEST CONDITIONS
Threshold voltage
Progagation delayt, 50% duty cycle,
No capacitor on COMP or OUT_u pin,
Frequency = 200 kHz
UNIT
V
Tumon
900
ns
Turnoff (with channel on)
400
ns
t The delay time In the table Includes the driver delay.
PWM/SKIP
PARAMETER
Threshold
Delay
TEST CONDITIONS
MIN
TYP
Low to high
MAX
0.5
High to low
2
High to low
550
Low to high
400
UNIT
V
ns
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-11
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239· SEPTEMBER 1999
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT (BOTH CHANNELS ON)
QUIESCENT CURRENT (BOTH CHANNELS STANDBy)
va
vs
INPUT VOLTAGE
INPUT VOLTAGE
800
160
ITJ = 1250C
700
3
I
&
!
2.5
~
i5
2
~
1.5
0
BI
2
.l...
~
:ii'
c
'>"
>"
01
01
0
0.1
0.5
I(arc) • Driver Source Current· A
0.5
0
0.1
Figure 3
7-12
1\
Figure 2
6
I
"- I'.ll
10
15
20
VCC· Supply Voltage· V
7
Figure 1
>
V
/
20
o
V
0.5
I(ank) • Driver Sink Current· A
Figure 4
:'IlExAs
INSTRUMENTS
p
I
CD
aI
!
~
0.6
l!
0.5
11
!
0.4
I
0.3
~
t
/'
0.7
5.1
TJ = -40°C
l"
.I
TJ = 25°C
25
vs
INPUT VOLTAGE
,
20
Vref5 VOLTAGE
vs
0.8
15
Figure 6
Figure 5
0.9
10
VCC - Supply Voltage - V
VCC - Supply Voltage - V
5
TJ = 125°C
,
>
4.9
I
------
Lr---1
-- ---- -= 125
4.8
~
0.2
.........
'"" "
TJ=-40°C'
I
>
c
l.. r--
TJ = 25°C
III
~
CURRENT
4.7
4.6
0.1
o
o
10
20
30
4.5
o
VI- Supply Voltage - V
-10
-20
-30
-40
-50
Ir - Current - rnA
Figure 7
Figure 8
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-13
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239· SEPTEMBER 1999
TYPICAL CHARACTERISTICS
SOFT START CHARGE CURRENT
vs
JUNCTION TEMPERATURE
MAXIMUM OUTPUT VOLTAGE
vs
SWITCHING FREQUENCY
2.5
-2.5~-+-+--+--+--+-+----l--I
2
c
t
~
'S
~
-2
CJ
1.5
II
t
!!l
01
-1.5
.c
\
0
E
::J
E
CJ
t:
Dl
';
-1
i
:::I
0.5
o
-O.51--+-+--+--+-+-+---If--I
O~~_~_~~
1
10
-40
1000
100
Switching Frequency - kHz
Figure 10
Figure 9
SWITCHING FREQUENCY
vs
TIMING RESISTOR
1000
Ct= 47pF
(
.J-
"'-
=
V~
=
I
.~
100
Ct= 100pF
i'I.
Ct=150pF
-
"
~~
~
Ct=220pF
'" '"
"-
""
Ct =330 pF
"
10
10
100
Timing Resistor - kO
Figure 11
~TEXAS
7-14
__~__~~~--J
-20
0
25
50
70
95
TJ - Junction Temperature - °C
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1000
125
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
TYPICAL CHARACTERISTICS
timing diagram
High
Low
I
II
I
Over-Current
II
I
I
__I________
----l+----J+----;_-++_----.,i---L___I-l-_'/etected
~er C~rrent
~
~II
Protection
_
Inductor Current
II
II
i
II
I
II
==t-tll---I~60=l-:
LLXVoltagel_-Iul-lo
I I
I
I
I
II
I
II
I
II
I
'-----I-_-L._ High
Low
I
I
+ul-t - -lI"l=T=R~=Px=v°=l-til-g-Iu""=oHU-l-_l-+~""....,j.t+-·
_e
~~D
.....
H_-+.u-+L+-N
__
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-15
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239· SEPTEMBER 1999
APPLICATION INFORMATION
The design shown in this application report is a reference design for notebook applications. An evaluation
module (EVM), TPS5102EVM-135 (SLVP135), is available for customer testing and evaluation, The intent is
to allow a customer to fully evaluate the given design using the plug-in EVM supply shown here, For subsequent
customer board revisions, the EVM design can be copied onto the users' PCB to shorten design cycle.
The following key design procedures will aid in the design of the notebook power supply using the TPS51 02:
TP27 SLVP135 EVM
R3~16J
Fj~
R6
ca"
~
TP3
C911
~TP4
TP5
C10\l
R9 ,II
JP1 A
Rl
""'_U
1
\ICC_
TP9
TP10 ..
R12
':'
C12"
TP12 12
C13\1
II
TP13 "
TP14 ..
C1~
R13t
R14
.,;.
L...
TP22
.
'"
"
"""
..,.
0U12..
0U12..
TP15
~,
'f' C17
'I
TP19
R21
.Y~
~C21
,.
TP1~
f
02
~~D1 C4+*
'04
II
R20
C2°)I_
r~GND
GND
Vo1
C22
~ Q3
~3
"~
...
C5
.~D2
~
TP25
RS1
J2
~
Vo1
~ Vo1GND
I
+
~
~Q4
TP28
R1B c'i6
R1
'"*"
TP18
TP16
~
R19
TP20
'R
'7
L1
R18
d~
TP21
SY_IN
TP11
JP2
tl:
TP2~ "
""'- "'"
,.
"""
TP8
R11
31
~~2
~3
ouroND1
TP6
C11\1
II
..
TP24.
Rl.1 28
TP7
I
[
""
TP2
\1
@01
R17
U1
TPS5192
TP1
I*C7
F
TP26
+
"*"
C2
+
Vo1GND
Vm
Vin
InpulGND
InputGND
10 V02GND
11
Vo2GND
1
V02
13
Vo2
14
RS2
R2
L2
--+-
Vin
lin
V01
101
V02
102
6 Vlo 1S V
6A
3.3 V
4A
SV
4A
3,3V
2.SA
SV
2.SA
16Vl02SV
output voltage setpolnt calculation
The output voltage is set by the reference voltage and the voltage divider, In the TPS51 02, the reference voltage
is 1,185-V, and the divider is composed of two resistors in the EVM design that are R4 and R5, orH14and R15,
The equation for the setpoint is:
R2. = R1 x Vr
Vo-Vr
Where R1 is the top resistor (Idl) (R4 or R15); R2 is the bottom resistor (kn) ( R5 or R14); Vo is the required
output voltage (V); Vr is the reference voltage (1,185 V in TPS51 02),
Example: R1
=1 Idl; Vr =1,185 V; Vo =3,3 V, then R2 =560 n,
Some of the most popular output voltage setpoints are calculated in the table below:
1.3V
1.SV
1.8V
2.SV
3.3V
R1 (lop) (kO)
1V
1V
1V
1V
1V
1V
R2 (bottom) (kO)
10V
3.7V
1.9V
0.9V
0.S6V
0.31 V
Vo
~TEXAS
7-16
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SV
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239" SEPTEMBER 1999
APPLICATION INFORMATION
output voltage setpolnt calculation (continued)
If a higher precision resistor is used, the voltage setup can be more accurate.
In some applications, the output voltage is required to be lower than the reference voltage. With a few extra
components, the lower voltage can be easily achieved. The drawing below shows the method.
vee
Rz1
Vo
?
R(top)
INV
Rz2
TPS5102
Zener
~~
'\'1
R(bottom)
V
In the schematic, the Az1, the Az2, and the zener are the extra components. Az1 is used to give the zener
enough current to build up the zener voltage. The zener voltage is added to INV through Az2. Therefore, the
voltage on the INV is still equal to the Ie internal voltage (1.185 V) even if the output voltage is regulated at a
lower setpoint. The equation for setting up the output voltage is shown below:
(Vz-Vr)
Rz 2 = (Vr-Vo)
Vr
--mop+ Rbtm
When Az2 is the adjusting resistor for low output voltage; Vz is the zener voltage; Vr is the internal reference
voltage; Atop is the resistor of the voltage sensing network; Abtm is the bottom resistor of the sensing
network;VO is the required output voltage setpoint.
Example: Assuming the required output voltage setpoint is Vo
Then the Az2 = 2.43 kO.
=0.8 V, Vz =5 V; Atop =1 kn; Abottom =1 kn,
output Inductor ripple current
The output inductor current ripple can affect not only the efficiency, but also the output voltage ripple. The
equation is exhibited below:
I' t - Vin - Vout - lout x (Rdson + RL)
D
T:
nppeLout
x x s
Where lripple is the peak-to-peak ripple current (A) through the inductor; Vin is the input voltage (V); Voutis the
output voltage (V); lout is the output current; Rdsonis the on-time resistance of M08FET (0); Dis the duty cycle;
and Ts is the switching cycle (8). From the equation, it can be seen that the current ripple can be adjusted by
changing the output inductor value.
Example: Vin
=5 V; Vout =1.8 V; lout =5 A; Adson = 10 mO; AL =5 mO; D = 0.36; Ts =10 118; Lout =6 I1H
=2 A.
Then, the ripple Iripple
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-17
TPS5102
DUAL, HIGH·EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239· SEPTEMBER 1999
APPLICATION INFORMATION
output capacitor RMS current
Assuming the inductor ripple current totally goes through the output capaCitor to ground, the RM8 current in the
output capacitor can be calculated as:
lorms
=.4L
.ff2
Where lo(rms) is the maximum RMS current in the output capacitor (A); 111 is the peak-to-peak inductor ripple
current (A).
Example: ..11 = 2 A, so lo(rms) = 0.58 A
Input capacitor RMS current
Assuming the input ripple current totally goes into the input capaCitor to the power ground, the RM8 current in
the input capacitor can be calculated as:
lirms
= /102 x
0
x (1-0) + 110 x Iripple2
Where li(rms) is the input RMS current in the input capacitor (A); 10 is the output current (A); Iripple is the
peak-to-peak output inductor ripple current; 0 is the duty cycle. From the equation, it can be seen that the
highest input RM8 current usually occurs at the lowest input voltage, so it is the worst case design for input
capacitor ripple current.
Example: 10 = 5 A; D = 0.36; Iripple = 2 A,
Then, Ii(rms) = 2.42 A
soft-start
The soft-start timing can be adjusted by selecting the soft-start capacitor value. The equation is
C soft
=2 x
Tsoft
Where Csoft is the soft-start capacitance (IlF) (C9 or C13 in EVM design); Tsoft is the start-up time (8).
Example: Tsoft = 5 mS, so Csoft = 0.01IlF.
~TEXAS
INSTRUMENTS
7-18
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS5102
DUAL, HIGH·EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
current protection
The current limit in TPS5102 on each channel is set using an internal current source and an external resistor
(R18 or R19). The sensed high side MOSFET drain-to-source voltage drop is compared to the set point, if the
voltage drop exceeds the limit, the internal oscillator is activated, and it continuously reset the current limit until
the over-current condition is removed. The equation below should be used for calculating the external resistor
value for current protection setpoint:
R 1= Rds(on)
x
c
(Itrip
+
Iind(p-p)/2)
0.000015
In skip mode,
R
(=
Rds(on) x (ltrip
c
+
Iind(p-p)/2)
0.000005
Where Rcl is the external current limit resistor (R10 or R11); Rds(on) is the high side MOSFET (01 or 03)
on-time resistance. Itrip is the required current limit; lind(p-p) is the peak-to-peak output inductor current.
Example for voltage mode: Rds(on) = 10 mO, Itrip = 5 A, lind = 2 A, so Rcl = 4 kO.
loop-gain compensation
Voltage mode control is used in this controller for the output voltage regulation. To achieve fast, stabilized
control, two parts are discussed in this section: the power stage small signal modeling and the compensation
circuit design.
For the buck converter, the small signal modeling circuit is shown below:
r--------,
a
I ~a
I D
I
I
ZL
r------,
I RL
L
I
.-~~~~~~nn~-+_.--~
I
Vo
I
I
I
I
--'
p
From this equivalent circuit, several control transfer functions can be derived: input-to-output, output
impedance, and control-to-output. Typically the control-to-output transfer function is used for the feedback
control design.
Assuming Rc and RL are much smaller than R, the simplified small signal control-to-output transfer function is:
Vod
=
/\
Vo
~
=
(1
1
+ sCRc)
s[ x(RC + RL) +~] + s2LC
+ C
Where C is the output capacitance; Rc is the equivalent serial resistance (ESR) in the output capacitor; L is the
output inductor; RL is the equivalent serial resistance (OCR) in the output inductor; R is the load resistance.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-19
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239· SEPTEMBER 1999
APPLICATION INFORMATION
loop-gain compensation (continued)
To achieve fast transient response and the better output voltage regulation, a compensation circuit is added to
improve the feedback control. The whole system is shown:
Vref
The typical compensation circuit used as an option in the EVM design is a part of the output feedback circuit.
The circuitry is displayed below:
C1
>--......-
ToPWM
This circuit is composed of one integrator, two poles, and two zeros:
Assuming R1 « R2 and C2« C3, the equation is:
(1
Comp
+ sC3R4)
x (1
= sC3R2(1 + sC2R4)
+ sC2R2)
+ sC1 R1)
(1
Therefore,
2.1r~ R1
Zero1
= 2.1rckR2
= 2.1rckR4
Zer02
= 2.1r6R4
Pole1 =
Pole2
_
1
Integrator - 2.1rC3R2
A simplified version used in the EVM design is exhibited below:
~TEXAS
INSTRUMENTS
7-20
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239· SEPTEMBER 1999
APPLICATION INFORMATION
loop-gain compensation (continued)
Vo
R2
>--.....R3
ToPWM
Vref
Assuming C2 « C3, the equation is:
(1 + sC3R4)
+ sC.2R4)
Comp = sC3R2(1
There is one pole, one zero and one integrator:
Zero = 2n'6aR4
Integrator = 2n'f6R2
1
Pole _- 2n'C.2R4
The loop-gain concept is used to design a stable and fast feedback control. The loop-gain equation is derived
by the control-to-output transfer function times the compensation:
Loop-gam=
Vod x Comp
The amplitude and the phase of this equation can be drawn with software such as MathCad. In tum, the stability
can be easily designed by adjusting the compensation parameters. The sample bode plot is shown below to
explain the phase margin, gain margin, and the crossover frequency.
The gain is drawn as 20 log (loop-gain), and the phase is in degrees. To explain them clearer, 180 degrees is
added to the phase, so that the gain and phase share the same zero.
The crossover frequency is the point at which the gain curve touches zero. The higher this frequency, the faster
the transient response, since the transient recovery time is 1/(crossover frequency). The phase is the phase
margin. The phase margin should be at least 60 degrees to cover all changes such as temperature. The gain
margin is the gap between the gain curve and the zero when the phase curve touches zero. This margin should
be at least 20 dB to guarantee stability over all conditions.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
7-21
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239· SEPTEMBER 1999
APPLICATION INFORMATION
20 Log (Loop·Gain)
180 + Phase
f - Frequency - Hz
synchronization
Some applications require switching clock synchronization. There are two methods that can be used for
synchronization: the triangle wave synchronization and the square wave synchronization.
The triangle wave synchronization is displayed below:
TPS5102
CI
It can be seen that both Rt and Ct are removed from the circuit. Therefore, two components are saved. This
method is good for the synchronization between two controllers. If the controller needs to be synchronized with
a digital circuit such as DSP, the square-type clock signal is usually used. The configuration exhibited below is
for this type of application:
i TEXAS
NSTRUMENTS
-!I1I
7-22
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239· SEPTEMBER 1999
APPLICATION INFORMATION
synchronization (continued)
TPS5102
An external resistor is added into the circuit, but Rt is still removed. Ct is keptto be a part of RC circuit generating
triangle waveform for the controller. Assuming the peak value of the square is known, the resistor and the
capacitor can be adjusted to achieve the correct peak-to-peak value and the offset value.
layout guidelines
Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult
than most general PCB designs. The general design should proceed from the switching node to the output,
then back to the driver section and, finally, parallel the low-level components. Below are several specific points
to consider before the layout of a TPS51 02 design begins.
•
All sensitive analog components should be referenced to ANAGND. These include components connected
to Vref5, Vref, INV, LH, and COMPo
•
Analog ground and drive ground should be isolated as much as possible. Ideally, analog ground will connect
to the ground side of the bulk storage capaCitors on Va, and drive ground will connect to the main ground
plane close to the source of the low-side FET.
•
Connections from the drivers to the gate of the power FETs should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
•
The bypass capacitor for Vee should be placed close to the TPS51 02.
•
When configuring the high-side driver as a floating driver, the connection from LL to the power FETs should
be as short and as wide as possible.
•
When configuring the high-side driver as a floating driver, the bootstrap capaCitor (connected from LH to
LL) should be placed close to the TPS51 02.
•
When configuring the high-side driver as a ground-referenced driver, LL should be connected to DRVGND.
•
The bulk storage capacitors across Vln should be placed close to the power FETS. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
•
High-frequency bypass capacitors should be placed across the bulk storage capaCitors on Va.
•
LH and LL should be connected very close to the drain and source, respectively, of the high-side FET. LH
and LL should be routed very close to each other to minimize differential-mode noise coupling to these
traces.
•
The output voltage sensing trace should be isolated by either ground trace or Vcc trace.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-23
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239· SEPTEMBER 1999
APPLICATION INFORMATION
PWM AND SKIP MODE EFFICIENCY
COMPARISON
95
=3.3 V
Output
90
I
80
100
.,,--
85
o
r
,r(
85
70
65
0.4
0.6
0.8
60
1.2
o
0.2
.1
90
'#.
I
I
85
80
/
J
70
It
100
---
10'
t---
90
'#.
I
85
r;
PWMMode
c
80
m
75
~
SklpMode
Output = 5 V
JI
lU,,,-
H-
4
5
60
Skip Mode
I
o
10 • Output Current· A
Figure 14
7-24
PWMMode
II
65
3
-
I~
70
2
1.2
I
95
I
o
0.8
EFFICIENCY
va
OUTPUT CURRENT
.~
65
0.6
Figure 13
=3.3 .I.V
If
I
75
60
Output
0.4
10 • Output Current· A
EFFICIENCY
va
OUTPUT CURRENT
I
I
PWMMode
I
I
75
Figure 12
I
l
/.1 Sk~Mode
10 • Output Current· A
95
IT
L--'
90
80
0.2
100
=5V.!
95
I
,I
70
...
Output
Skip Mode
/J
75
60
-
/ {/
'#.
I
~
I
85
..1.
PWMM~
PWM AND SKIP MODE EFFICIENCY
COMPARISON
2
3
10 • Output Current· A
Figure 15
:II
1ExAs
INSTRUMENTS
POST OFFICE BOX 655300 • DALlAS. TEXAS 75265
4
5
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239· SEPTEMBER 1999
APPLICATION INFORMATION
EFFICIENCY
OUTPUT LOAD REGULATION
vs
OUTPUT CURRENT
100
.1
3.4
I.
Output Load
Dual Output Efficiency
95
/
90
.,.
I
~
c
CD
'u
IE
w
= 3.3 V
3.38
-
.....
,
3.36
>
I
CD
85
~
'5
80
f
0
75
I
3.34
3.32
3.3
3.28
~ 3.26
70
3.24
65
60
3.22
o
40
20
60
80
3.2
100
2
0
Output Current - %
OUTPUT LOAD REGULATION
Output Load
I
CD
al
!
~
3.4
=5 V
Output Line
,
5.06
5.04
3.36
>
.......
I
.............
CD
5.02
~
3.34
3.32
5
'5
3.3
0
4.98
0
I
3.28
~ 4.96
~ 3.26
4.94
3.24
4.92
3.22
I
4.9
= 3.3 V
3.38
'5
f
5
OUTPUT LINE REGULATION
5:08
>
4
Figure 17
Figure 16
5.1
3
10 • Output Current - A
f
o
2
4
3
5
3.2
0
10 - Output Current - A
10
20
30
VI- Input Voltage - V
Figure 18
Figure 19
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-25
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239· SEPTEMBER 1999
APPLICATION INFORMATION
OUTPUT LINE REGULATION
5.1
Output Line
5.09
,
>
I
CD
~
'!!i
!
0
I
DIODE VERSION EFFICIENCY
95
=5 V
I
I
Output Diode Version
90
5.08
85
5.07
5.08
f
_I
=3.3 V
/
-
80
5.05
/
5.04
75
~ 5.03
70
5.02
65
5.01
5
5
10
15
20
25
30
60
o
2
3
10 " Output Current" A
VI" Input Voltage" V
Figure 20
Figure 21
3.3-V OUTPUT VOLTAGE RIPPLE
5-V OUTPUT VOLTAGE RIPPLE
T
T
Figure 22
Figure 23
~TEXAS
7-26
4
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
Table 1. Bill of Materials
REF.
PN
DESCRIPTION
RV-35V221MH10-R
Capacitor, electrolytic, 220 I1F, 35 V
Cltopt
10TPB220M
C2
GMK325Fl06ZH
C3
C4
Cl
MANUFACTURER
SIZE
ELNA
10xl0mm
Capacitor, POSCAP, 220 I1F, 10 V
$anyo
7.3x4.3mm
Capacitor, ceramic, 10 I1F, 35 V
TaiyoYuden
1210
GMK325Fl06ZH
Capacitor, ceramic, 10 I1F, 35 V
Talyo Yuden
1210
4TPB470M
Capacitor, POSCAP, 470 I1F, 4 V
Sanyo
7.3x4.3mm
C5
10TPB220M
Capacitor, POSCAP, 220 I1F, 10 V
Sanyo
7.3x4.3mm
C5t opt
6TPB330M
Capacitor, POSCAP, 330 I1F, 6.3 V
Sanyo
7.3x4.3mm
C6t
Standard
Open, capacitor, ceramic, 0.22 I1F, 16 V
C7
Standard
Capacitor, ceramic, O,OlI1F, 16 V
805
C8
Standard
Capacitor, ceramic, 220 pF, 16 V
805
805
805
C9
Standard
Capacitor, ceramic, O.OlI1F, 16 V
Cl0
Standard
Capacitor, ceramic, 100 pF, 16 V
Cll
Standard
Capacitor, ceramic, l11F, 16 V
muRata
C12
GMK316F225ZG
Capacitor, ceramic, 2.2 I1F, 35 V
TaiyoYuden
C13
Standard
Capacitor, ceramic, 0.01 I1F, 16 V
805
805
1206
805
C14
Standard
Capacitor, ceramic, 220 pF, 16 V
805
C15
Standard
Capacitor, ceramic, O.lI1F, 16 V
805
C16t
Standard
Open, capacitor, ceramic, 0.1 I1F, 16 V
C17
GMK316F225ZG
Capacitor, ceramic, 2.2I1F, 35 V
C18
Standard
Open
C19
Standard
Open
C20
GMK325Fl06ZH
Capacitor, ceramic, 10 I1F, 35 V
TaiyoYuden
C21
GMK316F225ZG
Capacitor, ceramic, 2.2I1F, 35 V
TalyoYuden
805
TaiyoYuden
1206
805
805
C22t
1210
1206
7.3x4.3mm
C23t
7.3x4.3mm
Dl
MBRS340T3
Diode, Schottky, 40 V, 3 A
Motorola
D2
MBRS340T3
Diode, Schottky, 40 V, 3 A
Motorola
SMC
SMC
D3
SD103-AWDICT-ND
Diode, Schottky, 40 V, 200 mA
Digikey
3.5xl.5mm
D4
SD103-AWDICT-ND
Diode, Schottky, 40 V, 200 mA
Digikey
3.5xl.5mm
Ll
D03316P-682
Inductor, 6.8I1H, 4.4 A
Coilcraft
0.5xO.37in
l2
D03316P-682
Inductor, 6.8 I1H, 4.4 A
Collcraft
0.5xO.37in
Jl.J16
CA26DA-D36W-OFC
Edge connector, surface mount, 0.040" board, 0.090"
standoff
NAS Interplex
O.04Oin
JPl
Sll32-2-ND
Headar, straight, 2-pin, 0.1
Sullins
DigiKey # 1132-2-ND
JPl shunt
Sl132-14-ND
Shunt, jumper, 0.1"
Sullins
DigiKey#
929950-QO-ND
JP2
Sl132-14-ND
Header, straight, 2-pin, 0.1 ctrs, 0.3" pins
Sullins
DigiKey # 1132-2-ND
Rl
Standard
Resistor, 5.1
R2
Standard
Resistor, 5.1 C, 5%
805
R3t
Standard
Open
805
R4
Standard
Resistor, 1.21 k11, 1%
805
R5
Standard
Resistor, 680 C, 1%
805
R6
Standard
Resistor, 5.1 kO, 5%
805
R8
Standard
Resistor, 1 k11, 5%
805
ctrs, 0.3" pins
no 5%
805
t Option table
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • OALlAS, TEXAS 75265
7-27
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
Table 1. Bill of Materials (continued)
REF.
PN
DESCRIPTION
MANUFACTURER
SIZE
R9
Standard
Resistor, 82 ko, 5%
805
R10
Standard
Resistor, 1 lin, 5%
805
R11
Standard
Resistor, 0 0, 5%
805
R12
Standard
Resistor, 1 ill, 5%
805
R13
Standard
Reistor, 1 ill, 5%
805
R14
Standard
Resistor, 310 ill, 1%
805
R15
Standard
Resistor, 1 ill, 1%
805
R16t
Standard
Open resistor, 5.1 0, 5%
805
R17
Standard
Resister, 15 0, 5%
805
R18
Standard
Resistor, 7.5 kO, 5%
805
R19
Standard
Resistor, 7.5 ko, 5%
805
R20
Standard
Resistor, 15 0, 5%
805
R21
Standard
Open
Q1
Si4410DY
Transistor, MOSFET, n-<:h, 30 V, 10 A, 13 mO,
Siliconix
Q2
Si4410DY
Transistor, MOSFET, n-<:h, 30 V, 10 A, 13 mO,
Siliconix
SO-8
Q3
Si4410DY
Transistor, MOSFET, n-<:h, 30 V, 10 A, 13 mO,
Siliconlx
SO-8
Q4
Si4410DY
Transistor, MOSFET, n-<:h, 30 V, 10 A, 13 mO,
Siliconix
SO-8
U1
TPS5102
IC, Dual Controller
TI
TSSOP
805
SO-8
t Option table
This EVM is designed to cover as many applications as possible. For some more specific applications, the circuit
can be simpler. The table below gives some recommendations.
11abl e 2 EVM A~PPIII cati on Recommen daf Ions
5V INPUT VOLTAGE
Change C1 to low profile capacitor
Sanyo 10TPB220M (220 I1F, 10 V)
Or 6TPB330M (330 I1F, 6.3 V)
Remove R12
c3-A OUTPUT CURRENT
Change Q1/Q2 and Q3IQ4 to dual pack MOSFET, IRF7311 to reduce the cost.
DIODE VERSION
Remove Q2 and Q4 to reduce the cost.
Table 3. Vendor and Source Information
MATERIAL
MOSFETS (Q1-Q4)
INPUT CAPACITORS (C1)
MAIN DIODES (D1 - 02)
INDUCTORS (L 1 - L2)
CERAMIC CAPACITORS
(C2, C3) (C12, C17, C21)
SOURCE
In EVM Design
Second Source
In EVM Design
PART NUMBER
Si4410DY (SILICONIX)
IRF7811 (Intematlonal Rectifier)
RV-35V221 MH1 G-R (ELNA)
Second Source
35CV330AXIGX (Sanyo)
UUR1V221MNR1GS (Nichicon)
MBRS340T3 (Motorola)
U3FWJ44N (Toshiba)
D03316P-682 (Collcraft)
CTD03316P-682 (Inductor Warehouse)
In EVM Design
Second Source
In EVM Design
Second Source
IN EVM Design
GMK325F106ZH
GMK316F225ZG
(Talyo Yuden)
Taiyo Yuden, Representative
~1ExAs
7-28
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
DISTRIBUTORS
Local Distributor
Bell Mlcroproducts
972-783-4191
870-833-5030
Future Electronics (Local Office)
Local Distributors
Local Distributors
972-248-3575
800-533-8295
SMEC
512-331-1877
e-mail: mike@millsales.com
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
Top Layer
Bottom Layer (Top View)
Top Assembly
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-29
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 " SEPTEMBER 1999
APPLICATION INFORMATION
NOTE: All wire pairs should be twisted.
Test Setup
~1EXAS
INSTRUMENTS
7-30
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
High current applications are described in table _The values are recommendations based on actual test circuits.
Many variations are possible based on the requirements of the user. Performance of teh circuit is dependent
upon the layout rather than the on specific components, if the device parameters are not exceeded. The power
stage, having the highest current levels and greatest dv/dt rates, should be given the most attention, as both
the supply and load can be severly affected by the power levels and edge rates.
Table 4. High Current Applications
REFERENCE
DESIGNATIONS
FUNCTION
8·AOUTPUT
2x ELNA
RV-35V221 MHl O-R
220I1F, 35 V
2x Taiyo Yuden
GMK325Fl06ZH
lOI1F,35V
12-AOUTPUT
3x ELNA
RV-35V221MH10-R
22OI1F,35V
3x Taiyo Yuden
GMK325Fl06ZH
lOI1F,35V
COiltronics UP4B-l R5
1.5I1H,13.4A
16-AOUTPUT
4xELNA
RV-35V221MH10-R
22OI1F,35V
4x Taiyo Yuden
GMK325Fl06ZH
lOI1F,35V
MicorMetals T68-8190
Corewm,#16
1.0 I1H, 25 A
4x Sanyo 4TPB470M
47011F, 4 V
Cl
Input Bulk Capacitor
C2(C3)
Input Bypass Capacitor
Ll (L2)
Output Filter Indicator
Coiltronics UP3B-2R2
2.2I1H,9.2A
C4(C22)
Output Filter Capacitor
2x Sanyo 4TPB470M
47011F,4V
3x Sanyo 4TPB470M
47011F,4V
C5 (C23)
Output Filter Capacitor
2x Sanyo 6TPB330M
330I1F,6.3V
4x Sanyo 6TPB330M
33OI1F,6.3V
01 (03)
Power Switch
2x Siliconix Si441 ODY
3OV,10A,13mO
3x Sanyo 6TPB330M
33OI1F,6.3V
3x Siliconix Si4410DY
30 V, lOA, 13mO
02(04)
Power Switch
2x Siliconix Si4410DY
30V,10A,13mO
3x Siliconix SI4410DY
30V,10A,13mO
4x Siliconix Si441 ODY
30 V, lOA, 13mO
R17(R20)
Rla (R19)
Switching Frequency
Gate Drive Resistor
Current Umit Resistor
70
10kO
200kHz
50
15kO
150 kHz
40
20kO
100 kHz
4x Siliconix Si4410DY
30 V, lOA, 13mO
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-31
7-32
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
• Step-Down DC-DC Converter
• Three Operation-Mode
- Heavy Load:
- Fixed Frequency PWM
- Hysteretic (User Selctable)
- Light Load:
- Skip Mode
• 4.5 V to 25 V Input Voltage Range
• Adjustable Output Voltage Down to 1.2 V
•
•
•
•
•
DB PACKAGE
(TOP VIEW)
SOFTSTART
95% Efficiency
Stand-By Control
Over Current Protection
UVLO for Internal 5 V Regulation
Low Standby Current •.. 0.5 mA Typical
1
LH
OUTGND
TRIP
vee_SENSE
vee
VREF5
VREG5V_IN
eOMP
PWMSKIP
STBY
=-40°C to 85°C
• TA
description
The TPSS1 03 is a synchronous buck dc/dc controller, designed for notebook PC system power. The controller
has three user-selectable operation modes available; hysteretic mode, fixed frequency PWM control, or SKIP
control.
In high current applications, where fast transient response is advantageous for reducing bulk capacitance, the
hysteretic mode is selected by connecting the Rt pin to VrefS. Selecting the PWM/SKIP modes for less
demanding transient applications is ideal for conserving notebook battery life under light load conditions. The
device includes high-side and low-side MOSFET drivers capable of driving low Rds (on) N-channel MOSFETs.
The user-selectable overcurrent protection (OCP) threshold is set by an external TRIP pin resister in order to
protect the system. The TPSS1 03 is configured so that a current sense resistor is not required, improving the
operating efficiency.
5Vo-~-------r~~
R1
, C1
r--i/I'::":""-+---'L....-.!.
U1
TPS5103
SOFTSTART
+---'VV'\r-~--..::2-1INV
R2
OUTU
---?- FB
........i.. CT
~_~5~RT
6
+--,,--::C"::"2-t--"::
7-1GNO
+-~/jt-==-+-----=8-1 REF
LH
J""-~~~2I
~19:......_",,,,~",,-'_+-..JI I
20
'T*"
01
1/
Q1 -
C3
":"
=
OUTPUT
L1
C5 :;;:oF:
t-1~8t::::='~
R3'==t::::r~~r,;::~:'1
Q2~
~1~6:......_wr_ _+-____~___~
LL
OUTOl-17
OUTGNO 15
R4
TRIP ~1':'=4'--,\M--+
VCCSENSE ~1':'::3'-----+
~--~9~COMP
VCC~2'-----+
+----t--.!:...iPWMISKIP
VREF5
-=:F"
-1!L STBY
VREG5V IN
~
~
Figure 1. Typical Design
A.
.a.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI is a trademark of Texas Instruments Incorgorated.
PRODUCT PREVIEW Information .o...ma products In tho Ionnatlve or
....Ign pha.. 01 _pmont. ChonIi:IerIlllc _
and oIhor
apeclllcatlo...redaalon goa... T.... lnstruments _ t h a rlght 10
change or dilcontlnuelhiio products wItfIoIII notlca.
~TEXAS
INSTRUMENTS
POST OFFICE sox 655303 • OALLAS, TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
7-33
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240-SEPTEMBER 1999
functional block diagram
-----------------------------~
SOFT START
FB
I
I
I
I
I
1
Soft Start
I
I
I
I
INV -t--I-+-t-I.~
I
I
~t---I---().L
>----j-
11 .185 V J,
I
I
I
_-r'"_
~~--~-;~>H----~
LH
OUT_u
'--~f-+-
LL
~__+-+-
OUT_d
'---+-+- OUTGND
PWMSKIP -t-----'
:..f-+--+-t- TRIP
Cr-i-------...------l
RT - ! - - - - - - + - - I
Comp
-+------'
J----+---4t---+_ VREFS
GNDTI
VCC~----------~
STBY
-t-----~-----__t
'-T----,......
I
REF
+L__
--'-'1.1""S""'S"'-V_______- - '
'----------+--AJ'I/v-t___________________________
_ VREGSV_IN
AVAILABLE OPTIONS
PACKAGE
TA
-40 DC to 8S DC
SSOP(DB)
EVM
TPS5103IDB
TPS5103EVM-136
TPS51031DBR
~lEXAS
7-34
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240-SEPTEMBER 1999
Terminal Functions
TERMINAL
NAME
NO.
1/0
COMP
8
I
CT
4
1/0
FB
3
0
GND
6
DESCRIPTION
Comparator input for voltage monitor
External capacitor from CT to GND for adjusting the triangle oscillator and decreasing the current limiting
voltage
Feedback output of error amp
ControlGND
INV
2
I
Inverting input of both error amp and hysteretic comparator
LH
20
1/0
Bootstrap. Connect 1 IIF low-ESR capacitor from LH to LL.
LL
18
1/0
Bootstrap low. High side gate driving return and output current protection. Connect to the junction of the high
side and low side FETs for floating drive configuration.
OUT_d
17
VO
OUTGND
16
OUT_u
19
0
Gate-drive output for high-side power sw~ching FETs
PWMSKIP
9
I
PWM/SKIP mode select
L:PWMmode
H:SKIPmode
Gate-drive output for low-side power switching FETs
Ground for FET drivers
REF
7
0
1.185-V reference voltage output
RT
5
1/0
External resistor connection for adjusting the triangle oscillator.
SOFTSTART
1
I
External capacitor from SOFTSTART to GND for soft start control
STBY
10
I
Standby control
TRIP
15
I
External resistor connection for output current control
VCC
13
I
Supply voltage input
VCC_SENSE
14
I
Supply voltage sense for current protection
VREF5
12
0
5-V-internal regulator output
VREG5V IN
11
I
External 5-V input (input voltage range = 4.5 V to 25 V)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
---- -
---- -------- - - - - -
7-35
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240-SEPTEMBER 1999
detailed description
REF
The reference voltage is used for the output voltage setting and the voltage protection(COMP). The tolerance
is 1.5% typically.
VREF5
An internal linear voltage regulator is used for the high-side driver bootstrap voltage. Since the input voltage
range is from 4.5 V to 25 V, this voltage offers a fixed voltage for the bootstrap voltage so that the design for
the bootstrap is much easier. The tolerance is 6%.
hysteretic comparator
The hysteretic comparator is used to regulate the output voltage of the synchronous-buck converter. The
hysteresis is set internally and is typically 9.7 mY. The total delay time from the comparator input to the driver
output is typically 400 ns for going both high and low.
error amplifier
The error amplifier is used to sense the output voltage of the synchronous buck converter. The negative input
of the error amplifier is connected to the Vref voltage(1.185 V) with a resistive divider network. The output of
the error amplifier is brought out to the FB terminal to be used for loop gain compensation.
low-side driver
The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The maximum drive voltage is 5 V
from VREF5. The current rating of driver is typically 1.2 A at sink current, -1.5 A at source current.
high-side driver
The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
1.2 A at sink current, -1.7 A at source current. When configured as a floating driver, the bias voltage to the driver
is developed from the VREF5, limiting the maximum drive voltage between OUT_u and LL to 5 V. The maximum
voltage that can be applied between LH and OUTGND is 30 V.
driver deadtime control
The deadtime control prevents shoot-through current from flowing through the main power FETs. During
switching transitions the deadtime control actively controls the turnon time of the MOSFET drivers. The typical
deadtime from the low-side-driver-off to the high-side-driver-on is 90 ns, and 110 ns from high-side-driver-off
to low-side-driver-on.
COMP
COMP is deSigned for use with a regulation output monitor. COMP also functions as an internal comparator
used for any voltage protection such as the input under voltage protection. If the input voltage is lower than the
setpoint, the comparator turns off and prevents external parts from damage. The investing terminal of the
comparator is internally connected to REF(1.185 V).
current protection
Current protection is achieved by senSing the high-side power MOSFET drain-to-source voltage drop during
on-time through VCC_SENSE and LL terminals. An external resistor between Yin and TRIP terminal with the
internal current source connected to the current comparator negative input adjusts the current limit. The typical
internal current source value is 1511A in PWM mode, 511A in SKIP mode. When the voltage on the positive
terminal is lower than the negative terminal, the current comparator turns on the trigger, and then activates the
oscillator. This oscillator repeatedly reset the trigger until the over current condition is removed. The capacitor
on the CT terminal can be open or added to adjust the reset frequency.
~TEXAS
7-36
INSTRUMENTS
POST OFFICE BOX 65S303 • DALlAS. TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 - SEPTEMBER 1999
detailed description (continued)
softstart
SOFTSTART sets the sequencing of the output for any possibility. The capacitor value for a start-up time can
be calculated by the following equation: C =2xT (uF) where C is the external capacitor value, T is the required
start-up time in (ms).
standby
This controller can be switched into standby mode by grounding the STBY terminal. When it is in standby mode,
the quiescent current is less than 1.0 uA.
UVLO
The under-voltage-Iock-out (ULVO) threshold is approximately 3.8 V. The typical hysteresis is 55 mY.
5-VSwitch
5-V Switch if the intemal 5-V switch senses a 5-V input from REG5V terminal, the intemal 5-V linear regulator
will be disconnected from the MOSFET drivers. The externalS V will be used for both the low-side driver and
the high-side bootstrap, thus increasing the efficiency.
PWM/SKIP switch
The PWM/SKIP switch selects the output operating mode. This controller has three operational modes, PWM,
SKIP, and Hysteretic. The PWM and SKIP mode control should be used for slower transient applications.
oscillator
The oscillator gives a triangle wave by connecting an external resistor to the RT terminal and an external
capacitor to the ~ terminal. The voltage amplitude is 0.43 V - 1.17 V. This wave is connected to the noninverting input of the PWM comparator.
Comparison Table Between PWM Mode and Hysteretic Mode
MODE
PWM
HYSTERETIC
Frequency
Fixed
Not Fixed
Transient Response
Normal
Very fast
Feed back compensation
Need
Needless
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-37
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 - SEPTEMBER 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ................................................... -0.3 V to 27 V
Input voltage, V" INV, CT, RT, PWM/SKIP, SOFTSTART, COMP .......................... -0.3 V to 7 V
Input voltage, VREG5V_IN .......................................................... -0.3 V to 6 V
Input voltage, STBY ............................................................... -0.3 V to 15 V
Input voltage, TRIP, VCC_SENSE ................................................... -0.3 V to 27 V
Output current, 10 .......................................................................... 3 A
Low level output voltage, VOL ...................................................... -0.3 V to 27 V
High level output voltage, VOH ...................................................... -0.3 V to 32 V
Reference voltage, Vref ............................................................. -0.3 V to 3 V
Operating free-air temperature range, TA ........................................... -40°C to 85°C
Operating virtual junction temperature range, TJ ............................................ -125°C
Storage temperature range, Tstg .................................................. -55°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other condRions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. See Dissipation Rating Table for free-air temperature range above 25°C.
DISSIPATION RATING TABLE
PACKAGE
TAS25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA=85°C
POWER RATING
DB
801 mW
6.408mWI"C
416mW
recommended operating conditions
MIN
VCC
Supply voltage
NOM
4.5
25
INV, CT, RT, COMP, PWM_SKIP, SOFTSTART
V,
Input voltage
Cr*
VREG5V_IN
5.5
STBY
12
f
TA
82
v
kO
Timing capacitor
100
pF
Frequency
200
kHz
Operating temperature range
-40
:I: Not a JEDEC symbol.
~TEXAS
7-38
v
25
Timing register
Oscillator frequency
UNIT
6
TRIP, VCC-SENCE
R,4
MAX
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
85
°c
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240-SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, Vee
(unless otherwise noted)
=7 V
reference voltage
PARAMETER
Vrel
Relerence Yoltage
TEST CONDITIONS
Ivrel = 50 IlA
TA = 25°C,
MIN
TYP
MAX
1.167
1.185
1.203
1.155
lYre! = 50 1lA*
Regin
Line regulation t
VCC=4.5 Vt025 V,
Regl
Load regulation t
1= 11lAt01 mA
1=501lA
1.215
UNIT
V
0.2
12
mV
0.5
10
mV
TYP
MAX
UNIT
500
kHz
t Not a JEDEC symbol.
oscillator
PARAMETER
1
Frequency
AT
liming resistor
Idv
fdt
TEST CONDITIONS
MIN
PWMmode
47
: Frequency change T
VHL'"
High-level output voltage
VLL'"
Low-level output voltage
k.Q
0.1%
VCC = 4.5 V to 25 V
2%
TA = -40°C to 85°C
DC includes internal comparator error
1
DC includes internal comparator error
1.1
1.2
1.17
1= 200 kHz, includes internal comparator error
0.4
0.5
0.6
0.43
1= 200 kHz, includes intemal comparator error
V
V
t Not a JEDEC symbol.
* The output voltages 01 oscillator (I = 200 kHz) are ensured by design.
error amp
PARAMETER
V
Input offset voHage
Av
Open-loop voltage gaint
GB
Unity-gain bandwidth t
TEST CONDITIONS
MIN
TA=25°C
TYP
MAX
2
10
50
10
Output sink current
VO=0.4V
IS
Output source current
VO=1V
30
UNIT
mV
dB
0.8
MHz
45
IlA
IlA
300
t Not a JEDEC symbol.
hysteresis comparator§
PARAMETER
TEST CONDITIONS
Vhsy
Hysteresis window
Vp-VS
Offset voltage
I
Bias current
tPHL
Propagation delay Irom INV to OUT_U
tpLH
Hysteretic mode
MIN
TYP
MAX
6
9.7
13
UNIT
mV
2
mV
10
pA
TTL input signal
230
ns
10 mV overdrive on hysteresis band signal
400
ns
§ The numbers In the table Include the dnver delay. All numbers are ensured by deSign.
control
PARAMETER
VIHA
High-level input voltage
VILA
Low-level input voltage
TEST CONDITIONS
STBY
PWM SKIP
MIN
TYP
MAX
2.5
UNIT
V
2
STBY
0.5
PWM_SKIP
0.5
V
~lExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-39
TPS5103
MULTIPLE· MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240-SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, Vee = 7 V
(unless otherwise noted) (continued)
S-Y regulator
PARAMETER
t
TEST CONDITIONS
Vo
Output voltage
1=10mA
Regln
Line regulation t
VCC =5.5 Vto25 V,
1=10mA
Regl
Load regulation t
1=1 rnA to lOrnA,
VCC=5.5V
Short-circuH output current
lOS
Not a JEDEC symbol.
MIN
TYP
4.7
MAX
V
20
mV
40
mV
70
Vref=OV
UNIT
5.3
rnA
S-Y switch
PARAMETER
VIT(high)
VlTClowl
Vhsy
t
TEST CONDITIONS
I Threshold voltageT
I
Hysteresis)
MIN
TYP
MAX
4.2
4.9
4.1
4.8
UNIT
V
50
150
250
mV
MIN
TYP
MAX
UNIT
Not a JEDEC symbol.
UYLO
PARAMETER
VI~;~lgv~)
VITlow
Vhvs
t
TEST CONDITIONS
: Threshold voltageT
Hysteresis
3.6
4.2
3.5
4.1
10
150
V
mV
Not a JEDEC symbol.
output
PARAMETER
TEST CONDITIONS
MAX
MIN
TYP
10
OUT_u sink curent
VO=3V
0.5
1.2
IS
OUT_u source current
VO=2V
-1
-1.7
A
10
OUT_d sink current
VO=3V
0.5
1.2
A
IS
OUT_d source current
VO=2V
I
TRIP terminal current
UNIT
A
-1
-1.5
PWMmode,
VTRIP=7V
10
15
20
SKIP mode,
VTRIP=7V
3
5
7
A
iJA
High side driver is GND referenced.
Input: INV = 0 - 3V
tr
Rise time
t,ltf= 10 ns,
Frequency = 200 kHz
ns
CL=22oopF
28
CL=3300pF
39
High side driver Is GND referenced.
Input: INV=0-3V
tf
FallHme
t,ltf= 10 ns,
Frequency = 200 kHz
30
CL =3300 pF
3B
~TEXAS
7-40
ns
CL=2200pF
INSTRUMENTS
POST OFAce BOX 665303 • DALLAS, TexAS 7526&
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SlVS240-SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, VCC
(unless otherwise noted) (continued)
=7 V
softstart
PARAMETER
VlTlhiahl
VIT(low)
TEST eONDmONS
Softstart current
leCTRl)
MIN
TYP
MAX
1.9
2.5
3
I
3.9
I Threshold voltage (SKIP mode)t
UNIT
IJA
V
2.6
t Not a JEOEC symbol.
output voltage monitor
PARAMETER
TEST CONDITIONS
Threshold voltage
MIN
TYP
MAX
1.08
1.18
1.28
MIN
TYP
MAX
driver deadtlme section
PARAMETER
TEST CONDITIONS
UNIT
TORVlH
Low-side to high-side
90
ns
TORVHl
High-side to low-side
110
ns
whole device
PARAMETER
ICC
Supply current
I
Shu1down current
TEST CONDITIONS
STBY=OV
SOFTSTART
INV
LL
OUT_d
RT
OUTGND
GND
TRIP
REF
VeC_SENSE
STBY
MAX
0.5
1.2
UNIT
mA
0.Q1
10
IJA
OUT_u
CT
PWMSKIP
TYP
LH
FB
COMP
MIN
VCC
VREF5
5V_IN
Figure 2_ Test Circuit
-!11
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
7-41
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240-SEPTEMBER 1999
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT
QUIESCENT CURRENT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
700
50
650
,
45
VCC=7V
---
::l.
I
i> / '
V ,...,.. ~~
~~
VCC=4.5V
~V
C
35
::I
30
~
j...--l-
0
C
VCCI=7~
I J
25
§
f----
VrC=r~~
40
CC
I VCC=25i./ 10-"1""'
~
15
~
9
11
5
25
r
0
125
85
TJ - Junction Temperature - °C
-40
-20
I
~
'S
,e.
4.5
::I
0
i
4
I-.
::II
...
::)
0
>-
vs
DRIVE CURRENT
3
I
VCC=7V,
TJ = 25°C
VCC=7V,
TJ = 25°C
>
5
~
I
'" "
2.5
&
~
2
;-
1.5
~
'S
~
0
~
~
I-.
::II
...
::)
0
>'
3
0.5
0
0.7
V
0.1
I(OUT_source) - Drive Source Current - A
Figure 5
V
L
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
0.7
I(OUT_slnk) - Drive Source Current - A
Figure 6
~TEXAS
7-42
./
CD
3.5
0.1
125
DRIVE OUTPUT VOLTAGE
vs
DRIVE CURRENT
&
85
Figure 4
DRIVE OUTPUT VOLTAGE
>
25
TJ - Junction Temperature - °C
Figure 3
5.5
'If
J
10
300
-20
J
20
0
I
350
-40
11
-
VdC=4.5V'-
I--
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240
SEPTEMBER 1999
TYPICAL CHARACTERISTICS
DRIVE OUTPUT VOLTAGE
DRIVE OUTPUT VOLTAGE
vs
DRIVE CURRENT
DRIVE CURRENT
vs
4.5
6
TJ = 25°C
TJ = 25°C
>
5
I
~
G)
I
~
4
'S
CL
'S
0
~I-..
:1
3
4
>
I
G)
I
"
~
3.5
~
3
t
2.5
g!
2
'S
~
0
"C
Q
I-..
2
"01
./
1.5
!:i
:::I
0
0
->
->
/'
0.5
/"
0
0
0.1
0.1
0.7
Figure 7
FigureS
OSCILLATOR OUTPUT VOLTAGE
OSCILLATOR OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
vs
500
1.125
>
>
I
I
G)
1.115
al
~
~
.
./
1.105
./
c5
!II
->
'S
CL
'S
0
/'
i 1.095
=
~
!cu
495
~
~
i
0.7
I(OUT_slnk) - Drive Source Current - A
I(OUT_source) - Drive Source Current - A
IlL
V
g
490
"'
.!!
1i
VCC = 4.5 V,
VCC=7V,
VCC=25V
c5
Ja
!II
1.085
\
VCC =4.5 V,
VCC=7V,
VCC=25V
485
->
480
1.075
-40
-20
25
85
125
-40
TJ - Junction Temperature - °C
Figure 9
25
85
125
-20
TJ - Junction Temperature - °C
Figure 10
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-43
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240-SEPTEMBER 1999
TYPICAL CHARACTERISTICS
ERROR AMPLIFIER INPUT OFFSET VOLTAGE
ERROR AMPLIFIER OUTPUT VOLTAGE
va
va
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.5
- --b "-
2.5
.........
2
hI "-
Vcc = 4.5 V,
I-- VCC=7V,
1.5
Vee=25V
II
"
r-.
-
_
-
........
Vee = 4.5 V,
Vee=7V,
Vee=25V
,
i'--
"
0.5
o
o
-20
25
125
85
TJ - Junction Temperature '- ·e
-40
25
85
-20
TJ - Junction Temperature -
Figure 12
Figure 11
HYSTERESIS COMPARATOR HYSTERESIS VOLTAGE
ERROR AMPLIFIER OUTPUT VOLTAGE
va
va
JUNCTION TEMPERATURE
>
E
I
&
1!
~
!
~
~
6
f
0
5.4
.!l
:I:
5.2
"15.
.~
~
5
w
4.8
I~
>0
/
Vee = 4.5 V,
Vee=7V,
Vee = 25 V
5.6
JUNCTION TEMPERATURE
>
6.2
5.8
~
I
10.5
I
10.25
1
i
1
1/
L
Vee=7V
.........
10
9.75
'r-...
""",-
8
--
I"- ........
4.6
4.4
-40
-20
25
85
TJ - Junction Temperature -
125
-40
·e
-20
25
85
TJ - Junction Temperature -
Figure 14
Figure 13
~TEXAS
7-44
125
·e
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
125
·e
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240-SEPTEMBER 1999
TYPICAL CHARACTERISTICS
STANDBY SWITCH THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
VREF5 OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
>
5.2
t
5.1
I I I
I
~
>
5
I
t
4.9
I
~
J
5
i
III
f
~
TJ = 125°C
4.8
4.7
4.6
0.51--t-----1I--+---+-+---+--+
=;-
4. 5
~
4. 4
4. 3
0L--~L5~~_~2-5~-2~5-~-9~5--~1~3~5~
4. 2
o
10
20
Vee - Supply Voltage - V
TJ - Junction Temperature - °e
Figure 15
Figure 16
VREF5 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
6
VREF5 SHORT CURRENT
vs
JUNCTION TEMPERATURE
-100
J I II
TJ = 125°C
5
.....
TJ=~~
I
t
4
,
~
~
"S
~
If
w
3
II:
I
~
-80
~
I
j
&
If
TJ=~ooe
w
2
J
Vee=25V
-60
1:
0
>
~ 25°C
II:
>"
-£
>"
>
I
\
TJ
~
i!:
t--
TJ=-40°e
...- '"
~
~
Vee = 4.5 V
V r-.... .........
~
"\
~ ~ ~ 1\
~ee=7V
~o
'"~
g:
I
~
~
\
\
0
o
-10
-20 -30 -40 -50 -60
10 - Output Current - mA
-70
-20
o
Figure 17
-20
25
85
TJ - Junction Temperature - °e
125
Figure 18
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
7~5
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240-SEPTEMBER 1999
TYPICAL CHARACTERISTICS
UVLO HYSTERESIS VOLTAGE
UVLO THRESHOLD VOLTAGE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
80
4
>
..
I
J
:§!
i
~
I!
...0
I-
>
:::)
I
3.95
VTLH
3.90
3.85
,..,..
3.80
::c
...I
~
..r
::c 3.75
~
........
"....,
V
-
/
V
/'
1/
V
/
io"'"
v
~
70
J
60
I
"....,
V
:§!
OJ
~
/VTHL
t
40
9>
30
~
>I!
20
::c
:::)
>
/'
50
,..,.. V
-40
-40
125
25
85
-20
TJ - Junction Temperature - °C
5 VSW HYSTERESIS VOLTAGE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
4.80
4.75
J
;g
4.70
:2
,g
4.65
~
F=
4.60
~
...::c
T T
VTLH . /
-
4.50
~ 4.45
..r
::c
~ 4.40
200
-
~
,/
>
E
I
160
../" V'
CI
140
.!!
120
i
100
>
60
:§!
""
."".
~
f.--
~
iE
II)
~
I!
>
80
40
20
0
4.35
-45
-25
25
95
TJ - Junction Temperature - °C
135
-45
Figure 21
-25
25
95
TJ - Junction Temperature - °C
Figure 22
~1ExAs
7-46
-
,..,..
180
II
-;7
...-
II)
I
."".
VTHL
4.55
-20
25
85
125
TJ - Junction Temperature - °C
Figure 20
5 VSW THRESHOLD VOLTAGE
I
V
10
Figure 19
II
V
~
0
3.70
>
v
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
135
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 - SEPTEMBER 1999
TYPICAL CHARACTERISTICS
SOFTSTART THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
SOFTSTART CURRENT
vs
JUNCTION TEMPERATURE
4.5
-2.45
>
4
t
3.5
-
I
c -2.40
::I.
I
!
o
::I
-2.35
vee=r~
1:
~~
-2.30
I
....I
I!:
E
~
.A ~
p
~
§!
I
~
~
Vee=7V
I:s
~
~~
3
2.5 I-2
1.5
I
Vee=25V
-2.25
~
0.5
o
-2.20
-40
25
-20
Vee = 4.5 V -
Vee=7V,
Vee=25V
-40
125
85
°e
TJ - Junction Temperature -
-20
25
85
TJ - Junction Temperature -
Figure 23
125
°e
Figure 24
OUTPUT VOLTAGE MONITOR COMPARATOR
THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
SOFTSTART THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
3.5
1.195
>
I
CD
01
1.193
3
~
i/V
§!
:s!
0
.c
2.5 I-- -
m
~
1:
~
-
0
I
....I
/'
V"""'"
2
II)
:z:
~
Vee=7V,
Vee = 25 V
1.5
-40
V
./
/
.."....
,..,
V
......... ~ee=4.5V
1.190
1.188
........
........ ........
........ ~f
-
1.185
Vee=4.5V, Vee=7V,
Vee=25V
1.183
-20
25
125
85
TJ - Junction Temperature -
1.180
°e
-40
-20
25
Figure 25
125
85
TJ - Junction Temperature -
°e
Figure 26
~TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS. TEXAS 75265
7-47
TPS51 03
MULTIPLE MODE SYNCHRONOUS DCfDC CONTROLLER
SLVS240 - SEPTEMBER 1999
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
OSCILLATOR OUTPUT VOLTAGE
va
va
JUNCTION TEMPERATURE
FREQUENCY
600
~
1.6
TI
500
I
t'
c
400
-...... f"oo,.,F'=5JkHJ
r--
...........
VCC=4.5V,
VCC=7V,
VCC=25V
1.4
j"-....
I
VOSCH
1.2
.... ""
II
:::I
~
II.
I
~
'u..
~
VCC = 4.5 V,
VCC=7V,
VCC=25V
300
.L
200
t--
0.8
0.6
F= 200 kHz
0.4
~
0.2
>
-40
85
-20
25
TJ - JUnction Temperature -
VOSCl
~
>.
100
o
-
!..J
r-
125
r-r--
o
10
100
°c
FOSC - Frequency - kHz
Figure 28
Figure 27
ERROR AMPLIFIER GAIN AND PHASE SHIFT
140
40 t--FFl:ttItlfl'..~,•..;~.ate It---+-t-+tl-tlll---+-t+HtH
30 Hf-H-ttltlt-I.....::!
.....J..1'ort-,-ffI?lI'--o;;l=HfttHlt-t-HHtItI
d-1
100
R
20 t--t--t-tt-Httt
j
10
'G~
,60
Hf-Htttltt-t-t-ttttttlr'\H~Htttt-+I\"t-HttH 20
r'\
-10 1-+-t+t1ftt1t--+-H++tIIIt-+l-+tHtft-f'l-l-ttIH
f - Frequency - Hz
Figure 29
~1ExAs
7-48
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
-20
I
1000
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 - SEPTEMBER 1999
TYPICAL CHARACTERISTICS
MAXIMUM DUTY CYCLE
SOFTSTART CAPACITANCE
vs
vs
JUNCTION TEMPERATURE
SOFTSTART TIME
100
104
f'=2JkHJ -
99.5
IL
a.
99
I
98.5
!
98
:::I
Q
97.5
E
:::I
E
97
~
..
'R
::IE
1/
I
";/.
f!c
.!
-
96.5
103
l~
/
1:
.!
~
102
I
til
til
96
0
V
95.5
95
-40
100
-20
25
125
85
TJ - Junction Temperature - °C
10
0.1
TSS - Soft Start TIme - ms
0.01
Figure 31
Figure 30
DRIVER DEAD TIME
CURRENT PROTECTION SOURCE CURRENT
vs
vs
JUNCTION TEMPERATURE
140
II
C
I
I I
TDRVHL
I.
I _I
VCC=4.5V
120
1=
"..
100
I!
~.!..
:z:
~
:z:
..J
~
Q
I-
TDRVLH
VCC=7V,
60 f- VCC=25V
Q
1-.
- -i ' -- ,.
b:::;::
f"'"'!
80
40
INPUT VOLTAGE PWM MODE
-
-
CD
E
14.5
CC
cr
VCC =4.5V
I
VCC=7V,
VCC=25V
14.25
~
G
~
~
I
TA=12~
14
13.75
I
1
I
TA=25°C
13 5
•
_ 13.25
j
20
o
100
-'
I
TA=-40°C
13
.!t.
-
ii: 12.75
.!:"
25
-25
95
TJ - Junction Temperature - °C
135
12.5
4.5
7
25
VTRIP - Input Voltage - V
Figure 32
Figure 33
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
7-49
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240-SEPTEMBER 1999
TYPICAL CHARACTERISTICS
CURRENT PROTECTION SOURCE CURRENT
vs
INPUT VOLTAGE SKIP MODE
4.6
CC
T
'E
4.5
~
4.4
~
::I
Ttl250
~
TA = 25°C _ _
C
0
'fi
4.3
'E
~
4.2
.!a.
ii:
1:'
4.1
£
8
d--
-----
TA=-40°C
4
4.5
25
7
VTRIP -Input Voltage - V
Figure 34
OSCILLATOR FREQUENCY
vs
RESISTOR
700
...
::I:!
I
CTI=l~JFII
:"
600
,\\VbTU5~J
~
c
500
W
400 -
u..
.\\~
CT=22pF
til
::I
I I I
1\\~
\ l\ ~ \
Cr=33pF
15
]i
~
b
300
200
Cr = 470 pF
}
II
.~
100
o
10
"CT= 680 pF
~ \1'i'
~
100
RT - Resistor - kO
Figure 35
~TEXAS
7-50
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1000
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240-SEPTEMBER 1999
APPLICATION INFORMATION
overshoot of output rectangle wave
The drivers in the TPS51 03 controller are fast and can produce high transients on Vee or the junction of 01 and
02(shown below). Care must be taken to insure that these transients do not exceed the absolute maximum
rating for the device or associated external component. A low-ESR capacitor connected directly from 01 drain
to 02 source can greatly reduce transient pulses on Vee. Also, 01 turn-on-speed can be reduced by adding
a resistor (5 - 15 0) in series with OUT_u. Poor layout of the switching node (V1 in figure) can result in the
requirement for additional snubber circuitry require from V1 to ground.
T
Vee
Q1
V1
Q2
T
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-51
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240-SEPTEMBER 1999
APPLICATION INFORMATION
application for general power
The design shown in this data sheet is a reference design for a general power supply application. An evaluation
module (EVM). TPS5103EVM-136 (SLVP136), is available for customer testing and evaluation. The intent is
to allow a customer to fully evaluate the given design using the plug-in EVM supply shown here. For subsequent
customer board revisions, the EVM design can be copied onto the users PCB to shorten design cycle time,
component count, and board cost.
To help the customers to design the power supply using TPS51 03, some key design procedures are shown
below.
R2
r-CC~15jr~---r~~tj--~~----------~====~~~==;=====~~vl
VI
C5
~-----t1"""t'"'< Input GND
InputGND
InputGND
Vo
Va
R6
Vo
..........~I_f_--4-~___._<
ouroNDI-'-'----+-------.,~+_-----4--t-4
VoGND
R6I\
VoGND
R7
-:- ........_--;---IJ-TP
:.:..;9"--''iOOMP
~----------+--O~~~
TP10
STBY
R13 -:-
JPl
Figure 36. EVM Schematic
~1ExAs
7-52
voGND
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240-SEPTEMBER 1999
APPLICATION INFORMATION
output voltage setpoint calculation
The output voltage is set by the reference voltage and the voltage divider. In TPS51 02, the reference voltage
is 1.185 V, and the divider is composed of two resistors in the EVM design that are R4 and R5, or R14 and R15.
The equation for the setpoint is:
R2 = R1 x Vr
Vo - Vr
Where R1 is the top resistor (kO) like R4 or R15; R2 is the bottom resistor (kO) such as R5 or R14; Vo is the
required output voltage (V); Vr is the reference voltage (1.185 V in TPS51 03).
Example: R1 = 1 kO; Vr = 1.185 V; Vo = 1.8 V, then R2 = 1.9 kO.
For your convenience, some of the most popular output voltage setpoints are calculated in the table below:
Vo
1.3V
1.5V
1.BV
2.5V
3.3V
R1 (top) (kn)
1
1
1
1
1
1
R2 (bottom) (kn)
10
3.7
1.9
0.9
0.56
0.31
5.0V
If higher precision resistor is used, the output voltage setpoint can be more accurate.
In some applications, the output voltage is required to be lower than the reference voltage. With few extra
components, the lower voltage can be easily achieved. The drawing below shows the method.
vee
Vo
R(top)
Rz1
Rz2
INV
,A
Zener
~~
TPS5103
R(bottom)
~
In the schematic, the Rz1, Rz1, and the zener are the extra components. Rz1 is used to give zener enough
current to build up the zener voltage. The zener voltage is added to INV through Rz2. Therefore, the voltage
on INV is still equal to the Ie internal voltage (1.185 V) even if the output voltage is regulated at lower setpoint.
The equation for setting up the output voltage is shown below:
Rz2
=
(Vz-Vr)
(Vr-Vo)
Vr
-Rtop
- - +Rbtm
--
Where Rz2 is the adjusting resistor for low output voltage; Vz is the zener voltage; Vr is the internal reference
voltage; Rtop is the top resistor of voltage sensing network; Rbtm is the bottom resistor of the sensing network;
Vo is the required output voltage setpoint.
Example: Assuming the required output voltage setpoint is Vo = 0.8 V, Vz = 5 V; Rtop = 1 kO; Rbottom = 1 kO,
then the Rz2 = 2.43 kO.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-53
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240-SEPTEMBER 1999
APPLICATION INFORMATION
switching frequency
With hysteretic control, the switching frequency is a function of the input voltage, the output voltage, the
hysteresis window, the delay of the hysteresis comparator and the driver, the output inductance, the resistance
in the output inductor, the output capacitance, the ESR and ESL in the output capacitor, the output current, and
the tumon resistance of high side and low side MOSFET. It is a very complex equation if everything is included.
To make it more useful to the deSigners, a simplified equation only considers the most influential factors. The
tolerance of this equation is about 30%:
V out x (V ln - V out) x (ESR - (10 x 10- 7
+ Td)/C out)
fs-~--~~~~~~~~~~~~~=-~--~~--~
- Yin x (V in x ESR x (10 x 10 7
+ Td) + 0.0097
x Lout - ESL x Yin)
Where fs is the switching frequency (Hz); Vout is the output voltage (V); Vin is the input voltage (V); Coutis the
output capacitance; ESR is the equivalent series resistance in the output capacitor (il); ESL is the equivalent
series inductance in the output capacitor (H); Lout is the output inductance (H); Tdis output feedback RC filter
time constant (S).
In the EVM module deSign, for the 1.8 V output, for example: Yin
40 mil; ESL 3 nH; Lout 61lH; TO 0.5115.
=
=
=
=5 V, Vout =1.8 V, Cout =680 IlF; ESR =
Then, the frequency fs = 122 kHz.
output inductor ripple current
The output inductor current ripple can affect not only the efficiency and the inductor saturation, but also the
output voltage capacitor selection. The equation is exhibited as below:
I ·
I
"ppe
=
Vin - Vout - lout x (Rdson
Lout
+
RL)
x
D
x
T:
s
Where lripple is the peak-to-peak ripple current (A) through inductor; Vin is the input voltage (V); Vout is
the output voltage (V); lout is the output current; Rdson is the on-time resistance of MOSFET (il); D is the duty
cycle; and Ts is the switching cycle (S). From the equation, it can be seen that the current ripple can be adjusted
by changing the output inductor value.
=5 V; Vout =1.8 V; lout =5 A; Rdson =10 mil; RL =5 mil; D =0.36; Ts =10 IlS; Lout =6 IlH
Then, the ripple Iripple =2 A.
Example: Yin
output capacitor RMS current
Assuming the inductor ripple current totally goes through the output capacitor to the ground, the RMS current
in the output capacitor can be calculated as:
I (rms) =
o
.M.
ff2
Where I(orms) is the maximum RMS current in the output capacitor (A); III is the peak-to-peak inductor ripple
current (A).
Example: III = 2 A, so lo(rms) = 0.58 A
~TEXAS
7-54
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240-SEPTEMBER 1999
APPLICATION INFORMATION
input capacitor RMS current
Assuming the input ripple current totally goes into the input capacitor to the power ground, the RMS current in
the input capacitor can be calculated as:
li(rms)
= /102 x
D x (1 - D)
+
11 x D x Iripple2
Where U(rms) is the input RMS current in the input capacitor (A); 10 is the output current (A); Dis the duty cycle.
From the equation, it can be seen that the highest input RMS current usually occurs at the lowest input voltage,
so it is the worst case design for input capacitor ripple current.
Example: 10 = 5 A; D = 0.36
Then, Ii(rms)= 3.36 A
softstart
The softstart timing can be adjusted by selecting the soft-start capacitor value. The equation is
C soft
=2
x T soft
Where Csoft is the softstart capacitance (JlF); Tsoft is the start-up time on softstart terminal (S).
Example: Tsoft = 5 mS, so Csoft = 0.01 JlF.
current protection
The current protection in TPS51 03 is set using an internal current source and an external resistor to set up the
current limit. The sensed high side MOSFET drain-to-source voltage drop is compared to the set point, if the
voltage drop exceeds the limit, the internal oscillator is activated, and it continuously resets the current limit until
the over-current condition is removed. The equation below should be used for calculating the external resistor
value for current protection:
PWM or HYS mode
R I
c
= Rds(on)
x (Itrip + Iind(p-p)j2)
0.000015
SKIP mode
R I
c
= Rds(on)
x (Itrip + Iind(p-p)j2)
0.000005
Where Rcl is the external current limit resistor (R10,R11); Rds(on) is the high side MOSFET on-time resistance.
Itrip is the required current limit; lind(p-p) is the peak-to-peak output inductor current.
Example: PWM mode or HYS mode
Rds(on) = 10 mO, Itrip =5 A, lind = 2 A, so Rcl = 4 kQ
Example: SKIP mode
Rds(on) = 10 mO, Itrip = 2 A, lind = 1 A, so Rcl = 5 kQ
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-55
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 - SEPTEMBER 1999
APPLICATION INFORMATION
loop gain compensation
Voltage mode control is used in this controller for the output voltage regulation. To achieve fast, stabilized
control, two parts are discussed in this section: the power stage small signal modeling and the compensation
circuit design.
For the buck converter, the small signal modeling circuit is shown below:
r--------.,
a
I ~d
I
I Die
ZL
r------,
--;+
I
RL
L
I
r-41~~~~r_~YL~~_.
L ______ .J
I
I
I
I
1"-"
I c
I
c
_.J
p
Vo
ZRC
I
I RC
R
I
I
I
L_.J
From this equivalent circuit, several control transfer functions can be derived: input-to-output, output
impedance, and control-to-output. Typically the control-to-output transfer function is used for the feedback
control design.
Assuming Rc and RL are much smaller than R, the simplified small signal control-to-output transfer function is:
A
Vod
a
=
(1 + sCRc)
1+S[CX(RC+Rd·+~]+s2LC
Where C is the output capacitance; Rc is the equivalent serial resistance (ESR) in the output capacitor; L is the
output inductor; RL is the equivalent serial resistance (ESR) in the output inductor; R is the load resistance.
To achieve the fast transient response and the better output voltage regulation, a compensation circuit is added
to improve the feedback control. The whole system is shown below:
Vref
~TEXAS
7-56
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 752115
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 - SEPTEMBER 1999
APPLICATION INFORMATION
The typical compensation circuit used as an option in the EVM design is a part of the output feedback circuit.
The circuitry is displayed below.
C1
>---......-
To PWM
This circuit is composed of one integrator, two poles, and two zeros:
Assuming R1 « R2 and C2 « C3, the equation is:
(1
Comp
+ sC3R4)
x (1
+ sC2R2)
= sC3R2(1 + sC2R4)(1 + sC1 R1)
Therefore,
Pole1
= 2:Jt61 R1
Zer02 = 2:Jtc1R4
Pole2 =
2;c;C~R4
1
Zer01 -- 2;c;C2R2
Integrator = 2:Jtf63R2
A simplified version used in the EVM design is exhibited below.
Vo
R2
R3
Assuming C2 « C3, the equation is:
(1 + sC3R4)
Comp = sC3R2(1 + sC2R4)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-57
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 - SEPTEMBER 1999
APPLICATION INFORMATION
there is one pole, one zero and one integrator:
Pole
= 2:n:c1R4
Integrator = 2:n:f63R2
The loop-gain concept is used to design a stable and fast feedback control. The loop-gain equation is derived
by that the control-to-output transfer function times the compensation:
Loop - gain
= Vod
X
Comp
By using a bode plot, the amplitude and the phase of this equation can be drawn with software such as MathCad.
In turn, the stability can be easily designed by adjusting the compensation perimeters. The sample bode plot
is shown below to explain the phase margin, gain margin and the crossover frequency.
The gain is drawn as 20 log (loop-gain), and the phase is in degrees. To explain them clearer, 180 degrees is
added to the phase, so that the gain and phase share the same zero.
Where the gain curve touches the zero is the crossover frequency. The higher this frequency is, the faster the
transient response is, since the transient recovery time is 1/(crossover frequency). The phase to the zero is the
phase margin at the crossover frequency. The phase margin should be at least 60 degrees to cover all the
condition changes such as temperature. The gain margin is the gap between gain curve and the zero when the
phase curve touches the zero. This margin should be at least 20 dB to guarantee the stability over all conditions.
180
166
II
II
152
Phase
138
II
~
124
110
96
82
68 I-20 Log (Loop-Gain)
180 + Phasa
54
-
10Phase
Margin
40
26
12
-2
-30 -
-16
Gain
-
~
Crossover
-44
--58
r.....
-as
Gain
Margin
111111
·IIIIN
111111
104
100
f - Frequency - Hz
~TEXAS
7-58
I
rHoJ.ll
1111
1111
11111
-72
-100
10
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 - SEPTEMBER 1999
APPLICATION INFORMATION
synchronization
Some applications require switching clock synchronization. Two methods are used for synchronization:
•
Triangle wave synchronization
740mV
----+
•
___
C-=-!t TPS5103
Square wave synchronization
It can be seen that RT and CT are removed from the circuit. Therefore, two components are saved. This method
is good for the synchronization between two controllers. If the controller needs to be synchronized with digital
circuit such as DSP, usually the square-type clock signal is used. The configuration exhibited below is for this
type of application:
lIm-.
----+
1M\
Ct
-.l
~-..&
TPS5103
An external resistor is added into the circuit, but RT is still removed. CT is kept to be a part of RC circuit generating
triangle waveform for the controller. Assuming the peak value of the square is known, the resistor and the
capacitor can be adjusted to achieve the correct peak-to-peak value and the offset value.
layout guidelines
Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult
than most general PCB designs. The general design should proceed from the switching node to the output, then
back to the driver section and, finally, place the low-level components. Below are several specific points to
consider before layout of a TPSS103 design begins.
•
All sensitive analog components should be referenced to ANAGND. These include components connected
to VrefS, Vref, INV, LH, and COMP .
•
Analog ground and drive ground should be isolated as much as possible. Ideally, analog ground will connect
to the ground side of the bulk storage capacitors on Va, and drive ground will connect to the main ground
plane close to the source of the low-side FET.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-59
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240-SEPTEMBER 1999
APPLICATION INFORMATION
•
Connections from the drivers to the gate of the power FETs should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
•
The bypass capacitor for Vee should be placed close to the TPS51 03.
•
When configuring the high-side driver as a floating driver, the connection from LL to the power FETs should
be as short and as wide as possible.
•
When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from LH to
LL) should be placed close to the TPS51 03.
•
When configuring the high-side driver as a ground-referenced driver, LL should be connected to DRVGND.
•
The bulk storage capacitors across VIN should be placed close to the power FETS. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
•
High-frequency bypass capacitors should be placed across the bulk storage capacitors on
•
LH and LL should be connected very close to the drain and source, respectively, of the high-side FET. LH
and LL should be routed very close to each other to minimize differential-mode noise coupling to these
traces. Ceramic decoupling capacitors should be placed close to where Vee connects to Vin, to reduce
high-frequency noise coupling on Vee.
•
The output voltage sensing trace should be isolated by either ground trace or Vee trace.
test results
The tests are conducted at TA =25°C, the point voltage is 5 V.
~1EXAS
7-60
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Vo.
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240-SEPTEMBER 1999
APPLICATION INFORMATION
EFFICIENCY
EFFICIENCY
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
95
95
1.8 V Output Efficiency
l
90
II
#.
r;
.!
80
75
85
PWMMode
L~
#.
I
80
r;
I
75
j
70
I
I
V
I
o
60
0.5
1.5
2
2.5
3
3.5
4
o
0.1
SKIP Mode
-
0.2
0.3
0.4
0.5
10 - Output Current - A
10 - Output Current - A
Figure 37
Figure 38
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
INPUT VOLTAGE
OUTPUT CURRENT
1.790,..---..,.-1----,1,..--.....,...--........----.
1.8 V Line Regulation
1.790
JI
1.7851----i---+---+----I-----I
I
>
I
j
j
~
"5 1.7801---.t---+---t----I----j
g
i
'"'
1.780
~
I
I
o
>' 1.7751----i---+---+----I-----I
I
I
I
1.8 V Output Load Regulation
1.790
>
V
-
14
65
65
V
V--'~~
c
"'- SKIP Mode
70
60
--,
90
..,
c
m
r----..
~ !'~M~e
85
I
-'
_II
1.8 V Output Efficiency
J'
1.780
""
......
.......
I'...... ..............
............
1.770
~
............
1.770
1.770'-_---'_ _---'-_ _......_ _...1-_---1
o
5
10
15
20
25
1.760
o
0.5
VI -Input Voltage - V
1.5
2
2.5
3
3.5
4
10 - Output Current - A
Figure 39
Figure 40
~lEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
7-61
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 - SEPTEMBER 1999
EFFICIENCY
OUTPUTNOLTAGE
vs
OUTPUT CURRENT
· .... r
1.8 V Output Diode TYpe Efficiency
.
.
.
· 50 mVlulv·
~
·:····:····:····:···t· .: .. 10::; O.S A ..
90
· . . . !
- r-
85
~
I
I
VOLTAGE
OUTPUT
95
V
80
I
75
r--.
...........
70
85
60
o
0.5
1.5
2
2.5
3
10 - Output Current - A
3.5
:VI=5V:
4
2.5 "slCllv
.;
Figure 41
Figure 42
TRANSIENT RESPONSE (OVERSHOOT)
TRANSIENT RESPONSE (UNDERSHOOT)
.... '6;S'Mlll
... " ................... .
.
.
.
.
.
50 mVldlv:
.
:t.V" 371i1V
.. t
... jOO.~Vldl~ .... : ...
5 Itsldllt
·
·
..
.
·
.
.
.
+. .
~
: 5IWdiv;
Figure 44
Figure 43
~TEXAS
7-62
:
4 ......... ..
4
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
..
1 A1di~
.
.
..
..
:4V.~~j.~V .. : ...
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 - SEPTEMBER 1999
APPLICATION INFORMATION
Table 1. Bill of Materials (see Note 3)
REF
C10pt
C1
PN
10TPB220M
RV-35V221MH10-R
Capacitor, POSCAP, 220 IlF, 10 V
Capacitor, electrolytic, 220 IlF, 35 V
C2
GMK325F106ZH
Capacitor, ceramic, 10 IlF, 35 V
TaiyoYuden
1210
C3
C4t
4TPB470M
std
Capacitor, POSCAP, 470 IlF, 4 V
Open, capacitor, Ceramic, 2.2IlF, 16 V
Sanyo
7.3x4.3mm
805
C5
std
C6
C7
std
Capacitor, ceramic, 11lF, 16 V
Capacitor, ceramic, 0.01 IlF, 16 V
C8
C9
C10
C11t
10x10mm
805
Capacitor, ceramic, 100 pF, 16 V
805
std
GMK316F225ZG
Capacitor, ceramic, 1 IlF, 16 V
Capacitor, ceramic, 2.2 IlF, 35 V
Open
TaiyoYuden
805
1206
Capacitor, Ceramic, 2.2 IlF, 35 V
TaiyoYuden
805
1206
Capacitor, Ceramic, 10 IlF, 35 V
Open
Taiyo Yuden
1210
GMK325F106ZH
D2
L1
ELNA
805
805
C13
D1
SIZE
7.3x4.3mm
Capacitor, ceramic, 220 pF, 16 V
std
GMK316F225ZG
D10pt
MFG
Sanyo
std
std
C12
C14
C14topt
C15t
DESCRIPTION
std
MBRS340T3
Open
Open, capacitor, ceramic, 1000 pF, 16 V
10x10mm
Diode, Schottky, 40 V, 3 A
Motorola
805
SMC
MBRS130LT3
SD103-AWDICT-ND
Diode, Schottky, 30 V, 1 A
Diode, Schottky, 40 V, 200 rnA, 400 mW
Motorola
Digikey
5MB
3.5x1.5mm
D03316P-682
Inductor, 6.8 uH, 4.4 A
Coilcraft
0.5xO.37 in
J1-J14
JP1
CA26DA-D36W-OFC
S1132-2-ND
Edge connector, surface-mount, 0.040" board, 0.090" standoff
Header, straight, 2-pin, 0.1 ctrs, 0.3" pins
NAS Interplex
Sullins
0.040"
DigiKey#
S1132-2-ND
JP1 Shunt
929950'OO-ND
Shunt, jumper, 0.1"
3M
DigiKey
#929950-00-ND
JP2
S1132-2-ND
Header, straight, 2-pin, 0.1 ctrs, 0.3" pins
Sullins
DigiKey
#S1132-2-ND
R1
R2t
std
Resistor, 5.1 kn, 5 %
Open, resistor, 1 kn, 5%
805
std
R3
std
Resistor, 9100,1%
805
R4
std
std
Resistor, 1.74 k.Q, 1%
805
805
R5
R6A
R6Bt
R7
R9
R10
R11
std
std
std
std
std
std
805
Resistor, 5.1 kO, 5%
Resistor, 82 k.Q, 5%
Open, 00,5%
805
805
Resistor, 1 kn, 5%
805
805
Resistor, 1 kn, 5%
Resistor, 1 k.Q, 5%
805
Resistor, 10 0, 5%
805
805
805
Q1
std
std
Si4410DY
Resistor, 51 k.Q, 5%
Open
Transistor, MOSFET, n-ch, 30-V, 10-A, 13-mO
Siliconix
SO--S
Q2
Si4410DY
Transistor, MOSFET, n-ch, 3O-V, 10-A, 13-mO
Siliconix
SO--S
SSOP-20
R12
R13t
U1
TPS51 03
IC, controller
t Components for optional mode test only.
NOTE 3: This operation mode is PWM mode only.
TI
~TEXAS
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-63
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 - SEPTEMBER 1999
APPLICATION INFORMATION
Top Layer
Bottom Layer (Top VIew)
~TEXAS
7-64
.
INSTRUMENTS
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TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 - SEPTEMBER 1999
APPLICATION INFORMATION
Top Assembly
NOTE: All wire pairs should be twisted.
Test Setup
~TEXAS
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75265
7~5
TPS5103
MULTIPLE MODE SYNCHRONOUS DCfDC CONTROLLER
SLVS240-SEPTEMBER 1999
APPLICATION INFORMATION
Table 2. Test Specifications
PARAMETER
CONDITIONS
MIN
Input voltage range
TYP
5
Output voltage range
Vi:5-25V 10:0-4A
Output current range
Vi:5-10V
Output current limit
Vi:5V
Output ripple
VI:5V,
Operating frequency
10:4A
Efficiency
Vi:5V,
1.7
1.8
MAX
25
V
1.9
V
4
A
50
mVp-p
250
KHz
0
4.3
A
10:4A
150
Vo:l.8V,
10:4A
UNITS
90
%
Table 3. EVM Operating Specifications
SKIP MODE
Remove JPl shunt
HYSMODE
Remove R5, C6 and C7
Remove R6A
Add R6B
Add C15
If it needs the loop-compensation, add R2 and C4
This EVM is designed to cover as many applications as possible. For some more specific applications, the circuit
can be simpler. The table below gives some recommendations.
Table 4. EVM Application Recommendations
5·V INPUT VOLTAGE
Change Cl to low profile capacitor
Sanyo 10TPB220M (220 ILF, 10 V)
Or 6TPB330M (330 ILF. 6.3 V)
Remove Rl0
<3·A OUTPUT CURRENT
Change 01 and 02 to dual pack MOSFET,
IRF7311 to reduce the cost.
DIODE VERSION
Remove 02 to reduce the cost.
Table 5. Vendor and Source Information
MATERIAL
MOSFETS (01-02)
INPUT CAPACITORS (Cl)
MAIN DIODES (01)
INDUCTORS (L1)
PART NUMBER
Si441 0
IRF7811 (Intemational Rectifier)
RV-35V221MH10-R (ELNA)
35CV330AXIGX (Sanyo)
UUR1V221MNR1GS (Nichicon)
Bell Microproducts 972-783-4191
870-633-5030
Future Electronics (Local Office)
In EVM design
Second source
In EVM design
MBRS340T3 (Motorola)
U3FWJ44N (Toshiba)
D03316P~82 (Coilcraft)
Local distributors
Local distributors
972-458-2645
CTD03316P~2
Second source
CERAMIC CAPACITORS
(C2. C14) (C12. Cl0)
(Inductor Warehouse)
GMK325Fl06ZH
GMK316F225ZG
(Taiyo Yuden)
IN EVM design
~TEXAS
Local distributor
800-533-8295
SMEC
512-331-1877
e-mail: mlke@millsales.com
Taiyo Yuden representative
7~6
DISTRIBUTORS
SOURCE
In EVM design
Second source
In EVM design
Second source
.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
·
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240- SEPTEMBER 1999
APPLICATION INFORMATION
High current applications are described in Table 6. The values are recommendations based on actual test
circuits. Many variations are possible based on the requirements of the user. Performance of the circuit is
dependent upon the layout rather than on the specific components, if the device parameters are not exceeded.
The power stage, having the highest current levels and greatest dv/dt rates, should be given the most attention,
as both the supply and load can be severely affected by the power levels and edge rates.
Table 6. High Current Applications
REFERENCE
DESIGNATIONS
FUNCTION
8-AOUTPUT
2x ELNA
RV-35V221MH10-R
220I1F, 35 V
2x Taiyo Yuden
GMK325Fl06ZH
l0I1F,35V
12-AOUTPUT
3xELNA
RV-35V221MH10-R
22011F, 35 V
3x Talyo Yuden
GMK325Fl06ZH
lOI1F,35V
Coiltronics UP4B-1R5
1.5/lH, 13.4 A
16-AOUTPUT
4x ELNA
RV-35V221MH10-R
220 IlF, 35 V
4x Taiyo Yuden
GMK325Fl06ZH
lOIlF,35V
MicorMetals T6B-B/90
Corewm, #16
1.0I1H,25A
Cl
Input bulk capacitor
C2
Input bypass capacitor
L1
Output filter indicator
Coiltronics UP3B-2R2
2.2I1H,9.2A
C3
Output filter capacitor
2x Senyo 4TPB470M
470 I1F, 4 V
01
Power switch
2x Siliconix Si4410DY
30 V, lOA, 13 mO
3x Siliconix Si441 ODY
30 V, lOA, 13mO
4x Siliconix Si4410DY
30 V, lOA, 13mO
02
Power switch
2x Siliconlx Si441 ODY
30 V, lOA, 13mO
3x Siliconix Si441 ODY
30 V, lOA, 13mO
4x Siliconix Si4410DY
30 V, lOA, 13mO
70
10kO
200 kHz
50
15kO
150 kHz
40
20kO
100kHz
Rll
R12
Switching frequency
Gate drive resistor
Current limit resistor
3x Senyo 4TPB470M
47011F,4V
4x Sanyo 4TPB470M
470 IlF, 4 V
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7~7
7-68
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
1999
• 700 KHz Operation
• 1.25 MHz Operation With External Driver
• 1.5% Reference Over Full Operating
Temperature Range
• Synchronous Rectifier Driver for Greater
Than 90% Efficiency
• Programmable Reference Voltage Range of
1.3 Vt03.5V
• User-8electable Hysteretic Type Control
• Droop Compensation for Improved Load
Transient Regulation
• Adjustable Overcurrent Protection
• Programmable Softstart
• Overvoltage Protection
• Active Deadtlme Control
• Power Good Output
• Internal Bootstrap Schottky Diode
• Low Supply Current •.. 3-mA Typ
• Reduced System Component Count and
Size
PWPPACKAGE
(TOP VIEW)
lOUT
DROOP
OCP
VHYST
VREFB
VSENSE
ANAGND
SlOWST
BIAS
lODRV
lOHIB
DRVGND
lOWDR
DRV
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PWRGD
VIDO
VID1
VID2
VID3
VID4
INHIBIT
IOUTlO
lOSENSE
HISENSE
BOOTlO
HIGHDR
BOOT
Vee
description
The TPS5211 is a hysteretic regulator controller which provides an accurate, programmable supply voltage to
microprocessors. An internal 5-bit DAC is used to program the reference voltage to within a range of 1.3 V to
3.5 V. The output voltage can be set to equal the reference voltage or some multiple of the reference voltage.
A hysteretic controller with user-selectable hysteresis and programmable droop compensation is used to
dramatically reduce overshoot and undershoot caused by load transients. Propagation delay from the
comparator inputs to the output drivers is less than 250 ns. Overcurrent shutdown and crossover protection for
the output drivers combine to eliminate destructive faults in the output FETs. The softstart current source is
proportional to the reference voltage, thereby eliminating variation of the softstart timing when changes are
made to the output Voltage. PWRGD monitors the output voltage and pulls the open-collector output low when
the output drops 7% below the nominal output voltage. An overvoltage circuit disables the output drivers if the
output voltage rises 15% above the nominal value. The inhibit pin can be used to control power sequencing.
Inhibit and undervoltage lockout assures the 12-V supply voltage and system supply voltage (5 Vor 3.3 V) is
within proper operating limits before the controller starts. Single-supply (12 V) operation is easily accomplished
using a low-current divider for the required 5-V signals. The output driver circuits include 2-A drivers with internal
8-V gate-voltage regulators. The high-side driver can be configured either as a ground-referenced driver or as
a floating bootstrap driver. The TPS5211 is available in a 28-pin TSSOP PowerPADTM package. It operates over
a junction temperature range of O°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
TJ
.A.
~
ooe 10 125°e
TSSOP
(PWP)
TPS5211PWPR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALlAS, TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
7-89
-
jI
C
:::J
~
Vee
r
VID1
VIDO~
5
VID2
VID3
VID4
ANAGND
17
PWRGD
LOSENSE
120
28
n
o·:::J
IOUTLO HISENSE
21
!..
c:r
119
>----'- lOUT
~ZO
:I
~
3
..... -<
:o"'U
0:0
~O
~Q
:0»
i:
i:
>to
.......
~
m
!~4r
m:a~
•
~~~
~~~
i~
0
o---J
MUX
14 DRV
•
!I
1 __"
••
t;
VID
BIAS
1
16
BOOT
17 HIGHDR
200kn
and
Shutdown
I
I
18 BOOTLO
•
13 LOWDR
2
6
23
5
VIDO VID1 VID2 VID3 VID4 VREFB DROOP VHYST VSENSE
LOHIB
LODRV
o
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243-SEPTEMBER 1999
Terminal Functions
TERMINAL
NAME
NO.
ANAGND
7
BIAS
9
DESCRIPTION
1/0
Analog ground
0
Analog BIAS pin. A 1-I1F ceramic capacitor should be connected from BIAS to ANAGND.
BOOT
16
I
Bootstrap. Connect a 1-I1F low-ESR capacitor from BOOT to BOOTLO.
BOOTLO
18
0
Bootstrap low. Connect BOOTLO to the junction of the high-side and low-side FETs for floating drive
configuration. Connect BOOTLO to PGND for ground reference drive configuration.
DROOP
2
I
Droop voltage. Voltage input used to set the amount of output-voltage set-point droop as a function of load
current. The amount of droop compensation is set with a resistor divider between lOUT and ANAGND.
DRV
14
0
Drive regulator for the FET drivers. A 1-I1F ceramic capacitor should be connected from DRV to DRVGND.
DRVGND
12
HIGHDR
17
0
High drive. Output drive to high-side power switching FETs
HISENSE
19
I
High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs; for
optional resistor sensing scheme, connect to power supply side of current-sense resistor placed in series with
high-side FET drain.
INHIBIT
22
I
Disables the drive signals to the MOSFET drivers. Can also serve as UVLO for system logic supply (either 3.3 V
or5 V).
lOUT
1
0
Current out. Output voltage on this pin is proportional to the load current as measured across the Rds(on) olthe
high-side FETs. The voltage on this pin equals 2xRds(on)xIOUT. In applications requiring very accurate
current sensing, a sense resistor should be connected between the input supply and the drain of the high-side
FETs.
10UTLO
21
0
Current sense low output. This is the voltage on the LOSENSE pin when the high-side FETs are on. A ceramic
capacitor should be connected from IOUTLO to HISENSE to hold the sensed voltage while the high-side FETs
are off. CapaCitance range should be between 0.033 I1F and 0.1 11F.
LODRV
10
I
Low drive enable. Normally tied to 5 V. To activate the low-side FETs as a crowbar, pull LODRV low.
LOHIB
11
I
Low side inhibit. Connect to the junction of the high and low side FETs to control the anti-cross-conduction and
eliminate shoot-through current. Disabled when configured in crowbar mode.
LOSENSE
20
I
Low current sense. For current sensing across high-side FETs, connect to the source of the high-side FETs; for
optional resistor sensing scheme, connect to high-side FET drain side of current-sense resistor placed in series
with high-side FET drain.
Drive ground. Ground for FET drivers. Connect to FET PWRGND.
LOWDR
13
0
Low drive. Output drive to synchronous rectifier FETs
OCP
3
I
Over current protection. Current limit trip point is set with a resistor divider between lOUT and ANAGND.
PWRGD
28
0
Power good. Power good signal goes high when output voltage is within 7% of voltage set by VID pins.
Open-drain output.
SLOWST
8
0
Siowstart (soft start). A capacitor from SLOWST to ANAGND sets the slowstart time.
Siowstart current IVREFB'5
Vee
VHYST
15
4
I
HYSTERESIS set pin. The hysteresis is set with a resistor divider from VREFB to ANAGND.
The hysteresis window 2 x (VREFB - VHYST)
VIDO
27
I
Voltage identification input 0
VID1
26
I
Voltage identification input 1
VID2
25
I
Voltage identification input 2
VID3
24
I
Voltage identification input 3
VID4
23
I
Voltage Identification input 4. Digital inputs that set the output voltage of the converter. The code pattern for
setting the output voltage is located in Table 1. Internally pulled up to 5 V with a resistor divider biased from VCC.
VREFB
5
0
Buffered reference voltage from VID network
VSENSE
6
I
Voltage sense input. To be connected to converter output voltage bus to sense and control output voltage. It is
recommended an RC low pass filter be connected at this pin to filter noise.
=
12-V supply. A 1-I1F ceramic capacitor should be connected from VCC to DRVGND.
=
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-71
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 - SEPTEMBER 1999
detailed description
VREF
The referencelvoltage identification (VID) section consists of a temperature-compensated bandgap reference
and a S-bit voltage selection network. The S VID terminals are inputs to the VID selection network and are
TTL-compatible inputs internally pulled up to S V by a resistor divider connected to Vee. The VID codes conform
to the Intel VRM 8.3 DC-DC Converter Specification for voltage settings between 1.8 V and 3.S V, and they are
decremented by SO mV, down to 1.3 V, for the 10werVID settings. Voltages higher than VREFcan be implemented
using an external divider. Refer to Table 1 for the VID code settings. The output voltage ofthe VID network, VREF>
is within ±1.S% of the nominal setting over the VID range of 1.3 V to 2.S V, including a junction temperature range
of SoC to +12SoC, and a Vee supply voltage range of 11.4 V to 12.6 V. The output of the referenceNlD network
is indirectly brought out through a buffer to the VREFB pin. The voltage on this pin will be within SmV of VREF
It is not recommended to drive loads with VREFB, other than setting the hystereSis of the hysteretiC comparator,
because the current drawn from VREFB sets the charging current for the slowstart capacitor. Refer to the
slowstart section for additional information.
hysteretic comparator
The hysteretiC comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by 2 external resistors and is centered on VREF. The 2 external resistors form a resistor divider from VREFB
to ANAGND, with the output voltage connecting to the VHYST pin. The hysteresis of the comparator will be
equal to twice the voltage difference between the VREFB and VHYST pins. The propagation delay from the
comparator inputs to the driver outputs is 2S0 ns (maximum). The maximum hysteresis setting is 60 mY.
low-side driver
The low-side driver is deSigned to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The bias to the low-side driver is internally connected to the DRV regulator.
high-side driver
The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The high-side driver can be configured either as a ground-referenced driver or as a floating
bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from the DRV
regulator. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved
drive efficiency. The maximum voltage that can be applied between BOOT and DRVGND is 30 V. The driver
can be referenced to ground by connecting BOOTlO to DRVGND, and connecting BOOT to either DRV or Vee.
The rms current through the drivers output should not exceed 110 rnA. Refer to the application information
section to determine how to calculate an operating frequency to meet this requirement.
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed
to turn on until the gate-drive voltage to the low-side FETs is below 2 V; the low-side driver is not allowed to turn
on until the voltage at the junction of the high-side and low-side FETs (Vphase) is below 2 V.
detatled description (continued)
current sensing
Current senSing is achieved by sampling and holding the voltage across the high-side power FETs while the
high-side FETs are on. The sampling network consists of an internal 60-n switch and an external ceramic hold
capacitor. Recommended value of the hold capacitor is between 0.033 IlF and 0.1 1lF. Internal logic controls
the turnon and turnoff of the sample/hold switch such that the switch does not turn on until the Vphase voltage
transitions high, and the switch turns off when the input to the high-side driver goes low. The sampling will occur
only when the high-side FETs are conducting current. The voltage on the lOUT pin equals 2 times the sensed
~TEXAS
7-72
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 - SEPTEMBER 1999
high-side voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can
be placed in series with the high-side FETs, and the voltage across the sense resistor can be sampled by the
current sensing circuit.
droop compensation
The droop compensation network reduces the load transient overshooVundershoot on YO, relative to VREF. Vo
is programmed to a voltage greater than VREF by an external resistor divider from Vo to VSENSE to reduce the
undershoot on Vo during a low-to-high load transient. The overshoot during a high-to-Iow load transient is
reduced by subtracting the voltage on DROOP from VREF- The voltage on lOUT is divided with an external
resistor divider, and connected to DROOP.
inhibit
INHIBIT is a TTL-compatible digital input used to enable the controller. When INHIBIT is low, the output drivers
are low and the slowstart capacitor is discharged. When INHIBIT goes high, the short across the slowstart
capacitor is released and normal converter operation begins. When the system-logic supply is connected to
INHIBIT, it also controls power sequencing by locking out controller operation until the system-logic supply
exceeds the input threshold voltage of the inhibit circuit. The 12-V supply and the system logic supply (either
5 V or 3.3 V) must be above UVLO thresholds before the controller is allowed to start up. The start threshold
is 2.1 V and the hysteresis is 100 mV for the INHIBIT comparator.
Vee undervoltage lockout (UVLO)
The undervoltage lockout circuit disables the controller while the Vee supply is below the 10-V start threshold
during power up. When the controller is disabled, the output drivers will be low and the slowstart capaCitor is
discharged. When Vee exceeds the start threshold, the short across the slowstart capaCitor is released and
normal converter operation begins. There is a 2-V hysteresis in the undervoltage lockout circuit for noise
immunity.
slowstart
The slowstart circuit controls the rate at which Vo powers up. A capaCitor is connected between SLOWST and
ANAGND and is charged by an internal current source. The current source is proportional to the reference
voltage, so that the charging rate of CSLOWST is proportional to the reference voltage. By making the charging
current proportional to VREFo the power-up time for Vo will be independent of VREF- Thus, CSLOWST can remain
the same value for all VID settings. The slowstart charging current is determined by the following equation:
'slowstart =I(VREFB) / 5 (amps)
Where I(VREFB) is the current flowing out of VREFB.
It is recommended that no additional loads be connected to VREFB, other than the resistor divider for setting
the hysteresis voltage. The maximum currentthat can be sourced by the VREFB circuit is 500 J.LA. The equation
for setting the slowstart time is:
tSLOWST =5 x CSLOWST x RVREFB
(seconds)
Where RVREFB is the total external resistance from VREFB to ANAGND.
detailed description (continued)
power good
The power-good circuit monitors for an undervoltage condition on yo. If Vo is 7% below VREFo then the PWRGD
pin is pulled low. PWRGD is an open-drain output.
~TExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-73
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 - SEPTEMBER 1999
overvoltage protection
The everveltage pretectien (OVP) circuit meniters Vo fer an everveltage cenditien. If Vo is 15% abeve VREF>
then a fault latch is set and beth eutputdrivers are turned eff. The latch will remain set until Vee gees be lew the
underveltage leckeut value. A 3-1lS deglitch timer is included fer neise immunity. Refer to. the LODRV sectien
fer infermatien en hew to. pretect the micreprecesser against everveltages due to. a sherted fault acress the
high-side pewer FET.
overcurrent protection
The evercurrent pretectien (OCP) circuit meniters the current threugh the high-side FET. The evercurrent
thresheld is adjustable with an external resister divider between lOUT and ANAGND, with the divider veltage
cennected to. the OCP pin. If the veltage en OCP exceeds 100 mV, then a fault latch is set and the eutput drivers
are turned eff. The latch will remain set until Vee gees belew the underveltage leckeut value. A 3-1lS deglitch
timer is included fer neise immunity. The OCP circuit is also. designed to. pretectthe high-side pewer FET against
a shert-te-greund fault en the terminal cemmen to. beth pewer FETs.
drive regulator
The drive regulater prevides drive veltage to. the eutput drivers. The minimum drive veltage is 7 V. The minimum
shert circuit current is 100 mA. Cennect a I-I1F ceramic capaciter frem DRV to. DRVGND.
LODRV
The LODRV circuit is designed to. pretect the micreprecesser against everveltages that can eccur if the high-side
pewer FETs beceme sherted. External cempenents to. sense an everveltage cenditien are required to. use this
feature. When an everveltage fault eccurs, the lew-side FETs are used as a crewbar. LODRV is pulled lew and
the lew-side FET will be turned en, everriding a" centrel signals inside the TPS5211 centreller. The crowbar
actien will shert the input supply to. greund threugh the faulted high-side FETs and the lew-side FETs. A fuse
in series with Yin sheuld be added to. discennect the shert-circuit.
Table 1. Voltage Identification Codes
VID TERMINALS
(0
=GND, 1 =floating or pull-up to 5 V)
VID4
VID3
VID2
VIDl
VIDO
(Vdc)
0
1
1
1
1
1.30
0
1
1
1
0
1.35
0
1
1
0
1
1.40
0
1
1
0
0
1.45
0
1
0
1
1
1.50
0
1
0
1
0
1.55
0
1
0
0
1
1.60
0
1
0
0
0
1.65
0
0
1
1
1
1.70
0
0
1
1
0
1.75
0
0
1
0
1
1.80
0
0
1
0
0
1.85
0
0
0
1
1
1.90
~TEXAS
7-74
VREF
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 - SEPTEMBER 1999
Table 1. Voltage Identification Codes (Continued)
VID TERMINALS
(0
=GND, 1 =floating or pull-up to 5 V)
VREF
VID4
VID3
VID2
VID1
VIDO
0
0
0
1
0
(Vdc)
1.95
0
0
0
0
1
2.00
0
0
0
0
0
2.05
1
1
1
1
1
No CPU
1
1
1
1
0
2.10
1
1
1
0
1
2.20
1
1
1
0
0
2.30
1
1
0
1
1
2.40
1
1
0
1
0
2.50
1
1
0
0
1
2.60
1
1
0
0
0
2.70
1
0
1
1
1
2.80
1
0
1
1
0
2.90
1
0
1
0
1
3.00
1
0
1
0
0
3.10
1
0
0
1
1
3.20
1
0
0
1
0
3.30
1
0
0
0
1
3.40
1
0
0
0
0
3.50
absolute maximum ratings over operating virtual Junction temperature {unless otherwise noted)t
Supply voltage range, Vee (see Note1) .............................................. -0.3 V to 14 V
Input voltage range: BOOT to DRVGND (High-side Driver ON) ......................... -0.3 V to 30 V
BOOT to HIGHDRV ............................................ -0.3 V to 15 V
BOOT to BOOTlO ............................................. -0.3 V to 15 V
INHIBIT, VIDx, lODRV ........................................ -0.3 V to 7.3 V
PWRGD, OCP, DROOP ......................................... -0.3 V to 7 V
lOHIB, lOSENSE, IOUTlO, HISENSE .......................... -0.3 V to 14 V
VSENSE ...................................................... -0.3 V to 5 V
Voltage difference between ANAGND and DRVGND ......................................... ±O.5 V
Output current, VREFB ................................................................... 0.5 rnA
Short circuit duration, DRV ........................................................... Continuous
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating virtual junction temperature range, TJ ....................................... O°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds ....................... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGND.
DISSIPATION RATING TABLE
=
=
PACKAGE
TA s 25°e
POWER RATING
DERATING FACTOR
ABOVE TA 25°e
TA 70 0 e
POWER RATING
TA 85°e
POWER RATING
PWP
1150mW
11.5mW/"C
630mW
460mW
=
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
7-75
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 - SEPTEMBER 1999
recommended operating conditions
UNIT
MIN
MAX
11.4
13
V
Input voltage, BOOT to DRVGND
0
28
V
Input voltage, BOOT to BOOTlO
0
13
V
Input voltage, INHIBIT, VIDx, lODRV, PWRGD, OCP, DROOP
0
6
V
Input voltage, lOHIB, lOSENSE, 10UTlO, HISENSE
0
13
V
Input voltage, VSENSE
0
4.5
V
Voltage difference between ANAGND and DRVGND
0
±O.2
V
Output current, VREFBt
0
0.4
rnA
Supply voltage, VCC
t Not recommended to load VREFB other than to set hystersis since IVREFB sets slowstart time.
electrical characteristics over recommended operating virtual junction temperature range,
Vee = 12 V, IORV = 0 A (unless otherwise noted)
reference/voltage Identification
PARAMETER
TEST CONDITIONS
VREF
Cumulative reference accuracy
(see Note 2)
VIDx
High-level input voltage
VIDx
lOW-level input voltage
VREFB
VIDx
MIN
VCC = 11.4to 12.6 V, 1.3 V S;VREFS;3.5 V
TYP
MAX
-0.015
0.Q15
2.25
IVREFB = 50 IIA
Output regulation
10 IIA S; 10 S; 500 IIA
Input resistance
VIDx=OV
VREf-5mV
VREF VREF+5mV
V
V
mV
2
Input pull-up vottage dMder
VN
V
1
Output voltage
UNIT
36
73
95
kO
4.8
4.9
5
V
NOTES: 2. Cumulative reference accuracy is the combined accuracy of the reference voltage and the input offset voltage of the hysteretic
comparator. Cumulative accuracy equals the average of the high-level and low-level thresholds of the hysteretiC comparator.
3. This parameter is ensured by design and is not production tested.
power good
PARAMETER
TEST CONDmONS
Undervoltage trip threshold
VOL
lOW-level output voltage
10=5mA
10H
High-level Input current
VPW8.GD=6V
Vhvs
Hysteresis voltage
MIN
TYP
90
93
0.5
MAX
UNIT
95 %VREF
0.75
V
1
IIA
1.3
2.9
4.5 %VREF
MIN
TYP
MAX
UNIT
10.4
13
15.6
IIA
slowstart
PARAMETER
TEST CONDIT10NS
Charge current
VSlOWST = 0.5 V,
IVREFB = 6511A
Discharge current
VSlOWST=1 V
VVREFB = 1.3 V,
Comparator Input bias current
10
See Note 3
Comparator hysteresis
10
-7.5
NOTE 3: This parameter Is ensured by deSign and IS not production tested.
~TEXAS
7-76
mA
3
Comparator input offset voltage
INSTRUMENTS
POST OFFICE sox 655303 • DALLAS. TEXAS 75265
mV
100
nA
7.5
mV
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 - SEPTEMBER 1999
electrical characteristics over recommended operating virtual junction temperature range,
Vee =12 V,IORV =0 A (unless otherwise noted) (continued)
hysteretic comparator
TEST CONDITIONS
PARAMETER
MIN
=0 V (see Note 3)
Input offset voltage
VDROOP
Input bias current
See Note 3
Hysteresis accuracy
VREFB - VHYST 15 mV
(Hysteresis window 30 mV)
Maximum hysteresis setting
VREFB -
TYP
-2.5
=
=
VHYST =30 mV
MAX
2.5
-3.5
UNIT
mV
500
nA
3.5
mV
60
mV
NOTE 3: ThiS parameter IS ensured by deSign and IS not production tested.
high-side VOS senSing
PARAMETER
TEST CONDITIONS
MIN
Gain
lOUT
lOUT
=
=
=
VLOSENSE 11.9V,
VHISENSE 12 V,
Differential input to V ds sensing amp 100 mV
Sink current
5 VSVIOUTLOS 13V
Source current
VIOUT 0.5 V,
VIOUTLO 11.5 V
Sink current
VIOUT 0.05 V, VHISENSE
VIOUTLO 12 V
=
=
VHISENSE
=
Output voltage swing
LOSENSE
MAX
2
Initial accuracy
IOUTLO
TYP
I High-level Input voltage
I Low-level Input voltage
=12 V,
=12 V,
=
VHISENSE =11 V, RIOUT =10 kn
VHISENSE =4.5 V, RIOUT =10 kn
VHISENSE =3 V, RIOUT = 10 kn
VHISENSE
=4.5 V (see Note 3)
194
UNIT
VN
206
mV
250
nA
tJ.A
500
tJ.A
50
0
2
V
0
1.5
V
0
0.75
V
V
2.S5
2.4
V
11.4 V S VHISENSE S 12.6 V,
LOSENSE connected to HISENSE,
VHISENSE - VIOUTLO 0.15 V
50
60
80
4.5 V S VHISENSE S 5.5 V,
LOSENSE connected to HISENSE,
VHISENSE - VIOUTLO 0.15 V
62
85
123
3 V S VHISENSE S 3.6 V,
LOSENSE connected to HI SENSE,
VHISENSE - VIOUTLO 0.15 V
67
95
144
69
75
MIN
TYP
MAX
1.9
2.1
2.35
V
Hysteresis
O.OS
0.1
0.12
V
Stop threshold
1.S5
=
Sample/hold resistance
Q
=
=
=
VHISENSE 12.6 V to 3 V,
VHISENSE - VOUTLO 100 mV
CMRR
=
dB
NOTE 3. This parameter IS ensured by deSign and IS not production tested.
Inhibit
PARAMETER
TEST CONDITIONS
Start threshold
UNIT
V
~lExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
7-n
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243-SEPTEMBER 1999
electrical characteristics over recommended operating virtual junction temperature range,
Vee 12 V, IDRV 0 A (unless otherwise noted) (continued)
=
=
overvoltage protection
PARAMETER
TEST CONDmONS
Overvoltage trip threshold
MIN
TYP
112
115
See Note 3
Hysteresis
MAX
UNIT
120 %VREF
10
mV
NOTE 3: ThiS parameter IS ensureltby deSign and IS not production tested.
overcurrent protection
PARAMETER
TEST CONDITIONS
oep trip threshold
MIN
TYP
MAX
90
100
110
mV
100
nA
Input bias current
UNIT
deadtime
PARAMETER
LOHIB
LOWDR
TEST CONDITIONS
High-level input voltage
MIN
TYP
MAX
2.4
Low-level input voltage
1.4
High-level input voltage
See Note 3
Low-level input voltage
See Note 3
3
1.7
UNIT
V
V
NOTE 3: This parameter Is ensured by deSign and IS not production tested.
LODRV
PARAMETER
LODRV
TEST CONDITIONS
I High-level input voltage
MIN
TYP
MAX
1.85
I Low-level input voltage
0.95
UNIT
V
droop compensation
PARAMETER
MIN
Initial accuracy
TYP
MAX
54
46
drive regulator
PARAMETER
TEST CONDITIONS
Output voltage
11.4 V:s Vee:S 12.6 V.
Output regulation
1 mA:s IDRV:S50 rnA
IDRV= 120 rnA
MIN
TYP
7
MAX
9
V
mV
100
120
Short-circuit current
UNIT
rnA
bias regulator
PARAMETER
Output voltage
TEST CONDITIONS
11.4 V :SVee:S 12.6 V.
See Note 4
MIN
TYP
MAX
6
NOTE 4: The bias regulator is designed to provide a quiet bias supply for the TPS5211 controller. External loads should not be driven by the bias
regulator.
input undervoltage lockout
MIN
TYP
MAX
UNiT
9.25
10
10.75
V
Hysteresis
1.9
2
2.2
V
Stop threshold
7.5
PARAMETER
TEST CONDITIONS
Start threshold
~TEXAS
INSTRUMENTS
7-78
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
V
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 - SEPTEMBER 1999
electrical characteristics over recommended operating virtual junction temperature range,
Vee = 12 V, IORV = 0 A (unless otherwise noted) (continued)
output drivers
PARAMETER
Peak output
current
(see Note 5)
MIN
High-side sink
High-side source
VHIGHDR = 1.5 V (source) or 6 V (sink),
See Note 3
2
Low-side sink
Duty Cycle < 2%,
TJ = 125°C,
2
Low-side source
VLOWDR = 1.5 V (source) or 5 V (sink),
See Note 3
High-side sink
Output
resistance
(see Note 5)
TEST CONDITIONS
Duty cycle < 2%,
TJ = 125°C,
High-side source
Low-side sink
Low-side source
tpw < 100 /lS,
VBOOT - VBOOTLO = 6.5 V,
tpw < 100 /lS,
VDRV=6.5V,
TVP
MAX
UNIT
2
A
2
3
TJ = 125°C,
VBOOT - VBOOTLO = 6.5 V,
VHIGHDR = 6 V (source) or 0.5 V (sink)
45
5.7
TJ = 125°C,
VDRV=6.5V,
VLOWDR = 6 V (source) or 0.5 V (sink)
Q
45
NOTES: 3. This parameter Is ensured by design and is not production tested.
5. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the Rds(on) of the MOSFET transistor when
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
supply current
PARAMETER
Vee
TEST CONDITIONS
Supply voltage
range
VINHIBIT = 5 V,
Vee> 10.75 V at startup,
Vee
Quiescent
current
High-side
driver
quiescent
current
VINHIBIT = 5 V,
Vee> 10.75 V at startup,
eHIGHDR = 50 pF,
fSWX = 200 kHz,
VID code .. 11111,
VBOOTLO=OV
VID code .. 11111,
VBOOTLO = 0 V,
eLOWDR = 50 pF,
See Note 3
MIN
TVP
MAX
11.4
12
13
3
10
VINHIBIT = 5 V,
VBOOT=13V,
eHIGHDR = 50 pF,
V
rnA
5
VINHIBIT = 0 V or VID code = 11111 or Vee < 9.25 V at startup,
VBOOT= 13V,
VBOOTLO=OV
VID code .. 11111, Vee> 10.75 V at startup,
VBOOTLO = 0 V,
fSWX = 200 kHz (see Note 3)
UNIT
80
2
I1A
rnA
NOTE 3: This parameter is ensured by design and is not production tested.
-!i1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
7-79
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243-SEPTEMBER 1999
switching characteristics over recommended operating virtual-Junction temperature range,
Vee 12 V, IORV 0 A (unless otherwise noted)
=
=
PARAMETER
TEST CONDITIONS
VSENSE to HIGHDR or
LOWDR (excluding deadtime)
MIN
1.3 V S VVREF S 3.5 V. 10 mV overdrive
(see Note 3)
2SO
200
1.3 V S VVREF S 3.5 V. 30 mVoverdrive
190
UNIT
ns
180
1
See Note 3
OVP comparator
1
PWRGD comparator
JI.S
1
SLOWST comparator
Overdrive = 10 mV (see Note 3)
CL=50pF.
HIGHDR output
Rise time
LOWDR output
560
35
CL=SOpF
8
35
TBD
CL=SOpF
2
5
2
5
See Note 3
OVP
VHISENSE = 12 V.
VIOUTLO pulsed from 12 Vto 11.9 V.
100 ns rlse/fall times
(see Note 3)
2
VHISENSE = 4.5 V.
VIOUTLO pulsed from 4.5 V to 4.4 V.
100 ns rise/fall times (see Note 3)
3
VHISENSE = 3 V.
VIOUTLO pulsed from 3 V to 2.9 V.
100 ns rise/fall times (see Note 3)
3
Short-circuit protection
rising-edge delay
SCP
LOSENSE = 0 V (see Note 3)
Tumon/tumoff delay
VDS sensing samplelhold
switch
Crossover delay time
Prefilter pole frequency
ns
40
CL=3nF
OCP
High-side VDS sensing
ns
TBD
VeoOTLO=OV
CL=3nF
LOWDR output
ns
40
CL=3nF
HIGHDR output
900
8
VSOOTLO=OV
CL=3nF
CL=SOpF.
Fall time
JI.S
JI.S
300
SOO
ns
3 V S VHISENSE S 11 V.
VLOSENSE = VHISENSE (see Note 3)
30
100
ns
LOWDR to HIGHDRV. and
LOHIB to LOWDR
See Note 3
30
100
ns
Hysteretic comparator
See Note 3
Propagation delay
LODRV
See Note 3
NOTE 3: thiS parameter IS ensured by deSign and IS not production tested.
~1EXAS
7-80
1SO
1.3 V S VVREF S 3.5 V. 20 mV overdrive
OCP comparator
Response time
MAX
1.3 V S VVREF S 3.5 V. 40 mVoverdrive
Propagation delay
Deglitch time (Includes
comparator propagation
delay)
TYP
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MHz
5
400
ns
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 - SEPTEMBER 1999
TYPICAL CHARACTERISTICS
SLOWSTART TIME
100
..
SLOWSTART TIME
vs
vs
SLOWSTART CAPACITANCE
SUPPLY CURRENT (VREFB)
V(VREFB) = 2 V
I(VREFBl: = 100 r.tA
TJ = 25 0
IL
lL
10
E
.
I
E
1=
V
t:
iii
'"
~
0
iii
/
0.1
o
0.0001
0.0010
0.0100
0.1000
Siowstart Capacitance - IlF
ICC - Supply Current (VREFB) - IlA
Figure 1
Figure 2
DRIVER
DRIVER
OUTPUT RISE TIME
OUTPUT FALL TIME
vs
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
1000
1000
~T
..
..E
..
c
=2
0
..
100
c
..
I
0
100
I
E
i=
..
i=
....~
.!!
II:
I
-
r, =21
I~n:
10
:Ide
--
V
oW.~!le
0.01
0.10
1.00
I
.!!
SI
II:
I
10.00
100.0
e
~~
~
J..,.o""
10
ow ~
1
0.01
CL - Load Capacitance - nF
0.10
e
1.00
10.00
100.(
CL - Load Capacitance - nF
Figure 3
Figure 4
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-81
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243-SEPTEMBER 1999
TYPICAL CHARACTERISTICS
OVP THRESHOLD
vs
JUNCTION TEMPERATURE
OCP THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
105.---.---,---,--,----,
118
117
>
103~-~---+---+--~----1
E
';I.
I
116
I
CD
CI
:ll!
'1:1
..
is
.c
~
115
.c
~
.c
>
0
114
.c
I!!
lII.
101~---1-----+-----r----~----i
-
I! 991-----+--+---t--+-----1
lll.
0
0
113
112
0
25
50
75
100
971------+----~----+_--_t----~
95~--~~--~--~~--_7.=---_7.
o
125
25
TJ - Junction Temperature - °C
INHIBIT START THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
>
I
E
2.05
I
125
CD
~
I
2
~
"'-
.r!!
I!
100
~
t
l-
"C
---..........
:r::
91
:is
:c
1.95
.5
.5
1.9 L-_---J_ _---L_ _.....L.._ _....!...._----l
o
25
50
75
100
125
I'----
V
75
50
o
TJ - Junction Temperature - °C
Figure 7
25
50
~1ExAS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
75
100
TJ - Junction Temperature - °C
Figure 8
INSTRUMENTS
7--a2
125
150
>
:is
:c
100
INHIBIT HYSTERESIS VOLTAGE
vs
JUNCTION TEMPERATURE
2.1
.c
I!!
.c
75
Figure 6
Figure 5
t
~
..
50
TJ - Junction Temperature - °C
125
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 - SEPTEMBER 1999
TYPICAL CHARACTERISTICS
UVLO START THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
10.5
UVLO HYSTERESIS
vs
JUNCTION TEMPERATURE
2.5
_I.
J
VI=12V
VI= 12V
>
2.3
I
GI
'"
S
-
10
~
~
:2
0
s:.
~
s:.
t:
l-
9l
---
>
I
r--
.~
2.1
J!!
~
0
....I
1.9
--
>
::J
9.5
0
....I
>
::J
1.7
9
o
25
50
100
75
125
1.5
o
TJ - Junction Temperature - °C
25
Figure 9
95
VI= 121V
--
94
4
C
93
~
=
()
..
.~
C
GI
a=
~
2
125
POWERGOOD THRESHOLD
vs
JUNCTION TEMPERATURE
6
I
100
Figure 10
QUIESCENT CURRENT
vs
JUNCTION TEMPERATURE
ct
E
75
50
TJ - Junction Temperature - °C
l,...--
~
~
-
92
91
o
o
25
50
75
100
125
90
o
TJ - Junction Temperature - °C
25
50
75
100
125
TJ - Junction Temperature - °C
Figure 11
Figure 12
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-83
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 - SEPTEMBER 1999
TYPICAL CHARACTERISTICS
DRIVER
REGULATOR VOLTAGE
SLOWSTART CHARGE CURRENT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
15~--~----~----~--~----~
8.5
=
=
V(VREFB) 1.3 V
R(VREFB) 20 len
~
14~---+----~----+---~----~
I
1
,
8.25
>
I
II
~
12~---+----~----+----4----~
8
I
I
7.75
11~---+----~----+---~----~
10~--~----~----~--~----~
o
25
50
75
100
-
I---
7.5
125
o
25
TJ - Junction Temperature - °C
Figure 13
~
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
6
c:
4
I
I••
J
i
i'S
3
~II
2
"a
------- ----I
~
II
~
./'"
4
II:
~
Do
~
~
~
V
2
I
i
i
o
o
25
50
75
100
125
o
o
25
50
75
100
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 15
Figure 16
~TEXAS
7-84
125
DRIVER
LOW-9IDE OUTPUT RESISTANCE
5
I
100
Figure 14
DRIVER
HIGH-SIDE OUTPUT RESISTANCE
c:
75
50
TJ - Junction Temperature - °C
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75266
125
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243-SEPTEMBER 1999
TYPICAL CHARACTERISTICS
SENSING SAMPLE/HOLD RESISTANCE
vs
JUNCTION TEMPERATURE
100
I
V(HISENSE)
c:;
=12 !.V
I
tl
c
I
75
~
:!la.
:z:
l..----
....--
~
50
E
c7l
Q
C
iii
Iii
25
In
I
0
II:
o
o
25
50
75
100
125
TJ - Junction Temperature - °C
Figure 17
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
7-85
TPS52t1
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243-SEPTEMBER 1999
APPLICATION INFORMATION
The following figure is a typical application schematic. The circuit can be divided into the power-stage section
and the control-circuit section. The power stage must be tailored to the input/output requirements of the
application. The control circuit is basically the same for all applications with some minor tweaking of specific
values. Table 2 shows the values of the power stage components for various output-current options.
l101
12V
r
--
l102
--
Q101
/"""'
~~
-;;:
C1~
r-
~~
-
R101~
1> R103
~ f::
;;;f::
R102
GND
C103
C102
;;;:
C104
f::
~~
'---
~~~!..-
Po
Co nlrol Section
~
r-----'
r-;::::=..-
---w I-ii - r - - - -
~
ffisa
J:
Q
J:
52
J:
CJ
i
Q
III
~
Q
....I
Z
ENAB lE
9
A
~
II:
>
~
R2 !"
150
R11 ~
10.0 k >
DROOP
h
2I. PWRGD
lOUT
1
28
TPS5211
U1
II
R31,~Ok
100
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
I
R7
I~2k
R9
".;S':K
Figure 18. Standard Application Schematic
~TEXAS
R6. 'v
,~~
NOTE A. VIDO - VID4 User - selected to set output voltage.
INSTRUMENTS
C4
1 uF
IL
1\
C511
0.1 uFI\
C711
1000pFI\
-
~
I- -
I-
DRV
14
C3\1 15
lOWDR
BOOT
1 ui:! 16 HIGH DR DRVGND ..!!...
17
BOOTlO
lOHIB .1!....18
HISENSE
lODRV
10
19 lOSENSE
BIAS
20
C611
SlOWST 9
IOUTlO
0.033 uFI\
8
21 INHIBIT
ANAGND
7
(see ~t!.A)..E.
VID4
VSENSE
6
VREFB
VID3
~
24
5
VHYST
;;;:~C8
I- - ....;:...:... VID2
4
VID1
OCP
~200PF I- VIDO
en
Z
w
en
~
w
C2
1--..2.
R4
2.55k ~
1%
~ !I:wi
:i:
0
1&
VCC
R1
3.40k
1%
-- I - -w --z 1 - - - -
- - - - - - - - - - r-
1C1,+
uF
7-86
Vo
1
20:0k
R8
1.00k
-vvv
-Fll0
I 1.00k
RTN
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 - SEPTEMBER 1999
APPLICATION INFORMATION
Table 2. Power Stage Components
Reference Designation
12-V-lnput Power Stage Components
Function
4-AOut
B-AOul
12-AOul
2O-AOut
Cl0l
Input capacitor
muRata,
GRM23SY106Z016A,
2 x lO-uF, 16-V, YSV
muRata,
GRM23SY106Z016A,
4 x lG-uF, 16-V, YSV
muRata,
GRM23SY106Z016A,
6 x lo-uF, 16-V, YSV
muRata,
GRM23SY106Z016A,
10 x 1O-uF, 16-V, YSV
Cl02
Snubber capacitor
muRata,
GRM39X7Rl02KOSOA,
100o-pF, SO-V, X7R
muRata,
GRM39X7Rl02KOSOA,
1000-pF, SO-V, X7R
muRata,
GRM39X7Rl02KOSOA,
2 x 100o-pF, SO-V, X7R
muRata,
GRM39X7Rl02KOSOA,
3 x 100o-pF, SO-V, X7R
Cl03
Output bulk
capaCitor
Sanyo,
4TPC1S0M,
lSG-uF, 4-V, 20%
Sanyo,
4TPC1S0M,
2 x lSG-uF, 4-V, 20%
Sanyo,
4TPC1S0M,
3 x lSo-uF, 4-V, 20%
Sanyo,
4TPC1S0M,
4 x lSo-uF, 4-V, 20%
Cl04
Output hi-lreq
bypass capacitor
muRata,
GRM23SY106Z016A,
2 x lo-uF, 16-V, YSV
muRata,
GRM23SY106Z016A,
4 x 1G-uF, 16-V, YSV
muRata.
GRM235Yl06Z016A,
6 x lo-uF, 16-V, YSV
muRata,
GRM23SY106Z016A,
6 x lG-uF, 16-V, YSV
Ll01
Inputlilter
inductor
CoilCraft,
D01607C-1S2,
1.5-uH,2.1-A
CoilCraft,
D01B13HC-122,
1.2-uH,4.4-A
CoilCraft,
D01B13HC-I22,
1.2-uH, 4.4-A
CoilCraft,
D03316P-1S2HC,
1.5-uH,9.o-A
CoilCraft,
DOI613HCP-S61,
0.56-uH, 6-A
Vlshay-Dale,
Vishay-Dale,
Output lilter
inductor
CoilCraft,
Ll02
Rl01
High-side gate
resistor
Rl02
IHLP~050CE-XX,
IHLP~OSOCE-XX,
0.6B-uH, 12-A
0.B2-uH,I6-A,
New product
O.5-uH, 25-A,
New product
10.0-Ohm,
l/1B-W,S%
lO.o-Dhm,
l/1B-W,S%
2 x 10.o-Dhm,
1/1B-W,5%
2 x 10.o-Dhm,
1I1B-W, S%
Lo-side gate
resistor
3.3-Ohm,
1/16-W, S%
3.3-0hm,
1116-W,5%
2x3.3-0hm,
3x3.3-0hm,
1/16-W,S%
1/16-W,S%
Rl03
Snubber resistor
2.7-Ohm,
1I1o-W, 5%
2.7-Ohm,
Il1o-W,5%
2x2.7-Ohm,
Il1o-W,5%
3x2.7-Ohm,
Il1o-W,5%
0101
Power switch
IR,IRF7Bl1,
NMOS, ll-mOhm
IR, IRF7Bll,
NMOS, ll-mOhm
IR, 2 x IRF7Bll,
NMOS, 11-mOhm
IR, 2 x IRF7Bll,
NMOS, l1-mOhm
0102
Synchronous switch
IR, IRF7Bl1,
NMOS, ll-mOhm
IR,IRF7Bll,
NMOS, l1-rnOhm
IR,2xIRF7Bl1,
NMOS, l1-mOhm
IR, 2 x IRF7Bl1,
NMOS, ll-mOhm
D03316P~61HC,
Nominallrequencyt
700 KHz
Hysteresis window
20mV
t Nominal frequency measured With Vo set to 2 v.
The values listed above are recommendations based on actual test circuits. Many variations of the above are
possible based upon the desires and/or requirements of the user. Performance of the circuit is equally, if not
more, dependent upon the layout than on the specific components, as long as the device parameters are not
exceeded. Fast-response, low-noise circuits require critical attention to the layout details. Even though the
operating frequencies of typical power supplies are relatively low compared to today's microprocessor circuits,
the power levels and edge rates can cause severe problems both in the supply and the load. The power stage,
having the highest current levels and greatest dv/dt rates, should be given the greatest attention.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-f37
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243-SEPTEMBER 1999
APPLICATION INFORMATION
frequency calculation
The simplified equation shown below can be used for a preliminary frequency calculation:
f :::
S -
V
x(V-V
)
REF
I
REF
x 0 85
VI x R11 x C7 x Hysteresis Window
.
(1)
High frequency operations require special attention not to exceed maxium current through the controller
(120mA), and the maximum total power dissipation.
1400
1300
1200
1100
1000
Fmall(D) 900
kHz 800
kHz
,
"
FmaxWlth
External Driver
I
I
"
I
~
/
600
/
500
400
I
I
/
SOD
200
100
I
I
/
700
Fm(D)
....... ~-
..4!-
,/
I
I
I
00
~
~
U
"
FmaxWlth
Internal Driver
"'
\
\.
\.
I
1
MUM
\.
\
U
M
\
,
U
D
Figure 19
Another restriction relates to the maximum rms current through the output of the highside driver, (11 OmA.) The
maximum allowable operating frequency can be defined by the following equation:
Fmax
=
(110mA)2 x 600hm)
Og x (VI
+
(2)
Vdrv)
Where Og = Total gate charge of the upper FETs in the hysteretic converter (in nanocoulombs)
Vdrv 8 V and is the drive regulator voltage of the TPS5211 controller
VI Input voltage
Fmax = Maximum switching frequency in kHz
=
=
Figure 19 and equation (2) should be used to determine the maximum operating frequency of a converter. The
operating frequency should not exceed the lower of the two values determined by Figure 19 and equation (2).
~TEXAS
7-88
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 - SEPTEMBER 1999
APPLICATION INFORMATION
Control Section
Below are the equations needed to select the various components within the control section.
output voltage selection
The most important function of the power supply is to regulate the output voltage to a specific value. Values
between 1.3 V and 3.5 V can be easily set by shorting the correct VID inputs to ground. Values above the
maximum reference voltage (3.5 V) can be set by setting the reference voltage to any convenient voltage within
its range and selecting values for R2 and R3 to give the correct output. Select R3:
R3 « than VREF/IBIAS(VSENSE); a recommended value is 10 k.Q
Then, calculate R2 using:
or
These equations are accurate if R2«R11. If this condition is not fullfilled, the following equation must be used:
V
o --
V
REF
(1
+ R3
R2 x R11
)
x (R2 + R11)
Another soultion is to use O.l-I1F DC decoupling capacitor in series with R11. In such a case, R11 does not
influence the output voltage value.
R2 and R3 can also be used to make small adjusts to the output voltage within the reference-voltage range
and/or to adjust for load-current active droop compensation. If there is no need to adjust the output voltage, R3
can be eliminated. R2, R3 (if used), and C7 are used as a noise filter; calculate using:
C7 =
150 ns
(R2 II R3)
slowstart timing
Siowstart reduces the startup stresses on the power-stage components and reduces the input current surge.
Siowstart timing is a function of the reference-voltage current (determined by R6) and is independent of the
reference voltage. The first step in setting slowstart timing will be to determine R6:
R6 should be between 7 k.Q and 300 kn, a recommended value is 20 k.Q.
Set the slowstart timing using the formula:
C5
=
tss
:::
tss
(5 x RVREFB) - (5 x R6)
Where C5 = Siowstart capacitance in I1F
tss Siowstart timing in I1S
RVREFB = Resistance from VREFB to GND in ohms ('" R6)
=
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-a9
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243-SEPTEMBER 1999
APPLICATION INFORMATION
hysteresis voltage
A hysteretic controller regulates by self-oscillation, thus requiring a small ripple voltage on the VSENSE pin
which the input comparator uses for sensing. Once selected, the TPS5211 hysteresis is proportional to the
reference voltage; programming Vref to a new value automatically adjusts the hysteresis to be the same
percentage ofVref. Since the output currentfrom VREFB should be less than 500 !lA, the total divider resistance
(R5 + R6) should be greater than 7 KO. The hysteresis voltage should be no greater than 60 mV so R6 will
dominate the divider.
VREFB
Hysteresis Window
=2 x VR5
R5
VHSYT
R6
Figure 20. Hysteresis Divider Circuit
The upper divider resistor, R5, is calculated using:
Hysteresis Window
x R6 '" V HYST (%) x R6
Hysteresis Window )
- (2 x 100)
R5 =
(2 x VREFB -
Where Hysteresis Window = The desired peak-to-peak hysteresis voltage
VREFB Selected reference voltage
VHYST (%) [(Hysteresis Window)NREFBl * 100 < VO(Ripple)(P-P) (%)
=
=
current limit
Current limit can be implemented using the on-resistance of the upper FETs as the sensing elements. Select
R8:
R8«
::;
VocP
IBiss(OCP)
0.1V
::; 10 kO
(100 x 100 nA)
(A recommended value is 1 kO)
The lOUT signal is used to drive the current limit and droop-circuit dividers. The voltage at lOUT at the output
current trip point will be:
(2x ROS(ON) x TF)
V/OUT(Trip)
=
NumFETs
x
100TriP)
=
Where NumFETS Number of upper FETS in parallel
TF = RDS(ON) temperature correction factor
IO(Trip) = Desired output current trip level (A)
~TEXAS
7-90
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 - SEPTEMBER 1999
APPLICATION INFORMATION
Calculate R7 using:
R7 =
(VI~~;(~riP) _
1)
x RS
Note that since ROS(ON) of MOSFETs can vary from lotto lot and with temperature, tight current-limit control (less
than 1.5 x 10) using this method is not practical. If tight control is required, an external current-sense resistor
in series with the drain of the upper FET can be used with HISENSE and LOSENSE connected across the
resistor.
droop compensation
Active voltage droop positioning is used to reduce the output voltage range during load transients by increasing
the output voltage setpoint toward the upper tolerance limit during light loads and decreasing the voltage
setpoint toward the lower tolerance limit during heavy loads. This allows the output voltage to swing a greater
amount and still remain within the tolerance window. The maximum droop voltage is set with R9 and R10.
Select R10:
R1 0 «
V DROOP(Min)
$;
IBias(DROOp,Max)
0.01 V $ ; 1 ill
(100 x 100 nA)
(Again, a value of 1 kQ is recommended)
The voltage at lOUT during normal operation (0 to 100% load) will vary from 0 V up to:
(2 x RDS(ON) x TF)
V'OUT(Max)
Where 10(Max)
x
NumFETs
=
IO(Max)
=Maximum output load current (A).
droop compensation (continued)
Then, calculate R9:
R9 = (V10UT(Max) _ 1) x R10
VOROOP
Where VOROOP
= Desired droop voltage
At full load, the output voltage will be:
Vo = V REF x
(1 + =~) -
VOROOP
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303. DALLAS. TEXAS 75265
7-91
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 - SEPTEMBER 1999
APPLICATION INFORMATION
using the TPS5211 when both 12 V and 5 V are available
When both 12 V and S V are available, several components can be removed from the basic schematic shown
in Figure 18. R1, R4, and C9 are no longer required if S V is brought in directly to INHIBIT and LODRV. However,
if undervoltage lockout for the S-V input is desired, R1 and R4 can be used to set the startup setpoint. The
INHIBIT pin trip level is 2.1 V. Select R4:
R4«
V,NH
I'NH(Max)
S
2.1V
S 210kQ
OOOx100nA)
Then, set the S-V UVLO trip level with R1:
R1=
(5 Vmp - 2V)
2V
xR4
iR1
5 V IN
LODRV
INHIBIT
R4
Figure 21. S-V Input With UVLO
~TEXAS
7-92
INSTRUMENTS
POST OFACE BOX 655303 • DALLAS, TEXAS 75?65
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243- SEPTEMBER 1999
APPLICATION INFORMATION
using the TPS5211 when only 5 V is available
The TPS5211 controller requires 12 V for internal control of the device. If an external source for 12 V is not
available, a small onboard source must be included in the design. A simple boost circuitry is described in Tis
application report AN452 Providing a DSP Power Solution from +5 V or +3.3 V only Systems. Total 12-V current
depends on switching frequency and power FETs gate charge characteristics. For reliable operation, this
current should not exceed 120 rnA. The power stage is not voltage dependent, but component values must be
selected for 5-V inputs. The frequency of operation is dependent upon the power stage input voltage. A typical
5-V only application circuit is shown in Figure 22.
L101
L102
--
,.....
--
5Vr
Q101
~~
C1~ r-:
R101
•
GN D
i-
R102
Vo
~ R103
~
C10~ r-: C10; '"
:;;: '" C102
J
*"
r---
,---J
roo--
Power Stage
RTN
-- -r-,r----- ----------r- --r-- r--- - - - --- ----Control Sectio
Z
0
~
isa
Q
:I:
Cl
:I:
IIIZ
W
g
0.....
i
In
ID----
Boo.t112~
Circuitry
I
!!! ~
II..
o .....
0
.....
W
~
Q
VCC
16 BOOT
R~.
150
DRV 14
LOWDR 13
R11
7.5k
ui!
:;;:
~PF
_ - --2. VID3
_ --A VID2
_ -..A VID1
_ -....J1
'I
VREFB 5
DROOP
PWRGD
lOUT
2
II
~r
C4
f - - 1 uF
1/
1\
C51f
0.1 uF 1\
C711
1000pFI\
R310.0 k
~~
100
VHYST 4
OCP 3
VIDO
>
W
~
ENA BLE'"
In
~
17 HIGHDR DRVGND 1L18
LOHIB .!LBOOTLO
19
LODRV
HISENSE
20
BIAS 9
LOSENSE
CSII
21
SLOWST 8
10UTLO
O.033uFI\
22
INHIBIT ANAGND 7
(see Note
A) 23
.... _.--..=.
VSENSE 6
VID4
R1
10.0 k < 1%
Ii:
W
Z
1:t
C3\1
In
Z
In
C2
15
W
:1:1
:I: Q
1 uF
1
R4 •
11.0 k <
1%
Z
C~1e
:I:
f2-V
Q
R] ,~92k
R6.'v
I
2O.0k
I
R8
1.0,~k
'v
V'A
R9Y 4.32k
TPS5211
U1
I
R10
1.00 k
NOTE A. VIDO - VID4 User - selected to set output voltage.
Figure 22. Typical S-V-Only Application Circuit
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-93
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243-SEPTEMBER 1999
APPLICATION INFORMATION
controller operation
Operation of the TPS5211 controller differs from a regular hysteretic controller. The additional ramp signal
through the input of the hysteretic comparator is formed by R11 and C7. The two signals are summed through
the inputs of the comparator. The two signals are the ramp signal from R11 - C7 circuitry and the signal from
the output converter. By proper selection of R 11 and C7, one can get the amplitude of an additional ramp signal
which is greater than the output ripple of the conver\er. As a result, the switching frequency is greater while the
output ripple becomes lower. The additional ramp signal and output ripple waveforms are shown in Figure 23.
The switching frequency now depends on R11 and C7 values and does not depend on the output filter
characteristics including ESR, ESL, and C of the output capacitor (see frequency calculation section).
The dc feedback signal from the output of the converter through resistor R2 controls the dc level of the output
voltage. Because the switching frequency of TPS5211 is high and it does not depend on output capacitor
characteristics, low cost cermic or film capacitors can be used in a dc to dc converter while having the same
load current transient response characteristics.
(VHI- VLO) - Hysteresis Window
(VMAX - VMIN) - Overshoot
Because of Delays
Additional Ramp..signal
Output Ripple
Figure 23. The Additional Ramp-Signal and Output Voltage Ripple Waveforms
~TEXAS
7-94
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 - SEPTEMBER 1999
APPLICATION INFORMATION
application examples
Below are waveforms and test results measured on the EVM for a 12-V input and a 2-V, 20-A output application.
The output voltage ripple and power switches midpoints are shown in Figure 24. The converter operates at 450
kHz. The 'peak to peak output ripple is 9.6 mY, while the hysteresis window is set at 20 mY. Therefore, the output
ripple for converter with TPS5211 is much lower than the hysteresis window.
Tek _
2S.0MSls
[I
152 ACQS
T
II
C1 Freq
44U8kHz
Output Voltage
Ripple (20 mV/div)
C3 Pk-Pk
UmY
LowFET
Drain-Source
Voltage (5 V/dlv)
25Aug IIDD
14:05:13
Figure 24. The Output Voltage Ripple ans Low FET Drain-Source Voltage Waveforms
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-95
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243-SEPTEMBER 1999
APPLICATION INFORMATION
The load current transient response waveforms are shown in Figure 25 to illustrate the excellent load current
transient response characteristics of TPS5211.
Tlk_ 5.00MS/s
[I
OUtput Voltage
(100 mV/dlv)
1879 Acqs
T
II
..
., .
..............................
...... .
.. .. . .
.
. ..
C3 Pk-Pk
156mV
Load Current
(10 Aldlv)
LowFET
Drain-Source Voltege
(10 V/dlv) "'11J,JJ,I\,1\IIJIol~1-4J\,I.I\III\oIU .fI1~L...f_"""'....;...,j WI...I,L.I;\,J.uu.q
25 Aug 1999
14:17:28
Figure 25
The output voltage transient response of the converter with TPS5211 controller. The load current has 14 A step
with slew rate of 30 A/IlS.
~TEXAS
7-96
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 - SEPTEMBER 1999
APPLICATION INFORMATION
Comparison of TPS5210 and TPS5211 controller applications
The TPS5210 and TPS5211 hysteretic controllers have excellent load current transient response
characteristics, which is one of the most important advantages of hysteretic mode. There are specific
application areas where one of the hysteretic controllers is preferable over the other. The table below gives a
comparative view on application areas for the TPS5210 and TPS5211 controllers
comparison of TPS521 0 and TPS5211 applications
Controller
Switching frequency, kHz
Frequency variation
TPS5210
TPS5211
100-400
400-700
Depends on outout filter characteristics
Independent of output filter and easy to
evaluate
Output current, A
up to 40
up to 18 - 20 (can be increased in multiphase configuration)
Efficiency, % (depends on frequency, output current, Vin, Vout, components, etc.)
85-95
75-85
Surface-mount ceramic and POSCAP
type capacitors and 40% - 65% smaller
Inductors.
Input and output filter
Requires bulk electrolytic capacitors especially If lout> 12A and larger inductor
Component Cost
20% - 40% lower for TPS5211
System cost Including reliability, power losses,
cooling, etc.
Can be estimated only during design for a given specifiC application.
Layout and design
Special attention to the noise sensitive
places such es the hysteresis comparator
and the. sample hold circuitry.
Special attention not to exceed frequency
and Icc limits. The high frequency dc dc converter design rules should be
used.
Compatibility with the whole system
For high current applications, it is difficult to
meet high density minimum size requirements.
A de - dc converter can be placed close
to the microprocessor or DSP to decreese the number of decoupling capacitors.
~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-97
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243-SEPTEMBER 1999
APPLICATION INFORMATION
layout guidelines
Good power supply results will only occur when care is given to proper design and layout. layout will affect noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult
than most general PCB design. The general design should proceed from the switching node to the output, then
back to the driver section, and, finally, to placing the low-level components. Below are several specific points
to consider before layout of a TPS5211 design begins.
1.
All sensitive analog components should be referenced to ANAGND. These include components connected
to SlOWST, DROOP, lOUT, OCP, VSENSE, VREFB, VHYST, BIAS, and lOHIB.
2.
Analog ground and drive ground should be isolated as much as possible. Ideally, analog ground will connect
to the ground side of the bulk storage capacitors on Va, and drive ground will connect to the main ground
plane close to the source of the low-side FET.
3.
Connections from the drivers to the gate of the power FETs, should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
4.
The bypass capacitor for the DRV regulator should be placed close to the TPS521 0 and be connected to
DRVGND.
5.
The bypass capacitor for Vee should be placed close to the TPS521 0 and be connected to DRVGND.
6.
When configuring the high-side driver as a floating driver, the connection from BOOTlO to the power FETs
should be as short and as wide as possible. The other pins that also connect to the power FETs, lOHIB
and lOSENSE, should have a separate connection to the FETS since BOOTlO will have large peak
currents flowing through it.
7.
When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from BOOT
to BOOTlO) should be placed close to the TPS521 O.
8.
When configuring the high-side driver as a ground-referenced driver, BOOTlO should be connected to
DRVGND.
9.
The bulk storage capacitors across VI should be placed close to the power FETS. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
C
10. High-frequency bypass capacitors should be placed across the bulk storage capacitors on Va.
11. HISENSE and lOSENSE should be connected very close to the drain and source, respectively, of the
high-side FET. HISENSE and lOSENSE should be routed very close to each other to minimize
differential-mode noise coupling to these traces. Ceramic decoupling capacitors should be placed close to
where HISENSE connects to Vin, to reduce high-frequency noise coupling on HISENSE.
~TEXAS
7-98
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS5615,TPS5618,TPS5625,TPS5633
SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER
1998 - REVISED NOVEMBER 1998
PWPPACKAGE
(TOP VIEW)
• ±1% Reference Over Full Operating
Temperature Range
• Synchronous Rectifier Driver for >90%
Efficiency
1 0
28
2
27
26
3
4
25
r----,
5 I
124
6
1 23
7 I
22
I
I
21
8
9 I
1 20
lOUT
AGND2
OCP
VHYST
VREFB
VSENSE
ANAGND
SlOWST
BIAS
lODRV
lOHIB
DRVGND
lOWDR
DRV
• Fixed Output Voltage Options of 1.5 V,
1.8 V, 2.5 V, and 3.3 V
• User-Selectable Hysteretic-Type Control
• Low Supply Current ... 3 mA Typ
• 11.4-V to 13-V Input Voltage Range, Vee
• Power Good Output
• Programmable Soft-Start
• Overvoltage/Overcurrent Protection
• Active Deadtime Control
description
10 IL _ _ _ .JI 19
18
17
16
15
11
12
13
14
PWRGD
NC
NC
NC
NC
NC
INHIBIT
IOUTlO
lOSENSE
HISENSE
BOOTlO
HIGH DR
BOOT
Vee
Ne - No internal connection
The TPS5615 family of synchronous-buck regulator controllers provides an accurate supply voltage to DSPs.
The output voltage is internally set by a resistive divider with an accuracy of 1% over the full operating
temperature range. A hysteretic controller with user-selectable hysteresis is used to dramatically reduce
overshoot and undershoot caused by load transients. Propagation delay from the comparator inputs to the
output drivers is less than 250 ns. Overcurrent shutdown and crossover protection for the output drivers
combine to eliminate destructive faults in the output FETs. PWRGD monitors the output voltage and pulls the
open-collector output low when the output drops below 93% ofthe nominal output voltage. An overvoltage circuit
disables the output drivers if the output voltage rises 15% above the nominal value. The inhibit pin can be used
to control power sequencing. Inhibit and undervoltage lockout assures that the 12-V supply voltage and system
supply voltage (5 V or 3.3 V) are within proper operating limits before the controller starts. The output driver
circuits include 2-A drivers with internal S-V gate-voltage regulators that can easily provide sufficient power for
today's high-powered DSPs. The high-side driver can be configured either as a ground-referenced driver or as
a floating bootstrap driver. The TPS5615 family is available in a 28-pin TSSOP PowerPad™ package. It operates
over a junction temperature range of O°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
TJ
OUTPUT VOLTAGE
TSSOpt
(PWP)
1.5 V
TPS5615PWP
DoC to 125°e
t The PWP package
1.8 V
TPS5618PWP
2.5V
TPS5625PWP
3.3V
TPS5633PWP
avallble taped and reeled. Add R suffiX to
device type (e.g., TPS5615PWPR).
A.
~
IS
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 199B, Texas Instruments Incorporated
7-99
TPS5615,TPS5618,TPS5625,TPS5633
SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER
SLVSlnA - SEPTEMBER 1998 - REVISED NOVEMBER 1998
functional block diagram
7
ANAGND
28
20
PWRGD LOSENSE
21
19
IOUTLO
HISENSE
J
22------'"""'"
1
INHIBrr
lOUT
3
OCP
Vee
VSENSE
Analog
Bias
PREREG
Analog
BI••
9
.
SL~
BIAS
14
DRV
16
BOOT
17
HIGHDR
18
BOOTLO
VREF
13
LOWDR
r
AOtfD2
VRIFB
VH4ST
VSE,",SE
~TEXAS
7-100
INSTRUMENTS
POST OFFICE BOX 656303 • DALlAS, TEXAS 75265
11
LOHIB
10
LODRV
TPS5615, TPS5618, TPS5625, TPS5633
SYNCHRONOUS-SUCK HYSTERETIC REGULATOR CONTROLLER
SLVS1nA - SEPTEMBER 1998 - REVISED NOVEMBER 1998
Terminal Functions
TERMINAL
NAME
NO.
DESCRIPTION
1/0
AGND2
2
Analog ground (must be connected).
ANAGND
7
Analog ground
BIAS
9
Analog bias pin. A 1-ILF capacitor should be connected from BIAS to ANAGND.
BOOT
16
Bootstrap. A 1-ILF capacitor should be connected from BOOT to BOOTlO.
BOOTlO
18
Bootstrap low. Connect to the junction of the high-side and low-side FETs for floating drive configuration.
Connect to PGND for ground-reference drive configuration.
DRV
14
Drive regulator for the FET drivers. A 1-ILF capacitor should be connected from DRV to DRVGND.
DRVGND
12
Drive ground. Ground for FET drivers. Connect to FET PWRGND.
HIGHDR
17
High drive. Output drive to high-side power switching FETs.
HISENSE
19
High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs;
for optional current sensing scheme, connect to power supply side of current-sense reSistor placed in series
with high-side FET drain.
INHIBIT
22
Disables the drive signals to the MOSFET drivers. Also serves as UVlO for system logic supply (3.3 V or
5 V). An extemal pull-up resistor should be connected to system-logic supply.
lOUT
1
Current out. Output voltage on this tenninal is proportional to the load current as measured across the
Rds(on) olthe high side FET. The voltage on this tennlnal equals 2 x RDS(ON) x lOUT. In applications where
very accurate current-sensing is required, a sense resistor should be connected between the input supply
and the drain of the high-side FETs.
IOUTlO
21
Current sense low output. This is the voltage on the lOSENSE tanninal when the high-side FETs are on.
A ceramic capacitor (between 0.0331LF and 0.1ILF) should be connected from IOUTlO to HISENSE to hold
the sensed voltage.
lODRV
10
low drive enable. Normally tied to 5 V. To configure the low-side FET as a crowbar, pull lODRV low.
lOHIB
11
low side Inhibit. Connect to the junction of the high- and low-side FETs to control the anti-crossconduction and eliminate shoot-through current. Disabled when configured in crowbar mode.
lOSENSE
20
low current sense. For current sensing across high-side FETs, connect to the sourca of the high-side FETs;
for optional current sensing scheme. connect to high-side FET drain side of current-sense resistor placed
in series with high-side FET drain.
lOWDR
NC
13
23--27
low drive. Output drive to synchronous rectifier FETs.
No connect
OCP
3
Over current protection. Current limit trip point is set with a resistor divider between lOUT and ANAGND.
PWRGD
28
Power good. PWRGD signal goes high when output voltage is within 7% of voltage setpoint. Open-drain
output.
SlOWST
8
Slow Start (soft start). A capacitor fonn SLOWST to ANAGND sets the slowstart time.
Siowstart current IVREFs/5
VHYST
4
HystereSis set input. The hysteresis is set with a resistor divider from VREFB to ANAGND.
Hysteresis 2 x (VREFB - VHYST)
VCC
VREFB
15
12-V supply. A 1-ILF capacitor should be connected from VCC to DRVGND.
5
Buffered reference voltage
VSENSE
6
Voltage sense Input. To be connected from converter output voltage bus to sense and control output voltage.
It is recommended that a RC low-pass filter be connected at this pin to filter noise.
=
=
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303- OALlAS, TEXAS 75265
7-101
TPS5615, TPS5618,TPS5625, TPS5633
SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER
SLVS177A - SEPTEMBER 1998 - REVISED NOVEMBER 1998
detailed description
Vref
The reference voltage section consists of a temperature-compensated bandgap reference and a resistive
divider that sets the output voltage option. The output voltage, VREF, is within 1% of the nominal setting over
the full junction temperature range of O°C to 125°C, and a Vee supply voltage range of 11.4 V to 12.6 V. The
output of the reference network is indirectly brought out through a buffer to the VREFB pin. The voltage on this
pin will be within 2% of VREF. It is not recommended to drive loads with VREFB, other than setting the hysteresis
of the hysteretic comparator, because the current drawn from VREFB sets the charging current for the slowstart
capacitor. Refer to the slowstart section for additional information.
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by 2 external resistors and is centered on VREF. The 2 external resistors form a resistor divider from VREFB
to ANAGND, with the output voltage connecting to the VHYST pin. The hysteresis of the propagation delay from
the comparator inputs to the driver outputs is 250 ns (maximum). The maximum hysteresis setting is 60 mY.
IO(MAX} = 0.5 I1A
VREFB -
?
VHYST
R2 x V H
Rt = 2 x VREFB-VH
R1
~
Where
VH
TPS56xx
=desired hysteresis voltage
~ R2
Figure 1. Setting the Hysteresis Voltage
low-side driver
The low-side driver is designed to drive 10W-Rds(on) n-channel MOSFETs. The current rating of the driver is 2
A, source or sink. The bias to the low-side driver is internally connected to the DRV regulator.
high-side driver
The high-side driver is designed to drive 10W-Rds(on) n-channel MOSFETs. The current rating of the driver is 2
A, source or sink. The high-side driver can be configured either as a ground-referenced driver or as a floating
bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from the DRV
regulator. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved
drive efficiency. The maximum voltage that can be applied between BOOT and DRVGND is 30 V. The driver
can be referenced to ground by connecting BOOTlO to DRVGND, and connecting BOOTto either DRV or Vee.
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side driver is not allowed
to turn on until the gate-drive voltage to the low-side FET is below 2 V; the low-side driver is not allowed to turn
on until the voltage at the junction of the 2 FETs (Vphase) is below 2 V.
~TEXAS
7-102
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5615,TPS5618,TPS5625,TPS5633
SYNCHRONOUS·BUCK HYSTERETIC REGULATOR CONTROLLER
SLVS177A - SEPTEMBER 1998 - REVISED NOVEMBER 1998
detailed description (continued)
current sensing
Current sensing is achieved by sampling and holding the voltage across the high-side power FET while the
high-side FET is on. The sampling network consists of an internal 60-n switch and an external ceramic hold
capacitor. Recommended value of the hold capacitor is between 0.0331lF and 0.1 IlF. The actual value should
give a time constant (60 n x CH) greater than the FET on time. Internal logic controls the turn-on and turn-off
of the sample/hold switch such that the switch does not turn on until the Vphase voltage transitions high, and
the switch turns off when the input to the high-side driver goes low. Thus sampling will occur only when the high
side FET is conducting current. The voltage on the lOUT pin equals 2 times the sensed high-side voltage. In
applications where a higher accuracy in current-sensing is required, a sense resistor can be placed in series
with the high-side FET and the voltage across the sense resistor can be sampled by the current sensing circuit.
See Figures 2 and 3.
overcurrent protection
The overcurrent protection (OCP) circuit monitors the current through the high-side FET. The overcurrent
threshold is adjustable with an external resistor divider between lOUT and ANAGND, with the divider voltage
connected to OCP. If the voltage on OCP (VS) exceeds 100 mV, then a fault latch is set and the output drivers
are turned off. The latch will remain set until Vee goes below the undervoltage lockout value. A 3-IlS deglitch
timer is included for noise immunity. The OCP circuit is also designed to protectthe high-side power FET against
a short-to-ground fault on the terminal common to both power FETs (Vphase).
--t~ .=-i~t-----
vp
Vp
2*VS
2*VS
lOUT
R1
R1
OCP
OCP
TPS56xx
TPS56xx
R2
Rl =
R2 x (VS~.05)
0.05
R2
Rl =
Figure 2. OCP Using FET ON-Resistance
R2 x (VS~.05)
0.05
Figure 3. Precision OCP Using External Resistor
Inhibit
INHIBIT is a TTL-compatible digital input used to enable the controller. When INHIBIT is low, the output drivers
are low and the slowstart capacitor is discharged. When INHIBIT goes high, the short across the slowstart
capacitor is rel~ased and normal converter operation begins. When the system-logic supply is connected to
INHIBIT, it also controls power sequencing by locking out controller operation until the system-logic supply
exceeds the input threshold voltage of the inhibit circuit. Thus the 12-V supply and the system-logic supply
(either 5 V or 3.3 V) must be above UVLO thresholds before the controller is allowed to start up. The INHIBIT
comparator start threshold is 2.1 V and the hysteresis is 100 mV.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-103
TPS5615, TPS5618, TPS5625, TPS5633
SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER
sLvs1nA - SEPTEMBER 1998 - REVISED NOVEMBER 1998
detailed description (continued)
Vee
---- 10.75 V at startup,
See Note 2
3
VINHIBIT = 5 V,
VBOOTLO = 0 V,
CLOWOR = 50 pF,
VCC> 10.75 V at startup,
CHIGHOR = 50 pF,
fswx = 200 kHz
5
VINHISIT = 5 V,
VBOOT=13V,
CHIGHOR = 50 pF,
Vee> 10.75 V at startup,
VBOOTLO = 0 V,
fswx = 200 kHz
V
mA
VINHIBIT = 0 V or VCC < 9.25 V at startup,
VBOOT=13V, VSOOTLO=OV
High-side drive regulator quiescent current
UNIT
10
2
~
mA
NOTE 2: Ensured by design, not tested.
~TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS. TEXAS 75265
7-109
TPS5615, TPS5618, TPS5625, TPS5633
SYNCHRONOUS·BUCK HYSTERETIC REGULATOR CONTROLLER
SLVS177A - SEPTEMBER 1998 - REVISED NOVEMBER 1998
switching characteristics over recommended operating virtual Junction temperature range,
Vee =12 V,IORV =0 V (unless otherwise noted)
PARAMETER
Propagation delay
TEST CONDITIONS
VSENSE to HIGHDR or
LOWDR (excluding deadtlme)
Overdrive = 10 mV (see Note 2)
MAX
UNIT
150
250
ns
OCP comparator
See Note 2
See Note 2
1
PWRGD comparator
See Note 2
1
1
Overdrive = 10 mV (see Note 2)
HIGHDR output
CL=9 nF,
VBOOTLO = 0 V,
VBOOT = 6.5 V,
TJ = 125°C
LOWDR output
CL=9 nF,
TJ = 125°C
VDRV=6.5V,
HIGHDR output
CL= 9 nF,
VBOOTLO = 0 V,
VBOOT = 6.5 V,
TJ = 125°C
LOWDR output
CL=9nF,
TJ = 125°C
VDRV=6.5V,
OCP
See Note 2
2
5
OVP
See Note 2
2
5
High-side VDS sensing
560
900
ns
60
60
ns
60
VHISENSE = 12 V,
VIOUTLO pulsed from 12 V to 11.9 V,
100 ns rlsellall times, See Note 2
2
VHISENSE = 4.5 V,
VIOUTLO pulsed from 4.5 V to 4.4 V,
100 ns risellall times, See Note 2
a
a
Short-circuit protection rislngedge delay
SCP
Tum-onltum-oll delay
VDS sensing sample/hold
switch
Crossover delay time
LOWDR to HIGHDRV, and
LOHIB to LOWDR
See Note 2
Prefilter pole frequency
Hysteretic comparator
See Note 2
Propagation delay
LODRV
See Note 2
LOSENSE = 0 V,
a v:s; VHISENSE:S; 11 V,
VLOSENSE = VHISENSE
(see Note 2)
NOTE 2: Ensured by design, not tested.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
lIS
lIS
a
a
(see Note 2)
ns
60
VHISENSE = V,
VIOUTLO pulsed from V to 2.9 V,
100 ns risellall times, See Note 2
7-110
lIS
SLOWST comparator
Fall time
Response time
TVP
OVP comparator
Rise time
Deglltch time (Includes
comparator propagation
delay)
MIN
300
500
ns
ao
100
ns
ao
100
ns
MHz
5
400
ns
TPS5615, TPS5618, TPS5625, TPS5633
SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER
SLVS177A- SEPTEMBER 1998- REVISED NOVEMBER 1998
TYPICAL CHARACTERISTICS
SLOWSTART TIMING
100
SLOWSTART TIMING
vs
vs
CAPACITANCE
VREFB CURRENT
1000
:: VREFB=2V
~VREFB) = 100llA
(SLOWST) = 0.1 I1F
TJ = 25°C
=
~
10
VREFB =2V
C(SLOWST) = 0.111F
TJ = 25°C
V
I
~
1=
V
Ii:
~
~
Ul
/
0.1
o
0.0001
0.001
0.01
0.1
10
Capacitance -I1F
Figure 5
OUTPUT DRIVER FALL TIME
vs
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
1000
'I
III
C
High Side Drivar
r--
I
CD
E
1/
:!
1\
I
CD
E
II.
1=
CD
1=
~~
.!!!
II:
I
1000
Figure 6
OUTPUT DRIVER RISE TIME
100
100
I(VREFB) - VREFB Current -1lA
10
~
Low Side Driver
'5
~
-.
1==
~
"C
-
High Side Driver
C
L
V V~
'5
""
1/
0
100
~
0
10
-...
I
Low Side Driver
I
1
0.1
10
1
100
0.1
CL - Load Capacitance - nF
10
100
CL - Load capacitence - nF
Figure 7
FigureS
~TEXAS
INSTRUMENTS
7-111
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
~~-----~~-----~-.
----
TPS5615, TPS5618,TPS5625, TPS5633
SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER
SLVS177A - SEPTEMBER 1998 - REVISED NOVEMBER 1998
TYPICAL CHARACTERISTICS
OCP THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
OVP THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
,---,---r---r---........- -......
118
,---,---r---r---........- -......
105
117
I---t---+--+---+--------l
103 t---+--+--+--~---I
116 t---+--+--+--~---l
115
~=+==+==t:==±=:::l
114 t - - - t - - - + - - + - - - l - - - - - l
I
t
1011-----+---+--+---l-------l
j
99t---+--+--+--~---I
--
~
:s!
D.
g
113 t---+--+--+--~---l
97 f - - - + - - + - - + - - - - - + - - - l
95~-~----~--~----~--~
100
125
75
o
25
50
112~-~--~---L--~--~
100
125
o
25
50
75
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 10
Figure 9
INHIBIT HYSTERESIS VOLTAGE
vs
JUNCTION TEMPERATURE
INHIBIT START THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
2.1
,
>
I
CD
150
,----,-----,-----,-----r-------.
>
E
2.05
I
~
~
:s!
0
.c
.!!
~
.c
~
2 i---
I!
t:
aJ
t:
s:
100
r--
t
:c
l-
III
125
CD
01
Iiis:
1.95
..............
-
~
-
~
75
i!i
i!i
1.90 '--_--I._ _-L-_ _.L-_---l_ _..J
100
125
75
o
25
50
50
o
TJ - Junction Temperature - °C
50
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
75
100
TJ - Junction Temperature - °C
Figure 12
Figure 11
7-112
25
125
TPS5615,TPS5618, TPS5625, TPS5633
SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER
SLVS177A - SEPTEMBER 1998 - REVISED NOVEMBER 1998
TYPICAL CHARACTERISTICS
UVLO HYSTERESIS VOLTAGE (Vee)
UVLO START THRESHOLD VOLTAGE Vee
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.5
....----,----,----,----r------.
2.3
1---1---+---+--+-----1
2.1
~=:j===+:::::::::~;:;:;;=T
10.5
>
>
I
I
,
-- ---
'0
.J'
.
r--- r---
10
~
~
~
.c
~
1:
9.5
(J
.J'
t~
Dl
....-1
!----
1.9 1 - - - - - 1 - - - + - - - + - - - - 1 - - - - - 1
1.7
1---1---+---+--+-----1
0
....I
>
::;)
1.5
9
o
25
100
75
50
TJ - JunctIon Temperature -
L..-_--I._ _....J.._ _-I-_ _-L-_----I
o
125
25
°e
Figure 13
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
95
6
0(
94
E
I
4
~
:::I
(J
C
j
2
:::I
C
o
125
PWRGD THRESHOLD VOLTAGE
vs
.J'
c
100
°e
Figure 14
QUIESCENT CURRENT Vee
(J
75
50
TJ - Junction Temperature -
--
~
------
93
25
----
~
92
91
90
o
~
50
100
75
TJ - JunctIon Temperature -
125
o
°e
Figure 15
25
50
75
TJ - Junction Temperature -
100
125
°e
Figure 16
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
7-113
TPS5615,TPS5618,TPS5625,TPS5633
SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER
SLVS177A - SEPTEMBER 1998 - REVISED NOVEMBER 1998
TYPICAL CHARACTERISTICS
VDS SAMPLE/HOLD RESISTANCE
vs
JUNCTION TEMPERATURE
SLOWSTART CHARGE CURRENT
vs
JUNCTION TEMPERATURE
100
15r----,-----r----~----~--~
c;
~
14~--_4----~----+_--~~--~
§
i b__--~....~~~=i~~~::::j
a
I
I
13 ~
~
6~
12~---+----~----+---~----~
j
11 ~--_4----~----+_----~--~
o
I
25
50
75
100
----
I~ ---g
125
o
25
50
100
75
125
TJ - Junction Temperature - DC
TJ - Junction Temperature - DC
Figure 17
Figure 18
DRIVE REGULATOR LOAD REGULATION
vs
JUNCTION TEMPERATURE
DRIVE REGULATOR OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
175
8.5
=e
>
I
f
~
25
o
10~--~----~----~--~~---J
o
75
I
c
i
8.25
~
::I
I
:;
~
0
I
8
Q
Ii!
!!
·c
Q
-
---
7.75
150
~.
.e
.!!
::I
I
125
V
!!
j§
I
/
V
/
/
>0
7.5
100
o
25
50
75
100
125
o
TJ - Junction Temperature - DC
Figure 19
50
INSTRUMENTS
POST OFFICE BOX 655300 • DALLAS, TEXAS 75265
75
100
TJ - Junction Temperature - DC
Figure 20
~TEXAS
7-114
25
125
TPS5615, TPS5618, TPS5625, TPS5633
SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER
SLVSl77A - SEPTEMBER 1998 - REVISED NOVEMBER 1998
TYPICAL CHARACTERISTICS
HIGH-SIDE DRIVER OUTPUT RESISTANCE
DRIVE REGULATOR LINE REGULATION
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
5
175
>
C;
I
I
S
c
E
C
I!il'
150
!
..
.e
:::i
..!!
=
DI
I.
125
~
V
100
o
V
/
V
V
II:
V
4
I
/
i
3
=
2
j§
~I
o
25
75
50
---
0
100
125
~
o
.....-
25
50
~
75
~
100
125
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 21
Figure 22
LOW-8IDE DRIVER OUTPUT RESISTANCE
vs
JUNCTION TEMPERATURE
6
cr
..
~..
I.
III
.-'"
5
C
4
'5
~
.!I!
0
j§
III
3
~
~
~
~
~
2
!!
1
....
o
o
25
50
75
100
125
TJ - Junction Temperature - °C
Figure 23
~TEXAS
INSTRUMENTS
POST OFACE BOX 655303 • DALLAS. TEXAS 75265
7-115
TPS5615, TPS5618, TPS5625,TPS5633
SYNCHRONOUS·BUCK HYSTERETIC REGULATOR CONTROLLER
SLVS177A-SEPTEMBER 1998- REVISED NOVEMBER 1998
APPLICATION INFORMATION
Synchronous rectifier buck regulator circuits are used where high efficiency and low dropout voltages are required.
The TPS56xx controller is useful in applications with very high transient loads and wide dc load ranges, such as
multiple-DSP applications.
The circuit below will meet a wide variety of applications with maximum continuous-rated output currents of up to 8 A.
Design tradeoffs, such as cost, size, or efficiency may need to be addressed for specific applications. Care should
be taken in the proper layout (see last section of this data sheet for specific layout guidelines), especially in the
higher-current configurations, to ensure that noise and ripple are kept to a minimum. Basic layout considerations are
discussed in the 1996 Power Supply Circuits Databook (Literature no. SLVD002). Design guidelines and equations
are discussed in Synchronous Buck Converter Design Using TPS56xx Controllers in SLVP10x EVMs User's Guide
(Literature no. SLVU007).
~TEXAS
7-116
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS5615,TPS5618,TPS5625,TPS5633
SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER
SLVS177A - SEPTEMBER 1998 - REVISED NOVEMBER 1998
APPLICATION INFORMATION
Z
II:
~
R7
11.0kn1%
R11
7500
II:
-,r
II
R9
10001%
U1
TPS5625
'-
...-j.~OOPF
R13
~I C160.1 uF
C17111F
II
C11
\1111F
II
Q
z
R8
1000<
1%
ic
-
C~~0.1I1F
R12
2O.0kn1%
CI
~
lOUT
3
AGND2
OCP
NC
NC
~
26
4
VHYST
NC
"25
--""--
5
6
7
8
9
NC
NC
INHIBIT
IOUTLO
LOSENSE
HISENSE
-#-23
--.!Q...
VREFB
VSENSE
ANAGND
SLOWST
BIAS
LODRY
11
12
LOHIB
DRVGND
BOOTLO
HIGHDR
18
17
-1!..
LOWDR
DRY
14
PWRGD
BOOT
VCC
)~
\1 C3 0.111F
II
C2
0.111F
C4
~\11I1F
/I R17
1}1
l"-
R2
10kn
22
21
20
19
C1
2211F
10V
R1
1.0kn
26
1
~
!.,
I
'---<~
\1
II
C14
0.0111F
jL
-
!., .,l .,'f .~,
'?
.,:I
R6
1.3kn
1 Mel
J
;:: [::;
\1 C7111F
C
R4
100
C18
t----1A~
02
SI4410
"1-
R16
4.70
R3
100 ~
rn 1 1 1 m
Z
CI
I
II.
II
41 C80.0111~A
II
R5
2.7D
\1 C9 820 I1F 4V
\1 C6 680 I1F 6.3 V
II
112.~H
- I~ .,!
.,:I
R15
4.70
L1
~r
I
"
SeeNoteA
L1 = 10T 1122 on T30-18 Core
L2 = 12T #20 on T44-8Core
Not Used:
R10, R13, R14
C13
(: C1010l1F
II
Q
01
SI4410
\1 C52.211F
Q
I~I~I~
~
I.., !..,~rl~
!.., ..,:r
G,
I
NOTE A. Theses two traces should be physically close to each other for good noise immunity.
Figure 24. Typical Design Schematic
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-117
TPS5615, TPS5618,TPS5625, TPS5633
SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER
SLVS177A - SEPTEMBER 1998 - REVISED NOVEMBER 1998
Table 1. Test Results for 2.5·V, a·A Converter
TEST
CONDITIONS
Oulpul vollage
VIN = 5.25 V,
10=8A
Load regulation
VIN = 5.25 V,
QTY
UNITS
2.50
V
10=0.8t08A
0.4
%
Line regulation
10 =6 A,
VCC =4.5 Vt06 V
0.2
%
Ripple
VIN = 5.25 V,
10=8A
50
mVpp
Efficiency
VIN = 5.25 V,
10=8A
89
%
Table 2. 2.5·V, a·A Converter Bill of Materials
REF DES
DESCRIPTION
PART NUMBER
QTY
MFG
Cl
1
10SS22M
Capacitor, Os-Con, 22IiF, 10 V, 20%
Sanyo
C2
4
GRM39X7Rl04K016A
Capacitor, Ceramic, 0.1 IiF, 16 V, 10%, X7R
muRata
GRM39X7Rl04K016A
Capacitor, Ceramic, 0.1 IiF, 16 V, 10%, X7R
muRata
muRata
C3
C4
4
GRM42-6Y5Vl05Z016A
Capacitor, Ceramic, 1 IiF, 16 V, +80%-20"k
C5
1
GRM42-6Y5V225Z016A
Capacitor, Os-Con, 2.2 IiF, 16 V, Y5U
muRata
C6
1
6SP680M
Capacitor, Os-Con, 680 IiF, 6.3 V, 20%
Sanyo
muRata
GRM42-6Y5Vl05Z016A
Capacitor, Ceramic, lliF, 16 V, +80%-20%
C8
2
GRM39X7Rl03K025A
Capacitor, Ceramic, O.Q1IiF, 25 V, 10%, X7R
muRata
C9
1
4SP820M
Capacitor, Os-Con, 820 IiF, 4 V, 20%
Sanyo
Cl0
1
C7
GRM235Y5Vl06Z016A
Capacitor, Ceramic, 10 IiF, 16 V, Y5V
muRata
Cll
GRM42-6Y5Vl05Z016A
Capacitor, Ceramic, lliF, 16 V, +800/0-20%
muRata
C12
GRM39X7Rl04K016A
Capacitor, Ceramic, 0.1 IiF, 16 V, 10%, X7R
muRata
C14
GRM39X7Rl03K025A
Capacitor, Ceramic, O.OIIiF, 25 V, 10%, X7R
muRata
GRM39X7Rl02K050A
Capacitor, Ceramic, 1000 pF, 50 V, 10%, X7R
muRata
C16
GRM39X7Rl04KOI6A
Capacitor, Ceramic, 0.1 IiF, 16 V, 10%, X7R
muRala
C17
GRM42-6Y5Vl05Z016A
Capacitor, Ceramic, 1 IiF, 16 V, +800/0-20%
muRata
C18
GRM39X7Rl04KOI6A
Capacitor, Ceramic, O.IIiF, 16 V, 10%, X7R
muRata
SI122-18-ND
Header, RA, 18-pin, 0.23 Posts x 0.20 Tails
Sullins
C15
1
Jl
1
Ll
1
L2
1
Ql
2
Inductor, Filler, 2.2IiH, 8.5 A (lOT #22 on T30-18 Core)
Inductor, Filter, 2.61iH, 8.5 A (12T #20 on T44-8 Core)
Si4410DY
FET, N-ch, 30-V, 10-A, 13-mO
Siliconix
Si4410DY
FET, N-ch, 30-V, 10-A, 13-mO
Siliconix
3
Std
Resistor, Chip, 1.0 kQ, 1/16W, 5%
R2
1
Std
Resistor, Chip, 101<0, 1/16W, 5%
R3
2
Std
Resistor, Chip, 10 n, 111 OW, 5%
Std
Resistor, Chip, 10 n, 111 OW, 5%
Sid
Resistor, Chip, 2.7 0, 1/4W, 5%
Sid
Resistor, Chip, 1.31<0, 1/16W, 5%
Q2
Rl
R4
R5
1
R6
R7
1
Sid
Resistor, Chip, 11.01<0, 1/16W, 1%
R8
2
Sid
Resistor, Chip, 100 O,1I16W, 1%
R9
Std
Resistor, Chip, 100 O,"1/16W, 1%
Rll
Std
Resistor, Chip, 750 0, 1/16W, 5%
R12
1
Std
Resistor, Chip, 20.0 kQ, 1/16W, 1%
R15
2
Sid
Resislor, Chip, 4.7 0, 1/16W, 5%
Std
Resistor, Chip, 4.7 0, 1/16W, 5%
R16
R17
1
Sid
Resistor, Chip, 1 MO, 1/16W, 5%
Ul
1
TPS5625PWP
IC, PWM Ripple Controller, Fixed 2.5 V
~TEXAS
INSTRUMENTS
7-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TI
TPS5615, TPS5618, TPS5625,TPS5633
SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER
SLVS177A - SEPTEMBER 1998 - REVISED NOVEMBER 1998
APPLICATION INFORMATION
EFFICIENCY
vs
OUTPUT CURRENT
100
95
#.
I
f
V
90
/
~
- r-- -
--
........
85
80
o
2
3
4
5
6
7
8
Output Current - A
Figure 25
Top: Vo 10 mV/dlv
Bottom: VDS Q2 5 V/div
, , : ' ... : .... : .... : .... ~ .. 2 J.lSIdiv
~~~~
................ .
Figure 26. Output Voltage Ripple at 8 A
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-119
TPS5615,TPS5618,TPS5625,TPS5633
SYNCHRONOUS·BUCK HYSTERETIC REGULATOR CONTROLLER
SLVS177A-SEPTEMBER 1998- REVISED NOVEMBER 1998
APPLICATION INFORMATION
rt!""'--------I
20 I1SIdlv
. . . . . . . . . . . . . . . . . . . . . . . . '+,;..<1'
0
1'>'-<-.......---""""'..................-_.........14" .... .: . 12.5A/dlv
Vo
20 mV/dlv
....
.
.
.
.
.
. ... : ... ': .... : .... : ....
Figure 27. Rising Load Transient Response
10
2.5A/dlv
201lS/div
Figure 28. Failing Load Transient Response
~1EXAS
7-120
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5615, TPS5618, TPS5625, TPS5633
SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER
SLVS177A - SEPTEMBER 1998 - REVISED NOVEMBER 199B
APPLICATION INFORMATION
layout guidelines
Good power supply results will only occur when care is given to proper design and layout. layout will affect noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult
than most general PCB design. The general design should proceed from the switching node to the output, then
back to the driver section and, finally, place the low-level components. Below are several specific points to
consider before layout of a TPS56xx design begins.
1.
All sensitive analog components should be referenced to ANAGND. These include components connected
to SlOWST, lOUT, OCP, VSENSE, VREFB, VHYST, BIAS, and lOHIB.
2.
Analog ground and drive ground should be isolated as much as possible. Ideally, analog ground will connect
to the ground side of the bulk storage capacitors, on Va, and drive ground will connect to the main ground
plane close to the source of the low-side FET.
3.
Connections from the drivers to the gate of the power FETs should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
4.
The bypass capacitor for the DRV regulator should be placed close to the TPS56xx and be connected to
DRVGND.
5.
The bypass capacitor for Vee should be placed close to the TPS56xx and be connected to DRVGND.
6.
When configuring the high-side driver as a floating driver, the connection from BOOTlO to the power FETs
should be as short and as wide as possible. The other pins that also connect to the power FETs, lOHIB
and lOSENSE, should have a separate connection to the FETs, since BOOTlO will have large peak
currents flowing through it.
7.
When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from BOOT
to BOOTlO) should be placed close to the TPS56xx.
8.
When configuring the high-side driver as a ground referenced driver, BOOTlO should be connected to
DRVGND.
9.
The bulk storage capacitors across VI should be placed close to the power FETs. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and close to the source of the low-side FET.
10. High-frequency bypass capacitors should be placed across the bulk storage capacitors on Va.
11. HI SENSE and LOSENSE should be connected very close to the drain and source, respectively, of the
high-side FET. HISENSE and lOSENSE should be routed very close to each other to minimize
differential-mode noise coupling to these traces.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75266
7-121
7-122
TPS5210
PROGRAMMABLE SYNCHRONOUS-BUCK REGULATOR CONTROLLER
SLVSl71A-SEPTEMBER 1998- REVISED MAY 1999
OW OR PWP PACKAGE
(TOP VIEW)
• ±1% Reference Over Full Operating
Temperature Range
• Synchronous Rectifier Driver for Greater
Than 90% Efficiency
• Programmable Reference Voltage Range of
1.3 Vto 3.5 V
• User-Selectable Hysteretic Type Control
• Droop Compensation for Improved Load
Transient Regulation
• Adjustable Overcurrent Protection
• Programmable Softstart
• Overvoltage Protection
• Active Deadtlme Control
• Power Good Output
• Internal Bootstrap Schottky Diode
• Low Supply Current .•. 3-mA Typ
lOUT
DROOP
OCP
VHYST
VREFB
VSENSE
ANAGND
SlOWST
BIAS
lODRV
lOHIB
DRVGND
lOWDR
DRV
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
3
4
5
6
7
8
9
10
11
12
13
14
PWRGD
VIDO
VIDl
VID2
VID3
VID4
INHIBIT
IOUTlO
lOSENSE
HISENSE
BOOTlO
HIGHDR
BOOT
VCC
description
The TPS521 0 is a synchronous-buck regulator controller which provides an accurate, programmable supply
voltage to microprocessors. An internalS-bit DAC is used to program the reference voltage to within a range
of 1.3 V to 3.5 V. The output voltage can be set to be equal to the reference voltage or to some multiple of the
reference voltage. A hysteretic controller with user-selectable hysteresis and programmable droop
compensation is used to dramatically reduce overshoot and undershoot caused by load transients. Propagation
delay from the comparator inputs to the output drivers is less than 250 ns. Overcurrent shutdown and crossover
protection for the output drivers combine to eliminate destructive faults in the output FETs. The softstart current
source is proportional to the reference voltage, thereby eliminating variation of the softstart timing when
changes are made to the output voltage. PWRGD monitors the output voltage and pulls the open-collector
output low when the output drops 7% below the nominal output voltage. An overvoltage circuit disables the
output drivers if the output voltage rises 15% above the nominal value. The inhibit pin can be used to control
power sequencing. Inhibit and undervoltage lockout assures the 12-V supply voltage and system supply voltage
(5 V or 3.3 V) are within proper operating limits before the controller starts. Single-supply (12 V) operation is
easily accomplished using a low-current divider for the required 5-V signals. The output driver circuits include
2-A drivers with internal B-V gate-voltage regulators. The high-side driver can be configured either as a
ground-referenced driver or as a floating bootstrap driver. The TPS5210 is available in a 2B-pin SOIC package
and a 2B-pin TSSOP PowerPADTM package. It operates over a junction temperature range of O°C to 125°C.
AVAILABLE OPTIONS
PACKAGES
TJ
SOIC
(OW)
TSSOP
(PWP)
TPS52100W
O°Cto 125°C
TPS5210PWPR
The OW package IS available taped and reeled. Add R suffix to device
type (e.g., TPS52100WR).
•
Please be aware that an important notice concerning availability. standard warranty. and use in critical applications of
~ Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
~~~::':1: '::ill'':'':..'~r::!'::: !.::\"~
atandard warranty. Production proceeaing does not nece8llrlly Include
testing 01 all param......
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 1999. Texas Instruments Incorporated
7-123
-n '"
l
C
::::lI
~
"'0-1
<
::a "'0
~
.."
Vcc
r
VID1
VIDO~
s
VlD2
VID3--VID4
ANAGND
17
PWRGD
lOSENSE
0"
IOUTlO HISENSE
::::lI
21
20
28
!!.
c:r
119
I
'"m
g ~
CD
m
~
Q,
~IOUT
V
INHIBIT 22
;:
E
;;
:I
2x
:II
co
rg
I
:II
~
m
iii
o
;;::
?(
.,
~
oCP
18
3
.......
~
m
r-
m
~
z
o
:::E:
::a
oz
o
c
m
!~~
•
c
o
::a
m
HIGHDR
"
~~d
~~
'"
::a~
:1>0
i:
cp
~-
~~~
ocn
QUI
VSENSE
8
Q
C
Analog
Bias
Analog Bias
I,
~
IVREFB
-S-
r-
9
BIAS
14 DRV
!i
o
::a
o
~
o
...-_S_hutdown
,
VID
MUX
1'-...._ I
---yr-
16
~
17 BOOT
HIGHDR
I VREF,
200 k.Q
I
Shutdown
I
_t __• I
18 BOOTlO
•
13 lOWDR
27126
125
124 123
.,S
12
6
VIDO VID1 VID2 VlD3 VID4 VREFB DROOP VHYST VSENSE
lOHIB
!i
~
rrm
::a
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A - SEPTEMBER 1998 - REVISED MAY 1999
Terminal Functions
TERMINAL
NAME
NO.
1/0
DESCRIPTION
ANAGND
7
BIAS
9
0
BOOT
16
I
Bootstrap. Connect a
BOOTlO
18
0
Bootstrap low. Connect BOOTlO to the junction of the high-side and low-side FETs for floating drive
configuration. Connect BOOTlO to PGND for ground reference drive configuration.
DROOP
2
I
Droop voltage. Voltage input used to set the amount of output-voltage set-point droop as a function of load
current. The amount of droop compensation is set with a resistor divider between lOUT and ANAGND.
DRV
14
0
Drive regulator for the FET drivers. A 1-~F ceramic capacitor should be connected from DRV to DRVGND.
DRVGND
12
HIGHDR
17
0
High drive. Output drive to high-side power switching FETs
HISENSE
19
I
High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs; for
optional resistor sensing scheme, connect to power supply side of current-sense resistor placed in series with
high-side FET drain.
INHIBIT
22
I
Disables the drive signals to the MOSFET drivers. Can also serve as UVlO for system logic supply (either 3.3 V
or5V).
1
0
Current out. Output voltage on this pin is proportional to the load current as measured across the Rds(on) of the
high-side FETs. The voltage on this pin equals 2xRds( On)xIOUT. In applications where very accurate current
senSing is required, a sense resistor should be connected between the input supply and the drain olthe high-side
FETs.
10UTlO
21
0
Current sense low output. This is the voltage on the lOSENSE pin when the high-side FETs are on. A ceramic
capacitor should be connected from 10UTlO to HISENSE to hold the sensed voltage while the high-side FETs
are off. Capacitance range should be between 0.033 ~F and 0.1 ~F.
lOUT
Analog ground
Analog BIAS pin. A 1-~F ceramic capacitor should be connected from BIAS to ANAGND.
1-~F
low-ESR capacitor from BOOT to BOOTlO.
Drive ground. Ground for FET drivers. Connect to FET PWRGND.
lODRV
10
I
low drive enable. Normally tied to 5 V. To activate the low-side FETs as a crowbar, pull lODRV low.
lOHIB
11
I
low side inhibit. Connect to the junction of the high and low side FETs to control the anti-cross-conduction and
eliminate shoot-through current. Disabled when configured in crowbar mode.
lOSENSE
20
I
low current sense. For current sensing across high-side FETs, connect to the source of the high-side FETs; for
optional resistor senSing scheme, connect to high-side FET drain side of current-sense resistor placed in series
with high-side FET drain.
lOWDR
13
0
low drive. Output drive to synchronous rectifier FETs
OCP
3
I
Over current protection. Current limit trip point is set with a resistor divider between lOUT and ANAGND.
PWRGD
28
0
Power good. Power Good signal goes high when output voltage is within 7% of voltage set by VID pins.
Open-drain output.
SlOWST
8
0
Slow Start (soft start). A capacitor from SlOWST to ANAGND sets the slowstart time.
Siowstart current = IVREFB'5
Vee
15
VHYST
4
I
HYSTERESIS set pin. The hysteresis is set with a resistor divider from VREFB to ANAGND.
The hysteresis window = 2 x (VREFB - VHYST)
VIDO
27
I
Voltage Identification input 0
VIOl
26
I
Voltage Identification input 1
VID2
25
I
Voltage Identification input 2
VID3
24
I
Voltage Identification input 3
VID4
23
I
Voltage Identification input 4. Digital inputs that set the output voltage of the converter. The code pattern for
setting the output voltage is located in Table 1. Internally pulled up to 5 V with a resistor divider biased from VCC.
VREFB
5
0
Buffered reference voltage from VID network
VSENSE
6
I
Voijage sense Input. To be connected to converter output voltage bus to sense and control output voltage. It is
recommended an RC low pass filter be connected at this pin to filter noise.
12-V supply. A
1-~F
ceramic capacitor should be connected from VCC to DRVGND.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-125
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A-SEPTEMBER 1998- REVISED MAY 1999
detailed description
VREF
The reference/voltage identification (VID) section consists of a temperature-compensated bandgap reference
and a 5-bit voltage selection network. The 5 VID terminals are inputs to the VID selection network and are
TIL-compatible inputs internally pulled up to 5 V by a resistor divider connected to Vee. The VID codes conform
to the Intel VRM B.3 DC-DC Converter Specification for voltage settings between 1.8 V and 3.5 V, and they are
decremented by 50 mY, down to 1.3 V, for the lower VID settings. Voltages higher than VREF can be implemented
using an external divider. Refer to Table 1 forthe VID code settings. The output voltage ofthe VID network, VREFo
is within ±1 % of the nominal setting over the VID range of 1.3 V to 2.5 V, including a junction temperature range
of 5°Cto+125°C, and a Vee supply voltage range of 11.4 Vto 12.6 V. The outputofthe referenceIVlD network
is indirectly brought out through a buffer to the VREFB pin. The voltage on this pin will be within 2% of VREF It
is not recommended to drive loads with VREFB, other than setting the hysteresis of the hysteretic comparator,
because the current drawn from VREFB sets the charging current for the slowstart capacitor. Refer to the
slowstart section for additional information.
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by 2 external resistors and is centered on VREF The 2 external resistors form a resistor divider from VREFB
to ANAGND, with the output voltage connecting to the VHYST pin. The hysteresis ofthe comparator will be equal
to twice the voltage difference between the VREFB and VHYST pins. The propagation delay from the comparator
inputs to the driver outputs is 250 ns (maximum). The maximum hysteresis setting is 60 mY.
low-side driver
The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The bias to the low-side driver is internally connected to the DRV regulator.
high-side driver
The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The high-side driver can be configured either as a ground-referenced driver or as a floating
bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from the DRV
regulator. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved
drive efficiency. The maximum voltage that can be applied between BOOT and DRVGND is 30 V. The driver
can be referenced to ground by connecting BOOTLO to DRVGND, and connecting BOOT to either DRV or Vee.
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the tum-on times of the MOSFET drivers. The high-side driver is not allowed
to turn on until the gate-drive voltage to the low-side FETs is below 2 V; the low-side driver is not allowed to turn
on until the voltage at the junction of the high-side and low-side FETs (Vphase) is below 2 V.
current sensing
Current sensing is achieved by sampling and holding the voltage across the high-side power FETs while the
high-side FETs are on. The sampling network consists of an internal 60-0 switch and an external ceramic hold
capacitor. Recommended value of the hold capacitor is between 0.033 ~F and 0.1 ~F. Internal logic controis
the tum-on and tum-off of the sample/hold switch such that the switch does not tum on until the Vphase voltage
transitions high, and the switch turns off when the input to the high-side driver goes low. The sampling will occur
only when the high-side FETs are conducting current. The voltage on the lOUT pin equals 2 times the sensed
high-side voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can
be placed in series with the high-side FETs, and the voltage across the sense resistor can be sampled by the
current sensing circuit.
~1ExAs
7-126
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A - SEPTEMBER 1998 - REVISED MAY 1999
detailed description (continued)
droop compensation
The droop compensation network reduces the load transient overshoot/undershoot on VO, relative to VREF' Vo
is programmed to a voltage greater than VREF by an external resistor divider from Vo to VSENSE to reduce the
undershoot on Vo during a low-to-high load transient. The overshoot during a high-to-Iow load transient is
reduced by subtracting the voltage on DROOP from VREF The voltage on lOUT is divided with an extemal
resistor divider, and connected to DROOP.
inhibit
INHIBIT is a TTL-compatible digital input used to enable the controller. When INHIBIT is low, the output drivers
are low and the slowstart capacitor is discharged. When INHIBIT goes high, the short across the slowstart
capacitor is released and normal converter operation begins. When the system-logic supply is connected to
INHIBIT, it also controls power sequencing by locking out controller operation until the system-logic supply
exceeds the input threshold voltage of the inhibit circuit. The 12-V supply and the system logic supply (either
5 V or 3.3 V) must be above UVLO thresholds before the controller is allowed to start up. The start threshold
is 2.1 V and the hysteresis is 100 mV for the INHIBIT comparator.
Vee undervoltage lockout (UVLO)
The undervoltage lockout circuit disables the controller while the Vee supply is below the 1O-V start threshold
during power up. When the controller is disabled, the output drivers will be low and the slowstart capacitor is
discharged. When Vee exceeds the start threshold, the short across the slowstart capacitor is released and
normal converter operation begins. There is a 2-V hysteresis in the undervoltage lockout circuit for noise
immunity.
slowstart
The slowstart circuit controls the rate at which Vo powers up. A capaCitor is connected between SLOWST and
ANAGND and is charged by an internal current source. The current source is proportional to the reference
voltage, so that the charging rate of Cslowst is proportional to the reference voltage. By making the charging
current proportional to VREF> the power-up time for Vo will be independent of VREF Thus, CSLOWST can remain
the same value for all VID settings. The slowstart charging current is determined by the following equation:
'slowstart = I(VREFB) 15 (amps)
Where I(VREFB) is the current flowing out of VREFB'
It is recommended that no additional loads be connected to VREFB, other than the resistor divider for setting the
hysteresis voltage. The maximum current that can be sourced by the VREFB circuit is 500 !.IA. The equation for
setting the slowstart time is:
tSLOWST = 5 x CSLOWST x RVREFB
(seconds)
Where RVREFB is the total extemal resistance from VREFB to ANAGND.
power good
The power-good circuit monitors for an undervoltage condition on VO. If Vo is 7% below VREF> then the PWRGD
pin is pulled low. PWRGD is an open-drain output.
overvoltage protection
The overvoltage protection (OVP) circuit monitors Vo for an overvoltage condition. If Vo is 15% above VREF>
then a fault latch is set and both output drivers are turned off. The latch will remain set until Vee goes below the
undervoltage lockout value. A 3-!!S deglitch timer is included for noise immunity. Refer to the LODRV section
for information on how to protect the microprocessor against overvoltages due to a shorted fault across the
high-side power FET.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
7-127
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A - SEPTEMBER 1998 - REVISED MAY 1999
detailed description (continued)
overcurrent protection
The overcurrent protection (OCP) circuit monitors the current through the high-side FET. The overcurrent
threshold is adjustable with an external resistor divider between lOUT and ANAGND, with the divider voltage
connected to the OCP pin. If the voltage on OCP exceeds 100 mY, then a fault latch is set and the output drivers
are turned off. The latch will remain set until Vee goes below the undervoltage lockout value. A 3-I1S deglitch
timer is included for noise immunity. The OCP circuit is also designed to protect the high-side power FET against
a short-to-ground fault on the terminal common to both power FETs.
drive regulator
The drive regulator provides drive voltage to the output drivers. The minimum drive voltage is 7 V. The minimum
short circuit current is 100 mAo Connect a I-I1F ceramic capacitor from DRV to DRVGND.
LODRV
The LODRV circuit is designed to protect the microprocessor against overvoltages that can occur ifthe high-side
power FETs become shorted. External components to sense an overvoltage condition are required to use this
feature. When an overvoltage fault occurs, the low-side FETs are used as a crowbar. LODRV is pulled low and
the low-side FET will be turned on, overriding all control signals inside the TPS521 0 controller. The crowbar
action will short the input supply to ground through the faulted high-side FETs and the low-side FETs. A fuse
in series with Yin should be added to disconnect the short-circuit.
Table 1. Voltage Identification Codes
VID TERMINALS
(0 = GND, 1 = floating or pull-up to 5 V)
VID3
VID2
VID1
VIDO
(Vdc)
0
1
1
1
1
1.30
0
1
1
1
0
1.35
0
1
1
0
1
1.40
0
1
1
0
0
1.45
0
1
0
1
1
1.50
0
1
0
1
0
1.55
0
1
0
0
1
1.60
0
1
0
0
0
1.65
0
0
1
1
1
1.70
0
0
1
1
0
1.75
0
0
1
0
1
1.80
0
0
1
0
0
1.85
0
0
0
1
1
1.90
0
0
0
1
0
1.95
0
0
0
0
1
2.00
0
0
0
0
0
2.05
1
1
1
1
1
No CPU
1
1
1
1
0
2.10
1
1
1
0
1
2.20
1
1
1
0
0
2.30
1
1
0
1
1
2.40
1
1
0
1
0
2.50
1
1
0
0
1
2.60
~TEXAS
7-128
vREF
VID4
INSTRUMENTS
POST OFFICE BOX 655303 • DALlJlS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A - SEPTEMBER 1998 - REVISED MAY 1999
Table 1. Voltage Identification Codes (Continued)
VID TERMINALS
(0
=GND, 1 =floating or pull·up to 5 V)
VREF
VID4
VID3
VID2
VID1
VIDO
1
1
0
0
0
(Vdc)
2.70
1
0
1
1
1
2.80
1
0
1
1
0
2.90
1
0
1
0
1
3.00
1
0
1
0
0
3.10
3.20
1
0
0
1
1
1
0
0
1
0
3.30
1
0
0
0
1
3.40
1
0
0
0
0
3.50
absolute maximum ratings over operating virtual junction temperature (unless otherwise noted)t
Supply voltage range, Vee (see Note1) .............................................. -0.3 V to 14 V
Input voltage range: BOOT to DRVGND (High-side Driver ON) ......................... -0.3 V to 30 V
BOOT to HIGHDRV ............................................ -0.3 V to 15 V
BOOT to BOOTlO ............................................. -0.3 V to 15 V
INHIBIT, VIDx, lODRV ........................................ -0.3 V to 7.3 V
PWRGD, OCP, DROOP ......................................... -0.3 V to 7 V
lOHIB, lOSENSE, IOUTlO, HISENSE .......................... -0.3 V to 14 V
VSENSE ...................................................... -0.3 V to 5 V
Voltage difference between ANAGND and DRVGND ......................................... ±0.5 V
Output current, VREFB ................................................................... 0.5 mA
Short circuit duration, DRV ........................................................... Continuous
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating virtual junction temperature range, TJ ....................................... O°C to 125°C
Storage temperature range, Tstg .................................................. --65°C to 150°C
lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds ....................... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGNO.
DISSIPATION RATING TABLE
PACKAGE
TA s 25°C
POWER RATING
=
=
DERATING FACTOR
ABOVE TA = 25°C
TA 70°C
POWER RATING
TA 85°C
POWER RATING
ow
1200mW
12 mW/oC
660mW
480mW
PWP
1150mW
11.5mW/oC
630mW
460mW
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
7-129
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A - SEPTEMBER 1998 - REVISED MAY 1999
recommended operating conditions
MIN
MAX
11.4
13
V
Input voltage, BOOT to DRVGND
0
28
V
Input voltage, BOOT to BOOTlO
0
13
V
Input voltage, INHIBIT, VIDx, lODRV, PWRGD, oep, DROOP
0
6
V
Input voltage, LOHIB, LOSENSE, 10UTlO, HISENSE
0
13
V
Input voltage, VSENSE
0
4.5
V
Voltage difference between ANAGND and DRVGND
0
±O.2
V
Output current, VREFBt
0
0.4
mA
Supply voltage, Vee
UNIT
t Not recommended to load VREFB other than to set hystersls since IVREFB sets slowstart time.
electrical characteristics over recommended operating virtual Junction temperature range,
Vee = 12 V, IDRV = 0 A (unless otherwise noted)
referencelvoltage Identification
PARAMETER
TEST CONDITIONS
VREF
Cumulative reference accuracy
(see Note 2)
VIDx
High-level Input voltage
VIDx
low-level input voltage
VREFB
VIDx
TYP
MAX
UNIT
0.01
VN
Vee = 11.4 to 12.6 V, VREF=2.6 V
-0.0104
0.0104
VN
=11.4t012.6V, VREF=2.7V
-0.0108
0.0108
VN
Vee = 11.4 to 12.6 V, VREF = 2.8 V
-0.0112
0.0112
VN
Vec = 11.4to 12.6 V, VREF=2.9 V
-0.0116
0.0116
VN
Vee = 11.4 to 12.6 V, VREF=3V
-0.0120
0.0120
VN
VCC = 11.4to 12.6 V, VREF = 3.1 V
-0.0124
0.0124
VN
Vec=11.4t012.6V, VREF=3.2V
-0.0128
0.0128
VN
Vec = 11.4 to 12.6 V, VREF = 3.3 V
-0.0132
0.0132
VN
Vee = 11.4 to 12.6 V, VREF = 3.4 V
-0.0136
0.0136
VN
Vce = 11.4to 12.6 V, VREF= 3.5 V
-0.0140
0.0140
VN
VREF = 1.3 V, Hysteresis window = 30 mV
-0.011
0.011
VREF =1.3 V, Hysteresis,
TJ = 600 e window = 30 mV (see Note 3)
-0.008
0.008
VREF = 1.9 Vv, Hysteresis,
TJ = 60°C window = 30 mV (see Note 3)
-0.0090
0.0090
VREF = 3.5 V, Hysteresis,
TJ = 60°C window = 30 mV (see Note 3)
-0.0115
0.0115
Vee
Reference voltage accuracy, (Includes
offset of droop compensation network)
MIN
-0.01
Vee = 11.4 to 12.6 V, 1.3 VSVREFS2.5 V
2.25
V
1
Output voltage
IVREFB = 50 ItA
Output regulation
10 ItA:;; 10 S 500 ItA
Input resistance
VIDx=OV
Input pull-up voltage divider
VREp-2%
VN
VREF VREF+2%
2
V
V
mV
36
73
95
4.8
4.9
5
kQ
V
NOTES: 2. Cumulative reference accuracy IS the combined accuracy of the reference voltage and the Input offset voltage of the hysteretic
comparator. Cumulative accuracy equals the average of the high-level and low-level thresholds of the hysteretic comparator.
3. This parameter is ensured by design and is not production tested.
~1ExAs
7-130
INSTRUMENTS
POST OFFICE BOX 65S303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A - SEPTEMBER 1998 - REVISED MAY 1999
electrical characteristics over recommended operating virtual junction temperature range,
Vee = 12 V, IDRV = 0 A (unless otherwise noted) (continued)
power good
PARAMETER
TEST CONDITIONS
Undervoltage trip threshold
VOL
Low-level output voltage
lo=5mA
IOH
High-level input current
VpWRGD=6V
Vhys
Hysteresis voltage
MIN
TYP
MAX
90
93
95
0.5
0.75
UNIT
%VREF
V
!1A
1
1.3
2.9
4.5
%VREF
MIN
TYP
MAX
UNIT
10.4
13
15.6
slowstart
PARAMETER
TEST CONDITIONS
Charge current
VSLOWST = 0.5 V,
IVREFB = 65 !1A
Discharge current
VSLOWST=l V
VVREFB = 1.3 V,
3
Comparator Input offset voltage
Comparator input bias current
10
10
See Note 3
-7.5
Comparator hysteresis
!1A
rnA
mV
100
nA
7.5
mV
NOTE 3: This parameter IS ensured by design and IS not production tested.
hysteretic comparator
PARAMETER
TEST CONDITIONS
Input offset voltage
VDROOP = 0 V (see Note 3)
Input bias current
See Note 3
Hysteresis accuracy
VREFB - VHYST = 15 mV
(Hysteresis window = 30 mY)
Maximum hysteresis setting
VREFB - VHYST = 30 mV
MIN
TYP
-2.5
MAX
2.5
-3.5
60
UNIT
mV
500
nA
3.5
mV
mV
NOTE 3: This parameter IS ensured by design and IS not production tested.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-131
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A - SEPTEMBER 1998 - REVISED MAY 1999
electrical characteristics over recommended operating virtual Junction temperature range,
Vee =12 V, IDRV =0 A (unless otherwise noted) (continued)
high-side
VDS sensing
PARAMETER
TEST CONDITIONS
MIN
Initial accuracy
VLOSENSE = 11.9 V,
VHISENSE = 12 V,
Differential input to V ds sensing amp = 100 mV
Sink current
5 V S; VIOUTLO S; 13 V
lOUT
Source current
VIOUT = 0.5 V,
VIOUTLO = 11.5 V
lOUT
Sink current
VIOUT = 0.05 V, VHISENSE = 12 V,
VIOUTLO = 12 V
Output voltage swing
VHISENSE = 4.5 V, RIOUT = 10 kn
IOUTLO
VHISENSE = 12 V,
VHISENSE = 11 V, RIOUT = 10 kn
LOSENSE
TYP
MAX
2
Gain
l High-level input voHage
I Low-level input voltage
VHISENSE = 3 V, RIOUT = 10 kn
VHISENSE = 4.5 V (see Note 3)
194
UNIT
VN
206
mV
250
nA
500
~
50
~
0
0
2
1.5
V
0
2.85
0.75
V
V
V
2.4
V
11.4 V S VHISENSE S 12.6 V,
50
60
80
62
85
123
67
95
144
69
75
MIN
TYP
MAX
UNIT
1.9
2.1
2.35
V
Hysteresis
0.08
0.1
0.12
V
Stop threshold
1.85
LOSENSE connected to HISENSE,
VHISENSE - VIOUTLO = 0.15 V
4.5 V S; VHISENSE S 5.5 V,
Samplelhold resistance
LOSENSE connected to HISENSE,
VHISENSE - VIOUTLO = 0.15 V
(2
3 V S VHISENSE S 3.6 V,
LOSENSE connected to HI SENSE,
VHISENSE - VIOUTLO = 0.15 V
VHISENSE = 12.6 V to 3 V,
VHISENSE - VOUTLO = 100 mV
NOTE 3. This parameter is ensured by design and is not production tested.
CMRR
dB
inhibit
PARAMETER
TEST CONDITIONS
Start threshold
V
overvoltage protection
PARAMETER
TEST CONDITIONS
Overvoltage trip threshold
MIN
TYP
112
115
See Note 3
Hysteresis
MAX
UNIT
120 %VREF
10
mV
NOTE 3: This parameter is ensured by design and is not production tested.
overcurrent protection
PARAMETER
TEST CONDITIONS
OCP trip threshold
Input bias current
~1ExAs
7-132
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MIN
TYP
MAX
90
100
110
UNIT
mV
100
nA
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A - SEPTEMBER 1998 - REVISED MAY 1999
electrical characteristics over recommended operating virtual Junction temperature range,
Vee = 12 V, IORV = 0 A (unless otherwise noted) (continued)
deadtime
PARAMETER
LOHIB
LOWDR
TEST CONDITIONS
High-level input voltage
MIN
TYP
MAX
2.4
Low-level input voltage
1.4
High-level input voltage
See Note 3
Low-level input voltage
See Note 3
3
1.7
UNIT
V
V
NOTE 3: This parameter IS ensured by design and IS not production tested.
LOORV
PARAMETER
LODRV
TEST CONDITIONS
I High-level input voltage
MIN
TYP
MAX
1.85
I Low-level input voltage
0.95
UNIT
V
droop compensation
PARAMETER
MIN
TYP
46
Initial accuracy
MAX
54
drive regulator
PARAMETER
TEST CONDITIONS
Output voltage
11.4 V:s; Vee:s; 12.6 V.
Output regulation
1 mA:S; IDRV:S;50 mA
IDRV=50mA
MIN
TYP
7
MAX
9
100
Short-circuit current
UNIT
V
mV
mA
100
bias regulator
PARAMETER
Output voltage
TEST CONDITIONS
11.4 V:S; Vee:s; 12.6 V.
See Note 4
MIN
TYP
MAX
6
NOTE 4: The bias regulator is designed to provide a quiet bias supply for the TPS521 0 controller. External loads should not be driven by the bias
regulator.
Input undervoltage lockout
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
9.25
10
10.75
V
Hysteresis
1.9
2
2.2
V
Stop threshold
7.5
Start threshold
V
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
7-133
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A - SEPTEMBER 1998 - REVISED MAY 1999
electrical characteristics over recommended operating virtual Junction temperature range,
Vee =12 V, IDRV =0 A (unless otherwise noted) (continued)
output drivers
PARAMETER
Peak output
current
(see Note 5)
TEST CONDITIONS
High-side sink
High-side source
VHIGHDR = 1.5 V (source) or 6 V (sink),
See Note 3
2
Low-side sink
Duty Cycle < 2%,
TJ= 125°C,
2
Low-side source
VLQWDR = 1.5 V (source) or 5 V (sink),
See Note 3
High-side sink
Output
resistance
(see Note 5)
tpw < 100 1lS,
VBOOT - VBOOTLO = 6.5 V,
tpw < 100 1lS,
VDRV=6.5V,
TYP
Low-side sink
MAX
UNIT
2
A
2
3
TJ = 125°C,
VBOOT - VBOOTLO = 6.5 V,
VHIGHDR = 6 V (source) or 0.5 V (sink)
High-side source
45
5.7
TJ= 125°C,
VDRV=6.5V,
VLOWDR = 6 V (source) or 0.5 V (sink)
Low-side source
NOTES:
MIN
Duty cycle < 2%,
TJ = 125°C,
n
45
3. ThiS parameter Is ensured by design and IS not production tested.
5. The pull-up/pull-down circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the Rds(on) of the MOSFET transistor when
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
supply current
PARAMETER
Vee
Vee
TEST CONDITIONS
Supply voltage
range
Quiescent
current
High-side
driver
quiescent
current
TYP
MAX
11.4
12
13
10
VINHIBIT = 5 V,
Vee> 10.75 V at startup,
VIDcode .. 11111,
VBOOTLO=OV
3
VINHIBIT = 5 V,
Vee> 10.75 V at startup,
eHIGHDR = 50 pF,
fSWX = 200 kHz,
VID code .. 11111,
VBOOTLO = 0 V,
eLQWDR = 50 pF,
See Note 3
5
VINHIBIT = 5 V,
VBOOT= 13V,
eHIGHDR = 50 pF,
VID code .. 11111, Vee> 10.75 V at startup,
VBOOTLO = 0 V,
fSWX = 200 kHz (see Note 3)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
V
mA
VINHIBIT = 0 Vor VID code = 11111 or Vee < 9.25 V at startup,
VBOOT=13V,
VBOOTLO=OV
NOTE 3: ThiS parameter IS ensured by design and IS not production tested.
7-134
MIN
80
2
!1A
mA
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A - SEPTEMBER 1998 - REVISED MAY 1999
switching characteristics over recommended operating virtual-Junction temperature range,
Vee = 12 V, IORV = 0 A (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VSENSE to HIGHDR or
LOWDR (excluding deadtime)
Propagation delay
MIN
1,3 V S VVREF S 3,5 V, 10 mV overdrive
(see Note 3)
OCP comparator
See Note 3
UNIT
150
250
ns
1
PWRGD comparator
ItS
1
SLOWST comparator
Overdrive = 10 mV (see Note 3)
HIGHDR output
CL=9nF,
VSOOTLO =
LOWDR output
CL= 9 nF,
TJ = 125°C
HIGHDR output
CL= 9 nF,
VSOOTLO =
LOWDR output
CL= 9 nF,
TJ = 125°C
Rise time
Fall time
Response time
MAX
1
OVP comparator
Deglitch time (Includes
comparator propagation
delay)
TYP
a V,
560
VSOOT = 6,5 V,
TJ = 125°C
ns
60
VSOOT = 6,5 V,
TJ = 125°C
60
ns
VDRV=6,5V,
OCP
60
2
5
2
5
See Note 3
OVP
High-side VDS sensing
VHISENSE = 12 V,
VIOUTLO pulsed from 12 V to 11,9 V,
100 ns rise/fall times
(see Note 3)
2
VHISENSE = 4,5 V,
VIOUTLO pulsed from 4,5 V to 4.4 V,
100 ns rise/fall times (see Note 3)
3
VHISENSE = 3 V,
VIOUTLO pulsed from 3 V to 2,9 V,
100 ns rise/fall times (see Note 3)
3
Short-circuit protection
rising-edge delay
SCP
LOSENSE =
Turn-on/turn-off delay
VDS sensing sample/hold
switch
Crossover delay time
LOWDR to HIGHDRV, and
LOHIS to LOWDR
Prefilter pole frequency
Hysteretic comparator
See Note 3
Propagation delay
LODRV
See Note 3
NOTE 3: ThiS parameter IS ensured by design and
IS
a V (see Note 3)
ns
60
VDRV=6,5V,
a V,
900
ItS
ItS
300
500
ns
3 V S VHISENSE S 11 V,
VLOSENSE = VHISENSE (see Note 3)
30
100
ns
See Note 3
30
100
ns
MHz
5
400
ns
not production tested,
~1ExAs
INSTRUMENTS
POST OFFICE
eox 655303 •
DALlAS, TEXAS 75265
7-135
TPS521 0
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A-SEPTEMBER 1998- REVISED MAY 1998
TYPICAL CHARACTERISTICS
SLOWSTART TIME
VB
SLOWSTART CAPACITANCE
SLOWSTART TIME
VB
SUPPLY CURRENT (VREFB)
100
1ooo~~~.
V(VREFB) = 2 V
V(VREFB) = 2 V
CS=0.1IlF
TJ=25°C
~REFB6 = 100 IIA
J=25°
V
10
~
I
I
I
/
/
0.1
0
0.0001
1
0.0010
0.0100
0.1000
Siowstart Capacitance -IlF
1
10
100
ICC - Supply Current (VREFB) -IIA
Figure 1
1000
Figure 2
DRIVER
DRIVER
OUTPUT RISE TIME
VB
LOAD CAPACITANCE
OUTPUT FALL TIME
VB
LOAD CAPACITANCE
100
1000
TJ = 25°C
TJ = 25°C
'I
I!
I-- I-
I
~
,..
i
10
HlghSlde~~
l.I
•c
100
I
LowSlde
High Side
1JA'
CD
E
1=
~
~
...
I
I
.~
.::-
10
1
1
0.1
10
100
0.1
CL - Loed Capacitance - nF
Figure 3
10
CL - Load Capacitance - nF
Figure 4
~1ExAs
7-136
V ~~~Slde
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
100
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A- SEPTEMBER 1998- REVISED MAY 1999
TYPICAL CHARACTERISTICS
OVP THRESHOLD
OCP THRESHOLD VOLTAGE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
118
105~-~r---.---r---r---'
117
>
103~--~~---+-----+-----r----,
E
'#.
I
116
I
GI
I
~
.c
~
115
II
i5
.c
i!:
II
a.
is
101~---4-----+-----r----~----'
'a
~~---4-----+-----r----~----'
i!:
114
a.
0
0
113
112
0
25
75
50
100
97~--~-----+-----r-----r--~
95~-~~-~--~--~-~
o
125
25
TJ - Junction Temperature - °C
Figure 5
JUNCTION TEMPERATURE
2.1
150
>
>
I
E
& 2.05
All
I
125
GI
~
J
~
2 I"'---.
.~
i!:
100
r----........
I
t:
.c
.5
125
vs
JUNCTION TEMPERATURE
91
-=
:9
100
INHIBIT HYSTERESIS VOLTAGE
vs
I!
75
Figure 6
INHIBIT START THRESHOLD VOLTAGE
~
.c
50
TJ - Junction Temperature - °C
r-.............
V
I"--.
':t:=
.a
1.95
:c
.5
1.9 L--......L--....I...--..L....-~:-:----:-'_
o
25
50
75
100
125
75
50
o
TJ - Junction Temperature - °C
Figure 7
25
50
75
100
125
TJ - Junction Temperature - °C
FigureS
-!I
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-137
TPS521 0
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A- SEPTEMBER 1998 - REVISED MAY 1999
TYPICAL CHARACTERISTICS
UVLO START THRESHOLD VOLTAGE
UVLO HYSTERESIS
vs
vs
JUNCTION TEMPERATURE
10.5
JUNCTION TEMPERATURE
2.5.-----,---,--.,---;----,
VI= 12V
.1
VI =12V
>
2.31----t---+--+---/------1
I
j
-----------r--
10
~
~
.c
I
~
1:
a!
>
I
r'~
o
~
9.5
0
1.91---+---+--+----11----1
....I
>
:::I
1.71----t--+--+---/------1
9
a
25
75
100
50
TJ - Junction Temperature - °C
125
1.5 L - _ - - I_ _-I.._ _~-___:_~-_:_I
a
25
50
75
100
125
TJ - Junction Temperature - °C
Figure 9
Figure 10
QUIESCENT CURRENT
6
POWERGOOD THRESHOLD
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
95
.1,
VI =12V
94
1
I
4
~
2
a
a
~
~
25
75
100
50
TJ - Junction Temperature - °C
125
90
a
Figure 11
75
100
25
50
TJ - Junction Temperature - °C
Figure 12
~TEXAS
INSTRUMENTS
7-138
~
-----
j
I
~
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
125
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A - SEPTEMBER 1998 - REVISED MAY 1999
TYPICAL CHARACTERISTICS
DRIVER
SLOW START CHARGE CURRENT
vs
JUNCTION TEMPERATURE
REGULATOR VOLTAGE
vs
JUNCTION TEMPERATURE
15~--~----~-----r----~--~
V(VREFB)
R(VREFB)
8.5
=1.3 V
=20 kn
14~--~~---+----~----~--~
8.25
>
I
III
I
~
8
15
i
1
12r---~-----+-----r----~----;
7.75
11r---~-----+-----r----~----;
10~--~----~----~----~--~
o
25.
75
50
100
---
....-
7.5
125
o
25
TJ - Junction Temperature - °C
Figure 13
...
4
I
3
0
2
I
DRIVER
DRIVER
HIGH-SIDE OUTPUT RESISTANCE
vs
JUNCTION TEMPERATURE
LOW-SIDE OUTPUT RESISTANCE
vs
JUNCTION TEMPERATURE
a
I
3c
15a.
15
~.c
125
6
c
III
100
Figure 14
5
a
75
50
TJ - Junction Temperature - °C
~
....--
~
----~
.
1
...".......
4
II:
~
15
t
v
V
V
0
III
~
2
~
....I
J
I
0
0
II:
II:
o
o
25
50
75
100
o
125
o
TJ - Junction Temperature - °C
25
50
75
100
125
TJ - Junction Temperature - °C
Figure 15
Figure 16
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
---_ ... - - - - - - - - - - - -
7-139
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171 A - SEPTEMBER 1998 - REVISED MAY 1999
TYPICAL CHARACTERISTICS
SENSING SAMPLE/HOLD RESISTANCE
vs
JUNCTION TEMPERATURE
100
I
V(HISENSE)
Cl
!
=12 V
I
~
c
!
~
75
~a.
50
~
l..--~
E
c7l
CIl
c
'ii
c
25
c7l
I
0
II:
o
o
25
50
75
100
TJ - Junction Temperature - °C
Figure 17
~TEXAS
7-140
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
125
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A- SEPTEMBER 1998 - REVISED MAY 1999
APPLICATION INFORMATION
The following figure is a typical application schematic. The circuit can be divided into the power-stage section
and the control-circuit section. The power stage must be tailored to the inpuVoutput requirements of the
application. The control circuit is basically the same for all applications with some minor tweaking of specific
values. Table 2 shows the values of the power stage components for various output-current options.
l101
12V r
l102
Q101
==
~
".-.
~~
+
C10;=' f'c1oi 'C1ta
I
i=:;;
?
~ R102
Q102
~ i=-
1];~
r----r-----
~R101
~
PowerStage
- - - - - - - - - - - - - - - - - - - - - - -W Wo
en ....
~ en
Q
Z I:c ZW IJ!g
~
- -
RTN
5: ~ gill
en
Q
....0 0....
g!
I:)
1 utJ
II)
11
la
<:.
-!:.
nl
"u
C6 If
0.033ul" I'
Note 1
>
~
~ r:;C8
2200 pF
Note 1:
VIDe - VlD4 Ueer-selected
to eat output voltage.
'"
....
- - - - --
~
Z
W
::::::::
DRV
BOOT
HIGH DR
i"'l
lOWDR
BOOTlO
lOHIB
HISENSE
lODRV
lOSENSE
t;r-
~
BIAS
IOUTlO
SlOWST
INHIBIT
ANAGND
VSENSE
--~
VID3
VREFB
--~
VID2
VHYST
- - - W VID1
OCP
- - ---rr
VIDO
DROOP
PWRGD
lOUT
R2
150 >
1"
DRVGND
- - --w- VID4
2IJ
- -
C2
1 uF
::::
C3\1
-
--
-
W
5: Q~
III
~
CI
ENABlE
- - - - - - - - -- - - - -
z
VCC
R4
2.55 k :
1%
f: C104
Q
C1_:::::
1 uF
R1
3.40k
1%
,
-:!::-
r-----
Control Section
.."
C1ts' F' C10;
~
GND
- - - - - - --
Vo
II
I
a
1uuu pF
C5
C7 If
1UU
A
:)
4
1
TPS5210
U1
I'
'!" 1u.u K
'VVV"
I)
rrl
:~
• u."
R5
3
C4
1 uF
If
R7
~.~2k
A
A
I ~~:
1
R8
1.00 k
AA
·vvv
A
R9
4.32K
R10
I 1.00
k
V
Figure 18. Standard Application Schematic
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-141
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A - SEPTEMBER 1998 - REVISED MAY 1999
APPLICATION INFORMATION
Table 2. Power Stage Components
Ref
Des
Cl0l
Cl02
12-V-lnput Power Stage Components
Function
Input Bulk
Capac~or
Input
Mld-Freq
Capac~r
WOuI
4-AOut
12-AOut
2o-AOut
4O-AOut
Sanyo,
lBSV100M,
l00-uF, 16-V, 20%
Sanyo,
16SA470M,
2 x 47Q-uF, 16-V, 20%
Sanyo,
16SA470M,
2 x 47Q-uF, 16-V, 20%
Sanyo,
1BSA470M,
3 x 47o-uF, 16-V, 20%
Sanyo,
lBSA470M,
4 x 47o-uF, 16-V, 20%
muRata,
GRM42-6YSV105Z025A
1.Q-uF, 25-V,
+80%-20%,
Y5V
muRata,
GRM42-6YSV225Z016A
2.2-uF, 16-V,
+80%-20%,
YSV
muRata,
GRM42-6YSV225Z01BA
2.2-uF, 16-V,
+80%-20%,
YSV
muRata,
GRM42-6YSV105Z025A
3 x l.Q-uF, 25-V,
+80%-20%,
Y5V
muRata,
GRM42-6YSV105Z025A
4 x 1.Q-uF, 25-V,
+90%-20%,
Y5V
Cl03
Input
Hi-Freq
Bypass
Capacitor
muRata,
GRM39X7R104KOI6A
0.1-uF, 16-V, X7R
muRata,
GRM39X7R104K01BA,
0.1-uF, 16-V,X7R
muRata,
GRM39X7R104KOI6A,
2xO.l-uF,I6-V,X7R
muRata,
GRM39X7R104KOI6A,
3xO.l-uF,I6-V,X7R
muRata,
GRM39X7R104K01BA,
4xO.l-uF,I6-V,X7R
C104
Snubber
Capacftor
muRata,
GRM39X7Rl02K050A,
l00O-PF, SO-V, X7R
muRata,
GRM39X7Rl02K050A,
l00O-PF, SO-V, X7R
muRata,
GRM39X7Rl02K050A,
2 x l000-pF, SO-V, X7R
muRata,
GRM39X7Rl02K050A,
3 x l00O-PF, SO-V, X7R
muRata,
GRM39X7Rl02K05OA,
4 x l000-pF, SO-V, X7R
Sanyo,
BTPB150M,
3 x 15o-uF, B.3-V, 20%
Sanyo,
4SP620M,
82Q-uF,4-V, 20%
Sanyo,
4SP82OM,
2 x 82Q-uF, 4-V, 20%
Sanyo,
4SP620M,
3 x 82Q-uF, 4-V, 20%
Sanyo,
4SP820M,
4 x 82Q-uF, 4-V, 20%
muRata,
GRM39X7R104K01BA,
0.1-uF, 16-V, X7R
muRata,
GRM39X7R104KOI8A,
0.1-uF, 16-V,X7R
muRata,
GRM39X7R104KOI6A,
2 x O.I-uF, 16-V, X7R
muRata,
GRM39X7Rl04K01BA,
3 x O.I-uF, 16-V, X7R
muRata,
GRM39X7Rl04KOI6A,
4xO.l-uF,I6-V, X7R
Cl05
Cloe
Output Bulk
Capac~or
Output
HI-Freq
Bypass
Capac~r
Ll0l
Input
Filter
Inductor
CoIiCraft,
DOI808C-332,
3.3-uH, 2.o-A
ColHronics,
UP2B-2R2,
2.2-uH,7.2-A
COiltronlcs,
UP2B-2R2,
2.2-uH,7.2-A
Coiltronlcs,
UP3B-1RO,
l-uH,12.5-A
CoiHronlcs,
UP3B-1RO,
l-uH, 12.5-A
Ll02
Output
Fitter
Inductor
CoilCrafl,
D03316P-332,
3.3-uH,B.l-A
CoiHronlcs,
UP3B-2R2,
2.2-uH, 9.2-A
Coittronlcs,
UP4B-1RS,
1.5-uH, 13.4-A
MicroMatals,
TB6-8190 Core wm
111 B, 1.Q-uH, 25-A
Pulse Engineering,
PI605,
l.o-uH, SO-A
Rl01
Lo-Side
Gate
Resistor
3.:Hlhm,
1/16-W,S%
3.:Hlhm,
1/16-W,S%
2x3.3-0hm,
3x3.:Hlhm,
4x3.3-0hm,
1/16-W,S%
1/16-W,S%
1/16-W,5%
Rl02
Snubber
Resistor
2.7-Qhm.
l/1o-W,S%
2.7-Ohm,
2x2.7-Ohm,
3x2.7-Ohm,
1/1O-W,S%
1/1O-W,5%
1/1O-W,5%
4x2.7-Ohm,
1I1o-W,5%
0101
Power
Swftch
Siliconlx, SI441 0,
NMOS, 13-mOhm
Siliconlx, S14410,
NMOS, 13-mOhm
Slllconlx, 2 x S14410,
NMOS, 13-mOhm
Sillconix, 2 x S14410,
NMOS, 13-mOhm
IR, 2x IRF7811,
NMOS,11-mOhm
0102
Synchronous
Swttch
Siliconix, S14410,
NMOS, 13-mOhm
Siliconlx, S1441 0,
NMOS, 13-mOhm
Siliconlx, 2 x S1441 0,
NMOS, 13-mOhm
Siliconlx, 3 x SI4410,
NMOS, 13-mOhm
IR, 4 x IRF1811,
NMOS,II-mOhm
Nominal Frequencyt
220 KHz
330 KHz
240KHz
140 KHz
168 KHz
Hysteresis Window
20mV
20mV
20mV
20mV
10mV
t Nominal frequency measured with Vo set to 2 v.
The values listed above are recommendations based on actual test circuits. Many variations of the above are
possible based upon the desires and/or requirements of the user. Performance of the circuit is equally, if not
more, dependent upon the layout than on the specific components, as long as the device parameters are not
exceeded. Fast-response, low-noise circuits require critical attention to the layout details. Even though the
operating frequencies of typical power supplies are relatively low compared to today's microprocessor Circuits,
the power levels and edge rates can cause severe problems both in the supply and the load. The power stage,
having the highest current levels and greatest dv/dt rates, should be given the greatest attention.
7-142
:lllEXAS
INSTRUMENTS
POST OFFICE BOX 655303 •. DALlAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A - SEPTEMBER 199B - REVISED MAY 1999
APPLICATION INFORMATION
frequency calculation
A detailed derivation of frequency calculation is shown in the application report, "Designing Fast Response
Synchronous Buck Regulators Using the TPS521(J', TI Literature number SLVA044. When less accurate results
are acceptable, the simplified equation shown below can be used:
(Vo x [VI - Vol x ESR)
fs == ..,--''-----------''--,(VI x L x Hysteresis Window)
Control Section
Below are the equations needed to select the various components within the control section. Details and the
derivations of the equations used in this section are available in the application report" Designing Fast Response
Synchronous Buck Regulators Using the TPS5210', TI Literature number SLVA044.
output voltage selection
Of course the most important function of the power supply is to regulate the output voltage to a specific value.
Values between 1.3 V and 3.5 V can be easily set by shorting the correct VID inputs to ground. Values above
the maximum reference voltage (3.5 V) can be set by setting the reference voltage to any convenient voltage
within its range and selecting values for R2 and R3 to give the correct output. Select R3:
R3« than VREF/IBIAS(VSENSE); a recommended value is 10 kQ
Then, calculate R2 using:
or
R2 and R3 can also be used to make small adjusts to the output voltage within the reference-voltage range
and/or to adjust for load-current active droop compensation. If there is no need to adjust the output voltage, R3
can be eliminated. R2, R3 (if used), and C7 are used as a noise filter; calculate using:
C7 =
150 ns
(R2 II R3)
slowstart timing
Siowstart reduces the startup stresses on the power-stage components and reduces the input current surge.
Siowstart timing is a function of the reference-voltage current (determined by R6) and is independent of the
reference voltage. The first step in setting slowstart timing will be to determine R6:
R6 should be between 7 kQ and 300 kQ, a recommended value is 20 kQ.
Set the slowstart timing using the formula:
C5 =
tss
::::
tss
(5 x RVREFB) - (5 x R6)
Where C5:::: Siowstartcapacitance in IlF
tss :::: Siowstart timing in J.LS
RVREFB Resistance from VREFB to GND in ohms ('" R6)
=
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-143
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A- SEPTEMBER 1998 - REVISED MAY 1999
APPLICATION INFORMATION
hysteresis voltage
A hysteretic controller regulates by self-oscillation, thus requiring a small ripple voltage on the output which the
input comparator uses for sensing. Once selected, the TPS5210 hysteresis is proportional to the reference
voltage; programming Vref to a new value automatically adjusts the hysteresis to be the same percentage of
Vref. The actual output ripple voltage is the combination of the hysteresis voltage, overshoot caused by internal
delays, and the output capacitor characteristics. Figure 20 shows the hysteresis window voltage (VHI to VLO)
and the output voltage ripple (VMAX to VMIN)' Since the output current from VREFB should be less than 500!IA,
the total divider resistance (R5 + R6) should be greater than 7 K.Q. The hysteresis voltage should be no greater
than 60 mV so R6 will dominate the divider.
VREFB
Hysteresis Window = 2 x VRS
RS
VHSYT
~
R6
...J...
Figure 19. Hysteresis Divider Circuit
Vo
VMAX
VHI
VREF
VLO
VMIN
Figure 20. Output Ripple
The upper divider resistor, R5, is calculated using:
R5
=
= V HYST ~) x R6
Hysteresis Window
x R6
Hysteresis Window)
-
(2 x VREFB -
(2 x 100)
Where Hysteresis Window = the desired peak-to-peak hysteresis voltage.
VREFB =selected reference voltage.
VHYST (%) = [(Hysteresis Window)NREFBj* 100 < VO(Ripple)(P-P) (%)
~TEXAS
7-144
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A - SEPTEMBER 1998 - REVISED MAY 1999
APPLICATION INFORMATION
current limit
Current limit can be implemented using the on-resistance of the upper FETs as the sensing elements. Select
R8:
R8«
VocP:s;
0.1V
:S;
10 kO
(100 x 100 nA)
/Bi8S(OCP)
(A recommended value is 1 kn)
The lOUT signal is used to drive the current limit and droop-circuit dividers. The voltage at lOUT at the output
current trip point will be:
VIOUT(TriP)
=
~x
RDS(ON) x TF)
NumFETs
x
/O(Trip)
=
Where NumFETS Number of upper FETS in Parallel.
TF = ROS(ON) temperature correction factor.
10(Trip) DeSired output current trip level (A).
=
Calculate R7 using:
R7 =
1)
(VI~~;~riP) _
x R8
Note that since ROS(ON) of MOSFETs can vary from lot to lot and with temperature, tight current-limit control (less
than 1.5 x 10) using this method is not practical. If tight control is required, an external current-sense resistor
in series with the drain of the upper FET can be used with HISENSE and LOSENSE connected across the
resistor.
droop compensation
Droop compensation is used to reduce the output voltage range during load transients by increasing the output
voltage setpoint toward the upper tolerance limit during light loads and decreasing the voltage setpoint toward
the lower tolerance limit during heavy loads. This allows the output voltage to swing a greater amount and still
remain within the tolerance window. The maximum droop voltage is set with R9 and R10. Select R1 0:
R1 0«
V DROOP(Min)
I Bias(DROOP,Max)
O.OW
:S;
:S;
(100 x 100 nA)
1 kn
(Again, a value of 1 kn is recommended)
The voltage at lOUT during normal operation (0 to 100% load) will vary from 0 V up to:
VIOUT(Max)
=
~ x ROS(ON) x TF)
Where 10(Max)
NumFETs
x
100Max)
=Maximum output load current (A).
~TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS. TEXAS 75265
7-145
TPS521 0
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A - SEPTEMBER 1998 - REVISED MAY 1999
APPLICATION INFORMATION
droop compensation (continued)
Then, calculate R9:
R9 = (V10UT(MaX) - 1) x R10
VDROOP
Where VDROOP = Desired droop voltage
At full load, the output voltage will be:
Vo = V REF x (1
+ ~~) -
VDROOP
using the TPS5210 when both 12 V and 5 V are available
When both 12 V and 5 V are available, several components can be removed from the basic schematic shown
above. R1, R4, and C9 are no longer required if 5 V is brought in directly to INHIBIT and LODRV. However, if
undervoltage lockoutforthe 5-V input is desired, R1 and R4 can be used to setthe startup setpoint. The INHIBIT
pin trip level is 2.1 V. Select R4:
R4«
VINH:5:
2.1V
:5: 210kQ
itNH(Max) (100 x 100 nA)
Then, set the 5-V UVLO trip level with R1:
R1 =
~VTriP
- 2V) x R4
2V
i-
LODRV
R1
INHIBIT
R4
Figure 21. 5-V Input with UVLO
using the TPS5210 when only 5 V is available
The TPS5210 controller requires 12 V for internal control of the device. If an external source for 12 V is not
available, a small on-board source must be included in the design. Total 12-V current is very small, typically
about 20 mA, so even a small charge pump can be used to generate the supply voltage. The power stage is
not voltage dependent, but component values must be selected for 5-V inputs and the frequency of operation
is dependent upon the power stage input voltage.
~TEXAS
INSTRUMENTS
7-146
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A- SEPTEMBER 1998 - REVISED MAY 1999
APPLICATION INFORMATION
L101
L102
QIOI
--
5V
/""'
~~
+
clof ~CI~i' "Cl0~
"
~~.
~
--
Vo
RI02
+
Cl0~ "
........
Clc£
~
;;:: f='CI04
RIOI
GND
~
~
,--PowerSlage
- - - - - - - - - - -
- -- ~
Control Sactlon
W
III
Q
Gi
:J:
CJ
:E
Z
-
- - - - - - - - - - -- - - - - - - - - - - -
we
Q
z ....
g
III ....
Z
sa lllg
:J: 9111
W
a:
Q
o.~~~
~'"
Boost
Circuli
C3\1
1:i
1 u~1
II>
--§
10
lO'
Rl ~
10.0 k ~
""
"
C6 II
0.0 I~U~ 1\
1%
ENABLE
N~te.!..
1%
;;:: F3_CB
2200 pF
Note 1:
VlDII - VlD4 User-selected
to aet output voltage.
DRV
BOOT
LOWDR
HIGHDR
DRVGND
BooTLO
LOHIB
HISENSE
LODRV
LOSENSE
BIAS
IOUTLO
SLOWST
INHIBIT
ANAGND
- : - VID4
VSENSE
VREFB
--~
VIOl
OCP
- --w-
VIDO
- - --s2IJ
- - -
- - - -- - - - - --
W
III
:E c~
e
....
II)
z
zw
9
Ii:
III
>
::::~
VCC
-""""""2lI"" VID3
VID2
R4
11.0 k •
C2
I uF
-
RTN
VHYST
~
R2
150
I~
~
~
I
B
100
."
R7
TPS5210
UI
K~
R5
3.9~K
DROOP
PWRGD
:>
~~I\
C7 II
.,
"
lOUT ~
C5
•
luuupF
0
f
C4
1 uF
II
R9
Y
".~"K
1\
lU.U K
v 'v
I 20~~
I
I
RB
1.00k
v
,~
RIO
1.00k
Figure 22. Typical S-V-Only Application Circuit
application examples
Various application and layout examples using the TPS5210 are available from Texas Instruments. This
information can be downloaded from http://www.ti.comlsc/docs/products/msp/pwrsp/y/defau/t.htm or received
from your TI representative.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-147
TPS521 0
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A-SEPTEMBER 1998- REVISED MAY 1999
APPLICATION INFORMATION
layout guidelines
Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult
than most general PCB design. The general design should proceed from the switching node to the output, then
back to the driver section, and, finally, place the low-level components. Below are several specific points to
consider before layout of a TPS5210 design begins.
1. All sensitive analog components should be referenced to ANAGND. These include components connected
to SlOWST, DROOP, lOUT, OCP, VSENSE, VREFB, VHYST, BIAS, and lOHIB.
2. Analog ground and drive ground should be isolated as much as possible. Ideally, analog ground will connect
to the ground side of the bulk storage capacitors on Va, and drive ground will connect to the main ground
plane close to the source of the low-side FET.
3. Connections from the drivers to the gate of the 'power FETs, should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
4. The bypass capacitor for the DRV regulator should be placed close to the TPS521 0 and be connected to
DRVGND.
5. The bypass capacitor for Vee should be placed close to the TPS5210 and be connected to DRVGND.
6. When configuring the high-side driver as a floating driver, the connection from BOOTlO to the power FETs
should be as short and as wide as possible. The other pins that also connect to the power FETs, lOHIB
and lOSENSE, should have a separate connection to the FETS since BOOTlO will have large peak
currents flowing through it.
7. When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from BOOT
to BOOTlO), should be placed close to the TPS5210.
8. When configuring the high-side driver as a ground-referenced driver, BOOTlO should be connected to
DRVGND.
9. The bulk storage capacitors across VI should be placed close to the power FETS. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
10. High-frequency bypass capacitors should be placed across the bulk storage capacitors on Va.
11. HISENSE and lOSENSE should be connected very close to the drain and source, respectively, of the
high-side FET. HISENSE and lOSENSE should be routed very close to each other to minimize
differential-mode noise coupling to these traces. Ceramic decoupling capacitors should be placed close to
where HISENSE connects to Vin, to reduce high-frequency noise coupling on HISENSE.
~TEXAS
7-148
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
OBTPACKAGE
(TOP VIEW)
• Independent Dual Channels
• Hysteretic Control for Fast Transient
Response
INV1
NC
SOFTSTART1
NC
• 4.5-V to 25-V Input Voltage Range
• Adjustable Output Voltage Down to 1.2 V
• Synchronous Rectifier Enables Efficiencies
of >95%
LH1
OUT1_u
LL1
3
OUT1_d
OUTGND1
TRIP1
Vee SENSE
TRIP2
Vref5
REG5V_IN
OUTGND2
OUT2_d
• Minimized External Component Count
• Separate Standby Control and Over Current
Protection
• Low Supply Current ••• 0.8 mA Typ
STBY2
• 3D-Pin TSSOP
• Low Standby Current (1-1JA maximum)
Vee
COMP
SOFTSTART2
NC
INV2
• EVM Available (TPS5602EVM-121)
description
LL2
OUT2_u
LH2
The TPS5602 is a dual-channel synchronous
Ne - No internal connection
buck switch-mode power supply controller
featuring very fast feedback control and minimized component count. By using the hysteretic control method,
it is ideal for high-transient current applications, such as 'C6000 and multiple 'C54x DSPs. The TPS5602 is
designed specifically for DSP applications that require high efficiency. Since both channels are independent,
the up and down power sequencing can be easily achieved by properly setting the standby pins. The wide input
voltage and adjustable output voltage make the TPS5602 suitable for many applications.
typical design
5V
I
D1~.L-,
.:LC3
T~
"",GN=:.DI-+--+-- - - '
R3
U1
I
I
TPS5602
R2
~
~7v-L-'lL(;'NV;;"--~,,u..-\-iII~
'C4--+I~
..9Q~1-H1"LiL1i1.... ~.~~
- ' - NO
C1 --.----"-ISOFTSTARfI
HI::..:
~ Ne
~
CT
~NC
t-=-l-.LJCND
C2-t---"-lREf'
t--JII\IF'
,---+--+--,->..jSTBfl
OUT1~'
"
I.i$.\
1\
IJ
ILLI
OUT1_'*"""---+----'
---f
OUTCNDI 28
TRIPI
AS
VCC_SfNS
TRlP2f"""---+---;R::-.NI/'---;
h
'vA::FS.. .22.. .a
I ~
~
~ :::~''I--:--'''--+---~--+---1
~
L-.J.t
R1
a-1!.
R4 "
COMP
OUT2_'*'""'---+-------,
SOfTSTART2
Li2l-"'-'----+----,
Ne
.'"
OUT2_ u
LH
~
"
V
j~)
&
1L--__
+-fi8\
C6~
l2
-
OUT>
3.3V
~
---L
A..
~
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright @ 1999, Texas Instruments Incorporated
7-149
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217-JUNE 1999
AVAILABLE OPTIONS
PACKAGE
TA
TSSOP
(DBT)
-40°C to 85°C
TPS56021DBT
TPS5602IDBTR
EVM
TPS5602EVM-121
functional block diagram
SFTl
LHl
INVl
>-_----¢-"O"'-'UTCU
LLl
::x>-+---o--",OU",Tl_d
,---+---¢-=-O:;.cUTGNDl
h-t--¢--T"R,IPl
VccSENSE
c.......-+-----<>---
Comp
TRIP2
GND
r--+---¢--,O-,-UTClN02
INV2
LL2
LH2
VREF5
Vee
STBYl
STBY2
_-"'RE::.F-¢-"l.c!.>l85"'--'-V_ _ _ _-'=...J"...J--L~
___:::'.1,IT:J_-!.!R~EG5Vin
~TEXAS
INSTRUMENTS
7-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 - JUNE 1999
Terminal Functions
TERMINAL
NAME
NO.
110
DESCRIPTION
COMP
12
1/0
Voltage monitor comparator input
CT
5
1/0
The oscillator frequency external capacitor connection
GND
7
INV1
1
Control GND
I
CH1 hysteretic comparator inverting input
CH2 hysteretic comparator inverting input
INV2
15
I
LH1
30
1/0
CH2 high-side gate drive boost capacitor input
LH2
16
1/0
CH1 high-side gate drive boost capacitor input
LL1
28
1/0
CH1 high-side drive and current protection
LL2
18
1/0
CH2 high-side drive and current protection
NC
2,4,6,14
OUT1 _d
27
1/0
CH1 low-side gate drive output
OUT2_d
19
CH2 low-side gate drive output
OUTCu
29
OUT2_u
17
0
0
0
OUTGND1
26
OUTGND2
20
REF
8
0
REG5V_IN
21
I
SOFTSTART1
3
CH1 high-side switch output
CH2 high-side switch output
OutputGND 1
OutputGND2
1.185-V reference voltage output
External 5-V input
SOFTSTART2
13
1/0
1/0
STBY1
9
I
CH1 standby control
STBY2
10
I
CH2 standby control
TRIP1
25
I
CH1 output current control input
TRIP2
23
I
CH2 output current control input
VCC
Vref5
11
I
Supply voltage input
22
0
5-V internal regulator output
VCCSENSE
24
I
Supply voltage sense input
CH1 soft start control external capacitor connection
CH2 soft start control external capacitor connection
detailed description
vref (1.185 V)
The reference voltage is used for the output voltage setting and the voltage protection (COMP).
vref (5 V)
An internal linear voltage regulator offers a fixed 5-V voltage as the bootstrap voltage so that the design for the
bootstrap is much easier. The tolerance is 6%. The extra current capability can also be used to power external
circuitry.
5·V switch
If the internal 5-V switch senses a 5-V input from REG5V pin, the internal 5-V linear regulator will be
disconnected from the MOSFET drivers. The external 5-V will be used for the low-side driver and the high-side
bootstrap, thus increasing the efficiency.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 76265
7-151
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 - JUNE 1999
detailed description (continued)
hysteretic comparator
Each channel has a hysteretic comparator to regulate the output voltage of.the synchronous-buck converter.
The hysteresis is set internally and is typically 8.5 mY. The total delay from the comparator input to the driver
output is typically 500 ns from low to high and 350 ns from high to low.
low-side driver
The low-side driver is designed to driver low-Rds(on) n-channel MOSFETs. The maximum drive voltage is 5 V
from Vref5. The current rating of the driver is typically 1 A, source and sink.
high-side driver
The high side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
1 A, source and sink. When configured as a floating driver, the bias voltage to the driver is developed from the
Vref5, limiting the maximum drive voltage between OUTxU and LLx to 5 V. The maximum voltage that can be
applied between LHx and OUTGNDx is 30 V.
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turnon time of the MOSFETs drivers. The typical deadtime from
low-side-driver-off to high-side-driver-on is 75 ns and 164 ns from high-side-driver-off to low-side-driver-on.
current protection
The current protection is achieved by senSing the high-side power MOSFET drain-to-source voltage drop during
on-time through VCCSense and LLx pins. An external resistor between Yin and TRIPx pin with the internal
current source connected to the current comparator negative input adjusts the current limit. The typical internal
current source current is 15 J.IA. When the voltage on the positive pin is lower than the negative pin, the current
comparator turns on the trigger, and then activates the oscillator. This oscillator repeatedly resets the trigger
until the overcurrent condition is removed. The equation for the external resistor selection is:
R l t
em
= Rds(on)
x (Itrip + Iind(p-p)/2)
0.000015
Where Rds(on) is the MOSFET turnon resistance; Itrip is the required trip current; lind(p-p) is the peak-to-peak
inductor ripple current. Itrip must be greater than 0.5xlind(p-p). The tolerance is ±30%.
COMP
COMP is an internal comparator used for any voltage protection such as the output under-voltage protection
for DSP power applications. If the core voltage is lower than the setpoint, the comparator turns off both channels
to prevent the DSP from damage.
SOFT1, SOFT2
Separate soft-start terminals make it possible to set the sequencing of each output for any possibility. The
capacitor value for a start-up time can be calculated by the following equation:
C=2x T
(IlF)
Where C is the external capacitor value, T is the required start-up time in (ms).
STBY1, STBY2
Both channels can be switched into standby mode separately by grounding the STBY pin. The standby current
is less than 1 J.IA. The STBY pins can be used for sequencing.
UVLO
When the input voltage rises to about 3.8 V, the IC is turned on, ready to function. When the input voltage falls
below the turnon value, the Ie is turned off. The typical hysteresis is 149 mY.
~TEXAS
INSTRUMENTS
7-152
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 - JUNE 1999
absolute maximum ratings over operating free-air temperature (see Note 1) (unless otherwise
noted)t
Supply voltage, Vee .............................................................. -0.3 V to 27 V
Input voltage, VI, INV ............................................................... -0.3 V to 7 V
Softstart ........................................................... -0.3 V to 7 V
COMP ............................................................ -0.3 V to 6 V
REG5V_IN ........................................................ -0.3 V to 6 V
STBY ............................................................ -0.3 V to 15 V
TRIP ............................................................. -0.3 V to 15 V
Maximum Driver current .................................................................... 3 A
Output voltage, LLx ............................................................... -0.3 V to 27 V
Output voltage, OUTx_u ........................................................... -0.3 V to 32 V
Output voltage, OUTx_d ............................................................ -0.3 V to 7 V
Power dissipation (TA =25°C) ............................................... See Dissipation Table
Operating free-air temperature range, TA ........................................... -40°C to 85°C
Operating virtual junction temperature range, TJ ............................................. 125°C
Storage temperature range, Tstg .................................................. -55°C to 150°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' Is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND terminal.
DISSIPATION RATING TABLE
PACKAGE
DBT
TA = 25°C
POWER DISSIPATION
TA <: 25°C
DERATING FACTOR
874 mW
TA = 85°C
POWER DISSIPATION
6.993 mW/"C
454 mW
recommended operating conditions
MIN
NOM
4.5
Supply voltage, VCC
25
INV1/2
6
COMP
6
SOFTSTART1/2
Input voltage, VI
MAX
UNIT
V
6
REG5V_IN
5.5
STBY1/STBY2
12
TRIP112
VCC_SENCE
25
Operation junCtion temperature range, TA
-40
electrical characteristics over recommended TA
(unless otherwise noted)
85
V
°C
= -40°C to 85°C temperature range, Vee = 7 V
reference voltage
PARAMETER
MIN
TYP
MAX
TA=25°C,
TEST CONDITIONS
Ivref = 50 jIA
1.167
1.185
1.203
VI =4.5 Vt025 V,
1=1j1At01mA
1.155
1=50jIA
Vref
Reference voltage
VI/Reain)
Line regulation
VCC = 5.5 Vto 25 V,
VI/Regl)
Load regulation
1=1jlA101mA,
1.215
UNIT
V
0.2
12
mV
0.5
10
mV
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
7-153
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217-JUNE 1999
quiescent current
PARAMETER
TEST CONDITIONS
ICC
Operating current without switching
Both STBY >2.5 V,
VI =4.5 Vt025 V
No switching
l(eeS)
Stand-by current
Both STBY <0.5 V,
VI = 4.5 V to 25 V
MIN
TYP
MAX
0.8
1.5
UNIT
mA
1
1000
nA
MIN
TYP
MAX
UNIT
5.5
8.5
11.5
mV
hysteretic comparator
PARAMETER
Vhvst
Hysteresis window
VH(off)
Offset voltage
IHlbies)
Bies current
TEST CONDITIONS
TTL input signal
t(HLn, t(LHTI
Propagation delay from INV to OUTxU;
t(LH)
2
mV
10
pA
230
10 mV overdrive on hysteretic band signal
tlHIl
500
650
350
500
TYP
MAX
ns
t Vhys is assured by design.
; The delay time in the table includes the driver.
driver deadtlme
PARAMETER
TEST CONDITIONS
MIN
t(DRVLH)
Low side to high side
90
tlDRVHL)
High side to low side
160
UNIT
ns
standby
PARAMETER
IH
High-level input voltage
IL
Low-level input voltage
Ttum-on
Ttum-off
JI Propagation delay
TEST CONDITIONS
MIN
TYP
MAX
STBY1, STBY2
UNIT
V
2.5
0.5
V
7.2
Staby to driver output
I1S
4.8
5 V regulator
PARAMETER
Vo
VI(Re!!in)
Output voltage
: Load regulation
VI (ReglL
lOS
Short~ircuit
output current
TEST CONDITIONS
MIN
TYP
4.7
1= 10mA
MAX
5.3
Vee =5.5 Vto25 V,
1= 10mA
20
1=1 mAtol0mA,
Vee = 5.5 V
40
Vref=OV
V
mV
mA
80
electrical characteristics over recommended free-air temperature range, Vee
otherwise noted) (continued)
UNIT
=7 V (unless
5-V Internal switch
PARAMETER
VTLH
TEST CONDITIONS
: Threshold voltage
VTHL
Rson
On-time resistance
Vhys
Hysteresis
TYP
4.9
4.1
4.7
2.5
~TEXAS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MAX
4.2
50
INSTRUMENTS
7-154
MIN
8
250
UNIT
V
0
mV
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 - JUNE 1999
current limit
PARAMETER
TEST CONDITIONS
Internal current source
MIN
TYP
MAX
10
15
20
2.5
Input offset voltage
UNIT
IJA
mV
UVLO
PARAMETER
VCTLH)
VCTHLl
TEST CONDITIONS
II Threshold voltage
Hysteresis
MIN
TYP
MAX
UNIT
3.6
4.2
3.5
4.1
50
250
mV
MAX
UNIT
V
driver output
MIN
TYP
OUT_u sink current
VO=3V
TEST CONDITIONS
0.5
1.2
OUT_u source current
VO=2V
-1
-1.7
OUT_d sink current
VO=3V
0.5
1.2
OUT_d source current
VO=2V
-1
-1.7
Rise time
High side driver is GND relerenced,
Input: INV = 0 V -3 V,
Frequency = 200 kHz,
trltf= 10 ns,
PARAMETER
High side driver is GND referenced,
Input: INV = 0 V -3 V,
Frequency = 200 kHz,
trftf= 10ns,
Fall time
CL=2200pF
25.6
CL = 3300 pF
30.8
CL = 2200 pF
23.2
CL = 3300 pF
25.2
A
A
ns
ns
Softstart
TEST CONDITIONS
PARAMETER
I(CTRL)
Soitstart current
MIN
TYP
MAX
1.8
2.5
3
0.92
Maximum discharge current
UNIT
I1A
mA
COMPt
PARAMETER
Threshold voltage
Tum on
Turn off
t
IPropagation del~ 50% dU~ cycle,
I No capacitor on
OMP or
UT_u pin,
I
TEST CONDITIONS
I
MIN
TYP
MAX
UNIT
1
1.1
1.25
V
452
Frequency = 200 kHz
ns
384
The delay time in the table includes the drivers.
oscillator
PARAMETER
TEST CONDITIONS
Frequency without Ct
Frequency with Ct
Ct= 100pF
MIN
TYP
MAX
UNIT
202.4
kHz
67.5
kHz
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-155
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217-JUNE 1999
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT (BOTH CHANNEL STANDBY)
vs
SUPPLY VOLTAGE
QUIESCENT CURRENT (BOTH CHANNELS ON)
vs
SUPPLY VOLTAGE
950
r---------,--------.
160.0
140.0
J,
~ :-TJ=25°C ..... ~
3
3
I
TJ = 125°C -
II
aI
!
~
'!5
t
0
~
a
2
I
I
~
>-
2.5
2
1.5
:>2"
c
~
III
III
0
0.1
0.5
I(src) - Driver Source Current - A
0.5
0
0.1
0.5
I(slnk) - Driver Sink Current - A
Figure 3
Figure 4
~TEXAS
INSTRUMENTS
7-156
10.0
Figure 2
DRIVE OUTPUT VOLTAGE
vs
DRIVE CURRENT (SOURCE)
5
7.0
vcc - Supply Voltage -
6
V
Ty 25°C ;:""TJ '-i-400 C -
Figure 1
>
\?
./
V
/
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
25.0
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 - JUNE 1999
TYPICAL CHARACTERISTICS
SOFTSTART CAPACITANCE
CURRENT-PROTECTION SOURCE CURRENT
vs
vs
SOFTSTART TIMING
SUPPLY VOLTAGE
C
I
C 13.8
I
~
~
j,t'
0.1
I
./
V
.... 1'
I
0.01
(J-
~
13.6
~c
13.4
J
TJ = 25°C
TJ=-40°C
J.
1
12.6
100
10
T(start) - Softstart TIming - ma
4.5
7.0
10.0
15.0
20.0
VCC(trlp) - Supply Voltage - V
FigureS
UVLO HYSTERESIS VOLTAGE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.5
0.20
>
GI
2.0
......
~
l!
0
.c
1.5
>
I
I'--. t......
&
"
I
.c
~
~
1.0
~ f'....
I
I
'>;
./
0.18
I
25.0
Figure 6
STANDBY THRESHOLD VOLTAGE (H-L)
I
I
l-a 12.8
V
0.001
~
TJ = 125°C
i:
1::
i
14.0
:::I.
U.
:::I.
0.5
i
i'.
~ t'
I
~
,. .,/
0.16
/'
0.14
V
0.12
0.10
I'
;'
V
./
0.08
0.06
0.04
.t:J
Ii
>-
0.02
0.0
-40
-20
0
25 50
70
95
TJ - Junction Tempereture - °C
125
0.00 -40
-20
0
25
50
70
95
TJ - Junction Temperature - °C
Figure 7
125
Figure 8
:'I
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-157
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 -JUNE 1999
TYPICAL CHARACTERISTICS
STANDBY THRESHOLD (L-H)
UVLO THRESHOLD VOLTAGE
vs
VB
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.5
3.80
>
3.78
I
>
I
t
~
I
CD
3.76
3.74
l--
3.72
",.
V
-
I.-
i
2.0
..... .........
~
:!2
0
.c
II
~
1.5
~ """-
.... r--.....
(:.
3.70
I
(:.
3.68
~
3.66
f
1.0
->
'"
.........
0.5
3.64
3.62
3.60
0.0
-40
-20
0
25
50
70
95
TJ - Junction Temperature - °C
125
-40
-20
25
50
0
70
95
TJ - Junction Temperature - °C
Figure 9
Figure 10
VREF5 VOLTAGE
SOFT START CHARGE CURRENT
vs
vs
JUNCTION TEMPERATURE
VREF5 CURRENT
5.1
-3.0
c(
::I.
5.0
-2.5
>
I
j
!
I
I
-2.0
III
4.9
i
~
-1.5
I
4.8
If
w
II:
>
-1.0
4.7
4.6
-0.5
4.5
0.0
-40
-20
0
25
50
70
95
TJ - Junction Temperature - °C
125
0
Figure 11
-10
-20
-30
-40
Vref5 - Current - mA
Figure 12
~TEXAS
7-158
125
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
-SO
J'
VOUT2 i)~ ~ I
YOUT2 I
~.u
~
l2
T02
,r-;-:--
lc,
Vin,
'II.,
AOND
.
...
AGND :
7
idi
PGND:~
-
-
-
-
-
-
-
-
-
-
§
fil-
~~~
i~~d
!;it::
.~
§!tI1
i~
I
.--
"lrtoUt1 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
~
Rl
TP3
1
CJ 2200 pI=' TP4
I
-------"ltU
..
~
Openf'Open,
~~
~
_
~
:
-
-
-
-
-
-
O~
C9
2.2 uF
."'-
1 uF TPS
-
~19uF
-
-
-
-
-
-
f'
TP14
L3
a4~
si4410rn
0UT1
1.
T022
27
e17:~
3.3 V
TP21
I
TP28
I~-
23 TP19
YREF5~
C,~
Cl~4-=J
5.1K
O.on
~
.7
TP'.
TP24
,--:.:..;c'---------'
TP23
15
{.
To2
~
U)
~
.:-t
z
::c
Z
is
::c
m
"'TI
l!
"'I'J
0
::D
i!:
Open
vee
LH2pL,
r-
(5
TP20
0UT0ND1P2...""'"""+-=,--_-=-~
R10
:J>
.r
"a
"a
(;
470 uF
e2l
19 uF
lIB
'-..--...-jvo'U12
S;;'~44'0DY
Q3
c:
~
~
2~2' ~F
J0
c
W13
I
LL46
LHt
8 REF
~~
C8 2200 F
1.21K
-
-
C4\1
IMnp2<.L'_ _+-'W'or-.,
129
~f! b
---1.Z. COUP
OUT2Df.J''''.--+-'''·=----~-_t_+-'
C7 \a290 P~P9
:: SOASTART2 Wf.J:"'7·--+-__
.'1".---.---~-+-'
TP,
-
-
TRIM 25 TPte
•
11
L-'-
-
¥
10 STBY2
~20~
~~
-
NC
7 ONO
9 SJ'BY1
I
V
Alternate
Sequencing
Section
-
C6
I
1-.,-.--+-"1=-'
en
5 CI
R14'--' Zorn
~R16:
U2
l--!
Open
I
~
-
~NC
:s SOFrSTART1OUT''"
U.l 28
--:-NC
CS
I
Open
-
TPS5602
INV1
R17
-
Ul
~;4~70
7
•••
-
-
WIll
+
-
9e9
Xl
_
-
Control Section
R6
TP53.305-'8
l'~-
R13
TP16
TPl7
" 5
~.
1.SV
+
68~'~F r
VOUTt
I
SENSE2
ela
~
_-+-=STP~'5tiT~16n-
-
Sequencing Section'
UJ
u
S;~"~4'.DY
02
leuF
>-;":-~
VOUTl :~
VOUT1 L _ J
a,~
Si4410DY
+
Open
PCNO:
VOUTl:~
=
~
I
VI
"C'2
2.2uF
LL46
,
5-9 V
5A
j.BV
4A
iii
z
n
-<
n
z
(5
Vo
I
I
n
~
3.3 V
3A
0
z
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-'-_ _ _ _.J
_I _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
.!
-I
::u
0
rrm
Figure 13. EVM Schematic Diagram
::u
"'TI
0
en
!<:
en
'"~
c::
J
r--..
,I
89
3.315
I
~
91
90
3.3-V OUTPUT LOAD REGULATION
3.32
t
~
-
!
--
3.31
I
o
88
> 3.305
87
86
10
20
30
40
50
60
70
80
90
3.3
100
o
0.1 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Percentage of Output Current on Both Channels - %
10 _ Output Current - A
Figure 16
Figure 17
3.3-V LINE REGULATION
1.8-V OUTPUT LOAD REGULATION
3.35
1.8
/'
3.34
> 1.795
I
...
t
~
i
o
~/
>
I
3.33
CIl
~
~
1.79
'5
~
- r-
I
o
V
3.32
0
I
,../
3.31
~
.,/
V
V"
~
>' 1.785
3.3
1.78
o
3.29
0.1 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
4.5 5
Figure 18
9 11 13 15 17 19 21 23 25
Figure 19
~TEXAS
7-164
7
VI- Input Voltage - V
10 - Output Current - A
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 - JUNE 1999
APPLICATION INFORMATION
1.8-V OUTPUT LINE REGULATION
OUTPUT VOLTAGE RIPPLE
1.805
1.8
>
~ 1.795
1
I
,/
I
V
v ""
50mV/div
1.79
-
I
-
,/
~
~
",
V
,/
f--
~
.A
t'l...
. JV
I
e.v = 48 mV
-
~- ."Sf-
, .Il ~ -~ I.\...- "iL.I~~
(
1--
1.785
1.78
1.775
VI=5V
5~~IV
4.5 5
7
9 11 13 15 17 19 21
VI-Input Voltage - V
23 25
Figure 20
Figure 21
POWER-UP SEQUENCING
POWER-DOWN SEQUENCING
I
200ms
3.3 V
I
~
1 V/dlv
1 V/dlv
1~!v
rr
1
I~
3.3 V
.,
1.8V
I
!.VI=5V
I
:..;
\
[\,..
-
r-
1 msldlv
100 msldlv
Figure 22
Figure 23
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-165
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217-JUNE 1999
APPLICATION INFORMATION
TRANSIENT RESPONSE (OVERSHOOT)
4- 9OAlIJ.S
1 Aldlv
A=100mV
... -- -/l
- -
-- ~- -
v
A • .1\.
1"1
-t-- t--
IA.
~
~
"-J
100mV/dlv
..:i
51J.S/div
Figure 24
TRANSIENT RESPONSE (UNDERSHOOT)
C - f- 6.5A1IJ.S
1 Aldlv
AV=75mV
~ 1'1/
/
.~
"-..... ;;rA
~~
-PI'J I\..
100mV/dlv
51J.S/div
,I J
Figure 25
~TEXAS
7-166
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS, TEXAS 75265
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217-JUNE 1999
APPLICATION INFORMATION
Table 1. SLVP121 Bill of Materials
REF.
MFR.
PART NUMBER
DESCRIPTION
Cit
SIZE
Open
C2
Sid
Capacitor, ceramic, 470 pF,16 V, X7R, 20%
805
C3
Std
CapacHor, ceramic, 2200 pF,16 V, X7R, 20%
805
C4
GRM235Y5Vl06Z016A
muRata
cst
CapacHor, ceramic, 10 I1F, 16 V, Y5V
1210
Open
805
C6
Sid
CapacHor, ceramic, 1 I1F, 16 V, X7R, 20%
1206
C7
Std
Capacttor, ceramic, 2200 pF, 16 V, X7R, 20%
805
C8
Std
CapacHor, ceramic, 2200 pF, 16 V, X7R, 20%
805
C9
GRK316F225ZG
Taiyo Yuden
Capacttor, ceramic, 2.2 I1F, 35 V, X7R, 20%
1206
Cll
GRK316F225ZG
TaiyoYuden
Capacitor, ceramic, 2.211F, 35 V, X7R, 20%
1206
C12
GRK316F225ZG
TalyoYuden
CapacHor, ceramic, 2.2 I1F, 35 V, X7R, 20%
1206
C13t
Sid
Open
805
C14t
SId
Open
805
CIS
10TPB220M
SANYO
Capacitor, electrolytic, 220 I1F, 10 V, 20%
10xl0mm
C16
2R5TPB680M
SANYO
Capacttor, POSCAP, 680 I1F, 2.5 V, 20%
7.3x4.3mm
C17
4TPB470M
SANYO
CapacHor, POSCAP, 470 I1F, 4 V, 20%
7.3x4.3mm
C18
GMK325Fl06ZH
TaiyoYuden
Capacitor, ceramic, 10 I1F, 35 V
1210
C21
GMK325Fl06ZH
TalyoYuden
CapacHor, ceramic, 10 I1F, 35 V
1210
Dl
SD103·AWDICT·ND
Digikey
Diode, Schottky, 40 rnA, 200 rnA, 400 mW
3.5xl.5mm
D2
SD103·AWDICT·ND
Digikey
Diode, Schottky, 40 rnA, 200 rnA, 400 mW
3.5xl.5mm
Jl
SI132-12-ND
Sullins
Header, right angle, 12-pln, 0.1 ctrs, 0.3" pins
Digikey, SI132-12-ND
L2
D03316P-682
Coilcraft
Inductor, 6.811H, 4.4 A
0.5xO.37in
L3
Ql-Q4
Rl
D03316P-l03
Coilcraft
Inductor 10 I1H, 3.9 A
0.5xO.37in
Si441 DY Rev. A
Siliconix
MOSFET, N-Ch, 30 V, 10-A, 0.013 n
S0-8
Sid
Resistor, SMD, MF, 1.74 kn, I/BW, 1%
805
R4
Sid
Resistor, SMD, MF, 680 n, 1/8W, 1%
805
R6
Std
Resistor, SMD, MF, 910 n,1/8W, 1%
805
R7
Std
Resistor. SMD, MF. 1.21 kn, I/BW. 1%
805
R8
Std
Resistor, SMD, MF, 15 n, 1/8W, 5%
805
R9
Std
Resistor, SMD, MF, 15 n, 1/8W, 5%
805
RIO
SId
Resistor, SMD, MF, 5.1 kn, I/BW, 5%
805
Rll
Std
ReSistor, SMD, MF, 5.1 kn, 1/8W, 5%
805
R13T
Std
Open, resistor, SMD, MF. 3.3 kn, 1I8W, 5%
805
R14
Std
Open, resistor, SMD, MF, kn, l/BW, 5%
805
R15T
Sid
Open, resistor, SMD, MF, 1 kn, 1/8W, 5%
805
R16t
Std
Open, resistor, SMD, MF, 200 kn, 1/8W, 5%
805
R17t
Std
Open, resistor, SMD, MF, 10 kn, 1/8W, 5%
805
R18t
Std
Open, reSistor, SMD, MF, 1 kn, I/BW, 5%
805
R19T
SId
Open, resistor, SMD, MF, 10 kn, 1/8W, 5%
805
R20T
Std
Open, resistor, SMD, MF, 0 kn
805
Ul
TPS5802DBT
TI
Dual channel controller
TSSOP 3O-pin
U2T
TLV1391
TI
Open, single Comparator
SOT-23
U3
TPS3305-18D
TI
Supervisor
D
NOTE: This table is for 5-9 V input voltage and 3.3 V/l.S V only.
Any components with t are for optional test purpose only.
t
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-167
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217-JUNE 1999
APPLICATION INFORMATION
To change the EVM operating specifications, several suggestions are shown in the following table.
HIGH INPUT VOLTAGE
(TO 25 V)
2.5 V OUTPUT VOLTAGE
LOW·COST POWER
SEQUENCING
Change Rl to 1 1<.0
Remove U3
Add R15 (1 1«0)
Change Rt to 1.2 1<.0
AddU2
Change C15 to ELNA
RV-35V221MH10-R (35 V, 220 11F)
Change U3 to TPS3305-25D
Add R13, R16, R17, R19
TOPSIDE
BOTTOM SIDE
7-168
:illExAs
INSTRUMENTS
POST OFFICE eox 855303 • DALLAS. TEXAS 75285
COMPONENT SECOND SOURCE
Ql-4
IR7811 for higher efficiency
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217-JUNE 1999
APPLICATION INFORMATION
BOARD ASSEMBLY
~TEXAS
INSTRUMENTS
POST OFFICE BOX 6S5303 • DALLAS. TEXAS 75285
7-169
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217-JUNE 1999
APPLICATION INFORMATION
NOTE: All wire pairs should be twisted.
Figure 26. Test Setup
~TEXAS
7-170
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPSS6100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR S-V INPUT SYSTEMS
• Single-Channel, 5-V Controller
• Synchronous-Rectifier Drivers for Greater
Than 90% Efficiency
• Useable for All Common DSP Supply
Voltages - Popular Output Voltage Options
Set With Program Pins
• EVM Available
• Ideal for Applications With Current Ranges
From 3 A to 30 A.
• Hysteretic Control Technique Enables Fast
Transient Response - Ideal for 'C6000 or
Multiple 'C5000 Applications
• Low Supply Current
- 3 rnA in Operation
- 90 J,LA in Standby
• Power Good Output
• 28-Pin TSSOP PowerPADTM Package
PWPPACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
lOUT
NC
OCP
VHYST
VREFB
VSENSE
ANAGND
SlOWST
BIAS
lODRV
lOHIB
DRVGND
lOWDR
DRV
28
27
26
25
24
23
22
21
20
19
18
PWRGD
VPO
VP1
VP2
VP3
VP4
INHIBIT
IOUTlO
lOSENSE
HISENSE
BOOTlO
HIGH DR
BOOT
Vce
17
16
15
NC - Not Connected
description
The TPS56100 is a high-efficiency synchronous-buck regulator controller which provides an accurate
programmable supply voltage to low-voltage digital signal processors, such as the 'C6x and 'C54x DSPs. An
internal 5-bit DAC is used to program the reference voltage from 1.3 V to 2.6 V. Higher output voltages can be
implemented using an external input resistive divider. The TPS561 00 uses a fast hysteretic control method that
provides a quick transient response. The propagation delay from the comparator input to the output driver is
application example
5V~~------------~--------~~;=E:====E:~'---~
GND~
cn;)
-
TPS56100
--
~)
-
1.5V
~
~r:
CVDD
DSP
,/
GND
'AA
y
..a..
•
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorpgrated.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
7-171
TPSS6100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR S-V INPUT SYSTEMS
SLVS201A-JUNE 1999- REVISED JULY 1999
description (continued)
less than 300 ns, even at maximum output current. Overcurrent shutdown and crossover protection combine
to eliminate destructive faults in the output MOSFETs, thereby protecting the processor during operation. The
slowstart current source is proportional to the reference voltage, thereby eliminating variation of the slowstart
timing when changes are made to the output voltage. When the output drops to less than 93% of the nominal
output voltage, PWRGD will pull the open-drain output low. The overvoltage circuit will disable the output drivers
if the output voltage rises more than 15% above the nominal output voltage. The TPS561 00 also includes an
inhibit input to control power sequencing and undervoltage lockout thereby insuring the 5-V supply is within
limits before the controller starts. The 2-A MOSFET drivers can power multiple MOSFETs in parallel to drive
single or multiple DSPs and load currents up to 30 A. The high-side driver can be configured as a
ground-referenced driver or as a floating bootstrap driver with the included internal bootstrap Schottky diode.
The TPS56100 is available in a 28-pin TSSOP PowerPAD package, which increases thermal efficiency and
eliminates bulky heat sinks.
AVAILABLE OPTIONS
PACKAGES
TJ
TSSOPt
(PWP)
EVM
O°C to 125°C
TPS561000PWP
TPS56100EVM-12B
t The PWP package IS also available taped and reel. To order, add an R
to the end of the part number (e.g., TPS561 OOOPWPR).
~TEXAS
7-172
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
a
C
:::J
r
Vcc
VPO~
5
VP1
VP2
VP3
VP4
ANAGND
17
PWRGD
LOSENSE
28
0"
IOUTLO HISENSE
120
21
:::J
!..
119
0-
0'
n
lI"
Q.
~.
V
INHIBIT 22
>--'-
lOUT
iii
3
2x
~
OCP
3
........
~-
::a::
~~~
•
~~d
~~~
~~~
i~
5
':f
m
HIGHDR
."
."
o
VSENSE
SLOWST~8-----------.
in
z
Analog Bias
Analog
Bias
IVREFB
---5-
CJ)
9
oil
BIAS
Q
14 DRV
c
en
j
Shutdown
'----,
VP
MUX
1'0..._
"'0
"'0
I
--v-
&-1;-,"'1r"
I VREF,
16 BOOT
'117 HIGHDR
o
00
!<
::em
:D
f:D c
c..UI "'0
00'"
~oen
Shutdown
I
2<:"'0
•
~z!:(
l8"'Oo
ICO
:D-f
VPO VP1 VP2
!
C:l
VP3 VP4 VREFB
6
VSENSE
~en!i -f
LOHIB
LODRV
m<:D "'0
~enoen
c-fr- UI
! 4.46 V at startup,
VPcode",,11111,
VSOOTLO=OV
3
10
VINHISIT = 5 V,
Vee> 4.46 V at startup,
eHIGHDR = 50 pF,
fSWX = 200 kHz,
VPcode",,11111,
VSOOTLO = 0 V,
eLOWDR = 50 pF,
See Note 3
5
VP code ",,11111, Vee> 4.46 V at startup,
VSOOTLO = 0 V,
fSWX = 200 kHz (see Note 3)
V
mA
VINHISIT = 0 V or VP code = 11111 or Vee < 3.8 V at startup,
VSOOT=13V,
VSOOTLO=OV
VINHISIT = 5 V,
VSOOT= 13V,
eHIGHDR = 50 pF,
UNIT
90
2
j.LA
mA
NOTE 3: ThiS parameter IS ensured by deSign and IS not production tested.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-183
TPS56100
HIGH·EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR S-V INPUT SYSTEMS
SLVS201A-JUNE 1999- REVISED JULY 1999
switching characteristics over recommended operating virtual-Junction temperature range,
Vee = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VSENSE to HIGHDR or
LOWDR (excluding deadtime)
Propagation delay
MIN
1.3 V S VVREF S 2.6 V, 10 mV overdrive
(see Note 3)
OCP comparator
See Note 3
230
300
ns
lIS
1
SLOWST comparator
Overdrive = 10 mV (see Note 3)
HIGH DR output
CL=6nF,
VSOOTLO = 0 V,
VBOOT = 4.5 V,
TJ = 125°C
LOWDR output
CL= 6 nF,
TJ = 125°C
VDRV=4.5V,
Rise and fall time
OCP
700
1000
High-side VDS sensing
ns
80
2
5
1.8
5
VHISENSE = 4.5 V,
VIOUTLO pulsed from 4.5 V to 4.4 V,
100 ns riseJfall times (see Note 3)
3
VHISENSE = 3 V,
VIOUTLO pulsed from 3 V to 2.9 V,
100 ns riseJfall times (see Note 3)
3
SCP
LOSENSE = 0 V (see Note 3)
Turnon/tumoti delay
VDS sensing samplelhold
switch
Crossover delay time
PrafiHer pole frequency
ns
120
See Note 3
OVP
Short-circuit protection
rising-edge delay
lIS
lIS
300
500
ns
3 V S VHISENSE S 5.5 V,
VLOSENSE = VHISENSE (see Note 3)
30
100
ns
LOWDR to HIGHDRV, and
LOHIB to LOWDR
See Note 3
50
200
ns
Hysteretic comparator
See Note 3
Propagation delay
LODRV
See Note 3
NOTE 3: This parameter Is ensured by design and is not production tested.
="1ExAs
7-184
UNIT
1
PWRGD comparator
Response time
MAX
1
OVP comparator
Deglltch time (Includes
comparator propagation
delay)
TVP
INSTRUMENTS
POST OFFICE BOX 65S303 • OALLAS. TEXAS 75285
MHz
5
400
ns
,
TPSS6100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR S-V INPUT SYSTEMS
SLVS201A-JUNE 1999- REVISED JULY 1999
TYPICAL CHARACTERISTICS
SLOWSTART TIME
SLOWSTART TIME
vs
vs
SLOWSTART CAPACITANCE
SUPPLY CURRENT (VREFB)
100
1000
V(VREFB) = 2 V
~VREFBl: = 100 IIA
J = 27"
V(VREFB) = 2 V
Cs = 0.1 !If
TJ = 27"C
V
10
V
V
0.1
0.01
0.0001
0.0010
0.0100
1
0.1000
1
10
Figure 1
Figure 2
DRIVER
DRIVER
RISE TIME
FALL TIME
vs
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
1000
1000
TJ=27"C
TJ=27"C
~
~
..
V./ V
c 100
.
~
E
1=
-.
100
..
I
HlghSlde
V'
~I
v. ~
c
I
CD
1000
100
ICC - Supply Current (VREFB) -IIA
Siowstart Capacitance - I1F
.....
./
~
t--
High Side
1=
I
:I:'
10
100
~
L
./
!
Low Side
10
1
0.1
I---
E
~
Low Side
10
1
0.1
CL - Load Capacitance - nF
10
100
CL - Load Capacitance - nF
Figure 3
Figure 4
~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
7-185
TPSS6100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR S-V INPUT SYSTEMS
SLVS201A-JUNE 1999-REVISEDJULY 1999
TYPICAL CHARACTERISTICS
OCP THRESHOLD VOLTAGE
OVP THRESHOLD
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
105r---~-----r----_r----"T""--__,
118.0 ,-----,,....--"""T--...,...--"T""----,
117.5 t------ir--_+---+--+------i
117.0 t------ir--_+---+--+------i
"#. 116.5 t------ir--_+---+--+------i
I
1 116.0
I
t
~
I
115.5 t - - - - / - - - - t - - - - I - - - - - - i - - - I
F-a.
115.0 t------ir---_+---+--+------i
o
114.5 t------i'---_+---+--+------i
>
1~t--__t_---+---t---1--__1
=e
99~--____l-----+---~---~--~
97t------i---+---+--+------i
114.0 t------ir--_+---+--+------i
113.5
101~--____l----+--~---~--~
t------i~-_+---+--+------i
113~_~
o
__
~
__
~
__
~~--~---~----~----~--~
~_~
25
50
75
100
TJ - Junction Temperature - °C
o
125
Figure 5
25
50
75
100
TJ - Junction Temperature - °C
125
Figure 6
INHIBIT START THRESHOLD VOLTAGE
INHIBIT HYSTERESIS VOLTAGE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
110
2.10
109
>
...I
J
2.05
~
l.---'"
I
!
2.00
.J:.
l-
t:
aJ
I.5
1.95
=e
108
I
107
~
106
t
'1
I
105
i
103
~
102
,.,,-
",/
104
101
1.90
o
100
100
25
50
75
TJ - Junction Temperatura - °C
125
o
Figure 7
FigureS
~TEXAS
7-186
75
100
25
50
TJ - Junction Temperature - °C
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
125
TPSS6100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR S-V INPUT SYSTEMS
SLVS201A-JUNE 1999 - REVISED JULY 1999
TYPICAL CHARACTERISTICS
UVLO HYSTERESIS
UVLO START THRESHOLD VOLTAGE
4.020
,
4.018
:5!
4.012
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
470
VI=5~
> 4.016
I
----
II
~
..
4.014
0
J:
I!!
4.010
J:
I-
"C
6l
0
....
4.008
,L
4.006
/
----
J
~
~
468
>
467
E
..
I
466
0;
I!!
t
465
:z:
464
9
>
462
4.002
461
460
o
25
75
50
100
V
/'
463
::::I
~ 4.004
4.000
VI=5~
469
125
o
25
TJ - Junction Temperatura - °C
Figure 9
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
93.0
VI=5V
1.9
92.9
1.8
E
1.7
./
I
1.6
0
1.5
~::I
C
i
·S
a
125
POWERGOOD THRESHOLD
vs
2.0
C
100
Figure 10
QUIESCENT CURRENT
c(
75
50
TJ - Junction Temperature - °C
1.4
V
1.3
./
~
./
~
92.8
~
I
~
I
./
J:
92.7
I-
92.5
0
92.4
i
92.3
og
E!I
-
~
92.6
D.
1.2
92.2
1.1
92.1
1
o
92
25
50
75
100
125
o
T J - Junction Temperature - °C
25
50
75
100
125
TJ - Junction Temperature - °C
Figure 11
Figure 12
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-187
TPSS6100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR S-V INPUT SYSTEMS
SLVS201A-JUNE 1999-REVISEDJULY 1999
TYPICAL CHARACTERISTICS
DRIVER
SLOW START CHARGE CURRENT
VB
JUNCTION TEMPERATURE
HIGH-SIDE OUTPUT RESISTANCE
VB
JUNCTION TEMPERATURE
15~--~----~----~--~----~
=
=
V(VREFS) 1.3 V
R(VREFS) 20 kO
1
14~---+----~----+---~----~
I
i
a
f
i
~
~~~--~~~~i=::~::::~
I
131:;
4.0
c:I
3c
I
3.5
3.0
.-
2.5
'S
~
12~---+----4-----+----4----~
III
:s!
1.5
.S!'
::r:
1.0
II:
10~--~----~----~--~----~
25
50
75
100
TJ - Junction Temperatura - °C
~
I"'"
---
'"
I
0
o
-
V
0
~
11~---+----~----+---~----~
2.0
..",..
0.5
o
125
o
75
100
25
50
TJ - Junction Temperature - °C
Figure 13
125
Figure 14
DRIVER
LOW-SIDE OUTPUT RESISTANCE
VB
JUNCTION TEMPERATURE
SENSING SAMPLE/HOLD RESISTANCE
VB
JUNCTION TEMPERATURE
125
8
c:
I
B
c
6
i
5
7
,..",.....,..-
l1I
II:
'S
~
..",....",..
",...-
I
",......-
~
~
....I
I
V(HISENSE)
!.
=5 V
100
----
II:
~
",......-
4
I
3
dl
0
III
c:
I
B
c
E
75
i"""
50
aI
C
!
2
c7l
I
I
0
25
0
II:
II:
o
o
25
50
75
100
TJ - Junction Temperature - °C
125
o
o
Figure 15
Figure 16
~1ExAs
7-188
25
50
75
100
TJ - Junction Temperature - °C
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS. TEXAS 75265
125
TPSS6100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR S-V INPUT SYSTEMS
SLVS201A-JUNE 1999- REVISED JULY 1999
APPLICATION INFORMATION
The hysteretic-type controller method used in the TPS56100 controller gives very fast transient response for
today's high-speed DSP applications. Traditional PWM-type controllers use an oscillator to control the timing
of the control signals used to adjust the output voltage. During a transient load event, the PWM-type controller
must wait until the next oscillator cycle to begin the output voltage adjustment process. This delay causes output
droop (or overshoot) and longer recovery times. Hysteretic-type controllers, such as the TPS56100, are
self-oscillating and require no cycle-time to begin the recovery process. HysteretiC controllers have extremely
high gain and are sensitive to noise. The TPS561 00 has internal low-pass noise filters to eliminate much of this
problem, however an external RC low-pass filter between the output and VSENSE input is recommended.
The TPS56100 controller includes all of the functions necessary for a dependable high-efficiency power
converter. High-current synchronous MOSFET drivers are used for fast, low-loss switching allowing for
efficiencies greater than 90%. An internal bootstrap circuit provides the high-side drive voltage necessary for
the upper n-channel MOSFET. Overcurrent protection protects the power supply in case of load faults.
Overvoltage protection protects the load in case of high-side switch failure. Programmable hysteresiS allows
users to tailor the output ripple and operating frequency to suit their needs. Siowstart provides a controlled
rampup time for the output voltage eliminating output overshoot. Inhibit is provided for sequencing of the
converter in multiple-voltage circuits. Power good provides an indication that the output voltage is within
operating limits. The design of each of these functions is discussed in detail in the following. Refer to Figure 19
for location of components discussed in the following.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-189
TPSS6100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR S-V INPUT SYSTEMS
SLVS2D1A-JUNE 1999- REVISED JULY 1999
APPLICATION INFORMATION
frequency calculation
A detailed derivation of frequency calculation is shown in the application report, Designing Fast Response
Synchronous Buck Regulators USing the TPS5210, TI Literature number SLVA044. When less accurate results
are acceptable, the simplified equation shown below can be used:
(Vo x [VI - Vol x ESR)
fs == -;-''---------:........,(V I x L x Hysteresis WindOW)
control section
Below are the equations needed to select the various components within the control section. Component
reference numbers refer to the example application given at the end of this section. Details and the derivations
of the equations used in this section are available in the application report Designing Fast Response
Synchronous Buck Regulators Using the TPS5210, TI Literature number SLVA044.
output voltage selection
Of course the most important function of the power supply is to regulate the output voltage to a specific value.
Values between 1.3 V and 2.6 V can be easily set by shorting the correct VP inputs to ground. Values above
the maximum reference voltage (2.6 V) can be set by changing the reference voltage to any convenient voltage
within its range and selecting values for R2 and R3 to give the correct output. Select R3:
R3 « than VREPIBIAS(VSENSE); a recommended value is 10 kO
Then, calculate R2 using:
V
o
=
V
(1
REF
+ R2)
or R2
R3
=
R3 x
(vO
- V REF)
V
REF
R2 and R3 can also be used to make small adjusts to the output voltage within the reference-voltage range.
If there is no need to adjust the output voltage, R3 can be eliminated. R2, R3 (if used), and C7 are used as a
noise filter; calculate using:
C7
=
150 ns
(R2 II R3)
Recommended values for 3.3 V: VREF
=1.65 V, R3 =1.00 kO, R2 =1.00 kO, and C7 =100 pF.
slowstart timing
Siowstart reduces the start-up stresses on the power-stage components and reduces the input current surge.
Siowstart timing is a function of the reference-voltage current (determined by R5) and is independent of the
reference voltage. The first step in setting slowstart timing will be to determine R5:
R5 should be between 7 kO and 300 kCl, a recommended value is 20 kn.
7-190
:lllExAs
INSTRUMENTS
POST OFFICE BOX 655300 • DALLAS. TEXAS 75265
TPSS6100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR s-v INPUT SYSTEMS
SLVS201A-JUNE 1999- REVISED JULY 1999
APPLICATION INFORMATION
slowstart timing (continued)
Set the slowstart timing using the formula:
CS
tss
_
(s x RVREFB)
tss
= (S x
RS)
Where
CS = Siowstart capacitance in IlF
tss = Siowstart timing in I1S
RVREFB = Resistance from VREFB to GND in ohms (= RS)
hysteresis voltage
A hysteretic controller regulates by self-oscillation, thus requiring a small ripple voltage on the output which the
input comparator uses for sensing. Once selected, the TPSS6100 hysteresis is proportional to the reference
voltage; programming Vref to a new value automatically adjusts the hysteresis to be the same percentage of
Vref. The actual output ripple voltage is the combination of the hysteresis voltage, overshoot caused by internal
delays, and the output capacitor characteristics. Figure 19 shows the hysteresis window voltage (VHI to VLO)
and the output voltage ripple (VMAX to VMIN). Since the output current from VREFB should be less than
SOO !lA, the total divider resistance (R4 + RS) should be greater than 7 kn. The hysteresis voltage should be
no greater than 60 mV so RS will dominate the divider.
VREFB
Hysteresis Window
=2 x VR4
R4
VHSYT
R5
"*"
Figure 17. Hysteresis Divider Circuit
Vo
VMAX
VHI
vREF
VLO
VMIN
Figure 18. Output Ripple
~lExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 76265
7-191
TPS56100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR 5-V INPUT SYSTEMS
SLVS201A - JUNE 1999 - REVISED JULY 1999
APPLICATION INFORMATION
hysteresis voltage (continued)
The upper divider resistor, R4, is calculated using:
R4
Hysteresis Window
2 x (VREFB - Hysteresis Window) x
RS ::: V HYST(%)
RS
- (2 x 100) x
Where
Hysteresis Window the desired peak-to-peak hysteresis voltage.
VREFB selected reference voltage.
VHYST (%) [(Hysteresis Window)NREFBj* 100 < VO(Ripple)(P-P) (%)
=
=
=
current limit
Current limit can be implemented using the on-resistance of the upper FETs as the sensing element. Select R7:
V
R7
l102
Q101
r--
~
~1
~
C10~ r:C1~ "C1ta
:::::
--
~
~
Q102
~
........
r--
R101
GND
-'- Vo
R102
+
ClIrs " C10~
;:: r: C104
"
~
~-b
- -
-- - -
Power Stage
- -
-- --- - -- - -- - --- Control Section
~
~ 111111
c zW zW
WW
5V
:J:
"
:f
- - -
-- - -- - --
0
- - - - -
- - -C
g
C2;: ~t3
1liF
~
S!l~ 0ID
c
:J:
R1
10
C3\1
1 uF/1
1
15
16
17
16
19
C61l
0.033 uF 1\
20
DRV
BOOT
HIGH DR
lOWDR
DRVGND
BOOTlO
lOHIB
HISENSE
lODRV
BIAS
lOSENSE
IOUTlO
SlOWST
'122
,;;..;:.23
INHIBIT
ANAGND
VP4
VSENSE
- - 24
- - 2s
VP3
VREFB
VP2
VHYST
- - 2&
VP1
OCP
- - 27
VPO
NC
21
Note
28
NOTE A. VPO- VP4 are user sleeted
to set output voltage.
C1 IS deleted.
VCC
PWRGD
lOUT
- - -
ID II:
c
~~
14
13
~
11
~
9
8
7
6
-- - - -
--
W
III
Z
Z
Ii:
W
~
C4
1 uF
II
1\
C5 II
0.1 uFI\
C7 II
1\
1000 pF
R~A 10.0 ~
R4
.1.00
VVy
I
4
3
RTN
R2 ,.
150 ,.
5
2
- -- - - - -
'-
R6
3.92k
1
1
RSY
20.0k
R7
1.00 k
U1
TPS56100
Figure 19. Typical Application Schematic
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-193
TPS56100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR 5-V INPUT SYSTEMS
SLVS201A-JUNE 1999- REVISED JULY 1999
APPLICATION INFORMATION
application example (continued)
Table 2. Power Stage Components
Ref Des
Function
4-AOut
8-AOul
12-AOut
2O-AOut
Cl01
Input Bulk
Capacitor
Sanyo,
10TPB220M,
22Q;!F, 100V, 20%
Sanyo,
10SA220M,
2 x 22O;lF, 100V, 20%
Sanyo,
10SP470M,
2x470-11F,IO-V,20%
Sanyo,
IOSP470M,
3x47Q;!F,IO-V,2O%
Cl02
Input Mid-Freq
Capacitor
muRata,
GRM42-6YSV105Z02SA,
1.Q;!F, 25-V,
+80%-20%, YSV
muRata,
GRM42-6YSV22SZ016A,
2.2;tF, 16--V,
+80%-20%, Y5V
muRata,
GRM42-6YSV225Z016A,
2.2;tF, 16--V, +80%-20%,
YSV
muRata,
GRM42-6YSV105Z02SA,
3 x 1.Q;!F, 25-V,
+80%-20%, YSV
Cl03
Input Hi-Freq
Bypass
Capacitor
muRata,
GRM39X7Rl04KOI6A,
O.I;tF, 16--V, X7R
muRata,
GRM39X7Rl04KOI6A,
O.I;tF, 16--V, X7R
muRata,
GRM39X7Rl04KOI6A,
2 x O.I-I1F, 16--V, X7R
muRata,
GRM39X7Rl04K016A,
3 x 0.1 ;tF, 16--V, X7R
Cl04
Snubber
CapacHor
muRata,
GRM39X7Rl02K050A,
1000-pF, SO-V, X7R
muRata,
GRM39X7Rl02K050A,
l000-pF, SO-V, X7R
muRata,
GRM39X7Rl02KOSOA,
2 x 1000 pF, 50-V, X7R
muRata,
GRM39X7Rl02KOSOA,
3 x 1000-pF, SO-V, X7R
Cl0S
Output Bulk
CapacHor
Sanyo,
4TPC150,
2 x ISQ;!F, 4-V, 20%
Sanyo,
4SP820M,
82Q;!F, 4-V, 20%
Sanyo,
4SP820M,
2 x 82Q;!F, 4-V, 20%
Sanyo,
4SP820M,
3 x 82Q;!F, 4-V, 20%
Cl06
Output Hi-Freq
Bypass Capaci·
tor
muRata,
GRM39X7Rl04KOI6A,
O.I;tF, 16--V, X7R
muRata,
GRM39X7Rl04KOI6A,
O.I;tF, 16--V, X7R
muRata,
GRM39X7Rl04KOI6A,
2 x O.I;tF, 16--V, X7R
muRata,
GRM39X7Rl04KOI6A,
3 x O.I;tF, 16--V, X7R
Ll0l
Input FiRer
Inductor
CoilCraft,
DOI608C-332,
3.3;tH, 2.O-A
Coiltronlcs,
UP2B-2R2,
2.2;tH, 7.2-A
CoiHronics,
UP2B-2R2,
2.2;tH,7.2-A
ColHronlcs,
UP3B-1RO,
I;tH,12.5-A
L102
Output Filter
Inductor
CoilCraft,
D03316P-332,
3.3;tH,6.1-A
CoiHronics,
UP3B-2R2,
2.2;tH, 9.2-A
CoiHronics,
UP4B-1RS,
1.5;tH,13.4-A
MicroMetals,
T68-8/90 Core w/7T #16,
1.Q;!H,25-A
Rl0l
Lo--Side Gate
Resistor
3.3-0, 1I16--W, S%
3.3--O,1/16--W, S%
2 x 3.3--0, 1I16--W, S%
3 x 3.3--0, 1I16--W, S%
Rl02
Snubber
Resistor
2.7-Q, I1100W, S%
2.7-Q, 1I10-W, S%
2x2.7-Q, 1I10-W,S%
3 x 2.7-Q, I1100W, S%
0101
Power Switch
IR,IRF7811,
NMOS,II-mO
IR,IRF7811,
NMOS,l1-mO
IR, 2 x IRF7811, NMOS,
ll-rnO
IR, 2 x IRF7811, NMOS,
l1-rna
0102
Synchronous
SwHch
IR,IRF7811,
NMOS,l1-rnO
IR,IRF7811,
NMOS,l1-mO
IR, 2 x IRF7811, NMOS,
ll-rnO
IR, 3 x IRF7811, NMOS,
l1-mO
Nominal Frequency'
280kHz
250kHz
170 kHz
170 kHz
Hysteresis Window
15mV
ISmV
ISmV
ISmV
Nominal Irequency measured wilh Vo sello I.S V.
The values listed above are recommendations based on actual test circuits. Many variations of the above are
possible based upon the desires and/or requirements of the user. Performance of the circuit is equally, If not
more, dependent upon the layout than on the specific components, as long as the device parameters are not
exceeded. Fast-response, low-noise circuits require critical attention to the layout details. Even though the
operating frequencies of typical power supplies are relatively low compared to today's microprocessor circuits,
the power levels and edge rates can cause severe problems both in the supply and the load. The power stage,
having the highest current levels and greatest dv/dt rates, should be given the greatest attention.
~1ExAs
7-194
INSTRUMENTS
POST OFFICE SOX 665303 • DALlAS, TEXAS 75265
TPSS6100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR S-V INPUT SYSTEMS
SLVS201A-JUNE 1999- REVISED JULY 1999
APPLICATION INFORMATION
layout guidelines
Good power supply results will only occur when care is given to proper design and layout. layout will affect noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult
than most general PCB designs. The general design should proceed from the switching node to the output, then
back to the driver section and, finally, place the low-level components. Below are several specific points to
consider before layout of a TPS56100 design begins.
1.
All sensitive analog components should be referenced to ANAGND. These include components connected
to SlOWST, lOUT, OCP, VSENSE, VREFB, VHYST, BIAS, and lOHIB.
2.
Analog ground and drive ground should be isolated as much as possible. Ideally, analog ground will connect
to the ground side of the bulk storage capacitors on Vo, and drive ground will connect to the main ground
plane close to the source of the low-side FET.
3.
Connections from the drivers to the gate of the power FETs should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
4.
The bypass capacitor for the DRV input should be placed close to the TPS56100 and be connected to
DRVGND.
5.
The bypass capacitor for Vee should be placed close to the TPS56100 and be connected to AGND.
6.
When configuring the high-side driver as a floating driver, the connection from BOOTlO to the power FETs
should be as short and as wide as possible. The other pins that also connect to the power FETs, lOHIB
and lOSENSE, should have a separate connection to the FETS since BOOTlO will have large peak
currents flowing through it.
7.
When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from BOOT
to BOOTlO) should be placed close to the TPS561 00.
B.
When configuring the high-side driver as a ground-referenced driver, BOOTlO should be connected to
DRVGND.
9.
The bulk storage capacitors across VI should be placed close to the power FETS. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
10. High-frequency bypass capacitors should be placed across the bulk storage capacitors on VO.
11. HISENSE and lOSENSE should be connected very close to the drain and source, respectively, of the
high-side FET. HISENSE and lOSENSE should be routed very close to each other to minimize
differential-mode noise coupling to these traces. Ceramic decoupling capacitors should be placed close to
where HISENSE connects to Vin, to reduce high-frequency noise coupling on HISENSE.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-195
7-196
General Information (Vol. 1)
I:=L=i=n=ea=r=v=o=lt=a=g=e=R=e=g=u=la=t=o=rs==========1EI
Shunt Regulators
•
I
~~~~~~~~~.
I Precision Virtual Grounds
•
Mechanical Data
General Information (Vol. 2)
•
~~~~~~~~.
Processor PS Controllers
.
Switching PS and DC/DC Converters
..
~M==O=S=F=ET==D=ri=v=er=s================1II
Supervisors
Mechanical Data
General Information (Vol. 3)
Power Distribution Switches
LED Drivers
Voltage Rail Splitters
Special Functions
Mechanical Data
8-1
II
en
...n:e_.
_.
:::T
:::J
cc
"tJ
en
m
:::J
Q.
o
Q
o
o
o
o
<
CD
:::J
~
CD
~
til
8-2
TPS60100
REGULATED 3.3 V 200-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
I
features
•
•
•
•
•
•
•
•
•
•
•
applications
Up to 200-mA Output Current
Less Than 5-mYpp Output Yoltage Ripple
No Inductors Required/Low EMI
Regulated 3.3-Y ±4% Output
Only Four External Components Required
Up to 90% Efficiency
1.S-Y to 3.S-Y Input Yoltage Range
50-j.LA Quiescent Supply Current
0.05-j.LA Shutdown Current
Load Isolated in Shutdown
Space-Saving Thermally-Enhanced TSSOP
PowerPADTM Package
Replaces DC/DC Converters With Inductors in
- Battery-Powered Applications
- Two Battery Cells to 3.3-V Conversion
- Portable Instruments
- Battery-Powered Microprocessor and
DSPSystems
- Miniature Equipment
- Backup-Battery Boost Converters
- PDAs
- Laptops
- Handheld Instrumentation
- Medical Instruments
- Cordless Phones
• Evaluation Module Available
(TPSS0100EYM-131)
output voltage ripple
description
3.45
The TPS60100 step-up, regulated charge pump
generates a 3.3-V ±4% output voltage from a
1.8-Vto 3.6-V input voltage (two alkaline, NiCd, or
NiMH batteries). Output current is 200 mA from a
2-V input. Only four external capacitors are
needed to build a complete low-noise dc/dc
converter. The push-pull operating mode of two
single-ended charge pumps .assures the low
output voltage ripple as current is continuously
transferred to the output. From a 2-V input, the
TPS601 00 can start into full load with loads as low
as 16 O.
The TPS601 00 features either constant frequency mode to minimize noise and output voltage
ripple or the power-saving pulse-skip mode to
extend battery life at light loads. The TPS60100
switching frequency is 300 kHz. The logic
shutdown function reduces the supply current to
1-1JA (max) and disconnects the load from the
input. Special current-control circuitry prevents
excessive current from being drawn from the
battery during start-up. This dc/dc converter
requires no inductors and has low EMI. It is
available in the small20-pin TSSOP PowerPADTM
package (PWP).
,........-~....,...,..,..,.,.~.,.........,..........,...,.....,~-r-~.....,
3.4 .
. :. ..: .. SKIP =COM = 3V8 = 0 V
VIN = 2.4 V
lo=200mA
:
CO=22~F
. ...
X5R Ceramic
3.2
I
.JJ
3.15
3.1
3.05 0
1
2
3
4
5
6
7
8
9 10
t-Tlme-~
typical operating circuit
INPUT
1.8 V to
3.6 V
CIN
+
10~FT
S
OFF/ON
OUTPUT
3.3 V
200mA
SKIP COM 3V8
IN
OUT I---e---...-IN
OUT
TPS60100 FB
C1+
C2+
C1-
C2-
ENABLE
SYNC
PGND GND
Figure 1
PowerPAD is a trademark of Texas Instruments Incorporated.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
TPS60100
REGULATED 3.3 V 20o-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS213B - MAY 1999 - REVISED SEPTEMBER 1999
PWPPACKAGE
(TOP VIEW)
10
GND
SYNC
ENABLE
FB
OUT
C1+
IN
C1PGND
PGND
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
3V8
COM
SKIP
OUT
C2+
IN
C2PGND
PGND
Figure 2. Bottom View of PWP Package.
Showing the Thermal Pad
AVAILABLE OPTIONS
PACKAGE
TSSOpt
(PwP)
TPS60100PWP
available taped and reeled. To order this packaging
option, add an R suffix to the part number (e.g., TPS60100PWPR).
t This package
IS
Terminal Functions
TERMINAL
NAME
3V8
NO.
19
I/O
DESCRIPTION
I
Mode selection.
When 3V8 is logic low the charge pump operates in the regulated 3.3-V mode. When 3V8 Is connected to IN the
regulator operates In preregulated 3.8-V mode.
C1+
6
C1-
8
Positive terminal of the charge-pump capacitor C1 F
Negative terminal of the charge-pump capacHor C1 F
C2+
15
Positive terminal of the charge-pump capacitor C2F
C2-
13
COM
18
I
Mode selection.
When COM is logic low the charge pump operates in push·pull mode to minimize output ripple. When COM is
connected to IN the regulator operates in single-ended mode requiring only one flying capacitor.
ENABLE
3
I
ENABLE Input. The device turns off, the output disconnects from the input, and the supply current decreases to
0.05 jJA when ENABLE Is a logic low. Connect ENABLE to IN for normal operation.
FB
4
I
FEEDBACK input. Connect FB to OUT as close to the load as possible to achieve best regulation. Resistive divider
is on chip to match internal reference voltage of 1.22 V.
Negative terminal of the charge'pump capacHor C2F
GND
1,20
IN
7,14
I
Supply Input. Connect to an input supply In the 1.8-V to 3.6-V range. Bypass IN to GND with a (C0J2) IlF capacitor.
Connect both INs through a short trace.
OUT
5,16
a
Regulated power output. Connect both OUTs through a short trace and bypass OUT to GND with the output filter
capacitor CO. Va = 3.3 V when 3V8 = low and Va = 3.8 V when 3V8 = high.
PGND
9-12
GROUND. Analog ground for intemal reference and control circuitry. Connect to PGND through a short trace.
PGND power ground. Charge-pump current flows through this pin. Connect all PGNDs together.
SKIP
17
I
Mode selection. When SKIP is logic low, the charge pump operates in constant-frequency mode. Output ripple
and noise are minimized in this mode. When SKIP is connect to IN, the device operates in pulse skip mode.
Quiescent current is lowest in this mode.
SYNC
2
I
Selection for extemal clock signal. Connect to GND to use the internally generated clock signal. Connect to IN
for extemal synchronization. In this case, the clock signal needs to be fed through 3V8 and the device operates
in the regulated 3.3-V mode.
~1ExAs
INSTRUMENTS
POST OFFICE eox 655303 • DALLAS. TEXAS 75265
TPS60100
REGULATED 3.3 V 200-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS213B - MAY 1999 - REVISED SEPTEMBER 1999
absolute maximum ratings (unless otherwise noted)t*
Input voltage range, VI (IN, OUT, ENABLE, SKIP, COM, 3V8, FB, SYNC) ............... -0.3 V to 5.5 V
Differential input voltage, VIO (C1 +, C2+ to GND) ........................... -0.3 V to (VOUT + 0.3 V)
Differential input voltage, VIO (C1-, C2- to GND) ............................. -0.3 V to (VIN + 0.3 V)
Continuous total power dissipation .................................... See Dissipation Rating Tables
Continuous output current ................................................................ 300 mA
Storage temperature range, Tstg .................................................. -55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10s ....................................... 260°C
Maximum junction temperature, T J ......................................................... 150°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
:j: VENABLE, VSKIP. VCOM, VaV8andVSYNccanexceedVINuptothemaximumratedvoitagewithoutincreasingtheleakagecurrentdrawnbythese
mode select inputs.
DISSIPATION RATING TABLE 1 - FREE-AIR TEMPERATURE (see Figure 3)
PACKAGE
TA:;; 25°C
POWER RATING
DERATING FACTOR
ABOVE TA 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PWP
700mW
5.6mW/"C
448mW
364mW
=
DISSIPATION RATING TABLE 2 - CASE TEMPERATURE (see Figure 4)
=
TC :;; 62.5°C
POWER RATING
DERATING FACTOR
ABOVE TC = 62.5°C
TC 70°C
POWER RATING
TC 85°C
POWER RATING
PWP
25W
285.7mW/OC
22.9W
18.5W
DISSIPATION DERATING CURVES
MAXIMUM CONTINUOUS DISSIPATION§
vs
VB
FREE-AIR TEMPERATURE
CASE TEMPERATURE
1400
30
J:
E
I 1200
c
0
J
J:
I
c
.2
:::I
0
:::I
Ir!I
800
C
'!0
~
600
0
E
:::I
E
0
:::I
400
~~
200
Q
a..
o
25
i
PWPPackage
.......... ~=178OCIW
·M
:II
25
'\
i
1000
10
=
PACKAGE
50
75
100
20
" \ . . PWP Package
15
~
0
0
E
:::I
E
..........
i::E
"-...
125
I
10
pa~
Measured with the exposed thermal
coupled to an Infinite heat sink with a
thermally conductive compound (the
thermal conductivity of the compound
Is 0.815 W/m . "C). The Re.tc Is 3.5°C/W.
5
Q
a..
150
o
25
TA - Free-Air Temperature - °c
Figure 3
50
~
100
125
75
TC - Case Temperature - °c
"\..
150
Figure 4
§ DISSipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 150°C.
It is recommended not to exceed a junction temperature of 125°C.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALlAS. TEXAS 75265
8-5
TPS60100
REGULATED 3.3 V 200-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS213B - MAY 1999 - REVISED SEPTEMBER 1999
electrical characteristics at CIN = 10 IlF, C1F = C2F = 2.2 11Ft, Co = 221lF, TC = -40°C to 85°C,
VIN=2V, VFB= YO, VENABLE VIN, VSKIP= VINorOVand VCOM = V3VS= VSYNC=OV (unless otherwise
noted)
=
PARAMETER
TEST CONDITIONS
VIN
Input voltage
VIN(UV)
Input undervoltage lockout threshold
10(MAX)
Maximum output current
MIN
MAX
3.6
1.a
1.a
1.a V c
5:
w
40
I
>c
'u
I
60
CD
50
w
40
..
~
30
30
20
20
10
0.1
10
100
VV
~ Vv
1000
1
70
'"
~
'#
I
60
~
c
50
~w
1000
EFFICIENCY
vs
OUTPUT CURRENT (VO = 3.8 V)
II
V
VN=:3V
i.-"
VI-'"
'"
40
40v
30
30
20
20~4-+++H~~-+4+~~~++~~
10
10~4-+++H~~-+4+~~4-++~~
o
0.1
10
100
1000
__~~~
100
1000
OL-~~LUW-~~LW~
1
10 - Output Current - rnA
10
10 - Output Current - rnA
Figure 7
Figure 8
tTc = 25°C, VCOM = VSYNC = 0 V, CIN = 10 IlF, C1 F = C2F = 2.2 IlF, Co = 22 IlF, unless otherwise noted
8-8
100
N'=' .
VI~ 12.
I-'"
V
10
10 - Output Current - rnA
Figure 6
V(SKIP) = VIN
80
=2.1 V
~
OL-~~LUW-~~LW~~~~~
EFFICIENCY
vs
OUTPUT CURRENT (VO = 3.8 V)
I- V(3V8) = VIN
.U ~!~V
~V
Figure 5
90
~
Ifl
I"""
1'\
V
10 - Output Current - rnA
100
V ~~I~
10~4-++~~~-+4+~~~~~~
V(SKIP) = VIN, V(3V8) = 0 V
ill'
",-
o
~I~ ~1~.8 v I
V
70
IN=2.
60
..
V(SKIP) = 0 v
V(3V8) = 0 V
-!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS60100
REGULATED 3.3 V 200-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS213B - MAY 1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICSt
QUIESCENT SUPPLY CURRENT
QUIESCENT SUPPLY CURRENT
vs
INPUT VOLTAGE
vs
INPUT VOLTAGE
60
2
V(SKIP) = VIN
V(3V8)=OV
C
:!.
55
I
I
J
j
a
---
50
1"-
45
(
./
~
)
I
1i
1.75
~
i
~
-... r---
1.5
40
J
35
I
I
9
V(SKIP)=OV
V(3V8)=OV
1.5
2
2.5
3
3.5
1
4
1.5
VIN -Input Voltage - V
3.5
vs
OUTPUT CURRENT
IIIIII
4.1
S
3.3
I
III
I
VIN-2V
0
I
~
VIN=3.6V
>
~
;-
V(SKIP) = VIN or 0 V
V(3V8) = VIN
I
4
>
3A
I --I 11111
3.2
4
3.5
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
V(SKlP)=VINorOV
V(3V8)=OV
I
3
2.5
Figure 10
OUTPUT VOLTAGE
3.6
2
VIN -Input Voltage - V
Figure 9
f
I-
1.25
9
30
25
I
~'" ~
rr
3.9
1,(
VIN=2.7V
VIN=2.4V
~
I.
SDo
3.8
~
I
~
3.1
3.7
3.6
3
1
10
100
1000
3.5
1
10 - Output Current - mA
10
100
1000
10 - Output Current - mA
Figure 11
Figure 12
tTc = 25°C, VCOM = VSYNC = OV, CIN = 10 IJ-F, C1F= C2F = 2.21J-F, CO=22IJ-F, unless otherwise noted
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-9
TPS60100
REGULATED 3.3 V 200-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS213B - MAY 1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICSt
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
3.5
3.10
V(SKIP) = VIN or 0 V
3.45 t- V(3V8) = 0 V
10=1 mAto200mA
3.4
>
>
I
I
3.35
t
~
3.3
~
3.25
:;
0
III
J~
J
J
:;
t
0
I
3.2
I
~
I
~
3.15
3.8
3.5
II
IO=11omA
1'----1
lo=100mA
I
lo=200mA
3.3
3.1
2.5
3
3.5
VIN -Input Voltage - V
'j
,III
3.4
3.05
2
,
3.6
3.2
3
1-/-1
3.7
3.1
1.5
V(SKIP) = VIN or 0 V
V(3V8)= VIN
3.9
J
I
3
4
2
1.5
Figure 13
Figure 14
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
TIME
3.36
I
>
t
3.34
I:;
3.33
I
3.32
~
I
TIME
I
~onsta~t
V(SKIP)=OV
V(3V8)=OV
VIN=2.4V
IO=100mA
Co = 22 IlF (X5R ceramic)
3.35
I
I_
Frequency
t-- Mode
>
3.38 r--r---,r--"'T""--r--r--,--r--r-,--.
V(SKIP) = VIN
V(3V8)=OV
VIN=2.4V
10 = 200 mA
3.36
I
III
1/\
n
/I
I
~
./\
:;
\
0
~
4
2.5
3
3.5
VIN - Input Voltage - V
!
Less than
5mVpp -
I
~
3.31
3.30
o
234
5
t-Tlme-1lS
6
7
8
3.3 L...--I...--I_...l.........L_.i..--I...---"'--....L..--L---I
o
2
Figure 15
6
8 10 12
t- Tlme-1lS
Figure 16
tTc = 25°C. VCOM = VSYNC = 0 V. CIN = 10 IlF. C1F
=C2F =2.2IlF. Co =221lF. unless otherwise noted
~TEXAS
8-10
4
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
14
16
18
20
TPS60100
REGULATED 3.3 V 200-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS213B - MAY 1999- REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICSt
LOAD TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
>
3.36
V(SKIP)=OV
V(3V8)=OV
V(IN) = 2.7 V
10= 10 mAto 200 mA
I
t
~
"S
~
I
~
3.35
3.34
3.33
- r--
~
r
3.33
I
o
2
4
8
6
10
12
14
I
l
16
I
18
20
.9
.1t4
WfI
3.31
400
200
o
o
I
2
I
V(SKIP)=OV
"S
3.35
o
3.33
t
I
~
,
~
>
I
I
\
i
I
~
~
i
~
'[
.5
16
l
18
20
3.45
=
Pulse-Skip Mode
V(SKIP) VIN
3.4 ~ V(3V8~OV
10=1 mA
3.35
.....
'\. ~
\
I--
3.3
~
3.25
>
I
3
,
2.5
2
I
!-
I
3.31
>
I
14
LINE TRANSIENT RESPONSE
I
Constant
Frequency Mode
10=10mA
~
12
t-nme-ms
LINE TRANSIENT RESPONSE
t
10
Figure 18
3.39
3.37 I- V(3V8~ = 0 V
8
6
4
Figure 17
I
"""
600
t-Tlme-ms
>
PUIS~.Ski~ Mode
"1'"
1
200
.9
I
I
400
o
"S
~
1
3.32
I
V(SKlP) = VIN
3.37 _ V(3V8)=OV
V(IN)=2.7V
10 = 10 mA to 200 mA
3.35
~
600
io
i
~
. L.-
r"
3.39
I
Constant
Frequency Mode
I
>
1.5
o
2
3
4
t
~
,
5
6
7
8
9
3
,
2.5
"S
10
l-I
2
!-
1.5
o
t-nme-ms
2
3
4
5
6
t-nme-ms
7
8
9
10
Figure 20
Figure 19
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
8-11
TPS60100
REGULATED 3.3 V 200-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS213B - MAY 1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICSt
FREQUENCY SPECTRUM
CONSTANT FREQUENCY MODEt
FREQUENCY SPECTRUM
PULSE-SKIP MODEt
100r-----~------~----~------,
90
V(SKIP)=OV
V(3V8)=OV
VIN=2.4V
10 = 100 mA
RBW = 300 Hz
80
70
>::!.
III
"g
I
'S
f
0
V(SKIP) = VIN
V(3V8)=OV
VIN = 2.4 V
10 = 100 mA
RBW=300Hz
80 IJII-----+---+_
-
60
>::!.
III
50
"g
I
i
40
30
~~
20
l.j.
J.
10
O~----~------~----~----~
0
0
5
2.5
7.5
o
10
2.5
f - Frequency - MHz
5
Figure 21
Figure 22
FREQUENCY SPECTRUM
CONSTANT FREQUENCY MODEt
90
>::!.
"g
90
I
70
III
FREQUENCY SPECTRUM
PULSE-SKIP MODEt
V(SKIP)=OV
V(3V8)=OV
VIN = 2.4 V
10= 10mA
RBW = 300 Hz
80
-
80
-
70
60
>::!.
III
50
"g
f
'S
a.
'S
40
0
30
V(SKIP) = VIN
V(3V8) = 0 V
VIN=2.4V
10=10mA
RBW=300 Hz
I
-
60
50
It
I
I
I I
.1 L .1.1 LJ IJ
L.a
0
I
Jl
40
20
10
10
o
2.5
5
7.5
10
,,~
30
20
o
o
f~
o
f - Frequency - MHz
....
~
5
2.5
Figure 24
tTc = 25°C, VCOM = VSYNC = 0 V, CIN = 10 I1F, C1 F = C2F = 2.2I1F, Co = 2211F, unless otherwise noted
:j:Test circuit: TPS60100EVM-131
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
, ...
.~
f - Frequency - MHz
Figure 23
8-12
-
I
I
'S
10
7.5
f - Frequency - MHz
7.5
10
TPS60100
REGULATED 3.3 V 200-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS213B - MAY 1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICSt
EFFICIENCY
vs
INPUT VOLTAGE
EFFICIENCY
vs
INPUT VOLTAGE
100
100
90
"
80
70
'#.
I
60
c
50
r;
III
V(3V8)=OV
lo=100mA -
'"
Skip = Low ~
40
~ ~kIP=HI9h
70
...... ~iP=Hi9h
'#.
I
60
c
50
~
40
r;
' --- t'
.!!!
30
30
20
20
10
10
SkiP=LO~ ~
~
o
o
1.5
2
2.5
3
VIN -Input Voltage - V
3.5
1.5
4
2
2.5
3
VIN -Input Voltage - V
Figure 25
!
~
'S
g
RO= 16.5n
VIN=2.4V
V(3V8)=OV
I
I.
2
3.5
/
I
2.5
>
I
I
Enable
RO= 19n
VIN =2.4 V
V(3V8)= VIN
/
2.5
~
2
'S
g,
'S
1.5
7
I
7
Enable
0
.,,-V
0.5
/'
0
-0.5
-100
0
I
~
I--""
100
0.5
/'"
0
200
300
t-Time;tS
400
500
600
-0.5
-100
"'""--
7
3
III
CI
!
/loUTPUT _
1.5
I
J'
4
4
I
III
CI
3.5
START·UP TIMING
START·UP TIMING
>
t::::
Figure 26
3.5
3
V(3V8)= VIN
lo=100mA
"-
80
'6
ffi
"-
90
0
Figure 27
V
.... . /
100
.I
OUTPUT
I
200
300
t-Time ;tS
400
500
600
Figure 28
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-13
TPS60100
REGULATED 3.3 V 200-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS213B - MAY 1999 - REVISED SEPTEMBER 1999
detailed description
operating principle
The TPS60100 charge pump provides a regulated 3.3-V output from a 1.8-V to 3.6-V input. It delivers a
maximum load current of 200 mAo Designed specifically for space critical battery powered applications, the
complete charge pump circuit requires only four external capacitors. The circuit can be optimized for highest
efficiency at light loads or lowest output noise. The TPS60100 consists of an oscillator, a 1.22-V bandgap
reference, an internal resistive feedback circuit, an error amplifier, high current MOSFET switches, a
shutdown/start-up circuit, and a control circuit (Figure 29)
CHARGE PUMP 1
r
00
T11~
OSCILLATOR
T12
IN
~
1800
Cl+
I
ClT13
-'
SKIP
T14L
-'
;-<
./
OUT
./
COM
3V8
L
SYNC
I
ENABLE t-
PGND
CONTROL
CIRCUIT
SHUTDOWN!
START-UP
CONTROL
FB
<
~~
r1u,v~
-=-
..
-----
-'
-'
CHARGE PUMP 2
T21
~
T22
IN
~
C2+
T23
C2T24L
;-<
~
C2F
OUT
PGND
GND
Figure 29. Functional Block Diagram TPS60100
The oscillator runs at a 50% duty cycle. The device consists of two single-ended charge pumps which operate
with 1800 phase shift. Each single ended charge pump transfers charge into its transfer capacitor (CxF) in one
half of the period. During the other half of the period (transfer phase), CxF is placed in series with the input to
transfer its charge to Co. While one single-ended charge pump is in the charge phase, the other one is in the
transfer phase. This operation guarantees an almost constant output current which ensures a low output ripple.
If the clock were to run continuously, this process would eventually generate an output voltage equal to two times
the input voltage (hence the name doubler). In order to provide a regulated fixed output voltage of 3.3 V, the
TPS601 00 uses either pulse-skip mode or constant-frequency mode. Pulse-skip mode and constant-frequency
mode are externally selected via the SKIP input pin.
~TEXAS
8-14
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TPS60100
REGULATED 3.3 V 200-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS213B - MAY 1999 - REVISED SEPTEMBER 1999
detailed description (continued)
start-up procedure
During start-up, i.e. when ENABLE is set from logic low to logic high, the switches T12 and T14 (charge pump
1), and the switches T22 and T24 (charge pump 2) are conducting to charge up the output capacitor until the
output voltage Vo reaches O.8xVIN. When the start-up comparator detects this limit, the IC begins to operate
in the mode selected with SKIP, COM and 3V8. This start-up charging of the output capacitor guarantees a short
start-up time and eliminates the need for a Schottky diode between IN and OUT.
pulse-skip mode
In pulse-skip mode (SKIP =high), the error amplifier disables switching of the power stages when it detects an
output higher than 3.3 V. The oscillator halts. The IC then skips switching cycles until the output voltage drops
below 3.3 V. Then the error amplifier reactivates the oscillator and switching of the power stages starts again.
The pulse-skip regulation mode minimizes operating current because it does not switch continuously and
deactivates all functions except bandgap reference and error amplifier when the output is higher than 3.3 V.
When switching is disabled from the error amplifier, the load is also isolated from the input. SKIP is a logic input
and should not remain floating. The typical operating circuit of the TPS60100 in pulse skip mode is shown in
Figure 1.
constant-frequency mode
When SKIP is low, the charge pump runs continuously at the frequency fOSC. The control circuit, fed from the
error amplifier, controls the charge on C1F and C2F by driving the gates of the FETs T12fT13 and T22fT23,
respectively. When the output voltage falls, the gate drive increases, resulting in a larger voltage across C1 F
and C2F- This regulation scheme minimizes output ripple. Since the device switches continuously, the output
noise contains well-defined frequency components, and the circuit requires smaller external capacitors for a
given output ripple. However, constant-frequency mode, due to higher operating current, is less efficient at light
loads than pulse-skip mode.
INPUT
1.&Vto3.6V -
SKIP COM 3V&
.....- - -.....---i IN
IN
CIN
+
10 11FT
...J
OUTI-.....- - -.....OUT
+
TPS60100 FB
C1+
C2+
C1-
C2-
T
OUTPUT
3.3 v 200 mA
CO=22I1F
C2F
2.211F
ENABLE SYNC
POND GND
OFF/ON
Figure 30. TYpical Operating Circuit TPS60100 in Constant Frequency Mode
Table 1. Tradeoffs Between Operating Modes
FEATURE
PULSE-SKIP MODE
(SKIP = HIgh)
Best light-load efficiency
CONSTANT-FREQUENCY MODE
(SKIP = Low)
X
Smallest extemal component size for a given ol>1put ripple
X
Output ripple amplitude
Small amplitude
Very small amplitude
Output ripple frequency
Variable
Constant
Load regulation
Very good
Good
NOTE: Even In pulse-skip mode the output npple amplitude IS small If the push-pull operating mode IS selected via COM.
~TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS. TEXAS 75285
8-15
TPS60100
REGULATED 3.3 V 200-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS213B - MAY 1999 - REVISED SEPTEMBER 1999
detailed description (continued)
push-pull operating mode
In push-pull operating mode (COM = low), the two single-ended charge pumps operate with 1800 phase shift.
The oscillator signal has a 50% duty cycle. Each single-ended charge pump transfers charge into its transfer
capacitor (CxF) in one-half of the period. During the other half of the period (transfer phase), CxF is placed in
series with the input to transfer its charge to Co. While one single-ended charge pump is in the charge phase,
the other one is in the transfer phase. This operation guarantees an almost constant output current which
ensures a low output ripple. COM is a logic input and should not remain floating. The typical operating circuit
of the TPS601 00 in push-pull mode is shown in Figure 1 and Figure 30.
single-ended operating mode
When COM is high, the device runs in single-ended operating mode. The two single-ended charge pumps
operate in parallel without phase shift. They transfer charge into the tran!lfer capacitor (CF) in one half of the
period. During the other half of the period (transfer phase), CF is placed in series with the input to transfer its
charge to CO, In single-ended operating mode only one transfer capacitor (CF = C1 F + C2F) is required, resulting
in less board space.
INPUT
1.& Vto 3.6 v -
SKIP COM 3V&
...- - -..........f--I IN
IN
OUTPUT
OUTI--+-----4...-- 3.3 V 200 rnA
OUT
TPS60100 FB
C2+ 1-----,
, - - - - - - 1 C1+
, - - - - - 1 C1-
S
OFF/ON
C2-
ENABLE SYNC
PGND GND
CF=4.7IlF
Figure 31. Typical Operating Circuit TPS60100 in Single-Ended Operating Mode
Table 2. Tradeoffs Between Operating Modes
FEATURE
Output ripple amplitude
PUSH-PULL MODE
(COM = Low)
SINGLE-ENDED MODE
(COM High)
Small amplitude
Large amplitude
Smallest board space
=
X
regulated 3.3 V operating mode
In regulated 3.3 V operating mode (3V8 =low) the device provides a regulated 3.3-V output from a1.8-V to 3.6-V
input. 3V8 is a logic input and should not remain floating. The typical operating circuit of the TPS601 00 in (3.3
V) regulated mode is shown in Figure 1 and Figure 30.
pre-regulated 3.8 V operating mode
When 3V8 is high, the device provides a preregulated 3.8-V output from a 2.2-V to 3.6-V input. This mode should
be used if a tighter output voltage tolerance is a major concern. In this case the charge pump generates the input
voltage for a low-dropout regulator.
~TEXAS
8-16
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS60100
REGULATED 3.3 V 200-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS213B-MAY 1999- REVISED SEPTEMBER 1999
detailed description (continued)
shutdown
Driving ENABLE low places the device in shutdown mode. This disables all switches, the oscillator, and control
logic. The device typically draws 0.05-1JA (1-1JA max) of supply current in this mode. Leakage current drawn from
the output is as low as 1 IJA max. The device exits shutdown once ENABLE is set high level. The typical no-load
shutdown exit time is 10 Jls. When the device is in shutdown, the load is isolated from the input and the output
is high impedance.
external clock signal
If the device shall operate at a user defined frequency, an external clock signal can be used. Therefore, SYNC
needs to be connected to IN and the external oscillator signal can drive 3V8. The maximum external frequency
is limited to 800 kHz. The switching frequency of the converter is half of the external oscillator frequency. It is
recommended to operate the charge pump in constant-frequency mode if an external clock signal is used so
that the output noise contains only well-defined frequency components.
External Clock
-=-
SKIP COM 3V8
IN
IN
CIN
+
10llFT
-=-
C1F
2.21lF
OUT
OUT
TPS60100 FB
C1+
C1-
S
C2+
C2SYNC
OFF/ON
-=Figure 32. Typical Operating Circuit TPS60100 With External Synchronization
undervoltage lockout
The TPS601 00 has an undervoltage lockout feature that deactivates the device and places it in shutdown mode
when the input voltage falls below 1.6 V.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
8-17
TPS60100
REGULATED 3.3 V 200-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS213B - MAY 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
capacitor selection
The TPS601 00 requires only four external capacitors as shown in the basic application circuit. Their values are
closely linked to the output current capacity, output noise requirements, and mode of operation. Generally, the
transfer capacitors (CxF) will be the smallest.
The input capacitor improves system efficiency by reducing the input impedance and stabilizes the input current.
CIN is recommended to be about two to four times as large as CxF
The output capacitor (CO) can be selected from 5-times to 50-times larger than CxFo depending on the mode
of operation and ripple tolerancet. Tables 3 and 4 show capacitor values recommended for low
quiescent-current operation (pulse-skip mode) and for low output voltage ripple operation (constant-frequency
mode). A recommendation is given for smallest size.
Table 3. Recommended Capacitor Values for Low Quiescent-Current Operationt
(pulse-skip mode)
Co
CIN
VIN
[V]
[j.LF]
10 [mA]
TANTALUM
t
2.4
150
2.4
150
2.4
200
2.4
200
[jLF]
CERAMIC
10
TANTALUM
2.2
10 (X5R)
10 (X5R)
CERAMIC
OUTPUT
VOLTAGE
RIPPLEVpp
[mV]
90
22
22 (X5R)
2.2
2.2
10
..
[jLF]
CxF
22
45
55
22 (X5R)
2.2
30
All measurements are done with additional 1·I1F X7R ceramic capacitors at Input and output.
Table 4. Recommended Capacitor Values for Low Output Voltage Ripple Operationt
(constant-frequency mode)
Co
CIN
VIN
[V]
10
[rnA]
2.4
150
2.4
150
2.4
200
2.4
200
[jLF]
TANTALUM
t
t
[jLF]
CxF
blF]
CERAMIC
10
TANTALUM
2.2
10 (X5R)
10
10 (X5R)
22
2.2
C9 ~ 22 rF
~ThXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4
15
22 (X5R)
All measurements are done with addltlonal1·I1F X7R ceramic capacitors at mput and output.
In constant·frequency mode always select
8-18
13
22 (X5R)
2.2
2.2
CERAMIC
22
OUTPUT
VOLTAGE
RIPPLE Vpp
[mV]
5
TPS60100
REGULATED 3.3 V 200-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS213B - MAY 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
For the TPS60100, the smallest board space size can be achieved using Sprague's 595D-series tantalum
capacitors for input and output. However, with the trend towards high capacitance ceramic capacitors in smaller
size packages, these type of capacitors might become competitive in size soon.
Table 5. Recommended Capacitors
MANUFACTURER
PART NUMBER
CAPACITANCE
TYPE
TaiyoYuden
LMK212BJ105KG-T
LMK212BJ225MG-T
JMK316BJ106ML-T
LMK432BJ226MM-T
111F
2.211F
lOI1F
2211F
Ceramic
Ceramic
Ceramic
Ceramic
AVX
OB05ZC105KAT2A
1206ZC225KAT2A
TPSC106025R0500
TPSC226016R0375
111F
2.211F
lOI1F
2211F
Ceramic
Ceramic
Tantalum
Tantalum
Sprague
595D106XOO10A2T
595D226X06R3A2T
595D226X06R3B2T
595D226XOO20C2T
lOI1F
2211F
2211F
2211F
Tantalum
Tantalum
Tantalum
Tantalum
Kemet
T494C106M010AS
T494C226M010AS
lOI1F
2211F
Tantalum
Tantalum
Table 6 lists the manufacturers of recommended capacitors. In most applications surface-mount tantalum
capacitors will be the right choice. However, ceramic capacitors will provide the lowest output voltage ripple due
to their typically lower ESR.
Table 6. Recommended Capacitor Manufacturers
MANUFACTURER
CAPACITOR TYPE
INTERNET
Taiyo Yuden
X7R1X5R ceramic
www.t-yuden.com
AVX
X7R1X5R ceramic
TP5-series tantalum
www.avxcorp.com
Sprague
595D-series tantalum
593D-series tantalum
www.vishay.com
Kemet
T494-series tantalum
www.kemet.com
power dissipation
The power dissipated in the TPS60100 depends on output current and is approximated by:
P DISS
= 10 x
(2 V IN
-
V o ) for 10 < < 10
PDISS must be less than that allowed by the package rating. See the ratings for 20-PowerPADTM package
power-dissipation limits and deratings.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
8-19
TPS60100
REGULATED 3.3 V 200-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS213B - MAY 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
layout
All capacitors should be soldered in close proximity to the IC. A PCB layout proposal for a two-layer board is
given in Figure 33. Care has been taken to connect both single-ended charge pumps symmetrically to the load
to achive optimized output voltage ripple performance. The proposed layout also provides improved thermal
performance as the exposed leadframe is soldered to the PCB. The bottom layer of the PCB is a ground plain
only. All ground areas on the PCB should be connected. Connect ground areas on top layer to the bottom layer
via through hole connections.
OUT
GND
_ 3ve
- COM
",.,...- ...... SKIP
C2+
C2-
GND
IN
Figure 33. Recommended PCB Layout for TPS60100 (top view)
An evaluation module forthe TPS601 00 is available and can be ordered under literature code SLVP131 or under
product code TPS60100EVM-131.
~1ExAs
INSTRUMENTS
8-20
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
TPS60100
REGULATED 3.3 V 200-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS213B - MAY 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
applications proposals
paralleling of two TPS60100 to deliver 400 mA
The TPS601 00 can be paralleled to yield higher load currents. The circuit of Figure 34 can deliver 400 mA at
an output voltage of 3.3 V. It uses two TPS60100 devices in parallel. The devices can share the output
capacitors, but each one requires its own transfer capacitors and input capacitor. For best performance, the
paralleled devices should operate in the same mode (pulse-skip or constant frequency).
INPUT
1.8Vta
3.6V 10~F
OUTPUT
+
T
S
OFF/ON
I---'-~'--+_ 3.3 V
200mA
ENABLE
SYNC
PGND GND
ENABLE SYNC
PGND GND
Figure 34. Paralleling of Two TPS60100
TPS60100 with LC output filter for ultra low ripple
For applications where extremely low output ripple is required, a small LC filter is recommended. This is shown
in Figure 35. The addition of a small inductor and filter capacitor will reduce the output ripple well below what
could be achieved with capacitors alone. The corner frequency of 500 kHz was chosen above the 300 kHz
switching frequency to avoid loop stability issues in case the feedback is taken from the output of the LC filter.
Leaving the feedback (FB) connection point before the LC filter, the filter capacitance value can be increased
to achieve even higher ripple attenuation without affecting stability margin.
OUTPUT
~,--"/yYY',--.....
+_---<.- 3.3 V 200 mA
T+ CO=22JLF I
INPUT
1.8 Vta 3.6 v
--
1~F
--
C1+
C1-
S
OFF/ON
ENABLE
SYNC
PGND GND
Figure 35. TPS60100 With LC Filter for Ultra Low Output Ripple Applications
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-21
TPS60100
REGULATED 3.3 V 200-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS213B - MAY 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
related Information
application reports
For more application information see:
•
PowerPAD'M Application Report (Literature Number: SLMA002)
•
TPS6010x/TPS6011x Charge Pump Application Report (Literature Number: SLVA070)
device family products
Other devices in this family are:
PART NUMBER
LITERATURE
NUMBER
TPS60101
SLVS214
Regulated 3.3-V, 100-mA Low-Noise Charge Pump DC/DC Converter
TPS60110
SLVS215
Regulated 5-V, 300-mA Low-Noise Charge Pump DC/DC Converter
TPS60111
SLVS216
Regulated 5-V, 150-mA Low-Noise Charge Pump DC/DC Converter
DESCRIPTION
~1EXAS
8-22
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS60101
REGULATED 3.3-V 100-mA LOW-NOISE
CHARGE PUMP DCfDC CONVERTER
features
applications
• Up to 100-mA Output Current
• Less Than 5-mVpp Output Voltage Ripple
Replaces DC/DC Converters With Inductors In
- Battery-Powered Applications
- Two Battery Cells to 3.3-V Conversion
- Portable Instruments
- Battery-Powered Microprocessor and
DSPSystems
- Miniature Equipment
- Backup-Battery Boost Converters
- PDAs
- Laptops
- Handheld Instrumentation
- Medical Instruments
- Cordless Phones
• No Inductors Required/Low EMI
• Regulated 3.3-V ±4% Output
• Only Four External Components Required
• Up to 90% Efficiency
• 1.S-V to 3.6-V Input Voltage Range
• 50-I1A Quiescent Supply Current
• 0.05-!1A Shutdown Current
• Load Isolated in Shutdown
• Space-Saving Thermally-Enhanced TSSOP
PowerPADTM Package
• Evaluation Module Available
(TPS601 00EVM-131)
output voltage ripple
description
The TPS60101 step-up, regulated charge pump
generates a 3.3-V ±4% output voltage from a
1.8-V to 3.6-V input voltage (two alkaline, NiCd, or
NiMH batteries). Output current is 100 rnA from a
2-V input. Only four external capacitors are
needed to build a complete low-noise dc/dc
converter. The push-pull operating mode of two
single-ended charge pumps assures the low
output voltage ripple as current is continuously
transferred to the output. From a 2-V input, the
TPS60101 can start into full load with loads as low
as 33 n.
The TPS601 01 features either constant frequency mode to minimize noise and output voltage
ripple or the power-saving pulse-skip mode to
extend battery life at light loads. The TPS60101
switching· frequency is 300 kHz. The logic
shutdown function reduces the supply current to
1-1lA (max) and disconnects the load from the
input. Special current-control circuitry prevents
excessive current from being drawn from the
battery during start-up. This DC/DC converter
requires no inductors and has low EMI. It is
available in the small 20-pin TSSOP PowerPADTM
package (PWP).
>
3.35
I
i
3.3
~
!i
3.25
!
0
3.2
I
3.15
.Jl
3.1
3.05 0
1
2
SKIP =COM = 3ve = 0 v
VIN = 2.4 V
VO=3.3V
lo=100mA
CO=22I1F
X5RCeramic
3 4 5 B 7 e 9 10
I-Time -118
typical operating circuit
INPUT
1.8Vlo
3.BV
CIN
4.7 I1F
+
T
C1F
111F
--'
OFF/ON
SKIP COM 3ve
IN
OUT
IN
OUT
TPS60101 FB
C1+
C2+
C1-
OUTPUT
3.3 V
100mA
C2-
ENABLE SYNC
PGND GND
-=
Figure 1
PowerPAD is a trademark of Texas Instruments Incorporated.
~TEXAS
Copyright © 1999. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-23
TPS60101
REGULATED 3.3-V 100-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS214A - JUNE 1999 - REVISED SEPTEMBER 1999
PWPPACKAGE
(TOP VIEW)
GND
SYNC
ENABLE
FB
OUT
C1+
IN
C1PGND
PGND
20
19
GND
1S
COM
SKIP
OUT
C2+
IN
C2PGND
PGND
17
16
15
14
13
12
11
3V8
Thermal
Pad
Figure 2. Bottom View of PWP Package,
Showing the Thermal Pad
AVAILABLE OPTIONS
PACKAGE
TSSOpt
(PWP)
TPS60101PWP
t
This package is available taped and reeled. To order this packaging
option, add an R suffix to the part number (e.g., TPS601 01 PWPR).
Terminal Functions
TERMINAL
NAME
3VS
NO.
19
110
DESCRIPTION
I
Mode selection.
When 3VS is logic low the charge pump operates in the regulated 3.3-V mode. When 3VS is connected to IN the
regulator operates in preregulated 3.S-V mode.
C1+
6
Positive terminal of the charge-pump capacitor C1 F
C1-
S
Negative terminal of the charge-pump capacitor C1 F
Positive terminal of the charge-pump capacitor C2F
C2+
15
C2-
13
COM
1S
I
Mode selection.
When COM is logic low the charge pump operates in push-pull mode to minimize output ripple. When COM is
connected to IN the regulator operates in single-ended mode requiring only one flying capacitor.
ENABLE
3
I
ENABLE Input. The device turns off, the output disconnects from the input, and the supply current decreases to
0.051!A when ENABLE is a logic low. Connect ENABLE to IN for normal operation.
FB
4
I
FEEDBACK input. Connect FB to OUT as close to the load as possible to achieve best regulation. Resistive divider
is on chip to match internal reference voltage of 1.22 V.
Negative terminal of the charge-pump capacitor C2F
GROUND. Analog ground for internal reference and control circuitry. Connect to PGND through a short trace.
GND
1,20
IN
7,14
I
Supply Input. Connect to an input supply in the 1.S-V to 3.6-V range. Bypass IN to GND with a (CoI2) ILF capacitor.
Connect both INs through a short trace.
OUT
5,16
0
Regulated power output. Connect both OUTs through a short trace and bypass OUT to GND with the output filter
capacitor CO. Vo = 3.3 V when 3VS = low and Vo = 3.S V when 3VS = high.
PGND
9-12
PGND power ground. Charge-pump current flows through this pin. Connect all PGNDs together.
SKIP
17
I
Mode selection. When SKIP is logic low, the charge pump operates in constant-frequency mode. Output ripple
and noise are minimized in this mode. When SKIP is connect to IN, the device operates in pulse skip mode.
Quiescent current is lowest in this mode.
SYNC
2
I
Selection for external clock signal. Connect to GND to use the internally generated clock signal. Connect to IN
for external synchronization. In this case, the clock signal needs to be fed through 3VS and the device operates
in the regulated 3.3-V mode.
~TEXAS
INSTRUMENTS
8-24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS60101
REGULATED 3.3-V 100-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS214A - JUNE 1999 - REVISED SEPTEMBER 1999
absolute maximum ratings (unless otherwise noted)t*
Input voltage range, VI (IN, OUT, ENABLE, SKIP, COM, 3V8, FB, SYNC) ............... -0.3 V to 5.5 V
Differential input voltage, VIO (C1 +, C2+ to GND) ........................... -0.3 V to (VOUT + 0.3 V)
Differential input voltage, VIO (C1-, C2- to GND) ............................. -0.3 V to (VIN + 0.3 V)
Continuous total power dissipation .................................... See Dissipation Rating Tables
Continuous output current ............................................... " ................ 150 mA
Storage temperature range, Tstg .................................................. -55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10s ....................................... 260°C
Maximum junction temperature, TJ ......................................................... 150°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
=1= VENABLE. VSKIP, VCOM. V3V8andVSYNccanexceedVIN uptothemaximumratedvoltagewithoutincreasingtheleakagecurrentdrawnbythese
mode select inputs.
DISSIPATION RATING TABLE 1 - FREE-AIR TEMPERATURE (see Figure 3)
PACKAGE
TA S 25°C
POWER RATING
PWP
700mW
DERATING FACTOR
ABOVE TA 25°C
=
=
=
TA 70°C
POWER RATING
TA 85°C
POWER RATING
448mW
364mW
DISSIPATION RATING TABLE 2 - CASE TEMPERATURE (see Figure 4)
=
TC S 62.5°C
POWER RATING
DERATING FACTOR
ABOVE TC 62.5°C
TC 70°C
POWER RATING
TC 85°C
POWER RATING
PWP
25W
285.7mW/oC
22.9W
18.5W
=
DISSIPATION DERATING CURVEt
MAXIMUM CONTINUOUS DISSIPATION§
vs
vs
FREE-AIR TEMPERATURE
CASE TEMPERATURE
1400
==E
I
c
30
1200
==cI
0
Iis
III
::I
ia.
1000
'il
is..
800
~
0
0
::I
c
.........
800
400
~ r-.....
'j(
iI
:e
PWPPackage
........... ~=178OCIW
u
E
::I
E
25
'\
20
~ PWP Package
::I
0
::I
C
200
Q
II.
o
=
PACKAGE
25
50
75
100
15
"
0
u
E
::I
E
10
:IE
5
..
pa~
Measured with the exposed thermal
coupled to an infinita heat sink with a
thermally conductive compound (the
thermal conductivity 01 the compound
Is 0.815 W/m· DC). The RSJC Is 3.5°CIW.
'j(
...........
~
125
I
Q
II.
150
o
25
TA - Free-Air Temperature - °C
Figure 3
50
'-
100
75
125
TC - Case Temperature - °C
~
150
Figure 4
§ Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 150°C.
It is recommended not to exceed a junction temperature of 125°C.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-25
TPS60101
REGULATED 3.3N 100-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS214A-JUNE 1999- REVISED SEPTEMBER 1999
electrical characteristics at CIN = 10 ~F, C1 F = C2F = 2.2 ~Ft, Co = 22 ~F, TC = -40°C to 85°C,
VIN=2V. VFB= Vo. VENABLE =VIN, VSKIP= VINorOVandVCOM= V3VS= VSYNc=OV{unlessotherwise
noted)
PARAMETER
TEST CONDITIONS
VIN
Input voltage
VIN(UV)
Input undervoltage lockout threshold
101MAX)
Maximum output current
TYP
1.B
MAX
3.6
1.6
1.a
100
0< 10<50mA,
TC=25°C
3.17
3.3
3.43
2 V
I
3.5
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.6
I
3
Figure 10
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
V(SKIP) = VIN or 0 V
V(3V8)=OV
2.5
2
VIN - Input Voltage - V
Figure 9
I
J
g
~
'!5
I
-?
>
I
3.35
J~
3.3
3.S
CD
3.7
~
'!a.5
3.6
I
I
3.25
I
3.4
-$'
3.3
3.1
3.2
3.05
3.1
2.5
3
VIN -Input Voltage - V
10 = 100 mA
3
4
3.5
IJ
,I
3.2
2
I,
10=10mA
3.5
3.15
3
t i'-
1
1'--1
'/
8
1.5
V(SKIP) = VIN or 0 V
V(3VS) = VIN
3.9
1.5
2
2.5
3
VIN -Input Voltage - V
Figure 13
I
>
I
I
Frequency
t-- Mode
Pulse-8k1p Mode
-
3.34
I
~
'a.
!5 3.33
I--
IA
...
/I,
./\
~
i
'!5
0
J>
OUTPUT VOLTAGE
vs
TIME
3.3S.----,----r--.,..---.----;;-----,
Jonsta~t
V(SKIP)=OV
V(3VS)=OV
VIN =2.4V
10=50mA
Co = 22 I1F (X5R ceremlc)
3.35
CD
I
I.
Less than
5 mVpp -
3.32
3.31
3.30
V(SKIP) = VIN
V(3VS)=OV
10= 100 mA
o
23456
t- T1me-11S
7
S
3.3L-_-'-_-'-_ _~-"""::---=:--~
-5
Figure 15
tTc =25°C, VCOM
10
15
t- T1me-11S
Figure 16
=VSYNC =0 V, CIN =10 I1F, C1F =C2F =2.2I1F, Co =2211F, unless otherwise noted
~1ExAs
8-30
4
Figure 14
OUTPUT VOLTAGE
vs
TIME
3.36
3.5
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
20
25
TPS60101
REGULATED 3.3-V 100-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS214A - JUNE 1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICSt
LOAD TRANSIENT RESPONSE
>
I
t
g
!j
"S
I
~
LOAD TRANSIENT RESPONSE
>
3.36
V(SKIP)=OV
V(3V8)=OV
3.35 f- V(IN) = 2.7 V
10 = 10 mAt0200 mA
3.34
3.33
-
r--
.........
r"
1
.~'
t
g
-
3.32
~
300
i
3.35
I
3.33
~
c
o
.9
I
!j
I
o
I
2
4
6
8
10
12
14
:::
I
l
16
18
20
2
4
~
I
Con~tantl
I
t
!j
i
.5
V(SKIP) = VIN
V(3V8t=OV
10=1 OmA
.,
\
! -
~
I
16
l
18
20
pUI~e-Sklp M~de
...
....
.~
......
3.3
~
I
2.5
,
,
2
0
2
3
4
t
,
5
6
7
8
9
!j
2.5
i
.5
2
I
Z
10
3
>"
1.5
,
y
o
t-Time-ms
2
3
4
5
6
7
8
9
10
t-Time-ms
Figure 19
tTc
14
3.25
3
1.5
I
\
>
I
i!!:
>
3.4 3.35
>
t
3.45
!j
3.31
I
12
LINE TRANSIENT RESPONSE
>
Frequency Mode
,
~
10
Figure 18
V(SKIP)=OV
3.37 f- V(3V8t = 0 V
10=10mA
3.35
8
6
t-Time-ms
3.39
3.33
,.
300
LINE TRANSIENT RESPONSE
I
,~
,J...
3.31
Figure 17
t
"S
g
~
.I
E
t-Tlme-ms
>
.i.
I ..
WIt
I
Pulse-Skip Mode
V(SKlP) = VIN
V(3V8)=OV
V(IN)=2.7V
10= 10 mA to 200 mA
200
100
I
3.37 -
!j
"S
200
o
~
I
Constant
Frequency Mode
I
3.39
Figure 20
=25°C, VCOM =VSYNC =0 V, CIN =10 I1F, C1F =C2F =2.2I1F, Co =2211F, unless othelWise noted
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALlAS. TEXAS 75265
HI
TPS60101
REGULATED 3.3-V 100-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS214A - JUNE 1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICSt
FREQUENCY SPECTRUM
CONSTANT FREQUENCY MODE*
FREQUENCY SPECTRUM
PULSE-SKIP MODE*
90
100
V(SKIP)=OV
V(3V8)=OV
VIN =2.4V
10=100mA
RBW=300 Hz
80
70
>
60
"a
50
::I.
III
-
0
80
>
::I.
III
60
"a
I
5a.
'5
V(SKIP) = VIN
V(3V8)=OV
VIN=2.4V
10 = 100mA
RBW=300 Hz
-
I
'5
40
~
0
30
~~
20
40
J.
20
10
0
0
0
2.5
5
10
7.5
2.5
0
f - Frequency - MHz
Figure 21
I
V(SKIP)=OV
V(3V8)=OV
VIN = 2.4 V
10=10mA
80
70
>
60
"a
50
::I.
III
I
'5
~
FREQUENCY SPECTRUM
PULSE-SKIP MODE*
90
-
80
-
70
60
"a
50
'5
~
I
I I 1I I
" I .1.1 LJ 1J JL.
l'-
20
0
30
,~
o
2.5
7.5
5
10
o
o
.......
~
5
2.5
f - Frequency - MHz
Figure 23
Figure 24
=25°C, VCOM =VSYNC =0 V, CIN =10 I1F, C1 F =C2F =2.211F, Co =2211F, unless otherwise noted
:!:Test circuit: TPS60100EVM-131 with TPS60101
~TEXAS
8-32
-
,
.
10
f - Frequency - MHz
tTc
-
..\1\
40
20
10
o
V(SKlP) = VIN
V(3V8)=OV
VIN = 2.4 V
10=10mA
I
40
30
>
::I.
III
0
10
Figure 22
FREQUENCY SPECTRUM
CONSTANT FREQUENCY MODE*
90
7.5
5
f - Frequency - MHz
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
7.5
10
TPS60101
REGULATED 3.3-V 100-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS214A - JUNE 1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICSt
EFFICIENCY
vs
INPUT VOLTAGE
EFFICIENCY
vs
INPUT VOLTAGE
100
100
90
"
80
70
'#.
I
60
~
c
50
I
V(3VS)=OV
10=100mA -
"-
80
'"
Skip = Low ~
~ ~klp=High
70
""'l1lI ~IP=Hlgh
'#.
'-
60
~
c
.91
50
IE
40
..
"
40
I
w
30
30
20
20
10
10
SklP=LO~ ~
~
o
o
1.5
2
2.5
3
VIN -Input Voltage - V
3.5
1.5
4
2
2.5
3
VIN -Input Voltage - V
4
RO=33n
VIN =2.4 V
V(3VS)=OV
2.5
I
2
Enable
~
~
'S
/
1.5
~
I
0.5
0
-0.5
-100
3.5
>
I
t
7
0
~
/
/
I
I
GI
CD
3.5
./
/
/
OUTPUT
3
/
2.5
~
2
i
1.5
J
Eneble
400
500
-0.5
-100
OUTPUT
/
I
./
/"
o
200
300
t - Time -J.1S
/
II
0.5
100
lr--
RO=3Sn
VIN = 2.4 V
V(3VS) =VIN
~
/'
o
4
START·UP TIMING
START·UP TIMING
3.5
>
P::
Figure 26
Figure 25
3
V(3VS~=VIN
10=10mA
~
90
o
Figure 27
100
200
300
t - Time -J.1S
400
500
Figure 28
tTc = 25°C, VCOM = VSYNC = 0 V, CIN = 10 I1F, Cl F = C2F = 2.2I1F, Co = 2211F, unless otherwise noted
-!11
TEXAS
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS, TEXAS 75265
8-33
TPS60101
REGULATED 3.3-V 100-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS214A - JUNE 1999 - REVISED SEPTEMBER 1999
detailed description
operating principle
The TPS60101 charge pump provides a regulated 3.3-V output from a 1.8-V to 3.6-V input. It delivers a
maximum load current of 100 rnA. Designed specifically for space critical battery powered applications, the
complete charge pump circuit requires only four external capacitors. The circuit can be optimized for highest
efficiency at light loads or lowest output noise. The TPS60101 consists of an oscillator, a 1.22-V bandgap
reference, an internal resistive feedback circuit, an error amplifier, high current MOSFET switches, a
shutdown/start-up circuit, and a control circuit (Figure 29)
CHARGE PUMP 1
r
0°
T11~
~
OSCILLATOR
IN
T12 \
180°
C1+
I
C1T13
./
SKIP
T14L
./
r--< OUT
/'
./
COM
3V8
FB
L
SYNC
I
ENABLE
PGND
CONTROL
CIRCUIT
0-
SHUTDOWNI
START-UP
CONTROL
~
r1
..
--.
.!::-
CHARGE PUMP 2
T21
~
IN
T22 \
C2+
T23
O,.V,.
-=-
./
/'
1T
C2T24L
r--< OUT
n=
PGND
GND
Figure 29. Functional Block Diagram TPS60101
The oscillator runs at a 50% duty cycle. The device consists of two single-ended charge pumps which operate
with 1800 phase shift. Each single ended charge pump transfers charge into its transfer capacitor (CxF) in one
half of the period. During the other half of the period (transfer phase), CxF is placed in series with the input to
transfer its charge to Co. While one single-ended charge pump is in the charge phase, the other one is in the
transfer phase. This operation guarantees an almost constant output current which ensures a low output ripple.
If the clock were to run continuously, this process would eventually generate an output voltage equal to two times
the input voltage (hence the name doubler). In order to provide a regulated fixed output voltage of 3.3 V, the
TPS60101 uses either pulse-skip mode or constant-frequency mode. Pulse-skip mode and constant-frequency
mode are externally selected via the SKIP input pin.
-!!1TEXAS
8-34
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS60101
REGULATED 3.3-V 100-rnA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS214A - JUNE 1999 - REVISED SEPTEMBER 1999
detailed description (continued)
start-up procedure
During start-up, i.e. when ENABLE is set from logic low to logic high, the switches T12 and T14 (charge pump
1), and the switches T22 and T24 (charge pump 2) are conducting to charge up the output capacitor until the
output voltage Vo reaches O.axVIN' When the start-up comparator detects this limit, the IC begins to operate
in the mode selected with SKIP, COM and 3va. This start-up charging of the output capacitor guarantees a short
start-up time and eliminates the need for a Schottky diode between IN and OUT.
pulse-skip mode
=
In pulse-skip mode (SKIP high), the error amplifier disables switching of the power stages when it detects an
output higher than 3.3 V. The oscillator halts. The IC then skips switching cycles until the output voltage drops
below 3.3 V. Then the error amplifier reactivates the oscillator and switching of the power stages starts again.
The pulse-skip regulation mode minimizes operating current because it does not switch continuously and
deactivates all functions except bandgap reference and error amplifier when the output is higher than 3.3 V.
When switching is disabled from the error amplifier, the load is also isolated from the input. SKIP is a logic input
and should not remain floating. The typical operating circuit of the TPS601 01 in pulse skip mode is shown in
Figure 1.
constant-frequency mode
When SKIP is low, the charge pump runs continuously at the frequency fosC' The control circuit, fed from the
error amplifier, controls the charge on C1F and C2F by driving the gates of the FETs T12fT13 and T22rr23,
respectively. When the output voltage falls, the gate drive increases, resulting in a larger voltage across C1 F
and C2F This regulation scheme minimizes output ripple. Since the device switches continuously, the output
noise contains well-defined frequency components, and the circuit requires smaller external capacitors for a
given output ripple. However, constant-frequency mode, due to higher operating current, is less efficient at light
loads than pulse-skip mode.
INPUT
1.8Vto3.6V
SKIP COM 3V8
--,----'--1
IN
IN
OUTI-......- - -......OUT
TPS60101 FB
C1+
C1-
S
ENABLE
OFF/ON
OUTPUT
3.3 V 100 mA
C2+
C2SYNC
PGND GND
Figure 30. Typical Operating Circuit TPS60101 in Constant Frequency Mode
Table 1. Tradeoffs Between Operating Modes
FEATURE
PULSE-SKIP MODE
(SKIP High)
=
CONSTANT-FREQUENCY MODE
(SKIP Low)
=
X
Best light-load efficiency
X
Smallest external component size for a given output ripple
Output ripple amplitude
Output ripple frequency
Load regulation
Small amplitude
Very small amplitude
Variable
Constant
Very good
Good
NOTE: Even In pulse-skip mode the output rtpple amplitude IS small I! the push-pull operating mode IS selected via COM.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
8-35
TPS60101
REGULATED 3.3-V 100-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS214A - JUNE 1999 - REVISED SEPTEMBER 1999
detailed description (continued)
push-pull operating mode
In push-pull operating mode (COM =low), the two single-ended charge pumps operate with 1800 phase shift.
The oscillator signal has a 50% duty cycle. Each single-ended charge pump transfers charge into its transfer
capacitor (CxF) in one-half of the period. During the other half of the period (transfer phase), CxF is placed in
series with the input to transfer its charge to CO, While one single-ended charge pump is in the charge phase,
the other one is in the transfer phase. This operation guarantees an almost constant output current which
ensures a low output ripple. COM is a logic input and should not remain floating. The typical operating circuit
of the TPSS0101 in push-pull mode is shown in Figure 1 and Figure 30.
single-ended operating mode
When COM is high, the device runs in single-ended operating mode. The two single-ended charge pumps
operate in parallel without phase shift. They transfer charge into the transfer capacitor (CF) in one half of the
period. During the other half of the period (transfer phase), CF is placed in series with the input to transfer its
charge to Co. In single-ended operating mode only one transfer capacitor (CF = C1 F + C2F) is required, resulting
in less board space.
INPUT
1.8 V to 3.6 V CIN
4.7 I1F
OUTPUT
OUTI-.....--~~- 3.3 v 100 mA
OUT
+
TPS60101 FB
CO= 10 I1F
C1+
C2+ 1------,
....- - -...........i---IIN
IN
+
.--------1
T
.------t
S
OFF/ON
T
C1-
C2-
ENABLE SYNC
PGND GND
Figure 31.-ryplcal Operating Circuit TPS60101 in Single-Ended Operating Mode
Table 2. Tradeoffs Between Operating Modes
FEATURE
Output ripple amplitude
PUSH-PULL MODE
(COM = Low)
SINGLE-ENDED MODE
(COM = High)
Small amplitude
Large amplitude
X
Smallest board space
regulated 3.3 V operating mode
In regulated 3.3-V operating mode (3V8 = low) the device provides a regulated 3.3-V output from a1.8-V to 3.S-V
input. 3V8 is a logic input and should not remain floating. The typical operating circuit of the TPSS0101 in (3.3
V) regulated mode is shown in Figure 1 and Figure 30.
pre-regulated 3.8 V operating mode
When 3V8 is high, the device provides a preregulated 3.8-V output from a 2.2-V to 3.S-V input. This mode should
be used if a tighter output voltage tolerance is a major concern. In this case the charge pump generates the input
voltage for a low-dropout regulator.
~1ExAs
INSTRUMENTS
POST OFACE BOX 655303 • DALLAS, TEXAS 75265
TPS60101
REGULATED 3.3-V 100-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS214A - JUNE 1999 - REVISED SEPTEMBER 1999
detailed description (continued)
shutdown
Driving ENABLE low places the device in shutdown mode. This disables all switches, the oscillator, and control
logic. The device typically draws 0.05-1JA (1-1JA max) of supply current in this mode. Leakage current drawn from
the output is as low as 1 IJA max. The device exits shutdown once ENABLE is set high level. The typical no-load
shutdown exit time is 10 1lS. When the device is in shutdown, the load is isolated from the input and the output
is high impedance.
external clock signal
If the device operates at a user defined frequency, an external clock signal can be used. Therefore, SYNC needs
to be connected to IN and the external oscillator signal can drive 3Va. The maximum external frequency is
limited to aoo kHz. The switching frequency of the converter is half of the external oscillator frequency. It is
recommended to operate the charge pump in constant-frequency mode if an external clock signal is used so
that the output noise contains only well-defined frequency components.
External Clock
SKIP COM 3V8
INPUT
1.8 V to 3.6 V ....> - - -.....---.--1 IN
IN
CIN
4.7 I1F
+
T
S
OUTPUT
3.3 V 100 mA
OUT
OUT
TPS60101 FB
C1+
C2+
C1-
C2-
ENABLE
+
T
CO=22I1F
.".
C2F
111F
SYNC
OFF/ON
-=Figure 32. lYpical Operating Circuit TPS60101 With External Synchronization
undervoltage lockout
The TPS601 01 has an undervoltage lockout feature that deactivates the device and places it in shutdown mode
when the input voltage falls below 1.6 V.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
8-37
TPS60101
REGULATED 3.3-V 100-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS214A - JUNE 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
capacitor selection
The TPS601 01 requires only four external capacitors as shown in the basic application circuit. Their values are
closely linked to the output current capacity, output noise requirements, and mode of operation. Generally, the
transfer capacitors (CxF) will be the smallest.
The input capacitor improves system efficiency by reducing the input impedance and stabilizes the input current.
CIN is recommended to be about two to four times as large as CxF.
The output capacitor (Co) can be selected from 5-times to 50-times larger than Cx !=> depending on the mode
of operation and ripple tolerancet. Tables 3 and 4 show capacitor values recommended for low
quiescent-current operation (pulse-skip mode) and for low output voltage ripple operation (constant-frequency
mode). A recommendation is given for smallest size.
Table 3. Recommended Capacitor Values for Low Quiescent-Current Operatlont
(pulse-skip mode)
VIN
[V]
10 [mA]
2.4
50
2.4
50
2.4
100
2.4
100
CIN
I!J.F]
TANTALUM
t
TANTALUM
CERAMIC
4.7
1
4.7 (X7R)
4.7
4.7 (XlR)
CERAMIC
OUTPUT
VOLTAGE
RIPPLEVpp
[mV]
135
10
10 (X5R)
1
1
..
Co
[ILF]
CxF
I!J.F]
10
125
70
10 (X5R)
1
65
All measurements are done WIth additIOnal 1-ILF X7R ceramic capacitors at Input and output.
Table 4. Recommended Capacitor Values for Low Output Voltage Ripple Operatlont
(constant-frequency mode)
VIN
[V]
10
[mAl
2.4
50
2.4
50
2.4
100
2.4
100
CIN
[ILF]
TANTALUM
t
t
CERAMIC
4.7
TANTALUM
1
4.7 (X7R)
4.7
4.7 (X7R)
CERAMIC
22
22 (X5R)
All measurements are done with addltlonall-ILF X7R ceramic capacitors at Input and outp'ut.
In constant-frequency mode always select
Cg > 22 MF
~TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS. TEXAS 75265
3
10
22
1
OUTPUT
VOLTAGE
RIPPLEVpp
[mV]
5
22 (X5R)
1
1
..
Co
I!J.F]
CxF
[ILF]
5
TPS60101
REGULATED 3.3-V 100-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS214A-JUNE 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
For the TPS601 01, the smallest board space size can be achieved using Sprague's 595D-series tantalum
capacitors for input and output. However, with the trend towards high capacitance ceramic capacitors in smaller
size packages, these type of capacitors might become competitive in size soon.
Table 5. Recommended Capacitors
MANUFACTURER
PART NUMBER
CAPACITANCE
TYPE
TalyoYuden
LMK212BJ105KG-T
LMK212BJ225MG-T
LMK316BJ475KL-T
JMK316BJ106ML-T
LMK432BJ226MM-T
111F
2.211F
4.711F
1Ol1F
2211F
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
AVX
OB05ZC105KAT2A
1206ZC225KAT2A
TPSC475035R0600
TPSC10B025R0500
TPSC226016R0375
111F
2.211F
4.711F
1Ol1F
22JLF
Ceramic
Ceramic
Tantalum
Tantalum
Tantalum
Sprague
595D475XOO16A2T
595D108XOO10A2T
595D226X06R3A2T
595D226X06R3B2T
595D226XOO2OC2T
4.7JLF
10JLF
22JLF
2211F
22JLF
Tantalum
Tantalum
Tantalum
Tantalum
Tantalum
Kemet
T494B475M010AS
T494C108M010AS
T494C226M010AS
4.7JLF
10JLF
22JLF
Tantalum
Tantalum
Tantalum
Table 6 lists the manufacturers of recommended capacitors. In most applications surface-mount tantalum
capacitors will be the right choice. However, ceramic capacitors will provide the lowest output voltage ripple due
to their typically lower ESR.
Table 6. Recommended Capacitor Manufacturers
MANUFACTURER
CAPACITOR TYPE
INTERNET
TaiyoYuden
X7R1X5R ceramic
www.t-yuden.com
AVX
X7R1X5R ceramic
TPS-series tantalum
www.avxcorp.com
Sprague
595D-series tantalum
593D-series tantalum
www.vishay.com
Kemet
T494-tieries tantalum
www.kemet.com
power dissipation
The power dissipated in the TPS601 01 depends on output current and is approximated by:
PDISS
= 10 x (2 V IN
-
V o ) for IQ < < 10
POISS must be less than that allowed by the package rating. See the ratings for 20-PowerPADTM package
power-dissipation limits and de ratings.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-39
TPS60101
REGULATED 3.3-V 100-mALOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS214A - JUNE 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
layout
All capacitors should be soldered in close proximity to the IC. A PCB layout proposal for a two-layer board is
given in Figure 33. Care has been taken to connect both single-ended charge pumps symmetrically to the load
to achive optimized output voltage ripple performance. The proposed layout also provides improved thermal
performance as the exposed leadframe is soldered to the PCB. The bottom layer of the PCB is a ground plain
only. All ground areas on the PCB should be connected. Connect ground areas on top layer to the bottom layer
via through hole connections.
OUT
GND
_ 3ve
- COM
" ' ' - , - , SKIP
C2+
C2-
GND
IN
Figure 33. Recommended PCB Layout for TPS60101 (top view)
The evaluation module designed for the TPS601 00 can, with slight modifications, be used for evaluation of the
TPS60101. The EVM can be ordered under literature code SLVP131 or under product code
TPS60100EVM-131.
="1ExAs
INSTRUMENTS
8-40
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TPS60101
REGULATED 3.3-V 100-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS214A- JUNE 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
applications proposals
TPS60101 with LC output filter for ultra low ripple
For applications where extremely low output ripple is required, a small LC filter is recommended. This is shown
in Figure 34. The addition of a small inductor and filter capacitor will reduce the output ripple well below what
could be achieved with capacitors alone. The corner frequency of 500 kHz was chosen above the 300 kHz
switching frequency to avoid loop stability issues in case the feedback is taken from the output of the LC filter.
Leaving the feedback (FB) connection point before the LC filter, the filter capacitance value can be increased
to achieve even higher ripple attenuation without affecting stability margin.
0.11lH
OUTPUT
rl~...fYYY''--......- _ , - - 3.3 V 100 mA
INPUT
1.8Vto3.6V - - - . - - - - - - - . - ; I N
S
ENABLE
OFF/ON
SYNC
PGND GND
Figure 34. TPS60101 With LC Filter for Ultra Low Output Ripple Applications
related Information
application reports
For more application information see:
•
PowerPA[}fM Application Report (Literature Number: SLMA002)
•
TPS6010xITPS6011x Charge Pump Application Report (Literature Number: SLVA070)
device family products
Other devices in this family are:
PART NUMBER
LITERATURE
NUMBER
TPS601 00
SLVS213
Regulated 3.3-V, 200-mA Low-Noise Charge Pump DC/DC Converter
TPS60ll0
SLVS21S
Regulated S-V, 300-mA Low-Noise Charge Pump DC/DC Converter
TPS60lll
SLVS216
Regulated S-V, lS0-mA Low-Noise Charge Pump DC/DC Converter
DESCRIPTION
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 752115
8-
I
5.1
I
5.05
i
4.95
~
0
I
~
5
SKIP =COM = ClK = 0 v
VIN=3.6V
.... ····lo=300mA
.: ... : ... Co = 22 j.lF + 10 j.lF
X5RCeramic
4.9
4.85
4.8 0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
t-Tlme-j.IS
typical operating circuit
INPUT
2.7 V to
5.4 V
CIN
+
15j.1FT
S
OFF/ON
SKIP COMClK
IN
OUT
IN
OUT
TPS60110 FB
C1+
C2+
C1-
C2-
OUTPUT
5V
300mA
1--..--......-
ENABLE SYNC
PGND GND
Figure 1
PowerPAD is a trademark of Texas Instruments InCOrporated.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Copyrlght© 1999. Texas Instruments Incorporated
TPS60110
REGULATED S-V 300-mA LOW-NOISE
CHARGE PUMP DCfDC CONVERTER
SLVS21SA - JUNE 1999 - REVISED SEPTEMBER 1999
PWPPACKAGE
(TOP VIEW)
GND
SYNC
ENABLE
FB
OUT
C1+
IN
C1PGND
PGND
10
2
20
19
3
4
5
6
7
8
18
17
16
15
14
13
12
11
9
10
GND
ClK
COM
SKIP
Thermal
Pad
OUT
C2+
IN
C2PGND
PGND
Figure 2. Bottom View of PWP Package,
Showing the Thermal Pad
AVAILABLE OPTIONS
PACKAGE
TSSopt
(PWP)
TPS60110PWP
t
This package IS available taped and reeled. To order this packaging
option, add an R suffix to the part number (e.g., TPS60110PWPR).
Terminal Functions
TERMINAL
NAME
NO.
I/O
I
DESCRIPTION.
ClK
19
C1+
6
Input for external clock signal. If the internal clock is used, connect this terminal to GND.
Positive terminal of the charge-pump capacitor C1 F
C1-
8
Negative terminal of the charge-pump capacitor C1 F
C2+
15
Positive terminal of the Charge-pump capac~or C2F
C2-
13
Negative terminal of the charge-pump capacitor C2F
COM
18
I
Mode selection.
When COM is logic low the charge pump operates in push-pull mode to minimize output ripple. When COM is
connected to IN the regulator operates in single-ended mode requiring only one flying capacitor.
ENABLE
3
I
ENABLE Input. The device turns off, the output disconnects from the input, and the supply current decreases to
0.0511A when ENABLE is a logic low. Connect ENABLE to IN for normal operation.
FB
4
I
FEEDBACK input. Connect FB to OUT as close to the load as possible to achieve best regulation. Resistive divider
is on-chip to match internal reference vo~age of 1.22 V.
GROUND. Analog ground for internal reference and control circu~ry. Connect to PGND through a short trace.
GND
1,20
IN
7,14
I
Supply Input. Connect to an input supply in the 2.7-Vt05.4-V range. Bypass INto GND with a (CoI2) I1F capacitor.
Connect both INs through a short trace.
OUT
5,16
0
Regulated 5-V power output. Connect both OUTs through a short trace and bypass OUT to GND with the output
filter capacitor CO.
PGND
9-12
PGND power ground. Charge-pump current flows through this pin. Connect all PGNDs together.
SKIP
17
I
Mode selection. When SKIP is logic low, the charge pump operates in constant-frequency mode. Output ripple
and noise are minimized in this mode. When SKIP is connect to IN, the device operates in pulse skip mode.
Quiescent current is lowest in this mode.
SYNC
2
I
Selection for external clock signal. Connect to GND to use the internally generated clock signal. Connect to IN
for external synchronization. In this case, the clock signal needs to be fed through ClK.
~1ExAs
INSTRUMENTS
8-44
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS60110
REGULATED S-V 300-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS215A - JUNE 1999 - REVISED SEPTEMBER 1999
absolute maximum ratings {unless otherwise noted)t*
Input voltage range, VI (IN, OUT, ENABLE, SKIP, COM, ClK, FB, SYNC) ............... -0.3 V to 5.5 V
Differential input voltage, VID (C1+, C2+ to GND) .............................. -0.3 V to (Va + 0.3 V)
Differential input voltage, VIO (C1-, C2- to GND) ............................. -0.3 V to (VIN + 0.3 V)
Continuous total power dissipation .................................... See Dissipation Rating Tables
Continuous output current ................................................................ 400 mA
Storage temperature range, Tstg .................................................. -55°C to 150°C
lead temperature 1,6 mm (1/16 inch) from case for 10s ....................................... 260°C
Maximum junction temperature, TJ ......................................................... 150°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
:l:VENABLE. VSKIR VCOM. VCLK and VSYNC can exceed VIN up to the maximum rated voltage without increasing the leakage current
drawn by these mode select inputs.
DISSIPATION RATING TABLE 1 - FREE·AIR TEMPERATURE (see Figure 3)
PACKAGE
TA S; 25°C
POWER RATING
PWP
700mW
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
448mW
364mW
DISSIPATION RATING TABLE 2 - CASE TEMPERATURE (see Figure 4)
PACKAGE
TC S; 52.5°C
POWER RATING
DERATING FACTOR
ABOVE TC = 52.5°C
TC = 70°C
POWER RATING
TC = 85°C
POWER RATING
PWP
25W
285.7mW/oC
22.9W
18.5W
DISSIPATION DERATING CURVEt
MAXIMUM CONTINUOUS DISSIPATION§
VB
CASE TEMPERATURE
vs
FREE·AIR TEMPERATURE
1400
30
~
E
I
c
I
o::L
!!I
~
1200
I
c
0
f
1000
0
~
c
r--....
600
E
~
E
I
I
'\
20
~ PWP Package
II)
~
800
0
'E
<3
25
:;:I
~
............
~ i'....
200
Q
A.
o
25
50
75
100
0
E
10
'E0
PWPPackage
~=178OCIW
400
c
15
'" ,
p~
~
E
..........
I
~
125
Measured with the axposed thermal
coupled to an Infinite heat sink with a
thermally conductive compound (the
thermal conductivity of the compound
Is 0.815 W/m· DC). The R9JC is 3.5°CIW.
5
I
Q
A.
150
o
25
TA - Free·Alr Temperature - °C
Figure 3
50
75
100
125
TC - Case Temperature - °C
~
150
Figure 4
§ Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 150°C.
It is recommended not to exceed a junction temperature of 125°C.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-45
TPS60110
REGULATED S-V 30G-mA LOW-NOISE
CHARGE PUMP DCfDC CONVERTER
SLVS215A - JUNE 1999 - REVISED SEPTEMBER 1999
electrical characteristics at CIN = 15 J.LF, C1F = C2F = 2.2 J.LFt, Co = 33 J.LF, Tc = ~oC to 85°C,
ViN=3V, VFB=VO, VENABLE=VIN, VSKIP=VINorOVandVCOM=VCLK=VSYNC=OV(unlessotherwlse
noted)
PARAMETER
TEST CONDITIONS
MIN
VIN
Input voltage
2.7
IOIMAX)
Maximum output current
300
2.7 V < VIN < 3 V,
VO(Start-Up) = 5 V,
Vo
Output voltage
MAX
5.4
4.B
5
3V
I
II
r--\
f
10=150mA
'!i
~
10=1 mAto10mA
0
5.04
5.02
I
4.98
~
4.96
4.92
4.92
3.5
4
4.5
VIN -Input Voltage - V
5
5.5
..--1"'"
(
5
4.94
3
V(SKI:6 = VIN
10=3 mA
5.06
4.94
4.9
2.5
4.9
2.5
Figure 11
tTc
3
4.5
3.5
4
VIN -Input Voltage - V
Figure 12
=25°C, VCOM =VSYNC =0 V, CIN =1511F, C1F =C2F =2.2I1F, Co =3311F, unless otherwise noled
~1ExAs
8-48
1000
Figure 10
V(SKIP)=OV
II
~
10
100
10 - Output Current - mA
5.1
I
1\
VIN=3V
4.7
1000
OUTPUT VOLTAGE
va
INPUT VOLTAGE
5.04
VIN=3.6V
5
Figure 9
I
. YiN =4 V
/
4.8
4.7
>
III
VIN=5.4V
>
VIN=3.6V
"
I
5.2
VIN=5.4V
I . ViN=4V
>
I
5.3
~
V(SKlP)=OV
I
OUTPUT VOLTAGE
va
OUTPUT CURRENT
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75.265
5
5.5
TPS60110
REGULATED S-V 300-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS215A - JUNE 1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICSt
OUTPUT VOLTAGE
OUTPUT VOLTAGE
va
va
TIME
5.05
>
I
TIME
I
I
V{SKIP)=OV
VIN =3.6V
10=150mA
Co = 22 Ill" + 10 I1F
X5Rceramic
5.04
I
Constant
Frequency
Mode
>
I
III
al
!
~
'i
5.03
~
I
~
,A
IA
IIW
J
,I
A
11
Y
1
~"
i
_A
~
I.
I
I
~
5.02
5.01
5.011--.......--4---+--+----1
V{SKIP) = VIN
VIN=3.6V
10= 150mA
o
2
4.99':-_-:':--_-:'::--_~--~-~
o
10
8
4
6
t-Tlme-IIB
10
Figure 13
~
I
I
>
5.04
t
~
50
I
5.03
5.02
40
LOAD TRANSIENT RESPONSE
5.05
I
i
30
Figure 14
LOAD TRANSIENT RESPONSE
>
20
t- Time-lIB
""""'"
.11
'1"1"
..
~
~-
..".,.
~
.-
t-I"""
...
IILI.'"
1"'''1
I
I
~
5.01
- V{SKIP) = 0 V
VIN=3.6V
_ 10= 10 mAto 300 mA _
_
_
Constant
Frequency
Mode
1
-
I
1
-
I
2
4
6
8 10 12 14
t-Tlme-me
16
18
20
.9
2
Figure 15
4
6
8 10 12 14
t-Tlme-ms
16
18
20
Figure 16
tTc = 25°C, VCOM = VSYNC = 0 V, CIN = 1511F, C1F = C2F= 2.2I1F, Co = 33I1F, unless otherwise noted
~lEXAS
INSTRUMENTS
POST OFRCE BOX 655303 • OALLAS, TEXAS 76265
8-49
TPS60110
REGULATED 5-V 300-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS215A - JUNE 1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICSt
LINE TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
>
I
t
5.08
.~
V(SKIP)=OV
I10=150mA
5.06
I
~
>
.,-
y.........
~
5
4
~
Z
3
2
I
\
\,
\,
2
3
4
5
6
I-TIme-ms
7
8
10
I.q
~
4
!
3
:>
2
\
o
2
4
5
6
7
8
9
10
FREQUENCY SPECTRUM
PULSE-5KIP MODE*
V(SKIP) = VIN
VIN=3V
10=150mA
I-t------t---------t- RBW 300 Hz
-
=
-
60
>::I.
III
50
'C
I
!
3
100r------r------~-----.----__,
70
0
\,
,
Figure 18
V(SKIP)=OV
VIN=3V
10=150mA
RBW = 300 Hz
80
'5
\
I-Tlme-ms
90
'C
..
\
~,.
5
FREQUENCY SPECTRUM
CONSTANT FREQUENCY MODE*
>::I.
I
I.,
.d.
5.02
Figure 17
III
!
mA
5.04
~
I
9
5.06
_ 10=1
I
Pulse-Sklp Mode
>
Z
o
I
5
i
\
I
V(SKI~=VIN
~
I
I
:>
~~
["1" ....
;:
~
i
!
5.08
~
r,"\
'1
5.02
5
.5
t
I
5.04
I
t
Constanl
Frequency Mode
I
~
I
II
>
I
I
40
30
l,l
~I
I..
1
LI.
I...
.l
20
10
0
0
2.5
7.5
5
10
O~----~------~----~----~
o
2.5
5
f - Frequency - MHz
f - Frequency - MHz
Figure 19
Figure 20
. tTc = 25°C, VCOM = VSYNC = 0 V, CIN = 15 j!F, C1 F = C2F = 2.2 j!F, Co = 33 j!F, unless otherwise noled
:j:Test circuit: TPS6011 OEVM-132
~TEXAS
INSTRUMENTS
8-50
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7.5
10
TPS60110
REGULATED S-V 300-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS215A - JUNE 1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICSt
FREQUENCY SPECTRUM
CONSTANT FREQUENCY MODE:!:
90
70
ID
'\::J
I
'5
!0
90
I
V(SKIP)=OV
VIN=3V
10=10mA
RBW = 300 Hz
80
>::I.
FREQUENCY SPECTRUM
PULSE-8KIP MODE:!:
-
70
60
>::I.
ID
50
'\::J
40
!
0
30
60
50
\
I
'5
~
.1,
II I I
.JII.iJ 11..J.
40
30
20
20
10
10
o
V(SKIP) = VIN
VIN =3V
10= 10mA
RBW=300 Hz
80
o
o
2.5
5
7.5
10
V 'y ~.,
o
I
~
START·UP TIMING
6
...
RO = 16.5 a
VIN =3V
5
'-110.
"'
60
>
I
~=Hi9h
Skip = Low
10
7.5
Figure 22
100
'#
.11. • .1.
f - Frequency - MHz
EFFICIENCY
vs
INPUT VOLTAGE
70
.k
5
2.5
Figure 21
80
-
\,.
y\,..
f - Frequency - MHz
90
-
"""'"
4
GI
CI
.!
~
~
'5
a.
'5
.~
50
ffi
40
0
30
~
~
3
/
Enable
2
I
/
I
r
/OUTPUT
.",- ~
20
0
10
o
2.5
-1
3
3.5
4
5
4.5
5.5
o
200
400
600
800
1000
1200
t-TIme"1!s
VIN -Input Voltage - V
Figure 23
Figure 24
tTc = 25°C, VCOM = VSYNC = 0 V, CIN = 15ILF, C1F = C2F = 2.21LF, Co = 33ILF, unless otherwise noted
:j:Test circuit: TPS60110EVM-132
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-51
TPS60110
REGULATED S-V 300-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS215A - JUNE 1999 - REVISED SEPTEMBER 1999
detailed description
operating principle
The TPS6011 0 charge pump provides a regulated 5-V output from a 2.7-V to 5.4-V input. It delivers a maximum
load current of 300 mA. Designed specifically for space critical battery powered applications, the complete
charge pump circuit requires only four external capacitors. The circuit can be optimized for highest efficiency
at light loads or lowest output noise. The TPS6011 0 consists of an oscillator, a 1.22-V bandgap reference, an
internal resistive feedback circuit, an error amplifier, high current MOSFET switches, a shutdown/start-up
circuit, and a control circuit (Figure 25)
CHARGE PUMP 1
0°
T11~
~
OSCILLATOR
IN
T12
180°
C1+
I
C1T13
"
"/
SKIP
T14L
f--I OUT
,/
COM
ClK
PGND
CONTROL
CIRCUIT
FB
IA
SYNC
I
~
~'''VIN
...
----t
CHARGE PUMP 2
T21
-:".
ENABLE t-
SHUTDOWN!
START-UP
CONTROL
-=-
"
"
~
IN
T22
C2+
T23
C2-
T24
L
~
-L
T
f--I
OUT
PGND
GND
Figure 25. Functional Block Diagram TPS60110
The oscillator runs at a 50% duty cycle. The device consists of two single-ended charge pumps which operate
with 1800 phase shift. Each Single ended charge pump transfers charge into its transfer capacitor (CxF) in one
half of the period. During the other half of the period (transfer phase), CxF is placed in series with the input to
transfer its charge to Co. While one single-ended charge pump is in the charge phase, the other one is in the
transfer phase. This operation guarantees an almost constant output current which ensures a low output ripple.
If the clock were to run continuously, this process would eventually generate an output voltage equal to two times
the input voltage (hence the name doubler). In order to provide a regulated fixed output voltage of 5 V, the
TPS60110 uses either pulse-skip mode or constant-frequency mode. Pulse-skip mode and constant-frequency
mode are externally selected via the SKIP input pin.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75285
TPS60110
REGULATED S-V 300-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS215A - JUNE 1999 - REVISED SEPTEMBER 1999
detailed description {continued}
start-up procedure
During start-up, i.e. when ENABLE is set from logic low to logic high, the switches T12 and T14 (charge pump
1), and the switches T22 and T24 (charge pump 2) are conducting to charge up the output capacitor until the
output voltage Vo reaches O.8xVIN' When the start-up comparator detects this limit, the IC begins to operate
in the mode selected with SKIP and COM. This start-up charging of the output capacitor guarantees a short
start-up time and eliminates the need for a Schottky diode between IN and OUT.
pulse-skip mode
In pulse-skip mode (SKIP = high), the error amplifier disables switching of the power stages when it detects an
output higher than 5 V. The oscillator halts. The IC then skips switching cycles until the output voltage drops
below 5 V. Then the error amplifier reactivates the oscillator and switching of the power stages starts again. The
pulse-skip regulation mode minimizes operating current because it does not switch continuously and
deactivates all functions except bandgap reference and error amplifier when the output is higher than 5 V. When
switching is disabled from the error amplifier, the load is also isolated from the input. SKIP is a logic input and
should not remain floating. The typical operating circuit of the TPS60110 in pulse skip mode is shown in
Figure 1.
constant-frequency mode
When SKIP is low, the charge pump runs continuously at the frequency fosc. The control circuit, fed from the
error amplifier, controls the charge on C1F and C2F by driving the gates of the FETs T12fT13 and T22fT23,
respectively. When the output voltage falls, the gate drive increases, resulting in a larger voltage across C1 F
and C2F This regulation scheme minimizes output ripple. Since the device switches continuously, the output
noise contains well-defined frequency components, and the circuit requires smaller external capaCitors for a
given output ripple. However, constant-frequency mode, due to higher operating current, is less efficient at light
loads than pulse-skip mode.
SKIP COMCLK
INPUT - -__- - - - - -__~IN
OUT~~------~-- OUTPUT
2.7Vto 5.4 V
IN
OUT
5 V 300 mA
T+ CO=33IlF
TPS60110 FB
C1+
C1-
S
ENABLE
OFF/ON
C2+
C2SYNC
PGND GND
Figure 26. Typical Operating Circuit TPS60110 in Constant Frequency Mode
Table 1. Tradeoffs Between Operating Modes
FEATURE
PULSE-8KIP MODE
(SKIP = High)
CONSTANT-FREQUENCY MODE
(SKIP = Low)
X
Best light-load efficiency
X
Smallest external component size for a given output ripple
Output ripple amplitude
Output ripple frequency
Load regulation
Small amplitude
Very small amplitude
Variable
Constant
Very good
Good
NOTE: Even In pulse-skip mode the output ripple amplitude is small if the push-pull operating mode is selected via COM.
~TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS, TEXAS 75265
8--53
TPS60110
REGULATED S-V 300-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS215A-JUNE 1999 - REVISED SEPTEMBER 1999
detailed description (continued)
push-pull operating mode
=
In push-pull operating mode (COM low), the two single-ended charge pumps operate with 1800 phase shift.
The oscillator signal has a 50% duty cycle. Each single-ended charge pump transfers charge into its transfer
capacitor (CxF) in one-half of the period. During the other half of the period (transfer phase), CxF is placed in
series with the input to transfer its charge to CO, While one single-ended charge pump is in the charge phase,
the other one is in the transfer phase. This operation guarantees an almost constant output current which
ensures a low output ripple. COM is a logic input and should not remain floating. The typical operating circuit
of the TPS60110 in push-pull mode is shown in Figure 1 and Figure 26.
single-ended operating mode
When COM is high, the device runs in single-ended operating mode. The two single-ended charge pumps
operate in parallel without phase shift. They transfer charge into the transfer capacitor (CF) in one half of the
period. During the other half of the period (transfer phase), CF is placed in series with the input to transfer its
charge to Co. In single-ended operating mode only one transfer capacitor (CF = C1 F + C2F) is required, resulting
in less board space.
INPUT
2.7Vto5.4V -
......- - -................ IN
IN
...-----~
OUT 1-.....> - - - -......OUT
+
TPS60110 FB
C1+
...-----1 C1-
...J
OFF/ON
ENABLE
C2+ r----,
T
OUTPUT
5 V 300 mA
CO=33I1F
C2SYNC
PGND GND
Figure 27. Typical Operating Circuit TPS60110 In Single-Ended Operating Mode
Table 2. Tradeoffs Between Operating Modes
FEATURE
PUSH-PULL MODE
(COM Low)
SINGLE-ENDED MODE
(COM High)
Small amplitude
Large amplitude
=
Output ripple amplitude
=
X
Smallest board space
detailed description (continued)
shutdown
Driving ENABLE low places the device in shutdown mode. This disables all switches, the oscillator, and control
logic. The device typically draws 0.05-~ (1-~ max) of supply current in this mode. Leakage current drawn from
the output is as low as 1 j.LA max. The device exits shutdown once ENABLE is set high level. The typical no-load
shutdown exit time is 20 j.LS. When the device is in shutdown, the load is isolated from the input and the output
is high impedance.
-
~TEXAS
8-54
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75255
TPS60110
REGULATED S-Y 300-mA LOW-NOISE
CHARGE PUMP DC/DC CONYERTER
SLVS215A - JUNE 1999 - REVISED SEPTEMBER 1999
external clock signal
Ifthe device operates at a user defined frequency, an external clock signal can be used. Therefore, SYNC needs
to be connected to IN and the external oscillator signal can drive ClK. The maximum external frequency is
limited to 800 kHz. The switching frequency of the converter is half of the external oscillator frequency. It is
recommended to operate the charge pump in constant-frequency mode if an external clock signal is used so
that the output noise contains only well-defined frequency components.
External Clock
INPUT
2.7 V to 5.4 V
SKIP COMCLK
--.>----.. . . ---.---1 ININ
CIN
+
1511FT
S
OUTPUT
5V300mA
OUT
OUT
TPS60110 FB
C1+
C2+
C1-
C2-
ENABLE
+
T
C2F
2.211F
-=
Co =33 I1F
SYNC
OFF/ON
Figure 28. Typical Operating Circuit TPS60110 With External Synchronization
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-55
TPS60110
REGULATED S-V 300-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS215A-JUNE 1999- REVISED SEPTEMBER 1999
APPLICATION INFORMATION
capacitor selection
The TPS6011 0 requires only four external capacitors as shown in the basic application circuit. Their values are
closely linked to the output current capacity, output noise requirements, and mode of operation. Generally, the
transfer capacitors (CxF) will be the smallest.
The input capacitor improves system efficiency by reducing the input impedance and stabilizes the input current.
CIN is recommended to be about two to four times as large as CxF.
The output capacitor (Co) can be selected from 8-times to 50-times larger than CxFo depending on the mode
of operation and ripple tolerancet. Tables 3 and 4 show capacitor values recommended for low
quiescent-current operation (pulse-skip mode) and for low output voltage ripple operation (constant-frequency
mode). A recommendation is given for smallest size.
Table 3. Recommended Capacitor Values for Low Quiescent-Current Operationt
(pulse-skip mode)
Co
CIN
VIN
[V]
(f.tF]
.lolmA]
(f.tF]
TANTALUM
3.6
225
3.6
225
3.6
300
3.6
300
(f.tF]
CxF
CERAMIC
15
TANTALUM
2.2
4.7 + 10, (X5R)
15
4.7 + 10, (X5R)
145
22 + 10, (X5R)
2.2
2.2
..
CERAMIC
33
55
135
33
22 + 10, (X5R)
2.2
OUTPUT
VOLTAGE
RIPPLEVpp
[mV]
75
t All measurements are done With additional 1-I1F X7R ceramiC capacHors at Input and output .
Table 4. Recommended Capacitor Values for Low Output Voltage Ripple Operatlont
(constant-frequency mode)
CIN
M
10
[mAl
3.6
225
3.6
225
3.6
300
3.6
300
VIN
Co
CxF
II1F]
1I1F]
TANTALUM
CERAMIC
15
TANTALUM
2.2
4.7 + 10, (X5R)
,
[11F]
15
..
4.7 + 10, (X5R)
17
33
22 + 10, (X5R)
2.2
2.2
CERAMIC
33
2.2
C9 2: 33 MF
~1ExAs
8--56
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
6
22
22 + 10, (X5R)
t All measurements are done With addHlonal1-I1F X7R ceramic capacitors at Input and output.
tin constant·frequency mode always select
OUTPUT
VOLTAGE
RIPPLEVpp
ImV]
8
TPS60110
REGULATED S-V 300-rnA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS215A - JUNE 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
For the TPS60110, the smallest board space size can be achieved using Sprague's 595D-series tantalum
capacitors for input and output. However, with the trend towards high capacitance ceramic capacitors in smaller
size packages, these type of capacitors might soon become competitive in size.
Table 5. Recommended Capacitors
MANUFACTURER
PART NUMBER
CAPACITANCE
TYPE
TaiyoYuden
LMK2128J105KG-T
LMK212BJ225MG-T
LMK316BJ475KL-T
JMK316BJ106ML-T
LMK432BJ226MM-T
1 !IF
2.2!lF
4.7!lF
IO!lF
22!lF
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
AVX
0805ZC105KAT2A
1206ZC225KAT2A
TPSCI56K020R0450
TPSC336K010R0375
1 !IF
2.2!lF
15!lF
33!lF
Ceramic
Ceramic
Tantalum
Tantalum
Sprague
595D156X06R3A2T
595D156XOO16B2T
595D336X06R3A2T
595D336XOO16B2T
595D336XOO16C2T
15!lF
15!lF
33!lF
33!lF
33!lF
Tantalum
Tantalum
Tantalum
Tantalum
Tantalum
Kemet
T494C156K010AS
T494C336K010AS
15!lF
33!lF
Tantalum
Tantalum
Table 6 lists the manufacturers of recommended capacitors. In most applications surface-mount tantalum
capacitors will be the right choice. However, ceramic capacitors will provide the lowest output voltage ripple due
to their typically lower ESA.
Table 6. Recommended Capacitor Manufacturers
MANUFACTURER
CAPACITOR TYPE
TaiyoYuden
X7R1X5R ceramic
www.t-yuden.com
AVX
X7R1X5R ceramic
TPS-series tantalum
www.avxcorp.com
Sprague
595D-series tantalum
593D-series tantalum
www.vishay.com
Kemet
T494-series tantalum
www.kemet.com
INTERNET
power dissipation
The power dissipated in the TPS60110 depends on output current and is approximated by:
P DISS = 10 x (2 V IN
-
V o ) for 10 < < 10
Po ISS must be less than that allowed by the package rating. See the ratings for 20-PowerPADTM package
power-dissipation limits and deratings.
-
~lExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-57
TPS60110
REGULATED5-V 300-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS215A-JUNE 1999- REVISED SEPTEMBER 1999
APPLICATION INFORMATION
layout
All capacitors should be soldered in close proximity to the IC. A PCB layout proposal for a two-layer board is
given in Figure 29. Care has been taken to connect both single-ended charge pumps symmetrically to the load
to achive optimized output voltage ripple performance. The proposed layout also provides improved thermal
performance as the exposed leadframe is soldered to the PCB. The bottom layer of the PCB is a ground plain
only. All ground areas on the PCB should be connected. Connect ground areas on top layer to the bottom layer
via through hole connections.
OUT
GND
_ ClK
- COM
= .....~~-,
SKIP
C2+
C2-
IN
Figure 29. Recommended PCB Layout for TPS60110 (top view)
An evaluation module forthe TPS6011 0 is available and can be ordered under literature code SLVP132 or under
product code TPS60110EVM-132.
~TEXAS
8-58
INSTRUMENTS '
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS60110
REGULATED S-V 300-mA i..OW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS215A - JUNE 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
applications proposals
paralleling of two TPS60110 to deliver 600 rnA
The TPS60110 can be paralleled to yield higher load currents. The circuit of Figure 30 can deliver 600 rnA at
an output voltage of 5 V. It uses two TPS6011 0 devices in parallel. The devices can share the output capacitors,
but each one requires its own transfer capacitors and input capacitor. For best performance, the paralleled
devices should operate in the same mode (pulse-skip or constant frequency).
INPUT
2.7Vto
S.4V 10llF
+
T
S
OFF/ON
IN
IN
1-,,--4~....-
OUT
OUT
TPS60110 FB
C1+
C2+
C1-
C2-
ENABLE SYNC
PGND GND
OUTPUT
SV
300mA
ENABLE SYNC
PGND GND
Figure 30. Paralleling of Two TPS60110
TPS60110 with LC output filter for ultra low ripple
For applications where extremely low output ripple is required, a small LC filter is recommended. This is shown
in Figure 31. The addition of a small inductor and filter capacitor will reduce the output ripple well below what
could be achieved with capacitors alone. The corner frequency of 500 kHz was chosen above the 300 kHz
switching frequency to avoid loop stability issues in case the feedback is taken from the output of the LC filter.
Leaving the feedback (FB) connection point before the LC filter, the filter capacitance value can be increased
to achieve even higher ripple attenuation without affecting stability margin.
OUTPUT
'--.....- -.... S v 300 mA
INPUT
2.7VtoS.4V -
SKIP COM CLK
.....- - -....-1 IN
OUT
IN
OUT
TPS60110 FB 1 - - - - - - - - - - - - - '
S
OFF/ON
C1+
C2+
C1-
C2-
ENABLE
SYNC
PGND GND
Figure 31. TPS60110 With LC Filter for Ultra Low Output Ripple Applications
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALlAS. TEXAS 75265
8-59
TPS60110
REGULATED S-V 300-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS21SA - JUNE 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
related Information
application reports
For more application information see:
•
PowerPA{)TM Application Report (Literature Number: SLMA002)
•
TPS6010x/rPS6011x Charge Pump Application Report (Literature Number: SLVA070)
device family products
Other devices in this family are:
PART NUMBER
LITERATURE
NUMBER
TPS60100
SLVS2l3
Regulated 3.3-V, 200-mA Low-Noise Charge Pump DC/DC Converter
TPS60l0l
SLVS2l4
Regulated 3.3-V, l00-mA Low-Noise Charge Pump DC/DC Converter
TPS60lll
SLVS2l6
Regulated 5-V, l50-mA Low-Noise Charge Pump DC/DC Converter
DESCRIPTION
~TEXAS
8-60
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS60111
REGULATED S-V 1S0-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
features
applications
•
•
•
•
•
Up to 150-mA Output Current
Less Than 10-mVpp Output Voltage Ripple
No Inductors Required/Low EMI
Regulated 5-V ±4% Output
Only Four External Components Required
•
•
•
•
•
•
Up to 90% Efficiency
2.7-V to 5.4-V Input Voltage Range
60-J,1A Quiescent Supply Current
0.05-J,1A Shutdown Current
Load Isolated in Shutdown
Space-Savlng Thermally-Enhanced TSSOP
PowerPADTM Package
Replaces DC/DC Converters With Inductors in
- Battery-Powered Applications
- Li-Ion Battery to 5-V Conversion
- Portable Instruments
- Battery-Powered Microprocessor
Systems
- Miniature Equipment
- Backup-Battery Boost Converters
- PDAs
- Laptops
- Handheld Instrumentation
- Medical Instruments
• Evaluation Module Available
(TPS60110EVM-132)
output voltage ripple
description
The TPS60111 step-up, regulated charge pump
generates a 5-V ±4% output voltage from a 2.7-V
to 5.4-V input voltage (three alkaline, NiCd, or
NiMH batteries; or, one lithium or lithium ion
battery). Output current is 150 mA from a 3-V
input. Only four external capacitors are needed to
build a complete low-noise dc/dc converter. The
push-pull operating mode of two single-ended
charge pumps assures the low output voltage
ripple as current is continuously transferred to the
output. From a 3-V input, the TPS60111 can start
into full load with loads as low as 33 Q.
The TPS60111 features either constant frequency
mode to minimize noise and output voltage ripple
or the power-saving pulse-skip mode to extend
battery life at light loads. The TPS60111 switching·
frequency is 300 kHz. The logic shutdown function
reduces the supply current to 1-~ (max) and
disconnects the load from the input. Special
current-control circuitry prevents excessive current from being drawn from the battery during
start-up. This dc/dc converter requires no
inductors and has low EM!. It is available in the
small 20-pin TSSOP PowerPADTM package
(PWP).
5.2
~~~~~~"T'""'"~~~~~-'-"
5.15 ---
>
I
t
5.1 -
5.05-
~
SKIP =COM = ClK = 0 v
VIN=3.6V
....... lo=150mA
4.9
.... : ......... : ... Co = 22 ILF + 10 ILF
X5RCeramic
4.85
4.8 0
0.5
1 1.5 2
2.5
3 3.5 4 4.5 5
t - Tlme-I!S
typical operating circuit
INPUT
2.7Vto
5.4 V
CIN
4.7 ILF
+
T
S
OFF/ON
SKIP COMClK
IN
OUTt--....IN
OUT
TPS60110 FB
C1+
C2+
C1-
C2-
OUTPUT
5V
150mA
...-
ENABLE SYNC
PGND GND
Figure 1
PowerPAD is a trademark of Texas Instruments Incorporated.
~:;r!~:=:.,;;~::.:.::g=..:
_
warranty. Production processing d... nOi n..._11y Includa
toiling 01011 paramotofl.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
1Hl1
TPS60111
REGULATED S-V 1S0-mA LOW·NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS216A-JUNE 1999- SEPTEMBER 1999
PWPPACKAGE
(TOP VIEW)
10
2
3
GND
SYNC
ENABLE
FB
OUT
C1+
IN
C1PGND
PGND
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
ClK
COM
SKIP
OUT
C2+
IN
C2PGND
PGND
Figure 2_ Bottom View of PWP Package,
Showing the Thermal Pad
AVAILABLE OPTIONS
PACKAGE
TSSOpt
(PWP)
TPS60111PWP
tThis package is available taped and reeled. To order this packaging
option, add an R suffix to the part number (e.g., TPS60111 PWPR).
Terminal Functions
TERMINAL
NAME
NO.
DESCRIPTION
1/0
ClK
19
C1+
6
I
C1-
8
Negative terminal of the charge-pump capacitor C1 F
C2+
15
Positive terminal of the charge-pump capacitor C2F
C2-
13
COM
18
I
Mode selection.
When COM is logic low the charge pump operates in push-pull mode to minimize output ripple. When COM is
connected to IN the regulator operates II) single-ended mode requiring only one flying capacitor.
ENABLE
3
I
ENABLE Input. The device turns off, the output disconnects from the input, and the supply current decreases to
0.0511A when ENABLE is a logic low. Connect ENABLE to IN for normal operation.
FB
4
I
FEEDBACK input. Connect FB to OUT as close to the load as possible to achieve best regulation. Resistive divider
is on-chip to match internal reference voltage of 1.22 V.
Input for ex1ernal clock signal. If the internal clock is used, connect this terminal to GND.
Positive terminal of the charge-pump capacitor C1 F
Negative terminal of the charge-pump capacitor C2F
GND
1,20
IN
7,14
I
Supply Input. Connect to an input supply in the 2.7-V to 5.4-V range. Bypass IN to GND with a (C0'2) I1F capacitor.
Connect both INs through a short trace.
OUT
5,16
0
Regulated 5-V power output. Connect both OUTs through a short trace and bypass OUT to GND with the output
filter capacitor CO.
PGND
GROUND. Analog ground for internal reference and control circuitry. Connect to PGND through a short trace.
·9-12
PGND power ground. Charge-pump current flows through this pin. Connect all PGNDs together.
SKIP
17
I
Mode selection. When SKIP Is logic low the charge pump operates inconstant-frequency mode. Thus output ripple
and noise are minimized. When SKIP Is connected to IN, the regulator operates in low-quiescent-current
pulse-skip mode.
SYNC
2
I
Selection for external clock signal. Connect to GND to use the internally generated clock signal. Connect to IN
for external synchronization. In this case, the clock signal needs to be fed through ClK.
~TEXAS
H2
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TPS60111
REGULATED S-V 1S0-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS216A-JUNE 1999-SEPTEMBER 1999
absolute maximum ratings {unless otherwise noted}t*
Input voltage range, VI (IN, OUT, ENABLE, SKIP, COM, CLK, FB, SYNC) ............... -0.3 V to 5.5 V
Differential input voltage, VID (C1 +, C2+ to GND) .............................. -0.3 V to (VO + 0.3 V)
Differential input voltage, VID (C1-, C2- to GND) ............................. -0.3 V to (VIN + 0.3 V)
Continuous total power dissipation .................................... See Dissipation Rating Tables
Continuous output current ................................................................ 200 mA
Storage temperature range, Tstg .................................................. -55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10s ....................................... 260°C
Maximum junction temperature, TJ ......................................................... 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause pennanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" is not
Implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
:j:VENABLE, VSKIP, VCOM, VCLK and VSYNC can exceed VIN up to the maximum rated voltage w~hout Increasing the leakage current
drawn by these mode select inputs.
DISSIPATION RATING TABLE 1 - FREE-AIR TEMPERATURE (see Figure 3)
PACKAGE
TA S 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = B5°C
POWER RAnNG
PWP
700mW
5.6mW/OC
448mW
364mW
DISSIPATION RATING TABLE 2 - CASE TEMPERATURE (see Figure 4)
PACKAGE
TC S 62_5°C
POWER RATING
DERATING FACTOR
ABOVE TC = 62_5°C
TC = 70°C
POWER RAnNG
TC = 85°C
POWER RAnNG
PWP
25W
285.7mWrC
22.9W
18.5W
DISSIPATION DERATING CURVEt
vs
FREE-AIR TEMPERATURE
MAXIMUM CONTINUOUS DISSIPATION§
vs
CASE TEMPERATURE
1400
==E
I
c
Iis
!0
30
:=I
1200
c
0
E
~
E
I
I
'\
I
1000
0;
is
800
'"
20
~
0
~
~
8
25
r-......
800
~
c
400
~ ...........
200
~
o
25
~E
PWPPackage
......... ~=17BoCIW
50
" "PWP Package
15
"
10
~
~
E
.........
'=
:E
~
75
100
125
TA - Free-Air Temperature - °C
I
Measured with the exposed thermal
coupled to an Inflnlla heat sink with a
tharmally conductive compound (the
thermal conductivity 01 the compound
Is 0.815 W/m . °e). The ReJe Is 3.SoelW.
5
Q
a..
150
o
25
Figure 3
50
I\.
75
100
125
TC - Case Temperature - °C
~
150
Figure 4
§ DISSipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 150°C.
It is recommended not to exceed a junction temperature of 125°C.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS60111
REGULATED S-V 1S0-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS21SA-JUNE 1999-SEPTEMBER 1999
electrical characteristics at CIN = 151lF, C1F = C2F = 2.2IlFt, Co = 331lF, TC = -40°C to 85°C,
VIN=3V, VFB= Yo, VENABLE= VIN, VSKIP= VINorOVandVCOM=VCLK= VSYNC=OV(unlessotherwise
noted)
PARAMETER
t
TEST CONDITIONS
MIN
VIN
Input voltage
2.7
10(MAX)
Maximum output current
150
MAX
5.4
0<10<75mA,
TC = 25°C
4.8
5
5.2
3V < VIN < 5 V,
0<10<150mA
4.8
5
5.2
4.8
5
5.25
Output voltage
5 V < VIN < 5.4 V,
0<10<150mA
VO(RIP)
Output voltage ripple
10= 150mA,
VSKIP=OV
10(lEAK)
Output leakage current
VIN=3.6V,
VENABlE=OV
IQ
Quiescent current
(no-load input current)
VSKIP = VIN = 3.6 V
VSKIP=OV,
VIN=3.6V
IDD(SDN)
Shutdown supply current
VIN=3.6V,
VENABlE=OV
fOSC(intl
Internal switching frequency
VIN=3.6V
fOSC(ext)
External clock frequency
VSYNC=VIN,
External clock duty cycle
VSYNC=VIN,
UNIT
V
mA
2.7 V < VIN < 3 V,
VO(Start-Up) = 5 V,
Vo
10*
V
mVpp
1
60
90
2.8
I!A
I!A
mA
0.05
1
I!A
200
300
400
kHz
VIN = 2.7 Vto 5.4 V
400
600
800
kHz
VIN= 2.7V to 5.4 V
20%
Efficiency
10 = 75mA
VINl
Input voltage low,
ENABLE, SKIP, COM, ClK, SYNC
VIN=2.7V
VINH
Input voltage high,
ENABLE, SKIP, COM, ClK, SYNC
VIN=5.4V
II(lEAK)
Input leakage current,
ENABLE, SKIP, COM, ClK, SYNC
VENABLE = VSKIP = VCOM = VClK =
VSYNC = VGND or VIN
Output load regulation
VO=5V,
TC=25°C
1 mA<10<150mA
Output line regulation
3 V
I
8,
Ii
5.1
'viN = 4 V
~
I
G)
CI
L
'5
~
I
~
~
'5
5
I
~
VIN=2.7V1
,
4.7
10
100
10 - Output Current - mA
4.7
1000
10
100
10 - Output Current - mA
1
Figure 9
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
5.1
5.1
V(SKIP)=OV
5.08
5.04
~
5.02
J
'5
I.
..- j.---
10=150mA
.......r:::::::
"".- ~
~
>
I
G)
CI
~
~
10=1 mAt010mA
5.06
5.04
5.02
I
4.98
I
I
4.98
~
4.96
~
4.96
~
0
5
4.94
4.94
4.92
3
3.5
4
4.5
VIN - Input Voltage - V
5
5.5
4.9
2.5
Figure 11
tTc
3
4
3.5
4.5
VIN -Input Voltage - V
Figure 12
=25°C, VCOM =VSYNC =0 V, CIN =1511F, C1F and C2F =2.211F (X7R ceramic), Co =3311F, unless otherwise noted
~TEXAS
INSTRUMENTS
8-66
---
./"
5
4.92
4.9
2.5
V(SKIP) = VIN
10 = 1 mA to 150 mA
5.08
5.06
CD
1000
Figure 10
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
I
V~~ = 3 V
1
4.9
4.8
1
..
VIN=2.7V
4.8
>
L
0
VIN =3V
4.9
1-'
5
~
"1 l\
0
5.1
~
~
III
VIN=5.4V
V
ViN=4V
I
VIN = 3.6 V
>
VIN=3.6V
1,(
I
5.2
VIN =5.4V
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5
5.5
TPS60111
REGULATED S-Y 1S0-mA LOW-NOISE
CHARGE PUMP DC/DC CONYERTER
SLVS216A-JUNE 1999-SEPTEMBER 1999
TYPICAL CHARACTERISTICSt
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
TIME
5.05
>
I
TIME
I
I
V(SKIP) = 0 V
VIN =3.6V
10= 150mA
CO=22I1F + 1O I1F
X5Rceramic
5.04
I
Constant
Frequency
Mode
>
I
CD
al
~
~
:;
r::L
IIY
If
:;
0
I
~
IA
A
5.03
11 -I\.,.....
1\
.I
Y
1
IJ"'
I"
~
i
I
~
5.02
5.01
i
5.01i-----lt-----'t------'t-----ii----;
V(SKIP) = VIN
VIN =3.6V
10=150mA
o
4
2
4.99':-_--:':-_--:':-_---:':-_---''-_--:'
o
10
8
6
t- Tlme-118
Figure 13
~
i
I
~
1
~
G
I
i
I
,9
40
50
LOAD TRANSIENT RESPONSE
>
5.05
I
I
i
20
30
t-Tlme-118
Figure 14
LOAD TRANSIENT RESPONSE
>
10
CD
J
5.04
5.03
~ .u
'.,.
.'
rrT"
5.02
...
~
IILIl
'OJ
r'1'¥"
...
IT"I
I
~
5.01
V(SKIP) = 0 V
10 = 10mAto 150 mA
_ VIN=3.6V
300 -
-
200
r-r--
Constant
Frequency
Mode
-
100
o
i
1
~
G
I
i
I
o
2
4
6
8
10
12
14
16
18
20
,9
200t---r--ii---r--i--r--i--r--i--r--i
100t--~~i---r~--r~--r--i~-r--i
O~~~--~~~~~~~~~~
2
4
6
8 10 12 14 16 18 20
o
t-Tlme-ms
t-Tlme-ms
Figure 15
Figure 16
fTc = 25°C, VCOM = VSYNC = 0 V, CIN = l511F, C1F and C2F = 2.211F (X7R ceramic), Co = 3311F, unless otherwise noted
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-67
TPS60111
REGULATED S-V 1S0-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS216A - JUNE 1999 - SEPTEMBER 1999
TYPICAL CHARACTERISTICSt
LINE TRANSIENT RESPONSE
>
5.08
1
t
5.06
"S
5.04
I'
5.02
g
~
5
>
1
t
~
"S
a.
.5
1con~ntl
Frequency Mode
V(SKIP)=OV
I- 10=150mA
!
5.04
1
~
......
I... •..•
t
V(SKI:6 = VIN
5.06 I- 10=1 rnA
::
5
>
1
5
4
3
1
\
t
\,
\,
~
4
i
3
1
Z
2
3
4
5
6
7
8
9
10
>"
.... .1A
2
o
2
70
\,
\,
4
5
6
t-Tlme-me
7
8
9
10
V(SKlP) = VIN
VIN=3V
10= 150 rnA
H------+------+_ RBW = 300 Hz
-
-
60
>::1.
DI
50
"a
1
~
\
100.------r------,------r------,
V(SKIP)=OV
VIN=3V
10 =150 rnA
RBW= 300 Hz
80
0
3
\
FREQUENCY SPECTRUM
PULSE-5KIP MODE*
90
"S
\.
Figure 18
FREQUENCY SPECTRUM
CONSTANT FREQUENCY MODE*
"a
~IJI.... u
~I,
::
Figure 17 .
DI
I
\
~
t-TIme-me
>::1.
!
.1
Pulse-Skip Mode
5
\
Z
>"
5.02
~
~
~
I
~
.
ij l..aot.
f+-
5.08
1
,
,
~
LINE TRANSIENT RESPONSE
>
I
!
40
30
IL 1,
II
Il,
I.
LI.
oW
La.
20
10
0
0
2.5
5
7.5
10
O~~--~------~----~----~
o
f - Frequency - MHz
2.5
5
7.5
f - Frequency - MHz
Figure 19
Figure 20
tTc =25°C, VCOM =VSYNC =0 V, CIN =15ILF, C1F and C2F =2.21LF (X7Rceramic), Co =33ILF, unless otherwise noted
:nest circuit: TPS60110EVM-132 \'Vith TPS60111
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
TPS60111
REGULATED S-V 1S0-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS216A-JUNE 1999-SEPTEMBER 1999
TYPICAL CHARACTERISTICSt
FREQUENCY SPECTRUM
CONSTANT FREQUENCY MODE;
90..----"T"""----r-----r1- - - - .
I - - - - + - - - + _ V(SKIP) = 0 V
80
VIN=3V
lo=10mA
7 0 1 - - - - + - - - + _ RBW = 300 Hz
III
V(SKlP) = VIN
VIN=3V
IO=10mA
RBW = 300 Hz
80
70
50~_+_r-+------+_-----+------1
"I
90
-
60~---+---+_-----+------1
>::l.
FREQUENCY SPECTRUM
PULSE·SKIP MODE;
>::l.
III
"S
i
r::L
I
30~
.1.
I
I
I
0
_J ..Jt 1 _I J
50
\
40
20
10r------+------+_-----+------1
10
o
\j
y\,..
30
20
o~____~------~----~----~
o
2.5
5
7.5
10
f - Frequency - MHz
-
60
I
S
-
V~ '\a&....,.....
o
2.5
Figure 21
..&
.11\ ..Ju. ....,
5
7.5
f - Frequency - MHz
10
Figure 22
EFFICIENCY
vs
START·UP TIMING
INPUT VOLTAGE
6
100
lo=150mA
90
80
"'-
5
"
70
'#.
60
I
~
c
>
I
.~=Hlgh
Skip = Low
50
I
Ro=33.3Q
VIN=3V
""'"
If
4
CD
~
I
~
S
,e.
~
40
d
30
~
J
3
/
Enable
2
I
20
V
V
./
OUTPUT
./'"
0
10
o
2.5
-1
3
3.5
4
4.5
VIN -Input Voltage - V
5
5.5
o
200
=
=
600
800
1000
1200
t .,. Time --I!S
Figure 23
=
400
Figure 24
=
tTc 25°C, VCOM VSYNC 0 V, CIN l511F, C1F and C2F
:j:Test circuit: TPS60ll0EVM-132 with TPS60ll1
=2_211F (X7R ceramic), Co =33I1F, unless otherwise noted
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-69
TPS60111
REGULATED S·V 1S0-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS216A - JUNE 1999 - SEPTEMBER 1999
detailed description
operating principle
The TPS60111 charge pump provides a regulated 5-V outputfrom a 2. 7 -V to 5.4-V input. It delivers a maximum
load current of 150 rnA. Designed specifically for space critical battery powered applications, the complete
charge pump circuit requires only four external capacitors. The circuit can be optimized for highest efficiency
at light loads or lowest output noise. The TPS60111 consists of an oscillator, a 1.22-V bandgap reference, an
internal resistive feedback circuit, an error amplifier, high current MOSFET switches, a shutdown/start-up
circuit, and a control circuit (Figure 25).
CHARGE PUMP 1
~
00
----+
OSCillATOR
T11~
IN
T12 \
180 0
C1+
I
--..
./
SKIP
T13
T14
/
C1-
L
---<
./
J::
T
C1F
OUT
./
COM
ClK
PGND
CONTROL
CIRCUIT
FB
L
SYNC
I
~
r1
CHARGE PUMP 2
~
~ T21
~
~
IN
T22 \
C2+
-
ENABLE t-
SHUTDOWNI
START-UP
CONTROL
.L
T
T23
./
-'
T24L
-
OM,.
-=-
C2-
0
OUT
PGND
GND
Figure 25_ Functional Block Diagram TPS60111
The oscillator runs at a 50% duty cycle. The device consists of two single-ended charge pumps which operate
with 1800 phase shift. Each single ended charge pump transfers charge into its transfer capacitor (CxF) in one
half of the period. During the other half of the period (transfer phase), CxF is placed in series with the input to
transfer its charge to CO. While one single-ended charge pump is in the charge phase, the other one is in the
transfer phase. This operation guarantees an aimost constant output current which ensures a low output ripple.
If the clock were to run continuously, this process would eventually generate an output voltage equal to two times
the input voltage (hence the name doubler). In order to provide a regulated fixed output voltage of 5 V, the
TPS60111 uses either pulse-skip mode or constant-frequency mode. Pulse-skip mode and constant-frequency
mode are externally selected via the SKIP input pin.
~TEXAS
8-70
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS60111
REGULATED S-V 1S0-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS216A-JUNE 1999-SEPTEMBER 1999
detailed description (continued)
start-up procedure
During start-up, Le. when ENABLE is set from logic low to logic high, the switches T12 and T14 (charge pump
1), and the switches T22 and T24 (charge pump 2) are conducting to charge up the output capacitor until the
output voltage Vo reaches O.8XVIN' When the start-up comparator detects this limit, the IC begins to operate
in the mode selected with SKIP and COM. This start-up charging of the output capacitor guarantees a short
start-up time and eliminates the need for a Schottky diode between IN and OUT.
pulse-skip mode
In pulse-skip mode (SKIP = high), the error amplifier disables switching of the power stages when it detects an
output higher than 5 V. The oscillator halts. The IC then skips switching cycles until the output voltage drops
below 5 V. Then the error amplifier reactivates the oscillator and switching of the power stages starts again. The
pulse-skip regulation mode minimizes operating current because it does not switch continuously and
deactivates all functions except bandgap reference and error amplifier when the output is higher than 5 V. When
switching is disabled from the error amplifier, the load is also isolated from the input. SKIP is a logic input and
should not remain floating. The typical operating circuit of the TPS60111 in pulse skip mode is shown in Figure
1.
constant-frequency mode
When SKIP is low, the charge pump runs continuously at the frequency fose. The control circuit, fed from the
error amplifier, controls the charge on C1F and C2F by driving the gates of the FETs T12rr13 and T22rr23,
respectively. When the output voltage falls, the gate drive increases, resulting in a larger voltage across C1 F
and C2F This regulation scheme minimizes output ripple. Since the device switches continuously, the output
noise contains well-defined frequency components, and the circuit requires smaller external capacitors for a
given output ripple. However, constant-frequency mode, due to higher operating current, is less efficient at light
loads than pulse-skip mode.
INPUT
2.7Vto5.4V
SKIP COMCLK
- .....- - -.....--1
IN
IN
OUTI-......- - -......OUT
+
TPS60111 FB
C1+
C1-
S
ENABLE
OFF/ON
T
C2+
OUTPUT
5 V 150 mA
Co
=33iJ.F
C2F
C2-
1 iJ.F
SYNC
PGND GND
Figure 26. Typical Operating Circuit TPS60111 in Constant Frequency Mode
Table 1. Tradeoffs Between Operating Modes
FEATURE
PULSE-SKIP MODE
(SKIP = High)
CONSTANT-FREQUENCY MODE
(SKIP = Low)
X
Best light·load efficiency
X
Smallest external component size for a given output ripple
Output ripple amplitude
Output ripple frequency
Load regulation
Small amplitude
Very small amplitude
Variable
Constant
Very good
Good
NOTE: Even In pulse-skip mode the output ripple amplitude IS small if the push-pull operating mode IS selected via COM.
~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-71
TPS60111
REGULATED S-V 1S0-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS216A-JUNE 1999-SEPTEMBER 1999
detailed description (continued)
push-pull operating mode
In push-pull operating mode (COM =low), the two single-ended charge pumps operate with 1800 phase shift.
The oscillator signal has a 50% duty cycle. Each single-ended charge pump transfers charge into its transfer
capacitor (CxF) in one-half of the period. During the other half of the period (transfer phase), CxF is placed in
series with the input to transfer its charge to CO, While one single-ended charge pump is in the charge phase,
the other one is in the transfer phase. This operation guarantees an almost constant output current which
ensures a low output ripple. COM is a logic input and should not remain floating. The typical operating circuit
of the TPS60111 in push-pull mode is shown in Figure 1 and Figure 26.
single-ended operating mode
When COM is high, the device runs in single-ended operating mode. The two single-ended charge pumps
operate in para"el without phase shift. They transfer charge into the transfer capacitor (CF) in one half of the
period. During the other half of the period (transfer phase), CF is placed in series with the input to transfer its
charge to CO, In single-ended operating mode only one transfer capacitor (CF = C1 F + C2F) is required, resulting
in less board space.
SKIP COMCLK
INPUT
OUT 1-......- - -......2.7Vto5.4V - - . - - -.....-.>--1 IN
IN
OUT
+
TPS60111 FB
.-------1 C1+
r - ' - - - - - I C1-
S
OFF/ON
C2+ 1 - - - - .
T
OUTPUT
5 v 150 rnA
CO=15J.1F
C2-
ENABLE
SYNC
PGND GND
Figure 27. Typical Operating CircultTPS60111 in Single-Ended Operating Mode
Table 2. Tradeoffs Between Operating Modes
FEATURE
Output ripple amplitude
PUSH-PULL MODE
(COM = Low)
SINGLE-ENDED MODE
(COM = High)
Small amplitude
Large amplitude
X
Smallest board space
detailed description (continued)
shutdown
Driving ENABLE low places the device in shutdown mode. This disables a" switches, the oscillator, and control
logiC. The device typically draws 0.05-~ (1-~ max) of supply current in this mode. Leakage current drawn from
the output is as low as 1 ~ max. The device exits shutdown once ENABLE is set high level. The typical no-load
shutdown exit time is 20 j.lS. When the device is in shutdown, the load is isolated from the input and the output
is high impedance.
~TEXAS
8-72
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
TPS60111
REGULATED S-V 1S0-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS216A-JUNE 1999-SEPTEMBER 1999
external clock signal
If the device operates at a user-defined frequency, an external clock signal can be used. Therefore, SYNC needs
to be connected to IN and the external oscillator signal can drive ClK. The maximum external frequency is
limited to 800 kHz. The switching frequency of the converter is half of the external oscillator frequency. It is
recommended to operate the charge pump in constant-frequency mode if an external clock signal is used so
that the output noise contains only well-defined frequency components.
External Clock
SKIP COMCLK
OUT
OUT
TPS60111 FB
INPUT
2.7V to 5.4 V
OUTPUT
5 V 150 mA
IN
IN
CIN
4.71lF
+
T
C1+
C1-
S
ENABLE
+
T
C2+
C2-
C2F
11lF
Co =33 IlF
-=
SYNC
OFF/ON
Figure 28. Typical Operating Circuit TPS60111 With External Synchronization
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-73
TPS60111
REGULATED S-Y 1S0-mA LOW-NOISE
CHARGE PUMP DC/DC CONYERTER
SLVS216A-JUNE 1999- SEPTEMBER 1999
APPLICATION INFORMATION
capacitor selection
The TPS60111 requires only four external capacitors as shown in the basic application circuit. Their values are
closely linked to the output current capacity, output noise requirements, and mode of operation. Generally, the
transfer capacitors (CxF) will be the smallest.
The input capacitor improves system efficiency by reducing the input impedance and stabilizes the input current.
CIN is recommended to b about two to four times as large as Cx!=-
r
The output capacitor (Co) can be selected from 8·times to 50-times larger than CxFo depending on the mode
of operation and ripple tolerancet. Tables 3 and 4 show capacitor values recommended for low
quiescent-current operation (pulse-skip mode) and for low output voltage ripple operation (constant-frequency
mode). A recommendation is given for smallest size.
Table 3. Recommended Capacitor Values for Low Quiescent-Current Operationt
(pulse-skip mode)
CIN
VIN
M
10 [mA]
3.6
75
3.6
75
3.6
150
3.6
150
Co
CxF
blF]
1ItF]
1ItF]
TANTALUM
CERAMIC
4.7
TANTALUM
1
4.7 (X7R)
4.7
4.7 (X7R)
150
1
10 (X5R)
1
..
CERAMIC
15
OUTPUT
VOLTAGE
RIPPLEVpp
[mV]
15
105
150
1
10 (X5R)
105
tAli measurements are done with addltlonall-I1F X7R ceramic capacitors at Input and output.
Table 4_ Recommended Capacitor Values for Low Output Voltage Ripple Operatlont
(constant-frequency mode)
CIN
VIN
[V]
10
[rnA]
t
t
75
3.6
75
3.6
150
3.6
150
[11F]
1ItF]
TANTALUM
3.6
Co
CxF
[11F]
CERAMIC
4.7
TANTALUM
1
4.7 (X7R)
4.7
4.7 (X7R)
1
Cg > 33 MF
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
17
33
22 + 10, (X5R)
All measurements are done with additional l-I1F X7R ceramic capacitors at input and output.
in constant-frequency mode always select
8-74
10
22 + 10, (X5R)
1
1
CERAMIC
33
OUTPUT
VOLTAGE
RIPPLEVpp
[mV]
10
TPS60111
REGULATED 5-V 150-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS216A-JUNE 1999-SEPTEMBER 1999
APPLICATION INFORMATION
For the TPS60111, the smallest board space size can be achieved using Sprague's 595D-series tantalum
capacitors for input and output. However, with the trend towards high capacitance ceramic capacitors in smaller
size packages, these type of capacitors might soon become competitive in size.
Table 5. Recommended Capacitors
MANUFACTURER
PART NUMBER
CAPACITANCE
TYPE
TaiyoYuden
LMK212BJ105KG-T
LMK212BJ225MG-T
LMK316BJ475KL-T
JMK316BJ106ML-T
LMK432BJ226MM-T
11lF
2.21lF
4.71lF
10llF
221lF
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
AVX
0805ZC105KAT2A
1206ZC225KAT2A
TPSC475K035R06OO
TPSC156K020R0450
TPSC336K010R0375
11lF
2.21lF
4.71lF
151lF
33IlF
Ceramic
Ceramic
Tanlalum
Tantalum
Tanlalum
Sprague
595D475XOO16A2T
595D156X06R3A2T
595D156XOO16B2T
595D336X06R3A2T
595D336XOO16B2T
595D336XOO16C2T
4.71lF
151lF
151lF
331lF
331lF
331lF
Tanlalum
Tantalum
Tanlalum
Tanlalum
Tanlalum
Tanlalum
Kemet
T494B475M010AS
T494C156K010AS
T 494C336K01 OAS
4.71lF
151lF
331lF
Tantalum
Tantalum
Tanlalum
Table 6 lists the manufacturers of recommended capacitors. In most applications surface-mount tantalum
capacitors will be the right choice. However, ceramic capacitors will provide the lowest output voltage ripple due
to their typically lower ESR.
Table 6. Recommended Capacitor Manufacturers
MANUFACTURER
CAPACITOR TYPE
INTERNET
TaiyoYuden
X7R1X5R ceramic
www.t-yuden.com
AVX
X7R1X5R ceramic
TPS-series tantalum
www.avxcorp.com
Sprague
595D-series lanlalum
593D-series tantalum
www.vishay.com
Kemet
T 494-series tantalum
www.kemet.com
power dissipation
The power dissipated in the TPS60111 depends on output current and is approximated by:
PDISS
= 10 x (2 VIN - Vol
for 10 < < 10
POISS must be less than that allowed by the package rating. See the ratings for 20-PowerPADTM package
power-dissipation limits and deratings.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-75
TPS60111
REGULATED S-V 1S0-mA LOW-NOISE
CHARGE PUMP DCIDC CONVERTER
SLVS216A - JUNE 1999 - SEPTEMBER 1999
APPLICATION INFORMATION
layout
All capacitors should be soldered in close proximity to the IC. A PCB layout proposal for a two-layer board is
given in Figure 29. Care has been taken to connect both single-ended charge pumps symmetrically to the load
to achive optimized output voltage ripple performance. The proposed layout also provides improved thermal
performance as the exposed leadframe is soldered to the PCB. The bottom layer of the PCB is a ground plain
only. All ground areas on the PCB should be connected. Connect ground areas on top layer to the bottom layer
via through hole connections.
OUT
GND
_ ClK
-------COM
'" SKIP
C2+
C2-
GND
IN
Figure 29. Recommended PCB Layout for TPS60111 (top view)
The evaluation module designed for the TPS6011 0 can, with slight modifications, be used for evaluation of the
TPS60111. The EVM can be ordered under literature code SLVP132 or under product code
TPS60110EVM-132.
~TEXAS
8-76
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS60111
REGULATED S-V 1S0-mA LOW-NOISE
CHARGE PUMP DC/DC CONVERTER
SLVS216A-JUNE 1999-SEPTEMBER 1999
APPLICATION INFORMATION
applications proposals
TPS60111 with LC output filter for ultra low ripple
For applications where extremely low output ripple is required, a small LC filter is recommended. This is shown
in Figure 30. The addition of a small inductor and filter capacitor will reduce the output ripple well below what
could be achieved with capacitors alone. The corner frequency of 500 kHz was chosen above the 300 kHz
switching frequency to avoid loop stability issues in case the feedback is taken from the output of the LC filter.
Leaving the feedback (FB) connection point before the LC filter, the filter capacitance value can be increased
to achieve even higher ripple attenuation without affecting stability margin.
O.lI1H
~1--...rvYY''---",______, -
INPUT
2.7VtoS.4V
--.----.--1
S
OUTPUT
S V lS0 mA
IN
IN
ENABLE
OFF/ON
SYNC
PGND GND
Figure 30. TPS60111 With LC Filter for Ultra Low Output Ripple Applications
related information
application reports
For more application information see:
•
PowerPAlYM Application Report (Literature Number: SLMA002)
•
TPS6010xITPS6011x Charge Pump Application Report (Literature Number: SLVA070)
device family products
Other devices in this family are:
PART NUMBER
LITERATURE
NUMBER
TPS60100
SLVS213
Regulated 3.3-V, 200-mA Low-Noise Charge Pump DC/DC Converter
TPS60101
SLVS214
Regulated 3.3-V. l00-mA Low-Noise Charge Pump DC/DC Converter
TPS60110
SLVS215
Regulated 5-V, 300-mA Low-Noise Charge Pump DC/DC Converter
DESCRIPTION
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
f'r-77
8-78
TL5001, TL5001A, TL5001V
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
Os
o OR P PACKAGE
•
•
•
•
•
•
Complete PWM Power Control
3.6-V to 40-V Operation
Internal Undervoltage-Lockout Circuit
Internal Short-Circuit Protection
Oscillator Frequency ••. 20 kHz to 500 kHz
Variable Dead Time Provides Control Over
Total Range
• ±3% Tolerance on Reference Voltage
(TL5001A)
(TOP VIEW)
OUT
VCC
COMP
FB
2
7
3
6
4
5
GND
RT
DTC
SCP
description
The TL5001 and TL5001 A incorporates on a single monolithic chip all the functions required for a
pulse-width-modulation (PWM) control circuit. Designed primarily for power-supply control, the TL5001/A
contains an error amplifier, a regulator, an oscillator, a PWM comparator with a dead-time-control input,
undervoltage lockout (UVLO), short-circuit protection (SCP), and an open-collector output transistor. The
TL5001A has a reference voltage tolerance of ±3% compared to ±5% for the TL5001.
The error-amplifier common-mode voltage ranges from 0 V to 1.5 V. The non inverting input of the error amplifier
is connected to a 1-V reference. Dead-time control (DTC) can be set to provide 0% to 100% dead time by
connecting an external resistor between DTC and GND. The oscillator frequency is set by terminating AT with
an external resistor to GND. During low VCC conditions, the UVLO circuit turns the output off until VCC recovers
to its normal operating range.
The TL5001 C and TL5001 AC are characterized for operation from -20°C to 85°C. The TL50011 and TL5001 AI
are characterized for operation from -40°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
-20°C to 85°C
-40°C to S5°C
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
CHIP FORM
(Y)
TL5001Y
TL5001CO
TL5001CP
TL5001ACO
TL5001ACP
TL500110
TL50011P
-
TL5001AIO
TL5001AIP
-
The 0 package IS available taped and reeled. Add the suffix R to the device type
(e.g., TL5001 CDR). Chip forms are tested at TA = 25°C.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Copyright © 1998. Texas Instruments Incorporated
8-79
TL5001, TL5001A, TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVSOB4D - APRIL 1994 - REVISED JUNE 1998
schematic for typical application
VI --~--.------.---.
+
T
2
VCC
5 SCP
Vo
1
COMP 3
TL5001/A
6
OTC
7
FB
RT
4
GNO
8
-=
functional block diagram
VCC
RT
OTC
OUT
2
7
6
1
lOT
r--------;r:::::~~~--+---~~-.r---~
FB
COMP~3~----~------~-----!=+++~======~__~______~____~~
SCp~5~---------------r------__~~~
18
GNO
~TEXAS
INSTRUMENTS
8-80
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A,TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084D - APRIL 1994 - REVISED JUNE 1998
TL5001Y chip information
This chip, when properly assembled, displays characteristics similar to the TL5001 C. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
OUT
(1)
(8)
(2)
(7)
VCC
COMP
FB
GND
RT
TL5001Y
(3)
(6)
(4)
(5)
DTC
SCP
-::
CHIP THICKNESS:
11 MILS TYPICAL
BONDING PADS:
7X7 MILS MINIMUM
TJ max
=150°C
TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
~
~
~
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-81
,
TL5001, TL5001A, TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084D-APRIL 1994- REVISED JUNE 1998
detailed description
voltage reference
A 2.5-V regulator operating from Vee is used to power the internal circuitry of the TL5001 and TL5001A and
as a reference for the error amplifier and SCP circuits. A resistive divider provides a 1-V reference for the error
amplifier noninverting input. The TL5001 1-V reference remains within 5% of nominal over the operating
temperature range. In theTL5001A, the 1-V reference remains within 3% of nominal.
error amplifier
The error amplifier compares a sample of the dc-to-dc converter output voltage to the 1-V reference and
generates an error signal for the PWM comparator. The dc-to-dc converter output voltage is set by selecting
the error-amplifier gain (see Figure 1), using the following expression:
Vo = (1 + A1/A2) (1 V)
3
Compensation
Natwork
r----------------,
COMP
TL500t/A
Rt
ToPWM
Comparator
R2
elGND
I
I
I
I
I
I
I
I
IL. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .JI
Figure 1. Error-Amplifier Gain Setting
The error-amplifier output is brought out as COMP for use in compensating the dc-to-dc converter control loop
for stability. Because the amplifier can only source 45 J,tA, the total dc load resistance should be 100 kO or more.
oscillator/PWM
The oscillator frequency (fosd can be set between 20 kHz and 500 kHz by connecting a resistor between AT
and GND. Acceptable resistor values range from 15 kO to 250 kO. The oscillator frequency can be determined
by using the graph shown in Figure 5.
The oscillator output is a triangular wave with a minimum value of approximately 0.7 V and a maximum value
of approximately 1.3 V. The PWM comparator compares the error-amplifier output voltage and the DTC input
voltage to the triangular wave and turns the output transistor off whenever the triangular wave is greater than
the lesser of the two inputs.
dead-time control (DTC)
DTC provides a means of limiting the output-switch duty cycle to a value less than 100%, vyhich is critical for
boost and flyback converters. A current source generates a reference current (lOT) at DTC that is nominally
equal to the current at the oscillator timing terminal, AT. Connecting a resistor between DTC and GND generates
a dead-time reference voltage (VOT), which the PWM/DTC comparator compares to the oscillator triangle wave
as described in the previous section. Nominally, the maximum duty cycle is 0% when VOT is 0.7 V or less and
100% when VOT is 1.3 V or greater. Because the triangle wave amplitude is a function of frequency and the
source impedance of AT is relatively high (12500), choosing AOT for a specific maximum duty cycle, D, is
accomplished using the following equation and the voltage limits for the frequency in question as found in
Figure 11 (Voscmax and Voscmin are the maximum and minimum oscillator levels):
~TEXAS
8--82
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A, TL5001Y
PULSE·WIDTH·MODULATION CONTROL CIRCUITS
SLVS084D- APRIL 1984 - REVISED JUNE 1998
dead·time control (OTe) (continued)
RDT = (Rt
+ 1250)
[D(Vosc max - Voscmin )
+ Voscmin ]
where
ROT and Rt are in ohms, D in decimal
Soft start can be implemented by paralleling the DTC resistor with a capacitor (COT) as shown in Figure 2. During
soft start, the voltage at DTC is derived by the following equation:
V DT "" IDTRDT ( 1-e
(-tjR DTC DT))
l
COT
r--t1---,,6'-10TC
T_
ROT
TL5001/A
1.....-_ _ _---1
Figure 2. Soft-Start Circuit
If the dc-to-dc converter must be in regulation within a specified period of time, the time constant, RO~OT'
should be t0l3 to t0l5. The TL5001/A remains off until VOT '" 0.7 V, the minimum ramp value. COT is discharged
every time UVLO or SCP becomes active.
undervoltage-Iockout (UVLO) protection
The undervoltage-Iockout circuit turns the output transistor off and resets the SCP latch whenever the supply
voltage drops too low (approximately 3 V) for proper operation. A hysteresis voltage of 200 mV eliminates false
triggering on noise and chattering.
short-circuit protection (SCP)
The TL5001/A includes short-circuit protection (see Figure 3), which turns the power switch off to prevent
damage when the converter output is shorted. When activated, the SCP prevents the switch from being turned
on until the internal latching circuit is reset. The circuit is reset by reducing the input voltage until UVLO becomes
active or until the SCP terminal is pulled to ground externally.
When a short circuit occurs, the error-amplifier output at COMP rises to increase the power-switch duty cycle
in an attempt to maintain the output voltage. SCP comparator 1 starts an RC timing circuit when COMP exceeds
1.5 V. If the short is removed and the error-amplifier output drops below 1.5 V before time out, normal converter
operation continues. If the fault is still present at the end of the time-out period, the timer sets the latching circuit
and turns off the TL5001/A output transistor.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-83
TLSOO1, TLS001A,TLS001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVSOB4D -APRIL 1994 - REVISED JUNE 1998
short-circuit protection (SCP) (continued)
r---------------------------------,
r
I
I
I
I
I
I
2.5 V
scp
cscpl
Iscp
To Output
Drive Logic
Figure 3. SCP Circuit
The timer operates by charging an external capacitor (Cscp), connected between the SCP terminal and ground,
towards 2.5 V through a 185-kn resistor (RSCp). The circuit begins charging from an initial voltage of
approximately 185 mV and times out when the capacitor voltage reaches 1 V. The output of SCP comparator
2 then goes high, turns on Q2, and latches the timer circuit. The expression for setting the SCP time period is
derived from the following equation:
VSCP
= (2.5 -
0.185)(1 - e-tlt ) + 0.185
where
t=
RSCpCscp
The end of the time-out period, tscP, occu,rs when Vscp = 1 V. Solving for CSCP yields:
Cscp = 12.46. x tscp
where
t is in seconds, C in 1lF.
tscp must be much longer (generally 10 to 15 times) than the converter start-up period or the converter will not
start.
output transistor
The output of the TL5001!A is an open-collector transistor with a maximum collector current rating of 21 mA and
a voltage rating of 51 V. The output is turned on under the following conditions: the oscillator triangle wave is
lower than both the DTC voltage,. and the error-amplifier output voltage, the UVLO circuit is inactive, and the
short-circuit protection circuit is inactive.
~TEXAS
8-84
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL5001,TL5001A,TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084D - APRIL 1994 - REVISED JUNE 1998
absolute maximum ratings over operating free-air temperature range {unless otherwise noted)f
Supply voltage, Vee (see Note 1) ........................................................... 41 V
Amplifier input voltage, VI(FB) ....................................................... . . . . . .. 20 V
Output voltage, Vo, OUT .................................................................. 51 V
Output current, 10, OUT .................................................................. 21 rnA
Output peak current, 10(peak), OUT ....................................................... 100 rnA
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating ambient temperature range, TA: TL5001 C, TL5001 AC ..................... -20°C to 85°C
TL50011, TL5001AI ....................... -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TAS25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA=70°C
POWER RATING
TA = 85°C
POWER RATING
D
725mW
5.8mW/"C
464mW
377mW
P
1000 mW
8.0mW/oC
640mW
520mW
recommended operating conditions
Supply voltage, VCC
Amplifier input voltage, VIIFB)
MIN
MAX
3.6
40
UNIT
V
0
1.5
V
Output voltage, YO, OUT
50
V
Output clJrrent, 10, OUT
20
mA
45
COMP source current
COMP de load resistance
100
IIA
k.Q
Oscillator timing resistor, Rt
15
250
k.Q
Oscillator frequency, fosc
20
500
kHz
-20
85
-40
85
Operating ambient temperature, TA
I TL5001C, TL5001AC
I TL50011, TL5001AI
electrical characteristics over recommended operating free-air temperature range,
f08C = 100 kl;fz (unless otherwise noted)
'C
Vee = 6 V,
reference
,-
PARAMETER
TEST CONDITIONS
Output voltage
COMP connected to FB
Input regulation
VCC = 3.6 V to 40 V
Output voltage change with temperature
TL5001
MIN
TL5001A
TVP1
MAX
MIN
1
1.05
0.97
2
12.5
0.95
UNIT
TYPt
MAX
1
1.03
V
2
12.5
mV
TA = -20°C to 25°C (C suffix)
-10
-1
10
-10
-1
10
TA = -40°C to 25°C (I suffix)
-10
-1
10
-10
-1
10
TA = 25°C to 85°C
-10
-2
10
-10
-2
10
mVN
t All typical values are at TA = 25°C.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-85
TL5001, TLS001A,TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVSOB4D - APRIL 1994 - REVISED JUNE 1998
vee =6 V,
electrical characteristics over recommended operating free-air temperature range,
fosc = 100 kHz (unless otherwise noted) (continued)
undervoltage lockout
PARAMETER
TEST CONDITIONS
TL5001A
TL5001
MIN
TYP't
MAX
MIN
TYP't
MAX
UNIT
Upper threshold voltage
TA=25°C
3
3
Lower threshold voltage
TA=25°C
2.8
2.8
V
V
Hysteresis
TA=25°C
100
200
100
200
mV
Reset threshold voltage
TA=25°C
2.1
2.55
2.1
2.55
V
t All typical values are at TA = 25°C.
short-circuit protection
PARAMETER
TEST CONDITIONS
TL5001
TL5001 A
MIN
TYP't
MAX
MIN
TYP't
MAX
UNIT
SCP threshold voHage
TA = 25°C
0.95
1.00
1.05
0.97
1.00
1.03
V
SCP voltage, latched
No pull up
140
185
230
140
185
230
mV
60
120
60
120
mV
-10
-15
-20
-10
-15
-20
ItA
SCP voltage, UVLO standby
Nopullup
Input source current
TA=25°C
SCP comparator 1 threshold voltage
t
1.5
1.5
V
All typical values are at TA = 25°C.
oscillator
PARAMETER
TEST CONDITIONS
Frequency
MIN
TL5001
TYpt
Rt=100kn
Standard deviation of frequency
Frequency change with voltage
MIN
TYP't
UNIT
100
kHz
15
15
kHz
TA = -40°C to 25°C
-4
-0.4
TA = -20°C to 25°C
'-4
TA = 25°C to 85°C
-4
Voltage at RT
MAX
100
1
1
VCC= 3.6 Vt040V
Frequency change with temperature
TL5001A
MAX
kHz
4
-4
-0.4
4
kHz
-0.4
4
-4
-0.4
4
kHz
-0.2
4
-4
-0.2
4
kHz
V
1
1
t All typical values are at TA = 25°C.
dead-time control
PARAMETER
Output (source) current
TEST CONDITIONS
=1=
TL5001
TYpt
TL5001A
MAX
MIN
TYP't
MAX
ITL5oo1C
VlDn = 1.5 V
0.9xIRT*
1.1 x IRT 0.9xlRT*
1.1 xlRT
ITL5OO11
V(DTl = 1.5 V
0.9xIRT*
1.2x1RT 0.9xlRT*
1.2x1RT
Input threshold voltage
t
MIN
Duty cycle = 0%
0.5
Duty cycle = 100%
0.7
1.3
AI! typical values are at TA = 25°C.
Output source current at RT
~lExAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALlAS, TEXAS 75265
0.5
1.5
0.7
1.3
1.5
UNIT
ItA
V
TL5001, TL5001A, TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084D - APRIL 1994 - REVISED JUNE 1998
electrical characteristics over recommended operating free-air temperature range, Vee
fosc 100 kHz (unless otherwise noted) (continued)
=
=6 V,
error amplifier
PARAMETER
TEST CONDITIONS
Input voltage
TL5001
MIN
Output voltage swing
MAX
MIN
1.5
0
-160
-500
0
VCC = 3.6 Vto40V
Input bias current
I Positive
1.5
2.3
INegative
0.3
Open-loop voltage amplification
1.5
0.4
1.5
UNIT
TYPt
MAX
1.5
V
-160
-500
nA
V
2.3
0.3
80
Unity-gain bandwidth
t
TL5001A
TYP't
0.4
V
80
dB
1.5
MHz
Output (sink) current
VI(FB) = 1.2 V,
COMP=1V
100
600
100
600
~
Output (source) current
VI(FB) = 0.8 V,
COMP= 1 V
-45
-70
-45
-70
~
All typical values are at TA = 25°C.
output
PARAMETER
TEST CONDITIONS
Output saturation voltage
TYPt
1.5
10= 10mA
VO=50V,
Off-state current
VCC=O
VO=50V
Short-circuit output current
TL5001A
TL5001
MIN
MAX
MIN
2
1.5
MAX
2
10
10
10
10
40
40
VO=6V
TYPt
UNIT
V
IiA
rnA
t All typical values are at TA = 25°C.
total device
TEST CONDITIONS
PARAMETER
Standby supply current
t
TYPt
IOff state
Average supply current
TL5001A
TL5001
MIN
Rt=100kQ
MAX
MIN
TYpt
MAX
UNIT
1
1.5
1
1.5
rnA
1.4
2.1
1.4
2.1
rnA
All typical values are at TA = 25°C.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-87
TL5001, TL5001A, TL5001Y
PULSE·WIDTH·MODULATION CONTROL CIRCUITS
SLVS084D - APRIL 1994 - REVISED JUNE 1998
electrical characteristics, Vee
=6 V, fosc =100 kHz, TA =25°C (unless otherwise noted)
reference
PARAMETER
TEST CONDITIONS
TLSOO1Y
MIN
TVP
MAX
UNIT
Output voltage
COMP connected to FB
1
V
Input regulation
VCC = 3.6 V to 40 V
2
mV
Output voltage change with temperature
-2
mVN
undervoltage lockout
PARAMETER
TL5001V
MIN
TVP
UNIT
MAX
Upper threshold voltage
3
Lower threshold voltage
2.8
V
Hysteresis
200
mV
Reset threshold voltage
2.55
V
V
short-circuit protection
PARAMETER
TEST CONDITIONS
TL5001V
MIN
SCP threshold voltage
TVP
MAX
1
SCP voltage, latched
Nopullup
SCP voltage, UVLO standby
No pull up
Input source current
SCP comparator 1 threshold voltage
UNIT
V
165
mV
60
mV
-15
J.LA
1.5
V
oscillator
PARAMETER
TEST CONDITIONS
Frequency
TLSOO1Y
MIN
MAX
100
Rt=100kO
Standard deviation of frequency
Frequency change with voltage
TVP
VCC = 3.6Vt040V
kHz
15
kHz
1
kHz
-0.4
Frequency change with temperature
kHz
-0.2
Voltage at RT
UNIT
1
V
dead-time control
PARAMETER
TEST CONDITIONS
Input threshold voltage
=
=
TL5001 V
MIN
TVP
Duty cycle = O"k
0.7
Duty cycle = 100%
1.3
MAX
UNIT
V
=
electrical characteristics, Vee 6 V, fOSC 100 kHz, TA 25°C (unless otherwise noted) (continued)
error amplifier
TEST CONDITIONS
PARAMETER
TVP
-160
Input bias current
-!!1TEXAS
INSTRUMENTS
8--88
TL5001V
MIN
POST OFFICE
BOX 655303 • DALLAS, TEXAS 75265
MAX
UNIT
nA
TL5001,TL5001A,TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084D - APRIL 1994 - REVISED JUNE 1998
Output voltage swing
I Positive
2.3
V
I Negative
0.3
V
Open-loop voltage amplification
80
dB
Unity-gain bandwidth
1.5
MHz
IIA
IIA
Output (sink) current
VIIFB) = 1.2 V,
COMP=1V
600
Output (source) current
VI(FB) = 0.8 V,
COMP=1V
-70
output
PARAMETER
TEST CONDITIONS
TL5001Y
MIN
TYP
MAX
UNIT
Output saturation voltage
10=10mA
1.5
V
Short-circuit output current
VO=6V
40
mA
total device
PARAMETER
Standby supply current
Average supply current
TEST CONDITIONS
I Oil state
Rt=100kD
TL5001Y
MIN
TYP
MAX
UNIT
1
mA
1.4
mA
-!111ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-89
TL5001,TL5001A, TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084D- APRIL 1994 - REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
i
DTCJ:;
.
COMP~
~
A~
osc/IVVV
..
6
6~
A
2~'3VI
~ 1
i l l
i
i
PWMlDTC
Comparator.
A
A
1.!V
A
YlV·'VV V\AZi::\I\C)VV'\¥fj~VVv\
1
1
1
1 1
I
I
1
IH
1
1
II
.
11-1_ _ _ _ __
1
OUT
SCP
Comparator 1
I
1.....j.I1,...::.;-I,_ _ _ __
. .
1 1
1
1
.---
i71~V
;1
SCP -,: _ _ _ _..Ji1
i
~~~~
1
SCP
Comparator 2
1
1
I
1
1
0V
I~~____- - - - - - - - - - - - - - - - - - - - - - - - - - - -
VCC X"3V
NOTE A. The waveforms show timing characteristics for an intermittent short circuit and a 10nQer short circuit that Is sufficient to activate SCPo
Figure 4. PWM Timing Diagram
~1ExAs
8-90
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS. TEXAS 75265
TL5001, TL5001A, TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084D - APRIL 1994 - REVISED JUNE 1998
TYPICAL CHARACTERISTICS
OSCILLATION FREQUENCY
vs
AMBIENT TEMPERATURE
OSCILLATOR FREQUENCY
vs
TIMING RESISTANCE
100
1M
Vee=6V
DT Resistance = Rt
TA=25°e
......
98
i
r-...
"
I
~
~
I
i'
I
~
"
'" I""~
94
92
()
88
-50
1M
100 k
90
Rt - Timing Resistance - 0
-25
1.8
I
1.6
t
1.4
~
I
50
75
100
REFERENCE OUTPUT VOLTAGE FLUCTUATION
vs
AMBIENT TEMPERATURE
.,.
TA=25Je
FB and eOMP
Connected Together
0.6 r----,----,.--T""""-""T'"---,-__
Vee=6V
FB and eOMP
0.4
Connected Together
I
c
It
1.2
~
0.8
J
0.6
f
0.4
I
I
I II
I
I
>
25
Figure 6
REFERENCE OUTPUT VOLTAGE
vs
POWER-SUPPLY VOLTAGE
>
o
, TA - Ambient Temperature - °e
Figure 5
2
"
.......
I
J~
10 k
10k
96
Vee=6V
Rt=100kO
DT Resistance = 100 kQ
I
0.2
o
o
f
~
4
2
3
5
6
7
8
Vee - Power-Supply Voltage - V
9
10
_ 0.8 ' - _ . . l - _ - . . L ._ _.L...-_-'-_--L_---'
-50
-25
0
25
50
75
100
TA - Ambient Temperature - °e
Figure 7
Figure 8
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
8-91
TL5001, TL5001A, TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084D - APRIL 1994 - REVISED JUNE 1998
TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT
AVERAGE SUPPLY CURRENT
vs
POWER-SUPPLY VOLTAGE
2
vs
AMBIENT TEMPERATURE
1.3
I
Rt = 100 kn
TA=25°C
C
E
I
~
1.5
~
a>-
0
i
1.1
t
~
CD
0.9
o
o
J
10
20
. 0
-50
40
30
0.8
-25
VCC - Power-Supply Voltage - V
ERROR AMPLIFIER OUTPUT VOLTAGE
vs
OSCILLATOR FREQUENCY
OUTPUT (SINK) CURRENT
1.5
~
vs
>
I
............... ~
t
Voscmax (100% duty cycle)
~
'5
1.2
!
is.
E
~
0.9
~
.!!
I
f
~
0.6
2.5
VCC=6V
VI(FB) = 1.2 V
TA=25°C
(
2
I
I
1.5
is.
Voscmln (zero duty cycle)
~
....
g
W
I
0.3
0.5
.Jl
o
10 k
100 k
1M
fose - Oscillator Frequency - Hz
10M
o
o
0.2
--
Figure 12
~ThxAs
~
J
0.4
10 - Output (Sink) Currant - mA
Figure 11
8-92
100
3
VCC=6V
TA=25°C
I
c
75
50
PWM TRIANGLE WAVE AMPLITUDE VOLTAGE
>
S
25
Figure 10
1.8
CD
'a
o
TA - Ambient Temperature - °C
Figure 9
CD
'"
I
~
E
CI
.........
~
0.5
0
!
~~
aI
CD
I
.............
i
::I
!II
~
.............
1.2
I
C
~
::I
1
.1
.1
VCC=6V
Rt= 100 kn
DT Resistance = 100 kO -
.
INSTRUMENTS
POST OFFICE BOX 655303 • OALlAS, TEXAS 75265
0.6
TL5001,TL5001A,TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084D - APRIL 1994 - REVISED JUNE 1998
TYPICAL CHARACTERISTICS
ERROR AMPLIFIER OUTPUT VOLTAGE
ERROR AMPLIFIER OUTPUT VOLTAGE
vs
vs
OUTPUT (SOURCE) CURRENT
AMBIENT TEMPERATURE
2.46
3
>
I
VCC=6V
VI(FBJ = 0.8 V
TA= 5°C
2.5
>
J
~
:i
~
0
2
til
J
1\
~
:i
ICI.
:i
0
1.5
a.
..g
E
C
E
c
I
-r-....
2.44
2.43
~
Ia.
~
2.45
I
..........
til
VCC=6V
VI(FB) = 0.8 V
No Load
w
0.5
2.42
"'- r-..
2.41
I
~
~
o
\
o
20
40
60
100
80
10 - Output (Sourca) Current - ~
2.40
-50
120
-25
25
50
75
o
TA - Ambient Temperature - °C
Figure 13
ERROR AMPLIFIER CLOSED-LOOP GAIN AND
PHASE SHIFT
vs
vs
AMBIENT TEMPERATURE
OSCILLATOR FREQUENCY
40
240
E
I
til
CI
220
VCC=6V
VI(FB) = 1.2 V
No Load
ID
I
:i
ICI.
:i
0
Ia.
E
C
160
I
140
~
~
./
200
180
V
./
30
c
V
/
'OJ
ClJ
/
I
..........
'a
~
~
"-
......
ICI.
0
0
/
"
1
0
U
10
~
a.
E
0
~
-10
c
I
-25
o
25
50
75
TA - Ambient Temperature - °C
100
-240'
\AV
~
-270'
\
\
r\ I"r-..
-20
10 k
100 k
-180'
-210'
"
,
20
....I
I I II
VCC=6V
TA=25°C
~
120
-50
100
Figure 14
ERROR AMPLIFIER OUTPUT VOLTAGE
>
'""""
1M
-300'
-330'
-360'
10M
fosc - Oscillator Frequency - Hz
Figure 15
Figure 16
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-93
TL5001, TL5001A, TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084D - APRIL 1994 - REVISED JUNE 1998
TYPICAL CHARACTERISTICS
OUTPUT DUTY CYCLE
SCP TIME·OUT PERIOD
vs
DTCVOLTAGE
SCP CAPACITANCE
vs
120
12
VCC=6V
Rt = 100 kf.l
TA=25°C
100
~
I
.!!
8D
/
S~
:::I
Q
60
'$
a.
'$ 40
0
20
o
/
o
I
/
II)
/
E
VCC=6V
Rt = 100 kf.l
DT ResIstance = 200 kf.l
TA=25°C
10
I
"'1:0
l.
II
cb
E
1=
6
/
~
4
j
2
1:1.
I
1.5
V
o
o
2
20
DTC Voltage - V
40
OUTPUT SATURATION VOLTAGE
vs
RT OUTPUT CURRENT
OUTPUT (SINK) CURRENT
2r-----~----_,------T_-----,
VCC=6V
TA=25°C
-50
>
V
I
C
~:::I -40
I
j
/
u
'$
-3~
0
-20
5
-10
V
o
o
/
-10
1.51-----+-----+-----::;0"""'""---;
~
I:
J
I
/
I
W
~
-20
-30
-40
-50
-60
o~----~----~------~----~
o
10 - RT Output Current-1lA
Figure 19
5
10
15
10 - Output (Sink) Current - mA
Figure 20
~TEXAS.
8-94
120
vs
DT Voltage = 1.3 V
TA = 25°C
:9
100
DTC OUTPUT CURRENT
-60
~I
8D
Figure 18
I
~
60
CSCP - SCP CapacItance - nF
Figure 17
c(
::I.
V
V'
I
1:1.
0.5
/~
8
'$
0
V
./
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
20
TL5001, TL5001A,TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084D- APRIL 1994 - REVISED JUNE 1998
APPLICATION INFORMATION
100~t
R1 ;>
4700
~
10V
GND
-=-
Q1
TPS11 01
L1
20~H
~
C3
rll 0.1~F
~~
MBRS140T3
2
5
1
SCP
r--
Vo
56 k.O
R3
43 k.O
.A
COMP
U1
TL5001/A
6
7
3
R5
7.50 k.O
1%
;::::::: C6
0.012 ~F
R4
5.1 k.O
DTC
C1
C2
CR1
Bill of Materials.
TL5001/A
TPS1101
CTX2D-1 or
23 turns of #28 wire on
Micrometels No. T50-26B core
TPSD107M010R0100
TPSD107M010R0100
MBRS140T3
C7
0.0047~F
R6
3.24 k.O
1%
GND
8
Partial
U1
Q1
LI
R7
2.0 kO
T
4
FB
RT
GND
~
C5
H~
R2
+
C2 ;:::::::
100 ~F
10V
VCC
C4
HI1~F
/1+
3.3V
'"'[0 CR1
...J
Texas Instruments
Texas Instruments
Colltronlcs
AVX
AVX
Motorola
NOTES: A. Frequency = 200 kHz
B. Duty cycle = 90% max
C. Soft-start time constant (TC) = 5.6 ms
D. SCP TC = 70 msA
Figure 21. Step-Down Converter
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
H5
8-96
SG2524, SG3524
REGULATING PULSE·WIDTH MODULATORS
SLVS0778 - APRIL 1977 - REVISED JULY 1999
• Complete PWM Power Control Circuitry
• Uncommitted Outputs for Single-Ended or
Push-Pull Applications
• Low Standby Current .•. 8 mA Typ
• Interchangeable With Silicon General
SG2524 and SG3524
o OR N PACKAGE
(TOP VIEW)
IN-
REF OUT
VCC
EMIT2
CURR LlM+
CURR LlM-
description
COL 2
COL 1
4
5
EMIT 1
RT
The SG2524 and SG3524 incorporate all the
SHUTDOWN
CT
functions required in the construction of a
GND
regulating power supply, inverter, or switching
regulator on a single chip. They also can be used
as the control element for high-power-output
applications. The SG2524 and SG3524 were
designed for switching regulators of either polarity, transformer-coupled dc-to-dc converters, transformerless
voltage doublers, and polarity converter applications employing fixed-frequency, pulse-width-modulation
(PWM) techniques. The complementary output allows either single-ended or push-pull application. Each device
includes an on-chip regulator, error amplifier, programmable oscillator, pulse-steering flip-flop, two uncommitted
pass transistors, a high-gain comparator, and current-limiting and shut-down circuitry.
The SG2524 is characterized for operation from -25°C to 85°C, and the SG3524 is characterized for operation
from O°C to 70°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
INPUT
REGULAnON
MAX (MV)
SMALL OUTLINE
(D)
PLASTIC DIP
(N)
DoC to 70°C
30
SG35240
SG3524N
SG3524Y
-25°C to 85°C
20
SG25240
SG2524N
-
CHIP FORM
(V)
The 0 package is available taped and reeled. Add the suffix R to the device type (e.g., SG35240R). Chip
forms are tested at 25°C.
~TEXAS
Copyright © 1999, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1HJ7
SG2524, SG3524
REGULATING PULSE-WIDTH MODULATORS
SLVS077B-APRIL 1917- REVISED JULY 1999
functional block diagram
Vee .."1.,,.5_.-_-1
r-_____.-_____________--'1~6
REF OUT
Vref
COL 1
'EMIT 1
COL 2
RT ~6~_ _ _ _ __I_=_~=:l
EMIT 2
CT 7
r - - -.....-----I--4t--------~ OSC OUT
Vref
ININ+
Error Amplifier
COMP
CURR LlM+
CURR LlMSHUTDOWN
GND
10
1kn
10kn
8
NOTE A. Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted}t
Supply voltage, Vee (see Notes 1 and 2) .................................................... 40 V
Collector output current, lee .............................................................. 100 mA
Reference output current, IO(ref) ........................................................... 50 mA
Current through CT terminal .............................................................. -5 mA
Package thermal impedance, 9JA (see Notes 3 and 4): D package .......................... 112°CIW
N package ............................ 88°CIW
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
Storage temperature range, Ts1g ...••.....•....•.....•.......•.................... -65°C to 150°C
t
Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
Implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network ground terminal.
2. The reference regulator may be bypassed for operation from a fixed S-V supply by connecting the Vee and reference output pin
both to the supply voltage. In this configuration, the maximum supply voltage is 6 V.
3. Maximum Power dissipation is a function of TJ(max). 6JA. and TA. The maximum allowable power dissipation at any
(TJ(max) - TpJ16JA. Operation at the absolute maximum TJ of 150°C can
allowable ambient temperature is PD
Impact reliability.
4. The package'thermal impedance is calculated in accordance with JESD 51, except for through-hole packages which use a trace
length of zero.
=
~TEXAS
8--98
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SG2524, SG3524
REGULATING PULSE-WIDTH MODULATORS
SLVS0778 - APRIL 1977 - REVISED JULY 1999
recommended operating conditions
SG2524
SG3524
UNIT
MIN
MAX
Supply voltage, VCC
8
40
8
40
V
Reference output current
0
50
0
50
mA
-0.03
-2
-0.03
-2
mA
1.8
100
1.8
100
kn
0.001
0.1
0.001
0.1
~F
-25
85
0
70
°C
Current through CT terminal
Timing resistor, RT
Timing capacitor,
Or
Operating free-air temperature
MIN
electrical characteristics over recommended operating free-air temperature range,
f = 20 kHz (unless otherwise noted)
MAX
Vee
=20 V,
reference section
PARAMETER
SG2524
TEST CONDITIONSt
MIN
Output voltage
TYP:j:·
4.8
SG3524
MAX
MIN
4.6
SG3524Y
TYpt
MAX
MIN
TYP:j:
MAX
UNIT
5
5.2
5
5.4
5
V
Input regulation
VCC =8 Vt040V
10
20
10
30
10
mV
66
dB
20
mV
100
mA
Ripple rejection
f= 120 Hz
66
Output regulation
10= 0 mA to 20mA
20
50
20
50
Output voltage change
with temperature
TA = MIN to MAX
0.3%
1%
0.3%
1%
Short-circuit output
current§
Vref=O
66
100
100
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:I: All typical values, except for temperature coefficients, are at TA = 25°C
§ Standard deviation is a measure of the statistical distribution about the mean as derived from the formula:
N
I
a
=
(Xn -
X)2
n-1
N-1
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-99
SG2524, SG3524
REGULATING PULSE-WIDTH MODULATORS
SLVS0778 - APRIL 1977 - REVISED JULY 1999
electrical characteristics over recommended operating free-air temperature range,
f = 20 kHz (unless otherwise noted)
vee = 20 V,
oscillator section
PARAMETER
fosc
Mosc
tw
SG2524, SG3524
TEST CONDITIONSt
MIN
Oscillator frequency
CT = 0.001 IlF,
Standard deviation of
frequency§
All values of voltage, temperature,
resistance, and capacitance constant.
Frequency change with
voltage
VCC=B Vto40V,
Frequency change with
temperature
TA = MIN to MAX
Output amplitude at OSC
OUT
TA=25°C
Output pulse duration
(width) at OSC OUT
CT=O.OlIlF,
TYI't
Rr=2kll
SG3524Y
MAX
MIN
TYI't
450
450
5%
5%
1%
TA = 25°C
MAX
UNIT
kHz
1%
2%
TA = 25°C
3.5
3.5
V
0.5
0.5
(.IS
.. shown as MIN or MAX, use the appropnate value specified under recommended operating conditions.
t For conditions
:j: All typical values, except for temperature coefficients, are at TA = 25°C
§ Standard deviation is a measure of the statistical distribution about the mean as derived from the formula:
N
L (Xn -
X)2
n-1
(1
N-1
error amplifier section
PARAMETER
TEST
CONDmoNst MIN
SG2524
VIO
Input offset voltage
VIC=2.5V
TYP*
0.5
liB
Input bias current
VIC=2.5V
2
Open-loop voltage
amplification
VICR
Common-mode Input
voltage range
CMMR
Common-mode rejection
ratio
B1
72
TA = 25°C
MAX
5
2
10
2
mV
10
2
10
2
ItA
80
dB
BO
60
TYI't
BO
70
3
0.5
V
70
3
3.B
0.5
:j: All typical values, except for temperature coefficients, are at TA = 25°C
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
dB
MHz
3
3.B
0.5
.. shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t For conditions
8--100
MAX
1.Bto
3.4
70
TA = 25°C
MIN
UNIT
TYI't
1.Bto
3.4
Unity-gain bandwidth
Output swing
SG3524Y
SG3524
MAX MIN
3.B
V
SG2524, SG3524
REGULATING PULSE-WIDTH MODULATORS
SLVS077B - APRIL 1977 - REVISED JULY 1999
electrical characteristics over recommended operating free-air temperature range,
f 20 kHz (unless otherwise noted)
=
Vee = 20 V,
output section
PARAMETER
V(BR)CE
Vsat
TEST CONDITIONSt
SG2534, SG3524
MIN
Collector-emitter breakdown
voltage
TYP*
SG3524Y
MAX
MIN
TYP*
MAX
40
Collector off-state current
VCE = 40V
Collector-emitter saturation
voltage
IC=50mA
IE = -250 J1A
UNIT
V
17
0.01
50
0.01
1
2
1
18
J1A
V
Vo
Emitter output voltage
VC=20V,
18
V
tr
Turn-off voltage rise time
RC=2kn
0.2
0.2
tf
Turn-on voltage fall time
RC=2kCl
0.1
0.1
lIS
lIS
.. shown as MIN or MAX, use the appropriate value specified under recommended operating conditions
.. .
t For conditions
:f: All typical values, except for temperature coefficients, are at TA = 25°C.
comparator section
PARAMETER
TEST CONDmoNst
Maximum duty cycle, each output
VIT
Input threshold voltage at COMP
liB
Inpu1 bias current
SG2534, SG3524
MIN
TYP*
SG3524Y
MAX
MIN
TYP*
MAX
UNIT
45%
Zero duty cycle
Maximum duty cycle
1
1
3.5
3.5
-1
-1
V
J1A
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:f: All typical values, except for temperature coefficients, are at TA = 25°C.
current limiting section
PARAMETER
TEST CONDITIONS
VI
Inpu1 voltage
range
(either input)
V(SENSE)
Sense voltage
atTA=25°C
Temperature
coefficient of
sense voltage
SG3524
SG2524
MIN
TYP*
MAX
MIN
-1
to
1
175
V(IN+) - V(IN-) ~ 50 mV,
V(COMP)=2V
TYP1
SG3524Y
MAX
MIN
TYpt
MAX
-1
to
1
200
225
175
UNIT
V
200
0.2
225
175
0.2
200
225
mV
mV/oC
0.2
..
:f: All typical values, except for temperature coeffiCients, are at TA = 25°C.
total device
PARAMETER
1st
Standby
current
TEST CONDmONS
SG3524Y
SG2524, SG3524
MIN
TYP*
MAX
8
10
MIN
TYP*
MAX
UNIT
cr,
VCC = 40 V, IN-, CURR LlM+,
GND, COMP,
EMIT 1, EMIT 2 grounded, IN + at 2 V,
All other inputs and outputs open
8
.
rnA
:f: All typicel values, except for temperature coefficients, are at TA = 25°C.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS, TEXAS 75265
8-101
SG2524, SG3524
REGULATING PULSE-WIDTH MODULATORS
SLVS077B - APRIL 1977 - REVISED JULY 1999
PARAMETER MEASUREMENT INFORMATION
Vcc =8Vto40V
V'1EF
2kO
T15
Vcc
SG2524 or SG3524
2kO<
10kO
Lo---~
2
10kO
~
1 kO
1
4
SHUTDOWN
IN+
OSCOUT L-(Open)
16
REF OUT
VREF
1
IN-
T
COMP
CURR LlM+
COL 2 13
<
5
CURRLlM-
2kO
~
II
7
6
AT
COL 1
2kO
lW
2 kO
1W
O.lIlF
-=
12
EMIT 2
.!L
EMIT 1
.n....
Outputs
Cy
RT
GND
81
Figure 1. General Test Circuit
VCC
Circuit Under Test
2kO
~t--+--
=VCC
Output
'\",,;,;10::..;%;;...._ _--=.1;:,;0%'J______ ..0 V
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 2. Switching Times
~1ExAs
8-102
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75285
SG2524, SG3524
REGULATING PULSE-WIDTH MODULATORS
SLVS077B-APRIL 1977 - REVISED JULY 1999
TYPICAL CHARACTERISTICS
OPEN-LOOP VOLTAGE AMPLIFICATION
OF ERROR AMPLIFIER
vs
FREQUENCY
III
"I
~
ii.
90
~
70
'0
J
J
i
~
....
8,:
0
"L,=11,~O
50
RL= 300 kO
30
RL=100kO
"L =
kO
~
400 k
:5!
'\
60
40
M
1111111 I I ~ I
VCC=20V
T = 25°C
RL= '':';'
80
~
OSCILLATOR FREQUENCY
vs
TIMING RESISTANCE
I
i
"
20
i'-
100 k
40 k
.........
10 k
~
1'"
~
4k
j
k
~
I......... ~
t'o-..
......
CT= b.031lF
I
10
·CT=O
CT =; 0.0~1 J.I~ ./:;
L CT = d.od3jtF
CT= .01
.....
f'.
1= "T =.0.111
40
t-~~~I~~~V
0
RL Is resistance from COMP to ground
~O~=---------------~----~~
100
1k
10 k
100 k
1M
10M
2
4
7
10
20
Rr - Timing Resistance -
Frequency - Hz
Figure 3
40
70 100
kO
Figure 4
OUTPUT DEAD TIME
vs
TIMING CAPACITANCE
10
4
III
:::I.
I
III
E
1=
]
L
"S
!0
v
~
-I"""
0.4
0.1
0.001
0.004
0.01
0.04
CT - Timing Capacitance -IlF
0.1
Figure 5
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-103
SG2524, SG3524
REGULATING PULSE-WIDTH MODULATORS
SLvsone - APRIL 19n - REVISED JULY 1999
PRINCIPLES OF OPERATIONt
The SG2524 is a fixed-frequency pulse-width-modulation voltage-regulator control circuit. The regulator operates at
a fixed frequency that is programmed by one timing resistor, RT, and one timing capacitor, CT. RT establishes a
constant charging current for CT. This results in a linear voltage ramp at CT, which is fed to the comparator providing
linear control of the output pulse duration (width) by the error amplifier. The SG2524 contains an onboard 5-V
regulator that serves as a reference, as well as supplying the SG2524 internal regulator control circuitry. The internal
reference voltage is divided externally by a resistor ladder network to provide a reference within the common-mode
range of the error amplifier as shown in Figure 6, or an external reference can be used. The output is sensed by a
second resistor divider network and the error signal is amplified. This voltage is then compared to the linear voltage
ramp at CT. The resulting modulated pulse out of the high-gain comparator is then steered to the appropriate output
pass transistor (01 or 02) by the pulse-steering flip-flop, which is synchronously toggled by the oscillator output. The
oscillator output pulse also serves as a blanking pulse to ensure both outputs are never on simultaneously during
the transition times. The duration of the blanking pulse is controlled by the value of Cr. The outputs may be applied
in a push-pull configuration in which their frequency is half that of the base oscillator, or paralleled for single-ended
applications in which the frequency is equal to that of the oscillator. The output ofthe error amplifier shares a common
input to the comparator with the current-limiting and shut-down circuitry and can be overridden by signals from either
of these inputs. This common point also is available extemallyandcan be employed to control the gain of,to
compensate the error amplifier, or to provide additional control to the regulator.
APPLICATION INFORMATIONt
oscillator
The oscillator controls the frequency of the SG2524 and is programmed by RT and CT as shown in Figure 4.
f=~
RTC T
where: RT is in k.Q
CT is in JlF
f is in kHz
Practical values of CT fall between 0.001 and 0.1 JlF. Practical values of RT fall between 1.8 and 100 k.Q. This
results in a frequency range typically from 130 Hz to 722 kHz.
blanking
The output pulse of the oscillator is used as a blanking pulse at the output. This pulse duration is controlled by
the value of CT as shown in Figure 5. If small values of CT are required, the oscillator output pulse duration can
still be maintained by applying a shunt capacitance from OSC OUT to ground.
synchronous operation
When an external clock is desired, a clock pulse of approximately 3 V can be applied directly to the oscillator
output terminal. The impedance to ground at this point is approximately 2 k.Q. In this configuration, RT CT must
be selected for a clock period slightly greater than that of the extemal clock.
t Throughout these discussions, references to the SG2524 apply also to the SG~524.
~TEXAS
8-104
. INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
SG2524, SG3524
REGULATING PULSE-WIDTH MODULATORS
SLVS077B - APRIL 19n - REVISED JULY 1999
APPLICATION INFORMATIONt
synchronous operation (continued)
If two or more SG2524 regulators are operated synchronously, all oscillator output terminals must be tied
together. The oscillator programmed for the minimum clock period is the master from which all the other
SG2524s operate. In this application, the CTRT values of the slaved regulators must be set for a period
approximately 10% longer than that of the master regulator. In addition, CT (master) =2 CT (slave) to ensure
that the master output pulse, which occurs first, has a longer pulse duration and subsequently resets the slave
regulators.
voltage reference
The 5-V internal reference can be employed by use of an external resistor divider network to establish a
reference common-mode voltage range (1.8 V to 3.4 V) within the error amplifiers as shown in Figure 6, or an
external reference can be applied directly to the error amplifier. For operation from a fixed 5-V supply, the internal
reference can be bypassed by applying the input voltage to both the Vee and VREF terminals. In this
configuration, however, the input voltage is limited to a maximum of 6 V.
Skn
.-----4t-- REF OUT
To Positive
Output Voltage
REF OUT
R2
Skn
2.SV
Skn
R1
2.SV
Skn
R1
R2
To Negative
Output Voltage
Vo = 2.SV R1;1 R2
Figure 6. Error-Amplifier Bias Circuits
error amplifier
The error amplifier is a differential-input transconductance amplifier. The output is available for dc gain control
or ac phase compensation. The compensation node (COMP) is a high-impedance node (RL =5 Mil). The gain
of the amplifier is Av =(0.002 il-1)RL and can easily be reduced from a nominal 10,000 by an external shunt
resistance from COMP to ground. Refer to Figure 3 for data.
compensation
COMP, as discussed above, is made available for compensation. Since most output filters introduce one or more
additional poles at frequencies below 200 Hz, which is the pole of the uncompensated amplifier, introduction
of a zero to cancel one 01 the output filter poles is desirable. This can best be accomplished with a series RC
circuit from COMP to ground in the range of 50 kn and 0.001 IlF. Other frequencies can be canceled by use
of the formula 1"" 1/RC.
t Throughout these discussions. references to the SG2S24 apply also to the SG3524.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-1 OS
SG2524, SG3524
REGULATING PULSE-WIDTH MODULATORS
SLVS077B - APRIL 1977 - REVISED JULY 1999
APPLICATION INFORMATIONt
shut-down circuitry
COMP can also be employed to introduce external control of the SG2524. Any circuit that can sink 200 J.LA can
pull the compensation terminal to ground and thus disable the SG2524.
In addition to constant-current limiting, CURR LIM + and CURR LlM- may also be used in transformer-coupled
circuits to sense primary current and shorten an output pulse should transformer saturation occur. CURR LlMmay also be grounded to convert CURR LlM+ into an additional shut-down terminal.
current limiting
A current-limiting sense amplifier is provided in the SG2524. The current-limiting sense amplifier exhibits a
threshold of 200 mV ±25 mV and must be applied in the ground line since the voltage range of the inputs is
limited to 1 V to -1 V. Caution should be taken to ensure the -1 V limit is not exceeded by either input, otherwise
damage to the device may result.
Foldback current limiting can be provided with the network shown in Figure 7. The current-limit schematic is
shown in Figure 8.
EMIT 1
EMIT 2
11
~
Yo
~~
1 (
R1
10(max) = Rs 200 mY
;:: [::;
SG2524
I
R2
CURR LlM-
5
T
CURR LIM+ 4
_ 200 mY
os -
Rs
Rs
rt7
Figure 7. Foldback Current Limiting for Shorted Output Conditions
COMP
Comparator
Error Amplifier
Constant-Current Source
CURR LlM-
CURR LlM+
Figure 8. Current-Limit Schematic
t Throughout these discussions, references to the SG2524 apply also to the SG3524.
~TEXAS
8-106
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
+
Yo R2 )
R1
+
R2
SG2524, SG3524
REGULATING PULSE-WIDTH MODULATORS
SLVS077B-APRIL 1977- REVISED JULY 1999
APPLICATION INFORMATIONt
output circuitry
The SG2524 contains two identical npn transistors, the collectors and emitters of which are uncommitted. Each
transistor has antisaturation circuitry that limits the current through that transistor to a maximum of 100 rnA for
fast response.
general
There are a wide variety of output configurations possible when considering the application of the SG2524 as
a voltage regulator control circuit. They can be segregated into three basic categories:
1. Capacitor-diode-coupled voltage multipliers
2. Inductor-capacitor-implemented single-ended circuits
3. Transformer-coupled circuits
Examples of these categories are shown in Figures 9, 10 and 11 respectively. Detailed diagrams of specific
applications are shown in Figures 12 through 15.
01
Figure 9. Capacitor-Diode-Coupled Voltage-Multiplier Output Stages
t Throughout these discussions, references to the SG2524 apply also to the SG3524.
~TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALlAS, TEXAS 75265
8-107
SG2524, SG3524
REGULATING PULSE-WIDTH MODULATORS
SLVS077B - APRIL 1977 - REVISED JULY 1999
APPLICATION INFORMATIONt
-vo
Figure 10. Single-Ended Inducor Circuit
Vo
PUSH-PULL
FLYBACK
Figure 11. Transformer-Coupled Outputs
t Throughout these discussions, references to the SG2524 apply also to the SG3524.
~1ExAs
8-108
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SG2524, SG3524
REGULATING PULSE·WIDTH MODULATORS
SLVS0778 - APRIL 1977 - REVISED JULY 1999
APPLICATION INFORMATIONt
VCC=15V
15kn
l
kO
O.lI1F
15
!>
1 IN-
5kO
\I
5kn
/I
SG2524
2kO
\1
11
..- -5V
20mA
...
....1
tE-
7CT
CURRLlM+
Ii
~
I ......
+"
4
~ SHUTDOWN CURRLlM- 5
0.0111F
--1.
OSCOUT
COMP
lN916
2Ol1F
COL 2 13
EMIT 2 14
6 RT
II
EMIT 1
COL 1
2 IN+
16
REF OUT
1
lN916
Vee
~, lN916
r!---
:::::i=:: 50 l1F
+
GND
81
rh
Figure 11. Capacitor-Diode Output Circuit
VCC=5V
1N916
J:;: 100 I1F25kO
15V
5kO
5kn
2
5kn
16
2kn
6
7
0.0211F
•
3000
IN-
Vee
2000
20T
11
SG2524 EMIT 1
12
IN+
COl1
13
REF OUT
COL 2
14
EMIT 2
RT
4
CT
CURR LlM+
1 MO
lO.1 I1F
1N916
2N2222
20mA
-15V
10
SHUTDOWN CURR LlM- 5
9
3 OSCOUT
COMP
GND
6200
8
5100
10
Input
Return
Figure 12. Flyback Converter Circuit
tThroughout these discussions, references to the SG2524 apply also to the SG3524.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-109
SG2524, SG3524
REGULATING PULSE-WIDTH MODULATORS
SLVS077B-APRIL 1977 - REVISED JULY 1999
APPLICATION INFORMATIONt
veer 28 V
TIP11S
0.9mH
~--~
5kn
Vee
1
-
SkO
5kn~
0,1 11f
II
IN-
2
6
7
\1
EMIT 1
SG2524 COL 1
IN+
16
3kO
II
0.0211F
'H '
15
Skn
REF OUT
COL 2
AT
EMIT 2
Cy
eURR LlM+
I
11
I
tl ~~J
J--
+
;:: :::::
~
SV
1A
soOI1F
.. 1N3880
3kn
14
4
~ SHUT
--.!
eURR LlM- S
DOWN
9
OSeOUT
eOMP r--GND
;::
J::::: 0.001 11F
8
SOkn
th
0.10
Input Return
Figure 13. Single-Ended LC Circuit
Vee=28V
1S
1 kn
1W
Vee
11
5kn
5kn
1
5kO
HII1F
/I
5kO~
2 kn
r-jII1F
IN-
2 IN+
16
6
EMIT 1
SG2524eOL 1
COL 2
REF OUT
AT
EMIT 2
7 CT
CURR LlM+
1 kn
1W
TIP31 A
TIR101A
/~)
~
r1L-1000
14
4
r:,"] 1 mH
1~
20T
IISTr
STI
20T
~
u"~)
,.--- +
+
11S0011F ;: [:;
I
~
:J
ITIP31A
---.!!!...
SHUT CURR LlM- S
3 DOWN
9
-----"- OSC OUT
COMP -"-- 0 001 F
GND
-::!::'"
11
8
--r-
0.10
20kn
T
+
10011f
fi7
Figure 14. Push-Pull Transformer-Coupled Circuit
tThroughout these discussions, references to the SG2S24 apply also to the SG3524.
~TEXAS
8-110
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5V
SA
TL494
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
D, N, NS, OR PW PACKAGE
(TOP VIEW)
• Complete PWM Power Control Circuitry
• Uncommitted Outputs for 200-mA Sink or
Source Current
• Output Control Selects Single-Ended or
Push-Pull Operation
• Internal Circuitry Prohibits Double Pulse at
Either Output
• Yarlable Dead Time Provides Control Over
Total Range
• Internal Regulator Provides a Stable 5-Y
Reference Supply With 5% Tolerance
• Circuit Architecture Allows Easy
Synchronization
11N+
11NFEEDBACK
21N+
21NREF
OUTPUTCTRL
3
CT
RT
GND
12
11
10
C1
9
VCC
C2
E2
E1
description
The TL494 incorporates all the functions required in the construction of a pulse-width-modulation (PWM) control
circuit on a single chip. Designed primarily for power-supply control, this device offers the flexibility to tailor the
power-supply control circuitry to a specific application.
The TL494 contains two error amplifiers, an on-chip adjustable oscillator, a dead-time control (DTC)
comparator, a pulse-steering control flip-flop, a 5-Y, 5%-precision regulator, and output-control circuits.
The error amplifiers exhibit a common-mode voltage range from --0.3 Y to VCC - 2 V. The dead-time control
comparator has a fixed offset that provides approximately 5% dead time. The on-chip oscillator can be bypassed
by terminating RT to the reference output and providing a sawtooth input to CT, or it can drive the common
circuits in synchronous multiple-rail power supplies.
The uncommitted output transistors provide either common-emitter or emitter-follower output capability. The
TL494 provides for push-pull or single-ended output operation, which can be selected through the
output-control function. The architecture of this device prohibits the possibility of either output being pulsed twice
during push-pull operation.
The TL494C is characterized for operation from O°C to 70°C. The TL4941 is characterized for operation from
-40°C to 85°C.
FUNCTION TABLE
INPUT TO
OUTPUTCTRL
OUTPUT FUNCTION
VI=GND
Single-ended or parallel output
VI =Vref
Normal push-pull operation
~TEXAS
INSTRUMENTS
POST OFFICE eox 855303 • OALLAS. TEXAS 75285
Copyright © 1999. Texas Instruments Incorporated
8-111
TL494
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS074B-JANUARY 1983- REVISED JULY 1999
AVAILABLE OPTIONS
PACKAGED DEVICES
SMALL
OUTLINE
(D)
PLASTIC
DIP
(N)
SMALL
OUTLINE
(NS)
SHRINK
SMALL
OUTLINE
(PW)
CHIP
FORM
(V)
O°C to 70°C
TL494CD
TL494CN
TL494CNS
TL494CPW
TL494Y
-40°C to 85°C
TL4941D
TL494IN
-
-
-
TA
The D, NS, and PW packages are available taped and reeled. Add the suffix R to deVice type (e.g.,
TL494CDR). Chip forms are tested at 25°C.
functional block diagram
OUTPUTCTRL
(see Function Teble)
-f==:J
13
RTJ!6~_ _
CT~5~--~--L-__--J
C1
4
E1
=0.1 V
DTC -"-----l
Error Amplifier 1
11N+ --'1'----_ _-1
>--4JI----t>C1
C2
Comperator
E2
11N-~2=---_ _-I
Pulse-Steering
Flip-Flop
Error Amplifier 2
2IN+--,1:.::6_ _--t
r -_ _ _ _ _ _ _ _ _ _ _....;1=2 VCC
21N---,1:.::5_ _--t
1-_ _ _ _ _ _ _ _ _...:1...;.,4
REF
r-_______~------------~7 GND
---+
FEEDBACK _3_ _ _ _ _ _ _- - ' 0.7 mA
~1ExAs
8-112
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL494
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS074B - JANUARY 1983 - REVISED JULY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
UNIT
TL494
Supply voltage, Vee (see Note 1)
Amplifier input voltage, VI
41
V
VCC+0.3
V
Collector output voltage, Vo
41
V
Collector output current, 10
250
mA
Package thermal impedance, 9JA (see Notes 2 and 3)
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds
o package
73
N package
88
NSpackage
64
°e
PWpackage
108
0, N, or PW package
260
°C
-65 to 150
°C
Storage temperalure range, Tsto
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the deVice. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the network ground terminal.
2. Maximum power dissipation is a function of TJ(max), 6JA, and TAo The maximum allowable power dissipation at any allowable
ambient temperature is Po (TJ(max) - TAl16JA. Operating at the absolute maximum TJ of 150°C can impact reliability.
3. The package thermal impedance is calculated in accordance with JESO 51, except for through-hole packages, which use a trace
length of zero.
=
recommended operating conditIons
TL494
MIN
Supply voltage, VCC
Amplifier Input voltage, V,
7
40
V
VCC-2
V
Collector output current (each transistor)
Current into feedback terminal
Timing capacitor, CT
Timing resistor, RT
ITL494C
Operating free-air temperature, TA
ITL4941
UNIT
------.--
FEEDBACK
Figure 2. Amplifier Characteristics
15V
1""-------,
I
I
680
2W
Each Output
Circuit
I
I
1--I
IL _ _ _ _ _ _ _ .JI
Output
CL=15pF
(See Note A)
TEST CIRCUIT
OUTPUT VOLTAGE WAVEFORM
NOTE A. CL includes probe and jig capacitance.
Figure 3. Common-Emitter Configuration
1""-------,
I
I
15V
Each Output
Circuit
I
I
1--I
----f--......- - + - Output
IL _ _ _ _ _ _ _ .JI
680
I
I
I
2W
CL=15pF
(See Note A)
~tf
TEST CIRCUIT
OUTPUT VOLTAGE WAVEFORM
NOTE A. CL includes probe and jig capacitance.
Figure 4. Emitter-Follower Configuration
~TEXAS
8--118
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
TL494
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS0748 - JANUARY 1983 - REVISED JULY 1999
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY AND
FREQUENCY VARIATIONt
N
~ 100k
i
Vee=15V
TA = 25°C
c
40k
~
~
4k
i
1k
~
...
I
I
...
0.0111F
.'
0.111F
400
100
40
I I II
0.00111F
0%= ~
1
1
I
:7
10k ~ ~ -1%
!I
r
(
--2ot.
.-
Oft = 1%
==
-
i
Cr=1I1F
III
1 1111111
10
1k
4k
10k
40 k
100 k
400 k
1M
n
RT - Timing Resistance -
t Frequency variation (AI) is the change in oscillator frequency that occurs over the full temperature range.
Figure 5
AMPLIFIER VOLTAGE AMPLIFICATION
vs
100
f--III
90
I
r--...
'\.
"CI
I
c
80
i
70
"ii
60
&
!
50
~
~
~
40
~
30
CC
20
~
E
Vee = 15V
I\.
'\.
_
I\.
~
"
~
I
cc
tNO=3V
TA=25°e
10
\.
~
10
100
1k
10 k
100 k
1M
f - Frequency - Hz
Figure 6
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-119
8-120
TL497A
SWITCHING VOLTAGE REGULATORS
•
•
•
•
•
•
•
•
D, N, OR PW PACKAGE
(TOP VIEW)
High Efficiency ••• 60% or Greater
Output Current ... 500 mA
Input Current Limit Protection
TTL-Compatible Inhibit
Adjustable Output Voltage
Input Regulation .•. 0.2% Typ
Output Regulation ••• 0.4% Typ
Soft Start-Up Capability
description
COMP INPUT
INHIBIT
FREQ CONTROL
SUBSTRATE
GND
CATHODE
ANODE
14
13
12
11
10
9
B
VCC
CUR LIM SENS
BASE DRIVEt
BASEt
COL OUT
NC
EMIT OUT
NC - No internal connection
t BASE (11) and BASE DRIVE (12) are used for device testing
The TL497A incorporates all the active functions
only. They normally are not used in circuit applications of the
device.
required in the construction of switching voltage
regulators. It can also be used as the control
element to drive external components for high-power-output applications. The TL497A was designed for ease
of use in step-up, step-down, or voltage-inversion applications requiring high efficiency.
The TL497A is a fixed-on-time variable-frequency switching-voltage-regulator control circuit. The switch-on
time is programmed by a Single external capaCitor connected between FREQ CONTROL and GND. This
capacitor, CT, is charged by an internal constant-current generator to a predetermined threshold. The charging
current and the threshold vary proportionally with VCC' Thus, the switch-on time remains constant over the
specified range of input voltage (4.5 V to 12 V). Typical on times for various values of CT are as follows:
TIMING CAPACITOR, Cr (pF)
ONTIME{JJ.s)
The output voltage is controlled by an external resistor ladder network (R1 and R2 in Figures 1, 2, and 3) that
provides a feedback voltage to the comparator input. This feedback voltage is compared to the reference
voltage of 1.2 V (relative to SUBSTRATE) by the high-gain comparator. When the output voltage decays below
the value required to maintain 1.2 V at the comparator input, the comparator enables the oscillator circuit, which
charges and discharges CT as described above. The internal pass transistor is driven on during the charging
of CT. The internal transistor can be used directly for switching currents up to 500 mAo Its collector and emitter
are uncommitted, and it is current driven to allow operation from the positive supply voltage or ground. An
internal Schottky diode matched to the current characteristics of the internal transistor also is available for
blocking or commutating purposes. The TL497A also has on-Chip current-limit circuitry that senses the peak
currents in the switching regulator and protects the inductor against saturation and the pass transistor against
overstress. The current limit is adjustable and is programmed by a single sense resistor, RCL, connected
between Vcc and CUR LIM SENS. The current-limit circuitry is activated when 0.7 V is developed across RCL.
External gating is provided by the INHIBIT input. When the INHIBIT input is high, the output is turned off.
Simplicity of design is a primary feature of the TL497A. With only six external components (three resistors, two
capacitors, and one inductor), the TL497A operates in numerous voltage-conversion applications (step-up,
step-down, invert) with as much as 85% of the source power delivered to the load. The TL497A replaces the
TL497 in all applications.
The TL497AC is characterized for operation from O°C to 70°C. The TL497AI is characterized for operation from
-40°C to 85°C.
~TEXAS
Copyright © 1999, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-121
TL497A
SWITCHING VOLTAGE REGULATORS
SLVS009D - JUNE 1976 - REVISED JULY 1999
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL-OUTLINE
(D)
PLASTIC DIP
(N)
SHRINK
SMALL·OUTLINE
(PW)
TL497ACPW
CHIP
FORM
(V)
TL497ACD
TL497ACN
TL497AY
O°C to 70°C
-40°C to 85°C
TL497AID
TL497AIN
The D and PW packages are only taped and reeled. Add the SuffiX R to the deVice type (e.g.,
TL497ACPWR). Chip forms are tested at 25°C.
-
-
functional block diagram
BASEt
~1~1
____________________________________~
BASE DRIVEt _1_2_~;:::;::==:;-
______I
CUR LIM SENS ...;1:.::3_ _-1
FREQ CONTROL ..::3'--_ _ _ _ _ _ _ _ _ _-1
Oscillator
INHIBIT
COMPINPUT
10 COL OUT
SUBSTRATE
CATHODE ~
EMIT OUT
___________~~__--------------------------~7 ANODE
t BASE and BASE DRIVE are used for device testing only. They normally are not used in circuit applications of the device.
~TEXAS
8-122
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL497A
SWITCHING VOLTAGE REGULATORS
SLVSOO9D - JUNE 1976 - REVISED JULY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supplyvoltage,Vcc(seeNote1) ........................................................... 15V
Output voltage, Vo ........................................................................ 35 V
Input voltage, V,(COMP INPUT) ............................................................. 5 V
Input voltage, V,(INHIBIT) ................................................................... 5 V
Diode reverse voltage ..................................................................... 35 V
Power switch current .................................................................... 750 mA
Diode forward current ................................................................... 750 mA
Package thermal impedance, 9JA (see Notes 2 and 3): D package ............................ 86°CIW
N package ........................... 101°CIW
PW package. . . . . . . . . . . . . . . . . . . . . . . . .. 113°CIW
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds ............................... 260°C
Storage temperature range, Tstg .................................................. --65°C to 150°C
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values except diode voltages are with respect to network ground terminal.
2. Maximum power dissipation is a function of TJ(max), 8JA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is Po = (TJ(max) - TA)teJA. Operating at the absolute maximum TJ of 150·e can impact reliability.
3. The package thermal impedance is calculated in accordance with JESD 51 , except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
Supply voltage, Vee
High-level input voltage, VIH
Low-level Input voltage, VIL
Output voltage
INHIBIT pin
INHIBIT pin
Step-up configuration (see Figure 1)
Step-down configuration (see Figure 2)
Inverting regulator (see Figure 3)
MIN
MAX
4.5
2.5
12
VI+2
Vref
-Vref
Power switch current
Diode forward current
0.8
30
VI-1
-25
500
500
lTL497Ae
ITL497AI
Operating free-air temperature range, TA
0
-40
70
85
UNIT
V
V
V
V
mA
mA
·e
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-123
TL497A
SWITCHING VOLTAGE REGULATORS
SLVSOO9D - JUNE 1976 - REVISED JULY 1999
electrical characteristics over recommended operating conditions, Vee = 6 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TL497AI
TYH
MAX
MIN
TYH
MAX
UNIT
High-level Input current, INHIBIT
VI(I)=5V
Full range
0.8
1.5
0.8
1.5
mA
Low-level input current, INHIBIT
VI(I)=OV
Full range
5
10
5
20
IIA
Comparator reference voltage
VI = 4.5 V to 6 V
Full range
1.2
1.32
1.2
1.26
V
Comparator Input bias current
VI=6V
Full range
40
100
40
100
IIA
0.13
0.2
0.13
0.2
110= 100mA
Switch on-state voltage
VI=4.5V
I 10=500 mA
Switch off-state current
VI = 4.5 V,
VO=30V
Sense voltage, CUR LIM SENS
VI=6V
Diode forward voltage
Diode reverse voltage
1.08
25°C
0.85
Full range
25°C
10
1
50
Full range
10
200
0.45
25°C
1.14
1
0.75
50
500
0.45
1
0.75
0.85
Full range
10=100mA
Full range
0.9
1
0.9
1.1
10=500mA
Full range
1.33
1.55
1.33
1.75
10 = 500 IIA
Full range
10 = 200 IIA
Full range
30
11
25°C
14
11
15
25°C
OIl-state supply current
6
Full range
IIA
V
V
V
30
Full range
V
0.95
10=10mA
On-state supply current
t
TL497AC
TAt
14
16
6
9
10
9
11
mA
mA
Full range IS O°C to 70°C for the TL497AC and -40°C to 85°C for the TL497 AI.
i All typical values are at TA = 25°C.
electrical characteristics over recommended operating conditions, Vee =6 V, TA
otherwise noted)
PARAMETER
TEST CONDITIONS
=25°C (unless
TL497AY
MIN
TYP
MAX
UNIT
High-level input current, INHIBIT
VI(I)=5V
0.8
rnA
Low-level input current, INHIBIT
VI(I)=OV
5
IIA
Comparator reference voltage
VI = 4.5 V to 6 V
1.2
V
Comparator input bias current
VI=6V
40
IIA
Switch on-state voltage
VI =4.5V,
10=100mA
Switch off-state current
VI =4.5V,
VO=3OV
10=10mA
Diode forward voltage
0.13
10
V
IIA
0.75
10= 100 mA
0.9
'0=500mA
1.33
V
On-state supply current
11
mA
Off-state supply current
6
mA
~TEXAS
INSTRUMENTS
8-124
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL497A
SWITCHING VOLTAGE REGULATORS
SLVS009D-JUNE 1976- REVISED JULY 1999
APPLICATION INFORMATION
RCL
......
L
Vo
~
T
~ r--
.~
14 13
8
10
R1
TL497A
1
2
3
4
;:
5
6
I
CT
7
DESIGN EQUATIONS
I(PK) = 2 lOmax
•
VI
L(I'H) = -I-ton (fIB)
(PI<)
R2=1.211n
Choose L (50 to 500 I1H), calculate
ton (25 to 150!1S)
;::::::
I
[:~]
•
F: Co
BASIC CONFIGURATION
(Peak Switching Current = I(PK) c 500 mAl
RCL
L
Co
TL497A
•
R1
•
R
0.5 V
CL = I(PK)
•
Co (I'F) = 10n(fIB)
=
(Vo - 1.2 V) kQ
[~ I(PK) + 10]
V.
(PK)
npple
R2 = 1.2 lin
-::-
EXTENDED POWER CONFIGURATION
(using external transistor)
Figure 1. Positive Regulator, Step-Up Configurations
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-125
TL497A
SWITCHING VOLTAGE REGULATORS
SLVSOO9D - JUNE 1976 - REVISED JULY 1999
APPLICATION INFORMATION
L
RCL
rv
Vo
T
14
13
DESIGN EQUATIONS
8
10
R1
TL497A
1
3
2
;:: [::;
4
6
5
7
Choose L (50 to 500 I1H), calculate
ton (10 to 150 111)
;:: r:.CT
•
R1 = (VO - 1.2 V) kQ
L
Vo •
rv'VV">
A¥13
4
CT
_ 0.5 V
I(PK)
• Co ("F) = ton(~)
10
3
R
CL -
~
8
R1
TL497A
2
L("H) = -I--ton(~)
(PK)
R2 = 1.2 kn
RCL
1
•
VI - Vo
BASIC CONFIGURATION
(Peak Switching Current = I(PK) < 500 mAl
14
I(PK) = 2 lOmax
Co
I
I
•
;:;:;:; Co
5
6
7
R2=1.2kQ
I
;:;:;:;
EXTENDED POWER CONFIGURATION
(using external transistor)
Figure 2. Positive Regulator, Step-Down Configurations
~TEXAS
8-126
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
[~ I(PK) + 10]
V.
(PK)
ripple
TL497A
SWITCHING VOLTAGE REGULATORS
SLVSOO9D - JUNE 1976 - REVISED JULY 1999
APPLICATION INFORMATION
L
RCL
....A
DESIGN EQUATIONS
r:---r
-=l:-
I
14 13
8
10
R1
~~ t
;:::r: Co
TL497A
1
2
3
4
R2
5
=1.2kn
I
Vo
;::: :::::Cy
Choose L (50 to SOO I1H), calculate
ton (10 to 150118)
BASIC CONFIGURATION
(Peak Switching Current I(PK) < SOO mAl
=
•
R
L
....... A
14
'A~
13
8
•
R1
~~ t
2
3
4
I(PK)
Co (I'F) = lon(J1S)
[
~ 1(p1<) + 10
]
V.
(PK)
npple
o
TL497A
1
- 0.5 V
CL -
J.
10
(lvol- 1.2 v) kQ
R1 =
;:::::::: C
5
R2
=1.2kn
~
I
Vo
;::: f'Cy
EXTENDED POWER CONFIGURATION
(using external transistor)
t
Use external catch diode, e.g., 1N4001, when building an inverting supply with the TL497A.
Figure 3. Inverting Applications
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
8-127
TL497A
SWITCHING VOLTAGE REGULATORS
SLVS009D - JUNE 1976 - REVISED JULY 1999
APPLICATION INFORMATION
Switching
Circuit
=})
Vo
I
1\
Control
\
TL497A
5
EXTENDED INPUT CONFIGURATION WITHOUT CURRENT LIMIT
Switching
Circuit - -
Vo
DESIGN EQUATIONS
•
1--t_ _ _ _V..
re""g_ _l ' \ 0 rnA
,,----'(\1..._-"""'\\
Control
TL497A
5
CURRENT LIMIT FOR EXTENDED INPUT CONFIGURATION
Figure 4. Extended Input Voltage Range (VI> 12 V)
~TEXAS
8-128
=
CL
'---.,....._...
R1
R
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
v
BE(Q1)
Ilimit (PK)
+~
•
R1
•
R2 = (Vreg - 1) 10 kn
IB(Q2)
TL499A
WIDE·RANGE POWER·SUPPLY CONTROLLERS
SLVS029D - JANUARY 1984 - REVISED JULY 1999
• Internal Series-Pass and Step-Up Switching
Regulator
• Output Adjustable From 2.9 V to 30 V
• 1-V to 10-V Input for Switching Regulator
• 4.5-V to 32-V Input for Series Regulator
• Externally Controlled Switching Current
• No External Rectifier Required
PPACKAGE
(TOP VIEW)
SERIES IN1 [ ] 8
REF 2
7
SW REG IN2 3
6
SW CURRENT CTRL 4
5
OUTPUT
GND (PWR)
SW IN
GND
description
The TL499A is an integrated circuit designed to provide a wide range of adjustable regulated supply voltages.
The regulated output voltage can be varied from 2.9 V to 30 V by adjusting two external resistors. When the
TL499A is ac-coupled to line power through a step-down transformer, it operates as a series dc voltage regulator
to maintain the regulated output voltage. With the addition of a battery from 1.1 V to 10 V, an inductor, a filter
capacitor, and two resistors, the TL499A operates as a step-up switching regulator during an ac-line failure.
The adjustable regulated output voltage makes the TL499A useful for a wide range of applications. Providing
backup power during an ac-line failure makes the TL499A extremely useful in microprocessor memory
applications.
The TL499AC is designed for operation from -20°C to 85°C.
AVAILABLE OPTIONS
TA
PLASTIC DIP
(P)
CHIP FORM
(V)
-20°C to 85°C
TL499ACP
TL499AY
Chip forms are tested at 25°C.
~lExAs
Copyright © 1999, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-129
TL499A
WIDE-RANGE POWER-SUPPLY CONTROLLERS
SLVS029D - JANUARY 1984 - REVISED JULY 1999
functional block diagram
SWIN
3
6
Blocking Diode
8
....- - e - - - - -
.---*---e--~.-
7
4
Current Sense
OUTPUT
GND(PWR)
SW CURRENT CTRL
+
2
REF
SERIESIN1
~1EXAS
8-130
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL499A
WIDE-RANGE POWER-SUPPLY CONTROLLERS
SLVS029D-JANUARY 1984- REVISED JULY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Output voltage, Vo (see Note 1) ............................................................ 35 V
Input voltage, series regulator, Vii .......................................................... 35 V
Input voltage, switching regulator, V,2 ....................................................... 10 V
Blocking-diode reverse voltage ............................................................. 35 V
Blocking-diode forward current .............................................................. 1 A
Power switch current (SW IN) ............................................................... 1 A
.................................... 127°CIW
Package thermal impedance, 9JA (see Notes 2 and 3):
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network ground terminal.
2. Maximum power diSSipation is a function of TJ(max), 9JA, and TA' The maximum allowable power dissipation at any allowable
ambient temperature is Po = (TJ(max) - TA)/9JA. Operating at the absolute maximum TJ of 150°C can impact reliability.
3. The package thermal impedance is calculated in accordance with JESO 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
MIN
NOM
MAX
UNIT
Output voltage, Vo
2.9
30
V
Input vottage, V,1 (SERIES IN1)
4.5
32
V
V
Input voltage, V,2 (SW REG IN2)
1.1
10
Output-ta-input differential voltage, switching regulator, Vo - V,2 (see Note 4)
1.2
28.9
V
100
rnA
500
rnA
Continuous output current, 10
Power swHch current (at SW IN)
Current-limiting resistor, RCL
150
1000
0
Fitter capacitor
100
470
IlF
50
150
IlH
-20
85
°C
0.1
Pass capacitor
Inductor, L (dcr S 0.1 0)
Operating free-air temperature, TA
IlF
NOTE 4: When operating temperature range is TA S70°C, minimum VO- V,2 is;;, 1.2 V. When operating temperature range is TA s85°C, minimum
VO- V,2 is;;, 1.9 V.
:II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8--131
TL499A
WIDE-RANGE POWER-SUPPLY CONTROLLERS
SLVS029D - JANUARY 1984 - REVISED JULY 1999
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TL499AC
TEST CONDITIONS
MIN
Voltage deviation (see Note 5)
Dropout voltage
Switching regulator
Series regulator
Reference voltage (internal)
20
Vll = 15 V,
10=50mA
1.8
VI2=5V,
VO=3V,
1.9
1.2
10= 1 rnA
10=1 rnA to 50 rnA
VO=12V,
V12= 1.5V,
VO=15V,
RCL= 1500,
TA = 25°C
15
VI2=6V,
VO=30V,
RCL= 1500,
TA = 25°C
65
Switching regulator
VI2=3V,
VO=9V,
TA = 25°C
Series regulator
Vll=15V,
VO=9V,
RE2 =4.7 kQ
RCL = 1500.
TA=25°C
UNIT
mVN
V
V
1.26
1.32
5
10
mV/"C
10
30
mV
10
rnA
Series regulator
Standby current
30
1.2
V12= 1.1 V,
Switching regulator
Output current
(see Figure 1)
MAX
TA = -20°C to 70°C
Reference voltage change with temperature
Output regulation (of reference voltage)
TYP
100
15
80
IIA
0.8
1.2
rnA
NOTE 5: Voltage deviation IS the output voltage differences that occurs In a change from senes regulation to switching regulation:
Voltage deviation = Vo(serles regulation) - Vo(swltching regulation)
electrical characteristics over recommended operating conditions, TA = 25°C (unless otherwise
noted)
PARAMETER
TL499AY
TEST CONDITIONS
MIN
Voltage deviation (see Note 5)
Dropout voltage
Switching regulator
Series regulator
Reference voltage (internal)
20
Output current
(see Figure 1)
TA = -20°C to 85°C
1.9
Vll=15V,
IO=50mA
1.8
VI2=5V,
VO=3V,
10=1 rnA
1.2
10=1 rnA to 50 rnA
VO=12V,
VI2 = 1.5 V,
VO=15V,
RCL= 1500
15
VI2=6V,
Vo = 30 V,
RCL=1500
65
Switching regulator
VI2=3V,
VO=9V
Series regulator
Vll =15V,
VO=9V,
RCL=1500
mVN
V
1.32
5
10
mVN
10
30
mVN
V
10
rnA
100
RE2 =4.7 kQ
15
80
IIA
0.8
1.2
rnA
NOTE 5: Voltage deviation is the output voltage differences that occurs In a change from series regulation to switching regulation:
Voltage deviation = Vo!series regulation) - Vo(swltching regulation)
~TEXAS
INSTRUMENTS
8-132
UNIT
1.26
Series regulator
Standby current
30
1.2
VI2=1.lV,
Switching regulator
MAX
TA = -20°C to 70°C
Reference voltage change with temperature
Output regulation (of reference voltage)
TYP
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL499A
WIDE-RANGE POWER-SUPPLY CONTROLLERS
SLVS029D - JANUARY 1984 - REVISED JULY 1999
APPLICATION INFORMATION
rvvv-.
1
1
SERIESINl
.-:!.
3
3
SWREGIN2
4
TL499A
SERIESINl
REF
OUTPUT
SW REG IN2
SWCURRENT
CTRL
7
SW IN
rs
GND
~
GND (PWR)
8
8
r----<
I
+
Cp=O.OlI1F ;::
r:
REl
ooa
~.
OUTPUT
470l1F
RE2 =4.7 kn
-
~
Figure 1. TL499A Basic Configuration
Table 1. Maximum Output Current vs Input and Output Voltages
for Step-Up Switching Regulator With RCL = 150 n
OUTPUT
VOLTAGE
SWITCHING REGULATOR INPUT VOLTAGE (SW REG IN2)
(V)
1.1
1.2
I
1.3
1.5
(V)
1.7
2
2.5
3
5
6
65
90
50
80
100
9
OUTPUT CURRENT
(mA)
30
25
20
15
15
20
20
25
30
80
100
100
30
45
55
100
100
100
100
12
10
15
20
25
30
40
55
70
100
100
10
15
20
25
30
35
45
65
80
100
100
40
50
70
90
100
100
55
75
95
100
9
20
25
25
6
30
35
40
35
45
5
35
35
40
45
55
70
85
100
100
Circuit of Figure 1 except:
4.5
45
50
60
75
95
100
lOOt
RCL=150a
3
55
65t
75t
95t
lOOt
CF= 33O I1F
2.9
60t
70t
75t
lOOt
lOOt
Cp=O.lI1F
..
t The difference between the output and Inpu1 voltage for these combinations IS greater than the minimum
output-to·input differential voltage specification at 70°C (1.2 V). bu1less than the minimum at 85°C (1.9 V).
-!I
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-133
TL499A
WIDE-RANGE POWER-SUPPLY CONTROLLERS
SLVS029D-JANUARY 1984- REVISED JULY 1999
APPLICATION INFORMATION
Table 2. Maximum Output Current vs Input and Output Voltages
for Step-Up Switching Regulator With RCL 200 n
=
SWITCHING REGULATOR INPUT VOLTAGE (SW REG IN2)
OUTPUT
VOLTAGE
M
1.1
I
1.2
1.3
1.5
(V)
1.7
2
2.5
3
I
5
6
9
50
100
50
70
100
OUTPUT CURRENT
(rnA)
30
25
20
15
15
25
30
70
90
100
10
15
25
35
45
90
100
100
100
12
10
10
15
20
25
35
45
60
100
100
10
15
20
20
25
30
40
55
70
100
100
100
9
20
20
25
30
35
45
60
80
6
25
30
35
45
50
65
90
100
5
30
35
60
75
100
100
Circuit of Figure 1 except:
35
40
40
45
55
4.5
55
65
85
100
100l
RCL= 200 Q
3
50
55t
65t
80t
90t
CF= 33O I1F
2.9
50t
60t
65t
85t
tOot
Cp= O.II1F
..
t The difference between the output and Input voltage for these combinations is greater than the minimum
output·ta-input differential voltage specification at 70°C (1.2 V), but less than the minimum at 85°C (1.9 V).
Table 3. Maximum Output Current vs Input and Output Voltages
for Step-Up Switching Regulator With RCL 300 n
=
OUTPUT
VOLTAGE
SWITCHING REGULATOR INPUT VOLTAGE (SW REG IN2)
(V)
1.1
I
1.2
1.3
1.5
(V)
1.7
2
2.5
3
5
6
40
70
40
55
100
9
OUTPUT CURRENT
(rnA)
30
25
10
15
20
55
70
100
10
10
20
30
35
75
95
100
100
20
15
12
10
10
10
15
20
25
35
45
95
100
10
15
15
15
20
25
30
45
55
100
100
100
100
9
15
15
20
25
30
35
50
60
6
25
25
30
35
45
55
70
90
5
30
30
35
45
50
65
85
100
Circuit of Figure 1 except:
4.5
30
35
40
45
55
70
95
lool
RCL=300Q
3
45
50t
55t
70t
90t
CF= 330 I1F
2.9
45t
50t
60t
75t
95t
Cp=O.II1F
..
t The difference between the output and Input voltage for these combinations IS greater than the minimum
output·to·input differential voltage specification at 70°C (1.2 V), but less than the minimum at 85°C (1.9 V).
~TEXAS
8-134
INSTRUMENTS
POST OFFICE eox 655303 • DALlAS. TEXAS 75265
TL499A
WIDE-RANGE POWER-SUPPLY CONTROLLERS
SLVS029D - JANUARY 1984 - REVISED JULY 1999
APPLICATION INFORMATION
Table 4. Maximum Output Current vs Input and Output Voltages
for Step-Up Switching Regulator With RCL 510 Q
=
OUTPUT
VOLTAGE
(V)
SWITCHING REGULATOR INPUT VOLTAGE (SW REG IN2)
(V)
1.1
1.2
1.3
1.5
1.7
2
2.51
3
6
5
9
OUTPUT CURRENT
(mA)
30
25
25
20
15
12
10
10
15
20
30
50
40
75
40
55
90
55
70
100
100
10
15
25
35
65
80
20
25
30
40
70
85
75
100
9
10
10
10
15
20
25
35
45
6
15
20
20
25
30
35
50
60
5
4.5
20
20
25
30
35
45
55
70
Circuit of Figure 1 except:
20
25
30
35
40
50
65
90T
RCL=510Q
3
35
35t
40t
50t
75t
CF= 33O ILF
2.9
35t
35t
40t
55t
sot
Cp=0.1ILF
t The difference between the output and input voltage for these combinations is greater than the minimum
output·to·input differential voltage specification at 70°C (1.2 V). but less than the minimum at 85°C (1.9 V).
Table 5. Maximum Output Current vs Input and Output Voltages
for Step-Up SWitching Regulator With RCL = 1 kQ
OUTPUT
VOLTAGE
(V)
SWITCHING REGULATOR INPUT VOLTAGE (SW REG IN2)
(V)
1.1
1.2
1.3
1.5
1.7
2
2.5
3
5
6
9
OUTPUT CURRENT
(mA)
30
35
25
35
20
35
60
45
65
85
15
10
12
10
10
10
20
40
45
15
25
40
55
45
60
10
10
15
25
30
10
15
20
20
30
35
9
6
30
5
10
10
15
20
20
25
35
40
4.5
15
15
15
20
25
30
40
45t
3
20
25t
25t
30t
35t
CF=330ILF
2.9
20t
25t
25t
30t
45t
Cp=0.1ILF
50
Circuit of Figure 1 except:
RCL= 1 kn
t The difference between the output and input voltage for these combinations is greater than the minimum
output-to-input differential voltage specification at 70°C (1.2 V). but less than the minimum at 85°C (1.9 V).
~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-135
8-136
TL594
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
• Complete PWM Power Control Circuitry
• Uncommitted Outputs for 200-mA Sink or
Source Current
• Output Control Selects Single-Ended or
Push-Pull Operation
• Internal Circuitry Prohibits Double Pulse at
Either Output
• Yariable Dead Time Provides Control Over
Total Range
• Internal Regulator Provides a Stable S-Y
Reference Supply Trimmed to 1%
• Circuit Architecture Allows Easy
Synchronization
• Undervoltage Lockout for Low Yee
Conditions
D OR N PACKAGE
(TOP VIEW)
11N+
11N-
FEEDBACK
21N+
21NREF
OUTPUTCTRL
VCC
C2
GND
C1
E2
description
The TL594 incorporates all the functions required in the construction of a pulse-width-modulation control circuit
on a single chip. Designed primarily for power-supply control, these devices offer the systems engineer the
flexibility to tailor the power-supply control circuitry to a specific application.
The TL594 contains two error amplifiers, an on-chip adjustable oscillator, a dead-time control (DTC)
comparator, a pulse-steering control flip-flop, a 5-V regulator with a precision of 1%, an undervoltage lockout
control circuit, and output control circuitry.
The error amplifiers exhibit a common-mode voltage range from -0.3 V to Vee -2 Y. The DTC comparator has
a fixed offset that provides approximately 5% dead time. The on-chip oscillator can be bypassed by terminating
RT to the reference output and providing a sawtooth input to CT, or it can be used to drive the common circuitry
in synchronous multiple-rail power supplies.
The uncommitted output transistors provide either common-emitter or emitter-follower output capability. Each
device provides for push-pull or single-ended output operation, with selection by means of the output-control
function. The architecture of these devices prohibits the possibility of either output being pulsed twice during
push-pull operation. The undervoltage lockout control circuit locks the outputs off until the internal circuitry is
operational.
The TL594C is characterized for operation from O°C to 70°C. The TL5941 is characterized for operation from
-40°C to 85°C.
FUNCTION TABLE
INPUT
OUTPUT
CTRL
OUTPUT FUNCTION
VI =-{)
Single-ended or parallel output
VI=Vref
Normal push-pull operation
~:'~I:.==-~~r::!..:::g,::.:'.n.~
aIandanI warranty. Producllon proceoolng dOlI not ....1IIII11y includo
....Ing or all paramoIII8.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
8-137
TL594
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS052C-APRIL 1988-REVISEDJ.ULY1999
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE
(D)
PLASTIC DIP
(N)
O·Cto 70·C
TL594CD
TL594CN
-40·C to 85·C
TL5941D
TL594IN
CHIP FORM
(Y)
TL594Y
The 0 package IS available taped and reeled. Add OR" suffix to device type (e.g.,
TL594CDR). Chip forms are tested at 25·C.
functional block diagram
OUTPUTCTRL
(see Function Table)
13
RT
~6---r::;;;:::::1
r
CT .=.5_
-L_ _.J
C1
E1
=0.1 V
DTC.!..t
C2
Error Amplifier 1
E2
Pulse-Steerlng
Flip-Flop
.--_______+-____..:.:12:;...
Error Ampllfler 2
Vee
Undervoltage
Lockout
Control
L -_ _ _ _ _
~----~1~4 REF
7
FEEDBACK 3"--_ _ _ _ _"*-_-< r - - - - - - - " * - - - - - - - - - - - - - - G N
D
---+
0.7mA
~TEXAS
8-138
INSTRUMENTS
POST OFFICE eox 656303 • DALlAS, TEXAS 75265
TL594
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS052C-APRIL 1988- REVISED JULY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, VCC (see Note 1)
Amplifier Input voltage
Collector output voltage
Collector output current
I
Package thermal impedance, 9JA (see Notes 2 and 3)
0 package
I Npackage
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds
Storage temperature range, Tsta
TL594X
41
VCC+0.3
41
250
73
88
260
-65 to 150
UNIT
V
V
V
mA
°c
°C
°C
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the network ground terminal.
2. Maximum power dissipation is a function of TJ(max), 6JA, and TA. The maximum allowable power diSSipation at any allowable
ambient temperature is Po = (TJ(max) - TA)/6JA. Operating at the absolute maximum TJ of 150°C can impact reliability.
3. The package thermal impedance is calculated in accordance with JESO 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
MIN
7
-0.3
Supply voltage, VCC
Amplifier Input voltage, VI
Collector output voltage, Vo
Collector output current (each transistor)
Current into feedback terminal
Timing capecitor, CT
Timing resistor, AT
Oscillator frequency, fose
I TL594C
Operetlng free-air temperature, TA
I TL5941
0.47
1.8
1
0
-40
MAX
40
VCC-2
40
200
0.3
10000
500
300
70
85
UNIT
V
V
V
mA
mA
nF
kn
kHz
°C
°C
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
8-139
TL594
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS052C - APRIL 1988 - REVISED JULY 1999
electrical characteristics over recommended operating conditions, VCC
(unless otherwise noted)
=15 V,
reference section
TL594C, TL5941
PARAMETER
TEST CONDInONSt
MIN
TYP*
MAX
4.95
UNIT
Output voltage (REF)
10=1 mA,
TA=25°C
5
5.05
Input regulation
VCC= 7Vt040V,
TA=25°C
2
25
Output regulation
10=1 to 10 rnA,
TA=25°C
14
35
mV
Output-voltage change with temperature
ATA = MIN to MAX
2
10
mVN
Short-circuit output current§
Vref=O
35
50
mA
10
V
mV
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:I: All typical values except for parameter changes with temperature are at TA = 25°C.
§ Duration of the short clrcuH should not exceed one second.
amplifier section (see Figure 1)
PARAMETER
TL594C, TL5941
TEST CONDITIONS
MIN
TYH
MAX
UNIT
Input offset voltage, error amplifier
FEEDBACK = 2.5 V
2
10
mV
Input offset current
FEEDBACK = 2.5 V
25
250
nA
Input bias current
FEEDBACK = 2.5 V
0.2
1
IIA
0.3
to
Vcc-2
Common-mode input voltage range,
error amplifier
VCC=7Vt040V
Open-loop vottage amplification, error
amplifier
AVO=3V,
RL=2 kn,
Unity-gain bandwidth
Vo = 0.5 V to 3.5 V,
RL=2kO
Common-mode rejection ratio, error
amplifier
Vo = 0.5 Vto 3.5 V
70
V
95
dB
800
kHz
VCC=4OV,
TA=25°C
65
80
dB
Output sink current, FEEDBACK
VID = -15 mV to -5 V,
FEEDBACK = 0.5 V
0.3
0.7
rnA
Output source current, FEEDBACK
VID=15mVt05V,
FEEDBACK = 3.5 V
-2
mA
:I: All typical values except for perameter changes With temperature are at TA = 25°C.
oscillator section, CT
=O.01IlF, RT =12 kn (see Figure 2)
PARAMETER
TL594C, TL5941
TEST CONDITIONst
MIN
TYP*
Frequency
Standard deviation of frequencyll
All values of VCC, CT, RT, and TA constant
Frequency change with voltage
VCC = 7Vt040V,
Frequency change with temperature#
ATA = MIN to MAX
TA=25°C
.. shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t For conditions
:I: All typical values except for parameter changes with temperature are at TA = 25°C.
11 Standard deviation is a measure of the statistical distribution about the mean as derived from the formula:
N
I
a
=
(X n - X)2
n=1
N
# Temperature coefficient of timing capecttor and timing resistor not taken into account.
~1ExAs
8-140
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MAX
UNIT
10
kHz
100
HzlkHz
1
HzlkHz
50
HzlkHz
TL594
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS052C - APRIL 1988 - REVISED JULY 1999
electrical characteristics over recommended operating free-air temperature range,
(unless otherwise noted)
Vee = 15 V,
dead·time control section (see Figure 2)
TEST CONDITIONS
PARAMETER
Input bias current
VI = 0 to 5.25 V
Maximum duty cycle, each output
DTC=OV
Tl594C, TL5941
MIN
TYpt
MAX
-2
-10
Maximum duty cycle
3
3.3
I1A
0.45
Zero duty cycle
Input threshold voltage
UNIT
0
V
t All typical values except for parameter changes with temperature are at TA = 25°C.
output section
PARAMETER
TEST CONDmONS
VC=40V, VE=OV,
Collector off-state current
TYpt
MAX
2
100
4
200
VCC=40V
DTC and OUTPUT CTRL = 0 V,
VC=15V,
VE=OV,
VCC= 1 t03V
EmlHer off-state current
Collector-emitler saturation voltage
II Common emiHer
Emitler follower
Output control input current
t
TL594C, Tl5941
MIN
-100
VCC = Vc =40V,
VE=O
VE=O,
IC=2oo mA
1.1
1.3
VC=15V,
IE=-200mA
1.5
2.5
3.5
VI =Vref
UNIT
IlA
I1A
V
mA
All typical values except for parameter changes with temperature are at TA = 25°C.
pwm comparator section (see Figure 2)
TEST CONDmONS
PARAMETER
Input threshold voltage, FEEDBACK
Zero duty cycle
Input sink current, FEEDBACK
FEEDBACK = 0.5 V
Tl594C, TL5941
MIN
TYpt
MAX
4
4.5
0.3
0.7
UNIT
V
mA
t All typical values except for parameter changes with temperature are at TA = 25°C.
undervoltage lockout section (see Figure 2)
PARAMETER
TEST CONDITIONS=!'
TL594C, TL5941
MIN
MAX
3.5
6.9
6
TA=25°C
Threshold voltage
---.----
FEEDBACK
Vref - - - I
Figure 1. Amplifier-Characteristics Test Circuit
8-144
:'IlEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL594
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS052C - APRIL 1988 - REVISED JULY 1999
PARAMETER MEASUREMENT INFORMATION
VCC=15V
..1.
? 150
L2
VCC
4
Test {
Inputs
3
DTC
C1
FEEDBACK
E1
12kO 6
Tl594
..A A
5
\I
II
-=
-b
0.011LF
1
T 2
L!§
15
-
RT
C2
CT
E2
I~}
ININ+
8
0
2W
150
0
2W
Output 1
9
-::!:11
Output 2
~-
Error
Amplifiers
IN-
13 OUTPUT
CTRl
REF
....1L
GND
17
5OkO
TEST CIRCUIT
Vee
Voltage
atC1
--------
OV
VCC
Voltage
atC2
------
OV
Voltage
atCT
DTClnput
OV
Feedback
________________
Input _
0.7 V
Duty Cycle
----I
~--~-- ~~Threshold~ltage
__
1
--1.*-11-
1
.
4.
-1
0% ---l4--l.~1
1
1_
MAX
~ 0% --.
VOLTAGE WAVEFORMS
Figure 2. Operational Test Circuit and Waveforms
:'I
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
8-145
TL594
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS052C - APRIL 1988 - REVISED JULY 1999
PARAMETER MEASUREMENT INFORMATION
15V
~tf
680
r E , ; - O ; - -,
Circuit
I
2W
I
CL=15pF
(includes probe and
jig capacitance)
TEST CIRCUIT
I
I
I
I
I
I
I
Output
L _ _ _ ...J
~tr
I
I
OUTPUT·VOLTAGE WAVEFORM
Figure 3. Common·Emltter Configuration
15V
---t-......----.-
L _ _ _ .J
I
I
Output
I
680
2W
CL=15pF
(includes probe and
Jig capacitance)
I
H-tr
I
I
I
I
I
j4-"i-- tf
-=TEST CIRCUIT
OUTPUT·VOLTAGE WAVEFORM
Figure 4. Emitter·Foliower Configuration
~TEXAS
13-146
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL594
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS052C - APRIL 1988 - REVISED JULY 1999
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY AND
FREQUENCY VARIATIONt
vs
TIMING RESISTANCE
100 k
~i~~5~~V
40k
N
:r:
r - .%
10 k "==l =-1"%
.0 1.111: 1
".-
I
g
1""
1k
IS
400
4k
• 1 ~F
~
CD
.~.-
O.lj!F
I&.
'Iii
Ll.ft=l%
i6
(3
100
i
~ ::' :or,= lj!
40
I II,
10
4k
10 k
40 k 100 k
RT - Timing Resistance - Q
1k
400 k
1M
t Frequency variation (.6.1) is the change in oscillator frequency that occurs over the full temperature range.
Figure 5
AMPLIFIER VOLTAGE AMPLIFICATION
vs
FREQUENCY
100
90
-
'\.
80
III
"c
I
70
.2
60
!E
50
i§
Q.
E
cc
40
J
30
CD
~
VCC=1 15v
.6.VO=3V TA = 25°C
:--...
l\.
.~
l\.
~
~
~
20
"-'\
10
10
100
1k
10 k
100 k
1M
f - Frequency - Hz
Figure 6
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-147
8-148
TL598
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
- FEBRUARY 1988 - REVISED JULY 1999
• Complete PWM Power Control Function
• Totem-Pole Outputs for 200-mA Sink or
Source Current
• Output Control Selects Parallel or
Push-Pull Operation
• Internal Circuitry Prohibits Double Pulse at
Either Output
• Variable Dead-Time Provides Control Over
Total Range
• Internal Regulator Provides a Stable 5-V
Reference Supply, Trimmed to 1%
Tolerance
• On-Board Output Current-Limiting
Protection
• Undervoltage Lockout for Low Vee
Conditions
• Separate Power and Signal Grounds
• TL598Q Has Extended Temperature
Range •.. -40°C to 125°C
D OR N PACKAGE
(TOP VIEW)
ERROR {lIN+
AMP 1
1INFEEDBACK
SIGNALGND
OUT1
1
15
14
13
12
11
21N+ }ERROR
21NAMP 2
REF
OUTPUTCTRL
VCC
Vc
POWERGND
OUT2
description
The TL598 incorporates all the functions required in the construction of pulse-width-modulated (PWM)
controlled systems on a single chip. Designed primarily for power-supply control, the TL598 provides the
systems engineer with the flexibility to tailor the power-supply control circuits to a specific application.
The TL598 contains two error amplifiers, an internal oscillator (externally adjustable), a dead-time control (DTC)
comparator, a pulse-steering flip-flop, a 5-V precision reference, undervoltage lockout control, and output
control circuits. Two totem-pole outputs provide exceptional rise- and fall-time performance for power FET
control. The outputs share a common source supply and common power ground terminals, which allow system
designers to eliminate errors caused by high current-induced voltage drops and common-mode noise.
The error amplifier has a common-mode voltage range from 0 V to Vee -2 V. The DTC comparator has a fixed
offset that prevents overlap of the outputs during push-pull operation. A synchronous multiple supply operation
can be achieved by connecting RT to the reference output and providing a sawtooth input to CT.
The TL598 device provides an output control function to select either push-pull or parallel operation. Circuit
architecture prevents either output from being pulsed twice during push-pull operation. The output frequency
for push-pull applications is one-half the oscillator frequency (f 0 = 2 R+ CT)' For single-ended applications:
f -
0-
1
RT CT'
The TL598C is characterized for operation from O°C to 70°C. The TL598Q is characterized for operation from
-40°C to 125°C.
•
Please be aware that an Important notice concemlng availability, standard warranty, and use in critical applications of
. . . . Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
="lExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
8-149
TL598
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS053C - FEBRUARY 1988 - REVISED JULY 1999
FUNCTION TABLE
INPUT/OUTPUT
CTRL
OUTPUT FUNCTION
VI=GNO
VI = REF
Single-ended or parallel output
Normal push-pull operation
AVAILABLE OPTIONS
PACKAGED DEVICES
SMALL
TA
OUTLINE
(D)
O°Cto 70°C
TL598CO
-40°C to 125°C
TL598QO
Chip forms are tested at 25°C.
CHIP FORM
PLASTIC
DIP
(N)
TL598CN
(V)
TL598Y
-
functional block diagram
OUTPUTCTRL
(see Function Table)
13
6
11 Vc
DTC
8 0UT1
=0.1 V
..!., r--r-...."
11N+
1IN21N+
21NFEEDBACK
2
9 0UT2
16
10 POWER
12 GND
15
r--------------------+--------------~VCC
3
Undervoltage
Lockout Control
L-~
____________________________1~4REF
r-__~~--------------------------------------~7SIGNAL
GND
--+
0.7mA
~TEXAS
8-150
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL598
PULSE·WIDTH·MODULATION CONTROL CIRCUITS
SLVS053C - FEBRUARY 1988 - REVISED JULY 1999
absolute maximum ratings over operating free-air temperature range {unless otherwise noted)t
Supply voltage, Vee (see Note 1) ........................................................... 41 V
Amplifier input voltage, VI ............................................................ Vee + 0.3 V
Collector voltage .......................................................................... 41 V
Output current (each output), sink or source, 10 ............................................. 250 mA
Package thermal impedance, 9JA (see Notes 2 and 3): D package ............................ 73°C/W
N package ............................ 88°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
Storage temperature range, Tstg .................................................. --65°C to 150°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the signal ground terminal.
2. Maximum power dissipation is a function of TJ(max), OJA, and TA. The maximum allowable power diSSipation at any allowable
ambient temperature is PD = (TJ(max) - TA)/OJA. Operating at the absolute maximum TJ of 150°C can impact reliability.
3. The package thermal impedance is calculated in accordance with JESD 51 , except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
MIN
MAX
Supply voltage, VCC
7
40
V
Amplifier input voltage, VI
0
VCC-2
40
V
Collector voltage
Output current (each output), sink or source, 10
Current into feedback terminal, IlL
TIming capacitor, CT
TIming resistor,
Rr
V
200
rnA
0.3
rnA
0.00047
10
1.8
500
/oL F
kn
kHz
1
300
ITL598C
0
70
I TL598Q
-40
125
Oscillator frequency, fosc
Operating free-air temperature, TA
UNIT
°C
-!I
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
8-151
TL598
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS053C - FEBRUARY 1988 - REVISED JULY 1999
electrical characteristics over recommended operating free-air temperature range, Vcc
(unless otherwise noted)
= 15 V
reference section (see Note 4)
TL598C
PARAMETER
TEST CONDITIONSt
IO=1mA
Input regulation
VCC = 7Vto 40 V
4.9
TA = full range
Output regulation
IO=1mAt010mA
Output voltage change with
temperature
ATA = MIN to MAX
TY"*
5
4.95
TA=25°C
Output voltage (REF)
Short-circuit output current§
MIN
TL598Q
MAX
MIN
5.05
4.95
5.1
4.9
TY"*
5
5.05
2
25
2
22
TA=25°C
1
15
1
15
50
2
-10
REF=OV
V
5.1
TA=25°C
TA = full range
UNIT
MAX
mV
mV
80
2
10
-48
-10
10
mVN
-48
mA
t
Full range is O°C to 70°C for the TL598C, and -40°C to 125°C for the TL5980.
:t: All typical values except for parameter changes with temperature are at TA = 25°C.
§ Duration of the short circuit should not exceed one second.
NOTE 4: Pulse-testing techniques that maintain the junction temperatura as close to the ambient temperature as possible must be used.
oscillator section, CT
=O.001I1F, RT ~ 12 kn (see Figure 1) (see Note 4)
TL598C,TL598Q
PARAMETER
TEST CONDITIONSt
MIN
Frequency
All values of VCC, CT,
Frequency change with voltage
AT, TA constant
VCC = 7Vt040V,
100
TA=25°C
ATA = full range
Frequency change with temperature#
ATA = full range,
CT=0.01ILF
Full range is O°C to 70°C for the TL598C, and -40°C to 125°C for the TL5980.
1
10
70
120
50
80
N
:t: All typical values except for parameter changes with temperature are at TA = 25°C.
I (xn-X)
n=1
11 Standard deviation is a measure of the statistical distribution about the mean as derived from the formula:
UNIT
MAX
100
Standard deviation of frequencyl1
t
TY"*
kHz
HzlkHz
HzlkHz
HzlkHz
2
0=
N-1
# Effects of temperature on extemal AT and Or are not taken Into account.
NOTE 4. Pulse-testing techniques that maintain the junction temperature as close to the ambient temperature as possible must be used.
error amplifier section (see Note 4)
PARAMETER
TL598C, TL598Q
TEST CONDITIONS
MIN
MAX
UNIT
Input offset voltage
FEEDBACK = 2.5 V
TY"*
2
10
mV
Input offset current
FEEDBACK = 2.5 V
25
250
nA
Input bias current
FEEDBACK = 2.5 V
0.2
1
\lA
Common-mode input voltage range
VCC= 7Vt040V
Open-loop voltage amplification
AVO (FEEDBACK) = 3 V,
Oto
VCC-2
Vo (FEEDBACK) = 0.5 V to 3.5 V
70
Unity-gain bandwidth
V
95
dB
800
kHz
Common-mode rejection ratio
VCC=40V,
Output sink current (FEEDBACK)
FEEDBACK = 0.5 V
Output source current (FEEDBACK)
FEEDBACK = 3.5 V
Phase margin at unity gain
FEEDBACK = 0.5 V to 3.5 V,
RL=2kn
65°
Supply-voltage rejection ratio
FEEDBACK = 2.5 V,
RL=2kn
100
AVIC=6.5V,
TA = 25°C
65
80
dB
0.3
0.7
mA
rnA
-2
AVCC=33V,
dB
:t: All typical values except for parameter changes with temperature ara at TA = 25°C.
NOTE 4. Pulse-testing techniques that maintain the junction temperature as close to the ambient temperature as possible must be used.
~TEXAS
INSTRUMENTS
8-152
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
TL598
PULSE·WIDTH·MODULATION CONTROL CIRCUITS
SLVS053C - FEBRUARY 1988 - REVISED JULY 1999
electrical characteristics over recommended operating free-air temperature range,
(unless otherwise noted)
vee = 15 V
undervoltage lockout section (see Note 4)
PARAMETER
TL598C
TEST CONDlTlONst
MIN
Hysteresis:l=
MIN
MAX
4
6
4
6
.1TA = full range
3.5
6.9
3
6.9
TA=25°C
100
100
50
30
TA=25°C
Threshold voltage
TL598Q
MAX
TA = full range
UNIT
V
mV
t Full range is O°C to 70°C for the T1598C, and -4Q°C to 125°C for the Tl598Q.
:1= Hysteresis
is the difference between the positive-going input threshold voltage and the negative-going input threshold voltage.
NOTE 4. Pulse-testing techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.
output section (see Note 4)
PARAMETER
TL598C, TL598Q
TEST CONDITIONS
MIN
High-level output voltage
VCC= 15V,
VC= 15V
lo=-2oomA
12
IO=-20mA
13
Low-level output voltage
VCC= 15V,
VC= 15V
IO=20mA
Output-control input current
VI =Vref
VI=0.4V
MAX
UNIT
V
2
lo=2oomA
0.4
V
3.5
mA
100
IJA
NOTE 4. Pulse-testing techniques must be used that maintain the Junction temperature as close to the ambient temperature as possible.
dead·time control section (see Figure 1) (see Note 4)
PARAMETER
TEST CONDITIONS
Input bias current (OTC)
VI = Oto 5.25 V
Maximum duty cycte, each output
OTC=OV
TL598C
MIN
TYPi
MAX
-2
-10
0.45
MIN
TL598Q
TYP§
-2
MAX
-25
UNIT
IJA
0.45
3
3.3
3
3.2
V
Maximum duty cycle
0
0
§ All typICal values except for parameter changes with temperature are at TA = 25°C.
NOTE 4. Pulse-testing techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.
Input threshold voltage (DTC)
Zero duty cycle
pwm comparator section (see Note 4)
PARAMETER
Input threshold voltage (FEEDBACK)
TEST CONDITIONS
TL598C, TL598Q
MIN
OTC=OV
TYPi
MAX
3.75
4.5
UNIT
V
Input sink current (FEEDBACK)
0.3
0.7
mA
V(FEEDBACK) = 0.5 V
§ All typical velues except for parameter changes with temperature are at TA = 25°C.
NOTE Pulse-testing techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.
total device (see Figure 1) (see Note 4)
PARAMETER
Standby supply current
TEST CONDITIONS
RT=Vref,
All other inputs and outputs open
TL598C, TL598Q
TYP§ MAX
MIN
I VCC= 15V
15
21
IVCC=40V
20
26
UNIT
mA
Average supply current
mA
OTC=2V
15
§ All typical values excapt for parameter changes with temperature are at TA = 25°C.
NOTE 4. Pulse-testing techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.
-!I
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-153
TL598
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS053C - FEBRUARY 1988 - REVISED JULY 1999
electrical characteristics over recommended operating free-air temperature range, Vee
(unless otherwise noted)
switching characteristics, TA
=15 V
=25°e (see Note 4)
TL598C, TL598Q
UNIT
TYP MAX
60
150
Output-voltage rise time
VCC=15V,
CL = 1500 pF,
VC=15V,
ns
See Figure 2
75
35
Output-voltage fall time
NOTE 4. Pulse-testing techniques must be used that maintain the junction temperature as close to the ambient temperature as pOSSIble.
PARAMETER
TEST CONDITIONS
MIN
electrical characteristics, Vee = 15 V, TA = 25°e
reference section (see Note 4)
TL598Y
TEST CONDInONS
PARAMETER
MIN
TYpi"
UNIT
MAX
Output voltage (REF)
10= 1 rnA
5
V
Input regulation
VCC =7Vt040V
2
mV
Output regulation
10=1 mAt010mA
Output-voltage change wRh temperature
Short-cIrcuit output current;
1
mV
2
mVN
rnA
-48
REF=OV
t All typical values except for parameter changes With temperature are at TA = 25°C.
; Duration of the short circuit should not exceed one second.
NOTE 4. Pulse-testing techniques that maintain the junction temperature as close to the ambient temperature as possible must be used.
oscillator section,
er = O.001IlF, Rr =12 kn (see Figure 1) (see Note 4)
PARAMETER
TL598Y
TEST CONDITIONS
MIN
Frequency
All values of VCC,
Standard deviation of frequency§
CT, AT, TA constant
Frequency change with voltage
VCC= 7Vt040V,
§ Standard deviation is a measure of the statistical distribution about the mean as derived from the formula:
0=
TYP
UNIT
MAX
100
kHz
100
HzlkHz
1
Hz/kHz
N
2
I (xn-X)·
n=1
N-1
NOTE 4. Pulse-testing techniques that maintain the junction temperature as close to the ambient temperature as possible must be used.
error amplifier section (see Note 4)
PARAMETER
TL598Y
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input offset voltage
Feedback = 2.5 V
2
Input offset current
Feedback = 2.5 V
25
nA
Input bias current
Feedback = 2.5 V
0.2
I1A
Open-loop voltage amplification
dVO (FEEDBACK) = 3 V,
Vo (FEEDBACK) = 0.5 V to 3.5 V
Unlty-galn bandwidth
95
dB
800
kHz
SO
dB
0.7
rnA
Common-mode rejection ratio
VCC=40V,
Output sink current (FEEDBACK)
FEEDBACK = 0.5 V
Phase margin at unity gain
FEEDBACK = 0.5 V to 3.5 V,
RL=2kO
65°
Supply-voltage rejection ratio
FEEDBACK = 2.5 V,
RL=2kO
100
dVIC=6.5V,
dVCC=33V,
mV
dB
NOTE 4. Pulse-testing techniques that maintain the Junction temperature as close to the ambient temperature as possible must be used.
~TEXAS
8-154
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL598
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVSD53C - FEBRUARY 1988 - REVISED JULY 1999
electrical characteristics, Vee = 15 V, TA = 25°C
dead·time control section (see Figure 1) (see Note 4)
PARAMETER
TEST CONDITIONS
MIN
TL598Y
TYP
MAX
UNIT
Input bias current (DTC)
VI = Oto 5.25 V
-2
I1A
Input threshold voltage (DTC)
Zero duty cycle
3
V
NOTE 4. Pulse-testing techniques that maintain the lunctlon temperature as close to the ambient temperature as posSible must be used.
pwm comparator section (see Note 4)
TEST CONDITIONS
PARAMETER
Input threshold voltage (FEEDBACK)
DTC=OV
Input sink current (FEEDBACK)
FEEDBACK = 0.5 V
MIN
TL598Y
TYP
MAX
UNIT
3.75
V
0.7
mA
NOTE 4. Pulse-testing techniques that maintain the junction temperature as close to the ambient temperature as possible must be used.
total device (see Figure 1) (see Note 4)
PARAMETER
TEST CONDITIONS
Standby supply current
RT=Vref,
All other inputs and outputs open
Average supply current
DTC=2V
MIN
TL598Y
TYP
IVCC=15V
15
IVCC=40V
20
15
MAX
UNIT
mA
rnA
NOTE 4. Pulse-testing techniques that maintain the junction temperature as ctose to the ambient temperature as pOSSible must be used.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-155
TL598
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS053C - FEBRUARY 1988 - REVISED JULY 1999
PARAMETER MEASUREMENT INFORMATION
Output
15V
VCC
1
2
3
Test {
Inputs
4
5
6
...----+--..- Vc
IN} ERROR
INAMP 1
ERROR {IN+
AMP 2
IN- 15
50kQ
FEEDBACK
DTC
CT
REF
OUTPUTCTRL
14
13
OUTPUT CONFIGURATION
11
Vc 1-'-'--- 15 V
RT
8
O.OOlI1F
OUT1 i-=--- OUTPUT 1
9
OUT2 1--"---- OUTPUT 2
12kQ
7
SIGNALGND
POWERGND
VI
FEEDBACK
10
-=MAIN DEVICE TEST CIRCUIT
ERROR AMPLIFIER TEST CIRCUIT
Figure 1. Test Circuits
. . , , - - - - - - Vc
. _ - - _ Output
CL
=1500 pF
OV
OUTPUT VOLTAGE WAVEFORM
OUTPUT CONFIGURATION
Figure 2. Switching Output Configuration and Voltage Waveform
~TEXAS
.
INSTRUMENTS
8-156
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL598
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS053C - FEBRUARY 1988 - REVISED JULY 1999
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY AND
FREQUENCY VARIATIONt
AMPLIFIER VOLTAGE AMPLIFICATION
vs
vs
TIMING RESISTANCE
FREQUENCY
80
100 k
Vee=15V
40k
roo.
-2%
N
J:
I
~
c
CD
:I
~
LL
j
10 k
6 t=
400
I
100
",-
0% -
I
1k
13
,
1--..,
0.111F
u
40
60
:;
0.0111F
loc. ...
~
.-
"ii
E
c(
CD
CII
40
~
F
10
1k
t
I
0
~
Aft=1%
~
J
"c
0.00111F
1%
4k
Vee = 15 V
AVO=3V
TA=25o e
ID
I:
~
"ii
E
Or=1I1F
~
20
c(
II IIII
o
4k
10 k
40k 100k
Ry - Timing Resistance - Q
400k
1M
1k
10 k
100k
1M
I - Frequency - Hz
Frequency variation (AI) is the change in predicted oscillator
Irequency that occurs over the lull temperature range.
Figure 4
Figure 3
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-157
8-158
UC284x, UC384x
CURRENT-MODE PWM CONTROLLERS
DPACKAGE
(TOP VIEW)
• Optimized for Off-Line and dc-to-dc
Converters
Low Start-Up Current «1 mAl
Automatic Feed-Forward Compensation
Pulse-by-Pulse Current Limiting
Enhanced Load-Response Characteristics
Undervoltage Lockout With Hysteresis
Double-Pulse Suppression
Hlgh-Current Totem-Pole Output
Internally Trimmed Bandgap Reference
5ao-kHz Operation
Error Amplifier With Low Output
Resistance
• Designed to Be Interchangeable With
Unltrode UC2842 and UC3842 Series
•
•
•
•
•
•
•
•
•
•
description
COMP! 1
NcI2
VFBI 3
NC 4
ISENSE 5
NC 6
AT/CT 7
v
14
13
12
11
10
gREF
NC
Vee
VC
OUTPUT
9 GND
S POWER GROUND
Ne - No Internal connection
D-8 OR P PACKAGE
(TOP VIEW}
COMPOS
VFB 2
7
ISENSE 3
6
RT/CT 4
5
REF
Vee
OUTPUT
GND
The UC284x and UC384x series of control
integrated circuits provide the features that are
necessary to implement off-line or dc-to-dc fixed-frequency current-mode control schemes with a minimum
number of external components. Some of the internally implemented circuits are an undervoltage lockout
(UVLO), featuring a start-up current of less than 1 mA, and a precision reference trimmed for accuracy at the
error amplifier input. Other internal circuits include logic to ensure latched operation, a pulse-width modulation
(PWM) comparator (which also provides current-limit contrOl), and a totem-pole output stage designed to source
or sink high-peak current. The output stage, suitable for driving N-channel MOSFETs, is low when it is in the
off state.
Major differences between members of these series are the UVLO thresholds and maximum duty-cycle ranges.
Typical UVLO thresholds of 16 V (on) and 10 V (off) on the UCx842 and UCx844 devices make them ideally
suited to off-line applications. The corresponding typical thresholds for the UCx843 and UCx845 devices are
8.4 V (on) and 7.6 V (off). The UCx842 and UCx843 devices can operate to duty cycles approaching 100%. A
duty-cycle range of 0 to 50% is obtained by the UCx844 and UCx845 by the addition of an internal toggle flip-flop,
which blanks the output off every other clock cycle.
The UC284x-series devices are characterized for operation from -40°C to 85°C. The UC384x-series devices
are characterized for operation from O°C to 70°C.
~1ExAs
Copyright@ 1999, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 855303 • OAlLAS, TEXAS 75265
8-159
UC284x, UC384x
CURRENT-MODE PWM CONTROLLERS
SLVS038D - JANUARY 1989 - REVISED JULY 1999
AVAILABLE OPTIONS
PACKAGED DEVICES
TJ
CHIP FORM
SMALL·OUTLINE
(D)
SMALL·OUTLINE
PLASTIC DIP
(0-8)
(P)
O°C to 70°C
UC3842D
UC3843D
UC3844D
UC3845D
UC3842D·8
UC3843D·8
UC3844D·8
UC3845D·8
UC3842P
UC3843P
UC3844P
UC3845P
UC3842Y
UC3843Y
UC3844Y
UC3845Y
-40°C to 85°C
UC2842D
UC2843D
UC2844D
UC2845D
UC2842D·8
UC2843D·8
UC2844D-8
UC2845D-8
UC2842P
UC2843P
UC2844P
UC2845P
-
(Y)
The D and D-8 packages are available taped and reeled. Add the suffix R to the deVice type (I.e.,
UC3842DR or UC3842DR-8). Chip forms are tested at 25°C.
functional block diagram
VCC~1~2______~______~________________________- .
1--1I1---__....-----it------------1-4
GND ""9=----<.....---4........,:=t
RT/CT -7-----ir----t
OSC
II
Vref
Good
Logic
REF
11 VC
OUTPUT
POWER
GROUND
Error
Amplifier
S
R
COMP ____________~
ISENSE_5________________________________~
t
The toggle flip-flop is present only in UC2844, UC2845, UC3844, and UC3845.
Pin numbers shown are for the D Package.
~TEXAS
INSTRUMENTS
8-160
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
PWM
Latch
UC284x, UC384x
CURRENT-MODE PWM CONTROLLERS
SLVS038D - JANUARY 1989 - REVISED JULY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted}t
Supply voltage (see Note 1) (Icc < 30 mAl ............................................. Self limiting
Analog input voltage range, VI (VFB and ISENSE) ................................... -0.3 V to 6.3 V
Output voltage, Vo (OUTPUT) .............................................................. 35 V
Input voltage, VI, (VC, D package only) ...................................................... 35 V
Supply current, Icc ...................................................................... 30 mA
Output current, 10 ......................................................................... ±1 A
Error amplifier output sink current .......................................................... 10 mA
Package thermal impedance, 9JA (see Notes 2 and 3): D package ............................ 86°C/W
N package .......................... 127°C/W
Output energy (capacitive load) .............................................................. 5!W
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the devica. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to the device GNO terminal.
2. Maximum power dissipation is a function of TJ(max), 9JA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is Po = (TJ(max) - TA)!9JA. Operating at the absolute maximum TJ of 150°C can impact reliability.
3. The package thermal impedance is calculated In accordance with JESO 51, excapt for through-hole packages, which use a trace
length of zero.
recommended operating conditions
MIN
NOM
MAX
UNIT
30
V
0
5.5
V
Input voltage, VI, VFB and ISENSE
0
5.5
V
Output voltage, vo' OUTPUT
0
30
V
-{).1
1
Supply voltage, VCC and VC:t
Input voltage, VI, RT/CT
Output voltage, VO, POWER GROUNOt
Supply current, extemally limited, ICC
V
25
mA
Averege output current, 10
200
mA
Reference output current, IOlref)
-20
mA
500
kHz
Timing capacitance, CT
nF
100
OSCillator frequency, fosc
I UC284x
Operating free-air temperature, TA
I UC384x
-40
85
0
70
°c
:t These recommended voltages for Vc and POWER GROUND apply only to the 0 package.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-161
UC284x, UC384x
CURRENT·MODE PWM CONTROLLERS
SLVS038D - JANUARY 1989 - REVISED JULY 1999
electrical characteristics over recommended operating free-air temperature range, Vee =15 V (see
Note 4), RT =10 kn, CT =3.3 nF (unless otherwise specified)
reference section
PARAMETER
UC284x
TEST CONDITIONS
MIN
TYPt
MAX
MIN
4.95
4.9
UC384x
TYpt
MAX
UNIT
Output voltage
10=1 rnA,
5
5.05
5
5.1
V
Line regulation
VCC=12Vt025V
6
20
6
20
mV
Load regulation
10= 1 rnA to 20 rnA
6
25
6
25
mV
0.2
0.4
0.2
0.4
mV...j°C
5.18
V
TJ = 25°C
Temperature coefficient
of output voltage
Output voltage
with worst-case variation
VCC=12Vt025V,
10=1 mAto 20 rnA
Output noise voltage
f= 10 Hz to 10 kHz,
TJ = 25°C
Output-voltage long-term drift
After 1000 h at TA = 25°C
4.9
5.1
4.82
50
Short-circuit output current
-30
).IV
50
5
25
-100
-180
-30
5
25
mV
-100
-180
rnA
t
All typical values are at TJ = 25°C.
NOTE Adjust VCC above the start threshold before setting it to 15 v.
oscillator section
PARAMETER
UC284x
TEST CONDITIONS
Oscillator frequency (see Note 5)
TJ = 25°C
Frequency change with supply voltage
VCC= 12Vt025V
UC384x
UNIT
MIN
TYPt
MAX
MIN
TYPt
MAX
47
52
57
47
52
57
kHz
2
10
2
10
HzlkHz
Frequency change with temperature
50
50
HzlkHz
Peak-to-peak amplitude at RT/CT
1.7
1.7
V
t All typical values are at TJ = 25°C.
NOTES: 4. Adjust VCC above the start threshold before setting it to 15 V.
5. Output frequency equals oscillator frequency for the UCx842 and UCx843. Output frequency is one-half oscillator frequency for the
UCx844 and UCx845.
error-amplifier section
PARAMETER
Feedback input voltage
UC284x
TEST CONDITIONS
COMPat2.5V
MIN
2.45
Input bias current
Open-loop voltage amplification
VO=2Vt04V
Supply-voltage rejection ratio
VCC=12Vt025V
VFB at 2.7 V,
CaMP at 1.1 V
Output source current
VFB at 2.3 V,
COMPat5V
High-level output vo~age
VFB at 2.3 V,
RL=15kQtoGND
Low-level output voltage
VFB at 2.7 V,
RL = 15 k!l to GND
MIN
2.50
2.55
2.42
-0.3
-1
UC384x
TYpf
MAX
2.50
2.58
-0.3
-2
UNIT
V
J.IA
dB
65
90
65
90
1
0.7
1
60
70
60
70
dB
2
6
2
6
rnA
-0.5
-0.8
-0.5
-0.8
rnA
5
6
5
6
t All typical values are at TJ = 25°C.
NOTE Adjust VCC above the start threshold before setting ~ to 15 V.
~TEXAS
8-162
MAX
0.7
Gain-bandwidth product
Output sink current
TYPt
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 752115
0.7
1.1
0.7
MHz
V
1.1
V
UC284x, UC384x
CURRENT-MODE PWM CONTROLLERS
SLVS038D - JANUARY 1989 - REVISED JULY 1999
electrical characteristics over recommended operating free-air temperature range, vee =15 V (see
Note 4), RT = 10 kn, CT = 3.3 nF (unless otherwise specified) (continued)
current-sense section
PARAMETER
TEST CONDITIONS
Voltage amplification
See Notes 6 and 7
Current-sense comparator threshold
COMPat5V,
See Note 6
Supply-voltage rejection ratio
VCC=12Vt025V,
See Note 6
UC284x
UC384x
MIN
TYPt
MAX
MIN
TYPt
MAX
2.85
3
3.13
2.85
3
3.15
0.9
1
1.1
0.9
1
1.1
Input bias current
Delay time to output
VN
V
dB
70
70
UNIT
-2
-10
-2
-10
j.tA
150
300
150
300
ns
t
All typical values are at TJ = 25°C.
NOTES: 4. Adjust VCC above the start threshold before setting ~ to 15 V.
6. These parameters are measured at the trip point of the latch, with VFB at 0 V.
7. Voltage amplification is measured between ISENSE and COMP, with the input changing from 0 V to 0.8 V.
output section
PARAMETER
TEST CONDITIONS
High-level output voltage
LOW-level output voltage
UC384x
UC284x
MIN
TYPt
13.5
13
13.5
13.5
12
13.5
MIN
TYP1
IOH =-20 mA
13
IOH=-200mA
12
MAX
MAX
UNIT
V
IOL=20mA
0.1
0.4
0.1
0.4
IOL=200mA
1.5
2.2
1.5
2.2
V
Rise time
CL= 1 nF,
TJ = 25°C
50
150
50
150
ns
Fall time
CL= 1 nF,
TJ = 25°C
50
150
50
150
ns
t
All typical values are at TJ = 25°C.
NOTE Adjust VCC above the start threshold before setting it to 15 V.
undervoltage-Iockout section
Start threshold voltage
Minimum operating voltage after startup
UC384x
UC284x
PARAMETER
MIN
TYP1
MAX
MIN
TYPt
MAX
UCx842, UCx844
15
16
17
14.5
16
17.5
UCx843, UCx845
7.8
8.4
9
7.8
8.4
9
UCx842, UCx844
9
10
11
8.5
10
11.5
UCx843, UCx845
7
7.6
8.2
7
7.6
8.2
UNIT
V
V
t All typical values are at TJ = 25°C.
NOTE Adjust VCC above the start threshold before setting it to 15 V.
pulse-width-modulator section
UC284x
PARAMETER
Maximum duty cycle
I UCx842, UCx843
I UCx844, UCx845
UC384x
MIN
TYPt
MAX
MIN
95%
97%
100%
46%
48%
50%
Minimum duty cycle
0
TYP1
MAX
95%
97%
100%
46%
48%
50%
UNIT
0
t All typical values are at TJ = 25°C.
NOTE Adjust VCC above the start threshold before setting it to 15 V.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-163
UC284x, UC384x
CURRENT-MODE PWM CONTROLLERS
SLVS038D - JANUARY 1989 - REVISED JULY 1999
electrical characteristics over recommended operating free-air temperature range, vee =15 V (see
Note 4), RT = 10 kn, CT = 3.3 nF (unless otherwise specified) (continued)
supply voltage
PARAMETER
UC284x
TEST CONDITIONS
MIN
Start-up current
TYPt
MAX
MIN
UC384x
TYpt MAX
UNIT
0.5
1
0.5
1
mA
Operating supply current
VFB and ISENSE at 0 V
11
17
11
17
mA
limiting voltage
ICC=25mA
34
34
V
t All typical values are at TJ = 25°C.
NOTE Adjust VCC above the start threshold before setting it to 15 V.
electrical characteristics, Vee = 15 V(see Note 4), RT= 10 I«l, CT = 3.3 nF, TJ =25°C (unless otherwise
specified)
reference section
PARAMETER
TEST CONDmONS
UC384xY
MIN
TYP
MAX
UNIT
Output voltage
10=1 mA
5
V
line regulation
VCC=12Vt025V
6
mV
Load regulation
10=1 mAt020mA
6
Temperature coefficient of output voltage
mV
0.2
Output noise voltage
f= 10 Hz to 10 kHz
Output-voltage long-term drift
After 1000 h at TA = 25°C
Short-circuit output current
NOTE Adjust VCC above the start threshold before setting ilto 15
mV/"C
50
ltV
5
mV
-100
mA
v.
oscillator section
PARAMETER
TEST CONDITIONS
Oscillator frequency (see Note 5)
Frequency change with supply voltage
VCC = 12Vt025 V
Frequency change with temperature
Peak-to-peak amplitude at RT/CT
NOTES:
TYP
MAX
UNIT
52
kHz
2
HzlkHz
5
HzlkHz
1.7
V
4. Adjust VCC above the start threshold before setting It to 15 V.
5. Output frequency equals oscillator frequency for the UCx842 and UCx843. Output frequency is one-half oscillator frequency for the
UCx844 and UCx845.
~TEXAS
8-164
UC384xY
MIN
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UC284x, UC384x
CURRENT-MODE PWM CONTROLLERS
SLVS03BD - JANUARY 1989 - REVISED JULY 1999
electrical characteristics, vee = 15 V (see Note 4), RT= 10 kn, CT = 3.3 nF, TJ = 25°C (unless otherwise
specified) (continued)
error-amplifier section
PARAMETER
Feedback Input voltage
TEST CONDITIONS
UC384xY
MIN
COMPat2.5V
Input bias current
Open-loop voltage amplification
TYP
MAX
UNIT
2.50
V
-D.3
!LA
90
VO=2Vt04V
Gain-bandwidth product
dB
1
MHz
70
dB
6
mA
-D.8
mA
Supply-voltage rejection ratio
VCC=12Vt025V
Output sink current
VFB at 2.7 V,
COMPatl.l V
Output source current
VFB at 2.3 V,
COMPat5V
High-level output voltage
VFB at 2.3 V,
RL = 15 kn to GND
8
V
Low-level output voltage
VFBat2.7V,
RL= 15 kn to GND
0.7
V
NOTE Adjust VCC above the start threshold before setting ~ to 15 V.
current-sense section
PARAMETER
TEST CONDITIONS
UC384xY
MIN
TYP
MAX
3
UNIT
Voltage amplification
See Notes 6 and 7
Current-sense comparator threshold
COMPat5V,
See Note 6
1
Supply-voltage rejection ratio
VCC = 12 V to 25 V,
See Note 6
70
dB
-2
!LA
150
ns
Input bias current
Delay time to output
VN
V
NOTES: 4. Adjust VCC above the start threshold before setting it to 15 V.
6. These parameters are measured at the trip point of the latch, with VFB at 0 V.
7. Voltage amplification is measured between ISENSE and COMP, with the Input changing from 0 V to 0.8 V.
output section
PARAMETER
TEST CONDITIONS
High-level output voltage
UC384xY
MIN
TYP
IOH=-20mA
13.5
IOH=-200mA
13.5
MAX
UNIT
V
IOL=20mA
0.1
IOL = 200 mA
1.5
Rise time
CL= 1 nF
50
ns
Fall time
CL = 1 nF
50
ns
Low-level output voltage
V
NOTE Adjust VCC above the start threshold before setting it to 15 V.
undervoltage-Iockout section
UC384xY
PARAMETER
Start thrashold voltage
Minimum operating voltage after startup
MIN
TYP
UC3842Y, UC3844Y
16
UC3843Y, UC3845Y
8.4
UC3842Y, UC3844Y
10
UC3843Y, UC3845Y
7.6
MAX
UNIT
V
V
NOTE Adjust VCC above the start threshold before setting It to 15 V.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS, TEXAS 75285
8--165
UC284x, UC384x
CURRENT·MODE PWM CONTROLLERS
SLVS038D-JANUARY 1989 - REVISED JULY 1999
electrical characteristics, Vee = 15 V (see Note 4), RT= 10 kn, CT = 3.3 nF, TJ = 25°C (unless otherwise
specified) (continued)
pulse-width-modulator section
UC384xY
PARAMETER
MIN
Maximum duty cycle
TYP
I UC3842Y, UC3843Y
97%
I UC3844Y, UC3845Y
48%
MAX
UNIT
NOTE Adjust VCC above the start threshold before setting it to 15 V.
supply voltage
PARAMETER
TEST CONDITIONS
Start-up current
UC384xY
MIN
TYP
MAX
UNIT
0.5
1
rnA
Operating supply current
VFB and ISENSE at 0 V
11
17
rnA
Limiting voltage
ICC=25mA
34
NOTE Adjust VCC above the start threshold before setting It to 15 V.
~TEXAS
8-166
INSTRUMENTS
POST OFFICE
eox 655303 •
DALLAS, TEXAS 75265
V
UC284x, UC384x
CURRENT-MODE PWM CONTROLLERS
SLVS038D - JANUARY 1989 - REVISED JULY 1999
APPLICATION INFORMATION
~ O.SmA
VFB
COMP
NOTE A.
Error amplifier can source or sink up to 0.5 mAo
Figure 1. Error-Amplifier Configuration
Error
Amplifier
liS
(see Note A)
2R
1V
n
Rf
Rs
COMP
fl
Current-8ense
Comparator
ISENSE
Ct
GND
-=
NOTE A. Peak current (IS) is determined by the formula:
_ 1V
's(max) -
As
A small RC filter formed by resistor Rf and capacitor Ct may be required to suppress switch transients.
Figure 2. Current-Sense Circuit
REF
RT
(see Note A)
RT/CT
;::::::::
GND
NOTE A. For AT > 5 kf.!: f =
~;T
-=
Figure 3. Oscillator Section
-!I
TEXAS
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75265
8-167
UC284x, UC384x
CURRENT-MODE PWM CONTROLLERS
SLVS038D - JANUARY 1989 - REVISED JULY 1999
APPLICATION INFORMATION
TIMING RESISTANCE
DEAD TIME
vs
vs
TIMING CAPACITANCE
FREQUENCY
100
VCC= 15"
RT~5kn
40
01)
::I.
TA = 25°C
~
~
10
~
4
i
.:
L
1
c
II
~=1
nF
I
I
i=
40 1--I-Hd-ttRjf-\-\I-t-N;lzl'!\l-\-\I\~l-tt.rrr =1 2,
\".
10
CT=22nF
l..-':
""
V\
1\
\.
\~
'''-
il100 nF
0.4
\.
\.
\
\
II
VCC=
0.1
1
o
10
4
40
T~=25°~II'
100
100
Cr - Timing Capacitance - nF
10 k
1k
100 k
1M
f • Frequency· Hz
Figure 4
Figure 5
open-loop laboratory test fixture
In the open-loop laboratory test fixture shown in Figure 6, high peak currents associated with loads necessitate
careful grounding techniques. Timing and bypass capacitors should be connected close to the GND terminal
in a single-point ground. The transistor and 5-kQ potentiometer sample the oscillator waveform and apply an
adjustable ramp to the ISENSE terminal.
r---------.----.--------------------~-------------------REF
RT
}---~~VCC
4.7kn
2N2222
OUT
100kn
REF
r~~~----~~COMP
0.111F
1 kn
Error Amplifier >+---+-----+----+--IVFB
UC284x
VCC 1--+---.
Adlust
0.1 I1F
5kn >+---+---IISENSE UC384x OUTPUT
1 kn, 1 W
OUTPUT
4.7kn
1
ISENSE
Adjust
RT/CT
GND
._-------------------GNO
-=-
Figure 6. Open-Loop Laboratory Test Fixture
~TEXAS
8-168
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
UC284x, UC384x
CURRENT-MODE PWM CONTROLLERS
SLVS038D-JANUARY 1989- REVISED JULY 1999
APPLICATION INFORMATION
shutdown technique
The PWM controller (see Figure 7) can be shut down by two methods: either raise the voltage at ISENSE above
1 V or pull the COMP terminal below a voltage two diode drops above ground. Either method causes the output
of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output
remains low until the next clock cycle after the shutdown condition at the COMP or ISENSE terminal is removed.
In one example, an externally latched shutdown can be accomplished by adding an SCA that resets by cycling
Vee below the lower UVLO threshold. At this pOint, the reference turns off, allowing the SCA to reset.
1 kO
r--'VV\~""'---I
REF
COMP
__.---1ISENSE
3300
Shutdown --+
5000 ' - - - - -
I To Current-Sense
~
Resistor
Figure 7. Shutdown Techniques
A fraction of the oscillator ramp can be resistively summed with the current-sense signal to provide slope
compensation for converters requiring duty cycles over 50% (see Figure 8). Note that capacitor C forms a filter
with A2 to suppress the leading-edge switch spikes.
REF~~---~----.
J
0.11-lF
RT
RT/CT 1 - - - - - -..
~ISENSE
R1
R2
ISENSE
~-------~----4~-WIr-----'
nn
RSENSE
Figure 8. Slope Compensation
~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-169
8-170
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
- REVISED JULY
PPACKAGE
(TOP VIEW)
• Output Current ••• 100 mA
• Low Loss ••• 1.1 Vat 100 mA
• Operating Range ••• 3.5 V to 15 V
• Reference and Error Amplifier for
Regulation
F B / S O O S VCC
CAP+ 2
7
asc
GNO
CAP-
• External Shutdown
• External OSCillator Synchronization
3
4
6
5
VREF
VOUT
DWPACKAGE
(TOP VIEW)
• Devices Can Be Paralleled
• Pin-to-Pln Compatible With the
LTC1044n660
NC
NC
description
NC
1
NC
FBISO
VCC
asc
The LT1054 is a bipolar, switched-capacitor
voltage converter with regulator. It provides higher
output current and significantly lower voltage
losses than previously available converters. An
adaptive-switch
drive
scheme
optimizes
efficiency over a wide range of output currents.
Total voltage drop at 100-mA output current is
typically 1.1 V. This holds true over the full
supply-voltage range of 3.5 V to 15 V. Quiescent
current is typically 2.5 mAo
12
11
10
9
VREF
VOUT
NC
NC
NC- No Internal connection
The LT1054 also provides regulation, a feature not previously available in switched-capacitor voltage
converters. By adding an external resistive divider, a regulated output can be obtained. This output is regulated
against changes in both input voltage and output current. The LT1 054 also can be shut down by grounding the
feedback terminal. Supply current in shutdown is typically 100!lA.
The internal oscillator of the LT1 054 runs at a nominal frequency of 25 kHz. The oscillator terminal can be used
to adjust the switching frequency or to extemally synchronize the LT1054.
The LT1054C is characterized for operation over a free-air temperature range of DoC to 70°C. The LT10541 is
characterized for operation over a free-air temperature range of -40°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP
FORM
SMALL
OUTLINE
(DW)
PLASTIC
DIP
(P)
O'Cto 70'C
LT1054COW
LT1054CP
LT1054Y
-40'C to S5'C
LT105410W
LT1054IP
-
TA
(V)
The OW package IS available taped and reeled. Add the suffix R to the
device type, (i.e., LT1054COWR). Chip forms are tested at 25'C.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
Copyright © 1999. Texas Instruments Incorporated
8-171
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
functional block diagram
Vee
8
2.5V
FB/SD ----'---*-+-+----1
ose-7~-~-~-~~
R
GND
VOUT
t External capacitors
Pin numbers shown are for the P package.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted*
Supply voltage, Vee (see Note 1) .......................................................... 16V
Input voltage range, VI (FB/SO terminal) ................................................ 0 V to Vee
Input voltage range, VI (OSC terminal) .................................................. 0 V to Vref
Junction temperature (see Note 2) TJ: LT1054C ............................................. 125°C
LT10541 .............................................. 135°C
Package thermal impedance, 9JA (see Notes 3 and 4): OW package .......................... 57°CIW
P package .......................... 127°CIW
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
Storage temperature range, Tstg .................................................. -55°C to 150°C
:j: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may allect device reliability.
NOTES: 1. The absolute maximum supply voltage rating of 16 V is for unregulated circuits. For regulation mode circuits with VOUT S; 15 V, this
rating may be increased to 20 V.
2. The devices are functional up to the absolute maximum junction temperature.
3. Maximum power dissipation is a function of TJ(max), OJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) - TA)/OJA. Operating at the absolute maximum TJ of 150°C can impact reliability.
4. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
~TEXAS
INSTRUMENTS
8-172·
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
recommended operating conditions
Supply voltage, Vee
I LT1054e
Operating free-air temperature range, TA
I LT10541
MIN
MAX
3.5
15
0
70
--40
85
UNIT
V
°e
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
Va
Vref
TEST CONDITIONS
TJ = 25°C,
UNIT
MIN
TYpt
MAX
--4.7
Regulated output voltage
Vee=7V,
RL=5000,
See Note 5
25°C
-5
-5.2
Input regulation
Vce=7Vt012V,
RL=5000,
See Note 5
Full range
5
25
mV
Output regulation
Vee=7V,
See Note 5
RL= 1000t05000,
Full range
10
50
mV
Voltage loss, Vee -I vol
(see Note 6)
110=10mA
Full range
0.35
0.55
el = Co = 100 I1F tantalum
110= 100 rnA
Full range
1.1
1.6
Output resistance
ala = 10 rnA to 100 rnA,
Oscillator frequency
Vee=3.5Vt015V
Reference voltage
I(REF) = 60
See Note 7
Full range
I1A
10=0
Supply current in
shutdown
V(FBlSD) = 0 V
V
10
15
0
25
35
kHz
25°C
2.35
2.5
2.65
Full range
2.25
25°C
Supply current
V
15
Full range
Maximum switch current
ICC
LT1054C
LT10541
TAt
2.75
300
V
rnA
I Vee = 3.5 V
Full range
2.5
4
I Vee=15V
Full range
3
5
Full range
100
200
rnA
I1A
t Full range IS ooe to 70°C for the LT1054e and --4Q°e to 85°C for the LT10541.
; Ali typical values are at TA = 25°C.
NOTES: 5. Ali regulation specifications are for a device connected as a positive-to-negative converter/regulator with R1 = 20 kO,
R2 = 102.5 kO, external capacitor elN = 10 I1F (tantalum), external capacitor eOUT = 100 I1F (tantalum) and C1 = 0.002 I1F
(see Figure 15).
6. For voltage-loss tests, the device is connected as a voltage inverter, with terminals 1, 6, and 7 unconnected. The voltage losses
may be higher in other configurations. elN and eOUT are external capacitors.
7. Output resistance Is defined as the slope of the curve (aVo versus ala) for output currents of 10 rnA to 100 rnA. This represents
the linear portion of the curve. The incremental slope of the curve is higher at currents less than 10 rnA due to the characteristics
of the Switch transistors.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-173
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
electrical characteristics over recommended operating conditions, TA = 25°C (unless otherwise
noted)
.
PARAMETER
Va
Regulated output voltage
VCC=7V
Input regulation
VCC = 7 V to 12 V,
Output regulation
VCC=7V,
Voltage loss, VCC -I VOl (see Note 6)
Vref
TEST CONDmONS
TJ = 25°C,
Ala = 10 mA to 100 mA,
VCC= 3.5 Vto 15V
Reference voltage
I(REF) = 60 I1A
See Note 5
-5
V
See Note 5
5
mV
mV
SeeNote7
Maximum switch current
ICC
Supply current
10=0
UNIT
RL=5000,
CI = Co = 100 IlF tantalum
Oscillator frequency
LT1054Y
TYP MAX
RL=5000,
RL = 1000 to 500 0.
Output resistance
MIN
See Note 5
10
110=10mA
0.35
110=100rnA
1.1
V
10
0
25
kHz
2.5
V
300
rnA
IVCC=3.5V
2.5
Ivcc= 15V
3
mA
Supply current in shutdown
100
V(FBlSD) = 0 V
I1A
NOTES: 5. All regulation speCifications are for a deVice connected as a posltlve-to-negatlve converter/regulator With Rl = 20 kCl,
R2 = 102.5 kCl, extemal capacitor CIN = 10 IlF (tantalum), extemal capacitor COUT = 100 IlF (tantalum) and Cl = 0.002 IlF
(see Figure 15).
6. For voltage-loss tests, the device Is connected as a voltage Inverter, with terminals 1, 6, and 7 unconnected. The voltaga losses
may be higher in other configurations. CIN and COUT are extemal capacitors.
7. Output resistance Is defined as the slope of the curve (AVO versus Ala) for output currents of 10 mA to 100 mAo This represents
the linear portion of the curve. The incremental slope of the curve is higher at currents less than 10 mA due to the characteristics
of the switch transistors.
..
-!111ExAs
8-174
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Shutdown threshold voltage vs Free-air temperature
1
Supply current vs Input voltage
2
OScillator frequency vs Free-air temperature
3
Supply current in shutdown vs Input voltage
4
Average supply current vs Output current
5
Output voltage loss vs Input capacitance
6
Output voltage loss vs Oscillator frequency (10 IlF)
7
Output voltage loss vs Oscillator frequency (100 1lF)
8
Regulated output voltage vs Free-air temperature
9
Reference voltage change vs Free-air temperature
10
Voltage Loss vs Output current
11
Table of Figures
FIGURE
Switched-Capacitor Building Block
12
Switched-Capacitor Equivalent Circuit
13
Circuit With Load Connected From VCC to VOUT
14
Extemal Clock System
15
Basic Regulation Configuration
16
Power-Dissipation-Limiting Resistor in Series With CIN
17
Motor Speed Servo
18
Basic Voltage Inverter
19
Basic Voltage Inverter/Regulator
20
Negative Voltage Doubler
21
Positive Doubler
22
100-mA Regulating Negative Doubler
23
Dual-Output Voltage Doubler
24
5-V to ±12-V Converter
25
Strain-Gage Bridge Signal Conditioner
26
3.5-V to 5-V Regulator
27
Regulating 200-mA +12-V to -S-V Converter
28
Digitally Programmable Negative Supply
29
Positive Doubler With Regulation (5-V to a-v Converter)
30
Negative Doubler With Regulator
31
~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-175
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
TYPICAL CHARACTERISTICSt
SHUTDOWN THRESHOLD VOLTAGE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
vs
INPUT VOLTAGE
0.6
0.5
5
I
10=0
............
...............
~
0.4
c
4
E
r--.......
I
...............
V(FB/SO)
1 -
t"-
3
0.3
~
a.
~
UI
2
I
0.2
0
9
0.1
o
-50
o
-25
75
25
50
TA - Free-Air Temperature - °e
o
100
o
10
5
Vee -Input Voltage - V
Figure 1
15
Figure 2
OSCILLATOR FREQUENCY
SUPPLY CURRENT IN SHUTDOWN
VS.
vs
FREE-AIR TEMPERATURE
INPUT VOLTAGE
35
120
33
!.lII:
31
I
r;
!
r
I:g
u..
S
29
27
::-....
........
1I
~ r--....
~
25
!
Vee = 15 V
Vee = 3.5 V ...............
23
.5
~ '"
~
I
19
17
15
-50
-25
o
25
50
75
TA - Free-Air Temperature - °e
80
..... ~
~
=0
---"'"'"
. . . - -V(FB/SO)
60
C
""
21
100
100
40
20
o
o
Figure 3
10
5
Vee -Input Voltage - V
Figure 4
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
~1ExAs
INSTRUMENTS
8-176
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
15
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE LOSS
vs
INPUT CAPACITANCE
AVERAGE SUPPLY CURRENT
vs
OUTPUT CURRENT
1.4
140
C
E
120
I
i
u=
~
Co
Co
ciJ
t
100
>
I
/
80
60
/
CD
~
1.2
V
./
40
/
20
o~
o
/
/
~
V
10=100mA
~
10=50mA
1.0
....I
CD
CI
0.8
j
0.6
.!I
I
;-
0
/
0.4
o
100
CoJgUr~tion
o
10
20
30 40 50 60 70 80
Input Capacitance - JlF
OUTPUT VOLTAGE LOSS
vs
OSCILLATOR FREQUENCY
OUTPUT VOLTAGE LOSS
vs
OSCILLATOR FREQUENCY
2.5 "'--'-"T""T""T"T''TT1'--'T''""''T''-;'''''T'''T''TTT1
Inverter Configuration
2.25 CIN = 10 JlF Tantalum
COUT = 100 JlF Tantalum
1.751--+--+-+t-+-t+l-r--+--+-t-+-f-H-H
~
2.5
InveJte':.~onlig~rlrtl~~ I
2.25 - CIN = 100 JlF Tantalum
COUT = 100 F Tantalum
2
>
I
t
"S
g
I
-4.9
~
11
-5
-
-
~
~
~
-11. 6
01
r!
-12
I
~ -12.2
r---
!
60
- -
40
t
20
~
o
I
-20
a:
-40
~
I
!
-100
-50
100
......-
VREF at 0
=2.500 V
-80
-12.4
-12.6
-50
80
I
-5.1
~ -11.8
:e
-25
0
25
50
75
100
TA - Free-Air Temperature - ·C
Figure 9
Figure 10
VOLTAGE LOSS
VB
OUTPUT CURRENT
2
1.8
J.5vkvcbs1$v
r- CI=Co =1ooI1F
1.6
>
I
~
1.2
~
[).,
r-- f-- J=2~·C
III
01
:!
J=l~
1.4
1"-.
,., ~
0.8
0.6
..........:
0.4
.~
,,o
0.2
o
e::::: /
~~
10
20
~
,.,
./
".
/
. / V- i.,...--'
.".
.......
"...,
"...,
K
T.i)-S
·C
30 40 50 60 70
Output Current..;. mA
80
90 100
Figure 11
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
~TEXAS
8-178
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
125
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
PRINCIPLES OF OPERATION
A review of a basic switched-capacitor building block is helpful in understanding the operation of the LT1054. When
the switch shown in Figure 12 is in the left position, capacitor C1 charges to the voltage at V1. The total charge on
C1 is q1 C1 V1. When the switch is moved to the right, C1 is discharged to the voltage at V2. After this discharge
time, the charge on C1 is q2 = C1V2. The charge has been transferred from the source V1 to the output V2. The
amount of charge transferred is shown in equation 1.
=
~q
= q1 -q2 = C1(V1 - V2)
(1 )
If the switch is cycled f times per second, the charge transfer per unit time (i.e., current) is as shown in equation 2.
I
=f
x ~q
=f
x C1 (1-V2)
(2)
To obtain an equivalent resistance for a switched-capacitor network, this equation can be rewritten in terms of voltage
and impedance equivalence as shown in equation 3.
I
= V1
- V2
(1/fC1)
= V1
- V2
REQUIV
(3)
V1~:r.IV2
1.
T C1 T C2
--
--
RL
--
Figure 12. Switched-Capacitor Building Block
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-179
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D- FEBRUARY 1990- REVISED JULY 1999
PRINCIPLES OF OPERATION
A new variable, REOUIV, is defined as REOUIV = 1 + fC1. The equivalent circuit for the switched-capacitor network
is shown in Figure 13. The LT1054 has the same switching action as the basic switched-capacitor building block.
Even though this simplification does not include finite switch-on resistance and output-voltage ripple, it provides an
insight into how the device operates.
.
These simplified circuits explain voltage loss as a function of oscillator frequency (see Figure 7). As oscillator
frequency is decreased, the output impedance is eventually dominated by the 11fC1 term and voltage losses rise.
Voltage losses also rise as oscillator frequency increases. This is caused by internal switching losses that occur due
to some finite charge being lost on each switching cycle. This charge loss per-unit-cycle, when multiplied by the
switching frequency, becomes a current loss. At high frequency, this loss becomes significant and voltage losses
again rise.
The oscillator of the LT1054 is designed to run in the frequency band where voltage losses are at a minimum.
Figure 13. Switched-Capacitor Equivalent Circuit
terminal functions (see functional block diagram)
Supply voltage Vee alternately charges CIN to the input voltage when CIN is switched in parallel with the input supply
and then transfers charge to COUT when CIN is switched in parallel with COUT' Switching occurs at the oscillator
frequency. During the time that CIN is charging, the peak supply current is approximately 2.2 times the output current.
During the time that CIN is delivering a charge to COUT, the supply current drops to approximately 0.2 times the output
current. An input supply bypass capacitor supplies part of the peak input current drawn by the LT1 054, and averages
out the current drawn from the supply. A minimum input supply bypass capacitor of 2 (IF, preferably tantalum or some
other low equivalent-series-resistance (ESR) type, is recommended. A larger capacitor is desirable in some cases.
An example of this would be when the actual input supply is connected to the LT1054 through long leads or when
the pulse currents drawn by the LT1054 might affect other circuits through supply coupling.
In addition to being the output terminal, VOUT is tied to the substrate of the device. Special care must be taken in
LT1054 circuits to avoid making VOUT positive with respect to any of the other terminals. For circuits with the output
load connected from Vee to VOUT or from some external positive supply voltage to VOUT, an external transistor must
be added (see Figure 14). This transistor prevents VOUT from being pulled above GND during start up. Any small
general-purpose transistor such as a 2N2222 or a 2N2219 device can be used. Resistor R1 should be chosen to
provide enough base drive to the external transistor so that it is saturated under nominal output voltage and maximum
output current conditions.
R1 s
(lvouTI) ~
~I;:=':..:.!...-
OUT
(4)
~TEXAS
8-180
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
APPLICATION INFORMATION
2
3
-=-
4
8
FB/SO
VCC
CAP+
OSC
LT1054
GNO
CAP-
7
6
VREF
-=5
VOUT
~COUT
Pin numbers shown are for the P package.
Figure 14. Circuit With Load Connected from Vce to VOUT
The voltage reference (Vref) output provides a 2.5-V reference point for use in LT1054-based regulator circuits.
The temperature coefficient (TC) of the reference voltage has been adjusted so that the TC of the regulated
output voltage is near zero. As seen in the typical performance curves, this requires the reference output to have
a positive TC. This non-zero drift is necessary to offset a drift term inherent in the internal reference divider and
comparator network tied to the feedback terminal. The overall result of these drift terms is a regulated output
that has a slight positive TC at output voltages below 5 V and a slight negative TC at output voltages above 5 V.
For regulator feedback networks, reference output current should be limited to approximately 60~. Vref draws
approximately 100 ~ when shorted to ground and does not affect the internal reference/regulator. This terminal
also can be used as a pullup for LT1054 circuits that require synchronization.
CAP+ is the positive side of input capacitor CIN and is alternately driven between Vee and ground. When driven
to Vee, CAP+ sources current from Vee. When driven to ground, CAP+ sinks current to ground. CAP- is the
negative side of the input capacitor and is driven alternately between ground and VOUT. When driven to ground,
CAP- sinks current to ground. When driven to VOUT, CAP- sources current from COUTo In all cases, current flow
in the switches is unidirectional, as should be expected when using bipolar switches.
The OSC can be used to raise or lower the oscillator frequency or to synchronize the device to an external clock.
Internally, OSC is connected to the oscillator timing capacitor (Ct '" 150 pF), which is alternately charged and
discharged by current sources of ±7 ~, so that the duty cycle is approximately 50%. The LT1054 oscillator is
designed to run in the frequency band where switching losses are minimized. However, the frequency can be
raised, lowered, or synchronized to an external system clock if necessary.
The frequency can be increased by adding an external capacitor (C2 in Figure 15) in the range of 5 pF - 20 pF
from CAP+ to OSC. This capacitor couples a charge into Ct at the switch transitions. This shortens the charge
and discharge time and raises the oscillator frequency. Synchronization can be accomplished by adding an
external pullup resistor from OSC to Vref. A 20-kn pullup resistor is recommended. An open-collector gate or
an NPN transistor can then be used to drive OSC at the external clock frequency as shown in Figure 15.
The frequency can be lowered by adding an external capacitor (C1 in Figure 15) from OSC to ground. This
increases the charge and discharge times, which lowers the oscillator frequency.
~TEXAS
.
INSTRUMENTS
POST OFFICE BOX 1155303 • DALLAS, TEXAS 75265
8-181
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
APPLICATION INFORMATION
r-------------------~
:I
I
FB/SO
VCC
CAP+
OSC
2
+
3
8
VIN
+C2
I
I
7
LT1054
GNO
4
' - - - - - I CAP-
VOUT
T
Pin numbers shown are for the P package.
Figure 15. External Clock System
The feedback/shutdown (FB/SO) terminal has two functions. Pulling FB/SO below the shutdown threshold
(., 0.45 V) puts the device into shutdown. In shutdown, the reference/regulator is turned off and switching stops.
The switches are set such that both CIN and COUT are discharged through the output load. Quiescent current
in shutdown drops to approximately 100 J.LA. Any open-collector gate can be used to put the LT1054 into
shutdown. For normal (unregulated) operation, the device will restart when the external gate is shut off. In
LT1 054 circuits that use the regulation feature, the external resistor divider can provide enough pulldown to keep
the device in shutdown until the output capacitor (COUT) has fully discharged. For most applications where the
LT1 054 is run intermittently, this does not present a problem because the discharge time of the output capacitor
is short compared to the off time of the device. In applications where the device has to start up before the output
capacitor (COUT) has fully discharged, a restart pulse must be applied to FB/SO of the LT1054. Using the circuit
shown in Figure 16, the restart signal can be either a pulse (tp > 100 JIS) or a logic high. Diode coupling the restart
signal into FB/SO allows the output voltage to rise and regulate without overshoot. The resistor divider R3IR4
shown in Figure 16 should be chosen to provide a signal level at FB/SO of 0.7 V - 1.1 V.
FB/SO is also the inverting input of the LT1054 error amplifier and, as such, can be used to obtain a regulated
output voltage.
~TEXAS
8-182
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
APPLICATION INFORMATION
VIN
R3
2
R4
CIN
10l1F
Tantalum
~~
Restart
3
8
FB/SD
VCC
CAP+
OSC
LT1054
GND
VREF
CAP-
VOUT
:.2~
-::-
7
6
R1
5
R2
-::-
4
Shutdown
For example: To get Vo
=-5 V, referenced to the ground terminal of the LT1054
VOUT
C1
COUT
+T 1OOl1F
Tantalum
-b
R2=R1(
Whara:
IVOUTI
+1)=20kn(
1-5 VI
+1) = 102.6 knt
_ 40 mV
2.~V - 40 mV
V~EF
=
R1 20 kO
VREF 2.5 V Nominal
=
t
Choose the closest 1% value.
Pin numbers shown are for the P package.
Figure 16. Basic Regulation Configuration
regulation
The error amplifier of the LT1054 drives the pnp switch to control the voltage across the input capacitor (CIN),
which determines the output voltage. When the reference and error amplifier of the LT1 054 are used, an external
resistive divider is all that is needed to set the regulated output voltage. Figure 16 shows the basic regulator
configuration and the formula for calculating the appropriate resistor values. R1 should be 20 kQ or greater
because the reference current is limited to ±1 00 ~. R2 should be in the range of 100 kQ to 300 k.Q. Frequency
compensation is accomplished by adjusting the ratio of CIN to COUTo
For best results, this ratio should be approximately 1 to 10. CapaCitor C1, required for good load regulation,
should be 0.002 IlF for all output voltages.
The functional block diagram shows that the maximum regulated output voltage is limited by the supply voltage.
For the basic configuration, IVOUT I referenced to the ground terminal of the LT1 054, must be less than the total
of the supply voltage minus the voltage loss due to the switches. The voltage loss versus output current due
to the switches can be found in the typical performance curves. Other configurations, such as the negative
doubler, can provide higher voltages at reduced output currents.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265
8-183
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D- FEBRUARY 1990- REVISED JULY 1999
APPLICATION INFORMATION
capacitor selection
While the exact values of CIN and COUT are non-critical, good-quality low-ESR capacitors, such as solid
tantalum are necessary to minimize voltage losses at high currents. For CIN, the effect of the ESR of the
capacitor is multiplied by four, since switch currents are approximately two times higher than output current.
Losses occur on both the charge and discharge cycle, which means that a capacitor with 1 n of ESR for CIN
has the same effect as increasing the output impedance of the LT1 054 by 4 n. This represents a significant
increase in the voltage losses; COUT is alternately charged and discharged at a current approximately equal
to the output current. The ESR of the capacitor causes a step function to occur in the output ripple at the switch
transitions. This step function degrades the output regulation for changes in output load current and should be
avoided. A technique used to gain both low ESR and reasonable cost is to parallel a smaller tantalum capacitor
with a large aluminum electrolytic capacitor.
output ripple
The peak-to-peak output ripple is determined by the output capacitor and the output current values.
Peak-to-peak output ripple is approximated as shown:
tlV
lOUT
2 fC OUT
(5)
where:
tN = pop ripple
f05C = oscillator frequency
For output capacitors with significant ESR, a second term must be added to account for the voltage step at the
switch transitions. This step is approximately equal to:
(21 0UT) (ESR of COUT)
(6)
power dissipation
The power dissipation of any LT1 054 circuit must be limited so that the junction temperature of the device does
not exceed the maximum junction temperature ratings. The total power dissipation is calculated from two
components, the power loss due to voltage drops in the switches, and the power loss due to drive current losses.
The total power dissipated by the LT1054 is calculated as shown.
P "" (Vcc
-
I VOUT I ) lOUT
+ (V CC) (lOUT) (0.2)
(7)
where both Vee and VOUT are referenced to ground. The power dissipation is equivalent to that of a linear
regulator. Limited power-handling capability of the LT1054 packages causes limited output-current
requirements or steps can be taken to dissipate power external to the LT1054 for large input or output
differentials. This is accomplished by placing a resistor in series with CIN as shown in Figure 17. A portion of
the input voltage is dropped across this resistor without affecting the output regulation. Since switch current is
approximately 2.2 times the output current and the resistor causes a voltage drop when CIN is both charging
and discharging, the resistor chosen is as shown:
RX
= VX/(4.4
lOUT)
where:
Vx "" VCC - [(LT1054 voltage loss) (1.3)
+
I vouTI]
(8)
and lOUT =maximum required output current. The factor of 1.3 allows some operating margin for the LT1 054.
~1EXAS
8-184
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
APPLICATION INFORMATION
When using a 12-V to -5-V converter at 100-mA output current, calculate the power dissipation without an
external resistor.
P
= (12 V - 1-5 V I ) (100 mA) + (12 V) (100 mA) (0.2)
P
=
700 mW
+
=
240 mW
(9)
940 mW
8
FBISD
VCC
Rx 2
OSC
CAP+
7
LT1054
CIN
3
+
GND
VREF
CAP-
VOUT
6
R1
5
R2
"::"
4
VOUT
CoUT
"f
C1
Pin numbers shown are for the P package.
Figure 17. Power-Dlsslpatlon-Limitlng Resistor in Series with CIN
At RaJA of 130°C/W for a commercial plastic device, a junction temperature rise of 122°C is seen. The device
exceeds the maximum junction temperature at an ambient temperature of 25°C. To calculate the power
dissipation with an external resistor (RX), determine how much voltage can be dropped across Rx. The
maximum voltage loss of the LT1054 in the standard regulator configuration at 100 mA output current is 1.6 V.
Vx
=
12 V - [(1.6 V) (1.3)
Rx
=
4.9 Vj(4.4) (100 mA)
+
1-5 VI]
=
4.9 V
and
=
11 Q
(10)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 65530G • DALLAS, TEXAS 75265
8-185
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
APPLICATION INFORMATION
=
The resistor reduces the power dissipated by the LT1054 by (4.9 V) (100 rnA) 490 mW. The total power
dissipated by the LT1054 is equal to (940 mW - 490 mW) 450 mW. The junction temperature rise is 58°C.
Although commercial devices are functional up to a junction temperature of 125°C, the specifications are tested
to a junction temperature of 100°C. In this example, this means limiting the ambient temperature to 42°C. To
allow higher ambient temperatures, the thermal resistance numbers for the LT1054 packages represent
worst-case numbers with no heat sinking and still air. Small clip-on heat sinks can be used to lower the thermal
resistance of the LT1054 package. Airflow in some systems helps to lower the thermal resistance. Wide PC
board traces from the LT1054 leads help to remove heat from the device. This is especially true for plastic
packages.
=
10V
1N4002
100 kn
8
VCC
FB/SO
2
7
OSC
CAP+
LT1054
3
+
511FT
6
GNO
VREF
CAP-
VOUT
-:;
4
Tach
5
Motor
-:;
NOTE: Motor-Tach Canon CKT26-T5-3SAE
Pin numbers shown are for the P package.
Figure 18. Motor Speed Servo
2
3
+
10l1F
FB/sO
VCC
CAP+
OSC
LT1054
8
I----e-Y,N
21tf
+
7
T
6
GNO
VREF
CAP-
5
VOUT 1---41>--- -VOUT
100 Itf
-:;
4
Pin numbers shown are for the P package.
Figure 19. Basic Voltage Inverter
~TEXAS
8-186
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
100kn
Speed Control
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
APPLICATION INFORMATION
VIN
2
+
3
-
Vcc
CAP+
;::::::r
4
1
8
1
' - - FBISD
OSC
LT1054
GND
7
r----
f
211F
6
R1
5
20kn
VREF
R2
CAP-
VOUT
VOUT -----<
+1(
1\
+ II
1\
R2 = R1 (
IVOUTI
VREF _ 40 mV
+ 1)
= 20 kO (IVour!
1.21 V
+ 1)
2
Pin numbers shown are for the P package.
Figure 20. Basic Voltage Inverter/Regulator
8
FBISD
VCC
CAP+
OSC
7
2
+
10 !1F
3
4
VIN
LT1054
6
GND
VREF
CAP-
VOUT
5
=-3.5 V TO -15 V
=2 VIN + (LT1054 Voltage Loss) + (QX saturation Voltage)
VOUT
Pin numbers shown are for the P package.
Figure 21. Negative-Voltage Doubler
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
8-187
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
APPLICATION INFORMATION
VIN
3.5 Vto 15 V
1N4001
1N4001
+
+
10l1F
VOUT
8
FB/sD
VCC
CAP+
osc
2
3
VIN=3.5VT015V
VOUT ~ 2 VIN - (VL + 2 V Diode)
VL = LT1054 Voltage Loss
4
LT1054
7
+
I211F
6
GND
VREF
CAP-
VOUT
5
Pin numbers shown are for the P package.
Figure 22. Positive-Voltage Doubler
VIN
3.5 Vto 15 V
2
+ 1Ol1F
10l1F
3
+
"::"
4
FB/SD
VCC
CAP+
OSC
LT1054 #1
GND
VREF
CAP-
VOUT
8
FB/SD
7
2
VOUT
SET
+
6
10 j.LF
3
"::" 4
5
+
VCC
OSC
CAP+
LT1054 #2
GND
VREF
CAP-
VOUT
1N4002
1N4002
. -________~----------~----~~~---- VOUT
lOUT'" 100 rnA MAX
1N4002
+J 100l1F
VIN = 3.5 V to 15 V
VOUT MAX ~-2 VIN + [LT1054 Voltage Loss +2 (VDlode)]
R2 = R1 (
IVOUTI
40
VREF
-2--
rn
V
+ 1)
= R1 (IVOUTI
1.21 V
+ 1)
~
Pin numbers shown are for the P package.
Figure 23. 100-mA Regulating Negative Doubler
~TEXAS
8-188
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8
HP5082-2810
CAP+of
LT1054 #1
20kO
5
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
APPLICATION INFORMATION
VI
3.5 Vto 15 V
1N4001
1N4001
2
VCC
CAP+
OSC
7
LT1054
3
-=-
8
FB/SO
GNO
6
VREF
100 JlF
4
5
CAP-
VOUT
1N4001
~
1N4001
VI = 3.5 Vlo 15 V
+Vo ~ 2 VIN - (VL + 2 VOlode) -yo ~ -2 VI + (VL + 2 VOlode)
VL = LT1054 Voltage Loss
l'°O~
1N4001
J
-Yo
Pin numbers shown are for the P package.
Figure 24. Dual-Output Yoltage Doubler
VI=5V
51!F
T
+
1N914
FB/SO
2
3
+
10l!F
-=-
4
CAP+
8
VCC
OSC
LT1054 #1
GNO
VREF
CAP-
VOUT
T
+
7
1N914
VO=+12V
lo=25mA
100I!F
+
6
2
5
3
4
8
FB/SO
VCC
CAP+
OSC
LT1054 #2
GNO
CAP-
7
6
VREF
VOUT
20kO
5
VO=-12V
lo=25mA
100l!F ' }
Pin numbers shown are for the P package.
Figure 25.
s-y to ±12-Y Converter
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
!Ha9
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D- FEBRUARY 1990 - REVISED JULY 1999
APPLICATION INFORMATION
5V
10kO
Input TTL or
CMOS Low
for On
+
T
400
2N2907
---t1---'VVI.r-i
10kO
ZeroTrim
10kO
10 l1F
-=-
301kO
0.02211F
VOUT
200kO
.--------,8
FB/sD
Vee
2
OSC
.------1 CAP+
1Ol1F
+
3
-=-
4
CAP-
rr:;-3kO
LT1054 #1
GND
7
5V
VREF
VOUT
6
5
-
2N2222
Tantalum
Pin numbers shown are for the P package.
Figure 26. Strain-Gage Bridge Signal Conditioner
~TEXAS
8-190
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AdJust Gain Trim
For 3 V Out
From Full-Scale Bridge
Output of 24 mV
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
APPLICATION INFORMATION
V,
3.S VtoS.S V
-
20kO
1
2
a...J
,...1
1 JLF;::::;
~, 1N914
(ALL)
."
1
2
-=10JLF ;;:
-
::::;r+
3
8
FB/SD
VCC
CAP+
OSC
-
LT10S4
VREF
CAP-
VOUT
- 4
-
r-
7
SJLFf
R1
2OkO
6
GND
3
S
-=-
O.OO2JLF;;:
r:
VCC
r-
CAP+
OSC
r--
GND
VREF
r--
CAP-
S
VOUT f--
LTC1044
4
7
6
R2
12SkO
] 1~f.
+
R2
100 JLF
125 kO;::
r:
3kO
~
1NS817
8
FB/sD
~~
~~
Vo
-=-
1N914
-=-
V, =3.SVtoS.SV
VO=5V
'0 MAX=50 mA
R2 = R1 (
IVOuTI
+ 1) = R1 (IVOUTI
40 mV
1.21 V
VREF _
2
+ 1)
Pin numbers shown are for the P package.
Figure 27. 3.5-Y to 5-Y Regulator
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-191
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
APPLICAnON INFORMATION
12V
51lF
1
r1i+
~
2
3
.r-
100
112W
~~
8
FBISD
VCC
CAP+
OSC
LT1054 #1
OND
t--
VCC
0.0021lF
::: ::::
39.2kn
5
+
R2
200 kn
Vour I - -
r-- ~~
HP5082·2810
7
CAP+
+
;:::~ 10llF
R1
6
8
FBISD
100
112W 2
7
VREF
CAP-
1
t--
OSC
LT1054 #2
r3
OND
4
6
VREF
20 kn
5
VOUTil
CAP-
10llF
VO=-oV
I0=0400 rnA
, .... L..-
R2
= R1
(
IVOUTI
40 V
rn
vREF
+ 1)
-2--
= R1
(IVOUTI
1.21 V
+ 1)
Pin numbers shown are for the'P package.
Figure 28. Regulating 20G-mA + 12-V to -S-V Converter
15V
11
2
+
3
10llF
FBISD
VCC
CAP+
OSC
LT1054
OND
VREF
CAP-
VOUT
8
7
6
uv{
LT1004-2.5
13
20kn
5
-=Vo = - VI (Programmed)
Pin numbers shown are for the P package.
Figure 29. Digitally Programmable Negative Supply
~1ExAs
8-192
12
-::-
-::-
4
}
16
20 kn
INSTRUMENTS
POST OFFICE BOX 856303 • OALLAS. TEXAS 75285
Digital
Input
LT1054
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATORS
SLVS033D - FEBRUARY 1990 - REVISED JULY 1999
APPLICATION INFORMATION
VI=5V
5OkO
FB/SO
B
VCC
2
VOBV ~~-e--~----~--i~-------r------~ CAP+
OSC
+
LT1054
10 kO
3
O·03I1F 10 kO
GNO
VREF
100 !IF
T
-=-
4
5V
5.5kQ
CAP-
7
6
5
VOUT
10 kO
-=-
2.5 kO
0. 111F
T
Pin numbers shown are for the P package.
Figure 30. Positive Doubler With Regulation (5·V to aN Converter)
VI
3.5Vlo 15 V
vee
FB/SO
2
CAP+
+
10llF
3
OSC
LT1054
GNO
B
211F
+~
7
6
R1
6OkO
VREF
100IlF
-=-
4
__-----I
CAP-
5
VOUT
I---+---l~
I J..
1N4001
+
0.00211F
R2
1 MQ
VI = 3.5 Vlo 15 V
Vo MAX ~ 2 VIN + (VL + 2 VOlode)
VL = LT1054 Voltage Loss
R2 = R1 (
IVOUTI
40
VREF
-2- -
V
+ 1)
= R1
m
(IVou~ +
1.21 V
1)
Pin numbers shown are for the P package.
Figure 31. Negative Doubler With Regulator
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-193
8-194
General Information (Vol. 1)
I Linear Voltage Regulators
IIJ
Shunt Regulators
Precision Virtual Grounds
•
Mechanical Data
•
General Information (Vol. 2)
..
Processor PS Controllers
•
Switching PS and DC/DC Converters
..
MOSFET Drivers
..
Supervisors
Mechanical Data
General Information (Vol. 3)
Power Distribution Switches
LED Drivers
Voltage Rail Splitters
Special Functions
Mechanical Data
9-1
II
s:
oen
'TI
m
-I
en
....:e
_a
(')
::::T
CD
tn
9-2
TPS2811, TPS2812, TPS2813, TPS2814, TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
TPS2811, TPS2812, TPS2813 ••• 0, P, AND PW
PACKAGES
(TOP VIEW)
• Industry-Standard Driver Replacement
• 25-ns Max Rise/Fa" Times and 40-ns Max
Propagation Delay -1-nF Load, Vee = 14 V
• 2-A Peak Output Current, Vee = 14 V
• 5-!IA Supply Current -Input High or Low
• 4-V to 14-V Supply-Voltage Range; Internal
Regulator Extends Range to 40 V (TPS2811,
TPS2812, TPS2813)
REG_IN 0 8 REG_OUT
liN
2
7 lOUT
GND
21N
3
4
6
5
Vee
20UT
TPS2814 ••• 0, P, AND PW PACKAGES
(TOP VIEW)
• -40°C to 125°C Ambient-Temperature
Operating Range
description
l 1 N 1 0 8 GND
11N2
2
7 10UT
21N1
21N2
The TPS28xx series of dual high-speed MOSFET
drivers are capable of delivering peak currents of
2 A into highly capacitive loads. This performance
is achieved with a design that inherently
minimizes shoot-through current and consumes
an order of magnitude less supply current than
competitive products.
3
4
6
5
Vee
20UT
TPS2815 ••• 0, P, AND PW PACKAGES
(TOP VIEW)
l 1 N 1 0 8 GND
11N2
2
7 10UT
The TPS2811, TPS2812, and TPS2813 drivers
21N1
3
6 Vee
include a regulator to allow operation with supply
21N2 4
5 20UT
inputs between 14 V and 40 V. The regulator
output can power other Circuitry, provided power
dissipation does not exceed package limitations. When the regulator is not required, REG_IN and REG_OUT
can be left disconnected or both can be connected to Vee or GND.
The TPS2814 and the TPS2815 have 2-input gates that give the user greater flexibility in controlling the
MOSFET. The TPS2814 has AND input gates with one inverting input. The TPS2815 has dual-input NAND
gates.
TPS28xx series drivers, available in 8-pin PDIP, SOIC, and TSSOP packages and as unmounted ICs, operate
over a ambient temperature range of -40°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
-40oe
to
125°e
INTERNAL
REGULATOR
LOGIC FUNCTION
SMALL
OUTLINE
(D)
PLASTIC
DIP
(P)
TSSOP(PW)
CHIP
FORM
(V)
Yes
Dual inverting drivers
Dual noninverting drivers
One inverting and one noninverting driver
TPS28110
TPS2812D
TPS2813D
TPS2811P
TPS2812P
TPS2813P
TPS2811PWLE
TPS2812PWLE
TPS2813PWLE
TPS2811V
TPS2812Y
TPS2813Y
Dual 2-input AND drivers, one inverting input on
each driver
Dual2-input NAND drivers
TPS2814D
TPS2814P
TPS2814PWLE
TPS2814Y
No
TPS2815D
TPS2815P
TPS2815PWLE
TPS2815Y
The 0 package IS available taped and reeled. Add R suffix to deVice type (e.g., TPS2811 DR). The ,PW package is only available left-end
taped and reeled and is indicated by the LE suffix on the device type (e.g., TPS2811PWLE).
~TEXAS
INSTRUMENTS
POST OFFICE BOX 855303 • DALlAS. TEXAS 75265
CoPYright@ 1997, Texas Instruments Incorporated
TPS2811, TPS2812, TPS2813, TPS2814,TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS132D - NOVEMBER 1995 - REVISED NOVEMBER 1997
functional block diagram
regulator diagram (TPS2811, TPS2812,
TPS2813 only)
TPS2811
REG_IN
11N
J.-i
Regulator
I~: ~~~_OUT
-=2=---____
4
21N
GND~
1f
7
10UT
1f
5
20UT
7.5 g
"""N\r- REG_OUT
L -_ _ _ _ _...
TPS2812
REG_IN
11N
J.-i
Regulator
I
:
REG_OUT
.--.------''- Vee
2
10UT
21N -,4,--"---~_
~--'--....-----
20UT
GND 3
input stage diagram
TPS2813
REG_IN
11N
J.-i
Regulator
I
Vee
REG_OUT
..---.------''- Vee
-=2=---___-+-f-,
10UT
IN
20UT
GND
...-__-+--+---+-
To Drive
Stage
TPS2814
.--.------''- Vee
11N1
11N2 _2_",-,-_
10UT
21N1
21N2 ----,..,L--._
20UT
output stage diagram
Vee
GND~
TPS2815
11N1
11N2
21N1
21N2
,--_...!6,-
-2-------Ir-S:
-=--------I~
3
4
Vee
10UT
~
~
OUT
20UT
GND~
~TEXAS
9-4
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
TPS2811, TPS2812, TPS2813, TPS2814, TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS132D - NOVEMBER 1995 - REVISED NOVEMBER 1997
TPS28xxY chip Information
This chip, when properly assembled, displays characteristics similar to those of the TPS28xx. Thermal
compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be
mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(S)
-=
-=
-=
-=
-=-=
-=
-=
REG_IN
(1)
(2)
11N
(4)
TPS2S11Y
TPS2S12Y
TPS2S13Y
REG_OUT
(7)
10UT
(6)
VCC
(5)
21N
20UT
(3)
-=
-=
GND
-=
-=
-=
-=-=
-=
21N1
--
21N2
11N1
(1)
(7)
10UT
(2)
11N2
(6)
(3)
-=
TPS2S14Y
VCC
(5)
(4)
20UT
(S)
-=-=--=
-=--
GND
(1)
(7)
11N1
10UT
(2)
11N2
(3)
TPS2815Y
21N1
VCC
(5)
(4)
-=
-=-=
-=
-=
-=-
(6)
20UT
21N2
(S)
GND
CHIP THICKNESS: 15 MILS TYPICAL
-=
-
-=
BONDING PADS: 4 x 4 MILS MINIMUM
14
47
.1
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1
TJmax OPERATING TEMPERATURE
=150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
~TEXAS
INSTRUMENTS
POST OFF'CE BOX 655303 • DALLAS, TEXAS 75265
9-5
TPS2811,TPS2812,TPS2813,TPS2814,TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS '
SLVS132D - NOVEMBER 1996 - REVISED NOVEMBER 1997
Terminal Functions
TPS2811, TPS2812, TPS2813
TERMINAL NUMBERS
TERMINAL
NAME
TPS2811
Dual Inverting
Drivers
TPS2812
Dual Nonlnvertlng
Drivers
TPS2813
Complimentary
Drivers
DESCRIPTION
REG_IN
1
1
1
Regulator input
liN
2
2
2
Input 1
GND
3
3
3
Ground
21N
4
4
4
5=21N
5=21N
5=21N
20UT
6
6
6
7= liN
7= liN
7= liN
8
8
8
VCC
lOUT
REG OUT
Input 2
Output 2
Supply voltage
Output 1
Regulator output
TPS2814, TPS2815
TERMINAL NUMBERS
TERMINAL
NAME
TPS2814
Dual AND Drivers with Single
Inverting Input
TPS2815
Dual NAND Drivers
llNl
1
1
l1N2
2
Inverting Input 2 of driver 1
l1N2
-
2
Nonlnverting input 2 of driver 1
21Nl
3
3
Noninverting input 1 of driver 2
21N2
4
-
Inverting Input 2 of driver 2
21N2
-
4
20UT
5 = 21Nl .21N2
5 = 21Nl • 21N2
DESCRIPTION
Noninverting Input 1 of driver 1
Noninverting input 2 of driver 2
Output 2
6
6
lOUT
7 = llNl .11N2
7=1INl.lIN2
Output 1
GND
8
8
Ground
VCC
Supply voltage
DISSIPAnON RATING TABLE
PACKAGE
TAS25°C
POWERRAnNG
DERAnNG FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA=85°C
POWER RATING
P
1090mW
8.74mW/"C
697mW
566mW
D
730mW
5.84mW/"C
487mW
380mW
PW
520mW
4.l7mW/"C
332mW
270mW
~1EXAS
9--6
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2811, TPS2812, TPS2813, TPS2814, TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS1 320 - NOVEMBER 1995 - REVISED NOVEMBER 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Regulator input voltage range, REG_IN .............................................. -0.3 V to 42 V
Supplyvoltage,Vee .............................................................. -0.3Vt015V
Input voltage range, 11N, 21N, 11N1, 11N2, 11N2, 21N1, 21N2, 21N2 ....................... -0.3 V to Vee
Continuous regulator output current, REG_OUT ............................................. 25 mA
Continuous output current, 10UT, 20UT ................................................. ±100 mA
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating ambienttemperature range, TA .......................................... -40°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds .... . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to device GND pin.
recommended operating conditions
UNIT
MIN
MAX
Regulator input voltage range
8
40
V
Supply voltage, VCC
4
14
V
-0.3
0
VCC
20
mA
-40
125
°c
Input voltage, llNl, l1N2, l1N2, 21Nl, 21N2, 21N2, liN, 21N
Continuous regulator output current, REG OUT
Ambient temperature operating range
V
TPS28xx electrical characteristics over recommended operating ambient temperature range,
Vee = 10 V, REG_IN open for TPS2811/12113, CL = 1 nF (unless otherwise noted)
Inputs
PARAMETER
TYP't
MAX
VCC=5V
3.3
4
V
VCC=10V
5.8
9
V
8.3
13
V
TEST CONDITIONS
Positive-going input threshold voltage
MIN
VCC=14V
Negative-going input threshold voHage
UNIT
VCC=5V
1
1.6
VCC=10V
1
4.2
V
VCC= 14 V
1
6.2
V
-1
0.2
1
!iA
5
10
pF
MAX
Input hysteresis
VCC=5V
Input current
InpulS=OVorVCC
V
1.6
Input capacitance
V
t Typlcals are for TA = 25°C unless otherwise noted.
outputs
PARAMETER
High-level output voltage
TEST CONDmONS
MIN
TYP't
10=-1 mA
9.75
9.9
8
9.1
10=-I00mA
Peak output current
V
0.18
0.25
10=I00mA
1
2
VCC=10V
2
10=1 mA
Low-level output voHage
UNIT
V
A
t Typlcals are for TA = 25°C unless otherwise noted.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9-7
TPS2811,TPS2812, TPS2813, TPS2814, TPS2815
DUAL HIGH·SPEED MOSFET DRIVERS
SLVS132D - NOVEMBER 1995 - REVISED NOVEMBER 1997
regulator (TPS2811/281212813 only)
PARAMETER
MIN
TYP't
MAX
Output voltage
14 S REG_IN S 40 V,
TEST CONDITIONS
OSloS20mA
10
11.5
13
Output voltage In dropout
10=10mA,
REG_IN = 10V
9
9.6
MIN
TYP't
MAX
0.2
5
40
100
UNIT
V
V
t Typlcals are for TA = 25°e unless otherwise noted.
supply current
PARAMETER
TEST CONDITIONS
Supply current into Vee
Inputs high or low
Supply current into REG IN
REG_IN = 20 V,
REG OUT open
UNIT
IIA
IIA
t TYPlcals are for TA = 25°e unless otherwise noted.
TPS28xxY electrical characteristics at TA = 25°C, Vee = 10 V, REG_IN open for TPS2811/12/13,
CL 1 nF (unless otherwise noted)
=
inputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Vee=5V
3.3
V
Vee=10V
5.8
V
Vee=14V
8.2
V
Vee=5V
1.6
V
Vee=10V
3.3
V
Vee=14V
4.2
V
Input hysteresis
Vee=5V
1.2
V
Input current
Inputs = 0 V or Vee
0.2
IIA
5
pF
Positive-going input threshold voltage
Negative-going input threshold voltage
Input capacitance
outputs
PARAMETER
TEST CONDITIONS
High-level output voltage
MIN
9.9
10=-100mA
9.1
Peak output current
MAX
10= 100mA
1
Vee=10.5V
2
UNIT
V
0.18
10=1 mA
LOW-level output voltage
TYP
10=-1 mA
V
A
regulator (TPS2811, 2812, 2813)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output voltage
14SREG IN S40V,
OSIOS20mA
11.5
V
Output voltage In dropout
10=10mA,
REG:...IN= 10V
9.6
V
power supply current
PARAMETER
TEST CONDITIONS
Supply current into Vee
Inputs high or low
Supply current Into REG IN
REG IN=20V,
TYP
0.2
REG OUT open
-!I11EXAS
9-8
MIN
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
40
MAX
UNIT
IIA
IIA
TPS2811, TPS2812,TPS2813, TPS2814,TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVSl32D- NOVEMBER 1995- REVISED NOVEMBER 1997
switching characteristics for all devices over recommended operating ambient temperature range,
REG_IN open for TPS2811 112/13, CL = 1 nF (unless otherwise specified)
TEST CONDITIONS
PARAMETER
MIN
TYP
MAX
14
25
Vee=10V
15
30
Vee=5V
20
35
Vee=14V
15
25
Vee=10V
15
30
Vee=5V
18
35
Vee=14V
25
40
Vee=10V
25
45
Vee=5V
34
50
Vee=14V
24
40
Vee=10V
26
45
Vee=5V
36
50
Vee = 14V
tr
tf
tPHL
tPLH
Rise time
Fall time
Prop delay time high-to-Iow-Ievel output
Prop delay time low-to-high-Ievel output
UNIT
ns
ns
ns
ns
PARAMETER MEASUREMENT INFORMATION
TPS2811
8
+
TO.1I1F T4.711F
--
Input
2
7
3
6
4
5
--
Output
500
NOTE A. Input rise and fall times should be S10 ns for accurate measurement of ac parameters.
Figure 1. Test Circuit For Measurement of Switching Characteristics
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
9-9
TPS2811,TPS2812, TPS2813, TPS2814,TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS132D - NOVEMBER 1995 - REVISED NOVEMBER 1997
PARAMETER MEASUREMENT INFORMATION
TPS2811
8
/
G-10Vdc
2
7
3
6
4
5
xOUT
Current
Loop
VCC
10 V
-::-
T-=-
4.711F
Figure 2. Shoot-through Current Test Setup
11N
~50%
\50%
,
OV
, -1
,
'
,
10UT
tPHL
,
I
,4
I+-tf
I
90%~5O%
10%
I
I
I
I
---+1 ~tr
I,
I
I
50%Ji;90%
10% - - OV
I
tPLH
~
,4
I~
I
Figure 3. Typical Timing Diagram (TPS2811)
TYPICAL CHARACTERISTICS
Tables of Characteristics Graphs and Application Information
typical characteristics
FIGURE
PAGE
Rise time
Supply voltage
4
10
Fall time
Supply voltage
5
10
Propagation delay time
Supply voltage
6,7
10
Supply voltage
8
11
Load capacitance
9
11
Ambient temperature
10
11
Input threshold voltage
Supply voltage
11
11
vs PARAMETER 2
PARAMETER
Supply current
Regulator output voltage
Regulator input voltage
12,13
12
Regulator quiescent current
Regulator input voltage
14
12
Peak sourca current
Supply voltage
15
12
Peak sink current
Supply voltage
16
13
Input voltage, high-to-Iow
17
13
Input voltage, low-to-hlgh
18
13
Shoot-through current
~TEXAS
INSTRUMENTS
9-10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2811, TPS2812, TPS2813, TPS2814, TPS2815
DUAL HIGH·SPEED MOSFET DRIVERS
SLVS132D - NOVEMBER 1995 - REVISED NOVEMBER 1997
TYPICAL CHARACTERISTICS
Tables of Characteristics Graphs and Application Information (Continued)
general applications
PARAMETER
vs PARAMETER 2
Switching test circuits and application information
Voltage of 10UT vs 20UT
Time
I Low-to-high
I High-to-Iow
FIGURE
PAGE
19,20
15
21,23,25
16,17
22,24,26
16,17
FIGURE
PAGE
27
17
28,30
18
29,31
18
FIGURE
PAGE
circuit for measuring paralleled switching characteristics
PARAMETER
vs PARAMETER 2
Switching test circuits and application information
Input voltage vs output voltage
Time
I Low-to-high
I High-to-Iow
Hex-1 to Hex-4 application information
PARAMETER
vs PARAMETER 2
Driving test circuit and application information
Drain-source voltage vs drain current
Time
Drain-source voltage vs gate-source voltage at turn-on
Time
Drain-source voltage vs gate-source voltage at turn-off
Time
32
19
Hex-l size
33
20
Hex-2 size
36
20
Hex-3size
39
21
Hex-4size
41
22
Hex-4 size parallel drive
45
23
Hex-l size
34
20
Hex-2size
37
21
Hex-3size
40
21
Hex-4size
43
22
Hex-4 size parallel drive
46
23
Hex-l size
35
20
Hex-2size
38
21
Hex-3size
42
22
Hex-4size
44
22
Hex-4 size parallel drive
47
23
synchronous buck regulator application
FIGURE
PAGE
3.3-V 3-A Synchronous-Rectified Buck Regulator Circuit
48
24
01 drain voltage vs gate voltage at turn-on
49
26
01 drain voltage vs gate voltage at turn-off
50
26
51,52,53
26,27
3A
54
27
5A
55
27
PARAMETER
01 drain voltage vs 02 gate-source voltage
vs PARAMETER 2
Time
Output ripple voltage vs inductor current
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
9'"11
TPS2811,TPS2812,TPS2813,TPS2814,TPS2815
DUAL HIGH.;SPEED MOSFET DRIVERS
SLVSl32D - NOVEMBER 1995 - REVISED NOVEMBER 1997
TYPICAL CHARACTERISTICS
RISE TIME
FALL TIME
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
22
eL=1 nF
20
.
c
18
TA=125°e
I
I
1=
:r
TA=75o e
16
TA=25°e
I
::
14
TA=-25 oe
12
10~~
5
__~~__~~__~~__~~
6
7
8
10~~~~~~~~~~~__~~
5
6
Vee - Supply Voltage - V
8
FigureS
PROPAGATION DELAY TIME,
HIGH-TQ-LOW-LEVEL OUTPUT
I
7
Vee - Supply Voltage - V
Figure 4
45
TA=-50oe
PROPAGATION DELAY TIME,
LOW-TQ-HIGH-LEVEL OUTPUT
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
.!
eL = 1 nF
~ r-....
""
~ ~r::: l'-. r--~ I" r:::: r.::
t"--. '""'-
'"'"
20
"
TA = 125°e
TA = 7~o{ jA = 25°e
I
I
~A=-50oe
TA=-25°e
15
5
6
7
15~~
8
9
10 11
12
Vee - Supply Voltage - V
13
14
5
6
Figure 6
Figure 7
~TEXAS
9-12
__~~__~~__~~__~~
7
8
9
10 11
12 13 14
Vee - Supply Voltage - V
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2811, TPS2812, TPS2813, TPS2814, TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS132D - NOVEMBER 1995 - REVISED NOVEMBER 1997
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
SUPPLY VOLTAGE
LOAD CAPACITANCE
16
14
c
E
I
12
~
10
::I
(J
aa.
2.5
c
g
2
I
C
~
1.5
~
8
a.
a.
::I
til
I
6
(J
(J
0.5
21"""''----+---t--
o
8
6
10
12
14
/'
o
V
Figure 8
Figure 9
INPUT THRESHOLD VOLTAGE
SUPPLY CURRENT
vs
vs
AMBIENT TEMPERATURE
SUPPLY VOLTAGE
1.2
9
CL=1 nF
Vee = 10 V
Duty Cycle = 50%
f = 100 kHz
1.19
1.18
j
I
>-
I
g
1.17
I'-...
TA
8
1.16
~
1.15
""",
1.14
=25°C
/'
>
I
II
............
2
0.5
1
1.5
CL - Loed Capacitance - nF
Vee - Supply Voltage - V
I
/
(J
4
1
/
E
::I
til
I
VCC=10V
f = 100 kHz
TA = 25°C
Duty Cycle = 50%
CL = 1 nF
I
~
!!
I
............ .....
fE.
'S
a.
1.13
.5
1.12
~
I
7
+ Threshold. /
6
5
. /"
4
3
2
~
/
V..,... V
/
V
/rhreshold
.... /
V
1.11
1.1
-00
-25
0
25
50
75
100
125
o
4
TA - Temperature - °C
Figure 10
6
10
12
8
VCC - Supply Voltage - V
14
Figure 11
:II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
9-13
TPS2811, TPS2812,TPS2813, TPS2814; TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS132D - NOVEMBER 1995 - REVISED NOVEMBER 1997
TYPICAL CHARACTERISTICS
REGULATOR OUTPUT VOLTAGE
vs
REGULATOR INPUT VOLTAGE
REGULATOR OUTPUT VOLTAGE
vs
REGULATOR INPUT VOLTAGE
14
13
13
>
12
i
11
T~=-~oe
I
~
I"
10
I
'$
!0
~
i51'
a:
9
6
5
"
CII
!
TA= 125°e
TA=25°e
~
0
8
~
"5
7
CII
II!
6
5
8
12 16 20 24 28 32
Regulator Input Voltage - V
36
V
4
40
L
4
V
2.5
c
I I
0
20
I
15
51'
Duty Cycle = 5%
2 t- TA=25°e
C
35
25
a:
f = 100 kHz
TA=25°e
21
.~
RL=0.50
TA=-55°e
40
30
I
C
fA
r-'
J'
§
TA=l25°e
1.5
0
~:::I
J
~
...
I
1""1\
'oj
V
14
PEAK SOURCE CURRENT
vs
SUPPLY VOLTAGE
!.....
I
0
12
Regulator Input Voltage - V
Figure 13
45
C
~
:::I
10
8
6
REGULATOR QUIESCENT CURRENT
vs
REGULATOR INPUT VOLTAGE
c::l.
L
/
Figure 12
50
~
L
~
I
I
4
9
A
~TA=125oe
10
:;
a.
'$
j
1/
4
11
I
CD
~
8
7
I
ITA=-55~e
TA=25°e
12
>
1/
J
RL=10kO
RL=10kO
./
V
V
~
~
V
.5
10
RL = 10 kO
5
o4
8
12
16
20
24
28
32
36
40
o
4
Regulator Input Voltage - V
12
8
10
Vee - Supply Voltage - V
Figure 15
Figure 14
~TEXAS
9-14
6
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
14
TPS2811,TPS2812,TPS2813,TPS2814,TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS132D- NOVEMBER 1995 - REVISED NOVEMBER 1997
TYPICAL CHARACTERISTICS
PEAK SINK CURRENT
vs
SUPPLY VOLTAGE
2.5
RL=0.5n
f= 100 kHz
Duty Cycle = 5%
TA=25°C
2
c
I
E
~
./
1.5
~
(J
.ot
~
..
.ot
01
11.
.5
V
o
4
I-"'"
-
V
V
6
~
10
12
8
VCC - Supply Voltage - V
14
Figure 16
SHOOT-THROUGH CURRENT
vs
INPUT VOLTAGE, LOW-TO-HIGH
SHOOT-THROUGH CURRENT
vs
INPUT VOLTAGE, HIGH-TO-LOW
6
6
I
5 -
VCC=10V
CL=O
TA=25°C
C
E
I
E
~
a
.c
Q
4
/
3
/
~
e
~g
/
2
/
.c
In
o
10
V
c
5
~
VCC=10V
CL=O
TA=25°C
/\
E
I
E
i
4
V\
(J
.c
Q
~
~
3
e
.c
t;"
'8
\"
2
/
.c
In
\
8
6
4
2
VI-Input Voltage, Hlgh-to-Low - V
o
o
I
V
o
Figure 17
\
-\
'\
2
4
6
8
VI-Input Voltage, Low-to-High - V
10
Figure 18
~TEXAS
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265
9-15
TPS2811, TPS2812, TPS2813, TPS2814, TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS1320 - NOVEMBER 1995 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
The TPS2811, TPS2812 and TPS2813 circuits each contain one regulator and two MOSFET drivers. The
regulator can be used to limit Vee to between 10 V and 13 V for a range of input voltages from 14 V to 40 V,
while providing up to 20 mA of dc drive. The TPS2814 and TPS2815 both contain two drivers, each of which
has two inputs. The TPS2811 has inverting drivers, the TPS2812 has noninverting drivers, and the TPS2813
has one inverting and one noninverting driver. The TPS2814 is a dual2-input AND driver with one inverting input
on each driver, and the TPS2815 is a dual2-input NAND driver. These MOSFET drivers are capable of supplying
up to 2.1 A or sinking up to 1.9 A (see Figures 15 and 16) of instantaneous current to n-channel or p-channel
MOSFETs. The TPS2811 family of MOSFET drivers have very fast switching times combined with very short
propagation delays. These features enhance the operation of today's high-frequency circuits.
The CMOS input circuit has a positive threshold of approximately 2/3 of Vee, with a negative threshold of 1/3 of
Vee, and a very high input impedance in the range of 109 Q. Noise immunity is also very high because of the
Schmidt trigger switching. In addition, the design is such that the normal shoot-through current in CMOS (when
the input is biased halfway between Vee and ground) is limited to less than 6 mA. The limited shoot-through
is evident in the graphs in Figures 17 and 18. The input stage shown in the functional block diagram better
illustrates the way the front end works. The circuitry of the device is such that regardless of the rise and/or fall
time of the input signal, the output signal will always have a fast transition speed; this basically isolates the
waveforms at the input from the output. Therefore, the specified switching times are not affected by the slopes
of the input waveforms.
The basic driver portion of the circuits operate over a supply voltage range of 4 V to 14 V with a maximum bias
current of 5 !lAo Each driver consists of a CMOS input and a buffered output with a 2-A instantaneous drive
capability. They have propagation delays of less than 30 ns and rise and fall times of less than 20 ns each.
Placing a O.1-!lF ceramic capacitor between Vee and ground is recommended; this will supply the
instantaneous current needed by the fast switching and high current surges of the driver when it is driving a
MOSFET.
The output circuit is also shown in the functional block diagram. This driver uses a unique combination of a
bipolar transistor in parallel with a MOSFET for the ability to swing from Vee to ground while providing 2 A of
instantaneous driver current. This unique parallel combination of bipolar and MOSFET output transistors
provides the drive required at Vee and ground to guarantee turn-off of even low-threshold MOSFETs. Typical
bipolar-only output devices don't easily approach Vee or ground.
The regulator, included in the TPS2811, TPS2812 and TPS2813, has an input voltage range of 14 V to 40 V.
It produces an output voltage of 10 V to 13 V and is capable of supplying from 0 to 20 mA of output current. In
grounded source applications, this extends the overall circuit operation to 40 V by clamping the driver supply
voltage (Ved to a safe level for both the driver and the MOSFET gate. The bias current for full operation is a
maximum of 150 !lAo A 0.1-I1F capaCitor connected between the regulator output and ground is required to
ensure stability. For transient response, an additional 4.7-I1F electrolytic capacitor on the output and a 0.1-I1F
ceramic capacitor on the input will optimize the performance of this circuit. When the regulator is not in use, it
can be left open at both the input and the output, or the input can be shorted to the output and tied to either the
Vee or the ground pin of the chip.
~TEXAS
IH6
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS2811, TPS2812, TPS2813, TPS2814, TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS132D - NOVEMBER 1995 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
matching and paralleling connections
Figures 21 and 22 show the delays for the rise and fall time of each channel. As can be seen on a 5-ns scale,
there is very little difference between the two channels at no load. Figures 23 and 24 show the difference
between the two channels for a 1-nF load on each output. There is a slight delay on the rising edge, but little
or no delay on the falling edge. As an example of extreme overload, Figures 25 and 26 show the difference
between the two channels, or two drivers in the package, each driving a 1O-nF load. As would be expected, the
rise and fall times are significantly slowed down. Figures 28 and 29 show the effect of paralleling the two
channels and driving a 1-nF load. A noticeable improvement is evident in the rise and fall times of the output
waveforms. Finally, Figures 30 and 31 show the two drivers being paralleled to drive the 1O-nF load and as could
be expected the waveforms are improved. In summary, the paralleling of the two drivers in a package enhances
the capability of the drivers to handle a larger load. Because of manufacturing tolerances, it is not recommen~ed
to parallel drivers that are not in the same package.
TPS2811
T
0.1 I1F
-::-
T4.7
Vee
11F
-::-
Output
I
-=
1nF
-::-
4
5
Figure 19. Test Circuit for Measuring Switching Characteristics
TPS2811
r--.------~---
+
TO.1 T
I1F
vee
4.711F
x>----I-''------+~~-------f---I-"-.......---.,K)) Output 2
NOTE A: Input rise and fall times should be ,;;10 ns for accurate measurement of ae parameters.
Figure 20. Test Circuit for Measuring Switching Characteristics with the Inputs Connected in Parallel
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
9-17
TPS2811, TPS2812, TPS2813, TPS2814, TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS132D - NOVEMBER 1995 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
~O
,
I
i=!..
st10J (5 LIy,I5
nsl~IY)
~Vo a120tiT (5~/dIY: 5 n~dIY)
I
-
TA = 25°C
VI= 14V
CL=O
Paralleled Input
.!.
~.
r--
~
~,.
~
.1.
Vo at 1,!,T (5 V/dlY,5 ns/dly)
".
Vo at 20UT (5 V/dlY,5 nsldly)
TA = 25°C
VI=14V
CL=O
Paralleled Inputs
t-TIme
t-Tlme
Figure 21. Voltage 01.1 OUT vs Voltage at
20UT, Low-to-High Output Delay
Figure 22. Voltage at 10UT vs Voltage
at 20UT, High-to-Low Output Delay
volat 1JUT(~ V/dly,10-+;'sldi~)
..:-..
TA = 25°C
VI= 14V
CL = 1 nF on Each Output
Paralleled Input
..po..
II. ~at120UT
~
rl
'1/\
(5 v IdiY, 10 nsldlY)
Vo
1\
I
I
volat1LT
(5 V/diY, 10 ns/dlv)
at20~'10lnslr
TA = 25°C
VI =14V
CL = 1 nF Each Output
Paralleled Input
t-TIme
t-Tlme
Figure 23. Voltage at 10UT vs Voltage at
20UT, Low-to-Hlgh Output Delay
Figure 24. Voltage at 10UT vs Voltage at
20UT, High-ta-Low Output Delay
~TEXAS
9-18
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS2811, TPS2812, TPS2813, TPS2814,TPS2815
DUAL HIGH·SPEED MOSFET DRIVERS
SLVSl32D - NOVEMBER 1995 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
+VO~110~T I
(5 V/dlv, 20 ns/dlv) I
,'"
-
~oa120UT
/:
(5 V/dlv, 20 ns/dlv)
'1\ '("
"VO at (5 V/dlv, 20 ns/dlv)
~
"
Vo al20UT (5 V/dlv, 20 ns/dlv)
TA~25oe
TA=25°e
Vee =14V
eL = 10 nF on Each Oulpul
Paralleled Inpul
Vee=14V
eL = 10 nF on Each OutpUI
Paralleled Input
I-Time
I-Time
Figure 25. Voltage at 1OUT vs Voltage at
20UT, Low-to-High Output Delay
Figure 26. Voltage at 10UT vs Voltage at
20UT, High-to-Low Output Delay
.--......----4.-vee
+
TO.1 T
I1F
4.711F
Output
4
5
NOTE A: Input rise and fall times should be :;;10 ns for accurate measurement of ac parameters.
Figure 27. Test Circuit for Measuring Paralleled Switching Characteristics
~1ExAs
INSTRUMENTS
POST OFFICE BOX 855303 • DALlAS. TEXAS 75285
9-19
TPS2811, TPS2812, TPS2813, TPS2814, TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS132D - NOVEMBER 1995 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
I--
~
TA=25°e
Vee=14\(
eL = 1 nF
Paralleled Input
and Output
v: (5 V}dIV, ~ nSidlV)
'"
tl (5
II
ITA=125oel
I
Vee = 14 V
eL= 1 nF
Paralleled Input
and Output
II
~
~
v
~/dIV! 20 n~divl
-
/.
V~5V/dl , 20 ns/dlv)
I
_
~
\
Vo (5 V/dlv, 20 ns/dlv)
\V ''--1
t-11me
t-Tlme
Figure 28. Input Voltage vs Output Voltage,
Low-to-Hlgh Propagation Delay of Paralleled
Drivers
Figure 29. Input Voltage vs Output Voltage,
Hlgh-to-Low Propagation Delay of Paralleled
Drivers
TA=25°e
Vee=14V
eL=10nF
Paralleled Input
and Output
\
r
~v
I
VI (5 V/dlv, 20 ns/dlv)
I
"\ VI (5 V/dlv, 20 ns/dlvj
I
\ ...
/.
A
V
A
\~
VVo (5 V/dlv, 20 ns/dlv)
AA
'" ~
TA=25°e
Vee = 14 V
eL=10nF
Paralleled Input
.... and Output
~J
Vo (5 V/dlv, 20 ns/dlv)
t-Tlme
t-Tlme
Figure 30. Input Voltage vs Output Voltage,
Low-to-High Propagation Delay of Paralleled
Drivers
Figure 31. Input Voltage vs Output Voltage,
High-to-Low Propagation Delay of Paralleled
Drivers
~1ExAs
9-20
v
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS2811, TPS2812,TPS2813, TPS2814,TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVSl32D - NOVEMBER 1995 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
Figures 33 through 47 illustrate the performance of the TPS2811 driving MOSFETs with clamped inductive
loads, similar to what is encountered in discontinuous-mode flyback converters. The MOSFETs that were tested
range in size from Hex-1 to Hex-4, although the TPS28xx family is only recommended for Hex-3 or below.
The test circuit is shown in Figure 32. The layout rules observed in building the test circuit also apply to real
applications. Decoupling capacitor C1 is a 0.1-IlF ceramic device, connected between Vee and GND of the
TPS2811, with short lead lengths. The connection between the driver output and the MOSFET gate, and
between GND and the MOSFET source, are as short as possible to minimize inductance. Ideally, GND of the
driver is connected directly to the MOSFET source. The tests were conducted with the pulse generator
frequency set very low to eliminate the need for heat sinking, and the duty cycle was set to turn off the MOSFET
when the drain current reached 50% of its rated value. The input voltage was adjusted to clamp the drain voltage
at 80% of its rating.
As shown, the driver is capable of driving each of the Hex-1 through Hex-3 MOSFETs to switch in 20 ns or less.
Even the Hex-4 is turned on in less than 20 ns. Figures 45, 46 and 47 show that paralleling the two drivers in
a package enhances the gate waveforms and improves the switching speed of the MOSFET. Generally, one
driver is capable of driving up to a Hex-4 size. The TPS2811 family is even capable of driving large MOSFETs
that have a low gate charge.
2
3
R1
500
4
5
....~t-- Vcc
+
C1
C2
O.1IlF
4.71lF
I
T
Figure 32. TPS2811 Driving Hex-1 through Hex-4 Devices
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OAUAS. TEXAS 75265
9-21
TPS2811,TPS2812, TPS2813,TPS2814, TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS132D - NOVEMBER 1995 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
+_
TA=25°C
Vee = 14V
VI=48V
I
_I
I
I
TA = 25°C
VCC=14V
VI=48V
Vos (20 V/diy, 0.5 J.1Sldly)
I
I
J .!
VOS (20 V/dly, 50 ns/dly)
.1
- ::"
VGS (5 V/dly, 50 nsJdly)
/
IL/
If
10 (0.5 Aldly, 0.5 J.1Sldly)
T-
I
I
I
I
t-Time
t-Tlme
Figure 33. Drain-Source Voltage vs Drain
Current, TPS2811 Driving an IRFD014
(Hex-1 Size)
TA=25°C
VCC=14V
VI=48V
~
Figure 34. Drain-Source Voltage vs
Gate-Source Voltage, at Turn-on,
TPS2811 Driving an IRFD014 (Hex-1 Size)
1\1
Vos (20 V/dly, 50 ns/dly)
J
,
VOS (50 V/dly, 0.2 !1S/diy)
I
TA=25°C
Vee = 14 V
VI=80V
VGS (5 V/dly, 50 ns/dIY)
.A
1M.
, V-
~
i"""
1\
VGS (0.5 Aldly, 0.2 !1S/dly)
t-Tlme
t-Tlme
Figure 35. Drain-Source Voltage vs
Gate-Source Voltage, at Turn-off,
TPS2811 Driving an IRFD014 (Hex-1 Size)
Figure 36. Drain-Source Voltage vs Drain
Current, TPS2811 Driving an IRFD120
(Hex-2 Size)
~TEXAS
9-22
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS2811, TPS2812, TPS2813, TPS2814, TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS132D - NOVEMBER 1995 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
TA=25°e
Vee = 14V
VI =80V
I I
I I
VOS (50 V/div, SO ns/div)
.
1\
.f
TA=25°e
Vee=14V
VI=80V
IF
J J J J
VOS (50 V/dlv, 50 ns/div)
/
~
.-
I
V.:::r,
r
VGS (5 V/dlv, 50 ns/dlv)
\
~
VGS (5 V/div, 50 ns/div)
V
*
t-Time
t-Time
Figure 37. Drain-Source Voltage vs
Gate-Source Voltage,
at Turn-on, TPS2811 Driving an IRFD120
(Hex-2 Size)
Figure 38. Drain-Source Voltage vs
Gate-Source Voltage,
at Turn-off, TPS2811 Driving an IRFD120
(Hex-2 Size)
TAI=25~e
Vee=14V
VI =80V
I
-
VOS (SO V/div, 2 ~/div)
TA=25°e
Vee = 14 V
VI=80V
,/
I
~
.".
VOS (50 V/dlv, SO
I
Ins/di~)
1
I\J.:I-',~
.1
,I
.1
VGS (5 Aldlv, 50 ns/dlv)
/:
I
10 (5 Aldiv, 2 ~/div)
I
T
I
I
t-Time
t-Time
Figure 39. Drain-Source Voltage vs Drain
Current, TPS2811 Driving an IRF530
(Hex-3 Size)
Figure 40. Drain-Source Voltage vs
Gate-Source Voltage, at Turn-on, TPS2811
Driving an IRF530 (Hex-3 Size)
~lExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9-23
TPS2811,TPS2812,TPS2813,TPS2814,TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS132D - NOVEMBER 1995 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
Vos (50 V/div, 0.2IJ.S1div)
I.a.
II'
IL
V
V
n
Vos (50 V/dlv, 50 nsldlv)
It- "
I
I
II IV V' 'A. ~
TAI=25~e
Vee = 14 V
VI=350V
TA=25°e
Vee=14V
VI=80V
J
-
.\
10 (2 Aldiv,
j
0.21J.S/dlv)
,
Vas (5 V/div, 50 ns/div)
\I"' --"""
I-Time
I-Time
Figure 41. Drain-Source Voltage vs Drain
Current,
One Driver, TPS2811 Driving an IRF840
(Hex-4 Size)
Figure 42. Drain-Source Voltage vs
Gate-Source Voltage,
at Turn-off, TPS2811 Driving an IRF530
(Hex-3 Size)
vvvt (1 ~~IV,
vos (50 V~ v, 50 nsldlv)
I
r
.~
IV::'-"~.~ I~_rvas (5 V/dlv, 50 nsidlv)
5J nslJIV)
1\
V
\
\
iV
TA=25°e
vee = 14 V
VI=350V
TA=25°e
Vee = 14V
VI=350V
J
I-Time
I-Time
Figure 43. Drain-Source Voltage vs
Gate-Source Voltage, at Turn-on,
One Driver, TPS2811 Driving an IRF840
(Hex-4 Size)
Figure 44. Drain-Source Voltage vs Gate-Source
Voltage, at Turn-off, One Driver,
TPS2811 Driving an IRF840
(Hex-4 Size)
~1EXAS
9-24
Vas (5 V/dlv, 50 nsldlv)
INSTRUMENTS
POST OFFICE BOX 655303 • DAU..AS. TEXAS 75265
TPS2811, TPS2812,TPS2813,TPS2814, TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS132D - NOVEMBER 1995 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
...
III
Vos(SO V/dlv, 0.2 J.lS/dlv)
VOS (50 V/dhl
50 nsldlv)
1\
\J V ~
"-'" ~
./
~
TA=25°e
vee = 14 V
VI=350V
V
~
VGS (5 V/dlv,
50 nsldlv)
10 (2 Aldlv,
0.2J.1S/dlv)
TA=25°e
Vee = 14 V
VI=3SOV
I
~ ..........
I
t-TIme
t-TIme
Figure 45. Drain-Source Voltage vs Drain
Current, Parallel Drivers,
TPS2811 Driving an IRF840 (Hex-4 Size)
Figure 46. Drain-Source Voltage vs Gate-8ource
Voltage, at Turn-on, Parallel Drivers,
TPS2811 Driving an IRF840 (Hex-4 Size)
N~i
'V'cY
vos (50 V/dlv, 50 nsldlv)
\
J
,.,
:VGS (5 V/dlv, 50 nsldlv)
TA=25°e
vee = 14 V
VI=350V
t-TIme
Figure 47. Drain-Source Voltage vs Gate-Source Voltage, at Turn-off,
Parallel Drivers, TPS2811 Driving an IRF840 (Hex-4 Size)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
~25
TPS2811, TPS2812, TPS2813, TPS2814, TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS132D - NOVEMBER 1995 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
synchronous buck regulator
Figure 48 is the schematic for a 100-kHz synchronous-rectified buck converter implemented with a TL5001
pulse-width-modulation (PWM) controller and a TPS2812 driver. The bill of materials is provided in Table 1. The
converter operates over an input range from 5.5 V to 12 V and has a 3.3-V output capable of supplying 3 A
continuously and 5 A during load surges. The converter achieves an efficiency of 90.6% at 3 A and 87.6% at
5 A. Figures 49 and 50 show the power switch switching performance. The output ripple voltage waveforms are
documented in Figures 54 and 55.
The TPS2812 drives both the power switch, 02, and the synchronous rectifier, 01. Large shoot-through
currents, caused by power switch and synchronous rectifier remaining on simultaneously during the transitions,
are prevented by small delays built into the drive signals, using CR2, CR3, R11, R12, and the input capacitance
of the TPS2812. These delays allow the power switch to turn off before the synchronous rectifier turns on and
vice versa. Figure 51 shows the delay between the drain of 02 and the gate of 01; expanded views are provided
in Figures 52 and 53.
L1
27""
1
+
V,
v,
-,
1
GND
GND
11N
GNO
21N
2 OUT
C14
0.1""
308Q015
I
I
3.ao
IAF7201
1000pF
S.SV
GND
GND
•
C2
R4
2.32k<>
1%
co
AS
160n
C3
0.0022
AO
,."
.F
A1.
1k<>
CA2
3.SV
'0
10V
.""
A7
A1.
10k<>
~
C7
_...I
L
U210UT
TPS2812D
Vee
T
CA1
COMP
FB
BAS16ZX
eR3
A11
SOW
C1.
1""
TL5001CD
AT
GND
BAS1=
AS
9O.9kn
1%
A12
'.k<>
DTC
SCP
R6
121 k.O.
1%
CO
O.22~F
Figure 48. 3.3-V 3-A Synchronous-Rectified Buck Regulator Circuit
~1EXAS
INSTRUMENTS
9-26
A1
1.00kn
1%
U1
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
+
,,,,,
C1
TPS2811, TPS2812, TPS2813, TPS2814, TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS132D - NOVEMBER 1995 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
Table 1. Bill of Materials,
3.3-V, 3-A Synchronous-Rectified Buck Converter
REFERENCE
TL5001 CD, PWM
Texas Instruments,
972-644-5580
U2
TPS2812D, N.I. MOSFET Driver
Texas Instruments,
972-644-5580
3 A, 15 V, Schottky, 3060015
International Rectifier,
310-322-3331
Signal Diode, 6ASI6ZX
Zetex,
516-543-7100
AVX,
800-448-9411
TDK,
708-803-6100
CRI
CR2,CR3
Cl
1 !1F, 16 V, Tantalum
C2
0.033 !1F, 50 V
C3
0.0022 !1F, 50 V
C4
0.022 !1F, 50 V
C5,C7,CIO,CI2
C6
100 !1F, 16 V, Tantalum, TPSEI 07M016ROI 00
1000 pF, 50 V
C9
0.22 !1F, 50V
Cll
0.47 !1F, 50 V, Z5U
C13
10 !1F, 10 V, Ceramic, CC121 OCY5Vl 06Z
C14
0.1 !1F, 50 V
C15
1.0!1F,50V
Jl,J2
4-Pin Header
L1
27 !1H, 3 N5 A, SML5040
Nova Magnetics, Inc.,
972-272-8287
01
IRF7406, P-FET
International Rectifier,
310-322-3331
02
IRF7201, N-FET
International Rectifier,
310-322-3331
Rl
1.00kO,I%
R2
1.6kQ
R3
1800
R4
2.32 k.Q, 1 %
R5,RI2,RI3
10kQ
R6
150
R7
3.30
NOTES:
VENDOR
DESCRIPTION
Ul
R8
121 k.Q, 1%
R9
90.9kQ,l%
RIO
1 kO
Rll
30kQ
2. Unless otherwise specified, capacitors are X7R ceramics.
3. Unless otherwise specified, resistors are 5%, 1/10 W.
~TEXAS
INSTRUMENTS"
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
9-27
TPS2811, TPS2812, TPS2813, TPS2814, TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVSl32D - NOVEMBER 1995 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
I~
/
\:
I J J I
A
Vo (5 V/dly, 20 nsJdly)
.I
I
\IV1\
I
..... 1-
.....
VG (2 V/dly, 20 nsJdly)
'\
Vo (5 V/dly, 20 ns/dly)
I"'·
V
\:
'V
VG (2 V/dly, 20 nsJdly)
J
TA=25°c
v, = 12 V
Vo = 3.3 V at SA
t-Time
t-Time
Figure 49. Q1 Drain Voltage vs Gate Voltage,
at Switch Turn-on
Figure 50. Q1 Drain Voltage vs Gate Voltage,
at Switch Turn-off
11
J I
f
1+
I
Vo (5 V/dly, 0.5
~dlY)
TA = 25°C
V,=12V
Vo= 3.3 Vat SA
--:
-
,
TA = 25°C
V,= 12V
Vo = 3.3 Vat SA
r"\
/
I
\
IV
_
..... "
...,
VGS (2 V/dly, 20 nsJdly)
""""-
~ -...(....
\r
~
Vo (5 V/dly, 20 nsJdly)
1\
VGS (2 V/diy, 0.5 ~dlY)
T
J
.J
l
t-Time
t-Time
Figure 51. Q1 Drain Voltage vs Q2
Gate-Source Voltage
Figure 52. Q1 Drain Voltage vs Q2
Gate-8ource Voltage
~TEXAS
9-28
A.
V~
V-
I
TA = 25°C
V,=12V
Vo = 3.3 ValSA
A
INSTRUMENTS
POST OFFICE BOX 655303 • OALlAS. TEXAS 75265
TPS2811, TPS2812,TPS2813, TPS2814,TPS2815
DUAL HIGH-SPEED MOSFET DRIVERS
SLVS132D - NOVEMBER 1995 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
TA=25°c
VI=12V
Vo = 3.3 V at SA
~
VD (5 V/dlv, 20 nsldlv)
~
I \r
V
}
VGS (2 V/dlv, 20 nsldlv)
JV: I~
I\..
1\
,..
t-TIme
Figure 53. Q1 Drain Voltage vs Q2 Gate-Source Voltage
I
TA = 25°C
VI=12V
Vo=3.3VaUA
Inductor Current (1 Aldiv, 2 f.ISIdlv)
I t
./
I
I
I
I
../
V .......... r---.. ...........
/ r--. ............ r-....;
I
+
II
V
It--r-..,;
-.......",
TA = 25°C
VI=12V
Vo = 3.3 Vat 5 A
Output Ripple Voltage (20 mY/diY, 2 J1S/dlv)
'"
~
J
1'10'
"
"'-
I
V r- r- r-
r-...
.........
/~
I
Inductor Current (2 Aldiv, 2 f.ISIdiv)
2
"I'- /
1'f N
JV
\1' VI
1\
2
Output Ripple Voltage (20 mY/diY, 2 J1S/div)
t-TIme
t-TIme
Figure 54. Output Ripple Voltage vs
Inductor Current, at 3 A
Figure 55. Output Ripple Voltage vs
Inductor Current, at 5 A
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
9-29
TPS2816, TPS2817, TPS2818, TPS2819, TPS2828, TPS2829
SINGLE-CHANNEL HIGH-SPEED MOSFET DRIVER
TPS2816, TPS2817
TPS2818, TPS2819
DBVPACKAGE
(TOP VIEW)
• Low-Cost Single-Channel High-Speed
MOSFET Driver
• Icc ... 15-J,LA Max (TPS2828, TPS2829)
• 25-ns Max Rise/Fail Times and 40-n8 Max
Propagation Delay •.• 1-nF Load
• 2-A Peak Output Current
• 4-V to 14-V Driver Supply Voltage Range;
Internal Regulator Extends Range to 40 V
(TPS2816, TPS2817, TPS2818, TPS2819)
VDD
GND
2
IN
3
• 5-pin SOT-23 Package
• -40°C to 125°C Ambient-Temperature
Operating Range
5
VCC
4
OUT
TPS2828, TPS2829
DBVPACKAGE
(TOP VIEW)
• Highly Resistant to Latch-ups
NC
5
VCC
4
OUT
description
The TPS28xx single-channel high-speed MOSFET drivers are capable of delivering peak
currents of up to 2 A into highly capacitive loads.
High switching speeds (tr and tf = 14 ns typ) are
obtained with the use of BiCMOS outputs. Typical
threshold switching voltages are 213 and 1/3 of
Vee. The design inherently minimizes shootthrough current.
GND
2
IN
3
NC - No internal connection
A regulator is provided on TPS2816 through TPS2819 devices to allow operation with supply inputs between
14 V and 40 V. The regulator output can be used to power other circuits, provided power dissipation does not
exceed package limitations. If the regulator is not required, Voo (the regulator input) should be connected to
Vee. The TPS2816 and TPS2817 input circuits include an active pullup circuit to eliminate the need for an
external resistor when using open-collector PWM controllers. The TPS2818 and TPS2819 are identical to the
TPS2816 and TPS2817, except that the active pullup circuit is omitted. The TPS2828 and TPS2829 are
identical to the TPS2818 and TPS2819, except that the internal voltage regulator is omitted, allowing quiescent
current to drop to less than 15 !LA when the inputs are high or low.
The TPS28xx series devices are available in 5-pin SOT-23 (DBV) packages and operate over an ambient
temperature range of -40°C to 125°C.
AVAILABLE OPTIONS
FUNCTION
TA
-40°C to 125°C
PACKAGED DEVICES
SOT-23-5 (DBY)
CHIP FORM
M
Inverting driver with active pullup input
TPS2816DBV
TPS2816Y
TPS2817Y
Noninverting driver with active pullup input
TPS2817DBV
Inverting driver
TPS2818DBV
TPS2818Y
Noninverting driver
TPS2819DBV
TPS2819Y
Inverting driver, no regulator
TPS2828DBV
TPS2828Y
Noninverting driver, no regulator
TPS2829DBV
TPS2829Y
The DBV package is available taped and reeled only.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
copyright © 1997, Texas Instruments Incorporated
9-31
TPS2816,TPS2817,TPS2818,TPS2819,TPS2828,TPS2829
SINGLE-CHANNEL HIGH-SPEED MOSFET DRIVER
SLVS160A - FEBRUARY 1997 - REVISED NOVEMBER 1997
functional block diagram
TPS2816, TPS2818
TPS2817, TPS2819
Vee
VDD
Active Pullup
(TPS2816 Only)
IN
GND
Active Pullup
(TPS2817 Only)
-"---1
OUT
---;h
-"---1
OUT
---;h
TPS2828
TPS2829
Vee
Vee
OUT
---;h
IN-r>GND
OUT
---;h
OUTPUT STAGE DIAGRAM
INPUT STAGE DIAGRAM
Vee
IN
IN
GND
IN--1>GND
Vee
VDD
Vee
+---<~-+--+---t- To Drive
Stage
OUT
~TEXAS
9-32
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS2816, TPS2817, TPS2818, TPS2819, TPS2828, TPS2829
SINGLE-CHANNEL HIGH-SPEED MOSFET DRIVER
SLVS160A - FEBRUARY 1997 - REVISED NOVEMBER 1997
TPS28xxY chip information
This chip, when properly assembled, displays characteristics similar to those of the TPS28xx. Thermal
compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be
mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(4)
(5)
OUT
VCC
(2)
GND
TPS2816Y
(1)
(3)
VDDt
IN
tTPS2816 through TPS2819 only
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 x 4 MINIMUM
TJ max
=150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
111111111111111111111111111111111111111111111111
Terminal Functions
TPS2816, TPS2818, TPS2828 (inverting driver)
TERMINAL
NAME
DESCRIPTION
NO.
VDD
1
Regulator supply voltage input. (Not connected on TPS2828)
GND
2
Ground
Driver input.
IN
3
OUT
4
Driver output, OUT = IN
Vee
5
Driver supply voltage/regulator output voltage
TPS2817, TPS2819, TPS2829 (noninvertlng driver)
TERMINAL
NAME
DESCRIPTION
NO.
VDD
1
Regulator supply voltage input. (Not connected on TPS2829)
GND
2
Ground
IN
3
Driver input.
OUT
4
Driver output, OUT= IN
Vee
5
Driver supply voltage/regulator output voltage
:II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
9-33
TPS2816,TPS2817, TPS2818,TPS2819,TPS2828,TPS2829
SINGLE-CHANNEL HIGH-SPEED MOSFET DRIVER
SLVSl60A - FEBRUARY 1997 - REVISED NOVEMBER 1997
DISSIPATION RATING TABLE
=
=
PACKAGE
TA S; 25°C
POWER RATING
DERATING FACTOR
ABOVE TA 25°C
TA 70°C
POWER RATING
TA 80°C
POWER RATING
DBV
437mW
3.5mW/"C
280mW
227mW
=
These dissipation ratlngs are based upon EIA specification JESD51-3, "Low Effective Thermal
Conductivity Test Board for Leaded Surface Mount Packages," in tests conducted In a zero-airflow, wind
tunnel environment.
absolute maximum ratings over operating temperature range (unless otherwise noted)t
Regulator supply voltage range, Voo ................................................ -0.3 V to 42 V
Supply voltage range, Vee .......................................................... -0.3 V to 15 V
Input voltage range, IN ............................................................ -0.3 V to 15 V
Continuous regulator output current, Vee ................................................... 25 mA
Continuous output current, OUT ........................................................ ±100 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. See Dissipation Rating Table
Operating ambient temperature range, TA •••••••••••••••••••.•.•••••••.••••• -40°C to 125°C
Storage temperature range, TstQ •..••...•••••..••••••••••..••••.•.•••.•.•. -65°C to 150°C
Lead temperature 1,6 mm (1/16Jnch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions' is not
Implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to device GNO terminal.
recommended operating conditions
MIN
MAX
Regulator Input voltage range, VOO, TPS2816 through TPS2819
8
40
V
Supply voltage, VCC
4
14
V
-0.3
0
VCC
20
mA
-40
125
°c
Input voltage, IN
Continuous regulator output current, ICC
Operating ambient temperature range, TA
~TEXAS
9-34
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS. TEXAS 75266
UNIT
V
TPS2816, TPS2817, TPS2818,TPS2819, TPS2828, TPS2829
SINGLE-CHANNEL HIGH-SPEED MOSFET DRIVER
SLVS160A- FEBRUARY 1997 - REVISED NOVEMBER 1997
TPS28xx electrical characteristics over recommended operating ambient temperature range,
Vee = 10 V, VDD tied to Vee, CL 1 nF (unless otherwise specified)
=
Inputs
TEST CONDITIONS
PARAMETER
MIN
Vee=5V
Positive-going Input threshold voltage
Negative-going Input threshold voltage
Input current, TPS2816117
MAX
3.3
4
Vee=10V
6.6
7
Vee = 14 V
9.3
10
Vee=5V
1
1.7
Vee=10V
2
3.3
Vee = 14V
2.5
4.6
UNIT
V
V
1.3
V
Input = 0 Vor Vee
0.2
!IA
Input=OV
650
Input voltage hysteresis
Input current, TPS2818119/28129
TYP't
!IA
15
Input = Vee
Input capacitance
5
10
MAX
pF
t Typlcals are for TA = 25°e unless otherwise noted.
outputs
PARAMETER
TEST CONDITIONS
10=-1 mA
High-level output voHage
10 =-100 mA
MIN
TYPt
9.75
9.9
8
9.1
V
0.18
0.25
1
2
MIN
TYPt
MAX
10
11.5
13
10=1 mA
Low-level output voltage
lo=100mA
UNIT
V
t Typlcals are for TA = 25°e unless otherwise noted.
regulator, TPS2816 through TPS2819
TEST CONDITIONS
PARAMETER
Output voltage
14SVOOS40V,
OSIoS20mA
Output voltage In dropout
10= 10mA,
VOO= 10V
8
10
UNIT
V
V
t Typicals are for TA = 25°e unless otherwise noted.
supply current
TYP't
MAX
IN = high = 10V
150
250
IN=low=OV
650
1000
25
50
0.1
15
PARAMETER
TEST CONDITIONS
TPS2816,
TPS2817
TPS2818,
TPS2819
Supply current Into Vee
TPS2828,
TPS2829
Supply current Into VOO
IN = high or low,
High=10V,Low=OV
MIN
TPS2816,
TPS2817
VOO=20V,
IN = high = 10 Vor low = 0 V
650
1000
TPS2818,
TPS2819
VOO=20V,
IN = high = 10 Vor low = 0 V
50
150
UNIT
!IA
!IA
t Typlcals are for TA = 25°e unless otherwise noted.
~TEXAS
INSTRUMENTS
POST OFFICE eox 655303 • DALlAS, TEXAS 75265
9--35
TPS2816, TPS2817, TPS2818, TPS2819, TPS2828, TPS2829
SINGLE-CHANNEL HIGH-SPEED MOSFET DRIVER
SLVS160A - FEBRUARY 1997 - REVISED NOVEMBER 1997
TPS28xxY electrical characteristics at TA
(unless otherwise specified)
=25°C, Vee = 10 V,
Voo tied to Vee, CL
= 1 nF
Inputs
PARAMETER
TEST CONDITIONS
MIN
Posltive-golng input threshold voltage
Negative-going input threshold voltage
Vee = 10V
6.6
Vee=14V
9.3
Input current, TPS2816117
MAX
UNIT
V
Vee=5V
1.7
Vee=10V
3.3
Vee = 14V
4.6
1.3
V
Input = 0 V or Vee
0.2
J.IA
Input = OV
650
Input = Vee
15
Input voltage hysteresis
Input current, TPS2818119/28129
TYP
3.3
Vee=5V
Input resistance
Input capacitance
V
J.IA
1000
Mel
5
pF
outputs
PARAMETER
TEST CONDITIONS
High-level output voltage
MIN
9.9
10=-loomA
9.1
MAX
UNIT
V
0.18
10= 1 mA
Low-level output voltage
TYP
10=-1 rnA
10= 100 rnA
V
1
regulator, TPS2816 through TPS2819
TEST CONDITIONS
PARAMETER
Output voltage
14SVOOS40V,
OSIoS20mA
Output voltage in dropout
'0=10mA,
VOO= 10V
MIN
TYP
MAX
UNIT
11.5
V
9
V
supply current
PARAMETER
TEST CONDITIONS
TPS2816,
TPS2817
Supply current into Vee
TPS2818,
TPS2819
TPS2828,
TPS2829
Supply current i~to VOO
MIN
TYP
IN=high=10V
150
IN = 10w=OV
650
IN = high or low,
Hlgh=10V, Low=OV
25
MAX
UNIT
J.IA
0.1
TPS2816,
TPS2817
VOO=20V,
IN = high = 10 V or low = OV
650
TPS2818,
TPS2819
VOO=20V,
IN = high = 10Vorlow= OV
50
:'I
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
J.IA
TPS2816, TPS2817, TPS2818, TPS2819, TPS2828, TPS2829
SINGLE-CHANNEL HIGH-SPEED MOSFET DRIVER
SLVS160A- FEBRUARY 1997 - REVISED NOVEMBER 1997
switching characteristics for all devices over recommended operating ambient temperature range,
Vee = 10 V, VDD tied to Vee, CL = 1 nF (unless otherwise specified)
TEST CONOInONS
PARAMETER
MIN
TVP
tr
Rise time
14
Vee = 10V
tPHL
tPLH
14
Vee=10V
Propagation delay time, high-to-Iow-Ievel output
Propagation delay time, low-to-high-Ievel output
30
ns
25
Vee=14V
tf
UNIT
35
Vee=5V
Fall time
MAX
25
Vee = 14V
30
Vee=5V
35
Vee=14V
40
24
Vee = 10V
45
VCC=5V
50
Vee=14V
40
24
Vee = 10V
45
ns
ns
ns
50
Vee=5V
PARAMETER MEASUREMENT INFORMATION
IN
.-i-
\'-~
SO%
_ _ _ _ _ OV
I
: -11+-tf
I
OUT
:
,
tpHL
jOll
90%~!_
,
I I
i ....., ~tr
' ! J90%
10%~11t.SO%
_ _ _ _ _il--50....;%)flo% - -
~
,
,oil
,
~
0V
tpLH
Figure 1_ Typical Timing Diagram (TPS2816)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9--37
TPS2816,TPS2817, TPS2818, TPS2819, TPS2828, TPS2829
SINGLE-CHANNEL HIGH-SPEED MOSFET DRIVER
SLVS160A - FEBRUARY 1997 - REVISED NOVEMBER 1997
PARAMETER MEASUREMENT INFORMATION
Input
Figure 2. Switching Time Test Setup
TPS2816
Current
Loop
VCC
0-10 Vdc - - t - - - i
~~-----'----10V
X)----t--- OUT
T+ 4.71!F
Figure 3. Shoot·Through Current Test Setup
~TEXAS
9-38
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS2816, TPS2817, TPS2818, TPS2819, TPS2828,TPS2829
SINGLE-CHANNEL HIGH-SPEED MOSFET DRIVER
SLVS160A - FEBRUARY 1997 - REVISED NOVEMBER 1997
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Rise time
vs Supply voltage
Fall time
vs Supply voltage
Propagation time (L>H)
vs Supply voltage
Propagation Time (H >L)
vs Supply voltage
Rise time
vs Ambient temperature
Fall time
vs Ambient temperature
Propagation time (L>H)
vs Supply voltage
Propagation time (H >L)
vs Ambient temperature
Supply current (Vee)
vs Supply voltage
Supply current (Vee)
vs Load capacitance
Supply current (Vee)
vs Ambient temperature
Input threshold voltage
vs Supply voltage
Regulator output voltage
vs Regulator supply voltage
Regulator quiescent current
vs Regulator supply voltage
Shoot-through current
vs Input voltage (l>H)
Shoot-through current
vs Input voltage (H >L)
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALU\S, TEXAS 75265
9--39
TPS2816, TPS2817, TPS2818, TPS2819, TPS2828, TPS2829
SINGLE-CHANNEL HIGH-SPEED MOSFET DRIVER
SLVS160A - FEBRUARY 1997 - REVISED NOVEMBER 1997
TYPICAL CHARACTERISTICS
FALL TIME
vs
SUPPLY VOLTAGE
RISE TIME
vs
SUPPLY VOLTAGE
35
30
25
I!
I
I
20
i
15
'" "
"-
30
TA~25°C
TA=I 25oC
r--.
25
.......
r--.
CL=2 200pF
'I"
c
E
1=
.............
5
I
CL=1000pF
::
10 ~
.......
C~=O
10
8
6
CL=1000pF -
5
r----....
4
15
~
----
10
o
14
12
o
CLI=O
4
6
VCC - Supply Voltage - V
25
i.3
oJ!:
20
~:E
15
~~
10
lio
', " '"
""
.........
/J.
5
o
i'--t"-.....
4
6
TA= 25°C
35
--
~
10
12
-=14
CL =2200 pF
/
~
-
r'-- . /
~'"
"-r-:::::
CL=!1000PF
CL'=O
1\
\.
............... -..!:.L = ~200 pF
8
14
40
TA=I25o C
35 ~
1'1
.!If!
gl
12
PROPAGATION DELAY TIME,
HIGH-TQ..LOW-LEVEL OUTPUT
vs
SUPPLY VOLTAGE
40
30
10
Figure 5
PROPAGATION DELAY TIME,
LOW-TQ..HIGH-LEVEL OUTPUT
vs
SUPPLY VOLTAGE
I- I!I
8
VCC - Supply Voltage - V
Figure 4
1= ...
CL= ~OpF
"-
II
1=
...I.
20
'-
CL=1000 pF ..........-:
::j:/'
CL=O
5
o
4
VCC - Supply Voltage - V
6
8
10
Vee - Supply Voltage - V
Figure 6
Figure 7
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75285
12
14
TPS2816,TPS2817,TPS2818,TPS2819,TPS2828,TPS2829
SINGLE-CHANNEL HIGH-SPEED MOSFET DRIVER
SLVSl60A- FEBRUARY 1997 - REVISED NOVEMBER 1997
TYPICAL CHARACTERISTICS
RISE TIME
19
FALL TIME
vs
vs
AMBIENT TEMPERATURE
AMBIENT TEMPERATURE
I
20
II
Vee 10V
I- Load = 1000 pF
18 I- f = 100 kHz
._1
Vee=10V
Load = 1000 pF
18 I- f = 100 kHz
III
c
17
17
l!
I
~
1=
16
I
III
16
E
15
:f
14
:;
13
1=
1II:
I
~
=
19
15
"..........
14
V
V'
./
" . V"
-25
0
25
11
50
75
Ambient Temperatura -
/
12
./
13
-50
./
I
100
--
10
-50
125
°e
V"
-25
25
50
75
100
125
°e
Figure 9
PROPAGATION DELAY TIME,
LOW-TO-HIGH-LEVEL OUTPUT
PROPAGATION DELAY TIME,
HIGH-TO-LOW-LEVEL OUTPUT
vs
vs
SUPPLY VOLTAGE
AMBIENT TEMPERATURE
20
I!
Vee=10V
Load 1000 pF
f- f = 100 kHz
=
./
./
/'
19
Ii!
18
1=>0:::1
17
E
j1
ij
".
V
15
e.3
14
!...~
13
II.
Vee=10V
Load = 1000 pF
f= 100kHz
I
~ g 16
V"
:/
/
0
Ambient Temperatura -
FigureS
19
V
./
foo"'"
b
_ff
'"
/
-
".
/
./
/
foo"'"
12
11
13
-50
-25
0
25
50
75
TA - Ambient Temperatura -
100
125
10
-50
-25
°e
0
25
50
75
TA - Ambient Temperature -
Figure 10
100
125
°e
Figure 11
:IlJ
1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9-41
TPS2816, TPS2817, TPS2818,TPS2819, TPS2828,TPS2829
SINGLE-CHANNEL HIGH-SPEED MOSFET DRIVER
SLVS160A- FEBRUARY 1997 - REVISED NOVEMBER 1997
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
va
SUPPLY VOLTAGE
16
12
'E
~
::J
10
4
/
f= 1 MHz
V
I
0
8
i
6
::J
III
I
~
4
2
o
vs
LOAD CAPACITANCE
Load = ~OOO pF I
Duty Cycle = 50%
14
~
SUPPLY CURRENT
/"
V
V
~
3
'E
~
::J
2.5
I
0
f=5'::V7
ta.
2
III
1.5
::J
./
,/
~
V
.--'
~
f=40kHz
I
6
~
/
f = 100 kHz
0.5
8
10
12
VCC - Supply Voltage - V
o
14
o
1000
CL - Load Capacitance - pF
INPUT THRESHOLD VOLTAGE
va
SUPPLY VOLTAGE
3
2.5
9
VCC=10V
Load = 1000 pF
f=100kHz
Duty Cycle = 50%
8
1.i
I
j
ic1l
2
-
I
0
E
1.5
--
oj
:!2
Poaltlve Going
6
5
~
'--.
(:.
'5
a.
.5
I
I-
25
50
75
100
TA - Ambient Temperature - °C
0
125
4
3
2
V
V
o
./
4
Figure 14
~1ExAs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Y
V
~
/
./
V
./
/'
..... VNegatlve Going
/"
6
12
8
10
VCC - Supply Voltage - V
Figure 15
INSTRUMENTS
9-42
/
/
J:.
1
-25
7
0
'>
-50
2000
Figure 13
SUPPLY CURRENT
va
AMBIENT TEMPERATURE
E
~
E
Figure 12
c
/
0
\
4
VCC = 10V
f = 100 kHz
Duty Cycle = 50%
3.5
14
TPS2816, TPS2817, TPS2818, TPS2819, TPS2828,TPS2829
SINGLE-CHANNEL HIGH-SPEED MOSFET DRIVER
SLVSl60A - FEBRUARY 1997 - REVISED NOVEMBER 1997
TYPICAL CHARACTERISTICS
REGULATOR OUTPUT VOLTAGE
vs
REGULATOR SUPPLY VOLTAGE
REGULATOR QUIESCENT CURRENT
vs
REGULATOR SUPPLY VOLTAGE
12
,
>
I
670
11
~
i
'!i
9
::1.
C
~
d
i
a
1
6
/
I
655
650
645
640
I
635
I
630
/
Load=10kQ
II
12
16
20
24
28
32
36
40
/
/
625
8
620 I'
4
8
12
VOO - Regulator Supply Voltage - V
16
6
7
E
I
/
5
II
C
i
e
.c
3
o
o
2
4
6
II
4
\
2
rn
/\,
5
\
\
.c
!f
TA = 25°C
1\
I
4
40
....
I- No Load
6
L
i f----'" II
0
36
32
I.
Vcc=10V
/'
CC
28
SHOOT·THROUGH CURRENT
vs
INPUT VOLTAGE HIGH·TO·LOW
I"
t-
24
Figure 17
SHOOT·THROUGH CURRENT
vs
INPUT VOLTAGE LOW·TO·HIGH
Vcc=10V
No Load
TA=250c
20
VOO - Regulator Supply Voltage - V
Figure 16
7
oil!!.
II
::J
/
44
660
I
I
7
5
CC
II
8
0
I'5
I
665 I- NoLoad
1
1
10
CD
--
TPS2816,17 only
I
i
3
~
8
10
2
i----'"
~
I
\
II
~
1
o
o
VI - Input Voltage - V
2
4
6
VI-Input Voltage - V
Figure 18
'"
8
10
Figure 19
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 752tl5
9-43
TPS2816,TPS2817,TPS2818,TPS2819,TPS2828,TPS2829
SINGLE·CHANNEL HIGH·SPEED MOSFET DRIVER
SLVS160A - FEBRUARY 1997 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
MOSFETs are voltage-driven devices that require very little steady-state drive current. However, the large input
capacitance (200 pF to 3000 pF or greater) of these devices requires large current surges to reduce the tum-on
and tum-off times. The TPS2816 series of high-speed drivers can supply up to 2 A to a MOSFET, greatly
reducing the switching times. The fast rise times and fall times and short propagation delays allow for operation
in today's high-frequency switching converters.
In addition, MOSFETs have a limited gate-bias voltage range, usually less than 20 V. The TPS2816 series of
drivers extends this operating range by incorporating an on-board series regulator with an input range up to 40 V.
This regulator can be used to power the drivers, the PWM chip, and other circuitry, providing the power
dissipation rating is not exceeded.
When using these devices, care should be exercised in the proper placement of the driver, the switching
MOSFET, and the bypass capacitor. Because of the large input capacitance of the MOSFET, the driver should
be placed close to the gate to eliminate the possibility of oscillations caused by trace inductance ringing with
the gate capacitance of the MOSFET. When the driver output path is longer than approximately 2 inches, a
resistor in the range of 10 n should be placed in series with the gate drive as close as possible to the MOSFET.
A ceramic bypass capacitor is also recommended to provide a source for the high-speed current transients that
the MOSFET requires. This capacitor should be placed between Vee and GND of the driver (see Figures 20
and 21).
TPS2816
vee
5
Load
2
Input
O.1IlF
3
4
J
Figure 20. Vee < 14 V
Load
3
Input -t-=--I----i
4
Figure 21. Vee> 14 V
9-44
:lllExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
J
TPS2816, TPS2817, TPS2818, TPS2819, TPS2828, TPS2829
SINGLE-CHANNEL HIGH-SPEED MOSFET DRIVER
SLVS160A - FEBRUARY 1997 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
The on-board series regulator supplies approximately 20 rnA of current at 11.S V, some of which can be used
for external circuitry, providing the power dissipation rating for the driver is not exceeded. When using the
on-board series regulator, an electrolytic output capacitor of 4.7 I1F or larger is recommended. Although not
required, a 0.1-I1F ceramic capacitor on the input of the regulator can help suppress transient currents (see
Figure 22). When not used, the regulator should be connected to Vee. Grounding Voo will result in destruction
of the regulator.
34VDC
Jo.
O.1I1F
Jo. J;
T4.7I1F
0.1 11FT
-=-
VCC
r
-
-=-
TPS2816
~
PWM
Controller
1
11
I.....
1
Regulator
5
±0.1 I1F'-
-=-tOut
3
rl
GND
4
I~
-=-
J.
.....1
~.J.
Vo
T10 I1F
-=-
Figure 22. Boost Application
The TPS2816 and TPS2818 drivers include active pullup circuits on the inputs to eliminate the need for external
pullup resistors when using controllers with open-collector outputs (such as the TLS001). The TPS2817 and
TPS2819 drivers have standard CMOS inputs providing a total device operating current of less than SO !lA. All
devices switch at standard CMOS logic levels of approximately 2/3 Vee with positive-going input levels, and
approximately 1/3 Vee with negative-going input levels. Being CMOS drivers, these devices will draw relatively
large amounts of current (Approximately S rnA) when the inputs are in the range of one-half of the supply voltage.
In normal operation, the driver input is in this range for a very short time. Care should be taken to avoid use of
very low slew-rate inputs, used under normal operating conditions. Although not destructive to the device, slew
rates slower than 0.1 V/JlS are not recommended.
The BiCMOS output stage provides high instantaneous drive current to rapidly toggle the power switch, and
very low drop to each rail to ensure proper operation at voltage extremes.
Low-voltage circuits (less than 14 V) that require very low quiescent currents can use the TPS2828 and
TPS2829 drivers. These drivers use typically 0.2 JlA of quiescent current (with inputs high or low). They do not
have the internal regulator or the active pullup circuit, but all other specifications are the same as for the rest
of the family
2.5-V/3.3-V, 3-A application
Figure 23 illustrates the use of the TPS2817 with a TLS001 PWM controller and a TPS1110 in a simple
step-down converter application. The converter operates at 27S kHz and delivers either 2.S V or 3.3 V
(determined by the value of R6) at 3 A (S A peak) from a S-V supply. The bill of materials is provided in
Table 1.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
9-45
TPS2816, TPS2817, TPS2818, TPS2819, TPS2828, TPS2829
SINGLE-CHANNEL HIGH-SPEED MOSFET DRIVER
SLVSl60A- FEBRUARY 1997 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
01
TPS1110D
--
C7qca \~
~
4.5Vto7V
L1
Vo
3 A Continuous
5APeak
R5
U1
TPS2817DBV
C5:;::
~ ~:-:Z1~
3
~ t"
CR1
~-~
C9
R4
5
+
SCP
~ VCC
DTC
1:;::::::1rf
C9
R1
1
:::: ~C6
1
4
TC2:;:: r:C3
~
RT
FB
3
\I
ci~1
R7
R6
GND
COMP
C13
GND
V
OUT
+
::::_ .?r:
4
GND
U2
TL5001CD
+
C1~ r: c1 i
7
~ R3
R2
91
1\
Figure 23. Step-Down Application
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2816, TPS2817, TPS2818, TPS2819, TPS2828, TPS2829
SINGLE-CHANNEL HIGH-SPEED MOSFET DRIVER
SlVS1 60A - FEBRUARY 1997 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
Table 1. Bill of Materials
REF DES
PART NO.
DESCRIPTION
MFR
UI
TPS2817DBV
IC. MOSFET driver. single noninverting
TI
U2
T1500ICD
IC. PWM controller
TI
01
TPS1110D
MOSFET. p-channel. 6 A. 7 V. 75 mO
TI
CI. C2. C5. C8
Capacitor. ceramic. O.IIlF. 50 V. X7R. 1206
C3
Capacitor. ceramic. O.033IlF. 50 V. X7R. 1206
C4
Capacitor. ceramic. 2200 pF. 50 V. X7R. 0805
C6
ECS-T1CYI05R
Capacitor. tantalum. 1.0 IlF. 16 V. A case
Panasonic
C7
IOSC47M
Capacitor. OS-Con. 47IlF.IO V
Sanyo
C9
Capacitor. ceramic. 1000 pF, 50 V, X7R, 0805
CIO, CI2
IOSA220M
Capacitor, OS-Con, 220 IlF. 10 V
CII
Sanyo
Capacitor, ceramic, 0.022IlF, 50 V. X7R, 0805
CI3
Capacitor. ceramic, 47 IlF, 50 V, X7R
CRI
5OWQ03F
Diode, Shollky, D-pak. 5 A 30 V
IR
L1
SML3723
Inductor. 27 IlH, +/- 20%,3 A
Nova Magnetics
Rl
Resistor. CF, 47 kn, 111 0 W. 5%, 0805
R2
Resistor, CF. 1.5 kn, 1110 W. 5%. 0805
R3
Resistor, MF, 30.1 kn, 1110 W, 1%,0805
R4
Resistor, MF. 1.00 kn, 1110 W, 1%,0805
R5
Resistor, CF. 47
R6 (3.3-V)
ReSistor, MF, 2.32 kn, 1/10 W, 1%,0805
R6 (2.5-V)
Resistor, MF, 1.50 kn, 1110 W, 1%,0805
R7
ReSistor, CF. 100
n. 1/10 W. 5%. 0805
n. 1/10 W. 5%. 0805
As shown in Figures 24 and 25, the TPS2817 turns on the TPS1110 power switch in less than 20 ns and off in
25 ns .
."~;-Ga~ : .1·AkJ·· ~v/~IV
.
1...
.... :... :........ :\.
.. \..i.y~.~:.
..
..
. ..
...... . . .. : .............. : ... .
Ql Drain:
.1'"1
:
\.:
.4'1-... ...
:'
I~~-..;-~:"'"" ;
:
I .... :..
: ... : ...
Io--o~""'--:
QI Gate
2 V/dlv :
•
....
~
Q1Drain
;
2V/dlv
~---,.;.........:,..........
:
.
··..............................
..
.. , .. .
·
.
.
........... ... ......... .
·
..
... : .......... :. 12.5 ns/dlv
"
"
•••••••
··
o •••••
..
Figure 24. Q1 Turn-On Waveform
.. .. ..
................. . . .. .......................
.
....................
12:5 ns/dlv :. . .
Figure 25. Q1 Turn-Off Waveform
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
9-47
TPS2816,TPS2817,TPS2818,TPS2819,TPS2828,TPS2829
SINGLE-CHANNEL HIGH-SPEED MOSFET DRIVER
SLVSl60A - FEBRUARY 1997 - REVISED NOVEMBER 1997
APPLICATION INFORMATION
The efficiency for various output currents, with a 5.25-V input, is shown in Figure 26. For a 3.3-V output, the
efficiency is greater than 90% for loads up to 2 A - exceptional for a simple, inexpensive design.
95
/
90
'/I.
I
I
~
l
85 --i-
.I 1 .I
r--.. ...... VO=3.3V
-I"-.....
........
VO=2.5V
r-..... ...........
.....
.....
80
VI = 5.25 V
TA=25°C
:--.... r-.....
.........
".....~ ~,
.........
.........
.........
75
70
o
0.5
1
1.5 2 2.5 3 3.5
Load Current - A
4
Figure 26. Converter Efficiency
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
4.5
5
TPS2830, TPS2831
FAST SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
o OR PWP PACKAGE
• Floating Bootstrap or Ground-Reference
High-Side Driver
(TOP VIEW)
• Active Deadtime Control
• SO-ns Max Rise/Fall Times and 100-ns Max
Propagation Delay - 3-nF Load
ENABLE
IN
CROWBAR
NC
SYNC
DT
PGND
• Ideal for High-Current Single or Mutiphase
Applications
• 2.4-A lYP Peak Output Current
• 4.S-V to 1S-V Supply Voltage Range
BOOT
NC
HIGH DR
BOOTLO
LOWDR
NC
Vec
Ne - No internal connection
• Internal Schottky Bootstrap Diode
• SYNC Control for Synchronous or
Nonsynchronous Operation
• CROWBAR for OVP, Protects Against
Faulted High-Side Power FETs
• Low Supply Current •.. 3-mA Typ
• -40°C to 12SoC Junction-Temperature
Operating Range
description
The TPS2830 and TPS2831 are MOSFET drivers for synchronous-buck power stages. These devices are ideal
for designing a high-performance power supply using a switching controller that does not include suitable
MOSFET drivers on the chip. The drivers are designed to deliver 2.4-A peak currents into large capacitive loads.
Higher currents can be controlled by using multiple drivers in a multiphase configuration. The high-side driver
can be configured as a ground-reference driver or as a floating bootstrap driver. An adaptive dead-time control
circuit eliminates shoot-through currents through the main power FETs during switching transitions, and
provides high efficiency for the buck regulator. The TPS2830/31 drivers have additional control functions:
ENABLE, SYNC, and CROWBAR. Both drivers are off when ENABLE is low. The driver is configured as a
nonsynchronous-buck driver when SYNC is low. The CROWBAR function turns on the low-side power FET,
overriding the IN signal, for over-voltage protection against faulted high-side power FETs.
The TPS2830 has a noninverting input. The TPS2831 has an inverting input. The TPS2830/31 drivers are
available in 14-terminal SOIC and TSSOP packages and operate over a junction temperature range of -40°C
to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
SOIC
(D)
TJ
-40oe to 125°e
TPS2830D
TPS2831D
TSSOP
(PWP)
TPS2830PWP
TPS2831PWP
The D and PWP packages are available taped and reeled. Add R
suffix to device type (e.g., TPS2830DR)
~~~~1!::=:';'ll::'::~=m~
Blandlrd WIItInty. Production pro..88lng do.. not no..oaarIly Includ.
telling 01 all param......
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
9-49
TPS2830, TPS2831
FAST SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS196B - JANUARY1999 - REVIS!:D SEPTEMBER 1999
functional block diagram
8
14
(TPS2830 Only)
12
~
,---
11
VCC
BOOT
HIGHDR
BOOTlO
IN
(TPS2831 Only)
>--4.....:1.=.0 lOWDR
7
PGND
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
BOOT
14
I
Bootstrap terminal. A ceramic capacitor is connected between BOOT and BOOTlO terminals to develop
the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1 JLF
and 1 JLF. A l-MO resistor should be connected across the bootstrap capacitor to provide a discharge path
when the driver has been powered down.
BOOTLO
11
0
This terminal connects to the junction of the high-side and low-side MOSFETs.
CROWBAR
3
I
CROWBAR can to be driven by an external OVP circuit to protect against a short across the high-side
MOSFET. If CROWBAR is driven low, the low-side driver will be turned on and the high-side driver will be
turned off, independent of the status of all other control terminals.
DT
6
I
Deadtime control terminal. Connect DT to the junction of the high-side and low-side MOSFETs.
ENABLE
1
I
If ENABLE is low, both drivers are off.
Output drive for the high-side power MOSFET
HIGHDR
12
0
IN
2
I
Input signal to the MOSFET drivers (noninverting Input for the TPS2830; inverting input for the TPS2831).
LOWDR
10
0
Output drive for the low-side power MOSFET
NC
4,9,13
PGND
7
SYNC
5
I
Synchronous Rectifier Enable terminal. If SYNC is low, the low-side driver is always off; If SYNC is high,
the low-side driver provides gate drive to the low-side MOSFET.
VCC
8
I
Input supply. Recommended that a 1-JLF capaCitor be connected from VCC to PGND.
Power ground. Connect to the FET power ground
~TEXAS
9-50
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS2830, TPS2831
FAST SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVSl96B - JANUARYl999 - REVISED SEPTEMBER 1999
detailed description
low-side driver
The low-side driver is designed to drive low Rds(on) N-channel MOSFETs. The current rating of the driver is
2 A, source and sink.
high-side driver
The high-side driver is designed to drive low Rds(on) N-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The high-side driver can be configured as a GND-reference driver or as a floating bootstrap
driver. The internal bootstrap diode is a Schottky, for improved drive efficiency. The maximum voltage that can
be applied from BOOT to ground is 30 V.
deadtime (DT) controlt
Deadtime control prevents shoot through current from flowing through the main power FETs during switching
transitions by controlling the turn-on times of the MOSFET drivers. The high-side driver is not allowed to turn
on until the gate drive voltage to the low-side FET is low, and the low-side driver is not allowed to turn on until
the voltage at the junction of the power FETs (Vdm) is low; the DT terminal connects to the junction of the power
FETs.
ENABLEt
The ENABLE terminal enables the drivers. When enable is low, the output drivers are low.
INt
The IN terminal is the input control signal for the drivers. The TPS2830 has a noninverting input; the TPS2831
has an inverting input.
SYNCt
The SYNC terminal controls whether the drivers operate in synchronous or nonsynchronous mode. In
synchronous mode, the low-side FET is operated as a synchronous rectifier. In nonsynchronous mode, the
low-side FET is always off.
CROWBARt
The CROWBAR terminal overrides the normal operation of the driver. When the CROWBAR terminal is low,
the low-side FET turns on to act as a clamp, protecting the output voltage of the dc/dc converter against over
voltages due to a short across the high-side FET. VIN should be fused to protect the low-side FET.
tHigh-level input voltages on ENABLE, SYNC, CROWBAR, IN. and DT must be greater than or equal to VCC.
~TEXAS
INSTRUMENTS
POST OFFICE
eox 665303 •
DALLAS. TEXAS 75266
9-51
TPS2830, TPS2831
FAST SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVSl96B -JANUARY1999 - REVISED SEPTEMBER 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................. -0.3 V to 16 V
Input voltage range: BOOT to PGND (high-side driver ON) ............................. -0.3 V to 30 V
BOOTLO to PGND ............................................... -0.3 V to 16 V
BOOT to BOOTLO .............................................. -0.3 V to 16 V
ENABLE, SYNC, and CROWBAR (see Note 2) ..................... -0.3 V to 16 V
IN (see Note 2) ................................................. -0.3 V to 16 V
DT (see Note 2) ................................................ -0.3 V to 30 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating virtual junction temperature range, TJ .................................... -40°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds ....................... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Unless otherwise specified, all voltages are with respect to PGND.
2. High-level input voltages on the ENABLE, SYNC, CROWBAR, IN, and DT terminals must be greater than or equal to VCC.
DISSIPATION RATING TABLE
TA';; 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
D
760mW
PWP
2400mW
PACKAGE
=
=
TA 70°C
POWER RATING
TA 85°C
POWER RATING
7.6mW/oC
420mW
305mW
25mW/oC
1275mW
900mW
recommended operating conditions
MIN
Supply voltage, VCC
Input voltage
I BOOT to PGND
NOM
MAX
UNIT
4.5
15
V
4.5
28
V
electrical characteristics over recommended operating virtual junction temperature range,
Vee = 6.5 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted)
supply current
PARAMETER
VCC
VCC
TEST CONDITIONS
Supply voltage range
TYP
4.5
Quiescent current
VENABLE = LOW,
VCC=15V
VENABLE = HIGH,
VCC=15V
VENABLE = HIGH,
ISW>< = 200 kHz,
CHIGHDR = 50 pF,
See Note 3
VCC =12 V,
BOOTLO grounded,
CLQWDR = 50 pF,
NOTE 3: Ensured by deSign, not production tested.
~TEXAS
INSTRUMENTS
9-52
MiN
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MAX
UNIT
15
V
100
J.IA
0.1
3
rnA
TPS2830, TPS2831
FAST SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS196B - JANUARY1999 - REVISED SEPTEMBER 1999
electrical characteristics over recommended operating virtual Junction temperature range,
Vee 6.5 V, ENABLE High, CL 3.3 nF (unless otherwise noted) (continued)
=
=
=
output drivers
MIN
TYP
VBOOT - VBOOTLO = 4.5 V, VHIGHDR = 4 V
0.7
1.1
VBOOT - VBOOTLO = 6.5 V, VHIGHDR = 5 V
1.1
1.5
2
2.4
1.4
PARAMETER
High-side sink
(see Note 4)
Peak outputcurrent
High-side
source
(see Note 4)
Low-side sink
(see Note 4)
Low-side
source
(see Note 4)
TEST CONDITIONS
Duty cycle < 2%,
rsw < 100 lIS
see Note 3)
VBOOT-VBOOTLO = 12V, VHIGHDR = 10.5 V
Duty cycle < 2%,
VBOOT - VBOOTLO = 4.5 V, VHIGHDR = 0.5V
1.2
rsw < 100 lIS
see Note 3)
VBOOT - VBOOTLO = 6.5 V, VHIGHDR = 1.5 V
1.3
1.6
VBOOT - VBOOTLO = 12 V, VHIGHDR = 1.5 V
2.3
2.7
Duty cycle < 2%,
tpw < 100 lIS
(see Note 3)
Vee = 4.5 V,
VLOWDR=4V
1.3
1.8
Vee = 6.5 V,
VLOWDR=5V
2
2.5
Vee = 12V,
VLOWDR = 10.5 V
3
3.5
Duty cycle < 2%,
Vee = 4.5 V,
VLOWDR = 0.5V
1.4
1.7
rsw < 100 lIS
see Note 3)
Vee = 6.5 V,
VLOWDR = 1.5 V
2
2.4
Vee = 12V,
VLOWDR = 1.5 V
2.5
3
High-side sink (see Note 4)
High-side source (see Note 4)
Output
resistance
Low-side sink (see Note 4)
Low-side source (see Note 4)
MAX
UNIT
A
A
A
A
VBOOT - VBOOTLO = 4.5 V, VHIGHDR = 0.5 V
5
VBOOT - VBOOTLO = 6.5 V, VHIGHDR = 0.5 V
5
VBOOT - VBOOTLO = 12 V, VHIGHDR = 0.5 V
5
VBOOT - VBOOTLO = 4.5 V, VHIGHDR = 4 V
45
VBOOT - VBOOTLO = 6.5 V, VHIGHDR = 6 V
45
VBOOT - VBOOTLO = 12 V, VHIGHDR =11.5 V
45
VDRV=4.5V,
VLOWDR = 0.5 V
9
VDRV=6.5V
VLOWDR = 0.5 V
7.5
VDRV= 12V,
VLOWDR = 0.5 V
6
VDRV=4.5V,
VLOWDR=4V
45
VDRV=6.5V,
VLOWDR=6V
45
VnRv= 12V,
VLnWDR = 11.5 V
45
n
n
n
n
NOTES: 3. Ensured by design, not production tested.
4. The pulluplpulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the Rds(on) of the MOSFET transistor when
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
deatlme control
TEST CONDITIONS
PARAMETER
LOWDR
DT
High-level input voltage
Over the Vee range (see Note 3)
Low-level input voltage
High-level input voltage
Over the Vee range
LOW-level input voltage
MIN
TYP
MAX
UNIT
V
2
1
V
V
2
1
V
NOTE 3: Ensured by deSign, not production tested.
digital control terminals
PARAMETER
High-level input voltage
Low-level input voltage
TEST CONDITIONS
Over the Vee range
MIN
TYP
MAX
2
UNIT
V
1
V
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9-53
TPS2830, TPS2831
FAST SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS196B - JANUARY1 999 - REVISED SEPTEMBER 1999
switching characteristics over recommended operating virtual Junction temperature range,
ENABLE =High, CL =3.3 nF (unless otherwise noted)
PARAMETER
TEST CONOInONS
HIGHDR output
(see Note 3)
Rise time
LOWDR output
(see Note 3)
HIGH DR output
(see Note 3)
Fall time
LOWDR output
(see Note 3)
HIGHDR going low
(excluding deadtime)
(see Note 3)
Propagation delay time
LOWDR going high
(excluding deadtlme)
(see Note 3)
Propagation delay time
LOWDR going low
(excluding deadtime)
(see Note 3)
MIN
TYP
MAX
VBOOTLO=OV
VBOOT = 6.5 V,
VBOOTLO=OV
50
VBOOT=12V,
VBOOTLO=OV
50
Vee=4.5V
40
Vee=6.5V
30
Vee = 12V
30
VBOOT = 4.5 V,
VBOOTLO=OV
60
VBOOT = 6.5 V,
VBOOTLO=OV
50
VBOOT=12V,
VBOOTLO=OV
50
Vee = 4.5 V
40
Vee=6.5V
30
Vee=12V
30
VBOOT = 4.5 V,
VBOOTLO=OV
130
VBOOT = 6.5 V,
VBOOTLO=OV
100
VBOOT= 12V,
VBOOTLO=OV
75
VBOOT = 4.5 V,
VBOOTLO=OV
80
VBOOT = 6.5 V,
VBOOTLO=OV
70
VBOOT= 12V,
VBOOTLO=OV
60
Vee=4.5V
80
Vee=6.5V
70
Vee = 12V
60
Vee = 4.5 V
40
170
Vee=6.5V
25
135
Vee = 12V
NOTE 3: Ensured by design, not production tested.
15
85
Driver nonoveriap time
DT to LOWDR and
LOWDR to HIGH DR
(see Note 3)
~1ExAs
INSTRUMENTS
POST OFFICE sox 655303 • DALLAS. TEXAS 75265
UNIT
60
VBOOT = 4.5 V,
ns
ns
ns
ns
ns
ns
ns
ns
TPS2830, TPS2831
FAST SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS196B - JANUARY1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
FALL TIME
RISE TIME
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
50
\.
45
1\,
40
If)
I
1=
i
...
I
35
30
.....
25
J
45
!
High Side
I
10
-
"
E
1=
:f
.-.
"-
35
-
....
25
20
15
High Side
'-"-
30
I
Low Side
20
r-
""-
Low Side
-
15
10
10
4
5
6
7 8
9 10 11 12 13
Vee-Supply Voltage-V
14 15
4
5
6
Figure 1
7 8
9 10 11 12 13
VCC - Supply Voltage - V
50
45 -
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
35
~
30
1=
I
--
...
.,........
High Side
.-"'"
.1.
40
c
I
20
~
1=
;f
.-.
I
-- --
High Side
If)
-
25
1
VCC = 6.5 V
45 r- CL=3.3nF
--
Low Side
III
II
50
!.
VCC = 6.5 V
CL=3.3nF
40
I
FALL TIME
vs
I
14 15
Figure 2
RISE TIME
!
!
I
CL=3.3nF
TJ=25·C -
40
i\
c
~
50
J ! L
CL = 3.3 nF
TJ=25·C
35
30
25
. /V
,
.."..
/"
Low Side
20
-I"""
15
15
10
-50
-25
0
25
50
75
100
TJ - Junction Temperatura - ·C
125
10
-50
-25
Figure 3
0
25
50
75
100
TJ - Junction Temperatura - ·C
125
Figure 4
~TEXAS
INSTRUMENTS
POST OFFICE BOX 855303 • DALlAS. TEXAS 75285
9-55
TPS2830, TPS2831
FAST SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS196B - JANUARY1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE, HIGH TO LOW LEVEL
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE, LOW TO HIGH LEVEL
!
I
150
140
>0
130
120
~
i=
-m
Q
a
I
D.
90
80
~
70
~
60
I
50
40
:5D.
-
\
30
20
l
I
!
I
~
\
}'
1\
110
100
1
J
CL = 3.3 nF
TJ=25°C
g
\
c
o
1\
....
4
......... t....
f"'"".. r-.....
f"'...
5
6
J
High Side
Low Side
......... ........
~
-r........
7 8 9 10 11 12 13
Vec - Supply Voltage - V
r-......
~
II
oJ
j
14 15
150
I
110
\.
100
I\.
90
\
80
~
>0
~
150
I
I
140 - VCC=6.5V
_ CL=3.3nF
130
!
50
......
40
30
20
4
...... ........
5
6
--
High Side
50
40
30
20
-50
......
-
~~
Low Side
~ I--
Low Side
....... ........
7 8 9 10 11 12 13
VCC - Supply Voltage - V
14 15
>0
120
a
100
.--
----
--
-25
o 25 50 75 100
TJ - Junction Temperature - °C
~
I
~
....o
110
90
80
70
60
z:
.!i!l
50
I
40
:z:
125
VCC=6.5V
CL=3.3nF
30
20
-50
High Side
-
-
~TEXAS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
----
~LOWSid~
-
o 25 50 75 100
TJ - Junction Temperature - °C
Figure 8
INSTRUMENTS
.- ~
"..,.
-25
Figure 7
9--56
r- i'o.....
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
JUNCTION TEMPERATURE
150
I
I
140 _
130
i=
110
70
.......
60
~
I
120
60
-
High Side
~
70
FIgure 6
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
JUNCTION TEMPERATURE
I
I
130
120
Figure 5
!
I
CL=3.3nF TJ=25°C _
140
125
TPS2830, TPS2831
FAST SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS196B - JANUARY1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
FALL TIME
RISE TIME
vs
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
1000
1000
=
=
~
Vee = 6.5 V
TJ=25°e
fII
~
!
100
c
I
Vee=6.5V
TJ=25°e
100
I
CD
m
,--
1=
~
~~
.!!
II:
I
...
-
1.....
10
f---
~
-
Low Side
1--'
f-- ~. HlghSlda
E
1=
~ HlghSlde
CD
I
~
./
10
""
Low Side
1/
1
0.1
10
100
1
0.1
10
Figure 9
Figure 10
SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
6000
TJ=25°e
5500 I- eL=50pF
5000
cc::i
I
~
CL
en:::I
I
~
/
5OOko/
4000
300k~
100kHz / ~
50 kHZX""2000 f---- 25 kHz
2500
1500
/
1000
~
4
6
/
/
'lj
X
A<-. X
'"
~ K'"
--
/ . ~ I--""
500
/
X
200kHz
3000
o
/
/
4500
C
~ 3500
:::I
0
100
eL - Load Capacitance - nF
eL - Load Capacltanca - nF
V
/'
V
./
~~
10
12
8
Vee - Supply Voltage - V
-
14
OL-__
16
~
4
6
__
~
8
__
~~
10
__
~
__
12
~
14
__
~
16
Vee - Supply Voltage - V
Figure 12
Figure 11
~TEXAS
INSTRUMENTS .
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265
9-57
TPS2830, TPS2831
FAST SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS196B - JANUARY1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
PEAK SOURCE CURRENT
4
vs
DRIVE VOLTAGE
DRIVE VOLTAGE
4
1
TJ = 25 'C
3.5
c(
3
LOW~ ~
I
C
~
~
0
~
...II
a..
,-
3
LOWS~
c(
I
C
§
...c
...en
0
High Side
I.
0.5
o
2.5
/
, /"
/'"
1.5
./'
V
~
/
2
V
-
High Side
/'
0.5
4
6
10
12
8
Vee - Supply Voltage - V
14
o
16
4
8
6
Figure 14
INPUT THRESHOLD VOLTAGE
vs
SUPPLY VOLTAGE
9
,
8
l
_ TJ=25'e
/
>
I
GI
~
7
5
s=
m
4
"S
r::L
3
I-
.5
I
!::
/
/'"
6
~
s=
/
/
V
/
V"
./
/
2
>
o
10
4
6
12
Vee - Supply Voltage - V
Figure 13
10
12
8
Vee - Supply Voltage - V
14
Figure 15
~TEXAS
INSTRUMENTS
9--58
..",-
~
."..-
V
-
1.5
--
1
TJ=25'e
3.5
./
~
2
~
~
./
r
/ /
2.5
PEAK SINK CURRENT
vs
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
16
14
16
TPS2830, TPS2831
FAST SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS196B - JANUARY1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
Figure 15 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001A
pulse-width-modulation (PWM) controller and a TPS2831 driver. The converter operates over an input range from
4.5 Vto 12 Vand has a 3.3-V output. The circuit can supply 3 A continuous load. The converter achieves an efficiency
of 94% for VIN = 5 V, Iload=1 A, and 93% for Vin = 5 V, Iload = 3 A.
If
VIN
+ 1\
C10
100IlF
C5
100llF
If
+ 1\
~(
R1
1 k.Q
U1
TPS2831
~
BOOT 14
ENABLE
2 IN
P
.-!
.........!
~
~
-::1-
NC ..!!.
12
CROWBAR HIGHDR
BOOTlO 11
NC
10
SYNC
lOWDR
NC ...L
DT
:~@
0
R6
1MO
C15
T1.01lF
Q1
SI441 0
0
1001l~
100IlF+
';::::::;
3.3 V
;::::::;
C7
C12
Q2
SI441 0
C14
11lF
C13
10llF
R7
3.30
Jf+
\1
--
~
r-
CSc:: ::::;
1000pF
GND
C6
rf
-=-
2
Vcc
1
OUT
FB
~ SCP
R8
121 k.Q
U2
TlS001A
C2
0.033IlF
COMP
6 DTC
..- ::::;
J
C3
0.OO22 1lF
0.11lF
t---
l1
27IlH
R11i'J§:
4.70
II
C9
0.221l~
-=-
--
Vcc ~
PGND
C11
0.47 1lF
RT
RTN
rlt-
Yt-
~
C4
0.0221lF
If
1.6k.Q
1
4
R3
1800
1\
'''1
R4
2.32 k.Q
~
GND
t - - - ;:: ::::- C1
..... 11lF
8
R9
90.9 kO
<
R10
1.0kO
Figure 16. 3.3-V 3-A Synchronous-Buck Converter Circuit
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
9-59
TPS2830, TPS2831
FAST SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS196B - JANUARY1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
Great care should be taken when laying out the pc board. The power-processing section is the most critical and
will generate large amounts of EMI if not properly configured. The junction of 01, 02, and L1 should be very
tight. The connection from 01 drain to the positive sides of C5, C1 0, and C11 and the connection from 02 source
to the negative sides of C5, C10, and C11 should be as short as possible. The negative terminals of C7 and
C12 should also be connected to 02 source.
Next, the traces from the MOSFET driverto the power switches should be considered. The BOOTLO signal from
the junction of 01 and 02 carries the large gate drive current pulses and should be as heavy as the gate drive
traces. The bypass capacitor (C14) should be tied directly across Vee and PGND.
The next most sensitive node is the FB node on the controller (terminal 4 on the TL5001A) This node is very
sensitive to noise pick up and should be isolated from the high-current power stage and be as short as possible.
The ground around the controller and low-level circuitry should be tied to the power ground as the output. If these
three areas are properly laid out, the rest of the circuit should not have any other EMI problems and the power
supply will be relatively free of noise.
~1ExAs
9-60
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
- REVISED SEPTEMBER 1999
DPACKAGE
(TOP VIEW)
• Floating Bootstrap or Ground-Reference
High-Side Driver
IN
PGND
DT
• Active Deadtime Control
• 50-ns Max Rise/Fail Times and 100-ns Max
Propagation Delay - 3-nF Load
• Ideal for High-Current Single or Mutiphase
Applications
• 2.4-A Typ Peak Output Current
• 4.5-V to 15-V Supply Voltage Range
• Internal Schottky Bootstrap Diode
• Low Supply Current ••• 3-mA Typ
• -40°C to 125°C Junction-Temperature
Operating Range
Vee
BOOT
HIGHDR
BOOTlO
lOWDR
description
The TPS2832 and TPS2833 are MOSFET drivers for synchronous-buck power stages. These devices are ideal
for designing a high-performance power supply using a switching controller that does not include suitable
MOSFET drivers on the Chip. The drivers are designed to deliver 2.4-A peak currents into large capacitive loads.
Higher currents can be controlled by using multiple drivers in a multiphase configuration. The high-side driver
can be configured as a ground-reference driver or as a floating bootstrap driver. An adaptive dead-time control
circuit eliminates shoot-through currents through the main power FETs during switching transitions and provides
high efficiency for the buck regulator.
The TPS2832 has a noninverting input. The TPS2833 has an inverting input. The TPS2832133 drivers, available
in 8-terminal SOIC packages, operate over a junction temperature range of -40°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TJ
-400 elo 125°e
SOIC
(D)
TPS2832D
TPS2833D
The 0 package is available taped and reeled. Add R
suffix 10 device type (e.g., TPS2830DR)
~TEXAS
INSTRUMENTS
POST OFFICE eox 655303 • DALLAS. TEXAS 75285
Copyright@ 1999. Texas Instruments Incorporated
!Hi1
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B - JANUARY 1999 - REVISED SEPTEMBER 1999
functional block diagram
4
8
7
(TPS2832 Only)
.
~
,--.....
6
VCC
BOOT
HIGHDR
BOOTLO
....
IN
I .....
~i
(TPS2833 Only)
5
2
LOWDR
PGND
DT
Terminal Functions
TERMINAL
NAME
NO.
1/0
DESCRIPTION
BOOT
8
I
Bootstrap terminal. A ceramic capacitor is connected between BOOT and BOOTLO terminals to develop
the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1 I1F
and 1 11F. A I-Mel resistor should be connected across the bootstrap capacitor to provide a discharge path
when the driver .has been powered down.
BOOTLO
6
0
This terminal connects to the junction of the high-side and low-side MOSFETs.
DT
3
I
Deadtime control terminal. Connect DT to the junction of the high-side and low-side MOSFETs
HIGHDR
7
0
Output drive for the high-side power MOSFET
IN
1
I
Input signal to the MOSFET drivers (noninverting input for the TPS2832; inverting Input for the TPS2833).
LOWDR
5
0
Output drive for the low-side power MOSFET
PGND
2
VCC
4
I
Input supply. Recommended that a 1 I1F capacitor be connected from VCC to PGND.
Power ground. Connect to the FET power ground.
~lExAs
9-62
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVSl95B -JANUARY 1999- REVISED SEPTEMBER 1999
detailed description
low-side driver
The low-side driver is designed to drive low Rds(on) N-channel MOSFETs. The current rating of the driver is
2 A, source and sink.
high-side driver
The high-side driver is designed to drive low Rds(on) N-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The high-side driver can be configured as a ground-reference driver or a floating bootstrap
driver. The internal bootstrap diode, is a Schottky for improved drive efficiency. The maximum voltage that can
be applied between the BOOT terminal and ground is 30 V.
deadtime (OT) controlt
Deadtime control prevents shoot through current from flowing through the main power FETs during switching
transitions by contrOlling the turn-on times of the MOSFET drivers. The high-side driver is not allowed to tum
on until the gate drive voltage to the low-side FET is low, and the low-side driver is not allowed to turn on until
the voltage at the junction of the power FETs (Vdrn) is low; the DT terminal connects to the junction of the power
FETs.
INt
The IN terminal is a digital terminal that is the input control signal forthe drivers. The TPS2832 has a noninverting
input; the TPS2833 has an inverting input.
tHigh-level input voltages on IN and DT must be greater than or equal to Vee.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
!HI3
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B - JANUARY 1999 - REVISED SEPTEMBER 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................. -0.3 V to 16 V
Input voltage range: BOOT to PGND (high-side driver ON) ............................. -0.3 V to 30 V
BOOTlO to PGND .............................................. -0.3 V to 16 V
BOOT to BOOTlO .............................................. -0.3 V to 16 V
IN (see Note 2) ................................................. -0.3 V to 16 V
DT (see Note 2) ................................................ -0.3 V to 30 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating virtual junction temperature range, TJ .................................... -40°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds ....................... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Unless otherwise specified, all voltages are with respect to PGND.
2. High-level input voltages on the IN and DT terminals must be greater than or equal to Vee.
DISSIPATION RATING TABLE
PACKAGE
TA:S; 25°C
POWER RATING
D
580mW
DERATING FACTOR
ABOVE TA 25°C
=
=
=
TA 70°C
POWER RATING
TA 85°C
POWER RATING
320mW
232mW
recommended operating conditions
MIN
Supply voltage, Vee
Input voltage
I BOOT to PGND
NOM
MAX
UNIT
4.5
15
V
4.5
28
V
electrical characteristics over recommended operating virtual junction temperature range,
Vce = 6_5 V, CL = 3_3 nF (unless otherwise noted)
supply current
PARAMETER
Vee
TEST CONDITIONS
Supply voltage range
MIN
TYP
4.5
Vee=15V
Vee
Vee =12 V,
fSWX = 200 kHz,
eHIGHDR = 50 pF,
Quiescent current
BOOTlO grounded,
eLOWDR = 50 pF,
See Note 3
NOTE 3: Ensured by design, not production tested.
~TEXAS
INSTRUMENTS
9--64
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
3
MAX
UNIT
15
V
100
I1A
mA
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B - JANUARY 1999 - REVISED SEPTEMBER 1999
electrical characteristics over recommended operating virtual junction temperature range,
Vee =6.5 V, CL =3.3 nF (unless otherwise noted) (continued)
output drivers
PARAMETER
High-side sink
(see Note 4)
Peak outputcurrent
TEST CONDITIONS
Duty cycle < 2%,
tpw < 100 I!S
(see Note 3)
MIN
TYP
VBOOT - VBOOTLO = 4.5 V, VHIGHDR = 4 V
0.7
1.1
VBOOT - VBOOTLO = 6.5 V, VHIGHDR = 5 V
1.1
1.5
2
2.4
1.4
VBOOT-VBOOTLO = 12V, VHIGHDR = 10.5 V
High-side
source
(see Note 4)
Duty cycle < 2%,
tpw < 100 I!S
(see Note 3)
VBOOT - VBOOTLO = 4.5 V, VHIGHDR = 0.5V
1.2
VBOOT - VBOOTLO = 6.5 V, VHIGHDR = 1.5 V
1.3
1.6
VBOOT-VBOOTLO = 12V, VHIGHDR = 1.5 V
2.3
2.7
Duty cycle < 2%,
tpw < 100 I!S
(see Note 3)
Vee=4.5V,
VLOWDR=4V
1.3
1.8
Low-side sink
(see Note 4)
Vee=6.5V,
VLOWDR=5V
2
2.5
Vee = 12V,
VLOWDR = 10.5 V
3
3.5
Duty cycle < 2%,
tpw < 100 I!S
(see Note 3)
Vee=4.5V,
VLOWDR = 0.5V
1.4
1.7
Vee = 6.5 V,
VLOWDR = 1.5 V
2
2.4
Vee=12V,
VLOWDR = 1.5 V
2.5
3
Low-side
source
(see Note 4)
High-side sink (see Note 4)
High-side source (see Note 4)
Output
resistance
Low-side sink (see Note 4)
Low-side source (see Note 4)
MAX
UNIT
A
A
A
A
VBOOT - VBOOTLO = 4.5 V, VHIGHDR = 0.5 V
5
VBOOT - VBOOTLO = 6.5 V, VHIGHDR = 0.5 V
5
VBOOT - VBOOTLO = 12 V, VHIGHDR = 0.5 V
5
VBOOT - VBOOTLO = 4.5 V, VHIGHDR = 4 V
45
VBOOT - VBOOTLO = 6.5 V, VHIGHDR = 6 V
45
VBOOT - VBOOTLO = 12 V, VHIGHDR =11.5 V
45
VDRV= 4.5 V,
VLOWDR = 0.5 V
9
VDRV=6.5V
VLOWDR = 0.5 V
7.5
VDRV= 12V,
VLOWDR = 0.5 V
6
VDRV=4.5V,
VLOWDR=4V
45
VDRV= 6.5 V,
VLOWDR=6V
45
n
n
n
n
45
VDRV= 12V,
VLOWDR = 11.5 V
NOTES: 3. Ensured by design, not production tested.
4. The pull-up/pull-down circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the Rds(on) of the MOSFET transistor when
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
deadtlme
TEST CONDITIONS
PARAMETER
LOWDR
DT
High-level input voltage
Over the Vee range (see Note 3)
Low-level input voltage
High-level input voltage
Over the Vee range
Low-level input voltage
MIN
TYP
MAX
2
UNIT
V
1
2
V
V
1
V
NOTE 3: Ensured by design, not production tested.
digital control terminals
PARAMETER
High-level input voltage
Low-level input voltage
TEST CONDITIONS
Over the Vee range
MIN
TYP
MAX
2
UNIT
V
1
V
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9-65
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B - JANUARY 1999 - REVISED SEPTEMBER 1999
switching characteristics over recommended operating virtual junction temperature range,
CL = 3.3 nF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
HIGHDR output
(see Note 3)
Rise time
LOWDR output
(see Note 3)
HIGHDR output
(see Note 3)
Fall time
LOWDR output
(see Note 3)
Driver nonoverlap time
NOTE 3:
TYP
I
MAX
60
VBOOT = 6.5 V,
VBOOTLO=OV
50
VBOOT=12V,
VBOOTLO=OV
50
Vee=4.5V
40
Vee=6.5V
30
Vee=12V
30
VBOOT = 4.5 V,
VBOOTLO=OV
60
VBOOT = 6.5 V,
VBOOTLO=OV
50
VBOOT=12V,
VBOOTLO=OV
50
Vee=4.5V
40
Vee=6.5V
30
Vee = 12V
30
VBOOT = 4.5 V,
VBOOTLO=OV
130
VBOOT = 6.5 V,
VBOOTLO=OV
100
VBOOT=12V,
VBOOTLO=OV
75
LOWDR going high
(excluding deadtime)
(see Note 3)
VBOOT = 4.5 V,
VBOOTLO=OV
80
VBOOT = 6.5 V,
VBOOTLO=OV
70
VBOOT= 12 V,
VBOOTLO=OV
60
LOWDR going low
(excluding deadtime)
(see Note 3)
Vee=4.5V
80
Vee=6.5V
70
Vee = 12V
60
DT to LOWDR and
LOWDR to HIGHDR
(see Note 3)
Vee = 4.5 V
40
170
Vee=6.5V
25
135
Vee=12V
15
85
Ensured by design, not production tested.
~TEXAS
9-66
I
HIGH DR going low
(excluding deadtlme)
(see Note 3)
Propagation delay time
Propagation delay time
MIN
VBOOTLO=OV
VBOOT = 4.5 V,
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B - JANUARY 1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
FALL TIME
RISE TIME
va
va
SUPPLY VOLTAGE
SUPPLY VOLTAGE
50
\.
45
...
,
40
I
...
~
35
i
....
I
.....
30
25
-
I
~
I
;
35
l
......
30
1=
I\.
High Side
i\...
-
I
Low Side
25
20
20
15
15
10
......
"
Low Side
10
4
5
6
7 8
9 10 11 12 13
VCC - Supply Voltage - V
14 15
4
5
6
7 8
9 10 11 12 13
Vee -SUpply Voltage - V
Figure 1
50
45 40
...
35
I
til
E
1=
30
....
25
,;
II:
FALL TIME
va
va
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
50
II
VCC=6.5V
CL=3.3nF
--
45
I
High Side
----
V
20
...c
I
--
-
I
30
l
......
25
I
20
0
25
50
75
100
TJ - Junction Temperature - °C
125
--
High Side
15
-25
VCC=6.5V
CL = 3.3 nF
35
1=
15
10
-SO
.t
I
r-
40
~
Low Side
I
14 15
Figure 2
RISE TIME
c
-
40
c
High Side
E
1=
-' = 1
l
CL
3.3 nF
TJ=25°C
45
r\
c
til
50
L
1 !
CL=3.3nF
TJ=25°C
10
-50
---
-
,......
V
, ,.
./
/
Low Side
~
-25
0
25
50
75
100
TJ - Junction Tempereture - °C
125
Figure 4
Figure 3
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
9-67
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B - JANUARY 1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
I!!
I
~
1=
>0
~
Q
c
.2
SUPPLY VOLTAGE, HIGH TO LOW LEVEL
\
\
80
.....
60
50
40
30
20
130
4
>0
120
5
100
~
Q
90
"
5
r-- ..........
Low Side
6
J
High Side
......... t--..
7
8
9
10
..........
11
r--... .......
........
:--
-
12 13
J
j
\
-
High Side
\.
70
r--. .......
.......
60
I
40
30
20
14 15
\
90
80
50
::t:
,
110
.2'
.....
Low Side
...... ' 4
5
6
Vee - Supply Voltage - V
7
JUNCTION TEMPERATURE
I
vs
I
I!!
Vee=6.5V
_ eL=3.3nF
I
~
1=
120
110
---- ---- - --
~
-
30
20
-50
-25
o
25
50
75
100
130
120
5
100
I
D.
~
~
I
~
150
I
..J
§
125
II
140 -
>0
~
Low Side
D.
_
Vee = 6.5 V
eL=3.3nF
110
90
80
70
60
50
40
30
20
-50
---
High Side
-
-25
TJ - Junction Temperature - °e
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
.-"
V
--
o
25
........
-
Low Side
I
I
50
75
TJ - Junction Temperature - °e
Figure 8
Figure 7
9-68
14 15
HIGH-To-LOW PROPAGATION DELAY TIME
....... ~
..J
12 13
11
vs
JUNCTION TEMPERATURE
High Side
::t:
10
Figure 6
140 >0
9
LOW-TO-HIGH PROPAGATION DELAY TIME
150
~
8
r--. .......
Vee - Supply Voltage - V
Figure 5
130
~
I
eL=3.3nF
TJ = 25 °e
140
\
110
70
150
~
\
120
:§,
~
~
J
vs
eL= 3.3 nF
TJ=25°e
130
I£
I
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE, LOW TO HIGH LEVEL
150
140
100
1
-~
LOW-TO-HIGH PROPAGATION DELAY TIME
100
125
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B -JANUARY 1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
FALL TIME
VB
LOAD CAPACITANCE
RISE TIME
vs
LOAD CAPACITANCE
1000
1000
f:
=VCC=6.5V
=TJ=25°C
VCC=6.5V
~TJ=25°C
!!!
I!!
100
I
100
I
~
,...- ~
f---
i
I
.:
-
:r
......-: ;;...
Low Side
...... 1--'
10
~
HlglISlde
I
::-
=.
High Side
V
10
......
LowS/de
1/
1
1
0.1
10
100
0.1
10
Figure 9
Figure 10
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
6000
5500
t-
/
TJ=25°C
CL=50pF
5000
c(
::L
I
4000
300k~
3000
::I
I
0
j}
2000
r--
100kHz, /
"
5OkHZX"
25kHz,
.I~ )<
1500
/
1000
o
4
6
X
-
-"
15r--~--r-~~~+--~--;
,,/
10r--+---r.~~--~~4---;
./
'lII
"'"
"'~
~~
V"
.......-:: ~ ,.....
~
500
/
X
200kHz
~
a. 2500
Ul
2Or--~--r-~--+-~~--;
500k~y
1:
3500
~
::I
0
TJ=25°C
CL=50pF
/
4500
100
CL - Load capacitance - nF
CL - Load Capacitance - nF
V
V
-
,,/
~
10
12
14
8
VCC - Supply Voltage - V
O,:-_~_-,:-_--::,:--_:,:-_-"-:-_--'
16
4
Figure 11
6
8
10
12
VCC - Supply Voltage - V
14
16
Figure 12
~TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALlAS. TEXAS 75265
9-69
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SlVS195B - JANUARY 1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
PEAK SINK CURRENT
PEAK SOURCE CURRENT
4
vs
vs
DRIVE VOLTAGE
DRIVE VOLTAGE
4
I
I
TJ=25°e
TJ = 25 °e
3.5
.-"""
3
""
LOW~
I
!
(,)
~
::I
c8
...
2.5
V
/
2
./
3
~V-
""C
~
::I
...c
iii
.....
2.5
2
(,)
High Side
/
1.5
/
V
/'fI'
l.
0.5
/
,/
/'
~
~
~
High Side
0.5
o
4
6
8
10
12
o
14
16
4
6
Vee - Supply Voltage - V
10
12
8
Vee - Supply Voltage - V
Figure 13
Figure 14
INPUT THRESHOLD VOLTAGE
vs
SUPPLY VOLTAGE
9
8
I
f-
/
TJ=25°e
/
>
I
QI
7
/
Cl
~
6
.c
~
..
5
.c
I!!
4
'S
Q.
3
~
I-
.5
I
I::
/"
/
V
./
V
",
2
>
o
4
6
8
10
12
14
Vee - Supply Voltage - V
Figure 15
~TEXAS
9-70
./'
V--
LOWS~ , /
I
./
-
i
...-
,/
/ V
1.5
3.5
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
16
14
16
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B - JANUARY 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
Figure 15 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001 A
pulse-width-modulation (PWM) controller and a TPS2833 driver. The converter operates over an input range from
4.5 V to 12 V and has a 3.3 V output. The circuit can supply 3 A continuous load and the transient load is 5 A. The
converter achieves an efficiency of 94% for VIN = 5 V, Iload=1 A, and 93% for Yin = 5 V, Iload = 3 A.
If
+1\
C10
100llF
VIN
C5
100llF
If
+ 1\
If
?
R1
1 kO
:;{E
U1
TPS2833
1 IN
BOOT
~
--.-!
PGND HIGHDR
BOOTLO
r-- ~ DT
LOWDR
~
;;: ==- C15
[""'1.0IlF
7
6
5
'v,A
R6
1 MO
Q1
SI441 0
r
rvv
l
.\L
R11{E
4.70
J~
v
C13
10llF
R7
3.30
3.3 V
';;:[::;
C7
C12 100llF :!;::"
100llF
~
Q2
SI441 0
';;: ~
C6~1
i'
1000 pF
GND
C8
r
l
-=-
2
Vcc
1 OUT
C1
;;;0" 11'F
'J-
RTN
r-1t~
~t- 1.6kO
FB 4
C4
0.0221lF
R3
1800
r~
1
R4
2.32 kO
RT ~
5
121 kO
U2
TLS001A
C2
0.0331lF
COMP
6 DTC
=~;::r; R8 r:~
-
C3
O.OO22IlF
O·~t
~
L1
271'H
--
II
C14
11lF
C
-=-
~
Vcc
C9Il
1\
C11
0.47 1lF
GND
8
R9
9O.9kO
R10
1.0kO
Figure 16. 3.3 V 3 A Synchronous-Buck Converter Circuit
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
9-71
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B - JANUARY 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
Great care should be taken when laying out the pc board. The power-processing section is the most critical and
will generate large amounts of EMI if not properly configured. The junction of Q1, Q2, and l1 should be very
tight. The connection from Q1 drain to the positive sides of C5, C1 0, and C11 and the connection from Q2 source
to the negative sides of C5, C10, and C11 should be as short as possible. The negative terminals of C7 and
C12 should also be connected to Q2 source.
Next, the traces from the MOSFET driver to the power switches should be considered. The BOOTlO signal from
the junction of Q1 and Q2 carries the large gate drive current pulses and should be as heavy as the gate drive
traces. The bypass capaCitor (C14) should be tied directly across Vee and PGND.
The next most sensitive node is the FB node on the controller (terminal 4 on the Tl5001A) This node is very
sensitive to noise pick up and should be isolated from the high-current power stage and be as short as possible.
The ground around the controller and low-level circuitry should be tied to the power ground as the output.lfthese
three areas are properly laid out, the rest of the circuit should not have any other EMI problems and the power
supply will be relatively free of noise.
~TEXAS
9-72
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
General Information (Vol. 1)
Linear Voltage Regulators
Shunt Regulators
I Precision Virtual Grounds
Mechanical Data
General Information (Vol. 2)
Processor PS Controllers
Switching PS and DC/DC Converters
MOSFET Drivers
Supervisors
Mechanical Data
General Information (Vol. 3)
Power Distribution Switches
LED Drivers
Voltage Rail Splitters
Special Functions
Mechanical Data
10-1
10-2
TPS3809J25, TPS3809L30, TPS3809K33, TPS3809150
3-PIN SUPPLY VOLTAGE SUPERVISORS
TPS3809 ..• DBV PACKAGE
(TOP VIEW)
• 3-Pin SOT-23 Package
• Supply Current of 9 !lA (Typical)
• Precision Supply Voltage Monitor
2.5 V, 3 V, 3.3 V, 5 V
GNDU
3
VDD
• Power-On Reset Generator With Fixed
Delay Time of 200 ms
RESET
2
• Pin-For-Pin Compatible With MAX 809
• Temperature Range ... -VIT
RESET
0
1
L
TPS380
lll
J
9
H
2S DBlV
l
Reel
Package
Nominal Supply Voltage
Nominal Threshold Voltage
Functionality
Family
functional block diagram
r-----------------------,
,,
,
,,
-!-,------'
,,,
,,
,
,
,,
TPS3809
,
,
RUM
~
~~
VDD -+--..J\I'I/Ir--......- - - I
,
Timer
,
+
R2
GND
Reference
Voltage
of 1.137 V
~-----------------------~
~TEXAS
10-4
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS3809J25, TPS3809L30, TPS3809K33, TPS3809150
3-PIN SUPPLY VOLTAGE SUPERVISORS
SLVS228 - AUGUST 1999
timing diagram
VDD
VeNOM)
Vrr
1.1 V
o
For VDD< 1.1 V Undefined
Behavior of RESET Output
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage, Voo (see Note1) .............................................................. 7 V
All other pins (see Note 1) ........................................................... -0.3 V to 7 V
Maximum low output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 mA
Maximum high output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -5 mA
Input clamp current, IrK (VrVoo) ................................................... ±20 mA
Output clamp current, 10K (VOVoo) .............................................. , ±20 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. See Dissipation Rating Table
Operating free-air temperature range, TA ............................................. -40°C to 85°C
Storage temperature range, Tstg .................................................... -65°C to 150°C
Soldering temperature .................................................................... 260°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voHage values are with respect to GND. For reliable operation the device should not be operated at 7 V for more than t=1000h
continuously.
DISSIPATION RATING TABLE
=
PACKAGE
TA<25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA 85°C
POWER RATING
DBV
437mW
3.5 mW/"C
280 mW
227 mW
recommended operating conditions at specified temperature range
Supply voltage, VOD
Operating free-air temperature range, TA
MIN
MAX
2
6
UNIT
V
-40
85
°C
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-5
TPS3809J25, TPS3809L30, TPS3809K33, TPS3809150
3·PIN SUPPLY VOLTAGE SUPERVISORS
SLVS228-AUGUST 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VOO = 2.5 V to 6 V, IOH = -500 iJA
VOH
VOL
High-level output voltage
Low-level output voltage
IOH=-2mA
VOO-Q.4
VOO=6V,
IOH=-4mA
VOO-Q.4
Negative-going input threshold
voltage (see Note 3)
TPS3809L30
TPS3809K33
IOL= 500iJA
0.2
IOL=2mA
0.4
VOO=6V,
IOL=4 mA
0.4
1.1 V,
Hysteresis
0.2
IOL= 50 iJA
TA- 40°C to 85°C
2.20
2.25
2.30
2.58
2.64
2.70
2.87
2.93
2.99
4.45
4.55
4.65
TPS3809J25
30
TPS3809L30
35
TPS3809K33
40
TPS3809150
100
Supply current
CI
Input capacitance
UNIT
V
VOO =2 Vto 6 V,
TPS3809150
Vhys
MAX
VOO=3.3V,
TPS3809J25
VIT-
TYP
VOO=3.3V,
VOO~
Power-up reset voltage (see Note 2)
MIN
VOO-Q·2
V
V
V
mV
60
VOO = 2 V, Output unconnected
9
12
VOO = 6 V, Output unconnected
20
25
5
VI =OVtoVOO
iJA
pF
NOTES: 2. The lowest supply voltage at which RESET becomes active. tr VOO ~ 15 JlS/V.
3. To ensure best stability of the threshold voltage, a bypass capacitor (0.1 I1F ceramic) should be placed near the supply terminals.
timing requirements at RL = 1 Mil, CL = 50 pF, TA = 25°C
TEST CONDITIONS
tw
Pulse width
VOO= VIT_+0.2 V,
MIN
VOO = VIT- - 0.2 V
TYP
MAX
3
switching characteristics at RL = 1 MQ, CL = 50 pF, TA = 25°C
PARAMETER
Id
Oelaytime
tPHL
Propagation (delay) time, high-to-Iow-Ievel output
I
VOO to RESET delay
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOO ~VIT_+O.2 V,
See timing diagram
120
200
280
ms
VIL = VIT_-0.2 V,
VIH = VIT- +0.2 V
~TEXAS
10-6
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
I1S
TPS3809J25, TPS3809L30, TPS3809K33, TPS3809150
3-PIN SUPPLY VOLTAGE SUPERVISORS
SLVS228-AUGUST 1999
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
LOW-LEVEL OUTPUT VOLTAGE
2.75
vs
vs
LOW-LEVEL OUTPUT CURRENT
SUPPLY VOLTAGE
r---~---r--"TT"-TT"1,.....-r----.
50
Voo= 2.5 V
2.50
TA=25°C
I---+---+---#--~HI--t
40
30
.------
C
::l.
20
I
C
~::s
10
0
0
~
Co
::s
TPS3809J25
~
-10
III
I
-20
Q
E
-30
-40
-50
2.5
5.0
7.5
10.0
IOl - low-level Output Current - mA
o
-2
12.5
2
4
Voo - Supply Voltage - V
Figure 1
Figure 2
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
6.5
6.0
>
I
III
5.5
I
5.0
~
4.5
"S
.e
::s
4.0
0
3.5
l!
3.0
!I
J:.
2.5
II
2.0
x
~
3.00
VOO=6V
~
>
I
"""
""~
1l!
T"I"°C-
~'(
A ~ '\. TA=O°C
~
TA=~50C\
\
\/f \
1.0
TA = 25°
0.5
o
III
Cl
~
o
VOO=2.5V
2.75
~
~~
1.5
6
\y
V\
2.50
2.25
~
2.00
!
0
1.75
"S
Gi
>
III
1-
1.00
0.75
~ 0.50
\
0.25
1\
-10
-20
-30
-40
IOH - High-level Output Current - mA
-50
."S ~
'"
~
1.25
I
X
~
1.50
Cl
:E
~
o
o
Figure 3
TA=/soC
"I
~"" ~A=OOC
~ 'l~'
~~
C\
+A=25 0
I
TA=-40°C
I
\
,
\
~
1\
\
\
\
-4
-8
-2
-6
IOH - High-level Output Current - mA
-10
Figure 4
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-7
TPS3809J25, TPS3809L30, TPS3809K33, TPS3809150
3-PIN SUPPLY VOLTAGE SUPERVISORS
SLVS22B-AUGUST 1999
TYPICAL CHARACTERISTICS
NORMALIZED INPUT THRESHOLD VOLTAGE
P
vs
FREE·AIR TEMPERATURE AT VDD
VDD THRESHOLD OVERDRIVE VOLTAGE
1.001
=
VDD 2.3 V
I::
0.999
t
0.998
>
$!
/
I
0.997
~
]
I
Z
0.996
I
1/ "-
V
>
2.5
~
2.0
1&
c
~
:::I
Q
"-
J
E
:::I
E
/
'c
i
I
~
-20
0
20
40
60
TA - Free-Air Temperature _·c
85
\
\
\
1.5
\
1.0
o
0.2
0.4
0.8
0.6
VDD - Threshold Overdrive Voltage - V
Figure 6
Figure 5
~TEXAS
10-8
'\....
0.5
o
0.995
-40
3.0
Q
Q
............
:2
o
i
III
::I.
I
1.000
cc
l::-
3.5
I
&
;
MINIMUM PULSE DURATION AT VDD
vs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
1.0
TLC7701, TLC7725,TLC7703,TLC7733,TLC7705
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
D, JG, P OR PW PACKAGE
• Power-On Reset Generator
(TOP VIEW)
• Automatic Reset Generation After
Voltage Drop
CONTROL
RESIN
CT
GND
• Precision Voltage Sensor
• Temperature-Compensated Voltage
Reference
3
4
5
RESET
• Programmable Delay Time by External
Capacitor
• Supply Voltage Range •.• 2 V to 6 V
U PACKAGE
(TOP VIEW)
• Defined RESET Output from VDO ~1 V
• Power-Down Control Support for Static
RAM With Battery Backup
• Maximum Supply Current of 16 J,1A
• Power Saving Totem-Pole Outputs
• Temperature Range ••• -40°C to 125°C
NC
CONTROL
RESIN
CT
GND
NC
Voo
SENSE
RESET
RESET
description
FKPACKAGE
(TOP VIEW)
The TLC77xx family of micropower supply voltage
supervisors provide reset control, primarily in
microcomputer and microprocessor systems.
During power-on, RESET is asserted when VDD
reaches 1 V. After minimum VDD (~ 2 V) is
established, the circuit monitors SENSE voltage
and keeps the reset outputs active as long as
SENSE voltage (VI(SENSE» remains below the
threshold voltage. An internal timer delays return
of the output to the inactive state to ensure proper
system reset. The delay time, td, is determined by
an external capacitor:
td=2.1 x104 xCT
..J
0
ex:
~
NC
RESIN
NC
CT
NC
4
5
6
7
8
IZ
3 2 1 2019
18
17
16
15
14
9 10 11 12 13
() Cl ()
Z Z Z
C!l
Where
CT is in farads
td is in seconds
Cl
8 ~ $l~
NC
SENSE
NC
RESET
NC
jtuCJ)Z()
w
ex:
Except for the TLC7701, which can be customized with two external resistors, each supervisor has a fixed
SENSE threshold voltage set by an internal voltage divider. When SENSE voltage drops below the threshold
voltage, the outputs become active and stay in that state until SENSE voltage returns above threshold voltage
and the delay time, ~, has expired.
~:;n..,ONnro:1:~~~~~'::!'::=~':'~
Production processing does nol neceuarily include
standard~.
tosIlng of all parametors.
~lEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
10--9
TLC7701,TLC7725,TLC7703,TLC7733,TLC7705
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVS087K - DECEMBER 1994 - REVISED JULY 1999
description (continued)
In addition to the power-on-reset and undervoltage-supervisor function, the TLC77xx adds power-down control
support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor
contains additional logic intended for control of static memories with battery backup during power failure. By
driving the chip select (CS) of the memory circuit with the RESET output of the TLC77xx and with the CONTROL
driven by the memory bank select signal (CSH1) of the microprocessor (see Figure 10), the memory circuit is
automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the
battery.)
The TLC77xxi is characterized for operation over a temperature range of -40°C to 85°C; the TLC77xxQ is
characterized for operation over a temperature range of -40°C to 125°C; and the TLC77xxM is characterized
for operation over the full Military temperature range of -55°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
THRESHOLD
VOLTAGE
TA
(V)
SMALL
OUTLINE (D)t
CHIP
CARRIER (FK)
CERAMIC DIP
(JG)
-
-
1.1
TLC770110
2.25
TLC772510
2.63
TLC770310
2.93
TLC773310
4.55
TLC770510
1.1
TLC7701QO
-40°C
to
125°C
2.25
TLC772500
2.63
TLC770300
2.93
TLC7733QO
4.55
TLC7705QO
-55°C
to
125°C
2.93
-
-4O"C
to
85°C
4.55
CERAMIC
DUAL
FLATPACK
(U)
-
PLASTIC DIP
(P)
-
TLC7701IP
TLC77251P
TLC77251PW
TLC7703IP
TLC7703IPW
-
TLC7733IP
TLC7733IPW
TLC7705IP
TLC7705IPW
TLC7701QP
TLC7701QPW
TLC7725QP
TLC7725QPW
-
-
TLC7733MFK
TLC7733MJG
-
TLC7705MFK
TLC7705MJG
TLC7705MU
-
THIN SHRINK
SMALL
OUTLINE
(P\Vl*
TLC7701IPW
TLC77030P
TLC77030PW
TLC7733QP
TLC7733QPW
TLC7705QP
TLC7705QPW
-
-
t The 0 package Is available taped and reeled. Add the suffix R to the device type when ordering (e.g., TLC7705QOR).
:j: The PW package Is only available left-end taped and reeled (lndlceted by the LE suffix on the device type; e.g., TLC7705QPWLE).
logic symbol~
FUNCTION TABLE
CONTROL
RESIN
L
L
VI(SENSE»VIT+
False
RESET
RESET
H
L
L
L
True
H
L
L
H
False
L
H§
SENSE
7
2
n
COMP.rr
S S !d.
C >1
Jl...
CX
;;,1
;;,1
;;,1
Z1
Z2
Z3
5
6
RESET
3
11 This symbol is in accordance wIIh ANSIIlEEE Sid 91-1984 and
IEC Publication 617-12.
~TEXAS
10-10
INSTRUMENTS
POST OFFICE BOX 655308 • DALLAS. TEXAS 75286
TLC7701,TLC7725,TLC7703,TLC7733,TLC7705
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVS087K - DECEMBER 1994 - REVISED JULY 1999
functional block diagram
VDD
CONTROL~1-------'----~--------------1-----------~
RESETt
RESIN -=2:...-____-+____+-____--,
R1;
SENSE -=.7---101/II'v-.-+____+---1
GND
3
CT
t Outputs are totem-pole configuration. External pullup or pulldown resistors are not required.
; Nominal values:
R1 (Typ)
R2 (Typ)
TLC7701
0
co
TlCn25
600 kn
600kn
502kn
TlCn03
698kn
TlC7733
750kQ
450kn
TLCn05
910kn
290kO
timing diagram
Threshold Voltages
Vres -
Output
Undefined
I
I"
I
I
I
I
I
I
~
I
I
1--
I
I
I
I
I
I
~
Id
~TEXAS
INSTRUMENTS
POST OFFICE eox 655303 • OALLAS. TEXAS 75265
10--11
TLC7701,TLC7725,TLC7703,TLC7733,TLC7705
MICROfiOWEH SUPPLY VOLTAGE SUPERVISORS
SLVS087K - DECEMBER 1994 - REVISED JULY 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage, Voo (see Note 1) .......................................................... , 7 V
Input voltage range, CONTROL, RESIN, SENSE (see Note 1) .......................... -0.3 V to 7 V
Maximum low output current, IOL .......................................................... 10 rnA
Maximum high output current, IOH ....................................................... -10 rnA
Input clamp current, 11K (VI < 0 or VI> Voo) . ..... . . . .. .... . ..... ..... . .. ... .... . . .. .. . ... ±10 rnA
Output clamp current, 10K (Vo < 0 or Vo > Voo) ........................................... ±10 rnA
Continuous total power dissipation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. See Dissipation Rating Table
Operating free-air temperature range, TA: TL77xxl ................................... -40°C to 85°C
TL77xxQ ................................. -40°C to 125°C
TL77xxM ................................. -55°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GNO.
DISSIPATION RATING TABLE
PACKAGE
DERATING FACTOR
ABOVE TA = 25°C
TAS25°C
POWER RATING
=
TA 85°C
POWER RATING
TA = 125°C
POWER RATING
0
725mW
5.8mW/"C
377mW
145mW
FK
1375mW
11.0mW/oC
715mW
275mW
JG
1050mW
8.4mW/oC
546mW
210mW
P
l000mW
8.0mW/oC
520mW
200mW
PW
525mW
4.2mW/"C
273mW
105mW
U
700mW
5.5mW/"C
370mW
150mW
recommended operating conditions at specified temperature range
MIN
MAX
UNIT
Supply vollage, VOO
2
6
V
Input VOltage, VI
0
VOO
V
High-level input voltage at RESIN.and CONTROL:!:. VIH
LOW-level input vo~age at RESIN and CONTROL:!:. VIL
High-level output current, IOH
Low-level output current. IOL
VOO~2.7V
Input transition rise and fall rate at RESIN and CONTROL. t.VI!1V
Operating free-air temperature range, TA
Operating free-air temperature range, TA
O.2xVOO
V
-2
rnA
2
rnA
100
ns/V
TLC77xxl
-40
85
TLC77xxQ
-40
125
TLC77xxM
-55
125
:!:To ensure a low supply current. VIL should be kept <0.3 V and VIH > VOO-0.3 V.
~1EXAS
INSTRUMENTS
10-12
V
0.7xVOO
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
°C
°C
TLC7701, TLC7725,TLC7703,TLC7733,TLC7705
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVS087K - DECEMBER 1994 - REVISED JULY 1999
electrical characteristics over recommended operating conditions (see Note 2) (unless otherwise
noted)
PARAMETER
VOH
High-level output voltage
TEST CONDITIONS
IOH =-20 IlA
IOH =-2 rnA
VOL
Low-level output voltage
IOL=20 IlA
IOL=2mA
VOO=2V
1.8
VOO=2.7V
2.5
VOO=4.5V
4.3
VOO=4.5V
3.7
0.2
0.2
VOO=4.5V
0.2
V
0.5
1.04
VOO=2Vto 6 V
TLC7733
TLC7705
TLC7701
UNIT
V
VOO=4.5V
TLC7703
MAX
VOO=2.7V
TLC7725
Negative-going input threshold voltage,
SENSE (see Note 3)
TYPt
VOO=2V
TLC7701
VIT-
TLcnxx
MIN
1.1
1.16
2.18
2.25
2.32
2.56
2.63
2.70
2.86
2.93
3
4.47
4.55
4.63
V
VOO =2 Vt06V
30
mV
VOO=2VIo6V
70
mV
TLC7725
Vhys
Hysteresis voltage, SENSE
TLC7703,
TLC7733,
TLCn05
Vres
Power-up reset voltage:!:
RESIN
II
Input current
IOL=201lA
1
VI =OVtoVOO
2
CONTROL
VI=VOO
7
15
SENSE
VI=5V
5
10
SENSE, TLC7701 only
VI=5V
V
IlA
2
100
Supply current
RESIN = VOO,
SENSE = VOO '" VITmax + 0.2 V
CONTROL = 0 V, Outputs open
IOO(d)
Supply current during td
VOO = 5 V,
RESIN = VOO,
CONTROL = 0 V,
CI
Input capacitance, SENSE
VI =OVtoVOO
VCT=O,
SENSE=VOO,
Outputs open
9
16
IlA
120
150
IlA
50
pF
t TYPical values apply at TA = 25°C.
:!:The lowest supply voltage at which RESET becomes active. The symbol Vres is not currently listed within EIA or JEOEC standards for
semiconductor symbology. Rise time of VOO '" 15 JJ13IV.
NOTES: 2. All characteristics are measured with CT = 0.1 11F.
3. To ensure best stability olthe threshold voltage, a bypass capacitor (ceramic, 0.111F) should be connected near the supplyterrninals.
-!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
10-13
TLC7701,TLC7725,TLC7703,TLC7733,TLC7705
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVSOB7K - DECEMBER 1994 - REVISED JULY 1999
electrical characteristics over recommended operating conditions (see Note 2) (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOO=2V,
IOH = -20 j.LA
VOH
VOO=2.7V
High-level output
voltage
VOO=4.5V
IOH=-2mA
VOO=4.5V
VOO=2V
IOL = 20 j.LA
VOL
VOO=2.7V
Low-level output
voltage
VOO=4.5V
IOL=2mA
VITVhyS
Vres
Negative-going input threshold
voltage, SENSE (see Note 3)
VOO=4.5V
TLC7733
TLC7705
100
1.7
TA = 25°C
2.5
TA = -55°C to 125°C
2.3
TA = 25°C
4.3
TA = -55°C to 125°C
4.2
TA = 25°C
3.7
TA = -55°C to 125°C
3.6
V
0.2
TA = 25°C
TA = -55°C to 125°C
0.2
TA=25°C
0.2
TA = -55°C to 125°C
0.2
TA=25°C
0.2
TA = -55°C to 125°C
0.2
TA = 25°C
0.5
2.86
2.93
3.1
4.3
4.5
4.8
1
VI =OVtoVOO
2
Input current
70
CONTROL
VI=VOO
7
15
SENSE
VI=5V
5
10
SENSE, TLC7701 only
VI=5V
Supply current during td
Input capacitance, SENSE
VCT=O,
RESIN=VOO,
CONTROL = 0 V,
SENSE=VOO,
Outputs open
V
j.LA
2
RESIN=VOO,
SENSE = VOO ~ VITmax + 0.2 V
CONTROL = 0 V, Outputs open
Supply current
V
mV
IOL = 20 j.LA
VOO=2Vt06V
V
0.5
TA = -55°C to 125°C
VOO=2Vt06V
UNIT
1.8
TA = -55°C to 125°C
VOO = 2Vt06V
TLC7705
CI
MAX
Power-up reset voltage:!:
TLC7733
IOO(d)
TYpt
Hysteresis voltage, SENSE
RESIN
II
TA = 25°C
TLC77xxM
MIN
9
16
j.LA
250
VOO=3.3V
j.LA
VOO=5V
VI=OVtoVoO
120
50
150
pF
t Typical values apply at TA = 25°C.
:!:The lowest supply voltage at which RESET becomes active. The symbol Vres is not currently listed within EIA or JEOEC standards for
semiconductor symbology. Rise time of VOO ~ 151JSN.
NOTES: 2. All characteristics are measured with CT = 0.1 IlF.
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 IlF) should be placed near the supply terminals.
~TEXAS
10-14
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS. TEXAS 752115
TLC7701,TLC7725, TLC7703,TLC7733,TLC7705
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVS087K - DECEMBER 1994 - REVISED JULY 1999
switching characteristics at VDD
=5 V, RL =2 kg, CL =50 pF, TA =25°C
MEASURED
PARAMETER
TLC77xx
TO
FROM
(INPUT)
(OUTPUT)
RESET
Id
Delay time
V, (SENSE) ~ V,T+
and
RESET
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ieveloutput
tpLH
Propagation delay time,
low-to-high-Ievel output
SENSE
RESET
tr
Rise time
MAX
1.1
2.1
4.2
CT= 100 nF,
See timing diagram
V,H = V,T+max + 0.2 V,
V,L = V,T_min - 0.2 V,
Fall time
ms
5
RESIN = 0.7 x VDD,
CONTROL = 0.2 x VDD,
CT=NCt
lIS
5
RESIN
RESET
lIS
V,H = 0.7 x VDD,
V,L = 0.2 x VDD,
SENSE = V,T+max + 0.2 V,
40
CONTROL = 0.2 x VDD,
CT= NCt
45
ns
20
lIS
38
ns
38
ns
V,H = 0.7 xVDD,
RESET
V,L = 0.2 x VDD,
SENSE = V,T+max + 0.2 V,
RESIN = 0.7 x VDD,
CT= NCt
V,H = V,T+max + 0.2 V,
V,L = V,T_min - 0.2 V,
SENSE
V,L = 0.2 x VDD,
RESIN
V,H = 0.7 x VDD
RESET
3
lIS
1
10% to 90%
8
90% to 10%
4
nsN
and
tf
UNIT
RESIN = 0.7 x VDD,
CONTROL = 0.2 x VDD,
20
RESET
Propagation delay time,
high-to-Iow-Ievel output
Low-level minimum pulse
duration to switch RESET
and RESET
TYP
20
CONTROL
tpHL
MIN
20
RESET
Propagation delay time,
high-to-Iow-Ievel output
tpLH
TEST CONDITIONS
RESET
t NC = No capacitor, and includes up to 1Oo-pF probe and jig capacitance.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
10-15
TLC7701,TLC7725,TLC7703,TLC7733,TLC7705
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVS087K - DECEMBER 1994 - REVISED JULY 1999
switching characteristics at Voo = 5 V, RL = 2 k.a, CL = 50 pF
MEASURED
PARAMETER
I(!
tPLH
Delay time
Propagation delay
time, low-to-high-Ievel
output
TLC77XxM
FROM
(INPUT)
TO
(OUTPUT)
VI(SENSE) 2 VIT+
RESET
and
RESET
RESET
SENSE
RESET
tPHL
Propagation delay
time, high-to-Iow-Ievel
output
RESET
SENSE
RESET
tpLH
Propagation delay
time, Iow-to-high-Ievel
output
RESET
RESIN
RESET
tpHL
Propagation delay
time, high-to-Iow-Ievel
output
RESET
RESIN
RESET
tPLH
Propagation delay
time, low-to-high-Ievel
output
tpHL
Propagation delay
time, high-Io-Iow-Ievel
output
CONTROL
Low-level minimum
pulse duration
tr
Rise time
tf
Fall time
RESET
TEST CONDITIONS
RESIN = 2.7 V,
CONTROL = 0.4 V,
CT= 100 nF,
See timing diagram
VIH = VIT+max + 0.2 V,
VIL = VIT_min - 0.2 V,
RESIN = 2.7 V,
CONTROL = 0.4 V,
CT=NCt
VIH = VIT+max + 0.2 V,
VIL = VIT.JIlIn - 0.2 V,
RESIN = 2.7 V,
CONTROL = 0.4 V,
CT=NCt
VIH = 2.7 V,
VIL=0.4V,
SENSE = VIT+max + 0.2 V,
CONTROL = 0.4 V,
CT=NCt
VIH = 2.7 V,
VIL=0.4V,
SENSE = VIT+max + 0.2 V,
CONTROL = 0.4 V,
CT=Nct
VIH=2.7V,
VIL= 0.4 V,
SENSE = VIT+max + 0.2 V,
RESIN = 2.7 V,
CT=NCt
SENSE
VIH = VIT+max + 0.2 V,
VIL = VIT.JIlin - 0.2 V,
RESIN
VIL= 0.4 V,
VIH = 2.7V
RESET
and
RESET
10% to 90%
90% to lOOk
t NC = No capacitor, and Includes up to l00-pF probe and Jig capaCitance.
~1ExAs
10-16
INSTRUMENTS
POST OFFICE BOX Il55303 • DALLAS. TEXAS 75265
TA
25°C
MIN
TYP
MAX
1.1
2.1
4.2
25°C
20
Full
range
24
25°C
5
Full
range
7
25°C
5
Full
range
7
25°C
20
Full
range
24
25°C
20
Full
range
24
25°C
45
Full
range
65
25°C
40
Full
range
60
25°C
20
Full
range
24
25°C
38
Full
range
58
25°C
38
Full
range
58
Full
range
Full
range
UNIT
ms
JlS
JlS
JlS
JlS
JlS
ns
ns
JlS
ns
ns
a
JlS
1
8
nsN
4
TLC7701,TLC7725,TLC7703,TLC7733,TLC7705
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVS087K- DECEMBER 1994- REVISED JULY 1999
PARAMETER MEASUREMENT INFORMATION
,
5V
J
I
I
I
J
I
I
I
RL
(see Note A)
.J
-=-
-=-
I
CL
(see Note B)
-=-
NOTES: A. For switching characteristics, RL = 2 kn.
B. CL = 50 pF Includes Jig and probe capacitance.
Figure 1. RESET AND RESET Output Configurations
I, Q, and Y suffixed devices
I+- tw(L) --.I
I
I
~
JC::'
"-----L___
0.7xV OO
0.5 x VOO
0.2 x VOO
M suffixed devices
I+I
~
Iw(L)
--.I
I
14-
JC::'
"-----L_~=
2.7 V
1.5V
0.4V
tw(L)
--.I
~I
I
VIT+max+200mV
- - VIT+
- - - VITJnln-200mV
VIT_
(a) RESIN
(b) SENSE
Figure 2. Input Pulse Definition Waveforms
~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
10-17
TLC7701,TLC7725,TLC7703,TLC7733,TLC7705
NliCROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVSOB7K - DECEMBER 1994 - REVISED JULY 1999
TYPICAL CHARACTERISTICS
NORMALIZED INPUT THRESHOLD VOLTAGE
u
o~
tl:
~
~
.J.
vs
TEMPERATURE
SUPPLY VOLTAGE
1.005
10
9
1.004
1.003
>'
!
1.002
I
L
~ 1.001
!
~
S 0.999
)
./'
1/
V
0.998
./
/'
I/'
8
cc
:1.
I
~
a
I
7
6
5
~
V
I
r)
SUPPLY CURRENT
vs
8:
u:"
./
C
E
4
3
2
V
0.997
-40
o
-20
o
-1
20
40
60
100
80
lPJ
II
-0.5
120
RESIN = VDD = -1 V to 6.5 V
SENSE = GND
CONTROL = GND
CT = Open = 100 pF
TA = 25°C
It
0.5
TA - Temperature - °C
1.5
I
I
I
I
2.5
3.5
4.5
5.5
6.5
VDD - Supply Voltage - V
Figure 4
Figure 3
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
6
,
>
5
I
CD
4
VDD= 4.5 V
RESIN = 4.5 V
SENSE = 5 V
CONTROL=OV
CT = Open = 100 pF --/f-t--tf--f--lH-----I
I
~
S
f
3
125°C--'
0
]
0.5
o
-0.5
2
~
VDD=4.5V
RESIN = 4.5 V
SENSE = 0.5 V
CONTROL=OV
CT = Open = 100 pF
I
\ 1\ \ \ \
,_\\
\
~~~--~~--~~--~~--~-..~
5
o -s
-10 -15
-20 -25 -30 -35 -40
IOH - High-Level Output Current - mA
Figure 5
Figure 6
~lExAs
10-18
IOL - Low-Level Output Current - mA
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7701,TLC772S,TLC7703,TLC7733,TLC770S
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVS087K - DECEMBER 1994 - REVISED JULY 1999
TYPICAL CHARACTERISTICS
INPUT CURRENT
vs
INPUT VOLTAGE AT SENSE
8
II
VOO=4.5V
I
6 - CT = Open = 100 pF
125°~
4
~
-55°C
CC
2
::I.
I
C
l!!
".,., ~
0
~
0
p-
-2
S
a.
.5
I - 125°C
-4
I
-
-5~OC
~
-8
-10
-1
o
2
4
3
5
6
VI -Input Voltage at SENSE - V
Figure 7
MINIMUM PULSE DURATION AT SENSE
vs
SENSE THRESHOLD OVERDRIVE
..
::I.
I
w
7
6
\
!II
Z
!ll
5
'Iii
I
4
:::I
C
~E
:::I
1
I
_I
VOO=2V
Control = 0.4 V
RESIN = 1.4V
CT = Open = 100 pF
3
2
\
\
\
\
E
'2
i
'r-----
I
~
o
o
50
100
----
150
200
250
300
350
400
Sense Threshold Overdrive - mV
Figure 8
~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
10-19
TLC7701,TLC7725,TLC7703,TLC7733,TLC7705
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVS087K - DECEMBER 1994 - REVISED JULY 1999
APPLICATION INFORMATION
VDD---.----~~-----------.--------------------.
l
100kQ
o.1l1F
VDD
TLC77xx
.-----~------~RESIN
RESET~
I1F
VDD
RESET~---------1RESET
-I SENSE RESET
r--
CONTROL
r---
L -_ _ _ _ _ _
rCT
TO.1
NC
TMS70C20
.J:.
T
'-----r-l----'
GND
GND
Figure 9. Reset Controller In a Microcomputer System
,.....
~
vDD
I...0Il
..... 1
I
I
±
O.1I1F
VDD
1
I
TLC77xx
-
~O.1I1F
RESIN
qO.1 I1F
SENSE
-::r---
RESET
CSH1
TMS370
RESET
CONTROL
RESET
-
CT~
GND
T
-=l=-
ADoo-15
DATAO-7
16
8
Lcs
VDD
32K x 8
CMOS RAM
AO-A15
00-D7
R/W
R/W
GND
GND
.1
.1
Figure 10. Data Retention During Power Down Using Static CMOS RAMs
10-20
:'I
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS3123J12, TPS3123G15, TPS3123J18,TPS3124J12, TPS3124G15
TPS3124J18,TPS3125J12, TPS3125G15,TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY
CIRCUITS
SLVS227-AUGUST 1999
typical applications
• Minimum Supply Voltage of 0.75 V
• Supply Voltage Supervision Range:
- 1.2 V, 1.5 V, 1.8 V (TPS3123, TPS3124,
TPS3125)
- 3 V (TPS3125 Devices only)
• Power-On Reset Generator With Fixed
Delay Time of 180 ms
• Manual Reset Input (TPS3123 and TPS3125)
• Watchdog Timer Retriggers the RESET
Output at Voo ~ VIT
• Supply Current of 1411A (Typ)
• SOT23-5 Package
• Temperature Range ••• -40°C to 85°C
• Applications Using Low Voltage DSPs,
Microcontrollers or Microprocessors
•
•
•
•
•
•
•
Wireless Communication Systems
Portable/Battery-Powered Equipment
Programmable Controls
Intelligent Instruments
Industrial Equipment
Notebook/Desktop Computers
Automotive Systems
OBVPACKAGE
(TOP VIEW)
VOO
2.5 V
1.2V
I
WOI
vOO
MR
VOO
CVOO
TPS3125J12
GNO
r
19
U
MR
vOO
RESET
WOI
RESET
OVOO
GNO
Il
TMS320UVC5402
f+--
XF
f--+
RESET
WOI
VOO
RESET
:~~3823-25
J
GNO
GND
RESET
l
Figure 1. Typical Dual-Voltage DSP Application
description
The TPS3123, TPS3124, TPS3125 family of ultra-low voltage processor supervisory circuits provides circuit
initialization and timing supervision, primarily for DSP and processor-based systems.
During power-on, RESET is asserted when the supply voltage (Voo) becomes higher than 0.75 V. Thereafter,
the supply voltage supervisor monitors Voo and keeps RESET output active as long as Voo remains below the
threshold voltage VIT' An internal timer delays the return ofthe outputto the inactive state (high) to ensure proper
system reset. The delay time, ~typ 180 ms starts after Voo has risen above the threshold voltage VIT,
=
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
10-21
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 - AUGUST 1999
description (continued)
When the supply voltage drops below the threshold voltage VIT, the output becomes active (low) again. No
extemal components are required. All the devices of this family have a fixed-sense threshold voltage VIT set
by an intemal voltage divider.
The TPS3123-xx and TPS3125-xx devices incorporate a manual reset input, MR. A low level at MR causes
RESET to become active. The TPS3124-xx devices do not have the input MR, but include a high-level output
RESET same as the TPS3125-xx devices. In addition the TPS3123-xx and TPS3124-xx have a watchdog timer
that need to be triggered periodically by a positive or negative transition at WDI. When the supervising system
fails to retrigger the watchdog circuit within the time-out interval ttout = 0.8 s, RESET output becomes active for
the time period~. This event also reinitializes the watchdog timer.
The circuits are available in a 5-pin SOT23-5 package. The TPS3123, TPS3124, TPS3125 devices are
characterized for operation over a temperature range of -40°C to 85°C.
PACKAGE INFORMATION STANDARD VERSIONS
TA
-40°C to 85°C
DEVICE NAME
THRESHOLD VOLTAGE
TPS3123J12DBvrt
1.08V
PBNI
TPS3123G15DBVRt
TPS3123G15DBvrt
1.40V
PBCI
TPS3123J18DBVRt
TPS3123J18DBvrt
1.62V
PBPI
TPS3124J12DBVRt
TPS3124J12DBvrt
1.08V
PBal
TPS3124G15DBVRt
TPS3124G15DBvrt
1.4OV
PBRI
TPS3124J18DBVRt
TPS3124J18DBvrt
1.62V
PBSI
TPS3125J12DBVRt
TPS3125J12DBvrt
1.08V
PBTI
TPS3125G15DBVRt
TPS3125G15DBvrt
1.40V
PBUI
TPS3125J18DBVRt
TPS3125J18DBvrt
1.62V
PBVI
TPS3125L30DBVRt
TPS3125L30DBvrt
2.64 V
PBXI
t The DBVR passive Indicates tape and reel of 3000 parts.
:I: The DBVT passive Indicates tape and reel of 250 parts.
10-22
MARKING
TPS3123J12DBVRt
:lllExAs
INSTRUMENTS
POST OFFICE BOX tl55303 • DALLAS. TEXAS 75265
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 - AUGUST 1999
ordering Information application specific versions
TPS312
L
Reel
Package
Nominal Supply Voltage
3lJL12lD[
Typical Reset Threshold Voltage
Functionality
Family
DEVICE NAME
NOMINAL SUPPLY
VOLTAGE, VNOM
TYPICAL RESET
THRESHOLD
VOLTAGE-VIT_
DEVICE NAME
TPS312xx12DBV
1.2 V
TPS312xAxxDBV
VNOM-1%
TPS312xx15DBV
1.5V
TPS312xBxxDBV
VNOM-2%
TPS312xx18DBV
1.8V
TPS312xCxxDBV
VNOM-3%
TPS312xx30DBV
3.0V
TPS312xDxxDBV
VNOM-4%
TPS312xExxDBV
VNOM-5%
TPS312xFxxDBV
VNOM-6%
TPS312xGxxDBV
VNOM-7%
TPS312xHxxDBV
VNOM-8%
TPS312xlxxDBV
VNOM-9%
TPS312xJxxDBV
VNOM-10"k
TPS312xKxxDBV
VNOM-11%
TPS312xLxxDBV
VNOM-12%
TPS312xMxxDBV
VNOM-13%
TPS312xNxxDBV
VNOM-14%
TPS312xOxxDBV
VNOM-15%
NOTE: Ten standard versions will be available at product introduction.
For the application specific versions contact the lOcal TI sales office for availability and lead time.
Function Tables
TPS3123
TPS3124
TPS3125
RESET
RESET
MR
VDD>VIT
RESET
L
VDD>VIT
0
L
H
L
0
L
H
L
1
H
L
L
1
L
H
L
H
0
L
H
H
H
1
H
L
MR
VDD>VIT
RESET
L
0
L
1
H
0
H
1
RESET
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-23
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 - AUGUST 1999
functional block diagram
r-------------------~
Device Power Supply
VDD
R1
MRt--~--~~--------__,
R2
>-__-+/
Reset Logic
+ Timer
R3
RESET§
-+-----'
GND
IL
___________________ J
tTPS3123 and TPS3125 Only
:t:TPS3123 and TPS3124 Only
§TPS3124 and TPS3125 Only
timing diagram TPS3123 and TPS3125
VDD
VIT
@@
®
I
I
I
- - - -:- - - - - ,- - - - - - -, - - - - - - - - -, -
,,
,,
I
cO,85 V - - - - -
I
,,
I
I
I
I
I
I
- - - - -r - - - - - - r - - - - - - - - - r-
"
Jf
Output Undefined
Output Undefined
~TEXAS
INSTRUMENTS
10-24
@
I
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12,TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 - AUGUST 1999
timing diagram TPS3123 and TPS3124
fi-
v~~ bfr- VOO) ................................................ ±10 rnA
Output clamp current, 10K (VO < 0 or Vo > VOO) ........................................... ±10 rnA
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA ........................................... -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Soldering temperature .................................................................... 260°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" Is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GNO.
DISSIPATION RATING TABLE
PACKAGE
TA ~ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DBV
437mW
3.5mWI"C
280mW
227mW
=
recommended operating conditions at specified temperature range
Supply voltage, VOO
MIN
MAX
ITA = O°C to 85°C
0.75
3.3
ITA = -40°C to 85°C
0.85
3.3
0
VOO+O·3
Input voltage, VI
High-level input voltage, VIH
0.3xVOO
Input transition rise and fall rate at WOI, tWIN
1
-40
Operating free-air temperature range, TA
1()-26
:II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
V
V
0.7xVOO
Low-level input voltage, VIL
UNIT
85
V
IJSIV
°C
TPS3123J12, TPS3123G15,TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15,TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227-AUGUST 1999
electrical characteristics over recommended operating free-alr temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MR pullup resistor (internal)
IIH
High-level input current
IlL
Low-level input current
WOI
WOI=OV,
VOO=3.3V
-1
1
MR
MR=OV,
VOO=3.3V
-80
-170
Low-level output voltage
RESET
VOO= 1.5V,
IOH =-1 rnA
VOO=3.3V,
IOH=-4.5mA
VOO=0.75V,
IOH =-811A
VOO= 1.5V,
IOH =-1 rnA
VOO=0.75V,
IOL = 1511A
VOO= 1.5V,
IOL= 1.4 rnA
VOO= 1.5V,
IOL= 1.4mA
VOO=3.3V,
IOL=3mA
TPS312xJ12
TPS312xG15
TPS312xJ18
TA = -40°C to 85°C
TPS3123-xx .
TPS3124-xx
100
Ci
Input capacitance at MR, WOI
..
1.12
1.35
1.40
1.45
1.56
1.62
1.68
2.57
2.64
2.71
20
30
MR unconnected
V
0.4
1.08
1.4 V < VIT_<2 V
Supply current
TPS3125-xx
(see Note 3)
O.2xVOO
2V VIT_+0.2 V,
See timing diagram
tpHL
Propagation delay time, high-to-Iow-Ievel output
MR to RESET delay
(TPS3123125 only)
tpLH
Propagation delay time, low-to-high-Ievel output
MRto RESET delay
(TPS3125 only)
tPHL
Propagation delay time, high-to-Iow-Ievel output
VDD to RESET delay
tpLH
Propagation delay time, low-to-high-Ievel output
VDD to RESET delay
(TPS3124/25 only)
VDD;:' VIT_ +0.2 V,
VIL = 0.2 x VDD,
VIH = 0.8 x VDD
VIL = VIT_ -0.2 V,
VIH=VIT_+0.2V
~TEXAS
INSTRUMENTS
10-28
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
UNIT
0.1
i1S
0.1
10
10
i1S
TPS3123J12, TPS3123G15,TPS3123J18, TPS3124J12,TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY
CIRCUITS
SLVS227 - AUGUST 1999
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
LOW-LEVEL OUTPUT CURRENT
25
TA=25°C
c(
::!.
r
20
I
C
~
::J
0
~
Q.
LOW-LEVEL OUTPUT VOLTAGE
vs
~
750
TPS3123J12
Voo = 0.75 V
=e
I
_t
~
5001----+---+---+------1it--H
TA=25°C
i
15
I
I ~ 1----+---+----;p~-t1r-_I_--I
::J
III
I
0
9
'---"""--"""--"'TT"---;rT""-'"
~
10
!.J
.p
o
-~
o
2
3
O~~~~-~-~~--==_-~
o
150
200
250
IOL - Low-Level Output Current - I1A
3.3
VOO - Supply Voltage - V
Figure 2
Figure 3
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
vs
LOW-LEVEL OUTPUT CURRENT
850
TPS3123J12
Voo = 0.85 V
MR = Open
800
>
E
I
•
al
!
~
'S
Q.
'S
0
]
~
700
1
I
I
I
TA=O°C
500
TA=-40°C-
300
200
o
~
~
l"-
I
400
100
t
1
TA = 25°C
600
-I
.p
>
l
0
-I
_I
TA=85°C
---
o
~
LOW-LEVEL OUTPUT CURRENT
1.5.----.---,----,--T"'T-.....-.,.......,
TPS3125L30
VOO=1.5V
1.25 MR = Open
1-r-
0
fj
§
I) I) ~V
~~
~
-
100
200
300
400
10L - Low-Level Output Current -1lA
0.751-----t---t---t--""]'i-"H:.ld------j
0.51-----t---t---tT-.#¥----+-----j
I
-I
.p
0.251---+-~~~-t--t---+----I
500
4
2
3
5
IOL - Low-Level Output Current - mA
Figure 4
6
Figure 5
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-29
TPS3123J12. TPS3123G15. TPS3123J1S. TPS3124J12. TPS3124G15
TPS3124J1S; TPS3125J12,' TPS3125G15; TPS3125J1S; TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 - AUGUST 1999
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.3
TPS3125L30
3
~=3.3V
MR = Open
>
II
2.5
I
A!
2.25
_I
I
aI
~
.!
-
2.75
TA=85°C
TA = 25°C
TA=O°C
2
'Sa.
1.75
'S
TA=-40°C ~
1.5
Vh
0
~
1.25
~I
0.75
~
0.5
...I
/
h
VAf?
~
0.25
oV
o
TPS3123J12
t----"""IIIIIII:::----j---t-- VDO = 1.5 V
MR = Open
>
I
H-.J 1
If--I)
.;
/
i
1.2 t----t--~ilt!o;::__--t---t---;
0
0.81----+---+------+'l--'lI.--T+-----I
1
~/
1
0.6 t----t----t---'""""i--::::r--:ft-t---;
~
%
I
-'"
~
:z::
~
5
10
15
20
25
IOL - Low-Level Output Current - mA
0.4t----t--0.2 t------t---+----;-----t-ttt-t----;
30
IOH - High-level Output Current - mA
Figure 6
Figure 7
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.4
3
>
2.75
II
2.5
A!
2.25
i
2
I
aI
~
0
J
.3
""
"
:z::
~
at:
>
:a
I'-
'E
~ II!..
=r
~
TA=85°C
1.75
1.5
i
~~
1\..'"
TA=-40°C
Ii
TA=25°C \. " ' ~
1.25
~
TAI=O°C'
0.75
"",
\\
~
0.5
o
\
"I
1\ \ \
\ ~\ \
0.25
o
P
TPS3123J12
VOO=3.3V
MR=Open
1:.
II
NORMALIZED INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
-5
-10
-15
-20
-25
IOH - High-level Output Current - mA
-30
1.005
TP8312xJ1 ~
1.004
1.003
1.002
/'
0.999
1 O.99!.to
z
Figure 8
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
-----20
0
20
40
60
TA - Free-Air Temperature - °C
Figure 9
:ilTEXAS
10-30
V
./
1.001
80
TPS3123J12, TPS3123G15, TPS3123J18,TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12,TPS3125G15, TPS3125J18,TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY
CIRCUITS
SLVS227-AUGUST 1999
TYPICAL CHARACTERISTICS
NORMALIZED INPUT THRESHOLD VOLTAGE
MINIMUM PULSE DURATION
vs
vs
FREE-AIR TEMPERATURE
!:'
&
t:
>
::a
'E
:r
-..~
~
Ii
THRESHOLD OVERDRIVE
1.005
4.5
TPS312xL30
1.004
1.003
4
1\
1.002
\
0.999
=O!
Z
0.998-40
r
3.5
t
3
c
1\
'"I, "
1.001
!
TPS312xL30
co
5
~
IL
E
E
"-
1.5
...........
~
-20
20
40
60
o
TA - Free-Air Temperature - °C
~
0.5
.............. 1'"
o
80
-
1\
2
::II
~
MR = Open
VIT= 2.64 V
TA = 25°C
11
2.5
:::I
:5
1
o
r--... """"'"'
50
100
150
200
250
VOO - Threshold Overdrive - mV
Figure 10
r300
Figure 11
MINIMUM PULSE DURATION
vs
THRESHOLD OVERDRIVE
3.5
co
r
3
c
2.5
:::I
Q
CD
2
t
IMR=o~n
\
\
\
.!!!
:::I
IL
E
:::I
E
1.5
~ ...............
'c
i
~
0.5
o
VIT= 1.08 V
TA=25°c
TPS312xJ12
o
50
100
r-- r--- ...........
150
200
250
300
VOO - Threshold Overdrive - mV
Figure 12
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-31
10-32
TPS3305-18, TPS3305-25, TPS3305-33
DUAL PROCESSOR SUPERVISORS
D OR DGN PACKAGE
(TOP VIEW)
• Dual Supervisory Circuits for DSP and
Processor-Based Systems
• Power-On Reset Generator with Fixed
Delay Time of 200 ms, no External
Capacitor Needed
SENSE1 [ ] 8 Voo
SENSE2 2
7 MR
WDI 3
6 RESET
GND 4
5 RESET
• Watchdog Timer Retriggers the RESET
Output at SENSEn ~ VIT+
• Temperature-Compensated Voltage
Reference
• Maximum Supply Current of 40 I1A
• Supply Voltage Range ••• 2.7 V to 6 V
• Defined RESET Output from VDD ~ 1.1 V
• MSOP-8 and SO-8 Packages
• Temperature Range ••• - 40°C to 85°C
typical applications
Figure 1 lists some of the typical applications for the TPS330S family, and a schematic diagram for a DSP-based
system application. This application uses TI part numbers TPS3305-2S, TPS7133. TPS7102S, and
TMS320VCS49.
I VI
5V-10V
I
"-
13•3v
TPS7133
VOl
GND
~,
J.
GND
lVI
TPS71 025
.~~
Vo 2.5V
I
DSP
VDD
External
Reset
Source
SENSE 1
MR
SENSE 2
TPS3305-25
RESET
WDI
GND
1
l
DVDD
CVDD
TMS320VC549
RESET
•
Applications using DSPs, Microcontrollars
or Microprocessors
•
•
•
•
•
•
•
Industrial Equipment
Programmabla Controls
Automotlva Systams
Portable/Battery Powered Equipment
Intelligent Instruments
Wireless Communication Systems
Notebook/Desktop Computers
XF
OND
I
Figure 1. Applications Using the TPS3305 Family
description
The TPS330S family is a series of micropower supply voltage supervisors designed for circuit initialization,
primarily in DSP and processor-based systems, which require two supply voltages.
The product spectrum of the TPS330S is deSigned for monitoring two independent supply voltages of
3.3 V/1.8 V, 3.3 V12.S V or 3.3 V 15 V.
~TEXAS
Copyright© 1998, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-33
TPS330S-18; TPS3305-2S; TPS330S-33
DUAL PROCESSOR SUPERVISORS
SLVS198 - DECEMBER 1998
description (continued)
The various supply voltage supervisors are designed to monitor the nominal supply voltage, as shown in the
following supply voltage monitoring table.
DEVICE
TPS3305-18
TPS3305-25
TPS3305-33
SUPPLY VOLTAGE MONITORING
THRESHOLD VOLTAGE (TYP)
NOMINAL SUPERVISED VOLTAGE
SENSE1
SENSE2
SENSE1
SENSE2
3.3V
1.8V
2.93 V
1.68V
3.3V
2.25 V
2.5V
2.93 V
5V
3.3V
4.55 V
2.93 V
During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the
supply voltage supervisor monitors the SENSEn inputs and keeps RESET active as long as SENSEn remains
below the threshold voltage VIT+.
An internal timer delays the return ofthe RESET output to the inactive state (high) to ensure proper system reset.
The delay time, ~ typ = 200 ms, starts after SENSE1 and SENSE2 inputs have risen above the threshold voltage
VIT+. When the voltage at SENSE1 or SENSE2 input drops below the threshold voltage VIT_, the RESET output
becomes active (low) again.
The TPS3305-xx devices integrate a watchdog timer that is periodically triggered by a positive or negative
transition of WDI. When the supervising system fails to retriggerthe watchdog circuit within the time-out interval,
tt(out) = 1.6 s, RESET becomes active for the time period td . This event also reinitializes the watchdog timer.
Leaving WDI unconnected disables the watchdog.
The TPS3305-xx family of devices incorporates a manual reset input, MR. A low level at MR causes RESET
to become active. In addition to the active-low RESET output, the TPS3305-xx family includes an active-high
RESET output.
The TPS3305-xx devices are available in either 8-pin MSOP or standard 8-pin SO packages.
The TPS3305-xx family is characterized for operation over a temperature range of - 40°C to 85°C.
TA
-40°C to 85°C
AVAILABLE OPTIONS
PACKAGED DEVICES
PowerPADTM
SMALL OUTLINE
IL-SMALL OUTLINE
(D)
(DGN)
TPS3305-18D
TPS3305-18DGN
TPS3305-25D
TPS3305-25DGN
TPS3305-33D
TPS3305-33DGN
MARKING
DGNPACKAGE
CHIP FORM
TIAAM
TIAAN
TIAAO
TPS3305-18Y
TPS3305-25Y
TPS3305-33Y
(V)
description (continued)
MR
L
H
H
H
H
H
FUNCTIONITRUTH TABLES
RESET
SENSE1>VIT1
SENSE2>VIT2
xt
xt
L
0
0
L
L
0
0
1
L
0
1
L
0
1
L
0
PowerPAD is a trademark of Texas Instruments Incorporated.
~TEXAS
10-34
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
RESET
H
H
H
H
H
H
TPS3305-18, TPS3305-25, TPS3305-33
DUAL PROCESSOR SUPERVISORS
SLVS198 - DECEMBER 1998
o
H
H
t
H
X = Don't care
L
H
L
H
H
L
functional block diagram
Voo
r----------------------~
TPS3305
14 k.Q
MR -11--......- - - - - - - - - - - ,
R1
SENSE 1 -If-------"VV'v---.-----1
RESET
R2
R3
SENSE 2 ---t1-----"VV'v-+___- t - I
>-__---1
RESET
Logic + Timer
R4
GNO~------~--l-~
Reference
Voltage
of 1.25 V
WOI -I1------4t----I
~----------------------~
~lExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-35
TPS330S-18, TPS3305-2S, TPS330S-33
DUAL PROCESSOR SUPERVISORS
SLVS198- DECEMBER 1998
timing diagram
SENSEn
V(nom)
-----T----
Vrr_
I
I
I
O+--r~+_rr_+~-------+------~--+___.
WOI
1
tt(out)
---II
----nIl
I
o
II
I II
I
I
"~t-tHiHi i i i+"
td ~ ~
L
I I ~ 14- td
I
ld~ i4-.
I·
4
ld~114--
RESET Because of WOI~
RESET Because of MR
RESET Because of SENSE Below VITRESET Because of SENSE Below VIT-
~1ExAs
10-36
RESET Because
of SENSE Below VIT_
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75285
TPS3305-18, TPS3305-25, TPS3305-33
DUAL PROCESSOR SUPERVISORS
SLVS19B-DECEMBER 199B
TPS3305Y chip information
These chips, when properly assembled, display characteristics similar to those of the TPS3305. Thermal
compression or ultrasonic bonding may take place on the doped aluminium bonding pads. The chips may be
mounted with conductive epoxy or a gOld-silicon preform.
(1)
(2)
(8)
TPS3305Y
(7)
(3)
(6)
(4)
(5)
CHIP THICKNESS: 10 TYPICAL
BONDING PADS: 4 x 4 MINIMUM
TJ max = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS
56
II
I I I
II
I I I
II
I I I
II
I I I
II
I I I
II
I I
Terminal Functions
TERMINAL
NAME
NO.
DESCRIPTION
110
GND
4
MR
7
I
Manual reset
Ground
RESET
5
0
Active-low reset output
RESET
6
0
Active-high reset output
SENSE1
1
I
Sense voltage Input 1
SENSE2
2
I
Sense voltage Input 2
WDI
3
I
Watchdog timer input
VDD
8
Supply voltage
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-37
TPS330S-18, TPS330S-2S, TPS330S-33
DUAL PROCESSOR SUPERVISORS
SLVS198 - DECEMBER 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Voo (see Note 1) ............................................................ 7 V
All other pins (see Note 1) ......................................................... - 0.3 V to 7 V
Maximum low output current, IOL ........................................................... 5 mA
Maximum high output current, IOH ........................................................ - 5 mA
Input clamp current, 11K (VI < 0 or VI> VOO) ................................................ ±20 mA
Output clamp current, 10K (YO < 0 or Vo > Voo) ............................................ ±20 mA
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA ........................................... -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Soldering temperature .................................................................... 260°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indiceted under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t 1000 h
continuously.
=
DISSIPATION RATING TABLE
DERATING FACTOR
ABOVE TA = 25°C
TA=70°C
TA = 85°C
POWER RATING
POWER RATING
POWER RATING
DGN
2.14mW
17.1 mWI"C
1.37mW
1.11 mW
D
725mW
5.8mWI"C
464mW
377mW
PACKAGE
TAS25°C
recommended operating conditions at specified temperature range
MIN
Supply voltage, VDD
2.7
MAX
UNIT
6
V
Input voltage at MR and WDI, VI
0
VDD+0.3
V
Input voltage at SENSE1 and SENSE2, VI
0
(VDD+0.3)VITI1·25V
V
High-level input voltage at MR and WDI, VIH
V
0.7xVDD
Low-level input voltage at MR and WDI, VIL
0.3xVOD
V
Input transition rise and fall rate at MR, IltJllV
50
nsN
85
°C
-40
Operating free-air temperature range, TA
~TEXAS
INSTRUMENTS
10-38
POST OFFICE
sox 655303 •
DALlAS. TEXAS 75265
TPS3305-18, TPS3305-25, TPS3305-33
DUAL PROCESSOR SUPERVISORS
SLVS198 - DECEMBER 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
High-level output voltage
low-level output voltage
Power-up reset voltage (see Note 2)
TEST CONDITIONS
MIN
VOO = 2.7 V to 6 V, IOH = -20 ItA
VOO-0.2V
VOO=3.3 V,
IOH=-2mA
VOo-O.4V
VOO=6 V,
IOH=-3 mA
VOo-O.4V
TYP
0.2
VOO=3.3 V,
IOl=2mA
0.4
VOO=6V,
IOl=3mA
0.4
VOO~I.IV,
IOl=201tA
VIT-
Negative-going input threshold voltage
(see Note 3)
VSENSE1,
VSENSE2
Vhys
IH(AV)
Hysteresis at VSENSEn input
Average high-level input current
WOI
IL(AV)
IH
Il
VOO= 2.7Vt06V,
TA = O°C to 65°C
Average low-level input current
High-level input current
low-level input current
100
Supply current
Ci
Input capacitance
VOO= 2.7Vt06V,
TA =-40°C to 850C
0.4
1.66
1.72
2.20
2.25
2.30
2.86
2.93
3
4.46
4.55
4.64
1.64
1.66
1.73
2.20
2.25
2.32
2.86
2.93
3.02
4.46
4.55
4.67
VIT-= 1.68V
15
VIT_=2.25V
20
VIT-= 2.93 V
30
VIT-= 4.55 V
40
100
150
WOI =OV,
VOO=6V,
TIme average (de = 12%)
-15
-20
WOI = VOO = 6 V,
MR
MR = 0.7 x VOO,
SENSEI
VSENSEI = VOO = 6 V
SENSE2
VSENSE2 = VOO = 6 V
WOI=OV,
VOO =6V
MR
MR=OV,
VOO=6V
SENSEn
VSENSEI ,2 = 0 V
120
170
-130
-180
5
8
6
9
-120
-170
-430
-600
-1
V
V
ItA
ItA
1
40
VI =OVtoVOO
V
ItA
VOO=6V
WOI
V
mV
WOI=VOO=6V
TIme average (de = 88%)
WOI
UNIT
V
VOO = 2.7 V to 6 V, IOl= 20 ItA
1.64
VSENSE1,
VSENSE2
MAX
10
ItA
pF
NOTES: 2. The lowest supply voltage at which RESET becomes active. t r, VOO ~ 151JS1V.
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic O.II1F) should be placed close to the supply terminals.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265
10-39
TPS330S-18, TPS330S-2S, TPS330S-33
DUAL PROCESSOR SUPERVISORS
SLVS198 - DECEMBER 1998
timing requirements at VDD
=2.7 V to 6 V, RL =1 MQ, CL =50 pF, TA =25°C
PARAMETER
SENSEn
tw
Pulse width
TEST CONDITIONS
VSENSEnL
MR
WDI
VIH
=VIT_ -0.2 V,
=0.7 x VDD,
switching characteristics at VDD
VSENSEnH
VIL
Watchdog time out
I(!
Delay time
IpHL
tPLH
tPHL
tpLH
= 0.3 x VDD
TEST CONDITIONS
~SENSEn) -
......
.5 0.997
0.996
J
12
8
6
4
~
i".....
"
)
~ t-....
16
cc::I.
~ 0.999
I
18
-
14
I
t=
SUPPLY VOLTAGE
I
Voo=6V
MR = Open
N
~
vs
FREE-AIR TEMPERATURE AT Voo
VOO - Supply Voltage - V
Figure 2
Figure 3
INPUT CURRENT
MINIMUM PULSE DURATION AT SENSE
vs
vs
INPUT VOLTAGE AT MR
THRESHOLD OVERDRIVE
.100
0
10
VOO=6V
TA = 25°C
-100
~
CC
::I. -200
I
C -300
§
(J
-400
'5
CI.
.5 -500
~
.....
..,I---"
~
'"
V
I....-'
I,..-' V
'"
::I.
I
MR=Open
-
CD
'"c
8
>'"
7
CD
OJ
c
ic
I
~OO~6VI
9
6
::I
5
.I::I
4
E
E
3
:E
2
IL
.= -600
::I
'2
-700
~
I
-800
~
-900
-1-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
VI-Input Voltage at MR - V
o
......
:--.....
o 100 200 300 400 500 600 700 BOO 900 1000
SENSE - Threshold Overdrive - mV
Figure 4
Figure 5
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-41
TPS3305-18, TPS3305-25, TPS3305-33
DUAL pROCESSOR SUPERViSORS
SLVS198- DECEMBER 1998
TYPICAL CHARACTERISTICS
HIGH·LEVEL OUTPUT VOLTAGE
HIGH·LEVEL OUTPUT VOLTAGE
vs
vs
HIGH·LEVEL OUTPUT CURRENT
HIGH·LEVEL OUTPUT CURRENT
2.5
6.5
VOO=2V
MR=Open
>
I
II)
2
CI
~
~
'$
!0
["""II1II
r-.~
1.5
>
I
~ ~ t--..
~
CI
:f
85° : -
I
:t:
~
Sa
.I!!
~
'" \ '\l\
~
.J:.
0.5
o
o -0.5
r-5.5
6
"
~
,
~,~,
1\ \
~ t-
-40°C
I
.....-:: ~ ~
......
~~
"."
'\.
3.:
1.5
1
IOH - Hlgh·Level Output Current - mA
Figure 7
LOW·LEVEL OUTPUT VOLTAGE
vs
6.5
II
VOO=2V
MR = Open
6
,
I
!
~
I
-I
~
0.5
5.5
I
4.5
~
~ V
85OC"V~VV
1
J
~
-I
>
I
I
~
0
LOW·LEVEL OUTPUT CURRENT
.!
2
1.5
V~~~
~~~
~P'
-40 0 C ' _
II
I1
4
1.5
~
J
J J J
II
5°(
-'i~ II V V 1..1
II
3
I
-I
MR = Open
3.5
2.5
~
JOO~6~
5
!I
0.J/M
o 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
1/
2
0.5
~
~
V ~V ~
-40°C
~ ~ ~ I'
I I
I
-
.J/M ~
00 5 10 15 20 25 30 35 40 45 50 55 60
IOL - Low·Level Output Current - mA
FigureS
IOL - Low·Level Output Current - mA
Figure 9
~TEXAS
10-42
\
-0 -10 -15 -20 -25 -30 -35 -40 -45 -50
vs
'$
\
,
j
o
LOW·LEVEL OUTPUT CURRENT
I
,\ \
1
LOW·LEVEL OUTPUT VOLTAGE
II)
~ -40°C
11 11\ \
1\ , \
Figure 6
>
'" "
i\
2
-1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 -0 -0.5 -6
r-....
\
IOH - Hlgh·Level Output Current - mA
2.5
~.....
~ ~~
85°C
2.5
O.5
0
_
MR=Open
3
~
1\
5
4.5
~O=6V
~
INSTRUMENTS
POST OFFICE BOX e55303 • DALLAS, TEXAS 75265
TPS3307-18, TPS3307-25, TPS3307-33
TRIPLE PROCESSOR SUPERVISORS
SENSE1
SENSE2
SENSE3
GND
• Temperature-Compensated Voltage
Reference
•
•
•
•
•
08
D OR DON PACKAGE
(TOP VIEW)
• Triple Supervisory Circuits for DSP and
Processor-Based Systems
• Power-On Reset Generator with Fixed
Delay Time of 200 ms, No External
Capacitor Needed
2
3
4
7
6
5
Voo
MR
RESET
RESET
Maximum Supply Current of 40 J,LA
Supply Voltage Range ••• 2 V to 6 V
Defined RESET Output from VDD ;;,: 1.1 V
MSOP-8 and SO-8 Packages
Temperature Range ••• - 40°C to 85°C
typical applications
Figure 1 lists some of the typical applications for the TPS3307 family, and a schematic diagram for a
processor-based system application. This application uses TI part numbers TPS3307-33 and MSP430C325.
2.SV
SV
3.3 V
1
T
;::
VDD
-
470110
SENSE 1
SENSE 2
RESET
VDD
•
Applications using DSPs, Mlcrocontrollers
or Microprocessors
MSP430C325
•
•
•
•
•
•
•
Industrial equipment
Programmable Controls
Automotive Systems
Portable/Battery Powered Equipment
Intelligent Instruments
Wlraless Communication Systems
Notebook/Desktop Computers
RESET
TPS3307-33
GND
SENSE 3
620110
r::100 nF
GND
1
Figure 1. Applications Using the TPS3307 Family
description
The TPS3307 family is a series of micropower supply voltage supervisors designed for circuit initialization
primarily in DSP and processor-based systems, which require more than one supply voltage.
The product spectrum of the TPS3307-xx is designed for monitoring three independent supply voltages:
3.3 Vl1.B V/adj, 3.3 Vl2.5 V/adj or 3.3 Vl5 Vladj. The adjustable SENSE input allows the monitoring of any supply
voltage> 1.25 V.
The various supply voltage supervisors are designed to monitor the nominal supply voltage as shown in the
following supply voltage monitoring table.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Copyright@ 1998. Texas Instruments Incorporated
10-43
TPS3307-18, TPS3307-25, TPS3307-33
TRIPLE PROCESSOR SUPERVISORS
SLVS199 - DECEMBER 1998
description (continued)
SUPPLY VOLTAGE MONITORING
THRESHOLD VOLTAGE (TYP)
NOMINAL SUPERVISED VOLTAGE
DEVICE
SENSE3
SENSE1
SENSE2
SENSE3
SENSE1
SENSE2
1.25Vt
TPS3307-18
3.3V
1.8V
User defined
2.93 V
1.68V
User defined
2.25 V
1.25vt
TPS3307-25
3.3V
2.5V
2.93 V
2.93 V
1.25Vt
TPS3307-33
5V
3.3V
User defined
4.55 V
. . according to the application reqUirements.
t The actual sense voltage has to be adjusted by an external resistor dIVIder
During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the
supply voltage supervisor monitors the SENSEn inputs and keeps RESET active as long as SENSEn remain
below the threshold voltage VIT+'
An internal timer delays the return ofthe RESET outputto the inactive state (high) to ensure proper system reset.
The delay time, lVIT1
xt
0
0
0
0
H
I
L
H
H
H
MARKING
DGN PACKAGE
CHIP FORM
TIAAP
TIAAO
TIAAR
TPS3307-18Y
TPS3307-25Y
TPS3307-33Y
FUNCTIONITRUTH TABLES
SENSE3>VIT3
SENSE2>VIT2
xt
x
0
0
I
0
I
0
RESET
RESET
L
H
L
H
L
H
L
H
I
I
L
H
0
L
H
H
I
0
0
I
L
H
H
I
I
0
L
H
H
I
I
I
H
L
t x = Don't care
PowerPAD is a trademark of Texas Instruments Incorporated.
~TEXAS
10-44
(V)
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS3307-18, TPS3307-25, TPS3307-33
TRIPLE PROCESSOR SUPERVISORS
SLVS199-DECEMBER 1998
functional block diagram
VDD
r----------------------,
I
I
I
I
I
I
TPS3307
14kCl
MR
-1--+----------,
R1
SENSE 1 -l--'\N"v-____- - - I
SENSE 2 ---1----'\N"v--+-.._-+--1
GND
>-__-1
RESET
Logic + Timer
-;-;::==:!;-'
I
I
Reference
Voltage
of 1.25 V
I
I
I
I
I
SENSE 3 - - ! - - - - - - - - 1
~----------------------~
timing diagram
SENSEn
Venom)
VIT-
MR
,-nT------------II
II
I II
III
I
I
II
III
I
I
I
I
I
II
I
II
II
II
I II
I II
II
!
o+--+~~~~HH------------------~--_+
"~l-trjJHi
L
tel --.! 14-
I I --.! 14- td
d --.! 114-. I RESET Because of SENSE Below VIT
j
"
4
RESET Because of MR
RESET Beceuse of SENSE Below VIT_
RESET Because of SENSE Below Vrr_
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-45
TPS3307-18, TPS3307-25, TPS3307-33
TRIPLE PROCESSOR SUPERVISORS
SLVS199 - DECEMBER 1998
TPS3307Y chip Information
These chips, when properly assembled, display characteristics similar to those of the TPS3307. Thermal
compression or ultrasonic bonding may take place on the doped aluminium bonding pads. The chips may be
mounted with conductive epoxy or a gold-silicon preform.
(1)
(8)
(2)
TPS3307Y
(7)
(3)
(6)
(4)
(5)
CHIP THICKNESS: 10 TYPICAL
BONDING PADS: 4 x 4 MINIMUM
TJmax=150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS
56
II
I I I
II
I I I
II
I I I
II
I I I
II
I I I
II
I
Terminal Functions
TERMINAL
NAME
NO.
1/0
DESCRIPTION
GND
4
MR
7
I
Manual reset
RESET
5
0
Active-low reset output
Ground
RESET
6
0
SENSE1
1
I
Sense voltage input 1
SENSE2
2
I
Sense voltage input 2
SENSE3
3
I
Sense voltage input 3
VDD
8
Active-high reset output
Supply voltage
~TEXAS
INSTRUMENTS
1Q-46
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3307-18, TPS3307-25, TPS3307-33
TRIPLE PROCESSOR SUPERVISORS
SLVS199- DECEMBER 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Voo (see Note1) ............................................................ 7 V
All other pins (see Note 1) .......................................................... -0.3 V to 7 V
Maximum low output current, IOL ........................................................... 5 mA
Maximum high output current, IOH ......................................................... -5 mA
Input clamp current, 11K (VI < 0 or VI > Voo) ................................................ ±20 mA
Output clamp current, 10K (VO < 0 or Vo > VOO) ............................................ ±20 mA
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA ........................................... -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Soldering temperature .................................................................... 260°C
t
Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t = 1000 h
continuously.
DISSIPATION RATING TABLE
PACKAGE
TA:S;25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA=85°C
POWER RATING
DGN
2.14mW
17.1 mW/oC
1.37mW
1.11 mW
D
725mW
5.8 mW/oC
464mW
3nmW
recommended operating conditions at specified temperature range
MAX
UNIT
Supply voltage, VDD
2
6
V
Input voltage at MR and SENSE3, VI
0
VDD+O·3
V
Input voltage at SENSEl and SENSE2, VI
0
(VDD+0.3)VIT/1.25V
MIN
High-level input voltage at MR, VIH
Low-level input voltage at MR, VIL
Input transition rise and fall rate at MR, I'J.VI:N
Operating free-air temperature range, TA
-40
V
V
0.7xVDD
0.3xVDD
V
50
nsIV
85
°C
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-47
TPS3307-18, TPS3307-25, TPS3307-33
iRIPi.E PROCESSOR SUPERViSORS
SLVS199 - DECEMBER 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VOO = 2 V to 6 V,
VOH
VOL
High-level output voltage
Low-level output voltage
Power-up reset voltage (see Note 2)
VSENSE3
VOo-O.2V
VOO=3.3 V,
IOH =-2 mA
VOo-O.4V
VOO=6 V,
IOH=-3mA
VOo-O.4V
VIT-
VSENSE3
IOL=20JIA
0.2
IOL=2mA
0.4
VOO=6V,
IOL=3mA
0.4
VOO~l.l V,
IOL=20JIA
0.4
VOO=2Vt06V,
TA = O°C to 85°C
1.22
VOO =2Vt06 V,
TA = -40°C to 85°C
1.68
1.72
2.25
2.30
2.86
2.93
3
4.46
4.55
4.64
1.22
1.25
1.29
1.64
1.68
1.73
2.20
2.25
2.32
2.86
2.93
3.02
4.46
4.55
4.67
15
VIT_=2.25 V
20
VIT_=2.93 V
30
High-level input current
IL
Low-level input current
100
Supply current
Ci
Input capacitance
-180
5
8
VSENSE2 = VOO = 6 V
6
9
SENSE2
VOO=6 V
=VOO
SENSE3
VSENSE3
MR
MR=OV,
SENSEn
VSENSEl ,2,3 = 0 V
V
V
40
VSENSEl = VOO = 6 V
SENSEl
V
mV
-130
MR=0.7xVOO
V
10
VIT-= 1.68 V
MR
V
1.28
1.64
VIT-= 4.55 V
IH
1.25
2.20
VIT-= 1.25V
Hysteresis at VSENSEn Input
UNIT
V
VOO=3.3 V,
VSENSE1,
VSENSE2
Vhys
MAX
VOO = 2 V to 6 V,
VSENSE1,
VSENSE2
Negative-going input threshold voltage
(see Note 3)
TYP
MIN
IOH =-20JIA
-1
-430
VOO=6V
-1
-000
1
40
VI =OVtoVOO
JIA
1
10
JIA
JIA
pF
NOTES: 2. The lowest supply voltage at which RESET becomes active. t r, VOO ~ 151J.S1V
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic O.lI1F) should be placed close to the supply terminals.
~1ExAs
10-48
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TPS3307·18, TPS3307·25, TPS3307·33
TRIPLE PROCESSOR SUPERVISORS
SLVS199-DECEMBER 1998
timing requirements at Voo = 2 V to 6 V, RL = 1 MD., CL = 50 pF, TA = 25°C
PARAMETER
tw
Pulse width
MIN
TEST CONDITIONS
I SENSEn
VSENSEnL
IMR
VIH
=VIT_ -0.2 V,
=0.7 x VDD,
VSENSEnH
VIL
=VIT+ +0.2 V
= 0.3 x VDD
TYP
MAX
UNIT
6
j.lS
100
ns
switching characteristics at Voo = 2 V to 6 V, RL = 1 MD., CL = 50 pF, TA = 25°C
PARAMETER
Id
Delay time
Propagation (delay) time,
tpHL
tpLH
tpHL
tpLH
TEST CONDITIONS
MIN
TYP
MAX
UNIT
~ENSEn) ~ VIT+ + 0.2 V,
MR ~ 0.7 x VDD, See timing diagram
140
200
280
rna
200
500
ns
1
5
j.lS
MRtoRESET
high-to-Iow level output
MRtoRESET
Propagation (delay) time,
low-to-high level output
MRtoRESET
MRtoRESET
Propagation (delay) time,
SENSEn to RESET
VI(SENSEn) ~ VIT+ +0.2 V,
VIH 0.7 x VDD, VIL 0.3 x VDD
=
=VIT+ +0.2
high-to-Iow level output
SENSEn to RESET
VIH
Propagation (delay) time,
SENSEn to RESET
SENSEn to RESET
MR~0.7xVDD
low-to-high level output
=
V, VIL
=VIT_ -0.2 V,
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-49
TPS3307-18, TPS3307-25, TPS3307-33
TRIPLE PROCESSOR SUPERVISORS
SLVS199
DECEMBER 1998
TYPICAL CHARACTERISTICS
NORMALIZED SENSE THRESHOLD VOLTAGE
vs
FREE·AIR TEMPERATURE AT VOO
J3~
1.005
~
1.003
~
t:
"
1.001
"CI
15
0.999
::I.
I
r-.....
"- .......
10.997
8
a
~
6
a
2
III
I
Q
E
.......
~ 0.996
§ 0.995
-15
10
35
60
TA - Free-Air Temperature - °C
-40
II
4
I
0
-2
7
/
-4
SENSEn = Voo _
MR=Open
TA=25°C
-
-6
-8
-10
-0.50 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
VOO - Supply Voltage - V
85
Figure 2
Figure 3
INPUT CURRENT
vs
INPUT VOLTAGE AT MR
MINIMUM PULSE DURATION AT SENSE
vs
THRESHOLD OVERDRIVE
100
o
VOO=6V
TA = 25°C
l;-
-100
~
I
~
:::I
tJ
:;
~
-200
-300
./
-400
I;-
V ....
~
.,-
V~
'"
t....-
..
9
c
=
>=
Ii
8
i
6
:::I
Q
GI
."
.!!!
-500
10
::I.
I
c
:::I
I
=
-
TPS3307-33
10
C
CL
:::I
'"I'"
~ 0.998
~
14
'"
........
~
i!
~
16
12
GI
J::
-
'\
::;- 1.002
.f
If
18
I
VOO=2V
MR = Open
j::"
:;: 1.004
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
!
I
I
VOO=6V
MR=Open
-
7
5
4
Go
-600
-700
E
:::I
E
3
iii!
2
C
1\
r-......
I
-800
~
-900
-1-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
VI - Input Voltege at MR - V
o
o
100 200 300 400 500 600 700 800 900 1000
SENSE - Threshold Overdrive - mV
Figure 4
Figure 5
~TEXAS
1D-50
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3307·18, TPS3307·25, TPS3307·33
TRIPLE PROCESSOR SUPERVISORS
SLVS199 - DECEMBER 1998
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
2.5
6.5
VOO=2V
MR = Open
>
I
CD
2
I
>
~
~
~
15
f
~
1\ ~ ~
0
sJ:.
5P
85° :-
J:
I
J:
.p
,
1\1\ r¥ r-
1
0.5
o
o -0.5
~
4.5
15
4
~\I~\
~
~
0
-40°C
1
~
5P
J:
\
I
II1
-1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 -5 -5.5
~
5
~
I,["::
........ ~
5.5
I
CD
CI
~ ~ t:--...
1.5
V
IVOOI= 6
MR = Open
6
J:
~~
......
'\
3.5
2
1.5
o
o
-5 -10 -15 -20 -25 -30 -35 -40 -45 -50
IOH - HIgh-level Output Current - rnA
Figure 7
LOW-LEVEL OUTPUT VOLTAGE
vs
vs
LOW-LEVEL OUTPUT CURRENT
I
2
~
J
1.5
VII 1/
0
...~
...
.p
85°C
V ~ ~ ~V
~~
~TI"')
I
V
~
0.5
~
--
o ~
o 0.5
I
t
4.5
~
15
~
0
1...
~
...
.p
I
5
4
/
3.5
II
3
5°C
2.5
2
3.5 4 4.5 5 5.5 6
)
i~ V
/ /
1/
V V 1/
j
II
V ~V ~
-40°C
......~ ~ ;....-
1.5
k::;; ~ ~
0.5
~
2.5 3
I
>
jiIIII'
1 1.5 2
!
6 - VOO=6V
_ MR=Open
5.5
I
I I
S
LOW-LEVEL OUTPUT CURRENT
6.5
I
I
I
VOO=2V
MR = Open
I
15
a.
15
,
,,
0.5
LOW-LEVEL OUTPUT VOLTAGE
CD
1\
\ 1
1\ \
\
\ \
E5°C
.p
-Q
~" -40°C
1\ 11\\ \
~ \ 1\
,
3
2.5
Figure 6
>
"
t--......... 1'0...
'\.. I,,\: r-...
IOH - High-Level Output Current - rnA
2.5
~~
00
~
5
IOL - Low-Level Output Current - rnA
I I
r---
I
"""" 15 20 25 30 35 40 45 50 55 60
10
IOL - Low-Level Output Current - rnA
Figure 9
FigureS
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-51
1O-S2
TPS3705-30, TPS3705-33, TPS370S-50
TPS3707-2S, TPS3707-30, TPS3707-33, TPS3707-S0
PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL
- REVISED JANUARY 1999
TPS3705 , , • D PACKAGE
(TOP VIEW)
features
• Power-On Reset Generator with fixed
Delay Time of 200 ms, no External
Capacitor Needed
• Precision Supply Voltage Monitor 2.5 V, 3 V,
3.3 V, and 5 V
• Pin-for-Pin Compatible with the MAX705
through MAX708 Series
• Integrated Watchdog Timer (TPS3705 only)
• Voltage Monitor for Power-fail or
Low-Battery Warning
• Maximum Supply Current of 50 IJA
• MSOP-8 and SO-8 Packages
• Temperature Range ..• -40°C to 85°C
MRDs
WOO
2
7 RESET
VDD
GNO
PFI
12V
5V
-u
PFO
TPS3705-50
-
MR
RESET
;> 910 kn
WOI
PFO
M R D s RESET
2
7 RESET
VDD
GNO
PFI
3
4
6
5
NC
PFO
NC - No internal connection
TPS3705 , , • DGN PACKAGE
(TOP VIEW)
• Designs Using DSPs, Microcontrollers or
Microprocessors
• Industrial Equipment
• Programmable Controls
• Automotive Systems
• Portable/Battery Powered Equipment
• Intelligent Instruments
• Wireless Communication Systems
• NotebOOk/Desktop Computers
V~D
6
5
TPS3707 , , , D PACKAGE
(TOP VIEW)
typical applications
I
3
4
100
RESETDs WOI
WOO
2
3
7
6
VDD
4
5
PFO
PFI
GNO
TPS3707 , •• DGN PACKAGE
(TOP VIEW)
RESET[]S
RESET 2
7
MR 3
6
VDD
1
I
MR
4
5
NC
PFO
PFI
GNO
NC - No internal connection
VDD
-::~
nPo:;.
MSP430P112
RESET/NMI
woo
1/0
WDI
I/O
PFI
120kn
GND
GND
1
1
..L
figure 1. Typical MSP430 Application
~TEXAS
Copyright © 1999. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-53
TPS3705-30, TPS3705-33, TPS3705-50
'fPS3107-25, TPS3707-30, TPS3707-33, TPS3707-50
PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL
SLVS184B - NOVEMBER 1998 - REVISED JANUARY 1999
description
The TPS370S, TPS3707 family of microprocessor supply-voltage supervisors provide circuit initialization and
timing supervision, primarily for DSP and processor-based systems.
During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the
supply voltage supervisor monitors V DD and keeps RESET active as long as V DD remains below the threshold
voltage VIT+. An internal timer delays the return of the output to the inactive state (high) to ensure proper system
reset. The delay time, ~typ= 200 ms, starts after V DO has risen above the threshold voltage VIT+. When the supply
voltage drops below the threshold voltage VIT_, the output becomes active (low) again. No external components
are required. All the devices of this family have a fixed-sense threshold voltage VIT_ set by an internal voltage
divider.
The TPS370S-xx and TPS3707-xx devices incorporate a manual reset input, MR. A low level at MR causes
RESET to become active.
The TPS370x-xx families integrate a power-fail comparator which can be used for low-battery detection,
power-fail warning, or for monitoring a power supply other than the main supply.
The TPS370S-xx devices have a watchdog timer that is periodically triggered by a positive or negative transition
at WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval,
1t(OUI) = 1.6 s, WDO becomes active. This event also reinitializes the watchdog timer. Leaving WDI unconnected
disables the watchdog.
The TPS3707-xx devices do not have the Watchdog function, but include a high-level output RESET.
The product spectrum is designed for supply voltages of 2.S V, 3 V, 3.3 V, and S V. The circuits are available in
either 8-pin MSOP or standard SOIC packages. The TPS370S, TPS3707 devices are characterized for
operation over a temperature range of -40°C to 8SoC.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
-40°C 10 85°C
THRESHOLD
VOLTAGE
CHIP FORM
(Y)
POWER-PADTM
I1-8MALL OUTLINE
(DGN)
2.63 V
TPS3705-30D
TPS3705-30DGN
TIMT
TPS3705-30Y
2.93 V
TPS3705-33D
TPS3705-33DGN
TIMU
TPS3705-33Y
4.55 V
TPS3705-50D
TPS3705-50DGN
TIMV
TPS3705-50Y
2.25 V
TPS3707-25D
TPS3707-25DGN
TIMW
TPS3707-25Y
2.63 V
TPS3707-30D
TPS3707-30DGN
TlAAX
TPS3707-30Y
2.93 V
TPS3707-33D
TPS3707-33DGN
TIMY
TPS3707-33Y
4.55 V
TPS3707-50D
TPS3707-50DGN
TIAAZ
TPS3707-50Y
~TEXAS
10-54
MARKINGDGN
PACKAGE
SMALL OUTLINE
(D)
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS3705·30, TPS3705·33, TPS3705·50
TPS3707·25, TPS3707·30, TPS3707·33, TPS3707·50
PROCESSOR SUPERVISORY CIRCUITS WITH POWER·FAIL
SLVS184B - NOVEMBER 1998 - REVISED JANUARY 1999
Function Tables
TRUTH TABLE, TPS3705
TYPICAL
DELAY
MR
VDD>VIT
RESET
H--+L
1
H--+L
30 ns
L--+H
1
L--+H
200ms
H
1--+0
H--+L
3115
H
0--+1
L--+H
200ms
TRUTH TABLE, TPS3707
RESET
TYPICAL
DELAY
MR
VDD>VIT
RESET
H--+L
1
H--+L
L--+H
30 ns
L--+H
1
L--+H
H--+L
200ms
H
1--+0
H--+L
L--+H
3118
H
0--+1
L--+H
H--+L
200ms
TRUTH TABLE, TPS370x
PFO
TYPICAL
DELAY
0--+1
L--+H
0.5118
1--+0
H--+L
0.5118
PFI>VIT
functional block diagram
VDD
r----------------------,
TPS3705
TPS3707
- + - -....----,
14kQ
MR
-;--.---+------~
Reset
Logic + Timer 1---;--
RESET
i
Only
TPS3707
GND
-+--------'
Reference
Voltage
of 1.25 V
PFI-+-------~
Watchdog
Logic + Timer
WDI - + -......---1
i
Only
TPS3705
40kQ
WOO
I
I
I
I
L ______________________ ~
i
Only
TPS3705
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10--55
TPS3705-30, TPS3705-33, TPS3705-50
TPS3707-25, TPS3707-30, TPS3707-33, TPS3707-50
PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL
SLVS184B - NOVEMBER 1998 - REVISED JANUARY 1999
timing diagrams
VDD
5VH-~~--T-~~~~~--+-~--~--4
4.5 V
1.1 V
OV~~--~~-+~--~--~~~--~--~
MR
RESET
5VH--+~--u-~-r~-r~--+-~--~~
-~
UV
I
I
1.1
v
OV~~--~~-T~--~~~~+---~--~
I
Undefined Behavior
1.1
o
t t(out)
--i144--~
5Vr-~----w-~--------r-~~~-+~~
4.5 V
------T-I
I
1.1 V
------+--
OV+-~~--~~--------~--~~~---++
~TEXAS
10-56
INSTRUMENTS
POST OFACE BOX 655303 • DALLAS. TEXAS 75265
TPS3705·30, TPS3705·33, TPS3705·50
TPS3707·25, TPS3707·30, TPS3707·33, TPS3707·50
PROCESSOR SUPERVISORY CIRCUITS WITH POWER·FAIL
SLVS184B - NOVEMBER 1998 - REVISED JANUARY 1999
TPS370xY chip information
These chips, when properly assembled, display characteristics similar to those of the TPS370x. Thermal
compression or ultrasonic bonding may be caused on the doped-aluminum bonding pads. The chips may be
mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(1)
(8)
(2)
TPS3705Y
TPS3707Y
(3)
(4)
(7)
(6)
(5)
CHIP THICKNESS: 10 MILS TYPICAL
BONDING PADS: 4 x 4 MINIMUM
TJ max
=150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS
~
II
I I I
II
I I I
II
~
II
I I I
I I I
~
II
I I I
I
Terminal Functions
TERMINAL
NAME
NO.
1/0
MR
1
VOO
2
GNO
3
PFI
4
I
PFO
5
0
WOI
NC
ITPS3705
I TPS3707
RESET
6
7
WOO
ITPS3705
RESET
ITPS3707
8
I
DESCRIPTION
Manual reset
Supply voltage
Ground
I
Power-fail comparator input
Power-fail comparator output
Watchdog timer input
No internal connection
0
Active-low reset output
0
Watchdog timer output
0
Active-high reset output
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-57
TPS3705-30, TPS3705-33, TPS3705-50
TPS3707-25, TPS3707-30, TPS3707-33, TPS3707-50
PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL
SLVS184B - NOVEMBER 1998 - REVISED JANUARY 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage, Voo (see Note1) .............................................................. 7 V
All other pins (see Note 1) ........................................................... -0.3 V to 7 V
Maximum low output current, IOL . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. 5 mA
Maximum high output current, IOH .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . .. -5 mA
Input clamp current, 11K (VI < 0 or VI > Voo) ................................................. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Voo) ............................................ ±20 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. See Dissipation Rating Table
Operating free-air temperature range, TA ............................................. -40°C to 85°C
Storage temperature range, Tstg .................................................... -65°C to 150°C
Soldering temperature .................................................................... 260°C
t Stresses beyond those listed under-absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under -recommended operating conditions· Is not
Implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t = 1000h
continuously.
DISSIPATION RATING TABLE
PACKAGE
OGN
o
TA<25°C
POWER RATING
2.14W
725mW
DERATING FACTOR
ABOVE TA 25°C
17.1 mW/oC
5.8mW/oC
=
=
TA 70°C
POWER RATING
=
TA 85°C
POWER RATING
1.11 W
1.37W
464mW
3nmW
recommended operating conditions at specified temperature range
MIN
MAX
UNIT
Supply voltage, VOO
2
6
V
Input voltage, VI
0
Voo+D·3
V
High-level Input voltage, VIH
Low-level input voltage, VIL
Input transition rise and fall rate at MR or WOI, At/IN
-40
Operating free-air temperature range, TA
~TEXAS
10-58
V
0.7xVOO
INSTRUMENTS
POST OFFICE
eox 655303 •
DALLAS, TEXAS 75265
V
0.3xVOO
100
nsN
85
°C
TPS3705·30, TPS3705·33, TPS3705-50
TPS3707·25, TPS3707·30, TPS3707·33, TPS3707·50
PROCESSOR SUPERVISORY CIRCUITS WITH POWER·FAIL
SLVS184B - NOVEMBER 1998 - REVISED JANUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TPS370x-xx
VOO=1.1V
IOH =-4!1A
MIN
TYP
MAX
UNIT
0.8
TPS3707-25
TPS37Ox-30
VOH
High-level output voltage
VOO =VIT++0.2V,
IOH = -500 !1A
0.7xVOO
V
TPS37Ox-33
TPS370x-50
VOO = VIT+ + 0.2 V,
IOH = -aoo !1A
TPS37Ox-xx
VOO=6V,
VOO-1.5V
IOH = -a00 !1A
TPS3707-25
TPS37Ox-30
VOL
TPS37Ox-50
VOO = VIT++0.2 V,
IOL=2.5mA
TPS37Ox-xx
VOO=6V
IOL=3mA
VOO<': 1.1 V,
IOL=50 !1A
Power-up reset voltage (see Note 2)
TPS3707-25
TPS37Ox-30
TPS37Ox-33
VIT-
0.3
VOO = VIT++0.2 V, IOL= 1 mA
Negative-going input
threshold voltage
(see Note 3)
0.3
2.20
TA = O°C to 85°C
2.57
2.63
2.68
2.87
2.93
2.98
4.55
4.63
2.20
2.25
2.32
TA = -40°C to 85°C
TPS37Ox-xx
VOO<':2V,
TA = -40°C to 85°C
2.57
2.63
2.70
2.87
2.93
3.0
4.45
4.55
4.65
1.20
1.25
1.30
TPS3707-25
VOO
PFI
IIH(AV)
Average high-level input
current
IIL(AV)
Average low-level input
current
IIH
High-level Input current
VA
IlL
Low-level Input current
II
Input current
IDD
Ci
TPS37Ox-30
50
50
TPS370x-50
70
TPS370x-xx
WOI
V
V
10
WOI=VOO=6V,
Time average (dc = 88%)
100
150
!1A
WOI=OV,
VOO=6V,
Time average (de = 12%)
-15
-20
!1A
120
170
-130
-180
WOI
WOI =OV,
VOO=6V
-120
-170
MFI
MR=OV,
VOO=6V
-430
-000
VOO=6V,
OVs VISVDD
WOI=VOO =6V
!1A
0
1
!1A
VDD=2 Vt06 V, MR=VDD,MR,
WDI and outputs unconnected
20
50
!1A
TPS3705-xx
VOO = 2 V to 6 V, MR= VDD, MR,
WDI and outputs unconnected
30
50
!1A
VI = OVtoVDD
-1
!1A
TPS3707-xx
Supply current
Input capacitance
V
mV
MR=0.7xVOO VOO=6V
PFI
V
40
TPS37Ox-33
WOI
V
2.30
4.45
TPS370x-50
Hysteresis
2.25
TPS3707-25
TPS37Ox-30
PFI
0.4
TPS370x-50
TPS37Ox-33
Vhys
V
TPS370x-33
Low-level output voltage
5
pF
NOTES: 2. The lowest supply voltage at which RESET becomes active. tr,VDD <': 151JS/V
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.111F) should be placed near to the supply terminals.
-!II lExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-59
TPS3705-30, TPS3705-33, TPS3705-50
fPS3707-25, fPS3707-30, TPS3707-33, TPS3707-50
PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL
SLVS184B - NOVEMBER 199B - REVISED JANUARY 1999
timing requirements at RL = 1 MOo CL = 50 pF, TA = 25°C
PARAMETER
tw
Pulse width
TEST CONDITIONS
atVoo
Voo = VIT+ + 0.2 V,
Voo = VIT_-0.2 V
atMR
VOO ~ VIT++ 0.2 V,
VIL = 0.3 x VDD,
atWDI
VDD ~VIT++ 0.2 V,
VIL = 0.3 x VOO,
MIN
TYP
MAX
UNIT
6
lIS
VIH = 0.7 x VOD
100
ns
VIH = 0.7 x VDO
100
ns
switching characteristics at RL = 1 MOo CL = 50 pF, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.1
1.6
2.3
s
140
200
280
ms
VOO~VIT++0.2 V,
50
250
VIL = 0.3 x VDD
VIH = 0.7 x VDO
50
250
tt(out)
Watchdog time out
VDD ~ VIT+ + 0.2 V,
See timing diagram
td
Delay time
VDD > VIT+ + 0.2 V,
See timing diagram
tpHL
Propagation (delay) time, high-to-Iow-Ievel
output
MR to RESET delay
tPLH
Propagation (delay) time, low-to-high-Ievel
output
MR to RESET delay
(TPS3707-xx only)
tPHL
Propagation (delay) time, high-to-Iow-Ievel
output
VDD to RESET delay
3
5
tpLH
Propagation (delay) time, low-to-high-Ievel
output
VDD to RESET delay
(TPS3707 -xx only)
3
5
tPHL
Propagation (delay) time, high-to-Iow-Ievel
output
0.5
1
0.5
1
tpLH
Propagation (delay) time, low-to-high-Ievel
output
PFI to PFO delay
ns
lIS
VOO= 2Vto 6V
~TEXAS
INSTRUMENTS
10-60
UNIT
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
lIS
TPS3705·30, TPS3705·33, TPS3705·50
TPS3707·25, TPS3707·30, TPS3707·33, TPS3707·50
PROCESSOR SUPERVISORY CIRCUITS WITH POWER·FAIL
SLVS184B - NOVEMBER 1998 - REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
NORMALIZED INPUT THRESHOLD VOLTAGE
vs
FREE·AIR TEMPERATURE AT Voo
o~ 1.002
VOO=6V
PFI = 1.05 V
MR = Open
~
S
~
~
1.001
Gl
I
~
'a
'0
1
~
""
"'
i
]
1
z
""'"
~
~
0.999
-40
-15
10
35
60
TA - Free-Air Temperature - °c
85
Figure 2
INPUT CURRENT
SUPPLY CURRENT
vs
vs
SUPPLY VOLTAGE
INPUT VOLTAGE AT MR
100
50
PFI=1.05V
MR = Open
TA=25°C
VOO=6V
PFI = 1.05 V
o
30
cc
CC
=.
C
~
10
D.
-10
a
:::I
,--V
~
/' .... TPS3707-S0
G
I
.5
fIl
I
I
-200
~
-300
C
E
-40°C/
-30
-400
-SO
-0.5
-SOO
0.5
1.5
2.5
3.5
4.5
VOO - Supply Voltage - V
5.5
6.5
V
,
./
/
=:- -100
I
,/
V-
II.
~50C
-1
0
I
4
2
3
VI-Input Voltage at MR - V
5
6
Figure 4
Figure 3
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-61
TPS3705-30, TPS3705-33, TPS3705-50
TPS3707-25, TPS3707-30, TPS3707-33, TPS3707-50
PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL
SlVS184B - NOVEMBER 1998 - REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
MINIMUM PULSE DURATION AT VOO
HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
VOO THRESHOLD OVERDRIVE
10
I
PFI=1.05V
MR = Open
III
:::l.
I
HIGH-LEVEL OUTPUT CURRENT
VOO=3.2V
8
Q
Q
>
I---::l....d---if--+--+--+- PFI = 1.05 V
t;j
c
0
;
2.51--+--+~~..,po."+--if--+--+--+---f
~
I
6
~
..
::I
Q
\
.!!
::I
4
D.
\
E
::I
E
';:
2
!iii
I
~
o
MR = Open
I
>
o
1
---
1
2~~~~~~~~~~
1.51--+--+--I1--+----+----i.-+~,--+---+--I
~
I
J:
I---r--
~
200
400
600
800
Voo - Threshold Overdrive - mV
0.51---t--+--I1---t--+-tt--lrH--H-t---I
O~O~--~~~--~~~~~~~~O
1000
IOH - High-Level Output Current - mA
Figure 6
Figure 5
LOW·LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
HIGH-LEVEL OUTPUT CURRENT
LOW·LEVEL OUTPUT CURRENT
3
6.5
6
>
.
5.5
~
~
4.5
'5
4
I
01
~
0
..
1.
1
01
:f
I
J:
VOO=6V
_
PFI=1.05V
MR=Open -
~
~
5
""
3.5
3
~
,~
"-
'"
2
1.5
~
0.5
o
o
I
~
~
85°C \
2.5
,.
>
'\.,
'5
a.
'5
"
0
'\.. -40°C
2.5
~
-30
II VV/
~
J
/ ~oC
85°V ~ ~ ;/
~~
0.5
~~
o~
o
I
/ / V/
1.5
:i:
.9
!.J
I I
2
1
Figure 7
~ ~~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
V
~
2 3 4 5 6 7 8 9 10 11 12 13
IOL - Low-Level Output Current - mA
FigureS
~TEXAS
1VIT
RESET
L
L
H
H
0
1
L
L
L
H
0
1
ORDERING INFORMATION
TPS380
ll
1l J
25 DCLK
l
Reel
Package
Nominal Supply Voltage
Nominal Threshold Voltage
Functionality
Family
functional block diagram
r-----------------------,I
I
I
I
I
TPS3801
MR-+.....------------~
3OkO
Reset
Logic
+
11mer
R1
VDD -+.....-.l\NIr---4I....----i
R2
GND
--!-I- - - - - - - '
I
I
Referenca
I
Voltage
I
of 1.137V
I
I
~-----------------------
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
I
I
I
I
I
TPS3801 J25, TPS3801 L30, TPS3801 K33, TPS3801150
ULTRA·SMALL SUPPLY VOLTAGE SUPERVISORS
SLVS219 - AUGUST 1999
timing diagram
Voo
V(NOM)
VIT
1.1 V
I
II
o
I
I
I I
I I
I
I
I I
I I
I I
II
II
I I
I I
I I
I
I
I
I
I I
I I
I I I
I I I
I I
I I
I I
I
I
I
II
I
I I
I I
I I
I
I I
I I
-I
I
I
i i
I
I
I
I
I
I
I
I
I
I
o
~--~--~--~~~----------~~~
**
Ie!
Ie!
Undefined Behavior of
RESET Output For VOO< 1.1 V
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
10-65
TPS3801 J25, TPS3801 L30, TPS3801 K33, TPS3801150
ULTRA-SMALL SUPPLY VOLTAGE SUPERVISORS
SLVS219-AUGUST 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage, Voo (see Note1) .............................................................. 7 V
All other pins (see Note 1) ........................................................... -0.3 V to 7 V
Maximum low output current, IOL ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 mA
Maximum high output current, IOH .......................................................... -5 mA
Input clamp current, 11K (VIVOO) ................................................... ±20 mA
Output clamp current, 10K (VOVoo) ............................................... ±20 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. See Dissipation Rating Table
Operating free-air temperature range, TA ............................................. -40°C to 85°C
Storage temperature range, Tstg .................................................... -65°C to 150°C
Soldering temperature .................................................................... 260°C
t
Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GNO. For reliable operation the device should not be operated at7 V for more than 1=1000h
continuously.
DISSIPATION RATING TABLE
PACKAGE
TA <25°C
POWER RATING
DERATING FACTOR
ABOVE TA 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
OCK
321 mW
2.6mW/oC
206mW
167mW
=
recommended operating conditions at specified temperature range
MAX
MIN
UNIT
Supply voltage, VOO
2
6
V
Input voltage. VI
0
Voo+0.3
V
High-level input voltage, VIH
Low-level input voltage, VIL
0.3xVOO
Input transition rise and fall rate at MR, allaV
Operating free-air temperature range, TA
-40
~TEXAS
INSTRUMENTS
1
,,~ ~ T~=~oC-
~
I
VOO=2.5V
MR = OPEN
2.75
I
:-rJ _~oCI\
2.50
0.00
3.00
I
:E'" 2.00
I
HIGH-LEVEL OUTPUT CURRENT
Voo = 6.0 V
MR=OPEN
6.00
~
6
Figure 2
HIGH-LEVEL OUTPUT VOLTAGE
5.00
4
2
Voo - Supply Voltage - V
Figure 1
.
~
TPS3801J25
-10
::I
In
~P'"
> 5.50 ~
I
.....
---
....
-10
TPS3801 J25, TPS3801 L30, TPS3801 K33, TPS3801150
ULTRA-SMALL SUPPLY VOLTAGE SUPERVISORS
SLVS219-AUGUST 1999
TYPICAL CHARACTERISTICS
INPUT CURRENT
NORMALIZED INTPUT THRESHOLD VOLTAGE
vs
vs
INPUT VOLTAGE AT MR
100
'&
~
VOO=6V
TA=25°C
0
(
~
/.,
-100
1
ii
5J
1.001
.....--~
;;; 1.000
>t::.
ell
0.999
~
0.998
-300
I
0.997
-400
:; 0.996
/
~
~
-2
o
/
/
J
'0
-600
1
4
2
L -...........
'"
"~
J
/
.~
V
z
0.995
-40
I
6
,I
VOO=2.3V
MR=OPEN
~
-200
:5
a=
1
FREE·AIR TEMPERATURE AT VOO
o
-20
VI- Input Voltage at MR - V
20
40
60
85
TA - Free-Air Temperatura - °C
Figure 6
Figure 5
MINIMUM PULSE DURATION AT Voo
vs
Voo THRESHOLD OVERDRIVE VOLTAGE
..
:!.
.5
3.5
Q
~
'Iii
2.5
c
0
~::I
2.0
Q
,;
1.5
a.
E
::I
E
1.0
::I
:5
:::&
1
MR~OPEN
3.0
0.5
1\
\
\
\,
"'
!
0.0
0.0
0.2
0.4
0.6
0.8
1.0
Voo - Threshold Overdrive Voltage - V
Figure 7
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-69
10-70
TPS3820-xx, TPS3823-xx, TPS3824-xx, TPS3825-xx, TPS3828-xx
PROCESSOR SUPERVISORY CIRCUITS
TPS3820T,TPS3823,TPS3828T
OBVPACKAGE
(TOP VIEW)
• Power-On Reset Generator With Fixed
Delay Time of 200 ms (TPS3823/4/5/8)
or 25 ms (TPS3820)
• Manual Reset Input (TPS3820/3/5/8)
• Push/Pull Reset (TPS3820/3/4/5), Reset
(TPS3824), or Open-Drain Outputs
(TPS3828)
RESET
GNO
MR
• Supply Voltage Supervision Range
2.5V,3V,3.3V,5V
RESET
• SOT23-5 Package
• Temperature Range ••• -40°C to 85°C
GNO
RESET
description
The TPS382x family of supervisors provides
circuit initialization and timing supervision,
primarily for DSP and processor-based systems.
1
T
::1100 nF
VOO
MR
WOI
WOI
5
VOO
4
WOI
2
3
RESET
GNO
RESET
5
VOO
4
MR
2
3
t This device is in the Product Preview
stege of development. Contect the
local TI sales office for availability
• Applications Using DSPs, Microcontrollers,
or Microprocessors
• Industrial Equipment
• Programmable Controls
RESET
TPS3823-33
\6
3
3.3 V
I
RESET
4
2
TPS382st ••• OBV PACKAGE
(TOP VIEW)
During power-on, RESET is asserted when
supply voltage Voo becomes higher than 1.1 V.
Thereafter, the supply voltage supervisor monitors Voo and keeps RESET active as long as Voo
remains below the threshold voltage VIT-. An
internal timer delays the return of the output to the
inactive state (high) to ensure proper system
reset. The delay time, tcJ, starts afterVoo has risen
above the threshold voltage VIT-' When the
supply voltage drops below the threshold voltage
VIT-, the output becomes active (low) again. No
external components are required. All the devices
of this family have a fixed-sense threshold voltage
VIT- set by an internal voltage divider.
VOO
VOO
TPS3824 ... OBV PACKAGE
(TOP VIEW)
• Watchdog Timer (TPS3820/3/4/8)
• Supply Current of 151lA (Typ)
typical application
u
u
u
5
MSP430C325
• Automotive Systems
• Portable/Battery-Powered Equipment
1/0
• Intelligent Instruments
GNO
GNO
1
.L
l
• Wireless Communications Systems
• Notebook/Desktop Computers
-!I
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Copyright@ 1999. Texas Instruments Incorporated
10-71
TPS3820-xx, TPS3823-xx, TPS3824-xx, TPS382S-xx, TPS3828-xx
PROCESSOR SUPERVISORY CIRCUITS
SLVS165B - APRIL i 998 - REVISED MAY 1999
description (continued)
The TPS3820/3lS/8 devices incorporate a manual reset input, MR. A low level at MR causes RESET to become
active. The TPS3824/S devices include a high-level output RESET. TPS3820/314/8 have a watchdog timer that
is periodically triggered by a positive or negative transition at WOI. When the supervising system fails to retrigger
the watchdog circuit within the time-out interval, ttout, RESET becomes active for the time period tel. This event
also reinitializes the watchdog timer. Leaving WOI unconnected disables the watchdog.
The product spectrum is designed for supply voltages of 2.S V, 3 V, 3.3 V, and S V. The circuits are available
in as-pin SOT23-S package. The TPS382x devices are characterized for operation over a temperature range
of -40°C to 8SoC.
PACKAGE INFORMATION
DEVICE NAME
THRESHOLD VOLTAGE
TPS3820-25DBVRt
2.25 V
MARKING
TPS3820-30DBVRt
2.63 V
TPS3820-33DBVRt
2.93 V
PDEI
TPS3820-50DBVRt
4.55 V
PDDI
TPS3823-25DBVR
2.25 V
PAPI
TPS3823-30DBVR
2.63 V
PAOI
TPS3823-33DBVR
2.93 V
PARI
TPS3823-50DBVR
4.55 V
PASI
TPS3824-25DBVR
2.25 V
PATI
TPS3824-30DBVR
2.63 V
PAUl
TPS3824-33DBVR
2.93 V
PAVI
TPS3824-50DBVR
4.55 V
PAWl
TPS3825-25DBVRt
2.25 V
TPS3825-30DBVRt
2.63 V
TPS3825-33DBVRt
2.93 V
PDGI
TPS3825-50DBVRt
4.55 V
PDFI
TPS3828-25DBVRt
2.25 V
TPS3828-30DBVRt
2.63 V
TPS3828-33DBVRt
2.93 V
PDII
TPS3828-50DBVRt
4.55 V
PDHI
t ThiS device is in the Product Preview stage of development. Contact the
local TI sales office for availability
~TEXAS
INSTRUMENTS
10-72
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS3820-xx, TPS3823-xx, TPS3824-xx, TPS3825-xx, TPS3828-xx
PROCESSOR SUPERVISORY CIRCUITS
SLVS1658 - APRIL 1998 - REVISED MAY 1999
FUNCTIONITRUTH TABLE
INPUTS
OUTPUTS
RESET
RESErt
L
VOo>VIT
0
L
H
L
1
L
H
H
0
L
H
H
1
H
L
MR*
tTPS3824/5
:t: TPS3820/315/8
functional block diagram
VOO
Resett
Watchdog
TImer Logic
52kn
40kn
WOI
trPS382415
:t:TPS38201315/8
timing diagram
VOO VIT
-~
1.1 V -
.~H
~
~',
'/,
~
"F-'--'------H-+-+----------------------'--=f'-----.~
I
~
I I4----+t- Id I
Id
/4---- tt(out)
... ~ Id
I I
I I
I
I I
I
I
I
I
I I
h
t""P t"
I
I
I
I
!
Ij I 1
I
Vii - :
I
I
I I
I
WOI
x = Don't care
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
10-73
TPS3820·xx, TPS3823·u, TPS3824-xJ(; TPS3825·xx; TPS3828-xx
PROCESSOR SUPERVISORY CIRCUITS
SLVSl65B - APRIL 1998 - REVISED MAY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltag~o (see Note 1) ............................................................ 6 V
Input voltage, MR, WDI (see Note 1) ........................................ -0.3 V to (Voo + 0.3 V)
Maximum low output current, IOL ........................................................... 5 mA
Maximum high output current, IOH ......................................................... -5 rnA
Input clamp current range, 11K (VI < 0 or VI > Voo) .......................................... ±10 mA
Output clamp current range, 10K (VO < 0 or Vo > Voo) ...................................... ±10 rnA
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-airtemperature range, TA ........................................... -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Soldering temperature .................................................................... 260°C
t
Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These ara stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" Is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
DISSIPATION RATING TABLE
=
PACKAGE
TA s 25°C
POWER RATING
OPERATING FACTOR
ABOVE TA = 25°C
TA=70°C
POWER RATING
TA 85°C
POWER RATING
DBV
350 mW
3.5 mW/oC
192mW
140mW
recommended operating conditions
Supply voltage, VDD
MIN
MAX
1.1
5.5
V
VDD+0.3
V
0
Input voltage, VI
High-level input voltage at MR and WDI, VIH
Input transition rise and fall rate at MR or WDI, 1lt/IlV
-40
Operating free-air temperature range, TA
~TEXAS
10-74
V
0.7xVDD
LOW-level input voltage, VIL
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
UNIT
0.3xVDD
V
100
ns/V
85
°C
TPS3820-xx, TPS3823-xx, TPS3824-xx, TPS3825-xx, TPS3828-xx
PROCESSOR SUPERVISORY CIRCUITS
SLVSl65B-APRIL 1998-REVISED MAY 1999
electrical characteristics over recommended operating free-alr temperature range (unless
otherwise noted)
TEST CONDITIONS
PARAMETER
RESET
VOH
High-level output voltage
RESET
TPS3B2x-25
VOO=VIT-+0.2 V
IOH =-201lA
TPS382x-30
TPS382x-33
Voo = VIT- + 0.2 V
IOH =-301lA
TPS382x-50
Voo = VIT_ + 0.2 V
IOH = -120 IlA
TPS3824-25
TPS3825-25
VOO ~ 1.8 V, IOH = -100 IlA
MIN
TYP
MAX
0.8 x Voo
V
VOO-1.5V
TPS3824-30
TPS3825-30
TPS3824-33
TPS3825-33
UNIT
V
0.8xVOO
VOO ~ 1.8 V, IOH =-150 IlA
TPS3824-50
TPS3825-50
TPS3824-25
TPS3825-25
RESET
VOL
Low-level output voltage
RESET
TPS3824-30
TPS3825-30
TPS3824-33
TPS3825-33
VOO = VIT- + 0.2 V
IOL=1 rnA
VOO = VIT- + 0.2 V
IOL= 1.2 rnA
TPS3824-50
TPS3825-50
VOO = VIT_ + 0.2 V
IOL=3mA
TPS382x-25
Voo = VIT_-0.2 V
IOL=1 rnA
TPS382x-3O
TPS382x-33
TPS382x-50
VOO = VIT_-o.2 V
IOL= 1.2 rnA
TPS382x-25
TPS382x-3O
TPS382x-33
VIT-
Negative-going input threshold
voltage (see Note 3)
V
0.4
V
0.4
V
Voo=VIT_-0.2V
IOL=3mA
VOO ~ 1.1 V, IOL = 20 IlA
Power-up reset voltage (see Note 2)
0.4
TA=0°C-85°C
2.21
2.25
2.30
2.59
2.63
2.69
2.88
2.93
3
TPS382x-50
4.49
4.55
4.64
TPS382x-25
2.20
2.25
2.30
TPS382x-30
TPS382x-33
TA = -40°C - 85°C
TPS382x-50
2.57
2.63
2.69
2.86
2.93
3
4.46
4.55
4.64
V
V
TPS382x-25
Vhys
Hysteresis at VOO input
TPS382x-30
30
TPS382x-33
TPS382x-50
mV
50
NOTES: 2. The lowest supply voltage at which RESET becomes active. t r, VOO ~ 15 fJBIV
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 11F) should be placed near the supply terminals.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75285
10-75
TPS3820-xx, TPS3823-xx, TPS3824-xx, TPS3825-xx, TPS3828-xx
PROCESSOR SUPERVISORY CIRCUITS
SLVS1658 - APRIL 1998 - REVISED MAY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
IIH(AV)
TEST CONDmONS
IIH
High-level input current
IlL
Low-level input current
lOS
Output short-circuit current
(see Note 4)
MAX
WDI = 0.3 V, VDD = 5.5 V
time average (dc = 12%)
-15
WDI
WDI= VDD
140
190
MR
MR = VDD x 0.7,
VDD=5.5V
-40
-60
WDI
WDI = 0.3 V, VDD = 5.5 V
140
190
MR
MR=0.3V, VDD=5.5V
-110
-160
WDI
Average low-level input current
TYP
120
Average high-level input current
IIL(AV)
MIN
WDI=VDD,
time average (dc = 88%)
UNIT
IIA
TPS382x-25
RESET
TPS382x-30
TPS382x-33
-400
VDD = VIT, max + 0.2 V,
VO=OV
TPS382x-50
IDD
-800
WDI and MR unconnected,
Outputs unconnected
Supply current
15
Internal pullup resistor at MR
Ci
Input capacitance at MR, WDI
IIA
VI = 0 V to 5.5 V
25
IIA
52
kO
5
pF
NOTE 4: The RESET short-circUit current IS the maximum pullup current when RESET is driven low by a I1P bidirectional reset pin.
timing requirements at RL
=1 Mo., CL =50 pF, TA =25°C
PARAMETER
tw
Pulse width
TEST CONDITIONS
tpHL
atMR
VDD 2:VIT_+ 0.2 V,
VIL = 0.3 x VDD,
VIH = 0.7 x VDD
1
I1S
I1S
atWDI
VOO 2:VIT_+ 0.2 V,
VIL = 0.3 x VOO,
VIH = 0.7 x VOO
100
ns
=1 Mo., CL =50 pF, TA =25°C
Watchdog time out
Delay time
Propagation (delay) time,
high-to-Iow-Ieveloutput
TEST CONDITIONS
TPS3820
TPS382314/8
TPS3820
TPS3823/4/5/8
MIN
TYP
MAX
UNIT
VOO 2: VIT_ + 0.2 V,
See TIming Oiagram
112
200
310
ms
0.9
1.6
2.5
s
VOO2:VIT_+0.2 V,
See timing diagram
15
25
37
120
200
300
VOD2:VIT_ +0.2 V,
VIL=0.3 x VOO,
VIH=0.7 x VOO
MR to RESET delay
(TPS3820/315/8)
VDO to RESET delay
VOO to RESET delay (TPS382415)
10-76
UNIT
VDD = VIT- - 0.2 V
PARAMETER
Icl
MAX
6
VDD = VIT- + 0.2 V,
switching characteristics at RL
ttout
MIN
atVDD
VIL = VIT- - 0.2 V,
VIH = VIT- + 0.2 V
:lllExAs
INSTRUMENTS
pogr OFFICF BOX
8..'i5.~03
• DALLAS; TEXAS 75265
ms
0.1
I1S
25
25
TPS3820-xx, TPS3823-xx, TPS3824-xx, TPS3825-xx, TPS3828-xx
PROCESSOR SUPERVISORY CIRCUITS
SLVS1S5B-APRIL 1998- REVISED MAY 1999
TYPICAL CHARACTERISTICS
NORMALIZED INPUT THRESHOLD VOLTAGE
~
~
SUPPLY CURRENT
vs
vs
FREE-AIR TEMPERATURE AT VOO
SUPPLY VOLTAGE
1.001
19
~
~
~
I
t
~
I
~
0.998
0.997
1
~
~
L
0.999
i
i
MR=Open
WOI = Open
TA=25°C
17
-'-
V
15
"
CC
::I.
I
C
13
~
11
(.)
aa.
9
b
5
::>
In
E
TPS382x-33
r1\.,./
7
I
I
I-'
3
0.996
-15
10
60
35
TA - Free-Air Temperature - °C
-1
85
v
-0.5
0.5
1.5
2.5
3.5
4.5
VOO - Supply Voltage - V
Figure 1
. vs
INPUT VOLTAGE AT MR
LOW-LEVEL OUTPUT CURRENT
50.---r---r---~--~--'---,---,
VOO=5.5V
WOI = Open
3
>
I
.1
I. .
!
VOO = 2.66 V
WOI = Open
2.5 t- MR=Open
L
1. 1.
I
, I
CD
cc::I.
I
~
I
-50
2
"S
~
0
(.)
.5
6.5
LOW-LEVEL OUTPUT VOLTAGE
vs
"S
a.
5.5
Figure 2
INPUT CURRENT
C
~
::>
/
f"
/"
::>
L
V
0.995
-40
.."
I-"'"
J
1.5
85°C-
S
-100
.:
.9
....I
-150
~
-200 UlL....L.....__.l......__.l......__..I..-__..L....__..L....---I
-1
0
2
3
4
5
6
VI-Input Voltage at MR - V
11 If) )
j
•
I
IJ
0.5
~
~~
o
o
/ ~~
"./ ~
~ 10-"'""
-11-
2
3
4 5
6
7
8 9
IOL - Low-Level Output Current - mA
Figure 3
10
Figure 4
~TEXAS
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265
10-77
TPS382G-xx, TPS3823-xx, TPS3824-xx, TPS3825-xx, TPS3828-xx
PROCESSOR SUPERVISORY CIRCUITS
SLVSl65B - APRIL 1998
REVISED MAY 1999
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
3.5
>
I
t
g'S
~
1
~
fI
:c
~
-50
-100
-150
-200
-250
-100 -200 -300 -400 -600 -600 -700
IOH - High-level Output CUrrent-1IA
IOH - High-level Output Current -IIA
Figure 5
Figure 6
MINIMUM PULSE DURATION AT VOO
vs
VOO THRESHOLD OVERDRIVE
10
I
WOI = Open
MR=Open
~
I
Q
e'Iii
8
c
~
d
~
II.
E
::J
E
C
!iii
I
6
4
2
\
\
\
I'...
o
o
-
~
~
r---- r--
200
400
600
800
Voo - Threshold OVerdrive - mV
Figure 7
~TEXAS
10-78
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1000
TPS5510
3-CHANNEL POWER SUPPLY SUPERVISOR
D OR P PACKAGE
(TOP VIEW)
• Over Voltage Protection and Lock Out for
5 V, 3.3 V, and 12 V
• Under Voltage Protection and Lock Out for
5V and 3.3 V
• Fault Protection Output with Open Drain
Output Stage
• Open Drain Power Good Output Signal for
Power Good Input, 5 V and 3.3 V
P G I [ ] a PGO
GND
2
7
Vee
FPO
PSON
3
4
6
5
VS5
VS33
• 300 ms Power Good Delay
• 75 ms Delay for 5-V and 3.3-V Short-Circuit
Turn On Protection
• 38 ms PSON Control Debounce
• 73!lS Width Noise Deglitches
• Wide Power Supply Voltage Range
from 4 Vto 15 V
description
The TPS5510 is designed to minimize extemal components of personal computer switching power supply
systems. It provides protection circuits, power good indicator, fault protection output (FPO), and a PSON control.
OVP (Over Voltage Protection) monitors 5 V, 3.3 V, and 12 V (12 V OV detects via Vee terminal). UVP (Under
Voltage Protection) monitors 5 V and 3.3 V. When an OV or UV condition is detected, the PGO (power good
output) is asserted low and FPO is latched high. PSON from low to high resets the protection latch. UVP function
will be enabled 75 ms after PSON is set low and debounced.
Power good feature monitors PGI, 5 V and 3.3 V and issues a power good signal when they are ready.
The TPS5510 is characterised for operation from TJ = -40°C to 125°C junction temperature.
PGI
1
5 VSB
?
PGO
TPS5510
~~
~ PGI
r
2
3
4
12V
PGO
GND
FPO
PSON
Vee
VSS
VS33
L
."
-'f-
0.5 V
Drop
7
~
I....
6
5
VSB
5V
3.3 V
Figure 1. TPS5510 Typical Application
~TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS, TEXAS 75265
Copyright © 199B, Texas Instruments Incorporated
10-79
TPS5510
3-CHANNEL POWER SUPPLY SUPERVISOR
SLVS168-JULY 1998
functional block diagram
VCC--.-----------------------------------~------~~-------.
VS33
75ms
Delay
3.3UV
Counter
R
EN
VCC
Pull-High
Resistor
PGO
Vref
5UV
EN
RST
Vref
PGI ------------\
~TEXAS
1Q-80
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5510
3-CHANNEL POWER SUPPLY SUPERVISOR
SLVS168-JULY 1998
Terminal Functions
TERMINAL
NAME
110
NO.
DESCRIPTION
VS33
5
I
VS5
6
I
GND
2
FPO
3
0
Inverted fault protection output, open drain output stage
PGI
1
I
Power good input signal pin
PGO
8
0
Power good output signal pin, open drain output stage
PSON
4
I
ON/OFF control input pin
VCC
7
I
Supply voltage/12 V over voltage protection input pin
3.3 V over/under voltage protection input pin
5 V over/under voltage protection Input pin
Ground
DISSIPATION RATING TABLE
=
PACKAGE
TAS25°C
POWER RATING
OPERATING FACTOR
ABOVE TA 25°C
TA 125°C
POWER RATING
P
1092mW
8.74mWFC
218mW
0
730mW
5.84mWFC
146mW
=
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supplyvoltage,Vcc,(seeNote1) .................................. " ....................... 16V
Output voltage, Vo (FPO) .................................................................. 16 V
Output voltage, Vo (PGO) .................................................................. 8 V
Supply current, ICC ....................................................................... 1 rnA
Continuous total power dissipation ..................................... see Dissipation Rating Table
Operating junction temperature range, TJ .......................................... -40°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to the device GND terminal.
recommended operating conditions
TEST CONDITIONS
Supply voltage, VCC
Input voltage, VI
Output voltage, Vo
4
TYP
MAX
UNIT
15
V
7
V
FPO
15
V
PGO
7
V
125
°C
FPO
30
mA
PGO
10
mA
PSON, VS5, VS33, PGI
Operating junction temperature, TJ
Output sink current, IO(sink)
MIN
-40
Supply voltage rising time, tr
NOTE 2: VCC riSing and failing slew rate must be less then 14 V/ms.
See Note 2
1
ms
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75285
1Q--81
TPS5510
3-CHANNEL POWER SUPPLY SUPERVISOR
SLVS168-JULY 1998
electrical characteristics, Vee =5 V, TJ
=full range. (unless otherwise specified)
over voltage protection
PARAMETER
TEST CONDITIONS
VS33
Over-voltage threshold
ILKG
VOL
MIN
TYP
MAX
3.9
4.1
4.3
VS5
5.7
6.1
6.5
Vee
13.3
13.8
14.3
Leakage current (FPO)
Low level output voltage (FPO)
V(FPO)=5V
5
Isink = 10 mA
0.3
ISink= 30 mA
0.7
UNIT
V
I1A
V
PGland PGO
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.141
1.192
1.242
V
VS33
2.71
2.83
2.95
VSS
4.1
4.3
4.47
49
75
114
ms
5
I1A
0.4
V
Input threshold voltage (PGI)
Under-voltage threshold
Short circuit protection delay time
3.3V,5V
ILKG
Leakage current (PGO)
PGO=5V
VOL
Low level output voltage (PGO)
Sink current = 10 mA
V
PSON control
PARAMETER
TEST CONDITIONS
Input pull-up current
MIN
PSON=OV
High-level input voltage
TYP
MAX
UNIT
I1A
150
2.4
V
Low-level Input voltage
1.2
V
total device
PARAMETER
lee
TEST CONDITIONS
Supply current
switching characteristics, Vee
MAX
TEST CONDITIONS
MIN
TYP
MAX
Delay time (PGlto PGO)
200
300
450
ms
De-bounce time (PSON)
24
38
57
ms
Noise deglitch time
47
73
110
I1S
~1ExAs
INSTRUMENTS
10-82
TYP
=5 V, TJ =full range
PARAMETER
lei
It>
MIN
PSON=5V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
TPS5510
3-CHANNEL POWER SUPPLY SUPERVISOR
SLVS168 - JULY 1998
timing chart
I
I
Vcc /
Reset
R
S
I
I
I
I
I
I
i
iI iI
I
!
I
I
I
I
J
I
I
I I
i.
~'------+!---InJ
tl
________~I
'-------I
PGI--.I:
I
12 V
/1
III
1
---...I,
----' I
PGO
__--+1
~
~
I
'\
[1:!
1
-1..
-+.--L
td
I I
I
I
J\
L...-_ _..L...!....I...!- ' \ . .
II
I
I
II
I I
I
I
1111
I II
L-
r----..
FPO - - ,
L
In.
I~----I~I------+_----I--------~I~II
I
Q
3.3 V
5V
I
I
I
II
--nl
"--
I
I
I
I
II
I-I
I
I
I
I
I
I
I
II~I 1/
: !Ii
I I
I I
I I
1
r
tb-+I
~
1'1-1---I ~
II
11'-,-It\.
J]
)
WI ~:
:
I
I
I !
I
I I I I
I I I I
td +--+-+ I
I I
I I I I
I I
I
I I tb -+1 I+-Protect Occur
I I
I
i+f-+
I
r r
PSON
OFF
:: "'---
I b-.I+---I ...
I I
PG OFF delay
I
:
PSON
ON
r-I- - -
~I
! IVI :
'I
I
II
I
I
11,111
I
\.;
"
III'+--":
III ~III
\.1
I
I
\..
~-;I_---I
I
I
--+lI :+---t
I
AC
OFF
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
·10-83
10-84
TPS5511
3-CHANNEL POWER SUPPLY SUPERVISOR
D OR P PACKAGE
(TOP VIEW)
• Over Voltage Protection and Lock Out for
5 V, 3.3 V, and 12 V
• Fault Protection Output with Open Drain
Output Stage
P G I ( J e PGO
2
7 Vee
FPO 3
6 VS5
PSON 4
5 VS33
GND
• Open Drain Power Good Output Signal for
Power Good Input, 5 V and 3.3 V
• 300 ms Power Good Delay
• 2.3 ms PSON Control to FPO Turn-Off Delay
• 38 ms PSON Control Debounce
• 73
IJ.S Width Noise Deglitches
• Wide Power Supply Voltage Range
from 4 V to 15 V
description
The TPS5511 is designed to minimize the external components of personal-computer switching power supply
systems. It provides protection circuits, power good indicator, fault protection output (FPO), and PSON control.
OVP (over voltage protection) monitors 5 V, 3.3 V, and 12 V (12 V OV detects via Vee terminal). When an OV
condition is detected, the PGO (power good output) is asserted low and FPO is latched high. PSON from low
to high resets the protection latch. There is a 2.3-ms tum-off delay from PSON to FPO. There is no delay during
tum on.
Power good feature monitors PGI, 5 V and 3.3 V under voltages and issues a power good signal when they are
ready.
The TPS5511 is characterized for operation from TJ
= -40°C to 125°C junction temperature.
PGI
1
5 VSB
?
PGO
TPS5511
~~
c...-!.
r
2
3
4
PGI
12V
PGO
GND
FPO
PSON
VCC
VS5
VS33
r!-
."
-'f-
0.5 V
Drop
7
L..oI
I~
6
5
VSB
5V
3.3 V
Figure 1. TPS5511 Typical Application
:II
TEXAS
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS, TEXAS 75265
Copyright Ii:) 1998, Texas Instruments Incorporated
1()...85
TPS5511
3-CHANNEL POWER SUPPLY SUPERVISOR
SLVS170-AUGUST 1998
functional block diagram
Vee--~----------------------------------~------~~-------'
VS5
Reset
Domlnent
Latch
2.3ms
Delay
VS33
Reset
EN
~-=-=-t-----+-
RTT
RST
Vee
Pull-High
Resistor
PGO
Vref
5UV
EN
RST
Vref
PGI ------------1
~TEXAS
10-86
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5511
3-CHANNEL POWER SUPPLY SUPERVISOR
SLVS170-AUGUST 199B
Terminal Functions
TERMINAL
NAME
DESCRIPTION
I/O
NO.
VS33
5
I
VS5
6
I
3.3 V over/under voltage protection input pin
GND
2
FPO
3
0
PGI
1
I
Power good Input signal pin
PGO
8
0
Power good output signal pin, open drain output stage
PSON
4
I
ON/OFF control input pin
VCC
7
I
Supply voltagel12 V over voltage protection Input pin
5 V over/under voltage protection input pin
Ground
Inverted fault protection output, open drain output stage
DISSIPATION RATING TABLE
PACKAGE
TAS25°C
POWER RATING
OPERATING FACTOR
ABOVE TA 25°C
TA= 125°C
POWER RATING
P
1092mW
8.74mWfOC
218mW
0
730mW
5.B4mWfOC
146mW
=
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage, Vee, (see Note1) ........................................................... 16 V
Output voltage, Va (FPO) .................................................................. 16 V
Output voltage, Va (PGO) .................................................................. 8 V
Supply current, lee ....................................................................... 1 rnA
Continuous total power dissipation ..................................... see Dissipation Rating Table
Operating junction temperature range, TJ .......................................... -40°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute·maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to the device GND terminal.
recommended operating conditions
TEST CONDITIONS
Input voltage, VI
Output voltage, Vo
TYP
MAX
UNIT
15
V
7
V
FPO
15
V
PGO
7
V
125
°c
FPO
30
mA
PGO
10
mA
PSON, VS5, VS33, PGI
-40
Operating junction temperature, TJ
Output sink current, IO(sink)
MIN
4
Supply Voltage, VCC
Supply voltage rising time, tr
..
NOTE 2: VCC rlsmg and failing slew rate must be less then 14 V/rns .
See Note 2
1
ms
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
1Q-87
TPS5511
3-CHANNEL POWER SUPPLY SUPERVISOR
SLVS170-AUGUST 1998
electrical characteristics, Vee =5 V, TJ
=full range. (unless otherwise specified)
over voltage protection
PARAMETER
TEST CONDITIONS
VS33
Over-voltage threshold
ILKG
VOL
MIN
TYP
MAX
3.9
4.1
4.3
VS5
5.7
6.1
6.5
Vee
13.3
13.8
14.3
Leakage current (FPO)
Low level output voltage (FPO)
V(FPO)=5V
5
ISink= lOrnA
0.3
Isink=30mA
0.7
UNIT
V
!1A
V
PGland PGO
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.141
1.192
1.242
V
Ivs33
2.71
2.83
2.95
IVS5
4.1
4.3
4.47
Input threshold voltage (PGI)
Under-voltage threshold
ILKG
Leakage current (PGO)
PGO=5V
VOL
Low level output voltage (PGO)
Sink current = lOrnA
5
0.4
V
!1A
V
PSON control
PARAMETER
TEST CONDITIONS
Input pull-up current
MIN
PSON=OV
TYP
MAX
High-level input voltage
UNIT
!1A
150
V
2.4
Low-level input voltage
1.2
V
total device
PARAMETER
lee
TEST CONDITIONS
Supply current
MIN
TYP
MAX
PSON=5V
switching characteristics, Vee =5 V, TJ =full range
MIN
TYP
MAX
UNIT
Idl
Delay time (PGI to PGO)
PARAMETER
200
300
450
ms
tb
De-bounce time (PSON)
24
38
57
ms
Noise deglitch time
47
73
110
j1S
tb+ 1.1
1tJ+2.3
tb+ 4
ms
1d2
TEST CONDITIONS
PSON to FPO delay time
~TEXAS
lD-88
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS5511
3-CHANNEL POWER SUPPLY SUPERVISOR
SLVS170 - AUGUST 1998
timing chart
"'
"'
', " "','"
,
Vcc
Reset
.I
,
,,
,
,
I
---1
'
,,
------I~I
Q
_ _ _ _---11
I
12V
,
,
,"
"
I "
I
, II
tl
S
3.3V
5V
I
I
,
I
f\
!1
i\
I
~--~
/:
----'
l
_ _.oJ. I
.
II In
I I
L111..---, I
~I
,".
/1, 1\
,.
I, , ,,, \.
,
,
L
II, ,
II
1
II~ ' /
''''
I
I
I
II"'\.
II
\..
,
'1-,- - -
, ~
I, ,! \.
,, 1\I\.
.
I
,
,,
! !
VI
'
I 11
/1 ,'","
i ~i
" \.,'\..t---/
,
~
I!I
~--~I~I
'-._-1-..1.
,
,
,,
,
,
~
,I
,I
I,
1..._ _
I]
,'W-H ~i
"'---I I I ! II I I I 11--+1_ __
I I I III : -'1 I+---.I, '+---I
I ,"'"
I'+---- ,
, ,
_ _.oJ'"
PGO
,"
,
~""""--------+----'!AJ
R
PGI
,
,
----+1-1[1
,.-rtd1 ---.,
1d1
I
i.+-t-t,
td1'-+--+I
,
,
:
',PG Off Delay
td2 ---.'
, ,
Protect Occur
I I~
tb
tb ---.,
'1_'
---','
~
PSON
OFF
"
,
AC
OFF
PSON
ON
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-89
10-90
TL7702A, TL7705A,TL7709A, TL7712A, TL7715A
SUPPLY-VOLTAGE SUPERVISORS
o OR P PACKAGE
• Power-On Reset Generator
(TOP VIEW)
• Automatic Reset Generation After Voltage
Drop
REF 0 8
RESIN 2
7
eT 3
6
GND 4
5
• Wide Supply-Voltage Range
• Precision Voltage Sensor
• Temperature-Compensated Voltage
Reference
VCC
SENSE
RESET
RESET
• True and Complement Reset Outputs
• Externally Adjustable Pulse Duration
description
The TL77xxA family of integrated-circuit supply-voltage supervisors is specifically designed for use as reset
controllers in microcomputer and microprocessor systems. The supply-voltage supervisor monitors the supply
for undervoltage conditions at the SENSE input. During power up, the RESET output becomes active (low)
when Vee attains a value approaching 3.6 V. At this point (assuming that SENSE is above VIT+), the delay timer
function activates a time delay, after which outputs RESET and RESET go inactive (high and low, respectively).
When an undervoltage condition occurs during normal operation, outputs RESET and RESET go active. To
ensure that a complete reset occurs, the reset outputs remain active for a time delay after the voltage at the
SENSE input exceeds the positive-going threshold value. The time delay is determined by the value of the
external capaCitor C" td 1.3 x 104 x CT, where CT is in farads (F) and ~ is in seconds (s).
=
During power down (assuming that SENSE is below VIT-), the outputs remain active until the Vee falls below
a maximum of 2 V. After this, the outputs are undefined.
An external capacitor (typically 0.1 I1F for the TLnxxAC and TL77xxAl) must be connected to REF to reduce
the influence of fast transients in the supply voltage.
The TL77xxAC series is characterized for operation from O°C to 70°C. The TLnxxAl series is characterized
for operation from -40°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP
FORM
SMALL
OUTLINE
(D)
PLASTIC
DIP
(P)
O°Cto 70°C
TL7702ACD
TL7705ACD
TL7709ACD
TL7712ACD
TL7715ACD
TL7702ACP
TL7705ACP
TL7709ACP
TL7712ACP
TL7715ACP
TL7702ACY
TL7705ACY
TL7709ACY
TL7712ACY
TL7715ACY
-40°C to 85°C
TL7702AID
TL7705AID
TL7709AID
TL7712AID
TL7715AID
TL7702AIP
TL7705AIP
TL7709AIP
TL7712AIP
TL7715AIP
-
TA
(V)
The 0 package IS available taped and reeled. Add the suffix R to the
device type (e.g., TL7702ACDR). Chip forms are tested at 25°C.
~TEXAS
Copyright © 1999. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
1lHl1
Tl7702A;Tl7705A; Tl7709A;Tl7712A, TL7715A
SUPPLY-VOLTAGE SUPERVISORS
SLVS028E - APRIL 1983 - REVISED JULY 1999
functional block diagram
The functional block diagram is shown for illustrative purposes only; the actual circuit includes a trimming
network to adjust the reference voltage and sense-comparator trip point.
Vee
8
~ ~100 IJA
eT
SENSE
RESET
3
7
RESET
R1
(see Note A)
R2
(see Note A)
RESIN
2
1
4
GND----__----------~--------------------------~------------~
NOTES: A. TL7702A: R1 = 0 n, R2 = open
TL7705A: R1 = 7.8 kQ, R2 = 10 kQ
TL7709A: R1 = 19.7 kQ, R2 = 10 kQ
TL7712A: R1 = 32.7 kQ, R2 = 10 kQ
TL7715A: R1 = 43.4 kQ, R2 = 10 kQ
B. Resistor values shown are nominal.
timing diagram
-g-
Vee and SENSE
Threshold Voltage
Vee~3.6V-
I
II
II
RESlJET
I l1li
I
Output
Undefined
IT
1<1
u
I 1
l 14
I
I
·j-I_1<1_--,1 I
~TEXAS
10-92
1\--. ·ee-'·
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ILN".
fl
Output
Undefined
REF
TL7702A, TL7705A, TL7709A, TL7712A, TL7715A
SUPPLY-VOLTAGE SUPERVISORS
SLVS028E - APRIL 1983 - REVISED JULY 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ........................................................... 20 V
Input voltage range, VI, RESIN .................................................... -0.3 V to 20 V
Input voltage range, VI, SENSE: TL7702A (see Note 2) ................................ -0.3 V to 6 V
TL7705A . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. -0.3 V to 20 V
TL7709A ............................................ -0.3 V to 20 V
TL7712A, TL7715A ................................... -0.3 V to 20 V
High-level output current, IOH' RESET .................................................... -30 mA
Low-level output current, IOL' RESET ..................................................... 30 mA
Package thermal impedance, 9JA (see Notes 3 and 4): D package ............................ 97°C/W
P package .......................... 127°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package ................. 260°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t
Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other cond~ions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. For proper operation of the TL7702A, the voltage applied to the SENSE terminal should not exceed Vee - 1 V or 6 V, whichever
is less.
3. Maximum power dissipation is a function of TJ(max), 9JA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is Po = (TJ(max) - TA)/9JA. Operating at the absolute maximum TJ of 150De can impact reliability.
4. The package thermal impedance is calculated In accordance with JESO 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
Supply voltage, Vee
MIN
MAX
3.5
18
2
High-level input voltage at RESIN, VIH
Input voltage, SENSE, VI
TL7702A
0
V
V
0.6
loW-level input voltage at RESIN, VIL
UNIT
V
See Note 2
TL7705A
0
10
TL7709A
0
15
TL7712A
0
20
TL7715A
0
V
20
-16
mA
Low-level output current, RESET, IOL
16
mA
Timing capacitor, eT
10
I1F
High-level output current, RESET, IOH
TL77xxAe
Operating free-air temperature range, TA
TL77xxAi
0
70
-40
85
De
NOTE 2: For proper operation olthe TL7702A, the voltage applied to the SENSE terminal should not exceed Vee -1 V or 6 V, whichever IS less.
~lExAs
INSTRUMENTS
POST OFFICE sox 655303 • DALLAS, TEXAS 75265
10--93
TL7702A,TL7705A,TL7709A, TL7712A, TL7715A
SUPPLY-VOLTAGE SUPERVISORS
SLVS028E-APRIL 1983 - REVISED JULY 1999
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TL77xxAC
TL77xxAl
TEST CONDITIONSt
MIN
VOH
High-level output voltage, RESET
IOH =-16mA
VOL
Low-level output voltage, RESET
IOL= 16mA
Vref
Reference voltage
TA=2Soe
2.S8
2.S3
2.S8
4.S
4.55
4.6
7.S
7.6
7.7
TL7712A
10.6
10.8
11
TL771 SA
13.2
13.S
13.8
TL7709A
TA=2Soe
TL7709A
1S
TA=2soe
35
45
-100
VI =0.4V
SENSE
t
20
VI =2.4 Vto Vee
RESIN
TL7702A
O.S
Vref
C
tCI.
1.0
:::I
C
C 0.8
~
~
TA = 85°C
TA=25°C
TA=-40°C
0.6
I
TA= 5°C -
13
TA=J5 0 C -
0
~
III
.c
0
t
0.4
0
9
14
:::I
:::I
II)
15
II)
I
i
TA=~O°C
I
E
0
16
E
1.2
0.2
0
12
lJ
11
.5
E
1=
10
CD
0
10
20
30
40
50
60
Figure 6. Supply Current vs Supply Voltage
506
~
.....
I
.....
~
=e
I
J
i
0.8
~
0.6
0.4
I
>'"
0
2
3
4
~
500
498
496
1/r--
"\
5
6
Figure 8.IOL vs VOL Characteristics
.......
r'\.
~
1'-
TA=25°e
Vs=498.3mV
492
490
488
-75 -50 -25
IOL - Low Level Output Current - mA
0
25
50
75 100 125 150
TA - Free-Air Temperature - °C
Figure 9. Timing Capacitor Charge Current
vs Supply Voltage
~TEXAS
10-106
60
I
Vs = 500.8 mV
- V
502
494
0.2
0
50
Tl=2~oe
504
1.0
0
'ii
~
40
Figure 7. Timing Capacitor Charge Current
vs Supply Voltage
1.2
t
30
VCC - Supply Voltage - V
Vce - Supply Voltage - V
>
I
5
20
10
0
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL7700
SUPPLY-VOLTAGE SUPERVISOR
SLVS220-JULY 1999
TYPICAL CHARACTERISTICS
3.5
3.4
3.0
3.2
~
3.0
I
2.8
I
c(
::L
2.6
-
!"'......
2.4
......
.......... ~
I
.5
1.0
81
c
0.5
I
I
II
0
c'l
2.0
J
1.5
'5
a.
..........
V
2.0
CJ
2.2
_Ill
2.5
I
C
~
::I
I
_Ill
1.8
~.5
1.6
-75 -50 -25
-1.0
0
25
50 75 100 125 150
o
I)
~',-
-1f
0.1 0.2 0.3 0.4 0.5 0.6 1.0 10
40
Vs - Sense Input Voltege - V
TA - Free·Alr Temperature - °C
Figure 10. Sense Input Current vs Temperature
Figure 11. Vs vs Is Characteristics
109
III
::L
I
c
t
107
~
105
::I
Q
GI
'5
/
V
104
103
I
102
J.
V
106
~
0
v
108
101
1
V
1
~
/
V
101 102 103 104 105 106 107 108 109
Ct - TIming Capacitor -
pF
Figure 12. Timing Capacitor vs Output Pulse Duration
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
10-107
TL7700
SUPPLY-VOLTAGE SUPERVISOR
SLVS220-JULY 1999
TYPICAL CHARACTERISTICS
Test
.----.----~I---o Point 1
TP
2.2kQ
240kO
Vee
/
V
RESET I-----~t---O Test
Point 2
ru
Vs SENSE
~
\
/
/
6V
3OkO
P2
\ -
\
J
\..
X·Axls
Figure 13. Vee vs Output Test Circuit 1
=0.2 mS I Division
Figure 14. Vee vs Output Waveform 1
Test
.----t---~I---o Point 1
T 1
2.2kO
240kO
J
Vee
RESET I--~"""--O Test
Point 2
V
s SENSE
ru
I
6V
V
/
30kO
\
\
TP2
\
J
'X·Axls
Figure 15. Vee vs Output Test Circuit 2
=0.2 mS I Division
Figure 16. Vee vs Output Waveform 2
~TEXAS
10-108
\
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL7700
SUPPLY-VOLTAGE SUPERVISOR
SLVS220-JULY 1999
TYPICAL CHARACTERISTICS
r - - - - 4 t - - - - - -......- - - - - . - O Test
Point 1
2.2kQ
240kn
RESET
v
s SENSE
T~1
I---e--._-o Test
Point 2
30kQ
/
M
/
I
TF2
\
X·Axis
Figure 17. Vee vc Output Test Circuit 3
\
/
ru
\
\
-~
=0.2 rnS I Division
Figure 18. Vee vs Output Waveform 3
-!I
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-109
TL7700
SUPPLY-VOLTAGE SUPERVISOR
SLVS220-JULY 1999
detailed description
sense voltage setting
The sense voltage, Vs, of the TL7700 is typically 500 mY. By applying two external resistors, the circuit designer can
obtain any sense voltage over 500 mY. In Figure 19, the sensing voltage, V's, is calculated as follows:
V's
=Vs x (R1 + R2)/R2
Where:
Vs = 500 mY, typically at TA = 25°C
At room temperature, Vs has a variation of 500 mV ±5 mY. In the basic circuit shown in Figure 19, variations of
[±5 x (R1 + R2)/R2] mV are superimposed on Vs.
'"'
I
RL
vee
R1
RESET
Vs
R2
'"'
SENSE
GND
1
~rr~
Figure 19.
~TEXAS
INSTRUMENTS
10-110
Vee
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
'"' GND
TL7700
SUPPLY-VOLTAGE SUPERVISOR
SLVS220-JULY 1999
sense voltage hysteresis setting
If the sense voltage, Vs, does not have hysteresis in it and the voltage on the sensing line contains ripples, the
resetting of TL7700 will be unstable. Hysteresis is added to the sense voltage to prevent such problems. As shown
in Figure 20, the hysteresis, Vhys, is added, and the value is determined as follows:
Vhys = Is x R1
Where:
Is
=2.5 j.LA, typically at TA =25°C
At room temperature, Is has variations of 2.5 ±0.5 j.LA, so in the circuit shown in Figure 19, Vhys has variations of
(±0.5 x R1) JlV. In circuit design, it is necessary to consider the voltage-dividing resistor tolerance and temperature
coefficient in addition to variations in Vs and Vhys'
vee Vhys
_i __ _
-f--
Vs
1.5V
~~----~---------+~---------4----~~--T
I
I
I
I
I tpo
I
I
I
I
I
I
I
tpo
~~---------L----~----~~----~----~~~T
Figure 20. Vee-RESET Timing Chart
output pulse duration setting
Constant-current charging starts on the timing capacitor when the sensing-line voltage reaches the TL7700's sense
voltage. When the capacitor voltage exceeds the threshold level ofthe output drive comparator, RESET changes from
a low to a high level. The output pulse duration is the time between the point when the sense-pin voltage exceeds
the threshold level and the point when the RESET output changes from a low level to a high level. When the TL7700
is used for system power-on reset, the output pulse duration, tpo , must be set longer than the power rise time. The
value of tpo is:
tpo
=Ct x 105 seconds
Where:
Ct is the timing capacitor in farads
=
There is a limit on the device response speed; even if Ct 0, tpo will not be 0, but approximately 5 to 10 Jls. Therefore,
when the TL7700 is used as a comparator with hysteresis, without connecting Ct , switching speeds (t,ltf' tpdtpd, etc.)
must be considered.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-:111
10-112
TL7702B, TLn05B
SUPPLY-VOLTAGE SUPERVISORS
TLnxxBC ••. 0 OR P PACKAGE
TL7705BM ••• JG PACKAGE
TL7705BQ •.• 0 PACKAGE
(TOP VIEW)
• Power-On Reset Generator
• Automatic Reset Generation After
Voltage Drop
• RESET Output Defined From Vee ;<: 1 V
REF[]8
RESIN 2
7
CT 3
6
GND 4
5
• Precision Voltage Sensor
• Temperature-Compensated Voltage
Reference
VCC
SENSE
RESET
RESET
TLn05BM ••• U PACKAGE
(TOP VIEW)
• True and Complement Reset Outputs
• Externally Adjustable Pulse Duration
NC
NC
REF
description
The TL7702B and TL7705B are integrated-circuit
supply-voltage supervisors designed for use as
reset controllers in microcomputer and
microprocessor systems. The supply-voltage
supervisor monitors the supply for undervoltage
conditions at the SENSE input. During power up,
the RESET output becomes active (low) when
VCC attains a value approaching 1 V. As VCC
approaches 3 V (assuming that SENSE is above
VT+), the delay timer function activates a time
delay, after which outputs RESET and RESET go
inactive (high and low, respectively). When an
undervoltage condition occurs during normal
operation, outputs RESET and RESET go active.
To ensure that a complete reset occurs, the reset
outputs remain active for a time delay after the
voltage at the SENSE input exceeds the
positive-going threshold value. The time delay is
determined by the value of the external capacitor
C.. td '" 2.6 x 104 x CT, where CT is in farads (F)
and ~ is in seconds (s).
9
8
VCC
SENSE
RESET
RESET
NC - No Internal connection
TLn05BM ••• FK PACKAGE
(TOP VIEW)
oza:z;::;:z
tb 0 80
NC
RESIN
NC
CT
NC
4
5
6
7
8
3 2 1 2019
18
17
16
15
14
9 10 11 12 13
NC
SENSE
NC
RESET
NC
NC - No internal connection
An external capacitor (typically 0.1 f.LF) must be
connected to REF to reduce the influence of fast
transients in the supply voltage.
The TL7702BC and TL7705BC are characterized for operation from O°C to 70°C. The TL7702BI and TL7705BI
are characterized for operation from -40°C to 85°C. The TL7705BQ is characterized for operation from -40°C
to 125°C. The TL7705BM is characterized for operation from -55°C to 125°C.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Copyright © 1999. Texas Instruments Incorporated
~=='1!!"n:"~'~I:"~~:='..r.:::
not _ I , Includellllr., 01 on poromators.
p_ng _
10-113
TLn02B, TLn05B
SUPPLY-VOLTAGE SUPERVISORS
SLVS037H - SEPTEMBER 1989 - REVISED JULY 1999
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
O°Clo 70°C
-40°C to 85°C
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(P)
CERAMIC
FLATPACK
(U)
TL7702BCD
-
-
TL7702BCP
-
TL7705BCD
TL7702BID
TL7705BID
-40°C 10 125°C
TL7705BQD
-55°C 10 125°C
-
TL7702BMFK
TLn02BMJG
TL7705BMFK
TL7705BMJG
TL7705BCP
TL7702BIP
-
TL7705BIP
-
-
CHIP FORM
(V)
TL7702BY,
TL7705BY
TL7702BMU
TL7705BMU
The D package Is available taped and reeled. Add Ihe suffix RIo device type (e.g., TL7702BCDR). Chip forms are lested al
25°C.
~TEXAS
1(H14
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
TL7702B, TL7705B
SUPPLY-VOLTAGE SUPERVISORS
SLVS037H - SEPTEMBER 1989 - REVISED JULY 1999
functional block diagram
The functional block diagram is shown for illustrative purposes only; the actual circuit includes a trimming
network to adjust the reference voltage and sense-comparator trip point.
8
Vee----------------~--------------~------------------------__.
~
=701lA
6
3
eT----------------~-----+--------~----------~~
SENSE
RESET
7
____-5- RESET
R1
(see Note A)
R2
(see Note A)
2
RESIN-----+----------4------+--------~
L -__________________
-+______________-+_____ REF
4
GND-----.----------~--------------------------~------------~
Pin numbers shown are for the 0, JG, and P packages.
NOTE A: TL7702B: R1 = 0 Q, R2 = open
TL7705B: R1 = 23 kQ, R2 = 10 kQ, nominal
typical timing diagram
Vee and
SENSE
C
Lk=
I
Vrr.
Vres
i7r
-yu
o I I
~
Vrr_ M II ;,..
U
I
I
RESETI :'-ld-+lHI ~
Output
Undefined
Vrr_
Vres
I I
_
I I
IlJ--
td1
Output
Undefined
o
~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
10-115
TLn02B.TLn05B
SUPPLY-VOLTAGE SUPERVISORS
SLVS037H - SEPTEMBER 1989 - REVISED JULY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vcc (see Note 1) ........................................................... 20 V
Input voltage range, VI: RESIN ..................................................... -0.3 V to 20 V
SENSE .................................................... -0.3 V to 20 V
High-level output current, IOH (RESET) .................................................... -30 rnA
Low-level output current, lodRESET) ...................................................... 30 rnA
Package thermal impedance, OJA (see Notes 2 and 3): D package ............................ 97°CIW
P package . . . . . . . . . . . . . . . . . . . . . . . . . . .. 127°CIW
Case temperature for 60 seconds, TC: FK package .......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG or U packages .............. 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P packages ................ 260°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under 'absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under 'recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. Maximum power dissipation is a function of TJ(max), OJA, and TA. The maximum allowable power disslpetion at any allowable
ambient temperature is Po (TJ(max) - TA)/OJA. Operating at the absolute maximum TJ of 1500 e can impact reliability.
3. The package thermal impedance is calculated In accordance with JESO 51, except for through-hole peckages, which use a trace
length of zero.
=
recommended operating conditions
Supply voltage, Vee
MIN
MAX
3.6
18
UNIT
V
High-level input voltage, VIH
RESIN
2
18
V
low-level input voltage, Vil
RESIN
0
0.8
V
Input voltage, VI
SENSE
0
18
High-level output current, IOH
RESET
lOW-level output current, IOl
RESET
Tl770xBe
Tl770xBI
Operating free-air temperature range, TA
Tl7705BQ
Tl7705BM
~TEXAS
10-116
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
V
-16
rnA
16
rnA
0
70
-40
-40
-55
125
85
125
°e
TL77028,TL77058
SUPPLY-VOLTAGE SUPERVISORS
SLVS037H - SEPTEMBER 1989 - REVISED JULY 1999
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TL77xxBC
TL77xxBI
TL7705BQ
TEST CONDlTlONSt
MIN
VOH
High-level output voltage, RESET
IOH=-16mA
VOL
Low-level output voltage, RESET
IOL= 16 mA
Vref
Reference voltage
Iref = 500 !lA,
TL7702B
VIT-
Negative-going
Input threshold voltage
at SENSE input
TL7705B
Vhys
VreS§
Power-up reset voltage
II
Input current
TL7702B
TL7705B
I RESIN
I SENSE
V
TA = 25°C
TA=25°e
TA = full range;
VCC=3.6Vt018V,
TA=25°C
IOL at RESET = 2 mA,
TA=25°e
0.4
V
V
2.48
2.53
2.58
2.505
2.53
2.555
4.5
4.55
4.6
2.48
2.53
2.58
4.45
4.55
4.65
10
1
-10
-0.1
VI =Vrefto 18V
V
mV
30
VI = 0.4 Vto Vec
TL7702B
UNIT
MAX
VCC-1.5
TL7702B
TL7705B
Hysteresis, SENSE
(VITrVIT-)
TYP
-2
V
!lA
IOH
High-level output current, RESET
VO=18V,
See Figure 1
50
IOL
LOW-level output current, RESET
VO=OV,
See Figure 1
-50
!lA
!lA
Supply current
3
mA
ICC
3.5
mA
. .
t
~2
VSENSE = 15 V,
RESIN
VCC=18V,
TA = full range;
V
1.8
All electrical characteristics are measured With 0.1-jLF capacitors connected at REF, CT, and Vee to GND.
; Full range is ooe to 70°C for the e-suffix devices, -400 e to 85°C for the I-suffix devices, and -400 e to 125°C for the Q-suffix device.
§ This is the lowest voltage at which RESET becomes active.
switching characteristics, Vee =5 V, CT open, TA =25°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
TL77xxBC
TL77xxBI
TL7705BQ
MIN
Propagation delay time from
low- to high-level output
RESIN
tPHL
Propagation delay time from
high- to low-level output
RESIN
tw
Effective pulse duration
tPLH
tr
Rise time
tf
Fall time
tr
Rise time
tf
Fall time
RESET
UNIT
TYP
MAX
270
500
ns
270
500
ns
See Figures 1, 2, and 3
RESET
RESIN
See Figure 2
SENSE
150
ns
100
75
RESET
See Figures 1 and 3
RESET
150
200
75
150
50
ns
ns
~TEXAS
INSTRUMENTS
POST OFFICE sox 655303 • DALLAS. TEXAS 75265
10-117
TL7702B,TL7705B
SUPPLY-VOLTAGE SUPERVISORS
SLVS037H - SEPTEMBER 1989 - REVISED JULY 1998
electrical characteristics over recommended operating conditions (unless otherwise noted)
TLnosBM
PARAMETER
TEST CONDITIONSt
VOH
High-level output voltage, RESET
IOH=-16mA
VOL
Low-level output voltage, RESET
IOL=16mA
Vref
Reference voltage
Iref = 500 !lA,
TL77028
VIT-
Negative-going
input threshold voltage
at SENSE input
TL77058
Vhys
Vres
*
TL77028
TL77058
Power-up reset voltage
II
Input current
LRESIN
I SENSE
TA=25°e
TA = 25°C
TA = -55°e to 125°C
Vee=3.6VtoI8V,
TA = 25°C
10L at RESET = 2 mA,
TA = 25°C
10H
High-level output current, RESET
VO=18V
10L
loW-level output current, RESET
VO=O
ICC
Supply current
0.4
V
V
2.48
2.53
2.58
2.505
2.53
2.555
4.5
4.55
4.8
2.48
2.53
2.58
4.45
4.55
4.85
10
1
-10
-0.1
-2
50
-50
VSENSE = 15 V,
RESIN:a:2V
Vee = 18V,
TA= -55°eto
125°C
1.8
V
mV
30
VI =VreftoVee-l.5 V
UNIT
V
VI =0.4 VtoVee
TL77028
UNIT
MAX
Vee-1.5
TL77028
TL77058
HysteresiS, SENSE
(VIT+ - VIT-)
TYP
MIN
V
!lA
!lA
!lA
3
mA
4
*
tAli electncal characteristiCS are measured with O.I-IIF capacitOrs connected at REF, eT, and Vee to GND.
This Is the lowest value at which RESET becomes active.
'
switching characteristics, Vee = 5 V, CTopen, TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
Propagation delay time from
low- to high-level output
RESIN
RESET
tpHL
Propagation delay time from
hlgh- to lOW-level output,
RESIN
tw
Effective pulse duration
PARAMETER
tpLH
tr
Rise time
tf
Fall time
tr
Rise time
tf
Fall time
TEST CONDITIONS
UNIT
TYP
MAX
270
500'
ns
270
500"
ns
See Figures 1, 2, and 3
RESET
RESIN
See Figure 2
SENSE
150
ns
100
75"
RESET
See Figures 1 and 3
RESET
• On products compliant to MIL-PRF-36535, these parameters are not production tested.
~TEXAS
INSTRUMENTS
10-118
TL7705BM
MIN
POST OFFICE SOX 655303 • DALLAS,' TEXAS 75265
150
200'
75
150"
50"
ns
ns
TL7702B,TL7705B
SUPPLY-VOLTAGE SUPERVISORS
SLVS037H - SEPTEMBER 1989 - REVISED JULY 1999
electrical characteristics over recommended operating conditions, TA = 25°C (unless otherwise
noted)
PARAMETER
TL7702BY
TL7705BY
TEST CONDITIONSt
TYP
MIN
VOH
High-level output voltage, RESET
IOH=-16mA
VOL
Low-level output voltage, RESET
IOL=16mA
Reference voltage
VIT-
Negative-going input threshold voltage
at SENSE input
Vhys
Hysteresis, SENSE (VIT+ - VIT-)
Vres:l:
Power-up reset voltage
V
VCC-1.5
Iref = 500 I1A
Vref
UNIT
MAX
0.4
V
V
2.48
2.53
2.58
TL7702BY
2.505
2.53
2.555
TL7705BY
4.5
4.55
4.6
TL7702BY
TL7705BY
10
VCC=3.6Vt018V
mV
30
1
IOL at RESET = 2 mA
I RESIN
-10
VI = 0.4 V to VCC
V
V
I1A
II
Input current
IOH
High-level output current, RESET
VO=18V,
See Figure 1
50
IOL
Low-level output current, RESET
VO=OV,
See Figure 1
-50
I1A
I1A
ICC
Supply current
VSENSE = 15 V,
RESIN
3
rnA
I SENSE
TL7702BY
- 450 Q
Using a 20% tolerance resistor, RT should be greater than 560
n.
Adding this series resistor changes the duration of the reset pulse by no more than 10%. RT extends the discharge
of CT, but also skews the V(Cn threshold. These effects tend to cancel one another. The precise percentage change
can be derived theoretically, but the equation is complicated by this interaction and is dependent upon the duration
of the supply-voltage fault condition.
Both outputs of the TL770xB should be terminated with similar value resistors, even when only one is being used.
This prevents unwanted plateauing in either output waveform during switching, which may be interpreted as an
undefined state or delay system reset.
10-122
:II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL7757
SUPPLY-VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041E-SEPTEMBER 1991- REVISED JULY 1999
o PACKAGE
u
(TOP VIEW)
• Power-On Reset Generator
• Automatic Reset Generation After Voltage
Drop
RESET
VCC
• Low Standby Current ••. 20 ~
• Reset Output Defined When Vee
Exceeds 1 V
• Complementary Reset Output
• True and Complementary Reset Outputs
• Precision Threshold Voltage
4.55 V ±120 mV
NC
GND
8
2
7
3
6
4
5
NC
NC
NC
NC
NC-No Internal connection
LPPACKAGE
(TOP VIEW)
GJ
• High Output Sink Capability •.. 20 mA
• Comparator Hysteresis Prevents Erratic
Resets
'1
o
o
GND
Vcc
RESET
description
PKPACKAGE
(TOP VIEW)
The TL7757 is a supply-voltage supervisor
designed for use in microcomputer and
microprocessor systems. The supervisor
monitors the supply voltage for undervoltage
conditions. During power up, when the supply
voltage, VCC, attains a value approaching 1 V, the
RESET output becomes active (low) to prevent
undefined operation. If the supply voltage drops
below threshold voltage level (VIT-), the RESET
output goes to the active (low) level until the
supply undervoltage fault condition is eliminated.
VCC
GND RESET
GND is in electrical contact with the tab.
The TL7757C is characterized for operation from
O°C to 70°C. The TL7757 I is characterized for
operation from -40°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP FORM
(V)
TA
SMALL OUTLINE
(D)
TQ-226AA
(LP)
SOT-89
(PK)
O°C to 70°C
TL7757CD
TL7757CLP
TL7757CPK
-40°C to 85°C
TL7757ID
TL7757ILP
TL7757IPK
TL7757Y
D and LP packages are available taped and reeled. Add the suffix R to device type (e.g.,
TL7757CDR). Chip forms are tested at 25°C.
~TEXAS
Copyright ~ 1999, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-123
ii..7757
SUPPLY-VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041 E - SEPTEMBER 1991 - REVISED JULY 1999
equivalent schematic
R1
GND
ACTUAL DEVICE
COMPONENT COUNT
Transistors
. Resistors
Capacitors
27
20
2
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................. -0.3 V to 20 V
Offstate output voltage range (see Note 1) ........................................... -0.3 V to 20 V
Output current, 10 ........................................................................ 30 mA
Package thermal impedance, 9JA (see Notes 2 and 3): D package ............................ 97°CIW
LP package ......................... 156°CIW
PK package ........................... 52°CIW
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds •.............................. 260°C
Storage temperature range, TSlg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network terminal ground.
2. Maximum power dissipation is a function of TJ(max), 8JA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) - TAl/8JA. Operating al the absolute maximum TJ of 150°C can impact reliability.
3. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
~lExAs
10-124
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL7757
SUPPLY-VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041E-SEPTEMBER 1991-REVISEDJULY1999
recommended operating conditions
MIN
MAX
1
7
Supply voltage, VCC
UNIT
V
High-level output voltage, VOH
15
V
low-level output current, IOl
20
mA
I Tl7757C
Operating free-air temperature, TA
I Tl77571
0
70
-40
85
°c
electrical characteristics at specified free-air temperature
PARAMETER
TL7757C
TEST CONDITIONS
VIT-
Negative-going input threshold voltage at VCC
Vhyst
Hysteresis at VCC
VOL
low-level output voltage
IOl=20mA,
VCC=4.3V
IOH
High-level output current
VCC=7V,
See Figure 1
VOH=15V,
vres:l=
Power-up reset voltage
Rl = 2.21<0,
VCC slew rate S 5 V/tJ13
ICC
Supply current
TA
MIN
TYP
MAX
"25°C
4.43
4.55
4.67
O°C to 70°C
4.4
25°C
40
O°C to 70°C
30
50
60
0.8
V
0.8
25°C
1
O°C to 70°C
1
0.8
25°C
IIA
1
V
1.2
O°C to 70°C
1400
25°C
VCC=5.5V
mV
70
O°C to 70°C
VCC=4.3V
V
4.7
0.4
25°C
UNIT
2000
O°C to 70°C
2000
O°C to 70°C
40
IIA
t This is the difference between positive-going inputthreshold voltage, VIT+, and negative-going input threshold voltage, VIT _.
:1= This is the lowest voltage at which RESET becomes active.
switching characteristics at specified free-air temperature
PARAMETER
Tl7757C
TEST CONDITIONS
TA
O°C to 70°C
tplH
Propagation delay time, low-to-high-Ievel
output
VCC slew rate S 5 V/tJ13,
See Figures 2 and 3
tpHL
Propagation delay time, high-to-Iow-Ievel
output
See Figures 2 and 3
tr
Rise time
VCC slew rate S 5 V/tJ13,
See Figures 2 and 3
tf
Fall time
See Figures 2 and 3
tw(min)
Minimum pulse duration at VCC for output
response
25°C
25°C
MIN
TYP
MAX
3.4
5
5
2
25°C
0.4
25°C
0.05
tJ13
1
1
O°C to 70°C
tJ13
5
5
O°C to 70°C
UNIT
tJ13
1
0°Cto70°C
1
25°C
5
O°C to 70°C
5
tJ13
tJ13
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-125
TL7757
SUPPLY·VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041 E- SEPTEMBER 1991 - REVISED JULY 1999
electrical characteristics at specified free-air temperature
PARAMETER
TL77571
TEST CONDITIONS
VIT-
Negative-going input threshold voltage at Vee
Vhyst
Hysteresis at Vee
VOL
Low-level output voltage
IOL= 20 mA,
Vee=4.3V
IOH
High-level output current
Vee=7V,
See Figure 1
VOH=15V,
Vres:t:
Power-up reset voltage
RL = 2.2kn,
Vee slew rete:;; 5 VIlIS
ICC
Supply current
Vee=4.3V
Vee=5.5V
..
TA
MIN
TYP
MAX
25°C
4.43
4.55
4.67
-40oe to 85°C
4.4
25°C
40
-4Q°e to 85°C
30
25°C
4.7
50
60
70
0.4
0.8
-4Q°e to 85°C
0.8
25°C
1
-4Q°e to 85°C
1
1
0.8
25°C
1.2
-40oe to 85°C
25°C
1400
UNIT
V
mV
V
IlA
V
2000
-40oe to 85°C
2100
-40oe to 85°C
40
IlA
t This IS the difference between pOSitive-going Input threshold voltage, VIT+, and negative-going Input threshold voltage, VIT-.
:t: This is the lowest voltage at which RESET becomes active.
switching characteristics at specified free-air temperature
PARAMETER
TL77571
TEST CONDITIONS
TA
-40oe to 85°C
tpLH
Propagation delay time, low-to-high-Ievel output
Vee slew rete:;; 5 VIlIS,
See Figures 2 and 3
tPHL
Propagation delay time, high-to-Iow-Ievel output
See Figures 2 and 3
tr
Rise time
Vee slew rete:;; 5 VIlIS,
See Rgures 2 and 3
tf
Fall time
See Figures 2 and 3
tw(min)
Minimum pulse duration at Vee for output
response
25°C
25°C
TYP
MAX
3.4
5
5
2
-40oe to 85°C
25°C
0.4
25°C
1
25°C
5
-40oe to 85°C
5
POST OFFICE SOX 655303 • DALLAS, TEXAS 75265
lIS
lIS
1
-40oe to 85°C
~TEXAS
lIS
1
1
0.05
UNIT
5
5
-40oe to 85°C
INSTRUMENTS
10-126
MIN
lIS
lIS
TL7757
SUPPLY-VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041E- SEPTEMBER 1991 - REVISED JULY 1999
electrical characteristics at TA = 25°C
TEST CONDITIONS
PARAMETER
VIT-
Negative-going input threshold vo~age at Vee
Vhyst
Hysteresis at Vee
TYP
MAX
4.55
IOL=20mA.
Vee=4.3V
High-level output current
Vee=7V.
VOH=15V.
Vres:j:
Power-up reset voltage
RL = 2.2 k.Q.
Vee slew rate,;; 5 V/iJS
V
IIA
See Figure 1
0.8
V
1400
Vee=4.3V
Supply current
mV
0.4
Low-level output voltage
IOH
UNIT
V
50
VOL
ICC
TLn57Y
MIN
IIA
Vee=5.5V
t This is the difference between positive-going Input threshold voltage. VIT+. and negatlve-golng Input threshold voltage. VIT _.
:j: This is the lowest voltage at which RESET becomes active.
switching characteristics at TA
=25°C
TEST CONDITIONS
PARAMETER
tpLH
Propagation delay time. low-to-high-Ievel output
Vee slew rete,;; 5 VliJS.
See Figures 2 and 3
tpHL
Propagation delay time. high-to-Iow-Ievel output
See Figures 2 and 3
tr
Rise time
Vee slew rete s 5 V/iJS.
See Figures 2 and 3
tf
Fall time
See Figures 2 and 3
TLn57Y
MIN
TYP
MAX
UNIT
3.4
iJS
2
iJS
0.4
iJS
0.05
iJS
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-127
TL7757
SUPPLY-VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041E - SEPTEMBER 1991 - REVISED JULY 1999
PARAMETER MEASUREMENT INFORMATION
+
5.5 V
GND
Figure 1. Test Circuit for Output Leakage Current
Vee
TLn57
Pulse
Generator
It
RESET
0.1 "F
OUT
eL=100pF
(see Note A)
NOTE A: Includes jig and probe capacitance.
Figure 2. Test Circuit for RESET Output Switching Characteristics
Vee
(see Note A)
4.3V
VI!'~~ VIT_
-L
~
I
I
tPLH ~ ~ ~
14--
tPHL
II
RESET
~
~
I
I
50%
10
I I
tr ----.I 14-NOTE A:
10%
I I
----.I
14-- tf
Vee slew rate S 5118
Figure 3. Switching Diagram
~TEXAS
10-128
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL7757
SUPPLY-VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041 E - SEPTEMBER 1991 - REVISED JULY 1999
TYPICAL CHARACTERISTICSt
Table of Graphs
FIGURE
Vee
Supply voltage vs RESET output voltage
4
ICC
Supply current vs Supply voltage
5
ICC
Supply current vs Free-air temperature
6
Val
low-level output voltage vs low-level output
current
7
Val
low-level output voltage vs Free-air temperature
8
IOl
Output current vs Supply voltage
9
VIT-
Input threshold voltage (negatlve-going Vee) vs Free-air
temperature
10
Vres
Power-up reset voltage vs Free-air temperature
11
Vres
Power-up reset voltage and supply voltage vs lime
12
Propagation delay time
13
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
vs
RESET OUTPUT VOLTAGE
8
2
I
TA=25°e
7 I- 10 =0
>
6
I
CD
I
5
~
4
~
~
CL
CL
"
til
I
V
V
ct
E
1.5
I
C
~
V
">-
V
"ii
CL
"I
3
til
2
~
Vi
o
o
2
3
4
5
6
7
0.5
o
o
2
3
4
5
6
7
Vee - Supply Voltage - V
RESET Output Voltage - V
Figure 5
Figure 4
t
V
./
(J
(J
(J
>
I
TA=25°e
10=0
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-129
TL7757
SUPPLY-VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041E-SEPTEMBER 1991- REVISED JULY 1999
TYPICAL CHARACTERISTICSt
SUPPLY CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
1.52
1.48
V
1.4
./
I
GI
I
./
::
0.040
I
0.036
~
0.032
0.028
~
"5
a.
:
-"-
TA=25°C
/
> 100
E
./
1.36
1.32
_
110
./
VCC= 4.3 V
1.44
J
120
.......- f - -
RL=O
1.28
LOW-LEVEL OUTPUT CURRENT
//
90
VCC= 1 V
80
70
"5
60
~
50
~
ff
0
"- ............
-...... """'-
0.024
0.020
-75 -50 -25
~=7V
I...........
~V
0
25
50
r-...
~
I
--
....I
~
-r-
75
100
40
20
/
10 ,
~
4
8
12
16
IOL - Low-Level Output Current - mA
OUTPUT CURRENT
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
E
100
I
0.02
.
TA=25°C
.I
'.
IOL=20mA
......
-
0.016
c
~
"5
a.
80
0
60
"5
§
;i:
E
~
0.01
!
0.008
I
0.006
0
40
9
20
0.004
0.002
IOL=1 mA
o
o
-100
0.012
:::I
""5
IOL=8mA
I
....I
0.014
I
.9
~
I
0.018
GI
CI
~
-50
o
50
100
150
0.75
TA - Free-Air Temperature - °C
FigureS
lJ
0.8
0.85
0.9
0.95
VCC - Supply Voltage - V
Figure 9
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
~TEXAS
10-130
20
Figure 7
LOW-LEVEL OUTPUT VOLTAGE
>
_
VCC = 4.3 V
~
Figure 6
VCC =4.3 V
V
./
30
TA - Free-Air Temperature - °C
120
/'
~V
o
o
125
/
//
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1.05
TL7757
SUPPLY-VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041E - SEPTEMBER 1991 - REVISED JULY 1999
TYPICAL CHARACTERISTICSt
INPUT THRESHOLD VOLTAGE
(NEGATIVE·GOING Vee>
POWER·UP RESET VOLTAGE
vs
vs
FREE·AIR TEMPERATURE
FREE·AIR TEMPERATURE
1000
4.6
_I
RL=2.2kn
RL=O
,
4.59
>
I
t
{l
4.56
~
4.55
I
.L
">
,
950
E
I
4.57
~
i
.5
>
4.58
-t---...
4.53
900
{l
850
'"
'cD
------
4.54
CD
'"
CD
II:
a..
BOO
;:)
.:.
!
750
I
700
r'\.
"'""
a..
'"
>
4.52
I!!
4.51
4.5
-100
~
650
600
-50
o
50
100
TA - Free-Air Temperature - °e
150
-100
o
-50
100
50
150
TA - Free-Air Temperature - °e
Figure 10
Figure 11
POWER·UP RESET VOLTAGE
AND SUPPLY VOLTAGE
vs
PROPAGATION DELAY TIME
TIME
>
2
6
~
I
TA=25°e
RL = 2.2 kn
t
{l
/
.5
~
{l
Ii8
J
4
i
t
o
Vee
5
1.5
J.
I
TA=25°e
RL= 2.2 kn
~
1.
Vee
RESET
I
\
RE~ET
-0.5
,
o
>
Oi
.J
-1
-1
o
0.5
1.5
2
2.5
3
o
2
4
6
8
10
12
14
16
18
1- Time -l1s
I-Time - lUI
Figure 12
Figure 13
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-131
TL7757
SUPPLY-VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041 E - SEPTEMBER 1991 - REVISED JULY 1999
APPLICATION INFORMATION
TYPICAL TIMING DIAGRAM
TYPICAL APPLICATION DIAGRAM
5 V -+------+----.,
1 kn
RESET
TL7757
GND
O~
__
~
_______
~~L-
~TEXAS
INSTRUMENTS
10-132
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1--_._-
System
Reset
TL7759
SUPPLY·VOLTAGE SUPERVISORS
• Power-On Reset Generator
• Automatic Reset Generation After Voltage
Drop
D, P, OR PW PACKAGE
(TOP VIEW)
• Precision Input Threshold
Voltage ••• 4.55 V ±120 mV
NC
NC
2
3
7
6
RESET
RESET
NC
GND
4
5
VCC
NcDa
• Low Standby Current ... 20 !LA
• Reset Outputs Defined When Vee
Exceeds 1 V
NC - No internal connection
• True and Complementary Reset Outputs
• Wide Supply-Voltage Range ... 1 V to 7 V
description
The TL7759 is a supply-voltage supervisor designed for use as a reset controller in microcomputer and
microprocessor systems. The supervisor monitors the supply voltage for undervoltage conditions. During power
up, when the supply voltage, VCC, attains a value approaching 1 V, the RESET and RESET outputs become
active (high and low, respectively) to prevent undefined operation. If the supply voltage drops below the input
threshold voltage level (VIT_ ), the reset outputs go to the reset active state until the supply voltage has returned
to its nominal value (see timing diagram).
The TL7759C is characterized for operation from O°C to 70 oe.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
O°C to 70°C
SMALL
OUTLINE
(D)
PLASTIC
DIP
(P)
SHRINK
SMALL
OUTLINE
(PW)
CHIP
FORM
TL7759CD
TL7759CP
TL7759CPW
TL7759Y
(V)
The D and PW packages are available taped and reeled. Add the suffix R to
the device type (e.g., TL7759CDR). Chip forms are tested at 25°C.
functional block diagram
--=-5 VCC
. - - - - - - - I t - - - - - -.....
RESET
RESET
~_~_ _~----~~~4
GND
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
10-133
TL7759
SUPPLY-VOLTAGE SUPERVISORS
SLVS042D-JANUARY 1991- REVISED JULY 1999
absolute maximum ratings over operating free-air temperature range {unless otherwise noted)t
Supply voltage, Vee (see Note 1) ........................................................... 20 V
Off-state output voltage range: RESET voltage ....................................... -0.3 V to 20 V
RESET voltage ....................................... -0.3 V to 20 V
Low-level output current, IOL (RESEn ...................................................... 30 mA
High-level output current, IOH (RESET) .................................................... -10 mA
Package thermal impedance, eJA (see Notes 2 and 3): D package ............................ 97°CIW
P package .......................... 127°CIW
PW package ........................ 149°CIW
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ........................... . . .. 260°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t
Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. Maximum power dissipation is a function of TJ(max), 6JA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is Po = (TJ(max) - TA)16JA. Operating at the absolute maximum TJ of 150°C can Impact reliability.
3. The package thermal impedance Is calculated in accordance with JESO 51 , except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
Supply voltage, Vee
MIN
MAX
1
7
V
15
Transistor off RESET voltage
Output voltage, Vo (see Note 4)
UNIT
Transistor off RESET voltage
V
0
Low-level output current, IOL
RESET
24
mA
High-level output current, IOH
RESET
-a
mA
Operating free-air temperature, TA
TL775ge
70
°e
0
NOTE 4: RESET output must not be pulled down below GNO potential.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TL7759C
TEST CONDITIONS
PARAMETER
IRESET
VOL
Low-level output voltage
VOH
High-level output voltage
TA = 25°C
VIT-
Input threshold voltage
(negative-going Vee)
Vres§
Power-up reset voltage
RL = 2.2 k.Q
V hysll
Hysteresis at Vee input
IOH
High-level output current
IOL
Low-level output current
ICC
Supply current
I RESET
Vee=4.3V
IOL=24mA
IOH=-amA
MAX
0.4
0.8
4.55
4.67
4.7
0.8
TA=25°e
1
TA = ooe to 70°C
1.2
40
TA = ooe to 70°C
30
60
50
70
1
VOH=15V
-1
VOL=OV
No load
Vee=4.3V
1400
2000
Vee=5.5V
:j: Typical values are at TA = 25°C.
§ This is the lowest voltage at which RESET becomes active, Vee slew rate:s; 5 V/IJ$.
11 This is the difference between positive-going input threshold voltage, VIT+, and negative-going input threshold voltage, VIT-
~TEXAS
INSTRUMENTS
10-134
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
V
V
4.4
TA=25°e
Vee = 7 V, See Figure 1
TYP*
Vee-1
4.43
TA = ooe to 70°C
I RESET
I RESET
MIN
40
V
V
mV
IJA
IJA
IJA
TL7759
SUPPLY-VOLTAGE SUPERVISORS
SLVS042D-JANUARY 1991 - REVISED JULY 1999
electrical characteristics, TA = 25°C (unless otherwise noted)
TL7759Y
PARAMETER
TEST CONDITIONS
IRESET
VOL
Low-level output voltage
VIT-
Input threshold voltage (negative-going Vee)
Vrest
Power-up reset voltage
Vhvs:l:
Hysteresis at Vee input
ICC
Supply current
. .
Vee =4.3 V,
MIN
IOL=24mA
RL=2.2kn
No load
Vee=4.3V,
TVP
MAX
UNIT
0.4
V
4.55
V
0.8
V
50
mV
1400
~
tThls IS the lowest voltage at which RESET becomes active, Vee slew rate::; 5 V/IlS .
:I: This is the difference between positive-going input threshold voltage, VIT+, and negative-going input threshold voltage, VIT-.
timing diagram
VCC
Output Undefined
for VCC Less Than 1 V
Output Undefined
switching characteristics at TA = 25°C (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
TL7759C
MIN
MAX
UNIT
tPLH
Propagation delay time, low-to high-level output
Vee
RESET
See Figures 2 and 3§
5
IlS
tpHL
Propagation delay time, high-to low-level output
Vee
RESET
See Figures 2 and 4
5
IlS
tr
Rise time
RESET
See Figures 2 and 4§
1
IlS
tf
Fall time
RESET
See Figures 2 and 4
1
IlS
tw(min)
Minimum pulse duration
RESET
See Figures 2 and 4
Vee
5
IlS
§ Vee slew rate::; 5 V/1lS
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-135
TL7759
SUPPLY-VOLTAGE SUPERVISORS
SLVS042D - JANUARY 1991 - REVISED JULY 1999
PARAMETER MEASUREMENT INFORMATION
15 V
RESETI----'
+
7V
TL7759
Figure 1. Test Circuit for Output Leakage Current
Vcc
4.8V
(see Note A)
4.3 V
I
---4.
tPLH
~
I
r-
r-
1-.- . . , . . -
-+I
tPHL
90·,140----: 90%
50% I
10% I
tr-+J
~
I 50%
I 0%
-.:
I+- tf
NOTE A. VCC slew rateS 5 V/IJS.
Figure 2. Switching Diagram
Vcc
Pulse
Generator
TL7759
RESET 1-.-_ _ _...._ _
0.1 ILF
GND
t
CL=100pF't
CL Includes jig and probe capacitance.
Figure 3. Test Circuit for RESET Output Switching Characteristics
Pulse
Generator
0.1 ILF
CL= 100 pFt
t
CL Includes jig and probe capacitance.
Figure 4. Test Circuit for RESET Output Switching Characteristics
~TEXAS
10-136
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL7759
SUPPLY-VOLTAGE SUPERVISORS
SLVS042D - JANUARY 1991 - REVISED JULY 1999
APPLICATION INFORMATION
5V-..-----,
a.1 I1F
T
RESET 1---'-7--110--- System Reset
TL7759
RESET
8
1kn
GND
4._-----'
Figure 5. Power-Supply System Reset Generation
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
10-137
10--138
TLn70-S, TL7770-12
DUAL POWER-SUPPLY SUPERVISORS
9F-OCTOBER 1987-REVISEDJULY 1999
DW OR N PACKAGE
• Power-On Reset Generator
• Automatic Reset Generation After Voltage
Drop
(TOP VIEW)
1RESIN
1CT
1RESET
1RESET
• RESET Defined When Vee Exceeds 1 V
• Wide Supply-Voltage Range ••• 3.5 V
to 18 V
• Precision Overvoltage and Undervoltage
Sensing
• 250-mA Peak Output Current for Driving
SCRGates
1SCR DRIVE
GND
3
4
Vee
2RESIN
2CT
2RESET
2RESET
2VSU
2VSO
2SCRDRIVE
• 2-mA Active-Low SCR Gate Drive for
False-Trigger Protection
• Temperature-Compensated Voltage
Reference
• True and Complementary Reset Outputs
• Externally Adjustable Output Pulse
Duration
description
The TL7770 is an integrated-circuit system supervisor designed for use as a reset controller in microcomputer
and microprocessor power-supply systems. This device contains two independent supply-voltage supervisors
that monitor the supplies for overvoltage and undervoltage conditions at the VSO and VSU terminals,
respectively. When VCC attains the minimum voltage of 1 V during power up, the RESET output becomes active
(low). As VCC approaches 3.5 V, the time-delay function activates, latching RESET and RESET active (high and
low, respectively) for a time delay (td) after system voltages have achieved normal levels. Above VCC 3.5 V,
taking RESIN low activates the time-delay function during normal system-voltage levels. To ensure that the
microcomputer system has reset, the outputs remain active until the voltage at VSU exceeds the threshold
value, VIT+, for a time delay, which is determined by an external timing capacitor such that:
=
td = 20 x 103
X
capacitance
where td is in seconds and capacitance is in farads.
The overvoltage-detection circuit is programmable for a wide range of designs. During an overvoltage condition,
an internal silicon-controlled rectifier (SCR) is triggered, providing 250-mA peak instantaneous current and
25-mA continuous current to the SCR gate drive terminal, which can drive an external high-current SCR gate
or an overvoltage-warning circuit.
The TL7770C series is characterized for operation from O°C to 70°C. The TL77701 series is characterized for
operation from -40°C to 85°C.
~TEXAS
Copyright © 1999. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75285
10-139
TL7770-5, TL7770-12
DUAL POWER-SUPPLY SUPERVISORS
SLVS019F - OCTOBER 1987 - REVISED JULY 1999
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE
(DW)
PLASTIC DIP
(N)
O°C to 70°C
TL7770-SCDW
TL7770-12CDW
TL7770-SCN
TL7770-12CN
-40°C to 8SoC
TL7770-SIDW
TL7770-SIN
CHIP FORM
(Y)
TL7770-SY
TL7770-12Y
-
DW package is available taped and reeled. Add the suffix R to the device type
(e.g., TL7770-SCDWR). Chip forms are tested at 2SoC.
functional block diagram (each channel)
vcc--------------------~~----------------------~----.
~ 65 !LA (TYP)
CT-----+-+-------+----~.---------~~
RESET
RESET
VSU
R1
R2
RESIN----~--------------~
VSO--------------------------------~
1 VSU
DEVICE
TL7770-S
TL7770-12
2VSU
'--4....-.....- - - - - SCR DRIVE
R1t
R2t
R1
R2
24 kn
70 kn
10kn
10 kf.I
Short
Short
Open
Open
2mA
(TYP)
t The values listed are nominal.
-=-
~TEXAS
INSTRUMENTS
10-140
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL7770-5, TL7770-12
DUAL POWER-SUPPLY SUPERVISORS
SLVS019F - OCTOBER 1987 - REVISED JULY 1999
timing requirements
1
VSU
1
I
--~----~-------I-td
I..
1
1
1
~I
I
I..-------.i-I
1
1
1
td
:
1
iI
""'--..11-+-----I
~ td
I
Vee
= 1 V (TYP)
1
1-_ _ VOH
1
1 _...._ _ _ _ VOL
_ _ L..._
I
I
~
Undefined Operation
for Vee Less Than 1 V
VT-------------
-----1
VSO
1
1
1
1
t
seRDRIVE
VOH
VOL
absolute maximum ratings over operating free-air temperature range (unless otherwise noted}t
Supply voltage, vee (see Note 1) ........................................................... 20 V
Input voltage range, VI: 1VSU, 2VSU, 1VSO, and 2VSO (see Note 1) .................... -0.3 V to 18 V
Low-level output current (1 RESET and 2RESET), IOL ........................................ 20 mA
High-level output current (1 RESET and 2RESET), IOH ....................................... -20 mA
Package thermal impedance, 9JA (see Notes 2 and 3): OW package. . . . . . . . . . . . . . . . . . . . . . . . . .. 57°C/W
N package ............................ 88°C/W
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds: OW or N package ................. 260°C
Storage temperature range, Tstg .................................................. --65°C to 150°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. Maximum power dissipation is a function of T J(max), 9JA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) - TA)/9JA. Operating at the absolute maximum T J of 150°C can impact reliability.
3. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-141
TL7770~5, TL7770~12
DUAL POWER-SUPPLY SUPERVISORS
SLVS019F - OCTOBER 1987 - REVISED JULY 1999
recommended operating conditions
Supply voltage, VCC
Input voltage range, VI (see Note 4)
I1VSU, 2VSU, 2VSO, lVSO
MIN
MAX
3.5
18
V
0
18
V
5
V
V
Output voltage, Vo (lCT, 2CT)
UNIT
High-level input voltage range, VIH (1 RESIN, 2RESIN)
2
18
Low-level input voltage range, VIL (1 RESIN, 2RESIN)
0
0.8
V
50
I1A
Output sink current, 10 (1 CT, 2CT)
-16
rnA
Low-level output current, 10L (1 RESET, 2RESET)
16
rnA
Continuous output current, 10 (lSCR DRIVE, 2SCR DRIVE)
25
rnA
liming capacitor, CT
10
High-level output current, 10H (1 RESET, 2RESET)
I TL7770C series
Operating free-air temperature, TA
I TL77701 series
..
0
70
IJ.F
°C
-40
85
°C
NOTE 4: The algebraic convention, in which the least positive (most negative) value IS designated minimUm, IS used In thiS data sheet for logic
voltage levels only.
~TEXAS
INSTRUMENTS
10-142
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL7nO-S, TL7770-12
DUAL POWER-SUPPLY SUPERVISORS
SLVS019F - OCTOBER 1987 - REVISED JULY 1999
electrical characteristics over recommended operating conditions (unless otherwise noted)
supply supervisor section
TEST
CONDITIONSt
PARAMETER
TLmo-SC
TL7770-12C
TL7770-SI
MIN
VOH
High-level output voltage
VOL
Low-level output voltage
RESET
IOH=-15mA
Vee-loS
seRDRIVE
IOH =-20 mA
Vee-loS
RESET
IOL= 1SmA
TL7770-S (S-V sense, 1VSU)
VIT-
Vhys
VT
Undervoltage input threshold
at VSU (negative-going)
TL7770-12 (12-V sense, 1VSU)
TA = MIN to MAX
TL777O-S, TL7770-12
(programmable sense, 2VSU)
TYpt
MAX
V
0.4
4.46
4.64
10.68
11.12
1.47
1.S3
TL7770-S (S-V sense, 1VSU)
1S
Hysteresis at VSU
(VIT+ - VIT-)
TL7770-12 (12-V sense, 1VSU)
36
Overvoltage threshold at VSO
TL7770-S, TL7770-12 (VSO)
TA = MIN to MAX
RESIN
VI = 5.5 V or 0.4 V
VSO
VI =2.4 V
TA = MIN to MAX
TL7770-5, TL7770-12
(programmable sense, 2VSU)
V
V
mV
S
II
Input current
IOH
High-level output current
RESET
VO=18V
IOL
Low-level output current
RESET
VO=O
IOH
Peak output current
SeRDRIVE
Duration = 1 ms
..
UNIT
2.68
2.48
-10
O.S
2
SO
-SO
2S0
V
!LA
itA
itA
mA
..
t For conditions shown as MIN or MAX, use the appropriate value speCified In the recommended operating conditions .
:I: Typical values are at Vee = S V, TA = 2soe.
total device
TEST CONDITIONst
PARAMETER
TL7770-SC
TL7770-12C
TL7770-51
MIN
VreS§
lee
Power-up reset voltage
Vee=VSU
Supply current
1VSU = 18 V, 2VSU = 2 V,
1RESIN and 2RESIN at Vee,
1VSO and 2VSO at 0 V
..
..
UNIT
TYpt
MAX
0.8
1
TA=2Soe
V
5
mA
TA = MIN to MAX
6.5
..
t For conditions shown as MIN or MAX, use the appropriate value speCified In the recommended operating conditions .
:I: Typical values are at Vee = S V, TA = 2Soe.
§ This is the lowest voltage at which RESET becomes active.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-143
TLn70-S, TL7nO-12
DUAL POWER-SUPPLY SUPERVISORS
SLVS019F - OCTOBER 1987 - REVISED JULY 1999
electrical characteristics over recommended operating conditions (unless otherwise noted)
supply supervisor section
TEST
CONDITIONS
PARAMETER
TL777Il-5Y
TL7770-12Y
MIN
TL7770-S (S-V sense, lVSU)
VIT-
Undervoltage input threshold at VSU
(negative-going)
TL7770-12 (12-V sense, lVSU)
TA = MIN to MAX
TL7770-S, TL7770-12
(programmable sense, 2VSU)
Vhys
TL7770-12 (12-V sense, WSU)
UNIT
MAX
4.46
4.64
10.68
11.12
1.47
1.S3
TL7770-S (S-V sense, lVSU)
Hysteresis at VSU
(VIT+ - VIT-)
TYpt
V
lS
36
TA = MIN to MAX
TL7770-S, TL7770-12
(programmable sense, 2VSU)
mV
S
VT
Overvoltage threshold at VSO
TL7770-S, TL777Q-12 (VSO)
TA =' MIN to MAX
II
Input current
VSO
VI =2.4V
2.48
2.68
V
I1A
O.S
tTYPlcal values are at Vee = S V, TA = 2soe.
total device
PARAMETER
TL7770-SY
TL777Q-12Y
TEST CONDITIONS
MIN
Vres:t:
ICC
Power-up reset voltage
Vee=VSU,
Supply current
lVSU = 18 V, 2VSU = 2 V,
1RESIN and 2RESIN at Vee,
1VSO and 2VSO at 0 V
TYPt
UNIT
MAX
0.8
VOL = 0.4 V, IOL= 1 rnA
ITA=2soe
V
S
rnA
tTYPICaJ values are at Vee = S V, TA = 2soe.
:t: This is the lowest voltage at which RESET becomes active.
switching characteristics,
Vee =5 V, CT open, TA = 25°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low-to-high-Ievel output
RESIN
RESET
270
SOO
ns
tpHL
Propagation delay time, high-to-Iow-Ievel output
RESIN
RESET
270
SOO
ns
tr
Rise time
tf
Fall time
tr
Rise time
tf
Fall time
tw(mln)
Minimum effective pulse duration
RESET
7S
lS0
7S
RESET
SO
RESIN
See Figure 2a
lS0
VSU
See Figure 2b
100
~TEXAS
INSTRUMENTS
10-144
See Figures 1
and 3
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
ns
ns
ns
TL7770-S, TL7770-12
DUAL POWER-SUPPLY SUPERVISORS
SLVS019F - OCTOBER 1987 - REVISED JULY 1999
PARAMETER MEASUREMENT INFORMATION
5V
5V
511 Q
RESET
J
1-115PF
I
I
_ _ _ _ _ .J
RESET __---,
(see Note A)
15pF
(see Note A)
511 Q
GND
RESET OUTPUT CONFIGURATION
RESET OUTPUT CONFIGURATION
NOTE A. This includes jig and probe capacitance.
Figure 1. RESET and RESET Output Configurations
~tw---1
~t4
'\-----1---::..
\-----1--- :v
v
- - - - Vrr- 2V
- - - - OV
a) RESIN
b)VSU
WAVEFORMS
Figure 2. Input Pulse Definition
I
I Voltage
Fault
it-~~~ ___ ~rv-:-+_-_-_-_-'l\~ ___________ .v
VSU _ _ _
I
RESIN
_ _ _...1.
"
RESET
1
i
1
I
1
'1
II
Jj
II
Undefined
J
I
tf---.!
I+-
9O%~1
II
1
_0.8V
i4---J
Jrttr---+
tPLH
l
i
I
I
I
I
10%
I
I
l 1i!4-1d1
it-Id-.'r
1
II
_ _ _ _ _1~0..::%"4
90%
I
tr ---.!
I
I
I
I
I
I
50%
1
I
~I
~Id-'
tf ....
RESET
----j+---t
90%
I
1
I
I
10%
I I
50%
I
I
~~ VOL
tpHL ~I
14-
Figure 3. Voltage Waveforms
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75266
10-145
TL7770·S, TL7770·12
DUAL POWER·SUPPLY SUPERVISORS
SLVS019F-OCTOBER 1987- REVISED JULY 1999
APPLICATION INFORMATION
Vs
System Supply
1
16
5
1
Reset Input
(from system)
RT
(see Note 8)
+~
10kO
VCC
1VSU
1RESET
4
To System Reset
1RESIN
2
3
1CT
To System Reset
1RESET
GND
1
10kO
8
l
NOTE B. When VCC and 1VSU are connected to the same point, it is recommended that series resistance (RT) be added between the time-delay
programming capacitor (CT) and the voltage-supervisor device terminal (1 CT). The suggested RT value is given by:
v -V
RT >...l..........Ia' where VI
1 x 10-
=
(the lesser of 7.1 V or Vs)
When this series resistor is used, the Id calculation is as follows:
td
=
1.3 - [(6.5E - 5) x 10- 5) x RTJ
6.5 x 10 5
x CT
Figure 4. System Reset Controller With Undervoltage Sensing
~TEXAS
10--146
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
General Information (Vol. 1)
Linear Voltage Regulators
Shunt Regulators
I Precision Virtual Grounds
Mechanical Data
General Information (Vol. 2)
I Processor PS Controllers
Switching PS and DC/DC Converters
I MOSFET Drivers
Supervisors
Mechanical Data
General Information (Vol. 3)
Power Distribution Switches
LED Drivers
Voltage Rail Splitters
Special Functions
Mechanical Data
11-1
. - -. . . . . .
--~
III
s:
(I)
(')
:r
Q)
_.
::::s
(')
Q)
-c
a
Q)
11-2
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
rr 11
14 PIN SHOWN
l
14
0.050 (1,27)
1
0.020 (0,51)
0.014 (0,3~
1-$-1 0.010 (0,25)
@1
T
0.244 (6,20)
0.228 (5,BO)
0.157 (4,00)
0.150 (3,81)
r-----------~~
c.
7
ifiUllbiiUllrlJ
t
.
0.069 (1,75) MAX
0.010(0,2il
0.004 (0,10)
~
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047/010/96
NOTES: A.
B.
C.
D.
All linear dimensions are in Inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
11-3
MECHANICAL DATA
MECHANICAL INFORMATION
PLASTIC SMALL·OUTLINE PACKAGE
DB (R·PDSO·G**)
28 PINS SHOWN
11
0,38\-$-\ 0,15
0,22
@\
'--"--'----=--------'=~
15
nl
5,60
5,00
8,20
7,40
~0"T"'T'T"T"T"T'T'T'T"T"I~ ~
14
~
8
14
16
20
24
28
30
38
A MAX
3,30
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
2,70
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065/C 10195
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice,
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
~TEXAS
INSTRUMENTS
11-4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MECHANICAL INFORMATION
PLASTIC SMALL-OUTLINE PACKAGE
DBT (R-PDSO-G**)
30 PINS SHOWN
11
0,271-$-1 0,08
0,17
@I
16
nT
4,50
4,30
0
6,60
6,20
TTTT"TT"TT'TTT'TT"TT"TT"T~ ~
c.
L.n-n-
15
Seating Plan~
1.c::..10,10
~*
DIM
28
30
38
44
50
A MAX
7,90
7,90
9,80
11,10
12,60
A MIN
7,70
7,70
9,60
10,90
12,40
4073252/009/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-1S3
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
11-5
--_._-- - - - - - - - - - - -
MECHANICAL DATA
MECHANICAL INFORMATION
DBV (R-PDSO-G3)
PLASTIC SMALL-OUTLINE
0,95 1--14--.t
1r:-
0,50
0,30
1~I
0,20
®I
L-.I.-'---'-----'=~
3
L~
2,80
t~,9~D----LD~dJ
0,95
0,05MINJ
4073253-2IE 05/99
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
~TEXAS
INSTRUMENTS
11-6
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MECHANICAL DATA
MECHANICAL INFORMATION
PLASTIC SMALL·OUTLINE PACKAGE
DBV (R.PDSO·G5)
0,25
®I
r
3,00
2,50
4073253·4/8 10/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusion.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11-7
MECHANICAL DATA
MECHANICAL INFORMATION
DCK (R·PDSO·G5)
PLASTIC SMALL·OUTLINE
1~
1.1
®I
0,30
0,10
0,15 '---'---'----'--':=::..0
4
o,so
0,00
4093553/8 06/99
NOTES: A.
B.
C.
D.
11-8
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO·203
:'I
TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS. TEXAS 75265
MECHANICAL DATA
MECHANICAL INFORMATION
PowerPADTM PLASTIC SMALL·OUTLINE PACKAGE
DGN (S·PDSO·G8)
Thermal Pad
(See Note 0)
,----,
I
I
I
I
3,05
2,95
I
_0I"""'TL.....,.-...,...-""I""--..,.--.J~
I
I
J
4,98
4,78
C3~_4
:-------"-
2,95
lf1i1iilld~
~MAX
.
~J
0,05
40732711A 04198
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions include mold flash or protrusions.
The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO·187
PowerPAD is a trademark of Texas Instruments Incorporated.
-!11
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
11-9
MECHANICAL DATA
MECHANICAL INFORMATION
DW (R-PDSO-G**)
16 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
1r-
0.020 (0,51)
0.01: (0,35)
1-$-1 0.010 (0,25) ® 1
1ll
0.419 (10,65)
0.400 (10,15)
0.299 (7,59)
0.293 (7,45)
Ir--------,JJ
8
rt friJLiiiiJiiiJi~
0.104 (2,65) MAX
0.012 (0,30tJ
0.004 (0,10)
~
16
20
24
28
A MAX
0.410
(10,41)
0.510
(12,95)
0.610
(15,49)
0.710
(18,03)
A MIN
0.400
(10,16)
0.500
(12,70)
0.600
(15,24)
0.700
(17,78)
DIM
4040000/C 07196
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimelers).
This drawing is subjecl to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MS-013
~TEXAS
11-10
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINALS SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
..
12
19
11
B
A
MIN
MAX
MIN
MAX
20
0.342
(8.69)
0.358
(9.09)
0.307
(7.80)
0.358
(9.09)
28
0.442
(11.23)
0.458
(11.63)
0.406
(10.31)
0.458
(11.63)
20
21
9
22
8
44
0.640
(16.26)
0.660
(16.76)
0.495
(12.58)
0.560
(14.22)
7
52
0.740
(18.78)
0.761
(19.32)
0.495
(12.58)
0.560
(14.22)
68
0.938
(23.83)
0.962
(24,43)
0.850
(21.6)
0.858
(21.8)
84
1.141
(28.99)
1.165
(29.59)
1.047
(26.6)
1.063
(27.0)
BSQ
ASQ
lti
24
6
23
25
5
'---------------------<
~~~~~_r'_,,_''_,,~v
26
27
28
234
0.020 (0,51)
0.010 (0,25)
-+I
14- .
IU
~ 0.020 (0,51)
0.010 (0,25)
0.028 (0,71)
0.022 (0,54)
--.I J.4040140/C 11/95
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hennetically sealed w~h a metal lid.
The terminals are gold-plated.
Falls within JEDEC MS-004
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
11-11
MECHANICAL DATA
MECHANICAL INFORMATION
JG (R-GDIP-T8)
CERAMIC DUAL-IN-L1NE PACKAGE
0.400 (10,20)
0.355 (9,00)
f
0.280 (7,11)
0.245 (6,22)
*
1-;:::=---;:::=0':;-02~0;::(=0';-51~)=M=IN;-(
+-----.
J (~'08)*
f
0.200
0.310 (7,87)
0.290 (7,37)
MAX
Seating Plane
0.130 (3,30) MIN
jL"... ~~f
0.015 (0,38)
JL
~
0°_15°
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in Inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal Identification only on press ceramic glass fril seal only.
Falls within MIL·STD·1835 GDIP1-T8
.
~TEXAS
INSTRUMENTS
11-12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MECHANICAL INFORMATION
PLASTIC CYLINDRICAL PACKAGE
LP (O·PBCY·W3)
0.022 (0,56)
0.016 (0,41)
Wid}
e
0.165 (4,19) --14---~
0.125 (3,17)
3 Leads
0.016 (0,41) Thl k
0.014 (0,35)
c
0.105 (2,67)
0.080 (2,03)
Seating Plane
0.055 (1,40)
0.045 (1,14)
0.050 (1,27)
(see Note C)
0.105 (2,67)
0.095 (2,41)
0.135 (3,43) MIN
f
0.205 (5,21)
DIA
0.175 (4,44)
*
0.210 (5,34)
0.170 (4,32)
---11~"----I.l"I----
0.500 (12,70) MIN
J
01~:J
0.080 (2,03)
40400011 B 01/95
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Lead dimensions are not controlled within this area.
Falls within JEDEC TO-226AA (TO-226AA replaces TO-92)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
11-13
MECHANICAL DATA
MECHANICAL INFORMATION
N (R·PDIP.T**)
PLASTIC DUAL·IN·LlNE PACKAGE
16 PIN SHOWN
~
14
16
18
20
A MAX
0.775
(19,69)
0.775
(19,69)
0.920
(23.37)
0.975
(24,77)
A MIN
0.745
(18,92)
0.745
(18,92)
0.850
(21.59)
0.940
(23,88)
DIM
f
0.260 (6,60)
0.240 (6,10)
1
~ ~
0.035 (0,89) MAX
0.070
(1~78)
MAX
*
~
0.020 (0,51) MIN
Seating Plane
JL
'I
0.310 (7,87)
0.290 (7,37)
1
~0.100(2,54)1
0.021 (0,53) ,::;:-r-::-::-cc::-::o-::-::::,...-;:;"
0.015 (0,38) 1-$-1 0.010 (0,25)
1
®
14/18 PIN ONLY
4040049/C 08195
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
~TEXAS
INSTRUMENTS
11-14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
NS (R-PDSO-G**)
MECHANICAL INFORMATION
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
~
14
1
II.
1-$-1
®I
0,51
0,25
0,35 '--"---'---'-----"'''-'
8
TIl
5,60
5,00
8,20
7,40
~O~...,...,......,...,....,.--,-, ~
~
14
16
20
24
A MAX
10,50
10,50
12,90
15,30
A MIN
9,90
9,90
12,30
14,70
DIM
40400621B 02195
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11-15
MECHANICAL DATA
MECHANICAL INFORMATION
P (R·PDIP·T8)
PLASTIC DUAL·IN·LlNE PACKAGE
r.
11--
- 8 - - - - - 5••
0.400
0.355(10,60)
(9,02)
--r-f
0.260 (6,60)
0.240 (6,10)
o
JL
*
4
R
0.070 (1,78) MAX
0.020 (0,51) MIN
14-------+1--
0.310 (7,87)
0.290 (7,37)
0.200 (5,08) MAX
+
--'f"---0.-12-5.L.(3,18) MIN
JLI..-.h
0.100(2,54)
1
Seating Plane
f
1-$-1.0.010 (0,25) ® 1.
0.021 (0,53)
0.015 (0,38)·
Jl
~OO_150
0.010 (0,25) NOM
40400821 B 03/95
NOTES: A. All linear dimensions are In inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS·OOI
~TEXAS
11-16
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MECHANICAL INFORMATION
PK (R-PSSO-F3)
PLASTIC SINGLE-IN-LINE PACKAGE
r-----:
0'4L+-1~
oTYP
,
4,40
460
1,80 MAX
-----.
I
L
2,60
2,40
4,25 MAX
------r
0,80 MIN
J L,.....
~
...
,,"MAX~ i ~
1,50 TYP
I.
0'44MAX~ ~
~I
4040234/803/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. The center lead is in electrical contact with the tab.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
11-17
MECHANICAL DATA
MECHANICAL INFORMATION
PS (R·PDSO·G8)
PLASTIC SMALL·OUTLINE PACKAGE
~881 11
~
15
~::! I~I
0,25@1
TIl
5,60
5,00
.......,..,.0....,...,.--r-rT"'T""""'"
~'$
8,20
7,40
~
•
5,90
4040063/B 02/95
NOTES: A. All linear dimensions are In millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not Include mold flash or protrusion, not to exceed 0,15.
~TEXAS
11-18
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MECHANICAL DATA
MECHANICAL INFORMATION
PW (R·PDSo-G**)
14 PIN SHOWN
PLASTIC SMALL·OUTLINE PACKAGE
1r ~:~: ~-,-,-1_0.:....,1_0..,,@,,-,1
,..,u-u-u-u-u-ur=fl
1-1
4,50
4,30
6,60
6,20
- .."~ @~I--__....IhL
rbooooood~
~20 MAX
, MIN J
1~lo,10 ~
005
~
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/E 08/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-I53
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11-19
MECHANICAL DATA
MECHANICAL INFORMATION
PowerPADTM PLASTIC SMALL·OUTLINE
PWP (R·PDSO·G**)
20 PINS SHOWN
1r-
0,30
0,19
11
Ii-I
0,10
@I
L..:I.--'---.:.!..:..::....::~
------,r
Thermal Pad
(See Note D)
o
LA
10
0-+---.---~
r6DDDDDDDDDa~ ...... A.Mj
~20MAX
,
.
mJ
1='10,10
0,05
~
~
14
16
20
24
28
A MAX
5,10
5,10
6,60
7,90
9,80
A MIN
4,90
4,90
6,40
7,70
9,60
DIM
40732251F 10/98
NOTES: A.
B.
C.
D.
All linear dimensions are In millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusions.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls wHhin JEDEC MQ-153
PowerPAD is a trademark of Texas Instruments Incorporated.
~TEXAS
11-20
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MECHANICAL DATA
MECHANICAL INFORMATION
U (S-GDFP-F10)
CERAMIC DUAL FLATPACK
Base and Seating Plane
~
0.008 (0,20)
0.004 (0,10)
'-- 0.080 (2,03)
0.050 (1 ,27)
J
0
I
0.280 (7,11)
0.230 (5,84)
1
:
I
I
I
lI---I----------'::!'.QOO".>nI
I
i
I
Il--'--------,~
l
L j
0.350 (8,89)
0.250 (6,35)
NOTES: A.
B.
C.
D.
E.
0.350 (8,89)
0.250 (6,35)
J
t
4Places
0.005 (0,13) MIN
4040179/B 03/95
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass lri!.
Index point is provided on cap lor terminal identification only.
Falls within MIL STD 1835 GDFP1-F10 and JEDEC MQ-092AA
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11-21
11-22
NOTES
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Local Access Code
Australia
1-80Q-B81-o11
China
10810
Hong Kong 800-96-1111
India
000-117
Indonesia 001-801-10
Korea
080-551-2804
Malaysia
1-800-800-011
New Zealand 000-911
Philippines 105-11
Singapore 800-0111-111
Taiwan
080-006800
Thailand
0019-991-1111
Fax
886-2-2378-6808
Email
tiasia@ti.com
Internet
www.ti.com/sc/apic
+32 (0) 27 45 55 32
+33 (0) 130 701164
+49 (0) 8161 803311
18009490107
8007911 37
+31 (0) 546 87 95 45
+34 902 35 40 28
+46 (0) 8587 555 22
+44 (0) 1604 66 33 99
+44 (0) 1604 66 33 34
epic@ti.com
www.ti.com/sc/epic
Japan
Phone
Intemational
Domestic
+81-3-3344-5311
0120-81-0026
TI Number
-800-800-1450
-800-800-1450
-800-800-1450
-80Q-B00-1450
-800-800-1450
-800-800-1450
-800-800-1450
-800-800-1450
-800-800-1450
-800-800-1450
Fax
International
Domestic
Internet
Intemational
Domestic
+81-3-3344-5317
0120-81-0036
www.ti.com/sc/jpic
www.tij.co.jp/pic
@1999Texas Instruments Incorporated
Printed in the USA
~TEXAS
INSTRUMENTS
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TEXAS
INSTRUMENTS
Printed in U.S.A.
10/99
SLVD004
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