20_WD10C01A 20 WD10C01A
User Manual: 20_WD10C01A
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WD10C01A
TABLE OF CONTENTS
Page
Section
Title
1.0
INTRODUCTION
Features
1.1
20-1
20-1
2.0
GENERAL DESCRIPTION
20-2
3.0
SYSTEM BLOCK DIAGRAM
20-3
4.0
SIGNAL DESCRIPTION
20-4
5.0
ARCHITECTURE
Error Correction And Detection Codes
5.1
5.1.1
CCID-CRC
Reed-Solomon ECC
5.1.2
20-7
20-8
20-8
20-8
6.0
PROGRAMMING REFERENCE
Register Assignments
6.1
6.2
Register Definitions
Configuration
Group
6.3
6.3.1
SRESET - Set Hardware Reset Register (00)
6.3.2
SISR - Interrupt Status Register (01)
SIMR - Interrupt Mask Register (02)
6.3.3
SEQSTS - Sequencer Status (03)
6.3.4
PVC - Port Y Configuration (03)
6.3.5
6.3.6
Control Store Windows
CSERR - Control Store Error Control Byte
6.3.6.1
Window (04)
CSCTL - Control Store
6.3.6.2
Control Byte Window (05)
CSVAL - Control Store Value Byte Window (06)
6.3.6.3
CSCNT - Control Store Count Byte Window (07)
6.3.6.4
Wait Condition Sequences
6.3.6.5
Device Control Group
6.4
PORTX - PORTX Output Bits (08)
6.4.1
PORTY - PORT Y I/O Bits (09)
6.4.2
PORTZ - PORT Z Input Bits (OA)
6.4.3
AMC - Address Mark Control (OA)
6.4.4
SEQCTL - Sequencer Control Register (OB)
6.4.5
START - Sequencer Start Address (OC)
6.4.6
LOOP - Sequencer Loop Address (00)
6.4.7
ECCCTL - Error Correction Control Register (OE)
6.4.8
SECCNT - Sector Count Register (OF)
6.4.9
6.4.10 ECCP- ECC Parameter Register (10)
ECCS - RS-ECC Status Register (11 )
6.4.11
20-9
20-9
~
~
11/19/91
· 20-10
· 20-11
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20-12
20-13
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· 20-16
· 20-17
· 20-18
· 20-20
· 20-21
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.20-23
.20-24
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20-25
20-26
20-27
20-28
20-29
20-30
20-i
..
WD10C01A
Section
Page
Title
6.5
6.6
6.4.12 SPORT - Syndrome Port (12)
6.4.13 TEST - Test Register (16) .
6.4.14 SKIP - Skip Address Register (17)
ID Register Group
Device Programming
6.6.1
Initialization
6.6.2
Command Programming
6.6.3
Control Store Programming
6.6.4
Programming Examples
6.6.4.1
Format Track Example
6.6.4.2
Read Sector Example
6.6.4.3
Write Sector Example
6.6.4.4
Read And Write Sector Example
6.6.5
ID Retry And Error Conditions
6.6.6
Error Recovery
6.6.7
Error Correction . .
.20-31
.20-31
.20-32
.20-33
.20-35
.20-35
.20-35
.20-35
.20-37
.20-38
.20-40
.20-42
.20-44
.20-46
.20-47
.20-48
7.0
DC ELECTRICAL SPECIFICATIONS
7.1
Absolute Maximum Ratings
7.2
Standard Test Conditions . .
7.3
DC Characteristics
.20-49
.20-49
.20-49
.20-50
8.0
AC OPERATING CHARACTERISTICS
8.1
OSC And CPUCLK Timing
8.2
CPU Interface Timing
8.3
Buffer Interface Timing . .
8.4
Serial Data Timing
. 20-51
.20-51
.20-54
.20-58
.20-61
A.O
WD10C01A PROGRAMMER'S BENCH REFERENCE (PBR)
A.1
Address Bit Tables
.20-63
.20-63
B.O
RESET CONDITIONS . .
.20-66
C.O
CRYSTAL OSCILLATOR APPLICATIONS
.20-67
D.O
PIN/SIGNAL SUMMARY . . . . . . .
.20-68
E.O
DIFFERENCES BETWEEN WD10COO AND WD10C01A
E.1
Error Correction And Detection
E.2 SRESET Register
E.3
ECCCTL Register
E.4 Timing
E.5
Pin Name . . .
E.6 Parity Error Handling
E.7 SEQCTL Register .
.20-69
.20-69
.20-69
.20-69
.20-69
.20-69
.20-69
.20-69
20-ii
11/19/91
WD10C01A
LIST OF ILLUSTRATIONS
Figure
Title
Page
1-1
3-1
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
C-1
WD10C01A Pin Diagram
System Block Diagram
TTL Source X1 Clock Input
OSC Output
CPUCLK Output
Microprocessor RD" Timing (RD" Controlled)
Microprocessor RD" Timing (CS" Controlled)
Microprocessor WR" Timing (WR" Controlled)
Microprocessor WR" Timing (CS" Controlled)
Reset Timing
Externally Generated Interrupt Timing
Asynchronous Mode Data Bus Read Timing (1)
Asynchronous Mode Data Bus Read Timing (0)
Asynchronous Mode Data Bus Write Timing (1)
Asynchronous Mode Data Bus Write Timing (0)
NRZ Data Input Timing
NRZ Data Output Timing
Oscillator with Capacitors
20-1
20-3
· 20-51
· 20-51
· 20-52
· 20-54
.20-54
· 20-55
.20-55
·
·
·
·
·
·
·
·
·
20-56
20-56
20-58
20-58
20-59
20-59
20-61
20-61
20-67
LIST OF TABLES
Page
Table
Title
4-1
4-2
4-3
4-4
4-5
6-1
6-2
6-2A
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
CPU Interface
Buffer Interface
Disk Data Interface
Disk Control Interface
Device Power
Register Groups
SRESET- Set Hardware Register (00)
ID Register Selection
SISR - Interrupt Status Register
SIMR -Interrupt Mask Register
SEQSTS - Sequencer Status Register
PVC - Port Y Configuration (03)
CSERR - Control Store Error Control Byte Window
~
CSCTL - Control Store Byte Window (05)
SVSEL of Control Byte Zero
SVSEL of Control Byte One
CWSEL of Control Byte Zero
CWSEL of Control Byte One
11/19/91
20-4
20-5
20-5
20-6
20-6
20-9
· 20-11
· 20-12
· 20-12
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·
·
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20-13
20-14
20-15
20-16
20-17
20-18
20-19
· 20-20
.20-20
20-iii
II
WD10C01A
Page
Table
Title
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
PortX Output Bits (08)
PortY 110 Bits (09)
PortZ Input Bits (OA)
AMC - Address Mark Control (OA)
SEQCTL - Sequencer Control Register (OB)
START - Sequencer Start Address (OC)
LOOP - Sequencer Loop Address (00)
ECCCTL - Error Correction Register (1 E)
SECCNT - Sector Count Register (OF)
ECCP - ECC Parameter Register (10)
ECCS - RS-ECC Status Register (11)
SPORT - Syndrome Port (12)
SKIP - Skip Address Register (17)
Skip Control Store Example
100 -10 Register 0 (18)
101 - 10 Register 1 (19)
102 -10 Register 2 (1A)
103 - 10 Register 3 (1 B)
104 - 10 Register 4 (1 C)
105 - 10 Register 5 (10)
106 - 10 Register 6 (1 E)
107 - 10 Register 7 (1 F)
Write Byte Sync Example
Oata Field Size Example
Format Track Example Control Store
Read Sector Example Control Store
Write Sector Example Control Store
Read and Write Sector Example Control Store
OC Characteristics
OSC and CPUCLK Timing Parameters
CPU Interface Timing Parameters
Buffer Interface Timing Parameters
Serial Oata Timing Parameters
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
7-1
8-1
8-2
8-3
8-4
20-iv
11/19/91
.20-22
.20-22
.20-22
.20-23
.20-24
.20-25
.20-26
.20-27
.20-28
.20-29
.20-30
.20-31
.20-32
.20-32
.20-33
.20-33
.20-33
.20-33
.20-34
.20-34
.20-34
.20-34
.20-36
.20-36
.20-38
.20-40
.20-42
. 20-44
.20-50
.20-53
.20-57
.20-60
.20-62
WD10C01A
INTRODUCTION
1.0
INTRODUCTION
The WD10C01A is a VLSI Winchester/Optical
Disk Controller chip that provides the data handling and control for intelligent disk applications.
The WD10C01A interfaces to nearly any serial
disk interface, including ST412, ST412HP, ESDI,
SMD, and many optical disk interfaces. The
WD1 OC01 A provides great flexibility in format
design, allowing for multiple ID fields, special
synchronization requirements, special information
fields, or almost any other special requirement.
The WD1 OC01 A can provide all of the data,
status, and control signals required by these interfaces.
cs·
VDD
DBO
DBl
DB2
DB3
DB4
DB5
DB6
DB7
RD'
WR'
M
fo3
fo2
Al
AO
RG
WG
PXO
PXl
PX2
PX3
PX4
PX5
PX6
PX7
PYO
PYl
PY2
PY3
PZO
VDD
1.1
PZl
FEATURES
• Disk interfaces and formats supported include
ST412, ST412HP, ESDI, SMD and optical disks
• Full multi-sector operation with four byte ID
auto-increment
• Up to 24 mbitlsecond maximum transfer rate
• Supports 16-bit CRC-CCITT polynomial on ID
field
• Degree 5 and 6 Reed-Solomon ECC with 3- or
5-way interleave to protect data field against
long error burst
• Provides composite syndromes for error
correction
• Up to 1:1 interleave operation
• Writeable control store allows flexible error
Recovery, including redundant ID and sync
fields
FIGURE 1-1, WD10C01A PIN DIAGRAM
• Support hard or soft sector formats, sector size
to 1250 bytes when 5-way interleave is used
for degree 5 Reed-Solomon code
• Built in crystal driver for data rate and/or CPU
use
• Generic non-multiplexed CPU interface with
maskable interrupts
• Separate CPU and disk data busses
• On-the-fly compare against buffer data
• 20 general I/O Lines for disk drive control
• 68-Pin PLCC package
11/19/91
20-1
•
WD10C01A
2.0
GENERAL DESCRIPTION
GENERAL DESCRIPTION
The WD10C01A has separate ports for data DMA
transfer and for the microprocessor to achieve a
maximum performance.
The WD10C01A performs the disk data serialization and de-serialization. It can interface with
various magnetic and optical Data Encoder/Decoders (ENDEC). The data format on the
disk is controlled by a Writeable Control Store. It
is very flexible with the capability to support
various formats including optical disk. The device
also has the capability to compare data and verify
the ECC. The WD10C01A can perform full track
operations without CPU intervention using the
Writeable Control Store, auto-incrementing 10
registers and the sector counter.
The WD10C01A includes logic implementing
CCITT-CRC and Reed-Solomon ECC for data
protection. The 10 field is protected by sixteen bit
CRC and the data field is protected by degree five
or six RS-ECC. The user can also select the interleave factor of three or five for the data field. The
term "interleave" here should not be confused
with the term "sector interleave," which defines
the relation between the physical and the logical
location of sectors within a track. Interleaving the
data field means spreading the data across
several ECC code words to improve the capability
for correcting longer error bursts.
For the error correction, the WD1 OC01 A
generates the composite syndromes. From this
error information, the correction software can
generate individual syndromes to correct up to
two error bytes per interleave (for degree 5) or up
to three error bytes per interleave (for degree 6).
Optionally, the user can use external, more
powerful ECC device, such as WD60C80.
20-2
The highly programmable nature of the
WD10C01A allows the use of redundant 10 and
data sync fields within a single sector. This feature, along with the programmable degree 5 or 6
RS-ECC, gives the WD1 OC01 A a greater
capability for recovering user data in a sector with
'grown' defects.
The WD10C01A interfaces to the buffer manager,
such as WD60C40 through an eight bit DMA port.
It uses asynchronous protocol through
DREQ/DACK signals.
The WD10C01A has a generic microprocessor interface that allows the WD10C01A to be used
with all popular 8-bit microprocessors. The
WD10C01A has interrupt capability, which frees
up the microprocessor from constantly polling the
device status. The WD1 OC01 A also has a built-in
crystal oscillator driver that can be used to
generate data reference, buffer management, or
microprocessor clocks. Two separate outputs are
provided with internal programmable dividers.
Both outputs have the extra drive voltage and current necessary for driving MOS microprocessor
clock inputs.
The WD10C01A has 20 lines dedicated to external I/O ports that the microprocessor can use to
control the drive and head select lines, seek command and drive status. Eight lines are output only,
six lines are input only, and four other lines can be
individually programmed for input or output. Two
other latch and hold input lines are tied to the
interrupt logic and can be used to detect fault and
ready conditions without constantly polling the
device.
11/19/91
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WD10C01A
4.0
SIGNAL DESCRIPTION
SIGNAL DESCRIPTION
The WD1 OC01A is a 68-pin PLCC device.
1/0 indicates that a signal is bidirectional.
The following section describes the external signals available on the WD10C01A. Conventions
are as follows:
1,0 indicates that a signal can be input
output.
*
indicates that a signal is an input to the
WD10C01A.
o
as a suffix indicates an active low signal;
however, most drawings and text use an
overscore to indicate an active low signal.
indicates that a signal is an output from
the WD10C01A.
PIN
25-21
MNEMONIC
AO-A4
I/O
I
36
CPUCLK
0
10
CS
I
11-18
DBO-DB?
1/0
2?
INT
0
33
OSC
0
19
RD
I
61
RST
I
20
WR
I
3?
X1
I
38
X2
0
DESCRIPTION
CPU ADDRESS BUS. These signals are used to address internal
WD10C01A registers.
CPU CLOCK OUTPUT. This is the OSC output (see below)
divided by two or three, selected by an internal register. This output has extra drive for use with certain microprocessors.
CHIP SELECT. This active low signal enables the WD10C01A bus
interface logic.
CPU DATA 1/0 BUS. This data bus is used to transfer data between the CPU and the WD10C01A.
CPU INTERRUPT. This active low, open drain output is asserted
whenever an enabled interrupt condition occurs on the
WD10C01A.
OSCILLATOR OUTPUT. The 1x crystal oscillator output, optionally
divided by two. This signal has the same drive capability as
CPUCLK.
CPU READ STROBE. This active low signal enables data from
the WD10C01Aon to the CPU data bus.
RESET. This active low signal resets all internal circuits that must
be reset at power on. A complete list is given later in this document. The reset is latched and the condition must be cleared by
the CPU.
CPU WRITE STROBE. This active low Signal strobes data into the
selected WD1 OC01 A register from the CPU data bus.
CRYSTAL DRIVER INPUT. X1 can also be driven by an external
clock.
CRYSTAL DRIVER OUTPUT.
TABLE 4-1. CPU INTERFACE
20-4
11119/91
WD10C01A
SIGNAL DESCRIPTION
PIN
67
MNEMONIC
ACKA
1/0
8-1
BMDO-7
1/0
68
BMDP
1/0
66
REQA
0
I
DESCRIPTION
BUFFER DATA ACKNOWLEDGE. This active low signal indicates
to the WD1 OC01 A that data can now be transferred to or from the
data buffer.
BUFFER MEMORY DATA BUS. This is an eight bit data bus that
interfaces the WD10C01A with the disk data buffer memory.
DATA BUS PARITY. This signal is used to generate and check
parity with the disk data buffer memory.
BUFFER DATA REQUEST. This signal is asserted when the
WD1 OC01 A has data to write to the data buffer, or needs data
from the data buffer.
TABLE 4·2. BUFFER INTERFACE
PIN
30
MNEMONIC
AMDET
1/0
31
AMENA
0
65
NRZI
I
63
NRZO
0
59
RG
0
64
RRCLK
I
32
SEQOUT
0
58
62
WG
WRCLK
0
0
I
DESCRIPTION
ADDRESS MARK DETECTED. Used only in ST412 type interfaces that use missing clocks or other qualifiers to the sync bytes
that mark the start of a field.
ADDRESS MARK ENABLE. Used to write a missing clock sync
byte (ST412) or soft sector mark (ESDI SMD) on the media.
NRZ READ DATA IN. Serial data input from the disk phase-locked
loop. This signal is clocked in by the rising edge of RRCLK.
NRZ WRITE DATA OUT. Serial data output. NRZO is valid on the
rising edge of WRCLK.
READ GATE. Active when reading from the disk drive. This signal
is turned off for one byte time on an ID search error to reset external data decoders.
READ/REFERENCE CLOCK. This is the reference clock used to
set the data rate for write, and is the recovered clock for read. The
switching must be glitch free. NRZI is clocked into the WD10C01A
by the rising edge of this clock.
SEQUENCER OUTPUT. This signal is a user definable output bit
that is set up in the control byte of the sequencer control store
(see below). This signal can be used to control an external ECC
generator and checker, and is byte aligned with both read and
write data.
WRITE GATE. Active when writing to the disk drive.
WRITE CLOCK. This is output during write for drives that require
it. NRZO data is valid on the rising edge of this clock.
TABLE 4·3. DISK DATA INTERFACE
11/19/91
20-5
II
WD10C01A
SIGNAL DESCRIPTION
PIN
35
MNEMONIC
COMPLT
I/O
34
DRVFLT
I
29
INDEX
I
57-50
PXO-7
0
49-46
PYO-3
1,0
45,44,
42-39
PZO-5
I
28
SECTOR
I
.
I
DESCRIPTION
COMPLETE. This signal is used to detect function complete conditions, such as seeks or status requests. The signal only generates
a CPU interrupt, and does not interfere with a read or write operation.
DRIVE FAULT. This signal is used to detect faults from the drive.
The signal only generates a CPU interrupt, and does not interfere
with a read or write operation.
INDEX. This signal is used to indicate the start of a track. This signal is latched for CPU status and interrupt.
PORT X. This general purpose output port is intended for use as
drive select and head select siQnals .
PORT Y. This general purpose port is intended for use as other
control outputs or inputs. Each bit is selectable as input or output,
but all bits are initialized to input when the WD1 OC01A is reset.
PORT Z. This general purpose input port is used to receive drive
status siQnals.
SECTOR MARK. This signal is used for marking sector start locations on the media. This can either be a hard sector mark, or a soft
mark written on the media using AMENA (ESDI or SMD).
TABLE 4-4. DISK CONTROL INTERFACE
PIN
26,60
9,43
MNEMONIC
VDD
VSS
I/O
I
I
DESCRIPTION
+5 VOLTS DC.
GROUND.
TABLE 4-5. DEVICE POWER
20-6
11/19/91
WD10C01A
ARCHITECTURE
5.0
ARCHITECTURE
The WD1 OC01 A consists of the functional blocks
shown in the block diagram in Figure 3-1. VDD
and VSS are applied to the device through two
separate pins each to improve noise immunity.
The top and left hand sides of the diagram show
CPU interface features, the right hand side shows
disk interface features, and the bottom shows
buffer interface features. These blocks are discussed in the following paragraphs.
The PORT DECODE block generates the 28 write
strobes and 25 read strobes used by the
microprocessor to access the various internal
control and status ports. These include the interrupt registers, external disk control ports, control
store, control store control, configuration, ECC
control, and 10 registers.
The BUFFER CPU DATA block controls the transfer of data between the microprocessor and the
internal registers. The direction control is qualified
by chip select (CS) and read strobe (RD).
The CPU CONFIGURATION PORTS are used to
reset the WD 1OCO 1A, set the address mark
enable timing, set the buffer interface timing, and
select the frequency of the clock outputs, OSC
and CPUCLK.
The OSCILLATORS AND DIVIDERS block
generates the clock outputs, OSC and CPUCLK,
using an external crystal (or clock input) and
dividers to select the frequency. Frequency selection is glitch free.
The INTERRUPT STATUS AND MASK registers
are used to check and mask interrupts. The mask
register does not affect the status register inputs.
The interrupt sources include index and sector
mark, drive fault and operation complete, ECC errors, and internal event status.
The EXTERNAL PORTS are used to generate
control signals and read status with the disk drive.
Eight bits are output, six are input, and four are
individually programmable for either input or output.
The CONTROL STORE consists of 32 words of
28 bits that are used to program the format of the
disk sector. The data source, field length, error
handling and checksum selection, and control sig-
nals, like Read Gate and Write Gate, are controlled by the data stored here.
The CONTROL STORE CONTROL determines
the next address in the control store to use,
whether the next sequential address or a jump to
another address. This block includes the sector
counter used for multi-sector commands. This
block also includes the BIT RING COUNTER,
which determines the timing of data transfers in
the WD10C01A.
The WAIT SEQUENCER handles searches for
index, sector mark, address mark, and byte
synchronization.
The 10 WRITE REGISTERS are 8 eight bit
registers that are used to set the 10 write field for
format, or the search field for read/update write.
Four of the registers are counters that auto-increment during multi-sector commands. The other
four registers do not increment, and are used for
defect and flag information. The first byte of the
four counters can be disabled for three byte 10
fields.
The 10 READ REGISTERS are used to read the
last 10 read from the media to aid in defect handling.
The ECD block performs the CRC on 10, selects
the degree of RS-ECC with 3- or 5-way interleave
on data fields, generates the checksum bytes,
creates the composite syndromes and ECC error
status necessary for the calculation of error location and mask.
The VALUE register holds immediate data from
the control store when generating gaps, sync
fields, and address mark bytes.
The SHIFT OUT register serializes internal or external (buffer) data for writing on the disk. The
output is multiplexed with the output of the checksum register.
The SHIFT IN register de-serializes the read data
from the disk, clocked in by RRCLK. The data is
also transferred to the checksum register for
checking.
The COMPARE block is used to compare incoming read data with an internal or external data
11/19/91
20-7
II
I
WD10C01A
ARCHITECTURE
source. These include byte synchronization
detection, 10 field search, and buffer data compare.
The coefficients of the polynomial in decimals are:
The BUFFER INTERFACE handles the fetching
and writing of data with the external data buffer.
This includes parity generation and checking, and
data handshake with the buffer controller.
2. Degree 6, distance 7:
5.1
The coefficients of the polynomial in decimals are:
5.1.1
ERROR CORRECTION AND
DETECTION CODES
1,60,183,183,60,1.
G(x) =(x+a 125)*(x +a126)*(x +a 127)*(x+a128)*
1,176,126,163,126,176,1.
CCITT·CRC
The WD10C01A protects the 10 fields using the
CCITT-CRC code. The polynomial is defined as
follow:
g(x) = x16 + x12 + x5 + 1
The user can select the initial state of the shift
registers to be either all zero's or all one's.
The calculated checkbytes are inverted before
they are written into the disk. During read operation, the WDl OCOl A computes the composite
syndromes by recalculating the checkbytes for the
data field being read and compare them against
the checkbytes written on the disk. The individual
syndromes can be computed by dividing the composite syndromes with the factors of the generator
polynomial:
Si(X)
5.1.2
= R(x) MODULO Gi(X)
where:
Reed·Solomon ECC
The data fields are protected using the interleaved
Reed-Solomon code operating on 8 bits symbols.
The redundancy bytes are inverted. WDl OCOl A
supports two polynomials of degree five and six.
The generator polynomials operate in the finite
field GF(256), which are defined as follow:
= O.. ecc degree -1.
= i'th individual syndrome.
R(x)
= composite syndrome.
Gi(X)
Let Bi represent elements of a finite field defined by a
polynofuial over GF(2):
The elements of the finite field employed by the
codes are:
Si(X)
= factQr of the generator polynomial,
(x+a l).
The WD10C01A supports two data interleaving
factors. The user can optimize the performance
by choosing the right degree and. interleave combination.
The following table shows the redundancy overhead and maximum field size.
The generator polynomials are self reciprocal and
defined as follows:
1. Degree 5, distance 6:
G(x) = (x+a253)*(x+a254)*(x+aO)*(x+a1)*(x+a2).
Interleave
Degree 5
DegreeS
Factor Overhead* Max. Data" Overhead" Max. Data"
Field Size"
Field Size"
747
15
750
18
3
1250
1245
25
30
5
* all units bytes
20-8
11/19/91
WD10C01A
PROGRAMMING REFERENCE
6.0
PROGRAMMING REFERENCE
6.1
REGISTER ASSIGNMENTS
The W01 OC01 A contains 32 output and 23 input
ports distributed i~a 32 QQ!"t address space,
selected by AO-A4, CS, and RO or WR.
The ports are split into three functional groups:
• configuration group
• device control group
• 10 registers.
Address lines A4 and A3 select the group, and A2
through AO select the register in the group.
CONFIGURATION
Address
00000
Assignment
DEVICE CONTROL 1
R/W
Address
Assignment
R/W
SRESET
W
01000
PORTX
R/W
00001
SISR
R/W
01001
PORTY
R/W
00010
SIMR
RIW
01010
PORTZIAMC
R/W
00011
SEQSTS/PYC
R/W
01011
SEQCTL
R/W
00100
CSERR
RIW
01100
START
R/W
00101
CSCTL
R/W
01101
LOOP
R/W
00110
CSVAL
R/W
01110
ECCCTL
R/W
00111
CSCNT
R/W
01111
SECCNT
R/W
10 REGISTERS
DEVICE CONTROL 2
Address
10000
Assignment
ECCP
R/W
W
Address
11000
Assignment
R/W
100
R/W
10001
ECCS
R
11001
101
R/W
10010
SPORT
R
11010
102
R/W
10011
11011
103
R/W
10100
11100
104
R/W
10101
10110
TEST - do not use
10111
SKIP
W
11101
105
R/W
11110
106
R/W
11111
107
R/W
TABLE 6-1. REGISTER GROUPS
11/19/91
20-9
WD10C01A
6.2
PROGRAMMING REFERENCE
REGISTER DEFINITIONS
Direction
The following sections describe each register in
detail. The use of the register is described in
general andlor each bit is described. The table
below defines how bit directions are defined in
these sections. Sometimes, a bit encoding is used
to select a function that is not obvious from the
definition of the bits involved. Refer to the section
on Programming Notes for descriptions of these
special modes.
The following table contains bit direction definitions.
20-10
11/19/91
Meaning
R
indicates that the bit is read only
W
indicates that the bit is write only
RIW
indicates that the bit may be written and read
RIC
indicates that the bit may be read
and cleared by writing a one to
that bit
C
indicates that the bit may be
cleared by writing a one to that bit
WD10C01A
PROGRAMMING REFERENCE
6.3
CONFIGURATION GROUP
The configuration group is used to do initial set up
of ports and clocks, handle interrupts, and set up
the control store memory.
6.3.1
OSCDlV
CLKDIV
OSC
CPUCLK
0
0
XTAU2
XTAU6
0
1
XTAU2
XTAU4
1
0
XTAL
XTAU3
1
1
XTAL
XTAU2
SRESET - Set Hardware Reset
Register (00)
Bits 7-1 are cleared to zero by reset. Bit 0 is set to
one by an external reset. When writing one to
SRST, any data on bits 7-1 are lost.
REGISTER
BIT
DlR
DEFINITION
00
7
W
CLKDIV: CPUCLK divisor (see Note 1 below)
00
6
W
OSCDIV: OSC divisor (see Note 1 below)
00
5
W
Unused.
00
4
W
Unused.
00
3
W
Unused.
00
2
W
REQTIM: buffer request timing. When this bit is one, REQA
is set at the same time that the internal buffer data holding
register is ready. When this bit is zero, REQA occurs one
RRCLK period early. This aids in interfacing to certain buffer circuits that have a lag in their response times.
00
1
W
ID3$4: select ID address size (see Note 2)
00
0
W
SRST: hardware reset. This bit is set by an external reset
on the RST input, or can be set by writing one to this bit.
This bit must be set to zero before operating the
WD1 OC01 A, or before setting any of the other bits in this
register or any other register.
TABLE 6-2. SRESET - SET HARDWARE REGISTER (00)
NOTE 1: The CPUCLK dividers are prescaled by
the OSC dividers, as shown in the table below
(XTAL is the clock generated by a crystal at X1
and X2):
NOTE 2: The eight ID register bytes are split into
two fields: the first four are address, and auto-increment for each sector; and the second four are
flag bytes which do not increment. The I D3$4 bit
selects whether 3 or 4 bytes of I D address bytes
will be used in the ID field. In 3 byte address
fields, register 100 is ignored. See Table 6-2A.
Two other considerations:
• CPUCLK = XTAU3 will not be a 50% duty
cycle unless XTAL is also a 50% duty cycle
clock.
• When resetting the WD10C01A under CPU
control, and the CPU is clocked by CPUCLK or
OSC, set CPUDIV and OSCDIV back to zero
before setting SRST. If this is not done, the
clocks could glitch and cause the CPU to fail.
11/19/91
20-11
WD10C01A
103$4
PROGRAMMING REFERENCE
Address Counter Size
First Reg ister In Field
0
4 bytes
100
1
3 bytes
101 (100 not used)
TABLE 6-2A. 10 REGISTER SELECTION
6.3.2
SISR - Interrupt Status Register (01)
The interrupt status register is designed to be
used in interrupt or polled mode. The status is not
affected by the interrupt mask register (see
below). The interrupting condition has precedence
over the CPU clear, which is performed by writing
a one to the selected interrupt bit. If the condition
still exists, the clear will not be successful. The
COMPLT and FAULT intArrupts will stay set until
the cause of the interrupt goes away. The IDFULL, DXFER, SECEND, and SM$IX interrupts
are generated by single bit time pulses that are
triggered by the leading edge of the interrupt
cause, and can therefore be cleared immediately.
SEOSTP is a direct status signal and is cleared
when the sequencer is executing a command.
Before checking any bit (except SEOSTP), it
should be cleared by writing a one to it. This
register is not affected by reset.
REGISTER
BIT
DIR
DEFINITION
01
7
R
GINT - group interrupt. This is the state of the INT output, which is
the logical OR of all of the enabled (by SIMR, see below) interrupt
sources in this register.
01
6
RIC
IDFULL - ID registers full. This interrupt is set at the end of any ID
field access by the transition of the control store ID bit from true to
false. This interrupt should be serviced before the next ID field is
accessed. This interrupt can be cleared immediately.
01
5
RIC
DXFER - data transfer started. This interrupt is set at the start of
the data field by the transition of the control store BUFF or NOXFER bit from false to true. This interrupt can be used to determine
when it is safe to write to the LOOP, SKIP, SECCNT, or ID
registers, if necessary. This interrupt can be cleared immediately.
01
4
RIC
COMPLT - complete. This interrupt is set in response to the COMPLT input pin going true. This interrupt cannot be cleared until the
COMPLT input pin goes false.
01
3
R
SEOSTP - sequencer stopped. This interrupt is set when the sequencer has stopped executing a command. This interrupt is
cleared when the sequencer starts a new command.
01
2
RIC
SECEND - sector end interrupt. This interrupt is set by the leading
edge of the LAST bit in the control store (see below). This is used
to signal the end of a sector for buffer management and other
overhead processing. The size of the field in which the LAST bit is
set can be adjusted to match the processing overhead to the end
of the sector for maximum CPU performance; the minimum size
for this field is two bytes. This interrupt can be cleared immediately.
01
1
RIC
SM$IX - sector mark or index passed. This interrupt is set by the
leading edge of the SECTOR or INDEX input going true, as
selected by the mask in the sequencer control register (SEOCTL).
RRCLK must be present for this interrupt to function. This interrupt
can be cleared immediately.
TABLE 6-3. SISR - INTERRUPT STATUS REGISTER
20-12
11/19/91
WD10C01A
PROGRAMMING REFERENCE
REGISTER
BIT
DIR
DEFINITION
01
0
RIC
FAULT - drive fault. This interrupt is set in response to the DRVFLT
input pin going true. This interrupt cannot be cleared until the
DRVFLT input pin goes false.
TABLE 6-3. SISR - INTERRUPT STATUS REGISTER (CONTINUED)
6.3.3
SIMR - Interrupt Mask Register (02)
The interrupts listed are described in the SISR
description. Writing a one to the mask bit enables
the interrupt. The state of the mask bits does not
affect the reading of status in SISR in any way. _
This register is cleared to zero by reset (interrupts _
disabled). Disabling GINT overrides any other
enables set in this register.
REGISTER
BIT
DIR
DEFINITION
02
02
02
02
02
02
02
02
7
RIW
GINT - enable all interrupts
6
RIW
IDFULL - enable IDFULL interrupt
5
RIW
DXFER - enable DXFER interrupt
4
RIW
COMPLT - enable COMPLT interrupt
3
2
1
0
RIW
SEOSTP - enable SEOSTP interrupt
RIW
SECEND - enable SECEND interrupt
RIW
SM$IX - enable SM$IX interrupt
RIW
FAULT - enable FAULT interrupt
TABLE 6-4. SIMR - INTERRUPT MASK REGISTER
11/19/91
20-13
WD10C01A
6.3.4
PROGRAMMING REFERENCE
SEQSTS - Sequencer Status (03)
The following status bits are further clarified in
later registers and sections. These bits can be
used to check what sequencer operation is taking
place.
REGISTER
BIT
DIR
DEFINITION
03
7
R
OATFLO - data field active. This bit means that the either
the BUFF or the NOXFER bit is now active from the control
store.
03
6
R
EGGEN - checksum calculation active. The W01 OG01 A is
now calculating the checksum. This status line usually encompasses the 10 or data field and checksum bytes, and is
active during both read and write.
03
5
R
LAST - The LAST bit is now active from the control store.
03
4
R
10 - The 10 bit is now active from the control store.
03
3
R
GHK - The GHK bit is now active from the control store.
The W01 OG01 is now processing the checkbytes or
syndromes for the GRG or EGG.
03
2
R
WAIT - The wait sequencer is waiting for an event such as
index, sector mark, address mark, or byte sync.
03
1
R
AMOET - Address mark detect. This is the raw AMOET pin
input. This pin can be used as an extra input bit in designs
(such as ST506) that do not require this function.
03
0
R
SEOOUT - The SEOOUT bit is now active from the control
store.
TABLE 6-5. SEQSTS - SEQUENCER STATUS REGISTER
20-14
11/19/91
WD10C01A
PROGRAMMING REFERENCE
6.3.5
PVC - PORT V Configuration (03)
This port is used to configure each port V bit for
input or output. This register is cleared to zero by
REGISTER
BIT
03
3
03
2
03
1
03
0
DIR
W
W
W
W
reset, which causes all port Y pins to become
inputs.
DEANITION
PY3DIR - bit 3 direction: 0 = in; 1 = out
•
PY2DIR - bit 2 direction: 0 = in; 1 = out
PY1 DIR - bit 1 direction: 0 = in; 1 = out
PYODIR - bit 0 direction: 0 = in; 1 = out
TABLE 6-6. PVC - PORT V CONFIGURATION (03)
11/19/91
20-15
WD10C01A
6.3.6
PROGRAMMING REFERENCE
Control Store Windows
The heart of the WD10C01A is its control store
memory, which is organized as 32 instruction
words of 28 bits each. Each 28 bit instruction is
divided into three 8 bit parts: the control byte, the
value byte, and the count byte; and one 4 bit part:
the error control byte. The window registers are
used to access these bytes. The control store address is specified by writing to the START
register. Any write to a control store window
register causes the START register to automatically increment to the next address to facilitate
loading.
The contents of the control store are not affected
by reset.
6.3.6.1
CSERR - Control Store Error Control
Byte Window (04)
The transition of DAC from false to true, together
with WG (in the control byte of the control store)
or RCMP (read compare enable in the SEQCTL
register), causes a one byte prefetch from the
buffer. If an immediate fill character is used to
specify the format data field or read compare byte
(see below), and DAC is used to select the ECC
.tor the data field, prefetch REQA signals are
generated anyway.
REGISTER
BIT
DIR
DEFINITION
04
3
RIW
FAIL - Enable error failure. Setting this bit to one causes a
command stop if an error is detected while executing the
current control store instruction. The error can be
CRC/ECC error, data miscompare error or a parity error
during write operation.
04
2
RIW
RTY - Enable read error retry. This bit is valid only during
read. Setting this bit to one causes a sector retry (see
below) if a read error is detected while executing the current control store instruction. An example of the use of this
bit is to cause a retry on an ID field miscompare.
04
1
RIW
DAC - Data field active. Set this bit to one when the current
control store instruction involves a data field operation.
This signal is used to select the data field checksum (RSECC) and to control data prefetch. When this bit is zero an
ID field operation is assumed, and the ID field checksum
(CRC) is selected.
04
0
RIW
SEQOUT - user defined output. This is tied to the
SEQOUT output pin through some delays which align the
signal to the byte boundary of the read or write serial data.
This output can be used to control an external ECC circuit,
such as a Reed-Solomon code circuit.
TABLE 6-7. CSERR-CONTROL STORE ERROR CONTROL BYTE WINDOW
20-16
11/19/91
WD10C01A
PROGRAMMING REFERENCE
6.3.6.2
CSCTL - Control Store Control Byte
Window (05)
REGISTER
BIT
DIR
DEFINITION
05
7
RIW
SVSEL - value byte select. This bit selects the use of the
value byte, which can be either immediate data (SVSEL =
0) or a select for data source or destination (SVSEL = 1).
05
6
RIW
CWSEL - count byte select. The bit selects the use of the
count byte, which can be either an immediate byte count
(CWSEL = 0) or to specify an external condition to wait for
(CWSEL= 1).
05
5
RIW
WG - write gate output. This is tied directly to the WG output pin.
05
4
RIW
RG - read gate output. This is tied to the retry logic, which
is then tied to the RG output pin.
05
3
RIW
AM - address mark enable output. This is tied to the AMC
register (see below) which generates the AMENA signal.
05
2
RIW
CMPEN - compare enable. This signal is used to indicate
that the bytes of the currently selected data source are to
be compared with incoming serial data (ID, marker bytes,
buffer data).
05
1
RIW
SKPEN - jump to SKIP address at end of the current instruction. This causes an absolute jump to the SKIP
register address when the current control store instruction
is finished. Typically, this is used to set up a read and write
program in the control store with a common ID search
routine. (See later examples and SKIP register definition.)
05
0
RIW
JMPEN - jump to LOOP address at end of the current instruction. This causes a conditional jump to the LOOP
register if the sector count (SECCNT) is not zero. If SECCNT is zero, the next sequential instruction is executed.
Typically, this is used to specify the end of a sector, and
tells the sequencer to go to the LOOP register address to
operate on the next sector.
TABLE 6-8. CSCTL - CONTROL STORE BYTE WINDOW (05)
11119/91
20-17
..
WD10C01A
6.3.6.3
PROGRAMMING REFERENCE
CSVAL - Control Store Value Byte
Window (06)
The use of the value byte depends on the state of
the SVSEL bit of the control byte. When SVSEL is
zero, the value byte specifies actual immediate
data, like address mark, gap, and PLL sync bytes.
When SVSEL is one, the value byte becomes an
encoded bit field that enables the correct data
source or destination. Both uses are shown
below.
REGISTER
BIT
DIR
06
7-0
RIW
I
I
To get large sector sizes, multiple control store
instructions are used. For example, for a 1024
byte sector size, use four instructions with 256
byte count fields. With this scheme, the last instruction must be flagged for error correction and
write prefetch purposes. The LAST bit must be set
with the BUFF or NOXFER bit to ensure proper
operation.
DEFINITION
VALUE7-0 (actual value for field)
TABLE 6-9. SVSEL of CONTROL BYTE ZERO
20-18
11/19/91
I
I
WD10C01A
PROGRAMMING REFERENCE
REGISTER
BIT
DlR
DEFINITION
06
7
RIW
BUFF - data buffer. This bit causes data to be transferred
to (disk read) or from (disk write or read compare) the disk
data buffer. The leading edge of BUFF causes a decrement of the SECCNT register, and increments the 10 write
register counters (see below).
06
6
RIW
NOXFER - no data transfer. This bit is used when an
ECC/CRC verify on the data field with no buffer data transfer is being performed. This bit is set INSTEAD of the
BUFF bit, and affects the SECCNT and 10 registers in the
same way as the BUFF bit.
06
5
RIW
LAST - last data buffer xfer control store instruction. Long
data fields (greater than 256 bytes) are specified by using
multiple control store instructions (2 for 512 bytes, 4 for
1024 bytes, etc.). When the control store instruction is the
last instruction of the data field specifiers, the LAST bit
must be set to flag this. This only applies to data buffer
transfers. LAST is set in ADDITION to BUFF or NOXFER.
The CSCNT byte must be set to at least 01 when this bit is
used.
06
4
RIW
R/W 10 - 10 registers. On 10 read, the incoming 10 field
from the disk is compared against the 10 write registers
and written at the same time to the 10 read registers. On
write (format), the data source is the 10 write registers.
06
3
RIW
CHK - checksum field. On read, this starts the check for a
correct checksum. On write, this causes the checksum
shift register to be gated into the NRZO data. In either
case, the calculation is halted at the end of this instruction.
The DAC bit in CSERR window selects the appropriate
checksum automatically.
TABLE 6-10. SVEL of CONTROL BYTE ONE
11119191
20-19
II
WD10C01A
6.3.6.4
PROGRAMMING REFERENCE
CSCNT· Control Store Count Byte
Window (07)
specifies a condition to wait for before proceding.
Both uses are shown below.
The use of the count byte depends on the state of
the CWSEL bit of the control byte. When CWSEL
is zero, the count byte specifies the actual length
of that field in bytes. When CWSEL is one, the
count byte becomes an encoded bit field that
The count value is set to the actual number of
bytes to do minus one. Therefore, 00 denotes a
one byte field, and FF a 256 byte field.
REGISTER
DEFINITION
07
COUNT7-0 (actual size of field - 1)
TABLE 6·11. CWSEL of CONTROL BYTE ZERO
REGISTER
BIT
DIR
DEFINITION
07
7
R/W
WDAM - Wait for data address mark (ST412 ONLY). This
bit causes the WD1 OC01A to pause until a data address
mark is detected at the AMDET input. Bits 6-0 specify a
timeout count that is the maximum number of byte times
from the end of the ID field to the data address mark. The
value field is used to specify the data pattern to compare
against for byte sync.
07
6
R/W
WIAM - Wait for ID address mark (ST412 ONLY). This bit
causes the WD1 OC01 A to pause until an ID address mark
is detected at the AMDET input. The value field is used to
specify the data pattern to compare against for byte sync.
07
5
R/W
WIX - Wait for index. Pauses until index is detected at the
INDEX input.
07
4
R/W
WSM - Wait for sector mark. Pauses until sector mark is
detected at the SECTOR input.
07
0
R/W
STOP - Stop immediate. This bit causes the command sequencer to immediately turn off all control outputs and
return to the stopped state.
TABLE 6·12. CWSEL of CONTROL BYTE ONE
20-20
11119191
WD10C01A
PROGRAMMING REFERENCE
6.3.6.5 Wait Condition Sequences
WIAM:
The following sequences are performed on the
above wait conditions to ensure proper error handling:
Wait for AMDET. Since 10 address marks
could be found anywhere, there is no byte
count, and the CPU must perform its own
timeout. However, after AMDET is
detected, the sequencer waits sixteen bit
times for the sync byte in the value byte to
be matched. The bit counter is decremented on each bit while the AMDET signal is active. If this bit count is exceeded
this is considered a sync error, and (if th~
control store RTY bit is set) a retry is performed (10 retry is discussed in a later
section). Checksum calculation starts
when the sync byte is detected, and the
sync byte is included in the calculation.
WDAM:
Wait for AMDET. If the byte count is exceeded, a sync error is recorded, and (if
the control store FAIL bit is set) the command halts. When AMDET is detected
correctly, the sequencer waits sixteen bit
times for the sync byte in the value byte to
be matched. The bit counter is decremented on each bit while the AMDET signal is active. If this bit count is exceeded
this is also a sync error. When a syn~
error occurs, the sequencer will stop or
retry as defined by the control store FAIL
and RTY bits. Checksum calculation starts
when the sync byte is detected, and the
sync byte is included in the calculation.
WIXandWSM:
11/19/91
The signal (index or sector mark) is waited
on forever. The CPU must perform its own
timeout and issue the KILL bit to the
SEQCTL register to stop the command
(see below). To do a wait for either index
or sector mark (typical on hard sector
drives), set both WIX and WSM.
20-21
II
WD10C01A
6.4
PROGRAMMING REFERENCE
DEVICE CONTROL GROUP
The device control group is used to set and read
port X, Y, and Z bits for drive control. It is also
used to execute data transfer commands with the
sequencer, and correct ECC errors.
6.4.1
PORTX - PORTX Output Bits (08)
This register is cleared to zero by reset. The state
of the output bits may be read back, allowing for
read/modify/write operation.
REGISTER
DEFINITION
08
PX7-0 (direct to output pins)
TABLE 6-13. PORTX OUTPUT BITS (08)
6.4.2
PORTY - PORT Y I/O Bits (09)
The direction of each bit is controlled by the Port
Y Control Register (03). If a particular bit is set for
input, then the state of the external pin is read by
a read of this port. If the bit is set for output, then
the last state written to that bit is read (same as
Port X). Writing to this register does not affect bits
configured for input. Reset sets all bits to input,
but does not affect the output latched data.
REGISTER
DEFINITION
09
6.4.3
I
I
PORTZ - PORT Z INPUT BITS (OA)
REGISTER
OA
I
I
BIT
5-0
I
I
DIR
DEFINITION
R
PZ5-0 (direct from input pins)
TABLE 6-15. PORTZ INPUT BITS (OA)
20-22
11/19/91
WD10C01A
PROGRAMMING REFERENCE
6.4.4
AMC - Address Mark Control (OA)
The AMC register defines during which bit times
the AMENA signal is active. When AM is set in the
control store control byte of the current instruction,
the AMENA signal will be active during the bit
times specified in this register. This register is not
affected by reset. Note that the bits in this register
are ordered backwards from the data bus numbering; i.e., writing 01 to this register will turn on
AMENA when bit 7 of the serial data stream is
active on NRZO.
,-------,-----.-----.-------a
REGISTER
OA
DEFINITION
W
Address mark bit control bit 0-7
TABLE 6-16. AMC - ADDRESS MARK CONTROL (OA)
11/19/91
20-23
WD10C01A
6.4.5
PROGRAMMING REFERENCE
SEQCTL - Sequencer Control Register
(OB)
REGISTER
BIT
DIR
DEFINITION
08
7
W
RGERLY - read gate early bit. This bit controls the timing
of RG signal. If the bit is set to zero, the RG signal is extended automatically until the ECC/CRC calculation is
finished. Setting this bit to one will disable this feature.
08
3
W
IXMASK - index interrupt mask. This bit is used with the
SMMASK bit to select the conditions for the SM$IX interrupt (see table below).
08
2
W
SMMASK - sector mark interrupt mask (see table below).
08
1
W
RCMP - enable read compare. This bit MUST be set when
performing a read data compare command with the data
buffer. It is used to change the buffer access from write buffer to read buffer.
08
0
W
KILL - immediately kill the currently executing command.
The sequencer will stop within three byte times. This bit
must be asserted for at least 2 bytes time.
08
5
R
ECCERR - checksum error. An ECC or CRC error has
been detected. This bit is valid when the sequencer is
stopped. If the control bit IGNERR in ECCCTL is turned on,
this status bit will always be zero and the sequencer will
continue its operation ignoring the error condition.
08
4
R
10ERR - 10 checksum error. A CRC 10 field error occurred
during the previous 10 field read. This condition is latched
when a checksum error causes an 10 retry, and is cleared
at the start of the next 10 field read (10 false to true transition).
08
3
R
PTYERR - parity error. A parity error during a transfer from
the data buffer to the W01 OC01A occurred during the previous command. If FAIL bit is set in the current CS instruction, the sequencer will stop its operation at the end of current instruction and WG output will be deasserted. This bit
is valid only after the sequencer is stopped.
08
2
R
SYNCER - sync search error. The search for a data field
marker byte or sync byte failed. This bit is valid when the
sequencer is stopped.
08
1
R
CMPERR - compare data error. A field that was compared
against some specified data source compared incorrectly.
This bit is valid when the sequencer is stopped.
TABLE 6-17. SEQCTL - SEQUENCER CONTROL REGISTER (08)
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PROGRAMMING REFERENCE
This register is not affected by reset. The IXMASK
and SMMASK select the conditions for the SM$IX
interrupt. Note that these mask bits are used to
select only the source, and do not affect or enable
the external interrupt signal. The table below
defines the use of the SM$IX source mask bits:
SMMASK
IXMASK
SM$IX set true on
leading edge of:
0
0
nothing
0
1
INDEX
1
0
SECTOR
1
1
INDEX OR SECTOR
6.4.6
transition times. Reading the counter
when the sequencer is stopped indicates
where in the control store the condition
causing the last halt occurred. This can be
used to determine in which instruction an
EGC or other fatal error occurred.
3. The START register is used to specify the
current address for control store window
access. See control store windows above.
The control store address counter is automatically incremented after any write to a
control store window register (CSERR,
CSCTL, CSVAL, or CSCNT).
4. Writing to the START register clears error
conditions. When a read error occurs,
causing the command to halt (see FAIL bit
in CSERR above), the error status is
latched in the SEQCTL register. A write to
the START register clears EGCERR, 10E14E, CERR, EERR, SYNCER, CMPERR,
and also PTYERR (which does not cause
a halt). This must be performed prior to
issuing any new commands. If SECCNT is
non-zero, the sequencer will start as soon
as the error is cleared.
START - Sequencer Start Address (OC)
The START register is not affected by reset. This
register is actually two devices: the START holding register, and the control store address counter.
When the CPU writes to this port, the data bus
value is latched into both the holding register and
the address counter. The holding register is affected only by CPU writes, but the counter is incremented or reloaded by several different
events. The START register is used for the following functions:
1. The START register specifies the starting
address in the control store for the program loaded there. When the CPU writes
to the SECCNT register (see below), and
the sequencer is stopped, the sequencer
loads the contents of the holding register
into the address counter and starts with
the instruction at that location.
While the sequencer is running, the control store
address counter is the program counter, and
points at the current instruction being executed.
The address in the counter can be changed by
the following events during program execution:
2. Reading this port gives the current contents of the control store address counter.
Reading the counter while the sequencer
is running indicates which control store instruction is currently being executed. It is
recommended that the CPU 'debounce'
this port by reading the START register
until the same value is read twice. This
prevents erroneous values being read at
REGISTER
BIT
OC
4-0
I
DIR
1 R/W
1. At the end of an instruction that has the
SKPEN bit set, the address counter is
loaded with the contents of the SKIP
register.
2. At the end of an instruction that has the
JMPEN bit set, if the SECCNT register is
not zero (Le., more sectors to do), the address counter is loaded with the contents
of the LOOP register. If SECCNT is zero,
the address counter is incremented and
the next sequential instruction is executed.
1 DEFINITION
1 START4-0
TABLE 6-18. START - SEQUENCER START ADDRESS (OC)
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WD10C01A
PROGRAMMING REFERENCE
3. If an instruction has the RTY bit set, and
an error flag is currently set (ECCERR,
CMPERR, or SYNCER), a retry occurs
and the address counter is loaded with the
contents of the LOOP register.
4. If a program halts due the STOP bit being
set (i.e., the normal end of the program
with SECCNT zero), and the CPU writes
to the SECCNT register with more blocks
to do before it detects the stopped condition, the sequencer will restart using the
current value of the START holding
register. This prevents erroneous restarts
from occurring.
6_4.7
LOOP - Sequencer Loop Address (OD)
The LOOP register specifies the address to set
the START value to at the end of a control store
instruction that has the JMPEN bit set in the control byte. This also happens when an 10 retry occurs (see below). The use of the LOOP register is
based on the idea that all sector operations are
sequential in nature, and that when the operation
is complete, a single jump back to the start of the
sequential sector operation is all that is needed.
This register is not affected by reset.
5. In all other cases, the control store address
counter is incremented and the next sequential instruction is executed.
r REGISTER
r
00
I
I
BIT
DIR
DEANITION
4-0
W
LOOP4-0 (address to loop to in loop)
TABLE 6-19. LOOP - SEQUENCER LOOP ADDRESS (OD)
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PROGRAMMING REFERENCE
6.4.8
ECCCTL - Error Correction Control
Register (OE)
CRCSET and ECCCLR must be set high and
then low to complete the preset or clear operation.
All bits in this register are cleared to zero upon
reset time.
REGISTER
BIT
DIR
DEFINITION
OE
5
W
ECCCLR - clear CRC and ECC shift register. Writing one
to this register causes the CRC and ECC shift register to
be held in the clear (all bits zero) state. The CPU must then
write zero to this bit to complete the clear pulse.
OE
4
W
CRCSET - preset CRC shift register. Writing one to this
register causes the CRC shift register to be held in the
preset (all bits one) state. The CPU must then write zero to
this bit to complete the preset pulse.
OE
3
W
CRCNIT - CRC shift register initial state. This bit selects
whether to start the CRC shift register with all zeros
(CRCNIT = 0) or all ones (CRCNIT = 1) when starting
checksum calculation.
OE
2
W
IGNERR - ignore CRC/ECC error. Forces ECCERR bit in
the SEOCTL register to zero, and causes the read error
logic to ignore this error by continuing with its operation.
The status bit EERR/CERR in the ECCS register is not affected by this control bit and will be set on error.
OE
1
W
DISPTY: disable parity checking. Setting this bit to one forces the PTYERR bit in the SEOCTL register to zero. Even
if the FAIL bit in the current CS instruction is set, the sequencer will continue its operation normally on parity error.
TABLE 6-20. ECCCTL - ERROR CORRECTION REGISTER (OE)
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WD10C01A
6.4.9
PROGRAMMING REFERENCE
SECCNT - Sector Count Register (OF)
The sector count register is used to specify the
number of iterations to perform the operation
programmed into the control store. Writing any
non-zero value to the SECCNT register causes
the sequencer to start, so therefore the range of
possible sector counts is from 1 to 255. Writing a
zero to SECCNT during the data field will cause
the sequencer to halt at the end of the current
sector. The sector count is automatically decre-
mented at the start of the data field, after the byte
sync or address mark character(s) have been
detected (leading edge of BUFF or NOXFER).
The SECCNT register can be written to at any
time except the start of the data field.
This register is cleared to zero by reset, or when
the KILL bit in the SEQCTL register is set. It is
NOT cleared by a halt on error, so that the sector
in error can be determined.
REGISTER
DEFINITION
OF
Sector count value
TABLE 6-21. SECCNT - SECTOR COUNT REGISTER (OF)
20-28
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WD10C01A
PROGRAMMING REFERENCE
6.4.10 ECCP- ECC Parameter Register (10)
REGISTER
BIT
DIR
DEFINITION
10
3
W
SYNGEGG - include sync byte in the EGG calculation. This
bit is initialized to one upon reset. If this control bit is set to
one, the EGG calculation begins with the first data sync
byte. Otherwise, the first data sync byte is excluded from
the EGG calculation.
10
2
W
WSYNGGRG - include sync byte in the GRG calculation.
This bit is initialized to one upon reset. If this control bit is
set to one, the GRG calculation begins with the first ID sync
byte. Otherwise, the first data sync byte is excluded from
the GRG calculation.
10
1
W
DEG6/S - RS EGG degree control bit. This bit is initialized
to zero upon reset. If this bit is set to zero, degree S polynomial is selected, otherwise degree 6 will be used.
10
0
W
WIFSS/3 - Interleave select. This bit is initialized to zero
upon reset. Setting this bit to one will select five way interleave format, otherwise three way format will be used.
TABLE 6-22. ECCP - ECC PARAMETER REGISTER (10)
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PROGRAMMING REFERENCE
6.4.11 ECCS· RS·ECC Status Register (11)
REGISTER
BIT
DIR
DEFINITION
11
6
R
EERR - EGG error detected. This bit is set whenever an
EGG error is detected in anyone of the interleaves. At least
one of the status bits 14E - 10E will also be set. This bit is
cleared to zero after reset and before another operation is
started. This bit is not affected by the control bit IGNERR,
which prevent the status EGGERR from being set.
11
5
R
GERR - GRG error detected. This status bit is set whenever
a GRG error is detected in the ID field. This bit is cleared
upon reset. The control bit IGNERR does not affect this
status bit.
11
4
RIW
14E - EGG error in interleave 4. This bit is set only when an
EGG error is detected in the interleave 4. The microprocessor can read the syndrome bytes from this interleave only
when this status bit is set. This status bit is cleared upon
reset. It also be cleared by writing a zero into this bit.
11
3
RIW
13E - EGG error in interleave 3. This bit is set only when an
EGG error is detected in the interleave 3. Jhe microprocessor can read the syndrome bytes from this interleave only
when this status bit is set. This status bit is cleared upon
reset. It also be cleared by writing a zero into this bit.
11
2
RIW
12E - EGG error in interleave 2. This bit is set only when an
EGG error is detected in the interleave 2. The microprocessor can read the syndrome bytes from this interleave only
when this status bit is set. This status bit is cleared upon
reset. It also be cleared by writing a zero into this bit.
11
1
RIW
11 E - EGG error in interleave 1. This bit is set only when an
EGG error is detected in the interleave 1. The microprocessor can read the syndrome bytes from this interleave only
when this status bit is set. This status bit is cleared upon
reset. It also be cleared by writing a zero into this bit.
11
0
RIW
10E - EGG error in interleave o. This bit is set only when an
EGC error is detected in the interleave O. The microprocessor can read the syndrome bytes from this interleave only
when this status bit is set. This status bit is cleared upon
reset. It also be cleared by writing a zero into this bit.
TABLE 6·23. ECCS· RS·ECC STATUS REGISTER (11)
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WD10C01A
PROGRAMMING REFERENCE
6.4.12 SPORT - Syndrome Port (12)
6.4.13 TEST - Test Register (16)
The microprocessor reads the syndrome bytes for
each interleave through this port. The WD10C01A
automatically transfers the syndromes of the next
interleave in error after all the syndromes in the
current interleave are read. The microprocessor
must read (interleave number * ECC degree)
times from this port to complete a syndrome
transfer from an interleave. The syndrome bytes
are transferred starting with the highest byte from
the lowest interleave number. Only the
syndromes from an interleave in error are transferred. If the microprocessor clears the error flag
from an interleave, the syndromes from that interleave cannot be read, but the content of the
syndrome registers are 110t destroyed. Those can
be read by reseting the error flag to one.
This register is intended for test purpose in the
manufacturing and must not be used in normal
operations. It is described here only for reference.
The syndrome bytes are valid only when sequencer is stopped. The syndrome registers are
cleared upon reset.
REGISTER
12
There are three test functions implemented in this
register. First, writing into this register with any
data, will set the OSC and CPUCLK outputs in a
predetermined state. During the write cycle, the
OSC output is set to 0 level and the CPUCLK
output is set to a 1 level.
Second, the microprocessor can write 080H into
this register to disable the output signal WG. This
signal will remain inactive until the microprocessor
writes a OOH into the register.
Third, the microprocessor can write OCOH into the
register to increment the ID registers. Subsequently, the microprocessor must write OOH,
before it can continue to increment the registers
again. The output WG is also disabled during the
test operation.
DEFINITION
R
SYNDR7-0 - Syndrome bit7-bitO.
TABLE 6-24. SPORT - SYNDROME PORT (12)
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WD10C01A
PROGRAMMING REFERENCE
6.4.14 SKIP - Skip Address Register (17)
This register is not affected by reset. The SKIP
register is used to perform an absolute jump to
the location specified at the completion of a control store instruction that has the SKPEN bit set to
one. This can typically be used to define whether
the current operation is to be a sector read or a
sector update write. Consider the following
generalized control store program that has three
parts: 10 search, read data field, and write data
field.
When the SKIP register is set to address 05, the
WD10C01A will perform a sector read operation.
When the SKIP register is set to address OC, the
WD10C01A will perform a sector write operation.
A more detailed example can be found in a subsequent section of this document.
REGISTER
BIT
DIR
DEFINITION
17
4-0
W
SKIP4-0
TABLE 6-25. SKIP - SKIP ADDRESS REGISTER (17)
ADDRESS
CONTROL STORE
OPERATION
00
10 SEARCH
01
10 SEARCH
02
10 SEARCH
03
10 SEARCH
04
10 SEARCH (SKPEN bit set)
05
READ DATA FIELD
06
READ DATA FIELD
07
READ DATA FIELD
08
READ DATA FIELD
09
READ DATA FIELD
OA
READ DATA FIELD
08
STOP
OC
WRITE DATA FIELD
00
WRITE DATA FIELD
OE
WRITE DATA FIELD
OF
WRITE DATA FIELD
10
WRITE DATA FIELD
11
WRITE DATA FIELD
12
STOP
TABLE 6-26. SKIP CONTROL STORE
EXAMPLE
20-32
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WD10C01A
PROGRAMMING REFERENCE
6.5
10 REGISTER GROUP
The eight 10 registers (100 - 107) are used to set
the 10 field during format and read/write operations. Writing to the 10 registers sets the field to
search for, or to write during format. These
registers are refered to as the 10 write registers.
The first four 10 write registers are set up as a
32-bit counter, and they automatically increment
at the start of the data field. The second four are
simple registers and are intended for use as flag
and defect indicators.
The 10 read registers contain the last 10 field read
from the media (valid when 10FULL in SISR is
true). These registers must be read when the sequencer is NOT reading an 10 field, or else the
CPU will not read the correct value .
REGISTER
BIT
OIR
DEFINITION
18
7-0
RIW
100 bits 7-0 (counter MSbyte)
TABLE 6-27.100 -10 REGISTER 0 (18)
REGISTER
BIT
19
7-0
I
DIR
T
RIW
I
I
DEFINITION
101 bits 7-0 (counter)
TABLE 6-28.101 -10 REGISTER 1 (19)
REGISTER
1A
I
I
BIT
DlR
DEFINITION
I
7-0
R/W
102 bits 7-0 (counter)
I
TABLE 6-29.102 -10 REGISTER 2 (1A)
REGISTER
BIT
DIR
DEFINITION
18
7-0
R/W
103 bits 7-0 (counter LSbyte)
TABLE 6-30. 103 - 10 REGISTER 3 (1 B)
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WD10C01A
PROGRAMMING REFERENCE
REGISTER
DEFINITION
1C
104 bits 7-0 (flag)
TABLE 6-31.104 -10 REGISTER 4 (1C)
REGISTER
BIT
DlR
DEFINITION
10
7-0
RIW
105 bits 7-0 (flag)
TABLE 6-32. 105 - 10 REGISTER 5 (1 D)
I
I
REGISTER
BIT
DIR
DEFINITION
1E
7-0
RIW
106 bits 7-0 (flag)
TABLE 6-33.106 -10 REGISTER 6 (1E)
REGISTER
BIT
DIR
DEFINITION
1E
7-0
RIW
107 bits 7-0 (flag)
TABLE 6-34. 107 - 10 REGISTER 7 (1 F)
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WD10C01A
PROGRAMMING REFERENCE
6.6
6.6.1
DEVICE PROGRAMMING
6.6.3
Initialization
There are a few 'tricks' in programming the
WD10C01A control store that are not indicated by
the discussions of the individual control bits:
1. Write one and then zero to the SRST bit of
the SRESET register to complete the
device reset sequence.
2. Write the remainder of the bits of the
SRESET register to the CPU and OSC
clock speeds, and ID counter size and
data request timing.
3.
CI~':lr
all interrupts that can be cleared by
writing OFFH to the SISR (some may still
be set because they are level true). Write
the initial mask to the SIMR.
Control Store Programming
READ BYTE SYNC
On formats that use a simple by1e sync byte (like
ESDI) for ID and data field markers, the search is
performed by setting the control byte bits RG and
CMPEN, and the count field is set with a maximum by1e timeout count. The condition of no byte
sync yet found, and RG * CMPEN set, defines
this mode. AMDET is not used and has no effect
on this operation. Checksum calculation starts
~~en the s~nc byte is detected, and the sync byte
IS Included In the calculation.
4. Configure port Y.
WRITE BYTE SYNC
5. Configure the address mark control bits
Write byte sync is used to mark the start of the
byte string for which the ECC/CRC checksum is
calculated. To do this, set WG and CMPEN in the
control byte. The start of the control store instruction with WG and CMPEN set clears the checksum register to the state defined by CRCNIT. The
transition to the next instruction begins the checksum calculation. For example, in a ST412 drive
the ID field might be defined by the byte string: A1
FE ID 10 10 FLAG ECC ECC ECC ECC; with PLL
sync before, and gap after. The control store instructions would be coded as follows.
using the AMC register.
6. Set up the ECC by programming the ECCCTL and ECCP registers. Set CRCNIT in
the ECCCTL register to the appropriate
value for a zero seed or a one's seed.
7. Load the control store program into the
control store.
6.6.2 Command Programming
1. Load the control store with the particular
instructions appropriate for the command
desired (format, read, write, etc.), if necessary.
2. Set the START, LOOP, and SKIP registers
to the appropriate values for the control
store program.
3. Write the number of sectors to do to SECCNT. This also starts the command sequencer.
4. Clear the interrupt status bits, and set the
mask.
5. Wait for SEQSTP. Check the SEQCTL and
ECCS status bits for an error.
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WD10C01A
PROGRAMMING REFERENCE
ADDRESS
DATA
COUNT
CONTROL
00
00
OB
WG,CMPEN
PLL sync field
01
A1
00
WG,AM
address mark
ERROR
02
FE
00
WG
address marker
03
10
02
WG,SVSEL
10 field
04
10
00
WG,SVSEL
flag byte
05
CHK
03
WG,SVSEL
checksum
06
00
03
WG
pad and splice
TABLE 6-35. WRITE BYTE SYNC EXAMPLE
In the example, control store instruction 00 contains the WG-CMPEN combination that says to
begin checksum calculation on instruction 01;
therefore, the bytes defined in instructions 01
through 05 are included in the checksum calculation. The calculation is terminated by the CHK
value code in instruction 05.
Rei Addr
DATA FIELD SIZES
03
Counts for
256
00
3F
01
02
512
1024
7F
FF
3F
7F
FF
3F
7F
FF
3F
7F
FF
TABLE 6-36. DATA FIELD SIZE EXAMPLE
The data field size is set by using multiple control
store instructions to build up the size in 256 (or
less) increments. Two issues come up with this
method:
1) The last data field instruction must be
marked to ensure correct buffer data
transfer timing and checksum calculation.
The LAST bit is used with the BUFF or
NOXFER bit to perform this marking.
2) For programming purposes, it is desirable
to not have to change the control store
significantly when changing sector size. To
do this, allocate enough control store instructions to be able to set the largest sector size to be supported. Then, adjust the
count fields in all of the instructions to get
the desired sector size. For example, if a
controller supports 256, 512, and 1024
byte sectors, use the programming shown
in the example below:
20-36
If the LAST bit is being used as an interrupt, the
last instruction can be split into two parts. The
second part contains the LAST bit, and can be
adjusted to the required time before the end of the
sector, since the leading edge of LAST generates
the interrupt.
ID SEARCH AND FLAG BYTES
When specifying an 10 field, it is desirable to have
address bytes that are compared on a search,
and flag bytes that are not. To do this, split the 10
field in the control store into two separate instructions for address and flag. When performing an 10
search, set the CMPEN bit only in the 10 address
instruction, and not in the 10 flag instruction.
DATA CHECKSUM VERIFY
To do a data field ECC or CRC verify only command, set the data field source as NOXFER. No
data will be transferred to the buffer.
11119191
WD10C01A
PROGRAMMING REFERENCE
DATA COMPARE VERIFY
6.6.4
To do a data field compare verify, set the RCMP
bit in the SEQCTL register, and set the CMPEN
bit in the data field control store instruction. Data
will be transferred from the data buffer and compared with the incoming disk data.
Programming Examples
This section gives programming examples for
ST412 format, read, and write commands. The
following design parameters are assumed:
1. The 10 field is three bytes of address, one
byte of flag, and two bytes of CRC.
FILL GAP TO END OF TRACK
2. Intersector gaps are 20 bytes of 04EH
data, PLL sync fields are 12 bytes of
OOOH.
To generate fill data through to the end of the
track during format, set the WIX bit in the la~t
control store instruction, and set WG and the fill
character. The WD10C01A will fill in gap bytes
until index occurs. This also works for gaps to
sector marks.
3. 10 address mark and marker byte are
OA 1FEH, data address mark and marker
byte are OA1F8H.
4. Data field is protected through degree six
ECC with interleave factor of five. There
are 30 bytes of checksum.
The WD10C01A registers are programmed as follows:
SRESET: 103$4 = 1 (3 bytes of address counter)
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WD10C01A
6.6.4.1
PROGRAMMING REFERENCE
Format Track Example
ADDRESS
VALUE
COUNT
CONTROL
NOTES
00
00
WIX
GWSEL
start on index
01
4E
13
WG
post index gap
02
00
DB
WG, GMPEN
PLL sync
03
A1
00
WG,AM
address mark
04
FE
00
WG
address mark
05
10
03
WG,SVSEL
10 address & flag
06
GHK
01
WG,SVSEL
GRG
07
00
02
WG
write splice
08
00
DB
WG, GMPEN
data PLL sync
09
A1
00
WG,AM,OAG
address mark
OA
F8
00
WG,OAG
address mark
DB
BUFF
7F
WG, SVSEL,OAG
data field
OG
BUFF
7F
WG, SVSEL,OAG
data field
00
BUFF
7F
WG, SVSEL,OAG
data field
data field
DE
BUFF, LAST
7F
WG, SVSEL,OAG
OF
GHK
10
WG, SVSEL,OAG
EGG
10
00
02
WG,JMPEN,OAG
write splice
11
4E
WIX
WG,GWSEL
pre-index gap
12
00
STOP
GWSEL
stop at end of
track
START = 00, LOOP
= 01, SKIP = NOT USED
TABLE 6·37. FORMAT TRACK EXAMPLE CONTROL STORE
Line by line discussion of Format Track Example:
00: This instruction just waits until the leading
edge of index. No writing is occurring. If there is
no index signal working on the drive, the GPU will
have to timeout and issue an abort. The OAG bit
is zero to select the checksum for the 10, as
specified by the SRESET register.
01: This instruction is the standard 4E gap from
index to the start of the first sector. This instruction is also the intersector gap, because after the
data field write splice on instruction 11 is written,
the W010G01A will jump to this address specified
by the LOOP register.
the start of the GRG calculation starting with instruction 03.
03: This is the first address mark byte for the 10
field. The AM bit generates AMENA with the AMG
register, suppressing the clock bit in the A 1 byte.
04: This is the second address mark byte, and is
treated as simple immediate data for format purposes.
05: This is the 10 address and flag field.
06: 10 GRG field. The count field is set to (2-1)
bytes for the 10 GRG. The end of this instruction
also stops the checksum calculation.
02: This instruction is the PLL sync field for the 10
field. The WG - GMPEN combination also marks
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WD10C01A
PROGRAMMING REFERENCE
07: 10 write splice and data PLL sync field. This
gap protects the end of the 10 field from the start
of the data field on later update write commands.
addressed by the LOOP register, in this case 01.
This happens only if SECCNT is not zero. If SECCNT is zero, the next control instruction is 11.
08: Data PLL sync field. The WG - CMPEN combination also marks the start of the ECC calculation starting with instruction OA. The DAC bit is set
here to select the data field checksum, and in this
case it also causes a one byte prefetch from the
buffer.
11: After the last sector, SECCNT is zero. After
instruction 10 is done, the next instruction will be
this one instead of instruction 01 (LOOP register).
This instruction writes the 4E gap until index.
09: This is the first address mark byte for the data
field. The AM bit generates AMENA with the AMC
register, suppressing the clock bit in the Ai byte.
12: The STOP bit causes the sequencer to shut
down immediately and turn off all external signals
(like WG, etc.).
The CPU performs the FORMAT TRACK command as follows:
OA: This is the second address mark byte, and is
treated as simple immediate data for format purposes.
OB·OD: These are the first three instructions that
define the sector data field. The data field is split
into four control instructions so that switching between sector sizes will not require reordering the
control store data (see above). The example
shows a 512 byte sector.
OE: The last instruction of the data field marks the
end of the data field using the LAST bit set with
BUFF.
OF: Data ECC field. ECC degree six with interleave factor of five is used, the count field is set to
(30-1) bytes. The end of this instruction also stops
the checksum calculation.
1. After setting up the control store and address registers as defined above, write the
total sectors per track to the SECCNT
register.
2. Write DXFER, FAULT, and SEQSTP true
to the SISR register to clear those status
bits, and to the SIMR register to enable
them.
3. Wait until GINT is true with a timeout in
case INDEX is not present on the interface. Check FAULT for error, and abort if
true. If DXFER goes true, update the 10
write registers with the next 10 field (when
using non-consecutive, i.e., not 1:1 interleave).
4. Repeat step 3 for all sectors on the track.
10: Data field write splice. This instruction pads
the end of the data field, making sure that the
checksum is not lost by the drive. The JMPEN bit
is also set in this instruction, meaning that the
next instruction to be accessed will be the one
11/19/91
5. After the last sector, wait for SEQSTP to be
true, indicating the end of the command.
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II
WD10C01A
PROGRAMMING REFERENCE
6.6.4.2 Read Sector Example
ADDRESS
VALUE
COUNT
CONTROL
NOTES
00
A1
WIAM
RG,CWSEL, RTY
address mark
search
01
FE
00
RG,CWSEL, RTY
ID marker byte
02
ID
02
RG, SVSEL,
CMPEN
ID address
03
ID
00
RG,SVSEL
ID flag
04
CHK
01
RG,SVSEL
CRC
05
00
03
RTY
allow ID retry
06
A1
WDAM (1F)
RG, CWSEL,
DAC, FAIL
address mark
search
07
F8
00
RG, CWSEL,
DAC, FAIL
data marker byte
08
BUFF
3F
RG, SVSEL, DAC
data field
09
BUFF
3F
RG, SVSEL, DAC
data field
OA
BUFF
3F
RG, SVSEL, DAC
data field
OB
BUFF, LAST
3F
RG, SVSEL,DAC
data field
OC
CHK
ID
RG, SVSEL,DAC
ECC
OD
00
02
JMPEN,DAC,
FAIL
end of sector
OE
00
STOP
WG, SVSEL,DAC
stop at end of
read
START = 00, LOOP
= 00, SKIP = NOT USED
TABLE 6-38. READ SECTOR EXAMPLE CONTROL STORE
Line by line discussion of Read Sector example:
00: This is the first instruction' of the read sector
command. The WIAM bit tells the WD10C01A to
search for an I D address mark byte. The
WD10C01A will not timeout, so the CPU will have
to abort after some period of time, if necessary.
The DAC bit is zero during the ID field to select
the ID checksum. The RTY bit is set so that if a
read error (in this case, no sync match after
AMDET true) occurs, a retry will be performed.
02: This is the ID address field. The CMPEN bit
causes a compare of the ID write registers with
the incoming ID field. The incoming ID is also
written to the ID read registers.
03: This is the ID flag field. This control store
instruction is separate from the ID address field
because the flag byte is not compared with the ID
write register. It is still written to the ID read
register.
04: ID CRC field. The count field is set to (2-1)
01: This tells the WD10C01A to verify the ID
marker byte. If it does not compare exactly, an ID
retry occurs (see below) because the RTY bit is
set.
bytes for the ID CRC. This instruction switches
the checksum shift register into check mode.
05: This instruction is both a pad over the write
splice and a check for an ID retry. The ID compare status and checksum error status are latched
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WD10C01A
PROGRAMMING REFERENCE
and held, and the RTY bit is now set, allowing the
checking of this status. An 10 retry occurs if the 10
did not match, or if there was a checksum error.
The checksum error is latched into the IDERR bit
for future reference. We waited until this instruction to check for an error so that the 10 read
registers could be loaded with this 10 field.
06: The WDAM bit tells the WD10C01A to look for
the data address mark. The (1 F) indicates the
byte count that is loaded into the byte count. This
value is the maximum number of byte times that
the WD1 OC01 A will look for the address mark.
This prevents locking up on a subsequent data
field address mark. An error here causes an immediate halt, with SYNCER set in the SEQCTL
register, because the FAIL bit is set.
07: This is the data marker byte. The CMPEN bit
indicates that the byte must compare exactly with
the immediate data byte. An error here causes an
immediate halt, with SYNCER set in the SEQCTL
register, because the FAIL bit is set.
00: The purpose of this instruction is to turn off
RG, resetting any external data decoder circuits.
The JMPEN bit is also set in this instruction,
meaning that the next instruction to be accessed
will be the one addressed by the LOOP register,
in this case 00. This happens only if the SECCNT
register is not zero. If SECCNT is zero, the next
instruction is 12. The FAIL bit is also set, causing
the checksum status to be checked, and if there
was an error, the command stops, with ECCERR
set in the SEQCTL register.
OE: After the last sector, the SECCNT register is
zero. After instruction 00 is done, the next instruction will be this one instead of instruction 00
(LOOP register). This instruction stops the command immediately.
The CPU performs the READ SECTOR command
as follows:
08-0A: These are the first three instructions that
define the sector data field. The data field is split
into four control instructions so that switching between sector sizes will not require rearranging the
control store data (see above). The example
shows a 256 byte sector. On ECC verify commands, change BUFF to NOXFER. On compare
verify commands, set BUFF, the CMPEN bit in the
control byte, and RCMP in the SEQCTL register.
OB: The last instruction of the data field marks the
end of the data field using the LAST bit set with
BUFF. LAST must be used for BUFF or NOXFER.
oc:
Data ECC field. ECC degree six with interleave factor of five is used, the count field is set to
(30-1) bytes. This instruction switches the checksum shift register into check mode.
11/19/91
1. After setting up the control store and address registers as defined above, write the
sector count to the SECCNT register to
start the transfer.
2. Write FAULT, IDFULL, and SEQSTP true
to the SISR register to clear those status
bits, and to the SIMR register to enable
them.
3. Wait until GINT is true with a timeout in
case INDEX is not present on the interface. Check FAULT for error, and abort if
true. If IDFULL is true, perform any checks
on the value in the 10 FIFO. If SEQSTP is
true, make sure that no error occurred that
must be serviced. Clear the status serviced.
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WD10C01A
PROGRAMMING REFERENCE
6.6.4.3 Write Sector Example
ADDRESS
VALUE
COUNT
CONTROL
NOTES
00
A1
WIAM
RG,CWSEL, RTY
address mark
search
01
FE
00
RG,CMPEN, RTY
10 marker byte
02
10
02
RG, SVSEL,
CMPEN
10 address
03
10
00
RG,SVSEL
10f/ag
04
CHK
01
RG,SVSEL
CRC
05
00
02
RTY
wait past splice
06
00
DB
WG, CMPEN,
OAC
PLLsync
07
A1
00
WG,AM,OAC
address mark
08
F8
00
WG,OAC
data marker byte
09
BUFF
FF
WG, SVSEL,OAC
data field
OA
BUFF
FF
WG, SVSEL,OAC
data field
DB
BUFF
FF
WG, SVSEL,OAC
data field
DC
BUFF, LAST
FF
WG, SVSEL,OAC
data field
00
CHK
10
WG, SVSEL,OAC
ECC
DE
00
02
WG,JMPEN,OAC
write splice
OF
00
STOP
CWSEL
stop at end of
cmd
START = 00, LOOP = 00, SKIP = NOT USED
TABLE 6-39. WRITE SECTOR EXAMPLE CONTROL STORE
Line by line discussion:
the incoming 10 field. The incoming 10 is also
written to the 10 read registers.
00: This is the first instruction of the write sector
command. The WIAM bit tells the W01 OC01A to
search for an 10 address mark byte. The
W010C01A will not timeout, so the CPU will have
to abort after it times out, if necessary. The OAC
bit is zero during the 10 field to select the 10
checksum. The RTY bit is set so that if a read
error (in this case, no sync match after AMOET
true) occurs, a retry will be performed.
03: This is the 10 flag field. This instruction is
01: This tells the W010C01A to verify the 10
marker byte. If it does not compare exactly, an 10
retry occurs (see below) because the RTY bit is
set.
05: This instruction spaces over the 10 field write
02: This is the 10 address field. The CMPEN bit
causes a compare of the 10 write registers with
20-42
separate from the 10 address field because the
flag byte is not compared with the 10 write
register. It is still written to the 10 read register.
04: 10 CRC field. The count field is set to (2-1)
bytes for the 10 CRC. This instruction switches
the checksum shift register into check mode.
splice to the start of the data field, protecting the
10 checksum in the process. This instruction also
performs a check for an 10 retry. The 10 compare
status and checksum error status are latched and
held, and the RTY bit is now set, allowing the
checking of this status. An 10 retry occurs if the 10
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PROGRAMMING REFERENCE
did not match, or if there was a checksum error.
The checksum error is latched into the IDERR bit
for future reference.
06: Data PLL sync field. This instruction is the
start of the update write sector data. The WG GMPEN combination also marks the start of the
EGG calculation starting with instruction 07.
07: This is the first address mark byte for the data
field. The AM bit generates AMENA with the AMG
register, suppressing the clock bit in the A 1 byte.
08: This is the data marker byte, and is treated as
is also set in this instruction, meaning that the
next instruction to be accessed will be the one
addressed by the LOOP register, in this case 00.
This happens only if the SECCNT register is not
zero. If SECCNT is zero, the next control instruction is OE.
OE: After the last sector, SECCNT is zero. After
instruction 11 is done, the next instruction will be
this one instead of instruction 00 (LOOP register).
This instruction stops the command immediately.
The CPU performs the WRITE SECTOR command as follows:
simple immediate data for write sector purposes.
09-0A: These are the first three instructions that
define the sector data field. The data field is split
into four control instructions so that switching between sector sizes will not require reordering the
control store data (see above). The example
shows a 1024 byte sector.
08: The last instruction of the data field marks the
end of the data field using the LAST bit set with
BUFF.
oc:
Data ECC field. ECC degree six with interleave factor of five is used, the count field is set to
(30-1) bytes. The end of this instruction also stops
the checksum calculation.
00: Data field write splice. This instruction pads
the end of the data field, making sure that the
checksum is not lost by the drive. The JMPEN bit
11/19/91
1. After setting up the control store and address registers as defined above, write the
sector count to the SECCNT register to
start the transfer.
2. Write IDFULL, FAULT, and SEOSTP true
to the SISR register to clear those status
bits, and to the SIMR register to enable
them.
3. Wait until GINT is true with a timeout in
case INDEX is not present on the interface. Check FAULT for error, and abort if
true. If IDFULL is true, perform any checks
on the data in the ID FIFO. If SEOSTP is
true, check to see if an error occurred that
must be serviced. Clear the status serviced.
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PROGRAMMING REFERENCE
6.6.4.4 Read and Write Sector Example
This example makes use of the SKIP register to
merge the read and write sector operations into
one control store program. Selection between
read and write is performed solely by changing
the contents of the SKIP register. The control
store example shown in the table below is divided
into the ID search, read data field, and write data
field sections.
ADDRESS
VALUE
COUNT
CONTROL
NOTES
00
A1
WIAM
RG,CWSEL, RTY
address mark search
01
FE
00
RG,CMPEN, RTY
ID marker byte
02
ID
02
RG, SVSEL, CMPEN
ID address
03
ID
00
RG,SVSEL
ID flag
04
CHK
01
RG,SVSEL
CRC
05
00
02
SKPEN,RTY
retry ID
08
00
00
00
wait past splice
09
A1
WDAM(1F)
RG,CWSEL;DAC,FAIL
address marker search
OA
F8
00
RG, SVSEL,DAC
data marker byte
DB
BUFF
3F
RG, SVSEL,DAC
data field
OC
BUFF
3F
RG, SVSEL,DAC
data field
OD
BUFF
3F
RG, SVSEL,DAC
data field
DE
BUFF,
LAST
3F
RG,SVSEL,DAC
data field
OF
CHK
10
RG,SVSEL,DAC
ECC
10
00
02
JMPEN,DAC, FAIL
end of sector
11
00
STOP
CWSEL
stop at end of read
14
00
OB
WG, CMPEN,DAC
PLLsync
15
A1
00
WG,AM,DAC
address mark
16
F8
00
WG, DAC
data marker byte
17
BUFF
FF
WG, SVSEL,DAC
data field
18
BUFF
FF
WG, SVSEL,DAC
data field
19
BUFF
FF
WG, SVSEL,DAC
data field
1A
BUFF,
LAST
FF
WG, SVSEL,DAC
data field
1B
CHK
10
WG, SVSEL,DAC
ECC
1C
00
02
WG,JMPEN,DAC
write splice
10
00
STOP
CWSEL
stop at end of cmd
START = 00, LOOP = 00, SKIP = 08 for read, 14 for write
TABLE 6-40. READ AND WRITE SECTOR EXAMPLE CONTROL STORE
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PROGRAMMING REFERENCE
Line by line discussion of Read and Write example:
00: This is the first instruction of the 10 search.
The WIAM bit tells the W010C01A to search for
an 10 address mark byte. The W010C01A will not
timeout, so the CPU will have to abort after it
times out, if necessary. The OAC bit is zero during
the 10 field to select the 10 checksum. The RTY
bit is set so that if a read error (in this case, no
sync match after AMOET true) occurs, a retry will
be performed.
01: This tells the WO 1OC01 A to verify the 10
marker byte. If it does not compare exactly, an 10
retry occurs (see below) because the RTY bit is
set.
02: This is the 10 address field. The CMPEN bit
causes a compare of the 10 write registers with
the incoming 10 field. The incoming 10 is also
written to the 10 read registers.
03: This is the 10 flag field. This instruction is
separate from the 10 address field because the
flag byte is not compared with the 10 write
register. It is still written to the 10 read register.
04: 10 CRC field. The count field is set to (2-1)
bytes for the 10 CRC. This instruction switches
the checksum shift register into check mode.
05: This instruction performs a check for an 10
retry. The 10 compare status and checksum error
status are latched and held, and the RTY bit is
now set, allowing the checking of this status. An
10 retry occurs if the ID did not match, or if there
was a checksum error. The checksum error is
latched into the 10ERR bit for future reference.
Also, the SKPEN bit is set, meaning the next address (assuming no errors occurred) will be the
value in the SKIP register, which is 08 for read
sector, and 14 for write sector.
READ DATA FIELD
08: This instruction spaces over the 10 field write
splice to the start of the data field, protecting the
10 checksum in the process.
09: The WOAM bit tells the W010C01A to look for
the data address mark. The (1 F) indicates the
byte count that is loaded into the byte count. This
value is the maximum number of byte times that
the W010C01A will look for the address mark.
This prevents locking up on a subsequent data
field address mark. An error here causes an immediate halt, with SYNCER set in the SEQCTL
register, because the FAIL bit is set.
OA: This is the data marker byte. The CMPEN bit
indicates that the byte must compare exactly with
the immediate data byte. An error here causes an
immediate halt, with SYNCER set in the SEQCTL
register, because the FAIL bit is set.
08-00: These are the first three instructions that
define the sector data field. The data field is split
into four instructions so that switching between
sector sizes will not require reordering the control
store data (see above). The example shows a 256
byte sector. On ECC verify commands, change
BUFF to NOXFER. On compare verify commands, set BUFF, the CMPEN bit in the control
byte, and RCMP in the SEQCTL register.
OE: The last instruction of the data field marks the
end of the data field using the LAST bit set with
BUFF. LAST must be used for BUFF or NOXFER.
OF: Data ECC field. ECC degree six with interleave factor of five is used, the count field is set to
(30-1) bytes. This instruction switches the checksum shift register into check mode.
10: The purpose of this instruction is to turn off
RG, resetting any external data decoder circuits.
The JMPEN bit is also set in this instruction,
meaning that the next instruction to be accessed
will be the one addressed by the LOOP register,
in this case 00. This happens only if the SECCNT
register is not zero. If SECCNT is zero, the next
control instruction is 11. The FAIL bit is also set,
causing the checksum status to be checked, and
if there was an error, the command stops, with
ECCERR set in the SEQCTL register.
11: After the last sector, the SECCNT register is
zero. After instruction 10 is done, the next instruction will be this one instead of instruction 00
(LOOP register). This instruction stops the command immediately.
WRITE DATA FIELD
14: Data PLL sync field. This instruction is the
start of the update write sector data. The WG CMPEN combination also marks the start of the
ECC calculation starting with instruction 15.
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PROGRAMMING REFERENCE
15: This is the first address mark byte for the data
field. The AM bit generates AMENA with the AMC
register, suppressing the clock bit in the A1 byte.
true. If IDFULL is true, perform any checks
on the data in the 10 FIFO. If SEQSTP is
true, check to see if an error occurred that
must be serviced. Clear the status serviced.
16: This is the data marker byte, and is treated as
simple immediate data for write sector purposes.
17-19: These are the first three instructions that
define the sector data field. The data field is split
into four instructions so that switching between
sector sizes will not require reordering the control
store data (see above). The example shows a
1024 byte sector.
The CPU performs the WRITE SECTOR command as follows:
1. After setting up the control store and address registers as defined above, write OF
to the SKIP register, and then write the
sector count to the SECCNT register to
start the transfer.
1A: The last instruction of the data field marks the
end of the data field using the LAST bit set with
BUFF.
2. Write IDFULL, FAULT, and SEQSTP true
to the SISR register to clear those status
bits, and to the SIMR register to enable
them.
18: Data ECC field. ECC degree six with interleave factor of five is used, the count field is set to
(30-1) bytes. The end of this instruction also stops
the checksum calculation.
1C: Data field write splice. This instruction pads
the end of the data field, making sure that the
checksum is not lost by the drive. The JMPEN bit
is also set in this instruction, meaning that the
next instruction to be accessed will be the one
addressed by the LOOP register, in this case 00.
This happens only if the SECCNT register is not
zero. If SECCNT is zero, the next control instruction is 10.
10: After the last sector, SECCNT is zero. After
instruction 1C is done, the next instruction will be
this one instead of instruction 00 (LOOP register).
This instruction stops the command immediately.
The CPU performs the READ SECTOR command
as follows:
1. After setting up the control store and address registers as defined above, write 06
to the SKIP register, and then write the
sector count to the SECCNT register to
start the transfer.
2. Write IDFULL, FAULT, and SEQSTP true
to the SISR register to clear those status
bits, and to the SIMR register to enable
them.
3. Wait until GINT is true with a timeout in
case INDEX is not present on the interface. Check FAULT for error, and abort if
20-46
3. Wait until GINT is true with a timeout in
case INDEX is not present on the interface. Check FAULT for error, and abort if
true. If IDFULL is true, perform any checks
on the data in the 10 FIFO. If SEQSTP is
true, check to see if an error occurred that
must be serviced. Clear the status serviced.
6.6.5
10 Retry and Error Conditions
The WD10C01A manages errors by using the
RTY and FAIL bits in the control store error control
byte. These bits tell the WD10C01A when to
check its internal error status bits, and what to do
about the error. All internal status bits in the
WD10C01A are held in their error state until reset
by a retry, or by writing to the START register.
If an error occurs when or before the RTY bit is
set, an 10 retry is performed. The LOOP register
address will be loaded into the control store address register, restarting the sector. Also, the RG
signal is switched false for one whole byte time to
reset external decoders/PLLs. If the control store
instruction at the LOOP address does not specify
that RG is true, then it will stay false.
If an error occurs when or before the FAIL bit is
set, an immediate abort of the command occurs
when FAIL goes true. The appropriate error status
bit(s) are set, and the sequencer stops.
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PROGRAMMING REFERENCE
The following list summarizes the read error conditions of the W010C01A:
1. When executing a WIAM or WOAM operation, and the AMOET signal goes true, but
the sync byte does not match within the
sixteen bit timeout period. SYNCER will
be set true if a halt is commanded (FAIL
set).
6.6.6
1. The SECCNT register contains a
remainder. If the error is an 10 error or a
sync error (SYNCER set), this is the num- •
ber of sectors to read including the one in
error. Any other error gives the number of
sectors to read after the one in error.
2. When searching for a simple byte sync
byte, and the count in the control store
count field is exhausted. SYNCER will be
set true if a halt is commanded (FAIL set).
2. The 10 set registers are set to an 10 field. If
the error is a sync error, this is the sector
address of the one in error. Any other error
gives the sector address following the o~e
in error. In general, any error that IS
detected after the data field transfer starts
(OXF went true, see the SEOSTS regist~r)
will cause SECCNT and the 10 wnte
registers to be set for the sector following
the one in error.
3. Once byte sync is established, any read
compare operations (CMPEN bit set) that
fail. In the case of immediate data, this
handles the ST412 second address mark
byte (FE or F8) and the SYNCER bit will
be true if a halt is commanded (FAIL set).
In all other cases (i.e., buffer or 10 data),
the CMPERR bit is be true if a halt is commanded (FAIL set).
4. Any checksum error. This error status is
retained by the 10ERR bit in the SEOCTL
register if a retry is commanded (RTY set)
until the next 10 field starts. The ECCERR
bit is set if an abort was commanded (FAIL
set). In this case, the checksum shift
register contains the correction syndrome.
The register ECCS shows the additional
ECC status.
5. When executing a WOAM operation, if the
AMOET signal does not go true, and the
count in the control store count field is exhausted. SYNCER will be set true if a halt
is commanded (FAIL set).
Error Recovery
When a read error occurs that causes a halt of the
command before it is completed, certain steps
must be performed to recover from that error.
When the sequencer stops, the following conditions are in effect:
3. The SEOCTL read bits define the error. If
ECCERR is set, then the error is a checksum error. If CMPERR is set, the error is a
verify or second address mark byte error.
If SYNCER is set, the error is a byte sync
error.
4. The internal checksum register may contain a correction syndrome, depending on
the type of error.
The SECCNT contains a non-zero remainder.
SECCNT is inhibited from restarting the sequencer by the latched error status. In orde~ to restart
for retry or continuing, the START register must
be written with the starting control store address.
This immediately clears any error status
(SEOCTL read bits), and if the SECCNT register
is still non-zero, will cause the sequencer to start.
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6.6.7 Error Correction
The Reed-Solomon EGG implemented in the
WD10G01A can correct up to 2 error bytes (dewee 5) and up to ~ error bytes (degree 6) per
Interleave. Depending on the interleave factor
being used, it can correct up to 30 bytes of error
within a sector.
During read operations, the device produces composite syndromes. These syndromes are used by
the error correction routine (microprocessor) to
calculate the error location and error value. The
microprocessor responses to the SEQSTP interrupt by first reading the SISR and the EGGS
registers to determine the type of failure. If the
EERR bit in the EGGS is set, the microprocessor
determines which interleaves are in error by read-
20-48
ing the status bits IOE-14E in the EGGS. The
microprocessor then start reading the SPORT
register to transfer the syndromes. The
WD1 OG01A automatically transfer the syndromes
from the lowest interleave number. The highest
byte is transferred first. The microprocessor has
to read the SPORT register five times for degree
5 and six times for degree 6 to complete the
syndrome transfer of an interleave. After all
syndromes of the interleave are transferred the
microprocessor must reset the correspon'ding
e~ror statu.s bit in the EGGS by writing a 0 into that
bit. The microprocessor can then continue reading
the syndromes of the next interleave.
11/19/91
WD10C01A
DC ELECTRICAL SPECIFICA TlONS
7.0
DC ELECTRICAL SPECIFICATIONS
7.1
MAXIMUM RATINGS
7.2
Ambient temperature
OOC to 70°C
Storage temperature
-65° C to 150° C
Voltage on any pin
with respect to Vss
-0.3 to VDD+0.3 Volts
Voltage on VDD with
respect to Vss
7 Volts
Leakage current
±10
Power dissipation
1000 mW
at Xi =32 MHz,
RRCLK=27 MHz,
OOC, all outputs open
Input Static
Discharge Protection
STANDARD TEST CONDITIONS
The characteristics below apply for the following
standard test conditions, unless otherwise noted.
All voltages are referenced to Vss (OV Ground).
Positive current flows into the referenced pin.
!1A
2000 V pin to pin
Operating temperature range
0° to 70° C
VDD supply voltage with
respect to Vss
+5 Volts ±
0.5 V
Vss
o Volts
Latch-up current (min)
±40mA
Operating humidity range
20 to 95%
Xi input operating frequency
with crystal
32 MHz{max)
8 MHz (min)
Xi input operating frequency
with TTL source
25 MHz{max)
--- MHz (min)
NOTE
Stresses above those listed under Maximum
Ratings may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational
section of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
11/19/91
20-49
..
WD10C01A
7.3
DC ELECTRICAL SPECIFICA TlONS
DC CHARACTERISTICS
SYMBOL PARAMETER
I
MIN
MAX
UNITS
CONDITIONS
VrH
Input High Voltage
2.0
---
V
Voo =5V ±5%
VrL
Input Low Voltage
---
O.S
V
Voo =5V ±5%
IrH
Input High Current
~
VrL= O.SV
IrL
Input Low Current
-----
600
-600
VOH
Output High Voltage
2.4
---
~
V
VrH = 2.0V
., IOH = -400 ~
VOL
Output Low Voltage
---
0.40
V
·,IOL= 2 mA
VOH
Output High Voltage
Voo-0.5
---
V
··,IOH = -SOO
VOL
Output Low Voltage
---
0.40
V
··,IOL=4mA
VOH
Output High Voltage
2.4
---
V
~
VOL
Output Low Voltage
---
0.40
V
···,IOH = -2.5 mA
•••• , IOL =6 mA
Cr
Input Capacitance
10
pF
all inputs
Co
Output Capacitance
-----
50
pF
All outputs except: 00-07,
BMOO-BM07,BMP, OSC, and
CPUCLK
Co
Output Capacitance
---
100
pF
Outputs 00-07,BMOO-BM07,
and BMP
Co
Output Capacitance
100
pF
Outputs OSC and CPUCLK
Icc
Supply Current
-----
200
mA
60 mA(typical); X1=32MHz,
RRCLK=27MHz, OOC, all outputs open, Voo=5V
TABLE 7-1. DC CHARACTERISTICS
NOTES:
Ta = OOC (32°F) to 70°C (15SoF),
Voo = +5V ±5%
• Output Voltages (all outputs except X2,
CPUCLK, OSC, 00-07), see t
*. Output Voltages (CPUCLK andOSC only),
seet
···Output Voltages (00-07), see t
····Output Voltages (00-07, INT Logic 0)
t Even under worst case AC transient switching
conditions VOL = O.SV shall not be exceeded on
any output pin at any time.
20-50
11/19/91
WD10C01A
AC OPERA TlNG CHARACTERISTICS
8.0
AC OPERATING CHARACTERISTICS
The following notes apply to all of the parameters
presented in this section:
1. All unit are in nanoseconds
2. These timing relationships assume the maximum capacitive loading for both inputs and outputs, VDD = 4.50 volts to 5.50 volts.
3. Temperature =
•
oOe to 70°C.
4. All timing is measured between 0.8 volts logic
low and 2.0 volts logic high, unless otherwise
noted.
8.1
x1
OSC AND CPUCLK TIMING
'-
I·
/
I·•
t1
.1
\
~
t3
t1
·1
•
t2
FIGURE 8-1. TTL SOURCE X1 CLOCK INPUT
/
ose "
I·•
I·
t4
.1
'\
Q
t8
t4
·1
t6
•
D
t8
FIGURE 8-2. OSC OUTPUT
11119191
20-51
WD10C01A
CPUCLK
AC OPERATING CHARACTERISTICS
" I·
•
/
I·
t5
.1
~
\
D-
ta
t5
·1
ta
•
t7
FIGURE 8-3. CPUCLK OUTPUT
The following table summarizes the relationship
between the clock at X1 and the resultant outputs
at OSC and CPUCLK. OSCDIV and CPUDIV are
control bits in the RESET register that determine
how the X1 clock is divided to produce OSC and
CPUCLK. See the programming section for more
information.
20-52
11119/91
OSCDIV
CLKDIV
OSC
CPUCLK
0
0
0
X1/2
X1/6
1
X1/2
X1/4
1
0
X1/1
X1/3
1
1
X1/1
X1/2
WD10C01A
AC OPERATING CHARACTERISTICS
No.
DESCRIPTION
MIN
MAX
UNITS
h
TIL source Xi high or 10w(*1)
13
ns
t2
TIL source Xi cycle time
40
ns
13
TIL source Xi rise or fall time (*1)
5
t4
OSC high or low when: (*2)
Xiii crystal (*3)
X1/2 crystal (*3)
Xiii TIL source (*5)
X1/2 TIL source (*4)
-----
t5
t6
t7
t8
ns
---
10
27
16
36
33
24
44
ns
ns
ns
ns
CPUCLK high or low when: (*2)
X1/2 crystal (*3)
X1/3 crystal (*3)
X1/4 crystal (*3)
X1/6 crystal (*3)
X1/2 TIL source (*4)
X1/3 TIL source (*5)
X1/4 TIL source (*4)
X1/6 TIL source (*4)
---
---
---
27
36
54
81
36
48
72
108
33
54
66
99
44
72
88
132
ns
ns
ns
ns
ns
ns
ns
ns
OSC cycle time when:
Xiii crystal (*3)
Xi 12 crystal (*3)
Xiii TIL source (*4)
X1/2 TIL source (*4)
---
---
---
30
60
40
80
125
250
ns
ns
ns
ns
CPUCLK cycle time when:
X1/2 crystal (*3)
X1/3 crystal (*3)
X1/4 crystal (*3)
X1/6 crystal (*3)
X1/2 TIL source (*4)
X1/3 TIL source (*4)
X1/4 TIL source (*4)
Xi/6 TIL source (*4)
60
90
120
180
80
120
160
240
CPUCLK and OSC rise or fall time (*2)
---
---
-----
---------
--ns
ns
ns
ns
ns
ns
ns
ns
5
ns
--250
375
500
750
TABLE 8-1. OSC AND CPUCLK TIMING PARAMETERS
NOTES:
*1)limes are measured relative to VIH and
VIL.
*2)High and low times are measured relative
to the midpoints between VOL and VOH.
Rise and fall times are measured between
VOH and VOL.
11119/91
*3)Assumes 33.3 MHz crystal across Xi and
X2 for min times, 8.0 MHz crystal for max
times.
*4)Assumes 25.0 MHz TTL source to Xi.
*5)Assumes 25.0 MHz TTL source to Xi,
50/50 duty cycle.
20-53
..
WD10C01A
8.2
AC OPERATING CHARACTERISTICS
CPU INTERFACE TIMING
AO-A4
~
Cs
X/
r-...
t 20
AD
,
•
"
,
t21
X
00-07
•
DATA
~I
EXTERNAL
INTERFACE
(inputs)
t22
I,
t 25
==><
VALID
,
t24
X
·1
•
input change
FIGURE 8·4. MICROPROCESSOR RD* TIMING (RD* CONTROLLED)
AO-A4
~
K:=
cs
I'
,
120
-
RO
•
•
•
"
•
00-07
121
X
~I
EXTERNAL
INTERFACE
(inputs)
122
I,
==><
125
•
DATA
VALID
,
124
X
·1
•
input change
FIGURE 8·5. MICROPROCESSOR RD* TIMING (CS* CONTROLLED)
20-54
11/19/91
WD10C01A
AC OPERATING CHARACTERISTICS
AO-A4
---..
X--
Cs
120
122
I
WR
..
•
"\
126
DBD-DB7
DATA
I 127
EXTERNAL
INTERFACE
(Outpul)
PREVIOUS DATA
VALID
X
,I
128
--:---!
129
X
I
NEW DATA
FIGURE 8·6. MICROPROCESSOR WR* TIMING (WR* CONTROLLED)
AD-A4
)
I
Cs
12Q
,
122
"\
I
WR
~
ADDRESS VALID
1 26
•
"-
DBD-DB7
DATA
I 127
-
X
VALID
I
128
·1
-129I
EXTERNAL
INTERFACE
(oulpul)
PREVIOUS DATA
X
NEW DATA
FIGURE 8·7. MICROPROCESSOR WR* TIMING (CS* CONTROLLED)
11/19/91
20-55
WD10C01A
RST
AC OPERATING CHARACTERISTICS
/
"
t30
«
EXTERNAL
INTERFACE
OUTPUTS
t31
«
·1
·1
><
undefined state
FIGURE 8·8. RESET TIMING
DRVFLT or
COMPLT
A
t32
INT
«
t33
l
'1
~
FIGURE 8·9. EXTERNALL V GENERATED INTERRUPT TIMING
20-56
11/19/91
reset state
WD10C01A
AC OPERATING CHARACTERISTICS
No.
MIN
DESCRIPTION
MAX
UNITS
20
ns
RE pulse width (*3)
100
ns
t22
RE or WE to address change (*3)
0
ns
t23
RE true to data valid (*3)
---
95
ns
t20
address valid to RE or WE (*3)
t21
t24
RE false to data hold (*3)
20
60
ns
t25
input port setup to RE true (*1)(*3)
80
-----
ns
t26
WE pulse width (*3)
100
t27
data setup to WE false (*3)
80
ns
ns
t28
WE false to data hold (*3)
0
ns
80
ns
---
ns
t29
WE false to output change (*2)(*3)
---
130
RST pulse width
100
131
RST true to stable outputs
---
150
ns
132
DRVFLT or COMPLT pulse width
100
---
ns
t33
DRVFLT or COMPLT high to INT low
---
150
ns
TABLE 8-2. CPU INTERFACE TIMING PARAMETERS
NOTES:
*1)lnputs are: PZO-5, PYO-3 when defined as
inputs, and AMDET when being used as a
simple input pin.
*2)Outputs are:PXO-7, and PYO-3 when
defined as outputs.
*3)RE = RD or C~
WE =WRorCS
11/19/91
20-57
II
WD10C01A
8.3
AC OPERATING CHARACTERISTICS
BUFFER INTERFACE TIMING
(Data is coming out of the WD1 OC01 A)
REQTIM=1 in RESET register. (REQA true when internal data register is full.)
RRCLK
REOA
143
BMDO·7, P
-----------D-~-A-U-ND-E-FI-NE-D----------~><
DATA VALID
X,----
FIGURE 8-10. ASYNCHRONOUS MODE DATA BUS WRITE TIMING (1)
REQTIM=O in RESET register. (REQA true one bit time before internal data register is full. Note that the
cycles overlap by one bit time.)
RRCLK
REOA
145
-I
BMDO-7, P'
FIGURE 8-11. ASYNCHRONOUS MODE DATA BUS READ TIMING (0)
20-58
11119/91
WD10C01A
AC OPERATING CHARACTERISTICS
(Data is going into the WD10C01A)
REQTIM=1 in RESET register. (REQA true when internal data register is empty.)
RRCLK
•
REOA
143
14
144
==d
145
BMDO-7. P
-I
X
DATA UNDEFINED
X"---
"'---D-A-TA-V-ALID
FIGURE 8·12. ASYNCHRONOUS MODE DATA BUS READ TIMING (1)
REQTIM=O in RESET register. (REQA true one bit time before internal data register is empty. Note that
the cycles overlap by one bit time.)
RRCLK
REOA
143
142
149
ACKA
144
148
147
BMDO·7. P
I-
X
DATA UNDEFINED
DATA VALID
-
I
-I
>C
FIGURE 8·13. ASYNCHRONOUS MODE DATA BUS WRITE TIMING (0)
11/19/91
20-59
I
WD10C01A
AC OPERA TlNG CHARACTERISTICS
DESCRIPTION
No.
MIN
MAX
UNITS
t40
DMA (REOA) cycle time (*1)
8*Tcyc
ns
41
RRCLK true to REOA true
40
ns
42
ACKA false to RRCLK true
43
REOA true to ACKA false: (*1)
REOTIM=O
REOTIM=1
20
ns
--100
44
ACKA active low
45
ACKA true to data valid
t46
ACKA false to data hold
10
47
data setup to ACKA * false
35
t48
ACKA false to data hold
5
49
ACKA true to REOA false
---
ns
60
ns
60
ns
ns
ns
35
TABLE 8-3. BUFFER INTERFACE TIMING PARAMETERS
NOTES:
*1)Tcyc is the RRCLK cycle time used.
20-60
ns
9*Tcyc-41-t42
8*TCyc-t4 d42
11/19/91
ns
WD10C01A
AC OPERATING CHARACTERISTICS
8.4
SERIAL DATA TIMING
AMDET
(if synchro nous)
.{
t66
RRCLK
"
160
'\J
,
t61
/
167
t62
t63
NRZI
j
Data Bit
t65
Control
__________ _________________________
x~
INDEX or
SECTOR or
AMDET (if asynchronous)
~
~
t68 _ _ _ _ _ __ _
________
"-_ _
FIGURE 8-14. NRZ DATA INPUT TIMING
WRCLK
/
t70
~,
"
t71
t72
;~
t73
)<
NRZO
Data Bit
--------}-----'~--~/-----~
•
RRCLK
j
175
•
FIGURE 8-15. NRZ DATA OUTPUT TIMING
11/19/91
20-61
WD10C01A
No.
AC OPERA TlNG CHARACTERISTICS
DESCRIPTION
MIN
MAX
UNITS
tso
RRCLK cycle time
37
ns
tS1
RRCLK low (*1)
14
ns
tS2
RRCLK high (*1)
14
ns
tS3
NRZI setup to RRCLK high
10
ns
tS4
RRCLK high to NRZI hold
10
ns
tS5
RRCLK high to new control out (*3)
tss
AMDET setup to RRCLK high (*4)
10
ns
tS7
RRCLK high to AMDET hold (*4)
10
ns
30
ns
tS8
asynchronous input width
2*Tcyc
ns
t70
W~CLK
high (*2) (*6)
(*2) (*6) (*7)
TrI0-6.0
TrI0-5.0
ns
t71
WRCLK low (*2) (*6)
(*2) (*6) (*7)
Trhi-6.0
Trhi-5.0
ns
t72
WRCLK low to NRZO change(*6)
(*6) (*7)
-3.5
-2.75
t73
NRZO setup to WRCLK high(*6)
(*6) (*7)
Trhi-9.5
Trhi-8.75
ns
t74
WRCLK high to NRZO hold (*6)
(*6) (*7)
Trlo-9.5
Trlo-8.75
ns
t75
RRCLK high to NRZO change
3.5
2.75
30
ns
ns
TABLE 8-4. SERIAL DATA TIMiNG PARAMETERS
NOTES:
*1)High and low times measured relative to
VIH and VIL.
*2)Trlo and Trhi are the clock low and clock
high (respectively) for the RRCLK input
used. Tcyc is RRCLK cycle time used.
*3)Control outputs are: SEQOUT, WG, RG,
andAMENA.
*4)When AMDET is supplied from a
synchronous source.
20-62
11119191
*5)Asynchronous inputs are: INDEX, SECTOR, and AMDET when it is supplied from
an asynchronous source.
*6)Where the RRCLK input is driven from
O.4V (VIL) to 2.4V (VIH).
*7)The specification with reduced load
capacitance of 25 pF.
WD10C01A
WD10C01A PROGRAMMER'S BENCH REFERENCE (PBR)
A.O
WD10C01A PROGRAMMER'S BENCH REFERENCE (PBR)
ADDR
NAME
DIR
SIZE
A.1
The following is a set of bit tables.
ADDRESS BIT TABLES
00
SRESET
W
6-0
01
SISR
R/W
7-0
02
SIMR
R/W
7-0
Bit
Write
03
SEOSTS/PYC
R/W
7-01
3-0
7
CLKOIV
6
OSCOIV
04
CSERR
R/W
3-0
05
CSCTL
R/W
7-0
06
CSVAL
R/W
7-2;
7-0
07
CSCNT
R/W
7-4,
0;7-0
08
PORTX
R/W
7-0
09
PORTY
R/W
3-0
OA
PORTZIAMC
R/W
5-01
7-0
Bit
Read/Write
OB
SEOCTL
R/W
5-0
7
GINT
OC
START
R/W
4-0
6
10FULL
00
LOOP
W
4-0
5
OXFER
SRESET(OO)
I
3
2
REOTIM
1
103$4
0
SRST
SISR(01) AND SIMR(02)
OE
ECCCTL
W
5-1
4
COMPLT
OF
SECCNT
R/W
7-0
3
SEOSTP
10
ECCP
R/W
3-0
2
SECENO
11
ECCS
R/W
4-0
1
SM$IX
12
SPORT
R
7-0
0
FAULT
13
Reserved
7-0
14
Reserved
7-0
15
Reserved
7-0
16
do not use - test only
17
SKIP
W
4-0
18
100
R/W
7-0
19
101
R/W
7-0
1A
102
R/W
7-0
1B
103
R/W
7-0
1C
104
R/W
7-0
10
105
R/W
7-0
1E
106
R/W
7-0
R/W
7-0
1F
107
TRUE = 1 FOR ALL BITS
..
5
4
SEQSTS(03)
11/19/91
Bit
Read
7
OATFLO
6
ECCEN
5
LAST
4
10
3
CHK
2
WAIT
1
AMOET
0
SEOOUT
20-63
WD10C01A
WD10C01A PROGRAMMER'S BENCH REFERENCE (PBR)
PYC(03)
Bit
CSVAl(06)
Write
Bit
Read/Write
7
7
BUFF
6
6
NOXFER
5
5
LAST
4
4
10
CHK
3
PY30UT
3
2
PY20UT
2
1
PY10UT
1
0
PYOOUT
0
CSERR(04)
Bit
CSCNT(07)
ReadlWrite
Bit
ReadlWrite
7
7
WOAM (COUNT)
6
6
WIAM
5
5
WIX
4
4
WSM
3
FAIL
3
2
RTY
2
1
OAC
1
0
SEQOUT
0
STOP
CSCTL(05)
Bit
SEQCTl(OB)
Write
Bit
7
SVSEL
7
6
CWSEL
6
Read
Write
RGERLY
5
WG
5
ECCERR
4
RG
4
10ERR
3
AM
3
PTYERR
IXMASK
2
CMPEN
2
SYNCER
SMMASK
1
SKPEN
1
CMPERR
RCMP
0
JMPEN
0
20-64
11119/91
KILL
WD10C01A
WD10C01A PROGRAMMER'S BENCH REFERENCE (PBR)
ECCCTL(OE)
Bit
ECCS(11)
Write
Bit
Read
7
7
6
6
EERR
Write
5
ECCCLR
5
CERR
4
CRCSET
4
14E
14E
3
CRCNIT
3
13E
13E
2
IGNERR
2
12E
12E
1
DISPTY
1
11E
11E
0
10E
10E
0
ECCP(10)
Bit
ReadlWrite
7
6
5
4
3
SYNCCRC
2
SYNCECC
1
DEG6/5
0
IFS5/3
11/19/91
20-65
WD10C01A
B.O
RESET CONDITIONS
RESET CONDITIONS
The following list defines what is reset when RST
is asserted on the WD10C01A, or the CPU sets
the internal reset bit (SRST in SRESET register):
• SRST bit in SRESET is left set, and must be
cleared by the CPU to take the WD10C01A
out of the reset state
• interrupts are disabled
• PYO-3 are set to input
• BMDO-7,P are disabled
• OSC is set to X1/2
• CPUCLK is set to X1/6
• command sequencer stops
The following outputs are reset to zero:
• PXO-7
• SEQOUT
• AMENA
• RG
• WG
• NRZO
• REQA
The following error status bits are reset to zero:
• IDERR
• PTYERR
The following CPU registers are reset to zero:
• PORTX
• PORT Y CONFIGURATION
• SECTOR COUNTER
• INTERRUPT MASK REGISTER
• SRESET REGISTER (except SRST)
• ECCP except SYNCCRC and SYNCECC,
which are initialized to one's
• ECCS
• SPORT
• KILL and RGERLY bits in SEQCTL register
20-66
11/19/91
WD10C01A
CRYSTAL OSCILLA TOR APPLICA TlONS
C.O
CRYSTAL OSCILLATOR APPLICATIONS
For applications that use the internal oscillator
capability of the WD1 OC01 A, a series resonant
crystal must be used. This crystal must meet the
following internal specifications:
CS = 7 pf MAX
RS
=30 ohms MAX
The oscillator also requires bypass capacitors, as
shown in the following diagram:The following
table lists values for C1 and C2 for several typical
crystal frequencies. The capacitor tolerances are
± 10%. Values for intermediate frequencies (not
listed in the table) may be extrapolated.
Pin 37
[x1]
FREQ (MHz)
C1 (pf)
C2 (pf)
8
180
100
10
180
68
12
150
47
14
120
56
16
82
56
20
82
33
24
56
27
25
56
22
30
39
12
32
33
12
II
------1....--------------.1C1
Crystal
L...l
Pin 38
[x2]
--------1
- - C2
""T"
FIGURE C·1. OSCILLATOR WITH CAPACITORS
11/19191
20-67
WD10C01A
0.0
PIN/SIGNAL SUMMARY
PIN/SIGNAL SUMMARY
SIGNAL
1/0
1
BMD7
110
Buffer
2
BMD6
I/O
Buffer
PIN
FUNCTION
SIGNAL
1/0
FUNCTION
36
CPUCLK
0
CPU Interface
37
X1
I
CPU Interface
PIN
3
BMD5
I/O
Buffer
38
X2
0
CPU Interface
4
BMD4
I/O
Buffer
39
PZ5
I
Disk Control
5
BMD3
I/O
Buffer
40
PZ4
I
Disk Control
6
BMD2
I/O
Buffer
41
PZ3
I
Disk Control
7
BMD1
1/0
Buffer
42
PZ2
I
Disk Control
8
BMDO
I/O
Buffer
43
VSS
I
Ground
9
VSS
I
Ground
44
PZ1
I
Disk Control
10
CS
I
CPU Interface
45
PZO
I
Disk Control
11
DBa
110
CPU Interface
46
PY3
1,0
Disk Control
12
DBa
110
CPU Interface
47
PY2
1,0
Disk Control
13
DBa
110
CPU Interface
48
PY1
1,0
Disk Control
14
DBa
I/O
CPU Interface
49
pya
1,0
Disk Control
15
DBa
110
CPU Interface
50
PX7
0
Disk Control
16
DBa
1/0
CPU Interface
51
PX6
0
Disk Control
17
DBa
I/O
CPU Interface
52
PX5
DBa
I/O
CPU Interface
53
PX4
0
0
Disk Control
18
19
RD
I
CPU Interface
54
PX3
0
Disk Control
20
WR
I
CPU Interface
55
PX2
0
Disk Control
21
A4
I
CPU Interface
56
PX1
0
Disk Control
22
A3
I
CPU Interface
57
PXO
0
Disk Control
23
A2
I
CPU Interface
58
WG
0
Disk Data
24
A1
I
CPU Interface
59
RG
0
Disk Data
25
AO
I
CPU Interface
60
VDD
I
+5 Volts
26
VDD
I
+5 Volts
61
RST*
I
CPU Interface
27
INT
0
CPU Interface
62
WRCLK
0
Disk Data
28
SECTOR
I
Disk Control
63
NRZO
0
Disk Data
29
INDEX
I
Disk Control
64
RRCLK
I
Disk Data
30
AMDET
I
Disk Data
65
NRZI
I
Disk Data
31
AMENA
0
Disk Data
66
REQA
0
Buffer
32
SEQOUT
0
Disk Data
67
ACKA
I
Buffer
33
OSC
0
CPU Interface
68
DBP
I/O
Buffer
34
DRVFLT
I
Disk Control
35
COMPLT
I
Disk Control
20-68
11/19/91
Disk Control
WD10C01A
DIFFERENCES BETWEEN WD10COO AND WD10C01A
E.O
DIFFERENCES BETWEEN WD10COO AND WD10C01A
E.1
ERROR CORRECTION AND
DETECTION
specifications with reduced loading capacitance of
25 pF.
The computer-generated-code ECC in WD10COO
was replaced with the Reed-Solomon ECC in
WD10C01A. Six registers (ECC[0:5]) which define
the masks for ECC polynomials in WD10COO
were taken out. The new ECCP, ECCS, SPORT
registers facilitate the configuration parameters,
operation status and the syndrome access for the
new RS encoder/decoder.
E.2
E.5
The name of the microprocessor data bus and the
DMA data bus are changed to reflect the name on
the circuit diagrams. The pin order and the f u n c - I I
tions are exactly the same as before.
SRESET REGISTER
The control bits IDCHK, DCHK, ECCSIZ bits of
the WD10COO are removed. By default, data field
is covered by RS-ECC, and ID Field is covered by
CCITT-CRC with g(x)= X16 + X12 + X5 + 1.
E.3
The ECCINL, ECCSHT, ECCINM bits of the
WD10COO are removed. The control bit ECCSET
is renamed to CRCSET, bit ECCNIT is renamed
to CRCNIT. These bits affect only the CRC shift
registers, the RS-ECC shift registers are be
default reset to zero. The control bit DISCHK of
WD10COO is changed into IGNERR. Its function is
still the same.
E.4
WD10COO
WD10C01A
DBO-DB7
BMDO-BMD7
DBP
BMDP
DO-D7
DBO-DB7
E.S
ECCCTL REGISTER
TIMING
The tim.l.!:!9..Jg (data setup time on the BMD bus
before ACKA goes inactive) is changed from 30
ns to 35 ns; t70, t71, t72, t73 and t74 have additional
PIN NAME
PARITY ERROR HANDLING
WD10COO will latch the parity error condition into
the SEOCTL register and the operation will continue normally. WD1 OC01 A will stop at the end of
the current CS instruction if the FAIL bit is set to
one. The WG output is also deasserted.
E.7
SEaCTL REGISTER
Bit 6 and bit 0 in the SEOCTL register are unused
in the WD10COO and in the WD10C01A. These
bits are read-only type and are set to one in the
WD10COO; in the WD1 OC01 A, these bits are set
to zero.
11/19/91
20-69
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