210830 013_Flash_Memory_Vol_2_1994 013 Flash Memory Vol 2 1994

User Manual: 210830-013_Flash_Memory_Vol_2_1994

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LOFINT1/1OO693

FLASH MEMORY
VOLUME II

1994

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may
appear in this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your locai Intel sales office or your distributor to obtain the latest specifications before placing your product order.
MDSis an ordering code only and is not used as a product name or trademark of Intel Corporation.
Intel Corporation and .Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH
trademark or products.
*Other brands and names are the property of their respective owners.
Additional copies of this document or other Intel literature may be obtained from:
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Literature Sales
P.O. Box7~1
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
©INTEL CORPORATION. 1993

LGCPV1/100693

intel~
DATA SHEET DESIGNATIONS
Intel uses various data sheet markings to designate each phase of the document as it
relates to the product. The marking appears in the upper, right-hand corner of the data
sheet. The following is the definition of these markings:
Data Sheet Marking

Description

Product Preview

Contains information on products in the design phase of
development. Do not finalize a design with this
information. Revised information will be published when
the product becomes available.

Advanced Information

Contains information on products being sampled or in
the initial production phase of development. *

Preliminary

Contains preliminary information on new products in
production. *

No Marking

Contains information on products in full production. *

'Specifications within these data sheets are subject to change without notice. Verify with your local Intel sales
office that you have the latest data sheet before finalizing a design.

DSDSG1/100693

intel~

Memory Overview

Flash Overview

FlashFileTM Components

Boot Block Components

Bulk..Erase Components

Memory Cards

Flash AT A Drives

Automotive Components

Process Engineering Reports

infel·
Article Reprin.ts

Table of Contents

Alphanumeric Index ...................................................... .

xiv

CHAPTER 1
Memory Overview
Intel Memory Technologies ................................................ .

1-1

CHAPTER 2
Flash Overview
Flash Overview .......................................................... .
APPLICATION NOTES
AP-357 Power Supply Solutions for Flash Memory ............................ .
AP-374 Flash Memory Write Protection Techniques ..................•........
AB-29 Flash Memory Applications in Laser Printers ........................... .

I;;

'T_

2-1
2-7
2-42
2-49

CHAPTER 3
FlashFile™ Components
DATA SHEETS
DD28F032SA 32 Mbit (2 Mbit x 16, 4 Mbit x 8) FlashFile™ Memory ............. .
28F016SA 16 Mbit (1 Mbit x 16, 2 Mbitx 8) FlashFile™ Memory ................ .
28F008SA 8 Mbit (1 Mbit x 8) FlashFile™ Memory ............................ .
28F008SA-L 8 Mbit (1 Mbit x 8) FlashFile™ Memory .......................... .
APPLICATION NOTES
AP-359 28F008SA Hardware Interfacing .................................... .
AP-360 28F008SA Software Drivers ........................................ .
AP-362 Implementing Mobile PC Designs Using High Density FlashFile™
Components .......................................................... .
AP-364 28F008SA Automation and Algorithms ............................... .
AP-375 Upgrade Considerations from the 28F008SA to the 28F016SA .......... .
AP-377 28F016SA Software Drivers ........................................ .
AP-378 System Optimization Using the Enhanced Features of the 28F016SA .... .
ENGINEERING REPORT
ER-27 The Intel 28F008SA Flash Memory ................................... .
SUPPORT TOOLS .
Intel 28F008SA FlashFile™ Memory Evaluation Module D, FLASHEVAL4 Product
Brief .................................................................. .

I
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J
3-1
3-6
3-49
3,77
3-105
3-116
3-139
3-194
3-208
3-221
3-259
3-282

3-307

CHAPTER 4
Boot Block Components
DATA SHEETS
28F400BX-T IB, 28F004BX-T IB 4 Mbit (256K x 16, 512K x 8) Boot Block Flash
Memory Family ..........................................•..............
28F400BX-TLlBL, 28F004BX-TL/BL 4 Mbit (256K x 16, 512K x 8) Low Power Boot
Block Flash Memory Family ............................................. .
28F200BX-T IB,28F002BX-T IB 2 Mbit (128K x 16, 256K x 8) Boot Block Flash
Memory Family ............................. : .......................... .
28F200BX-TLlBL, 28F002BX-TL/BL 2 Mbit (128K x 16, 256K x 8) Low Power Boot
Block Flash Memory Family ............................................. .
28FOOl BX-T/28FOOl BX-B 1M (128K x 8) CMOS Flash Memory ...............•.
APPLICATION NOTES
, AP-341 Designing an Updatable BIOS Using Flash Memory .................... .
AP-363 Extended Flash Bios Concepts for Portable Computers ................ .
ENGINEERING REPORTS
ER-26 The Intel 28FOOl BX-T and 28FOOl BX-B Flash Memories ................ .
ER-29 The Intel2/4-Mbit Boot Block Flash Memory Family .................... .
SUPPORT TOOLS
Boot Block Flash: The Next Generation White Paper .......................... .

4-1
4-49

I
I~
I

4-92

,1I

4-138
4-179
4-208
4-251
4-273
4-288
4-317
xi

l:kJ

Table of Contents' (Continued)
Intel2/4Mbit Boot Block Flash Memory Evaluation Module (D,FLASHEVAL5)
Product Brief ....................... .............
'
; ................. ,., .•. 4-321

CHAPTERS
Bulk-Erase Components
DATA SHEETS
28F020 2048K (256K x 8) CMOS Flash Memory ............ " . . . . . . . . . . . . . . . . . .
28F010 1024K (128K x 8) CMOS Flash Memory. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .
28F512512K (64Kx 8) CMOS Flash Memory.................................
28F256A 256K (32K x 8) CMOS Flash Memory ..........•....................
APPLICATION NOTES
AP-316 USing Flash Memory for In-System Reprograrnmable Nonvolatile Storage.
AP-325 Guide to First Generation FI,ash Memory Programming .. : . . . . . . . . . . . . . ..
ENGINEERING REPORT
ER"24 Intel Flash Memory 28F256A, 28F512, 28F010, 28F020 .•. " , .... " . .. . ..
SUPPORT TOOLS
Intel Flash Memory Evaluation Kit II (D, FLASHEVAL2)ProductBrief.............
Small Outline Package Physical Dimensions .. , . . . . . . . . . . .. . . . . . . . . . . . . . .. . . ..

5-1
5-33
5-64
5-92
5-117
5-162
5-184
5-207
5-209

CHAPTER 6
Memory Cards
DATA SHEETS
Series 2 + Flash Memory Cards, iMC040FLSP . .. . .. . . . . . . . . . . . . . . . . . . . . .. . . . .
Series 2 + Flash Memory Cards, iMC004FLSP/iMC020FLSP ......... " , . . . . . .. .
Series 2 Flash Memory Cards, iMC002/004/010/020FLSA . . . . . . . . . . . . . . . . .. . . .
iMC004FLKA 4-Megabyte Flash Memory Card................................
iMC002FLKA2-Mbyte Flash Memory Card ............ ; .................... ,.
iMC001 FLKA1-Megabyte Flash Memory Card , . , , ',,' , . " .. , . , , . . . . . . . . . . . . . . ..
APPLICATION NOTES
',
,
AP-343 Solutions for High Density Applications Using Intel Flash Memory........
AP-361 Implementing the Integrated Registers of the Series 2 Flash Memory Card .
AB-56 Preparing for the Next Generation Intel Flash Memory Card. . . . . . . . . . . . . •.
SUPPORT TOOLS
Intel FlashFile™Memory-The Key to Diskless Mobile PCs. . . . . . . . . . . . . . . . .. . ...
Intel ExCATM Hardware Developer's Kit Product Brief ..... " . . . . . . . . . . . .. . . . . ..

6-1
6-6
6-37
6-75
6-105
6-135
6-165
6-195
6-212
6-220
6-226

CHAPTER 7
Flash ATA Drive
Flash Drive iFD005P2SAliFD010P2SA ................. ;....................
iFD005P2SAl010P2SAFIash Drive Product Brief.............................

7-1
7-32

CHAPTER 8
Automotive Components
A28F400BX-T IB 4-Mbit(256K x 16,512K x 8) Boot Block Flash Memory Family
8-1
(Automotive) ...................................................•... ;...
A28F200BX-T IB 2-Mbit (128K x 16, 256Kx 8) Boot Block Flash Memory Family
'
; .......................... ; . . . 8-35
(Automotive) .. ,;. ........................
8-68
A28F010 t024K (128 x 8) CMOS Flash Memory (Automotive)...................
8-91
A28F512 512K (64K x 8) CMOS Flash Memory (Automotive) ........ ,...........
A28F256A 256K (32K x 8) CMOS Flash Memory (Automotive) ........•........• 8-115

CHAPTER 9
Process Engineering Reports
ER-20 ETOXTM II Flash Memory Techno!ogy ..•. .............................
ER-28 ETOXTM III Flash Memory Technology. . . . .. . . .. . . . . . . . . . . . . . . . . . . . . . . .

xii

9-1
9-6

Table of Contents (Continued)
ER-33 ETOXTM IV Flash Memory Technology: Insight to Intel's Fourth Generation
Process Innovation ................................... ; . . . . . . . • . . . • . . . . . . .
CHAPTER 10
Article Reprints
AR-710 Flash Solid-State Drive with 6MB/s Read/Write Channel and Data
Compression ..•..••..•....•......•..•..................................
AR-711 Flash: Big News in Storage? .........•.....•..........•...•...•......
AR-715 Flash Memory: Meeting the Needs of Mobile Computing •...............
AR-716 Flash Memory for Top Speeds in Mobile Computing Applications ........ .
AR-717 The Many Facets of Flash Memory ............•...........•.•........
AR-718 Standardizing on a Flash File System; •.....•..•...•..••......•...•...
AR-723 Interfacing BootBlock Flash Memories to the MCS$ 96 Family .....•.....

9-19

10-1
10-4
10-8
10-16
10-18
10-27
10-31

xiii

. AlphanumeriC Index ......;

28F001 BX"T't28FOQ1 BX'!'B .tM (128K x 8)eMOSF~a$h~Memory .: ... , •,...•..; .\ ': .• : .• ,;; ,;
28F008SA 8 Mbit (1 Mbit x 8) FlashFile™ Memory ................... ";~,,, • , .••... : ... .
. 28FOQ8SA-L 8 Mbit (1 Mbit x 8) FlashFile™ .Memory .•........••.............. , ..... .
28F010 1024K (128K x 8) CMOS Flash Memory •••..••.•••...•••....•...•... , .' ..••.•
28F016SA 16 Mbit (1 Mbit x 16, 2 Mbit x 8) FlashFileT~ Memory ...•.....••...••.• ~ •...
28F020 2048K (256K x 8) CMOS FlashMemory .. ~: ~ .•. ; ; •.•..••. '.' .•. ~: .•...•..... : .
28F200BX-T IB, 28FOO2BX-TIB 2 Mbit (128Kx 16, 256K x 8) Boot Block Fla.sh Memory
.i'family .• : . " .••..•.••.••.•...• ; ...••..•.• ; .; ...•.. : ,,:.',"; .•. '~'~'" .:.'; ,. ..,.:: •...•..•..
?8F200BX-TL/BL, 28F002BX-rLlSt 2 Mbit (1281<'x16, ~56K x8) LowPciwerBOot BI9Ck
.Flash Memory Fainily .... ,.' .. ;':.';: ..... : .. : ., •.. ~ .. ; ..• : .... ; .' •.•....•.• : ....... .
28F256A 256K (32K x 8) CMOS Flash Memory ;; .........•..•.......•.. : ........... .
28F400BX-TIBi28F004BX-TIB 4Mbit (256Kx '16, 512Kx 8) Boot Block Flash Memory
Family ......••..•..•.••.•...••. ; ......... " . '....•. '.•.•.. '......................... "
. 28F400BX-TLlBL, 28FOO4BX-TL/BL 4 Mbit (256K x 16, 512K x 8) Low Power Boot Block
Flash Memory Family. ; ..••.....•.•••.•.....•......•.•.......•.••.••......•..•..
28F512 512K (64K x 8) CMOS Flash Memory .....•.•..•..•...•.....•.••..•..........
A28F010 1024K (128 x 8) CMOS Flash Memory (Automotive) •...•..•......•..•.......
A28F200BX-TIB 2-Mbit (128K x 16, 256K x8) Boot Block Flash Memory Family
.
(Automotive) .................................................................. .
A28F256A 256K (32K x 8) CMOS Flash Memory (Automotive) •..•.........••.....•....
A28F400BX-T/B 4-Mbit (256~ x 16,512Kx 8) Boot Block Flash Memory Family'
(Automotive) ........•........•.....••..•.•.....•..........••.......•...•.......
A28F512. 512K (64K x 8) CMOS Flash Memory (Automotive) ......•.....•....... : .....
AB-29 Flash Memory Applications in Laser Printers ..•.•...•.•...••....•...• ; .....•..•
AB~56 Preparing for the Next Generation Intel Flash Memory Card •.......•.. '......... .
AP-3t6 Using Flash Memory for In-System Reprogrammable Nonvolatile Storage ..•.....
AP-3,25 Guide to First Generation Flash Memory Programming ...••..•..•..............
AP-341 Designing an Updatable BIOS Using Flash Memory •...•..•....••..•..........
AP-343 Solutions for High Density Applications Using Intel Flash Memory .............. .
AP-357 Power Supply Solutions for Flash Memory ................................... .
AP-359 28F008SA Hardware Interfacing .••....•..•......•.....••...........•.......
AP-360 28F008SA Software Drivers ......•.....•.....•..................•.........•
AP-361 Implementing the Integrated Registers of the Series 2. Flash Memory Card .•.....
AP-362 Implementing Mobile PC Designs Using High Density FlashFile™ Components •..
AP-363 Extended Flash Bios Concepts for Portable Computers .•••.. : ..... : ...•...•...
AP-364 28F008SA Automation and Algorithms ..•....••..•..•.....•.................
AP-374 Flash Memory Write Protection Techniques .....................•......•.....
AP-375 Upgrade Considerations from the 28FOO8SA to the 28F016SA .......•..•.......
AP-377 28F016SA Software Drivers ................................................ .
AP-378 System Optimization Using the Enhanced Features of the 28F016SA ....•.......
AR-71 0 Flash Solid-State Drive with 6MB/s Read/Write Channel and Data Compression .•
AR-711 Flash: Big News in Storage? .•.••..•••...•.....•.....•.•••.••...•..•••.. ; .•
AR-715 Flash Memory: Meeting the Needs of Mobile Computing .....•.................
AR-716 Flash Memory for Top Speeds in Mobile Computing Applications ...........•...
AR-717 The Many Facets .of Flash Memory ..............•....•.•.•.....•...•..•..•.
AR~718 Standardizing on a Flash File System ............................ : ......... .
AR~723 Interfacing BootBlack Flash Memories to the MCS~ 96 Family ................. .
Boot Block Flash:The Next Generation White Paper ..•••.....••....••..••.......•.••
DD28F032SA 32 Mbit (2 Mbit x 16, 4 Mbit x 8) FlashFile™ Memory .................... .
ER-20 ETOXTM II Flash MemoryTechnology •••...•...••••..••.........•..••........
ER~24lntel Flash Memory 28F256A, 28F512, 28F010, 28F020 •.......................
ER-26 The Intel 28FOO1 BX-T and 28FOO1 BX-B Flash Memories ....•..•..•. ; ..•.......
ER-27 The Intel 28F008SA Flash Memory ..•..•. ; ••.•..••.•....••.•...........•..•..
ER-28 ETOXTM III Flash Memory Technology .•.................•..•........ ,' ......•.
xiv

4-179
3-49 .

·3,77
5~33

... 3-6
5-1
4-92
4-138
5-92
. 4-1
4-49
5-64
8-68

8-35
8-115
8-1
8-91
2-49
6-212
5-117
5-162
4-208
6-165
2-7
3-105
3-116 .
6-195
3-139
4-251
3-194
2-42
3-208
3-221
3~259

10-1
,10-4
10-8
10-16
10-18
10-27
10-31
4-317
3-1
9-1
5-184
4-273
3-282
9-6

Alphanumeric Index (Continued)
ER-29 The Intel 2/4-Mbit Boot Block Flash Memory Family. . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-288
ER-33 ETOXTM IV Flash Memory Technology: Insight to Intel's Fourth Generation Process
Innovation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . .. . . .. . . . . . . . 9-19
Flash Drive iFD005P2SAliFD010P2SA .............................................
7-1
Flash Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . .. . . . . . . . . . . . . .
2-1
iFD005P2SAl010P2SA Flash Drive Product Brief.................................... 7-32
iMC001 FLKA 1-Megabyte Flash Memory Card. . . . . . .. . . . . . .. . . . . . . . . . . . . . . . .. . . . . . .. 6-135
iMC002FLKA 2-Mbyte Flash Memory Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-105
iMC004FLKA 4-Megabyte'Flash Memory Card ...... , . . . . . . . . . . . .. . . . . . . .. . ... . . . . . . . 6-75
Intel 28 F008SA FlashFile™ Memory Evaluation Module D, FLASHEVAL4 Product Brief... 3-307
Intel 2/4Mbit Boot Block Flash Memory Evaluation Module (D,FLASHEVAL5) Product
Brief ......................................................................... 4-321
Intel ExCATM Hardware Developer's Kit Product Brief................................ .6-226
Intel Flash Memory Evaluation Kit II (D, FLASHEVAL2) Product Brief................... 5-207
Intel FlashFile™ Memory-The Key to Diskless Mobile PCs ............................ 6-220
Intel Memory Technologies ............................................ ............
1-1
Series 2 Flash Memory Cards, iMC002/004/0101020FLSA ......................... :.
6-37
Series 2 + Flash Memory Cards, iMC004FLSPliMC020FLSP ..... '.' . . . . . . . . . . . . . . . . . . .
6-6
Series 2 + Flash Memory Cards, iMC040FLSP .................................... ; . .
6-1
Small Outline Package Physical Dimensions.. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. 5-209

II
i

Memory Cards

f
:.~

1'1:
;~

SERIES 2+ FLASH MEMORY CARDS
40 MEGABYTES
IMC040FLSP

•
•
•
•
•
•

Single Power Supply Operation
Automatically Reconfigures for 3.3V
and 5V Systems
150 ns Maximum Access Time with
13 MBIS Read Throughput
High Performance Random Writes
- 0.85 MBIS Sustained Throughput
- 1 KB Burst Write @ 10 MBIS
PCMCIA 2.01JEIDA 4.1 Compatible
PCMCIA Type 1 Form Factor

Architecture
• -Revolutionary
Pipelined Command Execution

•
•
•
•

- Write During Erase
- Series 2 Command Superset
50 ,..,A Typical Deep PowerDown
State-of~the-Art 0.6 ,..,m ETOX IV Flash
Technology
1 Million Erase Cycles per Block
640 Independent Lockable Blocks

Intel's Series 2+ Flash Memory Card sets the new record for high-performance disk emulation and XIP
applications in mobile PC's and dedicated equipment. Manufactured with Intel's DD28F032SA 32-Mbit
FlashFile™ Memory, this card takes advantage of a revolutionary architecture that provides innovative capabilities, low power operation and very high read/write performance.
The Series 2 + Card provides today's highest density, highest performance non-volatile read/write solution for
solid-state storage applications. These applications are further enhanced with this product's symmetrically
blocked architecture,extended MTBF, low power 3.3V operation, built-in Vpp generator, and multiple blocklocking methods. The Series 2 + Card's dual read and write voltages allow interchange between 3.3V and 5V
systems.

I
'.1

it
"~I'

1.:/:

290512-2

ETOX and FlashFile™ are trademarks of Intel Corporation.

November 1993
Order Number: 290512-001

6-1

SERIES 2 + FLASH MEMORY CARD

PRODUCT OVERVIEW
The 40 Megabyte, Series 2 + Flash Memory Cards
contain a flash memory array that consists of 10
DD28F032SA TSOP . memory devices. Each
DD28FO~2SA, encapsulating two 28F016SA devices, contains sixty-four diStinct, individuaIlY-Elrasable,
64 Kbyte blocks; therefore, the cards contain 640
device blocks:
The Series 2 + Card offers additional product features to those of the Series 2 Card product family
(refer to ,the iMC002FLSA, iMC004FLSA, iMC010FLSA, and iMC020FLSA data sheets). Some of the
more notable card-level enhancements inClude: single power supply operation at either 3.3V or 5V and
page buffers to increase write performance.
The card incorporates Vee and Vpp detect circuitry,
referred to as SmartPower, to sense the voltage level present at the card interface. The card's control
logic automatically configures its circuitry and the
DD28F032SA memory array accordingly. The Card
Information Structure reports that the card is 3.3V or
5V compatibl,e. The card also detects the presence
of 12V on the socket Vpp pin and passes this supply
to each DD28F032SA. When 12V is unavailable, the
card generates the required Vpp via its integrated
Vpp-generation circuitry, whether Vee is 3.3V or 5V.
At the device level, internal algorithm automation allows write and block erase operations to be executed using a two-write command seqlJence in the
same way as the 28F008SA FlashFiI~ memory in the
Series 2 Card. A superset of commands and additional performance enhancements have been added
to the basic 28F008SA command-set:
• Page buffer writes to flash result in 4 times
faster writes than Series 2 Cards.

.'In~,·.~
+:-.
bl6ck retirement. These techniques, analogous to
those used in hard disk drives, have already been
employed in many flash file systems. '
The Series 2 + Card has two means for p.utting its
flash devices into a Deep-Sleep mode for reduced
power consumption: 1)Write to the card's PCMCIAcompatible Configuration and Status Register, to activate a Reset-PowerDown to all devices simultaneously; 2) Issue a command to individual devices,
referred to as the software-Controlled Deep-Sleep
mode. Using this approach, the device will retain
status register contents and finish any operation in
progress.
The carciJ achieves its PCMCIA-compatible wordwide access by pairing the DD28F032SA devices resulting in an accessible memory block size of
64 KWords. The card's decoding logic (contained
within its ASICs) allows the system to write or read
one word at a time, or one byte at a time by refer- •
encing the high or low byte. Erasure can be performed on the entire. block pair (high and low device
block simultaneously) or on the high or low byte portion separately. Although the DD28F032SA supports
byte or word-wide data access, the byte interface
was utilized within the card to allow the delivery of
higher performance benefits (such as the doubling
'
of the effective page buffer size).
The Series 2 + Card's ASICs also contain the Card
Information Structure and the Component Management Registers that provide five control functionsReady-Busy mode selection, software-controlled
write protection, card status, voltage-control and
status, and soft reset.

• Command queuing permits the devices to receive new commands during the execution of the
current command.

The memory, card interface supports the Personal
Computer Memory Card Industry Association
(PCMCIA 2.01) and Japanese Electronics Industry
Development Association (JEIDA 4.1) 68-pin card
format. The Series 2 + Flash Card meets all
PCMCIAI JEIDA Type 1 mechanical specifications,

• Automatic data writes during erase allows the
DD28F032SA to perform write operations to one
block of memory while performing ,an erase on
another block.

SERIES 2 + CARD ARCHITECTURE
OVERVIEW

• Software locking of memory blocks provides a
means to selectively protect code or !iata within
the card.
• Erase all unlocked blocks provides a quick and
simple method' to sequentially erase, the blocks
within a DD28F032SA.

Each block of the DD28F032SA can be written and
erased a minimum ,of 100,000 cycles. The Series
2 + Card can achieve 1 million Block Erase Cycles
by providing wear-leveling a:igorithmsand graceful

6-2

As depicted in Figure 1, the Series 2 + Card consists of three major functional elements-the
DD28F032SA Flash Memory array, card control logic and SmartPower circuitry. The card control logic
handles the interface between the flash memory array and the host system's PCMCIA signals. The
SmartPower circuitry provides the card's integrated
Vpp generator and a means for detecting the socket's voltage levels.

SERIES 2 + FLASH MEMORY CARD

0< 15:0>

ZOO<15:8>

A<25:0>

ZOO<7:0>

REG#

ZA<20:0>

CE1#

ZWE#

CE2#
WE#
OE#
RST#
WAIT#

ZOE#

CARD
CONTROL
LOGIC

BV01#

ZCEO#<7:0>
ZCEI #<2:0>
ZRY/ZBY#
ZRP#
zWP

BV02#
WP

CEO# DD28F032SA 0<7:0>

D<7:0> DD28F032SA CEO.
A<20:0> Device 9 CEI.
Ryley·
WE·
RP.
OE·
WP

C01#
C02#
ROY /BSY#
Vss

CEI"

RYley.

RP"
WP

Vee Vpp Vss 3/5#

Vee

I I

3/5# Vss Vpp Vee

RYley.
RP#
WP

I I I I
Ryley.

WE·
OE·

RP#
WP

Vee Vpp Vss 3/5#

Vee
VpPI

Vpp

v pP2

GENERATION

Vce
Vpp

1 1'1

WE·
OE·

3/5"

Vss Vpp Vee

I I I

I I I I
0<7:0> DD28F032SA CEO#
A<20:0> Clylce 1 CEI#

T T

CEO# DD28FD32SA 0<7:0>
CE1# Device 8 A<20:0>

D<7:0> DD28FO.2SA CEO#
A<20:0> Device 7 CEI#
Ryley.
WE#
RP#
OE·
WP
Vee Vpp Vss 3/5#

lij

Device 8 A<20:0>
WE·
OE.

... :..~!~2 ..~,,>
CE1#

Device 0 A<20:0>

Ryley.
RP#
WP

3/5.

WE#
OE#

till
f---

Vss Vpp Vee

I I
T

vss

VS1
VS 2

SmartPower

3/5#

290512-1

Figure 1. Series 2+ Card Block Diagram showing Major Functional Elements including the Card's
Control Logic, Smart Power Circuitry and the DD28F032SA Flash Memory Components

6·3

intel®

SERIES 2 + FLASH MEMORY CARD

The Series 2+ Card signals pomplywith the PCMCIA specification, as shown in Table 1. Table 2 describes the
functionality of these signals.
Table 1. Series 2+ Flash Memory Ca~d Signals
Pin

Signal

I/O

1 GND

Function

Active

Ground

Pin .

Si~nal

GND'

I/O

Function

D03

I/O

Data Bit 3

CD1#

D04

I/O

Data Bit 4

0011

1/0

Data Bit 11

005

I/O

Data Bit 5

0012

1/0

Data Bit 12

DOs

I/O

Data Bit 6

0013

1/0

Data Bit 13

007

I/O

0014

1/0

Data Bit 14

CE1#

0015

1/0

Data Bit 15

A10

Address Bit 10

OE#

Output Enable

I
I

Data Bit 7
Card Enable 1

LOW

Card Detect 1

CE2#

Card Enable 2

VS1

Voltage Sense 1

Address Bit 11

RFU

Reserved

Address Bit 9

RFU

Reserved

LOW

A11

Address Bit 8

A17

Address Bit 17

A13

Address Bit 13

Address Bit 18

A14

Address Bit 14

47 . A1S
48 A1S

Address Bit 19

WE#

Write Enable

LOW

A20

Address Bit 20

RDY/BSY#

Ready-Busy

LOW

A21

Address Bit 21

Vee

Supply Voltage

Vee

VPP1

Supply Voltage

VpP2

A1S

Address Bit 16

A22

Address Bit 22

A15

Address Bit 15

A23

Address Bit 23

Address Bit 24

(

A12

Address Bit 12

A24

Address Bit 1

A25

Active

~round

LOW

Supply Voltage
$upply Voltage

Address Bit 25

Address Bit 6

VS2

Voltage Sense 2

Address Bit 5

RST

Reset

HIGH

Extend Bus Cycle

LOW

Address Bit 4

WAIT#

Address Bit 3

RFU

Reserved

Address Bit 2

REG#

Address Bit 1

BVD2

Batt. Volt Det 2

Address Bit 0

BVD1

000

1/0

Data BitO

DOs

1/0

Data Bit 8

001

1/0

Data Bit 1

DOs

1/0

Data Bit 9

002

1/0

Data Bit 2

0010

1/0

Data Bit 10

CD2#

GND

30
31

6·4

Write Protect
Ground

HIGH

N.C.

LOW

Batt. Volt Det 1

Card Detect 2
Ground

LOW

infel~

SERIES 2 + FLASH MEMORY CARD
Table 2. Series 2 + Flash Memory Card Signal Descriptions

Symbol

Type
I

Ao-A25

Description
ADDRESS INPUTS: Ao through A25 are address bus lines which enable direct
addressing of 64 megabytes of memory on a card. Ao is not used in word
access. A25 is the most significant bit.

000-0015

I/O

CE1#,CE2#

CARD ENABLE 1,2: CE1 # enables even bytes, CE2# enables odd bytes.
Multiplexing Ao, C01 # and C02# allows 8-bit hosts to access all data on 000
through 1?07.

QE#

OUTPUT ENABLE: Active low signal gating read data from the memory card.

DATA INPUT/OUTPUT: 000 through 0015 constitute the bidirectional data
bus. 0015 is the most significant bit.

WE#

WRITE ENABLE: Active low signal gating write data to the memory card.

ROY/BSY#

READY/BUSY OUTPUT: Indicates status of internally timed erase or write
activities. A high output indicates the memory card is ready to accept accesses.
A low output indicates that a device(s) in the memory card is(are) busy with
internally timed activities. -

C01#,C02#

CARD DETECT 1, 2: These signals provide for correct card insertion detection.
They are positioned at opposite ends of the card to detect proper alignment. The
signals are connected to ground internally on the memory card and will be
forced low whenever a card is placed in the socket. The host socket interface
circuitry shall supply 10K or larger -pull-up resistors on these Signal pins.

WRITE PROTECT: Write Protect reflects the status of the Write"Protect switch
on the memory card. WPset high = write protected, providing internal hardware
write lockout to the flash array.
WRITE/ERASE POWER SUPPLY: (12V nominal) for erasing memory array
blocks or writing data in the array. They must be 12V to perform an erase/write
operation, when not using the card's integrated Vpp generator; These signals
"lay be disconnected but are required for ExCA compliance.

VPP1, VPP2

Vee
GNO

REG#

CARD POWER SUPPLY: (3.3V/5V nominal) for all internal Circuitry.
I

GROUND for all internal circuitry.

REGISTER SEI.,ECT: provides access to Series 2 + Flash Memory Card
registers and Card Information Structure in the Attribute Memory Plane.

RST

RESET from system, active high. Places card in Power-Ori Oefault State.

WAIT#

WAIT: (Extend Bus Cycle) Used by Intel's I/O cards and is driven high.

BV01, BV02

BATTERY VOLTAGE DETECT: Upon completion of the power On reset cycle,
these signals are driven high to maintain SRAM-card compatibility.

VS1, VS2

VOLTAGE SENSE: Signals notify the host socket of the card's Vee
requirements. VS1 is grounded and VS2 open indicates a 3.3V /5V card as
depicted in the CIS;
.-

RFU

RESERVED FOR FUTURE USE.

N.C.

NO INTERNAL CONNECTION. Pin may be driven or left floating.

6-5

. OS@W£OO©f§

OOOIF@OO~£i1'O@OO

SERIES 2+ FLASH MEMORY CARDS
4 and 20 Megabytes
iMC004FLSp, iMC020FLSP

•
•
•
•
•
•

Single Power Supply Operation
Automatically Reconfigures for 3.3V
and 5V Systems
150 ns Maximum Access Time with
13 MBtS Read Throughput
High Performance Random Writes
- 0.85 MBtS Sustained Throughput
-1 KB Burst Write @ 10 MBtS
PCMCIA2.0tJEIDA 4.1 Compatible
PCMCIA Type 1 Form Factor

•

Revolutionary Architecture
- Pipelined COmmand Execution
- Write During Erase
- Series 2 Command Superset

•
•
•
•

12 ,..,A Typical' Deep Powerdown
State-of-the Art 0.6 ,..,m ETOX IV FlllSh
Technology
1 Million Erase Cycles per Block
320 Independent Lockable Blocks

Intel's Series 2 + Flash Memory Card' sets the new record for high-performance disk emulation and XIP
applications in mobile PC's and dedicated equipment. Manufactured with Intel's 28F016SA 16-Mbit
FlashFile™ Memory, this card takes advantage of a revolutionary architecture that provides innovative capabilities, low power operation andvery,high read/write performance.
The Series 2+ Card provides today's highest density, highest p(:lrformance non-volatile read/write solution for
solid-state storage applications. These applications are further enhanced with this product's symmetrically
blocked architecture, extended MTBF, low power 3.3V operation, built-in Vpp generator, and multiple blocklocking methods. The Series 2 + Card's dual read and write voltages allow interchange between 3.3V and 5V
systems.

290491-8
ETOX and FlashFile™ are trademarks of Intel Corporation.

6-6

December 1993
Order Number: 290491-002

Series 2 + Flash Memory Cards
CONTENTS

PAGE

CONTENTS

PAGE

SCOPE OF DOCUMENT ................. 6-8

OPERATION SPECiFiCATIONS ........ 6-22

PRODUCT OVERVIEW .................. 6-8

Absolute Maximum Ratings .............. 6-22
Operating Conditions .................... 6-22

ARCHITECTURE OVERVIEW . ........... 6-9

Block Diagram ............................ 6-9
Card Pinout .and Pin Descriptions ........ 6-10
Address Decode Logic .................. 6-12
Data Control Logic ...................... 6-12
Component Management Registers ..... 6-13
Smart Power Circuitry ................... 6-14
DEVICE COMMAND SET ............... 6-14

DC CHARACTERISTICS . ............... 6-22
General ................................. 6-22
Vee = 5V, Vpp = 12V .............. ; ... 6-23
Vee = 5V, Vpp = OV ............... ~ ... 6-24
Vee';" 3.3V, Vpp = 12V ................ 6-25
Vee. = 3.3V, Vpp = OV ..... ~ ........... 6-26
AC CHARACTERISTICS . ............... 6-27

Series 2 + Command Set ................ 6-14
Command Bus Cycle Definitions
(28F008SA-Compatible Mode) ........ 6-15
Command Bus Cycle Definitions
(Performance Enhancement Mode) .... 6-16

Common and Attribute Memory: ReadOnly Operations ....................... 6-27
Common and Attribute Memory: Write
Operations ............................ 6-29
Common and Attribute Memory: CE#Controlled Write Operations ........... 6-31

DEVICE STATUS REGISTERS ......... 6-17

ORDERING INFORMATION ............ 6-31

Compatible Status Register (CSR) ....... 6-17
Global Status Register (GSR) ............ 6-17
Block Status Register (BSR) ............. 6-18

Power-Up/Power-Do,,:,n ................. 6-33

PCMCIA CARD INFORMATION
STRUCTURE ......................... 6-18

CAPACITANCE ......................... 6-34
OPERATION TIMINGS .................. 6-34
PACKAGING ........................... 6-35

SYSTEM DESIGN
CONSIDERATIONS .................. 6-21

Power Supply Decoupling ............... 6-21
Power Up/Down Protection .............. 6-21
Hot Insertion/Removal .................. 6-21

6-7

SERIES 2 + FLASH MEMORY CARDS

,SCOPE OF DOCUMENT
"the documentation for Intel's Series 2+ Flash
Memory Card includes this data sheet and a detailed
design guide. The data sheet provideS all AC and
DC characteristics (lncliJdin!;ltiming waveforms)ahd
a convenient reference for the devicecQmmand set
lind the card's integrated registers (including the
28F016SA's status registers). The design guide (order number 297373-001) provides a complete l;Iescription of the methods for using the card. It also
.col')tains the full list of software algorithms and flowcharts and a section for upgrading from Intel's 'Series 2 Flash Memory Cards.

PRODUCT OVERVIEW
The 4 and 20 Megabyte, Series 2 + Flash Memory
. Cards cohtain a flash memory array that consists of
2 to 10 2SF016SA TSOP memory devices, respectively. Each 2SF016SA contains 32 distinct, individually-erasable, 64 Kbyte blocks; therefore, the cards
contain: 64 and 320 device blocks, respectively.
The Series 2 + Card offers additional product features to those of the Series 2. Card producUamily
(refer . to
the. iMC002FLSA, .iMCOO4FLSA,
iMC010FLSA, and iMC020FLSA data. sheets). Some
of the more notable card-level enhancements inplude: interchangeable operation at 3.3V or 5V and
internal Vpp generation.
The card incorporates Vee detect circuitry, referred
to as SmartPower, to sense the voltage level present at the card interface. The card's control logic
automatically configures its circuitry and the
2SF016SA memory array accordingly. The Card Information Structure reports that the card is 3.3V or
5V compatible. The card also detects the presence
of 12V 9n the socket Vpp pin and passes this supply
to each 2SF016SA. When 12V are unavailable, the
card generates the required Vpp via its internal Vppgeneration circuitry, whether Vee is 3.3V or 5V.
At the device level, internal algorithm automation allows write and block erase operations to be executed using a, two-write command· sequence in the
same way as the 2sFoOSSA FlashFile memory in the
Series 2 Card. A superset of commands and addi-·
tional. performance enhancements have been added
to the basic 2SFOOSSA command-set:
• Page buffer writes to flash results in writes up to
4 times faster than Series 2 Cards. .

6-8

• 'Command queuing permits the devices to receive new commands during the execution of the
currel1t command.
• ~utomatlc data writes during erase allows the
2SF016SA to perform write operations to one
block of memory while performing an erase Clri another block.

• Software locking of memory blocks provides a
means to selectively protect code or data within
the card.
· • Erase all unlocked blocks provides a quick and
simple method to sequentially erase the blocks
within a 28F016SA.
The Series 2 + Card has two means for putting its .
flash devices into· a Deep-Sleep mode for reduced '
power consumption: 1) Issue a command to individual devices, referred to as the software-controlled
Deep-Sleep mode. Using this approach the .device
will retain status register contents and finish any operation in progress: 2) Write to the card's PCMCIAcompatible Configuration and Status Register to activate a Reset-PowerDown to. all devices simultaneously.
The card achieves its PCMQIA-compatlble wordwide access by pairing the 2SF016SA devices resulting in an accessible memory block size of
64 KWords. The card's decoding logic (contained
within its ASICs) allOws the system to write or read
one word at a time, or one byte at a time by referencing the high or low byte. Erasure call be performed on the entire block pair (high and low device
block simultaneously) or on the high 'or low byte portion separately. Although the 2SF016SA supports
byte or word-wide data access, the byte interface
was utilized within the card to allow the deU)fery 91
higher performance benefits (such as the doubling
of t!'leeffective page buffer size):
The Series 2 + Card's ASICs also contain .the Component ManagementRegisters that provide fiv8 con~
trol . functions-Ready-Busy mode selection, software-controlled write protection, card status,
voltage-control and status, and. soft reset. ~.
· The memory card . interface supports the Personal
Computer Memory Card Industry Association.
(PCMCIA 2.01) and Japanese ElectrClnics Industry
Development Association (,JEIDA 4.1) 6S-pln card
format. The Series 2+ Flash Card meets all
· PCMCIAlJEIDA Type 1 mechanical specifications;

SERIES 2 + FLASH MEMORY CARDS

SERIES 2 + ARCHITECTURE OVERVIEW
As depicted in Figure 1, the Series 2 + Card consists of three major functional elements-the
28F016SA Flash Memory array, card control logic
and SmartPower circuitry. The card control logic

0< 15:0>

ZOQ<15:8>

A<25:0>

ZOQ<7:0>

REG#

ZA<20:0>

CE1#

ZWE#

CE2#
W[#

ZCEO#<7:0>

0[#
RST#
WA1T#

handles the interface between the flash memory array and the host system's PCMCIA signals. The
Smart Power circuitry provides the card's integrated
Vpp generator and a means for detecting the socket's voltage levels.

ZOE#

CARD
CONTROL
lOGIC

BV01#

ZCE1#<2:0>
ZRY /ZBY#
ZRP#
zWP

BV02#
WP
C01#

0<7:0> 28F016SA CEO#
A<20:0> Device 9 eEl#

C02#

WE#
OE#

ROY /BSY#

Vss

Vee

RY/BY#
RP#
WP
Vee vpp Vss 3/5#

J J J

Vee

Vpp

VpP2

GENERATION

Vpp

28F018SA

CEO#

WE#
OE#

WE#
RY/BY#
OE#
RP#
WP
3/5# Vss Vpp Vee

RY/BY#
RP#
WP

I I I I

VpP1

0<7:0> 28F018SA CEO#
A<20:0> Device 7 eE1#

Vee Vpp Vss 3/5#

Lij

CEO# 28F018SA
0<7:0>
eEl# Device 8 A<20:0>
WE#
RY/BY#
RP#
OE#
WP
3/5# Vss Vpp Vee

I I I I
0<7:0>

28F018SA

CEO#
Device 1 eEl#
RY/BY#
RP#
WP
Vee Vpp Vss 3/5#

A<20:0>
WE#
OE#

eEl#

0<7:0>
Device 6 A<20:0>

I! I I

1 11 "'. ~.~!P I O<~,.,

eE1#" Device 0 A<20:0>
RY/BY#
WE#
RP#
OE#
WP
3/5# Vss Vpp Vee

1 I
1

till
t--

I I
j

Vss

VS1
VS 2

SmartPower

3/5#

290491-1

Figure 1. Series 2+ Card Block Diagram Showing
Major Functional Elements Including the Card's Control Logic,
Smart Power Circuitry and the 28F016SA Flash Memory Components

~'I:
t

I.,

6-9
I

SERIES 2 + FLASH'MEMORY CARDS
The Series 2 + Card signals comply with the PCMCIA specification, as shown in Table .1. Table 2 describes the
functionality of these signals.
Table 1. Series 2+ Flash MelTlory Card Signals
::

Signal

GND

1/0

Signal

Ground

Function

Active

GND

1/0

Function

D03

I/O

Data Bit 3

CD1#

D04

I/O

Data Bit4

DOn

I/O

Data Bit 11

D05

I/O

Data Bit 5

D012

I/O

Data Bit 12

D013

I/O

Data Bit 13

D014

I/O

Data Bit 14

DOt5

I/O

D06

I/O

Data Bit 6

007

I/O

Data Bit7

CE1#

Card Enable 1

8: A10

Address Bit 10

LOW

Data Bit 15

Card Enable 2

Voltage Sense 1

OE#

Output Enable

VS1

A11

Address Bit 11

RFU

LOW

Card Detect 1

42 . CE2#

Address Bit 9

Address Bit 8

A13

Address Bit 13

A14

Addressait14

LOW

Reserved

A17

Address Bit 17

A1S

Address Bit 18

A19

Address Bit 19

WE#

Write Enable

LOW

A20

Address Bit 20

RDY/BSY#

Ready-Busy

LOW

A21

Address Bit 21

Vee

Supply Voltage

Vee

Supply Voltage

VPP1

Supply Voltage

VPf>2

Supply Voltage

19 A16

Address Bit 16

A22

Address Bit 22

Address Bit 15

A23

AddresS Bit 23

A15

LOW

Reserved

Active

Ground

A12

Address Bit 12

A24

Address Bit 24

Address Bit 7

A25

Address Bit 25

Address Bit 6

VS2

Voltage Sense 2

N.C.

Address Bit 5

RST

Reset

HIGH

Address Bit 4

WAIT#

Extend Bus Cycle

LOW

Address. Bit 3

RFU

Address Bit 2

REG #

Address Bit 1

BVD2

Batt. Volt Det 2

Batt. Volt Det 1

Reserved

Address Bit 0

BVD1

DOo

I/O

Data BitO

DOs

I/O

Data Bit 8
Data Bit 9

D01

I/O

Data Bit 1

D09

I/O

D02

I/O

Data Bit 2

DO 10

I/O

Write Protect

HIGH

CD2#

GND

6·10

Ground

LOW

Oata.Bit 10
Card Detect 2
Ground

LOW

intel~

SERIES 2 + FLASH MEMORY -CARDS

Table 2. Series 2 + Flash Memory Card Signal Descriptions
Symbol
Ao-A25

Type
I

Description
ADDRESS INPUTS: Ao through A25 are address bus lines which enable direct
addressing of 64 megabytes of memory on a card. Ao is not used in word
access. A25 is the most significant bit.

000-0015

I/O

DATA INPUT/OUTPUT: 000 through 0015 constitute the bidirectional data
bus. 0015 is the most significant bit.

CE1#,CE2#

CARD ENABLE 1,2: CE1 # enables even bytes, CE2# enables odd bytes.
Multiplexing Ao, C01 # and C02# allows a.bit hosts to access all data on OClo
through 007.

OE#

OUTPUT ENABLE: Active low signal gating read data from the memory card.

WE#

WRITE ENABLE: Active low signal gating write data to the memory card.

ROY/BSY#

READY/BUSY OUTPUT: Indicates status of internally timed erase or write·
activities. A high output indicates the memory card is ready to accept accesses.
A low output indicates that a device(s) in the memory card is(are) busy with
internally timed activities.

C01#, C02#

CARD DETECT 1,2: These signals provide for correct card insertion detection.
They are positioned at opposite ends of the card to detectproper alignment. The
signals are connected to gro!Jnd internally on the memory card and will be
forced low whenever a card is placed in the socket. The host socket interface
circuitry shall supply 10K or larger pull-up resistors on these signal pins.

WRITE PROTECT: Write Protect reflects the status·of the Write-Protect switch
on the memory card. WP set high = write protected, providing internal hardware
write lockout to the flash array.
WRITE/ERASE POWER SUPPLY: (12V nominal) for erasing memory array
blocks or writing data in the array. They must be 12V to perform an erase/write
operation, when not using the card's integrated Vpp generator. These signals
may be disconnected but are required for ExCA compliance.

VPPh VPP2

CARD POWER SUPPLY: (3.3V /f$V nominal) for all internal circuitry.

Vee
GNO

GROUND for all internal circuitry.

REG#

REGISTER SELECT: Provides access to Series 2+ Flash· Memory Card
registers and Card Information Structure in the Attnbute Memory Plane.

RST

RESET: Active high signal from system for placing card in
State.

WAIT#

WAIT: (Extend Bus Cycle) Used by Intel's I/O cards and is driven high.

BV01, BV02

BATTERY VOLTAGE DETECT: Upon completion of the power on reset cycle,
these Signals are driven high to maintain SRAM·card compatibility.

VS1, VS2

VOLTAGE SENSE: Notify the host socket of the card's Vee 'requirements. VS1
is grounded and VS2 open indicates a 3.3V /5V card as depicted in the CIS.

Power~On

RFU

RESERVED FOR FUTURE USE.

N.C.

NO INTERNAL CONNECTION. Pin may be driven or left floating.

Default

6-1f

.'.ft'tel"
"'.'". ' '
1
.1181 '

SERIES 2 + :FLASHMEMORV CARDS

WE#, OE#,CEf#, andCE2# as logic inputs. The
Data Control logic selects any of the PCMCIAWord.
Wide, Byte-Wide, lind Odd~Byte modes' for either
ijeads or Writes to Common or Attribute Memory. All
accesses to, the Attribute Memory Plane must be
, made through 07-0; no valid data can be written on
the high byte. Reads of 015-8 will yield FFH

CARD CQNTROL LOGlC
The.C~rdControl Logic, contained within tWo ASICs,
handlell.the address decoding. find data control for
,the Series 2 + Card. The card's Component Management Registers are also contained within the
Card Control Logic.

ODD,BYTE

EVEN BYTE

MEMORY
ADDRESS

ADDRESS DECODE ,LOGIC
At the highest level,' the Address Decode section
determines when to select. the Common Memory
(REG# = VI H) or Attribute Memory (REG# = VIU
Planes. Within the Attribute Memory Plane, the address decode logic determines when to select the
Card Information Structure (CIS) or Component
Management Registers (CMR). The CIS is contained
at even-byte locations beginning at addressOOOOH.
The CMRs are, mapped at even-byte locations be- .
ginning at address 4000H as shown in Figure 2.

1FFFFFH
004200H
004000H

000100H

OOOOOOH

Figure 2. Attribute Memory Plane

DATA CONTROL LOGIC
As shown in Table 3, data paths and directions are
selected by the Data Control logic using REG#, Ao. '

Table 3. Data Access Mode Truth Tables
MODE

REG#

CE2#

CE1#

OEiI!

WE#

VPP2

VPP1

015-8

07-0'

•,COMMON MEMORY PLANE
STANDBY
BYTE-READ

WORD-READ
ODDBYTE READ

VIH

VIL

VIH

VIL

VIH

X
X

" VIH

VIL

VIH

VIL

¥IH. '

X
"

VPPL

VPPL'

HIGH-Z

EVEN-BYTE

VIL

VIH

VPPL

VIL

ViH

VPPL

HIGH-Z

ODD-B'0'E

VPPL

ODD-BYTE

EVEN-BYTE

VIL

VIH

VPPL

'VIL

VIH

VpPL VPPL ODD-BYTE

HIGH~Z

' VIH

VIH

VIL

VIH

VIL

XXX

VPPH

Xxx

VIH

VIL

VIH

VIL

VPPH

XXX

WORD-WRITE

VII>!

VII_

Vil

VIH

VIL

VPPH

VPPH ODD-BYTE

EVEN-BYTE

ODDBYTE WRITE

VIH

VIL

VIH

' ¥IH'

VIL

VPPH

VPPL ODD-BYTE

XXX

BYTE,WRITE

EVEN-BYTE
ODD-BYTE

ATTRIBUTE MEMORY PLANE

VIH

VpPL

HIGH-Z

VIL

VIH

VIL,

¥IL

VIL

,VIH

VPPL· VPPL

HIGH-Z

VIL

VIH

VIL

VIH

V1L

VIH

VpPL

HIGH-Z

FFH"

WORD-READ

VIL

VIH

VpPL

FFH

EVEN-BYTE

ODDBYTE READ

VIL

VIH

VIL

VIH

VPPL

FFH

HIGH-Z

BYTE WRITE

VIL

VIH

V1L

VIL

VIH

VIL

VPPL

VpPL

XXX

EVEN-BYiE

XXX
XXX
XXX

EVEN-BYTE

STAND.BY
BYTE-READ

VPPL

VIL

VIH

VIL

VIH

VIL

VPPL

WORD-WRITE

VIL

VIH

VIL

VPPL

ODDBYTE WRITE

VIL

V1H

X
X

VIH

VIL, ' VPPL

VPPL

" HIGH-Z
EVEN-BYTE

XXX

XXX'

SERIES 2 + FLASH MEMORY CARDS

COMPONENT MANAGEMENT
REGISTERS

4100H-Card Status Register
(Intel-READ ONLY)

The Component Management Registers (CMRs) are
classified into two categories: those defined by
PCMCIA R2.0 and those included by Intel to enhance the interface between the host system and
the card's flash memory array. The CMRs provide
five control functions-Ready-Busy Mode selection,
Voltage Control, Software-controlled Write Protection, Card Status, and Soft Reset.

BIT 5 SOFT RESET
- Mirrors the SRESET Bit
(7) of the Configuration
Option Register.
1 = RESET
BIT 4 COMMON
MEMORYWP
- Indicates the Write
Protect Status of the
Common Memory
Plane, Minus the
CMCIS.

Card Register Tables
4000H-Configuration Option Register
(PCMCIA)

BIT 7 SOFT RESET
1 = Reset to Power On
State
= End Reset Cycle

rREsERvEo,l SRESET 1CMWP 1PwrOwn 1CISWP 1WP 1ROYIBSY " J
6 1 5
1 4 1 3 1 2 111
0
J

I7 I

BIT 3 POWER DOWN
- Reflects the PwrDwn
Bit (2) of the
Configuration and
Status Register.
1 = POWER DOWN

BITS 6-0
- Driven Low

BIT 2 COMMON
MEMORY CIS WP
- Indicates the Write
Protect Status of the
Common Memory CIS.
1 = WRITE
PROTECTED
BIT 1 WRITE PROTECT
SWITCH
- Reports the Status of
the Card's Mechanical
Write Protect Switch.
1 = WRITE PROTECT
SWITCH ON
BIT 0 READY IBUSY #
- Mirrors the Card's
RDY/BSY# Pin
1 = READY

Default·

1H or 3H

Default: 02H

4104H-Write Protection Register (Intel)
4002H-Configuration and Status Register
(PCMCIA)

BIT 2 POWER DOWN
1 = Force All Devices Into Deep Sleep via the
Device's RP# Pin. All Device Register
Contents are Lost.
= Power Up
Default:

RESERVED'

BIT 2 BLOCK LOCKING
ENABLE
1 = Enable Independent
28F016SA Block
Locking.
= All Blocks Unlocked.

o
OOH

BIT 1 COMMON
MEMORYWP
1 = Force Common
Memory, Minus the
CMCIS, to Write
Protected Status.
= WriteProtect
According to
Independent
27F016S Block
Locking.

BL:EN

CMWP
1

CI:WP

BIT 0 COMMON
MEMORY CIS WP
1 = Force Only the
Common Memory
CIS Into Write
Protected Status.
= Write Protected
According to
Independent
28F016SA Block
Locking.

Default: 04H

6-13

SE~IES 2

+ FLASH MEMORY CARDS

410CH-'Voltage Control Reglster·(lntel)

BIT 7 Vee LEVEL
1 - Host Supplying
3.3V.
0= Host Supplying 5V.

BIT 0 Vee GENERATION
1 - Turn on Integrated
Vpp Generator
o = Turn off Integrated
. VppGenerator

BIT 1 Vpp VAblD
1 = Vpp Between 11.4V
and 12.6V
o = Vpp Invalid.

Default;. 82H or 02H

4140H-Ready/Busy Mode Register (Intel)

RESERVED'

BIT 1 READY
ACKNOWbEDGE
- Clear to Set up ROY /
BSY # Pin. Then Clear
After Each Becomes
Ready to Acknowledge
TranSition.

I
2

RACK

MODE

1·0

Series 2 + Command Set
Code (H)

Series 2-Compatible Mode

Invalid/Reserved

Byte Write

Single Block Erase

Byte Write

Clear Status Register

BIT 0 ROYIBSY #. MODE

Read Compatible Status Register

1 = High Performance
Mode
o = PCMCIA Level
Mode

Intelligent Identifier

Erase Suspend

Erase Confirm/Resume

Read Array

Default OOH

NOTE:
"Reserved bits should be zero (low) to insure future
compatability.

SMART POWER
The Smart Power circuitry generates and monitors
the card's programming VOltage. When a host system does not provide a Vpp supply, the card's integrated generator can be switched on via the card's
Voltage Control Register. The Smart Power circuitry
also detects the host system's VCC level (3.3V or
5V) and configures the card's flash mem()ry devices
accordingly (using the 2BF016SA 3/5# pin as
shown in Figure 1).

DEVICE COMMAND SET
The 28F016SA-based Series 2+ Command Set increases functionality over earlier 2BFOOB-based de-

6-14

signs while maintaining backwards compatibility.
The extended 2BF016SAcommand set supports
many new features to improve programmability and
write performance such as: page buffered writing.
individual block-locking, multiple ROY /BSY # configurations and device level queuing capabilities. The
following pages .list the. Series 2 + .command set and
Bus Cycle Operations overview.

Code (H)

Series 2 + Performance
Enhancement

Page Buffer Write to Flash

Read Extended Status Registers

Page Buffer Swap

Single Load to Page Buffer

Read Page Buffer

Lock Block

Abort

RY /BY # Reconfiguration

Status Bits Upload

Erase All Unlocked Blocks

Sequential Load to Page Buffer

Sleep

SERIES 2 + FLASH MEMORY CARDS

Command Bus Cycle Definitions (28F008SA·Compatlble Mode)
First Bus Cycle
Command

Second Bus Cycle

Data

R/W

Adrs.

x16

Read Array

FFH

Intelligent Identifier

ReadCSR

Notes

Data

R/W

Adrs.

FFFFH

90H

9090H

70H

7070H

CSRD

eSRD

x16

Clear Status Register

50H

5050H

Word/Byte WriteS

40H

4040H

Word/Byte Write (Altemate)§

10H

1010H

Block Erase/Confirm§

20H

2020H

DOH

DODOh

Erase Suspend/Resume

BOH

BOBOH

DOH

DODOh

ADDRESSES:
DA
= Device Address
BA
= Block Address
IA
= Identifier Address
WA
= Write Address
§ =

DATA:
AD
CSRD
10
WD

=
=
=
=

Array Data
CSR Data
Identifier Data
Write Data

Queueable Commands

NOTES:
1. The CSR is automatically available after the device enters Data Write, Erase or Suspend operations.
2. This command clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and BSR.5 and BSR.2 bits.

6-15

intel®

S~RIES 2 +.FLASH,MEMORY .CARDS

Command Bus Cycle Definitions (28F016SA Superset Mode)
First Bus Cycle

.
. Command
R/W

Adrs.

Third Bus Cycle

Second Bus Cycle

Data
x8'

x16

Data

R/W • Adrs.

R/W

x16

Adrs•

Data
x8

Notes

x16

PAGE BUFFER CONTROL
Read Page Buffer

75H

7575H

PO PO

PDPD

Page Buffer Swap

12H

7272H

Single load to Page
Buffer

74H

7474H

Sequential load to
Page Buffer

EOH

EOEOH

BCl

BCH

2,3

Page Buffer Write to
Flash Array§

OCH

OCOCH

BC(L,H)

BC(H,L)

2,3,4

96H

9696H

READY IBUSY CONFIGURATION
0303H

RY IBY # Pulse·On·
Erase§

RY/BY# Pulse-OnWrite§

96H

9696H

02H

0202H

RY/BY# Enable§

96H

9696H

01H

0101H

RY IBY # Disable§

96H

9696H

04H

0404H

03H

WRITE PROTECTION AND DEVICE STATUS
Lock Blockl Confirm§

77H

7777H

DOH

DODOH

Upload Status Bitsl
Confirm§

97H

9797H

DOH

DODOH

ADDITIONAL FUNCTIONS
Read Extended
Registers

71H

7171H

GSRD/BSRD

Erase All Unlocked
Blocks/Confirm§

A7H

A7A7H

DOH

Sleep

FOH

FOFOH

Abort

SOH

SOSOH

ADDRESSES:
DA = Device Address
BA = Block Address
IA
= Identifier Address
PA = Page Buffer Address
RA = Extended Register Address
WA = Write Address
= Don't Care
X

DATA:
AD
CSRD
G/BSRD

10
WD
PO

=
=
=
=
=
=

Array Data
CSR Data
GSR/BSR Data
Identifier Data
Write Data
Page Buffer Data

DODOH

DATA COUNTS:
WC(L,H) = Word Count (Low, High)
BC(L,H) = Byte Count (Low, High)
WD(L,H) = Write Data (Low, High)

§ = Queueable CommandS
NOTES:
1. This command allows the user to swap between available page buffers (0 or 1).
2. BCH/WCH must be at OOH for this product because of the 256-byte Page Buffer size AND to avoid writing the Page
Buffer contents into more than one 256"byte segment within an array block. They are simply shown for Page Buffer expandability.
3. Page Address and Page Data (whose count is given in cycles 2 and 3) are supplied starting in the 4th cycle (not shown).
4. AO is automatically complemented to load the second byte of data.
5. These commands reconfigure RY IBY # output to one of two pulse modes, or they enable and disable the RY IBY # function.
6. Upon device power-up, all BSR lock bits are locked. The Lock Status Upload command must be written to reflect the
actual lock bit status.
7. RA can be the GSR address or any BSR address.

6·16 .

SERIES 2 + FLASH MEMORY CARDS

DEVICE STATUS REGISTERS
Each 2BF016SA has three types of status registers:
the Compatible Status Register, the Global Status
Register and the Block Status Register. The Compatible Status register is identical to the 28FOOBSA
Status Register. The Global Status Register provides queue and page buffer information about each
device. Each block within the device has a Block
Status Register assigned to it. The BSR contains the
Block-Locking Status and other information specific
to the block being addressed.
Compatible Status Register (CSR)

CSR.7 WRITE STATE
MACHINE STATUS
1 = Ready
0= Busy
CSR.B ERASE SUSPEND

IIAIYI

1 = Erase Suspended

Erase in Progress!
Completed

CSR.5 ERASE STATUS
1 = Error in Block
EraSUre
o = Successful Block
Erasure

CSR.4 DATA-WRITE

STmlI
1=

Error in Data Write
Data Write
Successful

CSR.S V-SWUS
1 - Vpp Low Detected,
Operation Aborted
0= VppOK

Global Status Register (GSR)

I
~

GSR.7 WRITE STATE
MACHINE STATUS
1 - Ready
0= Busy

1 = unA...,.nn

Suspended
Operation in
Progress!
Completed

GSR.5 DEVICE
OPERATION STATUS
1 - Opel'ation
Unsuccessful
0= Operation
Successful or
Running
G$R.4 DEVICE SLEEP!

§IIIII!
1 = Device in Sleep

GSR.' QUEUE STATUS
1 - QueueFull
o =' Queue Available
GSR.2 PAGE BUFFER
AVAILABLE STATUS
1 - One or Two Buffers
. Available
o = No Page Buffer
Available
I.

GSR.1 PAGE BUFFER

IIAIYI

1 = Selected Page

Buffer. Ready
Selected Page
Buffer Busy

GSR.O PAGE BUFFER
SELECT STATUS
1 - Page Buffer 1
Selected
o = Page Buffer 0
Selected

Device Not in Sleep
Default: BEH

~
Reserved
Default: BOH

6-17

intel®

SERIES 2 + FLA§HMEMORY CARDS

PCMCIA CARD INFORMATION
STRUCTURE

BloCk Status Register (BSR)

.as

The Card Information Structure begins at address
OOOOOOOH of the card's Attribute Memory 1'lane. It
contains a variable·length chain of data blocks (tuples) that conform to a basic format (Table 4). The
CIS of the Series 2 + Flash Memory Card is found in
Table S.

BSR.7 BLOCK STATUS.
1 ';Ready
..
.
0= ,Busy
BSR.6 BLOCK-LOCK
STATUS
1 = . Block Unlocked
o = Block Locked
BSR.5BLOCK
OPERATION STATUS
1 - Operation
Unsuccessful
o = Operation
Successful or
Running

BSR.4BLOCK
OPERATION ABORT
STATUS
1 = Operation Aborted
o = Operation Not
Aborted

Table 4. PCMCIA Tuple Format

BSR.3 QUEUE STATUS
1 -. Queue Full
o = Queue Available

BYTES

BSR.2 Vpp STATUS
1 = Vpp Low Detect
0= VppOK

TUPLE CODE: CISTPL-xxx. The
tuple code OFFh indicates no more
tuples in the list.

TUPLE LINK: TPLLlNK. Link to the
next tuple in the list. This can be
viewed as the number of additional
bytes in tuple, excluding this byte. If
the link field is zero, the tuple body is
empty; If the link field contains OFFh,
this tuple is the lasttuple in the list.

BSR.1-0 RESERVED
Default: COH

DATA

2-n

Bytes specific to this tuple.

Table 5. Series 2 + Tuples
Value

Description

1AH

17H

CISTPLDEVICEJ

1CH

04H

TPLLlNK

Address

Value

Description

Address

OOH

01H

CISTPL DEVICE

02H

04H

TPLLlNK

04H

57H

FLASH

1EH

1FH

ROM

06H

22H
2AH

1S0 ns
200 ns

20H

22H

1S0ns

OEH
4EH

CARD SIZE
4MB
20MB

08H

22H

01H

2 Kb

24H

FFH

END OF DEVICE

26H

1DH

CISTPLDEVICLOA

28H

OSH

TPLLlNK

OAH

FFH

END OF DEVICE

OCH

1CH

CISTPLDEVICLOC

2AH

02H

OTHER CONDITIONS-3 Vee

17H

ROM
200 ns

OEH

OSH

TPLLlNK

2CH

10H

02H

. OTHER CONDITIONS-3 Vee

2EH

2AH
. 01H

2Kb

12H

S7H

FLASH

30H

14H

2AH

200 ns

32H

FFH

. END OF DEVICE

18H

CISTPLJEDEC_C

OEH
4EH

CARD SIZE
4MB
20MB

34H
36H

02H

TPLLlNK

38H

89H

INTELJ-ID

FFH

END OF DEVICE

3AH

AOH

28F016J-ID

3CH

OOH

Null Control Tuple

16H
18H

6-18

SERIES 2 + FLASH MEMORY CARDS

Table 5. Series 2 + Tuples (Continued)
Value

Description

Address

Value

Description

3EH

15H

CISTPL VERS 1

40H

39H

TPLLlNK

7CH

65H

7EH

6CH

42H

04H

TPLLV1_MAJOR

80H

20H

SPACE

44H

01H

TPLLV1_MINOR

82H

43H

84H

4FH

46H

49H

TPLLV1_INFO
I

86H

52H

48H

6EH

88H

50H

4AH

74H

8AH

4FH

4CH

65H

8CH

52H

4EH

6CH

8EH

41H

50H

OOH

END TEXT

90H

54H

52H

53H

54H

32H

Address

92H

49H

94H

4FH

56H

45H

96H

4EH

58H

34H
32H

4MB
20MB

98H

20H

SPACE

5AH

20H
30H

4MB
20MB

9AH

31H

9CH

39H

53H

9EH

39H

20H

SPACE

AOH

33H

57H

A2H

20H

SPACE

20H

SPACE

A4H

47H

OOH

ENDTEXT

A6H

4CH

41H

5CH

5EH

60H
62H

43H

A8H

64H

4FH

AAH

44H

ACH

45H

4BH

K
END TEXT

66H

50H

68H

59H

AEH

6AH

52H

BOH

OOH

6CH

49H

B2H

FFH

END OF LIST

1AH

CISTPLCONF
TUPLLlNK

6EH

47H

B4H

70H

4814

B6H

05H

72H

54H

B8H

01H

TPCC_SZ

04H

TPCC_LAST

74H

20H

SPACE

BAH

76H

49H

BCH

OOH

TPCC_RADR

BEH

40H

TPCC_RADR

78H

6EH

7AH

74H

6·19

SERIES 2 + FLASH MEMORY CARDS
Table 5. Series 2 + Tuples. (Continued)
!Address Value
COH

03H

Description

Address Value

TPCC_RMSK

C2H

OOH

NULL CONTROL TUPLE

C4H

1BH

CISTPLCFTABLE_ENTRY

C6H

08H

TPLLlNK

C8H

01H

TPCE_INDEX (01H)

CAH

01H

TPCE_FS (Vcc ONLY)

CCH

7.9H

TPCE_PD
Vcc PARAMETER SELECTION
BYTE

Description
TPCE_PD
Vcc PARAMETER SELECTION
BYTE

102H

79H

104H

B5H

Vcc = 3.3V

106H

1EH

EXTENSION BYTE

108H

'04H

Icc STATIC 1 rnA

10AH

1EH

ICC AVERAGE 150 rnA

10CH

1EH

Icc PEAK 150 rnA

10EH

53H

Icc PWRDWN 500 /LA

CEH

55H Vcc NOMINAL VOLTAGE 5V ±5%

110H

1BH

CISTPLCFTABLE_ENTRY

DOH

53H

Icc STATIC 500 /LA

112H

10H

TPLLlNK

D2H

1EH

ICC AVERAGE 150 rnA

114H

04H

TPCE_INDEX (04H)

D4H

1EH

Icc PEAK 150 rnA

116H

02H

TPCLFS (Vcc AND Vpp)

118H.

79H

TPCE_PD
Vcc PARAMETER SELECTION
BYTE

11AH

B5H

Vcc = 3.3V

D6H

1BH

Icc PWRDWN 200 /LA

D8H

1BH

CISTPLCFTABLE_ENTRY

DAH

OFH

TPLLlNK

DCH

02H

TPCLINDEX (02H)

DEH

02H

TPCE_FS (Vcc AND Vpp)

EOH

79H

TPCE_PD
Vcc PARAMETER SELECTION
BYTE

E2H

55H Vec NOMINAL VOLTAGE 5V ±5%

E4H

2BH

11CH

1EH

EXTENSION BYTE

11EH

2BH

Icc STATIC 250 /LA .

120H

06H

Icc AVERAGE 100 rnA

122H

06H

Icc PEAK 100 rnA

124H

52H

Icc PWRDWN 50 /LA

126H

79H

TPCE_PD
Vpp PARAMETER SELECTION
BYTE

Icc STATIC 250 /LA

E6H

06H

Icc AVERAGE 100 rnA

E8H

06H

Icc PEAK 100 rnA

EAH

52H

Icc PWRDWN 50 /LA

ECH

79H

128H

8EH

12.0V ±5%

12AH

7DH

NC OK ON STANDBY &PWD

TPCE_PD
Vpp PARAMETER SELECTION
BYTE

12CH

53H

IppSTATIC 500/LA

12EH

25H

Ipp AVERAGE 20 rnA

EEH

8EH

12.0V ±5%

130H

25H

IppPEAK20 rnA

FOH

7DH

NC OK ON STANDBY & PWD

132H

1BH

Ipp PWRDWN 150 /LA

F2H

53H

Ipp STATIC 500 /LA

134H

OOH

NULL CONTROL TUPI,.E

F4H

25H

Ipp AVERAGE 20 rnA

136H

OOH

NULL CONTROL TUPLE

25H

Ipp PEAK 20 rnA

138H

1EH

CISTPL DEVICEGEO

F6H
F8H

52H

Ipp PWRDWN 50 /LA

13AH

06H

TPLLlNK

FAH

1BH

CISTPLCFTABLE_ENTRY

13CH

02H

DGTPLBUS

FCH

09H

TPLLlNK

13EH

11H

DGTPLEBS

FEH

03H

TPCE_INDEX (03H)

140H

01H

DGTPLRBS

100H

01H

TPCE_FS (Vcc ONLY)

142H

01H

DGTPLWBS

SERIES 2 + FLASH MEMORY CARDS

Table 5. Series 2 + Tuples (Continued)
Description

Address

Value

144H

01H

DGTPLPART= 1

146H

01H

FLASH DEVICE INTERLEAVE

148H

20H

CISTPL MANFID

14AH

04H

TPLLlNK (04H)

POWER UP/DOWN PROTECTION

14CH
14EH

89H
OOH

TPLMID_MANF
LSB
MSB

150H

12H
42H
11H
41H

4 MB-150 ns
20 MB-150 ns
4 MB-200ns
20 MB-200 ns

The PCMCIAlJEIDA specified socket properly sequences the power supplies and control signals to
the flash memory card via shorter and longer pins.
This assures that hot insertion and removal will not
result in card damage or data loss.

152H

83H
84H

TPLMID_CARD MSB
TPLMID_CARD MSB

154H

21H

CISTPLFUNCID

156H

02H

TPLLlNK

158H

01H

TPLFID_FUNCTION
(MEMORY)

15AH

OOH

TPLFID_SYSiNIT
(NONE)

15CH

FFH
OOH

CISTPL-END
INVALID ECIS ADDRESS
(15EH-1FEH)

SYSTEM DESIGN CONSIDERATIONS
~

The card connector should also have a 4.7 ,...F electrolytic capacitor between Vee and GND, as well as
between VpP1IVPP2 and GND. The bulk capacitors
overcome voltage slumps caused by printed-circuitboard trace inductance, and supply charge to the
smaller capacitors as needed.

POWER SUPPLY DECOUPLING

Flash memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current issues: standby, active and transient current peaks which are produced by rising and falling edges of CE1 # and
CE2 #. The capacitive and inductive loads on the
card and internal flash memory device pairs determine the magnitudes of these peaks.

Each device in the card is designed to offer protection against accidental erasure or writing, caused by
spurious system-level signals that may exist during
power transitions. The card will power up into the
read state.
A system designer must guard against active writes
for Vee voltages above VLKO when Vpp is active.
Since both WE# and CE1 # must be low for a command write, driving either to VIH will inhibit writes.
With its control register architecture, alteration of device contents only occurs after successful completion of the two-step command sequences. While
these precautions are sufficient for most applications, an alternative approach would allow Vee to
reach its steady state value before raising VPP1/
VPP2 above Vee + 2.0V. In addition, upon powering
down, VPP1IVPP2 should be below Vee + 2.0V before lowering Vee.
NOTE:
The Integrated Vpp generator defaults to the power
off condition after reset and system power up.
HOT INSERTION/REMOVAL

The capability to remove or insert PC cards while the
system is powered on (Le., hot insertion/removal)
requires careful design techniques on the system
and card levels. To design for· this capability consider card over-voltage stress, system power droop
and control line stability.

Three-line control and proper decoupling capacitor
selection suppress transient voltage peaks. Series
2 + Cards contain on-card ceramic decoupling capacitors connected between Vee and GND, and between VPP1IVpP2 and GND.

6-21

intel®

SERtES 2 + FLASH MEMORY CARDS

OPERATION SPECIFICATIONS
ABSOLUTE· MAXIMUM RATINGS·
Operating TEilmperature
During Read .................. 0·Cto +60·C(1)
During Erase/Write .............. O·C to + 60·C
Storage Temperature .......... -30·C to + 70·C(2)
Voltage on Any Pin with
Respect to Ground ... - 2.0V to + Vee + 2.0V(2)

NOTICE: This data .sheet contains information on
produCts in the sampling and initial production phases
of development. The specifications are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet before finalizing a design.

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Vpp1IVpp2 Supply Voltage with
RespeCt to Ground .
during Erase/Write ....... - 2.0V to + 14.0v(2, 3) .
Vec SupplyVoltage with
Respect to Ground ............ - 0.5V to + 6.0V
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum O.C. input voltage is -0.5V. During transitions, inputs may undershoot to 2.0V for periods less than 20 ns.
Maximum D.C. voltage on output pins is Vee + 0.5V, which may overshoot to Vee + 2.0V for periods less than 20 ns.
3. Maximum D.C. input voltage on VPP1IVPP2 may overshoot to + 14.0V for periods less than 20 ns.

OPERAtiNG CONDITIONS
Symbol
Vee3.3
Vee5

Parameter

Min

Max

Units

Vee Supply Voltage (5%)

3.0

3.6

4.75

5.25

Vee Supply Voltage (5%)

SERIES 2 + DC CHARACTERISTICS, GENERAL
Symbol

Parameter

ILl

Input Leakage Current

ILO

Output Leakage Current

Notes

Min

Max

Units

1,3

±1

±20

p,A

±1

±20

p,A

Test Conditions
Vee = Vee MAX
VIN = Vee or GND
Vee

= Vee MAX
= VeeorGND

Your
VIL

Input Low Voltage

-0.5

0.8

Min = - 0.3V for
3.3VVee

VIH

Input High Voltage

0.7Vee

Vee +0.3

Max = Vee + 0.5V
for 5VVee

VOL

Output Low Voltage

0.4

Max = 0.45V for 5V
W/IOH = -2.0 mA

VOH1

Output High Voltage
(@3.3V)

2.4

VOH2

Output High Voltage
(@5.0V)

0.85Vee

VPPL

Vpp during Read Only
Operations

1,2

0.0

6-22

6.5

IOH

-2.5I"!lA

SERIES 2 + FLASH MEMORY CARDS

SERIES 2 + DC CHARACTERISTICS, GENERAL (Continued)
Symbol

Parameter

Notes

Min

Max

Units

VPPH

Vpp during Read/Write Operations

11.4

12.6

VLKO

Vee Erase/Write Lock Voltage

2.0

Test Conditions

NOTES:
1. Values are the same for byte and word wide modes and for all card densities.
2. Block Erases/Data Writes are inhibited when Vpp and VPPL are not guaranteed in the range between VPPH and VPPL.
3. Exceptions: With VIN = GND. the leakage on CE1 #. eE2#. REG#. OE# and WE# will be S:500 ,...A due to internal pull
up resistors and. with VIN = Vee. RST leakage will be S:500 IJ.A due to internal pull-down resistors.

SERIES 2+ DC CHARACTERISTICS(1)
Symbol

Parameters

Density
(Mbytes)

Notes

Vee = 5V, vpp = 12V

xSMode
Typ

Max

x16 Mode
Typ

Max

Units

Test
Conditions

leCR

Vce Read
Current

4,20

2,3

120

rnA

Vec = Vee MAX
tcYCLE = 150 ns

Icew

Vee Write
Current

4,20

2,3

120

rnA

Data Write in
Progrfilss

lecE

Vee Erase
Current

4,20

2,3

100

rnA

Block (Pair)
Erase in
Progress

leesL

Vee Sleep
Current

IJ-A

Ices

Vee Standby
Current

4,20

2,3

115

170

210

IJ-A

Vec = Vec MAX
Control Signals
= VIH

Ippw

Vpp Write
Current (Vpp =
VPPH)

4,20

2,3

rnA

Data Write in
Progress

IpPE

VPP Erase
Current (V pp
VPPH)

4,20

2,3

rnA

Block (Pair)
Erase in
Progress

IpPSL

VppSleep
Current

VPP

= OV

IpPS1

VPP Standby or
Read Current
(Vpp ~ Vce>

VPP

= OV

4
20
4
20

2,3

IJ-A

NOTES:
1. All currents are RMS values unless otherwise specified. Typical Vee = 5V. Vpp = 12V, T = 25°C.
2. Two devices active in word mode, one device active in byte mode.
3. Currents are not added in for devices not accessed or in sleep mode.

6-23

inte!®

SERIES 2 + FLASH MEMORY CARDS

SERIES 2 + DC CHARACTERISTICS,CMOS(1} vcc = 5V, vpp= OV··
Symbol

Parameters

Density
(MBytEls)

Notes

x8Mode
Typ

Max

x16Mode
Typ

Max

Test
Conditions

Units

ICCR

Vcc Read
Current

4,20

2,3,4

120

Vcc = MAX
\cYCLE = 150 ns

.Iccw

VccWrite
Current

4,20

2,3,5

119

150

Data Write in
Progress

ICCE

VccErase
Current

4,20

2,3,5

104

150

Block Erase in
Progress

ICCSL

Vcc Sleep
Current

Iccs

VccStandby
Current

20
4,20

3,4

p,A

115

110

250

p,A

Vcc = Vcc MAX
Control Signals
= VIH

•• Ipp specs not Incluclecl because all Ipp IS derived from Icc via the Internal Vpp Generation Circuitry.

NOTES:
1.
2.
3.
4.
5.

All currents are RMS values unless otherwise specifiecl. Typical Vcc = 3.3V, Vpp = 12V, T = 25'C.
Two devices active in word mode, one device active in byte mode.
Currents .are not added in for devices not accessed or in sleep mode.
Vpp Generation Circuitry turned off.
Vpp Generatio.n Circuitry turned on.

6·24

SERIES 2 + FLASH MEMORY CARDS

SERIES 2+ DC CHARACTERISTICS(1}
Symbol

Parameters

Density
(MBytes)

Notes

vcc

3.3V, vPP

.,x8Mode
Typ

Max

Typ

Teat
Conditions

Units

Max

ICCR

Vcc Read
Current

4,20

2,3

rnA

Vcc = Vcc MAX
tCYCLE = 200 ns

Iccw

VccWrite
Current

4,20

2,3

rnA

Data Write in
Progress

ICCE

VccErase
Current

4,20

2,3

rnA

Block (Pair)
Erase in
Progress

ICCSL

VccSleep
Current

Iccs

VccStandby
Current

Ippw

VccWrite
Current (Vpp
VPPH)

IpPE

VccErase
Current (Vpp
VpPH)

IpPSL

VccSleep
Current

IpPS1

VccStandby
or R~ad
Current (Vpp ::;;
Vce>

115

250

p.A
p.A
p.A

2,3

4,20

2,3

Data Write in
Progress

4,20

2,3

rnA

Block (Pair)
Erase in
Progress

p.A
p.A
p.A
p.A

VPP

Vpp

4
20

2,3

Vcc = Vcc MAX
Control Signals
= VIH

4,20

12V

x16Mode

NOTES:
1. All currents are RMS values unless otherwise specified. Typical Vee = 3.3V, Vpp = 12V, T = 25°C.
2. Two devices active in word mode, one device active in byte mode.
3. Currents are not added in for devices not accessed or in sleep mode.

6-25

SERIES 2 + FLASH MEMORY CARDS
SERIES

DC CHARACTERISTICS(1) vcc = 3;3V, Vpp= OV··

Parameter.

SYlflbQl

, Density
(""Byte.)

VceRead
Current

4,20

VctWrite
Current

4,20

ICCE

VccErase
CUrrent

4,20

ICCSL

VccSleep
Current

.' 4

VccStandby
Current

4;20

ICCR

Iccw

Iccs

Note.

x8Mode.
Typ
,,

Max

x16Mode
Typ

Max

Te.t
Condition.

Unit.

Vcc = Vcc MAX
tcVCLE = 200 ns

2,3,5

100

177

Data Write in
.Progress

2,3,5

134

Block (Pair)
Erase in
Progress

JJ.A
JJ.A
/A:A

2,3,4
I

20
3,4

20,

155

110

250

Vcc = Vcc MAX
Control Signals
= VIH

•• Ipp specs not Included because all Ipp IS derived from Icc via the internal Vpp Generation Circuitry.
NOTES:
1. All currents are RMS values unless otherwise specified. Typical Vee = 3.3V. Vpp = 12V. T = 25°C.
2. Two devices active in word mode, one device active in byte mode •.
3. CurreniS·are not added In for devices not accessed or In t;lleep mode.
4. Vpp Generation Circuitry tumed off.
5. Vpp Generation Circuitry tumed on.

.6-26

SERIES 2 + FLASH MEMORY CARDS

AC CHARACTERISTICS
AC Timing Diagrams and characteristics are guaranteed to meet or exceed PCMCIA Release 2.01 spec-

COMMON AND ATTRIBUTE MEMORY
Symbol

ifications. No delay occurs when switching between
the Common and Attribute Memory Planes.

Read-OnlyOperations

Parameter

150 ns .

Notes

200ns

Units

JEDEC

PCMCIA

tAVAV

tRC

Read Cycle Time

tA.VQV

ta (A)

Address Access Time

150

200

tELQV

ta (CE)

Card Enable Access Time

150

200

tGLQV

ta (OE)

Output Enable Access Time

100

tEHQX

tdis (CE)

Output Disable Time from CE #

Min

150

tdis (OE)

Output Disable Time from OE #

tGLQX

ten (CE)

Output Enable Time From CE #

tELQX

ten (OE)

Output Enable Time from OE #

tsu (Vce>

Min

Max

200

tGHQZ

tpHQV

Max

90
5

ns
ns

Powerdown Recovery to
Output Delay. Vcc = 5V

530

Powerdown Recovery to
Output Delay. Vcc = 3.3V

670

CE Setup Time on Powerup

i;~
!.,,'
I'"~

i
I
I

m
N
CX>

1ft

in
U)

Vee POWER-UP

DEVICE AND
ADDRESS SELECTION

STANDBY

N
OUTPUTS ENABLED

DATA VALID

STANDBY

Vee POWER-DOWN

YIH
ADDRESSES (A)

!j;

ADDRESSES STABLE

(/)

::J:

YIL

I-

:!!
a
c

==
o==

1ft

·1

t AvAV

YIH

vv vv vv y v yy y

Y V

VI'

__ _

JIo

<
CD

YIH

(G)

0'
...

VIL

-...
3

__ _

bO< IS,S>

WE#

00<7,0>

OE#
WE#

ROY!SSY#

OE#

RST
A<2S,0>

REG#

RY !SY#< 19,0>
,RP#<9,0>

CARD
CONTROL
LOGIC

CE I #
CEZ #
WAIT

:::Sr
BVOZ

A< 19,0>
WP

CE#<19,0>
WP

v~j

~
-

2SFOOSSA
~ AI9 -AO

oeq-ooo ~

CE#
WRITE-PROTECT
SWITCH

f-f-

2SFOOSSA

~ A19 -Ao

RY!BY#
WE# DEVICE 0

'"""

OE#

CD 1#

GND

Vee

RP#
Vpp ,

ceq-oOo

CE#

RY!BY#
WE# DEVICE 1
OE#
RP#
'GNO

Vee

Vppz

CARD
DETECT

~ AI9 -Ao

oeq-ooo -

CE#

RY!SY#
WE#
DEVICE 2

l --

1
A'9 -AO
CE#

Vee

CE#

007 -000
RY!BY#

WE# DEVICE 3

!
..

RP#
Vpp ,

J oeq~DOO

RY!BY#
WE# DEVICE' S
OE#
GND

AI9 -Ao

OE#

OE#
GNO

I-

Vee

RP#
Vpp,

RP#
GNO

··
·

J I
-

I
A'9

-Ao

CE#

Vee

VpP 2

.!.

I oeq~oOo ~J
RY!SY#

r--

WE# DEVICE '9
' - - - OE#
RP#
GNO

Vee

VpP2

GND
Vee
VpPI
Vppz

290434-3

Figure 1. Detailed Block Diagram. The Card Control Logic Provides
Decoding Buffering and Control Signals.
6-40

SERIES 2 FLASH MEMORY CARDS

APPLICATIONS
Intel's second generation Series 2 Flash Memory
Cards facilitate high performance disk emulation for
the storage of data files and application programs on
a purely solid-state removable medium. File management software, such as Microsoft's Flash File
System, in conjunction with the Series 2 Flash Memory Cards enable the design of high-performance
light-weight notebook, palmtop, and pen-based PCs
that have the processing power of today's desktop
computers.
Application software stored on the flash memory
card substantially reduces the slow disk-to-DRAM
download process. Replacing the mechanical disk
results in a dramatic enhancement of read performance and substantial reduction of power consumption, size and weight-considerations particularly
important in portable PCs and equipment. The Series 2 Card's high performance read access time allows the use of Series 2 Cards in an "execute-inplace" (XIP) architecture. XIP eliminates redundancy
associated with DRAM/Disk memory system architectures. Operating systems stored in Flash Memory
decreases system boot or program load times, enabling the design of PCs that boot, operate, store
data files and execute application programs from/to
nonvolatile memory with put losing the ability to perform an update.
File management systems modify and store data
files by allocating flash memory space intelligently.
Wear leveling algorithms, employed to equally distribute the number of rewrite cycles, ensure that no
particular block is cycled excessively relative to other blocks. This provides hundreds of thousands of
hours of power on usage.
This file management software enables the user to
interact with the flash memory card in precisely the
same way as a magnetic disk.
For example, the Microsoft Flash File System enables the storage and modification of data files by
utilizing a linked-list directory structure that is evenly
distributed along with the data throughout the memory array. The linked-list approach minimizes file
fragmentation losses by using variable-sized data
structures rather than the standard sector/cluster
method of disk-based systems.
Series 2 Flash Memory Cards provide durable nonvolatile memory storage for mobile PCs on the road,
facilitating simple transfer back into the desktop environment.

For systems currently using a static RAM/battery
configuration for data acquisition, the Series 2 Flash
Memory Card's nonvolatility eliminates the need for
battery backup. The concern for battery failure no
longer exists, an important consideration for portable computers and medical instruments, both requiring continuous operation. Series 2 Cards consume
no power when the system is off, and only 5 p.A in
Deep-Sleep mode (20 Megabyte card). Furthermore,
Flash Memory Cards offer a considerable cost and
density advantage over memory cards based on
static RAM with battery backup.
Besides disk emulation, the Series 2 Card's electrical block-erasure, data writability, and inherent nonvolatility fit well with data accumulation and recording needs. Electrical block-erasure provides design
flexibility to selectively rewrite blocks of data, while
saving other blocks for infrequently updated parameters and lookup tables. For example, networks and
systems that utilize large banks of battery-backed
DRAM to store configuration and status benefit from
the Series 2 Flash Card's nonvolatility and reliability.

SERIES 2 ARCHITECTURE
OVERVIEW
The Series 2 Flash Memory Card contains a 2 to 20
Megabyte Flash Memory array consisting of 2 to 20
28F008SA FlashFile Memory devices. Each
28F008SA contains sixteen individually-erasable, 64
Kbyte blocks; therefore, the Flash Memory Card
contains from 32 to 320 device blocks. It also contains two Card Control Logic devices that manage
the external interface, address decoding, and component management logic. (Refer to Figure 1 for a
block diagram.)
To support PCMCIA-compatible word-wide access,
devices are paired so that each accessible memory
block is 64 KWords (see Figure 2). Card logic allows
the system to write or read one word at a time, or
one byte at a time by referencing the high or low
byte. Erasure can be performed on the entire block
pair (high and low device blocks simultaneously), or
on the hiQh or low byte portion separately.
Also in accordance with PCMCIA specifications this
product supports byte-wide operation, in which the
flash array is divided into 128K x 8 bit device blocks.
In this configuration, odd bytes are multiplexed onto
the low byte data bus.

6-41

.SERIES 2.FLASH MEMORY CARDS

015
~ow Byte

High Byte

x 16 mode

..............

. [.en Byte,

;.;..;..-~

x 8 .mode

.r----------..
,'1

Odd Byt.
I
._-------:"",.."

...... ......

"",,,,,,,,,,,,

."1.ii:a_...... _ _
""

"
""

,
.,
,

.16 mode
~IOCK :,....r--"" •

8 mod.

,
BLOCK PAIR
290434-1

Flgunt2. Memory Architecture. Each Device Pair Consists of Sixteen 64 KWord Blocks.
.. Write/erase automation simplifies the system software Interface to the card. A two-step command sequence initiates write or erase operations and provides additional data security. Internal device circuits
automatically execute the algorithms. and timinQs
necessary for data-write or block-erase operations,
including verifications for long-term data integrity.'
While perfotming either data-write Or block-erase,
the memory card interface reflects this by bringing
its RDY/BSY# (Ready/Busy) pin low. This output
goes high when the operation completes. This feaErase blocking facilitates solid-state storage applicature reduces CPU overhead and allows software
tions by allowing .selective memory reclamation. Multiple 64 Kbyte blocks may be sirnultaneously erased
polling or. hardware interrupt mechanisms. :Writing
within the memory card as long as not more than
memory data is achieved in .single byte or word inone block per device is erasing. This shortens the
crements, typically in 10 p.s.
I" ,
total time required for erasure, but requires additional supply current. A block typically requires 1.6 secRead access time is 200 ns or less over the O·C to
onds .to erase. Each memory block can be erased
SO·C temperature range.
arid completely written 1'00,000 times.
The Reset-PowerDowil mode reduces power conErase suspend allows the system to temporarily insumption to less than 5 p.A. to help extend battery
terrupt a block erase operation. This mode permits
life of portable host systEims. Activated through softreads from alternate· device blocks while that same
ware control, this mode optionally affects the entire
device contains an erasing block. Upon cOmpletion
flash array (Global Reset-PowerDown Register) or
of the read operation, erasure of the ··suspended
specific device »airs (Sleep Control Register).
block must be resumed.

Series' 2 Flash Memory Cards offer additional features over the Bulk Erase Flast) .card prOduct family
(refer
to
iMC001 FLKA,. iMC002FLKA
and
iMCP04FLKA data sheets). Some of the more notable enhancements include: high density 'capability,
erase blocking, internal write/erase automation,
erase suspension to read, Component Management
Registers. that provide software control Of devicelevel functions and a deep-sleep mode.

6-42

SERIES 2 FLASH MEMORY CARDS

PCMCIA/JEIDA INTERFACE

BATTERY VOLTAGE DETECT

The Series 2 Flash Memory Card interface supports
the PCMCIA 2.01 and JEIDA 4.1 68-pin card format
(see Tables 1 and 2). Detailed speCifications are described in the PC Card Standard, Release 2.0, September 1991, published by PCMCIA. The Series 2
Card conforms to the requirements of both Release
1 and Release 2 of the PC Card Standard.

PCMCIA requires two signals, BVD1 and BVD2, be
supplied at the interface to reflect card battery condition. Flash Memory Cards do not require batteries.
When the power on reset cycle is complete, BVD1
and BVD2 are driven high to maintain compatibility.

CARD DETECT

Series 2 Card pin definitions are equivalent to the
Bulk-Erase Flash Card except that ce.rtain No Connectsare now used. A22 through A24, RST (Reset),
and RDY1BSY# (Ready/Busy) have pin assignments as set by the PCMCIA standard.

Two signals, CD1 # and C02 #, allow the host to determine proper socket seating. They reside at opposite ends of the connector and are tied to ground
within the memory card.

NOTE: The READY/BUSY signal is abbreviated as
RDY/BSY# by PCMCIA {card levelj and as
RY/BY# by JEDEC {component levelj.

DESIGN CONSIDERATIONS

The outer shell of the SerieS 2 card meets all
PCMCIAlJEIDA Type 1 mechanical specifications.
See Figure 19 for mechanical dimensions.

WRITE PROTECT SWITCH
A mechanical write protect switch provides the
card's memory array with internal write lockout. The
Write-Protect (WP) output pin reflects the status of
this mechanical switch. It outputs a high signal (YOH)
when writes are disabled. This switch does not lock
out writes to the Component Management Registers.

The Series 2 Card consists of two separate memory
planes: the Common Memory Plane (or Main Memoryland the Attribute Memory Plane. The Common
Memory Plane resides in the banks of device pairs
and represents the user-alterable memory space.
The Component Management Registers (CMR) and
the hardwired Card Information Structure (CIS) reside in the Attribute Memory Plane within the Card
Control Logic, as shown in Figure 3. The Card Control'Logic interfaces the PCMCIA connector and the
internal flash memory array and performs address
decoding and data control.

COMPONENT MANAGEMENT REGISTERS
ATrRIBUTE MEMORY PLANE
FUNCTION

CIS ADDRESS

NOT USED
(OOO4200H)

4142H - 41 FEH

RESERVED

4140H

READY-BUSY MODE (INTEL)

4136H - 413EH

RESERVED

4130H - 4134H

READY-BUSY STATUS (INTEL)

COMPONENT MANAGEMENT

4126H - 412EH

RESERVED

REGISTERS

4120H - 4124H

READY-BUSY MASK (INTEL)

(OOO4000H)

411CH - 411EH

RESERVED

NOT USED
(OOOOODBH)
HARDWIRED PCMCIA CIS
(OOOOOOOH)

Attribute Memory Plane
accessible with
REG (pin 61) = VIL

,,
,,
,,
,

,,
,

411BH - 411AH

SLEEP CONTROL (INTEL)

4106H - 4116H

RESERVED

4104H

WRITE PROTECTION (INTEL)

4102H

RESERVED

4100H

CARD STATUS (INTEL)

4004H - 40FEH

RESERVED

4002H

GLOBAL RESET-PWRDWN (PCMCIA)

4000H

SOFT RESET (PCMCIA)

290434-2
INTEL
PCMCIA

=
=

Performance Enhancement Register
Defined InPCMCIA Release 2.0

Figure 3_ Component Management Registers Allow S/W Control of Components within Card
6-43

intel®

SERIES 2 FtASH MEMORY CARDS

ADDRESS DECODE
Address decoding provides the decoding logic for
the 2 to 20 Device Chip Enables and the elements of
the Attribute Memory Plane. REG# selects between
the Common Memory Plane (REG # =. VI H) and the
Attribute Memory Plane (REG# = Vlt>.

NOTE:
The Series 2 Card has active address inputs Ao to ,
A24 implying that reading and writing to addresses
beyond 32 Megabytes causes wraparound. Furthermore, reads to illegal addresses (for example, between 20 and 32 Meg on a 20 Megabyte card) returns OFFFFh data.
The 2SFOOSSA devices, storing data, applications or
firmware, form the Common Memory Plane accessed individually or as device pairs. Memory is linearly mapped in the Common Memory Plane. Three
memory access modes are available when accessing the Common Memory Plane: Byte-Wide, Word
Wide, and Odd-Byte modes.
Additional decoding selects the hardwired PCMCIA
CIS and Component Management Registers
mapped in the Attribute, Memory Plane beginning at
address OOOOOOH.

6-44

The 512 memory7mapped even-byte CMRs arelin~
early mapped beginning at address 4000H in the Attribute Memory Plane.

DATA CONTROL
Data Control Logic selects the path and direction for
accessing the Common or Attribute Memory Plane.
It controls any of the PCMCIA-defined Word-Wide,
Byte-Wide or Odd-Byte modes for either'reads or
writes to these areas. As shown in Table 3, input
pins which determine these selections are REG#,
AO through A24, WE#, OE#, CE1#, and CE2#.
PCMCIA specifications allow only even-byte access
to the Attribute Memory Plane.
In Byte-Wide mode, bytes contiguous in software actuallyalternate between two device blocks of a device pair. Therefore, erasure of one device block
erases every other contiguous· byte. In accordance
with tl')e PCMCIA standard for memory configuration,
the Series 2 Card does. not support confining contiguous bytes within one flash device when in by-S
mode.

intel®

SERIES 2 FLASH MEMORY CARDS
Table 3. Data Access Mode Truth Table

Function Mode

REG# CE#2 CE#1 Ao OE# WE#

VPP2

VPP1

D15-D8

D7-DO
,

COMMON MEMORY PLANE
STANDBy(1)

BYTE READ

WORD READ

ODD-BYTE READ

BYTE
, WRITE

H·

WORD WRITE

ODD-BYTE WRITE

VPPL(2) VPPL(2)

HIGH-Z

VPPL(2) VPPL(2)

HIGH-Z

EVEN-BYTE

VPPL(2) VPPL(2)

HIGH-Z

ODD-BYTE

VPPL(2) VPPL(2)

ODD-BYTE

EVEN-BYTE

VpPl.(2) Vppd2)

ODD-BYTE

HIGH-Z

VPPH

EVEN-BYTE

VPPH

ODD-BYTE

VPPH

ODD-BYTE

EVEN-BYTE

ODD-BYTE

X(2)

1'-llGH-Z

EVEN-BYTE

X(2)

VPPH
VPPH VPPL(2)

ATTRIBUTE MEMORY PLANE
BYTE READ

X(2)

HIGH-Z

INVALID

WORD READ

X(2)

INVALID
DATA(3)

EVEN-BYTE

ODD-BYTE READ

X(2)

INVALID
DATA(3)

HIGH-Z

BYTEWRITE·

X(2)

EVEN-BYTE

X(2)

INVALID
OPERATION(3)

WORD WRITE

X(2)

INVALID
OPERATION(3)

EVEN-BYTE

ODD-BYTE WRITE

X(2)

INVALID
OPERATION(3)

NOTES:
1. Standby mode is valid in Common Memory or Attribute Memory access.
2. To meet the low power specifications, Vpp = VPPL; however VPPH presents no reliability problems.
3. Odd-Byte data are not valid during access to the Attribute Memory Plane.
4. H = VIH, L = VIL, X -:i Don't Care.

6-45

I
.\

PRINCIPLES OF OPERATI9N

HARDWIRED.. CIS

l,nte!'s'Seri~s 2 Fh:1sh Memory Card provides 'electrinon,volatile, random-access storage. ,
,Individual 28F.008SA devices utilize a Command
User Interface' ,(CUI) ,and Write State Machine
(WSM) to simplify bioqk"eras\.lre and data write oper~
ations.

The card's structure description resides in the even~
byte locations starting atOOOOHand going to the
CIS en~ing tuple (FNULL)within the Attribute M~mo
ry Plane.' Data included in the hardwired CIS consists of tuples. Tuples are a variable-Ie",gthlist of
data blocks describing 'details such as manufacturer's hame, the size of each memory device and the
number of flash devices within the card.

cally~alterable,

,COMMON MEMORY ARRAY
Figure 4 ,shows the Common Memory Plane's organization.The first block pair (64 KWords) of Common Memory, referred to, as the Common Memory ,
Card Information Structure Block, optionally extends
the hardwired CIS in the Attribute Memory Plane for
additional card information. This may be written during initial card formatting fot OEM customization~
Since this CIS Block is part of Common Memory, it!\
data can be altered. Write access to the Common
Memory CIS Block is controlled by the Write Protect
Control Register which may be activated by system
software after power-up. Additionally, \he entire
Common Memory plane (minus the Common Memory CIS Block) may be'software write protected. Note
that the Cominon Memory CIS Block is not part of
the Attribute Memory Plane. Do not bsert REG# to
access the Common Memory CIS Block.

Device Pair 9 '

COMPONENT MANAGEMENT
REGISTERS (CMRs) ,
The CMRs in the Attribute Memory Plane provide
special, software-controlled functionality. Card Con~
trol Logic includes circuitry to access the CMRs.
REG (PCMCIA, pin 61) selects the Attribute Memory
Plane (and therefore 'the CMRs) when eq\.lal to VIL.
CMRs are' classified into two categories: those defined by PCMCIA R2.0 and those included by Intel
(referred to as Performance' Enhancement Registers) to enhance the interface between the host System and the card's .flash memory array. CMRs (See'
,Figure 3) provide seven control functions-ReadyBusy Interrupt Mode, Device Ready-Busy Status,
Device Ready-Busy Mask, Reset-PowerDown Con~
trol, Software-controlled Write' Protection, Card
Status and Soft Reset.

SOFT RESET REGISTER (PCMCIA)
(CONFIGURATION OPTION)
The SOFT RESET REGISTER (Attribute Memory
Plane Address 4000H, Figure 5) is defined in the
PQMCIA Release 2.0 specification as tlie Configuration ,Option Register.,
Bit 1 is the soft reset bit (SRESE'l). Writing a 1 to,
this bit initiates card reset to the power-on default
state (see Side Bar page 11). This bit must be
cleared to use the CMRs or to access the devices.

Figure 4. Common Memory Plane. Use
the Optional Common Memory Plane
CIS for Custom Card Format'lnformation.

SRESET implements in software what the reset pin
il1,'lplements in hardware. On power-up, the card automiltically assumes default conditions. Similar to
the reset pin (pin 58), this bit clears at the end of a
power-on reset cycle or a system reset cycle.
Bits 0 through 6 are not used by this memory card,
but power up as zeroes for PQMCIA compatibility;

SER,ES 2 FLASH MEMORY CARDS

SOFT RESET REGISTER
(CONFIGURATION OPTION REGISTER)
(Read/Write Register)
ADDRESS

BIT 7

4000H

SRESET

1 = RESET, CLEAR TO ACCESS CARD

Figure 5. SOFT RESET REGISTER (PCMCIA). Sets the Memory Card In the Power-On Default State.

Global Power Down Register (PCMCIA)
(Configuration and Status)
The Global Reset-PowerDown Register (Attribute
Memory Plane Address 4002H, Figure 6) is referred
to as the Configuration and Status Register in the
PCMCIA Release 2.0 specification.
Bit 2 (RP) controls global card power-down. Writing
a 1 to this bit places each device within the card into
"Deep-Sleep" mode. Devices in Deep·Sleep are not
accessible. Recovery from power·down requires
500 ns for reads and 1 /Ls for writes,
The RP bit defaults to 0 on card power·up or reset.
Setting or clearing this bit has no affect on the bit
settings of the Sleep Control Register.
The remaining Global Reset·PwrDwn Register bits
are defined for Intel's family of I/O cards and are
driven low for compatibility.

GLOBAL RESET-POWER-DOWN REGISTER
(CONFIGURATION AND STATUS REGISTER)
(Read/Write Register)
1 = POWER OOWN

Figure 6. GLOBAL RESET-PWRDWN REGISTER (PCMCIA). The RP
Bit Enables Reset PowerDown of All Flash Memory Devices.

6-47

SERIES 2 FLASH MEMORY CARDS

CARD STATUS REGISTER
(Read Only Register)
ADDRESS

BIT?

BIT6

BIT5

BIT4

BIT3

BIT2

BIT 1

BIT 0

4100H

ADM

ADS

SRESET

CMWP

CISWP

RDY/BSY#

Figure 7. CARD STATUS REGISTER (Intel) Provides a Quick Review of the Card's Status

CARD STATUS REGISTER (INTEL)
The Read-Only, CARD STATUS REGISTER (Attribute Memory Plane Address 4100H, Figure 7) returns generalized status of the Series 2 Card and its
CMRs.
Bit 0 (RDY/BSY#) reflects the card's RDY/BSY#
(Ready-Busy) output. Software polling of this bit provides data-write or block-erase operation status. A
zero indicates a busy device(s) in the card.
Bit 1 (WP) reports the position of the card's Write
Protection switch with 1 indicating write protected. It
reports the status of the WP pin.
Bit 2 (CISWP) reflects whether the Common Memory CIS is write protected using the WRITE PROTECT
REGISTER, with 1 indicating write protected.
Bit 3 (RP) reports whether the entire flash memory
array is in "Deep-Sleep" (Reset-PwrDwn) mode,
with 1 indicating "Deep-Sleep". This bit reflects the
RP bit of the GLOBAL RESET-POWERDOWN REGISTER: Powering down al/ device pairs individually
(using the Sleep Control Register), also sets this bit.
Bit 4 (CMWP) reports whether the Common Memory
Plane (minus Common Memory CIS) is write protected via the WRITE PROTECT REGISTER with 1 indicating write protected.
Bit 5 (SRESET) reflects the SRESET bit of the SOFT
RESET REGISTER. It reports that the card isin Soft

6-48

Reset with 1 indicating reset. When this bit is zero,
the flash memory array and CMRs may be accessed, otherwise clear it via the SRESET REGISTER.
Bit 6 (ADS, ANY DEVICE SLEEP) is the "ORed"
value of the SLEEP CONTROL REGISTER. Powering down any device pair sets this bit.
Bit 7 (ADM, ANY DEVICE MASKED) is the "ORed"
value of the READY IBUSY MASK REGISTER.
Masking any device sets this bit.

WRITE PROTECTION REGISTER
(INTEL)
The WRITE PROTECTION REGISTER (Attribute
Memory Plane Address 4104H, Figure 8) selects
whether the optional Common Memory CIS and the
remaining Common Memory blocks are write protected (see Figure 4).
Enable Common Memory CIS write protection by
writing a 1 to the CISWP Bit (bit 0).
Enable write protection of the remaining Common
Memory blocks by writing a 1 to the CMWP Bit (bit
1).
In the power-on default state, both bits are 0, and
therefore not write protected.
Reserved bits (2-7) have undefined values and
should be written as zeroes for future compatibility,

SERIES 2 FLASH MEMORY CARDS

I
ie

WRITE PROTECTION REGISTER
(Read/Write Register)

WRITE PROTECT

Figure 8. WRITE PROTECTION REGISTER (Intel) Eliminates Accidental Data Corruption

SLEEP CONTROL REGISTER (INTEL)
Unlike the GLOBAL RESET·POWERDOWN REGIS·
TER, which simultaneously resets and places all
flash memory devices into a Deep·Sleep mode, the
SLEEP CONTROL REGISTER (Attribute Memory
Plane Address 4118H-411AH, Figure 9) allows selective power·down control of individual device pairs.
Writing a 1 to a specific bit of the SLEEP CONTROL
REGISTER places the corresponding device pair
into the "Deep·Sleep" mode. Devices in Deep-Sleep
are not accessible. On cards with fewer than
20 Megabytes (10 device pairs), writing a one to an
absent device pair has no affect and reads back as
zero.
This register contains all zeroes (i.e., not in Deep·
Sleep mode) when the card powers up or after a
hard or soft reset. Furthermore, the Global Reset·
PowerDown Register has no affect on the contents
of this register. Therefore, any bit settings of the

Sleep Control Register will remain unchanged after
returning from a global reset and power down (writ·
ing a zero to the RP bit of the Global Reset·PowerDown Register).

READY-BUSY STATUS
REGISTER (INTEL)
The bits in the Read-only, READY-BUSY Status
Register (Attribute Memory Plane Address 4130H4134H, Figure 10) reflect the status (READY = 1,
BUSY = 0) of each device's RY /BY # output. A busy
condition indicates that a device is currently processing a data-write or block-erase operation.
These bits are logically "AND-ed" to form the
Ready/Busy output (ROY /BSY #, pin 16) of the
PCMCIA interface. On memory cards with fewer
than 20 devices, unused Device RY /BY # Status
Register bits appear as ready.

SLEEP CONTROL REGISTER
(Read/Write Register)

1 = SELECTED DEVICE PAIR IN POWER-DOWN MODE AND RESET

Figure 9. SLEEP CONTROL REGISTER (Intel) Allows Specific
Devices to be Reset and Put into Power-Down Mode

6-49

I
I

'I
!'

SERIES 2 FLASH MEMORY CARDS

READY-SUSYSTATUS REGISTER
(Read/Write. Register)

4132H

4130H

DEVICE

1 = DEVICE READY, 0

DEVICE

8
DEVICE

DEVICE

DEVICE BUSY

Figure 10. READY-BUSY STATUS REGISTER (Intel) Provides
Operation Status of All Flash Memory Devices

In an unmasked condition (MASK REGISTER bits =
O),any device RY /BY # output going low pulls the
card's ROY /BSY # output to VIL (BUSY). In this
case, all devices must be READY to allow the card's
ROY /BSY # output to be ready (VIH). This is referred
to as the PCMCIA READY-BUSY MODE. An alternate typ~ of READY-BUSY function is described in
thf/ next section, READY-BUSY MODE REGISTER.

READY-BUSY MASK REGISTER
(INTEL)
The bits of the Read/Write READY-BUSY MASK
REGISTER (Attribute Memory Plane Address
4120H-4124H, Figure 11) mask out the corresponding "AND-ed" READY-BUSY STATUS REGISTER
bits from the PCMCIA data bus (ROY /BSY #, pin 16)
and the CARD STATUS REGISTER RDY/BSY# Bit
(bit 0).

READY-BUSY MASK
(Read/Write Register)

19
4122H

4120H

DEVICE

1 = MASK ENABLED
Figure 11. READY-BUSY MASK REGISTER (Intel) Essential for Write Optimization

6.-50

SERIES 2 FLASH MEMORY CARDS
If the READY-BUSY MASK REGISTER bits are set
to ones (masked condition), the RDY /BSY # output
and the CARD STATUS REGISTER RDY/BSY# bit
will reflect a READY condition regardless of the
state of the corresponding devices. The READYBUSY MASK REGISTER does not affect the
READY-BUSY STATUS REGISTER allowing software polling to determine operation status.
Unmasked is the default condition for the bits in this
register. On memory cards with fewer than 20 devices, unused device mask bits appear as masked.

READY-BUSY MODE REGISTER
(INTEL)
The READY-BUSY MODE REGISTER (Attribute
Memory Plane Address 4140H, Figure 12) provides
the selection of two types of system interfacing for
the busy-to-ready transition of the card's
RDY /BSY # pin:
1. The standard PCMCIA READY-BUSY MODE, in
which the card's RDY /BSY # signal generates a
low-t,o-high transition (from busy to ready) only
after all busy devices (not including masked
devices) have completed their data-write or blockerase operations. This may result in a long interrupt latency.
2. A High-Performance mode that generates a lowto-high (from busy-to-ready) transition after each
device becomes' ready. This provides the host

system with immediate notification that a specific
device's operation has completed and that device may now be used. This is particularly useful
in a file management application where a block
pair, containing only deleted files, is being erased
to free up space so new file data may be written.'
Enabling the HIGH-PERFORMANCE READY-BUSY
MODE requires a three step sequence:
1. Set all bits in the READY/BUSY MASK REGISTER. This prevents ready devices from triggering
an unwanted interrupt when step 3 is performed.
2. Write 01 H to the READY-BUSY MODE REGISTER. This sets the MODE bit.
3. Write 01H to the READY-BUSY MODE REGISTER. This clears the RACK bit.
The MODE and RACK bits must be written in the
prescribed sequence, not simultaneously. The
card's circuitry is designed purposely in this manner
to prevent an initial, unwanted busy-to-ready transition. Note that in Step 2, writing to the RACK bit is
a Don't Care.
When the High-Performance Mode is enabled, specific READY-BUSY MASK bits must be cleared after
an operation is initiated on the respective devices.
After each device becomes ready, the RDY IBSY #
pin makes a low-to-high transition. To catch the next
device's. completion of an operation, the RACK bit
must be cleared.

READY-BUSY MODE REGISTER
(Read/Write Register)

MODE = READY-BUSY MODE
PCMCIA MODE
1 = HIGH PERFORMANCE

RACK = READY ACKNOWLEDGE CLEAR TO
SET UP RDY IBSY'" PIN, THEN CLEAR AFTER
EACH DEVICE BECOMES READY TO ACKNOWLEDGE TRANSITION.

Figure 12. High Performance Ready-Busy Mode REGISTER (Intel)
Used to Trigger a Ready Interrupt for Each Device

6-51

SERIES 2 FLASHMEMORV CARDS

PRINCIPLES OF DEVICE OPERATION
Individual 28F008SA devices include a Command
User Interface (CUI) and a Write State Machine
(WSM) to manage write and erase functions in each
device block.
The CUI serves as the device's interface to the Card
Control Logic by directing commands to the appropriate device circuitry (Table 4). It allows for fixed
power supplies during block erasure and data writes.
The CUI handles the WE# interface into .the device
data and address latches, as well as system software requests for status while the WSM is operating.

The CUI·· itself does not occupy an addressable
memory locatioh. The CUI provides a latch used to
store the command and address and data information needed to execute the command. Erase Setup
and Erase Confirm commands require bothappropri"
ate command data and an address within the block
to be erased. The Data Write Setup command requires both appropriate command data and the address of the locati.on to be written, while the Data
Write command consists of the data to be written
and the address of the location to be written.

The CUI initiates flash memory writing and erasing
operations only when Vpp is at 12V; Depending .on
the applic?ltion, the system designer may choose to
make the Vpp power supply switchable (available
when writes and erases are required) or hardwired to
VPPH. When Vpp = VPPL, power savings are incurred and memory contents cannot be altered. The
CUI architecture provides protection from unwanted
write and erase operations even when high voltage
is applied to Vpp. Additionally, all functions are disabled whenever Vcc is below the write lockout voltage VLKO, or when the card's Deep-Sleep modes
are enabled. The WSM automates the writing and
erasure of blocks within a device. This on-chip state
machine controls block erase and data-write, freeing
the host processor for other tasks. After receiving
the Erase Setup and Erase Confirm commands from
the CUI, the WSM controls block-erase, Progress is
monitored via the device's status register, the card's
control logic, and the ROY IBSY# pin of the
PCMCIA interface. Data-write is similarly controlled,
after destination address and expected data are
supplied.

Table 4. Device Command Set
First BusCcyle
Second Bus Cycle
Bus
Cycles
Data
Data
Addr(2)
Operation Addr(2)
Req'd Operation
xS Mode x16 Mode
xSMod.e x16Mode

28F008SA Command(1)

Read Array/Reset

Write

FFH

FFFFH

Intelligent Identifer

Write

90H

9090H

Read

110(3)

IID(3t

Read Device Status Register

Write

70H

7070H

Read

SRD(4)

Clear Device Status Register

Write

50H

5050H

Erase Setup/Erase Confirm

Write

20H

2020H

Write

DOH

DODOH

Erase Suspend/
Erase Resume

Write

BOH

BOBOH

Write

DOH

DODOH

Write Setup/Write

Write

40H

4040H

Write

WD(5)

WD(5).

WD(5)

Alternate Write Setup/Write(6)

Write

10H

1010H

Write

NOTES:
1. Commands other than those shown above are reserved by Intel for future device implementations and should not be
used.
2. DA = A device-level (or device pair) address within the card.
BA = Address within the block of a specific device (device pair) being erased.
WA = Address of memory location to be written.
IA = A device-level address; OOH for .manufacturer code, 01 for device code.
3. Following the intelligent identifier command, two read operations access manufacturer (B9H) and device codes (A2H).
4. SRD = Data read from Device Status Register.
.
.,
~
5. WD = Data to be written at location WA. Data is latched on the riSing edge of WE#.
6. Either 40H or 10H are recognized by the WSM as the Write Setup command.
I

6-52

Intale
COMMAND DEFINITIONS
Read Array (FFH) Upon initial card power-up. after exit from the DeepSleep modes, and whenever illegal commands are
given, individual devices default to the Read Array
mode. This mode is also entered by writing FFH into
the CUI. In this mode, microprocessor read cycles
retrieve array data. Devices remain enabled for
reads until the CUI receives an alternate command.
, Once the internal WSM has started a block-erase or
data-write 9peration within a device, that device will
not recognize the Read Array command until the
WSM has completed its operation (or the Erase Suspend command.is issued during erase).

Intelligent Identifier (90H) After executing this command, the intelligent identifier values can be read. Only address Ao of each device is used in this mode, all other address, inputs
lire ignored [(Manufacturer code = 89H for Ao =
0), (Device code = A2H for Ao = 1»). The device
will remain in this mode until the CUI receives anoth- .
er command.
This information is useful by system software in determining what type of flash memory device is contained within the card and allows the correct matching of device to write and erase algorithms. System
software that fully utilizes the PCMCIA specification
will not use the intelligent identifier mode, as this
data is available within the Card Information Structure (refer to section on PCMCIA Card Information
Structure).

Read Status Register (70H)
After writing this command, a device read outputs
the contents of its Status Register, regardless ,of the
address presented to that device. The contents of
this register are latched oil the falling edge of, OE # ,
CEl # (and/or CE2#), whichever occurs last in the
read cycle. This prevents possible bus errors which
might occur if the contents of the Status Register
changed while reading its contents. CEl # (and
CE2 # for odd-byte or word access) or OE # must be
toggled with each subsequent status read, or the
completion of a write or erase operation will not be
evident. This command is executable while the
WSM is operating, however, during a block-erase or
data-write operation, reads from the device will auto-

SERIES 2 FLASH MEMORY CARDS

matically return status register data. Upon completion of that operation, the device remains in the
Status Register read mode until the CUI receives
another command.
The read Status Register command functions when
Vpp = VPPL or VPPH.

Clear Status Register (SOH)
The Erase Status and Write Status bits may be set
to "1"s by the WSM and can only be reset by the
Clear Status Register Command. These bits indicate
various failure conditions. By allowing system' software to control the resetting of these bits, several
operations may be performed (such as cumulatively
writing several bytes or erasing multiple blocks in
sequence). The device's Status Register may then
be polled, to determine if an 'error occurred during
that sequence. This adds flexibility to the way the
device may be used.
Additionally, the Vpp Status bit (SR.3) MUST be reset by system software (Clear Status Register command) before further block-erases are attempted
(after an error).
'
The Clear Status Register command functions when
Vpp = VPPL or VPPH. This command puts the device
, in the Read Array mode.

Write Setup/Write
A two-command sequence executes a data-write
operation. After the system switches Vpp to VPPH,
the write setup command (40H) is written to the CUI
of the appropriate device, followed by a second
write specifying the address and write data (latched
on the rising edge of WE#). The device's WSM controls the data-write and write verify algorithms internally. After receiving the two-command write sequence, the device automatically outputs Status
Register data when read (see Figure 13). The CPU
detects the completion of the write operation by analyzing card-level or device-level indicators. Cardlevel indicators include the ROY /BSY # pin and the
READY-BUSY STATUS REGISTER; while devicelevel indicators include the specific device's Status
Register. Only the Read Status Register command
is valid while the write operation is active. Upon
completion of the data-write sequence (see section
on Status Register) the device's Status Register reflects the result of the write operation. The device
remains in the Read Status Register mode until the
CUI receives an alternate command.

6-53

SERIES
2 F1.ASHMEMORY CARDS
..
'

(

Er.~ Setup/Erase Confirm
Co."ma,nds (20H)' ,
"
Within a device,a two-command sequence initiates
an erase operation on one device block at a time.
After the system SWitches Vpp to VpPH, an Erase
Setup command (20H) prepares the CUI for the
Erase Confirm command (DOH). The device's WSM
controls the erase algorithms internally. After receiving the two-command erase sequence, the device
automatically. outputs Status Register data when
read (see Figure 14). If, the command after erase
setup. is not an Erase Confirm command, the CR
setS the Write Failure !lnd Erase Failure bits of the
StatUs Register, places the device into the Read
Status Register mode, and waits for anbther command. The Erase Confirm command enables the
WSMfor erase (simultaneously closing the address
latches for that device's block (A16-A19)' The CPU
detects the completion of the erase operation by analyzing card-level or device-level" indicators. Cardlevel indicators include the RDY/BSY pin and the
READY-BUSY STATUS RE~ISTER; While devicelevel 'indicators include the sPecific device's Status
Register. Only the Read 'Status Register and Erase
Sus~nd command is valid during an active erase
operation. Upon completion of the erase sequence
(see section on Status Register) the device's Status
, Regi~ter reflects the result of the erase operation.
The',devlce' remains in the Read Status Register
mOde until the CUI receives an alternate command.
The ,two-s~ep block-erase sequence ensures that
memory contents ai'e not aCCidentally erased. Erase
'attempts while VPPL < Vpp< VPPH produce spurious results and are not recommended. Reliable
bloekerasure only occurs when Vpp = VPPH. In the
absence of this Voltage, memory contents are protec:t$d against erasure. If block e,rase is attempted
while Vpp = VPPL, the Vpp Status bit will be set to
u1".'
When erase completes, the Erase Status bit should
be checked. If an erase error is detected, the devic&'s l?tatus Register should be cleared. The CUI
remltlne in Read Status Register mode until repeivIng an alternate command.

6-54,

Erase Suspend (BOH)/Erase, Resume ' .
(DOH)
Erase Suspend allows block', eraSeintel'ruption .to
read data from another block of the device or to
temporarily conserve power for another system op~ .
eration. Once the erase process starts, writing the
Erase Suspend command to the CUI (see Figure 15)
requests the WSM to suspend the erase sequence
,at a predetermined point i~ the erase algorithm. In
the erase suspend state, the device continues to
output Status Register data· when read.
Polling the device's RY IBY # and Erase Suspend
Status bits (Status Register) will determine when the
erase suspend mode is valid. It is important to note
that the card's ROY IBSY #, pin will also transition to
VOH and will generate an interrupt if this pin is connected ,to a system-level interrupt. At this point, a
Eiead Array command can be written to the device's
CUI to read data from blocks other than those
which are suspended. The only other valid commands at this time are Read Status Register (70H)
and Erase Resume (DOH). If Vpp goes low during
Erase Suspend, the Vpp Status bit is' se,t in the
Status Register and the erase operation is aborted.
The Erase Resume command clears the Erase Suspend state and allows the WSM to continue with the
erase op-eration. The device's RY/BY# Status and
Erase Suspend Status bitS and the card's READYBUSY Status Register are automatically lipdated tei
reflect the erase ,resume condition. The card's ROY I
BSY# pin also returns to VOL.

Invalid/Reserved
These are unassigned commands having the same
effect. as the Read Array command. Do not issue
any command other than the valid commands specified above. Intel reserves the right to redefine these
.
codes for future functiOnS.

SERIES 2 FLASH MEMORY CARDS

DEVICE STATUS REGISTER

Bit 5-Erase Status

Each 28F008SA device in the Series 2 Card contains a Status Register which displays the condition
of its Write State Machine. The Status Register is
read at any time by writing the Read Status command to the CUI. After writing this command, all subsequent Read operations output data from the
Status Register, until another command is written to
the CUI.

This bit will be cleared to 0 to indicate a successful
block-erasure. When set to a "1", the WSM has
been unsuccessful at performing an erase verification. The device's CUI only resets this bit to a "0" in
response to a Clear Status Register command.

Bit 7-WSM Status
This bit reflects the Ready/Busy condition of the
WSM. A "1'~ indicates tl1at read, block-erase or
data- write operations are available. A "0" indicates
that write or erase operations are in progress.

Bit 4-WrlteStatus
This bit will be cleared to a 0 to indicate a successful
data-)Nrite operation. When the WSM fails to write
data after receiving a write command, the bit is set
to a "1" and can only be reset by the CUI in response to a Clear Status Register command.

Bit 3-Vpp Status
Bit 6-Erase Suspend Status
If an Erase Suspend command is issued during the
erase operation, the WSM halts execution and sets
the WSM Status bit and the Erase Suspend Status
bit to a "1". This bit remains set until the device
receives an Erase Resume command, at which point
the CUI resets the WSM Status bit and the Erase
Suspend Status bit.

During blOck-erase and data-write operations, the
WSM monitors the output of the device's internal
Vpp detector. In the event of low Vpp, the WSM sets
("1 ") the Vpp Status bit, the status bit for the operation in progress (either write or erase). The CUI resets these bits in response to a Clear Status Register command. Also, the WSM RY /BY bit will be set
to indicate a device ready condition. This bit MUST
be reset by system software (Clear Status Register
command) before further data writes or block erases
are attempted.

DEVICE STATUS REGISTER
b7

b<4

1
1

1
1
1

1
1

1
reserved

reserved

Vpp Status
1 Write Status
Erase Status

Erase Suspend status

WSW Status

290434-16

6-55

I
il

SERIES 2 FLASH.MEMORY CARDS

Bus
Operation

Command

x8Mode

x18M~

Write

Write Setup

Write

'Data Write

Data'= 40H
, Addre$s = Byte ,
Within Card to be
WrittEin
Data 10 be Written
Address = ByteWithin Card to be
Written

Data =' 4040H·
Address = Word
Within Card 10 ~
Written
Data 10 be Written
Address = Word
Within Card 10 be
Written

Read

Status Register
Status Register
Defaults to
DeviceSta- Data. Toggle'OE", Data. ToggleOE# or
tus Register CE1#or CE2#to
(CE1# andCE2#)
Read Mode
updaie status
to update Status
Register
Registers

Standby

Check SR Bit 7
1 = Ready,
0= Busy

CheckSRBIts
7 and 15
1 = Ready,
0= Busy

x8Mode

x18Mode

Check SR Bit 3

CheckSR Bits
3 and 11
1 = Vpp Detected

290434-17

FULL STATUS CHECK
PROCEDURE
Bus
Cpmmand
Operation

Vpp Range(5)

Error

Standby

t = Vpp Detected
. Low

Low

Data Writ.(6)
Error
Standby

CheckSR BH4
1 = 'Data Wr"e Error

Check SR Bits
4 and 12
1 = Data Write Error

290434-18

Figure 13. Device-Level Automated Wrlt,e Algorithm
NOTES:
1. Repeat fo~ subsequent data writes.
2. In addition, the card's R\=ADY-BUSY STATUS REGISTER or the RDY/BSY# pin may be used.
3. Full device-level status check can be done after each data write or after a sequence of data writes.
4. Writ~ FFH (or FFFFH) after the last data write operation to reset the device(s) to Read Array Mode.
5. If a data write operation fails due to a low Vpp (setting SR Bit 3), the Clear Status Register command
.
before further attempts·are allowed by the Write State Machine..
6. If a data write operation fails during a multiple write sequence, SR Bit 4 (Write Status) will not be
Command User Interface receives the Clear Status Register command.

6.56

MUST be. issued
.
cleared until the
. .

SERIES 2 FLASH MEMORY CARD,S

Bua

Command

xBMocIe

xlBMode

Write

Erase'
Setup

Date = 20H
Address = Block
Within Card to be
Erased

Date = 2020H
AddteS6 = Block Pair
Within Card to be
Erased

Write

Erase

Date = DOH
Address = Block
Within Card to be
Erased

Date = DODOH
Address = Block
Pair Within Card to
be Erased

Operation

Suspend Erese

loop

Read

YES

Delaultsto
Stetus Register
DeviceSia- Date. Toggle OE.oo,
tus Register CEl # OrCE2.oo to
Read Mode
update Stetus
Register.

Stendby

Check SR Bit 7
1 = Ready,
0= Busy

Stetus Register
Date. Toggle OE # or
(CE1.oo andCE2.oo)
\0 update Stetus
Register
Check SR Bits 7 and 15
1 = Ready,
0= Busy

290434-19

FULL STATUS CHECK PROCEDURE
Bus
Command
Operation

xBMode

x16Mode

CheckSRBil3
1 = Vpp Detected
Low

Check SR Bits
3 and 11
Either Bit 1 = Vpp
Detected Low

Vpp Rang.(5)

Error

Standby

Command Sequence

Error

Stendby

Check SR Bits 4 and 5 Check SR Bits 4, 5,
Both 1 = Command
12,13
Sequence Error
Alii = Command
Sequence Error

Block Era ••(6)

Error

Standby

Check SR Bit 5
1 = Block Erase
Error

Check SR Bits
5 and 13
Both 1 = Block
Er~e Failure

290434-20

Figure 14: Device-level Automateci Erase Algorithm
NOTES:
1. Repeat for subsequent data writes.
2. In addition, the card's READY-BUSY STATUS REGISTER .or the RDY/BSY# pin may be used.
3. Full device-level status check can be done after each block erase or after a sequence of block erases.
4.. Write FFH (or FFFFH) after the last block erase operation to reset the device(s) to Ready Array Mode.
5. If a block erase operation fails due to a low Vpp (setting SR Bit 3), the Clear Status Register command MUST be issued
before further attempts are allowed by the Write State Machine.
6. If a block erase operation fails during a multiple block erase sequence, SR Bit 4 (Write Status) will not be cleared until the
Command User Interlace receives the Clear Status Register command.

6-57

' .

SERIES 2 FLASH MEMORY CARDS

Sua
, Operallon
Write

COmmand

x8Mode

x18Mode

Suspend
Erase

Data = BOH.
Address = Desired
Block to Erase
Suspend

Data' - BOBOH.
Address ,i., Desired
BlOck P8Ir to Erase
Suspend

Status Register
Data. Toggle OE#.
CE,# orCE2# to
update Status
Register

Status Register
Data. ToggleOE# or
(CE,# andCE2#)
to updata Status
Register

Check SR Bit 7
1 = Ready.
0= Busy

Check SR'Slt7 and 15
1 = Ready.
0= Busy

CheckSR Bit 6
1 = Suspended.
o = In Progress

Check SR Bit 6 and 14
1 = Suspended.
o = In Progress

Read'

Standby
\

Standby

Write

RdArray
Cmd

Data

Erase
Resume

Data = FFFFH

Read Data
until finished

Data = DOH.
Address = Valid
, Block Address.

Data = DOOOH.
Address = Valid
Block Pair Address,

Read

Write

= FFH

Figure 15. Erase Suspend/Resume Algorithm. Allows Reads to Interrupt Erases.

POWER

CONSUMPTIO~

STANDBY MODE
In mostapplications, software will only be acc~ssing
one device pair at a time. The Series 2 Card IS defined to be in ,the standby mode when one device
pair is in the Read Array Mode while the rem8:ining
devices are in the, Deep-Sleep Mode. The Sarles 2
Card's CEI "", and CE2"" input signals must also be
at VIH.ln standby mode, much of the card's circuitry
is shut off,substantially reducing power consumption. Typical power consumption for a 20 Megabyte
Series 2 card in standby mode is 65 MA.

SLEEP MODE
Writing a "1" to the PWRDWN 'bit of the GLOBAL
POWERDOWN REGISTER places all FlashFile
Memory devices into a Deep-Sleep mode. This disables most of the 28F008SA's circl,Jitry and reduces
. current consumption to 0.2 p.A per device. Additionally when the host system pulls ASIC control logic
high and latches all address and data lines (Le., not
toggling), the card's total current draw is reduced to
approximately 5 p.A (CMOS input levels) for a 2?
Megabyte card. On writing a "0" to the PWRDWN bit
(Global PowerDown Register) or any individual device pair (Sleep Control Register). a Deep-Sleep
mode recovery period must be ,allowed for
28F008SA de'vice circuitry to power bliCk on.

SERIES 2 FLASH MEMORY CARDS

I
~

'",.,'.'

SYSTEM DESIGN CONSIDERATIONS
POWER SUPPLY DECOUPLING

Flash memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current issues-standby, active and transient current peaks, produced by
rising and falling edges of CEl # and CE2#. The
capacitive and inductive loads on the card and internal flash memory device pairs determine the magnitudes of these peaks.
The Flash Memory Card features on-card ceramic
decoupling capacitors connected between Vee and
GND, and between VPP1IVPP2 and GND to help
transient voltage peaks.
On the host side, the card connector should also
have a 4.7 J-LF electrolytic capacitor between Vee
and GND, as well as between VPP1IVPP2 and GND.
The bulk capacitors will overcome voltage slumps
caused by printed-circuit-board trace inductance,
and will supply charge to the smaller capacitors as
needed.

POWER UP/DOWN PROTECTION
Each device in the Flash Memory Card is designed
to offer protection against accidental erasure or writing, caused by spurious system-level signals that
may exist during power transitions. The card will
power-up into the Read Array Mode.
A system designer must guard against active writes
for Vee voltages above VLKO when Vpp is active.
Since both WE# and CEl # (and/or CE2#) must be
low for a command write, driving either to VIH will
inhibit writes. With its Command User Interface, alteration of device contents only occurs after successful completion of the two-step command sequences.

While these precautions are sufficient for most applications, an alternative approach would allow Vee to
reach its steady state value before raising VPP1/
VPP2 above Vee + 2.0V. In addition, upon powering-down, VPP1IVPP2 should be below Vee + 2.0V,
before lowering Vee.

it
"

1·.1."

HOT INSERTION/REMOVAL
The capability to remove or insert PC cards while the
system is powered on (Le., hot insertion/removal)
requires careful design approaches on the system
and card levels. To design for this capability consider card overvoltage stress, system power droop and
control line stability.
A PCMCIAlJEIDA specified socket properly sequences the power supplies to, the flash memory
card via shorter and longer pins. This assures that
hot insertion and removal will not result in card damage or data loss.

PCMCIA CARD INFORMATION
STRUCTURE
The Card Information Structure (CIS) starts at address zero of the card's Attribute Memory Plane. It
contains a variable-length chain of data blocks (tuples) that conform to a basic format as shown in
Table 5. This section describes each tuple contained
within the Series 2 Flash Memory Card.

II
','j

The Device Information Tuple
, This tuple (CISTPLDEV = 01 H) contains information pertaining to the card's speed and size. The Series 2 Card is offered with a 200 nanosecond access
time. Card sizes range between 2 and 20 Megabytes.

Table 5 Tuple Format
Bytes

Data

Tuple Code: CISTPLxxx. The tuple code OFFH indicates no more tuples in the list.

Tuple Link: TPLLlNK. Link to the next tuple in the list. This can be viewed as the. number of
additional bytes in tuple, excluding this byte. If the link field is zero, the tuple body IS empty. If the
link field contains OFFH, this tuple is the last tuple in the list.

2-n

,~
.•..

Bytes specific to this tuple.

~,I

6-59

SERIES 2 FLASH MEMORY CARDS

The Device· Geometry Tuple
This tuple (CISTPLDEVICEGEO =1 EH) is Conceptually similar to a DOS disk geometry tuple
(CISTPLGEOMETRY), except it is not a formatdependent property; this deals with the fixed architecture of the memory device(s).

Level 1 Version/Product
Information Tuple
This tuple (CISTPLVERI = 15H) contains Level-1version COmpliance and card-manufacturer information. Fields are described as follows:
TPLLV1 MAJOR-Major version number = 04H.

Fields are defined as follows:
DGTPLBU8-Value = n, where system bus width
= 2(n -1) bYtes. N = 2 for standard PCMCIA Release 1.0/2.0 'cards.
DGTPL EB8-Value = n, where the memory array's
physical' memory segments have a minimum erase
block size of 2(n-1) address increments of
DGTPLBUS-wide accesses.
DGTPL RB8-Value = n, where the memory array's physical memory segments have a minimum
read block size of 2(n-1) address increments of
DGTPLBUS-wide accesses.
DGTPL WB8-Value = n, where the memory array's physical memory segments have. a minimum
write block size of 2(n-1) address increments of
DGTPLBUS-wide accesses.
DGTPL PART-Value = n, where the memory array's physical memory segments can have partitions
subdividing the arrays .in mini~um granularity of
2(n -1) number of erase blocks.
FL DEVICE INTERLEAVE-Value = n, where card
architectures employ a multiple of 2(n-1) times interleaving of the entire memory arrays with the above
characteristics. Non-interleaved cards have values

= 1.

Jedec Programming
Information Tuple
This tuple (CIS!TPLJEDEC
18H) contains the
Intel manufacturing identifier (89H) and the
28F008SA device ID (A2H).

6-60

TPLLV1 MINOR-Minor version number = 01 Htor
release 2.0.
'
TPLLV1 INFOName of manufacturer
Name of product
Card type
Speed
Register Base
Test Codes
Legalities

= intel;
= SERIES2 c"Card size";

= 2;

=
=
=
=

150 ns or 200 ns
REGBASE4000H
DBBDRELP
COPYRIGHT intel
Corporation 1991

The Configurable Card Tuple
This tuple (CISTPLCONF = 1AH) describes the
interface supported by the card and the locations of
the Card Configuration Registers and the Card Configuration Table.
Fields are described as follows:
TPCC SZ-,-Size of fields byte

01 H.

TPCC LAST-Index number of the last entry in the
Card Configuration Table = OOH.
TPCC RADR-Configuration Registers Base Address in Reg Space = .4000H.
TPCC RMSK-Configuration
Mask = 03H.

Registers

Present

The End-Of-List Tuple
The end-of-list tuple (CISTPLEND = FFH) marks
the end of a tuple chain. Upon encountering this tuple, continue tuple processing as if a long-link to .address 0 of common memory space were encoun~
teredo

SERIES 2 FLASH MEMORY CARDS

Tupl.e
Address

Value

Description

Tuple
Address

Value

OOH

01H

CISTPLDEV

32H

6CH

02H

03H

TPLLlNK

34H

OOH

END TEXT

04H

53H

DEVICE_INFO =
FLASH 150 ns
DEVICE_INFO =
FLASH 200 ns

36H

53H

52H

06H

OSH

06H
OEH
26H
4EH
FFH

CARD SIZE
2M
4M
10M
20M
ENDOF
DEVICE

OAH

1EH

OCH

06H

TPLLlNK

OEH

02H

DGTPLBUS

Description

3SH

45H

3AH

52H

3CH

49H

3EH

45H

40H

53H

42H

32H

44H

2DH

46H

30H
30H
31H
32H

2M = 0
4M = 0
10M = 1
20M = 2

4SH

32H
34H
30H
30H

2M = 2
4M = 4
10M = 0
20M = 0
SPACE

CISTPL
DEVICEGEO

10H

11H

DGTPLEBS

12H

01H

DGTPLR,BS

14H

01H

DGPLWBS

4AH

20H

16H

03H

DGTPLPART

4CH

OOH

END TEXT

4EH

32H

CARD TYPE 2

50H

·41H
42H
45H
5AH
4SH
49H
4CH
4FH

A = 2M,150 ns
B = 4M;150ns
E = 10M, 150 ns
Z = 20M, 150 ns
H = 2M, 200 ns
1= 4M, 200 ns
L = 10M, 200 ns
o = 20M, 200 ns

1BH

01H

FLDEVICE
INTERLEAVE

1AH

1SH

CISTPLJEDEC

1CH

02H

TPLLlNK

1EH

S9H

INTELJ-ID

20H

A2H

2SFOOSJ-ID

22H

15H

CISTPLVER1

24H

50H

TPLLlNK

26H

04H

TPLLV1
MAJOR

2SH

01H

TPLLV1
MINOR

2AH

69H

TPLLV1 INFO
i

2CH

6EH

2EH

74H

30H

65H

6-61

SERIES 2 FLASH MEMORY CARDS

Tuple
Address

Value

52H
54H
56H

45H

9AH

74H

58H

47H

9CH

65H

5AH

42H

9EH

6CH

5CH

41H

AoH

20H

SPACE

5EH

53H

60H

45H

A2H

43H

CORPORATION
C

62H

20H

SPACE

A4H

4FH

A6H

52H

6-62

Description

Tuple
Address

20H

SPACE

96H

69H

52H

REGBASE-R

98H

6EH

Value

Description

64H

34H

4000h
4

A8H

50H

66H

30H

iAAH

4FH

68H

30H

ACH

52H

6AH

30H

AEH

41H

6CH

68H

BOH

54H

6EH

20H

SPACE

B2H

49H

70H

44H

B4H

4FH,

72H

42H

B6H

4EH

74H

. 42H

B8H

20H

SPACE

76H

44H

BAH

31H

78H

52H

BCH

39H

7AH

45H

BEH

39H

7CH

4CH

COH

31H.

7EH

50H

C2H

OOH

END TEXT

80H

OOH

END TEXT

C4H

FFH

ENDOF LIST

C6H

1AH

CISTPLCONF

82H

43H

C8H

06H

TPLLlNK

84H

4FH

86H

50H

CAH

01H

TPCC_SZ

CCH

OOH

TPCC_LAST

CEH

OOH

TPCC_RADR

DOH

40H

TPCC_RADR

88H

59H

8AH

52H

8CH

49H

D2H

03H

TPCC_RMSK

8EH

47H

, D4H

FFH

ENDOF LIST

90H

48H

D6H

FFH

CISTPLEND

92H

54H

D8H

OOH

94H

20H

SPACE

INVALID ECIS
ADDRESS

SERIES 2 FLASH MEMORY CARDS

OPERATING SPECIFICATIONS

NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.

ABSOLUTE MAXIMUM RATINGS·
Operating Temperature
During Read .........•.....•.. 00Cto +60"C(1)
During Erase/Write •.•.•..•..•..• O"C to + 60"C
Storage Temperature .•••.•.••.•• - 30·C to + 70"C
Voltage on Any Pin with
. Respect to Ground •.•.••.... - 2.0V to + 7.0V(2)
VPP1IVPP2 Supply Voltage with
Respect to Ground
during Erase/Write •....•. - 2.0V to + 14.0V(2, 3)
Vee Supply Voltage with
Respect to Ground •..••.•..•.. - 0.5V to + 6.0V

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not rscommended and extended 9XfXJSUre beyond the "Operating Conditions"
may affect device reliability.

NOTES:

1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC input voltage is -0.5V. During transitions,inputs may undershoot to -2.0V tor periods less than 20 ns.
Maximum DC voltage on output pins is Vee + 0.5V, which may overshoot to Vee + 2.0V for periods less than 20 ns.
3. Maximum DC input voltage on VPP1IVpP2 may overshoot to + 14.0V tor periods less than 20 ns.
OPERATING CONDITIONS
Symbol

Parameter

Min

Operating Temperature

Vee

Vee Supply Voltage (5%)

Max

Unit

·C

4.75

5.25

COMMON DC CHARACTERISTICS, CMOS and TTL
Typ

Max

Unit

1,3

±1

±20

,..,A Vee = Vee Max
VIN = Vee or GND

Output Leakage Current

±1

±20

,..,A Vee = Vee Max
VOUT = Vee or GND

VIL

Input Low Voltage

VIH

Input High Voltage (TTL) .

Symbol

Parameter

III

Input Leakage Current

ILO

Notes

Input High Voltage (CMOS)

Min

-0.5

0.8

2.4

Vee

0.7 Vee

Vee

+ 0.3
+ 0.3

Test Condition

V
V

VOL

Output Low Voltage

Vss

0.4

Vee = Vee Min
IOL = 3.2mA

VOH

Output High Voltage

4;0

Vee

Vee = Vee Min
IOH = 2.0mA

VPPL

Vpp during Read Only Operations

1,2

0.0

6.5

VPPH

Vpp during Read/Write Operations

·1

11.4

12.6

VLKO

Vee Erase/Write Lock Voltage

2.0

NOTES:

1. Values are the same for byte and word wide modes and for all card densities.
2. Block Erases/Data Writes are inhibited when Vpp and VPPL and not guaranteed in the range between VPPH and VPPL.
3. Exceptions: With VIN == GND, the leakage on CEl #, CE2#, REG#, OE#, WE#, will be :s; 500 p.A due to internal pullup
resistors and, with VIN = Vee, RST leakage will be :s; 500 p.A due to internal pulldown resistor.

SERIES 2 'FLASK MeMOAY cARDS
DC/CHARACTERISTICS, CMOS
"

Pilrameter . !

symbol

Notes'

Byte Wide Mode
Min

I,CCR

Vee Read Current

WordWl~e

Mode

Unit

Test Condition
'
,

120

Vee = Vee Max;
Contrtjl Signals
=GND'
tcYClE =200 ns,
IOUT,,;,OmA,

Typ

Max

Typ

Max

1,3

Min

Iccw

Vee Write Current

1,3

110

mA "Data Write
In Progress

ICcE

Vcc Erase Current

1,2,3

.45

110

lees

Vee Standby Current

leesl

Vee Sleep Current

2 Meg

220

4 Meg

222

10Meg

230

,63

230

20 Meg

242

2 Meg

4 Meg

1,4,6

1,4,5

10Meg

= VPPH)

IpPE

VppErase
Current (Vpp

= VPPH)

Ippsl..

Vpp Sleep Current

IpPS1

IpPS2

NOTES:

Vpp Standby or
Read current
(Vpp s;: Vce)

Vpp Standby or
Read Current
(Vpp = Vecl

p.A

Data Write
in Progress

1,3

Block (Pair) Erase
in Progress

2 Meg

0.2

4 Meg

,0.4

0.4

' 20

10 Meg

20 Meg

100

2 Meg

2.0

4 Meg

2.2

10 Meg

2.8

20 Meg

3.8

110

3.8

110

2 Meg

180

400

180

400

1,5

1,6

180

410

180

410

10 Meg

181

440

181

440 '

20 Meg

182

4110

182

490

4 Meg

Vce = Vce Max,
Control Signals
= VIH

1,3

20 Meg
Vpp,Write
Current (Vpp

Ippw

Black (Pair) Erase
in Progress

1,6

p.A

('Ali 'currents are in RMS un.less otherwise noted. Typical values at Vcc

= 5.0V, Vpp = 12.0V, T = 25°C.
2. The OatS. Sheet specification for ~he ?8FOO8SA in Erase Suspend (lecES) is 5 mA ~pical an,d 10 mA
w.iththe deVice
deselected. If thedevice(s) are read while in Erase Suspend Mode; current draw,is the sum of IcCESand lecR.
'
3. Standby or Sleep currents are not included for non-accessed devices.
4. Address and data inputS to card static. Control line voltages equal to VIH or Vll'
5. All 28F008SA,devices in Deep-Sleep (Reset-PowerDown) mode.
In Byte and Word Mode,all but two devices in peep-Sleep.

6-64

m!lJ(

SERIES 2 FLASH MEMORY CARDS

DC CHARACTERISTICS, TTL
Symbol

Parameter

Notes

Byte Wide Mode

Word Wide Mode

Min

Typ

Max

Typ

Max

Unit

Test Condition

ICCR

Vcc Read Current

1,3

135

170

mA Vee = Vcc Max,
Control Signals = GND
tCYCLE = 200 ns,
lOUT = OmA

Iccw

Vcc Write Current

1,3

130

160

mA Data Write
in Progress

ICCE

VCC Erase Current

1,2,3

130

160

mA Block (Pair) Erase
in Progress

Ices

Vcc Standby Current

2 Meg
I---4 Meg
----"-

1,4,6

10 Meg

100

Vcc = Vcc Max,
Control Signals
mA =VIH

20 Meg
ICCSL

2 Meg

Vcc Sleep Current

'---

4 Meg

1,4,5

100

10Meg

r-----=20 Meg

Ippw

VppWrite
Current (V pp = VPPH)

1,3

mA Data Write
in Progress

IpPE

Vpp Erase
Current (V PP = VPPH)

1,3

mA Block (Pair) Erase
in Progress

IpPSL

Vpp Sleep Current

0.2

0.4

1.0

20 Meg

2.0

100

2.0

100

2Meg

2.0

4Meg
----=.
10 Meg

2.2

-20 Meg

2.8

3.8

110

3.8

110

2 Meg

180

400

180

400

4 Meg

180

410

180

410

10 Meg

181

440

181

440

20 Meg

182

490

182

490

2 Meg

!-----'4 Meg

r-----=-

1,5

10Meg

---'-

IpPS1

IpPS2

VPP Standby or
Read Current
(Vpp ,;; Vce>

Vpp Standby or
Read Current
(Vpp = Vce>

,----

---:;.

1,6

,..A

1,6

,..A
I':'

,..A

NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, VPP = 12.0V, T = 25'C.
2. The Data Sheet specification for the 28F008SA in Erase Suspend (lcCES) is 5 mA typical and 10 mA max with the device
deselected. If the device(s) are read while in Erase Suspend Mode, current draw is the sum of ICCES and ICCR.
3. Standby or Sleep currents are not included for non-accessed devices.
4. Address and data inputs to card static. Control line voltages equal to VIH or VIL.
5. All 28F008SA devices in Deep-Sleep (Reset-PowerDown) mode.
6. In Byte and Word Mode, all but two devices in Deep-Sleep.
7. The current consumption from the 28F008SA is insignificant in relation to the ASIC's.

I
I·'•.'·
,.

6-65

intel®

SERIES 2FLASHMEMOAY CARDS

AC CHARACTERISTICS'
AC Timing Diagrams and characteristics are guaranteed to meet or exceed PCMCIA Release 2,0 specifications, PCMCIA allows a 300 ns access time for
Attribute Memory, Note that read and write access

timings to the Series 2 Fla,sh Memory Card's Common and Attribute Memory Planes are identical at
200 ns, Furthermore, there is no delay in switching
between the Common and Attribute Memory Planes:

COMMON. AND ATTRIBUTE MEMORY, AC CHARACTERISTICS: Read-Only Operations
Symbol
JEDEC

PCMCIA

tAvAV

tRC

Parameter
Read Cycle Time

Notes

Min
200

Max
I

Unit
ns

Address Access Time

200

tAVQV

ta (A) .

tELQV

ta (CE)

Card Enable Access Time

200

tGLQV

ta (OE)

Output Enable Access Time

100

tEHQX

tdis (CE)

Output Disable Time from CE #

tGHQZ

tdis (CE)

Output Disable Time from OE #

tGLQX

ten (CE)

OlJtput Enable Time from CE #

tELQX

ten (OE)

Output Enable Time from OE #

tAXQX

tv (A)

Data Valid from Add Change
Reset-PwrDwn Recovery to Output Delay

tRHQV
tsu (Vce>

CE Setup Time on Power-Up
First Access after Reset

6-66

500

'\9l
2PJ
IiiiiI

IF'
=>

~
=>

vee POWER-UP

DEVICE AND
ADDRESS SELECTION

STANDBY

-.
@

OUTPUTS ENABLED

DATA VALID

STANDBY

Vee POWER-DOWN

VIH

ADDRESSES (A)

·aeJ
~

VIL

:!!

VIH

...

CE# (c)

:.0
=e
DI

......
3
......

VIL

VIH

<
CD
0

OE# (G)
, VIL

VIH

a.
0

"iii

WE# (w)

::a

VIL

t AXQX

:::I

1/1

VOH

."
HIGH Z
VALID OUTPUT

DATA (0/0)

I·

t AVQV

'1
290434-21

NOTE:

o::a
<

1. The hatched area may be either high or low.

~
::a

0/>
m

-2¥""ilWF3%~~~-=~-'i";;:;r"--;;;;;"-

_~,--";",>~:,:;,,,

iwaea__ik

-__ H

~-_~;;~..i~~-;;~.;.;",;>;,o;;£:i~"",

1i1

., .

SERIES 2 FLASHMEMORV CARDS

COMMON AND ATTRIBUTE MEMORY, AC CHARACTERISTICS: Write Operatjons(1)
Symbol
JEDEC

Parameter

PCMCIA

Notes

Unit

120

Address Setup Time

Address Setup Time for WE #

140

100

140

tsu (D-WEH)

Data Setup Time for WE #

th (D)

Data Hold Time

tree (WE)

Write Recover Time

twc

Write Cycle Time

tWLwH

tw (WE)

Write Pulse Width

tAVWL'

tsu (A)

tAVWH

tsu (A-WEH)

tVPWH

tvps

Vpp Setup to WE# Going High

tELWH

tsu (CE~WEH)

Card Enable Setup Time for WE #

tOVWH
tWHOX

...

. tWHQV1

Duration of Data Write Operation

. tWHQV2

Duration of Block Erase Operation

\aWL

Vpp Hold from Operation Complete
th (OE-WE)

tRHWL

120

WE# HightoRDY/BSY#

tWHRL

tWHGL

Max

200

tAVAV

tWHAX

Min

Write Recovery before Read
Reset-PwrDwn Recovery to WE # Going Low

,""S

0.3

sec

,""S

NOTES:

1. Read timing characteristics during erase and data write operations are the same as during read-only operations. Refer to
AC Characteristics for Read-Only operations.
2. Refer to text on Data-Write and Block-Erase Operations.
BLOCK ERASE AND DATA WRITE PERFORMANCE
Parameter

Notes Min Typ(3) Max Unit

Block Pair Erase Time(1)

1.6

sec

Block Pair Write Time

0.6

2.1

sec

NOTES:

1. Individual blocks can be erased 100,000 times.
2. Excludes System-Level Overhead.
3. 2S'C, 12.0 Vpp.

~:-.

:::s

WRITE VALID

~
~

Vee POWER-UP WRITE DATA WRITE OR
& STANDBY
ERASE SHUP COMMAND

IiiiiJ

F
<=

ADDRESSES (A;"

A,.

ADDRESS" DATA (DATA WRITE)
OR ERASE CONFIRM COMMAND

)(

'IN

READ STATUS
REGISTER DATA

WRITE READ ARRAY
COMMAND

€:

AUTOMATED DATA WRITE
'OR ERASE DELAY

V'H

CEo (E)

V'l

I-

\wHGl

I-

tWHQV1.2

·1

V,H

DE' (G)

V,l

....

:"I

WE' (W)

V'l

V'H
DATA (0/0)

I
I
o

V'H

Vil

VOH
ROY /BSY' (R)

~
in

VOL

:II

V,.

RP'

V'l

l----+f

VpPH

"TI

tVPWH

(V) VpPl

iii:

V1H

V,l

290424-22

:II

NOTE:

By writing the appropriate register, or on power-up, the card control ASIC generates the RP# Signal to the card's devices.

:II

"''''''iPT-'C~

"'
o

iiI;g;::-W~

--&~[

-§fiWW--TWT~~~-::;:~;--

;::-",,~,;~~~~~-

.....

--~----

SERIES 2 FLASH MEMORY CARDS

COMMON AND ATTRIBUTE MEMORY, AC CHARACTERISTICS: CE#-Controlled Write Operations(1)
Symbol
JEDEC

Parameter

PCMCIA

Notes

Min

Unit

.Max

tAVAV

twc

Write Cycle Time

200

tELEH

tw (WE)

Chip Enable Pulse Width

120

ens

tAVEL

tsu (A)

Address Setup Time

tAVEH

tsu (A-WEH)

Address Setup Time for CE #

140

tVPEH

tvps

Vpp Setup to CE# Going High

100

tWLEH

tsu (CE-WEH)

Write Enable Setup Time for CE #

140

tDVEH

tsu (D-WEH)

Data Setup Time for CE#

tEHDX

th (D)

Data Hold Time

tEHAX

trec (WE)

tEHRL

Write Recover Time

CE # High to RDY IBSY #

ns
....

120

tEHOV1

Duration of
Data Write

Duration of Data Write Operation

""s

tEHOV2

Duration of
Erase

Duration of Block Erase Operation

0.3

sec

Vpp Hold from Operation Complete

1,2

tovvL
tEHGL
tRHEL
NOTES:

th (OE-WE)

Write Recovery before Read
Reset-PwrDwn Recovery to CE # Going Low

""s

1. Read timing characteristics during erase and data write operations are the same as during read-only operations. Refer to
AC Characteristics for Read.Only operations.
2. Refer to text on Data-Write and Block-Erase Operations.

6-70

Vee POWER-UP WRITE DATA WRITE OR
& STANDBY
ERASE SETUP COMMAND

agJ

IiiiiI

ADORESSES(A;H~

IF'

AUTOMATED DATA WRITE
OR ERASE DELAY

READ STATUS
REGISTER DATA

€:

WRITE READ ARRAY
COMMAND

Vil
leHA'

VIH

~
~
~

WRITE VALID
ADDRESS & DATA (DATA WRITE)
OR ERASE CONFIRM COMMAND

WE' (W)

VIL

....

!II»

leHGl
VIH
OE' (G)
Vil

leHOVI,2

VIH

CEo (E)
Vil

~
0'

3
0'
...
:::e

0'
~
III

VIH
DATA (0/0)
Vil

VOH
ROY /BSY' (R)
VOL

en
m

VIH

m
en

RP'

Note: As shown, RP# is generated in the cord by the ASIC by writing to the appropriate register.

VIC

"11

~
en

t VPEH

VpPH

::J:

i:
m
i:

Vpp (V) VPPL
VIH
Vil

1MMMMI\MMMMI
290434-23

NOTE:
By writing the appropriate register, or on power-up, the card control ASIC generates the RP# signal to the card's devices.

o:D
<
o

Cf'
"-J

~;o~~~r:#Qi'-SiW:~""'f

-__ .:=,i'-:O:

~--,<;:;~~,ila"f~~iI-~-ir~~.~-~

Sj:RIES 2 FLASH MIM()RY CARDS
\

Surfaco A

&.
TP

--L
2x T

-l r--

C MIN

L t 0.008

PMIN&

S MIN

Wt 0.004

X t 0.002

Yt 0.002

0.294
( 10.0)

3.370
(85.60)

0.394
(10.0)

0.118
(3.0)

0.065
( 1.65)

2.126
(54.0)

0.039
(1.00)

0.083
( i.60)

&.
&.
3

PO.LARIZATION KEY LENGTH.
INTERCONNECT AREA TOLERANCE = to.002
SUBSTRATE AREA TOLERANCE = to.OD4
MILLIMETERS AR.E IN PARENTHESIS O.

Figure 19. Series 2 Flash Memory Card Package Dimensions
6-72

290434-24

SERIES 2 FLASH MEMORY CARDS

--I

I--

0.037 (0.94) MIN

PIN INSERTION

290434-25

Figure 20. Card Connector Socket

.&.
2.

SOCKET CONTACT

PIN/SOCKET CONTACT AREA
MILLIMETERS ARE IN PARENTHESIS

0
290434-26

L1MAX

0.020
(0.5)

L3REF

Pin Type-See Table 1
Detect . 0.059 (1.5) ± 0.039
General 0.084 (2.1) ± 0.064
Power
0.098 (2.5) ± 0.078

0.024
(0.6)

Figure 21. Pin/Socket Contact Length with Wipe

6-73

+i..I·
•". . ;:~e

SERIES 2 FLASH MEMORY CARDS

Table 5 Capacitance TA = 25°C, f =1 0 MHz
Symbol

Comme;clal

Characteristics

Min

·Vcc, Vpp

p,F

Output capacitance

Addr~ss/Control Capacitanc~

CIN

(Ao;..Ae; CE1 #, CE2#)

Address/Control Capacitance(A9~A24' all others)

CaUT

Unit

"IIax

ORDERING INFORMATION
iMC020FLSA,SBXXXXX
WHERE:
= INTEL
= MEMORY CARD
= DENSITY IN MEGABYTES
(002,004,010,020 AVAILABLE)
FL
= FLAsH TECHNOLOGY
S
= BLOCKED ARCHITECTURE
A
REVISION
SBXXXXX = CUSTOMER IDENTIFIER
i
MC
020

ADDITIONAL INFORMATION
28F008SA FlashFile™ Memory Data Sheet
iMCOO1 FLKA 1-Mbyte Flash Memory Card
iMC002FLKA 2-Mbyte Flash Memory Card
iMC004FLKA 4-Mbyte Flash Memory Card
AP-361 "Implementing the Integrated Registers of the Series 2 Flash Memory Card"
AP-364 "28F008SA Automation and Algorithms"
.
.
ER-27 '.'The Intel 28F008SA Flash Memory"
ER-28 "ETOX III Flash Memory Technology"
. AP-359 "28F008SA Hardware Interfacing"
AP-360 "28F008SA Software Drivers"

ORDER NUMBER
290429
290399
290412
290388
292096
292099
294011
294012
292094
292095

REVISION HISTORY
Number
02 .'

03
,

6-74

Description
Added 150 ns TUPLE, 'Deleted 250 ns TUPLE
Corrected Global POWer Register Address to 4002H
Corrected Write Protection Register Address to 41 04H
Corrected Ready-BuSy Mode Register Address to 4140H
Icc Standby Byte Wide Mode MAX/TYP Increased
Added Power-On Timing Spec
\
Added First Access after Reset Spec
Changed Advanced Information to P~eliminary
Added 2 MByte card support
Changed write timing waveforms to match PCMCIA
Changed PowerDown(PWD),to Reset-PowerDown (RP)

intel~

•
•
•
•
•

iMC004.fLKA
4-MBYTE FLASH MEMORY CARD

Inherent Nonvolatlllty (Zero Retention
Power)
- No Batteries Required for Back-up
High-Performance Read
- 200 ns Maximum Access Time
CMOS Low Power Consumption
- 40 mA Typical Active Current (XS)
- SOD I-'-A Typical Standby Current
Flash Electrical Zone-Erase
- 2 Seconds Typical per 256 Kbyte
Zone
- Multiple· Zone-Erase
Random Writes to Erased Zones
-10 I-'-s Typical Byte Write

•
•
•

•
•

Write Protect Switch to Prevent
Accidental Data Loss
Command Register Architecture for
Microprocesssor/Mlcrocontroller
Compatible Write Interface
ETOXTM II Flash Memory Technology
- 5V Read, 12V Erase/Write
- High-Volume Manufacturing
Experience
PCMCIA/JEIDA 6S-Pin Standard
- Byte- or Word-wide Selectable
Independent Software & Hardware
Vendor Support
-Integrated System Solution Using
Flash Filing Systems

Intel's iMC004FLKA Flash Memory Card is the. removable solution for storing and transporting important user
data and application code. The combination of rewritability and nonvolatility make the Intel Flash Memory Card
ideal for data acquisition and updatable firmware applications. Designing with Intel's Flash Memory Card
enables OEM system manufacturers to produce portable and dedicated function systems that are higher
performance, more rugged, and consume less power.
The iMq004FLKA conforms to the PCMCIA 1.0 international standard, providing standardization at the hardware and data interchange level. OEMs may opt to write the Card Information Structure (CIS) at the memory
card's address OOOOOH with a format utility. This information provides data interchange functional capability.
The 200 ns access time allows for "execute-in-place" capability, for popular low-power microprocessors.
Intel's 4-MByte Flash Memory Card operates in a byte-wide and word-wide configuration providing performance/power options for different systems.
Intel's Flash Memory card employs Intel'sETOX " Flash Memories. Filing systems, such as Microsoft's· Flash
File System (FFS), facilitate data file storage and card erasure using a purely nonvolatile medium in the DOS
environment. Flash filing systems, coupled with the Intel Flash Memory Card, effectively create an all-silicon
nonvolatile read/write random access memory system that is more reliable and higher performance than diskbased memory systems.

'Microsoft is a trademark of Microsoft Corp.
October 1993
Order Number: 290388-004

6-75

intel®

iMC004FLKA

3.3:1:0.1 mm

r--

'r--r

54.0:1: 0.1 mm

,,-

I
I

I
I
I

E
E

..
'"d
,,;
'"

IX>

.E
::E

I
I

::E

q
0

Jl~

800ooo0000ooo00oooooo000oooo00000@
00000000000000000000000000000000
68 '

..I-

FRONT SIDE

34 ,

BACK SIDE

'290388-1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

GNO

Vee

03
04
05
06
07
CE 1 #
A10
CE#
A11
A9
As
A13
A14
WE#
NC

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

GNO

35
36
37
38
39
40
41
42
43

45·
46
47
48
49
50
51

VPP1
A16
A15
A12
A7

As
A5
A4

Ao
Do
01
02
WP
GNO

VpP2
NC

A17

52
53
54
55
56
57
58
59
60
61
62
63

A1S

A19

65
66
67
68

C01*
0 11
0 12
0 13
0 14
0 15
CE2*
NC

A20
A21
Vee

NC
NC
NG

NC
NC
NC
NC
REG#1
BV02*2
BV01*2

0 10
C02 *
GNO

NOTES:,
1. REG# = register memory select = No Connect (NC). unused. When REG# is brought low. PCMCIA/JEIDA standard card information structure data is expected. This is accomplished by formatting the card with this data.
2. BVD# = battery detect voltage = Pulled high through pull up resistor.

Figure 1_ IMC004FLKA Pin Configurations

6-76

iMC004FLKA

Table 1. Pin Description
Symbol

Type

Name and Function

Ao-A21

ADDRESS INPUTS for memory locations. Addresses are internally
latched during a write cycle.

Do-D15

I/O

DATA INPUT/OUTPUT: Inputs data during memory write cycles;
outputs data during memory read cycles. The data pins are active high
and float to tri-state OFF when the card is deselected or the outputs
are disabled. Data is internally latched during a write cycle.

CE1#,CE2#

CARD ENABLE: Activates the card's high and low byte control logic,
input buffers, zone decoders, and associated memory devices. CE # is
active low; CE # high deselects the memory card and reduces power
consumption to standby levels.

OE#

OUTPUT ENABLE: Gates the cards output through the data buffers
during a read cycle. OE# is active low.

WE#

WRITE ENABLE controls writes to the control register and the array.
Write enable is active low. Addresses are latched on the falling edge
and data is latched on the rising edge of the WE # pulse.

NO.TE:
With Vpp ,,; 6.5V, memory contents cannot be altered.
VPP1, VPP2

ERASE/WRITE POWER SUPPLY for writing the command register,
erasing the entire array, or writing bytes in the array.

Vee

DEVICE POWER SUPPLY (5V ± 5%).

GND

GROUND

CD1#,CD2#

CARD DETECT. The card is detected when CD l # and
CD2 # = ground.

WP.

WRITE PROTECT. All write operations are disabled with WP
high.

NC
BVD1#,BVD2#

= active

NO INTERNAL CONNECTION to device. Pin may be driven or left
floating.

BATTERY VOLTAGE DETECT. NOT REQUIRED.

;'"1

1.\

:.~I;.

Ii
!j

6-77

IMC004FLKA

!!f..!~
.!!:...-

Da-o,s
I/o tRANSCEIVERS
AND
BUFFERS

DO D-r
WE#
OE#

r---

,cr~,
0-0

-= \..

AO
A, -A2 ,

ADDRESS
BUFfERS
AND
DECODERS

CE2 #
Ce:,

WRITE PROTECT
SWITCH
Ao-A17

CEHO # - CEH3 #
CELo # -CEL3 #

28F020
~ Ao-A'7
REG#

-Co,-# -

~
--

Do-D-r

CE#

I-

WE#

OE#
VSS Vee Vpp ,

28F020
I-

~ Ao-A17 Da-o,S

CE#

I-

WE#

OE#
VSS Vee VpP2

I I I

CARD DETECT

~ Ao-A'7

BDV, #

I-

CE#

WE#

I-

OE#

Do-D-r

I I I

Vss Vee Vpp ,

BVD #

•
•
•

~ Ao-A,7

D8 -o,s

I-

CE#

WE#

I-

OE#
Vss Vee VpP2

•
•
•

Vee
BA HERY VOLTAGE
DETECT

OE#

GND

Vp ,
Vpp

290388-2

Figure 2. IMC004FLKA Block Diagram

6-78

iMC004FLKA

APPLICATIONS
The iMC004FLKA Flash Memory Card allows for the
storage of data files and application programs on a
purely solid-state removable medium. System resident flash filing systems, such as Microsoft's Flash
File System, allow Intel's ETOX II highly reliable
Flash Memory Card to effectively function as a physical disk drive.
User application software stored on the flash memory card substantially reduces the slow disk-DRAM
download process. Replacing the disk results in a
dramatic enhancement of read performance and
substantial reduction of active power consumption,
size, and weight-considerations particularly important in portable PCs and equipment. The
iMC004FLKA's high performance read access time
and command register microprocessor write interface allows for use of the flash memory system in an
"execute-in-place" architecture. This configuration
eliminates the need for the redundancy associated
with DRAM and Disk memory system architectures.
ROM based operating systems, such as Microsoft's
MS-DOS ROM Version allow for "instant-on" capability. This enables the design of PCs that boot, operate, store data files, and execute application code
from/to purely nonvolatile memory.
The PCMCIAlJEIDA 68-pin interface with flash filing
systems enables the end-user to transport user files
and application code between portable PCs and
desktop PCs with memory card Reader/Writers. Intel Flash Memory cards provide durable nonvolatile
memory storage for Notebook PCs on the road, facilitating simple transfer back into the desktop environment.

For systems currently using a static RAM/battery
configuration
for
data
acquisition,
the
iMC004FLKA's inherent nonvolatility eliminates the
need for battery backup. The concern of battery failure no longer exists, an important consideration for
portable computers and medical instruments, both
requiring continuous operation. The iMC004FLKA
consumes no power when the system is off. In addition, the iMC004FLKA offers a considerable cost
and density advantage over memory cards based on
static RAM with battery backup.
The flash memory card's electrical zone-erasure,
byte writability, and complete nonvolatility fit well
with data accumulation and recording needs. Electrical zone-erasure gives the designer the flexibility to
selectively rewrite zones of data while saving other
zones for infrequently updated I!i>ok-up tables.

6-79

inte!®

iMC004FLKA

In the absence of high voltage on the VPP1;2 pins,
the iMC004FLKA remains in the read-only mode.
Manipulation of the external memory· card-control
pin yields the standard read, standby, and output
disable operations.
The same read, standby, and output disable operations are available when high voltage is applied to
the VPP1;2 pins. In addition, high voltage on VPP1;2
enables erasure and rewriting of the accessed
zone(s). All functions assoCiated with altering zone
contents-erase, erase verify, write, and write verify-are accessed via the command register.
Commands are written to the internal memory reg.ister(s), decoded by zone size, using standard microprocessor write timings. Register contents for a given zone serve as input to that zone's internal statemachine which controls the erase and rewrite circuitry. Write cycles also internally latch addresses and
data needed for write and erase operations. With the
appropriate command written to the register(s), standard microprocessor read timings output zone data,
or output data for erase and write verification.

Note that two zones logically adjacent in x1 p mode
are multiplexed through Do-D7 in x8 mode and are
toggled by the Ao address. Thus,· zone specific
erase operations must be kept discrete in x8 mode
by addressing even bytes only for one-half of the
zone pair, then addressing odd bytes only for the
other half.

Card Detection
The flash memory card features two card detect pins
(CD1;2#) that allow the host system to determine if
the card .is proPElrly loaded. Note that the two pins
are located at opposite ends of the card. Each CD#
output should be read through a port bit. Should only
one of the two bits show the card to be present, then
the system should instruct the user to re-insert the
card squarely into the socket. Card detection can
also tell the system whether or not to redirect drives
in the case of system booting. CD1;2# is active low,
internally tied to ground.

Write Protection
Byte-wide or Word-wide Selection
The flash memory card can be read, erased. and
written in a byte-wide or word-wide mode. In the
word-wide configuration VPPl and/or CEl # control
the LO-Byte while VPP2 and CE2# control the HIByte (Ao = don't care).
Read, Write, and Verify operations are byte- or wordoriented, thus zone independent. Erase Setup and
Begin Erase Commands are zone dependent such
that commands written to any address within a 256
Kbyte zone boundary initiate the erase operation in
that zone (or two 256 Kbyte zones under word-wide
operation).
Conventional x8 operation uses CEl # active-low,
with CE2 # high, to read or write data through the
Do-D7 only. "Even bytes" are accessed when Ao is
low, corresponding to the low byte of the complete
x16 word. When Ao is high, .the "odd byte" is accessed by transposing the high byte of the complete
x16 word onto the Do-D7 outputs. This odd byte
corresponds to data presented on D8-D15 pins in
x16 mode.

6-80

The flash memory card features three types of write
protection. The first type features a mechanical
Write Protect Switch that disables the circuitry that
. control Write Enable to the flash devices. When the
switch is activated, the WE# internal to the card is
forced high, which disables any writes to the Command Register. The second type of write protection
is based on the PCMCIAlJEIDA socket. Unique pin
length assignments provide protective power supply
sequencing during hot inserti.on and removal. The
third type operates via software control through the
Command Register when the card resides in its connector. The Command Register of each zone is only
active when VPP1;2 is at high voltage. Depending
upon the application, the system designer may
choose to make VPP1;2 power supply switchableavailable only when writes are desired. When VPP1;2
= VPPL, the contents of the register default to the
read command, making the iMC004FLKA a readonly memory card. In this mode, the memory contents cannot be altered.
The system designer may choose to leave VPP1;2 =
VPPH, making the high voltage supply constantly
available. In this case, all Command Register functions are inhibited whenever Vee is below the write
lockout voltage, VLKO. (See the section on Power
Up/Down Protection.) The iMC004FLKA is designed
to accommodate either design practice, and to encourage optimization of the processor-memory card
interface.

iMC004FLKA

BUS OPERATIONS
Read

reader/writer; Following a write of 90H to a zone's
Command Register, a read from address location
OOOOOH on any zone outputs the manufacturer code
(89H). A read from address 0002H outputs the memory device code (SOH).

The iMCOO4FLKA has two control functions, both of
which must be logically active, to obtain data at the
outputs. Card Enable (CE II) is the power control
and should be used for high and/or low zone(s) selection. Output Enable (OEI1) is the output control
and should be used to gate data from the output
pins, independent of accessed zone selection. In the
byte-wide configuration, only one CE II is required.
The word-wide configuration requires both CElis active low.

Zone erasure and rewriting are accomplished via the
Command Register, when high voltage is applied to
VPP1~. The contents of the register serve as input to
that zone's internal state-machine. The state-machine outputs dictate the function of the targeted
zone.

When VPP1~ is high (VPPH), the read operations can
be used to access zone data and to access data for
write/erase verification. When VPP1~ is low (VpPU,
only read accesses to the zone data are allowed.

The Command Register itself does not occupy an
addressable memory location. The register isa latch
used to store the command, along with address and
data information needed to execute the command.

Output Disable
With Output Enable at a logic-high level (VIH), output
from the card is disabled. Output pins are placed in a
high-impedance state.

Standby
With one Card Enable. at a logic-high level, the
standby operation disables one-half of the x16 output's read/write buffer. Further, only the zone corresponding to the selected address. within the upper or
lower CE1~11 bank is active at a time. (NOTE: Ao
must be low to select the low half of the x16 word
when CE211 = 1 and CE1 II = 0.) All other zones
are deselected, substantially reducing card power
consumption. For deselected banks, the outputs are
placed in a high-impedance state, independent of
the Output Enable signal. If the iMC004FLKA is deselected during erasure, writing, or write/ erase veri,fication, the accessed zone draws active current until the operation is terminated.

Intelligent Identifier Command
The manufacturer- and device-codes can be read
via the Command Register, for instances where the
iMC004FLKA is erased and rewritten in a universal

Write

The Command Register is written by bringing Write
Enable to a logic-low level (VIU, while Card Enable(s) is/are low. Addresses are latched on the fall. ing edge of Write Enable, while data is latched on
the rising edge of the Write Enable pulse. Standard
microprocessor write timings are used.
.
Refer to AC Write Charcteristics and the Erase/
Write Waveforms for specific timing parameterS.

COMMAND DEFINITIONS
When low voltage is applied to the Vpp pin(s), the
contents of' the zone Command Register(s) default
to OOH, enabling read-only operations.
Placing high voltage on the Vpp pines) enable(s)
read/write operations. Zone operations are selected
by writing specifiC data patterns into the Command
Register. Tables 3 and 4 define these iMC004FLKA
register commands for both byte-wide and word.
wide configurations.
All commands written to the Command Register require that the Zone Address be valid or the incorrect
.zone will receive the command. Any Command/
Data Write or Data Read requires the correct Valid
Address.

6-81

IMC004FLKA

Table 2. Bus Operations
PIns

Notes

Operation
Read (xS)

[1,71
. VPP2 VPP1

CE#2

CE#1

WE# . Da-D15

Do-D1

VPPL

VIL

VIH

VII.

VIL

VIH

Tri-state

Data Out-Even

VPPL

VpPL

VIH

VIL

VIH

Tri~state

Data Out-Odd

VPPL

VIL

VIH

VIL

VIH

, 11

VPPL

VIL

VIH

. Data Out

Data Out

Output Disable

VPPL

VIH

Tri-state

Standby

VPPL

VIH

Tri-state

~
z Read (xS)

Read (xS)
cC Read (x16)

1&1

a::

[1,7]

Data Out' Tri-state

Read (xS)

3,S

Vppx

VPPH

VIL

VIH

VIL

VIH

Tri-state

Data Out-Even

,Read (xS)

3,9

VpPH

VPPl<

VIH

VIL

VIH

Tri-state

Data Out-Odd

Read (xS)

VpPH ·VpPX

VIL

VIH

VIL

VIH

Data Out Tri-state

VIL

VIH

Data Out Data Out

1&1

!::

a::
.....
==

R~ad

(x16)

Write (xS)

3,11

VPPH

5,S

VPPX

VPPH

VIL

Write (xS)

VPPH

VpPX

Write (xS)

VPPH·

Write (x16)

VPPH

Standby

~
a::

VPPH

Output Disable

VIH

VIL

VIH

VIL

Tri-state

Data In-Even

VIH

VIL

VIH

VIL

Tri-state

Dat~

VPPX

.. VIL

VIH

VIL

Data In

Tri-state

VPPH

VIL

VIH

VIL

Data In

VPPH

VIH

Tri-state

VPPH

VP~H

VIH

VIL

Tri-state

Tri~state

In-Odd,

NOTES:
1. Refer to DC Characteristics. When VPP1,1.! = VPPL memory contents can be read but not written or erased.
2. Manufacturer and device codes' may be aCCl;lssed via·a command register write seqUence. Refer to lable 3. All other
. .
.
addresses low.
3. ,Read operations with VPP1,1.!= VPPH may.access array data or the "ntelligent Identifier cades,
4. WithVpP1,1.!at high voltage, the standby.currentequals Icc +Ipp (standby).
5. Refer to Table 3 for valid Data-In during write operation.
.
6. X can be VIL or VIH.
.
7. Vppx == VPPH or VPPL.
S. This xS operation reads or writes the low byte ofthe·x16 word on 000_7, I.e., Ao low reads "even" byte in xS mode.
9. This xS operation reads or writes the high byte of the x16 word on 000"7 (transposed from 008-15), l.e./Ao high reads
"odd" byte in xS mode..
to. This xS operation reads or writes the high byte of. the x16 on 008-15. An Is "don't care."
11. Ao is "don't care," unused in li16 mode. High and low bytes are presented. simultaneously.

·6-S2

iMC004FLKA

Table 3. Command Definitions Byte-Wide Mode
Command

Bus
First Bus Cycle
Second Bus Cycle
Notes Cycles
Req'd Operatlon(1) Address(2) Data(3) Operatlon(1) Addres8(2) Data(3)

Read Memory

Write

OOH

Write

90HT

Write

20H

Write

20H

Write

AOH

Read

Set-up Write/Write

EVO

Write

40H

Write

Write Verify

Write

COH

Read

WVO

Reset

Write

FFH

Write

FFH

Read Intelligent 10 Codes
Set-up Erase/Erase
Erase Verify

Read

Table 4. Command Definitions Word-Wide Mode
Command

Bus
First Bus Cycle
Second Bus Cycle
Notes Cycles
Req'd Operatlon(1) Address(2) Data(3) Operation(1) Address(2) Data(3)

Read Memory

Write

OOOOH

Read Intelligent 10 Codes

Write

9090H

Read

Set-up Erase/Erase

Write

2020H

Write

2020H

Erase Verify

Write

AOAOH

Read

EVO

Set-up Write/Write

Write

4040H

Write

Write Verify

Write

COCOH

Read

WVO

Reset

Write

FFFFH

Write

FFFFH

NOTES:
1. Bus operations are defined in Table 2.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during enise verify.
RA = Read Address
WA = Address of memory location to be written.
ZA = Address of 256 Kbyte zones involved in erase operation.
Addresses are latched on the falling edge of the Write Enable pulse.
3. 10
= Data read from location IA during device identification. (Mfr = 89H, Device = BDH).
EVD = Data read from location EA during erase verify.
WD = Data to be written at location WA. Data is latched on the rising edge of Write Enable.
WVD = Data read from location WA during write verify. WA is latched on the Write command.
4. Following the Read inteligent 10 command, two read operations access manufacturer and device codes.
5. Figure 5 illustrates the Erase Algorithm.
6. Figure 6 illustrates the Write Algorithm.
7. The second bus cycle must be followed by the desired command register write.
8. The Reset command operation on a zone basic, To reset entire Card, requires reset write cycles to each zone.

6-83

iMC004FLKA

R~ad

Command

While VPP1;2 is high,for erasure and writing, zone
memory contents can be accessed via the read
command. The read operation is initiated by writing
OOH (OOOOH for the word-wide configuration) into the
zone Command Register(s) .. Microprocessor read
cycles retrieve zone data. The' accessed zone remains enabled for reads until the Command Registeres) contents are altered.
The default contents of each zone;s register(s) upon
VPP1;2 power-up is OOH (OOOOOH for word-wide).
This default value ensures that no spurious alteration of memory card contents occurs during the
VPP1;2 power transition. Where the VPP1;2 supply is
left at VPPH, the memory card powers-up and remains enabled for reads until the command Register
contents of targeted zones are changed. Refer to
the AC Read Characteristics and Waveforms for
specific timing parameters.

Intelligent Identifier Command
Each zone of the iMC004FLKA contains an Intelligent Identifier
,identity memory card device characteristics. The operation is initiated by writing90H
(9090H for word-wide) into the Command Registeres) with Zone Address. Following the command
write, a· read cycle from address OOOOOH retrieves
the manufacturer code 89H (8989H for word-wide).
A read cycle frOm address 0002H returns the device
code BOH (BOBOH forword-wide). To terminate the
operation, it is necessary to write another valid command into the register(s).

Set-up Erase/Erase Commands
Set-up Erase stages the targeted zone(s) for electrical erasure of all bytes in the zone. The set-up erase
operation is performed by writing 20H to the Com,
mand Register (2020H for word-wide) with Zone Address.
.
To commence zone-erasure, the erase command
(20H or 2020H) must again be written to the registeres). The erase operation begins with the rising
edge of the Write-Enable. pulse and terminates with
the rising edge of the next Write-Enable pulse (Le.,
Erase-Verity Command with zone address).

tents are protected against erasure. Refer to AC.
Erase Characterstics and Waveforms for specific
timing parameters.

Erase-Verify Command
The erase command erases all of the bytes of the
zone in parallel. .After each erase operation, all bytes
in .the zone must be individually verified ..In bytemode operations, zones are segregated by Ao in
odd and even banks; erase and erase verify operations must be done in complete passes of evenbytes-only then odd-bytes-only. See the Erase Algorithm for byte-wide mode. The erase verity operation
is initiated by writing AOH (AOAOH for word-wide) into
the Command Register(s). The address for the
byte(s) to be verified must be supplied as it is
latched on the falling edge of the Write Enable
pulse. The Jegister write terminates the erase operation with the rising edge. of its Write Enable pulse.
The enabled zone applies an internally-generated
margin voltage to the addressed byte. Reading FFH
from the addressed byte indicates that all bits in the
byte are erased. Similarly, reading FFFFHfrom the
addressed word indicates that all bits in the word are
erased.
The erase-verity command must be written to the
Command Register prior to each byte (word) verification to latch its' address. The process continues
for each byte (word) in thezone(s) until a byte (word)
does not return FFH (FFFFH) data, or the last address is accessed.
In the case where the data read is not FFH(FFFFH),
another erase operation is performed. (Refer to Setup Erase/Erase.) Verification then reSUmes frOm the
address of the last-verified byte. (word). Once all
bytes (words) in the zone(s) have been verified, the
erase step is complete. ,The accessed zone can now
be written. At this point, the verity operation is termi"
natedby writing a valid command (e.g., Write Setup) to the Command Register. The Erase algorithms
for byte-wide and word-wide configurations illustrate
how commands and bus operations are combined to
perform electrical erasure of the iMC001 FLKA. Refer to AC Erase Characteristics and Waveforms for
specific timing parameters.

Set-up Write/Write Commands
This two-step sequence of set-up followed by execution ensures that zone memory contents are not acCidentally erased. Also, zone-erasure can only occur
when high voltage is applied to the VPP1;2 pins. In
the absence of this high voltage, zone memory con-

6-84

Set-up write is a command-only operation that
stages the targeted zone for byte writing. Writing
40H (4040H) into the Command Register(s) performs the set-up operation.

iMC004FLKA

Once the write set-up operation is performed, the
next Write Enable pulse causes a transition to an
active write operation. Addresses are internally
latched on the falling edge of the Write Enable
pulse. Data is internally latched on the rising edge of
the Write Enable pulse. The rising edge of Write Enable also begins the write operation. The write operation terminates with the next rising edge of Write
Enable, which is used to write the verify command.
Refer to AC Write Characteristics and Waveforms
for specific timing parameters.

Write Verify Command
The iMC004FLKA is written on a byte-by-byte or
word-by-word basis. Byte or word writing may occur
sequentially or at random. Following each write operation, the byte or word just written must be verified.
The write-verify operation is initiated by writing COH
(COCOH) into the Command .Register(s) with the correct address. The register write(s) terminate(s) the
write operation with the rising edge of its Write Enable pulse. The write-verify operation stages the accessed zone(s) for verification of the byte or word
last written. The zone(s) apply(ies) an internally-gen~
erated margin voltage to the byte or word. A microprocessor read cycle outputs the data. A successful
comparison between the written byte or word and
true. data means that the byte or word is successfully
written. The write operation then proceeds to the
next desired byte or word location. The Write algo e
rithms for byte-wide and word-wide configurations illustrate how commands are combined with bus operations to perform byte and word writes. Refer to
AC Write Characteristics and Waveforms for specific
timing parameters.

Reset Command
A reset command is provided as a means to safely
abort the erase- or write-command sequences. Following either set-up command (erase or write) with

two consecutive writes of FFH (FFFFH for wordwide) will safely abort the operation. Zone memory
contents will not be altered. A valid command must
then be written to place the accessed. zone in the
desired state.

EXTENDED ERASE/WRITE CYCLING
Intel has designed extended cycling capability into
its ETOX II flash memory technology enabling a
flash memory card with a MTBF that is many times
more reliable than rotating disk technology. Resulting improvements in cycling reliability come without
increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field minimizes
the probability of oxide defects in the region. The
lower electric field greatly reduces oxide stress and
the probability of failure.

WRITE ALGORITHMS
The write algorithm(s) use write operations of 10 /-Ls
duration; Each operation is followed by a byte or
word verification to determine when the addressed
pyte or word has been successfully written. The aigorithm(s) allows for up to 25 write operations per
byte or word, although most bytes and words verify
on the first or second operation. The entire sequence of writing and byte/word verification is performed with Vpp at high voltage.

ERASE ALGORITHM
The Erase algorithm(s) yield(s) fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the write
algorithm, to simultaneously remove charge from all
bits in the accessed zone(s).
Erasure begins with a read of memory zone contents. Reading FFH (FFFFH) data from the accessed zone(s) can be immediately followed by writing to the desired zone(s).

6-85

IMCOO4FLKA
Forzo~~$beingerased andrewritten,uniform .and
reliable .erasure is ensured by first writing all bits in
the a.cce$~ed zone to their charged state (data =
OOHbyte~Wide, OOOOOH word-wide). This is accornplishe!1,using the write algorithm, in approximately
four seConds per zone.

Eraseel(ecution then continues with an initial erase
openltion.Erase verification (data = FFH byte-wide,
FFFFH .word-wide) begins at address OOOOOH and
continue$ through the zone to the last address, .or
until data other than FFH (FFFFH) is encountered.

(Note: byte-wide erase operation requires, separate
even- and odd-address passes to handle the individual256 Kbyte zones.) With each erase operation, an
increasing number Of bytes or words verify to the
erased state. Erase efficiency maybe improved by
storing the address of the .last byte or word verified
in a register(s). Following the next erase operation,
verification starts at the stored address location. Follow this procedure until all. bytes in the zone are
eras,ed. Then, re-start the procedure for the next
zone or word-wide zone pair. Erasure typically occurs in two seconds per zone.

INITIALIZE· SIZE
AND NUMBER OF ZONES
ZONE L = 0
ZONE H = 1

290388-3

Figure 3. Fuil Card Erase Flow

6-86

IMC004fLKA

(START WRITING
[IJ

Bus
Operation

APPLY
VPPH [2J

PLSCNT" 0

WRITE

C~D(A/D)

...

6 ~S

!
READ DATA
DEVICE

FRO~

Write

Set-up
Write

Data = 40H
+ Valid Address

Write

Valid address/data

Write(3)
Verify

Duration of Write
Operation (twHWH1)
Data = COH at Valid
Address; Stops (4)
Write Operation
tWHGL

Write

WRITE
+ ADDRESS

C~D

I TI~E OUT

Wait for Vpp ramp
to VPPH (= 12.0V) (2)

Standby

fTlWE OUT 10 ~S I

j,VERIfY

Standby

Read

Read byte to verify
Write Operation
at Valid Address

Standby

Compare data output
to data expected

N
VERIFY
DATA

INC
PLSCNT.
= 251

INCRE~ENT

Comments

Initialize pulse-count

WRITE SET-UP
WRITE C~D + ADDRESS

Standby

Command

LAST
ADDRESS
?

ADDRESS

WRITE
READ C~D

vpPL [2J

(

.L
APPLY

WRITING
CO~PLETED

Write

I I
(

APPLY
VpPL [2J

Read

Standby

Data = OOH, rese~s the
register for read
operations.
Wait for Vpp ramp
to VPPL(2)

WRITE
ERROR

290388-4

NOTES:

1. CAUTION: The algorithm MUST BE FOLLOWED to
ensure proper and reliable operation of the device.
2. See DC Characteristics for the value of VPPH and
VPPL'

3. Write Verify is only performed after a by1e write oper·
ation. A final read/compare may be performed (option.
al) after the register is written with the Read command.
4. Refer to principles of operation.

I
I"

Figure 4. Write Algorithm for Byte-Wide Mode

I
i'

6·87

"r;

iMC004FLKA

Bus
Operation

Command

Standby

Comm.nt.

WaitforVpp ramp to VPPH (= 12.0V)(2)

Use with Write Operation Algorithm
Initialize even/odd Addresses, Erase Pulse
Width, and Pulse Count

Write

Set-up
Erase

Data = 20H

+ Address

Wr~e

Erase

Data = 20H

+ Address

Standby

Wr~e

Duration of Erase operation (tWHWH2)

Erase
Verity(3)

Addr = Byte to verify;
Data = AOH; Stops

Standby

Erase Operation(4) tWHGL

Read

Read byte to verify erasure at address

Standby

Compares output to FFH Increment pulse
count

Write

Standby

Reed

Data = OOH, resets the register for read
operations.
Wait for Vpp ramp to VPPL(2)

NOTES:

1. CAUTION: The algorithm MUST BE FOLLOWED to
ensure proper and reliable operation of the device.
2. See DC Characteristics for the value of VpPH and
VPPL·

3. Erase Verify is only performed after a chip erasure. A
final read/ compare may be performed (optional) after
the register is written with the Read command.
4. Refer to principles of operation.

Figure 5. Erase Algorithm for Byte-Wide Mode

iMC004FLKA

Comments

Wait for Vpp ramp to VPPH

ADAS

address to write

W_DAT = data word to write

Initialize Data Word Variables:
V-DAT ~ valid data
W_COM = Write Command
V_COM ~ Write Verify Command
PLSCNT_HI ~ HI Byte Pulse Counter
PLSCNT_LO ~ LO Byte Pulse Counter
FLAG ~ Write Error Flag
Write Set-up Command
Address needs to be Valid

PLSCNLHI = 0
PLSCNLLO= 0
FLAG 0

W~ite

High/Low Byte
Compare Be Mask
Subroutine

See Write Verify and Mask Subroutine
Write Verify Command

F_OAT

flash memory data

Compare flash memory data to valid data
(word compare). If not equal, check for
Write Error flag. If Flag not set, compare
High and Low Bytes in the Subroutine.

Check buffer of 1/0 port for more data to write

Write READ_COM

Reset device for read operation

Apply VpPL

Turn offVpp

290388-6

Figure 6. Write Algorithm for Word-Wide Mode

6-89

intel~

IMC004FLKA

Comments
To look at the LO Byte,
Mask' the HI Byte with
00
W_COIoi = (W _COIoi OR OOFFH)
LOAT (LOAT OR OOFFH)
v_COIoi = (LCOIoi OR OOFFH)

If the LO Byte verifies,
mask the LO Byte
commands with the reset
command (FFH)
If the LO Byte-does not
verify, then increment its
pulse counter and check
for max count
FLAG = 1 denotes a LO
Byte error
Repeat the sequence for
the HI Byte'

W_COIoi = (w _COIoi OR FFOOH)
LOAT=(LOAT OR FFOOH}
V_COIoi (v _COIoi OR FFOOH)

FLAG = 2 denotes a HI
Byte error
FLAG = 3 denotes both
a HI and LO Byte errors.
Flag = 0 denotes no
max count errors;
continue with algorithm .

';'

290388-7

-Masking can easily and efficiently be done in assembly languages. Simply load word registers with the incoming data
(F_OAT), the program commands and the verify commands. Then manipulate the HI or LO register contents.

Figure 7. Write Verify and Mask Subroutine for Word.Wlde Mode

6-90

intel~

IMC004FLKA

Comments
Wait for Vpp to stabilize.
Use Write operation algorithm in xB or x16
configuration

FLAG

Initialize Variables:
PLSCNT_HI = HI Byte Pulse Counter
PLSCNT_LO = LO Byte Pulse Counter
FLAG = Erasure error flag
ADRS = Address
E_COM = Erase Command
V_COM = Verify Command
Erase Set-up Command

=0
=2020H
=AOAOH

E_COM
V_COM

Start Erasing
Duration of Erase Operation

Erase Verify Command stops erasure
See Block Erase Verify & Mask Subroutine

When both devices at ADRS are erased,
F_DATA = FFFFH. If not equal, Increment
the pulse counter and check for last pulse
Reset commands default to
(E-COM = 2020H) (V_COM
before verifying next ADRS

= AOAOH)

Reset device for read operation
Turn offVpp

290388-8

NOTE:
X16 Addressing uses A1-A21 only.

= 0 throughout word-wide operation.

Figure 8. Erase Algorithm for'Word·Wlde Mode

6-91

iMC004FLKA

Comment.
This subroutine reads ~he data
word (F_DATA). It then masks
the HI or LO Byte of the Erase
and Verify Commands from
executing during the next
operation.
If both HI and LO Bytes verify.
thenretum.
Mask· the til Byte with OOH.

cco'" = (CCO'"
V_COM

or OOFFH)

=(V_COM or OOFFH)

If the LO Byte verifies erasure.
then mask· the next erase and
verify commands with FFH
(RESEn.
If the LO Byte does not verify.
then increment its pulse counter
and check for max count. FLAG
= 1 denotes a LO Byte error.

Repeat the sequence for the HI
Byte.
CCOM
V_COM

=(CCOM or FFOOH)
=(LCOM or FFOOH)
Flag = 2 denotes a HI Byte error.
Flag = 3 denotes both a HI and
LO Byte errors. FLAG = 0
denotes no max count errors; .
continue with algorithm.

290388-9

·Masking can easily and efficiently be done in assembly languages, Simply load word registers with the incoming.data
(F_DAn. the program commands and the verify commands. Then manipulate the HI or LO register contents.

Figure 9. Erase Verify and.Mask Subroutine for Word·Wlde Mode

6·92·

IMC004FLKA

SYSTEM DESIGN CONSIDEj:lATIONS
Three-Line Control
Three-line control provides for:
, a. the lowest possible power dissipation and.
b, complete assurance that output bus contention
will not occur.
'
To efficiently use these three control inputs, an address-decoder output should drive CE1 2#, while
the system's Read signal controls the card OE # signal, and other parallel zones. This, coupled with the
internal zone decoder, assures that only ,enabled
memory zones have active outputs, while deselected zones maintain the low power standby condition.

Power-Supply Decoupllng
Flash memory, power-switching characteristics require careful device decoupling. System designers
are interested in three supply current issues-standby, active and transient current peaks,' produced by
falling and rising edges of CE1,,2#' The capacitive
and inductive loads on the card and internal flash
memory zones determine the magnitudes of these
'
peaks.
Three-line control and proper decoupling capacitor
selection will suppress transient voltage peaks. The
iMC004FLKA features on-card ceramic decoupling
capacitors connected between Vee and Vss, and
between VPP1IVPP2 and Vss.

The card connector, should also have a 4.7 p,F electrolytic capacitor between Vee and Vss, as well as
between VPP1IVPP2 and Vss. The bulk capacitors
will overcome voltage slumps caused by printed-drcuit-board trace inductance, and will supply charge
to the smaller capacitors as needed.

A system designer must guard against active writes
for Vee voltages above VLKO when Vpp is active.
Since both WE# and CE1 2# must be low for a
command write, driving either to VIH will inhibit
writes. With its control-register architecture, alteration of zone contents only occurs after successful
completion of the two-step command sequences.
While these precautions are sufficient for most applications, it is recommended that Vee reach its steady
state value before raising VPP1,,2 above Vee + 2.0V.
In addition,upon powering-down, VPP1,,2 should be
below Vee + 2.0V, before lowering Vee.

6-93

IMCOO4FLKA

Absolute Maximum Ratings·

NOTICE: This is a.production data sheet, The specifications· are subject to change. without notice.

Operating TemperaMe
i During Read :........ , ....•...•. O"C to + 6O"C(1)
.During Erase/Write ...• ~ .'.....•.• O"C to + sa·C

• WARNING: Stressing thB device beyond thB "Absolute

Maximum Ratings" may cause permanent c1Bmsge.
Thf!se are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex~
tef1(led exposurs beyond the "Operating Conditions"
may affect device ralisbilily.

Temperature UnderBtas ......... -1 O"C to + 70·C
Storage Temperature .. -. ......... -30·C to + 70·C
Voltage on Any Pin with
.
.
Respect to Ground .......... - 2.0V to + 7.0V(2)
VPP1IVPP2 Supply Voltage with
Respect to Ground
During.Erase/Write ....... - 2.0V to

+ 14.0V(2, 3)

Vcc Supply Voltage with
..
Respectto Ground ..• , .•...• ...: 2.0V to

+7.0V(2)

NOTES:

1. Operating temperature is for colVmercial product defined by this specification.
2. Minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods less
than 20 ns. Maximum DC voltage on output pin~ is Vcc + 0.5V, which may overshoot to Vee + 2.0V for
periods less than 20 ns~.·
.
3. Maximum DC input voltage on VPP1IVPP2 may overshoot to + 14.0V for periods less than 20 ns.

OPERATING CONDITIONS
Symbol.
TA

Umlts

Parameter
. Operating Temperature

Unit

Comments

·C

For Read-Only and
Read/Write Operations

Min

Max

Vee

Vee Supply Voltage

4.75

5.25

VPPH

Active VPP1, VPP2
Supply Voltages

11.40

12.60

VPPL

VPP During Read Only
Operations

0.00

6.50

DC CHARACTERISTICS-Byte Wide Mode
Symbol

Parameter

Notes

Limits
Min Typical Max

Unit

Test Conditions

1,4

±1.O

±20

p.A

Vec =; Vcc max
VIN. = Vce or Vss

Output Leakage Current

±1.0

±20

p.A

Vcc = Vcc max
VOUT = Vee or Vss

Vcc Standby Current

0.8

1.6

Vcc = Vcc max, CE = Vee ±0.2V

rnA

CElli = VIH,VCC = Vee max

Vee = VecmaxCElII =VIL
f = 6 MHz, lOUT = 0 mA

III

Input Leakage Current

ILO
Iccs

ICCl

Vcc Active Read Current

1,2

lec2

Vee Write Current

1,2

.5.0

Writing in Progress

ICC3

Vec Erase Current

1,2

Erasure in Progress

ICC4

Vec Write Verify Current

1,2

Vpp = VpPH
Write Verify in Progress

6~94

intel®

iMC004FLKA

DC CHARACTERISTICS-Byte Wide Mode (Continued)
Symbol

Parameter

Notes

Limits
Min

Typical

Max

Unit

Test Conditions

Vpp = VpPH
Erase Verify in Progress

±80

/A-A

Vpp";: Vee

1.6

Vpp> Vee

Vpp = VpPH
Write in Progress

Vpp = VPPH
Erasure in Progress

1,3

3.0

6.0

Vpp = VpPH
Write Verity in Progress

1,3

3.0

6.0

Vpp = VpPH
Erase Verify in Progress

~0.5

0.8

2.4

Vee ± 0.3

0.40

IOl = 3.2mA
Vee = Vee min

IOH = ~2.0 mA
Vee = Vee min
Note: Erase/Write are
Inhibited when Vpp = VPPl

1,2

Ices

Vee Erase Verify Current

Ipps

Vpp Leakage Current

IpP1

Vpp Read Current
or Standby Current

1,3

0.7

IpP2

Vpp Write Current

1,3

8.0

IpP3

Vpp Erase Current

1,3

IpP4

Vpp Write Verify Current

IpP5

Vpp Erase Verify Current

Vil

Input Low Voltage

Vpp ~ Vee

±0.08

VIH

InplAt High Voltage

VOL

Output Low Voltage

VOH1

Output High Voltage

VPPl

Vpp During Read-Only
Operations

0.00

6.5

VPPH

Vpp During Read/Write
Operations

11.40

12.60

VlKO

Vee Erase/Write Lock
Voltage

2.5

3.8

NOTES:
1. All currents are in RMS unlessotherwise noted. Typical values at Vee = 5.0V, Vpp "" 12.0V, T = 25"e.
2. 1 chip active and 15 in standby for byte-wide mode.
3. Assumes 1 Vpp is active.
4. Due to 100 kO pull up resistors, OE#, eE1 #, eE2#. and WE# will exhibit <;; 55 /-LA of additional ILl when VIN = Vss.

PC CHARACTERISTICS-Word Wide Mode
Symbol

Parameter

Notes

Limits
Min Typical Max

Test Conditions

Unit

1,4

± 1.0

±20

/A-A

Vee = Vee max
VIN = Vee or Vss

Output Leakage Current

±1.0

±20

/A-A

Vee = Vee max
VOUT = Vee or Vss

Vee Standby Current

0.8

1.6

= Vee max, CE# = Vee
CE# = VIH, Vee = Vee max

III

Input Leakage Current

IlO
Ices

Vee

±0.2V

6-95

intet®

IMCQQ4FLKA

DC CHARACTERISTICS-Word Wide Mode (Continued)
Symbol

Parameter

Notes

lee1

Vee Active Read Current

lee2

. Limits

Unit

Test Conditions

Typical

Max

1,2

100

mA Vee = Vee max CE# = VIL
I =.6 MHz, lOUT = 0 mA

Vee Write Current

1,2

5.0

mA Writing in Progress

lee3

Vee Erase Current

1,2

lee4

Vee Write Verily Current

1,2

mA Vpp = VpPH
Write Verify in Progress

lees

Vee Erase Verify Current

1,2

mA Vpp = VPPH
Erase Verily in Progress

Ipps

Vpp Leakage Current

IpP1

Vpp Read Current

IpP2

Min

±160

p.A

Erasure in Progress

Vpp

Vee

> Vee

1,3

1.5

Vpp Write Current

1,3

Vpp = VPPH
Write in Progress

IpP3

Vpp Erase Current

1,3

Vpp = VPPH
Erasure in Progress

IpP4

Vpp Write Verily Current

, 1,3

5.0

Vpp = VPPH
Write Verily in Progress

Ipps

Vpp Erase Verily Current

1,3

5.0

mA Vpp = VPPH
Erase Verily in Progress

VIL

Input Low Voltage·

-0.5

0.8

VIH

Input High Voltage

2.4

Vee ± 0.3

VOL

Output Low Voltage

0.40

IOL = 3.2 mA
Vee = Vee min

VOH1

Output High Voltage

3.8

IOH = -2.0 mA
Vee = Vee min

VpPL

Vpp During Read-Only
Operations

0.00

6.5

Note: Erase/Write are
Inhibited when Vpp = VPPL

VPPH

Vpp During Read/Write
Operations

11.40

12.60

VLKO

Vee Era~e/Write Lock
Voltage

2.5

or Stam:lby Current

3.0

mA Vpp

±.16

Vpp

Vee

NOTES:

1.
2.
3.
4.

All currents are in RMS unless otherwise noted. Typical values at Vee = S.OV, Vpp = 12.0V, T ,; 2S'e.
2 chips active and 14 in standby for word-wide mode.
Assumes 2 VpPS are active.
Due to 100 k!l pull up resistors, OE#, eE1 #, eE2#, and WE# will exhibit os; S5 fJ-A of additionallu when VIN

6-96

Vss.

IMC004FLKA

CAPACITANCE T
Symbol

= 25°C, f = 1.0 MHz

Parameter

Notes

Limits
Min

Max

Unit

I,~'

~~1'

Conditions

CIN1

Address Capacitance

VIN =OV

CIN2

Control Capacitance

VIN = OV

COUT

Output Capacitance

VOUT = OV

CliO

1/0 Capacitance

VI/O = OV

•. '.l

AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ..........•...... Val and VOH1
Input Timing Reference Level .......... Vil and VIH
Output Timing Reference Level ........ Vil and VIH

AC CHARACTERISTIC5-Read-Only Operations
Symbol

Characteristic

Notes

Min
200

Max

Unit

tAVAv/tRC

Read Cycle Time

tElQV/tCE

Chip Enable Access Time

200

ns
ns

tAVQV/tACC

Address Access Time

200

tGLQV/tOE

Output Enable Access Time

100

tElQX/tlZ

Chip Enable to Output
in LowZ

tEHQZ

Chip Disable to Output
in HighZ

tGlQX/tOLZ

Output Enable to Output
in Low Z

tGHQZ/tOF

Output Disable to Output
in High Z

tOH

Output Hold from Address,
CE II! , or OE II! Change

tWHGl

Write Recovery Time
before Read

5
60

ns
ns

5
60

1,2

ns.

,...s

NOTES:
1. Whichever occurs first.
2. Rise/Fall Time,;; 10 ns.

6-97

IMC004FLKA

Vee POWER-UP /
STANDBY,

DEVICE: AND
ADDRESS SELECTION

ADDRESSES

OUTPUTS [NASL[O

STANDBY/
Vee POWER-DOWN

DATA VALID

ADDRESS STABLE

1---~-~------C---tAVAV

(..c) - - - - - - - - - - - - . . j

OEM (Gili')

t WHGl

+-----1

WE'" (Will')

IilGH Z

DATA (00)

5.0V

Vee

VAllO OUTPUT

j.
290388-10

NOTE:
CE# refers to CE1. 2#'

Figure 10. AC Waveforms for Read Operations

6·98

intel~

IMC004FLKA

AC CHARACTERISTICS-For Write/Erase Operations
Symbol

CharacterIstIc

Notes

MIn

Max

UnIt

tAVAV/tWC

Write Cycle Time

1,2

200

tAVWL/tAS

Address Set-up Time

1,2

tWLAX/tAH

Address Hold Time

1,2

100

tovWH/tOS

Data Set-up Time

1,2

tWHOX/tOH

Data Hold Time

1,2

tWHGL

Write RecoverY Time before Read

1,2

,""s

tGHWL

Read Recovery Time before Write

1,2

,...s

twLOZ

Output High-Z from Write Enable

1,2

tWHOZ

Output Low-Z from Write Enable

1,2

tELWL/tCS

Chip Enable Set-up Time before Write

1,2

tWHEH/tCH

Chip Enable Hold Time

tWLWH/tWP

Write Pulse Width

tWHWL/twPH

Write Pulse Width High

tWHWH1

60
40

1,2

100

1,2

Duration of Write Operation

1,2,3

,...s

tWHWH2

Duration of .Erase Operation

1,2,3

9.5

tVPEL

Vpp Set-up Time

1,2

100

1. Read timing parameters during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Rise/Fall time s; 10 ns.
3. The integrated stop Umer terminates the write/ erase operations, thereby eliminating the need for a maximum specification.

ERASE/WRITE PERFORMANCE
Typ

Max

UnIt

1,3,4

2.0

sec

1,2,4

4.0

sec

10(6)

Notes

Zone Erase Time
Zone Write Time
MTBF

II.~
•. '.·

!
,

I";~~

NOTES:

Parameter

to Chip Enable Low

Min

Hrs

NOTES:

1. 25°C. 12.0V Vpp.
2. Minimum byte writing time excluding system overhead is 16,..s (10,..s program + 6,..s write recovery). while maximum is
400 ,..s/byte (16
x 25 loops allowed by algorithm). Max chip write time is specified lower than the worst case allowed by
the write algorithm since most bytes write significantly faster than the worst case byte.
3. Excludes OOH writing Prior to Erasure.
4. One zone equals 256 Kbytes.
5. MTBF - Mean Time between Failure. 50% failure point for disk drives.

,..S

I
I

6-99

iMC004FLKA

Vee POWER-UP .t
STANDBY

SET-UP WRITE
COMMAND

WRITE COMMANO
LATCH ADDRESS It: DATA

WRITE
VERIFY

" WRITING

COMMAND

WRITE
VERIFICATION

STANDBY!

Vee POWER-OQWN

ADDRESSES

CE# (E#)

DATA (00)

5.0V

Vee
OV

290388-11

NOTE:
CE# refers to CE1, 2#'

Figure 11. AC Waveforms for Write Operations

6-100

iMC004FLKA

ERASE
Vee POWER-UP !:

SET-UP ERASE

STANoe~

COWNAND

ERASE COWh4ANO

ERASING

....ERIFy

[RASE

CO~MAND

VERIfiCATION

STANDBY I
Vcc POWER-OOWN

ADDRESSES

C[# (EIII)

0[# (G#)

WEfil (WII)

DATA (00)

s.ov
V~C
OV

290388-12

NOTE:
CE# refers

CE#1, 2.

Figure 12. AC Waveforms for Erase Operations

6-101

IMCOO4FLKA

ALTERNATIVE CE #-CONTROLLED WRITES
Symbol
I

Character,lstlc

Min

Max

Unit

200

tAVEL

.. 'Address Set-up Time

tELAX

Address Hold Time
Data Set-up Time

100
80
30

tOVEH

Write cYcle Time

tAVAV

Notes

tEHOX

Data Hold Time

tEHGL

Write Recovery Time before Read

. p.s

tQHEL

Read Recovery Time before Write

p.s

twLEL

Write Enable Set-Up Time
before Chip-Enable

0
100

. 100'

. tEHwH

Write Enable Hold Time

tELEH

Write Pulse Width

tEHEL.

Write Pulse Width High

tpEL

Vpp Set-up Time
to Chip Enable Low

NOTES:

1. Chip Enable Controlled Writes: Write operations are driven by the vaiid combination of Chip Enable and Write. Enable. In
systems where Chip Enable defines the write pulse width (with a longer Write Enable timing wavefbrm) all set-up, hold and
,inactive Write Enable times' should be measured relative to the Chip Enable waveform.

6-102

intel®

iMC004FLKA

PROGRAt.I
SET-UP PROGRAht
COMMAND

Vee POWER-UP &:
STANDBY

PROGRAt.I COIilIolAND
LATCH ADDRESS &; DATA

VERIFY
PROGRAMMING

COM hilAND

PRQGRAIit
VERIFICATION

STANDBY I
Vee POWER-OOWN

ADDRESSES

W[# (E#)

"HEH

---+---/--

DATA (DO)

5.0V

Vee
OV

12.0V
Vpp

t'vPEl

~
290388-13

NOTE:
CE# refers to CE1, 2#.

Figure 13. Alternate AC Waveforms for Write Operations

6-103

intel®

IMC004FLKA

ORDERING INFORMATION

II 1·IMlel~ioi.IFI(lKIAI , islBlxlilxjxi~1
I

OiliER IDENTIFIER

REVISI~N

ORO-WIDE
ARCH ITECTURE

FL= FLASH

00.

=. IIIEGABYTE
DENS ITY IN IIIEGABYTES
MC= IIIEIII~RY CARD
I=INTEL
.=pACKAGE

PLACEH~LDER

ADDI'TIONAL IN.FORMATION
ER-20, "ETOX II Flash Memory Technology"
RR-SO, "ETOX II Flash Memory Reliability Data Summary"
AP-343, "Solutions for High Density Applications using. Flash Memory"
RR-70, "Flash Memory Card Reliability Data Summary"

290388-14

·ORDER NUMBER
294005
293002
29~079

293007

REVISION HISTORY
Number

Description

Removed PRELIMINARY
Removed ExCA Compliance Section
Clarified need for Valid Address during CommandS"
Corrected Vpp = VPPH in Erase Algorithm
Increased ICC2-ICC5 D.C. Current Specifications for
both Byte-Wide and Word-Wide modes.
Revised and updated Application Section discussion
Changed order number

Change signals with "_" to """
Change TIC values

6-104

iMC002FLKA
2-MBYTE FLASH MEMORY CARD

•
•
•
•
•

Inherent· Nonvolatillty (Zero Retention
Power)
- No Batteries Required for Back-up
High-Performance Read
- 200 ns Maximum Access Time
CMOS Low Power Consumption
- 25 rnA Typical Active Current (XS)
- 400 /-LA Typical Standby Current
Flash Electrical Zone-Erase
- 2 Seconds Typical per 256 Kbyte
Zone
- Multiple Zone-Erase
Random Writes to Erased Zones
-10 /-Ls Typical Byte Write

•
•
•
•
•

Write Protect Switch to Prevent
Accidental Data Loss
Command Register Architecture for
Microprocesssor/Mlcrocontroller
Compatible Write Interface
ETOXTM " Flash Memory Technology
- 5V Read, 12V Erase/Write
- High-Volume Manufacturing
Experience
PCMCIAlJEIDA 6S-Pln Standard
- Byte- or Word-wide Selectable
Independent Software & Hardware
Vendor Support
-Integrated System Solution Using
Flash Filing Systems

Intel's iMC002FLKA Flash Memory Card is the removable solution for storing and transporting important user
data and application code. The combination of rewritability and nonvolatility make the Intel Flash Memory Card
ideal for data acquisition and updatable firmware applications. Designing with Intel's Flash Memory Card
enables OEM system manufacturers to produce portable and dedicated function systems that are higher
performance, more rugged, and consume less power.
The iMC002FLKA conforms to the PCMCIA 1.0 international standard, providing standardization at the hardware and data interchange level. OEMs may opt to write the Card Information Structure (CIS) at the memory
card's address OOOOOH with a format utility. This information provides data interchange functional capability.
The 200 ns access time allows for "execute-in-place" capability, for popular low-power microprocessors.
Intel's 2-MByte Flash Memory Card operates in a byte-wide and word-wide configuration providing performance/power options for different systems.

Intel's Flash Memory card employs Intel's ETOX II Flash Memories. Filing systems, such as Microsoft's· Flash
File System (FFS), facilitate data file storage and card erasure using a purely nonvolatile medium in the DOS
environment. Flash filing systems, coupled with the Intel Flash Memory Card, effectively create an all-silicon
nonvolatile read/write random access memory system that is more reliable and higher performance than diskbased memory systems.
'-~.

'Microsoft is a trademark of Microsoft Corp.
October 1993
Order Number: 290412-003

6-105

inte!®

IMC002FLKA

54.0*0.1 mm
I

/'I'

rT3.3 * 0.1 mm

r--

"--

E
E

'"ci

..
'"

E
.!
c

J1:

i,
I

FRONT SIDE

3.4, •

.,II

tJ·~
68 •

BACK SIDE

LJ
290412-1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

GNO
03
04
05
Os

D7
CE1#
A10
OE#
. A11
Ag
Aa
A13
A14
WE#
NC
Vee

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

VPP1
A1S
A15
A12
A7
As
A5

~
A3
A2
A1
AO

Do
01
02
WP
GNO

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

GNO
C01#
011
012
013
014
015
CE2#
NC
NC
NC
A17
Ala
A19
A20
NC
Vee

52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

VPP2
NC
NC
NC
NC
NC
NC
NC
NC
REG#
BV02#2
BV01#2
Oa
09
010
C02#
GNO

NOTES:
1. REG# = register memory select = No Connect (NCl. unused. When REG;!! is brought low. PCMCIAlJEIOA standard card information structure data is expected. This is accomplished by formatting the card with this data.
2. BVO;!! = battery detect voltage = Pulled High through Pull-Up Resistor.

Figure 1.IMC002FLKA Pin Configurations

6-106

IMC002FLKA

Table 1. Pin Description
Symbol

Type

Name and Function
ADDRESS INPUTS for memory locations. Addresses are internally latched
during a write cycle.

Ao-A20

Do-D15

I/O

DATA INPUT/OUTPUT: Inputs data during memory write cycles; outputs
data during memory read cycles. The data pins are active high and float to tristate OFF when the card is deselected or the outputs are disabled. Data is
internally latched during a write cycle.

CE1#,CE2#

CARD ENABLE: Activates the card's high and low byte control logic, input
buffers, zone decoders, and associated memory devices. CE# is active low;
CE #. high deselects the memory card and reduces power consumption to
standby levels.

OE#

OUTPUT ENABLE: Gates the cards output through the data buffers during a
read cycle. OE # is active low.

WE#

WRITE ENABLE controls writes to the control register and the array. Write
enable is active low. Addresses are latched on the falling edge and data is
latched on the rising edge of the WE # pulse.
NOTE:
With Vpp ::;; 6.5V, memory contents cannot be altered.

VPP1, VPP2

ERASE/WRITE POWER SUPPLY for vvriting the command register, erasing
the entire array, or writing bytes in the array.

Vee

DEVICE POWER SUPPLY (5V ±5%).

GND

GROUND

CD 1#, CD2#

CARD DETECT. The card is detected at CD1/2# = ground.

WRITE PROTECT. All write operations are disabled with WP = active high.

BATTERY VOLTAGE DETECT. NOT REQUIRED.

NO INTERNAL CONNECTION to device. Pin may be driven or left floating.

NC
BVD1#,BVD2#

6-107

IMCOO2FLKA

00-015

%-0,5

"""'--"'-

~
!i.E..-

DO-Oj

I/O TRANSCEIVERS
AND
BUFFERS

WE#
OE#

r----

'~K
~

\... WRITE PROTECT
SWITCH
An-An

Ao
Al -Azo
CEz #
CE, #

ADDRESS
BUFFERS
AND
DECODERS

CEHo #-CEH3 #
CELo #-CEL3 #

28F020

Do-P7

~ An-An

REG#

CE#

WE#

28F020
f-<

-- OE#
Vss Vce VpP1

I I I

CARD DETECT

Do-Oj

""" An-A,7

OE#
Vss Vee Vppz

I I I
""" An-A,7

08-0,5

CE#

WE#

I- OE#

I-

OE#
vss Vee vppz

vss Vee vpP1

BVD2 #

I-

.... CE#

BDV1 #

CE#

I- WE#

COl #

08 -0,5 I-

""" An-An

••
•

•
•
•

Vee
BATTERY VOLTAGE
DETECT
WE#

GND
Vee
VPP

290412:-2

Figure 2.lMC002FLKA Block Diagram

6·108

iMC002FLKA

APPLICATIONS
The iMC002FLKA Flash Memory Card allows for the
storage of data and application programs on a purely solid-state removable medium. System resident
flash filing systems, such as Microsoft's Flash File
System, allow Intel's ETOX II highly reliable Flash
Memory Card to effectively function as a physical
disk drive.
User application software stored on the flash memory card substantially reduces the slow disk-DRAM
download process. Replacing the disk results in a
dramatic enhancement of read performance and
substantial re~uction of active power consumption,
size, and weight-considerations particularly important in portables and dedicated systems. The
iMC002FLKA's high performance read access time
and command register microprocessor write interface allows for use of the flash memory system in an
"execute-in-place" architecture. This configuration
eliminates the 'need for the redundancy associated
with DRAM and Disk memory system architectures.
ROM based operating systems, such as Microsoft's
MS-DOS ROM Version allow for "instant-on" capability. This enables the design of systems that boot,
operate, store data files, and execute application
code from/to purely nonvolatile memory.
The PCMCIAlJEIDA 68-pin interface with flash filing
systems enables the end-user to transport data and
application code between portables and host systems. Intel Flash Memory Cards provide durable
nonvolatile memory storage protecting valuable user
code and data. .
For systems currently using a static RAM/battery
configuration for data acquisition, the iMC002FlKA's
inherent nonvolatility eliminates the need for battery
backup. The concern of battery failure no longer exists, an important consideration for portable computers and medical instruments, both requiring continu-

ous operation. The iMC002FLKA consumes no power when the system is off. In addition, the iMC002FLKA offers a considerable. cost and density advantage over memory cards based on static RAM with
battery backup.

I
'(

The flash memory card's electrical zone-erasure,
byte writability, and complete nonvolatility fit well
with data accumulation and recording needs. Electrical zone-erasure gives the designer the flexibility to
selectively rewrite zones of data while saving other
zones for infrequently updated look-up tables, for
example.

PRINCIPLES OF OPERATION
Intel's Flash Memory Card combines the functionality of two mainstream memory technologies: the rewritability of RAM and the nonvolatility of EPROM.
The flash memory card consists of an array of individual memory devices, each of which defines a
physical zone. The iMC002FLKA's memory devices
erase as individual blocks, equivalent in size to the
256 Kbyte zone. Multiple zones can be erased
simultaneously provided sufficient current for the appropriate number of zones (memory deviCes). Note,
multiple zone erasure requires higher current from
both the Vpp and Vee power supplies. Erased zones
can then be written in bit- or byte-at-a-time fashion
and read randomly like RAM. Bit level write capability also supports disk emulation.
In the absence of high voltage on the VPP1,12 pins,
the iMCO02FLKA remains in the read-only mode.
Manipulation of the external memory card-control
pin yields the standard read, standby, and output
disable operations.
The same read, standby, and output disable operations are available when high voltage is applied to
the VPP1,12 pins. In addition, high voltage on VPP1,12

6-1Q9

JMCOO2FLKA.
enables. erasure and tewritingof t~e accessed
zone(s). ~AII functions associated with. altering zone
contents---erase, erase verify,'write, and write veri. fy-are accessed via t!:lecommand register.
Commands are written to the internal memory register(s), decoded .by zO,ne size,. using standard microprocessor write timings.. Register.contents. for' a given zone serve as input to that zQne'sinternal statemachine which controls the erase.and rewrite circuitry. Write cycles also internally latch addresses and
data needed for write and erase operations. With the
appropriate command written to the register(s), standard microprocessor read timings output zone data,
or output data for erase and writ~ verification. .

Card Detection
The flash memory card features two card detect pins
. (CD1,t2#) that allow the host system to determiQ~if
the card is properly lOaded .. Note that the two pins
are located at opposite ends of the card. Each CD#
output should be read through a port bit. 'Should only
.one of the two bits show the card to be present, then
, the system should instruct the user to re-insert the
card squarely into the s.ocket. Card detection can
also tell the system whether or not to redirect drives
in.the case of system booting. CD1,t2# is active low,
internally tied to ground. ' .

Write Protection

Byte-wide or Word-wide Selection
The flash memory card can be read, erased, and
written in a byte-wide or word-wide mode. -In the
word-wide configuration VPP1 and/or CE1 # control
the LO-Byte while VPP2 and CE2# control the. HIByte (Ao =; don't care):
Read, Write, and 'Verify operations are byte- or wordoriented, thus zone independent. Erase Setup and
Begin Erase Commands are zone dependent such
that commands written to any address within a 256
Kbyte zone boundary initiate the erase operation in
that zone (or tWo 256 Kbyte zones under word-wide
operation).
Conventional x8 operation uses CEt # active-low,
with CE2 # high, to read or write data through the
00-07 only. "Even bytes" are accessed when Ao is
low, corresponding to. the low byte of the complete
x16 word; When Ao is high, the "odd byte" is ac-'
cessed by transposing the high byte of the complete
x16 word onto the 00-07 'outputs. This odd byte
corresponds to data presented on 08-015. pins in
x16 mode.
!'iote that two zones logically adjacent in x16 mode
are multiplexed through 00-07 in ic8 mode and are
toggled by the Ao address. Thus, zone specific
erase operations must be kept discrete in x8 mode
by addressing even byte,S only for one-half of the
zone pair, then addressing odd bytes only for the
other half.

6-110

The flash memory card features three types of write
protection. The first type features a mechanical
Write P~otect Switch that disables the circuitry that
control Write Enable to the flash devices. When the
switch is activated, the WE # internal to the cord is
forced high, which disables any writes to t!:le Command Register. The second type of write protection
is based on lhe' PCMCIAI JEIDA socket. Unique pin
length assignments proVide protective power supply
sequencing during hot insertion and removal. The
third type operates via software .control through the
Command Register when the card resides in its connector. The Command ~egister of each zone is only
active when VPP1;2 is at high voltage. Depending
upon the application, the system designer may
choose to. make VPP1j2 power supply switchableavailable only when writes are desired. When VPP1,t2
= VPPL, the contents of the register default to the
read command, making the iMC002FLKA a readonly memory .card. In this mode, the memory contents cannot be altered.
.
The system designer may choose to leave VPP1,t2 =
VPPH, making the high voltage supply com~tantly
available. In this case, all Command Register functions are inhibited whenever Vee is below the write
lockout voltage, VLKO. (See the section on Power
Up/Down Protection.) TheiMC002FLKAis designed
to accommodate either design practice, and to encourage optimization of the processor-memory card
interface.

intel~
BUS OPERATIONS
Read
The iMC002FLKA has two control functions, both of
which must be logically active, to obtain data at the
outputs. Card Enable (CE #) is the power control
and should be used for high and/or low zone(s) selection. Output Enable (OE#) is the output control
and should be used to gate data from the output
pins, independent of accessed zone selection. In the
byte-wide configuration, only one CE # is required.
The word-wide configuration requires both CE#s active low.
When VPP1;2 is high (VPPH), the read operations can
be used to access zone data and to access data for
write/erase verification. When VPP1;2 is low (Vppd,
only read accesses to the zone data are allowed.

Output Disable
With Output Enable at a logic-high level (VIH), output
from the card is disabled. Output pins are placed in a
high-impedance state.

Standby
With one Card Enable at a logic-high level, the
standby operation disables one-half of the x16 output's read/write buffer. Further, only the zone corresponding to the selected address within the upper or
lower CE1;2# bank is active at a time. (NOTE: Ao
must be low to select the low half of the x16 word
when CE2# = 1 and CE1 # = 0.) All other zones
are deselected, substantially reducing card power
consumption. For deselected banks, the outputs are
placed in a high-impedance state, independent of
the Output Enable signal. If the iMC002FLKA is deselected during erasure, writing, or write/erase verification, the accessed zone draws active current until the operation is terminated.

IMC002FLKA

Intelligent Identifier Command
The manufacturer- and device-codes can be read
via the Command Register, for instances where the
iMC002FLKA is erased and rewritten in a universal
reader/writer. Following a write of 90H to a zone's
Command Register, a read from address location
OOOOOH on any zone outputs the manufacturer code
(89H). A read from address 0002H outputs the memory device code (SOH).

Write
Zone erasure and rewriting are accomplished via the
Command Register, when high voltage is applied to
VpP1;2. The contents of the register serve as input to
that zone's internal state-machine. The state-machine outputs dictate the function of the targeted
zone.
The Command Register itself does not occupy an
addressable memory location. The register is a latch
used to store the command, along with address and
data information needed to execute the command.
The Command Register is written by bringing Write
Enable to a logic-low level (Vld, while Card Enable(s) is/are low. Addresses are latched on the failing edge of Write Enable, while data is latched on
the rising edge of the Write Enable pulse. Standard
microprocessor write timings are used.
Refer to AC Write Charcteristics and the Erase/
Write Waveforms for specific timing parameters.

COMMAND DEFINITIONS
When low voltage is applied to the Vpp pin(s), the
contents of the zone Command· Register(s) default
to OOH, enabling read-only operations.
!:.\
III

Placing high voltage on the Vpp pin(s) enable(s)
read/write operations. Zone operations are selected
by writing specific data patterns into the Command
Register. Tables 3 and 4 define these iMC002FLKA
register commands for both byte-wide and wordwide configurations.
All commands written to the Command Register require that the zone address be valid or the incorrect
zone will receive the command. Any Command/
Data Write or Data Read requires the correct valid
address.

6-111

iMC002FLKA
Table 2~'Bu8 Operations

Vp,p'L VPPL '

\tIL:

'ilH

VIL

VIH

Trj-statlil

Dat~ Out-Even

React (ic8)'

VPPL' VPPL

VIH

VIL

VIL;

VIH

Tri-state

Data Out-Odd

Read(X8)i,

·10

VPPL

VIL

VIH

VIL

VIHDataOut Tri-state,

i:i

Read (x16)

VPPL

VIL

VIH

Output Disable

VPPL

VIH

VIH' Tri-statEiTri-state

Standby

VPPL

VIH

"8ead (xS) , .'

>~--~~~-+~~~~~+-~~~~~~4-~~+-~~~~+-----~--~----~~

Data Out Data Out

~~~~~~-+----~~~+-~~--~--~4-~~+-~~~~+-~--~--~~--~~

X , Tri-state

Tri~state

Read (x8) , "

3, 8

VpPX

VPPH

VIL

VIH

VIL

VIH

Tri-state

Data Out"Even '

Read (x8)

3, 9

VPPH' VpPX

VIH

VIL

VIH

Tri-state

Data Out-Odd

~~R_e_a~d~(x_8~)__-+__1_0-4_V~P~PH~'+-V~PP~X~'~X-+__V~IL~__V~IH~__
V~IL~_V~IH~'~D_a_ta__
O_ut4-T_ri_-s~ta_t_e__~
~ Read (x16)
3, 11 VPPH VpPH X
VIL
"IL
VIL'
VIH Data Out Data Out

~r---~~~~---+-~~~~--+--~-r~~--~~~+--~---+-~----~

Write (x8)

5, 8

VpPX

VPPH

VIL

VIH

VIL

VIH

Write (x8)

VPPH

VpPX

VIH

Write (x8)

, 10 '

'liP-PH

VpPX

Write (x16)

VPPH VPPH

Standby

VPPH

Vp,PH

VPPH

VIL

Tri-state

Data In-Even

VIH

VIL

VIH

VIL

Tri-state

Data In-Odd

VIL

¥IH

VIH

VIL

Data In

Tri-state

VIL

'IIIH

VII~.

VIH

VII-i

Tri-state

VIH

VIL

Tri-state

~~--~~--~----+-~~~~r-~--~~~=-+-~~~~r------+--------~

Output Disable

Data In ,Data, In

NOTES:
,
1. \:Iefer to DC Character:istics. When VPP1j.! = VPPL ~mory contents can be read but not written or erased.
2. Manufacturer arid device codes may be accessed via a command. register write sequence. Fiefer to Table 3. All other
addresses low.
, 3. Read operations with VPP1,.2 = VPPH may ace,ess array data or the Intelligent Identifier codes.
4. With VPP1,.2 at high, voltage, the standby current equals Icc + Ipp (standby).
'
"
5. Refer to Table ~ for valid Data-In during a write operation.
.
'6. X can be VIL or VIH.
7. VpPX = VPPH or VPPL·
S. This xS operation reads or writes the lOw byte of the xi6 word on 000:"7, i.e.; Ao low reads "even" byte in x8 mode.
9. This xS operation reads or writes the high byte of the x16 word on 000-7 (transposed from DOs..: ts), i.e., Ao high reads
"odd" byte in xS ,mode.
10. This xS operalionreadsorwrites,the hlgh,gyte of the xi6 on oo8-,1S. Ao is'''don't care."
11. Ao is "don't care," unused in x16 mode. Higl:t and low bytes are presented simultaneously.

6-11~

intel~

IMC002FLKA

!:,i

Table 3. Command Definitions Byte-Wide Mode
Command

Read Memory
Read Intelligent 10 Codes,

Bus
SeCond Bu. Cycle
First Bus Cycle
Notes Cycles
Req'd Operatlon(1) Address(2) Data(3) Operatlon(1) Address(2) Data(3)

Write

OOH

Write

Set-up Erase/Erase

Write

20H,

Write

20H

Erase Verify

Write

AOH

Read

EVO

Set-up Write/Write

Write

40H

Write

Write Verify.

Write

COH

Read

WVO

2,7,8

Write

FFH

Write

' "lA

FFH

Read

Table 4. Command Definitions Word-Wide Mode
Bus
SeCond Bus Cycle
First Bus Cycle
Notes Cycles
Req'd Operatlon(1) Address(2) Dalai(3) Operatlon(1) Address(2) Data(3)

OOOOH

Write

9090H

Read

Write

2020H

Write

Read Memory .

Write

Read Intelligent 10 Codes

Set-up Erase/Erase

2020H
EVO

Erase Verify

Write

AOAOH

Read

Set-op Write/Write

Write

4040H

Write

' Write

WA.

COCOH

Read

WVO'

2,7,8

Write

FFFFH

Write

FFFFH

Write Verify
Reset
NOTES:

1. Bus operations are defined in Table 2.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during erase verify.
RA ;= Read Address
WA = Address of memory location to be written.
ZA = Address of 256 Kbyte zones involved in erase or Reset operations.
Addresses are latched on the falling edge of the Write Enable pulse.
3. 10
= Data read from location.'IA during device identification. (Mfr = 69H, Device = BDH).
EVD = Data read from location EA during erase verify.
WD = Data to be written at location WA. Data is latched on the rising edge of Write Enable.
WVD= Data read from location WA during write. verify. WA is latched on the Write comma!)d.
4. Following the Read IntelligE!nt 10 cOmmand, two read operations access manufacturer and device codes.
5. Figure 5 illustrates the Erase Algorithm.
6. Figure 6 illustrates the Write Algorithm.
7. The second bus cycle must be followed by the desired command register write.
6. The Reset command operates on a zone basis: To reset the entire card requires reset write cycles to each :one:

Command

,'I

Reset

90HT

6-113

intel®

iMC002F.LKA

Read Command
While VPP1;2 is high, for, erasure and writing, zone
memory contents can be accessed via . the' read
command. The read operation is initi.ated by writing
ooH (OOaOH for the word-wide configuration) into the
zone Command Register(s). Microprocessor read
cycles retrieve zone data. The aocessed zone remains enabled for reads until the Command Register(s) contents are altered.
The default contents of each zone's register(s) upon
VPP1;2 power-up is OOH (OOOOOH for word-wide).
This default value ensures that no' spurious alteration of memory card .contents occurs dl!ring the
VPP1;2 power transition. Where the VPP1;2 supply is
left at VPPH, the memory card powers-up and remains enabled for reads until the command Register
contents of targeted zones are changed. Refer to
the AC Read Characteristics and Waveforms for
specific timing parameters.

Intelligent Identifier Command
E:acti zone of the iMC002FLKA contains an Intelli- '.
gent Identifier to identify memory card device characteristics. The operation is initiated by writing 90H
(9090H for word-wide) into· the Command Registeres) with zone address. Following the command
write, a read cycle from address OOOOOH retrieves
the manufacturer code 89.H (8989H for word-wide).
A read cycle from address 0002H returns the device
code BOH (BOBOH for word-wide). To terminate the
.operation, it is necessary to write another valid command into the register(s).

Set-up Erase/Erase Commands
Set-up Erase stages the targeted zone(s) for electri- ,
cal erasure of all bytes in the 'zone. The set-up erase
operation is performed by writing 20H. to the Command Register (2020H for word-wide) with zone address.
To commence zone-erasure, the erase command
(20Hor 2020H) must again be written to the registeres) with zone address. The erase operation begins
with the rising edge of the Write"Eoablepulse and
terminates with the rising edge ofthe next Write-Enable pulse (Le., Erase-Verify Command with zone
address).
This two-step sequence of set-up followed byexecution ensures that zone memory contents are not accidentally erased. Also, zone-erasure can only occur
when high voltage is applied to the VPP1;2 pins. In
the absence of this high voltage, zone memory con-

6-114

tents are protected against erasure. Refer to AC
Erase Characterstics and Waveforms for specific
timing parameters.

Erase-Verify Command
The erase .command erases all of the bytes of the
zone in paranel. After each erase operation, all bytes
in the zone must be indiVidually verified. In bytemode operations, zones are segregated by' Ao in
odd and even banks; eras~ and erase verifyqperations must be done in complete passes of evenbytes-only then odd-bytes-only. See the Erase Algorithm for byte-wide mode. The erase verify operation
is initiated by writing AOH (AOAOH for word-wide) into
the Command Register(s). The address for the
byte(s) to be verified must be supplied as it is
latched on the falling edge of the Write Enable
pulse. The register write terminates the erase' operation with the rising' edge of its Write Enable pulse.
The enabled zone applies an internally-generated
margirrvoltage to the addressed byte. Reading FFH
from the addressed byte indicates that all bits. in the
byte are erased. Similarly, reading FFFFH from the
addressed word indicates that all bits in the word are
erased.
.
The erase-verify command must· be written to the
Command Register prior to each byte (word) verification to latch its address. The process continues
for each byte (word) in the zone(s) until a byte (word)
does not return FFH (FFFFH) data, or the last address is accessed .
In the case where the data read is not FFH (FFfFH),
another erase operation is performed. (Refer to Setup Erase/Erase.) Verification then resumes from the
address of the last-verified byte (word). Once all
bytes (words) in the zone(s) have been verified, the
erase step is complete. The accessed zone can now
be written. At this. point, the verify operation is terminated.by writing a valid command (e,g., Write Setup) to the Command Register. The Erase algorithms
for byte-wide. and word-Wide configurations illustrate
how commands and bus operations ar'e.combined to
perform electrical erasure of the iMCC002FLKA. Refer to AC Erase Characteristics and. Waveforms for
specific timing parameters.

Set-up Write/Write Commands
Set-up write is a command-only operation that
stages the targeted zone for byte writing. Writing
40H (4040H) into the Command Register(s) performs the set-up operation.

intel®
Once the write set-up operation is performed, the
next Write Enable pulse causes a transition to an
active write operation. Addresses are internally
latched on the falling edge of the Write Enable
pulse. Data is internally latched on the rising edge of
the Write Enable pulse. The rising edge of Write Enable also begins the write operation. The write operation terminates with the next rising edge of Write
Enable, which is used to write the verify command.
Refer to AC Write .Characteristics and Waveforms
for specific timing parameters.

Write Verify Command
The iMC002FLKA is written on a byte-by-byte or
word-by-word basis. Byte or word writing may occur
sequentially or at random. Following each write operation, the byte or word just written must be verified.
The write-verify operation is initiated by writing COH
(COCOH) into the Command Register(s) with correct
address. The register write(s) terminate(s) the write
operation with the rising edge of its Write Enable
pulse. The· write-verify operation stages the accessed zone(s) for verification of the byte or word
last written. The zone(s) apply(ies) an internally-generated margin voltage to the byte or word. A microprocessor read cycle outputs the data. A successful
comparison between the written byte or word and
true data means that the byte or word is successfully
written. The write operation then proceeds to the
next desired byte or word location. The Write algorithms for byte-wide and word-wide configurations illustrate how commands are combined with bus operations to perform byte and word writes. Refer to
AC Write Characteristics and Waveforms for specific
timing parameters.

Reset Command
A reset command is provided as a means to safely
abort the erase- or write-command sequences. Following either set-up command (erase or write) with

iMC002FLKA

EXTENDED ERASE/WRITE CYCLING
Intel has designed extended cycling capability into
its ETOX II flash memory technol9gy enabling a
flash memory card with a MTBF that is many times
more reliable than rotating disk technology. Resulting improvements in cycling reliability come without
increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field minimizes
the probability of oxide defects in the region. The
lower electric field greatly reduces oxide stress and
the probability of failure.

WRITE ALGORITHMS
The write algorithm(s) use write operations of 10 ,""S
duration.. Each operation is followed by a byte or
word verification to determine when the addressed
byte or word has been successfully written. The algorithm(s) allows for up to 25 write operations per
byte or word, although most bytes and words verify
on the first or second operation. The entire sequence of writing and byte/word verification is performed with Vpp at high voltage.

ERASE ALGORITHM
The Erase algorithm(s) yield(s) fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the write
algorithm, to simultaneously remove charge from all
bits in the accessed zone(s).
Erasure begins with a read of memory zone contents. Reading FFH (FFFFH) data from the accessed zone(s) can.be immediately followed by writing to the desired zone(s).

6-115

inteli

iMC002FLKA

For zones. being erased and rewritte,n, uniform and
reliable erasure is ensured by first writing all bits in
the accessed zone· to their charged state {data =
00H byte-wide,OOOOOH word-wide)~ This is accomplished, using the write algorithm, in approximately
four seconds per zone.
EraseexeCiJtic)O .then continues with an initial erase
operation. Erase verification (data = FFH byte-wide,
FFFFH word"wide) begins at address OOOOOH and
continues through the zone to the last address, or
until data other thanFFH (FFFFH) is encountered.

(Note:. byte-wide erase operation. requires separate
even- and odd-address passes to handle the individual 256 Kbyte zones.) With each erase operation, an
incre.asing number of bytes or words verify to. the
erased state. Erase efficiency may. be .improvedby
storing the address of the last byte or word verified
ina register(s). Following the next erase operation,
verification starts at the. stored address location. Follow this procedure until all. bytes in the· zone.are
erased. Then, re-start. the procedure for· the next
zone or word-wide zone pair.· Erasure typically oc·
curs in two seconds per zone.

INITIALIZE SIZE
AND NUMBER Of ZONES
ZONE L= 0
ZONEH=I

290412-3 .

Figure 3. Full Card Erase Flow

6-116

infel~

iMC002FLKA

( START WRITING

Bus

[1]

Operation

APPLY
VpPH (2)

PLSCNT = 0

Command

Standby

Comments

Wait for Vpp ramp
to VPPH (= 12.0V) (2)

Initialize pUlse-count

WRITE SET-UP ;
WRITE CWO + ADDRESS

WRITE
CMD(A/D)

Data = 40H +
Valid Address

Write

Valid address/data

--l.
l
READ DATA
FROM DEVICE

operation (tWHWH1)

Write

Data = COH + Valid Address;
Stops(4) Write Operation

Write(3)
Verify

TlIolE O.UT 6 pS

Duration of Write

Standby

10 pSi

WRITE
VERIFY cwo + ADDRESS

Set-up
Write

LTIME OUT

Write

Standby

tWHGL

Read

Read byte to verify Write
Operation at Valid Address

Standby

Compare data output
to data expected

N
INC
PLSCNT,

VERIFY
DATA

= 251
Y

INCREIolENT
ADDRESS

LAST
ADDRESS

1
Y

WRITE
READ.CMO

APPLY
vPPL[~)

(

Write

I I

l
WRITING
)
COIolPLETED

(

APPLY
VpPL (2)

Read

Standby

Data = OOH, resets the
register for read
.operations.
Wait for VPP ramp
to VPPL(2)

WRITE
ERROR

290412-4

NOTES:
1. CAUTION: The algOrithm MUST BE FoLLOWED to
ensure proper and reliable operation of the device.
2. See DC Characteristics for the value of VPPH and
VPPL·

3. Write Verify is only performed after a byte write operation. A final read/compare may be performed (optional) after the register is written with the Read command.
4. Refer to principles of operation.

Figure 4. Write Algorithm for Byte-Wide Mode

6-117

· IMCOO2FLI(A
..

Bus
Command
Operation

.Comments
Wait for Vp.~ ramp to VPPH
(= 12.0V)< )

Standby

Use with Write Operation
Algorithm
.
Initialize even/Odd Addresses,
Erase Pulse Width, and Pulse
Count

Write

Set-up
Erase

Data = 20H

+ Address

Write

Erase

Data = 20H

+ Address

Standby
Write

Erase
Verify(3)

Addr=Byte to verify;
lYata = AOH; Stops

Standby

Erase Operation(4) tWHGL

Read

Read byte to verify erasure at
address

Standby

Compares output to FFH
increment pulse cqunt

Write
Standby

290412-5
NOTES:
.
1. CAUTION: The algorithm MUST BE.FOLLOWED to
ensure proper and reliable operation of the device.
2. See DC Characteristics for the value of VPPH and
VpPL·

Duratipn of Erase operation
(tWHWH2)

Read

Data = OOH, resets the register
for read operations.
Wait for Vppramp to VPPL(2)

3. Erase Verify is only performed afler a chip erasure. A
final read/coinpare may be performed (optional) after
the register is written with the Read command.
4. Refer to principles of operation.

Figure 5. Erase Algorithm for Byte-Wide Mode

6-118

IMC002FLKA

Comments

Walt for Vpp ramp to VPPH
ADRS = addre•• to write
W_DAT = data word to write
Initialize Data Word Variables:
V_OAT = valid data
W_COM = Write Command
V_COM = Wr~e Verify Command
PLSCNT--HI = HI Byte Pulse Counter
PLSCNT_LO = LO Byte Pulse Counter
FLAG = Write Error Flag
Write Set-up Command
Address nead. to be Valid
Write

PLSCNT _HI = 0
PLSCNLLO=O
FLAG = 0

High/Low Byte
Compare &: Mask
Subroutine

See Write Verify and Ma.k Subroutine
Write Verify Command

F_OAT = flash memory data

Compare flash memory data to valid data
(word compare). If not equal, check for
Write Error flag; If Flag not .et, compare
High and Lo,,! Byte. in the Subroutine.

Check buffer of 110 port for more data to write

Reset device for read operation
Turn offVpp

290412-6

Figure 6. Write Algorithm for Word·Wlde Mode

6-119

IMC002FLKA

COlT!ments
To look at the LO Byte,
Mask· the HI Byte with
00
LDAl,;, (LDAl OR OOFFH)
ILcoM = (W_COM OR OOFFH)
V_COM = (V _COM OR OOF'F'H)

Ifthe LO Byte verifies,
mask the LO Byte
commands. with the reset
command (FFH)
If the LO Byte does not
verify, then increment its
puise counter and check
for max count
'
, FLAG = .1 denotes a LO
Byte error
, Repeat the sequence for
the HI Byte

LDAT = ('LOAT OR FFOOH)
W_COM = (W _COM OR FFOOH)
V_COM = (LCOM OR FFOOH)

FLAG = 2 denotes a HI
Byte error
FLAG = 3 denotes both
a HI and LO Byte errors.
Flag = 0 denotes no
max count errors;
continue with algorithm.

290412-7

"Masking can easily and efficiently be done in assembly languages. Simply load word registers with the incoming data
(F_DAn. the program commands and the verify commands. Then manipulate the HI or LOregister contents.

Figure 7. Write Verify and Mask Subroutine fen Word-Wide Mode

IMCOO2F.LKA

Commanta

Wait for Vpp to stabilize.

;~
',~

Use Write operation algorithm in x8 or x16

oonflguraiton

INITIALIZE:
PLSCNT _HI 0
PLSCNLLO=O
ADRS = 0

Inllializa Variables:
PLSCNT-HI = HI Byte Pulse Counter
.PLSCNT-1.0 - LO Byte Pulse Counter
FLAG = Erasure error flag
AORS = Address
LCOM = Erase Commend
V_cOM = Verify Command

fLAG = 0
LCOM=2020H
V ~COM = AOAOH

I
I
I

I.. ~

Erase Set-up Command

S1art Erasing

Duration of Erase Operatiorl

Erase Verify Command slops erasure

See Block Eraee Verify & Mask Subroutine

When both devices at ADRS are eraeed. F_
DATA = FFFFH. If not equal. incrementlhe
,pulse counter and check for last pulse
Reset oommands delaun 10
(LCOM = 2020H) (V_COM
bsfore verifying ~xt ADRS

= AOAOH)

Reset device for read operation
I'

Tum ofIVpp
'.

290412-8

NOTE:
X16 Addressing uses Al-A20 only.

= 0 throughout word~wide operation.

Figure 8. Erase Algorithm for Word-Wide Mode

6-121

tMC002FLKA,

This s,l,Ibro~tine read,s the data
.word (F_D.a;TA). It then masks
the HI or LO Byte of the Erase
,andVerify commands from
executing during the next
operatiQn.
",
If both HI and'LO Bytes verify,
then return. '
Mask' the HI Byte with OOH.

LeoM" (LCOM or OOffH
V_COM- IV_COM or OOrrH)

If the LO Byte verifies erasure,
then mask" the next erase and
verify commands with ,FFH
(RESET).
If the LO Byte does not verify,
. then increment its pulse counter
and check for max count. FLAG
= 1 denotes a LO Byte error.

Repeat the sequence for the HI
Byte.
LCOM
V_COM

=(LCOM or FFOOH)
=(V _COM or rfOOH)
Flag =2 dEmotes a HI Byte error.
Flag = 3 denotes both a HI and
LO Byte errors. FLAG = 0
denotes no max count errors;
continue with algorithm.

290412-9

'Masking can easily and effiCiently be done in assembly languages. Simply load word registers with the incoming data
(F..,.DAT), the program commands and the verify commands. ·Then manipulate the HI or LO register contents.

Figure 9. Eras.e Verify and Mask Subroutine ·for Word-Wide Mode

iMC002FLKA

SYSTEM DESIGN CONSIDERATIONS
Three-Line Control
Three-line control provides for:
a. the lowest possible power dissipation and.
b. complete assurance that output bus contention
will not occur.
To efficiently use these three control inputs, an address-decoder output should drive CE1 2#, while
the system's Read signal controls the card OE # signal, and other parallel zones. This, coupled with the
internal zone decoder, assures that only enabled
memory zones have active outputs, while deselected zones maintain the low power standby condition.

Power-Supply Decoupling
Flash memory power-switching chara~teristics require careful device decoupling. System designers
are interested in three supply current issues-standby, active and transient current peaks, produced by
falling and rising edges of CE 1;2 #. The capacitive
and inductive loads on th!'l card and internal flash
memory zones determine the magnitudes of these
peaks.
Three-line control and proper decoupling capacitor
selection will suppress transient voltage peaks. The
iMC002FLKA features on-card ceramic decoupling
capacitors connected between Vee and Vss, and
between VPP1IVPP2 and Vss.

The card connector should also have a 4.7 ,iF electrolytic capacitor between Vee and Vss" as well as
between VPP1IVPP2 and Vss. The bulk capacitors
will overcome voltage slumps caused by printed-circuit-board trace inductance, and will supply charge
to the smaller capacitors as needed.

Power Up/Down Protection
The PCMCIAlJEIDA socket is specified, via unique
Pin lengths, to properly sequence the power supplies to the flash memory card. This assures that hot
insertion and removal will not result in card damage
or data loss.,
Each zone in the iMC002FLKA is designed to offer
protection against accidental erasure or writing,
caused by spurious system-level signals that may
exist during power transitions. The card will powerup into the read, state.
A system designer must guard against active writes
for Vee voltages above VLKO when Vpp is active.
Since both WE# and CE1 2# must be low for a
command write, driving either to VIH will inhibit
writes. With its control register architecture, alteration of zone contents only occurs after successful
completion of the two-step command sequences.
While these precautions are sufficient for most applications, it is recommended that Vee reach its steady
state value before raising VPP1;2 above Vee + 2.0V.
In addition, upon powering-down, VPP1;2 should be
below Vee, + 2.0V, before lowering Vee.

6-123

IMC002FLKA

Absolute Maximum Ratings· .

NOTICE:.This is a production data sheet. The specifications are subject to change without notice.

Operating Temperature
During Read ...... , ............ O"C to + SO·C(l)
During Erase/Write .............. O·C to + SO·C
Temperature Under Bias .. , ...... '- 10·C to

+ 70"C

Storage Temperature ............ -30·C to +70·C
Voltage on Any Pin with
Respect to Ground .......... - 2.0V to + 7.0V(2)
VPP1/VPP2 Supply Voltage with
Respect to Ground
During Erase/Write ....... - 2.0V to

• WARNING; Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is riot recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

+ 14.0V(2,3)

Vee Supply Voltage with
Respect to Ground .......... - 2.0V to + 7.0V(2)
.
NOTES:
1. Operating temperature is. for commercial product defined by this specification.
2. Minimum DC input voltage is -O.5V. During transitions, inputs may undershoot to - 2.0V for periods less
than 20 ns. Maximum DC voltage on output pins is Vee + 0.5V, which may overshoot to Vee + 2.0V for
periods less than 20 ns.
3. Maximum DC input voltage on VPP1/VPP2 may overshoot to + 14.0V for periods less than 20 ns.
I

OPERATING CONDITIONS
Symbol
TA
Vee

Parameter

Min

Operating Temperature

. Vee Supply Voltage

limits .....
Max

Unit

Comments

·C

For Read-Only and
Read/Write Operations.

4.75

5.25

V
V
V

VPPH

.Active VPP1, VPP2
Supply Voltages

11.40

12.S0

VPPL

Vpp During Read Only
Operations

0.00

S.50

DC CHARACTERISTICS-Byte Wide Mode
Symbol
III

Parameter
. Input Leakage Current

Notes

limits
Min

Unit

Test Conditions

Typical

Max

1,4

±1.0

±20

jJ.A

Vee = Veernax
VIN = VeeorVss

ILO

Output Leakage Current

±1.0

±20

jJ.A

Vee'; Vee max
Your = Vee or Vss

lees

Vee Standby Current

0.4

0.8

Vee = Vee max
CE1# = CE2# = Vee±0.2V

Vee = Vee max
CEl # = CE2# = VIH

leel

Vee Active Read Current

1,2

Vee = Vee max CE# = VIL
f = SMHz,lour= 0 mA

lee2

Vee Write Current

1,2

.5.0

15.0

Writing in Progress

lee3

Vee Erase Current

1,2

10.0

20.0

Erasure in Progress

lee4

Vee Write Verify Current

1,2

10.0

20.0

Vpp = VpPH
Write Verify in Progress

S-.124

iMC002FLKA

DC CHARACTERISTICS-Byte Wide Mode (Continued)
Symbol

Parameter

Limits

Notes
Min

.lee5

Vee Erase Verify Current

1.2

Unit

Test Conditions

Typical

Max

10.0

20.0

rnA

VPP = VpPH
Erase Verify in Progress

±SO

p.A

Vpp

O.S

rnA

Vpp> Vee

Ipps

VPP Leakage Current

IpPl

Vpp Read Current
or Standby Current

1.3

IpP2

Vpp Write Current

1.3

S.O

rnA

Vpp = VPPH
Write in Progress

IpP3

VPP Erase Current

1.3

Vpp = VPPH
Erasure in Progress

IpP4

Vpp Write Verify Current

1.3

2.0

5.0

VPP = VPPH
Write Verify in Progress

IpP5

VPP Erase Verify Current

1.3

2.0

5.0

rnA

Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

O.S

VIH

Input High Voltage

2.4

Vee ± 0.3

VOL

Output Low Voltage

0.40

IOL = 3.2mA
Vee = Vee min

VOHl

Output High Voltage

3.S

IOH = -2.0 mA
Vee = Vee min

VpPL

Vpp During Read-Only
Operations

0.00

6.5

Note: Erase/Write are
Inhibited when VPP = VPPL

VPPH

VPP During Read/Write
Operations

11.40

12.60

VLKO

Vee Erase/Write Lock
Voltage

2.5

0.4

±O.OS

Vpp

Vee
Vee

NOTES:

1.
2.
3.
4.

AII.currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V. Vpp = 12.0V. T = 25'e.
1 chip active and 7 in standby for byte-wide mode.
Assumes 1 Vpp is active.
Due to 100 k!l pull up resistors OE#. eEl #, eE2# and WEll' will exhibit :S: 55 /LA of additionallu when VIN

Vss.

DC CHARACTERISTICS-Word Wide Mode
SYrnbol

Parameter

Notes

Limits

Unit

Test Conditions

Typical

Max

1.4

±1.0

±20

p.A

Vee = Vee max
VIN = Vee or VSS

Min

III

Input Leakage Current

ILO

Output Leakage Current

±1.0

±20

p.A

Vee = Vee max
VOUT = Vee or VSS

Vee Standby Current

0.4

O.S

Vee = Vee max
CEl # = CE2# = Vee ± 0.2V

Vee = Vee max
CEl # = CE2# = VIH

.Ices

6-125

...+~.
•-n'"
"'Ere

'IMCOO2FLKA

DC CHARACTERISTICS-Word Wide Mode (Continued)
Symbol
leel

Parameter

Notes

Vee,Active Reac:iCurrent

Limits

Test Conditions"

Max

1,2'

80,

mA Vee = VeemaxCE# = VIL
f = 6 MHz, lOUT =0 mA

Unit

Typical

Min

lee2

Vee Write Current

1,2

7.0

mA Writing in Progr~

Iccs

Vee Era,e Current

1,2

30 '

mA Erasure in Progress

ICC4

Vee Wr;ite Verify Current

1; 2

mA Vpp == VPPH
Write Verify in Progress

ICC5

Vee Erase VerifY Current

Ipps

Vpp Leakage Current

IpPl

Vpp Read Current

1,2

mA VPP = VPPH
erase Verify in Progress

±80

p.A VppS: Vee

1.6

mA Vpp> Vee

1,3

0.7

IpP2

Vpp Write Currem
(,,'

1,3

Vpp = VPPH
Write in Progress

Ipps

Vpp Erase Current

1,3.

Vpp = VpPH
Er8$ure in Progress

IpP4

Vpp Write Verify Current

1,3

5.0

mA VPP = VPPH
Write Verify in Progress

IpP5

VPP Erase Verify Current

1,3

,5.0

mA VPP = V;PPH
Er~e Verify in Progress

Vil

Input Low Voltage

-0.5

0.8

VIH

Input High Voltage

2.4

Vee.± 0.3.

VOL

Output Low Voltage

0.40

10l = 3.2mA
Vee = Vee min

VOHl

Output High Voltage

3.8

10H = - 2.0 inA
Vee = Vcc min

VPPl

VPP During Read·Only
Operations

0.00

8.5
,

NQte: Erase/Write are
Inhibited when VPP = VPPl

VPPH

' VPP During Read/Write
Operations

11.40

12.60

VlKO

Vee Erase/Write Lock
,Voltage

2.5

±0.16

or Standby Current

NOTES:.

. '

VPP

Vee

1. All currents are in RMS unless otherwise noted. Typi~ values at Vcc'= 5.0V. Vpp = 12.0V. T = 25°C.
2. 2 chips active and 6 in standby for word-wide mode.
S. Alisumes2 Vpps are active.
'
4. Due to 100 kG pun up resistors 01;:#. CEl #. CE2# and WE# will exhibit s: 55 ""A of additionallu when VIN = Vss.

6·128

intet~

IMC002FLKA

CAPACITANCE T = 2S0C, f = 1.0 MHz
Parameter

Symbol

Notes

Limits
Min

Max

Unit

Conditions

CIN1

Address Capacitance

VIN = OV

CIN2

Control Capacitance

VIN = OV

COUT

Output Capacitance

VOUT = OV

CliO

1/0 Capacitance

VIIO = OV

AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ................. VOL and VOH1
Input Timing Reference Level .......... VIL and VIH
Output Timing Reference Level ........ VIL and VIH

AC CHARACTERISTIC8-Read-Only Operations
Symbol

Characteristic

Notes

Min
200

tAVAV/tRC

Read Cycle Time

tELQV/tcE

Chip Enable Access Time

Max

Unit
ns

200

tAVQV/tACC

Address Access Time

200

ns.

tGLQV/toE

Output Enable Access Time

100

. ns

tELQX/tLZ

Chip Enable to Output
in LowZ

·2

tEHQZ

Chip Disable to Output
in HighZ

tGLQX/toLZ

Output Enable to Output
in LowZ

tGHQZ/tDF

Output Disable to Output
in HighZ

toH

Output Hold from Address,
CE;II, or OE;II Change

twHGL

Write Recovery Time
before Read

..,

ns
ns

S
60

1,2

,...s

I:
;

NOTES:
1. Whichever occurs first.
2. Rise/Fall Time S; 10 ns.

I
!

6-127

IMCOO2FLKA

Vee POWER-Upl

DEVICE AND

STANDBY

ADDRESS SELECTION

ADDRESSES

OUTPUTS ENABLED

AD~RESS

,STAND8Y/ '
, Vee POWER-DOWN

DATA VALID

STABLE

!-------------tAVAv (Ioc) --"'-....,..~-------.J
r-------~~

~--~--~

CEO (EO)

OEO (Go)

IwHGL+-----i
WEO (W.)

VALID OUTPUT

OATA (00)

IoiIGH Z

I - - - -..VQV (tACe ) - - - - - I
!5.DV

V~~ J

290412-10

NOTE:
CE#refers

to CE1,

2#.

Figure 10. ~C Waveforms for ~ead Operations

6·128

iMC002FLKA

AC CHARACTERISTICS-For Write/Erase Operations
Symbol

Characteristic

Max

Unit

Notes

Min

Write Cycle Time

1,2

200

tAVWL/tAS

Address Set-up Time

1,2

tWLAX/tAH

Address Hold Time

1,2

100

tOVWH/tOS

Data Set-up Time

1,2

tAVAV/tWC

tWHOX/tOH

Data Hold Time

1,2

tWHGL.

Write Recovery Time before Read

1,2

J.ts

tGHWL

Read Recovery Time before Write

1,2

J.ts

twLOz

Output High-Z from Write Enable

1,2

tWHOZ

Output Low-Z from Write Enable

1,2

tELWL/tCS

Chip Enable Set-up Time before Write

1,2

tWHEH/tCH

Chip Enable Hold Time

1,2

tWLWH/tWP

Write Pulse Width

1,2

100

tWHWL/tWPH

Write· Pulse Width High

1,2

tWHwH1

Duration of Write Operation

1,2,3

J.ts

tWHWH2

Duration of Erase Operation

1,2,3

9.5

tVPEL

Vpp Set-up Time
to Chip Enable Low

1,2

100

ms
ns

NOTES:

1. Read timing parameters during read/write operations are the same as during read-only operations. Ref;r to A.C. Characteristics for Read-Only Operations.
2. Rise/Fall time,:; 10 ns.
3. The integrated stop timer terminates the write/erase operations, thereby eliminating the need for a maximum specifiction.

ERASE/WRITE PERFORMANCE
Typ

Max·

Unit

2.0

sec

1,2,4

4.0

sec

106

Parameter

Notes

Zone Erase Time

1,3,4

Zone Write Time
MTBF

Min

Hrs

NOTES:

1. 25'C, 12.0VVpp.
2. Minimum byte writing time excluding system overhead is 16 p.s (10 p's program + 6 !'is write recovery). while maximum is
400 p.s/byte (16 P.s x 25 loops allowed by algorithm). Max chip write time is specified lower than the worst case allowed by
the write algorithm since most bytes write significantly faster than the worst case byte.
3. Excludes OOH writing Prior to Erasure.
4. One zone equals 256 Kbytes.
5. MTBF - Mean Time between Failure, 50% failure point for disk drives.

6-129

IMC002FLKA

Vee POWER-UP
STANDBY

SET-UP WRITE

COtolMAND

WRITE COloitAANO
LATCH' ADDRESS a: DATA

WRITE
VERIFY
WRITING

COMMAND

WRITE
VERIFICATION

STANDBY /
Vee' POWER-DOWN

ADDRESSES

CE# ([#)

0[# (G#)

DATA (00)

s.ov
Vee

290412-11

NOTE:
GE# refers to GE1, 2#'

Figure 11. AC Waveforms for Write Operations

6-130

IMC002FLKA

Vee POWER-UP &:

SET-UP [RASE

STANDBY

COIoCWAND

ERASE COWWAND

ERASING

ERA.SE
VER1F'Y
COWMAND

[RASE

VERIFICATION

STANDBY /
Vee POWER-DOWN

ADDRESSES

CE# (E#)

,:j
'[I

Il
I~

WE# (W#)

DATA (DO)

s.ov
Vee
OV
t VPEL
12.0V

Vpp
VpPL

290412-12

NOTE:
CE# refers to CE1. 2#.

Figure 12. AC Waveforms for Erase Operations

6-131

ALTERNATIVE CE#-CONTROLLED WRITES
,
, ',,'
Characterls~lc '
Symbol
Notes
'\

'tAVAV
\

tAVEL

Write'byCie Time

"','

A~re$~set,u~ Time',

" ,\

tELAX

Min

Address Hold Time

, tOVEH

Data Set-up Time

tEHOX

Data Hold Time '"

"
"

Max

Unit

,~oo

too

80_

tEHGl.

Write Recovery Time before Read

6, '

'tGHEL

Read Recovery Time before Write,

,...S
,...S

tWLEL

Write Enable Set-Up Time
before Chip-Enable

tEHWH

Write Enable Hold Time

tELEH

Write Pulse Width

100

ns
ns
ns

tEHEL

Write Pulse Width High

,20.

tpEL

Vpp Set-up Time
to Chip Enable Low

100

NOTES:
, ,
,,'"
"
1. Chip Enable COntrolled Writes: Write operations are driven by the valid combination of Chip Enable and Write Enable. In
systems where Chip Enable defines the write pulse width (with a longer Write Enable timing waveform) all set-I,IP. hold and
inactive Write Enable times should be measured relative to the Chip Enable waveform.

6-132

IMC002FLKA

PROGRAt.!

Vee POWER-UP

STANDBY

SET-UP PROGR.N
COWIoiAND

PROGRAM COMMAND
LATCH A.DDRESS II: DATA

VERIFY
PROGRAW",UNG

COMMAND

PROGRAM
VERIFICATION

STANDBY/

Vee POWER-DOWN

ADDRESSES

1=-+--~f ~H'H~H

DATA (DO)

HIGH Z

s.ov
Vee

ov
12.011
Vpp

. .tt

VPEL

~
290412-13

NOTE:
CE# refers to CE1, 2#.

Figure 13. Alternate AC Waveforms for Write Operations

6-133

iMC002FLKA

ORDERING INFORMATION
M

I '~:'"'"

IDENTIFIER
A = REVISION
K = WORD..,WIDE
ARCHITECTURE
FL= FLASH
002 = 2 MEGABYTE
DENSITY IN MEGABYTES
MC = MEMORY CARD
i = INTEL
PACKAGE PLACEHOLDER

290412-14

ADDITIONAL INFORMATION

ORDER NUMBER

ER-20, "ETOXTM II Flash Memory Technology"
RR-BO, "ETOXTM II Flash Memory Reliability Data Summary"
AP-343, "Solutions for High Density Applications using Flash Memory"

294005
293002
292079

REVISION HISTORY
Description

Number
-002

Removed Preliminary
Removed ExCA Compliance Section
Clarified need for Valid Address during commands
Corrected Vpp = VPPH in Erase Algorithm
Increased ICC2-lcC5 D.C. current specs for both Byte Wide and Word Wide modes
Revised and Updated Application Section discussion
Changed order number

-003

- Change Signal with Bar to #
- Changed TIC Values

iMC001FLKA
1·MBYTE FLASH MEMORY CARD
Nonvolatillty (Zero Retention
• Inherent
Power)
- No Batteries Required for Back-Up
Read
• -High-Performance
200 ns Maximum Access Time
Low Power Consumption
• -CMOS
25 mA Typical Active Current (X8)
- 400 p.A Typical Standby Current
Electrical Zone-Erase
• .-Flash1 Second
Typical per

•

128 Kbyte Zone
-Multiple Zone Erase> 128 KB/s
Random Writes to Erased Zones
-.- 10 p.s Typical Byte Write

Protect Switch to Prevent
• Write
Accidental Data Loss
Register Architecture for
• Command
Mlcroprocessor/Mlcrocontroller
Compatible Write Interface
II Flash Memory Technology
• -ETOXTM
5V Read, 12V Erase/Write

•
•

- High-Volume Manufacturing
Experience
PCMCIAlJEIDA 68-Pin Standard
- Byte- or Word-Wide Selectable
Independent Software & Ha.rdware
Vendor Support
-Integrated System Solution Using
Flash Filing Systems ,

Intel's iMC001 FLKA Flash Memory Card is the removable solution for storing and transporting important user
data and application code. The combination of rewritability and nonvolatility make the Intel Flash Memory Card
ideal for. data acquisition and updatable firmware applications. Designing with Intel's Flash Memory Card
enables OEM system manufacturers to produce portable and dedicated function systems that are higher
performance, more rugged, and consume less power.

I'
I
I;

The iMC001 FLKA conforms to the PCMCIA 1.0 international standard, providing compatibility at the hardware
and data interchange level. OEMs may opt to write the Card Information Structure (CIS) at the memory card's
address OOOOOH with a format utility. This information provides data interchange functional compatibility. The
<200 ns access time allows for "execute-in-place" capability, for popular low-power microprocessors. Intel's
1-Mbyte Flash Memory Card operates in a byte-wide and word-wide configuration providing performance/pow'er options for different systems.
Intel's Flash Memory card employs Intel's ETOXTM II Flash Memories. Filing systems, such as Microsoft's·
flash File System (FFS), facilitate data file storage and card erasure using a purely nonvolatile medium in
the DOS environment. Flash filing systems, coupled with the Intel Flash Memory Card,· effectively create an
all-silicon nonvolatile read/write random access memory system that is more reliable and higher performance
than disk-based memory systems.

·Microsoft is a trademark of Microsoft Corp.
October 1983
Order Number: 290398-004

6-135

I
I
I

IMC()01 FLKA,

r-t

/':'

3.3* 0;1 inin

I
I
I,
I
I
I

I
I
I
I,

.~
N

...

1~',

:Ii'"

.,,-

I
34.

..1-'-'

FRONT SIDE

t:J~.U·
68 •

BACK SIDE

. 35_

, 290399-1

1
2
3
4
5
6

7
8
9

10
11
12
13
14
15
16
17

GNO
03
04
05
06
07
CE1#
A10
OE#
A11
A9
Ae
A13,
A14
IWE#
NC,
Vee

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

' VPP1
A16
At5
A12
A7
~

A5
~

Aa
A2
A1

Do
01
02

GNO

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

GNO
C01#
011
012
013
014
015
CE2#
NC
NC
NC
A'7,
A1e
A19
NC
NC
Vee

52
53

VPP2
NC
54 NO
55 NC
66 NC
57 NC
58 NC
59 NC
60 NC
61 REG#1
62 BV02#2
63 BV01#2
64 , De
65 09
66 010
67 . C02*
68 GNO

NOTES:
'
1. REG# = register memory Select :, No Connect (NC), unused. When REG.# is brought low, PCMCIAlJEIOA stim,dard card infOrmation structure 'data is expected. This is accomplished by formatting the card with this data.
2. BVO# =' battery detect voltage = Pulled high through pull-up resistor.

Figure 1. IMC001FLKA Pin Configuration

6'136

intel®

iMC001FLKA

Table 1. Pin Description
Symbol

Type

Name and. Function

Ao-A19

I·

00- 0 15

1/0

CE1#,CE2#

CARD ENABLE: Activates the card's high and low byte control logic, input
buffers, zone decoders, and associated memory devices. CE # is active low;
CE# high deselects the memory card and reduces power consumption to
standby levels.

OE#

OUTPUT ENABLE: Gates the cards output through the data buffers during a
read cycle. OE# is active low.

WE#

WRITE ENABLE controls writes to the control register and the array. Write
enable is active low. Addresses are latched on the falling edge and data is
latched on the rising edlle of the WE # pulse.
NOTE: With Vpps 6.SV, memory contents cannot be altered.

ADDRESS INPUTS for memory locations. Addresses are internally latched
during a write cycle.

ERASE/WRITE POWER SUPPLY for writing the command register, erasing
the entire array, or writing bytes in the array.

VPP1, VPP2
Vee

DEVICE POWER SUPPLY (SV ±S%).

GNO

GROUND

= ground.
= active high.

C01#,CO#2

CARD DETECT: The card is.detected when C01 # and CO#2

WRITE PROTECT: All write operations are disabled with WP

NC
BV01#,BV02#

NO INTERNAL CONNECTION to device. Pin may be driven or left floating.

BATTERY VOLTAGE DETECT: Not Required.

6-137

INlCOO1F.LKA

08 -0,5 '

00-0,5
...::.-..:.;:..

I/o TRANS~

Oo-~

CEIVERS
AND
aUFFERS

WE" ,

.2¥!-

OE#

I, '

"
,,'

"
"',

'"",

Vce,

~,
"

An
A, -A,g
CE2 #
CE, #

(

\.. WRITE PROTECT
SWITCH
\
Ao-A,,&
ADDRESS
BUFFERS
AND
DECODERS

CEHo #-CEH3 #
CELo # -eEl3 #
I

28F'010
~

REG#

Co, #

:;:q
'-

WE#

~ Ao-A,s

CE#

,,'

CE#'

I- WE#

Ao-A,s 08 -0,5
~

CE#

OE#
Vss Vee VpP2

WE#

OE#
Vss Vee Vpp ,

••

•

I' 1 1

Do-~' I-

~ Ao-A,s

WE#

Da-0,5

OE#
Vss Vec , VpP2

Vss Vee Vpp ,

BDV #

I- OE#

CARD DETECT

BDV,#

Do-~

Ao-A,s

I- CE#

28F'010

•
••

Vee
BATTERY VOLTAGE
DETECT

GND
Vee
V

v
290399-2

Figure 2.IMC001FLKA Block Diagram

iMC001FLKA

APPLICATIONS
The iMC001 FLKA Flash Memory Card allows for the
storage of data and application programs on a purely solid-state removable medium. System resident
flash filing systems, such as Microsoft's Flash File
System, allow Intel's ETOX II highly reliable Flash
Memory Card to effectively function as a physical
disk drive.
User application software stored on the flash memory card substantially reduces the slow disk-DRAM
download process. Replacing the disk results in a
dramatic enhancement of read performance and
substantial reduction of active power consumption,
size, and weight-considerations particularly important in portables and dedicated systems. The
iMC001 FLKA's high performance read access time
and command register microprocessor write interface allows for use of the flash memory system in an
"execute-in-place" architecture. This configuration
eliminates the need for the redundancy associated
with DRAM and Disk memory system architectures.
ROM based operating systems, such as Microsoft's
MS-DOl5 ROM Version allow for "instant-on" capability. This enables the deSign of systems that boot,
operate, store· data files, and execute application
code from/to purely nonvoh~tile memory.
The PCMCIAlJEIDA 68-pin interface enables the
end-user to transport data and application code between portables and host systems. Intel Flash Memory Cards provide durable nonvolatile memory storage protecting valuable user code and data.
For systems currently using a static RAM/battery
configuration
for
data
acquisition,
the
iMC001 FLKA's inherent nonvolatility eliminates the
need for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable computers and medical instruments,
both
requiring
continuous
operation.
The

iMC001 FLKA consumes no power when the system
is off. In addition, the iMC001 FLKA offers a considerable cost and density advantage over memory
cards based on static RAM with battery backup.
The flash memory card's electrical zone-erasure,
byte writability, and complete nonvolatility fit well
with data accumulation and recording needs. Electrical zone-erasure gives the deSigner the flexibility to
selectively rewrite zones of data while saving other
zones for infrequently updated look-up tables, for
example.

PRINCIPLES OF OPERATION
Intel's Flash Memory Card combines the functionality of two mainstream memory technologies: the rewritability of RAM and the nonvolatility of EPROM.
The flash memory card consists of an array of individual memory devices, each of which defines a
physical zone. The iMC001 FLKA's memory devices
erase as individual blocks, equivalent in size to the
128 Kbyte zone. Multiple zones can be erased
simultaneously provided sufficient current for the appropriate number of zones (memory devices). Note,
multiple zone erasure requires higher current from
both the Vpp and Vee power supplies. Erased zones
can then be written in bit- or byte-at-a-time fashion
and read randomly like RAM. Bit level write capability also supports disk emulation.
In the absence of high voltage on the VPP1/2 pins,
the iMC001 FLKA remains in the read-only mode.
Manipulation of the external memory card-control
pins yields the standard read, standby, and output
disable operations.
The same read, standby, and output disable operations are available when high voltage is applied to
the VpP1/2 pins. In addition; high voltage on VPP1/2

6-139

iMC001FLKA

enables erasure and rewriting of the accessed
zone(s). All functions associated with altering zone
contents-erase, erase verify, write, and write verify-are accessed via the command register.
Commands are written to the internal memory register(s), decoded by zone size, using standard microprocessor write timings. Register contents for a given zone serve as. input to that zone's internal statemachine which -controls the erase and rewrite circuitry. Write cycles also internally latch addresses and
data needed for write and erase operations. With the
appropriate command written to the register(s), standard microprocessor read timings output zone data,
or output data for erase and write verification.

Byte-Wide or Word-Wide Selection
The flash memory card can be read, erased, and
written in a byte-wide or word-wide mode. In the
word-wide configuration VPP1 and/or CE1 # control
the LO-Byte while VPP2 and CE2# control the HIByte (Ao = don't care).
Read, Write, and Verify operations are byte- or wordoriented, thus zone independent. Erase Setup and
Begin Erase Commands are zone dependent such
that commands written to any address within a 128
Kbyte zone boundary initiate the erase operation in
that zone (or two 128 Kbyte zones under word-wide
operation).
Conventional x8 operation uses CE1 # active-low,
with CE2 # high, to read or write data through the
00-07 only. "Even bytes" are accessed when Ao is
low, corresponding to the low byte of the complete
x16 word. When Ao is high, the "odd byte" is accessed by transposing the high byte of the complete
x16 word onto the 00-07 outputs. This odd byte
corresponds to data presented on 08-015 pins in
x16 mode.
Note that two zones logically adjacent in x16 mode
are multiplexed through 00-07 in x8 mode and are
toggled by the Ao address. Thus, zone specific
erase operations must be kept discrete in x8 mode
by addressing even bytes only for one-half of the
zone pair, then addressing odd bytes only for the
other half.

Card Detection

the card is properly loaded. Notethat the two.pios
are located at opposite ends of the card. Each CD #
output should be read through a port bit Should only
one of the two bits show the card to be present, then
the system should instruct the user to re-insert the
card squarely into the socket. Card detection can
also tell the system whether or not to redirect drives
in the case of system booting. CD112 # is active low,
internally tied to ground.

Write Protection
The flash rnemory card features three types of write
protection. The first type features a mechanical
Write Protect Switch that disables the circuitry that
control Write Enable to the flash devices. When the
switch is activated, the WE # internal to the card is
forced high, which disables any writes to the Command Register. The second type of write protection
is based on the PCMCIAI JEIDA socket. Unique pin
length assignments provide protective power supply
sequencing during hot insertion and removal. The
third type operates via software control through the
Command Register when the card resides in its connector. The Command Register of each zone. is only
active when VPP1I2 is at high voltage. Depending
upon the application, the system designer may
choose to make VPP1/2 power supply switchableavailable only when writes are desired. When
VPP1/2 = VPPL, the contents olthe.register default
to the. read command, making the iMC001 FLKA a
read-only memory card. In this mode, the memory
contents cannot be altered.
The system designer may choose to leave VPP1I2 =
VpPH, making the high voltage supply constantly
available. In this case, all Command Register functions are inhibited whenever Vee is below the write
lockout voltage, VLKO. (See the section on Power
Up/Down Protection.) The iMC001 FLKAis designed
to accommodate either design practice, and to encourage optimization of the processor-memory card
interface.

BUS OPERATIONS
Read
The iMC001 FLKA has two control functions, both of
which must be logically active, to obtain data at the

The flash memory card features two card detect pins
(CD1/2#) that allow the host system to determine if

6-140

IMC001FLKA
outputs. Card Enable (CE #) is the power control
and should be used for high and/or lowzone(s) selection. Output Enable (OE #) is the output control
and should be used to gate data from the output
pins, independent of accessed zone selection. In the
byte-wide configuration, only one CE# is required.
The word-wide configuration requires both CE # S active low.
When VPP1/2 is high (VPPH), the. read operations
can be used to access zone data and to access data
for write/erase verification. When VPP1/2 is low
(VppLl, only read accesses to the zone data are allowed.

Output Disable
With Output Enable at a logic-high level (VIH), output
, from the card is disabled. Output pins are placed in a
high-impedance state.

Standby
With one Card Enable at a logic-high level, the
standby operation disables one-half of the x16 output's read/write buffer. Further, only the zone corresponding to the selected address within the upper or
lower CE1,2# bank is active at a time. (NOTE: Ao
must be low to select the low half of the x16 word
when CE2# = 1 and CE1 # = 0.) All other zones
are deselected, substantially reducing card power
consumption. For deselected banks, the outputs are
placed in a high-impedance state, independent of
the Output Enable signal. If the iMC001 FLKA is deselected during erasure, writing, or write/ erase verification, the accessed zone draws active current until the operation is terminated.

Intelligent Identifier Command
The manufacturer- and device-codes can be read
via the Command Register, for instances where the
. iMC001 FLKA is erased and rewritten in a universal
reader/writer. Following a write of SOH to a zone's
Command Register, a read from address location
OOOOOH on any zone outputs the manufacturer code
(aSH). A read from address 0002H outputs the memory device code (B4H).

Write
Zone erasure and rewriting are accomplished via the
Command Register, when high voltage is applied to
VPP1/2. The contents of the register serve as input
to that zone's internal state-machine. The state-machine outputs dictate the function of the targeted
zone.
The Command Register itself does not. occupy an
addressable memory location. The register is a latch
used to store the command, along with .address and
data information needed to execute the command,
The Command Register is written by bringing Write
Enable to a logic-low level (VILl, while Card Enable(s) is/are low. Addresses are latched on the failing. edge of Write Enable, while data is latched on
the rising edge of the Write Enable pulse. Standard
microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/
Write Waveforms for specific timing parameters.

COMMAND DEFINITIONS
When low voltage is applied to the Vpp pins(s),. the
contents of the zone Command Register(s) default
to OOH, enabling read-only operations.
Placing high voltage on the Vpp pin(s) enable(s)
read/write operations. Zone operations are selected
by writing specific data patterns into the Command
Register. Tables 3 and 4 define these iMC001 FLKA
register commands for both byte-wide and wordwide configurations.
All commands written to the Command Register require that the zone address be valid or the incorrect
zone will receive the command; Any Command/
Data Write or Data Read requires the correct valid
address.

6-141

IMC001FL~A

Table 2. Bus Operations
Pins
Notes
Operation

Vce

rnA

Vcc

I'
!I{

6-155

IMC001FLKA

DC CHARACTERISTICS-Word Wide Mode
Symbol

Parameter

Notes

Limits
Min

Unit

Test Conditions

Typ

Max

1,4

±1.0

±20

p,A

Vee = Vee Max
VIN = Vee or VSS

III

Input Leakage Current

ILO

Output Leakage
Current

±1.0

±20

p,A

Vee = Vee Max
VOUT = Vee or Vss

lees

Vcc Standby Current

0.4

O.S

rnA

Vee = Vee Max,
CE# = Vee ±0.2V

rnA

Vee

1,2

rnA

Vee = Vee, Max CE# == VIL
f = 6 MHz, lOUT = 0 rnA

lee1

- Vee Active Read Current

Vee Max, CE#

lee2

Vee Write Current

1,2

5.0

rnA

Writing in Progress

lee3

Vee Erase Current

1,2

15.0

rnA

Erasure in Progress

lee4

Vee Write Verify Current

1,2

15.0

rnA

Vpp = VPPH
Write Verify in Progress

lees

Vee Erase Verify Current

1,2

15.0

rnA

Vpp = VPPH
Erase Verify in Progress

±SO

p,A

Ipps

Vpp Leakage Current

IpP1

Vpp Read Current
or Standby Current

1,3

IpP2

Vpp Write Current

1,3

rnA

Vpp = VPPH
Write in Progress

IpP3

Vpp Erase Current

,1,3

rnA

Vpp = VPPH
Erasure in Progress

IpP4

Vpp Write Verify Current

1,3

5.0

rnA

Vpp = VPPH
Write Verify in Progress

IpP5

Vpp Erase Verify Current

1,3

5.0

rnA

Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

O.S

VIH

Input High Voltage

2.4

VOL

Output Low Voltage

VOH1

Output High Voltage

VPPL

Vpp during Read-Only
Operations

0.00

VPPH

Vpp during Read/Write
Operations

11.40

VLKO

Vee Erase/Write Lock
Voltage

2.5

0.7

1.6

rnA

±0.16

Vee

+ 0.3

0.40
3.S
6.5

Vpp::;;; Vee
Vpp;:: Vee
Vpp::;;; Vee

V
V

IOL = 3.2 rnA
Vee = Vee Min

IOH'7' -2.0rnA
Vee = Vee Min

Note: Erase/Write are
Inhibited when Vpp

12.60

VIH

VPPL

V
V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at Vee = S.OV, Vpp = 12.0V, T = 2S'C.
2. 2 chips active and 6 in standby for word-wide mode.
3. Assumes2vpps are active.
4. Due to 100 kO pull up resistors, OE#, CE1 #, eE2#, and WE# will exhibit s; 55 p.A of additionallu when VIN = Vss.

6-156

iMC001FLKA

CAPACITANCE

Symbol,

25°C, f

1.0 MHz

Parameter

Limits

Notes
Min

Unit

Conditions

Max

=
=

CINl

Address Capacitance

VIN

CIN2

Control Capacitance

VIN

COUT

Output Capacitance

VOUT

CI/O

I/O Capacitance

VI/O

OV
OV

= OV
= OV

AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ................. VOL and VOHl
Input Timing Reference Level .......... VIL and VIH
Output Timing Reference Level ........ VIL and VIH

AC CHARACTERISTICS-Read-Only Operations
Symbol

Parameter

Notes

Min
200

Max

Unit

tAvAV/tRC

Read Cycle Time

tELQV/tCE

Chip Enable Access Time

200

tAVQV/tACC

Address Access Time

200

tGLQV/tOE

Output Enable Access Time

100

tELQX/tLZ .

Chip Enable to Output in Low Z

tEHQZ

Chip Disable to Output in High Z

tGLQX/tOLZ

Output Enable to Output in Low Z

tGHQZitOF

Output Disable to Output in High Z

tOH

Output Hold from Address,
CE # , or OE # Change

tWHGL

Write Recovery Time before Read

ns
60

ns
ns

1,2

IJ-s

NOTES:

1. Whichever occurs first.
2. Rise/Fall time';; 10 ns.

6-157

C)
0
0

(11

vee POWER-UPI
STANDBY

ADDRESSES

)(

DEVICE AND
ADDRESS SELECTION

)(

OUTPUTS ENABLED

STANDBYI
Vee POWER-DOWN

DATA VALID

ADDRESS STABLE

II
t AVAV ('tic)

,.......
'TI

CE# (E#)

~
C

...

CD
....
p

~I
~

OE# (G#)

I·

...0'3

1/1

...

WE# (w#)

:II

CD
III

", ,-

~LQV

c.:l

~---;_r

ujifeSf--"W1'.. ~~~~;f;~-;;---~

-_~~-C¥~S;;~~~W..it-li-~,.:,,-' z,..:~-~

>~"'~

IMC001FLKA

ORDERING INFORMATION

lilMlclololilFILlklAI I IslBlxlxlxlxlxl

OtolER IDENTIFIER

REVISION

K=WORO-WIDE
ARCH ITECTURE

FL= FLASH

001 = I tolEGABYTE
DENS ITY IN tolEGABYTES
tolC= tolEtolORY CARD
I=IN TEL

ADDITIONAL INFORMATION

290399-14

Order Number

ER·20, "ETOX II Flash Memory Technology"
RR·60, "ETOX II Flash Memory Reliability Data Summary"
AP·343, "Solutions for High Density Applications using Flash Memory"
RR70, "Flash Memory Card Reliability Data Summary"

294005
293002
292079
293007

REVISION HISTORY
Number

Description

-Removed PRELIMINARY
-'-Removed ExCA Compliance Section
-Clarified need for Valid Address during commands
....:.Corrected Vpp = VpPH in Erase Algorithm
-'-Increased ICC2-lcC5 D.C. current specs for both byte wide and word wide modes
-Revised and updated Application Section discussion
-Changed order number
-Corrected Erase Algorithm Pulse count to 3000

....:.Change signals with bars to #
....:.Change TIC values

6-164

int'et

AP-343
. APPLICATION
NOTE

Solutions for High Density
ApplicationsU sing .
Intel Flash Memory

MARKUS A. LEVY
DALE ELBERT
APPLICATIONS ENGINEERING
INTEL CORPORATION

October 1993

6-165

I
\~

Solut.ions For High Density Applications
Using Intel Flash Memory
.

CONTENTS

.. '.

PAGE

INTRODUCTION ....................... 6-167
ADVANCED PACKAGING ............. 6-167
Plastic Leaded Chip Carrier (PLCC) ..... 6-167
Thin Small Outline Package (TSOP) .... 6-168
Memory Cards ..•............. ,. ........ 6-170
Solid-&tate Memory Alternatives ........ 6-170
Designing a PCMCIA/JEIDAStaridard .
Memory Card .. '..............•....... 6-171
HARDWARE DESIGN
IMPLEMENTATIONS ................ 6-172
Design Example-A Paged-Mapped
.'
Memory Board ........... " ........... 6-172
The Window Address ................... 6-175
Vpp Generation ........................ 6-176
Page Number Selection and Reading ... 6-178
Optional Board Features ............•.. 6-179
Switchable Data Bus W.idth ............. 6-179
Linear Addressing ...................... 6-179
110 Addressing ......................... 6-181
Capacitive Loading .... ; ................ 6-183

, 6-166

CONTENTS

PAGE

SOFTWARE DESIGN
IMPLEMENTATIONS ... ....... ~ ..... 6-184
Data Recording ........................ 6-184
Interleaving ............................ 6-184
Power Requirements for Interleaving ... 6-.188
Write-Once-Read-Many {WORM)
Drives ............................... 6-188
Disk Emulation .. ;, .•.... ; ............... 6-189
Creating a Bootable Drive .............. 6-192
WHYFLASH?-CHARACTERISTICS
OF INTEL F~SH MEMORY ... ..... 6-192
, Power- consumption Comparison
(Watts) .........................'..... 6-192
Data Access Time ...................... 6-192
Reliability ............................... 6-193
Weight .......•......................... 6-194
SUMMARY ............................ 6-194

AP-343

INTRODUCTION
Mass storage encompasses many different technologies.
Though commonalities exist, mass storage strives for
nonvolatility, low cost per bit, and high density. Disk
drives provide the best known example. However,
many environments now require higher performance
and reliability with lower power consumption, even at
the expense of capacity. Flash memory uniquely meets
these demands.
Flash memory can be used as a mass storage medium in
applications including factory automation, notebook
computers, high-end workstations, point of sale terminals, and data acquisition systems. Even desktop computers benefit from solid-state storage. The motivation
to incorporate flash memory in any of these applications becomes obvious to the system designer who understands flash memory's benefits and density projections.
In an effort to understand these benefits, this document
includes both conceptual and application oriented discussions. These discussions will be kept to a minimum
with the real focus being on specific design techniques
and considerations.

ADVANCED PACKAGING
Mass storage is synonymous with high density. Disk
drives have increased the bit density of the rotating media via material improvements and closer tolerances.
For semiconductors, density requires advanced packag-

ing as well as higher capacity silicon (improVed photolithography). Intel's Flash Memory devices are based on
the company's EPROM Tunnel Oxide (ETOX) technology that enables the high degree of scaling required
to achieve high density.
Intel offers the high density flash memories in several
package types. The standard packages are the Plastic
Dual In-line Package (PDIP), the Plastic Leaded Chip
Carrier (PLCC), and the Thin Small Outline Package
(TSOP). Advanced modular packaging in the form of
PCMCIA compatible memory cards and flash drives
provide the total solution.
Which package is best for your application?

Plastic Leaded Chip Carrier (PLCC)
The engineer striving to reduce board space is already
using surface-mounted technology, such as PLCC. The
PLCC is seen frequently on PC add-in cards and motherboards. Compared to the DIP, PLCC uses as little as
35% the overall board space. Its small size, compared
to the DIP, is attributed to the terminal center-to-center spacing-50 mils versus 100 mils-as well as its
four-sided pinout. No drilling or lead-cutting is necessary as leads are soldered directly to pads on the circuit
board. The PLCC's 50-mil pad pitch is compatible with
most circuit board manufacturing equipment. Additionally, components can be mounted on both sides of
the board. However,the four-sided PLCC generally requires the use of a multi-layered board to layout conductor traces for maximum compaction.

6-167

AP-343

Thin Small Outline Package (TSOP)
When overall space constraints are critical, the TSOP is
the best choif:e. This is best exemplified by Ie memory
cards. Low height is the key attribute of the TSOP;
measuring 1:2 mm versus 3.5 inm for the PLee. (Mechanical drawingS iii Appendix.) State-of-the-art center-to-centerterminal spacing of 0.5 mm yields a smaller package and narrower conductor traceS than the
PLee or DIP. In comparison, the volume of the TSQP
is 112.8 mm 3 versus 656.3 mm 3 for the PLee and
1812.3 mm 3 for the DIP.

OE#

'i,

~
As
A'3
11,4
An

The TSOP is available in standard and reverse pin configurations (Figure. 1). Pins are located on only two
ends of the package. This approach simplifies trace layout while reducing the number of board layers because
traces can be routed out the. non-leaded sides of the
devices. Very dense board layouts are accommodated
because components can literally be. laid out end-to-end
and side-by-side. Figure 2 displays an optimal layout
best utilizing the TSOP's attributes. The close spacing
allows one bypass capacitor to be used for two devices
(provided they are not simultaneously selected). This
optimal component layout can be mirror-imaged
through the board to easily double the memory capacity.

'io

CE#
0.,
5

WE#

STANDARD PINOUT

Vee
Vpp

E28F020

'i6
'is
11,2
A7
A6
As
A4

OEiI
11,0

CE#

vss
O2
0,

Vss
O2

0,
DO

Ao
A,
A2
A3

'\l

Ag
As

07
06
05
04
03

Os
04
03

A'3
11,4
A17

REVERSE PINOUT
F28F020

WE#
Vee
Vpp
. A'6
'is
A'2
A7

DO
Ao
A,

A2
A3

As
A4

292079-17

Figure 1. 28F020 32-Lead TSOP-Standard and Reverse Pinouts

6-168

AP-343

!== I
~ 1-

OZO.:lBZ.:I

b,. !==
~

,=-

====-

E28F020

OZO.:lBZ3

F28F020

-==

fr
~
-=
-

==
==
==
-==
==
===-=== !==
==
==!== =~

OZO.:lBZ.:I

0
E28F020

OZO.:lBZ3

==
==
==
==
-

~
;::::: ====- -==-

F28F020

292079-18

Figure 2. TSOP Optimal Layout: Highest Density Configuration (Conceptual)

6-169

AP-343

Memory Cards
Many computer manufacturers are pursuing the IC
memory card to incorporate a removable mass storage
medium. This is an ideal application for the Intel Flash
Memory TSOP, due to the package's minimal height.

Solid-State Memory Alternatives
ROM and SRAM are currently the dominant IC card
memory technologies. ROM has the advantage of being
inexpensive, but is not changeable. When newer software revisions (e.g. Lotus' 123, Windows, etc.) are
available, the user must buy a new ROM card for each
upgrade. Intel Flash Memory's reprogrammability
minimizes the user's expense and the OEM's inventory
risk.
SRAM is reprogrammable but requires batteries to
maintain data, risking data loss. Like magnetic disks,
flash memory is truly nonvolatile and thus has virtually

infinite storage time with power off (100 years typical).
Additionally, SRAM is expensive and not a high derlsity solution. Intel Flash Memory provides a denser,
more cost effective and reliable solution.
System level cost is about the same for Intel Flash
Memory and SRAM + batteryFlash memory requires 12V for programming and erasing. If a 12V supply is not available, 5V can easily be
boosted. (See Application Note AP-316.) SRAM +
battery requires battery state detect circuitry.
Card level cost differences are substantial (Figure 3)SRAM must have a battery to retain data. It also requires aVec monitor and Write Lockout circuitry. Intel's Flash Memory only requires Write Lockout circuitry (switching Vpp to OV is an alternative write protect). This leads to increased area for memory components. More importantly, Intel's Flash Memory density
is 4 times that of static RAM, yielding lower cost per
bit.

CARD LEVEL

Battery
Higher Densities

SYSTEM LEVEL
Voltage
Converalon

Battery
State

SV-12V

Detoct
Circuit

FLASH

SRAM

Increased Area
for Memory
Components

Vee Monitor
CIrcuits

Writ.
Lockout
Circuit

Writ.
Lockout

CIrcuit

Lower
Densttl.s

FLASH

SRAM
292079-23

Figure 3. Support Circuitry Cost Comparison

'LOTUS is a registered trademark of LOTUS Development Corporation.
"WINDOWS is a registered trademark of Microsoft.

6-170

AP-343

Designing a PCMCIAIJEIDA Standard
Memory Card
Choosing among IC card design options depends on
card architecture (standardization), memory capacity,
data bus width, card intelligence, Vpp generation, and
reliability.
What are the advantages of a standardized memory card
pinout?

From the computer system's viewpoint, a standardized
pinout enables the use of multiple third-party memory
cards. This ensures competitive pricing and wide availability. From the memory card point of view, standardization allows use in a variety of systems.
The Personal Computer Memory Card International
Association/Japan Electronic Industry Development
Association (PCMCIA/JEIDA) 68-pin format has become the dominant IC memory card standard. Several

proprietary formats are also available from their respective manufacturers, but these same manufacturers now
. offer PCMCIA/JEIDA versions. The PCMCIAI
JEIDA standard specifies physical, electrical, information structure, and data format characteristics of the
card. This standard accommodates either 8- or 16-bit
system data bus widths.
The following 2 Mbyte memory card design provides a
byte-addressable interface using 8-28F020s (2 Mbit,
256k x 8 devices) as. shown in Figure 4. The same principles may be applied to higher density cards using
. higher density components. While TTL equivalent interfacing is shown, most cards will use gate arrays to
reduce chip count. Address lines Al8 and A19 are decoded with a 2-to-4 decoder (74HC139) to generate
high and low byte chip select signals for each of the 4
pairs of flash memory devices (one pair = high and
low byte). The PCMCIA/JEIDA format specifies inputs CEI # and CE2# (along with the AO address line)
select the low and high byte, respectively.

AO-17

HIGH

LOW

AO-17

28F020

74HC244

ADDRESSES

(Octal Buffer)

-----:r....,

AO ...

292079-24

Figure 4. Decoding for PCMCIA/JEIDA Standard Bus Interface

6-171

intel®
According· to· the .PCMCIA/JEIDA standard, the
memory card is designed with the flexibility.to have
both an 8Cbit or a 16cbitinterface, dependent upon the
machine it is plugged into. When the .memory card is
plugged into an 8-bitsystem, the high byte transceiver
is muitiplelled to the low byte of the system. In Figure
4, the highlighted transceiver (#2), maps the upper
byte to the lower byte of the data bus (i.e., DS-15 to
00-7)' Signals are. decoded according to the truth table
in the Appendix.
One can double the memory capacity lind select from
among 8 pairs of flash memory devices by using a 3 to 8
decoder with inputs AIS~2(); Notice that additional
transceivers are not needed to support the additional
data fanout. (See section on capacitive loading.)

HARDWARE DESIGN
IMPLEMENTATIONS
Paged, linear, and I/O are the three fundamental addressing methods that can be used for accessing an array of memory devices. Linear addressing offers the
fastest and most direct access to a memory array. It

consumes the largest portion of the system's memory
and is only practical in a 386 microprocessor (or other
32-bit processor). family system because of the. targe
memory space available above 1 Mbyte. The I/O
mapped memory array consumes the smallest amount
of the system address space but has the lowest performance. A page-mapped memory array, also called a sliding AT window, is a hybrid of the linear and I/O designs. The memory array is usually very large relative
to· the system interface, consisting of pages typically
ranging in size from 8 Kbytes to 64 Kbytes. (LIM-EMS
use four to twelve 16 Kbyte pages.)

Design Example-A Paged-Mapped
Memory Board
.
A paged desi~ employs addressing techniques similar
to the Lotus-Intel-Microsoft expanded memory specification (LIM-EMS). It allows access to one or more
sections (or pages) ofthe flash memory array at a time.
This minimal interface is particularly useful within .the
DOS 1 Mbyte memory space. The DOS map (Figure 5)
shows 128 Kbytes of memory space available in the
Optional I/O Adapter ROM area.

1OOOOOOH (16 MBytes)
EXTENDED
MEMORY
1OOOOOH (I MByte)
PC/XT/AT PS/2
ROM-BIOS
FOOOOH (960k)
PC/AT PS/2
ROM-BIOS
EOOOOH (896k)
PAGE MEMORY BOARD CAN /
BE INSTALLED
WITHIN THIS
128 Kbyte AREA ...........

OPTIONAL I/O
ADAPTER ROM
COOOOH (768k)
DISPLAY
BUFFERS
AOOOOH (640k)
APPLICATIONS
DEVICE DRIVERS
DOS
OOOOOH

2112079-25

Figure 5. DOS Memory Map

6-172

AP-343

Figure 6 shows the block diagram of a page-mapped
flash memory board design. (Except for the addressing
method, all the functional components of a board could
be used on a linear or I/O mapped flash memory array.) This PC-AT'" compatible design example consists of a flash memory array and the corresponding
memory and I/O decoding, Vpp generation, and the

interface to the system bus. A page size of 64 Kbytes is
used. Depending on the system's Coilfiguration, memory contention may require a smaller page size. (Note
that the LIM EMS 4.0 standard uses 4 contiguous
16 Kbyte pages. Multiple pages can exist as space petmits.)

I
I/o

ADDRESS

DECODE

DATA
I/O CONTROL

SELECT

Vpp ENABLE

vpp
GENERATOR

SYSTEM
BUS

MEMORY CONTROL

vpp

FLASH
MEMORY
ARRAY

1
CHIP ENABLE' (CE#)

MEMORY
DECODE

RD#, WEL#, WEH#
TRANSCEIVER SELECT

292079-26

Figure 6. Page-Mapped Flash Memory Board

ill:;
I
I.

I.
I

-"PC-AT is a registered trademark of International Business Machine Corporation.

6-173

AP·343
Ina system design usingPCMCIA/JEIDA stand~rd
memory cards thernemory card is treated like a large
memory array. Using a 64 Kbyte page size as an example:

Address lines AO-15 ate supplied directly from the system address bus {after buffering).. Address lines A 16-23.
which select the pages. are sent as data to a latch before
entering the memory card (Figure 7).

PCMCIA STANDARD
MEMORY CARD

74F521
COMPARATOR
Au-15

SWITCH

r---

I,
A16- 23

00- 7

PO-7
AEN

G#
P=O

:::::>
CD

-----

74F273
(O-TYPE FLIP-FLOP)

BHE#:=J

A16 - 23

00- 7

---- ~

] ) - CE1 #
1_

::IE

>V)

Control signals and data lines

I.&J
l-

Au-15

-------I-- -----

00- 7

00-7

SELECTS PAGES

CE2 #

11,6-23

10W#

10 PAGE
NUMBER
(from I/O decode circuitry,
not shown)

ClK
ClR

RESET
(forces pdgezeroon power up)

292079-29

Figure 7. Memory Card Interfacing

AP-343

an address is selected that is within the 64 Kbyte window. This signal (with AEN low) allows board level
memory de.code.

The Window Address
A user-selectable window address can be set up on any
64K boundary below 1 Mbyte. (The memory window
should be placed between COOOOh and EOOOOh to be
DOS compatible.) A DIP switch (connected to a transceiver for reading) and the four address lines A 16-19
are the inputs to the 74F521 comparator (Figure 8).
. There are 16 possible window addresses. The comparator outputs the "Memory Decode Enable" signal when

The location of this 64 Kbyte window can be moved
above 1 Mbyte by adding A20-23 to the comparator's
inputs P4 to P7 of the 74F521. Bits D4-7 of the data
bus can be connected to the comparator's pinsQ4 to Q7
to allow reading of the full base memory address .

READ AS 10 PORT

74rS21
COMPARATOR
SWITCH
A16
A17

----fpo
PI

~8----I

00 ....~-+-+-.,;:Wli.t
0 1 .........-+-+-W""2"'
02J--~i-.".;W34
03

t-----4........~

USER SELECTS 16 POSSIBLE
BASE ADDRESSES ON
64 KBYTE BOUNDARIES

04
05
06
07
GND (AEN·)
AEN----aG#
(ADDRESS ENABLE)

p=o#

MEMORY DECODE
ENABLE

292079-32

• NOTE:
Ignore the contents within parentheses. This is used for section on master/slave configuration.

Figure 8. User Selects Base Memory Address

6-175

AP-343

vPP ,Generation
Vpp can be generated locally to ensure astable,switch"
able 12V (±5%) supply. (Many systems generate their
own 12V"power supply. However, it should not be used
ifits regulation is greater than 5%.) On power-up, sys:.
tern reset, or when Vee is below 4.5V, Vpp is forced
otT. It is. enabled (or disabled) by writing to anI/Oport
address that generates the VPPEN # signal. This

on/off capability is essential for..battery.operatedequipment and eliminates the need for WE# filtering (as
discussed below). (See Intel data.sheet forVpp standby
current.) The VPPEN# sjgnal"ORed" with the system I/O write, lOW # ,functions as the clock signal for'
the, 74HC74 D-flip, flop (Figure 9). The D-input is
latched when lOW # goes high. Writing a,one or azero
turns VPI' on or off, respectively.

Read to determine'i-_ _ _-:::~
Vpp status

Vee

74F125

PR
10 DATA liNE a

(O-TYPE POSITIVE EDGE
TRIGGERED FLIP-FLOP)

10W#

270k

Q# 1--'V1IIr-....- -____

ClK

VPPEN#

....---'-41-+- (12V,
Vpp
200 mAl

D 74HC74 Q

RESET#
(Vpp OFF ON POWER-UP)

GND

r-----......------,......,---

RESET#

100 "F

GND

RESET

(from system bus)

+---.....-OC
292079-34

Figure 9. Vpp and RESET# Generation

6-176

AP-343

Linear Technology's LTlOn switching regulator is
used as a SV to 12V boost converter. The FB input'
regulates the voltage output. The 1O.7k and 1.24k resistors establish the correct reference voltage to obtain
12V. The 100 ,...F capacitor at the output is used to
handle up to 200 rnA. (See Linear Technology's
LTlOn data sheet for more information.) Typically
this will be much more than needed and a smaller capacitor can be used. However, this will accommodate
interleaving of 8 components but may not be practical
in a battery-operated system. (See section on Interleaving in the Software Design Implementation chapter.)
Additionally, sufficient time should be allowed when
switching Vpp on. The delay is a factor of the load on
the line and the quality of the passive components chosen. The diode, MURI20, keeps the inductor from absorbing current from the charged output capacitor. The
S.6V zener diode ensures that when Vpp is less than
S.6V, the Vpp output is held at OV. (This is optional if
Vpp :>: SV is tolerable.)

During system power-up, some probability exists that
noise may generate spurious writes which are actually
the sequence of flash memory commands that initiate
erasure or programming. Power-up protection in this
design is provided by disabling Vpp until voltages have
stabilized. The Motorola component, MC34064P, is an
undervoltage sensing circuit that begins functioning
when Vee is above IV. Between IV and 4.6V, the
RESET # output is active. The RESET # output or a
system RESET clears the 74HC74, keeping Vpp off
when Vee is less than 4.6V. Alternatively, this signal,
or a supply's "POWERGOOD" signal, may gate WE#
or CE#, as is common with battery-backed SRAM or
EEPROM designs. As an example, the RESET # output of the MC34064P can be tied to the active-high
enable of the decoder to disable any CEs # until Vee
= 4.6V, as shown in Figure 10.

Vee

RESET#
10k

MC34064P

74HC138
3 TO 8 DECODER

UNDERVOLTAGE
SENSING CIRCUIT
A3

G1
G2A#

MEMDECODE#

G2B#

GND

CEo#

cE1

CE2 #

CE3 #

CE4 #

CEs#

cEs#

CE7 #

292079-35

Chip Enables will not be active until Vee = 4.SV.
At this point, signals are stable and involuntary writes will not occur.

Figure 10. Protecting the Circuit from Involuntary Erasure and Programming.
Use an Undervoltage Sensing Circuit, or a System's "POWERGOOD" Signal, to Control Chip Enables

6-177

inte!®

Ap·343
Latching a one into the 74HC74 D-input puts a zero on
the output Q# .This turns off the transistor 2N3904.
When the 2N3904is off, the VC input ()fthe LTlOn is
5V and the VOLTAGE SWITCH (VSW) output generates 12V.

Page Number Selection and Reading
It is standard practice to use an I/O port· to gelllilrate

the page number for 'this type of memory array. The
potential number of pages that can be selected is determined by the size of the data bus as well as the amount
of decoding the system can practically handle. In this
design, this I/O port allows selection of 256 64-Kbyte
pages, for a total of 16 Mbytes of flash memory. The
page number is written to the 74F273, Octal D-Type
Flip-Flop (Figure 11). It is latched by the rising edge

10 DATA 0-7 -

clock signal derived by the "ORing" of the correspond~
'ing74F138 decode signal (I/O PAGE NUMBER) and
the system IOW#.
Page zero is automatically selected on power-up because the 74F273 clear input is connected to RESET #
(generated as part of the Vpp circuitry). This feature
ensures that the board will power up in page zero. Given the proper software, this board can be turned into
the system's bootable drive. (See section on Software
Design Implementations.)
The current page number can be obtained by reading
the same I/O port. The I/O decoder output, I/O
PAGE NUMBER, "ORed" .with the system IOR#,
produces the signal enabling the 74F245 bus transceiver
(that is tied to the output of the 74F273).

74F273
(OCTAL O-TYPE FLIP-FLOP)
00

05·

07
10W#
10 PAGE
NUMBER

-=D

RESET#
(FOR STARTUP AT PAGE ZERO)

10R#
10 PAGE
NUMBER

::f'
~

07
CLK
CLR

.......

' - - - A1

-r::-

r--

G#
D1R

74F245
(OCT ilL BUS TRANSCEIVER)
292079-36

Figure 11. Selecting or Reading Page Number

6-178

intel®

AP-343

must include similar provisions as shown earlier. At the
PC-I/O channel interface, (for use in an 8-bit system),
an extra transceiver redirects the upper data bus
(D8-1S) to the lower data bus (Figure 12). The 16BIT#
signal is generated from a ground on the PC AT I/O
channel extension; it will be high (because of the pullup resistor) when a PC XT is used.

Optional Board Features
So far we have described the components required to
design a functional flash memory array. Optional features can be added to make an implementation more
versatile in an application environment:

Switchable Data Bus Width

Linear Addressing

This feature allows a board to execute in a PC XT*
(8-bit bus) or a PC AT system (16-bit bus). Memory
card designs for adopting the PCMCIA/JEIDA format

Linear addressing directly maps the flash memory array into the system's memory space. "Instantaneous

An extra transceiver is used to redirect
the upper data bus to the lower data bus

I
DO
01

LOW 8-16-BIT
PO

Dg
0,0
011
0,2
013
014

f\.

02
03
04
05
06

P7
G#

0,5

HIGH 8-BIT
00
PO

01
PI
O2
P2
°3
P3
°4
P4
05
P5
06
P6

08
09 ,

01
02
03
04
05
06
07

P7
G#

0,0
011
012,
013

°14
015

,..-- OIR
74F245

DATA BU 5

OIR

10
CHANN EL

PI
O2
P2
03
P3
04
P4
05
P5
06
P6

74F245

,03

00-015

LOW 8-16-BIT

HIGH 8-BIT

o(:J=1

,01R
74F245

16-BIT
IOR#
SMEMR#

'-.'
--...

/'"""'j
'-..

EMOECOOE#

OECOOE#

10k

From

ground

of AT
16BIT# 10
channel

292079-37

Figure 12_1/0 Channel Transceiver Interface for 8- or 16-Blt Data Bus Selection

'PCXT is a registered trademark of International Business Machine Corporation.

6-179

Ap·343

SHE"

WE"

High 'and low byte selection
SWITCH
INPUTS

P=Q

An and A23 are
system address inputs

RO"
74.521

DIRECTION
74,244

ENABLE

GND

A, - 11,8
TO 28,020.
74F245

292079-44

Figure 13. Linear Addressing Hardware Block Diagram

Access" of the entire array is the obvious advantage
over paging. Additionally, the decode circuitry is simplified. Figure 13 shows an example for accessing 16
Intel Flash Memory 28F020s arranged in a 4 Mbyte
linear array.
The number of address lines used, as well as the decoder type (2 to 4, 3 to 8, etc.), is determined by the flash
memory device size. The address lines AI-AI8
are used for byte selection within each device
(256 Kbytes • 8).
The decodes for the individual devices can be designed
in a row-column method similar to that used for the
page memory board. An alternative design uses an individual chip enable for each of the 16 devices.

6-180

The enable for the 74HC138 (3 to 8 decoder) is governed by a 74F52l comparator. System address inputs
to the comparator are chosen to locate this. array on a
4 Mbyte boundary. (The array base address could be
located on a non-4 Mbyte boundary but this would add
to the decoding complexity.) With the inputs chosen in
this example (A22-A23), the array base address will be
between address 0 and 12 Mbytes to confine this memory. array within the PC AT defined address space of
16 Mbytes. A19-A21 are inputs to the decoder which
generates one of the eight chip enables (CE#). (Use a
74F245 transceiver for the data bus of every 8 flash
memory devices. THe address lines also need buffering
when connected to a PC bus.)

intel®

Ap;.343

1/0 Addressing
From the standpoint of the system's address space usage, 1/0 addressing provides a conservative solution.
As an example, four gigabytes of a flash memory array
can be addressed through only two 1/0 ports. An 1/0
write sends the flash memory addresses out on the data
bus. This "data" is latched (using '574s) and made
available to the flash memory devices and decoding circuitry (Figure 14). A third 1/0 port, used as an enable
for the flash memory device decoder and transceivers,
helps conserve power when the array is not being accessed.

S
Y
S

T
E
M

Relative to linear addressing, 1/0 addressing generally
has limited access speed capability because of the 1/0
"bottleneck": Read speed can be increased to match
linear addressing by replacing the '574 latches with
'191 counters.

In the following circuit example, decoding for 1/0 is
accomplshed with a 74F138, 3 to 8 decoder (Figure 15,
UI). The base address for these 1/0 ports is' on an
8-byte boundary. When any one of the 8110 addresses
is selected, the comparator (U2) generates the enable
signal (if AEN is low) for the decoder.

ADDRESS LINES

"o-A ' 5

FLASH

DATA BUS

MEMORY

00"'°,5
ADDRESS LINES

ARRAY

A,S-A 31

AND

U
S

DECODING

292079-45

Figure 14. Data Bus Generates Flash Memory Addresses

IOW#

--------lS;~--+:;:=:[)---~+
>------+

PLON

Pl1 #

Hr,38
3 TO 8 DECODER

'010-------'

"10------'

~~~~~~~j=)-____ transceivers end
To ENABLE th,

device decoder

>-----+
RESET#

10-------------

CLOCK_PULSE
1,1,'

VppEN#

I·

i
I,

'0
Q1
Q2

""
"

DIP SWITCH

TO SET

11
I

I/O BASE
ADDRESS

0'
Q7

lOR_

IOW#

II
Ij

74F521
COhlPARATOR

292079-46

Figure 15.1/0 Decode and Enable Circuitry

6-181

AP·343
An 1/0· write to the first and. second ports' generates
parallel load signals, PLo" and PLJ ". These signals
latch the "data" (addresses) into the 4-bit counters
(Figure 16, U3-'UIO). This latched data represents the
address for the flash memory devices.

A read or write from the selected flash IllemQryaddress
is performed when the third. 1/0 port is accessed (Figure 15, UI); this generates all enable for the flash memory device decoder and associated transceivers (Figure
17, To and.TJ).

TRANSCEIVER

BurrERED

o/u#

---0;- B•
0,
0,

QA
QB

-'.
-"
-',

DO _ A ,

0,
0,
0,
0,

E# ReO#l
Pl"

P'o"

ClOCK~PUL~

Os
O.

~
A

0"
Dg

0,.

_A.

D.
0,

-',
_As

QB _ A ,

QC
DO

0"
0"
0,.

•

Q'
. QB

0" ~
A QA
Dg

-",
_A"

0,.
0"

E" ReO"
Pl"
' - - CP
U9

28F'020's

YO I>--,
YlI>--,

-;:-- B
e

22-.

A'6

Y3 1>--,.

AI8

r--+
r--+
r--+

Aio

0
f--+

Y5 I>--,

Vee
ENABLE

1:.. G1

r-=

from Ul

Y6 I>--,

'23

Y7 I>--,

G2A#

G'.'
74F'138

GND

292079-48

A21
A22

Y2 I>--,

NOTE:
All counters are config-

ured in the
mode.

count

r--+
r--+
f--+ ',.
r--+

11.24
A25

A27

"----

r--+ '12
f--+ ",
r--+
".
f--+ A"

0"
0"
0,.

•

Qe
QD

RCO#

' - - CP

r--+
',.
f--+ A,•
r--+
A"
_A"

Reo#

Pl"

Pl'
CP

r--+,
f--+ A"
r--+
r--+

QB
Qe

E# RCO#
Pl"

E" RCO#l
Pl"
-

~ CP

_A.

E" RCa"]
Pl#

'---~

o/u#

•
B

E" ReO"
Pl"
CP
U7

v-=~
o.

A"
.,:;.A,.

GND

OATA BUS

TO 16-

'74Hci91

Ul0

P4 #

292079-41

NOTE:
Ao-A31 are inputs to flash memory devices. Only address lines Ao-A18 are used forthe

28F020s.

Figure 16. Counter Circuitry

6·182

Ap·343

$
.0

IOW#

8HE#

~--------------------------------------------------------WEL#

~------------------------------------------------------- WEH"

o-~
TO TRANSCE IVER
8UFF ERED
DATA BUS

FDa
BO
AO

A3
A4
AS

r--<:

85
87

FDI
FD2
FD3
FD.
FDs
FD6
F~

A7
Gil

',;

; '~

DIR
74F24S
(TRANSCEIVER)

DATA
ENA8LE

74F12S
IOR#

10-

t'
V
V
V
V
V

Os -015
TO TRANSCE IVER
8UFFERED
DATA 8US

FOs
FOg
Fo,o
FOil

Fo,2
FD13

F014
Fo,s

.... G#
DIR

TO DATA BUS OF
FLASH WEWOR y
DEVICES

74F245
(TRANSCEIVER)
292079-49

NOTE:
The 16-2BF020's are arranged as a 16-bit word configuration. WEL # and WEH # are for the low and high bytes, respectively.

Figure 17. Transceiver Enable Circuitry

The fourth 1/0 port activates the circuitry that obtains
very high performance from an 1/0 board. A read from
the fourth 1/0 port address generates the clock signal
for the 74HC191s, CLOC~PULSE. The counter increments on the rising edge of the clock (read signal),
selecting the next flash memory address. This rising
edge occurs at the end of the 1/0 read cycle and the
data has already been read. This method is analogous
to address pipelining. It is perfect for a "string" read
because continuous reads from the fourth 1/0 port automatically increments the address to access the next
word of data stored in the flash memory array.

Capacitive Loading
Capacitive loading is an important consideration for a
solid-state mass storage device. If proper buffering
techniques are not followed, performance degradation
will occur.
The specifications for Intel's Flash Memory devices are
based on a test capacitive load of 100 pF. Each data line
contributes 12 pF, therefore 8 devices connected to one
data transceiver will not experience speed derating
(12 pF • 8 = 96 pF). Additional flash memory devices

6-183

intel®
on that transceiver will increase the loading seen by any
one device.
Degradationis calculated as follows (Q = Amount of
Charge, T = Time, C = Capacitance, V = Voltage,
and 1= Current):
COULOMBS LAW STATES:
Q.= ItiT
AND GIVEN THE RELATION:

tiQ/C .... 1= C.tiV/tiT

FROM THIS RELATION, THE CHANGE IN ACCESS TIME CAN BE EXPRESSED IN TERMS OF
CAPACITIVE LOAD:
tiT = C tiV/I
For example, using four SIMMs,. each with 8 components in a 16-bit configuration (4 components on high
byte and 4 components on low byte), each Intel Flash
Memory device sees a load of 15 devices(12 pF • 15 =
180 pF). This loading is 80 pF in excess of the device
specification so therefore:
Time
_ Additional
x (Vee ~ VOL)
Change - Capacitance .
IOL
=80pFX

'(5.0 -

O.4)V
A

5.8 m

= 64n5

(Reflecting worst case conditions.)

SOFTWARE DESIGN
IMPLEMENTATIONS
Each hardware implementation discussed above can be
used in several types of mass storage applications. The
general .categories include: data recoders, Write-OnceRead-Many (WORM) drives for storing application
programs and fixed data, and magnetic disk emulators.

Data Recording .
The applications for data recording represent an endless list. Examples include digital imaging, digital pho·
tography, point-of-sale terminals, patient monitors, and
flight recorders. These systems. will . use Intel Flash
Memory as' a more economical and reliable replacemenlfor SRAM + battery. Alternatively, mechanical

6-184

disks will also be replaced by Intel's Flash Memory
when higher reliability, lower power consumption,
. higher performance, and lighter weight are required.

Interleaving
Although the basic concept of data recording is similar
from system to system, variations. in implementation
exist. For instance, some applications require highspeed data acquisition. Data programming rates are improved considerably by employing interleaving techniques. The majority of time spent programming or
erasing a flash memory device results from the delay
times in the software algorithms, (It is advised to review the standard algorithms first. See any Intel Flash
Memory data sheet for Quick-Pulse Prpgramming algorithm.) Interleaving takes advantage of these delay
times to begin programming consecutive devices.
There are hardware and software mechanisms for interleaving. The flash memory array for hardware interleaving requires special decoding techp.iques (Figure
18). Contrary to linear decoding, the system address
lines Ao-A3 are decoded to provide the chip select signals and individual bytes are selected with the address
lines ~-A20. (For the Intel 28FOlO.) This decoding
technique allows software to automatically access sequential devices by writing or reading sequential memory addresses. (Data accumulated with program interleaving will not be stored consecutively within a single
device.)
The interleaving algorithm to program the 2 Mbyte
flash memory array is shown in Figure 20 and 21. The
basic goal is to utilize the delay times. To simplfy the
algorithm for this discussion, the data will be pro.
grammed on a byte-wide basis. Wprd-wide and double
word-wide techniques, discussed later, will further increase programming speeds.
During mUlti-component programming, the number of
pulses required could vary between different devices.
Code is reduced if the programming loop !loes not have
to selectiyely "decide" if a byte has programmed correctly (verified). However, continual programming of a
programmed byte is not necessary and should be avoided. This is done by masking the command sent to that
particular device. The RAM table in: Figure 19 is used
aSa data and flash memory command buffer.. Aft~r a
programmed byte has verified, its associated, data and
commands in the RAM table are written with the value
OFFH (RESET command for Intel flash memory). The
data is also written as an OFFH sinc~ this is null program data.

AP-343

_
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _. ._ _-!AO-16
A[ 4, 20J WORD SELECT
28FO 10

CHIP
SELECTS

Ao
~

A2
A3

CE2 #

System
Address

Device
Pin

A..

-+
-+

A20

A16

Figure 18. Hardware Interleaving Block Diagram

DATA

2
D

3
AI

I IN P IU T I

F ~ 0 I,M

I / 10

n+1 n+2
Ip OIR T

40H 40H 40H

VERIFY COMMAND COH COH COH COH COH COH COH

COH COH COH

PROGRAM COMMAND 40H

VERIFY DATA

40H 40H 40H

D AI T AI

10rl~DIFr

o M

A ~ 0 ~ E

)
292079-51

NOTE:
n = 14 for the example shown in text.

Figure 19. RAM Array Used as Data Buffer and Command Mask Storage

'j~

292079-50

DEVICE#

,
"

Connection of Pins
at the Device Level

C
D

6-185

COUNTO=SIZLOf_COWPONENT
PTR 1= 1ST ADDRESS Of fLASH WEWORY ARRAY

~~~~.;;;;;;;::~0
LOAD RAW TABLE (AS SHOWN IN fiGURE 30
fLAG=OHffH
STORLPTR= PTR 1
COUNT 1=MALPROGRAW_ TRIES

FLAG used as indicator for successful byte program
verify.
MAX PROGRAM TRIES = 25

COUNT2= # _Of _COMPONENTS
PTR2= 1ST ADDRESS Of RAM TABLE DATA
PTR3= 1ST A.DDESS Of RAM TABLE PROGRAW_COMWAN
PTR4= 1ST ADDRESS Of RAW TABLE VERifY-COMMAND
PTR5=IST ADDRESS Of RAM TABLE VERifY-DATA

CONTENTS . AT PTR I =CONTENTS AT PTR3
CONTENTS AT PTRI=CONTENTS AT PTR2
INCREMENT PTR1, PTR2, and PTR3
COUNT2=COUNT2 - I

16 components for this example.
Initialize pointers.

Program command to flash device.
Program data to flash device.
To get to next byte location.

All components gone through?

PTR I =STORL PTR
COUNT2= # _Of _COMPONENTS

CONTENTS AT PTRI=CONTENTS AT PTR4
INCREWENTPTR I AND PTR4
COUNT2 = COUNT2 - I

Verify command to flash device.

~~----------~D
292079-52

Figure 20. Program Interleaving "Algorithm

6-186

AP·343

COUNT2= # OF COWPONENTS
PTR 1=STORE_PTR
PTR2= 1ST ADDRESS OF RAW TABLE DATA
PTR3= 1ST ADDRESS OF RAW TABLE PROGRAW_COWWAND
PTR4= 1ST ADDRESS OF RAW TABLE VERIFLCOWWAND

Does Flash Memory Byte = Verify
Byte?

Shift bits of flag left.
INCREMENT PTR1, PTR2, PTR3, PTR4, AND PTR5
COUNT2=COUNT2-1

YES, GO TO PROGRAWMING ERROR

Exceeded program tries, go to error.
All l's shifted out?

I.:

To access next byte of each device.

'~-----""''lA

292079-53

Figure 21. Program Interleaving Algorithm (Continued)

I
I:~

6-187

AP-343

Software and hardware interleaving are very similar.
Software interleaving is performed using conventional
decoding and addressing methods. Instead of incrementing flash memory addresses by one to access the
next byte (as with hardware decoding), increment the
address by the size of the component. While allowing
the use of "general-purpose" (non-interleaved) hardware, software interleaving requires reading back the
data in the same, non-sequential fashion as was used for
recording.

ly consumes 9 rnA (1 rnA IcC and 8 rnA Ipp) while
programming or erasing; this translates to about 100
mW. If interleaving with 16 devices, about 144 rnA (16
devices • 9 rnA) or 1.6W, is drawn. Battery powered
systems will have a practical limit on the number of
components in the interleaving loop. Failure to accommodate these current levels, resulting in Vpp voltage
drop, will compromise programming and erase reliability.

Interleaved erase is useful for quickly erasing an array
of flash memory devices. This approach greatly reduces
the total subsystem format time. As specified in the
erase algorithm, each erase pulse requires a 10 ms delay. (See Quick-Erase algorithm in Intel Flash,Memory
data sheet.) Without interleaving, the processor idles
during this delay time. As with program interleaving,
this time is used to begin the erasure of consecutive
devices, thereby reducing the overall erase time.

Wrlte-Once-Read-Many (WORM)
Drives

Further program and erase time can be saved by supplementing the byte-wide algorithm with 16· or 32-bit
interleaving. Extra data and commands are added to
the RAM Mask Table. The major difference in the algorithms involves the verify operation. Depending on
the bus width, 2 or 4 bytes are verified simultaneously
as shown in Figure 22 (for a l6-bit algorithm).

Power Requirements for Interleaving
Current consumption is an important consideration for
interleaving. During programming, each device typical-

~-........

The optical disk is an example of a typical WORM
drive application. Its strengths are extremely high densities and low cost per bit. However, it is an unacceptable solution for a low powered, lightweight laptop
computer system. It is this environmel).t that solid-state
drives offer the greatest benefit. Solid-state ROMs have
historically been used in. portable systems to store software programs that seldom change. When the software
changes, discard the ROM "application hardfile" and
program a new one.
Unlike the ROM drive, Intel Flash Memories can be
reused and reprogrammed in a true WORM fashion. A
computer user can load favorite software programs on
the flash memory drive. Add revised programs to the
drive by writing to the next free space or by erasing and
reprogramming the entire drive. Software drivers can
be written to implement this functionality in most operating systems.

PROGRAILCOMMAND=~PROGRAM_COMMAND OR OOFFH)

VERIf"CCOMMAND= VERIFY_COMMAND OR OOFFH)
VERIFY_DATA= VERIFY_DATA OR OOFFH)

PROGRAM_COMMAND=~PROGRAM_COMMAND OR FFOOH)

VERIFY_COMMAND= VERIFY_COMMAND OR FFOOH)
VERIFY_DATA= VERIFY_DATA OR FFOOH)

292079-54

NOTES:
1. MASK the HI Byte with OOH.
2. If the LO Byte verifies, then mask the data, program, and verify command with OOFFH (RESEn.
3. Mask the LO Byte with OOH.
.
4. If HI Byte verifies, then mask the data, program, and verify command with OOFFH (RESET).

Figure 22. 16-Blt Masking for Verify Operation
6-188

AP"343

Disk Emulation
Microsoft has a flash memory file system. It stores and
retrieves data or application programs in a manner
that, to the end user, appears similar to a disk drive.
New files are written sequentially from beginning of
memory. However, when the disk is full, it reclaims
memory space for storing additional files.
When an application accesses a disk through INT 21H,
the MS-DOS' kernel checks the drive letter (Figure
2~). If th~ d~ve h.as been declared as a flash memory
disk, a bUilt-in redlrector services the call (analogous to
~etworked drive accesses). Otherwise, if the drive letter
IS that of a floppy or hard disk, the call is handled by
the standard DOS file system. The File System provides
the link between DOS and the Flash Memory and
Hardware device driver. It changes DOS file system
commands into a form understood by this unique file
structure.

The Flash File System Driver contains the "intelligence" of this file system. It searches for:
I. A Boot Record that identifies the file system and
version, and locates the start of the data area;
2. The Root DireCtory Entry Record and many Directory and File Entry Records.
The file system driver is independent of the hardware
interface to the flash memory disk. The PCMCIA device drivers, developed by the OEM or BIOS software
vendors, interfaces the flash memory disk to the flash
file system. The actual implementation of the interface
is dependent on the hardware configuration of the disk
(I/O, paged, and linear addressing are examples).
To minimize fragmentation losses and allow arbitrary
extension of files, the flash memory file system uses
variable sized blocks rather than the standard sector/
cluster method of more traditional file systems. The

INTEL
FLASH MEMORY
SOLID-STATE>
DISK

292079-55

Figure 23. Disk Interface Levels

OMS-DOS and Microsoft are registered trademarks of Microsoft Corporation.

6-189

AP-343
fundamental structure employed to offer this flexibility
is based on linked list concepts; files are chained together using address pointers located within directory entries for each file.
Files and directories are written to the flash memory
disk using sequentially free memory locations-a stacklike operation (Figure 24). Furthermore, file sizes can
be variable, abandoning the traditional sector/cluster
apptoach of DOS. Wh~n "the stack" fills up, (containing deleted files), the intelligent software algorithm performs a cleanup operation to reclaim the "dirty" space.
File and subdirectory information is essentiaIly attached to the beginning of each file, unlike the standard
DOS approach of directory and FAT placement. As
directory and file entries are added, they are located by
building a linked-list. Besides containing the customary
fields (e.g., name, -0«
z>00«

82365SL

so (7:0)

,;;,,,, T

I--

CAROCTRL/STAT /INTR

SA(16:0)
LA (23: 17)

CONTROL
CAOOR (25: 12)

ISACTRL
IRQ

PWRCTRL

Vpp GENERATOR

SYSCTRL

PORT

Vee

PWR

292096-1

'This solution requires minimal glue logic.
Figure 1. The 82365SL Requires Minimal Glue Logic
NOTES:

1. The Bulk-Erase iMC001 FLKA, iMC002FLKA, and iMC004FLKA (One, Two and Four Megabytes. respectively).
2. Higher density cards may be realized in the future as component densities go beyond 8 Megabits.

intel®

AP-361

Ser!es 2 Flash Memory Card

I
I

REG#!

ASICS

-{>c>-

MEMORY PLANE
-HARDWIRED
- -ATTRIBUTE
----- CARD
- - - - - COMPONENT
INFORMATION
STRUCTURE

MANAGEMENT
REGISTER.S

FLASH DEVICES
I

~Lu

",L>

~i~

.....
~~
~

- - - MEMORY
- - - PLANE
-- - -- -- - - - -COMMON
28FOO8SA

28FOO8SA

t-sTA-TUS
REGISTER

t-sTA'Tus
REGISTER

rsrATUS
REGISTER

ts;:A-TUS
REGISTER

ts;:A'TUS
REGISTER

28FOO8SA

rsrA-TUS
REGISTER

t--si:A'TUS
REGISTER

t-sTATUS
REGISTER

1---,STATUS
REGISTER

292096-2

Operation Status Available at ASIC and Component Levels

Figure 2. Selecting the Attribute or Common Memory Planes
Computer systems using the Series 2 Card as a solidstate disk drive employ file management software, s~ch
as Microsoft's' Flash File System. This software capitalizes on the architectural benefits of flash memory. It
includes drivers that interface directly to the Senes 2
Card. Beyond specifying the harCiware architecture,
PCMCIA provides a software solution that consists of
modular software pieces designed for easy adaptation to
the various hardware platforms and memory technologies. The various pieces of the PCMCIA system may be
obtained from your BIOS vendor. Essentially, this
means that a system OEM is relieved of having to write
any software for Series 2 Flash Memory Card.

SERIES 2 COMPONENT
MANAGEMENT REGISTERS

This application note supplements the information contained in the Series 2 Flash Memory Card Data Sheet.
It benefits OEMs developing their own Series 2 Flash
Memory Card software pieces, including custom flash
file management software and software for embedded
systems running non-DOS applications. Specifically, it
describes the software aspects of implementing the
card's CMRs which provide software control of many
28FOO8SA functions, elevating the system designer
above device-level issues used by higher-level file system software.

PCMCIA RELEASE 2.0 DEFINED

The CMRs optimize the Series 2 Flash Memory Card's
performance by supplying a software-controlled interface to the individual devices within the card. As shown
in Figure 2, they are accessed as memory-mapped I/O
in the Attribute Memory Plane by pulling the card's
Register Select pin low (REG # , pin 61)(3). CMRs can
be divided into two basic categories; those defined by
the PCMCIA Release 2.0 specification and Intel defined "Performance Enhancement Registers".

Soft Reset Register
(Configuration Option Register)

During card operation, it may be necessary to place the
card into a known state by resetting the 28FOO8SA-level Status Registers and the CMRs in the ASICs to their
power.on conditions (Figure 3). Specifically, in the
NOTE:
3. No switch-over setup-time from Common Memory is
needed when PCMCIA timing requirements are met.

6-198

AP-361

III',:,,·

;.~1

Component Managment Reglsters(4)
Defined by the PCMCIA R2.0 specification
• Soft Reset Register (S)--(R/W)
• Global Reset-Powerdown Register (6)--(R/W)

i'~

:.!,'

PERFORMANCE ENHANCEMENT REGISTERS designed to deliver control benefits tied
directly to the Intel 28FOO8SA:
•
•
•
•
•
•

Sleep Control Registers--(R/W)
Ready-Busy Status Registers--(RO)
Ready-Busy Mode Registers-(R/W)
Ready-Busy Mask Registers--(R/W)
Write Protection Registers--(R/W)
Card Status Register--(RO)

ASICs, this reset affects the RP bit (Global Reset-Powerdown Register), the Sleep Control Register, the
Ready-Busy Mode Register, the Ready-Busy Mask
Register, and the CISWP and CMWP bits (Write Protection Register). There are several ways to enter power-on status:
1. Issuing a hardware reset, with a complete system reset or socket reset through the interface hardware, '
affects the entire system or the Series 2 Card, respectively.
2. During normal operation of many portable systems,
tremendous power savings are realized by entering a
suspend state. In this state, power to the card's socket is removed. After reapplying power, the card automatically attains its power-on status. Therefore, before removing power from the Series 2 Card, system
software must save the contents of the Component
Management Registers. It should also be pointed
out, that a startup period must elapse to allow all
internal circuitry to stabilize before accessing the
card. This time period depends on host system power
supply capabilities. (7)

3. The third method utilizes a software-controlled
mechanism built into the Series 2 Card. This option,
activated with, the Soft Reset Register, provides a
simple approach for placing the card in its power-on
state without time delay.
The Soft Reset Register (Figure 4) contains a soft reset
(SRESET) bit that performs a function similar to the
hardware reset invoked by the card's RESET pin
(RST#, pin 58)(8). Achieve the reset condition by issuing a two-step write sequence to the SRESET bit (i.e.
toggling from 0 to 1 and back to 0).
During reset (SRESET = 1), the ASICs drive the flash
memory array into the deep-sleep mode. This aborts
any device operations in progress and resets each device's Status Register. After initiating a soft reset, the
SRESET bit must be cleared (zero) to enable access to
the flash memory array or write to another CMR. The
host system can clear this bit by writing in a zero or
issuing a hardware reset.

Power-On Conditions'
ALL DEVICES IN STANDBY MODE.
SOFTWARE WRITE-PROTECT DISABLED.
ALL DEVICES' READY/BUSY # OUTPUTS UNMASKED.
PCMCIA-READY/BUSY# MODE ENABLED.
READY/BUSY# OUTPUT PIN GOES TO READY.
NOTE:

Generated by Hardware Reset or Toggling SRESET Bit.

Figure 3
NOTES:
4. R = READ, W = WRITE, RO = READ ONLY
5. Referred to as Configuration Option Register by PCMCIA R2.0.
6. Referred to as Configuration and Status Register by PCMCIA R2.0.
7. As specified by PCMCIA Release 2.0.
8. Soft reset puts all devices into power-down mode and requires a recovery time after returning from soft reset (500 ns for
reads and 1 ,..s for writes).

6-199

intel®

Ap-361

Soft Reset Register
(Configuration Option Register)

PCMCIA·Deflned
CIS
ADDRESS

BIT?

4000H

SRESET

II TogglE! SAESET to' reset and return to standby-mode .

• For power-on default, SAESET = O.

Figure 4. Useful for placing the card into a known state
The other two fields (not implemented with the Series 2
Card), defined in this register by the PCMCIA R2.0
specification, include the Configuration Index and the
LevIREQ. After powerup or soft reset, the Configuration Index contains zeros to maintain compatibility as a
Memory-Only Interface. The LevlREQ bit is hardwired
to zero.

system aimed at power conservation looks to shut down
portions of system circuitry not in use (Le. the solidstate drive not accessing files, the screen's backlight
when the keyboard has not been touched in a certain
amount of time, etc.). Powering down the entire socket
achieves a minimal power usage status. However, the
poweruprecovery time from this approach produces
varying delays.

GLOBAL RESET-POWERDOWN
REGISTER

The Series 2 Card offers the optimal solution with the
Global Reset·Powerdown Register (Figure 5). Writing
a one (I) to the Reset-PwrDwn Bit(RPbit 2) of this
register puts all internal devices into the Deep-Sleep
Mode by pulling every device's RP# input low(9). In
the Deep-Sleep mode, a 20 Megabyte Series 2 Card consumes90% less current versus the standby mode cur·
rent(lO).

PCMCIA R2.0 Defined
(Configuration and Status Register)

The portable system designer strives to minimize power
consumption in every conceivable way. Solid-state storage devices using Intel Flash Memory deliver significant power consumption reductions (When compared to
the mechanical disk) and therefore play an important
part of the system design considerations. The portable

When the host system drives the. two card enable pins
high(ll), the Series 2 ASIC circuitry blocks system-level
address and data signals from the internal devices. Additionally, latching address buffers and data transceiv-

Global Powerdown Register
(Configuration Option Register)

PCMCIA-Defined

• Aeset-Powerdown places all devices into ueElP-~SleE'p
• Write zeros to maintain PCMCIA compatibility.
• AP.,,;, 0 after reset.

FigureS
NOTES:
9. The remaining fields in this register (Changed, SigChg, IOisa, Audio, Intr and Asvd) are tied low in the Series 2 Card for
PCMCIA compatibility and for simplifying software masking.
'
10. Iccs = 30 jJ.A vs, ICCSL = 0.2 IJ-A; refer to 28FOOaSA Data Sheet. The ASICs consume 1 IJ-A.
11. CE1# (pin 7) and CE2# (pin 42) = VIH

6-200

AP-361

I
I~

I'i,'I.
I

:'~

SAMPLE BOXB6 CODE TO HANDLE RECOVERY-PERIOD TIMING

GLOBAL_RP
NOLRP

EQU
4002H
EQUOH

MOV AX, MEM_CARD_BASE
MOV ES, AX
MOV DI, GLOBAL_RP

;Global Reset-PowerDown Register

i1'

;Load card address
;Pointer setup

;Software assumes already in REG# mode access
MOV BYTE PTR ES:[DI], NOT_RP ;ClearsRP bit
MOV CX, RECOVERY_TIME
FOR_A_WHILE:
LOOP FOR_A_WHILE

;Based on speed of processor

Figure 6. Assembly Language Code for Returning from "Deep-Sleep" Mode

ers on the host side eliminate address and data signal
switching at the Series 2 Card input buffers further reducing power consumption levels. In other words, to
achieve the lowest power consumption levels, these signals should not be floated or tristated.
After clearing the RP bit, the device-recovery times
must be met before accessing the flash memory. As
shown in Figure 6, the recovery period can be implemented using a simple software algorithm(12).

successful status (Status Register = 80H) indicating
the need for software drivers to use the reset-powerdown function intelligently.

PERFORMANCE ENCHANCEMENT
REGISTERS

Sleep Control Register
(Performance Enhancement Register)

Prior to entering' the Reset-Powerdown Mode, your
softw!lre must check operation status for data-writes or
block-erases in progress(13). Any operations in progress
will be terminated when powering down the flash array.
The 28FOO8SA does not maintain Status Register contents in the Reset-Powerdown Mode. Therefore, when
the card returns to standby mode, all devices will report

The reset-powerdown functionality of the Global Reset-Powerdown Register has a global affect on all devices. In many solid-state storage applications, reading or
writing files only requires access to select device pairs
and the remaining devices could be kept in Deep-Sleep
status until needed.

Sleep Control Registers
Performance Enhancement Register

411AH
4118H
• For reset, all devices powered up (bits = 0).
• On cards less than 20 megabytes, absent devices read as "O"s.
• Bits cleared to zero by SRESET and RESET.

Figure 7. Allows Selective Reset-Powerdown of Devices within the Series 2 Card
NOTE:
12. PCMCIA does not specify a maximum recovery time. Recovery times, varying for different card technologies, must be
handled on a case-by-case basis.
13. Polling the individual device's Status Register, the Ready/Busy Status Register, or the RDY/BSY# bit in the Card Status
Register.

6-201

AP·361

21FOOISA Status Register 81t Definition

Figure I. Read during Write ol\Erase Operations to Determine Status
The Sleep Control Register (Figure 7) offers this option; each bit provides power down for a specific device
pair. ExceptJor the global vs individual affect, this reg·
ister functions identically to the Global Reset-Powerdown Register. The global reset-powerdown can be enabled while individual devices are sleeping. Disabling
the global RESET-PWRDWN does not affect prior bit
settings of the Sleep Control Register.
In many applications using the Series 2 Card, the card
will be in the Standby Mode a large percentage of the
time. This avoids device recovery times associated with
complete socket power off or entering the Deep-Sleep
Mode. In the Standby, Mode, the Sleep Colltrol Register offers the greatest advantage over the Global Reset.
Powerdown Register. With the capability of controlling
individual device pairs,' a power savings improvement
of approximately 16 times (based on typical current
values) will be seen. This is derived from the following
information:
• 28FOO8SA devices in Deep-Sleep; Icc = 0.2 ,..,A,

Ipp = 0.1 ,..,A.
• 28FOO8SA devices in Standby; Icc = 30 p.A,
. Ipp,= I,..,A.
• ASICs in Standby and Sleep; Icc =.1 ,..,A.
• With device-pair control,'unaccessed devices remain
in Deep Sleep.
'
Although the other operating modes (read, data-write,
or block-erase) also experience power savings by using
the Sleep Control Register, the effects are not as si~ifi
cant relative to the higher current 'requirements of
those modes.
When using the Sleep Control Register, SQftware must
account for the same device-recovery time of the global
reset-powerdown method. To access files (or data) that
span multiple device pairs (and experience uninterrupted access), software can perform a "look-ahead" function to determine which' device '}»drs, must be powered
up.

6-202

READY-BUSY STATUS REGISTER
Performance Enhancement Register
The automated data-write and block-erase capability of
the Intel 28FOO8SA FlashFile Memory results in' a significant performance'improvemellt. Furthermore, automation simplifies system-level interfacing as the user
only delivers the proper command and monitors the
operation's READY/BUSY, status. Referring to the
28FOO8SA Data Sheet (or Figure 8). operation status
can be obtained from the device's Statua Register or
RY/BY# pin. The device's Status Register allows software,polling for ready status in addition to write and
erase Status. The RY/BY # pin can be used to generate
an interrupt when making a busy to ready transition.
Regardless of the method uSed for determining ready
status, the Status Register should be read to determine
whether an, operation was successful.
In the Series 2 Card, where multiple devices are present
and muitiple simultaneous operations can occur, soft- '
ware polling each device's Status Register requires extra I!Oftware and time. Furthermore, the, PCMCIA interface only has one RDY/BSY # pin which obviously
prevents 20 devices from hooking their individUa1
RY/BY# out to the system. The ASICs within the
card take these signals and feed them into the BUSY #
Status Register (Figure 9). This facilitates multiple device-pair operations by allowing an analysis of all devices simultaneously. AfteJ:" initiating the data-write and
block-erase operatio~, the system can switch the card
to the Attribute Memory Plane to access these registers: Alternatively, each device's RY/BY # signal funnels into a single "wired
si~al that becomes the
PCMCIA-RDY/BSY#pin driving an interrupt or
polledthrougll an 1/0 port.
'' ,

or"

When performing single device pair operations, Ready1
Busy status should, be accessed directly from the Status
Register of the"flash memory devices for the following
reasons: 1) A device's Status Register must be read anyway to determine the result of. an operation; 2) This
saves several instructions required to switch to the Attribute Memory Plane.

AP-361

Ready-Busy Status Register
Performance Enhancement Register
CIS
ADDRESS
4134H
4132H

DEVICE
15

DEVICE DEVICE DEVICE
13
14
12

4130H

DEVICE DEVICE
7
6

DEVICE
5

DEVICE
4

BIT3

BIT2

DEVICE
19

DEVICE
1'S

DEVICE DEVICE
17
16

BIT 1

BITO

DEVICE
11

DEVICE
10

DEVICE DEVICE
S
9

DEVICE DEVICE
3
2

DEVICE DEVICE
0
1

'I!'

:1
I:f,'

i¥

• Each bit corresponds to a device's RY IBY 11 signal.
• Devices not present (i,e, < 20 Megabytes) return ready status,

'l
"

Figure 9. Monitors Individual Device's RY /BY # Pins

Example for Monitoring Ready/Busy Status

(Assume ES contains memory card base address)

RDLBSLSTATUS
DEVICE_O
DEVICE_l
DEVICE_2
DEVICE_3
DEVICE_4
DEVICE_5
XOR AX, AX

EQU
EQU
EQU
EQU
EQU
EQU
EQU

4l30H ;Register address
:Settings in register for specific devices
OlH
02H
04H
OSH
lOR
20H
;Zero AX Register

MOV DI, RDY_BSY_STATUS
;Insert code to start write operation in first 3 Device Pairs
;i.e. Devices 0, 1, 2, 3, 4, 5.
OR
OR
OR
OR
OR
OR

AX,
AX,
AX,
AX,
AX,
AX,

DEVICE_O
DEVICE_l
DEVICE_2
DEVICE_3
DEVICE_4
DEVICE_5

;Assume card already in REG mode.
TEST BYTE PTR ES:[DI), AX
:Zero flag cleared when programming
;devices are ready.

6-203

AP-361

tions perform well as background tasks because the interrupt latency constitutes a small fraction of the total
time.

READY-BUSY MASK REGISTER
Performance Enhancement Register
As described earlier, completion of 'a data-write or
block-erase operation can be determined by attaching
the card's RDY /BSY # pin into a system interrupt.
This frees the host system to perform alternate tasks
after initiating an operation.' In other words, device-level automation allows Series 2 Card operations to become background tasks.
Occasions exist where the interrupt generated from a
device becoming ready produces unacceptable latency
times. For instance, data-write operations, completing
in only 10 ,""S, realize a performance penalty dealing
with interrupt latenCies longer than the write time itself. The data-write operations would achieve a higher
level of performance by using software polling techniques(14). On the other hand, block-erase operations
typically require one second. Therefore, these opera-

This discussion implies that the system interrupt should
be disabled for data,writes and enabled for block-erases. What if an application requires simultaneous writes
and erases? The Series 2 Flash Memory Card handles
this situation with its Ready-Busy Mask Register (Figure 10). Setting the appropriate mask bits in the ReadyBusy Mask Register blocks the corresponding device's
RY/BY# signals. With a device's mask bit set, the
card's RDY /BSY # pin and Card Status Register (bit
0) always reflect a ready condition, regardless of the
operation status. Figure 11 displays a conceptual mask
circuit for a single device; The mask settings have no
effect on the card's Ready-Busy-Status Registers (providing direct access to each device's RY/BY# output)
' or the Devjce Status Register. This allows software
polling in the usual manner.

'Ready-Busy Mask Register
Performance Enhancement Register
CIS
ADDRESS
4124H

BIT3

BIT2

DEVICE
19

DEVICE
18

DEVICE DEVICE
17
16

DEVICE
11

DEVICE
10

DEVICE DEVICE
9
8

4122H

DEVICE
15

DEVICE
14

DEVICE
13

DEVICE
12

4120H

DEVICE
7

DEVICE
6

DEVICE
5

DEVICE DEVICE
4
3

BIT 1

DEVICE DEVICE
2
1

BITO

DEVICE
0
MASKED

Figure 10. Allows Masking of Individual Device's Ready/Busy Signals
Selecting the Appropriate Device to Mask
Assume the register set DI:DX contains a 32-bit physical address into SERIES 2 card.
Each device pair represents 2 Megabytes (i.e. 200000H).

MOV CL, 5 ;Load shift count
SHR DI, CL ;Result in DI is device ,pair number to mask.
;Now determine whether to mask device pair for word operations or use Bit 0 of
the DX portion to determine high or low device (odd or even) for byte
operations.
NOTE:
14. Polling the individual device's Status Register, the Ready/Busy Status Register, or the ROY /BSY # bit in the Card Status
Register.

6-204 •

AP·361

Single Device Representation of RDY IBS\' # Mask and Status

o
o
o

READ IN READY/BUSY
STATUS REGISTER

~2~aF-O-O-a-SA-'~DE~V~IC~E~~~-i,
~~_ _..

o
o
o
o
o
o
o
o
o
o

READY/BUSY

COMBINE WITH ALL DEVICE
OUTPUTS TO PRODUCE CARD
INTERFACE AND CARD STATUS
REGISTER READY/BUSY

MASK ENABLE
1-MASKED

292096-3

• Each device has a Ready/Busy (RY/BY#) output.
• When mask enabled, devices always appear ready.
• RY/BY# available in RDY-BSY# Status Register.

Figure 11. The Ready-Busy Mask is Very Useful for Write Optimization

READY·BUSY MODE REGISTER
Performance Enhancement Register
The PCMCIA specification for the Ready/Busy interface states that "the RDY/BSY# line is driven low by
the memory card to indicate that the memory-card circuits are busy and unable to accept a data-transfer operation." Contrary to the PCMCIA specification, devicelevel data-write and block-erase automation enables the
Series 2 Card to perform mUltiple operations simultaneously. Using the PCMCIA-specified method of
RDY/BSY # functionality for multiple device operations, the RDY /BSY # interrupt does not notify the
system until all devices finish because busy devices hold
the RDY/BSY# signal low, as shown in Figure 12.
Multiple block erases (typical block erase time of 1 second) could present an unacceptable pushout if system
software waits for the first available "clean" block to
write data.

The Series 2 Card offers an alternative Ready/Busy
mode (High-Performance Ready/Busy mode, alias
"Levy"-mode) removing the performance impact of the
PCMCIA mode. Circuitry internal to the ASIC catches
every "READY-going" edge from each device. After
an individual device becomes ready (Ready/Busy signal
goes high), the system has the opportunity to immediately service the interrupt. System software must now
toggle the CLEAR bit (bit 1) in the Ready-Busy Mode
Register (Figure 14) to reactivate the Ready/Busy signal. Figure 13 demonstrates the resulting waveform.
The Series 2 Card powers up in the PCMCIA-mode.
Switching into the High Performance mode requires a
two step prOcess; as shown in Figure 15. ASIC circuitry
design prevents being able to write a zero to the RACK
bit on the same cycle as entering the High-Performance
RDY /BSY Mode. This intentional design technique
eliminates the possibility of receiving a noise generated
RDY/BSY# rising edge, which would trigger an unwanted interrupt.

6-205

AP·361

PCMCIA·Deflned RDY IBSY # Waveform for Multiple Device Operations
IFirst operation finishes
DEVICE 0 RY!BY# - - - - ,.._ _....,jI""._lnterrupt _ '
latency
I
DEVICE 1 RY !BY #

DEVICE 2 RY !BY #
PCMCIA RDY!BSY#

---'L';..,--------...t:'----Interrupt occurs

292096-4

Figure 12. PCMCIA-Deflned RDY IBSY Waveform for Multiple·Devlce Operations
High-Performance RDY IBSY # for Multiple Device Operations
,

DEVICE 0 RY!BY# - - '.._ _~

DEVICE 1 RY!Byi; - - - - . . . . ,..-+,_ _:---.,-,- - - - -

DEVICE 2 RY!BY#
(Masked)
RDY!BSY# SIGNAL

------+:,-1
...... . ,-'*'I,t(-----.
LI:_ _

~...._~_____

tL.

:v.I

292096-5

MASK BIT ~ RDY!BSY#
RY !BY# ~ (PCMCIA-interface)

292096-6

NOTES:,
1. Device 0 operation completes. RDY/BSY# generates system interrupt. A masked RY/BY# is zero. Unmasking
simultaneously or after RY IBY # going high, still enables a low-to·high transition on ROY IBSY # to generate interrupt.
2. Software clears bit 1 of Ready-Busy Mode Register pulling RDY/BSY# signal low.
3. Last device operation completes. Masked ROY IBSY # signal does not generate interrupt. Software must poll to
detect operation completion of masked device(s);

Figure 13. Hlgh·Performance Mode Catches Each Device Going Ready

6·206

AP-361

Ready/Busy Mode Register
Performance Enhancement Register

• Mode = Ready/Busy Mode
o = PCMCIA Mode
1 = High-Performance Mode
• RACK = Ready Acknowledge Bit
Clear this bit after receiving ready status to prepare for next device's ready transition
• Register defaults to PCMCIA Mode for power on or reset. In PCMCIA Mode, RACK is a Don't Care

Figure 14. To Prevent Accidental Ready Transitions, a Three Step
Sequence mustbe Followed to Enter High-Performance Mode
As discussed in the previous section, the block-erase
operation benefits from the interrupt capabilities of the
RDY IBSY # signal. However, if your software only
erases one device pair at any time. the PCMCIA-RDYI
BSY# Mode will be sufficient for two reasons: I) Both
devices started simultaneously will complete the erase
operation almost at the same time; 2) in 16-bit access
mode. both devices of the pair must be erased before
writing.

,':'

To block-erase in multiple devices:
1. Be sure to mask all devices (in Ready /Busy Mask
Register).
2. If not already done. place the Series 2 Card in the
High"Perforrnance Mode (refer to Figure 15).
3. Issue the block-erase command sequence to the appropriate devices.

Enabling High-Performance Ready/Busy Mode

SET ALL BITS IN
RY /BY# MASK

PUT CARD IN
HIGH-PERFORMANCE
MODE

I CLEAR RACK BIT I

Prevents ready devices from triggering an unwanted rising edge, and generating an interrupt after clearing RACK bit.

Write a one (1) to the Mode bit of the RY/BY# Mode Register.

Write a zero (0) to the RACK bit of the RY/BY# Mode Register. The hardware requires this sequence to eliminate unwanted interrupts caused by signal-bounce.

292096-7

Figure 15. Entering High-Performance Mode

6-207

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, ,~

,intel®
4. Unmask appropriate Ready-Busy Mask Register
bits. The circ/litry catches devices with already completed erase operations with the conceptual setup ,
shown in Figure 13. Use a RAM-based variable or
register for an erase"block queue to monitor erasing
devices.
The interrupt service routine (ISR) can be as simple as
removing the erase block from the queue, It could also
be used to notify the system that this block is free to
use. Regardless of the ISR implementation, it. should
.
include the following basic procedures:
1. Set all RY/BY# masks in the Ready-Busy Mask
Register. This prevents additional interrupts within
the ISR (i.e. preventre-entrant interrupt). Keep
track of mask setup to reinstate before ISR exit.
2. Check the queue of erasing devices and read the
Ready-Busy Status Register to determine which device completed the operation.

3. Service the erased block(s). Even though one erased
block generated the interrupt, more blocks may have
completed· erasing at this. point.
4. Clear RACK in the Ready-Busy Mode Register.
S. Before exiting the ISR, reset the mask. This
"catches" devices that went ready during the ISR
and will cause a re-entrant ISR. However, at this
point in the ISR, this will not affect system or software integrity.

WRITE-PROTECTION REGISTER
The. Series 2 Card contains a PCMCIA-defined, hardwired Card Information Structure (CIS) accessed in the
Attribute Memory Plane. This data structure provides
fundamental, unchanging information pertaining to the
card. It includes card size, type of components, access
speed, etc. Situations exist where the user needs to include custom-format information, such as card partitioning and operating system specific information.

DIAGRAM OF COMMON MEMORY PLANE
13FFFFFH

DEVICE I PAIR 9

1200000H

DEVICE I PAIR 8

1000000H

OEOOOOOH

DEVICE: PAIR 7

OCOOOOOH

DEVICE I PAIR 6

OAOOOOOH
0800000H
0600000H
0400000H
0200000H

OOOOOOOH

28FOO8SA

DEVICE I PAIR 5
DEVICE I PAIR 4
DEVICE I PAIR 3
I

DEVICE: PAIR 2
I
I

DEVICE PAIR 1

'E0

•

><
co

"I ..
-::<

I ()
",0

_: The organization formed to promote interchangeability of IC cards by providing a
standardized mechanical, electrical and metaformat interface.
Performance Enhancement Registers: Memory"
Mapped I/O registers included by Intel in the Series 2
Card to boost performance by providing software control of the internal 28FOO8SA functions.
Ready/Busy: Indicator used to determine when a datawrite or block-erase operation has completed. Symbolized by RY /BY # for tJte 28FOO8SA and RSY /BSY #
at
Series 2 Card interface.

the

Status Register:. A register internal to a 28FOO8SA
FlashFile™ Memory device used to determine write
and erase operation status.

RELATED DOCUMENTS
Deep-Sleep Mode: A special very low power mode useful for saving power when not accessing the flash memory components.
Device-Pair: Arrangement of the 8-bit 28FOO8SA devices in the SERIES 2 card in a word-wide manner.

28FOO8SA, 8 Megabit, FlashFile™ Memory Data
Sheet
Series 2 Flash Memory Card Data Sheet
8236SSL, PC Card Interface Controller Data Sheet
PCMCIA PC Card Standard Release 2.0

Hardwired Card Information Structure (CIS): Embedded into the Attribute Memory Plane to describe

6-211

inial.

AB-56
. APPLICATION
BRIEF

Preparing for the Next
Generation Intel Flash
Memory Card

MARKUS LEVY
SENIOR TECHNICAL MARKETING ENGINEER

October 1993

6-212

Order Number: 292136-001

Preparing for the Next Generation
Intel Flash Memory Card
CONTENTS

PAGE

CONTENTS

PAGE

STANDARDIZATION .................. 6-214

WHY SUPPORT NEW CARDS? ....... 6-217

SOFTWARE DRIVERS FOR FLASH
CARDS .. ...... , " . " ................ 6-214
Flash Card Driver Functions ............ 6-216
Interfacing to the Flash Card Driver ..... 6-216
Installing the Flash Card Drivers ........ 6-217

THE DIFFERENCE BETWEEN
UPGRADABILITYAND
COMPATIBILlTY .................... 6-217
Device Boundaries ..................... 6-218
Device 10 .............................. 6-219
. SUMMARY ............................ 6-219

I
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!.f
'1

!.······.;:'··.

AB-56

STANDARDIZATION
What single word explains both the advantage. and disadvantage 0/ a PCMCIA socket? Standardization!

A customer buys a computer system with a PCMCIA
slot and expects to be able' to plug any 68-pin
PCMCIA-compatible PC card into that slot. Sure, the
form factor allows it to fit-The electrical signals even
. match Up,so there's no concern about damaging theIC
card (or computer system). The surprise comes when
that customer discovers that the system doesn't contain
the software drivers that support his newly purchaSed
card. Flash' memory, modems, faxes, and LAN cards,
to name· but a. few, all require .some type of software
driver to operate. For example, a flash file system that
fits into the PCMCIA software model can easily support new flash memory cards by using a Memory Technology Driver (generically referrred to as a flash card
driver).

This application brief explains. the benefits and .fundamental techniques for building in the upgrade capabili.ty required for new flash memory cards.

SOFTWARE DRIVERS FOR FLASH
CARDS
From a read standpoint, all of Intel's flash memory
cards (Series 1, Series 2, and even future generations of
cards) have similar functionality. They don't require
any special algorithms to read from them.. However,
these cards do have very distinct differences, especially
from a write and erase standpOint. For example, the
Series 1 cards require manual algorithms versus the automated algorithms of Series 2 cards '(Figure 2). But
don't be fooled, this situation is not restricted to Intel
alone. Flash memory writing and erase algorithms will
differ significantly depending on the card manufacturer, the included options, and the type of flash memory
devices in the card.

Flash

,
,,

Card

~.MOd.,m.·
L:J
{:<,',""" """"CJax.
4------

HOST SYSTEM
and
PCMCIA
Compatible
Socket
Adapter

Memory

__ - - - - -

\ ,
\

\
\

"""CJ

\
\
\
\
\
\
\

L:J

292136-1

Figure 1. Any PCMCIA-Compatlble PC Card Plugs into Any PCMCIA Socket

6-214

AB-56

Using a monolithic software model as shown in Figure
3 (one approach for integrating Microsoft's Flash File
System), the low-level driver, CARDDRV.EXE, contains all the code for interfacing the flash file system to
the socket adapter hardware and flash memory cards.
Specifically, it includes the write and erase algorithms
for Intel's Series I and Series 2 Flash Memory Cards.
After installing this monolithic piece of software in the
computer system, any unsupported flash memory card
could probably be read, but attempts to write or erase
would probably not work, for one reason or another.

Using the "monolithic" model, including support for
additional cards obviously requires a code modification
to incorporate the new software algorithms. But if the
system was already in the field, it would be most difficult to upgrade the software for each additional card on
the market.
What if the new flash memory card algorithms could be
"hooked" into the file system software without having
to make any modifications? What if the new flash card
algorithms could be installed automatically when the
new card was inserted into the socket? This concept
provides the foundation behind a flash card driver.

Series 2 Automated Algorithm

Series 1 Manual Algorithm
292136-2

Figure 2. Depending on the Card, Write and Erase Algorithms Can Differ Significantly

6-215

infel®

AB-56

MS-Flash

File System

• Copy-Transfers the specified data from one location to another within the same PC memory card, as
seeit when doingblock-to"block transfer during flas\!.
file system cleanup.
• Erase-Restores all of the !:>ytes in the specified
block to their erased state.

Hardware}.. Independent
Piece!

}

Hardwar~:'"

Depen.dent Piece
Requires Modifications

In a PCMCIA-compatible implementation (Figure 4),
Card Services interfaces between a flash file system and
the Memory Technology Driver. The file system ~lls
upon Card Services whenever it needs to perform one pf
the operations listed. above. Card Services, in turn, calls
uppn the MTD.

Socket
Hardware

Flash

Memory
Cord

292136-3

Figure 3. Th~ Original Fjle System
Approach Required Modifications for
Every New Card and System

Interfacing to the Flash Card. Driver

Most computer systems will ship with some level of
software support built into the box. For example, to
support Intel's Series 2 Flash Memory Card, a PC system would ship with Mjcrosoft's Flash File System,
CARDDRV.EXE (a low-level block device driver),
Socket Services, and Card Services. The algorithms that
write and erase this particular memory card would be
included within this original software package.

Flash Card Driver Functions
As shown in the PCMCIA softwaremddel below (Figure 4), the flash card driver (referred to as Memory
Technology Driver. or MTD) plays an integral role. The
purposes behiitd the flash card driver include:
• Isolation of the software required to monitor and
control a specific flash memory card.
• Increasing system performance by specifically optimizing software algorithms for flash memory cards.
• Reducing system m~mory requirements by eliminating software necessary to support other memory
card types. In other words, the only driver that
needs to be present is the one that supports the card
currently installed in the PCMCIA slot.

ROM/DOS

Fundamentally, the flash card driver manages 4 types
of operations to work in association with a flash file
system:
• Read-Transfers the byte(s) specified from a PC
memory c.ard to a buffer.
• Write-Transfers the byte(s) specified from a buffer
toa PC memory card.
292136-4

Figure 4. The Flash File System Indirectly Calls
the MTDthrough Card Services

6-216

AB·56

Installing the Flash Card Drivers

• A special loader utility can read the flash card driver from the card (hopefully it will have one).

When Intel's next generation flash memory card becomes available, a new flash card driver must be integrated into the system. How that happens will depend
on the system's memory-storage architecture, as depicted in Table 1.

• A system described as Case 1 in Table 1 cannot permanently store the new driver because it is ROMbased. After pulling the flash card driver from the
card, it must be loaded into system RAM while being used (i.e., until that card is removed). The other
system cases have more flexibility because the new
driver can be installed in flash -or on disk. However
the most practical solution calls for putting the driver on the card and leaving it there, where it is automatically pulled off upon insertion into the socket.

Table 1. System Memory Storage Architectures
Case

Hard
Drive

Floppy
Drive

Flash
Disk

ROM
Disk

Yes

External

Don't Care

Yes

Don't Care

WHY SUPPORT NEW CARDS?

The new driver can be installed into the system in several ways:
• Download the new driver from a bulletin board
• Use a cable transfer utility
• Floppy disk
• Flash memory card
From the customer's perspective, the flash card drivcr
on the card provides the most automatic solution. It
delivers the most convenient approach, especially if it is
automatically pulled off the card without user intervention. The mechanism to accomplish this could proceed
as shown in Figure 5:

EXECUTABLE
SYSTEM MEMORY

Flash Cord Driver

Flash Fite
System

Special Loader
Utility Pulls Driver
From Cord

I--r®

Flosh Card

Cord
Driver

Install

~
1----

292136-5

Figure 5. A Flash Card Driver Can Be Pulled from
the Card without User Intervention
• After interpreting the Card Information Structure
(CIS) to identify card and discovering an unsupported card type (i.e., specific flash card driver not built
into system), the file system realizes that it needs a
new driver.

• The OEM has a financial opportunity by selling
these cards as retail products.
• A system can accommodate any card already available on the market.
• An infinite number of drivers do not have to reside
in the system at the same time.

THE DIFFERENCE BETWEEN
UPGRADABILITY AND
COMPATIBILITY

SOCKET ADAPTER

1---.:

What motivation do OEMs have to include support for
flash card drivers and hence, new flash memory cards?
Intel's next generation flash memory cards will provide
much higher performance, densities greater than
40 Megabytes, and increased functionality. The generation after that will deliver even more technical advancements. Using these new cards will make a computer
system more desirable, ultimately producing a competitive advantage. The ability to support new cards via the
flash card driver method has the following benefits:

Upgradability allows a system to take advantage of new
capabilities; compatibility only allows basic functionality. At a minimum, compatibility implies that when trying to use a new flash memory card (i.e., not already
supported within the system) the system will not lock
up. Some OEMs may only desire to ship a computer
that supports one and only one type of flash memory
card. This system would not possess an upgrade path to
any additional flash memory cards.
This brings up the question of whether new flash memory cards will even be compatible when plugged into
this type of system. For the most part, the answer to
this question will be "NO". Intel has taken great efforts
to allow the Series 2 and next generation flash memory
cards to be compatible, at least from the write/erase
algorithm perspective. However some fundamental
concepts must be considered:

6-217

infel®

AB-56

Device Boundaries
Assuming the block sizes, remain the same, higher density flash devices (8 Mbit versus 16 Mbit) implies more
blocks per device. This changes the device boundaries
which only becomes an issue when performing multiple
operations per card (Figure 6). For, example, assume 2

28r008SA DEVICE PAIRS in a 4-,Mbyte Card

simultaneous block erases in a Series 2 card (occurring
in 2 separate devices). By virtue of the differences in
device sizes, these same 2 operations in the next generation card could be within the same device. The negative
impact behind this depends on the specifics of thesystern's software, but at the very least, it' would prevent
the second operation.

28rO 16SA DEVICE PAIRS in a 4-Mbyte Card

BLOCK 31

BLOCK 30

I
I
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I
I
I
I
I
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I
I
I
I
I
I
I
I
I

I
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I
I
I
I
I
I
I
I
I
I
I
I

BLOCK 17

BLOCK 16

aLOCK 15

BLOCK 15

BLOCK 14

I
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I

BLOCK 15

BLOCK 14

I
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BLOCK 2

BLOCK 1

BLOCK 0

I
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I
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I
I
I
BLOCK 2

BLOCK 2

BLOCK 1

BLOCK 0

292136-6

Figure 6. The 28F008SA and,28F016SA Have Different Device Boundaries

6-218

intel~
Device ID
Any new devices within a flash memory card will possess a new device ID. For example, the 8-Mbit devices
in Series 2 Cards have an ID value of A2H, and the
16-Mbit will have a value of AOH. System software
generally incorporates some type of lookup table to
match these values and determine the proper algorithms to use. However, every system should also have
a method for handling unrecognized values, which at
the very least should be a "graceful" rejection. These
values can be obtained from either the card's CIS or
directly from the flash memory device (Intelligent Identifier).

SUMMARY
The PCMCIA socket enables a computer system to
support an unlimited number of capabilities simply by
removing one IC card and inserting another. These
cards ranging from modems to flash memory, require

AB-56

some form of system software support. From a flash
memory card perspective, software drivers perform the
various read/write/copy/erase algorithms. These drivers can accommodate two levels of functionality:
Compatibility-As a minimum, flash card drivers
should support the basic write and erase algorithms required by a flash memory card. The word compatibility
implies that this software allows new flash memory
cards to work without failing and nothing more.
Upgradability-As Intel's flash memory technology
evolves and improves, new,cards will require flash card
drivers that optimize their functionality. From an enduser perspective, the simplest way to integrate these
new drivers is to automatically install them from the
flash memory cards. This implies that OEMs must be
developing mechanIsms to "hook" these drivers.
Be compatible for basic functionality. Upgrade to take
advantage of the future!!!

6-219

Intel FlashFile™ Memory
The Key to Diskless
Mobile pes

JANET WOODWORTH
. MEMORY COMPONENTS DIVISION

November 1992

6-220

Order Number: 297115-001

INTEL FlashFile™ MEMORY

INTRODUCTION

ENTER FLASH MEMORY

As the PC evolves into what is truly a "personal" computer-one that can be held in your hand-a completely different system memory architecture will emerge.
Step aside ROM, DRAM, floppy disk, and hard disk;
Intel's FlashFile™ memory is here. FlashFile memory
will finally make it possible to build a thin, 2-pound
notebook computer that runs for many hours on a few
AA batteries. But before these mobile PCs are built,
designers must learn some new ways to configure system memory.

Because Intel's ETOXTM III flash memory cell is
30"percent smaller than equivalent DRAM cells, the
company expects it to track DRAM density closely.
Intel's new 28F008SA FlashFile Memory can store
8 megabits, or one megabyte, of data today. Flash
memory is more scalable than DRAM due to its simple
cell structure, so as DRAM technology shrinks towards
0.25 microns and 64 megabits, flash will pace and ultimately overtake DRAM's technology treadmill. In
fact, expect to see 256-Mbit flash memory by the end of
the '90s.

In April 1992, Intel introduced a new flash memory
architecture with a combination of functionality and
price that redefines mobile computing. This new architecture, when implemented in new system memory configurations, enables nonvolatile executable system
memory and removable file and program storage.
Intel's new flash architecture lets designers create a
portfolio of products that will clearly differentiate them
from their competition.

WHY A NEW MEMORY
ARCHITECTURE?
The ideal memory system is:
• Dense (stores lots of code and data in a small
amount of space and weighs very little)
• Fast (lets you read and write data quickly)
• Inexpensive (low cost per megabyte)
• Nonvolatile (data remains when power is removed)
• Power Conscious (prolongs battery life and reduces
heat)
• Reliable (retains data when exposed to extreme temperature and mechanical shock)
Since PCs were introduced over 10 years ago, designers
have grappled with how to construct memory systems
that offer all these attributes. They have wisely elected
to use to optimum combination of solid-state memory
and magnetic storage, i.e:, DRAMs plus magnetic hard
disks. DRAMs are dense and inexpensive, yet slower
than the processors they serve, and they are volatile.
SRAMs are used in caching schemes to compensate for
DRAM's slowness. While SRAMs keep pace with today's high-performance microprocessors,· they are not
as dense as DRAM, are inherently more expensive, and
volatile. Magnetic hard disks are very dense, inexpensive on a cost-per-megabyte basis, and nonvolatile, but
they are painfully slow, power hungry and subject to
damage from physical shock.

FLASH MEMORY IS FAST
Don't be misled by technology-to-technology speed
comparisons. Designing your system memory around
flash will break the code/data bottleneck created by
connecting a mechanical memory such as disks to a
high-performance electronic system. For instance, data
seek time for a 1.8" magnetic hard disk is 20 ms, plus
an 8 ms average rotational delay, while flash is less than
0.1 ms. At the chip level, current read speeds for'flash
are about 90 ns. Thus, downloading from flash to system RAM or directly executing from flash will dramatically enhance system speed.

FLASH MEMORY IS INEXPENSIVE
At the 8-Mbit density, Intel flash pricing matches
DRAM and Intel expects to continue decreasing price
as both densities and volumes increase.

FLASH 1$ NONVOLATILE
Unlike SRAM orpseudo-SRAM (SRAM with built-in
battery), flash needs no battery backup. Further, Intel's
flash devices retain data typically for over 100 years,
well beyond the useful lifetime of even the most advanced computer.

FLASH IS POWER CONSCIOUS
FlashFile Memory in a hard-disk drive configuration
consumes less than one two-hundredth. the. average
power of a comparable magnetic disk drive based on
the typical user model. At the chip level, the 28F008SA
has a DEEP POWERDOWNmode that reduces power
consumption to less than 0.2 /LA.

FLASH IS RUGGED AND RELIABLE
On average, today's hard-disk drives can withstand up
to 10 Os of operating shock; Intel FlashFile memory
can withstand as much as 1000 Os. FlashFile compo-

intel®

INTEL FlashFUe™ MEMORY
nents can operate at up to 70"C while magnetic drives
are limited to 55·C. Intel FlashFile memory can be cycled 100,000 times per block or segment. By employing
wear-leveling techniques, a 20-Mbyte flash array can
provide over 30 million hours before failure.

Flash-based solid-state disks, intended to replace magnetic hard disks in certain applications, with IDE interfaces will be "plug compatible" with existing systems
that are already designed with IDE magnetic drives in
mind.

WHY. NOW?

3. Flash File System

Flash memory is not a new technology. Intel has been
the flash technology and market leader since 1988.
Then why hasn't flash taken the mobile PC market by
storm yet? Why now?

Intel has worked very closely with Microsoft' to implemen( a DOS flash memory extension called Flash File
System (FFS) that transparently handles ,swapping of
data between flash blocks, much as DOS now handles
swaps betw~ disk sectors. With Flash File System,
the user inputs a DOS comand and doesn't need to
think about whether a magnetic disk or a flash memory
is being \lsed. Flash File System employs wear leveling
algorithms that prevent any block from being cycled
excessively, thus ensuring millions of hours of use
across multiple chips.

One reason that 1992 is the pivotal year for flash-based
systems is the sharply increased demand for highlymobile computers. The other reason· is that a number of
key capabilities, in development for sometime, reached
maturity together.

1. Intel Introduces FlashFlle™
Memory
MS-DOS', the ubiquitous operating system for PCs,
was developed specifically to optimize the sectoring
scheme inherent to disk technology. Intel's first generation "bulk.erase" flash required that all of the chip be
erased before data could be re-written: a natural fit for
updatable firmware and data acquisition, but not for
data file storage or disk emulation. Intel FlashFile
memory, based on a block-erase architecture, divides
the ·flash memory space into segments that are some-·
what analogous to the zones recognized by MS-DOS.
For instance, the Intel 28F008SA contains sixteen identical, individually-erasable, 64-Kbyte blocks. This organization has been carefully optimized to maximize cycling capability while preserving the smallest granularity possible. The ability to segment block memory into
individual segments allows disk-like data-file storage.

2.· Standardization of Delivery System
and Interface Thanks to work by the Personal Computer Memory
Card International Association (PCMCIA), and the
Japanese Electronics Industry Development Association (JEIDA), there is now an internationally recognized standard for memory cards. PCMCIA cards are
the size of a business card but about four times as thick.
Intel is widely promulgating its Exchangeable Card Architecture (ExCATM), a hardware and software implementation of the PCMCIA system interface. When
used with the proper BIOS, ExCA/PCMCIA-compatible cards will be completely interchangeable between
systems and vendors, and clln be equated to solid-state
floppy disks, albeit with many advantages.

6-222

4. Off-the-Shelf Hardware Interface
The introduction of the Intel 82365SL PC Card Interface Controller provides a ready-made interface between the PC:s ISA bus and up to two PCMCIA sockets. It is a key component for memory and 1/0 card
implementations since the designer is relieved from
building the interface from scratch.

5. Cost Reductions
Magnetic drives do not scale well; that is, it becomes
increasingly difficult to improve or even retain density
as platter size shrinks. Thus, every reduction. in drive
size requires complete retooling and costly learning.
Also, the complex controller circuitry provides a price
floor under which magnetic drives cannot drop. Since
flash is scalable, at some point in the near future, small
magnetic drives are likely to become more expensive
per megabyte than flash cards and are certain to have
less capacity. But even today, the value of a particular
memory technology is a result of more than just dollars
per megabyte.
Notes market analysis expert Dataquest:
"The question is, "Can you put a floppy disk drive
ina palmtop PC to take advantage of the cost disparity (between disk and flash)?" The answer· is,
'No.' There is not enough power (or space). The
issue then, is not cost. Here, the removable storage
medium dictates the product's .capabilities and its
success or failure in the marketplace. Without a
memory card, a palmtop is nothing more than an
electronic organizer. It. is the memory card that
transforms a palmtop into a full-fledged personal
computer." ... Nick Samaras, SAMS Newsletter.

INTEL FlashFile™ MEMORY

All of the aforementioned features, Intel FlashFile
memory's block-erase architecture,PCMCIA standards, ExCA, Flash File System, 82365SL ISAPCMCIA interface controller and reduced costs, are
deliverables ... now. And not a moment too soon
based on the tremendous market opportunity created
by the increasing demjmd for truly mobile computers.
Dataquest predicts that the worldwide sale of portable
PCs will increase from six million units in 1992 to nearly 30 million units in 1995. While laptop PCs are only
expected to increase by about two million units, notebooks, pen-based, and handheld PCs will increase from
three million units in 1992 to nearly 25 million in 1995,
an eight-fold increase. This extraordinary growth will
be greatly assisted by FlashFile memory.

ENABLING THE TRULY MOBILE
COMPUTER
In the world of the desktop PC, DRAM is used for
executable code storage and data manipulation. Since
DRAM is volatile, if power is lost, both programs and
data are lost, hence the need for a nonvolatile magnetic
hard disk. With the addition of the hard disk, programs
and dat~ are stored on the hard disk and swapped in
and out of DRAM as needed. Some part of the DRAM
is reserved for use as a register to store temporary results during compute-intensive operations. Today's PCs
are typically. configured with 4 megabytes of DRAM
and at least a 40-Mbyte disk.
FlashFile memory fully supports this system configuration when used simply as a magnetic drive replacement.
Instructions and data are, still swapped to DRAM but
at a much faster rate. Plus, execution speed can be en'
hanced if the DRAM is replaced with SRAM.
In the solid-state computer, the "DRAM + magnetic
hard drive" are replaced by a "flash memory +
SRAM". The key to this architecture is the ability to
eXecute-InPlace (XIP). Program instructions stored in
the flash memory are read directly by the processor.
Results are written directly to the flash memory. Compute-intensive operations that require the fastest memory and byte-alterability use high-speed SRAM or pseudo SRAM. Most of what we now think of as the
"DRAM" is replaced by low-cost flash and only a relatively small part of the DRAM is replaced by SRAM.

The flash memory space is made even more storage-efficient through the use of compression techniques
which offer at least 2:1 compression. For example, one
20-Mbyte flash card that uses 2:1 compression offers
the same storage as a 4O-Mbyte hard disk!
The advantages of a flash-based computer include:
•
•
•
•
•

Blazingly fast speed
Instant-on and instant-resume
Ultra-light PC (2-4 lbs.)
Very secure data retention
Flexible firmware

As you can see, by changing the system memory architecture to a. flash-based one, designers will be able to
build a new generation of PCs that meets the needs of
the computer user of both today and tomorrow.
Progress has been made toward implementing this approach with the introduction of Hewlett-Packard's successful HP95LX DOS-compatible palmtop. MS-DOS
and Lotus 1-2-3* are stored in ROM. Internally, pseudo-static RAM is used, and a PCMCIA memory socket
is provided. Lotus 1-2-3 was re-written to allow ROMbased storage so it could execute in place. Other ROMexecutable versions of popular operating systems are
expected to be available shortly.

DESIGNING YOUR SYSTEM WITH
FLASHFILE MEMORY
Details of the three Intel flash applications and implementations-flash cards, silicon disks, and Resident
Flash Array (RFA)--are presented below.

APPLICATION NUMBER 1: MEMORY
CARDS
Memory cards arF the most rugged and reliable of the
removable memory media. A card can be slipped into a
shirt pocket and moved from location to location. With
high-density flash cards, you can download files from
the desktop and use the card in your notebook or palmtop.

6-223

INTEL FlasI)Fflett.lNlENlQRY
M~ry

cards .have been around for sOme time. The
first cards to be hltroduced were ROM'"Only cards used
in video games ,and pocket organizers. These were produced in various formats prior tathe formation of
PCMCIA and lEIDA.· Later cards included batterybacked SRA¥ and EEPROM. Neither became very
popular due to their high cost of $500-$600 per megabyte and limited capacity. Fla~ cards overcome the
cost barrier and they are certain to bci mul~ply sourced,
assuring availability and .Competitive .pricing.' A
20-Mbyte fl8sh card has three times the real storage
density of a 2O-Mbyte 1.8" magnetic drive
(0.95 Mbyte/cm3 vs 0.34 Mbyte/cm3) and it has 10
times the weight density'(2 Mbyte/gm vs 0.21 Mbytel
gm). The PCMCIA has complete industry support, and
enhanced versions, such as PCMCIA Version 2.0, are
designed to be backward-compa,ible with earlier versions.

As part of itS flash product family, Intel's new Series 2'
memory cards are the ~t to utilize chips processed on
its 0.8-micron flash teChnology. Storing up to 2q megabytes, these cards are designated Series 2 to differentiate them from the earlier bulk-erase' flash cards. The
cards consist of 4 to 20, 28FOO8SA TSOP FlashFile
memory devices. Each 28FOO8SA contains 16 distinct,
indiyidually-erasable, 64~Kbyte blocks. Therefore, each
card contains from 64 to 320 blacks.
With the re1el\SC of PCMCIA Version 2.0 in September
of 1991, the PCMCIA-compatible field grew somewhat
larger. The PCMCIA interface grew from memoryonly. to one that supports many types of VO devices.
Intel's system-level implementation of PCMCIA 2.0,
called, ExCA; ensures that if there are two ExCA sockets available, one can be used for a flash memory card
~d one for a' lIlodem; and the car!is may be inter~
..' changed.
How difficult is it to design-iR an ExCA socket? Not
verY. Intel's ppen ExCA specit1cation details the system
illlplementation. Other than the .physical inconx>ration
of the socket and card, the only required hardware is ali
ISA-to.PCMCIA interface such as Intel's 82365SL
chip, and
an" ExCA Compliarit
from vendors like.
"
.
. BIOS
,',

6-224

SystemSpft, Award and Phoen~. You'll also need a
flash file management 'system like' Microsoft's Flash
File System~ Intel's block-erase architecture, along With
the DOS Filing System and ExCAinos; makes it easy
to incOrporate ExCA features. II! addition, ExCA-com~
pliant systems will !illow system-to-system interoperability much like flopP! disks.

APPLICATIOt4 NUMBER 2:,
FLASH~~ASED SOLID $TATE DISK
The implementation of block-erase flash as a "solidstate disk" '(SSD) is' something of a misnomer. It is not
Ii disk at all, rather a flash module that has. the same
form, fit and function as a 2.5" or smaller magnetic
drive.
I
A flash-based SSD implementation is the most direct
route to adapting flash to an existing design. A built-in
IDE' interface would make it plug-compatible. But
what a difference a silicon disk will make! A 1.8" drive
typically uses,one watt-hourlhour while: a silicon disk
uses as little as 0.035 watt-hourlhour. This kind of
power savings makes it possible to reduce battery size
and weight considerably: Or,consider reliability; We've'
already discussed differences in susceptibility to shock
and temperature elttremes. In addition, an SSD theoretically has a mean-time-between-failure (MBTF) of
250,000 hours, compared to loo,boo hoUrs for the magnetic drive.
With all th~ advantages, when should you use memory cards and when is use ofa flash-based SSD preferable?
First and foremost, the SSD is considered to be installable while memory cards are removable and transp~r
table. In othet words,' the SSD is meant to be installed
and then . left alone, while memory cards are designed
for constant removal and reinsertion. In operation, the
only change a user would notice in a notebOok computer equipped with a flash-based SSD is that access speed
is Unprecedented.

INTEL FlashFile™ MEMORY

The flash-based solid-state drive is one very good way
to get to market early with flash technology. In February 1992, Conner Peripherals, Inc., and Intel an-'
nounced the signing of a joint product and technology
development contract focused on designing and bringing to market proprietary FlashFile memory-based
SSD storage products.
Incidentally, manufacturers of magnetic drives are
starting to take notice. In a manner much like the tail
wagging the dog, 1.8" magnetic hard disks with
PCMCIA interfaces are currently being developed.

APPLICATION NUMBER 3:
RESIDENT FLASH ARRAY
The one approach that offers totally new capabilities is
the Resident Flash Array (RFA). This is an arrangement of from 8 to 20, 8-Mbit FlashFilememories. In
the long term, it replaces some of the motherboard's
DRAM. This is the approach that is applicable to all
levels of PC, from desktop to palmtop. For near-term
applications, however, RF A is an ideal way of making
code or ROM-executable operating systems such as
DOS or Windows' updatable to protect the end-user's
software investment. Also, when used as a resident ap-

plication program and data-file storage medium on the
local memory bus, RF A provides a high-performance,
low-power solution.
The Resident Flash Array provides the highest possible
performance of any option, especially since the processor can be closely coupled to it; and hence, would not
be encumbered by IDE or PCMCIA interfaces, or even
the ISA bus itself. The flash memory and the processor
will sit side-by-side.
The proliferation of flash memory card-based systems
will accelerate the process of converting disk-oriented
applications to a flash-eXecutable orientation. Those
manufacturers who elect to be early adopters of Intel
FlashFile memory will be able to develop a new generation of PC-the truly "personal" computer you can
hold in your hand,
NOTE:
ETOX, ExCA and FlashFile are trademarks of Intel
Corporation.
'Microsoft and MS-DOS are registered trademarks;
Windows is a trademark of Microsoft Corporation.
'Lotus and 1-2-3 are registered trademarks of Lotus
Development Corporation.

Ii
I'.

6-225

I
Intel ExCi\M Hardware Developer' sKit
Product Brief
Kit _ 1 PC·AT· Add·in Board with
Contents 2 PCMCIA sockets
_ ExCA Hardware Developer's
Kit User's Guide
_ Technical documentation
describing Intel's Series 2 Flash
Memory Card and FlashFile™
Components
_ A copy oflntel's ExCA
Specification
_ An evaluation copy of
Microsoft's* Flash File
System Software
_ iCardrv1.exe - Intel's Low
Level Driver Software
_ 8236SSL Diagnostic Software

Intel's ExCATM Hardware Developer's Kit provides the mobile computer
designer with the hardware, software and system interface to evaluate the
benefits of Intel's Series 1 and Series 2 Flash Memory Cards. This kit will
allow your design to be flash card ready, completing the evaluation, using
your Series 1 or Series 2 cards. An ExCA add· in board in an IBM PC-AT*
desktop PC using MS-DOS* serves as the development platform.
Intel's ExCA Hardware Developer's Kit product number for ordering is
EXCAHWEBD

Kit Description
A PC-AT add-inboard based on ExCA hardware, two PCMCIA slots, Microsoft's
Flash File System arid associated Flash driver, diagnostic software and Intel's ExCA
Specification, provides a hands-on evaluation/development tool for flash ready
mobile computer designs.
The Kit User's Guide,provides hardware and software installation instructions and
advice on how to maximi~e kit usage.
This kit will enable systems designers to:
I. Familiarize yourself with Intel's Exchangeable Card Architecture
2. Use your Series I and Series.2 cards in a PC-AT system.
3. Plan your next mobile computer design to be Intel Series I or Series 2 Flash Card
ready.
The ExCA Developer'S Board will accept software upgrades that allow the
integration of future Intel Flash Memory Cards as they become available.
=I<

ExCA and FlashFile are trademarks of Intel Corporation
Other brands and names are the property of their respeitive owners.

Order Number: 297293-002

6-226

intel~

Flash A TA Drives

Iil
Flash Drive
iFD005P2SAli FD01 OP2SA

•
mW Idle, Standby, and Sleep
• 10Power

•
Flash Memory Cycle
• Embedded
Management

• 5 MB/s Interface Transfer Rate
• 1000G Shock
• Four PCMCIA-ATA Modes
• IDE-ATA Mode
• Absolutely Silent
with Standard Data
• Compatible
Compression Utilities

• Weighs only 1 oz. (29 gms)
• Nonvolatile; No Batteries Required
• Single +5 Volt Supply
• 32-Kbyte Buffer
FlashFile™ Architecture
• Uses
ETOXTM III 0.81J Flash Memory

PCMCIA-ATA Type-2 PC Card

5 and 10-Mbyte versions

Technology

Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit
patent lic!!nses are implied. Information contained herein supersedes previously published specifications on these Intel devices.
@INTELCORPORATlON, 1993
October 1993
Order Number: 290492-001

I
'P'

'i,

I
II~,',~,

Flash Drive iFD005P2SAliFD010P2SA

. INTRODUCTION
Intel's Flash Drive brings FlashFile™ memory's
mass storage advantages to PCMCIA-ATA and
IDE-ATA-equipped mobile computers.
These
nonvolatile storage products provide performance,
ruggedness, reliability, silent operation, and
extended battery life that these systems need.

Its proprietary energy-saving modes can double
system battery life.
Unlike disk drives that
consume substantial disk-spinning and headpositioning power, the flash drive's solid state
circuitry uses power only when managing and
transferring data.

In default mode, the flash drive operates in
PCMCIA-ATA compliant sockets. It conforms to
PCMCIA PC Card standard 2.01, or higher (with
ATA version 1.01 or higher hardware and software).

Spinup, seeks, and rotational latency, which
su~stantially degrade hard disk drive performance,
are virtually non-existent in the flash drive. This,
coupled with 5-MB/sec interface and 8-MB/sec
read-media transfer rates, makes it the highest
performance ATA drive available.

Its IDE-ATA auto-detect mode allows it to operate
in standard IDE hardware- and BIOS-equipped
systems (with 68-pin connector).
It uses the
industry-standard ATA command set so no
software drivers are required.
PCMCIA and
ATA power management
commands are supported. In addition, automatic
power management reduces power without
system intervention. Its instant-on capability allows
it to enter a power-down mode when not active; this
reduces power to less than 10 mW.

The PCMCIA Type-2 profile maintains interface
compatibility with Type-3 1.8" PCMCIA- and IDEATA magnetiC hard disk drives; at only half the
thickness and half the weight. And, its solidstate construction, embedded flash memory
management, 1000G shock speCification, builtin ECC, and flash memory's inherent reliability
provide maximum data Integrity.

1~111I#1

15##1111#1
15##1111#1
Flash
Array

1,.........,1#t~II,...:....,1#t~1

11#111#1

[l]rrnnJ
Controller

SARA_Bl..K.DS4.WMF

Figure 1. The Flash Drive's Block Diagram

7-2

infel~

Flash Drive iFD005P2SAliFD010P2SA

SPECIFICATION SUMMARY
Capacity (CHS Auto-Translate)
Formatted
Bytes (cylinders, heads, sectors)
iFD005, 5M
5,242,880 (160, 2, 32)
iFD010, 10M
10,485,760 (320, 2, 32)

Environmental
Temperature
Operating
O°C to 60°C
Non-operating
-30°C to +70°C
Humidity, Operating
(non-cond, 26°C wet bulb) 5% RH to 95% RH
Altitude, Operating
-60m to 12Km
(-200 tt to 40K tt)

Power (see DC specifications for details)
Read
Write
Idle
Standby
Sleep mode
Peak current
(programming voltage start-up)
Supply Voltage

Performance
Seek Time (maximum or track-to-track) ,< 1 ms
Rotational Latency
Oms
Spinup Time
Via Command (from deep power-down) 10ms
Power-on to ready
2.5s (max)
Media Transfer Rate
8.0 MB/s
Read
Write
.27 MB/s
Interface Transfer Rate (burst)
5.0 MB/s
Buffer Size
32KB

0.7A
5.0V ±5%

Reliability
MTBF
(TA = 25°C)

Interfaces
68-pin PCMCIA-ATA
PCMCIA PC Card Standard, Release 2.1
PCMCIA PC Card ATA Specification 1.02
68-pin IDE-ATA
1.8" disk-drive-type ATA
ATA Interface for Disk Drives Standard 4A

0.5W
0.7W
0.010W
0.010W
0.010W

250K power-on-hours
(25KB write every 5 minutes)
5M power-on-hours (typical)

Read Error Rate
(with retries and ECC)
1 in 10 14 bits read
ECC (optimized for flash memory) 32 bits/sector

Ruggedness (any axis or direction)
Shock, op/non~operating
Vibration,op/non,operating

Size

1000G
>15 G, 10-500 Hz

85.6mm x 54.0mm x 5.0mm
(3.37" x 2.126" x 0.196")

Weight

Noise Absolutely silent operation

29gms
(1.05 oz.)
OSPL

(Sound Pressure Level)

7-3

infel®

Flash Drive iFD005P2SA/iFD010P2SA

PHYSICAL CHARACTERISTICS
Intel's Flash Drive has one surface·mount oircuit
board. Dimensions and physical characteristics are
industry·stahdard PCMCIA and 68-pin IDE·ATA
disk drive compatible.

RELIABILITY
Non-Recoverable Error Rate
Minimum error rate is 1 error per10 14 bit-reads with
retries and error correction enabled (typically 1
error in 10 17). Correctable defects are not included.

Mean Time Between Failures (MTBF)
Mean time between failure (MTBF) estimates the
time between physical repair or faulty-part
replacement to restore a unit to full functionality. It
is the reciprocal of failure rate during useful life,
when failures are random and the .failureoccurrence rate is constant. Flash drive MTBF
calculations incorporate flash cycling to give a
clearer comparison to magnetic hard disk drives.
MTBF conditions:
(TA = 25°C)
Environment:
25KB write every 5 minutes over 250,000 hours
on 10-Mbyte drive.

Error Correction
The 32-bit error correction code can correct one
error burst (8 bits maximum) per 512-byte sector.

Preventive Maintenance
No preventive maintenance is required.

LOW-POWER APPLICATIONS
The flash drive's low-power modes make it ideai for
battery. based applications.
• Self-Initiated deep power-down mode places
non-critical circuitry, including the flash array and
programming power unit, into a power-down
mode (which is transpar.ent to the host) when the

7-4

drive detects no activity. The drive powers up
and responds to a host command within 10 ms.

• Idle or standby commands initiate ,Idle or
Standby modes. If requested by tMhost, the
drive places itself in idle mode for about 1.5
seconds. If no activity is detected, it transitions
to standby mode, which is identical to its sleep
mode (or deep power-down mode). The drive
wakes.upon receiving any Command.
• Host-initiated Sleep mode places all flash drive
circuitry in a power-down state when the host
executes a set sleep mode command.
A
hardware or software reset brings the drive out of
sleep mode.

PCMCIA-STANDARD.COMPATIBILITY
Intel's Flash Drive is compatible with PCMCIA PC
Card Standard, Release 2.1.
To obtain this
specification, write to:
PCMCIA
1030G East Duane Avenue
Sunnyvale, Ca 94086
Tel: (408) 720-0107
. Fax: (408) 720-9416

ATA-STANDARD & COMPATIBILITY
The flash drive is compatible with the "ATAttachment Interface for Disk Drives" draft proposal
Revision 4A. See the intemal working document
X3T9.2,a Task Group of Accredited Standards
Committee X3 of the American National Standard
for Information Systems and the AT Attachment
Specification for detailed information. To obtain
this specification, write to:
AT-Attachment Document Distribution
Global Engineering
15 Inverness Way East
Englewood, Co. 80112-5704
Tel: (800) 854-7179 or (303)792-2181
Fax: (303) 792-2192

Flash Drive Physical Dimensions
Figure 2 shows the drive's 68-pin PCMCIA Type-2
memory-card case dimensions.

infel~

Flash Drive iFDO05P2SAliFD010P2SA

CONFIGURATIONS

PCMCIA·ATA Modes

The flash drive has five addfessing configurations
that allow system designers to tailor hardware and
software for system requirements.
These
configurations, describecllater, are:

• Memory Mode (2-KByte contiguous memory
space)
• Independent 1/0 (16 contiguous 1/0 addresses)
• Primary Drive Address (1 FO-1 F7, 3F6 & 3F7)
• Secondary Drive Address (17Q-1n, 376 & 3n).

1.8" AT·Attachment (IDE) Mode
• 68-pin IDE-ATA disk drive emulation.

1.00

{
i

1\135

#68 gg #34
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

100

! ~
--=r=
1 L5
"« "«L5
t>
('Of9 ) (.394)

(.063)

3.0

(.118)

54.0
(2.126)

(
~
0
w
z
z

0
0

.r:

Z
Z

IUJ
::l
UJ

1~0 ~
(.394)

~~.oo

(.039)

SUrfaceA~

85.60
(3.370)

5.00
(.196)

3.30

i t

(.130).t---=rf~1====I'o;;;;::==========~:I
NOTE: (Inches in parenthesis)
Figure 2. Flash Drive Dimensions

-7-5

Flastl.Drive iFD005P2SAIIFD010P2SA

PCMCIA

Memory, 110

Signa'·

1
2
3
4
5

6
7
8
9
10
11
12
13
14
15
16
17
18
19

20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

PCMCIA·
ATA
Mode

Table 1 Flash Drive Pinout
Pin PCMCIA
IDE·ATA Notes
Mode
Memory, I/O
Signal

GNO
GNO
GNO
03
03
H03
04
04
H04
Os
Os
HOs
Os
De
HOe
07
07
H07
CE1#
CE1#
HCSO#
AlO
Al0
N.U.
OE#
OE#
IDE_DEn
N.C.
An
N.C.
A9
N;U.
A9
As
Ae
N.U.
A13
N.C.
N.C,
A14
N.C.
N.C.
WE#/PGM#
WE#
N.C.
ROY/BSY#I ROY/BSY#I HIRQ
IREQ#
IREQ#
Vee
Vee
Vee
VPPl
N.C.
N.C.
N.C,
Ale
N.C.
N.C.
A1S
N.C.
A12
N.C.
N.C.
A7
A7
N.U.
Ae
As
N.U.
As
As
N.U.
A4
N.U;
A4
As
Aa
N.U.
A2
A2
HA2
Al
HAl
Al
Ao
Ao
HAo
Do
Do
HOo
01
01
HOl
02
H02
02
WP/lOIS16# WPIIOIS16# HI016#.
GNO
GNO
GNO

2
6

1
2
2
1
1
1
5
1
1
1
1
2
2
2
2
2

Notes:
1. N.C. = Not connected intemally.
2. N.U. = Not Used. Connected intemallybut not used in
specified mode.
3. D.U. = Don't Use in specified mode; intemally driven.

7-6

35
36
37
38
39
40
41
42
43

GNO
C01#
On
012
013
014
01S
CE2#
RFSH#
IORO#
44
IOWR#
45
46
Au
Ale
47
48
Ale
49
A20
50
A21
51
Vee
VPP2
52
A22
53
54
A23
55
A24
56
A25
57 Reserved
58
RESET
WAin
59
60 INPACK#
REG#
61
62
BV02
63 . BV011
STSCHG#
64
De
09
65
66
010
C02#
67
GNO
68

PCMCIA·
ATA
Mode

IDE-ATA Notes
Mode

GNO
C01#
011
012
013
014
015
CE2#
N.C.
IORO#
IOWR#
N.C.
N.C.
N.C.
N.C.
N.C.
Vee
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
RESET
WAIT#
INPACK#
REG#
Pullup
STSCHG#

GNO
GNO
HOll
H012
H013
H014
H015
HCS1#
N.C.
HIOR#
HIOWR#
N.C.
N.C.
N.C.
N.C.
N.C;
Vee
N.C.
N.C.
N.C;
N.C.
N.C;
N.C.
HRST#
O.U.
HOREQ
HOACK#
HOASP#
HPOIAG#

De
09
010
C02#
GNO

HOe
HOe
H010
GNO
GNO

1
1
1
1
1
1
1
1
1
1
1
1
5
3

4. CD1# and CD2# are internally pulled low with 470 ohm
resistors.
5. PCMCIA-ATA RESET and IREO# polarities are
. inverted to form HRST# and HIRO in IDE-ATA mode.
S. IDE-ATA sockets ground this signal. This Signal is
used during reset to determine PCMCIA-ATA or IDEATA configuration.

intet
Symbol

Flash Drive iFD005P2SAliFD010P2SA
rive Pm Description
Table 2. Flash D'
Direction Description

1/0

HDo-15

1,34,35,
68
2-6,3032,37-41,
64-66

CE1#

8,
10-14,
19-29,
46-50,
53-56
9

WE#

RDY/BSY#

GND
DO-15

Ground between the host and drive.

HCSO#
AO-24

HAo-3
OE#

IDE_DET#

HIRQ

Vee
VPP1,VPP2
WP/I0IS16#

17,51
18,52
33

I
N.C.
0

36,67

N.C.

H1016#

CD1#, CD2#
CE2#
HCS1#
RFSH#

PCMCIA-ATA mode: 16-bit bi-directional data bus between the
host and drive.
IDE-ATA mode: Register and ECG accesses use DO-7. Data
transfers use 00-15.
PCMCIA-ATA mode: Card Enable 1 enables even data bytes on
00-7 (see table 3 for detailed description).
IDE-ATA mode:
IDE-ATA Host Chip Select 0 accesses
command block reQisters.
PCMCIA-ATA Mode: Addresses AO-10 access data and registers
depending on the memory or 1/0 mode chosen by the host (see
table 3). Addresses A11-24 are not used.
IDE-ATA mode: Only addresses AO-2 are used (see table 3).
PCMCIA-ATA mode: Output Enable used to read attribute- and
memory-mode data onto 00-15.
IDE-ATA mode:
Detects IDE-ATA mode when externally
Qrounded durinQreset (see table 3).
PCMCIA-ATA mode: Active-low Write Enable used to write
attribute- and memory-mode data that is on 00-15.
IDE-ATA mode: Not used.
PCMCIA-ATA mode: Indicates Internally timed activities status.
Drive can accept host accesses when hiQh.
IDE-ATA mode: Host enables Interrupt Request only when drive
is selected and the host activates the Digital Output register's
IEN#. HIRQ (a three-state pin) is high-Z when IEN# is inactive or
the drive is not selected. HIRQ is set when the drive's CPU sets
IRQ. HIRQ resets during Status register read or Command
register write.
+5 Volt DC supply to the drive.
+ 12 Volt DC proQramminQ supply is not required.
PCMCIA-ATA mode:
Held low after the reset initialization
sequence (Write Protect is not supported).
IDE-ATA mode: Host 1/0 16 tells the host that the data register
was accessed and the drive can send/receive 16-bit data.
H1016# is a three-state pin.
Card Detect pins, internally pulled low with 220n resistors, allow
the host to determine that the drive is fully inserted in the socket.
PCMCIA-ATA mode: Card Enable 2 enables odd data bytes on
08-15 (see table 3).
IDE-ATA mode: Host Chip Select 1 selects drive control block
registers.
Not used.

7-7

Fla$hDriveiFD005P2SAliFD010P2SA

Symbol
IORD#

Pin
44

HIOR#
I/OWR#

HIOW#
Reserved
RESET

57
58

HRST#
WAIT#

INPACK#

HDREQ
REG#

HDACK#
BVD2
HDASP#

BVD11
STSCHG#
HPDIAG#

Table 2. Flash Drive Pin Description (Continued)
Direction Description
PCMCIA-ATA mode: Active-low 1/0 Read gates data onto DO,15
I
.during I/O-mode accesses.
IDE.-ATA mode: Host 1/0 Read enables drive register data onto
HDo-15. The host latches drive data on HIOR#'s rising edge.
I
PCMCIA-ATA mode: Active-low 1/0 Write gates data from DO-15
duringl/O-mode accesses.
IDE-ATA mode: Host 1/0 Write's rising edge strobes data into a
drive register.
N.C.
Reserved.
I
PCMCIA-ATA mode: At power-on or hardware reset, this activehioh sional resets all drive reoisters.
IDE-ATA mode:· At power-on or hardware reset, this active-low
sionai resets all drive registers.
0
PCMCIA-ATA mode: The drive's WAIT# signals the host that the
in-progress memory or 1/0 cycle is not complete.
IOE:-ATA mode: Do not connect.
PCMCIA-ATA mode: When . selected, the drive asserts Input
0
Acknowledge while respondino to an 1/0,read cycle.
IDE-ATA mode: Host DMA Request is not supported.
I
PCMCIA-ATA mode: Common memory is accessed when high.
Attribute memory and ATA r~isters are accessed when low.
IDE-ATA mode: HDACK# is not sUpported.
0
PCMCIA-ATA mode: 10K Pull up to Vee.
IDE-ATA mode: Orive-Active/Second-Present drives an LED
when the disk is accessed. This open-drain output is pulled up
with a 10K-ohm resistor.
1/0
PCMCIA-ATA mode: Notifies the host of RDY/BSY# and Write
Protect state charmes.
IDE-ATA mode:
In· slave mode (not supported), Passed
Diagnostics (low) tells a master that diagnostics.was passed. In
master mode, it is an input.

* Note: All pin directions are referenced to the dnve.

7-8

intel~

Flash Drive iFD005P2SAliFD010P2SA

Table 3 Data Access Mode Truth Table
COMMON MEMORY PLANE
Function
ADDR
RIW REG# CE2# CE1# OE# WEI IORD# IOWRM
Standby
Byte
Odd-Byte
Word
Byte
Odd-Byte
Word

Ao=X1
Ao=L
Ao=H
Ao=X
Ao=X
Ao=L
Ao=H
Ao=X
Ao=X

Read

Write

015-8

07-0

X
H
H
H
H
H
H
H
H

High-Z
High-Z
High-Z
Odd-Byte
Odd-Byte
X
X
Odd-Byte
Odd-Byte

Hloh-Z
Even-Byte
Odd-Byte
Hioh-Z
Even-Byte
Even-Byte
Odd-Byte
X
Even-Byte

X
H
H
H
H
L
L
L
L

X
H
H
H
H
H
H
H
H

X
.H
H
H
H
H
H
H
H

High-Z
Hiah-Z
High-Z
Invalid
Invalid
X
X
Invalid
Invalid

Hioh-Z
Even-Byte
Invalid
Hioh-Z
Even-Byte
Even-Byte
Invalid
X
Even-Byte

Hiah-Z
Invalid
Data High
Data Hiah
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid

Hiah-Z
Invalid
Data Low
Data Low
Error
Feature
Sect. Cnt.
Sect. Cnt.
Sect. No.
Sect. No.
Cyl. Low
Cyl. Low
Cyl. High
Cyl. Hioh
. Drv/Hd
Drv/Hd
Status
Command
Invalid
Alt. Status
Control
Drv. Add.
Not Used

X
H
H
H
H
H
H
H
H

H
H
H
L
L
H
H
L
L

H
L
L
H
L
L
L
H
L

X
L
L
L
L
H
H
H
H

X
H
H
H
H
L
L
L

X
L
L
L
L
L
L
L
L

H
H
H
L
L
H
H
L
L

H
L
L
H
L
L
L
H
L

ATTRIBUTE MEMORY PLANE
Standby
Byte
Odd-Byte
Word
Byte
Odd-Byte
Word

Ao=X
Ao=L
Ao=H
Ao=X
Ao=X
Ao=L
Aa=H
Ao=X
Ao=X

IDE-ATA MODE (Primar~
No Operation
Invalid
Data

X
X

Error
Set Feature
Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive/Head

Status
Command
Invalid
Alternate Status
DJive Control
Drive Address

7
0-5
6
7

Read

Write

L
L
L
L
H
H
H
H

= 1FO-1F7 3F6-3F7- Secondary = 170-177. 376-3n)2
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write

X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

H
L
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H
L
L
L
L
L

H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H

X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

X
X
H

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
H
H
H

X
X
L
H
L
H
L
H
L
H

L
H
L
H
L
H
L
H
X
L
H
L
H

X
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
H
L
H
L

7-9

I
r

Flash Drive iFD005P2SAliFD010P2SA
Table 3. Data Access Mode Truth TableJContinued)
PCMCIA·ATA MODE (Independent 1/0 address xxO-xxF)3
Function
ADDR
R/W REG# CE2# CE1# OE# WEi 10RD# 10WR#
No Operation
X
X
H
H
X
X
X
X
H
X
X
X
X
X
X
'H
0
Read
L
L
L
H
H
L
Data
Write
L
L
L
H
H
H
L
Error
1
Read
L
H
L
H
H
L
H
L
L
H
H
H
L
H
Set Feature
Write
L
H
L
H
H
H
L
L
L
H
H
H
H
L
Sector Count
2
Read
L
X
L
H
H
L
H
Write
L
X
L
H
H
H
L
Read
L
H
H
L
Sector Number
L
H
H
3
L
H
L
H
H
L
hi
Write
L
H
H
H
H
L
L
,
L
L
H
H
H
H
L
Cylinder Low
4
Read
L
X
L
H
H
L
H
Write
L
X
L
H
H
H
L
Cylinder High
Read
L
H
L
H
H
L
H
5
L
H
H
H
L
H
·L
Write
L
H
H
H
L
H
L
L
L
H
H
H
H
L
Drive/Head
6
Read
L
X
L
H
H
L
H
Write
L
X
L
H
H
H
L
Status
7
Read
L
H
H
H
L
L
H
L
L
H
H
H
L
H
Command
Write
L
H
L
H
H
H
L
'H
L
L
L
H
H
H
Data (duplicate)
H
8
Read
L
X
L
L
H
H
(see note 6)
Write
L
X
L
H
H
H
L
H
H
9
Read
L
H
L
L
H
L
L
H
H
H
L
H
Write
L
H
L
H
H
H
L
L
L
H
H
H
H
L
A-C
Invalid
L
X
X
X
X
X
X
Error (duplicate)
D
Read
L
H
L
H
H
L
H
L
L
H
hi
H
H
L
Write
L
H
L
H
H
H
L
L
L
H
H
H
H
L
Alternate Status
E
Read
L
X
L
H
H L
H
Drive Control
Write
L
X
L
H
H
H
L
Drive Address
F
Read
L
H
L
H
H
L
H
L
L
H
H
H
L
H
Write
L
H
L
H
H
H
L
L
L
H
H
H
H
L

7-10

015.8

High-Z
High-Z
Data High
Data High
Invalid
Error
Invalid
Feature
Invalid
Invalid
Invalid
Sect. No.
Invalid
Sect. No.
Invalid
Invalid
Invalid
CyL High
Invalid
Cyl. High
Invalid
Invalid
Invalid
Status
Invalid
Command
Invalid
Invalid
Invalid
Data High
Invalid
Data High
lilValid
Invalid
Error
Invalid
Feature
Invalid
Invalid
Invalid
Drv. Add;
Invalid
Not Used

07.0
High-Z
High-Z
Data Low
Data Low
Error
Invalid
Feature
. Invalid
Sect. Cnt.
Sect. Cnt.
Sect. No.
Invalid
Sect. No.
Invalid
Cyl. Low
Cyl. Low
Cyl. High
Invalid
Cyl. High
Invalid
Drv/Hd
DrvlHd
Status
Invalid
Command
Invalid
Data Low
Data Low
Data High
Invalid
Data High
Invalid
Invalid
Error
Invalid
Feature
Invalid
Alt. Status
Control
Drv. Add.
Invalid
Not Used
Invalid

infel~

Flash Drive iFD005P2SAliFD010P2SA

Table 3. Data Access Mode Truth Table (Continued)
PCMCIA-ATA MODE (Independent Memory address =OOO-OOF, 400-7FF)4
Function
ADDR
RIW REG# CE2# CE1# OE# WEI IORD# IOWRtj
No Operation
X
X
H
H
X
X
X
X
L
X
X
X
X
X
X
Data .
000
Read
H
L
L
L
H
H
H
Write
H
L
L
H
L
H
H
001
Read
Error
H
H
L
L
H
H
H
H
L
H
L
H
H
H
Set Feature
Write
H
H
H
L
H
L
H
H
L
H
H
L
H
H
Sector Count
002
Read
H
X
L
L
H
H
H
Write
H
X
L
H
L
H
H
Sector Number
003
Read
H
H
L
H
H
L
H
H
H
L
H
L
H
H
Write
H
H
L
H
H
H
L
H
L
H
H
L
H
H
Cylinder Low
004
Read
H
X
L
L
H
H
H
Write
H
X
H
H
L
H
L
Cylinder High
005
Read
H
H
L
L
H
H
H
H
L
H
L
H
H
H
Write
H
H
H
H
L
H
L
H
L
H
H
H
H
L
Drive/Head
006
Read
H
H
X
L
L
H
H
Write
H
X
L
H
L
H
H
Status
007
Read
H
H
L
L
H
H
H
H
L
H
L
H
H
H
Command
Write
H
H
H
L
H
L
H
H
L
H
H
H
H
L
Data (duplicate)
008
Read
H
X
L
L
H
H
H
(see note 6)
Write
H
X
H
H
L
H
L
009
Read
H
H
L
L
H
H
H
H
L
H
H
H
L
H
H.
Write
H
H
L
H
L
H
H
L
H
H
H
H
L
Invalid
OOA-OOC
H
X
X
X
X
X
X
Error (duplicate) OOD
Read
H
H
H
L
L
H
H
H
L
H
L
H
H
H
Write
H
H
L
H
H
H
L
H
H
H
L
H
H
L
Alternate Status OOE
H
Read
X
L
H
H
H
L
Drive Control
Write
H
X
L
H
H
H
L
Drive Address
OOF
Read
H
H
L
L
H
H
H
H
L
H
L
H
H
H
Write
H
H
L
H
H
H
L
H
L
H
H
L
H
H
Data (duplicate) 400-7FF Read
H
L
L
L
H
H
H
(see note 7)
Write
H
L
H
H
L
H
L

015-8

High-Z
Hioh-Z
Data High
Data High
Invalid
Error
Invalid
Feature
Invalid
Invalid
Invalid
Sect. No.
Invalid
Sect. No.
Invalid
Invalid
Invalid
Cvl. High
Invalid
Cyl. High
Invalid
Invalid
Invalid
Status
Invalid
Command
Invalid
Invalid
Invalid
Data High
Invalid
Data High
Invalid
Invalid
Error
Invalid
Feature
Invalid
Invalid
Invalid
Drv. Add.
Invalid
Not Used
Data High
Data Hioh

07-0
High-Z
Hioh-Z
Data Low
Data Low
Error
Invalid
Feature
Invalid
Sect. Cnt.
Sect. Cnt.
Sect. No.
Invalid
Sect. No.
Invalid
Cvl. Low
Cyl. Low
Cyl. High
Invalid
C.YI. High
Invalid
Drv/Hd
Drv/Hd
Status
Invalid
Command
Invalid
Data Low
Data Low
Data Hioh
Invalid
Data Hioh
Invalid
Invalid
Error
Invalid
Feature
Invalid
Alt. Status
Control
Drv. Add.
Invalid
Not Used
Invalid
Data Low
Data Low

7-11

I,.

Flash Drive iFD005P2SAliFD010P2SA
Table 3•. Data Acc~ss Mode Truth Table (Continued)
PCMCIA-ATA MODE (Primary address = 1FO-1F7, 3F6-3F7;Secondary address .. 110-177 3760377)5
Function
ADDR
R/W REG' CE2# CE1# OE# WE; IORDI IOWRII D15-8
D7-o
No Operati0r'
,x
,X
H
H
X
X
X
X
Hiah-Z
Hiah"Z
H
X
X
X
X
X
X.
High-Z
High-Z
Data
1F~170~R~e=a=d~'~=L~~=L~__~L~~H~~H~~~L~~H~~D~a=ta~H~li~glh~D~a~ta~Lo~w~
Write
L
H
L
H
H
H
L
Data Hiah Data Low
Error
1F1/111 Read ~=L~~X~.·-+--=L::,;,.·-+.,:H'-'-f--'H-=-r--,::.L~--=H-=-+-.:':lh=::-va=l:.::id-+--=E::.:.rr;.,;:o.:':r-l
L
L
H
H
H
L
H
Error
'Invalid
Set Feature
Write I-.::L'--I-.:.:X'--1I-:=L--lr--:-H.!....1r--:-H..:.....I-:..:H_·+-7L--l-=ln:,!;v:.:a~lid=--~F:-=e=a:t==:u::-:re:..;
L
t
H
H
H
H
L
Feature
Invalid
Sector Count
1F~172~R~e=a=d~.,:L=--+-~X~r-.::L~~H~~H~~L=--+-~H~~I~nv~a=lid=--¥S~e:.:c~t.:.::C~n~t.
L
X
L
H
H
H
L
Invalid Sect. Cnt.
Write
L
X
L
H
H
'L
H
Invalid Sect. No.
Sector Number 1F3I173 Read
L
L
H
H
H
L
H
Sect. No.
Invalid
H
H
L
Invalid Sect. No.
L
X
L
H
Write
L
L
H
H
H
H
L
Sect. No.
Invalid
Cylinder Low
1F4/174 ~R:..;.e~a::;:d~....;L::..-+~X~r--=L'-I~H~....:.H~--=L=-+-~H~t--'I.:.:.nv~a=li.:;.d-I-.;;;;C"",yll,,-.L:;:.;O:..;.w:..;
L
'X
L
H. H
H
L
Invalid
Cyl.- Low
Write
L
X
L
H
H
L
Hlnvalid Cyl. Hiah
1F5/175 Read
Cylinder High
L
L
H
H
H
L
H
Cyl. High
Invalid
Invalid Cyl. High
L
X
L
H
H
H
L
Write
L
L
H
H
H
H
L
Cyl. Hiah Invalid
Drive/Head
1,F6/176 ~R~e=a=d~_L=--+-.:.X,!--r-.::L.yf-'-!.H~~H~.....,.:L=--+-~H~~I~nv~a=li=-d-+...;D:,:rv,!,:lH.:,,:,:::d-l
Write
L
X
L
H
H
H
.L
Invalid
DrvlHd
Status
1F7/177 Read ~.::.L~--=X-=-+--=L=--f--'H-=-~H~I--~L-+--=H-=-+-::,:ln~va=li:.::d-+-=,Sta=tu:::s-l
L
L
H
H
H
.L
H
Status
Invalid
Command
Write
L
X
L
H
H
H,
L
Invalid Command
L
L
H
H
H
H
L
Command Invalid
Invalid
3F/370-5 RIW
L
L
H
X
X
X
X
Invalid
Invalid
Altemate Status 3F61376I-R:..:.e~a::;:d+...;.L~I--'X"'-+-_L::..-t~H~~H~__L=-+-..:H~+-.:;ln.:.:v-=a=lid=-1-'-A~lt,,-.S~t=a=tu'"'is
Drive Control
Write
LX· L
H
H
H
L
Invalid
Control
Driv9Address 3F7/377 Read
L
X
L
H
H
L
H
Invalid Drv. Add.
L
L
H
H
H
L
H
Drv. Add.
Invalid
Write
L
XL'H
H
H
L
Invalid Not Used
L
L
H
,H
H
H
L
Not Used Invalid
NOTES.:
1. X = don't care.
2. For AT-BIOS compatibility, a host adapter decodes
thes.e 110 addresses. The flash drive decodes address
lines Ao-2.
3. The host must d(:lcode addresses A4-l0 and provide
card enables CE1# and CE2# that place ihe drive on a
16-byte,boundary.. The drive decodes Ap-3.
4. The host must'decOde ilddresses above Al0 and
provide card enal1les CEl # and CE2# that place the
drive on a 2-Kbyte boundary.. The drive decodesAo-l0.

7-12

5. The drive. fully decodes thesE! addresses using
addresses AO-l0.
6. The drive operates in PCMCIA-ATA 16-bit data mode.
Its auto-incrementing datil register transfers Ii new data
word with. each access. Accessing address 008
presents word .X's low byte; accessing address 009
presents word X+ 1's high byte.
.
7. In independent memory mode, each 'access to '.
:addresses 400-7FF prliisent a new data-register word.
This allows sequential accesses of up to 1-Kbyte using
a single memory string-move instruction.

Flash Drive iFD005P2SAliFD010P2SA

,
I
'i

PCMCIA FUNCTIONS
Available card status information allows arbitration
between resources that share interrupts and
memory-only-card status of pins 16, 33, 62, and 63.
Table 4 describes these registers.

Attribute Memory Access
Attribute memory, which contains the card
information structure (CIS), holds socket, card
identification, and configuration information. The
host reads this information by asserting REG#-Iow,
CE1#-low, CE2#-high, OE#-Iow, WEI-high and
even-numbered addresses (AO=VIL) starting at
OOOOh. Table 3 shows PCMCIA signal levels for
accessing the attribute memory plane.

CONFIGURATION OPTION REGISTER

The host uses the read/write Configuration Option
register to configure the drive for one of its four
PCMCIA-ATA addressing modes, establish the
interrupt signal mode, and issue a soft reset.

In addition to device, interface, features, and
manufacturer information, the CIS conveys
information about the drive's four PCMCIA-ATA
configurations: independent I/O, independent
memory, primary, and secondary addressing
modes (described below).

SRST

Resets the card when 1. When 0
(default), the card is unconfigured,
similar to the state following hardware
reset or power-on (which also reset
this bit to 0) ,

IRQLvl

Selects level mode interrupts when 1;
pulse mode interrupts when 0 (default)

Conf lOX The host chooses an option from the
card's configuration table tuples and
writes that option's Configuration Index
number into this field. When zero
(default), the memory-only interface is
chosen; I/O accesses are disabled.

PCMCIA Card Configuration Registers
These read/write one-byte registers are located on
even-byte attribute~plane addresses to ensure
single-cycle access in both 8- and 16-bit systems.

Table 4. PCMCIA Card Configuration Registers Truth Table
Add. Offset* RIW REG# CE2# CE1# OE# WEI

Configuration Option

200h

Card Configuration and
Status
Pin Replacement

202h
204h

Socket and Copy

206h

Read
Write
Read
Write
Read
Write
Read
Write

Configuration Index

The host picks one mode that fits its hardware and
software requirements.
It writes the preferred
option's index number to the Configuration Option
register at card attribute memory address 200h.
The host can also read/write the Card Configuration
and Status, Pin Replacement, and Socket and
Copy registers at attribute memory addresses
202h, ~04h, and 206h.

765

L
L
L
L
L
L
L
L

H
H
H
H
H
H
H
H

L
L
L
L
L
L
L
L

L
H
L
H
L
H
L
H

H
L
H
L
H
L
H
L

015-8
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid

07-0
Option
Option
Status
ConfiQ.
Pin Status
Pin Status
Socket 10
Socket 10

Note. The host obtains the attribute-memory address offset from the Configuration Tuple's TPCC_RADR field when it reads·
the drive's CIS.

7-13

infel®

Flash Drive iFD005P2SAliFD010P2SA
STATUS

Crdyl
bsy#

Set when Rrdy/bsy# changes state
or when written by the host

The read/write Card Configuration and Status
register contains card condition information.

cwp

Set when written
otherwise zero

CARD
CONFIGURATION
REGISTER

AND

I Chng ISigChcllOiS81 0 IAudiol PwrDn I Intr I 0
Chng

The Change bit indicates that a Pin
Replacement register bit was set (1)

SigChg

The host sets/resets the Signal
Changed bit to enable/disable a statechange signal from the status register.
When set and the drive is' configured
for I/O, Chng controls pin 63 and is
called the Changed Status signal.
This bit should be 0 (BVD1/STSCHG#
held high when configured for I/O) if no
state change signal is desired

IOis8

This bit is ignored

Audio

Audio is not supported

PwrDn

Setting PwrDn places the drive in
sleep mode. Host-initiated ATA taskfile-register commands can also invoke
low-power modes
This bit represents the interrupt
request's internal state. Its value is
available whether or not. interrupts are
configured. It remains true until the
initiating-interrupt request is serviced.

PIN REPLACEMENT REGISTER

The read/write Pin Replacetnent register provides
card status information that is otherwise provided
on memory-only interface pins 16, 33, 62, and 63.
When written, bits 0-3 are masks for setting
. corresponding bits 4·7.

CBvd1,2 Set when

7-14

w~tten,

otherwise zero

the

host,

RBvd1,2 Cleared when written by the host,
otherwise set
RWP

Set when written by the host,
otherwise zero, since the flash drive
has no write protect switch.

SOCKET AND COPY REGISTER

The read/write Socket and Copy register allows the
drive to distinguish between similar drives at the
same address. The flash drive does not support
this feature.
7

Copy Number

Copy #

Intr

Socket Number

The twin-card option is not supported.
These bits are ignored

Socket # The socket number is ignored.
Memory and I/O transfers can be either 8 or 16 bits.
wide. The card asserts 101S16# when active I/O
addresses contain 16-bit data. The ATA data
register supports only 16-bit accesses. All other
ATAtask-file registers are 8-bit (see table 3 for
available modes).

IDE-AlA Mode
The host Ul:;es programmed I/O to address the
drive. To access a desired register, the host
asserts the drive's address lines (HAo.2), a drive
select (HCSO# or HCS1 #), and an I/O read or write
strobe (HIOR# or HIOW#).
The host· generates two interface drive selects.
The high-order sEllect, HCS1#, accesses registers
XX6 and XX7 (typically 3F6 and 3F7 or 376 and
377). The low order select, HCSO#, accesses
registers XXO-XX7 (typically 1FO-1 F7 or 170-177).

Flash Drive iFD005P2SAliFD010P2SA
H1016# indicates to the host that data bus HOS-15 is
active when it accesses the data register. ECC
transfers occur on bits HOo-7 only during read- or
write-long operations.

contents onto 00-7.
The hOst must decode
addresses above Al0 to place the drive on a 2Kbyte. memory boundary. The drive decodes
addresses AO-l0 as described in table 3.

PCMCIA-ATA Independent 110 Mode

101516# indicates to the host that data bus 00-15 is
active when it accesses the data register. ECC
transfers occur on bits 00-7 only during read- or
write-long operations.

Once the host configures the socket for PCMCIAATA independent I/O mode, it addresses the drive
using programmed I/O. To access a desired
register, the host asserts REG#, the drive's address
lines (AO-3), card select(s) (CE1# and/or CE2#), and
an I/O read or write strobe (IORO# or 10WR#).
The host generates two card selects. The highorder select, C52#, accesses high-byte data or
odd-register contents onto data lines OS-15. The
low-order select, C51#, accesses low-byte data or
even-register contents onto data lines 00·7.
Asserting both card selects while accessing the
data register. places high-byte data-register
contents onto OS·15 and low-byte data"register
contents onto 00-7.
The host must decode
addresses A4-10 to place the drive on a 16-byte1l0
boundary. The drive decodes addresses AO-3 as
described in table 3.
101516# indicates to the host that data bus 00-15 is
active when it accesses the data register. ECC
transfers occur on bits 00-7 only during read- or
.
write-long operations.

PCMCIA-ATA Independent Memory
Mode
Once the host configures the socket for PCMCIAATA independent memory mode, it uses memory
instructions and a memory window, within the
host's PCMCIA interface chip, to address the drive.
To access a desired register, the host de-asserts
REG#, asserts the drive's address lines (AO-l0),
card select(s) (CE1# and/or CE2#), and a read or
write strobe (OE# or WE#).

Primary or Secondary Address Mode
(1 FO-1F7, 3F6,3F7 or 170-177, 376, 377)
Once the host configures the socket for PCMCIAATA primary or secondary drive-address I/O mode,
it uses programmed 110 to address the drive. To
access a desired register, the host asserts REG#,
the drive's address lines (Ao-g), card select(s)
(CE1# and/or CE2#), and an 110 read or write
strobe (IORO# or 10WR#).
The host generates two card selects. The highorder select, C82#, accesses high-byte data or
odd-register contents onto data lines OS-15. The
low-order select, C81 #, accesses low-byte data or
even-register contents onto data lines 00-7.
Asserting both card selects while accessing the
data register places high-byte data-register
contents onto OS-15 and low-byte data-register
contents onto 00-7.
The host must decode
addresses above Ag to generate drive chip selects
when the primary (1 FO-1F7, 3F6, and 3F7) or
secondary (170-177, 376, and 377) drive-address
range is selected. The drive decodes addresses
Ao·g as described in table 3.
101816# indicates to the host that data bus 00-15 is
active when it accesses the data register. ECC
transfers occur on bits 00-7 only during read- or
write-long operations.
Table 3 defines all 1/0- and memory-mapped
register addresses and their functions.
ATA
register descriptions follow.

The host generates two card selects. The highorder select, C52#, accesses high-byte data or
odd-register contents onto data lines 01\-15. The
low-order select, C51#, accesses low-byte data or
even-register contents onto data lines 00-7.
Asserting both card selects while accessing the
data register places high-byte data-register
contents onto 08-15 and low-byte data-register
7-15

Flash DriveiFD005P2SAliFD01 OP2SA

ATA FUNCTIONS

ABRT

Drive status error or aborted invalid
command

In the following, unused read bits are "don't cares"
and unused write bits are zeros. The. data register
is 16-bits wide; all others are 8-bits wide.

TONF

Track 0 Not Found during a recalibrate
command

DATA REGISTER (READIWRITE)

AMNF

Address Mark Not Found after finding
the correct ID field.

Data· block PIO(programmed 1/0) transfers
between the drive's data buffer and the host use
this 16-bit register.
A format track command
transfers sector information through this register.

Unused bits are zero.

WRITE PRECOMP REGISTER (WRITE)
This register previously set write precompensation;
now it enables .look-ahead reads.

SECTOR COUNT REGISTER (READIWRITE)

ERROR REGISTER (READ)
The Error register contains la~t drive-commandexecuted status or a diagnostic code. At any .
command completion, - except execute drive
diagnostic, the Error register's contents are Villid
when the Status register's ERR is 1. It contains a
diagnostic code (see table 6) following power-on,
reset, or execute drive diagnostic command.

This register contains the number of data sectors to
be transferred during.a read or write operation. A
zero register value specifies 256· sectors: The
command was successful if this register is zero at
command completion.
If the request is not
completed, the register contains the number of
sectors left to be transferred.
Some commands (e.g. initialize drive parameters or
format track) may redefine this register's·contents.

76543210

I BBK I UNC I· MC IIDNFI MCR IABRTjTONFI AMNFI

I sC71 sC61 sC51 sC41 scal SC21 SC1 Isco I

BBK

Bad Block mark detected in the
requested sector's 10 field

UNC

Uncorrectable Data Error encountered

Removable Media Changed; media
access ability has changed -- not
supported

IDNF

Requested sector's ID-field Not Found

MCR

Media Change Request indicates that
the removable-media drive's latch has
changed, indicating that. the user
wishes to remove the media -- not
supported

7-16

SECTOR NUMBER REGISTER (READIWRITE)
In CHS (cylinder, head, sector) mode, this regi~ter
contains the subsequent command~s starting sector
number. The sector number can be from 1 to the
maximum number of sectors per track; See the
command descriptions for register contents at
command completion (whether successful or
unsuccessful).
in LBA (logical block address) mode, this register
contains LBA bits 0-7. It reflects updated LBA bits
0-7 at command completion.
7

ISN71 SN61 SN51 SN41 SN31 SN21sN1 I SNO

intel~

Flash Drive iFD005P2SAliFD010P2SA

CYLINDER LOW REGISTER (READIWRITE)

STATUS REGISTER (READ)

In CHS mode, this register contains the current
cylinder number's low-order 8 bits at any disk
access start or at command completion.

This register contains drive status, which is updated
at each command's completion. When BSY is
cleared, register bits are valid within 400 nsec. If
set, no other Status register bits are valid. A host
read, while interrupt is pending, constitutes interrupt
acknowledge which clears any pending interrupt.

in lBA mode, this register contains lBA bits 8-15
and reflects their status at command completion.
76

I Cl71 Cl61 CL51 CL41 CL3I CL2I CL1 I CLO

76543210

I BSY IDRDY!DWFI DSC IDROlcORRllDXI ERR!
BSY

CYLINDER HIGH REGISTER (READIWRITE)

In CHS mode, this register contains the current
cylinder number's high-order 8 bits at any disk
access start or at command completion.
in LBA mode, this register contains lBA bits 16-23
and reflects their status at command completion.

within 400 nsec after HRST# negation
or after setting the Device Control
register's SRST. Following reset, the
drive sets BSY for up to 31 seconds

76543210

within 400 nsec of host command:
read, read long, read buffer, seek,
recalibrate, read verify, initialize drive
parameters, identify drive, execute
drive diagnostic

DRIVE/HEAD REGISTER (READIWRITE)

This register contains the drive and head numbers
(heads minus 1, when executing an initialize drive
parameters command).
7

The drive can access command block
registers (the host should not access
them) when set; any command block
register read returns the Status
register contents. The drive sets BSY:

within 5 Ilsecs after a 512 byte write,
format track, or write buffer command
or data-plus-ECC write long command

I DRV I HS31HS21 HS1 I HSO!

Address mode select.
O=CHS
(cylinder, head, sector) mode; 1=lBA
(logical block address) mode

DRV

Binary drive select number; DRV=O
selects drive 0, DRV=1 is ignored (on
HDDs this bit selects drive 1)

HS3-0

If l=O: HS3-0 is the selected head's
binary coded address (e.g. if HS3-0 is
0011 b, head 3 is selected).
At
command completion, these bits
reflect the currently selected head
If l=1: HS3-0 contain lBA bits 24-27
and reflect their status at command
completion.

DRDY

Drive Ready indicates that the drive
can respond to a command. On error,
DRDY changes only after the host
reads the Status register; the bit again
indicates drive readiness. Power-on
clears this bit; it remains clear until the
drive can accept a command

DWF

Drive Write Fault status. On error, it
changes only after the host reads the
Status register; the bit again indicates
the current write fault status

DSC

Drive Seek Complete indicates that the
requested sector was found. On error,
it changes only after a host Status
register read; the bit again indicates
the current seek complete status

7-17

Flash DriveiFD005P2SAliFD01 OP2SA
ORO

Data Request indicates that the drive
can transfer a data word or byte

High-Z

For floppy
drive address-space
compatibility, bit 7 is not driven (it is
high-Z) when this register's address is
accessed. This allows a floppy-drive's
disk-change bit to provide bit 7 data

CORR

Indicates that a data error was
Corrected; transfer is not terminated

lOX

,Index is not used

WTG#

Write Gate bit is active during inprogress disk writes

ERR

An Error occurred during the previous
command's execution. The Error
register indicates the error's cause.

HSs-o#

Ones complement of the currently
selected head number. For example,
head 3 is selected if HSs-o is 11 OOb

DS1#

Drive Select 1 is low when drive 1 is
selected and active (not supported)

DSO#

Drive Select 0 is low when drive 0 is
selected and active.

COMMAND REGISTER (WRITE)

. E:xecution commences when this register receives
Table 5 lists executable
a host command.
command codes and indicates valid parameters.
ALTERNATE STATUS REGIST.ER (READ)

AT-ATTACHMENT COMPATIBILITY
This register contains command block Status
information (see Status register). Unlike reading
the Status register, reading this register does not
acknowledge or clear an interrupt.
7

0.5%
o = disk transfer rate> 10 Mbs

1 = disk transfer rate> 5 Mbs but <= 10 Mbs

8
7
6

o = disk transfer rate::;; 5 Mbs

5
4

o = spindle motor control option implemented
o = head switch time> 15 IJsec

1 = not MFM encoded

o = removable cartridge drive
1 = fixed drive

1 = soft sectored

o = hard sectored

0= reserved

Number of cylinders in the default translation mode

Number of heads in the defallit translation mode

42
52

Number of unformatted bytes per sector in the default translation mode

62
10-19
203

Number of unformatted bytes per track in the default translation mode
Number of sectors per track in the default translation mode
Serial No. 20 ASCII chars, right justified, space padded (20h); OOOOh=not specified
Buffer Type
OOOOh Not specified; 0004h-FFFFh Reserved
0001 h Single port single sector buffer; no simultaneous host-disk transfer
0002h Dual port multi-sector buffer; simultaneous host-disk transfers
0003h Dual port multi-sector buffer; simultaneous transfers with read caching

Buffer size in 512-byte increments (OOOOh=not specified)

7-23

'intel~

Flash Drive iFDO05P2SAliFD010P2SA

, Word1

Bit

Number of ECC bytes passed on readlwrite long commands (OOOOh=not specified)
Firmware rev.; 8 ASCI! chars, left justified, space padded (20h); OOOOh=not specified

22
23-26
27-46
47
48
49

,7-0

15-8
15-8

54
55
56
57-58
59
60-61
, 62

Model NoAO ASCII chars, left justified, space padded (20h); OOOOh=not specified
Max readlwrite multiple sectors transferredlinterrupt (OOh=not allowed)'
OOOOh = cannot perform doubleword I/O;OOO1h = can performdoubleword 1/0

15-10

9
8
51 4

Table 7. Identify Drive Arguments (continued)
Description

Capabilities; 0 == reserved
1 = LBA mode supported; 0 = CHS mode supported
1 = DMA supported; 0 = DMA not supported
PIO data transfer cycle timing mode
DMA data transfer cycle timing mode (not supported)
Number of current cylinders in the current translation mode
Number of current heads in the current translation mode

8
7-0

Number of current sectors-per-track in the current translation, mode
Current sector capacity, excluding device-specific sectors, = words (54 * 55 * 56)
1 = Multiple sector setting, bits7-0,is valid
No. of sectors set to transfer per interrupt on readiwrite multiple commands

15-8

Total number of user addressable sectorS if LBA mode is supported, CHS mode = 0
Single-word DMA transfer mode active, indicated by bits 7-0; (not supported)

7-0
15-8
7-0

Single-word DMA transfer modes available; (not supported)
Multi-word DMA transfer mode active, indi~ted by bit~ 7-0; (not supported)
Multi-word DMA transfer modes available; (not supported)

1. Words not listed are ATA or Intel reserved.
2. Initialize drive parameters does not affect words1-S.
3. These codes, not typically used by an operating
system, are for diagnostic program initialization.

7-24

4. Each ATA deVIce's transfer timing falls into unique
parametric timing specification categories, determined
by compa,ring the cycle time specified in figure 7 with
bits 15-8. 'Mode 0 is the default timing. '

Flash Drive iFD005P2SAliFD010P2SA

Command
Check Power Mode
Execute Drive Diags
Format Track
Identify Drive
Idle
Idle Immediate
Initialize Drive params
Recalibrate
Read Buffer
Read DMA
Read Long
Read Multiple
Read Sector(s)
Read Verify Sector(s)
Seek
Set Features
Set Multiple Mode
Sleep
Standby
Standby Immediate
Write Buffer
Write DMA
Write Long
Write Multiple
Write Same
Write Sector(s)
Write Verify
Invalid Command

. ErrOr p osting
Tabl e 8. Reglster
.
Contents Durlng
Status Reg ister
Error Register
BBK UNC IDNF ABRT TKONF AMNF DRDY DWF DSC CORR ERR

V
V
V
V

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V ..
V
V
V
V
V
V
V
V
V
V
V

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

V
V
V
V
V
V
V

V
V
V
V
V
V

V
V
V
V
V

V
V
V
V
V
V

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

V
V
V
V
V
V

V
V
V
V
V

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

v = Valid for this command

7-25

'j:

I
i~

~
I'~.il: ·.

Flash Drive iFD005P2SAliFD010P2SA

ABSOLUTE MAXIMUM RATINGS·
Operating temperature 1 ....................... O°C to +60°C
Storage temperature ........................ -30°C to +70°C
Any pin voltage, from ground2 ••••••••••• -2.0V to +7.0V
vee voltage, from ground ...... :.......... -0.5V to +6.0V
NOTES:
1. Operating temperature is for commercial product
defined by this specification.
2. Minimum DC input voltage is -0.5V. During
transitions, inputs may undershoot to -2.0V for
periods less than 20ns .. Maximum DC output-pin
voltage is Vee + 0.5V which may overshoot.to
Vee + 2.0Vfor periods less than 20ns.

*NOTICE: Stresses beyond those listed under
"Absolute Maximum Ratings· may permanently
damage the flash drive. This is a stress rating only.
Flash drive functional operation at or beyond
conditions 'in this specification's operational
sections is not implied. Extended exposure to
absolute maximum, rating conditions may affect
flash drive reliability.
NOTICE:
This data sheet contains initial
production-development. and sampling-phase
information. Specifications may change without
notice.· Obtain the latest data sheet from your
local Intel sales office before finalizinQ a desiQn.

DC CHARACTERISTICS' TA - O°C to 60°C , Vee -- 4 75V to 5 25V
Typ
Symbol Parameter
Notes Min

Max

Unit

III

Input Leakage Current

±1

±20

IJA

Vee = Vee Max
VIN = Vee or GND

ILO

Output Leakage Current

±1

±20

IJA

Vee = Vee Max
VIN = Vee or GND

leeR

Vee Read Current
Vee Write Current

100

leew,

mA
mA

140

Vee Idle Current

Vee Standby Current

lecE

Vee Reclamation (erase) Current

140

leesl
leep

Vee Sleep Current
1,2,3
Vee Peak Current at Vpp Startup

700

Vil

Input Low Voltage

-0.5

0.8

VIH

Input High Voltage

2.0

Vee+0.3

Vss

0.45

7-26

leel
Ices

•..
VOL
Output Low VoltaQe
VOH
Output High VoltaQe
1. leel Max current applies only when a host idle
command forces the drive into idle mode. If no activity
is detected after about 1.5 seconds, the drive
automatically transitions to standby mode.

Test Condition

Vee = Vee Min
2.4
V
Vee = Vee Min
Vee
2. Standby and Sleep modes are equivalent.
3. After command completion. the drive enters standby
mode. It wakes and responds to a host command
within 10 ms.

infel~
INPUT

Flash Drive IFDOOSP2SAliFD010P2SA

.:~TESTPOINTS:~

--...·1

I·

OUTPUT

=><

I:ST POINTS-=-:<::>C

AC test Inputs are driven at VOH (2.4V) for a logic "1" and VOL (0.45V) for a logic "0".
Input timing begins at VIH (2.0V) and VIL (0.8V). Output timing ends at VIH and VIL.
Input rise and fall times (10% to 90%) < 10ns.
Figure 3. AC Input/Output Reference Waveform

HRST#

\~_ _~

I-tM

r-----~~----

BSY

IiI.·

r----tQ---eoj
HDASP#

,--

Ii
1

I __
_ _ _ _ _- ' _ L-

t-----tR---...,..---ts
Control
Register'$

I·

------~----cC==

Figure 4. Reset Timing Diagram

mlng Parameters
Table 9• Power..()nan d Reset TI·
Symbol IEEE

Parameter

tSLSH

HRST# pulse width

tSHYH

Min

Max

Units

HRST#toBSY

100

tSHDSPH· HRST# to HDASP# high

tDSHDSL

HDASP# pulse width

tSHOSL

HRST# to HDASP# low

450

sec ..
ms

·tOSHOSLE HDASP# pulse width (extended)

30.5

sec

IlS

7-27

intet'

Flash Orive iFD005P2SAliFD010P2SA

to
tl
Address, REG#

CS1#, CS2#

~
t13

-tlS--

t14
t15

OE#,WE#

-t17-\
ts I--

WAIT#

-ts

Write Data
(00-15 or 00-7)

------ ..,.....,
---,---'-+

Read Data
(00-15 or 00-7)

-- -

---

V
-

t16

t19

r:--

'-t9

t22

--tl0

-I tl11--

t,2--

t20 l-

t21

r--

...,

...

f--

-t4is

Figure 5. Attribute and Memory-mode Timing Diagram

Table 10. Attribute and Memory-mode Timing Parameters
READ
Symbol IEEE
Min
Parameter
tl
tAVAVR
Read cycle time
300
tAVOV
Address access time
t2
tELOV
t3
Card Enable access time
Output Enable to data change
t4
tGLONZ
5
ts
tGLOV
Output Enable acceSs time
ts
tGLWtV
Wait valid from Output Enable
t7
tWtLWtH 'Wait pulse width
ts
tOVWtH
Data setup for Wait released
0
t9
tAxox
. Data valid after address change
0
ttO
tGHEH
Card Enable hold time
20
ttt
tEHOZ
Data disable from Card Enable high
t12
Data disable from Output Enable high
tGHOZ

7-28

Max

300
300
150
35
12

100
100

Units
ns
ns
r;lS

ns
ns
ns
IJS

ns
ns
ns
ns
ns

infel~

Flash Drive iFD005P2SAliFD010P2SA
Table 10. Attribute and Memory-mode Timing Parameters (continued)

WRITE
Symbol
to
t13
t14
t15
t16
t17
t18
t19
120
121
122

IEEE
tAVAVW
tAVWH
tELWH
tWLWH
tDVWH
tAVWL
tELWL
tWLOZ
tWHDX
twHONZ
twHAX

Address

Parameter
Write cycle time
Address valid to Write Enable high
Card Enable to Write Enable high
Write Enable pulse width high
Data valid to Write Enable high
Address valid to Write Enable low
Card Enable setup to Write Enable low
Write Enable to previous read·data disabled
Data hold after Write Enable high
Data driven after Write Enable high
Address hold after Write Enable high

Min

Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Max

200
140
140
120
60
20
0
90
30
5

tso

~
I--t51

t61 r----

t54

REG#

~ts2

155

I-

--l ts2

CS1#,C82#

~153-.

10RD#, 10WR#

t63

-1

INPACK#
(Read Only)

-t56

i+- -t64

--I

101816#

. -t65---1

t66-j

WAIT#

Write Data
(00-15 or 00-7)

t70

-157

Read Data
(00-15 or 00-7)

158

t59-

,...---~--,--

t60:.-

l.
-'I

"'\
or

Figure 6. I/O-Mode Timing Diagram

7·29

i
Ic

i'l.

:.t·

infel~

Flash Drive iFD005P2SAliFD010P2SA

·
P arameters
Table 11. U ·ModeTImlng
READ

150
151
tS2

Min

Read cycle time
Address valid to 10RD# low
REG# low to 10RD# low

300
70
5'

tS3
tS4
tss

tlGLlGH
tlGLQV
tlGLlAL
tlGLWTL
twrLWTH
tWTHQV
tlGHQX

Card Enable to 10RD# low
10RD# pulse width
10RD# to data valid
10RD# low to INPACK# low
10RD# low to WAIT# low
WAIT#pulse width
WAIT# to Data valid
Dala hold after 10RD# hi~h

5
165
100
0

ns
ns
ns
ns

tS6
tS7
158
159
t60
t61

tlGHAX
IIGHRGH

Address hold after 10RD# hioh
10RD# high 10 REG# high

t62
163
164
165

IIGHEH
IIGHIAH'
lAVISH
IIAVISL

10RD# high 10 Card Enable hiah
10RD# high 10 INPACK# high

166
WRITE
Symbol
t50
151
152
153
154
157

IEEE
IAVAVR
IAVIWL
IRGLlWL
IELlWL
t,WLIWH

Parameter
Wrile cycle lime
Address valid 10 IOWR# low
REG# low 10 10WR# low
Card Enable t6 10WR# low
10Wf'!# pulse width

tAVAVR
tAVIGL
tRGLlGL
tELlGL

10WR# low 10 WAIT# low
IWTLWTH WAIT#pulse width
IIWHQX
Data hold after 10WR# hiah
IIWHAX
Address hold after 10WR# hioh
IIWHRGH 10WR# high 10 REG# high

163
165
t66
170

IIWHEH
tAvlSH
tlAVISL
IQVIWL

7-30

Address valid to 101516# low
Data valid 10 10WR#

45
35
12
35

Min

ns
us
ns
ns
ns
ns

0
20
45
35

ns
ns
ns

Max

Units

300
70

ns
ns

5
5
165

ns
ns
ns

IIWLWTL

10WR# hiOh 10 Card Enable hioh
Address change to 101516# high

ns
ns

0
20

Address chan~e to 101516# hiah
Address valid 10 101516# low

158
160
161
162

Max

Units

Parameter

Symbol IEEE

35
12
30
20
0

US
ns
ns
ns

20
35
35
60

ns
ns
ns
ns

intel~

Flash Drive IFD005P2SAliFD010P2SA

~~----------~----~)~--b 1 - - - - - I - - b2----foo-- b9-+- b8

Address Valid
HCSO#, HCS1#

1-----

HIOR#, HIOW#

- - - - - r-----'---+"-'\

Write Data Valid
(HOO-15 or HOQ-7)

- - - - - '--------+-

Read Data Valid
(HOQ-15 or HOQ-7)

---"~,---I____---,r

H1016#

Figure 7. IDE-ATA Programmed 1/0 Timing Diagram
Table 12. IDE-ATA Programmed 1/0 Timing Parameters
Parameter
Min
Cycle time
333
Address HCSO# HCS1# to HIOR#/HIOW# setup_
50
HIOR#/HIOW# pulse width
80
Data setup to HIOW# high
20
HIOW# data hold
10
Oata setup to HIOR# hiQh
HIOR# data hold
0
Address, HCSO#, HCS1# valid to H1016# assertion
0
Address HCSO# HCS1# valid to HI016# negation
HIOR#/HIOW# to address HCSO# HCS1 # invalid
10

Svmbol IEEE
t30
tlGLlGL
lsi
tAVIGL
t32
tlGLlGH
t33
tDVIGH
t34
tlGHDX
t35
tOVIGH
t36
tlGHOX
t37
tAVISL
be
tAXISH
t39
tlGHAX

Max

50
5
30
20

Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ORDERING INFORMATION
iFD005P2SAXXXXX
iFD010P2SAXXXXX
Where:

FD
005,010
P
2

S
A

Intel
Flash drive
Density in Megabytes
PCMCIA-ATA
PCMCIA Type-2 form factor
Power supply voltage = 5V
Revision or stepping number

7-31

iFD005P2SA/OIOP2SA Flash Drive Product Brief

Product - PCMCIA·ATA Interface
Highlig·hts • PCMCIA·ATAinterfaceand
command set
• Uses standard ATA host
software driver
• Compatible with PCMCIA
2.0 sockets
• Compatible with 1.8"
ATA·IDE sockets
• Compatible with standard
data compression utilities

_ .Low Battery Drain
• Supports power management
drive commands
• Autoinatic integrated power
management
• 10 mW Sleep Mode
_ High Performance
• No Spinup Time
• No Rotational Latency
.. Seek Time < Imsec
_ Extremely Rugged and Reliable
• Solid·state reliability
• 1000G Operating &
Non'operating Shock
• 250K Power·on Hour MTBF
_ Absolute Silent Operation

The flash drive extends the system battery life by only using power when it
needs it. There are no spinning disks continually consuming power.
Automatic integrated power management reduces current without special
system BIOS support. Systems can have battery life extended up to 100%by
the flash drive.

_ Small Size, Low Weight
• PCMCIA Type 2 form factor
• 65 gms (2.0 oz.)

The flash drive is intelface compatible with PCMCIA -ATA magnetic drives,
so using the flash drive is as easy as replacing the disk drive with a flash
drive. No additional system software drivers are typically required.

_ 5, 10Mbyte versions

With its Type 2, 5mmformfactor the flasn drive is very compact, only one
half the thickness of a 1.8" Type 3 hard disk drive, allowing two cards to
occupy the space of one disk drive.

_ Embedded Flash Memory
Management
_ Non volatile (Zero· Power Data
Retention)
• No Batteries Required
_ Uses ETOXTM nash Memory
Technology Chips
• Intel FlashFile™ Architecture
_ Single +5 Volt Supply

7·32

Intel's Flash Drive brings the mass storage advantages of Intel's
FlashFile™ memory to mobile computers equipped with the PCMCIA·ATA
hard disk drive interface . Offering up to 10 megabytes of nonvolatile
storage; the iFDOIOP2SA provides the battery life, peiformance,
ruggedness, reliability and totally silent operation needed by leading edge
mobile computing applications.

The flash drive's solid state construction yields high pelformance and a
IOOOg shock specification, andflash memory reliabilityprovide the ultimate
in data integrity for critical data applications.

I
Specification Summary
Capacity (CHS Auto-Translate)
Formatted
iFDOO5
5M
iFDOIO
10M
Environmental
Temperature, operating/non-operating
Temperature Gradient
Humidity, Operating (non-cond, 26% wet bulb)
Altitude, Operating
Interface
System

Performance (Typical)
Seek Time (Maximum of Track-to-track)
Controller Overhead (Command to DRQ)
Rotational Latency
Spinup Time via Command, Power-on to ready
Media Transfer Rate
.
Interface Transfer Rate
Sustained Transfer Rate
Buffer Size
Power (RMS, Typical)
Read
Write
Reclamation (additional to above)
Idle
Standby
Sleep mode
Supply Voltage
Reliability
MTBF (TA =25'C)
Read Error Rate (with retries and ECC)
Start/Stop Cycles
ECC
Ruggedness
Shock, op/non-operating
Vibration, op/non-operating
Size
Length
Width
Thickness
Weight (with mounting hardware)
Noise (Sound Pressure Level)

Bytes (cylinders, heads, sectors)
5,242,880
10,653,696
O'C to 6O'C / -20"C.to+85'C
20"C/hr
5 to 95% RH
-200 to40K ft (-60 to 12Km)
68-pin, PCMCIA-ATA
PCMCIA, PC Card Standard, Release 2.02
PCMCIA-ATA Standard, Release 1.01
68-pin, \.8" ATA-IDE (a.k.a. "68 pin ATA")

< 1 ms
<
......
.!t

::D
C
......

"'1'1
~i

CD
~

»
ClO
"'1'1
....
0

-t
m
I

CE#
WE#
OE#
RP#

6
m

Po)

III

Y-GATING/SENSING

Ao-A,7

Vpp

""
'-'

iii"

f6 ca

~'"

>-«

""
'-'
0

....
'" ....~g""
>-«
--'

'"""~.... '"

III

....

¥~

·1

....

"':::. "':::.
~

;1.

.... "" .... ""
>-0
>-0
>-0
"'--' ""'"
'" --' """,
'" --'
""",
c!,!!: ~!:: ~~
....
""
~'-'

~'-'

N«

~:::.

C:=lJ

-------

::D
"'V

-t

~:::.

;1.

(")

'iii)

2m
~

-t
en

-a

::D

c:
(")

III
'<

0"
()

.....

~
I§

BYTE#

---

. 290501-4

_
.
::J

cC
@

A28F400BX-T/B

2.1 A28F400BX Memory Organization
2.1.1 BLOCKING
The A28F400BX uses a blocked array architecture
to provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block address range and the Erase Setup and Erase Confirm
commands are written to the CUI. The A28F400BX
is a random read/write memory. only erasure is performed by block.
2.1.1.1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of power failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being written or
erased when RP# is not at 12V. The boot block can
be erased and written when RP# is held at 12V for
the duration of the erase or program operation. This
allows customers to change the boot code when
necessary while providing security when needed.
See the Block Memory Map section for address locations of the boot block. for the A28F400BX-T and
A28F400BX-B.

2.1.2 BLOCK MEMORY MAP
Two versions of the A28F400BX product exist to
support two different memory maps of the array
blocks in order to accommodate different microprocessor protocols for 1>90t code location. The
A28F400BX-T'memory map is inverted from the
A28F400BX-B memory map.
2.1.2.1. A28F400BX-B Memory Map
The A28F400BX-B device has the 16-Kbyte boot
block located from OOOOOH to 01 FFFH to accommodate those microprocessors that boot from the bottom of the address map at OOOOOH. In the
A28F400BX-B the first 8-Kbyte parameter block resides in memory space from 02000H to 02FFFH.
The second 8-Kbyte parameter block resides in
memory space from 03000H to 03FFFH. The 96Kbyte main block resides in memory space from
04000H to OFFFFH. The three 128-Kbyte main
block resides in memory space from 10000H to
1FFFFH. 20000H to 2FFFFH and 30000H to
3FFFFH (word locations). See Figure 4.
(Word Addresses)

3FFFFH
12B-Kbyte MAIN BLOCK

3OOO0H
2FFFFH

2.1.1.2 Parameter Block Operation
128·Kbyte MAIN BLOCK

The A28F400BX has 2 parameter blocks (8 Kbytes
each) . .The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The parameter blocks can also be used to store additional
boot or main code. The parameter blocks however.
do not have the hardware write protection feature
that the boot block has. The parameter blocks provide for more efficient memory utilization when dealing with parameter changes versus regularly blocked
devices. See the Block Memory Map section for address locations of the parameter blocks for the
A28F400BX-T and A28F400BX-B.
2.1.1.3 Main Block.Operatlon
Four main blocks of memory exist on the
A28F400BX (3 x 128 Kbyte blocks and 1 x 96-Kbyte
blocks). See the following section on Block Memory
Map for the address location of these blocks for the
A28F400BX-T and A28F400BX-B products.

20000H

lFFFFH
128·Kbyte MAIN BLOCK

l0000H
OFFFFH
9B-Kbyte MAIN BLOCK

04000H
03FFFH
03000H
02FFFH
02000H
01FFFH

B-Kbyte PARAMETER BLOCK
B-Kbyte PARAMETER BLOCK

lB-Kbyte BOOT BLOCK

OOOOOH

Figure 4. A28F400BX-B Memory Map

8-9

..~

intel®

A28F4008X-T/8

2.1.2.2 A28F400BX-TMemory Map
The A28F400BX-T device has the 16-Kbyte boot
block located from.3EOOOH to 3FFFFH to accommodate those microprocessors that boot from the top
of the address map. In the A28F400BX-T the first
8-Kbyte parameter block resides in memory space
from 30000H to 30FFFH. The second 8-Kbyte· parameter block resides in memory space from
3COOOH to 3CFFFH. The. 96-Kbyte main block resides in memory space from 30000H to 3BFFFH.
The three 128-KbytEj main blocks reside in memory
space from20000H to 2FFFFH, 10000H to 1FFFFH
and OOOOOH to OFFFFH as shown below in Figure 5.
(Word Addresses)
3FFFFH
16-Kbyle BOOT BLOCK
3EOOOH
3DFFFH
3DOOOH
3CFFFH
3COOOH
3BFFFH

S·Kbyte PARAMETER BLOCK

3..0

PRODUCT FAMILY PRINCIPLES
OF .OPERATION

Flash memory augments EPROM functionality with
in-circuit electrical write and erase. The 4-Mbit flash
family utilizes a Command User Interface (CUI) and
internally generated and timed algorithms to simplify
write and erase operations.
The CUI allows for 100% TTL-level· control inputs,
fixed power supplies during erasure and programming, and maximum EPROM compatibility.
In the absence of high voltage on the Vpp pin, the
4-Mbit boot block flash family will only successfully·
execute the following commands: Read Array, Read
Status Register, Clear Status Register and Intelligent Identifier mode. The device provides standard
EPROM read, standby and output disable operations. Manufacturer Identification and Oevice'ldentification data can be accessed through the CUI or
through the standard EPROM A9 high voltage ac. cess (VID) for PROM programming equipment.

S-Kbyte PARAMETER BLOCK

96-Kbyle MAIN BLOCK
30000H
2FFFFH
12S-Kbyte MAIN BLOCK
20000H
1FFFFH
12S-Kbyte MAIN BLOCK
10000H
OFFFFH

The same EPROM read, standby and output disable
functions are available when high voltage is applied
to the Vpp pin. In addition, high voltage on Vpp allows write and erase of the device. All functions associated with altering memory contents: write and
erase, Intelligent Identifier read and Read Status are
accessed via the CUI.
The purpose of the Write State Machine (WSM) is to
completely automate the write and ,erasure of the
device. The WSM will begin operation upon receipt
of a signal from the CUI and will report status back
through a Status Register. The CUI will handle the
WE # interface to the data and address latches, as
well as system software requests for status while the
WSM is in operation.

12S-Kbyte MAIN BLOCK
OOOOOH

Figure 5. A28F400BX-T Memory Map

8-10

3.1

Bus Operations

Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.

A28F400BX-T IB

Table 1. Bus Operations for WORD-WIDE Mode (BYTE #
Mode
Read

CE#

OE#

WE#

Vpp

1,2,3

VIH

VIL

VIH

DOUT

HighZ

VIH

VIL

VIH

Standby

VIH

VIL

X
·X

Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
Write

VIH

VIL

VIH

VID

VIL

0089H

VIH

VIL

VIH

VID

VIH

4470H
4471H

6,7,8

VIH

VIL

VIH

VIL

DIN

DQO-7

DQS-14

Read

HighZ

Notes

RP#

CE#

1,2,3

VIH
VIH

Output Disable
Standby

DQO-15

4,5

Table 2. Bus Operations for BYTE-WIDE Mode (BYTE
Mode

V'H)

RP#

Output Disable

Deep Power-Down

Notes

OE#

WE#

VIL

VIH

VIL

VIH

X
X
X

VIH

VIL

V,Ll

A-1

Vpp

DOUT

HighZ

89H

HighZ

Deep Power-Down

Intelligent
Identifier (Mfr)

VIH

VIL

VIH

VID

VIL

4,5

VIH

VIL

VIH

VID

VIH

70H
71H

HighZ

6,7,8

VIH

VIL

VIH

VIL

DIN

HighZ

Intelligent
Identifier (Device)
Write

NOTES:
1. Refer to DC Characteristics.
.
2. X can be VIL, VIH for control pins and addresses, VPPL or VPPH for Vpp.
3. See DC Characteristics for VPPL, VpPH, VHH, VIO voltages.
4. Manufacturer and Device codes may also be accessed via a CUI write sequence. A1-A17 = X.
5. Device ID = 4470H for A2SF400BX-T and 4471H for A2SF400BX-B.
6. Refer to Table 3 for valid DIN during a write operation.
7. Command writes for Block Erase or Word/Byte Write are only executed when Vpp = VPPH.
S. To write or erase the boot block, hold RP# at VHH.
9. RP# must be at GND ±0.2V to meet the SO /LA maximum deep power-down current.

3.2 Read Operations
The 4-Mbit boot block flash family has three user
read modes; Array, Intelligent Identifier, and Status
Register. Status Register read mode will be discussed in detail in the "Write Operations" section.
During power-up conditions (VCC supply ramping), it
takes a maximum of 300 ns from when VCC is at
4.5V minimum to valid data on the outputs.

3.2.1 READARRAY
If the memory is not in the Read Array mode, it is
necessary to write the appropriate read mode command to the CUI. The 4-Mbit boot block flash family
has three control functions, all of which must be logically active, to obtain data at the outputs. Chip-Enable CE # is the device selection control. Reset!
. Power-Down, RP# is the device power control. Output-Enable OE# is the DATA INPUT/OUTPUT
(DO[0:15] or DO[0:7]) direction control and when
active is used to drive data from the selected memory on to the I/O bus.

8-11

intel®

A28F400BX-T/B

3.2.1.1 Output Control
With OE# atlogic-highlevel (VIH), the output from
the device is disabled and data input! output pins
(00[0:15] or 00[0:7] are tri-stated. Data input is
then controlled by WE # .

are dElsired. The system designer can also choose
to "hard-wire" Vpp to 12V. The 4-Mbit boot block
flash family is designed to accommodate-either design practice. It is strongly recommended that RP#
be tied. to logical Reset for data protection during
unstable CPU reset function as described in the
"Product Family Overview" section .

. 3.2.1.2 Input Control
With WE # at logic-high level (VIH), input to the device is disabled. Data Input!Output pins (DQ[0:15]
or 00[0:71) are controlled by OE #.

3.2.2 INTELLIGENT IDENTIFIERS
The manufacturer and device codes are read via the
CUI or by taking the Ag pin to 12V. Writing 90H to
the CUI places the device into Intelligent 'Identifier
read mode.' A read of location OOOOOH outputs the
manufacturer's identification code, 0089H, and location 00001 H outputs the device code; 4470H for
A28F400BX-T, 4471H for A28F400BX-B. When
BYTE # is at a logic low only the lower byte of the
above signatures is read and D015/A-l is a "don't
care" during Intelligent Identifier mode. A read array
command must be written to the memory to return to
the read array mode.

3.3 Write Operations
Commands are written to the CUI using standard microprocessor write timings. The CUI serves as the
interface between the microprocessor and the internal chip operation. The CUI can decipher Read Array, Read Intelligent Identifier, Read Status Register,
Clear Status Register, Erase and Program commands. In the event of a'read command, the CUI
simply points the read path at either the array, the
Intelligent Identifier, or the status register depending
on the specific read command given. For a program
or erase cycle, the CUI informs the write state machine that a write or erase has been requested. During a program cycle, the Write State Machine will
control the program sequences and the CUI will only
respond to status reads. During an erase cycle, the
CUI will respond to status reads and erase suspend.
After the Write State Machine has completed its
task, it will allow the CUI to respond to its full command set. The CUI will stay in the current command
state until the microprocessor issues another command.
The CUI will successfully initiate an erase or write
operation only when Vpp is within its voltage range.
Depending upon·theapplication, the system designer may choose to make the Vpp power supply
switchable, available only when memory .updates

8-12

3.3.1 BOOT BLO,CK WRITE OPERATIONS
In the case of Boot Block modifications (write and
erase), RP# is set to VHH = 12V typically, in addi. tion to Vpp at high voltage.
However, if RP# is not at VHH when a program or
erase operation of the boot block is attempted, the
corresponding status register. bit (Bit 4 for Program
and Bit 5 for Erase, refer to Table 5 for Status Register Definitions) is set to indicate the failure to complete the operation.

3.3.2 COMMAND USER INTERFACE (CUI)
The Command User Interface (CUI) serves as the
interface to the microprocessor. The CUI points the
read/write path to the appropriate circuit block as
described in the previous section. After the WSM
has completed its task, it will set the WSM Status bit
to a "1", which will also allow the CUI to respond to
its full command set. Note that after the WSM has
returned control to the CUI, the CUI will remain in its
current state.

3.3.2.1 Command Set
Command
Codes

Device Mode

00
10
20
40
50
70
90
BO
DO
FF

InvalidlReserved
Alternate Program Setup
Erase Setup
Program Setup
Clear Status Register
Read Status Register
Intelligent Identifier
Erase S,uspend '
Erase Resume/Erase Confirm
Read Array

3.3.2.2 Command Function Descriptions
Device operations are selected by writing specific
commands into the CUI. Table 3 defines the 4-Mbit
boot block flash family commands.

A28F400BX-T /B
Table 3. Command Definitions
Command

Bus Notes
First Bus Cycle
Second Bus Cycle
Cycles
Req'd
8
Operation Address Data Operation Address Data

Read Array

Write

Intelligent Identifier

2,4

Write

90H

Read

liD

Read Status Register

Write

70H

Read

SRD

DOH

FFH

Clear Status Register

Write

50H

Erase Setup/Erase Confirm

Write·

20H

Write

Word/Byte Write Setup/Write

6, 7

Write

40H

Write

Erase Suspend/Erase Resume

Write

BOH

Write

DOH

Alternate Word/Byte
Write Setup/Write

Write

10H

Write

6, 7

NOTES:
1. Bus operations are defined in Tables 1, and 2.
2. IA = Identifier Address: OOH for manufacturer code, 01 H for device code.
3. SRD = Data read from Status Register.
4. 110 = IntelliQent Identifier Data.
Following the Intelligent Identifier Command, two read operations access manufacturer and device codes.
5. BA =. Address within the block being erased.
6. WA = Address to be written.
WD. = Data to be written at location WD.
7. Either 40H or 10H commands is valid.
8. When writinq commands to the device, the upper data bus [DQ8-oo15] = X which is either Vee or Vss to avoid buming
additional current.

Invalid/Reserved

Read Status Register (70H)

These are unassigned commands. It is not recommended that the customer use any command other
than the valid commandS specified above. Intel reserves the right to· redefine these codes for future
functions.

This is one of the two commands that is executable
while the state machine is operating. After this command is written, a read of the device will output the
contents of the status register, regardless of the address presented to the device.

Read Array (FFH)

The device automatically enters this mode after program or erase has completed.

This single write command points the read path at
the array. If the Host CPU performs a CEnOE#
controlled read immediately following a two-write sequence that started the WSM, then the device will
output status register contents,. If the Read Array
command is given after Erase Setup the device is
reset to read the array. A two Read Array command
sequence (FFH) is required to reset to Read Array
after Program Setup.
.
Intelligent Identifier (90H)
After this command is executed, the CUI points the
output path to the Intelligent Identifier circuits. Only
Intelligent Identifier values at addresses 0 and 1 can
be read (only address Ao is used in this mode, all
other address inputs are ignored).

Clear Status Register (SOH) ,
The WSM .can only set the Program Status and
Erase Status bits in· the status register, it can not
clear them. Two reasons exist for operating the
status register in this fashion. The first is a synchronization. The WSM does not know when the host
CPU has read the status register, therefore it would
not knoW when to clear the status bits. Secondly, if
the CPU is programming a string of bytes, it may be
more efficient to query the status register after programming the string. Thus, if any errors exist while
programming the string, the status register wiU return
the accumulated error status.

Program Setup(40H or 10H)

This command simp~ iI,ets the CUI into state such
that the next write Will load the address and data
registers. Either 40Hor 10H can be usect for Program Setup. Both commands" are included to accommodate efforts to achieve an industry ,$tandard
command code !\EIt.
'
Program
The second write after the program setup command, '
will latch addresses and data. Also, the CUI initiates
the WSM to begin execution of the program algorithm. While the WSM finishes the algorithm, the device will output Status Register contents. Note that
the WSM cannot be suspended during programming.
Erase Setup (20H)
Prepares the CUI for the Erase Confirm command.
No other action is taken. If the next command is not
an Erase Confirm command then the CUI will set
both the Program Status and Erase Status bits of the
Status Register to a "1", place the device into the
Read Status Register state, and wait for another
'
command.
Erase Confirm (DOH)c
If the previous command was an Erase Setup com-'
mand, then the CUI will enable the WSM to erase, at
the same time closing the address and data latches,
and respond only to the Read Status Register and
Erase Suspend commands. While the WSM is executing, the device will output StatU$ 'Register data
when OE,; is toggled low. StatU$ Register data can
, only be updat~ by toggling either OE # or CE # low.
Era.. SUspend (BOH)
This command only has meaning while the WSM i$
executing an Erase operation, and therefore ,will only
be responded to during an' era$e operation. After
this command has been executed, the CUI will set
an output that directs the WSM to suspend Erase
operations, arid then retum to re$ponding to only
Read 'Status Register or the Erase Resume com- '
mands. Once the WSM ha$ reached the Suspend
$tate, it will !\EIt an output into the CUI which allows
the CUI to respond to the Read Array, Read Status
Regi$ter, and Erase Re$ume comman'ds. In this
mode, the CUI will not respond to any other,command$. The WSM will al$Clset the WSM Status bit to
a "1". The WSM will continue to run, idling in the
SUSPEND state, regardless of the state of all input

8-14

control pins, with the exclusion of RP#. RP# will
immediately s!lut down the WSM and the remainder
of the Chip. During, a $u$pend operation, the data ,
and address latches will remain closed, but the address pads are able to drive the address into the
read path.
Erase Resume (DOH) ,
Thi$ command will cause the CUI to clear the SU$pend state and set the WSM Status bit to a "O!', but
only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.
3.3.3 STATUS REGISTER
The 4-Mbit boot block flash family contains a status
register which may be read to determine when a program or erase operation is complete, and whether
that operation completed successfully. The status
, register,may be read at any time by writing the Read
Status command to the CUI. After writing this command, all subsequent Read operations output data
from the status register until another command is
written to the CUI. A Re~d Array cpmmand must be
written to the CUI to return to the Read Array mode.
The status register bits are output on 00[0:7]
whether the device is in the byte-wide (x8) or wordwide (x16) mode. In the word-wide mode the upper
byte, 00[8:15] is set to DOH during a Read Status
command. In the byte-wide mode, 00[8:14] are tristated and 001s/A-1 retains the low order address
function.
It should be noted that the contents of the status
regi$ter are latched on the falling edge of OE # or
CE # whichever occurs' la$t in the read cycle. This
prevents possible bus errors which might occur if the
contents of the status register change while reading
the status ,register.CE#' or OE# must be toggled
with each subsequent status read, or the completion
ofa prograinorerase' operation will not be evident.
The Status Register is the interface between the mi, croprocessor and the Write State Machine (WSM).
When the' WSM is active, this register will indicate
, the status of..the WSM, and will also hold the. bits
indicating whether or not the WSM was successful in
performing the deSired operation. The WSM sets
status bits "Three'; through "Seven" and clears bits
"Six" and "Seven", but cannot clear status bits
"Three"through "Five": These bits can only be
cleared by the controlling CPU through the use of
the Clear Status Register command.

A28F400BX-T IB

3.3.3.1 Status Register Bit Definition
Table 4. Status Register Definitions

IWSMS I ESS
7

I VPPS I

NOTES:

SR.? = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy

Write State Machine Status bit must first be checked to
determine byte/word program or block erase comple·
tion, before the Program or Erase Status bits are
checked for success.

SR.6 = ERASE SUSPEND STATUS
1 = Erase Suspended
o = Erase in Progress/Completed

When Erase Suspend is issued, WSM halts execution
and sets both WSMS and ESS bits to "1". E$S bit remains set to "1" until an Erase Resume command is
issued.

SR.5 = ERASE STATUS
1 = Error in Block Erasure
o = Successful Block Erase

When this bit is set to "1". WSM has applied the maximum number of erase pulses to the block and is still
unable to successfully perform an erase verify.

SR.4 = PROGRAM STATUS
1 = Error In BYte/Word Program
o = Successful Byte/Word Program

When this bit is set to "1", WSM has attempted but
failed to Program a byte or word.

SR.3 = Vpp STATUS
1 = Vpp Low Detect; Operation Abort
0= Vpp OK

The Vpp Status bit unlike an AID converter, does not
provide continuous indication of Vpp level. The WSM
interrogates the Vpp level only after the byte write or
block erase command sequences have been entered
and informs the system if Vpp has not been switched
on. The Vpp StE!tus bit is not guaranteed to report accurate feedback between VPPL and VpPH.

SR.2-SR.O = RESERVED FOR
FUTURE ENHANCEMENTS

These bits are reserved for future use and should be
masked out when polling the Status Register.

3.3.3.2 Clearing the Status Register

3.3.4 PROGRAM MODE

Certain bits in the status register are set by the write
state machine, and can only be reset by the system
software. These bits can indicate various failure conditions. By allowing the system software to control
the resetting of these bits, several operations may
be performed (such as cumulatively programming
several bytes or erasing multiple blocks in sequence). The status register may then be read to
determine if an error occurred during that programming or erasure series. This adds flexibility to the
way the device may be programmed or erased. To
clear the status register, the Clear Status Register
command is written to the CUI. Then, any other
command may be issued to the CUI. Note again that
before a read cycle can be initiated, a Read Array
command must be written to the CUI to specify
whether the read data is to come from the array,
status register, or Intelligent Identifier.

Program is executed by a two-write sequence. The
Program Setup command is written to the CUI followed by a second write which specifies the address
and data to be programmed. The write state machine will execute a sequence of internally timed
events to:
1. Program the desired bits of the addressed memory word (byte), and
2. Verify that the desired bits are sufficiently programmed.
Programming of the memory results in specific bits
within a byte or word being changed to a"O".
If the user attempts to program "1"s, there will be no
change of the memory cell content and no error occurs.
I"~

I
!
8-15

A28F400ex-T IB
Simirar to erasure, the status register indicates
whether programming is complete. While the pr()gram sequence is executing, bit 7 of the status register is a "0". The status register can be polled by
, toggling either CE # or OE # to determine when the
program sequence is complete. Only the Read
Status Register command is valid while programming is active.
When programming is complete, the status bits,
which indicate whether the program operation was
successful, should be checked. If the programming
operation was unsuccessful, Bit 4 of the status register is set to a "1" to indicate a Program Failure. If
Bit 3 is set then Vpp was not within acceptable limits,
and the WSM will not execute the programming sequence.
The status register should be cleared before. attempting the next operation. Any CUI instruction can
follow after programming is completed; however, it
must be recognized that reads from the memory,
status register, or Intelligent Identifier cannot be accomplished until the CUI is given the appropriate
command. A Read Array command must first be given before memory contents can be read.
Figure 6 shows a system software flowchart for device byte programming operation. Figure 7 shows a
similar flowchart for device word programming operation (A28F400BX-only).

3.3.5 ERASE MODE
Erasure of a single block is initiated by writing the
Erase Setup and Erase Confirm commands to the
CU I, along with the addresses A [12: 171, identifying
the block to be erased. These addresses are latched
internally when the Erase Confirm command is issued. Block erasure results in all bits within the block
being set to "1".
The WSM will execute a sequence of internally
timed events to:
1. Program all. bits within the block
2. Verify that all bits within the block are sufficiently
programmed
3. Erase all bits within the block and
4. Verify that all bits within the block are sufficiently
erased

8-16

While the erase sequence is executing, Bit,7 of the
status register is a "0".
When the status register indicates that erasure is
complete, the status bits, which indicate whether the
erase operation was successful, should be checked.
If the erasure operation was unsuccessful, Bit 5 of
the status register is set to a "1" to indicate an
Erase Failure. If Vpp was not within acceptable limits
ilfter the Erase Confirm command is issued, the
WSM will not execute an erase sequence; instead,
Bits of the status register is set to a ': 1" to indicate
an Erase Failure, and Bit 3 is set to a "1" to identify
that Vpp supply voltage was not within acceptable
limits.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after erasure is completed; however, it must
be recognized that reads from the memory array,
status register, or Intelligent Identifier can not be accomplished until the CUI is given the appropriate
command. A Read Array command must first be given before memory contents can be read.
Figure 8 shows a system software flowchart for
Block Erase operation.

3.3.5.1 Suspending and Resuming Erase
Since an erase operation typically requires 1.5 to 3
seconds to complete, an Erase Suspend command
is provided. This allows erase-sequence interruption
in order to read data from another block of the memory. Once the erase sequence is started, writing the
Erase Suspend command to the CUI requests that
the Write State Machine (WSM) pause the erase sequence at a predetermined point in the erase algorithm. The status register must be read to determine
when the erase operation has been suspended.
At this point, a Read Array command can be written
to the CUI in order to read data from blocks other
than that which is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register operation.
Figure 9 shows a system software flowchart detailing the operation.

A28F400BX·T IB

'Ii

During Erase Suspend mode, the chip can go into a
pseudo-standby mode by taking CE# to VIH and the
active current is now a maximum of 10 mA. If the
chip is enabled while in this mode by taking CE # to
VIL, the Erase Resume command can be issued to
resume the erase operation.
Upon completion of reads from any block other than
the block being erased, the Erase Resume command must be issued. When the Erase Resume
command is given, the WSM will continue with the
erase sequence and complete erasing the block. As
with the end of erase, the status register must be
read, cleared, and the next instruction issued in order to continue.

3.3.6 EXTENDED CYCLING
Intel has designed extended cycling capability into
its ETOX III flash memory technology. The 4-Mbit
boot block flash family is designed for 1,000 program/ erase cycles on each of the seven blocks. The
combination of low electric fields, clean oxide processing and minimized oxide area per memory cell
subjected to the tunneling electric field, results in
very high cycling capability.

8-17

A28F400BX·TIB

Bus
Operation

Command

Comments

Write

Setup,
Program

Data = 40H
Address = Byte to be
programmed

Write

Program

Data to be programmed
Address = Byte to be
programmed

Read

Status Register Data.
Toggle OE# or CEll' to update
Status Register

Standby

Check SR.?
1 = Ready, 0

= Busy

Repeat for subsequent bytes.
Full status check can be done after each byte or after a
sequence of bytes.

Write FFH after the last byte programming operation to
reset the device to Read Array Mode.
290501-5

Bus
Operation

Full Status Check Procedure

Vpp Range
Error

Commsnd

Comments

Standby

CheckSR.3
1 = Vpp Low Detect

Standby

CheckSR.4
1 = Byte Program Error

SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
Byte Program
Error

SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple bytes are programmed
before full status is Checked.
If error is detec1ed, clear the Status Register before
attempting retry or other error recovery.

290501-6

Figure 6. Automated Byte Programming Flowchart

8·18

A28F400BX-T IB

Bus
Operation

Command

Comments

Write

Setup
Program

Data = 40H
Address = Word to be
programmed

Write

Program

Data to be programmed
Address = Word to be
programmed

Read

Status Register Data.
Toggle DE # or CE # to update
Status Register

Standby

Check SR.7
1 = Ready, 0

Busy

Repeat for subsequent words.
Full status check can be done after each word or after a
sequence of words.

290501-7

Write FFH after the last word programming operation to
reset the device to Read Array Mode.

Bus
Operation

Full Status Check Procedure

vpp

Command

Comments

Standby

CheckSR.3
1 = Vpp Low Detect

Standby

Check SR.4
1 = Word Program Error

Range
Error

SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
Word Program
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple words are programmed
before full status is checked.

Error

If error is detected, clear the Status Register before
attempting retry or other error recovery.
290501-8

Figure 7. Automated Word Programming Flowchart

8-19

intel®

A28F400BX-TIB

Bus
Operation

Command

Comments

Write

Setup
Erase

Data ~ 20H
Address = Within block to be
erased

Write

Erase

Data = DOH
Address ~ Within block to be
erased

Read

Status Register Data.
Toggle OE # or CE # to update
Status Register

Standby

CheckSR.7
1 = Ready,O

= Busy

Repeat for subsequent blocks.
Full status check can be done aiter each block or after a
sequence of blocks.

290501-9

Write FFH after the last block erase operation to reset the
device to Read Array Mode.

Bus
Operation

Command

Comments

Standby

Check SR.3
1 = Vpp Low Detect

Standby

Check SRA,5
Both 1 = Command Sequence
Error

Standby

CheckSR.5
1 = Block Erase Error

Full Status Check Procedure

Vpp Range
Error

Command Sequence
\ Error

Block Erose
Error

SR.a MUST be cleared, if set during an erase attempt,
before further attempts are allowed by the Write State
Machine.
SR.5 is only cleared by the Clear Status Register
Command, in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.

290501-10

Figure 8. Automated Block Erase Flowchart

8-20

&1lDW&l1IIJ Vee

Vpp Word Write Current

rnA Vpp= VPPH
Word Write in Progress

Ippw

Vpp Byte Write Current

rnA Vpp = VpPH
Byte Write in Progress

IpPE

Vpp Block Erase Current

rnA Vpp = VPPH
Block Erase in Progress

IpPES

Vpp Erase Suspend Current

200

/LA Vpp = VPPH
Block Erase Suspended

IRP#

RP# Current

1,4

500

p,A RP# = VHH

110

AS Intelligent Identifier Current

1.4

500

/LA Ag = VIO

VIO

Aglntelligent Identifier Voltage

11.5

13.0

VIL

Input Low Voltage

-0.5

O.S

VIH

Input High Voltage

2.0

VOL

Output Low Voltage
I

S-24

Vee

+ 0.5

0.45

V
V

Vee = Vee Min
IOL = 5.SrnA

A28F400BX-T IB

DC CHARACTERISTICS
Symbol

Parameter

Notes

Min

VPPL

Vpp during Normal Operations

0.0

VPPH

Vpp during Erase/Write Operations

11.4

VLKO

Vcc Erase/Write Lock Voltage

2.0

VHH

RP# Unlock Voltage

11.5

Symbol

Typ

Max

2.4

Output High Voltage

CAPAC IT ANCE(4)

(Continued)

VOH

Unit
V

12.0

6.5

12.6

13.0

Test Condition
Vcc = Vcc Min
IOH = -2.5 mA

V
Boot Block Write/Erase

TA = 25°C, f = 1 MHz
Typ

Parameter

Max

Unit

Condition

= OV
= OV

CIN

Input Capacitance

VIN

COUT

Output Capacitance

VOUT

NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 5.0V, VPP = 12.0V, T = 25°C. These currents
are valid for all product versions (packages and speeds).
2. ICCES is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum
of ICCES and ICCR.
3. Block Erases and Word/Byte Writes are inhibited when Vpp = VPPL and not guaranteed in the range between VPPH and
VpPL·
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces ICCR to less than 1 mA typical in static operation.
6. CMOS Inputs are either VCC ±0.2V or GND ±0.2V. TTL Inputs are either VIL or VIH.
7. VPP = 12.0V ± 5% for applications requiring 1,000 block erase cycles.

STANDARD TEST CONFIGURATION
STANDARD
AC TESTING LOAD CIRCUIT

STANDARD
AC INPUT/OUTPUT REFERENCE WAVEFORM

1.3V

2.4 - - - ' \ . r::-::---~~--_ ~2.0::----INPUT
2.0
TEST POINTS
OUTPUT
0.45 _ _ _" ,,0;,;;.8::.-_.......!;~_ _.1 ,,0;,;;.8::.-_ __

290501-12

AC test inputs are driven at VOH (2.4 VnLl for a Logic "1" and VOL
(0.45 VnLl for a logic "0". Input timing begins at VIH (2.0 VnL) and VIL
(O.B VnLl. Output timing ends at VIH and VIL. Input rise and fall times (10%
to 90%) < 10 ns.

1N914

r-~~-oOUT

290501-13

CL = 100 pF
CL Includes Jig Capacitance
RL = 3.3 KO

8-25

intel®

A28F400BX-T/B

AC CHARACTERISTIC5-ReadOnly' Operations(1)
A28F400BX-90(4,5)

Versions
Symbol

Parameter

Notes

Min

Max

Unit

tAVAV

tRC

Read Cycle Time

tAVQV

tACC

Address to
Output Delay

tELQV

tCE

CE # to Output Delay

tpHQV

tPWH

RP# High to
Output Delay

tGLQV

tOE

OE # to Output Delay

tELQX

tLz

CE # to Output Low Z

tEHQZ

~HZ

CE# High to Output
HighZ,

tGLQX

tOLZ

OE # to Output Low Z

tOF

OE # High to Output
HighZ.

tOH

Output Hold from
Addresses,
CE # or OE # Change,
Whichever is First

tELFL
tELFH

CE# to BYTE #
Switching
Low or High

tFHQV

BYTE # Switching
High to Valid
Output Delay

3,5

tFLQZ

BYTE# Switching
Low to
Output High Z

tGHQZ

90,

300

35
0

ns
ns

NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE,# may be delayed up to teE-tOE after the falling edge of, CE#without impact on teE,
3. Sampled, not 100% tested.
4. See Standard Test Configuration.
5. tFLQV, BYTE # switching low to valid output delay, will be equal to tAVQV from the time OQ1s/A_1 becomes valid.

8-26

-_.

Vee POWER-UP

DEVICE AND
ADDRESS SELECTION

STANDBY

~"~"" ,.) :: X>001

@
IiiiiI

OUTPUTS ENABLED

DATA VALID

€:

---

ADDRESSES STABLE

--tAVAV

=
~

V,H

'iijJ
CE# (E)

C
III

=
©

e::J ....

V,H
OE# (G)

III

V,H

---

VIL ....

~
<

-..
-•..

---

VIL ....

WE# (w)
V,L

:D
III
AI

V,H

a.
0

.'i

•

HIGH Z

DATA (D/Q)

l- ~Lox-l

I--

toH

hox

tl I I It

VALID OUTPUT

-T\ \ \I\.

HIGH Z

V,L

0:I

tAVQV

5.0V
Vee
GND

V
,H

"'HOV

RP# (P)

V,L

290501-14

cp
I\)

,.'11t:
g

m
.!t
......
)(

-.J

c- ' __-:-:-~-'<4'~.;-:;r.~~,-~~_~_;

__ -":~-<-, >4."'':'-~1iilJlfir _T$ii-fiij5¥t :." ?l %iJ:liilf3!liiilifii!

:a:-

II)

DEVICE
ADDRESS SELECTION

STANDBY
"11

C'
c
CiJ

.oo.m,,';:, ~
DOs-DOlO

m
~

::!

ADDRESSES STABLE

..3

iii'

{}XXXXXXX

AVAV

::t
m

VIH
CE# (C)
VIL

STANDBY

:""

m
-<
-f

DATA VALID

AVPL = i,:LFL

VIH
OE# (G)

IQ
II)

-...
0

::a

V1L

V1H
BYTE# (F)
V1L

toLQV

II)

~
1§1

~
~

:::I
Q.

:.e

,~
0

'1:1
It

V1H
HIGH Z

DATA (000-00])
V1L

=
~ ~I
0
CUi!

DATA OUTPUT
ON DQO-D~

AvQv

II)

IiiiiJ

Lt I

~\\~

...

1111.-

I HIGH Z

DATA (DOS-DOlO)

»
:w "11c:o
~ ....
0
@
~

~
=
@
~

II)

m
X

DO,5/A-,

ADDRESS
INPUT

HIGH Z

290501-15

_.
::J
c[
@

A28F400BX-T IB

AC CHARACTERISTICS-WE # Controlled Write Operations(1)
Versions(4)
Symbol

A28F400BX-9O(9)
Unit

Parameter

Notes

Min

Max

tAVAV

twc

Write Cycle Time

tPHWL

tps

RP# High Recovery to
WE# Going Low

210

tELWL

tcs

CE # Setup to WE # Going Low

tPHHWH

tpHS

RP# VHH Setup to WE#
Going High

6,8

100

tVPWH

tvps

Vpp Setup to WE # Going High

5,8

100

tAVWH

tAS

Address Setup to WE #
Going High

tovwH

tos

Data Setup to WE# Going High

tWLWH

twp

WE # Pulse Width

tWHOX

tOH

Data Hold from WE# High

tWHAX

tAH

Address Hold from WE# High

tWHEH

tCH

CE# Hold from WE# High

tWHWL

tWPH

WE# Pulse Width High

tWHQV1

Duration of Word/Byte
Programming Operation

tWHQV2

Duration of Erase Operation (Boot)

tWHQV3

Duration of Erase Operation
(Parameter)

2,5

/Ls

2,5,6

0.4

2,5

0.4

tWHQV4

Duration of Erase Operation (Main)

2,5

0.7

tQWL

tVPH

Vpp Hold from Valid SRD

5,8

tQVPH

tpHH

RP# VHH Hold from Valid SRD

6,8

Boot-Block Relock Delay

7,8

tpHBR

100

8-29.

infel®

A28F400BX';'T IB

AC CHARACTERISTICS-WE# Controlled.· Write Oper,8tlons(1) (Continued)
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
characteristics during Read Mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify and margining operations.
3.. Refer to command definition table for valid AIN.
4. Refer to command definition table for valid DIN.
5. Program/Erase durations are measured to valid SRD data (successful operation, SA. 7 = 1l.
6. For Boot Block Program/Erase, RP# should be held at VHH until operation completes successfully.
7. Time tpHBR is required for successful relocking of the Boot Block.
8. Sampled but not 100% tested.
9. See Standard Test Configuration.

BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE Vpp = 120V ±5%
Max

A28F400BX-90
Typ(1)
,
1.5

10.5

Main Block
Erase Time

3.0

Main Block Byte
Program Time

1.4

5.0

0.7

2.5

Parameter

Notes

Boot! Parameter
Block Erase Time

Main Block Word
Program Time

NOfES:
1. 25'C
2. Excludes System-Level Overhead.

8-30

Min

Unit

~
I§!

~
~

=
~

'iii!

vee

POWER-UP
WRITE PROGRAM OR
& STANDBY
ERASE SETUP COMMAND

......

WRITE
VALID ADDRESS & DATA (PROGRAM)
OR ERASE CONFIRM COMMAND

AUTOMATED PROGRAM
OR ERASE DELAY

READ STATUS
REGISTER DATA

€:

WRITE READ ARRAY
COMMAND

V,H
ADDRESSES (A)

V,L

V,H
CE# (E)
V,L

V,H
OE# (G)
V,L

~---- tWHQYI,2,3,4

:IE

V,H

:1..

WE# (w)
V,L

CI.

1/1-

V,H
DATA (D/Q)
V,L

C!:

::I

1/1

iIn

VHH

'Ito

...
0

::I

V,L

2-CD

tYPWH

CI.

:IE

;;:
CD

.!.

If:~~"-------------------

6.SV
V,H
RP# (P)

(v)

VpPH

VPPL
V,H

N
C»
."
olio

III

r:p
~

V,L

290501-16

~
.....

III

~li! ~nlNiffFf~~'~~Riir1i( --li1iiiFi"~~

infel®

A28F400BX;'T/B

AC CHARACTERISTICS--CE#-CONTROLLED WRITE OPERATIONS(1,9)
Versions
Symbol
tAvAV
tpHEl

Parameter

twc

Write Cycle Time

tps

RP# High Recovery to CE # Going Low

A28F400BX-90(10)

Notes

tWlEl

tws

WE # Setup to CE # GOing Low

tPHHEH

tpHS

RP# VHH Setup to CE#Going High

tVPEH

tvps

Vpp Setup to CE # Going High

tAVEH

tAS

Address Setup to CE # Going High

tOVEH

tos

Data Setup to CE# Goiog High

tElEH

tcp

CE# Pulse Width

tEHOX

tOH

Data Hold from CE # High

tEHAX

tAH

Address Hold from CE # High

tEHwH

tWH

WE# Hold from CE# High

tEHEl

tCPH

CE # Pulse Width High

tEHOVl

Duration of Word/Byte Programming
Operation

tEHOV2

Duration of Erase Operation (Boot)

tEHOV3

Duration of Erase Operation (Parameter)

tEHOV4

Duration of Erase Operation (Main)

tOWl

tVPH

Vpp Hold from Valid SRD

tovPH

tpHH

RP# VHH Hold from ValidSRD

tPHBR

Boot:Block Relock Delay

6,8
5,8
3
4

2,5
2,5,6
2,5
2,5
.. 5,8
6,8
7

Mi,n

Unit

Max

90
210
0
100
100
60
60
60
0
10
10
30
7

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
p,s

0.4
0.4
0.7
0
0

s
s
s
ns
ns

100

NOTES:

1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination-of CE# and WE# in systems where
CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should
be measured relative to the CE# waveform.
2,3,4,5,6,7,8: Refer to. AC Characteristics for WE#-Controlled Write Operations.
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
10. See Standard Test Configuration.

8-32

©J c'"
~ c:CD.......
~

@
fiiiiI

vee POWER-UP
&: STANDBY

~
~

AUTOMATED PROGRAM
OR ERASE DELAY

READ STATUS
REGISTER DATA

WRITE READ ARRAY
COMMAND

V1H

V1L

il
fl

V1H
WE# (W)

V1L

l!)

V1H
OE# (G)

= 0© 1/13
~

ADDRESSES (A)

i•
=
~

'iii!
@
2:eJ

WRITE PROGRAM OR
ERASE SETUP COMMAND

WRITE
VALID ADDRESS &: DATA (PROGRAM)
OR ERASE CONFIRM COMMAND

V1L

\HaVl.2.3.4

V1H
CE# (E)
V1L

CD
DI
~

~~I

V1H
DATA (0/0)

~
CD

V1L

VHH

iil
~

,fIpHHEH--'

I/)

'0
m

6.5V
V1H
RP# (p)

V1L

a
...

2i'
a.

...=E
;::;:

tVPEH

»
N

VpPH

CI)

(V) VPPL
V1H

.!!.

V1L

290501-17

IX)

f..J
U)

><
!t
......
CD

--::-~'~~-:}:'-~~<::'~~'~

~~'lr

fiiliiiruilli .

inte!®

A28F400BX...T IB

ORDERING INFORMATION

I A I p I A 1-21,81 r,141 0 I 0' lsi X 1-191 0 I

L-r:=

I P!CK:GE
PA

= 44

LEAD PSOP

ACCESS SPEED
90

(ns)
290501-18

VALID. COMBINATIONS:
APA28F400B>,<·T90
APA28F400BX~B90

ADDITIONAL INFORMATION
A28F200BX Datasheet

Order Number
290500

28F200BX/28F002BX Datasheet

290448

28F200BX·Ll28F002BX·L Datasheet

290449

28F400BX·Ll28F004BX·L Datasheet

290450

AP·363 "Extended Flash BIOS Design for Portable Computers"

292098

ER·28 "ETOXTM III Flash Memory Technology"

204012

ER·29 "The Intel2/4·MBit Boot Block Flash Memory Family"

294013

8·34

A28F200BX-T IB
2-MBIT (128K x 16, 256K x 8) BOOT BLOCK
FLASH MEMORY FAMILY
Automotive
• x8/x16 Input/Output Architecture
- A28F200BX-T, A28F200BX-B
- For High Performance and High
Integration 16-bit and 32-bit CPUs
• Optimized High Density Blocked
. Architecture
- One 16 KB Protected Boot Block
- Two 8 KB Parameter Blocks
- One 96 KB Main Block
- One 128 KB Main Block
- Top or Bottom Boot Locations

•

Very High-Performance Read
- 90 ns Maximum Access Time
- 45 ns Maximum Output Enable Time

•

Low Power Consumption
- 25 rnA Typical Active Read Current

•

Deep Power-Down/Reset Input
- Acts as Reset for Boot Operations

• Automotive Temperature Operation
- -40·C to + 125·C
• Write Protection for Boot Block

• Extended Cycling Capability
-1,000 Block Erase Cycles

•

• Automated Word/Byte Write and
Block Erase
- Command User Interface
- Status Register
- Erase Suspend Capability

Industry Standard Surface Mount
Packaging
- JEDEC ROM Compatible
44-Lead PSOP

•

12V Word/Byte Write and Block Erase
- Vpp = 12V ± 5% Standard

•

ETOXTM III Flash Technology
-5V Read

•

Independent Software Vendor Support

• SRAM-Compatible Write Interface
• Automatic Power Savings Feature
- 1 rnA Typical Icc Active Current in
Static Operation
• Hardware Data Protection Feature
- Erase/Write Lockout during Power
Transitions

October 1993
Order Number: 290500-001

8-35

A28F200BX-T/B
Intel's 2-Mbit Flash Memory Family is an extension of the Boot Block Architecture which includes block-selective erasure, automated write and erase operations and standard microprocessor interface. The 2 Mbit Flash
Memory Family enhances the Boot Block Architecture by adding more density and blocks, x8/x16 input/output control, very high speed, low power, an industry standard ROM compatible pinout. The 2-Mbit flash family
allows for an easy upgrade to Intel's 4-Mbit Boot Block Flash Memory Family.
The Intel A2SF200BX-T/B are 16-bit wide flash memory offerings optimized to meet the rigorous environmental requirements of Automotive Applications. These high density flash memories provide user selectable bus
operation for either S-bit or 16-b.it applications. The A2SF200BX-T and A2SF200BX-B are 2,097,152-bit nonvolatile memories organized as either 262,144 bytes or 131,072 words of information. They are offered in 44Lead plastic SOP packages. The xS/x16 pinout conforms to the industry standard ROM/EPROM pinout. Read
and Write Characteristics are guaranteed over the ambient temperature range of -40·C to + 125·C.
These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
word/byte write and block erasure. The A2SF200BX-T provides block locations compatible with Intel's
MCS~1S6family, S0286, i3S6™, i4S6™, iS60TM and S0960CA microprocessors. The A2SF200BX-B provides
compatibility with Intel's S0960KX and S0960SX families as well as other embedded microprocessors.
The boot block includes a data protection feature to protect the boot code in critical applications. With a
maximum access time of 90 ns, these 2 Mbit flash devices are very high performance memories which
interface at zero-wait-state to a wide range of microprocessors and microcontrollers.
Manufactured on Intel's O.S micron ETOXTM III process, the 2-Mbit flash memory family provides world class
quality, reliability and cost-effectiveness at the2-Mbit density level.

S-36

A28F200BX-T/B

1.0 PRODUCT FAMILY OVERVIEW
Throughout this datasheet the A28F200BX refers to
both the A28F200BX-T and A28F200BX-B devices.
Section 1 provides an overview of the 2-Mbit flash
memory family including applications, pinouts and
pin descriptions. Section 2 describes -in detail the
specific memory organization. Section 3 provides a
description of the family's principles of operation. Finally, the family's operating specifications are described.

1.1

Main Features

The A28F200BX boot block flash memory family is a
very high performance 2-Mbit (2,097,152 bit) memory family organized as either 128-KWords (131,072
words) of 16 bits each or 256-Kbytes (262,144
bytes) of 8 bits each.
Five Separately Erasable Blocks including a hardware-lockable boot block (16,384 Bytes), two parameter blocks (8,192 Bytes each) and two main
blocks (1 block of 98,304 Bytes and 1 block of
131,072 Bytes) are included on the 2-Mbit family. An
erase operation erases one of the main blocks in
typically 3 seconds, and the boot or parameter
blocks in typically 1.5 seconds. Each block can be
independently erased and programmed 1,000 times.
The Boot Block is located at either the top
(A28F200BX-T) or the bottom (A28F200BX-B) of the
address map in order to accommodate different microprocessor protocols for boot code location. The
hardware lockable boot block provides the most
secure code storage. The boot block is intended to
store the kernel code required for booting-up a system. When the RP# pin is between 11.4V and 12.6V
the boot block is unlocked and program and erase
operations can be performed. When the RP# pin is
at or below 6.5V the boot block is locked and program and erase operations to the boot block are
ignored.
The A28F200BX products are available in the ROMI
EPROM compatible pinout and housed in the
44-Lead PSOP (Plastic Small Outline) package as
shown in Figure 3.
The Command User Interface (CUI) serves as the
interface between the microprocessor or microcontroller and the internal operation of the A28F200BX
flash memory.

Program and Erase Automation allows program
and erase operations to be executed using a twowrite command sequence to the CUI. The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations, including verifications, thereby unburdening the microprocessor or microcontroller. Writing of memory data is performed in word or
byte increments for the A28F200BX family typically
within 9 p.s which is a 100% improvement over previous flash memory products.
The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation:
Maximum Access Time of 90 ns (TACC) is achieved
over the automotive temperature range (- 40°C to
125°C), 10% Vcc supply voltage range and 100 pF
output load.
Ipp maximum Program current is 40 mA for x16
operation and 30 mA for x8 operation. Ipp Erase
current Is 30 mA maximum. Vpp erase and programming voltage is 11.4V to 12.6V (Vpp = 12V
± 5%) under all operating conditions. Typical Icc
Active Current of 25 mA is achieved.
The 2-Mbit boot block flash family is also designed
with an Automatic Power Savings (APS) feature to
minimize system battery current drain and allow for
very low power deSigns. Once the device· is accessed to read array data, APS mode will immediately put the memory in static mode of operation
where ICC active current is typically 1 mA until the
next read is initiated.
When the CE# and RP# pins are at Vcc and the
BYTE# pin is at either Vcc or GND the CMOS
Standby mode is enabled where Icc is typically
80 p.A.
A Deep Power-Down Mode is enabled when the
RP# pin is at ground minimizing power consumption
and providing write protection during power-up conditions. Icc current during deep power-down mode
is 50 ,xA typical. An initial maximum access time or
Reset Time of 300 ns is required from RP# switching until outputs are valid. Equivalently, the device
has a maximum wake-up time of 210 ns until writes
to the Command User Interface are recognized.

8-37

I
",

infel®

A28F200BX·TIB
When RP# is at ground the WSM is reset, the
Status Register is cleared and the entire device is
protected from being written to. This feature prevents data corruption and protects the code stored
in the device during system reset. The system Reset
pin can be tied to RP # to reset the memory to normal read mode upon activation of the Reset pin.
With on-chip program/erase automation in the
2 Mbit family and the RP# functionality for data protection, when-the CPU is reset and even if a program
or erase command is issued, the device will not recognize any operation until RP# returns to its normal
state.
For the A28F200BX, Byte-wide' or Word-wide Input/Output Control is possible by controlling the
BYT,E# pin. When the BYTE# pin is at a logic low
the device is in the byte-wide mode (x8) and data is
read and written through 00[0:7]. During the bytewide mode, 00[8: 14] are tri-stated and 0015/ A-1
becomes the lowest order address pin. When the
BYTE # pin is at a logic high the device. is in the
word-wide mode (x16) and data is read and written
through 00[0:15].

8-38

.1.2 Applications
The· 2"Mbit boot block flash family combines high
density, high performance, cost-effective flash memories with blocking and hardware protection capabilities. Its flexibility and Versatility will reduce costs
throughout the product life cycle. Flash memory is
ideal for Just-In-Time production flow, reducing system inventory and costs, and eliminating component
handling during the production phase. During the
product life cycle, when code updates'or feature enhancements become necessary, flash memory will
reduce the update costs by allowing either a user"
performed code change via floppy disk or a remote
code change via a serial link. The 2-Mbit boot block
flash family provides full function, blocked flash
memories suitable for a wide range of automotive
applications.

A28F200BX·T IB

0[7:0]

I\.

i.I'

',);,

A[10:0]

~:~:"

"\'

SRAM
2K x 8

II.

WE# '
OE#

---t
WR#
RO#
ALE
AO[15:0]'

8XC196KC

r-r-r--

CE#

WE#

.....

OE#
A15

CE#

ALE A15 A[14: 1]

lATCHES

JI..
A[13:0]

0[15:0]

II.

0[15:0]
y

BUSWIOTH

SRAMCS

A[15:11]

:::::::

EPLD

PORTS {
XTAll

l-----

ClK REAOY

, TClK

A28F200BX
FLASH
MEMORY
A14
A15
A16

REAOY

Vee
POWERGOOO
RP#

RESET#

Vee

Vee
MONITORING
EXTERNAl_
CIRCUIT
RESET

,
,PORT

D+iL _!:

RESET#

BYTE#

Vpp

....

Vpp
SWITCH

12V

290500-1

Figure 1. A28F200BX Interface to8XC196KC

8-39

A28F~OOBX-T/B

1.3 Piriouts
The A28F200BX 44·Lead PSOP pinout follo~s the
. industry standard F,lOM/EPROM pinout as shown in
Figure 2 with
upgrade to the 28F400BC (4-Mbit
flash family).

A28F400BX

A28F4008X

Vpp

RP#

A17
A7
As
A5
A4
A3
A2
Al

WE"
A8

As
A,o
A,.1
A4

CE;!!
GNO
OE;!!

000
OOs
001
009

CE#

'GND

APA28F200BX
44 LEAD PSOP
0.525" X 1.110"
TOP VIEW

A,4

BYTEII
GND

As
A9
Al0
All
A12
A13
A14.
A15
A1S
BYTE;!!
GNO

DOs

00,
00,4

DO,

DOs

D
I\,)

C»

OQ8~OQ15/A_1

°Oo-O~

)(

I\,)

.!t
.....
m

0
0

::!!
c...

a::I

:0
0
......
OJ

:J>
N

01
"T\
N
0
0

BYTE#

)(

CE#

::e

WE#

OE#

......

RP#

os
~
§

.~
~

IiiiiI

=
~
'iii!

'1Jf:

iii'

a::I

;

Ci1

0'
C')

~.
0

i
ID

<
-f
m
•

Ao -

Y-GATING/SENSING

A16

Vpp

""<.>g
~_Ql

""g

"''''
>-'"
'"><1'"
"''''
I'"
I'"
>-'"

I-

"I-

",:><

'"a....:

..:

'"a..

",""
~g

",--'
",,'"

'" -~

0'1-

",,,,,
....,.·u
>0.
'"""'"--'

m
en
0

:!!
"U

-f

N":

S
Z

-:><

:w
~

C::I
=

290500-4

-::J

€:
€I

A28F200BX-T IB

2.1 A28F200BX Memory Organization
2.1.1 BLOCKING
The A2SF200BX uses a blocked array architecture
to provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block ad,dress range and the Erase Setup and Erase Confirm
commands are written to the CUI. The A2SF200BX
is a random read/write memory, only erasure is performed by block.
2.1.1.1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of power failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being written or
erased when RP# is not at 12V. The boot block can
be erased and written when RP# is held at 12V for
the duration of the erase or program operation. This
allows customers to change the boot code when
necessary while providing security when needed.
See the Block Memory Map section for address locations of the boot block for the A2SF200BX-T and
A2SF200BX-B.
2.1.1.2 Parameter Block Operation
The A2SF200BX has 2 parameter blocks (S-Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The parameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not have the hardware write protection feature
that the boot block has. The parameter blocks provide for more efficient memory utilization when dealing with parameter changes versus regularly blocked
devices. See the Block Memory Map section for address locations of the parameter blocks for the
A2SF200BX-T and A2SF200BX-B.

2.1.1.3 Main Block Operation
Two main blocks of memory exist on the
A2SF200BX (1 x 12S-Kbyte block and 1 x 96-Kbyte
block). See the following section on Block Memory
Map for the address location of these blocks for the
A2SF200BX-T
and A2SF200BX-B products.
2.1.2 BLOCK MEMORY MAP
Two versions of the A2SF200BX product exist to
support two different memory maps of the array
blocks in order to accommodate different microprocessor protocols for boot code location. The
A2SF200BX-T memory map is inverted from the
A2SF200BX-B memory map.
2.1.2.1 A28F200BX·B Memory Map
The A2SF200BX-B· device has the 16-Kbyte boot
block located from OOOOOH to 01 FFFH to accommodate those microprocessors that boot from the bottom of the address map at OOOOOH. In the
A2SF200BX-B the first S-Kbyte parameter block resides in memory space from 02000H to 02FFFH.
The second S-Kbyte parameter block resides in
memory space from 03000H to 03FFFH. The
96-Kbyte main block resides in memory space from
04000H to OFFFFH. The 12S-Kbyte main block resides in memory space from 10000H to 1FFFFH
(word locations). See Figure 4.
(Word Addresses)
1FFFFH

128·Kbyte MAIN BLOCK
10000H
OFFFFH

96·Kbyte MAIN BLOCK
04000H
03FFFH

8·Kbyte PARAMETER BLOCK
03000H
02FFFH
02000H
01FFFH

8·Kbyte PARAMETER BLOCK

16·Kbyte BOOT BLOCK
OOOOOH

Figure 4. A28F200BX-B Memory Map

S-43

intel®

A28F200BX-T/B

2.1.2.2 A28F200BX-T Memory Map
The A28F20.DBX-Tdevicehas the 16-Kbyte boot
block located from 1EOOOH to 1FFFFH to accommodate those microprocessors that boot from the top
of the address map. In the A28F200BX-T the first
8 Kbyte parameter block resides in memory space
from 1DOOOH to 1DFFFH. The se.cond 8-Kbyte parameter block resides in memory space .from
1COOOH to 1CFFFH. The 96-Kbyte main block resides in memory space from.1 OOOOH to 1BFFFH.
The 128-Kbyte main block resides in memory space
from OOOOOH to OFFFFH as shown in Figure 5.
(Word Addresses)

lFFFFH
lS·Kbyte BOOT BLOCK

1EOOOH
lDFFFH
lDOOOH
lCFFFH
lCOOOH
lBFFFH'

B·Kbyte PARAMETER BLOCK

The CUI allows for 100% ntAevel control inputs,
fixed power supplies during erasure and programming, and maximum EPROM compatibility.
In the absence .of high voltage on the Vpp pin, the
2-Mbit boot block flash family will only. successfully
execute the following commands: Read. Array, Read
Status Register, Clear Status Register and Intelligent Identifier mode. The device provides standard
EPROM read, standby and output disable operations. Manufacturer Identification and Device Identification data can be accessed through the CUI or
through the standard EPROM A9 high voltage access (VID) for PROM programming equipment.
The same EPROM read, standby and output disable
functions are available. when high voltage is applied
to the Vpp pin. In addition, high voltage on Vpp allows write and erase of the device. All functions associated with altering memory contents: write and
erase, Intelligent Identifier read and Read Status are
accessed via the CUI.

B·Kbyte PARAMETER BLOCK

9S·Kbyte MAIN BLOCK

10000H

OFFFFH
12B·Kbyte MAIN BLOCK

The purpose of the Write State Machine (WSM) is to
completely automate the write and erasure of the
device. The WSM will begin operation' upon receipt
of a signal from the CUI and will report status back
through a Status Register. The CUI will handle the
WE # interface to the data and address latches, as
well as system software requests for status while the
WSM is in operation.

OOOOOH

3.0

Figure 5. A28F200BX-T Memory Map

3.1 Bus Operations

PRODUCT FAMILY PRINCIPLES
OF OPERATION

Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycleS.
'

Flash memory augments EPROM functionality with
in-circuit electrical write and erase. The 2-Mbit flash
family utilizes a Command User Interface (CUI) and
internally generated and timed algorithms to simplify
write and erase operations.

8·44

A28F200BX-T IB

= VI H)

Table 1. Bus Operations for WORD-WIDE Mode (BYTE #
Mode

Notes

RP#

CE#

OE#

WE#

Vpp

1,2,3

VIH

VIL

VIH

DOUT

Output Disable

VIH

VIL

VIH

HighZ

Standby

VIH

HighZ

Read

DQO-15

Deep Power-Down

VIL

HighZ

Intelligent Identifier (Mfr)

VIH

VIL

VIH

VID

VIL

0089H

4,5

VIH

VIL

VIH

VID

VIH

2274H
2275H

6,7,8

VIH

VIL

VIH

VIL

DIN

Intelligent Identifier (Device)
Write

Table 2. Bus Operations for BYTE-WIDE Mode (BYTE#
Mode
Read

Vld

RP#

CE#

OE#

WE#

A-1

Vpp

DQO-7

DQS-14

1,2,3

VIH

VIL

VIH

DOUT

HighZ

Output Disable

Deep Power-Down
Intelligent Identifier (Mfr)

VIH

VIL

VIH

HighZ

VIL

HighZ

VIH

VIL

VIH

VID

VIL

89H

HighZ

74H
75H

HighZ

DIN

HighZ

Standby

4,5

VIH

VIL

VIH

VID

VIH

6,7,8

VIH

VIL

VIH

VIL

Intelligent Identifier
(Device)
Write

Notes

NOTES:
1. Refer to DC Characteristics.
2. X can be VIL or VIH for control pins and addresses, VPPL or VPPH for Vpp.
3. See DC characteristics for VPPL, VPPH, VHH, VIO voltages.
4. Manufacturer and Device codes may also be accessed via a CUI write sequence. A1-A17 = X.
5. Device 10 = 2274H for A28F200BX-T and 2275H for A28F200BX-B.
6. Refer to Table 3 for valid DIN during a write operation.
7. Command writes for Block Erase or Word/Byte Write are only executed when Vpp = VPPH.
8. To write or erase the boot block, hold RP# at VHH.
9. RP# must be at GND ±0.2V to meet the 80 ",A maximum deep power-down current.

3.2 Read Operations

3.2.1 READ ARRAY

The 2-Mbit boot block flash family has three user
read modes; Array, Intelligent Identifier, and Status
Register. Status Register read mode will be discussed in detail in the "Write Operations" section.

If the memory is not in the Read Array mode,. it is
necessary to write the appropriate read mode command to the CUI. The 2-Mbit boot block flash family
has three control functions, all of which must be logically active, to obtain data at the outputs. Chip-Enable CE # is the device selection control. Reset!
Power-Down RP# is the device power control. Output-Enable OE# is the DATA INPUT/OUTPUT
(DO[0:15] or DO[O:7]) direction control and when
active is used to drive data from the selected memoryon to the 1/0 bus.

During power-up conditions (VCC supply ramping), it
takes a maximum of 300 ns from when VCC is at
4.5V minimum to valid data on the outputs.

8-45

intel®

A28F200BX-T/B

3.2.1.1 Output Control
With OE # at logic-high level (VIH), the output from
the device is disabled and data input/output pins
(00[0:15] or 00[0:7]) are tri-stated. Data input is
then controlled by WE # .
3.2.1.2 Input Control
With WE# at logic-high level (VIH), input to the device is disabled. Data Input/Output pins (00-[0:15]
or 00[0:7)) are controlled by OE#.
3.2.2 INTELLIGENT IDENTIFIERS
The manufacturer and device codes are read via the
CUI or by taking the Ag pin to 12V.Writing 90H to
the CUI places the device into Intelligent Identifier
read mode. A read of location OOOOOH outputs the
manufacturer's identification code, 0089H, and location 00001H outputs the device code; 2274H for
A28F200BX-T, 2275H for A28F200BX-B. When
BYTE # is at a. logic low only the lower byte of the
above signatures is read and D01S/A-1 is a "don't
care" during Intelligent Identifier mode. A read array
90mmand must be written to the CUI to return to the
read array mode.

3.3 Write Operations
Commands are written to the CUI using standard microprocessor write timings. The CUI s.erves as the
interface between the microprocessor and the internal chip operation. The CUI can decipher Read Array, Read Intelligent Identifier, Read Status Register,
Clear Status Register, Erase and Program commands. In the event of a read command, the CUI
simply points the read path at either the array, the
Intelligent Identifier, or the status register depending
on the specific read command given. For a program
or erase cycle, the CUI informs the write state machine that a write or erase has been requested. During a program cycle, the write State Machine will
control the program sequences and the CUI will only
respond to status reads. During an erase cycle, the
CUI will respond to status reads and erase suspend.
After the Write State Machine has completed its
task,it will allow the CUI to respond to its full command set. The CUI will stay in the current command
state until the microprocessor issues another command.

Depending upon the application, the system designer may choose to make the Vpp power supply
sWitchable,' available only when merpory updates
are desired. The· system designer can also choose
to "hard-wire" Vpp to 12V. The 2-Mbit boot plock
flash family is designed to accommodate either design practice. It is strongly recommencled that RP#
be tied to logical Reset for data protection' during
unstable CPU reset function as described in the
"Product Family Overview" section.
3.3.1 BOOT BLOCK WRITE OPERATIONS
In the case of Boot Block modifications (write and
erase), RP# is set to VHH = 12V typically, in addition to Vpp at high voltage. However, if RP# is not at
VHH when a program or erase operation of the boot
block is attempted, the corresponding status register
bit (Bit 4 for Program and Bit 5 for Erase, refer to
Table 4 for Status Register Definitions) is set to indicate the failure to complete the operation.
3.3.2 COMMAND USER INTERFACE (CUI)
The Command User Interface (CUI) serves as the
interface to the microprocessor. The CUI points the
read/write path to the appropriate circuit block as
described in the previous section. After the WSM
has completed its task, it will set the WSM Status bit
to a "1", which will also allow the CUI to respond to
its full command set. Note that after the WSM has
returned control to the CUI, the CUI will remain in its
current state.
3.3.2.1 Command Set
Command
Codes

Device Mode

00
10
20
40
50
70
90
BO
DO
FF

Invalid/Reserved
Alternate Program Setup
Erase Setup
Program Setup
Clear Status Register
Read Status Register
Intelligent Identifier
Erase Suspend
Erase Resume/Erase Confirm
Read Array

3.3.2.2 Command Function Descriptions
The CUI will' successfully initiate an erase or write
operation only when Vpp is within its voltage range.

8-46

Device operations are selected by writing specific
commands into the CUI. Table 3 defines the 2-Mbit
boot block flash family commands.

A28F200BX·TlB.
Table 3. Command Definitions
Command

Bus
Notes
First Bus Cycle
Second Bus Cycle
Cycles
Req'd
8
Operation Address Data Operation Address Data

Read Array/Reset

Write

Intelligent Identifier

2,4

Write

90H

Read

110

Read Status Register

Write

70H

Read

SRD

Write

50H

Write

20H

Write

DOH

Clear Status Register

Erase Setup/Erase Confirm

Word/Byte Write Setup/Write

6, 7

Erase Suspend/Erase Resume

Alternate Word/Byte Write Setup/Write

6,7

FFH

Write

40H

Write

BOH

Write

DOH

Write

10H

Write

NOTES:
1. Bus operations are defined in Tables 1, 2.
2. IA = Identifier Address: OOH for manufacturer code, 01 H for device code.
3. SRD = Data read from Status Register.
4. 110 = Intelligent Identifier Data.
.
Following the Intelligent Identifier Command, two read operations access manufacturer and device codes.
5. BA = Address within the block being erased.
6. PA = Address to be programmed.
PO = Data to be programmed at location PA.
7. Either 40H or 10H command is valid.
a. When writing commands to the device, the upper data bus [ooa-DQ15] = X which is either Vee or Vss to avoid burning
additional current.

Invalid/Reserved

Read Status Register (70H)

These are unassigned commands. It is not recommended that the customer use any command other
than the valid commands specified above. Intel reserves the right to redefine these codes for future
functions.

Read Array (FFH)

The device automatically enters this mode after program or erase has completed.

This single write command points thE! read path at
the array. If the host CPU performs a CE#/OE#
controlled read immediately following two-write sequence that started the WSM, then the device will
output status register contents. If the Read Array
command is given after Erase Setup the device is
reset to read the array. A two Read Array command
sequence (FFH) is required to reset to Read Array
after Program Setup.

Intelligent Identifier (90H)
After this command is executed, the CUI points the
output path to the Intelligent Identifier circuits. Only
Intelligent Identifier values at addresses 0 and 1 can
be read (only address AO is used in this mode, all
other address inputs are ignored).

Clear Status Register (50H)
The WSM 'can onl'y set the Program Status and
Erase Status bits in the status register, it can not
clear them. Two reasons exist for operating the
status register in this fashion. The first is a synchronization. The WSM does' not know when the host
CPU has read the status register, therefore it would
not know when to clear the status bits. Secondly, if
the CPU is programming a string of bytes, it may be
more efficient to query the status register after programming the .string. Thus, if any errors exist while
programming the string, the status register will return
the accumulated error status.

8-47

A28F200BX~T1B

intel®

Program Setup (40H or 10H)

This command simply sets t.heCUI into a state such
that the nf3xt write will load the address and data
regi~ters. Either 4:OH or 10H can be used for. Program Setup. Both commands are ·included to accommodate efforts to .achieve an industry standard
command code set.
Program

The second write after the program setup' command, .
will latch addresses and data. Also, the CUI initiates
the. WSMto begin execution of the program algorithm. While the WSM finishes the algorithm, the device will output Status Register contents. Note that
the WSM cannot be suspended during programming.
Erase Setup (20H)
Prepares the CUI for the Erase' Confirm' command.
No other. action is taken. If the next command is not
an Erase Confirm command. then the CUI will set
both the Program Status and Erase Status bits of the
Status ,Register to a "1", place the device into the
, Read Sta~us Register state, and wait for another
c:ommand.
EraSe Confirm (DOH) .

If the previous c.ommand was an Erase Setup command, then the CUI will enable the WSM to erase, at
the salTle time closing the address and data latches,
, and respond only to the Read Status Register and
Erase Suspend commands. While the. WSM is executing, 'the device will output Status Register data
when DE # is toggled low. Status. Register data can
only be updated by toggling either OE# or CE# low.
Erase Suspend (BOH) .

This command only has meaning while. the WSM is
executing an Erase operation, and therefore will only
be responded to during an erase operation. After
this command has been executed, the CUI will set.
an output that directs the WSM to suspend Erase
operations, and then return to· responding to only
Read Status Register or to the Erase Resume com. mands. OnCe the WSM has reached the Suspend
state, it.will set an output into the cut Which allows
the CUI to respond to the Read Array, Read Status
Register, and Erase Resume commands. In this
mode, the CU I will. not respond to any other commands. The WSM will also set the WSM Status bit to
a "1". The WSM'wili continue to run, idling in the
SUSPENID state, regardless of the state of all input

8-48

control pins, witli the exclusion of RP#. RP# will
immediately shut down the WSM and the remainder
of the chip. Ouring a suspend operation, the data
and address latches will remain closed, but the address pads are able to drive the address into the
read path.
Erase Resume (DOH)

This command will cause the CUI to clear the Suspend state and set the WSM Status bit to a "0", but
only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.

3.3.3 STATUS REGISTER
The 2-Mbit bootblock flash family contains a status
register which may be read to determine when a program or erase operation is complete, and whether
that operation completed successfully. The status
register may be read at any time by writing the Read
Status command to the CUI. After writing thiS command, all subsequent Read operations output data
from the status register, until another command is
.written to the CUI..A Read Array command must be
,written to the CUI to return to the Read Array mode.
The status register bits are output on 00[0:7]
whether the device is in the byte-wide (x8) or wordwide (x16) mode. In the word-wide mode the upper
byte, 00[8:15] is set to OOH during a Read Status
command. In the byte-wide mode, 00[8:14] are tristated and' 00151 A -1 retains the low order ad.
dress function~
It should be noted that the contents of the status'
register are latched 6n the falling edge of OE # or
CE # whichever occurs last in the read cycle. This
prevents possible bus errors which might occur if the
contents of the status register change while reading
the status register. CE#. or OE# must be toggled
with each subsequent status read; or the completion
of a program or erase operation will not be evident.
The Status Register is the interface between the microprocessor and the Write State Machine (WSM).
When the WSM is active, this register will indicate
the status of the WSM, and will also. hold the bits
indicating whether or not the wsM was successful in
performing the desired operation. The. WSM sets
status bits "Three" through"Seven" and clears bits
"Six" and "Seven", but cannot clear status bits
"Three" through "Five". These ,bits can only be
cleared by the. controlling CPU through the use of
the Clear Status Regi,ster command.

infel~

A28F2008X·T /8

3.3.3.1 Status Register Bit Definition
Table 4. Status Register Definitions

I I
WSMS

ESS

785

PS
4

NOTES:
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy

Write State Machine Status bit must first be checked to
determine byte/word program or block erase completion,
before the Program or Erase Status bits are checked for
success.

SR.6 = ERASE SUSPEND STATUS
1 = Erase Suspended
= Erase in Progress/Completed

When Erase Suspend. is issued, WSM halts execution
and sets both WSMS and ESS bits to "1". ESS bit remains set to "1" until an Erase Resume command is issued.

SR.5 "" ERASE STATUS
1 = Error in Block Erasure
o =. Successful Block Erase

When this bit is set to "1". WSM has applied the maximum number of erase pulses to the block and is still unable to successfully perform an erase verify.

SR.4 = PROGRAM STATUS
1 = Error in Byte/Word Program
o = Successful Byte/Word Program

When this bit is set to "1", WSM has attempted but failed
to Program a byte or word.

SR.3 = Vpp STATUS
1 = Vpp Low Detect; Operation Abort
.0 = VppOK

The Vpp Status bit, unlike an AID converter, does not
provide continuous indication of Vpp level. The WSM· interrogates the Vpp level only after the byte write or block
erase command sequences have been entered and informs·the system if Vpp has not been switched on. The
Vpp Status bit is not guaranteed to report accurate feedback between VPPL and VPPH.

SR.2-SR.O
MENTS

3.3~3.2

RESERVED FOR FUTURE ENHANCE-

Clearing the Status Register

Certain bits in the status register are set by the write
state machine, and can only be reset by the system
software. These bits can indicate various failure conditions. By allowing the system software to control
the resetting of these bits, several operations may
be performed (such as cumulatively programming
several bytes or erasing multiple blocks in sequence). The status register may then be read to
determine if an error occurred during that programming or erasure series. This addl;l flexibility to the
way the device may be programmed or erased. To
clear the status register, the Clear Status Register
command is written to the CUI. Then, any other
command may be issued to the CUI. Note again that
before a read cycle can be initiated, a Read Array
command must be written to the CUI to specify
whether the read data is to come from the array,
status register, or Intelligent Identifier.

These bits are reserved for future use and should be
masked out when polling the Status Register.

3.3.4 PROGRAM MODE
Program is executed by a two-write sequence. The
Program Setup command is written to the CUI followed by a second write which specifies the address
and data to be programmed. The write state machine will execute a sequence of internally timed
events to:
1. Program the desired bits of the addressed memory word (byte), and
2. Verify that the desired bits are sufficiently programmed
Programming of the memory results in specific bits
within a byte or word being changed to a "0".
If the user attempts to program "1 "s, there will be no
change of the memory cell content and no error occurs.
Similar to erasure, the status register indicates
whether programming is complete. While the program·sequence is executing, bit 7 of the status register is a '~O". The status register can be polled by
8-49

toggling either CE # or OE # to determine when the
program sequence is complete. Only. the Read
Status Register command is .valid while program~
ming is active.
,

When programming is complete, the status bits,
Which indicate whether the. program operation was
successful, should be Checked. If the programming
operation was unsuccessful, Bit 4 of the status register is set to a "1" to indicate a Program Failure. If Bit
3 is set then Vpp was not within acceptable limits,
and the WSM will not execute the programming sequence.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after programming is completed; however, it
must be recognized that reads from the memory,
status register, or Intelligent Identifier cannot be ac.complished until the CUI ·is given the appropriate
commalJd. A Read Array command must first be given before memory contents can be read. ,
Figure 6 shows a system software flowchart for device byte programming operation. Figure 7 shows a
similar flowchart for device word programmingoperation (A28F200BX-only).
3.3.5 ERASE MODE
Erasure of a single block is initiated by writing the
Erase Setup and Erase Confirm commands to' the
CUI, along with the addresses, A[12:16], identifying
the block to be erased; These addresses are latched
internally when the Erase Confirm command is issued. Block erasure results in all bits within the bldc~
being set to "1".

,
The WSM will execute a sequence of internally
timed eyents to:
1. Program all qits within the block
2. Verify that all bits within the block are sufficiently
programmed
3. Erase all. bits within the block and
4. Verify that a:1I bits within the block are sufficiently
erased
While the erase sequence is executing, Bit 7 of the
status register is a "0".
When the statlJs register indicates that erasure is
complete, the status bits, which indicate whether the
erase operation was successful, should be checked.
If the erasure operation was unsuccessful, Bit 5 cif
the status register is set to a "1" to indicate an
Erase Failure. If Vpp was not within acceptable limits
after, the Erase Confirm command is issued, the
WSM will not axecute an erase sequence; instead,
Bit 5 oUhe status register is set to a "1" to indicate

8-50

an Erase Failure, and Bit 3 is set to a "1~' to identify
that Vpp.supply voltage was I)ot within acceptable
'limits.
'
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after erasure is completed; however, it must
be, recogniz8d that reads, from the memory array,
status register, or Intelligent Identifier can not be ac.
complished until the CUI is given the appropriate
command. A Read Array command must first be given before memory contents can be read.
Figure 8 shows a system software flowchart for
Block Erase operation.
3.3.5.1 Suspendlnlil and Resuming Erase
Since an erase operation typically requires 1.5 to 3
~econds to complete, an Erase Suspend command
is provided. This allows erase-sequence interruption
in order to read data from another block of the memory. Once the erase sequence is started, writing the
Erase Suspend command to the CUI requests that
the Write State Machine (WSM) pause the erase Sequenceat a predetermined point in the erase algorithm. The status register must be read to determine
when the erase operation has been suspended.
At this pOint, a Read Array command can be written
to the CUI. in order to read data from blocks other
than that which is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register operation.
Figure 9 shows a system software flowchart detailing the operation.
During Erase Suspend mode, the chip' can go into a
pseudo-standby mode by taking CE# to VIH and the
active current is now a maximum of 10 rnA. 'If the
chip is enabled while in thi!! mode by taking CE # to
. VIL, the Erase Resume command can be issued to
resume the erase operation,
'
Upon completion of reads from any block other than
the block being erased, the' Erase Resume command must be issued. When the Erase Resume
command is given, the WSM will continue with'the
erase sequence and comp,lete erasing the block. As
with the end of erase, ttiestatus register must be
read, cleared, and the next instruction issued in order to continue.
3.4.6 EXTENDED CYCLING
Intel .has designed 'extended. cycling capability into
its ETOX III flash memory. technology. The 2-Mbit
boot block flash farT)ily is designed fof 1,000 pro.
gram/erase cycles on each of the five blocks; The
combination of low electriC fields, ctean oxide processing and minimized oxide area per memory cell
subjected to the tunneling electric field, results in
very high cycling capability,

intel~

A28F200BX-T IB

Bus
Operation

Command

Comments

Write

Setup
Program

Data = 40H
Address = Byte to be
programmed

Write

Program

Data to be programmed
Address = Byte to be
programmed

Read

Status Register Data.
Toggle OE # or CE # to update
Status Register

Standby

CheckSR.7
1 = Ready, 0

Busy

Repeat for subsequent bytes.
Full status check can be done after each byte or after a
sequence of bytes.

Write FFH after the last byte programming operation to
reset the device to Read Array Mode.

290500-5

Full Status Check Procedure

Bus
Operation

Comments

Command

Vpp Range
Error

Standby

CheckSR.3
1 = V PP Low Detect

Byte Pro9ram

Standby

Check SR.4
1 = Byte Program Error

Error

SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.

290500-6

SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple bytes are programmed
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.

Figure 6. Automated Byte Programming Flowchart

8-51

intet®

A28F200BX"T/B

Bus
Operation

Command

Comments

Write

Setup
Program

Data = ,\OH
Address = Word to be
programmed

Write

Program

Data to be programmed
Address = Word to be
programmed

Read

Status Register Data.
Toggle OE # or CE # to update
Status Register

Standby

CheckSR.7
1 = Ready, 0

= Busy

Repeat for subsequent words.
Full statos check can be done after each word or after a
sequence of words.

290500-7

Write FFH after the last word programming operation to
reset the device to Read Array Mode.

Full Status Check ProceduJre

Bus
Operation

Command

Comments

Vpp Range
Error

Standby

Check SR.3
1 = Vpp Low Detect

Byte Program

Standby

Check SR.4
1= Worlj Program Error

-Error

SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.

290500-8
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple words are programmed
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.

Figure 7. Automated Word Programming Flowchart

8-52

A28F200BX-T /B

Bus
Operation

Command

Comments

Write

Setup
Erase

Data = 20H
Address = Within block to be
erased

Write

Erase

Data = DOH
Address = Within block to be
erased

Read

Status Register Data.
ToggleOE# or CEll' to update
Status Register

Standby

Check SR.7
1 = Ready, 0 = Busy

Repeat for subsequent blocks.
Full status check can be done after each block or after a
sequence of blocks.

290500-9

Write FFH after the last block erase operation to reset the
device to Read Array Mode.

Full Status Check Procedure
Bus
Operation
Vpp Range

Error

Command

Comments

Standby

CheckSR.3
1 = Vpp Low Detect

Standby

Check SR.4,5
Both 1 = Command Sequence
Error

Standby

CheckSR.5
1 = Block Erase Error

SR.3 MUST be cleared, if set during an erase attempt,
before further attempts are allowed by the Write State
Machine.
•

290500-10
SR.5 is only cleared by the Clear Status Register
Command, in cases where multiple blocks are .erased
befere full status is checked:
[1

If error is detected, clear the Status Register before
attempting retry or other error recovery.

Figure 8. Automated Block Erase Flowchart
8-53

intel®

A28F200BX-T/B

Bus
Operation

Write

Command

Erase
Suspend

Comments

Data

= SOH

Read

Status Register Data.
ToggleOE# orCE# to
update Status Register

Standby

Check SR.7
1 = Ready

Standby

Check SR.6
1 = Suspended

Write

Read Array

Read

Write

Data

= FFH

Read array data from block
other than that being
erased.

Erase Resume

Data = DOH

290500-11

Figure 9. Erase SuspendlResume Flowchart

3.4 Power Consumption
3.4.1 ACTIVE POWER
With CE# at a logic-low level and RP# ata logichigh level, the device is placed in the active mode.
The device Icc current· is a maximum of 65 rnA at
1,0 MHzwith TI.L input signals.

3.4.2 AUTOMATIC POWER SAVINGS
Automatic Power Savings (APS) is a low powerfeature .during active mode of operation. The 2-Mbit
family of products incorporate Power Reduction
Control (PRC) circuitry which basically allow8')the device to put itself into a low current state when it is
not being accessed. After data is read from the
memory array, PRC logic controls the device's power consumption by entering the APS mode where
8-54

maximum Icc current is 3 rnA and typical Icc current
is 1 rnA. The device stays in this static state with
outputs valid until a new location is read.

3.4.3 .STANDBY POWER
With CE # at a logic-high level (VIH), and the CUI in
read mode, the memory is placed in standby mode
where the maximum Icc standby current is. 100 p.A
with CMOS input signals. The standby operation disables much of the device's circuitry and substantially
reduces device power consumption. The outputs
(00[0:t5]or 00[0:7]) are placed ina high-impedance state independent of the status of the OE#
signal. When the 2-Mbit boot block flash family is
deselected during erase or program functions, the
devices will continue to perform the. erase or program function and consume program or erase active
power until program or erase is completed.

A28F200BX-T/B

3.4.4 RESETIDEEP POWER-DOWN
The 2-Mbit boot block flash family has a RP# pin
which places the device in the deep power-down
mode. When RP# is at a logic-low (GND ± 0.2V), all
circuits are turned off and the device typically draws
a maximum 80 p.A of Vee current.
During read modes; the RP# pin going low deselects the memory and places the output drivers in a
high impedance state. Recovery from the deep power-down state, requires a minimum of 300 ns to access valid data (tpHQV)'
During erase or program modes, RP# low will abort
either erase or program operation. The contents of
the memory are no longer valid as the data has been
corrupted by the RP# function. As in the read mode
above, all internal Circuitry is turned:off to achieve
the low current level.
.
RP# transitions to VIL or turning power off to the
device will clear the status register.
This use of RP# during system re~et is important
with automated writel erase devices. When the system comes out of reset it expects to read from the
flash memory; Automated flash' memories provide
status information when accessed during writel
erase modes. If a CPU reset occurs with no flash
memory reset, proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data. Intel's
Flash Memories allow proper CPU initialization following a system reset through the use of the RP#
input. In this application RP# is controlled by the
same RESET# signal that resets the system CPU.

3.5 Power-Up Operation
The 2-Mbit boot block flash family is designed to
offer protection against accidental block ,erasure or
programming during power transitions. Upon powerup the 2-Mbit boot block flash family is indifferent as
to which power supply, Vpp or Vee, powers-up first.
Power suppy sequencing is not required.
The 2-Mbit boot block flash family ensures the CUI is
reset to the read mode on power-up.
In addition, on power-up the user must either drop
CE# low or present a I)ew address to ensure valid
data at the outputs.
A system designer must' guard against spurious
writes for Vee voltages above VLKO when. Vpp is
active. Since both WE# and CE# must be low for a
command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides
an added level of protection Sirce alteration of memo.

ory contents can only occur after successful completion of the two-step command sequences. Finally, the device is disabled until RP# is brought to VIH,
regardless of the state of its control inputs. This feature provides yet another level of memory protection.

3.6 Power Supply Decoupllng
Fiash memory's power switching characteristics require careful device decoupling methods. System
designers are interested in 3 supply current issues:
• Standby current levels (lees)
• Active current levels (lecR)
• Transient peaks produced by falling and rising
edges of CE # .
Transient current magnitudes depend on the device
outputs' capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 p.F ceramic capacitor
connected between each Vee andGND",and between its Vpp and GND. These high frequency, lowinherent inductance capaCitors should be placed as
close as possible to the package leads.
3.6.1 Vpp TRACE ON PRINTED CIRCUIT
BOARDS
Writing to flash memories while they reside in the
target system, requires special consideration of the
Vpp power supply trace by the printed circuit board.
designer. TheVpp pin supplies the flash memory'
cell's current for programming and' erasing. One
should use similar trace widths and layout considerations given to the Vec power supply trace. Adequate Vpp supply traces and decoupling will decrease spikes and overshoots:
3.6.2 Vee. Vpp AND RP# TRANSITIONS
The CUI latches commands as issued by system
software and is not altered by Vpp or CE# tran.!
sitions or WSM actions. Its state upon power-up, after 'exit from deep power-down mode or after Vee
transitions below VLKO (Lockout voltage); is Read
Array mode.
After any word/byte write. or block erase operation is
complete and even' after Vpp transitions down to
VPPL, the CUI must be reset to Read Array mods-via
the Read Array command when accesses to the
flash memory are desired.

8-55

A28F20QB)(-T/8

'ABSOLUTE, MAXIMUM RATINGS·

+ 125°C

Storage Temperature ..•.•••... -,65°C to

+ 125°C
+ 150°C

NOTICE: This data sheet coritains information on
products in t!1e sampling and initial production phasel!l
of _development. The spec::ifications are subject to
change without notice. Verify with your local Intel
-Sales office that you !lave the latest data: sheet before finalizing a deSign.

Voltage on Any Pin
(except Yee,Ag. Vppand RP#)
with Respect to GND .•..•••• - 2.0V to

+ 7.0V(2)

• WARNING: Stressing the device beyond the "Absolute
Maximu,;, Ratings" may cause permanent -damage.
, These are -stress ratings only. Ope,.,tion beyond the
"Operaflng Conditions" is not recommended, and extended exposurtJ beyond the "Operating Conditions"
may affect device reliability.

AUtomatic Operating Temperature '
During Read ••••. ' ...•.•.•.•. -40°C to
During Block Erase
and Word/Byta Write •....•.• - 4QoC to
TemPerature Under Bias ..•.• -40°C to

+ 125°C

Voltage on Pin RP# or Pin Ag
with Respect to GND ...•. - 2.0V to

+ 13.5V(2. 3)

Vpp Program Voltage with ,Respect
to GND during Block Erase
, and Word/Byte Write ..... - 2.0V to

+ 14.0V(2, 3)

Vee Supply Voltage
with Respect to GND ....•... - 2.0Y to

+ 7.0V(2)

Output Short Circuit Current ......•.•.••. 100 mA(4)
NOTES~

1. Operating temperature is for automotive product defined by this specification.
2. Minimum Qe voltage is ~0.5V on input/output pins. During transitions. this level may undershoot to -2.0V for periods
<20 ns. Maximum be voltage on input/outpUt pins is Vee -I: 0.5V w!1ich. duriogtransitionll, may overshoot to Vee +2.0V
for periods < 20 ns.
,
3. Maximum DC voltage-on Vpp may overshoot to + 14.0V for periods <20 'ns. Maximum DC voltage 01'1 RP# or Ag may
overshoot to 13.5V for periods <20ns.
'
4. Output shorted for no more than one second. No more than one output shorted at a time.

OPERATING CONDITIONS
Symbol

Parameter

Operating Temperature

Vee

Vee Supply Voltage (10%)

Notes

Min

Max

Units

-40

125

°C

4.50

5.50

DC CHARACTERISTICS
Symbol

Parameter

Notes

Min

Typ

Max

Unit

III

Input Load Current

±1.0

p.A

Vee == Vee Max
VIN= Vee or GND

ILO

Output Leakage Current

±10

p.A

Vee = Vee Max
VOUT = VeeorGND

lees

Vee Standby Current

1,3

1.5

rnA

Vee == Vee Max
CE#= RP#
VIH

130

p.A

8·56

Test Condltio,n

' Vee = Vee Max
CEil! = RP# = Vee ±0.2V
A28F200BX:
BYTE # = Vee ± 0.2V or GND

intel®

A28F200BX-T IB

DC CHARACTERISTICS
Symbol

(Continued)

Parameter

Icco

Vcc Deep Power-Down Current

ICCR

Vcc Read Current for
A28F200BX Byte-Wide and
Word-Wide Mode

Notes Min Typ

Unit

Test Condition

p.A RP# = GND ±0.2V

1,5,
6

mA Vcc = Vcc Max, CE# = GND
f = 10 MHz, lOUT = 0 mA
CMOS Inputs

mA Vcc = Vcc Max, CE# = VIL
f= 10 MHz, lOUT = OmA
TTL Inputs

mA Word Write in Progress

mA Block Erase in Progress

mA Block Erase Suspended,
CE# = VIH

Vcc Write Current

1,4

ICCE

Vcc Block Erase Current

1,4

ICCES

V cc Erase Suspend Current

1,2

ICCW

Max

Ipps

Vpp Standby Current

±0.15

Ippo

Vpp Deep Power-Down Current

5.0

p.A Vpp:::: Vcc
p.A RP# = GND ±0.2V

IpPR

Vpp Read Current

200

p.A Vpp> Vcc

Ippw

Vpp Word Write Current

mA Vpp = VPPH
Word Write in Progress

Ippw

Vpp Byte Write Current.

mA Vpp = VPPH
Byte Write in Progress

IpPE

Vpp Block Erase Current

mA Vpp = VPPH
Block Erase. in Progress

IpPES

Vpp Erase. Suspend Current

200

p.A Vpp = VpPH
Block Erase Suspended

IRP#

RP# Current

1,4

500

p.A RP# = VHH

1,4

500

p.A A9 = VIO

110

A9 Intelligent Identifier Current

VIO

A9 Intelligent Identifier Voltage

11.5

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

VPPL

Vpp during Normal Operations

0.0

6.5

VPPH

Vpp during Erase/Write Operations

11.4 12.0

12.6

VLKO

Vcc Erase/Write Lock Voltage

2.0

VHH

RP# Unlock Voltage

11.5

13.0

0.8

Vcc

+ 0.5

0.45
2.4

V
V VCC = Vcc Min
IOL = 5.8 mA
V Vcc = VcC Min
IOH = -2.5mA

V
13.0

V Boot Block Write/Erase

8-57

A28F200BX·T IB

CAPACITANCE(4) TA = 25°C, f = 1 MHz
Symbol

Parameter

Typ

Max

Unit

Condition

CIN

Input Capacitance

VIN = OV

COUT

Output Capacitance

VOUT = OV

NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 5.0V, VPP = 12.0V, T = 25'C. These currents
are valid for all product versions (packages and speeds).
2. leCES is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum
of leeES and ICCR.
3. Block Erases and Word/Byte Writes are inhibited when VPP = VPPL and not guaranteed in the range between VPPH and
VPPL·
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces ICCR to less than 1 mA typical in static operation.
6. CMds Inputs are either Vce ±0.2V or GND ±0.2V. TIL Inputs are either VIL or VIH.
7. VPP = 12.0V ±5% for applications requiring 1,000 block erase cycles.

STANDARD TEST CONFIGURATION
STANDARD AC INPUT/OUTPUT
REFERENCE WAVEFORM

>
<
---ir----'

STANDARD AC TESTING
LOAD CIRCUIT

-r

1.3V

2.4 --~ --2o~---1~--"" 1'~2.0~--INPUT

•

0.45 _ _ _" ~,;;,;O';;;.8

TEST POINTS

OUTPUT

~O';;;.8_ __

iI'

lN914

290500-12

AC, test inputs are driven at VOH (2.4 VnLl for a Logic "1" and VOL
(0.45 VnLl for a logic "0". Input timing begins at VIH (2.0 VnLl and VIL
(0.8 VnLl. Output timing ends at VIH and VIL. Input rise and fall times (10%
to 90%) < 10 ns.

1\
DEVICE
UND~R

TEST

fct

OUT

290500-13

CL = 100 pF
CL Includes Jig Capacitance
RL = 3.3 K!l

8-58

A28F200BX-T IB

AC CHARACTERISTICS-Read Only Operations(1):
A28F200BX-90(4)

Versions
Symbol

Parameter

tAVAV

tRC

Read Cycle Time

tAVQV

tACC

Address to
Output Delay

tELQV

teE

CE # to Output Delay

tpHQV

tPWH

RP# High to
Output Delay

Notes

Min

Max

Unit
ns

300

tGLQV

tOE

OE # to Output Delay

tELQX

tLZ

CE # to Output Low Z

tEHQZ

tHZ

CE # High to Output
HighZ

tGLQX

tOLZ

OE # to Output Low Z

tGHQZ

tDF

OE # High to Output
HighZ

tOH

Output Hold from
Addresses,
CE # or OE # Change,
Whichever is First

tELFL
tELFH

CE# to BYTE #
Switching
Low or High

tFHQV

BYTE # Switching
High to
Valid Output Delay

3,5

tFLQZ

BYTE# Switching
Low to
Output High Z

35
0

ns
ns

NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE# may be delayed up to tCE-toE after the falling edge of CE# without impact on tCE.
3. Sampled, not 100% tested.
4. See Standard Test C o n f i g u r a t i o n . ,
5. tFLOV, BYTE# switching low to valid output delay, will be equal to tAVOV, measured from the time OQs/A-1 becomes
valid.

8-59

V
IH

~vee
POWER-UP
STANDBY

ADDRESSES (A)

VIL _

DEVICE AND
ADDRESS SELECTION

OUTPUTS ENABLED

DATA VALID

ADDRESSES STABLE

-t
......

---

~
VIH
CE# (E)

V1l _

~
c
;;

...?

VIH
OE#

(G)

V1l _

:IE
I»

-...
-...

---

VIH

3(/I

WE#

(\1')

~
(§)

IiiiiI

=
?g
'iii]

CD
I»

VIH
DATA

"'3"V

trLQX

HIGH Z

(0/0)

VIL

~+r-----------

III .
- .........

VALID OUTPUT

~\ \1\

HIGH Z

tAVQV

:::J

(/I

S.OV
Vee

VIH

"'~·I

::J

C:::I
RP# (p) VIL

290500-14

€:
@

_.
~
l§

::g
©

Iiiiil

=
::g

ADDRESSES V;:)

......

cS"

."" ••

'"
GIl

.",

HIGH Z

0
0

INPUT

til

290500-15

><
I

-f
til

......

A28F200BX-T IB

AC CHARACTERISTICS

For WE#-Controlled Write Operations(1):

Verslons(4)

A28F200BX-90(9)
Unit

Symbol

Parameter

Notes

Min

Max

210

100

tAVAV

twc

Write Cycle Time

tPHWl

tps

RP# High Recovery to
WE # GOing Low

tElWl

tcs

CE # Setup to WE # Going Low

tPHHWH

tpHS

RP# VHH Setup to WE# Going High

6,8

tVPWH

tvps

Vpp Setup to WE# Going High

5,8

100

tAVWH

tAS

Address Setup to WE # Going High

tOVWH

tos

Data Setup to WE # Going High

tWlWH

twp

WE # Pulse Width

tWHOX

tOH

Data Hold from WE # High

tWHAX

tAH

Address Hold from WE # High

·tWHEH

tCH

CE# Hold from WE# High

tWPH

WE # PulseWidth High

f.ts

tWHWl
tWHOV1

Duration of Word/Byte .
Write Operation

tWHOV2

Duration of Erase Operation (Boot)

tWHOV3

Duration of Erase
Operation (Parameter)

2,5
2,5,6

0.4

2,5

0.4

tWHOV4

Duration of Erase Operation (Main)

2,5,6

0.7

tOWl

tVPH

Vpp Hold from Valid SRD

5,8

taVPH

tpHH

RP# VHH Hold from Valid SRD

6,8

Boot-Block Relock Delay

7,8

tpHBR

100

NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify and margining operations.
3. Refer to command definition table for valid AIN. .
4. Refer to command definition table for valid DIN.
5. Program/Erase durations are measured to valid SRO data (successful operation, SR.7= 1).
6. For BOot Block Program/Erase. RP# should be held at VHH until operation completes successfully.
7. Time tpHBR is required for successful relocking of the Boot Block.
8. Sampled but not 100% tested.
9. See Standard Test Configuration.

8-62

A28F200BX-T IB

BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE: Vpp
Parameter

Notes

12.0V ± 5%

A28F200BX-90
Min

Typ(1)

Max

Unit

Boot/Parameter
Block Erase Time

1.5

10.5

Main Block
Erase Time

3.0

Main Block Byte
Program Time

1.4

5.0

Main Block Word
Program Time

0.7

2.5

NOTES:

1. 25'C, 12.0V Vpp.
2. Excludes System-Level Overhead.

8·63

en
~

Vee POWER-UP
WRITE PROGRAM OR
ERASE SETUP COMMAND
&: STANDBY

WRITE
VALID ADDRESS &: DATA (PROGRAM)
OR ERASE CONFIRM COMMAND

AUTOMATED PROGRAM
OR ERASE DELAY

READ STATUS
REGISTER DATA

,.~

WRITE READ ARRAY
COMMAND

I\)

o
o

VIH

il...

ADDRESSES (A)

AIN

"'N

)(

.!.t
......

VIL

~I
DI

VIH
CE# (E)
VIL

<
CD

[I
il
il...0

' VIH
OE# (G)

VIL

I-

tWHOV1,2,3,4

-I

VIH
WE# (w)

V1L

...m
DI

1/1

l§J

Iiiiil

:::J
1/1

= :::J0
~ ...
2-

'iii]

2.PJ

~
~

"=lI

=
@
~

VIL

O·

~ i
m

VIH
DATA (D/O)

VHH

RP# (p)

VIL

iii

Il.

...;::;:=E
CD

.!!!,.

6.5V
VIH

t VPWH
VpPH
V ' (V) VpPL
PP
VIH
VIL

290500-16

~
@)

A28F200BX-T IB

I
I,

AC CHARACTERISTICS FOR CE#-CONTROLLED WRITE OPERATIONS(1,9)
A28F200BX-90(10)

Versions
Symbol

Parameter

Notes

Min

Max

Unit

I
11

tAVAV

twc

Write Cycle Time

tpHEL

tps

RP# High Recovery
to CE # GOing Low

210

tWLEL

tws

WE # Setup to CE #
Going Low

tpHHEH

tPHS

RP# VHH Setup to
CE # Going High

6,8

100

tVPEH

tvps

Vpp Setup to CE #
Going High

5,8

100

tAVEH

tAS

Address Setup to
CE # Going High

tovEH

tos

Data Setup to CE #
Going High

tELEH

tcp

CE # Pulse Width

tEHOX

tOH

Data Hold from
CE# High

tEHAX

tAH

Address Hold
from CE # High

tEHWH

tWH

WE # Hold from CE # High

tCPH

CE# Pulse
Width High

2,5

JLs

2,5,6

0.4

tEHEL
tEHOVl

Duration of Word/Byte
Programming
Operation

tEHOV2

Duration of Erase
Operation (Boot)

tEHOV3

Duration of Erase
Operation (Parameter)

2,5

0.4

tEHOV4

Duration of Erase
Operation (Main)

2,5

0.7

taWL

tVPH

Vpp Hold from
ValidSRD

5,8

tOVPH

tpHH

RP# VHH Hold
from Valid SRD

6,8

tpHBR

Boot-Block Relock Delay

100

NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE# and WE# in systems where
CE # defines the write pulse-width (within a longer WE # timing waveform), all set-up, hold and inactive WE # time should be
measured relative to the CE # waveform.
2, 3, 4, 5, 6, 7, 8~ Refer to AC Characteristics for WE # -Controlled Write Operations.
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
10. See Standard Test Configuration.

8-65

c:o

vee

POWER-UP
WRITE PROGRAM OR
& STANDBY ERASE SETUP COMMAND

...

C
It

....

WRITE
VALID ADDRESS & DATA (PROGRAM)
OR ERASE CONFIRM COMMAND

AUTOMATED PROGRAM
OR ERASE DELAY

READ STATUS
REGISTER DATA

;::

WRITE READ ARRAY
. COMMAND

VIH
ADDRESSES (A)

AtN

)(

AtN

!t
m

Vil

......

VIH

WE# (W)
Vil

(')

VIH

·OE# (G)
Vil

--~- 'EHQV1,2,3,.

1/1

-I

VIH

CE# (E)
Vil

DI
:::I

~
@l

II
"

VIH
DATA (0/0)
Vil

...DI

~ o:::I·
~
.

VHH

1/1

@
IiiiiI '0
rn

=
~
'liiI

'Ij,

VIH
RP# (p)

(')

Vil

0
:::I

=
©
~

3:
It

.!.

. ---------------

If:~H!.."1------

6.SV

t VPEH
VpPH

(v) VPPl
VIH

":3

Vil

290500-17

ci!
@)

A28F200BX-T IB

ORDERING INFORMATION

I I I 12181 121 I 181 1-191 I
A

I .

P~CK~GE
PA

~ ACCESS SPEED (ns)

= 44 LEAD PSOP

90 ns

290500-18

Valid Combinations:

APA28F200BX-T90

APA28F200BX-B90

ADDITIONAL INFORMATION

Order Number

A28F400BX Datasheet

290501

28F400BX/28F004BX Datasheet

290451

A28F200BX-l/28F002BX-L Datasheet

290449

28F400BX-l/28F004BX-L Datasheet

290450

AP-363 "Extended Flash BIOS Design for Portable Computers"

292098

ER-28 "ETOXTM III Flash Memory Technology"

204012

ER-29 "The Intel2/4-Mbit Boot Block Flash Memory Family"

294013

8-67

A28F010
1024K (128K x8) CMOS FLASH MEMORY
(Automotive)

Extended Automotive· Temperature
• Range:
- 40°C to + 125°C
Flash Memory Electrical Chip-Erase
• - 1 Second Typical Chip-Erase
Programming Algorithm
• -Quick-Pulse
10 ,..,s Typical Byte-Program

Program/Erase Stop Timer
• Integrated Register
Architecture for

•
•

:..... 2 Second Chip-Program
1,000 Erase/Program Cycles Minimum
• over
Automotive Temperature Range
12.0V ± 5% Vpp
• High-Performance
• -150 ns MaximumRead
Access Time
CMOS Low Power Consumption
• - 30 mA Maximum Active Current
-100,..,A Maximum Standby Current

•
•

Comm~nd

Microprocessor/Microcontroller
Compatible Write Interface
Noise Immunity Features
- ± 10% Vee Tolerance
- Maximum Latch-Up Immunity
through EPI Processing
ETOXTM III Flash Nonvolatile Memory
Technology
- EPROM-Compatible Process Base
- High-Volume Manufacturing
Experience
JEDEC-Standard Pinouts
....,. 32-Pin Plastic DIP
..... 32-Lead PLCC
(Sire Packaging Spec., Order # 231369)

Intel's 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F010 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: ina test socket; in a PROM-programmer socket; onboard during subassembly test; in-system during final test; and in-system after-sale. The 28F010 increases
memory flexibility, while contributing to time- and cost-savings.
The 28F010 is a 1024-kilobit nonvolatile memory organized as 131,072 bytes of 8 bits. Intel's 28F010 is
offered in 32-pin Plastic DIP or 32-lead PLCC packages. Pin assignments conform to JEDEC .standards.
Extended erase and program cycling capability is designed into Intel's ETOXTM III (EPROM Tunnel Oxide)
process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field
combine to extend reliable cycling beyond that of traditional EEPROMs .. With the 12.0V Vpp supply, the
28F010 performs a minimum of 1,000 erase and program cycles well within the time limits of the Quick-Pulse
Programming and Quick-Erase algorithms.
Intel's 28F01 0 employs advanced CMOS circuitry for systems requiring high-performance access speeds, low
power consumption, and immunity to noise. Its 150 nanosecond access time provides no-WAlT-state performance for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 p,A translates into power savings when the device is deselected. Finally, the highest degree of latch-up protection is
achieved through Intel's unique EPI processing. Prevention of latch-up .is provided for stresses up to 100 mA
on address and data pins, from -1V to Vee + 1V.
With Intel's ETOX III process base, the 28F010 leverages years of EPROM experience to yield the highest
levels of quality, reliability, and cost-effectiveness.
In order to meet the rigorous environmental requirements of automotive applications, Intel offers the 28F01 0 in
extended automotive temperature range. Read and write characteristics are guaranteed over the range of
-40·C to + 125°C ambient.

8-68

September 1993
Order f!lumber: 290266-003

A28F010

DOo-D~

c--+
s--+

fl
WE#

J INPUT/OUTPUT

JERASE VOLTAGj
SWITCH

----+
~

BUFfERS

. ,.

TO ARRAY
SOURCE

r--

STATE
CONTROL·

COMMAND
REGISTER

~ ~ .~""

SWITCH

CHIP ENABLE
OUTPUT ENABLE
LOGIC

CE#

7
STB

DATA
LATCH

OE#

Y-DECODER
STB

'"<>

11.

VI
VI

'"...
Q
Q

Y-GATING

I--t

...

f----t

X-DECODER

•
•
•
•
~

1;048,576 BIT
CELL MATRIX

290266-1

Figure 1. 28F010 Block Diagram

AUTOMOTIVE TEMPERATURE FLASH
MEMORIES"",
The Intel Automotive Flash memories have received
additional processing to enhance product characteristics. The automotive temperature range is - 40·C
to + 125°C during the read/write/erase/program
operations.

Packaglng,Optlons

Speed
Versions

Plastic DIP

150

PLCC

8-69

A28F~10

- 28F010
vpp
~6

vee
WE#

~U")COQ.u~

......

As.

'A4

A4·

OE#

CE#

000

.,e-~

a
28FO 1Ii
32 - PIN PlCC
0.450" x 0.550"
TOP VIEW

~4
~3
.Ag

Ag
~1
OE#

~o
CE#
D~

DOs

0°2

D0.

"55

003

gg>'fJ.gg'l'l
290266-3

'290266-2

Figure 2. 28F010 'Pin Configurations
Table 1. Pin Description
Symbol

Type

Name and FunCtion

Ao-A16

INPUT

ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.
'.
.

000-007 .

INPUT/OUTPUT

DATA INPUT/OUTPUT: Inputs data during memory write cycles;
outputs data during memory read cycles. The data pins are active high
and float to tri-state OFF when the chip is deselected or the outputs
are disabled. Data is internl;llly latched during a write.;cycle..

eE#

INPUT

CHIP ENABLE: Activates the device'slcontrollogic, input buffers,
decoders and sense amplifiers. eE# is active low; eE# high
deselects the memory device and reduces power consumption to
standby levels.

OE#

I"!PUT

OUTPUT ENABLE: Gates the devices output through the data buffers
during a read cycle. OE# is-active lo~.

WE#

INPUT

WRITE ENABLE: Controls writes to the cdntrol register and the array.
Write enable is active low. Addresses are latched on the falling edge
and data is latched on the rising edge of the WE # pulse.
Note: With Vpp ::;; 6.5V, memory contents cannot be altered.

Vpp

ERASE/PROGRAM POWER SUPPLY for writing the command
register, erasing the entire array, or programming bytes in the array.

Vee

DEVICE POWER SUPPLY (5V±10%)

"ss

GROUND

NO INTERNAL CONNECTION to device. Pin may bedrilien or left
floa:ting.

8-70

""'1·

A28F010

APPLICATIONS
The 28F010 flash-memory adds electrical chip-erasure and reprogrammability to EPROM non-volatility
and ease of use. The 28F010 is ideal for storing
code or data-tables in applications where periodic
updates are required. The 28F010 also serves as a
dense, nonvolatile data acquisition and storage medium.
The need for code updates pervades all phases of a
system's life-from prototyping to system manufacture to after-sale service. In the factory, during prototyping, revisions to control code necessitate ultraviolet erasure and reprogramming of EPROM-based
prototype codes. The 28FO 10 replaces the 15- to
20-minute ultraviolet erasure with one-second electrical erasure. Electrical Chip-erasure and reprogramming occur in the same workstation or PROMprogrammer socket.
Diagnostics, performed at subassembly or final assembly stages, often require the socketing of
EPROMs. Socketed test codes are ultimately replaced with EPROMs containing the final program.
With electrical Chip-erasure and reprogramming, the
28F010 is soldered to the circuit board. Test codes
are programmed into the 28F01 0 as it resides on the
circuit board. Ultimately, the final code can be downloaded to the device. The 28F010's in-circuit alterability eliminates unnecessary handling and less-reliable socketed connections, while adding greater
test flexibility.
Material and labor costs associated with code
changes increase at higher levels of system integration-the most costly being code updates after sale.
Code "bugs", or the desire to augment system functionality, prompt after-sale code updates. Field revisions to EPROM-based code require the removal of
EPROM components or entire boards.

Designing with the in-circuit alterable 28F010 eliminates socketed memories, reduces overall material
costs, and drastically cuts the labor costs associated with code updates. With the 28F010, code updates are ,implemented locally via an edge-connector, or remotely over a serial communication link.
The 28F010's electrical chip-erasure, byte reprogrammability, and complete nonvolatility fit well with
data accumulation needs. Electrical Chip-erasure
gives the designer a "blank-slate" in which to log
data. Data can be periodically off-loaded for analysis-erasing the slate and repeating the cycle. Or,
multiple devices can maintain a "rolling window" of
accumulated data.
With high density, nonvolatility, and extended cycling
capability, the 28F010 offers an innovative alternative for mass storage. Integrating main memory and
backup storage functions into directly executable
flash memory boosts system performance, shrinks
system size, and cuts power consumption. Reliability
exceeds that of electromechanical media, with
greater durability in extreme environmental conditions.
A high degree of on-chip feature integration simplifies memory-to-processor interfacing. Figure 3 depicts two 28F010s tied to the 80C186 system bus.
The 28F010's architecture minimizes interface circuitry needed for complete in-circuit updates of
memory contents.
With cost-effective in-system reprogramming and
extended cycling capability, the 28F010 fills the
functionality gap between traditional EPROMs and
EEPROMs.
EPROM-compatible
specifications,
straightforward interfacing, and in-circuit alterability
allows designers to easily augment memory flexibility and satisfy the need for updatable nonvolatile
storage in today's designs.

8-71

I
l~

intel®

A28F010

Vee

BOClB6
SYSTEM BUS

Vee
~ -All

----------l.t Ao-A16
+ - - - - - - - -......

000 -00-;

2BF010
MCSI# AND M C S 2 # - - - - - - - -...... CE#
BHE#

28FOI0

Jo---+I CE#

' ) - - - -..... WE#

WR#

1 - -.... WE#

RP# - - - - - - - _..... OE#

1---+1

OE#
290266-4

Figure 3. 28F010 in a 80C186 System

PRINCIPLES OF OPERATION
Flash·memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F010 introduces a command register to manage
this new functionality. The command register allows
for: 100% TTL-level control inputs; fixed power supplies during erasure and programming; and maximum EPROM compatibility.
In the absence of high voltage on the Vpp pin, the
28F010 is a read-only memory. Manipulation of the
external memory-control pins yields the standard
EPROM read, standby, output disable, and Intelligent Identifier operations.
The same EPROM read, standby, and output disable
operations are available when high voltage is applied to the Vpp pin. In addition, high voltage on Vpp
enables erasure and programming of the device. All
functions asspciated with altering memory contents-Intelligent Identifier, erase, erase verify, program, and program verify-are accessed via the
command register.
Commands are written to the register using standard
microprocessor write timings. Register· contents
serve as input to an internal state-machine which
controls the erase and programming circuitry. Write
cycles also internally latch a~dresses and data

8-72

needed for programming or erase operations. With
the appropriate command written to the register,
standard microprocessor read timings output array
data, access the Intelligent Identifier codes, or output data for erase and program verification.

Integrated Program/Erase Stop Timer
Successive command write cycles define the durations of prowam and erase operations; specifically;
the program or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simplified timing control over these operations; thus eliminating the need for maximum program/erase timing
specifications. Program and erase pulse durations
are minimums only. When the stop timer terminates
a program or erase operation, the device enters an
inactive state and remains inactive until receiving the
appropriate verify or reset command.

Write Protection
The command register is only alterable when Vpp isat high Voltage. Depending upon the application, the
system designer may choose to make the Vpp power supply switchable-available only when memory
updates are desired. When high voltage is removed,

A28F010

Table 2. 28F010 Bus Operations
Pins

Vpp(1)

CE#

OE#

WE#

VIL

VIH

Data Out

DQo-DQ7

Operation

READ·ONLY

READ/WRITE

Read

VPPL

Output Disable

VpPL

VIL

VIH

Tri-State

Standby

VpPL

VIH

Tri-State

Intelligent Identifier (Mfr)(2)

VpPL

VIL

VID(3)

VIL

VIH

Data = 89H

VIL

VIH

Data = B4H

VIL

VIH

Data Out(4)

Intelligent Identifier (Device)(2)

VPPL

VIH

VID(3)

Read

VPPH

Output Disable

VPPH

VIL

VIH

Tri-State

Standby(S)

VpPH

VIH

Tri-State

Write

VPPH

VIL

VIH

VIL

Data In(6)

NOTES:
1. VPPL may be ground, a no-connect with a resistor tied to ground, or s 6.SV. VPPH is the programming voltage specified
for the device. Refer to D.C. Characteristics. When Vpp = VpPL memory' contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
addresses low.
3. VIO is the Intelligent Identifier high voltage. Refer to DC Charactjlristics.
4. Read operations with Vpp = VPPH may access array data or the Intelligent Identifier codes.
S. With Vpp at high voltage, the standby current equals Icc + Ipp (standby).
6. Refer to Table 3 for valid Data-In during a write operation.
7. X can be VIL or VIH.

the contents of the registElr default to the read command, making the 28F010 a read-only memory.
Memory contents cannot be altered.
Or, the system designer may choose to "hardwire"
Vpp, making the high voltage supply constantly
available. In this instance, all operations are performed in conjunction with the command register.
The 28F010 is designed to accommodate either design practice, and to encourage optimization of the
processor-memory interface.
The two-step Program/Erase write sequence to the
Command Register provides additional software
write protection.
BUS OPERATIONS
Read
The 28F01 0 has two control functions, both of which
must be logically active, to obtain data at the outputs. Chip~Enable (CE #) is the power control and
should be used for device selection. Output-Enable
(OE#) is the output control and should be used to
gate data from the output pins, independent of device selection. Figure 6 illustrates read timing waveforms.
When Vpp is low (Vppd, the read only operation is
active. This permits reading the data in the array and
outputting the Intelligent Identifier codes (see Ta-

ble 2). When Vpp is high (VPPH), the default condition of the device is the read only mode. This allows
reading the data in the array. Further functionality is
achieved though the Command Register as shown
in Table 3.
Output Disable
With Output-Enable at a logic-high level (VIH), output
from the device is disabled. Output pins are placed
ina high-impedance state.
Standby
With Chip-Enable at a logic-high level, the standby
operation disables most of the 28F010's circuitry
and substantially reduces device power consumption. The outputs are placed in a high-impedance
state, independent of the Output-Enable signal. If
the 28F010 is deselected during erasure, programming, or program/erase verification, the. device
draws active current until the operation is terminated.
Intelligent Identifier Operation
The Intelligent Identifier operation outputs the manufacturer code (89H) and device code (B4H). Programming equipment automatically matches the
device with its proper erase and programming
algorithms.
8-73

in1:el®

A28F010

With Chip-Enable and Output-Enable at a logic low
level, raising A9 to high voltage VID (see DC Characteristics) activates the operation. Data read from locations OOOOH, and 0001 H represent the manufacturer's code and the device code, respectively.
The manufacturer- and device-codes can also be
re,ad via the command register, for instances where
the 28F010 is erased and reprogrammed in the target system. Following a write of 90H to the command register, a read from address location OOOOH
outputs the manufacturer code (89H). A read from
address 0001 H outputs the device code (B4H).

used to store the command, along with address and
data information needed to execute the command.
The command register is written by bringing WriteEnable to a logic-low level (VILl, while Chip-Enable is
low. Addresse's are latched on the falling edge of
Write-Enable, while data is latched on the rising
edge of the Write-Enable pulse. Standard microprocessor write timings are used.
Refer to A.C. Write Characteristics and the Erase/
Programming Waveforms for specific timing
parameters.

Write

COMMAND DEFINITIONS

Device erasure and programming are accomplished
via the command register, when high voltage is applied to the Vpp pin. The contents of the register
serve, as input to the internal state-machine. The
state-machine outputs dictate the function of the
device.

When low voltage is applied to the Vpp pin, the contents of the command register default to OOH, enabling read-only,operations.

The command register itself does not occupy an addressable memory location. The register is a latch

Placing high voltage on the Vpp pin enables read/
write operations. Device operations are selected, by
writing specific data patterns into the command, register. Table 3 defines these 28F010 register
commands.

Table 3. Command Definitions
Command

Bus
Cycles

Second Bus Cycle

First Bus Cycle

Req'd Operation(1) AdClress(2) Data(3) Operatlon(1) Address(2) Data(3)
Read Memory

Write

OOH

Read Intelligent Identifier Codes(4)

Write

90H

Read

Set-up Erase/Erase(5)

Write

20H

Write

20H

Erase Verify(5)

Write

AOH

Read

EVO

Set-up Program/Program(6)

Write

40H

Write

Program Verify(6)

Write

COH

Read

PVO

Reset(7)

Write

FFH

Write

FFH

NOTES:

1. Bus operations are defined in Table 2.
2. IA "7 Identifier address: OOH for manufacturer code, 01 H for d~vice code.
EA ,= Address of memory location to be read during erase verify.
PA = Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-'Enable pulse.
3. ID = Data read from location IA during device identification (Mlr = 89H, Device = B4H).
EVD = Data read from location EA during erase verify.
PD = Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
PVD = Data read from location PA during program verify. PA is latched on the Program commal)d.
4. Following the Read Intelligent 10 command, two read operations access manufacturer and device codes.
5. Figure 5 illustrates the Quick-Erase Algorithm.
'
6. Figure 4,illustrates the Quick-Pulse Programming Algorithm.
7. The second bus cycle must be followed by the desired command register write.

8-74

A28F010

Read Command
While Vpp is high, for erasure and programming,
memory contents can be accessed via the read
command. The read operation is initiated by writing
OOH into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register contents are altered.
The default contents of the register upon Vpp power-up is OOH. This default value ensures that no spurious alteration of memory contents occurs during
the Vpp power transition. Where the Vpp supply is
hard-wired to the 28F010, the device powers-up and
remains enabled for reads until the command-register contents are changed. Refer to 'the AC. Read
Characteristics and Waveforms for specific timing
parameters.

Intelligent Identifier Command
Flash-memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be accessible while the device resides in the target system. PROM programmers typically access signature
codes by raising AS to a high voltage. However, multiplexing high voltage onto address lines is not a, desired system~design practice.
The 28F01 0 ,contains an' inteligent Identifier operation to supplement traditional PROM-programming
methodology. The operation is initiated by writing
SOH into the command register. Following the command write, a read cycle from address OOOOH retrieves the manufacturer code of 8SH. A read cycle
from address 0001 H returns the device code of
B4H. To terminate the operation, it is necessary to
write another valid command into the register.

high voltage is applied to the Vpp pin. In the absence
of this high voltage, memory contents are protected
against erasure. Refer to AC. Erase Characteristics
and Waveforms for specific timing parameters.

Erase-Verify Command
The erase command erases all bytes of the array in
, parallel. After each erase operation, all bytes must
be verified. The erase verify operation is initiated by
writing AOH into the command register. The address
for the byte to be verified must be supplied as it is
latched on the falling edge of the Write-Enable
pulse. The register write terminates the erase operation with the rising edge of its Write-Enable pulse.
The 28F010 applies an internally-generated margin
voltage to the addressed byte. ReadingFFH from
the addressed byte indicates that all bits in the byte
are erased.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.
In the case where the'data read is not FFH, another
erase operation is performed. (Refer to Set-up
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once all bytes in
the array have been verified, the erase step is complete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g. Program Set-up) to the command
registe~. Figure 5, the Quick-Erase algorithm, illustrates how commands and bus operations are com, binedto pen:orm electrical erasure of the 28F010.
Refer to AC. Erase Characteristics and Waveforms
for specific timing parameters.

Set-up Erase/Erase Commands

Set-up Program/Program Commands

Set-up Erase is a ,command-only operation that
stages the device for electrical erasure of all bytes in
the array. The set-up erase operation is performed
by writing 20H to the command register.

Set-up program is a command-only operation that
stages the device for byte programming. Writing 40H
into the command register performs the set-up
operation.
'

To commence chip-erasure, the erase command
(20H) must again be Written to the register. The
erase operation begins with the rising edge of the
Write-Enable pulse and terminates with the rising
edge of the next Write-Enable pulse (i.e., Erase-Verify Command).
_

Once the program set-up operation is performed,
the next Write-Enable pulse causes a transition to
an active programming operation. Addresses are internally latched on the falling edge of the Write-Enable pulse. Data is internally latched on the rising
edge of the Write-Enable pulse. The rising edge of
Write"Enable ,also begins the programming operation. The programming operation terminates with the
next rising edge of Write-Enable, used to write the
program-verify command. Refer to AC. Program-

This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur When

8-75

A28F010

ming Characteristi.cs and Waveforms for specific
timing parameters.

Program~Verlfy

Command

The 28F01 0 .is programmed on a byte-by-byte basis.
Byte programming may occur sequentially or at random. Following each programming operation; the
byte just programmed must be verified.
'
The program-verify operation is initiated by writi~g
·COH into the· command register. The register write
· terminates the programming operation with the rising edge of .its Write-Enab'e pulse. The program-verify operation stages the device for verification of the
byte last programmed. No new address information
is latched.
.
The 28F010 applies an internally-generated ,margin
voltage to the byte. A' microprocessor read. cycle
outputs the data. A successful comparison between
the progra(Tlmed byte and true data means that the
byte is successfully programmed. Programming then '
proceeds to the next, desired byte location. Figure 4,
the 28FO.10 Quick-Pulse Programming algorithm, illustrates how commands are combined with busop-·
erations to perform byte programming. Refer to A.C.
Programming Characteristics and Waveforms for
specific timing parameters.

Reset Command
A reset command is provided as a means to safely
abort the eraSe- or Program-command sequences.
Following either set~up command (erase or program)
with two consecutive writes of FFH will safely abort
the operation. Memory contents will not be altered.
·A valid command must then be written to placethe
device in the desired state.

EXTENDED ERASE/PROGRAM

CVCLlN~

EEPROM cycling failures have always concerned
users. The high electrical field required by ~hin oxide
EEPROMs for tUnneling can literally tear .apart the
oxide at defect regions. To combat this, some suppliers' have implemented redundancy schemes, reducing cycling failures to insignificantlevels. Howev~
· er, redundancy requires that cell size be double~
, an expensive solution.
Intel has deSigned extentled 'cYCling capability into
its ETOX-II flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell· size or com'pll;!xity. First, an
advanced tunnel oxide increases the cnarge carryc
ing ability ten-fold. Second, .the ox.ide area. per cell
subjected' to the tunneling ~Iectric field is one-tenth
that of commonEEPROMs, minimizing the probabili8-76

ty of oxide defects in the region. Finally, the peak
electric field during erasure is apprOXimately 2 MV /
cm lower than, EEPROM.' The lower electric field
greatly reduces oxide stress and the probability. of
faHur~ncreasing time to wearout by a factor of
100,000,000.
The device is programmed and erased using. Intel's
Quick-Pulse Programming and Quick-Erase algo':
, rithms. Inte.I's algorithmic approach uses a series of
operations (pulses), along with byte verification, to
completely and reliably erase and program the device..
.

QUICK-PULSE PROGRAMMING ALGORITHM.
The Quick-Pulse Programming algorithm uses programming operations·of 10 p.s duration. Each operation is followed by a byte verification to c;ietermine'
when the addressed byte has been successfully programmed. The algorithm allows for up to '25 programming operations per byte, although most bytes
verify on the first or second operation, The entire
sequence of programming and byte verification is
performed with Vpp at high voltage. Figure 4' illustrates the Quick-Pulse Programming algorithm.
QUICK-ERASE ALGORITHM
Intel's Quick-Erase ,algorithm yields fast and reliable
electrical erasure of memory contents. The algo'rithm employs a closed~loop flow, .similar to tlJe
Quick-Pulse Programming algorithm, to simultaneously remove charge from all bits in the array.
Erasure begins with a read of memory contents. The
28F010 is erased when shipped from the factory.
Reading FF!-I' data 'from the device would immediately be followed by device programming.
For devices being .erased· and reprogrammed, uni- .
form and reliable erasure is ensured by first pro. gramming all.bits in the device to their charged state
(Data = OOH). This is accomplished, using the
Quick-Pulse Vcc

±1.o p.A Vpp
,

8-8.0

Vec

A28F010

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE (Continued)
Symbol

Parameter

Limits

Notes

Min Typical

Unit

Test Conditions

Max

IpP2

VPP Programming Current

1,2

8.0

rnA Vpp = VPPH
Programming in Progress

IpP3

VPP Erase Current

1,2

4.0

rnA VPP = VPPH
Erasure in Progress

IpP4

VPP Program Verify Current

1,2

2.0

5.0

rnA VPP = VPPH
Program Verify in Progress

IpP5

VPP Erase Verify Current

1,2

2.0

5.0

rnA VPP = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOHl

Output High Voltage

VIO

Ag Intelligent Identifer Voltage

110

Vee ID Current

0.8

+ 0.5

Vee

0.45
2.4
11.50
1

VPP ID CURHENT

13.00

IOL = 2.1 rnA
Vee = Vee Min

IOH = -2.5 rnA
Vee = Vet Min

V Ag

rnA

500

p.A

VPP during Read-Only Operations

0.00

6.5

VPPH

VPP during Read/Write Operations

11.40

12.60

VLKO

Vee Erase/Write Lock Voltage

VPPL

2.5

VID

VIO

NOTE: Erase/Program are
Inhibited when VPP = VPPL

DC CHARACTERISTIC5-CMOS COMPATIBLE
Symbol

Parameter

Limits

Notes
Min

Typical

Unit

Test Conditions

Max

III

Input Leakage Current

± 1.0

p.A

Vee = Vee Max
VIN = Vee or Vss

ILO

Output Leakage Current

±10

p.A

Vee = Vee Max
VOUT = Vee or Vss

lees

Vee Standby Current

100

p.A

Vee = Vee Max
CE# = Vee ±0.2V

leel

Vee Active Read Current

rnA

Vee = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 rnA

lee2

Vee Programming ,Current

1,2

1.0

rnA

Programming in Progress

1,2

5.0

Erasure in Progress

lee3

Vee Erase Current

Ipps

VPP Leakage Current

IpPl

VPP Read Current or
Standby Current

rnA

±10

p.A

VPP::;; Vee

200

p.A

Vpp> Vee

±10

VPP::;; Vee

8-81

intel®

A28F010

DC CHARACTERISTICS-CMOS COMPATIBLE (Continoed)
"

Symbol

Parameter

Limits

Notes
Min

Typical

Max

8.0

Unit

Test Conditions

rnA

Vpp = VPPH
Programming in Progress

Vpp
Programming
Current

1,2

IpP3

Vpp Erase
Current

1,2

4.0

rnA

Vpp = VPPH
Erasure in Progress

IpP4

Vpp Program
Verify Current

1,2

2.0

5.0

rnA

Vpp = VPPH Program
Verify in Progress

IpP5

VppEras~

1,2

5.0

rnA

Vpp = VpPH
Erase Verify in Progress

0.8

IpP2

Verify

Current
VIL

Input Low
Voltage

-0.5

VIH

Input High
Voltage

0.7 Vee

VOL

Output Low
Voltage

VOH1

Output High
Voltage

Vee

+ 0.5

0.45

V
V

0.85 Vee

VID

Aglntelligent
Identifier Voltage

lID

Vee 10 Current

110

VpplO Current

VPPL

Vpp during ReadOnly Operations

0.00

VPPH

Vpp during
Read/Write
Operations

11.40

VLKO

Vee Erase/Write
Lock Voltage

IOH = - 2.5 rnA,
Vee ~' Vee Min
IOH = -100/LA,
Vee = Vee Min

Vee - 0.4

VOH2

IOL = 2.1mA
Vee = Vee Min

11.50

13.00

rnA

Ag = 10

500

/LA

Ag = 10

6.5

NOTE: Erase/Programs

are Inhibited when
Vpp = VPPL
12:60

2.5

CAPACITANCE(3) T A = 25°C, f = 1.0 MHz
Symbol

Limits

Parameter
Min

CIN
COUT

. Address/Control Capacitance
Output Capacitance

Unit

Conditions

Max

VIN = OV

VOUT = OV

NOTJOS;
,1. All currents are inRMS unless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, T= 25°e.
2. Not 100% tested: characterization data available.
3, Sampled, not 100% tested.
4. "Typicals" are not guaranteed, but are based on a limited n,umber of samples from production lots.

8-82

A28F010
AC TESTING INPUT/OUTPUT WAVEFORM

AC TESTING LOAD CIRCUIT

2.:~

2.4V

INPUT
O.45V

~~IN914
2.0V:>

OUTPUT

O.BV

DEVICE
UNDER
TEST

TEST POINTS

11--+-0 OUT

290266-7
AC Testing: Inputs are driven at 2.4V for a logic "I" and O.4SV for
a logic "0". Testing measurements are made at 2.0V for a logic
"I" and 0.8V for a logic "0". Rise/Fall time ,;; IOns.

I·.,.~·

3.3K

CL =100pr

290266-8
CL = 100 pF
CL includes Jig Capacitance

AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ................ 0.45V and 2.4V
Input Timing Reference Level ....... 0.8V and 2.0V
Output Timing Reference Level ...... 0.8V and 2.0V

AC CHARACTERISTIC5-Read-Only Operations(2)
Versions
Symbol

Notes
Characteristic

28F010-150
Min

Unit

Max
. ns

tAvAv/tRC

Read Cycle Time

tELQV/tCE

Chip Enable Access Time

150

tAVQV/tACC

Address Access Time

150

tGLQV/tOE

Output Enable
Access Time

tELQXltLZ

Chip Enable to
Output in Low Z

tEHQZ

Chip Disable to
Output in High Z

tGLQX/tOLZ

Output Enable to
Output in Low Z

tGHQZ/tOF

Output Disable to
Output in High Z

tOH

Output Hold from Address,
CE # , or OE # Change

tWHGL

Write Recovery Time
before Read

1,3

150

ns
ns

0
35

JA-s

NOTES:
1. Whichever occurs first.
2. Rise/Fall Time';: 10 ns.
3. Not 100% tested: characterization data available.
4. Guaranteed by design.

8-83

(J)

Co
.j>.

....~

STANDBY

Vce POWER-UP

DEVICE AND
ADDRESS SELECTION

OUTPUTS ENABLED

DATA VALID

STANDBY

;

ADDRESSES

ADDRESSES STABLE

I-n
CO
c

Vee POWER-DOWN

----

---

tAvAv('Re)

CE# (E#)

OE# (G#)

(II

l:J

---'

t WHGL

·1

---

;

WE# (w#)

o
"0

toH

;

::!:

o:::I

DATA (DO)

l.: " , , , b

HIGH Z

d{ < \ J

OUTPUT VALID

(II

I'»)}!>

---

q<{''l

~~~~~--------~~
I-

Vee / ' S.OV

tAVQv(tAee)

•I

''''''_.

-:::J-

<£
@

A28F010

AC CHARACTERISTICS-Write/Erase/Program Operations(1, 3)
Versions

Notes

Symbol

Characteristic

tAYAy/tWC

Write Cycle Time

28F010-150
Min

Max

Unit

150

Data Set-up Time

tWHDX/tDH

Data Hold Time

tWHGL

Write Recovery Time before Read

IJ-s

tGHWL

Read Recovery Time before Write

IJ-s

tELWL/tCS

Chip Enable
Set-Up Time before Write

tWHEH/tCH

Chip Enable Hold Time

tWLWH/tWP

Write Pulse Width(2)

tELEH

Alternative Write(2)
Pulse Width

tWHWL/tWPH

Write Pulse Width High

tWHWH1

Duration of Programming Operation

IJ-s

tWHWH2

Duration of Erase Operation

9.5

tYPEL

Vpp Set-Up
Time to Chip Enable Low

1.0

tAYWL/tAS

Address Set-Up Time

tWLAX/tAH

Address Hold Time

tDYWH/tDS

NOTES;

1. Read timing characteristics during read/write operations are the same as during read-only operations, Refer to AC Characteristics for Read-Only Operations.
2. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up, hold, and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.
3. Rise/Fall time:;:; 10 ns.
4. The internal stop timer terminates the programming/erase operations, thereby eliminating the need for a maximum specification.

ERASE AND PROGRAMMING PERFORMANCE
Parameter

Limits

Notes
Min

Chip Erase Time
Chip Program Time
Erase/Program Cycles

Unit

Comments

Typ

Max

1,3,4,6

Sec

Excludes OOH Programming
Prior to Erasure

1,2,4

12.5

Sec

Excludes System-Level Overhead

1,5

1,000

100,000

Cycles

NOTES;

1. "Typicals" are not guaranteed, but based on a limited number of samples taken from production lots. Data taken at
T = 25'C, Ypp = 12.0Y, Yee = 5.0Y.
2. Minimum byte programming time excluding system overhead is 16 ,...sec (10 ,...sec program + 6 ,...sec write recovery),
while maximum is 400 ,...sec/byte (16 ,...sec x 25 loops allowed by algorithm). Max chip programming time is specified lower
than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case
byte.
3. Excludes OOH programming prior to erasure.
4. Excludes system-level overhead.
5. Refer to RR-60 "ETOX Flash Memory Reliability Data Summary" for typical cycling data and failure rate calculations.
6. Maximum erase specification is determined by algorithmic limit and accounts for cumulative effect of erasure at
•
T = - 40'C, 1,000 cycles, Ypp = 11.4Y, Yee = 4.5Y.

8-85

A28F010

99.9

(

70
60
50

11
..' ..

,/",l'

V
1/

7fj

~~.

../. ..-

6!!J

.//

",I

.....

.
1/ ...
/

•0

30
20

.:"

,
,,

0.1
2.5

....

l- V

/
2

3.5 4 4.5 5

.... .. .'
/

V-

)

I
I

,'-

III

100 110 120 130

TEWP (C)

Chip Program Tlmo (Soc)
- - 1 2 V ; 10 kc; 23C
• ••••• ·I1..V; 10 kc: 70C
~ •• 12V; 100 kc; 23C

290266-17

Figure 7. 28F010 Typical Programming Capability

~1kCyclt.

•••• 10k Cycle.
--100« eyel"

290266-18

Figure 8. 28F010 Typical Program Time at 12V

See Note 1, Page 8·85.

8-86

A28F010

99.9

11.i
•. .

3.0

"
i.

II , ,"V
95

3.2

".'
I'~/

2.8

2.6

/ '
lL ,/

70
60
50
40

III

...
...i!
~
g,

,:'

2.2

2.0

1/1
i
l
1/ ,I

I .'/
I '

1.8

r-....

1.4

'I
I.

1.2

1.6

,.
'}i"

0.5

II
0.7

2345678910
CHIP ERASE nME (SEC)

- •••• -

12V: 10 ke :23C
11.4V:l0 ke:OC
12V:l00 ke:23C

1.0

". 1",

, ....

'1'" ,
r--- l'-. ' .. ....
"'r--- 1"'- . ......
"'" .....t-,....a

70 80 90 100 110 120 130 1.0
TEMP (OC)

_1kCycln

-.·.IOk Cyel..
- - 100k Cycles

290266-19

Figure 9. 28F010Typicai Erase Capability
See Note 1, Page 8-85.

o.1

290266-20

Figure 10. 28F010 Typical Erase Time at 12V

8-87

r:p
--I 1~ ~ ,~,>
--.t-

r-tWHDX ('oH)

'oVWH ('os)

tWHDX ('oH)'

-11

'oVWH('oS)

WLWH

,,> "",'' >
WP

~LQX(toLZ)

_r-tWHDX('oH)

HIGH Z

'ELQX(\z)
'ELQv(lcE)
S.OV
Vee
OV

I- t VPEL

VpPH

Vpp

~
~

VpPL

290266-15

(XI

-~.:.;;;:~~

CII

...oo

"'II

A28F010

Ordering Information

L..----ACCESS SPEEI) (ns)
AUTOMOTIVE TEMP ,

150ns

-4O"C to +125"C

Valid COmbinations:
AP28F010-150

290266-16

AN28F010-150

ADDITIONAL INFORMATION

Order Number

ER-20, "ETOXTM II Flash Memory Technology"

294005

ER-2( "The Intel 28F010 Flash Memory"

294008

RR-60,-"ETOXTM Flash Memory Reliab~lity Data Summary"

293002

AP-316, "Using Flash Memory.for In-System Reprogrammable
Nonvolatile Storage"

292046

AP-325, "Guide to Flash Memory Reprogramming"

292059

REVISION HISTORY
Description,

Changed Erase/Program Cycles to 1,000 minimum

8-90

A28F512
512K (64K x 8) CMOS FLASH MEMORY
(Automotive)

•
-40·C
•
•
•
•
• -1201150
•

Extended Automotive Temperature
to + 125°C
Range:

Flash Electrical Chip-Erase
- 1 Second Typical Chip-Erase
Quick-Pulse Programming Algorithm
- 10 IJ-s Typical Byte-Program
- 1 Second Chip-Program
1,000 EraselProgram Cycle Minimum
Over Automotive Temperature Range
12_0V ±5% Vpp

•
•
•
•

High-Performance Read
ns Maximum Access Time

CMOS low Power Consumption
- 30 mA Maximum Active Current
- 100 IJ-A Maximum Standby Current

•

Integrated ProgramlErase Stop Timer
Command Register Architecture for
MicroprocessorlMicrocontrolier
Compatible Write Interface

I;~
!. . ':

Noise Immunity Features
- ± 10% Vee Tolerance
- Maximum latch-Up Immunity
through EPI Processing

I
..

ETOXTM II Flash Nonvolatile Memory
Technology
- EPROM-Compatible Process Base
- High-Volume Manufacturing
Experience
JEDEC-Standard Pinouts
....;. 32-Pin Plastic DIP
- 32-Pin PlCC
(See Packaging Spec., Order # 231369)

Intet's 2SF512 CMOS flash memory offers the most cost-effecttveand ,reliable alternative for read/write
random access nonvolatile memory. The 28F512 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: ina test socket; in a PROM-programmer socket; onboard during subassembly test; in-system during final test; and in-system after-sale. The 28F512 increases
memory flexibility, while contributing to time- and cost-savings.
The 28F512 is a 512-kilobit nonvolatile memory organized as 65,536 bytes of 8 bits. Intel's 28F512 is offered
in 32-pin cerdip or 32-lead PLCC packages. Pin assignmE;!nts conform to JEDEC standards.
Extended erase and program cycling capability is designed into Intel's ETOXTM II (EPROM Tunnel Oxide)
process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field
combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0V Vpp supply, the
28F512 performs a minimum of 1,000 erase and program cycles well within the time limits of the Quick-Pulse
Programming and Quick-Erase algorithms.
Intel's 28F512 employs advanced CMOS circuitry for systems requiring high-performance access speeds, low
power consumption, and immunity to noise. Its 150 nanosecond access time provides no-WAlT-state performance for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 /LA translates into power savings when the device is deselected. Finally, the highest degree of latch-up protection is
achiE;!ved through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA
on address and data pins, from -1V to Vee + 1V.
With Intel's ETOX II process base, the 28F512 leverages years of EPROM experience to yield the highest
levels of quality, reliability, and cost-effectiveness.
In order to meet the rigorous environmental requirements of Automotive applications, Intel offers the 28F512
in extended Automotive temperature range. Read and Write Characteristics are guaranteed over the range of
- 40°C to + 125°C ambient.

September 1993
Order Number: 290265-004

i~.'."'

8-91

!~
'-f

infel®

A28F512

c--+
s--+

1l
WE# ..,..-.-+

r--+

.IERASE VOLTAGj
SWITCH J

STATE
CONTROL

COMMAND
REGISTER

INPUT/OUTPUT
BUFFERS
~

TO ARRAY
SOURCE

I--

PGM VOLTAGE
SWITCH

CHIP ENABLE
OUTPUT ENABLE
LOGIC

CE#

...
STB

OE#

...
:t:

U
....

A,S

j..

Vl
Vl

.....
Q
Q

Y-GATING

r--+

::5

DATA
LATCH

Y-DECODER
STB

X-DECODER

•
•
•
•

524,288 BIT
CELL MATRIX

I+-

r--+
290265-1

Figure 1. 28F512 Block Diagram

AUTOMOTIVE TEMPERATURE FLASI1
MEMORIES
The Intel Automotive Flash Memories have received
additional processing to enhance product characteristics. The automotive temperature range is - 40·C
to + 125·C during the read/write/erase/program
operations.

8-92

Speed
Versions

Packaging Options

Plastic DIP

PLCC

-120

-150

intel®

A28F512

28F512
Vpp

Vee

« «"'

WE#

Cl.

<.l

U
U

~ >

"w
~

<.l

A15

A12

A14

A13

All

OE#

A10

CE#

D07

DOc

D06

DOl

DOs

DOz

D0 4

Vss

D0 3

A14
A13

:;1

28F512
32 - PIN PLCC
0.450" x 0.550"
TOP VIEW

I ~,

Ag
All

l~\

CE#
D~

0
0

VJ
VJ

0
0

... 0"'
0
"' o.
0

c'f
0
290265-3

290265-2

Figure 2. 28F512 Pin Configurations
Table 1. Pin Description
Symbol

Type

Name and Function

Ao-A15

INPUT

ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.

DOo-DO?

INPUT /OUTPUT

CE#

INPUT

CHIP ENABLE: Activates the device's control logic, input buffers,
decoders and sense amplifiers. CE # is active low; CE # high
deselects the memory device and reduces power ~onsumption to
standby levels.

OE#

INPUT

OUTPUT ENABLE: Gates the devices output through the data buffers
during a read cycle. OE# is active low.

WE#

INPUT

WRITE ENABLE: Controls writes to the control register and the array.
Write enable is active low. Addresses are latched on the falling edge
and data is latched on the rising edge of the WE # pulse.
Note: With Vpp S 6.5V, memory contents cannot be altered.

Vpp

ERASE/PROGRAM POWER SUPPLY for writing the command
register, erasing the entire array, or programming bytes in the array.

Vee

DEVICE POWER SUPPLY (5V ± 10%)

Vss

GROUND

NO INTERNAL CONNECTION to device; Pin may be driven or left
floating.

8-93

A28F512

APPLICATIONS
The 28F512 flash-memory adds electrical chip-erasure and reprogrammability to EPROM non-volatility
and ease of use. The 28F512 is ideal for storing
code or data-tables in applications where periodic
updates are required. The 28F512 also serves as a
dense, nonvolatile data acquisition and storage medium.
The need for code updates pervades alf phases of a
system's life-from prototyping to system manufacture to after-sale service. In the factory, during prototyping, reviSions to control code necessitate ultraviolet erasure· and reprogramming of EPROM-based
prototype codes. The 28F512 replaces the 15- to
20-minute ultraviolet erasure with one-second electrical erasure. Electrical chip-erasure and reprogramming occur in the same workstation or PROMprogrammer socket.
Diagnostics, performed at subassembly or final assembly stages, often require the socketing of
EPROMs. Socketed test codes are ultimately replaced with EPROMs containing the final ·program.
With electrical chip-erasure and reprogramming, the
28F512 is soldered to the circuit board. Test codes
are programmed into the 28F512 as it resides on the
circuit board. Ultimately, the final code can be downloaded to the device. The.28F512's in-circuit alterability eliminates unnecessary handling and less-reliable socketed. connections, while adding greater
test flexibility.
Material and labor costs associated with code
changes increase at higher levels of system integ~a
tion-the most costly being code updates after sale.

8-94

Code "bugs", or the desire to augment system functionality, prompt after-sale code updates. Field revisions to EPROM-based code require the removal of
EPROM components or entire boards.
DeSigning with the in-circuit alterable 28F512 eliminates socketed memories, reduces overall material
costs, and drastically cuts the labor costs associated with code updates. With the 28F512, code updates are implemented locally via an edge-connector, or remotely over a serial communication link.
The 28F512's electrical chip-erasure, byte reprogrammability,and complete nonvolatility fit well with
data accumUlation needs. Electrical chip-erasure
gives the deSigner a "blank-slate" in which to log
data. Data can be periodically off-loaded foranalySis-eraSing the slate and repeating the cycle. Or,
multiple devices can maintain,a "rolling window" of
'
accumulated data.
With high density, nonvolatility, and extended cycling
capability, the 28F512 offers an innovative alternative for mass storage.
Integrating main memory and backup storage functions into directly executable flash memory boosts
system performance, shrinks system size, and cuts
power consumption. Reliability exceeds that of electromechanical media, with greater durability in extreme environmental conditions.
A high degree of on-chip feature integration simplifies memory-to-processor interfacing. Figure 3 depicts two 28F512s tied to the 80C186 system bus.
The 28F512's architecture minimizes interface circuitry needed for complete in-circuit updates of
memory contents.

A28F512

Vee

80CI86
SYSTEM BUS

Vee

Ao-A,s

A, -A'6
DOs-D~S

Ao-A,s

IlOo-D~

DOo-D~

r,~
28f512

MCS1#

CE#

i:~
i!

28f512

i~~

CE#

1.\
!i

BHE#

I'
I

WE#

WR#
WE#

Ao
RD#

OE#

290265-4

Figure 3. 28F512In an 80C186 System
With cost-effective in-system reprogramming and
extended cycling capability, the 28F512 fills the
functionality gap between traditional EPROMs and
EEPROMs.
EPROM-compatible
specifications,
straightforward interfacing, and in-circuit alterability
allows designers to easily augment memory flexibility and satisfy the need for updatable nonvolatile
storage in today's designs.

PRINCIPLES OF OPERATION
Flash-memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F512 introduces a command register to manage
this new functionality. The command register allows
for: 100% TIL-level control inputs; fixed power supplies during erasure and programming; and maximum EPROM compatibility.
In the absence of high voltage on the Vpp pin, the
28F512 is a read-only memory. Manipulation of the
external memory-control pins yields the standard
EPROM read, standby, output disable, and Intelligent Identifier operations.
The same EPROM read, standby, and output disable
operations are available when high voltage is applied to the Vpp pin. In addition, high voltage on Vpp
enables erasure and programming of the device. All
functions associated with altering' memory contents-Intelligent Identifier, erase, era~e verify, program, and program verify-are accessed via the
command register.

Commands are written to the register using standard
microprocessor 'write timings. Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for programming or erase operations. With
the appropriate command written to the register,
standard microprocessor read timings output array
data, access the Intelligent Identifier codes, or output data for erase and program verification.

Integrated Program/Erase Stop Timer
Successive command write cycles define the durationsof program and erase operations; specifically,
the program or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simplified timing control over these operations; thus eliminating the need for maximum program/erase timing
specifications. Program and erase pulse durations
are minimums only. When the stop timer terminates
a program or erase operation, the device enters an
inactive. state and remains inactive until receiving the
appropriate verify or reset c()mmand.

Write Protection
The command register is only alterable when Vpp is
at high voltage. Depending upon the application, the
system designer may choose to make the Vpp pow.er supply switchable-available only when memory
updates are desired. When high voltage is removed,
8-95

A28F512

Table 2 28F512 Bus Operations
Pins

Vpp(1)

CE#

OE#

WE#

VPPL

VIL

VIH

Data Out

VIL

VIH

Tri-State
Tri-State

DQo-DQ7

Operation
Read
Output Disable
READ-ONLY

,
READ/WRITE

;

Standby

VPPL

VIH

Intelligent Identifier (Mfr)(2)

VPPL

VIL

VI0(3)

VIL

VIH

Data = 89H

Intelligent Identifier (Device)(2)

VPPL

VIH

VI0(3)

VIL

VIH

Data =B8H

Read

VPPH

VII:'

VIL

VIH

DataOut(4)

Output Disable

VPPH

VIL

VIH

Tri-State

Standby(5)

VPPH

X-

VIH

Tri~State

Write

VPPH

VIL

VIH

VIL

Data In(6)

NOTES:

1. VpPL may be ground, a no-connect with a resistor tied to ground, or ,,; 6.5V. VPPH is the programming voltage specified
for the device. Refer to D.C. Characteristics. When Vpp = VPPL memory contents can be'read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
.
addresses low.
3. VIO is the Intelligent Identifier high voltage. Refer to DC Characteristics.
4. Read operations with Vpp = VPPH may access array data or the Intelligent Identifier codes.
5. With Vpp at high voltage, the standby current equals Icc + Ipp (standby).
6. Refer to Table 3 for valid Data-In during a wriie operation.
7. X can be VIL or VIH.
.

the contents of the register default to the read command, making the .28F512 a read-only memory.
Memory .contents cannot be altered.
Or, the system designer may choose to "hardwire"
Vpp, .making the high voltage supply constantly

available .. In this instance, all operations are performed in conjiJnction with the command register.
The 28F512 is designed to accommodate either design practice, and to encourage optimization 'of the
processor-memory interface.
The two~step programl erase write sequence to the
Command Register provides additional software
write protection.

Output Disable
With Output-Enable at a logic-high level (VIH), output
from the device is disabled. Output pins are placed
in a high-impedance state.
Standby

BUS OPERATIONS
Read

When Vpp is low (Vppu, the read only operation is
active. This permits reading the data in the array and ,.
outputting the Intelligent Identifier codes (see Table
2). When ypp is high (VPPH), the default condition of
the device is the read only mode. This .allows reading the data in the array. Further functionality is
achieved though the Command Register as shown
in Table 3.

The 28F512 has two control functions, both of which
must be logically active, to obtain data at the outputs. Chip-Enable (CE #) is the power control and
should be used for device selection. Output-Enable
(OE #) is the output control and should be used to
gate data from the output pins,independent of de~
vice selection. Figure. 6. illustrates r~ad timing waveforms.
.

With Chip-Enable at a logic-high level, the standby
operation disables most of the 28F512's circuitry
and substantially reduces device power consumption. The outputs are placed in a high-impedance
state, independent of the Output-Enable signal. If
the 28F512 is deselected during erasure, programrT1ing, or program/erase verification, the device
draws aCtive current untiL the operation is terminated.
Intelligent Identifier Operation
The Intelligent Identifier operation outputs th.e manufacturer code (89H) and device code (B8H), Pro-

8-96

A28F512

gramming equipment automatically matches the device with its proper erase and programming algorithms.
With Chip-Enable and Output-Enable at a logic low
level, raising A9 to high voltage VIO (see DC Characteristics) activates the operation. Data read from 10catio[ls OOOOH and 0001 H represent the manufacturer's code and the device code, respectively.
The manufacturer- and device-codes can also be
read via the command register, for instances where
the 28F512 is erased and reprogrammed in the target system. Following a' write of 90H to the command register, a read from address location OOOOH
outputs the manufacturer code (89H). A read from
address 0001 H outputs the device code (B8H).
Write

Device erasure and programming are accomplished
via the command register, when high voltage is applied to the Vpp pin. The contents of the register
serve as input to the internal state-machine. The
state-machine outputs dictate the function of the
device.

The command register itself does not occupy an addressable memory location. The register is a latch
used to store the command, along with address and
data information needed to execute the command.
The command register is written by bringing WriteEnable to a logic-low level (VIL>, while Chip-Enable is
low. Addresses are latched on the falling edge of
Write-Enable, while data is latched on the rising
edge of the Write-Enable pulse. Standard microprocessor write timings are used.
Refer to A.C. Write Characteristics and the Erasel
Programming Waveforms for specific timing
parameters.

I':

I~i~,

I~
1,,1

COMMAND DEFINITIONS

When low voltage is applied to the Vpp pin, the contents of the command register default to OOH, enabling read-only operations.
Placing high voltage on the Vpp pin enables readl
write operations. Device operations are selected by
writing specific data patterns into the command register. Table 3 defines these 28F512 register
commands.

Bus
First Bus Cycle
Second Bus Cycle
Cycles
Req'd Operatlon(1) Address(2) Data(3) Operatlon(1) Address(2) Data(3)

Read Memory

Write

OOH

Read Intelligent Identifier Code(4)

Write

90H

Read

Set-up Erase/Erase(5)

Write

20H

Write

20H

Erase Verify(5)

Write

AOH

Read

EVD

Set-up Program/Program(6)

Write

40H

Write

Program Verify(6) "

Write

COH

Read

PVD

Reset(7)

Write

FFH

Write

FFH

NOTES:
1~ Bus operations are defined in Table 2.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during erase verify.
PA = Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write~Enable pulse.
3. 10 = Data read from location IA during device identification (Mfr = 89H, Device = B8H).
EVO = Data read from location EA during erase verify.
'
PO = Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
PVO = Data read from location PA during program verify. PA is latched on the Program command.
4. Following the Read Intelligent 10 command, two read operations access manufacturer and device codes.
5. Figure 5 illustrates the Quick-Erase algorithm.
6. Figure 4 illustrates the Quick-Pulse Programming algorithm.
7. The second bus cycle must be followed by the desired command register write.

I
i!

Table 3. Command Definitions
Command

i"",,

8-97

intel®

A28F512

Read Command

While Vpp is high, for erasure and programming,
memory contents can be accessed via the read
command. The read operation is initiated qy writing
OOH into the command register. Microprocessor
read cycles' retrieve' array data. The device remains,
enabled for reads until the command register. contents are altered.
/

The default contents of the register upon Vpp power-up is OOH. This default value ensures that no spurious alteration of memory contents occurs during
the Vpp power transition. Where the Vpp supply is
hard-wired to the 28F512, the device powers-up and
remains enabled for reads until the command-register contents are- changed. Refer to the A.C. Read
Characteristics and Waveforms for specific timing
parameters.
Intelligent Identifier Command

Flash-memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be accessible while the device resides itl the target system. PROM programmers typically access signature
codes by raising AS to a high voltage. However, multiplexing high voltage onto address lines is not a desired system-design practice.

high voltage is applied.to the Vpp pin. In the absence
of this,high voltage, memory contents are protected
against erasure. Refer to A.C. Erase Characteristics
and Waveforms for specific timing parameters.
Erase-Verify Command

The erase command erases all bytes of the array in
parallel. After each erase operation, all bytes must
be verified. The erase verify operation is initiated by
writing AOH into the command register. The address
for the byte to' be verified must be supplied as it is
latched on the falling edge of the Write-Enable
pulse. The register write terminates the erase operation with the rising edge of its Write-Enable pulse.
The 28F512 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.

The 28F512 contains an Intelligent Identifier operation to supplement traditional PROM-programming
methodology. "The operation is initiated by writing
SOH into the command register. Following the command write, a read' cycle from address OOOOH retrieves the manufacturer code of 8SH. A read cycle
from address 0001 H returns the device code of
B8H. To terminate the operation, it is necessary to
write another valid command into the register.

In the case where the data read is not FFH, another
erase operation is performed. (Refer to Setcup
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once all bytes in
the array have been verified, the erase step is complete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g. Program Set-up) to the command
register. Figure 5, the Quick-Erase algorithm, illustrates how commands and bus operations are combined to perform electrical erasure of the 28F512.
Refer to A.C. Erase Characteristics and Waveforms
for specific timing parameters.

Set-up Erase/Erase Commands

Set-up Program/Program Commands

Set-up Erase is a command-only operation that
stages the device for electrical erasure of all bytes in
the array. The set-up erase operation is performed
by writing 20H to. the command register.

Set-up program is a command-only operation that
stages the device for byte programming. Writing 40H
into the command register performs the set-up
operation.

To commence chip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
Write-Enable pulse and terminates with the rising
edge of the next Write-Enable pulse (i.e., Erase-Verify Command).

Once the program set-up operation is performed,
the next Write·Enable pulse causes a transition to
an active programming operation. Addresses are internally latched on the falling edge of the Write-Enable pulse. Data is internally latched on the rising
edge of the Write-Enable pulse. The rising edge of
Write-Enable also begins the programming operation. The programming operation terminates with the
next rising edge of Write-Enable, used to write the
program-verify command. Refer to A.C. Program-

This two-step sequence of set-up followed byexecution ensures that memory contents are not accidentally erased. Also,chip-erasure can only occur When

8-S8

A28F512
ming Characteristics and Waveforms for specific
timing parameters.
Program-Verify Command
The 28F512 is programmed on a byte-by-byte basis.
Byte programming may occur sequentially or at random. Following each programming operation, the
byte just programmed must be verified.
The program-verify operation is initiated by writing
COH into the command register. The register write
terminates the programming operation with .the rising 'edge of its Write-Enable pulse. The program-verify operation stages the device for verification of the
byte last programmed. No new address information
is latched.
The 28F512 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 4,
the 28F512 Quick-Pulse Programming algorithm, illustrates how commands are combined with bus operations to perform byte programming. Refer to A.C.
Programming Characteristics and Waveforms for
specific timing parameters.
Reset Command
A reset command is provided as a means to safely
abort the erase- or program-command sequences.
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort
the operation. Memory contents will not be altered.
A valid command must then be written to place the
device in the desired statE!.
EXTENDED ERASE/PROGRAM CYCLING

EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubledan expensive solution.
. Intel has designed extended cycliMg .capability into
its ETOX-II flash memory technology. Resultingimprovements in cycling reliability come without increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probabili-

ty of oxide defects in the region. Finally, the peak
electric field during erasure is approximately 2 MV /
cm lower than EEPROM. The lower electric field
greatly reduces oxide stress and the probability of
failure-increasing time to wearout by a factor Of
100,000,000.
The device is programmed and erased using Intel's
Quick-Pulse Programming and Quick-Erase algorithms. Intel's algorithmic approach uses a series of
operations (pulses), along with byte verification, to
completely and reliably erase and program the device.
QUICK-PULSE PROGRAMMING ALGORITHM

The Quick-Pulse Programming' algorithm uses programming operations of 10 ,""S duration. Each operation is followed by a byte verification to determine
when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence of programming and byte verification is
performed with Vpp at high voltage; Figure 4 illustrates the Quick-Pulse. Programming algorithm.
QUICK-ERASE ALGORITHM

Intel's Quick-Erase algorithm yields fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the
Quick-Pulse Programming algorithm, to simultaneously remove charge from all bits in the array.
Erasure begins with a read of memory contents. The
28F512 is erased when shipped from the factory.
Reading FFH data from· the device would immediately be followed by device programming.
For devices being erased and reprogrammed, uniform and reliable erasure is ensured by first pro- .
gramming all bits in the device to their charged state
(Data = OOH). This is accomplished, using the
Quick-Pulse Programming algorithm, in approxi. mately one second.
Erase execution then continues with an initial erase
operation. Erase verification (data ~ FFH) begins at
address OOOOH and continues through the array to
the last address, or until data other than FFH is encountered. With each erase operation, an increaSing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the address of
the last byte verified in a register. Following the next
erase operation, verification starts at that stored address location. Erasure typically· occurs in one seconds. Figure 5 illustrates the Quick-Erase algorithm.

8-99

intel®

A28F512

Bus
Command
Operation

Standby

Comments

Wait for Vpp Ramp to VPPH(1)

Initialize Pulse-Count

Write.

Set-up
Program

Data

Write

Program

Valid Address/Data

Standby
Write

40H

Duration of Program
Operation (tWHWH1)
Program(3)
Verify .

Data = COH; Stops Program
Operation(2)

Standby

tWHGL

Read

Read Byte to Verify
Programming

Standby

Compare. Data Output to Data
Expected

Write

Standby

290265-5
NOTES:
1. See DC Characteristics for value of VpPH. The VPP
power supply can be hard-wired fo. the device or
switchable. When VPP is switched,· VPPl may be
ground, no-connect with· a resistor tied t() ground,· or
less than6.5V. Refer to Principles of Operation.
2. Refer to Principles of Operation.

Read

Data = OOH, Resets the
Register for Read Operations
Wait for VPP Ramp loVppL(1)

.3. Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the register is written with the Read command.
4_ CAUTION: The algorithm MUST BE FOLLOWED
. • 0 ensure proper and reliable operation of thedevice.

Figure 4.• 28F512 Quick-Pulse Programming Algorithm

8-100

intel®

A28F512

Bus
Command
Operation

Comments
Entire memory must
before erasure

= OOH

Use Quick·Pulse
Programming Algorithm
(Figure 4)
Standby

Wait for Vpp Ramp to VPPH(1)

Initialize Addresses and
Pulse·Count

Write

Set·up
Erase

Data = 20H

Write

Erase

Data

Duration of Erase Operation
(tWHWH2)

Standby
Write

Erase(3)
Verify

Addr = Byte to Verify;
Data = AOH; Stops Erase
Operation(2)

Standby

tWHGL

Read

Read Byte to Verify Erasure

Standby

Compare Output to FFH
Increment Pulse·Count

Write

Read

Standby

290265-6
NOTES:
1. See DC Characteristics for value of VPPH. The VPP
power supply can be hard·wired to the device or
switchable. When Vpp is switched, VpPL may be
ground, no·connect with a resistor tied to ground, or
less than 6.5V. Refer to Principles of Operation.
2. Refer to Principles of Operation.

= 20H

Data = OOH, Resets the
Register for Read Operations
Wait for VPP Ramp to Vppd1)

3. Erase Verify is performed only after chip·erasure. A
final read/compare may be performed (optional) after
the register is written with the read command.
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the de-

vice.

Figure 5. 28F512 Quick-Erase Algorithm

8·101

A28F512

DESIGN CONSIDERATIONS
Two-Line Output Control
Flash-memories are often used in larger memory arrays. Intel provides two read-control inputs to accommodate multiple memory connections. Two-line
control provides for:
a. the lowest possible memory power dissipation
and,
b. complete assurance that output bus contention
will not occur.
To efficiently use these two 'control inputs, an addr~ss-decoder output should drive chip-enable,
while the system's read signal controls all flashmemories and other parallel memories. This assures
that only enabled memory devices have active outputs, while deselected devices maintain the low
power standby condition.

Place the high-frequency, low-inherent-inductance
capacitors as close as possible to the devices. Also,
for every eight devices, a 4.7 J.l.F electrolytic capacitor should be placed at the array's power supply
conn~ction, between Vee and Vss. The bulk capacitor Will overcome voltage slumps caused by printedcircuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.

Vpp Trace on Printed Circuit ,Boards
Programming flash-memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the Vpp power supply trace. The Vpp pin supplies the memory cell current for programming. Use similar trace widths and
layout considerations given the Vee power bus. Adequate Vpp supply traces and decoupling will decrease Vpp voltage spikes and overshoots.
\

Power Up/Down Protection
Power Supply Decoupling
Flash memory power-switching characteristicsrequire careful device decoupling. System designers
are interested in three supply current (Ieel issuesstandby, active, and transient current peaks produced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 /LF ceramic capacitor
connected between Vee and Vss, and between Vpp
and Vss.

8-102

The 28F512 is designed to offer protection against
accidental erasure or programming, caused by spurious system-level signals that may exist during power
transitions. Also, with its control register architecture, alteration of memory contents only occurs after
successful completion of the two-step command sequences. Power supply sequencing is not required.
Internal circuitry of the 28F512 ensures that the
command register architecture is reset to the read
mode on power up.
A system designer must guard against active writes
for Vee voltages above the VLKO when Vpp is active. Since both WE # and CE # must be low for a
command write, driving either to VIH will prohibit
writes.

A28F512

The control register architecture provides an added
level of protection since alteration of memory contents only occurs after successful completion of the
two-step command sequences.

28F512 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time .. Flash nonvolatility increases the
usable battery life of your system because the
28F512 does not consume any power to retain code
or data when the system is off. Table 4 illustrates the
power dissipated when updating the 28F512.

Table 4_ 28F512 Typical Update
Power Dlsslpatlon(4)
Operation

Power Dissipation
Notes
(Watt-Seconds)

Array Program/
Program Verify

0.085

Array Erase/
Erase Verify

0.092

One Complete Cycle

0.262

NOTES:
1. Formula to calculate typical Program/Program Verify
Power = [Vpp x # Bytes x typical # Prog Pulses
(tWHWH1 x IpP2 typical + tWHGL X IpP4 typical») + [Vcc
x # Bytes x typical # Prog Pulses (twHWH1 x ICC2 typical + tWHGL X ICC4 typical»).
2. Formula to calculate typical Erase/Erase Verify Power
= [Vpp (lpP3 typical x tERASE typical + IpP5 typical x
tWHGL X # Bytes») + [VCC (lCC3 typical x tERASE typical
+ Iccs typical x tWHGL X # Bytes»).
3. Once Complete Cycle = Array Preprogram + Array
Erase + Program.
4. "Typicals" are not guaranteed, but based on a limited
number of samples from production lots.

8-103

intel®

A28F512

. Vee Supply Voltage with
Respect to Ground .......... - 2.0V to + 7.0V(2)

ABSOLUTE MAXIMUM RATINGS*
Operating Temperature
During Read,;" ,,'., ..... -40·C to + 125·C(1)
During Erase/Program ....... - 40·C to + 125·C
Temperature Under Bias ........ -40·C to/+ 125·C
Storage Temperature .......... - 65·C to. + 150·C
Voltage on Any Pin with
Respect to Ground .......... - 2.0V to + 7.0V(2)
Voltage on Pin Ag with
Respect to Ground ....... - 2.0V to + 13.5V(2, 3)
Vpp Supply Voltage with
Respeqtto Ground
During EraseIProgram .. ,. -2.0V to + 14.0V(2, 3)

Output Short Circuit Current ............. 100 mA(4)
Maximum Junction Temperature (TJ) ........ 140·C
NOTICE: This is a production data sheet. The
cations are subject to change without notice.

specifi~

• WARNING: Stressing the device beyond the "Absolute
Maximum Rati,?gs" may cause permanent damage.
These are stress. ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability."

NOTES:
1. Operating temperature is for automotive product as defined by this specification.
2. Minimum De input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for· periods less than 20 ns.
Maximum De voltage on output pins is Vee + 0.5V, which may overshoot to Vee + 2.0V for periods less than 20 ns.
3. Maximum De voltage on Ag or Vpp may overshoot to + 14.0V for periods less than 20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.

OPERATING CONDITIONS
Symbol

limits

Parameter
Min

Max

Unit

Comments
For Read-Only and
Read/Write Operations

Operating Temperature

-40

125

·C

Vee

Vee Supply Voltage

4.50

5.50

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE
Symbol

Parameter

Limits

Notes
Min

Typical.

Unit

Test Conditions

Max

III

Input Leakage
Current

±1.0

JJ-A

Vee = Vee Max
V,N = Vee or Vss

ILO

Output Leakage
Ourrent

±10

JJ-A

Vee = Vee Max
VOUT = Vee orVss

lees'

Vee Standby Current

1.0

Vee = Vee Max
CE# = V,H

lee1

Vee Active Read
Current

Vee = Vee Max, CE# = V,L
f = 6 MHz, lOUT = 0 mA

leC2

Vee Programming Current

1,2

1.0

Programming in Progress

leC3

Vee Erase Currant

1,2

5.0

Erasure in Progress

lee4

Vee Program Verify
Current

1,2

5.0

Vpp = VPPH
Program Verify in Progress

lee5

Vee Erase Verify Current

1,2

5,0

Vpp = VpPH
Erase Verify in Progress

Ipps

Vpp Leakage Current

. ±10

JJ-A

Vpp s Vee

IpP1

Vpp Read Current or
Standby Current

200

JJ-A

Vpp

±10

JJ-A

Vpp s Vee

8-104

1
1

Vee

A28F512

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE (Continued)
Symbol

Parameter

Notes

Limits
Min

Typ

Max

Test Conditions

Unit

IpP2

Vpp Programming
Current

1,2

8.0

rnA

Vpp = VPPH
Programming in Progress

IpP3

Vpp Erase Current

1,2

4.0

rnA

Vpp = VPPH
Erasure in Progress

IpP4

Vpp Program Verify
Current

1,2

2.0

5.0

rnA

Vpp = VpPH
Program Verify in Progress

IpP5

Vpp Erase Verify
Current

1,2

2.0

5.0

rnA

Vpp = VpPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

0.8

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH1

Output High Voltage

VID

A9 Intelligent Identifier
Voltage

liD

Vee ID Current

Vee

+ 0.5

IOL = 2.1 rnA
Vee = Vee Min

IOH = -2.5 rnA
Vee = Vee Min

13.00

VIO

rnA

VID

500

/LA

0.45

2.4
11.50
1

Vpp ID Current

V
V

VpPL

Vpp during Read-Only
Operations

0.00

6.5

VpPH

Vpp during Read/Write
Operations

11.40

12.60

VLKO

Vee Erase/Write Lock
Voltage

2.5

NOTE: Erase/Program are
Inhibited when Vpp = VpPL

DC CHARACTERISTICS-CMOS COMPATIBLE
Symbol

Parameter

Notes

limits
Min Typ Max

Unit

Test Conditions

III

Input Leakage Current

± 1.0 /LA Vee = Vee Max
VIN = VeeorVss

ILO

Output Leakage Current

±10

/LA Vee = Vee Max
VOUT = Vee or Vss

Ices

Vee Standby Current

100

/LA Vee = Vee Max
CE# = Vee ±0.2V

lee1

Vee Active Read Current

rnA Vee = Vee Max, CE# = VIL
f = 6 MHz, lOUT = 0 rnA

lee2

Vee Programming Current

1,2

1.0

rnA Programming in Progress
rnA Erasure in Progress

lee3

Vee Erase Current

1,2

5.0

lee4

Vee Program Verify Current

1,2

5.0

rnA Vpp

lee5

Vee Erase Verify Current

1,2

5.0

rnA Vpp

=
=

VPPH Program Verify in Progress
VpPHErase Verify in Progress

8-105

A28F512

DC CHARACTERISTICS-CMOS COMPATIBLE (Continued)
Symbol

Parameter

Limits

Notes
Min

Ipps

Vpp Leakage Current

IpP1

Vpp Read Current or
Standby Current

Typ

±10
90

Test Conditions

Unit
Max

200

",A
",A

Vpp

s::

Vee

.Vpp> Vee
Vpp ~ Vee

±10

IpP2

Vpp Programming Current

1,2

8.0

rnA

Vpp = VPPH
Programming in Progress

IpP3

Vpp Erase Current

1,2

4.0

rnA

VPP '" VPPH
Erasure in Progress

IpP4

Vpp Program Verify
Current

1,2

2.0

5.0

rnA

VPP = VPPH
Program Verify in Progress

IpP5

VPP Program Erase Verify
Current

1,2

2.0

5.0

rnA

VPP = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

0.7 Vee

VOL

Output Low Voltage

VOH1

Output High Voltage

0.8

+ 0.5

Vee

0.45

0.85 Vee

V
V

IOL = 2.1 rnA
Vee = Vee Min

IOH = - 2.5 mA,
Vee = Vee Min
IOH = -100 ",A,
Vee = Vee Min

Vee - 0.4

VOH2
VIO

Ag Intelligent Identifier
Voltage

110

Vee 10 Current

110

VPP 10 Current

VPPL

VPP during Read-Only
Operations

0.00

VPPH

VPP during Read/Write
Operations

11.40

VLKO

Vee Erase/Write Lock
Voltage

2.5

CAPACITANCE(3) TA
Symbol

25°C, f

11.50

13.00

rnA

500

6.5

NOTE: Erase/Programs are
Inhibited when VPP = VPPL

12.60

Vpp

= 10
= 10

= 12.0V

1.0 MHz

Limits

Parameter
Min

Unit

Conditions

Max

CIN

Address/Control Capacitance

VIN = OV

COUT

Output Capacitance

VOUT = OV

NOTES:

1.
2.
3.
4.

All currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, T = 25°C.
Not 100% tested: characterization data available.
Sampled, not 100% tested.
"Typicals" are not guaranteed, but are based on a limited number of samples from production lots.

8-106

intel~

A28F512

AC TESTING INPUT/OUTPUT WAVEFORM

AC TESTING LOAD CIRCUIT

2.4V

.!:~

INPUT
O.4SV

~l1N914

2.0V>
O.BV
TEST POINTS

OUTPUT

3.3K

DEVICE ,
UNDER
TEST

290265-7

AC Testing: Inputs are driven at 2.4V for a logic "I" and 0.45V for
a logic "0". Testing measurements are made at 2.0V for a logiC
"I" and 0.8V for a logic "O"~ RiS4!/Fall time s: 10 ns.

,1---1--0 OUT

CL =100pF

290285-8
CL = 100 pF
CL includes Jig Capacitance

AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels .........•...... 0.45Vand 2.4V
Input Timing Reference Level ....... O.BV and 2.0V
Output Timing Reference Level ...... O.BV and 2.0V

AC CHARACTERISTICS-Read-Only Operatlons(2)
Versions
Symbol

Characteristic

28F512-120

Notes

Min

Max

28F512-150

Min

Max

Unit

tAVAV/tRC

Read CyclE! Time

tELQV/tCE

Chip Enable
Access Time

120

150

tAVQV/tACC

Address Access Time

120

150

tGLQV/toE

Output Enable
Access Time

tELQX/tLZ

Chip Enable to
Output in Low Z

tEHQZ

Chip Disable to
Output in High Z

tGLQX/toLZ

Output Enable to
Output in Low Z

tGHQZ/tOF

Output Disable to
Output in High Z

toH

Output Hold from
Address, CE # ,
or OE# Change(1)

tWHGL

Write Recovery Time
before Read

120

150

0
50

0
30

""S

NOTES:
1. Whichever occurs first.
2. Rise/Fall Time,,;; 10 ns.
3. Not 100% tested characterization data available.
4. Guaranteed by design.

B-107

:r:-

...
U'I

STANDBY

VCC POWER-UP

to.)

DEVICE AND
ADDRESS SELECTION

OUTPUTS ENABLED

DATA VALID

STANDBY

,----.;...--------------------- -- ADDRESSES

ADDRESSES STABLE

Vcc POWER-DOWN

,
tAYAY(~C)

I'
."

CE# (E#)

~
):>

OE# (G#)

IIJ

t WHGl

• 1

...0'

::
a.

WE# (W#)

IoH

::I

I;)));b

DATA (DQ) .

EI( « «
I\'»)P

HIGH Z

IIJ

dC{(,1

---

~«{'1

-~~~~--------~\
~-,
I'

Vee ..I; ,-"
OV

--OUTPUT YALID

tAYQy(tACC)

·1

_.
J
c[
@

A28F512

AC CHARACTERISTICS-Write/Erase/Program Operations(1, 3)
Versions

Notes

Symbol

Characteristic

28F512·120
Min

Max

28F512·150
Min

Unit

Max

120

150

Data Set-up Time

tWHOX/tOH

Data Hold Time

tWHGL

Write Recovery Time
before Read

/l.s

tGHWL

Read Recovery Time
before Write

/l.s

tELWL/tCS

Chip Enable
Set-Up Time before Write

tAvAV/tWC

Write Cycle Time

tAVWL/tAS

Address Set-Up Time

tWLAX/tAH

Address Hold Time

tOVWH/tOS

tWHEH/tCH

Chip Enable Hold Time

tWLWH/tWP

Write Pulse Width(2)

tELEH

Alternative Write(2)
Pulse Width

tWHWL/tWPH

Write Pulse Width High

tWHWH1

Duration of
Programming Operation

/l.s

tWHWH2

Duration of Erase Operation

9.5

tVPEL

Vpp Set-Up
Time to Chip Enable Low

1.0

NOTES:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip·Enable and Write-Enable. In
systems where Chip-Enable defines the write pulse width (within a longer Write-Enable Jiming waveform) all set-up, hold, and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.
3. Rise/Fall time';; 10 ns.
4. The integrated stop timer terminates the programming/erase operations, thereby eliminating the need for a maximum
specification.
ERASE AND PROGRAMMING PERFORMANCE
Limits

Parameter
Min
Chip Erase Time
Chip Program Time
Erase/Program Cycles

1,000

Notes

Typ

Max

1,3,4,6

6.25

100,000

Unit

Comments

Sec

Excludes OOH Programming
Prior to Erasure

1,2,4

Sec

Excludes System-Level Overhead

1,5

Cycles

NOTES:

1. "Typicals" are not guaranteed, but based on a limited number of samples taken from production lots. Oata taken at
T = 25'C, Vpp = 12.0V, Vee = 5.0V.
2. Minimum byte programming time excluding system overhead is 16
(10
program + 6
write recovery), while
maximum is 400 ",s/byte (16
x 25 loops allowed by algorithm). Max chip programming time is specified lower than the
worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte.
3. Excludes OOH programming prior to erasure.
4. Excludes system-level overhead.
5. Refer to RR-60 "ETOX Flash Memory Reliability Oata Summary" for typical cycling data and failure rate calculations.
6. Maximum erase specification is determined by algorithmic limit 'Ind accounts for cumulative effect of erasure at
T = -40'C, 1,000 cycles, Vpp = 11.4V, Vee = 4.5V.

"'S

8-109

A28F512

99.9

V
V

I
99

. ,.

.,.._. l-

1.25

.... .- .-

.
. ..-

...

....//
'

...,. .'
;'

.~"-

. .'
.
.
/

;

J
~

V
11

~ :~

V
ro

"
o

,; 40

, 1.75

/
v

../,/

o.1
~

TEMP ('C)

1.25 1.5 1.752 2.252.5

7.5

Chip Program TIm. (.. e)

_1kCyciu
.--- 10k Cycles

-_•• lOOk Cycle.

290265-17

Figure 7. 28F512 Typical Program Time at 12V

- - 12V; 10 ko; 230C
------·11.4V; 10 kc; 700C
- - - - 12V; 100 ko; 2lOC

290265-18

Figure 8. 28F512 Typical Programming Capability

See Note 1, Page 8·109.

8-110

A28F512

,.9

1I ,
/ III' ,
/ ,I,
IV

,.8

'.
,.7
,.6

,.5

1.4

:: 1.3

"
~

1.1.1.

1.2

...

.,,

1.0

o.9

.'.
,,

"I'..

l'-

..i!l

'. ,
,,

" ,

........

o.6
MO

~ ~ ~ ~

a
,

:---. I'-. "
00

I"'-- r-..

I /,'

I ,/
V,' ,

o.7

,/ ,.', ' ,

"a ,~a

,oo,m,~,~,~

,
.,
a

0.3

/ 1/

.. 5a

r'-.

r--..

0.8

I Ii

0.5 0 . 7 '

4 5 6 7 89 10

CHIP ERASE TIME ( ••c)

TEWP (OC)

--'kCyc'"
- •• - 'Ok Cye",
---- 'OOk Cyel..

290265-19

NOTE:
Does not include Pre-Erase program.

Figure 9. 28F512 Typical Erase Time at 12V

- - - '2V;'0 kc; 230C
- - - - '1.4V; ,0 kc; OOC
.-----. '2V; ,00 kc; 230C

290265-20

NOTE:
Does not include Pre-Erq,~ program.

Figure 10. 28F512 Typical Erase Capability

See Note 1, Page 8-109.

8-111

!.....

•
N

PROGRAM CQMJilANO

I\)

Vee POWER-UP &:
STANDBY

SET - UP PROGRAM
COMMAND

LATCH- ADDRESS
&: DATA

PROGRAM
VERIFICATION

VERIFY

PROGRAMMING

COMMAND

...""

STAND~Y /

Vee POWER-DOWN

N
ADDRESSES

eE# (E#)

"11

IE
c::
Cil

:a-

OE# (G#)

WE# (w#)

3
0'
...

IIJ

(;

HIGH Z

DATA (DO)

;

3
3
$'
a

'tJ

'ElOX(\.z)

'u""
;0

u
z

1.,4
1.,3

28F256A
32 - PIN PLCC
0.450" x 0.550"
TOP VIEW

1.,1
OE#

1.,0

CE#

000

14 15 16 17 18 19 20

0"
o

g >t1 ct9 c1
c Jl
c c~
OJ

290168-3
29016S-2.

Figure 2. 28F256A Pin Configurations
Table 1. Pin Description
Symbol

Type

Name and Function

Ao-A14

INPUT

ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.

DOO-D07

INPUT/OUTPUT

CE#

INPUT

CHIP ENABLE: Activates the device's control logic, input buffers,
decoders and sense amplifiers. CE# is active low; CE high deselects
the memory device and reduces power consumption to standby levels.

OE#

INPUT

OUTPUT ENABLE: Gates the devices output through the data buffers
during a read cycle. OE# is active low.

WE#

INPUT

Vpp

ERASE/PROGRAM POWER SUPPLY for writing the command
register, erasing the entire array, or programming bytes in the array.

Vee

DEVICE POWER SUPPLY (5V ± 10%)

Vss

GROUND

NO INTERNAL CONNECTION to device. Pin may be driven or left
floating.

8-117

'inte!®

A28F256A

Material and labor costs associated with code
changes increase at higher levels of system integration-the most costly being code updates after sale.
Code "bugs", or the desire to augment system functionality, prompt after-sale code updates. Field revisions to EPROM-based code require the removal of
EPROM components or entire boards.

APPLICATIONS
The 28F256A flash memory adds electrical chip-erasure and reprogrammability to EPROM non-volatility
and ease of use. The 28F256A is ideal for storing
code or data,tables in applications where periodic
updates are required. The 28F256A also serves as a
dense, nonvolatile data acquisition and storage medium.

Designing with the in-circuit alterable 28F256A eliminates sock,eted memories, reduces overall material
costs, arid drastically cuts the labor costs associated with code updates. With the 28F256A, code updates are implemented locally via an edge-connector, or remotely over a serial communication link.

The need for code updates pervades all phases of a
system's life-from prototyping to system manufacture to after-sale service. In the factory, during prototyping, revisions to control code necessitate ultraviolet erasure and reprogramming of EPROM-based
prototype· codes. The 28F256A replaces the 15- to
20-minute ultraviolet erasure with one-second electrical erasure. Electrical chip-erasure and reprogramming occur in the same workstation or PROMprogrammer socket.

The 28F256A's electrical chip-erasure, byte reprogrammability, and complete nonvolatility fit well with
data accumulation needs. Electrical Chip-erasure
gives the designer a "blank-slate" in which to log
data. Data can be periodically off-loaded for analysis-erasing the slate and repeating the cycle: Or,
multiple devices can maintain a "rolling window" of
accumulated data.

Diagnostics, performed at subassembly or final assembly stages, often require the socketing of
EPROMs. Socketed test codes are ultimately replaced with EPROMs containing the final program.
With electrical chip-erasure and reprogramming, the
28F256A is soldered to the circuit board. Test codes
are programmed into the 28F256A as it resides on
the circuit board. Ultimately, the final code can be
downloaded to the device. The 28F256A's in-circuit
alterability eliminates unnecessary handling and
less-reliable socketed connections, while adding
greater test flexibility.

A high degree of on-chip feature integration simplifies memory-to-processor interfacing. Figure 3 illustrates the interface between the MCS®-51 microcontroller and one 28F256A flash memory in a
minimum Chip-count system. Figure 4 depict~ two
28F256As tied to the 80C186 system bus. In both
instances, the 28F256A's architecture minimizes interface circuitry needed for complete in-circuit updates of memory contents. (Comprehensive system
design information is included in AP-316, "Using

Vee

ADo -AD7

ALE

~°D-DO-,

LATeH
STB

As-A 7

°1
eE"

28F256A

tAeS-51

As -A14

Ae-A14

WR#
PSEN#
RO#

WE#
OE#

290168-4

Figure 3. 28F256A In an MCS®-51 System

8-118

intel~

A28F256A

80C186
SYSTEM BUS

Vee

A, -1<,5

---------"

Ao-A'4

+---------+1 DQO-D~

MCSO# - - - - - - - - - " CE#
BHE#

>-----"WE#

WR#

RD# - - - - _ - - - -.. OE#

290168-5

Figure 4. 28F256A in an 80C186 System
the 28F256A Flash Memory for In·System Reprogrammable Nonvolatile Storage", Order Number
292046-002).
With cost-effective in-system reprogramming and
extended cycling capability, the 28F256A fills the
functionality gap between traditional EPROMs and
E2PROMs.
EPROM-compatible
specifications,
straightforward interfacing, and in-circuit alterability
allows designers to easily augment memory flexibili- .
ty and satisfy the need for updatable nonvolatile
storage in today's designs.

PRINCIPLES OF OPERATION
Flash-memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F256A introduces a command register to manage
this new functionality. The command register allows
for: 100% TTL-level control inputs; fixed power supplies during erasure and programming; and maximum EPROM compatibility.
In the absence of high voltage on the Vpp pin, the
28F256A is a read-only memory. Manipulation of the
external memory-control pins yields the standard
EPROM read, standby, output disable, and intelligent identifier operations.
The same EPROM read, standby, and output disable
operations are available when high voltage is applied to the Vpp pin. In addition, high voltage on Vpp

enables erasure and programming of the device. All
functions associated with altering memory contents-intelligent identifier, erase, erase verify, program, and program verify-are accessed via the
command register.
Commands are written to the register using standard
microprocessor write timings. Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for programming or erase operations. With
the appropriate command written to the register,
standard microprocessor read timings output array
data, access the intelligent identifier codes, or output data for erase and program verification.

Integrated Program/Erase Stop Timer
Successive command write cycles define the durations of program and erase operations; specifically,
the program or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simplified timing control over these operations; thus eliminating the need for maximum program/erase timing
specifications. Programming and erase pulse durations are minimums only. When the stop timer terminates a program or erase operation, the device enters an inactive state and remains inactive until receiving the appropriate verify or reset command.

8-119

A28F256A

Table 2. 28F256A Bus Operations
Pins

lAo

CE#

VPPL

VIL

VIH

Data Out

VPPL

VIL

VIH

Tri-State
Tri-State

vppf1r

Operation
Read
O~tput

READ-ONLY

READ/WRITE

Disable

OE#

WE#

DQo-DQ7

Standby

VpPL

VIH

intelligent 10 Manufacturer(2)

VpPL

VIL

VID(3)

VIL

VIH

VIL

VIH

= 89H
Data = 89H

VIL

VIH

Data Out(4)

Data

intelligent 10 Device(2)

VPPL

VIH

VID(3)

Read

VpPH

Output Disable

VpPH

VIL

VIH

Tri-State

Standby(S)

VpPH

VIH

Tri-State

Write

VpPH

VIL

VIH

VIL

Data In(S)

NOTES:
1. VPPL may be ground, a no-connect with a resistor tied to ground, or ,;; S.SV. VpPH is the programming voltage specified
for the device. Refer to D.C. Characteristics. When Vpp = VpPL memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
addresses low. ,
3. VID is the intelligent identifier high voltage. Refer to DC Characteristics.
4. Read operations with Vpp = VPPH may access array data or the intelligent 10.
5. With Vpp at high voltage, the standby current equals Icc + Ipp (standby).
6. Refer to Table 3 for valid Data-In during a write operation.
7. X can be VIL or VIH.

Write Protection
The command register is only alterable when Vpp is
at high voltage. Depending upon the application, the
system designer may choose to make the Vpp power supply switchable-available only when memory
updates are desired. When high voltage .is removed,
the contents of the register default to the read command, making the 28F256A a read-only memory.
Memory contents cannot be altered,.
Or, the system designer may choose to "hardwire"
Vpp, making the high voltage supply constantly
available. In this instance, all operations are performed in conjunction with the command register.
The 28F256A is designed to accommodate either
design practice, and to encourage optimization of
the processor-memory interface: '
The two-step Program/Erase write sequence to the
command register provides additional software write
'
protection.
BUS OPERATIONS
Read
The 28F256A has two control functions, both of
which must be logically active, to obtain data at the
outputs. Chip:Enable (CE #) is the power control and
should be used for device sell9ction. Output-Enable
(OE #) is the output control and should be used to
8-120

gate data from the output pins, independent of device selection. Figure 7 illustrates read timing waveforms.
When Vpp is low (VppLl, the read only operation is
active. This permits reading the data in the array and
outputting the intelligent identifier codes (See Table
2). When Vpp is high (VPPH), the default condition of
the device is the read-only mode. This allows reading the data in the array: Further functionality is
achieved through the Command Register as shown
in Table 3.
Output Disable
With Output-Enable at a logic-high level (VIH), output
from the device is disabled. Output pins are placed
in a high-impedance state.
Standby
With Chip-Enable at a logic-high level, the standby
operation disables most of the 28F256A's circuitry
and substantially reduces device power consumption. The outputs are placed in a high-impedance
state, independent of the Output-Enable signal. If
the 28F256A is deselected during erasure, programming, or program/erase verification, the device
draws active current until the operation is terminated.

A28F256A
state-machine outputs dictate the function of the
device.

Intelligent Identifier Operation
The Intelligent Identifier operation outputs the manufacturer code (89H) and device code (B9H).Programming equipment automatically matches the device with its proper erase and programming
algorithms.
With Chip-Enable and Output-Enable at a logic low
level, raising A9 to high voltage, VID (See DC Characteristics), activates the operation. Data read from
locations OOOOH and 0001 H represent the manufacturer's code and the device code, respectively.
The manufacturer- and device-codes can also be
read via the command register, for instances where
the 28F256A is erased and reprogrammed in the target system. Following a write of 90H to the command register, a read from address location OOOOH
outputs the manufacturer code (89H). A read from
address 0001 H outputs the device code (B9H).
Write
Device erasure and programming are accomplished
via the command register, when high voltage is applied to the Vpp pin. The contents of the register
serve as input to the internal state-machine. The

The command register itself does not occupy an addressable memory location. The register is a latch
used to store the command, along with address and
data information needed to execute the command.
The command register is written by bringing WriteEnable to a logic-low level (Vld, while Chip-Enable is
low. Addresses are latched on the falling edge of
Write-Enable, while data is latched on the rising
edge of the Write-Enable pulse. Standard microprocessor write timings are used.

I
I

Refer to A.C. Write Characteristics and the Erase/
Programming Waveforms for specific timing
parameters.
COMMAND DEFINITIONS
When low voltage is applied to the Vpp pin, the contents of the command register default to OOH, enabling read-only operations.
Placing high voltage on the Vpp pin enables read/
write operations. Device operations are selected by
writing specific data patterns into the command register. Table 3 defines these 28F256A register
commands.

Table 3. Command Definitions
Command

Bus
First Bus Cycle
. Second Bus Cycle
Cycles
Req'd Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3)
1

Write

OOH

Read Intelligent ID(4)

Write

90H

Read

Set-up Erase/Erase(S)

Write

20H

Write

20H

Erase Verify(S)

Write

AOH

Read

EVD

Set-up Program/Program(6)

Write

40H

Write

Program Verify(6)

Write

COH

Read

PVD

Reset(7)

Write

FFH

Write

FFH

NOTES:
1. Bus operations are defined in Table 2.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during erase verity.
PA = Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
3. ID = Data read from location IA during device identification (Mfr = 89H, Device = B9H).
EVD = Data read from location EA during erase verify.
PD = Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
PVD = Data read from location PA during program verity. PA is latChed on the Program command.
4. Following the Read Intelligent 10 command, two read operations access manufacturer and device codes.
S. Figure 6 illustrates the QuiCk-Erase Algorithm.
6. Figure S illustrates the Quick-Pulse Programming Algorithm.
7. The second bus cycle must be followed by the desired command register write.

i
I

Read Memory

8-121

intel®

A28F256A

Read Command

While Vpp is high,for erasure and programming,
memory contents can be accessed via the read
command. The Jeadoperationis initiated by writing
OOH into the· command .register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register contents are altered.
The default contents of the register upon Vpp power-up is OOH. This default value ensures that no spurious alteration of memory contents occurs during
the Vpp power transition. Where the Vpp supply is
hard-wired to the 28F256A, the device powers-up
and remains enabled for reads until the commandregister contents are changed. Refer to the A.C.
Read Characteristics and Waveforms for specific
timing parameters.
Intelligent Identifier Command

Flash memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be ac-.
cessible while the device. resides in the target system. PROM programmers typically access signature
codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not a desired system-design practice.
The 28F256A contains an Intelligent Identifier operation to supplement traditional PROM-programming
methodology. The operation is initiated by writing
90H into the command register. Following the command write, a read cycle from address OOOOH retrieves the manufacturer code of 89H. A read cycle
from address 0001 H returns the device code of
89H. To terminate the operation, it is necessary to
write another valid command into the register.

of this high voltage, memory contents are protected
against erasure. Refer to AC. Erase Characteristics
and Waveforms for specific timing parameters.
Erase-Verify Command

The erase command erases all bytes of the array in
parallel. After each erase operation, all bytes must
be·verified. The erase verify operation is initiated by
writing AOH into the command register. The address
for the byte to be verified must be supplied as it is
latched on the falling edge of the. Write-Enable
pulse. The register write terminates the erase operation with the rising edge of its Write-Enable pulse.
The 28F256A applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is acc,essed.
.
In the case where the data read is not FFH, ahother
erase operation is performed. (Refer to Set-up
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once all bytes in
the array have been verified, the erase step is complete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g. Program Set-up) to the command
register. Figure 6, the Quick-Erase AlgOrithm, illustrates how commands and bus operations are combined to perform electrical erasure of the 28F256A
Refer to AC. Erase Characteristics and Waveforms
for specific timing parameters.
Set-up Program/Program .Commands

Set-up Erase/Erase Commands

Set-up Erase is a command"only operation that
stages the device for electrical erasure of all bytes in
the array. The set-up erase operation is performed
by writing 20H to the command register.
To commence chip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
Write-Enable pulse and terminates with the rising
edge of the next Write-Enable pulse (Le., Erase-Verify Command).
This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when
high voltage is applied to the Vpp pin. In the absence

8-122

Set-up program is a command-only operation that
stages the device for byte programming. Writing 40H
into t.he command register performs the set-up
operation.
Once the program set-up operation is performed,
the next Write-Enable pulse causes a transition to
an active programming operation. Addresses are internally latched on the falling edge of the Write-Enable pulse. Data is internally latched on the rising
edge of the Write-Enable pulse. The rising edge of
Write-Enable also begins the programming operation. The programming operation terminates with the
next rising edge of Write-Enable, used to write the
program-verify command. Refer to AC. Programming Characteristics and Waveforms for specific
timing parameters.

A28F256A

Program-Verify Command

The 28F256A is programmed on a byte-by-byte basis. Byte programming may occur sequentially or at
random. Following each programming operation, the
byte just programmed must be verified.
The program-verify operation is initiated by writing
COH into the command register. The register write
terminates the programming operation with the rising edge of its Write-Enablt!l pulse. The program-verify operation stages the device for verification of the
byte last programmed. No new address information
is latched.
The 28F256A applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 5,
the 28F256A Quick-Pulse Programming Algorithm,
iIIust~ates how commands are combined with bus
operations to perform byte programming. Refer to
A.C. Programming Characteristics and Waveforms
for specific timing parameters.

2 mV/cm lower than EEPROM. The lower electric
field greatly reduces oxide stress and the probability
of failure-increasing time to wearout by a factor of
100,000,000.
The device is programmed and erased using Intel's
Quick-Pulse Programming and Quick-Erase algorithms. Intel's algorithmic approach uses a series of
operations (pulses), along with byte verification, to
completely and reliably erase and program the device.
For further reliability information, see Reliability Report RR-60 (ETOX II Reliability Data Summary).
QUICK-PULSE PROGRAMMING ALGORITHM

The Quick-Pulse Programming algorithm uses programming operations of 10 J.ts duration. Each operation is followed by a byte verification to determine
when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence of programming and byte verification is
performed with Vpp at high voltage; Figure 5 illustrates the Ouick-Pulse Programming algorithm.

Reset Command

A reset command is provided as a means to safely
abort the erase- or program-command sequences.
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort
the operation. Memory contents will not be altered.
A valid command must then be written to place the
device in the desired state.
EXTENDED ERASE/PROGRAM CYCLING

EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubledan expensive solution.
Intel has designed extended cycling capability into
its ETOX-II flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge-carrying ability ten-fold. Second, the oxide area per ceU
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probability of oxide defects in the region. Finally, the peak
electric field during erasure is approximately

QUICK-ERASE ALGORITHM

Intel's Quick-Erase algorithm yields fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the
Quick-Pulse Programming algorithm, to simultaneously remove charge from all bits in the array.
Erasure begins with a read of memory contents. The
28F256A is erased when shipped from the factory.
Reading FFH data from the device would immediately be followed by device programming.
Uniform and reliable erasure is ensured by first programming all bits in the device to their charged state
(Data = DOH). This is accomplished, using the
Quick-Pulse Programming algorithm, in approximately, one-half second.
Erase execution then continues with an initial erase
operation. Erase verification (data = FFH) begins at
address OOOOH and continues through the array to
the last address, or until data other than FFH is encountered. With each erase operation, an increasing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the .address of
the last byte verified in a register. Following the next
erase operation, verification starts at that stored address location. Erasure typically occurs in one second. Figure 6 illustrates the Quick-Erase Algorithm.

8-123

intel®

A28F256A

Bus
COmmand
Operation

Standby

Comments

Wait for Vpp Ramp to VpPH(1)

Initialize Pulse-Count

Write

Set-up
Program

Data = 40H

Write

Program

Valid Address/Data

Duration of Program
Operation (tWHWH1)

Standby
Write

Data = COH; Stops Program
Operation(2)

Standby

tWHGl

Read

Read Byte to Verify
Programming

Standby

Compare Data Output to Data
Expected

Write

Standby

290168-6

Program(3)
Verify

Read

Data = OOH. Resets the
Register for Read Operations
Wait for Vpp Ramp to Vppd1)

NOTES:
1. See DC Characteristics for value of VPPH. The Vpp
power supply can be hard-wired to the device or switchable. When Vpp is switched. VpPl may be ground. no-connect with a resistor tied to ground. or less than 6.5V. Refer to Principles of Operation.
2.· Refer to Principles of Operation:
3. Program Verify is only performed aiter byte programming. A final read/compare may be performed (optional)
aiter the register is written with the Read command.
4. CAUTION: The algorithm MUST BE FOLLOWED to
ensure proper and reliable operation of the device.

Figure 5. 28F256A Quick~Pulse Programming Algorithm

8-124

A28F256A

Bus
Operation

Command

Comments
Entire memory must
before erasure

= OOH

Use Quick-Pulse
Programming Algorithm
(Figure 5)
Standby

Wait for VPP Ramp to VPPH(1)

Initialize Addresses and
Pulse-Count

Write

Set-up
Erase

Data

= 20H

Write

Erase

Data

= 20H

Standby
Write

Duration of Erase Operation
(tWHWH2)
Erase(3)
Verify

Addr = Byte to Verify;
Data = AOH; Stops Erase
Operation(2)

Standby

tWHGL

Read

Read Byte to Verify Erasure

Standby

Compare Output to FFH
Increment Pulse-Count

Write

Read

Standby

Data = OOH, Resets the
Register for Read Operations
Wait for VPP Ramp to Vppd1)

290168-7

NOTES:
1. See DC Characteristics for value of VPPH. The VPP
power supply can be hard-wired to the device or
switchable. When VPP is switched, VPPL may be
ground, no-connect with a resistor tied to ground, or
less than 6.5V. Refer to Principles of Operation.
2. Refer to Principles of Operation.

3. Erase Verify is performed only after chip-erasure. A
final read/compare may be performed (optional) after
the register is written with the read command.
4. CAUTION: The algorithm MUST BE FOLLOWED to
ensure proper and reliable operation of the device.

Figure 6. 28F256A Quick-Erase Algorithm

8-125

A28F256A

D.ESIGN CONSIDERATIONS
Two-Line Output Control
Flash memories are often used in larger memory arrays. Intel provides two read-control inputs to accommodate multiple memory connections. Two-line
control provides for:
a. the ·Iowest possible memory power dissipation
and,
b. complete assurance- that output bus contention
will not occur.
To efficiently use these two control inputs, an address-decoder output should drive chip-enable,
while the system's read signal controls all flash
memories and other parallel memories. This. assures
that only enabled memory devices have active outputs, while deselected devices maintain the low
power standby condition.

Power Supply Decoupling

Vpp Trace on Printed Circuit Boards
Programming flash memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the Vpp power supply trace. The Vpp pin supplies the memory cell current for programming. Use similar trace widths and
layout considerations given the Vee power bus. Adequate Vpp supply traces and decoupling will decrease Vpp voltage spikes and overshoots.

Power Up/Down Protection
The 28F256A is designed to offer protection against
accidental erasure or programming, caused by spuri~
ous system-level signals that may exist during power
transitions. Also, witli its control register architecture, alteration of memory contents only occurs after
successful completion of the two-step command sequences. Power supply sequencing is not required.
Internal circuitry of the 28F256A ensures that the
command register architecture is reset to the read
mode on power up:

Flash memory power-switching characteristics· require careful device decoupling. System designers
are interested in three supply current (led issuesstandby, active, and transient current peaks produced by falling. and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.

A system designer must guard against active writes
for Vee voltages above VLKO when Vpp is active.
Since both WE # and CE # must be low for a command write, driving either to VIH will inhibit writes.
The control register architecture provides an added
level of protection since alteration of memory contents only occurs after successful completion of the
two-step command sequences.

Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 p.F ceramic capacitor
connected between Vee and Vss, and between Vpp
and Vss.

28F256A Power Dissipation

Place the high-frequency, low-inherent-inductance
capacitors as close as possible to the devices. Also,
for every eight devices, a 4.7 p.F electrolytic capacitor should be placed at the array's power supply
connection, between Vee and Vss. The bulk capacitor will overcome voltage slumps caused by printedcircuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.

8-126

When designing portable systems, deSigners must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory nonvolatility increases the usable biittery life of your system because the 28F256A does not consume any power to
retain code or data when the system is off. Table 4
illustrates the power dissipated when updating the
28F256A.

A28F256A

Table 4. 28F256A Typical Update Power Dissipatlon(4)
Operation

Power Dissipation
(Watt-Seconds)

Array Program/Program Verify

0.043

Array Erase/Erase Verify

0.083

One Complete Cycle

0.169

Notes

NOTES:
1. Formula to calculate typical Program/Program Verify Power = [Vpp x # Bytes x typical # Prog Pulses (tWHWHl x IpP2
typical + tWHGL x IpP4 typical)] + [Vcc x # Bytes x typical # Prog Pulses (tWHWHl x ICC2 typical + tWHGL x ICC2
typical)].
2. Formula to calculate typical Erase/Erase Verify Power = [Vpp (lPP3 typical x tERASE typical + IpP5 typical x tWHGL x
# Bytes)] + [VCc(ICC3 typical x tERASE typical + Iccs typical x tWHGL x # Bytes)].
3. One Complete Cycle = Array Preprogram + Array Erase + Program.
4. "Typicals" are not guaranteed, but based on a limited number of samples from production lots.

8-127

intel®

A28F256A

ABSOLUTE MAXIMUMRATINGS*

Vee Supply Voltage with
Respect to Ground· .......... - 2.0V to + 7.0V(2)

Operating Temperature
During Read .............. - 40°C to + 125°C(1)
During Erase/Program ....... -40°C to + 125°C

Output Short Circuit Current .......... ; .. 100mA(4)

Temperature Under Bias ........ -40°C to + 125°C
Storage Temperature .......... -65°C to· + 150°C
Voltage on Any Pin with
Respect to Ground .......... - 2.0V to + 7.0V(2)
Voltage on Pin Ag with
Respect to Ground ....... - 2.0V to + 13.5V(2, 3)
Vpp Supply Voltage With
Respect to Ground
During Erase/Program .... - 2.0V to + 14.0V(2, 3)

Maximum Junction Temperature (TJ) ........ 140°C
NOTICE: This is a production data sheet. The specifications are subject to change without notice.

NOTES:

1. Operating temperature is for automotive product defined by this specification.
2. Minimum De input voltage is - 0.5V. During transitions, inputs may undershoot to - 2.0V for periods less than 20 ns.
Maximum De voltage on output pins is Vee + 0.5V, which may overshoot to Vee + 2.0V for periods less than 20 ns.
3. Maximum De voltage on Ag or Vpp may overshoot to + 14.0V for periods less than 20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.

OPERATING CONDITIONS
Symbol

limits

Parameter
Min

Max

Unit

Comments
For Read-Oniy and
Read/Write Operations

Operating Temperature

-40

+125

°C

Vee

Vee Supply Voltage

4.50

5.50

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE
Symbol

Parameter

Limits

Notes
Min

Typical

Unit

Test Conditions

Max

III

Input Leakage Current

± 1.0

p.,A

Vec = Vce Max
VIN= Vce or Vss

ILO

Output Leakage Current

±10

p.,A

Vcc = Vcc Max
VOUT = Vee or Vss

lecs

Vec Standby Current

1.0

Vce = Vec Max
CE# = VIH

ICC1

Vce Active Read Current

Vee = Vee Max, CE# = VIL
f = 6 MHz, lOUT = 0 mA

ICC2

Vee Programming Current

1,2

1.0

Programming in Progress·

lec3

Vce Erase Current

1,2

5.0

Erasure in Progress

lec4

Vee Program Verify Current

1,2

5.0

Vpp = VpPH
Program Verify in Progress

lec5

Vee Erase Verify Current

1,2

5.0

VPP = VPPH
Erase Verify in Progress

IpPS

VPP Leakage Current

±10

p.,A

VPP ~ Vcc

8-128

A28F256A

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE (Continued)
Symbol

Parameter

Limits

Notes

Unit

Min Typical
IpP1

Vpp Re~d Current or
Standby Current

Test Conditions

Max

200

"A Vpp> Vee
"A Vpp S; Vee

±10

IpP2

Vpp Programming Current

1.2

8.0

mA Vpp = VPPH
Programming in Progress

IpP3

Vpp Erase Current

1.2

4.0

mA Vpp = VPPH
Erasure in Progress

IpP4

Vpp Program Verify Current

1.2

2.0

5.0

"A Vpp = VPPH
Program Verify in Progress

Ipps

Vpp Erase Verify Current

1.2

2.0

5.0

mA Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH1

Output High Voltage

0.8

Vee + 0.5 V
0.45

V IOH = -2.5mA
Vee = Vee Min

2.4

VIO

Ag Intelligent Identifer Voltage

110

Vee 10 Current

11.50
1

Vpp 10 Current

IOL = 2.1 mA
Vee = Vee Min

13.00
10

500

VIO

Ag = VIO
"A
V NOTE: Erase/Program are
Inhibited when Vpp = VPPL

VPPL

Vpp during Read-Only Operations

0.00

6.5

VPPH

Vpp during Read/Write Operations

11.40

12.60

VLKO

Vee Erase/Write Lock Voltage

2.5

V Ag
mA

V
V

DC CHARACTERISTIC&-CMOS COMPATIBLE
Symbol

Parameter

Notes

Limits

Unit

Test Conditions

Min Typical Max
III

Input Leakage Current

±1.0 "A Vee = Vee Max
VIN = Vee or Vss

ILO

Output Leakage Current

±10 "A Vee = Vee Max •
VOUT = VeeorVss

Ices

Vee Standby Current

100

"A Vee = Vee Max
CE# = Vee ±0.2V

lee1

Vee Active Read Current

mA Vee = Vee Max. CE# = VIL
f

6 MHz. lOUT

0 mA

lee2

Vee Programming Current

1.2

1.0

mA Programming in Progress

lee3

Vee Erase Current

1.2

5.0

mA Erasure in Progress

rnA Vpp = VPPH Program Verify in Progress

mA Vpp = VPPH Erase Verify in Progress

1CC4

Vee Program Verify Current

1.2

5.0

lees

Vee Erase Verify Current

1.2

5.0

8-129

A28F256A

DC CHARACTERISTICS-CMOS COMPATIBLE (Continued)
Symbol

Parameter

Limits

Notes
Min

Ipps

Vpp Leakage Current

IpP1

Vpp Read Current or
Standby Current

Typical

Unit

Test Conditions

Max
±10

200

/LA Vpp
/LA

±10

Vee

Vpp> Vee
Vpp

Vee

IpP2

Vpp Programming Current

1,2

8.0

mA Vpp = VPPH
Programming in Progress

IpP3

Vpp E(ase Currellt

1,2

4.0

mA Vpp = VPPH
Erasure in Progress

IpP4

Vpp Program Verify Current

1,2

2.0

5.0

mA Vpp = VPPH
Program Verify in Progress

IpP5

Vpp Erase Verify Current

1,2

2.0

5.0

mA Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

0.7 Vee

VOL

Output Low Voltage

VOH1

0.8
Vee

+ 0.5

0.45

Output High Voltage

V
V IOL = 2.1 mA
Vee = Vee Min
V

0.85 Vee

VOH2

IOH = -100/LA,
Vee == Vee Min

Vee - 0.4
Ag Intelligent Identifer
Voltage

VIO

IOH = - 2.5 mA,
Vee = Vee Min

11.50

13.00

110

. Vee 10 Current

mA Ag

500

/LA Ag

110

Vpp 10 Current

VPPL

Vpp during
Read-Only Operations

0.00

6.5

VpPH

Vpp during Read/
Write Operations

11.40

12.60

VLKO

Vee Erase/Write Lock Voltage

= 10
= 10

V NOTE: Erase/Programs are
Inhibited when Vpp = VPPL
V Vpp

12.0V

2.5

CAPACITANCE(3) TA = 25°C, f = 1.0 MHz
Symbol

Limits

Parameter
Min

Unit

Co,nditions

Max

CIN

Address/Control Capacitance'

VIN = OV

COUT

Output Capacitance

VOUT = OV

NOTES:
1.
2.
3.
4.

All currents are inRMS unless otherwise noted. Typical values at Vee = 5.0V. Vpp = 12.0V. T = 25'e.
Not 100% tested: characterization data available.
Sampled, not 100% tested.
"Typicals" are not guaranteed, but are based ona limited number of samples from production lots.

8-130

A28F256A
AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ................ 0.45V and 2.4V
Input Timing Reference Level ....... 0.8V and 2.0V
Output Timing Reference Level ...... 0.8V and 2.0V
AC TESTING INPUT/OUTPUT WAVEFORM

AC TESTING LOAD CIRCUIT

2.4V

1.3V

INPUT
a.45V...Il----------

lN914
2.av
a.8V

3.3K

TEST POINTS

t--+-o OUT

290168-8

AC Testing: Inputs are driven at 2.5V for a logic "1" and 0.45V for
a logic "0". Testing measurements are made at 2.0V for a logic
"1" and 0.8V for a logic "0". Rise/Fall time ,;; 10 ns.

290168-9

CL = 100 pF
CL includes Jig Capacitance

AC CHARACTERISTIC5-Read-Only Operations(2)
Versions
Symbol
tAVAV/tRC
tELQv/tCE

Characteristic
Read Cycle Time

28F256A-120

28F256A-150

Notes

Min

120

Chip Enable
. Access Time

Max

Unit

Max

150

120

150

tAVQv/tACC

Address Access Time

120

150

tGLQV/tOE

Output Enable
Access Time

tELQX/tLZ

Chip Enable to
Output in LolO/ Z

tEHQZ

Chip Disable to
Output in High Z

tGLQX/tOLZ

Output Enable to
Output in Low Z

tGHQZ/tOF

Output Disable to
Output in High Z

tOH

Output Hold from
Address, CE # ,
or OE # Change

1,3

tWHGL

Write Recovery Time
before Read

0
50

55
0

ns
ns

/Ls

NOTES:
1. Whichever occurs first.
2. Rise/Fall Time s 10 ns.
3. Not 100% tested: characterization data available.
4. Guaranteed by design.

8-131

~
N
CXI

c.:>

I\)

."
N

Vee POWER-UP

STANDBY

DEVICE AND
ADDRESS SELECTION

OUTPUTS ENABLED

DATA VALID

STANDBY

J
ADDRESSES

,
ADDRESSES STABLE

,
tAvAv{~e)

"11
i'jj

;

Vee POWER-DOWN

CE# (E#)

;

:"I
l>

OE# (G#)

i3
1/1

...0-

t WHGL

..
WE#

(w#)

toH

m
D-

'tI
CD

DATA {DQ}

1/1
5.0V
Vee

"' /

OUTPUT VALID

I'»)}P

---

HIGH Z

iil:::!:
o~

I;""b
(I(
«I
tAVQv{tAee)

---

d«( ..1

q(/'I

~'M-,"

£
@l

A28F256A

AC CHARACTERISTICS-Write/Erase/Program Operations(1,3)
Versions

28F256A-120

Symbol

Characteristic

Notes

Min

28F256A-150

Max

Unit

150

0
60
50
10

IJ-s

0
80
80

2
2

Duration of
Programming Operation

20'
10

20
10

IJ-s

tWHWH2

Duration of
Erase Operation

9.5

tVPEL

Vpp Set-Up
Time to Chip Enable Low

1.0

tAVAV/tWC

Write Cycle Time

tAVWL/tAS

Address Set-Up Time

tWLAX/tAH

Address Hold Time

tDVWH/tDS

Data Set-up Time

tWHDX/tDH

Data Hold Time

tWHGL

Write Recovery Time
before Read

tGHWL

Read Recovery Time
before Write

tELWL/tcs

Chip Enable
Set-Up Time before Write

tWHEH/tCH

Chip Enable Hold Time

tWLWH/tWP

Write Pulse Width

tELEH

Alternative Write
Pulse Width

tWHWL/tWPH

Write Pulse Width High

tWHWH1

120
0

Min

60
50
10
6

ns
ns
ns

NOTES:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up, hold, and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.
3. Rise/Fall time s 10 ns.
4. The integrated stop timer terminates the programming/erase operations, thereby eliminating the need for a maximum
specification;

ERASE AND PROGRAMMING PERFORMANCE
Parameter

Limits

Notes
Min

Chip Erase Time
Chip Program Time
Erase/Program Cycles

1,3,4,6
1,2,4
1,3,5

1,000

Unit

Typ

Max

0.5
100,000

3.1

Comments

Sec

Excludes OOH Programming
Prior to Erasure

Sec

Excludes System-Level Overhead

Cycles

NOTES:

1. "Typicals" are not guaranteed, but based on a limited number of samples taken from production lots. Data taken at
T = 25°C, Vpp = 12.0V, Vee = 5.0V.
'
2. Minimum byte programming time excluding system overhead is 16
(10
program + 6
write recoveM, while
maximum is 400 ",s/byte (16
x 25 loops allowed by algorithm). Max chip programming time is specified lower than the
worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte.
3. Excludes OOH Programming prior to erasure.
4. Excludes system-level overhead.
5. Refer to RR-60 "ETOX Flash Memory Reliability Data Summary" for typical cycling data and failure rate calculations.
6. Maximum erase specification is determined by algorithmic limit and accounts for cumulative. effect of erasure at
T = -40°C, 1,000 cycles, Vpp = 11.4V, Vee = 4.5V.

"'S

8-133

A28F256A

99.9

//
99

a:.

, ,

i'"

_/.~"

/,
,/,/
,' .."

;I ""

..,, "

V "

/,
,

/
V
,
,

10
5

0.1
0.5 0.630.750.881.01.11.3

2.5

3.8

5.0

Chip Program limo (_)
- - - 12V; 10 kc; 23"1:

••••••• 11.4V; 10 kc; 7O"C
- - - - 12V; .100 kc; 23"1:

290168-14

Figure 8. 28F256A Typical Programming Capability
See Note 1, Page 8-133

1.9

1.8

1.1

,/
1.5

.1
I

........ -' . '

•is'

1.0

,/
-.
0.75
0.8

«l

eo.

J
./

,-/

CI5
. O'

100 110 120 13D'

1IIIP (CC)
_ l k C '....
••••• 10k

C'C'"

~IOOkC1c""

290168-15

Figure 9; 28F256A Typical Program Tim, at Vp; = 12.0V
8-134

A28F256A

99.9

V ,, .,V

95
90
80

60
50

'
,~.,

V
I , 'i.' .
i

,,'.
,'.If'

,' .
,.

t.'

I,',.
if

,.,',

0.1
0.3

0.5

0.7

4 5 6 789 10

CHIP ERASE TIME ( ••e)

- - - 1 2 V ; 10 ke; 23CC
-··-I1.4V; 10 ke; OCC
••••••• 12V; 100 ke; 23CC

290168-16

Figure 10. 28F256ATypicai Erase Capability
See Note 1, Page 8·133

1.8

1.6

'. ,

1.4

'U'1.2

!
~
...

i'.

1.0

0.8

0.6

,
"

....

" r--... r-... .
,

"'t'-.
'
" ,
.............. "
....... "

r-.. r--- ..::.:'.

0.4

0.2

40 50 .60

60 90 tOO t to t20 130 140

TEMP (CC)

-tkC,cIos
••••• tOk C,cln
---1OOk eyel..

Figure 11. 28F256A Typical Erase Time at Vpp

290168-17

= 12.0V
8·135

~
(,.)
0)

Ycc POWER-UP 8c

SET - UP PROGRAM

ST ANDBr

COMMAND

PROGRAM COMMAND
LATCH ADDRESS
a DATA

PROGRAMMING

VERIfY
COMMAND

PROGRAIII
VERI FICA TlON

STANDBY /
Vee POWER-DOWN

'"
CJI
)0

ADDRESSES

CEO (E#)

:!!

IG
C

Cil
....
!'3

OE# (G#)

"tI

~
;~

o·
::J

III

'cHQZ("')

tGLOV(tQE)

'cLOX('oL~)

WHOX('oH)
DATA (DO)

HIGH Z

'nOX("'Z)

iil
3
3

~tWHGL

tWlWH (t wp-)

S·
co

WEn' (w#)

3
III

..0'

twHWHl

"LOV("')

S.ov
Vee
OV

tVPEl

VpPH

Vpp
VpPl

ALTERNAT-IVE
WRITE TIMING

"LEH

CEO (EO)

WE# (w#)

290168-11

€:
@!

_.
Vee POWER-UP &:
STANDBY

SET - UP ERASE
COMMAND

ERASE COMMAND

ERASE VERIFY
COMMAND

ERASURE

ERASE
VERIFICATION

STANDBY /
Vee POWER-DOWN

ADDRESSES

€:
@J

CE# (E#)
"II

iFi
c

;

...
~

i
III

OE# (G#)

I•

t WHGL

t WLWH (twp )

IovWH (los)

•

WE# (W#)

tWHWH2

tWHDX (IoH)
DATA (DO)

IovWH(los)

tGLaV(~E)

~LQX(taL~)

WHDx(IoH)

HIGH Z

iill-

It:LQX(tu)
It:LQv(lcE)
S.OV
Vee
OV

VpPH

\
:J>

Vpp

N
C»

YpPL

"T1

290168-12

c.l

:J>

--.j

">::;'~-~:~,~~,,,~..c,:;:,~-

...... _ ~-Wk- B3P7FTfE -u9FRiDlIt

~-,,;..

intel®

A28F266A

Ordering Information

I[A
I~ 2181 F 12151s1 A l-li2]j
LPACKAGE
..
,

P=. 32~PIN. P-DIP
N = 32-lEAD PlCC
AUTOMOTIVE

L....,----ACCESS SPEED (ns)
150 ns
120 ns

290168-13

ADDITIONAL INFORMATION

VALID COMBINATIONS:
AP28F256A-120

AP28F256A-120

AP28F256A-150

AN28F256A-150

Order
Number
AP-316, "Using the 28F256A Flash
Memory for In-System
Reprogrammable Non-Volatile
Storage"

292046

ER-21 , "The Intel 28F256 Flash
Memory"

294004

RR-60, "ETOXTM II Flash Memory
Reliability Data Summary"

293002

AP-325, "Guide to Flash Memory
Reprogramming"

292059

REVISION HISTORY

8-138·

Number

Description

005

Changed Erase/Program Cycles to 1,000 minimum.

006

Added 120 ns Speed

Process Engineering
Reports

.'.,

intel·

ER-20
'ENGINEERING
REPORT

ETOXTMII Flash Memory
Technology

JASON ZILLER
PRODUCT ENGINEERING

September 1993

9-1

ETO~TM,UFLASt.l MEMORY

, .

TECHNOLOGY

CONTENTS

PAGE

INTRODUCTION ......................... 9·3
ETOXTM II FLASH MEMORY CELL ...... 9·3
. MEMORY ARRAY
CONSIDERATIONS . ................... 9·3
ETOXTM II FLASH MEMORY
RELIABILITY ........................... 9·3
SUMMARY . .......... ; ................... 9·4

9·2

ER-20

INTRODUCTION

MEMORY ARRAY CONSIDERATIONS

Intel's ETOXTM II (EPROM tunnel oxide) flash memory technology is derived from theCHMOS" III-E
EPROM technology. It replaces ultraviolet erasability
with a non-volatile memory cell that is electrically erasable in bulk array form. Intel flash memory combines
the EPROM programming mechanism with EEPROM
erase, producing a versatile memory device that is highly reliable and cost effective. This report describes the
fundamentals of the ETOX II flash memory cell in
comparison to the standard EPROM, and gives insight
into its operation in a system environment.

The ETOX II flash memory cells have the same array
configuration as standard EPROM, thereby matching
EPROM in density. Also, identical peripheral circuitry
for normal access achieves the same read performance
as the Intel CHMOS III-E EPROMs.

The ETOX II flash memory cell is nearly identical in
size to CHMOS III-E EPROM. This allows comparable densities. The primary difference between ETOX II
flash memory and EPROM cells is the flash memory
cell's thinner gate oxide, which permits the electrical
erase capability. (See Photo 1.)

ETOX II FLASH MEMORY CELL
Intel's ETOX II flash memory cell is composed of a
single transistor with a floating gate for charge storage,
like the traditional EPROM. (See Figure 1.) In contrast, conventional two-transistor EEPROM cells are
typically much larger. Intel produces ETOX II flash
memory devices on LOp. photolithography.
The ETOX II cell's programming mechanism is identical to the EPROM; that is, hot channel electron. injection. The device programming mode forces the cell's
control gate and drain to a high voltage while leaving
the source grounded. The high drain voltage generates
"hot" electrons that are swept across the channel.
These hot electrons collide with other atoms along the
way, creating even more free electrons. Meanwhile, the
high voltage on the control gate attracts these free electrons across the lower gate oxide into the floating gate,
where they are trapped. (See Figure 2.) Typically, this
process takes less than 10 p.s.
Flash memory's advantage over EPROM is electrical
erasure, discharging the floating gate without ultraviolet light exposure. The erase mechanism is an
EEPROM adaptation which uses "Fowler-Nordheim"!
tunneling. A high electric field across the lower gate
oxide pulls electrons off the floating gate. The erase
mode routes the same external voltage used for programming to the source of the memory cell, while the
gate is grounded and the drain is left disconnected.
(Figure 3.)

Intel flash memory's programming circuitry is also
identical to Intel's EPROM designs. Row decoders
drive the selected wordline to high voltage, while input
data combined with column decoders determine the
number of bitlines that are gated to high voltage. This
provides the same byte programmability as an
EPROM. Intel Flash Memories offer the efficient
Quick-Pulse Programming algorithm that is featured
on advanced EPROMs.
Array erase is unique to flash memory technology. Unlike conventional EEPROMs, which use a select transistor for individual byte erase control, flash memories
achieve much higher density with single transistor cells.
Therefore, the erase mode supplies high voltage to the
sources of every cell simultaneously, performing a full
array erasure. A programming operation must be performed before every erase to equalize the amount of
charge on each cell. Then Intel's. Quick-Erase algorithm intelligently erases the array down to the 'appropriate minimum threshold level required to read all
"ones" data. This procedure ensures a tight distribution
of erased cell thresholds throughout the array.

ETOX II FLASH MEMORY RELIABILITY
The reliability of Intel's CHMOS ETOX II flash memory process is equivalent to its sister EPROM technology. The ETOX II and EPROM processes share the
same data retention characteristics. Qualification data
shows that 1 Megabit flash memories produced on the
ETOX II process provide 100,000 program and erase
cycles with. no cycling failures due to oxide stress or
breakdown. This extended cycling capability is attributed to improvements in tunnel oxide processing and advantages inherent in the ETOX II cell approach.

1M. Lenzlinger, E.H. Snow, "Fowler-Nordheim Tunneling into Thermally Grown Si02," Journal of Applied Physics, Vol. 40
(1969), p. 278.
"Intel's ETOX II flash memory process has patents pending.
""CHMOS is a patented process of Intel Corporation.

9-3

intel®

ER·20

SUMMARY
ETOX II flash memory technology is the optimal combination of EPROM and EEPROM technologies. In~
tel's ETOX II flash memory process offers· extended
cycling capability with the density and manufacturability of EPROMs. From an· application standpoint,flash
memory technology provides the capability to
improve overall system quality throughout the product

development and manufacturing stages. Also,flash
memory density is ideally suited for applications requiring version u~ates of entire programs which, in turn,
suit the "flash" characteristics of erasing the entire array at once. In addition, individual byte programming
allows for data acquisition. Flash memory devices produce on the ETOX II process provide a high density,
low cost solution to many system memory storage requirements which·were previously unavailable.

Table I

EPROM

ETOX II Flash
Memory

EEPROM

1.0

1.2-1.3

3.0

Resolution
Typ. Time

Hot Electron
Injection
Byte
< 100 fJ-s

Hot Electron
Injection
Byte
< 10 fJ-s

Tunneling
Byte
5ms

Erase:
Mechanism
Resolution
Typ. Time

UV Light
Bulk Array
20 Min.

Tunneling
Bulk Array
< 1 Sec.

Tunneling
Byte
5ms

Normalized Cell Size
Programming:
Mechanism

294005-1

Figure 1. ETOX II Flash Memory Cell Layout (Top View)

294005-2

Figure 2. ETOX \I Flash Memory Cell during Programming (Side View)

9-4

ER-20

294005-3

Figure 3. ETOX II Flash Memory Cell during Erase (Side View)

PHOTO 1

294005-4

ETOX II Cell

(50,000 x Magnification)

294005-5

CHMOS III-E EPROM Cell
(SO,OOOx Magnification)

9-5

ER"28

ENGINEERING
REPORT

ETOXTM III Flash Memory

Technology

ALAN BUCHECKER
MARK NEWMAN
MEMORY COMPONENTS DIVISION

September 1993

9-6

Order Number: 294012-002

ETOXTM III Flash Memory Technology
CONTENTS

PAGE

INTRODUCTION ......................... 9-8
ETOXTM III FLASH MEMORY CELL ..... 9-8
Cell Processing ........................... 9-9
Byte Write ................................ 9-9
Block Erase ............................. 9·10
ETOX III PROCESS
CHARACTERISTICS ................. 9·10
Write/Erase Performance with Voltage
and Temperature ...................... 9·10
Write/Erase Cycling ..................... 9·11
Process Variation ....................... 9·12
Electrical Testing ........................ 9·12

CONTENTS

PAGE

ETOX III MEMORY ARRAY
CONSIDERATIONS ..................
28F008SA Array Architecture ............
28F008SA Byte-Write Operation .........
28F008SA Block-Erase Operation .......
28F008SA Cell Voltage Threshold .......
FLASH VS. OTHER SEMICONDUCTOR
MEMORY TECHNOLOGIES ..........
SRAM and DRAM .......................
EPROM .................................
EEPROM ...............................
NAND ...................................

9·12

9·12
9·12
9·12
9-12
9·13
9·15
9-16
9·16
9·17

SUMMARY ............................. 9·17
OTHER REFERENCES ................. 9-17
APPENDIX A ........................... 9·18

9·7

ER·28
INTRODUCTION
Intel's ETOXTMIII (EPROM tunnel oxide) flash
memory technology builds on previous flash and
EPROM processes spanning over two decades of manufacturing. experience. This third-generation process
produces devices, based on 0.8 ""m photolithography.
Intel's Flash Memories combine EPROM programming with EEPROM-like in-system electrical erasure.
This functionality, experience and technology yield a
versatile non-volatile memory that is highly reliable and
cost effective.
ETOX III cell integrity enables applications requiring
100,000 write/erase cycles. New designs incorporate array blocking schemes and on-chip automation of write
and erase to simplify customer designs and software
interface. These features combine with existing Intel
Flash Memory technology to produce a device that can
be termed a block-alterable non-volatile RAM. Access
time (tACe) and die size decrease via this smaller photolithography, making new Intel Flash Memories competitive with DRAM in read speed and cost.

The Intel 28FOO8SA. 8-Mbit flash memory is the first
ETOX III product offering. This report references the
28FOO8SA to explain device-level concepts, and ends by
highlighting important flash memory application
trends.

ETOX '" FLASH MEMORY CELL
ETOX III is a 0.8 ""m double-polysilicon N-well and
P-well CMOS process. This lithographic advance i1l1proves memory cell/array compaction more than twofold over its predecessor, the 1.0 ""m ETOX II process.
ETOX III-aided compaction allows for a 4x product
density growth given current packaging constraints.
Second-generation device architecture (see Appendix
A) and 0.8 ""m geometries increase byte-write and read
access performance by 2x over ETOX II products.
Double-metal technology enhances these improvements
by aiding die size compaction, and wordline strapping.
EPI wafer processing, which reduces latch-up, also factors into this performance boost by shrinking transistor
layout.

This report describes the fundamentals of Intel's ETOX
III flash memory cell. It provides insight into device
reliability and performance enhancements based on
ETOX III advances, and compares other semiconductor memory technologies.

9-8

ER-28

Cell Processing
Intel's single-transistor Flash Memory cell stores
charge on a floating polysilicon gate. Dimensions of 2.5
JJ.m by 2.9 JJ.m make an ETOX III cell measuring 7.25
JJ.m2. Cell layout locates the polysilicon control gate
above the floating gate (Figure I). Tungsten silicide, deposited on the control gate, reduces wordline resistance. Two .dielectrics isolate metal-I from the control
gate.

Inter-poly dielectrics of oxide and nitride isolate the
floating gate from the control gate. A very thin tunnel
oxide ( - lOOt\.) separates the floating gate from its silicon interface. Both the floating and control gates have
additional isolation between them and their respective
source/drain regions. A deeper source diffusion prevents breakdown during erase operations. In the array
metal-2 straps the wordline to enhance access times. ;\s
with ETOX I and ETOX II, metal-I carries bitline data
to the sense amps and routes voltages to cell sources.

294012-18

Figure 1. ETOX III Flash Memory Cell (Side View)

Byte Write
Writing data to an addressed byte transitions selected
cells from the "I" (erased or no charge) state to the "0"
(charged) state. This involves a programming mechanism called channel hot-electron injection. When programming (Figure 2), a cell's control gate (wordline)
connects to the external programming supply voltage
(Vpp at 12V). The drain (bitline) sees an intermediate
level (- Vpp/2), while the source is at ground. Vpp on
the control gate capacitively couples to the floating gate
through the intervening dielectric. This coupling raises
the floating gate to a programming voltage, inverting
the channel underneath.

The channel electrons now have a higher drift velocity,
with resulting increased kinetic energy. Collisions between these electrons and 'substrate atoms heat the silicon lattice. At the programming bias voltage, the electrons cannot transfer their kinetic energy to the atoms
fast enough to maintain a thermal balance. They become "hotter," and many scatter toward the tunnel oxide. These electrons overcome the 3.leV (electron voltage) tunnel oxide barrier and accumulate onto the floating gate.

9-9

ER·28

While biased in this fashion, electrons tunnel off the
floating gate. They pass through the thin oxide to the
source, lowering that cell's Vt . During a read operation,
the resulting "I" at the output corresponds to an "on"
cell discharging its bitline through the grounded source.

=Vpp
I

~==CO=N=TR=OL:;;;G=AT:;;E;:::;~I

Erase automation sets the internal Vpp pulse to 10 ms,
The WSM provides sufficient 10 ms pulses, and automatically verifies all memory cells in a given block.
This optimized pulse width enhances block-erase time
and cycling endurance.
294012-2

Figure ~. ETOX '" Flash Memory Cell
during Programming (Side View)
The electrons stored on the' floating gate raise the turnon voltage threshold (VV of that cell. During device
read operations this transistor remains in the off state.
A "0" results at the output because the "off" cell does
not pass current, causing the bitline to electrically stay
at/pull-up to the Vcc read voltage.
The internal programqtlng pulse on ETOX III is 4 p.s
(excluding WSM overhead), reduced· from 10 p.s on
ETOX II devices. This optimi2ed pulse width yields
faster byte-write times and greater cycling reliability.
Like previous ETOX· products, the automated WSM
allows for the occasional byte requiring ~ore than one
pulse.

Block Erase
During erasure, electrons are pulled off selected memory cells simultaneously. The erase process ("FowlerNordheim" tunneling) starts by routing Vpp to the
source, ground to. the select gate, and floats the drain
(Figure 3).

294012-3

ETOX III PROCESS
CHARACTERISTICS
Intel leverages over two decades of EPROM/flash
technology and manufacturing. eXPerience to produce
reliable memory products. Refined processing techniques inherent to new Intel memory technologies and
continuous improvements in process control ensure
tunnel oxide quality. A scaled substrate EPI thickness
reduces product latch-up. Double-metal technology requires improved planarization processing, which in
turn enhances moisture performance. Additionally, decreases in defect density show lasting cell integrity in
cycling and data retention..
'

Write/Erase Performance with Voltage
and Temperature
Voltage affects byte-write and block-erase performance.
Maximum Vpp improves byte-write and block-erase
times. Figure 4 shows little difference in block-write
time versus Vpp, but visible .differences in block-erase
performance. A secondary and negligible effect results
from the operating supply voltage (V Ce). Byte-write
and block-erase times are guaranteed to specification
across minimum and maximum voltage levels.
Temperature also affects byte-write and block-erase
performance. Low temperatures cause block-erase
times to increase and byte-write times to improve (Figure 4). When cold, the breakdown voltage at the source
lowers, clamping the external voltage applied for block
erase. This nets a lower potential between the source
and gate, slowing the tunneling process. Increased erase
time results from the WSM providing extra pulses. Although electron mobility decreases at hotter temperatures, typical cells still require only one programming
pulse.

Figure 3. ETOX '" Flash Memory
Cell during Erase (Side View)

9-10

ER-28

From a performance perspective, an intrinsic mechanism occurs in long-term cycling that cause byte-write
and block-erase times to increase (Figure 5), but still
conform to specification. Specifically, hot electrons
from programming trap in the tunnel oxide near the
drain junction. This creates a negatively-charged barrier, slowing hot-electron injection. Similarly, erase times
increase due to charge trapping near the source junction, making tunneling less efficient. The robustness of
ETOX III minimizes these effects. Write and erase
times remain consistent over the first 10,000 cycles, and
typically double as the device nears 100,000 cycles.

Write/Erase Cycling
Intel designs extendeci' cycling capability into its ETOX
III products. For example, the 28F008SA is designed
for 100,000 write/erase cycles on each of its sixteen
64-Kbyte blocks. Low electric fields, advanced
low-defect oxides, and minimal oxide area per cell combine to greatly reduce oxide stress and the probability
of failure.

2.3
2.2

2.1

I
M

2.0

1.8

ERASE TIME, Vpp = 11.4 Volts

1.9
1.7

I
N

1.6
ERASE TIME, Vpp = 12.0 Volts

1.5
1.4

S
E
C
0

1.3

N
D
S

0.9
0.8

ERASE TIME, Vpp = 12.6 Volts

1.2
1.1
1.0

WRITE TIME, Vpp = 11.4 Volts
WRITE TIME, Vpp = 12.0 Volts
WRITE TIME, Vpp = 12.6 Volts

0.7
0.6
0.5
0

TEMPERATURE (CELCIUS)

294012-4

Figure 4. 28F008SA Block Write and Erase Times vs Temperature and Vpp

5.0

T
I
M
E

4.0

3.0

N
S
E
C
0
N

2.0

ooc Block Erase
70 0 e Block Erase

1.0

70 0 e Block Write

D
S

OOC Block Write

100

1,000

5,000

10,000

CYCLES

100,000

294012-5

Figure . Write and Erase Times vs Cycling

9-11

Process Variation

28F008SA Array Architecture

Intel's process control of ETOX III critical cell dimensions keep write and erase electrical characteristics on
target. with little variance. This capability produces devices with consistent byte-writelblock-erasetimes making product performance predictable.

Figure 6 illustrates the 28FOO8SA. Sixteell equal
64-Kbyte blocks make up this8,388,608-bit memory
array. Each block coI1sists of 512 columns by 1024
rows. Columns in each block are further subdivided
into eight input/outputs, each pontaining 64 columns.
Typical block-erase and block-write times for this device are 1.6 and 0.6 seconds. Typical byte-write time,
including WSM overhead, is 9 /Ls.

Over the processes lifetime, internal cell dimensions
may exhibit some small variance. The primary process
variable affecting erase is tunnel oxide thickness. Channell length (Leff) has. the largest impact on programming. Outgoing product testing ensures performance to
specification regardless of these minor variances.

28F008SA Byte-Write Operation
During byte write, column address decoding determines which eight bitlines of a target block connect to
the intermediate programming voltage (- Vpp/2).
Row decoding determines wordline drive to Vpp. For
example, writing a byte of data in block 0 sets that one
wordline to Vpp. Address selection sets all other wordlines in the array to ground. Array decoding/layout
and cell durability assure device performance and reliability, and long-term data retention.

Electrical Testing
Electrical testing provides added value to Intel Flash
Memory products. This elaborate testing gives insight
to device characteristics and ensures product longevity.
Moreover, flash reliability qualifications assure product
performance and long-term durability.

28F008SA Block-Erase Operation

Electrical erase at wafer and package test allow high
confidence of detecting oxide. defects. This. electrical
testing also ensures that outgoing products perform to
specified temperature extremes. Optimization of
ETOX III process and designs, developed from previous ETOX generations and continuous data collection,
yield a very manufacturable and cost-effective technology.

Erasing a block involves simultaneous erasure of all bits
in that block. For example, erasing block 0 sets all
block 0 sources to Vpp and all block 0 wordlines to
ground. Address decoding drives all other wordlines,
bitlines and sources in the array to ground. This eliminates the possibility of corruption to data stored in nonselected blocks.

28F008SA Cell Voltage Threshold

ETOX III FLASH MEMORY
ARRAY CONSIDERATIONS

Efficient blocking layout and optimized decoding result
in smaller die size. Blocking tightens program and erase
VtS by dividing process variation into smaller regions.
The internal WSM algorithms and their associated program/erase and verify Circuits also keep Vt variations
to a minimum. This design for manufacturing approach
increases product stability.

Intel Flash Memory architecture has evolved from bulk
arrays (full-chip electrical erase), to array segmentation
referred to as blocking. Blocking divides the device
memory array into smaller sections that function as individually-erasable units.

......
c

BLOCK 0

BLOCK 1

BLOCK 2

BLOCK 3

C
I
X

BLOCK 4

Y-DECODE

BLOCK 5

BLOCK 6

BLOCK 7

Y-DECODE

BLOCK 8

BLOCK 9

BLOCK 10

BLOCK 11

BLOCK 12

BLOCK 13

BLOCK 14

BLOCK 15

294012-6

Figure 6. Intel 28F008SA Memory Array Layout

9-12

ER-28

FLASH VS. OTHER SEMICONDUCTOR
MEMORY TECHNOLOGIES
Intel's scaling advances in flash memory manufacturing
and design provide optimal cell/array compaction. In
roughly twenty years, Intel non-volatile memory densi-

ty has gone from 2,048 bits to 8,388,608 bits, a 4096x
increase. Figure 7 compares other memory types to
show relative density progression. The fast ramp in
ETOX flash memory density results from its similarity
to EPROM.

64M

32M

16M

4M
(

!=
Vl

512K

Z
.....
0

256K

0:::

::::!E
.....

128K

::::!E

32K

16K

1970

1974

1978

1982

1986

1990

1994

1998

PRODUCTION YEAR
294012-7

Figure 7. Memory Evolution

ER·28
Figure 8 illustrates the relationship between cell sizes of
different memory. types and minimum geometries. As
dimensions scale, certain memory types become cellsize .
limited (i.e. some components cannot shrink pro-

portionaIly). The memory cost per bit learning curve
shows flash in a strong position. This curve, shown in
Figure 9, reflects how Intel's experience reduces cost
for incr.eased memory density.

1000
500

.......

.3
.....

200
100

iii
..:J

-'
.....
(.)

50
20

Q::

0
:::Ii

.....

:::Ii

2.0

'1.6

1.2

1.0

MINIMUM FEATURE SIZE (}.I)

294012-8

Figure 8. Memory Cell Size Trends

-------- .... ....

.... ....

---- ..................
-.:::-,.

i ii
~
II>

.... ......

...... ......
EEPROM

........

411'.:: ___ _

---- ----- ... ....

......

(.)
....

....

_--- -----EPRO~

1988

1989

1990

1991

1992

1993

1994

294012-9

Figure 9. Memory Cost/Bit Learning Curves

9-14

intel~

ER·28

Since the late 1980s, a new memory sub-system has
arrived on the market, offering an alternative to highdensity. file system media. Inters Series 2 Flash Memory Cards take advantage of the 28FOO8SA and its' second-generation architecture to provide card densities of

up to 20 Mbytes and new functionality. This relatively
new technology offers a solid-state file system (Figure
10) that will double in density with new ETOX generations.

'.,:s.

3'"

128

320

160

·in

.,IIIQ.
E

(")

I,ll

640

256

::::E

.."

~
c

I.,
:'!

~
CD

COl

c
c

'91

'92

'93

'94

'95

'96

'97

'98

'99

III

1
~

294012-10

2000

Figure 10. ETOX Component and Memory Card Density Over Time
currents and read operations. Charge storage requirements limit size reduction of the capacitor, which in
tum limits memory array compaction. With smaller
geometries, DRAM cell structures are more complex, ,
requiring more process manufacturing steps.

294012-11

Figure 11. Six-Transistor SRAM Cell Schematic

SRAM and DRAM
SRAM and DRAM have fast read/write speeds. Both
are volatile memories requiring continuous power to
retain data. Standard SRAMs (Figure 11) require four
to six transistors for each flip-flop cell. This greatly
reduces memory capacity per unit area, raising product
cost for a given density.
DRAM requires constant refresh of the capacitor-like
storage mechanism (Figures 12 and 13) due to leakage

294012-12

Figure 12. Stacked DRAM Cell (Side View)

c:::J

~r- - - ', - - )_S[s---,'
294012-13

Figure 13. Trenched DRAM Cell (Side View)

9-15

'intel®

Eft-28

Most DRAMs require a read parity bit for two reasons.
First, alpha particle strikes can disturb cells by ionizing
radiation, resulting in lost data. Second, when rtiading
DRAM, the cell's storage mechanism capacitively
shares its charge with the bitline through a select transistor. This creates a small voltage differential to be
sensed during read access. This low voltl\ge differential
can also be influenced by nearby bitline. voltages and
\
device noise.
ETOX III floating-gate technology electrically isolates
the substrate from the charge storage mechanism. Unlike DRAM, floating-gate charge determines cell VtS,
which in tum controls bitline voltages. This allows
flash memory read sensing to easily detect cell VtS. A
current swing of 70 /lA, from strong cell VtS, make
bitline voltage transitions a· key factor to fast read
speeds.
Most DRAMs require high active power consumption.
Charge storage requirements and read signal strength
constrain DRAM cell compaction. Low-power ETOX
III flash memory has a simple single-transistor cell with
only minor scaling limitations through the year 2000.
This results ina mainstream memory that does not
.
need power to retain data.

Intel's ETOX'· III technology. employs double-metal
processing to strap wordlines in metal for improved
read performance. This advance is not likely to appear'
on EPROM because it would· block even more UV
light. Since flash memory electrically erases, it eliminates these concerns. Moreover, flash electrical erasure
eliminates the UV window and its associated cost, and
allows for the· most advanced and innovative plastic
surface-mount packaging solutions.

EEPROM
Conventional two-transistor EEPROM cells (Figures
15 and 16) limit layout density. This is primarily due to
the second tran$istor (bit select) and associated decoding.required for single byte program and erase capability. Technology design requirements make EEPROM
cells, like triple poly, significantly larger than flash.
Typical EEPROM technologies are more complex,
making wafer manufacturing difficult and expensive.

EPROM
Intel's EPROM and Flash Memory cells share a common stacked-gate profile (Figure 14), with two basic
differences relating to their respective erase mechanisms. EPROM requires ultraviolet light to erase; flash
erases electrically. For this reason, flash has a thinner
cell oxide to allow Fowler-Nordheim tunneling, and a
deeper source junction to prevent breakdown during
erase.

(~-)

)

C"'----'-....J",(

)

294012-14

Figure 14. EPROM Cell (Side View)
EPROM technologies that migrate toward smaller geometries make floating-gate discharge (erase) via UV exposure increasingly difficult. One problem is that the
width of metal bitlines cannot reduce proportionally
with advancing process technologies. EPROM metal
width requirements limit bitline spacing, thus reducing
the amount of high-energy photons that reach charged
cells. EPROM products built on submicron technologies will face longer UV exposure times.
9-.16

1 - - )- )

(

294012-15

Figure 15. Flotox EEPROM Cell (Side View)

294012-16

Figure 16. Triple Poly EEPROM Cell (Side View)
_Because of their traditional al'plication, EEPROMs use
a very high internal voltage (17V to 30Y) to· achieve fast
program and erase times. These high voltages and resulting electric fields cause cell oxides to breakdown,
shortening cycling life and degrading cell· thresholds.
Additionally, this high voltage stresses periphery transistors. Intel's Flash Memories are more akin to
EPROM; both use a significantly lower voltage around
12V.

ER-28

NAND
Futuristic types of EEPROM (Figure 17) that have
shifted from highly-manufacturable NOR-gate architectures, appear to provide ETOX-likedensity on a per
cell basis and potential use in similar applications. A
closer examination reveals internal positive and negative charge pumping. When applied across a memory
cell, the dual charge pumps net a high voltage that
cause oxide stress. These stacked-gate cells program
and erase via tunneling. They program from the substrate to the floating gate, and erase in the reverse bias.
. Bit Line

Select Gate 1 ---H--~;_---

Control Gate 8 - -.....I#--~;.....---

CG7--~~--~------

CG 6

however the first read always remains slow. Fast write
times require a page buffer for full wordline programming. Several wordlines erase at once, setting the block
size. Product scaling becomes limited from high-voltage
requirements on periphery transistors and isolation
technology. Compared to EEPROM, the NAND approach improves array compaction at the expense of
more complex decoding and periphery circuitry.

SUMMARY
Intel's technology advances result in products that are
more efficient, more reliable, less expensive and higher
performance. Submicron geometries and double-metal
technology allow considerable memory array compaction, providing increased read. and byte-write performance. Design compaction also improves with EPI wafers that reduce latch-up, allowing closer transistor layout. Strong cycling endurance results from the quality
of the thin low-defect tunnel oxide, and the electrical
characteristics of internal program and erase operations. Cycling, voltage and temperature exhibit only a
small influence on byte-write and block-erase speeds.
Products built on Intel's CMOS ETOX III flash memory technology require minimal power consumption during writes, erasure, read, and low-power sleep or standby modes.

--~I#--~;.....---

CG5----~~----~-------

CG4----Ht---~;_----

CG3---~~----~-----

CG2----I#----~;.....-----

Intel Flash Memory products designed on ETOX III
will satisfy many different applications. The Thin SmallOutline Package (TSOP) provides customers with high
memory density in the smallest footprint. Some applications for ETOX III flash products include memory
cards, solid-state drives, non-volatile operating systems,
high-performance system storage, data acquisition, and
application and embedded code storage. The solid-state
nature of flash results in improved ruggedness over mechanical rotating media. With blocking, applications
can perform background erase to optimize system performance. Today, Intel's technological advances in
flash memory are driving cost to parity with DRAM.
This steep decline in the price learning curve enables
new classes of systems and system architectures.

CG1----~~----~-------

OTHER REFERENCES
Select Gate 2

-----H---~;_----

294012-17

Related documents of interest to readers of this engineering report:
28FOO8SA Data Sheet (Order No. 290429)

Figure 17. Eight Cell NAND Configuration

Series 2 Memory Card Data Sheet (Order No. 290434)

Layout of the NAND array groups eight cells as a set,
each set requires two select transistors to control bitline
access. Due to this NAND configuration, the read path
goes through other cells making access slow. Increased
read speed requires an internal SRAM page buffer,

ER-27: The Intel 28FOO8SA Flash Memory (Order No.
2940!1)

9-17

intel®

ER·28

APPENDIX A
Fir~t-generation flash devices, like the 28F020, use externally-controlled algorithms for byte write and bulk
erase. These algorithms require that customer software
control:
• Sell pulse widths, and pulse repetition where required.
• Erase preconditioning (i.e. pre-programming all
cells before erase).
• Timeout delays to allow cell voltages to transition
from program or erase levels to read verify levels.
• Read compare operations to determine success.

Second-generation architectures, like that on the
28FOO8SA, contain an internal Write State Machine
(WSM) to simplify software development. This WSM
provides internal control of all of these first-generation

~-18

requirements, as well as reporting on activity progress/
success through the internal Status Register. A dedicatedoutput on the 28FOO8SA allows immediate hardware signaling of WSM activity status. The Command
User Interface (CUI) provides customer control.
The other major architectural feature of second-generation devices is array segmentation, also referred to as
"blocking". First-generation products erase in bulk.
This means that all cells in the array erase simultaneously. Second-generation "sectored" architectures divide the array into separately-erasable block segments.
This provides logical segmentation· of customer code,
and allows reads of other device blocks while one is
erasing (i.e. via the erase-suspend/resume commands).

ER-33
ENGINEERING REPORT

ETOXTMIV
Flash Memory Technology:
Insight to Intel's
Fourth Generation

Process Innovation

ALAN K. BUCHECKER
ALEXANDER C. MITCHELL, III
MEMORY COMPONENTS DIVISION
INTEL CORPORATION

September 1993

Order Number: 294016-001

I
9-19

, ETOXTMIV Flash Memory Technology: Insight to Intel's
Fourth Generation Process Innovation
CONTENTS

PAGE

INTRODUCTION . ....................... 9-21
ETOXTMIV FLASH MEMORY CELL ....
Cell Processing .........................
Data Write ............. , ................
Erase : .......................... , .......

9-21
9-22
9-23

PAGE

FLASH VS. OTHER SEMICONDUCTOR
MEMORY TECHNOLOGIES .......... 9-44
SRAM and DRAM ....................... 9-47
EPROM ................................. 9-48
EEPROM ............................... 9-49

9-28

ETOX IV PROCESS
CHARACTERISTICS ................. 9-31
Write/Erase Performance with Voltage
and Temperature ...................... 9-31
Write/Erase Cycling ..................... 9-33
Process Variation ....... ; .............. ; 9-36
Electrical Testing ...... ; ................. 9-38
ETOX IV PROCESS-RELATED
IMPROVEMENTS ..................... 9-39
History and Evolution .................... 9-39
Cell/ Array Compaction .................. 9-41
Enhanced Contact Technology .. , ....... 9-41
Improved Cell/ Array Uniformity' .....' ..... 9-42
Write/Erase Performance ............... 9-42
Cycling Performance .................... 9-42
Read Access ............................ 9-43

9-20

CONTENTS

PROCESS/DESIGN TRADEOFFS TO
ACHIEVE THE PERFECT FLASH
MEMORY ............................. 9-49
NOR Flash .............................. 9-50
ETOX Flash ............................. 9-50
Negative Gate-Bias Erase (NGE) ........ 9-51
NAND Flash ............................. 9-52
Triple-Poly Flash ........................ 9-53
SUMMARY ............................. 9-55
OTHER REFERENCES ................. 9-55

ER-33

INTRODUCTION
Intel's ETOXTM IV (EPROM with Tunnel Oxide)
NOR-based Flash Memory technology builds on
three previous generations of ETOX process
learning, while also leveraging decades of stackedgate memory cell manufacturing experience dating
back to the development of the first EPROM in
1971. This fourth-generation ETOX process yields
devices based on 0.6-llm minimum-design-rule
geometries.
Intel's ETOX Flash Memories combine state-of-theart EPROM programming methodology with
EEPROM-like
in-system
electrical
erasure.
Sectoring of the large memory array into smaller
independent-erase blocks, coupled with on-chip
automation of their write and erase algorithms,
enables a flash product that can be termed a B1ockAlterable Non-volatile Random-Access Memory
(BANRAM). This functionality, combined with
Intel's accumulated years of manufacturing
experience, electrical-test and temperature-stress
data collection, and advanced design/architectural
technology
innovation,
yields
a
very
manufacturable and versatile non-volatile memory
that is highly reliable, extremely stable and cost
effeetive.

This report describes the fundamentals of Intel's
ETOX IV Flash Memory cell. It provides insight to
device operating characteristics and reliability with
ETOX
IV -related
performance
focus
on
enhancements, and compares other semiconductor
and flash memory technologies. The 28F016SA
16-Mbit FlashFile™ Memory is Intel's second
ETOX IV product offering. This report references
the 28F016SA to explain device-level concepts and
ends by highlighting important flash memory
application trends.
More information on the 28F016SA can be found in
the following documents:
:.~

-28FOI6SA Data Sheet
-28F032SA Data Sheet
-28FOI6SA User's Manual
-ER-31: the Intel 28FOl6SA FlashFile MemoryArchitecture and Characterization Summary
(Available QI'94)
-AP-375: Upgrade Considerations from the
28F008SA to the 28FO l6SA
-AP-377: the 28F016SA Software Drivers
-AP-378: System Optimization using the Enhanced
Features of the 28F016SA

ETOX IV FLASH MEMORY CELL
Intel considered all aspects of product technology
and usage, and balanced the associated tradeoffs of
cell size, array architecture and system design to
generate a very robust and well-rounded flash
memory approach. ETOX IV cell integrity produces
devices with 100,000-cycle minimum write/erase
endurance per block (1,000,000 cycles are
obtainable with proper software control techn,iques).
Write/erase times and die size decrease via ETOX
IV's finer photolithography, allowing Intel Flash
Memories to gain on DRAM in-system performance
and cost-per-megabyte advances. Manufacture on 8"
wafer technology significantly increases the number
of die per wafer vs. 6" fabrication. This capacity
demands investment in new capital equipment, but
in the end bears yet another path to reduce product
cost.

ETOX IV is a 0.6 Ilm, double-metal, doubleP-well
CMOS
polysilicon,
N-well
and
manufacturing process. Its lithographic advance
improves memory cell and array compaction more
than" two-fold over its predecessor, the 0.8 ]Jm
ETOX III process.
Such a significant level of compaction greatly
lessens the economic impact associated to
incorporate
additional
logic.
Consequently,
advanced circuits can be cost-effectively
implemented to provide the system designer with
enhanced product flexibility and operating
characteristics, and new modes of user functionality.
Additionally, ETOX IV compaction allows for a 4x
density growth path given current packaging
constraints (i.e., the leadframe of the l4-mm-long x

9-21

ER-33
20-mm-wide x 1.0-mm-thick 56-ld Thin SmallOutline Package).
Data-Write performance dramatically· improves via
0.6-J.lm geometric scaling advances. Raw cell
programming time decreases to 2.5 J.lS, nearly
halving the 4 J.ls pulsewidth of ETOX III products,
and a 4x reduction from 10 J.ls on 1.0-J.lm ETOX II
products.
Erase performance also improves. 28F016SA Block
Erase (64-KB block size) is typically 800 ms. This
duration is 50% faster than the ETOX III
28F008SA, with identical block size. From the
process perspective, erase timing gains come from
the aforementioned boost to cell programming
performance (during Block-Erase pre-conditioning)
and a higher degree of cell and array uniformity.
Streamlining and enhancement of the internal state
machine's algorithm and support circuitry contribute
design improvements that speed up erase.

Cell Processing
Intel's single-transistor 0.6-J.lm ETOX IV Flash
Memory cell, with dimensions of 1.8 J.lm x 2.0 J.lm,
measures a mere 3.6 J.lm2. Figure 1 shows a
photomicrograph cross section of this cell.
A floating polysilicon gate (poly-I) provides the
charge storage mechanism used on both ETOX flash
and EPROM technologies. This component is
depicted at the center of the photomicrograph.
Intel's ultra-pure thin-oxide formation technology
produces a low-defect tunnel oxide (-lOOA) which
separates the floating gate from its silicon.interface.
Cell construction locates a poly-2 control gate
directly above the floating gate. Inter-poly
dielectrics isolate the floating gate from the control
gate. Both the floating and control gates have
additional isolation between them and their
respective source/drain regions (side or spacer
oxide). Tungsten silicide, deposited on the control
gate, reduces wordline resistance. A dielectric layer
isolates metal-l from the control gate.

Figure 1. Photomicrograph qf ETOX IV Flash Memory Cell (Side View)

9-22

ER-33
A graded source diffusion improves erase
efficiency. This grading is achieved via a
phosphorous implant incorporated into the source
junction. The deeper implant also improves
reliability by preventing source/oxide junction
breakdown during erase.
As with ETOX I, II and III, metal-I carries bitline
data to the sense amplifiers and routes voltages to
cell sources. Throughout the array, metal-2, which
was first used on ETOX III, straps the wordline to
reduce its resistance. This technique enhances
device read (tACC) performance and the routing of
signals and voltages during program and erase
operations.
Double-metal technology also aids ~ACC
improvements via its role in compacting the array.
EPI wafer processing, which practically eliminates
latch-up, also helps read.access timings by allowing
tighter transistor layout.'

In addition to smaller geometries, ETOX IV offers
several other major advancements to this process
generation via new manufacturing and contacting
capabilities. These advancements tighten cell
dimensions and improve step coverage.
New processing steps maintain very strict
manufacturing adherence to tight cell dimensional
tolerances.
Cumulatively,
these
individual
adherences translate into a more uniform array.
Tighter dimensioning at the cell level enhances
individual
source-to-tloating-gate
coupling
consistency, and therefore erase efficiency. Spread

across the full array, this provides greater control of
erase-threshold distribution.
New technologies and materials improve mask layer
interconnecting through the narrower contact holes
of ETOX IV geometries. This enhanced step
coverage reduces fallout at wafer electrical test.
Tighter cell dimensions, improved array uniformity,
and superior step coverage in both the array and
periphery also contribute toward a higher degree of
cell/array compaction and a more planar silicon
formation. In combination with erase-threshold
control improvements and reduced electrical test
fallout, the, following device characteristics
improve:
.Yields (and thus cBst)
-Erase Performance
-Moisture Performance
-Reliability
-Durability
-Stability

Data Write
Writing data to an addressed memory location
transitions selected cells from the "1" (erased or no
charge) state to the "0" (charged) state. This
involves the EPROM programming mechanism of
Channel Hot-Electron (CHE) injection. When
programming (Figure 2), a cell's control gate links
to the external Vpp supply voltage via wordline
connection and row decoding. The drain sees an
intermediate level of -Vppl2 via bitline connection
and column decoding; the source is at ground.

9-23

In ,'"
•

tel'"
" ,,~'

CONTROL GATE

n + DRAIN

DEPLETION
REGION

293002-1

Figure 2. ETOX IV Flash Memory Cell during Programming (Side View). CHE Injection produces
electron migration across the tunm;ll-oxide barrier; the electrons store on the isolated floating
'
gate, raising this cell's tum-on threshold.

Vpp on the control gate (VCG= 12V)capacitively
couples to the floating gate through the intervening
dielectric. This coupling raises the floating gate to a
programming bias voltage, which in turn inverts the
p-type channel underneath. After channel itlversion
(now taking on characteristics of n-type material),
the aforementioned intermediate-level voltage is
appljed to the drain. This drain voltage attracts
electrons, the majority charge carrier in n-type
material, from the source.
As the drain voltage ramps, channel electrons gain a
higher drift velocity with resulting increased kinetic
energy. Collisions between them and substrate
atoms energize the silicon lattice. At that point,
these channel electrons cannot transfer their kinetic
energy to the atoms fast enough to maintain a
thermal balance. They become "hotter" and many

9-24

scatter toward the tunnel oxide. At some point they
overcome the 3.1eV (electron Voltage) tunnel-oxide
barrier and accumulate onto the floating gate.
Electron storage on the floating gate creates a
negative potential opposing voltage (e.g., read or
margin-verify bias)applied to the control gate. This
opposition results in' a higher turn-on threshold
voltage (Vt' Figure 3) for that transistor (memory
cell). An unprograrmned cell has a turn-on Vt Vtp. This,
threshold is guaranteed by an internally-conducted
margin-bias read producing a <:urrent (lPMrgn) that
is sensed against a program reference circuit
providing a current relationship to Vtp (lPRef)' See
Figures 4 and 5 for detail of the program reference
circuit and current.

ER-33

VOLTAGE

VtpMIN

Vt.MAX

#OFCELLS
Figure 3. ETOX IV Program and Erase Thresholds. The upper plot shows Vt distribution for "0"
cells (programmed), the lower plot displays for "1" cells (erased).

9-25

.ER·33

Address
Queue
Latcbes

"","~, ~

P",om
Circuits

... l!

OQ0-7
to output Buffer
through Output MuHiplexer

OQ0-718-1S

Status
Registers

Data-in
Buffer

~~'-.-----

.----~~7---,-,======l====+===:;___!-_n1 r-"
Column Decoding
u-~
1.i
a; Gi
~

}-2!

V.'1fl;ji (
.~

"'0
OJ

Just- J'
Programmed
Cells

~~.~~

IPMrgn < IPRe! I

':.

0Hf:1 ~
i

0 tp t u u -

T
,DO.,

W'M

-- ~
I

~ CUI ~

I/O

Logic

L_~-'-I~--"

VL--~--'-I
Data
lJt-L ... ~,.om, IV- L-~_R~_~_i~_~e_~_s~_--"rr~

L-

,Memory Array

Page
Buffers

Figure 4. 28F016SA Program Verify Scheme. Cell current IPMrgn' derived by a program margm
bias, is sensed against current IPRef (from Program Reference Circuit). The sensed outputs are
then compared to the original data written and stored in a Data Queue Register.
los

Figure 5. ETOX IV Program, Erase and Read Reference Currents. The reference circuitry, shown in
Figures 4, 6, 8 and 9, provides these currents for sensing against cell program and erase
verification currents, and read currents during memory access.

9-26

intet

ER-33

During read operations (Figure 6) Vee (or a
boosted voltage for 3.3V operation) is placed on the
control gate, the source is grounded and a drain bias
is applied. In this mode, a programmed cell
conducts little to no current. The bitline (column)

current for this cell is sensed agBinst the current
produced by a read reference circuit. If the current
in the read reference circuit is greater than that
through the programmed cell, a ·0· results at the
output of the sense amplifier.

+VD

,vcc

Read Reference Circuits

WSM

Vt>Vtp-4CG~
current lrom

•••

,.18881381
s

_therce'

being reed

o
Cro•• Section 01
Cen being Reed

IPRead < IRRef
------------------------~Ompm=O

CUI

110
Logic

Figure 6. ETOX IV Flash Memory Read Scheme (Programmed Cell). The negaOve charge stored on
the poly-1 floating gate (FG) Increases this cell's tun'l-on threshold, thus with VCC applied to the
control gate (CG) Its current IPRead < IRRef (Read Reference Current).

The internal ETOX IV programming pulse is 2.S f.lSj
this optimized pulsewidth yields faster Data-Write
performance and greater cycling reliability. The
28F016SA's on-chip write/erase automation circuits,
governed by a functionBi unit called the Write State
Machine (WSM), impart an additional 3.S f.lS of
overhead to the programming operation. The
combined 6-f.l5 duration begi.ns with the laSt WEN
rising edge (WEN-controlled timings) of the
command/data bus-cycle string for a Data-Write
sequence. This 3.S-f.ls . overhead is required to
activate
WSM support circuits,
decode
programming voltages onto correct cell locations
and run through the flow of the internal algorithm.

Additionally, part of this same overhead is needed
for voltages to switch from a programming bias to
an elevated read bias in preparation for margin
sensing against a program reference current. This
margin-sense activity is followed with a comparison
to the origlnBl data written and held by an input
register (see Figure 4 of this report. and the sensing
and data comparator sections of the 28F016SA.
Block Diagram in Data Sheet or ER-31).
Cell current IpM n' which in. the case of DataWrite verification~s derived ftom an elevated read
bias on that cell, is fed, as well as program reference
current IPRef\ into a sense amplifier. The output of

9-27

ER-33
multipl~ sense
amplifiers (8 for byte-wide
operations, or 16 for word-wide ,'''operations) is
routed into a data comparator, for collation'with the
'original input' held by one of, the data-in queue
registerS. The cbrilparato~ signals the WSM with the
outcome of this data-compare operation. Like
previouS Intel Flash Memory products,', the
automated WSM allows for the occasional word or
byte requiring more than one pulse.

EEPROM-like erase mechanism called Fowler, Nordheim (F-N) tunneling. Outing erase, VppiS
routed to all source connections within a single
block via the appropriate block source switch (see
Figure 10, and its corresponding text in ER-31). All
control gates are grounded and the drains for the
block to erase are floated (see Figure 7 of this report
for individual cell configuration); all other block
drains are grounded.

When programming completes, the WSM updates
the R~ady/Busy# (RYIBY#) bit, of the device's
internal Status Registers and the dedicated RYIBY#
acknowledgement pin. Additional status bits detail
success/error information, and the probable reason
for failure, if one occurs.

While a cell is biased in this fashion, electrons
previously stored on the floating gate now attract
towards the SO\lrce. The electrons tunnel through the
thin oxide layer, producing the desired effect of
'lowering that cell's Vt' ThiS Vt is verified

Cells ;f I

'6 being Verified

~
0::

••••

.J--" I
1

sens8JJ
Amp • • • Amp
16 _ _ _ _ _ 0 }E------I

•

1/0
Logic

VGEV

Data·in
Buffer

WSM

CUI

~c__,----,_J

IEMrgn > IERef
Output = 1

Data Comparator
L -_ _ _ _ _ _

[;1-L------l

l\r

Data= FFFFH

Memory Array

Figure 8. 28F016SA Erase Verify Scheme. Cell current IEMr..gn' derived from. a erase-margin bias,
sensed against current IERef (from Erase Reference Circuit). The sensed outputs are then
compared to data FFFFH.

·9-29

int"et

ER-33

V,<

ve\.~:

L~~~~

c +VO

.-e.
'"

'"..

Jl Jl

.l!

k--

Read Reference Circuit!;!

current from
another cell
being read

II:

.!: .!:

WSM

...
~y~y

~~ono~

Amp

Cell being Read

Amp

IERead > IRRe
Output =1
Output Multiplexer

~~
Output Buffer

CUI

1/0
Logic

Figure 9. ETOX IV Flash Memory Read Scheme (Erased Cell). The absence of floating-gate (FG)
charge gives this cell a turn-on threshold similar to a MOSFET. Therefore, with.VCC applied to the
control gate (CG), its current IERead > IRRef (Read Reference Current).
Without a floating-gate-stored negative potential to
overcome, erased-cell thresholds produce a higher
current relative to the read reference circuit. During
read operations then, a "1" is seen at the output
(Figure 9).
Since NOR-type flash memories do not contain the
two-transistor storage-and-selection cell structure of
EEPROM technology, they cannot ,erase with
wordlbyte granUlarity. Instead, flash memories erase
in bulk (entire device) or via blocks (sectored
portion of array). This means that many cells have
their floating-gate charge dep,leted simultaneously.
To avoid device damage (I.e., over-erasure), the
internal flash-erase algorithm (or the external
customer-controlled algorithm on older products)
first pre-conditions the block to be erased (I.e.,
programs all cells to "0"). After successfully
completing this portion of the erase operation, the
WSM can then initiate erase pulsing.

9-30

• The ETOX IV erase pulse is 10 ms; this pulse
duration is optimized and balanced for fast BlockErase time and enduring cyclability. After each
pulse attempt, the WSM signals for margined
sensing against the erase reference current, and
compare to data value FFFFH for all word addresses
withih the associated block.
An internal address counter controls selection for
. the array data location to be sensed (see Figure 8 of
this report,' and the address counter section of .the
28F016SA Block Diagram in Data Sheet or ER-31).
This counter starts at the last word location within a
block, then. decrements its pointer through the
remaining addresses via increments of one.
The WSM halts this internal margin-sense/datacompare function when a word location does not
verify. In this instance, another 10 ms erase pulse is
applied. The location last checked is then re-tested,
and if successful, address sequencing and verifytesting recommences; if not, another erase pulse is

intel~

ER-33

applied. This testing, re-pulsing and re-testing flow
continues until all block memory words confirm
erased.
As with programming, the WSM updates Status

Register RYIBY#and dedicated hardware RYIBY#
indicators at erase completion. Additional register
bits provide success/error status, and the probable
reason for failure, if one occurs.

ETOX IV PROCESS
CHARACTERISTICS
This section expands on key device performance,
stability and reliability characteristics relative to the
process, showing influences of voltage and
temperature. The following topics are covered:
-WritelErase Performance
Temperature
-WritelErase Cycling
-Process Variation
-Electrical Testing

with

Voltage

and

Write/Erase Performance with
Voltage and Temperature
Voltage. influences Data-Write and Block-Erase
performance. Maximum Vpp bias significantly
reduces Block-Erase times, while providing, only
slight improvement to Data Write (i.e., averaged
Data-Write times over numerous operations). The
effect on erase. is more pronounced because' DataWrite operations typically require a single
programming pulse at nominal Vpp, therefore gains
from raising Vpp are not discernible on single
WordlByte Writes. Conversely, reduction in the
number of pulses r"quired for Block Erase, when
using VpPMAX' is perceptible.
VCC also influences Data-Write and Block-Erase
times. The WSM is designed using clocked logic
circuits, with a ring oscillator generating their clock
signals. The frequency of a standard ring oscillator
varies with processing, temperature and .supply

voltage.
Improved designs mmlmlze these
variations, but some level will always exist. For
Data Write, VCC's influence on the oscillator's
operating frequency imparts the primary effect to
these operations (as mentioned above, Vpp's effects
are secondary). VCC min-max variances, while in
S.OV or 3.3V mode are negligible, but the difference
between modes is observable. For Block Erase,
VCC's influence is secondary, about 112 to 113 the
impact seen by varying Vpp to minimum, nominal
and maximum levels. Despite these dependencies,
write and erase times are guaranteed to specification
across all minimum and maximum voltage comers.
TemperatUre also affects Data-Write and BlockErase times. Low temperatures cause a decline in
Block-Erase
performance,
but
Data-Write
operations improve. When cold, the breakdoWn
voltage at the source lowers, thus clamping the
internal B~ock-Erase voltage. This nets a lower
potential between source and gate, slowing the
tunneling process. The time increase results from
extra WSM pulses.
Cold temperatures enhance Data-Write performance
because electron mobility improves. Increased
mobility yields a higher rate of electron travel
toward the drain producing fewer, but stronger
collisions with substrate atoms. These CQllisions,
now more fierce, impart greater kinetic energy to
the electrons being freed. This energy gain aids their
migration across the isolation barrier of the tunneloxide .layer, resulting in greater electron
accumulation onto the floating gate per unit time.
Although 'electron mobility decreases at hotter
temperatures, typical cells still require only one
programming pulse.
Figures 10 and 11 depict the voltage and
temperature dependencies of 28FOl6SA WordWrite and Block-Erase times. For Figure 10, it is
shown that higher VCC levels and colder
temperatures improve Data-Write performance,
Figure 11 reveais maxim~m Vpp and hot.
temperature enhances Block-Erase times, as well as
high VCC bias.

9-31

ER·33

8.5

7.5

- - VCC=3.0V.VPP=12V
-0--

VCC = 3.3V.VPP = 12V

iii
.l!

-0--

VCC=3.6V.VPP=12V

-<>-- VCC=4.5V.VPP=12V

6.5

--VCC=5.0V.VPP=12V
--fr--

VCC=5:5V.VPP=12V

5.5

Temperatur. {Cel.Iu.,

Figure 10. 28F016SA Word·WriteTime vs. Temperature and Vee. Word·Write efficiency
at cold temperature and maximum Vee.

improve~

600
575
550
- - VCC .. 3.3V.VPP= 12V
525

~
~

500
475

450

r~~:::::::,~~~

~~~~--~~--~==-

y---_~

-0--

VCC=5.0V.VPP=12V

~.-

VCC=3.3V.VPP=11.4V

-<>-- VCC=5.0V.VPP= 11.4V
- - VCC=3.3V.VPP=12.6V

425
--tr-

VCC=5.0V.VPP=12.6V

400 •.
375
350+-----+-----r---~----_+----+~-_r---1_--~

TemptrBtur. {Celsius'

Figure 11. 28F016SA Block·Erase Time vs. Temperature and Vpp. Block·Erase durations.shprten
at maximum Vpp and higher temperature.
.

9·32

ER-33

Write/Erase Cycling
Cycling is a critical consideration for applications
like filing systems using flash-based memory cards.
or solid-state drives in harsh mobile or industrial
computing environments, or a notebook/pad
computer DRAM suspend storage array built with
flash memory chips on the motherboard. Other
parameters, such as read-access timings, write/erase
performance,. power consumption and data retention
follow in order of precedence, and of course, flash
solid-state ruggedness is far superior to electromechanical rotating media, hence not a concern
here.
Intel designs extended cycling capability into its
ETOX IV products. As an example, the 28F016SA
is specified for a minimum of 100,000 write/erase
cycles on each of its thirty-two 64-KB (32-KW)
blocks. Furthermore, the 28F016SA can deliver
1,000,000 Bock-Erase cycles provided wearleveling concepts and block-retirement methods are
employed.
Wear-leveling concepts, like those contained in
'Microsoft's Flash File System and the embedded
control code for Intel's Flash Drive product,
periodically cycle stable data segments to other
blocks, ensuring distributed usage.
Block
retirement. is a methodology whereby the system
logs cycling count data on all blocks; as each block
reaches 1,000,000 cycles, they are tagged for no
more erases.
To bring a 1,000,000-cycle specification into
perspective, it would take> 10,740 hours to cycle
every block on a single 28FO 16SA device 1,000,000

times, i.e., given blocks were continually erased and
rewritten as fast as these operations could be
performed. (This assumes byte-wide mode with 225
ns ,of overhead to initiate each programming
operation. No Status Register Read times are
included, and only one pulse is assumed for all
2,097,152,000,000 programming sequences. Erase
is calculated at the 800-ms typical duration for all
32,000,000 sequences.) Of course this is not
realistic usage- typical modus operandi for filestorage media is 80% reads vs. 20% writes. Also,
the average human user does not work 24 hours a
day saving data files, just to rewrite them.
Cycling-induced hard failures do not occur until an
intrinsic wearout mechanism, caused by electron
trapping, becomes so severe that the allotted
maximum number of internal WSM program or
erase pulses cannot overcome their opposing
potential. Low electric fields, advanced low-defect
oxides and minimal oxide area per cell combine to
greatly reduce oxide stress and prolong the
probability of this failure.
From a performance perspective, electron trapping
eventually pushes out write. and erase times. Within
the poundary conditions of the device, these times
still conform to specification. Explicitly, hot
electrons from programming trap in the tunnel oxide
near the drain junction. This creates a ilegativelycharged barrier slOWing CHE injection. Similarly,
electrons trap near the source junction because of
erase. Their negative potential makes F-N tunneling
less efficient. Figures 12 and 13 show the reslilt of
these degradations over long-term cycling.

9-33

~R-33
Vpp = , 2.0V. Vee = 5.0V

6.9
6.8
6.7

6.6

~_.

6.5
6.4

----TEMP=O

iii 6.3
.a

-0--

6.2

TEMP=25

~-TEMP=70

6.1

6
5.9 ~~-D-----------5.8

__-----------------------------~D

5.7
5.6

5.5

10000

20000

30000

40000

50000

60000

70000

80000

90000

100000

eyelll

Figure 12. 28F016SA Word-Write Tlmevs. Cycling. Word-Write times remain flat to 100,000 cycles.
This figure will be updated to 1,000,000 cycles In next revision (Order nurnber 294016-O02).

Vpp= 12.0V. Vee=5.0V
425
420
415
410
405

- - - - TEMP=70

400

-O--TEMP=O

396
390
385
'380
375
0

10000

20000

30000

40000

50000

60000

70000

80000

90000

100000

Cycl••

Figure 13. 28F016SA Block-Erase Time vs. Cycling. As device cycling approaches 100,000
Iterations, Block-Erase t1mealncrease Slightly, but hard failures do not occur. This figure will be
updated to 1,000,000 cyclea In next revlalon (Order number 294016-002).

9-34

ER-33

Program and erase Vt distributions are a critical
factor in determining device reliability. Since the
amount of electron trapping differs from cell to cell,
post-program and -erase thresholds spread
somewhat with cycling (Figures 14 and 15). The
purity of Intel's ETOX IV thin-oxide formation
technology, coupled with optimally-short WSM

pulsewidth durations and a smaUer oxide area under
stress, reduces electron trapping. Reduced trapping
behavior prolongs buildup of electrons near the
drain and source junctions, keeping threshold
distributions tight while extending the livelihood of
the tunnel-oxide isolation layer.

To Be Available Next Revision
(Order No. 294016-002)
in QI'94

Figure 14. 28F016SA Typical Process Data for Program Vt vs. Cycles. Post Data-Write threshold
distribution increases by only a small degree with cycling.

9-35

a.'

+~I

In",«

To Be Av~ilable Next Revision
(Order NO. 294016-002)
in QI'94

Figure 15. 28F016SA Typical Process Data for Erase Vt vs. (fycles. Erase *hreshold distribution Is .
affected more by cycling than Data Write, but still remains well within acceptable limits.

The robustness of ETOX IV minimizes the negative
effects of write/erase cycling. Write and erase times
remain consistent over the first 10,000 cycles, and
typically double as the d~vice nears 100,000 cycles.
For programming, this means the likelihood of a
second 2.5-I1S WSM pulse; and for erase, the
requi~et'nentJor double the number oftO-ms pulseS.

Process Variation
Intel's process control of ETOX IV critical cell
dimensions keep Data-Write and Block-Erase
electrical characteristics on target with little
variance. This capability assures manufacture of
devices with consistent write/erase performance,
making product operation predictable.
Statistical variation, inherent to any process, will
cause internal cell dimensions to exhibit some small
degree of deviation. The primary process variable
affecting erase is tunnel~xide thickness. Channel
length (Leff) has the largest impact on
< programming. Outgoing product testing ensures
performance to specification regardless of these
minor variances.

9-36

Since statistical variation is inherent to any
manufacturing process, post-program and -erase Vts
for flash memory devices will display Some normal
distribution. The exact time necessary to program or,
erase a particular cell differs across the array, and
from device to device. Be.cause the WSM algorithm
uSes set program and erase pulsewidths (2.5 lis and
10 ms), cells with slow moving Vts can lengthen
overall Data-Write and Block-Erase durations by
requiring additional pulses. These. small variances,
affecting write and erase times, can be seen in
Figures 16 and 17.
In addition to employing program, erase and verify
methods designed to reduce .celi Vt variation, ETOX
IV devices like the 28F016SA are aided by blocking
and new process capabilities.
.
Blocking tightens program and erase Vts by
dividing process variation into sQlaller regions. The
64-KB (32~KW) block size is optimized to balance
threshold control and layout efficiency, so that
accurate VtS can be maintained while keeping die
size to a minimum.

ER-33

To Be Available Next Revision
(Order No. 294016-002)
in Ql'94

Figure 16. 28F016SA Word-Write Times across Process Variation. Control of ETOX IV process
variables via electrical testing and in-line monitors ensures Word-Write conformance to
specification.

To Be Available Next Revision
(Order No. 294016-002)
in Ql'94

Figure 17. 28F016SA Block-Erase Times across Process Variation. Control of ETOX IV process
variables via electrical testing and in-line monitors ensures Block-Erase conformance to
specification.

9-37

.. +:.;:;..
ER-33

In"",.;

New process manufacturing steps maintain very
strict dimensional compliance to stringent
tolerances. Greater dimensional accuracy improves
individual cell erase efficiencies, and therefore
speed. By proliferating theseaccllracies across the
entire array, all .cells erase more efficiently.
Additionally, a uniform array structure makes
source-to-floating-gate coupling more consistent,
thereby providing yet another means to tighten erase
Vt distribution.
The combined benefits of blocking and consistent
accurate dimensions greatly enhances erase
performance and Vt distribution.. Improved cell
erase efficiency, made consistent across entire
blocks, lowers the number of WSM-directed pulses
required to successfully complete Block-Erase
op~rations. Reduced pulsing requirements provides
additional benefit by decreasing the potential for
electron trapping, which completes the circle by·
also aiding to keep erase Vt distributions narrow.
This design for manufacturing approach provides
significant enhancement to product stability and
reliability, while also benefiting the customer via
lower cost.

Electrical Testing.
Electrical testing gives added value to Intel Flash
Memory products. This elaborate testing provides
valuable insight to device characteristics and
ensures product longevity. Electrical test is
performed at both wafer and package levels (Figure
18). All die pass through wafer sort. This testing
involves a screen of the array for defects and
verifies overall circuit functionality. In so doing,
each flash cell on every die is checked for integrity
and proper operation. Additionally, a very high
level of fault coverage is obtained via exercise of
the peripheral logic circuits.

Figure 18. ETOX IV Electrical Testing Flow.
Electrical test and its associated data
collection ensures product integrity and
quality meet high levels, while providing
valuable information to further enhance
process control.
All product shipped proceeds through finished
package test prior to mark. This level of tests
verifies correct assembly, .checks· for defects made
visible from bum-in stressing and guarantees
operation to all timing specifications. The array and
peripheral circuits are again checked for correct
operation.
Supply and input voltage levels and ambient
temperature (TA) are cycled to worst-case minimum
and maximum com!!rs during testing to. ensure

in1et
outgoing product performs to those parameters.
Healthy guardbands compensate for tester
tolerances and tester-to-tester variations.
In addition to guaranteeing that each part meets
specifications, electrical testing serves as a means
for continuous data collection. This accrual of
information allows for a meaningful and optimized
evolution of process and design, contributing
toward a very robust, manufacturable and costeffective technology.

ETOX IV PROCESS-RELATED
IMPROVEMENTS
This section begins with a Historical and
Evolutionary preface, and expands on the following
areas:
-Cell/Array Compaction
-Enhanced Contact Technology
-Improved Cell/Array Uniformity
-Write/Erase Performance
-Cycling Performance
-Read Access

History and Evolution
To put the scope of such an advanced flash memory
manufacturing process into perspective, it would be
helpful to understand the evolutionary and
revolutionary steps involved to reach that point.
Intel, the world's largest IC supplier, is also the most
widely experienced manufacturer of semiconductor
technologies. From the memory side, the company
leverages a long history in a broad variety of
different types and associated processes including:
Static, Dynamic, Pseudostatic and Integrated RAMs
in Bipolar, MOS (PMOS and NMOS) and CMOS
configurations, MOS/CMOS Erasable and Bipolar
PROMs, MOS ROMs, Magnetic Bubble Memories,
EEPROMs and NVRAMs. .Intel invented and
commercialized DRAM and EPROM technologies
via:
-the 1103, 1024 x I-bit Dynamic MOS RAM in
1970

ER·33
-the 1702,256 x 8-bit UV-Erasable MOS PROM in
1971
The 1702, using a charge storage element referred to
as a Floating-gate Avalanche-injection MOS
(FAMOS) device, gave birth to Intel's EPROM
product family. This device had a cell size
measuring 909 11m2 via IO-Ilm lithography. The
upgrade I702A-2 offered this product's fastest
maximum access time of 650 ns via +5V ±5% on
three VCC inputs and one VBB input, and -9V
±5% on VDD and VGG. The requirements for
programming input and· supply voltages (with
respect to the three VCC inputs held at OV) were:
-VB B held at+I2V ±1O%
-VDD and PGM pulsed to -47V ±IV
-VGG pulsed to -37.5V ±2.5V
-Address input voltages at OV for logic "1" and
-44V ±4V for logic "0"
-Data input voltages were OV (cell remains
unchanged) or -47V ±IV to program a logic "1"
(output high in read mode)
Programming time for this device was very slow
relative to today's technology; it required
approximately 64 seconds for the tiny 2048-bit
array. A large .part of this was due to the greater
number of input pins requiring transition with
longer setup, . hold and pulsewidth durations.
However; the ..biggest factor affecting throughput
was that the programmer had to scan through all
addresses in ascending binary sequence 32 times
(i.e., a data location could not be pulsed 32 times
before moving up to next byte).
Since those early days, substantial advances have
been made in the manufacturing process and
architectural design resulting from a strong
commitment to continuous test data collection and
process monitoring, capital expenditure to maintain
equipment and facilities on the forefront ofleadingedge capabilities, and extensive R&D spending to
lay the groundwork for today's technologies. These
advancements made possible Intel's final EPROM
development vehicle, the 8,388,608-bit 0.8-llm
27C800 in late 1990. This device, with a cell size of
6.5 11m2, advanced then current EPROM technology
to the state-of-the-art for read access and
programming. Advanced array layout design and

9-39

ER-33

improved read path technology enabled
85 ns
maximum tACC from a single +5V VCC
requirement. A theoretical array programming time
of 6 seconds resulted from a simplified algorithm
flow (very simple relative to the 1702 or 2708) with
individual byte pulses at 10 flS, and address/data
setup and hold times in the 400 ns and I flS range.
Voltage requirements (referenced to the GND pin)
were:
.Vpp at 12V ±0.2SV
• VCC at S.OV ±JO% during programming and
6.25V ±0.25V for margined verification
.Address, data and control inputs at CMOSrrTLcompatible voltages
In retrospect, early EPROMs like the 1702 and
1702A were constructed with p-channel MOS
transistors,
and
had
minimum-design-rule
geometries of 10 flm. The first major technological
milestone came about in 1975 when EPROMs
transitioned to n-channel devices. Intel's 1024 x 8bit 2708 dramatically improved device read
performance because of the inherent higher speed of .
n-channel charge carriers (electrons) in silicon.
The 2708, which was manufactured on 6-flm
technology, required three power supplies for read:
.VCC at+5V'±5%
• VBB at -5V ±5%
.VDD at +12V ±5%
Its 2708-1 version was specified at 350 ns
maximum tACe- Programming for' this device,
which was specified at 100-seconds typical for all 8
Kbs, allowed use of the same VILIIHTTL-Ievel
address/data input signals required during reads.
The following additional input voltages (referenced
to the GND pin) were required:
• CS#IWE input held at + 12V ±5%
.PGM input pulsed to +26V ±IV
The 2716, introduced in 1977, evolved the
technology to a single +5V ±5% VCC supply
requirement for read. Access time though, remained
at 350-ns maximum for the fastest product offering.
The 2716 also incorporated a dedicated
programming supply input, Vpp, requiring +25V

9-40

±IV, with address and. data setup and hold time
minimums reduced to 2flS.
It wasn't until 1980 though, when Intel's 2764, the
first EPROM manufactured on. the company's
patented HMOS-E (High-PerfOrnlance ncchannel
MOS) technology, that read performance made a
large gain by achieving 200 ns. This device
incorporated a 159-flm2 cell via 4-flm geometries.
The next HMOS-E device,.a 2732A (stepping of the.
2732) reduced cell size to 100.6flm2 via 3-flm
geometries .
Since then, HMOS-E progressed to HMOS II-Eand
HMOS III-E, with dimensions shrinking from 4/3
flm to 2.0/1.5 flm to 1.2 flm. These process
evolutions enabled shorter programming pulsewidth
durations and address/data setup and hold times, as
well as a reduction in the VPP programming
voltage. New algorithm flows could be developed,
enhanCing production programming throughput.
Also, coupled with architectural design advances in
array layout, d,coding and sense amplifier circuitry,
read performance continued to improve to 150ns.
CMOS circuits, implemented for the periphery of
the device, were first used on the 27C64. This was
the next major milestone for EPROM technology, as
it provided significant reduction to device power
consumption. This advancement ushered in Intel's
next pate!1ted EPROM. process- CHMOS II-E
HMOS),
which
fostered
(Complementary
geometries of 1.5 flm and 1.2 flm. CHMOS III-E
produced a geometric reduction to 1.0 flm, and 0.8
flm was realized on what would have been CHMOS
Iv-E if Intel had continued to stay in the EPROM
market. It was also becoming very apparent, at this
point, that migration toward smaller geometries
would make floating-gate discharge (erase) via
ultra-violet light exposure increasingly longer and
more difficult to achieve .
Intel's first Flash Memory device, the 57F64, was a
8-K x 8 Flash EPROM manufactured on the
company's CHMOS II-E process. This device, when
introduced in early 1988, leveraged a three-year
manufacturing base built on the CHMOS process. It
laid the groundwork for the first ETOX I product,
the 27F64 flash memory, which was soon followed
by the higher-density 27F256,. 28F256PI and
28F256P2 devices.

in1et
Intel's 28F256A, 28F5l2, 28FOIO, 28FOOIBX and
28F020 flash memories, which were introduced in
1990 and 1991, are manufactured on the ETOX II
process, which itself .had knowledge gained from
l.O-f.1m CHMOS II~-E technology. ETOX III
devices such as the 28F002BX, 28F200BX,
28F004BX, 28F400BX and 28F008SA, which were
introduced in ,1992, leveraged the earlier 0.8f.1m
development work performed on the 27COIOA and
27C800. The 28FOIO, 28FOOIBX and 28F020 have
since transferred to 0.8-f.1m manufacture.
This long history of experience has allowed Intel to
travel further along the semiconductor memory
learning curve than any other flash manufacturer in
the world. Continuous improvements ih process
control have culminated in the highest levels of
quality, reliability and manufacturability which are
inherent to the company's ETOX IV process. The
most notable sign of this quality and reliability is in
the cleanliness and integrity of the ETOX IV tunnel
oxide. All areas of performance for a flash device,
such as consistent timings, data retention and
cycling durability depend, to a great extent, on the
tunnel oxide.
ETOX IV maintains an advanced scaled substrate
EPI thickness to practically eliminate product latch~p, and uses double-metal technology to carry
bitline data and strap the wordline. These process
advancements aid cell/array compaction and
enhance device read/write times. Array compaction,
in turn also boosts read/write performance. Doublemetal technology, 'first used on ETOX III, requires
improved planarization processing. A desirable byproduct of improved planarization is enhanced
moisture performance.
ETOX III achieved a very high level of
planarization through several ' of its process
improvements. The enhanced contact materials and
methodologies of ETOX IV aid in making the array
structure even more planar. Additionally, tighter cell
dimensions proliferated across the entire array
enhance planarity by making it more consistent.
Greater structural uniformity and improved step
coverage enhance process manufacturability,
improve product reliability, and make program and
erase threshold distributions and read/write timings

ER-33
more consistent. Also, ETOX IV's smaller oxide
~ea per cell,' coupled with extremely low defect
density, provide lasting integrity for cycling and
data retention.

Cell/Array Compaction
Not too many years ago, it was doubtful whether
semiconductor minimum dimensions would ever
scale below 1.0 f.1m. Through roughly six years of
Intel Flash Memory development, ETOX process
geometries have shrunk from l.2f.1m on a device
like the 28F256-PIC2 to 0.6 !1m on the 28FOI6SA.
This rapid advance in reducing minimum-designrule geometries not only exhibits superior technical
prowess, but also increases cell, density per unit
area, thus keeping flash memory cost-per-bit
learning on track with prior expectations.
The shrinking of minimum dimensions also enables
the capacity to cost-effectively incorporate higher
levels of logic integration, while maintaining or
reducing the periphery-to-array transistor ratio. This
logic integration brings .the control functions for
flash memory operations on the chip. Also, new
features can be cost-effectively added into designs
(28FOI6SA as example).
In addition to higher integration, array ~ompaction
allows a means for packing dense memory devices
into ultra-small packages like 56-ld TSOP (14-mmlong x 20-mm-wide x l.O-mm-thick Thin SmallOutline Package). This small package gives the
versatility to ~uild compact high-density modules
and systems like a 40-MB Flash Memory Card with
form and fit to PCMCIA 68-pin type-II mechanical
specifications.

Enhanced Contact Technology
Ever-shrinking geometries mandate continuous
improvement to existing production methodologies
and materials; and development/use of new
capabilities. These improvements and developments
allow compaction not possible via minimumdesign-rule reductions only.

9-41

ER-33
The enhanced contact. technology of ETOX IV is
such an example of new development and
continuous improvement, enabling the tighter
placement of array. cells via metal-I-to-silicon
contact hole minimization. Step coverage and
contact resistance improve via these advances,
enhancing yields, reliability and performance.

Improved Cell/Array Uniformity
Large flash memory arrays require uniform cell
structures to maintain tight program and erase Vt .
distributions. Consistent Vt distributions are critical
for reliable device operations, especially Block
Erase.
ETOX IV employs new manufacturing techniques
that improve cell, and therefore array layout
uniformity. In addition to improved threshold
distribution, this uniformity provides:
more consistent read, write and erase timings,
increased product reliability,
a higher degree of cell/array compaction,
a more planar silicon formation,
and greater manufacturing yields.

Write/Erase Performance
Data-Write and Block-Erase timings are reduced
from previous product generations via the combined
effects of geometric scaling, enhanced cell/array
dimensional uniformity and optirnization of WSM
pulses, support circuitry and algorithmic flows.
Additionally, new device features like multiple
command queuing, a Block-Erase tagging
mechanism and fast data-in caching buffers improve
write and erase performance at the system level.
An externally-controlled timeout of 100 J,lS
. programs a byte on the l.5-J,lm 28F2~6-170PIC2.
An internally-controlled pulsewidth of 2.5 J,lS
programs a word. or byte on the 28FOI6SA.
28FOl6SA erase, which includes WSM pre-erase
conditioning of all block bits (64-K:B/32-KW
block), typically requires 800 ms. A combination of
4-second typical chip-program and I-second typical
chip-erase times is necessary to net the same erase

9-42

infe[
result on the 32~KB 28F256-170PIC2, whose entire
. array is half that of one 28FOI'6SA erase block.

Cycling Performance
Cycling durability has made tremendous gains from
early first-generation devices, such as the 28F256170PIC2 with a 100-cycle specification. Current
products, such as Intel's ETOX III 28F008SA, are
registering above 1,000,000 cycles. Experiments
with these units have been conducted to prove their
reliability. These parts typically do not produce
hard failures, instead they see program and erase
timings push out.
ETOX cycling longevity has progressed due to
continued improvements in tunnel-oxide qUality. As
oxide layers become cleaner and more consistent,
cycling-induced electron trapping mmlmlzes.
Reduced electron trapping helps to keep Vt
distributions tight. Additionally, reduced electron
trapping improves program and erase pulsing
efficiencies. Improved pulsing efficiency lessens the
number of pulses required for a given operation to
succeed, which in tum also reduces electron
trapping. Since trapping is the primary source of
program/erase timing pushout (Le., more pulses
required), higher quality oxides reduce this
degradation and extend cycling performance.
Improved
source-to-floating-gate
coupling
consistency via enhanced cell/array uniformity also
extends cycling longevity by lowering the number·
of erase pulses required. Additionally, the Intel
ETOX cell, in combination with optimal WSM
control, typically requires a very low number of
pulse repetitions to achieve a program or erase state
(typically one pulse for programming). This also
lowers the pulse count, extending cycling
.
livelihood.
Improvements in isolation, both from cell to cell
and around the floating gate, have practically
eliminated charge retention and data disturb
concerns. Contrary to competitor reports, parts with
more than 1,000,000 cycles retain data as well as
devices with much less cycling.

intel·

ER-33

Read Access
Intel Flash Memory architecture has evolved by
leaps and bounds since its inception. Read access
time (tACe> has made significant gains, while
maintaining very high levels of noise immunity.
The 27F64's fastest speed bin was ISO ns with
±S%VCC' while the 28FOl6SA wiJI offer a S.OV
70/80-ns version with ±5/10%VCC tolerance and a
3.3V ±O.3V 120,-ns version.
Double metal, introduced on ETOX III, has been the
biggest contributing factor toward improving read
access times. This enhancement reduces wordline
and bitline resistance, thereby enabling faster cell
turn-on and sensing paths during read operations.
Continually-improved
circuit
designs
also
contribute to shorter read timings. Again, cell and
of
array
compaction
enables
inclusion
new/additional circuitry that enhance read
performance, and will also allow future 3.3V parts
with access times much faster than their S.OV
predecessors.

!,
I.

9-43

· ER-33

volatile memory density hIlS grown from 2,048 bits
to 16,777,216 bits, a factor of·8192x. Figure 19
compares other memory types to show relative
density progression. The fast ramp in ETOX flash
memory density results from' its similarity to
EPROM.

FLASH VS. OTHER
SEMICONDUCTOR MEMORY
TECHNOLOGIES
Intel's scaling advances in flash memory
manufacturing and design provide optimal cell/array
compaction. In roughly twenty-two years, Intel non-

32M

IBM

>iii

I-

...c

512K

256K

Q::

...
:::IE

12BK

32K

16K

1970

1974

1978

1982

1986

li90

19U

1998

PRODUCTION YEAR
294012-7

Figure 19. Memory Evolution

9-44

intel~

ER-33

Figure 20 illustrates the relationship between cell
sizes of different memory types 1IIld minimum
geometries. As dimensions scale, certain memory
types become cell-size limited (i.e., some
components cannot shrink proportionally). The
memory cost-per-bit learning curve shows flash in a
strong position. This curve, shown in Figure 21,
reflects how Intel's experience reduces cost for
increased memory density.

Since the late 1980's, a new memory sub-system has
arrived on the market offering an alternative to
high-denisty file system media. Intel's Series 2+
Flash Memory Cards take advantage of the
28FO 16SA an 'its third-generation .architecture to
provide card densities of up to 40 Mbytes and·new
functionality. This relatively new technology offers
a solid-state file system (Figure 22) that will double
in denisty with new ETOX gellerations.

1000
500

......

200

'-'
LoJ

100

In
..J
..J
LoJ

>-,

50
20

0::

0
:::Ii

LoJ

:::Ii

2.0

1.2

1.0

MINIMUM FEATURE SIZE ("')

294012-8

Figure 20. Memory Cell Size Trends

9-45

intei.

ER·33

---------- .... ....

...... - ...

...,;.

- ....
.........

----- ----'- ....

EEPRO;

.....

---- ----

EPRO~

1988

1989

1990

Figure 21. Memory Cost/Bit Learning Curves

9·46

1991

1992

1994

294012-9

intet

ER-33

:cII
:il'

256

640

128

320

160

.!l

'iii
c:

...0

I\ ~

~
c

II'

I ~;

::I

II>

c:
CD
c:

I'i1:

"'-

s:
CD

..
.,

:::I!

(.)

'91

'92

'93

'94

'95

'96

'97

'99

2000

294012-10

Figure 22. ETOX Component and Memory Card Density Over Time

SRAM and DRAM
SRAM and DRAM have fast read/write speeds.
Both though, are volatile memories requiring
continuous power to retain data. Standard SRAMs
(Figure 23) require four to six transistors for each
flip-flop cell. This greatly reduces memory capacity
per unit area, raising product cost for a given
density.
DRAM requires constant refresh of its capacitor-like
storage mechanism (Figures 24 and 25) due to
leakage currents and read operations. Charge
storage requirements limit size reduction of this
capacitor, which in turn limits memory array
compaction. With smalier geometries, DRAM cell
structures become increasingly complex requiring
additional and more difficult manufacturing steps.

294012-11

FIgure 23. Six-Transistor SRAM Cell
Schematic

9-47

.'In-e-;.
+_J

ER-3.3

which in turn controls bitline voltages. This allows
flash memory read sensing to easily detect cell Vts.

St'-

C~;:==]~

r----=~....,

STORAGE

I:::" ELEMENT

S = SOURCE
D = DRAIN
CG = CONTROL GATE

Most DRAMs require high active. power
consumption. Charge storage requirements and read
signal strength constrain DRAM cell compaction.
Low-power ETOX IV flash memory has a simple
single-transistor cell with only minor scaling
limitations through the year 2000. This results in a
mainstream memory that does not need power to
retain data.

EPROM
294012-12

Figure 24. Stacked -DRAM Cell (Side View)

Intel's prior EPROM technology and Flash Memory
cells share a common stacked-gate profile (Figure
26), with two basic differences relating to their
respective erase mechanisms. EPROM requires
ultraviolet light to erase, flash erases. electrically.
Electrical erase is possible because flash. has a
thinner cell oxide to allow F-N tunneling, and a
graded. source diffusion to improve source-tofloating-gate coupling and rrevent . breakdown
during erase.

S = SOURCE
D = DRAIN
CG = CONTROL GATE

294012-13

Figure 25. Trenched DRAM Cell (Side View)

Most DRAMs require. read parity. This additional
bit is needed for two reasons: First, alpha-particle
strikes can disturb cells via ionizing radiation, with
resulting loss of data. Second, during reads, only a
small voltage differential is available for sensing
because the cell's storage mechanism capacitively
shares its charge with the bitline through the select
transistor. This low:voltage differential can also be
influenced by nearby bitline voltages and device
noise.
Parity bits are not required .on floating-gate
technology because the -substrate is electrically
isolated from the charge storage mechanism. Unlike
DRAM, floating-gate charge determines cell Vts,

) SiD)
('--------->{
S=SOURCE
CG=CONTROL GATE

D=DRAIN
FG=FLOATING GATE

Figure 26. EPROM Cell (Side View)

EPROM technologies migrating to smaller
geometries will find floating-gate discharge (erase)
via UV exposure increasingly difficult. One
problem is that metal bitline widths cannot reduce
proportionally
with
process
technology
advancements. EPROM metal-width requirements

ER-33
limit bitline compaction in order to maintain low
resistance. As such, they reduce the amount of highenergy photons that otherwise would reach charged
cells. Additionally, as dimensions scale, airborne
(and other) particles that were once insignificant,
now become a factor as they also obscure photons.
EPROMs
built on
sub-micron
Therefore,
technologies will face longer UV exposure times.
Intel's ETOX IV technology employs a secondmetal processing step to strap word lines for
improved read performance. This advance is not
likely to appear on EPROM because it would block
even more UV light. Since flash memory
electrically erases, it eliminates these concerns.
Moreover, flash electrical erasure eliminates the UV
window and its associated cost. This allows ready
acceptance of the most advanced and innovative
plastic surface-mount packaging solutions.

....._ _ _F _ G _ J

)

(
S = SOURCE
CG = CONTROL GATE

D = DRAIN
FG = FLOATING GATE
294012-15

Figure 27. Flotox EEPROM Cell (Side View)

EEPROM
Conventional two-transistor EEPROM cells limit
layout density. In addition to the main cell shown in
these figures (27 and 28), a second transistor works
as a bit select. This extra transistor and decoding
circuitry are required for single byte program and
erase capability. Technology design requirements
make EEPROM cell, like triple-poly, significantly
larger than flash. Typical EEPROM technologies
are more complex, making 'wafer manufacturing
difficult and expensive.
Because of their traditional application, EEPROMs
use a very high internal voltage (17V to 30V) to
achieve fast program and erase times. These high
voltages and resulting electric fields cause cell
oxides to breakdown, shortening cycling life and
degrading cell thresholds. Additionally, this high
voltage stresses periphery transistors. Intel's Flash
Memories are more akin to EPROM; both use a
significantly lower voltage around 12V.

S = SOURCE
D = DRAIN
CG = CONTROL GATE
FG = FLOATING GATE
EG = ERASE GATE
294012-16

Figure 28. Triple-Poly EEPROM Cell (Side
View)

PROCESS/DESIGN TRADEOFFS TO
ACHIEVE THE PERFECT FLASH
MEMORY
There are two main differences in flash memories
today. The first is in the structure of how the
individual' flash cell is built. Examples are Intel's
stacked-gate approach and SunDisk's triple-poly
flash cell. The second difference is in the
architecture of the array. Array layout not only
affects the structure and complexity of the chip, but

9-49

ER-33
it· also influences the methods used to write, erase
and read the device, and the subsequent
performance of these operations. This section
describes several oftoday's prominent flash memory
technologies, and discusses various characteristics
for each.

NOR Flash
There are several types of NOR flash in
development today, most of which use structures
similar· to Intel's stacked"gate ETOX cell. The
defining characteristic of NOR technology is array
layout (Figure 29). In this implementation, many
flash cells are connected, via their drains, to a
common column, or bitline. Many bitlines are
grouped to make up individual I/0s. A select line,
or wordline, serves as the control gates for a row of
flash cells, one on each bitline. This layout allows
for many cells, usually a byte or word, to be
accessed in parallel, thereby providing .for fast
random read/write access performance. Different
NOR technologies vary mainly in erase
methodology.
BL

8~ 0

Figure 29. NOR Flash Array

9-50

eTOX Flash
Intel's ETOX NOR technology uses a High-voltage
Source with grounded-gate' Erase
(HSE)
methodology, as described earlier in this report
(Figure 7). A paper published by Toshiba Corp. in
1992 entitled, "Comparison of Current Flash
EEPROM Erasing' Methods: Stability and How to
Control", describes Intel's HSE as "the most stable
scheme for the control of erasing speed and erased
threshold voltage distribution." It also concluded
that certain tools are needed for "suppressing the
erased-Vt distribution width" in other methods of
erase, such as Negative Gate-bias Erase (NGE).

intat
Negative Gate-Bias Erase (NGE)
The method of erasing flash cells via NGE is
inherently more complex than Intel's HSE approach.
There are two main variations of this scheme. The
first is a Negative Gate with positive Source Erase
(NGSE) method. NGSE requires a large negative
voltage on the cell's control gate while placing an
intermediate positive voltage on the source.
Advanced Micro Devices, Inc. uses this approach
with voltages as seen in Figure 30. The second is a
Negative Gate with positive Channel Erase
(NGCE). This practice is being considered by NEC
Corp. by placing voltages as seen in Figure 31 on
the cell.

--10V
CG

S=SOURCE
CG=CONTROL GATE

ER-33
Routing negative voltages throughout the device
requires a higher degree of isolation in the periphery
than needed for HSE devices. Consequently, the
peripheral circuitry consumes a larger percentage of
total die area. In addition to increased isolation, a
triple-well process or large p-channel devices are
necessary to switch the negative voltages onto cell
gates. An on-chip charge pump must generate this
negative voltage. These three requirements increase
die size, thus inflating the product's cost.
In general, a more complex manufacturing process
is required to produce flash memory devices using
NGE. Small statistical variations in manufacturing
parameters can cause threshold voltage instability in
these devices. Without the use of advanced tools
and close process monitoring, this complex process
can lead to inherently less reliable and inconsistent
flash memory devices.

D=DRAIN
FG=FLOATING GATE

Figure 30. NGSE Cell Erase Voltages

--13V
CG

-5V
S=SOURCE
CG=CONTROL GATE

D=DRAIN
FG=FLOATING GATE

Figure 31. NGCE Cell Erase Voltages

9-51

ER-33

NAND Flash
Bit Line

NAND flash· memories, such·· as those produced at·
Toshiba Corp., use a cell similar to NOR, but with a
distinctively ·different array layout (Figure 32). NOR
cells are accessed in parallel, while NAND access is
serial. This serial access unfortunately leads to very
slow random read timings. Toshiba's 16-Mb NAND
has random read timings that are more than two
orders .of magnitude longer (15 f.lS vs. 70 ns) than
those available via a NOR-layout approach.

Select Gate 1 ----If-+---+---

Control Gate 8

-'----11++----+-..;...-

CG7----+H-----~------

Also, if the data-read requirement is greater than
256 bytes in length, additional delays occur. These
additional delays happen on the first memory access
when page boundaries are traversed (i.e., the
Toshiba 16-Mb NAND array is decoded into 256byte pages; switching to read from another 256"byte
boundary causes a 15 f.lS delay to valid data-out.

CG6----+H-----~------

CG5----II++----+___

NAND program and erase methodologies differ
from those of NOR devices. Toshiba Corp. employs
F-N electron tunneling for both operations. A very
high voltage (20V) is applied to the control gate
during programming, and to the substrate for
erasure (Figure 33). This high voltage amplifie~
reliability risks in both cases. Tunnel-oxide
breakdowll is more probable than with Intel's ETOX
technology. In fact, Toshiba Corp.'s flash memories
compensate for these concerns by incorporating
extra bytes in each page for error correction.

CG4--~+r---+-----

NAND's serial scheme allows tighter compaction in
the array because its architecture only requires one
contact for each string of 8 or 16 cells, vs. one
contact per each .cell pair in NOR devices. The
downside for NAND is that this gain is lost due to
an overall drop in array efficiency. This loss results
from increased decoder size and complexity
necessary to handle the serial array structure. Also,
large charge pumps and extra isolation in the
periphery are needed because of the requirement for
very high write and erase voltages. Besides
impacting reliability, high voltage isolation also
induces fixed limitations to the future scalability of
this technology.

Select Gate 2 --""""if+---+---

9-52

CG3---~+r---+-----

CG2--~+r---+-----

CG1-----tH-----E-------

294012-17

Figure 32. NAND Flash Array

in1et

ER-33

PROGRAM

ERASE

-+20V

FLOAT

)

OV/+7V
D

(

FLOAT

)

{

(

FLOAT
D

')
{

+20V

OV
S=SOURCE
CG=CONTROL GATE

D=DRAIN
FG=FLOATING GATE

S=SOURCE
CG=CONTROL GATE

D=DRAIN
FG=FLOATING GATE

Figure 33.. NAND Cell Program and Erase Voltages

Triple-Poly Flash
The name of this technology reveals its cell
structure difference from the ETOX double-poly
stacked gate. .See Figure 34 for a schematic
representation of this cell and array configuration.
Although the theory behind triple-poly is sound,
manufacture is very difficult. As such, SunDisk
Corp. uses extensive error correction and
redundancy in their devices to provide yield and
reliability enhancement.

cell. Programming, via CHE injection, proceeds by
placing 12V on the poly-2 control gate and 7V on
the drain (Figure 35). The source and erase gate are
atOV.
The third poly layer is used during erase operation.
Poly-to-poly tunneling is invoked by bringing the
poly-3 erase gate to voltages ramping between 12V
and 22V. This high voltage prevents minimum
design-rule scaling below certain limits, and
increases the likelihood of oxide wearout due to a
high field stress, acr~ss the small oxide area.

This technology incorporates a poly-l floating gate,
storing charge in much the same way as an ETOX

·9-53

intet

ER-33
D (DRAIN)

EG
CG

-1

-til

S (SOURCE)
DIS

DIS

DRAINISOURCE (DIS)

ERASE GATE (EG) -==+==::;:::=+===::;:::=+==:::::;;:::::::j==:::::;;:=t:~ CONTROL GATE (CG)

Figure 34. Triple-Poly Flash Cell Schematic and Array Configuration

WORDLINE
::>

12TO 22V
12V

iP:Z:\
P

PROGRAM
EG=ERASE GATE

ERASE
CG=CONTROL GATE

Figure 35, Triple-Poly Cell Program and Erase Voltages

9-54·

POL

FG=FLOATING GATE

ER-33

SUMMARY

OTHER REFERENCES

Intel's technological advances result in flash
memory products that are more efficient, more
reliable, less expensive and higher performance.
Finer geometries, double-metal technology and EPI
wafer processing allow considerable gains in
memory array compaction. This compaction nets
improved write/erase performance and lower
product cost.

Related documents of interest to readers of this
engineering report:

New ETOX IV manufacturing steps and contacting
technologies also contribute to cell compaction and
improved reliability.
Extremely high cycling
endurance results from the superior quality of Intel's
ultra-pure thin tunnel oxide and the electrical
characteristics of internal program and erase
operations.

ER-31: the Intel 28F016SA FlashFile™ MemoryArchitecture and Characterization· Summary (Order
No. 294015 - Available QI'94)

Cycling, voltage and temperature exhibit only a
small influence on Data-Write and Block-Erase
speeds. Products built on Intel's CMOS ETOX IV
Flash Memory technology require very low power
consumption during Data-Write, Block-Erase, Read,
Sleep and Standby modes.

28FO 16SA Data Sheet (Order No. 290489)
28F032SA Data Sheet (Order No. 290490)
28F016SA User's Manual (Order No. 297372)

AP-375: Upgrade Considerations from the
28F008SA to the 28FO 16SA (Order No. 292124)
AP-377: the 28F016SA Software Drivers (Order No.
292126)
AP-378:System Optimizaiton using the Enhanced
Features of the 28.FOI6SA (Order No. 292127)

Intel Flash Memory products designed on ETOX IV
will satisfy many different applications. The Thin
Small-Outline Package (TSOP) provides high
memory density in an extremely small footprint.
Some applications include memory cards, solidstate drives, resident code (O/S and application) and
file storag~, data acquisition and embedded code
storage.
The solid-state nature of flash provides far superior
ruggedness over mechanical rotating media. With
blocking, applications can perform erase as a
background task to optimize system performance.
Today, Intel's technological advances in flash
memory are driving cost to parity with DRAM. This
steep decline in the price learning curve enables
new classes of systems and system architectures.

9-55

Article Reprints

ISSCC 931 SESSION 31 NON-VOLATILE, DYNAMIC, AND EXPERIMENTAL MEMORIES I PAPER WP 3.6

WP 3.6: Flash Solid·State Drive with 6MB/s ReadlWrite
Channel and Data Compression
Steven Wells, Don Clay'
Intel Corporation, Folsom, CAI'Conner Peripherals Incorporaled, Longmon~ CO
Flash memory densities are sufficient for solid-state mass
storage applications. Hard-drive emulation using flash memory
provides a standardized system interface with characteristics
superior to those of magnetic drives in read and seek performance, energy consumption, acoustics, ruggedness, and reliability. This 42MB 2.5" drive includes a thirty 8Mb device
flash array, an embedded processor, and interface ASIC. The
O.7i1m standard-cell ASIC contains drive interface circuitry,
4-port butTer manager, flash interface, and a LempeVZiv type
hardware compressor. Flash device architecture is optimized
for cost-etTective high-density systems.
The dominsnt cost of the flash-based drive is in the flash
device. Two issues have significant impact on flash device
costs: 1) number of cells in the erase-block, and 2) required
erase performance. Prior reported triple-poly and NAND device architectures closely match erase-block with drive- sector
size and require high-performance erase before each sector
write [1,2]. This flash drive supports a large erase-block size
and reduces requirements on erase performance allowing use
oflower-cost stacked-gate NOR flash devices (Table 1) [3]. A
large erase-block reduces flash die size and complexity of
decoders and drivers. Reduced requirements on erase performance reduce cost by simplifying the flash cell and enhancing
yield.
The system block diagram is shown in Figure 1. The device
array is organized into pairs for increased performance. The
embedded processor handles drive commands and manages
the flash. A butTer RAM provides drive-interface compatibility
and allows caching.
A linear write algorithm executed by the embedded processor
writes each sector to the next available location in the flash
array and notes the sector number. A prior copy of a sector
stored in the flash array is marked ·old" and is no longer
referenced. Reclamation of old sectors is managed by the
embedded processor transparent to the drive interface by
identifying erase-blocks with old sectors, moving remaining
sectors to other blocks and initiating erase. Measured program/erase cycling with this algorithm is shown in Figure 2.
Optimum erase-block size for stacked gate NOR flash devices
minimizes the time required to reclaim old sectors (Figure 3).
A custom interface ASIC is designed for maximum transfer
performance from flash to drive interface. A 20MB/s circuit
transfers data from flash to the butTer RAM. A 4-port prioritized butTer controller interfaces the flash transfer circuits,
the drive interface, and the embedded processor with sustained 6MB/s on both drive interface and flash media. The
interface controller is state-machine controlled to allow the
embedded processor to focus on acquiring the next sector or
flash reclamation. The drive is capable of sustained 4MBls

Zero spindle-energy provides 30x energy savings over conventional magnetic drives. This drive quickly enters and exits
lowest power oscillator-disabled sleep modes. An intermediate
energy-saving mode disables ASIC clock distribution during
momentary idle times; a data request re-enables it within
5Ons. Figure 4 diagrams the oscillator control and clock distribution circuit. REQUEST strobes the oscillator or clock disable request into latches Ll and LB. Latch Ll, which stores the
clock on/otT request (CLlCEN), disables the ASIC clock via
embedded processor command ACTIVATE A host interrupt
re-enables it through latch L2. Latch LB stores the embedded
processor oscillator-disable request from OSC_EN. Latches
L4-LS ensure glitch-free clock-signal propagation. The ASIC
vendor optimized latch elements reduce metastability.
A LempeVZiv data compressor is integrated into the read/
write channels to enhance read/write performance, reduce
energy consumption, increase density, and enhance etTective
butTer bandwidth. The compressor operates on 512B ~sectors
and achieves an average compression ratio of 1.6x at a sustained 6MB/s for read and write. The linear write algorithm
combined with large erase blocks is key for efficiently storing
variable-size sectors. Increased density is achieved through
drive interface protocol enhancements. Sectors that generate
compression ratios <1 are stored uncompressed.
Overall system performance is compared to a typical 2.5" drive
in Table 2. Figure 5 shows drive read timing with parallel host,
sector butTer, and flash transfer. A photograph of the system
is shown in Figure 6.
Acknowledgments
This work was made possible by S. Anderson, R. Garner, T.
Kendall, R. Hasbun, S. Domonkos, S. Barbarich, M. Powell,
and D. Edwards. The authors thank J. Squires, P. Jacobs, D.
Pashley, B. McCormick, M. Winston, and J. Weisenstein for
vision and support.
References
[1] Mehrotra, S., et al., "Ser/aI9 Mb Flash EEPROM For Solid Stste

Disk Applications", Symposium on VLSI Circuits, pp. 24-25, June
1992.
(2) Itoh, Y., et aI., "An Experimental 4Mb CMOS EEPROM with a
NAND Structured Cell", ISSCC DIGEST OF TECHNICAL PAPERS,
pp. 134-135, Feb. 1989.
(3) Kynett, V., etal., "A90ns 100kEraseiProgram Cycle MegabitFlash
Memory", ISSCC DIGEST OF TECHNICAL PAPERS, pp. 140-141,
Feb. 1989.

random read transfers.

© 1993 IEEE. Reprinted, with permission, from
1993 IEEE International Solid·State Circuits Conference Digest of Technical Papers,
San Francisco, CA, February 24-26, 1993.

Order Number 295077-001

10·1

100000

10000

/.M"~~.,..~'.

IS MlIIion 60 KB rile WriIC!

1000

60 KB/min Ale Wrhc Rille f1'O( 28 Years

I()()

+---___-+______+-___

1.008+07

1.008+08

1.008+09

Number Of'Scclor Wrilcs

Figure 2: Device cycling versus sector writes.

Figure 1: System block diagram.

INTR

~\"

~
.l!
~

64 KB '" 2 Devjc~s/Pair
____ Total Reclaim Time

'--- -----

AenVATE

..................

....... Pre-Erase SeClOr Copy Time

~-'-''------ Block Erase Time

.........
50

150

100

250

200

300

Block Size (KB)

Figure 4: Oscillator control and clock distribution.

Figure 3: Optimum block size to minimize reclaim time.
Disk Interface

Read
Dara (I6b)
Write

Buffer Interface Read

Dala (8b)

Flash Inlerface Read
Dala (16b)

J'C:::X=;O<..J~~"'"'C::iCCX:::;Qo(

--"LJ

---x

,:><)(:::==============

Figure 5: Capture interface, buffer, and flash transfer.
Figure 6: See page 262.
Feature size
CeIl
Organization
Erase block
Die size

Read throughput
. Program throughput
Erase throughput

0.8J.U1l
7.25J.U1l2 stacked-gate NOR
8Mbx8
.
64kB
102mm2
70nsIB
111kBIs
64kB1s

Table 1: Flash device features.

10-2

This System (read/writel
6MB/s, 6MB/s
Yes
9.6MBls, 0.36MBls
(with compression)
Spinup time
3ms, 6m.
Shock, oplnon-op lkGllkG
Seek, avg/trk-trk I32/F Two Pacific Place

Intel Japan K.K. *
Hachioji ON Bldg.

88 Queensway

~·~~1ojr.r~I~'T~~~h;92

Central
Hong Kong
Tel: (852) 844-4555
FAX: (852) 868-1989
INDIA
Inlel Asia ElectroniCS, Inc.

4/2, Samrah Plaza
S1. Mark's Road

Bangalore 560001
Tel: 91-80-215065
FAX: 91-80-215067
TLX: 953-845-2646 INiL IN

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JAPAN
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Ibaraki, 30()'26
Tel: 0298-47-8511
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Tel: 0426-48-8770
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