210912 001 I APX 86 88 186 188 Users Manual 1985

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iAPX 86/88, 186/188 User's Manual
Hardware Reference

1985

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Table of Contents
Chapter 1
8086/8088 CPU
1.1 Introduction................................................................. 1-1
1.2 Component Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-1
1.2.1 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-2
1.2.2 Software Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-12
1.3 Device Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-42
1.3.1 Functional Description of All Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-43
1.3.2 Electrical Description of Pins .................................................. 1-43
1.3.3 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-43
1.3.4 Minimum Mode System Overview/Description .............. , ..................... 1-44
1.3.5 Maximum Mode System Overview/Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-52
1.3.6 General Design Considerations ................................................ 1-64
1.4 Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-64
1.4.1 Multiplexed Address and Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-64
1.4.2 Bus Cycle Definition ........................................................ 1-65
1.4.3 Address and Data Bus Concepts ............................................... 1-66
1.4.4 Memory and 110 Peripherals Interface ........................................... 1-71
1.4.5 System DeSign Alternatives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-92
1.4.6 Multiprocessor/Coprocessor Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-97
1.4.7 Interpreting The 8086/8088 Bus Timing Diagrams ................................. 1-98
1.4.8 Wait State Insertion .........................................................1-107
1.4.9 8086/8088 Instruction Sequence ............................................ , .. 1-109
1.5 Bus Exchange Mechanisms ....................................................1-110
1.5.1 Minimum Mode (HOLD/HLDA) ................................................1-110
1.5.2 Maximum Mode (RQ*/GT*) ...................................................1-113
1.6 RESET ....................................................................1-118
1.6.1 Reset Bus Conditioning ......................................................1-118
1.6.2 Multiple Processor Considerations .............................................1-119
1.7 Interrupts ...................................................................1-120
1.7.1 Classes of Interrupts ........................................................1-120
1.7.2 Divide Error-Type 0 ........................................................1-121
1.7.3 Single Step-Type 1 ........................................................1-121
1.7.4 Non-Maskable Interrupt-Type 2 ...............................................1-121
1.7.5 One Byte Interrupt-Type 3 ...................................................1-121
1.7.6 Interrupt on Overflow-Type 4 ........................................ '......... 1-121
1.7.7 User-Defined Software Interrupts ..............................................1-122
1.7.8 User-Defined Hardware Interrupts ..............................................1-122
1.7.9 Interrupt Acknowledge .......................................................1-122
1.8 Support Components .........................................................1-125
1.8.1 8284A Clock Generator and Driver .............................................1-125
1.8.2 8288 Bus Controller .........................................................1-130
1.8.3 8289 Bus Arbiter ...........................................................1-133
1.8.4 8259A Programmable Interrupt Controller ....................................... 1-134
1.8.5 8237A Programmable DMA Controller .......................................... 1-142

Chapter 2
80186/80188 CPU
2.1 Introduction-The High Integration Concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
2.2 Component Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
2.2.1 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
2.2.2 Software Overview ....'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-4
2.3 Device Pin Definitions ......................................................... 2-12
2.3.1 Functional Description of All Signals ............................................ 2-12
2.3.2 Electrical Description of Pins .................................................. 2-12

iii

TABLE OF CONTENTS

2.4 Operating Modes ............................................................
2.4.1 8086/88·80186/188 Operating Mode Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.4.2 Queue Status Mode of Operation ............................................. ,
2.4.3 Interrupt Controller Operating Modes ...........................................
2.5 Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.5.1 HALT Bus Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.5.2 8086/80186 Bus Operation Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.5.3 Multiplexed Address/Data Bus (186,188) ........................................
2.5.4 Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.5.5 Memory and I/O Peripherals Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.5.6 Interpreting the 80186/80188 Bus Timing Diagrams ................................
2.5.7 Wait State Generator ........................................................
2.5.8 80186 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.6 Bus Exchange Mechanisms ....................................................
2.6.1 HOLD Response ...........................................................
2.6.2 HOLD/HLDA Timing and Bus Latency ..........................................
2.6.3 End of HOLD Timing ........................................................
2.7 Interrupts ...................................................................
2.8 Support Circuits .............................................................
2.8.1 Direct Memory Access (DMA) Unit .............................................
2.8.2 Timer Unit ................................................................
2.8.3 Interrupt Controller .........................................................
2.8.4 Chip Select/Wait State Generation Unit .........................................
2.8.5 Clock Generator/Reset/Ready .................................................

2·12
2·12
2·12
2·19
2·19
2·23
2·24
2·29
2·34
2·34
2·41
2·44
2·46
2·47
2·47
2·48
2·48
2·50
2·51
2·51
2·56
2·59
2·74
2·79

Chapter 3
8087 Numeric Processor Extension
3.1 Introduction.................................................................
3.1.1 iAPX86,88,186,188Base ...................................................
3.1.2 8087 Mobility In Any iAPX 86, 88, 186 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.2 Component Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.2.1 Architecture Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . ..
3.2.2 Software Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.3 Device Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.4 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.4.1 8087/8086(88) Interface ......................................................
3.4.2 8087/80186(88) Interface .....................................................
3.5 8086 (80186)/8087 Operation ...................................................
3.5.1 Decoding Escape Instructions .................................................
3.5.2 Concurrent Execution of Host and Coprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.5.3 Instruction Synchronization ...................................................
3.6 Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.6.1 iAPX86/20 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2 iAPX186/20 Bus Operation ...................................................
3.7 Bus Exchange Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.7.1 8087 RQ/GT Function .......................................................
3.7.2 Delay Effects of the 8087 .....................................................
3.7.3 Reducing 8087 Delay Effects .................................................
3.8 Interrupts...................................................................
3.8.1 Recommended Interrupt Configurations .........................................

3·1
3·1
3·2
3·3
3·3
3·7
3·8
3·8
3·11
3·11
3·12
3·12
3·13
3·13
3·15
3·15
3·15
3·16
3·16
3·17
3·19
3·22
3·22

Chapter 4
8089 Input/Output Processor
4.1 Introduction.................................................................
4.2 Component Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
iv

4·1
4·1

TABLE OF CONTENTS

4.2.1 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.2.2 Software Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.3 Device Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.4 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.4.1 Interfacing the SOS9 to the SOS6 and S01S6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.4.2 lOP Initialization ............................................................
4.4.3 Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.4.4 Direct Memory Access Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.4.5 DMA Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.4.6 Peripheral Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.4.7 Status Lines ...............................................................
4.5 Bus Operation ...............................................................
4.6 Bus Exchange Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.6.1 Bus Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.6.2 Bus Load Limit. . . . . . . . . . . . . . . . . . . . . . . . .. ..................................
4.6.3 Bus Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.7 Interrupts ...................................................................

4-1
4-3
4-20
4-20
4-24
4-26
4-27
4-30
4-32
4-33
4-34
4-34
4-36
4-37
4-39
4-39
4-40

Chapter 5
80130 Operating System Firmware
5.1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.2 S0130 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.3 Device Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.4 Operating System Primitives Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.5 Interfacing With the SOS6/SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.5.1 Programming The S0130 OSP's Onchip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.6 OSP Memory Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.7 Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1 Level-Triggered Mode .......................................................
5.7.2 Edge-Triggered Mode .......................................................
5.7.3 Local Interrupt Requests .....................................................
5.7.4 Interrupt Sequence .........................................................
5.S Timing .....................................................................

5-1
5-1
5-1
5-1
5-1
5-1
5-11
5-12
5-12
5-12
5-13
5-13
5-13

Tables
1-1
Implicit Use of General Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-7
Logical Addresses Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-10
1-2
1-3
Data Transfer Instructions ......................................................... 1-13
1-4
Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-14
1-5
Arithmetic Interpretation of S-Bit Numbers ............................................ 1-14
1-6
Bit Manipulation Instructions ....................................................... 1-15
String Instructions ............................................................... 1-15
1-7
1-S
String Instruction Register and Flag Use .............................................. 1-15
1-9
Program Transfer Instructions ...................................................... 1-16
1-10 Interpretation of Conditional Transfers ................................................ 1-17
1-11 Processor Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-17
1-12 Key to Instruction Coding Formats .................................................. 1-22
1-13 Key to Flag Effects ............................................................... 1-23
1-14 Key to Operand Types ............................................................ 1-23
1-15 Effective Address Calculation Time .................................................. 1-24
1-16 Instruction Set Reference Data ..................................................... 1-24
1-17 Single-Bit Field Encoding ......................................................... 1-42
1-1S Mode (MOD) Field Encoding ....................................................... 1-42
1-19 REG (Register) Field Encoding ..................................................... 1-42

v

TABLE OF CONTENTS

1·20
1·21
1·22
1·23
1·24
1·25
1·26
1·27
1·28
1·29
1·30
1·31
1·32
1·33
1·34
1·35
1·36
1·37
1·38
1·39
1·40
1-41
1·42
1·43
1-44
1·45
2·1
2·2
2·3
2·4
2·5
2.6
2·7
2·8
2·9
2·10
2·11
2·12
2·13
2·14
2·15
2·16
2·17
2·18
2·19
2·20
2·21
2·22
2·23
2·24
2·25
2·26
2·27
2·28
2·29
2·30

Register/Memory Field Encoding ................................................... 1·43
Key to Machine Instruction Encoding and Decoding ..................................... 1-45
8086/88 Instruction Encoding ................................. : .................... 1·46
Machine Instruction Decoding Guide ................................................ 1·52
8086/8088 Device Pin Descriptions .................................................. 1·61
D.C. Characteristics ............................................................. , 1·66
A.C. Timing Requirements for Minimum .............................................. 1·67
A.C. Timing Requirements for Maximum Complexity System .............................. 1·69
Minimum/Maximum Mode Pin Assignments ........................................... 1·71
Status Bit Decoding .............................................................. 1·71
Status Line Decoders ............................................................ 1·71
Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1·82
EPROM/ROM Parameters ......................................................... 1·82
Typical Static RAM Write Timing Parameters .......................................... 1·84
Cycle Dependent Write Parameters for RAM Memories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1·84
Peripheral Compatibility Parameters ................................................. 1·89
Peripherals Cycle Dependent Parameter Requirements .................................. 1·89
Compatible Peripherals for a 5 MHz 8086/88 .......................................... 1·90
Peripheral Requirements for Full Speed Operation with a 5MHz 8086/88 .................... 1·91
Queue Status Bit Decoding ........................................................ 1·99
Condition of 8086/88 Bus and Output Signal Pins During Reset ........................... 1·119
8288 Outputs During Passive Modes ...................... , ......................... 1·119
Interrupt Processing Timing .......................................................1·121
Status Line Decode Chart .......... , ..............................................1·131
8237A Internal Registers ..........................................................1·146
Definition of Register Codes .......................................................1·147
Data Transfer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·8
Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·8
Arithmetic Interpretation of 8·Bit Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·9
Bit Manipulation Instructions ................................ , ........... , . . . . . . . . .. 2·9
String Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. 2·10
Program Transfer Instructions ............................................ , ......... 2·10
Interpretation of Conditional Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·11
Processor Control Instructions .................................................... , 2·11
Instruction Set Summary .......................................................... 2·13
80186/80188 Device Pin Descriptions ................................................ 2·20
D.C. Characteristics ............................................................. , 2·23
A.C. Characteristics Timing Requirements ........................................
2·24
A.C. Characteristics Master Interface Timing Responses.
2·25
A.C. Characteristics Chip·Select Timing Requirements.
2·25
A.Co Characteristics CLKIN Requirements
2·26
A.C. Characteristics CLKOUT Requirements ...........
2·26
80186 Queue Status.
2·28
2·32
80186 Status Line Interpretation
Bank Selection Decoding and Word Expansion ....................
2·41
80186 Bus Signals .................
o' 2·42
80186/188 Interrupt Vectors ............
2·50
DMA Request Inactive Timing.
o' 2·57
Timer Control Block Format ....
2·57
2·65
Internal Source Priority Level ...........
80186 Interrupt Vector Types .........................
2·73
UMCS Programming Values ....
2·76
LMCS Programming Values .
2·77
MPCS Programming Values.
2·77
80186WAIT State Programming ..........
2·78
80186 Initial Register State After RESET ............................................. 2·81
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TABLE OF CONTENTS

3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
5-1
5-2
5-3
5-4
5-5

8087 Device Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Worst Case Local Bus Request Wait Times In Clocks ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical/Logical Bus Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Channel Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . ..
Instruction Set Reference Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Operand Identifiers Definitions .....................................................
Operand Type Definitions ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Instruction Fetch Timings (Clock Periods) .............................................
8089 Instruction Encoding .........................................................
8089 Machine Instruction Decoding Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
R/B/P Field Encoding .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
WB Field Encoding ..............................................................
AA Field Encoding ...............................................................
MM Field Encoding ..............................................................
8089 DIP Pin Assignments ........................................................
DMA Assembly Register Operation ..................................................
DMA Transfer Cycles .............................................................
Status Signals SO-S2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Status Signals S3-S6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Data Bus Usage .................................................................
Bus Cycle Decoding ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Type of Cycle Decoding ......................................................... ;.
Bus Arbitration Requirements and Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
80130 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
OSP Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . ..
Mnemonic Codes for Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Baud Rate Counter Values (16X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-9
3-19
4-2
4-4
4-7
4-14
4-14
4-15
4-15
4-21
4-21
4-21
4-22
4-22
4-23
4-31
4-32
4-34
4-34
4-37
4-37
4-37
4-39
5-4
5-6
5-8
5-9
5-11

Figures
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-11
1-12
1-13
1-14
1-15
1-16
1-17
1-18
1-19
1-20
1-21
1-22
1-23
1-24
1-25

Small 8088-Based System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8086/8088/8089 Multiprocessing System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8086 Simplified Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8088 Simplified Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Overlapped Instruction Fetch and Execution .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
General Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Segment Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Status Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Segment Locations in Physical Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Currently Addressable Segments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Logical and Physical Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Physical Address Generation ......................................................
Dynamic Code Relocation ........................................................ ,
Stack Operation ............................................... ; .................
Reserved Memory and I/O Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Flag Storage Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . ..
Memory Address Computation .....................................................
Direct Addressing .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Register Indirect Addressing .......................................................
Based Addressing ...............................................................
Accessing A Structure With Based Addressing .........................................
Indexed Addressing ..............................................................
Accessing an Array with Indexed Addressing ..........................................
Based Index Addressing ............................................... ; . . . . . . . . ..
Accessing a Stacked Array with Based Index Addressing ................................
vii

1-2
1-3
1-4
1-5
1-6
1-7
1-7
1-7
1-8
1-8
1-9
1-10
1-11
1-12
1-12
1-13
1-19
1-19
1-19
1-19
1-20
1-20
1-20
1-20
1-21

TABLE OF CONTENTS

1-26
1-27
1-28
1-29
1-30
1-31
1-32
1-33
1-34
1-35
1-36
1-37
1-38
1-39
1-40
1-41
1-42
1-43
1-44
1-45
1-46
1-47
1-48
1-49
1-50
1-51
1-52
1-53
1-54
1-55
1-56
1-57
1-58
1-59
1-60
1-61
1-62
1-63
1-64
1-65
1-66
1-67
1-68
1-69
1-70
1-71
1-72
1-73
1-74
1-75
1-76
1-77
1-78
1-79
1-80
1-81

String Operand Addressing .......................... ; ......... , ..... : ; ........... ,
110 Port Addressing ................................................. " ...........
Typical 8086/88 Machine Instruction Format. ...................... , ...................
Machine Instruction Encoding Matrix ................................................
8086/8088 DIP Pin Assignments ....................................................
Minimum Mode Waveforms ........................................................
Maximum Mode Waveforms .......................................................
Elementary Maximum Mode System .................................................
8086/88 Minimum Mode System ................................................ : ...
8086/88 Maximum Mode System ...................................................
8086/88 Queue Tracking Circuit ....................................................
8086/88 Lock Activity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Decoding Memory and 110 RD" and WR" Commands ...................................
Linear Select for 110 . .............................................................
Basic 8086/88 Bus Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8086 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Memory Even and Odd Data Byte Transfers .......................................... ,
Memory Even and Odd Data Word Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8086/8088 Memory Organization ............................. , .....................
Reserved Memory Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8086/8088 Memory Array .........................................................
EPROMIROM Bus Interface .......................................................
Chip Select Generation for Devices Without Output Enables. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Chip Selection for Devices With Output Enables .......................................
Sample Compatibility Analysis Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5 MHz 8086 System USing an 8202 Dynamic RAM Controller .............................
8202 Timing Information ............................................. , ............
2118 Family Timing ..............................................................
110 Device Chip Select Techniques ..................................................
16-bit to 8-bit Bus Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Bipolar PROM Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
16-bit I/O Decode ................................................................
8086 System Configurations ...................................................... ,
Device Assignment ..................................... ; . . . . . . . . . . . . . . . . . . . . . . ..
110 Input Request Code Example ................................ , ................. ,
Block Transfer to 16-bit 110 Using 8086/88 String Primitives ...............................
Block Transfer to 8-bit 110 USing 8086/88 String Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ..
Code For Block Transfers ..........................................................
Multiplexed Data Bus .............................................................
Buffered Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Devices With Output Enable on the Multiplexed Bus ....................................
Relationship of ALE to READ ......................................................
Devices Without Output Enable on the Multiplexed Bus ..................................
Access Time: CS Gated with AO"twR" ..............................................
CE TO WR" Setup and Hold ...................................................... ,
Bus Transceiver Control. ..........................................................
Devices With Output Enable on the System Bus .......................................
CS"/Bus Driving Device Timing ....................................................
De-multiplexing Address and Data From the Processor Bus ..............................
Multiplexed Bus With Local Address Oemultiplexing ................................... ,
Fully Buffered System ...................................................•.........
ContrOlling System Transceivers with DEN and OT/R" ...................................
Buffering Devices with OE"/RO" ......................................... " ..... " ..
Buffering Devices Without OE"/RO" and With Common or Separate Input/Output. ............
Buffering Devices Without OE"/RO" and With Common or Separate Input/Output .............
Buffering Devices Without OE"/RO" and With Separate Input/Output. ......................
viii

1-21
1-21
1-41
1-44
1-65
1-72
1-74
1-76
1-77
1-77
1-78
1-78
1-79
1-79
1-80
1-80
1-81
1-82
1-82
1-82
1-83
1-83
1-83
1-84
1-84
1-85
1-86
1-87
1-88
1-88
1-88
1-88
1-90
1-91
1-92
1-92
1-92
1-93
1-93
1-93
1-93
1-94
1-94
1-94
1-94
1-95
1-95
1-95
1-96
1-96
1-97
1-97
1-97
1-97
1-97
1-98

TABLE OF CONTENTS

1-82
1-83
1-84
1-85
1-86
1-87
1-88
1-89
1-90
1-91
1-92
1-93
1-94
1-95
1-96
1-97
1-98
1-99
1-100
1-101
1-102
1-103
1-104
1-105
1-106
1-107
1-108
1-109
1-110
1-111
1-112
1-113
1-114
1-115
1-116
1-117
1-118
1-119
1-120
1-121
1-122
1-123
1-124
1-125
1-126
1-127
1-128
1-129
1-130
1-131
1-132
1-133
1-134
1-135
1-136
1-137

8086 Family Multiprocessor System ................................................. 1-98
8086 Bus Timing-Minimum Mode System ........................................... 1-100
8086 Bus Timing-Maximum Mode System Using 8288) .................................1-102
Max Mode 8086 with Master 8259A on the local Bus and Slave 8259A's on the System Bus ..... 1-107
Normally Ready System Inserting a Wait State .........................................1-108
Normally Not Ready System Avoiding a Wait State ...................................... 1-108
Ready Inputs to the 8284 and Output to the 8086/88 .................................... 1-108
8284 With 8086/88 Ready Timing ................................................... 1-110
Using RDY1/RDY2 to Generate Ready ...............................................1-110
Using AEN1'/AEN2' to Generate Ready .............................................1-110
Representative Instruction Execution Sequence .......................................1-111
Instruction loop Sequence ........................................................1-111
HOlD/HlDA Sequence Timing Diagram .............................................1-112
DMA Using the 8237-2 ............................................................1-114
8086/88 Minimum System, 8257 on System Bus 16-Bit Transfers .......................... 1-115
HOlD/HlDA-to/from-RQ '/GT' Conversion Circuit. ..................................... 1-116
HOlD/HlDA-to/from-RQ'/GT' Conversion Timing .....................................1-116
Request/Grant Sequence Timing ...................................................1-117
Channel Transfer Delay Timing .....................................................1-117
Circuit to Translate HOLD into AEN Disable for Maximum Mode 8086/88 .................... 1-118
8086/88 Bus Conditioning on Reset Timing Diagram .................................... 1-119
Reset Disable for Max Mode 8086/8088 Bus Interface ................................... 1-119
Reset Disable for Max Mode 8086/88 Bus Interface in Multi-CPU System .................... 1-120
Interrupt Vector Table .............................................................1-120
Interrupt Acknowledge Timing ......................................................1-123
NMI During Single Stepping and Normal Single Step Operation ........................... 1-125
NMI, INTR, Single Step and Divide Error Simultaneous Interrupts .......................... 1-126
8284A Clock Generator/Driver Block Diagram ......................................... 1-127
8086/88 Clock Waveform ..........................................................1-127
Recommended Crystal Clock Configuration ...........................................1-127
8284A Interfaced to an 8086/88 .....................................................1-127
External Frequency for Multiple 8284's ...............................................1-128
Oscillator to ClK and ClK to PClK Timing Relationships ................................1-128
Synchronizing CSYNC With EFI ....................................................1-128
CSYNC Setup and Hold to EFI .....................................................1-128
EFI From 8284A Oscillator .........................................................1-129
Synchronizing Multiple 8284As .....................................................1-129
Buffering the 8284 ClK Output .....................................................1-129
8086 and Coprocessor on the local Bus Share a Common 8284 ........................... 1-129
8284A Reset Circuit. .............................................................1-130
Constant Current Power Up Reset Circuit. ............................................ 1-130
8086/88 Reset and System Reset. ..................................................1-130
8288 Bus Controller Block Diagram .................................................1-131
Status Line Activation and Termination ...............................................1-132
Maximum and Minimum Mode Command Timing .................•.....................1-132
8289 Bus Arbiter Block Diagram ......................................... , .......... 1-133
Parallel Priority Resolving Technique ................................................ 1-135
Higher Priority Arbiter Obtaining the Bus From a lower Priority Arbiter ...................... 1-135
Serial Priority Resolvi ng ..........................................................1-136
Typical Medium Complexity CPU Circuit ..............................................1-136
Min Mode 8086 with Master 8259A on the local Bus and Slave 8259A's on the System Bus ..... 1-137
Max Mode 8086 with Master 8259A on the local Bus and Slave 8259A's on the System Bus ..... 1-138
MCE Timing to Gate 8259A CAS Address onto the 8086 local Bus ......................... 1-138
Interrupt Vector Byte .............................................................1-139
Priority Structure Variations-Fully Nested Mode ....................................... 1-139
IR Triggering Timing Requirements ..................................................1-141
ix

TABLE OF CONTENTS

1-138
1-139
1-140
1-141
1-142
1-143
1-144
1-145
1-146
1-147
1-148
1-149
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
2-31
2-32
2-33
2-34
2-35
2c36
2-37
2-38
2-39
2-40
2-41
2-42
2-43
2-44

Cascaded 8259A's22 Interrupt Levels ....................................... , ....... 1-141
Cascade-Buffered Mode Example ...................................................1-143
8237A DMA Controller Block Diagram ...............................................1-143
Cascaded 8237As ...............................................................1-145
Memory-To-Memory Transfer Timing .................................................1-146
Command Register ..............................................................1-147
Software Command Codes ........................................................1-147
Mode Register ..................................................................1-147
Request Register ................................................................1-147
Mask Bits ......................................................................1-148
Mask Register ..................................................................1-148
Status Register .................................................................1-148
80186/80188 Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-2
ENTER Instruction Stack Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-7
Flag Store Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-8
80186/80188 DIP Pin Assignments .................................................. 2-19
Major Cycle Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
Generating Queue Status Information ................................................ 2-28
80186 and 8086 Queue Status Generation ............................................ 2-29
Example 80186 Buffered/Unbuffered Data Bus ........................................ 2"30
Read Cycle Timing .............................................................. 2-30
Generating 1/0 and Memory Read Signals ............................................ 2-31
Write Cycle Timing ............................................................... 2-31
Synthesizing Delayed Write from the 80186 ........................................... 2-32
Active-Inactive Status Transitions ................................................... 2-32
80186/8288 Bus Controller Interconnection ........................................... 2-32
Circuit Holding LOCK' Active Until Ready Is Returned .................................. 2-33
80186/8288/8289 Interconnection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
Physical Memory BytelWord Addressing .............................................. 2-35
80186/External Chip SelectlDevice Chip Select Generation .............................. 2-35
Example 2764/80186 Interface ..................................................... 2-35
Example 2186/80186 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-37
Example 8203/DRAM/80186 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 2-38
8203/2164A-15 Access Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-39
8208 Dynamic RAM Controller Interfaces ............................................. 2-40
8208 Processor Address Interfaces .................................................. 2-41
8208 Differentiated Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-42
Single T-State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-42
Example 80186 Bus Cycle ......................................................... 2-43
80186 Address Generation Timing .................................................. 2-43
Demultiplexing the 80186 Address Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-44
Valid/lnvalid ARDY Transitions ...................................................... 2-45
Asynchronous Ready Circuits for the 80186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46
Valid SRDY Transitions on the 80186 ............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-46
Valid & Invalid Latch Input Transitions & Responses ..................................... 2-47
Signal FloatlHLDA Timing ......................................................... 2-47
80186 Idle Bus HOLD/HLDA Timing ............................................... " 2-48
HOLD/HLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-49
End of HOLD Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-49
80186 CPUlDMA Channel Internal Model ............................................. 2-51
80186 DMA Register Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-52
DMA Control Register .............. ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-52
Example DMA Transfer Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. 2-53
DMA Request Timing ............................................................. 2-55
DMA Request Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-55
DMA Acknowledge Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-55

x

TABLE OF CONTENTS

2-45
2-46
2-47
2-48
2-49
2-50
2-51
2-52
2-53
2-54
2-55
2-56
2-57
2-58
2-59
2-60
2-61
2-62
2-63
2-64
2-65
2-66
2-67
2-68
2-69
2-70
2-71
2-72
2-73
2-74
2-75
2-76
2-77
2-78
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
4-1
4-2

Source & Destination Synchronized DMA Request Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-56
Timer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57
80186 Timer Out Signal ........................................................... 2-59
Example Timer Interface Code ..................................................... 2-60
80186 Real Time Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-64
80186 Baud Rate Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-64
80186 Event Counter ............................................................. 2-65
Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-65
iRMXTM 86 Interrupt Controller Interconnection ........................................ 2-66
80186 Interrupt Controller Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
INTO/INT1 Control Register Formats ................................................. 2-66
INT2/INT3 Control Register Format .................................................. 2-67
80186 Interrupt Sequencing ....................................................... 2-67
Interrupt Controller Control Register ................................................. 2-68
80186 Non-Cascaded Interrupt Connection ........................................... 2-69
Cascade and Special Fully Nested Mode Interface ...................................... 2-69
80186/8258A Interrupt Cascading ................................................... 2-70
Example Interrupt Controller Interface Code ........................................... 2-71
80186 iRMXTM 86 Mode Interface ................................................... 2-72
80186/80130 iRMXTM 86 Mode Interface ............................................. 2-72
80186 iRMXTM 86 Mode Interrupt Acknowledge Timing .................................. 2-74
80186 Cascaded Interrupt Acknowledge Timing ........................................ 2-75
80186 Memory Areas and Chip Selects .............................................. 2-75
80186 Chip Select Control Registers ................................................. 2-76
UMCS Register ................................................................. 2-77
LMCS Register. ................................................................. 2-77
MPCS Register ................................................................. 2-77
MMCS Register ................................................................. 2-78
Clock In/Clock Out Timing ......................................................... 2-79
80186 Clock Generator Block Diagram ............................................... 2-79
Recommended iAPX 186 Crystal Configuration ........................................ 2-80
80186 Crystal Connection ......................................................... 2-80
80186 Clock Generator Reset ...................................................... 2-81
Coming out of Reset ............................................................. 2-81
Submit file Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-2
8087 Numeric Data Processor Pin Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-3
Typical iAPX 86/2X Family System Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-4
Typical iAPX 186/2X Family System Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-5
Test for the Existence of an 8087. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-6
iSBC 337 MULTIMODULE Mounting Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-6
8087 Numeric Processor Extension Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-6
Non-Memory Reference Escape Instruction Form
......................................3-7
Memory Reference Escape Instruction Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-8
ESCAPE Instructions Not Used By the 8087 NPX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-8
8087 NPX-8086/88 CPU System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-11
8087 NPX-80186/188 CPU System Configuration ..................................... 3-12
Synchronizing Execution With WAIT ................................................. 3-15
Three Processor System Bus Signal Connections ...................................... 3-17
iAPX 88/21 System Configuration ................................................... 3-18
iAPX 86/22 System . . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . 3-20
SMALLBLOCK-NP)LSAVE ..................................................... 3-21
SMALLBLOCK-NP)LRESTORE ................................................. 3-21
NP)LCLEAN Code Example ...................................................... 3-22
Inhibit/Enable 8087 Interrupts ...................................................... 3-23
8089 Simplified Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-2
Channel Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
xi

TABLE OF CONTENTS

4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
5-1
5-2
5-3
5-4
5-5

Register Operands in MOV Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-5
Register Operands in Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
Register Operands in Logical Instructions............................... , . . . . . . . . . . . .. .4-6
Typical 8089 Machine Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
80891/0 Processor Pinout Diagram ................................................. 4-22
Command Communication Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-24
CPU/lOP Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. 4-24
iAPX 86/11,88/11 Configuration with 8089 in Local Mode .......... " .................... 4-25
Typical 8089 Remote Configuration ................................................ " 4-26
RESET-CA Initialization Timing ..............................•...................... 4-27
Channel Attention Decoding Circuit ................................................. 4-28
Channel Command Word Encoding ................................................. 4-28
Channel Commands ............................................................. 4-29
Channel State Save Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . .. 4-30
Source Synchronized Transfer Cycle ..................... : ........................... 4-31
Destination Synchronized Transfer Cycle ............................................. 4-32
Read Bus Cycle (8-bit Bus) ........................................................ 4-35
Write Bus Cycle (16-bit Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-36
Wait State Timing ................................................................ 4-38
Program Status Word ....................... . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. 4-40
80130 Simplified Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . .. 5-2
80130 OSP Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-3
OSP Typical Configuration With An 8086 .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . . .. 5-10
80130 OSP Timing Diagram ....................................................... 5-14
High-Speed Address Decoding Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. 5-15

xii

808618088 CPU

1

CHAPTER 1
8086/8088 CPU
In the "minimum mode," the CPU is configured for
small, single-processor systems. In this configuration all
control signals are provided by the CPU and the dual
function pins transfer signals directly to memory and
input/output devices.

1.1 INTRODUCTION
This chapter contains specific hardware design information on the operation and functions of INTEL's 8086/8088
Central Processing Units (CPUs). This information consists of a component overview of the 8086/88 microprocessors presenting architectural and software
considerations, individual device pin functional and electrical signal definitions, a detailed description of the minimum and maximum operating modes, detailed
descriptions of the operation of the address and data
buses, an explanation of the protocols supported for local
bus transfers to other devices, and a detailed description
of interrupt operation. In addition, descriptions of the various 8086/88 family support circuits and their circuit
functions appear at the end of the chapter. For more specific information of any of the 8086 family support circuits, refer to the Microsystem Components Handbook
(Order Number: 230843-002).

In the "maximum mode" these same pins take on different functions that are helpful in medium to large systems,
especially systems with multiple processors. An Intel
8288 Bus Controller is used to provide the control signal
outputs. This allows several of the device pins previously
delegated to these control functions to be redefined in order to support multiprocessing applications. A detailed
description of this feature is presented later in the chapter.
The 8086 and 8088 Microprocessors are designed to operate with the 8089 Input/Output Processor (lOP) and
other processors in multiprocessing and distributed processing systems. When used in conjunction with one or
more 8089s, the 8086 and 8088 expand the applicability
of microprocessors into lIO-intensive data processing systems. Built-in coordinating signals and instructions, and
electrical compatibility with Intel's MULTIBUS® shared
bus architecture, simplify and reduce the cost of developing multiple-processor designs.

1.2 COMPONENT OVERVIEW
The 8086 and 8088 are closely related third-generation
microprocessors. Both CPU's contain a 20-bit address
bus (1 mega-byte of address space) and utilize an identical
instruction/function format. Differences between the two
devices consist essentially of their respective data bus
widths. The 8088 is designed with an 8-bit external data
path to memory and lIO, while the 8086 can transfer 16
bits at a time. In almost every other respect the processors
are identical; software written for one CPU will execute
on the other without alteration. Both chips are contained
in standard 40-pin dual in-line packages and operate from
a single + 5V power source. Except where expressly
noted, the descriptions contained in this chapter are applicable to both microprocessors.

Both the 8086 and 8088 are substantually more powerful
than any microprocessor previously offered by Intel. Actual performance, of course, varies from application to
application, but comparisons to the industry standard
2-MHz 8080A are instructive. The 8088 is from four to
six times more powerful than the 8080A; the 8086 provides seven to ten times the 8080Xs performance.
The 8086's advantage over the 8088 is the result of the
8086's 16-bit external data bus. In applications that manipulate 8-bit quantities extensively, or that are
execution-bound, the 8088 can approach to within 10%
of the 8086's processing throughput.

The 8086 and 8088 Microprocessors can be used for a
wide spectrum of microcomputer applications. This flexibility is one of their most outstanding characteristics. Systems can range from small uniprocessor minimal-memory
designs implemented with a few chips (see Figure 1-1), to
multiprocessor systems with up to a megabyte of memory
(see Figure 1-2).

The improved performance of the 8086 and 8088 is accomplished by combining a l6-bit internal data path with
a pipelined architecture that allows instructions to be prefetched during spare bus cycles. In addition, a compact
instruction format that enables more instructions to be
fetched in a given amount of time contributes to this high
performance.

Both the 8086 and 8088 microprocessors use a combined,
or "time-multiplexed", address and data bus that permits
several of the device pins to serve dual functions. Some
microprocessor control pins also serve dual functions.
These pins are defined according to the strapping of a
single input pin (the MN/MX* pin). This feature provides
configuration of the CPU's in either "minimum mode" or
"maximum mode" circuits.

Software for 8086 and 8088 systems does not need to be
written in assembly language. The CPUs are designed to
provide direct hardware support for programs written in
high-level languages such as Intel's PLlM-86. Most
high-level languages store variables in memory; the
8086/8088 symmetrical instruction set supports direct operation on memory operands, including operands on the
1-1

210912·001

8086/8088 CPU

..

...

...

l..t

.1..
8155

4

•

RAM
I/O

TIMER

•
ADDRESS

8088

~

CPU

CONTROl.

•

.

4ADDRESS/DATA

,...

~
~

PORT B

PORTe

-______
} C l OTIMER
CK

,.

..

•
•

I>

•
•

~

PORT A

I~

r

8755A
EPROM

~

PORT A

~

PORTS

I/O

•

•

I>

r-- '--

r

4

8284
CLOCK

•

GEN.

,..

'---

8185
1K XB

RAM

•

...

... ""

""

Figure 1·1 Small8088·8ased System
the 8086 the BID incorporates a 16-bit data bus and a
6-byte instruction queue. In the 8088 the BID incorporates an 8-bit data bus and a 4-byte instruction queue.

stack. The hardware addressing modes provide efficient,
straightforward implementations of based variables, arrays, arrays of structures and other high-level language
data constructs. A powerful set of memory-to-memory
string operations is available for efficient character data
manipulation. Finally, routines with critical performance
requirements that cannot be met with PLlM-86 may be
written in ASM-86 (the 8086/8088 assembly language)
and linked with PLlM-86 code.

The EU executes instructions and the BIU fetches instructions, reads operands and writes results. The two units can
operate independently of one another and are able, under
most circumstances, to extensively overlap instruction
fetch with execution. The result is that, in most cases, the
time normally required to fetch instructions "disappears"
because the EU executes instructions that have already
been fetched by the BID. Figure 1-5 illustrates this overlap and compares it with traditional microprocessor operation. In the example, overlapping reduces the elapsed
time required to execute three instructions, and allows two
additional instructions to be prefetched as well.

Although the 8086 and 8088 Microprocessors are totally
new designs, they make the most of user's existing investments in systems designed around the 8080/8085 microprocessors. Many of the standard Intel memory,
peripheral control and communication chips are compatible with the 8086 and the 8088. Software is developed in
the familiar Intellec Microcomputer Development System
environment, and most existing programs, whether written in ASM-80 or PLlM-80, can be directly converted to
run on the 8086 and 8088.

In the 8086 CPU, when two or more bytes of the 6-byte
instruction queue are empty and the EU does not require
the BIU to perform a bus cycle, the BIU executes instruction fetch cycles to refill the queue. In the 8088 CPU,
when one byte of the 4-byte instruction queue is err-pty.
the BID executes an instruction fetCh cycle. Note that
since the 8086 CPU has a 16-bit data bus, it can access
two instruction object code bytes in a single bus cycle.
Since the 8088 CPU has an 8-bit data bus, it accesses one
instruction object code byte per bus cycle. If the EU

1.2.1 Architectural Overview
Both the 8086 and 8088 microprocessors incorporate two
separate processing units (see Figures 1-3 and 1-4). These
are the Execution Unit (EU) and the Bus Interface Unit
(BID). Both microprocessors contain identical EU's. In
1-2

210912'()01

8086/8088 CPU

Figure 1·2 8086/8088/8089 Multiprocessing System

empty when the EU is ready to fetch an instruction byte,
the EU waits for the instruction byte to be fetched. If a
memory location or I/O port must be accessed during the
execution of an instruction, the EU requests the BIU to
perform the required bus cycle.

issues a request for bus access while the BIU is in the
process of an instruction fetch bus cycle, the BIU completes the cycle before honoring the EU's request.

EXECUTION UNIT

The execution units (EU's) of the 8086 and 8088 are identical (see Figures 1-3 and 1-4). The EU is responsible for
the execution of all instructions, for providing data and
addresses to the BIU, and for manipulating the general
registers and the flag register. A 16-bit arithmetic/logic
unit (ALU) in the EU maintains the CPU status and control flags, and manipulates the general registers and instruction operands. All registers and data paths in the EU
are 16 bits wide for fast internal transfers.

BUS INTERFACE UNIT

The 8086 and 8088 BIU's are functionally identical, but
are implemented differently to match the structure and
performance characteristics of their respective buses.
Data is transferred between the CPU and memory or I/O
devices upon demand from the EU. The BIU executes all
external bus cycles. This unit consists of the segment and
communications registers, the instruction pointer and the
instruction object code queue. The BIU combines segment and offset values in a dedicated adder to derive
20-bit addresses, transfers data to and from the EU on the
AL U data bus and loads or "prefetches" instructions into
the queue. These "prefetched" instructions can then be
fetched by the EU with a minimum of wait.

The EU has no connection to the system bus, the "outside
world." It obtains instructions from a queue maintained
by the BIU. Likewise, when an instruction requires access to memory or to a peripheral device, the EU requests
the BIU to obtain and store the data. All addresses manipulated by the EU are 16 bits wide. The BIU, however,
performs an address relocation that gives the EU access to
the full megabyte of memory space.

During periods when the EU is busy executing instructions, the BIU "looks ahead" and fetches more instructions from memory. These instructions are stored in an
internal RAM array called the instruction stream queu-:.
The 8088 instruction queue holds up to four bytes of the
instruction stream, while the 8086 queue can store up to

When the EU is ready to execute an instruction, it fetches
the instruction object code byte from the BIU's instruction
queue and then executes the instruction. If the queue is
1-3

210912·001

8086/8088 CPU

AH

Al

CH

Cl

Bl

GENERAL

REGISTERS

DATA BUS

SP

(16 BITS)

BP
CS
SI
OS

INTERNAL
ALU DATA BUS

COMMUNICATIONS
REGISTERS

BUS
CONTROL

LOGIC

(1& BITSI

EXECUTION UNIT

(EUI

808&

BUS

BUS INTERFACE UNIT
(Btu)

Figure 1-3 8086 Simplified Functional Block Diagram
requests a memory or 110 read or write (except that a
fetch already in progress is completed before executing
the EU's bus request).

six instruction bytes. These queue sizes allow the BIU to
keep the EU supplied with pre fetched instructions under
most conditions without monopolizing the system bus.
The 8088 BIU fetches another instruction byte whenever
one byte in its queue is empty and there is no active request for bus access from the EU. The 8086 BIU operates
similarly except that it does not initiate a fetch until there
are two empty bytes in its queue. The 8086 BIU normally
obtains two instruction bytes per fetch. If a program
transfer forces fetching from an odd address, the 8086
automatically reads one byte from the odd address and
then resumes fetching two-byte words from the subsequent even addresses.

GENERAL REGISTERS

Both CPU's have the same complement of eight 16-bit
general registers (see Figure 1-6). The general registers
are subdivided into two sets of four registers each. These
are the data registers (sometimes called the H & L group
for "high" and "low"), and the pointer and index registers (sometimes called the P & I group).
The data registers are unique in that their upper (high) and
lower halves are separately addressable. This means that
each data register can be used interchangeably as a 16-bit
register, or as a two 8-bit registers. The other CPU registers are always accessed as 16-bit only. The data registers
can be· used without constraint in most arithmetic and
logic operations. In addition, some instructions use cere
tain registers implicitly (see Table 1-1), therefore allowing compact yet powerful encoding.

In most circumstances the queues contain at least one byte
of the instruction stream and the EU does not have to wait
for instructions to be fetched. The instructions in the
queue are those stored in memory locations immediately
adjacent to and higher than the instruction currently being
executed. That is, they are the next logical instructions so
long as execution proceeds serially. If the EU executes an
instruction that transfers control to another location, the
BIU resets the queue, fetches the instruction from the new
address, passes it immediately to the EU, and then begins
refilling the queue from the new location. In addition, the
BIU suspends instruction fetching whenever the EU

The pointer and index registers can also be used in most
arithmetic and logic operations. All eight general registers fit the definition of an "accumulator" as defined in
1-4

210912-001

8086/8088 CPU

AH

AL

BL
CH

GENERAL
REGISTERS

OH

OL
DATA SUS
(6 BITS)

BP

01

CS

51

os
ss
ES

INTERNAL
COMMUNICATIONS
REGISTERS

BUS

CONTROL
LOGIC

sus INTERFACE

8088
BUS

UNIT

(BIU)

Figure 1-4 8088 Simplified Functional Block Diagram
INSTRUCTION POINTER

first and second generation microprocessors. The P & I
registers (except for BP) are also used implicitly in some
instructions (see Table I-I).

The 16-bit instruction pointer (IP) is similar to the program counter (PC) in the 8080/8085 CPUs. The instruction pointer is updated by the BIU so that it contains the
offset (distance in bytes) of the next instruction from the
beginning of the current code segment; i.e., IP points to
the next instruction. During normal execution, IP contains the offset of the next instruction to be fetched by the
BIU. Whenever IP is saved on the stack, however, it is
first automatically adjusted to point to the next instruction
to be executed. Programs do not have direct access to the
instruction pointer, but instructions cause it to change and
to be saved on and restored from the stack.

SEGMENT REGISTERS

The 8086 and 8088 memory space (up to one megabyte) is
divided into logical segments of up to 64k bytes each. The
CPU has direct access to four segments at a time. The
base addresses (starting locations) of these memory segments are contained in the segment registers (see Figure
1-7). The CS register points to the current code segment.
Instructions are fetched from the CS segment. The SS
register points to the current stack segment. Stack operations are performed on locations in the SS segment. The
DS register points to the current data segment. The DS
register generally contains program variables. The ES
register points to the current extra segment, which also is
typically used for data storage.

FLAGS
The 8086 and 8088 have six I-bit status flags (see Figure
1-8) that the EU posts to reflect certain properties of the
result of an arithmetic or logic operation. A group of instructions is available that allows a program to alter its
execution depending on the state of these flags, i.e., on
the result of a prior operation. Different instructions affect the status flags differently; in general, however, the
flags reflect the following conditions:

The segment registers are accessable to programs and can
be manipulated with several instructions. Good programming practice and consideration of compatibility with future Intel hardware and software products dictate that the
segment registers be used in a disciplined fashion.
1-5

210912-001

8086/8088 CPU

~------------------------ELASPEDTIME------------------------~.~

{ "" l\~J~'&'(~

SECOND
GENERATION
MICROPROCESSOR

BUS:

EU:

~~~~1J~~

t~1~~ ~ft9}] ~~~§fJj 1\:~!~i~:~\\1

lEI

1\~~~R:~~~il

a a

a a

I :~~ff8~~~: il

EffX?YX~~

8086/8088
MICROPROCESSOR

-

INSTRUCTION STREAM
1st INSTRUCTION (ALREADY FETCHED):
EXECUTE AND WRITE RESULT

I II
III

2nd INSTRUCTION:
EXECUTE ONLY

III

4th INSTRUCTION:
(UNDEFINED)

III

5th INSTRUCTION:
(UNDEFINED)

3.d INSTRUCTION:
READ OPERAND AND EXECUTE

Figure 1-5 Overlapped Instruction Fetch and Execution
1. If AF (the auxiliary flag) is set, there has been a carry
out of the low nibble into the high nibble or a borrow
from the high from the high nibble into the low nibble
of an 8-bit quantity (low-order byte of a 16-bit
quantity). This flag is used by decimal arithmetic instructions.

its destination location. An Interrupt On Overflow instruction is available that will generate an interrupt in
this situation.
4. If SF (the sign flag) is set, the high-order bit of the
result is a 1. Since negative binary numbers are represented in the 8086 and 8088 in standard two's complement notation, SF indicates the sign of the result
(0 =positive, 1 =negative).

2. If CF (the carry flag) is set, there has been a carry out
of, or a borrow into, the high-order bit of the result
(8-or 16- bit). The flag is used by instructions that add
and subtract multibyte numbers. Rotate instructions
can also isolate a bit in memory or a register by placing it in the carry flag.

5. If the PF (the parity flag) is set, the result has even
parity, an even number of I-bits. This flag can be used
to check for data transmission errors.
6. If ZF (the zero flag) is set, the result of the operation
is O.

3. If OF (the overflow flag) is set, an arithmetic overflow
has occurred; that is, a significant digit has been lost
because the size of the result exceeded the capacity of

Three additional control flags (see Figure 1-8) can be set
and cleared by programs to alter processor operations:
1-6

210912-001

8086/8088 CPU

I

15

H

I - - AH

-

~ -Ai: - BX

I- - B H DATA {
GROUP

m

I

8 7

-r -

IiL. - -

ACCUMULATOR

I----~---CH
CL

COUNT

1--6H-~-DL--

DATA

15

F

BASE

AUXILIARY CARRY

' - - - - - - - ZERO

' - - - - - - - - - SIGN

0

POINTER {
AND
INDEX
GROUP

'----------OVERFLOW

SP

STACK
POINTER

BP

BASE
POINTER

SI

SOURCE
I NDEX

01

DESTINATION
INDEX

'-----------INTERRUPT-ENABLE

'--------------OIRECTlON

'---------------TRAP

Figure 1-8 Status Flags
1. Setting DF (the direction flag) causes string instructions to auto-decrement; that is, to process strings
from the high address to the low address, or from
"right to left." Clearing DF causes string instructions
to auto-increment, or process strings from "left to
right."

Figure 1-6 General Registers

15
CS

CODE
SEGMENT

OS

DATA
SEGMENT

SS

STACK
SEGMENT

ES

EXTRA
SEGMENT

2. Setting IF (the interrupt-enable flag) allows the CPU
to recognize external (maskable) interrupt requests.
Clearing IF disables these interrupts. IF has no affect
on either non- maskable external or internally generated interrupts.
3. Setting TF (the trap flag) puts the processor into
single-step mode for debugging. In this mode, the
CPU automatically generates an internal interrupt after each instruction, allowing a program to be inspected as it executes instruction by instruction.

Figure 1-7 Segment Registers
Table 1-1 Implicit Use of General Registers

MODE SELECTION
Each of the processors has a strap pin (MN/MX*) that
defines the function of eight CPU pins in the 8086 and
nine pins in the 8088. Connecting MN/MX* to + 5V
places the CPU in minimum mode. This configuration is
designed for small systems (roughly one or two boards)
and the CPU provides bus control signals needed by
memory and peripherals. When MN/MX* is strapped to
ground, the CPU is configured in maximum mode. In this
configuration the CPU encodes control signals on three
lines. An 8288 Bus Controller is added to decode the signals for the rest of the system. The CPU uses the remaining free lines for a new set of signals designed to help
coordinate the activities of other processors in the system.

OPERATIONS

REGISTER

B~CARRY
~PARITY

AX

Word Multiply, Word Divide,
Word 1/0

AL

Byte Multiply, Byte Divide, Byte
1/0, Translate, Decimal Arithmetic

AH

Byte Multiply, Byte Divide

BX

Translate

CX

String Operations, Loops

CL

Variable Shift and Rotate

OX

Word Multiply, Word Divide,
Indirect 1/0

SP

Stack Operations

SI

String Operations

01

String Operations

SEGMENTATION
Programs for the 8086 and 8088 "view" the memory
space (one megabyte) as a group of segments that are defined by application. A segment is a logical unit of memory that may be up to 64k bytes long. Each segment is
made up of contiguous memory locations and is an independent, separately-addressable unit. Every segment is
1-7

210912-001

8086/8088 CPU

FULLY

OVERLAPP~D1SEGMENT 0
PARTLY

•

OVERLAP~I

CONTIGUOUS~~

-!

SEGMENTC

1- j
I

I

1 SEGMENTB

SEGMENT A

I

I

DISJOINT
LOGICAL
SEGMENTS

SEGMENT E

I

-+1___-+-1___-+1___--..17 }~~S~~~L

""1_ _ _

t

t

OH

10000H

t

t

20000H

30000H

Figure 1·9 Segment Locations in Physical memory

assigned (by software) a base address, which is its starting
location in the memory space. All segments begin on
16-byte memory boundaries. There are no other restrictions on segment locations. Segments may be adjacent,
disjoint, partially overlapped, or fully overlapped (see
Figure 1-9). A physical memory location may be mapped
into (contained in) one or more logical segments.

Every application will define and use segments differently. The currently addressable segments provide a generous work space; 64k bytes for code, a 64k byte stack
and 128k bytes of data storage. Many applications can be
written to simply initialize the segment registers and then
forget them. Larger applications should be designed with
careful consideration given to segment definition.

The segment registers point to (contain the base address
values of) the four currently addressable segments (see
Figure 1-10). Programs obtain access to code and data in
other segments by changing the segment registers to point
to the desired segments.

The segment structure of the 8086/8088 memory space
supports modular software design by discouraging huge,
monolithic programs. The segments also can be used to
advantage in many programming situation. Thke, for example, the case of an editor for several on-line terminals.
A 64k test buffer (probably an extra segment) could be
assigned to each terminal. A single program could maintain all the buffers by simply changing register ES to point
to the buffer of the terminal requiring service.

FFFFFH

PHYSICAL ADDRESS GENERATION
DATA:

os:

CODE:

CS:

I
I

STACK: SS:

I

EXTRA: ES:

I

B

H

/--1---,
1-, I

I I
I
I II
I
I L
I

h

In theory, it is useful to think of every memory location as
having two kinds of addresses, physical and logical. A
physical address is the 20-bit value that uniquely identifies each byte location in the megabyte memory space.
Physical addresses range from OR to FFFFFH. All exchanges between the CPU and memory components use
this physical address.

D

-: 8

Programs deal with logical, rather than physical addresses and allow code to be developed without prior
knowledge of where the code is to be located in memory
an facilitate dynamic management of memory resources.
A logical address consists of a segment base value and an
offset value. For any given memory location, the segment
base value locates the first byte of the containing segment
and the offset value is the distance, in bytes, of the target
location from the beginning of the segment. Segment base
and offset values are unsigned 16-bit quantities. The
lowest-addressed byte in a segment has an offset of O.
Many different logical addresses can map to the same

L_

OH

Figure 1·10 Currently Addressable Segments

1·8

210912·001

8086/8088 CPU

r
PHYSICAL
ADDRESS

2 C4H

.

t
OFFSET

r

2 C3H
2 C2H

(3H)

SEGMENT
BASE

'r

2 C1H

.. I

2 COH
2 BFH
2 BEH
2 BDH
2 BCH
2 BBH

LOGICAL
ADDRESSES

...

2 BAH

OFFSET
(13H)

2 B9H
2 B8H
2 B7H
2 B6H
2 B5H
2 B4H
2 B3H
2 B2H
2 B1H

'- SEGMENT
BASE

2 BOH

"

"

Figure 1-11 Logical and Physical Addresses

physical location. In the example (see Figure 1-11) physical memory location 2C3H is contained in two different
overlapping segments, one beginning at 2BOH and the
other at 2COH.

a memory variable is calculated by the EU. This calculation is based on the addressing mode specified in the instruction; the result is called the operand's effective
address (EA).

Whenever the BIU accesses memory -to fetch an instruction or to obtain or store a variable -it generates a physical
address from a logical address. This is done by shifting
the segment base value four bit positions and adding the
offset as illustrated in Figure 1-12. Note that this addition
process provides for modulo 64k addressing (addresses
wrap around from the end of a segment to the beginning
of the same segment).

Strings are addressed differently than other variables. The
source operand of a string instruction is assumed to lie in
the current data segment, but another currently addressable segment may be specified. Its offset is taken from
register SI, the source index register. The destination operand of a string instruction always resides in the current
extra segment; its offset is taken from 01, the destination
index register. The string instructions automatically adjust SI and DI as they process the strings one byte or word
at a time.

The BIU obtains the logical address of a memory location
from different sources, depending on the type of reference that is being made (see Table 1-2). Instructions are
always fetched from the current code segment; IP contains the offset of the target instruction from the beginning of the segment. Stack instructions always operate on
the current stack segment; SP contains the offset of the
top of the stack. Most variables (memory operands) are
assumed to reside in the current data segment, although a
program can instruct the BIU to access a variable in one
of the other currently addressable segments. The offset of

When register BP, the base pointer register, is designated
as a base register in an instruction, the variable is assumed
to reside in the current stack segment. Therefore, register
BP provides a convenient way to address data on the
stack. However, BP can also be used to access data in any
of the other currently addressable segments.
The BIU's segment assumptions are a convenience to programmers in most cases. However, it is possible for a programmer to explicitly direct the BIU to access a variable
in any of the currently addressable segments. (The only

1-9

210912-001

8086/8088 CPU

rlFTLEFT 4 BITS

·,-1------~-4~!~0~1
~;9~------t,..........· ~O

I

+

0

o

2

2

2

0 0 2 2

II....------l

,OFFSET

0

o

I~19:-----r+---!0I
1

1 2 3 4

15

t

15

I
U~~~ENT}
~15~--------~0
~~g~E~~
I

6

2

PHYSICAL ADDRESS

TO MEMORY

Figure 1·12 Physical Address Generation

other words, all offsets in the program must be relative to
fixed values contained in the segment registers. This allows the program to be moved anywhere in memory as
long as the segment registers are updated to point to the
new base addresses.

exception is the destination operand of a string instruction
which must be an extra segment.) This is done by preceding an instruction with a segment override prefix. This
one-byte machine instruction tells the BID which segment
register to use to access a variable referenced in the following instruction.

STACK IMPLEMENTATION
DYNAMICALLY RELOCATABLE CODE

Stacks in the 8086 and 8088 are implemented in memory
and are located by the stack segment register (SS) and the
stack pointer (SP). A system may have an unlimited number of stacks, and a stack may be up to 64k bytes long, the
maximum length of a segment. (An attempt to expand a
stack beyond 64k bytes overwrites the beginning of the
segment.) One stack is directly addressable at a time; this
is the current stack, often referred to simply as "the"
stack. SS contains the base address of the current stack
and SP points to the top of stack (IDS). In other words,
SP contains the offset of the top of the stack from the
stack segment's base address. However, the stack's base
address (contained in SS) is not the "bottom" of the stack.

The segmented memory structure of the 8086 and 8088
makes it possible to write programs that are
position-independent, or dynamically relocatable. Dynamic relocation allows a multiprogramming or multitasking system to make particularly effective use of
available memory. Inactive programs can be written to
disk and the space they occupied allocated programs. If a
disk-resident program is needed later, it can be read back
into any available memory location and restarted. Similarly, if a program needs a large contiguous block of storage, and the total amount is only available in non-adjacent
fragments, other program segments can be compacted to
free up a continuous space. This process is illustrated
graphically in Figure 1-13.

Stacks in the 8086 and 8088 are 16 bits wide; instructions
that operate on a stack add and remove stack items one
word at a time. An item is pushed onto the stack (see
Figure 1-14) by decrementing SP by 2 and writing the
item at a new IDS. An item is popped off the stack by

To be dynamically relocatable, a program must not load
or alter its segment registers and must not transfer directly to a location outside the current code segment. In

Table 1·2 Logical Addresses Sources

TYPE OF MEMORY REFERENCE

Instruction Fetch
Stack Operation
Variable (except following)
String Source
String Destination
BP Used As Base Register

DEFAULT
SEGMENT
BASE

ALTERNATE
SEGMENT
BASE

OFFSET

CS
SS
DS
DS
ES
SS

NONE
NONE
CS,ES,SS
CS,ES,SS
NONE
CS,DS,ES

IP
SP
Effective Address
SI
DI
Effective Address

1-10

210912-001

8086/8088 CPU

AFTER RELOCATION

BEFORE RELOCATION

CODE
SEGMENT

I
STACK
SEGMENT

CS

CS

J

-

,.....

SS

SS

DS

DS

ES

ES

CODE
SEGMENT
STACK
SEGMENT
DATA
SEGMENT
EXTRA
SEGMENT

DATA
SEGMENT

EXTRA
SEGEMENT

r::::::J

FREE SPACE

Figure 1-13 Dynamic Code Relocation

copying it from 'IDS and the incrementing SP by 2. In
other words, the stack goes down in memory toward its
base address. Stack operations never move items on the
stack, nor do they erase them. The top of the stack
changes only as a result of updating the stack pointer.

accesses the complete word in one bus cycle. If the word
is located at an odd-numbered address, the 8086 accesses
the word one byte at a time in two consecutive bus cycles.
To maximize throughput in 8086-based systems, 16-bit
data should be stored at even addresses (should be
word-aligned). This is particularly true of stacks. Unaligned stacks can slow a system's response to interrupts.
Nevertheless, except for the performance penalty,
word alignment is totally transparent to software. This
allows maximum data packing where memory space is
constrained.

RESERVED MEMORY

Two areas in extreme low and high memory (see Figure
1-15) are dedicated to specific processor functions or are
reserved by Intel Corporation for use by Intel hardware
and software products. The locations are OH through 7FH
(128 bytes) and FFFFOH through FFFFFH (16 bytes).
These areas are used for interrupt and system reset processing. 8086 and 8088 application systems do not use
these areas for any other purpose. Doing so may make
these systems incompatible with future Intel products.

The 8086 always fetches the instruction stream in words
from even addresses except that the first fetch after a program transfer to an odd address obtains a byte. The instruction stream is disassembled inside the processor and
instruction alignment will not materially affect the performance of most systems.

8086/8088 MEMORY ACCESS DIFFERENCES

The 8088 always accesses memory in bytes. Word operands are accessed in two bus cycles regardless of their
alignment. Instructions are also fetched one byte at a
time. Although alignment of word operands does not

The 8086 can access either 8 or 16 bits of memory at a
time. If an instruction refers to a word variable and that
variable is located at an even-numbered address, the 8086
1-11

210912-001

8086/8088 CPU

POPAX
POPBX
PUSH AX
EXISTING
STACK

AX'12134

~

1062

00

11

1060

22

33

105E

44

55

105B

66

77

105A

88

99

TOS
:...::..::-. 1058 AA BB
1056

r

01

23

1054 45

67

1052 89

AB

1050; CD; EF

I'"

00

11

1060

22

33

105E

44

55

~(I)

105B

66

77

0'"
0>0

105A

88

99

:1;0
~~

r
~O

~~
ffl(l)

1058

AA

BB

~1056

34

12

1054

45

67

1052

89

AB

r

a:w
a..:I:

~~

1-1
I
I

1062

0«

I 34 1-,
I
BX' BB IAA
I

AX '12

I
I

11

1060

22

33

lOSE

44

55

105C 66

~105A

r

1050; CD; EF

00

1062

f.J

'-1

77

88

99

105B AA

BB

1056

12

34

I
I
I
I

1054

45

67

1052

89

AB

J

I
I
I
I
I
I

_--1

1050; CD; EF

10

50 , SS

10

50 'SS

10

50 , SS

00

I 08 I SP

00

061 SP

00

I OA I SP

STACK OPERATION FOR CODE SEQUENCE
PUSH AX
POPAX
POPBX

Figure 1·14 Stack Operation
affect the performance of 8088, locating 16-bit data on
even addresses will insure maximum throughput if the
system is ever transferred to an 8086.

1.2.2 Software Overview
The 8086 and 8088 execute exactly the same instructions.
This instruction set includes equivalents to the instructions typically found in previous microprocessors, such as
the 8080/8085. Significant new operations include:

FFFFFH
RESERVED
FFFFCH
FFFFBH
DEDICATED

•

multiplication and division of signed and unsigned binary numbers as well as unpacked decimal numbers,

•

move, scan and compare operations for strings up to
64k bytes in length,

•

non-destructive bit testing,

•

byte translation from one code to another,

•

software generated interrupts,

FFFFOH
FFFEFH

OPEN

.,

I
,

[FFH

OPEN

• a group of instructions that can help coordinate the
activities of multiprocessing systems.

BOH
7FH
RESERVED
14H
13H

RESERVED

The following paragraphs provide a description of the instructions by category and a detailed discussion of the
various operand addressing modes. In addition, a complete instruction set summary is provided in tabular form
which recaps each device instruction by category, and
provides timing cycles for each instruction. Information
is also described on how to encode and decode machine
instructions for any given assembly code instructioh.

OPEN

DEDICATED

OH

OH
MEMORY

100H
FFH
FBH
F7H

liD

Figure 1·15 Reserved Memory and 110 Locations
1-12

210912·001

8086/8088 CPU

Table 1-3 Data Transfer Instructions

8086/8088 INSTRUCTION SET
The 8086/8088 instructions treat different types of operands uniformly. Nearly every instruction can operate on
either byte or word data. Register, memory and immediate operands may be specified interchangeably in most
instructions. The exception to this is that immediate values serve as "source" and not "destination" operands. In
particular, memory variables may be added to, subtracted
from, shifted, compared, and so on, in place, without
moving them in and out of registers. This saves instructions, registers, and execution time in assembly language
programs. In high-level languages, where most variables
are memory based, compilers can produce faster and
shorter object programs.

GENERAL PURPOSE
MOV
PUSH
POP
XCHG
XLAT

Move byte or word
Push word onto stack
Pop word off stack
Exchange byte or word
Translate byte
INPUT /OUTPUT

IN
OUT

Input byte or word
Output byte or word
ADDRESS OBJECT

The 8086/8088 instruction set can be viewed as existing
on two levels. One is the assembly level and the other is
the machine level. To the assembly language programmer, the 8086/8088 appear to have a repertoire of about
100 instructions. One MOV (move) instruction, for example, transfers a byte or a word from a register or a memory location or an immediate value to either a register or a
memory location. The 8086/8088 CPU's, however, recognize 28 different MOV machine instructions ("move
byte register to memory," move word immediate to register," etc.).

LEA
LDS
LES

Load effective address
Load pointer using DS
Load pointer using ES
FLAG TRANSFER

LAHF
SAHF
PUSHF
POPF

The two levels of instruction set address two different requirements: efficiency and simplicity. The approximately
300 forms of machine-level instructions make very efficient use of storage. For example, the machine instructions that increments a memory operand is three or four
bytes long because the address of the operand must be
encoded in the instruction. To increment a register, however, does not require as much information, so the instruction can be shorter. The 8086/88 have eight different
machine-level instructions that increment a different
16-bit register. Each of these instructions are only one
byte long.

Load AH register from flags
Store AH register in flags
Push flags onto stack
Pop flags off stack

Data transfer instructions are categorized into four types:
1) general purpose; 2) input/output; 3) address object;
and 4) flag transfer. The stack manipulation instructions,
which are used for transferring flag contents, and the instructions for loading segment registers are also included
in this group. Figure 1-16 shows the flag storage formats.
These formats are used primarily by the LAHF instruction

~:~~'

The assembly level instructions simplify the programmers
view of the instruction set. The programmer writes one
form of an INC (increment) instruction and the ASM-86
assembler examines the operand to determine which machine level instruction to generate. The following paragraphs provide a functional description of the
assembly-level instructions.

I

Z ! U !A! U ! P! U!C
1765432101

Is!

1_8080/8085 FLAGS_I

1

1

I

~g~~F, I u , U

I

U , U ,0,0

I

I

I , T , S

15 14 13 12 11 10 9

8

7

I

Z

6

I

U

5

I

A

I

4

U , P, U

3

2

1

,c

I

0

=
=

U UNDEFINED; VALUE IS INDETERMINATE
D
OVERFLOW FLAG
D = DIRECTION FLAG
I = INTERRUPT ENABLE FLAG
T = TRAP FLAG
S = SIGN FLAG
Z = ZERO FLAG
A = AUXILIARY CARRY FLAG
P = PARITY FLAG
C = CARRY FLAG

Data Transfer Instructions
The 8086/8088 instruction set contains 14 data transfer
instructions. These instructions move single bytes and
words between memory and registers, and also move single bytes and words between the AL or AX registers and
110 ports. Table 1-3 lists the four types of data transfer
instructions and their functions.

Figure 1-16 Flag Storage Formats
1-13

210912-001

8086/8088 CPU

Table 1-4 Arithmetic Instructions

ADD
ADC
INC
AAA
DAA
SUB
SBB
DEC
NEG
CMP
AAS
DAS
MUL
IMUL
AAM
DIV
IDIV
AAD
CBW
CWO

always assumes that the operands specified in arithmetic
instructions contain data that represents valid numbers for
the type of instruction being performed. Invalid data may
produce unpredictable results.

ADDITION
Add byte or word
Add byte or word with carry
Increment byte or word by 1
ASCII adjust for addition
Decimal adjust for addition
SUBTRACTION

Arithmetic instructions post certain characteristics of the
result of an operation to six flags. Refer to Chapter 3 in
the iAPX 86/88,186/188 User's Manual Programmers
Reference for a detailed description of the arithmetic instructions and flags.

Subtract byte or word
Subtract byte or word with
borrow
Decrement byte or word by 1
Negate byte or word
Compare byte or word
ASCII adjust for subtraction
Decimal adjust for subtraction

Bit Manipulation Instructions
The 8086 and 8088 CPU's provide three groups of instructions for manipulating bits within both bytes and
word. These three groups are logicals, shifts and rotates.
Thble 1-6 lists these three groups of bit manipulation instructions with their functions.

MULTIPLICATION
Multiply byte or word unsigned
Integer multiply byte or word
ASCII adjust for multiply
DIVISION
Divide byte or word unsigned
Integer divide byte or word
ASCII adjust for division
Convert byte to word
Convert word to doubleword

a. Logical
The logical instructions include the boolean operators

"not", "and", "inclusive or", and "exclusive or". A
TEST instruction that sets the flags as a result of a boolean "and" operation, but does not alter either of its operands, is also included.

b. Shifts
when converting 8080/8085 assembly language programs
to run on the 8086 or 8088. The address object instructions manipulate the addresses of variables instead of the
contents of values of the variables. This is useful for list
processing, based variable and string operations.

The bits in bytes and words may be shifted arithmetically
or logically. Up to 255 shifts may be performed, according to the value of the count operand coded in the instruction. The count may be specified as a constant 1, or
register CL, allowing the shift count to be a variable supplied at execution time. Arithmetic shifts may be used to
multiply and divide binary numbers by powers of two.
Logical shifts can be used to isolate bits in bytes or words.

Arithmetic Instructions
The arithmetic instructions (see Table 1-4) perform operations on four types of numbers: 1) unsigned binary; 2)
signed binary (integers); 3) unsigned packed decimal; and
4) unsigned unpacked decimal. See Table 1-5. Binary
numbers may be 8 or 16 bits long. Decimal numbers are
stored in bytes, two digits per byte for packed decimal and
one digit per byte for unpacked decimal. The processor

c. Rotates
Bits in bytes and words can also be rotated. Bits rotated
out of an operand are not lost as in a shift, but are "circled" back into the other "end" of the operand. As in the
shift instructions, the number of bits to be rotated is taken

Table 1-5 Arithmetic Interpretation of 8-Bit Numbers
HEX

BIT PATTERN

UNSIGNED
BINARY

SIGNED
BINARY

UNPACKED
DECIMAL

PACKED
DECIMAL

+7

7

7

07

00000111

7

89

1 0001001

137

-119

invalid

89

C5

1 1000101

197

-59

invalid

invalid

1-14

210912-001

8086/8088 CPU

Table 1-7 String Instructions

Table 1-6 Bit Manipulation Instructions
LOGICALS

NOT
AND
OR
XOR
TEST

"Not" byte or word
"And" byteorword
"Inclusive or" byte or word
"Exclusive or" byte or word
"Test" byte or word

SHLISAL

Shift logical! arithmetic left
byte or word
Shift logical right byte or word
Shift arithmetic right byte or
word

SHIFTS

SHR
SAR

REP

Repeat

REPE/REPZ

Repeat while equal/zero

REPNE/REPNZ

Repeat while not
equal/not zero

MOVS

Move byte or word string

MOVSB/MOVSW

Move byte or word string

CMPS

Compare byte or word
string

SCAS

Scan byte or word string

LODS

Load by.te or word string

STOS

Store byte or word string

ROTATES

ROL
ROR
RCL
RCR

Rotate left byte or word
Rotate right byte or word
Rotate through carry left byte
or word
Rotate through carry right byte
or word

from the count operand, which may specify either a constant of 1, or the CL register. The carry flag may act as an
extension of the operand in two of the rotate instructions,
allowing a bit to be isolated in CF and then tested by a JC
(jump if carry) or JNC (jump if not carry) instruction.

contents of register DI (destination index) is taken as the
offset of the current destination string element. These
registers must be initialized to point to the
source/destination strings before executing the string instructions. The LDS, LES and LEA instructions are useful in performing this function.

String Instructions

String instructions automatically update SI and/or DI in
anticipation of processing the next string element. Setting
DF (direction flag) determines whether the index registers
are auto-incremented (DF =0) or auto-decremented
(DF = 1). Ifbyte strings are being processed, SI and/or DI
is adjusted by 1. The adjustment is 2 for word strings.

Five basic string operations, called primitives, allow
strings of bytes or words to be operated on, one element
(byte or word) at a time. Strings of up to 64k bytes may be
manipulated with these instructions. Instructions are
available to move, compare and scan for a value, as well
as moving string elements to and from the accumulator.
Table 1-7 lists the string instructions. These basic operations may be preceded by a special one-byte prefix that
causes the instruction to be repeated by the hardware, allowing long strings to be processed much faster than
would be possible with a software loop. The repetitions
can be terminated by a variety of conditions, and a repeated operation may be interrupted and resumed.

Table 1-8 String Instruction Register
and Flag Use

The string instructions operate similarly in many respects
(refer to Table 1-8). A string instruction may have a
source operand, a destination operand, or both. The harde
ware assumes that a source string resides in the current
data segment. A segment prefix may be used to override
this assumption. A destination string must be in the current extra segment. The assembler checks the attributes of
the operands to determine if the elements of the strings
are bytes or words. However, the assembler does not use
the operand names to address strings. Instead, the contents of register SI (source index) is used as an offset to
address the current element of the source string. Also, the
1-15

SI

Index (offset) for source string

01

Index (offset) for destination
string

CX

Repetition counter

ALiAX

Scan value
Destination for LODS
Source for STOS

OF

0= auto-increment SI, 01
1 = auto-decrement SI, 01

ZF

Scan / compare terminator

210912-001

8086/8088 CPU

If a repeat prefix has been coded, then register CX (count
register) is decremented by 1 after each repetition of the
string instruction. CX must be initialized to the number of
repetitions desired before the string instruction is executed. If CX is 0, the string instruction is not executed,
and control goes to the following instruction.

Table 1·9 Program Transfer Instructions
UNCONDITIONAL TRANSFERS

CALL
RET
JMP

Program Transfer Instructions
The sequence in which instructions are executed in the
8086/8088 is determined by the content of the code segment register (CS) and the instruction pointer (lP). The
CS register contains the base address of the current code
segment, the 64k portion of memory from which instructions are currently being fetched. The IP points to the
memory location from which the next instruction is to be
fetched. In most operating conditions, the next instruction
to be executed will have already been fetched and is waiting in the CPU instruction queue. The program transfer
instructions operate on the instruction pointer and on the
CS register; changing the content of these causes normal
sequential operation to be altered. When a program transfer occurs, the queue no longer contains the correct instruction. When the BIU obtains the next instruction from
memory using the new IP and CS values, it passes the
instruction directly to the EU and then begins refilling the
queue from the new location.
Four groups of program transfers are available with the
8086/8088 CPU's. See Table 1-9. These are unconditional
transfers, conditional transfers, iteration control instructions, and interrupt-related instructions.

a. Unconditional Transfers
The unconditional transfer instructions may transfer control to a target instruction within the current code segment
(intrasegment transfer) or to a different code segment (intersegment transfer). The ASM-86 Assembler terms an
intrasegment transfer SHORT or NEAR and an intersegment transfer FAR. The transfer is made unconditionally
any time the instruction is executed.

b. Conditional Transfers
The conditional transfer instructions are jumps that may
or may not transfer control depending on the state of the
CPU flags at the time the instruction is executed. These
18 instructions (see Thble 1-10) each test a different combination of flags for a condition. If the condition is "true"
then control is transferred to the target specified in the
instruction. If the condition is "false" then control passes
to the instruction that follows the conditional jump. All
conditional jumps are SHORT, that is, the target must be
in the current code segment and within -128 to + 127
bytes of the first byte of the next instruction (IMP OOH
jumps to the first byte of the next instruction). Since

Call procedure
Return. from procedure
Jump
CONDITIONAL TRANSFERS

JA/JNBE
JAE/JNB
JB/JNAE
JBE/JNA
JC
JE/JZ
JG/JNLE
JGE/JNL
JLlJNGE
JLE/JNG
JNC
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS

Jump if above/not below
nor equal
Jump if above or
equal/not below
Jump if below/not above
nor equal
Jump if below or
equal/ not above
Jump if carry
Jump if equal/zero
Jump if greater/not less
nor equal
Jump if greater or
equal/not less
Jump if less/not greater
nor equal
Jump if less or equal/not
greater
Jump if not carry
Jump if not equal/not
zero
Jump if not overflow
Jump if not parity/parity
odd
Jump if not sign
Jump if overflow
Jump if parity / parity
even
Jump if sign
ITERATION CONTROLS

LOOP
Loop
LOOPE/LOOPZ
Loop if equal/zero
LOOPNE/LOOPNZ Loop if not equal/not
zero
JCXZ
Jump if register CX = 0
INTERRUPTS

INT
INTO
IRET

Interrupt
Interrupt if overflow
Interrupt return

210912·001

8086/8088 CPU

Table 1·10 Interpretation of Conditional Transfers
MNEMONIC

CONDITION TESTED

"JUMP IF .....

JA/JNBE
JAE/JNB
JB/JNAE
JBE/JNA
JC
JE/JZ
JG/JNLE
JGE/JNL
JLIJNGE
JLE/JNG
JNC
JNE/JNZ
JNO
JNPIJPO
JNS
JO
JP/JPE
JS

(CF OR ZF)=O
CF=O
CF=1
(CF OR ZF)=1
CF=1
ZF=1
((SF XOR OF) OR ZF)=O
(SF XOR OF)=O
(SF XOR OF)=1
((SF XOR OF) OR ZF)=1
CF=O
ZF=O
OF=O
PF=O
SF=O
OF=1
PF=1
SF=1

above/not below nor equal
above or equal/not below
below Inot above nor equal
below or equal I not above
carry
equal/zero
greater I not less nor equal
greater or equal/not less
less/not greater nor equal
less or equal I not greater
not carry
not equal I not zero
not overflow
not parity I parity odd
not sign
overflow
parity I parity equal
sign

Note: "above" and "below" refer to the relationship of two unsigned values;
"greater" and "less" refer to the relationship of two signed values.

OPERAND ADDRESSING MODES

jumps are made by adding the relative displacement of the
target to the instruction pointer, all conditional jumps are
self-relative and are appropriate for position-independent
routines.

The 8086 and 8088 access instruction operands in many
different ways. Operands may be contained in registers,
within the instruction itself, in memory, or at I/O ports.
Also, the addresses of memory and I/O port operands can
be calculated in several different ways. These addressing

c. Iteration Control
The iteration control instructions can be used to regulate
the repetition of software loops. These instructions use the
CX register as a counter. Like the conditional transfers,
the iteration control instructions are self-relative and may
only transfer to targets that are within -128 to + 127
bytes of themselves, i.e., they are SHORT transfers.

Table 1·11 Processor Control Instructions
FLAG OPERATIONS
STC
CLC
CMC
STO
CLO
STI
CLI

d. Interrupt Instructions
The interrupt instructions allow interrupt service routines
to be activated by programs as well as by external hardware devices. The effect of software interrupts is similar
to hardware-initiated interrupts. However, the processor
does not execute an interrupt acknowledge bus cycle if the
interrupt originates in software or with an NMI.

Set carry flag
Clear carry flag
Complement carry flag
Set direction flag
Clear direction flag
Set interrupt enable flag
Clear interrupt enable flag
EXTERNAL SYNCHRONIZATION

HLT
WAIT
ESC
LOCK

Processor Control Instructions
The processor control instructions (see Table 1-11) allow
programs to control various CPU functions. One group of
instructions updates flags, and another group is used primarily for synchronizing the 8086 or 8088 to external
events. A final instruction causes the CPU to do nothing.
Except for the flag operations, none of the processor control instructions affect the flags.

Halt until interrupt or reset
Wait for TEST pin active
Escape to external processor
Lock bus during next
instruction
NO OPERATION

NOP

1-17

No operation

210912-001

8086/8088 CPU

modes greatly extend the flexibility and convenience of
the instruction set. The following paragraphs briefly describe the register and immediate modes of operand addressing, and then provide a detailed description of the
memory and I/O addressing modes.

The displacement element is an 8-or 16-bit number that is
contained in the instruction. The displacement generally
is derived from the position oftheoperand name (a variable or label) in the program. The programmer can also
modify this value or explicitly specify the displacement.

Register and Immediate Operands

A programmer may specify that either BX or BP is to
serve as a base register whose content is to be used in the
EA computation.

Instructions that specify only register operands are generally the most compact and fastest executing of the operand
addressing forms. This is because the register operand
addresses are encoded in instructions in just a few bits,
and because these operands are performed entirely within
the CPU (no bus cycles are run). Registers may serve as
source operands, destination operands, or both.

Similarly, either SI or DI may be specified as the index
register. The displacement value is a constant. The contents of the base and index registers may change during
execution. This allows one instruction to access different
memory locations as determined by the current values in
the base and/or index registers. Effective address calculations with the BP are made using the SS register, by default, Although either the DS or the ES registers may be
specified instead.

Immediate operands are constant data contained in an instruction. The data may be either 8 or 16 bits in length.
Immediate operands can be accessed quickly because they
are available directly from the instruction queue. Like the
register operand, no bus cycles need to be run to obtain an
immediate operand. The limitations on immediate operands are that they may only serve as source operands and
that they are constant value i

b. Direct Addressing
Direct addressing is the simplest memory addressing
mode (see Figure 1-18). No registers are involved and the
EA is taken directly from the displacement of the instruction. Direct addressing is typically to access simple variables (scalars).

Memory Addressing Modes

Although the EU has direct access to register and immediate operands, memory operands must be transferred to
and from the CPU over the bus. When the EU needs to
read or write a memory operand, it must pass an offset
value to the BIU. The BIU adds the offset to the (shifted)
content of a segment register producing a 20Cbit physical
.address and then executes the bus cycle or cycles. needed
to access the operand.

c. Register Indirect Addressing
The effective address of a memory operand may be.taken
directly from one of the base or index registers (see Figure 1-19). One instruction can operate on many different
memory locations if the value in the base or index register
is updated appropriately. Any 16-bit general register may
be used for register indirect addressing with the JMP or
CALL instructions.

a. The Effective Address
The offset that the EU calculates for a memory operand is
called the operand's effective address or EA. This address
is an unsigned l6-bit number that expresses the operand's
distance in bytes from the beginning of the segment in
which it resides. The EU can calculate the effective address in several different ways. Information encoded in
the second byte of the instruction tells the EU how to calculate the effective address of each memory operand. A
compiler or assembler derives this information from the
statement or instruction written by the programmer. Assembly language programmers have access to all addressing modes.

d. Based Addressing
In based addressing (see Figure 1-20), the effective address is the sum of a displacement value and the content of
register BX or BP. Specifying register BP as a base register directs the BIU to obtain the operand from the current
stack segment (unless a segment override prefix is
present). This makes based addressing with BP a very
convenient way to access stack data.
Based addressing also provides a simple way to address
structures which may be located at different places in
memory (see Figure 1-21). A base register can be pointed
at the base of the structure and elements of the structure
can be addressed by their displacement from the structure
base. Different copies of the same structure can be accessed by simply changing the base register.

The EU calculates the EA by summing a displacement,
the content of a base register and the content of an index
register (see Figure 1-17). Any combination of these
three components may be present in a given instruction.
This allows a variety of memory addressing modes.
1-18

210912-001

8086/8088 CPU

SINGLE INDEX

DOUBLE INDEX

OR

OR

ENCODED
INTHE
INSTRUCTION
EU

{
EXPLICIT
INTHE
INSTRUCTION

l

ASSUMED
UNLESS
OVERRIDDEN
BY PREFIX

BIU

Figure 1-17 Memory Address Computation

e. Indexed Addressing

-..,
CEM!N: .-J

r----,.----r---~-

I

OPCODE

I MOD RIM 1

DISPLA

The effective address is calculated from the sum of a displacement plus the content of an index register (SI or DI)
in index addressing (see Figure 1-22). Indexed address is
often used to access elements in an array (see Figure
1-23). The displacement locates the beginning of the array, and the value of the index register selects one element

EA

Figure 1-18 Direct Addressing

II

OPCODE

I MOD RIM I

E~+i

BX

I--g~OR

SI

1--%7-

I

EA

I

I

EA

Figure 1-20 Based Addressing

Figure 1-19 Register Indirect Addressing
1-19

210912-001

8086/8088 CPU

cr
DISPLACEMENT

r1

,

BASE REGISTERj

I

HIGH ADDRESS

cr
Fi
DISPLACEMENT

,.

AGE

STATUS

RATE
VAe

i

DEPT

I
I

SICK
DIV

[BASE REGISTER

EMPLOYEE

L _____t---.JI
EA

ISTATUS

AGE

RATE
VAe

SICK

DePT

DIV

EMPLOYEE

J-,

Ei~=+i
I

:

I

EA

I

_-----.J

Figure 1-24 Based Index Addressing

LOW ADDRESS

f. Based Index Addressing

Based index addressing generates an effective address that
is the sum of a base register, an index register and a displacement (see Figure 1-24). This mode of addressing is
very flexible because two address components can be varied at execution time.

Figure 1-21 Accessing A Structure
With Based Addressing
( the first element is selected if the index register contains
0). Since all array elements are the same length, simple
arithmetic on the index register may select any element.

Based index addressing provides a convenient way for a
procedure to address an array allocated on a stack (see
Figure 1-25). Register BP can contain the offset of a reference point on the stack, typically the top of the stack
after the procedure has saved registers and allocated local
storage. The offset of the beginning of the array from the
reference point can be expressed by a displacement value,
and the index register can be used to access individual
array elements. Arrays contained in structures and matrices (two-dimensional arrays) can also be accessed with
based indexed addressing.
g. String Addressing
String instructions do not use the normal memory addressing modes to access operands. Instead, the index
registers are used implicitly (see Figure 1-26). When a
string instruction is executed, SI is assumed to point to the
first byte or word of the source string. DI is assumed to
point at the first byte or word of the destination string. In
a repeated string operation, the CPU's automatically adjust SI and DI to obtain subsequent bytes or words. Note
that for string instructions DS is the default segment register to SI and ES is the default segment register for DI.
This allows string instructions to easily operate on data
located anywhere within the one megabyte address space.

Figure 1-22 Indexed Addressing

HIGH ADDRESS

ARRAY (8)

r 'I.

DISPLACEMENT

I

I
I

INDEX

~GISTER

r-

"i I
t-L ------- .....
I

I

I

EA

A-RRAY (7)

ARRAY (6)

&':;':::;~=:..Il

ARRAY (5)
ARRAY (4)

ARRAY (3)
ARRAY (2)
ARRAY (1)
ARRAY (0)

--I

t
EA

I

I
I
I
I
I

_-------J

1/0 Port Addressing
Any of the memory operand addressing modes may be
used to access an I/O port if the port is memory mapped,
For example, a group of terminals can be accessed as an
"array". String instructions can also be used to transfer
data to memory-mapped ports with an appropriate hardware interface.

.... lWORO .....
LOW ADDRESS

Figure 1-23 Accessing an Array
With Indexed Addressing
1-20

210912-001

8086/8088 CPU

HIGH ADDRESS
DISPLACEMENT

I

6

J

~

r-

1

1

I

12

1

i

1

EA

1
1

1

OLD

1
INDEX !GISTER

2

PARM
IP

I BASE REGISTERJIBPI

1

. PARM

BP
IBPI

1

OLD

BX

OLD

AX

1

ARRAY (61

I
1

ARRAY 151

I

4

ARRAY (4)

ARRAY 131

t-

ARRAY 121

.------1

+ ______ 1_
L

ARRAY 111

---I

i
EA

1
1
1

ARRAY 101
COUNT
TEMP
STATUS

..... 1 WORD .....

LOWER ADDRESS

Figure 1-25 Accessing a Stacked Array with Based Index Addressing
Instruction timings are presented as the number of clock
periods required to execute a particular form of the instruction (register-to-register, immediate-to-memory,
etc.). If the system is running with a 5 MHz maximum
clock, the maximum clock period is 2oons; at 8MHz, the
clock period is 125ns. When memory operands are used,
" + EA" indicates a variable number of additional clock
periods needed to calculate the operand's effective address. Table 1-15 lists all effective address calculation
times.

Two different addressing modes can be used to access
ports located in the 110 space (see Figure 1-27). The port
number is an 8-bit immediate operand for direct addressing. This allow fixed access to ports numbered 0-255.
Indirect 110 port addressing is similar to register indirect
addressing of memory operands. The port number is
taken from register DX and can range from 0 to 65,535.
By previously adjusting the content of register DX, one
instruction can access any port in the 110 space. A group
of adjacent ports can be accessed using a simple software
loop that adjusts the value of DX.

INSTRUCTION SET SUMMARY
The following paragraphs, and tables, provide detailed information for the 8086/8088 instruction set. Tables 1-12,
1-13 and 1-14 explain the symbols that are used in Table
1-16, the instruction set reference data table. Machine
language instruction encoding and decoding information
is provided in the paragraphs immediately following the
instruction set summary.

IOPCODE

DIRECT PORT ADDRESSING

~

I

~___S~I____~~I

~1~P~O~R~T~A~D~D~R'=ES~s~1

SOURCEEA

____D_I____...J - - - I DESTINATION EA

INDIRECT PORT ADDRESSING

I

Figure 1-27 1/0 Port Addressing
Figure 1-26 String Operand Addressing
1-21

210912-001

8086/8088 CPU

Table 1·12 Key to Instruction Coding Formats
IDENTIFIER

USEDIN

destination

data transfer,
bit manipulation

A register or memory location that may contain data
operated on by the instruction, and which receives (is
replaced by) the result of the operation.

source

data transfer,
arithmetic,
bit manipulation

A register, memory location or immediate value that is
used in the operation, but is not altered by the instruction.

source-table

XLAT

Name of memory translation table addressed by register

EXPLANATION

BX.
target

JMP, CALL

A label to which control is to be transferred directly, or a
register or memory location whose content is the
address of the location to which control is to be transferred indirectly.

short-label

cond. transfer,
iteration control

A label to which control is to be conditionally
transferred; must lie within -128 to +127 bytes of the first
byte of the next instruction.

accumulator

IN,OUT

Register AX for word transfers, AL for bytes.

port

IN,OUT

An I/O port number; specified as an immediate value of
0-255, or register DX (which contains port number in
range 0-64k).

source-string

string ops.

Name of a string in memory that is addressed by register
SI; used only to identify string as byte or word and
specify segment override, if any. This string is used in
the operation, but is not altered.

dest-string

string ops.

Name of string in memory that is addressed by register
DI; used only to identify string as byte or word. This
string receives (is replaced by) the result of the operation.

count

shifts, rotates

Specifies number of bits to shift or rotate; written as
immediate value 1 or register CL (which contains the
count in the range 0-255).

interrupt-type

INT

Immediate value of 0-255 identifying interrupt pOinter
number.

optional-pop-value

RET

Number of bytes (0-64k, ordinarily an even number) to
discard from stack.

external-opcode

ESC

Immediate value (0-63) that is encoded in the instruction
for use by an external processor.

1-22

210912-001

8086/8088 CPU

Table 1-14 Key to Operand Types

Table 1-13 Key to Flag Effects
IDENTIFIER

IDENTIFIER

EXPLANATION

(blank)

not altered

0

cleared to 0

1

set to 1

X

set or cleared according
to result

U

undefined-contains no
reliable value

R

restored from previouslysaved value

(no operands) No operands are written
register
An 8- or 16-bit general register
reg 16
A 16-bit general register
seg-reg

Register AX or AL

immediate

A constant
O-FFFFH

For instructions which repeat a specified number of times,
the values m and n each consist of two parts in the relation
"x + y/rep", where x is the initial number of clocks required to start the instruction, and y is the number of
clocks corresponding to the number of iterations specified. For 16-bit repeated instructions on the 8088 and
80188, when the expression "(4 * transfers)" has to be
added to m or n, it should be added to the y part of the
expression before it is multiplied by the number of
repetitions.

in

the

range

immed8

A constant in the range O-FFH

memory

An 8- or 16-bit memory
location(1)
An 8-bit memory location(1)
A 16-bit memory location(1)

source-table

Name
table

source-string

Name of string addressed by
register SI
Name of string addressed by
register 01

dest-string

All of the instruction times given are of the form "n(m)" ,
where"n" is the number of clocks required for the 8086
to execute the given instruction, and "m" is the number of
clocks required by the 80186 for the same instruction.
The number of clocks required for the 8088 will be n for
8-bit operations and n + (4 * transfers) for 16-bit operations. For the 80188, the number of clocks will be m for
8-bit operations and m + (4 * transfers) for 16 bit
operations.

A segment register

accumulator

mem8
mem16

The timings given for control transfer instructions include
any additional clocks required to reinitialize the instruction queue as well as the time required to fetch the target
instructions. For instructions executing on an 8086, four
clocks should be added for each instruction reference to a
word operand located at an odd memory address to reflect
any additional operand bus cycles required. Also, for instructions executing on an 8088, four clocks should be
added to each instruction reference to a 16-bit memory
operand. This includes stack operations. The required
number of data references is listed for each instruction in
Table 1-16 to aid in this calculation.

Several additional factors can alter the actual execution
time from the figures shown in Table 1-16. The time provided assumes that the instruction has already been prefetched and that it is waiting in the instruction queue. This
assumption is valid under most, but not all, operating conditions. A series of fast executing (fewer than two clocks
per opcode byte) instructions can drain the queue and increase execution time. Execution time is also slightly

EXPLANATION

of

256-byte

translate

OX

Register OX

short-label

A label within -128 to +127
bytes of the end of the instruction

near-label

A label
segment

in

current

code

far-label

A label
segment

in

another

code

near-proc

A procedure in current code
segment

far-proc

A procedure in another code
segment

memptr16

A word containing the offset of
the location in the current code
segment to which control is to
be transferred(1)

memptr32

A doubleword containing the
offset and the segment base
address of the location in
another code segment to which
control is to be transferred(1)
A 16-bit general register
containing the offset of the
location in the current code
segment to which control is to
be transferred

regptr16

repeat

A string
prefix

instruction

repeat

(1)Any addreSSing mode-direct, register indirect, based, indexed, or based
indexed-may be used

1-23

210912·001

8086/8088 CPU

Table 1·15 Effective Address Calculation Time

EA COMPONENTS
Displacement Only
Base or Index Only
Displacement
+
Base or Index
Base
+
Index
Displacement
+
Base
+
Index

for this operand to avoid waiting a full 4-clock bus cycle).
If the queue is full the EU does not have to wait because
the BIU is idle. (This assumes the BIU can obtain the bus
on demand and no other processors are competing for the
.
bus).

CLOCKS'

6
(BX,BP,SI,DI)

5
With typical instruction mixes, the time actually required
to execute a sequence of instructions will be within
5 - 10% of the sum of the individual timings provided in
Table 1-16. Cases can be constructed, however, in which
execution time may be much higher than the sum of the
figures provided in the table. The execution time for a
given sequence of instructions is always repeatable, assmning .comparable external conditions (interrupts, coprocessor activity, etc.). Ifthe execution time for a given
series of instructions must be determined exactly, the instructions should be run on an execution vehicle such as
the iSBC 88/25 or 86/30 board.

9

(BX,BP,SI,DI)
BP + 01, BX + SI
BP+SI, BX+DI
BP+DI+DISP
BX+SI+DISP
BP+SI+DISP
BX+ 01+ DISP

7

8
11

12

• Add 2 clocks for segment override

effected by the interaction of the EU and BIU when memory operands must be read or written. If the EU needs
access to memory, it may have to wait for up to one clock
if the BIU has already started an instruction fetch bus cycle. (The EU can detect the need for a memory operand
and post a bus request far enough in advance of its need

MACHINE INSTRUCTION ENCODING AND
DECODING
Machine instruction encoding and decoding is primarily
the concern of the programmer. It is presented here for
the hardware designer since such encoding and decoding

Table 1·16 Instruction Set Reference Data

IAAA (no operands)

AAA

FIODITSZAPC
ags U
U UX UX

ASCII adjust for addition

Operands

(no operands)

Clocks

Transfers'

Bytes

8(8)

-

1

IAAD (no operands)

AAD
(no operands)

Clocks

Transfers'

Bytes

60(15)

-

2

IAAM (no operands)

AAM

AAA
FIODITSZAPC
ags U
XXUXU

ASCII adjust for division

Operands

Coding Example

Coding Example

ADD
FI

ASCII adjust for multiply

Operands

(no operands)

Clocks

Transfers'

Bytes

83(19)

-

2

IAAS (no operands)

AAS
Operands

(no operands)

Clocks

Transfers'
-

8(7)

AAM

0 0 ITS ZAP C

ags U

UUXUX

Coding Example

Bytes
1

XXUXU

Coding Example

FI

ASCII adjust for subtraction

0 0 ITS ZAP C

ags U

AAS

• For the 8086 (80t 86) add. four clocks for each 16·M word transfer With an odd address. For the 8088 (80188) add four clocks for each 16·M wora
transfer.

1-24

210912·001

8086/8088 CPU

Table 1·16 Instruction Set Reference Data (continued)

I

ADC destination, source
Add with carry

ADC
Operands
register, register
register, memory
memory, register
register, immediate
memory, immediate
accumulator, immediate

I

FIODITSZAPC
ags
XXX XX

x

Clocks

Transfers·

Bytes

3(3)
9(10)+EA
16(10)+EA
4(4)
17(16)+EA
4(3-4)

-

2
2-4
2-4
3-4
3-6
2-3

1
2

2

-

ADD destination, source
Addition

ADD
Operands
register, register
register, memory
memory, register
register, immediate
memory, immediate
accumulator, immediate

I

FIODITSZAPC
ags X
XXXXX

Clocks

Transfers·

Bytes

3(3)
9(10)+EA
16(10)+EA
4(4)
17(16)+EA
4(3-4)

-

2
2-4
2-4
3-4
3-6
2-3

1
2

2

-

Operands
register, register
register, memory
memory, register
register, immediate
memory, immediate
accumulator, immediate

I

Operands
register, memory

CALL

I

Clocks

Transfers·

Bytes

3(3)
9(10)+EA
16(10)+EA
4(4)
17(16)+EA
4(3-4)

-

2
2-4
2-4
3-4
3-6
2-3

1
2

2

-

near-proc
far-proc
memptr 16
regptr 16
memptr32

I

CBW

Clocks

Transfers·

Bytes

(35)

2

2

(no operands)

ANDAL, BL
AND CX, FLAB WORD
AND ASCII [DI), AL
AND CX, OFOH
AND BETA, 01 H
AND AX, 01 01 OOOOB

Coding Example
BOUND AX, ALPHA
FIODITSZAPC
ags
XXXXX

x

Clocks

Transfers·

Bytes

19(14)
28(23)
21(19)+EA
16(13)
37(38)+EA

1
2
2
1
4

3
5
2-4
2
2-4

CBW (no operands)
Convert byte to word

Operands

XXUXO

Coding Example

Flags 0 D ITS ZAP C

CALL target
Call a procedure

Operands

0 D I TSZAPC

Flags 0

BOUND destination, source
Array bounds check

BOUND

Coding Example
ADDCX, DX
ADD DI, [BX),ALPHA
ADD TEMP, CL
ADDCL,2
ADDALPHA,2
ADD AX, 200

.

AND destination, source
Logical and

AND

Coding Example
ADCAX,SI
ADC CX, BETA [SI)
ADC ALPHA [BX) [SI), DI
ADC BX, 256
ADC GAMMA, 30H
ADCAL,5

Coding Example
CALL NEAR_PROC
CALL FOR_PROC
CALL PROC_TABLE [SI)
CALL AX
CALL [BX).TASK [SI)
FIODITSZAPC
ags u
UUXUX

Clocks

Transfers·

Bytes

2(2)

-

1

Coding Example
CBW

"For the 8086 (80186) add four clocks for each 16·bit word transfer with an odd address. For the 8088 (80188) add four clocks for each 16-bit word
transfer.

1-25

210912'()01

8086/8088 CPU

Table 1-16 Instruction Set Reference Data (continued)

I

CLC (no operands)
Clear carry flag

CLC
Operands
(no operands)

I

Flags

Clocks

Transfers·

Bytes

2(2)

-

1

CLD (no operands)
Clear direction flag

CLO
Operands
(no operands)

Transfers·

Bytes

2(2)

-

1

I

Cli (no operands)
Clear interrupt flag

CLI
Operands
(no operands)

I

Operands
(no operands)

I

Clocks

Transfers·

Bytes

2(2)

-

1

Clocks

Transfers·

Bytes

2(2)

-

1

Operands
register, register
register, memory
memory, register
register, immediate
memory, immediate
accumulator, immediate

I

Operands
dest-string, source-string
(repeat) dest-string, source-string

I
Operands

ODITSZAPC
X
XXX XX

3(3)
9(10)+EA
9(10)+EA
4(3)+EA
10(10)+EA
4(3-4)

-

2
2-4
2-4
3-4
3-6
2-3

CMP BX, CX
CMP DH, ALPHA
CMP [BP + 21, SI
CMP BL, 02H
CMP [BXI.RADAR [01), 3420H
CMP AL; 000100008

1
1

1

-

FI

Clocks

Transfers'

Bytes

22(22)
9+22/rep
(5 + 22/rep)

2
2/rep

1
1

Clocks
4(4)

Transfers·

Bytes

-

1

Coding Example
CMPS BUSS1, BUFF2
REPE CMPS 10, KEY

00 I TSZAPC

Coding Example
CWO
ODITSZAPC
Flags X
XXXXX

Transfers·

Bytes

-

1

.

0 0 ITS ZAP C
ags X
XXXXX

Flags

DAA (no operands)
Decimal adjust for addition

(no operands)

Coding Example
CMC

Coding Example

I
Operands

ODITSZAPC
X

Bytes

5(4) .

OAA

Coding Example
CLI

Transfers·

Clocks

(no operands)

ODITSZAPC
0

Clocks

CWD(no operands)
Convert word to doubleword

CWO

CLD

Flags

CMPS des-string, source-string
Compare string

CMPS

ODITSZAPC
0

Coding Example

Flags

CMP destination, source
Compare destination to source

CMP

CLC

Flags

CMC (no operands)
Complement carry flag

CMC

Coding Example

Flags

Clocks

ODITSZAPC
0

Coding e:xample
DAA

"For the 8086 (80186) add four clocks for each 16·bit word transfer with an odd address. For the 8088 (80188) add four clocks for each 16'bit word
transfer.

1-26

210912-001

8086/8088 CPU

Table 1-16 Instruction Set Reference Data (continued)

I

DAS (no operands)
Decimal adjust for subtraction

DAS
Operands

FI

Clocks

Transfers'

Bytes

4(4)

-

1

(no operands)

IDEC destination

DEC
reg 16
reg8
memory

Clocks

Transfers'

Bytes

3(3)
3(3)
15(15)+EA

-

1
2
2-4

-

2

IDIV source

DIV
reg 8
reg 16
mem8
mem 16

locals, level

I
Operands

immediate, memory
immediate, register

1

2
2
2-4

DIVCL
DIVBX
DIVALPHA

1

2-4

DIV TABLE [SI]

(no operands)

Coding Example

Flags

Clocks

Transfers'

Bytes

L=0(15)
L=1(25)
L>1
(22+
16(n-1))

-

4

Clocks

Transfers'

Bytes

8(6)+EA
2(2)

1
-

2-4
2

ENTER 28, 3

Transfers'

Bytes

2(2)

-

1

ODITSZAPC

Coding Example

ESC 6.ARRAY [SI]
ESC 20, AL
Flags

Clocks

ODITSZAPC

Coding Example

Flags

Halt

Operands

DEC AX
DECAL
DEC ARRAY [SI]

80-90(29)
144-162(38)
86-96+EA
(35)
150-168+
EA(94)

IHLT (no operands)

HLT

Coding Example

Bytes

ESC external-opcode, source
Escape

ESC

ODITSZAPC
X
XXXX

Transfers'

ENTER
Procedure entry

Operands

XXXXX

Coding Example

Clocks

I

ENTER

U

FIODITSZAPC
ags U
UUUUU

Division, unsigned

Operands

0 D ITS ZAP C

DAS
Flags

Decrement by 1

Operands

ags

OD ITSZAPC

Coding Example

HLT

"For the 8086 (80186) add four clocks for each 16·bit word transfer with an odd address. For the 8088 (80188) add four clocks for each 16·bit word
transfer.

1-27

210912·001

8086/8088 CPU

Table 1-16 Instruction Set Reference Data (continued)
FI

IIDIV source
Integer division

IDIV
Operands
reg 8
reg 16
mem8
mem 16

Clocks

Transfers·

Bytes

101-112
(44-52)
165-184
(53-61)
107-118+
EA(50-58)
171-190+
EA(58-67)

-

2

IDIVBL

-

2

IDIVCX

Operands
immed8
immed 16
reg 8
reg 16
mem8
mem 16

Operands
accumulator, immed 8
accumulator, OX

IDIV DIVISOR_BYTE [SI)

1

2-4

IDIV [BX].DIVISOR_WORD

FI

Operands
reg 16
reg 8
memory

Operands
dest·string, port
(repeat) dest-string, port

UUUUX

Transfers·

Bytes

(22-24)
(29-32)
80-98
(25-28)
128-154
(34-37)
86-104+
EA(31-34)
134-160+
EA(40-43)

-

3
4
2

IMUL6
IMUL20
IMULCL

-

2

IMULBX

1

2-4

IMUL RATE_BYTE

1

2-4

IMUL RATE_WORD [BP) (01)

Coding Example

Flags

Clocks

Transfers·

Bytes

10(10)
8(8)

1
1

2
1

Clocks

Transfers·

Bytes

3(3)
3(3)
15(15)+EA

-

1
2
2-4

2

ODITSZAPC

Coding Example
IN AL, OFFEAH
IN AX, OX
Flags

IINS source-string, port
Input string

INS

0 0 ITS ZAP C

ags X

Clocks

IINC destination
Increment by 1

INC

Coding Example

2-4

liN accumulator, port
Input byte or word

IN

U U U U U

1

IIMUL source
Integer multiplication

IMUL

0 01 T S ZAP C

ags U

~0

I

TSZAPC
XXXX

Coding Example
iNCCX
INCBL
INC ALPHA [01) [BX)
Flags 0 0 ITS ZAP C

Clocks

"TI'ansfers·

Bytes

(14)
(9 +8/rep)

2
2/rep

1
1

Coding Example
INS BUFF1, USART D
REP INS BUFF1, USART D

'For the 8086 (80186) add four clocks for each 16·bit word transfer with an odd address. For the 8088 (80188) add four clocks for each 16-bit word
transfer.

1-28

210912-001

8086/8088 CPU

Table 1-16 Instruction Set Reference Data (continued)

~

INT

INT interrupt-type
Interrupt

Operands
mmed 8 (type = 3)
immed 8 (type"* 3)

Clocks

Transfers·

Bytes

52(45)
52(47)

5
5

1
2

IINTR (external maskable interrupt)
Interrupt if INTER and IF = 1

INTRt
Operands
(no operands)

Clocks

Transfers·

Bytes

61

7

N/A

Operands
(no operands)

Transfers·

Bytes

53 or
4(48 or 4)

5

1

Operands
(no operands)

JA/JNBE
Operands
Short-label

JAE/JNB
Operands
short-label

JB/JNAE
Operands
short-label

JBE/JNA
Operands

I

OOITSZAPC
00

Coding Example
N/A
OOITSZAPC
00

Coding Example
INTO

00 I TSZAPC
Flags R R R R R R R R R

IIRET (no operands)
Interrupt Return

IRET

INT3
INT67

Flags

Clocks

OOITSZAPC
00

Coding Example

Flags

I INTO (no operands)
Interrupt if overflow

INTO

short-label

Flags

Clocks

Transfers·

Bytes

32(28)

3

1

JA/JNBE short-label
Jump if above/Jump if not below nor equal
Clocks

Transfers·

Bytes

16 or
4(13 or 4)

-

2

I JAE/JNB short-label
Jump if above or equal/Jump if not below
Clocks

Transfers·

Bytes

16 or
4(13 or 4)

-

2

I JB/JNAE
Jump if below/Jump if not above nor equal
Clocks

Ti'ansfers·

Bytes

16 or
4(13 or 4)

-

2

I JBE/JNA short-label
Jump if below or equal/Jump if not above
Clocks

Transfers·

Bytes

16 or
4(13 or 4)

-

2

Coding Example
IRET
Flags

OOITSZAPC

Coding Example
JAABOVE

Flags

00 I TSZAPC

Coding Example
JAE ABOVE_EQUAL

Flags

00 I TSZAPC

Coding Example
JB BELOW

Flags

OOITSZAPC

Coding Example
JNA NOT-ABOVE

'For the 8086 (80186) add four clocks for each 16-bit word transfer with an odd address. For the 8088 (80188) add four clocks for each 16-bit word
transfer.
tlNTR is not an instruction, it is included in table 1-16 only for timing information.

1-29

210912-001

8086/8088 CPU

Table 1-16 Instruction Set Reference Data (continued)

I

Operands
short-label

1

Clocks

Transfers·

Bytes

16 or
4(13 or 4)

-

2

JCXZ short-label
Jump if CX is zero

JCXZ
Operands
short-label

I
Operands

short-label

JG/JNLE

I

Clocks

Transfers·

Bytes

16 or
4(16 or 5)

-

2

short-label

I

Clocks

Transfers·

Bytes

16 or
4(13 or 4)

-

2

Clocks

Transfers·

Bytes

16 or
4(13 or 4)

-

2

JGE/JNL short-label
Jump if greater or equal/Jump if not less

JGE/JNL
Operands
short-label

JLlJNGE

I

Clocks

Transfers·

Bytes

16 or
4(13 or 4)

-

2

JL/JNGE short-label
Jump if less/Jump if not greater nor equal

Operands
short-label

I

Clocks

Transfers·

Bytes

16 or
4(13 or 4)

-

2

JLElJNG short-label
Jump if less or equal/Jump if not greater

JLE/JNG
Operands

Coding Example
JCXZ COUNT_DONE

Flags

JG/JNLE short-label
Jump if greater/Jump if not less nor equal

Operands

Coding Example
JC CARRY_SET

FIODITSZAPC
ags

JE/JZ short-label
Jump if equal/Jump if zero

JE/JZ

short-label

FIODITSZAPC
ags

JC short-label
Jump if carry

JC

Clocks

Transfers·

Bytes

16 or
4(13 or 4)

-

2

00 I TSZAPC

Coding Example
JZZERO

Flags

ODITSZAPC

Coding Example
JG GREATER

Flags 0 0 ITS ZAP C
Coding Example
JGE GREATER_EQUAL

Flags

00 I TSZAPC

Coding Example
JL LESS

Flags

00 I TSZAPC

Coding Example
JNG NOT_GREATER

'For the 8086 (80186) add four clocks for each 16-bit word transfer with an odd address. For the 8088 (80188) add four clocks for each 16-bit word
transfer.

1-30

210912-001

8086/8088 CPU

Table 1-16 Instruction Set Reference Data (continued)

I

JMP target
Jump

JMP
Operands
short-label
near-label
far-label
memptr 16
regptr 16
memptr32

I

Clocks

Transfers·

Bytes

15(13)
15(13)
15(13)
18(17)+EA
11 (11)
24(26)+EA

-

2
3
5
2-4
2
2-4

-

1

2

JNC short-label
Jump if not carry

JNC
Operands
short-label

I

Operands
short-label

I

Clocks

Transfers·

Bytes

16 or
4(13 or 4)

-

2

Operands
short-label

JNP/JPO

I

Clocks

Transfers·

Bytes

16 or
4(13 or 4)

-

2

short-label

I

Clocks

Transfers·

Bytes

16 or
4(13 or 4)

-

2

Operands
short-label

I

Clocks

Transfers·

Bytes

16 or
4(13 or 4)

-

2

Operands

Coding Example
JNO NO_OVERLOW

Coding Example
JPO ODD_PARITY

Flags 0 D ITS ZAP C

Clocks

Transfers·

Bytes

16 or
4(13 or 4)

-

2

JO'short-label
Jump if overflow

JO

Coding Example
JNE NOT_EQUAL

Flags 0 D ITS ZAP C

JNS short-label
Jump if not sign

JNS

JNC NOT_CARRY

Flags OD I TSZAPC

JNP/JPO short-label
Jump if not parity/Jump if parity odd

Operands

Coding Example

Flags OD I TSZAPC

JNO short-label
Jump if not overflow

JNO

Coding Example
JMPSHORT
JMP WITHIN_SEGMENT
JMP FAR_LABEL
JMP [BX).TARGET
JMPCX
JMP OTHER.SEG [SI)
Flags 0 D ITS ZAP C

JNE/JNZ short-label
Jump if not equal/Jump if not zero

JNE/JNZ

short-label

Flags 0 D ITS ZAP C

Coding Example
JNS POSITIVE

Flags OD I TSZAPC

Clocks

Transfers·

Bytes

16 or
4(13 or 4)

-

2

Coding Example
JO SIGNED_OVRFLW

'Forthe 8086 (80186) add four clocks for each HI·bit word transfer with an odd address. For the 8088 (80188) add four clocks for each 16·bit word
transfer.

1-31

210912·001

8086/8088 CPU

Table 1·16 Instruction SetReference Data (continued)

I

JP/JPE short-label
Jump if parity/Jump if parity even

JP/JPE
Operands
short-label

I

Flags 0 D ITS ZAP C

Clocks

Transfers"

Bytes

16 or
4(13 or 4)

-

2

JS short-label
Jump if sign

JS
Operands
short-label

I
Operands

(no operands)

Clocks

Transfers"

Bytes

16 or
4(13 or 4)

-

2

I

I

Clocks

I

4(2)

Operands
reg 16, tnem 16

1 Clocks

I Transfers· I Bytes
I

-

I

1

I

I Transfers· I Bytes

116(18)+EAI

I

Operands
reg 16, mem 16

I

Clocks

I 2(6)+EA

2

1 2-4

I Transfers·
1

-

Operands
(no operands)

I

I

Clocks

I

(8)

I

Operands
reg 16, mem 32

I

Clocks

I

I

1

Operands

I Transfers" I Bytes

116(18)+EAI

(no operands)

I
I

Clocks
2(2)

ags

2

12-4

Coding Example

ODITSZAPC

Coding Example
LES DI, [BX), TXT_BUFF
Flags 0 D ITS ZAP C

I Transfers· I Bytes
I

0 D I T SZ A P C
U UX U X

LEAVE
Flags

LOCK (no operands)
Lock bus

LOCK

LEA BX, [BP) [DI)

I Transfers· I Bytes
1

OD I TSZAPC

Coding Example

FI

LES destination, source
Load pOinter using ES

LES

LDS SI, DATA, SEG [DI)

1 Bytes

r 2-4

ODITSZAPC

Coding Example

Flags

LEAVE (no operand)
Restore stack for procedure exit

LEAVE

Coding Example
LAHF
Flags

LEA destination, source
Load effective address

LEA

Coding Example
JS NEGATIVE

Flags 0 D ITS Z A P·C

LOS destination, source
Load pointer using DS

LOS

JPE EVEN_PARITY

Flags 0 D ITS ZAP C

LAHF (no operands)
Load AH from flags

LAHF

Coding Example

-

I

1

Coding Example
LOCKXCHG FLAG, AL

• For the 8086 (80186) .add four clocks for each 16-bit word transfer with an odd address. For the 8088 (80188) add four clocks for each 16-bit word
transfer.

1-32

210912-001

8086/8088 CPU

Table 1-16 Instruction Set Reference Data (continued)

I

LODS source-string
Load string

LODS
Operands
source-string
(repeat) source-string

Flags a D ITS ZAP C

Clocks

Transfers·

Bytes

12(10)
9+ 13/rep
(6+ 11/rep)

1
1/rep

1
1

I

LOOP short-label
Loop

LOOP
Operands
short label

LOOPE/LOOPZ

I

short label

LOOPNE/LOOPNZ

Clocks

Transfers·

Bytes

17/5(15/5)

-

2

Clocks

Transfers·

Bytes

18 or
6(16 or 6)

-

2

LOOPNE/LOOPNZ short label
Loop if not equal/Loop if not zero

short label

I

Clocks

Transfers·

Bytes

19 or
5(16 or 5)

-

2

Operands
(no operands)

I

Clocks

Transfers·

Bytes

50

5

N/A

MOV destination, source
Move

MOV
Operands
memory, accumulator
accumulator, memory
register, register
register, memory
memory, register
register, immediate
memory, immediate
seg-reg, reg 16
seg-reg, mem 16
reg 16, seg-reg
memory, seg-reg

00 ITSZAPC

Coding Example
LOOPEAGAIN

Flags

NMI (external nonmaskable interrupt)
Interrupt if NMI = 1

NMlt

Coding Example
LOOP AGAIN
Flags

I

Operands

LODS CUSTOMER_NAME
REP LaDS NAME

Flags a D ITS ZAP C

LOOPE/LOOPZ short label
Loop if equal/Loop if zero

Operands

Coding Example

ODITSZAPC

Coding Example
LOOPNE AGAIN

Flags

00 I TSZAPC
00

Coding Example
N/A
Flags

ODITSZAPC

Coding Example

Clocks

Transfers·

Bytes

10(9)
10(8)
2(2)
8(12)+EA
9(9)+EA
4(3-4)
10(12-13)
+EA
2(2)
8(9)+EA
2(2)
9(11)+EA

1
1

3
3
2
2-4
2-4
2-3
3-6

MOV ARRAY [SI], AL
MOV AX, TEMP_RESULT
MOVAX,CX
MOV Sp, STACK-TOP
MOV COUNT [DI], CX
MOVCL,2
MOV MASK [SX] [SI], 2CH

2
2-4
2
2-4

MOVES,CX
MOV DS, SEGMENT_SASE
MOV Sp, SS
MOV [SX], SEG~SAVE, CS

1
1

1

1

1

-For the 8086 (80186) add four clocks for each 16-bit word transfer with an odd address. For the 8088 (80188) add four clocks for each 16-bit word
transfer.

tNMI is not an instruction, it is included in table 1-16 only for timing information.

1-33

210912-001

8086/8088 CPU

Table 1-16 Instruction Set Refere"ce Data (continued)

I

MOVS dest-string, source-string
Move string

MOVS
Operands

dest-string, source-string
(repeat) dest-string, source-string

MOVSB/MOVSW

I

Clocks

Transfers·

Bytes

Coding Example

18(9)
9+ 17/rep
(8+8/rep)

2
2/rep

1
1

MOV5 LINE EDIT_DATA
REP MOV5 5CREEN, BUFFER

MOVSB/MOVSW (no operands)
Move string (byte/word)
Clocks

Operands

Transfers·

18(9)
9 + 17/rep
(8+8/rep)

(no operands)
(repeat) (no operands)

2
2/rep

Flags 0 D I T 5 ZAP C

1
1

Operands

reg 16
mem8
mem 16

I
Operands

register
memory
o if destination is 0

I
Operands

UUUUX

Bytes

-

2

MULBL

-

2

MULCX

1

2-4

MUL MONTH [51)

1

2-4

MUL BAUD_RATE

Coding Example

Flags 0 D I T 5 ZAP C

Clocks

Transfers·

Bytes

3(3)
16(3)+EA

-

2
2-4

2

Coding Example
NEGAL
NEG MULTIPLIER

Flags

Clocks

Transfers·

Bytes

3(3)

-

1

NOT destination
Logical not

NOT

x

Transfers·

I

Operands
(no operands)

0 D I .T S ZAP C

70-77
(26-28)
118-133
(35-37)
76-83+
EA(32-34)
124-139+
EA(41-43)

NOP (no operands)
No Operation

NOP

ags

Clocks

NEG destination
.
Negate

NEG

MOV5B
REP MOV5W

FI

MULsource
Multiplication, unsigned

reg 8

Coding Example

Bytes

I

MUL

register
memory

Flags 0 D I T 5 ZAP C

Transfers·

Bytes

3(3)
16(3)+EA

-

2
2-4

2

D I T 5 ZAP C

Coding Example
NOP
Flags

Clocks

°

oD

I T 5 Z A.P C
.

Coding Example
NOT AX
NOT CHARACTER

'For the 8086 (80186) add four clocks for each 16-bit word transfer with an odd address. For the 8088 (80188) add four clocks for each 16-bit word
.
transfer.

1-34

210912-001

8086/8088 CPU

Table 1-16 Instruction Set Reference Data (continued)

I

OR destination, source
Logical inclusive or

OR
Operands
register, register
register, memory
memory, register
accumulator, immediate
register, immediate
memory, immediate

FIODITSZAPC
ags 0
XXUXO

Clocks

Transfers·

Bytes

Coding Example

3(3)
9(10)+EA
16(10)+EA
4(3-4)
4(4)
17(16)+EA

-

2
2-4
2-4
2-3
3-4
3-6

ORAL, BL
OR DX, PORT_ID [DI]
OR FLAG_BYTE, CL
OR AL, 011011008
ORCX,01H
OR [BX], CMD_WORD, OCFH

1
2

2

lOUT port, accumulator
Output byte or word

OUT
Operands
immed 8, accumulator
DX, accumulator

Flags

Clocks

Transfers·

Bytes

10(9)
8(7)

1
1

2
1

lOUTS port, source-string
Output string

OUTS
Operands
port, source-string
(repeat) port, source-string

POP

I

Transfers·

Bytes

(14)
(8) + 8/rep)

2
2/rep

1
1

POP destination
Pop word off stack

Operands
register
seg-reg (CS illegal)
memory

POPA

I

(no operands)

POPF

I

Clocks

Transfers·

Bytes

8(10)
8(8)
17(20)+EA

1
1
2

1
1
2-4

Operands

PUSH

I

Clocks

Transfers·

Bytes

(51)

8

1

Operands

Coding Example
OUTS PORT2, BUFF2
REP OUTS PORT2, BUFF2
OOITSZAPC

Coding Example
POP OX
POP OS
POP PARAMETER

Coding Example
POPA
Flags

Clocks

Transfers·

Bytes

8(8)

1

1

PUSH source
Push word onto stack

register
seg-reg (CS legal)
memory

ODITSZAPC

Flags 0 D ITS ZAP C

POPF (no operands)
Pop all registers

(no operands)

OUT 44,AX
OUTDX, AL

Flags

POPA (no operands)
Pop all registers

Operands

Coding Example

Flags

Clocks

ODITSZAPC

OOITSZAPC
RRRRRRRRR

Coding Example
POPF
Flags

OOITSZAPC

Clocks

Transfers·

Bytes

Coding Example

11 (1 0)
10(9)
16(16)+ EA

1
1
2

1
1
2-4

PUSH SI
PUSH ES
PUSH DRETURN_CODE [SI]

'For the 8086 (80186) add four clocks for each 16-bit word transfer with an odd address. For the 8088 (80188) add four clocks for each 16-bit word
transfer.

1-35

210912-001

8086/8088. CPU

Table 1·16 Instruction Set Reference Data (continued)

I

FI ags ODITSZAPC

PUSHA (no operands)
Push all registers

PUSHA
Operands
(no operands)

I

Clocks

I

(36)

I Transfers· I Bytes
I

8

I

4

I

pUSHF (no operands)
Push flags onto stack

PUSHF

I
I

Operands
(no operands)

Flags

I Transfers· I Bytes
I 1 I 1

Clocks
10(9)

I

RCL destination, count
Rotate left through carry

ReL

register, n
memory, n

Bytes

2(2)

2

8+41

2

bit(5 + 1/bit)
15(15)+EA

memory, 1
memoryCL

20+41

2
2

2·4
2·4

bit(17 +
1/bit)+EA
(5+ 1/bit)
(17 + 1/bit)

2

3-5

3

I

RCR destination, count
Rotate right through carry

RCR
Operands

Clocks

register, 1
register, CL
memory, 1
memoryCL

register, n
memory, n

Transfers·

Bytes
2

8+41

2

20+41

2
2

2-4
2-4

bit(17 +
1/bit)+EA
(5 + 1/bit)
(17 + 1/bit)

2

3-5

3

I

REP (no operands)
Repeat string operation

REP
Operands
(no operands)

REPE/REPZ
Operands
(no operands)

Transfers·

2(2)

-

Bytes

I

2(2)

RCLCX,1
RCLAL, CL
RCLALPHA,1
RCL [BP), PARM, CL

RCLCX,5
RCLALPHA,5

Coding Example
RCR BX, 1
RCR BL, CL
RCR [BX), STATUS, 1
RCR ARRAY, [DI), CL

RCR BX, 5
RCRALPHA,5

-

Coding Example

Flags 0 D ITS ZAP C

I Transfers· I Bytes
I

Coding Example

REP MOVS DEST, SRCE

REPE/REPZ (no operands)
Repeat string operation while equal!
while zero
Clocks

PUSHF

Flags 0 D ITS ZAP C

Clocks

I

Coding Example

ODITSZAPC
Flags X
C

2(2)

bit(5 + 1/bit)
15(15)+EA

ODITSZAPC

FIODITSZAPC
ags X
C

Transfers·

Clocks

Operands
register, 1
register, CL

Coding Example
PUSHA

I

1

Coding Example
REPE CMPS DATA, KEY

'Forthe 8086 (80186) add four clocks for each 16-bit word transfer with an odd address. For the 8088 (80188) add four clocks for each 16-bit word
transfer.

1-36

210912-001

8086/8088 CPU

Table 1-16 Instruction Set Reference Data (continued)

REPNE/REPNZ

REPNEIREPNZ (no operands)
Repeat string operation while
not equal/not zero

Operands
(no operands)

I

I
I

Clocks
2(2)

Flags

I Transfers· I Bytes
I I 1

RET optional-pop-value
Return from procedure

RET
Operands
(intra-segment,
(intra-segment,
(inter-segment,
(inter-segment,

no pop)
pop)
no pop)
pop)

I

Operands
register, 1
register, CL

Clocks

Transfers·

Bytes

16(16)
20(18)
26(22)
25(25)

1
1
2
2

1
3
1
3

J

Flags

-

2
2

2
2

2-4
2-4

ROL FLAG_BYTE [01),1
ROL ALPHA, CL

-

3
3-5

ROLBX,5
ROLBETA,5

bit(17 +
1/bit)+EA
(5+ 1/bit)
(17 + 1/bit)

2

Clocks

register, 1
register, CL

-

-

2
2

2
2

2-4
2-4

ROR PORT_STATUS, 1
ROR CMO_WORO, CL

-

3
3-5

ROR BX, 5
ROR BETA, 5

bit(5 + 1/bit)
15(15)+EA

20+41

I

FIOOITSZAPC
ags X
X
Bytes

2(2)

register, n
memory, n

bit(17+
1/bit)+EA
(5+ 1/bit)
(17 + 1lbit)

2

SAHF (no operands)
Store AH into flags

SAHF
Operands
(no operands)

Coding Example
ROL BX, 1
ROLOI,CL

'n'ansfers •

8+41

memory, 1
memoryCL

OOITSZAPC
X
X

Bytes

ROR destination, count
Rotate right

Operands

Coding Example
RET
RET4
RET
RET2

'n'ansfers·

20+41

ROR

Coding Example
REPNE SCAS INPUT_LINE

2(2)
bit(5 + 1lbit)
15(15)+EA

register, n
memory, n

TSZAPC
UUXUX

Clocks

8+41

memory, 1
memoryCL

0 I

Flags 0 0 ITS ZAP C

ROL destination, count
Rotate left

ROL

~

Coding Example
ROR BX, 1
ROR BX, CL

FI

Clocks

'n'ansfers •

Bytes

4(3)

-

1

ags

00 I TS ZAP C
RRRRR

Coding Example
SAHF

• For the 8088 (80186) add four clocks for each 16-blt word transfer with an odd address. For the 8086 (80188) add four clocks for each 16-bit word
transfer.

1-37

210912-001

8086/8088 CPU

Table 1·16 Instruction Set Reference Data (continued)

SALISHL

I

SAL/SHL destination
Shift arithmetic left/Shift logical left

Operands
register, 1
register, CL
memory, 1
memory, CL

register, n
memory, n

I

FIOOITSZAPC
ags X
·X

Clocks

Transfers·

Bytes

2(2)
8+4/
bit(5 + 1/bit)
15(15)+EA
20+41
bit(17 +
1/bit)+EA
(5+ 1/bit)
(17+ 1/bit)

-

2
2

Operands
register, 1
register, CL
memory, 1
memoryCL

register, n
memory, n

I

2-4
2-4

SAL [BX], OVERDRAW, 1
SAL STORLCOUNT, CL

-

3
3-5

SALAH,5
SAL ALPHA, 5

2

Flags

Operands
register, register
register, memory
memory, register
accumulator, immediate
register, immediate
memory, immediate

dest-string
(repeat) dest-string

TSZAPC
XXUXX

Bytes

2(2)
8+41
bit(5 + 1/bit)
15(15)+EA
20+41
bit(17+
1/bit)+EA
(5+ 1/bit)
(17 + 1/bit)

-

2
2

2
2

2-4
2-4

SAR N_BLOCKS, 1
SAR N_BLOCKS, CL

-

3
3-5

SAR OX, 5
SAR OGLTH, 5

-

2

Clocks

Transfers·

Bytes

3(3)
9(10)+EA
16(10)+EA
4(3-4)
4(4)
17(16)+EA

-

2
2-4
2-4
2-3
3-4
3-6

1
2

2

Coding Example
SAR OX, 1
SAR 01, CL

FI

SCAS dest-string
Scan string

Operands

0 I

Transfers·

I

SeAS

~

Clocks

SBB destination, source
.
Subtract with borrow

SBB

SALAL,1
SAL 01, CL

2
2

SAR destination, source
Shift arithmetic right

SAR

Coding Example

0 0 ITS ZAP C
ags X
XXXXX
Coding Example

SBBBX, CX
SBB 01, [BX), PAYMENT
SBB BALANCE, AX
SBBAX, 2
SBBCL,1
SBB COUNT, [SI), 10
FIOOITSZAPC
ags X
XXXXX

Clocks

li'ansfers·

15(15)
9+ 15/rep
(5+ 15/rep)

1
1/rep

Bytes
1 .
1

Coding Example
SCAS INPUT_LINE
REPNE SCAS BUFFER

'For the 8086 (80186) add four clocks for each 16-bit word transfer with an odd address. For the 8088 (80188) add four clocks for each 16-bit word
transfer.·
.

1-38

210912-001

8086/8088 CPU

Table 1·16 Instruction Set Reference Data (continued)

SEGMENTt
Operands

(no operands)

ISEGMENT override prefix

Flags

Override to specified segment
Clocks

Transfers'

Bytes

2(2)

-

1

ISHR destination, count

SHR
register, 1
register, CL

Clocks

Transfers'

Bytes

2(2)

-

2
2

2
2

2·4
2-4

SHR ID_BYTE [SII [BX], 1
SHR INPUT_WORD, CL

-

3
3-5

SHR SI, 5
SHRALPHA,5

8+41
bit(5 + 1/bit)
15(15)+ EA
20+41
bit(17 +
1/bit)+EA
(5+ 1/bit)
(17 + 1/bit)

memory, 1
memoryCL

register, n
memory, n

SINGLE STEPt
Operands

(no operands)

2

ISINGLE STEP (Trap flag interrupt)
Interrupt if TF

Clocks

Transfers'

Bytes

50

5

N/A

Operands

Clocks

Transfers'

Bytes

2(2)

-

1

ISTD (no operands)

STO
Operands

Clocks

Transfers'

1

ISTI (no operands)

STI
Operands

(no operands)

Clocks

Transfers'

Bytes

2(2)

-

1

ODITSZAPC
C

Coding Example

STC
ODITSZAPC
1

Coding Example

STD
Flags

Set interrupt enable flag

00

N/A

Bytes

-

2(2)

ODITSZAPC

Coding Example

Flags

Set direction flag

(no operands)

SHR SI, 1
SHRSI, CL

Flags

Set carry flag

(no operands)

Coding Example

Flags

=1

ISTC (no operands)

STC

Coding Example

MOV SS:PARAMETER AX
FIODITSZAPC
ags X
X

Shift logical right

Operands

ODITSZAPC

ODITSZAPC
1

Coding Example

STI

"For the 8086 (80186) add four clocks for each 16-bit word transfer with an odd address. For the 8088 (80188) add four clocks for each 16-bit word
transfer.
tASM-86 incorporates the segment override prefix into the operand specification and not as a separate instruction. SEGMENT is included in table
1-16 only for timing information.
tSINGLE STEP is not an instruction, it is included in table 1-16 only for timing information.

1-39

210912-001

8086/8088 CPU

Table 1-16 Instruction Set Reference Data (continued)

I

STOS dest-string
Store byte or word string

STOS
Operands
dest-string
(repeat) dest-string

I

Clocks

Transfers·

Bytes

11 (1 0)
9+ 10/rep)
(6 + 9/rep)

1
1/rep

1
1

SUB destination, source
Subtraction

SUB
Operands·
register, register
register, memory
memory, register
accumulator, immediate
register, immediate
memory, immediate

I

Operands
register, register
register, memory
accumulator, immediate
register, immediate
memory, immediate

I

Operands
(no operands)

Clocks

Transfers·

Bytes

3(3)
9(10)+EA
16(10)+EA
4(3-4)
4(4)
17(16)+EA

-

2
2-4
2-4
2-3
3-4
3-6

1
2

2

I

Operands
accumulator, reg 16
memory, register
register, register

I

Operands

Coding Example
SUBCX, BX
SUB DX, MATH_TOTAL [S1)
SUB [BP+2), CL
SUBAL,10
SUB SI, 5280
SUB [BP), BALANCE, 1000

Clocks

Transfers·

Bytes

Coding Example

3(3)
9(10)+EA
4(3-4)
5(4)
11(10)+EA

-

2
2-4
2-3
3·4
3·6

TESTSI,DI
TEST SI, END_COUNT
TEST AL, 001000008
TEST BX, OCC4H
TEST RETURN_COUNT, 01 H

1

-

-

-

Flags

Clocks

Transfers·

Bytes

4+5(6)n

-

1

Clocks

Transfers·

Bytes

3(3)
17(17)+EA
4(4)

-

1
2·4
2

2

-

ODITSZAPC

Coding Example
WAIT
Flags

XLAT source-table
Translate

XLAT

Coding Example
STOS PRINT_LINE
REP STOS DISPLAY

FIODITSZAPC
ags o
XXUXO

XCHG destination, source
Exchange

XCHG

0 D ITS ZAP C

x

WAIT (no operands)
Wait while TEST pin not asserted

WAIT

ags

FIODITSZAPC
ags
XXX XX

TEST destination, source
Test or non-destructive logical and

TEST

source-table

FI

ODITSZAPC

Coding Example
XCHGAX, BX
XCHG SEMAPHORE, AX
XCHGAL, BL
Flags 0 D ITS ZAP C

Clocks

Transfers·

Bytes

11 (11)

1

1

Coding Example
XLAT ASCII_TAB

'For the 8086 (80186) add four clocks for each 16-bit word transfer with an odd address. For the 8088 (80188) add four clocks for each 16-bit word
.
transfer.

1·40

210912-001

8086/8088 CPU

Table 1-16 Instruction Set Reference Data (continued)

IXOR destination, source

XOR

FI

Logical exclusive or

Operands

register, register
register, memory
memory, register
accumulator, immediate
register, immediate
memory, immediate

0 D I T 5 ZAP C

ags 0

XXUXO

Clocks

Transfers·

Bytes

Coding Example

3(3)
9(10)+ EA
16(10)+EA
4(3-4)
4(4)
17(16)+EA

-

2
2-4
2-4
2-3
3-4
3-6

XORCX, BX
XOR CL, MA5LBYTE
XOR ALPHA [51], DX
XOR AL, 010000108
XOR 51, 00C2H
XOR RETURN_CODE, OD2H

1
2

2

• For the 8086 (80186) add four clocks for each 16-bit word transfer with an odd address. For the 8088 (80188) add four clocks for each 1S-bit word
transfer.

ADD, XOR, etc. The following bit, called the 0 field,
generally specifies the "direction" of the operation: 1 =
the REG field in the second byte identifies the destination
operand, 0 = the REG field identifies the source operand. The W field distinguishes between byte and word
operations: 0 = byte, 1 = word.

directly affects bus activity. As an example of the encoding and decoding process, consider writing a MOV instruction in ASM-86 in the form:
MOV destination ,source
This will cause the assembler to generate I of 28 possible
forms of the MOV machine instruction. A programmer
rarely needs to know the details of machine instruction
formats or encoding. An exception may occur during debugging when it may be necessary to monitor instructions
fetched on the bus, read unformatted memory dumps, etc.
This section provides the information necessary to translate or decode an 8086 or 8088 machine instruction.

One of three additional single-bit fields, S, V or Z, appears in some instruction formats (refer to Table 1-17). S,
in conjunction with W, indicates the sign extension of immediate fields in arithmetic instructions. V distinguishes
between single-and variable-bit shifts and rotates. Z is a
compare bit with the zero flag in conditional repeat and
loop instructions.
The second byte of the instruction usually identifies the
instruction's operands. The MOD (mode) field indicates
whether one of the operands is in memory or whether
both operands are registers (refer to Table 1-18). The
REG (register) field identifies a register that is one of the
instruction operands (refer to Table 1-19). In a number of
instructions, particularly the immediate-to-memory variety, REG is used as an extension of the opcode to identify
the type of operation. The encoding of the R/M
(register/memory) field (refer to Table 1-20) depends on
how the mode field is set. If MOD = 11

To pack instructions into memory as densely as possible,
the 8086 and 8088 CPUs utilize an efficient coding technique. Machine instructions vary from one to six bytes in
length. One-byte instructions, which generally operate on
single registers or flags, are simple to identify; the keys to
decoding longer instructions are in the first two bytes.
The format of these bytes can vary, but most instructions
follow the format shown in Figure 1-28.
The first six bits of a multibyte instruction generally contain an opcode that identifies the basic instruction type:

BYTE 1

II II
OPCODE

BYTE 3

BYTE 2

I II II
Dlw MOD REG

R/M

~

BYTE 4

BYTE 5

BYTE 6

------~-----r-----~------l

LOW DISP/DATA

I
I
I HIGH DISP/DATA I
I
I

LOW DATA

I
I
I

HIGH DATA

I
I
I

-----------~------~-----~
REGISTER OPERAND/REGISTERS TO USE IN EA CALCULATION
REGISTER OPERAND/EXTENSION OF OPCODE
REGISTER MODE/MEMORY MODE WITH DISPLACEMENT LENGTH
WORD/BYTE OPERATION
DIRECTION IS TO REGISTER/DIRECTION IS FROM REGISTER
OPERATION (INSTRUCTION) CODE

Figure 1-28 Typical 8086/88 Machine Instruction Format

1-41

210912-001

8086/8088 CPU

Table 1·17 Single·Bit Field Encoding
Field

Value

S

0
1

No sign extension
Sign extend 8·bit immediate data to 16 bits if W=1

W

0
1

Instruction operates on byte data
Instruction operates on word data

D

0
1

Instruction source is specified in REG field
Instruction destination is specified in REG field

V

0
1

Shift/ rotate count is one
Shift/rotate count is specified in CL register

Z

0
1

Repeatlloop while zero flag is clear
Repeatlloop while zero flag is set

Function

(register-to-register mode), then RIM identifies the second register operand. If MOD selects memory mode,
then R/M indicates how the effective address of the memory operand is to be calculated.

Bytes 3 through 6 of an instruction are optional fields that
usually contain the displacement value of a memory operand and/or the actual value of an immediate constant
operand.

Table 1·18 Mode (MOD) Field Encoding
CODE

EXPLANATION

00

Memory Mode, no displacement
follows*

01

Memory Mode, 8-bit
displacement follows

10

MemoryMode, 16-bit
displacement follows

11

Register Mode (no
displacement)

The displacement value may contain one or two bytes; the
language translators generate one byte whenever possible.
The MOD field indicates how many displacement bytes
are present. Following Intel convention, if the displacement is two bytes, the most-significant byte is stored second in the instruction. If the displacement is only a single
byte,the 8086 or 8088 automatically sign-extends this
quantity to l6-bits before using the information in further
address calculations. Immediate values always follow any
displacement values that may be present. The second byte
of a two-byte immediate value is the most significant.
Table 1-22 lists the instruction encodings for all
8086/8088 instructions. This table can be used to predict
the machine encoding of any ASM-86 instruction. Table
1-23 lists the 8086/8088 machine instructions in order by
the binary value of their first byte. This table can be used
to decode any machine instruction from its binary
representation. Table 1-21 is a key to the abbreviations
used in Tables 1-22 and 1-23. Figure 1-29 is a more compact instruction decoding guide.

*Except when RIM = 110, then 16-bit
displacement follows
Table 1·19 REG (Register) Field Encoding
REG

W=O

W=1

000
001
010
011
100
101
110
111

AL
CL
DL
BL
AH
CH
DH
BH

AX
CX
DX
BX
SP
BP
SI
DI

1.3 DEVICE PIN DEFINITIONS
The following paragraphs present functional descriptions
of all input/output signals and electrical descriptions of all
of the input/output pins on the 8086 and 8088 40-pin
DIP's.

1·42

210912-001

8086/8088 CPU

Table 1-20 Register/Memory Field Encoding
MOD=11

EFFECTIVE ADDRESS CALCULATION

RIM

W=O

W=1

RIM

000
001
010
011
100
101
110
111

AL
CL
OL
BL
AH
CH
OH
BH

AX
CX
OX
BX
SP
BP
SI
01

000
001
010
011
100
101
110
111

MOD=OO
(BX)+(SI)
(BX)+(OI)
(BP)+(SI)
(BP)+(OI)
(SI)
(01)
OIRECT AOORESS
(BX)

MOD=01
(BX)+(SI)+08
(BX)+(0I)+08
(BP)+(SI)+08
(BP) + (01) + 08
(SI)+08
(01)+08
(BP)+08
(BX)+08

MOD=1~

(BX)+(SI)+016
(BX)+(0I)+016
(BP)+(SI)+016
(BP) + (01) + 016
(SI)+016
(01)+ 016
(BP)+016
(BX)+016

1.3.1 Functional Description of All Signals

1.3.3 OPERATING MODES

Figure 1-30 shows the 8086/8088 DIP pin assignments
and Table 1-24 provides a complete functional description
of each device pin signal and correlates the description to
the pin number and associated signal symbol.

One of the unique features the 8086 and 8088 CPU's allow the user is the ability to select between two functional
definitions of a subset of the 8086/8088 outputs. This enables the user to tailor the intended CPU system environment. This "system tailoring" is accomplished by
strapping the CPU's MN/MX* (minimum/maximum) input pin. Table 1-28 defines the 8086 and 8088 pin assignments for both the minimum and maximum modes of
operation.

1.3.2 Electrical Description of Pins
The absolute maximum ratings for the 8086/8088 device
are as follows.

In the minimum mode, the CPU's support small systems
by strapping the MN/MX* pin to + SY. In this mode of
operation, the 8086/8088 CPU generates all bus control
signals (DT/R*, DEN*, ALE and either M/IO* or
IO/M*) and the command output signals (RD*, WR* or
INTA *). The CPU also provides a mechanism for requesting bus access (HOLDIHLDA) that is compa~ible
with bus master type controllers (e.g., the Intel 8237A
DMA Controller).

ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias
Storage Temperature

OOC to 70°C
-65°C to
+ 150°C
-1.0to +7V

Voltage on Any Pin with Respect to
GND
Power Dissipation
2. S Watt
Stresses above those listed above may cause permanent
damage to the device. These values present stress ratings
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of the device specifications is not implied.
Exposure to absolute maximum conditions for extended
periods of time may affect the device reliability.

When a bus master requires bus access in the minimum
mode, it activates the HOLD input to the CPU through its
request logic. In response to the "hold" request, The
CPU activates HLDA as an acknowledgement to the bus
master, requesting the bus, and simultaneously floats the
system bus and control lines. Since a bus request is asynchronous, the CPU samples the HOLD input on the positive transition of each CLK signal and activates HLDA at
the end of either the current bus cycle (if a bus cycle is in
progress) or idle clock period. The CPU maintains the
hold state until the bus master inactivates the HOLD input. At that time the CPU regains control of the system
bus. Note that during a "hold" state, the CPU continues
to execute instructions until a bus cycle is required.

Table 1-25 presents the D. C. voltage characteristics of the
8086/8088 CPU's. Table 1-26 lists the A.C. characteristics timing requirements and timing responses for minimum complexity systems, and Table 1-27 lists the A.C.
characteristics timing requirements and timing responses
for maximum complexity systems (using 8288 bus
controller). Figure 1-31 and Figure 1-32 presents waveforms for the minimum mode and maximum mode
operation related to the preceding A. C. characteristics
tables.

In the minimum mode, the VO-memory control line for
the 8088 CPU is the reverse of the corresponding control
line for the 8086 CPU (M/IO* on the 8086 and IO/M* on
the 8088). Since the 8088 CPU is an 8-bit device, this
conditioning provides compatibility with existing
MCS® -85 systems specific MCS-85 family devices (e.g.,
the Intel 8155/56).
1-43

210912-001

8086/8088 CPU

Lo

Hi

0

I

2

ADD

ADD
b.l.r/m
ADC
b.tJ/m
AND

4

5

8

1

ADD

ADD

w.t.r/m

b, ia

AOC
w,t.r/rn
AND

PUSH
ES
PUSH
SS
SEG
cES

POP
ES
POP
SS

PUSH
BX

AOC
b,i
AND
b.i
XOR
b.1
INC
SP
PUSH
SP

ADD
w,la
AOC
W.I
AND
W,I
XOR
W,I
INC
BP
PUSH
BP

INC
SI
PUSH
SI

INC
01
PUSH
01

JNBI
JAE
Immed

JEI
JZ
TEST

b,r/m

is,r/m

b.r/m

JBEI
JNA
XCHG
b.r/m
XCHG
SI

JNBEI
JA
XCHG
w.r/m
XCHG
01

JNS

w.r/m

JNEI
JNZ
TEST
w.r/m
XCHG
BP

JS

Immed

JBI
JNAE
Immed

MOV
b,fJ/m

MOV
w,f.rfm

CBW

CWO

MOVS

CMPS

CMPS

TeST

TeST
w,l,a

MOV
i - CH

MOV
1- OH
MOV

MOV
MOV
I - BH I - AX
MOV

MOV
1- CX

b.i.r/m

w.i.r/rn

ADD
Mr/m
ADC
b.f,r/m
AND
b,fJ/m
XOR
b.fJ/m
INC
AX
PUSH
AX

ADC
w.f.r/m
AND
w.f.r/m
XOR
w,f.r/m
INC
CX
PUSH
CX

1

JO

JNO

8

Immed
b.r/m

0
I

2
3
4

5

w,fJ/m

b,t,r/m
XOR

b,t.r/m
INC
OX
PUSH
OX

3

w,Ulm
XOR
w.t.r/rn
INC

ax

OAA

SEG

AAA

~SS

9

8
OR
b.fJ/m
SBB
b,fJ/m
SUB
b,fJ/m
CMP
b,f.r/m
DEC
AX
POP
AX

0

E

OR
W.I
SBB
W.I
SUB
W.I
CMP
W,I
DEC
BP
POP
BP

PUSH
CS
PUSH
OS
SEG
CS
SEG
OS
DEC
SI
POP
SI

JlI
JNGE
MOV

JNlI
JGE
lEA

.r,t,r/m

JNlEI
JG
POP

w,l,r/m

.r,l,r/m

JlEI
JNG
MOV

WAIT

PUSHF

POPF

SAHF

lAHF

STOS

STOS

LOOS

LOOS

SCAS

SCAS

MOV
I - OX
RET.
1.(i·SP)
ESC
2
JMP
I,d

MOV
1- BX
RET
I
ESC
3
JMP

MOV
1- SP
INT
Type 3
ESC

MOV
I - BP
INT
(Any)

MOV
I - SI

MOV
1-01

INTO

IRET

ESC

5
IN
v,w

ESC
7
OUT

si,d

4
IN
v,b

ESC
6
OUT

Cli

STI

ClO

STO

Grp 2

Grp 2

b.rfm

w.r/m

A
OR
b.tJ/m
SBB
b.l.r/m
SUB

OR
w,f.r/m
SBB
w,f.r/m
SUB
w.f.r/rn
CMP

w.t,r/m
DEC
CX
POP
CX

8
OR
w,t,r/m

SBB
w,t.r/m
SUB

b.t.rlm

w,U/rn

CMP
b.t.r/m
DEC
OX
POP
OX

CMP
w.t.r/rn
DEC
BX
POP
BX

JPI
JPE
MOV
b.l.r/m
CAll
I,d

JNPI
JPO
MOV

C
OR
b.1
SBB
b.i
SUB
b.1
CMP
b,i

DEC
SP
POP
SP

F

POP
OS
OAS
AAS
DEC
01
POP
01

6

XCHG
XCHG
XCHG
XCHG
XCHG
AX
ex
OX
BX
SP
A
MOV
MOV
MOV
MOV
MOVS
m - Al m - AX Al - m AX - m
8
MOV
MOV
MOV
MOV
MOV
1_ Al i _ Cl 1- Ol I - Bl i - AH
C
RET,
RET
lES
(I.SP)
Shift
Shilt
Shift
Shift
0
AAM
b
w
b.Y
W.Y
E lOOPNZI lOOPZI
IN
lOOP
JCXZ
lOOPNE lOOPE
b
F
REP
lOCK
REP
HLT

9

z

lOS
AAO

b,I,.

XlAT

ESC

ESC
1
JMP
d
STC

0

IN
w

OUT

OUT

b

W

CAll
d

CMC

Grp 1
b.rlm

Grp 1
w.r/m

ClC

where
modOr/m
Immed
Shill
Grp1

Grp 2

000
ADD
AOl
TEST
INC

-

0'0
ADC
ACl
NOT

DEC

CALL

00'
DA
ADA

"

0"

saa
ACA
NEG
CALL
l.id

'00
AND
$HlISAL
MUl
JMP

"0
XOA

'0'

sua
SHA
IMUl

DIY

JMP

PUSH

Ud

"

b • byte operation
d • direct
f • from CPU reg
i = immediate

m = memory

ia "'" immed. to accurn,

t • to CPU reg
v '" variable

v,b

rim

v,w

",

CMP
SAA
IOIV

-

rIm • EA is second byte

SI = short intrasegment

sr '" segment ,.egister

id • indirect
is • immed. byte, sign ext.
I • long ie. intersegment

W

= word operation

z = zero

Figure 1·29 Machine instruction Encoding Matrix
In the maximum mode (MN/MX* pin strapped to
ground), the Intel 8288 Bus controller is added to provide
sophisticated bus control functions and compatibility with
the MULTIBUS architecture, (Combining an Intel 8289
Arbiter with the 8288 permits the CPU to support multiple processors on the system bus.) The bus controller, instead of the CPU (see Figure 1-33), provides all bus
control and command outputs, This allows the pins previ-

ously delegated to these functions to be redefined to support multiprocessing functions,

1.3.4 Minimum Mode System
Overview/Description
The minimum mode 8086 (see Figure 1-34) is optimized
1·44

210912·001

8086/8088 CPU

Table 1-21 Key to Machine Instruction Encoding and Decoding
IDENTIFIER

EXPLANATION

MOD

Mode field; described in this chapter.

REG

Register field; described in this chapter.

R/M

Register/Memory field; described in this chapter.

SR

Segment register code: OO=ES, 01=CS, 10=SS, 11 =OS.

W,S, 0, V,Z

Single-bit instruction fields; described in this chapter.

DATA-S

S-bit immediate constant.

DATA-SX

8-bit immediate value that is automatically sign-extended to 16-bits
before use.

DATA-LO

Low-order byte of 16-bit immediate constant.

DATA-HI

High-order byte of 16-bit immediate constant.

(OISP-LO)

Low-order byte of optional S- or 16-bit unsigned displacement; MOD
indicates if present.

(OISP-HI)

High-order byte of optional 16-bit unsigned displacement; MOD
indicates if present.

IP-LO

Low-order byte of new IP value.

IP-HI

High-order byte of new IP value

CS-LO

Low-order byte of new CS value.

CS-HI

High-order byte of new CS value.

IP-INCS

S-bit signed increment to instruction pointer.

IP-INC-LO

Low-order byte of signed 16-bit instruction pointer increment.

IP-INC-HI

High-order byte of signed 16-bit instruction pointer increment.

AOOR-LO

Low-order byte of direct address (offset) of memory operand; EA not
calculated.

AOOR-HI

High-order byte of direct address (offset) of memory operand; EA not
calculated.
Bits may contain any value.

xxx

First 3 bits of ESC opcode.

YYY

Second 3 bits of ESC opcode.

REGS

S-bit general register operand.

REG16

16-bit general register operand.

MEMS

S-bit memory operand (any addressing mode).

MEM16

16-bit memory operand (any addressing mode).

IMMEOS

S-bit immediate operand.

IMME016

16-bit immediate operand.

SEGREG

Segment register operand.

OEST-STRS

Byte string addressed by 01.

1-45

210912-001

8086/8088 CPU

Table 1-21 Key to Machine Instruction Encoding and Decoding (continued)
IDENTIFIER

EXPLANATION

SRC-STR8

Byte string addressed by SI.

DEST-STR16

Word string addressed by 01.

SRC-STR16

Word string addressed by SI.

SHORT-LABEL

Label within ±127 bytes of instruction.

NEAR-PROC

Procedure in current code segment.

FAR-PROC

Procedure in another code segment.

NEAR-LABEL

Label in current code segment but farther than -128 to +127 bytes
from instruction.

FAR-LABEL

Labei in another code segment.

SOURCE-TABLE

XLAT translation table addressed by BX.

OPCOOE

ESC opcode operand.

SOURCE

ESC register or memory operand.

the full megabyte memory space, 64K-byte 1/0 space and
16-bit data path. The CPU directly provides all bus control (DT/R*, DEN*, ALE, M/IO*) , commands (RD*,
WR *, INTA *) and a simple CPU preemption mechanism

for small to medium (one or two boards), single CPU systems. Minimum mode system architecture is directed at
satisfying requirements of the lower to middle segment of
high performance l6-bit applications. The CPU maintains

Table 1-22 8086/88 Instruction Encoding
DATA TRANSFER
MOV = Move:

78543210

78543210
reg

78543210

71543210

71543210

I

Register/memory to/from register

100010dw

mod

rim

(DISP·lO)

(DISP·HI)

Immediate to register/memory

1 1 0 0 0 1 1 w

mod 0 0 0 rim

(DISP·lO)

(DISP·HI)

I

Immediate to register

1 0 1 1 w reg

data

dataifw-1

I

Memory to accumulator

1010000w

addr·lo

addr-hl

Accumulator to memory

1 0 1 0 0 0 1 w

addr-!o

.ddr-hi

Register/memory to segment register

1 0 0 0 1 1 1 0

mod

o

SR rim

(DISP·lO)

(DISP·HI)

Segment register to register I memory

10001100

mod

o

SR rim

(DISp·lO)

(DISP·HI)

I

Register/memory

11111111

mod 1 1 o· rim

Register

01010reg

Segment register

OOOreg110

data

78543210

I

dataitw-1

I

PUSH.. Push:

POP

I

(DISP·lO)

I

(DISP·HI)

I

(DISP·lO)

I

(DISP-HI)

I

= Pop:

Register/memory

1 0 0 0 1 1 1 1

Register

o1

Segment register

OOOreg111

mod 0 0 0 r/l'!"

I

0 1 1 reg

1-46

210912-001

8086/8088 CPU

Table 1-22 8086/88 Instruction Encoding (continued)
DATA TRANSFER (Conl'd.)

= ElCchange:

18543210

78543210

Fixed port

1 1 1 0 0 1 1 w

OATA-8

Variable port

1 1 1 0 1 1 1 w

XCHG

76543210

76543210

76543210

78543210

Register Imemory with register
Register with accumulator

IN :: Input from:
Fixed port

Variable port

OUT

=Outputto:

XLAT

= Translate byte to AL

1 1 0 1 0 1 11

LEA = Load EA to register

1 0 0 0 1 1

a1

mod

reg

rim

(OISP-LO)

(OISP-H1)

LOS

= Load pointer to OS

1 ·1 0 0 0 1

a1

mod

reg

rim

(DISP-LO)

(DISP·HI)

LES

=Load pointer to ES

1 1 0 0 0 1

aa

mod

reg

rim

(DISP·LO)

(DISP·HI)

LAHF = load AH with flags
SAHF = Store AH into flags
PUSHF
POPF

= Push flags

= Pop lIags

1 0 0 1 1 111
1 0 0 1 1 1 1
1 0 0 1 1 1

a

aa

1 0 0 1 1 1 0 1

ARITHMETIC

ADO = Add:

I

Reg/memory with register to either

OOOOOOdw

mod

reg

rim

(DISP-LO)

(DISP-HI)

Immediate to register/memory

100000sw

mod

aaa

rim

(DISP-LO)

(DISP-HI)

I

Immediate to accumulator

0OOOO10w

I

data

I

data if s: w=Ol

I

data

I

data if s: w=Ol

I

data if w=l

data

ADC = Add with carry:
Reg/memory with register to either

0OO100dw

mod

Immediate to register/memory

100000sw

mod

Immediate to accumulator

0OO1010w

data

Register/memory

1 1 1 1 1 1 1 w

mod 0 0 0 rim

Register

01000reg

AAA :: ASCII adjust for add

aa1

reg

a

1

a

rim

(DISP-LO)

(DISP-HI)

rim

(DISP-LO)

(DISP-HI)

I

(DISP-HI)

I

data if w""l

INC ... Increment:

DAA

= Decimal adjust for add

a0

1

a1

I

(DISP-LO)

I

11

1 o 0 1 1 1

1-47

210912-001

808618088 CPU

Table 1·22 8086/88 Instruction Encoding (continued)
ARITHMETIC (Cont'd.)

SUB

= Subtract:

1,654321'07654321016$4321,078:.5'43210

Reg/memory and register to either

0Ol'010dw

mod

"0

Immediate from register/memory

100000sw

mod

,o,

Immediate from accumulator

0010110w

rim
rim

(D1SP·LO)

(DISp·HI)

(DlSP'LO)

(DISP-HI)

18543210

I
I

18543210

data

I

data if s: w=Ol

I

data

I

data if s: w=Ol

I

data

1

data if s: w=l

data ifw=l

data

see = Subtract with borrow:
Aegfmemoryand register 10 either

0OOl10dw

mod

Immediate from register/memory

100000sw

mod

Immediate from accumulator

0OOl110w

reg

o,

,

rim

(DISP-LO)

(DISP-HI)

rIm

(DISP-LO)

(DISP-HI)

I
I

data if w=l

data

DEC Decrement:
Register/memory

1 1 1 1 1 1 1 w

Register

01001reg

NEG Change sign

1 1 1 1 0 1 1

w

mod001

rim

mod 0 1 1 rim

i
I

(DISP·LO)

I

(DISP-HI)

I

(DISP·LO)

I

(DISP-HI)

I

CMP = Compare:

Register/memory and register

001110dw

Immediate with register/memory

100000sw

Immediate with accumulator

o0

1 1 1 lOw

AAS ASCII adjust lor subtract

o0

,
,

mod

reg

rim

(DISP·LO)

(DISP·HI)

mod

,,,

rim

(DISP·LO)

(DISP·HI)

0 rim

J

data

,," ,
o, , ,,

OAS Decimal adjust tor subtract

o0

MUl Multiply (unsigned,

1 1 1 1 0 1 1 w

mod

,o

IMUL Integer multiply (signed)

,,1 1 0 11 w

mod

,o,

AAM ASCII adjust for multiply

(DISP·LO)

(DISP·H1)

rim

(DISP·lO)

(DISp·HI)

(DISP-LO)

(DISP·HI)

(DISP-LO)

(DISP-HI)

rim

(DISP-LO)

(DISP·HI)

00001010

(DISP·lO)

(DISP·HI)

1 1

a

1 0 1 0 0

00001010

DIV Divide (unsign,ed)

"

,

, 0 , , w

mod

,,

mod

,,,

IDIV Integer divide (signed)

1 1 1 1 0 1 , w

AAD ASCII adjust for divide

1 1 0 1

caw Convert byte to word

1 0 0 1 1 0 0 0

CWD Convert word to double word

, 0 0 1 1 0 ,0 1

o1

0 1

0 rim

LOGIC

NOT Invert

1 1 1 1 0 1 1 w

mod

SHl/SAL Shift logical I arithmetic left

1 1 0 1 0 0

vw

mod

o, o

rim

(DISP·lO)

(DISP-Hl)

0 rim

(DISP-LO)

(DISP-HI)

rim

(DISP-LO)

(DISP·Hl)

rim

(DISP·lO)

(DISP·HI)

0 0 rim

(DISP·lO)

(DISP·HI)

SHR Shift logical right

1 1 0 1

o0 vw

mod

,o
,o,

SAR Shift arithmetic right

1 1 0 1

o0

W

mod

,,,

ROl Rotate left

110100vw

mod

o

Y

1·48

210912·001

8086/8088 CPU

Table 1-22 8086/88 Instruction Encoding (continued)
LOGIC IConl'd.)

76543210

76543210

ROR Rotate right

1101QOvw

mod

ACL Rotate through carry flag left

110100vw

RCA Rotate through carry right

1 1 0 1 0 0 v w

mod

Regl memory with register to either

001000dw

mod

Immediate to register/memory
Immediate to accumulator

76543210

76543210

0 1 <1m

(DISP-LO)

(OISP·HI)

mod 0 I

o rim

(DISP-LO)

(DISP-HI)

o1

1 <1m

(OISP-LO)

{D1SP-HI}

<1m

(DISP-lO)

(DISP-HI)

1000000w

mod 1 0 0 rim

IDISP-LOI

(OISP-HI)

Q010010w

data

data if w=l

o

76543210

78543210

AND == And:
reg

I
I

data

I

dataifw=l

I

data

I

data it w=l

I

data

I

data if w=l

I

data

I

data if w=l

I

TEST = And function to flaga no result:
Register/memory and register

0OO100dw

mod

Immediate data and register/memory

1 1 1 1 0' 1

w

mod

Immediate data and accumulator

1010100w

OR

rim

(DISP-lOI

0 0 <1m

(DISP-LO)

reg

o

I

I

(DISP-HI)

(DISP-HI)

I

j

data

=Or;

Reg/memory and register to either

0000lQdw

mod

Immediate to register/memory

1000000w

mod

Immediate to accumulator

OOOQ110w

XOR

rim

(D1SP-LO)

(OlSP·HI)

0 1 rim

IDISP-LO)

(DISP-HI)

reg

o

I
I

data if w=l

data

= Exclusive or:

Reg/memory and register to either

o0

1 1 0 0 d w

Immediate to register/memory

o0

1 1 0 lOw

Immediate to accumulator

o0

1 1 0 lOw

mod

IDISP-LOI

IDISP-HI)

data

reg

rim

IOISP-LO)

IOIS.P-HI)

data

data if w=l

I
I

STRING MANIPULATION

REP_Repeat

1 1 1 1 0 0 1 z

MOVS.Move byte/word

1010010w

eMPS == Compare byte I word

1 0 1 0 0 1 1 w

SCAS.Scan byte/word

1 0 1 0 1 11 w

LODS. Load byte/wd to ALI AX

1 0 1 0 1 1 0 w

STDS. Star byte/wd from ALI A

1 0 1 0 1 0 1 w

1·49

210912-001

8086/8088 CPU

Table 1-22 8086/88 Instruction Encoding (continued)
CONTROL TRANSFER
CALL

= Call:

76543210

765432'~O

76543210

o1

IP·INC-LO

IP·INC-HI

Direct within segment

111

Indirect within segment

1111 1111

Direct intersegmenl

1 0 0 1 1 0 1 0

Indirect intersegment

JMP

0 0 0

11111111

mod

mod

o

1 0 rim

IP·hi

CS-Io

CS·hi

1 1 rim

(DISP·LO)

76543210

IOISP·HI)

I

(DISP·HI)

I

(DISP·HI)

I

(DISP·HI)

I

78543210

= Uncondltlonll Jump:

Direct within segment

11 1 0 1

o0

1

Ip·INC·LO

Direct within segment-shorl

1 1 1 0 1

o1

1

IP·INC8

Indirect within segment

111 11 111

mod 1 0 0

Direct intersegment

11 1 0 1

Indirect intersegment

11111111

o1

0

Ip·INC·HI

rim

IP·lo

mod 1 0 1

(DISP·LO)

IP-hi
CS-hi

CS·lo

RET

IOISP·LO)

IP-Io

o

76543210

rim

(DISP-LO)

= Return from CALL:

o0

Within segment

11

Within seg adding immed to SP

11000010

0 0 1 1

Intersegmenl

1 1 0 0 1

o1

1

Intersegment adding immediate to SP

1 1 0 0 1

o1

JE/JZ=Jump on equallzero

o1

1 1 0 1

JL/JNGE =Jump on less/not greater or equal
JLE/JNG =Jump on less or equal/not greater

dala-Io

dala-hi

I

0

data-Io

dala-hi

I

o0

IP-INC8

o1

1 1 1 1 0 0

Ip·INC8

o1

1 1 1 1 1 0

IP-INC8

Jet JNAE = Jump on below I not above or equal

o1

1 1 0 0 1 0

Ip·INC8

JBEI JNA = Jump on below or equal I not above

o1

1 1 0 1 1 0

IP-INC8

JP I JPE = Jump on parity I parity even

o1

1 1 1 0 1 0

IP·INC8

JO=Jumpon overflow

o1

1 1 0 0 0 0

Ip·INCB

JS=Jump on sign

o1

1 1 1 0 0 0

Ip·INCB

JNEI JNZ., Jump on not equal I not zerO

o1

1 1 0 1

o1

Ip·INCB

JNL/JGE=Jumpon not less/greater or equal

o1

1 1 1 1 0 1

IP-INC8

JNLE/JG =Jump on not less or equal/greater

o1

11 11 11

IP-INC8

JNBI JAE. Jump on not below I above or equal

o1

1 1 0 0 1 1

IP·INCB

JN8E/JA=Jump on not below or equal/above

o1

1 1 0 1 1 1

IP~INCB

JNP/JPO_Jumpon not par/parodd

o

1 1 1 1 0 1 1

Ip·INC8

JNO =Jump on not overflow

o1

1 1 0 0 0 1

IP·INCB

1-50

210912-001

8086/8088 CPU

Table 1-22 8086/88 Instruction Encoding (continued)
CONTROL TRANSFER (Cont'd.)
RET = Return from CALL:

76543210

78543210

JNS=Jump on not slg"

0' , 11001

IP-INC8

LOOP = loop ex times

" ,o0 0 1 0

IP-INC8

LOOPZ/lOOPE= Loop while zero/equal

1 1 1 0 0 0 0 1

IP-1NC8

1 1 1 0 0 0 0 0

Ip·INC8

,,

1 0 0 0 1 1

IP-INC8

Type specified

1 1 0 0 1 1 0'

DATA·8

Type3

11001 , 0 0

INTO = Interrupt on overllow

1 1 0 0 1 , , 0

IRET = Interrupt return

1 1 0 0 1 1

LOOPNZlLOOPNE

=Loop while nol zero/equa I

JCXZ=Jump on ex zero

76543210

78543210

76543210

78543210

INT = Interrupt:

l

,,

PROCESSOR CONTROL

eLC =Clear carry

11111000

CMC =Complement carry

11110101

STC = Set carry

1111 1 0 0 1

etD =Clear direction

"

STD

=Set direction

,

1 1 1 0 0

1111 1101

eLi = Clear mterrupt

1111 1 0 1 0

STI = Set interrupt

"

HLT=Halt

"

WAIT=Wait

1 0 0 1 1 0 1 1

ESC = Escape (to extern,,1 device)

1 1 0 1 1 x x x

LOCK

=Bus lock prefix

SEGMENT = Override prefix

,
,

11011
1 0 1 0 0

modyyyr/m

I

(DISP·LO)

I

(DISP·HI)

I

1 1 1 1 0 0 0 0

o0

1 reg 1 1 0

1-51

210912-001

8086/8088 CPU

(HOLD, HLDA) compatible with existing DMA controllers (e.g., 8259A Interrupt Controller).
In the minimum mode the 8088 CPU provides an SSO
status output. This output is equivalent to SO in the maximum mode and can be decoded with DT/R*
and - IO/M*, which are equivalent to S 1* and S2 * respectively, to provide the same CPU cycle status information (see Table 1-29). This type of decoding could be used
in a minimum mode 8088-based system to allow dynamic
RAM refresh during passive CPU cycle.

1.3.5 Maximum Mode System
Overview/Description
The maximum mode (see Figure 1-35) extends the system
architecture to support multiprocessor configurations and
local instruction set extension processors (coprocessors).
By adding the 8288 bipolar bus controller, the 8086 outputs assigned to bus control and commands in the minimum mode are redefined to allow these extensions and
enhance general system performance. Specifically, (1)
two prioritized levels of processor preemption
(RQ*/GTO*, RQ*/GTl *) allow multiple processors to reside on the 8086's local bus and share its interface to the
system bus, (2) Queue status (QSO, QSI) is available to
allow external devices like ICETM-86 or special instruction set extension co-processors (such as the 8087 Numeric Co-processor) to track the CPU instruction
execution, (3) access control to shared resources in multiprocessor systems is supported by a hardware bus lock
mechanism and (4) system command and configuration
options are expanded via devices like the 8288 bus controller and 8289 bus arbiter.

QUEUE STATUS

The queue status indicates what information is being removed from the internal queue and when the queue is being reset due to a transfer of control (Thble 1-30). By
monitoring the SO*, S I *, S2 * status lines for instructions
entering the 8086 (1, 0, 0 indicates code access while AO

and BHE* indicate word or byte) and QSO, QSI for instructions leaving the 8086's internal queue, it is possible
to track the instruction execution. Since instructions are
executed from the 8086's internal queue, the queue status
is presented each CPU clock cycle and is not related to the
bus cycle activity. This mechanism (1) allows a
co-processor to detect execution of an ESCAPE instruction which directs the co-processor to perform a specific
task and (2) allows ICETM-86 to trap execution of a specific memory location.
An example of a circuit used by ICE is given in Figure
1-36. The first up down counter tracks the depth of the
queue while the second captures the queue depth on a
match. The second counter decrements on further fetches
from the queue until the queue is flushed or the count goes
to zero indicating execution of the match address. The
first counter decrements on fetch from the queue (QSO =
I) and increments on code fetches into the queue. Note
that a normal code fetch will transfer two bytes into the
queue so two clock increments are given to the counter
(T201 and T301) unless a single byte is loaded over the
upper half of the bus (AO-P is high). Since the execution
unit (EU) is not synchronized to the bus interface unit
(BIU), a fetch from the queue can occur simultaneously
with a transfer into the queue. The Exclusive-OR gate
driving the ENP input of the first counter allows these
simultaneous operations to cancel each other and not
modify the queue depth.

HARDWARE LOCK

To address the problem of controlling access to shared
resources, the maximum mode 8086 provides a hardware
LOCK* output. The LOCK* output is activated through
the instruction stream by execution of the LOCK prefix
instruction. The LOCK* output goes active in the first
CPU clock cycle following execution of the prefix and
remains active until the clock following the completion of
the instruction following the LOCK prefix. To provide
bus access control in multiprocessor systems, the LOCK*
signal should be incorporated into the system bus arbitration logic resident to the CPU.

Table 1·23 Machine Instruction Decoding Guide
1ST BYTE
BINARY
HEX
00
01
02
03
04
05
06
07

0000
0000
0000
0000
0000
0000
0000
0000

2ND BYTE

0000 MOD REG RIM
0001 MOD REG RIM
0010 MOD REG RIM
0011 MOD REG RIM
0100 DATA-S
0101 DATA-LO
0110
0111

BYTES 3, 4, 5, 6
(DISP-LO),(DISP-HI)
(DISP-LO).(DISP-HI)
(DISP-LO).(DISP-HI)
(DISP-LO).(DISP-HI)
DATA-HI

1-52

ASM·86 INSTRUCTION FORMAT
ADD
ADD
ADD
ADD
ADD
ADD
PUSH
POP

REGS/MEMS,REGS
REG16/MEM16.REG16
REGS.REGS/MEMS
REG16.REG161 M EM16
AL.IMMEDS
AX.IMMED16
ES
ES

210912-001

8086/8088 CPU

Table 1-23 Machine Instruction Decoding Guide (continued)
1ST BYTE
HEX
BINARY

2ND BYTE

08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
20
21
22
23
24
25
26

0000
0000
0000
0000
0000
0000
0000
0000
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
0010
0010

1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110

MOD REG
MOD REG
MOD REG
MOD REG
DATA-8
DATA-LO

RIM
RIM
RIM
RIM

MOD REG
MOD REG
MOD REG
MOD REG
DATA-8
DATA-LO

RIM
RIM
RIM
RIM

MOD REG
MOD REG
MOD REG
MOD REG
DATA-B
DATA-LO

RIM
RIM
RIM
RIM

MOD REG
MOD REG
MOD REG
MOD REG
DATA-B
DATA-LO

RIM
RIM
RIM
RIM

27
2B
29
2A
2B
2C
20
2E

0010
0010
0010
0010
0010
0010
0010
0010

0111
1000
1001
1010
1011
1100
1101
1110

MOD REG
MOD REG
MOD REG
MOD REG
DATA-B
DATA-LO

2F
30
31
32
33
34
35
36

0010
0011
0011
0011
0011
. 0011
0011
0011

1111
0000
0001
0010
0011
0100
0101
0110

MOD REG
MOD REG
MOD REG
MOD REG
DATA-B
DATA-LO

BYTES 3,4,5,6
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI

ASM-86 INSTRUCTION FORMAT
OR
OR
OR
OR
OR
OR
PUSH

REG81 MEM8,REG8
REG16/MEM16,REG16
REG8,REG8/MEM8
REG16, REG161 MEM16
AL,IMMED8
AX,IMMED16
CS

(not used)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI

RIM
RIM
RIM
RIM

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO,(DISP-HI)
DATA-HI

RIM
RIM
RIM
RIM

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI

1-53

ADC
ADC
ADC
ADC
ADC
ADC
PUSH
POP
SBB
SBB
SBB
SBB
SBB
SBB
PUSH
POP
AND
AND
AND
AND
AND
AND
ES:
DAA
SUB
SUB
SUB
SUB
SUB
SUB
CS:
DAS
XOR
XOR
XOR
XOR
XOR
XOR
SS:

REG81 M EM8, REG8
REG161 MEM16, REG16
REG8,REG8/MEM8
REG16, REG161 M EM16
AL,IMMED8
AX,IMMED16
SS
SS
REG81 MEM8, REG8
REG16/MEM16,REG16
REG8,REG8/MEMB
REG16, REG161 M EM16
AL,IMMEDB
AX,IMMED16
OS
OS
REGB/MEMB,REGB
REG16/MEM16,REG16
REGB,REGB/MEMB
REG16,REG16/MEM16
AL,IMMEDB
AX,IMMED16

(segment override
prefix)
REGSI M EMB, REGB
REG16/MEM16,REG16
REGB, REGBI MEMB
REG16,REG16/MEM16
AL,IMMEDB
AX,IMMED16

(segment override
prefix)
REGB/MEMB,REGB
REG16/MEM16,REG16
REGB,REGB/MEMB
REG16,REG161 MEM16
AL,IMMED8
AX,IMMED16

(segment override
prefix)

210912-001

8086/8088 CPU

Table 1-23 Machine Instruction Decoding Guide (continued)
1ST BYTE
HEX
BINARY

37
38
39
3A
3B
3C
3D
3E

0011
0011
0011
0011
0011
0011
0011
0011

0110
1000
1001
1010
1011
1100
1101
1110

3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67

0011
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0110
0110
0110
0110
0110
0110
0110
0110

1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111

2ND BYTE

MOD REG
MOD REG
MOD REG
MOD REG
DATA-8
DATA-LO

RIM
RIM
RIM
RIM

BYTES 3,4,5,6

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI

ASM-86 INSTRUCTION FORMAT
AAA
CMP
CMP
CMP
CMP
CMP
CMP
DS:
AAS
INC
INC
INC
INC
INC
INC
INC
INC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
POP
POP
POP
POP
POP
POP
POP
POP
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)

1-54

REG8/MEM8,REG8
REG16/MEM16,REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
AL,IMMED8
AX,IMMED16
(segment override
prefix)
AX
CX
DX
BX
SP
BP
SI
DI
AX
CX
DX
BX
SP
BP
SI
DI
AX
CX
DX
BX
SP
BP
SI
DI
AX
CX
DX
BX
SP
BP
SI
DI

210912-001

8086/8088 CPU

Table 1-23 Machine Instruction Decoding Guide (continued)
1ST BYTE
HEX
BINARY

2ND BYTE

68
69
6A
6B
6C
60
6E
6F
70
71
72

0110
0110
0110
0110
0110
0110
0110
0110
0111
0111
0111

1000
1001
1010
1011
1100
1101
1110
1111
0000 IP-INC8
0001 IP-INC8
0010 IP-INC8

73

0111

0011

IP-INC8

74
75
76
77
78
79
7A
7B
7C
70
7E
7F
80

0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
1000

0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000

IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
MOD 000 RIM

80

1000

0000

MOD 001 RIM

80

1000

0000

MOD010 RIM

80

1000

0000

MOD011 RIM

80

1000

0000 MOD100R/M

80

1000

0000

MOD101 RIM

80

1000

0000

MOD110 RIM

80

1000

0000

MOD 111 RIM

81

1000

0001

MODOOOR/M

81

1000

0001

MOD 001 RIM

81

1000

0001

MOD010R/M

81

1000

0001

MOD011 RIM

BYTES 3,4,5,6

(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI

1-55

ASM-86 INSTRUCTION FORMAT

(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
JO
JNO
JB/JNAEI
JC
JNB/JAEI
JNC
JE/JZ
JNE/JNZ
JBE/JNA
JNBE/JA
JS
JNS
JP/JPE
JNP/JPO
JLlJNGE
JNLlJGE
JLE/JNG
JNLE/JG
ADD

SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
REG8/MEM8,IMMED8

OR

REG8/MEM8,IMMED8

ADC

REG8/MEM8,IMMED8

SBB

REG8/MEM8,IMMED8

AND

REG8/MEM8,IMMED8

SUB

REG8/MEM8,IMMED8

XOR

REG8/MEM8,IMMED8

CMP

REG8/MEM8,IMMED8

ADD

REG16/MEM16,IMMED16

OR

REG16/MEM16,IMMED16

ADC

REG16/MEM16,IMMED16

SBB

REG16/MEM16,IMMED16

210912-001

8086/8088 CPU

Table 1·23 Machine Instruction Decoding Guide (continued)
1ST BYTE
HEX
BINARY

2ND BYTE

81

1000

0001

MOD 100 RIM

81

1000

0001

MOD101 RIM

81

1000

0001

MOD110R/M

81

1000

0001

MOD 111 RIM

82

1000

0010

MOD 000 RIM

82
82

1000
1000

0010 MOD 001 RIM
0010 MOD010 RIM

82

1000

0010

82
82

1000
1000

0010 MOD100 RIM
0010 MOD 101 RIM

82
82

1000
1000

0010 MOD110R/M
0010 MOD 111 RIM

83

1000

0011

MODOOOR/M

83
83

1000
1000

0011
0011

MOD001 RIM
MOD010 RIM

83

1000

0011

MOD011 RIM

83
83

1000
1000

0011
0011

MOD 100 RIM
MOD101 RIM

83
83

1000
1000

0011
0011

MOD 110 RIM
MOD 111 RIM

84
85
86
87
88
89
8A
8B
8C
8C
8D
8E
8E
8F
8F
8F

1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000

0100
0101
0110
0111
1000
1001
1010
1011
1100
1100
1101
1110
1110
1111
1111
1111

MOD REG RIM
MOD REG RIM
MOD REG RIM
MOD REG RIM
MOD REG RIM
MOD REG RIM
MOD REG RIM
MOD REG RIM
MOD OSR RIM
MOD1--R/M
MOD REG RIM
MODOSR RIM
MOD 1-- RIM
MODOOO RIM
MOD 001 RIM
MOD010 RIM

MOD011 RIM

BYTES 3,4,5,6
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-8

ASM-86 INSTRUCTION FORMAT
AND

REG16/MEM16,IMMED16

SUB

REG16/MEM16,IMMED16

XOR

REG16/MEM16,IMMED16

CMP

REG16/MEM16,IMMED16

ADD

REG8/MEM8,IMMED8

(not used)
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8

ADC

REG8/MEM8,IMMED8

SBB

REG81 MEM8,IMMED8

(not used)
(DISP-LO),(DISP-HI),
DATA-8

SUB

REG8/MEM8,IMMED8

(not used)
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-SX

CMP

REG8/MEM8,IMMED8

ADD

REG16/MEM16,IMMED8

(DISP-LO), (DISP-HI),
DATA-SX
(DISP-LO),(DISP-HI),
DATA-SX

ADC

REG161 M EM16,IMMED8

SBB

REG16/MEM16,IMMED8

(not used)

(not used)
(DISP-LO),(DISP-HI),
DATA-SX

SUB

REG16/MEM16,IMMED8

(DISP-LO),(DISP-HI),
DATA-SX
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)

CMP

REG16/MEM16,IMMED8

TEST
TEST
XCHG
XCHG
MOV
MOV
MOV
MOV
MOV

REG8/MEM8,REG8
REG16/MEM16,REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
REG8/MEM8,REG8
REG16/MEM16/REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
REG16/MEM16,SEGREG

(not used)

(not used)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)

LEA
MOV

REG16,MEM16
SEGREG,REG16/MEM16

(not used)
(DISP-LO),(DISP-HI)

POP

REG16/MEM16

(not used)
(not used)

1-56

210912-001

8086/8088 CPU

Table 1·23 Machine Instruction Decoding Guide (continued)
1ST BYTE
HEX
BINARY
8F
8F
8F
8F
8F
90
91
92
93
94
95
96
97
98
99
9A

1000 1111
1000 1111
1000 1111
1000 1111
1000 1111
1001 0000
1001 0001
1001 0010
1001 0011
1001 0100
1001 0101
1001 0110
1001 0111
1001 1000
1001 1001
1001 1010

9B
9C
90
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB

1001
1001
1001
1001
1001
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1011
1011
1011
1011
1011
1011
1011
1011
1011
1011
1011
1011

1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
1011
0100
0101
0110
0111
1000
1001
1010
1011

2ND BYTE

BYTES 3,4,5,6

MOD011 RIM
MOD 100 RIM
MOD101 RIM
MOD110 RIM
MOD111 RIM

DISP-LO

DISP-HI,SEG-LO,
SEG-HI

ADDR-LO
ADDR-LO
ADDR-LO
ADDR-LO

ADDR-HI
ADDR-HI
ADDR-HI
ADDR-HI

DATA-8
DATA-LO

DATA-HI

DATA-8
DATA-8
DATA-8
DATA-8
DATA-8
DATA-8
DATA-8
DATA-8
DATA-LO
DATA-LO
DATA-LO
DATA-LO

DATA-HI
DATA-HI
DATA-HI
DATA-HI

ASM-86 INSTRUCTION FORMAT
(not used)
(not used)
(not used)
(not used)
(not used)
NOP
XCHG
XCHG
XCHG
XCHG
XCHG
XCHG
XCHG
CBW
CWO
CALL
WAIT
PUSHF
POPF
SAHF
LAHF
MOV
MOV
MOV
MOV
MOVS
MOVS
CMPS
CMPS
TEST
TEST
STOS
STOS
LODS
LODS
SCAS
SCAS
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV

1-57

(exchange AX, AX)
AX,CX
AX,DX
AX,BX
AX,SP
AX,BP
AX,SI
AX,DI

FAR_PROC

AL,MEM8
AX,MEM16
MEM8,AL
MEM16,AL
DEST -STR8, SRC-STR8
DEST-STA16,SRC-STR16
DEST -STR8,SRC-STA8
DEST-STR16,SRC-STR16
AL,IMMED8
AX,IMMED16
DEST-STR8
DEST-STR16
SRC-STR8
SRC-STR16
DEST-STR8
DEST-STA16
AL,IMMED8
CL,IMMED8
DL,IMMED8
BL,IMMED8
AH,IMMED8
CH,IMMED8
DH,IMMED8
BH,IMMED8
AX,IMMED16
CX,IMMED16
DX,IMMED16
BX,IMMED16

210912-001

8086/8088 CPU

Table 1-23 Machine Instruction Decoding Guide (continued)
1ST BYTE

HEX
BC
BD

BINARY

2ND BYTE

BF
CO
C1
C2
C3
C4
C5
C6

1011 1100 DATA-LO
1011 1101 DATA-LO
1011 1110 DATA-LO
1011 1111 DATA-LO
1100 0000
1100 0001
1100 0010 DATA-LO
1100 0011
1100 0100 MOD REG RIM
1100 0101 MOD REG RIM
1100 0110 MODOOOR/M

C6
C6
C6
C6
C6
C6
C6
C7

1100
1100
1100
1100
1100
1100
1100
1100

0110
0110
0110
0110
0110
0110
0110
0111

MOD 001 RIM
MOD010 RIM
MOD011 RIM
MOD 100 RIM
MOD101 RIM
MOD110 RIM
MOD 111 RIM
MOD 000 RIM

C7
C7
C7
C7
C7
C7
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
DO
DO
DO
DO
DO
DO
DO
D1
D1
D1
D1
D1

1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101

0111
0111
0111
0111
0111
0111
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0000
0000
0000
0000
0000
0000
0000
0001
0001
0001
0001
0001

MOD 001 RIM
MOD010R/M
MOD011 RIM
MOD 100 RIM
MOD101 RIM
MOD110R/M
MOD 111 RIM

BE

DATA-LO

BYTES 3,4,5,6
DATA-HI
DATA-HI
DATA-HI
DATA-HI

MOV
MOV
MOV
MOV

SP,IMMED16
BP,IMMED16
SI,IMMED16
DI,IMMED16

(not used)
(not used)
DATA-HI
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI),
DATA-8

RET
RET
LES
LDS
MOV

IMMED16 (intraseg)

(intrasegment)
REG16,MEM16
REG16,MEM16
MEM8,IMMED8

(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI

MOV

MEM16,IMMED16

(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used
(not used)
(not used)
DATA-HI

DATA-8

MOD 000 RIM
MOD 001 RIM
MOD010 RIM
MOD011 RIM
MOD100R/M
MOD101 RIM
MOD110R/M
MOD 111 RIM
MOD 000 RIM
MOD 001 RIM
MOD010R/M
MOD011 RIM
MOD100R/M

ASM-86 INSTRUCTION FORMAT

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)

RET
RET
INT
INT
INTO
IRET
ROL
ROR
RCL
RCR
SALISHL
SHR

IMMED16 (intersegment)
(intersegment)
3
IMMED8

REG8/MEM8,1
REG8/MEM8,1
REG8/MEM8,1
REG8/MEM8,1
REG8/MEM8,1
REG8/MEM8,1

(not used)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)

1-58

SAR
ROL
ROR
RCL
RCR
SALISHL

REG8/MEM8,1
REG16/MEM16,1
REG16/MEM16,1
REG161 MEM16, 1
REG16/MEM16,1
REG16/MEM16,1

210912-001

8086/8088 CPU

Table 1-23 Machine Instruction Decoding Guide (continued)
1ST BYTE
HEX
BINARY
01
01
01
02
02
02
02
02
02
02
02
03
03
03
03
03
03
03
03
04
05
06
07
08

1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101

2ND BYTE
M00101 RIM
M00110 RIM
MOD 111 RIM
MOD 000 RIM
MOD 001 RIM
M00010 RIM
MOD 011 RIM
M00100 RIM
M00101 RIM
MOD 110 RIM
M00111 RIM
MOOOOO RIM
MOD 001 RIM
MOO010R/M
M00011 RIM
M00100 RIM
M00101 RIM
MOD 110 RIM
M00111 RIM
00001010
00001010

OF
EO

0001
0001
0001
0010
0010
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
0011
0011
0011
0011
0100
0101
0110
0111
1000
1XXX
1101 1111
1110 0000

MOD 000 RIM
MOOYYY RIM
M00111 RIM
IP-INC-8

E1

1110

0001

IP-INC-8

E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5

1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1111
1111
1111
1111
1111
1111

0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101

IP-INC-8
IP-INC-8
OATA.-8
OATA-8
OATA-8
OATA-8
IP-INC-LO
IP-INC-LO
IP-LO
IP-INC8

BYTES 3,4,5,6
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)

(OISP-LO), (OISP-HI)

IP-INC-HI
IP-INC-HI
IP-HI,CS-LO,CS-HI

1-59

ASM-86 INSTRUCTION FORMAT
REG16/MEM16,1

SHR
(not used)
SAR
ROL
ROR
RCL
RCR
SALISHL
SHR
(not used)
SAR
ROL
ROR
RCL
RCR
SALISHL
SHR
(not used)
SAR
AAM
AAO
(not used)
XLAT

SOURCE-TABLE

ESC

OPCOOE,SOURCE

REG16/MEM16,1
REG8/MEM8,CL
REG8/MEM8,CL
REG8/MEM8,CL
REG8/MEM8,CL
REG8/MEM8,CL
REG8/MEM8,CL
REG8/MEM8,CL
REG16/MEM16,CL
REG16/MEM16,CL
REG16/MEM16,CL
REG16/MEM16,CL
REG16/MEM16,CL
REG16/MEM16,CL
REG16/MEM16,CL

LOOPNEI SHOR~LABEL
LOOPNZ
LOOPEI SHORT-LABEL
LOOPZ
SHORT-LABEL
LOOP
JCXZ
SHORT-LABEL
IN
AL,IMME08
IN
AX,IMME08
OUT
AL,IMME08
OUT
AX,IMME08
CALL
NEAR-PROC
JMP
NEAR-LABEL
JMP
FAR-LABEL
SHORT-LABEL
JMP
IN
AL,OX
IN
AX,OX
OUT
AL,OX
OUT
AX,OX
(prefix)
LOCK
(not used)
REPNE/REPNZ
REP/REPE/REPZ
HLT
CMC

210912-001

8086/8088 CPU

Table 1-23 Machine Instruction Decoding Guide (continued)
1ST BYTE
BINARY
HEX

2ND BYTE

BYTES 3,4,5,6
(DISP-LO),(DISP-HI),
DATA-8

F6

1111

0110

MOD 000 RIM

F6
F6
F6
F6
F6
F6
F6
F7

1111
1111
1111
1111
1111
1111
1111
1111

0110
0110
0110
0110
0110
0110
0110
0111

MOD 001 RIM
MOD010 RIM
MOD011 RIM
MOD100 RIM
MOD101 RIM
MOD 110 RIM
MOD 111 RIM
MOD 000 RIM

F7
F7
F7
F7
F7
F7
F7
F8
F9
FA
FB
FC
FD
FE
FE
FE
FE
FE
FE
FE
FE
FF
FF
FF
FF
FF
FF
FF
FF

1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111

0111
0111
0111
0111
0111
0111
0111
1000
1001
1010
1011
1100
1101
1110
1110
1110
1110
1110
1110
1110
1110
1111
1111
1111
1111
1111
1111
1111
1111

MOD 001 RIM
MOD010 RIM
MOD011 RIM
MOD100 RIM
MOD101 RIM
MOD110 RIM
MOD 111 RIM

MOD 000 RIM
MOD 001 RIM
MOD010 RIM
MOD011 RIM
MOD100 RIM
MOD101 RIM
MOD110 RIM
MOD 111 RIM
MODOOOR/M
MOD001 RIM
MOD010 RIM
MOD011 RIM
MOD100 RIM
MOD101 RIM
MOD110 RIM
MOD 111 RIM

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI),
DAT A-LO, DAT A-H I
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)

1-60

ASM-86 INSTRUCTION FORMAT
TEST

REG8/MEM8,IMMED8

(not used)
NOT
NEG
MUL
IMUL
DIV
IDIV
TEST

REG8/MEM8
REG8/MEM8
REG8/MEM8
REG8/MEM8
REG8/MEM8
REG8/MEM8
REG16/MEM16,IMMED16

(not used)
NOT
NEG
MUL
IMUL
DIV
IDIV
CLC
STC
CLI
STI
CLD
STD
INC
DEC
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
INC
DEC
CALL
CALL
JMP
JMP
PUSH
(not used)

REG16/MEM16
REG16/MEM16
REG16/MEM16
REG16/MEM16
REG16/MEM16
REG16/MEM16

REG8/MEM8
REG8/MEM8

MEM16
MEM16
REG16/MEM16 (intra)
MEM16 (intersegment)
REG161 MEM16 (intra)
MEM16 (intersegment)
MEM16

210912-001

8086/8088 CPU

Table 1-24 8086/8088 Device Pin Descriptions
The following pin function descriptions are for iAPX 86 systems in either minimum or maximum mode. The "Local
Bus" in these descriptions is the direct multiplexed bus interface connection to the 8086 (without regard to additional
bus buffers).
Symbol

Pin No.

AD'S- AD o 2-16,39

A, g1Ss,
A , s1Ss,
A 17/S 4,
A , s1S3

35-38

Type

Name and Function

1/0

Address Data Bus: These lines constitute the time multiplexed memoryllO address (T 1)
and data (T 2, T3, Tw, T4) bus. Ao is analogous to SHE for the lower byte of the data bus,
pins DrDo. It is LOW during T, when a byte is to be transferred on the lower portion of
the bus in memory or 1/0 operations. Eight-bit oriented devices tied to the lower half
would normally use Ao to condition chip select functions. (See SHE.) These lines are
active HIGH and float to 3-state OFF during interrupt acknowledge and local bus "hold
acknowledge:'

0

Address/StatuI: During T1 these are the four most sign ificant address lines for memory operations. During 1/0
operations these lines are LOW. During memory and 110
operations, status information is available on these
lines during T 2, T3, Tw, and T 4. The status of the interrupt
enable FLAG bit (Ss) is updated at the beginning of each
CLK cycle. A'7/S4 and A,s1S3 are encoded as shown.
This information indicates which relocation register is
presently being used for data accessing.

A17'S4

A,oIS3

Characteristics

o (LOW)

0

Alternate Data
Stack
Code or None
Data

0

1

1 (HIGH)
1
s6 is 0
(LOW)

0
1

These lines float to 3-state OFF during local bus "hold
acknowledge."
SHE/S7

34

0

Bus High Enable/Status: During T, the bus high enable
signal (SHE) should be used to enable data onto the
most significant half of the data bus, pins D,s-D s. Eightbit oriented devices tied to the upper half of the bus
would normally use SHE to condition chip select functions. SHE is LOW during T, for read, write, and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus. The S7 status information is available during T 2, T 3, and T4. The signal is active
LOW, and floats to 3-state OFF in "hold." It is LOW during T 1 for the first interrupt acknowledge cycle.

iRE

Ao

0

0

Whole word

0

1

Upper byte froml
to odd address

1

0

Lower byte froml
to even address

1

1

None

Characterlsllcs

AD

32

0

READY

22

I

READY: is the acknowledgement from the addressed memory or 110 device that it will
complete the data transfer. The READY signal from memory/IO is synchronized by the
8284A Clock Generator to form READY. This signal is active HIGH. The 8086 READY input is not synchronized. Correct operation is not guaranteed if the setup and hold
times are not met.

INTR

18

I

Interrupt Request: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt
acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table
located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.

TEST

23

I

TEST: input is examined by the "Wait" instruction. If the TEST input is LOW execution
continues, otherwise the processor waits in an "Idle" state. This input is synchronized
internally during each clock cycle on the leading edge of CLK.

Read: Read strobe indicates that the processor is performing a memory of 110 read cycle, depending on the state of the S2 pin. This signal is used to read devices which
reside on the 8086 local bus. RD is active LOW during T2, T3 and Tw of any read cycle,
and is guaranteed to remain HIGH in T2 until the 8086 local bus has floated.
This signal floats to 3-state OFF in "hold acknowledge."

1-61

210912-001

8086/8088 CPU

Table 1·24 8086/8088 Device Pin Descriptions (continued)
Symbol

Pin No.

Type

NMI

17

I

Non·maskable interrupt: an edge triggered input which causes a type 2 interrupt. A
subroutine is vectored to via an interrupt vector lookup table located in system
memory. NMI is not maskable internally by software. A transition from a lOW to HIGH
initiates the interrupt at the end of the current instruction. This input is internally syn·
chronized.

RESET

21

I

Reset: causes the processor to immediately terminate its present activity. The signal
must be active HIGH for at least four clock cycles. It restarts execution, as described in
the Instruction Set description, when RESET returns lOW. RESET is internally syn·
chronized.

ClK

19

I

Clock: provides the basic timing for the processor and bus controller. It is asymmetric
with a 33% duty cycle to provide optimized internal timing.

Vee

40

GND

1,20

MN/MX

33

Name and Function

Vcc: + 5V power supply pin.
Ground
I

Minimum/Maximum: indicates what mode the processor is to operate in. The two
modes are discussed in the following sections.

=

The fol/owing pin function descriptions are for the 808618288 system in maximum mode (i.e., MNIMX VssJ. Only the
pin functions which are unique to maximum mode are described; aI/ other pin functions are as described above.
S2, S" So

26-28

0

Status: active during T4, T" and T2 and is returned to the
passive state (1,1,1) during T3 or during Tw when READY
is HIGH. This status is used by the 8288 Bus Controller
to generate all memory and 1/0 access control signals.
Any change by 5;,5;, or
during T4 is used to indicate
the beginning of a bus cycle, and the return to the pas·
sive state in T3 or Tw is used to indicate the end of a bus
cycle.

So

These signals float to 3-state OFF in "hold acknowledge." These status lines are encoded as shown.

RO/GTo,
RCi/GT,

30,31

110

$2

$,

So

Characteristics

OILOW)

0

0

0
0
0

0

,

1
1

0

,

0
0

0

1
1

1
1

0

Interrupt
Acknowledge
Read 1/0 Port
Write 1/0 Port
Hall
Code Access
Read Memory
Write Memory
Passive

1 (HIGH)

1
1
1

Request/Grant: pins are used by other local bus masters to force the processor to
release the local bus at the end of the processor's current bus cycle. Each pin is
bidirectional with RO/GT o having higher priority than RO/GT,. RO/GT has an internal
pull-up resistor so may be left unconnected. The request/grant sequence is as follows
(see Figure 9):
1. A pulse of 1 ClK wide from another local bus master indicates a local bus request
("hold") to the 8086 (pulse 1).
2. During a T4 or T, clock cycle, a pulse 1 ClK wide from the 8086 to the requesting master
(pulse 2), indicates that the 8086 has allowed the local bus to float and that it will enter
the "hold acknowledge" state at the next ClK. The CPU's bus interface unit is disconnected logically from the local bus during "hold acknowledge."
3. A pulse 1 ClK wide from the requesting master indicates to the 8086 (pulse 3) that
the "hold" request is about to end and that the 8086 can reclaim the local bus at the
next CLK.
Each master-master exchange of the local bus is a sequence of 3 pulses. There must
be one dead CLK cycle after each bus exchange. Pulses are active lOW.
If the request is made while the CPU is performing a memory cycle, it will release the local
bus during T4 of tne cycle when all the following conditions are met:
1.
2.
3.
4.

Request occurs on or before T2 ·
Current cycle is not the low byte of a word (on an odd address).
Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
A locked instruction is not currently executing.

1·62

210912-001

8086/8088 CPU

Table 1-24 8086/8088 Device Pin Descriptions (continued)
Symbol

Pin No.

Type

Name and Function
If the local bus is idle when the request is made the two possible events will follow:
1. local bus will be released during the next clock.
2. A memory cycle will start within 3 clocks. Now the four rules for a currently active
memory cycle apply with condition number 1 already satisfied.

~

QSh QSo

29

0

LOCK: output indicates that other system bus masters are not to gain control of the
system bus while lOCK is active lOW. The lOCK signal is activated by the "LOCK"
prefix instruction and remains active until the completion of the next instruction. This
signal is active lOW, and floats to 3·state OFF in "hold acknowledge."

24, 25

0

Queue StatuI: The queue status
QSo
CHARACTERISTICS
Q~
is valid during the ClK cycle
o
(LOW)
0 No Operation
after which the queue operation
1 First Byte of Op Code from Queue
is performed.
(HIGH) 0 Empty the Queue
QS, and QSo provide status to
1
1 Subsequent Byte from Queue
allow external tracking of the
internal 8086 instruction queue.

~

The fol/owing pin function descriptions are for the BOB6 in minimum mode (i.e., MN/MX = Vee!- Only the pin functions which
are unique to minimum mode are described; aI/ other pin functions are as described above.

M/iO

28

0

Status line: logically equivalent to S2 in the maximum mode. It is used to distinguish a
memory access from an I/O access. MIlO becomes valid in the T4 preceding.!. bus cycle
and remains valid until the final T4 of the cycle (M = HIGH, 10 = LOW). MilO floats to
3·state OFF in local bus "hold acknowledge."

WJ:f

29

0

Write: indicates that the processor is performing a write memory or write I/O cycle,
depending on the state of the M/iO signal. WR is active for T 2, T3 and Tw of any write cy·
cle. It is active LOW, and floats to 3·state OFF in local bus "hold acknowledge."

INTA

24

0

INTA is used as a read strobe for interrupt acknowledge cycles. It is active LOW during
T 2, T3 and Tw of each interrupt acknowledge cycle.

ALE

25

0

Address Latch Enable: provided by the processor to latch the address into the 82821
8283 address latch. It is a HIGH pulse active during Tl of any bus cycle. Note that ALE
is never floated.

OT/R

27

0

Data Transmit/Receive: needed in minimum system that desires to use an 8286/8287
data bus transceiver. It is used to control the direction of data flow through the
transceiver. Logically DT/R is equivalent to S"; in the maximum mode, and its timing is
the same as for M/iO. (T = HIGH, R = LOW.) This signal floats to 3·state OFF in local bus
"hold acknowledge."

DEN

26

0

Data Enable: provided as an output enable for the 8286/8287 in a minimum system
which uses the transceiver. DEN is active LOW during each memory and I/O access and
for INTA cycles. For a read or INTA cycle it is active from the middle of T2 until the mid·
die of T 4, while for a write cycle it is active from the beginning of T 2 until the middle of
floats to 3·state OFF in local bus "hold acknowledge."
T4 .

31,30

I/O

HOLD: indicates that another master is requesting a local bus "hold." To be acknowl·
edged, HOLD must be active HIGH. The processor receiving the "hold" request will
issue HLOA (HIGH) as an acknowledgement in the middle of a T, clock cycle. Simul·
taneous with the issuance of HLDA the processor will float the local bus and control
lines. After HOLD is detected as being LOW, the processor will LOWer the HLOA, and
when the processor needs to run another cycle, it will again drive the local bus and
control lines.

om

HOLD,
HLOA

The same rules as for RQlelT apply regarding when the local bus will be released.
HOLD is not an asynchronous input. External synchronization should be provided if the
system cannot otherwise guarantee the setup time.

1-63

210912·001

8086/8088 CPU

During normal multiprocessor system operation, priority
of the shared system bus is determined by the arbitration
circuits on a cycle by cycle basis. As each CPU requires a
transfer over the system bus, it request access to the bus
via its resident bus arbitration logic. When the CPU gains
priority (determined by the system bus arbitration scheme
and any associated logic), it takes control of the bus, performs its bus cycle and either maintains bus control, voluntarily releases the bus or is forced off the bus by the
loss of priority. The lock mechanism prevents the CPU
from losing bus control (either voluntarily or by force)
and guarantees a CPU the ability to execute multiple bus
cycles (during execution of the locked instruction) without intervention and possible corruption of the data by
another CPU. A classic use of the mechanism is the
'TEST and SET semaphore' during which a CPU must
read from a shared memory location and return data to the
location without allowing another CPU to reference the
same location between the TEST operation (read) and the
SET operation (write). In the 8086 this is accomplished
with a locked exchange instruction (see Figure 1-37).

1.3.6 General Design Considerations
Since the minimum mode 8086 has common read and
write commands for memory and 1/0, if the memory and
110 address spaces overlap, the chip selects must be qualified by M/IO* to determine which address space the devices are assigned. This restriction on chip select
decoding can be removed if the 1/0 and memory addresses in the system do not overlap and are properly decoded, all 1/0 is memory mapped, or RD*, WR * and
M/IO* are decoded to provide separate memory and 1/0
readlwrite commands (see Figure 1-38). The 8288 bus
controller in the maximum mode 8086 system generates
separate 1/0 and memory commands in place of a MilO'"
signal. An 110 device is assigned to the 1/0 space or
memory space (memory mapped 1/0) by connection of
either 1/0 or memory command lines to the command inputs of the device. To allow overlap of the memory and
110 address space, the device must not respond to chip
select alone but must require a combination of chip select
and a read or a write command.
Linear select techniques (see Figure 1-39) for 1/0 devices
can only be used with devices that either reside in the 110
address space or require more than one active chip select
(at least one low active and one high active). Devices with
a single chip select input cannot use linear select if they
are memory mapped because memory address space
FFFFOH-FFFFFH is aSSigned to reset startup and memory space OOOOOH-003FFH is assigned to interrupt
vectors.

LOCK XCHG reg, MEMORY; reg is any register
; MEMORY is the address
of the
; semaphore
Another application of LOCK* for multiprocessor systems consists of a locked block move which allows high
speed message transfer from one CPU's message buffer
to another.

1.4 BUS OPERATION

During the locked instruction, a request for processor
preemption (RQ*/GT*) is recorded but not acknowledged
until completion of the locked instruction. The LOCK*
has no direct affect on interrupts. As an example, a locked
HALT instruction will cause HOLD (or RQ*/GT*) requests to be ignored but will allow the CPU to exit the
HALT state on an interrupt. In general, prefix bytes are
considered extensions of the instructions they preceded.
Therefore, interrupts that occur during execution of a prefix are not acknowledged (assuming interrupts are enabled) until completion of the instruction following the
prefix (except for instructions which are servicing interrupts during their execution, i.e., HALT, WAIT and repeated string primitive). Note that multiple prefix bytes
may precede an instruction. Another example is a 'string
primitive' preceded by the repetition prefix (REP) which
is interruptible after each execution of the string primitive. This holds even if the REP prefix is combined with
the LOCK prefix. This prevents interrupts from being
locked out during a block move or other repeated string
operation. As long as the operation is not interrupted,
LOCK* remains active. Further information on the operation of an interrupted string operation with multiple prefixes is presented in the section dealing with the 8086
interrupt structure.

In order to understand the operation of a time-multiplexed
bus, the BIU's bus cycle must be understood. A bus cycle
is an asynchronous event that presents the address of an
1/0 peripheral or memory location. The address is followed by either a read control signal to capture or read
data from the addressed device, or a write control signal
and the associated data to transmit or write the data to the
addressed device. The selected device (memory or 1/0
peripheral) accepts the data on the bus during a write cycle or places the requested data on the bus during a read
cycle. On termination of the specified cycle, the device
latches the data written or removes the data read.

1.4.1 Multiplexed Address and Data Bus
The 8086/88 has a combined address and data bus commonly referred to as a time multiplexed bus. Time multiplexing makes the most efficient use of pins on the
processor while permitting the use of a standard 4O-pin
package. This "local bus" can be buffered directly and
used throughout the system with address latching provided on memory and 1/0 modules. In addition, the bus

1-64

210912·001

8086/8088 CPU

GND

VCC

AD14

AD15

AD13

GND

VCC

A14

A15

A16/S3

A13

A16/S3

AD12

A17/S4

A12

A17/S4

ADll

A18/S5

All

A18/S5

AD10

A19/S6

Al0

AD9

SHE/57

A9

AD8

MN/Mx

A8

AD7

Rii

8086

(RO/GTO)

AD6

AD5

HLDA

(RQ/GT1)

AD5

AD4

WR

(LOCK)

CPU

M/iO

AD3

(HIGH)

MN/Mx

iiii

AD7

HOLD

AD6

A19/S6
550

8088

HOLD

(RQ/GTO)

HLDA

(RO/GT1)

AD4

WR

(LOCK)

(52)

AD3

IO/M

(52)

CPU

AD2

DTIR

(51)

AD2

DTIR

(51)

ADl

DEN

(So)

ADl

DEN

(So)

(050)

ADO

ALE

(050)

NMI

INTA

(051)

INTR

TEST

CLK

READY

GND

RESET

ALE

ADO
NMI

INTA

INTR

TEST

(051)

READY

CLK

RESET

GND

MAXIMUM MODE PIN FUNCTIONS (e.g., LOCK)
ARE SHOWN IN PARENTHESES

Figure 1-30 8086/8088 DIP Pin Assignments

preparation for a ready cycle or asserts write data. Data
bus transceivers are enabled in either T 1 or T2 depending
on the 8086 system configuration and the direction of the
transfer (into or out of the CPU). Read, write or interrupt
acknowledge commands are always enabled in TZ. The
maximum mode 8086 configuration also provides a write
command enabled in T3 to guarantee time for data setup
prior to command activation.

can also be demultiplexed at the processor with a single
set of address latches if a standard non-multiplexed bus is
desired for the system,

1.4.2 Bus Cycle Definition
The 8086 is a true 16-bit microprocessor with 16-bit internal and .external data paths, one megabyte of memory
address space (220) and a separate 64K byte (2 16) 1/0 address space. The CPU communicates with its external environment via a twenty-bit time multiplexed address,
status and data bus and a command bus. To transfer data
or fetch instructions, the CPU executes a bus cycle (see
Figure 1-40). The minimum bus cycle consists of four
CPU clock cycles ("T") states. During the first T state
(Tl), the CPU asserts an address on the twenty-bit multiplexed addressldatal status bus. For the second T state
(TZ), the CPU removes the address from the bus and either tri-states its outputs on the lower sixteen bus lines in

During T2, the upper four multiplexed bus lines switch
from address (AI9-AI6) to bus cycle status (S6, S5, S4,
S3). The status information (see Table 1-31) is available
primarily for diagnostic monitoring. However, a decode
of S3 and S4 could be used to select one of four banks of
memory, one assigned to each segment register. This technique allows partitioning the memory by segment to expand the memory addressing beyond one megabyte. It
also provides a degree of protection by preventing erroneous write operations to one segment from overlapping
into, and destroying information, in another segment.
1-65

210912-001

8086/8088 CPU

Table 1·25 D.C. Characteristics
(8086: TA = O°C to 70°C. Vee = 5V :t 10"10)
(8086-1: TA = O°C to 70°C. Vee = 5V :t 5"10)
(8086-2: TA = O°C to 70°C. Vee = 5V :t 5"10)
Symbol

P.rameter

Min.

VIL

Input Low Voltage

-0.5

M••.

Units

+0.8

V

V IH

Input High Voltage

2.0

V ee + 0.5

V

VOL

Output Low Voltage

VOH

Output High Voltage

0.45

V

IOL=2.5 mA

V

Icc

Power Supply Current: 8086
8086-1
8086-2

340
360
350

10H= - 4oo,.A

mA

ILl

Input Leakage Current

± 10

,..A

OV", VIN '" VCC

ILO

Ol!tput Leakage Current

± 10

,..A

0.45V" VOUT " Vee

VCL

Clock Input Low Voltage

+0.6

V

2.4

-0.5

Tast Conditions

TA=25°C

VCH

Clock Input High Voltage

Vcc + 1.0

V

C IN

Capacitance 01 Input Buffer
(All input except
ADo - AD 15. RQ/GT)

15

pF

Ic= 1 MHz

C IO

Capacitance 01 110 Buffer
(ADo - AD 15.m:i/GT)

15

pF

Ic= 1 MHz

3.9

The CPU continues to provide status information on the
upper four bus lines during T3 and will either continue to
assert write data or sample read data on the lower sixteen
bus lines. If the selected memory or I/O device is not
capable of transferring data at the maximum CPU transfer
rate. the device must signal the CPU "not ready" and
force the CPU to insert additional clock cycles (Wait
states, TW) after T3. The 'not ready' indication must be
presented to the CPU by the start of T3. Bus activity during TW is the same as T3. In a "normally not ready"
system, when the selected device has had sufficient time
to complete the transfer, it aSserts "Ready" and allows the
CPU to continue from the TW states. The CPU will latch
the'data on the bus during the last wait state or during T3
if no wait states are requested: The bus cycle is terminated
in T4 (command lines are disabled and the selected external device releases the bus). To devices in the system, the
bus cycle appears as an asynchronous event consisting of
an address to select the device followed by a read strobe
or data and a write strobe. The selected device accepts
bus data during a write cycle and drives the desired data
onto the bus during a read cycle. On termination of the
command, the device latches write data or disables its bus
drives. The only way the device controls the bus cycle is
by inserting wait cycles.

interface executes idle cycles (T 1). During the idle cycles, the CPU continues to drive status information from
the previous bus cycle on the upper address lines. If the
previous bus cycle was a write, the CPU continues to
drive the write data onto the multiplexed bus until the start
of the next bus cycle. If the CPU executes idle cycles
following a ready cycle, the CPU will not drive the lower
16 bus lines until the next bus cycle is required.
Since the CPU prefetches up to six bytes of the instruction
stream for storage and execution from an internal instruction queue, the relationship may be skewed in time and
separated by additional instruction fetch bus cycles. In
general, if the BIU fetches an instruction into the 8086's
internal instruction queue, it may also fetch several additional instructions before the EU removes the instruction
from the queue and executes it. If the EU executes a jump
or other control transfer instruction from the queue, it
ignores any instructions remaining in the queue; the CPU
discards these instructions with no effect on operation.
The bus activity observed during execution of a specific
instruction depends on the preceding instructions; the activity, however, may always be determined within a specific sequence.

1.4.3 Address and Data Bus Concepts
The 8086 CPU only executes a bus cycle when.instructions or operands must be transferred to or from memory
or I/O devices. When not executing a,bus cycle, the bus

The programmer views the 8086 memory address space
as a sequence of one million bytes in which any byte may

1-66

210912-001

8086/8088 CPU

the data bus to participate in the transfer. Another 8086
signal, Bus High Enable (BHE*), disables the bank on the
upper half of the data bus to prevent its participation in the
transfer. This action prevents a write operation to the
lower bank from destroying data in the upper bank. Device pin 34 (refer to paragraph 1.3) is multiplexed between BHE* during Tl and S7 during T2 through T4.
The current implementation of the 8086 equates BHE* to
S7. That is, if BHE * is high during T I then S7 will likewise be high during T2 through T4. Since BHE* is a multiplexed signal with timing identical to the A19-A16
address lines, it also should be latched during Tl with
ALE to provide a stable signal during the bus cycle. To
perform byte transfers to odd addresses (see Figure 1-42),

contain an eight bit data element and any two consecutive
bytes may contain a 16-bit data element. There is no constraint on byte or word addresses (i.e., boundaries). The
address space is physically implemented on a 16-bit data
bus by dividing the address space into two banks of up to
512K bytes (see Figure 1-41). One bank connects to the
lower half of the 16-bit data bus (D7-0) and contains even
addressed bytes (AO = 0). The other bank connects to the
upper half of the data bus (DI5-8) and contains odd addressed bytes (AO = I). Address lines AI9-AI select a
specific byte within each bank. To perform byte transfers
to even addresses (Figure 1-42), the information is transferred over the lower half of the data bus (D7-0). AO (active low) enables the bank connected. to the lower half of

Table 1·26 A.C. Timing Requirements for Minimum Complexity System
(8086: TA ; O'G to 70'G, vec ; 5V ± 10%)
(8086-1: TA ; O'G to 70'G, Vee; 5V ± 5%)
(8086-2: TA ; O'G to 70'G, Vee; 5V ± 5%)

MINIMUM COMPLEXITY SYSTEM
TIMING REQUIREMENTS
Symbol

Parameter

8086-2

8086·1 (Preliminary)

8086

Units

Min.

Max.

Min.

Max.

Min.

Max.

TClCl

ClK Cycle Period

200

500

100

500

125

500

TClCH

ClK low Time

118

53

68

TCHCl

ClK High Time

69

39

44

TCH1CH2

elK Rise Time

10

Test
Conditions

ns
ns
ns

10

10

ns

From 1.0V to

3.5V
TCL2Cl1

ClK Fall Time

10

10

10

ns

TDVCl

Data in Setup Time

30

5

From 3.SV to

1.0V

-20

ns

TClDX

Data in Hold Time

10

10

10

ns

TR1VCl

ROY Setup Time
into 8284A (See
Notes 1. 2)

35

35

35

ns

TClR1X

ROY Hold Time

0

0

0

I

into 8284A (See
Notes 1. 2)

ns

TRYHCH

READY Setup
Time into 8086

118

53

68

ns

TCHRYX

READY Hold Time
into 8086

30

20

20

ns

TRYlCl

READY Inactive to
ClK (See Note 3)

-8

-10

-8

THVCH

HOLD Setup Time

35

20

20

ns

TINVCH

INTR. NMI. TEST
Setup Time (See
Note 2)

30

15

15

ns

TlllH

Input Rise Time
(Except ClK)

20

20

20

ns

TIHll

Input Fall Time
(Except ClK)

12

12

12

ns

,

ns

From O.8V to

2.0V

1-67

From 2.0V to
O.8V

210912-001

8086/8088 CPU

Table 1-26 A.C. Timing Requirements for Minimum Complexity System (continued)
TIMING RESPONSES
Symbol

Parameter

8086

8086·1 (Preliminary)

Unit.

8086-2

Min.

Max.

Min.

Max.

Min.

Max.

TCLAV

Address Valid Delay

10

110

'10

50

10

60

TCLAX

Address Hold Time

10

TCLAZ

Address Float
Delay

TCLAX

10

10

10

80

40

TCLAX

ns
ns

50

ns

TLHLL

ALE Width

TCLLH

ALE Active Delay

80

40

50

ns

TCHLL

ALE Inactive Delay

85

45

55

ns

TLLAX

Address Hold Time
to ALE Inactive

TCLDV

Data Valid Delay

10

TCHDX

Data Hold Time

10

10

10

ns

TWHDX

Data Hold Time
AfterWA

TCLCH-30

TCLCH-25

TCLCH-30

ns

TCVCTV

Control Active
Delay 1

10

110

10

50

10

70

ns

TCHCTV

Control Active
Delay 2

10

110

10

45

10

60

ns

TCVCTX

Control Inactive
Delay

10

110

10

50

10

70

ns

TAZAL

Address Float to
AEAD Active

0

TCLCH-20

TCLCH-l0

TCHCL-l0

TCLCH-l0

TCHCL-l0
110

10

ns

TCHCL-l0

50

10

T••t
Condition.

ns
60

ns

'CL

= 20-100 pF

for all 8086 Out-

puts (In addition to 8086 self-

load)

0

0

i

ns

TCLAL

AD Active Delay

10

165

10

70

10

100

TCLAH

RD Inactive Delay

10

150

10

60

10

80

TAHAV

RD Inactive to Next
Add ress Active

TCLHAV

HLDA Valid Delay

TALAH

AD Width

2TCLCL-75

2TCLCL-40

2TCLCL-50

ns

TWLWH

WAWidth

2TCLCL-60

2TCLCL-35

2TCLCL-4O

ns

TAVAL

Address Valid to
ALE Low

TCLCH-60

TCLCH-35

TClCH-4O

ns

TOLOH

Output Aise Time

20

20

20

ns

.From 0.8V to.
2.0V

Output Fall Time

12

12

12

ns

From 2.0V to
0.8V

I TOHOL

TCLCL-45
10

TCLCL-40

TCLCL-35
160

10

10

60

ns
ns
ns

100

ns

NOTES:
1. Signal at 8284A shown for ref.. rence only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next elK.
3. Applies only to T2 state. (8 ns into T3).

the information is transferred over the upper half of the
data bus (DIS-D8). BHE* (active low) will enable the
upper bank and AO will disable the lower bank. Directing
the data transfer to the appropriate half of the data bus and
activation of S7 (BHE*) and AO is performed by the
8086, transparent to the programmer. For example, consider loading a byte of data into the ex register (lower
half of the ex register) from an odd addressed memory
location (referenced over the upper half of the 16-bit data

bus). The data is transferred into the 8086 over the upper
8 bits of the data bus, automatically redirected to the
lower half of the 8086 internal 16-bit data path and stored
in the ex register. This capability also allows byte I/O
transfers with the AL register to be directed to I/O devices
connected to either the upper or lower half of the 16-bit
data bus.

1-68

210912-001

8086/8088 CPU

To access even addressed l6-bit words (two consecutive
bytes with the least significant byte at an even byte address), A19-Al select the appJOpriate byte within each
bank and AO and BHE* (active low) enable both banks
simultaneously (see Figure 1-43). To access an odd addressed l6-bit word (see Figure 1-43), the least significant byte (addressed by A19-Al) is first transferred over
the upper half of the bus (odd addressed byte, upper bank,
BHE* low active and AO-l). The most significant byte is

accessed by incrementing the address (A19-AO) which allows A19-Al to address the next physical word location
(recall that AO was high which indicates a word referenced from an odd byte boundary). A second bus cycle is
then executed to perform the transfer of the most significant byte with the lower bank (AO is now low and BHE* is
high). The sequence is automatically executed by the
8086 whenever a word transfer is executed to an odd address. Directing the upper and lower bytes of the 8086 's

Table 1·27 A.C. Timing Requirements for Maximum Complexity System
MAX MODE SYSTEM (USING 8288 BUS CONTROLLER)
TIMING REQUIREMENTS
Symbol

Paramater

8088·1 (Preliminary)

8086

8088·2 (Preliminary)

Unit.

Min.

Max.

Min.

Max.

Min.

Max.

TClCl

ClK Cycle Period

200

500

100

500

125

500

TClCH

elK Low Time

118

53

68

ns

TCHCl

ClK High Time

69

39

44

ns

TCH1CH2

elK Rise Time

10

10

10

T..t
Condition.

ns

ns

From l.QVto
3.5V

TCl2Cll

ClK Fall Time

TDVCl

Data in Setup Time

30

5

20

TClDX

Data In Hold Time

10

10

to

ns

TR1VCl

ROY Setup Time
into 8284A (See
Notes I, 2)

35

35

35

ns

TClR1X

ROY Hold Time
into 8284A (See
Notes I, 2)

0

0

0

ns

TRYHCH

READY Setup Time
into 8086

118

53

68

ns

TCHRYX

READY Hold Time
into 8086

30

20

20

ns

TRYlCl

READY Inactive to
ClK (See Note 4)

-8

-10

-8

ns

TINVCH

Setup Time for
Recognition (INTR,
NMI, 'fEST) (See
Note 2)

30

15

15

ns

10

10

10

ns

From 3.5Vto
1.0V

ns

TGVCH

RO/GT Setup Time

30

12

15

ns

TCHGX

RO Hold Time into
8086

40

20

30

ns

TILIH

Input Rise Time
(Except ClK)

20

20

20

ns

From 0.8Vto
2.0V

TIHll

Input Fall Time
(Except ClK)

12

12

12

ns

From 2.0Vto
0.8V

NOTES:
1. Signal at 8284A or 8288 shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next elK.
3. Applies only to T3 and wait states.
4. Applies only to T2 state (8 ns into T3).

1-69

210912·001

8086/8088 CPU

Table 1-27 A.C. Timing Requirements for Maximum Complexity System (continued)
TIMING RESPONSES
Symbol

TCLMl

Parameter

Command Active

TI.'

8088

8088-1 (Prellmlnlry)

8088-2 (Prellmlnlry)

Unit.

Min.

Me•.

Min.

Mu.

Min.

Ma •.

10

35

10

35

10

35

ns

10

35

10

35

10

35

ns

65

ns

Condition.

Delay (See Note 1)
TClMH

Command Inactive
Delay (5. . Note 1)

TRYHSH

READY Active to

110

45

Status Passive (See
Note 3)
TCHSV

Status Active Delay

10

110

10

45

10

60

ns

TCLSH

Status Inactive

10

130

10

55

10

70'

ns

TCLAV

Address Valid
Delay

10

110

10

50

10

60

ns

TCLAX

Address Hold Time

10

TCLAZ

Address Float Delay

TCLAX

40

TCLAX

50

ns

TSVlH

Status Valid to ALE
High (See Note 1)

15

15

15

ns

Status Valid to

15

15

15

ns

Delay

TSVMCH

10

80

10

10

ns

MCE High (Soe
Notel)
TCLlH

ClK low to ALE
Valid (See Note 1)

15

15

15

ns

TCLMCH

ClK low to MCE
High (See Note 1)

15

15

15

ns

TCHll

ALE Inactive Delay
(SoeNotel)

15

15

15

ns

MCE Inactive Delay

15

15

15

ns

TCLMCl

(SooNotel)
TClOV

Data Valid Delay

10

TCHOX

Data Hold Time

10

TCVNV

Control Active

5

45

5

45

5

45

ns

45

10

45

10

45

ns

110

10

50

10

10

60

=

CL 20-100 pF
for an 8086 Outputs (In add ition to 8086 self·
load)

ns
ns

10

Delay (See Note 1)
TCVNX

Contrellnaetive
Delay (5. . Note 1)

10

TAZRL

Address Float to

0

0

0

ns

Read Active
TCLRl

RO Active Delay

10

165

10

70

10

100

ns

TCLRH

RD Inactive Delay

10

150

10

60

10

80

ns

TRHAV

RO Inactive to

TCLCl-45

TClCl-4O

TClCl-35

ns

Next Address Active
TCHOTl

Direction Control

50

50

50

ns

30

30

30

ns

ns

Active Delay (Soe
Note 1)
TCHOTH

Direction Control
Inactive Delay (See
Note 1)

TCLGL

GT Active Delay

0

85

0

45

0

50

TCLGH

GT Inactive Delay

0

85

0

45

0

50

TRLRH

ROWldth

TOLOH

Output Rise Time

20

20

20

ns

TOHOL

Output Fan Time

12

12

12

ns

2TCLCL-50

2TCLCL-4O

2TCLCL-75

ns
ns
From 0.8V to
2.0V
From2.0Vto

O.SV

1-70

210912-001

8086/8088 CPU

Table 1·28 Minimum/Maximum Mode Pin Assignments
8088

8086
Mode

Mode
Pin

Pin
Minimum

Maximum

HOLD
HLDA
WR
MIlO
DT/R
DEN
ALE
INTA

RO/GTO
RO/GT1
LOCK
52

31
30

29
28
27
26
25
24

31
30
29
28
27
26
25
24
34

51

50
OSO
OS1

Minimum

Maximum

HOLD
HLDA
WR
101M
DT/R
DEN
ALE
INTA
SSO

RO/GTO
RO/GT1
LOCK
52
51
SO
OSO
OS1
High State

Table 1·29 Status Bit Decoding
Status Inputs
S2

S1

SO

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

CPU Cycle

8288 Command

Interrupt Acknowledge
Read I/O Port
Write I/O Port
Halt
Instruction Fetch
Read Memory
Write Memory
Passive

INTA
10RC
10WC,AIOWC
None
MRDC
MRDC
MWTC,AMWC
None

data bus. The information on the half of the data bus not
transferring data is indeterminate. These concepts also
apply to the I/O address space. Specific examples of I/O
and memory interfacing are considered in the corresponding sections.

Table 1·30 Status Line Decoders

S2

Sl

So

o (LOW)

0
0

0

1
1

0

0
0

0

1
1

0

0
0
0
1 (HIGH)
1
1
1

1
1
1
1

Interrupt Acknowledge
Read I/O Port
Write I/O Port
Halt
Code Access
Read Memory
Write Memory
Passive

1.4.4 Memory and 1/0 Peripherals Interface
The 8086 and 8088 CPUs have a 20-bit address bus and
are capable of accessing one megabyte of memory address space. The memory is organized as a linear array of
up to 1 million bytes, addressed as OOOOO(H) to FFFFF(H). The memory is logically divided into code, data,
extra data, and stack segments of up to 64 K bytes each,
with each segment falling on 16-byte boundaries (see Figure 1-44).

internal 16-bit registers to the appropriate halves of the
data bus is also performed automatically by the 8086 and
is transparent to the programmer.
During a byte read, the CPU floats the entire 16-bit data
bus even though data is only expected on the upper or
lower half of the data bus. As will be demonstrated later,
this action simplifies the chip select decoding requirements for read only devices (ROM, EPROM). During a
byte write operation, the 8086 will drive the entire 16-bit

All memory references are made relative to base addresses contained in high speed segment registers. The
segment types were chosen based on the addressing needs
of programs. The segment register to be selected is auto-

1-71

210912-001

8086/8088 CPU

WAVEFORMS
MINIMUM MODE

T,
V

T2

f3

.vt..

eLK ('. .A OutpuQ

-

f

'---.j

TCHCTV

I--

-

f

~

TCLAX-

iRE. A1.-A,.

TCHDX-

57-53

I

I

_TLLAX

TLHLl-::::

I

I

ALE
_

TAL

TCHLL-I

_
-

V,H-

ROY ( ' _ InpuQ
SEE NOTE 4

VIL-

I
I

READY (1IOII1npuQ

I

II
I

TCLAV-

.- :r

RD

:::~TCHCTV

INOTE 1)

cWJt. iNTi. VOH)

-

----

-TCHRYX

-

,-- I

!-TCLAZ
!-TCLAX

TDVCL-- ,-TCLDX-

~

DATA IN
TCLRH-

FLO~~

--I t-TRHAV

"'-

,,,"L.t~r --

I

OTIR

TCVCTV- {

r--

-

TRYHCH-

--

I

I_CLRIX

I
TAVAL
TLLAX-

I

TR1VCt

I

--

!

DC- '\

TR~r={

TAZRL-

READ CYCLE

f\--/~

I--TCLCH-

TCHCL

TCLDV _ i

rCLAV-

TCLlH-

~

T,

Tw

_TCLCL_~CH1CH]HC'
I
CH r - - \
v---\
r,",

TCVCTX-

-TCHCTV

I

Figure 1-31 Minimum Mode Waveforms

1-72

210912-001

8086/8088 CPU

WAVEFORMS (Continued)
MINIMUM MODE (Continued)

elK (I2UA Output)

MliO

ALE

WRITE CYCLE

(NOTE 1)

(RD,iii'fA,
DT"'zYOH)

I
TCVCTX--

INTA CYCLE

DTIR

(NOTES , . 3)

Ati. WR",VOH
lIRE. VoL!

SOFTWARE HALT-

AD, WA, INTA. = YaH
DT/A = INDETERMINATE

INVALID ADDRESS

SOFTWARE HALT

TelAV

NOTES:
1. All signals switch between VOH and VOL unless otherwise specified.
2. ROY is sampled near the end of T2, T3, Tw to determine if Tw machines states are to be inserted.
3. Two INTA cycles run back-to-back. The 8086 LOCAL AODR/OATA BUS is floating during both INTA cycles. Control signals shown
for second INTA cycle.
4. Signals at 8284A are shown for reference only.
5. All timing measurements are made at 1.5V unless otherwise noted.

Figure 1-31 Minimum Mode Waveforms (continued)
1-73

210912-001

8086/8088 CPU

WAVEFORMS
MAXIMUM MODE

T,

n

iCH1CH2--lF-=i i-TCl2Cll

VCH~ - T C l C

ClK

X

~

vel ....I
TClAV-

"---J

'------'

r" ~~
Tw

_TClCH_

I---- TCHCl

aSo,QSl

f-----<
~,I1,~ (EXCEPT HAL 1)

TSVlH

TCllHALE (8288 OUTPUT)
SEE NOTE 5

1

-

TCHSV

-TClSH

VI/I;:

------

~ t:=..rCLAV
~CLDV
TClAX -

X

BHE, A'I-A,I

- (

\

flY(SEE NOTE 81
TCHDX-

x:

,~-----

X

57·$3

TCHLL

I

-[k t~~~,X
- -

r--

----

-TR1VCl

RDY (8214A INPUn

TRYlCl_

READY (8088 INPUT)

zf -

TRYHCH-

READ CYCLE

TCLAV-I

£

""- 'r'
I

-TClAZ -

TAZRl-

,

~

..0...- TCHRYX

TRYHSH~I,
-TClAX-·I·

-

TDVCl~

TCHDTl-1

I"-

TClRH

lALRH

1- ~ TeLRl

DTIR
TClMl--

-

TCLMH-...

8288 OUTPUTS
SEe NOTES 5,6

TCVNV-

DEN

-TClDX-1

\I

DATA IN

V

RD

\\\

\

t-

1/

TCVNX ---

flOAT

~

TRHAV----!

TCHDTH

~
-

Figure 1-32 Maximum Mode Waveforms
1-74

210912-001

8086/8088 CPU

WAVEFORMS (Continued)
MAXIMUM MODE (Continued)
T,

T,

T,

T,
T..

eLK

\

$2,~,S:O (EXCEPT HALT)

WRITE CYCLE

\~----

TCHDX-

AD15-ADo

DATA
TCYNX--

DEN

TClMH--

8288 0VfPUTS
SEE NOTES 5,6

AMWC OR AIOWC

_TCLMH

INTACYCLE
ADu-ADo
(SEE NOTES 3 " 4)

FLOAT

~ TeL,OX
A015-AOO

MCEJ
PD£N
DTIR

8288 OUTPUTS

see NOTES 5,6

INTA

DEN
SOFTWARE HALT -

(DEN. YOL;R'D,IIlHR:,R»R:.MWfC,AMWC,iOWC,AiOWC.INTA, = VOH)

INVALID ADDRESS

relAY

-------

~
/,..---------~\
' - - - - _ _......J
\ . _____ _

NOTES:
1. All signals switch between VOH and VOL unless otherwise specified.
2. ADY is sampled near the end of T2, T3, Tw to determine if Tw machines states are to be inserted.
3. Cascade address is valid between first and second INTA cycle.
4. Two INTA cycles run back-to-back. The 8086 LOCAL ADDA/DATA BUS is floating during both INTA cycles. Control for pointer
address is shown lor second INTA cycle.
5. Signals at 8284A or 8288 are shown for reference only.
6. The issuance of the 8288 command and control signals (MADC, MWTC, AMWC, IOAC, lOWe, AiOWc, INTA and DEN) lags the
active high 8288 CEN.
7. All timing measurements are made at 1.SV unless otherwise noted.
8. Status inactive in state just prior to T4'

Figure 1·32 Maximum Mode Waveforms

1-75

210912-001

8086/8088 CPU

vCC

rOl
8284

t-- RES

l

CLOCK
GENERATOR

1-<>'-

r---

r-

n

ClKMN /MlC
READY

SO
!fi

RESET

!:2

L

8288
ClK BUS
CONTROLLER

SO
!fi

-

!:2

- r-

II'iTlI

f1IfI5l!
gwrn

DEN
DT/II

Imrn

ALE

R5WC

8088
CPU

L.
ADDRESS
A19-A8

STB

..

8282
OR

8283

I I

I ... ADDRESS/DATA ..

""'~,' ~~ -!-

ADDRESS BUS

l!

l

c:>E

8286

MEMORY

110 PERIPHERAL

DATA

DATA

1

DATA BUS

t

OR

8287

.
~

Figure 1·33 Elementary Maximum Mode System

lectively allow reading from or writing into either an odd
byte location, even byte location, or both. The instruction
stream is fetched from memory as words and is addressed
internally by the processor to the byte level as necessary.

matically chosen according to the rules of the following
table. All information in one segment type share the same
logical attributes (e.g., code or data). By structuring
memory into relocatable areas of similar characteristics
and by automatically selecting segment registers, programs are shorter, faster, and more structured.

In referencing word data the BIU requires one or two
memory cycles depending on whether or not the starting
byte of the word is on an even or add address, respectively. Consequently, in referencing word operands performance can be optimized by locating data on even
address boundaries. This is an especially useful technique
for using the stack, since odd address references to the
stack may adversely affect the context switching time for
interrupt processing or task multiplexing.

Word (16-bit) operands can be located on even or odd
address boundaries and are thus not constrained to even
boundaries as is the case in many 16-bit computers. For
address and data operands, the least significant byte of the
word is stored in the lower valued address location and the
most significant byte in the next higher address location.
The BIU automatically performs the proper number of
memory accesses, one if the word operand is on an even
byte boundary and two if it is on an odd byte boundary.
Except for the performance penalty, this double access is
transparent to the software. This performance penalty
does not occur for instruction fetches, only word operands.

Certain locations in memory are reserved for specific
CPU operations (see Figure 1-45). Locations from address FFFFOH through FFFFFH are reserved for operations including a jump to the initial program loading
routine. Following RESET, the CPU will always begin
execution at location FFFFOH where the jump must be.
Locations OOOOOH through 003FFH are reserved for interrupt operations. Each of the 256 possible interrupt
types has its service routine pointed to by a 4-byte pointer
element consisting of a 16-bit segment address and a
16-bit offset address. The pointer elements are assumed to

Physically, the memory is organized as a high bank
(015-08) and a low bank (07-00) of 512K 8-bit bytes
addressed in parallel by the processor's address lines
A 19-A 1. Byte data with even addresses is transferred on
the 07-00 bus lines while odd addressed byte data (AO
HIGH) is transferred on the 015-08 bus lines. The processor provides two enable signals, BHE* and AO, to se1-76

210912-001

8086/8088 CPU

Vee

t

~D~
8284 CLOCK
GENERATOR

RES

I

RDY

MNIMX "'-Vcc

~

ClK

MIlO

f+
f+

READY

INTA

RESET

liD

COMM AND
BU S

WR

t

GND

}

DTiRr----,

I

DEN I- - - - ,
8086 CPU
ALE

I ___iljl~-+I;;r~:-:-=-i-l'
III
STB
I
GND! !
OE
I
~

~

II

ADo-AD" ~ADDRIDATA
A'6-A"
BHE

r--

I

8282
lATCH
20, R 3

•
•

>

W
..----,

1 MEGABYTE
ADDRESS BUS

I I
II

J:---""
IL-JT----,I
L--!oe

' - - - - - II

FO~~~~OR~~~ED

DATA BUS DRIVE

8286

TRAN~;'EIVER

I

L ___ I

II
II i-A----\
~
v' D;;:~TUS

!I

Figure 1-34 8086/88 Minimum Mode System

Vee

t

, 10

1

8284
CLOCK
GENERATOR

RES

I

GND

t
~

ClK

f+
f+

READY

SO
51

RESET

52

-

RDY

t

ClK

MNIMX -4-GND

--

MWTC

S;
S2

8288 AMWC ' - BUS
IORC
CTRlR
10WC

DEN

COMMAND
BUS

r-r--

; - - - DTilI

8086
CPU

MRDC

SO

AIOWC

r---

fN'fA

r--

r-- ALE
lOCK -N.C.

'--.
ADo-AD15 A
A18-Au rDDRIDA

iHe

STB

OE

GND

to.

8282
lATCH
(2 OR 3)

~.

-

Y

-t=
~

r-

Y

1 MEGABYTE
ADDRESS BUS

T

DE
8288
TRANSCEIVER
(2)

A
I~

t..

18-BIT

r DATA BUS

r

Figure 1-35 8086/88 Maximum Mode System

1-77

210912-001

8086/8088 CPU

,-----1 ><>----'2'tCLK

-t________~'~LOAD

MHBYf~:::::::::::::::::::::::::::::::::::::::::::::~==)o~_ _ _ _ _ _ _
iilii\'I'E1

74S'"

elKA - - - - - - - - - : ; :_ _ _ _ _ _ _ _ _ _---<'--:+

QA 14
OB 13

ac 12
aD 11
RIP 15
CAR
OUT

aCTO

74532

MHBYTEAND 1 - MATCH CONDITIONS
elKA
- CPU CLOCK
aS1, aso
- CPU QUEUE STATUS
T301,1201
- T STATES 13 Ind T2 (CLOCK LOW TIME_Ot)
SOIH~S2LH
- CPU STATUS so.S2
C ACCESS
- CODE ACCESS
aCTO
- QUeUE MATCH
AO·P
- SINGLE BYTE ON UPPER HALF OF THE 8US

SOLH

----..:..r-...

)o'~'~-------------------------------C.CCESS

S1IH -----''!....../

ffiii-----""'-I'
74SOo1

Figure 1·36 8086/88 Queue Tracking Circuit
MEMORY INTERFACE

have been stored at the respective places in reserved memory prior to occurrence of interrupts.

The basic characteristics of 8086/8088 memory organization (see Figure 1-46) are partitioning of the 16-bit word
memory into high and low 8-bit banks on the upper and
lower halves of the data bus and inclusion of BHE* and

"'~~JLJ
'.~~~~~

~

LOCK

LOCK

NOP BYTE

NEXT LOCK

PREFIX
BYTE FROM
aUEUE

FROM THE
QUEUE
(LOCKED NOP)

PREFIX FROM
THE QUEUE

LOCKED INSTRUCTION

1

QUEUE STATUS INDICATES FIRST BYTE OF OPCODE FROM THE QUEUE.

2

THE LOCK OUTPUT WILL GO INACTIVE BETWEEN SEPARATE LOCKED INSTRUCTIONS.

3

TWO CLOCKS ARE REQUIRED FOR DECODE OF THE LOCK PREFIX AND
ACTIVATION OF THE [OCR SIGNAL.

4

SINCE QUEUE STATUS REFLECTS THE QUEUE OPERATION IN THE PREVIOUS CLOCK
CYCLE, THE iJ5CK OUTPUT ACTUALLY GOES ACTIVE COINCIDENT WITH THE START
OF THE NEXT INSTRUCTION AND REMAINS ACTIVE FOR ONE CLOCK CYCLE
FOLLOWING THE INSTRUCTION.

S

IF THE INSTRUCTION FOllOWING THE LOCK PREFIX IS NOT IN THE QUEUE, THE
LOCK OUTPUT STILL GOES ACTIVE AS SHOWN WHILE THE INSTRUCTION IS BEING
FETCHED.

6

THE BIU WILL STIll PERFORM INSTRUCTION FETCH CYCLES DURING EXECUTION
OF A LOCKED INSTRUCTION. THE U)CR MERelY LOCKS THE BUS TO THIS CPU FOR
WHATEVER BUS CYCLES THE CPU PERFORMS DURING THE LOCKED INSTRUCTION.

Figure 1·37 8086/88 Lock Activity

1·78

210912-001

8086/8088 CPU

AO in selection of the banks. Specific implementations
depend on the type of memory and system configuration.

74LS02

74LS388

ROM and EPROM
ROM's and EPROM's are the easiest devices to interface
to the 8086/8088 system (see Figure 1-47). The byte format of these devices provides a simple bus interface and,
since they are read only devices, AO and BHE* do not
need to be included in their chip enable/select decoding.
(Chip enable is similar to chip select and also determines
if the device is in active or standby power mode.) The
address lines connected to the devices start with A 1 and
continue up to the maximum number of address lines the
device can accept. The remaining address lines are used
for chip enablel select decoding. To connect the devices
directly to the multiplexed bus, they must have output enables. The output enable is also necessary to avoid bus
contention in other configurations. No special decode
techniques are required for generating chip
enable/selects. Each valid decode selects one device on
the upper and lower halves of bus to allow byte and word
access. Byte access is achieved by reading the full word
onto the bus with the 8086 only accepting the desired
byte. If RD*, WR * and M/IO* are not decoded to form
separate commands for memory and 110 in a minimum
mode 8086, M/IO* (high active) must be a condition of
chip enable/select decode. This is also true if the 1/0
space overlaps the memory space assigned to the
EPROM/ROM. The output enable is controlled by the
system memory read signal.

DEFINED

EN~~~: _ _ _ _ _ _ _-.4--'

NOTE: IF IT IS NOT NECESSARY TO THREE·STATE THE COMMAND LINES. A
DECODER (1205 OR 745131) COULD IE USED. THE 74LS257 IS NOT
RECOMMENDED SINCE THE OUTPUTS MAY EXPERIENCE VOLTAGE
SPIKES WHEN ENTERING OR LEAVING THREE·STATE.

Figure 1·38 Decoding Memory and 1/0 RD"
and WR" Commands
Static RAM
Several new memory design requirements are introduced
when interfacing static RAM's to the system. To begin
with, AO and BHE* must be included in the chip
select/chip enable decoding of the devices and write timing must be considered in the compatibility analysis.
Data bus connections must be restricted to either the upper half or the lower half of the data bus for each device.
Also, devices must not straddle the upper and lower
halves of the data bus. In order to select either the upper
byte, lower byte or the full 16-bit word for a write operation, BHE* must be a condition of decode for selecting
the upper byte and AO must be a condition of decode for
selecting the lower byte. Several selection techniques for

Four parameters must be evaluated when determining the
compatibility of static ROM's and PROM's to an
808618088 system. The parameters, equations and evaluation techniques given in the 110 section are also applicable
to these devices. The relationship of parameters is given
in Table 1-32. TACC and TCE are related to the same
equation and differ only by the delay associated with the
chip enable/select decoder. The following example shows
a 2716 EPROM memory residing on the multiplexed bus
of a minimum mode 8086 configuration:

ADD~~~~:U
Il!lIll

1m

~

WlI

110 DEVICE

TACC: 3TCLCL -140 - address buffer delay:
430 ns (8282 : 30 ns max delay)
(I) SEPARATE 110 COMMANDS

TCE : TACC - decoder delay: 412 ns (8205
decoder delay: 18 ns)

ADDRESS\~S
e!
LINESl

TOE: 2TCLCL - 195 : 205 ns

1m

1m

WlI

WII

110 DEVICE

TDF: :155
(b) MULTIPLE CHIP SELECTS

The results of the calculations in the previous example
represent the times a minimum mode configuration requires from the component for full speed compatibility
with the system.

Figure 1·39 Linear Select for 1/0
1-79

210912-001

8086/8088 CPU

I-T,-CLK
--J

r

A19/S6,A16/S3

--

--T,--

Jr---;

X

-

~T"".

It-----

T.-

i~

,1"'--'

X

STATUS

AD DR

-

READY

ADDRESS

A1S~AO

,

P

FLOAT - -

)(

DATA IN

015~OO

1---

~-- ~----.

)( FLOAT

1-.

-----

RD
READ
CYCLE

V

DliA

V

r-,.

DEN

ADDRESS

X

-x::::..

DATA OUT

WR
WRITE
CYCLE

V

DEN

DTIR

---

---Figure 1·40 Basic 8086/88 Bus Cycles

CA) LOGICAL ADDRESS SPACE

devices with single chip selects and no output enables are
illustrated in Figure 1-48 and Figure 1-49 illustrates selection techniques for devices with chip selects and output
enables.

(I) PHYStCAllMPlEMENTATlON OF THE
ADDRESS SPACE

FFFFF

512K IYTES
FFFFF

FFFF£

FFFFD

512K BYTES

FFFF£
FFFFC

FFFFO
FFFFC

In the first examples (see Figure 1-48) AO and BHE*
must be included to decode or enable the chip selects.
Since these memories do not have output enables, read
and write are used as enables for chip select generation to
prevent bus contention. If read and write are not used to
enable the chip selects, devices with common
input/output pins will be subjected to severe bus contention between chip select and write active. For devices with
separate input/output lines, the outputs can be externally
buffered with the buffer enable controlled by read. This
solution will only allow bus contention between memory
devices in the array during chip select transition periods.

~
1 MEO .... YTE

Figure 1·41 8086 Memory

1-80

210912-001

8086/8088 CPU

For devices with output enables (see Figure 1-49), write
may be gated with BHE* and AO to provide upper and
lower bank write strobes. This simplifies chip select decoding by eliminating BHE* and AO as a condition of
decode. Although both devices are selected during a byte
write operation, only one will receive a write strobe. No
bus contention will exist during the write since a read
command must be issued to enable the memory output
drivers.

8086 Momory

If multiple chip selects are available at the device, BHE*
and AO may directly control device selection. This allows
normal chip select decoding of the address space and direct connection of the read and write commands to the
devices. Alternately, the multiple chip select inputs of the
device could directly decode the address space (linear select) and be combined with the separate write strobe technique to minimize the control circuits needed to generate
chip selects.

BHE (HIGH)
0,.-00
Even Addressed Byte Transfer

D1S-De

Ao (lOW)

TRANSFER X + 1

"

Y+1

r---1\

~(X+1)~

II"

Y

""

I

As with the EPROM's and ROM's, if separate commands
are not provided for memory and 110 in the minimum
mode 8086 and the address spaces overlap, M/IO* (high
active) must be a condition of chip select decode. Also,
the address lines connected to the memory devices must
start with Al rather than AO.

t'--

LF--

I

~ ~I
D15-0,

y
X

BHE (LOW)

""0,-00~

... (HIGH)

Odd Addressed Byte Transfer

Figure 1·42 Memory Even and Odd
Data Byte Transfers

The write timing parameters listed in Table 1-33 may also
need to be considered to analyze RAM compatibility (depending on the RAM device being considered). CPU
clock relative timing is listed in Table 1-34. The equations
specify the device requirements at the CPU and provide a
base for determining device requirements in other configurations. For example, consider the write timing requirements of a 2148 in a maximum mode buffered 8086
system (see Figure I-50). The write parameters of the
2148 that must be analyzed are TWP write pulse width,
TWR write recovery time, TDW data valid at end of
write, and TDH data hold from write time.

Engineer and simplify the design task somewhat, Intel
provides the 8202,8203,8207, and 8208 dynamic RAM
controllers as part of the 8086 family of peripheral devices. The following paragraphs describe the use of the
8202 with the 8086 in designing a dynamic memory system for an 8086 system.
For example, a standard interconnection for an 8202 in an
8086 system (see Figure I-51) accomn1odates 64K words
(128 bytes) of dynamic RAM which is addressable as
words or bytes. To access the RAM, the 8086 must initiate
a bus cycle with an address that selects the 8202 (via
PCS*) and the appropriate transfer command (MRDC* or
MWTC*). If the 8202 is not performing a refresh cycle,
the access starts immediately, otherwise, the 8086 must
wait for completion of the refresh. XACK* from the 8202
is connected to the 8284 RDY input to force the CPU to
wait until the RAM cycle is completed before the CPU
can terminate the bus cycle. This effectively synchronizes
the asynchronous events of refresh and CPU bus cycles.
The normal write command (MWTC*) is used rather than
the advanced command (AMWC*) to guarantee that data
is valid at the dynamic RAMs before the write command
is issued. Gating WE* withAO and BHE* provides selective write strobes to the upper and lower banks of memory
to allow byte and word write operations. The logic which
generates the strobe for the data latches allows read data
to propagate to the system as soon as the data is available
and latches the data on the trailing edge of CAS*.

TWA = 2TCLCL - TCLMLmax + TCLMHmin
=375 ns.
TWR = 2TCLCL - TCLMHmax + TCLLHmin
+ TSHOVmin = 17Ons.
TDW = 2TCLCL - TCDLVmax + TCLMHmin
- TIVOV max = 265ns.
TDH = TCLCH - TCLMHmax + TCHDXmin
+ TIVOVmin = 95ns.
A comparison of these results with the 2148 family indicates the standard 2148 write timing is fully compatible
with this 8086 configuration. The read timing must also
be analyzed to determine the complete compatibility of
the devices.

Dynamic RAM
A dynamic RAM is one of the most complex devices to
design into an 8086 system. In order to help the Design
1-81

210912-001

8086/8088 CPU
1l!Ibie 1·31 Status Information
r-__....,TRANSFER X+ 1. X...._ _......

S3

S4

o

o
o

1

o

Alternate (relative to the ES segment)
Stack (relative to the SS segment)
Code/None (relative to the CS segment or a default of zero)
Data (relative to the OS segment)

0,-110

A.(LOW)

S5 = IF (interrupt enable flag)
S6 = 0 (indicates the 8086 is on the bus)

E.... AdckelHCI Word Trlnl'or

Table 1·32 EPROM/ROM Parameters

,...-_ _-iFIRST IUS CYCLE...-_ _- ,

TOE - Output Enab(e to Valid Data .. TRLDV
TACC - Address to Valid Data 5 TAVDV
TCE - Chip Enable to Valid Data" TSLDV
TDF - Output Enable High to Output Float. TRHDZ

a. Read Cycle
iKE (LOW)

Ao(HIGHI

For no wait state operation, the 8086 requires data to be
valid from MRDC* in:

...-_ _.....;SECOND BUS CYCL;;;E_ _.....,

Y+1

2TCLCL-TCLML-TDVCL-buffer delays
ns.

iKE (HIOHI

0,-110

Ao(LOWI

Since the 8202 is CAS* access limited, only CAS* access
time needs to be examined. The 8202/2118 guarantees
data valid from 8202 RD* low to be:
(tph + 3tp + 100 ns) 8202 TCC delay + TCAC for the
2118

Figure 1·43 Memory Even and Odd
Data Word Transfers

D}

..r----l- FFFFFH

•.1..
j

r

'=

CODE SEGMENT

XXXXOH

A 25 MHz 8202 and 2118-3 pro"ide only 297 ns, which is
insufficient for no wait state operation. If only 64K bytes
are accessed, the 8202 requires only (tph + 3tp = 85 ns)
giving 282 ns access and no wait states required (see Figures 1-52 and 1-53). Refer to the devices respective data
sheets for additional information.
RESET IOOTSTAAP

} STACK SEGMENT

SEGMENT

cs
55

os

ES

~

t1

FFF .... H

PROGRAM JUMP

FFFFOH

+ OFfSET

REGISTER FilE

= 291

INTERRUPT POINTER

} DATA SEGMENT

3FFH

FOR TYPE 255

3FCH

f--

7H
INTERRUPT POINTER

}EXTRA DATA SEGMENT

FOR TYPE 1
INTERRUPT POINTER

FOR TYPE 0

'H

'H

OH

Figure 1·45 Reserved Memory Locations

Figure 1·44 8086/8088 Memory Organization
1-82

210912-001

8086/8088 CPU

ADDRESS ' - -_ _ _- ,

"0-----1

LOW BANK
CHIP SELECTS

ADDRESS _ _ _ _ _-,

CONTROL

DATA

BHE

MliO OR

---++----01

HIGH BANK
CHIP SELECTS

+---q

ADDITIONAL - - -......
ADDRESS

(I)

Figure 1·46 8086/8088 Memory Array

a. Write Cycle
An important consideration for dynamic RAM write cycles is to guarantee data to the RAM is valid when both
CAS* and WE* are active. For the 2118, ifWE* is valid
prior to CAS*, the data setup is to CAS* and if CAS* is
valid before WE* (as would occur during a read modify
write cycle) the data setup time is to WE*.
For the 8202, the WR* to CAS* delay is analyzed to determine the data setup time to CAS* inherently provided
by the 8202 command to RAS*/CAS* timing. The minimum delay from WR* to CAS* is:
ce)

.5
AOOR
CHIP SELECT

------<>----------,

IfL.J....,.-,---'\ ::~rpHERAL

Table 1-35 presents a list of bus parameters, their definition and how they relate to the A. C. characteristics of.

DATA BUS

ADDAESS

iIif

PERIPHERAL
C8

----h/l "0..

m

00

.2051
Ii

Ao -'---+-
<0:--------,"""---,

360

372
772
258
58
,4,
'47
347
258
,3
572
772
40
'43
354
240
'43
40

DEVICES ARE CONNECTED TO THE UPPER AND
LOWER HALVES OF THE DATA BUS.
ADDRESS

o
1

2
3
4
5
6
7

DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE
DEVICE

0
1
0
1
2
3
2
3

DATA
DATA
CONTROUSTATUS
CONTROUSTATUS
DATA
DATA
CONTROUSTATUS
CONTROUSTATUS

ETC.

Not applicable.

Figure 1·59 Device Assignment

clock) or not using the device. As an example, consider
address valid prior to advanced write lower (TAVWLA)
for the maximum mode fully buffered:

The routine begins operation by loading CX with a count
of the number of lines in the system and DX with the I/O
address of the first line. The I/O addresses are designed
with 8251's as the 110 devices (see Figure 1-59). The status of each line is read to determine if it needs service. If
yes, the appropriate routine is called to input or output a
character. After servicing the line or if no service is
needed, CX is decremented and DX is incremented to test
the next line. After all lines have been tested and serviced,
the routine terminates. If all interrupts from the lines are
OR'd together, only one interrupt is used for all lines. If
the interrupt is input to the CPU through an 8259A interrupt controller, the 8259A should be programmed in the
level triggered mode to guarantee all line interrupts are
serviced.

TAVWLA= TCYC-1OO ns-address latch delay- address buffer delay - chip select decode delay + write buffer delay (minimum)
Assuming inverting latches and buffers with 22 ns delay
(8283/8287) and an 8205 address decoder with 18 ns delay:
TAVWLA = 38 ns which is the time a 5 MHz 8086
system provides.

To service either an input or an output request (see Figure
1-60), the called routine transfers DX to BX, and shifts
BX to form the offset for this device into the table of input
or output buffers. The first entry in the buffer is an index
to the next character position in the buffer and is loaded
into the 81 register. By specifying the base address of the
table of buffers as a displacement into the data segment,
the base + index + displacement addressing mode allows
direct access to the appropriate memory location.

Multiple Communications Lines Example

Consider an interrupt drive procedure for handling multiple communications lines. On receiving an interrupt from
one of the lines, the invoked procedure polls the lines
(reading the status of each) to determine which line to
service. The procedure does not enable lines but simply
services input and output requests until the associated output buffer is empty (for output requests) or until an input
line is terminated (for the example, only EOT is considered). On detection of the terminate condition, the routine
will disable the line. It is assumed that other routines will
fill a lines output buffer and enable the device to request
output or empty the input buffer and enable the device to
input additional characters.

Memory - 1/0 Block Transfers Example

The memory mapped 110 and the 8086 string primitive
instructions may be used to perform block transfers between memory and 110. By assigning a block of the
1·91

210912·001

8086/8088 CPU

THIS CODE OEMONSTRATES TESTING DEVICE
STATUS FOA SERVICE, CONSTRUCTINQ THE
APPROPRIATE LINE IUFFER ADDRESS FOR INPUT
AND OUTPUT AND SERVICING AN INPUT
REQUEST

CHECtCS'A'US:

MASK EQU OFFFDH
INPUT AL, OX
MQY
AH, AL

TEST
JZ
CALL
TEST
JZ
CALL
TEST
JZ
WRITE_ SEAVICE:
NEXT_IO:

ADDRESS:

CALL
DEC

ex

JNC
AND
ADD

EXIT
ox, MASK
OX, 3

; YE., REITO'" • AnU"N,

OR
JMP

CHECILSTATUI

; NEXT INPUT,

AND

ox, MASK

; IELICT DATA.,
; CONSTRUCT IUFFER
; OIiPLACEMINT II'OR
; THII DEVICE.
; IX IS THI DISPLACEMENT,

MOY
INC

SHA
AEAD:

: OET 1251. STATUS,

AH, AEAD_OR_WRITLSTATUS
NEXT_IO
ADDRESS
AH, READ STATUS
WfUTE_SERYICE
READ
AH, WAITE SUTUS
NEXT_IO

WRITE
; TEIT IF DONE.

ox, 2

IH,DL
IH
IH

; REMOVE.t AND

TAANSFER 258 BYTE BLOCKS TO THE I/O DEVICE

; INCRIMINT ADDRUI.
; IILICT ITATUS FOR

THE ADDRESS SPACE ASSIGNED TO THE 110 DEVICE IS

A"
FROM
THAU

XOR
IL,IL
AIT
INPUT AL, DX
MOV II, AIlAD-I.UFflAI,I)(j

JNZ CONT _RIAD
CONT _READ:

RIT

ADDRESS
ADDRESS

A' ~
_0',
~
1',

MEMORY DATA NEED NOT IE ALIGNED TO EVEN ADDRESS 10UNDAAIES
110 TAANSFERS MUST IE WORD TRANSFERS TO EVEN ADDRESS 10UNDARIES

i RIAD CHAMCTIIII.
j on CHARACTER POINTIR.
MOY IIIIAD_IU"ERI,IX .• IIJ.AL ; ITO~I CHAIlACTI~.
j INCR CH......CTIR POINTE ...
INC ~IIAD_'UFfI~II')(j
eMP AL, lOT
j END 0' TMNIMIUION?

CALL DIUILI READ

i-IASE
~IASE

Figure 1·61 Block Transfer to 16·blt 1/0
Using 8086/88 String Primitives

j VEl, DIIAILE "ICIIVEIII.
; lEND M.18'GI THAT INPUT
j II RIADY,

There are several techniques available for interfacing devices without output enables to the multiplexed bus, Note
that each of these techniques introduces other restrictions
or limitations. Consider the case of chip select gated with
read and write (see Figure 1-68). Two problems exist with
this technique. First, the chip select access time is reduced to the read access time, and may require a faster

Figure 1·60 1/0 Input Request Code Example
memory address space (equivalent in size to the maximum
block to be transferred to the liD device) and decoding
this address space to generate the liD device's chip select,
the block transfer capability is easily implemented. Figure 1-61 gives an interconnect for 16-bit liD devices
while Figure 1-62 incorporates the 16-bit bus to 8-bit bus
mUltiplexing scheme to support 8-bit liD devices. A code
example to perform such a transfer is shown in Figure
1-63.

A"., L-_ _ _-,/

3805
A·1
CHIP SELECT

1.4.5 System Design Alternatives
Two implementation alternatives must be considered
when referring to the system data bus: 1) the multiplexed
addressldata bus (see Figure 1-64); and 2) a data bus buffered from the multiplexed bus by transceivers (see Figure 1-65).

CS

iiiiE --+-4._,
DATA

iiii

If memory or liD devices are connected directly to the
multiplexed bus, the designer must guarantee the devices
do not corrupt the address on the bus during T 1. To avoid
this, device output drivers should not be enabled by the
device chip select. They should have an output enable
controlled by the system read signal (see Figure 1-66).
The 8086 timing guarantees that read is not valid until the
address is latched by ALE (see Figure 1-67). All Intel
peripherals, EPROM products, and RAM's for microprocessors provide output enable or read inputs to allow connection to the multiplexed bus.

8·BIT
110
DEVICE

Wii

ADDRESS ASSIGNMENT SAME AS PREVIOUS EXAMPLE. 18-BIT BUS IS
MULTIPLEXED ONTO AN 8·BIT PERIPHERAL BUS.

Figure 1·62 Block Transfer to 8·bit 1/0
Using 8086188 String
Primitives
1-92

210912·001

8086/8088 CPU

BUFFERED DATA BUS

; DEFINE THE 110 ADDRESS SPACE
1I0_BLOCK:

110 SEGMENT
ORG BLOCKJDDRESS
OW, a8 DUP (?)
110 ENDS
; ASSUME THE DATA IS FROM THE CURRENT
: DATA SEGMENT
CLD
; OF. FORWARD
LES 01, I/O_BLOCKJDDAESS ; 110 BLOCK ADDRESS
; CONTAINS THE ADDRESS
MOV ex, BLOCK_LENGTH
MOV 51, SOURCILADDRESS
MOVS 110 BLOCK

; OF 1/0 BLOCK
: PERFORM WORD TRANSFERS

; END CODE EXAMPLE
NOTE THE CODE IS CAPABLE OF PERFORMING BVTE TRANSFERS BY
CHANGING THE 110 BLOCK DEFINITION FROM
WORD TO
BYTES

'a.

as.

SYSTEM
BUS

Figure 1·63 Code For Block Transfers

device if maximum system performance (Le., no wait
states) is to be achieved (see Figure 1-69). Second, the
designer must verify that the chip select-to-write setup
and hold times for the device are not violated (see Figure
1-70). Alternate techniques can be extracted from the bus
interfacing techniques, also described in this chapter, but
are subject to the associated restrictions. In general, for
best results, use devices with output enables.
To guarantee the specified A.C. characteristics, the 8086's
drive capability of 2.0 rnA and capacitive loading of 100
pF subsequently limits the fan out of the multiplexed bus.
Assuming capacitive loads of 20 pF per I/O device, 12 pF
per address latch and 5-12 pF per memory device, a system mix of three peripherals and two to four memory devices (per bus line) approach the loading limit.

Figure 1·65 Buffered Data Bus

The data bus must be buffered using inverting or
non-inverting octal buffers to satisfy the capacitive loading and drive requirements of larger systems. To enable
and control the direction of the transceivers, the 8086 provides Data Enable (DEN) and Data Transmit/Receive
(DT/R*) signals (see Figure 1-65). These signals provide
the appropriate timing to guarantee isolation of the multiplexed bus from the system during Tl and elimination of

MULTIPLEXED DATA BUS

BHE

8282
ALE-----I

ADDRESS BUS
ADDRESS

MULTIPLEXED
BUS

L-_ _ _ _--'A"'D"',,'--:::::AD"",'-'\ MULTIPLEXED
ADDRESS/OAT A

Figure 1·66 Devices With Output Enable
on the Multiplexed Bus

Figure 1·64 Multiplexed Data Bus

1-93

210912-001

8086/8088 CPU

T1

T2

T3

T4

,---,-----

/

ALE

Figure 1·67 Relationship of ALE to READ

bus contention with the CPU during read and write (see
Figure 1-71). Although the memory and peripheral devices are isolated from the CPU (see Figure 1-72), bus
contention may still exist in the system if the devices do
not have an output enable control other than chip select.
As an example, bus contention will exist during transition
from one chip select to another (the newly selected device
begins driving the bus before the previous device has disabled its drivers). Another, more severe case exists during
a write cycle: from chip select to write active, a device
whose outputs are controlled only by chip select, will
drive the bus simultaneously with write data being driven
through the transceivers by the CPU (see Figure 1-73).
The same technique given for circumventing these problems on the multiplexed bus can be applied here with the
same limitations.

ADDRESS

'--_ _ _ _ _ _ _-::><:---,/ MULTIPLEXED BUS

Since the majority of system memories and peripherals
require a stable address for the duration of the bus cycle,
the address on the multiplexed address/data bus during Tl
should be latched and the latched address used to select
the desired peripheral or memory location. Since the
8086 has a 16-bit data bus, the multiplexed bus components of the 8085 family are not applicable to the 8086 (a
device on address/data bus lines 8-15 will not be able to
receive the byte selection address on lines 0-7). To demultiplex the bus (see Figure 1-74), the 8086 system provides an Address Latch Enable signal (ALE) to capture
the address in transparent D-type latches. The latches

Figure 1·68 Devices Without Output Enable
on the Multiplexed Bus

.000 ...

---<. . .________-----.
'\

,

-,-

J

.ooo~~_ _ _ _ _ _ _ _ _ _ _ _ __
WR-------------~

C!.WII----h}~

DATA
1

ACCESS TIME FOA CS GENERATED FROM ADDRESS DECODE.

2

ACCESS TIME IF CS IS GATED WITH ADlWlt

k

1

cs IS NOT VALID PRIOR TO WRITE AND BECOMES ACTIVE ONE OR TWO GATE

a

CS REMAINS VALID AFTER WRITE ONE OR TWO GATE DELAYS,

DELAVS LATER.

Figure 1·69 Access Time: CS Gated
with AD*IWR*

Figure 1·70 CE to WR* Setup and Hole
1-94

210912-001

8086/8088 CPU

AD.

ADDRESS A,,-Ao

AOtS-ADo

1

READ
CYCLE

T4_

"_Tlll·~~~_T3
I FLOAT

f---

IX

DATA IN

)

015-Do

--- -----

--- -----

FLOAT

iffi
DTIR

- ~
V

1\

DEN

X

AD,s·ADo

ADDRESS

X

i

DATA OUT

FLOAT

Viii
2 WRITE
CYCLE

II

DiN
DT/A"

- ---,

-

_J

1

DiN IS ENABLED AnER THE _

2

!!Ell ENABLES THE TRANSCEIVERS EARLY IN THE CYCLE, BUT DTIR GUARANTEES

HAS FLOATED THE MULTIPLEXED BUS

THE TRANSCEIVERS ARE IN TRANSMIT RATHER THAN RECEIVE MODE AND WILL
NOT DRIVE AGAINST THE CPU.

Figure 1-71 Bus Transceiver Control
may be either inverting or non-inverting. These devices
propagate the address through to the outputs while ALE is
high and latch the address on the falling edge of ALE.

ADDA~~__________________________

0'" J /

~10'" THIIUS
Dl¥telS DillY r-

lUI CONTENllON"...;._______• • _ _ _ _ _ _ __
~

Figure 1-72 Devices With Output Enable
on the System Bus

Figure 1-73 CS·/Bus Driving Device Timing
1-95

210912-001

8086/8088 CPU

NOTE
Throughout this chapter consider the multiplexed bus as the local CPU bus and the demultiplexed address and buffered data bus as
the system bus.
ADDRESS
BUS

MULTIPLEXED ADDRESS AND DATA BUS

AD1S-ADo

Figure 1-74 De-multiplexing Address and Data
From the Processor Bus

This timing delays address access and chip select decoding by only the propagation delay of the latch. The outputs are enabled through the low active OE* input. The
demultiplexing of the multiplexed address/data bus
(Jatchings of the address from the multiplexed bus), can
be done locally at appropriate points in the system or at
the CPU with a separate address bus distributing the address throughout the system (see Figure 1-75). For optimum system performance and compatibility with
multiprocessor and MULTIBUS configurations, the latter
technique is strongly recommended over the first.

An additional extension to bus implementation is a second
level of buffering to reduce the total load seen by devices
on the system bus (see Figure 1-76). This technique is
typically used for multiboard systems and for isolation of
memory arrays. The concerns with this configuration are
the additional delay for access and, more important, control of the second transceiver in relationship to the system
bus and the device being interfaced to the system bus. One
technique for controlling the transceiver (see Figure 1-77)
simply distributes DEN and DT/R* throughout the system. DT/R * is inverted to provide proper direction control for the second level transceivers. Another technique
(see Figure 1-78) provides control for devices with output
enables. RD* is used to normally direct data from the
. system bus to the peripheral. The buffer is selected whenever a device on the local bus is chip selected. Bus contention is possible on the device's local bus during a read as
the read simultaneously enables the device output and
changes the transceiver direction. Contention may also
occur as the read is terminated.
For devices without output enables, the same technique
can be applied (see Figure 1-79) if the chip select to the
device is conditioned by read or write. Controlling the
chip select with read/write prevents the device from driving against the transceiver prior to the command being
received. Using this technique, read/write time and
CS-to-write setup and hold times limit access to the devices.

ADDRESS BUS

8088
CPU

Using an alternate technique applicable to devices with
and without output enables, (see Figure 1-80). RD* controls the direction of the transceiver but it is not enabled
until a command and chip select are active. The possibility for bus contention still exists but is reduced to variations in output enable versus direction change time for the
transceiver. Full access time from chip select is now available, but data will not be valid prior to write and will only
be held valid after write by the delay to disable the transceiver.

DATA BUS

SEPARATE ADDRESS AND DATA BUSSES

r------,
I
I
I

I

I

,

I

r'--~~~~

I

8086

I

CPU

I
,,
,L ______ J,
I

1----..-----.. ALE
L-.L-____J\ ADDRESS/DATA
BUS

In the last example of a technique for devices with separate inputs and outputs (see Figure 1-81) separate bus receivers and drivers are provided rather than a single
transceiver. The receiver is always enabled while the bus
driver is controlled by RD* and chip select. The only possibility for bus contention in this system occurs as multiple devices during chip selection changes.

Figure 1-75 Multiplexed Bus With Local
Address Demultiplexing

1-96

210912·001

8086/8088 CPU

CPU LOCAL
BUS

MEMORY/IO
LOCAL BUS

SYSTEM
BUS

Figure 1·76 Fully Buffered System

1.4.6 Multiprocessor/Coprocessor
Applications
The 8086 architecture supports multiprocessor systems
based on the concept of a shared system bus (see Figure
1-82). All CPU's in the system communicate with each
other and share resources using the system bus. The bus
may be either the Intel MULTIBUS system bus or an extension of the system bus. Arbitration logic consists of the
major addition required to the demultiplexed system bus

MEMORY/IIO

DEVICE

,2H/7

Figure 1·79 Buffering Devices Without
OE*/RD* and With Common
or Separate Input/Output
MEMORY/IIO DEVICES

~------1>------------'

Figure 1·77 Controlling System Transceivers
with DEN and DT/R*

WR-----------.
1lI------?------,
RD--------~--+_--------_r-+_,
SYSTEM DATA BUS

828617
SVSTEM fL ____J'\1
DATA
BUS

MEMORY/I/O
DEVICE

MEMORYIIIO
DEVICE

Figure 1·80 Buffering Devices Without OE*/RD*
and With Common or Separate
Input/Output

Figure 1·78 Buffering Devices with OE*/RD*
1-97

210912-001

8086/8088 CPU

access to shared resources to include concurrent support
of a local CPU bus for private resources. For specific configurations and additional information on the 8289, refer
to paragraph 1.8.3.

e!~~-------------------------,

lm--qL-'"
Wft---------+--~----------__,

SYSTEM
DATA
BUS

LOCK·

74804
OR
74S240

-.----+--1

LOCAL WRITE BUS

LOCAL READ BUS

The LOCK*outputis used in conjunction with an Intel
8289 Bus Arbiter to guarantee exclusive access of a
shared system bus for the duration of an instruction. This
output is software controlled and is effected by preceding
the instruction with a one byte "lock" prefix (see instruction set description earlier in this chapter).

o

MEMORY/I/O
DEVICE

748240

When the lock prefix is decoded by the EU, the EU informs the BID to activate the LOCK* output during the
next clock cycle. This signal remains active until one
clock cycle after the execution of the associated instruction is concluded.

Figure 1·81 Buffering Devices Without OE*/RO·
and With Separate
Input/Output

to control access to the system bus. As each CPU asynchronously requests access to the shared bus, the arbitration logic resolves priorities and grants bus access to the
highest priority CPU. Having gained access to the bus,
the CPU completes its transfer and will either relinquish
the bus or wait to be forced to relinquish the bus. For
discussion on MULTIBUS arbitration techniques, refer to
Application Note AP-28A, Intel MULTIBUS Interfacing.

QSO, QS1
The QSl and QSO (Queue Status) outputs permit external
monitoring of the CPU's internal instruction queue to allow instruction set extension processing by a coprocessor.
(The corresponding Intel ICE modules use these status
bits during "trace" operations.) The encoding of the QS 1
and QSO bits is shown in Table 1-39.

To support a multi-master interface to the MULTIBUS
system bus for the 8086 family, the 8289 bus arbiter is
included as part of the family. The 8289 is compatible
with the 8086's local bus and in conjunction with the 8288
bus controller, implements the MULTIBUS protocol for
bus arbitration. The 8289 provides a variety of arbitration
and prioritization techniques to allow optimization of bus
availability, throughput, and utilization of shared resources. Additional features (implemented through strapping options) extend the configuration options beyond a
pure CPU interface to the multi-master system bus for

1.4.7 Interpreting The 8086/8088 Bus
Timing Diagrams
The 8086/8088 bus timing diagrams are a powerful tool
for determining system requirements. The timing diagrams for both the minimum and maximum modes (Figures 1-83 and 1-84) may be divided into six sections: (1)
address and ALE; (2) read cycle timing; (3) write cycle
timing; (4) interrupt acknowledge timing; (5) ready timing; and (6) HOLD/HLDA or RQ*/GT* timing. Since the
A.C. characteristics of the signals are specified relative to
the CPU clock, the relationship between the majority of
the signals can be reduced by simply determining the
clock cycles between the clock edges the signals are relative to and adding or subtracting the appropriate minimum
or maximum parameter values. One aspect of system timing not compensated for in this approach is the worst case
relationship between the minimum and maximum parameter values (also known as tracking relationships). As an
example, consider a signal which has specified minimum
and maximum turn on and turn off delays. Depending on
device characteristics, it may not be possible for the component to simultaneously demonstrate a maximum turn on
and a minimum turn off delay even though worst case
analysis might imply the possibility. This argument is
characteristic of MOS devices and is therefore applicable
to the 8086 A.C. characteristics. Therefore, the designer
should assume that in worst case analysis mixing mini-

SHARED
PERIPHERALS

Figure 1·82 8086 Family Multiprocessor System

1·98

210912'()01

8086/8088 CPU

and TCLAX apply to the entire multiplexed bus for both
read and write cycles. AD15-0 is tri-stated for read cycles
and immediately switched to write data during write cycles. AD 19-16 immediately switch from address to status
for both read and write cycles. TLHLLmin, which takes
precedence over the value obtained by relating
TCLLHmax and TCHLLmin, guarantees the minimum
ALE pulse width.

Table 1·39 Queue Status Bit Decoding
QS1

QSO

Queue Status

o(low)

0

No Operation. During the last
clock cycle, nothing was taken
from the queue.

0

1

First Byte. The byte taken from the
queue was the first byte of the
instruction.

1 (high)

0

Queue Empty. The queue has
been reinitialized as a result of the
execution of a transfer instruction.

1

1

Subsequent Byte. The byte taken
from the queue was a subsequent
byte of the instruction.

To determine the worst case delay-to-valid address on a
demultiplexed address bus, two paths are considered: (1)
delay of valid address and (2) delay to ALE. Since the
D-type latches are flow through devices, a valid address is
not transmitted to the address bus until ALE is active. A
comparison of address valid delay TCLAVmax with ALE
active, delay TCLLHmax indicates TCLAVmax is the
worst case. Subtracting the latch propagation delay gives
the worst case address bus valid delay from the start of the
bus cycle.

Minimum Mode Read Cycle Timing
The queue status is valid during the eLK cycle after which the
queue operation is performed.

Read timing consists of conditioning the bus, activating
the read command and establishing the data transceiver
enable and direction controls. DT/R* is established early
in the bus cycle and requires no further consideration.
During read, the DEN* signal must allow the transceivers
to propagate data to the CPU with the appropriate data
setup time and continue to do so until the required data
hold time. The DEN* turn on delay allows TCLCL +
TCHCLmin - TCVCTV max - TDVCL = 127 ns transceiver enable time prior to valid data required by the
CPU. Since the CPU data hold time TCLDXmin and minimum DEN* turnoff delay TCVCTXmin are both 10 ns
relative to the same clock edge, the hold time is guaranteed. Additionally, DEN* must disable the transceivers
prior to the CPU, redriving the bus with the address for
the next bus cycle. The maximum DEN* turn off delay
(TCVCTXmax), compared with the minimum delay for
addresses out of the 8086 (TCLCL + TCLAVmin), indicates the transceivers are disabled at least 105 ns before
the CPU drives the address onto the multiplexed bus.

mum and maximum delay parameters will typically exceed the worst case obtainable and should therefore
receive further subjective degradation to obtain
worst-worst case values. This following paragraphs provide guidelines for specific areas of 8086 timing sensitive
to tracking relationships.

MINIMUM MODE BUS TIMING
The minimum mode address and ALE timing relationship
determines the ability to capture a valid address from the
multiplexed bus. Since the D-type latches capture the address on the trailing edge of ALE, the critical timing involves the state of the address lines when ALE terminates.
If the address valid delay is assumed to be maximum
TCLAV and ALE terminates at TCHLLmin, its earliest
point (assuming zero minimum delay), the address would
be valid only if TCLCHmin-TCLAVmax = 8 ns prior to
ALE termination. This result is unrealistic in the assumption of maximum TCLAV and minimum TCHLL. To provide an accurate measure of the true worst case, a
separate parameter specifies the minimum time for address valid prior to the end of ALE (TAVAL). TAVAL =
TCLCH-60 ns overrides the clock related timings and
guarantees 58 ns of address setup to ALE termination for
a 5 MHz 8086. The address is guaranteed to remain valid
beyond the end of ALE by the TLLAX parameter. This
specification overrides the relationship between TCHLL
and TCLAX which might seem to imply the address may
not be valid by the end of the latest possible ALE.
TLLAX holds for the entire address bus. The TCLAXmin
specification on the address indicates the earliest the bus
will go invalid if not restrained by a slow ALE. TLLAX

If memory or 110 devices are connected directly to the
multiplexed address and data bus, the TAZRL parameter
guarantees the CPU will float the bus before activating
read, allowing the selected device to drive the bus. At the
end of the. bus cycle, the TRHAV parameter specifies the
bus float delay the device being deselected must satisfy to
avoid contention with the CPU driving the address for the
next bus cycle. The next bus cycle may start as soon as
the cycle following T4 or any number of clock cycles
later.
The minimum delay from read active to valid data at the
CPU is 2TCLCL - TCLRLmax - TDVCL = 205 ns. The
minimum pulse width is 2TCLCL -75 ns = 325 ns. This
specification (TRLRH) overrides the result which could

1-99

210912·001

8086/8088 CPU

T,

CLK (8214 OUTPUll

~

TCHCTV

I--

TCLAV-

- -

TCLLHALE

r

~TfLDV

TCLAX-

TCHDX -

lilt, A,,-A,

I

I

VIH-X

. ' "';\ ~~~\~ ~~ ~~

\'

_f-

I-TCLR X

-

-

I

- :- TAVAL

-TRYHCH-

-

TDVCL _ _ -TCLDX-

!-TCLAX

DATA IN

Au-Ao
TAZRL-

READ CYCLE

::'~TCHCTV

TCLRL

-"FCHRYX

-

-

TLLAX-

I--

r--

----

_TR1VCL

4-

~R~R

TCLAV

-

I-- T~LAX

V,L -

I
I

)

57-Sa

TLHLL-=:

-TAVAL-

RDY (12141NPUll
SEE NOTE 4

DT/R

T.

_TCLCH_

TCHCL

TCHLL-I

NOTE'
(WI!, IRTA. VOH)

Tw

''"''=-;C:JHC~~'---In-

MOO

READY (1011 IN PUll

T,

T.

::{
f/

TCLAH-

,-'

r----

TRLRH

TCVCTV-

FLOAT/--!'--TRHAV

t=.rCHCTV

I

TCVCTX -

I

1

Figure 1·83 8086 Bus Timing - Minimum Mode System

1-100

210912-001

8086/8088 CPU

T,

12

T3

Tw

T4

"'_oo_:"~=~~n,t::. ~

TCHCTV

TCHCL

MI~

.~

~

ALE

TCLDV_
TClAX _
'--

TCHDX -

TLHLL-:::::

_

-

TLlAX

AD,,-AD,

TCVCTV __

r-:.r,

_+-__+-___'""',,ffi

-JJ: __ _

1~~__~I______________~I____~l____

TA1AL

AD,,-ADo -+---t-,:,J-(J

r __

I

"~-; ;:~1 E

TelAV"

,II:......

~+-_________S_,-_S3____~I______~J)(~______

1-

TCLLH-

~iI"f,.~~)

x=

TCLCH_

~
TClAV-

WRITE CYCLE
NOTE 1

-

I ""P -

If.-

{
Jr----{/

DATA OUT

-TWHD~

-ITAVAl

T~lAX 1_

-

'TCVCTX

~~--+-----------+-+-~~
I

TCVCTV-

1'-__
-- +-___

'{

TWlWH

Viii
I~

TCVCTX-

_+-_-_t---.\I-TClAZ

~r
INTA CYCLE
NOTES 113

DT/R

I-TDVCL-

>---.....-+-.,,-,--,--+L-----,,(1/

TCHCTV

FLOAT

\

"J..-_'TC_I+-.D.".X,.."..,.".-_-<,
"

I/\J

Fl,O_A_:_C_HC_T_V_ _

-+;--t--

\

---'1/

:Rr~~L~OH

POINTER

_:==TCV=CTV_:{/--

~4-);--

r-7

V

TCVCTV_V

TCVCTX-

DEN

t;r-+-------

"-'- _ _ _ _ _---J

SOFTWARE HALT _ (DEN ..

VOL; lID, \VA.1liTA DT/Ii. VOH; AD,,-AD,
T!'S FOllOW TI, THEN NMI OR INTR
BEGIN A NEW TI.
AD1S- AD o

~ 'r
TClAV::::::j
NOTES:

INVALID ADDRESS

'-r=--

1. All SIGNALS SWITCH BETWEEN VOH AND VOl UNLESS OTHERWISE
SPECIFIED.
2. ROY IS SAMPLED NEAR THE END OF Ta. Ta. Tw TO DETERMINE IF Tw
MACHINES STATES ARE TO BE INSERTED.
3. BOTH INTA CYCLES RUN BACK·TO·BACK. THE lIOII lOCAL ADDRIDATA BUS IS
FLOATING DURING THE SECOND INTA CYCLE. CONTROL SIGNALS SHOWN
FOR SECOND INTA CYCLE•
•. SIGNALS AT 1214 ARE SHOWN FOR REFERENCE ONLY.
5. All TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE
NOTED.

Figure 1·83 8086 Bus Timing - Minimum Mode System (continued)

1-101

210912-001

8086/8088 CPU

T,
-TCLCLCLK

vCH r--"
VCl -1

.;----\
"---J

TCLAV~

.1:-

~

-

1

SEE NOTE 5

_TCLCH_

-

TCLLH-

-TCLSH

W& ~/.1

~CLOV

{

\

SEj NOTE 8
TCHOX-

ii'HE,A ... A1I

ALE (8288 OUTPUT)

-f\-

~

-

r-TCLAV
TCLAX-

T.

;~

TCHCL

TCHSV

TSVLH~

I

1"'---"

~

l.

Q5"QS,

s,:s"S;; (EXCEPT HALT)

T,

TCH1CH21H[TCL2CLl

------

'------

57-53

TCHLL

r--

1..---

~ -~~~ ~
!--TR1VCL

~

ROY (8284 INPUT)

I

~-TCLR1~

TRYLCL

READY (8088 INPUT)

TYHSH~I

--

TRYHCHzf

READ CYCLE

TClAV--j

AD'S-ADo

i

F . . -. 'f('
-TCLAZ

I-

f-TCHRYX

-

TDVCL~ !--TCLDX-

DATA IN
TCLRH

TAZRL- -

/

RD
TCHDTL

-I

--

TCLRL
TRLRH

DT/A

-

TCLML-

TCLMH--

8288 OUTPUTS
SEE NOTES 5,6
TCVNVDEN

,

FL~:JL

~

TRHAV

TCHDTH

F1

II---

/r
TCVNX-

Figure 1-84 8086 Bus Timing - Maximum Mode System (Using 8288)

1-102

210912·001

8086/8088 CPU

T,

T,

ClK

1i.It.SO (EXCEPT HALT)

WRITE CYCLE

-

}

TCLAV--

~SEENOTE.

TCYNV-

.I:.TCLDY

\

,~----

TCHDX-

X

Y-c

DATA

,--

TCYNX-

DEN

.... """"'"

SEe NOTES 5,.

-

i-TClMl

TCLMH-

AMWC: OR Alowe
~

TCLMl

-

t--

-TCLMH

INTACYCLE
"On-ADo

SEE NOTES 3 ....

FLOAT

_

RESERVED FOR

/~ICT~:DEADDR

\

rr:,

.lOu-ADo

:=

\.)....--1-....,.__-------4---+.,-=--(rFLOAT

TDVCl-

~TC :~OAT

POINTER

MCEI

PliEIi
OTIA

..... """"'"

SEE NOTES 5,6

DEN
TCVNX-

x.:
'F' ------------

ADn-ADo

INVALID ADDRESS

TClAV-

'

jr------.-\-------

~

----'

.......

NOTES:

\._-----

1. ALL SIGNALS SWITCH BETWEEN YOH AND VOL UNLESS OTHERWISE

SPECIFIED.
2. ROY IS SAMPLED NEAR THE END OF T2. T3. Tw TO DETERMINE IF Tw
MACHINES STATES ARE TO BE INSERTED.
S. CASCADE ADDRESS IS VALID BETWEEN FIRST AND SECOND INfA CYCLES•
•• 10TH INTA CYCLES RUN BACK·To-IACK. THE I0Il LOCAL ADDRIOATA BUS IS

FLOATlNQ DURING THE SECOND INTA CYCLE. CONTROL FOR POINTER ADDRESS
IS SHOWN FOR SECOND INTA CYCLE.
5. SIGNALS AT 1214 OR 1211 ARE SHOWN FOR REFERENCE ONLY.
e. THE ISSUANCE OF THE 1211 COMMAND AND CONTROL SIGNALS (1IRDe,
IIWTC. ~.RI"IIe. ~. ~.1IiTl AND DEN) LAGS THE ACnVE HIGH
UIII eEN.
7. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE
NOTID.
I. ITATUI INACTIVE IN ITATE JUST PRIOR TO T..

Figure 1-84 8086 Bus Timing - Maximum Mode System (continued)
1-103

210912-001

8086/8088 CPU

be derived from the clock relative delays (2TCLCL-TCLRLmax + TCLRHmin).

each of the INTA * bus cycles. The interrupt type number
read by the 8086 on the second INTA * bus cycle must
satisfy the same setup and hold times required for data
during a read cycle.

Minimum Mode Write Cycle Timing

The write cycle provides write data to the system, generates the write command and controls data bus transceivers. The transceiver direction control signal DT/R* is
conditioned to transmit at the end of each ready cycle and
does not change during a write cycle. This process allows
the transceiver enable signal DEN* to be active early in
the cycle (while addresses are valid) without corrupting
the address on the multiplexed bus. The leading edge of
T2 enables both the write data and write command. A
comparison of minimum WR* active delay TCVCTVmin
with the maximum write data delay TCLDV indicates that
write data may be not valid until 100 ns after write is
active. The devices in the system should capture data on
the trailing edge of the write command rather than the
leading edge to guarantee valid data. The data from the
8086 is valid a minimum of 2TCLCL - TCLDVmax +
TCVCTXmin = 300 ns before the trailing edge of write.
The minimum write pulse width is TWLWH =
2TCLCL - 60 ns = 340 ns. The CPU maintains valid
write data TWHDX ns after write. The TWHDZ specification overrides the result derived by relating TCLCHmin
and TCHDZmin which implies write data may only be
valid 18 ns after WR*. Normally the CPU simply
switches the output drivers from data to address at the
beginning of the next bus cycle. If forced off the bus by a
HOLD or RQ* input, the 8086 floats the bus after write.
As with the read cycle, the next bus cycle may start in the
clock cycle following T4 or any clock cycle later.
The CPU disables DEN* a minimum of TCLCHmin +
TCVCTXmin-TCVCTXmax= 18 ns after write to
guarantee data hold time to the selected device. Again
comparing TCVCTXmin with TCVCTXmax, the real
minimum delay from the end of write to transceiver disable equals approximately 60 ns.

Minimum Mode Interrupt Acknowledge Timing

The interrupt acknowledge sequence consists of two interrupt acknowledge timing cycles as previously described.
The detailed timing of each cycle is identical to the read
cycle timing with two exceptions: command timing and
.address/data bus timing.
The multiplexed address/data bus floats from the beginning (Tl) of the INTA* cycle (within TCLAZ ns). The
upper four multiplexed address/status lines do not
three-state. The address value on A19-A16 is indeterminate, but the status information will be valid (S3 = 0,
S4=0, S5=IF, S6=0, S7=BHE*=0). The multiplexed
address/ data lines will remain in three-state until the cycle after T4 of the INTA * cycle. This sequence occurs for

The DEN* and DT/R* signals are enabled for each
INTA * cycle and do not remain active between the two
cycles. Their timing for each cycle is identical to the read
cycle.
The INTA * command has the same timing as the write
command. It is active within lIOns of the start of T2 providing 260ns of access time from command to data valid
at the 8086. The command is active a minimum of
TCVCTXmin = IOns into T4 to satisfy the data hold time
of the 8086. This provides minimum INTA* pulse width
of 300ns, however, taking signal delay tracking into consideration gives a minimum pulse width of 340ns. Since
the maximum inactive delay of INTA* is TCVCTXmax = lIOns and the CPU will not drive the bus until 15ns
(TCLAVmin) into the next clock cycle, 105ns are available for interrupt devices on the local bus to float their
outputs. If the data bus is buffered, DEN* provides the
same amount of time for local bus transceivers the
three-state the outputs.

Minimum Mode Ready Timing

The CPU typically generates the system ready signal from
either the address decode of the selected device or the
address decode and the command (RD*, WR *, INTA *.
For a system which is normally not ready, the time to
generate ready from a valid address and not insert a wait
state, requires 2TCLCL - TCLAVmax - TRI VCLmax =
255 ns. This time is available for buffered delays and address decoding to determine if the selected device does
not require a wait state and drive the RDY line high. If
wait cycles are required, the user hardware must provide
the appropriate ready delay. Since the address will not
change until the next ALE, RDY will remain valid
throughout the cycle. If the system is normally ready, selected devices requiring wait states also have 255 ns to
disable the RDY line. The user circuits must delay
re-enabling RDY by the appropriate number of wait
states.
If the RD* command is used to enable the RDY signal,
TCLCL - TCLRLmax - TRIVCLmax = 15 ns are available for external logic. If the WR* command is used, TCLCL - TCVCTVmax - TRIVCLmax = 55 ns is available.
Comparison of RDY control by address or command indicates that address decoding provides the best timing. If
the system is normally not ready, address decode alone
could be used to provide RDY for devices not requiring
wait states while devices requiring wait states may use a
combination of address decode and command to activate a
wait state generator. If the system is normally ready, devices not requiring wait states do Iiothing to RDY while

1-104

210912-001

8086/8088 CPU

devices needing wait states should disable RDY via the
address decode and use a combination of address decode
and command to activate a delay to re-enable RDY.
If the system requires no wait states for memory and a
fixed number of wait states for RD* and WR* to alillO
devices, the M/IO* signal can be used as an early indication of the need for wait cycles. This techniques allows a
common circuit to control ready timing for the entire system without feedback of address decodes.

Minimum Mode TEST" Timing
The TEST* input is sampled by the 8086 only during execution of the WAIT instruction. The TEST* signal should
be active for a minimum of 6 clock cycles during the
WAIT instruction to guarantee detection.

TCLCHmax must be used since TCHCLmin was assumed
to derive the 58 ns ALE enable delay. The address is guaranteed to be valid TCLCHmin + TCHLLmin - TCLAVmax = 8 ns prior to the trailing edge of ALE to capture
the address in the latches. Again we have assumed a very
conservative TCHLL = O. Note, since the address of ALE
are driven by separate devices, no tracking of A.C. characteristics can be assumed.
The address hold time to the latches is guaranteed by the
address remaining valid until the end of Tl while ALE is
disabled a maximum of 15 ns from the positive clock transition in Tl (TCHCLmin - TCHLLmax = 52 ns address
hold time). The multiplexed bus transitions from address
to status and write data or tri-state (for read) are identical
to the minimum mode timing. Also, since the address
valid delay (TCLAV) remains the critical path in establishing a valid address, the address access times to valid data
and ready are the same as the minimum mode system.

MAXIMUM MODE BUS TIMING
Maximum Mode Read Cycle Timing
The maximum mode 8086 bus operations are logically
equivalent to the minimum mode operation. Detailed timing analysis now involves signals generated by the CPU
and the 8288 bus controller. The 8288 also provides additional control and command signals which expand the
flexibility of the system.

Maximum Mode Address and ALE Timing
In the maximum mode, the address information continues
to come from the CPU while the ALE strobe is generated
by the 8288. To determine the worst case relationships
between ALE and the address, we first must determine
8288 ALE activation relative to the SO*-S2* status from
the CPU. The maximum mode timing diagram specifies
two possible delay paths to generate ALE. The first is
TCHSV + TSVLH measured from the rising edge of the
clock cycle preceding T1. The second path is TCLLH
measured from the start of T 1. Since the 8288 initiates a
bus cycle from the states lines leaving the passive states
(SO* - S2* = I), if the 8086 is late in issuing the status
(TCHSVrnax) while the clock high time is a minimum
(TCHCLmin), the status will not have changed by the
start of T I and ALE is issued TSVLH ns after the status
changes. If the status changes prior to the beginning of
Tl, the 8288 will not issue the ALE until TCLLH ns after
the start of T1. The resulting worst case delay to enable
ALE (relative to the start of Tl) is TCHSVmax +
TSVLHmax - TCHCLmin = 58 ns. Note, whencalculating signal relationships, be sure to use the proper maximum mode values rather than equivalent minimum mode
values.
The trailing edge of ALE is triggered in the 8288 by the
positive clock edge in Tl regardless of the delay to enable
ALE. The resulting minimum ALE pulse width is
TCLCHmax-58 ns= 75 ns assuming the TCHLL= O.

The maximum mode system offers read signals generated
by both the 8086 and the 8288. The 8086 RD* output
signal timing is identical to the minimum mode system.
Since the A.C. characteristics of the read commands generated by the 8288 are significantly better than the 8086
output, access to devices on the demultiplexed buffered
system bus should use the 8288 commands. The 8086
RD* signal is available for devices which reside directly
on the multiplexed bus. The following evaluations for
read, write and interrupt acknowledge only consider the
8288 command timing.
The 8288 provides separate memory and 1/0 read signals
which conform to the same A.C. characteristics. The
commands are issued TCLML ns after the start of T2 and
terminate TCLMH ns after the start of T4. The minimum
command
length
is
2TCLCL - TCLMLmax +
TCLMLmin = 375 ns. The access time to valid data at the
CPU is 2TCLCL - TCLMLmax - TDVCLmax = 335 ns.
Since the 8288 was designed for systems with buffered
data busses, the commands are enabled before the CPU
has tri-stated the multiplexed bus and should not be used
with devices which reside directly on the multiplexed bus
(to do so could result in bus contention during 8086 bus
float and device tum-on).
The direction control for data bus transceivers is established in TI while the transceivers are not enabled by
DEN until the positive clock transition of T2. This provides TCLCH + TCVNVmin = 123 ns for 8086 bus float
delay and TCHCLmin + TCLCL - TCVNVmax - TDVCLmax = 187 ns of transceiver active to data valid at the
CPU. since both DEN and command are valid a minimum
of 10 ns into T4, the CPU data hold time TCLDX is guaranteed. A maximum DEN disable of 45 ns (TCVNXmax)
guarantees the transceivers are disabled by the start of the
next 8086 bus cycle (215 ns minimum from the same

H05

210912-001

8086/8088 CPU

clock edge). On the positive clock transition of T4,
DT/R * is returned to transmit in preparation for a possible write operation on the next bus cycle. Since the system memory and.IlO devices reside on a buffered system
bus, they must tri-state their outputs before the device for
the next bus cycle is selected (approximately 2TCLCL) or
the transceivers drive write data onto the bus (approximately 2TCLCL).

Maximum Mode Write Cycle Timing

In the maximum mode, the 8288 provides normal and advanced write commands for memory and I/O. The advanced write commands are active a full clock cycle ahead
of the normal write commands and have timing identical
to the read commands. The advanced write pulse width is
2TCLCL- TCLMLmax + TCLMHmin = 375 ns while
the normal write pulse width is TCLCL - TCLMLmax +
TCLMHmin = 175 ns. Write data setup time to the selected device is a function of either the data valid delay
from the 8086 (TCLDV) or the transceiver enable delay
TCVNY. The worst case delay to valid write data is
TCLDV = 110 ns minus transceiver propagation delays.
This implies the data may not be valid until lOOns after
the advanced write command but will be valid approximately TCLCL-TCLDVmax+ TCLMLmin 100 ns
prior to the leading edge of the normal write command.
Data will be valid 2TCLCL-TCLDVmax +
TCLMHmin = 300 ns before the trailing edge of either
write command. The data and command overlap for the
advanced command is 300 ns while the overlap with the
normal write command is 175 ns. The transceivers are
disabled a minimum of TCLCHmin - TCLMHmax +
TCVNXmin = 85 ns after the write command while the
CPU provides valid data a minimum of TCLCHmin - TCLMHmax + TCHDZmin = 85 ns. This guarantees
write data hold of 85 ns after the write command. The
transceivers are disabled TCLCL - TCVNXmax + TCHDTLmin = 155 ns (assuming TCHDTL = 0) prior to
transceiver direction change for a subsequent read cycle.

Maximum Mode Interrupt Acknowledge Timing

The maximum mode INTA * sequence is logically identical to the minimum mode sequence. The transceiver control (DEN and DT/R*) and INTA* command timing of
each interrupt acknowledge cycle is identical to the read
cycle. As in the minimum mode system, the multiplexed
address/data bus will float from the leading edge of Tl for
each INTA * bus cycle and not be drive by the CPU until
after T4 of each INTA* cycle. The setup and hold times
on the vector number for the second cycle are the same as
data setup and hold for the read. If the device providing
the interrupt vector number is connected to the local bus,
TCLCL - TCLAZmax + TCLMLmin = 130 ns are available from 8086 bus float to INTA * command active. The

selected device on the local bus must disable the system
data bus transceivers since DEN is still generated by the
8288.
If the 8288 is not in the lOB (I/O Bus) mode, the 8288
MCE/PDEN* output becomes the MCE output. This output is active during each INTA * cycle and overlaps the
ALE signal during Tl. The MCE is available for gating
cascade addresses from a master 8259A onto three of the
upper AD15-AD8 lines and allowing ALE to latch the
cascade address into the address latches. The address
lines may then be used to provide CAS and address selection to slave 8259A's located on the system bus (see Figure
1-85). MCE is active within 15 ns of status or the start of
Tl for each INTA * cycle. MCE should not enable the
CAS lines onto the multiplexed bus during the first cycle
since the CPU does not guarantee to float the bus until 80
ns into the first INTA * cycle. The first MCE can be inhibited by gating MCE with LOCK*. The 8086 LOCK* output is activated during T2 of the first cycle and disabled
during T2 of the first cycle and disabled during T2 of the
second cycle. The overlap of LOCK* with MCE allows
the first MCE to be masked and the second MCE to gate
the cascade address onto the local bus. Since the 8259A
will not provide a cascade address until the second cycle,
no information is lost. As with ALE, MCE is guaranteed
valid within 58 ns of the start of Tl to allow 75 ns CAS
address setup to the trailing edge of ALE. MCE remains
active TCHCLmin - TCHLLmax + TCLMCLmin = 52
ns after ALE to provide data hold time to the latches.
If the 8288 is strapped in the lOB mode, the MCE output
becomes PDEN* and all I/O references are assumed to be
devices on the local bus rather than the demultiplexed system bus. Since INTA * cycles ilre considered I/O cycles,
all interrupts are assumed to come from the local system
and cascade addresses are not gated onto the system address bus. Additionally, the DEN signal is not enabled
since no I/O transfers occur on the system bus. If the local
I/O bus is also buffered by transceivers, the PDEN* signal is used to enable those transceivers. PDEN* A.C.
characteristics are identical to DEN with PDEN* enabled
for I/O references and DEN enabled for instruction or
memory data references.

Maximum Mode Ready Timing

Ready timing based on address valid timing is the same
for maximum and minimum mode systems. The delay
from 8288 command valid· to RDY valid ;It the 8284 is
TCLCL - TCLMLmax - TRlVCLmin = 130 ns. This
time is available for external circuits to determine the
need to insert wait states and disable ROY or enable RDY
to avoid wait states. INTA*, all read commands and advanced write commands provide this timing. The normal
write command is not valid until after the RDY signal
must be valid. Since both normal and advanced write

1-106

210912-001

8086/8088 CPU

ADDRESS

~T------r------'-r-------~,~----~/BUS

DATA

~------------------------------~/BUS

Figure 1-85 Max Mode 8086 with Master 8259A on the Local Bus and Slave 8259A's on the System Bus

commands are generated by the 8288 for all write cycles,
the advanced write may be used to generate a RDY indication even though the selected device uses the normal write
command.
Since separate commands are provided for memory and
110, no M/IO* signal is specifically available as in the
minimum mode to aIlowan early 'wait state required' indication for 110 devices. The S2 * status line, however is
logically equivalent to the M/IO* signal and can be used
for this purpose.
Other Maximum Mode Considerations

The RQ*/GT* timing is covered in the Bus Exchange
Mechanisms section paragraph 1.6.2 Maximum Mode
(RQ*/GT*) later in this chapter and will not be duplicated
here. The only additional signals to be considered in the
maximum mode of operation are the queue status line
QSO and QS1. These signals are changed on the leading
edge of each clock cycle (high to low transition) including
idle and wait cycles (the queue status independent of bus
activity). External logic may sample the lines on the low
to high transition of each clock cycle. When sampled, the
signals indicate the queue activity in the previous clock
cycle and therefore lag the CPU's activity by one cycle.
The TEST* input requirements are identical to those
stated for the minimum mode.
To inform the 8288 of HALT status when a HALT instruction is executed, the 8086 will initiate a status transition

from passive to HALT status. The status change will
cause the 8288 to emit an ALE pulse with an indeterminate address. Since no bus cycle is initiated (no command
is issued), the results of the address will not affect the
CPU operation (i.e., no response such as READY is expected from the system). This external hardware to latch
and decode all transitions in system status.

1.4.8 Wait State Insertion
The ready signal is used in the system to accommodate
memory and I/O devices that cannot transfer information
at the maximum CPU bus bandwidth. Ready is also used
in multiprocessor systems to force the CPU to wait for
access to the system bus or MULTmUS system bus. To
insert a wait state in the bus cycle, the READY signal to
the CPU must be inactivate (low) by the end of T2. To
avoid insertion of a wait state, READY must be active
(high) within a specified setup time prior to the positive
transition during T3. Depending on the size and characteristics of the system, ready implementation may take
one of two approaches.
The classical ready implementation is to have the system
'normally not ready'. When the selected device receives
the command (RD*IWR*/INTA*) and has had sufficient
time to complete the command, it activates READY to the
CPU, allowing the CPU to terminate the bus cycle. This
implementation is characteristic of large multiprocessor,
MULTIBUS systems or systems where propagation de-

1-107

210912-001

8086/8088 CPU

CLOCK

8088 READY

READY INACTIVE.

I

na

HOLD TIME 30 '"

-J I--.•

1 nl TO GUARANTEE THE
NEXT CYCLE IS T,

Figure 1·86 Normally Ready System Inserting a Wait State

CLOCK

1D18 READY

Figure 1·87 Normally Not Ready System Avoiding a Wait State
lays, bus access delays and device characteristics inherently slow down the system. for maximum system
performance, devices that can run with no wait states
must return 'READY' within the previously described
limit. Failure to respond in time will only result in the
insertion of one or more wait cycles.
An alternate technique is to have the system 'normally
ready'. All devices are assumed to operate at the maximum CPU bus bandwidth. Devices that do not meet the
requirement must disable READY by the end of T2 to
guarantee the insertion of wait cycles. This implementation is typically applied to small single CPU systems and
reduces the logic required to control the ready signal.
Since the failure of a device requiring wait states to disable READY by the end of T2 will result in premature
termination of the bus cycle, the system timing must be
carefully analyzed when using this approach.

both cases, READY must satisfy a hold time of 30 ns
(TCHRYX) from the T3 or TW positive clock transition.
To generate a stable READY signal which satisfies the
previous setup and hold times, the 8284 provides two separate system ready inputs (RDY1, RDY2) and a single
synchronized ready output (READY) for the CPU. The
RDY inputs are qualified with separate access enables
(AEN1*, AEN2*, low active) to allow selecting one of
the two ready signals (see Figure 1-88). The gated signals
are logically OR'ed and sampled at the beginning of each
CLK cycle to generate READY to the CPU (see Figure

aYE---1!
.7

+5

The 8086 has two different timing requirements on
READY depending on the system implementation. for a
'normally ready' system to insert a wait state, the READY
must be disabled within 8 ns (TRYLCL) after the end of
T2 (start of T3) (see Figure 1-86). To guarantee proper
operation of the 8086, the READY input must not change
from ready to not ready during the clock low time of T3.
For a 'normally not ready' system to avoid wait states,
READY must be active within 119 ns (TRYHCH) of the
positive clock transition during T3 (see Figure 1-87). For

1·108

~
11

~

~

~
~

...!

X.

ClK

8

RESET .0
X.

Fie

READY

8284

5

18
21
22

ClK
RESET
READY
8088

RES
AENI
RDYI
AEN2
RDY2

Figure 1·88 Ready Inputs to the 8284
and Output to the 8086/88
210912·001

8086/8088 CPU

1-89). The sampled READY signal is valid within 8 ns
(TRYLCL) after CLK to satisfy the CPU timing requirements on 'not ready' and ready. Since READY cannot
change until the next CLK, the hold time requirements
are also satisfied. The system ready inputs to the 8284
(RDY1, RDY2) must be valid 35 ns (TRIVCL) before T3
and AEN* must be valid 60 ns before T3. For a system
using only one RDY input, the associated AEN* is tied to
ground while the other AEN* is connected to 5 volts
through approximately lK ohms (see Figure 1-90). If the
system generates a low active ready signal, it can be connected to the 8284 AEN* input if the additional setup time
required by the 8284 AEN* input is satisfied. In this case,
the associated RDY input would be tied high (see Figure
1-91).

1.4.9 8086/8088 Instruction Sequence
Figure 1-92 illustrates the internal operation and bus activity that occur as an 8086 CPU executes a sequence of
instructions. This figure presents the signals and timing
relationships that help illustrate 8086 operation. The following discussion interprets the figure.
Figure 1-92 shows the repeated execution of an instruction loop. This loop is defined in both machine code and
assembly language by Figure 1-93. The loop demonstrates both the effects of a program jump on the queue
and makes the instruction sequence easy to follow. The
program sequence consists of seven instructions and 16
bytes, and is typical of the tight loops found in many application programs. This particular sequence contains
several sort, fast-executing instructions that demonstrate
both the effect of the queue on CPU performance and the
interaction between the execution unit (EU) fetching code
from the queue and the bus interface unit (BIU) filling the
queue and performing the requested bus cycles. For the
purpose of this discussion, code, stack, and memory data
references are aligned on even word boundaries. The entire sequence of instructions has taken 55 clock cycles.
Eighteen opcode bytes were fetched, one word memory
read occurred, and one word stack write was performed.
Consider that the loop starts in clock cycle 1 with the
queue reinitialization that occurs as part of the JMP instruction. The EU completes JMP instruction execution.
While the BIU performs an opcode fetch to begin refilling
the queue.
In clock cycle 8, the queue status lines indicate that the
first byte of the MOV immediate instruction has been removed from the queue (one clock cycle after it was placed
there by the BIU fetch) and that execution of this instruction has begun. The second byte of this instruction is
taken from the queue in clock cycle 10 and then, during
clock cycle 12, the EU pauses to wait one clock cycle for
the second BIU opcode fetch to complete and for the third

byte of the MOV immediate instruction to be come available for execution (recall that the queue status lines indicate queue activity that has occurred in the previous
clock).
Clock cycle 13 begins the execution of the PUSH AX
instruction, and during clock cycle 15, the BIU begins the
fourth opcode fetch. The BIU finishes the fourth fetch in
clock cycle 18 and prepares for another fetch when it receives a request from the EU for a memory write (the
stack push). Instead of completing the opcode fetch and
forcing the EU to wait for additional clock cycles, the BIU
immediately aborts the fetch cycle (resulting in two idle
clock cycles, TI, in clock cycles 19 and 20) and performs
the required memory write. This interaction between the
EU and BIU results in a single clock extension to the execution time of the PUSH AX instruction, the maximum
delay that can occur in response to an EU bus cycle request.
Execution continues during clock cycle 24 with the execution of sequential register-to-register MOV instructions. The first of these instructions takes full advantage
of the pre fetched opcode to complete this operation in two
clock cycles. The second MOV instruction, however, depletes the queue and requires two additional clock cycles
(28 and 29).
During clock cycle 30, the ADD memory indirect to AX
instruction begins. In the time required tv execute this
instruction, the BIU completes two opcode fetch cycles
and a memory read, then begins a fourth opcode fetch
cycle. Note that in the case of the memory read, the EU's
request for a bus cycle occurs at a point in the BIU fetch
cycle where it can be incorporated directly (idle states are
not required and no EU delay is imposed).
During clock cycle 44, the EU begins the ADD immediate instruction, taking four bytes from the queue and completing instruction execution in four clock cycles. Also
during this time, the BIU senses a full queue during clock
cycle 45 and enters a series of bus idle states (five or six
bytes constitute a full queue in the 8086; the BIU waits
until it can fetch a full word or opcode before accessing
the bus).
At clock cycle 47, the BIU again begins a bus cycle sequence, one that becomes an "overfetch" since the EU is
executing a JMP instruction. As part of the JMP instruction, the queue reinitialization (which began the instruction sequence) occurs.
The example can be easily extended to incorporate wait
states in the bus access cycles. In the case of a single wait
state, each bus cycle would be lengthened to five clock
cycles with a wait state (TW) inserted between every T3
and T4 state of the bus cycle. As a first approximation,
the instruction sequence execution time would appear to
be lengthened by 10 clock cycles, one cycle for each useful read or write bus cycle that occurs. Actually, this ap-

1-109

210912-001

8086/8088 CPU

---~~I--

T4ffw

CLOCK

8284 RDY SETUP

8284 READY OUT
(TO 8088)

NOTE: THE 8284 DATA SHEET SPECIFIES READY OUT DELAY (TRYLCL) AS -I ..
'BEFORE' THE END OF T2 WHICH IMPLIES THE TIMING SHOWN.

Figure 1·89 8284 With 8086/88 Ready Timing
proximation for the number of wait states inserted is
incorrect since the queue can compensate for wait states
by making use of previously idle bus time. For the example code sequence, this compensation reduced the actual
execution time by one wait state, and the sequence was
completed in 64 clock cycles, one less than the approximated 65 clock cycles.
This example is, deliberately, partially bus limited and indicates the types of EU and BIU interaction that can occur
in this type of situation. Most application code sequences,
however, use a high proportion of more complex,
longer-executing instructions and addressing modes, and

8284

SYSTEM
READY

1.5 BUS EXCHANGE MECHANISMS
The 8086 supports protocols for transferring control of
the local bus between itself and other devices capable of
acting as bus masters. The minimum mode configuration
offers a signal level handshake similar to the 8080 and
8085 systems. The maximum mode provides an enhanced
pulse sequence protocol designed to optimize utilization
of CPU pins while extending the system configurations to
two prioritized levels of alternate bus masters. These protocols are simply techniques for arbitration of control of
the CPU's local bus and should not be confused with the
need for arbitration of the system bus.

RDYl

AeN2
RDY2

1.5.1 Minimum Mode (HOLD/HLDA)

+5

Figure 1·90 Using RDY1/RDY2 to
Generate Ready

SYSTE~ ----.! RIi1

~~RDYl
~AEN2

r-

K
lKJ.

+5

therefore tend to be execution limited. In this case, less
BIU-EU interaction is required, the queue more often is
full, and more idle states occur on the bus.

8284

RDY2

-=

Figure 1·91 Using AEN1*/AEN2*
to Generate Ready

The minimum mode 8086 system uses a hold request input (HOLD) to the CPU and a hold acknowledge (HLDA)
output from the CPU. To gain control of the bus, a device
must assert HOLD to the CPU and wait for the HLDA
before driving the bus. When the 8086 can relinquish the
bus, it floats the RD*, WR *, INTA * and M/IO* command lines, the DEN* and DT/R* bus control lines and
the multiplexed address/data/status lines. The ALE signal
is not tri-stated. The CPU acknowledges the request with
HLDA to allow the requestor to take control of the bus.
The requestor must maintain the HOLD request active until it no longer requires the bus. The HOLD request to the
8086 directly affects the execution unit. The CPU will
continue to execute from its internal queue until either
more instructions are needed or an operand transfer is
required. This allows a high degree of overlap between
CPU and auxiliary bus master operation. When the re-

1·110

210912·001

8086/8088 CPU

I • I • I • I .. I " I " I " I " I " I " I " I " I " I • I " I

WIIlTt~~MO"Y

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L-_ _ _ _ _ _ _ _ _ _ _ _ _ _--'

FIRST
NfJ(T II lYlE
NUT II lYlE
NUT II FIIIST
,nt II ,YTt
lYlE

~

.. ,

L--------'E?~W1Dl- - --

o---------_I---·~··_--II_-----

Figure 1·92 Representative Instruction Execution Sequence
questor drops the HOLD signal, the 8086 will respond by
dropping HLDA. The CPU will not re-drive the bus,
command and control signals from tri-state until it needs
to perform a bus transfer. Since the 8086 may still be
executing from its internal queue when HOLD device is
driving the bus. To prevent the command lines from drifting below the minimum VIH level during the transition of
bus control, 22K ohm pull up resistors should be connected to the bus command lines. The timing diagram in
Figure 1-94 shows the handshake sequence and 8086 tim-

ASSEMBLY LANGUAGE MACHINE CODE
MOV AX, OF802H
PUSH AX
MOVCX, BX
MOVDX,CX
ADD AX, [SI]
ADD SI, 8086H
JMP$ -14

B802F8

50
8BCB
8BD1
0304
81C68680
EBFO

Figure 1·93 Instruction Loop Sequence

ing to sample HOLD, float the bus, and enable/disable
HLDA relative to the CPU clock.
To guarantee valid system operation, the designer must
assure that the requesting device does not assert control of
the bus prior to the 8086 relinquishing control and that the
device relinquishes control of the bus prior to the 8086
driving the bus. The HOLD request into the 8086 must be
stable THVCH ns prior to the CPU's low to high clock
transition. Since this input is not synchronized by the
CPU, signals driving the HOLD input should be synchronized with the CPU clock to guarantee the setup time is
not violated. Either clock edge may be used. The maximum delay between HLDA and the 8086 floating the bus
is TCLAZmax - TCLHAVmin - 70 ns. If the system cannot tolerate the 70 ns overlap, HLDA active from the 8086
should be delayed to the device. The minimum delay for
the CPU to drive the control bus from HOLD inactive is
THVCHmin + 3TCLCL = 635 ns and THVCHmin +
3TCLCL+ TCHCL= 701 ns to drive the multiplexed
bus. If the device does not satisfy these requirements,
HOLD inactive to the 8086 should be delayed. The delay
from HLDA inactive to driving the busses is TCLCL +
TCLCHmin-TCHAVmax= 158 ns for the control bus
and 2TCLCL - TCLHAVmax = 240 ns for the data bus.

1-111

210912·001

8086/8088 CPU

elK

HOLD

CONTROL

HlOA _ _ _ _..oJ

Figure 1·94 HOLD/HLDA Sequence Timing Diagram
LATENCY OF HLDA TO HOLD
The decision to respond to a HOLD request is made in the
bus interface unit. The major factors that influence the
decision are the current bus activity, the state of the
LOCK* signal internal to the CPU (d by the software
LOCK prefix) and interrupts.
If the LOCK* is not active, an interrupt acknowledge cycle is not in progress and the Bus Interface Unit (BIU) is
executing a T4 or T1 when the HOLD request is received,
the minimum latency to HLDA is:

35 ns
65 ns
200ns
IOns

THVCH min (Hold setup)
TCHCLmin
TCLCL (bus float delay)
TCLHAV min (HLDA delay)

310 ns

@5MHz

latency by four additional clocks plus N additional wait
states. With no wait states in the bus cycle, the maximum
would be 2.476 microseconds.
Although the minimum mode 8086 does not have a hardware LOCK* output, the software LOCK prefix may still
be included in the instruction stream. The CPU internally
reacts to the LOCK prefix as would the maximum mode
8086. Therefore, the LOCK does not allow a HOLD request to be honored until completion of the instruction
following the prefix. This allows an instruction which
performs more than one memory reference (example
ADD [BXJ, CX; which adds CX to [BX]) to execute without another bus master gaining control of the bus between
memory references. Since the LOCK signal is active for
once clock longer than the instruction execution, the maximumlatency to HLDA is:
34 ns
200ns
82 ns
(M+ 1)*200
200 ns
160 ns

The maximum delay under these conditions is:
34 ns
200 ns
82 ns
200 ns
160 ns
677 ns

(just missed setup time)
delay to next sample
TCHCLmax
TCLCL (bus float delay)
TCLHAV max (HLDA delay)
@5MHz

(M*200 ns) + 876 ns @ 5MHz

If the BIU just initiated a bus cycle when the HOLD request was received, the worst case response time is:
34 ns
82 ns
7*200
N*200
160 ns

THVC (just missed)
delay to next sample
TCHCLmax
ns LOCK instruction execution
set up HLDA (internal)
TCLHAV max (HLDA delay)

If the HOLD request is made at the beginning of an interrupt acknowledge sequence, the maximum latency to
HLDA is:

34 ns
82 ns
2600ns
160 ns

THVCH (just missed)
TCHCLmax
bus cycle execution
N wait stateslbus cycle
TCLHAV max (HLDA delay)

THVCH (just missed)
TCHCLmax
13 clock cycles for INTA
TCLHAVmax

2.876 microseconds @ 5 MHz

1.676 microseconds @ 5 MHz, no wait states
Note, the 200 ns delay for just missing is included in the
delay for bus cycle execution. If the operand transfer is a
word transfer to an odd byte boundary, two bus cycles are
executed to perform the transfer. The BIU will not acknowledge a HOLD request between the two bus cycles.
This type of transfer would extend the above maximum

MINIMUM MODE DMA CONFIGURATION
A typical use of the HOLD/HLDA signals in the minimum mode 8086 system is bus control exchange with
DMA devices like the Intel 8257-5 or 8237 DMA control-

1·112

210912-001

8086/8088 CPU

lers. Figure 1-95 illustrates a general interconnect for this
type of configuration using the 8237-2. The DMA controller resides on the upper half of the 8086 's local bus
and shares the A8-A15 demultiplexing address latch of
the 8086. All registers in the 8237-2 must be assigned odd
addresses to allow initialization and interrogation by the
CPU over the upper half of the data bus. The 8086
RD*/WR* commands must be demultiplexed to provide
separate 110 and memory commands which are compatible with the 8237-2 commands. The AEN control from
the 8237-2 must disable the 8086 commands from the
command bus, disable the address latches from the lower
(AO-A7) and upper (AI9-AI6) address bus and select the
8237-2 address strobe (ADSTB) to the A8-A15 address
latch. If the data bus is buffered, a pull-up resistor on the
DEN line will keep the buffers disabled. The DMA controller will only transfer bytes between memory and 1/0
and requires the 110 devices to reside on an 8-bit bus derived from the 16-bit to 8-bit bus multiplex circuit given
in Section 4. Address lines A7-AO are drive directly by
the 8237 and BHE* is generated by inverting AO. If
A19-A16 are used, they must be provided by an additional port with either a fixed value or initialized by software and enabled onto the address bus by AEN.
Figure 1-96 gives an interconnection for placing the 8257
on the system bus. By using a separate latch to hold the
upper address from the 8257-5 and connecting the outputs
to the address bus as shown, 16-bit DMA transfers are
provided. In this configuration, AEN simultaneously enables AO and BHE* to allow word transfers. AEN still
disables the CPU interface to the command and address
busses.

RO*/GT* TO HOLD/HLDA CONVERSION
Consider a circuit for translating a HOLD/HLDA handshake sequence into a RQ*/OT* pulse sequence (see Figures 1-97 and 1-98). After receiving the grant pulse, the
HLDA is enabled TCHCLmin ns before the CPU has
tri-stated the bus. If the requesting circuit drives the bus
within 20 ns of HLDA, it may be desirable to delay the
acknowledge one clock period. The HLDA is dropped not
later than one clock period after HOLD is disabled. The
HLDA also drops at the beginning of the release pulse to
provide 2TCLCL + TCLCH for the requestor to relinquish control of the status lines and 3TCLCL to float the
remaining signals.

1.5.2 Maximum Mode (RQ*/GT*)
The maximum mode 8086 configuration supports a significantly different protocol for transferring bus control.
When viewed with respect to the HOLD/HLDA sequence
of the minimum mode, the protocol appears difficult to
implement externally. However, it is necessary to understand the intent of the protocol and its purpose within the
system architecture.

The maximum mode RQ*/OT* sequence is intended to
transfer control of the CPU local bus between the CPU
and alternate bus masters which reside totally on the local
bus and share the complete CPU interface to the system
bus. The complete interface includes the address latches,
data transceivers, 8288 bus controller and 8289
multi-master bus arbiter. If the alternate bus masters in the
system do not reside directly on the 8086 local bus, system bus arbitration is required rather than local CPU bus
arbitration. To satisfy the need for multi-master system
bus arbitration at each CPU's system interface, the 8289
bus arbiter should be used rather than the CPU RQ*/OT*
logic.

RO*/GT* USAGE
The RQ*/OT* protocol was developed to allow up to two
instruction set extension processor (co-processors) or
other special function processors (like the 8089 110 processor in local mode) to reside directly on the 8086 local
bus. Each RQ* IOT* pin of the 8086 supports the full protocol for exchange of bus control. The sequence consists
of a request from the alternate bus master to gain control
of the system bus, a grant from the CPU to indicate the
bus has been relinquished and a release pulse from the
alternate master when done. The two RQ*/OT* pins
(RQ*/OTO* and RQ*/OTI *) are prioritized with
RQ*/OTO* having the highest priority. The prioritization
only occurs if requests have been received on both pins
before a response has been given to either. For example,
if a request is received on RQ* lOTI * followed by a request on RQ*/OTO* prior to a grant on RQ*/OTI *,
RQ* IOTO* will gain priority over RQ* lOTI *. However,
if RQ*/OTI * had already received a grant, a request on
RQ* IOTO* must wait until a release pulse is received on
RQ*/OTl*.
The requestl grant sequence interaction with the bus interface unit is similar to HOLD/HLDA. The CPU continues
to execute until a bus transfer for additional instructions
or data is required. If the release pulse is received before
the CPU needs the bus, it will not drive the bus until a
transfer is required.
Upon receipt of a request pulse, the 8086 floats the multiplexed address, data and status bus, the SO*, S1*, and S2 *
status lines, the LOCK* pin and RD*. This action does
not disable the 8288 command outputs from driving the
command bus and does not disable the address latches
from driving the address bus. The 8288 contains internal
pull-up resistors on the SO*, SI*, and S2* status lines to
maintain the passive state while the 8086 outputs are
tri-state. The passive state prevents the 8288 from initiating any commands or activating DEN to enable the transceivers buffering the data bus. If the device issuing the
RQ* does not use the 8288, it must disable the 8288 command outputs by disabling the 8288 AEN* input. Also,
address latches not used by the requesting device must be
disabled.

1·113

210912·001

8086/8088 CPU

Vee

T

DEMULTIPLEX
MIN MODE COMMANDS

r

t~

I

8284

I

L

I

RDIWRIIO/M
BHE
Ai." l'

8018
READY
CLK
RESET
HOLD

1

L

ALE
AD1S-D

HLDA

T
T

COMMAND
BUS

EIIAIU
8282

DO

01
STa

m

f----

'(

~

m

=

UPPER
OMA
AD DR -

00-

>c>-

01

-

8282

1/0 PORT
LOADED DURING
8237 INITIALIZATION

LOCAL DATA
BUS
8282
74LS74
Q
CLR
If-D

r-

01

~

DO

STa

-

AD7.----10
RESET

OSC

PClK

ClK

READY

Figure 1-109 8284A Clock GeneratorlDriver Block Diagram

Xl
24MHZ$
X2

CSYNC

~

.".

.".

FIe:

I

A.

I

Figure 1-111 Recommended Crystal
Clock Configuration

Figure 1-110 8086/88 Clock Waveform

+5

"lJ.X1X,
~

The oscillator output is inverted from the oscillator signal
used to drive the CPU clock generator circuit. Because of
this inversion, the oscillator output of one 8284A should
not drive the EFI input of a second 8284A if both are
driving clock inputs of separate CPU's that are to be synchronized. The variation on EFI to CLK delay over a
range of 8284A's may approach 35 to 45 ns. If, however,

1-127

EXTEANAl
FREQUENCY
SOUACE

F'~

14

ClK

EFI

1214

1

\I

ClK

-

Figure 1-112 8284A Interfaced to an 8086/88

210912·001

8086/8088 CPU

+5

14

lK

17

OSC

X,

C

~

8284

18
13

TO
CSYNC

EXTERNAL

SYNC-----I

INPUT

CONDITION
IiXTERNAl
FREQUENCY

X,

Fie

TO
L--------------EFI
INPUT

Figure 1-115 Synchronizing CSYNC With EFI
+5

Figure 1-113 External Frequency for
Multiple 8284's

all 8284A's are the same package type, have the same relative supply voltage and operate in the same temperative
environment, the variation will be reduced to between IS
and 25 ns.

8284A OUTPUTS

There are three frequency outputs from the 8284A, the
oscillator (OSC) mentioned above, the system clock
(CLK) which drives the CPU, and a peripheral clock
(PCLK) that runs at one half the CPU clock frequency
(see Figure 1-114). The oscillator output is only driven by
the crystal and is not affected by the F/C* strapping option. If a crystal is not connected to the 8284A when the
external frequency input is used, the oscillator output is
indeterminate. The CPU clock is derived from the selected frequency source by an internal divide by three
counter. The counter generates the 33 % duty cycle clock
which is optimum for the CPU at maximum frequency.
The peripheral clock has a 50 % duty cycle and is derived
from the CPU clock. The maximum skew is 20 ns between OSC and CLK, and 22 ns between CLK and
PCLK.

Since the state of the 8284A divide by three counter is
indeterminate at system initialization (power on), an external sync to the counter (CSYNC) provides synchronization of the CPU clock to an external event. When
CSYNC is brought high, the CLK and PCLK outputs are
forced high. When CSYNC returns low, the next positive
clock from the frequency source starts clock generation.
CSYNC must be active for a minimum of two periods of
the frequency source. If CSYNC is asynchronous to the
frequency source, use the circuit in Figure 1-115 for synchronization. The two latches minimize the probability of
a meta-stable state in the latch driving CSYNC. The
latches are clocked with the inverse of the frequency
source to guarantee the 8284A setup and hold time of
CSYNC to the frequency source (see Figure 1-116). If a
single 8284A is to be synchronized to an external event

EFI

CSVNC

J,
I

--l

I
I
I

I--TYHEH
-MAX IS SPEC'ED TO GUARANTEE MAX

aoee CLOCK FREQUENCY

Figure 1-116 CSYNC Setup and Hold to EFI

=
ClK

PClK~

~

Figure 1-114 Oscillator to ClK and ClK to PClK Timing Relationships
1-128

210912·001

8086/8088 CPU

+5
17

+5

X,

osc

100Q

12

elK

Cl

~

18

X,

8284

100Q

FIe
CSYNC elK 8

SYNC

100Q

Figure 1·117 EFI From 8284A Oscillator

Figure 1·119 Buffering the 8284 ClK Output

and an external frequency source is not used, the oscillator output of the 8284A may be used to synchronize
CSYNC (see Figure 1-117). Since the oscillator output is
inverted from the internal oscillator signal, the inverter in
the previous example is not required. If multiple 8284A's
are to be synchronized, an external frequency source
must drive all 8284A's and a single CSYNC synchronization circuit must drive the CSYNC input of all 8284A's
(see Figure 1-118). Since activation of CSYNC may
cause violation of CPU minimum clock low time, it
should only be enabled during reset or CPU clock high.
CSYNC must also be disabled a minimum of four CPU
clocks before the end of reset to guarantee proper CPU
reset.

input high Voltage) (see Figure 1-119). A single 8284A
should not be used to generate the CLK for multiple
CPU's that do not share a common local (mUltiplexed)
bus since the 8284A synchronizes ready to the CPU and
can only accommodate ready for single CPU. If multiple
CPU's share a local bus, they should be driven with the
same clock to optimize transfer of bus control. Under
these circumstances, only one CPU will be using the bus
for a particular bus cycle which allows sharing a common
READY signal (see Figure 1-120).

Due to the fast transitions and high drive (5 rnA) of the
8284A CLK output, it may be necessary to put a 10 to 100
ohm resistor in series with the clock line to eliminate ringing (resistor value depending on the amount of drive required). If multiple sources of CLK are needed with
minimum skew, CLK can be buffered by a high drive device (74S241) with outputs tied to 5 volts through 100
ohms to guarantee VOH = 3.9 min (8086 minimum clock

+.

THE 8284A RESET FUNCTION
The reset signal to the 8086 can be generated by the
8284A; the 8284A has a Schmitt trigger input (RES*) for
generating reset from a low active external reset. The hysteresis specified in the 8284A data sheet implies that at
least 0.25 volts will separate the 0 and 1 switching point
of the 8284A reset input. Inputs without hysteresis will
switch from low to high and high to low at approximately
the same voltage threshold. The inputs are guaranteed to
switch at specified low and high voltages (VIL and VIH)
but the actual switching point is anywhere in-between.
Since VIL min is specified at 0.8 volts, the hysteresis
guarantees that the reset will be active until the input

MULTIPlEX£D IUS

Figure 1·120 8086 and Coprocessor on the
local Bus Share
a Common 8284

Figure 1·118 Synchronizing Multiple 8284As
1-129

210912-001

8086/8088 CPU

reaches at least I. 05 volts. A reset will not be recognized
until the input drops at least 0.25 volts below the reset
inputs VIR of2.6 volts.

+V

RESETIN~

POWER UP RESET

±T":284

To guarantee reset from power up, the reset input must
remain below 1.05 volts for 50 microseconds after Vee has
reached the minimum supply voltage of 4.5 volts. The
hysteresis allows the reset input to be drive by a simple
RC circuit (see Figure 1-121). The calculated RC value
does not include time for the power supply to reach 4.5
volts or the charge accumulated during this interval.
Without the hysteresis, the reset output might oscillate as
the input voltage passes through the switching voltage of
the input. The calculated RC value provides the minimum
required reset period of 50 microseconds for 8284A's that
switch at the 1.05 volt level and a reset period of approximately 162 microseconds for 8284A's that switch at the
2.6 volt level. If tighter tolerance between the minimum
and maximum reset times is necessary, the reset circuit
shown in Figure 1-122 might be used rather than the simple RC circuit. This circuit provides a constant current
source and a 1.inear charge rate on the capacitor rather
than the inverse exponential charge rate of the RC circuit.
This implementation generates a maximum reset period
of 124 microseconds.

Yc

=

AC

= 188.10- 6

1.05

V

5

I

.'

MINIMUM RESET ACTIVE TIME
/ - - MAXIMUM RESET ACTIVE TIME

Figure 1·121 8284A Reset Circuit

Vee

0,
R, - DETERMINES CURRENT TO CHARGE C
Ra - VALUE NOT CRITICAL ::10K

0,

The 8284A synchronizes the reset input with the CPU
clock to generate the RESET signal to the CPU (see Figure 1-123). The output is also available as a general reset
to the entire system. The reset has no effect on any clock
circuits in the 8284A.

1.8.2 8288 Bus Controller

= 50 j.lsec
= 4.5

Ie = tfHARGE CURRENT = VbcCO,

R02 - Td

RESET
IF All SEMICONDUCTORS ARE SILICON. Ie.

¥

· l n f - - - - - < v e e - 08

The 8288 Bus Controller (Figure 1-124) uses the S2*,
SI * and SO* status bit outputs from the CPU (and the
8089 lOP) to generate all bus control and command output signals required for a bus cycle. The status bit outputs
are decoded as outlined in Table 1-43. For a detailed description of the operation of the 8288 Bus Controller, refer to the Microsystems Component Handbook (Intel
Order No. 230843-002).
The three status lines (SO*, S1*, S2 *) are defined to provide communications with the 8288 and 8289. The status
lines tell the 8288 when to initiate a bus cycle, what type
of command to issue and when to terminate the bus cycle.
The 8288 samples the status lines at the beginning of each
CPU clock (CLK). To initiate a bus cycle, the CPU drives
the status lines from the passive state (SO*, S 1*, S2 * 1)
to one of the seven possible command codes (see Table
1-43). This occurs on the rising edge of the clock during
T4 of the previous bus cycle or a TI (idle cycle, no current bus activity). The 8288 detects the status change by
sampling the status lines on the high to low transition of
each clock cycle. The 8288 starts a bus cycle by generat-

T

Figure 1·122 Constant Current Power
Up Reset Circuit

17
CJ

Y
+5

=

1-130

18
13

ClK

X,

SYSTEM
RESET

8

8284

11

X,
FIe

ClK

8086
RESET

10

21

RESET

'::-

11

liB

~
Figure 1·123 8086/88 Reset and System Reset
210912-001

8086/8088 CPU

5o~
8086 {
STATUS

5,--

52--

STATUS
DECODER

MRDC
- - . MWTC
COM·
MAND
SIGNAL
GENER·
ATOR

AMWC

10RC
lowe

1

I

MUL TlSUS ™

COMMAND
SIGNALS

Alowe
INTA

CONTROL
INPUT

{

ClK~

AEN CEN-

CONTROL
lOGIC

CONTROL
SIGNAL
GENER·
ATOR

+5V

GND

108--

DTiR
} ADDRESS lATCH, DATA
DEN
TRANSCEIVER, AND
MCE/PDEN INTERRUPT CONTROL
SIGNALS
ALE

Figure 1·124 8288 Bus Controller Block Diagram

ing ALE and appropriate buffer direction control of the
clock cycle immediately following detection of the status
change (T 1). The bus transceivers and the selected command are enabled in the next clock cycle (T2) (or T3 for
normal write commands). When the status returns to the
passive state, the 8288 will terminate the command (see
Figure 1-125). Since the CPU will not return the status to
the passive state until the 'ready' indication is received,
the 8288 maintains active command and bus control for
any number of wait cycles. The status lines may also be
used by other processors on the 8086's local bus to monitor bus activity and control the 8288 if they gain control
of the local bus.

and static RAMs. The normal write provides data setup
prior to write to accommodate dynamic RAM memories
and I/O devices which strobe data on the leading edge of
write. The advanced write commands do not guarantee
that data is valid prior to the leading edge of the command. The DEN signal in the maximum mode is inverted
from the minimum mode to extend transceiver control by
allowing logical conjunction of DEN with other signals.
While not appearing to be a significant benefit of interrupt
control and various system configurations will demonstrate the usefulness of qualifying DEN. Figure 1-126
compares the timing of the minimum and maximum mode
bus transfer commands. Although the maximum mode
configuration is designed for multiprocessor environments, large single CPU designs (either MULTIBUS systems or greater than two PC boards) should also use the
maximum mode. Since the 8288 is a bipolar dedicated
controller device, its output drive for the commands (32
rnA) and tolerances on A.C. characteristics (timing parameters and worse case delays) provide better large system performance than the minimum mode 8086.

The 8288 provides the bus control (DEN, DT/R*, ALE)
and commands (INTA*, MRDC*, IORC*, MWTC*,
AMWC*, IOWC*, AIOWC*) removed from the CPU.
The command structure has separate read and write commands for memory and I/O to provide compatibility with
the MULTIBUS command structure.
The advanced write commands are enabled one clock period earlier than the normal write to accommodate the
wider write pulse widths often required by peripherals
Table 1·43 Status Line Decode Chart

s; s, So
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

Processor State

0 InterrUQI Acknowledge
1 Read I/O Port
0 Write I/O Port
1 Halt
0 Code Access
1 Read Memory
0 Write Memory
1 Passive

8288Command
INTA
10RC
10WC,AIOWC
None

M'RoC
MRDC
MWTC,AMWC
None

In addition to assuming the functions removed from the
CPU, the 8288 provides additional strapping options and
controls to support multiprocessor configurations and peripheral devices on the CPU local bus. These capabilities
allow assigning resources (memory or I/O) as shared
(available on the MULTIBUS system bus) or private (accessible only by this CPU) to reduce contention for access
to the MULTIBUS system bus and improve multi-CPU
system performance. The following paragraphs describe
these strapping options.

1-131

210912-001

8086/8088 CPU

I

T,

I

T,

I

ClKf\J\J\.

GOES INACTIVE IN THE STATE

:~~ !=<~'.

\'----

READY

~\\~\\\

READY

9

WAIT

Figure 1·125 Status Line Activation And Termination

ClK (8284 OUTPUn

MN
MODE
8088

110 ns

TCVCTX TClMH

35

MX
MODE
8088

WITH

~ OR AIllWil

-----------hl

8288

Figure 1·126 Maximum and Minimum Mode Command Timing

1-132

210912-001

8086/8088 CPU

aoaeIlOIIIlOII
STATUS

PROCESSOR
CONTROL

\

BClK
INIT
BREQ
BPRN
BPRO

Ii

~

I

MUlTlBUSTM
COMMAND
SIGNALS

BUSY
CIRQ

lOCK
ClK
~
RESB
ANYRQST

1

iOa

AEN

I===~~~=~~~~;J- SYSB/IIED

} SYSTEM
SIGNALS

+5Y

Figure 1-127 8289 Bus Arbiter Block Diagram
I/O BUS MODE

Strapping the lOB pin HIGH puts the 8288 in the 110 Bus
mode of operation. In the 110 Bus mode all command
lines (lORC*, 10WC*, AIOWC*, INTA*) are always enabled and not dependent on AEN*. When an 110 command is issued by the processor, the 8288 immediately
activates the command lines using PDEN* and DT/R* to
control the 110 bus transceiver. In this configuration the
110 command lines should not be used to control the system bus because there is no arbitration present. In this
mode one 8288 can handle two external busses. No waiting is involved when the CPU wants to gain access to the
1/0 bus. Normal memory access requires a "Bus Ready"
signal (AEN* LOW) before it will proceed. The lOB
mode of operation is especially advantageous in a
multi-processor system where there are 110 or peripherals
are dedicated to only one processor.

SYSTEM BUS MODE

When the lOB pin is strapped LOW the 8288 is in the
System Bus Mode of operation. No commands are issued
in this mode until 115ns after the AEN* line is activated
(LOW). The System Bus Mode assumes arbitration logic
will inform the bus controller (on the AEN* line) when
the bus is free for use. Both memory and 110 commands
wait for arbitration. This mode is used when only one bus
exists. In this case, both 110 and memory are shared by
more than one processor.

The processor is unaware of the arbiter's existence and
issues commands as though it has exclusive use of the
system bus. If the processor does not have the use of the
multi-master system bus, the bus arbiter prevents the bus
controller, the data transceivers and the address latches
from accessing the system bus (i.e., all bus driver outputs
are forced into the high impedance state). Since the command was not issued, a transfer acknowledge (XACK)
will not be returned and the processor will enter into wait
states. Transfer acknowledges are signals returned from
the addressed resource to indicate to the processor that the
transfer is complete. This signal is typically used to control the ready inputs of the clock generator. The processor
will remain in a wait state until the bus arbiter acquires the
use of the multi-master system bus. At that time the bus
arbiter will allow the bus controller, the data transceivers
and the address latches to access the system bus. The
8089 uses the LOCK* output to guarantee exclusive access of a shared system bus for the duration of an instruction. LOCK* is software controlled and must be preceded
by the instruction requiring exclusive access with a one
byte "lock" prefix. When the lock prefix is decoded by
the EU, the EU informs the BIU to activate the LOCK*
output during the next clock signal. This signal remains
active until one clock cycle after the execution of the associated data transfer is concluded. Once the command has
been issued and a data transfer has taken place, a transfer
acknowledge (XACK) is returned to the processor. The
processor then completes its transfer cycle. In this way,
the arbiter serves to multiplex a processor (or bus master)
onto a multi-master system bus and avoid contention problems between bus masters.

1.8.3 8289 Bus Arbiter
The 8289 Bus Arbiter (see Figure 1-127) operates in conjunction with the 8288 Bus Controller to interface an
8086, 8088, or 8089 processor to a multi-master system
bus (the 8289 is used as a general bus arbitration unit).

Since there can be many bus masters on a multi-master
system bus, some means of resolving priority between bus
masters simutaneously requesting the bus must be provided. The 8289 provides several resolving techniques.
These techniques are based on a priority concept that at

1-133

210912·001

8086/8088 CPU

any given time one bus master will have priority over the
rest. Two of the techniques, parallel and serial priority
resolving techniques, are discussed in the following paragraphs.
The parallel priority resolving technique uses a separate
bus request line (BREQ*) for each arbiter on the
multi-master bus system (see Figure 1-128). Each
BREQ* line enters into a priority encoder which generates the binary address of the highest priority BREQ* line
which is active. The binary address is decoded by a decoder to select the corresponding BPRN* (Bus Priority
In) line to be returned to the highest priority requesting
arbiter. The arbiter receiving priority (BPRN* true) then
allows its associated bus master onto the multi-master system bus as soon as it becomes available. When one bus
arbiter gains priority over another arbiter it cannot immediately seize the bus, it must wait until the present bus
transaction is complete. Upon completing its transaction
the present bus occupant recognizes that it no longer has
priority and surrenders the bus by releasing BUSY*.
BUSY* is an active low "OR" tied signal line which goes
to every bus arbiter on the system bus. When BUSY*
goes inactive (high), the arbiter which presently has bus
priority (BPRN* true) then seizes the bus and pulls
BUSY* low to keep other arbiters off the bus. Refer to
Figure 1-129. Multi-master system bus transactions are
synchronized to the bus clock (BCLK). This allows the
parallel priority resolving circuits or any other priority
resolving scheme to settle.
The serial priority resolving technique eliminates the need
for the priority encoder-decoder. arrangement by
daisy-chaining the bus arbiters together, connecting the
higher priority bus arbiter's BPRO* (Bus Priority Out)
output to the BPRN* of the next lower priority. (See Figure 1-130).
There are two types of processors in the 8086 family - -an
I/O processor (the 8089 lOP) and a non-I/O processor
(the 8086 and 8088 CPU's). Consequently, there are two
basic operating modes in the 8289 Bus Arbiter. One, the
I/O Peripheral Bus (lOB) mode, permits the processor access to both an I/O peripheral bus and a multi-master system bus. The second, the Resident Bus (RESB) mode,
permits the processor to communicate over both a resident bus and a multi-master system bus. Even though.it is
intended for the arbiter to be configured in the lOB mode
when interfacing to an I/O processor and for it to be in the
RESB mode when interfacing to a non-I/O processor, it is
quite possible for the reverse to be true. That is, it is possible for a non-I/O processor to have access to an I/O
peripheral bus or for an I/O processor to have access to a
resident bus as well as access to a multi-master system
bus. The lOB strapping option configures the 8289 Bus
Arbiter into the lOB mode and RESB strapping optires it
into the resident bus mode. If both strapping options are
strapped false, a third mode of operation is created, the
single bus mode, in which the arbiter interfaces. the processor to a multi-master system .bus only. See Figure

1-131. With both options strapped true, the arbiter interfaces the processor to a multi-master system bus, a resident bus and an I/O bus.

1.8.4 8259A Programmable Interrupt
Controller
The 8259A is a programmable interrupt controller (PIC)
designed to accommodate the INTA * protocol of maskable hardware interrupts. This component is programmable to operate in both 8080/8085 systems and 8086
systems. The 8259A manages eight levels of interrupts
and has built-in features for expansion. The devices are
cascadable in master/slave arrangements to allow up to 64
interrupt levels in the system with additional 8259A's.
Figures 1-132 and 1-133 are examples of 8259 A's in minimum and maximum mode 8086 systems. The minimum
mode configuration (a) shows an 8259A connected to the
CPU's multiplexed bus. Configuration (b) illustrates an
8259A connected to a demultiplexed bus system. These
interconnects are also applicable to maximum mode systems. The configuration given for a maximum mode system shows a master 8259A on the CPU's multiplexed bus
witave 8259A's out on the buffered system bus. This configuration demonstrates several unique features of the
maximum mode system interface. If the master 8259A
receives interrupts from a mix of slave 8259A's and regular idevices, the slaves must provide the type number for
devices connected to them while the master provides the
type number for devices directly attached to its interrupt
inputs. The master 8259A is programmable to determine
if an interrupt is from a direct input or a slave 8259A and
will use this information to enable or disable the data bus
transceivers (via the NAND function of DEN and EN*).
If the master must provide the type number, it will disable
the data bus transceivers. If the slave provides the type
number, the master will enable the data bus transceivers.
The EN* output is normally high to allow the 8086/8288
to control the bus transceivers. To select the proper slave
when servicing a slave interrupt, the master must provide
a cascade address to the slave. If the 8288 is not strapped
in the I/O bus mode (the 8288 lOB input connected to
ground), the MCE/PDEN* output becomes a MCE or
Master Cascade Enable output. This signal is only active
during INTA * cycles (see Figure 1-134) and enables the
master 8259A's cascade address onto the 8086's local bus
during ALE. This allows the address latches to capture
the cascade address with ALE and allows use of the dress
bus for selecting the proper slave 8259A. The MCE is
gated with LOCK* to minimize local bus contention between the 8086 tri-stating its bus outputs and the cascade
address being enabled onto .the bus. The first INTA * bus
cycle allows the master to resolve internal priorities and
output a cascade address to be transmitted to the slaves on
the subsequent INTA* bus cycle.

1-134

210912·001

8086/8088 CPU

74148
PRIORITY
ENCODER

74138

3TOB
DECODER

Figure 1-128 Resolving Technique

The following paragraphs provide a more detailed description of interrupt vectoring, the interrupt priority
scheme, the edge and level triggering modes and interrupt
cascading. For additional information on the 8259A, refer
to Intel Application Note AP-59.

MCS-86/88 mode of operation to insure correct interrupt
vectoring when used in an 8086/8088 system.
When programmed in the MCS-86/88 mode, the 8259A
should only be used with an MCS-86 or MCS-88 system.
In this mode, the 8086/8088 will handle interrupts in the
format described in the 8259A - 8086/8088 Overview.

INTERRUPT VECTORING

Each IR input of the 8259A has an individual interrupt
vector address in memory associated with it. Designation
of each address depends upon the initial programming of
the 8259A. The 8259A must be programmed in the

I

Upon interrupt in the MCS-86/88 mode, the 8259A will
output a single interrupt-vector byte to the data bus. This
is in response to only two INTA * pulses issued by the
8086/8088 after the 8259A has raised INT high.

3

HIGHER PRIORITY 8US ARBITER REQUESTS THE MUlTI·MASTER SYSTEM BUS.
ATTAINS PRIORITY.
LOWER PRIORITY BUS ARBITER RELEASES BUSY.

4

HIGHER PRIORITY BUS ARBITER THEN ACQUIRES THE BUS AND PULLS BUSY DOWN.

Figure 1-129 Higher Priority Arbiter Obtaining the Bus from a Lower Priority Arbiter
1-135

210912-001

8086/8088 CPU

rupt vector byte are user definable. The lower 3 bits are
automatically inserted by the 8259A depending on the IR
level.
Contents of the interrupt-vector byte for 8086/8088 type
selection is put on the data bus during the second INTA *
pulse and shown in Figure 1-135.

INTERRUPT PRIORITIES
CaRQ:

A variety of modes and commands are available for controlling the interrupt varieties of the 8259A. All of them
are programmable, i.e., they may be changed dynamically under software control. With these modes and commands, many possibilities are conceivable, giving the
user enough versatility for almost any interrupt controlled
application.

: BUSY

THE NUMBER OF ARBITERS THAT MAY 8E DAISY·CHAINED TOGETHER IN THE
SERIAL PRIORITY RESOLVING SCHEME IS A FUNCTION OF BCLK AND THE PROPA·
GATION DELAY FADM ARBITER TO ARBITER. NORMALLY, AT 10 MHz ONLY 3 AR81·
TEFl MAY BE DAISY-CHAINED.

Figure 1·130 Serial Priority Resolving.
Fully Nested Mode

The first INTA * pulse is used only for set-up purposes
internal to the 8259A. As in the MCS-80/85 mode, this
setup includes priority resolution and cascade mode operations which will be covered later. Unlike the MCS-80/85
mode, no CALL opcode is placed on the data bus.

The fully nested mode is a general purpose priority mode.
This mode supports a multilevel-interrupt structure in
which priority order of all eight IR inputs are arranged
from highest to lowest.

The second INTA * pulse is used to enable the single
interrupt-vector byte to select one of 256 interrupt
"types" in the 8086/8088 memory. Interrupt type selection for all eight IR levels is made when initially programming the 8259A. However, reference to only one interrupt
is needed for programming. The upper 5 bits of the inter-

Unless otherwise programmed, the fully nested mode is
entered by default upon initialization. At this time, IRO is
assigned the highest priority through IR7 the lowest. The
fully nested mode, however, is not confined to this IR
structure alone. Once past initialization, other IR inputs
can be assigned highest priority also, keeping the

-

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ XACK MULnM"'$TEA SVSTEM BUS

f-"---'"

I============v ~~:~:NO

MULTJ.MASTHI
MULTI·MASTER
SYSTEM BUS

MULTI·MASTER

~==~~=========:>SVSTEM
."

ADDRESS

Figure 1·131 Typical Medium Complexity CPU Circuit

1·136

210912-001

8086/8088 CPU

1-----'-----'--'----'--'---.... \

ADDRESS

1J1--------"""----""---.... \

DATA

I-__-,____,-~---r,---,;BUS

1\,---------------,/ BUS
a.

b.

Figure 1-132 Min Mode 8086 with Master 8259A on the Local Bus and Slave 8259A's
on the System Bus

multilevel-interrupt structure of the fully nested mode.
Figure 1-136 shows some variations of the priority structures in the fully nested mode.
In general, when an interrupt is acknowledged, the highest priority request is determined from the IRR (Interrupt
Request Register). The interrupt vector is then placed on
the data bus. In addition, the corresponding bit in the ISR
(In-Service Register) is set to designate the routine in
service. This ISR bit remains set until an EOI
(End-Of-Interrupt) command is issued to the 8259A.
EOI's will be explained in greater detail shortly.
In the fully nested mode, while an ISR bit is set, all further requests of the same or lower priority are inhibited
from generating an interrupt to the microprocessor. A

higher priority request, though, can generate an interrupt,
thus vectoring program execution to its service routine.
Interrupts are only acknowledged, however, if the microprocessor has previously executed an"Enable Interrupts"
instruction. This is because the interrupt request pin on
the microprocessor gets disabled automatically after acknowledgement of any interrupt. The assembly language
instruction used to enable interrupts is "ST!". Interrupts
can be disable by using the instruction "eLi". When a
routine is completed a "return" instruction "IRET" is
executed.
A single 8259A is essentially always in the fully nested
mode unless certain programming conditions disturb it.

1-137

210912-001

8086/8088 CPU

ADDRESS
r-~-----r------'-r-------'-r------,/BUS

I/L---------------"'''---------'''''------...... '\ DATA
~-------------------------------,/BUS

Figure 1·133 Max Mode 8086 with Master 8259A on the Local Bus and Slave 8259A's
on the System Bus

The following programming conditions can cause the
8259A to go out of the high to low priority structure of the
fully nested mode.
•

•

The special mask mode

•

A slave with a master not in the special fully nested
mode

The automatic Eor mode

T,

I

T2

T3

T..

TI

I

------'n'----_
TI

T,

T,

T,

A L E J \_ _ _

\1....-_ _ _ _----11

FLOAT

Figure 1·134 MCE Timing to Gate 8259A CAS Address onto the 8086 Local Bus

1-138

210912-001

8086/8088 CPU

IR
7
6
5
4

3
2
1

a

command, it resets the highest priority ISR bit. This confirms to the 8259 A that the highest priority routine of the
routines in service is finished.

07 06 05 04 03 02 01 00
T7
T7
T7
T7
T7
T7
T7
T7

T6
T6
T6
T6
T6
T6
T6
T6

T5
T5
T5
T5
T5
T5
T5
T5

T4
T4
T4
T4
T4
14
T4
T4

T3
T3
T3
T3
T3
T3
T3
T3

1
1
1
1

a
a
a
a

1
1

1

a
a 1
a a
1
1
1
a
a 1
a a

b. Specific EOI Command

Figure 1-135 Interrupt Vector Byte
Additional details on these interrupt modes can be
found in Intel Application Note AP-59. These modes
are mentioned here so that the designer will be aware
of them. As long as these program conditions are not
enacted, the fully nested mode remains undisturbed.

A specific EOI command is sent from the microprocessor
to let the 8259A know when a service routine of a particular interrupt level is completed. Unlike the non-specific
EOI command which automatically resets the highest priority ISR bit, a specific EOI command specifies an exact
ISR bit to be reset. One of the eight IR levels of the 8259A
can be specified in this command. The purpose of the
specific EO! command is to reset the ISR bit of a completed service routine whenever the 8259 A cannot automatically determine the completion.

End of Interrupt (EOI)

c. Automatic EOI Mode

Upon completion of an interrupt service the 8259A must
be informed so that its ISR can be updated. This is done to
keep track of which interrupt levels are in the process of
being serviced and their relative priorities. Three different End-Of-Interrupt (EO!) formats are available to the
designer. These are: 1) non-specific EO! command; 2)
specific EOI command; and, 3) automatic EOI command.
Selection of which EOI to use is dependent on the interrupt operation the designer wishes to perform.

When programmed in the automatic EOI mode the microprocessor does not need to issue a command to notify the
8259A of a completed interrupt routine. The 8259A accomplishes this by performing a non-specific EOI automatically at the trailing edge of the last INTA * pulse
(second pulse). The advantage of automatic EOI over the
other EOI commands is that no command has to be issued. This simplifies programming and lowers code requirements within interrupt routines. However, special
consideration must be taken when deciding to use the automatic EO! mode because it disturbs the fully nested
mode.

a. Non-Specific EOI Command
The microprocessor sends a non-specific EOI command
to let the 8259A know when a service routine has been
completed. This command does not specify the the exact
interrupt level. The 8259 A automatically determines the
interrupt level and resets the correct bit in the ISR.
To use the non-specific EO! command the 8259A must be
in a mode of operation where it can predetermine
in-service routine levels. For this reason the non-specific
EOI command should only be used when the most recent
level acknowledged and serviced is always the highest priority level. When the 8259A receives a non-specific EO!

IR LEVELS rr=IR6 J R5 lR4 IR3_IR2 IR1 IRO
PRIORITY
7 ---.L_L_~ __ ~ ___1 0
A
IR LEVELS
PRIORITY

1R7 IRG IRS IR4 IR3 IR2 IR1 IRO
4. '3
2·' 1 a 7 6 5

IR LEVELS
PRIORITY

IR7 IRG IRS IR4 IR3 IR2 I 1 IRO
1 ~L_7_6___
5 _4_3 2
C

Figure 1-136 Priority Structure VariationsFully Nested Mode

Automatic Rotation - Equal Priority
Automatic rotation of priorities is used in applications
where interrupting devices are of equal priority, such as
communications channels. The concept is that once a peripheral is serviced, all other equal priority peripherals
should be given a chance to be serviced before the original peripheral is serviced again. This is accomplished by
automatically assigning a peripheral the lowest priority
after it has been serviced. Therefore, worst case, the device would have to wait until all other devices have been
serviced before being serviced again.
There are two methods of accomplishing automatic rotation. One is the "rotate on non-specific EO! command"
which is used with the non-specific EOI command. The
other is the "rotate in automatic EOI mode" which is used
with the automatic EOI mode.

a. Rotate On Non-Specific EOI Command
When the rotate on non-specific EOI command is issued,
the highest ISR bit is reset as in a normal non-specific
EO! command. However, after the ISR bit is reset the
1-139

210912'()01

8086/8088 CPU

corresponding IR level is assigned the lowest priority.
Other IR priorities rotate to confonn to the fully nested
mode based on the newly assigned low priority.

b. Rotate On Automatic EOI Mode

gered mode and the level triggered mode to allow the user
the capability of either method. Selection of one of these
methods is done during the programmed initialization of
the 82S9A.

Level Triggered Mode

The rotate in automatic EOI mode operates similar to the
non-specific EO! command. The main difference is that
priority is done automatically after the last INTA * pulse
of an interrupt request. Th enter or exit this mode a
rotate-in-automatic-EOI set command and a
rotate-in-automatic-EOI clear command is provided. After these two commands, no other commands are needed,
as in the automatic EOI mode. However, when using any
fonn of the automatic EO! mode, special consideration
since the guideline for the automatic EO! mode also
stands for the rotate in automatic EO! mode.

Specific Rotation - Specific Priority
The specific rotation mode provides the designer with
versatile capabilities in interrupt controlled operations.
This priority mode is very useful in applications where a
specific device's interrupt priority must be altered. Unlike
automatic rotation, which automatically sets priorities,
specific rotation is completely user controlled. The user
selects which interrupt level is to receive lowest or highest
priority. This can be done during the main program or
within interrupt routines. Two specific rotation commands are available to the user, the "set priority command" and the "rotate on specific EOI command".

a. Set Priority Command

The set priority command allows the programmer to assign an IR level to the lowest priority. All other interrupt
levels will confonn to the fully nested mode based on the
newly assigned low priority.

b. Rotate On Specific EOI Command

The rotate on specific EOI command is a combination of
the set priority and the specific EO! command. As in the
set priority command, a specified IR level is assigned
lowest priority. As in the specific EOI command, a specified level will be reset in the ISR. Therefore, the rotate on
specific EOI command accomplishes both tasks in only
one command.

When the 82S9A is in the level triggered mode it will
recognize any active (high) level on the IR input as an
interrupt request. If the IR input remains active after an
EOI command has been issued, resetting its ISR bit, another interrupt will be generated. This assumes the processor INT pin is enabled. Unless repetitious interrupt
generation is desired, The IR input must be brought to an
inactive state before an EOI command is issued in its
service routine. However, necessary timing requirements
must be obeyed (see Figure 1-137). Note that the request
on the IR line must remain until after the falling edge of
the first INTA>I< pulse. On any IR input, if the request goes
inactive before the first INTA>I< pulse, the 82S9A will respond as if IR7 was active. In any design where there is a
possibility of this happening, the IR7 default feature can
be used as a safeguard. This can be accomplished by using the IR7 routine as a "cleanup routine" which might
check the 82S9A status or merely return program executi
to its pre-interrupt location.

Edge 1l'lggered Mode
In the edge triggered mode the 82S9A will only recognize
interrupts if generated by an inactive (low) to active (high)
transition on the IR input. The edge triggered mode incorporates an edge lockout method of operation. This means
that after the rising edge of an interrupt request and the
acknowledge of the request, the positive level of the IR
input will not generate further interrupts on this level. The
user does not neeto worry about quickly removing the request to avoid generating further interrupts. Before another interrupt can be generated the IR input must return
to the inactive state.

Timing requirements for the edge triggered mode are
shown Figure 1-137. As in the level triggered mode, the
request on the IR input must remain active until after the
falling edge of the first INTA>I< pulse in the edge triggered
mode. Unlike the level triggered mode, after the interrupt
request is acknowledged its IRR latch is disarmed. Only
after the IR input goes inactive will the IRR latch again
become armed making it ready to receive another interrupt request (in the level triggered mode the IR latch is
always armed). Note that the IR7 default discussed in the
level triggered mode also works in the edge triggered
mode.

INTERRUPT TRIGGERING
INTERRUPT CASCADING
There are two basic ways of sensing an active interrupt
request. One is a level sensitive input and the other is an
edge sensitive input. The 82S9A provides the edge trig-

More than one 82S9A can be used to expand the priority
interrupt scheme to up to 64 levels without additional

1·140

210912'()01

8086/8088 CPU

IR

-+-..J

INT _ _ _ _ _

INTA--------~------------,

LATCH"

EARLIEST IR
CAN BE REMOVED

ARMED

LATCH"
ARMED

"EDGE TRIGGERED MODE ONLY

Figure 1·137 IR Triggering Timing Requirements
1-138 shows a typical system containing a master and two
slaves, providing 22 interrupt levels. Note that the master
is designated by a high on the SP*/EN* pin, while the
SP*/EN* pins on the slaves are grounded (this can also be
done by software, see the buffered mode). Also the INT
output pin of each slave is connected to the an IR input pin
on the master. The CASO-2 pins on all 8259A's are paralleled. These pins, which act as outputs when the 8259A is
a master and inputs for the slaves, serve as a private
8259A bus. They control which slave has control of the
system bus for interrupt vectoring operation with the
processor. All other pins are connected as in normal operation (each receives an INTA pulse).

hardware. This method for expanded interrupt capability
is called cascading. The 8259A supports cascading operations with the cascade mode. Additionally, the specially
fully nested mode and the buffered mode are available for
increased flexibility when cascading 8259A's under certain applications.

Cascade Mode
In the cascade mode, basic operation consists of one
8259A acting as a master to the others which are acting as
slaves. A specific hardware set-up is required to establish
operation in the cascade mode (see Figure 1-138). Figure

ADDRESSBUSl161

CONTROL BUS

tNT REa

\

DATA BUS (81

--

- .- ---

--

-

--

--+--

-

'0

cs

•

I

•

f-- t--

r- j -

5

4

5

4

CAS 1

!-

CAS2

!-

,

2

,r

r ,r r
2

I-

,

0

0

r---;,

'0

CS

INT

INTA

CASO

Jo 1 1 1 r
7

f-- t--

-- - - t-

r-

DO·'

B259A
SLAVE A

m!1if7

---

t-

DO·'

6

5

4

oro r r 1 1
7

•

CASO

CASO
8259A
SLAVE B

m!1if 7

cs

INT

INfA

5

4

I

,

CAS 1

CAS 1

,

CAS 2

2

!!!

0

DO·'

7
[NTA

INT

B259A
MASTER

CAS2

mm M7 M6

0

1

'0

I

MS M4 M3 M2 Ml MO

LL1.1 1 ),11
6

4

1
0

I

INTEARUPT AEoueSTS

Figure 1·138 Cascaded 8259A's 22 Interrupt Levels
1·141

210912·001

8086/8088 CPU

In addition to the hardware set-up requirements, all
8259A's must be software programmed to work in the cascade mode. Programming the cascade mode is done during the initialization of each 8259A. The 8259A that is
selected as master must receive specification during its
initialization as to which of its IR inputs are connected to
a slave's INT pin. Each slave must be designated during its
initialization with an ID (0 -7) corresponding to which of
the master's IR inputs its INT pin is connected to. This is
necessary so the master's CASO-2 pins will be able to address each individual slave. Note that as in normal operation' each 8259A must also be initialized to give its IR
inputs a unique interrupt vector.

output is enabled, its SP*/EN* pin will go low. This signal can be used to enable data transfer through a buffer
transceiver in the required direction.
A conceptual diagram of three 8259A's in cascade is show
in Figure 1-139. Each slave is controlling an individual
8286 8-bit bidirectional bus driver by means of the buffered mode. Note the pull-up on the SP*/EN* line. This
pull-up is used to enable data transfer to the 8259A for its
initial programming. When data transfer is to go from the
8259A to the processor, SP*/EN* will go low, otherwise
it will be high.

1.8.5 8237A Programmable DMA
Controller

Specially Fully Nested Mode
Depending on the application, changes in the nested
structure of the cascade mode may be desired. This is
because the nested structure of a slave 8259 A differs from
that of the normal fully nested mode. In the cascade
mode, if a slave receives a higher priority interrupt request than the one in service (through the same slave), it
will not be recognized by the master. This is because the
master's ISR bit is set, ignoring all requests of equal or
lower priority. In this case, the higher priority slave interrupt will not be serviced until after the master's ISR bit is
reset by an EO! command. This will normally be after
completion of the lower priority routine.
If the user wishes to have a truly fully nested structure
within a slave 8259A, the specially fully nested mode
should be used. The specially fully nested mode is programmed in the master only. This is done the master's
initialization. In this mode the master will ignore only
those interrupt requests of lower priority than the set ISR
bit and will respond to all requests of equal or higher priority. Therefore, if a slave receives a higher priority request than the one in service, it will be recognized. To
ensure proper interrupt operation when using the special
fully nested mode, the software must determine if any
other slave interrupts are still in service before issuing an
EOI command to the master. This done by resetting the
appropriate slave ISR bit with an EO! and then reading it's
ISR. If the ISR contains all zeros, there aren't any other
interrupts from the slave in service and an EOI command
can be sent to the master. If the ISR isn't all zeros, an EO!
command should not be sent to the master. Clearing the
master's ISR bit with an EOI command while there are
still slave interrupts in service would allow lower priority
interrupts to be recognized at the master.

When configured in minimum mode, the 8086 and 8088
provide HOLD (hold) and HLDA (hold acknowledge) signals that are compatible with the 8237 A DMA controller.
The 8237 A can request use of the bus for direct transfer
of data between an I/O device and memory by activating
HOLD. The CPU will complete the current bus cycle, if
one is in progress, and the issue HLDA, granting the bus
to the DMA controller. The CPU will not attempt to use
the bus until HOLD goes inactive.
The 8086 addresses memory that is physically organized
in two separate banks, one containing even-addressed
bytes and one containing odd-addressed bytes. An 8-bit
DMA controller must alternately select these banks to access logically adjacent bytes in memory. Used as a maximum mode DMA controller, the 8089 provides a simple
way to interface a high-speed 8-bit device to an
8086-based system (refer to Chapter 4).
The 8237A Multimode Direct Memory Access (DMA)
Controller (see Figure 1-140) is a peripheral interface circuit designed to improve system performance by allowing
external devices to directly transfer information from the
system memory. Memory-to-memory transfer capability
is also provided. The 8237 A offers a wide variety of programmable control features to enhance data throughput
and system optimization and to allow dynamic reconfiguration under program control. The 8237 A is designed
to be used in conjunction with an external 8-bit address
register such as the 8282. It contains four independent
channels and may be expanded to any number of channels
by cascading additional controller chips. The three basic
transfer modes allow programmability of the types of
DMA service by the user. Each channel can be individually programmed to Autoinitialize to its original condition
following an End of Process (EOP).

Buffered Mode
DMA OPERATION
The buffered mode is useful in large systems where buffering is required on the data bus. Although not limited to
cascading, the buffered mode is most pertinent for this
use. In the buffered mode, whenever the 8259A's data bus

The 8237 A operates in two major cycles, the Idle cycle
and the Active cycle. Both device cycles are made up of
several states. The 8237 A can assume seven different

1-142

210912-001

8086/8088 CPU

SLAVE
8259A

MASTER
8259A

SLAVE
8259A

INT

INTR

Figure 1-139 Cascade-Buffered Mode Example

states, each composed of one or more complete clock cycles. State I (SI) is the inactive state. This state is entered
when the 8237A has no valid DMA requests pending. In
the SI state, the DMA controller is inactive, but may be in
the Program Condition, being programmed by the processor. State SO (SO) is the first state of a DMA service. At
this point the 8237A has requested a hold, but the processor has not yet returned an acknowledge. The 8237 may
still be programmed until it receives HLDA from the

CPU. An acknowledge from the CPU signals that DMA
transfers can begin. S 1, S2, S3 and S4 are working the
states of the DMA service. If more time is needed to complete a transfer than is available with normal timing, wait
states (SW) can be inserted between S2 or S3 and S4 by
use of the Ready line on the 8237A. Note that the data
transferred directly from the I/O device-to-memory (or
visa versa) with IOR* and MEMW* (or MEMR* and
IOW*) being active at the same time. The data is not read

.".
RESET

READY
CLOCK

•••

"DSTB

.......
ilili

;ow

DREOOOREQ3

HRQ

DACKOOACK3

Figure 1-140 8237A DMA Controller Block Diagram
1-143

210912·001

8086/8088 CPU

into or driven out of the 8237A in lIO-to-memory or
memory-to-llb DMA transfers.
Memory-to-memory transfers require a read-from and a
write-to-memory to complete each transfer. The states.
which resemble the normal working states, use two digit
numbers for identification. Eight states are required for a
single transfer. The first four states (SII, S12, S13, S14)
are used for the read-from-memory half and the last four
states (S21, S22, S23, S24) for the write-to-memory half
of the transfer.

lowing each transfer. When the word count "rolls over"
from zero to FFFFH, a Thrminal Count (TC) will cause
an Autoinitialization if the channel has been programmed
to do so.
DREQ must be held active until DACK becomes active in
order to be recognized. If DREQ is held active throughout
the single transfer, HRQ will go inactive and release the
bus to the system. HRQ will again go active and another
single transfer will occur upon receipt of a new HLDA.
This ensures one full machine cycle execution between
DMA transfers.

Idle Cycle

b. Block Transfer Mode

When no channel is requesting service, the 8237A will
enter the Idle cycle and perform SI states. In this cycle the
8237A will sample the DREQ lines every clock cycle to
determine if any channel is requesting a DMA service.
The device will also sample CS*, looking for an attempt
by the microprocessor to write or read the internal registers. When CS* is low and HLDA is low, the 8237 A enters the Program condition. The CPU can now establish,
change or inspect the internal definition of the part by
reading from or writing to the internal registers. Address
lines AO-A3 are inputs to the device and select which registers will be read or written. The lOR * and 10W* lines
are used to select and time reads or writes. An internal
flip-flop is used to generate an additional bit of address
due to the number and size of the internal registers. This
bit is used to determine the upper or lower byte of the
16-bit Address and Word Count registers. The flip-flop is
reset by Master Clear or Reset. A separate software command can also reset this flip-flop.

In the Block Transfer Mode the device is activated by
DREQ to continue making transfers during service until a
TC, caused by word count going to FFFFH, or an external
End of Process (EOP*) is encountered. DREQ should be
held active until DACK becomes active. Autoinitialization
will occur at the end of the service if the channel is preprogrammed for it.

Special software commands can be executed by the
8237A in the Program Condition. These commands are
decoded as sets of addresses with the CS* and 10W*. The
commands do not make use of the data bus. Instructions
include Clear First/Last Flip-Flop and Master Clear.

c. Demand Transfer Mode
In this mode the device is programmed to continue making transfers until a TC of external EOP* is encountered,
or until DREQ goes inactive. Therefore, transfers may
continue until the lIO device has exhausted its data capacity. After the 1/0 device has had a chance to catch up, the
DMA service is re-established by means of a DREQ.
During the time between services when the microprocessor is allowed to operate, the intermediate values of address and word count are stored in the 8237A Current
Address and Current Word Count registers. Only EOP*
can cause an Autoinitialize at the end of the service.
EOP* is generated by TC or by an external signal.
d. Cascade Mode

a. Single Transfer Mode

This mode is used to cascade more than one 8237A together for simple system expansion. The HRQ and HLDA
signals from the additional 8237A are connected to the
DREQ and DACK signals of a channel of the initial
8237A. This allow the DMA requests of the additional
device to propagate through the priority network circuits
of the preceding device. The priority chain is preserved
and the new device must wait for its turn to acknowledge
requests. Since the cascade channel of the initial 8237 A is
used only for prioritizing the additional device, it does not
output any address or control signals of its own. The
8237A will respond to DREQ and DACK but all other
outputs except HRQ will be disabled.

In the Single Transfer mode the 8237 A is programmed to
make one transfer only. The word count will be decremented and the address decremented of incremented fol-

Two additional 8237A devices cascaded into an initial device using two of the previous channels are shown in Figure F14L This forms a two level DMA system. More

Active Cycle

When the 8237A is in the Idle cycle and a non-masked
channel requests a DMA service, the device will output
an HRQ to the microprocessor and enter the Active cycle.
In this cycle the DMA service will take place. The DMA
service takes place in one of four modes: 1) single transfer mode; 2) block transfer mode; 3) demand transfer
mode; and 4) cascade mode.

1-144

210912-001

8086/8088 CPU

Temporary register to memory using the address in its
Current Address register and incrementing or decrementing it in the normal manner. The channel 1 Current Count
is decremented. When the word count of the channel goes
to FFFFH, a TC is generated causing an EOP* output
terminating the service. To allow a single word to be written to a block of memory Channel 0 may be programmed
to retain the same address for all transfers.

2ND LEVEL

8237A

1ST lEVEL

MICROPROCESSOR

1f-----

HRQ

DREQ

1-

HRa

DACK

I---

HL.DA

I--

HRa

DREa

~

HlDA

DACK

HlDA

8237A

INITIAL DEVICE

The 8237 A will respond to external EOP* signals during
memory-to-memory transfers. Data comparators in block
schemes may use this input to terminate the service when
a match is found. Memory-to-memory operations can be
detected as an active AEN with no DACK outputs.

8237A

ADDITIONAL

DMA REGISTERS

DEVICES

Figure 1-141 Cascaded 8237As

8237As could be added at the second level by using the
remaining channels of the first level. Additional devices
can also be added by cascading into the channels of the
second level devices, forming a third level.

The 8237A contains 344 bits of internal memory in the
form of registers. Table 1-44 lists the registers by name
and shows the size of each. The following paragraphs provide a detailed description of each register and their functions.

Current Address Register

TRANSFER TYPES

Each of the three active transfer modes can perform three
different types of transfers. These are Read, Write, and
Verify. Write transfers move data from an 110 device to
the memory by activating MEMW* and lOR *. Read
transfers move data from memory to an 110 device by
activating MEMR * and 10W*. Verify transfers are
pseudo transfers. The 8237 A operates as in Read or Write
transfers generating addresses, and responding to EOp,
however, the memory and 1/0 control lines all remain inactive. Verify mode is not permitted during memory to
memory operation.

Each channel has a 16-bit Current Address register. This
register holds the value of the address used during DMA
transfers. The address is automatically incremented or decremented after each transfer and the intermediate values
of the address are stored in the Current Address register
during the transfer. This register is written or read by the
microprocessor in successive 8-bit bytes. The register
may also be reinitialized back to its original value by an
:Autoinitialize. Autoinitialize takes place after EOP*.

Current Word Register
Memory-to-Memory Transfers

The 8237A includes a memory-to-memory transfer feature to perform block moves of data from one memory
address space to another with a minimum of program
space and effort. (See Figure 1-142 for timing.) Channels
o and 1 are selected to operate in the memory-to-memory
mode by programming a bit in the Command register. A
transfer is initiated by setting the software DREQ for
channel O. The 8237A requests a DMA service in the normal manner. After HLDA is true, the device reads data
from the memory using eight-state transfers in the Block
Transfer mode. The channel 0 Current Address register is
the source for the address used and is decremented or
incremented in the normal manner. The data byte read
from the memory is stored in the 8237A internal Temporary register. Channel 1 then writes the data from the

Each channel has a 16-bit Current Word Register. This
register determines the number of transfers to be performed. The actual number of transfers will be one more
than the number programmed in the Current Word register (programming a count of 100 will result in 101 transfers, etc.). The word count is decremented after each
transfer. The immediate value of the word count is stored
in the register during the transfer. When the value in the
register goes from zero to FFFFH, a TC will be generated. This register is loaded or read in successive 8-bit
bytes by the microprocessor in the Program Condition.
Following the end of a DMA service it may also be reinitilized by an Autoinitialization back to its original value.
Autoinitialize can occur only when EOP* occurs. If it is
not Autoinitialized, this register will have a count of FFFFH after TC.

1-145

210912-001

8086/8088 CPU

ADSTB

AO-A7

080-oB7

MEMW

EOP

----------t--W
-------------+----------------------------~----------+_~I

Figure 1-142 Memory-To-Memory Transfer Timing
Base Address and Base Word Count Registers
Each channel has a pair of Base Address and Base Word
Count Registers. These 16-bit registers store the original
value of their associated current registers. During Autoinitialize these values are used to restore the current registers to their original values. The base registers are

Table 1-44 8237A Internal Registers
Ne_

Sin

Number

Base Address Aeglsters
Base Word Count Aeglsters
Current Address Registers
Current Word Count Aeglsters
Temporary Address Aeglster
Temporary Word Count Aeglster
Stetul Aeglster
Command Register
Temporary Register
Mode Registers
Mask Aeglster
Aequest Register

16 bits
16blts
16 bits
16 bits
16 bits
16 bits
8blts
8 bits
8 bits
6 bits
4 bits
4 bits

4
4
4
4
1
1
1
1
1
4
1
1

written simultaneously with their corresponding current
register in 8-bit bytes in the Program Condition by the
microprocessor. These registers cannot be read by the microprocessor.

Command Register
The 8-bit Command register controls the operation of the
8237A (see Figure 1-143). This register is programmed
by the microprocessor in the Program Condition and is
cleared by Reset or a Master Clear instruction. Figure
1-143 lists the function of each of the command bits. Figure 1-144 shows the address coding.

Mode Register
Each channel has a 6-bit Mode register associated with it
(see Figure 1-145). When the register is being written to
1-146

210912-001

8086/8088 CPU

7

o
1
o

6

l

Memory-ta-memory disable
Memory-la-memory enable

5

4

3

2

1

~

0

T-LfOO ,...

~

o
X

L _ _ _ _-I 0
1
o

'-------1

Normal1lming
Compressed liming
11 bit 0 ... 1

Fixed priority
Rotating priority
Late write selection
Extended write selection
If bit 3= 1

o.~

01 Channel 1 select
10 Cha"el 2 s.'ec,
11 Channel 3 select

Channel 0 address hold disable
Channel 0 address hold enable
If bit 0=0
Controller enable
Controller disable

L----I 1

Bit Number

I I I I I I I

00
01
10
11
XX

Verdy transfer
Write transfer
Read transfer
lIIegal
If bits 6 and 7 = 11

o

Autoinitialization disable

1

Autoinitialization enable

o
1

Address increment select
Address decrement select

( 00 Demand mode select
L_ _ _ _ _ _ _-{ 01 Single mode select
'0 Block mode select
11 Cascade mode select

l

DREQ sense active high
DAEQ sense active low

Figure 1·145 Mode Register
Figure 1·143 Command Register
by the microprocessor in the Program condition, bits 0
and 1 determine which channel Mode register is to be
written.

Request Register
The 8237A can respond to requests for DMA service
which are initiated by software as well as by a DREQ.
Each channel has a request bit associated with it in the
4-bit Request register (see Figure 1-146). These are
non-maskable and subject to prioritization by the Priority
Encoder network. Each register bit is set or reset separately under software control or is cleared upon generation of a TC or external EOP*. The entire register is
cleared by a Reset. To set or reset a bit, the software loads

the proper form of the word. See Table 1-45 for register
address coding. In order to make a software request, the
channel must be in Block Mode.

Mask Register
Each channel has a mask bit (see Figure 1-147) which can
be set to disable the incoming DREQ. Each mask bit is set
when its associated channel produces an EOP* if the
channel is not programmed for Autoinitialize. Each bit of
the 4-bit Mask register (see Figure 1-148) may also be set
or cleared separately under software control. The entire
register is also set by a Reset. This disables all DMA
requests until a clear Mask register instruction allows

A2

At

AO

lOR

Operation

lOW

Register

Read Status Register

Write Command Register
Illegal

Signals

Operation

Command
Mode
Request
Mask
Mask
Temporary
Status

Signals

A3

Table 1·45 Definition of Register Codes
CS

lOR

lOW

A3

A2

AI

AO

0
0
0
0
0
0
0

1

0
0
0
0
0
1
1

1
1
1
1
1
1
1

0
0
0
0
1
1
0

0
1
0
1
1
0
0

0
1
1
0
1
1
0

Write
Write
Write
Set/Reset
Write
Read
Read

1

1
1

1
0
0

Write Request Register
Illegal

Wnte Single Mask RegISter 811
Illegal

7

Write Mode Register

6

5

4

3

2

1

0

....-Bit Number

I I I I I I I I I

Illegal

-..Don't Care

Clear Byte POinter Flip i Flop
Read Temporary Register
Master Clear
Illegal

~ 00

Select channel 0
01 Select channel 1
10 Select channel 2
11 Select channel 3
Reset request bit
Set requesl bit

Clear Mask Register
Illegal
Write All Mask Register Bits

Figure 1·144 Software Command Codes

Figure 1·146 Request Register
1-147

210912-001

8086/8088 CPU

7

6

5

4

3

2

1

0_

-..-- L{

Bit Number

I I I I I I I I I
Don't Care

00
01
10
11

Select
Select
Select
Select

channel
channel
channel
channel

0 mask
1 mask
2 mask
3 mask

bit
bit
bit
bit

Clear mask bit
Set mask bit

Temporary Register

Figure 1·147 Mask Bits

o
1

ing DMA requests. Bits 0-3 are set every time a TC is
reached by that channel or an external EOP* is applied.
These bits are cleared upon Reset and on each Status
Read. Bits 4-7 are set whenever their corresponding channel is requesting service.

Clear channel 0 mask bit
Set channel 0 mask bIt

The Temporary register is used to hold data during
memory-to-memory transfers. Following the completion
of the transfers, the last word moved can be read by the
microprocessor in the Program Condition. The Temporary register always contains the last byte transferred in
the last memory·to-memory operation, unless cleared by
a Reset.

Clear channel 1 mask bit
Set channel 1 mask bit

a
1

Clear channel 2 mask bit
Set channel 2 mask bit

Figure 1·148 Mask Register
them to occur. The instruction to separately set or clear
the mask bits is similar in form to that used with the Request register. See Thble 1-45 for instruction addressing.

Software Commands
The software commands are additional special software
commands which can be executed in the Program Condition (see Figure 1-144). The commands do not depend on
any specific bit pattern on the data bus. The software
command are Clear First/Last Flip-Flop, Master Clear
and Clear Mask Register. Figure 1-144 lists the address
codes for the software commands.
a. Clear First/Last Flip/Flop

Status Register
The Status register (see Figure 1-149) is available to be
read out of the 8237 A by the microprocessor. This register contains information about the status of the devices at
this point. This information includes which channels have
reached a terminal count and which channels have pend-

This command is executed prior to writing or reading new
address or word count information to the 8237 A. This
initializes the flip-flop to a known state so that subsequent
accesses to register contents by the microprocessor will
address upper and lower bytes in the correct sequence.
b. Master Clear

1
1

L~======= 1

Channel
Channel
Channel
Channel

0 has
1 has
2 has
3 has

reached
reached
reached
reached

TC
TC
TC
TC

This software instruction has the same effect as the hardware Reset. The Command, Status, Request, Temporary,
and Internal First/Last Flip-Flop registers are cleared and
the Mask register is set. The 8237 A will enter the Idle
cycle.

Channel 0 request
Channell request
Channel 2 request

Channel 3 request

Figure 1·149 Status Register

c. Clear Mask Register
This command clears the mask bits of all four channels,
enabling them to accept DMA requests.

1-148

210912·001

80186180188 CPU

2

CHAPTER 2
80186/80188 CPU
In addition, the 80186 may be interfaced to the 8087 Numeric Data Co-Processor to make use of the "number
crunching" capabilities of that device.

2.1 INTRODUCTION-THE HIGH
INTEGRATION CONCEPT
This chapter presents hardware design data for the 80186/
80188 CPU's and describes the features that distinguish
them from the 8086/8088. The 80186/80188 are upward
compatible from the 8086/8088. In compatible modes of
operation the 80186/188 operate virtually the same as the
8086/88. This chapter also describes the use of the 80186/
188 with various input/output peripheral and memory devices. As the reader will discover, the integrated devices
of the iAPX186 (a DMA unit, timer, interrupt controller,
bus controller, chip select logic, and ready generation
logic all integrated onto the chip) greatly simplify system
configuration.

2.2.1 Architectural Overview
The 80186/188 device architecture consists of the same
Bus Interface Unit (BIU) and Execution Unit (EU) as the
8086188 (see Figure 2-1). The 80186 and 80188 CPUs
have the same basic register set, memory organization,
and addressing modes as the 8086 and 8088. The differences between the 80186 and 80188 are the same as the
differences between the 8086 and 8088: the 80186 has a
16-bit architecture and a 16-bit bus interface; the 80188
has a 16-bit internal architecture, but an 8-bit data bus
interface; the 80186 has a 6-byte prefetch queue and the
80188 has a 4-byte prefetch queue. The execution times
of the two processors differ accordingly. For each nonimmediate 16-bit read/write instruction, 4 additional
clock cycles are required by the 80188. In addition, the
801861188 contain a programmable interrupt controller,
three 16-bit programmable timers, a chip select unit, and
a two channel programmable direct memory access
(DMA) unit.

The iAPX86/88 family consists of two devices: the 80186
processor with a 16-bit external bus and the 80188 processor with an 8-bit external bus. Internally, both devices
use the same processor with the same integrated components. Except where noted, all references to the 80186 in
this chapter apply equally to the 80188. Also, all parametric values in this chapter are from the iAPX186 Advance
Information Data Sheet and pertain to 8 MHz devices.

2.2 COMPONENT OVERVIEW

EXECUTION UNIT AND BUS INTERFACE UNIT

The 80186 and 80188 microprocessors each contain a
number of the most common iAPX system components
integrated onto a single chip (see Figure 2-1). These onboard devices include:

As in the 8086/88, the EU is responsible for the execution
of all instructions, for providing data and addresses to the
BIU, and for manipulating the general registers and the
flag register. Except for a few control pins, the EU is
completely isolated from the "outside" world. The BIU
executes all external bus cycles and consists of the segment and communications registers, the instruction
pointer and the instruction object code queue. The BIU
combines segment and offset values in its dedicated hardware adder to derive 20-bit addresses, transfers data to
and from the EU on the Arithmetic Logic Unit (ALU)
data bus and loads "pre-fetched" instructions into the
queue from which they are fetched by the EU.

• Clock generator
• Two, independent, high speed DMA channels
•

Programmable Interrupt Controller

•
•

Three programmable 16-bit timers
Programmable memory and peripheral chip select
logic

•

Programmable wait state generator

•

Local bus controller.

When the EU is ready to execute an instruction, it fetches
the instruction object code byte from the BIU's instruction
queue and then executes the instruction. If the queue is
empty when the EU is ready to fetch an instruction byte,
the EU waits for the instruction byte to be fetched. If a
memory location or I/O port must be accessed during instruction execution, the EU requests the BIU to perform
the required bus cycle.

This high scale integration doubles the throughput of the
standard 5 MHz 8086. The 80186/88 instruction set is
completely upward compatible with iAPX86 object code
and contains only ten new instructions in addition to the
complete 8086 instruction set. Device compatibility extends to 8086 bus support components that include:
•

8282 and 8283 Octal Latches

•

8286 and 8287 Bus Transceivers

•

8288 Bus Controller for the iAPX86/88

•

8289 Bus Arbiter

The two processing sections of the CPU operate independently. In the 80186 CPU, when two or more bytes of the
6-byte instruction queue are empty and the EU does not
2-1

210912-001

80186/80188 CPU

INT3I1NTA1

INT2/INTAO
CLKOUT Vee GND

!!

rO~

I x,I

TMR IN

1t

ExEcUTIONUNIT]

x,

ALU

GENERATOR

'.-BIT

INTERRUPT

I

REGISTER A
CONTROL REGISTERS

I

R~~~::S

t

MAX COUNT

CONTROLLER

I

GENERAL

It

~:~I~~t:J ~

PROGRAMMABLE

I
I

CLOCK

TMR IN

PROGRAMMABLE
TIMERS
a ,
2

I
I

l6-BIT

t

TMR OUT 1 TMR OUT 0

INTl

CONTROL
REGISTERS

'--..,.---I.--.J

I
I

16-BIT
COUNT REGISTER

{'t

{(

INTERNAL BUS

.-------+-OROO
ORO'

u

'"""'PRD=G:;;R:-:A::M::M:-:A~BL:-;E~

CHIP-SELECT
UNIT

20-BIT
SOURCE POINTERS

J

aDMAUNIT,

SO-S2
SROY-+
AROY-+

BUS INTERFACE
UNIT

Tm-+
HOLO-+

H:;:=+

16-BIT
SEGMENT
REGISTERS
PROGRAMMABLE'

6-BYTE

CONTROL
REGISTERS

PREFETCH

---l-L

IlL HI--------1 uh 1

RESET_

QUEUE

I

.loft.
LOCK

~

WR

BHElS7

DTIII

A ,6/53-

AOO-

AD15

r-r-

~

~ DES~N~~ION
POINTERS

I

Il

la-BIT

TRANSFER COUNT
CONTROL
REGISTERS

L kS6/A2

LCS

PCSSlA1

A191S6

INT3/INTAl

INT2IiN'fAO
CLKOUT Vee GHD

!!

rO~

Jx, jx,

ExEcUTIONuNrr]

CLOCK

GENERATOR

l6·BIT
GENERAL

PURPOSE

REGISTERS

'r

{(

~

~

TMR IN

1t

INITa

It

,

MAX COUNT

PROGRAMMABLE
INTERRUPT
CONTROLLER

REGISTER B

t

2

f..."'"

_~~

MAX COUNT
REGISTER A
CONTROL REGISTERS

CONTROL
REGISTERS

--.J

II

16-BIT
COUNT REGISTER

{(
INTERNAL BUS

r-

.------+-OROO
ORO'

u

U

,>

TMR IN

PROGRAMMABLE
TIMERS

a

I
I
I
I
I
I
I

16-BIT
ALU

·r

t

TMR OUT 1 TMR OUT 0

INn

NTI

~

PROGRAMMABLE
OMAUNIT

a

SO-S2

;=:

BUS INTERFACE
UNIT

HOLD-~

H::,::f.
RESET ....

I

.lot.
LOCK

DTIR

16-81T
SEGMENT
REGISTERS
4-BYTE
PREFETCH
QUEUE

RD

ADO-

A8-

A015

A 15

~

DES~:l~ION
POINTERS

16-8IT
TRANSFER COUNT

REGISTERS

tU.iH!-

BHEJS7

I

LLL 11
I~ 1 L ks.,A2

PROGRAMMABLE
CONTROL

LCS

,

2O-81T
SOURCE POINTERS

CHIP-SELECT
UNIT

SROY--+

CONTROL
REGISTERS

PCS5.'A1

Meso-a

Figure 2-1 80186/80188 Functional Block Diagrams

2-2

210912-001

80186/80188 CPU

require the BIU to perform a bus cycle, the BIU executes
instruction fetch cycles to refill the queue. In the 80188
CPU, when one byte of the 4-byte instruction queue is
empty, the BIU executes an instruction fetch cycle. Note
that since the 80186 CPU has a 16-bit data bus, it can
access two instruction object code bytes in a single bus
cycle. The 80188 CPU, since it has an 8-bit data bus, can
access only one instruction object code byte per bus cycle. If the EU issues a request for bus access while the
BIU is in the process of an instruction fetch bus cycle, the
BIU completes the cycle before honoring the EU's
request.

programmable number of CPU clocks, to give a count
pulse to either or both of the other two timers after a programmable number of CPU clocks, or to give a DMA
request pulse to the integrated DMA unit after a programmable number of CPU clocks.

CHIP SELECT AND READY GENERATION UNIT

The 80186 integrated chip select logic is used to enable
memory or peripheral devices. Memory addressing uses
six output lines and peripheral addressing uses seven output lines. The memory chip select lines are split into 3
groups in order to separately address the three major
memory areas in a typical 80186 system. These major
memory areas are upper memory for reset ROM, lower
memory for interrupt vectors and mid-range memory for
programs. The size of each of these areas is user programmable. The starting location of lower memory is
OOOOOH and the ending location for upper memory is
FFFFFH. Starting and ending locations for mid-range
memory is user programmable.

CLOCK GENERATOR

The 80186/188 integrated circuits include a clock generator and crystal oscillator. The crystal oscillator can be
used with a parallel resonant, fundamental mode crystal
at 2X the desired CPU clock speed (i.e., 16 MHz for an 8
MHz 80186), or with an external oscillator also at 2X the
CPU clock. The output of the oscillator is internally divided by two to provide the 50% duty cycle CPU clock
that initiates all 80186 system timing. The CPU clock is
externally available, and all timing parameters are referenced to this externally available signal. The clock generator also provides ready synchronization for the
processor.

The seven peripheral select lines each address one of
seven contiguous 128 byte blocks above a user programmable base address. The base address for each of these
blocks can be located in either memory or 110 space so
that the peripheral devices may be either memory or I/O
mapped.

PROGRAMMABLE INTERRUPT CONTROLLER

Each of the programmed chip select areas has a set of
programmable ready bits. These ready bits control an integrated wait state generator. This allows a programmable
number of wait states (from 0 to 3) to be inserted whenever an access is made to the area of memory associated
with the chip select area. Each set of ready bits also contains a bit which determines whether the external ready
signals (ARDY and SRDY) will be used or ignored (i.e., a
bus cycle will terminate even though a ready has not been
returned on the external pins). A total of 5 sets of ready
bits allow independent ready generation for each of upper
memory, lower memory, mid-range memory, peripheral
devices 0-3 and peripheral devices 4-6.

The integrated 80186 interrupt controller arbitrates interrupt requests between all internal and external sources.
The integrated interrupt controller has two major modes
of operation, non-iRMXTM 86 mode (called master
mode) and iRMX 86 mode. In the master mode, the integrated controller acts as the master interrupt controller for
the system. It can be directly cascaded as the master system interrupt controller for up to two slave external
8259A interrupt controllers to allow up to 128 interrupts.
In the iRMX 86 mode the integrated interrupt controller
can be configured as a slave controller to an external master system interrupt controller. This provides complete
compatibility with an 80130, 80150, and the iRMX 86
operating system. Some of the interrupt controller registers and interrupt controller pins change definition between the two modes, but the basic function of the
integrated interrupt controller remains basically the same.

PROGRAMMABLE DIRECT MEMORY

ACCESS UNIT
The 801861188 contain an integrated programmable Direct Memory Access (DMA) Unit which contains two
high speed DMA channels. This DMA unit performs
transfers to or from any combination of 110 space and
memory space in either byte or word units. Each DMA
cycle requires from two to four bus cycles: one or two
cycles to fetch the data to an internal register; and one or
two cycles to deposit the data. This operation allows word
data to be located on odd boundaries, or byte data to be
moved from odd locations to even locations. (Locating
word data on odd boundaries and moving bytes from odd

PROGRAMMABLE TIMERS

The integrated timer unit contains three independent programmable 16-bit timer/counters. Two of these timers can
be used to count external events, to provide waveforms
derived from either the CPU clock or an external clock of
any duty cycle, or to interrupt the CPU after a specified
number of timer "events". The third timer counts only
CPU clocks and can be used to interrupt the CPU after a

2-3

210912·001

80186/80188 CPU

to even locations is normally difficult, since odd bytes are
transferred on the upper 8 data bits of the 16-bit data bus,
while even data bytes are transferred on the lower 8 data
bits of the data bus.)

tion of new instructions designed to improve the existing
code, or to produce optimum 80186/188 code. Increased
integration simplifies system construction, which results
in lower part count, therefore, a substantial reduction in
system cost for the user.

Each DMA channel maintains a set of independent 20-bit
source and destination pointers which are used to access
the source and destination of the data transferred. Each of
these pointers may independently address either I/O or
memory space. After each DMA cycle, the pointers may
be independently incremented, decremented, or maintained constant. Each DMA channel also keeps a transfer
count which may be used to terminate a series of DMA
transfers after a pre-programmed number of transfers.

The 80186/188 have the same basic instruction set, memory organization, and addressing modes as the 8086/88.
The differences between the 80186 and 80188 are the
same as the differences between the 8086 and 8088: the
80186 has a 16-bit architecture and a 16-bit bus interface;
the 80188 has a 16-bit internal architecture, but an 8-bit
data bus interface. The instruction execution times of the
two processors differ accordingly. For each nonimmediate 16-bit data read/write instruction four additional clock cycles are required for the 80188.

INTERNAL PERIPHERAL INTERFACE
CPU Execution Speed

The 80186 CPU uses 16-bit registers, contained within an
internal 256-byte control block, to control all integrated
peripherals. This control block may be mapped into either
memory or I/O space. Internal logic recognizes the address and responds to the bus cycle. During bus cycles to
the internal registers, the bus controller signals the operation externally (i.e., the RD*, WR * status, address, data,
etc., lines will be driven as in a normal bus cycle), and
ignores D15-0, SRDY and ARDY. The base address of the
control block must be on an even 256-byte boundary (i.e.,
the lower 8 bits of the base address are all zeros). The
80186 CPU may read from or write to all of the defined
registers within this control block at any time. The current base address of the control block determines the location of any register contained within the 256-byte control
block. Refer to Volume I of this manual for a description
of control block programming.

Because of 80186/188 hardware enhancements in both the
bus interface unit and the execution unit, most instructions require fewer clock cycles to execute than on the
8086/88. Execution speed is gained by performing the
effective address calculations (base + displacement +
index) with a dedicated hardware adder, which takes only
4 clock cycles in the 80186/188 bus interface unit, rather
than with a microcode routine (used by the 8086/88). This
results in an execution speed which is three to six times
faster than the 8 MHz 8086/88.
In addition, the execution speed of specific instructions
has been enhanced. All multiple-bit shift and rotate instructions execute 1.5 to 2.5 times faster than the 8 MHz
8086/88. Multiply and divide instructions execute three
times faster. String move instructions run at bus bandwidth (i.e., data is transferred onto the bus in each consecutive CPU clock cycle), allowing transfers at 2
Megabytes per second (80186),and 1 Megabyte per second (80188), which is about twice the speed of the 8 MHz
8086 or 8088, respectively. Overall, the 80186/188
CPU's are 30-percent faster than the 8 MHz 8086/88
CPU's, and 50-percent faster than the 5 MHz 8086/88
CPU's.

The integrated iAPX 80186 peripherals operate semiautonomously from the CPU. Access to them is, for the
most part, through software read/write of the control and
data locations in the control block. Most of these registers
can be both read from and written to. A few dedicated
lines, such as interrupts and DMA requests, provide realtime communication between the CPU and peripherals
similar to the more conventional system that uses discrete
peripheral blocks. The overall interaction and function of
the peripheral blocks has not substantially changed.

2.2.2 Software Overview
The following paragraphs describe the functions of the
new instructions and interrupts provided by the 80186/
80188 CPU's. A description of the overall instruction set
by category is also provided. In addition, a complete instruction set summary is provided in tabular form which
recaps each device instruction by category, and provides
timing cycles for each instruction.

CPU ENHANCEMENTS
The 80186 and 80188 are highly integrated microprocessors. They effectively combine 15 to 20 of the most common iAPX86 system components on a single chip (see
Figure 2-1). The 80186 and 80188 provide higher performance and more highly integrated solutions to the total
system problem of the microprocessor user. The higher
performance results from the enhancements made to both
the general and specific areas of CPU operation. These
include faster effective address calculation, improvements
in the execution speed of many instructions, and the addi-

NEW 80186/80188 INSTRUCTIONS
The 80186/188 CPU's add ten new instructions to those in
the basic 8086/88 instruction set. These instructions are
2-4

210912-001

80186/80188 CPU

only a single bit shift can be performed, or a multiple shift
can be performed where the number of bits to be shifted is
specified in the CL register.

designed to simplify assembly language programming,
enhance the performance of high-level language implementations, and reduce the size of object code for the
80186/188. The new instructions appear shaded in the instructions set summary at the back of the 80186 data
sheet. The following paragraphs explain the operation of
these new instructions. In order to use these new instructions with the 8086/80186 assembler, the "$modI86"
switch must be given to the assembler. This can be done
by placing the line: "$modI86" at the beginning of the
assembly language file.

All of the shift/rotate instructions of the 80186 allow the
number of bits shifted to be specified by an immediate
value. Like all multiple bit shift operations performed by
the 80186, the number of bits shifted is the number of bits
specified modulus 32 (i.e., the maximum number of bits
shifted by the 80186 multiple bit shifts is 31).

Push Immediate (PUSHI) Instruction

These instructions require two operands: the operand to
be shifted (which may be a register or a memory location
specified by any of the 80186 addressing modes) and the
number of bits to be shifted.

The PUSHI instruction allows immediate data to be
pushed onto the processor stack. This data can be either
an immediate byte (sign extended 8-bit value) or an immediate word (16-bit value). If the data is a byte, it will be
sign extended to a word before it is pushed onto the stack
(since all track operations are word operations).

Block Input/Output (INS/OUTS) Instructions

The two new 80186 input/output instructions (INS and
OUTS) perform block input or output operations similar
to the string move instructions of the processor.

Push All/Pop All (PUSHA, POPA) Instructions

The INS instruction performs block input from an 110
port to memory. The 110 address is specified by the DX
register and the memory location is pointed to by the DI
register. After the operation is performed, the DI register
is adjusted by 1 (if a byte input is specified) or by 2 (if a
word input is specified). The adjustment is either an increment or a decrement, as determined by the Direction
bit in the flag register of the processor. The ES segment
register is used for memory addressing, and cannot be
overridden. When preceeded by a Repeat (REP) prefix,
this instruction allows blocks of data to be moved from an
110 address to a block of memory. The 110 address in the
DX register is not modified by this operation.

These two instructions allow all of the eight of the 80186
general purpose registers to be saved onto the stack, or
restored from the stack. The registers saved by this instruction (in the order they are pushed onto the stack) are
AX, CX, DX, BX, SP, BP, SI and DI. The SP value
pushed onto the stack is the value of the register before the
first PUSH (AX) is performed; the value popped for the
SP register is ignored.
PUSHA and POPA do not save any of the segment registers (CS, DS, SS, ES), the instruction pointer (IP), the
flag register, or any of the integrated peripheral registers.

The OUTS instruction performs block output from memory to an 110 port. The 110 address is specified by the DX
register and the memory location is pointed to by the SI
register. After the operation is performed, the SI register
is adjusted by 1 (if a byte output is specified) or by 2 (if a
word output is specified). The adjustment is either an increment or a decrement, as determined by the Direction
bit in the flag register of the processor. The DS segment
register is used for memory addressing, but can be overridden by using the segment override prefix. When preceeded by a Repeat (REP) prefix, this instruction allows
blocks of data to be moved from a block of memory to an
110 address. The 110 address in the DX register is not
modified by this operation.

Integer Immediate Multiply (IMUL)

The IMUL instruction allows a value to be multiplied by
an immediate value. The result of this operation is 16 bits
long. One operand for this instruction is obtained using
one of the 80186 addressing modes (meaning it can be in
a register or in memory). The immediate value can be
either a byte or a word, but will be sign extended if it is a
byte. The 16-bit result of the multiplication can be placed
in any of the 80186 general purpose or pointer registers.
IMUL requires three operands: the register in which the
result is to be placed, the immediate, and the second operand. The second operand can be any of the 80186 general
purpose register or a specified memory location.

Like the string move instructions, these two instructions
require two operands to specify whether word or byte operations are to take place. Additionally, this determination
can be supplied by the mnemonic itself by adding a "B"
or "W" to the basic mnemonic. For example:

Shifts/Rotates By An Immediate Value

The 80186 can perform multiple bit shifts or rotates
where the number of bits to be shifted is specified by an
immediate value. This is different from the 8086, where

INSB
REPOUTSW
2-5

;perform byte input
;perform word block output
210912-001

80186/80188 CPU

Array Sounds (SOUND) Instruction

struction, this involves only moving the contents of the BP
register to the SP register, and popping the old BP value
from the stack.

The 80186 supplies the BOUND instruction to facilitate
bound checking of arrays. In this instruction, the calculated index into the arrays is placed in one of the general
purpose registers of the 80186. Located in two adjacent
word memory locations are the lower and upper bounds
for the array index. The BOUND instruction compares
the register contents to the memory locations, and if the
value in the register is not between the values in the memory locations, an interrupt type 5 is generated. The comparisons performed are SIGNED comparisons. A register
value equal to the upper bound or the lower bound will not
cause an interrupt. This instruction requires two arguments: the register in which the calculated array index is
placed, and the word memory location which contains the
lower bound of the array which can be specified by any of
the 80186 memory addressing modes). The location containing the upper bound of the array must follow immediately the memory location containing the lower bound of
the array.

Neither the ENTER nor the LEAVE instructions save any
of the 80186 general purpose registers. If they must be
saved, this must be done in addition to the ENTER and the
LEAVE. In addition, the LEAVE instruction does not perform a return from a subroutine. If this is desired, the
LEAVE instruction must be explicitly followed by the
RET instruction.

ADDITIONAL INTERRUPTS
The 80186/80188 include two additional interrupts to detect program execution errors and escape opcodes. These
two new interrupts are the Unused Opcode and Escape
Opcode. The following paragraphs describe these new
interrupts.

Unused Opcode
ENTER And LEAVE Instructions

When opcodes OFH, 63H -67H, FIH and FFFFH are executed an interrupt type 6 is generated. This interrupt is
useful in detecting programs errors (e.g., the execution of
data), and provides a set of opcodes which the user may
define for specific purposes, emulating the action of the
instruction in software.

The 80186 contains two instructions which are used to
build and tear down stack frames of the higher level,
block structured languages. The instruction used to build
these stack frames is the ENTER instruction. The algorithm for this instruction is:
PUSH BP

/*save

the

previous

frame

Escape Opcode

pointer*/

if level=O then
BP:=SP;
else
templ: =S P; I*save current frame pointer*/
temp2:=level-l;
do while temp2>O I*copy down previous level
BP: =BP-2 ;
PUSH [BP];
BP:=templ;
PUSH BP;

The 801861188 CPU's may be programmed to cause an
interrupt type 7 when an escape opcode (D8H-DFH) is
encountered. This provides a straightfoward method of
giving instructions to coprocessors, e.g., the 8087. The
programming is done by a bit in the relocation register. It
is programmed not to cause a interrupt on reset.

frame*/
l*pointers*1

I*put current level frame pointer*1

80186/80188 INSTRUCTION SET

/*create space on the stack for*1

The 80186 and 80188 execute exactly the same instructions. This instruction set includes equivalents to the instructions typically found in previous microprocessors,
such as the 8080/8085. Significant new operations
include:

I*in the save area*1

SP:=SP-disp;
I*local variables*!

Figure 2-2 shows the layout of the stack before and after
this operation.
This instruction requires two operands. The first value
(disp) specifies the number of bytes the local variables of
this routine require. This is an unsigned value and can be
as large as 65536. The second value (level) is an unsigned
value which specifies the level of the procedure and can
be as great as 255.
The 80186 includes the LEAVE instructions to tear down
stack frames built by the ENTER instruction. As can be
seen from the layout of the stack left by the ENTER in-

•

Multiplication and division of signed and unsigned binary numbers as well as unpacked decimal numbers,

•

move, scan and compare operations for strings up to
64k bytes in length,

•

non-destructive bit testing,

•

byte translation from one code to another,

•

software generated interrupts,

• a group of instructions that can help coordinate the
activities of multiprocessing systems.

2-6

210912-001

80186/80188 CPU

?

t

BEFORE

BP

~

SP

-----.~------__--~

AFTER

BP -

OLDBP

1-

.....- - - - - 1
OLD FRAME
PTRS.

CURRENT FRAME
PTR

-

LOCAL
VARIABLE
AREA

SP

_~------------~

Figure 2-2 ENTER Instruction Stack Frame

In addition to these improvements, the 80186/80188
CPU's provide ten new instructions that are used to
streamline existing code and produce optimum new iAPX
186 code (refer to the paragraphs on "NEW 80186/80188
INSTRUCTIONS" in paragraph 2.2.2).

encoded in the instruction. To increment a register, however, does not require as much information, so the instruction can be shorter. The 80186/188 have eight
different machine-level instructions that increment a different 16-bit register. Each of these instructions are only
one byte long.

The 80186/80188 instructions treat different types of operands uniformly. Nearly every instruction can operate on
either byte or word data. Register, memory, and immediate operands may be specified interchangeably in most
instructions. The exception is that immediate values serve
as source and not destination operands. In particular,
memory variables may be added to, subtracted from,
shifted, compared, and so on, in place, without moving
them in and out of registers. This saves instructions, registers, and execution time in assembly language programs. In high-level languages, where most variables are
memory based, compilers can produce faster and shorter
object programs.

The 801861188 instruction set is divided into seven functional groups. These are data transfer, arithmetic, bit manipulation, string manipulation, control transfer, high
level and processor control instructions. The following
paragraphs provide a functional description of the
assembly-level instructions.

Data Transfer Instructions

Data transfer instructions move single bytes and words
between memory and registers. These instructions also
move single bytes and words between the AL or AX registers and 110 ports. Table 2-1 lists the four types of data
transfer instructions and their functions. The data transfer
instructions are categorized in four types: general purpose; input/output; address object; and flag transfer. The
stack manipulation instructions, the instructions for transferring flag contents and the instructions for loading segment registers are included in this group. Figure 2-3
shows the flag storage formats primarily used by the
LAHF instruction when converting 8080/8085 assembly
language programs to run on the 80186 or 80188. The
address object instructions manipulate the addresses of
variables instead of the contents of values of the variables.
This is useful for list processing, based variable and string
operations.

The 80186/80188 instruction set basically exists on two
levels. One is the assembly level and the other is the machine level. To the assembly language programmer, the
80186 appears to have a repertoire of about 100 instructions. One MOV (move) instruction, for example, transfers a byte or a word from a register or a memory location
or an immediate value to either a register or a memory
location. The CPU's, however, recognize 28 different
MOV machine instructions ("move byte register to memory", "move word immediate to register", etc.).
The two levels of instruction set address two different requirements: efficiency and simplicity. The approximately
300 forms of machine-level instructions make very efficient use of storage. For example, the machine instructions that increments a memory operand is three or four
bytes long because the address of the operand must be
2-7

210912-001

80186/80188 CPU

Table 2·2 Arithmetic Instructions

Table 2·1 Data Transfer Instructions
GENERAL PURPOSE
MOV
PUSH
POP
XCHG
XLAT

ADD
ADC
INC
AAA
DAA

Move byte or word
Push word onto stack
Pop word off stack
Exchange byte or word
Translate byte

SUBTRACTION
SUB
SBB

INPUT /OUTPUT
Input word or byte
Output word or byte

IN
OUT

DEC
NEG
CMP
AAS
DAS

ADDRESS OBJECT
LEA
LDS
LES

Load effective address
Load pointer using DS
Load pOinter using ES

MUL
IMUL
AAM

FLAG TRANSFER
LAHF
SAHF
PUSHF
POPF

DIV
IDIV
AAD
CBW
CWD

Load AH register from flags
Store AH register in flags
Push flags onto stack
Pop flags off stack

Arithmetic Instructions

Is,
I7

Z , U , A , U

6

5

4

3

!

P

2

I

U

1

!

C

0

Bit Manipulation Instructions
The 80186 and 80188 CPU's provide three groups of instructions for manipulating bits within both bytes and
words. These three groups are logicals, shifts and rotates.
Table 2-4 lists the three groups of bit manipulation instruetions with their functions.

I
I

1....--6080/8085 FLAGS----..I

I

I

I

I

~g~~F'lu!

U,U ,U ,0,0, I, T,S ,Z ,U tA,U, P, Ute
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

a. Logical

I

The logical instructions include the boolean operators
"not", "and", "inclusive or", and "exclusive or". A
TEST instruction that sets the flags, but does not alter
either of its operands is also included.

U = UNDEFINED; VALUE IS INDETERMINATE
0= OVERFLOW FLAG
o = DIRECTION flAG
I = INTERRUPT ENABLE flAG

T

Subtract byte or word
Subtract byte or word with
borrow
Decrement byte or word by 1
Negate byte or word
Compare byte or word
ASCII adjust for subtraction
Decimal adjust for subtraction
MULTIPLICATION
Multiply byte or word unsigned
Integer multiply byte or word
ASCII adjust for multiply
DIVISION
Divide byte or word unsigned
Integer divide byte or word
ASCII adjust for division
Convert byte to word
Convert word to doubleword

the operands specified in arithmetic instructions contain
data that represents valid numbers for the type of instruction being performed. Invalid data may produce unpredictable results.

Arithmetic operations (see Table 2-2) may be performed
on four types of numbers: unsigned binary, signed binary
(integers), unsigned packed decimal and unsigned unpacked decimal (see Table 2-3). Binary numbers may be 8
or 16 bits long. Decimal numbers are stored in bytes, two
digits per byte for packed decimal and one digit per byte
for unpacked decimal. The processor always assumes that

~~~~.

ADDITION
Add byte or word
Add byte or word with carry
Increment byte or word by 1
ASCII adjust for addition
Decimal adjust for addition

= TRAP flAG

S = SIGN FLAG
Z = ZERO flAG

A = AUXILIARY CARRY FLAG

b. Shifts

Figure 2·3 Flag Store Formats

The bits in bytes and words may be shifted arithmetically
or logically. Up to 255 shifts may be performed, according to the value of the count operand coded in the instruction. The count may be specified as a constant 1, or

P = PARITY FLAG
C = CARRY flAG

2·8

210912-001

80186/80188 CPU

Table 2·3 Arithmetic Interpretation of a·Bit Numbers
HEX

BIT PATTERN

UNSIGNED
BINARY

SIGNED
BINARY

UNPACKED
DECIMAL

PACKED
DECIMAL

+7

7

7

07

o0 0 0 0 1 1 1

7

89

10001001

137

-119

invalid

89

C5

11000101

197

-59

invalid

invalid

extension of the operand in two of the rotate instructions,
allowing a bit to be isolated in CF and then tested by a JC
(jump if carry) or JNC (jump if not carry) instruction.

register CL, allowing the shift count to be a variable supplied at execution time. Also, the number of shifts may be
specified as an immediate value in the instruction. This
eliminates the need for a MOV immediate to the CL register if the number of shifts is known at assembly time.
Before the 80186/80188 perform a shift or rotate, they
AND the value to be shifted with 1FH. This limits the
number of shifts occurring to 32 bits. Arithmetic shifts
may be used to multiply and divide binary numbers by
powers of two. Logical shifts can be used to isolate bits in
bytes or words.

String Instructions
The string instructions, also called primitives, allow
strings of bytes or words to be operated on, one element
(byte or word) at a time. Strings of up to 128k bytes may
be manipulated with these instructions. Instructions are
available to move, compare and scan for a value, as well
as moving string elements to and from the accumulator
and 110 ports. Table 2-5 lists the string instructions. These
basic operations may be preceded by a special one-byte
prefix that causes the instruction to be repeated by the
hardware, allowing long strings to be processed much
faster than would be possible with a software loop. The
repetitions can be terminated by a variety of conditions,
and a repeated operation may be interrupted and resumed.

c. Rotates
Bits in bytes and words can also be rotated. Bits rotated
out of an operand are not lost as in a shift, but are "circled" back into the other "end" of the operand. As in the
shift instructions, the number of bits to be rotated is taken
from the count operand, which may specify either a constant of 1, or the CL register. The carry flag may act as an

Program Transfer Instructions
Table 2·4 Bit Manipulation Instructions

The instruction execution sequence for the 80816/80188
is determined by the content of the code segment register
(CS) and the instruction pointer (IP). The CS register contains the base address of the current code segment (i.e.,
the 64k memory area where instructions are currently being fetched). The IP points to the memory address where
the next instruction to be fetched is located. In most operating conditions, the next instruction to be executed will
have already been fetched and will be waiting in the CPU
instruction queue. The program transfer instructions operate on the instruction pointer and on the CS register.
Changing the content of these causes normal sequential
operation to be altered. When a program transfer occurs,
the queue no longer contains the correct instruction.
When the BIU obtains the next instruction from memory
using the new IP and CS values, it passes the instruction
directly to the EU and then begins refilling the queue
from the new location.

LOGICALS
NOT
AND
OR
XOR
TEST
SHLISAL
SHR
SAR

ROL
ROR
RCL
RCR

"Not" byte or word
"And" byte or word
"Inclusive or" byte or word
"Exclusive or" byte or word
"Test" byte or word
SHIFTS
Shift logical/arithmetic left
byte or word
Shift logical right byte or word
Shift arithmetic right byte or
word
ROTATES
Rotate left byte or word
Rotate right byte or word
Rotate through carry left byte
or word
Rotate through carry right byte
or word

Four groups of program transfers are available with the
80186/188 CPU's (see Table 2-6). These are unconditional transfers, conditional transfers, iteration control instructions, and interrupt-related instructions.

2-9

210912·001

80186/80188 CPU

Table 2·6 Program li'ansfer Instructions

Table 2·5 String Instructions
REP

Repeat

REPE/REPZ

Repeat while equal/zero

REPNE/REPNZ

Repeat while not
equal/not zero

MOVS

Move byte or word string

MOVSB/MOVSW

Move byte or word string

CMPS

Compare byte or word
string

SCAS

Scan byte or word string

LODS

Load byte or word string

STOS

Store byte or word string

UNCONDITIONAL TRANSFERS
Call procedure
Return from procedure
Jump

CALL
RET
JMP

CONDITIONAL TRANSFERS
JA/JNBE
JAE/JNB
JB/JNAE
JBE/JNA
JC
JE/JZ
JG/JNLE
JGE/JNL

a. Unconditional Transfers

JLlJNGE

The unconditional transfer instructions may transfer control to a target instruction within the current code segment
(intrasegment transfer) or to a different code segment (intersegment transfer). The ASM-86 Assembler terms an
intrasegment transfer NEAR and an intersegment transfer
FAR. The transfer is made unconditionally any time the
instruction is executed.

JLE/JNG
JNC
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE

b. Conditional Transfers
The conditional transfer instructions are jumps that may
or may not transfer control depending on the state of the
CPU flags at the time the instruction is executed. These
18 instructions (see Table 2-7) each test a different combination of flags for a condition. If the condition is "true"
then control is transferred to the target specified in the
instruction. If the condition is "false" then control passes
to the instruction that follows the conditional jump. All
conditional jumps are SHORT, that is, the target must be
in the current code segment and within -128 to + 127
bytes of the first byte of the next instruction (IMP DOH
jumps to the first byte of the next instruction). Since
jumps are made by adding the relative displacement of the
target to the instruction pointer, all conditional jumps are
self-relative and are appropriate for position-independent
routines.

JS

Jump If above/not below
nor equal
Jump If above or
equal/not below
Jump If below/not above
nor equal
Jump If below or
equal! not above
Jump if carry
Jump if equal/zero
Jump if greater/not less
nor equal
Jump if greater or
equal! not less
Jump if less/not greater
nor equal
Jump if less or equal/ not
greater
Jump if not carry
Jump if not equal/ not
zero
Jump if not overflow
Jump if not parity / parity
odd
Jump if not sign
Jump if overflow
Jump if parity / parity
even
Jump if sign
ITERATION CONTROLS

Loop
LOOP
Loop If equal/zero
LOOPE/LOOPZ
LOOPNEI LOOPNZ Loop If not equal! not
zero
Jump If register CX - 0
JCXZ
INTERRUPTS
INT
INTO
IRET

Interrupt
Interrupt If overflow
Interrupt return

c. Iteration Control
The iteration control instructions can be used to regulate
the repetition of software loops. These instructions use the
CX register as a counter. Like the conditional transfers,

2·10

210912·001

80186/80188 CPU

Table 2-7 Interpretation of Conditional Transfers

MNEMONIC

CONDITION TESTED

"JUMP IF ..."

JA/JNBE
JAE/JNB
JB/JNAE
JBE/JNA
JC
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JNC
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS

(CF oRZF)-O
CF-O
CF-1
(CF OR ZF)-1
CF-1
ZF-1
«SF XOR OF) OR ZF)-O
(SF XOR OF)-O
(SF XOR OF)-1
((SF XOR OF) OR ZF)-1
CF-O
ZF-O
OF-O
PF=O
SF-O
OF=1
PF=1
SF=1

above/not below nor equal
above or equal I not below
below I not above nor equal
below or equal/not above
carry
eQual/zero
greater I not less nor equal
greater or equal I not less
less I not greater nor equal
less or equal I not greater
not carry
not equal I not zero
not overflow
not parity I parity odd
not sign
overflow
parity I parity equal
sign

Note: "above" and "below" refer to the relationship of two unsigned values;
"greater" and "less" refer to the relationship of two signed values.

the iteration control instructions are self-relative and may
only transfer to targets that are within -128 to + 127
bytes of themselves, i.e., they are SHORT transfers.

ternal events. A final instruction causes the CPU to do
nothing. Except for the flag operations, none of the processor control instructions affect the flags.

Table 2-8 Processor Control Instructions

d. Interrupt Instructions

FLAG OPERATIONS

Interrupt instructions allow interrupt service routines to
be activated by programs as well as by external hardware

Set carry flag
Clear carry flag
Complement carry flag
Set direction flag
Clear direction flag
Set interrupt enable flag
Clear interrupt enable flag

STC
CLC
CMC
STD
CLD
STI
Cli

devices. The effect of software interrupts is similar to
hardware-initiated interrupts. However, the processor
does not execute an interrupt acknowledge bus cycle if the
interrupt originates in software or with an NMI.

High-Level Instructions

EXTERNAL SYNCHRONIZATION

The 80186/188 CPU's have two instructions used with
high-level languages. These are ENTER and LEAVE. Detailed descriptions of the operation of these two instructions are contained in the paragraphs on "NEW 801861
80188 INSTRUCTIONS" in paragraph 2.2.2.

HLT
WAIT
ESC
LOCK

Halt until interrupt or reset
Wait for TEST pin active
Escape to external processor
Lock bus during next
instruction

Processor Control Instructions
NO OPERATION

The processor control instructions allow programs to control various CPU functions. Table 2-8 lists the groups of
processor control instructions and their functions. One
group of instructions updates flags, and another group is
used primarily for synchronizing the processor with ex-

NOP

2-11

No operation

210912-001

80186/80188 CPU

sections of the device specifications is not implied. Exposure to absolute maximum conditions for extended periods of time may affect the device reliability.

INSTRUCTION SET SUMMARY

Table 2-9 presents a reference data table of the complete
80186/80188 instruction set with timing cycles for each
instruction. The instruction timings represent the minimum execution time in clock cycles for each instruction.
The timings are based on the following assumptions:
•

Table 2-11 presents the D. C. voltage characteristics of the
80186/188 CPU's. Tables 2-12 through 2-16 list the various A. C. characteristics timing requirements and timing
responses for the 80186/188 CPU's. Figure 2-5 presents
the major cycle timing waveforms for the 80186/80188
CPU's related to the preceding A.C. characteristics
tables.

The opcode, along with any data or displacement required for execution of a particular instruction, has
been prefetched and resides in the queue at the time it
is needed.

•

No wait states or bus HOLDS occur.

•

All word-data is located on even-address boundaries.

2.4 OPERATING MODES
The following paragraphs present the various operating
modes of the 801861188 CPU's and compare these to
those of the 8086/88 CPU's described in Chapter 1. Refer
to the 8086/88 operating mode discussion in paragraph

All jumps and calls include the time required to fetch the
opcode of the next instruction at the destination address.
Any instructions which involve memory references can
require one (and in some cases, two) additional clocks
above the minimum timings shown. This is du.e to the
asynchronous nature of the handshake between the BIU
andEU.

1.4.

2.4.1 8086/88-80186/188 Operating Mode
Comparisons

2.3 DEVICE PIN DEFINITIONS

The 80186/188 multiplexed address/data bus simultaneously supports both the 8086/88 minimum mode local bus
and the maximum mode system bus. The 80186/188 provides both local bus controller outputs (RD*, WR * , ALE,
DEN* and DT/R*) and the system status outputs (SO*,
S 1* and S2*) for use with the 8288 bus controller. This is
different from the 8086/88 where local bus controller outputs (generated only in the minimum mode) are not available if the status outputs (generated only in the maximum
mode) are required.

The following paragraphs present functional descriptions
of all input/output signals and electrical descriptions of all
of the input/output pins on the 80186 and 80188 40-pin
DIP's.

2.3.1 Functional Description of All Signals
Figure 2-4 shows the 80186/80188 DIP pin assignments
and Table 2-10 provides a complete functional description
of each device pin signal and correlates the description to
the pin number and associated signal symbol.

Because the 80186/188 simultaneously provides both local bus control signals and status outputs, many systems
supporting both a system bus (MULTIBUS) and a local
bus will not require two separate external bus controllers.
The bus control signals may be used to control the local
bus while the status signals are concurrently connected to
the 8288 bus controller to drive the system bus control
signals. The 801861188 CPU's require an 8288 and an
8289 to interface with the MULTIBUS.

2.3.2 Electrical Description of Pins
The absolute maximum ratings for the 8086/8088 device
are as follows.
Absolute Maximum Ratings

Ambient Temperature
Under Bias
Storage Temperature
Voltage on Any Pin with
Respect to GND
Power Dissipation

2.4.2 Queue Status Mode of Operation
OOC to 70°C
-65°C to + 150°C

When the RD* line is externally grounded during reset
and remains grounded during processor operation, causes
the 80186 to enter "queue status" mode. In this mode, the
WR * and ALE signals become queue status outputs, reflecting the status of the internal pre-fetch queue during
each clock cycle. These signals allow a processor extension (such as the Intel 8087 numeric data processor) to
track execution of instructions within the 80186. The interpretation of QSO (ALE) and QSl (WR*) are given in
Table 2-17. These signals change on the high-to-low clock

-1.0 to +7V
3.0 Watt

Stresses above those listed above may cause permanent
damage to the device. These values present stress ratings
only and functional operation of the device at these or any
other conditions above those indicated in the operational

2-12

210912·001

80186/80188 CPU

Table 2·9 Instruction Set Summary

FUNCTION

Clock
Cycles

FORMAT

Comments

DATA TRANSFER
MOV = Move:
Register to Register/Memory
Register'memory to register
Immediate to register memory
Immediate to register

Memory to accumulator

11 000100wi
11 000101wl
11 1 0 0 0 1 1 w
11 01 1 w reg

I
I

mod reg

rim

mod reg

rim

modOOO

rim

datailw,-1

addr-Iow

addr-high

addr-Iow

addr-high

Accumulator to memory

11 010000wl
11 0100 01w l

Registermemory to segment register

11 00 0 1 1 1 0

Segment register to reglster,'memory

11 00011001 mod 0 reg rim

PUSH = Push:
Memory

1111111111

RegISter

10 1 0 1 0

Segment reglSler

10 0 0 reg

I

dala

data

2/12
2/9
12-13
3-4
9
8
2/9
2/11

dal,,1 w " 1

mod 0 reg rim

16
10
9

modl10 rim

I
11 0I
reg

¥_:fl£~~il~l\l;;l(?:~ll:J'f!Jl;lir;J!it,\;.~,~~;~li;'f'~i; ; i§j~"';!;i4; ;,';:;I .:;:"': "':I:A" 'i;i"'I.","',', "',i,:"'},"";"'l"",''"':"'ili"',"' "i' ' ~I:' '$'i' ' 'W' 'I' 'li,' ' ~:';' 'Y,HflC,,',lj"

;;1;;,1,;",'::,,::, ,'10,'::!',; ','c"" "",,',' ,",'/,I/i:Yti/',I:/iU;,
I,,'!

POP = Pop:
Memory

11 00 0 1 1 1 11
reg

modOOO rim

Register

10 1 0 1 1

Segment register

10 0 0 reg 1 1 11

(reg ~011

8/16-bit
8/16-bit

I",:; ,

I"~

,,",",I!',

20
10
8

I
",'',1,,',:'

'I""""",,,>:://,,/!

"",',!

XCHG = exchlnge:
Register/memory with register
Register with accumulator

IN = Input lrom:
Fixed port
Variable port
OUT = OUlpUtlD:
FIXed porI
variable port

XLAT, Translale byte to AL
LEA = Load EA to reg ISler
LOS = Load pointer to OS

11 000011wl
11 00 1 0 reg

mod reg

4/17
3

rim

I

11 1 1 0 0 lOw
11 1 1 0 1 lOw

I
I

11 1 1 00 1 1 W
11 1101 1 1 w
11 1 0 1 0 1 1
11 00 0 1 1 0 1

LES = Load pOinter 10 ES

11 1 0 0 0 1 0 1
11 1000100

LAHF = Load AH wllh flags

11

SAHF ~ Slore AH Inl0 Ilags
PUSHF = Push Ilags

11 00 1 1 1 1 0 1
11 00 1 1 1 0 0

POPf - Pop lIags

11 00 1

o0 1

port

10
8

port

9
7
11
6
18
18
2
3
9
8

mod reg

rim

mod reg

rim

(mod + II)

mod reg

rim

(mod + II)

1111

I

10 t 1

SEGMENT. Sigmont Ovor,ldo:

os

I
I
10 0 1 1 1 1 1 0 I

ES

1001001101

CS

10 0 1 0 1 1 1 0

ss

10 0 1 1 0 1 1 0

2
2
2
2

Shaded areas indicate instructions not available in iAPX 86, 88 microsystems.

2-13

210912·001

80186/80188 CPU

Table 2-9 Instruction Set Summary (continued)

FUNCnON

Clock
Cycl••

FORMAT

ADD '= Add:
Reg/memory with register to either

10 00 0 0 0 d w

Immediate to registerlmemory

1100000swi modOOO rim

Immediate to accumulator

10 00 0 0 1 0 wi

I

mod reg

rim

data

data

10 0 0 1 0 0 d w

Immediate to registerlmemory

1100000swl

mod 0 10 rim

data
dataifw=1

mod reg

I
I
• I

Immediate to accumulator

10001010wl

data

11 11 1 1 11 wi

mod 000 rim

Register

10 1 0 0 0

reg

dataifsw=01

4/16
3/4

8116-bit

3/15

I

3

sua = Sublract:
Reg/memory and register to either

10 0 1 0 1 0 d wi

mod reg

rim

Immediate from register/memory

1100000swi

mod 1 01

rim

Immediate from accumulator

10 0 1 0 1 1 0 wi

data

SaB = Sublract willi borrow:
Reglmemory and register to either

10 00 t 1 0 d wi

mod reg

rim

Immediate from registerlmemory

11 OOOOOs wi

mod011

rim

Immediate from accumulator

10 00 1 1 1 0 wi

data

DEC = Decrement:
Registerlmemory

8116-bit

3/10

rim

INC = Incremenl:
Register/memory

3/10
4/16
3/4

dataifw=1

ADC = Add with carry:
Reg/memory with register to either

I

dataifsw=01

Comments

data

dataifsw=01

dataifw= 1

data

dataifsw=01

dataifw=1

3/10
4/16
3/4
3/10
4/16
3/4

11 111111 wi
reg

mod 00 1 rim

Register

10 1 0 0 1

3/15
3

CMP = Compare:
Registerlmemory with register

10 01 1 1 01 wi

mod reg

rim

Register with register/memory

10 0 1 1 1 00 w

mod reg

rim

Immediate wifh registerlmemory

!100000sw

mod111

rim

Immediate with accumulator

10 01 1 1 1 0 w

data

NEG = Change sign

11 11 1011 w

mod011

3/10
3/10
3/10
3/4
3

AM = ASCII adjust for add

10 01 1 01 1

OM = Oecimal adjust for add

10 01 0 0 1 1

AAS = ASCII adjust for subtract

10 01 1 1 1 1

DAS = Decimal adjust for subtract

10 01 0 1 1 1

MUL = Multiply (unsigned):
Register-Byte
Register-Word
Memory-Byte
Memory-Word

11 11 1011 w

IMUL = Integer multiply (signed):
Register-Byte
Register-Word
Memory-Byte
Memory-Word

11 11 101 1 wi

DIY = Divide (unsigned):
Register-Byte
Register-Word
Memory-Byte
Memory-Word

11 11 1 011 wi

I

data

dataifsw=01

dataifw=1

rim

8116-b,it

8116-bit

8116-bit

8
4
7
4
mod 100 rim

26-28
35-37
32-34
41-43
mod1'01

rim

25-28
34-37
31-34
40-43

mod110 rim

29

38
35

Shaded areas indicate instructions not available in iAPX 86,88 microsystems,

2-14

210912-001

80186/80188 CPU

Table 2·9 Instruction Set Summary (continued)

FUNCTION

Clock
Cycles

FORMAT

Comments

(Continued):
IDlY ~ Integer divide (signed)
Register-Byte
Register-Word
Memory-Byte
Memory-Word
AAM = ASCII adlustfor multiply

11 1 1 1 0 1 1 w 1 mod 111

rim

44-52
53-61
50-58
59-67
19
15

11 1 0 1 0 1 0 0 1 0 0 0 0 1 0 1 0 1

AAO= ASCII adjustfor.divide

11 10101011000010101

CBW=Convertbytetoword

11 001 100 01

CWO = Convert word to double word

11 0 0 1 1 0 0 1 1

LOGIC
Shill/Rotate Inst,uctlons:
RegisterlMemory by 1

11 1 0 1 000 wi

mod

RegisterlMemory by CL

11 1 0 1 o 0 1 wi

mod

2
4

Tn
m

~·H

rim

1

rim

I

-~:

2/15
5+n/17+n
i

i.~

:n~:

m Instruction
ROL
o00
o0 1
ROR
RCL
o 10
o 11
RCR
1 0 0 SHUSAL
101
SHR
111
SAR
AND = And:
Reg/memory and register to either

1001000d w i

mod reg

Immediate to register/memory

11000000wl

mod 1 00 rim

data

Immediate to accumulator

10010010wl

data

data ifw= 1

TEST = And function 10 flags, no ,esult:
Register/memory and register
11 000010wl
Immediate data and register/memory
11 11 1 011 wi

mod reg

rim

dataifw=1

rim

modOOO rim

data

data

dataifw=1

Immediate data and accumulator

11 010100wl

OR = Or:
Reglmemory and register to either

1000010dwi

mod reg

Immediate to register!memory

11000000wl

mod 00 1 rim

data

Immediate to accumulator

10000110wl

data

dataifw=1

dataifw=1

rim

dataifw=1

3/10
4/16
3/4

8/16-bit

3/10
4/10
3/4

8/16-bit

3/10
4/16
3/4

8/16-bit

XOR = Exclusive or:
Reg/memory and register to either

1001100dwi

mod reg

Immediate to register/memory

11000000wl

mod 11 0 rim

data
dataifw= 1

rim

Immediate to accumulator

10011010wl

data

NOT = Invert registerlmemory

[1 1 1 1 0 1 1 wi

mod010 rim

STRING MANIPULATION:
MOYS ~ Move byte/word

11 010010wl

CMPS = Compare byte/word

11 01 001 1 wi

SCAS = Scan byte/word

11 01 0 1 1 1 wi

LOOS = Load byte/wd to AUAX

11

dataifw=1

3/10
4/16
3/4
3

8/16-bit

14
22
15
12

Shaded areas indicate instructions not available in iAPX 86,88 microsystems.

2-15

210912·001

80186/80188 CPU

Table 2-9 Instruction Set Summary (continued)

FUNCTION

FORMAT

Repeated by count In ex
MOVS - Move strIOg

11

CMPS - Compare strIOg

11

SCAS - Scan string

11 11

LOOS - Load string

11 11

Clock
Cycles

10 0 1

o0 1
oa 1
o0 1

8+8n
5+22n
5+15n
6+11n

11010010wl
z 11 0 1 0 0 1 1 w

Comments

I

CONTROL TRANSFER
CALL; Call:
Direct within segment
Re91ster memory
indirect within segment
Direct intersegment

11

10 1

oa a

11

11

11

11 00 1 1

dlsp-Iow

dlSp-hlgh

mod010rm

a1

15
13/19
23

segment offset
segment selector

Indirect mlersegment

11 111111 1

JMP; Unconditional jump:
Short!long

11 1 1 0 1 0 1

disp-Iow

Direct within segment

11 1 1

a 1 00

disp-Iow

Reglster.tmemory indirect within segment 1

I

11111

Direct mtersegment

11

1

modOl1rm

I
11 111111 1

RET ; Return from CALL:
Within segment

11 1 0

Within seg addmg Immed to SP

11 1

T

11)

dlSp·hlgh

mod 1 00 rm

a10 1 aI

Indirect intersegment

(mod

a0 a1
aaaa1 aI

Intersegment

~OO 1 01 11

Intersegment adding Immediate to SP

11 1

a a 10 1 a I

segmen10ilset

38
14
14
11/17
14

segment selector

mod 1 0 1 r m

(mod Til)

data-lOw

data·hlgh

data-low

data"hlgh

26

16
18
22
25

Shaded areas indicate instructions not available in iAPX 86,88 microsystems.

2-16

210912·001

80186/80188 CPU

Table 2-9 Instruction Set Summary (continued)

FUNCTION

Clock
Cycles

FORMAT

Comments

CONTROL TRANSFER
JE/JZ Jump on equaliZero

10 1 1 1 0 1 0 0

disp

4/13

JLJJNGE ::= Jump on less;not greater or equal

10 1 1 1 1 1 0 0

disp

JLE/JNG ::= Jump on less or equal mol greater

10 1 1 1 1 1 1

dlSp

J8/JNAE = Jump on belowmot above or equal

10 1 1 1 0 0 1

dlSp

JBE/JNA ~ Jump on below or equalmol above

10 1 1 1 0 1 1

dlSp

4/13
4/13
4/13
4/13

JP/JPE ~ Jump on parl~'pan~ even

10 1 1 1 1 0 1

dlSp

JO ~ Jump on ovtrtlow

101110000

disp

0

JS = Jump on sign

10 1 1 1 1 00 0

dlSP

JNE/JNZ ~ Jump on not equal'not zero

10 1 1 1 0 1 0 1

disp

JNl/JGE == Jump on not less;greater or equal

10 1 1 1 1 1 0 1

disp

13 if JMP
taken
4ifJMP
not taken

4/13
4/13
4/13
4/13
4/13

JNLE/JG ~ Jump on notlessorequaligreater

10 1 1 1 1 1 1 1

disp

4/13

JNB/JAE ~ Jump on not belowlabove orequal

10.1 1 1 0 0 1 1

disp

4/13

JNBElJA ~ Jump on not below orequal"bove

10 1 1 1 0 1 1 1

disp

JNP/JPO ~ Jump on not par'par odd

10 1 1 1 1 0 1 1

dlSp

4/13
4/13

JNO ~ Jump on not Ovtrtlow

10 1 1 1 0 00 1

dlSP

JNS ~ Jump on not Sign

10 1 1 1 1 0 0 1

dlSp

JCXZ ~ Jump on ex zelO

11 1 1 0 0 0 1 1

I

dlSp

LOOP ~ loop ex times

11 1 1 0 0 0 1 0

disp

LOOPZlLOOPE ~ loop while zewequal

11 1 1 0 0 0 0

I
1I

dlSP

LOOPNZ/LOOPNE ~ loop while not zerOiequal

11 11000001

disp

INT =Interrupt:
Type specilied

11 1 0 0 1 1 0 1 1

type

Type 3

11 1 0 0 1 1 0 0 1

INTO::= Interrupt on overflow

11 1 0 0 1 1 1 01

45
48/4

IRET ~ Inlerlupt return

11 1 0 0 1 1 1 11

28

4/13
5/15
6/16
6/16

16
5

JMP takenl

J MP not taken

47
if INT. takenl
if INT. not
taken

Shaded areas indicate instructions not available in iAPX 86,88 microsystems.

2-17

210912-001

80186/80188 CPU

Table 2-9 Instruction Set Summary (continued)

FUNCTION

Clock
Cycles

FORMAT

PROCESSOR CONTROL
CLC = Clear carry

11 1 1 1 1 00 01

CMC = Complement carry

11 1 1 1 0 1 0 1 1

STC = Set carry

11 1 1 1 1 00 1 1

CLO = Clear direclion

11 1 1 1 1 1 0 01

STO = Set direction

11 1 1 1 1 1 0 1 1

CLI = Clear interrupt

11 1 1 1 1 0 1 01

sn = Set interrupt

11 1 1 1 1 0 1 1 1

HLT = ~alt

11 1 1 1 0 1 0 01

\VAIT=Wait

11 00 1 1 0 1 1 1

LOCK = Bus lock prefix

11 t I l 0 0 0 01

ESC = Processor Extension Escape

11 1 0 lIT TTl mod LLL rim 1
(ITT lLL are opcode to processor extension)

2
2
2
2
2
2
2
2
6
2
6

Comments

if test

=0

Shaded areas indicate instructions not available in iAPX 86, 88 microsystems.

FOOTNOTES
The effective Address (EA) of the memory operand is
computed according to the mod and rim fields:

regis assigned according to the following:

if mod = 11 then rim is treated as a REG field
if mod = 00 then OISP = 0*, disp-Iow and disp-high
are absent
if mod = 01 then OISP = disp-Iow sign-extended to
16-bits, disp-high is absent

reg

Segment
Register

00
01
10
11

ES
CS
SS
OS

if mod = 10 then OISP = disp-high: disp-Iow
REG is assigned according to the following table:

if rim = 000 then EA = (BX) + (SI) + OISP
if rim = 001 then EA = (BX) + (01) + OISP
if rim = 010 then EA = (BP)

l6-Bit (w = 1)

+ (SI) + OISP

000
001
010
011
100
101
110
111

if rim = 011 then EA = (BP) + (01) + OISP
if rim = 100 then EA = (SI) + OISP
if rim = 101 then EA = (01) + OISP
if rim = 110 then EA = (BP)

+ OISP*

if rim = 111 then EA = (BX) + OISP
OISP follows 2nd byte of instruction (before data if
required)
·except if mod

= 00 and rim = 110 then EA = disp-high: disp-Iow.

8-Bit (w = 0)
000
001
010
011
100
101
110
111

AL
CL
OL
BL
AH
CH
OH
BH

The physical addresses of all operands addressed by
the BP register are computed using the SS segment
register. The physical addresses of the destination operands of the string primitive operations (those addressed by the 01 register) are computed using the ES
segment, which may not be overridden.

NOTE:
•
EA CALCULATION TIME IS 4 CLOCK CYCLES FOR ALL MODES AND IS INCLUDED
IN THE EXECUTION TIMES GIVEN WHENEVER APPROPRIATE.

SEGMENT OVERRIDE PREFIX
10 0 1 reg 1 1 0

AX
CX
OX
BX
SP
BP
SI
01

I
2-18

210912-001

80186/80188 CPU

BOTTOM

TOP

Sci ..,,:+--"--"_' U

'U

S1
52

AROY
CLKOUT
RESET
X2

X1

Vss
ALElQSD
RD/QSMO
WAlQS1
BHE
A191S6
A18/S5
A17/S4
A18/53 1Mc, r11r1 r1

TMRIN1
TMRIND
ORQ1
',DRQD

~ 'I.:lJ'L..JJ...IL:'-~I..II..JJ..J.'::'J::.lW~U::J

........................................................................Il....Ij,J' ,

PIN NO.1 MARK..............

Figure 2-4 80186/80188 DIP Pin Assignments
transition, one clock phase earlier than on the 8086. Note
that since execution unit operation is independent of bus
interface unit operation, queue status lines may change in
any T ,state.

tions between the two modes, but the basic function of the
interrupt controller remains basically the same. The main
difference between the two modes is that when in the master mode, the interrupt controller presents its input directly to the 80186 CPU and in the iRMX 86 mode the
interrupt controller presents its interrupt input to an external controller. The external interrupt controller then
presents the interrupt inputs to the CPU.

Since the ALE, RD*, and WR * signals are not directly
available from the 80186 when it is configured in queue
status mode, these signals must be derived from the status
lines SO*-S2 * using an external 8288 bus controller. Th
prevent the 80186 from accidentally entering queue status
mode during reset, the RD* line is internally provided
with a weak pullup device. RD* is the ONLY tri-state or
input pin on the 80186 which is pulled up (neither pullups
nor pulldowns are used for any other 80186 tri-state or
input pin).

Placing the interrupt controller in the iRMX 86 mode is
done by setting the iRMX mode bit in the peripheral control block relocation register. A description of the operation of the integrated interrupt controller in the iRMX 86
and non-iRMX 86 modes of operation is contained in paragraph 2.8.3.

2.4.3 Interrupt Controller Operating Modes

2.5 BUS OPERATION

The integrated interrupt controller has two major modes
of operation. These are the non-iRMX 86 mode (referred
to as master mode) and the iRMX 86 mode. In master
mode the integrated interrupt controller acts as the master
interrnpt controller for the system.

Bus operation in the 80186/188 and 8086/88 CPU's is
basically the same. Before proceeding with this section
review the 8086 Bus Operation discussion in paragraph
1.5.
In the 80186, bus cycles occur sequentially, but do not
necessarily follow one after another; that is, the bus may
remain idle for several T states (Ti) between each bus
access initiated by the 80186. A bus idle occurs whenever
the 80186 internal queue is full and no read/write cycles

In iRMX 86 mode the controller operates as a slave to an
external interrupt controller which operates as the master
system interrupt controller. Some of the interrupt controller registers and interrupt controller pins change defini2-19

210912·001

80186/80188 CPU

Table 2·10 80186/80188 Device Pin Descriptions
Symbol

Pin No.

~

Vcc, Vee

9.43

I

Vss, Vss

System

Name and Function
Power: + 5 volt power supply.

26.60

I

System Ground.

RESET

57

0

Reset Output Indicates that the 80186 CPU ir. being reset, and can be used as a system
reset. It Is active HIGH. synchronized with the procassor clock, and lasts an Integer
number of clock periods corl'!lsponding to thfllength of the ~ signal.

Xl,X2

59.58

I

Crystel Inputs, Xl and X2, provide an external connecllon for a fundamental mode
parallel resonant crystal' for the intarnal. crystel oscillator. Xl can interface to an
external clock instead of a crystel. In this case, minimize the capacitanca on X2 or
drive X2 with complemented Xl. The input or oscillator frequency is Internally divided
by two to generate the clock signal (CLKoi.JT).

CLKOUT

56

0

Clock Output provides the system with a 50% duty cycle waveform. All device pin
timings are specified relative to CLKOIJT. CLKOUT has suffiCient MOS drive capabilitias
for the 8087 Numeric Processor Extension.

RES

24

I

System Reset causas the 80186 to Immediately terminate Its present activity, clear the
Internal logic, and enter a dormant stata. This signal may be asynchronous to the
80186 clock. The 80186 begins fetching instructions approximately 7 clock cycles
after RES Is returned HIGH. RES Is required to be LOW for greater than 4 clock
cycles and Is Internally synchronized. For proper Initialization. tha LOW-to-HIGH transition of RES must occur no sooner than 50 microseconds after power up. This Input
is provided with a Schmitt-trigger to facilitate power-on RES generation via an RC
network. When RES occurs. the 80186 will drive the status lines to an Inactive level
for one clock, and then trl-state them.

'inT

47

I

TEST is examined by the WAIT instruction. If the TEST input is HIGH when
"WAIT" execution begins, instruction execution will suspend. TEST will be
resampled until it goes LOW, at which time execution will resume. If interrupts
are enabled while the 80186 is waiting for TEST, interrupts will be serviced. This
input is synchronized internally.

TMR IN 0,
TMRINl

20
21

I
I

Timer Inputs are used either as clock or pontrol signals, depending upon the
programmed timer mode. These inputs are active HIGH (or LOW-to-HIGH
transitions are counted) and internally synchronized.

TMR OUT 0,
TMR OUT 1

22
23

0
0

Timer outputs are used to provide single pulse or continUous waveform generation, depending upon the timer mode selected.

,DRaO
ORal

18
19

I
I

DMA Request is driven HIGH by an external device when it desires that a
DMA channel (Channel 0 or 1) perform a transfer. These signals are active
HIGH, level-triggered, and internally synchronized.

NMI

46

I

Non-Maskable Interrupt is an e.dge-triggered input which causes a type 2
interrupt. NMI is not maskable internally. A transition from a LOW to HIGH
initiates the interrupt at the next instruction boundary. NMI is latched internally. An NMI duration of one clock or more will guarantee service. This input is
internally synchronized.

INTO,INT1,
INT2/fNTAij
INT3/INTAl

45,44
42
41

I
I/O
I/O

Maskable Interrupt Requests can be requested by strobing one of these pins.
When configured as inputs, these pins are active HIGH. Interrupt Requests are
synchronized internally. INT2 and INT3 may be configured via software to
provide active-LOW interrupt-acknowledge output signals. All interrupt inputs
may be configured via software to be either edge- or level-triggered. To ensure
recognition, all interrupt requests must remain active until the interrupt is
acknowleged. When iRMX mode is selected, the function of these pins
changes (see Interrupt Controller section of this data sheet).

A19/S6,
A18/S5,
A17/S4,
A16/53

65

0
0
0
0

Address Bus Outputs (16-19) and Bus Cycle Status (3-6) reflect the four most
significant address bits during T1. These signals are active HIGH. During T2,
T3, Tw, and T4, status information is available on these lines as encoded
below:

66'
67
66

I

I

56

Low
Processor Cycle

53,$4, and 55 are defined as LOW during T2-T4'
AD15-ADO

10-17,
1-8

I/O

I

High
DMA Cycle

I

Address/Data Bus (0-15) signals constitute the time mutiplexed memory or I/O
address (T1) and data (T2' T3, Tw, and T4) bus. The bus is active HIGH. Ao is
analogous to BHE for the lower byte of the data bus, pins 07 through Do. It is
LOW during T1 when a byte is to be transferred onto the lower portion of the
bus in memory or I/O operations.

2-20

210912-001

80186/80188 CPU

Table 2·10 80186/80188 Device Pin Descriptions (continued)
Symbol
BHE/S7

Pin
No.

Type

Name and Function

64

0

During T, the Bus High Enable sign-al should be used to determine if data is to
be enabled onto the most significant half of the data bus. pins 0'5-08. BHE is
LOW during T, for read. write. and interrupt acknowledge cycles when a byte is
to be transferred on the higher half of the bus. The S7 sta~information is
available during T2. T3. and T4. S7 is logically equivalent to BHE. The signal is
active LOW. and is tristated OFF during bus HOLD.
BHE and AO Encodings
BHE Value

AO Value

Function

0
0
1

0
1
0
1

Word Transfer
Byte Transfer on upper half of data bus (015-08)
Byte Transfer on lower half of data bus (07-00)
Reserved

,
ALE/QSO

61

0

Address Latch Enable/Queue Status 0 is provided by the 80186 to latch the
address into the 8282/8283 address latches. ALE is active HIGH. Addresses are
. guaranteed to be valid on the trailing edge of ALE. The ALE rising edge is
generated off the rising edge of the CLKOUT immediately preceding T, of the
associated bus cycle. effectively one-half clock cycle earlier than in the standard 8086. The trailing edge is generated off the CLKOUT rising edge in T, as
in the 8086. Note that ALE is never floated.

WR/QSl

63

0

Write Strobe/Queue Status 1 indicates tl;1at the data on the bus is to be written
into a memory or an I/O device. WR Is active for T2, T3, and Tw of any write
cycle. It is active LOW, and floats during "HOLD." It is driven HIGH for one clock
during Reset, and then floated. When the 80186 is in queue status mode, the
ALE/QSO and WR/QSl pins provide information about processor/instruction
queue interaction.
QSl
0
0
1
1

QSO
0
1
1
0

Queue Operation
No queue operation
First opcode byte fetched from the queue
Subsequent byte fetched from the queue
Empty the queue

RD/QSMD

62

0

Read Strobe indicates that the 80186 is performing a memory or 1/0 read cycle.
RD is active LOW for T., T 3 , and Tw of any read cycle. It is guaranteed not to go
LOW in T. until after the Address Bus is floated. RD is active LOW, and floats
during "HOLD." RD is driven HIGH for one clock during Reset, and then the output
driver is floated. A wllak internal pull-up mechanism on the RD line holds it HIGH
when the line is not driven. During RESET the pin is sampled to determine
whether the 80186 should provide ALE, WR and RD, or ilthe Queue-Status should
be provided. RD should be connected to GND to provide Queue-Status data.

ARDY

55

I

Asynchronous Ready informs the 80186 that the addressed memory space or I/O
device will complete a data transfer. The ARDY input pin will accept an
asynchronous input, and is active HIGH. Only the rising edge is internally
synchronized by the 80186. This means that the falling edge of ARDY must be
synchronized to the 80186 clock. I! connected to Vee, no WAIT states are inserted.
Asynchronous ready (A ROY) or synchronous ready (SRDY) must be active to
terminate a bus cycle. I! unused, this line should be tied LOW.

SRDY

49

I

Synchronous Ready must be synchronized externally to the 80186. The use of
SRDY provides a relaxed system-timing specification on the Ready input. This is
accomplished by eliminating the one-hal! clock cycle which is required for
internally resolving the signal level when using the ARDY input. This lineis active
HIGH. I! this line is connected to Vee, no WAIT states are inserted. Asynchronous
ready (ARDY) or synchronous ready (SRDY) must be active before a bus cycle is
terminated. I! unused, this line should be tied LOW.

LOCK

48

0

LOCK output indicates that other system bus masters are not to gain control of
the system bus while LOCK is active LOW. The LOCK signal is requested by the
LOCK prefix instruction and is activated at the beginning of the first data cycle
associated with the instruction following the LOCK prefix. It remains active
until the completion of the instruction following the LOCK prefix. No prefetches will occur while LOCK is asserted. LOCK is active LOW, is driven HIGH
for one clock during RESET, and then floated.

--

I

2-21

210912-001

80186/80188 CPU

Table 2·10 80186/80188 Device Pin Descriptions (continued)
Symbol
SO,Sl,S2

Pin
No.

Type

Name and Function

52-54

0

Bus cycle status SO-S2 are encoded to provide bus-transaction information:
80186 Bus Cycle Status Information
S2

Sl

SO

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Bus Cycle Initiated
Interrupt Acknowledge
Read I/O
Write I/O
Halt
Instruction Fetch
Read Data from Memory
Write Data to Memory
Passive (no bus cycle)

The status pins float during "HOLD."
S2 may be used as a logical M/IO indicator, and 51 as a DT/R indicator.
The status lines are driven HIGH for one clock during Reset, and then floated
ntil a bus cycle begins.
HOLD (input)
HLDA (output)

50
51

I
0

HOLD Indicates that another bus master Is requesting the local bus. The
HOLD Input Is active HIGH. HOLD may be asynchronous with respect to the
80186 clock. The 80186 will Issue a HLDA (HIGH) In response to a HOLD
re~uest at the end of T4 or Tl. Simultaneous with the Issuance of HLDA, the
80 86 will float the local bus and control lines. After HOLD Is detected as
being LOW, the 80186 will lower HLDA. When the 80186 needs to run
another bus cycle, It will again drive the local bus and control lines.

UCS

34

0

Upper Memory Chip Select is an active LOW output whenever a memory
reference Is made to the defined upper portion (1 K-256K block) of memory.
This line is not floated during bus HOLD. The address range activating
is
software programmable.

ues

LCS

MCSO-3

33

0

Lower Memory Chip Select is active LOW whenever a memory reference is
made to the defined lower portion (lK-256K) of memory. This line is not
floated during bus HOLD. The address range activating LCS is software
programmable.

38,37,36,35

0

Mid-Range Memory Chip Select signals are active LOW when a memory
reference is made to the define~id-range portion of memory (8K-512K).
These lines are not floated during us HOLD. The address ranges activating
~-3 are software programmable.
Peripheral Chip Select signals 0-4 are active LOW when a reference is made to
the defined peripheral area (64K byte I/O space). These lines are not floated
during bus HOLD. The address ranges activating PCSO-4 are software
programmable.

25

0

l5C'Sl·4

27,28,29,30

0

PCS5/Al

31

0

Peripheral Chip Select 5 or Latched Al may be programmed to provide a sixth
peripheral chip select, or to provide an internally latched Al Signal. The
address range activating ~ is software programmable. When programmed
to provide latched Al, rather than PCS5, this pin will retain the previously
latched value of Al during a bus HOLD. Al is active HIGH.

PCSS/A2

32

0

Peripheral Cblp Select 6 or Latched A2 may be programmed to provide a
seventh peripheral chip select, or to provide an internally latched A2 signal.
The address range activating PCSS is softwa!!..R!:ogrammable. When programmed to provide latched A2, rather than PCS6, this pin will retain the
previously latched value of A2 during a bus HOLD. A2 Is active HIGH.

DT/R

40

0

Data Transmit/Receive controls the direction of data flow through the external
8286/8287 data bus transceiver. When LOW, data Is transferred to the 80186.
When HIGH the 80186 places write data on the data bus.

DEN

39

0

Data Enable is provided as an 8286/8287 data bus transceiver o'utput enable.
l5EN Is active LOW during each memory and I/O access.l5EN is HIGH whenever
DTIJ!f changes state.

PCSO

2-22

210912·001

80186/80188 CPU

Table 2-11 D.C. Characteristics
D.C. CHARACTERISTICS (T3A =oo-70o, Vcc=5V :l::10%)
.Symbol

Parameter

VIL

Input Low'Voltage

VIH

Input High Voltage
(All except Xl and (RES)

,

Min.

Max.

Units

- 0.5

+ 0.8
Vee + 0.5

Volts

Vee + 0.5

Volts

0.45

Volts

2.0

Test Conditions

Volts

VIH1

Input High Voltage (1lES)

Va.

Output Low Voltage

3.0

VOH

Output High Voltage

2.4

Icc

Power Supply Current

550
45ij

mA

Max measured at +A = ~~~c

lu

Input Leakage Current

",lQ

~

OV < VIN < Vee

Ito

Output Leakage Current

",10

~

0.45V

Vew

Clock Output Low

0.6

Volt~

I~ - 4.0 mA

Volts

10 • = -200~

VCHO

Clock Output High

Vcu
VCHI

Clock Input Low Voltage

-0.5

Clock Input High Voltage

3.9

~

Input Capacitance

c:.,

1/0 Capacitance

Volts

4.0

loa = -400 ~
AS

0.6

Volts

Vee + 1.0
10

Volts

20

pF

are being requested by the execution unit or integrated
DMA unit. Recall that the bus interface unit fetches opcodes (including immediate data) from memory, while the
execution unit actually executes the pre-fetched instructions. The number of clock cycles required to execute an
80186 instruction vary from 2 clock cycles for a register
to register move to 67 clock cycles for an integer divide.

I. = 2.5 mA for· m:l-~
I•. = 2..0 mA lor all other outputs

<

VOUT < Vee

PI"

fetch queue at a greater rate. This usage also means that
the effect of wait states is more pronounced in an 80186
system than in an 8086 system. In all but a few cases,
however, the performance degradation incurred by adding
a wait state is less than might be expected because instruction fetching and execution are performed by separate
units.

If a program contains many long instructions, program
execution will be CPU limited, that is, the instruction
queue will be constantly filled. Thus, the execution unit
does not need to wait for an instruction to be fetched. If a
program contains mainly short instructions or data move
instructions, the execution will be bus limited. Here, the
execution unit will be required to wait often for an instruction to be fetched before it continues its operation.

2.5.1 HALT Bus Cycle
The 80186 uses a HALT bus cycle to signal external circuits that the CPU has executed a HLT instruction. This
bus cycle differs from a normal bus cycle in two important ways. First, since the processor is entering a halted
state, none of the control lines (RD'" or WR*) will be
driven active. Address and data information will not be
driven by the processor, and no data will be returned.
Second, the SO"'-S2'" statUs lines go to their passive state
(all high) during T2 of the bus cycle, well before they go
to their passive state during a normal bus cycle. RD"',
WR"', INTA*, DEN'" will all go high (VOH) and DT/R'"
will go low (VOL)' Like a normal bus cycle, ALE is driven
active. Since no valid address information is present, the

Although the amount of bus usage (Le., the percentage of
bus time used by the 80186 for instruction fetching and
execution required for top performance) will vary considerably from one program to another, a typical instruction
mix on the 80186 will require greater bus usage than the
8086. This is greater usage caused by the higher performance execution unit requiring instructions from the pre-

2-23

210912·001

80186/80188 CPU

Table 2·12 A.C. Characteristics Timing Requirements
A.C. CHARACTERISTICS (TA = O·-70·C. Vee = 5V ::t: 10%)
80186 Timing Requirements. All Timings Measured At 1.5 Volts Unless Otherwise Noted.
Applicable to 80186 (8 MHz) and 80186·6 (6 MHz)

-----

•....

Symbol

Parameter

Min.

Max.

Units

TOVCl

Data in Setup (AID)

20

ns

TClOX

Data in Hold (AID)

10

ns

TARYCHl Asynchronous Ready
inactive hold time

15

ns

TARYHCH Asynchronous Ready
(AREAOY) active setup
time·

20

ns

TARYlCL AREAOY inactive setup
time

35

ns

TCHARYX AREADY hold time

15

ns

TSRYCL

Synchronous Ready
(SREADY) transition setup
time

20

ns

TClSRY

SREADY transition hold
time

15

ns

THVCl

HOLD Setup·

25

ns

TINVCH

INTR, NMI. TEST, TIMERIN.
Setup·

25

ns

TINVCl

DRQO. DRQ1. Setup·

25

ns

Test Conditions

--

·To guarantee recognition at next clock.

33% duty cycle CPU clock (one-third of the time it is
high, the other two-thirds of the time, it is low). These
differences manifest themselves as follows:

information strobed into the address latches should be ignored. However, this ALE pulse can be used to latch the
HALT status from the SO*-S2* status lines.

1. No oscillator output is available from the 80186, as it
is available from the 8284A clock generator.
2. The 80186 does not provide a PCLK (50% duty cycle, one-half CPU clock frequency) output as does the
8284A.
3. The clock low phase of the 80186 is narrower, and the
clock high phase is wider than on the same speed
8086.
4. The 80186 does not internally factor AEN with ROY.
Therefore, if both ROY inputs (AROY and SROY) are
used, external logic must be used to prevent the ROY
not connected to a certain device from being driven
active during an access to this device (remember,
only one ROY input needs to be active to terminate a
bus cycle).
5. The 80186 concurrently provides both a single asynchronous ready input and a single synchronous ready
input, while the 8284Aprovideseither two synchronous ready inputs or two asynchronous ready inputs as
a user-strapable option.
6. The CLOCKOUT (CPU clock output signal) drive cac
pacity of the 80186 is less than the CPU clock drive
capacity of the 8284A. Therefore, not as many high
speed devices (e.g., Schottky TTL flip-flops) may be
connected to this signal as can be used with the 8284A
clock output.

Halting the processor does not interfere with the operation of any of the 80186 integrated peripheral units.
Therefore, if a OMA transfer is pending while the processor is halted, the bus cycles associated with the OMA
transfer will run. In fact, OMA latency time will improve
while the processor is halted because the OMA unit will
not be contending with the processor for access to the
80186 bus.

2.5.2 8086/80186 Bus Operation

Differences
The 80186 bus was designed to be upward compatible
with the 8086 bus. As a result, the 8086 bus interface
components (the 8288 bus controller and the 8289 bus
arbiter) may be used directly with the 80186. There are a
few differences between the two processors, however,
which must be considered. These are described in the following paragraphs.
CPU DUTY CYCLE AND CLOCK GENERATOR

The 80186 contains an integrated clock generator which
provides a 50% duty cycle CPU clock. The 8086 differs
by using an external clock generator (the 8284A) with a

2·24

210912-001

80186/80188 CPU

Table 2-13 A.C. Characteristics Master Interface Timing Responses
80188 (8 MHz)
Symbol

Paramelers

TCLAV

Address Valid Delay

TCLAX

Address Hold

TCLAZ

Address Float Delay

TCHCZ

Command Lines Float Delay

TCHCV

Command Lines Valid Delay
(afterftoat)

TLHLL

ALE Width

TCHLH

ALE Active Delay

Min.
5

MalL

Min.

Max.

Units

55

5

63

ns

35

TcLAX

10
TCLAX

80188-6 (6 MHz)

10

ns
44

ns

45

56

ns

55

76

ns

44

ns

TCLCL-35

ns

TCLCL-35
35

TCHLL

ALE Inactive Delay

TLLAX

Address Hold to ALE Inactive

TCLOV

Data Valid Delay

10

TCLOCX

Data Hold Time

10

10

TWHOX

Data Hold after WR

TCLCL-40

TCLCL-50

TCVCTV

Control Active Delay 1

5

70

5

87

ns

TCHCTV

Control. Active Delay 2

10

55

10

76

ns

TCVCTX

Control Inactive Delay

5

55

5

76

ns

TCVOEX

DEN Inactive Delay
(Non-Write Cycle)

10

70

10

87

ns

TAlRL

Address Float to RD Active

0

TCLRL

RD Active Delay

10

70

10

87

ns

TCLRH

RD Inactive' Delay

10

55

10

TCLCH

ns

TRHAV

RO Inactive to Address Active

TCLHAV

HLDA Valid Delay

TRLRH

RDWidth

2TCLCL-50

2TCLCL-50

ns

TWLWH

WRWidth

2TcLCL-40

2TcLCL_40

ns

TAVAl

Add,ess Valid to ALE Low

TCLCH-25

TClCH-45

TCHSV

Status Active Delay

10

55

10

TCHCL

ns

TCLSH

Status Inactive Delay

10

65

10

TCLCH

ns

TCLTMV

Timer Output Delay

60

75

ns

TCLRO

Reset Delay

60

75

ns

44

ns

35

44

TCHCL-25

10

5

55

ns

ns

ns

TCLCL-50
5

50

ns
ns

0

TClCL-40

ns
ns

TCHCL-30
44

67

ns

ns

TCHQSV

Queue Status Delay

TCHDX

Status Hold Time

10

10

ns

TAVCH

Address Valid to Clock High

10

10

ns

35

Test Conditions
CL : 20-200 pF all outputs

100 pF max

LOCAL BUS CONTROLLER AND CONTROL
SIGNALS

7, The crystal or external oscillator used by the 80186 is
twice the CPU clock frequency, while the crystal or
external oscillator used with the 8284A is three times
the CPU clock frequency,

The 80186 simultaneously provides both local bus controller outputs (RD*, WR*, ALE, DEN*, and DT/R*)

Table 2-14 A.C. Characteristics Chip-Select Timing Requirements
Symbol

Parameter

Min,

TCLCSV

Chip-Select Active Delay

Tcxcsx

Chip-Selct Hold from
Command Inactive

35

TCHCSX

Chip-Select Inactive Delay

5

Max,

Min_

66

Max.

Units

80

ns
ns

35
10

35

2-25

Test Conditions

47

ns

210912-001

80186/80188 CPU

Table 2·15 A.C. Characteristics ClKIN Requirements
80186 ClKIN Re.quirements
Symbol

80186 (8 MHz) 80186·6 (6 MHz)
Min.
Max. Units
Min.
Max.

Parameter

Test Conditions

TCKIN

ClKIN Period

TCKHl

ClKIN Fall Time

TCKlH

ClKIN Rise Time

TClCK

ClKIN Low Time

25

33

ns

1.5 volts

TCHCK

ClKIN High Time

25

33

ns

1.5 volts

62.5

250

83

250

ns

10

,10

ns

3.5 to 1.0 volts

10

10

ns

1.0 to 3.5 volts

and status outputs (SO*, S 1*, S2 *) for use with the 8288
bus controller. This is different from the 8086 where the
local bus controller outputs (generated only in minimum
mode) are sacrificed if status outputs (generated only in
maximum mode) are desired. These differences will manifest themselves in 8086 systems and 80186 systems as
follows:

HOlD/HlDA VERSUS RQ*/GT*

The 80186 uses a HOLD/HLDA type of protocol for exchanging bus mastership (like the 8086 in minimum
mode) rather than the RQ*/GT* protocol used by the
8086 in maximum mode. This allows compatibility with
Intel's new generation of bus master peripheral devices
(for example the 82586 Ethernet controller or 82730 CRT
controller) .

1. Because the 80186 can simultaneously provide local
bus control signals and status outputs, many systems
supporting both a system bus (e.g., a MULTIBUS)
and a local bus will not require two separate external
bus controllers, that is, the 80186 bus control signals
may be used to control the local bus while the 80186
status signals are concurrently connected to the 8288
bus controller to drive the control signals of the system bus.

STATUS INFORMATION

The 80186 does not provide S3-S5 status information. On
the 8086, S3 and S4 provide information regarding the
segment register used to generate the physical address of
the currently executing bus cycle. S5 provides information concerning the state of the interrupt enable flip-flop.
These status bits are always low on the 80186.

2. The ALE signal of the 80186 goes active a clock
phase earlier on the 80186 then on the 8086 or the
8288. This timing minimizes address propagation
time through the address latches, since typically the
delay time through these latches from inputs valid is
less than the propagation delay from the strobe input
active.

Status signal S6 is used to indicate whether the current
bus cycle is initiated by either the CPU or a DMA device;
subsequently, S6 is always low on the 8086. On the
80186, it is low whenever the current bus cycle is initiated
by the 80186 CPU, and is high when the current bus cycle
is initiated by the 80186 integrated DMA unit.

3. The 80186 RD* input must be tied low to provide
queue status outputs from the 80186 (see Figure 2-6).
When so strapped into "queue status mode", the
ALE and WR * outputs provide queue status information. Notice that this queue status information is available one clock phase earlier from the 80186 than from
the 8086. See Figure 2-7.

BUS DRIVE

The 80186 output drivers will drive 200pF loads. This is
double that of the 8086 (l OOpF). This allows larger systems to be constructed without the need for bus buffers. It

Table 2·16 A.C. Characteristics ClKOUT Requirements
80186 ClKOUT Timing (200 pF load)
Symbol

Parameter

Min.

Max.

Min.

Max. Units

Test Conditions

TCICO

~lKIN

TClCl

ClKOUT Period

TClCH

ClKOUT Low Time

V2 TClCl-7.5

V2 TClCl-7.5

ns

TCHCl

ClKOUT High Time

'/2 TClCl-7.5

'/2 TClCl-7.5

ns

1.5 volts

to ClKOUT Skew

TCH1CH2 ClKOUT Rise Time
. TCL2Cll

ClKOUT Fall Time

50
125

500

167

62.5

ns

500

ns
1.5 volts

15

15

ns

1.0 to 3.5 volts

15

15

ns

3.5 to 1. volts

2-26

210912-001

80186/80188 CPU

T,

Tw

T,

CLKOUT

BHE/S7,

A19/$s-A'6 /5:J

ALE

TCHU;-:;:~ 1::LAV____

I:::

~gt~l::

1~5~Ao
WRITE CYCLE

1\

DATAOU'

TClpox:r-

~--------II.~~~I~~

--I_--+"_V"'_-+-'~ ~r-+ITLLA:

RQ,INTA,
DT/R ~ VOH

J-

TC,LAZ_

jl#~-

--

__~__-+____'~_YY ~'_-~~I-~-+----l·~..,.LW.. ~------~~__~__~_____
__

- ..J-

j/

TCLAZ

--t---JI

INTA CYCLE
DT/R

~-

/r

FLOAT

TCHCTV

\ 1- :CLDX
POINTEI

//

~ -J-~
___+-____'_~Y~I

tlit11: = VOL

_

FLOAT

I~lfl;=':!:£!!£!!..--

~[)'f-----

~

fiij,~~VOH

1

__I..-[j

VI/

.__.

i-rj-+J+-_ _ __

I
SOFTWARE HALT-DT/R ~VOL'
RD, WR, INTA, DEN ~ VOH

pcs,
MCS
LCS,
UCS

---+---t

-

INVALID ADDRESS

TCHC~X­
_TCLCSV

TCXCSX_

-

Figure 2·5 Major Cycle Timing Waveforms
READIWRITE SIGNALS

also means that good grounds must be provided to the
80186, since its large drivers can discharge its outputs
very quickly causing large current transients on the 80186
ground pins.

The 80186 does not provide early and late write signals,
as does the 8288 bus controller. The WR * signal generated by the 80186 corresponds to the early write signal of

2-27

210912-001

80186/80188 CPU

TCH1CH2

CLKOUT

52.So

---r----~----_+-----r------r_--_+--+.r~~77~t_----_+------------

BHEIS7,A19156-A16/S3

ALE

AD,,-ADo

READ CYCLE

DTIR

DEN
PCS,

MCii
LCS,
UCS

----t""""'

NOTES:
1. Following a Write cycle, the Local Bus is floated by the 80186 only when the
80186 enters a "Hold Acknowledge" state.
2. INTA occurs one clock later in RMX-mode.
3. Status inactive just prior to T4

Figure 2·5 Major Cycle Timing Waveforms (continued)
Table 2·17 80186 Queue Status
QS1

QSO

80186

Interpretation

QSO - - - - ; ALE

0

0

no operation

0

I

first byte of instruction taken
from queue

I

0

queue was reinitialized

I

I

subsequent byte of instruction
taken from queue

QS1 .....- - - I WR

r-L-R_D__. .
Figure 2·6 Generating Queue Status Information

2-28

210912-001

80186/80188 CPU

CLOCK
OUT

186

as ________~------~----~L-~----~_*---------------~~------~--------~~,~----~~~-----as ____________________________
____
______

8086

~'~

~J~

1. 80186 changes queue status off falling edge of ClK
2. 8086 changes queue status off rising edge of ClK

Figure 2-7 80186 and 8086 Queue Status Generation

active bus cycle when address information is not being
generated on the address/data pins. In most systems, the
DEN* signal should NOT be directly connected to the
OE* input of buffers, since unbuffered devices (or other
buffers) may be directly connected to the processor's
address/data pins. If DEN* were directly connected to
several buffers, contention would occur during read cycles, as many devices attempt to drive the processor bus.
Rather, DEN* should be a factor (along with the chip selects for buffered devices) in generating the output enable
input of a bi-directional buffer.

the 8288. This means that data is not stable on the
address/data bus when this signal is driven active.
The 80186 also does not provide differentiated lIO and
memory ready and write command signals. If these signals are desired, an external 8288 bus controller may be
used, or the S2* signal may be used to synthesize differentiated commands.

2.5.3 Multiplexed Address/Data Bus
(186,188)

The DT/R * signal determines the direction of data propagation through the bi-directional bus buffers. It is high
when ever data is being driven out from the processor,
and is low whenever data is being read into the processor.
Unlike the DEN* signal, DT/R* may be directly connected to bus buffers, since this signal does not usually
directly enable the output drives of the buffer. See Figure
2-8 for an example data bus subsystem supporting both
buffered and unbuffered devices. Observe the A side of
the 8286 buffer is connected to the 80186, the B side to
the external device. The B side of the buffer has greater
drive capacity than the A side (since it is meant to drive
much greater loads). The DT/R* signal can directly drive
the T (transmit) signal of the buffer, since it has the correct polarity for this configuration.

Because of the bus drive capabilities ofthe 80186 (200pF,
sinking 2mA, sourcing 400!-,A, roughly twice that of the
8086), this bus may not require additional buffering in
many small systems. If data buffers are not used in the
system, take steps to prevent bus contention between the
80186 and the devices directly connected to the 80186
data bus. Since the 80186 floats the address/data bus before activating any command lines, the only requirement
on a directly connected device is that it floats its output
drivers after a read BEFORE the 80186 begins to drive
address information for the next bus cycle (consider the
minimum time from RD* inactive until addresses active
for the next bus cycle (tRHAV ) which has a minimum value
of 8Sns). If the memory or peripheral device cannot disable its output drivers in time, data buffers will be required to prevent both the 80186 and the peripheral or
memory device from driving these lines concurrently.
Note, this parameter is unaffected by the addition of wait
states. Data buffers solve this problem because their output float times are typically much faster than the 80186
required minimum.

CONTROL SIGNALS

The 80186 directly provides the control signals RD*,
WR*, LOCK*, and TEST*. In addition, the 80186 provides the status signals SO*-S2 * and S6 from which all
other required bus control signals can be generated.

If buffers are required, the 80186 provides DEN* (Data
ENable) and DT/R* (Data Transmit/Receive) signals to
simplify buffer interfacing. The DEN* and DT/R * signals
are activated during all bus cycles, whether or not the
cycle addresses buffered devices. The DEN* signal is
driven low whenever the processor is either ready to receive data (during a read) or when the processor is ready
to send data (during a write); that is, any time during an

RD* ANDWR*

The RD* and WR * signals strobe data to or from memory
or lIO space. The RD* signal is driven low off the beginning of T2, and is driven high off the beginning of T4
during all memory and lIO reads (see Figure 2-9). RD*
2-29

210912-001

80186/80188 CPU

80186 SIGNALS
AD8-D15
DEN
BUFFERED

8286

8
A

~

8

J)

OE

r--

DEVICES

B

r

08AD15

T
BUFFERED

SELECT

DATA
BUS

8288

8
ADO- AD7

A

8

OE

B

00-

r---"L--. 07

T

DT/A

/8
//8
r

UNBUFFERED

}

DATA
BUS

Figure 2·8 Example 80186 Buffered/Unbuffered Data Bus

Figure 2-10). If this approach is used, the 52* signal will
required latching, since the 52* signal (like 50* and 51 *)
goes to a passive state well before the beginning of T4
(where RD* goes inactive). If 52* was directly used for
this purpose, the type of read command (I/O or memory)
could change just before T4 as 52* goes to the passive
state (high). The status signals may be latched using ALE
in an identical fashion as is used to latch the address signals (often using the spare bits in the address latches).

will not become active until the 80186 has ceased driving
address information on the address/data bus. Data is sampled into the processor at the beginning of T4. RD* will
not go inactive until the processor's data hold time (IOns)
has been satisfied.
Note that the 80186 does not provide separate I/O and
memory RD* signals. If separate I/O read and memory
read signals are required, they can be synthesized using
the 52* signal (which is low for all I/O operations and
high for all memory operations) and the RD* signal (see

CLOCK
OUT
ADOAD15

1.
2.
3.
4.
5.

tClAZ: Clock low until address float=35 ns max
tClRl: Clock low until RD active = 70 ns max
t AZRl : Address float until RD active = 0 ns min
t DVCl : Data valid until clock low (data input set-up time) = 20 ns min'
tClDX: Clock low until data invalid (data input hold time from clock) = 10
ns min'
6. tClRH: Clock low until RD high = 10 ns min
7. tRHAV: RD high until addresses valid = 85 ns min
_
8. tRHDX: Read high until data invalid (data input hold from RD) = 0 ns min'
, Input requirements of 80186, all others are output characteristics

Figure 2·9 Read Cycle Timing
2-30

210912-001

80186/80188 CPU

LATCH

--------I D
Qr---~------~~

ALE --------I STB

RD --------------------------~~~~

Figure 2·10 Generating 1/0 and Memory Read Signals

Often the lack of separate liD and memory RD* signal is
not important in an 80186 system. Each of the 80186 chip
select signals will respond on only one of memory or liD
accesses (the memory chip selects respond only accesses
to memory space; the peripheral chip selects can respond
to accesses to either I/O or memory space, at programmer
option). Therefore, the chip select signal enables the external device only during accesses to the proper address in
the proper space.

applications, a DRAM controller (such as the Intel 8207
or 8203) solves this problem while with iRAMs this problem may be solved by placing cross-coupled NAND gates
(S-R latch) between the CPU and the iRAMs on the WR*
line (see Figure 2-12). This S-R latch will delay the active
going edge of the WR * signal to the iRAMs by a clock
phase, allowing valid data to be driven onto the data bus.
STATUS LINES

The WR * signal is also driven low off the beginning of T2
and driven high off the beginning of T4. Like the RD*
signal, the WR* signal is active for all memory and liD
writes, and also like the RD* signal, separate liD and
memory writes may be generated using the latched S2 *
signal along with the WR* signal (see Figure 2-11). More
importantly, however, is the active going edge of write. At
the time WR * makes its active (high to low) transition,
valid write data is NOT present on the data bus. When
using this signal as a write enable signal for DRAMs and
iRAMs consider that both of these devices require that the
write data be stable on the data bus at the time of the
inactive to active transition of the WE* signal. In DRAM

T,

The 80186 provides three status outputs which are used to
that indicate the type of bus cycle currently being executed. These signals go from an inactive state (all high) to
one of seven possible active states during the T state immediately preceding T1 of a bus cycle (see Figure 2-13).
The possible status line encodings and their interpretations are given in Table 2-18. The status lines are driven
to their inactive state in the T state (T3 or Tw) immediately preceding T4 of the current bus cycle.
The status lines may be directly connected to an 8288 bus
controller, which can be used to provide local bus control

T3

ADO·
AD15 __~~~~J~______+-~~

__~~____~~'\-~~___

\Vii
I
I

I

I

I

1. tCLOV: Clock low until data valid = 44 ns max
2. tCVCTV: Clock low until WR active = 70 ns max
3. tCVCTX: Clock low until WR inactive = 55 ns max
4. tCLOOX: Clock high until data invalid = 10 ns max

5. WR inactive until data invalid = t CLCL min - t CVCTX + tCLDOX
= 125 -

55 + 10

= 80 ns

Figure 2·11 Write Cycle Timing
2-31

210912·001

80186/80188 CPU

CLKOUT --------~r-~

DELAYED
WRITE
(DATA VALID
ON LEADING EDGE)

Figure 2·12 Synthesizing Delayed Write from the 80186

T, or
Tw

T,

T.

CLOCK
OUT
STATUS

ACTIVE
STATUS

INFO

I

T,or

INACTIVE
STATUS
T,

T.

Tw

CLOCK
OUT
STATUS

ACTIVE
STATUS

ACTIVE
STATUS

LINES

Figure 2·13 Active·lnactive Status Transitions
Table 2·18 80186 Status Line Interpretation

S2

S1

S9

0
0
0
0
1

0
0

0

I
I

0
1
0
1
0
1

I

0
0

1
1

1

I

I

Operation

80186
8288

interrupt acknowledge
read I/O
write I/0
halt
instruction fetch
read memory
write memory
passive

SO-52

SO-52
BUS CONTROL

CLOCK
OUT

SIGNALS
CLK

Figure 2·14 80186/8288 Bus Controller
Interconnection
signals or MULTIBU5 control signals (see Figure 2-14).
Use of the 8288 bus controller does not preclude the use
of the 80186 generated RD*, WR* and ALE signals,
however. The 80186 directly generated signals may be
used to provide local bus control signals, while an 8288
provides MULTIBU5 control signals, for example.

The 80186 provides two additional status signals: 56 and
57. 57 is equivalent to BHE* (refer to Volume I of this
User's Guide) and appears on the same pin as BHE*.
BHE*/57 changes state, reflecting the bus cycle about to
2-32

210912·001

80186/80188 CPU

be run, in the middle of the T state (T4 or Ti) immediately
preceding Tl of the bus cycle. This timing means that
BHE*/S7 does not need to be latched, i.e., it may be used
directly as the BHE* signal. S6 provides information concerning the unit generating the bus cycle. It is time multiplexed with A19, and is available during T2, T3, T4, and
Tw. In the 8086 family, all central processors (e.g., the
8086, 8088, and 8087) drive this line low, while all I/O
processors (e.g., 8089) drive this line high during their
respective bus cycles. Following this scheme, the 80186
drives this line low whenever the bus cycle is generated by
the 80186 CPU, but drives it high when the bus cycle is
generated by the integrated 80186 DMA unit. This process allows external devices to distinguish between bus cycles fetching data for the CPU from those transferring
data for the DMA unit.

Figure 2-15 Circuit Holding LOCK" Active
Until Ready is Returned

executed. The LOCK prefix may be executed well before
the processor is prepared to perform the locked data
transfer. This process activates the LOCK* signal before
the first LOCKED data cycle is performed. Since LOCK*
is active before the processor requires the bus for the data
transfer, opcode pre-fetching can be LOCKED. However,
since the 80186 does not activate the LOCK * signal until
the processor is ready to actually perform the locked
transfer, locked pre-fetching will not occur with the
80186.

The three other status signals, S3, S4, and S5, available
on the 8086 are not provided on the 80186. Together, S3
and S4 indicate the segment register from which the current physical address derives. S5 indicates the state of the
interrupt flip-flop. On the 80186, these signals will always be low.
TEST" AND LOCK"

The LOCK* signal does not remain active until the end of
the last data cycle of the locked transfer; this may cause
problems in some systems if, for example, the processor
requests memory access from a dual ported RAM array
and is denied immediate access (because of a DRAM refresh cycle, for example). When the processor finally
gains access to the RAM array, it may have already
dropped its LOCK* signal. This allows the dual port controller to give the other port access to the RAM array
instead. Figure 2-15 illustrates an example circuit which
can be used to hold LOCK* active until a RDY has been
received by the 80186.

The 80186 provides a TEST* input and a LOCK* output.
The TEST* input is used in conjunction with the processor WAIT instruction. TEST* is typically driven by a
processor extension (like the 8087) to indicate whether it
is busy. Then, by executing the WAIT (or FWAIT) instruction, the central processors may be forced to temporarily suspend program execution until the processor
extension indicates that it is idle by driving the TEST*
line low.
The CPU drives LOCK* output low whenever the data
cycles of a LOCKED instruction are executed. A
LOCKED instruction is generated whenever the LOCK
prefix occurs immediately before an instruction. The
LOCK prefix is active for the single instruction immediately following the LOCK prefix. This signal indicates to
a bus arbiter (e.g., the 8289) that a series of locked data
transfers is occurring. The bus arbiter should not release
the bus while locked transfers are occurring. The 80186
will not recognize a bus HOLD, nor will it allow DMA
cycles to be run by the integrated DMA controller during
locked data transfers. Locked transfers are used in multiprocessor systems to access memory based semaphore
variables which control access to shared system resources
(refer to Intel Application Note AP-106, "Multiprogramming with the iAPX88 and iAPX86 Microsystems," by
George Alexy, September 1980).

MULTIBUS® APPLICATIONS

The 8288 and 8289 are the bus controlled and multimaster bus arbitration devices used with the 8086 and
8088. Because the 80186 bus is similar to the 8086 bus,
they can be directly used with the 80186 (see Figure
2-16).
The 8288 bus controller generates control signals (RD*,
WR*, ALE, DTlR*, DEN, etc.) for an 8086 maximum
mode system. It derives its information by decoding status
lines SO*-S2 * of the processor. Because the 80186 and the
8086 drive the same status information on these lines, the
80186 can connect directly to the 8288 just as in an 8086
system. Using the 8288 with the 80186 does not prevent
using the 80186 control signals directly. Many systems
require both local bus control signals and system bus control signals. In this type of system, the 80186 lines could
be used as the local signals, with the 8288 lines used as
the system signals.

On the 80186, the LOCK* signal goes active during Tl of
the first DATA cycle of the locked transfer. It is driven
inactive three T states after the beginning of the last DATA
cycle of the locked transfer. On the 8086, the LOCK*
signal is activated immediately after the LOCK prefix is
2-33

210912-001

80186/80188 CPU

the upper and lower byte of a 16-bit word each have a
unique byte address by which they may be individually
accessed, even though they share a common word address
(see Figure 2-17).

TO MULTI-MASTER BUS
ADDRESS LATCHES &
DATA BUFFERS

All bytes with even addresses (AO = 0) reside on the lower
8 bits of the data bus, and all bytes with odd addresses
(AO =1) reside in the upper 8 bits of the data bus. Whenever an access is made to only an even byte, AO is driven
low, BHE* is driven high, and the data transfer occurs on
00-07 of the data bus. Whenever an access is made to
only an odd byte, BHE* is driven low, AO is driven high,
and the data transfer takes place on 08-016 of the data
bus. If a word access is performed to an even address,
both AO and BHE* are driven low and the data transfer
takes place over the entire 16-bit data bus (00-015).

80186
8288

so-

so-

52

S2

ALE
DEN
DT/R

f--

CLK

CLOCKOUT
LCS UCS PCSO

~

8289

L...,..

SO-

52
SYSB/RESB

"----0. CLK

Word accesses are made to the addressed byte and the
next higher numbered byte. Two byte accesses must be
performed if a word access is performed to an odd address, the first to access the odd byte at the first word
address on 08-015, and the second to access the even
byte at the next sequential word address on 00-07. For
example, byte 0 and byte 1 can be individually accessed
(read or written) in two separate bus cycles (byte accesses) to byte addresses 0 and 1 at word address 0 (see
Figure 2-17). They may also be accessed together in a
single bus cycle (word access) to word address O. However, two word access bus cycles are required to address
1. The first cycle accesses byte 1 at word address 0 (note
byte 0 will not be accessed), and the second cycle accesses byte 2 at word address 2 (note byte 3 will not be
accessed). Therefore, to maximize processor performance, all data should be located at even addresses.

Figure 2·16 80186/8288/8289
Interconnection

NOTE
In an 80186 system, the 8288-generated ALE
pulse occurs later than that of the 80186 itself.
In multi-master bus systems, use the 8288 ALE pulse to
strobe the addresses into the system bus address latches to
insure that the address hold times are met.
The 8289 bus arbiter arbitrates the use of a multi-master
system bus among various devices each of which can become the bus master. This component also decodes status
lines 80*-82 * of the processor directly to determine when
the system bus is required. When the system bus is required, the 8289 forces the processor to wait until it has
acquired control of the bus, then it allows the processor to
drive address, data and control information onto the system bus. The system determines when it requires system
bus resources by an address decode. Whenever the address being driven coincides with the address of an
on-board resource, the system bus is not required and
thus will not be requested. The circuit shown in Figure
2-16 factors the 80186 chip select lines to determine when
the system bus should be required, or when the 80186
request can be satisfied using a local resource.

When byte reads are made, the data returned on the half
of the data bus not being accessed is ignored. When byte
writes are made, the data driven on the half of the data bus
not being written is indeterminate.

2.5.5 Memory and 110 Peripherals Interface
The 80186 uses the same techniques for interfacing memory (i.e., static RAM, dynamic RAM, EPROM, and
ROM) as used for the 8086. Before continuing with this
section, review the discussions regarding memory interface in paragraphs 1.5.4.

MEMORY INTERFACE

2.5.4 Data Transfer

The 80186 includes a chip select unit that generates hardware chip select signals for memory and I/O accesses
generated by the 80186 CPU and OMA units. This unit is
programmable to fulfill the chip select requirements (in
terms of memory device or bank size and speed) of most
small and medium sized 80186 systems.

During clock cycles T2, T3, Tw, and T4 of a bus cycle the
m}lltiplexed address/data bus becomes a 16-bit data bus.
Data transfers on this bus may be either in bytes or in
words. All memory is byte addressable. This means that
2-34

210912-001

80186/80188 CPU

r.: 16_BITS:~
8 BITS--I..-8 BITS

WORD ADDRESS
4

5

4

3

2

0

0
08015

DO07

I~UM"'~
IN BYTE FIELD

80186 SIGNAL
CONNECTIONS

Figure 2-17 Physical Memory Byte/Word Addressing
Chip selects are driven for internally generated bus cycles
only. Any cycles generated by an external unit (e. g., an
external DMA controller) will not cause the chip selects
to go active. Therefore, any external bus masters must be
responsible for their own chip select generation. Also,
during a bus HOLD, the 80186 does not float (i.e., tristate) the chip-select lines. Therefore, logic must be included to enable the devices to which the external bus
master wishes to access (see Figure 2-18).

to the Al address line from the 80186, NOT to the AO
line. Also, AO signals a data transfer on only the lower 8
bits of the 16-bit data bus. The EPROM outputs are connected directly to the address/data inputs of the 80186,
and the 80186 RD* signal is used as the OE* for the
EPROMs.
The chip select output of the 80186 drives the chip enable
of the EPROM directly. For this configuration, access
time for the EPROMs is calculated as follows:

ROM and EPROM Interface
Time from address:

The Intel 2764 EPROM provides one of the simplest
memory interfaces to implement with the 80186. The address is latched using the address generation circuit (see
Figure 2-19). The AO line of each EPROM is connected

!cLAY + (3 + N)*tcLcL - t[YQy(8282) -tDYCL
= 375 + (N * 125) -44-30 -20
=281 +(N * 125) ns

80186 CHIP SELECT~ MEMORY or I/O
EXTER"N'A"LL~Y~G~E=N~E=R~AT~E~D"'CHIP SELECT ---~ DEVICE CHIP SELECT

Figure 2-18 80186/External Chip Select/Device Chip Select Generation

2764

CE
13
A13
A1
RD

/

/13
/

~

A12
AO
OE
00-07

f
ADO-AD7
AD8-AD15

I

/8

2764

' - CE

r-

A12
AO
OE
00-07

/8

Figure 2-19 Example 2764/80186 Interface
2-35

210912-001

80186/80188 CPU

Time from chip select:

used to afford a much simpler interface with no loss of
performance. The iRAM automatically selects between
these modes by the nature of the control signals.

(3 + N)*tCLC - tCLCSV - tOVCL
= 375 + (N * 125) -66-20
=289+(N * 125) ns

The 2186 is a leading edge triggered device, therefore,
address and data information are strobed into the device
on the active going (high to low) transition of the command signal. This action requires that both CE* and WR*
be delayed until the address and data driven by the 80186
are guaranteed stable. Figure 2-20 shows a simple circuit
which can be used to perform this function. ALE CANNOT be used to delay CE* if addresses are not latched
externally. This would violate the address hold time required by the 2186 (30ns).

Time from RD* (OE*):
(2 + N)tcLCL - tCLRL - tOVCL
=250+(N * 125)-70-20
=160+(N * 125) ns
where:
tcLAV
tcLCL
t,vov
tOVCL
tcLCSV
tCLRL
N

time from clock low in T1 until address are
valid
clock period of processor
time from input valid of 8282 until output valid
of 8282
186 data valid input setup time until clock low
time ofT4
time from clock low in T 1 until chip selects are
valid
time from clock low in T2 until RD* goes low
number of wait states inserted

Since the 2186 devices are RAMs, data bus enables BHE*
and AO MUST be used to factor either the chip enables or
write enables of the lower and upper bytes of the 16-bit
RAM memory system. If this is not done, all memory
writes, including single byte writes, will write to both the
upper and lower bytes of the memory system. The example system shown in Figure 2-20 uses BHE* and AO as
factors to the 2186 CE * because both of these signals (AO
and BHE*) are valid when the address information is
valid from the 80186.

As indicated in the preceding calculations, 250ns
EPROMs must be used for zero wait state operation. The
only significant parameter not included in the preceding
calculations is t RHAV ' This is the time from RD* inactive
(high) until the 80186 begins driving address information.
This parameter is typically 85ns to meet the 2764-25
(250ns speed selection) output float time requirement
(85ns). If slower EPROMs are used, a discrete data buffer
MUST be inserted between the EPROM data lines and the
address/data bus. This is required since these devices may
continue to drive data information on the multiplexed
addressl data bus when the 80186 begins to drive address
information for the next bus cycle.

The 2186 requires a certain amount of recovery time between the time chip enable goes inactive and the chip enable going active to insure proper operation. For a
"normal" cycle (a read or write), this time is tEHEL = 40
ns. The 80186 chip select lines go inactive soon enough at
the end of a bus cycle to provide the required recovery
time even if two consecutive accesses are made to the
iRAMs. If the 2186 *CE is asserted without a command
signal (WE* or OE*), a false memory cycle (FMC) is
generated. Whenever an FMC is generated, the recover
time is much longer; another memory cycle must not be
initiated for 200ns. As a result, if the memory system will
generate FMCs, CE* must be taken away in the middle of
the T state (T3 or Tw) immediately preceding T4 to insure
that two consecutive cycles to the iRAM will not violate
this parameter. Status going passive (all high) can be used
for this purpose. These lines will all go high during the
first phase of the next to last T state (either T3 or Tw) of a
bus cycle.

RAM Interface

Randon access memory (RAM) devices are interfaced to
the 80186 very much as they are interfaced to the 8086.
The Intel 2186 iRAM is a memory device ideally suited
for 80186 applications (see Figure 2-20). This RAM device incorporates many requisite system features, including low power dissipation, automatic initialization,
extended cycle operation, and two-line bus control to
eliminate bus contention. The 2186 almost ideally
matches the 80186 because of its large scale integration
and the fact that it does not require address latching.

Since the 2186 is a dynamic device, it requires refresh
cycles to maintain data integrity. The circuits that generate these refresh cycles are integrated within the 2186. To
support the required refresh cycles the 2186 has a ready
line which is used to suspend processor operation if a
processor RAM access coincides with an internally generated refresh cycle. The ready line is an open collector
output, allowing many devices to be wire OR'ed together,
since more than one device may be accessed at a time.
These lines are also normally ready, which means that
they will be high whenever the 2186 is not being accessed, i.e., they will only be driven low if a processor
request coincides with an internal refresh cycle. Therefore, the ready lines from the iRAM must be factored into

The 2186 is internally a dynamic RAM integrated with
refresh and control circuits. It operates in two modes:
pulse mode and late cycle mode. Pulse mode is entered if
the CE* input signal to the device is low for a maximum
of 130ns, and requires the command input (RD* or WE*)
to go active within 90ns after CE*. Because of these requirements, interfacing the 80186 to the 2186 in pulse
mode would be difficult. Instead, the late cycle mode is
2-36

210912·001

80186/80188 CPU

CLKOUT -,~---ir\-'>----r-_
LCS

BHE -------------4---------~~
AO
CLKOUT

----------------L../
---.:------j-"\.-______

WR
2186

2186

CE

CE

WE

WE

~ --------------------~~ OE

OE

4.7K

AO-A12

AO-A12
ROY

AROY

00-07

:g~

_______________

8

A01- 13

~~L_~---~~~-~~~_~
A013

AD8AD15

Figure 2-20 Example 2186/80186 Inter1ace
the 80186 RDY circuit only during accesses to the iRAM
itself. Since the 2186 refresh logic operates asynchronously to the 80186, this RDY line must be synchronized
for proper operation with the 80186, either by the integrated ready synchronizer or by an external circuit. The
example circuit uses the integrated synchronizer associated with the ARDY processor input.

3 * tCLCL - tcLCSV - (TTL delay) - tovCL
= 375 -66- 30-20ns
=258 ns
where:
tcLCL
tcLCsv

tOVCL

The 2186 ready lines are active unless a processor access
coincides with an internal refresh cycle. These lines must
go inactive after a cycle is requested in time to insert wait
states into the data cycle. The 2186 drives this line low
within 50ns after CE * is received, which is early enough
to force the 80186 to insert wait states if they are required.
Of primary concern in this case is that the ARDY line be
driven not active before its setup time in the middle of T2.
This setup time is required by the nature of the 80186
asynchronous ready synchronization circuits. Since the
2186 RDY pulse may be as narrow as 50ns, if ready was
returned after the first stage of the synchronizer, and subsequently changed states within the ready setup and hold
time of the high to low going edge of the CPU clock at the
end of T2, improper operation may occur.

CPU clock cycle time
time from clock low in T1 until chip selects are
valid
= 80186 data in setup time before clock low in T4

The data valid from OE* active is less than lOOns, and is
therefore not an access time limiter in this interface. Additionally, the 2186 data float time from RD* inactive is
less than the 85ns 80186 imposed maximum. The CE*
generation circuit shown in Figure 2-20 provides an address setup time of at least 11 ns, and an address hold time
of at least 35ns (assuming a maximum two level TTL delay ofless than 30ns).
Write cycle address setup and hold times are identical to
the read cycle times. This circuit shown provides at least
Ilns write data setup and lOOns data hold time from
WE*, easily meeting the Ons setup and 40ns hold times
required by the 2186.
For more information concerning 2186 timing and interfacing refer to the 2186 data sheet in the Memory Components Handbook (Intel Order Number: 210830-004, or

The example interface shown in Figure 2-20 has a zero
wait state RAM read access tie from CE* of:
2-37

210912-001

80186/80188 CPU

"
8203
MCS1
MCSO

J

'17/

A17-A1

J

SEL WR
AOA16, WE ~
BO
SACK

1

/

AROY

r-

~
220
UPPER
BYTE WE

220
LOWER
BYTE WE

DRAMS,

XACK
RO

f
AOO-A015

/-

f

010-15
000-15

8282
~

000-7
010-7

OE

./
~

I-

STB

-

000-7

-

8282

OE

'-----

STB

010-7

-

Figure 2·21 Example 8203/DRAM/80186 Interface
the Intel Application Note AP-132, "Designing Memory
systems with the 8Kx8 iRAM" by John Fallin and
William Righter (June 1982).

zation time, the 8203 should be used with the highest
speed crystal that will maintain DRAM compatibility.
Even if a 25 MHz crystal is used (the maximum allowed
by the 8203), two wait states will be required by the example circuit when using 150ns DRAMs with an 8 MHz
80186, three wait states if 200ns DRAMs are used (see
Figure 2-22).

8203 Dynamic RAM Interface
The Intel 8203 Dynamic RAM Controller is designed specifically to provide all of the signals necessary (i.e., control, address multiplexing, and refresh generation) to use
2164, 2117 or 2118 dynamic RAMs in microcomputer
systems. As such, it is ideally suited to 80186 applications. For an application example of an 80186 used with
the 8203 and interfaced with 64K dynamic RAMs (see
Figure 2-21).

The entire RAM array controlled by the 8203 can be selected by one or a group of the 80186 provided chip selects. These chip selects can also be used to insert the wait
states required by the interface.
Since the 8203 is operating asynchronously to the 80186,
the RDY output of the 8203 (used to suspend processor
operation when a processor DRAM request coincides
with a DRAM refresh cycle) must be synchronized to the
80186 (the 80186 ARDY line provides the necessary
ready synchronization). The 8203 ready outputs operate
in a normally not ready mode, that is, they are only driven
active when an 8203 cycle is being executed, and a refresh cycle is not being run. This process differs fundamentally from the normally ready mode used by the 2186

All 8203 cycles are generated from control signals (RD*
and WR*) provided by the 80186. These signals will not
go active until T2 of the bus cycle. In addition, since the
8203 clock (generated by the internal crystal oscillator of
the 8203) is asynchronous to the 80186 clock, all memory
requests by the 80186 must be synchronized to the 8203
before the cycle will be run. To minimize this synchroni2-38

210912-001

80186/80188 CPU

T,

Tw

T,

T,

186 ___~~+-,.,

RD
8203 _ _ _ _ _ _ _ _ _ _~--...,

RAS

-+_____+ __~--_I_...

8203 _ _

CAS
RAM ""~~~""~~~""~~""~~~~~\r----4~-------DATA ~~~~~~~~~~~~~~~~~~'~__-+~_________

LATCH
DATA

~""~mm~mmmm~~~~~~~~~~~~~r~~--------~~~~~~~~~~~~~~~~~~~U~

__~_________

1. tCLEL: Clock low until read low = 70 ns max
2. tCR: Command active until RAS = 150 ns max'
3. tcc: Command active until CAS = 245 ns max'
4. tCAC: Access time from CAS = 85 ns max
5. tISOU: Input to output delay = 30 ns max
6. t OVCL: Data valid to clock low (data in set up) = 20 ns min
Total Access Time = 70 + 245 +85 +30 +20 = 450 ns (3.6 T-states)

(j)

&@ are 186 specs

® & @ are 8203 specs
@
@

is a 2164A-15 spec
is on 8282 spec

'Assumes 25MHz
8203 operation

Figure 2·22 8203/2164A·15 Access Time Calculation
iRAMs. The 8203 SACK* signal is presented to the
80186 only when the DRAM is being accessed. Notice
that the SACK* output of the 8203 is used, rather than the
XACK * output. Since the 80186 will insert at least one
full CPU clock cycle between the time RDY is sampled
active, and the time data must be present on the data bus,
using the XACK* signal would insert unnecessary additional wait states, since it does not indicate ready until
valid data is available from the memory. (For more information about 8203/DRAM interfacing and timing, refer
to the 8203 data sheet, or Intel Application Note AP97 A,
"Interfacing Dynamic RAM to iAPX86/88 Systems Using the Intel 8202A and 8203" by Brad May, April 1982).

when programmed to run asynchronously it inserts the
necessary synchronization circuits for RD*, WR *, PE*,
and PCTL inputs.
The 8208 is capable of addressing 64K and 256K dynamic
RAMs. It directly supports the 2164A RAM family or
any RAM with similar timing requirements. Figure 2-24
shows the connection of the processor address bus to the
8208 using the different RAMs.
The 8208 divides memory into two banks with each bank
having its own Row Address Strobe (RAS*) pair and
Column Address Strobe (CAS*) pair. This organization
permits RAM cycle interleaving. RAM cycle interleaving
overlaps the start of the next RAM cycle with the RAM
precharge period of the previous RAM cycle. Hiding the
precharge period of one RAM cycle behind the data access period of the next RAM cycle optimizes memory
bandwidth and is effective as long as successive RAM
cycles occur in the alternate banks. Successive data accesses to the same bank cause the 8208 to wait for the
precharge time of the previous RAM cycle. The exception to this is when the 8208 is programmed in an iAPX
186 synchronous configuration consecutive read cycles to
the same bank do not result in additional wait states, zero
wait state reads result.

8208 Dynamic RAM Interface
The Intel 8208 Dynamic RAM Controller is designed to
address, refresh and directly drive 64K and 256K Dynamic RAM's in iAPX 186 and iAPX 188 systems. The
8208 contains the control circuits capable of supporting
one of several possible interface bus structures (see Figure 2-23). It may be programmed to run synchronous or
asynchrouous to the processor clock. The 8208 has been
optimized to run synchronously with the 801861188 and

2-39

210912-001

80186/80188 CPU

8208/AACK - - _ _ , - - , .

Slil-----.\
51 t--------~

:g~:~

Sl
S2~-.+-I--+-----~

ADDR/DATA

SYNCHRONOUS-STATUS INTERFACE
ADDRESS
DECODE 1------,./

ASYNCHRONOUS-STATUS INTERFACE

ASYNCHRONOUS-COMMAND INTERFACE

SYNCHRONOUS-COMMAND INTERFACE

Figure 2·23 8208 Dynamic RAM Controller Interfaces
h. Refresh

If all of the RAM banks are not occupied, the 8208 reassigns the RAS* and CAS* strobes to allow wider data
words without increasing the loading on the RAS* and
CAS* drivers. Table 2-19 shows the bank selection decoding and the horizontal word expansion, including RAS*
and CAS* assignments. For example, if only one RAM
bank is occupied, the two RAS* and CAS* strobes are
activated with the same timing. Program bit RB is not
used to check the bank select input BS. System design
must protect from "illegal", non-existent banks of memory by deactivating the PE input when addressing an "illegal", non-existent bank of memory. The 8208 adjusts
and optimizes either the fast or slow RAMS as
programmed.

The 8208 provides an internal refresh interval counter and
a refresh address counter to allow the 8208 to refresh
memory. It will refresh 128 rows every 2 milliseconds or
256 rows every 4 milliseconds. This allow RAM refresh
options to be supported. Also, the 8208 has the ability to
refresh 256 row address locations every 2 milliseconds
via the Refresh Period programming option. the 8208
may be programmed for any of five refresh options.
These are:
1. Internal refresh only;
2. External refresh with failsafe protection;
3. External refresh without failsafe protection;

a_ 8208 Memory Initialization

4. Burst Refresh modes;
5. No Refresh.

After programming is complete, the 8208 performs eight
RAM "wake-up" cycles to prepare the dynamic RAM for
proper device operation. During the "warm-up" some of
the RAM interface parameters may not be met, but this
should not harm the dynamic RAM array.

The refresh time interval may be decreased by 10%,20%
or 30%. This option allows the 8208 to compensate for
reduced clock frequencies. An additional 5 % interval
2-40

210912-001

80186/80188 CPU

TRESP = PROG + TPREP
where:

(NOTE 1)
AH8

TPROG
TPREP

A11-A19
AHO-AH7

= (40)(TCLCL) which is programming time
= (8)(32)(TCLCL) which is RAM warm-up
time

if TCLCL = 125 nsec then TRESP = 37 usec
8208
AL8

d. Reset
The 8208 uses the falling edge of the asynchronous RESET input to directly sample the logic levels of the PCTL,
RFRQ, and POI inputs. The internally synchronized falling edge of reset is used to begin programming operations
(shifting the contents of the external shift register, if
needed, into the POI input).

eso
256K RAM
INTERFACE

64K RAM
INTERFACE

NOTES:

The 8208 will register bu t not respond to command and
status inputs until programming is completed. A simple
means of preventing commands or status from occurring
this period is to differentiate the system reset pulse to obtain a smaller reset pulse for the 8208. The total time of
the 8208 reset pulse and the 8208 programming time must
be less than the time before the first command the CPU
issues in systems that alter default port synchronization
programming bit (default is synchronous interface). Differentiated reset is unnecessary when the default synchronization programming is used.

1. Unassigned address input pins should be strapped high
or low.
2. AO along with BHE are used to select a byte within a
processor word.
3. low order address bits are used as bank select inputs so
that consecutive memory access requests are to
alternate banks allowing bank interleaving of memory
cycles.

Figure 2-24 8208 Processor Address Interfaces

The differentiated reset pulse would be shorter than the
system reset pulse by at least the programming period required by the 8208. The differentiated reset pulse first
resets the 8208, and system reset would reset the rest of
the system. While the rest of the system is still in reset,
the 8208 completes its programming. Figure 2-25 illustrates a circuit to accomplish this task. Within four clocks
after RESET goes active, all the 8208 outputs will go
high, except for AOO-2, which will go low.

shortening is built-in in all refresh interval options to compensate for lock variations and non-immediate response to
the internally generated refresh request.
c_ External Refresh Requests After RESET
External refresh requests are not recognized by the 8208
until after it is finished programming and preparing memory for access. Memory preparation includes 8 RAM cycles to prepare and ensure proper dynamic RAM
operation. The time it takes for the 8208 to recognize a
request is shown as follows.

2.5.6 Interpreting the 80186/80188 Bus
Timing Diagrams

Table 2-19 Bank Selection Decoding and Word
Expansion
Program
Bit
RB

Bank
Input
BS

0

0

'AAS'o l'

0

1

Illegal

1

0

1

1

RASo, CAS'o to Bank 0
~1' CAS 1 to Bank 1

The 80186 bus and the 8086 bus are very similar in structure. Both include a multiplexed address/data bus, along
with various control and status lines. Table 2-20 lists the
80186 bus signals by function and name. Each bus cycle
requires a minimum of 4 CPU clock cycles along with
any number of wait states required to accommodate the
speed access limitations of external memory or peripheral
devices. The bus cycles initiated by the 80186 CPU are
identical to those initiated by the 80186 integrated DMA
unit. The following paragraphs describe the 80186 bus
timing with all timing values given for an 8MHz 80186.
Any future speed selections for the 80186 may have different values for the various parameters.

8208

AAS/eA$ Pair Allocation

CASo

1to Bank 0

2-41

210912-001

80186/80188 CPU

SYSTEM

r--------,

8208

.1----- t1~

RE~

L--

=-1

RES~_______________

t1 PROGRAMMING TIME OF 8208

-(!}-1~

1-1

I
I
I

..·1

RESET

DIFFERENTIATED RESET

(!}2

(LOW

(HIGH

PHASE)

PHASE)

L

Figure 2-26 Single T-State

NOTES:
1. Required only when the port synchronization option(s) is
altered from its initial default value.
2.

diately before TI (either T4 or T j ). Because information
concerning an upcoming bus cycle occurs during the
T-state immediately before the first T-state of the actual
bus cycle, two different types of T4 and T j can be generated. One where the T-state is immediately followed by a
bus cycle and one where the T-state is immediately followed by an idle T state.

Vee must be stable before system reset is activated when
using this circuit.

Figure 2-25 8208 Differentiated Reset Circuit
Eaeh 80186 clock cycle (called "T" states) are numbered
sequentially T 1, T2 , T 3 , Tw and T4. Additional idle T
states (T) can occur between T4 and TI when the processor requires no bus activity (instructions fetches, memory
writes, 110 reads, etc.). The ready signals control the
number of wait states (Tw) inserted in each bus cycle. This
number can vary from zero to positive infinity.

During the first type of T4 or Tjo status information concerning the upcoming bus cycle is generated. This information will be available no later than tcHsv (55 ns) after
the low-to-high transition of the 80186 clock in the middle
of the T state. During the second type of T4 or Tjo the
status outputs remain inactive (high), since no bus cycle is
to be started. This means that the decision per the nature
of a T 4 or T j state (Le., whether it is immediately followed
by a T j or a T I) is decided at the beginning of the T-state
immediately preceding the T4 or T j (see Figure 2-13).
This has consequences for the bus latency time.

The beginning of the T state is signaled by a high to low
transition of the CPU clock. Each T state is divided into
two phases, phase 1 (or the low phase) and phase two (or
the high phase) which occur during the low and high levels of the CPU clock, respectively (see Figure 2-26).

Physical addresses are generated by the 80186 during TI
of the bus cycle. Since the address and data lines are multiplexed on the same set of pins, addresses must be
latched during T 1 if they are required to remain stable for
the duration of the bus cycle. To facilitate latching of the
physical address, the 80186 generates an active high ALE
(Address Latch Enable) signal which can be directly connected to a transparent latch's strobe input.

Different types of bus activity occur during all of the
T-states (see Figure 2-27). Address generation information occurs during T 1, data generation during T2 , T l , Tw
and T4. The beginning of a bus cycle is signaled by the
status lines of the processor going from a passive state (all
high) to an active state in the middle of the T-state imme-

Table 2-20 80186 Bus Signals

Slgn.IN.me

Function
address/data
address/status
co-processor control
local bus arbitration
local bus control
multi-master bus
ready (wait) interface
status information

ADO-ADIS
A16/S3-A19-S6,BHE/S7
TEST
HOLD,HLDA
ALE,RD,WR,DT/it,DEN
LOCK
SRDY,ARDY
SO-S2

2-42

210912-001

80186/80188 CPU

T,

T2

T,

LINES
DATA
LINES
ADDRESSI

-;--------~~~~~:J~~----~--------~----~

CONTROL ~--------~---------ft
SIGNALS
(RD,WR)

Figure 2-27 Example 80186 Bus Cycle
Addresses are guaranteed valid for no more than teLAv (44
ns) after the beginning of T I' and will remain valid at least
teLAX (10 ns) after the end of T 1 • See Figure 2-28 for
80186 physical address generation parameters. The ALE
signal is driven high in the middle of the T state (either T4
or T.) immediately preceding T I and is driven low in the
middle ofT!> no sooner than t AVAL (30 ns) after addresses
become valid. This parameter (tAVAL) is required to satisfy
the address latch set-up times of address valid until strobe
inactive. Addresses remain stable on the address/data bus
at least tLLAX (30 ns) after ALE goes inactive to satisfy
address latch hold times of strobe inactive to address
invalid.

the propagation delay through the latch rather than the
delay from the latch strobe, which is typically longer than
the propagation delay. For the Intel 8282 latch, this parameter is tIVOV , the input valid to output valid delay when
strobe is held active (high). Note that the 80186 drives
ALE high one full clock phase earlier than either the 8086
or 8288 bus controller. The 80186 also keeps ALE high
throughout the 8086 or 8288 ALE high time (i.e., the
80186 ALE pulse is wider).
A typical circuit for latching physical addresses (see Figure 2-29) uses three 8282 transparent octal non-inverting
latches to demultiplex all 20 address bits provided by the
80186. Typically, the upper 4 address bits are used only to
select among various memory components and subsystems, so when the integrated chip selects (see paragraph

Because ALE goes high long before addresses become
valid, the delay through the address latches will be mainly

T,

T2

CLOCK
OUT

ALE
AO-A19 -----...,..-t-~

NOTES:
1. tCHlH: Clock high to ALE high=35 ns max
2. tcLAv: Clock low to address valid =44 ns max
3. tCHlL: CloCk high to ALE low=35 ns max
4. tCLAx: Clock low to address invalid (address hold from clock low)=10 ns
min
5. tllAX: ALE low to address invalid (address hold from ALE)=30 ns min
6. t AVAl : Address valid to ALE low (address setup to ALE)=30 ns min

Figure 2-28 80186 Address Generation Timing
2-43

210912-001

80186/80188 CPU

186 SIGNALS
A16A19

I

/

0

STS

-

AD8AD15

A16-A19

8282

/8

I

7

~

-,

L4
7

OE

STS

ADOAD7

LATCHED ADDRESS
SIGNALS

8282

/4

/8

0

/

0

/

A8-A15

OE

8282

/8

I
STS

ALE
~

=

L.8

AO-A7

OE

Figure 2-29 Oemultiplexing the 80186 Address Bus

2.8.4) are used, these upper bits do not need to be
latched. The worst case address generation time from the
beginning of T 1 (including address latch propagation time
tIVOV of the Intel 8282) for the circuit is:

2_5_7 Wait State Generator
The 80186 provides two ready lines, a synchronous ready
(SRDY) line and an asynchronous ready (ARDY) line.
These lines signal the processor to insert wait states (Tw)
into a CPU bus cycle. Wait states allow slower devices to
respond to CPU service requests (reads or writes). They
are only inserted when both ARDY and SRDY are low
(i.e., only one of ARDY or SRDY need be active to terminate a bus cycle). Any number of wait states may be inserted into a bus cycle. The 80186 will ignore the RDY
inputs during an access to the integrated peripheral registers, and to any area where the chip select ready bits indicate that the external ready should be ignored.

tCLAV (44 ns) + t1vOV (30 ns) =74 ns
Many memory and peripheral devices may not require
addresses to remain stable throughout data transfer. Examples of these are the 80130 and 80150 operating system
firmware chips, and the 2186 8K x 8 iRAM. If a system is
entirely constructed of these types of devices, addresses
do not need to be latched. In addition, two of the peripheral chip select outputs from the 80186 may be configured
to provide latched A I and A2 outputs for peripheral register selects in a system which does not demultiplex the
address/data bus.

Since the timing between the two ready lines is different,
asynchronous ready inputs to the ARDY line are internally synchronized to the CPU clock before being presented to the processor (see Figure 2-30). Figure 2-31
illustrates an ARDY synchronization circuit. The first
flip-flop to "resolves" the asynchronous transition of the
ARDY line. It will achieve a definite high or low level
before the second flip-flop latches its output for presentation to the CPU. When latched high, it allows the level
present on the ARDY line to pass directly to the CPU;
when latched low, it forces not ready to be presented to
the CPU.

One additional signal is generated by the 80186 to address
memory. This is BHE* (Bus High Enable). This signal,
along with AO, is used to enable byte devices connected to
either or both halves (bytes) of the 16-bit data bus. Because AO is used only to enable devices onto the lower
half of the data bus, memory chip address inputs are usually driven by address bits AI-AI9, NOT AO-AI9. This
provides 512K unique word addresses, or 1M unique
BYTE addresses. BHE* is not present on the 8-bit 80188.
All data transfers occur on the eight bits of the data bus.

With this scheme, only the active going edge of the
ARDY signal is synchronized. Once the synchronization
flip-flop has sampled high, the ARDY input directly
drives the RDY flip-flop. Since inputs to this RDY
2-44

210912-001

80186/80188 CPU

:

~

:

~

:

~

~

:

C\.OCK~
"DY~
OUT

1. No setaup or hokt times required
2. !cLARYX: Clock low to AROY Inactive (ARDY active hold ttme) - 15 ns min

:

:

~

:

~

~

~

:

CLOCK~

.:~\~

1. I ARyHCti : AROY valid until clock high (ARDY inactive set-up time to clock
high) - 20 ns min
2. No set-up or hold time required ONLY if m is guaranteed
3. !cLARY)(: Clock low to AROY inactive (AROY active hold time) - 15 ns min

~

:

~

:

~

:

~

c::~
1. tARVLCL: ARDY low to clock low (ARDY inactive set-up time to clock low) =
35 ns min
must be satisfied since synchronizing FLIP-FLOP has sampled
active
2. tARYHCH: AROY high to clock high (ARDYactive set-uptime) = 20 ns min

must be satisfied ONLY to guarantee recognition at the next clock
(Le. to guarantee synchronizing FLlp·FlOP will sampte AADY
active)
3.lcLARYX: Clock low to AROV Inactive (ARDY active hold time) "'" 15 ns

-~
OUT:

ARDY

,CD

:

:

,
I
I
t
~
t
•
I
I
t t l
I

CD LESS THAN 3S,..

CLOCK~:
T.
:
T,
:
?
:.
OUT
ARDY

~ CD

(VI

I

t

~
I

I

I

I

I

I

I

:
I
t
I

1. Less than 20 ns
2. Less than 35 ns

Figure 2·30 Valid/Invalid ARDY Transitions
flip-flop must satisfy certain setup and hold times, these
setup and hold times (tARYLCL = 35ns and tcHARYX = 15ns
respectively) must be satisfied by any inactive going transition of the ARDY line. Used in this manner, ARDY allows a slow device the greatest amount of time to respond
with a not ready after it has been selected. In a normally
ready system, a slow device must respond with a not
ready quickly after it has been selected to prevent the
,processor from continuing and accessing invalid data
from the slow device. By implementing ARDY in the
above manner, the slow device has an additional clock
phase to respond with a not ready.

If RDY is sampled active into the RDY flip-flop at the
beginning of T3 or Tw (meaning that ARDY was sampled
high into the synchronization flip-flop in the middle of aT
state, and has remained high until the beginning of the
next T state), that T state will be immediately followed by
T4. If RDY is sampled low into the RDY flip-flop at the
beginning of T3 or T2 (meaning that either ARDY was
sampled low into the synchronization flip-flop OR that
ARDY was sampled high into the synchronization
flip-flop, but has subsequently changed to low before the
ARDY setup time) that T state will be immediately followed by a wait state (Tw). Any asynchronous transition
on the ARDY line not occurring during the above times,
that is, when the processor is not "looking at" the ready
2·45

210912-001

80186/80188 CPU

ARDY
INPUT

r----------------~

I

80186

I

I

I
I

TO BUS
INTERFACE
UNIT

I c c

I

CPU

IL-CLOCK________ _

_ _ _ -.J

FROM SYNCHRONOUS
READY

1. Asynchronous Resolution Flip Flop
2. Ready Latch Flip Flop
NOTE: The second flip-flop is not actually in the circuit. It is drawn here only
to show the functional equivalent of the interface to the BIU.

Figure 2·31 Asynchronous Ready Circuits for the 80186
lines, will not cause CPU malfunction. Again, for ARDY
to force wait states to be inserted, SRDY must be tied low,
since they are internally ORed together to form the processor RDY signal.

2.5.8 80186 Synchronization
Many input signals to the 80186 are asynchronous, that is,
a specified set up or hold time is not required to insure
proper functioning of the device. Associated with each of
these inputs is a synchronizer which samples this external
asynchronous signal, and synchronizes it to the interal
80186 clock.

The synchronous ready (SRDY) line requires that ALL
transitions on this line during T2, T3 or Tw satisfy a certain setup and hold time (tSRYCL =35 ns and tcLSRY =15 ns
respectively). If these requirements are not met, the CPU
will not function properly (see Figure 2-32). The processor looks at this line at the beginning of each T3 and Tw.
If the line is sampled active at the beginning of either of
these two cycles, that cycle will be immediately followed
by T4. If, however, the line is sampled inactive at the
beginning of either of these two cycles, that cycle will be
followed by a Tw. Any asynchronous transition on the
SRDY line not occurring at the beginning of T3 or Tw,
that is, when the processor is not "looking at" the ready
lines will not cause CPU malfunction.

SYNCHRONIZER REQUIREMENTS
Every data latch requires a certain set up and hold time in
order to operate properly. At a certain window within the
specified set up and hold time, the latch will try to latch
the data. If the input makes a transition within this window, the output cannot attain a stable state within the
given output delay time. The size of this sampling

CLOCK

OUT
SRDY
1. Decision: Not ready, T-state will be followed by a wait state
2. Decision: Ready, T-state will not be followed by a wait state
3. tSRYCl: Synchronous ready stable until clock low (SRDY set-up
time) = 35 ns min
4. tClSRY:
Clock low until synchronous ready transition (SRDY hold time) =
15 ns min

Figure 2·32 Valid SRDY Transitions on the 80186
2-46

210912-001

80186/80188 CPU

STROBE

CLOCK

,

OUT

INPUT ---S--E"""T.-UP-T-IM-EJHOLD TIME

rrl

I
ACTUAL SAMPLING INSTANT

V

INVALID

INPUT~
RESPONSE
VALID

--.l

I-

RESOLUTION TIME

HOLD

---~--~~~--~----

HLDA

--:---/-'1-"-1

--r-/I--~l-...!!:2!~~-__

AD15·ADO
DEN ___

1

~-+

~

A16·A19

RD,WR,BHE

INPUT

DT/R,SO·S2

---i---'

RESPONSE - - - - - - - - ' ,

Figure 2·34 Signal Float/HLDA Timing
Figure 2·33 Valid & Invalid Latch Input
Transitions & Responses

synchronization technique described above (with some
minor modifications for the ARDY line, refer to paragraph 2.5.1). The sampling window of the latches is designed to be in the tens of pico-seconds, and should allow
operation of the synchronizers with a mean time between
failures of over 30 years assuming continuous operation.

window is typically much smaller than the actual window
specified by the data sheet specifications, however, part to
part variation can move this actual window around within
the specified window.
Even ifthe input to a data latch makes a transition while a
data latch is attempting to latch this input, the output of
the latch will attain a stable state after a certain amount of
time-typically much longer than the normal strobe to
output delay time (see Figure 2-33). Therefore, in order
to synchronize an asynchronous signal, sample the signal
into one data latch, wait a certain amount of time, then
latch it into a second data latch. Since the time between
the strobe into the first data latch and the strobe into the
second data latch allows the first data latch to attain a
steady state (or to resolve the asynchronous signal), the
second data latch will be presented with an input signal
which satisfies any set up and hold time requirements it
may have. The output of this second latch is a synchronous signal with respect to its strobe input.

2.6 BUS EXCHANGE MECHANISMS
The 80186 uses a HOLD/HLDA bus exchange protocol.
This protocol allows other asynchronous bus master devices (i.e., ones which drive address, data, and control
information on the bus) to gain control of the bus to perform bus cycles (memory or 110 reads or writes).

2.6.1 HOLD Response
In the HOLD/HLDA protocol, a device requiring bus
control (e.g., an external DMA device) raises the HOLD
line. In response to this HOLD request, the 80186 will
raise its HLDA line after it has finished its current bus
activity. When the external device is finished with the bus,
it drops its bus HOLD request. The 80186 responds by
dropping its HLDA line and resuming bus operation.

A synchronization failure can occur if the synchronizer
fails to resolve the asynchronous transition within the
time between the two latch's strobe signals. The rate of
failure is determined by the actual size of the sampling
window of the data latch, and by the amount of time be·
tween the strobe signals of the two latches. Obviously, as
the sampling window gets smaller, the number of times an
asynchronous transition will occur during the sampling
window will drop. In addition, however, a smaller sampling window is also indicative of a faster resolution time
for an input transition which manages to fall within the
sampling window.

80186 SYNCHRONIZERS

When the 80186 recognizes a bus hold by driving HLDA
high, it will float many of its signals (see Figure 2-34).
ADO·ADI5 (address/data 0·15) and DEN* (data enable)
are floated within tCLAZ (35 ns) after the same clock edge
that caused HLDA to be driven active. A16-A19 (address
16-19), RD*, WR*, BHE* (Bus High Enable), DT/R*
(Data Transmit/Receive*) and SO-S2 (status 0·2) are
floated within lcHCZ (45 ns) after the clock edge immediately before the clock edge on which HLDA becomes
active.

The 80186 contains synchronizers on the RES*, TEST*,
TmrInO·I, DRQO·I, NMI, INTO-3, ARDY, and HOLD
input lines. Each of these synchronizers use the two stage

Only the signals described in the previous paragraph float
during bus HOLD. Signals that do not float during
bus HOLD are mainly associated with peripheral
2-47

210912·001

80186/80188 CPU

normally insert no Tj states between T4 and T J of the next
bus cycle if it requires any bus activity (e.g., instruction
fetches or 110 reads). However, the 80186 may not have
an immediate need for the bus after a bus cycle, and will
insert Tj states independent of the HOLD input.
When the HOLD request is active, the 80186 will be
forced to proceed from T4 to TjsO that the bus may be
relinquished. See Figure 2-36. HOLD must go active 3
T-states before the end of a bus cycle to force the 80186 to
insert idle T-states after T4 (and to synchronize the request, and one to signal the 80186 that T4 of the bus cycle
will be followed by idle T-states). After the bus cycle has
ended, the bus hold will be immediately acknowledged. If
the 80186 has already determined that an idle T-state will
follow T4 of the current bus cycle, HOLD only needs to
go active two T-states before the end of the bus cycle to
force the 80186 to relinquish the bus at the end of the
current bus cycle. This is because the external HOLD request is not required to force the generation of idle
T-states.

HOLD
HLDA _ _ _ _:......_ _ _...:-_ _ _-1

1. tHVCL: Hold valid until clock low = 25 ns min
2. tCLHAV: Clock low until HLDA active = 50 ns max

Figure 2-35 80186 Idle Bus HOLD/HLDA Timing

functionality or control bus devices, either directly or indirectly. These signals include TmrOut, ALE (Address
Latch Enable) and the chip select lines (UCS*, LCS*,
MCSO-3*, and PCSO-6*). The designer should be aware
that the chip select circuits do not look at externally generated addresses. Discrete chip select and ready generation logic must be used for memory or peripheral devices
that are addresses by external bus master devices.

An external HOLD has a higher priority than both the
80186 CPU or the integrated DMA unit. However, an external HOLD will not separate the. two cycles needed to
perform a word access to an odd memory location. Also,
an external HOLD will not separate the two-to-four bus
cycle required to perform a DMA transfer using the integrated controller. Each of these factors will add additional
bus cycle times to the bus latency of the 80186.

2.6.2 HOLD/HLDA Timing and Bus Latency

Another factor influencing bus latency is locked transfers.
Whenever a locked transfer is occurring, the 80186 will
not recognize external HOLDs. The 80186 will also not
recognize internal D MA bus requests. Locked transfers
are programmed by preceding an instruction with the
LOCK prefix. Any transfers generated by such a prefixed
instruction will be locked, and will not be separated by
any external bus requesting device. String instructions
may be locked. Since string transfers may require thousands of bus cycles, bus latency will suffer if they are
locked.

The time required between HOLD going active and the
80186 driving HLDA active is known as bus latency.
Many factors affect this latency, including synchronization delays, bus cycle times, locked transfer times and
interrupt acknowledge cycles. Since the HOLD request
line is internally synchronized by the 80186, and it may
be an asynchronous signal. To guarantee recognition on a
certain clock edge, it must satisfy a certain setup and hold
time to the falling edge of the CPU clock. A full CPU
clock cycle is required for this synchronization, that is,
the internal HOLD signal is not presented to the internal
bus arbitration circuits until one full clock cycle after it is
latched from the HOLD input. If the bus is idle, HLDA
will follow HOLD by two CPU clock cycles plus a small
amount of setup and propagation delay time. The first
clock cycle synchronizes the input and the second clock
cycle signals the internal circuits to initiate a bus hold.
(See Figure 2-35.)

The final factor affecting bus latency time is interrupt acknowledge cycles. When an external interrupt controller
is used, or if the integrated interrupt controller is used in
the iRMX86 mode the 80186 will run two interrupt acknowledge cycles back to back. These cycles are automatically "locked" and will never be separated by any bus
HOLD, either internal or external.

Many factors influence the number of clock cycles between a HOLD request and a HLDA. These factors may
make the latency longer than the best case shown above.
One of the most important factors is that the 80186 will
not relinquish the local bus until the bus is idle. An idle
bus occurs whenever the 80186 is not performing any bus
transfers. When the bus is idle the 80186 generates idle
T-states. The bus can become idle only at the end of a bus
cycle. Therefore, the 80186 can recognize HOLD only
after the end of the current bus cycle. The 80186 will

2.6.3 End of HOLD Timing
After the 80186 recognizes that the HOLD input has gone
inactive, it will drop its HLDA line in a single clock cycle. Figure 2-37 shows this timing. The 80186 will insert
only two Tj after HLDA has gone inactive, assuming that
the 80186 has internal bus cycles to run. During the last
Tj, status information will go active concerning the bus

2-48

210912·001

80186/80188 CPU

CLOCK
OUT

HOLD

-;-1

HL.DA _ _ _-;.. _ _ _.;..-_ _

1 Decision: No additional internal bus cycles required, idle T-states will be
inserted after T4
2. Greater than 25 ns (tHvcd

3. less than 50 ns

(tCLHAV}

4. HOLD request internally synchronized
I
I

T 3 0R
Tw

I
I

T.

I
I

T;

CLOCK~(D
~
OUT

HOLD

0~
I

I

\
I

HLOA _ _ _ _ _ _ _ _ _ _ _ _ _ __

1. Decision: Additional internal bus cycles required, no idle T-states will be
inserted, Hold not active soon enough to force idle T-states
2. Greater than 25 ns (tHVCL): not required since it will not get recognized
anyway
3. HOLD request interna!ly synchroniled

CL.OCK
OUT

HOLD
HlOA _ _ _ _ _ _ _ _ _ _ _ _ _ _...1

1. HOLD request internally synchronized
2. Decision: HOLD request active, Idle I-slates will be inserted at end of
current bus cycle
3. Greater than 25 ns
4. Less than 50 ns

Figure 2-36 HOLD/HLDA Timing

CLOCK
OUT

HOLD

HLOA

AOO-AD15

DEN
A16/53-A19/S6

RO,WR,BHE
OT/A,5O-82
1.
2.
3.
4.

HOLD internally synchronized
Greater than 25 ns
Less than 50 ns
Lines come out of float only if a bus cycle is pending

Figure 2-37 End of HOLD Timing Diagram
2-49

210912-001

80186/80188 CPU

Table 2·21 801861188 Interrupt Vectors

cycle about to be run. If the 80186 has no pending bus
activity, it will maintain all lines floating (high impedance) until the last Ti before it begins the first bus cycle
after the HOLD.

Interrupt Name
Divide Error
Exception
Single Step
Interrupt
NMI
Breakpoint
Interrupt
INTO Detected
Overflow
Exception
Array Bounds
Exception
Unused-Opcode
Exception
ESC Opcode
Exception
Timer 0 Interrupt
Timer 1 Interrupt
Timer 2 Interrupt
Reserved
DMA 0 Interrupt
DMA 1 Interrupt
INTO Interrupt
INTI Interrupt
INT2 Interrupt
INT3 Interrupt

2.7 INTERRUPTS
Interrupts fall into three classes: hardware initiated interrupts; INT instructions; and instruction exceptions. Hardware initiated interrupts usually occur in response to some
external input and are classified as non-maskable or
maskable. Software programs cause an interrupt with an
INT instruction. Interrupt exceptions usually occur when
some unusual circumstance, that prevents further instruction processing, occurs while attempting to process
instructions.
The 801861188 CPU receives interrupts from both internal and external sources. Internal interrupt sources such
as the timers and DMA channels can be disabled by their
own control registers or by mask bits in the integral interrupt controller. The 80186/188 integral interrupt controller has its own control registers that set the mode of
operation for the controller.

Vector Default
1\'pe ,Priority

Related
Instructions

'1

1

12"2

All

2
3

1
'1

All
INT

4

'1

INTO

5

'1

BOUND

6

'1

Undefined
Opcodes
ESC Opcodes

7

'1'"

8
18
19
9
10
11
12
13
14
15

2A ....
2B ....
2C ....

I

DIV,IDIV

0

!

3
4

5
6
7
8
9

NOTES:
*1. These are generated as the result of an instruction
execution.
* *2. This is handled as in the 8086.
* * * *3. All three timers constitute one source of request to
the interrupt controller. The Timer interrupts all have
the same default priority level with respect to all
other interrupt sources, However, they have a defined priority ordering amongst themselves, (Priority
2A is higher priority than 2B,) Each Timer interrupt
has a separate vector type number.
4. Default priorities for the interrupt sources are used
only if the user does not program each source into a
unique priority level.
* * * 5, An escape opcode will cause a trap only if the
proper bit is set in the peripheral control block relocation register.

The integral interrupt controller operates in two major
modes (refer to paragraph 2.4). These two modes of operation are the master (non-iRMX 86) mode and the iRMX
86 mode.
In the master mode the integral interrupt controller acts as
the system master interrupt controller. Five pins (NMI
and INTO-INT3) are provided in this interrupt mode for
external interrupt sources. Each external interrupt source
has a pre-assigned vector type and priority. (See Table
2-21.) Vector types point to address information for interrupt service routines. The user can program the interrupt
sources into any of eight different priority by placing a
3-bit priority level (0-7) in the control register of the interrupt source. Vectors generated in the master mode are
fixed and cannot be changed.

coding of the priority level requesting service. The
significant five bits of the vector are programmed by writing to the Interrupt Vector at offset 20H.

In addition, the integral interrupt controller will generate
interrupt vectors for the the integrated DMA channels and
the integrated timers. Interrupt vectors for the external
interrupt lines will also be generated by the integral interrupt controller if the external interrupt lines are not configured in the cascade or special fully nested modes.

For a detailed description of the operation of the integral
interrupt controller in the various interrupts modes, and
vector generation in these modes (refer to paragraph
2.8.4).

In the iRMX 86 mode the integral interrupt controller operates as a slave to an external interrupt controller which
is the master system interrupt controller. Vector generation in this mode of operation is exactly like the operation
of an 8259A slave. The interrupt generates an 8-bit vector
which the CPU multiplies by four and uses as an address
into a vector table. The significant five bits of the vector
are user programmable while the lower three bits are generated by the priority logic. These bits represent the en-

2.8 SUPPORT CIRCUITS
The following paragraphs describe the various integral
support circuits that are use to support the 801861188
CPU's. These integral circuits are the Direct Memory
Access (DMA) Unit, the Timer Unit, the Interrupt
2-50

210912-001

80186/80188 CPU

Controller Unit, the Chip Select Unit and the Clock Generator Unit. Paragraph 2.2.1 provides an overview of
these integral circuits.

EXTERNAL ADDRESS/DATA,
CONTROL, CHIP SELECTS,
ETC.
BUS INTERFACE

2.8.1 Direct Memory Access (DMA) Unit

&
CHIP SELECT CIRCUITRY

The 80186 contains an integrated DMA unit with two independent high speed DMA channels. These channels operate independently of the CPU, and drive all integrated
bus interface components (bus controller, chip selects,
etc.) exactly as the CPU (see Figure 2-38). Therefore,
bus cycles initiated by the DMA unit are exactly the same
as bus cycles initiated by the CPU (except that S6 = I during all DMA initiated cycles, refer to paragraph 2.5).
Therefore, interfacing with the DMA unit itself is very
simple, since, except for the addition of the DMA request
connection, it is exactly the same as interfacing to the
CPU.

DMA
REQUESTS

Figure 2-38 80186 CPU/DMA Channel
Internal Model
After every DMA transfer the 16-bit DMA transfer count
register is decremented by I, whether a byte transfer or a
word transfer has occurred. If·the TC bit in the DMA
control register is set, the DMA ST/STOP* bit (discussed
later) will be cleared when this register goes to zero, causing DMA activity to cease. A transfer count of zero allows 65536 (2 16) transfers.

Data transfers can occur between memory and I/O spaces
(e.g., Memory to I/O) or within the same space (e.g.,
Memory to Memory or I/O to I/O). Data can be transferred either in bytes (8 bits) or in words (16 bits) to or from
even or odd addresses. Each DMA channel maintains
both a 20-bit source and destination pointer which can be
optionally incremented or decremented after each data
transfer (by one or two depending on byte or word transfers). Each data transfer consumes two bus cycles (a minimum of eight clocks), one cycle to fetch data and the
other to store data. This provides a maximum data transfer rate of one MW/sec (megaword/second) or two
MBytes/sec.

The DMA control register contains bits which control
various channel characteristics. (See Figure 2-40.) This
includes control bits for each of the data source and destination whether the pointer points to memory or I/O space,
or whether the pointer will be incremented/decremented/
left alone after each DMA transfer. The control register
also contains a bit which selects between byte or word
transfers. Two synchronization bits are used to determine
the source of the DMA requests. The TC bit determines
whether DMA activity will cease after a programmed
number of DMA transfers. The INT bit is used to enable
interrupts to the processor when this has occurred.

PROGRAMMING THE DMA UNIT

Each of the two DMA channels contains several registers
which are used to control the channel operations. These
registers are included in the 80186 integrated peripheral
control block. Registers included are the source and destination pointer registers, the transfer count register, and
the control register. Layout and bit interpretations for
these registers are shown in Figure 2-39.

NOTE
An Interrupt will not be generated to the CPU
when the count reaches zero unless both the
INT bit and the TC bit are set.

The 20-bit source and destination pointers allow access to
the complete I Mbyte address space of the 80186. All 20
bits are affected by the auto-increment or auto-decrement
unit of the DMA (i.e., the DMA channels address the full
1 Mbyte address space of the 80186 as a flat, linear array
without segments). When addressing I/O space, the upper
4 bits of the DMA pointer registers should be programmed to be O. If these upper 4 bits are not programmed to 0, the programmed value (greater than 64K
in 110 space) will be driven onto the address bus where it
is not accessable to the CPU. However, the data transfer
will take place correctly.

The control register also contains a start/stop (ST/STOP*)
bit. This bit is used to enable DMA transfers. Whenever
this bit is set, the channel is "armed" and a DMA transfer
will occur whenever a DMA request is made to the channel. If this bit is cleared, no DMA transfers will be performed by the channel. A companion bit, the CHG/
NOCHG* bit, allows the contents of the DMA register to
be changed without modifying the state of the start/stop
bit. The ST/STOP* will only be modified if the CHG/
2-51

210912·001

80186/80188 CPU

OFFSET
DEH
DCH
DAH
D8H
D6H

x

I
15

DOH

15

CEH

C2H
COH

I I I XI .1 I

I I I

CONTROL WORD

0
119

16

119

16

0
0

X

X

TRANSFER COUNT
DESTINATION POINTER

t

SOURCE POINTER CHANNEL 1

X

I I I

I I I xl I I

X

X

X

X

X

X

I

CHANNELO~
0

15

C6H
C4H

X

15

D4H
D2H

CCH
CAH
C8H

X

119

16

J19

16

0

15

CONTROL WORD
TRANSFER COUNT
DESTINATION POINTER
SOURCE POINTER

0

15

(1) CONTROL REGISTER LAYOUT:

-------DESTINATION

SOURCE

-..SYNCHRONIZATION

Figure 2·39 80186 DMA Register Layout

NOCHG* bit is also set during the write to the DMA
control register. The CHG/NOCHG* bit is write only.
This bit will always be read back as a '0'. Because DMA
transfers could occur immediately after the ST/STOP* bit
is set, this bit should only be set after all other DMA
control registers have been programmed. This bit is automatically cleared when the transfer count reaches zero
and the TC bit in the DMA control register is set. This bit
is also cleared when the transfer count register reaches
zero and unsynchronized DMA transfers are programmed
(regardless of the state of the TC bit).

gramming values should be placed into memory locations
and moved into the DMA registers using a locked string
move instruction. This will prevent a DMA transfer from
occurring after only half of the register values have
changed. This also holds true if a read/modify/write type
of operation is being performed (e.g., ANDing off bits in
a pointer register in a single AND instruction to a pointer
register mapped into memory space.

All DMA unit programming registers are directly accessable by the CPU. This means the CPU can, for example,
modify the DMA source pointer register after 137 DMA
transfers have occurred, and have the new pointer value
used for the 138th DMA transfer. If more than one register in the DMA channel is being modified during the time
when a DMA request may be generated, and the DMA
channel is enabled (ST/STOP* bit set), the register pro-

Every DMA transfer in the 80186 consists of two independent bus cycles, the fetch cycle and the deposit cycle
(see Figure 2-41). During the fetch cycle, the byte or
word data is accessed from memory or I/O space using
the address in the source pointer register. The data accessed is placed in an internal temporary register, which
is not accessible by the CPU. During the deposit cycle,
the byte or word data in this internal register is placed in

DMA TRANSFERS

Figure 2·40 DMA Control Register
2-52

210912-001

80186/80188 CPU

CLOCK

I
I

T.

I
I

T,

T.

T.

Tw

Tw

T,

T.

T.

T.

T4

OUT~
I

I
I

I

DRQ~

I
I

~

ADOAD15

I
I
I

I

I

I
I
I

I

\

I

WR

I

I.

:I~
CD:

CD

I

i

RD

1.
2.
3.
4.

\

I

I
I

I
I
I

l\I

I

0:

I
I
I
I
I
I
I
I

I

I
I
I
I
I

lr
I

Sou ce address
Source data
Destination address
Destination data

NOTE: Wait states are inserted by the bus condition during the bus cycle, not by the DMA controller

Figure 2·41 Example DMA Transfer Cycle
memory or I/O space using the address in the destination
pointer register. These two bus cycles will not be separated by bus HOLD or by the other DMA channel, and
one will never be run without the other except when the
CPU is RESET. Notice that the bus cycles run by the
DMA unit are exactly the same as memory or liD bus
cycles run by the CPU. The only difference between the
two is the state of the S6 status line (which is multiplexed
on the A 19 line): on all CPU initiated bus cycles, this
status line will be driven low; on all DMA initiated bus
cycles, this status line will be driven high.

channel can be programmed to generate a DMA request
whenever Timer 2 reaches its maximum count. Setting
the TDRQ bit in the DMA channel control register selects
this feature. A DMA request generated in this manner
will be latched in the DMA controller, so that once the
timer request has been generated, it cannot be cleared except by running the DMA cycle or by clearing the TDRQ
bits in both DMA control registers. Before any DMA requests are generated in this mode, Timer 2 must be initiated and enabled.
A timer requested DMA cycle being run by either DMA
channel will reset the timer request. Thus, if both channels are using the timer to request a DMA cycle, only one
DMA channel will execute a transfer for every timeout of
Timer 2. Another implication of having a single bit timer
DMA request latch in the DMA controller is that if another Timer 2 timeout occurs before a DMA channel has
a chance to run a DMA transfer, the first request will be
lost (Le., only a single DMA transfer will occur, even
though the timer has timed out twice).

DMA REQUESTS
Each DMA channel has a single DMA request line by
which an external device may request a DMA transfer.
The synchronization bits in the DMA control register determine whether this line is interpreted to be connected to
the source of the DMA data or the destination of the
DMA data. All transfer requests on this line are synchronized to the CPU clock before being presented to internal
DMA logic. Any asynchronous transitions of the DMA
request line will not cause the DMA channel to malfunction. In addition to external requests, DMA requests may
be generated whenever the internal Timer 2 times out, or
continuously by programming the synchronization bits in
the DMA control register to call for unsynchronized
DMA transfers.

The DMA channel can also be programmed to provide its
own DMA requests. In this mode, DMA transfer cycles
will be run continuously at the maximum bus bandwidth,
one after the other until the preprogrammed number of
DMA transfers (in the DMA transfer count register) have
occurred. This mode is selected by programming the synchronization bits in the DMA control register for unsynchronized transfers. In this mode, the DMA controller
monopolizes the CPU bus (Le., the CPU will not be able
to perform opcode fetching, memory operations, etc.,
while the DMA transfers are occurring). Also, the DMA

The 80186 DMA controller handles two types of internally synchronized DMA transfers: the first Timer 2 generates the DMA request, and the second where the DMA
channel itself generates the DMA request. The DMA
2-53

210912-001

80186/80188 CPU

will only perform the number of transfers indicated in the
maximum count register regardless of the state of the TC
bit in the DMA control register.

signal can be generated, if required, by decoding an address, or by using one of the PCS* lines (see Figure
2-44).

NOTE

DMA REQUEST TIMING AND LATENCY

Before any DMA request can be generated, the 80186
internal bus must be granted to the DMA unit. A certain
amount of time is required for the CPU to grant this internal bus to the DMA unit. The time between a DMA request being issued and the DMA transfer being run is
known as DMA latency. Many of the issues concerning
DMA latency are the same as those concerning bus latency (refer to the paragraphs on Bus Exchange Mechanisms). Consider the important difference that external
HOLD always has bus priority over an internal DMA
transfer. Thus, the latency time of an internal DMA cycle
will suffer during an external bus HOLD.

ALE must be used to factor the DACK because
addresses are not guaranteed stable when chip
selects go active. The use of ALE is required
because if the address is not stable when the
PCS goes active, glitches can occur at the output of the DACK generation circuits as the address lines change state. Once ALE has gone
low, the addresses are guaranteed to have been
stable for at least tAvAL (30ns).
EXTERNALLY SYNCHRONIZED DMA
TRANSFERS

Each DMA channel has a programmed priority relative to
the other DMA channel. Both channels may be programmed to be the same priority, or one may be programmed to be of higher priority than the other channel.
If both channels are active, DMA latency will suffer on
the lower priority channel. If both channels are active and
both channels are of the same programmed priority, DMA
transfer cycles will alternate between the two channels
(i.e., the first channel will perform a fetch and deposit,
followed by a fetch and deposit by the second channel,
etc).

The 80186 DMA controller is capable of two types of
externally synchronized DMA transfers (requested externally rather than by integrated Timer 2 or by the DMA
channel itself (in unsynchronized transfers). These transfers are source synchronized and destination synchronized transfers and are selected by programming the
synchronization bits in the DMA channel control register.
Source synchronized and destination synchronized transfer differ in the time at which the DMA request pin is
sampled to determine if another DMA transfer is immediately required after the currently executing DMA transfer. For source synchronized transfers, the DMA request
is sampled such that two source synchronized DMA transfers may occur one immediately after the other. For destination synchronized transfers a certain amount of idle
time is automatically inserted between two DMA transfers
to allow time for the DMA requesting device to drive its
DMA request inactive.

The DMA request (DRQ) is sampled four clock cycles
before the beginning of a bus cycle to determine if any
DMA activity will be required. A minimum of four CPU
clock cycles must occur between the time DRQ goes active and the beginning of the first DMA cycle (see Figure
2-42). It takes at least four clock cycles for the request to
propagate through the logic circuits (see Figure 2-43).
This time is independent of the number of wait states inserted in the bus cycle. The maximum DMA latency is a
function of other processor activity.

Source Synchronized DMA Transfers

If DRQ is sampled active at point 1 in Figure 2-42, the
DMA cycle will be executed, even if the DMA request
goes inactive before the beginning of the first DMA cycle. If the BIU is busy and cannot run the cycle when
DRQ goes active, DRQ must remain active for a minimum of four clock cycles before the time that it is possible to run the requested cycle. DMA requests are not
permanently stored, therefore, if DRQ goes inactive after
one clock, a zero will be propagated through the logic and
no DMA cycles will be run.

In a source synchronized DMA transfer, the source of the
DMA data requests the DMA cycle (for example, a
floppy disk read from the disk to main memory). In this
type of transfer, the device requesting the transfer is read
during the fetch cycle of the DMA transfer. Since four
CPU clock cycles elapse from the time DMA request is
sampled to the time the DMA transfer is actually begun,
and a bus cycle takes a minimum of four clock cycles, the
earliest time the DMA request pin will be sampled for
another DMA transfer will be at the beginning of the deposit cycle of a DMA transfer. This allows over three
CPU clock cycles between the time the DMA requesting
device receives an acknowledge to its DMA request
(around the beginning ofT2 of the DMA fetch cycle), and
the time it must drive this request inactive (assuming no
wait states) to insure that another DMA transfer is not
performed if it is not desired (see Figure 2-45).

DMA ACKNOWLEDGE

The 80186 does not generate an explicit DMA acknowledge signal. Instead, a read or write directly to the DMA
requesting device is performed. A DMA acknowledge
2-54

210912·001

80186/80188 CPU

T,o.
T,o.

T,o.

I
I

T.o.

T,o.

T,o.

I

T,o.

T.o.

T,o.

:

Two,

Two,

Two,

T,o.

I

T,

T,

T,

T,

T,
olDMA
I

C'fCLE

~
111011

~~

I

I

I

I

\.!J~,~
I

I
I

DRQ

I
I
I
I'
I

CD

I
I.
I
I
.1
I

CD

I
.1
I
I
I
I

I
I
I
I
I
I

1. tOROCL = DMA request to clock low = 25 ns min to guarantee recognition
2. Synchronizer resolution time
3. DMA unit priority arbitration, etc. time
4. Bus Interface Unit latches DMA request and decides to run DMA cycle

Figure 2·42 DMA Request Timing

Figure 2·43 DMA Request Logic

ADDR.
LATCH

80186

A6

DMADEVICE

ALEr-------------------------~

ACKNOWLEDGE

PCSO r - - - - - - - - - - - - - - - - - - - + - - - - - - - - '... CHIP SEL
DRQO

DMA REQUEST

Figure 2·44 DMA Acknowledge Synthesis

2-55

210912·001

80186/80188 CPU

DEPOSIT CYCLE

FETCH CYCLE

T,

T,

T,

T,

T,

DRQ --~----~--~~--~~

80186

DECISION:

1. Current DMA source synchronized transfer will not be immediately
followed by another DMA transfer
NEXT
DMA
TRANSFER

DEPOSIT CYCLE

T,

80186

T,

:

Ta

:

T,

Tw

T,

T,

T,

Decision:

1. Current DMA destination synchronized transfer will be followed
immediately by another DMA transfer

Figure 2-45 Source & Destination Synchronized DMA Request Timing
Destination Synchronized DMA Transfers

unit will insert only two CPU clock cycles between the
deposit cycle of one DMA transfer and the fetch cycle of
the next DMA transfer. The DMA destination requesting
device must drop its DMA request at least two clock cycles before the end of the deposit cycle regardless of -the
number of wait states inserted into the bus cycle. Figure
2-45 shows the DMA request ending too late to prevent
the immediate generation of another DMA transfer. Any
wait states inserted in the deposit cycle of the DMA transfer will lengthen the amount of time from the beginning of
the deposit cycle to the time DMA will be sampled for
another DMA transfer. Therefore, if the amount of time a
device requires to drop its DMA request after receiving a
DMA acknowledge from the 80186 is longer than the 0
wait state 8MHz 80186 maximum (lOOns) from the start
of T2, wait states can be inserted into the DMA cycle to
lengthen the amount of time the device has to drop its
DMA request after receiving the DMA acknowledge. Table 2-22 lists the amount of time between the beginning of
T2 and the time DMA request is sampled as wait states
are inserted in the DMA deposit cycle.

In destination synchronized DMA transfers, the destination of the DMA data requests the DMA transfer (for example a floppy disk write from main memory to the disk).
In this type of transfer, the device requesting the transfer
is written during the deposit cycle of the DMA transfer.
This transfer causes a problem since the DMA requesting
device will not receive notification of the DMA cycle being run until three clock cycles before the end of the
DMA transfer (if no wait states are being inserted into the
deposit cycle of the DMA transfer) and four clock cycles
elapse before the DMA controller can determine whether
another DMA cycle should be run immediately following
the current DMA transfer. To avoid this problem, the
DMA unit will relinquish the CPU bus after each destination synchronized DMA transfer for at least two CPU
clock cycles. This action allows the DMA requesting device time to drop its DMA request if it does not immediately desire another immediate DMA transfer.
When the DMA unit relinquishes the bus, the CPU may
resume bus operation (e.g., instruction fetching, memory
or I/O reads or writes, etc.). Typically, a CPU initiated
bus cycle will be inserted between each destination synchronized DMA transfer. If no CPU bus activity is required, however (and none can be guaranteed), the DMA

2.8.2 Timer Unit
The 80186 contains three internal 16-bit programmable
timers (see Figure 2-46) two of which are connected to
2-56

210912·001

80186/80188 CPU

Table 2-22 DMA Request Inactive Timing

!

WAIT
STATES
0
I

2
3

reaching the MAX COUNT register value, the timer
count value will reset to zero during that same clock (i.e"
the maximum count value is never stored in the count register itself). Timers 0 and I contain, in addition, a second
MAX COUNT register, which enables the timers to alternate their count between two different MAX COUNT values programmed by the user. If a single MAX COUNT
register is used, the timer output pin switches LOW for a
single clock, one clock after the maximum count value
has been reached. In the dual MAX COUNT register
mode, the output pin indicates which MAX COUNT register is currently in use, thus allowing nearly complete
freedom in selecting waveform duty cycles. For the timers
with two MAX COUNT registers, the RIU bit in the control register determines which is used for the comparison.

MAXIMUM TIME (ns)
6MHz
8MHZ
141
308
475
641

100
225
350
475

Table 2-23 Timer Control Block Format
'Reg later Offset
Reglater Name
Mode/Control Word
Max Count B
Max Count A
Count Register

Tmr.O Tmr.1
56H
54H
52H
50H

Tmr.2

5EH
5CH
5AH
58H

66H
not present
62H
60H

Each timer gets serviced every fourth CPU-clock cycle.
Therefore, the timers, whether clocked internally or externally can only operate at speeds up to one-quarter the
internal clock frequency (one-eighth the crystal rate).
This will be 2 MHz for an 8 MHz CPU clock. Due to
internal synchronization and pipelining of the timer circuits, a timer output may take up to six clocks to respond
to any individual clock or gate input. Since the count registers and the maximum count registers are all 16 bits
wide, 16 bits of resolution are provided. However, any
read or write access to the Timers will add one wait state
to the minimum four-clock bus cycle. This is needed to
synchronize and coordinate the internal data flows between the internal timers and the internal bus.

four external pins (two pins per timer). These timers
(Timers 0 and I) can be used to count external events,
time external events, generate non-repetitive waveforms,
etc. The third timer is not directly accessible through dedicated pins. This timer is useful for real-time coding and
time delay applications and may be used to prescale the
other two timers (refer to Volume I of this User's Guide).
The timers are controlled by II 16-bit registers in the
internal peripheral control block (refer to Table 2-23).
The count register contains the current value of the timer
and it can be read or written at any time independent of
whether the timer is running or not. The value of this
register will be incremented for each timer event. Each of
the timers contains a MAX COUNT register, which defines the maximum count the timer will reach. After

TIMER INPUT PIN OPERATION
Timers 0 and 1 each have individual timer input pins.
All low-to-high transitions on these input pins are

DMA
REQ.
T2
INT.
REQ.

TIMERO'
TIMER 2
MAX COUNT VALUE

CLOCK

B

MAX COUNT VALUE

B

MAX COUNT VALUE

MODE/CONTROL
WORD

INTERNAL ADDRESS/DATA BUS
ALL 16 BIT REGISTERS

Figure 2-46 Timer Block Diagram
2-57

210912·001

80186/80188 CPU

synchronized, latched, and presented to the counter element when the particular timer is being serviced by the
counter element.

TIMER OUTPUT PIN OPERATION

Timers 0 and 1 each contain a single timer output pin.
This pin can perform two functions at programmer option. The first is a single pulse indicating the end of a
timing cycle. The second is a level indicating the maximum count register currently being used. The timer outputs operate as outlined below whether internal or
external clocking of the timer is used. If external clocking
is used, however, the user should remember that the time
between an external transition on the timer input pin and
the time this transition is reflected in the timer out pin will
vary depending on when the input transition occurs relative to the timer's being serviced by the counter element.

Signals on this input affect timer operation in three different ways. The way the pin signals are used is determined
by the external (EXT) and retrigger (RTG) bits in the
timer control register. If the EXT bit is set, transitions on
the input pin cause the timer count value to increment if
the timer is enabled (the timer control register enable bit
is set). Thus, the timer counts external events. If the EXT
bit is cleared, all timer increments are caused by either
the CPU clock or by Timer 2 timing out. In this mode, the
RTG bit determines whether the input pin will enable
timer operation, or whether it will retrigger timer
operation.

When the timer is in single maximum count register mode
(timer control register ALT bit cleared) the timer output
pin goes low for a single CPU clock the clock after the
timer is serviced by the counter element where maximum
count is reached (see Figure 2-47). This mode is useful
when using the timer as a baud rate generator.

If the EXT bit is low and the RTG bit is also low, the timer
will count internal timer events only when the timer input
pin is high and the enable (EN) bit in the timer control
register is set.

When the timer is programmed in dual maximum count
register mode (timer control register ALT bit set), the
timer output pin indicates which maximum count register
is being used. The pin is low if maximum count register B
is being used for the current count, high if maximum
count register A is being used. If the timer is programmed
in continuous mode (the CONTinuous bit in the timer
control register is set), this pin could generate a waveform
of any duty cycle. For example, if maximum count register A contained 10 and maximum count register B contained 20, a 33% duty cycle waveform would be
generated.

In this mode, the pin is level sensitive, not edge sensitive.
A low-to-high transition on the timer input pin is not required to enable timer operation. If the input is tied high,
the timer will be continually enabled. The time enable
input signal is completely independent of the EN bit in the
timer control register: both must be high for the timer to
count. Example uses for the timer in this mode would be a
real time clock or a baud rate generator.
If the EXT bit is low and the RTG bit is high, the timer
will act as a digital one-shot. In this mode, every
low-to-high transition on the timer input pin will cause the
timer to reset to zero. If the timer is enabled (i.e., the EN
bit in the timer control register is set) timer operation will
begin and the timer will count CPU clock transitions or
Timer 2 timeouts. Timer operation will cease at the end of
a timer cycle, that is, when the value in the maximum
count register A is reached and the timer count value resets to zero (in single maximum count register mode, remember that the maximum count value is never stored in
the timer count register) or when the value in maximum
count register B is reached and the timer count value resets to zero (in dual maximum count register mode). If
another low-to-high transition occurs on the input pin before the end of the timer cycle, the timer will reset to zero
and begin the timing cycle again regardless of the state of
the continuous (CONT) bit in the timer control register. If
the CONT bit in the timer control register is cleared, the
timer EN bit will automatically be cleared at the end of
the timer cycle. This means that any additional transitions
on the input pin will be ignored by the timer. If the CONT
bit in the timer control register is set, the timer will reset
to zero and begin another timing cycle for every
low-to-high transition on the input pin, regardless of
whether the timer had reached the end of a timer cycle,
because the timer EN bit would not have been cleared at
the end of the timing cycle. An example use of the timer
is this mode is an alarm clock time out signal or interrupt.

TIMER APPLICATIONS

The 80186 timers can be used for almost any application
for which a Qiscrete timer circuit would be used. These
include real time clocks, baud rate generators, or event
counters.
Real Time Clock

The sample program (see Figure 2-48) shows the 80186
timer being used with the 80186 CPU to form a real time
clock (see Figure 2-49). In this implementation, Timer 2
is programmed to provide an interrupt to the CPU every
millisecond. The CPU then increments memory based
clock variables.
Baud Rate Generator

The 80186 timers can be used as baud rate generators for
serial communication controllers (e.g., the 8274). Figure
2-50 shows this simple connection and Figure 2-48 lists
the code to program the timer as a baud rate generator.
2-58

210912·001

80186/80188 CPU

--

TIMER 0 SERVICED

INTERNAL
COUNT
VALUE

------------------~,r_--------4_-----------------MAXCOUNT-1

TMROUT--------------------------~
PIN

Figure 2-47 80186 Timer Out Signal
Event Counter

The interrupt controller resolves priority among simultaneous requests. Nesting is provided so interrupt service
routines for lower priority interrupts may themselves be
interrupted by higher priority interrupts.

The 81086 timer can be used to count events. Figure 2-51
shows a hypothetical application in which the 80186 timer
will count the interruptions in a light source. The number
of interruptions can be read directly from the count register of the timer, since the timer counts up (i.e., each interruption in the light source will cause the timer count value
to increase). Figure 2-48 lists the code to set up the 80186
timer in this mode.

iRMXTM 86 MODE OPERATION
The iAPX 186/188 integrated interrupt controllers have a
special iRMX compatibility mode of operation that allows
the use of the 80186/188 within the iRMX 86 operating
system interrupt structure. To use this mode of operation,
bit 14 in the peripheral control block relocation register
must be set and special initilization software must be
provided.

2.8.3 Interrupt Controller
The 80186 integrated interrupt controller performs the
tasks of an 8259 A type interrupt controller in a typical
microprocessor system. Figure 2-52 shows a block diagram of the integrated interrupt controller. These tasks
include synchronizing and prioritizing interrupt requests,
and request type vectoring in response to a CPU interrupt
acknowledge. Nesting is provided so interrupt service
routines for lower priority interrupts may themselves be
interrupted by higher priority interrupts. The integrated
controller has two major modes of operation, the
iRMX-86 mode and the non-iRMX 86 (master) mode. In
the master mode the integrated interrupt controller can be
the master controller for up to two external Intel 8259 A
interrupt controllers allowing up to 128 interrupts. In the
iRMX 86 mode it can be the slave to an external interrupt
controller to allow compatibility with the iRMX86 operating system and the 80130/80150 operating system coprocessors (refer to Volume I ofthis User's Manual).

When the iRMX mode is used, the internal interrupt controller is used as a slave controller to an external interrupt
controller. The internal 80186/188 resources are monitored through the internal interrupt controller, and the external interrupt controller functions as the system master
interrupt controller. When an external interrupt controller
(such as an 8259A) is used it requires additional control
pins from the 80186. Therefore, some of the external interrupt pins are no longer used for external interrupt inputs. Since the external interrupt registers are no longer
required, the unused registers can now be used by the
timers. There are enough of these unused registers to dedicate one to each timer. Previously all of the timers shared
one register. In this mode of operation each timer interrupt source has its own mask bit, IS bit and control word.

The 80186 can receive interrupts from a number of
sources, both internal and external. The internal interrupt
controller merges these requests on a priority basis, for
individual service by the CPU.

The iRMX 86 operating system requires peripherals to be
assigned fixed priority levels. This is incompatible with
the normal operation of the 80186/188 interrupt controller. Therefore the initialization software must program the
proper priority for each source. The required priority levels for the internal interrupt sources in the iRMX 86 mode
are shown in Table 2-24. These priority level assignments
must remain fixed in the iRMX mode of operation.

Internal interrupt sources (Timers and DMA channels)
are disabled by their own control registers or by mask bits
within the interrupt controller. The 80186 interrupt controller has its own control registers that set the controller
mode of operation.

The iRMX 86 mode of operation allows nesting of interrupt requests. The configuration of the 80186/188 with
respect to an external 8259 A master is shown in Figure
2-59

210912·001

80186/80188 CPU

$mod186
name
this file contains example 80186 timer routines. The first routine
sets up the timer and interrupt controller to cause the timer
to generate an interrupt every 10 milliseconds, and to service
interrupt to implement a real time clock. Timer 2 is used in
this example because no input or output signals are required.
The code example assumes that the peripheral control block has
not been moved from its reset location (FFOO·FFFF in I/O space).
word ptr [BP
word ptr [BP
word ptr [BP
19
OFF66h
OFF62h
OFF32h
OFF22h
OFF30h

+ 4]
+ 6]
+ 8]

argl
arg2
arg3
timer.2int
timer.2control
timer.2malLcti
timer.inLcti
eoLregister
interrupLstat

equ
equ
equ
equ
equ
equ
equ
equ
equ

data
msec_
hOUL
minute_
seconcL.
data

segment
public
db
db
db
db
ends

cgroup
dgroup

group
group

code
data

code

segment
public
assume

seUime.
cs:code,ds:dgroup

timer 2 has vector type 19
interrupt controller regs

public 'data'
hour.,minute.,second.,msec_

?
?
?

public 'code'

seuime(hour,minute,second) sets the time variables, initializes the
80186 timer2 to provide interrupts every 10 milliseconds, and
programs the interrupt vector for timer 2
seuime.

proc
enter
push
push
push
push

near
0,0
AX
DX
SI
DS

xor

AX,AX

mov

DS,AX

mov

S[,4

set stack addressability
save registers used

set the interrupt vector
the timers have unique
interrupt
vectors even though they share
the same control register

* timer2.int

Figure 2-48 Example Timer Interface Code (Sheet 1 of 4)

2·60

210912·001

80186/80188 CPU

timer2-interrupLroutine

mov
inc
inc
mov
pop

os: [SI] ,offset timer_2-interrupLroutine
SI
SI
OS: [SI],CS
OS

mov
mov
mov
mov
mov
mov
mov

AX,argl
hour_,AL
AX,arg2
minute_,AL
AX,arg3
second.,AL
msec_,O

set the time values

mov
mov

OX,timer2_malLcti
AX,20000

set the max count value
10 ms /500 ns (timer 2 counts
at 1/4 the CPU clock rate)

out
mov
mov

OX,AX
OX,timer2_control
AX,II1000000000000 1b

out

OX,AX

mov
mov

OX,timer-inLctl
AX,OOOOb

out
sti

OX,AX

pop
pop
pop
leave
ret
endp

SI
OX
AX

proc
push
push

far
AX
OX

cmp
jae
inc
jmp

msec_,99
bump_second
msec_
reseLinLcti

see if one second has passed
if above or equal...

mov
cmp
jae
inc
jmp

msec_,O
second_,59
bump_minute
second_
reseLinLcti

reset millisecond
see if one minute has passed

mov
cmp
jae
inc
jmp

second.,O
minute_,59
bump_hour
minute_
reseLinLctl

set the control word
enable counting
generate interrupts on TC
continuous counting

set up the interrupt controller
unmask interrupts
highest priority interrupt
enable processor interrupts

bump.second:

bump_minute:
see if one hour has passed

Figure 2-48 Example Timer Interface Code (Sheet 2 of 4)

2-61

210912-001

80186/80188 CPU

bumpllour:
mov
cmp
jae
inc
jmp

minute.,O
hour.,12
reset.hour
hour.
reseLint.ctl

mov

hour., I

mov
mov
out

OX,eoLregister
AX,8000h
OX,AX

pop
pop
iret
endp
ends
end

OX
AX

see if.12 hours have passed

reseLhour:
reseLint.ctl:

timer2JnterrupLroutine
code
$mod186
name

non·specific end of interrupt

example.80 I 86.baud.code

this file contains example 80186 timer routines. The second routine
sets up the timer as a baud rate generator. In this mode,
Timer I is used to continually output pulses with a period of
6.5 usec for use with a serial controller at 9600 baud
programmed in divide by 16 mode (the actual period required
for 9600 baud is 6.51 usec). This assumes that the 80186 is
running at 8 MHz. The code example also assumes that the
peripheral control block has not been moved from its reset
location (FFOO-FFFF in I/O space).

,
timer Lcontrol
timer LmalLcnt

equ
equ

OFF5Eh
OFF5Ah

code

segment
assume cs:code

public 'code'

set-baudO initializes the 80186 timer! as a baud rate generator for
a serial port running at 9600 baud
set-baud.

proc
push
push

near
AX
OX

mov
mov
out
mov
mov

OX,timerLmalLcnt
AX,13
OX,AX
OX,timerLcontrol
AX, 11 0000000000000 1b

out

OX,AX

save registers used
set the max count value
500ns * 13 - 6.5 usec
set the control word
enable counting
no interrupt on TC
continuous counting
single max count register

Figure 2-48 Example TImer Interface Code (Sheet 3 of 4)

2-62

210912.001

80186/80188 CPU

seLbaud..
code
$modl86
name

pop
pop
ret
endp
ends
end

DX
AX

example_80 I 86_counLcode

this file contains example 80186 timer routines. The third routine
sets up the timer as an external event counter. In this mode,
Timer I is used to count transitions on its input pin. After
the timer has been set up by the routine, the number of
events counted can be directly read from the timer count
register at location FF58H in I/O space. The timer will
count a maximum of 65535 timer events before wrapping
around to zero. This code example also assumes that the
peripheral control block has not been moved from its reset
location (FFOO-FFFF in I/O space).
timerl_control
timer LmalLcnt
timer LcnLreg

equ
equ
equ

OFF5Eh
OFF5Ah
OFF58H

code

segment
assume

cs:code

public 'code'

seLcountO initializes the 80186 timer I as an event counter
seLcounL

seLcounL
code

proc
push
push

near
AX
DX

mov
mov

DX, timer l_malLcnt
AX,O

out
mov
mov

DX,AX
DX,timerLcontrol
AX, II 00000000000 I 0 I b

out

DX,AX

xor
mov
out

AX,AX
DX,timerLcnLreg
DX,AX

pop
pop
ret

DX
AX

save registers used

set the max count value
allows the timer to count
all the way to FFFFH
set the control word
enable counting
no interrupt on TC
continuous counting
single max count register
external clocking

zero AX
and zero the count in the timer
count register

endp
ends
end

Figure 2-48 Example Timer Interface Code (Sheet 4 of 4)

2-63

210912-001

80186/80188 CPU

+ 5V

fully nested modes of operation. Five pins are provided
for external interrupt sources. One of these pins is dedicated to NMI. The other four (INTO-INT3) may be configured in three ways. The response to internal interrupts is
identical in all three modes, but the function of the four
external interrupt pins differs in each mode. The interrupt
controller is set to one of these modes by programming
the correct bits in the INTO and INTI control registers.

TMR IN 1
TMR OUT 1
TIMER

o

TMR INO

Figure 2·49 80186 Real Time Clock
2-53. The INTO input is used as the 80186 CPU interrupt
input. INT3 functions as an output to send the 80186
slave-interrupt-requests to one of the 8 master-PIC-inputs.
Correct master-slave interface requires decoding of the
slave addresses (CASO-2). Because of pin limitations, the
80186 slave address will have to be decoded externally.
INTI * is used as a slave-select input. In this configuration
the slave vector address is transferred internally, but the
READY input must be supplied externally. INT2 * is used
as an acknowledge output, suitable to drive the INTA *
input of an 8259A.

In the fully nested mode of operation, the four pins are
configured as four interrupt input lines with internally
generated interrupt vectors. In both the cascade and the
special fully nested modes of operation the four interrupt
input pins can be configured as either three interrupt input
lines and interrupt a~knowledge output, or two interrupt
inputs lines and two dedicated interrupt acknowledge output lines. In the cascade mode of operation, when two
interrupts are received from the same interrupt controller,
one after the other, the internal controller will wait until
the service routine for the first is complete before acknowledging the second internal interrupt. When this occurs in the special fully nested mode, the second interrupt
from the same cascaded interrupt controller is assumed to
be of higher priority and will be acknowledged before the
first interrupt service routind is completed. These four
interrupt inputs can be programmed in either edge-or
level-trigger mode, as specified by the LTM bit in the
source's control register.
The interrupt controller will generate interrupt vectors for
the integrated DMA channels and the integrated timers. In
addition, interrupt vectors for the external interrupt lines
will be generated if they are not configured in cascade, or
special fully nested mode.

NON·iRMXTM 80 MODE

Each interrupt source has a preassigned vector type (see
Thble 2-21). Vector types point to address information for
interrupt service routines. The vectors generated are fixed
and cannot be changed.

When configured in the non-iRMX 86 mode, the internal
interrupt controller operates in one of three basic modes:
the fully nested mode, the cascade mode, and the special

80186

-

The user can program the interrupt sources into any of
eight different priority levels. Programming is done by
placing a 3-bit priority level (0-7) in the control register of
each interrupt source. (A source priority of 4 has higher
priority over all priority levels from 5-7. Priority registers
containing values lower than 4 have higher priority.) All
interrupt sources have preprogrammed default priority
levels.

+ 5V
TMRINOt

TIMER

-

0

TMROUTO

If two requests with the same programmed priority level
are pending at once, the priority ordering scheme indicated in Table 2-21 is used. If the serviced interrupt routine reenables interrupts it allows other requests to be
serviced.

TxC } SERIAL
RxC CONTR'OLLER

CONTROL REGISTERS
The interrupt controller contains registers that control its
operation (see Figure 2-54). Certain registers change

Figure 2·50 80186 Baud Rate Generator
2-64

210912·001

80186/80188 CPU

o
o

80186

o

TMRINO

3Q-LIGHT
"/

Figure 2·51 80186 Event Counter
Table 2·24 Internal Source Priority Level
Priority Level
0
1
2

3
4

5

and the INTI control registers; Figure 2-56 shows the format of the INT2 and INT3 registers. In cascade mode or
special fully nested mode, the control words in the INT2
and INT3 registers are not used.

Interrupt Source
TimerO
(reserved)
DMA 0
DMA1
Timer 1
Timer 2

INTERRUPT SOURCES
The 80186 interrupt controller receives and arbitrates
among many different interrupt request sources, both internal and external. Each interrupt source may be programmed to be a different priority level in the interrupt
controller. Figure 2-57 shows an interrupt request generation flow chart. Such a flowchart would be followed independently by each interrupt source.

their modes of operation between the two major modes of
the interrupt controller: master mode and iRMX86 mode.
These control registers include the Timer Register, two
DMA registers, and four external input registers. The
Timer and the DMA registers are used for interrupt controller interaction with the internal DMA and Timer units
of the processor. Refer to Volume I of this User's Manual
for full descriptions of these registers. The external input
registers are of the greatest concern to the hardware
designer.

Internal Interrupt Sources

The external input registers contain the control words for
the four external interrupt input pins. See Figures 2-55
and 2-56. Figure 2-55 illustrates the format of the INTO

TIMER TIMER TIMER OMA
o
2
0

The 80186 internal interrupt sources include three timers
and the two DMA channels. These sources operate independently of external devices as regards to interrupts to

OMA
INTO

INn

INT2

INTJ

NMI

INTERRUPT
REaUEST REG
OMAO
CONTROL REG.

INTERRUPT

DM"1
CONTROL REG

IN·SERVICE
REG
PRIOR. lEV.
MASK REG

EXT INPUT 0
CONTROL REG

EXT. INPUT 1

MASK REG

PRIORITY
RESOLVER

CONTROL REG

INTERRUPT
STATUS REG.

EXT. INPUT 2
CONTROL REG

Figure 2·52 Interrupt Controller Block Diagram

2-65

210912-001

80186/80188 CPU

82SU.
MASTER

., INTl
80118 'NT. IN

<==

lOa

REQUESTS FROM

OTHER SLAVES

INT

1

.,.

-

107
CA..... '

~

INTO

IiiI'fi

SlA"vtSELECf

II

CASCADE

ADDRESS DECODER

I

jjffi t-INTl

101. SLAVE INTERRUPT OUTPUT

Figure 2·53 iRMXTM 86 Interrupt Controller Interconnection
;RMX86~

Mode

MASTER MODE

OFFSET ADDRESS

INT3 CONTROL REGISTER

3EH

CD

3CH
3AH

===========0===========

38H

TIMER 1 CONTROL REGISTER

DMAI CONTROL REGISTER

36H

DMAI CONTROL REGISTER

DMAO CONTROL REGISTER

34H

DMAO CONTROL REGISTER

TIMER CONTROL REGISTER

32H

TIMER 0 CONTROL REGISTER

INTERRUPT CONTROLLER STATUS REGISTER

30H

INTERRUPT CONTROLLER STATUS REGISTER

INTERRUPT REQUEST REGISTER

2EH

INTERRUPT REQUEST REGISTER

INT2 CONTROL REGISTER
INTI CONTROL REGISTER
----------------------INTO CONTROL REGISTER

TIMER 2 CONTROL REGISTER

----------------------IN-SERVICE REGISTER

2CH

IN SERVICE REGISTER

PRIORITY MASK REGISTER

2AH

PRIORITY MASK REGISTER

28H

MASK REGISTER

----------------------MASK REGISTER
POLL STATUS REGISTER

== == == =====0=
=== =======_
0 __________

POLL REGISTER

26H
24H

EOI REGISTER

22H

SPECIFIC EOI REGISTER

20H

INTERRUPT VECTOR REGISTER

-----------0-----------

___________

1. Unsupported in this mode: values written mayor may not be stored

Figure 2·54 80186 Interrupt Controller Registers

15

o

I

14
0

6543210

I

o

ISFNMI

c

I LTM

I

MSK

I

PR21 PAl I PRO

I

Figure 2·55 INTOIINT1 Control Register Formats

External Interrupt Sources

the 80186. Refer to Volume I of this User's Manual for
detailed information regarding the operation of interrupts
from these sources.

The 80186 provides five dedicated pins for external interrupt sources. One of these pins is dedicated to nonmaskable interrupt, (NMI). NMI is typically used for

2-66

210912-001

80186/80188 CPU

15

14

o

0

5

I

4

3

2

1

0

Figure 2-56 INT211NT3 Control Register Format

power-fail interrupts, etc. The other four pins may function either as four interrupt input lines with internally
generated interrupt vectors, as an interrupt line and an
interrupt acknowledge line (called the "cascade mode")
along with two other input lines with internally generated
interrupt vectors, or as two interrupt input lines and two
dedicated interrupt acknowledge output lines.

mode, the external pins associated with the interrupt controller may serve either as direct interrupt inputs, or as
cascaded interrupt inputs from other interrupt controllers
as a programmed option. These options are selected by
programming the C and SFNM bits in the INTO and INTI
control registers (see Figure 2-58).
When the interrupt lines are configured in cascade mode,
the 80186 interrupt controller will not generate internal
interrupt vectors for external sources. The interrupt

When programmed in master mode, the 80186 interrupt
controller accepts external interrupt requests only. In this

NO

NO

PRESENT INTERRUPT
REQUEST TO
EXTERNAL CONTROLLER

Figure 2-57 80186 Interrupt Sequencing

2-67

210912-001

80186/80188 CPU

15

CDt

0

SPECIAL
FULLY
NESTED
BIT

CD

CAS-

LEVEL

CADE

TRIG.

MODE

CD

MODE

MASK

CD

BIT

:

:

o

PRIORITY BITS
I
I

1. This bit present only in INTO-INT3 control registers
2. These bits present only in INTO-INTl control register

Figure 2-58 Interrupt Controller Control Register
controller will generate interrupt vectors for internal
sources. External sources in the cascade mode use externally generated interrupt vectors. When an interrupt is acknowledged, the controller initiates two INTA * cycles and
reads the vector into the 80186 on the second cycle.
Therefore, the capability to interface to external 8259A
programmable interrupt controllers is provided when the
inputs are configured in cascade mode.

If the C (Cascade) bits in the INTO or INTI control registers are set, the interrupt input is cascaded to an external
interrupt controller. Whenever the interrupt presented to
the INTO or INTI line is acknowledged in this mode, the
integrated interrupt controller will not provide the interrupt type for the interrupt. Instead, two INTA bus cycles
will be run, with the INT2 and INT3 lines providing the
interrupt acknowledge pulses for the INTO and the INTI
interrupt requests respectively. INTO/INT2 and
INTlIINT3 may be individually programmed into cascade and special fully nested modes. This allows 128 individually vectored interrupt sources if two banks of nine
external interrupt controllers each are used.

The basic modes of operation on the interrupt controller
in master mode are similar to the 8259A. The interrupt
controller responds identically to internal interrupts in all
three modes: the modes differ only in the interpretation of
function of the four external interrupt pins. Programming
the correct bits in the INTO and INTI control registers
sets.

iRMXTM Mode Sources
When the interrupt controller is configured in iRMX
mode, the integrated interrupt controller accepts interrupt
requests only from the integrated peripherals. Any external interrupt requests must go through an external interrupt controller. This external interrupt controller requests
interrupt service directly from the 80186 CPU through
the INTO line on the 80186. In this mode, the function of
this line is not affected by the integrated interrupt controller. In addition, in iRMX 86 mode the integrated interrupt
controller must request interrupt service through this external interrupt controller; this interrupt request is made
on the INT3line.

When the four interrupt inputs are programmed as direct
inputs, each is controlled by an individual interrupt control register. These registers each contain three bits to select the interrupt priority level and a single bit to enable
the processor interrupt source. In addition, each control
register contains a bit which selects either the edge or
level triggered interrupt input mode. When edge triggered
mode is selected, a low-to-high transition must occur on
the interrupt input before an interrupt is generated. In
level triggered mode, only a high level needs to be maintained to generate an interrupt. In both modes, the interrupt level must remain high until the interrupt is
acknowledged (i.e., the interrupt request is not latched in
the interrupt controller). The status of the interrupt input
can be shown by reading the interrupt request register.
Each of the external pins has a bit in this register which
indicates an interrupt request on the corresponding pin.

EXTERNAL INTERFACE
The four 80186 interrupt signals can be programmably
configured into three major options. These options are
direct interrupt inputs (with the integrated controller providing the interrupt vector), cascaded (with an external
interrupt controller providing the interrupt vector), or
iRMX 86 mode. In all these modes, any interrupt presented to the external lines must remain set until the interrupt is acknowledged.

NOTE
Since interrupt requests on these inputs are not
latched by the interrupt controller, if the external input goes inactive, the interrupt request
(and also the bit in the interrupt request register) will also go inactive (low). Also, if the inter rupt input is in edge triggered mode, a
low-to-high transition on the input pin must occur before the interrupt request bit will be set
in the interrupt request register.

Direct Input Mode
Clearing cascade mode bits configures the interrupt input
lines as direct interrupt input lines (see Figure 2-59). In
this mode an interrupt source (e.g., an 8272 floppy disk
2-68

210912·001

80186/80188 CPU

vided on the INT2/INTAO* line, and will also be reflected
by interrupt acknowledge status being generated on the
SO*-S2 * status lines. On the second pulse, the interrupt
type will be read in.

80186
INTO
INn

INTERRUPT
SOURCES

.

INTO/INT2/INTAO* and INTI/INT3/INTAI * may be individually programmed into interrupt request/
acknowledge pairs, or programmed as direct inputs.
Therefore, INTO/INT2/INTAO* may be programmed as
an interrupt/acknowledge pair, while INTI and INT3/
INTAI * each provide separate internally vectored interrupt inputs.

INT2
INT3

Figure 2·59 80186 Non·Cascaded
Interrupt Connection

When an interrupt is received on a cascaded interrupt, the
priority mask bits and the in-service bits in the particular
interrupt control register are set into the interrupt controller's mask and priority mask registers. This action prevents the controller from generating an 80186 CPU
interrupt request from a lower priority interrupt.

controller) may be directly connected to the interrupt input line. Whenever an interrupt is received on the input
line, the integrated controller will do nothing unless the
interrupt is enabled, and it is the highest priority pending
interrupt. At this time, the interrupt controller will
present the interrupt to the CPU and wait for an interrupt
acknowledge. When the acknowledge occurs, it will
present the interrupt vector address to the CPU. In this
mode, the CPU will not run any interrupt acknowledge
cycles. Also, in this mode, the SFNM bit in the interrupt
control register is ignored.

As an example of the cascade mode, consider the 80186
interface to an 8259A (see Figure 2-61). The INTO and
the INT2 lines are used as direct interrupt input lines.
(Figure 2-62 lists assembly code that may be used to initialize the 80186 interrupt controller.) This configuration
provides ten external interrupt lines: two provided by the
80186 interrupt controller and eight from the 8259A. The
8259A, configured as the master controller, will only receive interrupt acknowledge pulses in response to an interrupt it has generated. It may be cascaded again with up
to eight additional 8259A's (each configured as slaves).

Cascade Input Mode
Setting the cascade mode bit and clearing the SFNM bit
configures the interrupt input lines in cascade mode. In
this mode, the interrupt input line pairs with an interrupt
acknowledge line. The INT2/INTAO* and INT3/INTAI *
lines are dual purpose; they can function as direct input
lines, or they can function as interrupt acknowledge outputs. INT2/INTAO* provides the interrupt acknowledge
for an INTO input, and INT3/INTAI * provides the interrupt acknowledge for an INTI input (see Figure 2-60).

NOTE
An interrupt ready signal must be returned to
the 80186 to prevent the generation of undesired wait states in response to the interrupt
acknowledge cycles.

When programmed in this mode, in response to an interrupt request on the INTO line, the 80186 will provide two
interrupt acknowledge pulses. These pulses will be pro-

8259A

Special Fully Nested Mode
When both the cascade mode bit and the SFNM bit are
set, the interrupt input lines are configured in the Special
Fully Nested Mode. In this mode the external interface is
identical to the Cascade Mode. The Special Fully Nested
Mode differs only in the conditions that allow an interrupt
sent from the external interrupt controller to the integrated interrupt controller to interrupt the 80186 CPU.

80186

INT

INTO

INTA

INT2

When an interrupt is received from a Special Fully Nested
Mode interrupt line, it will interrupt the 80186 CPU if it
is the highest priority interrupt pending, regardless of the
state of the in-service bit for the interrupt source in the
interrupt controller. When an interrupt is acknowledged
from a Special Fully Nested Mode interrupt line, in-serve
bits in the particular interrupt control register will be set
into the interrupt controller's in-service register. This will
prevent the interrupt controller from generating an 80186

8259A
INT

INn

INTA

INT3

Figure 2·60 Cascade and Special Fully
Nested Mode Interface
2-69

210912-001

80186/80188 CPU

80186
AROY

.J

-L

OTHERARD Y

-

INTO
10

INT2

EXTERNAL
8259A-2
INTl

INT

INT3

INTA

AOO-A07

00-07

RD

RD

WR

WR

INTERRUPTS
/

8/

+5V

SP
CS

,

U

t

PCSA

Figure 2·61 80186/8258A Interrupt Cascading
spectively supply these two signals. The external master
interrupt controller must be able to interrupt the 80186
CPU, and needs to know when the interrupt request is
acknowledged. The INTO and INT2/INTAO* lines provide these functions.

CPU interrupt request from a lower priority interrupt.
Unlike cascade mode, however, the interrupt controller
will not prevent additional interrupt requests generated by
the same external interrupt controller from interrupting
the 80186 CPU. If the external (cascaded) interrupt controller receives a higher priority interrupt request on one
of its interrupt request lines and presents it to the integrated controller's interrupt request line, it may cause an
interrupt to be generated to the 80186 CPU, regardless of
the state of the in-service bit for the interrupt line.

In the iRMX86 mode (see Figure 2-64), the 80130 interrupt controller is the master interrupt controller of the
system. The 80186 generates an interrupt request to the
80130 interrupt controller when one of the 80186 integrated peripherals has created an interrupt condition, and
that condition is sufficient to generate an interrupt from
the 80186 integrated interrupt controller. The 80130 decodes the interrupt acknowledge status directly from the
80186 status lines; thus, the INT2/INTAO* line of the
80186 need not be connected to the 81030. The circuit
illustrated by Figure 2-64 uses this interrupt acknowledge
signal to enable the cascade address decoder. The 80130
drives the cascade address on AD8-ADIO during Tl of
the second interrupt acknowledge cycle. This cascade address is latched into the system address latches, and if the
proper cascade address is decoded by the 8205 decoder,
the 80186 INTlISLAVE SELECT* line will be driven active, enabling the 80186 integrated interrupt controller to
place its interrupt vector on the internal bus. (See Figure
2-62 for the code to configure the 80186 into iRMX 86
mode.)

If the SFNM mode bit is set, but the cascade mode bit is
not set, the controller provides internal interrupt vectoring. The controller also ignores the state of the in-service
bit in determining whether to present an interrupt request
to the CPU. In other words, it uses the SFNM conditions
of interrupt generation with an internally vectored interrupt response (i.e., if the interrupt pending is the highest
priority type pending, it will cause a CPU interrupt regardless of the state of the in-service bit for the interrupt).
iRMX Mode

When the RMX bit in the peripheral relocation register is
set, the interrupt controller is set into iRMX 86 mode. In
this mode, all four interrupt controller input lines are used
to perform the necessary handshaking with the external
master interrupt controller (see Figure 2-63).

Interrupt Latency
Because the integrated interrupt controller is a slave controller, it must be able to generate an interrupt input for an
external interrupt controller. It also must be signaled
when it has the highest priority pending interrupt to know
when to place its interrupt vector on the bus. The INT3/
Slave Interrupt Output and INTI/Slave Select* lines, re-

Interrupt latency time is the period of time between the
time the 80186 receives the interrupt to the time it begins
to respond to the interrupt. Interrupt latency differs from
interrupt response time, which is the time from when the
processor actually begins processing the interrupt to when
2-70

210912-001

80186/80188 CPU

$modl86
name

example.80 I 86JnterrupLcode

This routine configures the 80186 interrupt controller to provide
two cascaded interrupt inputs (through an external 8259A
interrupt controller on pins INTO/INT2) and two direct
interrupt inputs (on pins INTI and INn). The default priority
levels are used. Because of this, the priority level programmed
into the control register is set the III, the level all
interrupts are programmed to at reset.
intO.control
inLmask

equ
equ

OFF38H
OFF28H

code

segment
assume
proc
push
push

CS:code
near
OX
AX

mov

AX,OIOOIlIB

mov
out

OX,intO.control
OX,AX

mov

AX,OIOOIlOIB

mov
out
pop
pop
ret
endp
ends
end

OX,inLmask
OX,AX
AX
OX

seLinL

seUnL
code
$modl86
name

public 'code'

cascade mode
interrupt unmasked

now unmask the other external
interrupts

example.80186JnterrupLcode

This routine configures the 80186 interrupt controller into iRMX 86
mode. This code does not initialize any of the 80186
integrated peripheral control registers, nor does it initialize
the external 8259A or 80130 interrupt controller.
reloca tion.reg

equ

OFFFEH

code

segment
assume
proc
push
push

CS:code
near
OX
AX

mov
in
or
out

OX,relocation.reg
AX,OX
AX,O I OOOOOOOOOOOOOOB
OX,AX

seLrmlL

public 'code'

read old contents of register
set the RMX mode bit

Figure 2-62 Example Interrupt Controller Interface Code

2-71

210912-001

80186/80188 CPU

80186

When interrupts are enabled in the CPU, the interrupt latency is a function of the instructions being executed.
Only repeated instructions will be interrupted before being completed, and those only between their respective
iterations. Therefore, the interrupt latency time could be
as long as 69 CPU clocks-the time it takes the processor
to execute an integer divide instruction (with a segment
override prefix) the longest single instruction on the
80186.

8259A

-

INTO

INT

INT2

INTA

INn

CASCADE
ADDR.
DECODE

0

Other factors can affect interrupt latency. An interrupt
will not be accepted between the execution of a prefix
(such as segment override prefixes and lock prefixes) and
the instruction. In addition, an interrupt will not be accepted between an instruction which modifies any of the
segment registers and the instruction immediately following the instruction. This interrupt denial is required to
allow the stack to be changed. If the interrupt were accepted, the return address from the interrupt would be
placed on a stack which was not valid (the Stack Segment
register would have been modified but the Stack Pointer
register would not have been). Finally, an interrupt will
not be accepted between the execution of the WAIT instruction and the instruction immediately following it if
the TEST* input is active. If the WAIT sees the TEST*
input inactive, however, the interrupt will be accepted,
and the WAIT will be re-executed after the interrupt

INT3

Figure 2·63 80186 iRMXTM 86 Mode Interface

it actually executes the first instruction of the interrupt
service routine. The factors affecting interrupt latency are
the instruction being executed and the state of the interrupt enable flip-flop. Interrupts will be acknowledged
only if the interrupt enable flip-flop in the CPU is set.
Therefore, interrupt latency will be very long indeed if
interrupts are never enabled by the processor!

80186
ALE

ADDR

r-

)8

ADO·AD15

/

ClK

AO-A15

lATCH

11'3

80130
ADO-AD15

A8·A 10

/

ClK

MMCS2

MEMCS
IRO·
IOCS IR7

PCS3
/3

Slj.S2

/

SHE

L8
/

L7
/

INTERRUPT
REQUESTS

SO-S2
SHE
INT

J

INTO
INT3

+5
8205
E2
E3
INT2
INn

-

~

E1
7

Figure 2·64 80186/80130 iRMXTM 86 Mode Interface

2·72

210912-001

80186/80188 CPU

In master mode, the integrated interrupt controller is the
master system interrupt controller. Therefore, no external
interrupt controller needs to be informed when the integrated controller is providing an interrupt vector or when
interrupt acknowledge is taking place. As a result, no interrupt acknowledge bus cycles will be generated. The
first external indication that an interrupt has been acknowledged will be the processor reading the interrupt
vector from the interrupt vector table to low memory.

Table 2-25 80186 Interrupt Vector Types
Interrupt
Name

Vector
Type

Default
Priority

timer 0
timer I
timer 2
DMAO
DMAI
INTO
INT I
INT 2
INT 3

8

18
19
10
II
12
13
14
15

Oa
Ob
Oc
2
3
4
5
6
7

Since the two interrupt acknowledge are not run, and the
interrupt vector address does not need to be calculated,
interrupt to an internally vectored interrupt is 42 clocks
cycles, which is faster than the interrupt response when
external vectoring is required, or the interrupt controller
is run in the iRMX 86 mode.

return. Re-executing WAIT is required, since the WAIT is
used to prevent execution by the 80186 of an 8087 instruction while the 8087 is busy.

If two interrupts of the same programmed priority occur,

the default priority scheme (see Table 2-25) is used.

INTERRUPT RESPONSE TIMING

Internal Vectoring, iRMXTM 86 Mode

The 80186 can respond to an interrupt in two different
ways. The first will occur if the internal controller is providing the interrupt vector information with the controller
in master mode. The second will occur if the CPU reads
interrupt type information from an external interrupt controller or if the interrupt is in the iRMX 86 mode. In both
of these instances the interrupt vector information driven
by the 80186 integrated interrupt controller is not available outside the 80186 microprocessor.

In the iRMX mode of operation the interrupt types associated with the various interrupt sources can be changed.
The upper 5 most significant bits are taken from the interrupt vector register, and the lower 3 significant bits are
taken from the priority level of the device causing the
interrupt. Since the interrupt type, instead of the interrupt
vector address, is given by the interrupt controller in this
mode the interrupt vector address must be calculated by
the CPU before servicing the interrupt.

In each interrupt mode the interrupt controller will automatically set the in-service bit when the integrated interrupt controller receives an interrupt response, and reset
the interrupt request bit in the integrated controller. The
priority mask bits are set by writing to the register only
(except on RESET when they are set to 7). The priority
mask bits will remain one value and prevent lower priority
interrupts from occurring until the programmer resets or
changes the register.

Internal Vectoring, Master Mode

In this mode of operation the integrated interrupt controller will present the interrupt type to the CPU in response
to the two interrupt acknowledge bus cycles run by the
processor. During the first interrupt acknowledge cycle,
the external master interrupt controller determines which
slave interrupt controller will be allowed to place its interrupt vector on the microprocessor bus. During the second
interrupt acknowledge cycle, the processor reads the interrupt vector from its bus. Therefore, these two interrupt
acknowledge cycles must be run since the integrated controller will present the interrupt type information only
when the external interrupt controller signal the integrated controller that it has the highest pending interrupt
request (see Figure 2-65). The 80186 samples the SLAVE
SELECT* line during the falling edge of the clock at the
beginning of T3 of the second interrupt acknowledge cycle. This input must be stable 20ns before and IOns after
this edge.

In the master mode of operation, the interrupt types associated with all interrupt sources are fixed and unalterable
(see Table 2-25). In response to an internal CPU interrupt
acknowledge the interrupt controller will generate the
vector address instead of the interrupt type. On the 80186,
as with the 8086, the interrupt vector address is the interrupt type multiplied by 4. This speeds up the interrupt
response time.

These two interrupt acknowledge cycles will be run back
to back, and will be LOCKED with the LOCK* (see paragraph 2.5.3) output active (meaning that DMA requests
and HOLD requests will not be honored until both cycles
have been run). Note that the two interrupt acknowledge
cycles will always be separated by two idle T state, and
that the wait states will be inserted into the interrupt acknowledge cycle if a ready is not returned by the

In addition, unless the interrupt control for the interrupt is
set in Special Fully Nested Mode, the interrupt controller
will prevent any interrupts from occurring from the same
interrupt line until the in-service bit for that line has been
cleared.

2-73

210912·001

80186/80188 CPU

T,

T,

T,

T,

T,

CLKOUT

T,

I

S~S2 --~~-----+:-----+I-r--~----~----~---r~:----~I-----fl~+-_+-----

I

INTO
(HIGH)

I

I

I

INTERRUPT ACKNOWLE GE

I

I

INTERRUPT ACKNOWLEDGE
I

I

I

---i----i----i---i----j----i---i----j----i'-f--;---

__

INT3 ___~--~--+_--~-~--~--~--+_~-~--_
(HIGH)
=-~--~-,,~--~--~--~--~--~--~~~-,
CAS
80186 SLAVE ENABLE CASCADE ADDRESS FROM 8259A

CD

-----+-----+--'\--+-----7'----~'----~'----~'----~'----~'----_+--,'--

INTA

:.I

~...._ - , -_ _ _ _ _ _
I

--

I

I

LOCK -----:\

I~--_+----_r-----r-----r----_r----f-----~,
I
I

1. SLAVE SELECT = INT1
2. INTA = INT2
3. Driven by external interrupt controller
4. SLAVE SELECT must be driven before Phase 2 of T2 of the second INTA
cycle _ __
5. SLAVE SELECT read by 80186

Figure 2·65 80186 iRMXTM 86 Mode Interrupt Acknowledge Timing
processor bus interface. The two idle T states are inserted
to allow compatibility with the timing requirements of an
external 8259A interrupt controller.

bus cycles, and that wait states will be inserted in the interrupt acknowledge cycle if a ready is not returned to the
processor. Also notice that the 80186 provides two interrupt acknowledge signal, one for interrupts signaled by
the INTO line, and one for interrupts signaled by the INTI
line (on INT2/INTAO* and INT3/INTAI * lines, respectively). These two interrupt acknowledge signals are mutually exclusive. Interrupt acknowledge status will be
driven on the status lines (50*-52*) when either INT2/
INTAO* or INT3/INTAI * signal an interrupt
acknowledge.

Because the interrupt acknowledge cycles must be run in
iRMX 86 mode, even for internally generated vectors,
and the integrated controller presents an interrupt type
rather than a vector address, the interrupt response time
here is the same as if an externally vectored interrupt was
required, in other words 55 clocks.

External Vectoring
External interrupt vectoring occurs whenever the 80186
interrupt controller is placed in the cascade mode, special
fully nested mode, or iRMX 86 mode (and the integrated
controller is not enabled by the external master interrupt
controller). In this mode, the 80186 generates two interrupt acknowledge cycles, reading the interrupt type off
the lower 8 bits of the address/data bus on the second
interrupt acknowledge cycle (see Figure 2-66). This interrupt response is exactly the same as the 8086, so that the
8259A interrupt controller can be used exactly as it would
in an 8086 system. Notice that the two interrupt acknowledge cycles are LOCKED, and that two idle T-states are
always inserted between the two interrupt acknowledge

2.8.4 Chip Select/Wait State Generation
Unit
The 80186/188 CPU contains an integrated chip select
unit which provides programmable chip-select' generation
logic for both the memories and peripherals. This unit can
also be programmed to provide WAIT state (READY)
generation and can provide latched address bits A 1 and
A2. The chip select lines are active for all memory and
I/O cycles in their programmed areas, whether the cycles
are generated by the CPU of the integrated DMA unit.

2-74

210912-001

80186/80188 CPU

so- S2

INTA

ADO-AD7 --~----~----~----~----~----~--~~--~--~

I
I

I

INTERRUPT TYPE
(FROM EXTERNAL
CONTROLLER)

Figure 2·66 80186 Cascaded Interrupt Acknowledge Timing
MEMORY CHIP SELECTS

chip select may also be selected. Only one chip select may
be programmed to be active for any memory location at a
time. All chip select sizes are in bytes, whereas iAPX 186
memory is arranged in words. For example, if16 64K xl
memories are used, the memory block size will be 128K,
not 64K. The upper limit of UCS* and the lower limit of
LCS* are fixed at FFFFFH and OH in memory space,
respectively. The other limit of these is set by the memory
size programmed into the control register for the chip select line. Mid-range memory allows both the base address
and the block size of the memory area to be programmed.
The only limitation is that the base address must be programmed to be an integer multiple of the total block size.
For example, if the block size was 128K bytes (four 32K
byte blocks) the base address could be 0 or 20000H, but
not 10000H.

The 80186 provides six discrete chip select lines which
connect to memory components in an iAPX186 system.
These lines (see Figure 2-67) output signals for three
memory areas: upper memory (UCS*), lower memory
(LCS*), and mid-range memory (MCSO-3*).
The range for each chip select is user-programmable and
can be set to 2K, 4K, 8K, 16K, 32K, 64K, 128K (plus lK
and 256K for upper and lower chip selects). In addition,
the beginning or base address of the mid-range memory

FFFFF
STARTUP

UCS

1
MCS3

MCS2

{

ROM

Four registers in the peripheral control block (see Figure
2-68) control the memory chip selects. These selects include one each for UCS* and LCS*, the values of which
determine the size of the memory blocks addressed by
these two lines. The other two registers control the size
and base address of the mid-range memory block.

---

{ --PROGRAM
MEMORY

On reset, only UCS* is active. Reset programs it to be
active for the top lK memory block, to insert three wait
states to all memory fetches, and to factor external ready
for every memory fetch. All other chip select registers
assume indeterminate states after reset, but none of the
other chip select lines will be active until all necessary
registers for a chip select have been accessed (not necessarily written, a read to an uninitialized register will enable the chip select function controlled by that register).

MCS1 {

--MCSO

{
INTERRUPT
VECTOR

'" 1

TABLE

0

Generally, the chip selects of the 80186 should not be programmed such that any two areas overlap. In addition,
none of the programmed chip select areas should overlap

Figure 2·67 80186 Memory Areas and Chip
Selects

2-75

210912-001

80186/80188 CPU

Table 2·26 UMCS Programming Values
OFFSET:

AOH

UPPER MEMORY SIZE

CD

UMCS

A2H

LOWER MEMORY SIZE

CD

LMCS

A4H

PERIPHERAL CHIP SELECT BASE ADDRESS

PACS

A6H

MID-RANGE MEMORY BASE ADDRESS

A8H

MID-RANGE MEMORY SIZE

CD
CD
CD

Ii I ~1

MMCS
MPCS

CD
1. Upper memory ready bits
2. Lower memory ready bits
3. PCSO-PCS3 ready bits
4. Mid-range memory ready bits
5. PCS4-PCSS ready bits
S. MS: 1 ~ Peripherals active in memory space
~ Peripherals active in 1/0 space
EX:1 ~ 7 PCS lines
o ~ PCS5 ~ A1, PCS6 ~ A2

Starting
Address
(Base
Address)

Memory
Block
Size

FFCOO
FF800
FFOOO
FEOOO
FCOOO
FBOOO
FOOOO
EOOOO
CODOC

1K
2K
4K
8K
16K
32K
64K
126K
256K

UMCS Value
(Assuming
RO=Rl =R2=O)
FFF8H
FFB8H
FF38H
FE38H
FC3BH
F838H
F036H
E038H
C038H

operation. After reset, the UMCS register is programmed
for a lK area. It must be reprogrammed if a larger upper
memory area is desired.

o

Any internally generated 20-bit address whose upper 16
bits are greater than or equal to UMCS (with bits 0-5
"0") will cause UCS to be activated. UMCS bits R2-RO
are used to specify READY mode for the area of memory
defined by this chip-select register.

Not all bits of every field are used

Figure 2·68 80186 Chip Select Control Registers

any of the locations of the integrated 256-byte control register block, If such an overlap condition exists, whenever
two chip select lines are programmed to respond to the
same area, both will become active during any access to
that area. When programmed as such, the ready bits for
both areas must be programmed to the same value. If not
programmed in this manner, the processor response to an
access in this area is indeterminate. If any of the chip
select areas overlap the integrated 256-byte control register block, the timing on the chip select line is altered. As
always, the CPU ignores any values returned on the external bus from this access.

Lower Memory CS·

The 80186 provides a chip select for low memory called
LCS*. The bottom of memory contains the interrupt vector table, starting at location OOOOOH.
The lower limit of memory defined by this chip select is
always Oh, while the upper limit is programmable. By
programming the upper limit, the size of the memory
block is also defined. Table 2-27 shows the relationship
between the upper address selected and the size of the
memory block obtained.
The upper limit of this memory block is defined in the
LMCS register (see Figure 2-70). This register is at offset
A2H in the internal control block. The legal values for
bits 6-15 and the resulting upper address and memory
block sizes are given in Table 2-27. Any combination of
bits 6-15 not shown in Table 2-27 will result in undefined
operation. After reset, the LMCS register value is undefined. However, the LCS* line will not become active until the LMCS register is accessed.

Upper Memory CS·

The 80186 provides a chip select, called UCS *, for the
top of memory, The top of memory is usually used as the
system memory because, after reset, the 80186 begins executing at memory location FFFFOH.
The upper limit of memory defined by this chip select is
always FFFFFH, while the lower limit is programmable.
By programming the lower limit, the size of the select
block is also defined. Table 2-26 shows the relationship
between the base address selected and the size of the
memory block obtained.

Any internally generated 20-bit address whose upper 16
bits are less than or equal to LMCS (with bits 0-5 "1")
will cause LCS* to be active, LMCS register bits R2-RO
are used to specify the READY mode for the area of
memory defined by this chip-select register.

The lower limit of this memory block is defined in the
UMCS register (see Figure 2-69). This register is at offset
AOH in the internal control block. The legal values for
bits 6-13 and the resulting starting address and memory
block sizes are given in Table 2-26. Any combination of
bits 6-13 not shown in Table 2-26 will result in undefined

Mid·Range CS·

The 80186 provides four MCS® * lines which are active
within a user-locatable memory block. This block can be
2-76

210912-001

80186/80188 CPU

15
OFFSET:

14

13

12

11

10

AOHI 1 I 1
A19

U

U

U I

u

6

2

1

0

I u I u I u I u I 1 I 1 I 1 I R2 I Rl I RO I
All

Figure 2·69 UMCS Register

15
OFFSET:

A2H I 0
A19

14

13

12

11

10

0

u

u

u

u

8

Iu

0

1

6

Iu

u

u
All

I 1 I1 I1

R2

I Rl I RO I

Figure 2·70 LMCS Register

15
OFFSET:

A8H I 1

14

13

12

11

10

9

8

7

2

6

I~I~I~I~I~I~I~I~I~I

1

1

0

I 1 I 1 I R2 I Rl I RO I

Figure 2·71 MPCS Register

NOTE

located anywhere within the iAPX 186 1M byte memory
address space exclusive ofthe areas defined by UCS* and
LCS*. Both the base address and size of this memory
block are programmable.

This register is located at A8H in the internal
control block. Only one of bits 8-14 must be
set at a time or unpredict able operation of the
MCS* lines will otherwise occur.

The size of the memory block defined by the mid-range
select lines (refer to Table 2-28), is determined by bits
8-14 of the MPCS register (see Figure 2-71).

Each of the four chip-select lines is active for one of the
four equal contiguous divisions of the mid-range block.
Therefore, if the total block size is 32K, each chip select
is active for 8K of memory with MCSO* being active for
the first range and MCS3* being active for the last range.

Table 2·27 LMCS Programming Values
Upper
Address

003FFH
007FFH
OOFFFH
01FFFH
03FFFH
07FFFH
OFFFFH
1FFFFH
3FFFFH

Memory
Block
Size

1K
2K
4K
8K
16K
32K
64K
128K
256K

The base address of the mid-range memory block is defined 15-9 of the MMCS register (see Figure 2-72) located at offset A6H in the internal control block. These
bits correspond to bits A19-A13 of the 20-bit memory
address. Bits AI2-AO of the base address are always O.
The base address may be set at any integer multiple of the
size of the total memory block selected. For example, if
the mid-range block size is 32K (or the size of the block
for which each MCS* line is active is 8K), the block
could ocated at 10000H or 18000H, but not at 14000H,
since the first few integer multiples of a 32K memory
block are OH, 8000H, 10000H, 18000H, etc. After reset,
the contents of both of these registers is undefined. However, none of the MCS* lines will be active until both the
MMCS and MPCS registers are accessed.

LMCS Value
(Assuming

RO=R1 =R2=O)
0038H
0078H
00F8H
01F8H
03F8H
07F8H
OFF8H
1FF8H
3FF8H

Table 2·28 MPCS Programming Values
Total Block
Size

Individual
Select Size

8K
16K
32K
64K
128K
256K
512K

2K
4K
8K
16K
32K
64K
128K

MPCS Bits

MMCS bits R2-RO specify READY mode of operation for
all mid-range chip selects. All devices in mid-range memory must use the same number of WAIT states.

14-8
00000018
00000108
00001008
00010008
00100008
01000008
10000008

The 512K block size for the mid-range memory chip selects is a special case. When using 512K, the base address
would have to be at either locations OH or 80000H. If it
were to be programmed at OH when the LCS* line was

2-77

210912·001

80186/80188 CPU

o

15

OFFSET:

A8H

Iu Iu Iu IU

ululull1111111111

A19

R2

RllROI

A13

Figure 2·72 MMCS Register
programmed, there would be an internal conflict between
the LCS* ready generation logic and the MCS* ready
generation logic. Likewise, if the base address were programmed at 80000H, there would be a conflict with the
UCS* ready generation logic. Since the LCS* chip-select
line does not become active until programmed, while the
UCS* line is active at reset the memory base can be set
only at OH. If this base address is selected, however, the
LCS* range must not be programmed.

tion circuit may be programmed to ignore external
READY signals (i.e., only the internal ready circuit will
be used) or to factor the external READY signal (i.e., a
ready will be returned to the processor only after both the
internal ready circuit has gone ready and the external
ready has gone ready). Also, when a memory access occurs where there is no programmed chip select, ARDY
and SRDY may be used to insert wait states as in the 8086
system.
A circuit must be included, however, to generate an external ready since, at reset, the READY generator is programmed to factor external READY to all accesses to the
top IK byte memory block. If a READY was not returned
on one of the external ready lines (ARDY or SRDY) the
processor would wait indefinitely to fetch the first
instruction.

INPUT/OUTPUT PERIPHERAL CHIP SELECTS
Since 80186 memory interfacing is similar to the 8086,
the two processors are also similar when interfacing to
I/O peripherals. The 80186 contains integral interfacing
logic that provides seven discrete chip select lines
(PCSO-6*). These seven chip select lines are intended for
connection to 110 peripherals in an iAPX86 system. The
signals on these lines, PCSO-6*, go active for one of
seven contiguous 128-byte areas in memory or 110 space
above a programmed base address.

READY control consists of 3 bits for each CS* line or
group of lines. This allows independent ready generation
for each of upper memory, lower memory, mid-range
memory, peripheral devices 0-3 and peripheral devices
4-6. The ready bits control an integrated WAIT State Generator that allows a programmable number of WAIT states
to be automatically inserted whenever an access is made
to the area of memory associated with a chip select area.
Each set of ready bits includes a bit which determines
whether the internal ready signals (ARDY or SRDY) are
used or ignored (i.e., the bus cycle terminates even
though a ready has not been returned on the external
pins).

Two registers in the internal peripheral control block (see
Figure 2-68) control the peripheral chip selects. These
registers allow the base address of the peripherals to be
set, and allow the peripherals to be mapped into memory
or 110 space. Both registers must be accessed before any
of the peripheral chip selects become active.
A bit in the memory/peripheral chip select (MPCS) register allows PCS5* and PCS6* to become latched when outputs Al and A2 occur. When this option is selected,
PCS5* and PCS6* indicate the state of Al and A2
throughout the bus cycle. These outputs provide for external peripheral register selection in a system where the address is not latched. On reset, these lines are driven high
and only indicate the state of Al and A2 after both PACS
and MPCS have been accessed (and are programmed to
provide Al and A2-refer to Volume I of this User's
Guide).

When the externally generated READY is used (R2 = 0),
the internal ready generator operates in parallel with the
external READY. For example, if the internal ready generator is set to insert two Wait states, but activity on the
external READY lines inserts four WAIT states, only four
WAIT states will be inserted by the processor. This is because the two WAIT states generated by the internal

Table 2·29 80186 WAIT State Programming

READY/WAIT STATE GENERATION
The 801861188 generates an internal READY signlll for
each of the memory or peripheral chip select (CS*) iines.
From 0 to 3 WAIT states may be inserted by the internal
ready generation unit for each access to any memory or
110 areas to which the chip select circuits respond. Table
2-29 shows how the ready control bits should be programmed to provide this. In addition, the READY genera-

2-78

R2

R1

RO

0
0
0
0
I
I
I
I

0
0

0
I
0
I
0
I
0
I

I

I
0
0
I
1

Number of Wait States

o + external ready
I
2
3

+ external ready
+ external ready
+ external ready

o (no external ready required)
I (no external ready required)
2 (no external ready required)
3 (no external ready required)

210912·001

80186/80188 CPU

CLKIN

CLKOUT

~--------------TCLCL------------~~

Figure 2·73 Clock In/Clock Out Timing

generator overlapped the first two WAIT states generated
by the external READY signal. The external ARDY and
SRDY lines are always ignored during cycles accessing
internal peripherals.

clock signal for use outside the iAPX 186 and may be
used to drive other system components. All timings are
referenced to the output clock.

CRYSTAL CLOCK REFERENCE

2.8.5 Clock Generator/Reset/Ready

The 80186 oscillator circuit is designed to be used with a
parallel resonant fundamental mode crystal (see Figure
2-75) as the time base. The crystal frequency selected
should be double the intended CPU clock frequency. Do
not use an LC or RC circuit with this oscillator. If an
external oscillator is used, connect it directly to input pin
Xl in lieu of a crystal (input pin X2 may be left to float).
The output of the oscillator is not directly available outside the 80186.

The 80186 clock generator produces the main clock signal (see Figure 2-73) for all 80186 integrated components, and all CPU synchronous devices in. the 80186
system (see Figure 2-74). This clock generator includes a
crystal oscillator, a divide-by-two counter, reset circuits,
and ready generation logic.
The clock generator generates the 50% duty cycle processor clock for the iAPX 186 by dividing the output of a
crystal oscillator by two to form the symmetrical clock
signal. If an external oscillator is used, the state of the
clock generator will change on the falling edge of the oscillator signal. The CLKOUT pin provides the processor

The crystal oscillator is a parallel resonant, Pierce oscillator designed to be used as shown in Figure 2-76 (the capacitor values shown are approximate). As the crystal

X,

CPU CLOCK &

x,

CLOCKOUT

ARDY

--------+~r-;;;,=-,

SRDY

-----------------+----f

~----------------~~~

CPU
READY

CPU RESET

&
RESET OUTPUT

Figure 2·74 80186 Clock Generator Block Diagram
2-79

210912-001

8086/80186 HARDWARE REFERENCE MANUAL

signal if it will occur during T2, T3, or Tw).
High-to-LOW transitions of ARDY must be performed
synchronously to the CPU clock.

x,I---------,

~ 11 MtU CRYSTAL

A second ready input (SRDY) is provided to interface
with externally synchronized ready signals. This input is
sampled at the end ofT2, T3, and again at the end of each
Tw until it is sampled HIGH. By using this input rather
than the asynchronous ready input, the half-clock cycle
resolution time penalty is eliminated. This input must satisfy set-up and hold times to guarantee proper operation
of the circuit.

X,I----------'
80186

Figure 2·75 Recommended iAPX 186
Crystal Configuration

Ready synchronization is discussed in more detail in paragraph 2.5.7. Refer to that discussion and the timing diagram contained in paragraph 2.5.7 for additional detail.

frequency drops, the de-coupling capacitor values should
be increased, (e.g., at the 4 MHz minimum crystal frequency supported by the 80186 these capacitors should be
30pF).

RESET

The 80186 provides both a RES* input pin and a synchronized RESET output pin for use with other system components. The RES* input pin is provided with hysteresis
to allow a power-on reset signal generated from an RC
network. RES* is required to be low for greater than four
clock cycles and must occur no sooner than 50 microseconds after power-up. RESET is guaranteed to remain active for at least five clocks, given a RES* input lasting at
least six clocks. RESET may be delayed from RES* up to
2.5 clocks.

EXTERNAL FREQUENCY CLOCK REFERENCE

The 80186 can use an external clock frequency standard
(similar to the 8086 when used in conjunction with the
8284A). The external frequency input (EFI) signal connects directly to the Xl input of the oscillator (X2 is left
open). This oscillator input drives an internal divide-bytwo counter to generate the CPU clock. The external frequency reference can thus be virtually any duty cycle, as
long as the minimum high and low times for the signal are
consistent with those specified for the 80186 (refer to the
Intel iAPX186 data sheet).

The reset input signal also resets the divide-by-two
counter. A one clock cycle internal clear pulse is generated when the RES* input signal first goes active. This
clear pulse goes active beginning on the first low-to-high
transition of the Xl input after RES* goes active, and
goes inactive on the next low-to-high transition of the Xl
input. In order to insure that the clear pulse is generated
on the next EFI cycle, the RES* input signal must satisfy
a 25ns setup time to the high-to-low EPI input signal (see
Figure 2-77). During this clear, clockout will be high. On
the next high-to-low transition of Xl, clockout will go
low, and will change state on every subsequent
high-to-low transition of EFI.

READY SYNCHRONIZATION

The 80186 provides both synchronous and asynchronous
ready inputs. Asynchronous ready synchronization is accomplished by circuits which samples ARDY in the middle of T2, T3, and again in the middle of each Tw until
ARDY is sampled HIGH. One-half CLKOUT cycle of
resolution time is used and full synchronization is performed only on the rising edge of ARDY (i.e., the falling
edge of ARDY must be synchronized to the CLKOUT

80186

x,

x,

Crystal Choice Recommendations:

ck

T
±2~F

±~F

Frequency & Tolerance:
Temperature Range:
ESR (Equivalent Series
Resistance):
Co (Shunt Capacitance):
C L (Load Capacitance):
Drive Level:

Determined by System
Requirements
o to 70°C
30 ohms max
7 pfmax
20 pf :!:2pf
1 mwmax

Figure 2·76 8018.6. Crystal Connection

2-80

210912-001

80186/80188 CPU

Figure 2-77 80186 Clock Generator Reset
Table 2-30 80186 Initial Register State After
RESET

The high-to-Iow transition of the clockout signal of the
80186 synchronizes the reset signal presented to the rest
of the 80186, and also the signal present on the RESET
output pin of the 80186. This signal remains active as
long as the RES* input also remains active. After the
RES* input goes inactive, the 80186 will begin to fetch its
first instruction (at memory location FFFFOH) after six
and a half CPU clock cycles (i.e., Tl of the first fetch will
occur six and a half clock cycles later). To insure that the
RESET output will go inactive on the next CPU clock
cycle, the inactive going edge of the RES* input must
satisfy certain hold and setup times to the low-to-high
edge of the clockout signal of the 80186 (see Figure
2-78).

Status Word
Instruction Pointer
Code Segment
Data Segment
Extra Segment
Stack Segment
Relocation Register
UMCS

•

Initialization and Processor Reset

Upon receipt of a RESET pulse from the RES* input, the
local bus controller will perform the following actions:
Drive DEN*, RD"', and WR* HIGH for one clock
cycle, then float.

RD* is also provided with an internal pull-up
device to prevent the processor from inadvertently entering Queue Status mode during reset.

Drive LOCK'" HIGH and then float.

Drive HLDA LOW.

•

All chip-select outputs will be driven high.

•

Upon leaving RESET, the UCS* line will be programmed to provide chip select to a lk block with the
accompanying READY control bits set at 011 to allow
the maximum number of internal wait states in conjunction with external Ready consideration (i.e.,
UMCS resets to FFFBH).

•

No other chip select or READY control registers have
any predefmed values after RESET. They will not become active until the CPU accesses their control registers. Both the PACS and MPCS registers must be
accessed before the PCS* lines will become active.

~'~

NOTE

•

Tristate ADO-I5, AI6-19, BHE*, DT/T*.

Upon reset, the Chip-Select/Ready logic will perform the
following actions:

Local Bus Controller and Reset

Drive SO*-S2* to the passive state (all HIGH) and
then float.

20FF(H)
FFFB(H)

Chip Select/Ready Logie and Reset

Processor initialization or startup is accomplished by
driving the RES* input pin LOW. RES* forces the 80186
to terminate all execution and local bus activity. No instruction or bus activity will occur as long as RES* is
active. After RES* becomes inactive and an internal processing interval elapses, the 80186 begins execution with
the instruction at physical location FFFFOH. RES* also
sets some registers to predefined values (see Table 2-30).

•

FFFF(H)

OOOO(H)
OOOO(H)
OOOO(H)

• Drive ALE LOW (ALE is never floated).
•

•

F002(H)

OOOO(H)

RES _ _ _ _
...J
RESET

---------"""'L-

Figure 2-78 Coming Out of Reset
2-81

210912·001

80186/80188 CPU

DMA Channels and Reset

Interrupt Controller and Reset

Upon RESET, the DMA channels will perform the following actions:

Upon RESET, the interrupt controller will perform the
following actions:

•

The Start/Stop bit for each channel will be reset to
STOP.

•

All SFNM bits reset to 0, implying Fully Nested
Mode.

•

Any transfer in progress is aborted.

•

All PR bits in the various control registers set to 1.
This places all sources at lowest priority (leve1111).

Timers and Reset
Upon RESET, the Timers will perform the following
actions:
•
•

All EN (Enable) bits are reset preventing timer
counting.
11 SEL (Select) bits are reset to zero. This selects
MAX COUNT register A, resulting in the Timer Out
pins going HIGH upon RESET.

•

All LTM bits reset to 0, resulting in edge-sense mode.

•

All Interrupt Service bits reset to O.

•

All Interrupt Request bits reset to O.

•

All MSK (Interrupt Mask) bits are set to 1 (mask).

•

All C (Cascade) bits reset to 0 (non-cascade).

•

All PRM (Priority Mask) bits set to 1, implying no
levels masked.

• Initialized to non-iRMX 86 mode.

2-82

210912-001

8087 Numeric
Processor Extension

3

CHAPTER 3
8087 NUMERIC PROCESSOR EXTENSION
3.1 INTRODUCTION

software based 8087 emulator is also included. Both the
component and the software emulator add extra data types
and operations to the iAPX 86/10 family ofmicroprocessors. The hardware component and the software emulator
are completely compatible.

This chapter provides specific hardware design information on the operation and functions of INTEL's 8087 Numeric Processor Extension (NPX). General information
on the NPX coprocessor and its applications is presented,
along with a component overview of the architectural and
software considerations, and individual device pin functional signal definitions. Detailed descriptions of the NPX
operating modes, general operation with the iAPX 86/186
host CPU's, and bus operation artd timing are also presented. In addition, an explanation of the protocols supporting local bus transfers to the host CPU's, and a
description of interrupt operation are also provided. For
more specific information of any of the 8086 family support circuits, refer to the Microsystem Component Handbook (Order Number: 230843-002).

NUMERIC PROCESSOR EXTENSION
APPLICATIONS

The versatility and performance of the 8087 NPX make it
appropriate for a broad array of numerically-oriented applications. Generally, any application that exhibits the following characteristics will benefit by implementing
numeric processing on the 8087:
1. Numeric data vary over a wide range of values or include non- integral values; non-integral values;
2. Algorithms produce very large or very small intermediate results;

3.1.1 iAPX 86, 88, 186, 188 Base

3. Computations must be very precise, i.e., a large number of significant digits must be maintained;

The 8087 Numeric Processor Extension (NPX) is based
on the iAPX861 88/186/188 family of microprocessors.
These microprocessors are general purpose devices, designed for general data processing applications that require fast, efficient data movement and control
instructions. The actual arithmetic performed on data values is fairly simple in data applications. The iAPX 86
family of microprocessors fills this need in an effective,
low cost manner. However, some applications require
more powerful arithmetic instructions and data types than
provided by a general purpose data processor. Since the
real world deals in fractional values and requires
arithmetic operations like square root, sine and logarithms, integer data types and their operations may not
meet the needed accuracy, speed, and ease of use requirements.

4. Performance requirements exceed the capacity oftraditional microprocessors;
5. Consistently safe, reliable results must be delivered
using a programming staff that is not expert in numeric techniques.
The 8087 can also reduce software development costs and
improve the performance of systems that do not use real
numbers, but operate on multi-precision binary or decimal integer values.
A few examples, which show how the 8087 might be used
in specific numerics applications, are described in the following list. In the past, these types of systems have typically been implemented with minicomputers. The advent
of the 8087 brings the size and cost savings of microprocessor technology to these applications for the first time.

These advanced functions are not simple to implement
and are not inexpensive. General data processors do not
provide these features because of their cost to other
less-complex applications that do not require such sophisticated features. Therefore a special, easy to use processor which has a high level of hardware and software
support is required to implement these functions.

1. Business data processing - The NPX's ability to accept decimal operands and produce exact decimal
results up to 18 digits greatly simplifies accounting
programming. Financial calculations which use power
functions can take advantage of the 8087's exponentiation and logarithmic instructions.

The 8087 (NPX) provides these features and supports the
data types and operations needed. The NPX allows use of
all of the current hardware and software support that is
available for the iAPX 86/10, iAPX 88/10, iAPX 186/10
and iAPX 188/10 microprocessors. The following paragraphs present some typical applications for microprocessors using the NPX. In addition, a discussion of the use of
the special hardware component, the 8087 NPX, and its

2. Process control - the 8087 solves dynamic range
problems auto maticaJly, and its extended precision
allows control functions to be fine-tuned for more accurate and efficient performance. Control algorithms
implemented with the NPX also contribute to improved reliability and safety, while the 8087's speed
can be exploited in real-time operations.
3-1

210912-001

8087 NUMERIC PROCESSOR EXTENSION

3. Numeric control - The 8087 can move and position
machine tool heads with extreme accuracy. Axis positioning also benefits from the hardware trigonometric
support provided by the 8087.

BOB7 BASED LINK/LOCATE COMMANDS
LlNKB6 :F1:PROG.OBJ, IO.LlB, BOB7.LlB TO
:F1:PROG.LNK
LOCB6 :F1:PROG.LNK TO :F1:PROG

4. Robotics - Coupling small size and modest power
requirements with powerful computational abilities,
the NPX is ideal for on-board six-axis positioning.

SOFTWARE EMULATOR BASED
LINK/LOCATE COMMANDS

5. Navigation - Very small, light weight, and accurate
inertial guidance systems can be implemented with the
8087. Its built-in trigonometric functions can speed
and simplify the calculation of position from bearing
data.

LlNKB6 :F1 :PROG.OBJ, IO.LlB, EB087.LlB,
EB087 TO :F1:PROG.LNK
LOCB6 :F1:PROG.LNK TO :F1:PROG

6. Graphics terminals - The 8087 can be used in graphics terminals to locally perform many functions which
normally demand the attention of a main computer;
these include rotation, scaling, and interpolation. By
also including an 8089 Input/Output Processor to perform high speed data transfers, very powerful and
highly self-sufficient terminals can be built from a relatively small number of 8086/88 family components.

Figure 3-1 Submit file Example
When the emulator is used, the linker changes all the
2-byte wait-escape, nop-escape, wait-segment override,
or nop-segment override sequences generated by an assembler or compiler for the 8087 component with a
2-byte interrupt instruction. Any remaining bytes of the
numeric instruction are left unchanged.

7. Data acquistion - The 8087 can be used to scan, scale
and reduce large quantities of data as it is collected.
This lowers the storage requirements as well as the
time required to process the data for analysis.

The host executes software interrupt instructions formed
by the linker when it encounters numeric and emulated
instructions. The interrupt vector table directs the host to
the proper entry point in the 8087 emulator. The host then
decodes any remaining part of the numeric instruction using the interrupt return address and CPU register set, performs the indicated operation, and returns to the next
instruction following the emulated numeric instruction.
One copy of the 8087 emulator can be shared by all programs in the host.

These examples are all oriented toward the "traditional"
numerics applications. There are, however, many other
types of systems that do not appear to the end user as
"computational" , but can employ the 8087 to advantage.
The 8087 presents the imaginative system designer with
an opportunity similar to that created by the introduction
of the microprocessor itself. Many applications can be
viewed as numerically-based if sufficient computational
power is available to support this view. This is analogous
to the thousands of successful products that have been
built around "buried" microprocessors, even though the
products themselves bear little resemblance to computers.

The decision to use the 8087 or the software emulator is
made at link time, when all software modules are brought
together. Depending on whether an 8087 or its software
emulator is used, a different group of library modules are
included for linking with the program.

If the 8087 component is used, the libraries do not add
any code to the program, they just satisfy external references made by the assembler or compiler. Using the emulator will not increase the size of individual modules,
however, other modules requiring about 16K bytes that
implement the emulator will be automatically added.

8087 EMULATOR VERSUS COMPONENT USE
Two basic implementations of the Numeric Data Processor Extension (NPX) are available. One is using the 8087
component and the other is with its software emulator
(E8087). Whether the emulator or the component is used
has no effect on programs at the source level. All instructions, data types and features are used in the same way at
the source level.

Selecting between the emulator or the 8087 can be very
easy. Different versions of submit files performing the
link operation can be used to specify the different set of
library modules needed. See Figure 3-1 for an example of
the two different submit files for the same program using
the NPX with an 8087 or the 8087 emulator.

All numeric instruction opcodes must be replaced with an
interrupt instruction when the emulator is used. This replacement is performed by the LlNK86 program. Interrupt vectors in the hosts interrupt vector table will point to
numeric instruction emulation routines in the 8087 software emulator.

3.1.2 8087 Mobility In Any iAPX 86, 88,
186 Design
The design of any maximum mode iAPX 86/1X, 88/1X,
18611X or 188/1X system can be easily upgraded with an
3-2

210912-001

8087 NUMERIC PROCESSOR EXTENSION

can test for the existence of the 8087 by initializing it and
then storing the control word. A program segment that
illustrates this technique is shown in Figure 3-5.

GND~~
(A14) AD14

2

(A13) "013~'
(A12)AD12

·,
·,
·· ...

(A11).011I.

(.'0)AD10
(A9) ADS

(AI) ADa
AD7
AOO

I

ADS
AD4 :
AOO _
A02 -

AD1 ~
ADO

I

NC,
NC

39

J

'"
"

"
"
"\5
"
"

..

eLK C

19

GND [

20

80e7

Vee

.,8$3
.,71$4

"
"
"

When no CPU board space has been left for the 8087
component (or memory space for its software emulator),
a maximum mode iAPX 86/1X system can be upgraded to
a numeric processor using the iSBC 337 MULTIMODULE. The iSBC 337 MULTIMODULE is designed for
just such a function. The iSBC 337 provides a socket for
the host microprocessor and an 8087. A 40-pin plug is
provided on the underside of the 337 to plug into the original host's socket (see Figure 3-6). Two other pins on the
underside of the MULTIMODULE allow easy connection
to the 8087 INT and RQ/GTl pins.

~ A015

3.

Al11S5

: A191S6

" HIS7
;;am'
" 'NT
RQ,(fto
,." NC
"

"
"
"
"u

NC

ii2
.51
,iiii
: QSO

J OS1

2JP BUSY

lip
21

J

READY
RESET

3.2 COMPONENT OVERVIEW
The 8087 Numeric Data Processor Extension (NPX) provides arithmetic and logical instruction support for a variety of numeric data types in iAPX 86/20, 88/20 systems.
The 8087 executes instructions as a coprocessor to a maximum mode 8086 or 8088 and effectively extends the register and instruction set of (including the addition of
several new data types) an iAPX 86/10 or 88/10 based
system. The 8087 is an extension to the iAPX 86/10 or
88/10 that provides enhanced register, data types, control,
and instruction capabilities at the harJwa,~ level.

Figure 3·2 8087 Numeric Data Processor
Pin Diagram
8087. Such a system would then be designated an 86/2X,
88/2X, 186/2X or 188/2X. See Figure 3-2 for 8087 DIP
pin assignments, Figure 3-3 for local bus interconnections
of a typical iAPX 86/20 (or iAPX 88120) system, and
Figure 3-4 for local bus interconnects of a typical iAPX
186/2X (or iAPX 188/2X) system. The 8087 shares the
maximum mode host's multiplexed address/data bus, status signals, queue status signals, ready status signals,
clock and reset signal. Two dedicated signals, BUSY and
INT, are used to inform the host of the 8087's status. To
ensure that the host will always see a "not busy" status if
an 8087 is not installed, a 10K pull-down resistor should
be installed on the BUSY signal line.

The 8087 extends the capability of an iAPX186/188 system when interfaced to an 80186 or 80188 through the
Intel 82188 Integrated Bus Controller. When interfaced to
the 80186/88, the combination of components form an
iAPXI86(188)/20 system.

3.2.1 Architecture Overview

Adding the 8087 to an iAPX 86/88/186/188 design has a
minor effect on the system timing. Installing the 8087
adds 15 pF to the total capacitive loading on the shared
address/data and status signals. The 8087 can drive a total
capacitive load of 100 pF above its own self load and sink
2.0 rnA of DC current on its pins. This AC and DC drive
is sufficient for an iAPX 86/21 system consisting of two
sets of data transceivers, address latches, and bus controllers for two separate busses, an on-board bus and an
off-board MULTIBUS using the 8289 bus arbiter. Refer
to paragraphs 3.8 and 3.7 in this chapter for additional
information on connecting the 8087 INT and RQ/GT
pins.

The 8087 is internally comprised of two processing elements (see Figure 3-7), the Control Unit and the Numeric
Execution Unit. The numeric execution unit executes all
numeric instructions, while the control unit receives and
decodes instructions, reads and writes memory operands
and executes NPX control instructions. These two elements operate independently of one another; this allows
the control unit to maintain synchronization with the CPU
while the numeric execution unit is busy processing numeric instructions.

CONTROL UNIT

A prewired 40-pin socket for the 8087 component can be
left on a CPU board. Then, adding the 8087 to such a
system would be as easy as plugging in the device. In this
case, if a program attempts to execute any numeric instructions when the 8087 is not installed, the instruction
will be treated as a NOP instruction by the host. Software

The control unit keeps the 8087 synchronized with its host
CPU. 8087 instructions intermix with host CPU instructions in a single instruction stream (the CPU fetches all
instructions from memory). By monitoring the status signals (SO*-S2 *, S6) of the CPU, the NPX control unit de-

3-3

210912-001

8087 NUMERIC PROCESSOR EXTENSION

... i::
~

Nol.2m.

~"
"

14

~

DO'
DO'
DO<

:::~

..

DO. ~

DOt

:::~
0"
STI

"

·

H

~

~
!.........!!

'j
, "
~
~

000
DO'
00'
•
16 003
00.
00 •
006
A~ 00'
OE

;H
~~

I

010

-:

--{II"

""

,,

CLK

2 A014

ROIOTI

3 A013
4 A012

"

RQlf3Tl

3

'NT

"

'NT

STB

5 A011

.5V

ill
!!l

8 A010

7 A09
8 ADB
9 AD7

"~

10 AD6
11 ADS

"
~
~

,

1

AD'
AD>
s;
AD'
'-AD'
~
~
16 AOO
OS, QSO : : BUSY:

~

.

.... ·•
ili

H±-

r!!- I - -

"Fi'"

RESET

DIS 6
016 1
017 8

0"
0"
0"
0"

"

11

38 AIIIS3
39 A015

0"
0"

010

M"

Vee

37 A17I54

..la ·
·
0"
012

READY

3

f'!-

"

r-

"

31

~1OK

015 6
016 7

017 8

...

m

"L-AO

,

,
~
~ "" ~~
~ " . " ,,
Ul ""
"
BO
B1

It

XI l'

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ON

38 A'BiSS

000
00'
00'
003
00.
DO.
00.
00'
OE

I

.

,

.IYHC

IIIEADY RESET elK OND m
10
•
11

J ,r;[*
"

35 A191S8 Vee

~
~

.JI"" .,.

ROVI AENI Ron AI .. 2

DI~~

~ DO'
O'

,]

.1~.lII.l9 11

:~

A1

. ... ··
A2 3
'3
AI

",

13

A6

T

OE

'I

"

·

35

36

" " " "
aSl OSO RafGT,

::::~

RESET 21
elK 19
",,"
IfO/(ffIj 31
rn~1{ 29

3 AOI4(AI4)

~~~~~~~

4
5 AD11(Al1)
6

H

~
~

....

AO

,

A1

,

.. 3
A3 •

"
~ " ;
~
'" " ,
~
eL.!! "
"
"
11LOE

A• •
AS ,

T

.

~

READY

33 AI6JS3

3: AOI5(AI5)

BO
B1

~

~SSi$) Bfiii/S7 ~

31 A17/S4

AD1~Al0)

; :::::

OJ>
tlOitmi
umK

-

_.
CD CD

;:

c-

NMI 11
INTR 18

9 AOT

:~ :~
12
13
14
15
16

AD4
AD3
AD2
AD1
ADO

S2 28
Sl 2i"
SO 26
Vee OND GNDMNIMY

1'~

'I

+5V

~

NM'
INTR

,~

, ,

1

ClK AEN

lOB OND

..

18 S2

351

..

10-:

MeE

Vee CEN

~
CD

19 SO

=
-

2~h,J
. .,

.

iOWC

-ATOWC

, ,

ALE DTIR DEN MRDC MWfC AMWC

....

'"

16

~I ~I

il
~

~
~

iNTA

"
~I

Figure 3·3 Typical iAPX 86/2X Family System Diagram

3·4

210912-001

TO OPTIONAL
THIRD BUS MASTER

~'11D""DATA.J. t

..,..
12MHz
"'1'1

cS'
e::

ARDY QSO
RD
QS1

iil

ftI
~
~
0'
!!!.

"

i=
'V

)(

~

....
CO

.fJfD Htt\
HLDA
HOLD
CSIN

HLDA
HOLD
MCSO

,.

----+

SRDY
RESETOUT
CLOCKOUT
S2
INTO
S1
TEST

ii3

-<

en

'<

~

3

c

g..
DI

3

-

......

~

-

------

STB

~

--

74LS
373

Il"

Z

c:

s::
m

:xl

~

(;

'tJ
:xl

ADDRESS

o
o

V

m

I

en
en
o

r

:xl

DT/R I - - DEN I - - -

RQ/GTO
RO/crr1

RQ/GTO
RO/crr1

C

I------t
~

DIR
OE

~

QSOO
QS10

l'

74LS
245

8

~

m

vi

i'f

z
en

oz

DATA

I

ADDRESS DATA BUSt

ARDY

'"
~

CII

82188

RDY
QSO
QS1

8087

CII

QS11

S2
S1
SO
CLK
RESET
~ SRO

)(

SO
S1
S2
CLK
RESET

QSOI

ALE

-

SO -

' - BUSY
'----- INT

COMMAND/CONTROL

'r

Q

en

it'
2,

;L-

SRDY
231051-7

8087 NUMERIC PROCESSOR EXTENSION

Test for the existence of an 8087 in the system. This code will always recognize an 8087
independent of the TEST pin usage on the host. No deadlock is possible. Using the 8087
emulator will not change the function of this code since ESC instructions are used. The word
variable control is used for communication between the 8087 and the host. Note: if an 8087 is
present, it will be initialized. Register ax is not transparent across this code.
ESC
XOR
MOV
ESC
OR
JZ

28, bx
ax, ax
control, ax
15, control
ax, control
no_8087

FNINIT if 8087 is present. The contents of bx is irrelevant
These two instructions insert delay while the 8087 initializes itself
Clear intial control word value
FNSTCW if 8087 is present
Control = 03ffh if 8087 present
Jump if no 8087 is present

Figure 3-5 Test for the Existence of an 8087
iSBC

I

BOARD
(iSec 86/12ATM)

337'~ MULTIMODULET~

termines when an 8086 instruction is being fetched. At
the same time, the control unit monitors the Data bus in
parallel with the host CPU to obtain instructions that pertain to the 8087.

BOARn

The CPU maintains an instruction queue that is identical
to the queue in the host CPU. By monitoring the BHE*IS7
line, the control unit automatically determines if the CPU
is an 8086 or an 8088 iinmediately after reset and matches
its queue length accordingly. Also, by monitoring the

OPTIONAL SOLDER
MOUNT

FiQure 3-6 iSBC® 337 MULTIMODULE
Mounting Scheme

DATA"--tI

T

A

(5)

G

W

(3)

0
R

STATUS

ADDRESS

(4)

REGISTER STACK

(2)

0

(1)

I

L

(0)

-

-

-

-

'-

80 BITS

-

~

-

-

-

-

-

~

Figure 3-7 8087 Numeric Processor Extension Block Diagram

3"6

210912-001

8087 NUMERIC PROCESSOR EXTENSION

MOD

CPU's queue status lines (QSO, QS1), the control unit obtains and decodes instructions from the queue synchronously with the CPU.

11 I 1 I
115

114

0

I 1I 1 I

113 112

111

I
ItO

I
19

11 I 1 I
18

17

16

I
IS

I I
14

13

I
12

I
11

1
10

Figure 3-8 Non-Memory Reference Escape
Instruction Form

A numeric instruction for the 8087 appears as an ESCAPE instruction to the 8086 or 8088 CPU; both the
CPU and the NPX decode and execute the ESCAPE instruction together. Only the 8087, however, recognizes
the numeric instructions. The start of a numeric operation
begins when the CPU executes the ESCAPE instruction
(the instruction mayor may not identify a memory operand).

When the numeric execution unit begins executing an instruction, it activates the 8087 BUSY signal. This signal
can be used in conjunction with the CPU WAIT instruction to resynchronize both processors when the numeric
execution unit has completed its current instruction.

The CPU does, however, distinguish between ESCAPE
instructions that refer to memory operands and those that
do not. If the instruction refers to a memory operand, the
CPU calculates the operand's address using anyone of its
available addressing modes, and then performs a "dummy
read" of the word at that location. (Any location with the
1M byte address space is allowed.) This read cycle is normal except that the CPU ignores the data it receives. If the
ESCAPE instruction does not contain a memory reference (e.g., an 8087 stack operation), the CPU simply proceeds to the next instruction.

3.2.2 Software Overview
The following paragraphs discuss the ESCAPE instruction format and discuss the use of the ESCAPE instruction with custom coprocessors. The constraints which the
designer must exercise when designing this type of circuit
are also discussed.

ESCAPE INSTRUCTION FORMAT

An 8087 instruction can have one of three memory reference options:

There are two basic forms of the ESCAPE instructions.
These are the non-memory form (see Figure 3-8) and the
memory reference form (see Figure 3-9). All ESCAPE
instructions start with the high order 5-bits of the instruction being 11011. The non-memory form ofthe ESCAPE
instruction initiates some activity in the coprocessor using
the nine available bits of the ESCAPE instruction to indicate which action to perform.

1. not reference memory;
2. load an operand word from memory into the 8087;
3. store an operand word from the 8087 into memory.
If the 8087 requires no memory reference, the numeric
execution unit simply executes its instruction. If the 8087
does require a memory reference, the control unit uses
the "dummy read" cycle initiated by the host CPU to capture and save the address that the CPU places on the bus.
If the instruction specifies a register load, the control unit
also captures the data word when it becomes available on
the local data bus. If the 8087 requires data longer than
one word, the control unit immediately obtains the bus
from the CPU using the request/grant protocol and reads
in the rest of the information in consecutive bus cycles. In
a store operation, the control unit captures and saves the
store address as in a register load operation, and ignores
the data word that follows in the "dummy read" cycle.
When the 8087 is ready to perform the store, the control
unit obtains the bus from the CPU and writes the operand
starting at the specified address.

The memory reference forms of the ESCAPE instruction
allow the host to point out a memory operand to the
coprocessor using any host memory addressing mode. Six
bits are available in this form to identify what to do with
the memory operand. Note that the coprocessor may not
recognize all possible ESCAPE instructions. In this case
the coprocessor ignores the unrecognized ESCAPE instructions.
In the memory reference forms of the ESCAPE instructions bits 7 and 6 of the byte follow the ESCAPE opcode.
These two bits are the MOD field of the 8086 or 8088
effective address calculation. Together with R/M field
bits 2 through 0, bits 7 and 6 determine the addressing
mode and how many subsequent bytes still remain in the
instruction.

NUMERIC EXECUTION UNIT

The 8087 executes all instructions that involve the numeric register stack. These instructions include
arithmetic, logical, transcendental, constant and data
transfer operations. The numeric execution unit in the
NPX has a 80-bit wide data path (64 fraction bits, 15 exponent bits and a sign bit) that allows internal operand
transfers to be performed at very high speeds.

The 8086 or 8088 ESCAPE instructions provide 64 memory reference opcodes and 512 non-memory reference
opcodes. The 8087 only uses 57 of the memory reference
opcodes and 406 of the non-memory reference opcodes.
Refer to Figure 3-10 for a list of the ESCAPE instructions
not used by the 8087.
3-7

210912·001

8087 NUMERIC PROCESSOR EXTENSION

MOD

11 I 1 I ° I 1 I 1 I
'15 114

113 1,2 '11

I I
'10

19

RIM

1° I ° 1 I
Ie

'7

'6

15

I 11 I 1 I °
'4

13

12

MOD
IH

'10

19

Ie

'7

'6

15

14

13

'2

MOD

11111011111
~

~ ~

~ ~

~

~

~

~

~

'15 '14

113 '12

'11

~

19

Ie

17

10

~

16·blt direct displacement
I I I
I I I I I

~

16

15

I I I
14

'3

12

I

07

06

0S

04

03

I I 1
02

I I I

De

07

06

Os

04

03

0,

DO

I I I
02

0,

Do

a·blt displacement
I I I I I I ~
~

~

~

~

~

~

~

~

I

I
1,

De

16·blt displacement
I I III I I I I

0,5 014 013 0'2 0'1 ~10 09

I I
~

RIM

I 11°1 0 1 I
'10

I II
'1

III
~

MOD

111110111'1

I

0,5 0'4 013 0'2 0'1 0'0 09

RIM

I I 10lljl
~

10

I I I

RIM

I 11 1 10 1 I I I I

11111011111
'15 1,4 113 1,2

1,

I

10

Figure 3·9 Memory Reference Escape Instruction Form
USING THE 8087 WITH CUSTOM
COPROCESSORS

1 I 1 I ° I 1 1 1 I 1 1 11 I 1 I 1 1 L ... 1.-1__
115

'14

113

19
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1

110
0
0
0
0
0
0
0
0
0
0
0
0
0

'10

19

18

18 IS 14
1 0 1
1 0 1
1 0 1
1 1 0
1 1 0
1 1 0
1 1 1
1 1 1
1 1 1
1 1 0
1 1 0
1 1 0
1 1 1
1 1
1 1 0
1 1 0
1 1 0
1 1 0
1 1 1

'12

1,1

13
0
0
0
0
0
1
0
1
1
0
0
1

12
0
0
1
0
1
1
1
0
1
1
1

17

'6

IS

11 10
0 1
1

14

13

12

'1

to

When designing numeric processors with custom coprocessors, the designer should limit the use of ESCAPE instructions to only those not used by the 8087. Using only
the unused ESCAPE instructions with custom coprocessors is necessary to prevent ambiguity as to whether any
specific ESCAPE instruction is intended for the numeric
or custom coprocessor. Note that using any escape instruction for a custom coprocessor may conflict with opcodes chosen for future Intel coprocessors.

Available codes

-

1
1
1
0
1
1
0
1

Using the 8087 together with other custom coprocessors
under the following constraints:

----

16

----0 0 0 1

1. All 8087 errors are masked. The 8087 will update its
opcode and instruction address registers for the unused opcodes. Unused memory references
instructions will also update the operand address
value. These changes make software-defined error
handling in the 8087 impossible.

32

0 0 1 0
0 1
1

--

----

16
105 total

2. If the coprocessors provide a BUSY signal, they must
be ORed together for connection to the host TEST
pin. When the host executes a WAIT instruction, it
does not know which coproces sor will be effected by
the following ESCAPE instruction. Typically, all coprocessors must be idle before executing the ESCAPE
instruction.

Available Non-Memory Reference Escape Instructions

MOD

11 1 1°1 1 11 1 I I I I
'15 1,4 113 112 "1

110
0
0
0
0
1
1
1

'10

'9

'8

'7

RIM

I I I LLL
16

15

'4

13

'2

'1

10

19 18 IS 14 13
0
0 0 1
1
0 0 1
1
1 0 0
1
1 1 0
0 0 1
0
1 0 1
0
0 0 1
1

3.3 DEVICE PIN ASSIGNMENTS
A complete functional description of each device pin signal is provided Thble 3-1. This table correlates the description to the pin number and associated signal symbol.

Available Memory Reference Escape Instructions

Figure 3·10 ESCAPE Instructions Not Used
By the 8087 NPX

3.4 OPERATING MODES
The following paragraphs describe the operation of the
8087 NPX in conjunction with the 8086(88) and

3·8

210912-001

8087 NUMERIC PROCESSOR EXTENSION

Table 3·1 8087 Device Pin Descriptions
Type

Name and Function

AD15-ADO

IlO

Address Data:These lines constitute the time multiplexed memory address (Tl) and data (T 2,
T3, Tw, T4) bus. AO is analogous to SHE for the lower byte of the data bus, pins 07-00. It is
LOW during T, when a byte is to be transferred on the lower portion of the bus in memory
operations. Eight-bit oriented devices tied to the lower half of the bus would normally use AO
to condition chip select functions. These lines are active HIGH. They are input/output lines for
8087 driven bus cycles and are inputs which the 8087 monitors when the 8086/8088 is in
control of the bus. A15-A8. do not require an address latch in an iAPX 88/20. The 8087 will
supply an address for the T,-T4 period.

A19/56,
A18/55,
A17/54,
A16/53

I/O

Address Memory: During T, these are the four most significant address lines
for memory operations. During memory operations, status information is available on
these lines during T2, T3, Tw, and T4. For 8087 controlled bus cycles, 56, 54, and 53
are reserved and currently one (HIGH), while 55 is always LOW These lines are inputs which
the 8087 monitors when the 8086/8088 is in control of the bus.

SHE/57

I/O

Bus High Enable: During T, the bus high enable signal (SHE) should be used to enable data
onto the most significant half of the data bus, pins 015-08. Eight-bit oriented devices tied to
the upper half of the bus would normally use SHE to condition chip select functions. SHE is
LOW during T, for read and write cycles when a byte is to be transferred on the high portion of
the bus. The 57 status information is available during T2, T3, Tw, and T4' The signal is active
LOW 57 is an input which the 8087 monitors during 8086/8088 controlled bus cycles.

I/O

Status: For 8087 driven bus cycles, these status lines are encoded as follows:

Symbol

52, 51,

SO

S2

S1
SO
X
X
Unused
1 (HIGH)
0
0
Unused
0
1
Read Memory
1
1
1
0
Write Memory
1
1
1
Passive
5tatus is driven active during T4, remains valid during T, and T2, and is returned to the
passive state (1,1, 1) during T3 or during Tw when READY is HIGH. This status is used by the
8288 Sus Controller to generate all memory access control signals. Any change in 52, 51, or
50 during T4 is used to indicate the beginning of a bus cycle, and the return tei the passive
state in T3 or Tw is used to indicate the end of a bus cycle. These signals are monitored by the
8087 when the 8086/8088 is in control of the bus.

o (LOW)

RQ/GTO

I/O

Request/Grant: This request/grant pin is used by the NPX to gain control of the local bus from
the CPU for operand transfers or on behalf of another bus master. It must be connected to one
of the two processor request/grant pins. The request grant sequence on this pin is as follows:
1. A pulse one clock wide is passed to the CPU to indicate a local bus request by either the
8087 or the master connected to the 8087 RQ/GT1 pin.
2. The 8087 waits for the grant pulse and when it is received will either initiate bus transfer
activity in the clock cycle following the grant or pass the grant out on the RQ/GT1 pin in this
clock if the initial request was for another bus master.
3. The 8087 will generate a release pulse to the CPU one clock cycle after the completion of
the last 8087 bus cycle or on receipt of the release pulse from the bus master on Ra/GT1.

3·9

2'0912-001

8087 NUMERIC PROCESSOR EXTENSION

Table 3·1 8087 Device Pin Descriptions (continued)
Symbol

~pe

RQ/GTl

I/O

QS1,
QSO

I

Name and Function
Request/Grant:This request/grant pin is used by another local bus master to force the 8087 to
request the local bus. If the 8087 is not in control of the bus when the request is made the
request/grant sequence is passed through the 8087 on theRQ/GTO pin one cycle later.
Subsequent grant and release pulses are also passed through the 8087 with a two and one
clock delay, respectively, for resynchronization. R<5/GT"l has has an internal pullup resistor,
and so may be left unconnected. If the 8087 has control of the bus the request/grant sequence
is as follows:
1. A pulse 1 ClK wide from another local bus master indicates a local bus request to the 8087
(pulse 1).
2. During the 8087's next T4 or Tl a pulse 1 ClK wide from the 8087 to the requesting master
(pulse 2) indicates that the 8087 has allowed the local bus to float and that it will enter the
"RQ/GT acknowledge" state at the next ClK. The 8087's control unit is disconnected
logically from the local bus during "RQ/GTacknowledge."
3. A pulse 1 ClK wide from the requesting master indicates to the 8087 (pulse 3) that the
"RQ/GT" request is about to end and that the 8087 can reclaim the local bus at the next
ClK.
Each master-master exchange of the local bus is a sequence of 3 pulses. There must be one
dead ClK cycle after each bus exchange. Pulses are active lOW
OS1, OSO: QSl and QSO provide the 8087 with status to allow tracking of the CPU
instruction queue.
OS1
OSO
o (lOW)
0 No Operation
0
1 First Byte of Op Code from Queue
1 (HIGH)
0 Empty the Queue
1
1 Subsequent Byte from Queue

INT

0

Interrupt: This line is used to indicate that an unmasked exception has occurred during
numeric instruction execution when 8087 interrupts are enabled. This signal is typically
routed to an 8259A. INT is active HIGH.

BUSY

0

Busy: This signal indicates that the 8087 NEU is executing a numeric instruction. It is connected to the CPU's TEST pin to provide synchronization. In the case of an unmasked
exception BUSY remains active until the exception is cleared. BUSY is active HIGH.

READY

I

Ready: READY is the acknowledgment from the addressed memory device that it will
complete the data transfer. The ROY signal from memory is synchronized by the 8284A Clock
Generator to form READY. This signal is active HIGH.

RESET

I

Reaet: RESET causes the processor to immediately terminate its present activity. The signal
must be active HIGH for at least four clock cycles. RESET is internally synchronized.

ClK

I

Clock: The clock provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty cycle to provide optimized internal timing.

Vee

Power: Vee is the +5V power supply pin.

GND

Ground: GND are the ground pins.

NOTE:

For the pin descriptions of the 8086 and 8088 CPU's reference those respective data sheets (iAPX 86/10, iAPX 88/10).

3-10

210912-001

8087 NUMERIC PROCESSOR EXTENSION

r -

-

..,
INT t------;~ INTR

8259A
PIC

iAPX86
BUS
INTERFACE
COMPONENTS

MUlTiMASTER
SYSTEM
BUS

8284A
CLOCK
GENERATOR

ClK

t-r-----'1~--t ClK

~"::

I
I

'------tr-----i INT

I
I

I

r'iar- ,
I
'- -

....,CLK

I

I:

~-~

~8~

... - - .....
Figure 3-11 8087 NPX - 8086/88 CPU System Configuration

80186(188) microprocessors, describe the overall electrical interface and present design considerations relate to
the interface.

bus with the 8087 on a first come first serve basis, and the
second master will be guaranteed to be higher in priority
than the 8087. All processors use the same clock generator and system bus interface components (bus controller,
latches, transceivers, and bus arbiter - see Figure 3-11).

3.4.1 8087/8086(88) Interface
When installed as a coprocessor to the 8086 or 8088, the
8087 connects in parallel with the CPU (see Figure 3-11).
The CPU's status lines (SO*-S2 *) and queue status lines
(QSO-QS1) allow the 8087 to monitor and decode instructions in synchronization with the CPU and without any
CPU overhead. The 8087 can process instructions in parallel with and independent of the host CPU. For resynchronization, the NPX's BUSY signal informs the CPU
that the 8087 is executing an instruction; the CPU WAIT
instruction tests this signal to insure that the NPX is ready
to execute subsequent instructions. The NPX can interrupt the CPU when it detects an error or exception. The
8087's interrupt request line is typically routed to the
CPU through an 8259A Programmable Interrupt Controller (see Figure 3-2) for 8087 pinout information.

3.4.2 8087/80186(88) Interface
The iAPX186/20 system operates similar to the
iAPX86/20. The 80186 contains integral controller devices (refer to Chapter 2) which result in device pin assignments and functions that differ from the 8086. To
simplify iAPX186/20 system configuration, Intel provides the 82188 Integrated Bus Controller which enables
communication between the 80186 and the 8087 without
the need for random logic (see Figure 3-12).
The 82188 converts the ARDY and SRDY signals of the
80186 to RDY for the 8087; similarly, it converts
HOLD/HLDA of the 80186 to RQ/OTO,1 for the 8087.
When configured into an iAPX186/20 system, RD* (pin
62) of the 80186 must be grounded. The 82188 supplies
the command and control signals to the devices on the
system bus that the 80186 would otherwise provide.
These signals include:

The 8087 uses one of the request/grant lines of the
iAPX86 architecture to obtain control of the local bus for
data transfers. The other request/grant line is available for
general system use (e.g., an I/O processor in LOCAL
mode). A bus master can also be connected to the 8087's
RQ*/OTl * line. In this configuration the 8087 will pass
the request/grant handshake signals between the CPU and
the attached master when the 8087 is in control. Therefore, two additional masters can be configured in an iAPX
86120 or an 88/20 system; one master will share the 8086

ARDY
SRDY
RD*
WR*
ALE
3-11

DEN*
DT/R*
CSOUT*
HOLD
HLDA
210912-001

8087 NUMERIC PROCESSOR EXTENSION

82188

80186
HOLD

HOLD

HLDA

HLDA

8087

RQ/GTO

RQ/GTO
RQ/GT1

.r-

RQ/GT1

SYSHOLD
RQ/GT1 r-NC
231051-4

Figure 3·12 8087 NPX - 801861188 CPU System Configuration

3.5 8086 (80186)/8087 OPERATION

COPROCESSOR INTERFACE TO MEMORY

The following paragraphs describe 8087 NPX escape sequence (ESCAPE) operation, and also describe the operational sequence where 8087 controls the bus.

Coprocessor design is greatly simplified if only the reading of memory values of 16 bits or less is required. The
host can perform all the reads with the coprocessor latching the value as it appears on the data bus at the end of T3
during the memory read cycle. The coprocessor does not
need to become a local bus master to read or write additional information.

3.5.1 Decoding Escape Instructions
The coprocessor must examine all instructions executed
by the host to recognize ESCAPE instructions. When the
host fetches an instruction byte from its internal queue,
the coprocessor must also fetch an instruction byte.

If the coprocessor must write information to memory, or
deal with data values longer than one word, it must save
the memory address and be able to become the local bus
master. The read operation performed by the host when
executing the ESCAPE instruction places the 20-bit physical address of the operand on the address/data pins during T1 of the memory cycle. The coprocessor can latch
the address at this time. If the coprocessor instruction also
requires reading a value, it will appear on the data bus
during T3 of the memory read. All other memory bytes
are addressed relative to this starting physical address.

The queue status state, fetch opcode byte, identifies when
an opcode byte is being examined by the host. At the
same time, the coprocessor will check if the byte fetched
from its internal instruction queue is an ESCAPE opcode.
If the instruction is not an ESCAPE, the coprocessor will
ignore it. The queue status signals for fetch subsequent
byte and flush queue let the coprocessor track the host's
queue without knowledge of the length and function of
host instructions and addressing modes.

Whether the coprocessor becomes a bus master or not, it
must be able to identify the memory read performed by
the host in the course of executing an ESCAPE instruction if it has memory reference instruction forms. Identifying the memory read requires the following conditions
be met:

HOST ESCAPE INSTRUCTION PROCESSING

The host performs one of two possible actions when an
ESCAPE instruction occurs. The host may either do nothing or read a word value beginning at that address. The
host ignores the value of the word read. ESCAPE instructions change none of the registers in the host except for
advancing IP. Therefore, the ESCAPE instruction will effectively be a Nap to the host if no coprocessor exists, or
the coprocessor ignores the ESCAPE instruction. Except
for calculating a memory address and reading a word of
memory, the host makes no other assumptions regarding
coprocessor activity.

1. A MOD value of 00, 01 or 10 in the second byte of the
ESCAPE instruction executed by the host.
2. This action must be the first data read memory cycle
performed by the host after it encountered the ESCAPE instruction (Le., S2-S0 will be 101 and S6 will
be 0).
The coprocessor must continue to track the host's instruction queue while it calculates the memory address and
reads the memory value. This simply requires following
the fetch subsequent byte status commands that occur on
the queue status pins.

Memory reference ESCAPE instructions have two purposes. One identifies a memory operand and the other is,
for certain instructions, to transfer a word from memory
to the coprocessor.
3-12

210912-001

8087 NUMERIC PROCESSOR EXTENSION

tions like jumps, it is given the responsibility for synchronization. To meet this need, a special host instruction
exists to synchronization host operation with a coprocessor.

The coprocessor must be aware of the host bus characteristics that determine how the host will read the word operand of a memory reference ESCAPE instruction. An
8088 host will always perform two byte reads at sequential addresses, but an 8086 can perform either single word
read or two byte reads to sequential addresses. The 8086
places no restrictions on the alignment of word operands
in memory. It will automatically perform two byte operations for word operands at an odd address. These two operations are necessary because the two bytes of operand
exist in two different memory words. The coprocessor
must be able to accept the two possible methods of reading a word value on the 8086.

A more detailed discussion of the effects of instruction
execution synchronization between the host CPU and the
8087 coprocessor is contained in the following paragraphs
under "Instruction Synchronization".

COPROCESSOR CONTROL

The host has the responsibility for overall program control. Coprocessor operation is initiated by special "ESCAPE" instructions encountered by the host. When the
host encounters an ESCAPE instruction, the coprocessor
is expected to perform the action indicated by the instruction.

The coprocessor determines whether an 8086 performs
one or two memory cycles as a part of the current ESCAPE instruction execution. During Tl of the first memory read by the host, the ADO pin tells the coprocessor if
this is the only read to be performed as part of the ESCAPE instruction. If ADO is a I during Tl of the memory
cycle, the 8086 immediately follows this memory read
cycle with another one at the next byte address.

The host's coprocessor interface requires the coprocessor
to recognize when the host has encountered an ESCAPE
instruction. Whenever the host begins executing a new
instruction, the coprocessor must look to see if it is an
ESCAPE instruction. Since only the host fetches instructions and executes them, the coprocessor must monitor
the instructions being executed by the host.

3.5.2 Concurrent Execution of Host and
Coprocessor
After the coprocessor has started its operation, the host
may continue on with the program, executing it in parallel
while the coprocessor performs the function started earlier. The parallel operation of the coprocessor does not
normally affect that of the host unless the coprocessor
must reference memory or I/O-based operands. When the
host releases the local bus to the coprocessor, the host
may continue to execute from its internal instruction
queue. However, the host must stop when it also needs the
local bus currently in use by the coprocessor. Except for
the stolen memory cycle, the operation ofthe coprocessor
is transparent to the host.

3.5.3 Instruction Synchronization
Instruction synchronization is required because the 8087
can only perform one numeric operation at a time. Before
any numeric operation is started, the 8087 must have
completed all activity from previous instructions. When
executing a typical NPX instruction, the CPU will complete the ESC long before the 8087 finishes interpretation
of the same machine instruction. Upon completion of the
ESC, the CPU will decode and execute the next instruction, and the NPX's control unit, tracking the CPU, will
do the same. (The NPX "executes" a CPU instruction by
ignoring it.) If the CPU has work to do that does not effect
the NPX, it can proceed with a series of instructions while
the NPX is executing in parallel. The NPX's control unit
will ignore these CPU-only instructions as they do not
contain the 8087 escape code. This asynchronous execution of the processors can substantially improve the performance of systems that can be designed to exploit it.

This parallel operation of the host and coprocessor is
called concurrent execution. Concurrent execution of in-'
structions requires less total time than a strictly sequential
execution would. System performance will be higher with
concurrent execution of instructions between the host and
coprocessor.

SYNCHRONIZATION

Two cases, however, make it necessary to synchronize the
execution of the CPU to the NPX:

In exchange for the higher system performance made
available by concurrent execution, programs must synchronize the coprocessor with the host. Synchronization
is necessary whenever the host and coprocessor must use
information available from the other. Synchronization involves either the host or coprocessor waiting for the other
to finish an operation currently in progress. Since the host
executes the program, and has program control instruc-

1. An NPX instruction that is executed by the numeric
execution unit must not be started if the execution unit
is still busy executing a previous instruction.

2. The CPU should not execute an instruction that accesses a memory operand being referenced by the
NPX until the NPX has actually accessed the location.
3-13

210912·001

8087 NUMERIC PROCESSOR EXTENSION

The host coprocessor synchronization instruction (WAIT)
uses the TEST pin of the host. The coprocessor can signal
that it is still busy to the host via this pin. Whenever the
host executes a wait instruction, it will stop program execution while the TEST input is active. When the TEST
pin becomes inactive, the host will resume program execution with the next instruction following the WAIT.
While waiting on the TEST pin, the host can be interrupted at 5 clock intervals; however, after the TEST pin
becomes inactive, the host will immediately execute the
next instruction, ignoring any pending interrupts between
the WAIT and the following instruction.

To satisfy the second synchronization case, the programmer must explicitly code the FWAIT instruction immediately before a CPU instruction that accesses a memory
operand read or written by a previous 8087 instruction.
This will ensure that the 8087 has read or written the
memory operand before the CPU attempts to use it. (The
FWAIT mnemonic causes the assembler to create a CPU
WAIT instruction that can be eliminated at link time if the
program is run on an 8087 emulator.)
A typical sequence of instructions that illustrates the effect of the WAIT instruction and parallel execution of the
NPX with a CPU is shown in Figure 3-13). The first two
instructions in the sequence (FMUL and FSQRT) are
8087 instructions that illustrate the ASM -86 assembler's
automatic generation of a preceding WAIT, and the effect
of the WAIT when the NPX is, and is not, busy.

The WAIT instruction allows software to synchronize the
CPU to the NPX so that the CPU will not execute the
following instruction until the NPX is finished with its
current (if any) instruction.
Whenever the 8087 is executing an instruction, it activates
its BUSY line. This signal is wired to the CPU's TEST*
input as shown in Figure 3-11. The NPX ignores the
WAIT instruction, and the CPU executes it. The CPU interprets the WAIT instruction as "wait while TEST* is
active." The CPU examines the TEST* pin every 5
clocks. If TEST* is inactive, execution proceeds with the
instruction following the WAIT. If TEST* is active, the
CPU examines the pin again. Therefore, the effective execution time of a WAIT can stretch from 3 clocks (3
clocks are required for decoding and setup) to infinity, as
long as TEST" remains active. The purpose of the WAIT
instruction is to prevent the CPU from decoding the next
instruction until the 8087 is not busy. The instruction following a WAIT is decoded simultaneously by both processors.

Since the NPX is not busy when the first WAIT is encountered, the CPU executes it and immediately proceeds to
the next instruction, and the NPX ignores the WAIT. The
next instruction is decoded simultaneously by both processors. The NPX starts the multiplication and raises its
BUSY line. The CPU executes the ESC and then the second WAIT. Since TEST* is active (it is tied to BUSY), the
CPU effectively stretches execution of the multiply by
lowering BUSY. The next instruction is interpreted as a
square root by the NPX and another escape by the CPU.
The CPU finishes the ESC well before the NPX completes the FSQRT. This time, instead of waiting, the CPU
executes three instructions (CMP, JG and MOV) while the
8087 is working on the FSQRT. The 8087 ignores these
CPU-only instructions. The CPU then encounters the
third WAIT, generated by the assembler immediately preceding the FIST (store stack top into integer word). When
the NPX finished the FSQRT, both processors proceed to
the next instruction, FIST to the NPX and ESC to the
CPU. The CPU completes the escape quickly and then
executes an explicit programmer-coded FWAIT to ensure
that the 8087 has updated BETA before it moves BETA's
new value to the register AX (refer to Figure 3-13).

To satisfy the first synchronization case, every 8087 instruction that affects the numeric execution unit should be
preceded by a WAIT to ensure that the execution unit is
ready. All instructions except the processor control class
affect the numeric execution unit. To simplify programming, the 8086 family language translators provide the
WAIT automatically, therefore, when an assembly language programmer codes:
FMUL
FDIV

The 8087 control unit can execute most processor control
instructions by itself regardless of what the numeric execution unit is doing. Therefore, in these cases the 8087
can potentially execute two instruction at once. The
ASM-86 assembler provides separate"wait" and "no
wait" mnemonics for these instructions. For example, the
instruction that sets the 8087 interrupt enable mask, and
therefore disables interrupts, can be coded as FDISI or
FNDISI. The assembler does not generate a WAIT if the
second form is coded, so that the interrupts can be disabled while the numeric execution unit is busy with a previous instruction. The no-wait forms are principally used
in exception handlers and operating systems.

; (multiply)
; (divide)

The assembler produces four machine instructions, as if
the programmer had written:
WAIT
FMUL
WAIT
FDIV

;(multiply)
;(divide)

This ensures that the multiply runs to completion before
the CPU and the 8087 control unit decode the divide.
3-14

210912·001

8087 NUMERIC PROCESSOR EXTENSION

;ASSUME 8087 REGISTER STACK IS LOADED WITH OPERANDS,
,
NEU IS NOT BUSY,
AND THAT' ALPHA' AND' BETA' ARE WORD
INTEGERS.
FSQRT
CMP
JG
MOV
CONTINUE: FIST
FWAIT

ALPHA,100
CONTINUE
ALPHA, 1 00
BETA

MOV

BUsv ..fEST:

AX,BETA

~_F_M_UL_.....I

NDP:

__-,I

MULTIPLY TOP STACK
ELEMENTS
SQUARE ROOT OF PRODUCT
ALPHA> 100 7
YES, LEAVE UNALTERED
NO, SET TO 100
STORE ROOT AS INTEGER WORD
WAIT FOR 8087 TO COMPLETE
STORE OF BETA
PROCEED TO PROCESS BETA

I..._____F_S_Q_RT_ _ _ _---'II

V

FIST

I

V"""'----''--

NOTES:
•

[W~iJ = Assembler-generated instruction .

• Instruction execution times are not drawn to scale.

Figure 3-13 Synchronizing Execution With WAIT

NOTE

3.6 BUS OPERATION

The 8086/8088 must be the only processor on
the local bus to drive S6 low.

Connecting the 8087 in tandem with an 8086
(iAPX86/20) or with an 80186 (iAPXI86120), does not
change system bus operation from the normal operation
of the bus in a iAPX861l0 or iAPX186/1O system. However, some minor differences exist between the
iAPX86120 and the iAPX186/20 systems, primarily due
the requirement for a 82188 Interface chip in the
iAPX186120 system. For additional information on the
82188 Integrated Bus Controller refer to the Preliminary
Data Sheet Revision 1.2. The following paragraphs describe the operation and timing of the bus in the various
configurations.

Line S7 multiplexes with BHE* and has the same value as
BHE* for all 8087 bus cycles. When an 8288 Bus Controller is used, status lines SO*-S2 * are used to determine
the type of bus cycle being run, as shown in the following
list:

o

Sl*
X

1
1

o

S2*

o

1

1

1

1

SO*
X Unused
o Unused
1 Memory Data Read
o Memory Data Write
1 Passive (no bus cycle)

3.6.1 iAPX86/20 Bus Operation

3.6.2 iAPX186/20 Bus Operation

Operation and timing for the 8087 bus structure are identical to all other processors in the maximum mode configuration iAPX 86,88 series and the iAPX 186, 188 series.
The address time-multiplexes with the data on the first
16/8 lines of the address/data bus. A16 through A19 are
time-multiplex with four status lines S3-S6. Lines S3, S4,
and S6 are always high (logical 1) for 8087 driven bus
cycles while S5 is always low (logical 0). When the 8087
is monitoring CPU bus cycles (passive mode), the 8087
monitors S6 to discriminate between 8086/8088 activity
and that of a local I/O processor or any other local bus
master.

The 82188 Interface chip provides a local bus arbitration
function for an 80186 system consisting of an 80186, an
8087 and a third processor with a HOLD-HLDA type bus
exchange protocol. The 82188 also provides the bus control signals otherwise supplied to the system by the 80186
and contains ARDY and SRDY signals to its own integral
Ready circuit (refer to paragraph 3.4.2).
The 82188 also has an integral queue status circuit which
inserts a one-phase delay on the queue status signals to
meet the 8087 Queue-Status timing requirements (refer to
paragraph 3.4.2).
3-15

210912-001

8087 NUMERIC PROCESSOR EXTENSION

BUS ARBITRATION

READY CIRCUIT

The 82188 defines the priorities for access to the system
bus for multiprocessor systems that include an 80186 and
an 8087. As indicated in Figure 3-14), HOLD output
from the 80186 and HLDA input to the 80186 interconnect directly to the 82188. The 82188 then exchanges its
own HOLD output and the HLDA input with the system.
In this configuration, the 82188 assigns the highest system bus access priority to the system (third processor in
Figure 3-14), second priority to the 8087, and default to
the 80186.

The system ARDY and SRDY signals are applied to the
82188 inputs for these signals. The 82188 samples SRDY
on the rising edge of the clock. Since ARDY is asynchronous, the 82188 contains a one-phase synchronizer at
its ARDY input. Using this synchronizer, the 82188 synchronizes only the leading edge of ARDY (the 82188 presumes the trailing edge of ARDY falls on the eLK edge).
From the ARDY and SRDY inputs, the 82188 produces a
single synchronized Ready signal SRO. The SRO is applied to the 8087 READY input and the 80186 SRDY input (note that the 80186 ARDY input should be tied low).

When the 8087 has control of the bus, and the third processor needs the bus, the 82188 asserts RQ* IGTl * to take
control of the bus from the 8087 and pass control to the
third processor. If the 8087 does not have control of the
bus, the 82188 passes control directly to the third processor without exercising the 8087 RQ*/GTl * protocol. The
80186 will not regain control of the bus from the 82188
until both the third processor and the 8087 are finished
with the bus.

The inherent 82188 propagation delays cause
iAPX186120 system timing to differ from that of a
iAPX186110 system. The 82188 samples ARDY one
clock phase earlier than in a non-iAPX186/20 system.
Also, SRDY setup time to the eLK falling edge is 30ns
longer than the 80186 requirements (the 82188 changes
SRO only when eLK is high).
The 82188 inserts three Wait states, by using SRO, in the
first 256 80186 bus cycles after a Reset. (This feature is
for programmer use to re-program the 80186 Wait State
generator to 0 Wait states.)

The third processor uses the system HOLD and HLDA
(SYSHOLD and SYSHLDA) lines to request bus access
from the 82188. Similarly, the 82188 uses the 80186
HOLD and HLDA lines to gain bus control from and return bus control to the 80186. The 82188 also uses the
RQ*/GTO* lines from the 8087 for NPX bus control.

3.7 BUS EXCHANGE MECHANISM
Two basic decisions must be made when connecting the
8087 to a system: 1.) interconnection of the RQ/GT signals of all of the local bus masters; and 2.) connecting the
Interrupt (INT) signal pin. The decision on where to connect the RQ/GT signal that is made at this point affects the
response time needed to service local bus requests from
other local bus masters, such as an 8089 lOP or other
coprocessor. The interrupt connection affects the response time to service an interrupt request and how
user-interrupt handlers are written. The implications of
how these pins are connected concern both the hardware
designer and programmer and must be understood by
both. The following paragraphs provide information on
making the decision where to connect the RQ/GT signal.
Refer to paragraph 3.8 for the discussion on interconnection of the Interrupt (INT) signal.

NOTE
The 82188 contains weak pull-up devices to
set both RQ*/GTl * and RQ*/GTO* high if the
82188 is configured in a system with out an
8087.

BUS CONTROL SIGNALS

Status line outputs from the 80186 and the 8087 (see Figure 3-12) are sent to the 82188. The 82188 decodes these
signal lines and generates bus control signals that would
otherwise be generated and output directly by an 80186.
The signals decoded by the 82188 include:

3.7.1 8087 RQ/GT Function

ALE
RD*
WR*
DT/R*
DEN*

The presence of the 8087 in the RQ/GT path from the lOP
to the host has little effect on the maximum wait time seen
by the lOP when requesting the local bus. The 8087 adds
two clocks of delay to the basic time required by the host.
This low delay is achieved due to a preemptive protocol
implemented by the 8087 on RQ/GTl.

The 82188 also contains the AEN* input which enables
the system command lines. This signal provides the hardware designer with the ability to tri-state RD*, WR *, and
DEN* by asserting AEN* high SO*, SI * and S2* decode
exactly the same as for the 8086 and the 80186.

The 8087 always gives higher priority to a request for the
local bus from a device attached to its RQ/GTl pin than to
a request generated internally by the 8087. If the 8087
3-16

210912-001

8087 NUMERIC PROCESSOR EXTENSION

80186

82188

8087

HOLD

HOLD

RQ/GTO

HLDA

RQ/GTO

HLDA

3 RD pROC

HLDA

SYSHLDA

HOLD

SYSHOLD

RQ/GT1

RQ/GT1

231051-3

Figure 3-14 Three Processor System Bus Signal Connections

currently owns the local bus and a request is made to its
RQ/GTl pin, the 8087 will finish the current memory
cycle and release the local bus to the requestor. If the
request from the devices arrives when the 8087 does not
own the local bus, the 8087 will then pass the request on
to the host via its RQ/GTO pin.

An 8086 host will not release the local bus between the
two consecutive byte operations performed for
odd-aligned word operands. In contrast, the 8088 will
never release the local bus between two bytes of a word
transfer, independent of its byte alignment. Host operations such as acknowledging an interrupt will not release
the local bus for several bus cycles. Using a lock prefix in
front of a host instruction prevents the host from releasing
the local during the execution of that instruction.

The RQ/GT issue can be broken into three general catagories depending on system configuration: 86/20 or
88120,86/21 or 88/21, and 86122 or 88122. Remote operation of an lOP is not effected by the 8087 RQ/GT connection.

iAPX 86/22, 88/22 SYSTEM CONFIGURATION

An 86/22 system offers two alternatives in regards to
which lOP to connect to an 110 device. Each lOP will
offer a different maximum delay time to service an 110
request. (See Figure 3-16.)

iAPX 86/20, 88/20 SYSTEM CONFIGURATION

For an 86/20, 88/20 just connect the RQ/GTO of the 8087
to RQ/GTO (1) of the host (see Figure 3-3).

The second 8089 (lOPA) must use the RQ/GTO pin of the
host. When using two lOP's the designer must decide
which lOP services which 110 devices. This decision is
determined by the maximum wait time allowed between
the time an 110 device requests lOP service and when the
lOP can respond. Since the maximum service delay times
of the two lOP's can be very different, it makes very little
difference which of the two host RQ/GT pins are used.

iAPX 86/21, 88/21 SYSTEM CONFIGURATION

For an 86121 or 88121, connect RQ/GTO of the 8087 to
RQ/GTO(I) of the host and connect RQ/GT of the 8089 to
RQ/GTl ofthe 8087 (see Figure 3-15).

The different wait times are due to the non-preemptive
nature of bus grants between the two host RQ/GT pins.
IOPA and the 8087/IOPB combination cannot communicate about the need to use the local bus. Any request for
the local bus by the IOPA must wait (worst case) for the
host, the 8087, and the 10PB to finish their longest sequence of memory cycles. 10PB must wait in the worst
case for the host and 10PA to finish their longest sequence
of memory cycles. The 8087 has little effect on the maximum wait time of 10PB.

The RQ/GTl pin of the 8087 exists to provide one 110
processor with a low maximum wait time for the local
bus. The maximum wait times to gain control of the local
bus for a device attached to RQ/GTl of an 8087 for an
8086 or 8088 host are shown in Table 3-2. These numbers
are all dependent on when the host will release the local
bus to the 8087.
Three factors determine when the host will release the
local bus (see Table 3-2):

3.7.2 Delay Effects of the 8087

1. Type of host;

2. Current instruction being executed;

The delay effects of the 8087 on 10PA can be significant.
When executing special instructions (FSAVE, FNSAVE,

3. Use ofthe lock prefix.
3-17

210912·001

8087 NUMERIC PROCESSOR EXTENSION

-

ClK

~

!~

r

AID

8088
~

r"'

READY

RESET

STATUS

as fHf

RC/GTf

"'" 7

ROlaTil os

r1D~

ill

L

I
(3)8282

I

ADDRESS
LATCHES

......

~

BUSY

!L- ~ i;L~
AID

rv'

rv-i7

DATA

~

TRANSCEIVER

T

DATA

;L

8286

8087

ClK

ADDRESS

~=;I

STB

READY

8284A

I

I

--V

~

\r-

READY

..,

j--

IA

fV

OE

ClK

CLOCK
GENERATOR

REseT

RESET

STATUS

RQIGT1

M
\rV

t

-

SYSTEM

READY

.o!~

4

--

RQ/GT

RESET

AID

8089

!L- W\

\r-

IV'

I

DT/R

READY

ClK

I
I
I
I
c- ALE

STATUS

r--l\

IY

DEN -

8288

h

STATUS

V

CON:~gLLER
ClK

I
I
I
I
ICOMMANKs I

I

I
I

V

I

I
I
ISYSTEM'
I BUS ,
L _ _ .J

Figure 3·15 iAPX 88/21 System Configuration

3·18

210912-001

8087 NUMERIC PROCESSOR EXTENSION

Table 3-2 Worst Case Local Bus Request Wait Times In Clocks
System
Configuration

No Locked
Instructions

Only Locked
Exchange

Other Locked
Instructions

iAPX 86121
even aligned words

lSI

3S 1

max (lSI'

iAPX 86/21
odd aligned words

lSI

43 2

max (43 2• 0 )

iAPX 88121

lSI

43 2

max (43 2• 0 )

0)

Notes: 1. Add two cla<:ks for each wait state inlCl'ted per bus cycle
2. Add four clocks for each wait state inserted per bu. cycle
• Execution time of IOlllest loc:ked instruction

FRSlDR), the 8087 can perform 50 or 96 consecutive
memory cycles with an 8086 or 8088 host, respectively.
These instructions do not affect response time to local bus
requests seen by an IOPB.

respectively). The FSAVE/FNSAVE/FRSlDR instructions, in contrast, perform 50/94 back-to-back memory
cycles for an 8086 or 8088 host.
COMPATIBILITY WITH FSAVE/FNSAVE

If the 8087 is performing a series of memory cycles while
executing these instructions, and IOPB requests the local
bus, the 8087 will stop its current memory activity, then
release the local bus to IOPB. The 8087 cannot release the
bus IOPA since it cannot know that IOPA wants to use the
local bus, like it can for IOPB.

This technique produces a context area of the same format
produced by the FSAVE/FNSAVE instructions. Other
software modules expecting this type of format will not be
affected. All of the same interrupt and deadlock considerations that apply to FSAVE and FNSAVE also apply to
FSTENV and FNSTENV. With the exception that the numeric environment is 7 words rather than the 47 words of
the numeric context, all factors concerning the use of the
FSAVE/FNSAVE also apply.

3.7.3 Reducing 8087 Delay Effects
For 86122 or 88122 systems requiring lower maximum
wait times for IOPA, it is possible to reduce worst case
bus usage. If three 8087 instructions are never executed
(namely FSAVE, FNSAVE, or FRSlDR) the maximum
number of consecutive memory cycles performed by the
8087 is 10 or 16 for an 8086 or 8088 host respectively.
The function of these instructions can be emulated with
other 8087 instructions.

The state of the NPX registers must be saved in memory
in the same as used with the FSAVE/FNSAVE instructions. The program example (see Figure 3-17) starting at
the label SMALLJ3LOCK......NP~SAVE illustrates a
software loop that will store their contents into memory in
the same top relative order as that of FSAVE/FNSAVE.
To save the registers the FSTP instructions, the FSTP instructions must be tagged valid, zero, or special. This
function will force all the registers to be tagged valid,
independent of their contents or old tag, and then save
them. No problems will arise if the tag value conflicts
with the register's content for the FSTP instruction. Saving empty registers insures compatibility with the
FSAVE/FNSAVE instructions. After saving all the numeric registers, they will all be tagged empty, the same as
if an FSAVE/FNSAVE instruction had been executed.

There are alternative techniques for switching the numeric context without using the FSAVE/FNSAVE or
FRSlDR instructions. These alternative techniques are
slower than those using these instructions, but they reduce
the worst case continuous local bus usage of the 8087.
Only an iAPX 86/22 or iAPX 88/22 systems derive any
real benefit from these alternatives. By replacing all
FSAVE/FNSAVE instructions, the worst case local bus
usage of the 8087 will be 6 or 10 consecutive bus cycles
for the 8086 or 8088 host, respectively.

COMPATIBILITY WITH FRSTOR

Instead of saving and loading the entire numeric context
in one long series of memory transfers, these alternative
routines use the FSTENV/FNSTENV/FLDENY instructions and separate numeric register load/store instructions. Using separate load/store instructions for the
numeric registers forces the 8087 to release the local bus
after each numeric load/save instruction. The longest series of back-to-back transfers required by these instructions are 8/12 memory cycles (8086/8088 host,

Restoring numeric context reverses the procedure described in the preceding paragraphs. This is shown by the
code starting at SMALLJ3LOCK-NP~ESlDRE
(see Figure 3-18). All eight registers are reloaded in the
reverse order. With each register load, a tag value will be
assigned to each register. The tags assigned by the register
load do not since the tag word will be {)verwritten when
the environment is reloaded later with FLDENV.
3-19

210912-001

8087 NUMERIC PROCESSOR EXTENSION

r--'
I

IADDRESS

.------

-----

--

I~

READY

eLK

J\

ADDRESS
LATCHES

V

(3)8282

AID

8089
(IOPA)

I

'"

STB

~

f---J\

STATUS

RESET

~

IV

RQ/GT

SYSTEM

RElDY

IA

RO/GTO
READY

READY

.. t-- IA.

j..

I'

v

AID

V

I'
8284A

STATUS

CLK

IV

8086

eLK

as:==-

CLOCK
GENERATOR
RESET

REseT

YOrJ

ROlm Tm

f---J\

DATA
TRANSCEIVERS

(2)8286

I
I
I
I
1
1
I
1

~
1

T

DE

I
I
1
I

OT/R

DEN

ICOMMAN Dsl

I

1-

~

IV

ALE

8288
STATUS

BUS CONTROLLER
eLK

I

I
I

V
I
I
ISYSTE MI

L.!U! .J

! -! - r -

t-t--

READyRQ/GTO BUSY ! -

8087

cslA--

eLK
AID

IrI'

t--

J\
V

STATUS

REseT

Allilm

I'

f---J\
IV
r--

'-

ifIllill

t-t--

READY

'-r-

eLK

AID~
I'

~

V

8089
(IOPB)

RESET

"

STATUS

V

Figure 3·16 iAPX 86/22 System
Two assumptions are required for the correct operation of
the restore function. First, all numeric registers must be
empty, and second, the TOP field must be the same as that
in·the context being restored. These assumptions will be

satisfied if a matched set of pushes and pops were performed between saving the numeric context and reloading
it. If these assumptions cannot be met, the code example
(see Figure 3-19)starting at NP~CLEAN shows how

3-20

210912-001

8087 NUMERIC PROCESSOR EXTENSION

Save the NPX context independent of NDP interrupt state. Avoid using the FSAVE instruction to
limit the worst case memory bus usage of the 8087. The NPX context area formed will appear the
same as if an FSAVE instruction had written into it. The variable save_area will hold the NPX
context and must be 47 words long. The registers ax, bx, and cx will not be transparent.
small_block_N PX_save:
FNSTCW save_area
NOP
FNDISI
ax, save_area
MOV
MOV
cx,8
XOR
bx, bx
FSTENV save_area
FWAIT
XCHG
save_area + 4, bx
FLDENV save_area
MOV
save_area, ax
MOV
save_area + 4, bx
XOR
bx, bx

Save current IEM bit
Delay while 8087 saves control register
Disable 8087 BUSY Signal
Get original control word
Set numeric register count
Tag field value for stamping all registers as valid
Save NPX environment
Wait for the store to complete
Get orig i nal tag val ue and set new tag val ue
Force all register tags as valid. BUSY is still masked. No data
synchronization needed. Put original control word into NPX
environment. Put original tag word into NPX environment
Set initial register index

reg_store~loop:

FSTP
ADD
LOOP

saved_reg [bx)
bx, type saved_reg
reg_store_loop

Save register
Bump pOinter to next register
All done

Figure 3-17 SMALLBLOCLNPLSAVE
to force all the NPX registers empty and set the WP of
field in the status word.

restore operations. These operations appear in
time-critical context-switching functions of an operating
system or interrupt handler. This technique has no affect
on the maximum wait time seen by IOPB or wait time
seen by IOPA due to IOPB:

These improvements do have a cost. This is the increased
execution time of 427 or 747 additional clocks for an
8086 or 8088, respectively, for the equivalent save and

Restore the NPX context without using the FRSTOR instruction. Assume the NPX context is in the
same form as that created by an FSAVE/FNSAVE instruction, all the registers are empty, and that
the TOP field of the N PX matches the TOP field of the N PX context. The variable save_area must
be an NPX context save area, 47 words long. The registers bx and cx will not be transparent.
small_blocLNPX_restore:
MOV
cX,8
MOV
bx, type saved_reg"7
reg_load_loop:
FLO
saved_reg [bx)
SUB
bx, type saved_reg
LOOP
reg_load_loop
FLDENV save_area

; Set register count
Starting offset of ST(7)
Get the register
Bump pOinter to next register
Restore N PX context
All done

Figure 3-18 SMALL_BLOCLNPLRESTORE
3-21

210912-001

8087 NUMERIC PROCESSOR EXTENSION

Force the NPX into a clean state with TOP matching the TOP field stored in the NPX context and all
numeric registers tagged empty. Save_area must be the NPX environment saved earlier.
; Temp_env is a 7 word temporary area used to build a prototype NPX environment. Register ax will
; not be transparent.
NPX_clean:
FINIT
MOV
AND
FSTENV

ax, save_area + 2
ax, 3800H
temp_env

FWAIT
OR
FLDENV

temp_env + 2, ax
temp_env

Put NPX into known state
Get original status word
Mask out the top field
Format a temporary environment area with all registers
stamped empty and TOP field =O.
Wait for the store to finish.
Put in the desired TOP value.
; Setup new NPX environment.
; Now enter small_block_NPX_restore

Figure 3·19 NPX_CLEAN Code Example
Which lOP to connect to which 110 device in an 86/22 or
88/22 system will depend on how quickly an 110 request
by the device must be serviced by the lOP. This maximum
time must be greater than the sum of the maximum delay
of the lOP and the maximum wait time to gain control of
the local bus by the lOP.

3. The 8087 interrupt is a stop everything event. Choose
a high priority interrupt input that will terminate all
numerics related activity. This is a special case since
the interrupt handler may never return to the point of
interruption (i.e., reset the system and restart rather
than attempt to continue operation).
4. Numeric exceptions or numeric programming errors
are expected and all interrupt handlers either do not
use the 8087 or only use it with all errors masked. Use
the lowest priority interrupt input. The 8087 interrupt
handler should allow further interrupts by higher priority events. The PIC's priority system will automatically prevent the 8087 from disturbing other
interrupts without adding extra code to them.

3.8 INTERRUPTS
One of the most important decisions to make in adding the
8087 to an 8086 or 8088 system is where to attach the
8087 Interrupt (INT) signal. The 8087 INT pin provides
an external indication of software-selected numeric errors. This causes the numeric program to stop until something is done about the error. A numeric error occurs in
the NPX whenever an operation is attempted with invalid
operand or attempts to produce a result which cannot be
represented. Deciding where to connect the INT signal
can have important consequences on other interrupt handlers.

5. Case 4 holds except that interrupt handlers may also
generate numeric interrupts. Connect the 8087 INT
signal to multiple interrupt inputs. One input would
still be the lowest priority input as in case 4. Interrupt
handlers that may generate a numeric interrupt may
require another 8087 INT connection to the next highest priority interrupt. Normally the higher priority numeric interrupt inputs would be masked and the low
priority numeric interrupt enabled. The higher priority interrupt would be unmasked only when servicing
an interrupt which requires 8087 exception handling.

3.8.1 Recommended Interrupt
Configurations
Five categories cover most of the uses of the 8087 interrupt in fixed priority interrupt systems. The following
presents an interrupt configuration for each of these categories.

All of these configurations hide the 8087 from all interrupt handlers which do not use the 8087. Only those interrupt handlers that use the 8087 are required to perform
any special 8087 related interrupt control activities.

1. All errors on the 8087 are always masked. Numeric
interrupts are not possible. Leave the 8087 INT signal
disconnected.

A conflict can arise between the desired PIC interrupt input and the required interrupt vector of 1016 for compatibility with Intel software for numeric interrupts. A simple
solution is to use more than one interrupt vector for numeric interrupts, all pointing at the same 8087 interrupt
handler. Design the numeric interrupt handler so that it

2. The 8087 is the only interrupt in the system. Connect
the 8087 INT signal directly to the host's INTR input
(see Figure 3- 20). A bus driver supplies interrupt
vector 10 16 for compatibility with Intel supplied software.

3·22

210912-001

8087 NUMERIC PROCESSOR EXTENSION

Disable any possible numeric interrupt from the 8087. This code is safe to place in any
procedure. If an 8087 is not present, the ESCAPE instructions will act as nops. These
; instructions are not affected by the TEST pin of the host. Using the 8087 emulator will not
convert these instructions into interrupts. A word variable, called control, is required to hold
the 8087 "ontrol word. Control must not be changed until it Is reloaded Into the 8087.
ESC 15, control
NOP
NOP
ESC 28,cx

;
;
;
;
;
;
;

(FNSTCW) Save current 8087 control word
Delay while 8087 saves current control
register value
(FNDISI) Disable any 8087 interrupts
Set IEM bit in 8087 control register
The contents of cx is Irrelevant
Interrupts can now be enabled

(Your Code Here)
Reenable any pending interrupts in the 8087. This instruction does not disturb any 8087 instruction
currently in progress since ail it does is change the IEM bit in the control register.
; Look at IEM bit
; If IEM = 1 skip FNENI
; (FNENI) reenable 8087 interrupts

TEST control,80H
JNZ $+4
ESC 28,ax

Figure 3-20 Inhibit/Enable 8087 Interrupts
does not need to know what the interrupt vector was (i.e.,
do not use specific EO! commands). If an interrupt system uses rotating interrupt priorities, it does not matter
which interrupt is used.

3-23

210912·001

8089 Input/Output
Processor

4

CHAPTER 4
8089 INPUT/OUTPUT PROCESSOR
4.1 INTRODUCTION

16-bit word and then writes the single word to the addressed memory location. Both 8-and 16-bit peripherals
can reside on the same (l6-bit) bus because the lOP transfers bytes with the 8-bit peripheral, and transfers words
with the 16-bit peripheral.

This chapter contains specific hardware design information on the operations and functions of INTEL's 8089
Input/Output Processor (lOP) when used with the iAPX
86,88 and iAPX 186,188 family of microprocesssors.
The chapter contains general information on the lOP,
along with a component overview presenting architectural
and software considerations, and individual device pin
functional signal definitions. Detailed descriptions of the
lOP's operating modes, bus operation, bus exchange
mechanisms and a description of interrupt operation are
also provided. For more specific information of any of the
8086 family support circuits, refer to the Microsystems
Components Handbook (Order Number 230843-002).

4.2.1 Architectural Overview
The 8089 lOP is internally divided into the functional
units described in the following paragraphs (see Figure
4-1). These functional units are connected by a 20-bit data
path to obtain maximum internal transfer rates.

COMMON CONTROL UNIT (CCU)
lOP operations (instructions, DMA transfer cycles, channel attention responses, etc.) are composed of sequences
called internal cycles. A single bus cycle takes one internal cycle, therefore, the execution of an instruction may
require several internal cycles. There are 23 different
types of internal cycles. Each of these take from two to
eight clocks to execute, not including possible wait states
and bus arbitration resolving.

4.2 COMPONENT OVERVIEW
The 8089 Input/Output Processor (lOP) is an intelligent
DMA controller that is used with the Intel iAPX 86,88
and iAPX 186,188 family of microprocessors. The processing power of the 8089 lOP can remove 110 overhead
from the 8086, 8088, 80186 or 80188 microprocessors.
In addition, it may operate concurrently with a CPU, giving improved performance in 110 intensive applications
over an iAPX 86,88 or iAPX 186,188 system operating
without an 8089. The 8089 provides two 110 channels,
each supporting a transfer rate of up to 1.25 megabytes
per second at the standard clock frequency of 5 MHz.
Memory based communication between the lOP and CPU
enhances system flexibility and encourages software modularity for more reliable, easier to develop systems.

The Common Control Unit (CCU) coordinates lOP activities by allocating internal cycles to the various processor units, i.e., the CCU determines which unit will
execute the next internal cycle. For example, when both
channels are active, the CCU determines which channel
has priority and lets that channel run; if the channels have
equal priority, the CCU "interleaves" their execution.
The CCU also initializes the processor.

The 8089 lOP combines the functions of a DMA controller with the processing capabilities of a microprocessor.
In addition to the normal DMA function of transferring
data, the 8089 dynamically translates and compares data
as it is transferred. The lOP also supports a number of
terminate conditions, including byte count, data compare
or miscompare, and the occurrence of an external event.
Each of the two separate DMA channels contains its own
register set. Depending on the established priorities (both
inherent and program determined), the two channels can
alternate (interleave) their respective operations.

ARITHMETIC/LOGIC UNIT (ALU)
The Arithmetic/Logic Unit (ALU) can perform unsigned
binary arithmetic on 8-and 16-bit binary numbers. The
results of this arithmetic may be up to 20 bits in length.
Available arithmetic instructions include addition, increment and decrement. Logical operations ("and," "or"
and "not") may be performed on either 8-or 16-bit quantities.

ASSEMBLY/DISASSEMBLY REGISTERS

The 8089 has transfer flexibility integrally designed into
it. It will perform routine transfers between an I/O peripheral and memory, and, in addition, transfer data between two 110 devices or between two areas of memory.
The 8089 automatically handles transfers between dissimilar bus widths. When the 8089 transfers data from an
8-bit peripheral bus to a 16-bit memory bus, it reads two
bytes from the peripheral, assembles the bytes into a

All data entering the chip flows through the
AssemblylDissassembly registers. When data is being
transferred between different width buses, the 8089 uses
the assembly/disassembly registers to effect the transfer
in the fewest possible bus cycles. During a DMA transfer
from an 8-bit peripheral to 16-bit memory, for example,

4-1

210912·001

8089 INPUT/OUTPUT PROCESSOR

CA

~----liil

1/0 CONTROL

TASK POINTER ~
I------I~
I/O CONTROL -ADDRESS VALID

AD, 5-AO o

eK

XNJJIX
-l rTCSAK
~

TSACK

FLOAT

ADDRESS VALID

WRITE DATA VALID

H

---

I

REA o CYCLE

AO'5- A00

I

~

TelDV

READ DATA VALID

~

ACK

TSACK

I

\ . - - TCSAK

)9
FLOAT

~

\

Figure 5-4 80130 OSP Timing Diagram

The propagation delay numbers used in the preceding
equation are worst-case values from the appropriate data
sheets. The CPU is an 8086-2 operating at 8 MHz. This
means the address decode logic must produce stable CS
outputs within 140 nanoseconds. Using standard, low
power Schottky TTL, it will typically not take longer than
140 nsec. to decode 6 program or 12 110 address bits.
Even if these timing specifications are not met the 80130
will work fine, although performance would be degraded
some because wait states would be needed until the
chip-select signal became active.
The second point of concern relates to ready signal timing. The 80130's acknowledge output signal, ACK*, can
be used to control the CPU's ready signal. For this case,
the chip-select signal must be active early in a memory or
I/O cycle to allow activation of ACK* early enough to
prevent wait states. There are two schemes for implementc
ing ready signals; "normally ready" and "normally not
ready". (For more details, refer to AP-67, "8086 System
Design.") Chip-select timing is more critical in some
"normally not ready" systems.

In a "normally not ready" design, acknowledge signals
are generated when each resource is accessed. The individual acknowledgements are combined to form a
system-wide ready signal which is synchronized by the
8284A clock generator via the RDY and AEN inputs. The
8284A can be strapped to accept asynchronous ready signals (asynchronous operation) or to accept synchronous
ready signals (synchronous operation). Synchronous
8284A operation provides more time for address latch
propagation and chip-select decoding. In addition, inverting ACK off chip produces an active-high ready signal
compatible with the 8284A RDY inputs, which have
shorter set-up requirements than AEN inputs. (Also, a
NAND gate used like this can combine ACK with the
active-low acknowledge signals from other parts of the
system.) Based on these assumptions, the time available
for address latch propagation and chip-select decoding at
8 MHz is:
T cLAv + Tovcs + TCSAK +RRIVCLo5TcLCL + T cLcL
T ovcs o52 TCLCL -TcLAv-TcsAK-TRlvcL

05250-60-110-35
0545 nsec.

5-14

210912-001

80130 OPERATING SYSTEM FIRMWARE

8288
80130

8086

as'

ALE

CPU

A19

BDG 8Q

A19

7D

70

A17

6D

A,.

'A

5D

50

AD15

4D

40

AD14

3D

30

}-DECODe

~

745373

READY
SYSTEM
ACKNOWLEDGE

Figure 5·5 Hlgh·Speed Address Decoding Circuit
The OSP will still operate even if the memory or 110 decoding is slow. The acknowledge signal returned to the
host CPU would just be delayed accordingly, so unnecessary wait states would be inserted in the access cycle, but
the 80130 would not malfunction. The OSP seldom accesses resources in its own I/O space. Even if slow decode
logic were to insert several wait states into every I/O cycle, the overall effect on system performance would be
insignificant.

A typical circuit (see Figure 5-5) which uses Schottky
TTL components leaves approximately 15 nanoseconds to
produce MEMCS* from the high order address bits, more
than enough for the 74S 138 one-of-eight decoders. This
type of circuit allows a minimum of time to fully decode
the 110 bits. Also, a 12-input NAND gate on ADl5-AD4
could be used. This introduces only a single propagation
delay, but forces the 110 register to start at OFFFOH. Incomplete decoding is also allowable; it is safe to drive
IOCS* with the (latched) AD15 signal directly, provided
all other ports in the system are disabled when this bit is
low. In this case, the effective address of the I/O block
(which must be specified during the system configuration
step) could be OOOOH, or any other multiple of 16 between OOOOH and 7FFOH.

The designer must exercise caution, though, if the 8284A
is strapped for synchronous operation. In this case, external circuits must guarantee that ready-input transitions do
not violate the latch set-up requirements. Also, the
chip-select signal must not remain low so long after the
address changes that the 80130 could respond to a
non-80130 access cycle.

5-15

210912·001

Index

INDEX
1
16-bit External Data Bus, 1-1
16-bit I/O Decode, 1-88
16-bit to 8-bit Bus Conversion, 1-88
16-byte Memory Boundaries, 1-8
2
2118 Family Timing, 1-87
2-byte Wait Escape, 3-2
4
4-byte Instruction Queue, 1-2

5
5 MHz 8086 System Using An 8202 Dynamic RAM
Controller, 1-85

6
6-byte Instruction Queue, 1-2
8
8-bit Transfer, 1-85
80130 ARCHITECTURE, 5-1
80130 OSP Pinout Diagram, 5-3
80130 OSP Timing Diagram, 5-14
80130 Pin Descriptions, 5-4
80130 Simplified Functional Block Diagram, 5-2
80130/80150 Operating System Firmware, 5-1
80186 Address Generation Timing, 2-43
80186 and 8086 Queue Status Generation, 2-29
80186 Baud Rate Generator, 2-64
80186 Bus Drive Capabilities, 2-26
80186 Bus Signals, 2-42
80186 Cascaded Interrupt Acknowledge Timing, 2-75
80186 Chip Select Control Registers, 2-76
80186 Clock Generator Block Diagram, 2-79
80186 Clock Generator Reset, 2-81
80186 CPU/DMA Channel Internal Model, 2-51
80186 Crystal Connection, 2-80
80186 DMA Register Layout, 2-52
80186 Event Counter, 2-65
80186 Generated Signals
ALE, 2-32
RD*,2-32
WR*,2-32
80186 Idle Bus HOLD/HLDA Timing, 2-48
80186 Initial Register State After RESET, 2-81
80186 Interrupt Controller Registers, 2-66
80186 Interrupt Sequencing, 2-67
80186 Interrupt Vector Types, 2-73
80186 IRMX 86 Mode Interface, 2-72
80186 IRMX-86 Mode Interrupt Acknowledge Timing,
2-74
80186 Memory Areas and Chip Selects, 2-75
80186 Non-Cascaded Interrupt Connection, 2-69
80186 Queue Status, 2-28
80186 Real Time Clock, 2-64
80186 Status Line Interpretation, 2-31
80186 Synchronization, 2-46
80186 SYNCHRONIZERS, 2-47
80186 Timer Out Signal, 2-59

80186 WAIT State Programming, 2-78
80186, CLOCKOUT Drive Capacity, 2-24
801861188 Interrupt Vectors, 2-50
80186/80130 IRMX 86 Mode Interface, 2-72
80186/80188 Device Pin Descriptions, 2-20
80186/80188 DIP Pin Assignments, 2-19
80186/80188 Functional Block Diagrams, 2-2
80186/80188 INSTRUCTION SET, 2-6
80186/8258A Interrupt Cascading, 2-70
80186/8288 Bus Controller Interconnection, 2-32
80186/8288/8289· Interconnection, 2-34
80186/Extemal Chip Select/Device, 2-35
8086 (80186)/8087 OPERATION, 3-12
8086 and Coprocessor On the Local Bus, 1-129
8086 Bus, 2-24
8086 Bus Timing -Maximum Mode System, 1-103
8086 Bus Timing -Minimum Mode System, 1-101
8086 Family Multiprocessor System, 1-98
8086 Family Support Circuits, 3-1
8086 Memory, 1-80
8086 Simplified Functional Block Diagram, 1-5
8086 System Configurations, 1-90
8086/80186 Bus Operation Differences, 2-24
8086/8088 Central Processing Units, .1-1
8086/8088 Device Pin Descriptions, 1-61
8086/8088 DIP Pin Assignments, 1-65
8086/8088 Instruction Sequence, 1-109
8086/8088 INSTRUCTION SET, 1-13
8086/8088 MEMORY ACCESS DIFFERENCES, 1-11
8086/8088 Memory Array, 1-83
8086/8088 Memory Organization, 1-82
8086/8088/8089 Multiprocessing System, 1-3
8086/88-80186/188 Operating Mode Comparisons, 2-12
8086/88 Bus Conditioning On Reset, 1-119
8086/88 Clock Waveform, 1-127
8086/88 Instruction Encoding, 1-46
8086/88 Lock Activity, 1-78
8086/88 Maximum Mode System, 1-77
8086/88 Minimum Mode System, 1-77
8086/88 Minimum System, 8257 On System Bus, 1-115
8086/88 Queue Tracking Circuit, 1-78
8086/88 Reset and System Reset, 1-130
8087 BUSY Signal, 3-7
8087 Component, 3-2
8087 Device Pin Descriptions, 3-9
8087 EMULATOR VERSUS COMPONENT USE, 3-2
8087 Instructions
Exponentiation, 3-1
Logrithmic, 3-1
8087 INT, 3-3
8087 Mobility In Any IAPX 86,88, 186 Design, 3-2
8087 NPX -80186/188 CPU System Configuration, 3-12
8087 NPX -8086/88 CPU System Configuration, 3-11
8087 Numeric Co-processor, 1-52
8087 Numeric Data Co-Processor, 2-1
8087 Numeric Data Processor Pin Diagram, 3-3
Index-1

210912-001

INDEX

8087 Numeric Processor Extension Block Diagram, 3-6
8087 Numeric Processor Extention, 3-1
8087 READY Input, 3-16
8087 RQ/GT Function, 3-16
8087/80186(88) Interface, 3-11
8087/8086(88) Interface, 3-11
8088 Simplified Functional Block Diagram, 1-5
8089 DIP Pili Assignments, 4-23
8089 DMA COMMUNICATION PROTOCOL, 4~33
8089 I/O Processor Pinout Diagram, 4-22
8089 Input/Output Processor, 3-2
8089 Instruction Encoding, 4-15
8089 Machine Instruction Decoding Guide, 4-21
8089 NON-DMA INTERRUPTS, 4-33
8089 Simplified Functional Block Diagram, 4-2·
8202 Timing Information, 1-86
8203 Dynamic RAM Interface, 2-38
8203/2164A-15 Access Time Calculation, 2-39
8208 Differentiated Reset Circuit, 2-41
8208 Dynamic RAM Controller Interfaces, 2-40
8208 Dynamic RAM Interface, 2-39
8208 Memory Iilitialization, 2-40
8208 Processor Address Interfaces, 2-40
82188,3-11
82188 Integrated Bus Controller, 3-11
8237A DMA Controller Block Diagram, 1-143
8237A Internal Registers, 1-145
8237A Programmable DMA Controller, 1-125, 1-142
8257-5 DMA Controller, 1-112
.
8259A Interrupt Controller, 1-91
8259A Priority Interrupt Controllers, 1-122
8259A Programmable Interrupt Controller, 1-123, .
1-124, 1-134
82730 CRT Controller, 2-26
8284 With 8086/88 Ready Timing, 1-110
8284A, CPU Clock Drive Capacity, 2-24
8284A Clock Generator and Driver, 1-125
8284A Clock Generator/Driver Block Diagram, 1-127
8284A Frequency Outputs
Oscillator (OSC) , ·1·128
Peripheral Clock (PCLK), 1-128
System Clock (CLK), 1-128
8284A Interfaced to An 8086/88, 1-127
8284A OUTPUTS, 1-128
8284A Reset Circuit, 1-130
8286 Bi-directional Bus Driver, 1-142
8286 Buffer
A Side, 2-29
B Side, 2-29
8288-Generated ALE Pulse, 2-34
8288 Bus Controller, 1-23, 1-38, 1-130,2-24,2-31
8288 Bus Controller Block Diagram, 1-131
8288 Outputs During Passive Modes, 1-119
8289 Bus Arbiter, 1-98, 1-133,4-38
8289 Bus Arbiter Block Diagram, 1-133
8289 Multi-master Bus Arbiter, 1-113
A
AA Field Encoding, 4-21
A.C. Characteristics, 1-98, 1-131
A.C. Characteristics Chip-Select, 2-25

A.C. Characteristics CLKIN Requirements, 2-26
A.C. Characteristics CLKOUT Requirements, 2-26
A.C. Characteristics Master Interface, 2-25
A.C. Characteristics Timing Requirements, 2-24
A.C. Characteristics Timing Requirements, 1-43
A.C. Characteristics Timing Responses, 1-43
A.C. Timing Requirements For Maximum, 1-69
A.C. Timing Requirements For Minimum, 1-67
A. C. Voltage Characteristics, 2-12
Access Time: CS Gated with AD*IWR *, 1-94
Accessing a Stacked Array with Based Index Address,
1-21
Accessing a Structure With Based Addressing, 1-20
Accessing An Array with Indexed Addressing, 1-20
Active Cycle, 1-144
Active States, Seven Possible, 2-31
Active-Inactive Status Transitions, 2-32
ADD Immediate Instruction, 1-109
ADDITIONAL INTERRUPTS, 2-6
Address and Data Bus Concepts, 1-66
Address Bus, 1-64
20-bit, 1-71
Address ENable (AEN*), 1-115
Address Information, 2-23
Address Latch Enable (ALE), 1-93
Address Latches, 2-26
Address Operands, 1-71
Address Spaces
1/0,1-64
Memory, 1-64
Address
16-bit Offset, 1-76
16-bit Segment, 1-76
Physical, 1-8
Addresses
20-bit, 2-1
Even-numbered, 1-11
110, 1-64
I/O Port Operands, 1-17
Logical, 1-8
Memory, 1-17, 1-64
Odd-numbered, 1-11
Physical, 1-8
Addressing
Direct, 1-21
Indirect 110 Port, 1-20
Register Indirect, 1-21 .
Advanced Write Lower TAVWLA, 1-91
Advanced Write Signal, 1-83
AL Register, 1-66, 1-85, 2-7
ALE,3-16
ALU, 2-1
Applications, 16-bit, 1-46
Arbitration Circuit, 1-118
Arbitration Devices
Bus Controlled, 2-33
Multi-master Bus, 2-34
Arbitration Techniques, 1-98
Architecture Overview, 1-2, 2-1, 3~3, 4-l
ARDY, 3-12, 3-16

Index-2

210912"()01

INDEX

Arithmetic Instructions, 1-14,2-8,4-4
Arithmetic Interpretation of8-Bit Numbers, 1-14,2-9
ARITHMETIC/LOGIC UNIT (ALU), 4-1
Arithmetic Shifts, 1-14
Array Bounds (BOUND) Instruction, 2-6
Array Elements, 1-20
Array
Matrices, 1-20
Structures, 1-20
ASM-86 Assembler, 3-22
Assembler, 8086/80186, 2-5
Assembly Code Instruction, 1-12
ASSEMBLY/DISASSEMBLY REGISTERS, 4-1
Asynchronous Bus Interface, 1-88
Asynchronous Handshake, 2-12
Asynchronous Ready Circuits For the 80186, 2-46
Asynchronous Ready Synchronization Circuits, 2-39
Automatic EO! Mode, 1-139
Automatic Initialization, 2-36
Automatic Rotation - Equal Priority, 1-139
Auxilary Flag (AF), 1-6
AX Register, 1-86
B
Bank Select Input BS, 2-49
Bank Selection Decoding and Word Expansion, 2-49
Base Address, Current Code Segment, 2-9
Base Address and Base Word Count Registers, 1-146
Base Point Register (BP), 1-9
Base Register Sum, 1-18
Base Register Content, 1-16
Based Addressing, 1-18
Based Index Addressing, 1-19, 1-20
Based Variable Operations, 2-8
Basic 8086/88 Bus Cycles, 1-80
Basic 8086/88 Instruction Set, 2-5
Baud Rate Counter Values (16X), 5-11
Baud Rate Generators, 2-58, 5-11
BHE*/S7 Line, 3-3
Bi-directional Buffer, 2-30
Binary Numbers
Divide, 1-14,2-9
Division, 1-13
Multiplication, 1-13
Multiply, 1-14, 2-9
Signed, 1-13
Unsigned, H3
Bipolar PROM Decoder, 1-88
Bit Manipulation Instructions, 1-14,2-9
Logicals, 1-14
Rotates, 1-14
Shifts, 1-14
Block Input/Output (INS/OUTS) Instructions, 2-5
Block Transfer Mode, 1-144
Block Transfer to 16-bit lIO Using, 1-92
Block Transfer to 8-bit I/O Using, 1-92
Boolean Operators
"and", 1-14
"inclusive Or", 1-14
"not", 1-14
Boundaries

16-byte, 1-70
Even Address, 1-70
Odd Address, 1-70
Bounds
Lower, 2-6
Upper, 2-6
Buffered Data Bus, 1-93
Buffered Devices, 2-30
Buffered Mode, 1-142
Buffering Devices with OE*/RD*, 1-97
Buffering Devices Without OE*/RD* And, 1-97, 1-98
Buffering the 8284 CLK Output, 1-129
Bus Access Control, 1-64
Bus Access Request, 2-1
BUS ACTIVITY DURING a HARDWARE
INTERRUPT, 1-124
BUS ARBITRATION, 3-16, 4-37
BUS ARBITRATION FOR lOP CONFIGURATIONS,
4-39
Bus Arbitration Requirements and Options, 4-39
Bus Contention, 1-96, 2-26
Bus Control and Command Outputs, 1-60
BUS CONTROL SIGNALS, 2-25, 3-16
Bus Cycle Decoding, 4-37
Bus Cycle Definition, 1-65
Bus Cycle, 2-36
Asynchronous Event, 1-65
Minimum, 1-65
Bus Cycle T2, 2-23
BUS DRIVE, 2-30
BUS EXCHANGE MECHANISMS, 1-110,2-54,3-16,
4-36
BUS INTERFACE UNIT, 1-3, H08, 1-110,2-5
Bus Interface Unit (BID), 2-1, 4-2
Bus Interface
16-bit, 2-1, 2-5
Bus Load Limit, 4-39
Bus Lock, 4-39
Bus Master Peripheral Devices, 2-25
Bus Master Type Controllers, 1-60
Bus Masters, 1-110
Bus Mastership, 2-25
BUS OPERATION, 1-64,2-24,3-15,4-34
Bus Parity Detection Logic, 1-120
Bus Request Line (BREQ*), 1-135
Bus Time Percentage, 2-24
Bus Transceiver Control, 1-95
Bus Usage Amount, 2-24
Bus
Address, 1-65
Command,I-65
Data, 1-65
Status, 1-65
Time-multiplexed, 1-64
Twenty-bit Time Multiplexed, 1-65
Business Data Processing, 3-1
BUSY Signal, 3-8
Byte Data, 2-7
Byte Units, 2-3

C
Index-3

210912-001

INDEX

Carry Flag (CF), 1-6, 1-14
Cascade and Special Fully Nested Mode Interface, 2-69
Cascade Input Mode, 2-69
Cascade Mode, 1-141, 1-144
Cascade-Buffered Mode Example, 1-143
Cascaded 8237As, 1-145
Cascaded 8259A's 22 Interrupt Levels, 1-141
CE to WR* Setup and Hole, 1-94
Channel Attention Decoding Circuit, 4-28
Channel Command Word Encoding, 4-28
Channel Commands, 4-27, 4-29
Channel Transfer Delay Timing, 1-117
Channel Register Set, 4-3
Channel Register Summary, 4-2
Channel State Save Area, 4-30
CHANNELS, 4-3
Chip Enable/select, 1-68
Chip Enable/select Encoding, 1-68
CHIP SELECT AND READY GENERATION UNIT,
2-1
Chip Select Decoding, 1-64
Chip Select Generation For Devices Without Output,
1-83
Chip Select, 1-97
Active, 1-64
High Active, 1-64
Low Active, 1-64
Signals, 2-30, 2-31
Chip Select/Ready Logic and Reset, 2-81
Chip Select/Wait State Generation Unit, 2-74
Chip Selection For Devices With Output Enables, 1-84
Circuit Holding LOCK* Active Until, 2-33
Circuit to Translate HOLD Into AEN Disable, 1-118
Classes ofInterrupts, 1-120
Clear First/Last Flip/Flop, 1-148
CLOCK GENERATION, 1-125
CLOCK GENERATOR, 2-3
Clock Generator/Reset/Ready, 2-79
Clock High Phase, 2-24
Clock In/Clock Out Timing, 2-79
Code For Block Transfers, 1-63
Column Address Strobe (CAS*) Pair, 2-49
Coming Out of Reset, 2-81
Command Activation, 1-65
Command Communication Blocks, 4-24
Command Inputs, 1-64
Command Lines
1/0, 1-65
Memory, 1-65
Command Signals
Ready, 2-31
Write, 2-31
Command Register, 1-146, 1-147
Commands
Interrupt Acknowledge, 1-65
Read, 1-64, 1-65
Write, 1-64, 1-65
COMMON CONTROL UNIT (CCU), 4-1
Common IAPX186 System Components, 2-4
Common Word Address, 2-33

Communication Chips, 1-2
COMPATIBILITY WITH FRSTOR, 3-19
COMPATIBILITY WITH FSAVE/FNSAVE, 3-19
Compatible Peripherals For a 5 MHz 8086188, 1-90
COMPONENT OVERVIEW, 1-1,2-1,3-3,4-1
Concurrent Execution of Host and Coprocessor, 3-13
Condition of 8086/88 Bus and Output Signal, 1-119
Conditional Jumps SHORT, 2-10
Conditional Transfers, 1-16, 2-10
Constant Current Power Up Reset Circuit, 1-130
CONTROL REGISTERS, 2-67, 2-68
CONTROL SIGNALS, 2-29
ALE*,2-32
DEN, 2-33

DT/R*,2-33
LOCK*,2-33
RD*, 2-29, 2-32
TEST"', 2-33
WR*, 2-29, 2-32
CONTROL UNIT, 3-3
Controlling System Transceivers with DEN and DT/R"',
1-97
Count Register (CX), 1-14
COPROCESSOR CONTROL, 3-13
COPROCESSOR INTERFACE TO MEMORY, 3-12
Count Operand Value, 2-8
CPU Bus Bandwidth, 1-106
CPU Clock, 1-98,2-3
50% Duty Cycle, 2-24
Duty Cycle, 2-3
Speed, 2-3
CPU DUTY CYCLE AND CLOCK GENERATOR,
2-24
CPU ENHANCEMENTS, 2-4
CPU Execution Speed, 2-4
CPU Local Bus, 1-88, 1-131
CPU Not Ready, 1-66
CPU Processing Sections, 2-1
CPU WAIT Instruction, 3-7
CPU/lOP Communications, 4-22
Crystal Choice Recomendations, 2-80
CRYSTAL CLOCK REFERENCE, 1-126, 2-79
Crystal Oscillator, 2-25
CS Register, 1-123, 1-124
CS*/Bus Driving Device Timing, 1-95
CSYNC Setup and Hold to EPI, 1-116
Current Address Register, 1-145
Current Code Segment, 1-5
Current Extra Segment, 1-5
Current Word Register, 1-145
Currently Addressable Segments, 1-8, 1-9
CX Register, 2-10
Cycle Dependent Write Parameters For RAM Memories,
1-84
D
D-type Latches, 1-94
D.C. Characteristics, 1-66,2-23
Data Access Period, 2-39
Data Acquistion, 3-2
Data Buffers, 2-29
Index-4

210912-001

INDEX

Data Bus Interface, 8-bit, 2-1, 2-4
Data Bus Usage, 4-37
Data Bus
16-bit, 1-66, 1-67, 1-85, 1-86, 1-123,2-1,2-34
8-bit, 2-1
Arithmetic Logic Unit (ALU), 1-3,2-1
DO-D7,2-34
D8-DI6,2-34
Lower 8 Bits, 2-34
Lower Half, 1-86
Lower Half (D7-0), 1-67
Multiplexed Address/data, 2-34
Upper 8 Bits, 2-34
Upper Half, 1-86
Upper Half (DI5-8), 1-67
Data Byte, 1-13
Data Element
16-bit, 1-67
Eight Bit, 1-67
Data Hold Time, 1-106
Data Operands, 1-76
Data Path, 16-bit, 1-46
Data Paths
16-bit External, 1-65
16-bit Internal, 1-65
Data Propagation Direction, 2-29
Data Registers
16-bit, 1-4
Lower Half, 1-4
Two 8-bit, 1-4
Upper (high) Half, 1-4
Data Strobe, 1-66
Data Throughput, 1-142
Data Tranceivers, 1-117
Data Transfer, 2-34
Data Transfer Instructions, 1-13, 1-14,4-4
Address Object, 1-13, 2-7
Flag Transfer, 1-13, 2-7
General Purpose, 1-13, 2-7
Input/output, 1-13,2-7
Data Transfers
16-bit, 1-86
8-bit, 1-86
Data Transmit/Receive (DT/R*), 1-93
Data Word, 1-12
Data Types, 5-8
Decimal Operands, 3-1
Decoding Escape Instructions, 3-12
Delay Effects of the 8087, 3-17
Delay of Valid Address, 1-99
De-multiplexing Address and Data From the Processor
Bus, 1-96
Demultiplexing the 80186 Address Bus, 2-44
DEN*, 3-16
Decoding Memory and I/O RD* and WR * Commands,
1-79
Definition of Register Codes, 1-147
Demand Transfer Mode, 1-144
Demultiplexed Address Bus, 1-96, 1-99
Demultiplexed Buffered System Bus, 1-105

Destination Index, 1-15
Destination Synchronized DMA Transfers, 2-56
Destination Synchronized Transfer Cycle, 4-32
Device Architecture, 801861188, 2-1
Device Assignment, 1-91
Device Output Drivers, 1-92
DEVICE PIN ASSIGNMENTS, 3-8, 4-20, 5-1
DEVICE PIN DEFINITIONS, 1-42,2-12
Device Pin Signal, 1-43,2-12
Device Reliability, 1-43,2-12
Device Specifications, 1-43,2-12
Devices, 8MHz, 2-1
Devices With Output Enable On the Multiplexed Bus,
1-93
Devices With Output Enable On the System Bus, 1-95
Devices Without Output Enable On the Multiplexed B,
1-94
Differences Between 80130 and 8259A, 5-8
Differences Between 80130 Timers and 8253/8254, 5-11
Differences, 80186 and 80188, 2-1
Direct Addressing, 1-18, 1-19
Direct Input Mode, 2-68
Direct Memory Access (DMA) Unit, 2-51
Direct Memory Access Transfers, 4-30
Direction Controls, 1-99
Direction Flag (DF), 1-7, 1-15
Discrete Data Buffer, 2-36
Displacement Summing, 1-18
Displacement Value Sum, 1-18
Divide Error -Type 0, 1-121
Divide Error Interrupt Service Routine, 1-121
DMA ACKNOWLEDGE, 2-54
DMA Acknowledge Synthesis, 2-55
DMA Assembly Register Operation, 4-31
DMA Channels and Reset, 2-82
DMA Control Register, 2-51
DMA Cycle, 2-3, 2-4
DMA Latency Time, 2-24
DMA OPERATION, 1-142
DMA REGISTERS, 1-145
DMA Request Inactive Timing, 2-57
DMA Request Logic, 2-55
DMA Request Timing, 2-55
DMA REQUEST TIMING AND LATENCY, 2-54
DMA Requests, 2-4, 2-53
DMA Termination, 4-32
DMA Transfer, 2-24
DMA TRANSFERS, 2-52
DMA Transfer Cycles, 4-32
DMA Unit, 2-24
DMA Using the 8237-2, 1-114
DRAM Controller
8203,2-31
8207,2-31
DS Register, 1-18
DT/R*, 3-16
Dynamic Code Relocation, 1-11
Dynamic RAM, 1-81
Dynamic RAM Controllers
8202, 1-81

Index-5

210912-001

INDEX

8203, 1-81
8207, 1-81
8208, 1-81
Dynamic Reconfiguration, 1-142
DYNAMICALLY RELOCATABLE CODE, 1-10
Dynamically Relocatable Program, 1-10
E
Edge Sensitive Input, 1-140
Edge Triggered Mode, 1-140,5-12
Effective Address Calculation Time, 1-24
EFI From 8284A Oscillator, 1-129
Eight Bit Data Element, 1-67
Eight Levels of Interrupts, 1-134
Eight-Bit I/O, 1-86
Electrical Description of Pins, 1-43,2-12
Element
Byte, 2-9
Word,2-9
Elementary Maximum Mode System, 1-76
End of HOLD Timing, 2-48
End of HOLD Timing Diagram, 2-49
End ofInterrupt (EOI), 1-139
End-OF-Interrupt Formats, 1-139
EOI Formats, 1-139
ENTER and LEAVE Instructions, 2-6
ENTER Instruction Algorithm, 2-6
ENTER Instruction Stack Frame, 2-7
EPROM/ROM Bus Interface, 1-83
EPROM/ROM Parameters, 1-82
ES Register, 1-18
ESCAPE Instruction, 3-7, 3-8
ESCAPE INSTRUCTION FORMAT, 3-7
ESCAPE Instructions Not Used By the 8087 NPX, 3-8
Escape Opcode, 2-6
EU,2-1
EU Bus Request, 1-4
Even Word Boundaries, 1-109
Event Counter, 2-59
Example 2186/80186 Interface, 2-37
Example 2764/80186 Interface, 2-35
Example 80186 Buffered/Unbuffered Data Bus, 2-30
Example 80186 Bus Cycle, 2-43
Example 8203/DRAM/80186 Interface, 2-38
Example DMA Transfer Cycle, 2-53
Example Interrupt Controller Interface Code, 2-71
Example Timer Interface Code (Sheet 1 of 4), 2-60
Execution Speed Improvements, 2-4
EXECUTION UNIT, 1-3,2-23
EXECUTION UNIT AND BUS INTERFACE UNIT, 2-1
External Bus
16-bit 80186, 2-1
8-bit 80188, 2-1
External Clock Generator, 2-24
External DMA Controller, 2-35
EXTERNAL FREQUENCY CLOCK
REFERENCE, 1-126,2-80
External Frequency For Multiple 8284's, 1-128
External Frequency Source, 1-125
EXTERNAL INTERFACE, 2-68
External Interrupt Controller, 2-19

External Interrupt Sources, 2-66
External Oscillator, 2-3
External Ready Signals, 2-3
External Refresh Requests After RESET, 2-41
External Synchronization Instructions, 2-11
External Vectoring, 2-74
EXTERNALLY SYNCHRONIZED DMA
TRANSFERS, 2-54
Extra Segment, 1-8

F
F/C* Strapping Option, 1-128
Faster Effective Address Calculation, 2-4
FDIV, 3-14
Field
D, 1-41
Immediate, 1-41
MOD (mode), 1-41
Optional, 1-41
R/M (register/memory), 1-41
REG, 1-41
REG (register), 1-41
S, 1-41
Single-bit, 1-41
V, 1-41
W,1-41
Z, 1-41
Financial Calculations, 3-1
Flag Operations, 2-11
Flag Store Formats, 2-8
Flag Storage Formats, 1-13
FLAGS, 1-5
Flags Register, 1-123, 1-124
Flags
Control, 1-3
Status, 1-3
Updates, 1-17
FMUL,3-14
FSQRT,3-14
Full Machine Cycle Execution, 1-144
Fully Buffered System, 1-96
Fully Nested Mode, 1-136
Functional Description of All Signals, 1-43,2-12
FWAIT,3-14
G
General Design Considerations, 1-64
GENERAL INFORMATION, 5-1
GENERAL REGISTERS, 1-7
Generating I/O and Memory Read Signals, 2-30
Generating Queue Status Information, 2-28
Graphics Terminals, 3-2
H
HALT,2-24
HALT Bus Cycle, 2-23
Hardware Chip Select Signals, 2-34
Hardware-initiated Interrupts, 2-11
HARDWARE LOCK, 1-52
Hardware-initiated Interrupts, 1-17
Hardware Trigonometric Support, 3-2
High-Level Instructions, 2-11

Index-6

210912-001

INDEX

High-level Languages, 2-11
High-Speed Address Decoding Circuit, 5-15
High Address, 1-7
Higher Priority Arbiter Obtaining the Bus, 1-135
HOLD Response, 2-47
HOLD/HLDA, 3-11
HOLD/HLDA INTERFACE TO MAXIMUM MODE
SYSTEMS, 1-115
HOLD/HLDA Sequence Timing Diagram, 1-112
HOLD/HLDA Timing, 1-98,2-48
HOLD/HLDA Timing and Bus Latency, 2-47
HOLD/HLDA-to/from-RQ*/GT* Conversion Circuit,
1-116
HOLD/HLDA-to/from-RQ*/GT* Conversion Timing,
1-116
HOLD/HLDA VERSUS RQ*/GT*, 2-26
HOST ESCAPE INSTRUCTION PROCESSING, 3-12
Host TEST Pin, 3-8
Hosts Interrupt Vector Table, 3-2
I
110 Address Space, 1-64
110 BUS MODE, 1-133
110 Control, 4-3
110 Device Chip Select Techniques, 1-88
110 DEVICE COMPATIBILITY, 1-88
110 Devices
16-bit, 1-88
8-bit, 1-86
110 Input Request Code Example, 1-92
110 Interfacing, 1-69
I/O Modules, 1-64
110 Peripheral Address, 1-64
110 PERIPHERAL INTERFACE, 1-85
I/O Port Addressing, 1-20, 1-21
I/O Port
Access, 1-21
Memory Mapped, 1-20
110 Read, 1-4
110 Space, 2-3, 2-4
64K-byte, 1-46
I/O Write, 1-4
1I0-intensive Data Processing Systems, 1-1
I/O-to-memory DMA Transfers, 1-143
IAPX 186/10 Microprocessors, 3-1
IAPX 188/10 Microprocessors, 3-1
IAPX186 Integrated Devices, 3-1
IAPX 86,88, 186, 188 Base, 3-1
IAPX 86/10 Microprocessors, 3-1
IAPX 86/11, 88/11 Configuration with 8089 In Local,
4-25
IAPX 86/20,88/20 SYSTEM CONFIGURATION, 3-17
IAPX 86121,88121 SYSTEM CONFIGURATION, 3-17
IAPX 86/22 System, 3-20
IAPX 86/22,88/22 SYSTEM CONFIGURATION, 3-17
IAPX 88/10 Microprocessors, 3-1
IAPX 88/21 System Configuration, 3-18
IAPX186/20 Bus Operation, 3-15
IAPX186/20 System, 3-11
IAPX86/20 Bus Operation, 3-15
Idle Cycle, 1-142

Idle Cycles (Tl), 1-66
Idle Status, 1-115
Idle T States (Ti), 2-19
IF Flag, 1-122
Immediate Operand, 8-bit Port Number, 1-21
Immediate Operands, Limitations, 1-18
Implicit Use of General Registers, 1-7
IMUL,2-5
In-Service Register (ISR), 1-137
Index Register, Content, 1-18
Inertial Guidance Systems, 3-2
Indexed Addressing, 1-19, 1-20
Inhibit/Enable 8087 Interrupts, 3-23
Initialization Command Word 1 (ICW1), 5-2
Initialization Command Word 2 (lCW2), 5-3
Initialization Command Word 3 (ICW3, 5-3
Initialization Command Word 4 (ICW4), 5-5
Initialization Command Word 5 (ICW5), 5-5
Initialization Command Word 6 (ICW6), 5-5
Initial Program Loading Routine, 1-76
Initializing the Timers, 5-11
Initialization and Processor Reset, 2-81
Input/output Memory Devices, 2-1
INPUT/OUTPUT PERIPHERAL CHIP SELECTS, 2-78
Input/output Peripheral Devices, 2-1
Input Request, 1-92
Instruction Execution, 2-23
Immediate-to-memory, 1-21
Register-to-register, 1-21
Instruction Execution Times, 2-4
Instruction Fetch Bus Cycle, 1-2,2-3
Instruction Fetch Overlap, 1-2
Instruction Fetch Timings (Clock Periods), 4-15
INSTRUCTION FETCH UNIT, 4-2
Instruction Loop Sequence, 1-111
Instruction Object Code Byte, 2-1
INSTRUCTION POINTER, 1-5,2-1,2-9
Instruction Queue
4-byte, 1-2
6-byte, 1-2
Instruction Set Extension, 1-98
Instruction Set Reference Data, 1-21, 1-24, 4-6
Instruction Set Summary, 1-13, 1-21,2-12,2-13,4-3
Instruction Set
80186/88,2-1
Assembly Level, 1-13
Machine Level, 1-13
Two Levels, 1-13,2-7
Instruction Synchronization, 3-13
Instruction/function Format, 1-1
Instructions
80186,2-23
Actual Execution Time, 1-23
ADD Immediate, 1-109
ADD Memory Indirect to AX, 1-109
Address Object, 2-7
Arithmetic, 2-7, 2-8
ASM-86, 1-42
Assembly-level, 2-7
Auto-decrement, 1-7

Index-7

210912-001

INDEX

Bit Manipulation, 2-7, 2-8
BOUND, 2-6
CALL, 1-18
Clock Cycles, 2-12
CLI, 1-122
Conditional, 1-16
Conditional Repeat, 1-41
Conditional Transfer, 1-16,2-10
Control Transfer, 1-23,2-7
Data, 1-64
Data Move, 2-23
Data Transfer, 2-7
Displacement, 1-18
Divide, 2-4
ENTER, 2-6
ENTER, 2-6
ESCAPE, 1-52
Fetch, 1-65
FWAIT,2-33
HALT, 1-64, 1-107
High Level, 2-7
HLT,2-23
Immediate-to-memory, 1-41
IMUL,2-5
INC, 1-13
INS, 2-5
INT Nn, 1-122
Interrupt, 1-17, 2-11
Interrupt On Overflow, 1-6
Interrupt-related, 1-16
INTO, 1-121
IRET, 1-122
Iteration Control, 1-17,2-10
JC, 1-15,2-9
JMP, 1-18
JMP, 1-109, 1-118
JNC, 1-15,2-9
LAHF,2-7
LDS,I-15
LEA, 1-15
LEAVE, 2-6
LES,I-15
LOCK* Prefix, 1-52
LOCKED, 2-33
Locked, 1-64
Locked Exchange, 1-64
Logical, 1-14,2-8
Long, 2-23
Machine Level, 1-13,2-7
Master Clear, 1-146
MOV, 1-13, 1-41, 1-109, 1-122
MOV Immediate, 1-109,2-9
MOVS,I-122
Multibyte, 1-41
Multiple-bit Shift, 2-4
Multiply, 2-4
Non-immediate 16-bit Read/write, 2-1
OUTS, 2-5
POP, 1-122
POPA,2-5

Prefetched, 1-3, 1-23,2-1,2-23
Process Control, 1-17
Processor Control, 2-7, 2-11
Program Transfer, 2-9
PUSH AX, 1-109
PUSHA,2-7
PUSHI,2-7
Queue, 1-24
Reset, 1-146
RET, 2-6
Rotate, 1-14,2-4,2-9
Shift, 2-9
Shift/rotate, 2-5
Short, 2-23
String, 1-15,2-9
String Manipulation, 2-7
String Move, 2-4, 2-5
Target, 1-23
TEST, 1-14,2-8
Timing Cycles, 1-12,2-12
Unconditional, 1-16
Unconditional Transfer, 1-16,2-10
WAIT, 1-64, 1-105, 1-122,2-33
INTO/INTI Control Register Formats, 2-66
INT2/INT3 Control Register Format, 2-67
Integer Immediate Multiply (IMUL), 2-5
Integrated Circuits, 80186/188,2-3
Integrated DMA Unit, 2-3, 2-26
Integrated Wait State Generator, 2-4
Intel Hardware Products, 1-11
Intel Software Products, 1-11
Intellec Microcomputer Development System, 1-2
Interfacing the 8089 to the 8086 and 80186, 4-24
INTERFACING WITH THE 8086/88,5-1
Internal 256-byte Control Block, 2-4
Internal Architecture, 16-bit, 2-1, 2-4
Internal CPU Registers, 1-118
Internal Data Path, 1-65
Internal Interrupt Sources, 2-65
INTERNAL PERIPHERAL INTERFACE, 2-4
Internal Pre-fetch Queue, 2-12
Internal Source Priority Level, 2-65
Internal Vectoring
IRMX 86 Mode, 2-73
Master Mode, 2-73
Interpolation, 3-2
Interpretation of Conditional Transfers, 1-17, 2-11
Interpreting the 80186/80188 Bus Timing Diagrams,
2-41
Interpreting the 8086/8088 Bus Timing Diagrams, 1-98
Interrupt Acknowledge, 1-104, 1-123
Bus Cycle, 1-17,2-11
Cycle, 1-118
Sequence, 1-112, 1-122, 1-123
Timing, 1-123
Timing Cycles, 1-104
INTERRUPT CASCADING, 1-140
Interrupt Classes, 1-120
Interrupt Controller, 2-59, 5-10
Interrupt Controller and Reset, 2-82
Index-8

210912-001

INDEX

Interrupt Controller Block Diagram, 2-65
Interrupt Controller Control Register, 2-68
Interrupt Controller Operating Modes, 2-19
Interrupt Controller Pins, 2-19
Interrupt Controller Registers, 2-3
Interrupt Enable Flip-flop, 2-26
Interrupt Instructions, 1-17, 2-11, 3-2
Interrupt Latency, 2-70
Interrupt On Overflow -Type 4, 1-121
INTERRUPT PRECEDENCE, 1-124
INTERRUPT PRIORITIES, 1-136
Interrupt Processing, 1-11, 1-76
Interrupt Processing Timing, 1-121
Interrupt Request Register (lRR), 1-137
Interrupt Requests
External (maskable), 1-7
External Sources, 2-3
Internal Sources, 2-3
INTERRUPT RESPONSE TIMING, 2-73
Interrupt Service Routine, 1-120, 1-124
Interrupt Sequence, 5-13
INTERRUPT SOURCES, 2-65
Interrupt-related Transfers, 2-9
INTERRUPT TRIGGERING, 1-140
INTERRUPT TYPE PROCESSING, 1-124
Interrupt Types, 1-120
256 Possible, 1-76
Interrupt Vector Byte, 1-139
Interrupt Vector Table, 1-120
INTERRUPT VECTORING, 1-135
Interrupt Vectors, 1-64, 3-2
Interrupt-enable Flag (IF), 1-7
Interrupt-related Instructions, 1-16
INTERRUPTS, 1-120, 3-22, 4-40
CPU, 1-120
Escape Opcode, 2-6
Hardware, 1-120
Hardware-initiated, 1-17, 2-11
Internal, 1-7
Internally Generated, 1-7
Maskable, 1-120
Non-maskable External, 1-7
Nonmaskable, 1-120
Response, 1-11
Single-step, 1-120
Software, 1-17, 1-120,2-11
Software-initiated, 1-120
Unused Opcode, 2-6
Intersegment Transfer
FAR, 1-16
Intrasegment Transfer
NEAR, 1-16
SHORT, 1-16,2-5
lOP Initialization, 4-26
IR Level, 1-139
IR Triggering Timing Requirements, 1-141
IRMX 86 Interrupt Controller Interconnection, 2-66
IRMX 86 Mode, 2-19
IRMX 86 MODE OPERATION, 2-64
IRMX Mode, 2-70

IRMX Mode Sources, 2-68
ISBC 337 MULTIMODULE, 3-3
ISBC 337 MULTIMODULE Mounting Scheme, 3-3
ISBC 86/30 Board, 1-24
ISBC 88/25 Board, 1-24
Iteration Control, 1-17, 2-10

J
JMP Instruction, 1-109
K
Key to Flag Effects, 1-23
Key to Instruction Coding Formats, 1-22
Key to Machine Instruction Encoding, 1-45
Key to Operand Types, 1-23
L
Language Translators, 1-42
Late Write Signal, 2-27
LATENCY OF HLDA TO HOLD, 1-112
Level Triggered Mode, 1-91, 1-140,5-12
Linear Select For 110, 1-79
LINK86 Program, 3-2
LMCS Programming Values, 2-77
LMCS Register, 2-77
Local Bus, 8086, 1-52
LOCAL BUS CONTROLLER AND CONTROL
SIGNALS, 2-25
Local Bus Controller and Reset, 2-81
Local Bus Controller Outputs, 2-12
Local Interrupt Requests, 5-13
LOCAL Mode, 3-11, 4-25
LOCK*,1-98
Locked Data Transfer, 2-33
Locked Exchange Instruction, 1-64
Logical, 1-14, 2-8
Lower 8 Data Bits, 2-4
Logical Addresses, 1-8
Logical Addresses Sources, 1-10
Logical and Bit Manipulation Instructions, 4-4
Logical and Physical Addresses, 1-9
Lower Bank Write Strobe, 1-81
Lower Bounds, 2-6
Lower Memory CS*, 2-76
Lower Memory For Interrupt Vectors, 2-3
Lower Memory Starting Location, 2-3
Lowest-addressed Byte, 1-8
M
Machine Instruction Decoding Guide, 1-52
MACHINE INSTRUCTION ENCODING AND
DECODING, 1-24,4-6
Machine Instruction Encoding Matrix, 1-44
Machine Instruction Formats, 1-24
8086, 1-41
8086/8088, 1-42
8088, 1-41
Decode, 1-12
Encode, 1-12
Length, 1-41
MOV,2-7
Machine Language
Instruction Decoding, 1-21
Instruction Encoding, 1-21
Index-9

210912-001

INDEX

Major Cycle Timing Waveforms, 2-12, 2-27
M~or Modes of Operation, 2-19
Mask Bits, 1-148
Mask Register, 1-147, 1-148
Master Clear, 1-148
Master System Interrupt Controller, 2-19
External, 2-3
Max Mode 8086 with Master 8259A 1-107, 1-138
Maximum and Minimum Mode Command Timing,
1-132
Maximum CPU Bus Bandwidth, 1-107
Maximum Mode (RQ*/GT*), 1-113
Maximum Mode Address and ALE Timing, 1-105
MAXIMUM MODE BUS TIMING, 1-105
Maximum Mode Interrupt Acknowledge Timing, 1-106
Maximum Mode Operation Waveforms, 1-43
Maximum Mode Read Cycle Timing, 1-105
Maximum Mode Ready Timing, 1-106
MAXIMUM MODE SYSTEM INTERRUPT, 1-124
Maximum Mode System Overview/Description, 1-52
Maximum Mode System Bus, 2-12
Maximum Mode Values, 1-105
Maximum Mode Waveforms, 1-74
Maximum Mode Write Cycle Timing, 1-106
Maximum Parameter Values, 1-98
Maximum Write Data Delay, 1-99
MCE Timing to Gate 8259A CAS Address, 1-138
Memory -I/O Block Transfers Example, 1-91
Memory Address Computation, 1-19
Memory Address Space, 1-64
Memory Address, Odd, 1-23
Memory Addressing Modes, 1-18
Memory and 110 Peripherals Interface, 1-71, 2-34
Memory Chip Select Lines, 2-3
MEMORY CHIP SELECTS, 2-75
Memory Components, 1-8
Memory Device, 1-42,2-3
Memory Even and Odd Data Byte Transfers, 1-81
Memory Even and Odd Data Word Transfers, 1-82
MEMORY INTERFACE, 1-78,2-34
Memory Interfacing, 1-71
Memory Mapped, 1-64,2-3
Memory Mapped 8-bit I/O, 1-87
Memory Mode, Effective Address Calculation, 1-41
Memory Modules, 1-64
Memory Operands, 1-17, 2-7
Displacement Value, 1-41
Read, 1-18
Register Indirect Addressing, 1-21
Write, 1-18
Memory Organization, 2-4
Memory Read, 1-4
Memory Read Signals, 1-105
Memory Reference Escape Instruction Form, 3-8
Memory Reference Opcodes, 3-7
Memory Space, 2-3
8086, 1-5
8086/8088, 1-8
8088, 1-5

Memory Writes, 1-11,2-31
Memory
High, 1-11
Low, 1-11
Memory-based Semaphore Variables, 2-33
Memory-To-Memory Transfer Timing, 1-145
Memory-to-Memory Transfers, 1-142, 1-145, 1-148
Microprocessor Control Pins, 1-1
Microprocessors
80186,2-1
80188,2-1
8080/8085, 1-12
Mid-Range CS*, 2-76
Min Mode 8086 with Master 8259A, 1-137
Minimum Execution Time, 2-12
Minimum Mode, 1-1
Minimum Mode (HOLD/HLDA), 1-110
Minimum Mode 8086 Systems, 1-134
MINIMUM MODE BUS TIMING, 1-99
MINIMUM MODE DMA CONFIGURATION, 1-112
Minimum Mode Interrupt Acknowledge Timing, 1-104
Minimum Mode Operation Waveforms, 1-43
Minimum Mode Read Cycle Timing, 1-99
Minimum Mode Ready Timing, 1-104
MINIMUM MODE SYSTEM INTERRUPT, 1-124
Minimum Mode System Overview/Description, 1-44
Minimum Mode TEST* Timing, 1-105
Minimum Mode Waveforms, 1-72
Minimum Mode Write Cycle Timing, 1-104
Minimum Parameter Values, 1-98
Minimum/Maximum Mode Pin Assignments, 1-71
MM Field Encoding, 4-22
MMCS Register, 2-78
MN/MX* Input Pin, 1-43
MN/MX* Pin, 1-7
Mnemonic Codes For Exceptions, 5-9
MOD Field, 3-7
Mode (MOD) Field Encoding, 1-42
Mode Register, 1-146, 1-147
MODE SELECTION, 1-7
Mode
Addressing, 1-20
Single-step, 1-7
Modes of Operation
IRMX 86, 2-19
Non-iRMX 86, 2-19
Modes
Late Cycle, 2-36
Pulse, 2-36
Most-significant Byte, 1-41
Move Word Immediate to Register, 2-7
MOVS Instruction, 1-122
MPCS Programming Values, 2-77
MPCS Register, 2-77
Multi-CPU System Performance, 1-131
Multi-master Bus Arbitration, 1-119
Multi-master Bus System, 1-134, 2-34
MULTIBUS APPLICATIONS, 2-33
MULTIBUS Protocol, 1-98
Index-10

210912-001

INDEX

MULTIBUS System Bus, 1-97, 1-107
MULTIBUS Systems, 1-131
Multibyte Numbers
Add, 1-6
Subtract, 1-6
Multiple Bit Rotates, 2-5
Multiple Bit Shifts, 2-5
Multiple Communications Lines Example, 1-91
Multiple Processor Considerations, 1-119
Multiple-processor Designs, 1-1
Multiplexed Address and Data Bus, 1-64, 1-96, 1-104
Multiplexed AddresslData Bus, 2-34, 2-36
Multiplexed AddresslData Bus (186/188), 2-29
Multiplexed Address/Status Lines, 1-104
Multiplexed Bus, 1-79, 1-92
Multiplexed Bus With Local Address Demultiplexing,
1-96
Multiplexed Data Bus, 1-93
Multiprocessing Functions, 1-44
Multiprocessor Environments, 1-131
Multiprocessor/Coprocessor Applications, 1-97
N
Navigation, 3-2
NEW 80186/80188 INSTRUCTIONS, 2-4
New Instructions, 2-1
NMI ACKNOWLEDGE, 1-124
NMI During Single Stepping and Normal, 1-125
NMI, INTR, Single Step and Divide Error, 1-125
Non-existant Banks, 2-39
Non-immediate Data Read/write Instruction, 2-4
Non-integral Values, 3-1
NON-iRMX 80 MODE, 2-64
Non-iRMX 86 Mode, 2-19
Non-Maskable Interrupt -Type 2, 1-121
Non-memory Reference, 3-7
Non-Memory Reference Escape Instruction Form, 3-7
Non-Specific EO! Command, 1-139
NOP Instruction, 3-3
Normal Bus Cycle, 2-23
Normally Not Ready System Avoiding a Wait State,
1-108
Normally Ready System Inserting a Wait State, 1-108
NPX, 3-lNPX Coprocessor Application, 3-1
NP~CLEAN Code Example, 3-22
Numeric Control, 3-2
NUMERIC EXECUTION UNIT, 3-7
Numeric Instruction Emulation, 3-2
Numeric Instruction Opcodes, 3-2
NUMERIC PROCESSOR EXTENSION
APPLICATIONS, 3-1
Numerically Based Applications, 3-1

o

Odd Address Boundary, 1-117
Odd Memory Address, 1-23
Offset, Memory Variable, 1-9
One Byte Interrupt - Type 3, 1-121
Opcode Fetch, 1-109
Opcode Extension
OPERAND ADDRESSING MODES, 1-18
Operand Addressing

Immediate Mode, 1-18
Register Mode, 1-18
Operand Identifiers Definitions, 4-5
Operand Names, 1-14
Operand Type Definitions, 4-14
Operands
16-bit Memory, 1-23
Additional, 1-23
Address, 1-71
Data, 1-71
Destination, 1-15
Extension, 2-9
110 Port, 1-17
Immediate, 1-21
Memory. 1-13, 1-18
Register, 1-13
Source, 1-15
Word, 1-21, 1-71
OPERATING MODES, 1-43,2-12,3-8,4-20
Maximum, 1-1
Minimum, 1-1
OPERATING SYSTEM PRIMITIVES SUMMARY, 5-1
Operation Command Word 1 (OCWl), 5-5
Operation Command Word 2 (OCW2), 5-5
Operation Command Word 3 (OCW3), 5-5
Operations
Arithmetic, 1-4, 1-5
Block Input, 2-5
Block Output, 2-5
Byte, 1-41,2-5
Compare, 1-12
Logic, 1-4, 1-5
Move, 1-12
Scan, 1-12
Stack, 1-5
Word, 1-24,2-5
Oscillator
Crystal, 2-24
External, 2-24
Oscillator to CLK and CLK to PCLK Timing, 1-128
Oscillators Feedback Circuit, 1-126
OSP Primitives, 5-1
OSP MEMORY USAGE, 5-11
OSP Primitives, 5-6
OSP Typical Configuration With An 8086, 5-10
Other Maximum Mode Considerations, 1-107
Output Request, 1-91
Outputs
Local Bus Controller, 2-25
Queue Status, 2-26
Status, 2-26
Overflow Error Service Routine, 1-121
Overflow Flag (OF), 1-6
Overlapped Instruction Fetch and Execution, 1-6

p
Parallel Priority Resolving Technique, 1-135
Parity Flag (PF), 1-6
Parity, Even, 1-6
Partitioning Memory By Segment, 1-65
PCLK Output, 2-24
Index-11

210912-001

INDEX

Performance Penalty, I-II
Peripheral Compatibility Parameters, 1-89
Peripheral Control Block Relocation Register, 2-19
Peripheral Devices, 2-3
8086 Family, 1-81
Peripheral Interfacing, 4-33
Peripheral Requirements For Full Speed, 1-91
Peripherals Cycle Dependent Parameter Requirements,
1-89
Physical Address, 1-8
PHYSICAL ADDRESS GENERATION, 1-8, 1-10
Physical Address, 20-bit, 1-18
Physical/Logical Bus Combinations, 4-2
Physical Memory Byte/Word Addressing, 2-35
PIC Commands, 5-2
Pin Assignments
Maximum Mode, 1-43
Minimum Mode, 1-43
Pipelined Architecture, 1-1
Pointer, 2-8, 32-bit, 1-122
POWER UP RESET, 1-130
Prefetch Queue
4-byte, 2-1
6-byte, 2-1
Prefetched Instructions, 1-1, 1-2,2-1
Preventing Erroneous Write Operations, 1-65
Priority Resolution, 1-65
Priority Structure Variations -Fully Nested Mode, 1-139
Process Control, 3-2
Processor Control Instructions, 1-17, 1-18, 2-11, 4-6
Processor Extension, 2-19
Processor Preemption

(RQ*/GT*), 1-64
Two Prioritized Levels, 1-52
Processor Ready Synchronization, 2-3
Processor
80186,2-1
80188, 2-1
Program Condition, 1-148
Program Counter (PC), 1-5
Program Execution Errors, 2-6
Program Status Word, 4-40
Program Transfer Instructions, 1-16,2-9,2-10,4-4
Conditional Transfer, 1-16
Interrupt-related, 1-16
Iteration Control, 1-17
Unconditional Transf, 1-16
Program Transfers, Four Groups, 1-16
Programs
8086,1-7
8088, 1-7
Disk-resident, 1-10
Dynamically Relocatable, 1-10
Inactive, 1-10
Position-independent, 1-10
Programmable 16-bit Timer/counters, 2-3
PROGRAMMABLE DIRECT MEMORY ACCESS
UNIT,2-3
Two Channel, 2-1

Programmable Interrupt Controller, 2-1, 2-3
PROGRAMMABLE INTERRUPT CONTROLLER
(PIC),5-2
Programmable Ready Bits, 2-3
PROGRAMMABLE TIMERS, 2-3, 5-8
16-bit, 2-1
Programming the 80130 OSP's Onchip Peripherals, 5-1
PROGRAMMING THE DMA UNIT, 2-51
Propagation Delay, 1-118
Protocol
HOLD/HLDA,2-26
RQ*/GT*, 2-26
Push All/Pop All (PUSHA, POPA) Instructions, 2-5
Push Immediate (PUSH!) Instruction, 2-5
Q
QSO, QSI, 1-98
QUEUE STATUS, 1-52
Queue Status (QSO, QSl), I-52
Queue Status Bit Decoding, 1-99
Queue Status Lines, 2-19
Queue Status Mode, 2-12
Queue Status Mode of Operation, 2-12
Queue Status Outputs, 2-26
Queue
4-byte Instruction, 2-3
6-byte Instruction, 2-1
8086, 1-3
8088 Instruction, 1-3
CPU Instruction, 1-16,2-9
Depth, 1-52
Instruction, 1-23,2-1,2-23
Instruction Object Code, 1-3,2-1
Instruction Stream, 1-3
Internal, 1-52,2-23
Internal Instruction, 1-66, 1-98
Internal Pre-fetch, 2-12
Pre-fetch, 2-23
Prefetch, 2-1
Sizes, 1-3
Status, 1-52
R
R/B/P Field Encoding, 4-21
RIM Field Bits, 3-7
RAM Bank, 2-40
RAM Interface, 2-36
RAM Wakeup Cycles, 2-40
RAS* Drivers, 2-40
RAS* Strobes, 2-40
RD*, 3-11, 3-16
RD* Active to Output Device Valid TRLDV, 1-89
RD* AND WR*, 2-29
RD* Status, 2-4
Read Bus Cycle (8-bit Bus), 4-35
Read Command, 1-99
Read Control Signal, 1-64
Read Cycles, 1-82, 1-99
Read Cycle Times, 2-37
Read Cycle Timing, 2-29
Read Pulse Width TRLRH, 1-89
READ/WRITE SIGNALS, 2-27

Index-12

210912·001

INDEX

Read-from Memory, 1-143
Reading the Count Value, 5-11
Reading the Interrupt Mask Register (IMR), 5-8
Ready Bits, 2-3
Ready Input
Asynchronous, 2-24
Synchronous, 2-24
OREADY CIRCUIT, 3-16
Ready Inputs to the 8284 and Output, 1-108
READY SYNCHRONIZATION, 2-80
Ready Timing, 1-98
READY/WAIT STATE GENERATION, 2-78
Real Time Clock, 2-58
Recommended Crystal Clock Configuration, 1-127
Recommended IAPX 186 Crystal Configuration, 2-80
Recommended Interrupt Configurations, 3-22
Reducing 8087 Delay Effects, 3-19
Refresh, 2-40
Refresh and Control Circuits, 2-37
Refresh Period Programming Option, 2-40
REG (Register) Field Encoding, 1-42
Register Address Coding, 1-147
Register and Immediate Operands, 1-18
Register Indirect Addressing, 1-18, 1-19
Register Operands, 2-7
Register Operands In Arithmetic Instructions, 4-5
Register Operands In Logical Instructions, 4-6
Register Operands In MOV Instructions, 4-5
Register/Memory Field Encoding, 1-43
Registers, 4-3
16-bit, 2-4, 2-7
16-bit Address, 1-144
16-bit Base Address, 1-145
16-bit Base Word Count, 1-145
16-bit Current Address, 1-145
16-bit Current Word, 1-145
16-bit General, 1-4
4-bit Mask, 1-147
4-bit Request, 1-147
6-bit Mode, 1-146
8-bit Command, 1-146
8237A Current Address, 1-144
8237A Current Word Count, 1-144
8237A Internal Memory, 1-145
AL, 1-13, 1-67, 1-85,2-7
AX, 1-13, 1-85,2-5,2-7
Base, 1-18
BP, 1-18, 1-20,2-6
BX, 1-18, 1-91,2-5
CL, 1-14, 1-15,2-5,2-9
Clear Mask, 1-148
Code Segment, 1-118
Command, 1-148
Communications, 1-3,2-1
Count (CX), 1-16
CS, 1-5, 1-120, 1-123, 1-124,2-9
Current Address, 1-45
Current Code Segment, 1-124
CX, 1-17, 1-68,2-5,2-9
Data, 1-7

01, 1-15, 2-5
DS,I-5
DX, 1-21, 1-85, 1-91,2-5,2-6
Eight General, 1-5
ES, 1-5
Flag, 1-3, 1-121, 1-122, 1-123, 1-124, 1-125,2-1,
2-5, 2-6
General, 1-4, 1-5,2-1
General Purpose, 2-5, 2-6
Index, 1-5, 1-18
Integrated Peripheral, 2-5
Internal, 2-4, 2-5
Internal First/Last Flip-Flop, 1-148
Internal CPU, 1-116
Interrupt Controller, 2-19
IP, 1-120, 1-123, 1-124
Mask, 1-148
P&I,I-4
Pointer, 1-4
Request, 1-148
Segment, 1-4, 1-5, 1-8, 1-122, 1-124,2-1,2-5,2-26,
2-33
SI, 1-15, 1-91,2-5,2-6
Single, 1-41
Sp, 1-122,2-5,2-9
SS, 1-4, 1-122
Status, 1-148
Temporary, 1-145, 1-148
Word Count, 1-144
Relationship of ALE to READ, 1-94
REMOTE MODE, 4-25
Repeat (REP) Prefix, 1-122
Repeated String Operation, 1-122
Representative Instruction Execution Sequence, 1-111
Request Register, 1-147
REQUEST/GRANT LINE, 3-11, 4-38
Request/Grant Sequence Timing, 1-117
Requests
HOLD, 1-64
RQ*/GT*, 1-64
RESERVED MEMORY, 1-11
Reserved Memory and 110 Locations, 1-12
Reserved Memory Locations, 1-82
RESET, 1-118,2-41,2-80
Reset Bus Conditioning, 1-118
RESET-CA Initialization Timing, 4-27
Reset Disable For Max Mode 8086/8088 Bus, 1-119
Reset Disable For Max Mode 8086/88 Bus, 1-120
Reset Startup, 1-65
Resident Bus, 1-134
Resident Bus (RESB) Mode, 1-134
Resident Bus Arbitration Logic, 1-64
Robotics, 3-2
ROM and EPROM, 1-82
ROM and EPROM Interface, 2-35
Rotate In Automatic EOI Mode, 1-139
Rotate On Automatic EOI Mode, 1-140
Rotate On Non-Specific EOI Command, 1-139
Rotate On Specific EOI Command, 1-140
Rotates, 1-14,2-9
Index-13

210912·001

INDEX

Rotation, 3-2
RQ/GTO, 1,3-11
RQ/GTI Pins, 3-3
RQ*/GT* LATENCY, 1-115
RQ*/GT* OPERATION, 1-114
RQ*/GT* Timing, 1-98
RQ*/GT* TO HOLD/HLDA CONVERSION, 1-113
RQ*/GT* USAGE, 1-113
S
S Field, 1-41
Sample Compatibility Analysis Configuration, 1-84
Scaling, 3-2
Schottky TTL Flip-flops, 2-26
Segment Base Value, 1-8
Segment Base Values, 1-8
Segment Locations In Physical Memory, 1-8
Segment Offset Values, 1-8
Segment Override Prefix, 1-9, 1-20
Segment Register Loading Instructions, 1-10
SEGMENT REGISTERS, 1-5, 1-71,2-1
CS,2-5
DS, 2-5, 2-6
ES, 2-5, 2-6
SS,2-5
Segment Values, 2-1
SEGMENTATION,I-7
Segments Adjacent, 1-8
Currently Addressable, 1-8
CS, 1-5
Current Code, 1-5
Current Data, 1-5, 1-15
Current Extra, 1-5, 1-15
Current Stack, 1-5
Disjoint, 1-8
Fully Overlapped, 1-8
Locations, 1-8
Logical, 1-8
Overlapping, 1-65
Partially Overlapped, 1-8
Serial Priority Resolving., 1-136
Set Priority Command, 1-139
Seven Contiguous 128 Byte Blocks, 2-3
Shared Bus Architecture, 1-1
Shared System Priority, 1-64
Shifts and Rotates
Single-bit, 1-41
Variable-bit, 1-41
Shifts, 1-14,2-5
Arithmetic, 1-14
Logical,I-14
Shifts/Rotates By An Immediate Value, 2-5
Sign Flag (SF), 1-6
Signal Float/HLDA Timing, 2-47
Signed Binary Numbers (integers), 1-14,2-8
Single Step -Type 1,1-121
Single T-State, 2-42
Single Transfer Mode, 1-144
Single-Bit Field Encoding, 1-42

Single-processor Systems, 1-1
Single-step Flags, 1-124
Single-step Mode, 1-7
Sixteen-Bit I/O, 1-88
Small8088-Based System, 1-2
SMALL~LOCK-NP~ESTORE,

SMALL~LOCK-NPX-SAVE,

3-21

3-21

software Based 8087 Emulator, 3-1
Software Command Codes, 1~147
Software Commands, 1-148
Software Emulator, 3-1
Software Emulator (E8087), 3-2
Software Overview, 1-12,2-4,3-7,4-3
Software Single Stepping, 1-121
Source & Destination Synchronized DMA, 2-56
Source Pointers, 2-4
Source String, 1-15
Source Synchronized DMA Transfers, 2-54
Source Synchronized Transfer Cycle, 4-31
Spare Bus Cycles, 1-1
Specially Fully Nested Mode, 1-142,2-69
Special One-byte Prefix, 2-9
Specific EO! Command, 1-139
Specific Rotation -Specific Priority, 1-140
Specified Cycle Termination, 1-64
SRDY, 3-11, 3-16
Stack Frames
Build,2-6
Tear Down, 2-6
STACK IMPLEMENTATION, 1-10
Stack Layout, 2-6
Stack Operation, 1-12
Stack Pointer Register (SP), 1-10
Stack Pointer Registers, 1-122
Stack Reference Point Offset, 1-20
Stack Segment's Base Address, 1-10
Stack
Current, 1-10
Directly Addressable, 1-10
Starting Locations, 1-5
Standard 5 MHz 8086, 2-1
Static RAM, 1-79
Status Bit Decoding, 1-71
Status Bit Output
SO*, 1-130
SI*, 1-130
S2*, 1-130
Status Bits, S3-S5, 2-26
Status Bus, 1-65
Status Flags, 1-5
Status Information, 1-72,2-26
Status Line Activation and Termination, 1-132
Status Line Decode Chart, 1-131
Status Line Decoders, 1-52
Status Line Encodings Interpretations, 2-31
STATUS LINES, 2-31, 4-34
Status Read, 1-148
Status Register, 1-148
Status Signals
SO*-S2*, 2-29, 3-3
Index-14

210912-001

INDEX

SO-S2,4-34
S3-S6,4-34
S3,2-33
S4,2-33
S5,2-33
S6, 2-29, 2-32, 3-3
S7,2-32
String Addressing, 1-20
String Instruction Register and Flag Use, 1-15
String Instructions, 1-15,2-10
Compare, 1-15
Destination Operand, 1-9
Move, 1-15
Scan, 1-15
String Operand Addressing, 1-21
String Operation
Interrupted, 1-64
Repeated, 1-64
String
Destination, 1-15
Source, 1-15
Strings of Bytes, 2-9
Strings of Words, 2-9
Submit File Example, 3-2
SUPPORT COMPONENTS, 1-125,2-51
Switch, $modI86, 2-5
Synchronization, 1-85, 3-13
SYNCHRONIZER REQUIREMENTS, 2-46
Synchronizing CSYNC With EPI, 1-128
Synchronizing Execution With WAIT, 3-15
Synchronizing Multiple 8284As, 1-129
Synchronizing the 8086 Or 8088, 1-17
Synchronous Interface, 2-41
Synthesizing Delayed Write From the 80186, 2-32
System Architecture, Minimum Mode, 1-44, 1-46
System Bus Arbitration, 1-113
System Bus Control Signals, 2-12
System Bus Interface, 1-52
SYSTEM BUS MODE, 1-133
System Bus Resources, 2-34
System Cost Reduction, 2-4
System Design Alternatives, 1-92
System Reset Processing, 1-11
System Status Outputs, 2-12
System Timing, 80186, 2-3
Systems
8086-based, 1-11
Multi-tasking, 1-10
Multiprogramming, 1-10

T
Tl, 1-65
Target Instruction Offset, 1-8
Thrget Location, 1-8
Thrget Relative Displacement, 2-10
Task Pointer, 4-3
Temporary Register, 1-148
TEST* AND LOCK*, 2-33
Test For the Existence of An 8087, 3-6
THE 8284A RESET FUNCTION, 1-129
The Effective Address, 1-18

Third Generation Microprocessors, I-I
Three Processor System Bus Signal Connections, 3-16
Time-multiplexed, 1-1
TIMER APPLICATIONS, 2-58
Timer Block Diagram, 2-57
Timer Control Block Format, 2-57
TIMER INPUT PIN OPERATION, 2-57
TIMER OUTPUT PIN OPERATION, 2-58
Timer Unit, 2-56
Timers, 5-10
Timers and Reset, 2-82
TIMING, 5-13
Top of Stack (TOS), 1-10
Transceiver Enable Delay, 1-106
Transfer Count, 2-4
TRANSFER TYPES, 1-145
Transfers, SHORT, 1-16
Trap Flag (TF), 1-7, 1-121
Tri-state Pin, 2-19
Type of Cycle Decoding, 4-37
Typical 8086/88 Machine Instruction Format, 1-41
Typical 8089 Machine Instruction Format, 4-21
Typical 8089 Remote Configuration, 4-26
TypicalIAPX 18612X Family System Diagram, 3-5
Typical IAPX 86/2X Family System Diagram, 3-4
Typical Medium Complexity CPU Circuit, 1-136
Typical Static RAM Write Timing Parameters, 1-84
U
UMCS Programming Values, 2-76
UMCS Register, 2-77
Unconditional Transfers, 1-16,2-10
Unformatted Memory Dumps, 1-25
Unsigned Binary Numbers, 1-14,2-8
Unsigned Packed Decimal Numbers, 2-8
Unsigned Unpacked Decimal Numbers, 1-14,2-8
Unused Opcode, 2-6
Upper Address Lines, 1-66
Upper Bank Write Strobe, 1-81
Upper Byte, 2-34
Upper Memory CS*, 2-76
Upper Memory Ending Location, 2-3
User Interrupt Routines, 1-120
User Programmable Areas, 2-3
User-Defined Hardware Interrupts, 1-122
User-Defined Software Interrupts, 1-122
Using AENI */AEN2* to Generate Ready, 1-110
USING THE 8087 WITH CUSTOM COPROCESSORS,
3-8
Using RDY 1/RDY2 to Generate Ready, 1-110
V
V Field, 1-41
Valid & Invalid Latch Input, 2-33
Valid Address Information, 2-23
Valid SRDY Transitions On the 80186, 2-46
Valid/Invalid ARDY Transitions, 2-45
Values
Compare, 2-9
Move, 2-9
Offset, 1-3
Scan For, 2-9
Index-15

210912-001

INDEX

Segment, 1-3
Variables, Memory Based, 1-13
Vector CS Address Pointer, 1-124
Vector IP Address Pointer, 1-124
Voltage Characteristics
A.C.,2-24
D.C., 2-23

W
WAIT, 3-14
WAIT Instruction, 3-11
Wait State Generator, 2-44
Wait State Insertion, 1-107
Wait State Timing, 4-38
WB Field Encoding, 4-21
Wait State Required Indication, 1-107
Wait States (TW), 1-66
Word Memory Location, 2-6

Word Memory Read, 1-109
Word Memory, 16-bit, 1-78
Word Operations, 2-5
Word Transfer, 1-112
Worst Case Local Bus Request Wait Times In Clocks,
3-28WR*, 3-26WR* Status, 2-4
Write Bus Cycle (l6-bit Bus), 4-36
Write Commands
Advanced, 1-106
Normal, 1-106
Write Cycle, 1-83, 1-99
Write Cycle Address Setup Times, 2-37
Write Cycle Address Times, 2-37
Write Cycle Timing, 2-31
Write Strobe Technique, 1-81
Write timing requirements, 1-81
Write-to-memory, 1-144

Z
Z field, 1-41
Zero flag (ZF), 1-6

Index-16

210912-001



---

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