2120 0085_DQ235_SMD_RK06_RK07_Controller_Jan86 0085 DQ235 SMD RK06 RK07 Controller Jan86
2120-0085_DQ235_SMD_RK06_RK07_Controller_Jan86 2120-0085_DQ235_SMD_RK06_RK07_Controller_Jan86
User Manual: 2120-0085_DQ235_SMD_RK06_RK07_Controller_Jan86
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DISTRIBUTED LOGIC CORPORATION
MODEL 00235
DISC CONTROLLER
INSTRUCTION-MANUAL
Part Number 2120-0085
MODEL DQ235
DISC CONTROLLER
INSTRUCTION MANUAL
January 1986
~Rnmm
I
I
DISTRIBUTED LOGIC CORPORATION
~~~~ :~:~n2c~gir Street
Anaheim. California 92806
Telephone: (714) 937-5700
Telex: 6836051
Copyright © 1986 by
Distributed Logic Corporation
Printed in the United States of America
TABLE OF CONTENTS
Section
1
Page
DESCRIPTION ................................................................. 1-1
INTRODUCTION .............................................................. 1-1
CONTROLLER CHARACTERISTICS ............................................ 1-1
LSI-IIQBUSINTERFACE .............................................
1-2
INTERRUPT .................................................................. 1-3
DISC INTERFACE ............................................................ 1-3
CONTROLLER SPECIFICATIONS .............................................. 1-4
I
•••••••
2
INSTALLATION ................................................................ 2-1
INSPECTION ................................................................. 2-1
PRE-INSTALLATION CHECKS ................................................. 2-3
INSTALLATION .............................................................. 2-3
3
OPERATION ................................................................... 3-1
INTRODUCTION .............................................................. 3-1
PRECAUTIONS AND PREOPERATIONAL CHECKS .............................. 3-1
BOOTSTRAP PROCEDURE .................................................... 3-1
FORMATANDDIAGNOSTICTESTPROGRAM ................ ; .................. 3-2
Description .................................................................. 3-2
Partitioning Program .......................................................... 3-7
Diagnostic Test Program ...................................................... 3-12
4
PROGRAMMING ............................................................... 4-1
PROGRAMMING DEFINITIONS ................................................ 4-1
DISC CONTROLLER FUNCTIONS ............................................... 4-1
Select Drive .................................................................. 4-1
Pack Acknowledge ............................................................ 4-1
Drive Clear .................................................................. 4-1
Recalibrate .................................................................. 4-1
Offset ...................................................................... 4-1
Seek ........................................................................ 4-1
Read Data ................................................................... 4-2
Write Data .................................................................. 4-2
Read Headers ................................................................ 4-2
Write Headers ................................................................ 4-2
Write Check ................................................................. 4-2
Mapping and Map Override. . . . . . . . . . . . . . . . . . . . . . . . .. . ......................... 4-2
ENABLE REAL TIME CLOCK CONTROL ........................................ 4-3
REGISTERS .................................................................. 4-3
Control and Status Register 1 ................................................... 4-5
Word Count Register .......................................................... 4-6
Bus Address Register .......................................................... 4-7
Disc Address (Track and Sector) Register .......................................... 4-7
Control and Status Register 2 ................................................... 4-8
Drive Status Register .......................................................... 4-9
Error Register ............................................................... 4-10
Attention Summary and Offset Register ......................................... 4-11
iii
TABLE OF CONTENTS (Continued)
Page
Section
Desired Cylinder Address Register .............................................. 4-12
Extended Memory Address Register (22-Bit) ...................................... 4-12
Read/Write Buffer Register .................................................... 4-13
Maintenance Register 1 ....................................................... 4-13
ECC Position Register ........................................................ 4-13
5
TROUBLESHOOTING AND THEORY ............................................. 5-1
BASIC SYSTEM TROUBLESHOOTING .......................................... 5-1
CONTROLLER SYMPTOMS .................................................... 5-1
PHYSICAL LAYOUT .......................................................... 5-1
TERM LISTING ............................................................... 5-1
THEORy ..................................................................... 5-5
Computer Interface ........................................................... 5-5
Disc Interface ................................................................ 5-6
Controller Internal Functions ................................................... 5-6
Data Buffer .................................................................. 5-7
ERROR CORRECTION CODE (ECC) LOGIC ....................................... 5-7
FunctionalOperation .......................................................... 5-7
Component Description ........................................................ 5-8
6
LOGICS
iv
ILLUSTRATIONS
Figure
1-1
2-1
2-2
3-1
4-1
5-1
5-2
5-3
Page
Disc Controller System Simplified Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Controller Configuration ........................................................... 2-1
Typical Backplane Configuration .................................................... 2-4
Partitions ....................................................................... 3-2
Controller Register Configurations .................................................. 4-4
Board Layout .................................................................... 5-3
Simplified Block Diagram .......................................................... 5-6
Data Paths ...................................................................... 5-8
TABLES
Table
Page
1-1
1-2
1-3
2-1
2-2
3-1
4-1
5-1
5-2'
Controller/Q-Bus Interface Lines .................................................... 1-2
Controller To Drive 110 Interface-" A" Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Controller To Drive 110 Interface-"B" Cable ......................................... 1-3
Configuration Switches ............................................................ 2-2
Jumper Installation .............................................................. 2-2
Values for Partitioning with Universal Firmware (DQ235) ............................... 3-3
Function Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Controller Symptoms ............................................................. 5-2
Term Listing .................................................................... 5-4
v
SECTION 1
DESCRIPTION
INTRODUCTION
This manual describes the installation, operation,
programming, troubleshooting, and theory of operation of Distributed Logic Corporation (DILOG)
Model DQ235 Disc Controller. The controller interfaces DEC· LSI -II based computer systems to one
or two SMD I/O disc drives, including 8- and 14-inch
Winchester, SMD pack and CMD cartridge type
drives. The complete controller occupies one quad
module in the backplane. Full sector buffering in the
controller matches the transfer rate of the disc drive
and the CPU. The controller is compatible with
RK06/RK07 software drivers in RT-ll, RSX-ll and
RSTS. Block mode transfers permit faster DMA
transfers to and from memory.
CONTROLLER CHARACTERISTICS
The disc controller links the LSI-II computer to
one or two disc storage units. Commands from the
computer are received and interpreted by the controller and translated into a form compatible with
the disc units. Buffering and signal timing for data
transfers between the computer and the discs are
performed by the controller.
A microprocessor is the sequence and timing
center of the controller. The control information is
stored as firmware instructions in read-onlymemory (ROM) on the controller board. One section
of the ROM contains a diagnostic program that
tests the functional operation of the controller. This
self-test is performed automatically each time power
is applied. A green diagnostic indicator on the controller board lights if self-test passes.
Data transfers are directly to and from the computer memory using the DMA facility of the LSI-II
I/O bus. Switch selectable DMA bursts of two or
four words may be used with or without block mode.
In addition, the controller monitors the status of the
disc units and the data being transferred and
presents this information to the computer upon
request. An error correction code with a 56-bit
checkword corrects error bursts up to 11 bits. To
compensate for media errors, bad sectors are
skipped and alternates assigned, and there is an
automatic retry feature for read errors. The controller is capable of addressing four megabytes and
controlling up to two disc drives in various configurations up to a total on-line formatted capacity of
220.32 megabytes. Figure I-I is a simplified diagram of a disc system.
*DEC, RSX and RSTS are registered trademarks of Digital
Equipment Corporation.
LSI-"
Q BUS
CONTROL (14)
26-PIN DATA
CABLE
J2
DISC
DRIVE
CONTROL (15)
a
Jl
DATA (16)/ ADDRESS (22)
COMPUTER
INTERFACE
MICROPROCESSOR
DISC
CONTROLLER
60-PIN
CONTROL
CABLE
DISC
DRIVE
INTERFACE
CONTROL (8)
DISC
DRIVE
J3
POWER GROUND
26-PIN DATA CABLE
FOR SECOND DRIVE
Figure 1-1. Disc Controller System Simplified Diagram
I-I
LSI·II Q BUS INTERFACE
Commands, data and status transfers between the
controller and the computer are executed via the
parallel 1/0 bus (Q bus) of the computer. Data trans·
fers are direct to memory via the DMA facility of
the Q bus; commands and status are under programmed 1/0. Controller/Q bus interface lines are
listed in Table 1-1.
Table 1-1. Controller/Q-Bus Interface Lines
Bus Pin
Mnemonic
Controller
Inputl
Output
Description
AC2, AJ1, AM1, AT1, BJ1,
BM1, BT1, BC2, CC2, CJ1,
CM1, CT1, DC2, DJ1, DM1,
DT1
GND
0
Signal Ground and DC return.
AN1
BDMR L
0
Direct Memory Access (DMA) request from controller: active
low.
AP1
BHALT L
N/A
AR1
BREF L
I
Memory Refresh, also signifies block mode memory.
BA1
BDCOK H
I
DC power ok. All DC voltages are normal.
BB1
BPOK H
N/A
BN1
BSACK L
0
Select Acknowledge. Interlocked with BDMGO Indicating
controller Is bus master In a DMA sequence.
BR1
BEVNT L
0
External Event Interrupt Request. Real Time Clock Control.
AA2,BA2, BV1,CA2,DA2
+5
I
+ 5 volt system power.
AD2, BD2
+12
N/A
+ 12 volt system power.
AE2
BDOUT L
110
Data Out. Valid data from bus master is on the bus. Interlocked
with BRPLY.
AF2
BRPLY L
110
Reply from slave to BDOUT or BDIN and during IAK.
AH2
BDIN L
110
Data Input. Input transfer to master (states master Is ready for
data). Interlocked with BRPLY.
AJ2
BSYNC L
110
Synchronize: becomes active when master places address on
bus; stays active during transfer.
AK2
BWTBT L
110
Write Byte: indicates output sequence to follow (DATO or
DATOB) or marks byte address time during a DATOB.
AA1, AB1, AL2, BP1
BI Ra4L,5,6, 7
0
Interrupt Request.
AM2
AN2
CM2
CN2
BIAK11 L
BIAK10 L
BIAK21 L
BIAK20 L
I
0
I
0
Serial Interrupt Acknowledge input and output lines routed from
a·Bus, through devices, and back to processor to establish an
Interrupt priority chain.
AT2
BINIT L
I
Initialize. Clears devices on 110 bus.
AU2, AV2, BE2, BF2, BH2,
BH~ BK2, BL~BM~ BN~
BP2, BR2, BS2, BT2, BU2,
BV2
BDALO L
through
BDAL15 L
110
AR2
AS2
CR2
CS2
BDMG11 L
BDMG10 L
BDMG21 L
BDMG20 L
0
I
AP2
BBS7 L
110
Bank 7 Select. Asserted by bus master when address in upper 4K
bank is placed on the bus, also asserted when requesting block
mode transfer.
AC1, AD1, BC1, BD1, BE1,
BF1
BDAL 16 L
·BDAL 21 L
0
Extended Address Bits 16·21
1-2
I
Stops program execution. Refresh and DMA is enabled.
Console operation Is enabled.
Primary power ok. When low activates power fall trap sequence.
Data/address lines, 0·15
DMA Grant Input and Output. Serial DMA priority line from
computer, through devices and back to computer.
INTERRUPT
The interrupt vector address is factory set to
address 210 (alternate 254). The vector address is
programmed in a PROM on the controller, allowing
user selection.
Interrupt requests are generated under the following conditions:
.
1. When the Controller Ready bit is set upon
completion of a command.
2. When any drive sets an associated Attention
Flat in the Attention register and the Controller Ready bit is set.
3. When the controller or any drive indicates the
presence of an error by setting the combined
ErrorlReset bit in the Control and Status
register.
4.
When the Controller Ready bit is set by conventional initialization upon completion of a
controller command or when an error condition is detected. For test purposes, a forced
interrupt may be generated by the Controller
Ready and Interrupt Enable bits.
DISC INTERFACE
The controller interfaces one or two disc drives
through so- and 2S-pin cables. If two drives are
used, the SO-pin control cable ("A" cable) is daisy
chain~d to drive 0 and 1. The 2S-pin cables ("B"
cable) are connected separately from the controller
to each drive. The maximum length of the SO-pin
cable is 100 feet. The maximum length of the 2S-pin
cable is 50 feet. Table 1-2 lists the SO-pin interface
signals, and Table 1-3 lists the 2S-pin interface
signals.
Table 1·2. Controller To Drive 1/0 Interface"A" Cable
Pin Polarity
(Active)
Signal Name
DEVICE SELECT 0
DEVICE SELECT 1
DEVICE SELECT 2
DEVICE SELECT 3
SELECT ENABLE
SET CYLINDER TAG
SET HEAD TAG
CONTROL SELECT
BUS aUTO
BUS OUT 1
BUS OUT 2
BUS OUT 3
BUS OUT 4
BUS OUT5
BUS OUT6
BUS OUT 7
BUS OUT 8
BUS OUT9
BUS OUT 10
DEVICE ENABLE
INDEX
SECTOR MARK
FAULT
SEEK ERROR
ON CYLINDER
UNIT READY
WRITE PROTECTED
ADDRESS MARK
BUS·DUAL·PORT ONLY
SEQUENCE IN
HOLD
-
+
Source
23
24
26
27
22
1
2
3
4
5
6
7
8
9
10
11
12
13
30
14
18
25
15
16
17
19
28
20
21
29
59
53
54
56
57
52
31
32
33
34
35
36
37
38
39
40
41
42
43
60
44
48
55
45
46
47
49
58
50
51
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Controller
Drive
Drive
Drive
Drive
Drive
Drive
Drive
Drive
Drive
Controller
Controller
Table 1-3. Controller To Drive 1/0 Interface"B" Cable
Signal
Ground
Servo Clock
Ground
Read Data
Ground
Read Clock
Ground
Write Clock
Ground
Write Data
Ground
Unit Selected
Seek End
Ground
Reserved for Index
Ground
Reserved for Sector
-
Pin Polarity
(Active)
+ Ground
Source
1
2
14
Drive
15
3
16
Drive
4
5
Drive
17
18
6
19
Controller
7
8
Controller
20
21
22
10
9
23
12
24
13
26
Drive
Drive
11
25
1-3
CONTROLLER SPECIFICATI()NS·
Mechanical-The Model DQ235 is completely contained on one quad module 10.44 inches wide by 8.88
inches deep, and plugs into and requires one slot in
any DEC LSI-II based backplane.
Computer 1/0
Register Addresses (PROM selectable)
-Control/Status Register 1 (RKCSl) 777 440
-Word Count Register (RKWC) 777 442
- Bus Address Register (RKBA) 777 444
- Disc Address Register (RKDA) 777-446
-Control/Status Register 2 (RKCS2) 777 450
- Drive Status Register (RKDS) 777 452
-Error Register (RKER) 777 454
-Attention Summary/Offset Register (RKAS/
OF) 777 456
-Desired Cylinder Register (RKDC) 777 460
-Extended Memory Address Register (RKXMA)
777 462
-Data Buffer Register (RKDB) 777 464
-Maintenance Register 1 (RKMRl) 777 466
- ECC Position Register (RKECPS) 777 470
- ECC Pattern Register (RKECPT) 777 472
- Maintenance Register 2 (RKMR2) 777 474
-Maintenance Register 3 (RKMR3) 777 476
-Enable Real Time Clock Control (RKERTC)
777 546
Data Transfer
-Method: DMA with or without block mode.
- Maximum block size transferred in a single
operation is 64K words.
-2 or 4 word DMA burst transfer.
1-4
Bus Load
-1 std unit load
Address Ranges
- Disc drive: up to 220.32 megabytes
-Computer Memory: to 2 megawords
Interrupt Vector Address
-PROM selectable, factory set at 210 (alternate
254) priority level BR5
Disc Drive 1/0
Connector-one 60-pin type "A" flat ribbon cable
mounted on outer edge of controller module Two 26pin type "B" ribbon cables (1 for each drive interfaced with).
Signal-SMD A/B flat cable compatible
Power-+5 volts at 3.5 amps from computer power
supply.
Environment-Operating temperature 40 of. to
140°F., humidity 10 to 95% non-condensing.
Shipping Weight-5 pounds, includes documentation and cables.
*Specifications subject to change without notice.
SECTION 2
INSTALLATION
CAUTION
INSPECTION
The padded shipping carton that contains the controller board also contains an instruction manual
and cables to the first disc drive if this option is
exercised. The controller is completely contained on
the quad-size printed circuit board. Disc drives, if
supplied, are contained in a separate shipping
carton. Inspect the controller and cables for
damage.
TP1 D
Installation instructions for the disc drive are contained in the disc drive manual. Before installing
any components of the disc system, read Sections 1,
2 and 3 of this manual. Figure 2-1 illustrates the configuration of the controller. Tables 2-1 and 2-2
describe switch and jumper settings.
PIN 1
PIN 1
A4
If damage to any of the components is
noted, do not install. Immediately inform
the carrier and DILOG.
J1
PIN 1
J2
~DQ23.
I
REV.
DTP2
817
SIN
1:0
C9
0
SW1
123
JP5
C18
1
2CJ4
3
JP1
C17
1D3
JP2
C22
~D
SW2
E23
3
540 2
F1
0
JP4
6 JP3 1
1
2
o
C
8
A
Figure 2-1. Controller Configuration
2-1
Table 2·1. Configuration Switches
LOCATION B17 SWITCHES (SW·1)
51
(LSB)
,
52
~
\
I
Binary Number of the first
logical unit of the second
physical drive. *
ON
57
56
55
54
53
(M5B)
(L5B
58
59
y
I
Binary number of last
addressable logical unit.
= Bootstrap
510
(M5B),
=
ON = Enable Real TimE
Clock Control. When
enabled, emulates the real
time clock register,
address 777 546
OFF = Disables Real Time
Clock Control.
ON
Controller
enable
error correction
OFF = Bootstrap OFF = CPU error
disable
correction
·ON = Enable
4-word burst
OFF= Enable
2-word burst
LOCATION C22 SWITCHES
Switch
Position
S1
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
S2
S3
S4
S5
S6
S7
*DEFAULT SETUP
S8
Logical Unit
and Emulation
LUO
LUO
LU1
LU1
LU2
LU2
LU3
LU3
LU4
LU4
LU5
LU5
LU6
LU6
LU7
LU7
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
RK07
RK06
RK07
RK06
RK07
RK06
RK07
RK06
RK07
RK06
RK07
RK06
RK07
RK06
RK07
RK06
Table 2-2. Jumper Installation
LOCATION C18
BOOTSTRAP ADDRESS
JUMPER JP1
12- - 4
*1* *2 to 3 (standard) 773 000
1 to 2 (alternate) 775 000
3-
LOCATION E23
INTERRUPT LEVEL
JUMPER JP3
Jumper Installed
Level
1·6, 2·5, 3·4
*2·5,3·4
1·6,3·4
1·6
BR4
BR5 (Factory Set)
BR6
BR7
*2·3 (standard) 777 440
Interrupt Vector = 210
LOCATION C17
DEVICE ADDRESS
JUMPER JP2
1·2 (alternate) 776 700
Interrupt Vector = 254
LOCATION F1
JUMPER JP4
LOCATION C9
JUMPER JP5
*
Factory use only. Must be installed.
*2·3 (standard)
1·2
For drives with data rates of 1.2
megabytes (9.677 megabits) per
second or greater.
For drives' with data rates of less
than 1.2 megabytes (9.677 megabits)
per second.
*DEFAULT SETUP
* *On an LSI-11/23 PLUS computer, bootstrap address 775 000 must be used.
PRE-INSTALLATION CHECKS
There are several backplane assemblies
available from DEC and other manufacturers. Figure 2-2 shows typical backplane configurations. Note that the processor module
is always installed in the first location of the
backplane or in the first location in the first
backplane of multiple backplane systems.
It is important that all option slots between
the processor and the disc controller be filled
to ensure that the daisy-chained interrupt
(BIAK) and DMA (BDMG) signals be complete to the controller slots. If there must be
empty slots between the controller and any
option board, the following backplane
jumpers must be installed:
There are various LSI-II configurations, many of
which were installed before DEC made a hard disc
available for LSI-II based systems. Certain configurations require minor modifications before operating the disc system. These modifications are as
follows:
A. If the system contains a REVII-C module, it
must be placed closer to the processor module
(higher priority) than the controller if the
DMA refresh logic on the REVII-C is
enabled.
B. If the 4K memory on the DKII-F is not used
and the memory in the system does not require external refresh, the D MA refresh logic
on the REV11-C should be disabled by removing jumper W2 on the REVII-C module.
C. If the system contains a REV11-A module,
the refresh DMA logic must be disabled since
the module must be placed at the end of the
bus (REVII-A contains bus terminator).
CO x NS
CO x S2
CO x M2
CO x R2
BIAK1/LO
BDMG1/LO
t
Controller
Slot
2.
Insert the controller into the selected backplane position. Be sure the controller is installed with the components facing row one,
the processor.
The controller module is equipped with
handles on the side opposite the slot connectors. Gently position the module slot connectors into the backplane then press until the
module connectors are firmly seated into the
backplane. Both handles must be pressed
simultaneously. When removing the module,
apply equal pulling pressure to both handles.
3.
Feed the module connector end of the disc I/O
cables into the controller module connectors.
Ensure pin 1 is matched with the triangle on
the connector as shown in Figure 2-1. Install
the cable connectors into the module connectors. Verify that the connectors are firmly
seated.
INSTALLATION
To install the controller module, proceed as
follows:
Select the backplane location into which the
controller is to be inserted. Be sure that the
disc controller is the lowest priority DMA
device in the computer except if the DMA
refresh/bootstrap ROM option module is installed in the system. The lowest priority
device is the device farthest from the processor module. Note that the controller contains
a bootstrap ROM.
SIGNAL
t
E. If the system requires more than one backplane, place the REV-II terminator in the
last available location in the last backplane.
1.
TO
Last Full
Option Slot
D. If the REV11-C module is installed, cut the
etch to pin 12 on circuit D3D (top of board)
and add a jumper between pin 12 and pin 13
of D3D.
CAUTION
Remove DC power from mounting assembly
before inserting or removing the controller
module.
Damage to the backplane assembly may
occur if the controller module is plugged in
backwards.
FROM
4. Connect the disc-end of the I/O cables to the
disc I/O connectors. Be sure that the bus
terminator is installed at the last disc in the
system.
5.
Refer to the disc manual for operating instructions and apply power to the disc and
computer.
6. Observe that the green DIAGnostic LED on
the controller board is lit.
7. The system is now ready to operate. Refer to
Section 3 for operating instructions, diagnostics, and formatting.
2-3
B
A
LOCATION
0
C
I
OPTION 1
OPTION 2
2
PROCESSOR
MODULE
COMPONENT SIDE
3
4
OPTION 3
OPTION 4
OPTION 6
OPTION 5
SOLDER SIDE
~
.. PREFERRED DISC
CONTROLLER LOCATION
/MODUL
H9270 MODULE INSERTION SIDE
PROCESSOR
A
B
C
E
D
.
E
F
/
OPTION
2
OPTION
1
-0
OPTION
3
OPTION
4
3
- 00
OPTION
6
OPTION
5
4
+5VB ~-
OPTION
7
OPTION
8
5
0
---0
-
OPTION
10
OPTION
9
6
OPTION
11
OPTION
12
7
OPTION
14
OPTION
13
8
OPTION
15
OPTION . 16
9
+ 12V
-5V
+5V
GND
GND
-12V
POWER
TERMINA L /
BLOCK
0
PREFERED DISC
CONTROLLER LOCATION
"
DDV11·B BACKPLANE MODULE INSERTION SIDE
i
2
/
USER DEFI N ED
SLOTS
NOTE
MEMORY CAN BE INSTALLED IN ANY SLOT; IT IS NOT
PRIORITY DEPENDENT AND DOES NOT NEED TO BE
ADJACENT TO THE PROCESSOR.
CONTROLLERS ARE ALSO COMPA TlBLE WITH H9273A
MODULES.
Figure 2-2. Typical Backplane Configuration
GROUNDING
To prevent grounding problems, DILOG recommends standard ground braid be installed from the
2-4
computer DC ground point to the disc drive DC
ground point and also between disc drives at the DC
ground points.
SECTION 3
OPERATION
INTRODUCTION
3. Be sure the disc drive cartridge is installed (if
it is to be used).
This section contains procedures for operating the
computer system with the controller and a disc
drive or drives. An understanding of DEC operating
procedures is assumed. The material here is provided for "first time users" of disc subsystems and
describes procedures for bootstrapping, formatting,
and diagnostic testing.
The programs supplied with each controller are on
floppy disc or magnetic tape media, depending on
wha t is specified on the sales order.
4. Apply power to the computer and the console
device.
PRECAUTIONS AND PREOPERATIONAL
CHECKS
The following precautions should be observed
while operating the system. Failure to observe these
precautions could damage the controller, the disc
cartridge, the computer, or could erase a portion or
all of the stored software.
1.
If the controller bootstrap is to be used, set
controller switch S4 ON, and disable other
.bootstraps that reside at that address.
2. See Figure 2-1 for proper positions of the
switches and jumpers. See Tables 2-1 and 2-2
for switch and jumper settings.
3. Do not remove or replace the controller board
with power applied to the computer.
4. If system does not operate properly, check
operating procedures and verify that the
items in Section 2 have been performed.
Before operation the following checks should be
made:
1. Verify that the controller board is firmly
seated in backplane connector.
5. Verify that green DIAO light on front edge of
the controller board lights.
6. Be sure power is applied to disc drive and
READY light is on.
BOOTSTRAP PROCEDURE
The following assumes the system is in ODT
mode. Note that the bootstrap can be used under
processor Power Up Mode 2 conditions. Refer to the
appropriate DEC manual for a discussion of the
Power Up Modes. Further note that the disc drive
does not need to be READY to enter the bootstrap.
Reset the system by pressing RESET or enter the
following (characters underlined are output by the
system; characters not underlined are input by the
operator):
@
7730000 or 7750000
Depends on jumper configuration above.
*
Enter one of the following: DMO, DPO, DLO,
DRO, MSO, MTO, DYO or FT .
Definitions are as follows:
DM = RK06/07 Disc
DP = RP02/03 Disc
DL = RLOll02 Disc
DR = RM02/03 Disc
MS = TSll Tape
MT = Tape
DY = RX02 Floppy Disc
Booting can be executed from logical units other
than "0" shown above by entering the desired logical unit number, i.e., 1, 2, 3, ... or 7.
2. Verify that the cables between the controller
and the disc drive are installed.
3-1
VERTICAL PARTITION
FORMAT AND DIAGNOSTIC TEST PROGRAM
*CYLINDER
Description
DILDO's Universal Firmware and Diagnostic
Program permits the user to format a disc pack for
his particular application; compensate for media
errors; and test the controller and drive. When formatted, the disc may be partitioned horizontally or
vertically. Either way the pack is divided into
logical units which the computer recognizes. Th~
user may select one of three types of partitioning:
I-head, 2-head or vertical.
The constraints for selecting each are:
/
823
\.
000
COVER - - - - - ,
HEAD PARTITION
DISK SURFACE _ _.......J
HEAD a
DISK SURFACE
HEAD 1
--~
Subsystem:
• Maximum number of logical units is 8.
I-head:
• Maximum number of heads (surfaces) is 8.
• Maximum size of logical units is 270,336
records.
DISK SURFACE - - - - - '
HEAD 2
DISK SURFACE - - - n
HEAD 17
2-head:
• Maximum number of heads (surfaces) is 16.
• Number of fixed and removable heads (surfaces) must be even.
• Maximum size of logical units is 270,336
records.
DISK SURFACE - - - - - '
HEAD 18
DISK SURFACE - - - + .
HEAD 19
Vertical:
• Maximum size of logical units is 270,336
records.
A TRACK IS ACCESSED
BY SPECIFYING CYLINDER
ADDRESS AND HEAD ADDRESS
Drive types CMD or DFR are formatted for a
I-head partition. SMD or MMD types are usually
formatted vertically.
The disc pack is divided vertically by cylinders
and horizontally by heads (or data surfaces). Each
head (surface) is further divided into tracks. A track
is addressed by cylinder number and head number.
Tracks are further divided into sectors (or records or
blocks) which the computer recognizes as increments within a logical unit. Sectors consist of overhead bytes (such as address, sync, error correction)
and data bytes. The standard number of data bytes,
bytes usable by the computer, is 512 data bytes per
sector. Figure 3-1 illustrates vertical and head
partitioning.
Table 3-1 is a partial list of disc drives and specifications for partitioning. Column 1 lists the manufacturer. Column 2 lists the model number. Column
3 lists the number of sectors (also called records and
blocks) per track. Column 4 lists the number of
heads (also called data surfaces) per drive. Column 5
lists the number of cylinders per drive. Columns 6
3-2
* NUMBER OF CYLINDERS AND HEADS
VARIES WITH TYPE OF DRIVE
Figure 3-1. Partitions
and 7 list the emulations, the number of megabytes
per logical unit, and the number of sectors per
logical unit. Column 8 lists the megabyte capacity
and number of sectors of the last logical unit partitioned. For CMD drives (Note c), the value listed is
for all logical units as well as the last.
To use the table, consider Ampex Capricorn 165
as an example. The drive is efficiently partitioned
into five RK07 units with capacity and number of
sectors shown at the top of Column 6. The remaining capacity is assigned as one RK06 unit with the
capacity and sectors shown at the top of Column 7;
however, the RK06 unit is the remainder after
partitioning five RK07 units, and as such, this
remainder is not a complete RK06 unit. Instead of
13.88 Mbytes with 27,126 sectors, the partial RK06
unit is assigned the remaining 8.78 Mbytes and
17,150 sectors. Notes a and b in Column 8 state
Table 3·1. Values for Partitioning with Universal Firmware (DQ235)
(2)
Model
Number
(1)
Manufacturer
AMPEX
AMPEX
Capricorn 165
Capicorn 330
(3)
Sectors
(Records)
(Blocks)1
Track
35
(4)
Heads
(Data Surfaces)1
DriVE
Removable Fixed
10
0
(7)
(6)
Total Logical Units
RK07
RK06
(8)**
(5)
Units
Units
Cyllndersl 27.54MB 13.88MB Last Logical Unit
53,790 27,126
Sectors
MB
Drlve*
823
16
1024
5
8
3
823
1
1
4
16.45b
2.25 8
32,130
4,410
2
1
6
1S.1Sb
3.498
35,525
6,825
2
14.25c
27,846
4
14.25c
27,846
6
14.25c
27,846
35
AMPEX
Scorpio SO
35
0
5
823
AMPEX
DFR·932
34
1
1
823
DFR·996
2,240
17,150
0
Scorpio 48
AMPEX
S.78 8
35
AMPEX
DFR·964
1
1.14d
0
AMPEX
5
34
34
1
3
1
5
823
823
AMPEX
DM980
34
5
0
823
2
1
6
16.10b
1.658
31,450
3,230
BALL
8050
23
5
0
815
1
1
4
20.19b
6.06 8
39,445
11,845
BALL
8080
34
5
0
815
2
1
6
15.40b
.95a
30,090
1,870
BASF
6172
23
0
3
600
2
7.13 8
13,938
1
6
14.86b
29,028
246
CENTURY DATA SYS.
M80
35
CENTURY DATA SYS.
M160
35
6
0
0
650
837
5
1
3.04 8
5,940
2
1
6
16.10b
1.658
31,450
3,230
3
5
7.60 8
7.60 8
14,058
14,858
2
14.25c
27,846
4
14.25c
27,846
923
6
14.25c
27,846
8.78 8
17,150
CENTURY DATA SYS.
Trident T·82RM
34
5
0
CENTURY DATA SYS.
T·302
34
19
0
823
CONTROL DATA CORP.
CMD 9448-32
34
1
1
823
CONTROL DATA CORP.
CMD 9448-64
CMD 9448-96
34
34
1
3
1
.128
6
823
CONTROL DATA CORP.
2
5
823
CONTROL DATA CORP.
FSD 9715
35
0
10
823
6
8
CONTROL DATA CORP.
FSD 9715-340
35
0
24
711
8
8
_d
CONTROL DATA CORP.
FSD 9715-500
50
0
24
711
8
8
_d
CONTROL DATA CORP.
MMD 9730-24
35
0
2(2)=4
320
2
8.74 8
17,080
35,525
6,825
CONTROL DATA CORP.
MMD 9730-80
35
0
5
823
2
1
6
18.18b
CONTROL DATA CORP.
MMD 9730-160
35
0
~5)=10
823
5
1
8.78 8
17,150
2
1
6
16.10b
1.658
31,450
3,230
2
3
6.63 8
6.278
12,950
12,250
1
23.48 b
45,866
CONTROL DATA CORP.
SMD 9762
34
5
0
823
CONTROL DATA CORP.
Lark II
35
0
10
823
CONTROL DATA CORP.
SMD 9764
34
19
0
411
4
3.49 8
*For a 1·head partition, the value of cylinders/drive = tracks/surface.
**Calculated using 4 alternates.
8Less than standard RK06
bGreater than standard RK06
cCMD
dMost efficient use is not standard RK06/07 logical units but as one large logical unit or up to eight equal-size nonstandard units.
3-3
Table 3·1. Values for Partitioning with Universal Firmware (DQ235) (Continued)
(2)
Model
Number
(1)
Manufacturer
I
(3)
Sectors
(Records)
(Blocks)'
Track
(4)
Heads
(Data Surfaces)'
Drive
Removable Fixed
(6)
(7)
Total Logical Units
RK07
RK06
(5)
(8)**
Units
Units
Cylinders' 27.54MB 13.88MB Last Logical Unit
53,790 27,126
MB
Sectors
Drlve*
7.60 8 14,858
5
823
3
7.60 8 14,858
CONTROL DATA CORP.
SMD 9766
34
19
0
FUJITSU
M-2283
35
0
4
823
2
1
5
3.518
3.088
6,860
6,020
FUJITSU
M-2284
35
0
~5)=10
815
5
1
7.34 8
14,350
28,000
420
FUJITSU
2311
35
0
4
589
1
1
4
14.33b
0.218
FUJITSU
M-2333K
65
0
10
823
8
8
_d
FUJITSU
2312
35
0
7
589
2
1
6
18.18b
3.76 8
35,525
7,350
FUJITSU
M-2351A
47
20
0
842
4
8
17.328
3.36 a
33,840
6,580
KENNEDY
5305
35
0
5
700
2
1
5
7.16 a
6.45 8
14,000
12,600
KENNEDY
5380
35
0
5
823
2
1
6
18.18b
3.49a
35,525
6,825
MITSUBISHI
2860-2
23
0
7
548
1
1
4
17.22b
3.05 8
33,649
5,957
NEC
D1220
35
0
4
530
1
1
3
10.108
9.89 8
19,740
19,320
NEC
01240
35
0
2(4)=8
530
2
1
6
20.07 b
5.87 a
39,200
11,480
NIPPON PERIPHERALS
NP30-40
35
0
5
370
1
1
3
5.19 a
4.03a
10,150
9,450
NIPPON PERIPHERALS
NP30-80
35
0
11
370
2
1
6
16.95b
2.16 a
33,110
4,235
NIPPON PERIPHERALS
NP30-120
35
0
11
555
3
1
8
25.82b
10.64a
50,435
20.790
PRIAM
806
35
0
11
850
7
1.188
2,310
8
-
d
PRIAM
807
35
0
11
1489
8
8
_d
PRIAM
808
50
0
11
1489
8
8
_d
PRIAM
DISKOS 3350
35
0
3
561
1
1
3
2.36 a
2.09 8
4,620
4,095
PRIAM
6650
35
0
3
1121
2
1
5
4.89 a
4.35 a
9,555
8,505
PRIAM
15450
35
0
7
1121
5
1
2.38 a
4,655
1
10.96a
21,420
1
8.78 8
17,150
TECSTOR
TECSTOR
Sapphire 160
Sapphire 165
35
35
0
0
12
10
700
823
5
5
*For a 1-head partition, the value of cylinders/drive = tracks/surface.
* *Calculated using 4 alternates.
aLess than standard RK06
bGreater than standard RK06
cCMD
dMost efficient use is not standard RK06/07 logical units but as one large logical unit or up to eight equal-size nonstandard units.
3·4
whether the last unit is an expanded or a partial
unit.
The values in the table are calculated for the most
efficient use of the drive; that is, total formatting
capacity of the drive with a standard number of
spare cylinders. The user may require another type
of partitioning for a particular application, in which
case the program will prompt and calculate for that
application.
Parameters for disc drives not listed in Table 3-1
may be determined from manufacturer's specifications and the following: Determine the number of
bytes per track from the manufacturer's specification. The number of bytes per sector (data and overhead) for DILOG controllers is 576. Divide the number of bytes per track by the number of bytes per
sector. Drop the remainder. This value is the
number of sectors per track. Then, number of
sectors per track X number of heads X number of
cylinders per drive = number of sectors per drive.
The user may require alternate cylinders, or
spares, to compensate for media flaws, soft errors,
or marginal drive conditions. The values in the table
provide for four alternate cylinders. All three types
of partitioning in the program make provisions !or
sparing. The program accounts for alternates when
calculating the number and size of logical units.
If the number of logical units is to be changed, the
configuration switches, shown in Figure 2-1, should
also be changed after completion of format and test.
The descriptions below indicate what parameters
will be changed as various elements are changed; for
example, if the number of logical units is changed,
the size of the logical units will change.
I-Head Partition
A I-head partition is used for CMD drives. The
column numbers below refer to Table 3-1. Parameters are developed as follows:
5. Then, sectors per track X heads per drive X
(tracks per surface minus alternates) =
sectors per drive.
6. Sectors per drive X 512
= byte capacity.
For example, an AMPEX DFR-932 has 34 sectors
per track, 2 heads per drive and 823 tracks/surface.
If 4 alternates are required, then:
34 X 2 X (823 - 4)
= 55,692 sectors/drive
Because there are two heads, there are two logical
units.
55,692 = 27,846 sectors/logical unit
2
and
27,846 X 512 = 14.25 megabytes/logical unit
2-Head Partition
The parameters for 2-head partitioning are the
same as for I-head except the number of sectors/
logical unit is multiplied by 2:
1. Determine the number of sectors per track
(Column 3), heads per drive (Column 4), and
tracks per surface (Cylinders per Drive,
Column 5).
2. Determine the number of alternate tracks
(cylinders) per drive. The standard number of
alternates is four.
3. Subtract the number of alternates from the
tracks per surface.
4. Then, sectors per track X heads per drive X
(tracks per surface minus alternates) =
sectors per drive.
5. Sectors per drive X 512
= byte capacity.
Determine the number of sectors per track
(Column 3), heads per drive (Column 4), and
tracks per surface (Column 5). For a I-head
partition, the number of tracks per surface is
the same as cylinders per drive in the table.
For example, a CDC 9730-24 has 35 sectors per
track, 4 heads per drive and 320 tracks per surface.
If 4 alternates are required, then:
2. Determine the number of alternate tracks
(cylinders) per drive. The standard number of
alternates is four.
Because there are four heads, and two heads comprise one logical unit, there are two logical units.
1.
3.
35 X 4 X (320-4)
44,240 = 22,120 sectors/logical unit
Subtract the number of alternates from the
tracks per surface.
4. The number of heads corresponds to the
number of logical units.
= 44,240 sectors/drive
2
and
22,120 X 512 = 11.32 megabytes/logical unit
3-5
1.
Vertical Partition
Determine the required number of alternate
cylinders per drive. Subtract the number of
alternates from the number of cylinders per
drive (Column 5). This value is the usable
cylinders per drive.
With vertical partitioning, the user may select the
number of logical units or the size of the logical unit.
If the number of logical units is selected, the logical
units will be of equal size. If the size of the logical
units is selected, all logical units may not be of equal
size. For example there may be 2 equal RK07 logical
units of 53,790 sectors/logical unit and a partial
RK06 logical unit of 31,450 sectors/logical unit.
Parameters for vertical partitioning are determined as follows:
The user specifies the number of logical units (all
logical units are of equal size):
3. Sectors per track (Column 3) X number of
heads (Column 4) divided into sectors per logical unit = cylinders per logical unit. If there
is a remainder, the number of cylinders per
logical unit is rounded off to the next higher
number.
Determine the required number of alternate
cylinders per drive. Subtract the number of
alternates from the number of cylinders per
drive (Column 5). This value is the usable cylinders per drive.
4. Number of usable cylinders divided by
cylinders per logical unit = number of logical
units. If there is a remainder, the number of
logical units is rounded off to the next higher
number.
2. Determine the number of logical units per
drive required. Then,
5. Number of cylinders per logical unit X
number of full (equal size) logical units =
Number of cylinders full (equal size) logical
units.
1.
3. Number of usable cylinders per drive divided
by number of logical units required = Number
of cylinders per logical unit. The remainder is
assigned as alternate.
4. Number of cylinders per logical unit X
sectors per track X number of heads =
Number of sectors per logical unit.
5. Number of sectors per logical unit X 512
Megabyte capacity per logical unit.
=
2. Determine the required number of sectors
(blocks) per logical unit. Then,
6. Number of usable cylinders per drive minus
number of cylinders in full logical units =
Number of cylinders in partial logical unit.
For example, if the user has a Century Data drive,
Model T-82RM, and 4 alternates and 53,790 sectors
per logical unit (standard RK07) are required, then
823 - 4
= 819 usable cylinders
and
For example, if the user has a Century Data drive,
Model T-82RM and 4 alternates (standard) and 3
logical units are required, then
823 - 4
= 819 usable cylinders
which becomes
31 7 cylinders per logical unit
and
819
3
= 273
If there was a remainder, the number of alternates
would be more than initially selected.
Then,
273 X 34 X 5 = 46,410 sectors per logical unit
and
then,
819
317
= 2.58 logical units per drive
or 2 RK07 units and 1 partial RK06 unit.
For the partial logical unit,
The user specifies the size of logical units in
sectors per logical unit (the last logical unit will be a
different size).
= 634
634 = 185 cylinders per partial logical
317 X 2
819 -
46,410 X 512 = 23.76 Mbytes per logical unit
3-6
53,790 = 316.41
34 X 5
unit
Sectors per the partial unit are calculated as
follows:
185 X 34 X 5
= 31,450 sectors per partial
logical unit.
Partitioning Program
The name of the program is DMXXD, where XX
is the revision number of the program.
Figure 3-2 is a flow diagram of the program. The
statements in quotes are program prompts. The
pentagonoid symbols with a letter and number, such
as "AI," are reference points for breaks in the flow.
The "A" designation refers to the first page
(Format) and the "B" designations refer to the
second page (Change Parameters). The following
descriptions refer to the first (Format) page of· the
diagrams.
The following paragraphs may contain values
enclosed in "<>." These values are the default
values and may be selected by pressing the
: RETURN key. To assist in determining whether a
parameter needs to be changed, the current values
are displayed enclosed in "()." The program prompts
and displays are indicated in capital letters.
When the program is initialized the following display will appear on the terminal:
DILOG'S UNIVERSAL FIRMWARE AND
DIAGNOSTIC PROGRAM VERIFIES PROPER FUNCTIONING OF THE DILOG RK06/
RK07 EMULATING DISC CONTROLLER
AND FORMATS THE DISC TO YOUR
SPECIFICATIONS.
YOUR DEFAULT PARAMETERS ARE:
SECTORS_
HEADS_
CYLINDERS_
ALTERNATES _
SIZE OF LOGICAL UNIT (RECORDS)_
The parameters displayed are calculated for the
efficiency of most applications. The units of
measure are as follows: sectors/track; heads/drive;
cylinders/drive; alternates/drive; and the size of
logical unit in sectors/logical unit.
The next display will be:
***************************************
******: RESTART ADDRESS IS 2000 r*****
*******~ "X RESTARTS PROGRAM Jr******
***** "c RESTARTS CURRENT TEST ****
***************************************
To restart, press the CTRL and X keys at the
same time, or CTRL and C.
The next query is:
ARE YOU RUNNING THE DIAGNOSTIC VIA
A CRT?
If the answer is NO, the CRT will not display the
current cylinder address during the test program.
The next prompt is:
ENTER THE NUMBER OF DRIVES <1>
Enter 1 or 2. If 1 is entered, the next queries will
refer only to Drive O. If 2 drives are selected, the
program will prompt for Drive 0 and Drive 1.
The next displays will be:
ENTER DM DEVICE ADDRESS <777440> ?
ENTER DM INTERRUPT VECTOR
<000210> ?
Enter the proper device address and interrupt
vector. The address and interrupt vector are factory
set unless the user requested an alternate address or
vector (see Section 2).
The next question will be:
LSI (Y OR N)?
Answer Yes.
The menu of drives will appear next, with the
following:
***** DRIVE 0 *****
ENTER NUMBER CORRESPONDING TO
DISC DRIVE
N
= NEXT PAGE
P = PREVIOUS PAGE E
ENTER DRIVE PARAMETERS
=
ENTER>
From the menu, the appropriate drive may be
selected. If E is pressed, the program will prompt
for drives not listed in the menu or will prompt to
change parameters in case of conflicts in
constraints. If the drive selected is not listed in the
menu, the program will prompt:
DOES DRIVE 0 HAVE REMOVABLE
MEDIA?
IS DRIVE O'S SPEED GREATER THAN 10
MHZ?
CHANGE DRIVE 0 INTERLACE FACTOR
(X:1)?
Enter the appropriate response (available from
the drive manufacturer's manual). If the answer to
the interlace factor question is Yes, the following
will be displayed:
SELECT ONE OF THE FOLLOWING INTERLACE FACTORS
(2) 2:1
(3) 3:1
(4) 4:1
(5) 5:1
(6) 6:1
3-7
SET CRT
SWITCH
DISPLAY
MENU
CLEAR MENU
SWITCH
SET
HARDCOPY
SWITCH
SET MENU
SWITCH
SET
REMOVABLE
MEDIA SWITCH
SET FOR
1 DRIVE
GET
PARAMETERS
FOR SELECTED
DRIVE
SET FOR
2 DRIVES
ENTER
INTERLACE
"ENTER DEVICE
ADDRESS OR
RETURN FOR
DEFAULT"
2) 2:1
3) 3:1
4) 4:1
"ENTER INTER·
RUPT VECTOR
OR RETURN
FOR DEFAULT"'
GO TO CHANGE
PARAMETERS
'TO OR FROM OPPOSITE PAGE
Figure 3-2(A). Universal Formatting
3-8
SET HIGH SPEED
DRIVE SWITCH
"ENTER
1) RK06
2) RK07"
ENTER NEW
VALUE
ENTER NEW
VALUE
ENTER NEW
VALUE
ENTER NEW
VALUE
ENTER NEW
VALUE
ENTER NEW
VALUE
N
DISPLAY EXTRA
CYLINDER MESSAGE
AND COLLECT
OPERATOR
RESPONSE
'TO OR FROM OPPOSITE PAGE
Figure 3-2(B). Universal Formatting-Change Parameters
3-9
PLEASE ENTER THE CORRESPONDING
NUMBER>
Enter the desired interlace factor (2, 3, 4, 5, or 6).
An interlace of 4: 1 is recommended for drives with
speeds greater than 10 MHz, and the default will
automatically be set at 4:1 if Yes was answered to
the query to change the interlace factor.
Note
The program responds with the minimum
number of inquiries; for example, if a drive is
selected from the menu, the program will not
prompt for the number of sectors, heads and
cylinders, because these responses are
predetermined.
If a drive is selected from the menu, the next
display will be:
DO YOU WISH TO CHANGE FORMAT
PARAMETERS?
Note
The format parameters are those last
entered. Each time there is a change, the
program will retain that change.
If the response is No, the next display will show
the configuration. An example of RK07 is as follows:
DISC SUBSYSTEM CONFIGURATION
LOGICAL
UNIT
DMO
DMI
DM2
DM3
DM4
DM5
DM6
DM7
PHYSICAL
RECORD
DRIVE MEGABYTES
SIZE
0
0
0
0
1
1
1
1
27.59
27.59
27.59
25.82
27.59
27.59
27.59
25.82
53900
53900
53900
50435
53900
53900
53900
50435
PHYSICAL DRIVE 0 HAS 44 ALTERNATE
TRACKS
PHYSICAL DRIVE 1 HAS 44 ALTERNATE
TRACKS
ARE YOU SURE?
If the answer to this prompt is No, the program
will return to the beginning. If the answer is Yes,
the program will continue.
The following descriptions refer to the second
(Change Parameters) page of the diagram.
If the answer is Yes to the prompt:
DO YOU WISH TO CHANGE FORMAT
PARAMETERS?
the next prompt will be:
3-10
CHANGE NUMBER OF SECTORS (XX)?
CHANGE NUMBER OF HEADS (XX)?
CHANGE NUMBER OF CYLINDERS (XXX)?
These prompts are for adding a drive that is not
on the menu. The values (after HOW MANY?) to be
entered are in the drive manufacturer's manual. The
next prompt of change parameters is for drives
which are or are not on the menu:
CHANGE NUMBER OF ALTERNATES (XX)?
The standard number of alternates selected is 4. If
a CMD drive is selected, there will be no further
questions. If Yes, HOW MANY? will appear. The
next query is:
CHANGE TYPE OF PARTITION (XXXXXX)?
If the answer is Yes, the following display will
appear:
SELECT ONE OF THE FOLLOWING TYPES
OF PARTITIONING
I-Head partition
(2) 2-Head partition
(3) Vertical partition
(1)
PLEASE ENTER THE CORRESPONDING
NUMBER>
Enter the number corresponding to the type of
partition desired. If I-Head or 2-Head partitioning
is selected there will be no further queries.
Next to appear is:
STANDARD SIZE UNITS?
If Yes, the program will prompt with selection of
RK07 or RK06. If RK07 is selected, the program
will divide the record size into RK07 units, and the
remaining records will be an RK06 unit. Standard
sizes are shown in Table 3-1. After selection of
standard units, the next message will be:
AFTER CALCULATING STANDARD SIZE
UNITS ON DRIVE 0, YOU HAVE _ _ __
CYLINDERS NOT YET ALLOCATED (_ _
MEGABYTES).
IF YOU WOULD LIKE, I COULD CREATE
ANOTHER UNIT, WHICH WILL BE
SMALLER THAN YOUR STANDARD SIZE
UNITS, OR I COULD ALLOCATE THE
CYLINDERS AS ALTERNATES.
PLEASE ENTER THE NUMBER OF
CYLINDERS YOU WOULD LIKE ME TO
ALLOCATE AS ALTERNATES, ANY REMAINDER WILL BE ALLOCATED AS
ANOTHER UNIT.
If the standard number of alternates previously
selected is adequate (default is 4), enter O.
The next display will be:
CHANGE SIZE OF LOGICAL UNIT
(RECORDS) (XXXXX)?
CHANGE NUMBER OF LOGICAL UNITS
(X)?
The program will pause for a response after each
question. If Yes is answered to either of the above
questions, the system will respond with "HOW
MANY?" Enter the desired value and the system
will respond with the next question. The user may
change the size of the logical units or the number of
logical units, but not both.
If two drives were selected, the program will
repeat the above sequence for the second drive,
beginning with:
***** DRIVE 1 *****
ENTER NUMBER CORRESPONDING TO
DISK DRIVE
N=NEXT PAGE P=PREVIOUS PAGE
E=ENTER DRIVE PARAMETERS
If the constraints are not violated, the Disc Subsystem Configuration and ARE YOU SURE? will
appear. If the subsystem constraints have been
violated, a message will be displayed explaining the
violation. Any violations must be corrected in order
to con~inue. Some possible errors are:
1)
2)
3)
4)
5)
More than 8 logical units on the subsystem
More than 8 heads with I-head partition
More than 16 heads with 2-head partition
Odd number of heads with 2-head partition
Maximum logical unit size exceeded
To resolve this conflict, the Change Format
Parameters option may be used to change the
number of logical units on Drive O. To provide logical units of equal size on both drives, the number of
logical units may be changed to 4 on each drive.
Restart the current address with "c, repeat the
sequence above up to the question CHANGE
NUMBER OF LOGICAL UNITS?, and answer Y.
When HOW MANY? appears, answer 4. Repeat this
sequence for Drive 1.
Examples of errors on a single drive when changing the type of partition are as follows:
FORMAT PARAMETER CONFLICTS
DRIVE 0
MAXIMUM NUMBER OF HEADS WITH
I-HEAD PARTITION IS 8
or
FORMAT PARAMETER CONFLICTS
DRIVE 1
MAXIMUM NUMBER OF HEADS WITH
2-HEAD PARTITION IS 16
or
FORMAT PARAMETER CONFLICTS
DRIVE 0
MAXIMUM NUMBER OF HEADS MUST BE
AN EVEN NUMBER WITH 2-HEAD
PARTITION
Examples of errors on a single drive when changing the size of the logical units is as follows:
FORMAT PARAMETER CONFLICTS
DRIVE 0
LOG ICAL UNIT SIZE IS 270, 720
MAXIMUM LOGICAL UNIT SIZE IS 270, 336
or
FORMAT PARAMETER CONFLICTS
DRIVE 0
LOGICAL UNIT SIZE IS BIGGER THAN THE
DISC
The algorithm for mapping, that is, what the controller should map, is as follows:
Record Number
Sector/Cylinder
Remainder (1)
Sector/Track
= Correct Cylinder Address
+ Remainder (1)
= Correct Head Address
+ Remainder (2)
Remainder (2) = Sector Address
A mapping error is displayed during the Random
Read test as follows:
*****MAPPING ERROR *****
RECORD NUMBER = XXX
SECTOR/CYLINDER = XXX
SECTOR/TRACK = XXX
DRIVE NUMBER = XXX
CORRECT ADDRESS
CYLINDER = XXX
HEAD = XXX
SECTOR = XXX
CONTROLLER ADDRESS
CYLINDER = XXX
HEAD = XXX
SECTOR = XXX
If the response to "ARE YOU SURE" is Yes, the
program will begin the Diagnostic Test Program.
3-11
Diagnostic Test Program
To begin the Diagnostic Test Program, the following display will appear:
*******************************************
SPACE BAR WILL EXIT CONTROLLER TEST
2.
3.
*******************************************
As tests are performed, the system will indicate
that activity by displaying:
TESTING
TESTING
TESTING
TESTING
CONTROLLER REGISTERS
DATA BUFFERS
DMA
ECC LOGIC
The next display will be the switches:
LOCATION ON
B-17
OFF
8
7
6
5
4
3
2
1
SWITCH
DESCRIPTION:
6-8 LAST LOGICAL
UNIT
5 ECC SWITCH
4 BOOTSTRAP
ENABLE
1-3 LOGICAL UNIT
CROSSOVER
DEFINITIONS:
LIU CROSSOVER: 1ST LOGICAL UNIT ON 2ND
DRIVE
BOOTSTRAP ENABLE: ON = ENABLED, OFF =
DISABLED
ECC SWITCH: ON = CONTROLLER MODE, OFF =
SOFTW ARE MODE
LAST.L/U: LAST LOGICAL UNIT ON SUBSYSTEM
SET SWITCHES 1-3 TO A BINARY WEIGHTED
VALUE OF X.
SET SWITCHES 6-8 TO A BINARY WEIGHTED
VALUE OF X.
USE (C) TO CONTINUE
If the switches are set incorrectly, the message
will repeat. Switch settings are described in Section
2. If the switches are set correctly, the program will
skip to "Test Disc Drive."
Pressing the SPACE bar will cause the diagnostic
to halt the current test and proceed to the next one.
If any of the tests fail, an error message will be displayed, followed by:
USE (C) TO CONTINUE
USE (0) TO TRANSFER TO ODT
USE (L) TO REBOOT YOUR SYSTEM
The format/test program contains the following:
1. TEST CONTROLLER
A. Registers
B. Data Buffer
3-12
4.
5.
6.
7.
8.
C. DMA
D. ECC
TEST DISC DRIVE
A. Disc Ready
B. Disc Restore (seek to cylinder 0)
FORMAT
A. Write Headers
B. Read Headers
C. Write Data Test Pattern
D. Read Data Test Pattern
SEQUENTIAL READ
SELECTED READ
RANDOM SEEK, READ
RANDOM SEEK, WRITE, READ, AND
COMPARE
ASSIGN ALTERNATE TRACK
Test Controller
The program will automatically test the controller
registers and data buffer. The program will only
display error messages during this test; the display
will be:
DATA BUFFER ERROR
or the mnemonics of the controller registers and the
location and contents (in Octal). The display of the
registers is followed by a 4·line message to aid in
isolating the specific problem.
Note
Whenever an error occurs and the registers
are displayed, an audio alarm signal is generated to notify the operator.
The 4-line message is as follows:
DISC ADDRESS _ _
HEAD _ _ CYLINDER _ _
TYPE OF COMMAND _ _
CONTROL STATUS ERROR _ _
DRIVE STATUS _ _
"DISC" lists the sector, head and cylinder (in
decimal) where the error occurred. An example of
Type of Command is Read Data Command. An
example of Control Status is Seek Error.
The ECC logic test is as follows: The program
selects whether a correctable or noncorrectable error
is to be programmed; then the program creates an
error; writes the data with an error to the controller;
reads to memory; then the program decides whether
the error is noncorrectable or correctable.
If noncorrectable, the program checks to ensure
an error has been returned by the controller.
If correctable, the program checks to make sure
there has been no error returned by the controller,
and checks to ensure the error was corrected in the
proper manner. If this test fails, the message is one
or more of the following:
CONTROLLER INDICATES CORRECTABLE
ERROR
CONTROLLER INDICATES NONCORRECTABLE ERROR
ERROR BURST IS CORRECTABLE
ERROR BURST IS NONCORRECTABLE
ERROR BURST WAS NOT CORRECTED
The space bar (SP) is used to exit from this test.
The program will next display:
USE C TO CONTINUE
USE 0 TO TRANSFER TO ODT
USE L TO REBOOT YOUR SYSTEM
"C" is used to continue the test. "0" is used for
aDT (on-line debugging technique). "L" is used to
initiate the system bootstrap.
Test Disc Drive
After the controller test is performed, the program will automatically test the drive for ready and
restore. The disc address is not displayed during
this test. If the disc will not restore, the program
will display the register for cylinder O.
Format
If all tests are successful, the program will display
the proper switch settings for the specified configuration, followed by:
USE (C) TO CONTINUE
The program will next display:
AUTOMATICALLY ASSIGN ALTERNATES?
If the response to this question is Yes, the
diagnostic program will assign an alternate cylinder
without waiting for operator approval when a media
flaw is detected during formatting.
The program will then ask what part of the system to format. Some of these questions will be suppressed if the response is Yes to a previous question.
The operator may either select logical units sequentially or select one or more specific logical units
to be formatted. Program messages are presented
for formatting in logical unit number sequence:
FORMAT
FORMAT
FORMAT
FORMAT
O?
FORMAT
I? ,
ENTIRE SUBSYSTEM?
ENTIRE DRIVE O?
ENTIRE DRIVE I?
ALTERNATE CYLINDERS DRIVE
ALTERNATE CYLINDERS DRIVE
FORMAT DMO?
FORMAT DM1?
FORMAT DM2?
FORMAT DM3?
FORMAT DM4?
FORMAT DM5?
FORMAT DM6?
FORMAT DM7?
Note
Before any write operation, the program will
display ARE YOU SURE? This aids the
operator in preventing reformatting of a
previously formatted logical unit {possibly
destroying good data}.
During formatting, the following messages will
appear sequentially:
WRITING HEADERS
CURRENT CYLINDER ADDRESS - - - READING HEADERS
CURRENT CYLINDER ADDRESS - - - WRITING DATA TEST PATTERN - - - CURRENT CYLINDER ADDRESS - - - READING DATA TEST PATTERN - - - CURRENT CYLINDER ADDRESS - - - When reading and writing headers, the program
will display the cylinder addresses sequentially. The
test pattern tests are also sequentially selected, and
the cylinder address displayed will correspond to
the current address being read.
Note
During formatting and testing, the current
cylinder address will appear only if the
diagnostic test program is being run on a
CRT.
After each logical unit is formatted, the display
will be:
DM _
FORMAT AND VERIFICATION
COMPLETE
If an error occurs during formatting, a message will
be displayed. If a media flaw is detected but automatic alternate assignment was not selected, the
program will display:
ASSIGN ALTERNATE CYLINDER?
A Yes response will map out the detected media
flaw.
When formatting is complete, the diagnostic program will proceed to the Sequential Read portion of
the test.
3-13
Sequential Read
For this test, the display will be:
SEQUENTIAL READ (ALL CYLINDERS AND
HEADS)?
If the response is Yes, the current cylinder
address is displayed as each cylinder is read. If an
error is detected, the register contents and location
are displayed with the 4-line identification message,
and the following:
ASSIGN ALTERNATE TRACK FOR
DEFECTIVE TRACK?
If no alternates (spares) are available, the following will be displayed:
NO ALTERNATE CYLINDER AVAILABLE
When marking or assigning alternate tracks, the
following error messages may occur:
TRACK HAS ALREADY BEEN MARKED
DEFECTIVE
TRACK HAS ALREADY BEEN MARKED
ALTERNATE
Selected Read
For this test, the display will be:
This check also ensures controller mapping is correct. The desired address and the actual address
will be displayed with the drive's physical
characteristics.
Random Seek/Read, Write Data, Compare Test
For this test, the display will be:
RANDOM SEEK/READ, WRITE DATA,
COMPARE TEST?
If the response is No, each logical unit will appear
in sequence until the response is Yes or the program
reaches the last logical unit.
DMO?
DM1?
DM2?
DM3?
DM4?
DM5?
DM6?
DM7?
This test selects a random cylinder address and
random sector address and writes five sectors (2560
bytes) of random data. The data written is then read
into CPU memory and compared for read errors.
This test allows logical units to be tested. The terminal keyboard space bar (SP) is used to exit from
this test.
This test ensures that the controller is executing
the Write Check command correctly and that the
controller is zero-filling the disc correctly.
The next prompt allows mapping out known bad
tracks on the disc.
READ DMO? (Y OR N)?
Assign Alternate Track
If the response is No, the next logical unit will be
displayed. If the response is Yes, the current
cylinder' address is displayed and each cylinder is
read. If an error is detected, the register contents
and location are displayed with the 4-line identification message. The ASSIGN ALTERNATE TRACK
message appears, and error messages if the track
has been marked DEFECTIVE or ALTERNATE.
Random Seek, Read
For this test, the display will be:
RANDOM SEEK, READ OF DRIVE (ALL
CYLINDERS AND HEADS)?
This test selects a random cylinder, logical unit,
and a sector address within the cylinder. The test
then reads data and tests for errors. All logical units
are used in this test. Alternate cylinders cannot be
assigned during this test. The terminal keyboard
space (SP) bar is used to exit this test.
If an error is detected, the register content and
locations are displayed with the 4-line identification
message.
3-14
This test may be used if the disc drive manufacturer provides a map describing defective tracks.
The message is:
ASSIGN ALTERNATE TRACK FOR
DEFECTIVE TRACK?
If the response is No, the program will revert to:
USE R TO REPEAT
USE 0 TO TRANSFER TO ODT
USE L TO REBOOT YOUR SYSTEM
If the response is Yes, the display will be:
PHYSICAL DRIVE (0 or I)?
(only if two drives are present)
CYLINDER ADDRESS (0 TO XXXX)?
Enter the cylinder address, in decimal, of the
defective track. If the cylinder address entered is incorrect, the message will be repeated.
The next message will be:
HEAD ADDRESS
(0
TO XXX)?
Enter the head address, in decimal, of the defective track. If the head address entered is incorrect,
the message will be repeated.
The next message will be:
MAP OUT
CYLINDER XXXX HEAD XX
ARE YOU SURE?
If No, the program will repeat the first message of
this test. If Yes, an alternate cylinder is assigned
and the message is:
ALTERNATE CYLINDER ASSIGNED
Other messages to appear may be:
TRACK ALREADY MARKED DEFECTIVE
or
TRACK ALREADY MARKED ALTERNATE
The program will then repeat the first message of
this test.
The Diagnostic Test Program ends with the
display:
USE (R) TO REPEAT
USE (0) TO TRANSFER TO ODT
USE (L) TO REBOOT YOUR SYSTEM
3-15
SECTION 4
PROGRAMMING
Table 4-1. Function Codes
PROGRAMMING DEFINITIONS
Function-The expected activity of the disc system (write, seek, read, etc.)
Command-To initiate a function (halt, clear, go,
etc.)
Instruction-One or more orders executed in a
prescribed sequence that causes a function to be
performed.
Address-The binary code placed in the BDALO15 lines by the bus master to select a register in a
slave device. Note memory other than computer
internal memory, i.e., peripheral device registers,
the upper 4K (2S-32K) address space is used.
Register-An associated group of memory elements that react to a single address and store information (status, control, data) for use by other
assemblies of the total computer system. Classically, registers have been made up of groups of flipflops. More and more often registers are the contents of addressed locations in solid-state or core
memory.
DISC· CONTROLLER FUNCTIONS
The disc controller performs 14 functions. A function is initiated by a GO command after the processor has issued a series of instructions that store
function-control information into controller registers. To accept a command and perform a function,
the controller must be properly addressed and the
disc drive(s) must be powered up, be at operational
speed, and be ready.
The functions performed by the controller are
established by bits 01, 02, 03 and 04 of the control
status register (RKCS1). The function and bit codings are given in Table 4-1. Descriptions of the functions are given in the following paragraphs.
Note that the controller automatically performs
certain functions during each command. For
example, the controller always performs the following steps:
1.
Decodes instruction
2.
Selects drive
3. Acknowledges pack (tests for RK06/RK07
drive type)
Bit
4321
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Command
SELECT DRIVE
PACK ACKNOWLEDGE (NO OP)
DRIVE CLEAR (RESET ATTENTION STATUS)
UNLOAD (NO OP)
START SPINDLE (NO OP)
RECALIBRATE (RESTORE DRIVE AND RESET
FAULT)
OFFSET
SEEK (SET ATTENTION STATUS)
READ DATA
WRITE DATA
READ HEADERS (1 TRACK OF HEADERS)
WRITE HEADERS (FORMAT TRACK)
WRITE CHECK
4. Executes one of the remaining nine functions
Select Drive
Performed automatically as part of all functions
related to drive selection (connects drive).
Pack Acknowledge
Performed automatically to verify emulation
(RK06/RK07) as part of all functions related to drive
selection. Controls bit os in RKDS.
Drive Clear
Resets attention status in RKAS/OF.
Recalibrate
Relocates the heads to cylinder zero and clears the
cylinder address register. Also resets all fault conditions. Sets Attention bit in RKASIOF.
Offset
Sets drive attention bit in RKAS/OF.
Seek
Performed automatically as part of all functions
-related to drive selection. Sets Attention bit in
4-1
RKAS/OF. During Overlapped Seeks, loads cylinder
address into RKMR3 (Maintenance Register 3).
Read Data
Causes the following sequence to be executed: A
Seek to the cylinder in RKDC is performed. Headers
are read and compared with the desired disc address
until the correct sector is found. Transfer of data
through the data buffer to memory is initiated.
When the sector data transfer is complete, the EPC
logic is checked to ensure that the data read from
the disc was error-free. If a data error occurred, the
ECC correction logic is initiated to determine
whether the error is correctable; when finished, the
command is terminated to allow software or hardware (as selected) to apply the correction information. Assuming no data errors, the word count in
RKWC is checked; if non-zero, the data transfer
operation is repeated into the next sector. The word
count is checked at the end of each sector until it
reaches zero, at which time the command is terminated by setting the Ready bit.
Write Data
Causes the following sequence to be executed: A
Seek to the cylinder in RKDC is performed. Transfer
of data from memory to the data buffer is begun,
and headers are read and compared with the desired
disc address until the correct sector is found. Preamble, Data (256 words), and ECC bits (56) are
written on the disc. If the word count in RKWC goes
to zero during the sector, the rest of the sector is
zero-filled. After the sector transfer, the word count
in RKWC is checked and, if non-zero, the data
transfer operation is continued into the next sector.
The word count in RKWC is checked at the end of
each sector and, when it equals zero, the command is
terminated by setting the Ready bit.
Read Headers
time, 5 header words and a 32-bit ECC are written
after each sector pulse. When Index is next
detected, the command is terminated and the Ready
bit is set.
Note
All five words and the ECC code are prepared by the format routine (software) and
treated as data by the controller. Only one
complete track can be formatted at a time.
Write Check
Causes the following sequence to be executed: A
Seek to the cylinder in RKDC is performed. The
selected drive provides data as in a Read command,
and data is obtained from memory as in a Write
command. The data are compared on a word-forword basis until the word count reaches zero or until
a failure to compare occurs. If the data fails to compare, the command is terminated immediately.
Mapping and Map Override
In a typical DEC disc subsystem, the method by
which the disc drive finds the proper location to read
data from or write data to is as follows:
1. The application software program running
under the operating system sends a record
number to the disc device driver software.
2.
3. The driver then sends this information to
dedicated hardware registers on the disc
controller.
4. The controller in turn passes these
parameters on to the disc drive over I/O
interface cables.
5.
A Seek to the cylinder in RKDC is performed.
This function causes the controller to read all
headers starting at the Index mark. Each 5-word
header is read in the order in which it appears on the
disc. If an ECC error is detected in the header, the
HRE bit of RKER is set.
Write Headers
A Seek to the cylinder in RKDC is performed. The
controller then waits untillndex is detected. When
detected, zeros are written until Index is again
detected. This "cleans" the track of potential
spurious signals. After Index is detected a second
4-2
The device driver converts this record
number into head, sector and cylinder
numbers.
The drive interprets these signals and
activates electronics and electromechanics
enabling it to seek to the exact physicallocation where information will be recorded or
retrieved.
In a DEC subsystem which includes a DILOG
controller, the above procedure is the same up to
step 4. But instead of passing on the head, sector
and cylinder information to the drive, the DILOG
controller first takes that information sent by the
device driver software and reconverts it to the
original record number. Then by invoking a special
algorithm, the controller develops a new head,
sector and cylinder number. This is called mapping
and it is a necessary procedure whenever the disc
drive that is attached to the CPU does not contain
the same specifications as the drive supplied by the
CPU manufacturer.
Map Override is nothing more than a special
operating mode of the DILOG disc controller which
allows it to transfer the disc address to the drive as
described in steps 1-5, bypassing the DILOG
mapping procedure. Typically, this feature is only
used in an environment in which the user requires
the entire disc drive to be formatted as one ~arge
logical unit. In other words, one logical unit would
equal one physical unit. For example, consider a
subsystem consisting of a DQ235 and a Fujitsu
Eagle 474 Mbyte drive. Obviously, the controller is
not a good match for a drive that large, considering
that one RK07 logical unit equals 27.6 Mbytes. If,
however, the user had a definite requirement for
running an RK07 instruction set, he could invoke
Map Override and format the Eagle as one very
large RK07. One requirement is that the device
driver software has to be modified. .
ENABLE REAL TIME CLOCK CONTROL
The real time clock line is from the 60-cycle power
supply in the LSI. The Operating System uses the
clock for time and date. The line on the Q Bus,
BEVNT, can be disabled by a switch on the controller, which when ON enables real time clock control or when OFF disables control. The register,
address 777 546, is shown at the end of this section.
REGISTERS
A summary of the registers is shown in Figure 4-1,
followed by a description of each register.
4-3
LSB
MSB
BIT POSITION
1
15
I
14
13
12
11
10
06
07
08
09
05
04
03
WORD COUNT
777 442 (RKWC)
WORD COUNT
BUS ADDRESS
777 444 (RKBA)
BUS ADDRESS
DISC ADDRESS
777 446 (RKDA)
DRIVE STATUS
777 452 (RKDS)
01 I 00
FUNCTION
CONTROL AND STATUS 1
777440 (RKCS1)
CONTROL AND STATUS 2
777450 (RKCS2)
02
SECTOR ADDRESS
HEAD ADDRESS
0
o
IWCEI
I I I I I I
SC
0
INEDINEMI PE IMDSI
0
PIP
WP
SPARES
0
~~ I
1
I
I
SCL IIBA
I
I I I I I
DR
OS
SE
0
OS
0
OF
0
0
I
1
ERROR REGISTER
777 454 (RKER)
ATTENTION SUMMARY AND
OFFSET 777 456 (RKAS/OF)
DESIRED CYLINDER
ADDRESS 777 460 (RKDC)
ATTENTION
DIAGNOSTIC
MODE
EXTENDED MEMORY
ADDRESS 777 462 (RKXMA)
I ON I OP I
BITS 16-21
DATA BUFFER
MAINTENANCE 1
777 466 (RKMR1)
NOT USED
NOT USED
FIRMWARE
MODEL
ERROR POSITION
ECC PATTERN
777 472 (RKECPT)
NOT USED
ERROR PATTERN
MAINTENANCE 2
777 474 (RKMR2)
HEAD MAPPED
SECTOR MAPPED
MAINTENANCE 3
777476 (RKMR3)
NOT USED
CYLINDER MAPPED
ENABLE REAL TIME CLOCK
CONTROL 777 546 (RKERTC)
Figure 4-1. Controller Register Configuration
4-4
NOT USED
CYLINDER ADDRESS
NOT USED
READ/WRITE BUFFER
777 464 (RKDB)
ECC POSITION
777470 (RKECPS)
NOT USED
I
CONTROL AND STATUS REGISTER 1
777 440 (RKCSl)
15
14
13
ERR
RST
01
0
12
11
GAP RBA
10
09
06/
07
X MEM
08
07
06
05
CR
IE
0
04
01
FUNCTION
00
GO
I
GO
'- SPARE-ALWAYS 0
--INTERRUPT ENABLE
--CONTROLLER READY
' - EXTENDED MEMORY (16-17)
~ RK06/RK07 (1 = RK07)
' - RELOAD BUS ADDRESS
I - LONG/SHORT GAP
FMTIDATA COMMANDS
I-SPARE-ALWAYS 0
--DRIVE INTERRUPT
L - COMBINED ERROR/RESET
BIT(S)
DEFINITION
00
GO-When set, this bit causes programmed commands (function codes) to be executed. When set,
only two other bits can be set (except in the diagnostic mode); they are: Bit 15, CCLR, in RKCS1
and Bit 05, SCLR, in RKCS2.
01-04
FUNCTION CODE-
BIT
4321
O(GO)
OCTAL COMMAND
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1
1
1
1
1
1
1
1
1
1
1
1
1
01
03
05
07
11
13
15
17
21
23
25
27
31
SELECT DRIVE
PACK ACKNOWLEDGE (NO OPERATION)
DRIVE CLEAR (RESET ATTENTION STATUS)
UNLOAD (NO OPERATION)
START SPINDLE (NO OPERATION)
RECALIBRATE (RESTORE DRIVE AND RESET FAULT)
OFFSET
SEEK (SET ATTENTION STATUS)
READ DATA
WRITE DATA
READ HEADERS (1 TRACK OF HEADERS)
WRITE HEADERS (FORMAT TRACK)
WRITE CHECK
05
SPARE-ALWAYS 0
06
INTERRUPT ENABLE-When this bit is set, the controller is allowed to interrupt the processor
under any of the following conditions:
• When the Controller Ready bit (bit 07 in RKCS1) is set upon completion of a command.
• When any drive sets an associated Attention flag (ATN7-ATNO) in RKAS/OF, and the Controller
Ready bit is set.
• When the controller or any drive indicates the presence of an error by setting the ERR/RST bit in
RKCS1.
4-5
In addition, via program control, an interrupt can be forced by the simultaneous setting of the IE
and RDY bits in RKCSl. The IE bit can be reset via program control as well as by conventional
initialization (lNIT, CCLR, SCLR).
07
CONTROLLER READY -This is a read-only bit. It is set via conventional initialization (lNIT,
CCLR, SCLR) upon completion of a controller command, or when an error condition is detected. The
RDY bit is reset when the GO bit (bit 00 in RKCSl) is set.
08-09
EXTENDED MEMORY BUS ADDRESS-These bits constitute an extension of the 16-bit Bus
Address register (RKBA), which contains the memory address for the current data transfer.
10
RK06/RK07 SELECT-When set, this bit selects RK07. When reset, RK06 is selected.
11
RELOAD BUS ADDRESS-When set, this read/write bit reloads the original bus address after
each sector time.
*12
GAP CONTROL-In the Write Header command (or Write Format) bit 12 will direct the controller
to generate a long gap (24 bytes) or a short gap (16 bytes) between sector and header.
Bit 12 1
= Short Gap
o = Long Gap
In the Write Data or Read Data command bit 12 will direct the controller to write or read a sector
data field (512 bytes) with or without ECC (7 bytes) to or from memory.
Bit 12 1
= 512 Bytes + 7 Bytes
DATA
ECC
o = 512 Bytes
13
SPARE-ALWAYS 0
14
DRIVE INTERRUPT (SEEK OR RESTORE)-This bit is set during a Seek or Restore operation
or when any Attention bit is set in the RKAS/OF register. This bit is reset by Bus Initialize (IN IT),
Subsystem Clear (SCLR) or by Drive Clear commands asserting attention.
15
COMBINED ERROR/RESET-When reading bit 15 via programmed control, a zero indicates an
operation complete with good status; a one indicates an operation complete with an error.
*NOTE: When bit 12 is set, the Word Count register should be set for 520 bytes.
WORD COUNT REGISTER
777 442 (RKWC)
15
00
WORD COUNT
This is a read/write register. The bits of this
register contain the 2' s complement of the total
number of words to be transferred during a Read,
Write, or Write Check operation. The register is
incremented by one after' each transfer. When the
4-6
register overflows (all we bits go to zero), the
transfer is complete and controller action is terminated at the end of the present disc sector. Only the
number of words specified in the RKWC are transferred. Cleared by INIT or RESET functions.
BUS ADDRESS REGISTER
777 444 (RKBA)
00
15
BUS ADDRESS
The Bus Address register is initially loaded with
the low-order sixteen bits of the bus address that
reflects the main memory start location for a data
transfer. With the low-order bit (bit 00) always
forced to zero, the Bus Address register bits are
combined with bits 09 and OS of the RKSCI register
(BAI7, BAI6) to form a complete even-numbered,
IS-bit memory address. Following each data transfer bus cycle, the Bus Address register is incremented to select the next even-numbered location.
DISC ADDRESS (TRACK AND SECTOR) REGISTER
777446 (RKDA)
08
15
HEAD ADDRESS
07
00
SECTOR ADDRESS
BIT(S)
DEFINITION
00-04
(00-07)
SECTOR ADDRESS-In the emulation mode, bits 00-04 select up to 20 sectors of 16-bit words. In
the map override mode, bits 15, 14, 13, and 12, in the Desired Cylinder register 777460, are set to 1,
0, 0, and 0, respectively. The Sector Address then uses bits 00-07.
08-10
(08-15)
HEAD (TRACK) ADDRESS-In the emulator mode, bits OS-10 select heads 0,1, or 2. In the map
override mode, bits 15, 14, 13, and 12 in the Desired Cylinder Address register 777 460, are set to 1,
0,0, and 0, respectively. The Head (TRACK) Address then uses bits OS-I5.
4-7
CONTROL AND STATUS REGISTER 2 .
777 450 (RKCS2)
15
14
13
12
11
10
09
08
07
06
05
04
03
02
00
DRIVE SELECT
SPARE-ALWAYS 0
INHIBIT BUS ADDRESS INCREMENT
SYSTEM CLEAR
.' INPUT READY (ALWAYS 1)
OUTPUT READY (ALWAYS 0)
SPARE-ALWAYS 0
MULTIPLE DRIVES SELECTED
PROGRAM ERROR
NONEXISTENT MEMORY
NONEXISTENT DRIVE
SPARE-ALWAYS 0
WRITE CHECK ERROR
SPARE-ALWAYS 0
BIT(S)
00-02
DEFINITION
DRIVE SELECT-These bits specify the drive to be selected.
03
SPARE-ALWAYS 0
04
INHIBIT BUS ADDRESS INCREMENT-When this bit is set, the Bus Address register is prevented from incrementing during data transfers.
05
SYSTEM CLEAR-When this bit is set, the controller and drive are reset.
06
INPUT READY-ALWAYS 1
07
OUTPUT READY-ALWAYS 0
08
SPARE-ALWAYS 0
*09
MULTIPLE DRIVES SELECTED-This bit is set when more than one drive has been selected at
the same time. This bit can only be cleared by INIT or SCLR.
*10
PROGRAM ERROR-This read-only error bit is set if any controller register is written (CCLR and
SCLR excluded) while the GO bit in RKCSI is set.
*11
NONEXISTENT MEMORY -This read-only error bit is set when the controller attempts to
. execute a bus cycle and SSYN is not returned within the specified time period.
*12
NONEXISTENT DRIVE-When set, this read-only error bit indicates that Select Acknowledge
(SACK) has not been asserted by the selected drive in response to a Select Enable sent to the drive.
*13
SPARE-ALWAYS 0
*14
WRITE CHECK ERROR-When set, this read-only bit indicates that a data word read from the
disc (during a Write Check command) did not compare with the data word in main memory. If a
Write Check error is detected and the IBA bit (bit 04 of RKCS2) is cleared, the Bus Address
register will contain the memory address of the mis-matched word plus two or plus four.
15
SPARE-ALWAYS 0
*Causes bit 15 in RKCSI to set.
4-8
DRIVE STATUS REGISTER
777 452 (RKDS) Read Only Register
15
14
13
12
11
1
SC
PIP
0
WP
10
09
08
07
06
05
04
03
02
01
SPARES
061
07
DR
OS
SE
0
OF
0
o
00
LL
SPARE-ALWAYS 1
SPARE-ALWAYS 0
- SPARE-ALWAYS 0
Io.-DRIVE FAULT
' - SPARE-ALWAYS 0
-SEEK ERROR
- DRIVE SELECT
--- DRIVE READY
-RK06/RK07
"-SPARES-ALWAYS 0
'-WRITE PROTECT
'-SPARE-ALWAYS 0
"-POSITIONING IN PROGRESS
"- SEEK COMPLETE
Io.-SPARE-ALWAYS 1
BIT(S)
DESCRIPTION
00
SPARE-ALWAYS 1
01
SPARE-ALWAYS 0
02
SPARE-ALWAYS 0
03
DRIVE FAULT-When set. this bit indicates that an error condition has been detected within the
drive and is prohibiting all operations. This bit is reset manually by clearing the fault condition
within the drive.
M
SPARE-ALWAYS 0
05
SEEK ERROR-When set. this bit indicates that a Seek was not completed within a specified time
period after it was initiated.
06
DRIVE SELECT-When set, this bit indicates that the drive is selected and on line.
07
DRIVE READY -Drive Ready is a read-only bit which when set indicates the selected drive is up
to speed, the heads are on cylinder and the drive is ready to accept commands. It is reset when these
conditions are not met or when the drive is seeking.
08
RK06/RK07 - When set, this bit indicates that RK07 has been selected; when reset, RK06.
09-10
SPARES-ALWAYS 0
11
WRITE PROTECT-When set, this bit indicates that the selected disc is write protected.
12
SPARE-ALWAYS 0
13
POSITIONING IN PROGRESS-When set, this bit indicates that the selected disc is write protected.
14
SEEK COMPLETE-This ready-only bit sets when the drive is ON CYLINDER. SEEK or RESTORE is completed.
15
SPARE-ALWAYS 1.
4-9
ERROR REGISTER
777 454 (RKER)
12
15
11
09
08
07
06
05
04
03
02
01
00
DCK
ILLEGAL FUNCTION
SEEK INCOMPLETE
NON-EXECUTABLE (DRIVE ERROR)
SPARE-ALWAYS 0
FORMAT ERROR
DRIVE TYPE ERROR
HARD ECC ERROR
BAD SECTOR ERROR
HEADER READ ERROR
CYLINDER OVERFLOW ERROR
INVALID DISC ADDRESS ERROR
WRITE PROTECT ERROR
SPARE-ALWAYS 0
OPERATION INCOMPLETE
DRIVE UNSAFE
DATA CHECK
BIT(S)
DEFINITION
00
ILLEGAL FUNCTION-When set, this read-only bit indicates that an illegal command has been
loaded into the RKCSI register.
01
SEEK INCOMPLETE-When set, this read-only bit indicates that a Seek operation has not been
completed by the selected drive.
02
NON-EXECUTABLE-When set, this bit indicates that a fault condition has been discovered
within the drive. The operation cannot be completed and the command is aborted.
03
SPARE-ALWAYS 0
04
FORMAT ERROR-When this bit is set in conjunction with bit 09, it indicates that the sector
pulses are too close together. Diagnostic message is "sector size too small."
05
DRIVE TYPE ERROR-This read-only bit is set when the drive type status does not compare with
Control Drive Type bit (RKCSl, bit 10), i.e., RK06 instead of RK07 or vice versa.
06
HARD ECC ERROR-When set, this read-only bit indicates that a data error detected by the ECC
logic cannot be corrected using ECC.
07
BAD SECTOR ERROR-When set, this read-only bit indicates that a data transfer was attempted
to or from a sector and the sector is bad.
08
HEADER READ ERROR-When set, this read-only bit indicates that an uncorrectable ECC error
was detected on a sector header during a data transfer. If bit 13 is also set, the error indication is
Header Not Found.
09
CYLINDER OVERFLOW ERROR-When set, the word count is not equal to zero and the
operation is programmed to continue beyond the last logical sector on the disc. This will occur on a
Read or Write Data operation.
10
INVALID DISC ADDRESS ERROR-When set, this bit indicates that an invalid cylinder
address or an invalid head address has been detected during a Seek command or Write/Read Data
command.
4-10
11
WRITE PROTECT ERROR-When set, this read-only bit indicates that the drive received
assertion of Write Gate while in the write protect mode.
12
SPARE-ALWAYS 0
13
OPERATION INCOMPLETE-When set, this read-only bit indicates that during a data transfer,
the desired header could not be found. This error can result from anyone of the following:
•
•
•
•
Head Misposition
Incorrect Head Selection
Read Channel Failure
Improper Pack Formatting
14
DRIVE UNSAFE-When set, this read-only bit indicates that a Read/Write Unsafe condition has
been detected.
15
DATA CHECK-When set, this read-only bit indicates that a data error was detected when the
current sector was read.
ATTENTION SUMMARY AND OFFSET REGISTER
777 456 (RKAS/OF)
15
08
ATTENTION
07
05
NOT USED
04
03
02
00
NOT USED
BIT(S)
DEFINITION
00-02
NOT USED-ALWAYS 0
03
OFFSET POSITIVE-Offsets the head in the positive direction from the centerline of the track
(positive is from the lower cylinder number toward the higher cylinder number).
04
OFFSET NEGATIVE-Offsets the head in the negative direction from the centerline of the track
(negative is from the higher cylinder number toward the lower cylinder number).
05-07
NOT USED-ALWAYS 0
08-15
ATTENTION - The eight Attention bits, one for each drive, correspond to the logical unit number
of each drive. Each bit indicates the state of the Drive Status Change flip-flop in the corresponding
drive. All of the ATTN bits are continuously scanned and updated (polled).
4-11
DESIRED CYLINDER ADDRESS REGISTER
777 460 (RKDC)
15
13
DIAGNOSTIC
MODE
I
12
00
CYLINDER ADDRESS
.
BIT(S)
DEFINITION
00-12
CYLINDER ADDRESS-The cylinder address in RKDC is the emulated address. The actual
mapped address is contained in RKMR2. The cylinder number is written in octal in the register.
13-15
DIAGNOSTIC MODE-These bits are as follows:
15 14 13
0
0
0
RK06/RK07 Emulation Mode
1
0
0
MAP OVERRIDE MODE-These bits can be set by the programmer to override
the mapping algorithm. When set, the head, cylinder, and sector addresse~ supplied
to the controller specify absolute address to the disc. Could be typically used to
permit the device handler to be modified to take advantage of the head per track
options available in some disc drives.
1
1
0
DMA BUFFER TEST MODE-Allows reading/writing of the controller data
buffer using the computer DMA interface. The controller word count and memory
address registers are used to set up the DMA transfer with a maximum transfer of
1024 bytes starting with location 0 of the data buffer. The Write command, 23H, will
write from the buffer. The Read command, 21 H, will read from the data buffer.
1
1
1
ECC TEST MODE
EXTENDED MEMORY ADDRESS REGISTER (22-Bit)
777 462 (RKXMA)
15
14
13
12
11
10
09
06
05
00
BITS 16·21
l
SPARE-ALWAYS 0
EXTENDED MEMORY FLAG BITS
SPARE-ALWAYS 0
EXTENDED MEMORY FLAG BITS
SPARE-ALWAYS 0
BIT(S)
DEFINITION
00-05
BITS 16-21-These bits, when set, define bits 16-21 of the 22-bit extended memory.
06-09
SPARE-ALWAYS 0
10, 13
EXTENDED MEMORY FLAG BITS-When bits 10 and 13 are set, the 22-bit address is used.
11-12,
14-15
SPARE-ALWAYS 0
4-12
READIWRITE BUFFER REGISTER
777464 (RKDB)
00
15
DATA BUFFER
BIT(S)
DEFINITION
00-15
The Data Buffer register is a read/~rite register. Writing into the register loads data into the controller data buffer, one word at a time. Reading the register reads data from the controller data
buffer one word at a time. Reading from or writing into the buffer will increment the address
register. A bus INITor setting the System Clear bit (SCL) in the RKCS2 register will reset the data
buffer address to location O.
MAINTENANCE REGISTER 1
777466
15
03
02
00
NOT USED
[
FIRMWARE MODEL
BIT(S)
DEFINITION
00-02
FIRMW ARE MODEL-These three bits define the model number of the firmware used in the
controller.
03-15
NOT USED-ALWAYS 0
ECC POSITION REGISTER
777 470 (RKECPS)
15
13
00
12
NOT USED
ERROR POSITION
BIT(S)
DEFINITION
00-12
ERROR POSITION-These read-only bits define the start location of an error burst (containing
from one to eleven error bits) within a 256-word data field, sequence. The position is valid if the
error is ECC correctable.
13-15
NOT USED-ALWAYS 0
4-13
ECC PATTERN REGISTER
777 472 (RKECPT)
11
15
00
10
ERROR PATTERN
NOT USED
BIT(S)
DEFINITION
00-10
ERROR PATTERN-These are read-only bits that provide an II-bit correction pattern for an error
burst that does not exceed 11 error bits, in length and is therefore ECC correctable.
11-15
NOT USED-ALWAYS 0
MAINTENANCE REGISTER 2
777 474 (RKMR2)
08
15
00
07
HEAD MAPPED
SECTOR MAPPED
BIT(S)
DEFINITION
00-07
SECTOR MAPPED-These bits define the actual mapped sector address in the disc as opposed to
the emulated address.
08-15
HEAD MAPPED-These bits define the actual mapped head address on the disc as opposed to the
emulated address.
MAINTENANCE REGISTER 3
777 476
15
11
00
10
NOT USED
CYLINDER MAPPED
BIT(S)
DEFINITION
00-10
CYLINDER MAPPED-These bits define the actual mapped cylinder address on the disc as
opposed to the emulated address.
11-15
NOT USED-ALWAYS 0
ENABLE REAL TIME CLOCK CONTROL REGISTER
777 546
15
07
NOT USED
06
IERTel
[
The Enable Real Time Clock Control register
performs a separate function from the other
registers. During a read operation, bit 06 is always
4-14
05
00
NOT USED
ENABLE REAL TIME CLOCK CONTROL
reset. During a write operation bit 06 is set enabling
the real time clock control. Switch S9 must be ON to
enable this function.
SECTION 5
TROUBLESHOOTING AND THEORY
This section describes troubleshooting procedures
at three levels of complexity: basic system, c9ntroller symptoms and detailed analysis. Basic system troubleshooting procedures are visual checks
not requiring test equipment and may be performed
by the operator. Controller symptom procedures
may require a scope, meter, extender board or diagnostics and should be performed by a technician.
Detailed analysis is troubleshooting at the IC level,
and is presented for engineers or system analysts
for controller evaluation. The latter method may
require the use of test equipment and the material
presented here: board layout, term listing, theory of
operation and logic diagrams.
CAUTION
Any troubleshooting requires a familiarity
with the installation and operation procedures in this manual, the appropriate DEC
manual, and the disc drive manufacturer's
manual. Ensure power is off when connecting or disconnecting board or plugs.
1.
Verify that the computer and disc drive generate the proper responses when the system is
powered up.
2. Verify that the computer panel switches are
set correctly.
3. Verify that the console can be operated in the
local mode. If not, the console may be
defective.
4.
With the drive POWER switch on, verify
that the drive READY light is on.
5. Verify that the green diagnostic light on the
controller is on.
CONTROLLER SYMPTOMS
Controller symptoms, possible causes and checks!
corrective actions are described in Table 5-1. Voltage checks should be performed before troubleshooting more complex problems.
BASIC SYSTEM TROUBLESHOOTING
The following should be checked before power is
applied:
1. Verify that all signal and power cables are
properly connected. Ribbon cable connectors
are not keyed. The arrows on the connectors
should be properly aligned.
2. Verify that all switches are properly set as
described in Sections 2 and 3.
3. Verify that all modules are properly seated in
the computer and are properly oriented.
The following should be checked during or after
application of power:
PHYSICAL LAYOUT
The physical layout of the board is shown in Figure 5-1. Column and row numbers on the layout correspond to the numbers on each IC on the logic
diagrams.
TERM LISTING
The input and output terms for each logic diagram
are described in Table 5-2. The sources and destinations refer to the sheet numbers on the logic
diagrams.
5-1
Table 5·1. Controller Symptoms
Symptom
1. Green diagnostic light
on the controller is
OFF.
Possible Causes
Check/Corrective Action
1. Microprocessor section of controller inoperative:
1. Controller/Place controller on extender
board. With a scope, check the pins on
the 2901. All pins except power and
ground should be switching. Check for
"stuck high" or "stuck low," or half-amplitude pulses. Check + 5V at various IC's.
Check PROMs A 1 through A7 for proper
seating. Check oscillator.
a.
b.
c.
d.
2. No communication between console and
computer.
Bad oscillator
Short or open on board
Bad IC
PROMs not properly seated
2. I/O section of controller "hanga. DEN always low
b. Shorted bus transceiver IC.
c. Bad CPU board.
3. No data transfers to/
from disc.
2. Computer interface logic of controller/
ing" Q Bus:
3. Disc not ready, bad connection, or bad IC in register section of the. controller.
a. Check signal DEN for constant
assertion.
b. Check I/O IC's. Remove controller
board to see if trouble goes away.
(Ensure slot is filled or jumpered.)
c. Run CPU diagnostics.
3. Disc/Consult the disc manufacturer's
manual for proper setting of disc
switches, or READY, NO FAULT, or UNSAFE lights. Check cable connections.
Controller RegisterslUsing ODT, examine
the Drive Status Register. The DISC
READY and SELECTED must be "one's."
Using ODT, deposit "ones" and "zeros" in
the remaining disc registers and verify
proper register data.
4. Data transferred to/from 4. Multiple Causes:
from disc incorrect.
a. Bad memory in backplane
b. Noise or intermittent source
of DC power in computer.
c. Bad IC in disc I/O section of
controller.
d. Bad area on disc.
,
e. Disc heads not properly
aligned.
5. Intermittent failureController runs for a
short time after power
is applied and then
fails.
5-2
5. Failure of heat sense
component on controller.
4. Computer-controller-discl
a. Run memory diagnostics.
b. Check AC and DC power.
c. While operating, check lines from controller to disc with a scope for short or
open.
d. Run the Format and Diagnostic Test
program (Section 3). If errors occur at
the same place on the disc, it is probably a bad area on the disc. Assign
alternate tracks as specified in Section
3.
e. Consult disc drive manufacturer's manual and align heads.
5. Isolate the bad component by using heat
and cooling methods (heat gun, freon
spray) and replace the bad component.
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5-3
Table 5·2. Term Listing
Term
Origin
AMF
17
BAOO-BA11 +
15
BBS7L
BBS7+
BC4+
BDALOOL
BDAL01L
BDAL02L
BDAL03L
BDAL04L
BDAL05L
BDAL06L
BDAL07L
BDAL08L
BDAL09L
BDAL10L
BDAL11L
BDAL 12L
BDAL 13L
BDAL14L
BDAL15L
BDAL16L
BUS (AP2)
4
13
BUS (AW2)
BUS (AV2)
BUS (BE2)
BUS (BF2)
BUS (BH2)
BUS (BI2)
BUS (BK2)
BUS (BL2)
BUS (BM2)
BUS (BN2)
BUS (BP2)
BUS (BR2)
BUS (BS2)
BUS (BT2)
BUS (BU2)
BUS (BY2)
BUS (AC1)
BDAL17L
BUS (AD1)
BDAL 18L
BUS (BC1)
BDAL 19L
BUS (BD1)
BDAL20L
BUS (BE1)
BDAL21L
BUS (BF1)
BDINL
BDIN+
BDMGIL
BDGOL
BDMRL
BDOUTL
BDOUT+
BEVNTL
BFULE +
BFULLBIAKIL
BIAKOL
BUS (AH2)
4
BUS (AR2)
BUS (AS2)
BUS (AN1)
BUS (AE2)
4
BUS (BR1)
3
15
BUS (AM2)
BUS (AN2)
BINITL
BIRQ4L
BIRQ5L
BIRQ6L
BIRQ7L
BITO·BIT10
BIT7+ ,-
BUS
BUS
BUS
BUS
BUS
BLKMDE
BLKMEM
BPOK·H
BPOKBREF
BREFL
BRPLYL
BRPLY +
BSACKL
BSY
BSYNCL
BTSPF +
BWTBTL
BWTBT+
BYTCK+
10
10
BUS (BB1)
4
4
BUS (AR1)
BUS (AF2)
4
BUS (BN1)
17
BUS (AJ2)
2
BUS (AK2)
4
13
5·4
(AT2)
(AL2)
(AA1)
(AB1)
(BP1)
16
13
Description
Address Mark Found From
Disc
Buffer Address Counter Bits
00-11
Bus Peripheral Address Select
Peripheral Address Select
Bit Count 4 From Bit Counter
Bus Data/Address Line 00
Bus Data/Address Line 01
Bus Data/Address Line 02
Bus Data/Address Line 03
Bus Data/Address Line 04
Bus Data/Address Line 05
Bus Data/Address Line 06
Bus Data/Address Line 07
Bus Data/Address Line 08
Bus Data/Address Line 09
Bus Data/Address Line 10
Bus Data/AdrJress Line 11
Bus Data/Address Line 12
Bus Data/Address Line 13
Bus Data/Address Line 14
Bus Data/Address Line 15
Bus Address Extension Line
16
Bus Address Extension Line
17
Bus Address Extension Line
18
Bus Address Extension Line
19
Bus Address Extension Line
20
Bus Address Extension Line
21
Bus Data In
Data In
Bus DMA Grant In
Bus DMA Grant Out
Bus DMA Request
Bus Data Out
Data Out
Bus Event
Enable Buffer Full
Buffer Full
Bus Interrupt Acknowledge In
Bus Interrupt Acknowledge
Out
Bus Initialize-Clear
Bus Interrupt Request Level 4
Bus Interrupt Request Level 5
Bus Interrupt Request Level 6
Bus Interrupt Request Level 7
Control Bits to Disc Drives
"Complete Byte" Output of
Bit Counter
Block Mode
Block Memory
Primary Power O.K.
Primary Power O.K.
Bus Refresh
Bus Refresh
Q Bus Reply
Q Bus Reply
DMA Select Acknowledge
Busy
Bus Synchronize I/O
Bootstrap Flag
Bus Write Byte
Bus Write Byte
Byte Clock
Table 5·2. Term Listing (Continued)
Term
Origin
Description
13 'Data Buffer Clock
10 Carry Out
12 Control Pulse 1
12 Control Pulse 2
12 Control Pulse 3
12 Control Pulse 4
12 : Control Pulse 5
12 !control Pulse 6
12 icontrol Pulse 7
13 Cyclic Redundancy Check
iError
9 Control Register One Bits 0·7
CR1-0/7
9 Control Register Two Bits 0-7
CR2-0/7
9 Control Register Three Bits 0-7
CR3-0/7
9 Gontrol Register Four Bits 0-7
CR4-0/7
9 Control Register Five Bits 0-7
CR5-0/7
9 Control Register Six Bits 0-7
CR6-0/7
CSAO + /CSA9 +
8 Control Store Address Bits 0-9
3 Extended Data/Address Bit 16
DA16+
3 Extended Data/Address Bit 17
DA17+
DATO+ IOAT7 +
14,15 Data Buffer Bits 0-7
13 Data Buffer Write Control In
DBWC1 +
13 Data Buffer Write Strobe
DBWSDBWS113 Data Buffer Write Strobe In
6 Data Bus Bits 0·7
DBOO + IOB07 +
7 Data Bus Bits 8·15
OB08 + IOB15 +
DCLK
3 ,System Clock
DEN6 Data Enable
4
DMA Grant In
DMGI+
Disc Read
13
DREAD
2,3,4,9,11, D·Bus Bits 0·7
DOO + ID07 +
12,14,17,
18,19
EADD+
3 Enable Address
EADD6 Enable Address
EBITC+
3 Enable Bit Count
ECCO+
19 Error Correction Code Out
EDATA +
3 Enable Data
ENRD13 Enable Read Data Register
ENWO13 Enable Write Data To Buffer
13 Enable Read Data
EROATA
14 Enable Write Data
EWDATA
FAULT
17 Drive Fault
GDATA+
13 Gated Read Data
GSCLK 3 Gated System Clock
GTIRQ+
5 Gated Transmit Interrupt
Request
IAKI+
4 Interrupt Acknowledge In
IAKIG2 Interrupt Acknowl~dge In
Grant
INDEX
17 Index Pulse From Drive
4 Initialize
INIT1
INIT+
4 Initialize
LCOUT
8 Latch Carryout
11 Load External Register Data
LXROOut MSB
11 Load External Register Data
LXR1Out LSB
11 Load External Register DMA
LXR2Address MSB
11 Load External Register DMA
LXR3Address LSB
11 Load External Register Data
LXR4Buffer LSB
11 Load External Register Data
LXR5Buffer MSB
11 Load External Register Data
LXR6Buffer
11 Load External Register
LXR7Extended Address
CLKDB
COUT+
CP1
CP2
CP3
CP4
CP5
CP6
CP7
CRCER+
Table 5-2. Term Listing (Continued)
Table 5·2. Term Listing (Continued)
Term
Origin
LXR9-
11
LXRA-
11
LXRB-
11
LXRC-
11
LXRD-
11
LXRE-
11
LXRF-
11
MROB+
OCD+/ONCYL+/PD1
PD4
PICK
oaUSA
03
RAM3+
RAMDE
RCKE1
RCLOCKA/B + /-
3
16
17
6
17
16
2
10
10
13
10
18
ROATAA/B+/RDATA+
REP
RESET
RMCLK
RSYNCRTBS7
RTCGO
R/WCKR/WSRE+
18
18
19
4
3
13
3
17
18
3
SELA/B
SENDA/B
SCLK
SCLOCKA/B
SOB08+
SEEKA/B
SEC+ISERR+ISlIlN +
18
18
3
18
2
18
17
TAG1/2/3
TDIN+
TOMG+
16
3
2
17
2
Description
Load External Register Drive
Control Tags
Load External Register Drive
Control Bus Bits
Load External Register Vector
Address
Load External Register
System Control
Load External Register
Bootstrap Address
Load External Register CPU
Bus Control
Load External Register RAM
Destination
Memory Request 0 Bus
Open Cable Detect
On Cylinder From Drive
Pull Down 1
Pull Down 4
Power Pick
Q Bus Access
Q Register Shift Line
Shift Output of ALU RAM
Ram Output Enable
Real Time Clock Enable
Read Clock From Drives A or
B
Read Data From Drives A or B
Read Data
Read Error Pattern
Reset Signal to Controller
RAM Clock
Read Synchronize
Transmit Bank 7
Real Time Clock Go
Read/Write Clock
Read/Write Shift Register
Enable
Drives A or B Selected
Drives A or B Seek End
System Clock
Servo Clock From Drives
Slave Data Bus Bit 8
Seek End From Drives
Sector Pulse From Drive
Seek Error From Drives
Slave Interrupt Acknowledge
Request
Tag Lines To Drives
Transmit Data In
Transmit Direct Memory Grant
Term
I
Description
Origin
TDMR+
2
TEVNT
TIAK+
10
2
TIRQ+
TRPLY
TSACK
rSYNC
TWTBT
UNRDY
USELO/1/213
USELA/B
USTAG
VEC-
3
3
2
3
3
17
16
18
16
8
WDATA+
WCLOCKAIB + 1WDATAA/B + 1WPRT
WRENXSDO
14
18
18
17
3
11
XSD1
11
XSD2
11
XSD3
11
XSD4
11
XSD5
11
XSD6
11
XSD7
11
XSD8
11
XSD9
11
XSDA
11
XSDB
11
XSDD
11
XSDF
YOO/Y07
ZERO+
1KOV +
11
10
10
15
Transmit Direct Memory
Request
Transmit Event
Transmit Interrupt
Acknowledge
Transmit Interrupt Request
Transmit Reply
Transmit Select Acknowledge
Transmit Synchronize
Transmit Write Byte
Drive Unit Ready
Drive Unit Select Bits 0, 1, 2, 3
Drive Unit Select A, B
Drive Unit Select Tag
Vector Address Register
Select
Write Data Bit Stream
Write Clock To Drives A or B
Write Data To Drives A or B
Drive Write Protect
Write Enable
External Source Decode Slave
Address
External Source Decode Data
Input MSB
External Source Decode Data
Input LSB
External Source Decode CPU
Bus Status
External Source Decode Data
Buffer
External Source Decode Disc
Drive Status
External Source Decode Seek
End Status
External Source Decode Error
Status Register
External Source Decode
Bootstrap PROM
External Source Decode
Configuration Switches
External Source Decode
Literal PROM
External Source Decode RK06
Switches
External Source Block Mode
Status
External Source Decode RAM
V-Bus Bits 0-7
Zero Output of 2901
1024 Address Counter
Overflow
THEORY
The controller may be examined as three parts:
computer interface, disc interface and controller
internal functions. Signals from and to the com·
puter are described in Section 1, Table I-I. Signals
from and to the disc drive are described in Tables 1-2
and 1-3. Figure 5-2 is a simplified block diagram
illustrating the interfaces and some of the functional components. Single lines in the illustration
represent serial data and the wider lines represent
parallel data. A detailed block diagram of the controller is shown on Sheet 1 of the logic drawings.
The numbers in the blocks on Sheet 1 refer to the
sheet numbers of the other logic diagrams.
Computer Interface
The purpose of the computer interface is to (1) buffer lines between the Q Bus of the LSI -11 computer
and the controller, and (2) to synchronize information transfers. The controller is a slave device during initialization and status-transfer sequences. The
controller is selected by base address 776 7008 , The
controller is bus master during data transfers and
5-5
a:
w
....
....
-..r
....
DATA/ADDRES~
DATA
""
v
f-
:::>
<
DATA
/
A
a.
COMPUTER
INTERFACE
~
o
o
f-
o
-
<"'.
~
WRITE DATA
.... /
...J
<{
A
DATA
"'"
MICROPROCESSOR
DATA
CONTROL
CONTROL
CONTROL
CONTROL
TIMING
TIMING
PERIPHERAL
INTERFACE
READ DATA
a:
w
I
a.
CONTRO~
a.
a:w
_
STATUS
• DATA INPUT REGISTER
• TIMING SOURCE
• DATA RECEIVER/DRIVER
• DATA OUTPUT REGISTER
• CONTROL CENTER
• CONTROL DRIVER
• ADDRESS DECODE DRIVER
• REGISTER STORAGE
• DRIVE STATUS RECEIVER
• ADDRESS DRIVER
• DAT~ BUFFERING
• ECC LOGIC
• BUS RECEIVERIDRIVER
of-
• SOURCE/DESTINATION DECODE
• BOOTSTRAP LOADER
• ECC LOGIC
Figure 5-2. Simplified Block Diagram
either receives data from or outputs data to the computer memory via the LSI-II DMA facility.
The control lines request information transfers,
select the type and direction of transfers, and synchronize the transfers. The control lines are unidirectional and used for "bus arbitration." Bus
synchronization is fully controlled by the controller
microprocessor. This allows the computer bus to be
used by other devices when the disc controller is
busy with internal functions and controller/disc
data transfers.
Data bus driver/receiver registers 12F and 13G
through 15F and 17G (Sheets 6 and 7) buffer the
input data and distribute it as DBOO-15 in the controller. The DB signals are routed to a data input
multiplexer (MUX) and address decode registers
located on Sheets 12 and 2.
Output data and addresses from the microprocessor Y Bus (YOO-Y07) are latched by registers 12F
and 13G through 15F and 17G and transferred to
the Q Bus via bus driver/receivers.
Note that the Device Enable signal (DEN -) is
active when either the Address Enable (EADD) or
the Data Enable (EDATA) signal is active. DEN
controls the operating mode of all data and address
driver/receivers, under control of the firmware, via
the Y Bus (Sheets 6 and 7).
Disc Interface
The disc is connected to the controller by separate
data and control cables. A common control cable is
daisy chained to both drives in a multiple-drive configuration, while separate data cables are always
used.
Serial read data is received by receivers 13A or
14A (Sheet 18) and then converted to parallel data
by the read/write shift register 4C (Sheet 14). In the
reverse direction, parallel data from the data buffer
5-6
is converted to serial data by the shift register, then
sent to data cable drivers (Sheet 18).
The control cable drivers 5B, 6B, 7B and 8B
(Sheet 16) are always enabled and are driven by the
output of registers 12C and 13C, whieh act as
latches to capture the Y-Bus data from the microprocessor.
Control Cable receivers 9B and lOB (Sheet 17)
supply data to the disc status register/multiplexer
15C (Sheet 17) at all times. The data is available to
the microprocessor via the D Bus when signal
XSD5 - is active.
Controller Internal Functions
The microprocessor is the timing and control
center of the controller. The microprocessor is controlled by instructions stored in Programmable
Read Only Memory (PROM). These instructions,
called "firmware," cause the microprocessor to
operate in a prescribed manner during each of the
computer-selected functions. The functions are
established by a series of instructions issued by the
LSI-II.
Because the disc and computer transfer data at
different rates, it is necessary to buffer data going
to and from the disc. High-speed Random Access
Memory (RAM) allows a full sector of data to be
buffered during read and write operations.
All data transfer and computer/disc protocol is
under microprocessor control. This feature allows
modification of controller operating characteristics
by making changes only to the firmware. Input/output logic remains essentially unchanged.
The output from the microprocessor is the Y Bus.
Y-Bus instructions govern all controller operations
by acting as the controller source for all receivers
and drivers, either directly or through the
source/destinations decode IC's (Sheet 11).
The D Bus is the data input to the microprocessor.
Tri-state drivers allow many signal sources to be
connected to the bus, while only one at a time is
enabled by the source/destination decode logic
(Sheet 11).
The following list describes D-Bus enabling
signals:
Function
Term
Component
Enabled
Sheet
Slave Address
Data Input (MSB)
Data Input (LSB)
Q Bus Status
Read Buffer
Disc Status
Seek End/Unit Select
Error Status
Boot PROM
Switches
Literal
Switches
Scratch RAM Enable
XSDO
XSDI
XSD2
XSD3
ENRD
XSD5
XSD6
XSD7
XSD8
XSD9
XSDA
XSDB
XSDF
15D
13D
14D
12D
2C
15C
16C
8D
10F
16D
7G
21C
8G,9G
2
1212
12
14
17
18
19
11
3
9
5
12
All data on the D Bus is under control of the firmware as decoded by source PROMs 11C, 12G on
Sheet 11. The microprocessor selects the proper
input data by enabling one of the above lines.
The Y Bus is the microprocessor output. Output
of the microcode PROM 5G (Sheet 9) is decoded by
lOG and 11G (Sheet 11) to select the destination of
the data on the Y Bus.
The following list describes Y-Bus enabling
signals:
Function
Data Out Register
(MSB)
Data Out Register
(LSB)
DMA Address (MSB)
DMA Address (LSB)
Data Buffer Address
(LSB)
Data Buffer Address
(MSB)
Data Buffer Load
Load Extended Address
Drive Control (Tags)
Drive Control (Bus 0-7)
Load Vector Address
System Control
External Event
Q Bus Control
RAM Destination
Term
Component
Enabled
Sheet
LXRO
12F
7
LXRl
LXR2
LXR3
14F
13F
15F
6
7
6
LXR4
10C, 14C
15
LXR5
LXR6
LXR7
LXR9
LXRA
LXRB
LXRC
LXRD
LXRE
LXRF
14C,7C
19E,6C
17G
12C
13C
8C
17F
15C
16F
8G,9G
15, 19
13, 14
7
16
16
8
3
17
3
12
With the single exception of bus reply detector
20F (Sheet 2), all Y-Bus data and address activity is
controlled by the 15 signals shown above.
Each LXR (Load External Register) signal activates a register which, in conjunction with Y-Bus
data, latches the appropriate data word.
Control Registers CR1 through CR6 are the outputs of the microcode PROMs (Sheet 9). These signals control the microprocessor functions and provide the data to the source/destination decode logic
(Sheet 11).
Data Buffer
The data buffer and associated logic are shown on
Sheets 13, 14 and 15. Data transfers to and from the
buffer are both two-step operations. First, an entire
sector of data is loaded into the buffer during either
a read or write operation. Once loaded, the buffer
contents are then transferred to disc or LSI -II
memory in a completely separate operation. Figure
5-3 illustrates read and write operations to and from
the RAM data buffer.
During a write operation, parallel data (YOO-Y07)
is transferred from LSI -II memory via microprocessor to the write data register 6C (Sheet 14). The data
(DATO-DAT7) is then transferred to the buffer 10D
(Sheet 15). Parallel data (DATO-DAT7) from the
buffer is then transferred to shift register 4C (Sheet
14), converted to serial data (W DATA), and transferred to the data cable driver 17 A (Sheet 18).
During a read operation, serial Read Data (R
DATA) from the data cable enters the shift register
3C and is transferred as parallel data to the Read
Data register 1C, for transfer to the data buffer
while the next byte is being shifted through shift
register 3C. The read data from the buffer (DA TODAT7) is transferred to driver 2C (Sheet 14) to the
microprocessor for transfer to LSI-II memory.
The counter located at 9C, 10C and 14C (Sheet 15)
is used to address the location in the buffer where
data can be written or read. The counter can be preset to a specific starting address via the Y Bus of
the microprocessor.
ERROR CORRECTION CODE (ECC) LOGIC
Functional Operation
The ECC Generator (Sheet 19) does not correct
errors; it generates codes during write and read
operations, and during reading generates a syndrome. A syndrome is the result of merging check
characters being read with check characters generated. A zero syndrome indicates no error; a nonzero
syndrome indicates an error. This syndrome contains all the information necessary to find the error
location and the error pattern, Le., to allow error
correction.
The error location is found by counting the
number of clock pulses required to make the Error
Pattern (EP) output go high. The error pattern is
then available on the LPO-LP3 and QO-Q7 outputs
5-7
A. WRITE -
YOO·?
2901
MICROPROCESSOR
MICROPROCESSOR'TO RAM
.....
10
DATO·?
......
....
.
WDATA
DATA
CABLE
DRIVER
14
DATO·?
READ/WRITE
DATA SHIFT
REGISTER
.
....
DATO·?
READ DATA
REGISTER
..
RAM
DATA
BUFFER
""
14
D. READ -
DATO·?
18
DISC TO RAM
14
RAM
DATA
BUFFER
RAM
DATA
BUFFER
15
READ/WRITE
DATA SHIFT
REGISTER
C. READ -
..
~
RAM TO DISC
15
G DATA
-.-
14
B. WRITE -
RAM
DATA
BUFFER
DATO·?
WRITE DATA
REGISTER
.....
15
RAM TO MICROPROCESSOR
READ
BUFFER
DATA DRIVER
DOO·O?
14
15
....
2901
MICROPROCESSOR
10
Figure 5-3. Data Paths
and can be used to exclusive OR with data. Either
the computer or the controller corrects the error.
Note that some error patterns cannot be corrected.
These are flagged to the computer.
Component Description
During a write operation, a 32-bit ECC is
appended to the header record and a 56-bit ECC is
appended to the data record of each sector of
information on the disc. ECC's are also generated
while information is being read from the disc. The
codes generated during the read operation are
compared to the equivalent codes previously
written. Discrepancies detected (errors) are signaled
to the microprocessor and corrected if possible.
The ECC logic is shown on Sheet 19. The ECC
Generator (7D), also referred to as the Burst Error
5-8
processor, is used in three different types of operations: write, read, and correct. Detailed information
about the ECC generator is given by an AMD,
AM9520/Z8065 product specification.
During writing or reading, information is connected to the DO-D7 inputs of the ECC Generator.
Select inputs SO and Sl determine whether a 32- or
56-bit polynomial is being used. The 32-bit
polynomial is used for ECC header checks, and the
56-bit polynomial is used for data record check. The
Data Buffer Write Strobe (DBWSl) is the source of
Clock Pulses (CP) to the ECC Generator.
Control information for the ECC Generator from
the Y Bus is stored by LXR5 into ECC Control
Register 7C.
When Master Reset (MR-) is asserted, the logic
is initialized. Asserting REP (Read Error Pattern)
makes outputs LPO-LP3 and QO-Q7 active.
Control inputs PO-P3 are not used. The ECC Generator functions selected by the CO-C2 inputs are as
follows:
C2
Cl
CO
Function
L
L
L
H
H
L
L
H
L
H
L
H
L
L
L
Compute Check Bits
Write Check Bits
Read Normal
Load
Correct Normal
Check bit outputs QO-Q7 are connected to the
DATO-DAT7lines one byte at a time under control
of REP and CO-C2. The remaining outputs of the
ECC Generator are stored in ECC status register
8D (Sheet 19) by clock GSCLK. The microprocessor
monitors ECC status on the D Bus during XSD7
time.
Outputs LPO-LP3 (Located Error Pattern),
together with outputs QO-Q7, provide the 12-bit
error pattern. Q7 is the MSB and LPO is the LSB of
the pattern. Outputs LPO-LP3 are active only when
REP is asserted. Output AE (Alignment Exception)
is asserted if the error pattern will not line up automatically during a correction sequence. This can
occur because of the method of polynomial division
implemented in the ECC generator.
Output EP (Error Pattern) is asserted when the
error pattern has been located during the correction
sequence. Output ER is asserted if an error was
detected after the last check byte had been read
during a read function.
5-9.
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