2223216 0001_TI_PC_Tech Ref_May_1984 0001 TI PC Tech Ref May 1984

2223216-0001_TI_PC_TechRef_May_1984 2223216-0001_TI_PC_TechRef_May_1984

User Manual: 2223216-0001_TI_PC_TechRef_May_1984

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Part No. 2223216-0001, Rev; A

May 1984

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Copyright © 1984 Texas Instruments Incorporated
All Rights Reserved - Printed in USA
The information herein and patents which might be granted thereon disclosing or employing the materials,
methods, techniques or apparatus described herein are the exclusive property of Texas Instruments
Incorporated.
No copies of the information or drawings shall be made without the prior consent of Texas Instruments
,.Incorporated .

......

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Technioal Reference Manual
Part No. 222:t216-()001
. "i.:Pre,IA~ifiary IsslJ,e.:Janu,ary 1983
, .. R~\lisiQn /fj: May 1984 ,:
Total numl1llr of page~ in this"publitation is

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Front Cover "
Effective
Pages:'
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Preface
v -xiv
1.~1 -1-6
2-1 -2-61
3-1 -3-72
4-1 -4-76
5-1 -5-202
6-1 -6-44
A-1 -A-5

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consisting of the following:

Page

Change

Page

Change

No.

No.

No.

No.

C-1 ~C-12
D-1
E,1 -E-6
F-1 -F-3
.; .G-1 -G-9

H-1 -H-7
Index-l -lndex-9
User's Response
Mailer
; ,Back Cover

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CHAN~lE'NOTICES

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ECN

Revision
Letter

Date

,;i\ ,,:

Description

,

;·~i..mier

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5,3/84

A

Level

:

518860

B

Update manual.

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Address all correspondence regarding orders to:
Texas Instruments Incorporated
Data Systems Group
P.O. Box 1444, MIS n93
Houston, TX n251

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TECHNICAL REFERENCE

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PREFACE
detailed
information
on ~h~'
The Technical Reference Manual contains
design
and function of the Texas Instruments Professional Computer and
is intended for use
by
software
and
hardware
designers"". and ,:"o,ti?e,r
technical persons.
This manual is divided into six major sections:
.""

. ":>

Section
1.
Introduction - Provides a general descri~ption:' of't,he Tex,as
Instruments
Professional
Computer
and
identifies
't'ts ",,:' various
configurations,
options,
and accessories.
This sectional~o includes
tables listfng' erivironmental requirements for the sysJ,em., ,.
"
......

"

Section 2.
System Hardware - Provides a de tai led d·e-..s:eir.;.-ip·td on
of 'each
component
of
the
system
including
specifications and
int~~face
information.
This section also includes hardware programni:lng data, such
as coding tables, registers, and signal pin-outs.
section 3.
Hardware Options - Provides a det~iled description
of
the
options
available
for
the
system.
This
section
contains
specifications, interface information, and
hardware
programming
data
such as coding tables, registers, and signal pin-ou~s.
Section
4.
Device
Service
Routines
Describes
the
interrupt vector lists, and a keyboard scan coding +abl~.

ROM,

gives.
."

Section 5.
Assembly
Drawings
and
Lists
of
Materials
Includi~
detailed
drawings for all field replaceable assembliflhiS a,nd option$~,~;~A"
List
of
Materials,
identifying all
components':'" a(s:,,,;pj,ece
parts,
accompanies ea·ch assembly drawing.
,'IIi,'",,:'¥i:'i~:!>'lIi~t',
,to
,to
/

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Section 6.
Schematics and LOglC Drawlngs - Provide_/il'lo9~ic diagrams and
schematics
for
each
component
and field replac~~~le ~iYembly ~i' the
Texas Instruments Professional Computer.
The
appendixes
provide
reference information, such as definition. of
all I/O addresses, and a complete memory map (covering ~he motherbo~rd,
all memory connected to the expansion bus,
and
the
memory
expa~sion
bus).
Also
included
are
complete information on the ch.ract~r sets
furnished with the computer and a breakdown
of
the
power
ali~cat~on
between the various options and printed wiring boards.

lil/1V

TECHNICAL REFERENCE

CONTENTS

Table of Contents
Section

Title

Page

Preface

iii

1

INTRODUCTION .

1-1

1.1
1.1. 1
.1. 1. 2

1-1
1-1

1. 2.5
1. 2.6
1. 2.7
1.3

SYSTEM COMPONENTS
Keyboard.
System Unit .
Display Unit
OPTIONAL COMPONENTS.
Diskette Drive S.
Winchester Disk Drive
Expansion Memory Boards.
---- S 'y n ch ron 0 u s - Asy n C h ron 0 u s
Communications Board .
Internal Modem Boards
Graphics-Video Controller Board
Color Display Unit
ENVIRONMENTAL CONDITIONS

2

SYSTEM HARDWARE

2.1
2.2
2.2.1
2.2.2
2.2.3

INTRODUCTION .
KEYBOARD
Encoding Keystrokes
Transmission
Receiving and Responding to system
Unit Commands
Implementing a Software-Switchable
Repeat-Action Function
Performing n-Key Rollover .
Locking/Unlocking the Keyboard
Performing a Self-Test
SYSTEM UNIT BOARD
SYSTEM SUPPORT
Keyboard Port
System CPU .
Optional Numeric Coprocessor
CPU Clock Generator
CPU Bus Buffering .
CPU Bus Controller.
Reset Detection Circuit
Motherboard Input/Output System
I/O Decoding.
Parallel Printer Port.
Timers.
Speaker Amplifier .
Motherboard Interrupt System
Motherboard Memory System.
Motherboard Memory Addressing

1.1. 3

1.2
1.2.1
1. 2.2
1.2.3
1. 2.4

2.2.4
2.2.5
2.2.6
2.2.7
2.3
2.4
2.4.1
2.4.2
2.4.2.1
2.4.2.2
2.4.2.3
2.4.2.4
2.4.2.5
2.4.3
2.4.3.1
2.4.3.2
2.4.3.3
2.4.3.4
2.4.4
2.4.5
2.4.5.1

-v-

1-2
1-2
1-2
1-3
1-3
1-3
1-3
1-3
1-4
,1-4
1-4

.

2-1
2-3
2-3
2-3
2-4
2-6
2 -6"
2-7
2-7
2-8
2-10
2-10
2-11
2-11
2-11
2-11
2-12
2-12
2-12
2-15
2-16
2-18
2-18
2-18
2-20
2-20

CONTENTS

TECHNICAL REFERENCE
Title

section
2.4.5.2
2.4.5.3
2.4.5.4
2.4.5.5
2.4.6
2.4.6.1
2.4.6.2
2.4.6.3
2.4.6.4
2.4.6.5
2.4.6.6
2.4.7
2.4.7.1
2.4.7.2
2.4.7.3
2.4.7.42.4.7.5
2.4.7.6
2.4.8
2.4.8.1
2.4.8.2
2.4.8.3
2.4.8.4
2.4.8.5
2.4.8.6
2.4.8.7
2.4.8.9
2.5
2.5.1
2.5.2
2.5.3
2.5.4

Memory Control Logic
CAS and Address Multiplexer Switch
Parity Generation and Checking.
Memory Control State Machine
Floppy Disk Controller
Floppy Disk Controller IC
Sector Buffer
Write Precompensation Circuit
Data Separator
Diskette Drive Interface.
Dlskette Drive
CRT Controller Board.
Display CharacterIstics
Character Attributes
Character Sets
Cursor ._
Scrolling.
Video Connector.
CRT Controller IC.
CRT Screen/CPU ArbItration Logic
Subsystem.
CRT Address Decode LogiC.
character set and Attribute Logic.
Generating a Character ROM
Attribute Interaction.
Attribute Hardware.
CRT Interrupt Logic Subsystem
Diagnostic Loopback
EXPANSION BUS.
Expanslon Bus Signal Descriptlons
Loading and Driving Requirements.
Memory Timing
I/O Timing .

Page
2-21
2-22
2-22
2-23
2-26
2-26
2-26
2-30
2-30
2-31
2-35
2-37
2-41
2-42
2-43
2-43
2-43
2-44
2-44
2-47
2-50
2-52
2-53
2-55
2-55
2-56
2-56
2-56
2-58
2-59
2-59
2-61

HARDWARE OPTIONS
3.1
3.2
3.2.1
3.2.2
3.2.2.1
3.2.2.2
3.2.2.3
3.2.2.4
3.3
3.3.1
3.3.2
3.3.3
3.3.4

INTRODUCTION
EXPANSION MEMORY, 512/768 K BYTES
Addressing the Expansion Memory
Expansion Memory Control Logic.
Expansion Memory Refresh Logic
CAS and Address MUX Switch Generation.
Expansion Memory Parity Generation
and Checking .
Expansion Memory Control State Machine
SYNCHRONOUS-ASYNCHRONOUS COMMUNICATIONS
BOARD.
System, Interface
Baud Rate Generation.
Addressing
Programming.

-vi-

.3-1
.3-1
.3-2
.3-2
.3-2
.3-3
3-3
3-4
3-8
3-9
3-10
3-11
3-11

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TECHNICAL REFERENCE
section
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.6.1
3.4.6.2
3.4.7
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.6
3.6.1
3.6.1.1
3.6.1.2
3.6.1.3

(

3.6.1.4
3.6.1.5
3.6.1.6
3.6.1.7
3.6.2
3.6.2.1
3.6.2.2
3.6.2.3
3.6.2.4
3.6.2.5
3.6.2.6
3.6.3
3.6.4
3.6.5
3.6.6
3.6.6.1
3.6.6.2
3.6.6.3
3.6.6.4
3.6.6.5
3.6.6.6
3.6.6.7
3.6.6.8
3.6.6.9
3.6.6.10
3.6.6.11
3.6.6.12
3.6.6.13
3.6.7
3.6.8
3.6.9
3.6.10
3.6.11

CONTENTS
Title

INTERNAL MODEMS
Archltecture
Zilog B530--Modem Signals
Modem Initiallzatlon.
Command Mode Operation
Dlaling Procedure.
Time-Outs
Terminal or Software Time-Outs.
Modem Time-Outs
Modem Software.
GRAPHICS VIDEO CONTROLLER BOARD.
Pixel Addressing
Color Selectiong
Timing and Synchronlzatlon.
Graphlcs Logic Array Program
WINCHESTER DISK DRIVE AND CONTROLLER OPTION.
Wlnchester Hardware Theory of Operation
On-Board EPROM/ROM.
Commands and Command Testlng
Explanation of Bytes in the Device
Control Block.
Control Field Detailed Description
Command Completion Status Byte.
Logical Address (HIGH, MIDDLE and LOW)
Sector Interleaving
Reglster Assignments.
Data Input Port.
Data Output Port
Controller Status Reglster
Reset Port
Interrupt Mask .
Error Status Byte
Bit Definitlons for Registers and Ports
Controller Status Bit Combinations
Kormal Command Sequence Operation
Detailed Description of Commands.
TEST DRIVE READY Command.
RECALIBRATE DRIVE Command
REQUEST SENSE STATUS Command
FORMAT DRIVE Command
CHECK TRACK FORMAT Command
FORMAT TRACK Command
FORMAT BAD TRACK Command.
READ Command.
WRITE Command
SEEK Command.
INITIALIZE DRIVE CHARACTERISTICS Command
READ ECC BURST ERROR LENGTH Command
FORMAT ALTERNATE TRACK Command.
Alternate Track Assignment.
Alternate Address Protocol.
WRITE SECTOR BUFFER Command
READ SECTOR BUFFER Command.
RAM DIAGNOSTICS Command.

-vii-

Page
3-14
3-15
3-15
3-18
3-18
3-19
3-20
3-21
3-21
3-22
3-24
3-26
3-27
3-31
3-33
3-34
3-34

3-34
3-35

3-35
3-36
3-37

3-37
3-37
3-38

3-39
3-39

3-39
3-39

3-40
3-40
3-40

3-42
3-43

3-44
3-44
3-44
3-44

3-51
3-52
3-53
3-54

3-55
3-55
3-56
3-57
3-59
3-60
3-61
3-62
3-64
3-64

3-65

CONTENTS

TECHNICAL REFERENCE

Section
3.6.~2

3.6.13
3.6.14
3.6.15
3.6.16
3.6.17
3.6.18
3.6.19
3.6.20

Title
DRIVE DIAGNOSTICS Command
CONTROLLER INTERNAL DIAGNOSTICS Command
READ LONG Command.
WRITE LONG Command
Execution Order of Remaining Diagnostics
Error Correction Philosophy
Sector Field Description
Specifications - Controller Board
Electrical Interface.

Page
3-65
3-66
3-66
3-67
3-68
3-68
3-69
3-71
3-72

4

DEVICE SERVICE ROUTINES

4.1
4.2

4-1
ROM INTERFACE INFORMATION.
WRITrNG SOfTWARE FOR COMPATIBILITY WITH
4-1
FUTURE PRODUCTS
4-1
Compatibility Levels.
4-2
Operating System
4-2
System ROM Interface
4-2
Hardware Interface.
Areas of ,Hardware Compatibility
4-2
Alphanumeric CRT
4-2
4-3
Graphics CRT.
Disk Subsystem.
4-3
Keyboard System.
4-3
4-3
Interrupt Controller
4-3
System Timers and Speaker
4-3
Parallel Printer Port.
Serial Communication •.
4-3
4-4
SYSTEM ROM INTERRUPT VECTOR USAGE
4-6
Hardware Interrupt Service R~utine~.
4-7
Common Interrupt Exit Vector
4-7
Timer Interrupts
ROM STRUCTURE.
4-8
ROM Usage
4-8
ROM Format
4-8
.-4-9
Option ROM Interrupt Vector ~sage
RAM Usage by Option ROM.
4-10
Initializing the Option ROM
4-10
BOOTING UP THE SYSTEM
4-10
Boot Sequence .
4-11
Loading and Calling the Boot Code
4-11
Booting From an OptIon Devjce.
4-13
SYSTEM CONFIGURATION FUNCTION CALL~
4-13
System Configuration Function.
4-13
Extra System Configuration Function.
4-14
Get Pointer to System Configuration.
4-16
Get Pointer to Extra System Configuration. 4-17
GENERAL-PURPOSE ROM FUNCTIONS
4-17
Delay.
4-17
CRC Calculation
4-17
Print ROM Message.
4-18
4-18
Display System Error Code

4.2.1
4.2.~.~

4.2.1.2'
4.2.1.3
4.2.2
4.2.2.1
4.2.2.2
4.2.2.3
4.2.2.4
4.2.2.5
4.2.2.6
4.2.2.7
4.2.2.8
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.5
4.5.1
4.5.2
4.5.3
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.7
4.7.1
4.7.2
4.7.3
4.7.4

-viii

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TECHNICAL REFERENCE
section
4.8
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.9
4.9.1
4.9.2
4.9.3
4.10
4.10.1
4.10.2
4.10.3
4.10.4
4.10.5
4.10.6
4.10.7
4.10.8
4.10.9
4.10.10
4.10.11
4.10.12
4.10.13
4.10.14
4.10.15
4.10.16
4.10.17
4.10.18
4.10.19
4.11
4.11.1
4.11.2
4.11.3
4.11.4
4.11.5
4.11.6
4.11.7
4.11.8
4.11.9
4.11.10
4.11.11
4.11.12
4.11.13
4.11.14

CONTENTS
Title

Page

SPEAKER DSR
Sound the Speaker - AH = O.
Get Speaker Status
AH = 1.
Set Speaker Frequency
AH = 2 .
Speaker ON
AH = 3
Speaker OFF
AH = 4
TIME OF DAY CLOCK DSR
Set the Date
AH = O.
Set the TIme
AH = 1 .
Get the Date and TIme
AH = 2 .
CRT DSR.
Set Cursor Type - AH = 01H.
Set Cursor Posltion - AH = 02H
Read Cursor Posltion - AH = 03H
Scroll Text Block - AH = 06H and 07H
Read Char~cter/Attrlbute at Cursor
Position - AH = 08H
WrIte Character/Attribute at Cursor
Position - AH = 09H
Wrlte Character at Cursor
Position - AH = OAH
Write ASCII Teletype - AH = OEH
Write Block of Characters at Cursor
With Attribute - AH=10H
Wrlte Block of Characters Only at Cursor
Position - AH
11H
Change Screen Attribute(s) - AH
12H
Clear Text Screen and Home the
Cursor - AH = 13H .
Clear Graphics Screen(~) - AH = 14H.
Set TTY Status Region Beginning AH = 15H .
Set Attrlbute(s) - AH = 16H
Get Physical Display-Begin POInter
AH
17H .
Prlnt TTY String - AH = 18H
CRT TTY Mode BehaVIor
Custom Encoding of the CRT.
DISK DSR
Reset Disk System - OOH.
Return Status Code - 01H
Read Sectors - 02H
Write Sectors -03H
Verify Sector CRCs - 04H
Null Operation - OSH.
VerIfy Data - 06H.
Return Retry Status - 07H
Set Standard Disk Interface Table - 08H
Set DIT Address for DrIve - 09H .
Return DIT Address for Drive - OAH
Turn Off All DIskette DrIves - OBH
Status Codes
Disk Interface Tables (DITs)

4-18
4-18
4-19
4-19
4-19
4-19
4-20
4-20
4-20
4-21
4-21
4-23
4-24
4-24
4-2S

=

=

=

-ix-

4-27
4-27

4-28
4-28

4-29
4-29
4-30
4-30
4-30
4-30
4-31
4-33
4-33
4-33
4-34

4-35
4-35
4-36
4-36
4-37
4-37
4-38
4-38
4-38
4-39
4-39
4-40
4-40
4-40
4-41

CONtENTS

TECHNICAL REFERENCE

Page

Title

Section

4-44
4-44

4.12
4.12.1

KEYBOARD DSR .
Initiallzation Logic.

4.12.2
4.12.3
4.12.4
4.12.5
4.12.6
4.12.7

Read Keyboard Input - AH
0
Read Keyboard Status
AH :: 1
Read Keyboard Mode
AH :: 2.
Flush Keyboard Buffer
AH
3.
Keyboard Output
AH :: 4.
Put Character Into Keyboard Buffer AH = 5.
General Keyboard Layout.
Character Codes
Extended Codes.
Keyboard Modes.
Type-Ahead Buffer.
Repeat-A~tlon Feature
Speclal Handling
User-Avallable Interrupts
Keyboard Mapping
Program Pause
Program Break
Print Screen.
Keyboard Queueing
Custom Encoding
Keyboard Interface Protocol
PARALLEL PRINTER PORT DSR.
output Character to Printer
AH
0, DL :: 0
Inltialize Prlnter
AH
1, DL = 0 .
Return Printer status
AH
2, DL
0
Use Under an Operating System.
WINCHESTER ROM
.'
Limitations.
System Interface
System RAM U!lage
Pover-up Testing
Booting from the Winchester
Error Recovery.
Error Reporting
Hardware Interface Routine!l
Initialize Winchester Disk System.
Check Winche!lter ROM Version
Reque!lt Controller Error Sense.
Send Winchester Controller Command
Get Data From the Winchester Controller.
Write Data to the Winchester Controller.
Get Status From Winchester Controller
Get and Compare Data From the
Winchester Controller
Enable Data and Status Interrupt
from Controller

4.12.8
4.12.9
4.12.10
4.12.11
4.12.12
4.12.13
4.12.14
4.12.15
4.12.15.1
4.12.15,2
4.12.15.3
4.12.15.4
4.12.15.5
4.12.16
4.12.17
4.13
4.13.1
4.13.2
4.13.3
4.13.4
4.14
4.14.1
4.14.2
4.14.3
4.14.4
4.14.5
4.14.6
4.14.7
4.14.8
4.14.8.1
4.14.8.2
4.14.8.3
4.14.8.4
4.14.8.5
4.14.8.6
4.14.8.7
4.14.8.8
4.14.8.9

=

=

=
=
=

=

-x-

4-44
4-45
4-45
4-46
4-46
4-47
4-48
4-49
4-52
4-53
4-53
4-54
4-54
4-55
4-55
4-55
4-56
4-56
4-56
4-56
4-57
4-60
4-60
4-60
4-60
4-62
4-63
4-63
4-64
4-64
4-65
4-66
4-66
4-67
4-69
4-70
4-70
4-71
4-71
4-71
4-72
4-72
4-73
4-73

'\
J

TECHNICAL REFERENCE
section
4.14.8.10
4.14.8.11
4.14.8.12
4.14.8.13
4.14.8.14
4.14.8.15
4.14.8.16
4.14.8.17

CONTENTS
Title

Page

Enable status Interrupt From Controller.
Disable Data and StatuG Interrupt From
Controller.
Poll for Controller Request.
Format a Track .
Format an Alternate Track
Format a Track as Bad.
Check the Track Format
Format a Winchester Drive

4-73
4-74
4-74
4-74
4-75
4-75
4-76
4-76

5

ASSEMBLY DRAWINGS AND LISTS OF MATERIALS

.

5-1

6

SCHEMATICS AND LOGIC DRAWINGS

.

6-1

APPENDIXES
A
B
C

o
E

F
G

H

System I/O Ma.p.
System Memory Map.
Character set
Current Requirements.
Asynchronous Communications Sample
Program
Modem Sample Routines
Boot Routine and Sample Assembly Code
Sample Interrupt Service Routine~

-xi-

A-l
B-1
C-1
0-1

E-1
F-1
G-l
H-1

ILLUSTRATIONS

TECHNICAL REFERENCE

List of Illustrations
Title

Figure
No.
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9

4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8

Page

System Block Diagram.
Motherboard Block Diagram
Memory System Timing Diagram
Floppy Disk Timing Diagrams
Alphanumeric CRT Controller Board Block Diagram.
Alphanumerics State Machine Timing Diagram
Sample Character Font Definition.
Encoding Examples.
_Expansion Bus ~emory Interface Timing Diagram
Expansion Bus I/O Interface Timing Diagram

2-2
2-9
2-25
2-29
2-38
2-40
2-53
2-54
2-60
2-61

Expansion Memory Timing Diagram .
Sync-Async Comm Board Block Diagram.
Modem Hardvare Interface
Zilog 8530--Modem Interface Signals.
Graphici Vide~ Controller Board Block Diagram
Color Latch Byte
Graphics Video Controller Timing Diagram .
Controller Operational Flovchart.
Control and Data Cabling for the Kinchester Disk
Drive.
"

3-7
3-8
3-15
3-16
3-25
3-29
3-32
3-42

Register AL Drive Byte
Byte Definition - Set Cursor Type
Byte Definition
Set Attribute(s)
CIT Structure
Byte Definition - Keyboard Modes,
General Keyboard Layout Shoving Scan Codes
Byte Definition - Keycode
Byte Definition - Return Printer Status

4-16
4-23
4-32
4-42
4-45
4-48
4-59
4-62

-xii-

\

3-72

TECHNICAL REFERENCE

TABLES

List of Tables
Table
No.
1-1
1-2
1-3
1-4

2-1
2-2
2-~

__ _

2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-'15
2-16

2-1'7
2-18
2-19
2-20
3-1
3-2

3-3
3-4

3-5
3-6

3-7
3-8

3-9
3-10

3-11
3-12
3-13
3-14

3-15
3-16
3-17

Title

Page

storage Conditions, Standard System.
Operating Conditions, Standard System
Storage Conditions,
System with Winchester Disk
Operating Conditions,
System with Winchester
Disk .

1-4
1-5
1-5

Keyboard Commands and Responses
Map of the Motherboard I/O Addresses
Input/Outp~_t Signals - HAL12L6 Integrated Circuit
Printer Port Pin-Out.
Interrupt Level ASSignments
Motherboard Memory Map .
ROM Access Times
Memory Control State Machine Logic - HAL16R4.
Programming for the HAL10L8 Device
Inter~al Diskette Drive Connector Pin-out.
External Diskette Drive Connector Pin-Out.
Diskette Drive Specifications.
VIDEO AC PARAMETERS .
Color Video Connector Pin-Out.
CRTC Programming Values.
Alphanumerics State Machine PAL
CRT System Memory Map
Alphanumeric Decoding PAL
Color Map
Expansion Bus Pin-Outs

2-5
2-13
2-15
2-17
2-19

Expansion Memory Control State Machine Logit HAL16R4 .
Sync-Async Comm Board Baud Rate .
Sync-Async Comm Board Port Addresses
Channel B Pin-out for Z8530
Channel B Pin-out for Z8530 Interrupt Enable.
RS-232-C Connector Signals.
Modem Default Parameters
Types and Durations of Disconnects
Commands from the Software to the Modem
Response from the Modem to the' Software
Diagnostic Status Indicators
Color Combinations
Bit Correlations
Default Values of Color Lat'ches
Programming for the Graphics State Machine HAL
Device Control Block Bit Diagram,
Command Descriptor Byte.

-xiii-

1-6

2-20
2-21
2-24
2-28

2-33
2-34
2-36
2-39
2-44
2-46
2-49

2-51
2-52
2-56
2-57

3-5
3-10

3-12
3-13'

3-13
3-14
3-18
3-'21

3-23
3-24

3-24
3-28
3-29
3-30

3-33
3-35

3-36

TABLES

TECHNICAL REFERENCE
Table
Ho.
3-18

3-19
3-20

3-21
3-22
3-23

3-24
3-25
3-26
3-27
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10

4-11
4-12
4-13

4-14

Title
Winchester Controller I/O Port Assignment.
Bit Definitions for Controller Registers and
Ports.
Valid Bit Combinations for Controller Status.
Type 0 Error Codes, Winchester Disx.
Type 1 Error Codes, Controller Board
Types 2 and 3 Error Codes, Command and
Miscellaneous .
Error Code Summary
Sector Field Format
512-Bytes-Per-Sector Format
Winchester Controller Board Specifications
System Interrupt Vector Usage.
ROM Addresses and Suggested Uses.
JOinter addres!es and Descriptions
System. Configuration Word-Bit Oefinition
Extra System Configuration Word 1 (BX).
CRT DSR Opcodes and Functions.
Disx DSR Opcodes and Functions
Error Codes.
Keyboard Commands.
Standard-Keyboard Character Codes
Extended Function Codes.
RAM Segment Pointers.
Winchester DSR Error Codes.
Displayed Error Codes

-xiv-

Page
3-:38

3-41
3-42
3-46
3-47
3-48
3-49
:3-69
:3-70
3-71

4-5
4-8
4-12
4-14
4-15
4-22
4-35
4-41
4-46
4-49
4-52
4-65
4-67
4-·68

INTRODUCTION

TECHNICAL REFERENCE

Section 1
INTRODUCTION

1.1

SYSTEM COMPONENTS

The basic Texas Instruments Professional Computer system consists of
three major parts:
the keyboard,
the
system unit
(including
the
diskette
drive),
and
a
monochrome display unit.
A general
description of each is given in this section.
The available
options
are also -briefly descr-i-bed
in
this
section.
For more detailed
information, refer to Section 2, "System Hardvare", and to Section 3,
"Hardvare Options."
1.1.1

Keyboard

The loy-profile keyboard is easy
to
use.
The large,
sculptured,
typevriter-like keys grouped on the main keyboard are used to enter
alphanumeric data.
The smaller numeric keypad on the right
side of
the keyboard can be used as a calculator.
A five-key cluster betveen
these
tvo groups controls
the display cursor movement.
Tvelve
programmable function keys are arranged in three groups of four
keys
each across the top of the keyboard.
Other keyboard features include:

*

A full-length
degrees.

*

The sculptured, loy-profile keys,
vhich comply vith
the
European 30-millimeter (mm) home roy height requirements.

*

Tactile-designed F and
J
keys,
vhich help to locate the
"home" position on the alphanumeric keys.'

*

A raised dot on the numeric keypad 5, indicating the
key.

*

A keyboard microprocessor,
vhich converts keystrokes into
character information and conducts keyboard diagnostics
on
every poyer-up.

tilt-bar,

adjustable

1-1

from

5 degrees to 15

center

TECHNICAL REFERENCE

1.1.2

INTRODUCTION

System Unit

The
system
unit
is
the heart of
the computer.
The basic
configuration includes the central processing unit (CPU), the floppy
disk controller
(FOe), a parallel printer port, a poyer supply, a
read-only memory (ROM), and 64K bytes
(K = 1024) dynamic randomaccess memory (RAM).
A cathode-ray tube (CRT) controller board is
standard equipment.
The system unit board is a 361.95 x 215.9-millimeter
(mm)
(14.25 x
9.5-inch (in» printed viring board (PNS) mounted horizontally on the
bottom
of
the
system unit chassis.
This board houses
the
microprocessor and control logic.
It also supports an expansion bus
vith
five card-edge connectors for option boards and another
connector for a memory expansion option.
The system unit poyer supply is a sVitching-type, 110-vatt
(N)
unit
vith three output levels.
It vill sustain a system equipped vith
every combination of options.
The 5 1/4-in diskette drive is a mass storage device for reading or
vriting
data to a
removable diskette.
The Texas
Instruments
Professional Computer uses a
double-density,
modified frequency
modulation
(MPM)
recording format.
This format requires certified
double-sided, dual-denSity, soft-sectored 5 1/4-in diskettes.
The'
data
separation
logic
uses a phase-lock loop technique for~
reliability.
The computer is equipped vith one diskette drive, vhich
can store approximately 320K byt.s of data.
1.1.3

Display Unit

The display unit furnished with the Texas Instruments' Professional
Computer is a high-resolution (720 x 300 pixels), composite video,
green phosphor monochrome unit.
The standard
CRT
controller
contained in the system unit supports eight intensity levels for the
display.
The display presents information -in a
25-line--x 90-column
alphanumeric ~ormat,
vhich yorks yell vith the bit-mapped graphics
option.
The display unit is specially adapted
to accomodate the
horizontal scan rate of 19 200 lines per second .

1.2

OPTIONAL COMPONENTS

There are several options available for
the Texas Instruments
Professional Computer.
These options
include additional 320K-byte
diskette drives,
a
Ninchester disk drive, expansion memory boards
(vhich can expand the system memory to 769K bytes),
a
synchronousasynchronous communications board, internal modem boards, a graphics
video controller board, and a high-resolution color display unit.
A
general description of each of
these options
is given in the
1-2

IHTRODUCTION

TECHNICAL REFERENCE

folloving paragraphs.
If more detailed information is needed,
to Section 3, Hardvare Options.
1.2.1

refer

Diskette Drive

dri ve
is' standard equ ipmen t for The Texas
One
internal di ske t t e
Professional Computer.
Enough
internal
space
is
Instruments
install either a second diskette drive or a Hinchester
available
to
You can also insta~l tvo external drives.
disk drive.
Diskettes used vith the Texas Instruments Professional computer must
be certified double-sided,
dual-density,
soft-sectored,
5 1/4-in
diskettes.
1.2.2

Hin--chester Disk Dr-tve

The Hinchester disk drive and controller option is available in 5- or
10-megabyte capacities.
You can install the Hinchester disk drive in
the space set aside for the second diskette drive.
1.2.3

Expansion Memory Boards

The system unit board contains 64K bytes
of dynamic RAM.
Adding
expansiDn RAM boards
can
increase the system memory to a total of
76BK bytes.
First, use the expansion RAM option boards
that
plug
into
the memory connector on
the motherboard.
These boards are
available in 64K-, 12BK-, or 192K-byte capacities.
After adding
the
192K-byte board (bringing the total to 256K bytes), further ex.pansion
requires that you add a 256K-byte board that plugs into the expansion
bus.
To reach the 76BK-byte total. another 256K-byte board attaches
(piggyback style) to the board on the e~pansion bus.
1.2.4

Synchronous-Asynchronous Communications Board

The synchronous-asynchronous communications (sync-async
comm)
board
option allovs
either synchronous
or asynchronous
communications
through an RS-232-C interface.
The sync-async comm board
supports
asynchronous data rates from 50 bits per second (bps) to 19 200 bps.
1.2.5

Internal Modem Boards

Tvo versions
of
the
internal modem board option are available:
300-bps board providing Bell 103-compatible communication,
and
300/1200-bps board providing Bell 212A~compatible communications.

1-3

a
a

TECHNICAL REFERENCE

1.2.6

INTRODUCTION

Graphics Video Controller Board

The graphics video controller board option is available in either one
or three planes.
It provides a resolution of 720 horizontal by 300
vertical picture elements
(pixels).
1.2.7

Color Display Unit

The 13-in color disp1ay unit permits the display of high-resolution
(720 x 300 pixels) colors.
The standard CRT controller located on
the system unit board supports eight colors for the unit, vhich
presents information in a 25-line x SO-column format.
Used vith the
graphics video controller board option,
the color display unit
produces high-quality raster and character graphics.

1.3

ENVIRONMENTAL CONDITIONS

The next four tables list
environmental conditions for
the Texas
Instruments Professional Computer.
Table 1-1 lists
the storage
conditions for a standard system.
(Storage assumes that
the system
is enclosed iri -the ~hipping container.)
Table 1-2 lists
the
operating conditions for a standard system.
Table 1-3 lists
the
storage conditions for a
system that includes a Winchester disk.
Table 1-4 lists the operating conditions for a system that includes a
Winchester disk.
Table 1-1

Storage Conditions, Standard System

Temperature

-30 C t~ +70·-C
(50 C maximum for diskette)

Relative humidity

10~

Shock

30
30
20
30

Vibration

Sinusoidal, 5 to 250 Hz linear
.veep at 1 octave/minute vith
0.50 input.
Dvell 15 minutes at
resonant points (2% input level.)

Altitude

45 000 feet maximum

1-4

to

90~,

no condensation

Gs, half-sinusoidal pulse vith
ms ~uration along ~ ~d y axes,
Gs, half-sinusoidal pulse vith
ms duration along Z axis.

TECHHICAL REFEREHCE

Table 1-2

IHTRODUCTIOH

Operating Conditions, Standard System

Temperature

+10 C to +40 C with gradient
less than 10 C per hour

Relative humidity

20~

Shock

5 Gs, half-sinusoidal pulse with
10 ms duration along any of the
three perpendicular axes.

Vibration

0.5 Gs peak accelleration in the
range of 5 to 250 Hz, linear sweep
at 1 octave/minute.

Altitude

10 000 feet maximum

to

80~,

no condensation

HOTE
Derate
the upper
limit
of
the
operating
temperature by 1 C for every 1000 feet above the
first SOO feet.

Table 1-3

Storage Conditions,

System with Kinchester Disk

Temperature

-30 C to +60 C with gradient
less than 10 C per hour

Relative humidity

20~

Shock

30 Gs, half-~inusoidal pulse with
11 ms duration.

Vibration

20 Ge, half-sinusoidal pulse with
11 ms duration.

Altitude

30 000 feet maximum
10 000 feet unpreseurized

1-5

to

80~,no

co~densation

TECHNICAL REFERENCE

Table 1-4

INTRODUCTION

Operating Conditions,

System vith Winchester Disk

Temperature

+10 C to +40 C vith gradient
less than 10 C per hour

Relative humidity

20' to 80'.

no condensation

5 Gs, half-sinusoidal pulse vith
the
three perpendicular axes.

Shock

10 ms duration along any of

Vibration

0.5 Gs peak acceleration in the
range of 5 to 250 HZ, linear sweep
at 1 octave/minute.

Altitude

10 000 feet maximum

NOTE
Derate
the upper
limit
of
the
operating
temperature by 1 C for every 1000 feet above the
first 500 feet.

1-6

SYSTEM HARDWARE

TECHNICAL REFERENCE

section 2
SYSTEM HARDWARE

2.1

INTRODUCTION

This section describes the design and functions of
the hardvare
in
the
standard
Texas
Instruments Professional Computer
system.
Hardvare described in this section includes the keyboard, the
system
unit
boar¢ .and
its tVQ~logical subdivisions, and the display unit.
Figure 2-1 is a block diagram of
the
system shoving
the
separate
hardvare
components, including some options.
The option hardvare is
described in Section 3, "Hardvare Options."

2-1

TECHNICAL REFERENCE

SYSTEH HARDWARE

'il ~

CONTROLLER BOARD ,OPTION'

.. .......
,

III I III....--!

""'NCHESTER DIS' .DPTID~

~

INTERNAL MODEM BOARD
'OPTION I 212 OR 103

[
[ .--------

lI'IIII,r-

CLOCK AND ANALDG INTERFACE
_.BOARP ,DPT,ION'

III"'"

320K
DISKETTE
DRIVE

320K
DISKETTE
DRIVE
IOPTIONI

IMOTHERBOARD

IIIr--

114---'SYSTEM UNIT BOARD •

.---11---- CRT CONTROLLER BOARD

+

GRAPHICS VIDEO CONTROLLER
'OP'TION'

T
EXPANSIO', RAM
BOARD 'OPTION'

64K
128K OR 192K

,
\
I

/

I

I

Iii i

I

I

I

i I

I

I

I

~

-=

=

-~

COLOR DISPL!lY UNIT
IOPTIONI

PARALLEL PRINTER
CABLE IOPTIONI

SERIAL PRINTER
CABLE {OPTIONI

MODEMCA8LE
tQPTIONJ

2223216-1

Figure 2-1

System

Bl~ck

2-2

Diagram

SYSTEM HARDWARE

TECHNICAL REFERENCE

2.2

KEYBOARD

The electronic functions of the keyboard include:

*

Scanning the key matrix and encoding keys depressed "by
operator

*
*
*
*
*
*

Transmitting data to the system unit

2.2.1

the

Receiving and responding to commands from the system unit
Implementing a software-switchable repeat-action function
Performing n-key rollover
Locking/unlocking the keyboard
Performing a self-test
Encoding Keystrokes

The encoder scans the keyswitch matrix, detects valid keyswitch state
changes,
looks up the proper key code, and transmits the keycode as
part of an 11-bit stream to the system unit.
Each key caus.s either
1 or 2 bytes
to be transmitted, based on the status of the SHIFT,
ALT, CAPS LOCK, and CTRL keys~
For specific details on byte
definitions, refer to subsection 4.12.
Some user-programming of
the function keys is possible at the
application level.
See the paragraph in Section 2 entitled,
"custom
Encoding."
2.2.2

Transmission

The keyboard
transmits data to the system unit at 2440 baud ~ 1.50
percent.
The keyboard transmits when one of the following conditions
is met:

*
*

When a valid key depression has been detected
When a system command is understood and acted upon

Khen the user presses a key, the keyboard responds by sending the
proper keycode byte. or bytes across
the keyboard transmit line.
Keycodes are explained in detail in subsection 4.12
entitled
"Keyboard
DSR."
Pressing some keys can si9nal repeat-action
transmissions.

2-3

TECHNICAL REFERENCE

2.2.3

SYSTEM HARDHARE

Receiving and Responding to System Unit Commands

The system unit transmits to the keyboard at 305 baud ~ 1.50 percent.
To respond to a
system unit
command,
the keyboard
transmits a
response code to the system unit, indicating that the required action
has been
taken.
The keyboard responds to every valid command.
For
certain conditions, such as parity errors,
unknown
commands,
and
start
bit
errors, the keyboard ingores the system unit commands and
sends no response.
If this happens,
the system unit
retries
the
command.
System
unit
commands
and keyboard
responses are
listed,
in
hexadecimal form, in Table 2-1.
In this table,
the
"Command Code"
column lists the codes sent to the keyboard.
The "Keyboard Response"
column lists
the code returned by
the keyboard microprocessor.
Typically; themicroproc~ssor returns Self-test OK (code 70)
to
the
system unit (except in the case of a failure during self-test).
HOTE
Throughout
this manual,
the symbol H denotes a
hexadecimal address or value.

2-4

TECHNICAL REFERENCE

Table 2-1

SYSTEM HARDWARE

Keyboard Commands and Responses

System Uni t
Command

Command
Code
(H)

Keyboard
Response

Perform a pover-up
self-test and install
default parameters

00*

10
71
12

Self-test OK
Keyboard ROM error
Keyboard RAM error

Turn repeat action QJi
Turn repeat action .Q.f.E

01*
02

10
10

Self-test OK
Self-test OK

Lock keyboard
Unlock keyboard

03
04*

70
10

Self-test OK
Self-test OK

Turn keyclick Q1!
Turn keyclick Qfi

05**
06**

10
10

Self-test OK
Self-test OK

Reset

(same as 00)

01

10
11
12

Self-test OK
Keyboard ROM error
Keyboard RAM error

Return version
(of keyboard ROM) .

08

10,13

(2-byte code)

(H)

* Indicates default values.
** Keyclick requires a hardvare modification.
It is not presently supported.

2-5

Response
Meaning

TECHNICAL REFERENCE

2.2.4

SYSTEM HARDWARE

Implementing a Software-Switchable Repeat-Action Function

A repeat-action key is one that automatically repeats when depressed
for
one-half second (s) or longer.
As long as the key is held down,
repeat-action transmissions from the keyboard
to
the
system unit
continue at a rate of 15 per second.
2.2.5

Performing n-Key Rollover

Repeat-action
interacts with n-key rollover in the following manner.
Pressing more than one nonmode key does not cause repeat-action.
Instead,
the most
recent key pressed transmits to the system unit,
When repeat-action is enabled and one k~y is pressed,
that key is
acted
upon by the repeat-action function.
The following examples
clarify the relationship between rollover,
repeat-action,
and mode
byte changes.
Example 1:
Assume that the following sequence of events occurs:
1. No mode bits are on.
2. The ~ key is depressed and held down for more than one-half
second.
3. The b key is depressed.
4. The SHIFT key is depressed.
(The SHIFT key can be held or
released without altering the characters transmitted to the
system unit.)
5. The b key is released.
6. The

~

key has not yet been released.

The result transmitted to the system unit and displayed is:
aaaaaaaaaaaaaabaaaaaaaaaaa ...

2-6

SYSTEM HARDWARE

TECHNICAL REFERENCE

Example 2:
Assume that the following sequence of events occurs:
1. No mode bits are on.
2. The a key is depressed and held down for more than one-half
second.
3.

The SHIFT key is depressed and held.

4.

(At this point, the SHIFT key can
The b key is depressed.
without
altering
the characters
be
held or released
transmitted to th_~ system un it. )

5. The b key is released.
6. The
The result

a

key has not yet been released.

transmi"tted to the system unit and displayed is:

aaaaaaaaaaaaaaBAAAAAAAAAAA ...
2.2.6

Locking/Unlocking the Keyboard

At certain times during system operation. the keyboard locks.
During
these times, all normal functions
of
the keyboard are
suspended.
That
is, the keyboard does not scan, encode, or transmit data to the
system unit.
The keyboard locks if:

*
*
*

The self-test is in progress.
The self-test fails.
The keyboard receives the LOCK KEYBOARD command.

The keyboard remains locked un til one'
occurs:

*
*
2.2.7

of

the

following

conditions

The self-test successfully completes.
The keyboard receives the UNLOCK KEYBOARD command.
Performing a Self-Test

The keyboard performs a self-test when it receives code 00 from the
system unit, interrupting any keyboard operation
in progress.
The
2-7

TECHNICAL REFERENCE

SYSTEM HARDWARE

self-test
completely checks
the keyboard system RAM and ROM, then
transmits the results to the system unit using a
code explained in
paragraph 2.2.3,
entitled "Receiving and Responding to System Unit
Commands .••

2.3

SYSTEM UNIT BOARD

The system unit board, or motherboard, is the heart of the computer.
It
is mounted on
the bottom of
the system unit chassis.
The
motherboard is divided into
two logical function areas,
one for
system support and one for the expansion bus.
Refer to Section 5,
drawing 2223005, for logic diagrams of the system unit board.
Figure
2-2 is a block diagram of the separate subsystems of the motherboard.

2-9

>i

~J

-

u
c- I-

..:
..........

808B
CPU

-

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'-~

I

It-

u

--

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'--~

SOCKET
RESERVED
FOR

8087
NUMERIC
CO PRO·
CESSOR

I-

l-

u

..:

RAMs
64K
SYSTEM MEMORY

U

W

~nrI

I-

::::J

i..S-

~

~

CD

I\)

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8288
BUS
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I---

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n
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t<

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Il.

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SYSTEM DATA BUS

SYSTEM DATA BUS

BUFCERt

til
tO
0

8251
KEYBOARD

LOG

8253·5
TRIPLE
TIMERS

>r'

I

0

....
III

.,

IQ

KEYBOARD
BUFFERS

FLOPPY DISK
CONTROL LOG I--

In
I

I

SPEAKER
AMP

FOC CONTROL LINES

1

FDC DATA BUS
1/0 DATA BUS

I

B259A
INTERRUPT
CONTROLLER

INTERRUPT
LOGIC

~

IBUFFERU

II II

I

I

1/0 DECODE

I
SYSTEM CONTROL BUS

0.

S

L---

.---

W

MEMORY
OECODEAND
RAM TIMING

~

0

III

I---

ADDRESS

X

:J'

,--

MEMORY DATA BUS

-

0

.,
0'
.,III

L--

r-

~

~

.---

~Ii

r9

II]

........
t;;;;;;;;J
KEYBOARD
CONNECTOR

r..................

PRINTER PORT

••••••••••••••••• 0

X

INTERNAL
DISKETTE DRIVE

:r:

rnl\ll\l~rTnR

IPAR.o.I I 1=1 I

~

;r:::::::::::::::::: I

!XI

o

CONNECTOR

2:

2223216·2

>

!XI
trI

TECHNICAL REFERENCE

2.4

SYSTEM HARDWARE

SYSTEM SUPPORT

That section of the motherboard dedicated to system support
hardvare and logic for the:

*
*
*
*
*
*
*
2.4.1

contains

Keyboard port
microprocessors,

System
CPU
(including
controllers, and buffers)

clocks,

bus

Motherboard input/output (I/O) system
Motherboard interrupt system
Motherboard .emory system
FDC subsystem (including buffers, vrite precompensation, and
diskette drive interface)
CRT controller

Keyboard Port

a
universal asynchronous
receiver-transmitter
The Intel 8251A,
(UART),
is
the port for serial data
transmission betveen the
Data received by the UART alvays
motherboard and the keyboard.
to
the interrupt controller.
The transmit
generates an interrupt
transmitter in
ready line does not generate an interrupt unless the
The keyboard port interrupt isORed vith the
the UART is enabled.
"interrupt request 1" line from the nu.eri~ coprocessor.
An SN15189A line receiver vith a slovdovn _capacitor. c~n~itions
the
receive data signal
to protect
the signal from transients.
The
receiver hysteresis is approximately 1 V centered around 1.4 V, vhich
improves the noise immunity.
Another SN15189A buffers
the
transmit
data line,
providing a good voltage sving and drive to the keyboard
cable.
This buffer consists internally of an output transistor vith
a 2-kilo ohms (kohms) pullup resistor.
To improve diagnostics,
the data set ready (DSR)
line on the
universal synchronous/asynchronous receiver
transmitter
(USART)
connects
to
the keyboard connector through a SN15189A buffer.
The
transmit data line connects to' the DSR line at
the keyboard,
vhich
alloys detection of a disconnected or defective keyboard.
The input clock to the transmit section is 19 531.25 Hz.
The 8251
divides this frequency by 64 to generate a baud rate of 305.
The
input clock for
the receiver
is 156 250 Hz.
This frequency is
2-10

SYSTEM HARDWARE

TECHNICAL REFERENCE

divided by 64 to generate a baud rate of 2441.
Because
these baud
rates are close to the standard 300- and 2400-baud rates, system test
instruments can simulate a keyboard vith standard equipment.
2.4.2

System CPU

The system CPU consists of an Intel 8088 16-bit microprocessor, the
CPU clock circuits, several CPU bus buffers and latches,
a
CPU bus
controller,
and
the
reset
circuit.
A special
socket
on
the
motherboard makes it easy to add the optional Intel 8087 numeric data
processor (also called a numeric coprocessor).
The Intel microprocessors york together and, to attached
components.
appear to be a single chip.
Therefore, the term CPU (as used in this
manual) refer~ to both devices.
2.4.2.1 Optional Numeric Coprocessor.
The user can choose to add an
8087 numeric coprocessor to the system unit board at any time.
Once
the 8087 is inserted into the socket provided, both the 8088 and
the
8087 decode
the
special escape
instructions.
The 8088 does any
memory-access computations required and accesses the
first
byte of
memory
according·.
to
the
instruction.
The 8087 decodes
the
instruction, "catches" the memory address generated by
the
8088,
requests
the
bus
from
the 8088, and completes the required memory
access.
After finishing vith the bus, the coprocessor releases it so
that the 8088 can continue vith the next instruction.
If necessary,
the 8088 sends a
WAIT
instruction
to
the 8087. ensuring their
synchronization.
2.4.2.2 CPU Clock Generator.
The CPU clock generator consists of an
Intel-designed 8284, a crystal, and
some discrete
components.
To
generate
the 5.0 MHz clock frequency, the 8284 divides the crystal
frequency (15.0 MHz ~ 0.01 percent) by 3.
The 8284 also
contains
logic to· synchronize the HAIT- line from the expansion bus and memory
subsystems vith the RESET- line from the pover-good circuit.
NOTE
Signal names
followed by a dash,
are active low signals.

such as HAIT-,

2.4.2.3 CPU Bus
Buffering.
The CPU operates
in
the
so-called
"maximum"
mode
of
this
integrated circuit.
(For additional
information,
see ·the
Intel
literature on
the
8088
and
8087
microprocessors.)
The CPU uses a multiplexed address and data bus in
order
to
reduce
the number of pins required on the processor chip.
For this reason, and to provide adequate buffering for
the address
and data lines
on the expansion bus, a set of address latChes (US,
U6, U7) and a data bus buffer (U8) are an integral part of the CPU.

2-11

TECHNICAL REFERENCE

SYSTEM HARDWARE

2.4.2.4 CPU Bus Controller.
The CPU bus controller chip
(U3 8288)
receives
the
status
information from the processor and converts it
into the lines KRDC- (memory read), AMWC(advanced memory vrite),
IORC(I/O read),
AIOWC(advanced
I/O vrite),
IHTA (interrupt
acknovledge),
OEM
(data buffer enable),
and
DTR
(data
buffer
direction control).
A simple open-loop signature analysis (SA) arrangement is provided to
check out the CPU.
Connecting pins E17 and £18 (on the motherboard)
vith a
jumper and
resetting
the
system
(pover up)
causes
the
processor
to execute a OBFH opcode.
The jumper disables the system
data bus buffer U8, and the pullup resistors in U66 pull the bus
up
to a
high state.
Transistor Q1 pulls dovn data line AD6 to provide
the "0" bit in the opcode.
The segmented architecture
then
causes
the processor to cycle from address FFFFOH through address FFFFFH and
from OOOOOH through OFFFOH during the SA loop.
HOTE
The
symbol
value.

"H" denotes a hexadecimal address or

2.4.2.5 Reset Detection Circuit.
The pover-good
(reset
detection)
circuit discovers insufficient pover conditions on the motherboard by
monitoring
the 12-volt
(V)
pover line.
Khen the pover drops, but
does not shut dovn completely,
this
circuit
causes an automatic
restart.
If
the
voltage
falls
to approximately 11 Vdc,
a
resistor/capacitor combination and a
voltagecomparator
vith
transistor
inverter hold
the RESET line
true
for at
least
3
milliseconds (ms).
2.4.3

Motherboard Input/Output System

The motherboard input/output (I/O) system decodes the
i/o addresses
for all
the devices on the board.
The input buffer and the various
Table
2-2
output latches are also components of
the
I/O system.
sho~s a map of the motherboard I/O addresses.
The various I/O devices have available 16 I/O address bits.
Only 10
of these bits, a total of 1024 bytes,
are decoded.
Beginning at
address
OOOH,
the motherboard
uses
48 bytes of this space.
This
leaves 976 bytes available for the expansion bus.
Table 2-2 lists the motherboard devices that are decoded and
their
addresses
~ithin
the CPU I/O space.
Appendix A provides a complete
map of all system I/O addresses.

2-12

TBCHHICAL REFEREHCB

Table 2-2

SYSTEM HARDWARE

Map of the Motherboard I/O Addresses

Hex
Address

Device

Bit/Use

00000

U41 Latch

o
1
2
3
4
5
6
1

Speaker timer enable
Timer 1 interrupt enable
Timer 2 interrupt enable
Single-density (FM) enable
Track greater than 1/2 (TG43)
Diskette side'one enable (FSID-)
Diskette mode control (M1)
Diskette mode control (MO)

00001

U48 Input buffer

o

Option jumper E1-E2
Option jumper E3-E4
Option jumper E5-E6
Parity interrupt pending
Printer port BUSY
Printer port paper out
Printer port printer selected
Printer port HO fault

1
2
3
4
5
6
1
00002
00003

U49 Latch
U50 Latch

00004

U51 Latch

0-1
o
1
2
3
4
5
6
1

o
1
2
3
4
5
6
1

Printer port data" outputs
LED 1 OFF
LED.2 OFF
LED 3 OFF
Parity interrupt enable
Printer port not autofeed
Printer port not strobe
Printer port not initialize
Printer ACK interrupt enable
Diskette
Diskette
Diskette
Diskette
Diskette
Diskette
Diskette
Disk~tte

2-13

drive
drive
drive
drive
drive
drive
drive
drive

SELECT
SELECT
SELECT
SELECT
MOTOR
MOTOR
MOTOR
MOTOR

1,f..2 ~~
3 -l,
4·~

1
2
3
4

SYSTEM HARDWARE

TECHNICAL REFERENCE

Table 2-2.

Map of the Motherboard I/O Addresses (Concluded)

Hex
Address

Device

00005--0000F
00010
00011
00012--00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024--0002F

Reserved
U44 8251 US ART
U44 8251 USART
Reserved
U45 8253 timer
U45 8253 timer
U45 8253 timer
U45 8253 timer
U46 8259A interrupt controller
U46 8259A interrupt controller
FoC command register or RAM
FoC track register
FOC sector register or RAM reset
FoC data register
Reserved

Bit/Use

2-14

Data register
Control register
Counter
Counter
Counter
Control

0
1
2
register

SYSTEM HARDWARE

TECHNICAL REFERENCE

2.4.3.1
I/O Decoding.
A combination of
three
integrated circuits
(IC) does the I/O decoding.
The first Ie is a hard-array-Iogic (HAL)
device HAL12L6.
The
second
is a 74LS138, ~hich is a one-of-eight
decoder.
The third is one-half of a dual 74LS139, ~hich is a one-offour decoder.
Table 2-3 gives the array logic device programming.
When the logical
AND of terms from one roy is ORed ~ith the AND of terms from another
roy
in
the
same
section,
the output goes active if the result is
true.
Expressed in Boolean terms,
IORQ

=

(XS2 x XSl x XSO x IORC)

Table

+

(XS2 x XS1 x XSO X AIOWC)

Input/Output Signals - HAL12L6 Integrated Circuit

~-3

Input
XSO

XS2
output

XSl

.. XA9
XA7
XA5
IORCAIOWCXA4
DEH- XA8
XA6

comment

-------+--+--+--+--+--+--+--+--+--+--+--+----------------------------Read I/O
IENL L H L L L L L L
or L
or L
or .

H
L

L
L

L
L

L

L

L

L

L

L

L

.Write I/O
Interrupt acknovledge
Inactive term

~------+--+--+--+--+--+--+--+--+--+--+--+-----------------------------

XCS-

L
or L

L
H

H

or L

H

L

FLCS- L
or L

H

L

L

L

L

L

H

L

H

L

L

L

L

L

L

L

L
L

L

L
L

L
L

L

L

L

L

H
H

L

Read I/O at 74LS139
Write I/O at 74LS139

L

Write 1/0/

L

-------+--+--+--+--+--+--+--+--+--+--+--+----------------------------IORQ- L
L
H
Read I/O
L
-------+--+--+--+--+--+--+--+--+--+--+--+----------------------------L H
Read diskette
L L L L H L
Write diskette

-------+--+--+--+--+--+--+--+--+--+--+--+----------------------------L L H
Read I/O at 74LS138
L L L L L L L

YCS-

or L

L

Write I/O at 74LS138

-------+--+--+--+--+--+--+--+--+--+--+--+----------------------------Halt

XXXX- H
or
or .
or

L

L
L

-------+--+--+--+--+--+--+--+--+--+--+--+----------------------------~-

Legend:
L = Lov signal.
H = High signal.

2-15

TECHNICAL REFERENCE

SYSTEM HAROH'ARE

2 .•. 3.2 Parallel Printer Port.
Printers with Centronics-compatible
interfaces
use
the parallel printer port.
This port contains a 25pin female. O-type connector.
The basic signals are the output data lines
from U44,
the PTSTRsignal
that
strobes
the data
into the printer, and the PBUSY and
PACK- lines, which indicate to the CPU
the printer's
readiness
to
receive a
character.
In regular printer operation, the PBUSY line
goes high when the printer is not ready to receive a
character and
low when the printer can accept a character.
The PACK- line goes low
for a
short
time when
the printer finishes
with
the
current
character.
The rising edge of this line generates an interrupt
when
printer
interrupts are enabled by the PTEH line.
This interrupt is
ORed with the "interrupt request 5" line on the expansion bus.
The pin-o-utof the port--is given in Table 2-..
Pin numbers
for
the
36-pin printer connector (at the printer end of the cable) are given
in parentheses.
The extra lines are used for
various
control and
status functions associated with the printer port.

2-l.6

TECHNICAL REFERENCE

SYSTEM HARDWARE

Table 2-4

Printer Port Pin-Out

-------+-------+-------------+-----------+--------------------------+
Signal
IReturn 1 Signal Name I Source

ISignal

+-------+-------+-------------+-----------+------------------~-------+

19

1

IDATA STROBE- 1

I

System

1

1 Data is sampled when
1 signal is low.

+-------+-------+-------------+-----------+--------------------------+
1 Data output bit.
System
1 DATA 1
+-------+-------+-------------+-----------+--------------------------+
System
120(21)*1 DATA 2
+-------+-------+-------------+-----------+--------------------------+
System
1 DATA 3
+-------+-------+-------------+-----------+--------------------------+
System
5
121(23) I DATA 4
2

4

-.
+-------+-------+----------~-+-----------+--------------------------+

System

1 DATA 5

6

+-------+-------+-------------+-----------+--------------------------+
System
122(25) I DATA 6
7

+-------+----~--+-------------+-----------+--------------------------+

System

1 DATA 7

9

+-------+-------+-------------+-----------+--~~----------------------+
9

123 (27)

, DATA·· 9

System

+-------+-------+-------------+-----------+--------------------------+
10
'ACKNOWLEDGE- I Pr inter ., Ano ther charac t er
I

,

1 can be received.

.------+-------+-------------+-----------+--------------------------+
Printer
1 No data can be sent
124(29) I BUSY
11

I

1

I when signal is high.

I

I when signal is high.

I (ON LINE)

I when signal is high.

+-------+-------+-------------+-----------+--------------------------+
12
1 PAGE END
Printer
1 Printer is out of paper
+-------+-------+-------------+-----------+--------------------------+
13
I SLCT
Printer
J Printer is online
+-------+-------+-------------+-----------+--------------------------+
14
AUTO FEEDSystem
Printer is to line feed
, on carriage return

I when signal is low.

+-------+-------+-------------+-----------+--------------------------+
115(32) I
1 FAULTPrinter
'Indicates a fault
J

I

I

I when signal is low.

1

1

1

I signal is low.

+-------+-------+-------------+-----------+--------------------------+
116(31) 125(30) I INITSystem
1 Resets printer when
+-------+-------+-------------+-----------+--------------------------+
117(36) 119(33) I SELECTIONSystem
1 Always low.
+-------+-------+-------------+-----------+--------------------------+
* The numbers in parentheses are the pin numbers for the 36-pin
Centronics-type connector.

2-17

TECHNICAL REFERENCE

SYSTEM HARDWARE

2.4.3.3 Timers.
The 9253-5 counter/timer IC provides three separate
timing units.
In this sys t.em, one is used asa programmable speaker
oscillator, and the other two are programmable interval timers.
The speaker timer is clocked by a square wave of 1.25 MHz.
Divisors
up to 65 536 can generate output frequencies as low as 19 Hz.
The
high input frequency creates output tones
that are more musically
accurate.
The speaker
timer clock is internally gated with the
speaker enable (SPKEN), an output of latch U47.
This signal allows
the interruption of tones without a reprogramming of the timer.
The second timer (Timer A) is used in system-timing applications and
as a real-time clock.
It generates an interrupt signal on the rising
edge of the timer output when the enable line (address 0 bit 1)
is
set high.
Toggling this line low resets the interrupt; holding this
line low ~isables the interrupt completely.
The interrupt level
is
3.
The input clock frequency to the timer is 625 kilohertz (kHz).
A
divisor of 62 500 generates a pulsewidth of 100 ms, while a divisor
of 15 625 generates a pulsewidth of 2S ms.
The
third
timer
(Timer 8)
is used for special-purpose
timing
applications.
It generates an interrupt on the rising edge of the
timer output when the enable line (address 0 bit
2)
is set high.
Toggling this line low resets the interrupt; holding this line low
disables the interrupt completely.
This line is shared with the
expansion interrupt line IR2.
The interrupt level is 2.
The input
clock frequency to this timer is 625 kHz.
2.4.3.4 Speaker Amplifier. The speaker
timer output goes
to an
amplifier
(LM
3S6)
that drives
the 9-ohm speaker,
providing
sufficient volume and allowing mixing of sig~als from external
sources
(option expansion cards).
To mix other signals with this
Signal, connect any other signal source (such as
the speech option
board) to P12, the summing input.
2.4.4

Motherboard Interrupt System

The motherboard interrupt system can encode eight separate interrupts
and
vector
the central processor
to eight separate interrupt
routines.
A nonmaskable interrupt (NMI) (which produces the highestpriority interrupts) is also available.
The majority of the interrupt logic is contained within
the Intel
9259A interrupt controller chip.
The 9259A is programmed for levelsensitive input and is
the master
(only)
interrupt controller.
During the
INTA cycle, the decoding logic array always enables the
contents of the
I/O data bus onto
the system data bus.
This
information is
the vector from
the 9929A chip, and the system,
therefore, requires only one controller.
The 9259A chip assigns priority to the
incoming interrupts, allows
masking of interrupts, and provides the vector to the CPU during the
2-19

/

TECHNICAL REFERENCE

SYSTEM HARDWARE

interrupt acknovledge (INTA) cycle.
A series of OR gates and
flipflops permit some interrupt levels to be shared, cause some inputs to
be edge-triggered, and cause others to be level-triggered.
The
interrupts
that come from the expansion bus are active high and
are, therefore, terminated
vith a
4.7-kohm pulldovn
resistor
to
ground.
All the pulled-dovn inputs are connectied to the 82S9A chip,
either
directly or through a CMOS OR gate.
This connection prevents
the gate input current from raising the input voltage above the legal
"lov" level through the pulldovn resistor.
CAUTION
Even though the system is protected,
programmers
_and designers_ using interrupts on the expansion
bus· should be s-ure to "mask off" unused interrupt
lines as a matter of good programming practice.
The NMI detects parity errors on
the motherboard RAM system.
To
generate
this interrupt vith softvare, set the DTR line on the 82S1A
USART.
The RAM ca"Jl. then be tested vithout parity-error interruption.
The interrupt levels and their expected uses are given in Table 2-S.
Table 2-S
Interrupt

na

Use

Bus Line

NMI
IRO
IRl
IR2

A01
B04
B24
B25

IR3
IR4
IR6
IR7

na
B23
B21
na

= Not

Interrupt Level Assignments

System parity error, CRT interrupt
Communications port 1
Communications port 2
Communications port 3
System board timer 2
Local area net board buffer full/empty
System board timer 1 (clock)
Communications port 4
Diskette drive, Winchester disk
Keyboard, numeric coprocessor

applicable.

2-19

TECHNICAL REFERENCE

2.4.5

Motherboard Memory

SYSTEM HARDWARE

Sy~tem

The memory system on the motherboard consists of 64K bytes (K = 1024)
of dynamic RAM, up to 16K bytes of ROM, decoding logic
to establish
the addresses, and timing and refresh logic to operate the system~
A
connector and
the necessary logic permit the addition of one of the
expansion RAM boards.
These boards are available in 64K-, 128K-, and
192K-byte capacities.
After adding the 192K-byte board (bringing the
total to 256K bytes), further expansion requires the addition of a
256K-byte board
that plugs into the expan~ion bus.
(This board and
another memory expansion board are fully described in Section 3.)
2.4.5.1 Motherboard Memory Addressing.
The memory space of
processor devices used by the motherboard is given in Table 2-6.
balance o~ the' system m~ory is given in Appendix B.

Table 2-6
Address

Motherboard Kemory Map
Device

Dynamic RAM:
OOOOO-OFFFF
10000-lFFFF'
20000-2FFFF
30000-3FFFF

64K-bytes
64K-bytes
64K-bytes
64K-bytes

motherboard RAM
expansion RAM board bank 1
expansion RAM board bank 2
expansion RAM board bank 3

ROM Usage:
FCOOO-FDFFF
FEOOO-FFFFF

8K ROM space, one wait state (%U62)
8K system ROM, one wait state (U63)

2-20

the
The

TECHNICAL REFERENCE

SYSTEM HARDWARE

2.4.5.2
Memory
Control Logic.
A bidirectional
buffer
(U61)
separates the main system data bus
from
the motherboard
expansion
memory,
thereby providing
sufficient
drive and margin to the data
transfers.
U28,
the memory hard array logic chip HAL16R4,
in
combination vith U53,
the
74LS139 decoder,
handles decoding and
timing for the ROMs.
Because ROMs and EPROMs (erasable programmable
read-only memories) are generally slov devices, a vait state is added
to all accesses to these devices.
The ROM access times are listed in Table 2-7.
Table 2-7

ROM Access Times

Functr~n

Time Required
(in Nanoseconds)

CS-ROM access

410

ROM address access

577

I/O Wait States.
The HAL chip also contains the logic to add a vait
state to all I/O accesses made by
the CPU.
The
vait
state
is
necessary because many of the I/O devices operate too slovly vhen the
system buffer and setup and decode times are included.
With the vait
state, the control lin~s are active for approximately 600 nanoseconds
(ns) .
Memory Refresh Logic.
The RAM refresh logic operates synchronously
vith the accesses to the RAM memory.
Refresh cycles begin only vhen
a
RAM memory cycle
is not in progress.
This implies that the RAM
refresh can occur at the same time as accesses to other system memory
(ROMs) or I/O space.
Each time a refresh cycle begins,
a
refresh
timer
(one-shot
U29)
starts.
When
it times out, it provides the
signal to begin another refresh cycle.
This
timer
is
set
to
15
microseconds
(us)
maximum, vhich alloys for the vorst-case refreshrequest latency.
To maintain the contents of the RAM
under vorstcase
conditions,
the refresh must occur at least 128 times vithin 2
ms.
(The average refresh timing is once per 15.625 us).
The
vorstcase latency for a refresh request is about 600 ns.
Once a
refresh cycle has begun, it must be completed (including the
precharge) before the next cycle
begins.
If a
RAM access
cycle
starts before the refresh cycle completes, the HAL state machine puts
the
CPU into a vait state until the refresh operation completes.
In
the vorst case, this delay could extend the normal memory access time
by four vait states, or 800 ns.
Assuming a refresh timer
value
of
14 us
and an average 600-ns
slovdovn
of
the CPU,
is approximately 4.3
the
refresh overhead

TECHNICAL REFERENCE

SYSTEK HARDWARE

percent average or 5.7 percent worst case.
2.4.5.3· CAS and Address Kultiplexer Switch.
A delay line from
the
RASI(row address strobe input) line produces the SWK (the address
multiplexer control). SWK ensures an adequate row address hold
time
(40 ns) and still operates
the RAK quickly enough to finish the
access within the system cycle time.
The CASI- (column address strobe input) timing depends' on whether the
cycle is a read or a write.
If the cycle is a read, the CASI- signal
is taken from the delay line 20 ns after the SWK signal
to produce
the ACAS- (advance column address strobe).
ACAS- ensures an adequate
column address setup time to the RAK and still gives fast RAK access.
If
the cycle is a
write, then the CASI- signal is taken from the
falling edge of the system clock. which is about
150 ns after
the
occurrence of RASI-.
This delay allows time for the data from the
processor-to propagata -through the data buffers and
the parity
generator chip (U31 74LS290).
To control the generation of the CASI- pulse, flip-flop U33 is timed
with CLK- (the system clock). samples the delay line (ACAS-). and
is
reset by KRDC- (the memory read signal).
The output of the flip-flop
is
then logically ANDed (U34) with the ACAS- signal to generate the
actual CASI- signal.
To prevent the generation of a
CASI- pulse
during refresh,
the refresh row address strobe (RRAS-) line holds
flip-flop U33 in the preset state during a refresh.
This forces
the
output of OR gate U34 (CASI-) to a high level.
2.4.5.4
Parity
Generation
and
Checking.
The
parity
generator/checker chip (74LS290) generates a "1" to
the parity RAM
bit whenever
ther~
is an even number of l·s in the da~a byte being
written.
The parity RAM chip has a separate data· bus
to drive
the
output
line.
A pullup resistor holds this line high when it is not
driving the output
(as in a write cycle).
The parity data is then
taken from the "odd sum" output of the parity generator and used to
write to the RAM.
This method of parity checking does not cause a parity error when the
system attempts to read from nonexistent RAM.
(To determine the size
of system memory, the system software sometimes "feels" for memory
not present.)
When
the RAM is read" all of the data bits and the parity bit are
presented to the generator/checker and the.parity output
is sampled
at
the end of
the read cycle.
If parity checking is enabled and
discovers a parity error, flip-flop U33 is set to interrupt the CPU.
Once set, this flip-flop must be reset by software before additional
interrupts can be given.
If the enable. bit (address 3 bit 3) is held
low, then no parity interrupts (PINT) are generated.
To distinguish
the parity interrupt
from other NMIs, the PINT line is fed to U49
(address 1 bit 3) and can be tested by software.

2-22

SYSTEM HARDWARE

TECHNICAL REFERENCE

2.4.5.5 Memory Control State Machine.
A hard array logic device
(HAL16R4 U28), set up as a state machine, drives the memory control.
This device has four outputs equipped vith a
set
of
clocked
flipflops
and
four
outputs that are direct combinations of the inputs.
The AND of the terms on a line ORed vith the AND of
terms
on other
lines
results in loy-going outputs.
This occurs either directly, on
those outputs vithout registers, or after the clock on those
outputs
vith registers.
The
signalRASI- activates RASout
of
the AM2964B RAM address
multiplexer.
The signal XWAIT- puts the processor into a vait state.
The signal MDEN- activates the motherboard memory system data buffer.
The signal RMSEL- selects access
to
the ROMs.
The
signa~
RFSHinstructs
the AM2964B address multiplexer
to put out the refresh
address.
The signal RRASindicates
that a
refresh RAS
is
in
progress. _ The
signal __ SY(used
internally to the HAL) indicates
refresh states.
The signal SX- (used internally to the HAL) cuts off
the vait state to the CPU atter one cycle.
Table 2-8 gives the logic for the memory control state machine.
A timing diagram of the memory system, shovn in Figure 2-3,
the major operation..s of the memory system.

2-23

indicates

TECHNICAL REFERENCE

Table 2-8

SYSTEM HARDWARE

Memory Control State Machine Logic - HALl6R4

Input
MRDXA18
RASIRFSHMKRRMXXKAIT- RRASRFRQ
IORCMDENSYoutput
XAl9
AIOKCRMSEL- SXComment
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+-------------------------------RASI- L
L L
H
H
Memory read
or
L
L L .
H . H
Memory write
or
L L
Refresh
or
L L .
All other OR terms
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+--------------------------------XKAIT- L
L
L
Refresh+read RFl,2,3
or L .
L
Refresh+read RF3,4
L
·
or
L
L
Refresh+write
RFl,2,3
L
·
or · L · L.
L
Refresh+write RF3,4
or ·
H H L
ROM read/write
L
H
or
. L
. H I/O read
or ·
L.
H
I/O write
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+--------------------------------MDENH
RAM read/write
L
H
or L
H H L
ROM read
or . L . H H L .
ROM write
or .
L L
All other OR terms
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+--------------------------------RMSEL- L
ROM read
· H H L
ROM write
or . L . H H L .
All
other QR terms
or .
. L L
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+--------------------------------The following foul" outputs have flip-flops:
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+--------------------------------Refresh RFl; no memory cycle
RFSH- H H H .
• H •
Refresh
RF1; no RAM cycle
or . . H H •
· H
or .
Refresh
RF2,3
· L . H
or .
All
~ther
OR ~~r~s
• L • H •
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+--------------------------------Refresh RF2,3,4
RRAS· L .
All other OR terms
or .
• L .
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+--------------------------------SyRefresh RF3,4
· L L .
or .
All other OR terms
· L L .
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+--------------------------------SXL
H H L
ROM read wai t cutoff
,
or
L
H H L
ROM write wai t cutoff
or
L
I/O read wai t cutoff
or ·
L
I/O write wait cutoff
or
L
All other OR terms
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+--------------------------------L = Low signal.
H = High signal.

.-

·
·

·

·

·

.

·

·

2-24

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2223216-3

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..,

SYSTEM HARDWARE

TECHNICAL REFERENCE

2.4.6

Floppy Disk Controller

The floppy disk controller
(FDC)
section contains a
floppy disk
controller IC
(FD1793-02), a floppy disk support logic IC (WD1691),
and a pulse delay IC (WD2143), all made by Kestern Digital.
The FDC
also has a
voltage-controlled oscillator
(VCO) and one-half of a
74LS221 on.-shot.
Two 2114 static RAMs, addressed by a
CMOS 4040,
act as a
sector buffer,
and a programmable array logic (PAL) IC
decodes and controls operations.
Miscellaneous logic handles
signal
timing and buffering.
The logic described in this section includes:

*

Floppy disk controller IC

*
*
*
*

Sector buffer
Data write precompensation circuit
Data separator
Diskette drive interface

2.4.6.1
Floppy Disk Controller IC.
The Kestern Digital FD1793-02
chip is the FDC IC.
This IC does
serial/parallel data conversion,
locates sectors on the disk, seeks the diskette drive, and performs
other high-level functions.
A complete description of the FD1793-02\
chip can be found in the literature available from Kestern Digital.
The 1.0-MHz controller input clock provides the correct data rate for
standard 5 1/4-in diskettes.
Bec~use U20 divides the clock down from
15.0 MHz, the duty cycle is 467 ns low, 533 ns high.
2.4.6.2 Sector Buffer.
During read or write operations,
data must
be
transmitted at a rate between 23 us per byte and 32 us per byte
nominal (for double-density operation).
A sector buffer,
operating
independently of the processor during a read or a write, ensures that
the diskette drive performs properly.
This buffer consists of:

*
*
*

A lK x 8 static RAM device
A counter (to address the RAM sequentially)
Control logic and a bus buffer (so that the CPU and the FDC'
can access the buffer)

2-26

SYSTEK HARDWARE

TECHNICAL REFERENCE

Two bits (KO, K1) in latch U47control the basic operating
the sector buffer. These four modes are as follows:
Latch U47 Bits
KO K1
1

o

1
1

o

o

1

o

modes

of

Kode
FDC
FDC
CPU
CPU

reads RAK and writes data to diskette.
reads di~kette and writes data to RAK.
reads or writes RAK sequentially.
reads or writes the FDC directly.

The counter that addresses the buffer increments automatically each
time either the CPU or the FDC accesses the RAK.
To set up a
fixed
starting address within the RAK, the CPU writes to the FDC sector
register while the KO, K1 bits are set to 0,
O.
This resets
the
address counter. The FDC is not affected because the CPU can access
the FDC only .in. mode KO~-J1.
The PAL provides the control logiC for the sector buffer, aided by a
flip-flop that provides a 1-us FDC clock-synchronized signal.
The
PAL uses this Signal, derived from the FDC data request
(DRQ)
line,
to generate
the read or write command for the FDC when the sector
buffer is in mode~ 1, 1 or 1, O.
The FDC activates the DRQ line when
a sector write ~eq~ires • byte or when a byte is ready in a
sector
read.
This control logic and the CPU generate other signals to control the
RAK and the counter. These signals are given in, Table 2-9.
The
timing diagram· in Figure 2-4 defines the usage of these signals.
When the logical ARD of terms from one row is ORed with the AND of
terms from another row, the output goes low when the result is true .

.,"

2-27

TECHHICAL REFEREHCE

SYSTEM HARDWARE

Table 2-9

PrograJlUlling for the HAL10L8 Device

Input

---------------------------------IORQMl
IORCXAl
output

MO
XAO

AIOWC- DEHFLCS

DRQD

Comment

-------+--+--+---+--+--+---+--+--+---+-----------------------------L
L H
CPU <---> FDC Mode 0,1

YAO

L

or .

L

L

L

L

(Unused)

-------+--+--+---+--+--+---+--+--+---+-----------------------------L H
CPU <---> FDC Mode 0,1

YAl

L

L

or .

(Unused)

-------+-~+~-+---+--+--~--+--+--+---+-----------------------------L H
L
L
Mode 0,1
CPU <-- FDC
or .
H- L
H
Mode 1,0
FDC --> RAM

FRD-

-------+-~+--+---+--+--+---+--+--+---+-----------------------------L H
L
L
CPU --> FDC
Mode 0,1

FWR-

or .

H

H

FDC <-- RAM

Mode 1,1

H

FOC --> RAM

Mode 1,0

H

FOC <--> RAM

Mode 1,X

H

-------+--+--+---+--+--+---+--+--+---+-----------------------------L L
L L
CPU --> RAM
Mode 0,0
L
4··

•

RWE-

or .

H

or .

H

L

-------+--+--+---+--+--+---+--+--+---+-----------------------------L L
L L
CPU <--> RAM
Mode 0,0
L

RCS-

-------+--+--+---+--+--+---+--+--+---+-----------------------------Reset counter Mode 0,0
H L
L L

RRSTor .

L

L

L

L

(Unused)

-------+--+--+---+--+--+---+--+--+---+----------~------------------L
CPU <--> RAM
Mode 0,0
L
L
L
L H
L
CPU <--> FOC
Mode 0,1
L

FDEK- L
or .

Legend:
L = Low signal.
H = High signal.

2-28

SYSTEM HARDWARE

TECHHICAL REFEREHCE

CONTROllER WRITING TO RAM

\

-1

1 MHZ ClK

V

ORO

/
I

\

ORaD
FRO

,RWE

,RCS_.

--

/

r\

DATA

MO -lOW, Ml-HIGH

I

VALID

\

READ FDC WRITE RAM

CONTROL l ER READING RAM
l-MHZClK

ORO

ORaD

I

\

--'

I

I

\

\

,

MO- HIGH, Ml-HIGH
::

FWR, RCS

II

r\

,

DATA

\

VALID

READ RAM WRITE FDC

Figure 2-4

Floppy qisk Timing Diagrams

2-29

2223216-4

TECHNICAL REFERENCE

SYSTEM HARDWARE

2.4.6.3
Write Precompensation Circuit.
Using modified frequency
modulation (MFM) to vrite certain double-density data patterns on
magnetic
media
causes
a
"bit shift",
requiring disk vrite
precompensation.
Compensating for the bit shift prevents
the read
data transitions from moving outside the detection range of the read
circuitry.
As track length shortens tovard the center of
the disk,
data bits are stored closer together, so the bit shift problem gets
vorse.
The ideal compensation gradually adjusts the vrite hardvare
as
the
track number
increases.
Hovever, a
compromise solution
produces nearly the same results.
The precompensation is turned off
vhile
the head is over the outer half of the disk, then turned on
vhen the head is over the inner half of the disk.
Disk drives can
have either 40 or 80 tracks, so the softvare checks the type of drive
installed,
then determines the halfvay point.
For this reason, U47
(rather than the FOC) controls the TG43 signal.
(Halfvay point for
an 8-in d!skette = TG43: track number greater than 43.)
The vrite precompensation and data separator circuits are controlled
by U14, R17, R18, and R19 on the motherboard.
When the ROOATA- line
(pin 11 of U14) is high, it forces the PU and PD- outputs from the
WD1691 to a tristate condition.
R17 adjusts
the PUMP line
(pins
13/14 of U14) voltage to 1.4 Vdc.
R18 generates a square vave of 2.0
MHz + 5.0 perce-nt f-rom
the VCO (pin 16 of U14).
The pulsewidth
(monitored from pin 5 of U14) should be 750 ns, giving a write pulse
width of 187.5 ns.
The vaveform is visible only vhen the computer is
vriting data to a diskette.
R19 control. the vrite pulsewidth through ·U15 (the HD2143 IC),
determining the amount
of
precompensating
bit
shift.
The
precompensation pulsevidth (monitored from pin 1 of U15 during a
vrite operation) should be set to approximately 200 ns.
The FDC signals EARLY and LATE control the direction of bit shift.
These signals cause WD1691 to select the appropriate tap along the
HD2143 (adjustable delay line) for the bit pattern being written.
If
precompensation is not needed on outer tracks,
the TG43 signal
inhibits the precompensation process.
Because single-density frequency modulation (PM) encoded data does
not require precompensation,
the
PD1691
also
disables
the
precompensation vhen the double-density enable signal (ODEH-) is
inactive (high).
2.4.6.4 Data Separator.
The data separator is composed of
two
parts:
clock recovery and separation of the data from the clock.
The actual separation of data from clock signals takes place in
the
F01793-02 FOC.
The H01691 contains the digital circuits necessary to
implement a phase-locked loop (PLL),the VCO is a 74LS628 chip, and
external components provide
the loop filter.
The one-shot U29
shortens and stabilizes the pulsevidth of the incoming read pulses so
that the PLL and data recovery operations operate properly during the
lockup interval.
2-30

SYSTEM HARDWARE

TECHHICAL REFEREHCE

The PLL provides a
contin~ous
clock locked in a specific phase
relationship with transitions in the incoming data.
For this system,
the falling edge of the RDDATA- signal should be nearly centered on
the high or low pulse of the RCLK signal.
When
the PLL is adjusted correctly, it locks to an incoming pulse
train in a frequency range from 217 kHz to 294 kHz
(~
15 percent)
within 150 us.
The pulses should be low-going, 2 us maximum applied
to the RDDATA- input (P9 pin 30), and the DDEH- line must be low.
Because of the analog nature of the PLL circuits, a linear regulator
governs the power-supply voltage to the VCO and the loop filter.
The
regulator prevents digital noise on the 5-V supply from interfering
with the PLL operation.
The data separator works with either single-density (FM)
or doubledensity ("JJFH) 'data.
Tbe-_choice is controlled by the DDEN- line.
2.4.6.5
Diskette Drive Interface.
The diskette drives communicate
through a series of buffers and receivers.
Low-impedance ribbon
cables connect the controller to the drive.
P9 connects the internal
diskette drives,
and P13 connects the external drives.
All signals
driven by the controller (except for the SID1- signal) have separate
drivers for
each- connector.
The receivers with their terminating
pullup resistors are shared between the two connectors.
connector P9 interfaces with a 34-conductor ribbon cable that has two
34-pin, card-edge connectors (one for each of
the diskette drives
that can be mounted inside the system unit chass'is).
There is always
one diskette drive installed in the system unit, mounted on the left
side (as viewed by a user).
This drive should be strapped for SELECT
on pin 10 (drive O)~ When only one drive is
installed,
the
select
line and all common lines except pin 32 (side select) should be
terminated at the drive.
If another drive is installed internally, it should be strapped for
SELECT on pin 12 (drive 1) with only the select line terminated.
With two drives installed, the terminating resistor must be installed
on the right-hand drive (drive 1) only.
NOTE
The floppy disk
controller
and
individual
diskette drive logic signals assign drives using
the convention of:
DRIVE 0, DRIVE 1,
DRIVE 2,
and DRIVE 3 (for a
four-drive
system).
The
diagnostics diskette uses the convention:
DRIVE
1, DRIVE 2, DRIVE 3, and DRIVE 4 for a four-drive
system.
Operating systems 'may use yet another
convention, such as DRIVE A, DRIVE B,
DRIVE C,
and DRIVE D.
Be sure to use the correct drive
designator.

2-31

TECHNICAL REFERENCE

SYSTEM HARDKARE

Connector P~3 interfaces with a 40-wire ribbon cable ending in a
31ptn, D-type connector.
The user mounts the mate to this connector on
the back panel of the system unit chassis.
Khen external drives are
installed, all lines used must terminate at the external drive.
All diskette drives must be of the same type.
That is, all must
be
either 320K-byte drives (double-sided, 48 tracks per inch [tpi]) or
all must be 640K-byte drives (double-sided, 96 tpi).
A jumper from
El
to E2 selects 320K-byte drives; a jumper from E3 to E4 selects
640K-byte drives.
The absence of a jumper selects ~60K-byte drives.
A jumper can be on either E~-E2 or E3-E4, but not both.
The diskette drives do not need head-load solenoids for proper
operation.
However,
if
the drives are equipped with head-load
solenoids, they should be strapped for head load with the motor on.
The signals. STEP, DIRC,_KG, and KDOUT are buffered by the 14LS244 in
order to drive the two standard 14~6 loads.
This buffer is necessary
because the FD~193-02 and the KD~691 can drive only one TTL load.
The input
signals KRITEPROT-,
IHDEX-,
TRKOO-,
and RDDATA- are
buffered by the 14LS244, providing more static protection
than
the
MOS-device inputs, and a small amount of hysteresis.
To install externa-l diskette drives, a short cable assembly links the
motherboard connector P~3 with a 31-pin, d-type connector on the back
of the system unit chassis.
Section 5 contains the wiring assembly
diagrams for
this cable.
(External diskette drives require an
external power source.)
Table 2-10 gives
the pin-outs for
the internal diskette drive
connector on the motherboard.
Table 2-1~ gives the pin-outs for
the
external
diskette drive connector on
the motherboard.
D-type
connector pin numbers are given in parentheses.

2-32

TECHNICAL REFERENCE

Table 2-10

SYSTEM HARDWARE

Internal Diskette Drive Connector Pin-Out

+------+------+-------------+--------+--------------------------+
ISignallReturnl Signal Hame I Source I
Function
+------+------+-------------+--------+--------------------------+
2
HC*
+------+------+-------------+--------+--------------------------+
3
HC
+------+------+-------------+--------+--------------------------+
5
HC
+------+------+-------------+--------+--------------------------+
7
I IHDEXI Drive
Indicates index hole
+------+------+-------------+--------+--------------------------+
10
I SELECT 1I System I Drive select 1
+------+------+-------------+--------+--------------------------+
12
I System I Drive select 2
+------+------+-------------+--------+--------------------------+
14
13
HC
+------+------+-------------+--------+--------------------------+
16
15
MOTOR OHI System I Drive motors
+------+------+-------------+--------+--------------------------+
.I
18
17
I DIRECTIOHI System' Step IN/OUT direction
+------+------+-------------+--------+--------------------------+
I STEp:'"
20
19
I System , Step IN/OUT command
+------+------+-------------+--------.--------------------------+
22
21
I WRITE DATA- I System I Serial data to drive
+------+------+-------------+--------+--------------------------+
24
23
I WRITE GATE- I System I Enables vriting to drivel
1

4

6

8

9

ON

J

I

I

I

vhen signal is loy

I

+------+------+-------------+--------+--------------------------+
26
25
TRACK 00Drive
Indicates head is over
track 00 vhen signal
is loy

+------+------+-------------+--------+-----------------?--------+
28
27
Indicates diskette
I WRITE PROT- I Drive
,

I

is vrite-protected

+------+------+-------------+--------+--------------------------+
30
29
Serial data from drive
I READ DATA- I Drive
+------+------+-------------+--------+------------~-------------+
32
31
I SIDE 1I System I Side select (0,1 =

I

,

I

high, loy)

+------+------+--------~----+--------+--------------------------+

33

34

HC

+------+------+-------------+--~-----+---~----------------------+

*

HC

= Hot

connected.

2-33

TECHHICAL REFEREHCE

Table 2-11

SYSTEH HARDWARE

External

Disk~tte

Drive Connector Pin-Out

+------+------+-------------+--------+--------------------------+
ISignallReturnl Signal Hame 1 Source I Function
+------+------+-------------+--------+--------------------------+
1 2 (1) 1 1 (20) 1
HC*
I
+------+------+-------------+--------+--------------------------+
HC
I 4 (2)1 3(21)1
+------+------+-------------+--------+--------------------------+
HC
16 (3)15(22)1
+------+------+-------------+--------+--------------------------+
HC
I 8 (4) 1 1(23) 1
+------+------+-------------+--------+--------------------------+
110 (5)1 9(24)1
MC

+------ +--.- ---+-- -- ------- -- +---- ----+------------ ------- -- -----+
112 (6)111(25)1

IHDEX-

I Drive

Indicates index hole

+------+------+-------------+--------+--------------------------+
114 (7.)113(26)1 HOTOR 3I System I Drive motor 3 enable
+------+------+-------------+--------+--------------------------+
116 (8)115(21)1 SELECT 4I System I Drive select 4
+------+------+-------------+--------+--------------------------+
118 (9)117(28)1 SELECT 3I System I Drive select 3
+------+------+-------------+--------+--------------------------+
120(10)119(29)1 HOTOR 41 System 1 Drive motor 4 enable
+------+------+-------------+--------+--------------------------+
122(11)121(30)1 DIRECTIOMI System I Step IH/OUT direction
1 \
+------+------+-------------+--------+-----~--------------------+
1 System 1 step IM/OUT command
124(12)123(31)1 STEP-

+------+------+-------------+--------+--------------------------+
126(13)125(32)INRITE DATA- 1 System I Serial data to drive
+------.------+-------------+--------+--------------------------+
128(14)127(33)1 WRITE GATE- 1 System 1 Enables write when low
+------+------+-------------+--------+--------------.------------+
Indicates head is over
130(15)129(34)1 TRACK 00I Drive
I

1

I

I

1

1

1

1

track 00 when low

.------+------+-------------+--------+--------------------------+
132(16)131(35)1 WRITE PROT- 1 Drive
1 - Indicates d·islCette
1

is write-protected

+------+------+-------------+--------.--------------------------+
Serial data from drive
134(17)133(36). READ DATAI Drive
+------+------+-------------+---~----+--------------------------+

136(18)135(31)1 SIDE 1-

1 System 1

Side select (0

= high)

+------+------.-------------.--------+--------------------------+
HC
138(19)131
+------+------+-------------+--------+--------------------------+
MC
140
139
+------+------.-------------+--------+--------------------------+
* HC = not connected.

2-34

SYSTEM HARDWARE

TECHNICAL REFERENCE

2.4.6.6 Diskette Drive.
The Texas Instruments Professional Computer
is equipped vith one S 1/4-in,
double-sided,
diskette drive.
The
self-contained unit
consists of a spindle drive, a head positioner,
and a read-vrite-erase system.
Plastic guides help to position
the diskette
inside
the diskette
slot.
After you insert the diskette and close the access door, three
things
happen:
the diskette clamps (0 the drive hub; a SOO-ms delay
begins, and the servo-controlled drive motor starts.
The head positioner is a 4-phase stepper-motor and band assembly vith
some related electronics.
It moves the head (using one-step rotation
to cause a one-track linear movement) to
the proper
track of
the
diskette.
The folloving sensor systems are built into the unit.

*

The
track 00 sensor.
This
svitch
head/carriage system is at track 00.

*

The index sensor.
When the phototransistor sees
the LED
light source through an index hole, it sends out a signal.

*

The vrite-protect
sensor.
When this svitch finds a vriteprotect tab applied to a diskette,
it disables
the vrite
head.

determines

that the

--

The diskette drive
reads and
vrites digital data using KFK.
The
vrite operation records a 0.33-mm (0.013 in)
data
track,
vhich is
later
tunnel-erased
to 0.30 mm
(0.012
in).
The track-to- track
access time is 6 ms.
The drive speed is 300 rpm.
Table 2-12 gives the specifications for the diskette drive.

TECHNICAL REFERENCE

SYSTEM HARDWARE

Table 2-12

Diskette Drive Specifications

Physical Dimensions:
Height
Width
Depth
Weight

95.95 mm (3.39 in)
149.10 mm (5.97 in)
203.20 mm (9.00 in)
2.04 kg (4.50 lb)

Environmental Parameters:
Tempera t ure·
o
40

o
(50

Relative Humid~.ty
o
(0 40
F wet-bulb
temperature,
no condensation

C

F

to 104

Mean sea level
to 10 000 ft

Power Requirements
Current
600 mA
900 mA

0

C to

-40

F)

(-40

C

65

o

0

20 'It to 90 'It

Voltage
+5 Vdc
(+/- 0.25 V)
+12 Vdc
(+/- 0.6 V)

o

0

C to

10

Altitude

Storage

Operating

0

F

to 149

F)

5 'It to 95 'It

Mean sea level
to 45 000 ft

TECHNICAL REFERENCE

2.4.1

SYSTEM HARDWARE

CRT Controller Board

The CRT controller board drives either a monochrome analog or a color
TTL display and makes the Texas Instruments Professional
Computer a
complete alphanumeric and raster graphics system.
As a
stand-alone option, the controller board provides one page of
high-resolution (80 columns x 25 lines) alphanumeric
display.
This
board also supports the optional graphics video controller piggyback
board, which is described in Section 3.
The
system makes
no physical
distinction
between
color
and
monochrome;
the
board
supports
output
in either eight-level gray
scale or eight-color RGB (red, green, blue).
Color is determined by
the monitor
used.
R~fer
to Section 6, drawing 2223011. for logic
diagrams.
Figure 2-5 is a block diagram
board.

of

the

alphanumeric

CRT

controller

Table 2-13 lists the video ac parameters.
Figure 2-6 shows the timing diagram for the Alphanumerics State
Machine PAL.

2-37

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r-

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GR ,';HICS
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6545
CRT
CONTROL
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SOCKET
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'---FOR
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CHAR GEN
EPROM

....-'-SHIFT
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"'--;"'

~I

t
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,

~
ILATCH.

CRT DOT AND CHAR TIMING
CPU CRT ARBITRATION
IBUFFERt

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LOGIC

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CRT DATA BUS

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>r'

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CHARACTER
RAM

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n

2K x 8
ATTRIBUTE
RAM

RAM SELECT

.tfj.-

0

~

CHARACTER DATA

~UFFERt

Q.

....

~

A TTRIBUTE LATCH BUS

t-t--

GR ,PHICS
CO \lNECT

r-

.....!...-

CRT
SYSTEM
DECODE
LOGIC

ADDRESS
MUX
11 x2-1

LATCH

U~rj
~M

SY STEM

\

REFRESH ADDRESS

DOT ROW AND MISC

:c-

0
0
::I

-

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CONNECT

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til

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DIAGNOSTIC DOT DATA

til

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Table 2-13
f* Parameter

Video AC Parameters

Value

Value**

Tolerance

------------------------------------------------------ ----------

A
B

C
0

E
F
G

H
:J
K
L

M
N

'1
S

T
U
V
H
X

*
**

Video dot frequency
Video dot pulse...,idth
Character block
horizontal
Character block
vertical
Number of character
lines
Characters/character
line
Number of active
scan 1 i-n e-s
Total scan lines
Vertical sync ...,idth
Vsync front porch
Vsync back porch
Vertical blanking
interval
Active vertical
display time
Total vertical time
Vertical rate
Hsync ...,idth
Hsync front porch
Hsync back porch
Horizontal blanking
interval
Active horizontal
display time
Total horizontal time
Horizontal rate

18.000 MHz
55.55 ns

1
1

,.,.

9 dots
12 dots

14 scan lines

25 ro...,s
80 columns
3-00
320
0.156 ms
0 ms
0.884 ms
1.040 me
15.60
16.63
60.10
4.50
2.00
5.50

ms
ms
Hz
us
us
us

350
385
0.156 ms
0 ms
1.664 ms

1
1
1

1.82 ms

1

19.20 me
20.02 ms
49.95 Hz

1
1
2 Hz
1
1
1

"

12.00 us
39.99 us
51.99 us
19231 Hz

,.,.
,.
"
",.
,.,.

1

",.
,.

1
1
100 Hz

Letters refer to areas on the timing diagram in the
next figura.
These values reflect the vertical timing adjustments
for 50-Hz refresh.

CAUTION
50-Hz operation can be used only in areas
that
run
on
50-Hz line
frequency.
Using 50-Hz
operation in any other area
can damage your
computer.
To select 50-Hz operation, jumper pins
E5-E6 on the motherboard.

2-39

tool

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en

SCREEN
REFRESH

I
SCREEN
,
REFRESH
SCREEN REFRESH I SCREEN WAIT
o I 8 9 10 11 12 I 13 14 15

t,)
STATE:
X15

I

oI

lIS

ATTRIBUTE WRITE
SCREEN
REFRESH

SCREEN
SCREEN READ
REFRESH
8 9 10 1l 12 I 13 14 15

"CJ

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AEN -

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SYSTEM HARDWARE

TECHNICAL REFERENCE

The CRT controller
paragraphs include:

j

/

board

*

Display characteristics

*
*
*
*
*
*
*
*
*
*

Character attributes

*

Diagnostic loopback

features

*
*
*

in

the

following

Character sets
Cursor
Scrolling
Video connector
CRT_~ontroller

IC

CRT screen/CPU arbitration logic
CRT address decode logic
Character sets and attribute logic
CRT interrupt logic

2.4.1.1 Display Characteristics.
follows:

*
*
*

described

The display characteristics are as

A 1 x 9 character in a 9 x 12 image cell
Twenty-five lines of 80 characters
A resolution
vertically

of

120

pixels

horizontally

'x

300

A horizontal scan rate of 19 200 lines per second
A vertical scan rate of 60 (50 frames per second)
A dot rate of 18.0000 MHz
NOTE
The horizontal scan rate
is
an
important
consideration.
Many monitors available
today
have a horizontal scan rate of 15 150.
Only a
monitor having a horizontal scan rate of 19 200
lines per second can operate with
the Texas
Instruments Professional Computer.

2-41

pixels

TECHHICAL REFEREHCE

SYSTEM HARDWARE

2.4.7.2
Character Attributes.
The controller's video memory is
organized as 2K bytes x ~6 bits.
The first 9 bits
convey character
information.
Tha second 9 bits select the folloving attributes on a
character basis:

*'
*'

Bit 0,

intensity level

Bit

intensity level 2 (red)

*'
*'
*'

Bit 2,

Bit 3, character enable

*'

Bit 5..., underline

*
*'

Bit 6, blink

1 ,

Bit 4

I

~

(blue)

intensity level 4 (green)

reverse

Bit 7, alternate character set

HOTE
The three intensity bits (bit 0
through bit
2)
determine
the gray scale intensity level and the
RGB outputs for color.
Thus,
hi/norm video
in
monochrome is handled bya one-of-eight intensity
select instead of a high-intensity bit.
I

To access
the attributes, the softvare vrites the attribute values
into an attribute latch.
The attribute value is then assigned to the
character each time that character is vritten to the screen (until a
screen read is done).
When any character on the screen is read, its attributes are copied
to the attribute latch.
These values are then read by a
subsequent
latch read operation.
Handling
the attributes by this method ensures that, in block moves
(moving data from one screen area to another), the characters
retain
their attributes.

2-42

SYSTEM HARDKARE

TECHHICAL REFEREHCE

2.4.7.3
Character Sets.
The video controller contains a
4K
character generator ROM, which contributes 256 characters.
Use
the
socket provided to add an optional 2K or 4K ROM/EPROM and expand the
character set to the maximum 512 characters.
Attribute bit 7 selects
the expanded character set.
Refer to subparagrahph 2.4.8.4 for more information on the
ROM.

character

2.4.7.4
Cursor.
Programming can change the cursor appearance.
The
possibilities include blinking, non-blinking,
block,
underline and
reverse-video.
Hardware handles the cursor display through a special
set of registers
in
the controller.
Using these registers, the
software can position the cursor anywhere on the screen (or off
the
screen if no visible cursor is desired).
2.4.7.5
~crolling.
The hardware maintains a screen start register
that supports character line scrolling in four directions.
The
software determines the need for a scroll, then changes the value of
this register by one line.
The screen appears to jump by one line.
The scrolling operation always affects all of the screen.
It is not
possible to scroll one region without affecting another.
Because the controller contains only 2K bytes of screen memory,
scrolling results in a
"wrap";
the original
top line of screen
contents moves to the bottom of the screen.
Therefore, the software
must clear the top line of the screen (or bottom) before the scrollup (or -down) operation.
To simplify programming of the line clear
operation, the 2K bytes of memory is phantomed over a 4K-byte address
space.
status lines must be implemented in software.
That is, ~uring scroll
operations,
the status line must be moved to its new memory position
before writing.
The screen start register changes the -screen-tomemory correspondence.

2-43

TECHNICAL REFERENCE

SYSTEM HARDWARE

2.4.7.6
Video Connector.
The video connector located on the rear
edge of the PWB is a standard, 9-pin, female, D-type connector.
This
connector is for a color display unit.
The signals available on this
connector are given in Table 2-14.
All signals are at
standard TTL
levels.
Table 2-14
Pin
1
2
3

4
5
6
7

8
9

Color"Video Connector Pin-Out
Function
Ground
Logic ground
Red video
Green video
Blue video
Logic ground
HC (no connection)
Horizontal drive (HEGATIVE TRUE)
Vertical drive (POSITIVE TRUE)

The other video ~onnector, on the lower rear edge of the PHB, is a
standard RCA phono jack.
This connector is for a monochrome display.
The signal available at this connector is a composite type, 1 V peakto-peak, 75-ohm load.
2.4.8

CRT Controller IC

The CRTC IC (6545A-l) contains the logic for:

*

Generating the horizontal and vertical synchronizing signals

*

Blanking display during retrace

*
*
*

Addressing screen memory during screen refresh
Cursor coincidence
Starting screen display registers for use in scrolling

The CRTC contains eighteen registers that must be appropriately set
before board operation begins.
To access these registers, the CPU
first writes the address of the register to be accessed into the CRTC
address register.
Then information can be written to that
register.
When writing
to or
reading from
(where appropriate)
the data
register, the information is accessed by the address latched
in
the
address register.

2-44

SYSTEM HARDWARE

TECHNICAL REFERENCE

Table 2-15 shovs hov to program these registers, using the signals
chip select
(CS),
register select
(RS),
and read/vrite
(R/W-).
Assume the folloving conditions:

*
*
*
*

A character rate (SWM-) of 2.0 KHz

*

20 line times of vertical blanking (1.04 ms)

12 lines per character block
25 rovs on the display

24 character times of horizontal blanking (12.0 us)

For more detailed programming information, refer to
Book.

2-45

~

Synercom Data

TECHNICAL REFERENCE

SYSTEM HARDWARE

Table 2-15

Signal Name
CS- RS

Register
Address

Refresh Rate
Value

Register
Name

60 Hz

R/H'-

H
L
L
L

L
L
H

X
L
H
L

o

L

H

L

1

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

CRTC Programming Values

X

L
L
L
L
L
L
L
L
L
L
L
L

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

X
X
H
H

2.

3
4

5
6
7
8
9

10

11
12
13
14
15
16
17

No register selected
Set address register
Set status register
Horizontal total characters
103
minus one
Horizontal displayed
80
characters
84
~orizontal sync position
39H
VSYNC width, HSYNC width
24
Vertical total rows minus 1
20
Vertical adjust lines
Vertical displayed rows
25
25
Vertical sync position
OOH
Mode control
Scan lines per row minus 1
11
40H
Cursor start line and BLINK
11
Cursor end line
Display start address high
OOH
Display start address low
OOH
OOH
Cursor position address h'igh
OOH
Cursor position address low
Light pen position address high
Light pen position address low

Legend:
H = High signal.
L
Low signal.
X
Don't care.

=
=

2-46

50 Hz

103
80
84
59H

31

00
25
28

OOH
11
40H

11

OOH
OOH
OOH
OOH

SYSTEM HARDHARE

TECHNICAL REFERENCE

'.4.9.1
CRT
Screen/CPU
Arbitration Logic Subsystem.
The CRT
;ontroller arbitration logic gives the programmer free access
to
the
1T display.
There
is
little overhead
time caused by arbitration
conflicts, because the refresh memory and its control logic allow
two
complete memory cycles between each character displayed on the screen.
One cycle accesses the character for display; the CPU uses
the
other
cycle for read or write operations.
Therefore, the CPU waits less than
two display-character
times
for
memory access.
Because a character
time is 500.9 ns and the CPU clock is 200 ns, a
synchronization delay
can occur.
The total time for a worst-case CPU access is 1.0 us.
The
usual access time is 600 ns (3 to 0 wait states).
The logic that generates this arbitration
scheme
includes a
counter
(which also counts
the
nine dots per Character), a PAL (which has
internal registers and gets feedback from the outputs),
and a
small
alphanumeric. state machine-(which provides RAM buffer control, control
outputs
for ~he RAM,
and- the wait state control for the CPU).
The
counter uses inputs to the PAL to identify the state within the display
cycle of the state machine.
The internal PAL registers define other
states
used during
the CPU read and write cycles.
To define the CPU
cycle type being executed, the PAL uses
the
inputs RD-,
HR-,
CSEL(character select), and ATSEL-(attribute select).
The outputs from the PAL are:

*
*

COE-,

the RAM output enable

CHE-,

the RAM write enable

*

AEN-,

the attribute bus buffer enable

*
*
*
*

AOE-,

the attribute latch output enable

ACK-,

the attribute latch clock

MIE-,

the character bus input buffer enable

*

SHM-,
the
Signal
that
from the CRTC to the CPU
HAIT-,

switches the RAM address multiplexer

the CPU wait control line

The
counter
(U24,
a
74LS163)
9,9,10,11,12,13,14,15,0, and repeat.

goes

through

states

Latch Ul0 is included because the window (when read data from the video
RAM is available) is rather short.
This latch captures and holds the
data for the CPU until the end of the CPU read cycle.
The ACK line.
which clocks
the attribute latch. clocks this latch when read data is
available from the RAM.
The output is enabled onto the local bus by a
combination of CSEL- and RD-.

2-47

SYSTEM HARDWARE

TECHNICAL REFERENCE

The CRT arbitration PAL programming is given in Table
2-16.
In
the
"comment"
column, the states generated by the AND of inputs are listed
according to the counter state number.
When the logical AND of
term!!"
from one row is ORed with the AND of terms from another row, the output'
goes low when the result is true.
Refer
to
Figure
2-6
for
an illustration of the--t'iming produced for
typical cycles by the alphanumerics state machine.

(

2-48

TECHNICAL REFERENCE

SYSTEM HARDWARE

Table 2-16

Alphanumerics State Machine PAL

Input
Xl
X2
output

SWMUX
AEHRDMIEACKWRX4
CSELCWEAOEATSEL- COEWAITLD-

Comment

------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+---------------------------------S9,9,10,11,12 X4 delayed
. L .

SWMUX .
or .

All other terms

. L .

------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+---------------------------------S9 RAM
begins
L L

MIE- L L L H
or .
or

L

~rite

L

S10,11,12 RAM ~rite continues
All other terms

------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+---------------------------------S9 RAM
begins
L L

CWE- L L L H
or H L L H
or L H L H
or
H L

L

L

L

•

L L

L

~rite

S10 RAM ~rite continues
S11 RAM ~rite continues
All other terms inactive

L .
L

------+-+-+-+-+-+-+~.+-+-+-+-+-+-+-+-+----------------------------------

COEor
or
or

H
L

L H L . L
•

L

H

L

L

L

H L

S13,14,15,0 screen refresh
S9,10 RAM read
S10,11,12 RAM read continues
All other terms inactive

------+-+-+-+-+-+-+-+-+-+'-+-+-+-+-+-+---------------------------------.
.LL
S9 RAM
begins

AEN- L L L H
L L
or
or
L L H L
L
or
H L H L
L
or
H L

~rite

L
H

.

L

L

.

S10,11,12 RAM ~rite continues
S9,10 RAM read
S11,12 RAM read
All other terms inactive

------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+---------------------------------L
S1.2 RAM read

ACK- H H L H L
L •
or L .
. L . L .
or . . H iL

Write attribute latch
All other terms inactive

------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+---------------------------------H L
S8 RAM

AOE- L L L L
L L
or
L L
or
L
L
or
L
L
or
L
L

.

~rite

L
L

.

89 till not ~rite
Read at.t r i bu te latch
S13 till not read
S13 till not read

·
------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+---------------------------------WAITL L
RAM vrite before S9
L

H

or
or

·

L

.

L

•

. H H .

H L .

RAM read before S9
All other terms inactive

------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+~+----------------------------------

Legend:
L = Lov signal.
H
High signal.

=

2-49

TECHNICAL REFERENCE

SYSTEM HARDWARE

2.4.8.2
CRT Address Decode Logic.
The CRT controller board handles
both alphanumeric- and graphics- address decode for the CRT subsystem.'
All of
the screen data is mapped into the processor memory address
space including the assorted latches and I/O ports.
The decoding is done with three ICs:
a
HAL10L8 PAL,
one-half of a
74LS20, and a 74LS155 ~ecoder.
The PAL produces the following signals:

*
*
*
*
*

GSEL-,

the graphics screen memory

*

CSEL-,

the alphanumerics screen memory select

*

CR/AT-,
selects one half of the 74LS155 (which decodes the
CRTC and the attribute latch)

*

XSEL-, selects the other half of the 74LS155
(which decodes
the graphics latch and the miscellaneous input buffer)

ZBEN-,

the master expansion bus buffer enable

XBEN-,

the secondary bus buffer enable

RD-, a decoded and buffered read control
WR-, a buffered and decoded write control

-

The XBEN- signal develops an enable
delaying
the signal that provides
the 6545a-1 CRTC.
The CRTE
(CRT
greater than 266 ns, satisfying the
setup and hold times are easily met.

~elect

clock for the CRTC by invertin9 and;',-the required setup time (90 ns) for
enable)
signal has a
pulsewidth
requirement of the CRTC.
The other
.

The 74LS155 decodes the following signals:

*
*
*

ATSEL-,
CRTSEL-,

the attribute latch select
the CRTC chip select

LAT-

LAT- combines with HR- and clocks
the interrupt enable and screen
enable latches.
The other half of ,the 74LS155 decodes
the
three
graphics board latches and ~he buffer enable for miscellaneous inputs.
The address space that each of these devices. occupies is given in Table
2-17.

2-50

TECHNICAL REFERENCE

SYSTEM HARDWARE

Table 2-17

CRT System Memory Map

Address

Device

COOOO-C7FFF
C9000-CFFFF
DOOOO-D7FFF
D9000-DDFFF

Graphics RAM Bank A
Graphics RAM Bank B
Graphics RAM sank C
Unusable

DEOOO-DE7FF
DE900-DEFFF

Active character memory
Phantom character memory

DFOOO
DFOOO
DFOOO
DFOOO

bit
bit
bi t
bit

0
1
2--

:3

Misc
Misc
.Mi sc
Mise

input
input
input
input

buffer,
buffer,
buffer,
buffer,

blue feedback, read only
red feedback, read only
green feedback, read only
interrupt pending, read only

DF010
DF020
DFO:30
DF900

Graphics blue palette latch, write only
Graphics green palette latch, write only
Graphics red palette latch, write only
Attribute latch

DF910
DF911
DF912
""IF91:3

CRTC
CRTC
CRTC
CRTC

DF920
DF920

bit 7
bit 6

address register, write only
status register, read only
registers write access, write only
registers read access, read only

Miscellaneous output latch, interrupt enable
Miscellaneous output latch, alphanumerics screen enable

PAL coding is given in Table 2-19.
When the logical AND of terms from
one row is ORed with the AHD of terms from another row, the_~utput goes
low when the result is true.

2-51

TECHNICAL REFERENCE

SYSTEM HARDWARE

Table 2-18

Alphanumeric Decoding PAL

Input
Ou tpu t:

MRDCA1516- A18
A14
A12
AMKRC- A19
A17
A13
All

Comment

-------+---+---+---+---+---+---+---+---+---+--------------------CRT space read

ZBEH- L
or .

L

XBEH- L
or .

L

H
H

H
H

L
L

H . H

L
L

CRT space write

-------+---+---+---+---+---+---+---+---+---+-----------------H
H
CRTC/ATT read
H
L
L

H
H

H
H

H
H

H

CRTC/ATT write

-------+---+---+---+---+--~+---+---+---+---+--------------------L
H
L
CRT space read
H
or L
L
(Inactive term)

RD-

-------+---+---+---+---+---+---+---+---+---+--------------------WRCRT space write
or L

L
L

H

H

L

(Inactive term)

-------+---+---+---+---+---+---+---+---+---+-----~--------------Graphic access
H
H
H
L
L
(Inactive term)

GSELor L

-------+---+---+---+---+---+---+---+---+---+--------------------Character access

CSELor L

L

CR/AT- .
or L

L

L

H

H

L

H

H

L

(Inactive term)

-------+---+---+---+---+---+---+---+---+---+--------------------i.
CRTC/ATT access
L
H

H

H

H

H

H

(Inactive term)

-------+---+---+---+---+---+---+---+---+---+--------------------Extra I/O write
L
L

XSELor L

L

H
H

H
H

L
L

H
H

H
H

H
H

L
L

Extra I/O read

Legend:
L
Low signal.
H = High signal.

=

2.4.8.3
Character Set and Attribute Logic.
Two 74LS374s (U14, U15)
latch the RAM output (both character and attribute) at the ~nd of each
screen refresh access cycle.
This allows a ful~ character cycle time
(500.8 ns) to access the character ROM and EPROM ~nd set
up the dot
shift register.
The required ROM access time is 452.8 ns.
So that the
character
set can include the ability for block graphics, bit 7 out of
the ROMs indicates that the leftmost and rightmost character dots are
to be copied
to
the left and right character-cell border dots.
The
character ROMs should be programmed with active-low data; that is, when
a dot is to appear, the ROM should be programmed with a zero.
Figure 2-7 shows some sample characters.
The reverse video block and
the cursor affect
the entire 9 x 12 character cell; the underline
appears on row 11.
The descenders of lowercase letters
should drop
only one dot line below the level of the other characters so that the
underline, cursor, and reverse video will appear in an acceptable form.
2-52

SYSTEM HARDWARE

TECHNICAL REFERENCE

Copied When Bit 7 is Low

I I
I I
I 654 3 2 1 0 I

I I
Row

165

RO
RI
R2
R3
R4
RS
R6
R7
Re
R9
R10
R11 (UndeI::l ine)

432 1 0

•••••••
• •••
I.i
•• •

.···.1
• ••

.......
.........

Figure 2-7

+++

+++

+++

+++

•••• ••
••••••
2223216-7

Sample Character Font Definition

2.4.8.4 Generating a Character ROM.
To generate a character ROM
EPROM), assemble and·.linkthe source code, then program the device.

Cor

The source file for a character ROM is organized into 16 bytes for each
of
the 256 characters (4096 bytes).
When assembled and linked, this
file fits into a 4K ROM.
Each character can contain only 12 rows
of
dots, and the last 4 bytes of each character must be set to FFH.
Each character on the monitor fits within a 9-column by 12-row block.
Each byte corresponds to the 9 columns within
one row.
For
regular
characters,
the first row is blank (reserved for ascenders), the last
two rows are blank (reserved
for
descenders),
and
the
two
outside
columns are
usually blank
(for intercharacter spacing).
Generally,
then, a typical character fits within a 7-column by 9-row block.
For each character block, column I
at the left.

is at

the right side and column 9 is

Each by t e is encoded as follows:"

*

Bit 0 (the low bit) is at the
right
side of
block and bit 7 (the high bit) is at the left.

*
*
*

Setting a bit to 0 means to put a dot at that location.

*

Bit 0 encodes column 2; bit 1 encodes column 3; and so on.

the

character

Setting a bit to 1 means do not put a dot at that location.
Setting
the high bit to 0 encodes column 1 the same as column
2 and encodes column 9 the same as column 8.

2-53

TECHNICAL REFERENCE

SYSTEM HARDHARE

Two encoding examples are shown in Figure 2-9
Example 1
is
the letter
"E."
Example 2,
a meaningless
graphii
character,
illustrates
some specific applications.
Both hexadecimal
and binary encoding are shown beside each character.
Example 1:

Example 1:

Bit Count
76543210

Dot Count
987654321

•••••••

•
•
•••••
•
•
••••••••

Hexadecimal

Binary

FFH
SOH
BFH
BFH
BFH
S7H
BFH
BFH
BFH
SOH
FFH
FFH

11111111
10000000
10111111
10111111
10111111
10000111
10111111
10111111
10111111

67H
A6H
C5H
E3H
E7H
OOH
6DH
92H
CDH
EBH
F7H
F7H

01100111
10100110
11000101
11100011
11100111
OOOOOOOO
01101101
10010010
U001101
11101011
11110111
11110111

10000000

11111111
11111111

Example 2:

••
• ••

•

•••• •
•
•••
••

•••••••••
• • •• • •
••
•

•• •

••
•
•

Notes:
,.
2.
3.
4.
5.

Column 1 and column 9 must be the same.
Column 1 and column 2 must be the same if the high bit is O.
Column 8 and column 9 must be the same if the high bit is O.
No capability exists for a half-dot shift.
Each character must have sixteen bytes; otherwise, strange characters result.
2223216-8

Figure 2-9

Encoding Examples
2-54

SYSTEM HARDWARE

TECHNICAL REFERENCE

2.4.9.5 Attribute Interaction.
The attributes available for use with
the character display can be used
in any of
the
129 possible
combinations.
The following
paragraphs
explain what
happens
when
'several attributes are active at once.
The attributes have a
priority
in
their effects, and the highest
priority attributes affect all attributes that have a
lower priority.
The order of priority is as follows.
Highest

Lowest

Color attributes - red, blue, green
Reverse video and cursor
Character enable
Blink
Underline

For
example,
when
the underline and blink attributes are set, both
character and underline b~nk.
When the character enable
is
set
to
disable,
no character,
underline,
or blinking activity is present.
When reverse video and blink are set, the character goes
on and off,
the
background
is
lighted,
and the foreground is dark and blinking.
When the character enable is set to disable and reverse video
is
set,
the entire cell is lighted (according to the color attributes).
The color attribut~s define the characteristics of the "light" portion
of the character, that is, either the color (when a
color monitor
is
used) or the intensity (when a monochrome monitor is used).
(

When
the graphics board is used with the alphanumerics CRT controller
board, the graphics screen "shows through" the "datk" portion of
the
alphanumeric character display.
2.4.9.6
Attribute Hardware.
The attribute logic design is of the
"pipeline" type because the activity of the attributes must occur with
dot-timing precision (within 55 ns).
To get data from a latch, through
several
levels of logic, and set up into the next latch, ~ome SCHOTTKY
logic is used.
The attribute data from
the RAM latches
is
latched
again by
two
74S175s
(U16, U17).
This latching allows for the onecharacter delay through the character ROM and provides
tightly
timed
outputs
to
the logic.
The cursor (CUR) and display enable (DE) lines
are also delayed
twice
to keep
them synchronous with
the
other
information (U18).
Propagation delay through the logic can cause timing skews greater than
a
dot
time, so the outputs of the first logic level are relatched one
dot-time later.
After going through the second logic level (MUX U20),
the outputs are latched again for presentation to the video outputs
(U39 74S174).

2-55

TECHNICAL REFERENCE

SYSTEM HARDWARE

The red, blue, and green outputs are buffered by a 74LS244 before being
sent to the 9-pin connector.
The color outputs and composite sync are
buffered by a
74S00,
vhich has an isolated poyer supply.
They arr
combined by a resistor netvork and buffered by a transistor to make up
the
composite video output.
The mapping of colors to intensity in the
composite video output is given in Table 2-19.
Table 2-19

Code
Composite sync
'000
001
010
011
100
101
110
111

Color Map
Composite Video Output
(in Volts)

Color

0.47
0.79
0.99
0.97
1.07
1.19
1.29
1.37
1.47

Black
Blue
Red
Magenta
Green
Cyan
Brovn
White

To blank the alphanumerics display to black. set the CRT ENABLE bit
in
the miscellaneous output latch to loy.
The board enters this state on
poyer-up.
2.4.9.7 CRT Interrupt
Logic Subsystem.
The CRT controller board
contains a
logic subsystem
that
alloys
the CRTC
to generate an
interrupt during
the vertical
interval.
The processor uses
this
interrupt
vhen doing scrolls
vith a status line or other operations
that must be done during the vertical blanking
interval.
To enable
this interrupt, set the interrupt enable bit in the miscellaneous latch
to high.
Vertical blanking causes the CPU nonmaskableinterrupt, and
the
interrupt pending bit
is
set.
This bit
is
read from
the
miscellaneous buffer.
To reset the interrupt, set the interrupt enable
bit to loy.
2.4.9.9
Diagnostic Loopback.
One diagnostic requires that the three
color outputs be looped back to the miscellaneous ~nput buffer so
that
the CPU can read them.
Using a program vith careful timing from the
vertical interval, the CPU can check the action of
the atribute bits
and the graphics board palette circuits.

2.5

EXPANSION BUS

The
other
logical
function area of the motherboard is the expansion
bus.
It provides space for the different option boards available
for
the Texas Instruments Professional Computer.

2-56

SYSTEM HARDWARE

TECHNICAL REFERENCE

The
expansion
bus
interface consists
of five card-edge connectors,
making it easy to add memory-mapped
or
I/O-mapped
options
to
the
system.
The expansion bus supports devices that require interrupts for
efficient
operation.
The system does not provide the special-purpose
hardvare required by direct memory access (DMA) devices.
The expansion bus pin-outs are given in Table 2-20.
Table 2-20

Expansion Bus Pin-Outs

Pin

Signal

Pin

Signal

A01
A02
A03
AO ...
A05
A06
A07
A09
A09
A10
All
A12
A13
A14
A15
A16
A17
A19
A19
A20
A21
A22
A23
A24
A25
A26
A27
A29
A29
A30
A31

NMIDATA 7
DATA 6
DATA 5
DATA 4
DATA 3
DATA 2
DATA 1
DATA 0
WAITLogic ground
ADDRESS 19
(MSB)*
ADDRESS 19
ADDRESS 17
ADDRESS 16
ADDRESS 15
ADDRESS 14
ADDRESS 13
ADDRESS 12
ADDRESS 11
ADDRESS 10
ADDRESS 9
ADDRESS 9
ADDRESS 7
ADDRESS 6
ADDRESS 5
ADDRESS 4
ADDRESS 3
ADDRESS 2
ADDRESS 1
ADDRESS 0
(LSB) *

B01
B02
803
804
B05
806
807
B09
B09
B10
B11
812
813
814
B15
B16
B17
B19
819
B20
821
822
823
B24
825
826
B27
B29
B29
B30
831

Ground
RESET
+5 V pover
IRO
(interrupt 0)
No connection
(bussed)
No connection
(bussed)
-12 V pover
Reserved
+12 V pover
Ground
AMHC(memory vrite)
MRDC(memory read)
AIOHC- (I/O vrite)
IORC( I/O read)
No connection (bussed)
No connection (bussed)
No connection (bussed)
No connection (bussed)
No connection (bussed)
PCLK
(5-MHz clock)
IR6
(interrupt 6)
IRS
(interrupt 5)
IR4
(interrupt 4)
IRl
(interrupt 1)
IR2
(inte~rupt 2)
Ho connection
(bussed)
RFSH
(refreshing)
ALE
(address latch)
+5 V pover
OSC
(15-MHz clock)
Ground

* MSB = Most significant bit; LSB = Least significant bi t.

2-57

TECHNICAL REFERENCE

2.5.1

SYSTEM HARDWARE

Expansion Bus Signal Descriptions

*

NMI-.
The nonmaskable interrupt signal can be driv~n by any
of
the expansion boards
to interrupt the system processor.
Typically, it is used to alert the processor to a parity error
in memory devices residing in
the I/O channel.
An open
collector device pulls this line lov vhen it is being driven
by an expansion board.
Othervise, it is held high by a pullup
resistor.

*

DATA 0-7.
These lines form the 8-bit system data bus and can
be driven by the processor, memory devices,
I/O, or the
expa~sion interfac~.
These bidirectional lines are active
high.
DO is
the least-significant bit,' (LSB) and D7 is the
most-significant bit (MSB).

*

WAIT-.
This signal indicates vhen a device is holding
the
system processor,
thereby extending the length of a memory
refresh or I/O cyc.le.
When a slov device is addressed on
the
expansion bus, the signal asserts this line lov, vhich extends
the cycle-completion time.
This line should never be held low
longer
than 10 processor clock cycles.
When driven by an
expansion board, an open collector device pulls this line low.
Otherwise, a pullup resistor holds it high.

*

ADDRESS 0-19.
These lines fQrm a 20-bit system address bus,
which can address up to 1 megabyte of memory.
They are
normally driveri by the system processor to address ~emory and
I/O devices vithin the system.
(Only XAO trough XA9 are used
for I/O addressing.) These lines are active high.XAO is
the
LSB and XA19 is the MSB.

*

RESET.
This line initializes or resets system logic at poverup or after a pover failure.
It i~ active high. _ A poversupply monitoring device generates RESET immediately when
the
12-V
line drops below 11.1 V.
It returns lov 3 ms after
regulation resumes.
Ho operator intervention is required.

*

INTERRUPT 0-6.
These lines signal the processor that an I/O
device requires attention.
When several devices require
service at the same time, the device, asserting the lovestnumbered line gets serviced first.
These lines are active
high.
The interrupt request signal must be held high until
the interrupt request has been acknowledged.

*

AMWC- (or MWRITE-).
The memory write signal is usually driven
by the system ubdex(AMWC-) processor.
It indicates that the
information on the data bus should be vritten
to
the memory
address given on the address bus.
This signal is active lov.

*

MRDC-

(or

MREAD-).

The memory read signal is driven by the
2-58

SYSTEK HARDWARE

TECHNICAL REFERENCE

system processor.
It indicates that the memory addressed by
the address bus should be placed on the data bus.
This signal
is active lov.

*

AIOWC- or
(IOWRITE-).
The I/O vrite signal is driven by the
system processor.
It indicates that the I/O device addressed
by
the address bus
should accept the data on the data bus.
This signal is active lov.

*

IORC- or (IOREAD-).
The I/O read line is driven by the system
processor.
It indicates that the I/O device addressed by
the
address bus
should place
its data on the data bus.
This
signal is active lov.

*

PCLK (processor clock).
This is the system clock.
It
is a
one-t~ird division &! the OSC clock and has a period of 200 ns
(5.0 KHZ).
The clock has a duty cycle of 37.6 percent (~ 3.0
percent).

*

RFSH (refreshing).
This line indicates that a memory refresh
cycle is taking place.
It is positive true.
Khen this signal
is asserted,_ all expansion bus activity is ignored.
Do not
use this lirte £or arty purpose.

*

ALE (address latch).
This line indicates that
is placing a valid address on the address bus.
valid on the falling edge of this signal.

*

ose (clock).
This signal describes a high-speed clock having
a 66.7-ns period (15.0 KHz).
It has a 50-percent duty cycle.

2.5.2

the processor
The address is

Loading and Driving Requirements

The expansion bus can drive five
expansion boards.
Each board can
support
the equivalent
of tvo TTL input loads on anyone line of the
bus.
Open collector outputs, vhich drive the bus, should be able
to
sink 16 milliamperes (mA) at 0.5 V.
Data bus drivers should be able to
sink 24 mA at
0.5 V and source 3 rnA at 2.4 V and 15 mA at 2.0 V.
Drivers for the interrupt lines IRO-IR6 should be able to source 1 mA
at 3.5 V and sink 1 mA at 0.5 V.
2.5.3

Kemory Timing

The memory bus cycles can be lengthened in integral multiples of the
CLK cycle time (200 ns) using the KAIT- line.
Figure 2-9 shovs
the
timing relationships of the expansion bus memory interface.

2-59

~

III

o

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....lI:

I - 133 -.J

....'II

67

~

200

o

>-

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t"4

IQ

.,c::

:u

PCLK

It

'"
I

I
I

'J
I

ALE

ID

III

:::I

I

:

.

MRDC-

0

II

I

\1)

0

.,

:::I
..,.

.,
It

til

PI
0

"

....~
iii
....

:::I
IQ

....t:7
PI

.,PI

IQ

a

I

I

I

:u

III
lI:

o

III

B

,I

\

I

I-

~I

C

-I E I-/-F
\ I

H

-.jG

I

7

/.-D

I I

I

\

1/1

I

II
I

!I--

-..J

I

i:)

VALID

J

I

~F
I

-.1

I
I..

I'
-i

I~------------------

I

-- - - - - - - i i { Il__.....X

_I..

K

-tI"•

~L

I

~

DATA
(READ)

I

III
'II
III

:1-~I
Ir----------------

I

--+-l

-I DIK
I

DATA
(WRITE)

I

i

VALID ADDRESS

_ _ _ _ _ _ _ _ _ _ _ _ _;.'~I-------__.

WAIT

'<

....

I

!
A

I

!

I

I \

It

'"

I

I"

!I:

a0

I

-----------------~!~

AMWC

IIJ

c::

I--

!,ix::

I

I

!x:::::x

ADDRESS

....CD
:::I

\

I

)(

'tJ
PI

I
I

I

X~JV~A~L~IDcbl:C)~~----------1- ivI-I

LEGEND:
A
B
.C
D
E
F
G
H
I

J
K
L
M

-

-

ADDRESS SETUP TO COMMAND
ADDRESS HOLD FROM COMMAND
COMMAND ACTIVE
COMMAND DELAY FROM P~LK
WAIT
ACTIVE SETUP
WAIT
HOLD
WAIT
INACTIVE SETUP
DATA VALID AFTER AMWC
ACTIVE
INACTIVE
DA T A HOLD AFTER AMWC
REQUIRED ACCESS TIME FROM MRDC
INACTIVE
DATA SETUO TO MRDC
INACTIVE
DATA HOLD FROM MRDC
DATA SETUP TO PCLK LOW

INACTIVE

72MIN
176MIN
575 MIN 375 min (WITHOUT WAIT STATE)
35MAX
lOMIN
40MIN
OMIN
50MIN
120MAX
EXPANSION BUS
108 MIN
515 MAX 315 MAX
MEMORY INTERFACE
77 MIN
4MIN
TIMING DIAGRAM
50MIN

fn
~
{/l

~

III
2223216-9

3:

:c
>:u
o
~

>-

:u
rq

SYSTEM HARDWARE

TECHNICAL REFERENCE

I/O Timing

2.5.4

Figure
2-10
shows the expansion bus timing relationships for standard
I/O cycles.
This timing
includes
the
single
wait
state
that
the
motherbo~rd always inserts in I/O cycles.

--l

67

~133

~I"

200

"I

PCLK
I

I

I

I

I

ALE

~
I

ADDRESS

I

I

I

I

I
\~~------------------------~------~;--

f-A-I
X~

__ i

~~~~~
VALID ADDRESS

____________

I_-B~
r-~I
____~__- -____----.I~

IORC

I
I

AIOWC

\,
.

I

_II I..

:

:

C ,
- -....

I

I

I

d

\

.+..l
I

I"

~I

E

F

-IDI-.

I-

DATAIW~R.;.;IT~E~)~I
I ------------~II~r----v
i '---"
I

______x:

I
I

I
I

I ·
I

~~

VALID DATA

'""",.._ _ . _ - - - - - H - - - - -......04-1......-

I

G

-l

I)
I -H J f.I

I

DATA(RE~A~D~I~____________-1I-1-------------------------------,~------~~

..JX

(~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

REQUIRED

VALID/

)

f--K-I
LEGEND:
A
B
C
D
E
F
G
H
I

J
K

.
-

ADDRESS SETUP TO PCLK LOW
ADDRESS SETUP TO AIWOC . OR IORC
ADDRESS HOLD AFTER AIOWC - OR IORC
COMMAND DELA Y FROM PCLK
ACTIVE IORC OR AIORC . TIME
DATA VALID FROM AIOWC LOW
DATA HOLD AFTER AIOWC - HIGH
REQUIRED ACCESS TIME FOR IORCREQUIRED DATA SETUP TO RISING EDGE OF IORC-REQUIRED DATA HOLD AFTER RISING EDGE OR IORC-REQUIRED DA T A SETUP TO PCLK LOW

Figure 2-10

Expansion BUB

62MIN
72 MIN
176 MIN
35 MAX
575 MIN
120 MAX
108 MIN
515 MAX
85 MIN
-4 MIN
50 MAX

10 MIN

I/O Interface Timing Diagram

2223216-10

HARDWARE OPTIONS

TECHNICAL REFERENCE

section 3
HARDWARE OPTIONS

3.1

INTRODUCTION

This section describes the hardvare options available for
the Texas
Instruments
Professional
Computer.
Subsections
describe
the
following options:

*
*
*
*
*.

Expansion Memory
Synchronous-Asynchronous Communications Board
Internal Modems
Graphics Video

~ontroller

Board

W.i ncb-est er Di sk Dr i ve

The optional diskette drive is
identical
to
the factory-installed
diskette drive.
Therefore. it is not described in this section.
For
information, refer to subparagraph 2 .. 4.6.6.

3.2

EXPANSION MEMORY. 512/169 K BYTES

Section 2 describes the expansion memory boards that connect to the
motherboard. increasing the memory to
256K bytes
eK = 1024). Tv~
additional
expansion memory boards (each 256K bytes) are available
for the Texas Instruments Professional Computer.
One board plugs
into
the
e~pansion
bus,
increasing the memory to 512K bytes.
The
second board mounts on the first (piggyback style so
that
they use
only one of the expansion bus slots), increasing the memory capacity
to 168K bytes.
This additional memory operates at the same speed as
the motherboard memory,
so
that there is no increase in execution
time vhen the memory is increased.
NOTE
The 512/168 K byte expansion boards
after
the
motherboard
192K-byte
installed.

3-1

-are added
board
is

TECHNICAL REFERENCE

HARDWARE OPTIONS

The first expansion memory card is the controller card.
This
card
contains thirty-six 64K-bit dynamic RAM ICs.
The card also holds:

*
*

*

Decoding logic to establish the addresses
Parity check logic for error detection
Timing and
system.

refresh

logic

to operate the expansion memory

Connectors and logic for the addition of the
are also part of the controller card.

second

expansion

card

The second card also contains thirty-six 64K-bit dynamic RAM ICs.
Secause tha.controller card contains all the logic for both cards,
this second card is smaller.
3.2.1

Addressing the Expansion Memory

The expansion memory operates at a fixed address in the computer's
memory space.
Addresses·040000H through 01FFFH are for
the first
256K bytes;
addresses 080000H through OSFFFFH are for the second
256K bytes.
If the second card is not installed, its assigned memory
space can be used by other hardware products.
3.2.2

Expansion Memory Control. Logic

The expansion bus contains a bidirectional buffer. to separate
the
data bus from
the expansion memory, thereby providing sufficient
drive and margins to the data transfers.
The hard array logic
(HAL)
chip HAL16R4
(U2) handles address decoding, buffer control, as well
as timing and ~efresh.
The refresh timer (U4) is a one-shot, and the
delay line (U3) provides the multiplexer timing.
3.2.2.1 Expansion Memory Refresh Logic.
The dynamiC RAM refresh
logic operates
synchronously with
the accesses to the RAM memory.
Refresh cycles begin only when a RAM cycle is not in progress.
This
means
that the RAM refresh can occur at the same time as accesses to
other system memory (ROMs or the main system memory)
or
I/O space.
Each
time a refresh cycle begins, a refresh timer (U4) starts.
When
it .times out, it provides the signal beginning another refresh cycle.
This timer is set to 15 us maximum, which allows for
the worst-case
refresh request
latency.
To maintain the contents of the RAM under
worst-case conditions, the refresh must
occur at
least
128
times
within 2 ms.
(The average refres~ timing is once per 15.625 us.)
The worst-case latency for a refresh request is about 600 ns.
Once a refresh cycle has begun, it must be completed
(including
the
precharge)
before
the next
cycle begins.
If a RAM access cycle
starts before the refresh cycle completes, the HAL state machine puts
the CPU into a wait state until the refresh operation completes.
In
3-2

c

HARDWARE OPTIONS

TECHNICAL REFERENCE

the
worst case, this delay could extend the usual memory access time
by three wait states or 600 ns.
Assuming a refresh timer value
of
14 us,
and an average
400-ns
slowdown of
the CPU,
the average
refresh overhead is about 2.9
percent.
The worst case is about 4.3 percent.
3.2.2.2 CAS and Address MUX Switch Generation.
A delay line from
the
Column Address Strobe X (CASX-) produces the address multiplexer
control (MSEL).
The delay line is set at
40 ns.
U1
buffers
the
CASIline,
and the RAM buffers are taken from the delay line 60 ns
after CASX-.
This ensures the maintenance of an adequate row address
hold, and enough column address setup time.
The RAM still
operates
quickly enough to finish an access within the system cycle time.
The CASXtiming dep&nds on whether the cycle is a read or a write.
If the cycle is a read, the CASX- signal
from
the
logic array
is
equivalent
to the RASI- signal.
This provides the maximum available
time for the RAM chip to access it's data and present
it
to
the
expansion bus.
The delay line guarantees the timing of MSEL and
CASI- to the dynamiC RAMs.
If the cycle is a write, then the CASXsignal follows
the
rising
edge of the first system clock during the write cycle.
This is about
130 ns after the occurrence of RASI-.
This delay allows time for the
data from the processor to propagate through the data buffers and US,
the parity generator chip (74LS280).
3.2.2.3 Expansion Memory Parity Generation and Checking.
The parity
generator/checker
chip (74LS280) generates a 1 to the parity RAM bit
whenever there is an even number of
"l"s
in
the data byte
being
written.
A separate data bus on the parity RAM chip uses a tristate
driver to provide a high on the output whenever it is not driving the
output line (as in the write cycle).
The parity is theft
taken
from
the "odd sum" output of the parity generator and used to write to the
dynamic RAMs.
The WCAS- line from the logic array holds the parity
error flip-flop (US) clear.
The timing on this line stays low until
after
the
CASIline
clocks
the
flip-flop.
This prevents the
generation of a parity error during write.
When the RAM is read, all of the data bits and
th~
parity bit
are
presented
to the generator/checker, and the parity output is sampled
at the end of the read cycle.
If a parity error is discovered, flipflop US is set to interrupt the CPU on the HMI- line.
This NKI- line
clears on the next read with correct parity, or on the first write to
this board.
Using the "odd sum" method of parity ~hecking does not cause a parity
error, even when the system attempts to read
from nonexistent
RAM.
(To determine
the
size of system memory, system software sometimes
"feels" for memory not present.

3-3

TECHNICAL REFERENCE

HARDWARE OPTIONS

3.2.2.4 Expansion Memory Control State Machine.
A hard array logic
device
(HAL16R4),
set up as a state machine (U2), drives the memory
control.
This device has four outputs equipped with clocked flipflops
and four
outputs that are direct combinations of the inputs.
Table 3-1 gives the logic for the memory control state machine.
The
logical AND of
the
terms
on a line ORed with the AND of terms on
other
lines
results
in low-going outputs.
This
occurs either
directly,
on
those outputs without registers, or after the clock on
those outputs having registers.

3-4

HARDWARE OPTIONS

TECHNICAL REFERENCE

Table 3-1

ExpanBion Memory Control State Machine Logic - HAL16R4

_.....;._ _ _ _ _ _ 1 npu t ___________

RFSHRASIXA19
MRDXWAIT- RRASLGNDMWRCASX- WCASXXXX
RFRQ
BU1;E- ZZZZ- Comment
B2INXA19
output
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+-------------------------------Mem.ory read loW' bank
H H
L H L
RASI- L
Memory read high bank
H H
L
H L L
or L
Memory W'rite loW' bank
H H
or
L
L H L
Memory W'rite high bank
H
H
L
L
L
or
L
H
Refresh
or
-.
- -- - ---+ - + - + -'+ _.+-+- + - +-- - +-+ -+-+ - + - +- + - +- ----- - --- - - -- - - - ---- - - - - -- -- --Refresh+memcycle 1, 2
. L L .
XWAIT- .
Refresh+memcycle 2. 3
. L • L •
or .

.

.

·
·

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+----~---------------------------

,
i

Write, either bank
H
CASXL
Read
loW' bank
or L . · L H L .
· H H .
Read
high
bank
or L . · H L L. . · ..L
-.
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+-------------------------------Write loW' bank
BUFEL
L H L
Write high bank
or
L
H L L
L
Read loW' bank
or L
L H L
or L
Read high bank
H L L
L
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+-------------------------------The folloW'ing four outputs have flip-flops:
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+-------------------------------Refresh 1 ; no memcycle
RFSH- H H H
H
Refresh 1 ; motherboard cycle
or
H L L
H
Refresh"l; graphic cycle
or
H H H
H
or
Refresh 1 ; high" bank not in
H
H H L
H
or
H
Refresh 1 ; illegal cycle
H
or
Refresh RF2,3
L H
or L L
H ..
Reset
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+-------------------------------RRASRefresh RF2,3,4
· L .
or L L .
Reset
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+-------------------------------WCASWrite loW' bank
L
L H L .
· H H
Write high bank
or . L . H L L . L
· H H .
or L L .
Reset.
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+-------------------------------ZZZZ- L L .
Reset
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+-------------------------------Legend:
L
LoW' signal.
H = High Signal.

.

.

.

.

.

·

.

=

3-5

TECHNICAL REFERENCE

HARDWARE OPTIONS

Notes for Table 3-1
1. The signal RASI- activates RAS- from the RAM address
multiplexer of the 2964.
2. The signal XKAIT- puts the processor into a vait state.
3. The signal BUFE- activates the expansion memory system data
buffer.
4. The signal CASX- controls the CAS and MSEL generation.
5. The signal RFSH- instructs the 2964 address multiplexer to
put out the refresh address.
6. The signal RRAS- combines vith RFSH- to indicate that a
refresh RAS is in progress.
7. The signal WCAS- delays CASX- during a vrite cycle.
8. The signal ZZZZis not used.
A timing diagram of the raemory system, shovn in Figure 3-1,
the major operations of the memory system.

indicates

"i

PI

n

T2

T2

T1

T4

1W

T3

Tl

T4

TW

T3

T2

Tl

T4

TW

T3

T2

TW

TW

T4

PClK
(5 MHzl
AMWC-

...

~

J

7~

\

Ir--------------------~-----------------------------------

\

MRDC-

'tJ

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r-

>---<

ADDRESS}----(

r-

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r---<

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DATA

(

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c=:x:E::3)

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RffiQ

til
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RFSH-

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_ _ _ _ __

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~

ZUZo-------------------------------------------------------------------------------------------------------------I
~
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3~
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'RASI- "

400

CASX-

450

I

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\_

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BUFE- ""'"""\

250

\

\

~

r-

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__~_---------'

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'-

116
WAIT-

\

300

I

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500

I

IQ

PI

CXY-

a

ROW
ROW ICOl
ADDR

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F3
WRITE

COLUMN

X

H
-

\

x:::x

ROW

E3

x

ROW

I

COLUMN

XH

\
ROW

X

WRITE + REFRESH

-

MUST BE VALID

I
COLUMN

x:::ax F"3
READ

\
ROW

X

lO<

Fd

ROW

COLUMN

x:::BX t=--i

r

:r:

x::

:u
o
s:
>:u

READ + REFRESH

:110

rrJ

256/512K OPTION MEMORY TIMING DIAGRAM
2223216-11

o"0

...o

"i

:z:
til

TECHNICAL REFERENCE

3.3

HARDWARE OPTIONS

SYNCHRONOUS-ASYNCHRONOUS COMMUNICATIONS BOARD

This subsection describes the theory of operation and
the functions
of
the synchronous-asynchronous
communications
(sync-async comm)
board.
Figure 3-2 is a block diagram of the sync-async comm board.
Refer to Section 6, draving 2223096, for logic diagrams.

INTERRUPT
ACKNOWLEDGE
LOGIC

ADDRESS

CHIP SELECTOR

...
IIOBUS

1

)

.

SELECT
COMM

II'

COMMUNICATIONS
CONTROLLER

DATA BUS )

...

SE LECTINPUT

SEL ECTOUTPUT

INPUT/OUTPUT
CYCLE
SELECT

-

~

l

II'

::.

RECEIVERS

S.YSTEM¢1
UNIT
BOARD

"I:

<

....
DATA BUS.

INTERRUPT

1

CLOCK

SELECT
1/0

ADDRESS
DECODE
LOGIC

~

ri

/~

SELECT
ACK-

- ..

INT ACK

...

~

RS-232-C
IN TERFACE

rf

tt
I I

DATA BUS
BUFFER

~

l...J",.
~

:r>
rt+U
I

TRANSMITTERS

EXTERNAL
DEVICES

I

INTERRUPT
LOGIC

2223216-12

Figure 3-2

Sync-Async Comm Board Block Diagram

The
sync-async comm board
is based upon
the Zilog Z8530 Serial
Communications Controller (SCC).
This device. automatically handles
asynchronous protocols.
It also services most synchronous protocols,
including data link control (SDLC) and high-level data link control
(HDLC), (both bit-oriented.)
Cyclic redundancy check
(CRC)
is an
automatic function and can be included in .any transmission.
NOTE
A sample program,
shoving general programming
procedures and recommended use of the sync-async
3-9

TECHNICAL REFERENCE

HARDWARE OPTIONS

=omm board,
is
in=luded
in Appendix E of this
manual.
For more detailed information, refer
to
the Zilog 8530 Technical Manual.

The functions of the sync-async comm board are:

*
*
*
3.3.1

System interface
Baud rate generation
Port addresses
Sist~m~nterface~

Most
of
the components on
the board are involved in handling the
interface between the system bus and the Z9S30.
Of special note
is
the logic
that
generates the interrupt acknowledge (INTACK) signal
that the Z9S30 requires in response to an
interrupt
request.
The
IKTACKsignal ~s software-generated.
It is not part of the system
interrupt acknowledge signal because of the setup time
required and
because
the
system expansion bus does not provide for expanding the
number of interrupt levels.
To generate the IKTACK- signal, the software does "a AIOKC- (write) to
the I/O address for interrupt acknowledge and
then does a
IORC(read)
from the same address.
The data received on this read is the
interrupt vector from the Z9S30.
The AIOKC- signal clears USB, activating the IKTACK- signal
to
the
Z9S30.
Khen
the
IORC- occurs, the vector from the Z9S30 is gated
~nto the data bus.
The rising edge of
IORC- clocks" USB
to
the
inactive state which releases the IKTACK-.
Other logic on the system side of the board delays the read and write
commands
to the SCC so that the address and data setup times and the
hold-time requirements of the part can be met.
IORQ is connected
to
the
input of a flip-flop 74LS74 (USA).
The clock input is connected
to the system CLK line.
The rising edge of the clock occurs 133 ns
after
the
IORC- or AIOKC- signal occurs.
The output of USA, gated
with IORC- and AIOKC-, delays the start of
the SCCRD- and SCCKRsignals.
The clear input to USA is connected to BDCS, allowing the
SCCRD-.and SCCKR- signals to occur only when the board is selected.
Resetting the Z9S30 requires that the SCCRD- and the SCCKR- lines be
held active simultaneously.
This results from the logical OR of U6C
and U6D with the RESET signal from the bus and the SCCRD- and SCCKRlines.
U4C
inverts and butters
the
interrupt output from the SCC.
This
signal then goe~ to a set ot stake pins and is used to determine
the

TECHNICAL REFERENCE

HARDWARE OPTIONS

interrupt level at vhich the board is operated.
3.3.2

Baud Rate Generation

The
4.9152-KHz
by 2,
crystal
oscillator
on
the
board,
divided
provides a clock for the SCCs (internal baud
rate
generators).
To
generate a specific baud rate, program the values given in Table 3-2.
Table 3-2

Baud
Rate
19
9
7
4
3
2
2
l.
1

20Q_
600
200
800
600'
400
000
800
200
600
300
200
l.50
134.5
l.l.0
75
50

Sync
Value
62
126
l.69
254
339
510
6l.2
-681
1022
2046
4094
6l.42
8l.90
9l.34
1l.l.69
16382
24574

Sync-Async Comm Board Baud Rate

Percentage
of Error
0.000
0.000
-0.l.96
0.000
0.098
0.000
0.065
-0.049
0.000
0.000
0.000
0.000
0.000
0.001
-0.001
0.000
0,000

Async
Value
2
6
9
l.4
19
30
36
4l.
62
26
54
82
l.0
69
96
1022
l.534

3-10

Percentage
of Error
0.000
0.000
-3.030
0.000
1.587
0.000
l..053
-0.775
0.000
0.000
0.000
0.000
0.000
0.001
0.026
0.000
0.000

TECHNICAL REFERENCE

3.3.3

HARDHARE OPTIONS

Addressing

A 74LS139 decoder
(U3)
and several gates (to qualify the address)
comprise the address selection logic.
The board design presents a
choice of four address locations, permitting the addition of several
communications boards to the system.
As vith other I/O devices for this bus, only 10 of the address
lines
are decoded.
U3 provides
tvo decoded
outputs:
INTCS-,
vhich
activates the INTACK logic; and SCCCS-, vhich activates
the
Z8530.
The
logical OR of INTCS- and SCCCS- creates the board select signal
(SDCS).
The logical AND of IORC- and AIOKC- creates IORQ.
SOCS and
IORQ combined enable the bus buffer U7.

3.3.4

Programming

The
sync-async comm board port
number
is programmed by placing
jumpers on the board.
Five I/O addresses and a
distinct
interrupt
level control each p~rt.
Table 3-3 gives the board addresses for
is the board connector.
I

/

the four possible ports.

P60

TECHNICAL REFERENCE

HARDWARE OPTIONS

Table 3-3

Sync-Async Comm Board Port Addresses
Port 1

Jumper
Locations

P60
Pin No.

EI-E2
E7-E8

8 (INTO)

Interrupt

Address

Function

OOEO
00E4
OOES
00E6
OOE7

Interrupt acknovledge
eHB command
CHB data
CHA command
CHA data

Port 2 Interrupt
E4-ES
EIO-Eli

50 (INTI)

00E9
OOEC
OOED
OOEE
OOEF

Interrupt acknowledge
eHS command
CHB data
CHA command
CHA data

Port 3 Interrupt
E2-E3
E8-E9

49

(INT2)

OOFO
00F4
OOFS
00F6
00F7

Interrupt acknovledge
CHB command
CHB data
CHA command
CHA data

Port 4 Interrupt
ES-E6
EII-EI2

46

(INT4)

00F9
OOFC
OOFD
OOFE
OOFF

·3-12

Interrupt acknowledge
CHS command CHB data
CHA command
CHA data

HARDWARE OPTIONS

TECHNICAL REFERENCE

Two

channels
(A and
B) from each port control the ZS530 operations.
A, the main communications channel through which data
transfer
"akes place,
also monitors or controls some of the RS-232-C signals.
Channel B does nothing but control or monitor signals.
It is not
used
for data transfer.
~hannel

Each channel
can be accessed by two addresses:
The command address for either channel is used to
read
or write
registers that control the Z8530
address for channel A is used
to
read
received
transmitted data.
The data address for channel B

"command" and "data."
access any of the
15
operations.
The data
data and
to write
is not used.

Because
the
Z8530 does not contain pin-outs for the DSR, SCF, and RI
signals, unused pins from channel B are used f~r these signals.
Table
3-4 lists the specific pin-out for these signals.
Table 3-5 lists the
Channel B pin_-o~t for theZ-~530 interrupt enables.
Table 3-4

Channel B Pin-Out for Z8530-

Z8530 Signal
DSR
SCA
SCF
RI

Channel B Pin-Out
DCD
DTR
SYNC/HUNT
CTS

/

Table 3-5

Channel B Pin-Out for Z8530 Interrupt Enable

Z9539 Interrupt
DSR
SCA
SCF
RI

Channel B Pin-Out
DCD
none
SYNC/HUNT
CTS

Each port has an I/O address used to acknowledge the Z9530
interrupts.
An I/O write followed by an I/O read done at this address acknowledges
the interrupt.
The data written during the I/O write
is
irrelevant.
After
the
I/O read, the Z8530 returns the code for the interrupt that
occurred.
These
codes are
explained
in
the
Zilog 9530 Technical
Manual.

3-13

TECHNICAL REFERENCE

HARDWARE OPTIONS

The external connector (369) is an RS-232-C type.
the signals at this connector.
Table 3-6

Table 3-6 identifies
(

RS-232-C Connector Signals

+------+-------------------------------+----------+
Signal Name
I Pin
I Signal
+------+-------------------------------+----------+
1.
Chassis ground
I AA
2
3
4

5
6

7
8
9

'1.0
1.1.
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9

20
21.
22

23
24
25

Transmitted data
Received data
Request to send
Clear to send
Data set ready
Signal-ground
Data carrier detect
No connection
No connection
Secondary request to send
Secondary clear to send
No connection
No connection
Transmitter clock in
No connection
Receiver clock in
No connection
No connection
Data terminal ready
No connection
Ring indicator
Same as pin 1.1.
External transmitter clock
No connection

I
I
I
I
I,
I
I
I

BA
BB
RTS/CA
CTS/CB
DSR/CC
AB
DCD/CF

J

1 SCA/CH
I SCF/CI
1

I
I TXC/DB
I
I RSC/DD
I
I

1

DT~/CD

I
I "RI/CE
J

SCA/CH

I DA
t

+------+-------------------------------+----------+
3.4

INTERNAL MODEMS

Texas
Instruments offers
tvo
internal modems for the Professional
Computer.
One is a Bell 1.03-compatible type, vhich operates at
300
baud.
The other
is Bell 21.2-compatible and operates at 1.200 baud.
Both are full-duplex modems, and the Bell 21.2-compatible can operate
in full-duplex,
synchronous,
1.200 baud.
These are "smart" modems,
and can handle a variety of commands for establishing communications.
Both modems have automatic dialing c_pability using either pulse or
tone dialing.
The modem also provides status
indications
for
monitoring the progress of the dialing procedure.
The folloving subsections describe the architecture and interface of
the modems to the system for those users vho vant to vrite their ovn
communication program, and vho vant to use an internal modem.
3-1.4

HARDWARE OPTIONS

TECHNICAL REFERENCE

3.4.1

Architecture

The interface hardware for the modem board
is
identical
to
that
created
for
the
sync-async
comm board.
Therefore, it is easy to
adapt software written for the sync-async comm board so that
it
can
operate
with either of the modems.
Adding code to handle the modem
dialing procedure is
the major
change
required.
The
same port
addresses
and interrupt levels used by the sync-async comm board are
used by the modem boards.
Figure 3-3 shows a block diagram of modem hardware.
The
serial
controller
(Zilog 8530)
sends
the modem commands during the modem
initialization and dialing procedure.
Then the Z8530 transfers
data
between the modem and the remote system.

MICROPROCESSOR
RJ

-

11

(1 )

ZILOG
8530

(2)
(3)

MODEM

-

I

RJ

11
2223216·13

Figure 3-3

3.4.2

Modem Hardware Interface

Zilog 8530--Modem Signals

Two special control signals, /RHCTL (request control mode) and /ACHTL
(acknowledge
control mode), tell the modem how to handle information
passed by the Z8530.
/RHCTL information is processed as
commands,
while /ACHTL information is interpreted as data t~ be transmitted.
The
signals that appear at
in Figure 3-4.

the Zilog 8530--modem interface are shown

3-15

TECHNICAL REFERENCE

HARDHARE OPTIONS

Zilog 8530
15
13
18
16
21
29
19
22

(fTD)
(fRD)
(lCTS)
(fDTR)
(TDSR)
(fSDCD)
(fDCD)
(fRI)

Modem

•
•

ICB

•

•
•

(/TRXCA)

ICD
ICC
ICI

•

ICF
ICE

•

23 (lRTSB)
11 (fSYNCA) •
12 IRTXCA)
22

BA
BB

~

IRCNTL
IACNTL

~

•
•

IRX CLOCK
ITX CLOCK

2223216-14

Figure 3-4

Zilog 8530--Modem Interface Signals

The folloving paragraphs give brief descriptions of these signals.
~

NOTE

'

In the folloving descriptions,
active-lov TTL voltage level.

"O~"

refers to

an

(ITO) -> SA The
Z8530
sends data
to the modem on this line.
The
condition of /RCKTL determines the type of data
(either
transmitted
data or command data).

SS -> (/RD)
The modem sends data
to the Z8530 on this line.
The
condition of /RCNTL determines the type of data
(either
transmitted
3-16

HARDKARE OPTIONS

TECHNICAL REFERENCE

data or eommand data).
ICB -} ICTS)
Khen
this
signal is on, the modem is ready to receive
transmitted data from the Z8530.
Even when this signal is
off,
the
Z8530
can
still
send command data if IACNTL is on and ICD (DTR) is
off.
No transmitted data is sent while this signal is off.

(/OTR) -} ICD Khen this signal is on, the terminal is ready to start
the communication.
This signal is turned on while the unit is in the
command mode, but before giving
the
start-dial
command.
(If
the
start-dial
command
is given before /DTR is on, the modem returns a
"command failed" status.)
ICC -> (/DSR)
The modem completes dialing, then turns this signal on
while waiting for
the answer
tone and
the
carrier.
The modem
indicates_. three
thingL by
turning
this
signal
on:
that it is
electrically connected to the communication line;
that
it
is
offhook; and that it is ready to start communication activity.

ICI -) (/SDCD)
After answering a
call,
the modem generates this
is
being
transmitted
to
the
signal to
indicate how fast
data
indicates
that
data
is
being
terminal.
Turn~ng
the
line
on
data
transmitted at high speed.
Turning the line off indicates that
During the originate modes, this
is
being transmitted at low speed.
signal represents the selected rate of data transfer.
ICF ->

(lOCO)

data
signal
begin.

Khen this signal is on, the modem
is
receiving
the
from
the
communications
line and communications can

ICE -> (/RI)
The modem generates the voltage levels on this line
to
indicate
the
ringing activity.
Khen the signal is on, the line is
ringing.
Between rings, or when there is no ringing, the
signal
is
off.
The
software detects the ringing activity thro~gh the ZS530,
and asserts DTR if the call is to be answered.

(/RTSS) -> IRCHTL The software uses this signal to change
the mode
of data
transfer.
Khen
this
signal is on, it indicates that the
terminal wants to enter into the command mode.
In command mode,
the
modem does
not transmit the data received on the line SA.
Instead,
it uses the data for command and status information exchange between
the
terminal
and
the modem.
During
initialization and dialing
procedures, the modem uses the command mode
to
send modem dialing
commands and to receive status information.
Once
the data transfer mode is initiated, the command mode cannot be
invoked again unless the line is disconnected.
IACNTL -> (SYNCA)
The modem generates this signal in response to the
IRCHTL signal from software.
The software does not send any command
data
on
line
SA
until
this signal is turned on.
Khen the /RCHTL
signal goes away and the modem enters the data
transfer mode,
this
Signal
is
turned
off.
The /ACHTL signal is usually pulled high on
the RS-232 interface board.
Khen both /RCNTL and /ACNTL are on,
the

3-17

TECHNICAL REFERENCE

HARDWARE OPTIONS

terminal can exchange commands and information with the modem.
The /ACKTL signal combined with the /RCKTL signal can differentiate'
between the modem board and a sync-async comm board.
To check for an
installed modem, the software first activates the RCNTL,
then
waits
for
the modem to return the /ACNTL signal.
If no acknowledge signal
returns, then a sync-async comm board is
installed,
rather
than a
modem board.
This
lRX CLOCK -> (lRTXCA)
asynchronous communication.

is

lTX CLOCK -> (.!TRXCA)
This is
asynchronous communication.
3.4.3

the
the

receive

data

clock

line

for

transmit

data

clock

line

for

Mo-dem Initialization

At
power-up,
the RESET signal
on
the system bus initializes the
modem, using the operating defaults.
The user can reset the modem to
these same defaults at any time with the software reset command.
The default parameters are listed in Table 3-7.
Table 3-7

Modem Default Parameters
\,

3.4.4

Parameter

Default Setting

Dialing
Line termination
.Kodem transmitter
Modem mode
Data/command mode
Communication

Pulse ·-dial
On hook
Squelched
Originate
Data mode
Asynchronous

Command Mode Operation

The modem has two modes of operation, data transfer mode and command
(also
called
control)
mode.
The
terminal
system software
communicates with the processor on the modem board,
either for
the
data
transfer or
the command mode.
All data and command transfer
passes through the USART.
At power-up, the default setting is for the data transfer mode.
For
various
reasons,
such as a software request for diagnostic status
information, it is necessary to place the unit in command mode.
The
terminal and
the modem are in master-slave configuration, and the
modem cannot initiate the command mode.

3-18

HARDWARE OPTIONS

TECHNICAL REFERENCE

To prepare for command mode operation, the Z8530 must be set
up for
300-baud
operation,
no
parity, 8 bits per character, one stop bit,
and one start bit.
The Zilog 8530 Technical Manual contains
details
on
setting the Z8530.
Also, refer to subsection 3.3 of this manual.
Appendix F contains "RCNTL", a sample subroutine that checks
for
an
installed modem.
Once
enter
line
modem
until

the appropriate signals are set, the modem and the terminal can
into a command status transfer dialogue.
The software asserts
/RCNTL,
requesting
the modem to enter the command mode.
The
responds by asserting the line /ACNTL.
The software then waits
/ACNTL is turned on by the modem before sending any commands.

To find the status of the modem,
the
computer
transmits
the
code
"send diagnostic status" (44H).
The modem returns a 2-byte response,
the
firsf- :byte
indicaFing
that
the "status byte follows" and the
second byte giving the status.
The commands and status codes are
listed
later
in
this
section.
Appendix F contains
"DIAGST",
a
sample
routine
for
starting a
dialogue in the command mode.
After the modem completes a command from the
computer,
it
sends
a
"command
complete"
(A=41H) code or a "command failed" (Z=5AH) code.
After sending a command, the computer waits
before
sending another
command,
expecting
either
a
direct
response
or a
command
complete/failed status.
The terminal software can insert a fail-safe time-out between issuing
a command to the modem and receiving the command
status
to protect
against possible modem malfunction.
After the software completes the command/status dialogue, it releases
the /RCNTL
line.
The modem responds by releasing the /ACNTL line.
Th~ system is now in the data transfer mode.
The command mode cannot be
reentered
unless
the
communication
is
halted and
the
phone line is disconnected.
The software turns off
the DTR signal when the
line
is
to
be
disconnected.
The modem
disconnects
the line any time DTR is turned off, once the connection
has been established.

3.4.5

Dialing Procedure

To begin a call, the terminal transmits the telephone
number
to
be
dialed
(including any separator symbols such as ( ) ,
+, or @) and
instructions on the method of dialing (such as T or P).
For example,
in the telephone number T(713)-895-0001X, T requests
tone
dialing,
and
X is
the
telephone
number
terminator.
The number can be a
maximum of 23 digits long.
The
modem
responds
with
the
"command
complete"
status,
then
dials
the
number.
Appendix F contains
"Dialer", a sample routine for dialing a telephone number.
3-19

TECHNICAL REFERENCE

HARDWARE OPTIONS

The ( ) and - separators are used for number-grouping purposes
only.
They have no meaning to the modem.
The modem reads the + separator
as tandem dialing.
Each time the modem finds a
+,
it
waits for
another dial
tone before continuing.
The a symbol represents blind
dialing.
When the modem finds the a separator. it waits 2.0 ~ 0.1
s
after
the command is received, then dials the number without waiting
for a dial tone.
The dialing methods
include
tone dialing,
pulse dialing,
and
automatic
selection.
The modem is able to alternate dialing methods
during the dialing procedure.
Simply insert the proper characters (T
for tone dialing, P for pulse dialing) in the telephone number.
For
example, in the number
T8-50-33333344-P(713)-895-0001,
the modem dials all the digits to P using the tone mode; all digits
after P are dialed using the pulse mode.
The modem echoes the number
back to the terminal (without separators) as
it dials each digit,
then
sends status to the terminal for full call-progress monitoring.
The status can be ringing, busy, no answer, or voice.
The
terminal
screen displays th~ appropriate message.
When
the connection attempt is successful, the modem does not return
a status indicator.
Instead, the computer monitors the Signal lOCO.
The modem asserts lOCO, indicating a successful connection.
The dialing procedure is aborted any time the DtR signal is dropped.
The modem sees this as a command to stop dialing, and goes on hook.
The modem waits
through 10 rings before reporting a
no-answer
condition.
The default
time
to wait between retries is 11 s, the
default number of retries is O.
Ten rings as a
no-answer condition
is a fixed number; however, the time to wait between retries and the
number of retries can be programmed into the terminal software.

3.4.6

Time-Outs

Both the terminal and the modem can cause
time-outs.
The
terminal
time-outs are:
loss of carrier"
long space received,
and no
response.
The two types of modem time-outs are:
loss of carrier and
abort timer.
Table 3-8 summarizes the time-outs.

3-20

TECHNICAL REFERENCE

Table 3-8

HARDWARE OPTIONS

Type~

and

Duration~

of Disconnects

Terminal

Modem

Type

Duration

Type

Duration

Loss of carrier
Long space received
No response time-out

200 ms
1.5 s
1 s

Abort timer
Loss of carrier

17 s
SO ms

The foIl oW'-i ng paragraphs---q i ve
conditions.
3.4.6.1

Terminal or

Soft~are

br i ef

descriptions

of

all

time-out

Time-Outs.

*

Loss of Carrier.
If
the
terminal is programmed for failsafe disconn~cts ~hen the carrier goes off, it ~aits
50 ms
before disconnecting.

*

Long Space Received.
At
start-up.
the
terminal
sends a
command to the modem, then ~aits for the modem
to
turn
on
the
/ACNTL signal.
If the modem fails to return the signal
~ithin 1.5 s,
the terminal disconnects.

*

No Response.
The terminal sends a
then
~aits for
the modem response.
disconnects.

3.4.6.2

command
to
the
modem,
After 1 s, the terminal

Modem Time-Outs.

*

Loss of Carrier.
During a temporary loss of
carrier,
this
timer holds
the
DCD line
true.
Ho~ever,
if the carrier
stays off for 50 ms ( the length of the
timer),
the modem
turns
off the DCD signal to the Z8530, causing the soft~are
to recognize the loss of the carrier.

*

Abort Timer - Originate Mode.
During the automatic
dialing
procedure,
the modem goes off hook to listen for the dial
tone.
The modem waits 17 s, then sends the "command failed"
status and goes on hook.
The terminal responds by dropping
DTR.
The
abort
timer
resets
after
the
dialing
procedure is
complete.
If the modem being used is a Bell 212A-compatible
type, the abort timer is set for Bell 212 high-band carrier.

*

Abort Timer - Answer Mode.
During
a
manual
dialing
procedure,
the answer-tone abort timer is used instead of
the dial-tone abort timer.
The originating modem looks
for

3-21

TECHNICAL REFERENCE

HARDWARE OPTIONS

an answer
from
the remote modem.
The answer depends upon
the type of modem installed in the remote
system.
If
the
remote
is
Sell
l03-compatible,
the modem looks for the
carrier.
If the remote is Sell
212-compatible,
the modem
looks
for
the scrambled mark or the unscrambled mark.
The
modem waits 17 s for the answer tone, then drops DSR.
3.4.7

Modem Software

The modem software is very simple.
Some commands are
only 1 byte
long,
such as the "Manual Disconnect" command.
Field commands, such
as "Telephone Number" (an op code followed by a field), are longer.
The terminal sends a command to
the modem.
The modem returns a
direct
re~po~se
or a ~tatus byte
(command complete or command
failed).
The terminal does not send additional commands
until
this
handshake is completed.
Table 3-9 lists the software commands from the terminal to the modem.

3-22

TECHNICAL REFERENCE

Table 3-9

ASCII Code
A
B
C
0

E
F
G

H
L
M
0

P
R
S
T
U

W
X

Y
+

•

HARDWARE OPTIONS

Commands from the Softvare to the Modem

Command
Dial folloving telephone number, select dialing mode
Next byte contains number of retries (ASCII, 0-9)
Next 2 bytes contain time (in s) betveen
retries (ASCII, 0-99 s)
Request diagnostic status
Disconnect on loss of carrier
00 not disconnect on loss of carrier
Manual ansver
Select lZOO- bps option
Select 300- bps option
What modem type?
Manual originate
Dial folloving telephone number using pulse dialing
Start RDLB test*
Syn~hronous communication mode
Dial folloving teleghone number using tone dialing
Asynchronous communication mode
Softvare reset
Telephone number terminator
Start ALB test**
Tandem dialing (vait for another dial tone)
Blind dial (vait 2.0 s, then dial)

* The RDLB (Remote Digital Loopback) test is for a Bell 212compatible
modem.
It checks the condition of
the
communication
lines.
The
originating modem makes the ansvering modem echo all
received data
back to the originating modem.
**

The ALB (Analog Loopback) test causes the modem's internal logic
to connect the transmitter to the receiver and loopback the data.

Table 3-10 lists the possible

re~ponses

3-23

from the.modem.

TECHNICAL REFERENCE

Table 3-10
ASCI I Code
A
B
D
E
F
H
L
N
0

R
V
Z

HARDWARE OPTIONS

Response from the Modem to the Softvare

Command
Command completed
Busy tone
Diagnostic status follovs
Phone number terminator
Phone number follovs
Bell 212A option installed
Bell 103 option installed
No ansver
Lost call
-Ringing from ringback
Voice reception
Command failed

One
possible modem response
is
D,
diagnostic
status
follovs.
Immediately after the modem sends this reply, it
sends
one of
the
diagnostic indicators from Table 3-11.

Table 3-11
Byte Value
00
01
02
04
08

10
20
40
80

3.5

Diagnostic Status Indicators

Meaning
Good check
ROM error
RAM error
Processor error
Timer error
Not used
Not used
Not used
Not used

GRAPHICS VIDEO CONTROLLER BOARD

The
graphics video controller board operates vith the CRT controller
board.
It is mounted
(piggyback
fashion)
on
the CRT controller
board,
and all
its
connections are
to the CRT controller board.
Figure 3-5 is a block diagram of the graphics video controller board.
(Refer to Section 6 for logic diagrams.)

3-24

HARDWARE OPTIONS

TECHNICAL REFERENCE

CPU
ADDRESS

RED PIXEL

TO

r-1'.. CRT
Y CONTROLLER
BOARD

8-1

8-1

MUX

MUX

W

~

~

3

..."
...w"t;;

~

'"
!:!

Q

"
~

!:
Q

..;t

"...
"
~

."~

;0
Q

t;;

.

;t

TO CPU ,,..,,-"-_ _ _ _- - ,

READ-DATA
HOLD LATCH

2223216-15

Figure 3-5

Graphics Video Controller Board Block Diagram

The graphics video controller board uses the same
number
of
pixels
(720
horizontal
x
300
vertical)
on
the
screen
as
does
the
alphanumerics board.
Each pixel
can
contain
a
maximum
of
three
attribute
bits
(labeled
A,
B,
and
C).
These attribute bits are
converted by a palette look-up table to threa colors
red, blue, and
green.
Aspects of the graphics video
section include:

controller

3-25

board

described

in

this

TECHNICAL REFERENCE

*
*
*
*

HARDWARE OPTIONS

Pixel addressing
Color selection
Timing and synchronization
Graphics logic array program

3.5.1

Pixel Addressing

Each dot
on the graphics screen is a pixel.
Each pixel has a 3-bit
value associated vith it that selects one of eight palettes (0 7).
Each palette
is assigned one of eight colors, as determined by the
contents of the latch._ The latch is simply an array of eight
3-bit
values.
The palette number of each pixel is an index into that
array.
So, the color of a pixel is the color value of
the latch
entry
that corresponds to the palette number of the pixel.
Changing
either the palette or the color assigned to the palette changes
the
color of
that pixel.
Changing
the color assigned to a palette
changes the color of every pixel vith the same palette number.
A plane is a block of memory containing 1 bit for each pixel
in
the
display.
Each of
the 3 bits assigned to a pixel is in a different
plane.
All three planes are formatted identically; only the
segment
address differs from plane to plane.
The segment addresses of the
three planes are COOO,
CBOO,
and 0000.
For example,
if a
bit
assigned
to pixel
(x,
y)
is
the fifth bit
of memory location
COOO:mmmm, then the other tvo bits assigned to
that pixel are
the
fifth bits of locations CBOO:mmmm and DOOO:mmmm.
In
the folloving explanation, memory addresses refer to offsets into
the segment of any of the three graphics planes.
The diagram belov
shovs the organization of graphics screen memory into pixels.
Pixels
are numbered (x coordinate, y coordinate) and are zero relative.
Byte
Address

I Pixels Represented

0000 - 0 0 5 B I (B , 0) 005C-00B7 I(B,l) -

(15, 0 ) I (0 , 0) (15,1)1(0,1) -

( 7 , 0) I (24, 0) (7,1)1.

(31, 0 ) 1.( 16 , 0) -

(23, 0 )

Pixel (0,0) is the MSB of location 0001.
The LSB of location 0001 is pixel (7,0).
Pixel (B,O) is the Msa of location 0000.
The LSB of location 0000 is pixel (15,0).
Pixel (16,0) is the Msa of location 0003.
The bytes are flip-flopped in this way so that if a move instruction
executed from a vord in the graphics plane to a word register, the
3-26

HARDHARE OPTIONS

TECHNICAL REFERENCE

register then contains 16 consecutive pixel bits in order from KSB to
LSB.
For example, if a
KOV AX,
ES:OOOO
is
executed
(where ES
contains
the segment address of the desired graphics plane), the KSB
of AX is pixel (0,0) and the LSB is pixel (15,0).
Hith this
scheme,
45 words are necessary to represent the 720 pixels in each row of the
display.
There is one unused word at the end of each line, so a new
row begins every 46 words, or 92
bytes.
Line
one
(zero-relative)
begins
at byte address 92 decimal, OOSCH.
Therefore, pixel (0,1) is
the KSB of location OOSDH and pixel (8,1)
is
the KSB
of
location
OOSCH (because the bytes are flip-flopped).
Example:
To
find
the values of the rightmost 16 pixels on the bottom line of
the display,
X
•

299 (zero-relative number of last line on display)
92 (bytes per line)
88 (first word = 0, second word = 2, so 45th word

= 27596

= 88)

(6BCC hex)

So, KOV AX, ES:6BCC puts the values of the
last
16 pixels
on
the
display
in AX, with the LSB of AX being the pixel in the lower right
corner.
The three graphics planes
are
named· A,
B,
and
C.
The
segment
addresses
of
the planes
A,
B,
and Care COOO, ceoo, and DOOO,
respectively.
In determining the palette number of a pixel, the
bit
from the C plane is the most significant, the bit from the A plane is
the least significant, and the B plane bit is in the middle.
Example:
To find
the
color
of
the
pixel in the lower right corner of the
display, first find the palette number assigned to it.
The KSB of the palette number is the LSB of DOOO:6BCC;
the middle bit of the palette number is the LSB of C800:6BCC;
the LSB of the palette .number is the LSB of COOO:6BCC
Say,
for
example,
that
these
three
bits are
1,
0,
and
1,
respectively.
Then
the
color of the lower right pixel is whatever
color is assigned to palette 5.
If the default color assignments are
in effect, the color of the pixel is cyan.
3.5.2

Color Selection

Each of the eight entries in the latch has one bit for
each of
the
three primary
colors:
green,
red, and blue.
The eight available
colors are formed by combinations of those three colors, as listed in
Table 3-12.

3-27

TECHNICAL REFERENCE

HARDWARE OPTIONS

/

Table 3-12
Green

Red

Color Combinations

Blue

0
0
0
0

0
0

0

1
1

0

1
1

0
0
1

0

1

1

1
1

Color
black
blue
red
magenta
green
cyan
yellov
vhite

1
1
1

0

Color
0
1

2
3
4
5
6
1

To access the latch, you must vrite all eight bits
~f
a
particular
primary cO~Dr to the appropriate memory location for that color.
You
cannot change all three bits corresponding to one palette number in a
single vrite.
The latch consists of three memory locations, ~ne for
each of the primary colors.
These locations are:
Blue latch
Green latch
Red latch

DFOO:0010
DFOO:0020
DFOO:0030

You can vrite to these iocations, but you cannot read from them.
For
this reason, it is necessary to maintain a memory image of the
three
color
latches ifindividual palettes are to be changed.
You are then
able to change a single palette by setting the appropriate bits
in
the memory
image
to the desired value and updating all three color
latches.
Each of the three color bits of a palette is in the same bit position
in all three color latches.
Hovever,
the
scheme for
determining
vhich bit
in
the
latch.is addressed by ~ pixel is n~t ~he same as
that for determining the palette number.
In determining
the
latch
bit addressed by the three-bit value assigned to a pixel, the B plane
value is the most significant and the C plane value is in the middle.
The A plane value is still the least significant.
Bit 1 is the KSB
and bit 0 is the LSB of the color latch byte.
Table
3-13 displays
the
correspondence betveen the bits assigned t~ a pixel and the bit
positions in any of the three color latches, and shovsthe comparison
of these bit positions to the palette numbers.

3-29

-

TECHNICAL REFERENCE

HARDWARE OPTIONS

Table 3-13

B Plane
Bit

C Plane
Bit

0
0
0
0
1
1

1
i

Bit Correlations

Palette
Number

Latch Bit
Addressed

A Plane
Bit

0
1
4

0
0
1

0

0

1

1

0

1

1

5

0
0
1
1

0

2
:3
4

5

3

6
7

6
7

1
0
1

2

Figure 3-6 shows this correspondence horizontally,
latch byte appears as a byte register.

B plane bit
C plane bit
A plane bit

1
1

1
1

1
0

1

0

1

0
1
1

1
0
0

so that

1

0
0

0

1

0

Latch bit addressed

7

6

5

4

3

2

Palette number

7

6

5

4

3

2

1

the

color

0
0
0

0
0
2223216-18

Figure 3-6

Color Latch Byte

Example
This example shows how to create a memory image of the default values
of the three color latches.
Combining information from Table 3-12 (the Color Combinations table),
with information from Table 3-13 (the Bit Correlations table), yields
the information necessary to construct Table 3-14.

3-29

TECHNICAL REFERENCE

HARDWARE OPTIONS

Table 3-14

Latch
Bit

Default Values of Color Latches

Palette Number
(= Color Number)

7

7

6
5

6

3
2

4
3
2
1

5

4
1
0

~

Green
Bit

(white)
(yellov)
(magenta)
(red)
(cyan)
(green)
(blue)
(black)

Red
Bit

1
1
·0
0
1
1
0
0

The defauit
condition
is palette number
the color latches are set as follows:

Blue
Bit
1
0
1
0
1
0
1
0

1
1
1
1
0
0
0
0

= color

number;

therefore,

-

Green latch = 11001100 binary = CC hexadecimal at DFOO:0020
Red latch
1111000 binary
FO hexadecimal at DFOO:0030
Blue latch
10101010 binary
AA hexadecimal at DFOO:0010

=

=
=

=

Example:
This example lists the steps necessary to change
yellov from the default condition (magenta).

palette

three

1. Find the desired palette number (three) in Table 3-14,
find the associated latch bit (five).

then

2. Find the desired color (yellow) in Table 3-14,
the bit settings (red = 1, green = 1, blue = 0).

find

3. Set bit five in each of the color
determined
in
the previous step.
nev values:

=

then

latches
to
the values
This ~hange creates the

=

Green latch
11101100 binary
EC hexadecimal
Red latch = 11110000 binary = FO hexadecimal
Blue latch = 10001010 binary = SA hexadecimal.
three
4. Krite the nev values (from the previous step) to the
not
color latah addresses.
(In
this
example,
it
is
necessary to change the red latch, because
the
value did
not change.)

3-30

to

HARDWARE OPTIONS

TECHNICAL REFERENCE

3.5.3

Timing and Synchronization

The
same
dot
clock
that
generates
internal
timing for the CRT
controller
board
clocks
the
graphics
video
controller
board.
Monitoring
the
display enable
(DE) signal from the CRT controller
board helps to synchronize the pixel outputs from the two boards.
If
the DE signal has been low for a
long period,
the
graphics
board
assumes that the scan is in the vertical interval.
When DE goes high
again, the graphics board resets the graphic memory and scan counters
to
zero.
When DE is low for a short period (horizontal retrace, for
example), the scan counters are stopped.
This places the last
pixel
on a line adjacent to the first pixel on the following line.
The
graphics
video
controller board gives the CPU essentially free
access to the screen memory.
During a single screen
display cycle,
the hardware ·can access ~t"he refresh memory twice -- once to read the
data for screen display, and once for the CPU to read or
write data
if needed.
To provide enough time for this access, a display cycle
accesses 16 adjacent pixels of 3 attribute bits each.
These are read
in parallel and loaded into three 1S-bit shift registers for display.
After the memory has been read for screen
display,
the
CPU access
cycle
starts
when. ..a read or write cycle is requested.
The accessed
memory is broken up into
one
of
six
separate bytes
by properly
decoding
the enabling of bus buffers and write enable signals to the
memory.
Dynamic memory is used on the graphics video
board because
of
the
large amount of memory required.
The memory chips are organized into
16k x
4 bits
and are
packaged in an 1S-pin, dual inline. package
(DIP).
The S address lines are multiplexed into
256
row addresses
and 64 column addresses to get to the 16 K locations in the memory.
The addresses to the RAM also need to be multiplexed between the
CPU
and
the
refresh counter.
Performing this four-way multiplexing are
four 74LS153 dual 4-to-1 multiplexers (U33 through U36).
Figure 3-7 is a timing diagram for
the
graphics
video
controller
board.
A 74LS163
4-bit counter (U39) and a HAL16RSA-1 logic array
(U41) generate the timing.
A 74LS163 counter connected as a one-shot
(U40), a 75LSOO gate (U44), and a 74LS04 gate (U45) provide the stop,
start, and reset logic for the refresh counter.

3-31

Ii
111

n

::c

'1'J
~.

IQ

.,c:
ID

W
I
~

FIRST
LAST SCREEN I DISPLAY I CPU READS, SECOND
CYCLE DURING', CYCLE ' SCREEN I DISPLAY
H BLANKING
OF LINE
MEM
CYCLE
Xl

I

!

, DISPLAY,
CYCLE

'DISPLAY
. CYCLE

>t;-t

I
I

DISPLAY
CYCLE

I

::0
111
'1J

111
::0
111

X2
ROW-

UJ-----:L-____~------~------~--~--~------~------L-----~r------i-----

GRCLK

.,PI

CPU
WRITES
SCREEN
MEMORY

...n:z:

::r:
o

111

Ii)

'tJ
::J'

....

n

UI

<
....

I

SRLD

U

I

y

U,r------------,u

U

u r- - -

RDWRGSELRAS- - - .
CAS-

\

I

I-

\

'

r-o~____~

0.
ID

0
W
I

n

I\)

0
!:I

w

.,

IT

0

.....

....

.,

ID

BUFFEN-

~r------~------~------~--------~------~~

LATENLA TO E_
GWAIT-

I I [J I Ll L ILl U

DE
DEDXRST-

,
u

tJ

....

PI

.,

aQ

PI
iii

It---

....
....iii
::s

~GRCLK~

XRST

nTlT)-Y-rT-r-r-r-r-,--,,-,--,

[

;-1

Ii

IQ

L-__--DII::I:T

fTTTJ

I

'

I

FIRST PIXEL OUT OF SHIFT REG
FIRST PIXEL OUT OF U43
FIRST PIXEL OUT OF PALLET
~

----,u

~
I

,

I

DEU-

!l

-----ur-----------,
~L------------~~,-----------

MC
CCLR
COUNT _

~

I

,

~r-------

END OF ACTIVE VIDEO

, ,
~

END OF H BLANKING

,

,

~

ONE-SHOT TIME-OUT DURING
VERTICAL INTERVAL

-----fi~

,

___________

,

~

END OF VERTICAL BLANKING

::c
>-

::0

tJ
~

>-

::0
111

o

"1J

2223216·19

...Iio
:z:
til

HARDWARE OPTIONS

TECHNICAL REFERENCE

3.5.4

Graphics LogiC Array Program

programming for the logic array is given in Table 3-15.
Table 3-15

Programming for

the Graphics State Machine HAL

Input
LATENBUFENRDXl
LATOE- SRLDWRX2
RASGWAITROWGSELGRCLK
CASDEDDE
output

Comment

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+------------------------------Read S5,6,7,8
H L

LATEH- L
-L .•
or
L L
or
L L
or L L

L

Write S3
write S4 till not write
All other ORs inactive

L

L

L .

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+------------------------------Read S8
H H H L
L

LATOE- L
L
or . L . L
or
L L .

.

.

L

Read S9 till not read
All other ORs inactive

.

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+------------------------------Refresh screen Sll
L H L H

RASor
or
or
or
or
or

L

L

L
L

L

L H
H H
L
L H

.

L

L L
L

H

H
H

,

L
"

L
L
L

L L

write S3
Read S3
CPU S4, refresh S12
CPU S5,6, refresh S13,14
CPU S7, refresh S15
(Inactive term)

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+------------------------------S13,14,15,0,5,6,7,8
. H •

CASor

.

H

,
.

,

L
L

,
.

All other ORs .

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+------------------------------BUFEH- L
L
Read S4,5,6,7,8
L

L

or
or
or

L L
L L
L

H L L L

Write S2
Write S3,4,5,6,7,8
All other ORs inactive

H
L

L

L

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+------------------------------, L H H H
S15

SRLDor

L L .

All other ORs inactive

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+------------------------------GWAIT- L
L
H H
Read
or
or

"

. L L ,
L

L

H .

Write
All other ORs inactive

.

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+------------------------------Delayed DE

DEDor

•
•

H
H

,
.

All other ORs .

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+------------------------------Legend:
L
H

= Low

= High

signal.
signal,

3-33

TECHNICAL REFERENCE

HARDWARE OPTIONS

When the logical AND of terms from one row of Table 3-15 is ORed with
the AND of terms from another row,
the
output
goes
low when
the
result is true.

3.6

WINCHESTER DISK DRIVE AND CONTROLLER OPTION

The Winchester disk drive and controller board option consists ofa
controller board,
cable and hardware,
and a
5or 10-megabyte
Winchester drive.
Aspects of this option described in the following
paragraphs include:

*
*
*
*
*
3.6.1

Winchester hardware theory of operations
Register assignments
Bit

~efinitions

for registers and ports

Controller status bit combinations
Kormal command sequence operation

Winchester Hardware Theory of Operation

The Winchester controller is addressed by the 8088 as a block of four
I/O ports:
0030H through 0033H.
I/O reads are indicated by the bus
signal IORC, and I/O writes are indicated by the ~us signal AIOWC-.
The controller can generate an interrupt to the host under one of the
following conditions:

*

When data
controller

*

and
When the operation
is
completed,
requesting a status read (C/D1, I/O

is

ready

to

be

read

=

from

or written to the

the
= 1)

controller

is

Both of the interrupt conditions can be individually disabled.
When
the interrupt is active, the computer's interrupt line 6 is held high
until it is cleared by a read to the controller status register.
3.6.1.1 On-Board EPROM/ROM.
A 4K x 8-bit
EPROM/ROM
driver
routines
for
the controller.
Addressing this
the output to drive the data bus
through a
tristate
EPROM/ROM
is at. memory address OF8000H.
Access time
EPROM or the ROM is less than 350 ns.

3-34

contains
the
device causes
buffer.
The
to either the

HARDWARE OPTIONS

TECHNICAL REFERENCE

3.6.1.2 Commands and Command Testing.
The computer sends a
6-byte
block
to the controller to specify the operation.
This block is the
device control block (DCB).
Table 3-16 gives the bit definition
for
the DCB.
Table 3-16

Device Control Block Bit Diagram

B

y+-------+-------+-B I T N U MB E R -+-------+-------+-------+
4 3 2 1 0
tl
1
I
6
I
5
+e+=======+=======+=======+=======+=======+=======+=======+=======+
o P COD E
101 COMMAND CLASS
+-+-------+-------+-------+-------+-------+---------+-----+-------+
HIGH

LOGICAL UNIT NUMBER

ADDRESS

( See Note 1 )

+-+-------+-~~-~-~+------~~------+-------+-------+-------+-------+

MIDDLE ADDRESS

( See Note 1 )

+-+-------+-------+-------+-------+-------+-------+-------+-------+
LOW ADDRESS
( See Note 1 )
131
+-+-------+-------+-------+-------+-------+-------+-------+-------+
141

INTERLEAVE OR NUMBER OF BLOCKS

( See Note 2 )

+-+-------+------~+-~~---~+-------+-------+-------+-------+-------+

151

CON T R 0 L

FIE L 0

+-+-------+-------+-------+-------+-------+-------+-------+-------+

Hotes:
1. Refer to paragraph 3.6.1.6.
2. I~terleave factor for FORMAT, CHECK TRACK, and READ 10 commands.

3.6.1.3
Explanation of
Bytes
in the Device Control Block.
The 6
bytes that comprise the device control block are defined as follovs:
Byte

Definition

o

Bits 1, 6, and 5 identify the class of the command.
4 through 0 contain the opcode of the command.

1

Bits 1, 6 , and 5 identify the logical un it number (LUN) .
Bits 4 through 0 contain logical disk address 2.

2

Bits 1

through 0 contain logica.l disk address 1.

3

Bits 1

through

0

contain logical disk address O.

4

Bits 1

through

0

specify the interleave or block count.

5

Bits 1

through 0 contain the control field.

3-35

Bits

TECHNICAL REFERENCE

HARDWARE OPTIONS

3.6.1.4 Control Field Detailed Description.
Byte 5,
the
control
field
of
the DCB,
allows
the
user to choose options for several
different types and makes of disk drives.
The following
listing
d e fin e s t he
bit s 0 f the con t r 0 I by t e '. Th est e pop t ion s are en cod e d
in control byte 5 of the command descriptor.
The
encoding
is
done
with bits 0 through 3 as given in Table 3-17.
Table 3-17

~

Command Descriptor Byte

Description

Bit No.

Default 3-ms step rate
Seagate ST506 (KLC2)
T~ndpn .fast-step_
Texas Instruments fast-step
200-us buffered-step
70-us buffered-step
30-us buffered-step
1S-us buffered-step
Olivetti 2 ms/step (561)
Olivetti (562) fast-step
(1.1 ms typical)
Spare '(for future use)

3

2

1

0

0

0
0

1

1
1

0
0
0
0
1
1
1
1
0
0

1
0
0
1
1
0
0

0
1
0
1
0
1
0
1

1

1

1

1

0
0
0
0
0
0
0

1

0

To
configure a
drive for fast-step or buffered-step. refer to the
manufacturer's manual for instructions.
If the drive
is hardwareconfigured for
fast-step.
all
commands
requiring the seek option
selection must use the fast-step option for that drive.
NOTE
The step option bits (3 through 0)
are
exclusive.
Select
only one option
configuration.

Bits 4 and 5 are reserved for future

mutually
for
any

us~.

Set bit 6 to 0 for regular operation.
When this
bit
is
set
to 1
during a
read sector command, any failing sectors are not reread on
the next revolution.
Set bit 7 to 0 for regular operation.
Setting this bit to 1 disables
the four retries by the controller on all ~isk-access commands.
Set
bit 7 to 1 only during the performance evaluation of a disk drive.

3-36

'"

.

HARDWARE OPTIONS

TECHNICAL REFERENCE

3.6.1.5
Command Completion status Byte.
At the end of a command,
the controller returns a completion status byte
to
the computer.
This byte
indicates whether or not an error has occurred during
command execution.
(If the error bit is set, and you want
to know
what
caused
the error,
you must
send
the REQUEST SENSE STATUS
command.)
The format of the completion status byte is
Bit
(KSB)
6
5
4
I/O
II
1
Port
AddressJ IDon't IDon't IDrive IDon't
0030
J J care
I care I No.
I care
(r ead) I I
I
J
I

Number

I

3

(LSB)
2

I

1

J

0

I

,+======+======+======+======+======+======+=====+======+
IDon't IDon't !ErrorlDon't I
I care
I care I bi t I care ,
I
I
I
I
I

1+======+======+======+======+======+======+=====+======+

3.6.1.6 Logical Address (HIGH, KIDDLE and LOW).
The logical address
of the drive is computed by using the following equation:
Logical Address
Where:

CYADR
HDCYL
HDADR
SETRK
SEADR

= (CYADR x HDCYL + HDADR) x SETRK +.
= Cylinder address
= Number of heads per cylinder
= Head address
= Number of sectors per track
= Sector address

SEADR

3.6.1.1 Sector Interleaving.
The disk controller supports variable
sector
interleaving.
When a format command is issued, an interleave
value can be passed in byte 4 of the device control block (DCS).
The
maximum interleave value is the number of sectors per track minus 1.
When transferring multiple data sectors, the interleave fa~tor can be
adjusted to achieve maximum system performance.
The practice of
interleaving involves mapping logical continuous
sectors of data from a given track onto nonadjacent physical sectors.
For example, an
interleave factor
of 5 means
that
every fifth
physical
sector
is
transferred as the next logical continuous data
sector.
It does not mean that five sectors of data are
transferred
on one revolution.
If the interleave factor is too low, the CPU cannot transfer the full
sector of data during
the sector-interleave time available.
The
controller has to wait one full revolution before reading
the next
logical
sector from
the disk.
Increasing
the interleave factor
increases the system's operating speed.
The operating system should perform multiple-sector data transfers to
take full advantage of the controller's
interleaving feature.
In
Single-sector
transfers,
the differences
in speed between various
interleave factors is probably not noticeable.
3-31

TECHNICAL REFERENCE

3.6.2

HARDWARE OPTIONS

Register Assignments

The regi~ter assignments
for
the
controller are given in Table 3-18.

Table 3-18

I/O

ports

of

the

Winchester

Winchester Controller I/O Port Assignment

+-------------+--------------------------------------------+
Address
Functions
+---------------------+----------------------+
out
In

+

+-------------+---------------------+----------------------+
0030H
Data IN port
Data OUT port
+-------------+---------------------+----------------------+
0})31H
status register
RESET
+-------------+---------------------+----------------------+
0032H
Hot used
Not used
+-------------+---------------------+----------------------+
0033H
Not used
Interrupt mask
+-------------+---------------------+----------------------+
An
IN function
gets data from the Winchester controller board and
puts it on the computer's I/O expansion bus.
Conversely,
an OUT
function
sets data from
the computer's I/O expansion bus onto the
Winchester disk controller board.
For byte definitions of the registers, refer to the
given in Table 2-1.
For pin-outs of
the
Electrical Interface.

Winchester

I/O

memory

map

cable, refer to paragraph 3.6.20,

3-38

~

HARDWARE OPTIONS

TECHNICAL REFERENCE

3.6.2.1 Data Input Port.
Disk read data and controller sense bytes
pass
through
this register
to the computer.
The data is held for
each handshake cycle.
The format is as follows:
(MSB)
II
7

( LSB)

Bit Number

o I
I/O
Port
I~======~======~======~======~======~======~======~======~
Addres s I I
I
I
I
1
1
I
I
I
0030
I I DATA 71DATA 61DATA 51DATA 41DATA 31DATA 21DATA 11DATA 01
JI
1
I
I
I
I
I
I
I
6

5

4

I

3

2

1

I+======+======+======+======+======+======+======~======~

3.6.2.2 Data Output Port.
Command bytes and disk data pass
through
this
register
to
the controller.
Data is latched until updated by
the CPU.
'i'he . bl t ar rangemen t i s as follows:
BIT HUMBER

MSB
I/O
Port
Address
0030
(wr it e)

6

5

4

I

3

LSB
2

J

1

o

I

"
'1
1+======+======+======+======+======+======+======+======+
II
I
I
I
I
I
I
I
I
II DATA 71 DATA 6·I·DATA 51 DATA 41 DATA 31 DATA 21 DATA 11 DATA 0 I
II
I
I
I
I
I
I
I
I
I+======+======~======+======+======~======+======~======+

3.6.2.3
Controller status Register.
This
register
stores
the
controller
status.
It enables the CPU to read the controller status
and to monitor the controller operation.
The controller status byte
is defined as follows:
MSB

BIT HUMBER

LSB

6
5
I/O
2
1
o
4
I
3
II
7
P0 r t
I + = = = = = = + = = = == == = + = = == = = = + ::: = = = = = ~ = = = = = = + = == == = == == + = == == = .. ':: + = = = == = = ~
AddressllDon't IDon't IDon't IDon't IDon't ICOMMAHDIINPUT/I DATA
I
0031
Ilcare
!care
Icare
Icare
I.care
!/DATA
10UTPUTIREQUESTI
( read) I I
I
I
I
I
I
I
I
I
I~======+======+======+========~=======+=====~===~=======+=======+

3.6.2.4
Reset Port.
This byte resels the controller.
Any write to
port 0031 causes a reset.
Reset clears each error status, aborts all
operations, and places
the Winchester controller
in
the command
receive mode.
The byte definition follows:
MSB
BIT HUMBER
LSB
I/O
6
5
4
I
3
1
o
II
7
2 I
Port
I+======+======+======+======+=======+======+=====~=======+
AddressllDon't IDon:t IDon't IDon't IDon't IDon't IDon'tlDon't
0031
Ilcare
Icare
Icare
Icare
Icare
Icare
Icare Icare
(wr it e) "
1
I
I
I
I
I
1
I~=======~======+======+======~======+======+=====+======+

3-39

TECHNICAL REFERENCE

HARDWARE OPTIONS

3.6.2.5
Interrupt Mask.
This is a 2-bit field that determines vhich
interrupts are
to
be serviced by the CPU.
The interrupt mask byte
definition follovs:
MSB
I/O
II
7
Port
AddressllDon't
0033
I I care
1I

6

5

SIT NUMBER
4
I
3

2

I

1

LSB
0

J+======+======+======+======+======+======+======+=======+
IDon't
I care
I

IDon't
I care
I

IDon't
I care
I

IDon't
I care
I

IDon't
I care

I

IDATA
ISTATUS
I INTR. 1 INTR.
I ENABLE I ENABLE

1+======+======+======+======+======+======+======+=======+

3.6.2.6
Error status Byte.
This
special
byte
is available
only
after
the
completion of a command.
The controller sets the I/O and
C/O bits vi{h·DRQ
to
in~icate
that
this
byte
is available.
A
definition of the error status byte follovs:
MSB
I/O
II
7
Port
Addressl IDon't
0030
Ilcare
( read) I I

BIT NUMBER
6

5

4

I

LSB
2

3

I

1

o

1+======+======+======+======+======+======+=====+======+
!Do~'t

Icare
I

JDrive !Don't
INo.
Icare
I
I

IDon't
Icare
I

IDon't
Icare
I

IErro~!Dontt

I bit Icare
I
J

J+======+======+======+======+======+======+=====+======+

3.6.3

Bit Definitions for Registers and Ports

Table
3-19 gives
the
definitions
controller registers and ports.

3-40

of

bits

for

the

Winchester

HARDWARE OPTIONS

TECHNICAL REFERENCE

Table 3-19

Bit Definitions for Controller Registers and Ports

Logical state

+---------+--------------------------------------------------------+
I Data
I Bit

I Data true ; data high
1 logical one >= 2.4 V

IDATA 0-7
I READ or
I WRITE

I
I

;

1

Data false

; data lo~ ;
(=
0.7 V

I logical zero

+---------+============================+============================+
Data bit = 1

Data bit

=0

+---------+----------------------------+-------------------------~--+

IDATA

I
I

REQUES~

Commands,

status,

or data

I, ready to b~__ transferred
I to or from controller.

No command,

status,

or

I data transfers to or from
I controller.

+---------+----------------------------+----------------------------+
I INPUT/
I The CPU reads data or
I The CPU writes data or
I OUTPUT-

J

status from the controller. I commands

to the controller. I

I COMMAND/
I DATAI
I
I
I

1 When INPUT/OUTPUT- is high, I When IKPUT/OUTPUT- is high,1
I status is sent to the CPU. I data is sent to the CPU.
I

+---------+----------------------------+----------------------------+
1****************************1****************************1
I When INPUT/OUTPUT- is low,
I commands are sent to the
I controller.

I When IKPUT/OUTPUT- is low,
I data is sent to the
I controller.

I
I
I

+---------+----------------------------+----------------------------+
I Controller interrupts the
I CPU after the CPU completesl
ISTATUS
I the current command and is J
I I NTERRUPT I ready to return the status I
I ENABLE
I byte.
I

No status interrupt
permitted.

+---------+----------------------------+---------------~------------+

lDATA
I
I INTERRUPTI
I ENABLE I
I
I

Controller interrupts the
CPU ~hen data needs to be
read from or written to
the controller.

No data interrupt
permitted.

+---------+----------------------------+----------------------------+

3-41

TECHNICAL REFERENCE

3.6.4

HARDWARE OPTIOKS

Controller status Bit Combinations

Table 3-20 gives all valid controller status bit combinations.

Table 3-20

Valid Bit Combinations for Controller status

--------------------------------------------------------------------+
!COMMAND/IINPUT/ I DATA
II
I

DATA

Meaning of Pattern

I OUTPUTIREQUEST!!

+========+=======+=======++=========================================+
o

I
~.

o

o

!

"

Kot valid

- II
II

+========+=======+=======++=========================================+
o

o

1

I I A data byte may be sent from the CPU
I I to the Winchester controller. The
I I controller waits for data to be written.

+========+=======+=======++=========================================+
o

1

o

II
II
II

Hot valid

+========+=======+=======++=========================================+
o

1

1

I I A data byte may be sent to the CPU
I I from the Winchester controller. The
II

controller waits until data is read.

+========+=======+=======++=========================================+
1

o

o

I!

Kot valid

"
II

+========+=======+=======++=========================================+
1

o

1

II Command bytes may be sent to the
II Winchester controller from the CPU.

"

+========+=======+=======++================~=~===========~=========+

1

1

o

II
II
II

Not valid

+========+=======+=======++=========================================+
1

1

1

II
II
II

A status byte may be sent from the
Winchester controller to the CPU.

+========+=======+=======++=========================================+

3-42

HARDWARE OPTIONS

TECHNICAL REFERENCE

2 6.5

Normal Command Sequence Operation

Figure 3-8 depicts the logical flow of the controller functLons.

WRITE OR READ
CONTROLLER DATA
(READ/WRITE TO
PORT 0030)

RESET THE
WINCHESTER
CONTROLLER
WRITE TO PORT 31
WAIT1

•
NO

READ STATUS
PORT 0031

NO
WAIT1

NO

READ STATUS
FROM PORT
0030

HARDWARE
FAULT
NO
WAIT1

OUTPUT COMMAND
BYTES TO
CONTROLLER
(WRITETO
PORT 0030)

DO REQUEST
STATUS COMMAND
AND
DECODE ERROR

NO

2223216-20

Figure 3-8

controller Operational

3-43

Floy~hart

TECHNICAL REFERENCE

3.6.6

HARDWARE OPTIONS

Detailed Description of Commands

The commands fall into eight classes -- 0 through 7;
however,
only
classes 0 and 7 are used.
Classes 1 through 6 are reserved.
Class 0
commands are data, non~data transfer, and status commands.
Class 7
commands perform diagnostics.
Each command is described in the following paragraphs.
The command
description
includes class,
opcode, and format.
"Don't care" bits
are shown as "unused."
3.6.6.1 TEST DRIVE READY Command.
This command selects a particular
drive and verifies that the drive is ready.
The following diagram
shows the for.mat of the d_evice control block for this command:
B

Y
t

+------~----------------Bit

Humber----------------------+

e'
+-V-+======+======+======+======+======+======+======+======+
7

6

5

4

321

0

o
o
o
o
o
o r 0
o
o
+---+------+------+------+------+------+------+------+------+
1
o
o I DRIVElunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
2 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+~-----+------+------+------+

3 lunusedlunusedJunusedJunusedJunusedlunusedlunu~edlunusedl
+---+------+------+------+------+------+------+------+------+
4 lunusedlunusedlunusedlunusedlunusedlunusedlunusedJunusedl
+---+------+------+------+------+------+------+------+-----~+

I 5 lunusedlunusedlunusedlunusedlunusedlunusedJunusedlunusedl
+---+------+------+------+------+------+------+------+---~--+

To determine
that
a drive has completed seeking before issuing the
next command, use the TEST DRIVE READY command with overla~ped seeks.
(Refer to the paragraph entitled "SEEK Command" in th.is section.)
If
the drive is still seeking, the end-of-command status byte
indicates
an error, and the sense status indicates "drive still seeking." This
is a
type 0 error,
code 9.
Sequential TEST DRIVE READY commands
determine when the drive is ready to accept another command.

3-44

HARDHARE OPTIOHS

TECHNICAL REFERENCE

3.6.6.2
RECALIBRATE DRIVE Command.
This
command
places
the
read/write
(R/H) arm at track 000.
Bit definitions for this command
are as follows:
B

Y +-----------------------BIT HUMBER----------------------+
t
7
I Bit 61 Bit 51 Bit 41 Bit 31 Bit 21 Bit 11 Bit 01

+-e-+======+======+======+======+======+======+======+======+
o
o
o
1
o
o
o
o
1 0 I
+---+------+------+------+------+------+------+------+------+
o 1 DRIVElunusedlunusedlunusedJunusedlunusedl
o
1.1
+---+------+------+------+------+------+------+------+------+
1 2 lunusedJunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+----~-+------+------+------+------+

+1 - 3__ +lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
____-__ + __
+ _______ + ______ + ____
+ ______ + ______ + ______ +
0 __

I

4

-

_

0 __

lunusedlun~sedlunusedlunusedlunusedlunusedlunusedlunusedJ

+---+------+------+------+------+------+------+------+------+
o
o
o /STEP 31STEP 2/STEP l/STEP 01
1 5 /RETRY?/
+---+------+------+------+------+------+------+------+------+
3.6.6.3 REQUEST SE,lfSE o$TATUS Command.
The compu ter
sends
thi s
command
immediately after it detects an error.
The controller then
returns 4 bytes of drive and the controller status.
The formats
for
these
4
bytes are shown after the DCB.
Definitions of these bytes
follow.
/
B

Y +-----------------------BIT NUMBER----------------------+
t 1
7
/ Bit 61 Bit 51 Bit 41 Bit 31 Bit 21 Bit 11 Bit 01
+-e-+======+======+======+======+======+======+======+===~==+

/

0

I

o

o

o

o

o

o

1

1

+---+------+------+------+------+------+------+------+------+
o
o / DRIVElunusedlunused/unusedlunusedlunusedl
1 1 1
+---+------+------+------+------+------+------+------+------+
1 2 lunusedlunused/unusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 3 lunusedlunusedlunusedlunusedlunusedlunusedlunused/unusedl
+---+------+------+------+------+------+------+------+------+
1 4 lunusedlunusedlunusedlunusedlunused/unusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 5 lunused/unused/unusedlunused/unused/unused/unused/unusedl
+---+------+------+------+------+------+------+------+------+
Bit 7, the address valid bit in the error code byte, is relevant only
when the previous command required a logical block address.
In
this
case,
it
is always returned as a 1; otherwise, it is set to O.
For
instance, assume that a RECALIBRATE command is
followed
immediately
by a
REQUEST SEHSE STATUS command.
The address valid bit could be
returned as 0 because the command does not require a
logical block
address to be passed in its DCB.

3-45

TECHNICAL REFERENCE

HARDWARE OPTIONS

The format for the sense bytes returned is as follovs:
B

Y +---------------------------BIT NUMBER---------------------------+

tl

7

I

6

I

5

I

1:3

4

I

2

I

1

101

+-e-+========+=======+=======+=======+=======+=======+=======+=======+
I 0 IADDRESS?I o
ERROR TYPE
ERROR CODE
+---+--------+-------+-------+-------+-------+-------+-------+-------+
o
o
HIGH ADDRESS (see Hote)
IDRIVE
I 1 I
+---+--------+-------+-------+-------+-------+-------+-------+-------+
MIDDLE ADDRESS (see Hote)
I 2 I
+---+--------+-------+-------+-------+-------+-------+-------+-------+
LOW ADDRESS (see Hote)
I :3 I
+---+--------+-------+-------+-------+-------+-------+-------+-------+
HOTE: Refer to paragraph :3.6.1.6.
When an error occurs on a multiple-sector data transfer (read or
vrite), the REQUEST SENSE STATUS command returns the logical address
of
the failing
sector
in bytes 1, 2, and:3.
If the REQUEST SEHSE
the format
commands or
the
STATUS command is issued after any of
CHECK TRACK FORMAT command,
and
if no error exists, the logical
address returned by' the controller pOints to one sector beyond
the
last track formatted or checked.
If an error does exist, the logical
address
returned points to the track in error.
Table :3-21, Table :322, and Table :3-2:3 list the types 0, 1, 2, and :3 error codes.
Table
:3-24 summarizes the error codes returned by. the REQUEST SEHSE STATUS
command.

Table 3-21
Code

Type 0 Error Codes, Wirichesfer Disk
Definition

OH

The controller detected no error during the execution
of the previous operation.

1H

The controller did not detect
drive.

2H

The controller did not get a SEEK COMPLETE
the drive after seek operation.

:3H

The controller detected a write fault from drive during
last operation.

4H

After the controller selected the drive,
not respond with READY signal.

5H

Not used.

6H

After stepping maximum number of cylinders, controller
did not receive track 00 signal from the drive.

~n

:3-46

index signal from the
~ignal

from

the drive did

TECHNICAL REFERENCE

Table 3-22

Hex
Code

HARDWARE OPTIONS

Type 1 Error Codes, Controller Board

Message

Definition

OH

ID Read
Error

The controller detected an ECC error in
the target ID field on the disk.

1H

Data
Error

The controller detected an uncorrectable
ECC error in the target sector
during a read operation.

2H

·Address
Mark

The controller did not detect the target
address mark (AM) on the disk.

3H

Hot used.

4H

Sector Hot
Found

The controller found the correct cylinder
and head, but not the target sector.

SH

Seek
Error

The controller detected an incorrect
cylinder or track, or both.

6H

Hot used.

7H

Hot used.

8H

Correctable
Data Error

The controller detected a correctable
ECC error in the target data field.

9H

Bad Track

The controller detected the bad track
flag during the last operation.

AH

Format Error

During a CHECK TRACK FORMAT command, the
controller detected one of the folloving:
* Track not formatted
* Wrong interleave
* ID ECC error on at least one sector

3-47

TECHNICAL REFERENCE

Table 3-23

HARDWARE OPTIONS

Types 2 and 3 Error Codes, Command and Miscellaneous

Code

Type

Message

Definition

OH

2

Invalid
Command

The controller received an
invalid command from the host.

1H

2

Illegal Disk
Address

The controller detected an
address beyond the maximum range.

OH

3

RAM Error

The controller detected a data
error during the RAM sector
buffer diagnostic.

1H

3

Program Memory
Checksum Error

During its internal diagnostics,
the controller detected a program
memory checksum error.

2H

3

ECC Polynominal
Error

During the controller's internal
diagnostics, the hardware ECC
generator failed its test.

3-48

HARDWARE OPTIONS

TECHNICAL REFERENCE

Table 3-24
Error Code

Error Code Summary

Meaning

OOH

Ho error detected (command completed OK).

01H

No index detected from disk drive.

02H

Ho seek complete from disk drive.

03H

Write fault from disk drive.

04H

Drive not ready after it vas selected.

----------~-------------------------------------------------------

OSH

Not used.

06H

Track

07H-OFH

Not used.

10H

ID field read error.

11H

Uncorrectable data error.

12H

Address mark not found.

13H

Hot used.

14H

Target sector not found.

00

not found.

.
.
~~------------------------------------------~-----~--- -------------

15H

Seek error.

16H-17H

Hot used.

18H

Correctable data error.

19H

Sad track flag detected.

lAH

Format error.

lBH

Not used.

------------------------------------------------------------------lCH

Illegal (direct) access to an alternate track.

-------------------------------------------------------------------

3-49

TECHNICAL REFERENCE

Table 3-24
Error Code

HARDWARE OPTIONS

Error Code Summary (Concluded)

Meaning

IDH

On a FORMAT ALTERNATE TRACK command, the track
is already assigned or is flagged as a bad track.

lEH

When the controller attempted to access an
alternate track from a spared track, the
alternate track vas not flagged as an alternate.

IFH

On a FORMAT ALTERNATE TRACK command, the
bad track equaled the alternate track.

~-------------------------------------------~---------------------~

20H

Invalid command.

21H

Illegal disk address.

22H-2FH

Not used.

30H

Ram diagnostlc failure.

31H

Program memory checksum error.

32H

ECC diagnostic failure.

33H-3FH

Mot used.

Note:

The Address Valid bit
not included here.

(bit 7) mayor may not be set and is

3-50

HARDWARE OPTIONS

TECHNICAL REFERENCE

3.S.S.4 FORMAT DRIVE Command.
This
command uses
the
selected
interleave factor
to
format all sectors having 10 and data fields,
and writes SCH into data fields.
The
controller formats
from
the
starting address,
which is passed in the command, to the end of the
disk.
Setting bit 5 (from control byte 5 of the command block)
with
the
FORMAT DRIVE command causes the sector buffer to be used as the data
pattern written on the disk data fields.
To initialize the
sector buffer,
issue
the WRITE SECTOR BUFFER
command before
the FORMAT DRIVE command.
Byte definitions are as
follows:

B

y+-------+-------+-B
I T MUM
BE3 R-+-------+-------+-------+
tl
7
,
6
,
5
4
2
0
+e+=======+=======+=======+=======+=======+=======+=======+=======+
o
o
o
o
o
o
o
101
+-+-------+-------+-------+-------+-------+---------+-----+-------+
o
HIGH ADDRESS
( Mote
)1
o
.J
III
+-+-------+-------+-------+-------+-------+-------+-------+-------+
MIDDLE ADDRESS
( Mote
)1
121
+-+-------+-------+-------+-------+-------+-------+-------+-------+
LOW ADDRESS
( Hote
)1
131
+-+-------+-------+-------+-------+-------+-------+-------+-------+
o
o
IMTERLEAVE FACTOR
o
( Mote 2 )1
14'
+-+-------+-------+-------+-------+-------+-------+-------+-------+
151 RETRY?,
o
o
, STEP 31 STEP 21 STEP
STEP 01
I. o
~

~

IDR~VE

~
~

~

~I

+-+-------+-------+-------+-------+-------+-------+~------+-------+

Hotes:
~. Refer to paragraph 3.6.1.S.
2. Factor is number of sectors per track minus one.

3-5~

TECHNICAL REFERENCE

HARDWARE OPTIONS

3.6.6.5
CHECK TRACK FORMAT Command.
This command checks the format
on
the spec"ified
track for correct 10 and interleave.
The command
does not read the data field.
The byte configuration is as follows:

B

y+-------+-------+-B I T
HUM B E R -+-------+-------+-------+
t 1
7
I
615
4
1 312
1 1
I
0
I
+e+=======+=======+=======+=======+=======+=======+=======+=======+
o
o
o
o
o
1
1
o
I0 f
+-+-------+-------+-------+-------+--------+--------+-----+-------+
o
o
HIGH ADDRESS (See note 1)1
IDRIVE
III
+-+-------+-------+-------+-------+-------+-------+-------+-------+
HIDDLE ADDRESS
(See note 1)
121
+-+-------+-------+-------+-------+-------+-------+-------+-------+
LOW ADDRESS
(See note 1)
131
+-+-------+-------+-------+-------+-------+-------+-------+-------+
o
o
o
IHTERLEAVE FACTOR (See note 2)
141
+-+-------+-------+-------+-------+-------+-------+-------+-------+
o
o
o
I STEP 31 STEP 21 STEP 11 STEP 01
151 RETRY? 1
+-+-------+-------+-------+-------+-------+-------+-------+-------+
Hotes:
1. Refer to paragraph 3.6.1.6.
2. Factor is number of sectors per track minus one.

3-52

HARDW~RE

TECHNICAL REFERENCE

OPTIONS

3.6.6.6 FORMAT TRACK Command.
The FORMAT TRACK command
reformats
the
track,
eliminating all references to bad and alternate tracks.
Setting bit 5 from control byte 5 of the
command block causes
the
sector buffer
to be used as. the data pattern in the data fields.
Otherwise, the command writes 6CH
in
the data fields.
The byte
definitions are as follows:

B

y+-------+-------+-B I T N U MB E R -+-------+-------+-------+
t I
7
I
6
I
5
4
I
3
I
2
I
1
101
+e+=======+=======+=======+=======+=======+=======+=======+=======+
1
o
o
o
o
o
1
o
I0 J
+-+-------+-------+-------+-------+-------+---------+-----+-------+
HIGH ADDRESS (See note 1)
o
o
IDRIVE
III
+-+-------+-------+-------+-------+-------+-------+-------+-------+
MIDDLE ADDRESS
(See note 1)
121
+-+-------+-------+-------+-------+-------+-------+-------+-------+
LON ADDRESS
(See note 1)
131
+-+-------+-------+-------+-------+-------+-------+-------+-------+
o
o
o
INTERLEAVE FACTOR
(See note 2)
141
+-+-------+-------+-------+-------+-------+-------+-------+-------+
o
o
151 RETRY? I
o
I STEP 31 STEP 21 STEP 11 STEP 01
+-+-------+-------+-------+-------+-------+-------+-------+-------+

Notes:
1. Refer to paragraph 3.6.1.6.
2. Factor is number of sectors per track minus one.

3-53

TECHNICAL REFERENCE

HARDWARE OPTIONS

3.6.6.7
FORMAT BAD TRACK Command.
This command formats a speeified
track, setting the bad sector flag in the 10 fields.
No data fields
are written.
The byte definitions are as follows:
B

y+-------+-------+-B
I T N4 U K I B E 3 R -+-------+-------+-------+
2
1
o
t I
7
I
6
I
5
+e+=======+=======+=======+=======+=======+=======+=======+=======+
o
o
o
o
1
1
o
1
101
+-+-------+-------+-------+-------+-------+---------+-----+-------+
o
HIGH ADDRESS
(See note 1)
o
IDRIVE
111
+-+-------+-------+-------+-------+-------+-------+-------+-------+
KIDDLE ADDRESS
(S·ee note 1)
+-+-------+-------+-------+-------+-------+-------+-------+-------+
LOW ADDRESS
(See note 1)
+-+-------+----~--+-------+-------+-------+-------+-------+-------+

141

o

o

o

INTERLEAVE FACTOR

(See note 2)

+-+----~~-+-------+-------+-------+-------+-------+-------+-------+

151 RETRY? I

o

o

o

I STEP 31 STEP 21 STEP 11 STEP 01

+-+-------+-------+-------+-------+-------+-------+-------+-------+
NOTES:
1. Refer

to paragraph 3.6.1.6.
2. Factor is number of sectors per track minus one.

3-54

HARDWARE OPTIONS

TECHNICAL REFERENCE

READ Command.
Starting with the sector address given in
specified number of sectors.
this command, the controller reads a
The byte definitions are as follows:
3.6.6.9

B

y+-------+-------+-B
I T N4 UMI BE3 R -+-------+-------+-------+
tl
7
I
6
I
5
I
2
I
1
101
+e+=======+=======+=======+=======+=======+=======+=======+=======+
o
a
o
a
1
a
a
a
101
+-+-------+-------+-------+-------+-------+---------+-----+-------+
a
(See note 1)
a
IDRIVE
HIGH ADDRESS
+-+-------+-------+-------+-------+-------+-------+-------+-------+
MIDDLE ADDRESS
(See note 1)
121
+-+-------+-------+-------+-------+-------+-------+-------+-------+
LOW ADDRESS
note 1)
+-+-------+-------+-------+-------+-------+-------+-------+-------+
BLOCK COUNT
+-+-------+-------+-------+-------+-------+-------+-------+-------+
a
o
151 RETRY?, Kote 21
I STEP 31 STEP 21 STEP 11 STEP 0/
+-+-------+-------+-------+-------+-------+-------+-------+-------+
Kotes:
(S~e

1. Refer

to paragraph 3.6.1.6.
2. If this bit is set in the READ command and an ECC error is
found, retry t~e command.
WRITE Command.
This command writes the specified number of
starting with the initial sector address contained in the
Byte definitions are as follows:

3.6.6.9

sectors~

DCB.
B

y+-------+-------+-B
I T N4U1
M-BE3 R -+-------+-------+-------+
tl
7
f
6
,
5
2
1
0
+e+=======+=======+=======+=======+=======+=======+=======+=======+
o
o
o
o
1
a
i
101
o
.1
+-+-------+-------+-------+-------+-------+---------+-----+-------+
a
IDRIVE
HIGH ADDRESS
J11
(See note)1
.-+-------+-------+-------+-------+-------+-------+-------+-------+
KIDDLE'ADDRESS
(See note)
12 t
+-+----- -+-------+-------+-------+-- - - - - - - +-------+' -------+.-------+
,

t3 1

LOW ADDRESS

,

(Sae note)

+-+-------+-------+-------+-------+-------+--~----+-------+-------+

BLOCK COUNT

+-+-------+-------+-------+--_._--+-------+-------+-------+-------+
o
151 RETRY?,
o
o
, STEP 31 STEP 21 STEP 11 STEP 01
+-+-------+-------+-------+-------+-------+-------+------~+-------+

Hote:

Refer to paragraph 3.6.1.6.

3-55

HARDWARE OPTIONS

TECHNICAL REFERENCE

/-

3.6.6.10
SEEK Command.
This command initiates a seek to the trac:
specified in the DCB.
The drive must be formatted.
The byte
definitions are as follows:
B

y+-------+-------+-B
I T NUKBE R -+-------+-------+-------+
t I
I
I
4
I
3
I
2
1
101
+e+=======+=======+=======+=======+=======+=======+=======+=======+
1
o
o
o
o
1
o
1
101
+-+-------+-------+-------+-------+-------+---------+-----+-------+
o
o
HIGH ADDRESS
(See note)1
IDRIVE
III
+-+-------+-------+-------+-------+-------+-------+-------+-------+
MIDDLE ADDRESS
(See note)
121
+-+-------+-------+-------+-------+-------+-------+-------+-------+
LOW ADDRESS
(See note)
131
+-+-------+-------+-------+-------+-------+-------+-------+-------+
U NUS E D
J 41
7

6

5

+-+-------+-~-----+-------+-------+-------+-------+-------+-------+

151 RETRY? I

o

o

o

f STEP 31 STEP 21 STEP 11 STEP 01

+-+-------+-------+-------+-------+-------+-------+-------+-------+
Note: Refer to paragraph .3.6.1.6.
For drives using buffered seeks, SEEK commands can be overlapped.
After the controller issues a SEEK to the drive, it does not wait for
the drive to complete the SEEK, but returns a completion status.
If
the return status shows no error, then ·the SEEK was issued correctly~
If
there
is an error,
then
the SEEK was not
issued.
After
transferring the status, another command can be
issued
to either
drive.
If a drive with an outstanding SEEK receives a new command,
the controller waits (holding BUSY active) until_the SEEK completes
before executing
the new command.
(See the section entitled "TEST
DRIVE READY Command" for a
special case.)
There is no
time-out
condition
in
the controller waiting for the buffer~d-step SEEK to
complete.

.... ";'

3-56

HARDWARE OPTIONS .

TECHNICAL REFERENCE.

INITIALIZE DRIVE CHARACTERISTICS Command.
This
command
enables
the controller
to work with drives
that have different
capacities and characteristics.
However, both Winchester drives must
be of the same manufacturer and model number.
3.6.6.~~

i t
After the computer sends the command
(DCB)
to
the controller,
sends an 9-byte block of data containing the drive parameters.
Some
of
the parameters occupy 2 bytes;
all 2-byte parameters
are
transferred with the most significant byte (MSB) first.
The 9 bytes
are:

e = Maximum number of cylinders (2 bytes)
E = Maximum Eee data burst length (~ byte)
H _=:=_.~~x.i.mum numbt:!: of heads (~ byte)
P = Starting write precompensation cylinder (2 bytes)
W = Starting reduced write current cylinder (2 bytes)
When the controller is powered up or reset,
values are set:

the following default

Maximum number of cylinders (e)= ~53
Maximum Eee data burst length (E)= ~~ bits
Maximum number of heads (H)= 4
Starting write precompensation cylinder (P)=64
Starting reduced write current cylinder (W)= 129
The parameter for the maximum Eee burst length defines the length of
a
burst
error
in the data field that the controller is to correct.
The burst length is defined as the number of bits from
the first
error bit
to
the last error bit.
For example, if the controller
detects as-bit Eee error and
the erroneous data appears
(before
correction) as e5
(1~00
010~),
it could appear" as D~ (1101 O~OO)
after the correction.
However, if the epu has set
the "maximum Eee
burst
length at
4 bits,
the controller might flag this data as
uncorrectable.
This is a type ~, code 1 error.

3-57

TECHNICAL REFERENCE

HARDWARE OPTIONS

Byte definitions for the INITIALIZE DRIVE CHARACTERISTICS command are.
as follows:
B

Y
t +-----------------------BIT NUMBER----------------------+
e 1 7 I Bit 61 Bit 51 Bit 41 Bit 31 Bit 21 Bit 11 Bit 01

+-V-+======+======+======+======+======+======+======+ ======+
I

o

I

0

o

o

o

1

o

1

o

+---+------+------+------+------+------+------+------+------+
I 1 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 2 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 3 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+--~-~-+------+--~---+------+------+------+------+------+

I 4 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 5 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
the drive parameter bytes
Byte definitions -for
(passed
to
the
controller after
the
INITIALIZE DRIVE CHARACTERISTICS command has
been issued) are as follows:

B

y+-------+-------+-B I T
t

I

7

I

6

J

5

N U M B E R
4

I

3

-+-------+-------+-------~

I

2

1

1

1

0

!

+e+=======+=======+=======+=======+=======+:======+=======+=======+

MAXIMUM NUMBER OF CYLINDERS: MSB
101
+-+-------+-------+-------+-------+-------+-------+-------+-------+
MAXIMUM NUMBER OF CYLINDERS: LSB
III
+-+-------+-------+-------+-------+-------+-------+-~-----+-------+

o
o
o
o
1 MAXIMUM NUMBER OF HEADS
J 21
+-+-------+-------+-------+-------+-------+-------+-------+-------+
STARTING REDUCED WRITE CURRENT CYLINDER:
MSB
131
+-+-------+-------+-------+-------+---_:_-+-------+---~---+-------+

STARTING REDUCED WRITE CURRENT CYLINDER:
LSB
141
+-+-------+-------+-------+-------+-------+-------+-------+-------+
STARTING WRITE PRECOMPENSATION CYLIND~R:
MSB
151
+-+-------+-------+-------+-------+-------+-------+-------+-------+
STARTING WRITE PRECOMPENSATIOK CYLINDER:
LSB
+-+-------+-------+-------+-------+-------+-------+-------+-------+
o
o
o
o
I MAXIMUM ECC DATA BURST LENGTH I
J 71
+-+-------+-------+-------+-------+-------+-------+-------+-------+

3-58

HARDWARE OPTIONS

TECHNICAL REFERENCE

READ
ECC
BURST ERROR LENGTH Command.
This
command
transfers 1 byte to the CPU.
This byte contains the value of the ECC
burst
length
that
the
controller
detected
during
the last READ
command.
This byte is valid only after a correctable ECC data error,
type 1, code 8.
Byte definitions are as follovs:
3.6.6.12

B

Y

t +-----------------------BIT HUMBER-~--------------------+
e 1
7
1 Bit 61 Bit 51 Bit 41 Bit 31 Bit 21 Bit 11 Bit 01

+-v-+======+======+======+======+======+======+======+======+
o
o
1
o
1
o
o
1
I 0
+---+------+------+------+------+------+------+------+------+
1 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedJ
+---+------+------+------+------+------+------+------+------+
1 2 lunusedJunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
3 lunusedJunusedfunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I

4

lunused/unusedlunusedlunusedlunusedlunusedlunusedlunusedl

+---+------+---~--+-~----+------+------+------+------+------+

I 5 lunusedlunusedlunusedlunusedlunusedlunusedJunusedlunusedl

+---+------+------+------+------+------+------+------+------+

3-59

TECHNICAL REFERENCE

HARDWARE OPTIONS

3.6.6.13 FORMAT ALTERNATE TRACK Command.
The FORMAT ALTERNATE TRACK
command formats the header
fields
of
the
ubad
track u vith
the
alternate
track
information
(assigned by the CPU).
The alternate
track is formatted to identify it as an alternate.
The command byte
definitions for FORMAT ALTERNATE TRACK are as follovs:
B

y+-------+-------+-B I T N U M B E R -+-------+-------+-------+
t I
7
161
5
4
I
3
2
1
0
I
+e+=======+=======+=======+=======+=======+=======+=======+=======+
o
o
o
o
1
1
o
1
101
+-+-------+-------+-------+-------+-------+-------+-------+-------+
o
o
HIGH ADDRESS
( Note 1 )1
IDRIVE
III
+-+-------+-------+-------+-------+-------+-------+-------+-------+
--MIDDLE ADDRESS
( Note 1 )1
+-+-------+-------+-------+-------+-------+-------+-------+-------+
.

LOW ADDRESS

( Note 1

)1

+-+-----~-+-------+-------+-------+-------+-------+-------+-------+

141

o

o

o

INTERLEAVE FACTOR

( Note 2 )1

+-+-------+-------+-------+-------+-------+-------+-------+-------+
o . . 1 (No t e 3)
o
I STEP 31 STEP 21 STEP 11 STEP 01
151 RETRY? I
+-+-------+-------+-------+-------+-------+-------+-------+-------+

Notes:

1. Refer

to paragraph 3.6.1.6.

2. Factor is number of sectors per track minus one.
3. If this bit is set, the data in the existing sector buffer
is used to fill the data field. If this bit is cleared,
the data field is vritten vith 6CM.
The
interleave byte
(4)
is programmed
the same as in the FORMAT
command, and is used on the alternate track.
If bit 5 of the control
byte (5) is set, the data in the existing sector buffer is vritten to
the data field.
If not, the data field is vritten vith 6Ca.
After issuing the command,
the controller
These
3
Alternate Address
data block.
Again
assigned alternate logical address.
ignored.

3-60

for
the Assigned
asks
bytes point to the CPUsector address
is
the

HARDWARE OPTIONS

TECHNICAL REFERENCE

The
byte definitions
are as follovs:

for

the Assigned Alternate Address Data Block

B

-+-------+-------+-------+
2
1
101
+e+=======+=======+=======+=======+=======+=======+=======+=======+
o
o
HIGH ADDRESS
o
(See note)
101
+-+-------+-------+-------+-------+-------+-------+-------+-------+
MIDDLE ADDRESS
(See note)
III
+-+-------+-------+-------+-------+-------+-------+-------+-------+
LOW ADDRESS
(See note)
121
+-+-------+-------+-------+-------+-------+-------+-------+-------+
y+-------+-------~-B

t

I

7

161

I T

5

N U M B E R
4
3

Note: Refer to paragraph 3.6.1.6.
3.6.7

Alternate Track Assignment

The computer both assigns alternate tracks and locks out bad
tracks.
Bad areas
on
the disk are
labeled defective on a track basis by
issuing a FORMAT BAD TRACK command (command code 07).
One procedure
for assignment and-handling of alternate tracks is given belovo
1. Give the FORMAT DISK command
(command code
04).
This
formats
the
entire disk drive starting at logical track
000.
a.

If any errors occur, give the
command.

REQUEST

SENSE

STATUS

b.

If a format error is indicated, bytes 1, 2, and 3 of
the
returned
status give
the address
of the bad
track.

c. Give a FORMAT BAD TRACK command (command code 07)
the track.

to

d. Reissue the FORMAT DISK command.
e.

If any other errors
occur during
the
subsequent
formatting,
reissue the REQUEST SENSE STATUS, FORMAT
BAD TRACK, and FORMAT DISK commands until the entire
disk is formatted.

2. Give the RECALIBRATE command (command code 01)
the heads over track 000.

to

position

All
sectors
on
the disk are read to see if any uncorrectable ECC
errors occurred in the data.
The FORMAT command places a 6CH pattern
in the data fields of all
sectors,
and
the
computer program can
verify
this
data pattern after
the
data
is
read
into memory.
Hovever, verifying the data byte for byte is not
usually necessary,
because
the
error detection and
correction circuitry flags all

TECHNICAL REFERENCE

HARDWARE OPTIONS

uncorrectable errors.
If a large block of host memory is available,
multiple sector reads can be issued to speed up the verify process.
When an
uncorrectable
error
is
found, issuing a FORMAT BAD TRACK
command (command code 07) to the failing track writes a
bad
track
flag
into all
identifier fields.
Later accessing of this track
results in an error, causing the sense status that follows to show an
error code ISH.

NOTE
Whenever a user program accesses
the disk,
be
sure that the operating system does not allow the
program
to
is-sue a READ or WRITE command to the
alternate tracks.

The disk controller has no way of knowing when an alternate track
is
being read.
The alternate tracks are sometimes assigned at the ~nd
of the disk (highest track numbers), but they can be assigned to any
tracks
so long as
the
track label is maintained by the computer.
Given the error correction capability of the controller, four
tracks
reserved as alternates
should be adequate for
all disk drives
currently available.
However, the system programmer
should consult
the disk drive manual for the hard-defect specifications.
3.6.8

Alternate Address Protocol

After receiving
the FORMAT ALTERNATE TRACK command and the assigned
alternate, the controller performs the following steps:
1. Seeks to the "alternate assigned track" and verifies
that
it
is not already an assigned alternate or a fla~ged bad
track.
NOTE
If the track has already been assigned as an
alternate
or
is
flagged "bad", then error code
lDH is given and the command
is aborted.
This
usually
implies
that the computer is attempting
to assign two bad tracks to
the
same alternate
track.

2. Formats the track as an assigned alternate track.
3. Seeks to the bad track and formats
3-62

the header

as

a

spare

HARDWARE OPTIONS

TECHNICAL REFERENCE

track pointing to the assigned alternate.
4. Destroys data fields on both the bad
track.
The
procedure
folloys:
1. Format

for

using

the

the entire disk,

track

and

alternate

FORMAT ALTERNATE TRACK command is as
including spare tracks.

2. Verify the disk.
3.

Assign each media defect an alternate track.

4. A s s-i-g n . a 1 t ern ate t-r a c k s
list.

for

drive

manufacturer's

defect

The
controller automatically
seeks to the assigned alternate track
yhen an access is made to a
flagged
defective
track.
Consecutive
accessing does
not result in reseeking to the alternate track.
The
controller maintains position on the alternate track.

NOTE

When using the FORMAT ALTERNATE TRACK command, be
sure
to
include
(in
the
controller
initialization)
cylinder and head ranges for the
alternate tracks.

Generally, the actual disk space is greater than the amount fixed
by
the
system
softvare.
This
extra
space can be used for alternate
tracks as needed.
The alternate tracks are invisible to the host.
The number of spare tracks depends on the drive
of
defects alloyed by the drive manufacturer.
track is allotted for each 50 to 100 tracks.

and
the
number
Generally, one spare

si~e

Direct access (attempted data transfers or
seeks)
to an alternate
track results in an error code lCH, and no transfer takes place.

3-63

TECHNICAL REFERENCE

3.6.9

HARDWARE OPTIONS

WRITE SECTOR BUFFER Command

This command is used t~ fill the sector buffer vith a host-given data
pat tern.
No data is transfered betveen the drive and the controller.
The
command accepts 512 bytes of data and stores them in the sector
buffer.
The byte definitions are as follovs:
B

Y

t +-----------------------BIT HUMBER----------------------+
e I
7
I Bit 61 Bit 51 Bit 4! Bit 31 Bit 21 Bit 11 Bit 01

+-v-+======+======+======+======+======+======+======+======+
I

0

I

o

o

o

o

1

1

1

1

+---+------+------+------+------+------+------+------+------+
I 1 lunusedlunusedlunusedJunusedlunusedJunusedlunusedlunusedj
+---+------+------+------+------+------+------+------+------+
I 2 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedt
+---+------+------+------+------+------+------+------+------+
I 3 lunusedlunusedlunusedlunusedlunusedlunused!unusedlunusedl
+---+------+------~------+------+------+------+------+------+

I 4 JunusedlunusedJunusedJunusedJunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 5 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedt
+---+------+------+------+------+------+------+------+------+

3.6.10

READ SECTOR BUFFER Command

This command sends 512 bytes of data from the sector
CPU.
The byte definitions are as follovs:

buffer

B

Y

t +- -- - --- - -- ---------- - - -BIT NUMBER-----:: -.--- - ----:- - ~ --:_- - +
e I
7
I Bit 61 Bi·t 51 Bit 41 Bit 31 Bit 21 Bit 11 Bit 01

+-v-+======+======+======+======+======+======+======+======+

o
o
o
o
o
o
o
1
1 0 I
+---+------+------+------+------+------+------+------+------+
I 1 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 2 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 3 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 4 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 5 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+

3-64

to

the

HARDWARE OPTIONS

TECHNICAL REFERENCE

3.6.11

RAM DIAGNOSTICS Command

This
command
performs
a
data pattern test on the RAM buffer.
byte definitions are as follows:

The

B

Y

t +-----------------------BIT NUMBER----------------------+
e I
1
I Bit 61 Bit 51 Bit 41 Bit 31 Bit 21 Bit 11 Bit 01
+-V-+======+======+======+======+======+======+======+======+

o

1

1

1

o

o

o

o

o

+---+------+------+------+------+------+------+------+------+
1

lunu~edlunusedlunus~dlunusedlunusedlunusedlunusedlunusedt

+ - - -+ - - - -:; - .. - -'---- + - - - - --- + - --- -- + --- - - - + - - - - -- + - - - -- - + -- -- - - +
2 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedt
+---+------+------+------+------+------+------+------+------+
3 lunusedlunusedlunusedlunusedlunused/unusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
4 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------~------+------+------+------+------+------+

5 lunusedlunusedlunusedlunused\unusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+

,(

3.6.12

DRIVE DIAGNOSTICS Command

This
command
tests
both
the
drive
and
the
drive-to-controller
interface.
The controller sends RECALIBRATE and SEEK commands to the
selected drive and verifies sector 0 of all the tracks on the disk.
The controller does not
perform any write
operations
during
the
command; it assumes the disk has been previously formatted.
The byte
definitions for the command are as follows:
B

Y

t +-----------------------BIT NUMBER----------------------+
e I
1
I Bit 61 Bit 51 Bit 4/ Bit 3/ Bit 21 Bit 11 Bit 01
+-V-+======+======+======+======+======+======+======+======+

o

1

1

1

o

0,

o

1

1

+---+------+------+------+------+------+------+------+------+
1 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
2 lunusedlunused/unusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
3 lunusedlunusedlunused/unusedlunusedlunusedlunuaedlunusedl
+---+------+------+------+------+------+------+------+------+
4 lunuaed/unused/unusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
5 IRETRY?)
o
o
o
ISTEP 3/STEP 21STEP 1/STEP 01
+---+------+------+------+------+------+------+------+------+

3-65

TECHNICAL REFERENCE

3.6.~3

HARDWARE OPTIONS

CONTROLLER INTERNAL DIAGNOSTICS Command

This command causes
the
controller
to perform a self-test.
The
controller
checks
its
internal processor,
data
buffers,
ECC
circuitry,
and
the
checksum of the program memory.
The controller
does not access the disk drive.
The byte definitions are as follovs:
B
Y

t +-----------------------BIT NUMBER----------------------+
e J
7
J Bit 61 Bit 51 Bit 41 Bit 31 Bit 21 Bit 11 Bit 01

+-v-+======+======+======+======+======+======+======+======+
1
o
1
1
1
o
o
o
I 0 I
+---+----_-:.:.+.:. __._--+-----;;;;+------+--.. . ---+------+------+------+
I 1 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 2 lunusedlunusedJunused/unusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 3 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 4 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+---~--+------+------+------+------+

I 5 lunusedlunusedlunusedl·unusedlunusedlunusedlunusedlunusedl

+---+------+------+------+------+------+------+------+------+
3.6.14

READ LONG Command

This command transfers the target sector and 4 byt&s of data ECC
to
the CPU.
If an ECC error occurs during the read, the controller does
not
attempt
to correct the data field.
This command is useful for
recovering data from a sector vith an uncorrectable ECC eiror and for
diagnostic operations.
The byte definitions are as follovs:
B

. -y+-------+-------+-B I T N U M B E R -+-------+-------+-------+
1
o
2
4
I
3
t I
7
I
6
I
5
+e+=======+=======+=======+=======+=======+=======+=======+=======+
1
o
1
1
1
o
o
1
10 I
+-+-------+-------+-------+-------+-------+---------+-----+-------+
o
o
HIGH ADDRESS
IDRIVE
(See note)1
+-+-------+-------+-------+-------+-------+-------+-------+-------+
MIDDLE ADDRESS
(See note)
121
+-+-------+-------+-------+-------+-------+-------+-------+-------+
LOW ADDRESS
(See note)
+-+-------+-------+-------+-----~-+-------+-------+-------+-------+

141

BLOCK COUNT

(See note)

+-+-------+-------+-------+-------+-------+-------+-------+-------+
o
o
151 RETRY? I
o
I STEP 31 STEP 21 STEP 11 STEP 01
+-+-------+-------+-------+-------+-------+-------+-------+-------+
Note: Refer to paragraph 3.6.1.6.
3-66

HARDWARE OPTIONS

TECHHICAL REFEREHCE

3.6.15

WRITE LONG Command

This command transfers a sector of data and four appended ECC bytes
this write operation,
the computer
to
the disk drive.
During
of
using
the
hardware-generated
ECC
supplies the 4 ECC bytes instead
The
bytes.
This
command is useful only for diagnostic operations.
byte definitions are as follows:
B

B E R -+-------+-------+-------+
y+-------+-------+-B
I T HUM
2
1
o
t I
7
I
6
I
5
4
I
3
+e+=======+=======+=======+=======+=======+=======+=======+=======+
1
1
1
o
o
1
1
o
101

+ - + - - - - --.;;;"- +'- - - - - - - + - - - - - - - + - - - - - - - + - - - - - - - + - - - - - - - - - + - - - - - + - - - - - - - +

o

o

HIGH

IDRIVE

ADDRESS

(see Hote)1

+-+-------+-------+-------+-------+-------+-------+-------+-------+
MIDDLE ADDRESS
(see Note)1
121
+-+-------+-------+-------+-------+-------+-------+-------+-------+
LOW AI)DRESS
(see Note)1
+-+-------+---~-::+---~---+-------+-------+-------+-------+-----~-+

/41

BLOCK COUNT

+-+-------+-------+-------+-------+-------+-------+-------+-------+
o
o
o
151 RETRY? I
I STEP 31 STEP 21 STEP 1/ STEP 01
+-+-------+-------+-------+-------+--~----+-------+-------+-------+

Mote: Refer to paragraph 3.6.1.6.

3-67

TECHNICAL REFERENCE

3.6.16

HARDWARE OPTIONS

Execution Order of Remaining Diagnostics

Not all of the diagnostics are executed by the computer on power-up.
The remaining diagnostics should be called by
the CPU in the
following order.
1. CONTROLLER INTERNAL DIAGNOSTICS (command code E4).
This
command
tests
all
the
logical and decision-making
capabilities of
the controller,
the
program
memory
checksum,
and
the error detection and correction circuits
(ECC).
Executing
this diagnostic
ensures
that
the
controller can communicate with the computer.
--

-

2. RAM DIAGNOSTICS (command code EO).
This command verifies
that
the sector buffer is operational by writing, reading,
and verifying various data patterns
to and from all
locations.
3.

INITIALIZE DRIVE CHARACTERISTICS (command code OC).
This
command sends the new drive configuration to the controller
vhen the parameters of the connected drives differ from the
defaults. The INITIALIZE DRIVE CHARACTERISTICS command must
be issued before executing the DRIVE DIAGNOSTIC command.

4. TEST DRIVE READY (command code 00).
This command,
issued
before the DRIVE DIAGNOSTIC is executed, finds out when the
drive is ready to accept a command.
5. DRIVE DIAGNOSTIC (command code E3).
This command issues a
to
the disk drive and then steps though all
RECALISRATE
tracks, verifying the ECC on the identifier fields
of
the
first
sector of each track.
If this diagnostic passes, it
implies that the disk has been formatted and that the first
ID field of each track is good.

3.6.17

Error Correction Philosophy

The typical error-correction time of the controller is approximately
50 ms, vhich is greater than the time for one revolution of the disk.
The
sector
in error can be reread (if bit.6 is not set in byte 5 of
the READ command DCS) on the next revolution during a READ command,
In most cases, the error is soft and does not reappear on the rereaa,
This initial reread of the failing sector is in addition to the retry
count passed in the DCS (bit 7, byte 5).
The controller presets the error retry count to 4 each time a sector
is read successfully.
Sometimes, an error labeled uncorrectable
is
later found
to be correctable.
If this happens during a multiplesector transfer, the controller resets the retry count
to 4 before
another sector is read.
3-68

HARDWARE OPTIONS

TECHNICAL REFERENCE

3.6.19

Sector Field Description

Table 3-25 describes the sector information fields.

Table 3-25

Field
AM
GAP1
SYNC
GAP2
COM
CYLH
CYLL
HEAD
SEC
FLAG
ZEa
ECC
GAP3
SYNC2
GAP4
DATA
ECC2
GAPS

Number of
Bytes
4
-9
1

2
1
1
1

1
1
1
1

4
16
1

2
512
4
43

Sector Field Format
Field
Description
Address mark
Zero byte gap
10 sync byte
10 zero byte gap
10 compare byte
Cylinder high (MSB)
Cylinder 10"" (LSB)
Head number
Sector number
Flag byte
Zero byte
ID ECC bytes
Zero byte gap
Data field sync byte
Data field zero byte gap
Data field
Data field ECC bytes
Inter-record zero gap

Notes:
1. Cylinder (track) numbering is O-based.
2. Sector numbering is I-based.
3. Disk surfa~e numbering is O-based

The
track layout for the 512 bytes/sector, 17 sectors/track is given
in Table 3-26.

3-69

TECHHICAL REFEREHCE

HARDWARE OPTIOHS

Table 3-26

512-Bytes-Per-Sector Format

MSB
LSB
+------------------BIT HUMBER-------------------+
BYTE
I 7 I 6 I 5 f 4 f 3 f 2 I 1 1 0 J
========+=====+=====+=====+=====+=====+=====+=====+=====+
1-4
ADDRESS MARK
--------+-----+-----+-----+-----+-----+-----+-----+-----+
5-13
o
o
o
o
o
o
o
o
--------+-----+-----+-----+-----+-----+-----+-----+-----+
14
ID SYHC BYTE
--------+-----+-----+-----+-----+-----+-----+-----+-----+
15-16
o
o
o
o
o
o
o f 0
--------+-----+-----+-----+-----+-----+-----+-----+-----+
17 --IID -COMPARE BYTE
--------+-----+-----+-----+-----+-----+-----+-----+-----+
18
CYLIHDER HUMBER ( MSB )
--------,-----+-----+-----+-----+-----+-----+-----+-----+
19
CYLIHDER HUMBER ( LSB )
--------+-----+-----+-----+-----+-----+-----+-----+-----+
20
HEAD HUMBER
--------+--~--+-----+-----+-----+-----+-----+-----+-----+

21
SECTOR HUMBER
--------+-----+-----+-----+-----+-----+-----+-----+-----+
22
FLAG BYTE
--------+-----+-----+-----+-----+-----+-----+-----+-----+
o
o
o
23
o
o
o
o
o
--------+-----+-----+-----+-----+-----+-----+-----+-----+
ID ERROR CORRECTIOH CODE BYTES
24-27 I
--------+-----+-----+-----+-----+-----+--~--+---~--+-----+

o
o
o
o
o
o
o
28-43 I 0
--------+-----+-----+-----+-----+-----+-----+-----+-----+
44
DATA FIELD SYNC BYTE
--------+-----+-----+-----+-----+-----+-----+-----+-----+
o
o
o
o
o
o
o
45-46 1 0
--------+-----+-----+-----+-----+-----+-----+-----+-----+
512 BYTES DATA
47-558 f
--------+-----+-----+-----+-----+-----+-----+-----+-----+
DATA FIELD ERROR CORRECTION CODE BYTES
559-562 1
--------+-----+-----+-----+-----+-----+-----+-----+-----+
o
o
o
o
o
563-605 1 o
o
o
--------+-----+-----+-----+-----+-----+-----+-----+-----+
605 bytes/sector including ID and overhead
Track Capacity = 10416

--,

10285
+131

=
=

17 sectors of 605 bytes/sector
SpeeQ tolerance gap

10416

3-70

HARDWARE OPTIONS

TECHNICAL REFERENCE

3.6.19

Specification~

Table 3-27 gives

- Controller Board

the Winchester controller board specifications.

Table 3-27

Winchester Controller Board Specifications

Environmental Parameters:
Operating

Storage

~
~

Temperature

0

0

0

10 C to 40 C
0

(32 F

0

-10 C to 60 C
0

0

0

to 131 F)

(-40 F

to 167 F)

Relative Humidity
o
(0 40 F vet-bulb
temperature, no
condensation)

10'1. to 90'1.

10'1. to 90'1.

Altitude

Mean sea level
to 10 000 ft

Mean sea level
to 45 000 ft

Pover Requirements:
Voltage

Range

+5.0 Vdc

4.75

-12.0 Vdc

-10.8 to -13.2 Vdc

Current
to 5.25 Vdc

3-71

2.5 A maximum
2.0 A typical
66.0 mA maximum
48.0 mA typical

HARDWARE OPTIONS

TECHNICAL REFERENCE

3.6.20

Electrical Interface

This paragraph specifies the electrical
the 5 1/4-in Winchester disk drive.

interface

requirements

for

assemblies
All
Winchester
controller
boards
use
header
interchangeable with the AMP type 87215-7 for the
20-pin connectors
(to J2/P2),
and type 1-87215-7 for the 34-pin connector ( to Jl/P 1) .
for
these
Section 5 contains assembly drawings showing the pin-outs
connectors.
The connector layout is shown in Figure 3-9.

WINCHESTER
CONTROLLER
.' BOARD

AMP HEADER
ASSEMBLY
TYPE 87215-7
OR EQUIVALENT

WINCHESTER
DISK DRIVE
RIBBON CABLE TO
WINCHESTER DRIVE
AMP
RIBBON
CONNECTOR
TYPE 88373-6

.AMP
RECEPTACLE
CONNECTOR
TYPE 88377-4
OR EQUIV.

J2

P2

Jl

P1

OR EQUIV.

20-PIN RIBBON CABLE

RIBBON CABLE TO
WINCHESTER DRIVE

AMP HEADER
ASSEMBLY
TYPE 1-87215-7
OR EQUIVALENT

AMP
RIBBON
CONNECTOR
TYPE 88373-3
OR EQUIV.

AMP
RECEPTACLE
CONNECTOR
TYPE
88377-6
OR EQUIV.

34-PIN RIBBON CABLE

2223216-21

Figure 3-9

Control and Data Cabling for the Winchester Disk Drive

3-72

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

Section 4
DEVICE SERVICE ROUTINES

4.1

ROM INTERFACE INFORMATION

This
section provides
information
on
writing
software
for
compatibility with future
products and on interfacing with the
hardware of
the Texas - Instruments Professional Computer.
The
interface information includes interrupt vectors, system memory maps,
and ROM usage.
The system ROM contains instructions for hardware
device control of the standard I/O devices in the system unit.
The functions described are implemented with code in the system ROM,
and thus are available to all users of the system regardless of which
disk operating sy~tem (bOS) is installed.
However, the user must be
careful to avoid causing any conflicts with the operating system's
use of these same functions.
Typically,
these functions are accessed through the 9099 software
interrupt mechanism.
Each major device service ~outine
(DSR),
such
as keyboard,
display,
and disk,' has a unique vector.
Individual
functions of a DSR are accessed by placing an opcode in register AH
and executing an INT (interrupt) instruction of the appli,cable type.
To replace all or part of a DSR, just patch the interrupt
vector
to
point to the user-written code.
For specific
information on
the architecture
microprocessor, read
the
IAPX 99 Book or
the
Manual.

4.2

of
the Intel 9099
IAPX 96,99 User's

WRITING SOFTWARE FOR COMPATIBILITY KITH FUTURE PRODUCTS

The software you develop for this product undoubtedly represents a
large investment
of your
time and money.
Making changes and
releasing
new
versions
of software
is usually difficult and
expensive, and should be avoided.
This guide will help you to create
software that can be used with future Texas Instruments products.
4.2.1

Compatibility Levels

In order for the software to work on more than one hardware product,
compatibility must exist at some level:
either the operating system
level, the system ROM interface level,
or
the hardware
interface
level.

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

4.2.1.1 Operating System.
Software that interfaces at the operating
system level is compatible with all products using the same operating
system, including products of other manufacturers.
4.2.1.2
System ROM
Interface.
Software that interfaces with the
Texas Instruments-supplied system ROMs through the interface vectors
is compatible with other hardware products having the same functional
characteristics.
These products can differ in physical or electrical
characteristics
from
the
standard Texas
Instruments product.
Programs compatible at this level or at the DOS level are more likely
to be compatible with future products.
4.2.1.3
Hardware
Interface.
Programs
that
use
the
hardware
directly
(for
example,
input or output to hardware addresses) are
least like-ly· to· be usable in another computer system.
4.2.2

Areas of Hardware Compatibility

Texas Instruments recognizes that the system ROM
interface
is not
sufficient
for ~ll applications.
Products
using
the advaneed
capabilities of the hardware cannot be restricted to
usage of
this
interface.
The
following
paragraphs
describe
the hardware
compatibility that can be expected in future subsystems or subsystems
accessed from ROM only.
4.2.2.1 Alphanumeric CRT.
The alphanumeric CRT is well-supported by
the system ROM.
AcceSSing the screen directly can speed processing,
lets you use "windowing", and lets you use horizontal scrolling.
You
should restrict
direct access to the alphanumeri~ CRT screen to the
attribute latch and to address ODEOOOH, the actual memory buffer
for
the
screen.
(The
"H"
represents
hexadeCimal.)
Before using the
screen directly, these programs should issue a Clear Screen function
call
to ensure that the hardware is set up for direct access.
Refer
to paragraph 2.4.7 for information about the CRT hardware.
Using the ROM functions to put data on the s-creen while accessing the
screen directly can cause
undesirable hardware actions.
It
is
pOSSible,
for instance, that the screen can be hardware-scrolled, so
that the logical upper left position is no longe~ the physical
upper
left
position.
All
operations
on
the cursor should use the ROM
interface calls.
This will ensure that possible redesigning of
the
cursor logic does not prevent the program from running.

4-2

, DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

4.2.2.2
Graphics
CRT.
The graphics screen is not supported by the
system ROM; therefore, all graphics screen functions must go directly
to the hard~are.
The graphics screen size is 720 by 300.
To simplify modification,
all
routines
that
access
the graphics
hard~are
should be arranged in a modular fashion.
Hard~are-specific
constants should be given symbolic names.
Refer
to
subsection
3.5
for more information.
Texas
Instruments
~ill
endeavor
to keep future graphics
fully compatible ~ith the current hard~are.

hard~are

4.2.2.3 Disk Subsystem.
The disk subsystem is
fully
supported
in
the
system ROM,
~ith
the
exception
of
the ability
to
format
diskettes. -_Fo,r normal ope_rations, direct access to any of
the
disk
hard~are
should
not
be necessary.
Upon request, Texas Instruments
will supply a format routine to qualified software vendors.
4.2.2.4 Keyboard System.
The keyboard system is fully supported
in
the
system ROM.
Direct access
to
the keyboard interface is not
necessary for normal operations.

/

4.2.2.5
Interrupt Controller.
The interrupt
controller
system
is
used
by
the system ROM, but it is not supported in a fashion usable
by soft~are ~riters.
In
future
products,
Texas
Instruments
viII
attempt
to keep
the
same
interrupt
levels,
usage, and hard~are
addresses for accessing the device.
Ho~ever,
the constants
used
to
access this hard~are should be symbolic to facilitate modification.
4.2.2.6
System Timers and Speaker.
The system ROMs contain vectors
that allo~ other
soft~are
to
intercept
the
25-ms
system
timer
interrupts.
The extra timer is reserved for use by Texas Instruments
soft~are products.
The
speaker
(or bell) is well-supported by the system ROM.
access is not necessary.

Direct

4.2.2.7 Parallel Printer Port.
The parallel printer port system
is
fully
supported
in
the system ROM.
Direct access is not necessary
for normal operation.
4.2.2.8 Serial Communications.
The serial
communications hard~are
is
not
directly
supported by
the
system ROM.
To ensure future
compatibility, Texas Instruments
does
not
intend
to
change
this
hard~are.

4-3

TECHNICAL REFERENCE

4.3

DEVICE SERVICE ROUTINES

SYSTEM ROM INTERRUPT VECTOR USAGE

The
system ROM uses interrupt vector locations in the first 1K bytes
of memory.
These vector locations are used for hardware
interrupts,
as
interfaces to the ROM functions, and other uses as given in Table
4-1.
The vectors marked with an asterisk are actually used by
the
ROM.
The other vector locations cause a "wild" interrupt if vectored
to, and the usual display is:

"**

SYSTEM ERROR

** -

1042"

To patch in replacement routines for those in the ROM, any of these
vectors c~n be 'changed by the disk operating system
(DOS)
or by
applications
software.
Table
4-1
gives vector usage in terms of
"interrupt typ~," which is the number used in an INT instruction.
To
calculate the
absolute
address
of
the
vector,
multiply
the
interrupt
,.
type by four.
For example,
the keyboard print screen interrupt
vector (type 5EH)
would be a
double word at
location 0:0178H
(5E x 4 = 1788).
HOTE
The symbol "H" denotes a hexadecimal value.

4-4

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

Table 4-1
Vector
00
01
02*
03
04

05-1F
20-3F
40

41
42

43*
44

45
46*
47*
48*
49*
4A*
4B*
4C

4D*
4E*
4F*
50*

51*

52*
53*

54*

55-56
57*
58*

59*
5A*

58*
5C*

5D*
5E*

5F*

Sy~tem

Interrupt Vector Usage
Reference

Description
Divide-by-zero trap
Single-step trap
Non-maskable interrupt
Break (single-byte)
software interrupt
OverfloW' trap
(Reserved by Intel)
(Reserved for MS-DOS)
8259 interrupt 0
8259 interrupt 1
8259 interrupt 2
8259 --interrupt 3 (-T-imer 1)
8259 interrupt 4
8259 interrupt 5
8259 interrupt 6 (Disk controller)
8259 interrupt 7 (Keyboard UART)
Speaker DSR interface
CRT DSR interface
Keyboard DSR interface
Parallel port DSR interface
(Reserved for future use)
Disk DSR interface
Time-of-day clock DSR interface
System configuration call
Fatal softW'are error trap
Restart timing event
Cancel timing event
SVC interface subroutine
Activate task subroutine
(Reserved for futu"'re- use)
CRT mapping vector
System timing, 25 ms (time slicing)
Common interrupt exit vector (ROM)
System timing, 100 ms
(timing serv.)
Keyboard mapping vector
Keyboard program pause key vector
Keyboard program break key vector
Keyboard print screen vector
Keyboard queueing vector

IAPX 88 Book
IAPX 88 Book
IAPX 88 Book
IAPX 88 Book!
IAPX 88 Book
IAPX 88 Book
KS-DOS Operating System a
Component Data Catalog
Component Data Catalog
Component Data Catalog
Component Data Catalog
Component Data Catalog
Component Data Catalog
Component Data Catalog
Component Data Catalog
Section 3 !!
Section 3 !!
Section 3 !!
Section 3 !!
**

Section 3 !!
Section 3 !!
Section 3 !!

**
**

**
**
**

**

Section 3 !!
Section 3 !!
Section 3 !!
Section
Section
Section
Section
Section
~ection

Notes:
* Vector actually used by ROM.
** Texas Instruments use only - not to be changed.
a Texas Instruments Incorporated publication
Intel Incorporated publication
!! This manual

4-5

3
3
3
3
3
3

!!
!!
!!
!!
!!
!!

TECHNICAL REFERENCE

Table 4-1
Vector
60*
61*
62*

65*
66*

68-9F
AO-OF
EO-E3

DEVICE SERVICE ROUTINES

System Interrupt Vector Usage (Concluded)

Description
System ROM
DS pointer
(F400:AOOO)
DS size in bytes
Factory ROM OS pointer
(F400:0000)
DS size in bytes
Option ROM
DS pointer
(F400:2000)
OS size in bytes
Option ROM
OS pointer
(F400:4000)
OS size in bytes
Option ROM
OS pointer
(F400:6000)
DS size in bytes
Option--ROM
OS point.-er
(F400:8000)
DS size in bytes
Memory size in paragraphs
Outstanding interrupt co-unt
Installed drive types
Extra system configuration
(word 1)
Extra system configuration
(word 2)
Reserved for Texas Instruments
User interrupt vectors
Reserved for CP/M [tmJ

E4-FF

Reference
(180H)
(182H)
(184H)
(186H)
(188H)
(lSAH)
(lSCH)
(18EH)
(190H)
(192H)
(194H)
(196H)
(198H)(word)
(19AH)(byte)
(19BH)(byte)

Section
Section
Section
Section
Section
Section
Section
Section
Section
Section
Section
Section
Section
Section
Section

3 t!
3
3

(19CH)

Section 3 !!

(19EH)

Section 3 !!

3

3
3
3
3
3
3
3
3
3 .!
3 !!
3 !!

CP/M 86
Programmer • s r-'l ide •

Reserved for Texas Instruments

Notes:
* Vector actually used by ROM.
** Texas Instruments use only - not to be changed .
• Texas Instruments Incorporated publication
Intel Incoporated publication
!! This manual

4.3.1

Hardware Interrupt Service Routines

All
standard
interrupt service routines (ISR) have limited internal
stacks.
They provide four levels (8 bytes),
which is
the amount
required by any application program or subroutine that runs with
interrupts enabled.
An ISR needs 8 bytes of
the
user's
stack;
2
bytes
to push the user's
code
segment
(CS),
2 bytes
for the
instruction pointer (IP), 2 bytes for flags, and 2 bytes to push
the
data segment (OS).
The ISR saves the user's stack segment and stack
pointer in the RAM data area of the system ROM.
The ISR then change~
the stack segment and
stack pointer
so
that
they point
to
the
internal
stack of the interrupt routine.
Khen the ISR is complete,
it executes a long jump to the common interrupt exit vector.
4-6

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

4.3.2

Common Interrupt Exit Vector

All ISRs (in the ROM and in Texas Instruments applications
programs)
use
a
common
interrupt
exit vector.
The ISR executes a long jump
(LONG JMP) to the routine pOinted out by the
common
interrupt
exit
vector.
The
common
interrupt
exit routine restores the stack and
commonly used registers, decrements the outstanding interrupt counter
(INTCTR), sends the end-of-interrupt (EOI) command to
the
interrupt
controller,
and
returns to the interrupted code vith a return-frominterrupt instruction (IRET).
A real-time operating system (OS),
such as
the
OS
kernel
of TI
communication
programs,
uses
the
INTCTR
to
keep
track of
the
outstanding interrupts.
Be sure to include the appropriate code vhen
creating an ISR.
A sample interrupt service routine,
vith
instructions, is included in Appendix G.

installation

and

removal

The
common interrupt exit routine is contained in ROM, but an OS can
patch it so that all interrupt
service
routines
exit
through
the
operating system.
lecause the interrupt structure is complex (due "to
interaction betveen
the shared interrupts and the requirement for a
common exit point), the potential
user
should
read
the
folloving
paragraphs, carefully studying the examples given.

4.3.3

Timer Interrupts

The
system
timer
ticks
every
25 ms.
The ISR for this timer is
located in the ROM, and it processes events such as disk motor
timeouts and date/time-keeping.
Softvare interrupts are performed at tvo
points
during this interrupt service routine, allowing access to the
timing services.
One interrupt occurs every count (every 25 ms), and
the other occurs every four
counts
(100-ms
intervals).
Usually,
these interrupt vectors point to an IRET instruction in the ROM.
The
user
can
patch one
or
both of
the
vectors to point to his ovn
routines.
These routines are free to use the
AX,
BX,
01,
and
ES
registers,
but
they must
preserve
any other registers used.
The
stack used is the internal
stack
of
the
timer
interrupt
service
routine
and
it is limited in depth.
If the user does not re-enable
interrupts (the INT instruction disabled them), there
are
8
levels
(16 bytes) of stack available.
If the interrupts are re-enabled, the
user has only four levels (8 bytes) available.
If more stack size is
required, the user should svitch to an internal stack of the required
size (allotting 8 bytes for higher priority interrupts).
It
is
important
to
remember
that
the routines installed in this
manner are executing at the interrupt level.
Interrupts must not
be
disabled
for
any significant length of time, because any time spent
in these routines directly affects system efficiency.
The user must
also
understand
hov some other mechanism (such as a timing event in
the handler routine of the OS)
can
patch
the
timing
vectors
and
install
its
ovn routines.
Instead of using the IRET instruction to

4-7

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

end the routine, make a long jump
to
the
original
(vhich vas saved vhen the routine vas installed.)

4.4

vector

address

ROM STRUCTURE

The
folloving
paragraphs describe
sequences for optional ROMs.
4.4.1

the

use,

forma t ,

and calling

ROM Usage

Optional ROMs provide an
interface
betveen
the hardvare and
the
system softvare.
With this interface installed, modification of the
hardvare requires chan9tng only the ROM
softvare,
not
all
of
the
applications programs.
The
system
system ROM.
board)
for
vhich can be

defines
locations
for
six ROMs.
One of these is the
Texas Instruments has
reserved another
the main
(on
future
use.
The four remaining are the optional ROMs,
used.by any of the available operating systems.

Table 4-2 shovs the ROM addresses and suggestions for
Table 4-2

Absolute
Address
CS:Offset
F4000H

F400:0000H

F6000H

F400:2000H

F8000H
FAOOOH
FCOOOH

F400:4000H
F400:6000H
F400:8000H

FEOOOH

F400:AOOOH

4.4.2

their use.

ROM Addresses and Suggested Uses

Comments

Qll

Miscellaneous
I/O opt ion
Local area
netvork
Mass storage
Open
System ROM
expansion
System ROM

Reserved for Texas· Instruments
Reserved for Texas Instruments
Texas Instruments Winchester card
Open
Reserved for Texas Instruments
Reserved for Texas Instruments

ROM Format

The ROM format must be knovn to:

*

Identify the ROM

*
*

Use a standard calling sequence
Use the diagnostics

4-8

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

ROMs can be one of the folloYing sizes:

*

256 bytes

*

512 bytes

*

1024 bytes

*

2048 bytes

*

4096 bytes

*

8192 bytes

The ROM size, in binary, is stored in the first yord in the ROM.
The
yord value-~~stored lov~yte first, folloYing the INTEL Corporation
convention.
The
second yord
in
the
option ROM is the poyer-up initialization
address.
The system ROM uses a NEAR call to this address during
the
poYer-up process.
The
user must
ensure
that the initialization
address is calculat~d as an offset from the segment address F400.
text
string
identifying
the
The next location in the ROM stores a
entry in
this string is the length of the string
ROM.
The
first
i n for ma I: ion
d e t e r min e 5
h IHf
mu c h
ma t e ria 1
is
(1 byte).
This
displayed.
The rest of the string consists of a five-character version number, a
space character,
a
six-character name,
and any descriptive text
(copyright, for example) that the vendor requires.
The option ROM code and fixed data (in a
vendor) folloys the text string.

j

format

determined

by

the

The last yord in the ROM stores the cyclic redundancy check (CRC-16)
remainder from all the previous bytes in the ROM.
Both the poYer-up
test
and
the advanced diagnostics test read this yord to see if the
ROM is yorking properly.
The CRC-16 routine, available in the system
ROM, calculates this remainder.
Khen the CRC remainder is
correctly
placed,
running
the CRC-16 routine through the entire length of the
ROM (including the CRC) results in a
zero
remainder.
The CRC-16
routine available in the system ROM calculates the remainder.
4.4.3

Option ROM Interrupt Vector Usage

The
system ROM uses interrupt vector locations in the first 1K bytes
of RAM for hardYare interrupts, interface to the ROM functions,
and
other ISRs.
See paragraph 4.3.1 for more information.
Interrupt
vectors access
the
option ROM entry points.
The option
softYare can use the vectors above SOH (vector address 200H).

4-9

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

NOTE
Conflicting vector assignments
can cause data
loss
or data errors.
Be extremely careful vhen
making these assignments.

4.4.4

RAM Usage by Option ROM

Each ROM has a separate RAM data area assigned
to
it.
These data
areas float; therefore, the ROM does not require a dedicated area in
RAM.
Copying the data area and updating the pointer moves
the data
area.
The ROM accesses these data areas using the pointers and sizes
in
the
i~terrupt vecto~ area,
so that moving the data area does not
affect the ROM.
The ROM initializes the pOinters and data areas at
boot-up
time,
so
the system ROM data area pointer is the only one
used.
All option ROMs are addressed at absolute
segment addresses
F400H,
vith an offset
from 0000 to AOOOH.
The ROM code is linked so that
its code segment is F400H.
This code
segment
vas chosen
so
that
option ROMs can be addressed vith the same code segment as the system
ROM.
This enables
the option ROM to access the ROM poverup entry
routines as NEAR instead of FAR.
The first location of
the
system /
ROM, described in segment:offset notation, is F400:AOOO.
There
is another advantage
to
linking the ROMs
this vay.
The
interrupt vector area at location 0000:0000 is nov also accessable as
F400:COOO.
This simplifies slightly the code seq~~nce used to assign
a local data area.
4.4.5

Initializing the Option ROM

The pover-up sequence executed by the main ROM tests each option ROM
address in sequence.
Address OF400:0000H i~ tested firs·t and address
OF400:eOOOH
(the main board option RO~) is tested last.
Khen a ROM
is found, the diagnostics performs a CRC-16 calculation.
The
system
displays an error message if the ROM is bad.
If,the ROM is good, the
system initializes the option ROM.
The initialization code saves the
BX, OX.
SI, SP, CS, SS, and DS registers so that using a NEAR return
instruction returns control to the system ROM.

4.5

BOOTING UP THE SYSTEM

Most
system softvare
is
contained
in some mass-storage
system
(diskette, Kinchester disk, or local netvork server).
The user must
be able to find and load the system softvare from these devices.
The
Texas
Instruments Professional Computer
loads a single sector of
program information from a knovn point on the specified device.
The
4-10

TECHNICAL REFERENCE

DEVICE ,SERVICE ROUTINES

system
then
calls
the code that vas loaded, vhich "bootstraps" the
rest of the programs.
The
location
loaded at
pover-up
is
the
lovest
available.
For
diskettes and Winchester
disks,
cylinder (track) 0, surface (side) 0, and sector 1.
start at 1.)
4.5.1

logical
sector
this location is
(Sector
numbers

Boot Sequence

The options installed in the system determine the boot sequence.
The
sequence starts at the highest-priority option address (OF400:0000H).
proceeds to the lowest (OF400:eOOOH). then boots the diskette system.
The boot s~quence is:
1. Local Area Netvork (LAN)
2.

Winchester disk subsystem

3.

Diskette drive A

4. Diskette drive B
5.

Diskette drive C

I

6. Diskette drive D
Pressing
the ~ key during the pover-up sequence (immediately after
the "vhite flash" appears across the top of the screen)
changes
the
boot
priority.
Each time the ~ key is pressed, the system lowers
the boot sequence to the next available option.
For example, if
the
system contains either an LAN or a Winchester dis-k, pressing the ESC
key once lowers the boot sequence to
the
first
diskette.
If
the
system contains
both an LAN and a Winchester, pressing the ESC key
once moves from the LAN down to the Winchester,
while pressing
the
ESC key twice moves to the first diskette.
4.5.2

Loading and Calling the Boot Code

The booting device
loads the boot code at address OOOO:COOOH.
The
stack operates below this address.
After the
code
is
loaded,
the
system checks address 0000:C1FCH for the bytes 74H and 69H (ti).
The
presence of
these bytes indicates a Texas Instruments system disk.
If these bytes are absent, the system generates an
error message.
(Texas
Instrument~
disks
used
only for
data storage contain the
characters "NO".)
The system then runs the CRC-16 test over all
512
bytes of the lovest logical sector loaded at pover-up.
If the CRC-16
remainder
is
incorrect,
the system generates an error message.
If
the system passes both these tests, it calls the boot sector code at
address OOOO:COOOH (FAR).
The logical drive number (0, 1, 2, 3) from
4-11

TECH~ICAL

DEVICE SERVICE ROUTINES

REFERENCE

which the system boots is placed in register BL.
Before loading
the operating
required initializations such as
(single or double sided, 40 or
Winchester drive.
(The DSR must
for further loading.)

system, the boot code performs other
setting up the type of floppy disk
80 track), or setting up the type of
be able to recognize the disk format

The boot code then loads any system files needed by the as and
jumps
to
the OS
code.
If the os requires RAM where the system ROMs are
using it, the RAM data areas used by
the ROM can be moved.
The
pointers
to the RAM segments must be modified accordingly.
If a ROM
is not using a RAM data area, its pointer is 0000.
This pointer must
remain zero even if the area is moved.
Table 4-3 gives the addresse~
of these pointers.

Table 4-3

Pointer addresses and Descriptions

Address Pointer De-scr i pt ion ROM Address
0000:0180
0000:0182

System ROM data segment pOinter
System ROM data length in bytes

F400:AOOO

0000:0184
0000:0186

Option ROM data segment pOinter
Option ROM data length in bytes

F400:0000

0000:0188
0000:018A

Option ROM data segment pointer
Option -ROM data length in bytes

F400:2000

0000:018C
0000:018E

Option ROM data segment pointer
Option ROM data length in bytes

F400:4000

0000:0190
0000:0192

Option ROM data segment pointer
Option ROM data length in byt_es

F400:6000

0000:0194
0000:0196

Option ROM data segment pointer
Option ROM data length in bytes

F400:8000

If any errors occur during the loading and initializing of
the OS,
the boot
code returns to the caller.
The registers BX, ES, CS, and
the stack must be preserved.
The register os must
be preserved
unless
toe ROM data areas are moved.
If the data areas are moved,
adjust the os register by
the amount
of difference between
the
original position and the new position.
A OSR error code returns to
the caller displayed as a
system error message.
This code
is
presented in register AH.
Appendix H gives
boot sector.

a sample source program that could be used in the

4-12

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

4.5.3

Booting FroM

~n

Option Device

When an option device is to be booted up, it must
be
the last
one
called
in
the power-up sequence.
Otherwise, other options must be
called and initialized during the boot sequence.
Appendix G contains
a sample assembly code showing the boot sequence.
If more than one bootable option is present in the system,
each one
must have
the DX register set to OFFFFH.
The bootable option then
calls all lower priority ROMs in the system.
Any ROM called in
this
manner performs all
required
initialization except for booting.
Because the system ROM sets the DX register to OOOOH when
it
calls
the option ROMs, an option device will boot if called by the system
ROM, but not if called by another ROH ..

-

If booting-- f'rom an optlon device ,fails,
the ROH displays
the
appropriate error messages and returns to the caller with registers
BX, DX, SI, and DS intact.
The system ROM then calls
the other
options.
If none of
the options boot, the system ROM boots the
Floppy Disk system.
This procedure can-~ause multiple
initializations of
the
However,
no
harm
results.
Entering
the warm boot
(CTRL/ALT/DEL)
from
the
keyboard
also
causes
initializations.

4.6

options.
sequence
multiple

SYSTEM CONFIGURATION FUNCTION CALLS

The following paragraphs describe
the function calls 'for the two
types of system configuration information, which are:

*

Function calls that return the
information
(System Configuration Function)

*

Function calls
that
return the address of the information
(Extra System Configuration Function)

in

a

register

The firs,t type, System Configuration Function, returns most
of
the
information
required
for
application programs.
Extra System
Configuration Function, the second type, is intended for use at
the
system level.
This method contains additional information usable for
changing the configuration of devices set by software.
4.6.1

Sy~tem

Configuration Function

This function is used to determine the installation status of certain
system options.
It is invoked by executing an INT 4FH instruction.
Upon return,
register ax contains
the size of contiguous RAM
(starting at OOOOOH) in paragraphs
(16-byte blocks).
A 129K-byte
system, for example. would return 2000H in ax.
4-13

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

Register AX contains
the system configuration word, which reflects /
the installation status of various system options.
The bits
of
the
word are defined in Table 4-4.
Table 4-4
Bit
0*
1
2
3
4
5
6
7
9
9·

10
11
12
13
14
15
*

Bit

0

stat~ment

4.6.2

System Configuration Hord-Bit Definition
Definition

Diskette drive 0 (internal) installed
Diskette drive 1 (internal) installed
Diskette drive 2 (external) installed
Diskette drive 3 (external) installed
E1-E2 jumper (0 indicates Drive A is double-sided)
. E3-E4 jumper (0 indicates Drive A has 90 tracks)
E5-E6 jumper (0 indicates a 50-Hz system)
Hinchester disk controller installed
Serial port 1 installed
Serial port 2 installed
Serial port 3 installed
Serial port 4 installed
Graphics RAM bank A installed
Graphics RAM bank B installed
Graphics RAM bank C installed
Reserved

is
the least-significant bit.
Unless otherwise stated, a
is true when its corresponding bit is a 1.

Extra System Configuration Function

This function determines the installation status
of
system options
that are not
covered
in
the
standard system configuration call.
Hhereas
the standard system configurati2n call returns a
word
containing the information necessary for most applications~ the extra
system
configuration
function
is
used primarily for
systems
programming purposes.
The extra system configuration function is invoked by placing a
OBH
in register AH and executing an INTerrupt 49H.
Upon return, register
AL contains the drive-type byte (AH is undefined).
BX contains extra
system
configuration
word
1,
and CX contains
extra system
configuration word 2.
The bits of extra system configuration word 1
are defined in Table 4-5.

4-14

DEVICE SERVICE ROUTINES

TECHHICAL REFERENCE

Table 4-5

Definition

Bit
0*
1
2
3
4
5
6

7
8
9 __

10
11
12
13
14
15

,(

*

Extra System Configuration Word 1 (BX)

8087 numeric coprocessor

is installed

\
I
I

>

Reserved

I
I
/
300/1200 baud modem in
300/1200-__baud modem in
300/1200 baud modem in
300/1200 baud modem in
300 baud modem in port
300 baud modem in port
300 baud modem in port
300 baud modem in port

port
port
port
port

1
2
3
4

1
2
3
4

Bit
0
is
the
least-significant bit.
Unless otherwise
stated, a statement is true when its corresponding bit is a
1.

Word 2 of the Extra Sy~tem C~nfiguration function call is contained
in CX.
This word is currently undefined, and is being reserved for
later expansion.

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

The
drive-type
byte
defines
the
types
of the installed diskette
drives.
This information, combined with the "installed drive"
bits
in
the
standard
system
configuration
word,
yields
complete
information about the drives in the system.
At power-up, the drive A
definition jumpers (El - E2 and E3 - E4) are read.
The
information
is
stored in memory as a byte of four identical, 2-bit fields.
This
byte is
read
during
the
extra
configuration
function
call
and
returned
in
register
AL.
The
drive
byte
(in
AL) is the 2-bit
configuration code for all four of
the
diskette
drives,
which
is
shown in Figure 4-1.

I

7

6

-

I

5

4

3

2

I

1

Drive B

Drive C

Drive D

I

0

Drive A

Each 2-bit field is defined as:
LSB

o

o

1
1

o

=

1

=

o

*MSB

=

Definition

MSB*

1

=
=

Single-sided
Double-sided
Single-sided
Double-sided

40
40
80
80

track
track
track
track

Most significant bit; LSB .= Least significant bit.
2223216-22

Figure 4-1

Register AL Drive Byte

The
operating
system uses this drive byte to format, copy, and use
diskette files.
It is possible to mix dri~e types i~ ~ne-system (for
example, one single-sided and one double-sided drive) by setting
the
drive-type
byte with
the
pertinent
information; but, this is not
recommended.
Mixed-drive
type
systems
are
confusing.
Users
frequently insert the wrong diskettes, thereby losing data.
4.6.3

Get Pointer to System Configuration

This
function
is
invoked
by
placing a
09H
in
register AH and
executing an interrupt 48H.
On return, ES contains the segment,
and
BX
contains
the
offset
of
the standard system configuration word
(hereafter, the notation for this is ES:BX).
This functi.on
is
used
by
system
software
that
has
a
need
to change the configuration
information.
Although an application
program
can
access
the
information in this manner, the configuration must not be changed.

4-16

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

4.6.4

Get Pointer to Extra System Configuration

This function
is
invoked by placing a
OAH in register AH and
executing an INTerrupt 49H.
On return, ES:BX points
to
the extra
system configuration information, formatted as follows:
ES:[BX-3]=(word)
ES:[BX+O]=(byte)
ES:[BX+l]=(word)
ES:[BX+3]=(word)

Size of memory in 16-byte blocks
Drive-type byte
Extra system configuration word 1
Extra system configuration word 2

This function
is used by system software that has a need to change
the confi~uration inform~tion.
Although an application program can
access
the- information in this manner, the configuration must not be
changed.

4.1

GENERAL-PURPOSE ROM FUNCTIONS

The following paragraphs describe some general-purpose functions,
summarize
the ROM interface interrupts, and explain how the RAM uses
the ROM.
4.1.1

Delay

This function causes a delay, in milliseconds, of the val~e placed in
register CX.
To invoke the function, place the delay value
in CX,
OSH in AH, and execute an INT 49H.
The delay is approximate, but can
be used wherever an inexact
software delay i~ acceptable.
All
registers except CX are preserved.
4.1.2

CRC Calculation

This function calculates the cyclic redundancy check
(CRC-16)
value
for a
specified block of memory.
It
is invoked by placing the
address of the memory block in ES:BX, the size of the block in BP,
and
the value 06H in AH, then executing an tNT 49H.
On return, OX
contains the CRC value; if OX=OOOO, the Z-flag is set.
For memory
blocks
that
follow the convention of the eRC being the last word in
the block, this routine allows easy CRC checking.
First, the CRC of
the memory block is calculated, with the size of the block set to the
actual size minus two.
The CRC word is then written to the last yord
of
the block.
Subsequently, the CRC of this block can be checked by
calling this function Yith the actual size of
the memory block
(including
the previously calculated CRe).
By definition, the CRe
result of this block is zero (if the eRC matches the data) and the Zflag is set; otherwise, the CRe fails and the Z-flag is
reset.
All
registers are used except 01, SI, and OS.
ES remains unchanged.

4-11

TECHNICAL REFERENCE

4.7.3

DEVICE SERVICE ROUTINES

Print ROM Message

This
function
displays a ROM CS-relative message.
It is invoked by
placing the offset of the zero-terminated message in SI, 07H
in AH,
and executing an INT 48H.
This function is used by the option ROMs,
because all the ROMs share a common CS.
It is not a
general-purpose
routine.
4.7.4

Display System Error Code

This
function
format:

is

used

** System

to

Er~or**

display

a system error in the standard

- xxxx

It is invoked by placing the
error
displayed message above)
in
BX,
executing an INT 4BH.

code
(the
xxxx
value
in
the
placing the value OBH in AH, and

SPEAKER DSR

4.8

The following paragraphs describe the speaker DSR and
the
functions
it
provides
to the system or application programs that use it.
The
functions are:'

*
*

Get Speaker Status

*

Set Speaker Frequency

*

Speaker ON

*

Speaker OFF

Sound the Speaker

The speaker DSR functions are located
in
the
system ROM and are
accessed
through
the
software
interrupt mechanism of
the
80B8
microprocessor.
The desired function is chosen hy placing an opcode
in register AH and executing an INT 48H instruction.
All registers
are preserved except AX.

4.B.l

Sound the Speaker - AH

=

0

This function turns the speaker on (at the current frequency) for the
length of time specified in register AL.
Time is measured
in
25-ms
increments.
For
example, a value of 40 in AL causes the speaker to
sound for 1 second.
Timing is handled in the
ROM with
the
result
that
the
request
turns
on
the
speaker,
starts
the
timer, and
immediately returns to the user.
The sound continues until timed out
by the ROM code.
Because this function call
occurs asynchronously

4-18

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

with
the
25-ms system timer. the time can be "off" by as much as 25
ms.
For example. specifying a single 25-ms unit of
time
can
cause
the speaker to sound for a period of 0 to 25 ms.
If there is need to
synchronize with
the
sound
or simply to know when sound is turned
off. use the Get Speaker Status (AH=l) function.
4.9.2

Get Speaker Status

AH

=1

This function returns the status of the speaker in
the Z-flag.
the speaker is currently enabled (sound). the Z-flag is set at O.
the speaker is currently disabled (no sound), the Z-flag is set at
This function can be used to find out when a sound requested with
Sound the Speaker (AH=O) function has been completed.
4.9.3

Set Speaker Frequency

If
If
1.
the

AH = 2

This
function
sets
the frequency of
the
speaker.
Usually this
function is called only when the speaker is disabled.
The value
in
cx sets the frequency of
the timer that drives the speaker.
The
input frequency of the timer is 1.25 MHz, and the value in CX becom'es
a divider for this f~~quen~y.
For example, the system beep routine
(900 Hz) uses a value of 1563 (1 250 000 Hz / 1563 = 900 Hz).
4.9.4

Speaker ON

AH

=

3

This
function enables the speaker (turns on the sound).
remains on until it is turned off by either
(1)

The speaker

the Speaker OFF (AH=4) function or

(2) by the ROM

timing routine, which results from
either
the Speaker (AH=O) function or a normal system beep.

4.9.5

Speaker OFF

AH

·the

Sound

=4

This function performs the reverse of the Speaker ON (AH=3) function
by disabling the speaker (turning off the sound) . .

TE~HNICAL

4.9

DEVICE SERVICE ROUTINES

REFERENCE

TIHE-OF-DAY CLOCK DSR

The following paragraphs de~cribe the time-of-day clock DSR and
the
functions
it provides to the system or application programs that use
it.
Th e fun c t ion s are:

*
*
*

Set the date
Set the time
Get the date and time

The clock DSR'consists of-routines to set and read the
time of day
and date
information kept by the timing services of the system ROM.
At power-up, the time is set to 00:00:00.00, and the date is
set
to
0000.
The~e can be reset by system or user programs.
Once set with
a valid time,
the clock keeps
the correct
time with a
1/10-s
resolution.
The
time
is kept
in 24-hour format and the date is
simply a cumulative-count of days since the clock was started.
As a
matter of convenience
(for MS-DOS),
the date is specified as the
number of days\ since 3anuary 1, 1980.
For example,
the date value
for September 10, 1982, is 983.
The
three clock functions are located in the system ROM and are
accessed
through the softWare interrupt mechanism of
the 8088
microprocessor.
The desired function is chosen by placing an opcode
in register AH and executing an INT 4EH instruction.
All registers
are preserved except AX and any other registers ia which' information
is returned.
4.9.1

Set the Date

AH

=a

The
This function sets the date to the value in
the BX register.
By
date
is simply a
count of days since the clock was·sfarted.
The count
is
convention, this is the number of days since 1-1-80.
incremented when the hour rolls over from 23 to 00.
4.9.2
T~

Set the Time

set the time,
CH
CL
DH
DL

AH

=1

the registers must be initialized as follows:

= Hours

(00 - 23)
59)
59)
seconds (00 - 99)

= Minutes (00 = Seconds (00
= Hundredths of

It
is
the user's responsibility to make sure the values passed are
within the ranges specified.
These values are not checked for
range
and can be set to represent a meaningless time.
The time, however,
4-20

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

eventually counts into the normal sequence.
4.9.3

Get

the Date and Time

AH

=

2

This function returns the current date in register AX and the current
time in registers eX/DX in the formats described previously.

4.10

CRT DSR

The folloving paragraphs describe the CRT DSR and
the
functions
it
provides
to
the
system or application programs that use it.
The
major
functions
are
(1)
video mode
control and
(2)
character
handling.
For

information about the eRT graphics hardvare. refer to paragraph
and to subsection 3.5.
The CRT DSR functions are
located
in
the
system ROM and are accessed through the use of the 80B8 softvare
interrupt mechanism (essentially an address-independent
subroutine
call) .
A typi cal .. user of
thi s
OSR
is
the OS-dependen t sy!! tem
interface code (the BIOS), vhich resides on a particular OS disk and
is
loaded
into RAM during disk boot up.
The desired function is
chosen by placing an opcode in register AH.
The CRT opcodes and
functions
are given
in Table
4-6.
Various CRT functions requirs
parameters to be passed in specific
registers. in addition
to AH.
After
register AH and the parameter registers are set up, the user
can execute an INT 49H and
the
specified function
is
performed.
During this interrupt, all registers are preserved except AX, CX, and
OX.
2.4.7,

4-21

TECHNICAL REFERENCE

Table 4-6
Opcode
OOH
OlH
02H
03H
04H
OSH
06H
07H
OSH
09H
OAH
OSH
OCH
ODH
OEH
OFH
lOH
llH
12H
13H
14H
lSH
16H
17H
lSH

DEVICE SERVICE ROUTINES

CRT DSR Opcodes and Functions

Function
(Null function)
Set cursor type
Set cursor position
Read cursor position
(Null function)
(Null function)
Scroll text block
Scroll text block
Be~d character _and attribute at current cursor position
Write character and attribute at current cursor position
Write character only at current cursor position
(Null function)
(Hull function)
(Null function)
Write ASCII teletype
(NullfuJfc t ion')
Write block of characters at current cursor with attribute
Write block of characters only at current cursor
Set entire screen to specified attribute(s)
Clear text screen and home the cursor
Clear graphics screen
Set TTY status line beginning
Set attribute latch to specified attribute(s)
Read physical· display begin pointer
Print TTY string

4-22

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

4.10.1

Set Cursor Type - AH

= 01H

This function allows an application to define the starting and ending
scan line for the cursor and its characteristics (either blinking or
no cursor).
Required input for this function is described in Figure
4-2.

CH

=

Byte 1
Start scan line of cursor
Cursor type:
00 = no blink
01 = no cursor
10 = fast blink
11 = slow blink
Not used

CL =

Byte 2
End scan line of cursor·
Bits 7 through 5 not used
(Valid values for scan line are 0 through 11 decimal.)
2223218-23

Figure 4-2

Byte Definition - Set Cursor Type

4-23

TECHNICAL REFERENCE

4.10.2

DEVICE SERVICE ROUTINES

Set Cursor Position - AH

=

02H

NOTE
The user should be avare that screen coordinates
use the 0,0 coordinate as
the
upper
left-hand
corner of the display.
All routines that require
a
coordinate parameter use this convention.
The
screen should look to the user as though he
vere
vorking
vith
the absolute value
of fourthquadrant
coordinates
of
a
tvo-dimensional
coordinate system.
This
function
causes
the cursor (of the current type) to be set at
the specified x,y (column/rov) coordinate of the display.
Required input for this function is as follovs:

4.10.3

DH

=x

Column coordinate
(Valid values are 0 through 79 deCimal.)

DL

=Y

Rov coordinate
(Valid values are 0 through 24

~ecimal.)

Read Cursor Position - AH = 03H

This function returns the current position and type of
the
Output from the read cursor position routine is as foll~vs:
DH, DL = x, y

cursor.

(column/rov) location of the cursor

CH, CL = current cursor type
Refer to paragraph 4.10.1 for an explanation of the values for CH and
CL.
The
"phantom" position of the cursor in column 81 creates a special
situation in reading the cursor postion.
If a character
is
vritten
in the last column of the screen by a TTY vrite, it can be read, even
though it is not visible.
This position, column 81 of the last line,
becomes
visible after another
character is vritten and the screen
scrolls.
The po~ition returns as column 0, rov 25.
This is
invalid
input to the Set Cursor Position (AH=02H) routine.
See paragraph 4.10.18 for additional information on the cursor.

4-24

: DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

4.~0.4

Scroll Text Block - AH

= 06H

and 07H

The ROM contains only one general-purpose scroll routine, which
handles both upward and downward scrolling.
When
the destination
coordinates are less
than the source coordinates, the scroll is up
and to the left; when the destination coordinates are greater
than
the source coordinates, the scroll is down and to the right.
The scrolling functions allow an application program to specify a
block of text, then move or copy that block to another location on
the screen.
Specifying a scroll with blanking causes the source text
to be blanked as
it
is moved.
During this process, the source
character is read
to a
temporary register and its location is
blanked.
_Then
the character
is rewritten
to
its destination
location.
This provides for a nondestructive move in the event
that
the source and destination locations are the same and blanking is
specified.
This method satisfies the requirement that, in scrolling,
the data being moved or copied be preserved in its destination
location.
Required input for this function is as follows:
AL

=

AL

=
= Source begin column/row location
= Destination begin column/row location

(DH,DL)
(BH,BL)

0 (Blank out source text.
This is a move block.)
or
)0 (Don't blank source text.
This is a copy block.)

CH

= Column

CL

= Line

length of block
(Valid values are ~ through 80 decimal.

r"

length of block
(Valid values are ~ through 2S deCimal.)

The source text block boundaries in (x,y) coordinates are as follows:
Upper
Upper
Lower
Lower

left
right
left
right

=

=
=
=

(DH.DL)
(OH + CH
DL
(ON
(ON + CH

+

OL)
CL)
' DL + CL)

4-25

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

The folloving
items further
describe
explain the sequence of operation.

*

the

scrolling routines and

A sentence is considered the smallest logical block of text.
Therefore, vith this
scrolling capability,
the user can
specify a
block
to be a sentence.
This may (or may not)
vrap to a nev line and "unvrap" as it is moved
(or copied)
to
its destination
(that
is, the column length parameter
would bypass line boundaries and pick up characters from the
next line).
The user
should note
that
this
is quite
effective when
the line length is equal to one but might
cause unwanted block movement if the line length is greater
than one.

*

for
the
scrolling routine is done on a
character basis as the characters are being moved.
When a
scroll down
is
in progress,
the scroll copies the last
character in the source block to the last character position
in
the destination block.
The processing is backward
through
the blocks while checking character positions for
out-of-bound characters.
This means that in the scroll-down
action, no scroll takes place if any destination position
lies beyond
the end of the screen.
Asymmetrically, when a
scroll up is
in progress,
the
scroll copies
the firs·t
character
in
the
source block
to
the first
character
position in the destination block.
The scroll proceeds
forward,
through the blocks,
While checking character
positions for out-of-bound characters.
In
the
scroll-up
action,
the scroll
takes place until it reaches a source
character position that lies beyond the en~ of the screen.

*

When the user requests scrolling vith blanking,
the
status
of the.attribute latch at entry is preserved.
Th~ character
attributes follov
the character as
it
is moved on the
screen, and the blanked area is written with
the default
attributes
(that
is,
high intensity for a
monochrome
monitor, and white for a color monitor).

*

When the user requests
scrolling without blanking,
the
attribute
latch is set to the same statu~ as the attribute
of the last character
that
was
scrolled
(that
is,
the
attribute of
the first character of the source block when
scrolling down, or the attribute of the last
character of·
the source block when scrolling up).

Bouid~ry

checkib~

4-26

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

Read Character/Attribute at Cursor Position - AH

4.~O.5

= OSH

This
function
returns a character and its associated attribute from
the current cursor position on the screen as follovs.
See paragraph
4.~O.~5
for
attribute
values and a description of the attributes
supported.
AH

= Attribute

value

AL

= Character

read
NOTE

The attribute latch remains set
that is returned.

4.~O.6

.
\

to the

attribute

Write Character/Attribute at Cursor Position - AH

= 09H

This
function
enables
the vriting of a character vith the given
attribute at the
current
cursor position.
(The attribute
latch
remains set to the attribute specified in register BL.)
The user can
specify a count and cause the character to be vritten a given number
of times starting at the. cursor's current
position.
This
function
does
not
increment the cursor automatically, and the cursor remains
at
its
current
position vhile
the
characters are
vritten
in
succession from that location.
If an application uses this method of
vriting characters,
it is assumed that the application also handles
the cursor positioning.
~herefore,
no
cursor
movement
is
implemented.
Control characters (CR,LF, and so on) are not executed
as such vhen using this function; their symbols are printed
on
the
display.
For more information, refer to paragraph 4.~O.~5.
The required input for
AL
BL
CX

= Character
= Attribute
= Number of

this function is as 10llovs:

to vrite
of

characte~(s)

times to vrite the character

4-27

TECHNICAL REFERENCE

4.10.7

DEVICE SERVICE ROUTINES

Write Character at Cursor Position - AH

= OAH

This
function
is similar to the preceding function.
The difference
is that the character being vritten takes on the attributes remaining
in the attribute latch from the last CRT call.
For more information.
refer to paragraph 4.10.6.
The required input for this function is as follows:
AL
CX

4.10.8

= 'Character
= Number of

to vrite
times to vrite the character

Write ASCII Teletype - AH

= OEH

This function alloys TTY output
to
the
screen from application
programs.
Writing begins at
the current cursor pOSition, and the
cursor is advanced automatically to its next position on the
screen.
For more
information,
refer
to paragraph 4.10.18.
The screen is
scrolled automatically when needed (such as writing past the
end
of
the screen).
The control characters CR, LF. as, and BEL are executed
rather than vritten.
NOTE
If a
status
region
is
currently
in use, the
scroll starts one line before
the beginning of
the
status
region, exactly as if that line ~~re
the end of the screen.
Because the contents of the attribute latch remain unchanged,
each
character
vritten vith
this function assumes the attributes of the
previously vritten character.
The required input for
AL

= Character

this function .is as follovs:

to vrite

4-28

r

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

4.l0.9

Krite Block of characters at Cursor Kith Attribute - AH=10H

This function writes a given block of data with a specified attribute
to the
screen,
starting at
the
current
cursor position.
This
function
requires less screen I/O overhead if an application program
has a "known" block of data to be written
to
the
screen.
"Known"
means
that
the
block
is
of a
given
length,
and is in a given
contiguous area of memory.
As with the Krite/Character Attribute at
Cursor
Position
function,
the
cursor
is
not
automatically
incremented.
For more information, see paragraph 4.10.15.
The required input for this function is as follows:
AL = it~ri'bute(s) of characters

*

OX = Segment location of character block
BX = Offset location of character block
CX = Block

4.10.10

le~gth

**

Write Block of Characters Only at Cursor Position - AH=llH

This
function
is
similar
to
the
preceding function,
with
the
difference that
the attribute
parameter
is
not
specified.
The
characters assume
the attribute(s) remaining in the attribute latch
from the last CRT call.
The required input for
AL
OX
BX
CX

*
**

this function is as follows:

= Don't care
= Segment location of character block
= Offset location of character block
= Block length **

The attribute(s) specified is in effect for the entire
block and the attribute latch remains set to the attribute
specified in register AL.
Thi~

routine "clips" any characters that do not fit on the
screen.
Characters are written to the end of the screen, then
all other characters are lost/not vritten.
To prevent losing
characters, the user should place the cursor so that the
number of character pOSitions from the cursor to the end of
the screen is greater than or equal to the block iength.

4-29

TECHHICAL REFEREHCE

4.10.11

DEVICE SERVICE ROUTIHES

Change Screen Attribute(s) - AH

= 12H

This
function
specifies attribute(s)
that
affect
all
of
the
characters on
the display.
The attribute
latch
is
set to the
attribute specified in register AL on exit.
This
routine does
not
change
the position
of any characters on the screen.
Two examples
are blinking of the entire screen and reverse video of
the
entire
screen.
For more information. see paragraph 4.10.15.
The required input for this function is as follows:
AL

4.10.12

= Attribute(s)

to use

Clear Text Screen and Home the Cursor - AH

= 13H

This
routine clears the text screen and sends the cursor to the home
position (0,0 coor4inates).

HOTE
This function "erases" any data contained in
the
region
status
region but
leaveD
the
Dtatus
implementation in effect.

The required input for this function is as follows:
AH

4.10.13

= 13H

(function number)

Clear Graphics Screen(s) - AH

= 14H

This function clears the graphics screen.
Required input for this function is as follows:
AH

4.10.14

= 14H

(function number)

Set TTY Status Region

Begi~ning

- AH

= 15H

This function specifies a beginning line on
the
screen.
The
text
from
this
beginning line to the end of the screen is considered the
status region.
This fucnction can define a status region of
one
or
more lines.
This region remains in effect until it is reset.
During
TTY writes,
this area remains intact and everything above this line

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

scrolls as necessary.
should:

In order to

vrite

to

this

area,

the

user

1. Read and save the current cursor position.
2. Locate the cursor vithin the status region.
Use one of the
vrite).

3.

vrite

character

f"nctions

(not

the

TTY

4. Restore the cursor to its original position.

Required input for

this function is as follovs:

CH = (f (must alvays be zero)
CL = Start line of status region
(Valid values are 0 through 24.)
A value
of
zero
(0)
for
the start line resets the status region
implementation.
The- start line must be
a
line after
the
curre"nt
cursor position, or no status region is implemented.

(

\

4.10.15

Set Attribute(s) - AH = 16H

This
function provides an alternate method vith vhich to control the
folloving attribute(s).

*
*
*

Reverse/normal video

"It

Underline

*
*

Blink

Intensity levels 1, 2, and 3 (blue,

red, and green)

Character enable/disable

Alternate character set

This function sets the
specified attribute(s)
into
the attribute
latch,
and
subsequent
characters
vritten to the screen assume the
attribute(s).
Combining this function vith a Krite Character (either
block or single) at Cursor Position (AH=OAH) function
has
the
same
effect
as
the Kr.ite Character/Attribute (either block or single) at
Cursor Position (AH=09H) function.
The attribute latch
remains
set
to the attribute specified in register SL.
Although more than one attribute can be used, certain combinations do
not
make
sense.
For instance, if the character enable attribute is

4-31

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

se t t a a zero, then the charac t er vi 11 no t appear nor vi 11 any of the/-other attributes except for reverse video.
The required input for

this function

is shovn in Figure 4-3.

BL = Attribute(s) to set
(BL is used to distinguish this function from the change screen attributes
function).

Intensity level 1 (blue)
Intensity level 2 (red)
Intensity level 3 (green)
Character enable (second dominant)*
Reverse video (first dominant)*
Underline
Blink
Alternate character set
* The user can specify more than one attribute. For instance, it is possible to have reverse video with an underlined, blinking, red,character. The user can mix the intensity (color) bits for different intensities
or colors for a given character.
2223216-24

Figure 4-3

Byte Definition - Set Attribute(s)

4-32

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

4.10.16

Get Physical Display-Begin Pointer - AH = 17H

This function is used to return the physical display-begin pointer to
an application.
Logically, the display-begin pointer
is
alvays
at
0,0,
but
there
is
a physical address (offset) associated vith the
beginning of the display that changes from time to time as the screen
is scrolled, cleared, or othervise
changed.
This
routine
returns
that
offset
address
relative
to the CRT memory area vhose segment
address is DEOOH.
The screen memory is a 2K-byte contiguous block of
RAM.
Once the starting location
of
this
block
is
knovn
to
the
application,
any
character
on
the
screen
can
be accessed.
For
example,
the
last
character
on
the
screen
is
located
at
(DEOOH: di~play-begin
+2~00)
and
the
eightieth
character
on the
screen
(to~li~e,
last-character
on
the
line)is
located
at
(OEOOH:display-begin
+ SO).
This returns the display-begin pointer
as follovs:

ox

= 16-bit

Example:

display-begin pointer (offset)

ox

=

O.implies that the first character on the
display resides in memory location DEOO:OOOOH

ox

=

150H implies that the first character on the
display resides in memory location DEOO:0150H

,(
\

4.10.17

Print TTY String - AH = 1SH

With this
function,
the
user
can
have
a
contiguous
string
of
characters,
of
a
given
length,
located
in
a code segment to be
printed (starting at the current cursor position) in a
TTY fashion.
As
vith
the
Write TTY function, this routine executes the control
characters CR, LF, BS, and BEL and scrolls the screen if necessary.
Required input for
BX

= Address
Where:

*

this function is as follovs:

(offset) of the string*
(BX) byte 0
(BX) byte 1

= length of the string
= first character of the

string

The user's code segment address is obtained from the stack
and therefore does not need to be passed as a parameter.

4.10.18

CRT TTY Mode Behavior

The folloving is a brief description of the behavior of the CRT vhen
used
in
the
TTY mode
as
veIl as its behavior vhen being used in
»mixed" modes.
The user
should
read
this
information
carefully,
especially if the user mixes non-TTY functions vith TTY functions.

4-33

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

Internally,
the
CRT DSR
implements
a "phantom" column 81 on each
line, which is actually column
1
of
the
following
line.
This
"phantom"
column
occurs
when a
TTY write puts a character in the
eightieth column of the current line.
If a
carriage
return
«CR»
command
is issued at this point. the cursor moves from the column 81
of the current line back to column 1 of the current
line.
However,
if
the
cursor
is in column 81, reading the cursor position returns
(current line + 1, column 0), instead of (current line,
column
81).
The
user must be aware of this before attempting to restore a cursor
position which logically came from column 81, because the Set
Cursor
Position
function
has
no
concept
of a
column 81.
This concept
disturbs the TTY mode and it restores the cursor
to a
new logical
position, that is, to column 1 of the next line.
Although the column
1 position has only one physical location, it can be interpreted as
two different logical lo~ations, depending on the current CRT action
(mode).
4.10.19

Ctistom Encoding of the CRT

It is possible for_ the user to custom encode the characters displayed
on
the CRT,
using the CRT "mapping" function.
This mapping allows
the applications first to intercept characters (and CRT actions
if
necessary) then to encode them.
Upon
entry
to
the CRT DSR, a sDftware interrupt is executed, which
points to an IRET instruction.
An application program can
reprogram
the
IRET to intercept calls to the CRT DSR.
The program can thereby
"take over" the CRT.
This
is
the
typical method. used
to
remap
characters
to the screen.
For instance, this feature can be used to
scan through a table, converting English characters to characters
in
some other
language.
Another u~e is intercepting "function calls"
(such as scroll
or attribute handling)
so
that
the. application
program can custom encode CRT functions.
The user must be careful
when performing this operation, however, because it
is
possible
to
disturb the data structures of the CRT DSR.
NOTE
After finishing with this function, t~e user ~
restore
the
vector
to
its
original
value.
Otherwise, the system could "go away."

After the user enters his mapping routine, he can use
all
registers
except
ES,
DS,
and BP.
To use these registers, he must save them,
then restore them. upon exit.
Before using this mapping feature,
the
user must
look at the opcode in register AH to determine if it is a
write character request.
If 50, he must also preserve
register AH
and any
registers associated
with
the write
function contained
therein.
For example, to map all dollar
sign
symbols
($)
to
the
percent
sign
(~),
the routine monitors register AH on each call to

4-34

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

the CRT DSR.
If AH contains a W'rite character
opcode,
the routine
then
looks at
register AL.
If register AL contains 24H (the ASCII
code for "$"), the user changes that register to 25H (the ASCII
code
for
"~"),
then executes an IRET instruction, returning to the screen
W'ith the neW' character.
(The currency symbol returned depends on the
internation keyboard being used.)
All registers are preserved,
but
register AL has been changed.

4.l,l

DISK DSR

Table 4-7 describes
the disk. device
service routines (disk DSR)
supported by the Texas Instruments Professional Computer.
To access
a
function,
place the proper opcode in register AH, then execute an
INT 40H. -an -return, all--registers are preserved except W'here stated.
Table 4-7
Alb

Disk DSR Opcodes and

Fun~tions

..

£sU!!.

Description

OOH

Reset disk system
Return status code (for last operation)
Read sectors
Write sectors
Verify sector CRCs
Null operation
Verify data
Return retry status
Set standard disk interface table (OIT) for unit
Set OIT address for unit
R~turn OIT address for unit
Turn off diskette drive motors

OlH

02H
03H
04H
05H
06H*
07H*
09H*
09H*
OAH*
OSH*
*

These functions are primarily for the use of
ayatem-level aoftW'.re and ~tilitie.,

Input:

AH

= OOH

DUinui~

AH

= OOH

This function causes ·the disk system to restore
itself
to a
knoW'n
state.
The actions performed for each supported device varies vith
the reqUirements of the device and the device-dependent softvare.
In
general, the function causes the disk controller(s)
to reinitialize
before their next use.

4-35

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

4.11.2

Return Status Code - 01H

In pu t :

AH

=

01H

Output: AH = OOH
AL
Status code for last disk I/O operation
CF = 0 (No change)

=

Not
all
disk DSR functions
are
I/O operations
(this
one, for
instance).
A status is returned in AH for
each function,
but
the
status
of
the
last I/O request is always retained for later acces~
(via this function), if desired.

-

4.11.:3

Read Sectors

In pu t :

AH = 02H
AL = Number of sectors to transfer
CH = Cylinder·number
CL = Sector number
DH = Track (surface or side) number
DL = Drive number
ES:BX = Segment:offset of buff~r

output: AH

02H

= I/O

status code
(For more information, refer to paragraph 4.11.13.)
AL = Number of unprocessed sectors
ES:BX = Segment:offset of the last sector processed*

This function reads data from the disk.
Any number o~sectors can be
transferred subject to memory boundary limitations (The segment's 64K
boundary and disk boundaries cannot be crossed.)

*

"Last sector processed" means exactly tbat.
Even if the
in error, .the data is transferred to memory.

4-36

read

was

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

4.11.4

Write Sectors -03H

Input:

AH
03H
AL
Number of sectors to transfer
CH
Cylinder number
CL = sector number
DH
Track (surface or side) number
DL
Drive number
ES:BX = Segment:offset of buffer

=
=
=
=
=

= I/O status code
(For more information, refer to paragraph 4.11.13.)
AL = Number of unprocessed sectors
ES~B~ ~ segment:~ffset of the last sector processed*

output: AH

This function vrites data to the disk.
Any number of sectors can be
transfered subject to memory boundary limitations.
(The
segment's
64K boundary and disk boundaries cannot be crossed.)

*

"Last
sector processed" means exactly that.
If the vrite is in
error, ES:BX ltiintsto the data vhich
the DSR is attempting
to transfer.

4.11.5

Verify Sector CRCs - 04H

Input:

AH = OQ
AL = Number of sectors to transfer
CH = Cylinder number
CL = Sector number
DH
Track (surface or side) number
DL
Drive number
ES:BX
Segment:offset of buffer

=
=

output: AH

=

=

I/O status ccide
(For more information, see paragraph 4.11.13.)
AL = Number of unprocessed sectors
ES:SX
Segment:offset of the last sector processed*

=

This
function verifies
the CRCs of the specified sectors.
Because
this function is handled like an I/O function,.ES:BX must be set as
though a
transfer
is
to
take place although no data is actually
transferred.
Any number of
sectors
can be processed subject
to
memory boun~ary limitations.
(The segment's 64K boundary and disk
boundaries cannot be crossed.)
* "Last sector processed" has little meaning
in
this
this function does not actually transfer data.

4-37

case

because

TECHNICAL REFERENCE

4.11.6

DEVICE SERVICE ROUTINES

Null Operation - OSH

This function ig not currently supported.
4.11.7

Verify Data - 06H

Input:

AH
06H
AL = Number of sectors to process
CH = Cylinder number
CL
Sector number
DH = Track (surface or side) number
DL = Drive number
ES:BX = Segment:offset of buffer

=
=

output: AH = I/O status code
(For more information, see paragraph 4.11.13.)
AL = Number of unprocessed sectors
ES:BX = On error, segment:offset of KORD in error
This
function verifies disk data against data in memory.
Any number
of sectors can be processed subject to memory boundary limitations,'
(The segment's 64K boundary and
the disk boundaries
cannot be
crossed.)
4.11.8

Return Retry status, - 07H

I npu t :

AH

Output: AH
AL

=

07H

= OOH

= Soft

error status of last I/O operation

This function is similar to the Return status Code function.
It
returns
the
"soft" error status of the last operation.
Soft error
referg to an error that did not recur whea the
la~t
o2eration was
retried.

4-38

'DEVICE SERVICE ROUTINES

TECHHICAL REFERENCE

4.~~.9

Set Standard Disk Interrace Table - 08H

Ine ut :

AH
AL
DL

outeut: AH
(Note:

= 08H
= Standard
(Valid
Diskette
=

DIT number
values are 0 through 3. )
drive number
(Valid values are 0 through 3. )

= Error

status
(For more information, see paragraph

4.~1.13.)

This function is used by the operating system softyare.)

Disk
interface
tables
(DITs)
are data structures containing
information that
the device-dependent part
of
the
DSR uses
to
interface Yith the device-dependent code for a specific disk device.
With this function, the user can set a diskette drive to one of four
standard configurat~~ns by setting the drives's DIT.
The
standard
DIT numbers are defined as folloys:
Humber

Description

-------------------0
1
2
3

4.11.~O

I neu t :

Single
Double
Single
Double

sided,
sided,
sided,
sided,

48
48
96
96'

tpi,
tpi,
tpi,
tpi,

8
8
8
8

sectors/track,
sectors/track,
sector!l/track,
sectors/track,

512-byte
S'12-byte
512-byte
512-byte

sectors
sectors
sectors
sectors

Set DIT Address for Drive - 09H
AH
DL

ES:BX
outeut: AH

= 09H
= Disk drive number
(Valid value is
= Segment:offset of
= Error status

o through 7.)
DIT for drive

(For more information, see paragraph 4.11.13.)
(Note:

This function is used by the operating system softyare.)

Disk
interface
tables
(DITs) are data structures containing
information that
the device-dependent
part
of
the DSR uses
to
interface Yith the device-dependent code, for a specific disk device.
Kith this functio",
the user
can set any disk to a nonstandard
configuration.
The disk drives are dynamically linked to the
system
by this mechanism.

TECHNICAL REFERENCE

4.11.11
Input:

Return DIT Address for Drive - OAH
AH
DL

output: AH
ES:BX
(Note:

DEVICE SERVICE ROUTINES

=

OAH

= Disk

drive number
(Valid value is 0 through 7.)

= Error status
(For more information, see paragraph
= Segment:offset of DIT for drive

4.11.13.)

This function is used by the operating system software.)

Disk
inLerface
table~
(DITs)
are data structures
containing
information that the device-independent
part
of
the
DSR uses
to
interface with the device-dependent code for a specific disk device.
With this function, the user can access a drive's DIT for information
and verification purposes.
4.11.12
Input:

Turn Off All Diskette Drives - OSH

AH

output: AH
ES:BX
(Note:

= aSH
=0
= not

preserved

This function is used by the operating system software.)

During regular operation, the diskette drive motors are left ON for a
short
period following a read or write operation, there~y saving the
time the motor would use to come up
to
speed.
Some applications,
notably diagnostiCS,
require assurance
that
the motors are not
running.
4.11.13

Status Codes

All functions return a status code in register AH and an error
flag
in
CF.
If
the
carry condition is set (CF = 1), then an error has
occurred and AH contains the error code.
If the
no-carry condition
is
set
(CF = 0), no error has occurred and AH contains a zero.
The
error codes are given in Table 4-8.

4-40

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

Table 4-8
Value
OOH
80H
40H
20H
10H
08H
04H
02H
01H
03H
-_OSH.
09H

4.11.14

Error Codes

Description
No error
Time-out - drive not ready or hardware failed
Seek failed - track not found
Controller hardware failed
CRC error
Data request error - controller failure
R~cord (sector) not found
No data - bad disk format
Command error - bad opcode or parameter
Disk write protected
Data ~_id not verify
I/O transfer crosses 64K byte boundary

Disk Interface Tables (DITs)

The Disk Interface ·Table(DIT) structure
interfaces
code with the generalized disk driver code.

,/
\

Because
in ROM.

DITs

contain read-only data exclusively,

The structure of a DIT is shown in Figure 4-4.

4-41

device-specific

they can be placed

TECHNICAL REFERENCE

~.~-

OEVICE SERVICE ROUTINES

16 bits

- - - !..~

Long pointer to disk interface routine

OOH
DITDIR

02H
04H

Sector size in bytes

DITSEC

06H

DITTRK

DITCYL

Track size in sectors; cyclinder size in tracks

OSH

DITDSK

DITERR

Disk size in cylinders; error retry limit

All other fields depelld on- the code
requirements of the specific device.
A.

General DIT Structure

......~--16 bits - - - !..~

DOH

Long pointer to diskette interface routine
FLPDIR

02H
04H

Sector size in bytes

DITSEC

06H

DITTRK

DITCYL

Track size in sectors; cyclinder size in tracks

OSH

DITDSK

DITERR

Disk size in cylinders; error retry limit

OAH

PRCOMP

Threshold track number for changing··
write precompensation
B.

Diskette Drive DIT Structure

Figure 4-4

OIT structure

4-42

. 2223216-26

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

The following procedure shows how to set up the disk DSR in order
to
access
a
flexible
disk
(floppy)
with a
"nonstandard"
format.
("Nonstandard" is a format that usually is not supported by the Texas
Instruments Professional Computer.)
MOV
MOV
INT
LES
MOV
MOV



MOV
MOV
MOV
MOV
INT

Set "return DIT address" opcode
Any floppy disk unit (0 - 3)
Call disk DSR
Es:ax .
address of floppy code
Put address of floppy-specific
code in your own DIT

AH, OAH
OL, 
4DH
ax, ES :( D5oiORD PTR [ax)
+O,aX
+2,ES

ES,SEG
ax, OFFSET
AH,9
DL,
40H

-

00 whatever else you need

EX:BX

=

to your OIT

address of your DIT

Set "SET OIT ADDRESS" opcode
Unit number
Call disk DSR

NOTE
The floppy-specific code comprehends only doubledensity (MFM) recording format.
It does not kno~
how
to
access
single-density
(FM)
recording
format diskettes.

4-43

TECHNICAL REFERENCE

4.12

DEVICE SERVICE ROUTINES

KEYBOARD DSR

This
subsection describes
the
keyboard
DSR and the functions it
provides to the system or application programs that use it.
It
also
shows
the
various
codes
returned
by
the
DSR
for
the standard
configuration of the keyboard.
The keyboard DSR functions are located in
the
system ROM and
are
accessed
through
the 8088 software interrupt mechanism (essentially
an address-independent subroutine call).
The
typical
user
of
the
keyboard
DSR
is
the
system
interface
code
(the
SIOS).
Each
operating:system-dependent SIOS resides
on
a
particular
operating
system diskette and is loaded into RAM during disk boot.
The
fUnctions
described
in this subsection access a buffer that is
controlled. by the keyboard interrupt service routine.
All
encoding
and any special handling (described in subsequent paragraphs) occurs
in the
interrupt
service
routine.
All
discussions
of
keyboard
mapping
vectors -refer
to actions occurring during the servicing of
the keyboard hardware (not software) interrupt.
Placing an opcode in register AH and executing an IKT 4AH chooses the
desired function.
All
registers
except
AX are
preserved.
The
functions
of
the
keyboard
DSR are
described
in
the
following
paragraphs.
4.12.1

Initialization Logic

The code for this function is automatically executed during
power-up
or
reboot
and
is not directly available to the user.
It performs
diagnostics on the
keyboard
hardware,
sends
to
it
the
required
initialization
sequences,
and
initializes
the
DSR
internal data
areas.

4.12.2

Read Keyboard Input - AH

=0

This function reads and removes the current character (if
any)
from
the keyboard buffer.
The character value is returned in register AX.
If
no character is ready, the DSR waits until one is received before
it returns to the caller.
This
character
has
already been
fully
encoded
(Table
4-10 lists the ASCII codes.)
Typically, the encoded
ASCII character is returned in register AL, and register AH
contains
00.
If AL = 0, then the coded value in AH corresponds to one of the
various function keys.
(Table 4-11 lists the non-ASCII codes for the
function keys.)

4-44

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

4.12.3

Read Keyboard Status

AH

=1

the
keyboard
This function determines that a character is ready at
but
does
not
actually read
it.
If no character is ~aiting, it
returns ~ith the
Z-flag set
(ZF = 1) ..
If
the
Z-flag
is
reset
(ZF = 0),
a
character is available to be read.
The character value
is returned in AX, but is not removed from the keyboard buffer.
4.12.4

Read Keyboard Hode

AH

=

2

This function determines the current mode of the keyboard.
The mode
value
is
returned in register AL in the format sho~n in Figure 4-5.
The definition of the byte is as follo~s.

Reg AL
1

= CTR L key depressed

1 = ALT key depressed
1

=

S H I FT key depressed

1 = Last key was result of
repeat-action sequence

\.

000

(always zero)

1 = CAPS LOCK key depressed
2223216-26

Figure 4-5

Byte Definition - Keyboard Modes

4-45

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

Because the
"mode"
applies
to
the
last
character
typed and
noY
necessarily to the one at the front of the queue. this function return.
valid
lnformation
only
if
the
keyboard buffer contains one ~r less
characters.
In order to use thlS function. read the key normally. then
make a status check to ensure that
the
buffer
1S
empty.
When
the
buffer is empty, the mode reading will be valid.
Use
this
function
only if it is necessary to know the state of the
mode when the last character was typed.
See
the
section
entitled
"Custom Encoding of
the
CRT"
in Section 4 for an explanation of
remapping the keyboard.

4.12.5

Flush Keyboard Buffer

AH

This function is used to
"flush"
buffer.
It
simply resets
the
empties the buffer.

4.12.6

Keyboard output

AH

=

3

(empty)
the keyboard
type-ahead
queue pOinters, which effectively

=4

This function sends the keyboard
command
in AL directly
to
the
keyboard,
with appropriate handshaking.
On return, the Z-flag has
the status of the operation.
If
the
Z-flag
is
set
(ZF=l),
the
command was performed correctly; otherwise (ZF=O), an error was made.
The keyboard commands sent by the CPU are given in Table 4-9.
Table 4-9

Keyboard Commands

Register
AL

Function
Performed

00

Performs a power-up reset and
installs default par~meters
Turns repeat-action feature ON
Turns repeat-action feature OFF
Locks the keyboard
Unlocks the keyboard
Turns keyclick ON**
Turns keyclick OFF**
Resets
Returns keyboard ROM version

01*
02
03

04*
05
06*
07
08

* Indicates the default value.
** Keyclick requires a hardware modification.
(It is not presently supported.)

4-46

~

'DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

These commands are intended for "one-shot" use, to set the keyboard
mode at poYer-up.
Although they may be sent at any other
time,
the
overhead of receiving several commands can cause the keyboard to miss
fast
keystrokes.
There are other yays to implement these commands.
A CRT emulator program may be required to turn repeat-action
on and
off
in response to escape sequences from a host.
For example, if an
application
needs
to
set/reset
the
repeat-action mode,
or
to
lock/unlock
the keyboard
in
real
time,
these
functions
can be
programmed into a
keyboard mapping routine.
Refer
to paragraph
4.10.19.
4.12.7

Put Character Into Keyboard Buffer - AH = 5

This
function
places
the 16-bit value
in BX directly into the
keyboard buf-fer.
On retur-ll-, if
the
Z-flag
is
reaet
(ZF=O),
the
character
vas placed in the buffer (this is the usual case).
If the
Z-flag is set (ZF=l), it means that
the buffer vas
full
and
the
character vas
not
placed in the buffer.
(The character remains in
BX.)
Assuming that the buffer vas empty at the start,
and
that
no
keys on the keyboard have been pressed, a Read Keyboard Input (AH=O)
function call retrieyes this character.
Any 16-bit value
can b~
placed
into
the ~~ffer',
but
unless
the
user has some explicit
application that understands "strange" characters from the keyboard,
it
is recommended
that
only standard characters generated by the
keyboard be used.
The format for the characters is the same as
that
given in the Read Keyboard Input function.
To place a normal ASCII character into the buffer, make the function
call Yith the character value
in BL and zero
in
BH.
To place
function
keys
into
the buffer,
make
the
function call Yith the
extended function value in BH, and zero in BL.
(See Table 4-10 and
Table 4-11.)
This
function is useful Yhen a program needs characters to appear as
though they had been typed.
Tyo examples folloy.

*

An a~plication can disable
the
operating system printer
"echo"
feature
by
inserting
the appropriate
"echo off"
character
(~
~
for
MS-DOS)
into
the buffer during
initialization.
The
operating system sees
this as just
another key and turns off the echo.

*

Many operating systems lack a
chaining feature,
and
this
function
can provide
one.
Immediately before a program
terminates, flush the keyboard buffer, then place characters
s'imulating a
typed command
into. the buffer.
When
the
program
terminates,
the operating system takes over, reads
the keyboard tiuffer, and performs that command (yhich could
invoke a second program, thereby "chaining" programs).

4-47

TECHNICAL REFERENCE

4.12.8

DEVICE SERVICE ROUTINES

General Keyboard Layout

The outline of the keyboard and the key-position numbers associated
with each of the keys are shown in Figure 4-6.
The numbers
in
the
'upper
right-hand corner of the keys are the scan codes sent from the
keyboard.
These codes are used internally by
the keyboard DSR
to
encode a
key when pressed.
The mode keys
(marked ***) do not
generate a scan code.

2223216-27

Figure 4-6

General Keyboard Layout Showing Scan Codes

4-48

TECHNICAL REFERENCE

4.12.9

DEVICE SERVICE ROUTINES

Character Codes

Table 4-10 lists the character and extended function
codes
returned
by
the
keyboard
OSR.
The modes
are handled
internally by the
, keyboard OSR, and the returned code reflects
the mapping
shown
in
this table.
Table 4-10

Standard Keyboard Character Codes

-----~------------------------------------~--------------------

I Key #1

Normal

I

SHIFT

I CTRL

ALT

Comments

-------------------------------------------~----------~----~---

1

I
I
I
I
I
I
I
I
I
,

1
I
1

01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21

I
I
I
I
I
I
I
I 22
I 23
I 24
I 25
I 26
I 27
I - 28
I 29
I 30
I 31
I 32
I 33
I 34
I 35

I f5
I _£6 "
I f7
I f8
I f9
I flO
I f11
I f12
1

1

3F*lsf5
40 * I s f 6
41*15f7
42*Isf8
43*lsf9
44*Isf10
45*Isf11
46*lsf12
31 I-

I

2

32

1

3
4

I
I
I
J

I
I

I
I
J

1
I

I
I
I
I
I
I
I
I

I
I
I
I
I

33
34
5
35
6
36
7
37
8
38
9
39
0
30
20
= 3D
BS
08
60
:
3D
+
2B
SP. 20
HT
09
1
31

58*lcf5

62*laf5
63*laf6
5A*lcf7
64*laf7
5B*lcf8
65*laf8
5C*!cf9
66*laf9
50*Icfl0
67*Iafl0
08*lcfll
OA*laf.t1
09*lcf12
OB*laf.t2
2.1 ,
-- I altl
1 0
40 1 Fnul 03*1 alt2
I #
23 I
I alt3
1 $
24 I
I alt4
25 I
I alt5
I '"
I 1\
5E 1 RS
.tE 1 alt6
I 426 1
1 alt1
I *
2A 1
1 alt8
1 (
28 I
1 alt9
I )
29 I
I altO
1
5F I
US
IF I altI +
1 alt:
2B I
1 BS
08 1 DEL 1F I
1 N
7E I
I
I :
3D I
:
3D I pf.t
I +
2B I
+
2B 1 pf2
1 SP
20 I SP
20 1 pf3
IBktab OF*I HT
09 I pf4
I 1
31 I
1
3.1 I
~_9*Icf6

I
0
CR
4
5
9

2

30 I
00 I
34 I
35 I
39 I
20 I
32'

0
CR
4
5
9
2

30
00
34
35
39
20
32

I
I
I
I

0
CR
4

I
I
I

5

I

2

9

30
00
34
35
39
20
32

I
I'
I
I
I
I
I
I

6C*1
60*1
6E*1
6F*1
10*1
11*1
OC*I
00*1
18*1
19*1
1A*/
1B*1
1C*1
10*1
1E*1
1F*i
80*1
81* "
82*1
83*1

FS
F6
F1
F8
F9
F.tO
Fll
F12

-- I Back space
-- I
8C* I Numeric:

I
I
I
I
1

1
I
I
I
I
I
I
I
I
I
I
I
I
I
1
I
I
I
I

SD*I Numeric +
8E*1 Numeric SPACEI
I
SF*I Numeric TAB
I
1 Numeric 1
I
I (unused)
I
! Numeric 0
Numeric
ENTERI
I
I
I Numeric 4
Numeric
5
1
1
1
1 Numeric 9
I
I Numeric I
I Numeric 2

---------------------------------------------------------------

4-49

TECHNICAL REFERENCE

Table 4-10.

DEVICE SERVICE ROUTINES

Standard Keyboard Character Codes (Continued)
'/'

--------------------------------------------------------------1 Key #1

Normal 1

SHIFT

I CTRL

ALT

Comments

--------------------------------------------------------------36
37
39
39
40
41
42
43
44
45
46
47
49
49
50
51
52
53
54
55
56

57
58
59
60
61
62
63
64
65
66
67
68
69
70

7
9
6
3

37
39
36
2C
33
2E

7
9
6
3

37
39
36
2C
33
2E

7
8
6
3

t 4.0* sC-rt eA* cC-rt
sIns 28*
cIns
52*
sDel
53*
38*1 cDel
09
Bktab OF*I
HT
q
71
51 1 DC1
Q
77
57 1 ETB
W'
H
65
45 1 ENQ
e
E
72
R
52 1 DC2
r
74
54 1 DC4
T
t
79
59 1 EM
Y
Y
75
55 1 NAK
u
U
69
49 1 HT
i
I
6F
4F 1 SI
0
0
70
P
50 1 OLE
P
{
7B 1 ESC
5B
[
}
50
7b 1 GS
]
LF OA
LF OA 1 cLF
br
1
C-up 48* sC-up 98*lcC-up
ESC lB 1 ESC
ESC 'lB
61
A
41 1 SOH
a
73
s
S
53 1 DC3
64
44 1 EOT
d
0
46 1 ACK
f
66
F
47 1 BEL
g
67
G

C-~r

Ins
Del
HT

(Unused)
(Unused)
(Unused)
Numeric 7
Numeric 8
Numeric 6
Numeric
Numeric 3
Numeric
(Unused)
Right ArroW'
INS
DEL
TAB

37
38
36
2C
33
2E

74*laC-rt 4E*
29*1 aIns 2A*
39*1 aDel 3A*
09 1
11 1 altQ 10*
17 1 altH 11*
05 I altE 12*
12 1 altR 13*
14 1 altT 14*
19 1 alty 15*
15 I altU 16*
09 I altI 17*
OF 1 altO 18*
10 1 altP 19*
1B 1
1
10 I
I
75*1 aLF 4F*J ~ine Feed
1
1 (Unused)
84*JaC-up 49*1 Up A'rro~
1B 1
1 ESC
01 J altA 1E*1
13 1 altS IF*1
04 1 altD_20*1
06 1 altF 21*1
07 1 altG 22*1

---

--

---

1
1

II

---------------------------------------------------------------

4-50

'DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

Table 4-10.

Standard Keyboard Character Codes

(Concluded)

--------------------------------------------------------------Comments
ALT
SHIFT
1 CTRL
1 Key #1 Normal
--------------------------------------------------------------48
BS
08 1 altH 23*1
68
H
71
h
I
1
1

J
6A
6B
K
I
L
1
6C
/
3B
I
27
I
CR
CR
00
5C
1 \
I
1 C-lf 4B*lsC-lf
I Home 47*lsHome
I ~p 20 I SP
7A I
Z
I z
x
78
I
I X
63 I
C
I c
V
76 I
I v
B
b
62 I
I
N
6E I
1 n
60 I ,'M
I m
2C I
<
I
IPtogl 72*1 ***
2E 1 >
J
?
2F I
/

72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
9.1
92
93
94
95
96
97
98
99
100
101
.102
103
104

j

k

..

,

,
I
I

LF
4A
VT
4B
4C
FF
3A
22
00
CR
7C
FS
8B*lcC-lf
86*lcHome
SP
2Q
SUB
5A
58
CAN
43
ETX
56
SYN
42
STX
4E
SO
40
CR
3C
**
3E
3F

OA / altJ 24*1
OB I altK 25* 1
OC / altL 26*/

,I

00 1
lC 1
73*laC-lf
77*laHome
20 1 SP
lA / altZ
18 / altX
03
altC
.16 1 altV
02 I altB
OE 1 altN
00 I altM

,
I
1

I
I
I

I

1
1
1
1
I C-dn 50*lsC-dn 89*lcC-dn 76*laC-dn
1
I
I
1
1
1
1
1
I
I
1
I
I Ppau ** I Pbrk ** I
1
f.1
54*lcf.1
3B*lsf.1
5E*laf.1
I
55*lcf2
3C*Jsf2
5F*laf2
1 f2
3O*15f3
56*lcf3
60*laf3
1 f3
57*lcf4
61*laf4
I f4 3E*lsf4
1

I
1
1

I

I

1
1 Return

1

I
4C*/ Left Arro..,
85*1 HOME
20 / Space bar
2C*1
20*1
2E*1
2F*1
30*1
31*1
32*1

I
I PRINT
I
J

I (Unused)
I (Unused)
I (Unused)
51*1
1
1
1
1
68*1
69*1
6A*1
6B*1

Oo..,n Arro..,
(Unused)
(Unused)
(Unused)
BRK/PAUS
F.1
F2
F3
F4

I
I
I
I
I
1

I
I
I
I
I
1
1

I
I
I
I
I
1
1

,
J

I
I
I
1
1

I·

--------------------------------------------------------------Notes

1.

to Table 4-10:

Key

#

is shown in Figure 4-6.

2.
In
the
"Normal","SHIFT",
"CTRL",
and "ALT" columns, both the
"graphic" and the h.xadecimal values of the character
are
given
in
the form:
GGG HH.
Mnemonics are used for the "graphic" descriptions
of
the
function
keys.
These
are
generally self-explanatory:
a
leading a, s, or c indicates ALT, SHIFT, or CTRL, respectively.
For
example,
fl
is the Fl function key; afl is the Fl key pressed ..,hile

4-51

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

holding down the ALT key.
cLF = CTRL linefeed.

C-rt means cursor right

3.
Entries consisting of "--»indicate that
suppressed within the keyboard DSR.

(right arrow), and

the

combination

is

4.
Entries
consisting of "xxx **" indicate special handling in the
form of direct
action
by
keyboard
DSR.
(For
details,
see
the
paragraph 4.12.14.)
5.
Normal
(ASCII)
characters are returned in register AL with the
scan code key number in AH.
6.
Entries consisting of "xxx yy" are returned
indicated value (yy) in AH.

with

AL=O

and

the

7.
An asterisk after a number means extended codes, listed in Table
4-11.

4.12.10

Extended Codes

The "extended" codjs ar~ non-ASCII
codes.
They
represent
sp~cial
function
keys on the keyboard.
To distinguish these codes, register
AL contains 00 upon returning from a Read Keyboard
(AH=l
or
AH=2)
function
call,
and
the
extended code is in register AH.
The code
range (OOH through FFH) includes normal ASCII
codes.
The
extended
codes
are given in Table 4-11.
Use the mnemonics to cross-reference
with Table 4-10.
Table 4-11
MSD* I
0
I 1
LSD
o IPbrk laltQ
1
IPpau 'altW
2
I
~altE
3
IFnul laltR
4
I
laltT
5
I
laIty
6
J
laltu
7
I
laitl
a
Isfll laltO
9
Isf12 laltP
A
lefll I
B
Icf12 I
C
lafl1 I
o laf12 I
E
I
laltA
F
IBktablaltS

I

2

I

Funeti~n

Extended

3

J

4

I

5

I

Cod~s

6

I

7

I

a

I

1-----------------------------------------------------laltD laltB I f6
I C-dnl ef3 I af9 lalt9 I

*

laltF
laltG
laltH
laltJ
laltK
laltL

I
IsIns
Iclns
taIns
I
laltZ
laltX
laltC
laltV

laltN I f7
laC-dnJlaltM I fa
I Ins I
I
I f9
I Del I
I
, flO I sfl I
I
J fl1 I sf2 I
J
I f12 I sf3 I
I
I Hamel sf4 I
IsDel I C-upl sf5 I
IcDel laC-upl sf6 I
laDel I
I sf7 I
I fl
I C-Ifl efa I
I f2
laC-If I 5f9· I
I f3
I C-rt I sflOI
I f4
laC-rtl efl I
I f5
I aLF I cf2 I

cf4 laflO laltO I
cf5 IPtogllalt- I
ef6 leC-Iflalt= I
ef7 leC-rtleC-upl
efa I eLF laHomel
ef9 leC-dnlsHomel
cfl0leHomei
I
afl laltl IsC-upl
af2 lalt2 IsC-dnl
af3 lalt3 IsC-rtl
af4 lalt4 IsC-lfl
af5 lalt5 I pfl I
af6 lalt6 I pf2 I
af7 lalt7 I pf3 I
afe lalta I pf4 I

MSD = most significant digit; LSD = least significant digit

4-52

DEVICE SERVICE ROUTIMES

TECHNICAL REFERENCE

4.12.11

Keyboard Modes

In the standard keyboard, the mode keys have
the effect
shown
in
Table
4-11.
The latching
(push-push)
CAPS LOCK key affects the
alphabetic keys (50-59, 66-74, and- 82-88 on the standard keyboard) by
forcing
the SHIFT mode.
Normally
the alphabetic keys produce
lowercase characters, and the SHIFT key temporarily causes them to be
uppercase.
Khen the CAPS LOCK mode is invoked (the CAPS LOCK key is
latched down and the LED in the CAPS LOCK key lights), the alphabetic
keys produce uppercase and the SHIFT key has no further
effect
(on
the alphabetic keys).
In
the standard encoding, the only valid combination of mode keys is
CTRL/ALT/DEL,
which is
used for
system reset.
Simultaneously
pressing
the CTRL,
~,
and DEL keys results in the keyboard DSR
initiating- the equivalent of a system power-up reboot.
The action is
handled internally by the DSR and does not
return a
code.
This
function
is
"hardwired" and cannot be disabled.
In any other case,
when two or more mo~~ key~ are pressed simultaneously,
only one
is
recognized.
The order of precedence, beginning with the highest, is
as follows:
ALT,

~,

SHIFT, and CAPS LOCK

(
\

The ALT key has a special use, letting the user enter any character
code (OOH-OFFH) from the keyboard.
Khen the ~ key is held down and
the decimal value of the desired character is typed on t~e numeric
keypad with
three keystrokes,
the value
is
returned
to
the
application as a normal character directly through the Read Keyboard
Input (AH=O) function.
If fewer than three digits are
typed,
the
next non-ALT key struck sends the currently accumulated ALT/HUK value
(from
the first
one or
two keystrokes).
If the first one or tvo
keystrokes were the zero key, the next key pressed sends - its normal
character,
because
the zero
is
simply a "place keeper" and adds
nothing to the ALT/NUK value.
Pressing more than
three keys
sends
the accumulated value and starts a new three-keystroke sequence.
Example:
ALT 003 places the value for an ETX in the keyboard buffer.
ALT 3, followed by any non-ALT key performs the same function.

4.12.12

Type-Ahead Buffer

The DSR
implements a Circular type-ahead queue, which can buffer up
to 15 keystrokes.
(Each keystroke is 2 bytes.)
If
the queue
is
filled,
entering further
characters from
the keyboard sounds the
4-53

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

system beeper.
The Flush Keyboard Buffer (AH=3) function resets
queue pointers, effectively emptying the buffer.
4.12.13

the

Repeat-Action Feature

If
the
repeat-action feature
(the default) is enabled, there is a
half-second delay and all keys become repeat-action at a 15-cps rate.
Repeat-action
characters are
ignored vhen
the queue
currently
contains more
than one pending character.
This means that the
application does not have to vorry about the repeat-action "coasting"
problem.
That is, if the application does not
or
cannot
read
the
keyboard
input
faster
than
the
repeat-action rate, the. undesired
repeat-action characters are not queued and the keyboard does not get
ahead of the application.
4.12.14

Special Handling

These paragraphs describe functions
handled
by
the keyboard DSR.
Several of these require immediate reaction (for example, pausing the
output
routine so a fast-scrolling screen can be read).
Most of the
keyboard DSR functions are implemented vith
the
softvare
interrupt
facility of the BOBB microprocessor.
Each of the defined interrupt vectors points to some default piece of
code
that
either
does
nothing
(for example,
a
single
IRET
instruction)
or performs
some system function.
An application
program can
change
these interrupt vectors in order to gain direct
access to a function.
Hovever, the application must
preserve
the
original contents of the v.ctor and restore it before terminating and
returning to the system.
If the application routin~ is used, it must
end vith an IRET or the equivalent (FAR) RET 2, vhich allovs flags to
be passed.
The stack used
is
the
internal
stack of the keyboard interrupt
service routine and only 10 levels (20 bytes) of stack are available
to the user's routine.
Interrupts are disab:t..ed vhen the .us.!r routine
is entered (by the IHT instruction).
Interrupts should be re-enabled
immediately unless
it
is necessary for
them to remain disabled.
Registers AX, ax, CX, 01, and ES can be used (information
is passed
in AX);
any others must be preserved.
When the available stack is
too small, the routine must svitch to an internal stack of sufficient
size (including B bytes for possible interrupts).
Also, the
routine
is
executed as a
part
of the keyboard interrupt s~rvice routine,
vhich means that no other keystroke~ are accepted until
the
user
routine finishes and returns.
The normal vay to communicate vith the
outside vorld
(outside
the
service
routine) is to set a flag and
vatch for it in the application.
This·, for example, is hov the BREAK
function is implemented in KS-DOS.
Control should not be retained by
the user's routine unless a complete system initialization is
to be
performed.

4-54

. DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

4.12.15

User-Available Interrupts

The folloving
is a summary of the softvare interrupts (performed by
the keyboard DSR) that can be
used by application programs.
The
interrupts are presented in their order of execution.
The number in
parentheses,
the
"interrupt
type,"
is
used
in
an
interrupt
instruction.
The absolute address of the corresponding vector. is the
interrupt
type
times 4.
As an example, the address of the keyboard
mapping vector is SBH x 4
16CH.
Any of the special key interrupt
functions
can be bypassed by re-encoding the key code.
For more
information on the key code, refer to paragraph 4.10.19.

=

The keyboard DSR interrupts and their

mappi~g

vectors are:

*
*

Keyboard mapping (5BH)
Program pause (SCH)

*

*
*
*

Program break (SDH)

*

*

These interrupts occur after internal encoding.

Print screen (5EH)

*

Keyboard queueing (SFH)

4.12.15.1 Keyboard Mapping.
This interrupt is performed each time a
key is pressed but before it is encoded, alloving the user to
encode
the key.
When the user encodes the key, the DSR places the key code
in the queue and performs
the keyboard queuing
(SFH)·interrupt.
Othervise,
the DSR encodes the key, checks for the special keys, and
then queues the key code, causing
the keyboard queuing
interrupt.
For more
information on using this interrupt to remap the keyboard,
refer to paragraph 4.10.19.
4.12.15.2 Program Pause.
Pressing
the
(unshifted)
BRK/PAUS key
causes a softvare interrupt and allovs the user to perform an action
or return a key code.
It returns an extended code
(refer to Table
4-11) to the caller if desired.
At system pover-up, the vector is
set so that the ~ key sequence causes a screen hold, vhich stops a
fast-scrolling
screen.
An application program can change
the
interrupt vector in order to support a pause function of its ovn, but
the program is
responsible for remembering the original vector and
restoring it before terminating.
The carry flag determines the action of the keyboard
DSR on
return
from
the softvare interrupt.
If the carry flag is set, the DSR does
nothing else and simply exits.
If the carry flag is reset, then
the
character value in AX is placed into the queue.
Before the softvare
interrupt is executed, the carry flag is reset and the extended
code
4-55

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

for
the program pause function is placed in AX.
Therefore, if an
IRET instruction is used to return instead of the default
ROM pause
routine,
the DSR returns
the program 'pause function code to the
application.
Because the carry flag is used to pass information, the
IRET instruction must be simulated vith a (FAR) RET 2
if
the
user
needs
to
return vith
the carry flag set.
(The IRET instruction
restores flags to their pre-interrupt state.)
4.12.15.3 Program Break.
Pressing the (shifted) BRK/PAUS key causes
a softvare interrupt and allovs the user
to perform an action or
return a
key code.
It can be set to return an extended code (see
Table 4-11)
to
the
caller,
if
desired.
During
pover-up
initialization,
this
interrupt
vector
is
set to point to an IRET
instruction so that the
BRK key sequence
is
ignored other
than
returning
the break code.
An application program can change the
interrupt vector in orde~ to support a break function
of
its
own.
Hovever,
the program is
responsible 'for preserving the original
contents of the vector and restoring it before terminating.
For more
information on
the
encoding/softvare-interrupt
technique,
see
paragraph 4~12.15.
4.12.15.4
Print Screen.
Pressing
the SHIFT and PRNT keys causes
another softvare iriterrtipt.
The user can perform an action or return
a key code.
This interrupt normally vectors to an
IRET instruction
vithin
the ROM.
The DSR checks
the carry flag upon return, as
described in paragraph 4.12.15.
The carry flag is set before the interrupt is executed, so that
vhen
the routine consists only of an IRET, the key is effectively ignored.
This
can be (and is, by the KS-DOS SIOS) patched so that it vectors
to an actual print screen routine.
This routine executes as a
part
of
the keyboard interrupt service routine ~nd, ~herefore, cannot b~
interrupted by another keystroke.
The preferred vay
to handle
the
Print Screen function
is
to use this interrupt to start the Print
Routine
(in
the background)
then return
immediately,
thereby
reenabling the keyboard.
4.12.15.5
Keyboard Queueing.
This softv&re interrupt. occurs every
time a character, vhether encoded by the DSR or by
the
user,
is
placed
in
the type-ahead buffer.
This interrupt lets the real-time
OS knov vhen there is a character to read.
The user can choose
to
ignore
the key
(not
queueing
the keycode).
Refer to paragraph
4.12.15 for keyboard queuing interrupt conditions.
4.12.16

Custom Encoding

An applicat'ion program can encode the keyboard using
this
function.
Each time a key is pressed on the keyboard, the keyboard sends one or
tvo key codes
to
the DSR.
The mode keys are handled internally.
(For more information, refer to paragraph 4.12.17.)
The DSR performs
a softvare interrupt each time it receives a key code (not
including
the mode keys).
Normally
the
interrupt vector points to an IRET
instruction.
An application program can reprogram
the .vector
to
4-56

~­

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

intercept
the~e
key codes.
Because everything comes through this
vector, the application can take control of everything but the system
reset combination (CTRL/ALT/DEL).
The routine
that
intercepts
the
key codes
typically scans through some tables to encode its special
keys, then executes a (FAR) RET 2 instruction.
NOTE
It is essential that the application restore
the
vector
to
its
original value after completion.
Othervise, the system vill crash vhen the special
encoding routine is later vritten over.

When the softvare interrupt is performed (from the keyboard ISR)
the
keyboard
scan
code
(including the repeat-action bit, if set) is in
AL, the mode byte is in AH (the mode byte is shovn in figure
) and
the carry flag is set (CF=~).
If the carry flag is reset (CF=O) vhen
returned
from the interrupt, then the standard encoding is bypassed.
Instead, the values in AL and AH are placed directly into
the
typeahead buffer.
This-Is on~ vay to change the standard encoding of the
keyboard.
If
the carry flag is set, and the value of AL is returned as OFFH,
the keystroke is ignored entirely,
and nothing
is placed
in
the
buffer.
This can be used vhen the special handli~g routine performs
some function directly and does not need to send a
character.
The
repeat-action
bit is included in the scan code as the high bit of AL
and in the mode byte as bit 3 of AH.
The user can choose vhich of
the tvo is more accessible to his particular routine.
If
the
scan code is used in a table look-up or a direct comparison,
the user must
strip off
the
(possible)
repeat-action' bit
(the
instruction
is AND AL, 7FH).
Because this is a softvare interrupt,
the IRET instruction must be simulated vith a (FAR) RET 2 in order to
pass flags back.

4.12.~7

Keyboard Interface Protocol

Pressing a key on the keyboard sends a' byte
representing
the key
position
to the keyboard DSR.
If the state of the mode keys (SHIFT.
ALT, CAPS LOCK, and CTRL) has changed since the last
keystroke,
the
key-pOSition byte is preceded by a byte shoving the current status of
the mode keys.
The mode byte is never sent alone.
It vill alvays be
folloved by, the key-position byte.
The mode byte
is
never
sent during a repeat-action transmission,
because it is sent only if
the mode has
changed
since
the
last
transmission.
The mode
cannot
change during
the
repeat-action
function.

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TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

The second byte (key position) contains a repeat-action key bit
(bit
7).
This
bit
is set to ~ during a repeat-action key transmission,
and reset to 0 during a non-repeat-action transmission.
If
the
key
is
still pressed after a half-second delay, the code is sent again,
this time vith bit 7 set to 1.
The keyboard remapping
routine
uses
this bit to suppress the repeat-action key function vhen necessary.
All communication vith the keyboard is:

*

Asynchronous

*
*
*

Serial

*

Even parity.

8

data bit

1

stop bit

The keyboard transmits its data at 2440 bps and receives its commands
at 305 bps.
Both bytes have
similar formats, as shovn in Figure 4-7.
Hovever,
bits 3 through 6 of the mode key status byte are all set to 1.

4-58

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

181716\5141312111

0

I

\

FIRST BYTE (Not always sent)
Control
Alternate
.Shift

=

1111 (denotes first byte)

Caps lock (uppercase)
-- --.

Parity

--

SECOND BYTE

Scan code
Repeated character
(repeat-action keys)
Parity
2223216-28

Figure 4-7

Byte Definition - Keycode

4-59

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

The keyboard
understands
several
commands,
as
explained
in
the
Keyboard
Output
(AH=4)
function,
and
the keyboard generally
acknowledges each command.
The codes sent by the keyboard (refer to Tables 4-10 and 4-11)
range
from scan code 01 through scan code 104 (OlH through 68H).
The spare
scan
codes
(from 69H through 6FH) will possibly be assigned in the
future.
If so, the size of the standard encoding tables will also be
increased.
Codes 70H through 73H are status codes
returned by
the
keyboard
in response to commands.
Codes 74H through 77H are unused
but reserved, and codes 78H through 7FH are for encoding the mode key
status byte.
For more specific information, refer to
the paragraph
entitled
"Receiving and responding to commands from the system unit"
in Section 2.

4.13

PARALLEL PRINTER PORT DSR

The following paragraphs describe the functions
that
the parallel
printer p~rt DSR provides to the system or application programs that
use it.
The printer DSR provides routines
to
implement
a
Centronicscompatible parallel port
interface.
The
user
is able to output
characters, get printer status, and initialize the printer.
The printer DSR functions, located in the system ROM,
are accessed
through
the ·software interrupt mechanism of the 8088 microprocessor.
To choose a function, place the opcode in register AH, place zeros in
register DL, and execute an IHT 4BH instruction.
(For an e~planation
of register DL, see paragraph 4.13.4.)
All r~gist~rs are preserved
except AH,
which always
returns
with. the printer status.
(See
paragraph 4.13.3.)
The functions available are:
output Character to Printer (AH=O, DL=O)
Initialize Printer (AH=l, DL=O)
Return Printer Status (AH=2, DL=O)
4.13.1

output Character to Printer

-

'AH = 0, DL = 0

This function sends the character in AL to
the printer port.
The
BUSY signal from the printer is checked before sending the character.
If the printer is still busy after approximately 0.33 s, the DSR sets
the
time-o~t
bit
in
the
status byte (in AH) and returns.
If the
printer is not busy, the DSR returns with
the
time-out
bit
reset.
Any unusual conditions on the status signals from the printer cause
the printer to go BUSY.
Time-out also occurs
if
the printer
sets
FAULT,
PAPER OUT,
or NOT SELECT.
The printer can also set BUSY,
causing a time-out.

4-60

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

It generally is not advisable to rely on the time-out of the printer
output routine during regular use, especially if one is using the DSR
from the printer task of a real-time OS.
This time-out is a softvare
loop and causes the application to "hang" during the time-out period.
The preferred method has
the application vatching the BUSY signal
through the printer status call so that the application can implement
'and control a time-out.
The standard sequence used to print a character is:
REPEAT
Interrupt 4BH vith AH
2 and DL
"Return Printer status."
UNTIL
STATUS = HOT BUSY
EHD

=

INTerrupt 4BH vith AH
IF STATUS
(time-out)
THEN

END

=

= 0,

DL

=0

=0

and AL

(see paragraph 4.13.3,

= 

(FAULT or PAPER OUT or (HOT SELECTED»

Hote:
Refer to Figure 4-8 for byte definition of the
Return Printer Status function.
4.13.2

Initialize

Pri~ter

AH

= 1,

DL

=

0

This function activates the IHIT signal on the interface causing
the
printer
to perform the equivalent of a pover-up reset.
The specific
action taken is printer-dependent (refer to the appropriate printer
manual).
The
system softvare activates this signal only once, at
actual system pover-up (not on system reset CTRL/ALT/DEL).
4.13.3

Return Printer Status

AH

= 2,

DL

=

0

This
function
reads
the printer
status port and
returns
the
information
in
register AH.
This is the same information as that
returned after the Output Character to Printer (AH=O, DL=O) function,
and the Initialize Printer (AH=l, DL=O) function.
The bits of AH are encoded as shovn in Figure 4-8.

4-61

TECHNICAL REFERENCE

. DEVICE SERVICE ROUTINES

,,.------

I

7

I

6

I

5

I

4

1

3

1

2

I

1

I ,0 I
I

Time Out (on busy)
(not used)
Busy
Paper Out
Selected (online)
Fault
2223216-29

Figure 4-8

4.13.4

Use Under

Byte Definition - Return Printer Status

a~' Oper~ting

System

Mhen the software interrupt technique interfaces with ROM routines, a
interface
interrupt
DSR can be enhanced or replaced by patching its
vec t or.
Under
MS -DOS"
for
exampl e ,
the
ser i al
pr in t er s uppor t
emulates the parallel printer fun~tions of the ROM.
The printer interface is implemented by patching a small
routine
in
front
of
the printer
interrupt
vector.
This
routine
looks at
register DL to determine the desired printer.
If DL=O, a jump to the
ROM routine is made, and the user is unaware of the patch.
If DL=l,
AH is decoded
to perform
the appropriate function on, the serial
printer.
If DL = FFH, then the desired function is performed on
the
default (c~rrently configured) printer.
Because
the
serial
support
emulates
the _status
r~t~r~ed by the
parallel routines of the ROM, the user knows of
the
operation· only
because he
set
register DL.
Some operating systems do not require
that register DL be set.
In the case of MS-DOS, however, the DSR
is
extended
in a manner t~at requires the setting of DL.
Refer to the
documentation appropriate for the operating system in use.

4-62

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

4.14

WINCHESTER ROM

The Winchester ROM, on the Winchester controller board,
interfaces
vith
the system ROM softvare, specifically the system disk DSR.
The
Winchester ROM is addressed by the system processor.
Its address, as
determined by the hardvare, is OF8000H.
The convention
locates
the
ROM at the address (as seen by the softvare) of OF400:4000H.
In addition to the disk DSR software, the Winchester ROM contains the
software necessary to drive the 'Winchester controller, to boot up the
system from
the
Winchester disk,
to format the disk, and to run
diagnostics (both power-up and advanced) on the controller and disk.
After initialization, all regular operations of
the
Winchester ROM
(read, vrite, verify, and so on) are done through the disk DSR.
(See
subsection 4.11.)
4.14.1

Limitations

The DSR and
other
utilities provided by the system ROM limit the
used by
the
system.
The
types of Winchester drives that can be
limits are as follows:

*
*
*
*
*
*

X x Y cylinders per drive where 1 < X < 256 and 1 < Y < 15
16 surfaces per drive
17 sectors per track
512 bytes per sector
255 error retries
11-bit error-burst length

Host
of
the
routines
vithin the ROM are driven by data structures
that describe the type of drive.
The system is povered
up assuming
the following drive parameters:
153 cylinders
4 surfaces
125 first track of reduced write current
64 first track of vrite precompensation
1 error retry
11-bit error-burst length
3-ms step' option
If
the default
parameters are not correct for the type of drive in
use, an Initialize Winchester Disk System option call must be made to
install the correct parameters.
The system can boot the first sector
4-63

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

vith the default parameters.
4.14.2

System Interface

The Winchester controller board ROM is initialized to the system vhen
·it is called by the system ROM folloving the poyer-up self-test.
The
system ROM tests the Winchester disk controller ROM to make
certain
the
controller
is functioning properly before calling it.
To allov
the system ROM to test and call it, the Winchester disk
controller
ROM contains a header defining the ROM size, the entry point of the
ROM, a version number for the ROM,
and an
identification message
preceded by the message length.
The
entry point
called by
the system ROM is required to do any
device- de.pe.ndent initia_lization and, optionally, to boot the
system
from the device that the called ROM serves.
For the Winchester disk,
the operations are as follovs:

*

*

Set ·the RAM area of the ROM in the system.
Set the deviceinstalled bit in the system configuration vord.
This second
step permits the system unit to »sense» that the controller
is
install~d,
a~d,
under the diagnostics diskette Display
System Configuration test. to display all options
installed
in the system unit.
If

the

caller has passed the »do not boot flag" (OFFFFH in
OX), return control to the caller . .othervise (vith
o in register OX). the initialization sequence continues.

regi~ter

the

*

If the user has pre~sed the ESC key. control returns to
system ROM and the system boots from the di~kette.

*

Othervise.
display the Winchester disk controller ROM signon message and execute the controller's poYer-up tests.

*

Test all ROM~ that have a lover priority than the Winchester
disk con t roller ROM and then call them ~
The "do nQ t
boo t"
flag
(DX = OFFFFH) must be set so that the ROM can do any
required initialization of associated hardvare.

*

Read in
the boot
sector from
the disk,
check
usability, and jump to the code in the boot sector.

*

If any errors occur in the above area; control is returned
to the system ROM.

4.14.3

it

for

System RAM Usage

The Winchester disk ROM uses 30 byte~ of RAM in the sy~tem RAM area.
This RAM
is allocated a~ a contiguous block of memory only after
previously called ROMs have been allocated their RAM space.
This RAM
block is pointed to by a vord in the system vector area.
The data
4-64

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

structure of this vector area is given in Table 4-12.

Table 4-12

RAM Segment Pointers

User

Value

Address

0000:0190
0000:0192
0000:0194
0000:0196
0000:0199
0000:019A

System ROM U63
System ROM U63
F400:0000 ROM
F400:0000 ROM
F400:2000 ROM
F400:2000 ROM

RAM segment address for ROM
Length of RAM segment in bytes
RAM segment address for ROM
Length of RAM segment in bytes
RAM segment address for ROM
Length of RAM segment in bytes

F400:AOOO

0000:019C
0000:019£

Windisk ROM
Windisk ROM

RAM segment address for ROM
Length of RAM segment in bytes

F400:4000
(30H)

0000:0194
0000:0196
0000:0194
0000:0196

F400:6000 ROM
F400:6000 ROM
Option ROM U62
Option ROM U62

RAM segment address for ROM
Length of RAM segment in bytes
RAM segment address for ROM
Length of RAM segment in bytes

F400:6000

,Address

F400:0000
F400:2000

F400:eooo

All accesses
to the Kinchester disk controller RAM area are through
the segment pOinter at
OOOO:019CH.
Because
the, Kinchester' disk
controller ROM
is
located at
segment OF400H, the segment pOinter
location can also be
reached from
the code
segment
at
address
OF400:C1SCH.
The segment pointer alloys the Kinchester disk controller RAM area to
be located anyvhere,
but
care must be taken if the ar.ea is moved
after the system is initialized.
If this
is done,
the' Kinchester
disk
system must
be reinitialized vith the Kinchester disk option
call "0" (Initialize System) after the RAM area
is moved and
the
vectors are set tb the nev values.
To do this, pass the nev segment
address in OS and OOOCH as ,the pointer to
the
initialization data.
(See paragraph 4.14.19.1.)
4.14.4

Poyer-up Testing

To determine that the Kinchester disk controller is vorking properly,
it is tested by its ovn internal diagnostics and the RAM diagnostics.
Failures are
reported as system errors 11xx, vhere xx indicates the
error received.
If an error
occurs,
control
is
returned
to
the
system ROM.

4-65

TECHNICAL REFERENCE

4.14.5

DEVICE SERVICE ROUTINES

Booting from the Winchester.
~

After
the
po~er-up
testing of
the
controller
completes,
the
Winchester goes through the boot sequence.
Only drive 4 (E:
for MSDOS) can be booted.
If drive 5 is connected to
the
controller,
it
can be used for data only.
First,
the boot
procedure polls the drive for the ready condition.
If the drive is not ready (as ~ould be true after the po~er is turned
on), the ROM routines ~ait approximately 30 seconds
for
the
ready
condition.
If
the user presses the ESC key at any time during this
~ait,
control is returned to the system ROM, and the diskette drive
conducts the initialization boot.
4.14.6

Erro~

Recovery

The error
recovery procedures depend on the error.
For hard~are
controller errors
(time-outs),
the
controller
is
reset,
and no
retries are attempted.
A hard~are error code is returned from the
disk DSR.
For disk drive errors (seek incomplete, ~rite fault, and so
on),
no
retries are
reported,
and
the disk DSR returns the hard~are error
code.
Read Data operations have
t~o
types
of errors:
correctable and
uncorrectable.
If
the data is correctable, it is corrected, and no
error is reported directly.
A DSR Read Soft Retry Status
reports
this error.
For
uncorrectable errors, a "restore" is done betore each retry.
If
the retry does not succeed, the data buffer is filled; ~ith CCH ~hen
the data cannot be read at all, or ~ith the uncorrected data if the
data can be read but contains an ECC error.
For other operation errors, a "restore" is placed before each retry.

4-66

..

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

4.14.7

Error Reporting

The disk DSR is capable of reporting only a fev errors.
The pover-up
boot can report more but not all.
Table 4-13 is a listing of errors
reported by the disk controller and the codes reported by the DSR.
Table 4-13

Reported Error
20H
20H
20H
20H
20H
10H
10H
02H
04H
40H

Hardvare failure
Hardvare failure
Hardvare failure
Hardvare failure
Hardvare failure
CRC error
CRC error
Disk format error
Record not found
Seek error
No error (on RETURN)
CRC error (soft stat)
Command error
Disk format error
Command error
Command error*
Disk format error
Command error*
Command error*
Command error*
Hardvare failure*
.Hardvare failure*
Hardvare failure*

OOH

10H
01H
02H
01H
01H
02H
01H
01H
01H
20H
20H
20H
*

Winchester DSR Error Codes

Controller Error
01H
02H
03H
04H
06H
10H
11H
12H
14H
15H
19H
19H
19H
1AH
1CH
lDH
1EH
1FH
20H
21H
30H
31H
32H

No index detected
No seek complete
Write fault
DRIVE NOT READY during operation
Track 00 not found
ID field read error
Uncorrectable data error
Address mark not found
Record not found
Seek error
Correctable data error
Correctable data error
Bad track flag detected
Format error
Illegal access to alternate track
Illegal alternate track for format
Expected alternate track, isn't
Alternate track = bad track
Invalid command
Illegal disk address
RAM diagnostic failure
Proqram memory checksum error
ECC diagnostic failure

This error should never be encountered by the DSR.

4-67

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

The errors that can be reported during boot are the controller error!"
given in Table 4-13 and Table 4-14.

/~--

Table 4-14

Displayed Error Codes

All errors have the following message displayed:

Where xx

Extended Error
33H
40a

41H
42H
43H
44H
4SH

46H
47H

48H
49H

4AH
4BH
4CH

4DH
4EH
4FH

SlH
S2H
S3H
S4H
SSH
S6H

S7H
S8H
S9H

** SYSTEM ERROR - llxx **
= the extended error
Explanation

Status error on REQUEST SENSE STATUS command
Time-out
while waiting for WRITE DATA mode
READ
MODE
while waiting for WRITE DATA mode
COMMAND MODE
while waiting for WRITE DATA mode
STATUS MODE
while waiting for WRITE DATA mode
WRITE
MODE
while waiting for READ DATA mode
Time-out
while waiting for READ DATA mode
COMMAND MODE
while waiting for READ DATA mode
STATUS MODE
while waiting for READ DATA mode
WRITE
MODE
while waiting for COMMAND mode
READ
MODE
while waiting for COMMAND mode
Time-out
while waiting for COMMAND mode
while waiting for COMMAND mode
STATUS MODE
WRITE
MODE
while waiting for STATUS mode
while waiting for STATUS mode
MODE
READ
COMMAND MODE
while waiting for STATUS mode
Time-out
while waiting for STATUS mode
Disk not ready
CRe error
Seek error
Sector-not-found error
Disk (unknown) error (controller failure)
Not a TI-system disk
Disk format error
Bad boot sector CRe or bad controller
System ROM version doesn~t support Winchester

4-68

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

4.14.8

Hardvare Interface Routines

This
interface
to
the Winchester disk system implements additional
functions in a straightforvard vay.
The calls provide a
method
of
interfacing vith the hardvare that is almost hardvare-independent.
To use this interface, do a long call through the first doublevord in
the RAH area of the Winchester disk controller ROH.
Place the opcode
for
the
operation
in
register AH.
Other register
usages are
explained vith each operation.
For more information,
paragraph 4.5.2.

refe~

to paragraph 4.4.4 and to

the

table

in

The programming steps required to do the long call are given belovo
WINROH DO

;LOCAL PLACE TO STORE VECTOR
;TO ROM.

00000000

The next steps get the entry vector for the Winchester ROH
code from the ROM data area and put it into local storage
PUSH
XOR
MOV
MOV
LES
MOV
KOV
POP

ES
AX,AX
ES,AX
ES,ES:WORD PTR 18Ca

;SAVE ES
; SET ES TO O·OOOH
;GET WINCH RAH SEGMENT INTO ES
;~ET VECTOR FOR WINCH ROH
.;SAVE IN OUR DATA AREA

AX,~DWORD PTR~~OOO

WORD PTR WINROH+2,ES
HORD PTR HINROH,AX
ES

;RESTORE ES

The folloving steps access the Winchester ROM functions
after the above initialization is completed
MOV AH,OPCODE
CALL WINROH
The folloving
entry point.

;SET OPCODE INTO AM
;GO DO THE OPERATION

paragraphs explain the operations available from this

4-69

TECHNICAL REFERENCE

4.14.8.1

DEVICE SERVICE ROUTINES

Initialize Winchester Disk System.
Opcode:
Entry:
Offset
OOH
02H
03H
04H
OSH
06H
08H
OAH
OBH
Exit:
Used:

AH = OOH
DS:SI
POINTER TO DATA BLOCK

=

Value/Use
(Hord)
(Byte)
(Byte)
(Byte)
(Byte)
(Hord)
-(Word)
(Byte)
(Byte)

Sector size in bytes
Track size in sectors
Number of surfaces
Humber of cylinders on disk
Number of error retries
Reduced write current cylinder
Hrite precomp start cylinder
Step option
Error-burst corrected length

=

AL
Error code
AX, BX

This operation tells the disk subsystem the type of Hinchester drive
being used.
It
sets
the hardware and software data structures so
that a user can simply call the DSR to use the drive.
4.14.8.2

Check Hinchester ROM Version.

=

Opcode:
Entry:
Exit:
Used:

AH
01H
Hone
AX = BCD ROM version number
AX

Example:

If ROM is V1.23,

then AX returns 0123H

This operation returns the Winchester ROM version
often useful for software-compatibility checks.

4-70

number.

This

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

4.14.8.3

Request Controller Error Sense.
Opcode:
Entry:
Exit:
Used:

=

AH
02H
DS:SI = Address of 6-byte data block
AL = Error code
Z
Set if no error
Data block contains what controller returned.
AX,CX,SI,DI

=

This operation gets error information from the controller and returns
an error code.
If
the controller hardware is broken, appropriate
error codes are returned.
4.14.8.4

Send Winchester Controller Command.
Opcode:
Entry:
Exit:

AH = 03H
DS:SI = Address of 6-byte data block containing
command and other data (see hardware spec)
AL = Error code if Carry flag is set
- Z = Set, C = Reset if no error
Z
Set, C
Set if time-out
Z
Reset, C
Set if improper controller mode
AX,CX,SI

=
=

Used:

=

=

This ope~ation sends a command to the controller.
for a response.
4.14.9.5

It does

not

wait

Get Data From the Winchester Controller.
Opcode:
Entry:
Exit:

AH

= 04H
= Address

of buffer to receive data
CX = Humber of bytes of data to get
AL = Error code if Carry flag is set
Z = Set, C = Reset if no error
Z
Set, C
Set if time-out
Z = Reset, C = Set if improper controller mode
AX,CX,DI
ES~DI

=

Used:

=

This operation waits for the controller to provide data and then puts
it into the user's buffer.
The operation waits about 1 second before
returning a
time-out
error.
If
the controller is in the command
state or the status state, an appropriate error code is returned.

4-71

TECHNICAL REFERENCE

4.14.8.6

DEVICE SERVICE ROUTINES

Write Data to the Winchester Controller.
Opcode:
Entry:
Exit:

AH = OSH
ES:DI = Address of data buffer to transmit
CX = Number of bytes of data to put
AL = Error code if Carry flag is set
Z = Set, C = Reset if no error
Z
Set, C
Set if time-out
Z
Reset, C
Set if improper controller mode
AX,CX,DI

=
=

Used:

=

=

This operation vaits for the controller to ask for
data and
then
vrites from the user's buffer to the controller.
The operation vaits
about
1 ~econd before r~turning a time-out error,
If the controller
is in the command state or the status
state,
an appropriate
error
code is returned.
4.14.8.7

Get Status From Winchester Controller.
Opcode:
Entry:
Exit:

Used:

AH = 06H
None
AL = Error code if Carry flag is set
Z = Set, C = Reset if no error
Z = Se t , C = set if time-out
Z = Reset, C = Set if controller mode is not status',
Z = Re set, C = Reset if status indicates controller
has an error
AX,CX

This
operation vaits for the status return from the controller,
The
operation vaits about 1 second before returning a time-out error.
If
the controller is in the command state or the data-transfer state, an
appropriate error code is returned.

4-72

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

4.14.9.9

Get and Compare Data From the Winchester Controller.
Opcode:
Entry:
Exit:

AH = 07H
ES:OI = Address of buffer to receive data
CX = Number of bytes of data to get
AL = Error code if C flag is set
Z = Set, C = Reset if no error
Z = Set, C = set if time-out
Z = Reset, C = Set if improper controller mode
Z
Reset, C
Reset if data does not compare;
if no compare, OI to the miscompared data
AX,CX,Ol

=

Used:

=

This operation vaits for the controller
to provide data and
then
compares it vith the data in the user's buffer.
If the data does not
compare, the data pointer (OS:OI) is set to point at the data address
that
does
not
compare.
After a vait of about 1 s, the controller
returns a time-out error.
If the controller is in the command state
or the status state, an appropriate error code is returned.
4.14.8.9

Enable Data and status Interrupt From Controller.
Opcode:
Entry:
Exit:
Used:

=

AH
08H
Hone
None
AX

This
operation enables
the Winchester controller interrupts to the
system bus.
Hovever, this
operation does
not
enable
the
system
interrupts from
the
interrupt
controller or
from
the processor
interrupt.
4.14.8.10

Enable Status Interrupt From Controller.
Opcode:
Entry:
Exity:
Used:

AH = 09H
None
None
AX

This operation enables the Winchester controller
interrupts
to
the
system bus.
Hovever,
this
operation does
not enable the system
interrupts from
the
interrupt
controller or from
the processor
interrupt.

4-73

TECHNICAL REFERENCE

4.14.8.11

DEVICE SERVICE ROUTINES

Disable Data and Status Interrupt From Controller.
Opcode:
Entry:
Exity:
Used:

=

AH
OAH
None
None
AX

This operation disables the Winchester controller interrupts to the
system bus.
Hovever, this operation does
not disable
the
system
interrupts
from
the
interrupt
controller
or from
the processor
interrupt.
4.14.8.12

Poll for Controller Request.
Opcode:
Entry:
Exit:
Used:

=

AH
OBH
None
Z = Set if request is not active
Z = Reset if request is active
AX

This operation determines vhen the controller is ready
status, data in, or data out.
4.14.8.13

for

command,

Format a Track.
AH = OCH
DL
Drive number (4,5)
DH
Interleave factor
CX
Logical track number to format
The drive parameters must have been set using operation O.
Exit:
AL = Error code, 0 if OK
CX
Track number of error, if there is an error
Used:
AX,BX,CX,DX,SI,DI

Opcode:
Entry:

=
=
=
=

This operation formats a
track on the Winchester disk.
The drive
parameters must be set up by a call to operation O.
Multiplying
the
cylinder number by the number of surfaces, then adding in the surface
number yields
the
logical
track number.
The interleave factor is
typically 12 or 13 for optimum use of the DSR in
reading sequential
sectors.
The error code returned is the controller error code vith
extentions for such conditions as time-outs.
This
operation alvays
does a
RESTORE operation before the track format, so it is slov to
format a disk.

4-74

: DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

4.14.8.14

Format an Alternate Track.
AH = ODH
DL = Drive number (4,5)
DH = Interleave factor
CX = Logical track number to format
BX = Logical track number of alternate
The drive parameters must have been set using operation o.
AL = Error code, 0 if OK
Exi t :
CX = Track number of error, if there is an error
AX,BX,CX,D~,SI,DI
Used:

Opcode:
Entry:

Formatting routines use this operation to map a
bad
track
to
an
alternate _track..
The
drive parameters must be set up by a call to
operation O.
Multiplying
the
cylinder
number
by
the
number
of
surfaces,
then adding
the
surface number yields the logical track
number.
The interleave factor is typically 12 or 13 for optimum use
of the DSR in reading sequential sectors.
The error code returned is
the
controller
error
code with extensions for such conditions as
time-outs.
4.14.8.15

Format a Track as Bad.
AH = OEH
DL = Drive number (4,5)
DH = Interleave factor
CX = Logical track number to format
The drive parameters must have been set using operation O.
Exit:
AL = Error code, 0 if OK
CX = Track number of error, if there is an error
Used:
AX,BX,CX,DX,SI,DI

Opcode:
Entry:

This operation formats a defective track so that read
operations
do
not
miss
the defect.
The drive parameters must be set up by a call
to operation O.
Multiplying the cylinder number
by
the
number
of
surfaces,
then adding
the
surface number yields the logical track
number.
The factor is typically 12 or 13 for optimum use of the
DSR
in
reading
sequential
sectors.
The
error
c,ode
returned is the
controller error code with extentions for such conditions
as
timeouts.
This
operation always
does
a RESTORE operation before the
t rack forma t .

4-75

TECHNICAL REFERENCE

4.14.8.16

DEVICE SERVICE ROUTINES

Check the Track Format.
AH = OFH
DL = Drive number (4,5)
DH = Interleave factor
CX = Logical track number to check
The drive parameters must have been set using operation o.
Exit:
AL = Error code, 0 if OK
CX = Track number of error, if there is an error
AX,BX,CX,DX,SI,DI
Used:

Opcode:
Entry:

This operation checks a track for proper format.
This
routine
does
not
report
errors for tracks that have been formatted as bad tracks
or altern~te tracks unl~ss the 10 fields are
incorrect.
The
drive
parameters
must be set up by a call to operation O.
Multiplying the
cylinder number by the number of surfaces, then
adding
the
surface
number,
yields
the
logical track riumber.
The interleave factor is
typically 12 or 13 for optimum use of the DSR in
reading
sequential
sectors.
The
error code returned is the controller error code with
extentions for such conditions as time-outs.
4.14.8.17

Format a Winchester Drive.
AH = 10H
DL = Drive number (4,5)
DH = Interleave factor
CX = Logical track number to begin format
The drive parameters must have been set using operation 0,
Exit:
AL = Error code, 0 if OK
CX = Track number of errot, if- there is an error
AX,BX,CX,DX,SI,DI
Used:
Opcode:
Entry:

This operation formats a Winchester drive.
The drive parameters must
be set by a call to operation O.
Multiplying the cylirider number
by
the
number
of
surfaces, then adding the ~urface numberL yields the
logical track number.
The interleave factor is typically 12
or
13
for
optimum use of the DSR in reading sequential sectors.
The error
code returned is the controller error code with extentions
for
~uch
conditions
as
time-outs.
If
an
~rror
occurs
during
the drive
formatting operation, register ex returns the track in error.
If the
formatting operation must be completed, increment
the
track number
and
call
the routine again.
This could be necessary, for instance,
if a drive defect falls directly on an address mark or 10 field.

4-76

TECHNICAL REFERENCE

SYSTEM I/O MAP

Appendix A
SYSTEM I/O MAP

Table A-I System I/O Map
Address

Device

Bit/Use

Mo therboard: - --.
00000

U41 Latch

0
1

2
3
4
S
6
1
00001

U48 Input buffer

0
1
2
:3
4

S
6
1
00002

U49 Latch

00003

USO Latch

0-1
0
I

2
4
S
6
1

A-I

Speaker timer enable
Timer 1 interrupt enable
Timer 2 interrupt enable
Single-density (FM) enable
Track greater than 1/2
(TG43)
Diskette side one enable
(FSID-)
Diskette mode control (Hl)
Diskette mode control (MO)
Option jumper EI-E2
Option jumper E3-E4
option jumper ES-E6
Par i ty interrupt pending
Printer port BUSY
Printer port paper .'ou t
Printer port printer
selected
Printer port NO fault
Printer port data
outputs
LED I OFF
LED 2 OFF
LED :3 OFF
Par i ty interrupt enable
Printer port not auto feed
Printer port not strobe
Printer port not
initialized

SYSTEM I/O MAP

TECHNICAL REFERENCE

Table A-l System I/O Map (Continued)
Address

Device

Bit/Use

Motherboard(Continued):
00004

OOOOS-OOOOF
0001.0
0001.1
00012-00013

USl Latch

0
1.
2
3
4
5
6
1

Diskette
Diskette
Diskette
Diskette
Diskette
Diskette
Diskette
Diskette

Drive
Drive
Drive
Drive
Drive
Drive
Drive
Drive

SELECT
SELECT
SELECT
SELECT
MOTOR
MOTOR
MOTOR
MOTOR

Reserved
U44 8251 USART
U44 8251 USART

Data Register
Control Register

Reserved

00014
0001.S
00016
0001.1
00018

U45
U4S
U45
U45
U46

00019

U46

00020

FDC

00021
00022

FDC
FDC

00023
00024-0002F

FDC

8253 Timer
Counter 0
8253 Timer
Counter 1
8253 Timer
Counter 2
8253 Timer
Control register
8259A Interrupt
controller
82S9A Interrupt
controller
Command register
or RAM
Track register
Sector register
or RAM reset
Data register
Re-s erved

Winchester Controller Board:
00030

Winchester I/O port
I npu t :
0-1
Don't care. Data is
held for each
handshake cycle.
Ou t pu t :
0-1
Don't care. Data is
latched til
updated.

A-2

1
2
3
4
1

2
3
4

SYSTEM I/O MAP

TECHNICAL REFERENCE

Table A-1 System I/O Map (Continued)
Address
00031

Device
Bit/Use
Winchester reset register
Read:
o Data request
1
Input/Output
2
Command/Data
3
Interrupt pending
(Level 6)
Write:
0-7 Don't care (Any
vrite vill do a RESET)

Winchester -Con-troller Boar-t! (Continued):
00032
00033

o
1

Hot used
Interrupt Mask
Status interrupt
enable
Data interrupt
disable

Future Options:
Reserved
Local Area Het
Reserved

00034-00038
0003C-0003F
00040-000BF

A-3

I/O

SYSTEM I/O MAP

TECHNICAL REFERENCE

Table A-1 System I/O Map (Continued)
Address

Bit/Use

Device

Clock and Analog Interface:
OOOCO

Clock/Analog
Interface
0
1
2
3
4
5
6

7
000C1
000C2

oooce
000C9
OOOCA
OOOCB
OOOCC
OOOCD
OOOCE
OOOCF
00000

00001-00007
OOODS
OOOD9-000DF

End of conversion
(EOC)(Active ~IGH)
Not used (tied LOW)
Lightpen interrupt latch ON
Battery loW'
SW'itch 4
Switch 3
Switch 2
SW'itch 1

Do not allow light
pen interrupt
(tri-state signal)
AlloW' light pen
interrupt (Pass
interrupt signal)
.Joystick port Xl
(Current sense)
.Joystick port Y1
(Current sense)
.Joystick port X2
(Current sense)
.Joystick port Y2
(Current sen-se)
Analog input 4
(SW4) (Voltag~ sense)
Analog input 3
(SW3) (Voltage sense)
Analog input 2
-( SM 2 ) ( Vol tag e --s ens e )
Analog input 1
(SW1) (Voltage sense)
Clock Control
o Address Bit 0 MSMS832 clock
1
Address Bit 1 MSMS832 clock
2 Address Bit 2 MSMS832 clock
3
Address Bit 3 MSMSe32 clock
4
HOLD
5
WRITE
6
READ
7
+ or - 30 sec adjust
Reserved
Clock data
(loW' nibble only)
Reserved

A-4

TECHNICAL REFERENCE

SYSTEM I/O MAP

Table A-l System I/O Map (Concluded)
Address

Device

Bit/Use

Sync-Async Comm Board:
Interrupt Acknowledge
CHB command
CHB data
CHA command
CHA data

OOOEO-OOOE3
OOOE4
OOOES
OOOES
OOOE7

COMM Port 1 IRl

OOOES-OOOEB
OOQEC
OOOED
OOOEE
OOOEF

COMM Port 2 IR2

Interrupt Acknowledge
CHB command
CHB data
CHA command
CHA data

OOOFO-OOOF3
OOOF4
OOOFS
OOOFS
OOOF7

COMM Port 3 IR3

Interrupt Acknowledge
CHB command
CHB data
CHA command
CHA data

OOOFS-OOOFB
OOOFC
OOOFD
OOOFE
OOOFF

COMM Port 4 IR4

Interrupt Acknowledge
CHB Command
CHB Data
CHA Command
CHA Data

OOlOQ-003FF

Available for
future products

A-Sis

SYSTEM MEMORY MAP

TECHNICAL REFERENCE

Appendix B
SYSTEM MEMORY MAP

Table B-1
Address

System Memory Map
Devices

Dynamic RAM:
OOOOO-OFFFF
10000-1FFFF
20000-2FFFF
:30000-:3FFFF

64-kbytes
64-kbytes
64-kbytes
64-kbytes

motherboard RAM
expansion RAM board Bank 1
expansion RAM board Bank 2
expansion RAM board Bank :3

40000-BFFFF

Expansion bus memory

CRT Controller:
COOOO-C7FFF
C8000-CFFFF
DOOOO-D7FFF
D8000-DDFFF

Graphics RAM Bank A
Graphics BAM Bank B
Graphics RAM Bank C
Reserved

DEOOO-DE7FF
DE800-DEFFF

Active character memory
Phantom character memory

DFOOO

Bit 0
Bit 1
Bit 2
Bit

::3

Miscellaneous input buffer,
BLUE feedback, read only
Miscellaneous input buffer,
RED feedback, read only
Miscellaneous input buffer,
GREEN feedback, read only
Miscellaneous input buffer,
interrupt pending, read only

B-1

TECHNICAL REFERENCE

Table B-1.
Address
DF001-DFOOF
DF010-DF01F
DF020-DF02F
DF030-DF03F
DF040-DF7FF
DF800-DF80F
DF810
DFB11
DF812
DF813
DF814-DF81F

SYSTEM MEMORY MAP

System Memory Map, Concluded
Devices
Miscellaneous input buffer
Graphics RED palette
latch, write only
Graphics GRN palette
latch, write only
Graphics BLU palette
latch, write only
Reserved
Attribute latch
CRT controller address register,
write only
CRT Controller status register,
read only
CRT Controller address register,
write only
CRT Controller address register,
write only
Reserved

DF820
Bit 7
Bit 6

Miscellaneous output latch,
interrupt enable
Miscellaneous output latch,
alphanumerics screen enable

Other Peripherals:
DF821-DFFFF.
EOOOO-E7FFF

Reserved
Reserved for speech storage RAM

E8000-F3FFF

Reserved

ROM Usage:
F4000-FSFFF
F6000-F7FFF
F8000-F9FFF
FAOOO-FBFFF
FCOOO-FDFFF
FEOOO-FFFFF

8K ROM space(Clock/Analog
Interface)
8K ROM space(Local Area Net
Option Board)
8K ROM space(Winchester Controller)
8K ROM space(Reserved)
8K ROM space, 1 wait state (XU62)
(motherboard)
8K system ROM, 1 wait state (U63)
(motherboard)

B-2

CHARACTER SET

TECHNICAL REFERENCE

Appendix C
CHARACTER SET

Table C-l

ASCII Control Characters

From USA Standards Institute Publication X3.4-l968

ACK
BEL
BS
CAN
CR
DCl
DC2
DC3
DC4
*DEL
OLE
EM
ENQ
EOT
ESC
ETB
ETX

acknowledge
bell
backspace
cancel
carriage return
device control 1
device control :2
device control 3
device control 4
delete
data link escape
end of medium
enquiry
end of transmission
escape
end of transmission block
end of text

*

FF
FS
GS
HT
LF
NAK
NUL
RS
S1
SO
SOH
STX
SUB
SYN
US
VT

form feed
file separator
group separator
horizontal tabulation
line feed
negative acknowledge
null
record separator
shift in
shift out
start of heading
start of text
substitute
synchronous idle
unit separator
vertical tabulation

Not strictly a control character

C-l

TECHNICAL REFERENCE

Table C-2.

CHARACTER SET

Numeric Cross Reference for Character Sets

Decimal

Hexadecimal

Keystrokelsl

ASCII
Character

Displayed
Character

0

00

CTRL2

NUL

01

CTRLA

SOH

@

2

02

CTRLB

STX

I

3

03

CTRLC

ETX

4

04

CTRLD

EOT

5

05

CTRLE

ENG

6

06

CTRLF

ACK

7

07

CTRLG

BEL

8

08

CTRL H,
BACKSPACE,
SHIFT,
BACKSPACE

BS

9

09

CTRLI

HT

<>

10

OA

CTRL RETURN,
CTRLJ,
LINE FEED

LF

I

11

OB

CTRLK

VT

a

12

OC

CTRLL

FF

9

13

00

CTRLM,
RETURN,
SHIFT RETURN

CR

]I

14

OE

CTRLN

SO

~

15

OF

CTRLO

SI

~

16

10

CTRLP

OLE

~

17

11

CTRLG

DC1

--4

18

12

CTRL R

DC2

+

19

13

CTRLS

DC3

•

•t
t

•
a

II
• I

20

14

CTRL T

DC4

9T

21

15

CTRLU

NAK

§

C-2

Comments

TECHNICAL REFERENCE

Table C-2.

CHARACTER SET

Numeric Cross-Reference for Character Sets (Continued)

Decimal

Hexadecimal

Keystroke(s)

ASCII
Character

22

16

CTRLV

SYN

23

17

CTRLW

ETB

24

18

CTRLX

CAN

t

25

19

CTRLY

EM

.J,

26

1A

CTRLZ

SUB

-+

27

1B

CTRL[,
ESC,
SHIFT ESC,
CTRLESC

ESC

....

28

1C

CTRL\

FS

1-

29

10

CTRL)

GS

30

1E

CTRL6

RS

++
A

31

1F

CTRL-

US

~

32

20

CTRLSPACE,
SPACEBAR,
ALTSPACE,
SHIFT SPACE

SP

33

21

Exclamation point

34

22

Quotation marks

35

23

#

#

#

Number, Pound

36

24

$

$

$

Dollar sign

37

25

%

%

%

Percent sign

38

26

&

&

&

Ampersand

39

27

Apostrophe

40

28

Open parenthesis

41

29

Close parenthesis

42

2A

*

*

*

Asterisk

43

2B

+

+

+

Plus

C-3

Displayed
Character

-

Comments

1

Blank space

TECHNICAL REFERENCE

Table C-2.

Decimal

Hexadecimal

CHARACTER SET

Numeric Cross-Reference for Character Sets (Continued)

Keystroke(s)

ASCII
Character

Displayed
Character

Comments

44

2C

Comma

45

2D

Minus, Hyphen

46

2E

Period, Decimal point

47

2F

48

30

49

31

50

32

2

2

2

Two

51

33

3

3

3

Three

52

34

4

4

4

Four

53

35

5

5

5

Five

54

36

6

6

6

Six

55

37

7

7

7

Seven

56

38

8

8

8

Eight

57

39

9

9

9

Nine

58

3A

Colon

59

38

Semicolon

60

3C

61

3D

62

3E

>

>

>

Greater than

63

3F

?

?

?

Question mark

64

40

@

@

@

Commercial "at"

65

41

A

A

A

A (uppercase)

66

42

8

8

8

8 (uppercase)

67

43

C

C

C

C (uppercase)

68

44

D

D

D

D (uppercase)

0

/

/

Slash, Virgule

0

0

Zero
One

<

<

<

Less than
Equals si!ln

C-4

TECHNICAL REFERENCE

CHARACTER SET

Table C-2. Numeric Cross-Reference for Character Sets (Continued)

Decimal

Hexadecimal

Keystroke(s)

ASCII
Character

Displayed
Character

Comments

69

45

E

E

E

E (uppercase)

70

46

F

F

F

F (uppercase)

71

47

G

G

G

G (uppercase)

72

48

H

H

H

H (uppercase)

73

49

74

4A

J

J

J

J (uppercase)

75

48

K

K

K

K (uppercase)

76

4C

L

L

L

L (uppercase)

77

40

M

M

M

M(uppercase)

78

4E

N

N

N

N (uppercase)

79

4F

0

0

0

o (uppercase)

80

50

P

P

P

P (uppercase)

81

51

Q

Q

Q

Q (u ppercase)

82

52

R

R

R

R (uppercase)

83

53

S

S

S

S· (uppercase)

84

54

T

T

T

T ·(uppercase)

85

55

U

U

U

U. (uppercase)

86

56

V

V

V

V.(uppercase)

87

57

W

W

W

W (uppercase)

88

58

X

X

X

X (uppercase)

89

59

y

y

y

Y (uppercase)

90

5A

Z

Z

Z

Z (uppercase)

91

58

92

5C

93

50

I (uppercase)

i

Open bracket

\

\

\

Left slash
Close bracket

C-s

TECHNICAL REFERENCE

Table C-2.

CHARACTER SET

Numeric Cross-Reference for Character Sets (Continued)

Displayed
Character,

Decimal

Hexadecimal

Keystroke(s)

ASCII
Character

94

5E

"

"

95

5F

96

60

"

"

"

Graves accent

97

61

a

a

a

a (lowercase)

98

62

b

b

b

b (lowercase)

99

63

c

c

c

c (lowercase)

100

64

d

d

d

d (lowercase)

101

65

e

e

e

e (lowercase)

102

66

f

f

f

f (lowercase)

103

67

9

9

9

9 (lowercase)

104

68

h

h

h

h (lowercase)

105

69

i (lowercase)

106

6A

j (lowercase)

107

68

108

6C

109

60

m

m

m

m (lowercase)

110

6E

n

n

n

n (lowercase)

111

6F

0

0

0

o (lowercase)

112

70

p

p

p

p (lowercase)

113

71

q

q

q

q (lowercase)

114

72

115

73

116

74

117

75

118

76

"

Comments
Circumflex
Underline

k

k

k

k (lowercase)
I (lowercase)

r (lowercase)
s

s

s (lowercase)

t

t

t (lowercase)

u

u

u

u (lowercase)

v

v

v

v (lowercase),

s

C-6

CHARACTER SET

TECHNICAL REFERENCE

Table C-2.

Numeric Cross Reference for Character Sets (Continued)

Decimal

Hexadecimal

Keystroke(s)

ASCIf
Character

Displayed
Character

119

n

w

w

w

w (lowercase)

120

78

x

x

x

x (lowercase)

121

79

y

y

y

y (lowercase)

122

7A

z

z

z

z (lowercase)

123

7B

124

'7C

125

70

126

7E

'\"

'\"

127

7F

CTRL'BACKSPACE

DEL

128

80

ALT 128

C;

129

81

ALT 129

U

130

82

ALT 130

e

131

83

ALT 131

"a

132

84

ALT 132

a

133

85

ALT 133

...a

134

86

ALT 134

it

135

87

ALT 135

9

136

88

Al.T 136

~

137

89

ALT 137

e

138

8A

ALT 138

...e

139

8B

ALT 139

I

140

8C

ALT 140

1

141

80

ALT141

142

8E

ALT 142

Comments

Open brace
Vertical Fule, Bar
Close brace
'\"

ASCII DEL

,

...

I

A

C-7

Tilde

rECHKICAL REFEREKCE

Table C-2.

CHARACTER SET

Numeric Cross-Reference for Character Sets (Continued)
/'

Keystroke(s)

ASCII
Character

Displayed
Character

Decimal

Hexadecimal

143

SF

ALT 143

A

144

90

ALT 144

E

145

91

ALT 145

ill

146

92

ALT 146

f.

147

93

ALT 147

1\
0

94

ALT 148

0

149

95

ALT 149

'0

150

96

ALT 150

151

97

ALT 151

...u

152

98

ALT 152

y

153

99

ALT 153

0

154

9A

ALT 154

U

155

98

ALT 155

¢.

156

9C

ALT 156

£.

157

90

ALT 157

~

158

9E

ALT 158

p+

159

9F

ALT 159

f

160

AO

ALT 160

a'"

161

A1

ALT 161

162

A2

ALT 162

163

A3

ALT 163

164

A4

ALT 164

n

165

A5

ALT 165

iii

166

A6

ALT 166

0

167

A7

AL T 167

a

148

-,

Comments

.-

1\

u

.I

,

0

.,
u

,

C-B

.",

TECHNICAL REFERENCE

Table C-2.

CHARACTER SET

Numeric Cross-Reference for Character Sets (Continued)

ASCII
Character

Displayed
Character

Decimal

Hexadecimal

Keystroke(s)

168

A8

ALT 168

~

169

A9

ALT 169

r

170

AA

ALT 170

.,

171

AB

ALT 171

~

172

AC

ALT 172

~

173

.. AD

-ALT173

174

AE

ALT 174

~

175

AF

ALT 175

~

176

BO

ALT 176

177

B1

ALT 177

178

B2

ALT178

179

B3

ALT 179

180

B4

ALT 180

181

B5

ALT 181

182

B6

ALT 182

183

B7

ALT 183

184

B8

ALT 184

185

B9

ALT 185

186

BA

ALT 186

187

BB

ALT 187

188

BC

ALT 188

189

BD

ALT 189

190

BE

ALT 190

191

BF

ALT 191

;92

CO

ALT 192

II

L

C-9

Comments

TECHNICAL REFERENCE

Table C-2.

CHARACTER SET

Numeric Cross-Reference for Character Sets (Continued)
~--

ASCII
Character

Displayed
Character

Decimal

Hexadecimal

Keystroke(s)

193

C1

ALT193

l.

194

C2

ALT 194

T

195

C3

ALT 195

196

C4

ALT 196

197

C5

ALT 197

198

C6

- ALT 198

199

C7

ALT 199

200

C8

ALT200

201

C9

ALT201

202

CA

ALT202

203

CB

ALT203

Comments

/

204

CC

ALT204

205

CD

ALT205

206

CE

ALT206

207

CF

ALT207

208

DO

ALT208

209

01

ALT209

210

02

ALT210

211

03

ALT211

212

04

ALT212

213

05

ALT213

214

06

ALT214

215

07

ALT215

216

08

ALT216

217

09

ALT217

n

C-10

.-

TECHNICAL REFERENCE

Table C-2.

CHARACTER SET

Numeric Cross-Reference for Character Sets (Continued)

ASCII
Character

Displayed
Character

Decimal

Hexadecimal

Keystroke(s)

218

DA

ALT218

219

DB

ALT219

220

DC

ALT220

221

DO

ALT221

222

DE

ALT222

223

.. OF

ALT223

224

EO

ALT224

a:

225

E1

ALT225

(3

226

E2

ALT226

r

227

E3

ALT227

rr

228

E4

ALT228

I

229

E5

ALT229

a

230

E6

ALT230

j.t

231

E7

ALT231

T

232

E8

ALT232

ell

233

E9

ALT233

9

234

EA

ALT234

Q

235

EB

ALT235

d

236

EC

ALT236

co

237

ED

ALT237

~

238

EE

ALT238

E

239

EF

ALT239

(1

240

FO

ALT240

=

241

F1

ALT241

±

242

F2

ALT242

~

C-ll

Comments

CHARACTER SET

TECHNICAL REFERENCE

Table C-2. Numeric Cross-Reference for Character Set (Concluded)
f/--~

ASCII
Character

Displayed
Character

Decimal

Hexadecimal

Keystroke(s)

243

F3

ALT243

~

244

F4

ALT244

r

245

F5

ALT245

246

F6

ALT246

247

F7

ALT247

::::

248

F8

ALT.248

0

249

F9

ALT249

•

250

FA

ALT250

•

251

FB

ALT251

V

252

Fe

ALT252

'1

253

FD

ALT253

z

254

FE

ALT254

•

255

FF

ALT255

Comments

J

C-12

"-

TECHNICAL REFERENCE

CURRENT REQUIREMENTS

Appendix 0
CURRENT REQUIREMENTS

This appendix contains information on the current allocations
for
the
Texas
Instruments Professional Computer.
Current requirements for the
options and the printed wiring boards are listed below.

-Total current avallable:

*
*
*

5 Volt line 10.0 A
..

12 Volt line··4.5

~

-5 Volt line 0.5 A

Table 0-1

Current Allocations

Device
Name

5 Volt
Line

12 Volt
Line

-12 Volt
Line

Motherboard
CRT Controller
RAM Expansion
Graphics
Diskette Drive
Winchester Drive
Winchester Controller
Communications
Modem
Speech

1.9

1.3
0.2
0.8
1.0
1.1
1.7
0.2
0.0

0.1
0.0
0.0
0.0
1.2
1.8
0.0
0.1
0.1
0.1

0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.1
0.1
0.1

1.9

0-1/2

TECHNICAL REFERENCE

ASYNCHRONOUS COMMUNICATIONS SAMPLE PROGRAM

Appendix E
ASYNCHRONOUS COMMUNICATIONS SAMPLE PROGRAM
Control and Status signals
Listed below are the RS232-C control and
status
signals,
with
the
corresponding 9530 functions
used to control and monitor them.
This
table is a summary of information available from
the
sync-async
comm
board schematic.

Table E-1

RS232-C Control and status signals

-------------------------------------------------------------------------

RS232-C
Signal

Pin
Number

9530
Function

Accessed
through

------------------------------------------------------------------------20

DTRA

Channel A, HR5, Bit 7

Request-to-Send (RTS)

4

RTSA

Channel A, WR5,

Bit 1

Data Set Ready (DSR)

6

DCDB

Channel B, RRO,

Bit 3

Data Carrier Detect (DCD)

9

DCDA

Channel A, RRO, Bit

Clear-To-Send (CTS)

5

CTSA

Channel A, RRO,

Ring Indicator (RI)

22

CTSB

Channe',l B, RRO, Bit 5

Speed Selector (CH)

11, 23

DTRB

Channel B, HR5, Bit 7

Speed Indicator (CI)

12

SYNCB

Channel B, RRO,

Data Terminal Ready (DTR)

3

Bit 5

Bit

4

-------------------------------------------------------------------------

E-1

TECHNICAL REFERENCE

ASYNCHRONOUS COMMUNICATIONS SAMPLE PROGRAM

$ERRORPRINT
$XREF

;*****************************************************************************:
TITLE

COMMEX - Example of Async communications

COMPUTER - 8088 ASSEMBLY LANGUAGE
ABSTRACT

This a sample program showing typical initialization
of the TIPC communications board in asynchronous, polled mode.

;*****************************************************************************

NAME COMMEX
$TITLE(COMMEX - ASYNC COMMUNICATIONS EXAMPLE)
$EJECT

;*************~***************************************************************

PUBLIC DEFINITIONS

;*****************************************************************************

PUBLIC COMMEX
$EJECT

;*****************************************************************************
LOCAL CONSTANTS

;*****************************************************************************

P1CMDA
P1CMDB
$EJECT
BIOCODE
ASSUME

EQU OE6H
EQU OE4H

PORT 1, CHANNEL A COMMAND ADDRESS.
; PORT 1, CHANNEL B COMMAND ADDRESS.

/
SEGMENT BYTE PUBLIC
CS:BIOCODE,DS:BIOCODE

~

;*****************************************************************************
8530 Initialization Routine

This routine initializes Port 1 according to a lable of initialization
parameters stored in PARMST.
PARMST contains an image of the contents
of the various 8530 registers.
The contents of each register is preceeded by the number of the register itself.
This number is used to
select the appropriate register on the 8530.
Thi sin it ial i za t i on programs· the por t for asynchronous, polled
operations where all interrupts from channel A (i.e., receive,
transmit and external status interrupts) and channel B (i.e., external
status interrupts) are disabled.
The software is to poll read
register RRO in channel A to determine when data has been received
and whether transmission of data has completed.

;*****************************************************************************

COMMEX PROC NEAR
First,

the 8530 channel A is initialized.

MOY SI,OFFSET PARMTA;
SI=Address of Chn A parm table.
MOY DX,OE6H
DX=Port 1,Channel A Command address.
MOV CX,PARMAS
CX=Parameter table size.
INIA: LODS DS:BYTE PTR[SI]
Get byte from parameter table.

E-2

TECHNICAL REFERENCE

OUT DX,AL
LOOP INIA

ASYNCHRONOUS COMMUNICATIONS SAMPLE PROGRAM

Write it to 8530 until
all registers are programmed.

Now to initialize channel B.
MOV SI,OFFSET PARMTB;
SI=Address of Chn B parm table.
MOV CX,PARMBS
CX=Parameter table size.
MOV DX,OE4H
DX=Port l,Channel B Command address.
IHIB: LODS DS:BYTE PTR[SI]
Get byte from parameter table.
OUT DX,AL
Write it until all registers
are programmed.
LOOP IHIB
RET
COMMEX ENDP
$E.1ECT

E-3

TECHNICAL REFERENCE

ASYNCHRONOUS CqMMUNICATIONS SAMPLE PROGRAM

;**************************************************************************.
This area contains the initialization parameters for channels A and B
of port 1.

/-

;****************************************************************************
Initialization parameters for channel A.
PARMTA

LABEL NEAR
DB 09
; Select WR9 code.
DB 11000000B
; Reset 8530.
DB 11
; Select WRll code.
OS 01010010S
; Rcv clock=Baud rate generator.
; Xmt clock=Baud rate generator.
OS 14
; Select WR14.
DB 00000011S
; Enable baud rate generator.
DB 12
; Select WR12.
OS 6
; Baud rate (lov byt~)= 9600 baud.
OS 13
; Select
WR13.
DB 0
; Saud rate (high byte)= 9600 baud.
OS 15
; Select WR1S.
DB 0
Disable external status interrupts.
DB 1
Select WR1.
OS 0
Disable all other interrupts.
DB 3
Select WR3.
DB 01000001S
Rcv=7 bits of data + parity bit.
OS 4
; Select WR4.
DB 01000110B
x16 clock input,! stop bit,
; even parity enabled.
OS 5
; Select WRS.
DB 10101010B
; Turn on DTR and RTS,
Transmit enable,
Xmt=7 bits of data + parity bit.
PARMAS EQU $-PARKTA
; Initialization parameters for channel B.
PARMTB LABEL NEAR
Select WR1S.
DB 15
Disable external status interrupts.
DB 00
Select WR1.
DB 01
Disable all other interrupts.
DB 00
PARKBS EQU $-PARMTB
$E~ECT

E-4

TECHNICAL REFERENCE

ASYNCHRONOUS COMMUNICATIONS SAMPLE PROGRAM

;****************************************************************************~

8530 Receive Character Routine
This routine is called to read a single received character from the
8530 receive receive fifo.
If no character is available in the fifo,
this routine
waits
until
a
character
is received before returning to
. ,
the caller.

;****************************************************************************,
READCH PROC NEAR
MOV DX,OE6H
DX=Port 1, Chn A, command address.
TRYRAG: IN AL,DX
; Read RRO contents.
AND AL,OOOOOOOlS
;Q: Any characters in rcv fifo?
JZ TRYRAG
No, try again.
MOV DX,OE7H
Yes, DX=data port address.
IN AL,DX
, AL=character received.
RET
READCH ENDP
$EJECT

\

E-5

TECHNICAL REFERENCE

ASYNCHRONOUS COMMUNICATIONS SAMPLE PROGRAM

;*****************************************************************************
8530 Transmit Character Routine

This routine is called to write a single character (in AL register) to
the 8530 for transmission.
If a character is currently being transmitted
this routine waits until transmission of that character completes before
attempting to transmit the next character.
I~

;*****************************************************************************
WRITEC PROC NEAR
MOV DX,OE6H
; DX=Port 1, Chn A, command address.
TRYXAG: IN AL,DX
; Read RRO contents.
AND AL,00000100B
;Q: Character being transmitted?
JZ TRYXAG
Yes, try again.
KOV DX,OE7H
No, DX=data port address.
OUT DX,AL
AL=character received.
RET
WRITEC ENDP
BIOCODE ENDS

£-6

TECHNICAL REFERENCE

MODEM SAMPLE ROUTINES

Appendix F
MODEM SAMPLE ROUTINES
RCNTL

;************************************************************
RCNTL -

This subroutine determines whether a modem is
installed in port 1 and if so, activates the
RCNTL signal to initiate the modem control Mode.

;************************************************************

RCNTL PROC
MOV
MOV
OUT
MOV
OUT

NEAR
DX,00E4H
AL,OS
DX,AL
A.;', 02
DX,AL

DX = PORT 1 CHANNEL B ADDRESS.
WRS.SELECT.
SELECT REGISTER S.
TURN ON RCNTL (RTS IN CHANNEL B) .

NOW TO DETERMINE IF MODEM IS INSTALLED.
LOOP: MOV
MOV
OUT
IN
TEST
.]Z

RET
RCNTL ENDP

DX,OOE6H
AL,10H
DX,AL
AL,DX
AL,00010000B
LOOP

=

~

DX
PORT 1 CHANNEL A ADDRESS.
RESET EXTERNAL STATUS INTERRUPTS.

READ RRO.
;Q: IS ACNTL (SYNCA) ACTIVE?
NO, CONTINUE TO LOOK FOR ACNTL .
; YES, RETURN TO CALLER IN CONTROL MODE.

F-l

TECHNICAL REFERENCE

MODEM SAMPLE ROUTINES

DIAGST

;**************************************************************

; DIAGST - This routine requests the diagnostics status from
,
the modem and returns the result in register AL.
It is assumed that the Zilog 9530 has been previously
initialized and that the modem has been placed in
Control Mode.

;**************************************************************

DIAGST

LOOP:

PROC
MOV
MOV
OUT
MOV
IN
TEST
.JZ

DIAGST

MOV
IN
RET
ENDP

NEAR
DX,00E7H
AL, 'D'
DX,AL
DX,00E6H
AL,DX
AL,000000018
LOOP
DX,00E7H
AL,DX

OX = PORT 1, CHANNEL A DATA PORT ADDRESS.
AL = DIAGNOSTIC COMMAND CODE.
REQUEST MODEM DIAGNOSTICS STATUS.
OX =PORT 1, CHANNEL A COMMAND ADDRESS.
READ CHANNEL A'S RRO.
;Q: HAS A CHARACTER ARRIVED FROM MODEM?
NO, KAIT FOR COMMAND RESPONSE.
YES, OX = PORT 1 DATA PORT ADDRESS.
READ DATA FROM RCV FIFO.
RETURN KITH STATUS IN AL.

F-2

TECHNICAL REFERENCE

MODEM SAMPLE ROUTINES

DIALER

;*********************************************************
DIALER - This routine dials a
does not monitor the
it assumes the Zilog
initialized and that
in Control Mode.

typical phone number. It
progress of the call and
8530 has been previously
the modem has been placed

The phone number to be dialed is contained in
a buffer (phonum) and is terminated by a nUll.

;*********************************************************

DIALER

PROC
MOV

M"OV· .

MOV
OUT

NEAR
DX,OOE7H
; OX = PORT 1, CHANNEL A DATA PORT ADDRESS.
01 ,OFFSET-"'"PHONUM ; 01 =ADDRESS OF PHONE NUMBER BUFFER.
AL, , T'
;Use T for touch tone
DX,AL
;Transmit - command to modem

Nest send the strip of telephone numbers
LOOP:

MOV
XOR
JE
OUT
INC
JMP

SENDPT: MOV
OUT

LOOP1:

DIALER

AL'- [01 J
AL,AL
SENDPT
DX.AL

; GET PHONE NUMBER DIGIT.

;Q: END OF PHONE NUMBER?

LOOP

YES, SEND PHONE NUMBER TERMINATOR.
NO, SEND DIGIT TO MODEK.
POINT TO NEXT DIGIT.
CONTINUE IN LOOP.

AL, t X'
DX,AL

AL
PHONE NUMBER TERMINATOR COMMAND.
SEND TO MODEM.

01

=

NOW TO WAIT FOR THE DIAL COMMAND COMPLETION.
AL RETURNS THE STATUS OF THE DIAL COMMAND.
OX =PORT 1, CHANNEL A COMMAND ADDRESS.
MOV
DX,OOE6H
READ CHANNEL A'S RRO.
IN
AL,DX
TEST
;Q: HAS A CHARACTER ARRIVED FROM MODEM?
AL,OOOOOOOlB
NO, WAIT FOR COMMAND RESPONSE.
LOOP1
JZ
DX,OOE7H
MOV
YES, OX = PORT 1 DATA PORT ADDRESS.
READ DATA FROM RCV FIFO.
IN
AL,DX
RET
ENDP

F-3/4

TECHNICAL REFERENCE

BOOT ROUTINE AND SAMPLE ASSEMBLY CODE

Appendix G
BOOT ROUTINE AND SAMPLE ASSEMBLY CODE
Appendix G gives a sample source program that
could
be
in
the
boot
sector.
This example is excerpted from the MS-DOS Vl.10 boot sector.

G-l

BOOT ROUTINE AND SAMPLE ASSEMBLY CODE

TECHNICAL REFERENCE

;*************************************************************************
TITLE

BOOT -

SAMPLE BOOT ROUTINE FOR THE TI PROFESSIONAL COMPUTER

This routine is responsible for loading the system files
ABSTRACT
from the disk.
This routine resides in the 'boot' sector
(track 0 sector 1) of the disk which is loaded at absolute
location OCOOOH boot code in the system ROM and then executed.

;******************************************************************************
NAME
TITLE
PAGE

BOOT
TIPC BOOT LOGIC)

;******************************************************************************
LOCAL CONSTANTS

;******************************************************************************
VERS
REV

EQU
EQU

o
o

CR
LF

EQU
EQU

ODH
OAH

Current version of BOOT logic
Revision level

;-----------------------~--~----------------------------------------------~~-~-

; WINCHESTER disk DIT (Disk Interface Table) equates
STRUC
DO
DW
DB
DB
DB
DB
OW
OW
DB
DB
OW
DITSTRC ENDS
PAGE
DITSTRC
DITDIR
DITSEC
DITTRK
DITCYL
DITDSK
DITERR
DITWRC
DITPRC
DITSTP
DITBUR

0
512
17
4
153
1
64
64
10000000B
11
0000

Di sk Interface Routine vector (dword)
Sector size in bytes (word)
Track size in sectors (byte)
Cylinder size in tracks (byte)
Disk size in cylinders (BYTE)
Maximum number of error retries
reduced write current .Write pre-comp threshold cylinder
step option
Error burst length
reserved for expansion

ROM BIOS lnterface vectors:
BELINT
CRTINT
KEYINT
PRTINT
GAMINT
DSKINT
CLKINT
CONINT

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

4BH
49H
4AH
4BH
4CH
4DH
4EH
4FH

System beeper I/O and general ROM interface
Screen I/O
Keyboard I/O
Parallel port I/O
Analog Input/Clock I/O
Floppy disk I/O
Time-of-day clock I/O
System conflguration

G-2

TECHNICAL REFERENCE

BOOT ROUTINE AND SAMPLE ASSEMBLY CODE

;----------------------------------------------------- ------------------------FIXED ROM DATA AREA - (absolute offsets from absolute 0)
These equations define the ROM communications area, containing data
that must be accessed by both the ROM and user/application programs.
This data is accessed from the 'user' program by setting OS = O.

DSADDR
DSSIZR
DSADDO
DSSIZO
DSADD2
DSSIZ2
DSADD4
DSSIZ4
DSADD6
DSSIZ6
DSADD8
DSSIZ8
MEMSIZ

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

4*60H
4*60H+2
4*61H
4*61H+2
4*62H
4*62H+2
4*6:3H
4*6:3H+2
4*64H
4*64H+2
4*65H
4*65H+2
4*66H

(WORD)
(WORD)
(WORD)
(WORD)
(WORD)
(WORD)
(WORD)
(WORD)
(WORD)
(WORD)
(WORD)
(WORD)
(WORD)

pointer to OS for System ROM (ROMDAT)
size of OS for System ROM (ROMDAT)
pointer to OS for ROM at ROMCOD:OOOO
size of OS for ROM at ROMCOD:OOOO
pointer to OS for ROM at ROMCOD:2000
size of OS for ROM at ROMCOD:2000
pointer to OS for ROM at ROMCOD:4000
size of OS for ROM at ROMCOD:4000
pointer to OS for ROM at ROMCOD:6000
size of OS for ROM at ROMCOD:6000
pointer to OS for ROM at ROMCOD:8000
size of OS for ROM at ROMCOD:8000
memory size (number of 16-byte blocks)

;------------------------------------------------------------~-----------------

, DISK DSR OPERATION .CODES

0
Reset disk system, drive parms must be preset
DKRSET EQU
DKSTAT EQU
1
Get disk status in Cal)
2
DKREAD EQU
Read sectors into memory
DKWRIT EQU
:3
Write memory to disk sectors
4
DKVERF EQU
Verify crc on disk sectors
6
.QKVRFY EQU
Verify memory against disk sectors
DKSSTA
EQU
7
Get disk status for pre-retry (if any)
DKFSET EQU
B
Set UNIT & standard DIT for a drive
DKXSET EQU
9
Set UNIT & DIT address for a drive
DKRDIT EQU
10
Return DIT address for drive
DKKMOT EQU
11
Turn off Floppy Disk Motors
DKBADC EQU
12
Old >= this is a bad command
;******************************************************************************
10 segment

- defines load address and entry point for BIOS
, absolute location 400H

10

SEGMENT AT 40H
ASSUME
CS: 10

IOSYS
IOSYS

PROC
ENDP

10

ENDS
PAGE
SEGMENT AT 0000
; Absolute location OOOOH
ASSUME CS:CODE, DS:CODE, SS:CODE, ES:CODE

CODE

FAR

IO.SYS loaded here (40:0000)

G-:3

BOOT ROUTINE AND SAMPLE ASSEMBLY CODE

TECHNICAL REFERENCE

;***********************************************************************~

:*.

Data area for ROM definitions

;****************************************************************************
OLDRMD
IOSIZ
ROMDAT
MOVDST

ORG
LABEL

400H
HORD

EQU
ORG
LABEL
ORG

7
1200H
BYTE
1200H+13CH

EQU

(ROMDAT-OLDRMD)/16

Initial location of ROM data area
Number of sectors in IO.SYS
(OLDRMD+7*512)
Location of rom data area

;****************************************************************************,
MODULE ENTRY POINT

;**********************************************************************~*****,

ORG
PROC
.IMP

BOOT

OCOOOH
FAR
BOOTST

Entry point for boot logic

;----------------------------------------------------------------------------HEADER DATA AREA
;------------------~-----------~---------------------------------------------~
ORG
OC003H
Always start here

File access table
IOSEC
IOTRK
IOHEAD

-

Shows the loader where to find IO.SYS
l

DB
DB
DB

8
0
0

1 side 40 track load sector
1 side 40 track load track
1 side 40 track load head

'-

THE FOLLOWING BYTE MUST BE SET UP BY THE FORMAT COMMAND TO
INDICATE THE DRIVE TYPE FOR WHICH THE DISK IS FORMATTED.
THE PERMISSIBLE VALUES ARE 0-3 WHICH CORRESPOND WITH THE
FLOPPY DISK TYPE.
DSKTYP

DB

00

Disk formatted

BOODRV

DB

00

Storage for boot drive n~m~er

type

WINCHESTER DIT
WINDIT

DITSTRC <>

SIGNON

DB
DB
DB

18 BYTES LONG

CR,LF, 'BOOT V'
VERS/IO+'O','.' ,VERS MOD 10+'0' ,REV+'O'
(c) 1983 Texas Instruments, Inc.' ,0

PAGE

;*****************************************************************************

G-4

BOOT ROUTINE AND SAMPLE ASSEMBLY CODE

TECHNICAL REFERENCE

DISK BOOT LOGIC - ROMOAT is moved from its initial location (absolute
address 400H) to its ~orklng location under MSDOS (absolute address
1200H).
This code is called (FAR) by the ROM.
If an error is
found, it can perform a RETurn to let the ROM handle it in the
same manner as the other boot-time errors.
INPUT:

BL = Floppy drive from which to attempt the boot
stack is set up below thlS code by the ROM

BOOTST:
MOV
CALL

SI,OFFSET SIGNON; Signon the boot sector
MSG

First, move the ROM data area out of

B002:

PUSH
MOV
MOV
MOV
MOV
MOV
KOV
OR

~ay.

Save the ROM's ES
Note that CS = CODE = OOOOH)
OS = CS = CODE = OOOOH
ES = CS = CODE = OOOOH
Save boot drive
Point to last possible rom data area pOinter
Get data pointer
;Q :
Da t a are a i nus e ?
Y: Jump and calc data length
N: Point to next data area pointer
And check lt

SUB
.IKP

ES
AX,CS
OS ,AX
ES,AX
BOODRV,BL
BX,DSAODe
AX ["B"X]
AX,AX
B004
BX,4
B002

KOV
SHL
ADD
SUB
KOV
KOV
KOV
MOV
ADD

CL , 4
Convert dsaddX pointer to absolute address
AX,CL
AX , (BX+2J
And add in the last data area length
AX,offset OLDRKD; Subtract the orlginal location
CX,AX
Results in total length to move
SI,offset OLDRMD; DS:SI = source for the move
DI,offset ROKDAT; ES:OI = destination for th~ move
Get length of move into BP
BP CX
BP ,01
+ ROKOAT = lo~est available memory

MOV
CKP

DX.DS:~ord

.IE

B007

ADD
ADD
DEC
DEC
STD
CLI
REP
CLD
MOV

SI,CX
DI,CX
SI

CMP

word ptr (BX].OOOO

.1NZ

B004:

the

I

I

Pick up the ROKO~T pointer
Q: Has the move already taken place ?
(True if ROM is retrying the boot)
Y: Then skip the move this time
N: Then do the move
00 the move in reverse in case ROKDAT
area is larger than move length.
a relative
a relative

ptr DSADOR
OX,(offset ROMDAT/16)

01

MOVSB
BX,OSAOOR

Protect the move
Do the move
, " RESET STRING DIRECTION
... Set up the rest
start with DSAOOR
I

"

I

I

I

BOOS:
Q:

G-S

ROK's DSADDx

=

zero?

BOOT ROUTINE AND SAMPLE ASSEMBLY CODE

TECHNICAL REFERENCE

JZ
ADD

B006

word ptr [BX),MOVDST

.

N: Not installed, go to next one
Y: Then adjust it

B007

,,
, , , Q: Are we all done?
Y: Continue with boot
, ,

BX,4
SHORT BOOS

"
"

B006:

CMP
JE
ADD
JMP

...
, ,,

.

BX,DSADD8

K: Point to the next ROM's DSADDx
and
loop for next one
,

,

B007:

, , , Shields down

STI

HERE ROMDAT HAS BEEN MOVED AND BP CONTAINS LOWEST AVAILABLE MEM ADDRESS
TELL DSR ABOUT THIS DISK TYPE
MOV
MOV
MOV
INT

DL,BOODRV
--AL,OSKTYP
AH,OKFSET
DSKINT

Set up

t~e

MOV
OR
JZ
PUSH
MOV
MOV
MOV
CALL
POP

Drive number
Get the disk formatted type
Set the floppy DIT opcode
Go do i t .

WINCHESTER if lt is lnstalled.

AX,DS:WORD PTR DS-ADD4
AX,AX
BOOT20
ES
ES,AX
SI,OFFSET WINDIT+4
AH,O
ES:DWORD PTR 0000
ES

;check for winchester
winchester installed?
; Q;
; N; jump
; Y; save OS
;get winchester ROM ES
;get pointer to new DIT
;copy and set new wlnchester DIT
;call the winchester ROM
;retrieve ES

BOOT20:
Load IO.SYS first

- 7 sectors (3.5K) loaded, have to miss the ROM data area

If a disk error occurs,
it
returns to the caller for error handling (the caller is assumed to be
the routine DKBOOT in the System ROM).
MOV
MOV
MOV
MOV

BX,offset OLDRMD
CX,word ptr IOSEC
DH, IOHEAD
DL,BOODRV

MOV
INT
JB
MOV
MOV
JMP

AX,DKREAD*256+IOSIZ
DSKINT
NOBOOT
BL,DL
AX,BP
IOSYS

Transfer offset (ES already set)
Starting at proper track and sector
. .. and head
From boot disk.
7 sectors
Select disk read function
Disk DSR
If error, die
Tell BIOS init about the boot drive
And the lowest available address
Else, go to BIOS init code

register AH contains an error code to be reported by the ROM
NOBOOT:
POP

ES

Restore original ES before ROM gets at it
G-6

"-

TECHNICAL REFERENCE

MOV
RET
ENDP
PAGE

BOOT

BOOT ROUTINE AND SAMPLE ASSEMBLY CODE

DS,DS:word ptr DSADDR
; And point OS at
; FAR Return to DK800T

the new ROMDAT

;******************************************************************************
MSG - Output string uf characters in the current CS to the CRT.
The string should be terminated with a zero byte.
INPUT:
SI = offset of strlng ~n current CS
OUTPUT: (screen)
USED:
AX,S1
STACK:

;-----------------------------------------------------------------------------FROC
NEAR

MSG
MSGO:

LODS

on
MSG1:
MSG
CODLEN
CODFIL

CODE

JNZ
RET
MOV
1NT
JMP
ENDP

CS:byte ptr (SI]; Get the char
AL,AL
Q:
Last char?
MSGl
N: Jump and print it.
Y: *** RETURN ***
AH,CRTWTY
CRT1NT
Else print it
MSGO
And loop

EQU
EQU
DB

$-BOOT
512-CODLEN-'4
CODFIL DUP (0)

LENGTH OF THE CODE
TOTAL SPACE AVAIL FOR CODE
SPACE FILLER

DB
OW

•t

Disk ldentifier
Boot sector eRC (Calculated by a utility)

1 '

OOOOH

ENDS
END

G-7

BOOT ROUTINE AND SAMPLE ASSEMBLY CODE

TECHNICAL REFERENCE

The following pages show a sample assembly code.
a 2048 byte ROM at address F400:6000.
DATASIZ EQU

30H

;ROMDS
;ROMDS
;ROMOS
ROMOS
; ROMDS

184H
188H
°18CH
192H
196H

CODE

0-

EQU
EQU
EQU
EQU
EQU

This code will set up:-~

;length of required data area
;can be zero but must be multiple of 16
;for ROM at F400:0000
;for ROM at F400:2000
;for ROM at F400: 4~00
;for ROM at F400:6000
;for ROM at F400:8000 (main board)

SEGMENT AT OF400H
ASSUME CS: CooDE
ORG
6000H

ROM HEADER

MSGBEG

MSGLEN

ON
ON
DB
DB
DB
DB
EQU

2048
ENTRY
MSGLEN
ODH,OAH
• Vl. 23-- XMPROM,
example ROM
OOH,OAH
$-MSGBEG

;ROM size
;entry point address
;message length
;carriage return, line feed
;version, 6-character name,
message
;carriage return, line feed

ENTRY POINT FOR PONERUP CODE
ENTRY

PUSH
PUSH
PUSH
PUSH

BX
OX
SI
OS

;save important registers

ALLOCATE OPTION ROM DATA AREA IN RAM
XOR
MOV

MOV

ENTOO:

MOV
MOV
SHL
ADD
ADD
CMP
.JNZ
SHR
MOV
MOV

AX,AX
OS ,AX
BX,180H
AX, [ BX J
CL,4
AX,CL
AX,[BX+2)
BX,4
BX,ROMDS
ENTOO
AX,CL
[BX) ,AX
[BX+2],DATASIZ

;setup segment to point
to vector ~r~a
.
;check for RAM in use starting
with system area
;get segment address for ROM
;convert to absolute address
;add 1n length of segment
;point to next ROMS RAM seg pOinter
;Q:
is this the pointer for my ROM?
N: continue adding up RAM usage
Y: convert address to segment
store my segment address
and the segment length

SET UP MY DS AS REQUIRED TO MY DATA AREA.
EACH TIME THIS ROM IS CALLED.

G-8

THIS CAN BE DONE

TECHNICAL REFERENCE

BOOT ROUTINE AND SAMPLE ASSEMBLY CODE

MOV DS,CS:(WORD PTR ROMDS+QCOOOH)
;additional init coed as required
POP
POP
POP
POP

DS
SI
DX
ax

;retrieve the calling ROMS regs

ORG
OW
ENDS
END

6000H+2048-2
ROMCRC

;address for

G-9/10

the ROM CRC

\...... ... "i

TECHNICAL REFERENCE

SAMPLE INTERRUPT SERVICE ROUTINE

Appendix H
SAMPLE INTERRUPT SERVICE ROUTINE
An ISR example, with the appropriate routines to install and remove it,
follows.
The source of the common interrupt exit routine and the
code
to
count the number of outstanding interrupts (INTCTR) are also given.
Using this code is not mandatory, but is recommended to maintain future
compatibility.

H-~

TECHNICAL REFERENCE

SAMPLE INTERRUPT SERVICE ROUTINE

Example 1

;---------------------------------------------------------------SAMPLE
INTERRUPT SERVICE ROUTINE - (RAM-based; for ROM-based
code,

the local data area vould have to be in a separate OS)

;---------------------------------------------------------------INTSEG

SEGMENT BYTE PUBLIC
ASSUME CS:INTSEG

; Segment declaration

Local constants:
INTNUM
STKSIZ

EQU
EQU

46H

OSAOOR

EQU

leOH

INTCTR

EQU

19AH

30

Interrupt number (example)
Size of local stack, including
space required to save any
registers used.
Offset of pointer to System
ROM's OS (Segment = 0000)
Offset of outstanding interrupt
counter (Segment
0000)

=

Local data storage:
OATSEG

OW

0000

If it is necessary for the
interrupt service routine
to access a certain OS, it
should be set up in this
variable vhen the interrupt
vector is initially installed

VECSAV

OW
OW

0000
0000

Save area for or i-9 i nal vec t or
(It must be restored vhen the
user application finishes)

STKSAV

OW
OW

0000
0000

Location to save stack pOinter

OW

STKSIZ+40UP (?); The local stack.
STKS IZ ffhould
be the size (in vords) of the
service routine's stack.
The
'+4' is to allov stack space
for the service routine to be
interrupted by a higherpriority interrupt.
WORD
Top of stack

INTSTK

LABEL

H-2

SAMPLE INTERRUPT SERVICE ROUTINE

TECHNICAL REFERENCE

Example 2

;----------------------------------------------------- -----------

The actual ISR - the appropriate hard~are interrupt vector is
set up by the installation routine to point to this routine.

;----------------------------------------------------- -----------

INTSRV

PROC

FAR

In the case of shared interrupt levels, any determination of
device caused the interrupt should be placed here,
before the local stack s~ap.
Note that this routine can't
use any registers or stack (if it does, it must be moved
to some point after the stack svap).
~hich

PUSH
MOV
MOV
MOV

MOV
MOV
PUSH
XOR
MOV
INC

OS
Save OS on 'interrupted' stack
CS:STKSAV+2,SS
Save current SS ~ SP
CS:STKSAV,SP
- SP, CS
Stack segment = local Code Seg
SS ,S]:I
SP,offset INTSTK; SS:SP
Local interrupt stack
AX
Save AX
AX,AX
Ax = 0000
OS,AX
Point to vector area
OS:(byte ptr INTCTR)
Increment interrupt counter

=

Insert code to reset

the cause of the interrupt

STI
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
MOV

Safe to re-enable interrupts
BX
CX
OX
01

SI
BP
ES
OS,CS:OATSEG

no~

Save rest of the environment
(The user need save only those
registers actually used in
his particular ISR)

Set up local OS from value
saved during installation.

Insert specific interrupt processing logic here

H-:3

TECHNICAL REFERENCE

SAMPLE INTERRUPT SERVICE ROUTINE

Exit logic
POP
POP
POP
POP
POP
POP
POP
CLI
MOV
OUT
XOR
MOV
-DEC
POP
MOV
MOV
POP
IRET
INTSRV

ES
BP
S1

Restore environment

01

OX
CX
BX
Disable interrupts
AL,20H
Reset 8259 interrupt controller
l8H,AL
AX,AX
AX = 0000
DS,AX
Point to vector area
OS: (byte ptr 1NTCTR) ; Decrement interrupt counter
AX
SS,CS:STKSAV+2
Restore original SS:SP
SP,CS:STKSAV
DS
Restore original DS
** INTERRUPT RETURN **

ENDP

~

..

)

.~

H-4

TECHNICAL REFERENCE

SAMPLE INTERRUPT SERVICE ROUTINE

Example 3

;---------------------------------------------------------------Interrupt service routine INStallation routine
;---------------------~------------------------------- -----------

INTINS

PROC
PUSH
PUSH
PUSH
MOV

NEAR
AX
ax
OS
CS:DATSEG,DS

Set up CS-relative pointer to
the local OS - This is
necessary because the only
reference the ISR has vhen
it is invoked is the CS.

Patch the interrupt vector to point to the Interrupt Service
Routine, saving the original vector.
This illustrates the
'brute force' method of setting and getting vectors.
Host
8088 Operating Systems (e.g. MS-DOS) have system calls to
accomplish this feat.
Their use is preferable, because some
Operating Syst~ms attempt to arbitrate vector usage.
XOR
MOV
CLI

AX,AX
DS,AX

Clear AX
OS <-- 0000
Protect the vector operation

Pick up original vector
MOV
MOV

AX,DS:{vord ptr (INTNUM*4»
aX,DS:(vord ptr (INTNUM*4+2»

Save original vector in local save area
MOV
MOV

CS:VECSAV,AX
CS:VECSAV+2,aX

Install vector to Interrupt Service Routine

INTINS

MOV
MOV
STI
POP
POP
POP
RET
ENDP

OS: (vord ptr (INTNUK*4»,offset INTSRV
DS:(vord ptr (INTNUM*4+2»,CS
Interrupts OK again
OS
ax
AX
*** RETURN ***

H-5

TECHNICAL REFERENCE

SAMPLE INTERRUPT SERVICE ROUTINE

Example 4

;----------------------------------------------------- ----------Interrupt Service Routine REMoval routine

;------------------------------------~---------------------------

INTREM

PROC
PUSH
PUSH
PUSH
XOR
MOV
CLI

NEAR
AX
ax
DS
AX,AX
DS,AX

Clear AX
DS <-- 0000
Protect the vector operation

Get original vector from local save area
MOV
MOV

AX,CS:VEGSAV
aX~CS:VECSAV+2

Restor. original vector

INTREM
INTSEG

MOV
MOV
STI
POP
POP
POP
RET
ENDP

DS: (vord ptr (INTHUM*4»,AX
DS:(vord ptr (INTHUM*4+2»,aX
; Interrupts OK again
DS

ax
AX
*** RETURN ***

ENDS
END

H-6

TECHNICAL REFERENCE

SAMPLE INTERRUPT SERVICE ROUTINE

This is the source for the common interrupt exit ~outine as
it
exists
in
ROM.
Any other common exit routine installed here will perform an
identical function.
The user should use this
exit
if
the
installed
interrupt service routine will be running concurrently with a real-time
Operating System
(for instance, during the execution of any of the TI
communication packages).
Example 5

;---------------------------------------------------------------Common Interrupt Exit logic
INFQT:

=

ES:BX
SS:SP of the interrupted code
Interrupt stack contains saved ES,BX,AX (ES at top
of stack)
---oS-tack of inter-rupted code contains saved OS

,._--------------------------------------------------------------ROMOAT
ROM OAT

SEGMENT BYTE PUBLIC
IXSSSV:WORO
EXTRN
IXSPSV:HORO
EXTRN
ENOS

;

Temporary stack pointer save

ROMCOO

SEGMENT BYTE' PUBLIC
ASSUME CS:ROMCOO, OS:ROMOAT

INTXIT

PROC
CLI
MOV
OUT
DEC

INTXIT
ROM COO

MOV
MOV
MOV
POP
POP
POP
MOV
MOV
POP
IRET
ENOP

FAR
Disable interrupts
Reset 8259 interrupt controller
AL,20H
18H,AL
CS: (byte ptr INTCTR+OCOOOH) ; Decrement interrupt
counter (remember, this is in
ROM, so access to the vector
area is CS-relative)
OSAOOR+OCOOOH)
; Get ROM's OS
ptr
OS ,CS: (vord
Save SS,SP of original c~ae
IXSSSV,ES
IXSPSV,BX
Restore commonly used registers
ES
from interrupt stack
BX
AX
Restore original SS,S?
SS,IXSSSV
SP,IXSPSV
Restore OS from original stack
OS
*** INTERRUPT RETURN ***

ENOS
END

H-1/8

TECHNICAL REFERENCE

ASSEMBLY DRAWINGS AND LISTS OF MATERIALS

Sec tion 4
ASSEMBLY DRAWINGS AND LISTS OF MATERIALS
This section contains assembly drawings and lists o~
applicable to the Texas Instruments Pro~essional Computer.
TITLE

TI DRAWING PAGE NO.

Motherboard Assembly
Alphanumeric CRT Controller Board
Option RAM Board
Power Supply Assembly
Main Enclosure
System Assy,Domestic
System Assy, International
Graphics Video Controller
Elecrtical Pin Con~iguration
Sync-Async Comm Sboard
Cable, Parallel Printer
Cable, Video Monochrome
Joy s tic k Boa r d
Option Kit, RAM Chips
Keyboard, Low Pro~ile
Drawings not available in time
Color Display Unit
Winchester Disk Controller
Parallel Test Plug Assembly
PWB,Parallel Test Plug
Con~iguration,Diskette Drive
Power Cord AC
Communications Loopback Plug

Texas Instruments

materials

4-1

~or

2228008
2228009
2228015
2228087
2228038
2223050
2228051
2228061
2228082
2228094
2228106
2228105
2228085
2228099
2280528

,4-8
4-12
4-18
4-23
4-27
4-81
4-37

4-43
4-48
4-52
4-55
4-58
·4-62
4-63
4-64

printing:
2228219
2228220
2228276
2228277
2228279
0996289
2207985

Preliminary Jan 21. 1993

~

5

6

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4 -15

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PART NlIMRER
ZZ7300q-5001

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.....----------lIST OF MATERIALS - - - - - - - - - -..
PART ~UM~ER
222300q-5001
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pry
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I1n4l82
PA~T NUMBER
2223015-0001

ITEM.
0002
0004

R[V
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4-19

. - - - - - - - . . . ; . . . . - - - l I S T OF MATERIALS
11124/82

PART NUMBER
2223015-0002
ITEM.

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11/24/82

PART NUMflfR
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....-----------LlST
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11/24/82
PART NUIIBFR
2223015-5001

I1F.V
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11174/82

PART NUMBER
2223015-5002

Rrv
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1669-000
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4-21

...-----------lIST OF MATERIALS ----------~

./

11/24/82

PART NmmER
2223015-5003

REV
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DESCRIPTION •••••••••••••• ·•••••••••••••••
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QUANTITY •

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0001

00001.000

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OCPZ763-0001

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0005
0005A
0006
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0001
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DESCRiPTION ••••••••••••••••••••••••••••• UM
PWB,EXPANSTPN RAM
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ONE CONDUCTOK #27 AWG CONSISTING OF 7 STRANDS OF #56 AWG
BARE COPPER WIRE OR 7 STRANDS OF #35 BARE COPPER COVERED
STEEL WIRE. SHELD CONSISTS OF 4 ENDS OF #36 AWG TINNED
COPPER SPIRAL WRAPPED OR BRAIDED COPPER WIRE. INTERNAL
INSULATION OF POLYETHYLENE WITH OUTER JACKET AND CONNECTOR
MOLDING TO BE LIGHT TAN IN COLOR MATCHING TI COLOR NUMBER
972939-2101. CABLE ASSEMBLY TO MEET THE REQUIREMENTS OF
UL AND CSA.

3.1.2

MARKINGS:
PARTS OR WRAPPER SHALL BE MARKED WITH TEXAS INSTRUMENTS
PART NUMBER

3.1.3

IMPEDANCE:
CABLE IMPEDANCE SHALL BE 75 Sl.. NOMIMAL.

3.1.4

CONNECTORS:
BOTH ENDS OF THE SHIELDED CABLE SHALL BE TERMINATED EITHER
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5.2

MARKING:
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DIRGRRM, LOGIC, DETRILEDCOMMUNI CRT! DN,
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01962141"

2223096

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A

Jan 21, 1983

Glossary

---,---------------------_.-----abort -- To end a program and return control to the operating
system, usuallu when a mistake or malfunction occurs.
ackno!&lledge
character
a sender.

character
(ACK)
A
transmission
control
sent by a receiver as an affirmative response to

address -- A number that represents a register, a
locati on. or some other da ta s oure e or des tina tion.

memory

analog -- An obJect (or variable) that is represented by a
physical ~uantity, such as a continuously varying voltage.
The physical ~uantity that represents the variable behaves
as some function of the variable.
(Contrast !&lith iiAital>.
AND -- A binary function which is "on" if: and only if all
its inputs are "on".

of

arithmetic and logic unit -- The part of a computer that does
arithmetic, logic, and similar operations.
array -- An arrangement of elements .
auto-call -- A feature that allows a terminal to initiate
call automatically over a switched (telephone) line.

Texas Instruments-

Glossary - 1

a

Preliminary

Jan 21.

Glos sary

1983

backup copy -- A copy of a fIle that is kept for reference in
case the original file is destroyed.
BASIC (~eginner's ~ll-Purpose aymbolic Instruction ~ode) -- a
higher.-Ievll languagE'. similar in structure to FORTRAN but
somewhat easier to learn because of a smaller command
repetoire and simpler syntax.
BASK was invented at
Dartmouth College in 1963 and is probably the most popular
language for personal computers.
batch processing -- a technique or data processing in
Jobs are collected and grouped beforE' processing.
thus are normally processed in a deferred mode.

which
Data

baud. baud rate -- a measure of data transfer rate, equal to
the number of discrete conditions or signal events per
second.
(See bits per second).
binary digit (bit) -- the smallest unit aT information in the
binary system of notation.
bit -- the abbreviation for binary digi~
In the
notation, a bit is either of the characters 0 or 1.
bit transTer rate
the number of bits transferred per
time, usually expressed in bits per second (bps>.

binary
~nit

bootstrap (to "boot") -- to get a system running from a
f...Q.ldstart in a manner like "pulling oneself off the ground
by tugging on ones bootstraps".
branch -- in programming, to make a selection
alternative choices of instructions.

~rom

among

break -- a long space on an asynchronous communications line
that is intended to alert the receiving CPU.
Minimum
duration is one character' time.
buffer -- a device or area 0; memory which is used to hold
something temporarily.
For example,
the screen buffe!,
contains graphic information to be displayed on the video
screen.
buffering -- (Disk Control) Storing data between transfer
op erat ions.
Data read from disk is buffered before
trans~er to
system memory and data to b e wr itt e n i s
buffered after trans~er from system memory.
byte -- a binary element string of 8 bits.
upon as a unit.

usually

carrier -- a continuous frequency capable of being
or impressed with a signal.

Texas Instruments

Glossary - 2

operated
modulated

Pre 1 imi nary

Glossary

Jan 21. 1983

CCITT -- (Comite Consultatif Internationale de Telegraphie et
Telephonie), an international consultative committee which
sets communications standards.
The CCITT V24 interface
sta~dard is similar to the ErA RS-232-C standard.
COBOL -- (COmmon Business-Oriented Language)- a programming
language designed for business data applications
code -- a system of
(c haracters >.

symbols

(bits)

for

representing

data

compile -- to translate a computer program expressed in a
human-oriented language into a computer-oriented language.
control character -- (1) A charcter whose occurrence in a
particular context controls the handling of data.
(2) In
the ASCII code, any of the 32 characters in the first two
columns of the standard code table.
CPS -- characters per second.
CPU (~entral ~rocessing ~nit)
unit of a computer that
includes
circuits
controlling the interpretation and
execution of instructions.
crosstalk
the undesired
circuit to another.

transfer

of

energy

from

one

cursor -- a movable spot of light on the screen of a display
device, usually indicating where the next character will be
entered.
cyclic redundancy check (CRC) -- a method of error detection
which matches CRC tharacters generated by transmitting and
receiving devices based on the content of the message at
th at I ocat ion.
(Disk Control) Comparison of the checksum derived from
data as it was originally written into disk storage with
the checksum derived from the same data as ~t is being read
out of storage. The first checksum is appended to the data
as it is written to the disk.
After reading this data, the
controller computes a new checksum from it and compares the
two.
If the checksums match,
the data is correct.
A
checksum error may indicate a damaged area on the disk,
data that ha.s changed Sllice it was written, or erroneous
reading of correct data where a retry may work.
cylinder -- in a disk pack, the set of all tracks with the
same nomi nal distance from the axis about which th e dis k
pac k rota tes.
These tracks can be accessed
without
repositioning the access mechanism.
data -- a general term for any type of information.
Texas Instruments

Glossary - :3

Pre limi nary

Jan 21,

Glos sary

1983

movement
DP
computer-encoded
of
communications transmission

data communications -- the
information
b~
means
sy stems.

debug -- to find and delete mistakes in computer programs
in other so-Ftware.
default value -- the value chosen automatically by
computer when no explicit choice is made by the user.
delimiter --a character
elements of data.
diagnostic

that

se para tes

or
the

organizes

and

pertaining to the detection of a malfunction.

digital -- the representation of numerical quantities by
means of ti1cret~teg~~mb~1.
It is possible to
express in digital form all information stored, transferred
or processed by a dual-state condition;
e. g.,
ON/OFF,
OP EN/ CLOSE D, or TR UEIF ALSE .
( Con t l' a s t wit h !llla log >.
direct memor~ access (DMA) -- direct data transfer between an
I/O peripheral and memor~1 without computer intervention.
(Disk Control) - The technique generally used to transfer
blocks of data between a peripheral and random-:access
memory.
It is called direct because the host does not
handle the data during the transfer operation.
directory -- a logically organized data structure which holds
pointers to access data sets b~ sequential number or name.
display -- a visual presentation of information.
double-precision
using two computer words instead
to represent a number.
downtime -- the time interval
inoperable due to a fault.

during

which

a

of

one

computer

is

EIA (~lectronic Industries ~ssociation) -- The EIA Standard
RS-232-C deTines interconnection interfaces for terminals.
emulate -- to imitate one system with another such that the
imitating system accepts the same data and achieves the
same results as the imitated system.
EOF(end-of-file mark) -- a code which signifies that the last
record of a file has been read.
equalization -- compensation for the
line.
FCC -- Federal
Texas Instruments

Communications

loss

of

Commission -- a

Glossary - 4

signal
board

in

a
of

Preliminary

Glossary

Jan 21, 1983

commissioners having the power to regulate all interstate
and foreign electrical communication systems originating in
th e Un i ted Sta tes.
~ield

-- an area in a record (see

~cord)

treated as a unit.

FIFO

First-In First-Out memory buffer.

file

a group of related records handled as a unit.

firmware -- memory chips with software programs already built
in.
flag -- a character that signals the
cond i t ian, suc h as the end of a word.

occurrence

of

some

foreground processing -- high-priority processing, usually
resulting from' real-time entries, given precedence by means
of interrupts, over lower priority "background" processing.
formatting:
(Disk Control) The division of tracks into
sectors to make it easier to retrieve and update data.' In
each sector,
the block of data is preceded
blJ
an
identifying header.
Gaps are inserted between sectors and
between the header and data blocks within each sector to
allow
time
'or
control
logic 'unctions and speed
'luctuations in the disk drive assembly.
FSK(frequency-shi,t keying) -- a means of transmitting data
in which a "1" is represented as one frequency and a "0" as
another frequency.
G -- giga; when re'erring to computer memory it represents 1
073 741 824. Otherwise it is 1,000,000,000.
global -- in programming, it is something that is de'ined in
one section
a program and used in at least on.e other
section.

0'

grap h ie s -- symb ols
normal I y
pro duce d
by
han dwri ting,
drawing, or printing.
Synonymous with graphic symbol.
graphic character -- a character.
other than a
control
charac tel', tha tis normall y re pres ente d by a graph i c.
hal' duplex channel -- a communications line capable of
transmitting in both directions, but not at the same time.
hardware -- phlJsical equipment, as opposed to a computer
program or method of use, e. g., mechanical, electrical,
magnet ie, or e lectroni c devices.

0' frequency

hertz -- a unit
Abbreviated Hz.
Texas Instruments

equal to one cycle

Glossary - 5

per

second.

Preliminary

Jan 21.

Glossary

1983

hex a dec i rna I -- pert a in i n 9 t 0
a
s e 1 e c ti 0 n
c hoi eli.?
0 l'
condition that has sixteen posslble values or states.
These values or states usually contain 10 digits and 6
letters A through F.
Hexadec imal digits are equivalent to
a power of 16.
I

J

host computer
(Also
Just
"host") -- the
prImary
or
controlling computer to which the terminal is connected by
cab Ie for communications.
identification characters -- characters sent by a station
a switched line to identify the station.

on

inputloutput (110) -- something that can be in an input
output process. either simultaneously or seperately.

or

a
meaningful
instruction -- in a programming language,
expression that tells the computer to execute a specific
task.
instruction set -- the set of the instruction of
01' language.

a

computer

integrated circuit -- a combination of interconnected circuit
elements inseperably associated on or within a continuous
substrate.
integrated modem
a modem that is an integral part
device with which it operates.

of

intelligent terminal -- a synonym for a terminal that
programmable and can do some processing operations.
interface -- interconnection between two pieces of
having different functions.

the
is

equipment

interpreter -- a computer program that interprets programming
languages.
Synonymous with interpretive program.
interrupt -- the temporary stopping of some phase of computer
operation caused by an event external to the operation.
Job -- a task submitted for a computer to dOl
it usually
contains all necessary instructions.
files, and data to
complete the task.
Joystick -- a stick that is hand-held by the user and usually
is used to position something on the screen.
K

-- an abbreviation for the prefi x k il0.
i. e.
1000 in
decimal notation.
In storage capacity, K frequently means
two to the tenth power which is 1024 in decimal notation.
I

Kb -- Kilobyte.

Texas Instruments

Glossary - 6

Pre 1 imi nary

Jan 21. 1983

Glossary

KHz -- Kilohertz.

a unit of frequency equal to 1000 hertz.

LED (Light Emitting Diode) -- a small solid-state
which emits light when a current is applied.

device

library -- a group of related Files.
light pen -- in computer graphics. a pen-like device that can
sense light.
When it is held up to a CRT it can be used to
identify display elements.
line. communications -- describes cables.
telephone lines,
etc .• over which data is transmitted to. and received From.
the terminal.
Also ref!erred to as the "line">.
list -- to print or display data.
listing

a printout. usually of a program.

load -- to enter data into memory or into registers.
machine language -- a language
machine.

that

is

used

as

is

by

a

magnetic disk -- a Flat circular plate with a magnetizable
surFac e I ayer on wh i ch data c an be store d by mag neti c
recording.
The disk may be rigid or Flexible.
mass storage -- storage havi ng a vel' y large storage capac i ty.
message -- in data communications. an amount of
that contains a predeFined beginning and. end.

inFormation

modem -- (contraction of !@,dulator/demodulator).
a device
which modulates and demodulates signals transmitted over
communicationbs Facilities. The modulator is included For
transmission and the demodulator for reception. A modem is
used to permit digital signals to be sent over analog
lines.
Also called a data set.
modulation -- the process by which some characteristic of one
wave is varied in accordance with another wave or signal.
This technique is used in modems to make computer signals
compatible with communications Facilities.
mnemonic -.:... symbol or symbols used instead of terminology
more diFFicult to remember.
Usually a mnemonic has t~o ~r
th ree lett ers.
multiplexing -- using a transmission line
diFferent signals at one time.
NAND -- a logic operator.
Texas Instruments

to

The NAND of! any two

Glossary - 7

carry

several

statements

P

Pre 1 imi nary

Jan 21,

Glossary

1983

and Gis .f a 1 s eo i.p and

0

n 1 y if bot h Pan d QaT' eo tr u e.

nanosecond -- one-thousand-millionth of a second.
noise -- undesirable disturbances in a communications system.
Noise can generate errors in transmission.
non-impact printers -- a printer in which printing is not the
result o~ mechanical impacts; e.g.
thermal printers.
obJect code -- output from a compiler or assembler which is
itself
executable
machine
code or is suitable for
processing to produce executable machine code.
(local) -- describes the state when equipment
devices are not connected to the communications line.

o'~line

or

online -- describes the state when equipment or devices are
connected to the communications lines under control o~ a
processor either directly or through a
communication
system.
The physical connection can be accomplished by
either multiwire cable or a communications line.
open -- to prepare a h 1 e .for pr oces sing

f

e. g.

editing.

operating system -- software that controls the execution of
computer
programs
and
that may provide scheduling,
debugging. input and output controL
accoun'ting,
storage
ass ignment,
data
manag emen t,
and
l' e lat ed
service.
Sometimes called Supervisor,
Executive,
Monitor, Master
Control Program depending on the computer manufacturer.
parallel transmission -- method oT data transfer in which all
bits 01 a character or byte are transmitted simultaneously
either over separate communications lines or on diTferent
carrier frequencies on the same communication line.
parameter -- a variable that is given a constant value Tor
specific purpose or process.

a

0'

parity check -- addition
non-information bits to data,
making the number of ones in each grouping 01 bits either
always odd '01' odd parity 01" always even loT' even parity.
A transmission erroT' can then be detected by checking each
group 01 bits received '01' correct parity.
password -- a word or string
01
characters
that
is
recognizable by automatic means and that permits a user
access to protected storage,
files,
01"
input or output
devices.
program -- a
problem.
programs.

series
Al so,

Texas Instruments

01 instructions written to
to des i gn.
wr i te,
and test

Glossary - 9

solve a
computer

. Pre I imi nary

Jan 21, 1983

G10$ sary

protocol -- a formal set of conventions or rules governing
the format, timing, and error control to -Facilitate message
exchange between two communicating processes.
protected field
enter data.

a field into

which

queue -- a line formed by items in a
processed.

the
system

operator

cannot

waiting

to

be

RAM -- random-access memory.
read -- to get data from a storage device.
record -- a coll~ction of fieldsi the information relating to
one area o~ activity in a data processing activity, e.g.,
all information on one inventory -item.
Sometime's called
item.
relational character -- a
character
that
expresses
a
relationship
between two operands.
Common relational
operators are) .
retry -- (Disk Control) Repetition of search or read/write
operations to recover from "50ft" (correctable> errors.
ROM

Read-only memory.

run
to process
computer.

a

task,

e. g.

a

program,

through

scratch file -- a file where temporary calculations and
is done.
scrolling
the continuous vertical
of data across the screen 'ace.

01"

horizontal

a

work

movement

search -- (Disk Control) Reading headers on the track passing
under a read/write head so as to locate the desired sector.
The controller compares each identification (ID) read 'rom
the track with the ID of the desired sector.
sector -- part of a track or band on a magnetic disk.
seek -- (Disk Control) Moving a set o' read/write
that one of them is over the desired track.

heads

so

serial transmission -- a method of transmission in which each
bit of information is sent sequentially on a single channel
rather than simultaneously as in parallel transmission.
simplex circuit -- synonym for one-way circuit.

Texas Instruments

Glossary - 9

Pre limi nary

Jan 21,

Glas sary

1983

slave station -- a data stat:nn that
a mast er 5 tati on.

IS

under the control

of

software -- a set of compute)' p,ogri:lms, procedures, rules and
associated documentation ~oncerned with the operation of
network computers,
e. g..
compilersl
monitors,
editorsl
utility programs.
(Compen;;):
hard~).
space -- usually equivalent to a binary zero condition.
switched network -- a communications
system
where
the
physical path of the messages may be different with each
USE',
such as the public telephone network.
synchronous transmission -- transmission in which the data
characters and bits are transmitted at a fixed rate with
the transmitt~r and receiver synchronized.
syntax -- the format, or rules. in which instructions must be
presented to the data processing equipment.
terminal -- a device or computer which may be connected to a
local or remote host system, and for which the host system
provides computational and data access services.
text -- a sequence of characters
forming
part
of
a
transmission which is sent from the data source to the data
sink, and contains the information to be conveyed.
track -- that portion of a moving data medium
accessible to a given reading head position.
trap -- a Jump to a specific location caused
con d i t ion.

by

a

which

is

hardw~re

turnaround time
in communications the time required for a
device to switch from receiving to sending on a two-way
alternate circuit.
Time is required by line pT'opogation
effects, modem timing and computer reaction.
TWX -- teletypewriter exchange service.
video -- computer data shown or displayed on
tube monitor or display.

a

cathode

ray

write -- to record data on some storage device.

Texas Instruments

Gloss",ry - 10

Preliminary

INDEX

TECHNICAL REFERENCE
INDEX

A

abor t timer:
answer mode
originate mode
address:
counter
decode
latch
lines
multiplexer switch
KUX switch generation
register
va).) q , bi, t
address, logical
addressing.
AlONe
ALB
ALE
alphanumeric:
CRT .
"
decode
graphics.
alternate character set
analog loopback
arbitration
assigning alternate track
attribute:
bits.
hardware.
interaction
latch
logic
attributes.

3-22
3-22

2-58,

2-26
2-50
2-58
2-58
2-22
3-3
2-44
3-46
3-38
2-20
3-35
3-23
2-58
4-2
2-50
2-37
2-42
3-24
2-47
3-62

2-42,

3-26
2-55
2-55
2-42
2-52
2-55

B

bit:
correlations
definitions
pos it i o·n
shift
blanking display
blink .
blinking
block .
buffer.
buffered-step
burst length
bytes, device control block
byte:
command completion status
error status

.3-29,
.3-4~,

.2-42,

3-30
3-42
3-29
2-30
2-44
2-55
2-43
2-43
2-26
3-37
3-58
3-36
3-38
3-4~

Index-l

INDEX

TECHNICAL RERERENCE

C

carrier loss
CAS
CAS and address multiplexer svitch.
CAS and address MUX svitch generation
Centronics compatible
character:
attributes
block.
enable
gl;.,erator ROM
rate.
ROM .
set and attribute l~gic
sets.
characteristics
CHECK TRACK FORMAT command.
check:
the track forma .
Winchester ROM version
checking parity
clock .
clock genera for
color:
attributes
combinations.
latch
location.
palette .
Command and miscellaneous error codes
command classes
command code
EO

3-22
2-22
2-22
3-3
2-16

2-42,

4-77
4-71
2-22
2-26
2-11
2-55
3-28
3-29
3-29
3-27
3-47
3-45

E3
E4

OC
00

..

command completion status byte.
commands and command testing
command:
CHECK TRACK FORMAT
CONTROLLER INTERNAL DIAGNOSTICS
FORMAT ALTERNATE TRACK
FORMAT BAD TRACK .
FORMAT DRIVE .
FORMAT TRACK .
INITIALIZE DRIVE CHARACTERISTICS
RAM DIAGNOSTICS .
READ.
READ ECC BURST ERROR LENGTH
READ LONG
READ SECTOR BUFFER
Index-2

2-42
2-44
2-55
2-43
2-44
2-53
2.52
2-43
2-41
3-53

-

.3-61,

.~~
'.

3-69
3-69
3-69
3-69
3-:69
3-38
3-36
3-53
3-67
3-63
3-55
3-52
3-54
3-58
3-66
3-56
3-60
3-67
3-65

'---

TECHNICAL REFERENCE

INDEX

RECALIBRATE DRIVE
REQUEST SENSE STATUS.
SEEK.
TEST DRIVE READY.
WRITE
WRITE LONG
WRITE SECTOR BUFFER
composite sync.
composite video
control byte
control field detailed description.
control logic, expansion memory
cOfltroller:
card.
erro_r_ codes
error sense
input clock
INTERNAL DIAGNOSTICS.
INTERNAL DIAGNOSTICS command.
operation flovchart
status b i t s .
status regist~r .
controller, interrupt
coprocessor
correction, error
CPU:
bus buffering
bus controller
clock generator

3-46
3-46
3-57
3-45
3-56
3-68
3-65
2-55
2-55
3-61
3-37
3-2
3-2
3-46
4-12
2-26
3-69
3-67
3-44
3-43
3-40
2-18
2-11
3-69
2-11
2-12
2-11

CRT:

address decode logic
controller
interrupt logic subsystem
screen/CPU arbitration logic sUbsystem
cursor.
cursor coincidence.
cylinder and head ranges

.
.2-43,

2-50
2-37
2-56
2-47
2-55
2-44
3-64

D

data:
input port
lines
output port
pa t t ern t est .
processor
separator .
decode.
description:
control field
sector field
device control block
diagnostic:
loopback.

3-40
2-58
3-40
3-66
2-11
2-30
2-50
3-37
3-70
3-36

.'

2-56

Index-3

TECHNICAL REFERENCE

INDEX

,/:-:..

~

status indicators
diagnostics, execution.
disable data and status interrupt from controller
disk subsystem.
diskette:
drive
drive interface
display:
blanking.'
characteristics
double density.
dot clock
dot rate
drive:
designator
DIAGNOSTIC
DIAGNOSTICS command
DRIVE, RECALIBRATE.

3-23
3-69
4-75
4-3
2-35
2-31
2-44
2-41
1-2
3-32
2-41
2-31
3-69
3-60
3-46

E

ECC burst length
enable data and status interrupt from controller
enable status interrupt from controller
EPROM/ROM .
error:
code summary.
correction philosophy
status byte .
execution of diagnostics
expanded character set
expansion CAS and address MUX svitch generation
expansion memory:
addressing
control logic
control state machine
parity generation and checking
refresh logic
expansion RAM .
explanation of bytes in the device control block
external drives

3-58
4-74
4-74
3-35
,--

3-46
3-69
3-41
3-69
2-43
3-3

'-

3-2
3-2
3-4
3-3
3-2
2-20
3-36
2-31

F

fast-step
512/768 K byte expansion memory boards.
floppy disk controller IC
format:
a track .
a track as bad
a Winchester drive
an alternate track
FORMAT ALTERNATE TRACK comm'and.
FORMAT BAD TRACK command
Index-4

3-37
3-2
2-27
4-75
4-76
4-77
4-76
.3-61, 3-63
3-55

\,

.

)

INDEX

TECHNICAL REFERENCE

FORMAT DRIVE command
FORMAT TRACK command

3-52
3-54

G

generating a character ROM.
generation and checking, expansion memory parity
get and compare data from the Winchester controller
Get data from the Winchester controller
get status from Winchester controller
graphic decode.
graphics:
CRT .
plane
vid~2 .controller.

2-53
3-3
4-74
4-72
4-73
2-50
4-3
3-27
2-37

H

handshake
HIGH logical address
horizontal:
blanking.
scan rate
synchronizing signal.

3-23
3-38
2-45
2-4.1
2-44

I

INITIALIZE DRIVE CHARACTERISTICS
INITIALIZE DRIVE CHARACTERISTICS command
initialize Winchester disk system
i npu t :
clock
port
lntensity
level
interface:
diskette drive
expansion bus
hardware.
system ROM
interleave byte
interleaving
internal drives
interrupt:
controller
lines
logic
mask
routines
IORC
IORCIOREADIOWRITEI/O

Index-5

3-69
3-58
4-71
.2-18,

2-26
3-40
2-55
2-42
2-3.1
2-56
4-2
4-2
3-61
3-38
2-31

.2-18,
.2-.18,

4-3
2-58
2-56
3-41
2-18
3-35
2-59
2-59
2-59
2-12

INDEX

TECHNICAL REFERENCE

I/O decoding
I/O ports
I/O wait states

.3-35,

,2-15
3-:39
2-21

K

keyboard:
mapping
queueing
system .

4-56
4-57
4-3

L

logical address, HIGH, MIDDLE, LOW.
logic:
.expansi on memory co-n t rol .
memory refresh
long space received
ltPopback
loss of carrier
LOW logical address

3-38
3-2
3-2
3-22
2-56
3-22
3-38

M

mask, interrupt
memory adddressing.
memory control:
logic
state machine
state machine, expansion.
memory refresh logic
KFM
KIDDLE logical address.
miscellaneous error codes
modem:
responses
software
time-outs
modified frequency modulation
motherboard:memory
memory addressing
KRDC- .
KREAD-.
multiplexer switch.
multiplexers
MWRITE-

3-41
2-20

.2-21,
.2-30,

1'-

2-:

2-21
2-23
3-4
3-2
2-35
3-38
3-46
3-23
3-23
3-22
2-30
2-20
2-20
2-58
2-58
2-22
3-32
2-58

N

NMI
no response
nonmaskable interrupt
non-blinking

2-18,

Index-6

2-56,

2-58
3-22
2-58
2-43

)

TECHNICAL REFERENCE

INDEX

numeric coprocessor

2-11

o
odd sum
on-board EPROM/ROM.
operating system
output port
OSC clock .

.

2-22
3-35
4-2
3-40
2-58

'

P

3-27

pal" t te
palette number.
port
parity generation and c-hecking.
parity generation and checking, expansion memory
PCLK
phase-locked loop
pixel .
pixel addressing
pixels.
plane .
poll for controller request
port:
data output
input data
reset
precompensation
print screen
processor clock
processor, data
program break
program pause .

paralle~_printer

. .3-2'8,
.2- .16,
,'-

3-.3,~

4-3
2-22
3-3
2-59
2-30,

~-4,

3-26
3-27·
2-41
3-27
4-7~

3-40
3-40
3-40
2-30
4-57
2-58
2-1~

4-57
4-56

R

RAM DIAGNOSTICS
RAM DIAGNOSTICS command
",
RAM, expansion.
raster graphics
RDLB
READ command
READ ECC BURST ERROR LENGTH command
READ LONG command ,
READ SECTOR BUFFER command,
RECALIBRATE DRIVE command
recovering data
refresh:
cycle
logic
logic, expansion memory
timer
refreshing,
"

Index-7

1-4,

3-69
3-,66
2-20
2-37
3-24
3-56
3-60
3-67
3-65
3-46
3-67
3-2
2-21
3-2
3-2
2-58

.

'

TECHNICAL REFERENCE

INDEX
/:,-:'->,

,<

•

register assignments
register, controller status
remote digital loopback
request controller error sense.
REQUEST SENSE STATUS command
reset:
detection circuit
line. '
por t ..;- '~'.'
resolution.
reverse
reverse video and cur.or
reverse..".video .
f'

RFSH,'

..~:i

3-39
3-40
3-23
4-72
3-46
2-12
2-58
3-40
2-41
2-42
2-55
2-43
2-59
2-53
4-2

.~

~

ROM
RO-!f i"n ferface , system
S

scan rate
screen display.
screen/CPU ar.pitration.
,scrolling .
sector buffer .
sector field description
sector interleaving
SEEK command
S en'd Wi nches t er con troller comma,nCi,. ;)"\(L"
~ense, controller error
~ <"~';:
separator .
;ij ', "'k
serial communications .
serial/parallel data conversi~n
softvare:
commands.
timeouts.
$pace received, long
speaker
.'
speaker amplifier .
.:..
starting .creen d~splay
state machine .
state machine, expansion memory <;,o,n)j::Ql."
.,:
J""
..... ',
s ta tic pro t ec t i on
" .;'.; '.:; :,.'.:"",
status lines
status register
~ ~
switch gen'eration, CAS and addr'ess"JoIU.X,.,
system ROM 'interface
system timeis and speaker .
.~j.,

...

'

:~~.

.

'\.

~.

2-41
2-44
2-47
.2-43, 2-44
2-26
3-70
3-38
3-57
4-72
4-72
2-30
4-3
2-26

,~,)

3-24
3-22
3-22
4-3
2-18
2-44
2-23
3-4
2-31
2-43
3-40
3-2
4-2
4-3

T

terminating resistor
terminal or software time-outs.
TEST DRIVE READY
TEST DRIVE READY command

2-31
3-22
3-69
3-45

,
''---

Index-8

INDEX

TECHNICAL REFERENCE

testing, command
timer, abort
timers.
time-outs, modem
time-outs, terminal or software

.2-18,

3-36
3-22
4-3
3-22
3-22

U

underline

v
vertical:
blanking"
se,an rate
synchronizing signal.
video:
connector
memory "

2·41

"TI:: 2 - 44
2-44
2-42

WAITWinchester contro~ler:
command
data
disable data and $tat~s interrupt
enable data and status:lnterrupt'
enable status int~rrupt
get and compare data
get status
poll for request
write data
Winchester:
disk system
drive format
error codes
I/O ports
ROM
wrap
WRITE command.,
. ,
Write data to the ~inch.ster c~ntroller
WRITE LONG command.
write preconpensation ci~~uit
WRITE SECTOR BUFFER'c6mmarrd

,".

Index-9llD

2-58
4-72
4-72
4-75
4-74
4-74
4-74
4-73
4-75
4-73

"

I," "'

."",'

,,4-71
'4-77
3-46
3·<~9

4-71
2-4,3
3-5'6
4-73
3-68
2-30
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