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Texaslnstrunnents
Professional Computer
au

•

(

Technical Reference Manual
~RELIMINARV

Copyright© 1983 Texas Instruments Incorporated
All Rights Reserved- Printed in U.S.A.
The information and/or drawings set forth in this docurr-ent and all rights in and to inventions
disclosed herein and patents which might be granted thereon disclosing or employing the
materials, methods, techniques or apparatus described herein are the exclusive property of
Texas Instruments Incorporated.
No copies of the inform"ation or ~rawings shall be made without the prior consent of Texas
Instruments Incorporated.
INSERT LATEST CHANGED PAGES DESTAOY SUPERSEDED PAGES

LIST OF EFFECTIVE PAGES

I

Nate

The porIIOn of the lUI afIecIed by the

c:nanges IS

IrIdICIIs.cs by a

-"Cal_ In the ourer JNrVI"S of IN P-oI!

Texas Instruments Professional Computer Technical Reference Manual
TI Part No. 2223216-0001
Preliminary Issue: 21 January 1983
TOlill

numbel of pages In

P.,.

ThiS

publica lion 15

CM""
No.

No.

.....

Len.,

C......
No.

No.

CHANGE NOTICES
Aev ..ion

conll.llng of the following:

P..-

C.....

No.

No.

I

ECN
o.t.

Numbe,

Levll

Dftcription

AQdress all correspondence regarding orders to:
Texas Instruments Incorporated
Data Systems Group
P.O. Box 1444, MIS n93
Houston. TX 77001

TECHNICAL REFERENCE

PREFACE

PREFACE
The Technical Re~erence Ma~ is designed to provide the so~tware and
hardware
designer,
and
other
technical persons with detailed
in~ormation as to how the Texas Instruments
Pro~es5ional
Computer is
designed and how it ~unctions.
This manual is divided into

~ive

maJor sections:

Section 1.
Instruments

Introduction - Provides a general description o~ the Texas
Pro~essioniilll
Computer.
and
identi~ies
various
con~igu-rations. options. and accesso-ries.

Section 2.
Ha-rdwa-re
Provides a detailed description o~ each
component o~ the 5~stem. including options.
This section .lso contains
speci~ications
~or
power and inter~ace in~o-rmation.
It provides
hardware prog-ramming data such as coding tab les. reg isters and signa 1
pin-outs.
Section 3.
Systems - Describes the ROM BIOS. interrupt
keyboard scan coding table. and a complete memory map.

vector

list5}

Section 4.
Assembly Drawings and Lists o~ Materials - Provid~,
detiilliled drawi'ngs ~o-r all ~ield replaceable assemblies and options.
"
List
of
Materials is provided with each assembly drawing ~or
identi4=ication o~ all components and piece pa,.ts.
Section 5.
Schematics - Provides logic diagrams and schematics ~(I'
each component and ~ield replaceable assembly of the Texas Instrumen l ~
p,. o~es 5 iona I Compu tel'.
The Glossary contains a de4=inition of
manuiilll.

technical

terms

used

in

this

Index

Texas Instruments

Preliminary - Jan 21,1983

TECHNICAL REFERENCE

Con tent s

Contents
Paragraph

Title

PREFACE

SECTION 1

INTRODUCTION

SECTION 2
2. 1

2.2

HARDWARE

INTRODUCTION
SYSTEM UNIT BOARD
SYSTEM CPU

2.3
CPU Bus Buffe1"ing
2.3.1
CPU Clock Qane1"at01"
2.3.2
2.3.3
CPU Bus Controller
2.3.4
Reset Circuit
2.3.5
Optional Nume1"ic Coprocesso1"
SYSTEM UNIT INPUT/OUTPUT '
controller board is standard equipment.
con~iguration

'.

The system unit board is a large 361.95 I 215.9 mm (14.25 x 8.5 in)
printed wiring board mounted horizontally on the bottom o-F the system
unit chassis.
The system unit board houses the microprocessor and
control circuitry.
It provides -Five sackets an an expansion bus -Fo~
option boards plus an additional socket ~o! a memory expansion option
The system memory can be expanded in 64-kbyte increments to a total of
256 kbytes.
The 5 1/4-in diskette drive is a mass storage device for reading or
writing data to a removable diskette.
The standard diskette drive
stores approximately 320-kbytes o-fl data.
The system unit provides
space -flor the installation o-F a second diskette drive or a Winchester
disk drive.
The Winchester disk drive and controller option is
available in 5-. 10-. 01' 15-megabyte capacities.
The Texas Instruments
Professional
Computer
uses
double-density,
modified
frequency
modul.tion (MFM) recording -Format.
Diskettes used with the Texas Instruments Professional Computer must be
certiof1ied
double-sided.
dual-density.
so-flt-sectored.
5
1/4-in
diskettes.
The system unit power supply is a switching-type 160-watt (W) un i t wi t ii
three output levels.
The supply is rated to support a system equipped
wit han y comb ina t ion 0 ~ 0 p t i un s.

Texas Instruments

1-1

Prel i minary - Jan 21,

1983

Technical Reference

INTRODUCTION

The low-profile keyboard is designed fo~ the operato~/s ease of usThe la~ge, sculptured, typewri ter-like, keyboard keys are used to eni.
alphanumeric data.
The smaller numeric Iceypad can· De used as i:I
calculator.
aetween these two groups of keys is a cluster of five keys
that controls the display cu~sor movement.
Across the top of the
keyboard are the twelve programmable function keys. wnlcn are arranged
in three groups of four keys each.
The featui'.=·S of tne keyboaro
include:

*

A sculptured, low-profile keyboard, which compIles
European 3O-mm home row height requirements.

*

An infinitely adJustable full-length
range of positions from 5 degrees to 15
individual user's preference.

*

Tactile designed F and ~ keys, which let your fingers find the
"home" position on the home row.
A raised dot on the numeric
keyboard number 5 indicates the center key on the pad and
provides reassurance to the operator.

*

A separate microprocessor on the keyboard, which converts
keystrokes into character information.
Separate ke\lboard
diagnostics are conducted on every power-up.

with

the

tilt-bar. which has a
degrees to suit an

The display unit mav b. either a monochrome or color unit. dependil
upon the system configuration.
The standard CRT controller boar\>
furnished with the system unit supports either a color or monochrome
display.
The graphics controller option is available in either one or three
planes.
It provides a resolution of 720 horizontal by 300 vertical
picture elements (pixels) for .. 60 hertz (Hz) system and a resolution
of 720 horizontal by 350 vertical pixels for a 50 Hz system.
The svnchronous-asynchronous communications (sync-async comm) board
option provides both synchronous and asynchronous communications using
an RS-232-C interface.
It supports asynchronous data rates from 50
bits per second to as high as 19 200 bits per second.
The internal modem board option is available in two versions, either
300-baud board providing Bell 103-compatible communication.
or
300/120o-baud board providing Bell 212A-compatible communications.

Texas Instruments

1-2

~reliminary

-

~an

21.

a
a

1983

HARDWARE

TECHNICAL REFERENCE

Section 2

HARDWARE

2. 1

INTRODUCTION

This section d.sc~ibes the design and ~unctions o~ the hardware
for
the Texas Inst,.uments. Pro~e55ional Computer system.
A block diagram
o~ the system is shown in Figure 2-1.

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2-1

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•

2-1

Diag~am

Preliminary - Jan 2L

1983

HARDWARE

TECHNICAL REFERENCE

2.2

SYSTEM UNIT BOARD

The system unit boa~d (contained within the system unit) is the hea~t
of the compute~.
A block diag~am of its operating pa~ts is shown in
Figure 2-2.
The system unit boa~d 'also called the "mothe~boa~d~)
contains the ~ollowing.

*
*
*
*

2. 3

Sldstem CPU
64 kbytes

o~

RAM

m.mo~y

Memory control logic
Input/Output (lID) to the keyboard unit.
dis ke t ted rive s

*

Timing services

*

Expansion
Section 5,

bus for the CRT
drawing 2223005.

controlle~
fo~

logic

p~int.r

and options.

port.

and

Re fer to

diag~ams.

SYSTEM CPU

The system CPU consists of one maJo~ component
an Intel 8088
cent~al
p~ocesso~
- and an optional Intel 8087 numeric cop~ocesso~.
Also included in the system CPU a~e the processor clock circuits, bus
buffers and latches, and CPU status decoding and control line
generati on.
Because the 8088 and 8087 processors are designed to work together in
such it way that they appea~ to attached components to be a single
Chip. it is easy to upgrade the system with an 8087 proc.sso~ at a
later time.
From th is point, the term CPU refers to both devices.

Texa 5 In strument s

2-2

Preliminary - Jan 21,

1983

TECHNICAL REFERENCE

HARDWARE

I

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Texas

Inst~uments

2-3

"

P~el imina~y

-

Jan 21.

1983

HARDWARE

TECHNICAL REFERENCE

2.3.1

CPU Bus BUTTering

The CPU i5 designed to operate in the so-calleo "maximum" mode .fo,:,
this integrated circuit.
(For additional inTormation, see the Int,d
literature on the BOB8 and 8087.) The CPU uses Ii multiplexed <1r1d-res~
and data bus in order to reduce the number OT pins required on the
processor chip.
For this reason, and to provide adequate buffe-ring
'01' the add-ress and data lines on the expansion bus,
a set of add-ress
latches
(U5. U6, U7) and a data bus bu"er (U8) are provided as part
oT the CPU.
2.3.2

CPU Clock Qenerator

The CPU clock generator consists OT an Intel-designed 8294 integrated
circuit,
a crvstal and some discrete components.
The crystai
Trequenc~
is 15.0 megahertz (tt-fz) +1-0.01 percent.
The 8284 (U4)
divides the crystal Trequenc~ bV 3 to obtain the CPU clock Trequency.
5. 0 MHz.
Th e 8284 al so c ont. ins sync hron i z in g log ic Tor the WAITline 'rom the expansion bus and memory subsystem and the RESET- line
Tram the power-good circuit.

0'

2.3.3

CPU Bus Controller

The CPU bus controller chip (U3 9299) takes the status inTormation
Trom the processor and converts it into the lines MRDC- (memory
,-ead), AMWC- (advanced memo,-v write),
IORC- (1/0 ,-ead), AIOWC(advanced 1/0 w,-ite), INTA (inte,-rupt acknowledge), DEN (data bu.f!f:eTo
enable), and DT/R (dat. bUTTer direction control>.
The DEN signal is
qualified with the DMA (di,-ect memorv access) signal beTe,-e it is
used to prevent premature activation aT the s~stem bus bUTTers during
a DMA ep erat ion.
A simple open-loep signature anal~sis (SA) arrangement is provided to
check out the CPU.
Connecting E17 and E18 with a Jumper and
resetting the s~stem (po~er up) causes the processor to execute a
OBFH opcede. The Jumper disables the svstem data bus bUTfer UB, and
the pullup resistors in U06 pull the bus up to a high state.
The
transistor 01 pulls down data line AD6 to provide the "0" bit in the
opcede.
The processer then cycles through addresses FFFFOH to FFFFFH
and OOOOOH to OFFFOH during the SA loop due to the segmented
arc hi tec tu,-e.
NOTE
The symbol "HI! and the te,-m
hex ad e c i ma 1 add res s 0 r va 1 u e.

Texas Instruments

2-4

"hex"

denote a

Preliminary -

~an

21.

1983

TECHNICAL REFERENCE

2.3.4

HARDWARE

Reget Circuit

The power-good or reset detection circuit is designed to detect
condition9 where the power on the motherboard is nat sufficient to
provide reliable operation.
This circuit monitors the 12-V power.
This condition causes automatic restart in the event o~ a power
dropout savere enough to affect the power suppl~ but not enough to
completely shut it dawn.
A resistor/capacitor having a discharg~
transistor combination is used to en9ure that an~ power-up or dropout
causes the RESET line to be true for at least 3 milligeconds (ms).
2.3.5

Optional Numeric Coprocessor

The system unit board is designed to allow the addition of an 8087
numeric coprocessor integrated circuit (IC)'
Once the 8087 is
inserted into the 90cket provided, the special ESCape instructions in
the instruction stream are decoded by both the 8088 and the 8087.
The SOBS doe9 any memory access computation9 required and accesses
the firs t b., ta 0# memory ac cord i ng t o t h e i nstruc t i on.
Tn e 8087,
after decoding the· instruction. IIcatche9" the address generated by
the SOBS for the memor., access and re~uests the bus #rom the 8088 to
#inish accessing the memory as re~uired.
Whe-n the coprocessor i;.
#inished with the bus.
it releases it to the 8OS8 which theT.
continues with the next instruction.
The hardware implements theWAIT instruction of the SOS8 to allow synchronization with the 8087
",han required.

2.4

SYSTEM UNIT INPUTIOUTPUT (1/0) SUBSYSTEM

Dw'l ~2-4230o~

~h.3

The input/output (I/O) subsystem on the system unit board decodes the
I/O addresses #or all of the devices an the board.
The various
output latches and the input bufTer are also components aT the 1/0
subsystem.
In ordar to simpli#y the address decoding o~ the various 1/0 devices.
onlV 10 0# the available 1b bits of 1/0 address are decoded Tor all
I/O devices.
This means that a maximum o~ 1024 bytes aT IIO are
available.
Th. sljstem unit boaT'd uses 48 bCAte9 of this space
beginning at address OOOH, which leaves 976 bytes available ~or the
expansion bus.
The sljstem unit boaT'd devices that are decoded and
their addresses within the CPU (cantral processor unit) IIO space are
listed in Table 2-1.

Texas Instruments

2-5

p,.el i minary -

Jan 2L

i983

TEC~NICAL

HARDWARE

REFERENCE

Table 2-1

ADDRESS

System Unit Board lID

Map

BIT IUSE.

DEVICE

MAIN BOARD:

o

00000

1

2
3
4

,
\.>

S
6
7
00001

U48 Input

o Option Jumper E1-E2

bu~fer

1

2
3
4
S
6
7

00002

U49 Latch

.0-7

00003

USO Latch

o
1

2
3
4
S
6
7

00004

o

US1 Latch

1
2
3
4
S
6
7

Texas Instruments

Speaker timer enable
Timer 1 interrupt enable
Timer 2 interrupt enable
Single-densitu (FM) enable
Track greater than 1/2
(TG43)
Diskette side one enable
(FSID-)
Diskette mode control (M1)
Diskette mode control 
Reserved
.

clock
cloci<
c I DCi<
c I oele

SYNC-ASYNC COM" BOARD:
000£0-OOOE3
000£4
000£5
000E6
000£7

COM" Port 1 rRl

000£9-000£1

COM" Por t 2 I R~

OOOEC

OOOED

OOOEE
OOOEF

oOOFO-OOOF3 CDMM Port 3

Interrupt Acknowledge
CHB Command
CHB Data
CHA Command
CHA Data

COM" Port 4 IR4

Interrupt Acknowledge
CHB Command'
CHB Data
CHA Command
CHA Data

OOOF5
OOOF6

OO0F7

OOOFF

Available ~or
4!uture prod ucts

00100-oo3FF

Texas Instruments

Interrupt Acknowledge
CHB Comman d
CHB Data
CHA Command
CHA Data

IR3

00OF4

OOOFB-OOOFB
OOOFC
OOOFD
OOOFE

Interrupt Acknowledge
CHB Command
CHB Data
CHA Command
CHA Data

2-9

Prel i minary - .Jan 21.

1983

TECHNICAL REFERENCE

HARDWARE

Table 2-3

P~inte~

Po~t

Pinout

+------+------+-------------+-----------+--------------------------+
ISIGNALIRETURNI SIGNAL NAME / SOURCE
FUNCTION
+------+------+-------------+-----------+--------------------------+
19
IDATA STROBE-: Svstem
: Data to be s.mpled when
1
: signal is LOW

+------+------+-------------+-----------+--------------------------+
2
I DATA 1
1 System
: Data output bit
+------+------+-------------+~----------+--------------------------+

3

/20(21)/ DATA 2

System

+------+------+-------------+-----------+--------------------------+
: DATA 3
4
: • Sy stem
+------+------+-------------+-~~--------+--------------------------+
5
121(23): DATA 4
System
+------+----~-+-------------+-----------+--------------------------+

6

/ DATA 5

+------+------+-------------+-----------+--------------------------+
7 /22(25): DATA 6
Sv stem
+------+------+-------------+-----------+--------------------------+
/ DATA 7
System
8
+------+------+--~----------+-----------+--------------------------+
9
/23(27): DATA 8
System

+------+------+-------------+-----------+--------------------------+
IACKNOWLEDGE- / Printer : Indicates that another
10
/ char can b.

~eceived

+------+------+-------------+-----------+--------------------------+
11
: 24 (29): B USV
1 Indicates no d.t. can be :
Printe~

I sent when HIQH

"

+------+------+-------------+-----------+-------------------~------+
Printer : Indicates paper is out
/ PAGE END
12

: IIIhen HIGH

+------+------+-------------+-----------+--------------------------+
Printer I Indicates
is on- 1
13
1 SLCT
p~inter

I

(ON LII'£)

r

1 line wh en HIGH

+------+------+-~-----------+-----------+--------------------------+
: Indicates printe~ is to
14
I AUTO FEEDSystem
1 linefeed on CR when LOW

+------+------+-------------+-----------+--------------------------+
: 15(32) 1
Printer : Indicates fault when LOW:
1 FAULT+------+------+-------------+-----------+--------------------------+
116(31) 125(30) 1 INIT/ Resets printer when LOW
Sv stem
+------+------+-------------+-----------+--------------------------+
117(36) /18(33) 1 SELECTION1 Always LOW
System
+------+------+-------------+-----------+--------------------------+

Texas Instruments

2-12

Pre 1 i mi nary - .Jan 21.

1983
.:

TECHNICAL REFERENCE

ke~boa~d

HARDWARE

is
implemented as a
universal
asynchronou~
(UART) ro~ se~ial data t~ansmission between
the
s~stem
unit and the keyboa~d.
Data received by the UART will always
generate an inte~~upt to
the inte~rupt cont,.oller.
The
transmit
~eady
line ~ill not geneTate an inte,.rupt unless the transmitt.,. in
the UART is enabled.
Note that the ke'dboa~d po~t int.~,.upt
is ORed
with the "inte,.~upt ~ectuest 7 11 line from the numeric cop~ocessor.
Th.

po~t

~eceive~-tTansmitte~

Th. ~eceive data signal is conditioned with a SN75199A line receiver
with a slollldollm capacito~ so that the
lignal
is mo~e immune to
t,..nsient5.
This ~eceive.~ also has a hyste,.esis of app,.oximately 1 V
centeTed a,.ound 1.4 V,
which
imp,.oves the noise immunity.
The
t,.ansmit data line is buffe~ed by a SN75199A buf~e~ to p~ovide a good
voltage sliling and d,.ive to the keyboa~d cable.
This buffe,. consists
int.,.nallv of an output t,.ansisto,. with a 2-kilo ohms (kohms) pull-up
~esi st01'.
to allow imp~oved diagnostics, ~he device se~vice routine
line on the unive~sal
Iynch~onous/asynch,.onous
~eceiver
tTansmitte,.
(USART) is connected to the keyboa~d connecto~ through a
SN7S189A buffe~.
Th. tTansmit data line il connected to the OSR line
at the k.yboa,.d to allolll detection of a
disconnected
defective
k e'lb oaTd.
In

o~d.~

oS"
The 9253-5 c ounte,./t ime~ IC p~ov ides thr ee,
sep ara t e t i mi n gun its.
In this system, one is used as a p~ogrammable speaker oscillator, and
the oth.~ tlilO a,. e p" og~ammab 1 e i nte1"val timers.
The
speake~ time~ is clacked b~ a square wave 041 1. 25 MHz.
With the
ability to divide by uyp to 65 536, the output frequency
can go as
10111 as 19 Hz.
Th. high input f~ectuency causes the output tones to be
mo,.. mUlicalll:l accu,.ate.
The speaker time,. cloc k is inte1"nally gated
~ith
the sp.ake~ enable (SPKEN) signale~ enable} !alhich is an output
of latch ~~~This lignal allolils the inte1""uption of tones !alithout a
rep,. og,.ammi n 9 of th e time~.
The second time1" (Timer A) is used in system-timing applications and
as a real-time clock.
It generates an interT'upt on the rising edge
041 the timer output i~ the enable line (address 0 bit 1) is set to
a
HIGH.
Toggling this line LOW resets the inteT'rupt. holding this line
10111 disables the inte~,.upt completely.
The level o~ the interT'upt is
Texas Instruments

2-13

Preliminary -

Jan 2L

1983

TECHNICAL

HARDWARE

REFERENC~

Table 2-5
ADDRESS

Motherboard Memory Map
DEVICES

DYNAMIC RAM:
0000 O-oF FFF
l0000-lFFFF
20000-2FFFF
30000-3FFFF

b4-kb~tes
64-kb~tes
64-kb~tes

40000-BFFFF

Expansion bus

motherboard RAM
expansion RAM board Bank 1
expansion RAM board Bank ~
b4-kbytes expansion RAM board Bank 3
memor~

CRT CONTROLLER:
COOOO-C7FFF
CSOOO-CFFFF
DOOOO-D7FFF
DSOOO-DDFFF

Qraphics RAM Bank A
Qraphics RAM Bank B
'Qraphics RAM Bank C
Reserved

DEOOO-DE7FF
DEBOO-DEFFF

Active character memory
Phantom character memorv

DFOOO
Bit 0

DF001-DFOOF
DF010-DF01F
DF020-DF02F
DF030-DF03F
DF040-DF7FF

Texas Instruments

Mise input buffer.
BLUE feedback, read only
Bit 1
Mise input buffer,
RED feedback, read onl~
Bit 2
Mise input buffer.
GREEN feedback. read onl~
Bit 3
Mise input buffer.
interrupt pending. read onl~
Mise input buffer
Qraphics RED palette
latch. ~rite onl~
Qraphics GRN palette
latch. ~rit. only
Qraphics BLU palette
latch. ~rite only
Reserved

2-16

Prel i mi nar~ - Jan 21.

1983

HARDWARE

TECHNICAL REfeRENCE
TEXAS INSTRUMENTS PROFESSIONAL COMPeTi ER
TABLE

2-~

MOTHORBOARD MEMORY MAP

+----------------+-------------------------------------------------------+
ADDRESS
DEVICES
----------------:-------------------------------------------------------,

64-KBYTl:.S MOTHIJR80ARD RAM
64-KBVTES EXPANE;ION RAM BOARD BANK 1
64-KBYTI:.~; EXPANSION RAM BOARD BANK 2
20000 => 2FFFF
64-KBVTES EXPANSION RAM BOARI) BANI< 3
30000 =:> 3FFFF
---------------- -------------------------------------- 256-KBYT~S ----64-KBYTES EXPANSION RAM
• 40000 =:> 4l- FFF
64-KBYTI:.!5 EXPANSION RAM
50000 => SFFFF
60000 =)- o.T='FFF
64-KBYTES EXPANSION RAM
70000 =) 7Ff-FF
64-KBYTES EXPANSION RAM
---------------- -------------------------------------- 512-KBVTES ----80000 =:> SFFFF
64-KBVTI:.S EXPANSION RAM
90000 => 9rFFF
64-KBYTES EXPANSION RAM
AOOOO => AFF-H"'64-KBYTES EXPANSION RAM
BOOOO =)- BFFFF
64-KBYTES EXPANSION RAM
---------------- -------------------------------------- 768-KBY1ES ----32-KBVTES GRAPHICS RAM BANK A
COOOO => ~FF
C8000 =:> CFFFF • 32-KBYTES GRAPHICS RAM BANK B
D8000 =)- D7FFF
32-ft..."BVTES GRAPHl CS RAM BANI< C
08000 => D8FF-f-- 16-I [lOt- FF
2-KBYTES RESERVED
2-KBVTI:.S CHARACTI:.H MEMORV
DEOOO =:> DE7FF'"
2-KBYTES CHARACTER ATrRUBUTE MEMORY
DEBOO => DErFF
16- BYTES MISC INPUT BUFFI:.H
DFOOO => DFOOF
16- BYTES RED
PALL~TTE LATCH
DF010 =:> DF01F
DF020 => DF02F
16- BYTI:.S GREEN PALLET1~ LATCH
DF030 =)- DF03F
16- BYTES BLUE PAL~~rTE LATCH
DF040 =:> DF3FF
960-BYTI:.S RESERVED
DF 400 =:> DF7FF t
l-ft..."BYTES RESERVED
16- BYTES ATHHBUTE LATCH
DF800 =:> DFSOF
DF810 => DF81F
16- BYTES CRT CONTROLLER REGISTERS
DFS20 =:> DF82F
16- BYTES MISC OUTPUT LATCH
DF830 =:> DF83F
16- BYTES
DF840 => DFBFF
960-BVTES RESERVED
DFCOO => DFFFF
l-KBYTES RESERVED
=:> OFFFF
10000 =:> 1FFFF

00000

EOOO(. => E3FFF

=> E7f'Fr
~8000 => EBFFF
ECOOO => EFFFF
E4000

FOOOO => F3FFFF4000

=> F5FFF

=:> F7F-FF
=> F9FFF
=> FBFFF
FCOOCl => FDFFF
FEOOO => FFFFF
F 6000

• F8000
FAOOO

16-KBYTES RESERVED FOR SPEECH STORAGE
16-KE:lY1ES RESERVED FOR SPEECH STORAGE
16-KBYTES RESERVED
16-KBVTI:.S RESE~VED
16-KBYTES
8-KBYTES
S-KBY1ES
8-KBYTES
8-KBVTI:.S
8-KBVl ES
S-KBYTES

RESERVED
ROM SPACE ( CLOCK/ANALOG INTERFACE )
ROM SPACE ( LOCAL AREA NET OPTION BOARD)
ROM SPACE ( WIN"CHESrER CONTROLER )
ROM SPACE
ROM SPACE
SYE', EM ROM

+----------------+-------------------------------------------------------+
TEXAS INSTRUMENTS

2-16

HARDWARE

TECHNICAL REFERENCE
Table 2-5

,

ADDRESS
DFSOO-DFSOF
•
DFB10
DFS11
DFS12
DFS13
DFS14-DFS1F
DFS20

Motherboard Memory Map

continued

DEVICES
Attribute latch
CRT controller address register,
write onllj
CRT Controller status ~egister,
read onllj
CRT Controller address register,
wr i t It on III
CRT Controller address register.
IIIr it It on III
Reserved
Bit 7

Bit 6

Misc output latch,
interrupt enabla
Mise output latch,
alphanumerics screen enable

OTHER PERIPHERALS:
DFS21-DFFFF
EOOOO-E7FFF

Reserved
Reserved

EBOOO-F3FFF

Reserved

~or

speech storage RAM

ROM USAGE:
F4000-F'FFF
F6000-F7FFF
FSOOO-F9FFF
FAOOO-FB FFF
FCOOO-FDFFF
FEOOO-FFFFF

Texas Instruments

8K ROM space(Clock/Analog
Interface)
SK ROM space(Local Are. Net
Option Board)
8K ROM spaca(Winchester Controller)
8K ROM space(Reserved)
81( ROM space, 1 wait state (XU62)
8K s'dstam ROM, 1 lIIait state (U63)

2-17

Prelimina,..~

-

~an

21.

1983

HARDWARE

TECHNICAL REFERENCE

2.6.2

Memorlj Control Logic

>""'---,'' Sl\~l-

The motherboard expansion memory is separated from the main system
data bus by a
bidirectional
bw~;er
(U61)
in order to provide
sufficient drive and margin to the data transfers.
Decoding and
timing for the ROMs is done by a combination of the memorij hard array
logic (HAL)
chip HAL16R4
(U28)
and
the 74LS139 decoder (U53).
Because ROMs and EPROMs (erasable programmable read-only memories)
are generallv slow devices. a wait state is .dded to .11 accesses to
these devices.
The ROM access times are listed 'in Table 2-6.
Table 2-6

ROM Access Times

THE REGU IRED
(In Nanoseconds>

FUNCTION

cs-

ROM .ccess

410

RDM address access

577

2. b. 2.1

I/O Wait States.
The HAL chip also contains the logic to
add a wait state to i l l I/O accesses made by the CPU.
The wait state
is necessary because manV of the I/O devices operate too slowly when
the
system buffer and setup and decode times are included.
With the
wait state,
the cont,.ol
lines are
active
approximately
600
nanoseconds (ns>.

2.6.2.2
Melllory Refresh Log ic.
The RAM refresh log ic is designed to
operate synchronously with the accesses to the RAM memorv.
Refresh
cycles are
begun only when a RAM memory cycle is not in proDress.
This implies that the RAM refresh can occur at the same
time as
accesses to other
system memory (ROMs) or I/O space.
Each time a
refresh cycle begins, a re~resh timer (one-shot U29) starts.
When it
times out, it provides the signal to begin another refresh cycle,
This
timer
is
set to 15 us maximum to allow for the worst-case
refresh-request laten.cy.
To maintain the contents of the RAM under
worst-case conditions.
the refresh must occur at least 128 times
within 2 ms.
(The average refresh timing is once
per
15.625 us).
The worst-case latency for a refresh request is about 600 ns.
Once a
refresh cycle has begun. it must be completed (including the
precharge) before the next cycle.
If a RAM access cycle
is started
before the refresh cycle is comp leted, the HAL state machine wi i 1 put
the CPU into a wait state until the refresh operation is completed
In the w 0 l' 5 t cas e. t his del a y c 0 u 1 d mea n ext end i n 9 the norma 1 memo l' Y
access time by four wait sta tes. or 800 ns.
Texas Instruments

2-18

Preliminary - Jan 21.

1983

HARDWARE

TECHNICAL REFERENCE

Assuming a refresh time~ ~alue
slowdown of the CPU,
the ret:resh
average or 5.7 percent worst case.

of 14 us and an average oOO-ns
overhead is about 4. 3 pe~cent

2.0.2.3 CAS and Address Mul1:1plexer Switch.
The address multiplexer
control (SWM)
is produced b'4 a delay line of~ of the row address
strobe input (RASI-) line.
This SwM ensures an adequate row address
hold time (40 ns) and still operates the RAM quickly enough to ~inish
the access within the s~stem cycle time.
The column address strobe input (CASI-) timing depends on whether the
e.,cle is a r.ad a ... a l&I1'ite.
If the c~cle is a ... ead. the CASI- signal
is taken off of the delay line 20 ns after the SWM signal (ACAS-).
This dela., p ... ovid.s an ade~uate column address setup time to the RAM
and still gives fast RAM acc.ss.
If the cllcla is a write. then the
CASI- signal is taken f ... om the falling .dge of the system clack,
which is about 150 ns aft.r the occu ....... nc. of RASI-.
This delay
.llows time fa ... the data f ... om the p... ocesso... to p ... opagate th ... ough the
data buff .... s and the pa ... ity generator chip CU31 74LS280).
To cont ... ol the generation of the CASI- pulse. flip-flop U33 is timed
with the system clock (CLK-), samples the delay line (ACAS-), and is
reset by the memo ... y read (MRDC-) signal.
Th. output of the flip-flap
is th.n logically ANOed (U34) with the ACAS- signal to generate the
actual CASI- signal.
To prevent the generation of a CASI- puls€
du... ing .... f .... sh,
flip-flop U33 is held in the preset state during ~
refrltsh b., the r.fresh row address stroba (RRAS-) line.
This forcec;.
the output of OR gat. U34 (CASI-) to a high level.
2.6.2.4
Pa... ity
Generation
and
Checking.
The
parity
generator/checke ... chip C74LS280) generates a "1" to the parity RAM
bit wheneve ... th .... e is an even numbe ... of "1"5 in the data byte being
w... itt.n.
This is done by using a separate data bus on the parity RAM
chip and using a pullup ... esistor to provide a hig~ on its output
whenever it is not driving the output line (as in a write cycle).
The paritg data is then taken from the "odd sum" output of the parity
generator and used to w~ite to the RAM.
By using this method of parity checking. an attempt to read from nonexistent RAM memo ... y does not ~e5ult in a parity er~or.
This method
is p1"efe1"able because system softwa~e sometimes "feels" fo~ memory
not present in orde,. to dete~mine the size of system memory.
When the RAM is read., all of the data bits and the parity bit are
presented to the gene~ato,,!checke,. and the parity output is sampled
at the end of the read cycle
If the pa,.ity is bad, flip-flop U33 is
set to interrupt the CPU ir ~nabled.
Note that once set, this flipflop must be reset by sor~wa~e before additional interrupts can b@
given.
If the enable bit .
The memor~ control state machine logic is given in Table 2-7.
This device has four outputs e~uipped with a set of clocked ~lip­
flops and four outputs. which are direct combinations o~ the inputs.
Note that the AND of the terms on a line ORed with the AND of terms
on other lines results in low-going outputs.
This occurs either
directl".
on those outputs without registers. or after the clock on
those outputs with registers.

'"

Texas Instruments

2-20

Preliminary - Jan 21.

1983

..

HARDWARE

TECHNICAL REFERENCE

,
Table 2-7

Memo~y

Control State Machine Logic - HAL16R4

INPUTS
MRDXA18
RASIRFSHMWRRMXXWAIT- RRASRFRG
IORCMDENSYOutputs
XA19
AIOWCRMSEL- SX-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+----------------------

RASI-

L

a~
a~
a~

L

H
H

L L .
L L

H
H

MEMORY READ
MEMORY WRITE
REFRESH
all other OR

L L
L L
te~ms
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+---------------------REFRESH+READ RF1,2,3
XWAIT- L
L
L
REFRESH+READ RF3,4
a~ L
L
L
REFRESH+WRITE RF1,2.3
a~
L
L
L
REFRESH+WRITE RF3,4
a~
L
L
L
H ROM READ I~ I TE
H HL
a~
L
H 1/0 READ
a~
L
H liD WRITE
a~
L
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+----------------------

L

MDENa~
a~
a~

L
L

H

H

H H L
H H L

L L

RAM
ROM
ROM
all

READ IWR I TE
READ
WRITE
ather OR te~ms

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+----------------------

RMSEL- L
a~
a~

ROM READ
ROM WRITE
all other OR terms

H HL .

. L . H H L ..
...... L L

-------+-+-+-+-+--+-+-+---+-+-+-+-+-+-+-+----------------------

THE FOLLOWING FOUR OUTPUTS HAVE FLIP-FLOPS
-------+-+-+-+-+-+-+-+-~+-+-+-+-+-+-+~+----------------------

RFSHo~

HH H
HH
L
L

a~
a~

H
H
H
H

RFSH RF 1 NO MEM eye
RFSH RF1 NO RAM eye
REFR ESH RF2, 3
all other OR terms

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+----------------------

RRASo~

. . . . . .
. . . . . . . .

. .. L ..
. L ..

REFRESH RF2,3,4
all other OR terms

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+----------------------

Sy-

........
or . . . . . . . .

. L L .
.... L L .

REFRESH RF3, 4
all other OR terms

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+----------------------

SXa~
a~
o~
a~

L
. L

H HL
H HL

ROM
ROM
I/O
I/O
all

L
L
L

READ WAI T CUTOFF
WRITE WAIT CUTOFF
READ WA t T CUTOFF
WRITE WAIT CUTOFF
other OR terms

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+----------------------

Texas Instruments

2-21

Preliminary - Jan 21, 1983

TECHNICAL REFERENCE

HARDWARE

The signal RASI- activates RAS- out of the AM2964B RAM add~ess
The signal XWAIT- puts the p~ocessor into a wait state.
The signal MDEN- activates the lI"Iott.erboard memory system data buffer.
The signal RMSEL- selects access to the ROMs.
The signal RFSHcont~ols the AM29b4B address multiplexe~ to put the
ref~.sh
add~ess
out.
The signal RRAS- indicates that a ~efresh RAS is in prog~ess.
The signal S¥- is used internally to the HAL to indicate ~ef~esh
states.
The signal SX- is used inte~nally to the HAL to c·ut off the
wait state to the CPU a4!ter one cycle.
multiplexe~.

A ti ming dia g~am of the Iftelftory s IJ stem, shown in Fig ure 2-3,
the maJor operations of the memory system .

ind i cate s

•

Texa s In strument s

2-22

P~elimjnary

- Jan 21,

1983

TECHNICAL REFERENCE

HARDWARE

The expansion inte~f.ce bus allows the addition to the syst~m of
standard and option devices.
Five expansion bus connectoT's are
p~ovided.
The expansion bus pin-outs a~e given in T.ble 2-8.
The expansion inte~f.ce bus allows memor~-mapped o~ lID-mapped
devices to be added to the system in iI straightforward wa~.
The bus
supports devices ~e~ui~ing inte~~upts for efficient ope~ation.
The
svstem does not p~ovide Direct Memory Access (DMA) hardware, because
devices that ~e~ui~e di~ect memo~y access have their own specialpurpose ha~dwa~e.
Table 2-8

Expansion Bus Pin-outs

PIN

SIGNAL

PIN

SIGNAL

AOl
A02
A03
A04
A05
A06
A07
A08

NMlDATA 7
DATA 6
DATA 5
DATA 4
DATA 3
DATA 2
DATA 1
DATA 0
WAITLOGIC QROUND
ADDRESS 19 ( MSB )
ADDRESS 18
ADDRESS 17
ADDRESS 16
ADDRESS 15
ADDRESS 14
ADDRESS 13
ADDRESS 12
ADDRESS 11
ADDRESS 10
ADDRESS 9
ADDRESS 8
ADDRESS 7
ADDRESS 6
ADDRESS 5
ADDRESS 4
ADDRESS 3
ADDRESS 2
ADDRESS 1
ADDRESS 0
(LSB)

BOl
B02
B03
B04
B05
B06
B07
B08
B09
Bl0
Bl1
B12
B13
B14
815
B16
B17
B1B
B19
B20
B21
B22
B23
B24
B25
B27
828

GROUND
RESET
+5 V powe~
IRO
(inte~rupt 0)
No connection (bussed)
No connection (bussed)
-12 V powe~
DMA(CPU enable>
+12 V powe~
OROUND
AMWC- (m.mo~y write)
MRDC- (memo~v ~ead)
AIOWC- (I/O w~ite)
IORC- (I/O ~ead)
No connec~ion (bussed)
No connection (bussed)
No connection (bussed)
No connection (bussed)
No connection (bussed)
PCLK (5-MHz clock)
IR6
(inte~~upt 6)
IRS
( in t e~ ~ up t 5 )
IR4
(inter~upt 4)
IR2
(Inte~~upt 2)
I R1
( in t e~ ~ up t 1)
No ~onnection (bussed)
RFSH (ref~eshing)
ALE
(add~ess liltcn)

B29

+5 V

B30
B31

OSC
(i 5-MHz c 1 0 c k)
GROUND

2-24

Prel i minary - Jan 21.

A09
Al0

AU
A12
A13
A14
A15
Al6
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31

Texas Instruments

B26

powe~

1983

TECHNICAL REFERENCE

2.7.1

HARDwARE

Expansion Bus Signal Descriptions

...

NMI-.
The non-maskable interrupt signal is driven by one o-t:
the expansion boards to interrupt the system processor.
Its
normal use is to indicate a system parity error condition.
This line is pulled low by an open collector large-scale
integration (LSI) device when driven by an expansion board.

...

DATA 0-7.
These bidirectional
signals carry
the data
bet ...een the processor.
memory,
1/0.
and the expansion
int.,...pace.
These lines are active high.
They can be tristated by use o.p the DMA- line .

...

WAIT-.
This signal indicates when a device in the system or
expansion bus is to hold or is holding the system p,..oc@ssor
in or de,.. to extend the length o.p a memory re.presh 0,.. 110
cljele.
When a slow device is addressed on the expansion
bus.
the signal can assert th is 1 ine 10... in order to extend
the time to complete a cycle.
An expansion boaT-d,
which
takes over the bus, must monitor this line when accessing
memory or 1/0 devices within the system.
(This line should
neve,.. be held 10 ... longer than 10 processor clock cycles. )
This line is pulled low by an open collecto,..,
LSI device
... hen driven by en expansion board .

...

ADDRESS 0-19.
These lines a,..e normally driven by the system
processor to address memory and 1/0 devices within the
system.
They can be tri-stated by use o.p the DMA- line.
They can be driven by an expansion bus board by asserting
the CPU ENABLE line low.
These lines are active high.
Only
XAO - XA9 are used .par 1/0 addressing .

...

RESET.
This line resets 0,.. initializes system logic an
power-up or during a power .pailure.
This signal is active
high.
RESET is generated by •
power supply monitoring
device.
During po .... r bro ... nouts or other times that the 12-V
line drops below 11. 1 V,
the RESET line is activated
immediately and returns 10111 3 ms a.pter regulation has
resumed.
This "'ill allolll .par unattended restarts .

...

INTERRUPT 0-6.
These lines signal the p"'ocessor that an 110
device req,uires attention.
In the. event ot: several devices
req,uiring service at the same time, the device asserting the
1 o ... est-numb .1'e d 1 i ne gets serv iced .f!i'T" st.
Th e se 1 ine s are
active high .

...

DMA- (CPU enable>.
This line,
when asserted low by an
expansion board, causes the processor to give up the system
busses and enter a wait state.
This alloUls an expansion
board to implement OMA or another processor.
When asserting
this line, the expansion board must wait until the sl:jstem

Texas Instruments

2-25

Preliminary - Jan 21.

1993

HARDWARE

TECHNICAL REFERENCE

busses are inactive (i. e.,
when MWRITE, MREAD, IOWRITE,
IOREAD are all inactivea).
When deasserting CPU enable,
the
expansion board must ~ir5t wait until the bus has been
inactive ~or two processor clock cycles,
assert the WAITline, de-assert the CPU enable line, and continue to hold the
WAIT- line ~or one additional clock cycle.
This will allow
the system processor to correctl~ execute its next bus
ev cle .

*

AMWC- or MWRITE- The memory write signal is normall~ driven
by the system processor.
It indicates that the in~ormation
on the data bus should be written to memory at the address
given on the address bus.
This signal is active low.
It
can be tri-stated by use o~ the DMA- line.
This signal can
be driven by an expansion bus board a~ter the CPU enable
1 i n e i s ass er ted.

*

MRDC- or MREAD- The memory read signal is normally driven by
the system processor and indicates that the memory addressed
by the address bus should be placed on the data bus.
This
sign~l is active lo~
It can be tri-stated by use of the
DMA- line.
This signal can be driven by an expansion bus
board after the CPU enable line is asserted.

*

AIOWC- Dr IOWRlTE- The I/O write signal is normally driven
by the system processor.
It indicates that the I/O. device
addressed by the address bus should accept the data on the
data bus.
This signal is active 10111.
It can be tl"i-stated
by use o~ the DMA- line.
This signal can be driven bV an
expansion bus board a~ter the CPU enable line is asserted.

*

IORC- Dr IOREAD- The 110 read line is normally driven by the
system
processor.
It indicates that the I/O device
addressed by the address bus should place its data on the
data bus.
This signal is active 10111.
It can be tri-stated
by use o~ the DMA- line.

*

PCLK - processor clock.
This is the system clocle.
It is a
one-third division of the OSC clock and has a period o~ 200
n s ( 5. 0 MH z >.
Th eel 0 c k has a d u t y c y c 1 e 0 ~ 37.' per c e n t
(+/-3.0 percent>.

*

RFSH

*

ALE - address latch.
This line indicates when the processor
is placing a valid addT'ess on the address bus.
The address
is valid on the ~alling edge o~ this signal.
This signal
cannot be tri-stated, and it should not be used by any
device accessed by an expansion bus DMA controller.

*

OS C

re~reshing.
This line indicates that a memory
cycle is taking place.
Wh en
It is positive tr ue.
this signal is asserted all expansion bus activity is
ignore d.

Dr

re~resh

( c 10 c k ) .

Texas Instruments

This signal describes a high-speed clock with
2-26

Preliminary - Jan 21.

i983

HARDWARE

TECHNICAL REFERENCE

a 66.7-ns
cycle.
2.7.2

pe~iod

(15.0

MHz).

Expansion Bus Loading and

It

D~iving

has

a

50-pe~cent

duty

Requirements

The expansion bus is designed to drive ~ive expansion boards.
Each
board may have no more than two LSI/TTL input loads on anyone line
o~
the bus.
Open collecto~ outputs. which drive the bus. should be
able to sink 12 mA at 0.5 V.
Data bus drivers should be able to'sink
24 mA at ~ 5 V and sou~ce 3 mA at 2.4 V and 15 mA at ~o V.
Drivers
~or
the int.r~upt lines IRO-IR6 should be able to sou~ce 1 mA at 3.5
V and sink 1 mA at 0.5 v. Drivers ~or the address and control bus in
iI OMA application should be able to sink 20 mA at 0.5 V and SOUl'ce
5
mA at 2. 4 V.
2.7. 3

Timing on Expansion Bus

H.mor~

The memor~ bus c~cles can be lengthened in integral multiples o~ the
CLK cycle time <200 n5) by the use o~ the WAIT- line.
Figul'e 2-4
provides the timing relationships o~ the expansion bus memol'Y
i nterfilc e.
2.7.4

Direct Memory Access

~l'om

Expansion Bus

The expansion bus interface has the minimum facility re~uired to
implement a ~ol'm of dil'ect memory access (OMA)'
This section
describes some of the design requil'ements of an expansion board that
would usa this facility.
The DMA designed into the system can be used to access memory on the
motherboard or standard option RAM board and any additional memo~y or
1/0 devices interfaced through the expansion bus.
The DMA Facility
can not be used to access 1/0 devices located on the mothe~board,
•

A board that implements OMA must simulate the processol' with respect
to the timing of input and output signals in order ~or the prope~
opel'ation of the system.
This implies specific phase relationships
with the processor clock (PCLK) and the ability to recognize WAlTsignals from the memol'Y or othel' peripherals.
.\

The ~oIIowing
Figure 2-5.

discussion relates to the OMA timing diagram shown in
du ty

*

PCLK:
eye Ie.

*

CMDi-:
Command input to the DMA controller.
This signal is
the log i cal OR" 0 ~ t nee x pan s ion bus s i 9 n a 1 s MR DC-. AMWC -.
lORC-. and AIOWC-.

The 5.0-MHz processor clock has a 37.6-percent
All signals are synchronous to this clock.
II

Texas Instl'uments

2-27

P~eliminary

- Jan 21.

1983

t--

133 --4 67 1---- 200

------1

-t

(Y1

0
::t:

PCLK

Z

t-4

ALE

_--',

\L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....Jr

ADDRESS

----,>e::x____________

.x::

~VA~L~IO~AD~O~RE~S~S_____________________________________

~ A ~

HRDCI\r~wc-

.1-

---------,

\. L

1\..1

•

LEGEND:

C)

El

F)

G)
H)

II

J)
K)

\\-____---J1

---t

J

t

ADDRESS SETUP TO COMMAND
ADDRESS HOLD FROM COMMAND
COMMAND ACTI VE
COMMAND DELAY FROM PCLK
WAIT - ACTIVE SETUP
WAlT - HOLD
WAIT - INACTIVE SETUP
DATA VALID AFTER AMWC - ACTIVE
DATA HOLD AFTER AMWC - INACTIVE
REQUIRED ACCESS TIME FROM MRDC - INACTIVE
DATA SETUP TO MRDC - INACTIVE
DATA HOLD FROM MRDC - INACTIVE
DATA SETUP TO PCLK LOW

M

Figure 2-4

LJ

/'

-1 I- D

F

-----------4--

K

--t

VALID

1-. H--

01

-{I
((I

t--+-

----------------{<=============:;X
I

A)
8)

.....

H

..

DATA
(READ

--1 Ii

r-- ---t
--------------~~~====JX~----------v-Al-I-D--------------------~)
, I--

m

--f E ...... F

:u

(Y1

"1l

gJ
(Y1

zn

,~-------

I

~

r

(Y1

n_

--t D I---

I\J
I

-t

\~--------____--~I
toC - - ..
":"I

WAIT-

DATA
(WRITE)

8

0

1-- L

. )----------

72
176
575
35
40

MIN
MIN
MIN 375 MIN (WITHOUT WAIT STATE)
MAX 10 MIN
MIN
o MIN
50 MIN
120 MAX
EXPANSION 8US
108 MIN
515 MAX 315 MAX
MEMORY INTERFACE
77 MIN
-4 MIN
TIMING DIAGRAM
50 MIN

Expansion Bus Memory Interlace Timing Diagram

-t

-t

~

•II
M

:J:

....oZ

IA

4

J

2

5

7

6

9

8

11

10

12

14

13

"1l

I

I

•

I

/I

\ \
\

,.

\

I

LI

WAIT O- --~----------------------or-\,-_1L.-

II.)

::u

rn

PCLK

I\l
I

•r-

.1

moO -

-0
I

-,

=lr

50 HIN -;,-OMA-

I \

~~

I

ILl

\\

20 t1AX

II

\\

--,t-

l7

~

WAITI -. WAlTo-' CHD n - MUST HEET TIlE SPECIFICATIONS SHOWN ON THE I1HIORY INTEPFACE ANn 110
INTERFACE TIMING DIAGRAMS.

nm x-

=

__. ./-Jl
.

ANY ONE OF TIlE BUS SIGNALS: AHWC-, '-lIRC-, JORC-, AIOWC-.

Figure 2-5

DMA Timing Diagram

35 HIIX

~
rn
zo
rn

HARDWARE

TECHNICAL REFERENCE

*

CMDo-:
Command output from the DMA controller.
This car. be
anyone of the command ~igna15 to the expansion bus (MRDC-.
AMwC-. IORC-. AIOWC-L

•

WAITi-:
The expansion bus WAIT- signal, which is monitored
by the DMA controller during DMA command cycles to determine
when to lengthen the command cycle.

*

WAITo-:
The expansion bus WAIT- signal as driven by the DMA
controller at the end of a DMA sequence.

*

DMA-:
This line causes the expansion bus control signals
(MRDC-. AMWC-,
IORC-. AIOWC-), the address lines (AO-A19),
and the CPU data bus lines (DO-D7) to go to the tristate
mode and the processor to be put into a "WAIT" state.

To initiate a DMA se~uence, the controller must monitor the bus for
an end to all activity.
The signal that shows the bus activity is
CMDi-.
The CMDi- signal is monitored until it goes inactive (HIGH).
The DMA- signal is then set active on the bus.
The DMA- signal must
be set active within the interval from 50 ns after the falling edge
of PCLK to 20 ns after the rising edge of PCLK in order to prevent
glitches on the expansion bus command lines.
The command out lines
may be driven to the high state immediately on the activation of DMAThe address lines from the DMA controller should not be driven
until 30 ns .fter the DMA- line goes active in order to prevent bus
call i sions.
In Figure 2-5 this seq,u ence is shown in sta tes 1 an d 2.
For proper operation of memory and other devices. a minimum of two
clock cycles must separate commands on the bus.
Therefore, the DMA
controller should not activate a command output until the second
falling edge of PCUK after DMA- is made active.
Figure 2-5 shows
CMDo- going low after the falling edge of state 3.
Once a command is begun from the DMA controller. the controller must
monitor the WAIT- input 1 ine for a possib Ie wait state.
This line
should be latched on the falling edge of PCLK during CMDo- active.
If it is inactive (high). the end of the command cycle is indicated
If it is active (1ow), then the cycle should be extended by an
additional PCLK period and the WAIT- should be monitored again.
There is no hardlllare in the system that limits the number of wait
states which could occur,
but no peT'ipheral or memory device is
expected to insert mOT'e than ten wait states in any command cycle
Tlllo DMA c'lcles are shown in Figure 2-5.
One cycle contains a wait
state (t4, t5, t6) and one does not (t9.
tlO).· Note that the
successive cycles aT'e two PCLK cveles apart.
When the DMA controller is ready to give up the bus. it should assert
the WAIT- line itself on the ~alling edge of PCL~ after the last
command cycle.
On the next r-ising edge of PCLK, the DMA- line should
be made inactive and the control and address lines from the DMA
controller should be tristated.
The tristate acticn should occur
within 30 r,s after the DMA- line is made inactive.
The WAIT- line
Texas Instruments

2-30

Preliminary - Jan 21,

1983

TECHNICAL REFERENCE

~

HARDWARE

0'

should b~ made inactive on the second 'ailing edge
PCLK a'ter it
is made .ctive.
This ""ill ensure that the ~irst command cycle o~ the
CPU is at least two full peLK c~cles long.
Figure 2-5 shows this
seq,uence in st.tes 11 to 14.
refresh occu~s transparentl~ through a controller that meets
the above requirements.
The number o~ consecutive DMA command cycles
""hich can be run is not limited except b~ the system so;tware
req,uirements.
Memor~

It may be desirable for a DMA controller to provide 4. 7-kohm pull-up
resistors on the bus comm.nd lines if the tristate .ction does not
overlap in order to prevent glitches on those lines.
Pull-ups should
not be req,uired on the address or data lines. as these do not affect
logic st.tes lIIithout the command lines.
Note tha~ the address and
data setup and hold times for the controller should Meet or exceed
the specifications for the expansion bus running under the processol'
even if the DMA .eq,uence must be padded lIIith extra clock cycles to
accomplish this.
2.7.5

1/0 Timing On Expansion Bus

The following information is provided to sholll the expansion bu~
timing for standard 1/0 c~cles.
Note that this timing includes thp
one wait state that the motherboard al""a~s includes on 1/0 c~cles
The s~st.m bus 1/0 timing relationships are shown in Figure 2-6.

Texas Instruments

2-31

Prel iminar~ - Jan 2L

1983

....

~

J:
Z

----i 67 J.--- 133 -1--

200

....

---1

o
~
r

:;u
III

PCLK
I

ALE

----~II

ADDRESS

\~

________________________________________

>e:

VALID ADDRESS
I
,

--1 0 1--

E

__________________~

I'J
I
t.l
I'J

.....
....

....
:3
3

III

"i
o.C

.....

-0
lD
t..:1

--~
...

I /

~

F

--10~ G~

t-

....

DATA (WRITE)
I r--v--------:"~~~----------~---..;--------------'___...J\
VALID DATA
)
H - - - - - - - - -........,....-

~

Jr-

REQIJIREO
VALID I )
DATA (REA!!.D)L-.:.._ _ _ _ _ _ _-<==============~X(""'i~O'-).-------

I-- K--'

~

111

C

------~
...
I
I

\

,..

"tJ

I-

----------------I \~----------------------------~I I
,

LEGEND:

A) ADDRESS SETUP TO PCLK LOW
8) . ADDRESS SETUP TO AIWOC- OR 10RCC) ADDRESS HOLD AFTER AIOWC- OR 10RCD) COMMAND DELAY FROM PCLK
E) ACTIVE 10RC- OR AIORC- TIHE
F) DATA VALID FROM AIOWC- LOW
G) DATA HOLD AFTER AIOWC- HIGH
H) REQUIRED ACCESS TIHE FOR 10RCI) REQUIRED DATA SETUP TO RISING EDGE OF 10RCJ) REQUIRED D~TA HOLD AFTER RISING EDGE OR 10RCK) REQUIRED DATA SETUP TO PCLK LOW

Figurw 2-6

III
Z
III

----....X

AIOWC-

"YJ
o

t-A-1
---'--'
8 ---.,

IORC-

~~

62 HIN

72 HIN
176 HIN

35 MAX 10 MIN
575 HIN

MAX
HIN
515 HAX
85 HIN
-4 MIN

120
108

50 MAX

ExpansiDn Bus 110 Interface Timing Diagram

TECHNICAL REFERENCE

2. B

HARDWARE

FLOPPY DISK CONTROLLER SUBSYSTEM

SL-t ~J.f

disk controller subsystem consists Or a floppy disK
IC (FD1793-o2), a rloppy disk suppo~t logic Ie (WD1691),
and a pulse delay IC (WD2143),
all of which are made by Western.
Dig i t .. l.
I t also has a vol tage-c ont~oll ed osc i llator (VeO), one-ha I f:
of a 74LS221 one-shot, two 2114 static RAMs used as a sector bur'er'
and add~es5.d bV a CMOS 4040 counte~, a p~og~ammable array logic
(PAL) IC used fo~ decoding and control operations. and
miscellaneous
logic used for the timing and buffering of signals.
The

floppy

controll.~

The sUbsvstem consists of several sub-subsections, including:

*

The disk

*

The sector buffer

*

The d.. t ..

.*

*
2.B.l

cont~oller

~rit.

IC

precompensation circuit

The data separator
The floPPV drive

(01'

diskette drive) cable interface.

Floppy Disk Controller

The floPPV disk controlle~ (FDC) is the FD1793-02 chip.
This IC is
responsible .par se~ial/pa~allel data conversion, locating sectors on
the disk, seeking the diskette d~ive. and othe~ high-level functions.
A complete
d.sc~iption
of the FD1793-o2 chip can b. found in tne
literature available .prom Weste~n Digital.
The input clock to the
controller is at 1.0 MHz to provide the correct data rate 'o~
standard 5-1/4-in diskettes.
Since the clock is divided down from
15.0 MHz in U20, the duty cycle is 467 ns 10111, 533 ns high.
,'\

2.B.2

Sector Buffer

,

Data transmitted f~om or to the diskette drive during a read or write
operation must occur as Fast as 23 us per byte or 32 us per byte
nominal for double-density operation.
In order to allolll proper
operation of the diskette drive IIIhile other processor operations are
occuring, a sector buffer that can operate independently Or the
processor for the duration of a sector read or write is implemented
This buffer consists of a 1 kbyte x 8 static RAM (2 x 2114),
a
counter to address the RAM se~uentially, and control logic and a bus
buffer to allolll the CPU and the FDe to access the bur~er.

Texas Instruments

2-33

Pl'eliminary - Jan 21.

1983

HARDWARE

TECHNICAL REFERENCE

'.
2. B. 2. 1 Sector Bu-F-Fer Modes.
The buH:er has -Four basic operating
modes controlled by two bits (1'10, 1'11> in the latch U47.
These modes
are as -Follows:
LATCH U47 BITS
I'll
MO
1
1

o
o

1

o
o
1

MODE OR FUNCTION
FDe
FDe
CPU
CPU

reads
reads
reads
reads

RAM and writes data to diskette.
diskette and writes data to RAM.
or writes RAM sequential IV.
or writes the FDC directly.

The counter that addresses the bu-F'er is automaticaliv incremented
a-Fter each access o-F the RAM bV either the CPU or FDC.
The CPU can
reset the address counter to set up a -Fixed starting address within
the RAM by .lIIT'iting to the FDC sector register ",hile the I'll. 1'10 bits
are set to 0,0.
This does not a.p.pect the FDC itself, because the FDC
can be accessed bV the CPU only in mode 0,1.
The control logic '01' the sector bu,.per is provided bV the PAL and by
a -Flip-.plop, which is used to provide a i-us FDC clock-sllnchronized
signal derived 'rom the FDC data request 
unused

FDe

MODE 0, 1

-------+--+--+---+--+--+---+--+--+---+------------------------L

VAl

L H

L

MODE

0. 1

-------+--+--+---+--+--+---+--+--+---+-------------------------

FRD-

L

L

CPU <-- FOC
FOe - ) RAM

MODE 1,0

CPU - ) FOC
FOe <- RAM

MODE 0, 1
MODE 1, 1

MODE 0, 1

------+-+--+---+--+--+--+-+--+---+----------------

FWR-

L

L

°

----+--+--+---+--+--+--+-+~--+--------------

RWE-

L
01'

•

L L
H L

L

H

L

CPU - ) RAM
FOe - ) RAM

MODE 0,
MODE 1,0

-------+--+--+---+--+--+---+--+--+---+------------------------RCS-

''--"

L

L

L

L

L

CPU

<-)

RAM

MODE 0.0

MODE 1,X
FOe <--) RAM
H
H
----+--+--+---+--+--+-+-+--+---+-------------RRSTH L
L L
L L
RESET COUNTER
MODE 0,
01'

.

01'

•

L

L

°

unused

------+--+--+---+--+--+--+--+--+---+------------------------CPU <--) RAM
MODE 0.0
FDEN- L L
L L
L
MODE 0, 1
01' •
L
CPU
<--)
FOC
L H
L

\..

..
Texas Instruments

2-35

Preliminary -

Jan 21.

1983

HARDWARE

CONTROL.L.ER WRITING TO RAM

1 MHZ eLK

\

-l

V

ORO

I

I
~

1/
ORaD

~L.

Ml-H

FRO·, RWE·, Res·

r\
I

DATA

\

VALID

READ Foe

WRITE RAM

CO NTROL.LER READING RAM

, MHZ eLK

V

ORO

J

\

J

~

J
1/

r\

ORQO

FWR, RCS

f

Figu~e

Texas

J

~

DATA

Inst~uments

2-7

MO, Ml-H

\

VALID

READ RAM

WRITE

Foe

Floppy Disk Timing Diagrams

2-36

P~eliminary

- Jan 21.

1983

TECHNICAL REFERENCE

2.8.3

Flopp~

Disk

HARDWARE

Cont~oller

Write Precompensation

Disk write precompensAtion is re~uired ~hen ~riting double-density
data using modified fre~uenc~ modulation (MFM) in orde~ to reduce the
"bit shift", ~hich results when certain data patterns are written on
the magnetic media.
Unless the bit shift is compensated Tor,
it
moves the read data t~Ansitions outside of the rAnge ~here the read
circuitr~ can p~aperlv detect
them.
The bit shift problem gets
progr.s.ivel~
~orse
as data bits ara stored closer together an the
disk (as track length gets shorter to~~d the center of the disk).
Th. ideal situation is to Adjust the ~rit. hard~are graduall~ to
compensate for the bit shift as the track number increase..
However,
The
a compromise solution pravides results that are nearl" A5 goad.
m.thod used is to l.av. all compensation turned off ~hile the head is
ov.r the auter hal' af the disk.
When the head is over the inner
half of the disk, a compramise precampensation is turned an.
As the
nu.ber af tracks an a disk drive could be eith.r 40 ar SO, the choice
af the half~" point is left up to software (~hich checks far the
t"pe of drive installed>' This is ~h" the TG43 signal is contralled
b~ U47, nat the FDC.
(TQ43 - Track Greater than 43 - is historically
the halfwa" point for an 8-in diskette drive. )
Th. amount af precompensatlng bit shift is controlled b" th~
adJustment of R19, which controls the write pulse~idth through U1S .
the WD2143 IC.
The precompensation should be set At about 200 n'·,
~hile monitoring pin 1 af the WD2143 IC during a write operation.
The di~ection of bit shift is contralled b" the FDC signals EARLY and
LATE. These signals cause the WD1691 to select the tap along thc?
WD2143 (adjustable dela" line), which is appropriate #01' the bi t
pattern being ~itten.
If precompensation is not needed an outel'
trac ks, the TQ43 sig nal i nh i bits th e pre camp ensa t ion pro cess.
Secause single-dens it" fre~uenc" modulation (FM) encoded data does
not re~uire precampensation,
the
FD1691
also
dis.bles
the
precompensation when the double density signal (DOEN-) is inactive
(high>'

\

The data separator is comprised o~ twa parts:
clock recovery and
sepa'ration o~ the d.ta from the clack.
The actual separation o~ data
and cloc k sign.l. tak e. p lac e in the FD1793-03 FOC.
Th e 1691
contains the digital ci~cuits necessary to implement A phase-locked
loop (PLL) ~ith the 74lS628 chip providing the veo and the external
component. providing the loop 'ilt.~.
The one-shot U29 is used to
shorten and stabilize the pulsewidth of the incoming read pulses so
that the Pll and data recovery operations operate properly during the
lac k up interval.

2-37

Preliminary - Jan 21.

1983

TECHNICAL

HARDWARE

REFER~NCE

The purpose o~ the PLL is to pro~ide a continuous clock locked in a
speci~ic
phase relationship with transitions in the incoming data.
Fer this system the ~alling edge of the RDDATA- signal should be
nearly centered on the high or low pulse o~ the RCLK signal.
When the adJustments are made correctl~ tne PLL should be able to
lock up to an incoming pulse train with a range o~ ~requencies ~rom
217
kHz to 294 kHz (+/-15 percent) within 150 us.
The pulses should
be low going (2 us m'aximum applied to the RDDATA- input - P9 pin 30)
and the DDEN- line must be low.
Because o~ the analog nature o~ the PLL circuits, the pOlller s upp 1 V
voltage to the veo and the loop ~ilter is regulated with a linear
The regulator prevents an~ digital n~ise present on th e
regu lator.
5-V supp ly ~rom inter'ering with the operation o~ the PLL.
Note that the data separator is capable 0' working with either
single-densit" (FM) 0'1' double-densitv (t'FM) data, and the choice is
controlled bV the DDEN- line.
2.8.5

FloPPV Disk Controller Alignment

To adjust the write precompensation
pe'r'orm the 'ollowing steps.

and

data

se.parat0'1'

ci'rcuits,

NOTE
Alignment o~ the ~lopp~ disk controlle'r requires
access to potentiometers and locations on the
svstem unit board nO'rmallv located unde'rneath the
le.f!t diskette drive and, the're~o're. inaccessible
without pa'rtial disassemblv 0' the sVstem unit.
Be'o're attempting to align this circuit'rY, the
system unit boa'rd must be either partiall" 0'1'
completely. removed ~rom the system unit chassis.
Extreme caution must be used to prevent the
system unit boa'rd ~rom contacting the chassis
during alignment.

1.

Insert a diagnostics diskette in the
the door.

le~t

drive

and

close

2. PIa c e the s y stem un i t ON / OFF s wit c h i n t neON p 0 sit ion.
Following the power-up self-test. the diagnostics menu is
c:iisplav ed .
3. Monito'r the RDDATA- line at pin 11 o~ U14 to make certain
it is inactive (high).
If the diskette drive read logic is
peT'mitting noise,
or extT'aneous low level on the RDDATATexas InstT'uments

. 2-38

PT'eliminary - Jan 2i.

1983

TECHNICAL REFERENCE

HARDWARE

line, it may be necessary to disconnect till' plug attached
to J9 (the diskette drive control/data connector cable) on
the syst.m unit board (motherboard>.
With RDDATA- high.
the PU and PD- outputs 9rom the W01691 are 90rced to a
tristate condition.

(

4.

The voltage on the PUMP line must be checked and adJusted
to 1.4 Vdc.
Attach a digital VOM with a high (greater than
5 megohms)
input impedance to pin 13 01' 14 (thelj are tied
togethe,.) of U14 (W01691>.
AdJust R17 for 1. 4 Vdc,
+/5
percent (between 1.33 and 1.47 Vdc)

5. The

veo line must now be checked fa...

accu ... aclj.
Attach a
30-mHz (01' higher) oscilloscope to pin 16 o~ U14 (WD1691).
Use a lOX p... obe, internal trigger, O.2-Vdc/Div.
v .... tical,
O.1-us/Div.
tim.base.
AdJust Rla #01' a sCluare wave 0#
2.G-mHz +/- 5 pe,.cent (between 1.90 and 2.10 mHz).

6. Recheck the 1.4-Vdc reading at pin 13 01' 14 to make ce,.tain
that adjustment of R18 did not cause a change.
Re.dJust if
necessa1'".

7. Tne advanced diagnostics must be .ntered by
the CTRL and A keys at the same time.

-.

8. The drive alignment test
KEYBOARD, then key in:

must

performed

FLOTST TEST=ALIGN ORIVE=Cente,. 1,2,3,

pressing
by

both

.electing

0,. 4)

9. Remove the diagnostics diskette and insert a blank,
"scratch", diskette into the approp ... iate diskette drive.

01'

10. Turn on writ. data by keying in menu selection W.
11. Turn on write precompensation by keying in

P.

menu

selection

12. Attach a lOX oscilloscope probe

to U14 pin 5:
Trigger
positive
slope.
O.2-Vdc/Div.
vertical.
O.l-us/Div.
timebase.
The wavefor.l1 is visible only when the computer
is writing data to a diskette.
AdJust R19 for a positive
puls.width of 750 ns.
This adJustment results in a lAlT'ite
pulsewidth o~ 187.5 ns.
NOTE

,-

1ft R19 is set
to near its maximum value, the
write pulsewidth will be very long (the length of
an entire sector write).
Adjustment 0; R!9 must
only be made when appropriate test equipment is
monitoring the pulsewidth.

Texas Instruments

2-39

Preliminary - Jan 21,

1983

HARDWARE

2.8.6

Diskette Drive Interface

The diskette drives are inter~.ced through a series of buffers and
receivers that allow the use of low-impedance ribbon cables to
connect the signals fro. controller to drive. This su~te. implements
two connectors for the drives.
All signals driven bU the controller
except for the SID1- signal have separate drivers for each connector.
The receivers with their terminating pull-up resistors are shared
between the two connectors.
The connector P9 is designed to interf.ce to a 34-conductor ribbon
cable that has two. 34-pin. card-edge connectors. one for each of two
diskette drives mounted inside the svste. unit chassis. Since there
is alwa~s one diskette drive installed in the sustem unit.
it is
nor.all" mounted on the left side (as viewed bU a us.r). This drive
should be strapped for SELECT on pin 10 (drive 0>'
The select line
and all common lines .xcept pin 32 (side select) should be terminated
at this drive.
The other drive in the box (if present) should be strapped for SELECT
on pin 12 (drive 1) with onlv the select line terminated.
When two
drives are installed, a terminating resistor must be installed on the
right-hand drive (drive 1) ani".
NOTE

The flopp" disk
controller
and
individual
diskette drive logic signals assign drives using
the convention of: DRIVE ZERO. DRIVE 1. DRIVE 2,
and DRIVE 3 (for a four-drive s"stem).
The
diagnostics diskette uses a different convention:
DRIVE 1, DRIVE 2, DRIVE 3, and DRIVE 4 for a
four-drive svstem.
Operating systems mav use vet
anothe~ convention, such as
DRIVE A.
DRIVE B,
DRIVE C, and DRIVE D.
Care must be used to avoid
using the incorrect drive designator.

The second connector on the .ain printed wlrlng board (PWB) P13 is
designed to interface to .. 40-wire ribbon cable terminated with a 37pin, D-tuP& connector (which . . V be installed bU the user) mounted on
the back panel of the chassis.
All lines used .ust be terminated in
the external diskette drives.
If additional diskette drives are planned, all diskette drives must
be of the same tupe. That is, all must be either 320-kbVte drives
(double-sided, 48 tracks per inch (tpU) or all must be 640-kbyte
drives (double-sided. 96 tpi).
A Jumper on E1 to E2 i.elects 320kbVte drives. No Jump.n selects 160-kbvte drives.
A Jumper on £3 to
E4 selects 640-kbvte drives.
A Jumper ma~ be on either E1-E2 Dr E3E4, but not both.
o

Texas Instruments

2-40

PT'eliminary - .Jan

21,

1983

HARDWARE

TECHNICAL REFERENCE

-..

Th. d~iv.s should all be st~app.d fo~ head load with motor on if they
a ..... Iluipp.d with head load solttnoids.
Head load solenoids are not
n •• ded fo~ p~op.~ optt~ation of the diskette drives.
Th. signals STEP, DIRC. WQ. and WDOUT a~e buffered by the 74LS244 in
o... d.r to d~i v. the two stand al"d 7416 loa d s.
Th i s bu ff.r is nee e s sal' y
b.caus. the 1793 and 1691 a~e capable of driving only one TTL load.
The inp ut sign.ls WRITEPROT-,
INDEX-. TRKOO-.
and RDDATA- ar e
buff ..... d bV the 74LS244 to provide a small amount of hysteresis and
mo .... static p~ot.ction than the MOS-device inputs provide.
Th. pin-outs fa ... the int .... nal and .xt.rnal diskette drive connectors
on the moth .... bo.... d a .... giv.n in Tabl. 2-10 and Table2-11,
~esp.ctiv.l ...

Texas Inst... um.nts

2-41

Prel iminar" - .Jan 21.

1983

HARDWARE

Table 2-10

Inte~nal

Diskette

D~ive

ConnectD~

Pin-out

+------+------+-------------+--------+--------------------------+
I SIGNAL I RETURN I SIGNAL NAME I SOURCE I
FUNCTION
+------+------+-------------+--------+--------------------------+
1
+------+------+-------------+--------+--------------------------+
4
3
~

+-----+------+----~-----+------+---.----------------+

NC

5

+------+------+-------------+--------+--------------------------+
: DRIVE
Indicates index hole
8
7
I INDEX+------+------+-------------+--------+--------------------------+
10
9 : SELECT 1I SYSTEM I ~ive select 1
+------+-----+-------------+----"----+-------------------------+
11
I SELECT 2I SYSTEM I
D~ive select 2
+------+------+-------------+--------+--------------------------+
14
13
NC
+-----+----+------+0-------+--------------+
16
15
I MOTOR ONI SYSTEM: ~ive moto~s ON
+------+------+-------------+--------+--------------------------+
18
17
I DIRECTION: SYSTEM I Step IN/OUT di~ection
+------+------+-------------+--------+--------------------------+
20
19
I STEPI SYSTEM I
Step IN/OUT command
+------+------+-------------+--------+--------------------------+

22
21
I WR ITE DATA- I SYSTEM r Se~ i.l dat. to d~ i ve
+------+------+------~------+--------+--------------------------+
24
2 3 : WRITE QATE- I SYSTEM:
Enables w~iting to
d~ive

when low

+------+------+-------------+--------+--------------------------+
26

25

I TR ACK 00-

: DRIVE

Indicates head is
00 when lo~

ove~

t~ack

+------+------+-------------+--------+--------------------------+
28
27
: WRITE PROT- : DRIVE
Indicates diskette
is

lII~ite-p~otected

+------+------+-------------+--------+--------------------------+
READ DATA-

30

29

I

32

31

: SIDE 1--

: DRIVE

Se~i.l

I SYSTEM:

Side select (0.1
Hi g h • Low)

data

f~om d~ive

+------+------+-------------+--------+--------------------------+
c

+------+------+-------------+--------+--------------------------+
33
: NC
+------+------+-------------+--------+--------------------------+
* NC me.ns not connected
~

Texas

Inst~uments

2-42

P~elimina~y

- Jan 21.

1983

HAROWARE

TECHNICAL REFERENCE

~

To connect exte,.nal diskette d,.ives, a sho,.t cable assembl" with a
4o-pin connector links ..J13 on the sljstem unit board· ",ith
a
(recommended) 37-pin d-t"pe connector on the back panel o~ the system
unit. Tabla 2-11 gives the 4o-pin J13 signals.
D-tlJpe connector pin
numbe,.s a,.. in parentheses ( >.
Table 2-11

External Diskette O,.ive Connector Pinout

+------+------+-------------+--------+--------------------------+
ISIGNALIRETURNI SIGNAL NAME I SOURCE I

FUNCTION

+------+------+-------------+--------+--------------------------+
12 (1)11(20)1
+------+------+-------------+--------+-----~------------------+
1 4 (2) 1 3 (21) 1
NC
+-..----+----+----------+-----~-~--------------------+

16(3)15(22)1

NC

19 (4)17(23)1

NC

110 (5) 1 9(24) 1

NC

+-----+-----+---------+----+-----------------++---+----+--------+-----+-------------------+
+-----+-----+-------+-----+---------------+
112

(6)

111 (25) 1 INDEX-

I

DRIVE

Indicates index hole

+------+------+-----------+--------+-----------------~-------+
f 14 (7) 113(26) I MOTOR 3-

+-----+----+--------+--------+-----....-_-------------+
I 16 ( 9) 115 ( 27) I SELECT 4-

1 SYSTEM I

D,.ive select 4

+----+-----+---~-----+-----+-------------+

119 (9) 117(29) 1 SELECT 3-

: SYSTEM I

D,.ive .elect 3

: 20( 10) :19 (29): MOTOR

I SYSTEM I

Drive

I SYSTEM:

Step IN/OUT direction

+------+-----+----------+----+------------------+
4-

mat~r

4 enable

+------+------+-------------+--------+--------------------------+
122(11)121(30) 1 DIRECTION-

+------+------+-------------+--------+--------------------~---+

124(12) 123(31) I STEP-

I SYSTEM I

Step IN/OUT command

+------+------+-------------+--------+--------------------------+
126(13)125(~)

I

WRITE OATA- I SYSTEM I

Serial data to drive

+------+------+-------------+--------+--------------------------+
'29(14)127(33) 1 WRITE QATE- I SYSTEM I

Enables

130(15) 129(34) I TRACK 00-

Indicates head is over
t,.ack 00 when low

~rite

"'hen low

+------+------+-------------+--------+--------------------------+
I

DRIVE

+------+------+-------------+--------+--------------------------+
132(16)131(35) 1 WRITE PROT- : DRIVE

Indicates diskette
is lII'rite-protected

+------+------+-------------+--------+--------------------------+
134(17) /33(36): READ OATA-

I

DRIVE

+------+------+-------------+--------+--------------------------+
136(19) /35(37) I SIDE 1/ SYSTEM: Side select (0 = High)

+------+------+-------------+--------+--------------------------+
139(19) 137
NC

+------+------+-------------+--------+--------------------------+
140

139

NC

"-. - +------+------+-------------+--------+--------------------------+
* NC means not connected
Texas Instruments

2-43

Preliminarlj - Jan 21,

1983

Pl(KEYBOARD) The keyboard is a 'airlv
keyboard electronics functions include:

*

simple

subassembly.

The

Scanning the keU .4trix

* Decoding new kevs depressed by the operator
•

Transmitting data to the system unit

* Receiving commands from the svstem unit
•

Performing N-key rollover

*

Implementing a

*
*

Locking/unlocking the keyboard

2.8.7

soft~re

switch6ble repeat-action function

Performing a set of self-diagnostics
Encoding Keustrokes

The encod.r detects va-lid kevswitch state changes,
looks up the
proper key code, and transmits the keycode as an 1i-bit stream to the
system unit.
Each key causes either one or two bytes to be
transmitted, based on the status of the SHIFT. ALT.
CAPS LOCK. and
CTRL kevs.
For specific details on the byte definitions, refer to
Section 3. subsection 3.1. "Keyboard DBR."
2.8.8

Transmission

Transmission from the keyboard to the system unit is done at a rate
2440 baud +/- !.50 percent. The kevb~ard transmits ~hen one of
two conditions is met.

0'

*

When a valid leey depression has been detected,

*

When a system command is understood and acted upon

or

In the case of a key depression •. the proper keVcode byte or bytes are
sent across the keyboard transmit line in response to the user
depression of .. leev.
(Re'er to Section 3, subsection 3.1, "Keyboard
DSR, II for details on kevcodes.)
In some cases
repeat-action
transmissions mav also be re~uired following keV depression.

Texas Instruments

2-44

Preliminary -

~an

21.

1983

TECHNICAL REFERENCE

HARDWARE

In the case of response to a system unit command, the keyboard
transmits the proper response code to the system unit to indicate
that the action req,uired has been taken.
System unit command s an d
ke~board responses are given in Table 2-1~
Table 2-12

Keyboard Commands and Responses

KEYBOARD RESPONSE

SYSTEM UNIT

COt't1AND

CODE

CODE

(J-EX)

Perform a power-up
.el~-test and install
default parameters
00*
Turn typamatic ON
Turn t,pa.atic OFF
Lack keyboard
Unlock ke,board
K.,click ON
K.,click OFF
Re •• t (same as 00)

........

71
72

Self-Test OK
Keyboard ROM error
Keyboard RAM error

70
70
70
70
70
70
70

Self-Test OK

70

01*
02

03
04*
05**
06**

07

Keyboard ROM error
71
Keyboard RAM error
72
(two-b yte code)
70.73

os

*
**

MEANINQ

(i-EX)

Indicates default parameters
Keyclick req,uires hardware modification.
It is not presently supported.

NOTE
I~.Table 2-126 the Code column
gives the codes
entered on the keyboard.
The Keyboard Response
Code column gives the code sent·by the keyboard
microprocesso,..
The keyboa,.d ,.asponds to every
valid command.
Typically, the self-test II OK II
code 70 is returned to the system unit (except in
the case of a failure during self-test>.
If the
s,stem unit command is ignored (for reasons such
a. par i ty error,
un known command,
start bit
error, or other error), a response code is not
returned.
In such a case,
the system unit
retries the command .

•

Texas Instruments

2-45

Preliminary -

~an

21,

1983

TECHNICAL REFERENCE

2 8. 9

HAt< JJWAH I:.

P oilier

This line is locally
The keyboard connection includes a 12-Vdc line.
regulated on the keyb'o.rd to 5 Vdc
(to prevent voltage drops and
electrostatic discharge (ESD) problems).

2.9

CRT CONTROLLER BOARD

The CRT controller board dri¥es either a monochrome .nalog or a color
TTL display.
As a stand-alone option, the controller provides one
page of high-resolution (80 columns x 25 lines) .lph.numeric display.
This board also provides the signals re~uired by the addition of an
option.l, graphics video controller piggyback board.
The addition of
the board makes the Texas Instruments Professional Computer a
complete alphanumerlcs and raster graphics system.
No physical
distinction exists bet~een color and monochrome; the board provides
both eight-level gray scale and eight-color RQB (Red,
Oreen,
Blue)
outputs.
Color is determined bV the monitor used.
Figure 2-8 shows
a block diagram of the alphanumeric CRT controller board.
Refer to
Section 5, drallling 2223011, for logic diagrams.
2.9.1

Display Characteristics

*
*

Twenty-five lines of 80 characters

*
*
*

A horizont.l scan rate of 19 200 lines per second

A resolution
vertic.lly

of

720

pixels

horizontally

x

300

pixels

A vertical sc.n rate of 60 (50 frames per second)
A dot r.te of 18.0000 MHz

Texas Instruments

2-46

Preliminary -

~an

21.

1983

(

-.

(

-.-

l

-.

ftI

111

"

0

II

Z

III

_

-

... Ikn

~

CRTC Solo"

"ddt...
MUll

I

I---

2K.B
AIl,_
R"M

1854Ii
CRT
Conllol

r---r--

Cit .pltocs
CORfWtct

1}=

Oo,R_oVIdMtsc

"'It~."h
L-

CRT
Sv...m
Decodto
logIC

..

C~~I~
R"MSeIo<.

f-

G

Con,!!""

I

(lIuIlO,

~

~ """'-U
CRI

ftI
........

...
3

:::I
III
.....

~h
It.·h:h

C.,mlM:LI

I
I

,

Inl~lIupl
loy.(

I

t

IBull..
I

Butte.

- --- .-~

fi~

~
g~

-

fi

,

t-t--

Allr.tkiUI

logIC

t

..J..

0

t---

L.--

,....-Chat

f'--

(;en

ROM
41< .8

.....

.lJ

m
W

'---

-:::;-

-

..Sac",
_.0<1
fooOplfon
CNt,Gen
EPROM

r-''---

SM.
Roy

if t
L-..

CRI DuI_Chat T - .
CPU CRT ",bit,."on
lMItnolloc De, 00,•

T

c

Figure 2-8

0
0° CDim
0°

I--

I - t---

L...--

Oo,R_

VodIIo OUI
COllnl!C IOf!a

t-!.

§ I---r-

~

I

~

II

,.........Sync La.ehu
.--

,.........

, (I

I I

I

....!!..
S.,!)h''''

Il~h

D.,. a...

~-~

IL

~

It I

ITI

Oo.Row

A1Ifllbul.OI••

I

,..

CitOj>llo<.
001 Dala

CharK'II' 0.••

~

,OJ>IIU

\

.--

-

-

>

r::u

Conneu

....--

E.

C

2k18...
ChatK
RAM

0

Grilptltcs

~

I

5 ~Shun

, II , I

Z
....

Rel,. "ddt...

,112-,

"'0
'1

)

Alphanumeric CRT Controll.r Board Block Diagram

MOlloch,anlt:

MOIU.ll:lullll~ CQfl"tlrler

ITI

Z
0

P1

2.9.2

AttT"i bute.

The controlleT"'s video memory is oT"ganized as 2 kbvtes x 16 bits.
The fiT"st eight bits convev characteT" i nformati on.
The sec and eigh t
bits select the following attrib utes on iI chilrilctel' basis:

...

Bit 0,

Intensi tv Level 1 (BLUE)

...

Bit 1,

Intensi tv Level 2 (RED)

Bit 2,

Intensi tv Level 4 (OREEN)

...
...

Bit 3, Chill'acteT" Enable

...

Bit 4, ReveT"se

*

Bit S, Und eT"l i ne

...

*

"
Bit 7,

Bit

Blink
Al t "T"na t e ch.-racteT" set

NOTE

\

The thr.ee intensit~ bits (bit 0 through bit 2)
deteT"mine the gT"ay scale intensitv level and the
ROB outputs faT" caloT".
Thus.
hi/naT"m video in
monachT"ame is handled by a one-of-eight intensitv
select instead of .- high-intensitv bit.
To acce.s the attT"ibutes, the saft"''-T''e "'T"ites an attT"ibute latch ",ith
the value of the attT"ibute foT" .11 chaT"ilcteT"s subse~uentlv written to
the SCT"een as long as no SCT"een T"ead is dane.
When any chaT"aC'teT" an the SCT"een is T"ead, its .-ttT"ibutes aT"e copied
to the attT"ibute l.-tch wheT"e they aT"e T"ead bV a subse~uent latch T"ead
aperiltion.
This method of handling the attT"ibutes allolils the softwaT"e to do
"block moves" of sC'reen d.ta fT"om Dne .c,.een .,.ea to anothel' with the
att'ribute. of e.ch ch.T"ilcteT" moving with the character.

Texas InstT"uments

2-48

P'reliminal'Y - '-'an 21.

1983

TECHNICAL REFERENCE

-

2.9.3

Characte~

HARDWARE

Sets

The video cont~oller contains a 4K character generator ROM, which
provides for 256 characters.
lit
socket is provided to allow ~or
optional 2K or 4K ROM/EPROM. which can expand the character set to a
maximum of ~12 chAracters.
Attribute bit 7 selects the expanded
character set.
2.9.4

Cursor

The cursor can be programmed to be blinking or nan-blinking. reversevideo block or unde1'lined.
The display of the cursor is handled by
the ha~dware through a special set of registers in the controller.
These registers allo~ the software to position the cursor anywhere on
the scr •• n (01' off the screen if no visible cursor is desi~ed>'
2.9.5

'-

SC1'olling

Th. hard.ar. supports cha1'acte~ lin. scrolling in fou~ di1'ections by
main tai n ing a n sc~e.n start I. reg ister.
When th e sof twar e determine s
a need fo'r a sC'roll. it changes the value of this register by oneline. causing the sC'reen to appea~ to Jump b" one line.
Th~
sC'rolling operation al..,ays a.f.fects all of the screen, that is. it is
not possible to sC'rqll one region without affecting anothe'r.
Since the cont1'olle'r is e~uipped ..,ith anI" 2 kb"tes of screen memory,
sC1'olling 'results in a "~1'ap" of the original top line of screen
content. to the bottom of the screen. Therefore, the software i~
re~ui1'ed to clea'r the top line of the screan (01' bottom)
before the
sC'roll-up (0,. -do~n) ape"ation.
To simplif" programming of the line
clear operation, the 2 kbytes of memor" is phantomed over a 4-kbyte
add,.ess spac e.
•
When a status line is i.p lamented, it mu st b. done in so ftware.
Tha t
is.
dU'ring sc,.oll operations. the status line must .be moved to its
ne~ position in memo,." before the screen-to-memory cor,.espondence
is
changed bV w,.iting the ·sc1'een sta1't" register.

Texas Instruments

Preliminary - Jan 21.

1983

.

-_ ........ _..- .._........ -- .....

~

-"
I

2.9.6

Video Connector

•

The video connector located on the rear edge o~ the printed circuit
board is a standard, 9-pin, -4!emale, D-type connector.
The signals
available on this connector are given in Table 2-13.
All signals are
at standard TTL levels.
Table

~-13

PIN
1
2
3
4
5
6
7
B
9
The
alphanumeT'ic-CRT
SUbsystems.

*
*
*
*
*
2.9.7

Color Video Connector Pin-out
FUNCTION
OT-ound
Logic ground
RED video
QREEN video
BLUE video
Logic Qround
Nt (no connection)
Horizontal dT'ive (NEQATIVE TRUE)
Vertical drive (POSITIVE TRUE)
can tro 11 eT'

boaT'd

contains

the

following

)

CRT controlleT' (CRTC) IC
Memorv/scT'.en arbitration logic
MemoT'V addT'ess decode logic
Character sets and attribute logic
PT'ocessor inteT'T'upt logic
CRT ControlleT' IC (6545A-l)

The CRTC IC(6545A-l) provides the logic to generate the horizontal
and vertical svnchronizing signals, display blanking during retrace.
screen memorv addressing during screen refresh,
cursoT' coincidence
logic, and start o~ screen display registeT's ~or use in scrolling.

Texas Instruments

......\

2-50

Preliminary - Jan 21.

1983

tECHNICAL REFERENCE

HARDWARE

CRTC P1'og1'amming.
The CRTC contains seventeen 1'egiste1's
that must be set up apP1'opriately be~ore ope1'ation o~ the board can
begin.
To access these T'egiste1's,
the CPU must ~i1'st w1'ite the
add1'ess o~ the ,.egiste1' to be accessed into the CRTC address
1'egiste,..
When w1'iting to 01' 1'eading (whe,.'e apP1'op1'iate) the data
registe1', the in#o1'mation is accessed acco~ding to the address
latched in the add1'ess 1'egister.
2.9,7.1

The values given in Table 2-14 assume a characte1' rate (SWM-) o~ 2.0
mHz, 12 lines pe,. cha1'acter block. 25 ,.OW& on the screen. 24
cha,.acte,. times 0# ho,.ilontal blanking (12.0 us). 20 line times o~
vertical blanking (1.04 ms) ~o" a 60-Hz re#,.esh rate.
When a 50-Hz
re#resh "at. is used, the second set 0# values appl~.
Table 2-14
CS- RS
H
L
L

....

"

,-)

L
L
L

L
L
L
L
L

L
L
L
L
L
L
L

L
L
L

R/W- ADD

X

X

L

L
H

L

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

L
L

X
X
X
0
1

L
L

2

L

4
5
6

L
L
L

:3

7

L

8

L

9

L
L
L

10
11
12

L

13

X
X

14
15

H

H

H

H

16'
17

Texas Instruments

CRTC p,.og,.amming Values

REO I STER NAME

VALUE
'60 Hz
50 Hz

Not selected
regist.,.
Status registe,.
H01'izontal total c ha,.s-1
Horizontal displayed cha~s
Ho,.izontal IV n cpo sit i on
VSYNC width. HSVNC width
Vertical total ,.0..,5-1
Vertical adJust lines
Ve,.tical displayed ,.o..,s
Ve,.tical sync position
Mode cont,.ol
Scan lines pel' 1'0..,-1
CU,.so,. start line and BLIN~
Curso'r end line
Displa~ sta,.t address HIGH
Display sta,.t add,.ess LOW
Cur so,. position add'ress HIGH
CU'rso,. position add1'ss! LOW
Light pen posi tion add HIGH
Light pen position add LOW
Add~.ss

2-51

103
80
84

39H
24
~

25
25
OOH
11
40H
11
OOH
OOH
OOH

OOH

103
80
84
39H
25
20
25
25
OOH
13
40H
13
OOH
OOH
OOH
OOH

Prel iminar~ - Jan 21,

1983

2.9.8
The

CRT

Sc~een/CPU

Arbitration

CRT

controller arbitration logic is designed to allo~ the
to have f~ee access to the CRT screen ~ith little overhead
time caused bV a~bitr.tion conflicts.
To achieve this end.
the
refresh memo~v and it. control logic are designed to allow ~or two
complete memo~v cvcle. bet~een each character displaved on the
sc~een.
One cvcle accesses the characte,. far displa..,. the other is
av.ilable to the CPU for ,.ead o~ write opeN.tions.
In this ~.V'
the
CPU must' ~ait at mast less than t~o displa.., character times ~or
access to the memor". Since a characte~ time is 500.8 ns and the CPU
clock is 200 ns, a s..,nchronization dela.., may also occu,..
The total
time fa,. a wo~st-case CPU access would be 1.0 us ~ith the usual
access time being bOO ns (3 to
~it states).
p~ogrammer

°

The logic that gene,.ates this .,.bitr.tion scheme is implemented with
a counter (which also counts the 9 do~s pe,. character) and a
p~ogr.mmable a~~a" logic (PAL) having inte~nal ,.egisters and feedback
from the outputs.
These parts a~e used to implement a small
alphanumerics state machine that p,.ovides the control outputs for the
RAM and buffer cont~ol and the wait state control for the CPU. The
counter identifies the state ~ithin the displa" cycle of the state
machine bV inputs to the PAL. The inte,.nal PAL ~egiste~s define
other st.tes used during the CPU ,.e.d and ...r i te eve les.
The other
inputs to the PAL a~e RD-,
WR-, CSEL-Ccha,.acte,. select), ATSEL(attribute .eleet"L
These inputs define ..,hat tvpe of cvcle, the CPU
is executing.
The outputs f,.om the PAL a~e COE- and CWE-, the RAM output enable and
write enable cont,.ol;
AEN-, the att"ribute bus bu~fer enable; ACE-,
the att,.ibute latch output enable; ACK-, the attribute latch clocki
MIE-, the cha~acter bus input buffe,. enable; SWM-, the signal that
switches the RAM address multiplexer f~om the CRTC to the CPU; and
WAIT-, the CPU ~ait cant~ol line.
The state. that the counter goes through a~e 8,9,10,11,12,13,14.15,0,
and repeat.
The window.

data f,.om the video RAM is available. is ,..ther
a latchCU10) is included to capture and hold the
data for the CPU until the end o~ the CPU ,.ead cvcle. This latch is
clacked when ,.e.d data is available f,.om the RAM by the ACK line
which also clacks the att~ibute latch.
The output is enabled onto
the local bus b.., a combination o~ CSEL- and RD-.
sho~t.

~hen

~ead

The~efo~e,

2.9.8.1 CRT A,.bitration PAL. The CRT arbit,.ation PAL programming is
given in Table 2-15.
In the comment column. the states that are
gener.ted by the AND of inputs aTe listed according to the counter
~tate
number.
Note that the outputs go LOW ~hen the AND D~ all the
listed conditions on a line are t,.ue OR il the same is true Dn
another line.

Texas Instruments

2-52

Prel i mi nary - .Jan 21.

1983

-'"

1

TECHNICAL REFERENCE

(

~

The

tiMing

HARDWARE

p1"aduced

by the alphanumerics stat. machine ~Dr typi~ai

c "C 1 • s i. s h DIIm in Fig u 1'.0 2- 90
Table 2-15

X1

RDWR-

X2
X4

Alphanumerics State Machine PAL

AEN-

SWMUX
I'1IE-

CSEL-

ACK-

AOE-

CWE-

Output:

L.DATSEL- COEWAITComment
------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------------------------SWt1UX . . L.. ~ . . . . .
S8, 9, 10, 11. 12 X4 DELAYED
a,. . . L.. . . . . . . . . . . . . Gill other terms
------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------------------------I'1IE- L. L. L H • L L.
L. L. S9 RAM WRITE BEGINS
01" . • . . . . . • o. . L.. • . . . S10, 11, 12 RAt1 WR ITE CONT.
01" . . . . . . . . . . L.. . . . . .11 oth.r t. rms
------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------------------------CWE- L L. L. H • L. L. .
L. L S9 RAM WR ITE BEG INS
a1" H L. L. H . L. L.
L
S10 RAM WRITE CONTINUES
01" L H L H . L. L.. . . L. . . . . Sll RAM WRITE CONTINUES
01" . . H L. . . . . . .
all other terMS inac tive
------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------------------------COEH
813. 14. 15.0 SCREEN REFRESH
01"
L. L H L.
L.
H
L S9, 10 RAM READ
01" . . • . L.. L.. . . . . L.. . . S10, 11, 12 RAM READ CONT.
'-

0,.

..

HL . .

. .

.

.

0

0

0

•

0

•

0

•

•

•

•

0

.

.

.

.

. .

.11 ath.1' terms inac tive

------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------------------------AEN- L. L. L. H
L. L.
L L S9 RAM WRITE BEGIN
01"
L
S10, 11.12 RAt1 WRITE CONT.
01" . L. L. H L.. L.. . . . . . H . L S9, 10 RAM READ
01" . H L. H L.. L.. . . . . L.. . . S11. 12 RAM READ
01" . . H L. ; . . . . . . . . . . . .11 other terms inae tive
----+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-----------------------ACK- H H L. H L.. L.. . . . . L.. . . S12 RAM READ
01" L.. . . . L. . L. . . . . . . . . WRITE ATTRIBUTE L.ATCH.
01" . . H L. . . . . . . . . . . . . .11 oth er t.,.ms i n.e t ive
------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------------------------AOE- L.L.LL.
L. L.
H L. S8 RAM WRITE
01"
S9 t i l l NOT WRITE.
. L. L. •
L
01"
L
L.
READ ATTRIBUTE LATCH.
01"
S13 t i l not read
L.
L..
L
01"
S13 t i l not ,.ead
L
L.
L.
------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------------------------WAITL. L.
H
RAM WRITE BEFORE S9
0,. . . . . L.. L. . . . . H H . . RAM READ BEFORE S9
01" . . H L. . . . . . . . . . . . . Gill other terms inactive
------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+--------------------------

T.xas Instruments

2-53

Prel iminaT'Y -

~an

21.

1983

-I

(11

0
:I:

~(IIIIN

.

UIAU"

~lAl(

Z

.....

I.

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,MAUN W"I1~ ,IIIIFR!'"
o
t 10 II I
11 14 I!I

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o·

,

10

I

~

0

~(lIInN

'''AIIN R["'O
"

,AHIUSH

II

I,.

~

1 UTA,lIuTI wlllIf'
, HAIE:N
.A(JAISH

I. 'S 0,

r

::0

.,

'an

I

JL45

LD-

------------L------,~r-------------------,t_Jr-------------------,~r'-------------------L-J------------~----~L_Jr----------,
I
I
,
,

AO-

WA-

",

I!oIL -

I I

I

'"T7"

,

1

An,lL-

r=T

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, ... f -

(OE-

--------IL______~--------,______~---------L-----~~L------~------~------~------_!------~
I

A(N-

,

AOE:-

.. 'a-

I\l
I

WAIT-

UI

AlllI

~

------------------~--------~------~--~----------------------,~~--------------------~~
' I
,

•
......r--:===~......C;;;;;;;::::)H

I

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-_-_-_-_-_-_-_-_-_-~---~---------:~~c========*!=x=x=x=CJ~1~--------~------~~-------eE I
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f
9
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cd 0

,

:

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"-

t--tr--;::;:::::::J
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.....
.-;;:::;;;:::::::Jrr------;;;:;=iHC==~H
'tAR'
,.....'L taWt
I
IDDR
"-tAR J ,
, (Nit.

iODA ,

II'I.D",'

DE
POE

t

I

Z

,I

j .,

I

I"

I

tN.II0=C" I.ArCtifO [
OoDClfIIUfoVAIL

I

HON Auru

u14,UIS
III .... fo'(US

lDfoO SA

1LL

flAU

PlalEL out Of un
"A"PtlrL
OF Ul7

(JU'

JlA" Plan OUT OJ !oMI" A'''''''IA
AND UIA.UIl.UI'

Figu .... 2-9

. .(I

m
(J

Alph.num .... ics st.te Machine Timing Diag ... am

.....
.-==::::::,"-

~~----~~

I'

='

fTI

"~

rr1
Z
0
III

TECHNICAL REFERENCE

2.9.9

CRT

Add~ess

HARDWARE

Decode

The add~ess decode 90~ the CRT subsystem,
both alphanume~ics and
graphics,
is handled by the CRT controller boa~d.
All o~ the screen
data is mapped into the processor memo~y add~ess space including the
assorted latches and 110 ports.
The decoding is done within three ICs:
a HAL10LB PAL. one-hal~ o~ a
74LS20, and a 74LS1S5 decode~.
The PAL p~oduces the following
signals:

*
*
*
*
*
*
*

-

*
The

RD-, a decoded and

bu~gered

read

WR-, a

bu'fe~.d

ZBEN-,

the .... st.~ Itxpansion bus b u ,~.,. enab 1•.

XBEN-,

the s.c onda~y bus b uffe~ enable.

CSEL-,

the

OSEL-.

the g,.aphics SCT'een memoT'Y select.

and decoded

alphanume~ics

w~ite

cont~ol.

cont~ol.

screen memol"Y sel.ct.

..

CR/AT-,
cont~o I
5 i gna 1
that selects the half of the
74LS155 that decodes the CRTC and the att~ibut. latch.
XSEL-, a cont~ol signal that selects the ha19 of the 74LS155
that decodes the g~aphics latches and miscellaneous input
buff.l".
XBEN-

signal also develops an Itnable clock faT' the CRTC by
and delaying the signal to p~ovide the T'e~ui~.d setup time
6545a-1 CRTC (90 ns).
The CRTE (CRT enable) signal has a
pulsewidth of >266 ns, thus satisfying the ~equi~ement of the CRTe.
The othe~ setup ~nd hold times a~e easily met.
inve~ting
fo~
the

The

74LS155 is used to decode the following signals:
ATSEL-, the
ibute latch select; CRTSEL-. the CRTC ch ip selec ti LAT-. a signa 1
which when combined with WR- clocks the inteT'~upt enable and SCT'een
enable latches.
The otheT' hal~ of the 74LS155 decodes the th~ee
g~aphics boa~d
latches and the buf~eT' enable faT' miscellaneous
inputs.
The address space that each of these devices occupies is
shown in Tab Ie 2-16.

att~

Texas

Inst~uments

2-55

Prel iminary - ,Jan 21.

1983

HARDWARE

TECHNICAL REFERENCE

Table 2-16

CRT System Memorv Map

ADDRESS

DEVICE

COOOO-C7FFF
CBOOO-CFFFF
DOOOO-D7FFF
D8000-DDFFF

Qraphics RAM Bank A
Qraphics RAM Bank B
Qraphics RAM Sank C
Unusable

DEOOO-DE7FF
DE800-DEFFF

Active character memor~
Phantom character memorv

\.DFOOO
DFOOO
DFOOO
DFOOO

bit
bit
bit
bit

0
1

:2
3

Misc
Misc
Misc
Misc

input
input
input
input

bu"er,
bu"er,
bu"er,
bu".",

SLUE 'eedback, read only
RED 'e.dback, read only
QREEN 'eedtack, read onlv
inte,.rupt pending, ,.ead onl~

DF010
DF020
DF030
DF800

Qraphics RED palette latch, ~ite onlv
Qraphics ORN palette latch, write onlv
Qraphics BLU palette latch, write anlv
Attribute latch

DFB10
DFBll
DFB1:2
DF813

CRTC
CRTC
CRTC
CRTC

DFS20
DFS20

bit 7
bit b

Texas Instruments

•

address registe,., write onlV
status register, read onlv
registers write access, write onlu
r.gisters r •• d .cc.ss, r.ad on1U

Mise output latch, interrupt enable
Mise output latch, alphanumerics screen enable

2-56

Preliminary - Jan 21.

1983

TECHNICAL REFERENCE

HARDWARe:

PAL coding is given in Table 2-17.
Nate that the output is" LOW when
the AND of .all the conditiDns on a line is
true OR when the
conditions on a second line are true.
Table 2-17

Output:

Alphanumeric Decoding PAL

MRDCA1516- A18
A14
A12
AMWRC- A19
A17
A13
All

COMMENT

-------+---+---+---+---+---+---+---+---+---+-----------------H
CRT SPACE READ
ZiEN- L
H
L
or .

H

L

H

CRT SPACE WR ITE

L

-------+---+---+---+---+---+---+---+---+---+-----------------H
H
XBEN- L
L
H
H
H
H CRTC/ATT READ
L
.

H
H
H CRTC/ATT WRITE
H
or
L
H
L
H
L
-------+---+---+---+---+---+---+---+---+---+-----------------RDCRT SPACE READ
H
H
L
L
inac tive term
or L
L

-------+---+---+---+---+---+---+---+---+---+-----------------H
CRT SPACE WR 11£
L
H
L

WR-

or L

L

i nac tive term

or L

L

inac tive teT'm

-------+---+---+---+---+---+---+---+---+---+-----------------H
GRAPHIC ACCESS
GSELH
H
L

-

----+---+---+---+---+---+---+---+---~--+------------

CSEL-

. or L

.

L

CHARACTER ACCESS
inac tive teT'm

or L

L

inac tive' teT'm

L

H

H

L

H

H

L

-------+---+---+---+---+---+---+---+---+---+-----------------CR/ATH
H
H CRTC/ATT ACCESS
L
H
L
H
H
-------+---+-~-+---+---+---~--+---+---+---+------------------

XSELOT' L

:2.9.10

,

L

L
L

H
H

H
H

L
L.

H
H

H
H

H
H

L
L

EXTRA I/O WR 11£
EXTRA 1/0 READ

Character Set and Attribut. L.ogic

The output of th., RAM (both character and attribute) is latched up at
the end of .ach scr.,.,n r.,fT'esh access c~cle b~ a pair of 74LS374s
(U14,
U15).
This .110ws a full characteT' c~c Ie time (500.8 ns) to
acc.,ss the chaT'acteT' ROM and EPROM and
set up
to the dot shift
r.,gist.r.
Th., r.q,uir.d ROM access "time is 452.8 ns.
In o,.de,. to
allow the cha,.act.r set to include the abilit~ fa,.
black g,.aphics,
bit 7 aut of the ROMs
is used to indicate that the leftmost and
,.ightmost chaT'acter dots are to be copied to the
left and right
chaT'&1ct.r cell border dots.
The cha,.acte,. ROMs should be programmed
with active low data, that is. if a dot is to appea,..
it should be
prog,.ammed to a zero.

Texas Instruments

~-57

Preliminary - .Jan

~L

1983

HARDWARE

TECHNICAL REFERENCE

Figure 2-10 shows some sample characters.
Note that the reverse
video block and the cursor a~fect the entire 9 x 12 character cell,
and that the underline appears on row 11.
In order to allow a
reasonable appe.ring underline,
cursor,
and reverse video,
the
lowercase letters with descenders should only drop one dot line belDw
the level D~ the other characters.

-;

COPIED WHEN BIT 7 IS LOW
+++

+++

+++

+++

6 5 4 3 2 1 0

6543210

• X X X X X
X
X
X X
X
X
X
X

X

X
X X

X
X

X
X

RO

R1
R2
R3
R4
R5
R6
R7

RB
Rq
RiO
R 11 UNDERLINE

X
X
X X
XX

X
X

X

X

X X X

X

X X X

X
X

X

X X X X X

X
X X X X

X XX XX XX XX

Figure 2-10

Sample Character Font

'.I

De~inition

2. q. 10.1

Attribute Interaction.
The attributes avai lable ~or use
with the character display can be used in any o~ the 128 possible
combinations.
The ~ollowing paragraphs explain what happens when
several attributes are active at once.

The attributes have a priority in their .~~ects.
and the highest
priority a~tributes a~~ect all attributes having a lower priority.
The order of priority is as follows.
Highest

Lowest

Color attributes - RED. BLUE. QREEN
~everse video and cursor
Charac tel' enab Ie
Blink
Underl ine

For example, when both the underline and blink attributes are set,
both character and underline would blink.
When the character enable
is set to disable, no character Dr underline or blinking activity is
pres ent.
When the revers e video is set wi th b 1 ink. the char acter
goes on and o~~ with the background lighted and the ~oreground dark
blinking.
When the character enable is set to di5able and reverse
videa is set.
the entire cell is lit (according to the calor
attributes).

Texas Instruments

2-58

Preliminary - Jan 21,

1983

TECHNICAL REFERENCE

HARDWARE

The, color attributes derine the characteristic:s of the Ulight"
port ion or the c:harac:ter. that is, either the color (~hen a color
monitor is used) or the int.nsi ty (when a monochrome monitor is
used) ,
When the graphics board is used with the alpha
screen ushows through" th~ "dark" portion
c~aracter display.

board,
the graphics
Or the alphanumeric

2.9.10.2 Attribute Hardware, The attribute logic design is or the
"pipeline" type because the activity of the attributes must occur
~ith dot timing precision. which is within 55 ns.
In order to get
data from a latch through several levels of logic and setup into the
next latch. some SCHOTTKY logic is used.
The attribute data from the
RAM latches is latched again bV two 74S175s (U16.
U17>.
This
latching allows for the one character delay through the character ROM
and provides tightlv timed outputs to the logic.
The cursor (CUR)
and display enable (DE) lines are also delayed twice to keep them
synchronous with the other information (U1S).

....

Propagation delay through the logic could cause timing skews greater
than a dot time. so the outputs of the first level of logic are relatched one dot time later.
After going through the second level of'
logic (MUX U20). they are latched again for presentation to the videC'
outputs (U39 749174),

Texas Instruments

2-59

Prel i minary - Jan 21.

1983

TECHNICAL REFERENCE

HARDWARE

The red, blue, and green outputs are bUTfered bV a 74LS244 before
being sent to the 9-pin connector.
The color outputs and composite
sync are buffered bV a 74900, which has an isolated power supply, and
are combined bV a resistor network and bufTered by a transistor to
make up the composite video output.
The mapping of colors to
intensity in the composite video output is shown in Table 2-18.
Table 2-18

CODE

COLOR

COMPOSITE SYNC
000
001
010
011
100
101
110
111

BLACK
BLUE
RED
MAQENTA
GREEN
CYAN
BROWN
loI-HTE

Color Map

COMPOSITE OUT
(In Volts)
0.47
0.78
0.88
0.97
1. 07
1. 18
1.28
1.37
1. 47

The alphanumerics display can be blanked to black by setting the CRT
ENABLE bit in the miscellaneous output latch to a low.
The board
enters this state on power-up.
2.9. 11

CRT Interrup t

The CRT controller board contains logic that allows it to generate an
interrupt during the vertical interval.
This interrupt is used by
the processor when doing scrolls with a status line or other
operations that need to be done during the vertical blanking
inteT'val.
The inteT'rupt is enabled bV setting the interT'upt enable
bit in the miscellaneous latch to. high.
When veT'tical blanking
occurs.
the CPU non-maskable interrupt is caused and the interrupt
pending bit is set allowing it to be read from the miscellaneous
buffer.
To reset the interrupt. the interT'upt enable bit must be set
low.
2.9. 12

Diagnostic Loopback

To assist in a low level OT diagnostic capability. the three color
outputs are looped back to the miscellaneous input buffer to allow
them to be read bV the CPU.
By the use of programming involving
careTul timing Tram the vertical interval.
the CPU can check the
action oT the attribute bits and graphic board palette circuits.

Texas Instruments

Preliminary - Jan 21.

1983

TECHNICAL REFERENCE

(

HARDWARE

~\

•

~.

10

QRAPHICS VIDEO CONTROLLER BOARD

The g~.phics video cont~olle~ boa~d is designed to ope~ate with the
CRT controlla~ bo.~d.
It is phvsicallv mounted in a piggyback
f •• hion on the CRT cont~oll.~ bDa~d and all its connections are to
tha CRT cont~oller board.
A block diag~am of the graphics video
controllar bo.~d is sho...n in Figu~e 2-11.
Refe~ to Section 5.
dr .... ing ~Z!3063, fo~ log ic d iagl'ams.

-CPU

'-.--

i

~

j
!!

c3

i

j

i...

~

!

...

~

i
~.

.!
!!

j

.:!

To CPU

-@]
L"""
• Conlflll

\.

Figure

~-11

Q~.phic:s

Video

Cont~oller

~-61

Board Block Diagram
Prel iminary - Jan

;!1.

i9B-3

TECHNICAL REFERENCE

HARDWARE

The graphics video controller board impl.ments the same number of
pixels (720 horizontal x 300 vertical) on the screen as does the
alphanumerics board_
Each pixel can contain a maximum of three
attribute bits Clabel.d A,
B,
and C),
which are converted by a
p a let tel 00 k up tab 1 e t e t hr e e color s - red, b 1 u e , and gr e en.
2. 10. 1

Grap h ie s Pal ette

The palette for the graphics video controller board is designed to
map the pixel attribut~ bits to the thr •• color outputs.
Three B-bit
latches contain the mapping information for the attributes.
The
three latches correspond to the three colors, as sholiln in Figure 212~
\.J
B plane value

11110000
1 1 0 0 1 100
.10101010

C plane value
A p lane va lue

Latch bit addressed

BLUE latch value
RED latch value
QREEN latch value

76543210

-----+
---+
-+

1
1
1
1

o

1
1
0
0
1

1
0
1
0
1

010

o

o

MONOCHROME

COLOR

0 1
0 0

Figure 2-12

INTENSITY

White
Ve II 0111
Clla n
Green
M.g .nta

4
:3

Red

2

Blue
Black

o

7 max
6

5

1 min
OFF

Color Palette

Figure 2-13 sholils the latch values to be programmed if the three
attributes A, B, and C map diT-eeily to green, red, and blue.

Texas Instruments

2-62

Preliminary -

Jan 21.

1983

,

HARDWARE

TECHNICAL REFERENCE

(

~

ATTRIBUTE

Example 1

+---------+------+-----,
• • +---+--------: 1+------I
I
I

: : I

CREEN latch
RED latch
BLUE latch
A B C
1 1 1
1 1 o

1
1
0
0

:+-----

: : : : : : +---10101010
11110000
11001100
I

•

I

•

I

•

I I

•

•

I

•

111

110
101
100
011
010
001
000

COLOR
Whit.
Vel 10...
C~an

CT' een
Mag.nta
Red
Blue
Black

I

I

---+: I:: I :
--+: I::

0 1 -------+1 I

o ------+

0

1 1 ---+ •I •I
1 0
•I
00 1
o 0 0 -----~--+

-----+
-------+-

(COOD FOR FLAGS)

Example 2

j

"'-'" '

Backg,.ound is black
Flag backg,.ound is b lu.
RED has p,.io,.it1j ov.r blue
WHITE has top p,. i 0,. i tlj

(A plan. )
(B plan. )
(C plane)

ATTRIBUTE

+-------+--------I .-----

I +---+-------I

11+------: 111+------

: 1:1 11+---11001100
11111100
11001110

CREEN latch
RED latch
BLUE latch
ABC
1
1
1
1

1
1
0
0

"
I

• I I,
I ••••

1 ---+: : I : I : I
0 ----+J II::
1 -----+1: :
0

011
010

o
o

I I
••

111
110
101
100
011
010
001
000

COLOR
White
Red
Blue
Black
Black
Black
Black
Black

0 1
0 0

-------+:
---+ I I I
------+ I :
------+ :

--------+

Figure 2-13

Texas Inst,.uments

Palette Programming

2-63

PT'el i minary - ,Jan 21.

1983

TECHNICAL REFERENCE

2.10.2

Pixel

HARDWARE

Add~.ssing

The pixels a~e mapped into the p~ocesso~is memo~y space such that ~
group o~ 16 adJacent pixels o~ a single attribute bit are contained
within a single wo~d.
The wo~ds of: pixels are mapped lnto d
continuous string o~ 4S words ~or every row.
One unused word occurs
at the logical end o~ each row.
The entire screen takes up a block
o~
32 768 m.mo~v locations o~ which 27 600 are actually used (which
corT'esponds to 736 I 300/8>'
The three att~ibute sections are
1 0 cat e d i n
t h1" e e.
ad J ace n t • 32- k b y t e b lac ks 0 ~ memo l' y .
Not e t hat
when a 50 Hz screen re~resh rate is used, .(350 displayed lines)
then
32200 bytes of the block are used.
Figure 2-14 shows examples of
pixel addressing.
Example:

Pixel in top

le~t

COT'ner

o~

screen.

ADDRESS

BIT

0123456789ABCDEF

OCOOOOH
OC8000H

o
o
o

X...••.. , ...... .
X•.. , ....•••••••

At tri b ute Ai
Attribute Bi
Attribute Ci

oDOOOOH

Example:

Second line down,

x....... , ...... .
123 from left margin.

x 736) +

«~

99

I

1~3) I 16 = 99
2 • 199 • OCbH

ADDRESS

Attribute Ai
At tri b ute Bi
At tri b ute Ci

BIT

0123456789ABCDEF

........... x....

OCOOC6H

11

OCBOC6H

11

ODOOC6H

11

.•..•...•.. X•••.

.... , ...... x... .

•

Figure 2-14

2.10.3

Examples of Pixel AddT'essing

Timing and Synchronization

The graphics video controller board uses the same dot clock used by
the CRT controller board to generate its other inte~nal timing.
To
sIJnchronize the pixel outputs from the two boards, the display enable
(DE) signal ~rom the CRT controller board is monito~ed.
If: the DE
signal has been low for a long period o~ time, the graphic board
assumes that the scan is in the vertical interval and resets the
graphic memory and scan counters to zero when DE goes high again.
When the DE signal is low for short periods of time, as in horizontal
retrace. the scan counters are stopped, thus making the last pixel on
a line adJacent to the first pixel on the following line.
During th~
vertical interval when DE is low ~or a long period o~ time,
the
Texas Instruments

2-64

Preliminary -

~an

21.

1983

TECHNICAL REFERENCE

counters are
dynamic RAM.

restarted

HARDWARE

a~ter

a time-out to continually re;resn the

The graphics video board is designed to allow the CPU essentially
~ree
access to screen memory.
During a single SCT'een display cycle,
the hardware can access the re~resh memory two times - once to read
the data 'or screen display. and once 4lor the CPU to read or wT'ite
data i# needed.
To allow su~~ici.nt time lor this access. a display
cycle accesses 16 ·adJacent pixels o~ three attribute bits each
These are read in parallel and loaded into three 16-bit Shl~t
registers 'or display.
A,tar the memory has been read "or screen
display, the CPU access cycle is started when a read or write cycle
is re~uestad.
The memory accessed is broken up into one o~ six
separate bytes bV properly decoding the enabling 0# bus bu'#ers and
write enable signals to the memory.
Dynamic memory is used on the graphics video board because 0# the
large amount 0# .emory re~uired.
The memorlJ chips are organized into
16k 14 bits and are packaged in an lS-pin.
dual inline package
(DIP),·
The e address lines are multiplexed into 256 row addl'esses
and 64 column addresses to get to the 16-k locations in the memory.
The addresses to the RAM also need to be multip lexed between the CPU
and the refresh counter.
This 'our-way multiplexing is done bid flour,
74LS153 dual 4-to-l multiplexers (U33 through U36L
'.

The timing 'or the graphics board is shown in Figure 2-15.
Th€
timing is g.nerated by a 4-bit counter(U3Q type 74LS63) and a logic
array CU41 type HAL16RSA-l). Tha ra#rash counter start or stop logit
and reset logic are provided by a count.r (connected as a one-shot)
and two gating circuits (U40 74LS163. U44 74LSOO. U45 74LS04).

,"-.

Texas Instruments

2-65

Prel i minary -

~an

21.

1993

TECHNICAL REFERENCE

HARDWARE

,

: ( PU W"'Tl'!l f
t
teRll"
I
I
MrIllOIl~
,DI'!Ipa, CYClE,
~L.TVl....n...!"

LAST SCAEEN;
: C-U Ilt &05 ;
, ... elf DURIM6'JlR~'DI~Pt&l,SCAUIIM£ .. ,5lCDMD
~
... IIl .. N .. ,N ... : ' ... CL£OfI....
,00SPlA... CYCU,

.' oJ

,

IDISPL'U ('tLl,

.

W-

IU

.

,

AOW-

r;Reu

r-------.---------------r-----------~-----------r----------~----------~r-----------~----------~----------_i~

,

.lllUI

,

I

---------~ur---------~ur---------~---------~~r:---------------------~ur:---------------------~~~---------~--------~

ROWR-

6UlAAS-

CASIUrrNLATEN -

lAfOIC.

W"'T-

!,

iii iii i

D[
orD-

.,,"-

ii'

C[u-

I J II I i I] I

. I

-----------iu

I--t--- I-

FIRST PIIIi[L OUT Of' !>MIF"'T AeGo
FIIUT PIIliEL OUT Of' u . l
flAST PlwEL OUT Of' "~LC:T

~

OACU(

.AIT

j

f,

---------...;u

~
,
,

--U

~~------------------

Ne
Celli
COUNT -

~

-11.....:..._ _ ______

~~-----------ENO Of "CTIY( "',DlO

Figure 2-15
Texas Instruments

~

r .. o or

.. !II AoN .. ,N6

ON[ SNOT T'''lOUT [lUAING
... lATOCAoL INTEAVAoL

EIIC

(If

"'(A I "'"

",I\..

al"6

Graphics Video Controller Timing Diagram
2-66

Preliminary

Jan 21.

1983

,

TECHNICAL REFERENCE

HARDWARE

2.10.4 Qraphies Log1c Arra~ Program
Programming -ror the logic arra~ is given in Table 2-19.
Note that
the output goes LOW when the AND o~ all the terms on a line OR the
ANO o-r all the terms on some other line is true.
Table 2-19

Programming

Xl

RDWR-

XC!

GSElOutput:

DE

~or

the

~aphics

LATEN- BUFENLATOE- SRLDROWRA5GWAITGRCLK
CA5OED-

State Machine HAL

Commttnt

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+--------------------------

LATEN- L
L
or
L L
or
L L
or L L .

H L
L

L
L
L

READ S5.6.7,8
WR ITE 53
WRITE 54 till not IIIrite
all other ORs inac tive

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+--------------------------

LATOE- L
L
H HH L
or L. L . .
or L L .

"-

L

READ S8
READ S9 ti 11 not read
allot h er OR s ina e t i v e

. L . .

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+-------------------------REFRESH SCREEN Sll
L H L H
L L
L
WRITE 93
L L
H
READ 93
L
L
L H L L
CPU 94, REF S12
H HL
L
CPU 95, ~h REF S13, 14
L H
L
CPU S7, REF S15
L H H
L

RASor
or
or
or
or
or

inactive term

L L

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+--------------------------

CASor

. H.
. H.

. . L.
. . L.

913. 14, 15, 0, 5, 6, 7, 8
allot h er OR s .

-------+-+-+-+-+-+-+-+--~+-+-+-+-+-+-+-+--------------------------

BUFEN- L
L
or
L L
or
L L
or L L .

L

HL L L

L

H
L

L

READ 94,5.6,',8
WRITE S2
WRITE S3,4.5.·6.',8
all othe,. ORs inactive

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+--------------------------

SRLDor

. L

H

H

S1 5
all other ORs inactive

H

L L .
-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+--------------------------

GWAIT- L
L
or . L L . . . .
or L L. . , . .

HH
H.

READ
WRITE
allot h er OR s ina c t i v e

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+--------------------------

DEDor

. . H.
. . H.

DELAYED DE
all other ORs.

-------+-+-+-+-+-+-+-+---+-+-+-+-+-+-+-+-------------------------, ..

Texas Instruments

2-67

Prel i minary - Jan 21,

1983

-

TECHNICAL REFERENCE

HARDWARE
.

2.11

"

SYNCHRONOUS-ASYNCHRONOUS COMMUNICATIONS BOARD

This subsection desc~ibes the ~unctions and theor~ of operaticn of
the synch~onou5-asynch~onous communications (sync-as~nc comm) boa~d
Figu~e 2-16 is a block diag~am o~ the sync-as~nc comm
boa~d.
Re~e~
to Section 5. d~awing 2223096. ~o~ logic diag~ams.

,

Interrupt
Acknowledge
Logic

'

INT ACK

.

r1

/).
Select

Select

ACK

110

Address
Decode

Address

Chip Selector

...

Logic

)

IIOBus

Select
Cornm

...
...
Oata BU$

Select Input
Input/OutpUt
CVcle
Select Output

svstem
Unit

Boerd

Select

-

Q

+
CommuniC8tions
Controller

)

/~

~

RS-232-C

r

Intarlace


InterrUpt

"",

r

Receive"

....

I

Clock

ExterNl
Devices

I
Transmine"

-t+
U

Interrupt
Logic

Sync-Async Comm

Boa~d

Block

Diag~am

The .~nc-asvnc comm board is designed a~ound the Zilog Z8530 Se~ial
Communications Cont~olle~ (SCC)'
This device automatically handles
a.vnc p~otocol5 a5 well as most sljnc' p~otocols, including bito~i.nted protocols such as sljnch~onous data link cont~ol
(SDLC) and
high-level data link cont~ol (HDLC)'
Cljclic ~edundancy check  signal,
which if
combination with the "ANO II of IORC- and AIOWC- (lORG) is used t"
enable the bus buffer U7.
The othe,. logic an the s~stem side of the board is used to delay the
re.d and write commands to the sec in order to meet the address and
data setup and the hold time requirements of the pa,.t.
The signal
IORG is connected to the input of U5A C74LS74 ~lip-9Iap) and the
clock input is connected to the system ClK line.
The rising edge of
the clack occurs 133 ns .fter the IORC- 0,. AIOWC- signal occurs.
The
output of U5a is gated with IORC- and AIOWC- to d.la~.the start a~
the SCCRD- and SCCWR- signals.
The clear input to USa is connected
to IDCS to allo~ the SCCRD- and SCCWR- signals to occur only when the
b oa r dis s. lee t. d.
In orde~ to reset the Z8530 sec, both the SCCRD- and SCCWR- lines
must be held active together. This holding is p~ovided b~ Vbc and
U6d ~hich II OR II in the RESET signal 4=ram the bus with the SeCRD- and
SCCWR- 1 ines.

,_

The interrupt output 9ram the sec is inve~ted and buf~eTed by U4c and
goes to a set 09 stake pins to determine the interrupt level at which
the board is operated.

2-69

Prel iminary - Jan 21,

1983

HARDWARE

TECHNICAL REFERENCE

2.11.2 Sync-Async Comm Board Baud Rate Generation
The crystal oscill.tor on the board is operated at 4.9152 MHz and is
divided
by 2 to provlde
~
clock for the sces internal baud-rate
generators.
The value to program for the generation of a
specific
baud rate is shown in Table 2-20.
Table 2-20

BAUD

ASVNC

RATE

VALUES

19 200
9 600
7 200
4 800

3 600
2 400

2 000
1 800
1 200

2
6
9

14
19
30
36
41
62

SVnc-Async Comm Board Baud R.t.
PERCENTAGE
OF ER RDR

1.587

339

0.000
1. 053

510
612
681
1022

-0.775

382

150
134.5
110
75

510
569

0.001

50

Texas Instruments

OF ERROR

62
126
169
254

200

300

126
254

PERCENTAGE

0.000
0.000
-3.030
0.000

0.000
0.000
0.000
0.000
0.000

600

SYNC

VALUES

696

0.026

1022
1534

0.000
0.000

2046
4094
6142
8190
9134
11169
16382
24574

2-70

O. 000
O. 000

-0. 196
0.000
0.098
O. 000
O. 065
-0.049
O. 000
O. 000
O. 000
O. 000
O. 000
0.001
-0.001

O. 000
O. 000

Pre 1 i minary - Jan 21.

1983

TECHNICAL REFERENCE

HARDWARE

2.11. 3 Sync-As~nc Comm Boa~d Add~esses
The boa~d add~esses ~o~ the ~our possible
21.

Table 2-21
PORT

,-.

Sync-Async Comm
ADDRESS

po~ts

Boa~d

Po~t

a~e

given in Table 2-

Add~esse5

FUNCTION

PORT 1
INTERRUPT IRO (PIN S)

00£0
OOE4
00£5
00£6
ooE7

CHB
CHB
CHA
CHA

Acknowledge
Command
Data
Command
Data

PORT 2
INTERRUPT IR1 (PIN 48)

00£8
OOEC
OOED
OOEE
OOEF

Interrupt Acknowledge
CHB Command
CHI Data
CHA Command .
CHA Data

PORT 3
INTERRUPT IR2 (PIN 50)

OOFO
OOF4
OOF5
OOF6
OOF7

Int.??upt Acknowledge
CHI Command
CHB Data
CHA Command
CHA Data

PORT 4
INTERRUPT IR4 (PIN 46)

OOF8
OOFC
OOFD
OOFE
OOFF

CHB
CHB
CHA
CHA

Inte~~upt

Acknowledge
Command
Data
Command
Data

Inte?~upt

t
' - •• 0

Texa s In strument s

2-71

Prel imina 'rij

-

.Jan 21.

1983

TECHNICAL REFERENCE

2.12

HARDWARE

WINCHESTER DISK DRIVE AND CONTROLLER

The Winchester disk drive and controller board option consists of a
controller board. cable and hardlltare. and a 5-. 10-. or 15-megabyte
Winchester drive.
2.12.1

Register Assignments

The register
Table 2-22.

assignment

Table 2-22

for

the Winchester controller is given in

Winchester Controller lID Port Assignment

+-------------+--------------------------------------------+
HEX

FUNCTIONS

+---------------------+----------------------+
IN
OUT
+-------------+---------------------+----------------------+
0030
n.ta OUT port
+-------------+---------------------+----------------------+
0031
Status register
RESET
+-------------+---------------------+----------------------+
0032
Not used
Not used
+-------------+---------------------+----------------------+
0033
Not used
+

ADDRESS

+-------------+---------~---------+----------------------+

An IN function sets data from the Winchester controller board and
drives it onto the computer's 110 expansion bus. Conversel~. an OUT
function sets data from the computers 110 expansion bus onto the
Winchester disk controller board.
For bVte definitions
given in Table 2-1.

Texas Instruments

of the registers. refer to the 110

2-72

memor~

Preliminary - Jan 21.

map

1983

TECHNICAL REFERENCE

--,

HARDWARE

2.12.1.1 Data Input Port.
r'isk read data and controller sense bytes
are passed through this register to the compoter. The data is he11
'01" each handshake cycle.
The con~iguration is as f!ollollls:

aIr

MSB
7

110

5

6

4

NUMBER

LSB

2

:3

l

o

1

Po.,.t
+===-==+======+======+======+======+======+======+======+
Add,.ess
IDATA 71DATA 6 IDATA 510ATA 4:0ATA 3:0ATA 2:DATA 1 I DATA 0:
0030

+-=-=-=+======+======+======+======+======+======+======+
2.12.1.2
Data Output Port. Command bytes and disk data are passed
through this ,..gist • .,. to the cont,.oller.
Data is latched until
updated by the CPU.
The bit ar.,.angement is as fo11ollls:
BIT NUMBER

MSB

110

7

6

S

4

LSD
0

211

3

Po,.t
+===-==+======+-=====+======+======+======+======+======+
Add,.ess
0030
IOATA 710ATA 61DATA 510ATA 4:0ATA 3lDATA 21DATA 1 I DATA 01
(write)

--

+=-----+======+-=====+======+===-==+======+======+======+

2.12.1.3
Controlle.,. Status Registe.,..
Sto.,.es the controller status
Enables the CPU to ,.ead the status of the controller and monitor it~
op.,.ation.
The controller status byte is defined as follolds:
MSB

110

7

5

BIT NJMDER
4
:3

LSD
2

o

1

Po.,.t
+====-=+-=-==-+--====+-=====+======+=======+======+=======+
Add.,..ss IDon't IDon't IDon/t IDon't IDon't ICOMMANDIINPUT/I DATA
0031
lca're Ica,.e lca.,.e leare leare I/DATA lOUTPUT1REGUESTI
('read)
I

.._aa._+ ____=-+=sa===+_=====+======+=======+======+=======+

2.12.1.4 Reset Port. Resets the controller.
Any write to port 0031
does a reset.
Reset must clear all error status. abort all
op • .,.ations, and place the Winehestar cantrall • .,. in the command
,.eceiv. mode. The byte definition is given as follollls:

MSB
1/0

7

5

BIT NUMBER
4
:3

LSD
2 I

1:

0

Po.,.t
+======+======+======+======+======+======+=====+======+
Add'res5 IDon't IDon't IDon't 100n't 100n't 100n't IDon'tIDon't
0031
lea.,.. leare leare leare leare leare leare leare
(ldrite)

+======+======+======+======+======+======+=====+======+

T.xas Inst'ruments

2-73

Prel i minary - ""an 21.

1993

HARDWARE

'TECHNICAL REFERENCE

2. 12. 1. 5

I nterrup t Ma s k.
to be serviced
definition follows:
inter~upts

b~

MSB
110

:

7

6:

5

A two-bit
the CPU.

fi eld which determines the
The interrupt mask byte

BIT NUMBER
4
:3

2:

1

LSB
0

Port
+======+======+======+======+======+======+=-====+=======+
Address IDon't :Don't IDon't :Don't IDon't :Don't IDATAt ISTATUS I
0033
leare leare leare leare leare leare IINTR. IINlR.
I

: ENAB LE I ENABLE

I

+======+-=====+======+======+======+======+-==--..--=====+
2.12.1.6
Error StatuI Byte.
This byte isa special cas. that is
onl" available after a command has been completed.
The controller
indicates that this b"te is available b" setting the 1/0 and CID bits
with ORG. A definition
the error statuI byte follows:

0'

MSB
110

7

6

5

BIT NUMBER
4
3

2 t

1:

LSB
0

PD,.t
+===--=+======+===-==+======+===-==+======+=====+======+
Address IDon't IDon't IDT"ive IDon't :Don't IDon't IEr,.or:DDn't
Icare Ie.,.. INo.
Ica,.e Ica,.e lea,.e I bit lea,.e
0030
(,..ad)
I
I
I
I

+======+=--===+----==+==--=-+==-...+-===-=+=.._-..---=-+

2.12.2

Bit DefinitiDn fDr Registe,.s and PDrts

Table 2-23 p,.ovides definition of bits for the Winchest.,. cont,.olle,.
,.egister. and pD,.tS.

Texas Instruments

2-74

Preliminary - Jan 21.

1983

HARDWARE

TECHNICAL REFERENCE

Table 2-23

Bit

De~initicn

lor Controller Registers and Ports

+-------+----------------c LOGI CAL STATE l - - - - - - - - - - - - - - +
: DATA
: Data true; data high
I Data false; data low;
: BIT
I logical one >= 2.4 V
I logical zero .(= 0.7 V
+--------+============================+===========================+
IDATA 0-7
I READ or 1
DA TAB I T = 01\£
DATA BIT = ZERO
I WRITE

+---------+---------------------------+--------------------------+
I DATA
Commands. status, or data
No command, status, or
: REGUEST I readlj to be transferred
I to or from controller.

: data t,.ansfers to
I controller.

0,.

from I

+--------+----------------------------+--------------------------+
IINPUTI
:Data or status is read
I Data or commands are
I

I

OUTPUT- Ilrom the controller by
I the CPU.

I b~ the CPU.

DATA-

I.DATA is sent to th e CPU.

l~ritten

TO the controller

+---------+---------------------------+---------------------------+
I COtt'1ANDI When INPUT/OUTPUT- is high. • Wh en INPUT IOUTPUT- is high, I
STATUS is sent to the CPU.

*********** **** ******** ***** IlWhen
******INPUT/OUTPUT****.**** ********
****,..
is 10'-"

When INPUT/OUTPUT- is lo~.
COMMANDS are sent to the
controller

I

IDATA is sent to the
Icantraller

+---------+---------------~------------+-------------------------~{

I INTERRUPTI An int.r,.upt ( level 6 )
I PENDING lhas been sent to the CPU.

No interrupt pending.

+---------+----------------------------+--------------------------~~

lThis lets the controller
linterrupt the CPU ~hen it
I STATUS
Ihas finished the current
lINTERRUPTlcammand, and is ready to
I ENABLE :return the status b~te.

No status interrupt
permitted.

: INTERRUPT: interrupt the CPU when
ENABLE ldata needs to be read ~rom
lor ~~itten to the conI tl'O ll.r.

No data interrupt
permitted.

+---------+----------------------------+---------------------------+
I DATA
IThis lets the controller
+---------+----------------------------+---------------------------+

Texas Instruments

2-75

Pre lim ina r

y -

Ja n 21.

1983

TECHNICAL REFERENCE

2.12. 3

Cont~olle~

HARDWARE

Status

Bi~

CombinatiDns

Table 2-24 gives all valid controller status bit combinations.

Table 2-24

Valid Bit Combinations for

Cont~oller

Status

--------------------------------------------------------------------+
I

I

I
I

: COMMAND/: INPUT I I DATA ::
DATA I OUTPUTIREGUEST::

MEANINQ OF PATTERN

+========+====--=+=======++=========================================+
o

o

o

I

I

•
I•

I
II

I

I

r

I

+-====--=+======-+=======++=========================================+
o

A data bVte mav be sent FROM the CPU

o

1

I: TO the Wincheste~ cont~olle~. The
I: cont~olleT' waits fo~ data to be ",~itten.

+===s==s=+====_=-+=======++=========================================+
o

1

I

0

I

Not Va l i d

: :

I :

+========+-===-..+-======++=======-===============--================+
o

1

1

I I
I I
I I

A data bVte mav be sent TO the CPU
FROM the Winchester cont~olle~. Again,
the cont~oller waits until read.

+========+=====-=+=======++========================-================+
1

o

o

I

I

I

I

I

Not valid

I

I

I

+========+====--=+=======++=====--=====-============================+
1

o

Command bVtes

1

: I
•
•

Winch.ste~

may

be sent TO the
FROM the CPU.

cont~Dller

I
I

+========+=======+=======++=========================================+
1

1

o

•I Ir
•
•

I

Not valid

I
I

I

I

•

I

I

I

I

I

,

I

I

+__=-====+_=-=_==+=a=====++=====_==================-================+
I
I

•
I

1

1

1

A status byte mav be sent FROM the
cDnt~Dller TO the CPU .

Wincheste~

+========+=-==-==+=======++=========================================+

Texas Instruments

2-76

Preliminary - .Jan 21,

1983

HARDWARE

TECHNICAL REFERENCE

,....

Figure 2-17 depicts the logical flow of the controller functions.

***************

*

*

START

***************

v

+---------.-----+---------------+
I

Reset the Winchester controller
( . wr i te to part 31 )

+-------------------+-------------------+
WAITt
--------------->:v
+-------------------+-------------------+
Read status port (OO3t)

+-------------------+-------------------+
v

...

-

*

...

...

... Is
...
...
... REGUEST

...

ACTIVE?

...

*

*

*

*

NO
...-----) WAITl

... YES
V

.

...

\

*

...

...

*

* COMMAND *
...
MODE?
* ( C/D=1, *
* 1/0=0)*

•

NO

*------------)

<: HARDWARE >

<

FAULT

...

...

*
v

<: OUTPUT ).

Figure 2-17

Controller Operational Flowchart

,.
Texas Instruments

2-77

Pre I i minarlj - .Jan 21,

1983

HARDWARE

TECHNICAL REFERENCE

< OUTPUT)

v

+-------------------+-------------------+
OUTPUT COMMAND BYTES TO CONTROLLER
( "1' i te to port 0030 )

+-------------------+-------------------+

:<----------------+

v

*
*
* DATA * *
MODE?'

NO
* ( C/D=O ) * *-----)--+
*
**
* *
* *
*

v
+--------~~----------+WRITE 'OR READ CONTROU.ER DATA

( r.ad/..,rite to port. 0030 )

+-----._------+------------+-

v:<--------------+

*

*

*
*

*
* *STATUSOUTPUT
MODE?
(I 10-1,

• C/D-l >*

*

*

•

*

Nl

*-----+

•

*

v
+--~--------------+-~--------------+READ STATUS FROM PORT 0030

+-------------------+~------------------+-

< END
Figul'e 2-17

Texa. Instruments

v
LOOP )

Controller Ope1'ational Flo..,ch.rt, Continued

2-78

p,.elimina,.~

-

~an

2L

1983

HARDWARE

TECHNICAL REFERENCE

< END LOOP >
V

* *AN

*

-

*
*DID *

ERROR
OCCUR?

*

*

*

*

*

*
*

NO
* ..-->
< WAIT1 >
*

V
+-------------------+---------~------+
DO REGUEST STATUS CCI1MAND AND

DECODE ERROR

+-------------------+-------------------+
********
* END *
********

Figu,.. 2-17

Cont,.oU.,. Ope,.ational Flolilchart,

Concluded

'--

T.xas Inst,.uments

2-79

p,.eliminar~

-

~an

21,

1983

TECHNICAL REFERENCE

2.12.5

HARDWARE

Winchester Hardware Theory of Operation

The Winchester controller is addressed by the B08S "s a block of four
I/O ports: Hex 0030 to 0033.
I/O reads are indicated by the bus
signal 10RC, and I/O writes are indicated by the bus signal AIOWCThe controller can generate
fallowing conditions .
to

an
be'

interrupt
read

from

to

...

When data is read,{
controller.

or

...

When the operation is camp leted,
and
re ques t ing a statu s read (C/D-=l, 1/0= 1 >.

the host under the
written

to

the

the controller is

Bath of the interrupt condit'ions can be individually disabled.
When
the interrupt is active, the computers interrupt line b is held high
until it is cle.red by • read to the controller status register.
2.12.5.1 On Board EPROM/ROM. The controller has a 4K x 8 bit
EPROM/ROM.
This device is addressed in memory space at address
OFBOOOH and contains the driver routines for the controller.
The
output of the EPROM/ROM drives the data bus through a tri-state
buffer IaIhen addressed.
Access times on either the EPROM or the ROM
are nat greate,. than 350 ns.

Texas Ins'truments'

2-80

Prel i minary -

~an

21,

1983

\

TECHNICAL REFERENCE

HARDWARE

2.1:2.5.:2
Commands and Command Testing.
The computeT' sends a sixb"te block to the cont... oll.,. to speci~lI the op .... ation.
This block is
the device cont ... ol block (DCB).
Table 2-25 de~ine5 the DCB.

Table :i2-:i25

Deviea Control Block Bit DiagT'am

B
1j+-----+-----+-8 1 T
t I

7

6

5

N U M B E R -+-------+-------+-------+
4
3
:2
I
1
0

+e+--....=+--..._=+=-=.._=+=====·_+===-===+=======+=======+=======+

10: CO....AND CLASS l O P COD E
+-+-------+-------+-------+-------+-------+---------+-----+-------+
HIGH ADDRESS (note 1 )1
111
LOQICAL. UNIT NJPtSER
+-+----+----+----+-----+----+----+-----+-----+
( note 1 ):
I :2 :
MIDDLE ADDRESS
+-+----+-----+-----+----+-----+-----+------+-----+
( not e 1 ):
r 31
LOW ADDRESS
+-+-----+------+------~-----+---~--+-------+------+------+

14 :

( not e :2 ) I

INTERLEAVE OR NUMBER OF BLOCKS

+-+------+------+------+------~----+------+------+-----+

CONTROL
FIE L D
+-+--___ _+_----+-----+------_+_-----+----+-----_+_-----=NOTES:
1. Re.f.,. to subp.,.ag,.aph 2. 12.5.6, "Logical Add,.ess".
2. Int.,.l.ilv. facto,. 410,. FORMAT. CHECK TRACK, and READ ID com.... 'l()

2.12.5.3 Explanation 01 S"tes in the Device Cont,.ol Black.
The si
b"tes which camp ... i •• the device cant ... al black are de~in.d a5 follow9
BYTE

l

DEFINITION

0

Bits 7, 6 and 5 idanti~" the class o~ the cammand. Bits
4 th ... ough o cantain the apcada af the command.

1

Bit. 7, 6 and 5 i dent i~V the log i cal unit numb ar (LUN) .
Bits 4 th ... ough 0 cantain lag i cal disk address :2.

2

Bits 7 th,.aug h 0 cantain lagical disk address 1.

3

Bits 7 throug h 0 cantain logical disk address 0 (LSB) .

4

Bits 7 th ... ough 0 spec

5

Bits 7 th ... augh 0 cantain the control fiel d.

i~"

the

inte~leave

2-81

a~

black caunt.

PreliminaT'Y - Jan 21,

1983

~

HARDWARE

TECHNICAL REFERENCE

2.12.5.4
Control· Field Detai led Description.
The control rield,
byte 5. Or the DCB allows the user to select options for several
different types and makes of disk drives.
The following listing
defines the bits of the control byte.
The step options are encoded
in control byte 5 of the command descriptor.
The encoding is done
with bits 0 through 3 as folluws:
.
BIT

DESCRIPTION
3

Default 3-ms step rate
Seagate ST506 (MLC2)
landon fast step
Texas Instrument fast step
200-us buffered step
70-us buffered step
30-us buffered step
1S-us buffered step
Olivetti 2 ms/step (561)
Olivetti (562) fast step (1. 1 ms typ ical)
Spare (for future use)

o

o
o
o
o
o
o
o
1
1
1

2

1

o

o

o
o

1
1

o

o

1
1
1
1

o
o

o
o

o
o

1

1

1

1

0
0
1
0
1
0
1
0
i
0
1
1

Refer to the drive manufacturer's manual in configuring the drive for
fast-, Dr buffer-step options.
In cases where the drive is hardwareconrigured for fast stePI all commands which re~uire seek option
selection must use the fast-step option for that drive.
NOTE
The Itep option bits (3 through 0) are mutually
elclusive and only one option should be selected
in an~ given configuration.

Bits 4-5 are reserved for future

US8.

If bit 6 is a 1, during a read sector command. the failing sector is
not re-read an the next revolution before attempting correction.
This bit should be set to 0 for normal operation.
Bit 7 dis.bles the four retries by the controller an all disk- access
command.
Set this bit only during the evaluation of the performance
of a disk drive.
This bit should be set to 0 for normal operation.

,
Texas Instruments

2-82

Preliminary - Jan 21.

1983

TECHNICAL REFERENCE

HARDWARE

Command Com~letion Status Byte. At the end 0# a command,
the cont~olle~ returns ONE completion status byte to the computer to
indicate if an er~ar occurred during command execution.
The REGUEST
SENSE STATUS COMMAND must be issued if the erro~ bit is set to
determine the cause 0# the er~o~.
The ¥o~mat o~ the completion
status byte is
2.12.5.5

MSB

BIT NUMBER
7

1/0

6

5

4

LSB
2 I

3

1

o·

Port
+==--==+-=====+======+======+======+======+=====+======+
Address IDon't IDon/t IDriv. IDon't IDon/t IOon/t IErrorlDon't
0030
Icare Icar. INo.
Icar. lear. lear. : bit leare
(Y-ead)

+======+======+======+======+======+======+=====+======+

Logical Address (HIGH,
MIDDLE AND LOW)'
address of the drive is computed b~ using the fallowing
2.12.5.6

The logical
e~uatian.

Logical Address • CCYADR x HDCYL + HDADR) x SETRK + SEADR
Where:

"

-"

CYADR
HDADR
SEADR
HDCYL
SETRK

•

C"linder address

-

Numb.,. of heads pe,. c~linder
Number of sectors per t~ack

Head addl'ess
= Sector
address

•

•

Sector Interleaving.
Va~iable
sector interleaving i:
supported by the disk eontl'oller.
When an~ format command is issue6'
an~
interleave value up to the number 0# sectors-per-track minus
ma" be passed in the' device control black (DCB b"te 4>.
Th:
interleave factor may be adJusted for maximum system performance ~hen
transferring multiple sectors of data.
Intel'leaving allows logical
continuous sectors of data on a given track to be mapped onto
nonadJacent physical sactors.
An interleave factor of 5,
Tor
instance, means that every fifth physical sector is transferred as
the next continuous l(',gical sector of data.
It does not mean that
five sectors of data are ~ransfer,.ed an one revaluti on.
If the CPU
cannot trans'e,. the full sector of data during the secto,. interleave
time availab Ie, then the cant~aller has to ~ait a full revol ution
before the next logical sector can be read from the disk.
IT this
happens, the interleave -flactar is too law and should be increased
until an incl'.ase in operating system speed is noticed.
2.12.5.7

In order to take full advantage of the interleaving feature a~ the
controller, the operating system should perform multiple-sector data
transfers.
If single-sector trans~e,.s are employed, the difference
in speed with val'ious interleave facto~s ma~ not be noticeable.

Texas Instruments

2-83

P~el

iminal'Y - .Jan 21,

1983

, TECHNICAL,.. REFERENCE

2.12.6

Detailed

HARDWARE

of Commands

Desc~iption

The commands fall into eight classes, 0 th~ough 7) only classes 0 and
7 a~ e us ed.
Cliil 5S 0 command 5 a~ e da ta, non-data transfer. and Ii tatu ~
commands.
Classes 1 through 6 a~e ~ese~ved,
Class 7 command~
pe~'o~m
diagnostics.
Each command is desc~ibed in the ~ollowin9
paTagraphs.
The command description includes class.
optod!!,
an'J
format.
IIDont eare ll bits are shown as "unused ll ,
2.12.6.1
TEST
DRIVE READY Command.
This command selec ts a
particular drive and ve~ifies'that the drive is read~.
The following
diagram shows the fOTmat of the device control block for this
command:
B
~

t +-----------------------BIT NUMBER----------------------+
e 1
7 1 Bit 61 Sit SI Bit 41 Bit 31 Bit 21 Bit 11 Bit 0:

+-V-+======+-=====+==--==+======+======+======+======+======+
1010

0

0

0

0

0

0

0

+---+------+------+------+------+------+------+------+------+
I 1 I
o
o I DRIVElunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 2

lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunused:

I 4

lunusedlunusedlunusedlunusedlunused:unusedlunusedlunusedl

+---+-------+-------+------+------+------+------+------+------+
I 3 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunused:
+---+------+-------+------+------+--------+------+------+------+
+---+-------+------+------+------+------+------+------+------+
I S lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunused:

+---+------+------+------+------+------+------+------+------+
The TEST DRIVE READY command can be used with overlapped seeks to
determine when a dTive has completed seeking before issuing the next
command.
If the drive is still seeking. the status bVte at the end
of the command indicates iiln eTro~. and the sense status indicates
"drive still seekingl' Ctvpe 0 eTTO~, code B>'
/It se'luence of TEST
DRIVE READY comm.nds can thus be used to determine when the d~ive is
re.dv for the next comm.nd.

•

Texas Instruments

2-84

Preliminarv - Jan 21.

1983

TECHNICAL REFERENCE

HARDWARE

2.12.6.2
RECALIBRATE DRIVE Command.
This command positions th~
read /1111' i te (R/W) arm to t,.ac k 000.
Bit d e-P i nit i ons ~or th is co mman d
are 'as fallo..,s:
B
~

t

+-----------------------BIT NUMBER------------~---------+
7· I Bit 61 Bit 51 Bit 4: Bit 31 Bit 2: Bit 1i Bit 0:

+-.-+-= ____
1010
0
a
0
a
010
1
+---+------+------+------+------+------+------+------+------+
I 1 I
o
o I DRIVElunusedlunusedlunusedlunusedlunusedi
+---+------+------+------+------+------+------+------+------+
I 2 lunusedlunusedlunusedlunusedlunusedlunusedlunused:unused:
+---++------+------+------+------+------+------+------+
+a.a=~+-====-+======+======+======+======+======+

13 lunusedlunusedlunusedlunusedlunused lunusedlunusedlunusedl

+---+------+------+------+------+------+------+------+------+
I 4

lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl

+---+------+------+------+------+------+------+------+------+
I 5 IRETRV?I
0
0
I
0
ISTEP 3:STEP 21STEP llSTEP 0:
+---+------+------+------+------+------+------+------+------+
2.12.6.3
REGUEST SENSE STATUS Command.
The computer must send this
command immediatelCj after it detects an e,.ro,..
The command cause~,
the ContT"olle1" to T"etu1"n fouT" bejtes of drive and cont,.olle,. status:
the formats of these flour bCJtes a,.e shown afte,. the DCB.
When an
e""o" OCCUl"S an • multiple-sectol" data tl"ans4le,. (,.ead 0,. ",,.ite). the
REQUEST SENSE STATUS command l"etul"ns the logical address 041 ~he
flailing sectol" in bCJtes 1, 2 and 3.
I-P the REQUEST SENSE STATUS
command is issued afte,. anCJ o~ the Format commands 0,. the CHECK TRAC~
FORMAT command, the logical addT"ess T'etuT'ned bej the controller points
to one secto,. beejond the last tT"ack fOl"matted 0,. checked i-P the,.e was
no errol".
I~ thel"e was an erl"Ol". the logical address returned points
to the track in e,.,.or.
Table 2-26. Table 2-27. Table 2-28. and Table
2-29 list the .1"1"01" codes.
De~initions aT these bytes -Pollow:

B
ej +-----------------------BIT NUMBER----------------------+
t
7
I Bit 61 Bit 51 Bit 41 Bit 3: Bit 21 Bit 11 Bit 01

+-e-+-=-===+--==a=+-====-+======+======+======+======+======+
a

1010
0
0
0
0
1
1
+---+---~-+-------+------+------+------+------+------+------+

1 1 I

o

o

I ORIVElunus&dlunusedlunusedlunusedlunused:

+---+------+------+------+-----+------+------+------+------+
I 2 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunused:

+---+-~----+------+------+------+------+------+------+------+

1 3

\

lunused:unused:unused:unu5e~lunused:unused:unused:unused:

+---+------+------+------+------+------+------+------+------+
: 4 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunused:
+---+------+-----+------+------+--...---+----+------+------+
1 5 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunused:
+---+------+------+------+------+------+------+------+------+
Tex.s Inst,.uments

2-85

Pre 1 i mi nary -

Jan 21,

198:3

TECHNICAL REFERENCE

HARDWARE

S.ns. Bytes R.turned. The ad=ress valid bit (bit 7) in the error code
byte
is relevant only when the previous command required a logical
block address; in this case it is always returned as a
1;
otherwise
it is set to O.
For instance, i~ a RECALIBRATE com.... nd is ~ollCMlled
immediately bV a REGUEST SENSE STATUS com.... nd, the address valid bit
could be returned as 0 since the command does not require a logical
block address to be passed in its DCB.
The ~or .... t
~Dr
the sense
bytes returned are as ~ollows:
B
y

·t

+---------------------------BIT

I

7

6

5

4

NUMBER------------------------·---+
I

3

I

2

1

0

+-e-+=c=-===_+==~==_+======-+===-===+===__==+.-s==-=+.----.=+-.

: 0

I ADDRESS? I

0

ERROR TYPE

___ ==+

ERROR CODE

+---+--------+-------+-------+-------+-------+-------+-------+-------+
(see note) I
: 1 I
o
o
IDRIVE
HIGH ADDRESS
+---+------~-+-------+-------+-------+-------+-------+-------+-------+

: 2 I

MIDD~

(see note) I

ADDRESS

+---+--------+-------+-------+-------+-------+-------+-------+-------+
(see note):
I 3 I
LCIol ADDR ESS
+---+--------+-------+-------+-------+----~--+-------+-------+-------+

Texas Instruments

2-86

Preliminarv -

Jan 21.

1983

HARDWARE

TECHNICAL REFERENCE

Table 2-26

HEX

T~pe

a

Error Codes, Winchester Disk

DEFINITION

CODE

o

The controller detected no error during the execution
of the previous operation.

1

The controller did not detect an index signal
drive.

~rom

The controller did not get a SEEK COMPLETE signal
the drive after seek operation.

the
~rom

3

The controller detected a write fault from drive during
last operation.

4

After the controller selected the drive,
not respond ~ith READY signal.

-' ,

the drive did

After stepping maximum number of c~linders, controller
did not receive track 00 signal from the drive.

Texas Instruments

2-87

Pre 1 i minary - .Jan 21.

1983

TECHNICAL REFERENCE

Table 2-27

•

HEX

CODE

HARDWARE

Tvpe 1 Error Cades,' Controller Board

DEFINITION

o

ID Re~d Error: The controller detected an ECC error in
the tilrget ID 4=ield on the disk.

1

Data Erro~: The controller detected an uncorrectable
ECC error in the target sector during a read operation.

2

Address Mark: The controller did not detect the target
ad dress ma~k (AM) on the disk.

3

Not used.

4

Se~tor

5

Seek Error: The controller detected an incorrect
c,linder or trilck, or both.

6

Not used.

7

Not used.

e

Correctable Data Error: The controller detected a
correctable ECC error in the target data field.

Not Found: The controller 4=ound the correct
cylinder and head, but not the target sector.

Sad Track: The controller detected the bad track 4=lag
during the last operation.
A

Formilt Error: During II check-track command,
troller detected one of the 4=ollowing:
1) track not 4=ormatted
2) wrong interleave
3) ID ECC error on at least one (1) sector

Texas Instruments

2-88

the con-

Prel i minarIJ -

~an

21,

198;j

TECHNICAL REFERENCE

Table 2-28

HEX

TVp.~

TYPE

CODE

HARDWARE

2 and 3 Error

Code~.

Command and Miscellaneous

DEFINITION

o

Invalid Command: The controller has received
an invalid command ~rom the hat

1

IllegAl Disk Address:
The cont-roller detected an address that is beyond the maximum
,..nga.

o

3

RAM Erro,.: The cont,.oller detected a d.ta
a,.,.or during the RAM sactor bu~fer
diAgnostic.

1

3

Prog,.am Memorv Chacksum Error:
During its
intern.l diagnostic, the ~ontroller detected
.. program-memory checksum er,.or.

3

ECC Polvnomin.l E,.,.o,.:
During the cont ... ollars int .... n.l diagnostic, the ha,.dware
ECC gane,.ato,. '.iled its test.

_."

•

\

Texas Instruments

i2-89

Preliminary - Jan 21.

1983

HARDWARE

TECHNICAL REFERENCE

2. 12.7

Error Codes

The following is a summar~ of the er~or cod.es returned as the Tesult
of the REQUEST SENSE STATUS ~ommana.
NOTE:
The ADDRESS VALID bit (bit 7)
included here.
Table 2-29

ma~

or

ma~

not be set and is not

Error Code Summary

MEANING

ERROR CODE

:
:1 I
o
o
101

o

+-+-------+-------+-------+-------+-------+-------+-------+-------+
(see note] I

MIDDLE ADDRESS

+-+-------+-------+-------+-------+-------+-------+-------+-------+
(see note):
LOW ADDRESS

13:

+-+-------+-------+-------+-------+-------+-------+-------+-------+
UNUSED

:41

+-+-------+-----~+-------+-------+-------+-------+-------+-------+

:5: RETRY?:
o
o
o I STEP 3: STEP 2: STEP 1: STEP 0:
+-+-------+-------+-------+-------+-------+-------+-------+-------+

,,
,,--.'

)

Ov.,.lap Seeks with Buffe,.ed St.p Drives.
For d,.ive5
buffe,..d s.eks, SEEK" commands can be overlapped.
After thE
cont,.oll.r issu.s ill SEEK to the d,.ive.
it retu,.ns ill completion
status, not l&Iaiting
the drive to complete the SEEK.
I~
th€.'
,.etu,.n status sho...s '('0 e,.ro,., then the SEEK l&Ias issued co,.,.ectly.
It
the,.. is an erro,., than the SEEK l&Ias not issued.
A~ter transflerino;,;
the status, anoth.,. command can be issued to eithe,. drive.
If a new
command
is ,.eceived ito,. a drive l&Iith an outstanding SEEK. then the
cont,.olle,. waits .... ith BUSV active. for the SEEK to complete be';ore
executing the n .... comm.nd
(except the TEST DRIVE READY command),
Th.,.e is no time-out condition in the cont,.oller,
l&I.iting for the
buffered-step SEEKS to complete.

2.12.14.1
.mplo~ing

'0,.

'-.
Texas

Inst~uments

~-97

Pl'eliminal'Y - Jan 21.

19SJ

HARDWARE

TECHNICAL REFERENCE

2. 12. 15

INITIALIZE DRIVE CHARACTERISTICS Command

This command enables the user to configure the ,ontroller to work
with drives that have diffe~ent capacities and cha~acteristics.
Howeve~,
both Winchester drives must be of the same manufacturer Cir,d
model number.
After the computer sends the command (DCB) to the controller. it then
sends an eight-byte block of data that contains the d~ive parameters
Some of the paT'amete~s occupy two b\jtesi all two-byte paT'amete~s aT'e
transfer~ed
with the most signi-Picant byte (MSB) first.
The eigh t
bytes are listed below.
C = Maximum number of cylinders (2 by tes)
H = Maximum number of heads ( 1 b \lte)
W = Starting reduced write curren t cylinder (2 bytes)
p = Starting write precompensation cylinder (2 b"tes)
E = M.u imum ECC data burst length (1 byte)
When the controller is powered up or reset, the default values
listed below are set.
Maximum number of cylinders = 153
Maximum number of heads
4
Starting reduced write current cylinder • 129
Starting write precompensation cylinder =64
Maximum ECC data burst length = 11 bits

=

The parameter for the maximum ECC burst length defines the length of
a burst error in the data field that the controller is to correct.
The burst length is defined as the number of bits from the first
error bit to the last error bit. For example, if the controller
detects as-bit ECC error and the erroneous data appears as C5 (liOO
0101) before correction, it could appear as D4 (1101 ·0100) after the
correction.
However, if the CPU has set the max imum ECC burst length
at 4 bits, the controller might flag this data .s uncarrectable.
This is a type 1. code 1 error.

Texas Instruments

2-98

Preliminary - .Jan 21,

1983

TECHNICAL REFERENCE

-,

Byte de'initions
as '0110"s:

'O~

HARDWARE

the INITIALIZE URIVE CHARACTERISTICS command

a~e

•

B

IJ
t

+-----------------------91T NUM9ER----------------------+
7
: Bit 61 Bit 5: Bit 4: Bit 3: Bit~: Bit 1: Bit 0:

e I

+-V-+======+======+======+======+======+======+======+======+

: 0 I
o
o
o
1
o
1
o
o
+---+------+------+------+------+------+------+------+------+
+---+------+------+------+-~---+------+------+------+------+

: 2 lunusedlunusedlunused:unusedlunusedlunusedlunusedlunusedl

+---+------+------+------+------+------+------+------+------+
: 3 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunused:

+---+------+--~+------+------+------+------+------+------+

I 4 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl

+---+------+------+------+------+------+------+------+------+
I 5 lunusedlunused lunusedlunusedlunusedlunused 1unused I unus edl
+---+------+------+------+------+------+------+------+------+
2. 12. 15. 1
cont~oller

D,.i ve
a~te,.

P aramete,. BIJ tes.
These bytes a,.e passed to the
the INITIALIZE DRIVE CHARACTERISTICS command has

been issued:

-.

B

y+-----+------+-8
7
6
I

t:

I T

5

N4
UMB3
ER-+-------+------+-------~
210

+e+===-===+-======+==--===+=======+=======+=======+=======+=======1
MAXIMUM NUMBER OF CYLINDERS: MSB

101

+-+-------+-------+-------+-------+-------+-------+-------+-------~

I 11

MAXIMUM NUMBER OF CYLINDERS: LSB

+--+-------+-------+-------+-------+-------+-------+-------+-------+
0
I
0
0
0 : MAXIMUM NUMBER OF HEADS
I~I

+-+-------+-~-----+-------+-------+-------+-------+-------+-------+

: 31

STARTING REDUCED wRITE CURRENT CYLINDER:

MSB

STARTINO REDUCED WRITE CURRENT CYLINDER:

LSD

+-+-------+-------+-------+-------+-------+-------+-------+-------+
+~+--------+-------+-------+-------+-------+-------+-------+-------+

STARTING WRITE PRECOMPENSATION CYLINDER:

lSI

MSB

+-+--------+-------+-------+-------+-------+-------+-------+-------+
161
LSB
STARTING WRITE PRECOMPENSATION CYLINDER:
+-+-------+-------+-------+-------+-------+-------+-------+-------+
17:

0

0

I

0

0 : MAXIMUM ECC DATA BURST LENGTH :

+-+-------+-------+-------+-------+-------+-------+-------+-------+

'-_

..

Texas

Inst~uments

2-99

p,.el imina,.y -

~an

21.

1983

TECHNICAL REFERENCE

2. 12. 16

HARDWARE

•
READ ECC BURST ERROR LENGTH Command

This command t1'.ns'ers ane byte to the CPU.
This byte contains the
value of the ECC bU1'st length that the cont1'oller detected during ~~e
last Read command.
This byte is valid onl" after a correct.ble ECC
data .1'1'01'. type 1. code B.. Byte definitions are as follows:
B

"et +-----------------------BIT
1
7 1 Bit 61'Bit SI Bit 41

NUMBER-------------------~--+

Bit 31 Bit 2: Bit 11 Bit 0:

+-v-+==---·+==-=-=+======+======+======+~===-=+======+-===-=+

I 0 I

o

o

o

o

1

1

o

1

+~--+------+------+--~---+------+------+------+------+------+

I 1 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedt

+---+------+--~---+------+------+------+------+------+------+

I 2 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunused;

+---+------+------+------+------+------+------+------+------+
I 3 lunused:unusedlunusedlunusedlunusedlunusedlunusedlunusedl

+---+------+------+------+------+------+------+------+------+
I 4 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedt

+---+------+------+------+------+------+------+------+------+
: 5 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedt

+---+------+------+------+------+------+------+------+------+

Texas Instruments

2-100

Preliminary -

~an

2i.

1983

TECHNICAL REFERENCE

2. 12. 17

HARDWARE

FORMAT ALTERNATE TRACK Command

F~MAT
ALTERNATE TRACK fa,. mat s th e hea d.,. f i el d 5 of th e .. bad t ,.ac k "
with the alt.,.nat. t,..ack info,..mation
(assigned by the CPU>'
The
alt.1"nate t,..ack is fo,.matt.d
to identify it as an alte1"nate.
The
command byte da9initions for FORMAT ALTERNATE TRACK a,.. as follows:

B

,,+------+----+-8 I T
tt

7

I

6

I

+e+--·---·+-------...
lor
0
0

5

N U 1'1 B E R
I

4

I

3

-+------+------+-----~

I

2

1

0

----=+=-a..--+-==---=+=-=---=+-=~==+====-==+

0

0

1

1

1

0

+~---+------+---~-+-----.-.-----+-----+----+------+

1 11

o

o

:DRIVE

HIQH

ADDRESS

(not. 1 ):

+-+------~-----+-------+-------+-------+-------+-------+-------~

( not e 1 ):

MIDDLE ADDRESS

+~-----+-------+--~-+-------+-------+-------+-------~------+

( note 1 ):

LOW ADDRESS

131

+-+---~-+------+-------+-------+-------+-------+-------+------+

( not. 2 ):
o
o ,,
INTERLEAVE FACTOR
+~-----+-------+-------+-------+-------+-------+-------+-------~
: 5: RETRY?:
o 1(Note 3) o I STEP 31 STEP 2: STEP 1: STEP 0,

o

+-+__----_+_-----~-----+__-----+_------+_------+__-----+_------i

NOTES:

1. R.fe,.. to pa,.ag,.ap h 2. 12. 5. II.

"Logical Add,.ass".

~

Int.,.le.v. 9acto,.. is 1 to 31 90,. 256 byte secto,..s
and 1 to 16 90,. 512 bvta sacto,.s.

3.

19 this bit is set, the data in the existing sector buffer
is used to fill the data field. 19 this bit is cl.a,..ed,
the data 9i.ld is w,..itten with 6C hex.
•

The inte,..l •• v. b"te (4) is prog,.Ammed the same AS in the FORMAT
command,
and is us.d on the alte,.nat. t,.ack.
If bit 5 of control
b"t. (,) i • • • t, the data in the existing secto,. buffe'" is used to
fill
the data 9i.ld.
If nat set, the data field is w,.itten with aC
h.l.
Aft.,. issuing the command,
the cont,.olle,. asks fo,. the
90110wing 3 bytes.
These bytes point to the CPU-assigned alte,.nate
logical add~.ss.
Again the seeto,. add,..s. is igno,..ed.

~-101

P,..l i mina,.y -

~n

21,

1983

TECHNICAL REFERENCE

HARDWARE

-,
Assigned Alternate
definitions are as follows:

2.12.17.1

Address

Data

B

V+-------+-------+-B I T
7
6
5

t:

N U M B E R

4

:3

Block.

The

-+-------+-------+-------+
1
o

+e+=======+--=====+··=====+=======+-======~=·-====+==-====+==-====+

101

0

0

0

HIGH

ADDRESS

(see note):

+-+-------+-------+-------+-------+-------+-------+-------+-------+
. (see note) I
111
MIDDLE ADDRESS
+-+-------+-------+-------+-------+-------+-------+-------+-------+
(see note):
LOW ADDRESS
+-+-------+-------+-------+-------+-------+-------+-------+-------+
NOTE:
t-o paragraph 2.12.5.6, "L.ogical Address".
Re~.r

Alternate Track Assignment.
The assignllent o~ alternate
tracks and the lockout o~ bad tracks has to be done bV the computer.
Bad ar.as on the disk are labeled de~.ctive on a track basis bV
issuing .. FORMAT BAD TRACK command (Command code 07). One pro·cedure
~or assignment and handling of alternate tracks is as follows:
2.12.17.2

1. The entire disk drive is formatted bV issuing a FORMAT DISK
command CCommand code 04) starting at logical t,.ack 000.
If an 1'''1'0,. occurs during formatting, then a REGUEST SENSE
STATUS co_and should be issued.
I~ a format error is
indicated, bVtes 1, 2, and :3 of the returned status gives
the address of the bad track and a FORMAT BAD TRACK command
(command code 07) should be issued to the track.
A new
FORMAT command is then issued to ~ormat the ,.est of the
disk starting at one track bevond the bad t,.ack.
I.f an"
other errors occur during the subse~uent formatting,
the
above process should be repeated until the enti,.e disk is
forma tted.
2. A RECAL.IBRATE command is issued
position the heads over track 000.

(Command

code

01)

to

3. All sectors on the disk are ,.ead to see whether an"
uncorrectable ECC error. have occurred in the data. The
FORMAT command places a 6C hex pattern in the data fields
of all sectors and the computer program can optionall~
verify this data pattern after the data is read into
memory.
However, verifying the data bvte-for-bvte is not
normallv necessa,.v since the error detection and correction
circuitrv flags .11 uncorrectable errors.
I~. la,.ge block
of host memory is available. multiple sector reads can be
issued to speed up the verify process.

Texas Instruments

2-102

Preliminary - Jan 21.

1983

TECHNICAL REFERENCE

HARDWARE

4. When .n unco,.,.ectabl", ~,.,.o,. is round, a FORMAT BAD TRACK
command (Command cod@ 07) is issued to the ~ailing t,.ack
which writes a bad t,.ack ~lag into .11 identi'ie,. ~ields.
Wheneve,. this t,.ack is sub5e~uently accessed, an e,.,.o,.
,.esults and the sense status which ~ollows indicat@s ~n
code 19 hex.

.,.,.0,.

Wheneve,. a use,. p,.og,.am accesses the disk, ~t should not b@ allowed
by the ope,..ting svstem to issue a READ 0,. WRITE command to the
.lte,.n.. t. t,.acks.
The disk cont,.oll.,. h.s no wav o~ knowing wn@n .n
.1t.,.nate t,.ack is being ,.ead.
The alte,.nate t,.acks a,.e sometimes
assigned at the end of the disk (highest t,.ack numbe,.s) but they may
be assigned to .nv t,..cks so lang •• the t,..ck label is maint.ined by
the compute,..
In gene,..l, i~ fau,. t,.acks .,.. ,.8se,.ved as .lte,.nates,
thev should b • • de~u.te ~o,. all disk d,.ive. cu,.,.ently av.ilable given
the .""01" correction c.p.bilitv of the cant,.all.,.;
however,
it is
recommended that the sv.tem p,.og,.amm.,. consult the disk d,.ive manual
for t h..
d de f • c t s p. c i f i cat ian s.

h.,.

2.12.17.3 Alternate Add"e.s p,.otocol.
Afte,. receiving the com.... nd
.nd the .ssigned .lte,.nate, the cont,.oll.r does the fallowing.

-

1. Se.ks to "alternate assigned track" .nd verifi.s it is

not
el,.e.dv an assigned alternate t,..ck, a,. flagged bad tT'ack.
If the t,.ack h.s .1T'eady b.en assigned .s.n alte,.nate a,.
is flagged "SAD", then 8rT'0" code 10 h.x is given and the
ea ..... nd is .bo,.ted.
This usually impli.s that the compute,.
is attempting to assign two (:2) bad t,..cks to the same
a 1 t.T' nitte t,.a c k.

2. Fo,.mats the track as an assigned alte,.nate t,.ack.
3. Seeks to the ubH tT'ack" and

~oT'mats the heade-r as a
t,.ack pointing to the assigned alte-rnate.

spa,..

NOTE
Data fields an both the bad t,.ack and alte-rnate
t,.ack aT'. dest-roy@d.

Using the FORMAT ALTERNATE TRACK Command
1. The cont,.alle-r must be initialized to includ@ the alteT'nate
t-rac k s cy 1 ind eT' and head ,.ang e9 .
..........

Texas Inst,.uments

~-103

HARDWARE

TECHNICAL REFERENCE

2. Note that. with alternate t,.acks. the entire disk is not
.vailable to the .vste~
Gene,.a11v the disk space is fixed
in the svstem software, which can be assigned as alternates
when need ed.
The number of spare tracks is dependent on d,.ive size and
number of defects allowed bV the drive manufacturer.
Generallv this is 1 spar. track for each 50 to 100 tracks .

4.

•

Assign each media defect an alternate track.

*

Assign alte,.nate
list of. defects.

t,.acks for drive manufacturer'.

In svstem operation, the alternate tracks ar, invisible to
the host.
The cont,.oller automaticilll" seeles to the
.ssigned alternate track when an access is made to a
flagged defective track.
"Consecutive" accesses to a flag
track does not ,.esult in reseeking to the alte,.nat. track.
The cont,.olle,. . . intains position ~n the alt.rnate track.

5. Direct acce.s (seeking to, or attempted data transfer) to
an alternate t,..ck results in an error code IC hex, and no
data transfer tak es place.

•

Texas Inst,.uments

2-104

Prel imina,.." - .Jan 21.

1983

TECHNICAL REFERENCE

2. 12. 1S

HARDWARE

WRITE SECTOR BUFFER Command

This command is used to ~ill the sector bu~~er with a host given data
pattern.
No t'rans~e,. of data takes place between the d,.ive and the
cont,.olle,. The command accepts 256 01' 512 bytes (depending on sector
size Jumpe'r) o~ data. and sto,.es" it in the sector buffer.
The byt~
definitions are as follo~s:

B
~

t +-----------------------BIT NUMBER----------------------+
• 1
7 I Bit 61 Bit 51 Bit 41 Sit 31 Bit 21 Sit 11 Sit 01

+-V-+--==--+=----=+===-==+-=====+===--=+=-====+======+=====-+

1010
0
0
0
1
1
1
1
+---+------+------+------+------+------+------+------+------+
I 1 lunu.edlunusedlunusedlunu.edlunusedlunusedlunusedlunusedl
+---+------+----+-------+0---+----+----+--........
I 2 lunusedlunu.edlunu.edlunusedlunusedlunusedlunusedlunused:
+---+-----+----+---+----+---+------+-----+------+
1 3 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+-----+----+-----+-----~----+---+--- ........
I 4 lunusedlunusedlunus.dlunusedlunusedlunusedlunusedlunusedl
+---+---+---+-----+-----+----+------+----+----+
I 5 lunusedlunu.edlunu •• dlunus.dlunusedlunusedlunusedlunusedl

----+
----+

\

~

+---+---+------+----+-----+--~-+----+----+----+

2. 12. 19

READ SECTOR BUFFER Command

0,.

This command .ends 256
512 bVtes of data (depending on secto,. siz~
Jumpe'r)
to the CPU from the secto,. buff.,.. "The byte definitions a,.e
AS

follo~s:

B
V

t +---------------------BIT NUMBER----------------------+
e I
7
I Bit 61 Bit 51 Bit 41 Bit 31 Bit 21 Bit 11 Bit 0:

+-V-+-~+=-----+----==+-==-==+======+======+======+==-===+

1010

0

0

1

0

0

0

0

+---+------+------+---~--+------+------+------+------+------+

I 1 lunusedlunu.edlunusedlunusedlunusedlunusedlunusedlunusedl

+---+------+~---+------+------+------+------+------+------+

I 2 lunusedlunusedlunusedlunu.edlunusedlunusedlunusedlunused:
+---+------+------+------+------+------+------+------+------+
I 3 lunusedlunusedlunu.edlunusedlunusedlunusedlunusedlunused:

+---+------+------+------+------+------+------+------+------+
I 4 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunused:

+---+------+------+------+------+------+------+------+------+
I 5 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
Tex.s Instruments

2-105

p,.el i mi na ry - Jan 21.

1983

TECHNICAL REFERENCE

HARDWARE

•

2. 12. 20

RAM DIAGNOSTICS Command

This command performs a data pattern test on
b~te definitions are as follows:

the

RAM

bUffer.

The

B
~

t

+-----------------------BIT NUMBER----------------------+

e

7

I Bit 61 Bit 51 Bit 41 Bit 31 Bit 21 Bit 11 Bit 01

+-V~+-=====+======+======+======+======+======+======+======+

1011

1

1

0

0

O'

0

0

+---+------+------+------+------+------+------+------+------+
I 1 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 2 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 3 lunusedlunusedlunusedlunused:unusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 4 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedt
+---+------+------+------+------+------+------+------+------+
I 5

lunusedlunused:unusedlunusedlunusedlunusedlunusedlunusedt

+---+------+------+------+------+------+------+------+------+
2.12.21

DRIVE DIAGNOSTICS Command

This command tests both the drive and the drive-to-controller
interface.
The controller sends recalibrate and seek commands to the
selected drive and verifies sector 0 of all the tracks on the disk.
The controller does not perform any write operations during the
command; it is assumed that the disk has been previousl~ formatted.
The bVte definitions for the command are as follows:
B
IJ

t

+-----------------------BIT NUMBER----------------------+

e I

7

I Bit 61 Bit 51 Bit 4: Bit 31 Bit 21 Bit 11 Bit 01

+-v-+=--===+-==-==+======+======+======+====--+======+======+
101111
1
0
0
0
1
1
+---+------+------+------+------+------+------+------+------+
I 1 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedt
+---+------+------+------+------+------+------+------+------+
1 2 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 3 lunusedlunusedlunusedlunusedlunusedlunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
14 lunusedlunusedlunusedlunusedlunused lunusedlunusedlunusedl
+---+------+------+------+------+------+------+------+------+
I 5 IRETRY? I
0
0
0
ISTEP 31STEP 21STEP 11STEP 01
+---+------+------+------+------+------+------+------+------+
Texas Instruments

2-106

Prel i minary -

~an

21.

1983

HARDWARE

TECHNICAL REFERENCE

2. 12. 22

CONTROLLER INTERNAL DIAGNOSTICS Command

This command causes the .:ontroller to per90rm a sel~-test.
The
controller checks its inte~nal processor,
data
bu~fters,
ECC
circuitrl:l'
and the checksum oft the p~og~am memor~.
The controller
does not access the disk drive.
The b~te de~initions are as ftollows:
B

"

t +-----------------·-31T NUMBER-----------------+
.:
7 I Bit 61 Bit 51 Bit 41 Bit 3: Bit 21 Bit 11 Bit 01
+-V-+--=~+=-=-~+=---==+====-=+======+=-=---+-====-+=====-+

: 0 :

1

o

o

1

1

o

1

o

+---+------+---~--+------+------+------+------+------+------+

I 1 lunusedlunusedlunusedlunus.dlunusedlunus.dlunusedlunusedl
+---+---~-+------+------+------+------+~---+------+------+

lunusedlunusedlunusedlunus.dlunusedlunusedlunus.dlunusedl

I 2

+---+------+------+------+------+------+------+------+------+

lunusedlunus.dlunusedlunusedlunusedlunusedlunusedlunusedt

I 3

+---+------+------+------+------+------+------+------+------+
I 4 lunusedlunusedlunusedlunus.dlunusedlunusedlunus.dlunusedl

+---+---+--+---+----+-----+---+---+----+
lunus.dlunus.dlunu •• dlunus.dlunus.dlunus.dlunu •• dlunusedl

I 5

+---+------+------+~--+------+------+------+-~---+------+

2.12.23

READ LONQ Comm.nd

This command transgers the target sector and ~our b"tes o~ data ECC
to the CPU.
1~ an ECC e,.ror occurs during the read, the cont1'"olie~
does nat attempt to c01'"rect the data ftield.· This com..... nd is useful
in ~.cov.1'"ing d.ta 'rom a .ecto1'" that contains an unco1'"1'"ectable ECC
.1'"ror.
It is .lso useful during di.gnostic operations.
The b"te
de'initions .re •• ~ollows:
B

y+-----+-----+-B I T

tl

7

I

6

I

5

NU MB E R -+------+------+------+
4

3

2

1

0

+e+-·~--+-=---==+---=-==+=-=-===+=====-=+=======+=======+=======+

: 0:

1

1

1

o

o

1

o

1

+-+-------+-------+-------+------~+-------+---------+-----+-------+

111
HIGH ADDRESS (see note)1
o
o
IDRIVE
+-+-------+-------+-------+-------+-------+-------+-------+-------+

MIDDLE ADDRESS

t 21

(see note) I

+-+------+------+--------+------+------+------+------+------+
: 3:
LOW ADDRESS
(see nate):
+-+-------+-------+------+-------+-------+-------+-------+-------+
: 41
BLOCK COUNT
(see nate):
+-+-------+-------+-------+-------+-------+-------+-------+------+
:51 RETRY?:

0

0

0 : STEP 3: STEP 2: STEP 1: STEP 0:

+-+-------+------+-------~-------+-------+-------+-------+-------+
NOTE: Re-P.1'" to pal'ag1'"aph ~_ 12.5.
"Logical Address".

o.

Texas Inst1'"uments

2-107

Pl'eliminar" - Jan 21,

1983

TECHNICAL REFERENCE

2.

1~,24

HARDWARE

WRITE LONe Command

This command t~ansfe~s a secto~ of data and fou~ appended ECC bytes
to th e dis k d~ i ve.
Du~i n 9
this wri t,. op.~ilti on,
the c:emp uter
supplies the fou~ ECC b~tes instead of the usual nardware- generated
ECC bytes.
This c:ommand is useful only for diilgnestic:. operations.
The but. definitions .~. as follows:
B
V+----+---+-B I T
tl

7

b

5

N U M B E R -+------+----+-----+
43210

o
1
: 0:
1
1
1
o
o
1
+-+-------+-------+-------+------+-------+---------+-----+-------+
HIGH ADDRESS (see note):
o IDRlVE
11:
o
+-+------+-----+-----+------+-----+-------+----~----+

121

MIDDL.E ADDRESS

(see note) I

+-+-----+-~-+-----+------+------+----+-----+----+

131

LOW ADDRESS

(see note) I

+-+-----+----+---+----+-----+-----+-----+-----+

BLoet( COLNr

141

+-+-------+----+-----+----+------+-----+------+-----+
151 RETRY? I

o

o

o

: STEP 3: STEP 2: STEP 11 STEP 0 I

+-+-------+---+-----+---+-----+-----+------+-------+

Texas Instruments

2-108

Prel i minary - Jan

~1.

1983

TECHNICAL REFERENCE

HARDWARE

2.12.25.1
Execution 041 Diagnostics.
Since all of the diagnostics
al"e nat executed b~ the computer on power-up, it is suggested that
the~ be called b~ the CPU in the 4Iollowing order:
1. CONTROLLER INTERNAL DIAGNOSTICS (Command code E4>'
This
diagnostic
tests all the logical and decision-making
capabilitv of the controller as well a. the program memor~
checksum and the errol" detection and correction circuits
(ECC). Execution of this diagnostic ensures that the
contl"olle1" cen communicate ~ith the computel".
2. RAM DIAONOSTICS (Command code EO). This command veri4lies
that th ••• ctOl" buffer i. opel"ational bV writing, l"eading,
and vel"il~ing various data pattel"ns to and fl"om all
1 ocetions.
3. If the pal"ametel"s of the connected drives al"e different
than the default pal"amete1"s, the ne.., configul"ation must be
.ent to the controller using
the
INITIALIZE
DRIVE
CHARACTERISTICS
(Command
code
eC) befol"e the DRIVE
DlAONOSTIC co--.nd is executed.

.........,

4. aelol"e the DRIVE DIAGI\I]STICS is executed,
the computel"
should continuously issue a TEST DRIVE READY command
(Command code 00) to the controller with the appl"opl"iate
tj . .-out until the d1"iva becomes l"ead~.
5. DRIVE DIAONlSTIC (Command coda E3>'
This diagnostic issuas
a RECALIBRATE to the di'sk d1"ive and tl1.n steps though all
tracks va1"ifving the ECC on the identi4lie1" fields of the
fi,.st seetol" of each tl-aclt.
If this diagnostic passes, it
impli •• that th. disk has bean fOl"m.tted and that the fil"st
ID field of each tl"ac It is good.

"•

2.12.25.2 El"l"ol" COl"l"ection Philosoph..,.
Since the t'lpical el"1"Ol"cOl"l"ection time of the cont1"011el" is approximatel.., SO ms and g1" •• te1"
than the time fol" one l"evalution of the disk, the .ecto1" in el"r01" is
option.IIv l"e-read (if bit 6 i. not set in byte 5 of the READ command
DeS) on the next 'revolution dU'ring a Read command.
In most cases,
the e'rl"Ol" is soft and does not l"eappeal" on the 're-read.
This initial
1"e-'read of the failing secto,. is ove,. and above the ,..1:1"'1 count
pas.ed in the DCB (bit 7, byte 5).

\.

The 'retl"'1 count on e1""o'rs is p,.e.et to 4 blJ the (ont1"oller each time
a sector has been read successfully.
On a multiple-sector trans~e1"
if an
uncG'rrect.ble .~~o~ was detscted but subs.qu.ntl~ ~ound to be
cOl"rectable an a r.tr~, the retr~ count is reset to 4 befo1"e the next
sector is read '~om the disk,
~-109

P1"eliminartj - Jan 21,

1983

HARDWARE

TECHNICAL REFERENCE

SectoT' Field De;cription.
The format of the sector'
configuration is given and the information fields in those sectors
~re identiFied in the follo~ing listing:
2.12.25.3

FIELD
AM
QAP1

SYNC
OAP2
COM
CVLH
CVll
I€AD
SEC

FLAO

ZER
ECC
OAP3
SVNC2
OAP4
DATA
ECC2
QAP5

NUMBER OF
BYTES
4
9
1

2
1
1
1
1
1
1

1
4
16

1
2
512

4
43

The tl"ack lavout faT' the 512
in Table 2-30.

Texas Instruments

FIELD
DESCRIPTION
Address mark
Zero bvt e gap
ID svnc bVte
1D Zel"D bVte gap
ID tompaT'e bvte
Cvlinder high (MSB)
C"lindeT' lo~ (lSa)
Head numbel"
Sector numbel"
Flag bvte
ZeT'o bVte
ID ECC bVte.
ZeT'o bvte gap
Data field svnc bV te
Data field zel"O bV te gilp
D.ta field
Data field ECC bVte.
Inter-record ze,.o gap
b~tes/sector,

2-110

17 sectors/t,.ack is

PT'eliminary -

~~n

21.

given

1983

HARDWARE

TECHNICAL REFERENCE

Table 2-30

512-Bytes-Per-Sector Format

MSB

LSD

+------------------BIT NUMBER-------------------+
B VTE
7
6
5
4
3
2
1
0
========+=====+=====+=====+=====+=====+=====+=====+=====+
ADDRESS MARK

1-4

--------+-----+-----+-----+-----+-----+-----+-----+-----+
o
o
o
o
o
o
o
o
5-13
--------+-----+-----+-----+-----+-----+-----+-----+-----+
14
ID SYNC BYTE
--------+-----+-----+-----+-----+-----+-----+-----+-----+
15-16
0
0
0
0
0 I 0
0
0
--------+----+-----+---_.+-----+-----+----+----+----+
17
ID COMPARE BYTE
--------+-----+----+-----+-----+----+-----+-----+-----+
CYLINDER NUMBER ( MSB )
1S
-------+-----+-----+----+----+-----+-----+----+-----+
19
CYLINDER NUMBER ( LSD )
----+--+-----+---+----+---+----+-----+-----+
HEAD NUMBER
20
-------+-----+-----+----+----+-----+-----+-----+-----+
21
SECTOR NUMBER
I
I

--------+-----+-----+-----+-----+----~+-----+----+-----+
...

-

FLAG BVTE

--------+-----+-----+-----+-----+-----+-----+-----+-----+
o
o
o
o
o
o
o
o
23

--------+-----+-----+-----+-----+-----+----+-----+-----+
24-27 I
ID ERROR CORRECTION CODE BYTES
--------+-----+-----+-----+-----+-----+-----+-----+-----+
28-43 I
0
0 I 0
0 I 0
0
0
0
--------+-----+-----+-----+-----+-----+-----+-----+-----+
44
DATA FIELD SYNC BYTE
--------+-----+-----+-----+-----+-----+-----+-----+-----+
45-46 I

0

o

o

o

o

o

o

o

--------+-----+-----+-----+-----+-----+-----+----+-----+
47-558 I
512 BYTES DATA
--------+-----+-----+-----+-----+-----+-----+-----+-----+
559-562 I . DATA FIELD ERROR CORRECTION CODE BYTES
--------+-----+-----+-----+-----+-----+-----+-----+-----+
563-605 I

0

o

o

o

o

o

o

o

--------+-----+-----+-----+-----+-----+-----+-----+-----+
Track
= 10416
Capacit~

10285
+131

=
=

17 sectors o~ 605 bytes/sector
Speed tolerance gap

10416
605 bytes/sector including 1D and overhead

Texas Instruments

2-111

Preliminary -

~an

21.

1983

l---w-tn"" ...." _

2.12.26
The

Specifications -

Wincheste~

Cont~oller

Board

controller board specifications are given in Table 2-

31

Tabl. 2-31

Winchester Controller Board Specifications

STDRAOE

DPERATINO
o

TemperatUT"e
Relative

0

0

0

10 CC32 F) to 40 CC131 F)

o
0
0
0
-10 CC-40 F) to 60 C(167 F)

Humidit~

o

(@ 40 F

wet bul b t.mp.,
no c ondenut ion)

lOX to 90%

Altitude

Va...TACE
+5.0 Vdc

-12.0 Vdc

Texas

Inst~uments

10%

Me.n sea level to
10 000 f.et

RANCE

to 90%

Mean sea level to
45 000 feet

CURRENT

4.75 to 5.25 Vdc

-10.B to -13.2 Vdc

2-112

2.5 A maximum
2.0 A tvpical
66. 0 mA max imum
48. 0 mA tvp ical

Preliminar" - Jan 21,

1983

TECHNICAL REFERENCE

HARDWARE

Thi. pa~ag~aph .pecifies the elect~ical
the 5 1/4-inch Wincheste~ disk d~iv •.

inte~face

requirements

for

All

Winchest_~
controller boa~ds shall
inte~changable ~ith the AMP type 87~15-7 ~o~

use header assemblies
the 20-pin connectors (
to J2/P2 ), and t,pe 1-87215-7 for the 34-pin connector ( to JI/Pl ).
The connector l • .,out is sho.n in Figure 2-18.

+--------Wine

---------------+
WINCHESTER

hest.~

CONTROLLER
BOARD

disle drive

--..-.---'

AMP heade,.
a •• emb 1'1
t,pe 87215-7
or eq,u ivalent

+--+

[
[

Ribbon cable to
Winchester drive

AMP
receptacl_ * *
c onnec tor * *
* *
tljpe
* *
98377-4
*
*
or eq,u i v.

C
[
C
[

AMP
ribbon
connector
tvp ..
88373-6
o~ equiv.

+--+

P:!

* *•••=-_ ......
-=--==---*
+--+

C

J2

+-+

+--+

Rib bon cab Ie to
Winchester drive

+--+

+-+
[

AMP he.de~
••• emb 1'1
tlj pe 1-87215-7
or _q,uivalent

C

AMP
*
receptacle *
*
connec tor *
*
t,pe
* *
88377-6
* *
or equiv.

C
C

•

t
C
C
C
C

• *

AMP
ribbon
connector
t,pe
88373-3
or eq,uiv.

P1

- J1

+-+

+--+

34-pin ribbon cable

+--+

+-----------

----------------+
Figure 2-18

Control and Data Cabling

2-113

P~.limina~v

- Jan 21,

1983

HARDWARE

TECHNICAL REFERENCE

2. 13

CLOCK AND ANALOG INTERFACE BOARD

This subsection d.sc~ib.s the operations of the clack and analog
interface boa~d.
This board contains logic for inteT'facing a light
pen to the compute~ s~stem and a ROM, which is p~ogrammed with the
driver routines faT' the boa~d.
2. 13. i

Desc~iption

The board is composed of thT'ee separate and distinct sections:
Tha
analog input section, the real-time clack section. and the light pen
section.
The sijstem black diagram is sho"," in Figure 2-19.
and the
timing diagram in Figu~. 2-20.

Texas Instruments

2-114

P~eliminaT'Y

- Jan 21,

1983

I

)

l

-t

..•
M

III

INTERRUPT
ENABLE

ADDRESS
BUS

2K)(8
ROM

ROM
ADDRESS
DECODE

.-

INT
LOGIC

INTERRUPT
DISABLE

iiif

"'"
LlGHTPEN
CONNECT R

a

TlPSW

'-.-)

-

INTS

TO INTERNAL
DATA BUS

ANALOG/CLOCK
INTERLOCK AND ROM
I"...........

ADDRESS
BUS

ADDRESS
DECODE

STATUS
LATCH

r-

~

,
...
P.l
~

UI

TO STATUS
LATCH

1

SYSTEM
DATA

,

.

CLOCK

ISTATUS
AND
DATAl

ANALOG/ CLOCK

2-19

ANALOG
INPUTS

'-.)

CLOCK
LATCHES

2

4

A TO-D
CONY

--

1/0
READ
WRITE
LOGIC

Figu~e

'-"

~

10RC
AIOWC

SWITCH
INPUTS

r----

DATA
BUS
BUFFER

BUS

-

4

V

BATTER V
LOW

VOLTAGE
SWITCH
LOGIC

I/O SECTION

Clock and Analog Interface Block Diagram

?
~

I

~

.."

It
1/1

....

:s
III

PClK

rt"

"i
C

:J

It

:s

ADDRESS
BUS

____

-Jx~

___________________________________________x=:

rt"
1/1

m
11 OF 41

,~--------------------------------------~;--

~

ALE
IADCOIIJ9I
START

,~--------------------------~/
----_____~I

\~---------

- - - - - - - - -_____~I

\~------

~ -------------~\~

____________________________JI

_________-J!

\~------------

OE

...,'lJ

'II

....
....3

::3
II

...,

(

DATA OUT
IADC0808I
DATA IN
1110881

DATA AVAILABLE

)

------------------------------------------~~~------------CLOCK AND ANALOG INTERFACE TIMING DIAGRAM

c
I

c..

III

Figur.2-20

Clock and Analog Interlace Timing Diagram

::J

....

-0

m
1..:1

J

./

1~~HNl~AL

"
,

r

2.13.2

HARDWARE

H~~CHENCE

Analog Input

The analog
input converter section is basically designed as a game
controller.
Allowable game controller conliguratlons include one or
tldO JOl:lsticks.
up
to lour paddle controllers,
and up to .pour
switches.
The slditches SW1-SW4 are semi-debounced by
the simpl~
resistance-capacitance
(Re)
circuit
consisting o.p a O.047-uF
capacitor to ground and a l-kohm ~esistor to +5 V.
The switch signal
is 9ad into the status latch along with an end 09 conversion
CEOC)
signal from th'e analog to digital converter (ADC) and the low battery
signal from the clack section.
The outputs ail the status latch U8
are tri-stable.
The (tri-stated) outputs are allowed to .pollow the
inputs until the latch is selected by an access to location COH.
The
latches a~e continued
in a high-impedance state until the 1/0 read
signal is asserted.
This prevents the contents oOP the latch
.pram
being gated onto the bus during a memory cycle.
The latch also
contains a bit indicating the state of the light pen inta~rupt signal
and a bit indicating the state of the tip switch an the light pen.
The ADC used is an eight input channel ADCOeOe.
This part can
multiplex eight analog input signals into one selected digital output
signal.
The analog channel is sele'cted by a ~ite into location C9HCFH.
This write .lso generates the timing req,uired to run the
ADCoeoe.
First, the inverted falling edge o.p the AIOWC- signal (near
the start of the c~cle) clocks the state of the ADCSEL- signal to the
Q- output of I.17A.
The~efo~e,
the ADCSEL- signal
goes high
onll.
du ... ing a write to a
location in the ADCSE.- address space.
Thi s
.ignal is used to g.n .... at. ALE to the ADC0808.
This sign.l
is als(
tied ta the D input af U7B.
This is clacked through abaut 100 m!>
lat.r an the nert falling .dge af PCLs( from the slJstem bus.
Th:::'
signal g.nerated by U7B is the START signal for the ADC080a
Both
U7A and U7B are s.t ta a laid output on the ~irst high
clack a~te'
AIOWC- ga.s inactive.
From this point an, the conve... sian is automatic.
It takes less than
70 us to camplet. the conve ... sion, at which time the EOC signal is
raised.
The state af this signal can be monitored by reading the
status latch ·US.
NOTE
The EOC signal should not be conside~ed valid
until 4 us . , t .... the write to the ADC0809.
The
EOe signal is narmally high, an~ does not go low
until
that length af time after receiving the
canvert cammand.
Once the convers ian
is
ind eed
complet., the data can be read from locati an C8H.

'-

To initialire the analog to digital conversion from the four analog
inputs, write ta the locations indicated .par the cor~esponding analoQ
inpu t c h anne 1.
;!-117

P~eliminary

- Jan;!L

i983

Channel 0
1
Channel 2
Channel :3
Ch~nnel

(X 1).
(Yi):
(X2):
(Y2):

Wri te
Write
Write
Write

to
to
to
to

C8H
C9H.
CAH.
CBH.

For extTa flexibility, the switch inputs ~re also connected to the
inputs . of the ADC.
This means anothe,.. fou,.. analog channels are
~vailable to the user if the switches are not present.
(Although the
switch state can be read by converting the proper channel,
this
techni'lue takes much
longer than ,..eading the status latch.) The
conversion addresses for the switch input lines a,..e as follows:
I.'

Channel
Channel
Channel
Channel

4
5
0
7

(S,",4) : Write
Write
Write
WT'i te

(8W:3) :
(8'"'2) :
(8'"'1) :

to
to
to
to

CCH.
CDH.
CEH.
CFH.

The ADC is used for two different tvpes of conversion.
Channels O.
1,
2,
and 3 are used as current-sensing converters.
U25 converts a
current input level to a voltage output, which is fed to the inputs
of the ADC.
Channel s 4, 5, 0, and 7 are use d as straigh t va 1 tag e
inputs.
Therefore, the user has a choice of analog cUTrent inputs or
analog voltage inputs.
Host Joysticks are set up as currentcontrolling
devices.
Switches are both voltage- and currentcontroll ing devices.
2.13.3

Clock

The most complex section is that used to control the clock, Ul4.
Due
to speed limitations. this part must be set up in a series of steps.
The parameters used to set up the clock are stored in latch UlO.
U10
is located at 1/0 space DOH.
Data to be written to the clock is
stored in latch U1i.
U11 is located at liD space DBH.
The following
examples help explain the operations involved.
2. 13.3. 1 Op erat ion.
internal registers:
1.

To

write

data

to

anyone

of

the

clock's

Write the byte 1X to location DOH.
This raises
the HOLD
line and
leaves the rest of the control lines low.
The
bottom four bits of this control word contain the specific
add,..ess within the clock.
The clock set-up addresses are
given in Table 2-32.

Texas Instruments

2-118

Preliminary - '-'an 21,

1983

')

TECHNICAL REFERENCE

HARDWARE

Table 2-32

Address

Clock Set-Up Addresses

Reg i s t@r

10
12
13
14
15

51
S10
Mil
MilO
H1
Hl0

16
17
IS

W
01
010

19
xA
IS

Mol
1'1010
V1
V10

xi

IC

Meolning
Units o~ seconds
Tens o~ seconds
Units o~ Minutes
Tens o~ minu tes
Units o~ haul's
Tens o~ haul' s
d2=1 for PM, d2=O ~01' AM
d3=1 ~01' 24 hl' fOl'mat
d3=0 '01' 12 hr format
Week
.
Units of days
Tens o~ day s
d2=1 '01' 29 days in month 2
d2=O fo1' 28 days in month 2
Uni t s 0' man ths
Tens of mont h 5
Units of veal'S
Tens o~ Vea ... s

2.

W... it. the data fa ... the
1 ocat i on DSH.

data

regist .... s

in

the

clock

to

3.

T his i s t h.. MIN I MU M '01 1 1 owed setWait fol' a t I. 01 S t 150 us.
up time.
To ba safe,
wait fo ... 'rom 200 to 250 us (to
C01'.... ct any hidden timing p... oblems in the so~twa... e wait
loops).

4.

Wl'ite the' byte 3X
s.me as
that in
the address lines
WRITE line to the

5.

Wait fol' . t least 1 us (about twa inst1'uction cycles try
using
two NOPs (NO OPERATION - assembly language steps) in
the code after step 4).

6.

Write the byte 1X to location DOH.
This lowers the
line, but keeps all other lines in the same state.

to location DOH.
Note that this X is the
step 1.
This byte continues the st.te of
and the HOLD line,
while l'aising the
c 10 c k.

~ITE

7. Fa ... anothel' w1'ite, wait fol' 1 us
(2 NaPs),
lIIT'ite
1V to
location DOH (where V is the new address), lIIT'ite the new
data to port D8H, wait for 0.5 un (1 NOP cycle), and return
to step 4.
If this was the last write, go to step 8.
8.

Wl'ite the byte 00 to location DOH.

Texas Instruments

2-119

This

lowers

Prel iminaT'Y -

the

HOLD

.Jan 21.

1983

line and completes the
Once set,
the
tllli c e a VeaT'.
To adJust time

cv~le.

clock should not require resetting more than once
b~

OT'

30 seconds:

1. Write SOH to location DOH.
2.

Wa i t

foT' 32 ms.

3. WT'ite 00 to location DOH.
Refer to the MSMS832 data sheets for details on this feature.
To T'ead anV T'egisteT' on the clock:
1. WT'ite lX to location DOH.
This T'aises the HOLD line.
indicates the addT'ess to be T'ead.
RefeT' to Table 2-33.

X

2. Wait at le.st 150 us.
3. WT'ite 5X to location DOH.
This maintains the HOLD line.
and T'aises the READ line.
This is the same X as that in
I tep 1.

S. Raad fT'om location DBH.
The valid data is
fouT' bits of the bute T'etuT'ned.

in

the

bottom

6. To peT'foT'm anotheT' T'ead, pick the nelll addT'ess foT' X and go
to step 3.
If this lIIas the last T'ead. lIIT'ite 00 to location
DOH.
It can T'eadilv be leen that the T'ead is much easieT' than the IIIrite.
This is good. because a T'ead is peT"oT'med at least once during every
svstem poweT'-up.
2.13.3.2 BatteT'Y Backup.
The clock is a CMOS device and has battery
backup.
The CS input on the clock is connected to Vee.
The function
this pin is to put the clock into the powerdown mode.
When th~
pOllleT' supply voltage goes dOllln, the CS pin is gT'ounded. This forces
the clock into the pOllleT'down state, at which time it drallls pOlller from
the
batteT'Y BTL
This 3-V lithium batteT'Y is rated at 170
milliampeT'e-hourl CmAHL
At the 10111 current levels and the given
tvpical
svstem on-times. it should provide backup power for several
vears.
The battery is a GE 2320 or equivalent.
This battery
fits

0'

Texas Instruments

2-120

Preliminary - .Jan 21,

1983

TECHNICAL REFERENCE

HARDWARE

into a batte~~ holde~ on the clock and analog inte~~ace board
Replacement batta~ies o~ this type are avail.ble at many retail
electronics outlets.
The QE batte~y is UL listed.

NOTE
must
conditions
a~e
lIet.
Ca~e

fu~nished

be taken to ensure that the operating
by the battery manuracturer
Read and ~ollow the instructions
with the battery.
speci~i~d

The diode D1 is a law-voltage-drop diode used to isolate the battery
frail the system during power-up.
The circuit Gl-~ isolates the rest
o~
the sy s tam f~oll the battery d u~i n g per iod s o~ pOlalerd own.
Th is
set-up prevents the batte~~ from being back-biased du~ing powe~-up
and prevents it from trying to power the enti~. s~stem du~ing
pOlilerdoliln times.
The comparator changes state ~~om high output to low output when the
battery voltage d~ops below 2./:' V du~ing power-up.
The low batte~y
signal is latched into the status latch and should be checked
occasionall~
so that the operator can be flagged during low-batter~­
voltage ope~ation.
For the safety of factory pe~sonnel ilnd the end user.
the lithium
battery is not connected until afte~ the boa~d has been tested
sufficiently to .ssu~e that no defects exist in the battery switching
ci~cuit,.y.
Once the tests are completed,
a Jumpe~ is installed
connecting ES to E9.
This adds the batte~y to the ~est of the board,
and make. the board reildy for use.
2.

1~.4

Light Pen

The light pen section is by far the simplest, consisting only of a
single NOR gate and an inte~rupt latch.
When the tip of the pen is
depressed,
the signal TIPSIr goes 10111.
When the light detector in
the tip of the light pen is activated by the CRT beam,
the signal
HIT- goes 10111.
These signals a~e appl ied to the inputs of NOR gate
U4A.
The output of U4A is the INT signal.
This signal is active
onllj when the TIPSW- ilnd the HIT- signals aT'e bath active .
The
INT signal is positive-true.
The rising edge of INT is used to cloc k
a TRUE sign.l to the output of flip-';lop U17A.
This signal .
Before using the screen directly,
these programs should issue a Clear Screen function call to ensure that
the hardware is set up for direct access,
3.2.2.1

No program. IIIhile using the screen, directly,
should use the ROM
functions to put any data on the screen.
Undesirable hardware
functions can occur.
All operations on the CUrSor should use the ROM interface calls,
This
will ensure that possible redesigning of the cursor logic does not
prevent the program ~rom running.

Texas Instruments

3-2

PRELIMINARY-.)an 21.

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

3. ~.2. 2
Qraphics CRT.
The graphics screen is not supported by the
svstem ROMi therefore, all graphics screen runctions must go directly
to the hardware.
Note that this graphics screen size depends on the
setting of the 50-HzlbO-Hz Jum;:;er on the system board.
With the Jumper
set to bO Hz. the resolution is 720 x 300. when the Jumper is set to 5(0
Hz. the resolution is 720 x 350.
To simplify modification.
all routines that
hardware should be arranged in a modular fashion,
constants should be given symbolic names.

access the graphics
and hardware-specific

Texas Instruments will endeavor to keep future graphics hardware fully
compatible, or as a superset oil the cur1'ent ha1'dwa1'e.

3. 2.2. 3 Di sk Subs ystem.
The disk sub syst em is fu lly supp orte din th e
system ROM,
with the exception of the ability to FORMAT floppy disks.
For nor .... l operations, direct access, to any of the disk hardware should
not be necessarlJ.
Texas Instruments will supply q,ualified softldare
vendors with an obJect module that can be used to provide the rormat
functi on.

r

3.2.2.4 Keyboard Syste~
The keyboard system is fully
Suppo1'ted in
the system ROM.
Direct access to the keyboard interface should not benecessary for any normal operations.
Future keyboard
scan cades an,·
their translations will maintain such compatibility.
3.2.2.5 Interrupt Controller.
The interrupt controller system is use"
by. the system ROM but is nat supported in a fashion usable by softwarl'w1"ite1"s.
In futu1"e p1"aducts, Texas Instruments will attempt
to
kee,'
the same inte1"1"upt levels, usage, and hardware add1"esses f01" accessing
the device.
HOClfeve1", the constants used to access thi s hardware shaul d
be symbolic to facilitate modification.
3.2.2. b SIj.tem Time1"s and Speaker.
The system ROMs contain vecto1's to
alloCif inte1"ception oT the 25-ms time1"
interrupts by
other so~t~are.
The ext1"a 'timeT' can nat be set up and used because it is reserved ,,"or
use by Texas Instruments software products.
The speake1" 01" bell is ClfeI1-suppo1"ted by the system ROM and should
be accessed di1"ectly .

3. 2.2. 7
Pa1"a llel Pr inte1" Port.
i1ully Suppo1"ted in the s~stem Rct1.
nor .... 1 operations.

not

The parallel printer port system is
Direct access is available during

3.2.2.8
Se1"ial Communications.
The serial communications hardware is
not directly
supported
by
the system ROM.
To
ensure
~uture
compatibility.
Texas
Instruments does not
intend
to
change
this
hardware.
3.2.2. q Analog Inter~ace.
The analog inter-Pace adapter
is supported
by its ROM.
Direct access to the adapter interrace hardwa1'e shoula not
be necessary i10r normal operations.
Texas Instruments

3-3

PRELIMI NARY-Jan 21,

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

-.....,
;

3. 3

SYSTEM ROM INTERRUPT VECTOR USAQE

The system ROM uses s.ve~.l inte~~upt vecto~ locations in the fi~st 1
kbVte o~ memo~y.
These vecto~ locations a~e used fo~ ha~dware
inte~~uptsl
inte~Iaces
to the ROM f~nctionsl and ot~e~ usage .s given
in Tabla 3-1.
The vecta~s marked with an a5te~isk <*> a~e actually
used by the ROM.
The athe~ vecto~ locations cause a IIWIl.D" inte~~upt
il vecto~ed to, ilnd the usual displilY ... ill be 11** SYSTEM ERROR **
1042D •
Any of these vecta~s can be changed bV the disk operating
sy stem (DOS) a~ by ap pi ic. t ion 5 so ft",are.
Tab 1 e 3-1 gives vee to~ usag e
in te~ms o~ "inte~~upt type, n ... hich is :the numbe,. used
in iln INT
in.t~uetion.
The ae tual ab solute add~e5s o~ the ve cto~ can be
calculated bV multiply-ing the inte~~upt tvpe bV 4.
Fo~
example,
the
kevbo .. ~d p,.int sc~.en inte~~upt vecto~ (type 5EH) would be • doubl~
... o~d .. t 0: 017BH.
NOTE
The _"mbol .1104 11 denotes a hexadecimal value.

Texas

In5t~uments

3-4

PRELIMINARY-'-'an 21.

1983

TECHNICAL REFERENCE

Table 3-1

VECTOR
00
01
02*
03
04
05-1F
20-3F
40
41

42
43*
44

45
46*
47*
48*
49*

-

41\*

49*
4C

4D*
4E*

4F*
50*
51*
52*
53*

54*
55-56

57*
58*

59*
5A*
58*
5C*

5D*
5E*
5F*

DEVICE SERVICE ROUTINES

System Interrupt Vector Usage

DESCRIPTION

REFERENCE FOR DETAILS:

Divide-b~-zero trap
Single-step t~ap
Non-maskable interrupt

B089 documentation
9089 documentation
8088 documentation
B~eak (5ingle-b~te) 50~t~are interrupt 8088 documentation
Ove1'flo... t,.ap
8088 documentation
(Reserved b~ Intel)
8088 documentation
(Reserved boy Micr oso~ t .par MS-DOS)
MS-DOS documentation
8259 interrupt 0
8259 inter,.upt 1
8259 inter1'upt 2
8259 inter~upt 3 (Timer 1)
8259 inte,.rupt 4
8259 inter"upt 5
8259 inter1'upt 6 (Disk controller)
8259 inte1'1'upt 7 (Ke~board USART)
Speaker DSR inte~.pace
Subsec tion 3. 5
CRT DSR inte~face
Sub sec tion 3.7
Subsection 3.9
Ke~boa1'd DSR inte,.face
Parallel po,.t DSR interface
Sub sec tion 3. 10
Clack and analog interface board
Subsec tion 3.8
Disk DSR inte1'face
Time-of-day clock DSR inte,.face
Subsec tion 3. 1
System configuration call
Fatal software e~~or t~ap (**>
Restart timing event (. . )
Cancel timing event c**)
sve inte1'face subroutine C**)
Activate task sub~outine C**)
(Reserved for .putu~e use) (**)
Sub sec t ian 3. 7
CRT mapping vector
System timing, 25 ms (time slicing)
Subsection 3.3.2
Common interrupt exit vector (ROM)
Subsection 3.3.1·
Subsection 3.3.2
S~ stem timing, 100 ms (t i ming serv.)
Su b se c t i on 3. 11. 15
Keyboard mapping vettor
Subsection 3.11.15
Keyboard program pause key vector
Subsection 3.11.15
K.~board p,.ogram break ke~ vector
Su b se c t i an 3. 11. 15
Ke~board print screen vector
SUbsection 3.11.15
Keyboard ~u.ueing vecto~

* Vecto~ actually used by ROM.
** Texas Instruments only .
..._"
Texas Instruments

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PRELIMI "'ARY-,)an

2i

I

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

Table 3-1
VECTOR
60

S~stem

Inte~~upt ~ector

REFERENCE FOR DETAILS.

DESCRIPTION
System ROM
DS Pointer
(lSOH)
(F400: AOOO)
DS Si ze
(i82H)
Factorv ROM
OS Pointer
(184H)
(F400: 0000)
OS Si ze
(186H)
Option ROM
OS Pointer
(188H)
(F400: 2000)
OS Si ze
(18AH)
Option ROM
DS Pointer
(18CH)
( F 400: 4000)
DS S i z e
( 18EH)
Option ROM
DS Pointer
(190H)
(F400:6000)
DS Size
(192H)
Option ROM
DS Pointer
(194H)
(F400:8oo0)
DS Size
(196H)
Memorv size (in paragraphs)
Outstanding interrupt count
(in paragraphs)
Installed drive tvpes (bVte)
Extra svstem con9iguration
(con9ig. &&lord 1)
* Extra system con9iguration
(c on9ig. &IIord 2)

61
62
63
64
65
66

67

EO-E3*** (Reserved by Digital
Research for CPtM)
*
***
NOTE:

3.3.1

Usage (Continued)

Subsec tion
Subsection
Subsec tion
Subsection
Subsection
Sub sec tion
Subsection
Subsection
Subsec tion
Subsec tion
Su b sec tion
Subsec tion
Subsection

3.4
3.4
3.4
3.4
3.4
3.4
3.4
3.4
3. 4,
3.4 "
3.4
3.4
3.5.1

Subsec tion 3.5. 1
Subsection 3.5.1
Subsection 3.5.2
Subsection 3.5.2
CPtM documentation

Vector ac tu.lly used bV ROM.
CPtM is a trademark 09 Digital Research Incorporated.
The data segment CDS) pointers associated &&lith the system
interrupt vectors are explained in subsection 3.4,
"Svstem ROM Usage of RAM. II

Common Interrupt Exit·Vector

All interrupt service routines in the ROM and Texas Instruments
Applications programs u.. this common exit bV executing a long Jump
(LONG .JMP) to the rout i ne pointed to blJ thi 5
ve ctor.
Th i s ro utin e
restores
the stack and commonly used registers,
decrements the
outstanding interrupt counter, sends the EOI command to the interrupt
controller, and returns to the interrupted code &&lith an IRE~
Thi$
routine is normaliv in ROM, but a real-time ope~ating system (OS) can
patCh it 50 that all interrupt 5e~vice routines exit through the
operating system.
Since the interrupt st~ucture is complex
(due to
interaction betlileen the shared interrupts and the requirement for a
common exit point), the potential user should contact Texas Instruments
prior to installing an interrupt service routine.
Texas Instruments

3-6

PRELIMI NARY-Jan 21.

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DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

Since all interrupt service routines (ISR) have limited internai
stacks, no ISR is allowed to use more than ~our levels (8 bytes) of
stack.
Three levels are required b~ the interrupt itsel'. which pushes
th e CS, IP, an d Fl ags.
Th e ~o urth allowed level is us ed to push th E'
users OS. after which 95: SF is changed to an internal stack.
For this
reason, any limited-size stacks must always leave at least ~our levels
~ree (i~ interrupts are enabled> to accommodate a possible interrupt.
3.3.2

Timer Interrupts

The s'lstem timer IlticksU ever" 25 185.
The ISR for this timer is
located in the ROM, and it processes events such as disk motor timeouts and d.te/time-Iceeping.
At t'-lO points during this interrupt
service routine. solt'-lare interrupts are performed to allow the user to
access the timing services.
One interrupt occurs every count (ever~ 25
Ifts). and the other occurs every lour counts (100-ms intervals).
NorllWllly,
these interrupt vectors point to an IRET instruction in the
ROM.
The user can patch one or both of the vectors to point to his own
routines.
Thesa routines ilre Iree to use the AX,
BX,
OJ,
and ES
re 9 isters,
bu t th e" must pres el"ve iln" oth eor reg i s tel'S use d.
The stac k
used is the internal stack o~ the timer interrupt service routine and
it is .limit,ed in depth.
If the user does not l".-enable interl"upts (the
INT instruction disabled them), there are eight levels (16 b'Jtes) o~·
stack aVililable.
II the interrupts are re-enabled, the user has onlt)
lour levels (8 bytes) available.
I~ more stack size is req,uired. th!:'
user can switch to an internal sta,ck of the req,uired size (plus eight
bytes to .llow for higher pr~orit" interrupts).
It must be remembered that an" routines installed in this mannel" are
executing ilt the interrupt level, and interrupts must not be disabled
for an'J leng th of time.
An" unneces silr" time sp ent in these rou tine s
will directly
affect 5'Jstem efficiency.
Further,
the user must
comprehend the cilse in which some other mechanism (such as a timing
avant in the handler or "routine" in the operating system) has patched
the timing vactors and installed its own routines.
Instead o~ ending
the routine with an IRET instruction, a long Jump should be made to the
o~iginal vector add~ess (the o~iginal vecto~ must
be saved when the
user ~outine is install"d. )

3. 4

....-

SYSTEM ROM USAGE OF RAM

The two (8K) ROM sockets on the s~stem unit board are addressed at
absolute addresses FCOOOH (aptian) and FEOOOH (main).
Because tne ROM
code is linked such that its code segment is F400H, the ~irst location
of the s'Jstem ROM can be described
in segment:o~~set notation as
F400:AOOOH.
This code segment was chosen so that othel" ROMs can be
addressed with the same code segment as the s'Jstem ROM. and thus,
the I,!
can access the ROM routines as /\EAR instead of FAR.
This feature Uloul d
t~picall~ be used onl~ by an option ROM program that uses more than one
ROM.
It should not be used to access system ROM routines, since
possible version changes in the ROMs could cause incompatibilitu
Texas Instruments

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DEVICE SERVICE ROUTINES

p~oblems.

The ROM code defines a total o~ six possible ROM locations
an e-kbyte bounda~ie5, ...hich aT-e given in Table 3-2.
The last two ar~
the sldstem unit boa~d 50cketsi the otheT"s aT"e- on option boaT'ds
F'OT
example, the Wincheste~ disk cont~oller has its own ROM.
Table 3-2
ABSOLUTE
ADDRESS

CODE
SEQMENT

F4000H
F6000H
FBOOOH
FAOOOH
FCOOOH
FEOOOH

F400:0000H
F400:2000H
F400:4000H
F400:6000H
F400:8000H
F400: AOOOH

ROM Locations

COMMENTS
Reserved

fo~

factorv use

Option ROM socket on svstem unit boa~d
Svstem ROM s~cket on svstem unit board

Each ROM has • sepa~ate RAM data a~ea assi gned to it.
These data a~eas
"float" and ma" be accessed bid the ~ointe~s/sizes located in the
inte~~upt
vecto~
a~ea
(the fi~st 1 kbvtes of memory described
p~eviouslV >.
The~efo~e, the ROM does not need 41 dedicated area in RAM.
The data area can be moved bV copving a data area and updating the
pointe~.
The ROM neve~ sees the change, since each ROM accesses its
data a~ea5 acco~ding to the pointe,.s.
Because the pointe~s and data
a,.eas a,.e initialized at boot time bV the ROM5 them5elves, in a base
."ste", ani" the .vste", ROM data area pointe~ is used.
Most application
p~og~ams do not ,.equire this info~mation, ... hich is
prima,.ilv used by
the
ope~ating
svstem.
Contact Texas Instruments fo~ additional
info~mation if \IOU need to use a ROM or move the ROMs' data areas.
In the cu,.rent implementation, the svstem ROM data a~ea is about 400
bvtes located at 40:0000H.
This is moved at MS-DOS boot time to its
final location at 120:0000H.

SYSTEM CONFIQURATION FUNCTION CALLS

3. 5

This SUbsection d.sc~ibes the system configu~ation function
The,.e a~e t ...o .epa~ate tvpes of con~igu~ation in~o~mation.

calls.

The

first t"pe is .asily accessed and ,.eturns most of the in~ormation
for ",ost appl ications programs.
The second type is addit iona 1
info~mation usable fo~ svstems p~ogra",s and routines.
The~e
.re two
methods for accessing each type of information.
~equi~ed

*

Function calls that

*

Function cal15 that ~etu~n the add~ess of the information.
This method is intended for use at the system level for
changing the configuration of devices set by soft ...are.

Texas

Inst~uments

-;

retu~n

the

in~ormation

3-8

in a ,.egister.

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1983

"\

DEVICE SERVICE ROUTINES

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~~

3.5. 1

S~stem Configu~~tion

This 'unction
sv_tem options.
Upon

Function

is used to dete~mine the installation status of certain
It is invoked by executing an INT 4FH instTuction.

BX contains the size of contiguous RAM (starting
in pa~agTaphs (16-byte blocks).
A 128-icbyt~ syst~m, f:or
example. would ~etu~n 2000H in BX.

~t

~etu~n,

~egiste~

OOOOOH)

AX contains the svstem configu~ation wOTd. which reflects
installation status of va~ious system options.
The bits o~ the
a~e defined as given in Table 3-3.
Regist.~

Table 3-3

ill
01

2
3

4
5
6

1
r~

e
9

10
11

.12
13

14
15

*
is

3.5.2

the
WOT!:

System Configuration Word-Bit Definition
DEFINITI(J\f

Diskette d~ive 0 (inte~nal) installed
Diskette d~ive 1 (inte~nal) installed
Diskette d~ive 2 (exteTnal) installed
Diskette d~ive 3 (ext.~nal) installed
E1-£2 Jumper 
£3-E4 Jumper (indicates Drive A has 96 tpi)
E5-£6 Jumper Cindicates a 50-Hz s~stem)
Wincheste~ disk cont~olle~ installed
Serial Port 1 installed
Se~ial Po~t 2 installed
Se~ial Po~t 3 installed
Se~ial Po~t 4 installed
Qraphics RAM bank A installed
Qraphics RAM bank B installed
Qraphics RAM bank C installed
Clock/analog board installed

Bit 0 is the least-significant bit, and a statement
t~ue if its co~~esponding bit is a 1.

Extra System

Configu~ation

Function

This function is used to determine the installation status of system
'options not covered in the standa~d system con'iguration call.
Whereas
the standard svstem con'iguration call returns a word containing the
information necessar" for most applications,
the
extra
sl,Istem
configuration function is used primarily for systems pTogTamming
ap p lications.
The extra system configuration function is invoked by placing ~ OBH in
register AH and executing an INTerrupt 48H.
Upon return, register AL
contains the d~ive ~pe b.,te (AH is unde'ined>.
BX contai-ns extra
system canfigu~ation word 1, and CX contains extra system configuration
Texas Instruments

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1983

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TECHNICAL REFERENCE

wo~d 2.
Table 3-4.

The bit5 of extra s~stem configuration wo~d 1 are defined in
Table 3-4

Extra

BIT

S~stem

Con~iguration

~

Word 1 

Cop~ocesso~

is installed

RESERVED

I

8
9

10

11

>

12
13
14
15

*

RESERVED

I

,
)

Bit 0 is the least-signi~icant bit, and a .tatement
is t~ue i~ its corresponding bit is a 1.

Word 2 (in eX) is
ex pan5 ion.

currently

unde~ined#

but

i.

reserved

'or

later

•

•

Texas Instruments

3-10

PRELIMINARY-~an

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1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

The d~ive-t~pe byte de~ines the types of the installed diskette drives
This in"ormation,
combined with the "installed drive ll vector in the
standard system configuration word, yields complete i~~ormation about
th e drives in the sys tem.
At pOllle~-u p, the drive A d efin i ti on Jumper s
(El - E2 and E3 - E4) are read,
This in~o~mation is returned as a twobit value.
Register AL contail's the two-b it con~iguration code ;01" all
"our o~ the diskette d~ives,
The drive byte (in AL) looks like this:

+-----+-----+-----+-----+-----+-----+-----+-----+
7654321
0

+--------+---"------+--------+--------+
D~ive

D

D~ive

C

+----------+---------+-----------+-----------+
Each tlilo-bit

o

o

1
1

o

o

r

~ield

1

1

is defined as
Sing 1 e-s i d ed
Doub 1 e-si ded
Sing 1 e-s i d ed
Doub 1 e-si ded

~ollollls:

40 trac k
40 t~ac k
80 trac k
SO t~ac k

Th e op e~at ing 5IJstem uses th i s d~ i ve byte to p ~operly fo~mat. cop y, an '.:
use diskette 'iles.
It is possible to mix d~ive t~pes
in one systen,
('o~
example,
one single-sided and one double-sided drive) by settinj
the d~ive-type bllte lIIith the pertinent info~lI.tion; but,
this is NO "1
recommended.
I'tiled-d~ive type slJstems are con'using to ..,o~k with, an~i
us.~s 'r.~uently find the w~ong diskettes
insert.d,
often lIIith
dat.~
lost.

3.5.3

Get

Pointe~

to System Con'iguration

This 4Iunction is invoked by placing a 09H in' register AH and executing
an INTerrupt 48H.
On return, ES contains the segment, and ax
contair,~'
the offset of the standard system configuration lIIord (herea;ter, the
notation for this is ES:BXL
This 'unction is intended to be
used by
system
soft..,a~e,
IIIhich has a need to change the configuration
information.
Although an application
prog~am
may
access
the
info~mation in this manner, the con~iguration must not be changed.

Texas Instruments

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1983

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3.5.4

DEVICE SERVICE ROUTINES

Get Pointer to Extra Svstem Configuration

This function is invoked bU placing a OAH in ~egi5te~ AH and executing
an INTerrupt 4SH.
On return,
ES: BX p Dints to the ext~a system
configuration information, formatted as rollows:
ES: [BX-3J-Cword)
ES:[BX+OJ-CbVte)
ES: [BX+1J-(word)
ES: [BX+3J-(word)

Size of memorv in 16 byte-blocks
Drive-tvpe byte
Extra system configu~ation word 1
Extra system configu~ation word 2

This function is intended to be used by system software that has a need
to change the configuration information.
Although the an applicatiDn
program can access the information in this manner.
the configuT'ation
must not be changed.

3. 6

GENERAL-PURPOSE ROM FUNCTIONS

The following
paragT'aphs describe the use of some
functions, summarize the ROM interface interrupts,
and
usage of RAM.
3.6.1

general-pu~pose

explain

ROM's

Del a..,

This function causes a delav, in milliseconds, of the value placed in
register CX.
To invoke the function. place the delal:! value in CS.
05H
in AH.
and execute an INT 48H.
The delay is onllJ approximate and may
be used wheT'ever a rough softwaT'e delau is T'equiT'ed.
All registe~s
except CX are preserved.
3.6.2

CRC Calculation

This function calculates the cvclic redundanc.., check (CRC-16) value for
a
specified block of memorv_
It is invoked bV placing the address of
the memor" block in ES:BX. the size Or the block in BP. and the value
06H in AH. then executing an INT 48H.
On return. OX contains the CRe
value; if DX-OOOO. the Z-flag 'is set.
For memoT'Y
blocks that folloUJ
the convention of the CRC being the
last word in the block. this
routine allows easy CRC checking.
First. the CRC' of the memory bloc i<
is calculated. with the size of the block set to 2 less th4ln the actual
size.
The CRC ... o~d
is then written to the last word of the block,
Subsequently. the CRC of this block may be checked by calling
this
function with the actual size of the memory block (including the
previously c4llculated CRC>'
BV definition,
the CRC result of this
block
is
zero (if the CRC matches the data> and the Z-flag is set;
otherwise, the CRC fails and the Z-flag is reset.
All registers a~e
used except DI, S1. and OS (ES remains unchanged. )

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(-

3. 6.3

P~int

ROM Message

This ~unction is used to display a ROM CS-relative message.
It i ;
invoked by placing the o~~set o~ the zero-te~minated message in SI, 07H
• in AH, and executing an INT 48H.
This ~unction is used by the option
ROMs,
since all
the ROMs share a common CS.
It is not a genera1purpos e routine.
3.6.4

Display System Error Code

This 'unction is used to display a system error in the standard ;ormat

It is invok.d by placing the
mess.g. above>
in
executing an INT 4SH.
displa~.d

3. 7

r

e~,.o~

ax,

cod e
placing

xxxx value in the
value OSH in AH, and

SPEAKER DEVICE SERVICE ROUTINE

This subsection describes the speake,. device service routine (DSR)
anci
the 'unctions it p~ovides to the sfjstem o~ application p~og,.ams tha'!
use it.
The ~unctions ar.:

•
•
•
•
•

Sound the sp •• ke,.
Qet spe. ke,. status
Set spea ke,. fr.quency
Speake,. ON
Spea k e~ OFF

The speake~ DSR 'unctions a,.e located in the system ROM and are
accessed
th~ough
the software inte~~upt mechanism o~ the 8088
mic~oprocesso,..
The desi~.d ~unct·ion is chos.n by placing an opcode in
regist.~ AH and executing an INT 4BH instruction.
All r.gisters a~e
prese,.ved except AX.
3.7.1

Sound the

Spe.ke~

- AH • 0

This ~unction turns the sp.ake~ on .

3.7.4

Speaker ON

AH •

3

This .f!unction is used to enable the speaker (turn on the sound>.
The
speaker remains on until it is turned off bV either (1) the Speaker OFF
(AH=4) function or (2) by the ROM timing routine. as a result of either
the Sound the Speaker (AH=O) function or a normal sustem beep.

3.7.5

Speaker OFF

AH •

4

This function performs the reverse o.f! the speaker ON (AH=3> function by
disabling the speaker (turning off the sound).

3. 8

TlME-OF-DAY CLOCK DSR

This subsection describes the time-of-da" clock DSR and the functions
it provides to the sIJstem ·01' application programs that use it.
The
functions are:
(1) set the date.
(2) set the time.
and (3) get the
date and time.
The clock DSR consists of routines to set and read the time of day and
date information kept b" the timing services of the svstem ROM.
At
po~er-up.
the time is set to 00:00:00.00, and the date is set to 0000.
These can be reset by sljstem or user programs.
Once set with a valio
time, the clock keeps the correct time with a 1/10-sec resolution.
The
time is kept in 24-hr format and the date is simply a cumulative count
of days since the clock was started.
As a matter of convenience (for
MS-DOS).
the date is specified as the number of days since .January L
1980.
For example, the date value for September 10. 1982, is 983.
The three clock functions are located in the system
accessed
through
the software interrupt mechanism
Texas Instruments

3-14

"

ROM
of

and are
the 8088

PRELIMI NARY-.Jan 21,

198J

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

r

micl'opl'ocessol'.
The desil'ed f!unction is chosen by placing an opcode in
registel' AH and executing an INT 4EH inst1'uction.
All 1'egiste1's al'e
preserved except AX and any other registe1's in which inTormation 15
returned.
3. 9. 1

Set the Date

AH

=0

This function sets the date to the value in the BX registel'.
The date
is simply a count of days since the clock was started.
The count is
incl'emented ~h.n the hou,.. 1'0115 over Tram 23 to 00.
3.9.2

Set the Ti.e

AH = 1

This function sets the time as follows:
CH
CL
DH
DL

• Haul'S (00 - 23)
• Minutes (00
59)
• Seconds COO
59)
= Hund ... edths of seconds (00 - 99)

It is the use1' 's l'esponsib ility to mak.e SU1'e the values passed art"
the ranges specified.
These values al'e not range checked and
may be set to ,.epl'esent a meaningless time.
The time eventually counts
into the no~mal •• ,uence, howeve,...
~ithin

AH

=2

This function retu ... ns the cU"'1'ent date in l'egiste1' AX and the
time in ,.egistel's CX/DX in the fOl'mats desc,..ibed p1'eviously.

cu,.. ... ent

-.
Texas Instl'uments

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3.9

DEVICE SERVICE ROUTINES

CRT DSR

This sUbsection describes the CRT DSR and the functions it provides to
the s~stem or application programs that use it.
The maJor function~
are (1) videa made control, and (2) character handling.
The CRT DSR functions are located in the system ROM and are accessed
through the use of the BOSS software interrupt mechanism (essentially
an address-independent subroutine callL
The typical user of this DSR
would be the OS-dependent BIOS, which resides an a particular OS disk
and is loaded into RAM during disk boot.
The desired function is
chosen by placing an opcode in register AH.
The CRT opcodes and
functiorts are given iri Table 3-5.
Various CRT functions re~uire
parameters to be passed in specific registers in addition to AH.
Once
register AH and the parameter registers are set up, the user can
execute an INT 49H and the specified function is performed.
During
this interrupt, all registers are preserved except AX, CX, and DX.
Table 3-5
OPCODE
OOH

01H
021-4
03H
O~

OSH
061-1
07H
OSH
09H
OAH

OBH
OCH
ODH

OEH
OFH

lOH
l1H
12H
131-4
1~

1SH
161-1
17H
1BH

CRT DSR Opcode. and Functions

FUNCTION
(Null function)
Set cursor tvpe
Set cursor position
Read cursor position
(Null function)
(Null function)
Scroll text black
Scroll text black
Read character and attribute at current cursor position
Write character and attribute at current cursor position
Write character only at current cursor position
(Null function)
(Null function)
(Null function)
Write ASCII teletype
(Null function)
Writ. block of ctoaracters at current cursor with attribute
Write block of characters only at current cursor
Set entire screen to specified attribute(s)
Clear text screen and home the cursor
Clear graphics screen
Set TTY status line beginning
Set attribute latch to specified attribute(s)
Read physical display begin pointer
Print TTY string

Texas Instruments

3-16

PRELIMI NARY-Jan 21.

1983

TECHNICAL REFERENCE

3. 9. 1

DEVICE SERVICE ROUTINES

Set Cursor Tvpe - AH

= 01H

This ~unction allows an application to define the starting and ending
scan line for the cursor and its characteristics (either blinking or no
cursor),
Required input for this tlunction is described in Figure 3-1.

+-------------------------------+
+-------------------------------+

CH • I 7 I 0 I 5 : 4 I 3 : 2 I 1 I 0 :
not usad<-+

+---) bits 4 through

B~te

1

o start

scan line of cur sor

+---+----) bits 6 and 5 indicate the cursor type:
00
no b I ink
01
no cursor
~ast blink
10
sIalY blink
11

=
=
=
=

+--~-----------+

CL •

r
./

I 7 I 0 I 5 I 4 I 3 I 2 I 1 I 0 I

+-------------------+

B~t.

2

+---) bits 4 through 0 and scan line of

curso~

+--+---+------) bits 7 through 5 nat used

(Valid values for scan line are 0 through
Figure 3-1

Taxas Instruments

B~te

O.~inition

3-17

- Set Cursor

~1

decimal)

T~pe

PRELIMINARY-~an

21.

i983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

3.9.2

Set Cursor Position - AH

= 02H
NOTE

The user should be aware that screen cDordinates
are based upon the 0,0 coordinate being located at
the upper left-hand carner of the display.
All
routines that r.~uire a coordinate parameter U5e
this convention.
The screenlilill look to the user
as if he were lIIorking lIIith the absolute value of
fourth ~uadrant coordinates of • two-dimensional
coordinate system.
This function causes the cursor (of the current tvpe) to be set at the
specified x,y (column/raw) coordinate of the display.
Re~uired

3.9.3

input for this function is as follollls:

DH

=X

DL

s

(columns) coordinate  routine.
Output from the Read Cursor Position routine is as fallows:
DH,

DL. x.

V (column/row) location of the cursor

CH, CL. current cursor type (see paragraph 3.9. 1.
ASet Cursor Type - AH=OlH" for values)

Texas Instruments

3-i8

PRELIMI NARY-~an 21.

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

3. q 4

Sc~oll

Text Block - AH = 06H and 07H

The ROM contains only ·one gene~t11 pu~pose "scroll" routine. which
handles both upward and downwa~d sc~olls.
When the destination
coordinates a~e less than the source coo-rdinates, the sc~oll is up and
to the le~t; when the destination coordinates are g~eatar than the
source coordinates. the sc·~oll is down and to the right.
The sc~olling function$ allow an application program to spaci~1j a block
of text and cause it to be moved or copied to another location on the
sc~een.
Speci41ving a scroll with blanking causes the sou~ce text to be
blanked as it is moved.
The user should note that during this process
the source charl1ct.~ is read to II temporarv register lind its location
is blanked.
Then th e c hara cter is rewri t ten to its de sti nati on
location.
This provides 'o~ a nondestructive move in the event that
the source and destinl1tion locations are the same and blanking is
specified.
This implementation comes from the idea that in scrolling
the user is concerned with the end result, IIIhich is that the data being
moved or copied is preserved in its destination location.
Re~uired
input 'or this 'unction is liS 'allows:

AL
o (Slank out source text) This would be a move block.
AL .. >0 (Don/t blank source text) This would be a copv block.
:III

(DH,DL) .. Source begin column/row location
(SH.BL) - Destination begin

column/~ow

location

CH = Column length of block (Valid values are 1 through 80 decima,
CL = Line length of block (Valid values are 1 through 25 decimal)

The source text block boundaries in (x,y) coordinates are as follollls:
Upper
Upper
Lower
Lower

le,t
ri ght
left
right

Texas Instruments

..
..

(DH,DL)
CH • DL)
CDH, DL + CL)
CDH + CH , Dl. + CL)

('DH +

PRELIMINARY-Jan 21,

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

The following items further d~scribe the scrolling routines and explain
the sequence of operation.

*

The smallest logical block of text is considered to be a
sentence.
Therefore, with this scrolling capabilit~, the user
could specif!y a block to be a sentence.
This malJ (or mal:J not)
wrap to a new line and "unwrap" as it is moved (or copied) to
its destination (that is, the column length parameter would
bypass line boundaries and pick up characters f!rom the next
line>.
The user should note that this is quite ef!f!ective when
the line length is equal to 1 but might cause unwanted block
movement ~hen the line length is greater than 1.

* Boundary checking for the scrolling

routine is done on a
ch.racter basis as the characters are being moved.
When a
scroll down is in progress.
the SC1'oll copies the last
character in the source block to the last character position
in the destination block. The p1'ocessing is backllh1rds through
the blocks ~hil. checking cha1'acter positions for out-of-bound
cha1'acters.
This means that in the scroll-down action,
no
scroll takes place if any destination position lies beyond the
end of the screen.
As"mmetr icall", ~hen a scroll up is in
p1'ogress. the scroll copies the first cha1'acter in the source
block to the fi1'st cha1'acte1' position in the destination
block.
The scroll proceeds for~ard, through the blocks. while
checking character positions for out-of-bound characters.
In
the scroll-up action, the scroll takes place until it reaches
a source character position that lies beyond the end of the
5 cre en.

*

When scrolling ~ith blanking is requested blJ the user, the
state of the attribute latch is preserved ~ith the same state
as on entr".
The attributes of the chaT'acter follow the
characteT' a. it is moved on the se1'een. and the blanked araa
is
~itten
~ith
the def!ault attT'ibutes (th.t is,
high
intensity for monochrome monitoT'.
and ~hite
faT'
coloT'
moni tar).

*

When scrolling without blanking is requested blJ the useT', the
state of the attribute latch is set to the attT'ibute of the
last cha1'acter that was .cT'olled (that is, the .ttribute of!
the first cha1'acter of the SOU1'ce black if st1'olling dawn,
or
the .tt1'ibute of the last character of the source block if!
s C1' 0 lli n 9 up >.

Texas Instruments

3-20

PRELIMINARY-Jan 2L

1983

~

TECHNICAL REFERENCE

3.9.5

Read

DEVICE SERVICE ROUTINES

Cha~acte~/Att~ibute

at

Cu~sor

Position - AH

= OSH

Thi. function retu~n. a cha~acte~ and its associated att~ibute from the
cur~ent cursor position on
the screen as follows.
See (paragraph
3.9.9.7) "Set Attribute
AH = 1.!aH".
for a description of th€c'
att~ibutes suppo~ted, and attribute values.
AH • Attribute value

NOTE
The att~ibute latch is left set
that is ~.tu~ned.

3.9.6

to

the

attribute

Write Character/Attribute at Cursor Position - AH - 09H

Thi.

function enables the lII~iting of· • cha~acte~ lIIith the give~,
at the cur~ent cu~.o~ position.
(The attribute latch is left
•• t to the attribute .pecified in ~egi.te~ BL.) The u.e~ can spec ify ic'
count and cause the characte~ to be lII~itten a given number of time,
starting at the cur.o~'s cu~"ent position.
This function does nat
increment the cursor automaticallv, and the cu,..sor ,..emains at it~.
cu,..,.ent position _hila the cha,.acte~s a,.. written in succession fro~k
that location.
If an application uses this method of
writing
characte,..s,
it is assumed that the application is a~so handling Cursal'
positioning and, thus, no cursor movement is implemented.
The user
sh oul d no te that c ont,..ol characters (CR, LF, etc.) ar e no t ex ecut ed as
such when using this function and thei~ s~mbols are printed an the
display.
The r.q,uired input for this function is as follollls:

att~ibute

AL • Character to write
BL •

ex

Att,.ibute of cha,..acte~(s)
(See pa,..agraph 19.9.7 "Set

= Numb.~

Texas Instruments

of times to

w~ite

Att~ibute

-

AH=16H")

it

3-21

PRELIMI NARY-.)an 21.

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

3.9.7

Write Character at Cursor Position - AH

= OAH

This ~unctian is similar to the preceeding ~unction except that the
character being written takes on the attributes o~ the attribute latch
wh ich is left over from the last CR,T call.
See paragraph 3.9.6, "Write
Character/Attribute at Cursor Position
AH=09H" for the function
behavior
The re~uired input ~or this function is as follo~s:

CX

3.9.8

= Number

Write ASCII

of times to write it

Telet~pe

- AH

&

OEH

This function allows for TTY output to the screen from application
programs.
Writing begins at the current cursor position. and the
cursor is advanced automatically to its next position on the screen
(See CRT TTY Mode Behavior, paragraph 3.9.9.10. for further details>.
The screen is scrolled automatically if need be (that is. ~riting past
the end o~ the screen). and the control characters CR. LF, BS, and BEL
are executed instead of written.
(NOTE:
If .. status region is
currently being implemented, a scroll occurs on the line previous to
the start of the status region as if that line were the end o~ the
screen.)
The characters IIIritten lIIith this ~unction lIIi!1 take on the
attributes of the previously IIIritten character,
since the attribute
latch contents remain unchanged.
The re~uired input for this function
is as follows:
AL

3.9.9

= Character

to IIIrite

Additional Functions

The following is a set o~ "extra" functions. which have
to give the user added screen liD capability.

Texas Instruments

3-22

been

provided

PRELIMINARY-'-'an 21.

1983

'\

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

3.9.9.1
Write Block of Chal'actel's at Cursor With Attribute - AH =
10H. This function allows the user the ability to ufrite a
given block
of data to the screen starting at the current cursor position.
This
abilit~ will allow for
less screen I/O overhead in the event an
application program has a "known" contiguous block of data that is to
be lII1'itten to the SCl'een.
"J.(.nol,Un" is taken to mean the block is in a
given contiguous area ot: memory with a given length.
As with the
Wl' i te/ChaT'acter AttT'i b ute at C Ul'SOl' P 05i t i on (AH=09H) f unc t ion.
th e
cut"sot" is not automatically incremented.
The t".q,uired input for this
function i. as follows:

AL

.

AttT'ibute(s) of chal'actet"s
(S •• paragraph 3.9. 9.7. "Set AttT'ibute (AH=l hH)
function fol' valu •• >*

DX

= Segment

BX

•

CX

-

II

location of characteT' bloc k

Offset location of chaT'acter block
Block length **

3.9.9.2 WT'ite Block of Charactet"s Onl~ at CUrSOT' Position- AH = 11H.
This function is similaT' to the preceeding fun~tion except that tho
attT'ibute paT'ameter is nat specified.
The characters take on thl
,attT'ibuta'.) of the att,.ibute latch left avet" ft"om the last CRT call
- . The req,ui,..d input fo,. this function,
!&lith the exception of theattT'ibute (Al, :. Don't care) parameteT'. is as follows:

r-

AL. Attribute(s) of chal'actel's (See paT'agT'aph 3.9.9.7,
"Set Attribute (AH=16H)" function for values)*
DX = Segment location of characteT' block
BX • Offset location of chal'acter block

ex • Block length **
*

**

The attT'ibute(s) specified is in effect fol' the
enti,.e block and the attT'ibute latch is left set
to the attribute specified in registeT' AL
This routine "clips" any charaeteT's that do not
fit on the screen C i. e., charae tel's are lII1'i tten
until the end of screen is reached and all other
characters are lost/not lII1'i tten).
In
order nat to lase charactel's, the user should make
SUl'. that the CUl'sar is located in a position such
that the numbeT' of character positions from the
C:UT'SOT' to the end of screen is gl'eater than OT' e'tua 1
to the block length.

Texas Instruments

3-23

PRELIMINARY-~an

21,

1983

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

3.9.9.3
Change Screen AttributeCs) - AH = 12H.
This function allows
the user to specify attribute(s} that affect all of the characters on
the .display.
This routine does not change .the position of any
characters on the screen.
Examples are to blink the entire screen or
reverse video the entire sc"een.
The required input for this function
is as follows:
AL - Attribute(s) to use
(See paragraph 3.9.9.7,
"Set Att,.ibute (AH=16H)" function)
NOTE: The attribute latch is set to the attribute specified
in register AL on ex it.
3.9.9.4 Cle.,. Text Screen and Home the Cu~sor
AH = 13H.
This
routirie allo..,s the user to clear the text screen and home the cursor
(that is, send the cursor to 0,0 coordinates>.
This function "erases"
anu data contained in the status region but leaves the status region
implementation in effect.
The required input for this function is as follows:
No input required other than AH - 13H (function number)
3.9.9.5 Cle.r OT-aphics Screen (s) - AH • 14H.
This function al10llls the
user to cle.r the graphics screen.
Required input for this function is
as fo 11 ows :

'\

No input ,.equired other than AH • 14H (function number)
3.9.9.6 Set TTY Status Region Beginning - AH 1SH.
This function
allows the user to specify the beginning line on the screen, which is
to be considered as the status region.
This is useful in defining a
st.tus reg ion of one or more 1 ine s.
Thi s reg ion rema ins in e ffec t
until it is clear.d or reset.
During TTY writes and subsequent
sc,.olls,
this .r.a remains intact and everything above this line
scrolls as nec·essa,.".
In order to write to this area, the user should
r •• d .nd save the current cursor position, locate the cursor within the
status region,
use one of the ..,rite character functions (not the TTY
lIJ1'ite) , and then restore the cursor to its origin.l position.
Required
input for this function is as follows:
CH • 0 (must alw."s be zero)
CL - St.rt line of status ,.egion (Valid values are 0 through 24)
A value of zero (0) for the start line will reset
the status region implementation.

*

If an attempt is made to set a status region b.ginning line
that does not occur ilfter the current line of the cursor, no
status line is implemented.
The text from the start line
(specif~ed in CL) to the end o~ the screen is considered to be
the status region.

Texas Instruments

3-24

PRELIMINARY-Jan 21,

1983

*

DEVICE SERVICE ROUTINES

TECHNICAL REFEHENCE

3.9.9.7 Set Att,.ibute(s) - AH = 16H.
This function allow. the user an
alte,.nate method with which to control the following att,.ibute(s) .
•

*
*

*
*

Intensity levels 1.' 2. and 3 (Blue. Red. and Go""een)
Cha,.act.,. enable/disable

Unde,.line
Blink

This function sets the att,.ibut. latch with the specified att,.ibute(s)
and subsequent cha,.act.,.s .,.itten to the sc,.een take
an
this
att,.ibute(s>'
Note that th.is function. in combination with a W,.ite
Cha,.act.,. Ceithe,. block a,. single> at CU,.so,. Position (AH=OAH) function
has the same effect as the W'rite Cha,.acte,./Att,.ibute (eithe,. black or
single) at CU1"'01" Position (AH=09H) function.
Nate also that the
att,.ibute latch 'remains set to the att,.ibute specified in ,.egister BL.

r

3-25

PRELIMINARY-~an

21. 1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

The required input for this 9unction is shown in Figure 3-2.

BL • Attribute(s)

~o

set

CBl is used in order to distinguish to the user
the difference between this lunction and the
Change Screen Attriblltes (AH=l2H) function)
7654321 0
I
I
I
I
I
I
I
I
_'_'_1_1_'_1_1_'

•• ••

level 1 (Blue)
level 2 (Red)
+-----> Intensitv level 3 (Oreen)
+-------) Character enable
(2nd dominant)
+---------) Reverse video
(1st dominant) *
+-----------) Underline
+---------) Blink
+---------~---) Alternate character set
I I +-)
I +---)

*

Intensit~
Intensit~

*

The user should realize that although more than one attribute
can be specified,
certain combinations do not make sense
(i.e .• if Character Enable Attribute is set to a zero.
then
the character will not appear nOr will an~ of the other
attributes except for reverse video).
In this manner, for
example.
the user could have a reversed video, underlined.
blinking. red character.
Also,
b" mlxlng the intensit"
(color) bits the user can get various levels of intensitv (or
colors) lor a given character.
Figure 3-2

Texas Instruments

Byte definition - Set Attributes

3-26

PRELIMI NARY-~an 21.

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

('

3.9.9.8 Qet Phvsical Displa~
Begin PointeT'
AH =- 17H.
This
function is used to return the phvsical display-begin pointeT' to an
application.
Logicaillj' tne d isplalj-begin is always at 0,0, but there
is a physical addT'ess (o~~set) associated with the beginning of the
display that changes from time to time as the screen is scrolled.
clear.d,
or otherwise changed.
This routine returns that of~set
addr.ss relative to the CRT memorv area whose segment address is DEOOH.
Th. screen memory is a ~OOO-byte contiguous black of RAM.
Once the
staT'ting location of this block is known to the application. any
chaT'acter an the sc,. •• n can b. accessed.
For example,
the last
c ha,.ac teT' an the sc r •• n is 1 oca ted at (DEOOH:
d isp lav- beg in +2000)
and the 80th chaT'acte", an the sc.ree·n (top lina. last characteT' on the
line>is located at CDEOOH:displav-begin + 80),
This retuT'ns the
displav bagin point.r as fallows:

Exampla:

DX. 0 implies that the first characta,. an the
displalj residas in memory location DEOO:OOOOH
DX • 150H implies that the first character on the
display resides in memory location DEOO:015OH

Print TTY St,.ing - AH =- 18H.
This function allows the user to
have a contiguous st'ring of characta,.s, of a given length, located in a
-' co de s egmant to be p,.i nted in a TTV-fa shi on s t.,.t ing at th. c UT'ren t
cu,.sor position.
As with the wT'ite TTV function, this routine executes
the cont,.ol cha,.act.,.s CR, LF, BS, and BEL and scrolls the scr •• n i~
necassaT'y.
Requi,...d input fa,. this function is as follows:
3.9.9.9

r

WheT'e:

*

(IX) byte 0
(IX) byte 1

= length

= first

01 the string
characte,.. 01 the string

The use,.'s code segment addT'ess is obtained from the stack
and theT'.fora doe. nat ne.d to be passed as a paT'ameter.

Texas Instruments

3-27

PRELIMI NARY-,-",an 21.

1983

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

3. q. q. 10 CRT TTY, Mode Behavior.
The ~oll owing
of the behavior of the CRT when used in the
behavior when being used in "mixed" modes.
The
information carefullv,
especiallv if the user
with TTY functions.

is a brie-r descri ptiOT
TTY mode as well as its
user should read
this
mixes non-TTY functions

Internallv, the CRT DSR implements a "phantom" 81st column on each line
which in realit.., is the first column of the following
line.
This
"phantom"
column occurs when a cha,.acter is w,.itten in the 80th column
of the cu,.rent line with a TTY blT"ite.
At this point,
if a carriage
return «CR» command is issued, the cursor moves ,,.om the 81st column
of the current line back to the fi,.&t column o~ the current line.
However,
if the cursor is in the 81st column and the user reads the
cu,.sor position, it is returned as (current line plus 1 line and column
0), not (cur,.ent line and column 81"
The user must be aw.re of this
if he is attempting to ,.esto,.e a cursor position which logicall.., came
from the 81st column.
At this point the TTY mode is distu,.bed and the
cu,.sor will be resto,.ed logicall.., to the first column of the next (a
logicallv new) line.
The "Set CU,.so,. Position (AH=02H)" function has
no concept of an 81st column.
Although the first column position has
anI.., one physical location, it can be inte,.p,.eted as two di~ferent
logical locations, depending on the current CRT action (modeL
3.9.9.11
Custom Encoding of the CRT.
The user may ..,ish to do same
custom encoding of the cha,.act.,.. being displaved to the CRT.
For this
reason,
a CRT "mapping" capability has been provided to
allow
applications to intercept cha,..cte,.s and CRT actions (if need be) and
to encode them as desi,.ed.

Texas Instruments

3-28

PRELIM! NARY-~an 21.

1983

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

Upon .nt... " to the CRT DSR a so.ptware interrupt is eXIHuted,
t'lpically
used to re-m .. p characters to the screen,
wh ich points to an IRET
inst... uction.
An application program can reprogram this vector to
int.,.cept c .. lls to the CRT DSR, tnereblj "taking ave ..... the CRT.
This
cap .. bilitV typically is us.d to scan through some table which might .pOl'
instance conv.rt English characters to German characters.
However .
this capabilitlj can also be used to intercept ".punction calls" (that
is, scrolL attribute h .. ndling.
etc.)
and allow an application to
encode custom CRT .punctions.
The user should be car • .pul IIIhen using
this capability however, because it might di"sturb the data structures
o.p the CRT OSR.
NOTE

When using
this capability, it is imperative that
the us.,. .... sto.... the v.cto... to its original v .. lu.
upon compl.tion of us. 0... the sljstem could "go
.. ~" u.

Onc. the u ..... ' . m"pping ... autine has b.en enter.d,
h. c ..n us. all ... egisters except ES, OS, and BP
unless h. saves them and restores them upon .xit.
When using
this mapping .p.atur.,
the us .... must
.pirst look at the opcode in ... egister AH
to
d.t .... min. if it is in .pact a ",... it. cha ...act.r
.... qu.st.
I.p so. he must also p .... se ... v. regist.r AH
and the .... gist .... s
associated ",ith that .punction
which contain c.,.tain pa ... aftlet .... s.
For .xamp 1.,
i.p
the u..... ",ish.d to map all
"s" symbols to the
int .... nation.l cu ....... nclJ sljmbo1,
his routine ",auld
manito... "'.gist.... AH an each call to the CRT DSR.
r.p it contained. ",rite characte ... opcode he ",ould
then loa k at ... eg i st .... AL.
I.p reg ist e ... AL contai n.d
II
24H (ASCII code .po... a
"S" symbol), he ",auld
change that .... gist .... to an A7H (ASCII code .po... the
int .... nation.l cu ...... enc" s"mbol>'
All registers a ... e
p......... v.a, but .... giste... AL has been changed as
d.sc ... ibed.

-

-

,

,
I

T.xas Instruments

3-29

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1983

3. 10

DISK DSR

Table 3-6 describes the functions supported by the Texas Instruments
Professional Computer disk
device
service
routines.
Detailed
descriptions ~or each function are given.
Table 3-6
CODE
OOH
01H
02H
03H
04H
OSH
06H*-

DESCRIPTION
Reset disk system
Return status code (for last operation)
Read sectol's
Write sectors
Veri~y sector CRCs
Null operation (format track>
Verify data
Return retry status
Set standard Disk Inter~ace Table (DIT>~or unit
Set DIT address ~or unit
Retul'n DIT address for unit
Turn o~f diskette dl'ive motol's.

07H*

08H*09H*OAH*OSH*-

*

Disk DSR Opcodes and Functions

These

al'e primarily for the use of system-level
and utilities

~unctions

soft~re

3. 10.1

Reset Disk System - OOH

Input:

AH - OOH

Output: AH

= OOH

This function causes the disk system to restore itself to a known
state.
What this function does for each type of device supported
varies with the l'equirements of the device and the device-dependent
softwaT'e.
In geneT'aL the ~unction causes the disk controller (s> to be
re-initialized pT'ior to their next use.
3.10.2

Return Sta tus Code - 01H

Input:

AH

Output: AH
AL
CF

Texas

= 01H
= OOH
= Status code ~OT'
= 0 (No change)

InstT'u~ents

last disk 110 opeT'ation

3-30

PRELIMI NARY-Jan 21.

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

Not all disk DSR functions are I/O operations (this one, for instance).
A status is returned in AH for eac h runcti on, but the s.t.tus o~ th e
last I/O re~uest is al~ays retained ror later access (via this
9unction). if desired.
:3. 10.:3

Input:

Read Sectors - 02H
AH

AL
CH

•

of sec tars
= Number
Cy linder number

•
DH •

Cl

02H

to tran sfer

•

Sector number
T,.ack Ci. e. , su,.face a,. side> number
DL • O,.ive numb.,.
ES;BX - Segment:
offset of buffer
Output: AH • 1/0 status code (se. pa,.agraph 3.10.12, "Status Cades")
AL • Numbe,. of unp,.acessed sacta,.s
ES:8X - Seg.ant:offset of tha last s8CtO,. p,.ocessed
This function reads data from the disk. ANY NUMBER of sectors can be
transfe,.ed subJect to memory boundary limit.tions (The segment/s 64K
boundary and disk bounda,.ies cannot be c,.ossad. )
-last secta,. p,.ocessed" means exactly that.
ar,.o,., the data is t,.ansfer,.ed to memory.

3-31

Even if the

,.ead

~as

ih

PRELIMI NARY-Jan 21. 1983

DEVICE SERVICE ROUTINES
•

3.10.4

Write Sectors -03H

Input:

AH III 03H
AL = Number of sectors to tran s fer
CH = C" Ii n d er number
CL = Sector number
DH = Track (i. e. , surface or side>
DL = D,.ive number
ES:BX • Segment:o~~set o~ bu~~er

•

numbe~

Output: AH .: 1/0 status code (see paragraph 3.10.12, "Status Code5
AL
Numb.r of unp,.ocessed sectors'
ES:BX • segment:o~~set o~ the last sector processed

=

11 )

This function ",rites data to the disk.
~V NUMBER o~ sectors can be
transfered subJect to memor~ boundary limitations.
(The segment's 64K
boundary and disk bound.ries cannot be c,.ossed. )
IILast sector processed" means exactl" that.
I~ the ..,,.ite is in error,
ES:BX point to the data which the DSR is attempting to t,.ans~er.

3.10.5

Vel' if" Sec tor CRC. - 04H

Input:

04H
AH
AL • Number of sec tor. to tran sfer
CH • Cylinder numbe,.
CL :III: Sector number
T,.ack (i. e., su,.face 0'1" side) number
DH
DL • Drive number
ES:BX • Segment: offset of buffer

-

Output: AH - 110 status code (see paragraph 3.10.12, "Status Codes")
AL • Number of unprocessed sectol'.
ES:BX • Segment: offset of the last sector processed
This function verifies the CRCs of the specified secto,.s.
Because this
~unction is handled like an 1/0 function, ES:BX must be set as though a
transfer is to take place although no data is actuall~ transferred.
ANV NUMBER of sectors ma" be processed subJect to memor~ boundary
limitations.
(The segment's 64K boundar~ and disk boundaries cannot be
crossed. )
ttLast sector processed" has little meaning
function does not actuall" transfer data.

in

this

case

as

this

)

Texas Instruments

3-32

PRELIMINARY-Jan 21,

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

3. 10.6
Input:

Veri'~

AH
AL

CH

Data - OOH

06H
= Numb.,.
of sec tOTS
=
a CIj 1 inde,. numbeT

to pTOC ess

CL = Sacto,. numbe,.
DH = T,.aclr H. e. , sUTface a,. side) numbe1"
DL = D1"ive numbe,.
ES:BX a Segment: offset of buff.,.
Output: AH - 110 status code (se. pa1"ag,.aph '3.10.12. "Status Codes")
AL a Numbe,. of unprocessed sec tOTS
ES:BX • On e,.ror, .egment: offset of WORD in er"01"
This function verifies disk data against data in memo,.v.
ANY NUMBER o~
secto,.s can b. proces.ed subJect to m.m01"1j boundaTY limitations (Th~
segment's 6410( boundarlj and the disk boundaries cannot be c1"ossed.)

I

3.10.7

R.tu,.n Retrv Status - 07H

Input:

AH - 07H

Output: AH - OOH
AL - So't .1',.01" status a' last 110 op.ration
This 'unction i. simi!a,. to tha R.tu~n Status Coda (OlH) function.
It
retu1"ns the "soft" .rror status a' the last opeTation. Soft erT01
Te'e1"s to an e1"ror that did nat recur ~han the last operation ~a~
re t1"ie d.

Texas Inst1"uments

3-33

PRELIMINARY-Jan 21,

1983

DEVICE SERVICE ROUTINES

3. 10. S

Set Standard Disk Interface Table - OSH

Input:

AH
AL
DL

= OSH
= Standard
= Diskette

OIT number (Valid values are 0 through 3)
drive number (Valid values are 0 through 3)

Output: AH = Error status (see paragraph 3.10.12,
(NOTE:
so~tlllare.

This
)

~unction

is

provided

~or

"Status Codes">

the use

o~

operating

Disk

inter~ace tables (DITs>
are data structures that
in~ormation used by the device-independent part o~ the DSR
with the device-dependent code ~or a speci~ic disk device.

s~stem

contain the
to inter~ace

This ~unction .1101115 one to set up a diskette drive to one o~
standard con~igurations by setting that drive'. OIT.
The standard
numbers are de~ined as ~o110Ills:
NUMBER

~our

DIT

DESCRIPTION

--------------si de,

Single
48
Single si de, 96
Doub 1 e si de, 48
Double • ide, 96

0

1

2
3

tp i,
t pi.
tp i,
tp i,

S sectors/track.
S sectors/track,
S sectors/track,
8 se c tor s/trac k I

512-byte
512-byte
512-byte
512-byt e

sectors
sectors
sectors
sectors

3.10.9

Set DIT Address

Input:

AH ~ 09H
DL - Disk drive number (Valid value is 0 through 7)
ES:BX = Segment:o~~set o~ DIT ~or drive

Output: AH
(NOTE:
50 ~tware.

= Error

This
)

~or

Drive - 09H

status (see paragraph 3.10.12,

~unction

is

provided

#or

"Status Codes")

the use

0'

operating system

Disk inter~ace tables (OITs) are data structures that contain the
information used by the device-independent part o~ the DSR to inter~ace
with the device-dependent code ~or a 5peci~ic disk device.
This function allows one to set any disk to a con~iguration other than
the four standard configurations.
This is the mechanism bV which
dynamic linking o~ dis.k drives to the system is accomplished.

Texas Instruments

3-34

PRELIMI NARY-..)an 21.

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

3.10.10

Input:
Output:

Return DIT Address

~oT'

= OAH
= Disk drive number
AH = Errol' status (see
ES:BX = Segment:o~rset
AH
DL

(NOTE:
This
so ftblare. )

runction

is

Drive - OAH
(Valid value is 0 through 7)
paragraph 2.13. S. IIEr1"o1" Codes
of DIT ror d1"ive

provided

ror

the use

Or

ll )

operating

s~stem

Disk interface tables (DITs) are data structures that contain the
information used by the device-independent part of the DSR to interface
with the device-dependent code for a specific disk device.
This function allows the user to access a drive's DIT for information
and verification pUTposes.
3. 10. 11

Input:
~

--

Turn OFF All Disk ette Dri ves - OBH

AH - OBH

Output: AH - 0
(NOTE: This function is provided
so ftw.re. )

for

use

of

operating

Un d er normal oper&ti on the diskette drive motors are l.ft ON ror ~
period of time following a read or write operation to save time waiting
for the motor to come up to speed.
Some applications.
notably
diagnostic S,
req,uire a function to ensure that the motors are not
running.
•

All functions return a status c·~de in register AH and an ert-or flag in
CF.
Ir the cart-y condition is set (CF = 1), then an error has occurred
and AH contains the error code.
If the no-carry condition is set (CF =
0), no Ift-ror bas occurred and AH always contains a zero (0).
The e1"1"01"
codes are.given in Table 3-7.

Texas Inst1"uments

3-35

PRELIMINARY-Jan 21,

1983

• , - V I • • • W'~

., ....... "

. . .w

..

Table 3-7

VALUE

DESCRIPTION

OOH

No error
Timeout - drive not ready Dr hardware failed
Seek failed - track not found
Controller hard~are failed
CR C er ,. 0,.
Data request error - controller ~ailure
Reco,.d (sector) not found
No data - bad disk format
Comm.nd error - bad opcod~ Dr paramet.r
Disk ~rite protected
Data did not verif~
110 transfer crosses 64-kb~te boundar~

80H
40H
20H
10H
08H
04H
02H
01H
03H

OSH
09H

3. 11

Error Codes

KEYBOARD DSR

This subsection describes the keyboard DSR and the functions it
provides to the svstem 0,. .pplication programs that use it.
It also
shows
the various codes returned b~ the DSR for the standard
configuration of the keyboard.
.The keyboard DSR functions are located in the system ROM and are
accessed th,.ough the SOSS software inte,.rupt mechanism (essentiall~ an
ad d,.ess-independent subroutine call>.
The typ ical user of the key board
DSR is the operating system-dependent BIOS,
which resides on a
particular operating system diskette and which is loaded into RAM
during disk boot.
The functiDns described herein access a buffer that is controlled by
the keyboard .interrupt service routine.
All encoding and any special
handling (described in subsequent paragraphs) occurs in the interrupt
servic e routi ne.
All di scuss ions of keVb oard map ping vec tors re;er to
actions occurring during the servicing of the keyboard hard~are (not
.oftware) interrupt.
The desired function is chosen bV placing an opcode in register AH and
executing an INT 4AH.
All registers except AX are preserved.
The
following functions are included in the keyboard DSR.
3.11.1

Initialization Logic

The code for this function is automatically executed during power-up Dr
reboot and is not directly
available to the user.
It performs
diagnostics on the keyboard hardware,
sends to it the required
initialization sequences, and initializes the DSR intern.l data ~reas.

Texas Instruments

3-36

PRELIMI NARY-Jan 21.

1983

~

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

r,
3.11.2
This

Read

Kevboa~d

~un~tion

~eads

Input - AH a 0

and

~emoves

the

cu~rent

cha~acte~

(i~

any) from the

bu~~e~.
The cha~ac te ... value is retu ... ned in ~eg iste ... AX.
If
there is no characte~ ready, the
wait until
one is received
be~o~. it ~.tu ... ns to the calle~.
This character has al~eady been fully
encoded (re~e~ to Table 3-8>'
No~mally, the encoded ASCII character is
... etu~ned in ~egiste,. AL, and register AH contains 00.
If AL.
0, then
the coded value in AH CO,. .... sponds to on. o~ the various function kevs
(R.~.~ to Table 3-9.
keyboa~d

DSR will

=

AH

=:

1

This function data~minas wh.th.~ a cha... act.~ is ~eady at the k.yboa~d
'-lithaut having to actually ~aad it.
If no cha~acte... is ...aiting,
it
retu ... ns '-lith tha Z-.,lag sat (-0.
If the Z-~lag is ~eset (=0), a
cha...act .... is availabla to ba ~.ad.
Th. cha~acta ... value is ~.turned in
AX, but is not ~amov.d f~om the k.yboa~d buf"e~.
AH -

2

This "unction d.t .... min.s the currant mode of the keljboa~d.
The moe,_
value is ~.tu ... n.d in ~.gilt.,. AL in tha ~ormat shown in Figure 3-3
Th. definition of the byta is as follo'-ls.

I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I

<---

Reg AL

1 - Cont... ol key depressed
-------

1

= Alternate key depressed

-----------

1

=:

---------------------------------------------------------

Figu .... 3-3

Texas Inst ... uments

BVte

0000
1

Shift kay depressed
( a 1 ilia y s

= Caps

De~inition

3-37

ze r

0 )

lock key depressed

- Keyboa ... d

Mode~

PRELIMINARY-Jan 21.

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

Because the IImod ell applies to the la st character typed and not
necessarily to the one at the front of the q,ue ue, this function re turn 5
va 1 id information only if the iceyboard bUrrel' conta i n50 one Dr les s
charae ters.
In order to uSe this runction, t.he key s h ou 1 d be read
normally, then a status eh ec k made to make sur' e th e bUrrel' is empty.
If the buffer is empty at this point, the mode may be read.
3.11. 5

Flush Keyboard Burfer

AH

z

~

3

This runction is used to "rlush"
(empty) the keyboard type-ahead
buffer.
It simply resets the q,ueue pointe'rs, which efrectively empties
the bUrrel'.
3.11. 6

Keyboard Output

AH

=4

This runction sends the keyboard command in AL directly
to the
keyboa'rd,
with appropriate handshaking.
Upon return, the Z-flag has
the 5 tat us 0 r the 0 per a t ion.
I r the Z-r lag
( ZF ) i 5 set ( -1) ,
the
c omman d was p err orme d c orree t ly; oth erwi 5e (ZF=O), an error was mad e.
The keyboard commands sent by the CPU are given in Table 3-8
Table 3-8

Keyboard Commands

AL

FUNCTION PERFORMED

00

Perfo'rm a powerup 'reset and
install derault parameters
Turn repeat-action reature ON
Turn repeat-action reature OFF
Lock the keyboa'rd
Unlock the keyboard
Turn keyclick ON**
Turn keyclick OFF**

.01*
02

03
04*
05
06*

)

* lnd icates the derault parameters.
** Keyclick req,uires hardware modirication.
p'resently supported.

Texas Instruments

3-38

It is not

PRELIMINARY-Jan 21,

1983

TECHNICAl REFERENCE

DEVICE SERVICE ROUTINES

3.11. 7

=5

Put Character Into Keyboard Buffer - AH

This function places the 16-bit value in BX directly
into the keyboard
buf.f!e1'.
On 1'eturn, if the Z-flag is reset (=0),
the character \alas
placed
in the buffer (this is the normal case),
If' the Z-flag is set
(=1),
the buffe1' \alas full, and the character \alas not placed
in the
buffe1'
(it is still in BX).
A subsequent Read Keyboard Input (AH=O)
function call retrieves this characte1' (assuming the buffer \alas empty
to start lAIith, and no keys have been typed on the keyboard.) Any 16bit value can be placed into the buf.f!er, but unless the user has some
explicit application that understands "strange" characters from the
keyboard, it is recommended that only standard characte1'S gene1'ated by
the keyboard
be used.
The format for the characters is the same as
that given in the Read Keyboa1'd Input function.
To place a normal ASCII character into the buff.r,
the function
call
should be made lAIith the character value in BL and zero in BH.
To ,place
function keys into the buffer, the function call should be made lIIith
the extended function value in BH, and zero in BL.
(Refer to Table 3-9
a., d Tab Ie 3-10 >.
This function can be useful in situations IIIhere a program needs to make
characters that appear to have been typed
in at the keldboard.
TI&H'i
x amp I e s 0 f t hi. folIo IAI.

r ·
j

*

An application can ensure that the op.rating system printer
necholl feature is disabled by ins.rting a CTRL N into the
buffer during initialization.
The operating system sees this
as Just another key and tUrns off the echo.

*

Many op erati ng 5 y stems lac Ie a
cha i nin g feature,
and
th is
function may be used
to provide one.
Immediately before a
program terminates, characters can be placed into the keyboard
buffer (a flush operation is recommended first> to simulate a
comm.nd
being typed at the
keyboard.
When the program
terminates,
the op.rating system takes aver,
reads
the
keyboard buffer, and performs that command (lilhich could invoke
a .econd program, effectively IIchaining" programs).

3. 11.

e

Q.n.ra1 Kevboard

L~yout

outline of the
keyboard .lind the ke~ position numbers associated
each key ~re sho~n in Figure 3-4.
These are the scan codes sent
f1'om the keyboa1'd and a1'e used internally by the keyboard DSR to encode
the key.
Note that the kevs marked lIIith "***" (mode keys) are not in
the actual matrix and do not generate a scan code.

The

~ith

Tex~s

Instruments

3-39

PRELIMINARY-~an

21.

1983

DEVIC~

(I i )

ED Q Q (·~Z~~IC)

(iii)
.....

rnr;J~~Q

m

IT]

SERVlCE ROUTINES

--,

E±)t;)r;)t;)D

0r;J@g=

m

GffJG

0

.....

."

0
(,)

C
II

u

cg]

OmJLJ

r~]

_It"
u~

(- []

~

CII

:: ~ ~z

=m
rJ,D6·!
h

GjDQO
Q~Q[J
(J~~["J
-.
-0

[1J

Ul

.....

~

oQ@r:i

LiJ ['d~~~
.....
::c
LiJ Q~~~
c.
=
LiJ rd~~~

r;t]
[' C!]

EJ~~~
••
Q
LJ~~~
.....
en
rJ~&JQ
C

....c

iii
0

~

En

..,
::t

,

0

)

::::I'

II

...J

."
~

II
0

.a
::::I'
...
:=c

II
~

...c

III

Q
~

I

C')

...
~

::t

....

aI

~

ON

r~J o~ ···W
- -

~

Texas Instruments

:~~

i

ti

•c

0~mm
III

•

3-40

PRELIMINARY-Jan 21,

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

J. 11.9

Character Codes

Table 3-9 lists the character and extended function codes returned
the keyboard DSR.
The modes are handled internalllj to the keljboaT"d
and the returned code reflects the mapping shawn in this table.

by
DSR

General nates to Table 3-9:
1.
:l.

Key .. is shown in Figure 3-4.
In each column, bath the "gT'aphic" and the hex value
of the characteT' are given in the farm: QQQ HH.

3. EntT'i.s consisting of 1 1 _ - _ _ II indicate that the
combination i. suppressed within the keyboard DSR.

4. EntT'i.s conSisting of
XXX **11 indicate special
handling in the farm of diT'ect action by the keyboard
DSR.
(For details, see paT'agraph 3.11. 14, nSpecial
Handling")
II

e.

r

6.

Normal (ASCII) characters aT'e T'etuT'ned in T'egisteT' AL
in AH.

lili th the Key •

Ent,.ies consisting of "xxx yy*1I are retu,.ned ... ith AL-O
and the indicated value (yy) in AH.

Texas InstT'uments

3-41

PRELIM! NARY-Jan 21.

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

"'\
Table 3-9

Standard

Keyboa~d

Character Codes

-----------------------------------------------CO\ITROL
COMMENTS
SHIFT
ALT
KEY *1 NORM
I
I

I

I
I

-----------------------------------------------4!5 3F* .'5
af5
F5
01
58* c4!5
02
03
04
05
Ob
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

fb
f7
f8
f9
flO
'11
f12
1
2
3
4
5

40*
41*
42*
43*
44*
45*
46*
31
32

33
34

35

b

~

7
8
9
0

37
3S
39
30
2D

BS
,

OS
60

=

3D
2B
20

+
SP
HT

1

3D

09
31

sfb
59* cfb
sf7
5A* cf7
5B* c '8
s'8
·5C*
5'9
c '9
sf10 50* c '10
sfl1 08* c'l1
sf12 09* cf12
21
@
40
Fnul
23
24
X
25
A.
5E
RS

..

•
&c

--US
DEL

..

30

00

0
CR

4

34

4

5
9

35
39

9

5

2D

32

2b

2A
(
28
)
29
SF
+
2B
BS 08
'" 7E
3D
+
2B
SP 20
Bktab OF*
1
31
*

0
CR

2

I

2

30
00
34
35
39
2D
32

64* af7
65* af8
66* a'9
b7* afl0
CA* .'11
OB* a'12
altl
03* aIt2
alt3
alt4
aI t5
lE
alt6
.. 1 t7
al t8
al t9
altO
lF
altalt7F

.

3D

+

2B

SP
HT
1

20
09
31

0
CR

pfl
pf2
pf3
p'4

---

bC*

bO*
bE*
6F*
70*
71*
OC*
00*
78*
79*
7A*
78*
7C*
70*
7E*
7F*
80*
81*
82*
83*

Fb
F7
F8
F9
FlO
F11
F12

BACK SPACE
Be*
80*
BE*
SF*

NUM ..
NUM +

NUM SPACE
NUM TAB
NUM t
(unused)

5

30
00
34
35

9

39

NUM 5
NUM 9

2D

NlJ'1 -

2

32

NUM 2

4

r

b2*
b3* a'b

NUM 0
NlJ'1 ENTER
NlJ'1 4

-----------------------------------------------

Texas Instruments

I

3-42

PRELIMINARY-Jan 21.

1983

TECHNICAL REFERENCE

r

Tab 1 e 3-9,

DEVICE SERVICE ROUTINES

Stan da1'd Keyboard Character Codes (Continued)

--------------------------------------------------,
,
. COMMENTS
NORM
SHIFT
CONTROL
ALT
KEY *'
------------------------------------------------I

I

I

36
37
38
39
40
41
42
43
44
45

46

('

47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
6S
69
70

7
8
6

37
38
36

3

2C
33
~

Ptogl
C-rt
Ins
Del
HT

I

7
8
6
3

37
7
38
8
36
6
2C
3
33
2£
**
8A*: cC-rt
28*= eIns
3S*' cDe1
HT
OF*'
51
DC1
57
ETB
45
ENG
S2
OC2
54
DC4
59
EM
NAK
55
49
HT
4F
SI
SO
OLE
78
ESC
QS
7D
OA
eLF
**
88* cC-up
ESC
18
41
SOH
S3
DC3

72* ***
4D* sC-1't
52* sIns
53* sDel
09 Bktab
71
G
It
W
77
e
65
E
72
R
l'
74
t
T
79
V
II
u
75
U
i
69
I
0
6F
0
p
70
P
[
(
58
]
)
5D
LF OA
LF
Ppau **
Pb1'k
C-up 48* sC-up
ESC 18
ESC
a
61
A
73
s
S
d
44
64
D
f
F
46
66
67
47
G
9

...

I

EOT
ACK

BEL

2C
33

(unused)
(unu sed)
(unused)
NUM 7
NUM 8
NUM 6
NUM
NUM 3

~

NUM

37
38
36

74* .C-1't 4E*
29* alns 2A*
39* aDel 3A*
09
altO 10*
11
17 I altW 11*
05
altE 12*
12
al tR 13*
14
altT 14*
19
altV 15*
15
altU 16*
altI 17*
09
altO lS*
OF
10
altP 19*
18
1D
75* aLF 4F*
84* aC-up 49*
18
01
altA 1E*
13
altS 1F*
04
altD 20*
06
altF 21*
altQ 22*
07

(PRINT)
RIGHT ARROW
INSERT
DELETE
TAB

LINE FEED
(BREAK/PAUSE)
UP ARROW
ESC

--------------------------------------------------

Texas Instruments

3-43

PRELIMI NARY-Jan 21.

1983

_ _ ..

Table 3-9.

Standard

Kevboa~d

Cha~acteT

_

__

_.

~

or . . . .

~

"

.... ' "

,

..

,.,.~

t.J

Codes (Concluded;

--------------------------------------------------.
CCt-.lTROL
COMMENTS
KEY.: NORM
SHIFT
.o.LT
-------------------------------------------------48
BS
71
H
al tH 23*
I
I

I
I

h
J
k

I
I

I

08

68

4.0.
LF OA
a1 tJ 24*
48
VT 08
altK 25*
FF OC
4C
altL 26*
I
~
3.0.
3S
II
I
27
22
CR OD
CR 00
CR 00
77
\
7C
FS 1C
5C
78
79
C-If 4B* sC-I,p SS* cC-lf 73* aC-If 4C*
SO
Home 47* sHame 86* cHome 77* aHome 85*
SI \,
SP 20
SP 20
SP 20
SP 20
5.0.
SUB 1.0.
z
7.0.
altZ 2C*
82
Z
78
CAN 18
altX 2D*
83
I
X
58
43
ETX 03
84
c
03
C
altC 2E*
76
SVN 16
85
v
V
56
altV 2F*
STX 02
b
42
86
62
B
altB 30*
n
4E
87
6E
N
SO DE
altN 31*
CR 00
m CD
M 40
88
illtM 32*
89
2C
< 3C
90
Ptogl 72* *** **
91
2E
> 3E
/
2F
?
3F
92
93
Del 53* sDel 38. cOeI 39* aD.I 3.0.*
94
Ins 52* sIns 2S* eIns 29* aln. 2.0.*
95
96
C-dn 50* sC-dn 89* eC-dn 76* aC-dn 51*
97
98
99
Ppau
100
Pbrk *.
,pI **
101
54* e ,p1
68*
5E* afl
38* sf1
f!2 3C* sf!2
102
55* e ,p2
69*
SF* a,p2
f3 3D* sf!3
103
56* c +'3
60* iI+'3
6.0.*
104
f4 3E* sf!4
61* af4
6B*
57* cf4
72
73
74
75
76

6A
bB

J
K
L

-

I

---

RETURN
LEFT ARROW
HOME
SPACE baT'

PRINT
'I

)

(unused)
(DELETE)
( INSERT)
DOWN ARROW
(·unu sed)
(uniJ sed)
(unused)
BREAK/PAUSE
Ft
F2
F3
F4

--------------------------------------------

Texas Instruments

3-44

PRELIMINARY-Jan 21,

1983

DEVICE SERVICE ROUTINES

r,

3.11.10

Extended Codes

Th e II extended II codas (non-ASC I I codes) repres ent spec ial ~unc tio" key s
on the keyboard.
They are distinguished by register AL being 00 upon
returning
~rom
a Read Keyboard (AH=),i, or 2) -Punction calL in which
case the extended code is in register AH.
They are in a range o~ codes
(OOH-FFH) that includes normal ASC.II and they are given in Table 3-10.
T~ble

MSD

o

3-10
3

1

Extended Function Codes
4

S

7

8

af9
afl0
Ptog 1
cC-If
cC-rt
eLF
cC-dn
cHoma
alt1
alt2
alt3
alt4
alt5
alt'
alt7
alt8

alt9
altO
alt-

LSD

o

~ltQ

altW

1
2

3
4

~ltE

Fnul

~ltT
~ltY
~ltU
~ltI

~

•e
7

(

9

altR

sfl1

altO

54112

~ltP

/it

cfl1

B

cl12

C
D
E
F

.-P11

Texas Instruments

C-dn

aC-dn
Ins

f7

418
f9
flO
fll

alt~

altK
altL

4112

sIns
elns

sDel

Home
C-up

eDel

~C-up

alns

aDel

:altX
altA :altC
Bktab altS laltV
.112

f.

altD
altF
altO
altH

11
f2

.C-lf

f3
14
fS

C-rt
.C-rt
.LF

C-lf

Del
sfl
sf2
sf3
sf4
sfS
sf6
sf7
sfS
sf9
5fl0

cfl
cl2

3-45

e-P3
c -P4
c-PS
c -P6
cl7
c -P8
c ~9
c~10

.fl
.-P2

.,3

.f4
.fS
.f6
.f7
afS

~lt·

cC-up
aHoma
sHome
sC-up
sC-dn
sC-l"t

sC-ll
p fl

pf2
pf3
pf4

PRELIMI NARY-Jan 21,' 1983

DEVICE SERVICE

TECHNICAL REFERENCE

ROUTIN~S

."'\
3.11. 11

Keyboard Modes

In the standard kevboard. the mode keys have the e~fect shown in Table
3-9.
The latching .
If the
queue is ~illed, anv further characters entered at the kevboard cause
the system beeper to sound.
The Flush Kevboard Buffer (AHc 3) function
causes the Q.ueue pointel's to be reset, which ef~ectively empties the
b u f'er.
3.11. 13

Repeat-Action Feature

If! the repeat-action f!eature (the def!ault)is enabled, .11 keys are
repeat action at a 15-cps rate after an initial delay of 1/2 second.
Repeat-action characters are ignored if the queue currently contains
Texas Instruments

3-46

PRELIMINARY-Jan 21,

1983

,

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

(

The result o~ th is is that th e
more than one pend ing character
, application does not have to worry about the repeat-action "c oas ting "
problem; that is, i~ the application doe s not or cannot read th e
ihe unde sired
input 9aster than the repeat-act ion rate,
ke~board
does
not get
characters
q,ueued
th
e
are
not
and
ke'dboard
l' e p eat-ac t ion
the
application.
04!
ah ead
3. 11.14

Special Handl ing

section deals with 4!unctions handled by the ke'dboard DSR itsel~.
are 5eve~al eases in ~hich immediate reaction is ~equired
(~or
example,
pausing the output routine so a flast-scrolling screen can be
read>.
Most
these 9unctions are implemented ~ith the so~tware
inte~~upt 'acility 0' the 8088.

This

The~e

0'

0'

0'

Each
the de'ined inter~upt vecto~s points to some de'ault piece
code that eithe~ does nothing (a single IRET inst~uction) o~ pe~flo~ms
some
system function.
An application p~og~am may change these
inte~~upt vecto~s in o~de~ to gain di~ect access to a 'unction. but the
application is responsible 'or p~ese~ving the o~iginal contents 0' the
vector and restoring it befo~e te~minating and retu~ning to the system.
Note that the application routine, i~ used, must end with an IRET (or
the equivalent "RET 2", ~hich allows flags to be passe~).

r

The stack used is the internal stack 09 the keyboard interrupt service
routine and only 10 levels (20 bytes)
stack are available to the
use~'s ~outine.
Note that inte~rupts are disabled when the user
routine is entered (due to the INT inst~uction). They should be ~e­
enabled immediatelv unless it is necessary for them to be disabled.
Registe~s
AX, ax. ex, 01, and ES may be used (in'o~mation is passed in
AX); antj Dthe~s must be p~ese~ved.
I' the available stack is not large
enough, then the routine should switch to an inte~nal stack of
su'ficient size (plus eight bytes 90~ possible interrupts>.
Also, the
routine is executed as a part 09 the keyboard interrupt service
routine,
~hich
means that no othe~ keystrokes are accepted until the
use,. ,.outine 'inishes and ,.etu,.ns.
The no,.mal .... '1 to communicate with
the outside wo~ld (outside the se~vice ~outine) is to set a 9lag, and
to watch fo,. the flag in the application.
For example, this is ho~ the
BREAK function is implemented in MS-DOS. For these ~easons, control
should not be retained b'J the use,.'s routine unless a complete s'dstem
initi.lization is to be pe,.formed .

0'

•

Texas Instruments

3-47

PRELIMINARY-Jan 21.

1983

DEVICe

3.11.15

~RVIC~

ROUTINES

User-Available Interrupts

The following is a summar" of the software interrupts performed D~ the
ke~board
DSR that may be used by application programs.
The interrupts
are presented in the order that they are executed.
The number ir,
parentheses, the "interrupt type ll , is used in an INTerrupt instruction
The abs'olute address of the corresponding vector is the interrupt type
times 4.
As an example, the address of the keyboard mapping vector is
SBH Ie 4
1bCH.
Note that any of the special
interT'upt functions
can be bypassed b" T'e-encoding the key code as described
in paragraph
3.11.21, "Custom Encodingll.
The keyboaT'd DSR interrupts "are:

Ic."

=

*

1.

Keyboard Mapping Interrupt C5BH)

2.

Program Pause Interrupt (5CH)

3.

Program areak Interrupt (SDH)

4.

Print Screen Interrupt (SEH)

5.

Keuboard Queueing Interrupt CSFH)

*
*
*

These Interrupts occur after internal encoding.

3.11.15.1
Keyboard Mapping.
This interrupt i. per'ormed each time a
ke" is pressed, but befo,.e it is encoded,
IIIhich a 11 OlliS the use,. to
encode th e key.
When the user encodes th e keu, the DSR places th eke"
code in the queue and performs Keyboard Queuing
(SFH) Interrupti
otherlilise,
the DSR encodes the key. checks for the special keys, and
then queues the Ice" code, causing the Keyboard Queuing Interrupt.
Use
this Inte,.,.upt in ,.e-mapping the keyboa,.d is described in pa,.ag,.aph
3.11.21, "Custom Encoding".

0'

3.11.15.2 p,.agram Pause.
Pressing the (unshifted) BRK/PAUS keU causes
a software inte,.,.upt and allolils the user to pe,.fo,.m an action 0,. return
a IceU code.
It will ,.etu,.n an extended code (see Table 3-0)
to the
calle,. if desi,..d.
At system power-up, the vector is set up such that
the PAUS keV sequence causes a screen hold,
which stops a fastsc,.olling
screen.
An .pplication program can change the interrupt
vector in order to suppo,.t a pause function
its allin, but the program
is responsible
,.emembering the original vector and restoring it
befo,.e terminating.
The Carr" 'lag determines the action
the
keyboard DSR upon retu,.n from the software interrupt.
If the Carr~
flag
is' set, the DSR does nothing else And simplu exits.
I' the .Carry
flag is reset, then the character value in AX is placed into the queue.
Before the sa,tlllare inte,.rupt is executed, the Carr" 'lag is reset and
the extended code
the p,.ogram Pause 'unction is placed in AX.
Therefore, if an IRET instruction is used
to return
instead
the
de'ault ROM pause routine. the DSR returns the Program Pause 'unction
code to the application.
Note that sin'ce the Carr" flag
is used to
pass in'ormation,
the IRET instruction must be simulated with "RET 2"

0'

'0,.

0'

'0,.

Texas Instruments

0'

3-48

PRELIMINARY-Jan 21.

1983

TECHNICAL REFERENCE

DEVICE SERVICE ROUTINES

i~ the use~ needs
~esto~es flags to

(The

'3.11. 15.3

~.tu~n with
Ca~~~
set.
thei~ p~e-inte~~upt state.)

to

P~ag~am B~ealr.

P~essing the

IRET

(shifted) BRK/PAUS ketJ causes a

.oftwa~e inte~~upt and allows the use~ to pe~~a~m an action o~ ~etu~n a
ke~
code.
It can be set to ~etUl'n an extended code (see Table 3-9) to
the calle~. if desi~ed.
Du~ing powe~-up initialization, this inte~~upt
vectal' is set up to paint to an IRET inst~uctian 50 that the BRK key
sequence
is
ignal'ed athe~ than ~etul'ning the bl'eak code.
An
application pl'ag~a. can change the intel'~upt vecto~ in arde~ to suppo~t
a break ~unctian of its awn.
Ho",eve~,
the program is ~espansible fo~
pl'ese~ving
the o~iginal contents a~ the vectal' and ~estoring it be~ore
tel'minating.
The encad ing Isof twar a-in t.~~ upt tec h n iqu e is th e same as
that descl'ibed in pa~ag~aph 3.11. 15.~. "P~ag~am Pause".

3.11.15. 4

P~int

Sc~een.

P~essing

the SHIFT and PRNT keys causes yet
The use~ can pe~form an action o~ l'etu~n a
Ire" code.
This no~mall" vectol"s to an IRET instl"uction lIIithin the ROM.
The DSR checks the c.~~" 'lag upon ~etul"n, ·as desc~ibed in the P~ogl"am
Pause and P~og~am B~ealr inte~~upt5 (pal"ag~aph5 3. 11. 15.2 and 3. 11. 15.3.
l"espectively). Befol". the inte~l"upt is executed, the Cal'l"Y ~lag is .et,
so if the l'autine consists ani" of an IRET,
the ke.,
is effectively
igno~ed.
This can be (and is, by MS-DOS BIOS) patched to vecto~ to an
actual P~int Sc~een l'autine.
This ~autine executes as a part of th~
keyboal"d inte~~upt se",vice l"outine and. thus. cannot be inte"'l"upted b~
anothel" keyst",oke.
anothe~ .oftwa~e inte~~upt~

('.

3.11.15.:5 Ke"ba.,.d Queueing.
This 50ftwa",e inter~upt accu~s evel'\:
time a characte"" IIIhethe~ encoded by the DSR Dar by the usel", is plac.i~
in the t"pe-ahead buffe~.
Its intended use is to enable a l'eal-time OS
ta sk to know IIIh en th e~e is a eh al"ac ter to be read.
The user ha 5 th I':
option of not having a
keycode q,ueued
(ignoring the keljL
S.~
paragl"aph 3.11.15. 1, nKe"baa~d Mapping" fal" Ke"baard Queuing interl"upt
conditions.
3.11.16

Custom Encodilag

Facilities a~e available to allow an application p~ogl"am to encode the
keyboard fa", itself, if nece5sa",,,.
Eve~" time a ke" is pressed on the
keyboa~d,
ana or twa Ice" cades are sent f~om the kayboal"d ta the DSR.
(Fo~
details see paragraph 3.11. 17Keyboard Interface Protocol).
Each
time a ke~ code (not including the made ke~ codes.
",hich a~e handled
inte~nally)
is l'eceived, a soft ... are inte'l'1'upt is per~ormed.
No-rmally
the inte",~upt vecto~ points to an IRET inst~uetian, but an application
pl"ag"'am can rep'l'agram the vector to
intercept these key codes. i~
neCe5Sa1'".
Since eve~"thing comes th'l'ough this vector. the application
can completel~ take ove~
(except fo~ the s~stem 'reset combination
CTRL/ALT/DEL>'
The 1"0utine that inte'rcepts the key codes typicallll
scans through same tables to encode its special keys and execute an
IJRET ~ ..
inst~uction
",hen done.
Note that in this situation it is
especiall~ critical that the application 'resto'l'es
the vector to its
original value aftel" completion Dr the 5ystem "'ill c'rash "'hen the
special encoding 'routine is w'I'itten ove'r.
Texas Inst'ruments

3-49

PRELIM! NARY-ojan 21.

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

When the sortwa~e inte~~upt is pe~rormed (r~om the k@yboa~d
inte~~upt
service routine), the keubaard scan code is in AL, the made byte is in
AH 

------------------------------------>

Parity

SECOND BYTE

18: 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I
I
I

I .

---------------------------)

------------------------------>
------------------------------------>
'Figure 3-5

Texas Instruments

Scan Code
Repeated Character
(Repeat-action keys)
Parity

Byte Oe9inition - Keycode

3-51

PRELIMI NARY-Jan 21.

1983

DEVICE SERVICE ROUTINES

The keyboard understands s.veral commands ~hich are detailed in the
Keyboard
Output
(AH=4)
funct ion,
and the Iceyboard (normallv)
ackno~ledges each command.
The codes sent bV the keyboard are given in Table 3-9 through scan code
104 (68 hexL
The scan codes ~rom 69H through 6FH are spares and may
be assigned in the 'uture. although the size o~ the standard encoding
tables does not comprehend thi s.
Codes 70H through 72H are status
codes returned by the keyboard in response to commands: 70H is normal
command ackno~ledge status. 71H indicates internal RAM 'ailure. and 72H
indicates internal ROM f.ilure. Codes 73H-77H are unused and codes
7SH-7FH are taken up bV the encoding 'or the mode key status byte.

3. 12

PARALLEL PRINTER PORT DSR

port DSR and th e
This subsection d.scrib.. the parallel printer
functions it provid.s to the system or application programs that use
it.
The
print.r
DSR provides routin.s ~ith ~hich to implement a
I'Centronics-compatibl. I' parallel port interface.
.It enables the us.r
to output characters. g.t p ... inter status • •nd ini tial ize the printe....
It is c.pable of int .... '.cing to most printer s ~ith a Centronicscompat ible inter'.ce.
The p... int.... DSR 'unctions .re located in the system ROM and are
acc.ssed
th ... ough
the .of.t~are interT'upt m.chanism
the 8088
micT'oprocessor. The desir.d 'unction is chos.n by placing .n opcode in
.... gist.r AH, zeros in register DL (see explanation of ... egister DL in
paT'agT'aph 3. 12. 4. "Use Und er .n Op erat i n9 Syst .m") and exe cut i ng an INT
4BH instruction.
All registers are preserved except AH. t1Jhich always
r.turns lIIith the printeT' status (see pa,.ag,.aph 3. 12.3, "R.turn Pr inter
Status - AH=2, Dl=O.'1 The 'allowing functions a .... available:

0'

3.

1~

1

Output Cha ... acter To p,.inte ...

AH • 0, DL

=0

This function sends the character in AL to the printer port.
The BUSY
signal from the printer is checked b.'ore sending the cha ...act.r.
If
the printer is still busy .,ter about 0.33 sec, the DSR sets the timeout bit in the status byte (in AH) and returns; otherlllise, it returns
~ith the time-out bit .... set.
Any abnormal conditions on the status
signals 'rom the p... int.r c.us.s the printer to go BUSY and time-out
occurs i' the print.r s.ts FAULT. PAPER OUT, or NOT SELECT.
It also
sets BUSY, c.using a time-out to occur.

0'

In gene,.a1, it is not desirable to rely on the time-out
the printer
output ... outine 'or normal use.
It is a so,tware loop and causes the
application to Uhang" during the time-out period.
The preoferable
method is to have the application watch the BUSY signal through the
printer status call and implement its ollln time-out (i' desired) under
its own control.
This is especially important ~hen using the DSR ~,.om
Texas Inst,.uments

3-52

PRELIMINARY-Jan 21,

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

the p~int.~ task
p~int a cha~act.~

a

o~

~.al-time

as.

There~o~e,

the

no~mal

se~uence

to

is:

REPEAT
INT.~rupt 4BH ~ith AH z 2 and DL
"R.tu~n p,.inte~ Status"Cparagraph

=0

(see paragraph 3.10.3,

3.10.33),

UNTIL
STATUS • NDT BUSY
END

=0

INT.rrupt 4BH with AH = 0, DL
IF STATUS • (tim.-out)

and AL = (character)

TJ-EN



(FAULT

PAPER OUT

01'

01'

(NOT SELECTED»

END

(R.ft,. to Figur. 3-6
3. 12.;

r

Initializ. Printer

~ar

b~te

de~initian

AHzl,

of Return p,.inter Status. )

OL-O

This function activat.s the INIT signal on the inter~ace causing the
p,.int.,.
to p.~fa,.m the .~uiva1ent a~ a po~e"-up res.t.
The speci~i,:
action tak.n is print.r-dependent (,.e~.,. to the app,.ap,.iate printe:
manual>'
The S'J stem soft...a~e aet i vates this si 9 na1 anI tj one e, a 'actual s~st.m pa.... ~-up (nat CTRL/ALT/DEL re •• t).

=0

AH - 2. DL

This function r.ads the print.~ status po~t and ~etUl'ns the infa,.matioi'
in ,.egist.~ AH. This is the same info~mation as that ~etu~ned a~tel
th. Output Cha~a C't.~ to P~ inter (AH=O, DL=O) and I ni ti a l i z e p,. intel'
(AH-l. DL-O) ~unctians. Th. bits a~ AH a~e encoded as sha~n in Figu,.e
3-6.

I 7 I 6 I

~

I 4 I 3 I ;

.

: 1 l 0 :

I

•
I

'

-------

TIME OUT (on bustj)

I

I

-------------------------------------

--------------------------------------------------------

----------------------------------•
Figu,.e 3-6
Texas

Inst~uments

Btjte

De~inition

-

(not used)
BUSY

PAPER OUT
SELECTED (ON LINE)

FAULT

Retu~n

3-53

p,.inte,. Status
PRELIMINARY-Jan 21.

1983

DEVICF. SERVICE ROUTINES

TECHNICAL REFERENCE

3. 12.4

Use Under an Operating System

One o-f the -features o-f using· the software intprrupt techniq,ue to
interface with the ROM routines is that a DSR can be enhanced or
replaced by patching its interface interrupt vector.
Under MS-OOS, for
example, the serial printer support emulates the ROM's parallel printer
func-tions.
The printer interface is implemented by patching a small
routine "in front of" the printer interrupt vector.
This 'routine looks
at register DL to determine the desired printer.
If DLczero,
then •
Jump to the ROM routine is made, and the u'ser is unaware of the patch.
If Dl.=1. however.
then AH is decoded to perform the appropriate
function on the serial printer.
Since the serial support emulates the
status returned bV the ROM's parallel routines, again the user is not
.ware of the operation. ex cep t for th e fa ct t hat he s.t DL.
Note tha t
some operating svstem. mav not require reg ister DL to be anvth ing.
In
the MS-DOS case, ho~.ver. the DSR was extended in a manner that DL must
be specified.
As this is not necessaril~ the case ~ith other operating
systems,
refer to the appropriate documentation for the operating
system used.

'\

Texas Instruments

3-54

PRELIMI NARY-Jan 21.

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

c
3. 13

The

WINCHESTER DSR

~egiste~

assignment

~o~

the Winchester

cont~oller

is given in Table

3-11.

Table 3-11

Winchester

Controlle~

1/0 Port Assignment

+-------------+---------------------+----------------------+
OUT FUNCTION
: t-EX ADDRESS :
IN FUNCTION
+-------------+---------------------+----------------------+
IMta IN
Data OUT port
0030
po~t

+-------~-----+---------------------+----------------------+
Status ~egi.t.~
RESET
0031

+-------+----.....--------+------------+Not used
0032
Not used
+-------------+---------------------+---------------------~
0033
Not used

+-------------+---------------------+----------------------+
An IN function .ets data f~om the Wincheste~ cont,.olle~ boa,.d an~:
d~iv.s
it onto the computers lID expansion bus.
Conve~sely, an OU1
function sets data ~~om the comput.~s lID expansion bus onto th~
Winchest.~ disk cont,.olle~ board.
3.13.1

Byte Definitions

The

following a~e byte definitions 'Dr the Wincheste~ cont~olle~
and po~ts.
(Additional inforflliltion /Ralj be
found
if!
subsection 2.13, "Wincheste,. Disk D,.ive and Cont,.oll.,.. II)

~egiste,.s

Cont~oile,. Status Regist.,..
This byte stores the controller
status.
It enables the compu~er to read the status o~ the controller
and manito,. its op.,.ation.
Bits o~ the cont~oller status byte a~e
defin.d as ~ollows.

3.13.1.1

I 7 : 6 I 5 I 4

I 3 : 2 : 1 : 0 I

(--- 1/0 Port address 0031H (READ)
1

= Data

Request

1 = Inp u t/ou tput

0 = Outp ut
1 = Command,

0 = Data
1 = Pend ing
'- .

---------------------Texas Instruments

3-55

interrupt

Don't care

PRELIMI NARY-Jan 2L

1983

3.13.1.2 Reset Pa,.t.
This bvte T'esets the contT'oller. An~ WRITE to
POT't 0031H T'esets the controlleT'.
Bits of the reset part b~te are

'"",.
I

defined as fallows.

: 7 : 6 : 5 : 4 : 3 : 2 : 1

I

0:

(--- I/O POT't addT'ess 0031H (WRITE>
Don't caT'e

•L>

\

"

Texas InstT'uments

3-56

PRELIMINARY-Jan 21,

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

3. 13.1. 3 Interrupt Mask.
in·t.,.,.upt to b. serviced.
as fo11allls.

A two-bit field in this byte determines the
Bits of the interrupt mask byte are definea

-----------------------I 7 I 6 I 5 I 4 I 3 I
: 1 : 0 I
~

<----- I/O Port address 0033H (READ)
1
1

= Status inte~~upt enable
= Data inter~upt enable
Don't care

3.13.1.4 Er,.o,. Status B~te.
available .fte~ a command has
that this bVte is available
Bits of the e,.ror status bVte

This bVte is a special case that is only
been completed.
The controller indicates
by setting the 110 and CID bits with DRG.
are defined as fa1101115.

I 7 I 6 I 5 I 4 I 3 : 2 : 1 I 0 I

-------

<---

1

= E,.ra,.

1

= Drive

---------------

3.13.2

Po~t

add,.ess 0030H CREAD)

bit

Don I t car.

---------------------------------

1/0

number

Don't care

WINCHESTER ROM

The Winch.st.,. ROM is designed to interface to the system ROM softillare,
speci'ica1lv, the system disk DSR.
It is located on the Winchester
c ant,.o lIe,. board,
bu t i s ad dre ssed b II th. sy stem pro cess or.
It IS
ad dress, as determined bg the hardlilare,
is OF8000H.
Th e convention
locates
the ROM at the address (as seen by the software) a~
OF400: 4000H.

The ROM contains softillare to interface to the system ROM disk DSR and
to drive the Winchester controller.
It also contains additional
softillare to a1lalll booting the system f,.om the Winchester disk,
formatting the disk, and running diagnostics (powe,.-up and advanced) an
the controller and disk.

Texas Instruments

3-57

PRELIMINARY-Jan 21.' 1983

DEVl~~

SERVICE ROUTINES

3.13.2.1
Limitations.
The DSR and other utilities provided bV the
system ROM limit t~e types of Winchester drives which can be used by
the svstem.
The limits are as follows;

*
*

X x Y cvlinders per drive.

*
*
*
*

17 sectors per track.

where 1

<

X

~

256 and 1 ( Y

<

"".
)

15.

16 surfaces per drive.

512 bytes per sector.
255 error retries
I1-bits error burst length

Most of the routines within the ROM are driven by data structures which
describe the type of drive compieteiv.
The svstem is powered up
assuming the following drive parameters;
153
4
125
64

c Vi in d er s
surfaces
first track of reduced write current
first track of write precompensation
1 error retrv
11-bit error burst length
3-millisecond step option

)

If the default parameters are not correct for the tvpe of drive in use.
the Initialize Winchester disk svstem option call must be done to setup
the correct parameters. Note that the svstem can always boot the first
sector with the default parameters.
3.13.3

System Interface

The ROM is initialized to the system when it is called after power-up
test by the sv.tem ROM.
The svstem ROM will have tested the Winchester
disk controller ROM to guarantee that it is functioning properly before
calling it.
To allow the svstem ROM to test and call it. the
Winchester disk controller ROM contains a header defining the size of
the ROM, the ROM's entry point. a version number, and an identification
message preceded bV the message length.
The entrv point called by the system ROM is re~uired to do any device
dependent initializ.ation and, optionally. to boot the system from the
device which the called ROM serves.
For the Winchest.r disk. the
operations are as follows.

*

Setup the ROM's RAM area 1n the svstem and set
installed bit in the system configuration word.

*

If the caller has passed the lido not boot" flag (OFFFFH in
register DX), return control to the caller.
Otherwise, (0 in

Texas Instruments

3-58

the

device

PRELIMINARY-Jan 21.

1983

DEVICE SERVICE ROUTINES

TECHNICAL REFERENCE

register OX) continue.

*

If the user has entered an IIESCII character from the ke\jboard,
return control to the system ROM (boot from the diskette>.

*

Otherwise, display the Winchester disk controller ROM
message and execute the controllers powerup tests.

*

Test all ROMs with a lo~er priority than the Winchester disk
controller ROM and then call them with the "do not boot" flag
set N

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PHYSICAL: SEE FIGURE 1

3.1.1

CABLE MATERIAL:
ONE CONDUCTOH #27 AWG CONSISTING OF 7 STRANDS OF #56 AWG
BARE COPPER WIRE OR 7 STRANDS OF #35 BARE COPPER COVERED
STEEL WIRE. SHELD CONSISTS OF 4 ENDS OF #36 AWG TINNED
COPPER SPIRAL WRAPPED OR BRAIDED COPPER WIRE. INTERNAL
INSULATION OF POLYETHYLENE WITH OUTER JACKET AND CONNECTOR
MOLDING TO BE LIGHT TAN IN COLOR MATCHING TI COLOR NUMBER
972939-2101. CABLE ASSEMBLY TO MEET THE REQUIREMENTS OF
UL AND CSA.

3.1.2

MARKINGS:
PARTS OR WRAPPER SHALL BE MARKED WITH TEXAS INSTRUMENTS
PART NUMBER

0

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IMPEDANCE:
CABLE IMPEDANCE SHALL BE 75.n. NOMIMAL.

,

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R
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CONNECTORS:
BOTH ENDS OF THE SHIELDED CABLE SHALL BE TERMINATED EITHER
WITH VICTOR PC-I03 PHONO PLUGS OR BELDEN STYLE PHG761 SHORT
STRAIGHT HANDLE PHONO PLUGS.
;...----------1219'. 2

c

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qUALITY ASSURANCE PROVISIONS:

4.1

RESPONSIBILITY FOR INSPECTION:
UNLESS OTHERWISE SPECIFIED IN THE CONTRACT OR PURCHASE ORDER,
THE SUPPLIER SHALL BE RESPONSIBLE FOR PERFORMING INSPECTIONS
THAT ARE SUFFICIENT TO ASSURE THAT THE PARTS SUPPLIED MEET
THE REQUIREMENTS SPECIFIED HEREIN.

5.0

PREPARATION FOR DELIVERY:
---

--------.-.~

5.1

PACKAGING:
PACKING AND WRAPPING SHALL BE SUFFICIENT TO PROTECT AGAINST
DAMAGE OR LOSS DURING SHIPMENT FROM THE SUPPLIER TO THE
DESTINATION SPECIFIED IN THE PURCHASE ORDER.

5.2

MARKING:
THE SHIPPING CONTAINER SHALL BE MARKED WITH THE TI PART
NUMBER (SEE PART NUMBER BLOCK) AND THE COUNT CONTAINED.
ADDITIONAL MARKING ARE PERMITTED.

~ TEXAS

INSTRUMENTS

IHCO",.OltATED
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RICHMOND, INDIANA 47374
2.

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,

,..,.

VICTOR ELECTRIC WIRE & CABLE CO.
618 MAIN ST.
WEST WARWICK,R.I. 02893

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SCHEMATICS AND LOGIC DRAWINGS
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"'an 21, 1983

Glossary

.bort -- To end • program .nd return control to the operating
svste., usuallv when a mistake or malfunction occurs.
acknowledge
charac ter
a sender .

character
(ACK)
A
transmission
control
sent bV a receiver .s an aPfirmative response to

• ddress -- A nUMber that represents a register,
a
location, or some other data source or destination.

memory

analog -- An obJect (or variable) that is represented by a
phvsical ~uantitVI such as a continuousl~ var~ing voltage.
The phvsical ~uantitv that represents the variable behaves
a. some function of the variable.
(Contrast ..,ith digital).

\

AND -- A binary function which is "on" if and only if all
its inputs are "on".
arithm.tic and logic unit -- The part .op a computer
arithmetic, logic, and similar operations.

~hat

oP
does

array -- An arrangement oP elements (such as numbers> usually
related in some fashion.

ASCII -- (American

Standard
Code
Por
Interchange),
an eight-level (7 bits +
conSisting of control and graphic characters .

InPormation
parity) code

• synchronous transmission-- Transmission in which information
characters arrive at irregular intervals of time (usually
bracketed by start elements and stop elements>.
(Contrast
with synchrongus transmission).
audio Pre~uencies -- Fre~uencies which can be heard by the
human ear (usually bet",een 15 cycles and 20 000 cycles pe~
second) .
".

'-

auto-call -- A feature that allows a terminal to initiate
call automatically over a switched (telephone) 1 in e.

TeXaS Instruments·

Gl ossa~y - 1

a

Pre 1 imi nar y

backup copy -- A copy or a rlle that is kept for reference in
case the original rile is destroyed.
BASIC (i2,eginner's AII-P,:,rposI!

~lJmb-o.lic Instruction ~ode) a
higher-level language,' similar in structure to FORTRAN but
somewhat easier to learn because or a 'smaller command
repetoire and simpler syntax.
~li
was invented at
Dartmouth College in 1963 and is probably the most popular
language ror personal computera.

batch processing - a technique ·or data procelsing in
Jobs are collected and grouped before processing.
thus are normally processed in a deferred mode.

which
Data

baud, baud rilte -- a measure of data transrer rate, equal to
the number of discrete conditions or signil1 events per
second.
(See bits per second).
binary digit (bit) -- the smallest unit of inrormation in the
binary 5.ystem Or notation.
bit ...;..- the abbreviation for binary digi1.
In the
notation, • bit is either of the characters 0 or 1.

binary

bit transfer rat.
the number Or bits transrerred per
time, usually expressed in bits per second (bps).

unit

bootstrap (to "bootH) -- to get a system running from a
,oldstart in a manner like "pulling oneself orf the ground
by tugging on ones bootstraps".
branch -- in programming, to make il
alternative choices of instructions.

selection

from

among

break -- a long space on an asynchronous communications line
that is intended to alert the receiving CPU.
Minimum
dur.1tion is one character time.
buffer -- a device or area or memory which is used to hold
something temporaril".
For example,
the screen bufrer
contains graphic informiltion to be displayed on the video
se reen.
buffering -- .

Lang 'J -3ge)- a programming
business data applications

Business-o"'i~nted

language designed
o~

~or

symbols

(bits)

~or

representing

data

compile -- to translate a computer program expressed in a
numan-oriented language into a computer-oriented language.
control character -- (1) A charcter whose occurrence in a
particular context controls the handling o~ data.
(~) In
the ASCII code, any o~ the ~ characters in the ~irst till a
columns o~ the standard code table.
CPS -- characters per second.
CPU (~entral ~rocessing ~nit)
unit 01 a computer that
includes
circuits
controlling the interpretation and
execution o~ instructions.
(

.I

crosstalk
the undesired
circuit to another.

trans~er

o~

energy

~rom

cursor -- a movable spot 01 light on the screen o~ a display
device, usually indicating where the next character will be
entered.
cyclic redundancy check (CRC) -- a method o~ error detection
which matches CRC characters generated by transmi tting and
receiving devices b.sed on the content 01 the Iftessag e a t
th at I ocat ion.
(Disk Control) Comparison o~ the checksum derived ~rom
data as it .as originally written into disk storage \&lith
the checksum derived ~rom the same data as it is being read
out of storage.
The first checksum is appended to the data
as it is \&Iritten to the disk.
Alter reading this data, the
controller computes a nelll checksum ~rom it and compares the
two.
I~
the checksums match,
the data is correct.
A
checksum error may indicate a damaged area on the disk,
data that has changed 51nce it was written, or .rroneous
reading o~ correct data where a retry may l.IIo:k.
cylinder in a disk pack, the set o~ all tracks with the
same nomi nal distance ~~om the axis about which the disk
pa c k rot. tes.
These tracks can be accessed
without
repositioning the access mechanism.
data -- a general term
Texas ·Instruments

~or

any type

Glossary - 3

o~

information.
Pre 1 imi nary

biJOSsary

movement
of
computer-encoded
of communications transmission

data

communications -- the
by
means
sy stems.
in~ormation

debug -- to ~ind and delete mistakes in computer programs
in other so~tware.

or

value -- the value chosen automatically by
computer when no explicit choice is made by the user.

the

de~ault

delimiter -- a character
elements of data.
diagnostic

separa tes

that

pertaining to the detection

or

organizes
a

mal~unction.

digital -- the representation or numerical quantities by
means o~ discrete integer numb.r!.
It is possible to
express in digital ~orm all in~orm.tion stored, transrerred
or processed bV a dual-state condition; •. g.,
ON/OFF,
(Contrast with analog).
OPEN/CLOSED, or TRUE/FALSE.
direct memory access (DMA) -- direct data transrer between an
I/O peripheral and memory, without computer intervention.
(Disk Control) - The technique generally used to trans~er
blacks of data b.tween a periph.ral and random-access
memor..,.
It is call.d direct b.cause the host does not
handle the data during the transrer op.,....tion.
directorv -- a 10gica11v organized data structure which holds
pointers to access data sets by sequential number or name.
displav -- a visual pr.sentation

o~

information.

double-precisian
using twa computer wards instead
to repr.sent a number.
downtime -- the time interval
inoperable due to a fault.

during

which

a

one

o~

computer

is

ElA (~lectronic Industries ~ssociation) -- The EIA Standard
RS-232-C derines interconnection inter~aces ~or terminals.
emulate -- to imitate one system with another such that the
imitating svstem accepts the same data and achieves the
same results as the imitated system.
EOF(end-0~-~i1e

record

o~

a

mark)·-- a code .which signiries that the last
has been read.

~ile

equalization -- compensation fan the
1 i ne.
FCC -- Federal
Texas Instruments

Communications

loss

or

Commi ss ion -- a

Glossary - 4

signal
board

in

a

or

PT'.liminaT'Y

Jai'1 21,

1993

Glossary

commissionel's having the powel' to.regulate all interstate
and 'ol'eign electl'ical communication systems originati'ng in
th e Un i ted Sta tes .

It

..

~ield

-- .n al'e. in a recol'd (see recol'd) tl'eated as a unit.

FIFO

Fil'st-In Fil'st-Out

'ile

a gl'OUp 0' l'elated records

memor~

bu~~er.
~andled

as a unit.

'il'mwal'e -- memol'Y chips with so'tware programs already built
in.
'lag -- a chal'actel' that lignals the
condition, such as the end 0' a wOl'd.

occurl'ence

or

some

'ol'egl'ound pl'oces.ing -- high-pl'iol'ity pl'ocessing,
usuall~
l'esulting 91'0111 1'.al-tim. entl'ies. given pl'ecedence by means
0' int el'l'U pts. oV.l' 10wel' p-ri 01' i ty. Mba c kgl' ound" p-r oces sing.

(

'ol'matting:
(Disk Cont1'ol) The division o~ tl'acks into
.ectol's to make it easiel' to ret1'ieve and update data.
In
each ••ctOl',
the block 0' data is preceded
by
an
identi9ying he.del'.
Gaps al'e insel'ted bet",een sectol's and
bet~en the headel' and data blocks ",ithin
each seetol' to
allow
time
~01'
cont1'ol
logic 'unctions and speed
'luctuations in the disk dl'ive .ssembly.
FSK('l'equency-shi't keying) -- a means 0' tl'ansmitting data
in which a "1" is l'ep,..esented as one 9requency and a "0" as
anothel' '1'equency.
Q

-- giga;

when 1'.'e-rl"ing to compute-r memo-ry it -represents 1
Othe-r",ise it is 1,000,000,000.

073 741 924.

global -- in pl'og-ramming, it is something that is de~ined in
one .ection 0' a p-rog-ram and used in at least one othel'
sec ti on.
gl'aphics -- symbols
nOl'mally
pl'oduced
by
handwriting,
dl'aCiling, o-r p-rinting.
Synonymous with gl'aphic symbol.
gl'aphic chal'acte-r -- a eharacte-r,
othe-r than at
co'nt-rol
chal'aetel', that i. nOl'mally -repl'esented by a g-raph-ic.
hal' duplex channel -- a communications line capable o~
t1'ansmitting in both di-rections, but not at the same time.
hal'dwal'e - phys ical equ ipment.
as opp osed to a computer
pl'ogl'am 01' method 0' use, e. g., mechanical. electrical.
magnetic, 01' elect-ronic devices.
hel'tz -- a unit Or
Ab b-rev iate d Hz.
Texas Inst-ruments

'-requenc~

equal to one cycle

Glossary

5

per

second.

Preliminary

wlan 21,

Glos sary

1983

.hexadecimal -- pertaining to
a
selection,
choic~,
or
condition that has 'sixt'!~n posslble values or states.
These values Dr states usually contain 10 diglts and 6
letters A through F.
Hexadecimal digits are e~uivalent to
a power of 16.
host computer
(Also
Just
"host") -- the
primary
or
controlling computer to which the terminal is connected by
cab 1e for c omm un i cat ion s.
identification characters -- characters sent by a station
a switched line to identify the station.

on

input/output (I/O) -- something that can be in an input
output process, either simultaneously or s~peratelv.

or

a
meaningful
instruction -- in a programming language,
expression that tells the computer to execute a specific
task.
instruction set -- the set of the instruction of
or languag e.

a

computer

integrated circuit -- a combination of interconnected circuit
elements inseperably associated on or within a continuous
sub strate.
integrated modem
a modem that is an integral part
device with which it operates.

of

intelligent terminal -- a synonym for a terminal that
programmable and can do. some. processing
. operations.
interface -- interconnection between two pieces of
having different functions.

the
is

e~uipment

interpreter -- a computer program that interprets programming
languages.
Synonymous with interpretive program.
inte.rrupt -- ~he temporary stopping of some phase of computer
operation caused by an event external to the operation.
Job -- a task submitted for a computer to do.
it usually
contains all necessary instructions,
files, and data to
C omp 1 e te the task.
Joystick -- a stick that is hand-held by the user and usually
is used to position something on the screen.
K -- an abbreviation for the prefi x kilo,
i. e.
1000 in
decimal notation.
In storage capacity, K -Frequently means
two to the tenth power which is 1024 in decimal notation.
I

Kb -- Ki lobyte.
Texas Instruments

Glossary - 6

Pre 1 imi nary

Jan 21, 1983

Olos sary

KHz -- Kilohertz.

a uni t of frequency equal to 1000 hertz.

LED (L1ght

Emitting Diode) -- a small solid-state
which emits light when a current is applied.

library -- a group

o~

d evi c e

related files.

light pen in computer graphics, a pen-like device that can
sense light.
When it is held up to a CRT it can be used to
identif~ displa~ elements.
line, communications -- describes cables,
telephone lines,
etc., ove,.. which data is transmitted to, and received ~,..om,
the terminal.
Also rePer,..ed to as the "line ll ) .
list -- to print or
listing

displa~

data.

a printout. usually of a program.

load -- to ent.", data into

memo,..~

machine language -- a language
machine.

0,.. into registers.

that

is

used

as

is

b~

a

~lat circuIa,.. plate
with a magnetizable
on !IIh ich dAtA CAn be stored by INgneti c
The disk .a~ be rigid 01" Plexible.

magnetic disk -- a

J:

(

sur~ac·e

la~e,..

recording.

mass sto,..age -- sto,..age having a

ve,..~

large storage

message -- in datA communications, an amount o~
that contains a p,...de~ined beginning and end.

capacit~.

in~ormation

modem (cont,..action o~ !!l.9.dulato,../demodulator).
a device
which mod~ates and demodulates signals t,..ansmitted over
communicationbs facilities.
The modulator is included ~or
t,..ansmission and the demodulator ~o,.. reception.
A modem is
used to pe,..mit digital signals to be sent over analog
lines.
Also called a data set.
modulation -- the process by which some characteristic o~ one
wave is varied in accordance !IIith another wave or signal.
This technique is used in modems to make computer signals
compatible with communications facilities.
mnemonic -- symbol or symbols
more di~Picult to remember.
til ree 1 ett ers.

'.

used
instead of terminologl,l
Usually a mnemonic has two or

multiplexing -- using a tran~mission line
different signals at one time.
NAND -- a logic operator.
Texas Instruments

to

The NAND of any two

Olossary - 7

carry

severa"!

statemen~s

P

Preliminary

Glo5stiry

and Q is ;alse i; and only i; both P and G are

t~ue.

nanosecond -- one-thousand-millionth 0; a second
noise -- undesirable disturbances in a communications system.
Noise can gene~ate er~o~s in transmission.
non-impact p~inte~s -- a printer in which printing is not the
~esult 0; mechanical imp .. cts;
e. g.
thermal printers.
obJect code -- output ;rom a compile~ or assembler which
itseI;
execut .. ble
m.. chine
code or is suitable
p~ocessing to produce executable machine code.
o;;line (local) -- describes the st .. te when equipment
devices are not connected to the communications line.

is
;o~

or

online -- descri~es the state when equipment or devices a~e
connected to the communications lines under control o~ a
processor either directly or through a
communication
system.
The phYSical connection can be accomplished by
either multiwire cable or a communications line.
open -- to prltpare a -Pile -POl' processing.

It.

g.

ed i t i ng.

operating svstem -- so-Ptware that controls the execution 0;
computer
programs
and
that -'v provide scheduling,
debugging, input and output control,
accounting,
storage
assignment,
data
•• nagement,
and
related
service.
Sometimes called Supervisor,
Executive,
Monitor, Master
Control Program depending on the computer manu;acturer.
parallel transmission -- method 0; data trans;er in which all
bits o-P a character or byte are transmitted simultaneously
either over separatlt communications lines or on di-P;erent
carrier -Prequencilts on the same communication line.
parameter -- a variable that is given a constant value
speci-Pic purpose or process.

;01'

a

parity check -- addition o-P non-in-Pormation bits to data,
making the number o-P ones in each grouping 0; bits either
always odd -POl' odd p.ritv or always even -POl' even parity.
A transmission error can then be detected by checking each
group 0; bits received -Par ~orrect parity.
password -- a word or string
0;
characters
that
is
recogniztilble by automatic means and that permits a user
access to protected storage,
;iles,
or input or output
devices.
program -- a
problem.
programs.

series
Al so,

Texas Instruments

ins tr u c t ion s wri t ten to
des i 9 n ,
wr i te,
and test

Glossary - 8

solve a
computer

Preliminary

.Jan 21, 1983

0105 sar~

protocol -- a for~l s.t of conventions or rules governing
the format, timing, and error control to ~acilitat~ message
.x~~nge bet~.en two communicating processes.

"

p.,.otect.d fi.ld
en te.,. datit.

it field into

wnicn

queue -- it lin. formed by items in a
p.,.oc.ssed .

the
system

operator

cannot

waiting

to

be

.,..cord -- it coll.ction of 'ields; the information .,.elating to
on. IIr.a o-Il activitv in a data p.,.ocessing activity, e. g.,
1111 infor.. ation on on. inventory
it.m.
Sometimes called
it ....
.,.elational charact.r -- II
~~a.,.acter
thllt
expresses
a
r.lationship
b.t .... n two operands.
Common relational
operators are> (greater than), < (less than), and- 
Double-density
Double-sided diskettes
DRIVE DIAGNOSTICS command

TECHNICAL REFERENCE MANUAL

~-~/~-5,~-14/~-5~,~-55/~-64

3-53
3-4~,3-43.3-44.3-45
~-49.~-57,3-~5.3-47

~-e5. ~-93
~-e9, ~-91, 3-~
1-1,~-e,~-5e,~-59,2-114,~-121/3-5

1-1,4-1
~-15,~-65
3-6~,3-66,3-69,3-70,3-71

~-107
~-11e,3-12,3-J6,3-62,3-63
~-55
~-5~
~-15, ~-65, ~-60
~-39.~-45,3-39,3-47,3-50,3-54
3-~e,

3-49,

3-~

3-7,3-14,3-15
~-e1, ~-83, ~-84
1-~,~13,2-38,2-84,3-35,3-58,3-61

2-38
1-1,~33,2-37,3-5,3-8,3-30, 3-56,~-1

1-1,2-2,2-40,2-43,3-11
1-1,~-33,2-e3,3-11

1-1,1-2,4-1
3-30,3-34,3-35
1-1,2-33,2-37,2-38
1-1,2-40,3-9,3-11
2-106

INDEX - 1

Preliminary -

Jan 21,

198~

J.naex

ECC

(e~~o~

E~ror

co~~ection

code)

~epo~ting

Error status byte
Expansion bus
Expansion RAM boa~d

~-90, ~-91, ~-9S

3-62,3-64
2-74,3-58
1-1,2-2,~-11,~-24,2-55,3-56

2-15,2-16

E
FDC (~loppy disk cont~olle~)
FLOTST (diskette d~ive test>
FLUSH KEYBOARD comnwand
FORMAT A TRACK comnwand
FORMAT ALTERNATE TRACK command
FORMAT BAD TRACK command
FORMAT DRIVE command
F o.rm.a tti n 9

2-7,2-33,2-37.~-57
~-39

3-38,3-47
3-69,3-70
~-101

2-95
2-92
~-10~,3-58.3-69

!:i

1
decoding
I/O timing
110 lII.it states
Index/secto~ hole
1/0

·Int.r~.cR p~otocol
Intl'~~.ces

~-10
~-31
~-18
~-42.2-137,3-62

3-50,3-51
2-11,3-2.3-4

Intl'rle.ve ~.cto~
Intl'rle .. ving
Intern.l modem
Intern.tion.l
Inte~rupt mask
Inter~upt system
INITIATE DRIVE CHARACTERISTICS

3-29.4-1
2-8,2-74.3-56.3-58
2-14
2-98

-.Joysticks

2-117,2-118

Keyboard

bu~~er

diagnostics
Kl'yboard DSR
Keyboard inte~~.ce
Keyboa~d m.pp ing
K.ybo.~d

K.ybo.~d

po~t

K.yb oard qul'u i ng
Keyc 1 ick
TECHNICAL REFERENCE MANUAL

2-81,~-83.2-88,2-92.~101,3-69

2-83
1-1, 1-2

3-37,3-39,3-47
1-2

2-45,2-94,3-5.3-36,3-40,3-47
3-3, 3-50,3-51
3-5,3-36,3-49
2-13
3-49.3-50
2-46,2-95,3-38

INDEX - 2

Preliminary - .Jan 21,

li7S

Index
"'.ycod.
b

2-45, 3-50,

L i gh t p.n
L.ithium b4itt.,.y
Logical add,..ss
Loopback

2-8,2-15,2-51,2-121
2-1120, 2-1~1
~-81. 2-134
3-1

Memo,.y add,..ssing
Memo,.y c:ont,.ol
M.mory c:ont,.ol st4it. mac:hin.
Memory ,..~,..s"
Memo,.y timing
MFM (modi~i.d '''.qu.nc:y-modu1ationJ
Moth.,.boa,.d •• mo"y

2-15,2-50
2-2,2-19,2-20,2-52,2-69,2-70
2-20,2-21
2-19,2-25,2-26,2-31
2-27
1-1,2-37,2-39
2-15,2-16,2-22

Option kit

4-1

3-5~

e.
PAL (p,.og,.4immabl. a,.,.ay logic)
Palette
Pa,..11.1 p,.int.".po,.t
Pa,.a11.1 t.st plug
Pix.l add,.essing
Pix.l att,.ibut.
Pi x.1s
Pl4in. (g,.aphic:s)
Pow.,.-good c:i,.cuit
Pow.,.-up s.1~-t.st
p,.ec:omp.nsation
p,.int.,. int.,.~ac.
p,. int.,. p o,.t
p,.int.,. po,.t OSR
p,.og,. am b ,..ale
p,.og,.am pause

2-33,2-34,2-5~,2-57
2-16,~-56,2-60.2-62,2-63

1-1,2-11,3-3.3-53,3-55,4-1
4-1, 5-1
2-64
2-6~

1-2,2-47,2-96,2-112,2-114,2-115
2-6~,2-63

2-4,2-5
2-39,2-46
2-33,2-37,2-38,2-39,2-99,3-59
3-55
2-2,2-6
3-53
3-5,3-49,3-50
3-5,3-49,3-50

Ii

\.

'--

RAM DIAQNOSTICS command
READ command
READ ECC BURST LENQTH command
Read-only memo,.y (ROM)
READ LONG command
READ SECTOR BUFFER command
TECHNICAL REFERENCE MANUAL

2-106
2-96
2-100
1-1. 2-19,2-69
2-107
2-105

INDEX - 3

I nde x

Technical Reference

keys
REGUEST STATUS command
R. ows

2-85,2-86.2-102,2-106.2-109
2-72,3- 5t2-20.2-49.2-bS,2-118.3-b.3-12
2-45,2-94.3-38.3-47
2-85
2-51, 3-18

S c r 0 lId 0 IIJn
Scroll up
Scrolling
SOLC (synchronous data-link control)
Sector bu~~er
Sector bu~~er modes
St?ctor not ~ound
Sector interleaving
Sectors per track
SEEK c ommlilnd
SeH-dililgnostics
Self-test
SENSE BYTES RETURNED
Software-interrupt
Sp ea k er
Sync-liIsync comm board
System unit board
System timing

3-20
2-99.3-20
2-50,2-99.3-2.3-19.3-49
2-68
2-33.2-139,2-151
2-34
3-63
2-83
2-133
2-97
2-45.2-94
2-38,2-46,2-107
2-86
3-50
2-6.2-13,3-3,3-14
1-2.2-9.2-108,4-1
1-1,2-2,2-8,2-38,2-43,3-7
2-13 .

DRIVE command
aS51gnment

~ECALIBRAT~
~egi5ter
?

eg is t ers

~epeat-actlon

I
Tilt bar
Time-of-day clock
Type-ahead buffer

1-2
3-5,3-14
3-38,3-47,3-50,3-51

UL listed (blilttery)
• 2-121
USART (universal synchronousasynchronous r.ceiver-trlilnsmitter) 2-7,2-13,2-15,3-5

VCO (voltage oontrolled oscillator)
Vectors

TECHNICAL REFERENCE MANUAL

2-33,2-37
3-1,3-36.3-48,3-50,3-61

INDEX - 4

Preliminary - Jan 21.

1983

Technical

Index

Refe~ence

cont~olle~ commands:
CHECK TRACK FORMAT
CONTROLLER INTERNAL DIAGNOSTICS
DRIVE DIAGNOSTICS
FORMAT ALTERNATE TRACK
FORMAT BAD TRACK
FORMAT DRIVE
FORMAT TRACK
INITIATE DRIVE CHARACTERISTICS
RAM DIAGNOSTICS
READ
READ ECC BURST ERROR LENGTH
READ LONQ
READ SECTOR BUFFER
RECALIBRATE DRIVE
REGUEST STATUS
SEEK
SENSE BYTES RETURNED
WRITE
WRITE LONQ
WRITE SECTOR BUFFER
Wincheste~ DSR
Wincheste~ ROM
WRITE comm_nd
WRITE LONG c:omm.nd
Wincheste~

W~ite-p~otected

WRITE SECTOR BUFFER comm_nd

:2-93
2-107
:2-106
:2-101
:2-95
:2-9:2
:2-94
:2-99
:2-106
:2-96
:2-100
:2-107
:2-10~
:2-8~
:2-8~

:2-97
:2-86
:2-96
:2-109
:2-105
3-5~h 3-62
3-58,3-65
2-34,:2-9612-103
:2-108
2-4:2,:2-43
:2-105

,Z-flag

TECHNICAL REFERENCE MANUAL

INDEX - 5/6

P1' elim i n.1' y -

Jan 21,

i 98:
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