223 2721 0_7094_II_CE_Instruction_Maintenance_Vol1 0 7094 II CE Instruction Maintenance Vol1

223-2721-0_7094_II_CE_Instruction_Maintenance_Vol1 223-2721-0_7094_II_CE_Instruction_Maintenance_Vol1

User Manual: 223-2721-0_7094_II_CE_Instruction_Maintenance_Vol1

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Customer Engineering
Instruction -Main tenance

7094 II Data Processing System-Volume 1
Introduction
Component Circuits
System and Functional Components
Timing

Customer Engineering
Instruction-Maintenance

7094 II Data Processing System-Volume 1
. Introduction
Component Circuits
System and Functional Components
Timing

Preface

Safety

This manual contains four sections: IBM 7094 II Data
Processing System, Component Circuits, System and
Functional Components, and Timing.
The purpose of these sections is to:
1. Introduce the 7094 II system.
2. Describe the various circuit cards and circuit configurations.
3. Explain briefly the purpose and operation of the
various system components (such as the multiplexor,
core storage, data channels, etc.), and internal functional components (such as registers, adders, counters,
etc.).
4. Explain the 7094 II timing and cyclic makeup.
Customer Engineers who are familiar with the 7094
system may easily skip over the first section by reading
only the portion on Instruction Overlap.
Condensed logic diagrams used in this manual are as
close to actual systems as possible. Most of these diagrams have been converted to positive logic by eliminating any references to + or - levels. In maintaining
this positive logic, in-phase outputs are used to indicate
an active (conditions met) state from the condensed
logic block. Out-of-phase outputs are also used in some
cases to simplify the diagrams by eliminating the cluttering effect of convert and invert blocks.
The material in this manual is written at engineering
change level 253407; however, future engineering
changes may change the logic and machine operations
from the presentation in this manual.
The following manuals pertain to the 7094 II system:

The follOwing safety practices should be observed:
l. At least two men should be within sight of each
other when working on a machine with power on.
2. Safety glasses must be worn when soldering or
performing other operations which may endanger the
eyes.
3. Use caution when lowering a tailgate. Keep fingers clear of gate slides when sliding a gate into a module. Avoid hitting laminar bus connections.
4. 120 volts, 60 cycles, and 48 vdc are still present
inside SMS frame with frame power off and 7618 power
on. If it is necessary to work near live power connectors, convenience outlets, or inside the MG unit or core
storage control, disconnect power cables, or turn off
wall circuit breakers.
5. Discharge capacitors before working on DC
power supplies.
6. Always turn off power before replacing a fuse.
7. Replace safety covers that have been removed
before proceeding to another operation.
8. Prior to servicing, note and check the following
items:
Master power switch location ________
Air conditioning switch location _______
Fire extinguishers (C02 type )_ _ _ _ _ _ __
Emergency exit doors 10cationL-_ _ _ _ _ __
Fire control phone number_ _ _ _ _ _ _ __
First aid phone number _ _ _ _ _ _ _ _ __
9. Remove metal jewelry before servicing the computer.

FORM

223-2721
223-2722
223-2723
223-2724
223-6910
223-2551

TITLE

7094 II DPS CEIM Manual Volume 1 (Introduction, Component Circuits, System and Functional
Components, and Timing)
7094 II DPS CEIM Manual Volume 2 (Arithmetic
Instructions)
7094 II DPS CEIM Manual Volume 3 (Non-Arithmetic Instructions, Overlap, Trapping, Compatibility, 7151-2 Console)
7302-3 Core Storage CEIM Manual
7607 Data Channel CE I-R Manual
7909 Data Channel CE I-R Manual

Copies of this and other publications can be obtained through IBM Branch Offices.
Address comments concerning the contents of this publication to:
IBM Corporation, CE Manuals, Dept. B96, PO. Box 390, Poughkeepsie, N.Y. 12602.

© 1964 by International Business Machines Corporation

Contents

IBM 7094 II Data Processing System . ............. .
COMPUTER WORDS. .
...
. . . . . . . . . . .. . ..
Data Word ....................................... .
Instruction Word . . . ..
Instruction Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Direct Address.
Effective Address.
Indirect Addressing ..
7607 Data Channel Command Word.
7909 Data Channel Command Word.
INSTRUCTION OVERLAP ....... .
BINARY ARITHMETIC .... '.
. ...... .
Octal Number System .............................. .
Addition . , . . . . . . . . . . . . . . . . . . . . .. ............ .
Subtraction .....................
. ......... .
Complement Method. .
. ...... .
l's Complement ................. .
2's Complement ....... .
Signed Number ................. .
Multiplication ........................ .
Division ......................................... .
Component Circuits . ................. .
BASIC D1F CIRCUIT OPERATION ............ .
AND-Invert .. . . . . . . . . . . . . . . . . . . . . . . . ..
oR-Invert ........................... .
AND-oR-Invert ................... .
D1F CIRCUIT LOGIC BLOCKS. . . . . . .
...........
Micro and Macro Blocks ................. .
AND-OR-Invert ............................... .
D1F (F-Level) Triggers. . . . . . . .
. ...... .
+AOI Trigger ................................... .
-OAI Trigger. . . . . . . .
. ................. .
IBR Trigger ................... .
Shift Cell-sc. . . . . . . . . . . . . . . . . . . .
DOT-oR'ing and AND'ing.
COMPONENT CIRCUITS CARD TYPES .... .
SMS Single Card. . . . . . . . . . . . . . . .. .
SMS Twin Card ..
SMS STAN-PAC Card ................... .
D1F CIRCUIT SPECIFICATIONS. . . . . . .
D1F Logic Block .....
Logic Block Input Specifications.
Logic Block Output Specifications.
Logic Block Circuit Delays .....
Logic Block Power Supply Requirements ............ .
Logic Block Extended Capabilities.
D1F Indicator Driver ....
Indicator Driver Input SpeGifications. . . . .
Indicator Driver Output Specifications ...... .
Indicator Driver Power Supply Requirements .. .
N-Line to D1F Converter-Terminator.
N to F Converter Input Specifications ............... .
N to F Converter Output Specifications ............. .
N to F Converter Delays .......................... .
Power Supply Requirements ....................... .
P-Line to D1F Converter-Terminator. . . . . .
. ........ .
P to F Converter Input Specifications ............... .
P to F Converter Output Specifications. . . . . . . . . . . . . . .
P to F Converter Delays. . . . . . . . . . . . . . . . . . . . . . . . . ..
P to F Power Supply Requirements ................. .
D1F to N-Line Converter-Driver.
. ........... .
F to N Converter Input Specifications. . . . . . . . . . . . . . . .
F to N Converter Output Specifications . . . . . . . . . . ....
F to N Converter Delays. . . . . . . . . . . . . . . . . . . . . . . . . . .
F to N Power Supply Requirements ................. .

7
8
8
9
9
9

9
10
10
11
11
11

13
13

14
14
15
16
16
16
17
18
18
18
19
19
20
20
20
20
21

22
22
22
23

24
24
24
24
27
27
27
27
27
27
27
28
28
28
28
28
28
28
29
29
29
29
29
29
29
29
30
30
30
30

D1F to P-Line Converter-Driver. .. . ................
F to P Converter Input Specifications ...............
F to P Converter Output Specifications ..............
F to P Converter Delays.
. ...................
F to P Power Supply Requirements .................

.
.
.
.
.

30
30
30

31
31

System and Functional Components . ............. . 33
SYSTEM COMPONENTS. . .
. ..................... . 33
7111 and 7109 Central Processing Units ............... . 33
7606 Multiplexor. . . . . . . . . . . . . . . . .. . .............. . 33
Multiplexor Storage Busses ........................ . 34
Multiplexor Storage Bus oR'ing ..................... . 34
Buffer Address Register. . . . . . . . .. . . . . . . . . . . . . . . . . . . 34
7302-3 Core Storage ............................... . 34
7302-3 Addressing ............................... . 36
Input-Output ..................................... . 36
7607 Data Channel ................................ . 36
7909 Data Channel ................................ . 37
7151-2 Console Control Unit ........................ . 37
7608 and 7618 Power Control Unit ................... . 37
FUNCTIONAL COMPONENTS ........................... . 38
Storage Register-sR ............................... . 38
Accumulator Register-AC .......................... . 41
Multiplier-Quotient Register-MQ. . . . . . .. . .......... . 42
Sense Indicator Register-sl ......................... . 42
Instruction Backup Register-IBR .................... . 43
Tag Register-TR .................................. . 44
Address Register-AR .............................. . 44
Program Counter-pc .............................. . 46
Index Registers-xR ................................ . 47
Program Register-PR .............................. . 47
Shift Counter-sc ................................. . 48
Stepping the Shift Counter. . . . . . . . . . . . . . . . . . . . . . . . . 48
Main Adders-AD .................................. . 52
Individual Main Adder Position .................... . 52
Main Adder Bit Carry Lookahead .................. . 52
Main Adder Group Carry Lookahead ............... . 53
Q Carry Lookahead .............................. . 57
Index Adders-xAD ................................ . 58
Index Adder Position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Index Adder Bit Carry Lookahead .................. . 59
Index Adder Group Carry Lookahead ............... . 59
Index Adder 3 Carry ............................. . 59
Index Adder Compatibility ........................ . 59
SR Zero Check ..................................... . 63
Memory Selection Circuits .......................... . 63
MAR Switching and Address Controls ................. . 64
Timing .......................................... .
MASTER CLOCKS AND PULSES ......................... .
CPU Clock Pulse Distribution. . . . . . . . . . . . . . . . . . . . .... .
cpu-l A and B Gate Clock Pulse Designation ........... .
CP Set Pulse Generation and Distribution .............. .
MACHINE TIMING CYCLES ............................ .
Master I Time .................................... .
Address Gating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Counter Update ......................... .
Storage Bus Gating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Modification ............................. .
N ext Machine Cycle ............................. .
Master E Time .................................... .
IA E Cycle ....................................... .
Master L Time .................................... .
Master II Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master B Time .................................... .
B Cycle .......................................... .

66
66
70
70
72
73

74
76

77
77
78
78
82
82
86
86
87
89

Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Cycle ........................... '.' . . . . . . . . ..
Indirectly Addressed BCW Cycle. . . . . . . . . . . . . . . . . . . ..
TCH Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Indirectly Addressed TCH Command. . . . . . . . . . . . .
Channel Cycle Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Channel I Time ................................. ,
Channel E Time. '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Channel L Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Channel-cpu Cycle Time Controls. . . . . . . . . . . . . . . . ..
Multiple Cycle Time Error Detection. . . . . . . . . . . . . . . . ..
BDW
BCW

WAVEFORMS AND VARIABLE DELAY ADJUSTMENTS. . . . . . . . ..

Initial Delay Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Odd and Even Clock Drive Pulses. . . . . . . . . . . . . . . . . . . ..

89
89
89
90
90
93
93
93
93
93
95
95
95
96

Set Pulses ..................................... '. .
cpu-l CP Set Pulse Width Adjustment. ................
CP Set Pulse--Clock Pulse Alignment. . . . . . . . . . . . . . . . ..
CPU and Channel Memory Select Alignment. . . . . . . .
Memory Select and MAR Bus Alignment. . . . . . . . . . . . . ....

96
96
96
97
97

Appendix A: Octal-Decimal Integer Conversion
Table ...... .. , ......... , .. ... .... ........

98

CP

Appendix B: Octal-Decimal Fraction Conversion
Table . ................. , ...................... 102
Appendix C: Table of Powers of Two. . . . . . . . . . . . .. 105

Illustrations

FIGURE
TITLE
PAGE
I ntrod uction
1 General Computer Functional Arrangement ..
7
2 7094 II Data Word ............................. .
9
. .............. .
3 7094 II Instruction Word. .
9
4 Instruction Word Address Modification Fields ...... .
9
5 Instruction Word Count Fields. . . . . . . . . . . . . . . . . . ..
9
6 Data Channel Command Word ......... .
10
7 7909 Command Word Formats ........ .
11
8 Double Instruction Overlap .... .
12
9 Extended Sequence Overlap ..................... . 12
Component Circuits
10 +AI (-01) Circuit .................. .
11 +AND, -OR Circuit.
12 +01 (-AI) Circuit ......... .
13 +OR, -AND Circuit.
14 AND -OR-Invert Circuit
15 Macro and Micro Blocks.. . ....... .
16 Systems Logic vs Condensed Positive Logic
Gating Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . ..
17 + A01 Trigger . . . . . . . . . . . . . . . . . . .
...... ..
18 -OAI Trigger. . . . . . . . . . . . . . . .
. ........ .
19 IBR Trigger ...................... .
20 Shift Cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21 Shift Cell Timing Chart ........... .
22 DOT-oR'ing and DOT-AND'ing ............. .
23 Twin-Card Locations for SR, AC and MQ Input Gating.
24 Twin-Card Locations for SI, IBR, XAD and XR ....... .
25 BDS Card Locations for SR, AC, MQ and AD.
26 Typical BDS Card Layout.
27 DIF Logic. . . . . . . . . . . . . . . . . . . . ..
28 DIF Indicator Driver ...... .
29 N-Line to F -Line Converter ...
30 P-Line to F -Line Converter. . . . . . . . . . . .. . ...... .
31 F-Line to N-Line Converter.
32 F-Line to P-Line Converter ....

21
21
22
22
22
23
23
24
25
25
26
27
28
28
29
30
30

System and Functional Components
33 7094 II System Configuration .................... .
34 Basic Functional Organization ..
35 Multiplexor Data Flow .................. .
36 7094 II Power Distribution. . . .
. ...... .
37 7094 II CPU Data Flow . . .
. ......... .
38 Storage Register Position 17. . . . . . . . . . . . . . . . . . . . . .
39 Accumulator Position 17. . . . . . .
...............
40 MQ Position 17. . . . . . . . . . . . . . .
...........
41 Sense Indicator Position 17 ...................... .
42 IBR Position 17. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
43 Tag Register Position 18 ................. .

32
33
35
38
39
40
41
42
43
43
44

18
19
19
20
20
21

FIGURE
TITLE
PAGE
44 Address Register Position 17. . . . . . . . . . . . . . . . . . . .
45
45 Program Counter Position 17 .................... . 46
46 XRA Position 17. . . . . . . . . . . .
47
47 Program Register Position 9.
. ................ . 47
48 Operation Decoding. . . . . . . .
. . . . . . . . . . . . . . . . . 48
49 Shift Counter Stepping ......................... . 49
50 Shift Counter Timing Chart. . . . . . . . . . . . . . . . . . . . .. 51
51 Main Adder Position 35 ......................... . 52
52 Group 1 Adder Carry, Generate and Propagate ..... . 54
53 Group 2 Generate and Propagate Lookahead ....... . 55
54 Main Adder Group Lookahead and Q Carry ........ . 56
55 Index Adder Routing. . . . . . . . . . . . . . .-. . . . . . . . . . . . . 58
56 Index Adder Positions. ... . . . . . . . . . . . . . . . . . . . . . 60
57 Group 1 Index Adder Bit Carry and Lookahead .... . 61
58 Index Adder Group Lookahead and XAD( 3) Carry ... . 62
59 SR Input Zero Check. . . . . . . .. . .......... .
63
60 Memory Select Circuitry. . . .
. .......... .
63
61 Program Counter MAR Bus Selection ..
64
62 MAR Bus Selection and Switching ................ . 65
Timing
63 Master Clock Logic.
64 5.71 MC Oscillator Output ...
65 Oscillator Output and Even Clock Drive .. .
66 CPU and Channel Cycle Relationship .............. .
67 CPU and Channel Clock Outputs and Controls. . . . . . .
. . . . . . . . . . . ..
68 CPU Clock Sequence Chart
69 Channel Clock Sequence Clrart. ................ .
70 CPU Clock Pulse Distribution. .. . .............. .
71 CPU Clock Pulse Designations and Usage. . . . . . . . . . .
72 CP Set Pulse Distribution ....................... .
73 Cycle Time Relationship ........................ .
74 I, E, and L Time Cycle Logic.
. .............. .
. .................. .
75 I Time Flow Chart. .
76 SB Gating Decision Chart.
. ................. .
77 IA Flow Chart. . . . . . . . .
. ............. .
78 Inhibit L Trigger Logic. . .
. ......... .
79 II Time Condensed Logic. .. . ........ .
80 B Time Condensed Logic ....................... .
81 B Time Sequence Chart ........................ .
. ................. .
82 B Time Flow Chart.
83 Channel Cycle Time Logic ................... .
84 Multiple Time Check Circuitry .................. .
85 Clock Drive Pulse ............................. .
86 Even and Odd Clock Drive Pulses ................ .
87 CP Set Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .
88 CP Set Pulse-Clock Pulse Alignment. . . . . . . . . . . . . .
89 Memory Select Pulse Alignment .................. .
90 Memory Select-MAR Bus Alignment ............. .

67
68
68
68
68
68
69
71
72
73
74
75
79
78
85
86
86
87
88
91
94
95
96
96
96
96
97
97

• j:.

;1..
.. ". 'J."1

• •

.
'.'

••

'."

•

.• '

~_\i~ "

. • .

7094 n Data ProCeSsing System

"

Jid~..
J

~';"
... ......
... :.~,
... ~~,
.. ~~
...
"..,
. " , >.
~
""~
~,.
'

...

• • •

',,:;;"

.

",'

.,'
••••• "
.. . " ) I . .
q

Ii,

 Subtrahend

-011
-010
- 001

011
011
000

Minuend
Subtrahend
Difference

100
010
110

100
011
III

Minuend complement
Subtrahend
Complement of difference

Minuend> Subtrahend

+011
- 010
+ 000

011
101
110

Minuend
Subtrahend
Difference

Minuend

011 011
101 010
000 101
With a 1 end carry 1
000 110

Minuend
Complement
Difference - 1
True difference
Introduction

15

same. The last requires the extra step of end-around
carry, which is a carry from the highest order around to
the lowest order. This carry is required because of the
cyclical nature of the number system.
The only time it is required is when the minuend is
larger than the subtrahend, that is, when the answer
will come out a true positive answer. Fortunately,
whenever it is required, there is a carry from the leftmost position, which serves as a reminder.
2's Complement

In the derivation of the complement system, it was
shown that a 2's complement of a number is equal to
the modulus minus the number, (M - N). Therefore, to
obtain a 2's complement in a six-place machine, the
number is subtracted from the modulus, 1 000 000. As
an example, find the 2's complement of the numbers
101 001 and 001 101:
aDO
101

1

010

ODD
.00'1
III = 2's Complement 110

000 = Modulus
00'1 = Number

1

000 = Modulus
101 = Number
all = 2's Complement

An examination of the numbers and their complements
shows that the 2's complement of a number is the same
as the 1's complement with a 1 added to it. The 2's complement is therefore formed by obtaining the 1's complement and adding 1 to it. For example, to form the
2's complement of 001101:
0'0'1
110'

110

101 = Number
OlD = 1's Complement

010 = l's Complement

+1
110'

on =

2's Complement

To perform subtraction by the 2's complement
method:
l. Find the 2's complement of the subtrahend.
2. Add this complement to the minuend.
The result is the difference in complement form if it is
negative and in true form if it is positive. In the 2's complement system, there is no need to end-around carry.
Signed Numbers

How can negative numbers in complement form be
distinguished from positive numbers in true form? In
this regard, also, binary numbers offer an advantage
with respect to representation. The sign of a number is
binary in nature; th:at is, a number is either positive or
negative. Thus, a bit representing the sign can be used
in addition to the bits representing magnitude. A 0 in
the sign bit position can be interpreted to mean that
the number is positive. A 1 in the sign bit position can
be interpreted to mean that the number is negative. By
treating the signs separately from the magnitudes in
each operation, the result sign can be predicted. Therefore, the rules of algebra apply in determining the result sign.
16

Multiplication

The rules for binary multiplication are similar to those
of decimal multiplication. The rules for multiplying
two single digits are the same in both systems. These
rules are:
DXD=D
DX1=D
1xD=0

1x1=1

The general procedure when multiplying two multiple
digit binary numbers is the same as that in decimal
arithmetic. That is, the multiplicand is multiplied by a
digit of the multiplier, and the partial product obtained
is placed so that the least significant digit is under the
multiplier digit. When all the partial products have
been found, they are added together to find the final
product. The only difference between decimal and binary multiplication, therefore, is in the summing of the
partial products. In binary, the binary addition table is
used while in decimal, the decimal table is used.
As can be seen from the following examples, the
method of obtaining partial products and then adding
them to obtain the final product is identical to that of
decimal arithmetic.
Multiplicand
Multiplier
First partial product
Second partial product
Third partial product
Fourth partial product
Final product

10'10

10'.11

1101
1010
0000
1010
1010
10'000010

100.1
1011
0000
0000
1011
1100'.011

1111
1111
1111
1111
1111
1111
11100001

Note the placement of the binary point in the second
example. The same rules hold for its placement as
hold for placement of the decimal point in decimal
arithmetic.
The third example also illustrates an interesting
point. This is the multiplication of the two largest possible 4-bit numbers. The product is 8 bits long. In other
words the largest product that can result from the multiplication of two numbers will be no longer than the
sum of the number of bits in the multiplier and multiplicand.
If a number is multiplied by the radix of the number
system, this multiplication has the effect of shifting the
number one place to the left with respect to the radix
point. This is true in any number system. For example,
multiply 12.51 10 by 10 (the radix of the decimal system)
and multiply the number 10.112 by 2 (the radix of the
binary system):
Number
Number times radix

12.51
125.1

10.11
101.1

Binary multiplication, then, is nothing more than a
series of add and shift operations. An example of such
an operation is given under Fixed Point Arithmetic in
Volume 2.

Division

Binary division is the process of counting the number
of times a divisor goes into a dividend. The count of
the number of times the divisor may be subtracted
from the dividend before a negative remainder occurs
is called the quotient.
Direct binary division is performed by a series of
subtractions of the divisor (actually a multiple of the
divisor), just as it is in the decimal system. For example, divide 100011100 by 1110:
(bd ehi jk)

10
1 110 }100 011
(a)
11 10
(c)
111
(f)
111
(g)
(1)

(m)

100.01
100.00
1
0
100 00
..1l...lQ.
10

In the example, the first step is to place the divisor
below the dividend in a position which is as far removed to the left as possible (a), but which will allow
a positive difference to result when the divisor is subtracted from the dividend. Since the divisor will go
into this many bits of the dividend once, a 1 is placed
in the quotient at b in the same column as the lowest
order digit of the divisor. The divisor is then multiplied
by the quotient digit, and the resulting product is subtracted from the dividend to produce the positive difference (c), called the current remainder. The next
digit in the dividend is brought down to the line c.
Compare the divisor to line c; note that the divisor is
larger than line c, or that the divisor goes into line c
o times. Therefore, place a 0 in the quotient at the d
position. The next digit of the dividend is then brought
down to line c. Comparing the divisor to line c shows
line c to be greater. Place a 1 in the quotient at the e

position. Multiply the divisor by the last quotient bit to
form line f. Subtract line f from line c to start line g.
The next digit in the dividend is brought down to line
g. Compare the divisor to line g; the divisor is greater,
so place a 0 in the quotient at position h. Bring the next
digit of the dividend down to line g; by comparison
line g is still smaller than the divisor. Place a 0 in the
quotient in position i, and place the next dividend digit
on line g. Still, line g is smaller than the divisor, so a 0
is placed in the quotient at position j. Placing the next
dividend digit on line g now makes line g greater than
the divisor. Place a 1 in the quotient at position k, and
multiply the divisor by this 1 to form line 1. Subtract
line I from line k to start line m. Assuming a quotient
has been developed of sufficient length, terminate the
operation. The quotient is 10 100.01 with a remainder
of 10 (line m).
Since the quotients bit is always either 0 or 1, the
division process can be reduced to a series of subtractions of the divisor, multiplied by the power of the quotient bit being sought from the dividend. Each time a
subtraction results in a positive current remainder, a
1 is placed in the corresponding quotient bit position,
and the process is immediately repeated for the next
quotient bit. Each time the subtraction results in a
negative remainder, a 0 is placed in the corresponding
quotient bit. In this case, the current remainder is
restored to a positive number by adding the divisor
back to it. Following this, the next quotient bit is obtained by the subtraction of the divisor multiplied by
the power of the next quotient bit.
Since the quotient bits are generated from left to
right, the power of each quotient bit is one smaller than
that of the last bit generated. This means that as the
divisor is successively subtracted from the dividend (or
current remainder), the divisor is shifted to the right in
relation to the binary point. The division process can
therefore be reduced to a process of successive subtract
and shift steps. An example of such a process is given
under Fixed Point Arithmetic in Volume 2.

Introduction

17

Component Circuits

+3v

All logic in the A and B gates of CPU 1 (7111) is composed of DIF (DIode Feedback) circuitry. This new Flevel circuitry is of the non-saturating type and provides the three basic logical functions of AND, OR, and
invert. A collector-to-base diode feedback network prevents transistor saturation and, therefore, allows highspeed circuit operation. Voltage inversion always occurs between the input and output.

+6v

AND
Output
Input 1

Basic DIF Circuit Operation
Three logical functions are performed by the DIF circuit block: AND'ing, oR'ing, and inverting. Other functions are also performed such as terminating, driving,
and converting from one voltage level to another, but
these are only "convenience" functions, not logical
functions.
DIF circuitry allows both the AND and OR logical functions to be performed within the same logic block before output powering and inversion. Not all logic blocks
contain both functions, however; some produce just
AND'ing, others just oR'ing, while others are simply
inverters.
AND-Invert

The two-legged circuit shown in Figure 10 represents
either a + AI or -01 function. The circuit configuration
for the + AND and -OR are identical. The polarity designations are adapted to work in negative logic; that is,
the recognition of the absence as well as the presence
of information. The +AI circuit requires that all inputs
must be up (+3 volts) to obtain a down-level output
(0 volts).
Note that even though this circuit represents only an
AND function; an OR diode, D3, is also included. This
one-legged OR circuit serves no logical function, but is
always a part of the +AI configuration.
Figure lla shows the junction point of the two input
AND diodes. Only two inputs are shown in this case-three or more could also be used. The resistor (Rl)
limits the current How and controls the rise time of the
output.
If both inputs are at 0 volts (Figure lIb), the polarity is correct for both diodes to conduct. The resultant
current How through Rl causes a voltage drop across it
to maintain a level of about 0 volts. (Consider the forward resistance of the diode to be insignificant.)
18

Input 2

Input 1
Input 2

I

,

I

I

I
'+3v

Output

!

I
lov

Figure 10. +AI (-01) Circuit

If input 1 rises to +3 volts (Figure llc), Dl is cut off
because the cathode is more positive than the plate.
D2, with 0 volts on its cathode, maintains conduction
and the output remains unchanged.
When input 2 changes to +3 volts (Figure lId), D2
is cut off momentarily. The junction voltage starts rising
towards +6 volts with a rise time effected by the stray
capacitance of the associated circuitry. As the junction
reaches 3 volts, both diodes return to conduction as a
final steady state condition. If the input signals are not
of the same voltage levels, the junction voltage assumes
the lowest of the input sources.
When input 1 falls to 0 volts (Figure lIe), Dl conducts harder, D2 is cut off, and the output follows the
input down to 0 volts. When input 2 falls to 0 volts, D2
goes back into conduction to help maintain the 0 volt
output level.
At the output of every DIF logic circuit is a powering
transistor which automatically causes a voltage inversion. When all inputs are down (0 volts), the base-toemitter voltage keeps the transistor out of conduction.
In this condition, the output signal level is essentially
at that of the collector power source, +3 volts.

When both inputs 1 and 2 are at +3 volts, for example, diode D3 conducts and causes the voltage at the
base of the transistor to go more positive. In this condition, the transistor conducts and the output signal is
essentially that of the transistor emitter, 0 volts.
If the active logical input lines are represented as
plus (+3 volts) levels, the active logical circuit output
is a minus (0 volt) level (Figure 10). If this output is
fed into a-AND or -OR circuit, however, the inversion
was not a "logical" inversion.
Diode D4 in the OR circuit performs a resistance
function only and does not affect the logic. D5 is the
diode which clamps the collector at a more positive
voltage than if the transistor were allowed to conduct
fully. By preventing the transistor from going into saturation, better waveshapes are produced to allow faster
computer operation.

Note that even though this circuit represents only an
OR function, two corresponding AND diodes (D3 and
D4) are included. These one-legged AND circuits serve
no logical function, but are always a part of the +01
configuration.
Figure 13 shows the junction point of the two input
OR diodes (D5 from Figure 12 has been eliminated at
this time). If both inputs are at 0 volts (Figure 13b),
the polarity is correct for both diodes to conduct. The
voltage drop across the current limiting resistor (R2)
sets the correct output level-for explanation purposes,
ovolts.
If either input rises to +3 volts (Figure 13c), that
circuit leg conducts harder. The other diode cuts off
and the output follows the input to +3 volts.
Normally only one input is active at anyone time.
The junction voltage, however, tends to follow the
highest of the input signal levels.

OR-Invert

The two-legged OR circuit shown in Figure 12 represents either a +01 or -AI function; both differ in logical function but are identical in circuitry. The +01 circuit produces a down-level output (0 volts) if anyone
of the inputs is up (+3 volts). This inversion, as explained previously for the AND-invert, is caused by the
output powering transistor.

+6v

AND-OR-Invert

Figure 14 shows the previously explained AND and OR
functions combined into a typical DIF + AOI circuit.
This circuit, too, can be considered as a -OAI depending on either the inputs available, or the output level
desired. For example, if a minus (-) output level is
desired, a +AOI designation would be used; if a plus
(+) output level is desired, a -OAI would be applicable.

+6v

Rl

Rl
ANO
Output

Input 1

Ov

Input 2

Ov

01

J-

02

.Jt

(0)

AND

Ov

+6v

INVERT

+3v

R3

(b)

Input 1
+6v

I
- - - - AND- -:(;:--,

+6v

I

Rl

+3v

Ov

Rl

Ov

01

01

-

Rl

+3v

~

02
+3v

I
N

I

Input 2

(c)

Output

I
I

+3v

02

D6

I

(d)

N

R2
+6v

Rl

}

Ov

-3v

Input 1

Ov

-.-J

Input I

I

Input2~
I

1+3v

+3v

~~----~~----­
~

Input 2

I
I

ANOOutPut~

Output

I

I

I
I

I
I

~

(e)

Figure ll.

+ AND, -OR Circuit

Figure 12. +01 (-AI) Circuit
Component Circuits

19

Ov

Input 1

D4

Ov

OR Output
Ov

Input 2
(To Transistor Base)

R2

R2

(a)

(b)

-3v

-3v

+3v

Input 3

+3v
~~~--~~

Ov

---.J

I

Input4~
I

R2

(c)

I

~

OR Output ~~---

. ~

-3v

Figure 13. +OR, -AND Circuit

DIF Circuit Logic Blocks

1. Two 2-way AND'S,
2. Three 2-way AND'S,
3. 3-way and 2-way AND,
4. 3-way and I-way AND, etc.
In cases of negative logic (or because of the availability of signal lines ), a +AOI can be represented by a
-OAI. In either case, the internal circuitry is identical;
only the final active output level will be changed.
The +AOI circuit is used in many cases to "gate" information into registers. In these cases the +AOI is replaced by a G within the circuit block.
Most circuit diagrams shown in this manual are condensed ALD systems with logic converted to positive
(active) logic. Figure 16 shows at comparison of systems logic (a) and condensed positive logic (b). Note
that the condensed logic is not concerned with voltage
levels, only active logical levels. The out-of-phase (inverted) output of the systems gating circuit feeds a
-sc; therefore, the inversion is not a logical inversion.
Because there is no logic to the inversion, the condensed logic, therefore, uses an in-phase (active) output from the gating (AO) circuit.

Micro and Macro Blocks

DIF (F-Ievel) Triggers

Both "macro" and "micro" logic blocks are used on the
7094 II systems pages; the type of block used depends
mainly on the availabilIty of printing space. Macro
blocks can incorporate two or more micro blocks, but
only when there are no pin connections and back panel
wiring between micro blocks.
As an example, consider the AND-OR-invert (AOI) circuit described in Figure 14. Figure 15a shows a macro
block condensation of the corresponding three micro
blocks at (b). Inputs to the macro block are "pinpointed" to specify input pins so that the AND functions
are grouped and easy to separate visually. Of the eight
possible inputs to the logic block, for example, the top
AND function is pinpointed to input pins 2 and 3; the
bottom AND function is pinpointed to input pins 6 and 7.
Input pins 4 and 5 provide a visual separation of the
two AND functions.
Note that the i~-phase output is used from the two
AND (+ A) micro blocks. These two blocks represent
diode circuitry only (see Figure 14). The out-of-phase
output is used from the +01 because the transistor is
located at this point.

Triggers (also referred to as "latches") act as storage
or remembering devices. Once they are turned on, they
remain in that state until turned off. Triggers are used
in some cases to form registers (tag register and address register, for example); in other cases they are

INVERT

Input 1

I

r --~I
I Rl
I
-------'
I
Input 2

The +AOI was described in a previous section. Because
of the limited number of logic block input pins, only
certain combinations of AND-OR functions can be shown
without losing the visual spacing. Obviously, then, it is
not possible to show two 4-way AND'S. Combinations
used include:
20

Output

+6v

D3

Input 3

D6

I
I

Input 4

I
I
I

AND

Input 1

AN D-OR-I nvert

+3v

+6v

..----...

-----'

~-----

Input 2 - - - - - - l
Input 3

-.J

Input 4 - - - - - . , ; : . . . . . . - - - - . . . : . . . . - - - - - - Output

..+_3v_ _.....1 Ov

Figure 14. AND-oR-!nvert Circuit

used singly to retain a specific condition (adder Q
carry and MQ overflow, for example). Various trigger
configurations exist in the 7094 II.

+ AOI Trigger
The +AOI is the most common type of trigger used

in
the new F-Ievel circuitry of the 7094 II. This circuit,
Figure 17, uses a +AOI followed by an inverter. One or
more input AND conditions can exist, usually consisting
of a data input and a gating input. The output from the
inverter is fed back to the input circuit and AND'ed with
the reset conditions to form a latch (or hold) circuit.
Outputs from the + AOI and inverter blocks indicate the
trigger ON and OFF conditions, respectively.
In Figure 17a, either data input AND being fully conditioned causes the output of the +AOI to go minus (-)
and the output of the inverter to go plus (+). This inverter output is fed back to AND with the reset pulse
line forming a hold circuit.
When the original data input AND circuit is deconditioned, the hold circuit keeps the trigger on. The trigger remains on until such time that the reset signal goes
minus (-) and breaks the hold circuit.
Figure 17b shows the trigger in positive condensed
logic. In-phase and out-of-phase trigger outputs indicate an ON and OFF state, respectively. Resets are shown
at the bottom of the trigger block with an additional
section added for each additional reset condition.

r
+

_In-'-pu_t_l_ _ _ _ D _
Input 2
E_

Input 3
Input 4

F -

1
2
3

PinS
----r -

--

+AOI

I

TPU

6

BDS
lB

IC

+ F Gate AD Left AC Line 4
+ FAD 18
+ F Gate AC Left Ln 4
+ F AC 18

B

Out-of-Phase
Outputs

+G

BBW

+ F Gate AC Left 2 Ln 4
+ F AC 19

6

2C

Gate AD - AC
AD17
Gate AD Rt - AC
AD16
Gate AD Rt 2 - AC
ADl5

A

In-Phase
Outputs

0

A
A

Gate AD Left AC
AD18
Gate AC left
ACl8
Gate AC Left 2
AC19

A

SC

(IB)

0

A
A (2C)

Figure 16. Systems Logic vs Condensed Positive Logic
Gating Circuitry

I

Sample

Tgr
r---

+AOI

I

1

+ F Sample Tgr On

'----

3D

+ F Data 2

l

+ F Data 2 Gate

+ F Sample Tgr Off

-4D-

3 _ A. _ _ _O_u-.:tp_u_t

ZHQ

Internal Connection

+A

Data 1
-=D-=a.:..::ta~I_G;:;.a::.:t~e---:J.... A

0

Data 2

Input 2

_D.. :,a. . :.ta.. .:.2. . :.G,;."a.:. t. .;,.e---:J.... A (4D)
Input 3

-T

-U

4
5
6

G-7
8

D

+ F Gate AD-Rt2 AC Ln3
+ FAD 15

vtJ

+G

+ F Data 1
+ F Data 1 Gate

(a)

Input 1

Gil
~
GD
~
B

+ F Gate AD-Rt AC Ln3
+ F AD 16

- F Reset

SMS Card
lnput/outPut Pins
Logic Block
(Input(output

+ F Gate AD-AC
+ F AD 17

A _ _O_ut-,-pu_t_

+A

Sample Tgr
(Out-of-Phase)
(In-Phase)

Trigger Off
Trigger On

Reset
_In.......p_ut_4_ _ _ _ G

Z HQ

t------t

Figure 15. Macro and Micro Blocks

Figure 17.

+AOI Trigger
Component Circuits

21

-

OAI Trigger

The -OAI trigger is sometimes used when + F input
levels are not available and - F levels must be used.
Figure 18 shows one example of a -OAI trigger that
can be turned on from two sources and reset by one
reset signal. Note that all of the active input levels are
- F. The overall logic remains the same as the + AOI
trigger discussed previously.
IBR Trigger

The !BR trigger circuit is packaged four to a twin card.
On systems pages the trigger is shown as two + T
blocks; two blocks are necessary because of the limited
number of input pins available on an individual block.
The trigger is also a macro block because the output inverter is not individually shown (Figure 19). The outof-phase output of the + T block originates before the
inverter; the in-phase output of the +T block originates
after the inverter.
The address portion of the !BR (21-35) requires an
additional input gate. The output of the + AI block is
connected to the trigger output at a point in front of
the output inverter; therefore, a hold circuit is established. The hold circuit is from pin 6 of the output inverter to pin 6 of the lower + T block. These two pin 6's

Sample

- F Set Pulse J
- F Set Pulse 2

Tgr
- F Tgr On

-OA I t--__....----I

are common points of internal card wiring; there is no
back panel wiring as might be concluded from the systems page layout.
Shift Cell-SC

The shift cell is an element which can accept new data
at its input while it simultaneously supplies old data at
its output. Shift cells make up the storage register, accumulator, and multiplier-quotient (MQ) register in the
7094 II.
These shift cells are a "double-latch" type of circuit
where two -OAI triggers are connected in series. Both
"set" and "hold" pulses are generated by control circuitry and used to introduce new data. Figure 20 shows
the shift cell configuration and sequence chart for setting in a 1 from an initial 0 condition. Note that the
active levels of the input data, set, and hold pulse are
-F. The appropriate data level must be present at the
input to the shift cell prior to arrival of the set and hold
pulses. The final output changes on the lagging edge of
the pulse.
The set and hold pulses are approximately 60 nanoseconds in width and occur at the end of the 175 nanosecond clock pulse. The hold pulse is generated from
the inverted output of the set pulse, skewed by one
level of circuit delay.
If the shift cell initially contains a 0, point B (Figure
20) is plus (+) and O2 is deconditioned. When a minus
(-) data signal arrives at the shift cell, 0 1 becomes con-

+ F Reset
2D

2C
- F Tgr Off

Figure 18.

-OAI

Trigger

- F SC
D

r---------------~~~

~y

t- T

IBR

I

35

+AOI

t------t

LD

TPX

~X

t-u TPX
L_...L_I _ _ _ _ _ _ _ _ _

I

-.J

- F Set

)icro

- F Hold

r-------------·I
IBR

35

----I~yo
---+I-'T
+T
7-------_~I
-----

~

-..J~

Set Pulse

1 level
of delay
Hold Pulse

:

--:

I

Point B

r--121.evels

~~tay

1 level of delay Point C

Point D

Figure 20. Shift Cell

~

-

:..- 2 levels of delay
I

=1

ditioned. When the set pulse goes minus (-), both inputs are conditioned; point A goes plus (+), point B
goes minus (-) and a data bit is set into the first half of
the shift cell.
The minus (-) signal at point B feeds 0 5 and 0 6 , but
the final condition at 0 7 is blocked because the hold
pulse has gone plus (+). The incoming data bit is not
allowed in the second half of the shift cell at this time
because doing so would destroy the old data and defeat the purpose of the shift cell. The minus (-) output
of the inverter at point B does, however, feed back to
O 2 to act as a hold on the first half of the shift cell when
the input data signal is removed.
At the end of the clock pulse, the hold pulse goes
minus (-) and conditions 0 7 , the final input to the second half of the shift cell. At this time, point C goes
plus (+), point D goes minus (-) and the shift cell indicates a 1 output. Point D is also returned to both 0 6
and 0 7 to form a hold circuit for the second half of the
shift cell.
Figure 21 shows a sequence chart of a shift cell,
AC(35) for example, under the following conditions:
1. Initially reset to a 0 state
2. The initial 0 replaced by a 1
3. The 1 replaced by a second 1
4. The second 1 replaced by a 0
5. The last 0 replaced by another 0

Figure 22a shows the DOT'ing function with a threelegged OR and a two-legged AND. The top three-legged
OR circuit supplies the collector load for both itself and
the unloaded two-legged AND circuit below. Output
connection between the two circuits is made by back
panel wiring.
Note that the logical input and output levels desired
(i.e., +F or -F) will determine whether the DOT'ing
function is an AND or OR.
Figure 22b shows a DOT-OR' ed configuration. Any + F
input to the +01 circuit causes transistor T1 to conduct
and produce a - F output; also, both inputs being + F
at the +AI circuit cause transistor T2 to conduct and
produce a - F output. Therefore, if the logical output
level is - F, either circuit block produces the required
output.
Figure 22c shows the same identical circuit as (a)
but as a DOT-AND configuration. All inputs being -Fat
the -AI circuit force transistor T1 out of conduction
and produce a +F output; either input being - F at the
-or circuit forces transistor T2 out of conduction and
also produces a + F output. If the input conditions are
not as just described, either Tl or T2 will conduct and
produce a - F output which is opposite to the logical
output desired.

,-------------------.
+3v

I

I

DOT-OR1ing and AND1ing

I
I

In many cases, the available circuits do not contain
enough inputs to satisfy a logical function. To meet
this requirement, two or more existing circuits can be
DOT'ed together so that the function of one logical block
is «extended" into the other. DOT'ing is accomplished by
having the circuits share a common transistor load, and
because of this, some circuit card types do not contain
transistor collector loads.

I

I

Input I

Back Panel
Input 2

/wirin g

I
I
Clock

Output

-3v

I

I

I
-------1

t------Data Input

I

I

I
Set Pulse

I

I
I

Hold Pulse

I
I
L _ _ _ _ _ _ _ _ _ _ _ _ _ _~v_ _ _ _-=_...1I

Point B

(a)

Point C

~~~__r-_,~--~~.~-F~I~np~ut~I--. .-

~~__~~

-F Input 2
-F Input 3

Point D

t-----hAC(35)= 1 AC(35)= 1 
.-----i-------i
AC(35)=O
AC(35)=O AC(35)=O

-F Input 5

(b)

Figure 21. Shift Cell Timing Chart

Dot-AND

-F Input 4

(c)

Figure 22. DOT-oR'ing and DOT-AND'ing
Component Circuits

23

Component Circuits Card Types
Three types of SMS component circuit cards are used to
support the DIF circuitry; single, twin, and STAN-PAC
cards. In many cases, register positions or similar functions are combined on cards as both a packaging and
trouble-shooting convenience.
SMS Single Card

All electronic components are mounted on the front
side of the card and connections to the components are
made on the back side by printed wiring patterns. The
16 contacts (labeled A through R) couple the signal
and service voltages to the circuit components when
the card is inserted into the SMS socket.
These single SMS cards form the bulk of the computer logic. They contain: basic circuit elements such
as AND'ing, oR'ing, inverting, and terminating; and
semi-specialized circuit functions such as adder lookahead and gating.
SMS Twin Card

The twin SMS card is one physical card which requires
the panel space of two single SMS cards. The use of
twin cards provides more circuitry in a given space
(compared to single cards) and is desirable in high
speed circuitry because more operations can be per-

Reg
Pos

S

6
7
8
9
10

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

01B4F27-28
01B4F27-28
01B4F27-28
01B4F27-28
01B4F27-28
01B4F27-28
01B4F25-26
01B4F25-26
01B4F25-26
01B4F25-26
01B4F25-26
01B4F25-26
01 B.4F07-08
01B4F07-08
01B4F07-08
OlB4F07-08
01B4F07-08
01B4F07-08
01B3F17-18
01B3F17-18
01B3F17-18
01B3F17-18
01B3F17-18
01B3F17-18
01B3H06-07
01B3H06-07
01B3H06-07
01B3H06-07
01B3H06-07
01B3H06-07
01B3H04-05
01B3H04-05
0IB3H04-05
01B3H04-05
01B3H04-05

*
*
*
*
'.\t

*
*
*
*
*

24

The STAN-PAC card is identified by its vertically mounted components. Resistors, diodes, chokes, and so forth
have their top terminal welded to a component mounting strip which clamps to the body of the component
for mechanical strength. The strip also provides an
electrical path to the adjacent component. Both terminals of the components pass through a hole in the card
and are soldered to a land pattern on the reverse side
of the card. The 32 contacts on the card (labeled A
through Z and 1 through 8) couple the signal and service voltages to the circuit components when the card is
inserted into the SMS sockets.

BBW

TPU

*

*
*
*

*
*
*

01B4A05
01B4A05
01B4A05
01B4A05
OlB4A05
0lB4A05

01B4A07
01B4A07
OlB4A07
01B4A07
01B4A07
0lB4A07

01B4A08
OlB4A08
01B4A08
01B4A08
OlB4A08
0lB4A08

*

*
*
*

*
*

01B4A04
OlB4A04
01B4A04
PIB4A04
0lB4A04
OlB4A04
01B3A25
0lB3A25
OlB3A25
01B3A25
0lB3A25
01B3A25
01B3A22
01B3A22
01B3A22
OlB3A22
OlB3A22
OlB3A22
OlB3A20
0lB3A20
OlB3A20
0lB3A20
0lB3A20
0lB3A20

01B4A06
0lB4A06
0lB4A06
0lB4A06
0lB4A06
0lB4A06
0lB3A24
0lB3A24
0lB3A24
0lB3A24
0lB3A24
0lB3A24
0lB3A23
0lB3A23
0lB3A23
0lB3A23
0lB3A23
0lB3A23
0lB3A21
0lB3A21
0lB3A21
0lB3A21
0lB3A21
0lB3A21

*
*

*

0lB3A19
0lB3A19
0lB3AI9
0lB3A19
0lB3AI9
01B3A19
0lB3A 18
0lB3AI8
01B3A18
01B3A18
0lB3A18
0lB3A 18
0lB3AI7
0lB3A17
0lB3A17
01B3A17
0lB3A17
0lB3A17
0lB3A16
0lB3AI6
01B3A16
OlB3A 16
01B3A 16
0lB3AI6

*

Indicates the use of single cards.

Figure 23. Twin-Card Locations for

SMS STAN·PAC Card

MQ

Accumulator
BBW
TPU

*

1
2
3
4
5

*

Storage Register
TPU

formed before the resultant signal must be directed to
other cards by way of connectors and back-panel wiring. The 32 contacts on the card (labeled A through Z
and 1 through 8) couple the signal and service voltages
to the circuit component when the card is inserted into
the SMS sockets.
Circuitry using twin cards includes: input gating to
the storage register, accumulator and MQ; instruction
backup register; sense indicator register; index registers; and index adder positions.
Register positions and twin card locations are as
shown in Figures 23 and 24.

SR, AC,

and

MQ

Input Gating

*
*
*
*
*
*
*
*
*
*
*
*

*
*
*
*
*
*
*
*

*
*
*
*
*
*

*

The various BDS card register positions and corresponding machine locations are shown in Figure 25.
Figure 26 shows a STAN-PAC BDS card. To achieve the
fast adder time of one clock pulse (175 nanoseconds),
corresponding positions of the storage register, accumulator, MQ, and main adder have been combined on
one STAN-PAC circuit card. Figure 26 shows position 35.
This card position contains the shift cells for SR ( 35 ) ,
MQ(35), and AC(35). One input gate (+C) circuit for

is also included; the remaining gates for the SR,
and AC are on other cards and DOT-OR'ed at the
shift cell as shown.
The corresponding main adder position also has its
input gating circuitry and output lookahead functions
(propagate, generate, and exclusive OR) on the same
card. Note, however, that the actual adder sum output
logic is on a separate card. Note, also, that the top circuit of the bottom adder gate is not used for AD( 35).

SR ( 35)
MQ,

SR,AC,MQ,AD Position

Card location (BDS)

SR(S),AC(S, P),AD(P)
1

01B4F22
0lB4F21
01 B4F20
01B4FI9
0lB4FI8
0lB4FI7
01B4FI6
0lB4FI5
0lB4F14
0lB4FI3
0lB4FI2
OIB4FIl
OlB4FIO
0lB4F09
OlB4F06
01B4F05
01B4F04
01B3F25
OlB3F24
OlB3F23
OlB3F22
OlB3F21
01B3F20
01B3FI9
01B3FI6
0lB3FI4
0lB3FI3
0lB3FI2
OlB3Fl1
OlB3FIO
OlB3F09
OlB3F08
0lB3F07
01B3F06
0lB3F05
0lB3F04

2
3
4
5
Sense
Indicator
Register

Card
Location
(TPW)

Instruction
Backup
Register

Card
Location
(TPX)

5-3
4-7
8-11
12-15
16-19
20-23
24-27
28-31
32-35

01B2H28
01B2H27
01B2H26
01 B2H25
01B2H24
01B2H23
01 B2H22
01B2H21
01B2H20

5-3
4-7
8-11
12-15
16-19
20
21-23
24-27
28-31
32-35

01A3D12
01A3D11
01A3D10
01A3D09
01A3D08
*
01A3D07
01A3D06
01A3D05
01A3D04

Index
Adder
Position

Card
Location
(TPS)

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

01A3F18
01A3F17
01A3F16
01A3F15
01A3F14
01A3F13
01A3F12
01A3Fll
01A3F10
01A3F09
01A3F08
01A3F07
01A3F06
01A3F05
01A3F04

(a)

(b)

*Indicates the use of
single cards
Index
Registers
Position

(c)

(d)

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

Figure 24. Twin-Card Locations for

6
7

8
9

10
11

12
13
14
15
16
17
18
19
20

Card
Location
(TPV)

2I

22
23
24
25
26
27
28
29
30
31
32

01A1G18
01A1G17
01A1G16
01A1G15
01A1G14
01A1G13
01A1G12
01A1G11
01A1G10
01A1G09
01A1G08
01A 1G07
01A1G06
01A 1G05
01A 1G04

SI, IBR, XAD,

and

33

34
35
XR

Figure 25.

BDS

Card Locations for

SR, AC, MQ

and AD

Component Circuits

25

: :t]GD~>--D-~"'F

+F Gate AD ...... SR
+F AD 35
+F Gate AC

~

SR

~---C

E

r--

F

+F SR 35

,--K-

G

r-H -

_1------.

_+.:...F--:G;....a_te_M--:Q-=--......
_S_R_ _ _ _ _ 1 _ _-4-_ _ E
,-L

-F {Dot OR of Other Input Gates} ....,D.,--+_-+--------I
-F Set SR
~K~+_-+------------~
-F Hold SR
..;.H-=---+_--+---------...J
- - --- ---

---

-i-- ----

-F {Dot OR or Input Gates}

M

-F Set MQ
-F Hold MQ

P
N

-F {Dot OR of Input Gates}

Storage Register {;35}
02.01.09.1

-- --

-- --

rr

--~ - - - - - - - - - -

MQ 35

V

---4-------------------

v-

-~F~S~e~t~A--'C~-----------I-T~+---------------------T....:-F_H;...;.o;:.,;l..:;.d;....A.;,.,:C'---_ _ _ _ _ _ I-=U'----i-----------------U

---=sc AC 35

G

--

L

+F MQ 35

G

+F AC 35

~~_r----------------------

---- ---- ---- -- --

--

MQ Register {35}
02.04.06.1

----+-+------------------------

__
Accumulator Register {35}
02.03.08.1

-- -- -- --- -- -- -- -- -- -- -- --- -- -- --- --- --- --- --+F Gate AC ~AD

+F Gate Comp AC

_R__-+---+--+-+ R
~+--+--+ G
~AD

-----+~_+

~
+G

S,

1....-1--

...---If---J-II --0011 ~ X ________________________________.:..:.X
rz~

+F Propagate 35

I

I
I

I

{Not Used}

-z - -

(Not Used)
6
----------,{Not Used}
7

+-----+---1
AD 35

+F Gate Comp SR +AD

I

6 -

_2_1--+-+-:

+G

I

I
L

~ ~-~y

y +F Generate 35

----4J----

I

Q

+F Gate SR+AD

I

---+--~,--Q

I....-F-_

I
I
I

Ground

1

-+-3....:v-o~lt-s---- ~~
+6 volts (MC)
-3 volts
Ground

_5_ _
_8_ _
_J_ _

I
I
I

~

~I

~w
~

1-

Main Adder (35)
02.02.19.1
BDS - Card Location 01 B3 F04

Figure 26. Typical BDS Card Layout
26

W +F Exclusive

OR 35

Dff Circuit Specifications
DIF Logic Block

Figure 27 shows a typical AND-OR-invert (AOI) DIF circuit. Diode Dl and the dotted circuitry below it indicates the AND function; diode D2 and the dotted circuitry below it indicates the OR function. Diode D3
produces an additional voltage drop in its circuit and
is used because it provides better control than a resistor. Diode D4 provides the transistor collector-tobase feedback network to prevent the transistor from
going into saturation. The inductor (L) in the transistor collector circuit is used to improve the output
signal rise time by overcoming stray capacitance associated with the output circuit.
Inverter circuits are formed by using one-legged AOI
circuits.

-Dfj

--E

+AOI
F
F

A--

_KME_+

Output

Dl

{

---.,
I

------l
- - ---1

---

....
---~

----~

___ ...1

------I

-3v

Figure 27.

DIF

Circuit delays vary as a function of: the number of fanin Signals, the number of fan-out signals, and the total
length of back panel wire. The total best-case to worstcase delays vary from approximately 5.0 to 20.0 nanoseconds. These delays apply to the logic block which is
performing two logic functions (AND-OR).
Logic Siock Power Supply Requirements

Nominal Voltages and Tolerances:
SUPPLY

+ 3 volts
- 3 volts

3V

U
+6v

Fan-in

Logic Siock Circuit Delays

+6M

--F
--G

Input

Logic blocks
Line drivers
Indicator drivers
Inverter (only one )-equivalent to three loads

Logic

Logic Siock Input Specifications

DC Voltage Levels and Limits:

TOLERANCE

± 4 percent
± 4 percent
± 4 percent

Overvoltage and Undervoltage Limits and C onditions:
1. The following overvoltages can be tolerated without causing component damage:
SUPPLY

OVERVOLTAGE LIMIT

+6M
+ 3 volts

+ 9.0 volts
+ 3.6 volts

- 3 volts

- 6.0 volts

2. Any power supply can be open-circuited without
causing component damage.
3. Any power supply can be shorted to ground without causing component damage.
4. Power supply sequencing is not required.
5. Logic block cards may be inserted into or removed from the computer with power on without causing component damage.

3.35 v

2.88 v
0.93 v
0.47 v / -

Fan-In Capabilities: The logic block can have a fanin of five on the AND circuitry, and five on the OR circuitry. Inputs can be expanded, however, as explained
later.
Logic Siock Output Specifications

DC Voltage Levels and Limits:

r

3.35V

2.88v

0.93 v
0.47 v

Fan-Out Capabilities: The logic block has a fan-out
capability of ten of the following in any combination.

Logic Siock Extended Capabilities

Eight-Way AND: An eight-way AND fan-in may be
used with a maxinlum of one nanosecond delay added
per block.
Dot-OR Connections: Logic block collectors may be
DOT-oR'ed to increase the OR fan-in. Up to two additional collectors may be connected to a logic block output; the DOT-OR' ed collectors will have a single collector
resistor and inductor. Each additional DOT-oR'ed collector adds 1.5 nanoseconds to the delay of the original
circuit.
Frequently all of the circuit diodes are not used. In
these cases:
1. AND diodes can "float"
2. OR diodes must be tied to ground

Component Circuits

27

DIF Indicator Driver

The DIF indicator driver (Figure 28) is a saturating
circuit designed to indicate an output level of the DIF
logic block. The indicator light will be on when the
logic block output is at the "up" (+3 volts) level, and
off when the logic block output is at the "down" (0
volts) level. A small amount of "pre-energization" current continues to flow through the indicator lamp even
when off and causes a faint glow at the indicator
filament.

U

~F­
---A

Power Supply Limitations:
1. Power supply sequencing not required.
2. Duty cycle is 100 percent.
3. Card can be removed from the computer with
power on without damage to the circuit.
N-Line to DIF Converter-Terminator

The N to F level converter provides proper termination for N-line (drift current mode) logic blocks (Figure 29). The converter also converts the N-line level to
one capable of driving an F-Ievel (voltage mode) logic
block. The circuit is designed to be driven by 200 feet
of coaxial cable from a B-type logic block.

r------,
~

:~ :

+6M

R4
r-----1a----vVV.... 1

L

Rl
820Q

R5

+30v

_L~ _ _

I

The circuit portion within
dotted lines is external to
the indicator driver card
assembly.

3.3K

---H

.J

r::l
BA-LJ-D-- U
_p

+3v

R8
150Q
..

Converter

L
3.3ttH

+6v

+3v

+12v

:lI----+-~

Out

-3v

Figure 28.

DIF

N

Indicator Driver

p
N

Indicator Driver Input Specifications

DC Voltage Levels and Limits:
3.12V
2.85 v

f

+ 0.93 v
+ 0.47 v

In _ _ " 1 / \ 1 ' , - - _

.

Loading: The indicator driver must be considered as
at least three loads.
-12v

Indicator Driver Output Specifications

Figure 29. N-Line to F-Line Converter

The output specifications for this circuit are determined
by the particular indicator lamp being driven. These
specifications are for driving indicator lamp PiN 550511
connected as shown in Figure 28.
DC Voltage Levels and Limits:

Lamp
OFF

f

·

29.2v
24.2v

Lamp
ON

22.8v
15.0v

Indicator Driver Power Supply Requirements

Voltages and Tolerances:

+ 6v
- 3v
+ 30 v
28

± 4 percent
± 4 percent
± 4 percent (required on the indicator panelnot on the circuit card)

N to f Converter Input Specifications

Input voltage levels are a fundion of the input current
which is set by the driving circuit, the 82 ohm input resistor, and the base-to-emitter drop of the transistor.
Fan-in Capabilities: The N to F converter-driver is
designed to accept a single N-Ievel input signal.
N to f Converter Output Specifications

DC Voltage Levels and Limits:

+ .912v
- .380 v

f
.

3.92V

2.98 v

Fan-Out Capabilities: The N to F converter without
the inverter output can drive only one logic block.
When the converter has the inverter (out-of-phase)
output, the capabilities are the same as for the AOI DIF
logic block.

circuit also converts the incoming signal to an F-Ievel
(voltage mode) signal sufficient to drive ten DIF logic
blocks.
P to F Converter Input Specifications

-

DC Voltage Levels and Limits:
N to f Converter Delays

The best-case to worst-case circuit delays for the N to
F converter vary from approximately 4 to 160 nanoseconds. Worst-case delays consider worst-case conditions
of components, voltages, driver and output loading.
Power Supply Requirements

Power Supply Limitations:
1. All power supply tolerances are ±4 percent at the
circuit.
2. Voltage sequencing not required.
3. Circuit card can be removed without damage to
itself, its driver, or its load.
Over-Voltage Limits:
SUPPLY

+ 12 volts
+ 3 volts
-

3 volts
- 12 volts

OVER-VOLTAGE LIMITS
20 volts

+
+

9 volts
- 9 volts
- 20 volts

These limits assure that breakdown limits will not be
exceeded; they do not assume proper delays and levels.

- 3.51 v
- 3.90v

2.90V

f

- 3.44 v

Fan-in Capabilities: The P to F converter-driver is
designed to accept a single P-Ievel input signal.
P to f Converter Output Specifications

DC Voltages Levels and Limits:

+ 0.91 v
+ 0.18 v

f

3. 12V
2.88 v

Fan-Out Capabilities: The converter block has a fanout capability of ten of the following in any combination.
1. Logic blocks
2. Line drivers
3. Indicator drivers
4. Inverter (only one )-equivalent to three loads
P to f Converter Delays

The best-case to worst-case circuit delays for the P to F
converter vary from approximately 4 to 54 nanoseconds.
P-Line to DIF Converter-Terminator

This converter-terminator circuit is designed to terminate up to 200 feet of 93 ohm coaxial line driven by a
P-line (current mode) logic block (Figure 30). The

~A­

--P-U

+12v

P to F Power Supply Requirements

Power supply requirements are the same as for the Nline to F converter-terminator.

+3v

R3
1.62K

Dl

Figure 30. P-Line to F-Line Converter
Component Circuits

29

DIF to N-Line Converter-Driver

F to N Converter Delays

The F to N-line converter is designed to accept an Flevel (voltage mode) input signal and drive a single
N-Ievel (current mode) output (Figure 31). This output can feed up to 200 feet (maximum) of 95 ohm coaxial cable piN 595997.

The best-case to worst-case circuit delays for the F to
N converter are approximately 6 to 76 nanoseconds.
F to N Power Supply Requirements

Voltages and Tolerances:
- 12 volts

+ 12 volts

{j-

---E

F

N

~--...

A--

Output

± 4 percent
± 4 percent

A ±3 volt excursion is permissible on the +12 volt
and -12 volt power supplies under fault condJ.tions.
DIF to P-Line Converter-Driver

The F to P-line converter is designed to accept an Flevel (voltage mode) input signal and drive a single
P-Ievel (current mode) output (Figure 32). The output c.an feed up to 200 feet (maximum) of 95 ohm coaxial cable PiN 595997.

R7

N
-12v

P

R6

N

-12v

+12v

p
Input
_--..1\1'1., .......---1

+12v
Output

N
p

R3
6.2K _

Input

Figure 31. F-Line to N-Line Converter
F to N Converter Input Specifications

Dl

DC Voltage Levels and Limits:
3.38 v
2.95 v
+ 0.93 v

+ 0.47 v / Fan-in Capabilities: The F to N converter-driver is
designed to accept a single F-Ievel input signal.

+12v

Figure 32. F-Line to P-Line Converter

F to P Converter Input Specifications

DC Voltage Levels and Limits:

F to N Converter Output Specifications

DC Voltage Levels and Limits: The converter output voltage levels depend on whether the terminator is
a translating (N to P-Ievel) block, or a non-translating
( N to N -level) block.
TRANSLATING

NON-TRANSLATING

LINE TERMINATOR

LINE TERMINATOR

- 0.20 v
- 0.35 v

j

+0.32V
+ 0.21 v

::t_2.64V
- 3.24 v
- 3.38 v
- 3.82 v

Fan-Out Capabilities: The F to N converter can drive
only one logic block. Output of the converter is an outof-phase signal level.
30

+ 0.93 v
+ 0.47 v

f

+ 5.80V
+ 4.42 v

Fan-in Capabilities: The F to P converter is designed
to accept a single F-Ievel input signal. This converter
circuit is to be driven by an unloaded DIF circuit. The
maximum wire length between the DIF circuit output
and converter input is not to exceed 24 inches. The DIF
circuit driving this converter is to drive no other loads.
F to P Converter Output Specifications

DC Voltage Levels and Limits: The converter output
voltage levels depend on whether the tenninator is a

translating (P to N-level) block, or a non-translating
(P to P-level) block.
TRANSLATING

NON-TRANSLATING

LINE TERMINATOR

LINE TERMINATOR

- 5.98 v
- 6.52 v

j

-5.39V
- 6.07 v
- 2.75v
- 3.12v

j

-2.16V
- 2.63v

Fan-Out Capabilities: The F to P converter can drive
only one logic block. Output of the converter is an outof-phase signal level.
F to P Converter Delays

These delays are measured from the input of the DIF
driving circuit to the output of the conversion circuit.
F to P Power Supply Requirements

Voltages and Tolerances:
-

3 volts

+ 12 volts

± 4 percent
± 4 percent

Power Supply Limitations:
1. The + 12 volt supply cannot be more positive than
+12.82 volts.
2. The -3 volt supply cannot be more positive than
-1.5 volts.

The best-case to worst-case circuit delays for the F to
P converter are approximately 11 to 62 nanoseconds.

Component Circuits

31

60 rv208v
7618
PCU

3~

7109
7111
Arithmetic
Instruction
Processi ng
Sequence
Unit
Unit
(Central Proc~ssing Unit)

Power (400'" 208v, 3~) to all frames

I

7909 Data Channel

716
Printer

711 Card
Reader

721 Card
Punch

Figure 33. 7094 II System Configuration

32

1009DTU
1011 PTU
1014 RIU
Telegraph
I/O Units

System and Functional Components

System Components

IBM 7111 and 7109 Central Processing Units

Figure 33 is a block diagram of the 7094 II system
configuration showing a possible combination of units.
Of course, not all units are required in every installation. The final selection would be determined by customer need.
Figure 34 illustrates the basic functional organization
of the 7094 II. Although there is a slight change in
terminology, components and functions are essentially
the same as previously described for a general computer (Figure 1). Note, however, that a multiplexor has
been added. Arrows indicate the general flow of information. Although the sections can be neatly separated
physically, there are many functional combinations not
shown in this grouping. Storage is the only functional
section that is a separate machine unit.

The central processing unit (cpu) of the 7094 II is actually made up of two sub-units-cpu-l and CPU-2. The
CPU-l is the IBM 7111 Instruction ProceSSing Unit and
CPU-2 is the IBM 7109 Arithmetic Sequence Unit.
As these names imply, CPU-l contains all arithmetic
and control registers and accepts, decodes, and routes
instructions to the rest of the computer. Because of the
dense circuit packing, CPU-l also performs a great deal
of instruction execution. CPU-2 controls instruction execution for most POD 76 and sense indicator instructions,
and I/O operations.
:Many of the functions previous associated with CPU-2
are now contained in CPU-I. There is a great deal of interplay and overlap between these two units, and in
some sequences it is difficult to determine an accurate
functional boundary.
The arithmetic section is the calculating section of
the computer system. Here, portions of information,
either instructions or data, can be transformed, combined, or altered. This section also keeps account of the
instruction it is using and the one it will use next.
The control section directs the other sections. It tells
them what to do and when to do it. Instructions come
into the control section from storage.

CPU
Control and
Arithmetic

f----Read
Storage

-- 0

" A
~f-,. A

To SR Zero Check

(4A)

"----

Gate SI +SR
SI 17
Gate IBR~SR
IBR 17
Gate Op Keys
Op Key 17

Gate AD~SR
AD 17
Gate AC+ SR
AC 17
Gate MQ ~SR
MQ 17

,.

,.

(02. 12.47.1)

-r-

A

-

0

A
'-

--"

A (3A)----4

Gate Comp SR ~AD
Not SR 17
Gate SR ~AD

-

;---~

~

A 0
' t---

;----

,. A

-'"

0

~ t--A (4B)

...;.

To AD 17

,.

'--'--

02.02.10. I

A
t--A (2A)

SR (17)
~
Shift
Cell

-

Set SR
Hold SR

(IA)

Gate SR Left .....AD

-'-

.J

To AD 16

(tG)

"

02.02.09.1
Gate SR 3-17 ..... XAD

02.01.05. I

"

A

..:. (4G)
0:3".05.47. I

SR 17

To XAD 17

,...--....,

Gate SR

~SB

r:J

(~)

MF SB 17 Output

",.

02.01.50. I

L{HJ
51

41

SR 17 Late
(ToMQ&SI)

02.01.11.1

Figure 38. Storage Register Position 17

Figure 38 shows condensed logic of SR( 17). Inputs to the
storage register as a whole can come from: the op keys;
instruction backup register (IBR); sense indicator register (SI); accumulator register (AC); MQ register; main
adders (AD); index adders (XAD); and either the even
or odd storage bus (even or odd memory) .
Note that the index adders can be gated into either
SR ( 3,.17) or SR ( 21 ~35 ). This choice in gating is helpful
when routing the index registers to either decrement
or address positions. SR( Q) also receives AC( Q) as temporary storage during certain instructions as mentioned
previously.
Note that the storage register inputs are also gated
to a zero check circuit (Systems 02.12.47.1). During
many operations, information is gated to the storage
register to make use of this circuit in checking for zero
values. Because there is no set pulse accompanying the
input data, the present storage register contents are not
destroyed or affected.
The storage register is the focal pOint for information
distribution and register swapping. Therefore, many
outputs are gated from various sections of the storage
register to various sections of other registers or adders.
Units receiving information from the storage register
include: the storage bus (the storage register is the
only exit from the CPU to memory), main adders, index
40

adders, SI register, MQ, accumulator, and tag register
(manual operations).
Note that either the true or complement SR values
can be sent to the main adders. The true output of the
SR can also be shifted left one place as it is sent to the
main adders. This shift feature is used during multiplication to effectively multiply by two (2).
There is no full-word routing path from the storage
register to the accumulator; data transfer of this type is
accomplished by routing the storage register to the
main adders and from there to the accumulator.
SR( s, 1-8) and SR( s, 1-5) have a direct path to AC( S, 1-8)
and AC(P, 1-5) respectively. These paths are used during
floating-point operations for characteristic routing and
convert instructions. SR ( Q) can also be gated directly
to AC( Q) when restoring the AC to its original value
after certain instructions.
Either SR( 3-17) or SR( 21-35) can be gated to the index
adders. SR( 3-17) gating is used primarily during class A
(TIX, TNX, etc.) and index transmission (LXD, LDC, PDX,
and PDC) instructions. SR( 21-35) gating is used primarily
as: a routing path for index transmission instructions
(LXA, LAC, etc.); POD 76 routing to the shift counter for
class and unit decoding; and normal address modification with a specified index register.

Each position of the storage register is combined on
the same STAN-PAC circuit card with a corresponding
position of the AD, AC, and MQ.
Accumulator Register-AC
(Systems 02.03.00.1-02.03.09.1)

. The accumulator is a 39-position register, each position
consisting of a shift cell (sc). The register positions are
labeled S, Q, P, 1-8, 9P, and 9-35. Positions Sand 1
through 35 accommodate the computer word in standard operations. Positions Q and P are used as overflow
positions because the sum of two 35-position numbers
can be greater than 35 positions. Position 9P is also an
overflow position used during floating-point operations;
it replaces the 9 overflow trigger which was used on
previous systems.
The term accumulator is somewhat misleading because the register is not actually able to accumulate.
The Accan contain only one word at a time. When
adding, the AC and adders work as a unit to perform
the addition, and the AC merely holds the result.
Figure 39 shows condensed logic of AC( 17). Inputs to
the accumulator can come from: the storage register,
main adders, adjacent positions of the accumulator, and
the MQ. SR( S, 1-8), SR( S, 1-5), and SR( Q) have a direct
path to the accumulator. When the entire storage reg-

Gate AD .... AC
AD 17
Gate AD Rt-+AC
AD16
Gate AD Rt 2 ~AC
AD15

ister contents is to be set into the accumulator, however, the main adders are used as a routing path.
Note that the main adders can be gated into the accumulator in a variety of ways: direct (true or complement form for positions Q, 1-8), shifted left one position, shifted right one position, or shifted right two
positions. Advantage is taken of this shift feature during execution of arithmetic operations.
Right and left shift operations cause a particular AC
position to receive data from adjacent right or left AC
positions; This shifting process proceeds at two positions per clock pulse as long as the shift counter value
is two or greater. With a shift count value of one, a
single position shift is accomplished. Because of these
shifts, routing circuits are available to either the first
( adjacent) or second left/right position. of the AC and
MQ registers. Right shifts take advantage of the "shift
right 1" and "shift right 2" circuitry from the main adders; for example, the shift is accomplished by routing
the AC to the main adders, and from there back into the
appropriate AC/MQ positions.
Routing paths are available to AC(9, 10) from MQ(34, 35)
and used during the initial phase of DFAD instructions
when aligning characteristics.
Outputs from the accumulator can go to a variety of
places: the storage register; main adders (true or com-

-A ,...0
~ -

...
,

-A

A ~C)

-'---

Gate AD Left ~ AC
ADIS
Gate AC Lett
ADIS
Gate AC Left 2
AC19

~
,.

...--..--A 0

r--

~ A
....,. I-... A (4D)

Gate Comp AC ~AD
Not AC (17)
Gate AC~AD

-

AC (17)

...

"'---""--

Set AC
Hold AC

...
...

-,...-"" A 0

...

--""

~

Shift
Cell

A (4A)

To AD 17

-'---

02.02.10.1
(2C)

Gate AC Left 2

02.03.04.1

...
LJA
(4H)

To AC 15

...

02-:03.03.1
Gate AC Left

.------.
A
(4B)
~

To AC 16
,.

02.03.04.1
Gate AC .... SR

LJ
:I-----(:A)

To SR 17

,.

02.01.05.1

AC17

Gate AC-+ IBR

(tG)

To IBR 17

...,.

03.0S.05.1

Figure 39. Accumulator Position 17
7094 II System and Functional Components

41

plement form); index adders (AC positions 30-35 for
convert instructions); IBR; and adjacent positions of the
AC or MQ during shift operations. The accumulator is
sent to the input of the storage register in many cases
(without a set pulse) to take advantage of the zero
check circuitry.
Each position of the accumulator is combined on the
same STAN-PAC circuit card with a corresponding position of the SR, AD, and MQ.

Multiplier-Quotient Register-MQ
{Systems 02.04.00.1-02.04.06.1}
The MQ is a 36-position register, each position consisting of a shift cell (sc). The MQ receives its name from
functions performed. At the start of a multiply operation it contains the multiplier; after the multiply it contains the least significant half of the product. At the
beginning of a divide operation, it contains the least
significant half of the dividend; after the divide it contains the quotient. Due to the double latch makeup of
the shift cell, the MQ has the ability of shifting left or
right.
Figure 40 shows condensed logic of MQ(17). Inputs
to the MQ can come from the storage register, accumulator, or main adders. The SR outputs may come to
the MQ as a full word, or SR( s, 1-5) may be gated to
MQ ( 30-35) for convert instruction operations.
Inputs from the adders during multiplication are
from AD(34-35) to either MQ(1-2) or MQ(9-1O), depending on fixed-point or floating-point operations. The

Gt
a e MQLft
e
MQ 18
Gate MQ Rt
MQ 16
Gate SR~MQ
SR 17

routing paths are also used as inputs to
when performing right shift operations.
Outputs from the MQ go to a variety of places. Gatings to the storage register are used for MQ store operations (the SR is the only output register to the storage
bus) or for register swapping during arithmetic operations. MQ(S, 1-5) are gated to the index adders to produce required core storage addresses during convert
operations. MQ(34, 35) are gated into AC(9, 10) during
DFAD operations when aligning the fractions prior to
the actual addition. Gating is provided for normal right
and left shifts within the MQ or between the MQ and AC.
Outputs are also available from MQ (s, 1) to MQ (34, 35)
for ring shift (RQL) operations.
Each position of the MQ is combined on the same
STAN-PAC circuit card with a corresponding position of
the SR, AD, and AC.

AD(34-35)
MQ( 1,2)

Sense Indicator Register-SI
{Systems 02.06.00.1-02.06.11.1}
The sense indicator register is a 36-position register
labeled S, 1-35. This register serves a variety of functions. It can be used as a set of switches which are set
and tested by the program to check the progress or direction of the program. It may also be used to store
words or parts of words temporarily; in this way the
register is useful in altering and testing words.
During some logical or masking operations, SI(S) is
referred to as SI( 0); in these cases the first position has
lost its identity as a sign and has become just another
bit in the overall group of bits being operated on.

G at e MQ Left 2

r-- r----

:: A

::10...

0
Gate MQ Left

~

.... A (4D)

~

J~

~i...--

~

...
~

-A

M~
(4E)

---~

Set MQ
Hold MQ

...

-.J

(~)

I

(tH)

Gate

MQ 17

42

Position 17

To MQ 19

1

MQ~SR

~I

...

A
(2A)

02.01.05.1
MQ

To MQ 18

02.04.03.1

02.04.03.1

Figure 40.

To MQ 16

02.04.03.1

Gate MQ Rt 2

Shift
Cell

I

--l

0

...

(:s)

02:04.Ci3. 1

J

-A

-

U

Gate MQ Rt
Gate MQ Rt 2
MQ 15
Gate MQ Lt 2
MQ 19

To MQ 15

02.04.03.1

A

To SR 17

Inv or Set 51
SR 17

Not 5117
Load 51
(To 5R)

5117

Elect Reset 51
Inv or Reset 51

Figure 41. Sense Indicator Position 17

During double-precision floating-point operations
the SI register is used extensively for temporary storage
of intermediate results. In these cases the S position retains its identity as an arithmetic sign.
Each sense indicator position is composed of a single
trigger-type position with a delayed output (Figure 41).
The delayed output holds the trigger information long
enough to allow proper input sampling during operations requiring SI register inversion. The only path for
information into or out of the SI register is by way of
the storage register.
Instruction Backup Register-IBR
(Systems 03.08.00.1-03.08.11.1)

The !BR is a 36-position trigger register labeled S, 1-35
and is used primarily during instruction overlap operations. As long as the instruction sequence permits, the
!BR contains the next sequential instruction to be executed. Because of the simultaneous readout feature
from both the even and odd core storages, the !BR is
able to obtain a next sequential instruction during the
same cycle that the current instruction is being placed
into the program register. Simultaneous memory readout also allows the !BR to obtain the next sequential instruction simultaneously with a data fetch (E) cycle of

the current instruction. The first case occurs during
"double-instruction" overlap and the second applies to
"extended-sequence" overlap. The IBR is also used as a
working register during double-precision floating-point
and ERA instructions. Figure 42 shows condensed logic
of IBR position 17.
Inputs to the IBR can come from: either the even or
odd storage bus when receiving a new instruction; the
accumulator during double-precision register swapping
or ERA operations; XAD(3-17) to !BR(21-35). In the latter
case, the index adder is either returning a modified IBR
instruction address or sending the incremented program counter value to the IBR for temporary storage.
Input gating is such that the outputs from the IBR
immediately follow the inputs from the storage bus.
This feature (the same as for the program register to be
discussed later) provides the earliest possible decoding
of instructions as they are read for core storage, and is
necessary for controlling overlap functions. This input
gating feature does not apply, however, for data arriving from the accumulator.
Outputs from the IBR can go to a variety of places:
IBR(S, 1-35) are gated to the SR during both overlap and
nonoverlap operations; !BR( S, 1-2) or IBR( S, 3-11) are
gated to the program register at a time when the current instruction has completed operation and the overlapping (IBR) instruction is to begin execution; IBR(18-20)
is sent to the tag register for indexing indications;
IBR(3-17) are gated to the index adders for index register
testing or modification during overlapping class A instructions such as TIX, TX1, and TNX; IBR(21-35) are also
gated to the index adders so that address modification
can be performed by the specified index register and
the new address returned to the !BR; IBR(21-34) are gated
to the MAR switch for an appropriate instruction or data
fetch memory reference.
Extensive decoding circuitry at the IBR analyzes the
overlapping instruction to determine the various aspects of overlap possibilities and their operation.

Gate 5B Even .... IBR
A

MF 5B 17 Even

Gate 5B

(4H)

Odd~IBR

A

MF 5B 17 Odd

(4G)

Gate IBR 3-17-XAD
To XAD 17
03.05.47.1

Not Hold IBR
AC17
IBR 17
Reset IBR

----~R(4H)

A

(3A)

To 5R 17

02.01.05.1

03.0B.05.1

Figure 42.

IBR

Position 17
7094 II System and Functional Components

43

Tag Register-TR
(Systems 03.05.22.1)

The tag register is a three-position trigger register. labeled 18, 19, 20. This register is used to inform the system which index register (XR) or registers are concerned
with a particular operation. The outputs of the tag register may be used singly or in combination to specify
the index register/registers required.
When operating in seven-XR mode, the tag register
uses all combinations of these tag bits to specify the
particular index register. Therefore, the presence of
more than one tag bit does not mean the oR'ing together of index register contents.
The 7094 II does provide compatibility with previous
systems having only three index registers. The normal
power-on status of the 7094 II is the three-xR mode. By
using the instructions LMTM and EMTM, the programmer has the ability to place the computer in either
seven-XR or three-xR mode, respectively. For a further
explanation, refer to the section on "7090/7094/7094 II
Compatibility" in Volume 3.

MF SB 18 Even
SB Even to TR
I Time or IA

------~~~J_--~--~~

SB Odd to TR

0

A

A (2A)

(To Tog
Decoding)
TR 18

Convert
A3(Dl)

IA Tgr

A
(4H)

Figure 43. Tag Register Position 18

44

Figure 43 shows condensed logic for TR(18). Inputs to
the tag register come from: either the even or odd storage bus during normal instruction loading from memory; the IBR during instruction overlap; or the storage
register during manual operations.
Outputs go to the tag register decoder circuits which
are conditioned by either three-xR or seven-XR mode of
operation.
Address Register-AR
(Systems 03.06.00.1-03.06.01.1)

The address register is a 15-position trigger register
labeled 3-17.
The primary purpose of the register is to provide
transfer or data reference addresses to core storage.
These references may be: a direct address; an effective
address as modified by an index register; an indirect
address; or a skip 1/2 address as required by skip-type
instructions.
The only gated input to the address register (Figure
44) is from the index adders which are used as either an
incrementing, modifying, or direct routing path from
other counters or registers. Positions AR(S, 16 and 17) can
also be forced on as a direct result of control logic resulting from certain trapping operations.
The address register is not a counter; any address
register incrementing is accomplished through use of
the index adders.
Outputs from the address register go to the index
adders when forming skip 1/2 addresses, or the MAR
switch when making references to core storage. The
output of AR(17) is sent to the MAR bus selection circuitry (Systems 03.06.28.9). This circuitry, depending
on whether AR(17) is a 0/1, controls address register
gating to either the even or odd memory during normal
mode of operation. When in diagnostic mode, however,
AR(17) becomes an integral part of the address; this latter condition, when applicable, forces a bit to be gated
to MAR(S) of either the even or odd memory. AR(S or 17)
also effects the "AR odd trigger" which in turn controls
gating circuitry for either the even or odd storage bus
into the CPU.
Indicator lights for the address register are located
in the CE test panel area of the operator's console.

Diagnostic Mode
AR 3
Not IBR to AR Odd T r

XAD~AR

CP Set A
Not Diagnostic Mode

Gate XAD
Latch ~AR

03.08.13.1

R(4E)
02.12.70.2

XAD Latch 17

CP Set D

PR Store
MAR Bus Selection (03.06.28.9)

E Time Early
03.06.02.1
03.06.01.1
Reset AR on Trap
Clear or Rst orlntlk Rst

Reset AR
03.06.02.1

Gate AR+XAD

Figure 44. Address Register Position 17

7094 II System and Functional Components

45

Program Counter-PC
(Systems 03.06.30.1-03.06.31.1)

The program counter (labeled "Instruction Counter"
on the operator's console) is a 15-position trigger register labeled 3-17.
The primary purpose of the program counter is to
keep account of the next sequential instruction in a
running program.
The program counter is not a counter; any incrementing or decrementing is accomplished through use
of the index adders. During normal sequential instruction execution, the new address associated with the
program counter is generated at 6-time of the cycle
when a reference is made to core storage. This new address is placed temporarily in either the address register Or!BR until I-time and then returned to the program
counter via the index adders. Note that when updating
the program counter at I-time, the index adders are
used as a routing path only, and do not affect the value
being transmitted.
The only gated input to the program counter (Figure
45) is from the index adders. As previously explained
for the address register, the index adders act as either
an incrementing, modifying, or direct routing path
from the other counters or registers. PC(S, 16, and 17) can
also be forced on directly by control logic resulting
. from certain trapping operations.
Note that either true or complement outputs can be
sent to the index adders. The true output is used dur-

ing incrementing, decrementing, or routing of the program counter to other registers. The complement PC
output is used only during overlap store operations to
check if the store instruction (in the program register)
is storing in the next sequential core storage location.
If this is the case, overlap is interrupted because the
overlapping instruction (now in the !BR) is being modified by the program and therefore invalid as it stands
in the !BR. The program counter is also sent to the MAR
switch when making references to core storage.
The output of PC(17) is sent to the MAR bus selection
circuitry (Systems 03.06.29.2) for the same purpose as
previously explained for the address register. This circuitry, depending on whether pc(17) is a 0/1, controls
program counter gating to either the even or odd memory during normal mode of operation. In diagnostic
mode, however, PC(17) becomes an integral part of the
address, and when applicable (for example, when
PC(17) equals 1) forces a bit to be gated to MAR(S) of
either the even or odd memory.
PC(17), indicating an even or odd status, also controls
gating circuitry from the even or odd storage busses
into the program register, storage register and !BR. It
must be remembered that the program counter is
stepped +1 prior to the time that this gating circuitry
is used. Because of this prior stepping, an odd PC indication, for example, gates the even storage bus to the SR
and PR, and the odd storage bus to the !BR. Storage bus
gating is explained later in the "Master I-Time" section.

XAD-+-PC
CP Set A

Gate Comp PC
~XAD

XAD Latch 17
Set PC

To XAD 17

Not PC 17
Gate PC .....XAD

To XAD 17
Reset PC on Tra
Clear or Rst or Int

03.06.32.1
PC 17

MAR Bus Selection

(03.06.29.2)

Diagnostic Mode
PC 3

A a

_N__o_t_Di......:ag::....n_os......:ti_c_M~od_e_ _---+~ A

PC Not Odd
PC Odd

(2A) 1-----.

03.06.30.1

FIgure 45. Program Counter Position 17
46

Index Registers-XR
(Systems 03.05.00.1-03.05.14.1)

Program Register-PR
(Systems 03.14.01.1-03.14.06.1)

The 7094 II has seven index registers. Each is a 15-position trigger register labeled 3-17. All seven XR'S are
identical and used primarily for address modification.
The 7094 II can be in either three-xR or seven-XR mode
of operation. In three-xR mode (multiple tag mode),
multiple tag bits cause an oR'ing of index registers.
Input to the index registers (Figure 46) is from the
index adders which are used, in this case, as either a
modifying or direct routing path from other registers
wi thin the CPU.
Individual positions of all seven XR'S have a common
output which is gated (under control of tag register decoding) to the index adders in either true or complement form. Because of the true XR outputs, it is possible to accomplish true addition in the index adders as
is required during TXI operations. True outputs are also
used to advantage during PXA, PXD, SXA, and SXD operations when true values are moved to the accumulator
or core storage.
Tag register decoding gates the complement outputs
of the specified index registers to the index adders for a
variety of operations, the primary one being address
modification. By addition of the complement XR valuc
to an address, the address is effectively reduced by the
contents of the XR.
There are many instructions which operate on the
index registers, thereby making these registers also useful programming tools for counting, word alteration,
and program loop control.

The program register is a ten-position trigger register.
The purpose of this register (labeled "Instruction Register" at the operator's console) is to receive and decode
the operation portion of the instruction to be executed.
Decoder outputs then initiate and control the computer
operation until the instruction is completed.
The operation code depends on the type of instruction involved and consists of either positions S, 1-2, or S,
3-11 of the instruction word. Positions S, 1-2 are routed
to PR(S, 8-9); positions S, 3-11 are routed to PR(S, 1-9).
Primary inputs to the program register (Figure 47)
come from: either the even or odd storage bus; or the
IBR depending on whether or not instruction overlap is
involved. Outputs from the PR follow (rise with) the
inputs from the storage bus. This feature of the input
gating provides the earliest possible decoding of instructions as they are read from core storage. (During
memory read-out, the S-bit is strobed before the 35-bit.)
Inputs from the IBR or op keys are gated in with a
clock pulse and, therefore, differ from SB input gating.
Certain trapping operations force specific PR triggers
on directly-for example, PR( sand 9 )-without having to rely on storage bus or IBR inputs.
During manual operations, the program register can
be entered from the console op keys to allow execution
of specific instructions set up by the operator or customer engineer.

XAD
Latch 17

4A

. . .:1.:.:.BRc..::2_ _ _...........,~

°

A

_1_BR_l_l_ _ _~

°

(4B

_O-,-p_K-,eY,-l_l_ _-..J

A

Gate Op Keys
Not IBR 1

Gate Camp
XR-XAD

Not XR 17

To XAD 17

,...---!~~.:.L..J"----I~

03.05.47.1
--'-....:.......t~

(lC)

A

0

MF SB 2 Odd

A

0

Force Store and Trap

XR (17)

A (lE)

03.05.14.1
Gate XR-XAD

Position 17

PR (9)

Not MF SB 1 or 2 Odd
MF SB 11 Odd
Gate SB Odd-PR

A (lD)

XRA

Not Hold PR

MF SB 2 Even

A

XRF(17)
Tag 6
XRG(17)
Ta 7

Gate IBR-PR

Not MF 5B 1 or 2 Even
MF SB 11 Even
Gate SB Even-PR

A

Tag 2

Figure 46.

°
°

e 1
--,N.....:o:..:...t-=..0c....K
C'-'.L..-_----.!
Op Key 2

XRA Set

PR 9 (To PR Decoding)
.;..:;Re=se,,-,-t-,-,PR,--_~ R(3C)
03.14.06.1
Gate PR to PR in 01 D

A

°

.:::.G.:::.:.ate:::....:.:::.:IBR~t:=...o-,-,-PR'-'.in:..:...O,,-,-l!::...D_ _~ A 2E) PR 9 to Gate D

Figure 47. Program Register Position 9
7094 II System and Functional Components

47

Outputs of the program register feed into the operation decoder circuitry (Figure 48). PR(S, 1-5) provides
the primary operation part and PR( 6-9) provides the secondary operation part of the operation decoding. During some instructions, the shift counter becomes an extension of the program register and provides a class and
unit address decoding.
Note that the 7094 II actually has two program registers: the "master" register, the one which receives inputs directly from the storage bus or IBR, is located in
A-gate of CPU-I (7111) and the second (slave) program register is the register that existed in the 7094 system. The "slave" register (Systems 03.04.00.1-03.04.06.1)
is located in D-gate of CPU-I and is not really a register
as such; converter circuit blocks have replaced the triggers so that these outputs follow the outputs of the
master register as gated to the D-gate (Figure 47).
Basically, the new program register provides new
and faster F-Ievel circuitry necessary in the 7094 II. The
old register provides PiN level operation decoding and
gating in CPU-2 for instructions that do not have such
critical timing requirements. The functions of the two
program registers and operation decoders cannot be
cleanly separated; therefore, both must be considered
when analyzing certain instruction operations.
Indicators at the operator's console are powered
from the old program register.
Shift Counter-SC
(Systems 03.14.14.1)

The shift counter is an eight-position count-down
counter labeled 10-17. Each position consists of a shift
cell (double latch) which allows simultaneous read-in
and read-out when counting.
The shift counter is used to count the number of
shifts or indicate the progress of operations such as
MPY, DIV, convert, floating-point add, shifting instructions, etc. The shift counter also functions as a class
and unit address decoder for operations that have a
primary operation of 76 (Figure 48).
The primary entrance to the shift counter is by way
of the index adders. The time at which the number is
gated is controlled by the operation being performed.
During POD 76 operations, the sc is set either during 15
time from PR decoding or at the beginning of L time
when the IBR is transferred to the PR during overlap.
During variable length multiply' or divide operations,
the count field is routed from the storage register via
the index adders in E time; during convert instructions,
the count is routed in the same manner in L time.
The shift counter is also used during single and double-precision floating-point add and subtract operations (POD 30). During these operations the shift counter
is used in lining up characteristics. The characteristic
difference between the numbers in the SR and AC is
48

Primary Operation
Decoding
(±OO ...

± 76)

Class Addr
Decoding

Secondary
Operation
Decoding
(00 ~ 17)

\

(00 .... 36)

Unit Addr
Decoding
(00 -+ 17)

v
Operation Decoding

Figure 48. Operation Decoding

computed in the main adders, AD(I-8), and then gated
directly to SC(1O-I7) to control the number of shifts necessary to align the fractions.
During multiply and divide operations (other than
variable length), a constant is forced into the shift
counter to control the number of iterations. In the case
of a floating-point operation, 33 8 is set into the shift
counter; for a fixed-pOint operation, 43 8 is set into the
shift counter.
Note that the 7094 II actually has two shift counters:
the "master" register, the one which receives the inputs
just described, is located in A-gate of CPU-I and the
second "slave" shift counter is the counter that existed
in the 7094 system. This "slave" register (Systems
03.04.14.1-03.04.17.1), located in D-gate of CPU-I, is not
really a register as such and has no counting capabilities; converter circuit blocks have replaced the triggers
so that these outputs follow the outputs of the master
counter as gated to the D-gate.
As for the program register described previously, the
new shift counter provides fast F-Ievel control and
counter circuitry necessary in the 7094 II. The old register, again, provides piN-level controls for instruction
operation in CPU-2; the main function is in class and
unit decoding and POD 76 controls. The functions of the
two counters overlap somewhat; therefore, both must
be considered when analyzing certain instruction operations.
Indicators at the operator's console are powered
from the old shift counter.
Stepping the Shift Counter

Figure 49 shows condensed logic for positions 10-17 of
the shift counter. Remember that the shift counter is a
self-contained true binary count-down counter and
does not rely on the index adders for decrementing as
is necessary with the address register and program
counter.

~
,. (2E)

-

SC 10

Insert SC 10

~-r-

o

r-+--' __

HoidSC10

A
18

Shift
Cell

~

No'

Lc

10

SC 10

-""

03.14.14.1

0

~; -0 (31)
'--

~
.(2D)

TO Tl T2 T3 T4 T5 T6 T7 T8 T9 TlO T]] T12 T13 T14

SC (13)
SC (14)
SC (15)
SCj16L
SC (17)

N F N F N F N F N F N
N N N N N N N N N N N

Value
(10)
(11)
(12)

33
F
F
F

23 21 17 15
F F F F
F F F F
F F F F
N N F F
F F N N
F F N N

13
F
F
F
F
N
F

11 7 5
F F F
F F F
F F F
F F F
N F F
F N N

31 27 25
F F F
F F F
F F F
N N NN
N N F F
F F N N

SC
sc
sc
SC

3
F
F
F
F

1
F
F
F
F

F
F

F
F

0
F
F
F
F
F
F

F
N

F
F

F N
N N

1

~
(10)

--

Set SC 10

SC 11

Hold SC 11

0

~ r--

0

A
19

~ r-0 (3H)

~

,----

-

.....
.....
~

A5

-~

-

-

HoldSC 12

~cell

(4A)

~

~

A6

~~

Y. --'--'(5B) f -

I

-

Set SC 12
SC 13

~

~

"-

r-=!:

== -

Hold SC 14

0 A
22
(41)

-0 -

r-=!

~
~

,

r--

0 16

t-- ~r-r-

~~(4H)

=:

Hold SC 15

SC Reset
Reset SC

SC 15

~Cell
~-

SC 15

Set SC 15

Insert SC 16

.---

HoldSC16

0 A
24
0

,

~

!. 0

(2G

~

I

J

Shift
Cell

--

J"':!

Not

1

SC 16

SC 16

03.14.14.1

Set SC 16

~-

Step By 1

'---

33 to SC
FAD AD~SC
XAD to SC Set Hold
Mpy Div 43 to SC

1

03.14.14.1

~ r--

2

A (3E)

Not

-"--

-.--------.
~Stepsc

..... r--

~

~OA
r-- 23
0

(3D)

r---

SC 14

Shift

',---

03.14.18.1

'Not lsc 14 ...

Set SC 14

~

(lC)

Shift
Ceil

03.14.14.1

Insert SC 15

(5E)

(4D)

...

SC 13

SC 14

,.--

Insert SC 14

0

~

SC 13

0 (4F) Set SC 13

A (2C)

~

Cell

1

~03.14.14.1

03.04.15.1

~

Not

Shift

0 A
r-- 21
0

&.r--

~

Insert SC 13

HoldSC13

1

t--

-. A O

SC 12

03.14.14.1

1

14

Step By 2

SC 12

~~

33 to SC

~

1

I~-

0 A
20

r:~3G

Mpy Div 43 to SC

7

Not

Shift

.--r--

SC 11

SC 11

SC 12

c=:'0

1

Set SC 11

Insert SC 12

(3B)

--

Ir!

Not

03.14.14.1

A (4C)

.---

Shift
Cell

'---

T

N = On
F = Off

-

Insert SC 11

~
-(5A)

~017
(4A)
~

1

SC 17

Hold SC 17

r--

0

~~I"""l
0
(2C/2E

~ ro

0 A
25

...

RI to SC Line 1 and Line 2
CP Set C

~

Insert SC 17

o

(4F)

~

Shift
Ceil

Not

1

sc 17

SC 17

03.14.14.1
Set SC 17

Oti4:16.1

Figure 49. Shift Counter Stepping

7094 II System and Functional Components

49

Figure 50 shows a sequence chart of the shift counter
stepping to zero from a count of seven.
Note that stepping the shift counter is conditioned
by either «step by I" or «step by 2" control circuitry.
Whether the stepping is by one or by two depends on
the particular instruction being executed. Stepping by
two is allowed during multiplication, floating-point
add/subtract, and shift-type instructions; stepping by
one must be performed during divide and convert-type
instructions.
Each position of the shift counter has control circuitry affecting three inputs to the shift cell ("insert sc
17," «set SC 17," and «hold sc 17"). The «insert" input is
activated only when that particular position is to be
fumed on. The "set" and "hold" pulses are both CP set
pulse inversions of one another, and generated from
the same control circuitry (OA blocks) only when the
status of that particular position is to be affectedturned off or on.
Whether a shift counter position is to be changed or
not by a set/hold pulse combination is determined by
the next lower position. If the next lower position shift
cell is to be set on, the state of the next higher position
will be reversed. This rule applies for both single and
double stepping.
When stepping large numbers, the ripple effect from
position to position can become too great for reliable
operation. To reduce this ripple time, look-ahead circuitryhas been inserted at the controlling circuitry of
SC(IS).

Note that SC(16) alternately changes state between
and OFF during double stepping and SC(17) alternates state during single stepping. The primary difference between single and double step operations is
where the step pulse control comes into the counter;
for example, SC(17) for single step and SC(16) for double
step. Double stepping is, therefore, the same as single
ON

50

stepping except that it occurs one rung higher on the
ladder.
Assume that a count of 338 has been set into the shift
counter and that counting is by 2. The initial status of
the counter with 33 8 is: positions SC(17), SC(16), SC(14),
and SC(IS) are in the ON position; all remaining positions
are OFF. Because the original number is odd, each stepping of the counter produces an odd result. If the original number was even (68 , for example) each double
step would, in turn, produce an even result. Note that
all during double stepping, SC(17) remains unaffected.
The first step reduces the counter from 338 to 31 8 •
This reduction is accomplished by reversing the state
of SC(16) from ON to OFF. SC(16) being initially on, blocks
A7 from activating "insert sc 16." Set and hold pulses,
however, are produced at CP set time by OA24 with the
overall effect of inserting a zero into SC(16).
The second step which reduces the counter from 31 8 ,
to 278 initially finds positions SC(17), SC(14), and SC(IS)
on; and all remaining positions off. SC( 16) being off conditions A7 and 0 16 to change the state of SC(16) to ON:
«Insert sc 16" conditions OA 23 to produce set and hold
pulses for SC(15), and also test the initial status of SC(15)
at A15 • SC(15) being off, activates "insert sc IS" to flip
SC(15) on. "Insert sc IS" also conditions SC(14) circuitry
to produce only the set and hold pulses thereby turning
SC(14) off. At the end of the clock pulse, positions SC(17),
SC(16), SC(15), and SC(lS) are on and all remaining positions are off.
This pattern of double-stepping continues until all
shift counter positions except SC(17) are turned off. As
the count is reduced from three to one, «step by I" control circuitry replaces "step by 2." "Step by I" tests the
status of SC(17) at A9, but SC(17) being on blocks «insert
sc 17." A set and hold pulse is produced at OA 25 , however, with the result of turning SC(17) off. At this point
the shift counter equals zero and all stepping controls
are dropped.

System Page Test Point

line Name

Level

02. II. 79.1

02A4E13D

Shift Gate

-N

03.14.20.1

0lA4G26C SC 20r More

-F

03.14.20.1

01A4G23F

SC Eq 1

-F

03.14.18.1

0lB2B28B

SC Zero Slow

-F

03.14.18.1

01A4D24D

Step by 2

-F

03.14.18.1

01A4G25B Step by I

-F

03.14.18.1

01A4A25B

Step SC

-F

03.04.16.1

01A4F28D

CP Set C

-F

03.14.14.1

01A4E24B

SC 15

-F

03.14.16.1

0lA4F27G Insert SC 15

-F

03.14.16.1

01A4F27F

-F

Set SC 15

03.14.14.1

01A4F20C

SC 16

-F

03.14.16.1

0lA4E27A

Insert SC 16

-F

03.04.16.1

01A4F27C

Set SC 16

-F

03.14.14.1

01A4E26B

Set SC 17

-F

03.14.16. ]

0lA4F25B

Insert SC ]7

-F

03.04.16.1

01A4F27E

Set SC 17

-F

(7)
I

(5)

2

(3)
3

(I)
4

(0)
5

6

7

:'I

I--

.

h

~

-.
1-h

~ ~~ ~

I.

I--I--

h

---

r-

h.~ ~
'-

Figure 50. Shift Counter Timing Chart

7094 II System and Functional Components

51

Main Adders-AD
(Systems 02.02.00.1-02.02.19.1)
The adders in the 7094 II are made up of basic building blocks shown in Figure 51. The adders perform
arithmetic functions and are involved in many internal
data transfers within the computer. Inputs to the basic
adder circuit may be from either the accumulator or
storage register. Outputs from the adders go to the accumulator, MQ, storage register, and shift counter, depending on the operation involved.
The adders are comprised of 39 individual adder
units, or bit positions. These positions include AD (Q,
P, 1-8, 9Q, 9P, 9-35); AD (Q and P) are used for overflows which might occur during certain arithmetic or
logical operations. AD (9Q and 9P) are used during
floating-point arithmetic.
Individual Main Adder Position

Figure 51 shows condensed logic for position 35 of the
main adders. The primary objective of an adder position is to determine whether or not there is a sum output. To determine the output, three values must be
analyzed; two adder inputs and one carry input.

Input A

Gate AC-AD
AC 35
Gate Cam AC-AD
Nat AC 35

Systems 02.02.19.1

A °1
A
(4A)
Propagate 35 (Either/Both)

Input B
Gate SR-AD
SR 35
Gate Comp SR-AD
Not SR 35

A °2
A

Generate 35 (Both)

(4B)

Exclusive OR 35

r

Comp Exclusive OR 35
(Both/Neither)

Carry In
AD Sum 35

Exclusive OR of Adder and Carry

Adder
Inputs

Adder
Outputs

0

1

0

1

0

1

0

1

SR

0

0

1

1

0

0

1

1

AC

0

0

0

0

1

1

1

1

Carry

-

+

+

+

-

+

+

+

Propagate 35

-

-

-

+

-

-

-

I

Generate 35

-

+

+

-

-

+

+

-

Exclusive OR 35

-

+

+

-

+

-

-

I'

AD (Sum) 35

+ Indicates an active logical state
-

Indicates an inactive logical stale

Figure 51. Main Adder Position 35
~

52

True or complement inputs from the storage register
and accumulator are gated into the adder at gate circuits AO l and A0 2 • Either/both adder inputs being
active produces "propagate 35" at 0 3 ; both inputs being
active produces "generate 35" at A4 • Block A05 performs an exclusive-oR test of the adder inputs. An input
exclusive-oR condition occurs only when either one but
not both of the inputs contains a 1. A0 5 performs the
test by looking for a "both" (generate 35) or "neither"
condition which is actually a complement exclusive-oR
function.
The in-phase (complement exclusive-oR) and out-ofphase (exclusive-oR) outputs of A0 5 are tested along
with input carry conditions in a second exclusive-oR
circuit configuration to determine the actual adder
sum output. One adder output condition occurs at Aa
with "no carry" and "EX OR 35" (case 1 below); the other
adder output condition occurs at 0 7 and Os with
"Comp EX OR" and "Carry" conditions, respectively
(Case 2).
CASE

1

CASE

2

(a)

(b)

1
0
0

0
1
0

Input A
Input B
Input Carry

Adder Output 1

1

Adder Output 1 (1)1

Input A
Input B
Input Carry

(a)

(b)

0
0
1

1
1
1

Taking the other four possible combinations of carry
and adder input conditions will prove that an adder
sum output is not produced. All combinations are summarized in the chart on Figure 51.
Main Adder Bit Carry Lookahead

Each adder position, besides being able to determine
a sum condition, must be able to provide necessary carries to adjacent positions. For determining possible
carries, three additional lines are generated from each
adder position: propagate (P), generate (G), and exclusive-OR (EX oR)-Figure 51.
The output of 0 3 , "propagate 35," is active when
either one or both of the adder inputs are a 1. With
these input conditions, an input carry must logically
be passed on, propagated, to adder position 34. This
carry requirement is proven below by taking the input
combinations of 0-1,1-0, and 1-1 and adding a carry; in
each case, a carry results. (Also, see chart on Figure 51.)
(a)

Input A
Input B
Input Carry

(b)

(c)

011
1
0
1
1

1

1

10

10

11

The output of A4 , "generate 35," is active whenever
both inputs to the adder position contain a 1. With both
inputs active, the adder position has the ability to generate a carry from its inputs alone independent of
whether or not an input carry is furnished from an

outside source or a lower adder position in the group.
Proof of this carry is easily obtained below and summarized in the chart on Figure 51. Note in the chart
that "generate 35" is not dependent on the input carry
status.
(a)
(b)
Input A l l
Input B
1
1
Inpu t Carry
0
1

10

11

The output of A0 5, "EX OR 35," represents an adder
input exclusive-oR condition; either one but not both
inputs are a 1.
With the propagate, generate, and EX OR conditions
just explained, individual adder bit carry lookahead
can be developed. This lookahead is shown by the
solid lines and logic in Figure 52.
Using adder 35 as an example, a "carry in 34" will be
generated if: adder 35 can generate a carry; or adder
35 can propagate and there is a carry into position 35
(K in). Note that the lookahead circuitry becomes more
involved as it progresses from the lowest-order to the
highest-order adder position within the adder group.
The "carry in 31" circuitry uses exclusive-oR inputs
instead of propagate as used in the lower-order positions of the adder group. This change was made because of circuit loading; the basic circuit logic, however, remains the same.
Note in Figure 52 that there is no individual adder
lookahead circuitry for carry generation into adder 30.
Adder 30, which is the low-order position of the next

group, receives its carry indication from the group
lookahead circuitry.
An important point to remember in the carry lookahead concept is that each input carry generation is
dependent solely on inputs to individual adder positions; there is no "ripple" effect from one adder position to another as is characteristic of slower type adders.
Main Adder Group Carry f.ookahead

If the lookahead were continued as explained in the
previous section, the circuitry would soon become too
large, unwieldly, and expensive. Therefore, to speed
up adder operation and facilitate lookahead, the adder
has been divided into seven groups as follows:
GROUP NUMBER

ADDER BIT POSITIONS

1
2
3
4
5
6
7

35,34,33,32,31
30,29,28,27,26
25,24,23,22,21,20
19,18,17,16,15,14
13,12,11, 10,9,9P
9Q,8,7,6,5
4, 3, 2, 1, P, Q

Each group contains either four, five, or six adder
positions. Adder position 9Q is shown in group six but
actually plays no part in the lookahead function.
The primary objective of the group lookahead is to
determine whether or not carries should be introduced
into the low-order adder positions of higher adder
groups. Lookahead circuitry for group 1 is shown as
dotted lines on Figure 52, lookahead circuitry for
group 2 is shown in Figure 53. Overall lookahead for
all seven adder groups is shown as solid lines on Figure 54.

7094 II System and Functional Components

53

1011';-----

I'~-----

Adder Positions 31-35 - - - - - _
....

Bit Corry (02.02.28.1)

--------------l,~I~I(----Generote

(02.02.36.1)

------;,~I

Propagate 31

----------,

Adder 31

I
I

Generate 31

r-----------I------------- - 02.02.17.1

r

AD Sum 31

~-----u_=

t------------ - -i - - - j - - -- - - - - - - - - - ""~ w,

:

X32 r---X33
A

I

'"G35

i
32

1

1
I

02.02.17.1

r

1

I

G33

I

I

AD Sum 32

I

I

Adder 33
Generate 33

~

AD Sum 33

I

In 32

(4D)

P33~

G33~
-I (3D) _ _

I

I

~

I
I

A

~

Propogate 35

~

,

(3C)

~-

G34~
·1 (3B)

I

o

Carry

(2B)

In 33

~

r-----------

t-t-

I

A

,----------- -

I
I

(4F)

~
Kin

(4B)

G35

A

......

0
Carry
(3A) In 34

(4A)

L1=t-+--r
L-t-.-

-P34
- - --P3:s
-----------------

L-.l_ - - - - - - - - - LI_

"N,"" DO"

~

~ ~,~
~-

G35

W'
J7J

i I I I : r--------- - - -

0

L

-------

1-------- - -

----

I

I

~

P34

t-Ll- , - - - - - - - - - - - -

I I

Generate 35

~ 'd",'," 0'"
A

I

>- Kin

I
I I t- ' - - - - - - - - - - - - ~III_r / - - - - - - - - - - I
I II i II
I I I
I

AD Sum 34

mrr-;El

P34

~A
(4C)

I

~JJ.

Excl usive OR 34

f-------

f1,
----

AD Sum 35

02.02.19.1

Figure 52. Group 1 Adder Carry, Generate and Propagate

54

Carry

G3<1 (:E)

i II
i1~

Adder 35

Carry In

I

II

Generate 34

Gate SR . . AD
SR 35
Gate Camp SR . .AD
Not SR 35

I

G35

0

(lD)

~r-iil r--

02.02.18.1

J

1

A

P34

t--!.l r - r - - - - - - - - - - I +---1-1-- - - - - - - - - - I I t-r-- 1 - - - - - - - - - - - ----------

Adder 34

Gate AC+AD
AC 35
Gate Camp AC . .AD
Not AC 35

1

I

(4E)

P33

I

I
I

Exclusive OR 33

Propagate 34

r

(:G)

J

P34
P35
r- Kin

I I
II
I I

r

Carry

~

I\

------

~ ''') '""

G32ID
(2F)
_

II

02.02.18.1

~
0

h---- / - - - - - - - - I t---- - - - - - - - - H- -+,--- - - - - - - - - - I

Exclusive

OR 32

Propagate 33

(Carry In G2)

X32~

I

I
Generate 32

(3G)
X32 ' - - X33 :.J A
G;L.(J (3F)

.-1- L-:::l

I
Adder 32

1--------

Generate or
Propagate G J

(3D)

X32 , - - A
X33
X34
X35

I
~opagate

o

Group Lookahead Circuitry---

(4G)

Lookahead for both groups 1 and 2 is shown because of their difference in logic. The dotted lines in
Figure 52 show group 1 lookahead. Six sets of conditions can produce an output from the group: first,
AD(31) can generate a bit alone; second, AD(32) can
generate a bit and AD(31) can propagate the bit; etc.
Note that the logic becomes more involved from top to
bottom; the last AND circuit indicates that an input
carry (Kin) will produce a group carry if AD(31-35)
have the ability to propagate.
Group 2, as well as the remaining groups 3-7, produce two outputs; «any generate G2" and «generate or
propagate G2." Both conditions must be active to produce a carry into the next higher group. Design of thf'
adder lookahead is the result of Boolean algebra, and
may not, therefore, seem immediately logical and
straightforward. This design, however, performs the
required task of adder lookahead in a more efficient

G30 " " " G29 ~ 01
G28 ...
G27:' (3A)
G26 "" (3B)

Propagate 26
Generate 26

1

and economical method than other «more straightforward" configurations.
The adder group output, "any generate G2" results
at 0 1 (Figure 53), from any or all adder pOSitions being
able to generate a bit (both adder inputs are a 1).
The "generate or propagate G2" output from 0 7 results from the following conditions: first, all adder positions are able to propagate at A6; second, each position, except the low-order adder position, has the
ability to generate and have this bit propagated
through the remaining higher-order adder positions at
A5 , A4 , A3 , and A2 • The ability of the low-order adder
position to generate and have its bit propagated by the
remaining adder positions is not defined specifically by
the function «generate or propagate G2." This latter
case is accounted for, however, because if AD(30) can
generate, it can also propagate. P30 activates A6 and
G30 activates 0 1 ; therefore, both of the group outputs
are active and a carry is passed into group 3.

Any Generate G2

~

ID-~

G26...

--=-=.:..:.::.:...::.:..=.-:=..::..-----t-t++,....----;l~

A2

(4B)

_L-_~---'

Propagate 27
Generate 27

P26

...

G27

~

Propagate 28
Generate 28

P26
_____
P27 ",.I A4
G28 --J (4D)

Propagate 29

P26
P27
P28

A3
(4C)

...

,.

r-!

~,...--­

"""

~

AS

-=G_e_ne_ra_te_2_9_ _-+-+++-t-4--G_29---:J~~ (4E)

-

(3D)

Generate or
Propagate G2

...
,.

_

' I -

Propagate 30
Generate 30

P26

... _

P27
P28
P29
P30

...
""
...
""

A6

(4F)

i---

02.02.35.1

Figure 53. Group 2 Generate and Propagate Lookahead
7094 II System and Functional Components

55

Adder Lookahead

GJ
GJ

_, •

G~~~:;..",

Group Lookahead

•

I.

___________ :~02~~~ _________ ,

Iol G~e~t~r~~~e_~?

~[!]

.,.02.4011

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ll-fOl

~r--------------------,0

gQ
[2]

~--11r-~
rr:

I
I

I
1IIIIr
1IIIII
I1I1I1
III

GJ
I
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .J
02.02.31. 1

GJ

o
~

Carry

Q

i11111
III

0

Any Generate G6

~

II I
III,

~ L2.J

" GJ

1I1I
III

-GJ --------0----

I: I

02.02 .32 .'1--- rn~mgj~[:l

I'II

Any Generate G5

'I
I

I
Generateor

-0

o

A
I

0

I

:~~~a~,:J._~I_I_-+_I_I-I_I_~~~-=_==_==~~==-=-=-= ~#-~J

-----------02:~33:i----

o

0

'II

Gen-

~

o

I

erateor

PropagateG4

I
I

:

-~----------o~~7----

C32:J

0

Any Generate G3

I

[EJ
~

I
I

J~

I

~
r----------02~.35.1-----~
0

:,:~: or
L---S---'Propa-

I
I

(5~)

(ts)

I

II

:

II

I
I

II

I
II

II

: I t:t~_o

Carry In GR 3

J==rFffiF==~~~==El
g~~
- - - - - - - - - - - - - - - - - - - - - , ~t-il.-----L-.....J------+t------------------'fl-TI-

(4F)

I1II1I

I

--==~~~~===El

1-::Jt~~Ir~~~

I1II

L

LL - -

~-L_~Pr..:::!op:::::ag:!:a.:.::te....:::G:..:.1----+-------=C:..:.ar::..!.ry....:.l:..:...nG..:. R. . :._
2 _---+-- __ =:_

Figure 54. Main Adder Group Lookahead and

Q

Q Carry

I

I 1/: /
II III
1111/
/IIILy
II L~-

Generate or

~

I

I: II

i

II

JI
- I
I

IIII
I II
02.02.36.1

1/
II

,

Ii II

56

III

I

~

G
M

I

1

I II

Any Generate G4

~0
e r;-:;r
"

I

(4G)

Carry Lookahead-----

I
I

I
/

I
__ .J

02.02.40.1

Figure 54 shows all adder group carries. Group 1
having the ability to either generate a bit internally or
to propagate a Kin produces a "carry in GR 2." Note
that this same carry line also conditions the top OR circuit in each of the higher group lookaheads. Depending on the inputs to the remaining adder positions, this
carry from group 1 may be propagated through the
rest of the main adder.
A carry into group 3 can result from two conditions:
group 2 can generate a carry internally, or group 2 can
propagate a carry from group 1. Taking the first case,
both "any generate G2" and "generate or propagate
G2" are active and condition the top leg of 05B and
05.A, respectively. In the second case, group 2 produces
only the "generate or propagate G2" line as input to
05.A. However, the carry from group 1 conditions the
bottom leg of 05B; A4B is satisfied and a carry is introduced into group 3.

Producing a carry into higher-order groups becomes
progressively more involved but the basic concept just
described remains the same. Note that each high-order
group is conditioned by the outputs of each lowerorder group. In this manner simultaneous decisions can
be made at each group lookahead; no "ripple" is involved from one group to another.
Q Carry Lookahead

The carry from the main adder, Q carry, is used in testing and logical operations as well as during arithmetic
instructions. The speed at which a Q carry can be obtained becomes important in many operations. Therefore, adder group outputs are also used in Q carry
lookahead circuitry (shown as dotted lines in Figure
54) to obtain the earliest possible Q carry indication.
This lookahead follows the same philosophy described
in the preceding sections.

7094 II System and Functional Components

57

Index Adders-XAD

(Systems 03.05.40.1-03.05.47.1)
The index adders (XAD ) in the 7094 IT perform a variety
of functions such as:
1. Address modification on the instruction in either
the storage register or IBR. In either case modification
is from an index register as specified by the tag portion
of the instruction concerned.
2. Tests on or modification of index registers as required by TIX, TNX, TXH, TXL, TXI (class A) instructions.
3. Incrementing the program counter, address register or address portion of the IBR.
4. Providing an address reference to MAR during
overlap operations.
5. Producing the required data reference addresses
during convert instructions.
6. Providing direct data flow paths to or from the
program counter, address register, index register, storage register (positions 3-17 or 21-35), instruction backup register (positions 3-17 or 21-35) and shift counter.
Two data input gates are provided to the index adders; input A and input B (Figure 55). These inputs are
divided such that one half of the input data always arrives at input A and the other half arrives at input B.
During address modification, for example, the address
arrives at input A and the modifying index register
value (complement) arrives at input B; during incrementing, the PC, AR, or IBR arrive at input A and a
"hot 1" is inserted at input B of XAD( 17).
It is possible to insert "hot 1's" into either all positions of the index adder or just XAD( 17); the first case
causes decrementing of the input value (-1); the latter
case causes incrementing of the input value (+1).
When the index adders are being used as a data
path, outputs go directly to SR(S-17), SR(21-S5) or the
shift counter. During instruction overlap, the index
adders supply a second memory address to the MAR
even/odd switch.
Note that during address modification, if no tag (tag
of 0) is specified, 1's are gated into all index adder positions along with a carry into XAD(17). These ones effectively add a zero to the incoming value; therefore, the
output value is the same as that supplied by the storage
register or IBR.
An index adder latch (XAD LTH) is used in conjunction with the index adders. The latch acts as a common
delay (second half of a shift cell) in the circuit for
modifying the index registers, program counter, address register and instruction backup register. These
registers consist of triggers (not shift cells); the delay
therefore, allows proper operation on successive clock
pulses.
The XAD latch is "free running" and always copies
the contents of the index adders at the end of each
58

clock pulse. The receiving register receives the new information immediately thereafter which is slightly into
the following clock period.
When gating from the index adder latch to the XR,
PC, AR, or IBR, four additional triggers are required as a
short-time memory device to remember which register
is to receive the output from the XAD latch. This remembering is necessary because the gating line to the
index adders (XAD to AR, for example) will have already dropped before the new output can be gated
from the XAD latch to the address register. Figure 44
shows condensed logic of the gating sequence for data
flow from the index adder latch to the address register.
Index Adder Position

Figure 56 shows condensed logic for index adder positions 3, 4, and 17. As can be seen, the index adder is almost identical to the main adders discussed previously.
The main difference between the XAD and AD is the
number of inputs and outputs used. Also, because of
the type of circuit cards used, some logic blocks appear
as micro blocks whereas others appear as macro blocks.
The basic function remains the same-that of determining whether or not there is an adder sum output.

SR 3-17
SR 21-35
IBR3-17

AR

True PC
Compl PC

' - - - - - - + T o SR 21-35

To MAR Switch
(3-16)

Figure 55. Index Adder Routing

The three basic inputs to the index adder are: input
A, input B, and an input carry. As already discussed,
the XAD inputs are divided so that the two values to be
added arrive at inputs A and B, respectively. Logically,
there never should be more than one input active at
either input A or B at any given time.
Using XAD ( 17) in Figure 56 as an example, there are
two A-input gates (AO l l and A0 12 ) tied together to
form a 6-way AND-OR function. Two B-input gates also
exist (A0 13 and A0 14 ) but are not oR'ed together directly. The difference between the A- and B-inputs is
due to circuit card usage and not because of logic.
Any data input being active (Ad A2/BdB 2) produces
"propagate 17" at 0 19 . Either AdA2 being active at
0 15 , and either BdB2 being active at 0 16 produces
"generate 17" at A20 . These propagate and generate
lines are used in the adder lookahead circuitry to be
discussed later.
The circuit combination of A17 , A18 , and 0 21 performs an exclusive OR test of the two data inputs. The
in-phase (active) output of 0 21 indicates a "not exclusive OR" state (not A"'V'B); the A and B inputs are
either both O's or both 1's. The out-of-phase (inactive)
output of 0 21 indicate an "exclusive OR" state (A"'tB);
either A or B is a 1, but not both. In the main adders,
loading conditions required that this exclusive OR function be used in adder lookahead. In the index adders,
however, loading is not as great and the exclusive OR
function is not required outside of the immediate
adder positions.
The carry into XAD(17) affects only the sum output.
The input carry is, therefore, combined with the output conditions of 0 21 in a second exclusive OR network
consisting of A22 and OA 23 . Taking various examples of
A, B, and carry inputs should quickly prove the circuit
validity.

Index Adeler Group Carry Lookahead

The 15 index adder positions are divided into three
groups of 5 positions each as follows:
GROUP NUMBEB

XAD POSITIONS

1
2

17, 16, 15, 14, 13
12, 11, 10, 9, 8
7,6,5,4,3

3

The object of dividing the index adders into three
groups is to speed up adder operation and simplify
lookahead circuitry. Group lookahead circuitry, as
shown by solid lines in Figure 58, determines whether
or not carries should be introduced into the low-order
positions of groups 2 and 3. The lookahead circuitry
for group 1 is also shown by dashed lines in Figure 57.
Lookahead circuitry for groups 2 and 3 are different
than group 1 but identical to that of the main adder as
shown in Figure 53. Because of the similarity, see
"Main Adder Group Carry Lookahead" section for a
more detailed explanation.
Index Adder 3 Carry

A carry from the index adder, "XAD 3 carry," is used
primarily as a test for successful transfers when executing class A instructions (TIX, TNX, etc.) from either
the program register or IBR.
Direct outputs from all three index adder groups are
used in detecting an XAD ( 3) carry. The circuitry is
shown as dashed lines in Figure 58 and is simply an extension of the lookahead circuitry used for groups 1 and
2. No XAD( 3) carry trigger is necessary; the circuit output is active long enough to allow all tests to be made.
Again, carry lookahead is dependent solely on inputs
to the individual adder positions; no individual adder
or group carries are involved.
Index Adder Compatibility

Index Adder Bit Carry Lookahead

As was explained with the main adders, each index
adder position must be able to provide necessary carries into adjacent positions. For determining possible
carries, two lines are produced from each adder position: propagate (P) and generate (G).
The output of 0 19 , "propagate 17" (Figure 56), is
active if any A/B input is a 1. The output of A20 , "generate 17," is active if both A and B inputs are 1's. With
the propagate and generate lines, individual adder bit
carry lookahead is developed as shown by the solid
lines in Figure 57. This lookahead circuitry, again, becomes progressively more involved as it progresses
from the lowest-order to the highest-order adder position within the adder group.
No adder bit carry lookahead circuitry is provided
for XAD(12). XAD(12), which is the low-order position
of the next group, receives its carry indication from
the group lookahead circuitry to be discussed next.

When executing 704 or 709 programs under compatibility mode, XAD ( 3) and XAD ( 4) must be effectively bypassed. This bypassing can be accomplished by forcing
the XAD position into a propagate condition (Figure 56).
When the memory nullify trigger is on, "memory
null" is applied through 0 6 to activate "propagate 3."
Any resulting carry up through XAD ( 4) will, therefore,
logically be "passed through" XAD ( 3 ) and give an
XAD( 3) carry. Because XAD( 3) does not theoretically
exist at this point, any possible sum output must be
blocked. This blocking is accomplished at the output
of OA24 by dot AND'ing with a "not memory null" condition.
If the 16K/24K switch on the CE panel is in the 24K
position, 24K of memory is available to the I/O compatibility program and 8K available to the executing
program. Under these conditions, XAD( 4) must also be
bypassed and the XAD ( 4) sum blocked. The methods
used are the same as those described above for XAD(s).
7094 II System and Functional Components

59

Input AI
AR 3
IBR 3

r---------~~~<3;r--

XAD 3 (03.0S.40. I)

.-----------+l~

~1~BR~2~1~_____~_H~====~~~~-~~~(4A),~_+~------~~r_~~_,

I

~

'-'-:Input A2
r-- f----4
~S~R~3_ _ _ _ _-+~~~-----+l'~ 04

0
(3A) ~_ _ _ _ _ _ _ _ _ _ _ _P_r_op_a_g_at_e_3_~

r-r--_-_-_-_-_-_-_-_-_--'--:--,-::J

r -_ _ _~r-'-

~SR21
~~
..!.P~C~3~_ _ _ _+++++-+_ _~ A (4B)

'

~
0
(2B)

A

~

(IB)

,-I,;,-

n ut B3

r-ill
06
(4D)

~

Generate 3

~--.~~J

Input A2
~~-+-l-+-~',.....:--:-ATOa r----

r-

I

0
(3A) ~-------------P-ro-p-a-ga-t-e-4-~

e-+--I-I-I----',~t_;

.:.P-=C_4~_ _ _ _l_+++!-·+--_++++++_-'~~t-; (4B)I--+.e-t-t--:~r---oI;;;~

Not PC 4

r-r-'-r-- -

NotXR4

~7

(2B).--.

~r==o=rI
(~) 1~~.~----------G-e-ne-r-at-e-4-~~
.
~ (3B) ~ T

..:..=---'---'------+-4++-I-+--+-++_'~ A 09

"':":'~"':':"'-~--+-4++~I----'+-+4--+lfXR4
~ A (4C)fOnes to XAD

_24_K_M_o_de--'.(S_w_it_c_h)_ _ _-.t,

J;;pu'ts2

~i) f--=2_4K:..:...:.N~..:.U~II~~~~~~:~~~~~:::::;:~:~::::'l_'~"'4'::~oL)

I~ ~
(2C)

~~~
(3C)

j -_ _----' ->. ' - -

1~

02.12.76. I

~

~-+---===---~r--r-

(IC)

~

~NO Carry _I

Carry In 4

lOA

(:D)

...

-.C~ ~:D XAD 4 Sum
~'-'--

In 4
I Not 24K Memory Null

'-------------~(IE)

1'-- _
I . . . . . Dot

AND

----- --- -----H-++-++.-+-H'--. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XAD 17 (03. OS. 47. J)

~A~R~17___~-~~!_!_!_+_-++4~ A 0 1

~?~B~~t~r7~IB~R~3~-~1~7--.~X~A~D~++I-+--+++-1~~
~G~a~t~e~I~BR~2~1~-~3S~-.~~X~A~D~~I__+_+4_~~

AI/~BI/B2

...:1.::::BR~3S=---_______-+-IH--+++~ A 4F) I-A__
I .....t-------~"'
'--';:;-:-:::1

'--~

r------~~J

~G~a~t~e~S~R~3--1~7-~~X~A~D~__~--!_++_~r-'-ln-~p~~

-"S~R~I!....7..,.,....__-::-:::---,.,...,..:::____f-+-_+++~ A 012 A2
~~~R~;~~~S~R~2~1~-3~5~-.~X~A~D~~~-+~---:~~~

Gate PC_XAD

A C13 BI

NotXR 17

A

D O l " " 20
(3)i')
~ A
~

~G~a~t~e~X~R~-.~X7A~D~-----------+-1~~

XR 17

I

Figure 56. Index Adder Positions

60

Generate 17

(G,;nerate)

T

(2H)

_

Ne~B

A¥ B

~

--------------~ A
L.-~ AI8
MQ5
(41) B2
(3H)
L..- " - ' -

I

~

LA~;

4H) BI

u;.E Not

.:.A~C::.....:.3S:"""=-=-=__""""'-=-_______--+l-"~ C1 ~2·
Gate MQ S-5 .... XAD

Propagate 17

~~

..:G::.:a::.;.t=:-e.,.::C;.:::o;:,;m~pX:;.:R--.=....:.X.::.A~D~------'_+-~
... A
..:G~a~to:.e.!:A~C'-'3~O'_-~3S~~....::...~X.:...:A""D_ _ _ _ _ _~
,In

I

AI/A2

-:-ca-t-~-C-o-m-p-p-C--.-X-A-D-----+++---'l~*;
Not PC 17

019

~

Carry In 17

0 21
(IH)

.........".,

T

I

NotA¥B

~

Not Carry,
In 17

A 22

(21)

r--r0
~

A

23

r4' ~~

XAD 17 Sum

XAD Positions 13-17

-----~.....I~f---- Generate

Bit Carry (03.05.52.1)

(03.05.57.1)

--1

....--X-A-D-I-3--- Propagate 13
Generate 13
I
- - -- -, -

03.05.45.1
-

r

..... -

-

-

-

XAD Sum 13

~

-- -

-

-

-

-

-

o

-- --

I

~------------- ..!13

~--~-------------I

,
I

I

P14
P15'
P16"
P17'"

I
I

I

I

I
I

I

P14
P15 ~

I

P16
G17
P14

P r o p o - I II
...- - - - - - - . gate
XAD 14
14'

I
I
_ .J!3.:..2? .46.1- _

r

_

=

A
(2G)_

==t:==
(2F)

'-------

I---

-=----=--=-_--=- -:~ ~ ~-....--,

-:1+- _=- .:- - _ ~

f-I

....

(lG)

I

PI?:
Kin"
(41)
PI5"7'=
P16 ~
A
,Q..!Z.;: (4H)

I

I

,.

~

~

Carry
In

(3H) ~
'--"--'-

G15~ ~

I I :
III

~

(4F)

H
:n=I"_~ ~ -=--=-"-- _-=--=--=--= -=--~:

XAD Sum
15
...

....>0..

1""' . . ._ _ _ _ _....

.......-0

Ur

I

I I

Generate
15

~_--.J

P15P16 --:
A

___
Pr-'opo'-----+-1--+--1-'"
gate 15
I
P15~ ~
__+--'--I-+--+--4--I,--G_l_6~
~ (4G)

f-------

G_15

-11- --' - - - - - - - - - -

I I
I I
I I

03.05.46.1

Carry
In
13

G14 ~
1 7 ' (2 E) \ - - _ - - J

II

XAD15

~- 0
--

A

.......

P14?
G15

I

I

S~m

XAD
_ _ _ _ _ _.. 14
--,
..

=

(2H)

P15~

I

I

A

G16

I

Gen- I
erate i.
14

r---

,.---+

I
'

I

I

-f----- -

III
I I

I

I

I

I

I

I'
i I

Generate
16

I

I

~

P16

G17~

I

I
III

I

XAD Sum

I

________~16

~

___________PI
------------~

1AI

I:

I
I I

Kin

I

G17

-

~

-

-

",.--;t:;I
II TI I I T
I
I (4A) l
I

~~~.~1__
XAD Sum 17 ~

..

A

I H--f----- _______ ~5

-J (ts) l

I

15

+ ___ - _ - _ - _ - __ -.fl

I

Generate 17

~ ~arry

~ (~)

~
A

~+tl ! - f - - I I , I
Propagate 17
I I : I
P17

~

,-

(4D)

(4E)

-~

I II~

....-X-A-D-I-7--..

-'-

tJ

~

G16",-1

~l

_ ..2.3.:..22 ..£:!.... ~~

I I

I

P16_
P17 -~
A
Kin -;. (4E)

A

PIS

---- --

... --tTT- - f- - - - - - - __ - __G
'
Propagate
....----~·16
I
XAD 16
,.----l

Generate
Gl

~~(,_2_1.).,t------l~-""'A_,

I

I

(3D)

--- ----

*
.
... - - - - - - - - - - -

XAD Group Lookahead and XAD 3 Carry

U---I

-----------------::.~I

Any Gen"a!e G3

~-----tr-~

0

(3A-3B)

r~-'

II

o

(3D)

Ge~ate
~ 4I ~o
Propagate G3 i
(4E)
I

:
I

I !~ro-ll~XAD3

L+t~~~a~_~
III
03.05.70. 1
------------1-1-1 ------~
,
III
~
III
III
Any Generate G2
r-t::,(3A-3B)
II
II
--II
II
'~
~
(4C)
II
..----.
,
0
II
A
...
~J (40)
II
,...
03 .05.55. 1

.-------. P8
1

8

I

G8

P9

I

9

I G9

I

~

L::

P10

~G10
-

~

~

.....

~P11
11

I

G11

.!"

(4E)

(30)

Generate or

Propagate G2

.-------. P12
112

I

,

G12

I

--'PT3 - -

~G13

....---...

I

-

A

... ~

o

(5

1

I

16

---

A

(3C)

l

--

Carry In
Gr 3

03.05.70.1
~--

---- -----

~

...

P14

,

G15

(4C)

A
(40)

~~

'----"

r-:lI

(4B)

(4B)

;;::l

I

A

I

.-------. P15
15

~

03.05.56.1

------ -- -------------- -

~G14

Q.

TO (~) l

I
I
1 ~

r--

~

,

I

-.:.

A

~()
...
....

~
~

(30)

Generate G1

Carry In Gr 2

,....

P16
G16

....

~~r--

:;;:,

P17

....

:

1

NG17

(4G)

-- ---- -- -- ---

-- ----

Carry In 17

03.05.57.1

- - ---------- -- - - - XAO 3 Carry Circuitry------

Figure 58. Index Adder Group Lookahead and XAD(3) Carry

62

SR Zero Check
(Systems 02.12.47.1 )
Outputs from storage register input gating (1-35) are
fed to a zero check circuit as shown in Figure 59. Note
that the test is made from data introduced at the storage register input gating and not from data presently
in the storage register. In most cases, the data to be
tested will not actually be set into the storage register.
Many instructions gate the contents of the various
CPU registers and adders to this zero check circuit as a
check for either zero or equal conditions. Arithmetic
operations make extensive use of this check circuit for
detecting initial zero quantities (i.e., multiplier or multiplicand) or zero final results. When tests are made
on the fraction of floating-point quantities, only positions 9:"35 are gated from the register concerned to the
check circuit.
Not
Not
Not
Not
Not
Not
Not

SR Input 1
SR Input 2
SR Input 3
SR Input 4
SR Input 5
SR Input 6
SRTnout 7

.---

~

A

~
~
~

is generated; when computer circuitry requires a reference to the odd memory, a «memory select odd" pulse
is generated-if both references are required, both select pulses are generated.
In Figure 60, 0 1 and O2 receive the circuit indications as to which memory/memories are required.
These gating pulses occur at the end of the machine
cycle, 6(D2) time, and also cause gating of MAR(S-16)
addressing lines to the 7302-3. Just how these even or
odd gating lines are developed will be discussed in the
following section.
The memory select pulses can occur at two different
times: CPU operations at 7(D1) time; and channel operations at A2(D1) time. Data channel operations select
memory ata later time because of the longer 12-point
cycle. The memory, operating at a faster rate, provides
the necessary data at the proper channel time. The reverse also applies when storing data from the channel.
Note from A0 3 that channel operations assume priority-cpu memory selection is blocked until all channels are completed with either B or E time.

~

?

(4A)

SR 1-7

= Zero

'----

Not
Not
Not
Not
Not
Not
Not

SR Input 8
SR Input 9
SR Input 10
SR Input 11
SR Input 12
SR 1nput 13
SR 1riPut T4

Not
Not
Not
Not
Not
Not
Not

SR
SR
SR
SR
SR
SR
SR

Input
Input
Input
Input
Input
Input
Input

15
16
17
18
19
20
21

Not
Not
Not
Not
Not
Not
Not

SR
SR
SR
SR
SR
SR
SR

Input
Input
Input
Input
Input
Input
Inout

22
23
24
25
26
27
28

Not
Not
Not
Not
Not
Not
Not

SR
SR
SR
SR
SR
SR
SR

Input
Input
Input
Input
Input
Input
Inout

29
30
31
32
33
34
35

Figure 59.

~~
"'7'

,
""7'
~

(4B)

~

,

SR 9-14

= Zero

~

A

~

-:

~-;;-

~

,
(4D)

?

SR 15-21

= Zero

~
~

.----

~

,

(2D)

~~

A

SR 1-35lnput = Zero

~

A7(Dl)S

...

_
-,.
""7'

(4E)

?

SR 22-28 = Zero
Gate
Gate
Gate
Gate
Gate

~r---;;~

,..

PC MAR Even
AR MAR Even
IBR MAR Even
BAR MAR Even
XAD MAR Even

,.

r---

01

-

(4A)

I~ A5
-]

~

,

SR

(4G)

SR 29-35

= Zero

Input Zero Check

Gate
Gate
Gate
Gate
Gate

PC MAR Odd
AR MAR Odd
IBR MAR Odd
BAR MAR Odd
XAD MAR Odd

~

(3B)

l

-.,.,
-,. 1

A6
(3E)

I,Mem Select (Odd)

r02

(4E)
L....---

Memory Selection Circuits
(Systems 03.06.29.4)
The 7302-3 core storage is divided into two logically
independent units of 16,384 positions each. To initiate
these two units, separate «memory select" pulses are
required. When computer circuitry requires a reference to the even memory, a «memory select even" pulse

~41
(3A) Mem Select (Even)

,. 1

I--,--:I
,....-- Not Chan
A 03 1Tr;;"e-

Channel E Time
MF Go Tgr

1J

A7
(3F)
03.0"6.2'9.4

A (3C) Chan Time

B Time

'--

Channel A2(Dl) Dlyd

Figure 60. Memory Select Circuitry
7094 II System and Functional Components

63

overall logic for all five controlling sources; the program counter controls as shown in Figure 61 are repeated at the top of Figure 62. Note the similarity of
the controls and also that they control only MAR(4-16).
Controls for MAR(S) are handled separately because
of the MAR(S and 17) "switching" for normal and diagnostic modes of operation. Circuit tests are made to determine whether or not a bit should be sent on the
MAR(S) bus. Four combinations of address bits (3 and
17) can exist:

MAR Switching and Address Controls

Only 14 of the 15 address bits are required to select
anyone of the 16,384 even or odd memory positions.
The remaining 15th address bit determines selection of
the appropriate memory.
Memory selection and MAR gating is effected by
whether the computer is operating in the normal mode
or diagnostic mode.
In normal mode, the even memory contains all of the
even addresses (0,2,4, 6, 10 through 77,7768); the odd
memory contains all of the odd addresses (1,3, 5, 7, 11
through 77,7778). With this normal case, memory selection is under control of address bit (17)-if bit (17) = 0,
select even memory; if bit (17) = 1, select odd memory.
This selection circuitry for program counter gating is
shown in Figure 61 at A2 and A4 , respectively.
In diagnostic mode, the "even" memory contains the
lower half of all memory addresses (0 through 37,777s);
the "odd" memory contains the upper half of all memory addresses (40,000s through 77,777s). With this diagnostic case, memory selection is under control of address bit (3)-if bit (3) = 0, select even memory; if bit
(3) = 1, select odd memory. This selection circuitry is
shown at A3 and A5 •
MAR selection and gating is under control of five
sources: the program counter as just described, the
address register, IBR, buffer address register for channel
operations, and index adders. Figure 62 shows the

Select even memory
Select odd memory
Select even memory
Select odd memory

PC-'MAR
PC'" MAR Line 1
PC .... MAR Li ne 2
PC-.MAR Line 3

Not Diagnostic Mode
Not PC 17

17
0
0
1

1

NORMAL MODE

Select even memory
Select even memory
Select odd memory
Select odd memory

Selection of MAR( S)-even memory requires item 2
for normal mode and item 3 for diagnostic mode. These
two cases are shown for the program counter at A6 and
A7 in Figures 61 and 62.
Selection of MAR(s)-odd memory requires only item
4. Note that this item is independent of either normal
or diagnostic mode, and is shown at As in Figures 61
and 62.
When operating in diagnostic mode, two sequential
instructions cannot be fetched from the same memory
on the same cycle. Because of the memory arrangement, "gate XAD to MAR" circuitry has no logic, and is,
therefore, blocked at A4B , Figure 62.

Not Block PC and XAD to MAR on Channel Trap
Gate
Gate
Gate
Gate

3
0
1
0
1

DIAGNOSTIC MODE

1.
2.
3.
4.

03.06.29.2

,.... ~

Dot

~

:.,.

/AND

-

(4A)

Diagnostic Mode
Not PC 3
PC 17

~
....

(3A)

~ A3

I _

_

J g~ I

Gate PC--.MAR (Even)

~ J, - . . - -1

Gate PC --. MAR (Odd)

I~

(3B)

...-.- ~ A4

,

(3E)
1 .... _ _ _ .

I~

PC 3

>--

...
~

7

~_

===
(3C)

64

,

l

(3D)

----=tJllil

~
Figure 61. Program Counter MAR Bus Selection

(2 F)

A7

'....

010

- A6

~

...
.....

___

(3F)

(3G)

(2D)

PC MAR 3 (Even)

PC MAR 3 (Odd)

....

...
,.

Not
Gate
Gate
Gate
Gate

Block PC and XAD to MAR on Channel Trap
PC-MAR
PC
MAR line 1 .1 0 1
PC - MAR line 21
PC-MARline 3.1 (4A)

03 06 29 2
Dot AND

,/

~

Not Diagnostic Mode
Not PC 17

(3A)

J g:) l

~

Diagnostic Mode
Not PC 3

(31l)

PC 17

.....

(3:)

-~ J 010 I""'dC-MAR (Odd)
~--~

PC 3

..... : : A6
,...~ (3C)

'-

f-~

011
(2 D)
PC MAR 3 (Even)
~
PC MAR 3 (Odd)

(3D)
~

~~)

-

Gate
Gate
Gate
Gate

Gate PC-MAR (Even)

;fA

-

-- -- -- -- -- - - ---

- - - - - - - - -r-

AR-MAR
AR-MAR line 1
AR- MAR Line 2
AR- MAR Line 3

03.06.28.9

0
(4A)

~~

Not AR 17

...-r-- f---,;:f-- (3B)

Not AR 3

~

r-

~r--

I

-=:!

-------J
J

r- (~)

I

L:I -(~) I
~

Gate AR-MAR (Odd)
PC 4

(3C)

~ -=;;-" I--r----'

~AR 3 (Even)

(3D)

A
A (3A)
A (3D) MAR 4 (Even)

XAD 4

~~

AR 3 (Odd)

- - -- ---- -- - - -

~A

03.06.29.1

~

r~
~

(tA)

r--~ (3~

L
D

~

A (3C)
A (3D) MAR 4 (Odd)

(~B)

~'--

I

03.06.28.1

Gate IBR-MAR (Even)

·~I

-=:I

'-C:; (~F)
;::::::=

..... t;:

'-r-- -

....

r- .::;

(~)

Gate IBR-MAR (Odd)

~

I

A

~

J (2~)

- - --- -

17=1,~~~

.~

Hot One to BAR Bus 17

.....

~BAR

17

.... -

~

(4A) h

:B

AQO
(4B)
(3B)

=

r;! (~E)

Not BAR 3 - MAR

....

BAR 3-MAR

-

--

(4D)

--~
(4G)

- - - - - ~t Diagnosti~e
NotBlockPCandxADp':j" A
to MARon Channel Trap
(4B)

I
PC 16
IBR 34

(~D)

I

~

BAR MAR 3 (Even)

BAR 16-MAR
XAD16

I I
..... 'A""'O
~

"A

I--

~ (3A)
A
A

(3B) MAR 16 (Even)

~~

BAR MAR 3 (Odd)

- - - - - --- --- --- - - -03.06.28.8

~~~

~ I--

a

a

A

Dot AND

A

/

(4A)

--

~
~

XAD 17

L~

XAD 3
I

MAR

I

I

A

Gate XAD*-MAR
Gate XAD*-MAR Line 1
Gate XA[)'MAR Line.1..
Gate XAD--MAR Line i
Gate XAD*-MAR Line 4..

I

AR 16

D

I
I
I

I

lGate BAR-MAR (Even)

~ 8F) IGate BAR-MAR (Odd)
I

I

I

~

~r-;;-

I

I
I
I

I

h

~

I

I

IBR MAR 3 (Odd)

!'"""---A - - - - - - - - - ---03.06.29.3

17

I

I

I

IIBR MAR 3 (Even)

A
(3G)

I

I
I
I
I
I

I

A
(3C)

=

I

I

~

~~ (~E)
~

IBR 21

GaleB~M~

0

--A
A

(4A)

IBR 35

Figure 62.

A

IBR 22
BAR 4-MAR

0

Not IBR 21

Not XAD 17

--'A'Cl

AR 4

~

Not IBR 35

BAR 17 ..... MAR (BAR

(Odd)

03.06.29.3

Gate AR-MAR (Even)

A

Gate IBR-MAR
Gate IBR-MAR
Gate IBR-MAR

Dot OR

/MAR3

A

dm--

t:~

~-

1"

0
(31)

I

0
(2B)

~--,;:-

~r--

MAR 3 (Even)'

~

~-=:---=

AR 3

0
(3H)

f

~==:=:=

AR 17

~~

}jrl

~ (3D) MAR 16 (Odd)
(3Q

A

Gate XAD*-MAR (Even)

~'--

03.06.28.7
Gate XAD-MAR (Odd)

XAD MAR 3 (Even)
XAD MAR 3 (Odd)

Bus Selection and Switching
7094 II System and Functional Components

65

Timing

Master Clocks and Pulses
All of the computer functions are directly related to
two master clocks shown in Figure 63. These clocks
located in the multiplexor, provide the basic pulses
necessary for CPU and channel operation.
The heart of these clocks is a 5.71 megacycle oscillator which produces a complete output cycle once
every .175 microseconds (175 nanoseconds). Each positive and negative oscillator output pulse is, then, approximately 87 nanoseconds long (Figure 64).
The CPU clock is an 8 cycle-point clock composed of
eight triggers (cpu clock triggers 0-7); the channel
clock is a 12 cycle-point clock composed of 12 triggers
(channel clock triggers 0-11). In either case, the clock
forms a closed ring-each trigger is turned on in sequence and provides a gated output of 175 nanoseconds. The combined outputs produce the basic cycle
times as follows:

=

CPU Cycle: 8 x .175
lAO microseconds
Channel Cycle: 12 x .175
2.10 microseconds

=

Clock drive pulses needed to sequentially step the
clock triggers are produced by the clock drive trigger
(Figure 63). Oscillator outputs gate two controlling
AND circuits to the clock drive trigger; the top AND
circuit is used to set, and the lower AND circuit is used
to reset the trigger. Delayed outputs from the clock
drive trigger condition the input AND circuits such that
the trigger changes state with each positive oscillator
pulse. Outputs from the clock drive trigger ("even
clock drive~' and "odd clock drive"), Figure 65, are a
series of pulses 175 nanoseconds in duration. The clock
drive trigger has acted to halve the output rate of the
·oscillator.
Both the CPU and channel master clocks are reset
under power-on conditions or by depression of the
console clear key (Figure 63). At the end of the reset
pulse, the DLY-AND circuit combination produces a 100
nanosecond "start clock" pulse which turns on both
the CPU clock 0 and channel clock 0 triggers.
Using the CPU clock as an example in Figure 63, the
next "even clock drive" gates the CPU clock 0 trigger
output to produce an AO(Dl) pulse of 175 nanoseconds
duration. This same AO(Dl) pulse, besides being gated
to other circuitry, also turns on the CPU clock 1 trigger.

66

Note that even though the CPU clock 1 trigger is turned
on at O-time, the output of its AND circuit does not become active until "odd clock drive," 175 nanoseconds
later. The main logical output of the trigger is, therefore, Al(Dl).
As a result of the preceding logic, the Al(Dl) pulse
turns on CPU clock 2 trigger. This trigger output when
gated with "even clock drive" produces an A2(Dl)
pulse. Referring to Figure 63, CPU clock 2 trigger
turning on at I-time acts as a reset to CPU clock 0 trigger, and the A2(Dl) gated output acts as a set pulse
for CPU clock 3 trigger. This sequence continues
through CPU clock 7 trigger. Rise of the A7(Dl) pulse
turns the CPU clock 0 trigger back on and the clock
continues to run in a closed ring.
I/O operations on the 7094 II are bascially the same
as for the 7090/7094. Timing conditions, however, are
such that the 1.4 microseconds cycle is too fast to support channel operations without considerable rework
within the channel itself. Therefore, to accommodate
the channels and simplify the 7094 to 7094 II conversions, the 12 cycle-point clock has been retained
strictly for use by the channels. Looking at the channel clock in Figure 63 shows that operation is identical
to the CPU clock except that the cycle duration is extended beyond clock 7 time to include clock 11 time.
Note that even though the CPU and channel clocks
are separate circuits, both are reset, started, and under
control of common clock logic. From Figure 66 it can
be seen that two channel cycles occur for every three
CPU cycles. Therefore, at every third CPU cycle both
clocks align themselves with respect to O-time. More
information concerning channel operation and timings will be found later in this section and in volume 3.
Figure 67 shows outputs and controls significant to
each stage of the CPU and channel clock rings. Figures
68 and 69 shows sequence charts for the CPU and
channel clocks respectively. Note that each clock trigger is on for 350 nanoseconds, twice the time duration
of an individual clock pulse. A particular clock trigger is turned on one clock pulse early and only the
last half of the output is gated by the clock drive pulse.
This slower SWitching of the clock triggers provides
increased reliability in the clock operation as well as
additional pulses usable in the computer.

Set Pulse Drive

r--5.71
MC
Osc

---(5A)

.------~,..

~J

J

A
(4C)

Clock Drive
L~
Even Clock Drive

~---------------,

T

-

,.

Odd Clock Drive

Clock Drive (Off)

1rDi;r

l.J

(2C)

lClock Drive (On)

I

Power On
Reset
100*

I

~

&lJ

Clock Reset
on Clear

I...

(:H)

Clock Start

Clock Reset
__

~OO.44.~~ _ _ _ _ _ _ _ _

1
II

Ch~O

l+

T(OR)

~

_

f----',.~I R(4C)

r

C=0

~

~

__

l---~----------------08.00.40.1-08.00.43.1

All (D2)

08.00.43.2-08.00.43.3

T(OR)

...

_

MPXR A7(D2)...

~

~

A

-

(3B)

t7'

_Chan AO(Dl)

I

r-----4-+-~f-------~

AO(D2)

J----I
(:E)

IChan Clk 2

-

t7 '

..

R(35)

I
Al(D2)

---- I

.-f----:..~R(4i)
,.~

(:H)

1 .

r------r~+_++-----~

L7'

_

...
MPXR
A3(D2)

MPXR Al (D2)

~MPXRA'(Dl)-

~
.~ ..B..illL

...Chan A2 (D 1>....

1

~MPXRA1(Dl) ...

r~

_Chan Al (D1)...

~r_A_3~(D_2~)_~~_.~~~

MPXR AO(D2) ...
,.

,.

I

!chan Clk 3

~rA2(D2)

...

A4(D2)e-+---l~~~

_A_4~(_D2~)_ _~+-_...
~RtKt
,. ---:........;..

,

MPXR A2(D2)
~

MPXR

e-1---i""''''R(4Cf

--'----'-+-+---l~~~

,~

Turn~

T

, Chan Clk 4~

'

,
I

Chan Clk 11

MPXR

Al0(Dl)
~
------~-~,
T

A6(Dl)

..

-

---'----'-+-+-~~

_

~) I
Channel Clock

CPU Clk 7

I

Al0(D2)

T
MPXR A6(D2) ..

_~

.ChaoAl1(Dl)
~

T

J

(:G)

I~XR

________~J

A7(Dl) ..

,.

CPU Clock

Figure 63. Master Clock Logic

Timing

67

CPU
Clock Tgr.

Turned
On by
A7
AO
AI
A2
A3
A4
A5
A6

0
I
2
3
4
5
6
7

Figure 64. 5.71

MC

Oscillator Output

(01)
(01)
(OJ)
(OJ)
(01)
(OJ)
(01)
(OJ)

Channel
Clock Tgr.

Turned
On by

0
I
2
3
4
5
6
7
8
9
10
II

AII(OI)
AO (01)
AI (OJ)
A2 (01)
A3 (OJ)
A4 (OJ)
A5 (OJ)
A6 (01)
A7 (OJ)
A8 (OJ)
A9 (01)
AIO (01)

Figurc 67.

CPU

Turned
Off by
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Clock

2
3
4
5
6
7
a
I

Tgr
Tgr
Tgr
Tgr
Tgr
Tgr
Tgr
Tgr

Turned
Off by
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Clock

2 Tgr
3 Tgr
4 Tgr
5 Tgr
6 Tgr
7 Tgr
8 Tgr
9 Tgr
10 Tgr
I I Tgr
0 Tgr
I Tgr

Odd Ring Drive

Start Clack Pulse
CPU Clack 0 Trigger
MPXR AO(Dl) Clock Pulse

Figure 65. Oscillator Output and Even Clock Drive
CPU Clock 1 Trigger
MPXR Al(Dl) Clock Pulse
CPU Clock 2 Trigger
MPXR A2(Dl) Clock Pulse
CPU Clock 3 Trigger
MPXR A3(Dl) Clock Pulse
CPU Clock 4 Trigger
MPXR A4(Dl) Clock Pulse
CPU Clock 5 Trigger
MPXR A5(Dl) Clock Pulse
CPU Clock 6 Trigger
MPXR A6(Dl) Clock Pulse
CPU Clock 7 Trigger
MPXR A7(Dl) Clock Pulse

68

CPU

and Channel Cycle Relationship

Figure 68.

CPU

A7
AO
AI
A2
A3
A4
A5
A6

(02)
(02)
(02)
(02)
(02)
(02)
(02)
(02)

Clock Sequence Chart

Gated
Output
AO
AI
A2
A3
A4
A5
A6
A7

(01)
(OJ)
(01)
(01)
(01)
(01)
(01)
(01)

Tgr Ouration
and Output

Gated
Output

A II (02)
AO (02)
AI (02)
A2 (02)
A3 (02)
A4 (02)
A5 (02)
A6 (02)
A7 (02)
A8 (02)
A9 (02)
Ala (02)

AO (01)
AI (01)
A2 (01)
A3 (OJ)
A4 (01)
A5 (OJ)
A6 (01)
A7 (01)
A8 (OJ)
A9 (01)
Ala (01)
A II (01)

and Channel Clock Output and Controls

Even Ring Drive

Figure 66.

Tgr Ouration
and Output

Even Ring Drive
Odd Ring Drive

Start Clock Pulse

I

I

LlJ

Ll.J

Channel Clock 0 Trigger'

-W

AO(D1) Clock Pulse

~~

Channel Clock 1 Trigger

-W-------iLJ

____~n~____~n~___
I

I

I

I

LJ

::::::IC~::k:I:;gg" ----'~r-------+i-...u
A2(D1) Clock Pulse
Channel Clock 3 Trigger
A3(D1) Clock Pulse
Channel Clock 4 Trigger
A4(D1) Clock Pulse
Channel Clock 5 Trigger
A5(D1) Clock Pulse
Channel Clock 6 Trigger
A6(D1) Clock Pulse

::;::~IC~~:k:I~~;gg"

-----'~

_ _--.~

Channel Clock 9 Trigger
A9(D1) Clock Pulse
Channel Clock 10 Trigger
A1O(D1) Clock Pulse
Channel Clock 11 Trigger
A11(Dl) Clock Pulse

! rLL----

W

I

I W

~

I

~

I

W
I
L..J
I
u______~~~____~I--~n~----~I--~~
W

I

~----~I--~

I

l...J

I

W--

----~~~--~I--~~~~I--~~

W

-~~

2J

I

W..-----.I-----.W-

I

~r----L....-I-~
2J..--.. . ----,~

I

I!

_

_

_

I

Channel Clock 8 Trigger
A8(D1) Clock Pulse

~

i

L...J

:Lj'------

_ _ _ _ _----...In
I

r1

I

----W

I"""---+-I

......

I

------~~~~I----~~
W I

I
I
I

Wr-...!-[-----

----------~n~i~------~n
i
w
Wr------_______

I

~~

I

n~

____

Figure 69. Channel Clock Sequence Chart

Timing

69

CPU Clock Pulse Distribution

The CPU clock is located in the multiplexor and the
output pulses are distributed to both CPU-I and CPU-2
for usage. Because of inherent delays in logic blocks
and cable transmission lines, clock pulses arrive at the
various CPU gates after finite delays.
Figure 70 shows the typical distribution pattern of a
CPU pulse. This MPXR A3(Dl) pulse is generated by the
CPU clock 3 trigger (Figure 63) and sent to both CPU-I
and CPU-2 for usage. By the time the MPXR A3(Dl)
pulse arrives at CPU-2, however, the MPXR A4(Dl) pulse
is being formed. Therefore, to provide alignment of
pulses between the multiplexor and CPU-2, the original
MPXR A3(Dl) pulse is relabeled as MF A4(Dl) upon
entering CPU-2.
As the original MPXR A3(Dl) pulse continues on its
way to CPU-I, additional delays are encountered similar
to the ones just described. With the help of a DLY
block, the incoming pulse to CPU-I is delayed a small
amount and again relabeled as a MF A A5(Dl).
There is, therefore, a skew of one clock pulse between the CPU-2 and multiplexor, and a skew of two
clock pulses between gates A and B of CPU-I and the
multiplexor. A5(Dl) pulses throughout the computer,
for example, are the result of three different CPU clock
trigger outputs in the multiplexor. Except for troubleshooting purposes, these various outputs need not
concern the reader. The computer circuitry doesn't
care where the pulses come from as long as they represent the correct timing or logic.
Although the AO(Dl) through A7(Dl) pulses are the
prime outputs of the CPU clock, the D2 pulses are also
distributed and used throughout the computer. Pulses
of other durations such as A3(D3), AO(D6), etc., are
produced throughout the systems as needed by using
either triggers or combinations of AND and OR circuits.

70

In the computer, clock pulses are gated during cyclic
operation and then labeled I6(Dl) or E5(Dl), depending on the particular cycle of operation. Whenever an
A pulse is encountered in studying the computer, for
example A6(Dl), it means this pulse is used directly
from the clock and is independent of the computer's
cycle of operation. This A pulse ·always occurs at 6 time
and is always available.

CPU 1 A and B Gate Clock Pulse Designation

Timing pulse alignment becomes increasingly more
important as the internal computer operations are
compressed into smaller and smaller intervals of time.
In the A and B gates of CPU-I where a major portion
of the computer operatiol)s are performed, the clock
pulses have been systematically delayed, aligned and
labeled accordingly.
In Figure 70 the clock pulse coming into the A gate
of CPU-I is directed into two similar groups of circuitry.
The top group of pulses labeled LN B (Line B) are sent
to the B gate for usage; the bottom group (LN A) remains in the A gate for usage.
Pulses used in both A and B gates of CPU-I also
have an additional letter and number designationA5(Dl) G3, for example. In Figure 70 "-F A5(Dl) G5
LNA" is the earliest A5(Dl) pulse used in the A gate.
This pulse delayed through an inverter produces a
"+ F A5(Dl) G4." Additional inverter delays produce
"-F A5(Dl) G3," "+F A5(Dl) G2," and "±F A5(Dl) R»
pulses. Note that the higher the G number, the earlier
the pulse. By picking the appropriate pulse, compensation can be made for the number of levels of logic delay
preceding a trigger or register gating circuitry.

Multiplexor (Figure 63)

CPU 2

CPU Clk 3

CPU 1 (D Gate)

CPU 1 (A Gate)

02.15.70.6

MPXR
A3(D1)

R

MF A4(D1)
02.15.08.1

Odd Clock
Drive

-F A5(D 1) G5 LNB
+FA5(D1)G4 LNB :
-F A5(D1)G3 LNB

B Gate
Usage

+F A5(Dl)G2 LNB
I ' I - F A5(D1)R

LNB

LMJ
-FA5(D1)G5 LNA
+FA5(D1) G4 LNA
-FA5(D1)G3 LNA
+FA5(D1)G2 LNA

Figure 70.

CPU

Clock Pulse Distribution

A Gate
Usage

Figure 71 shows four typical examples of pulse
usage. At circuit (a), the A5(D1) G4 pulse is used because of the four levels of logic in front of the register
gate. At circuits (b) and (c) the G3 and G2 pulses are
used because of the three and two levels of logic in
front of the register gating. The R (register) pulse, circuit (d), is the latest pulse and is usually used as a
direct input to a trigger. There are, of course, exceptions to the pattern of usage just discussed.
Note that the G-pulse levels alternate between +F
and -F at each step because of the natural inversion
from each DIF logic block. The majority of the triggers
and register inputs use + level logic (i.e. +G or +AOI).
CP Set Pulse Generation and Distribution

Computer set pulses (cp set pulses) are developed directly from the master oscillator. These pulses are pre-

r

cisely generated and timed to set triggers and registers, and control much of the gating and shifting of
data within the computer. Width and timing of the
Cp set pulses, as related to the clock pulses, are extremely important to successful machine operation.
The input set pulse drive pulses are received directly
from the oscillator. A variable delay is used to pOSition
the cp set pulse when aligning it with the clock pulses
in the computer. Actual CP set pulse settings are made
at the A and B gates in CPU-I.
Figure 72 shows condensed logic of how the CP set
pulses are shaped, delayed, and distributed for specific usage in the computer. The inverters in Figure 72
have been included, not because they perform logic,
but because they contribute to the timing delays.

2 Levels

(a) +F A5(Dl}G4

r-1 Level ----:i~

-F

+F
-AI
Gate

+G
(b) -F A5(Dl)G3

(c) +F A5(Dl}G2

* Refer to Figure 70

Figure 71. CPU Clock Pulse Designations and Usage

72

(d) +F A5(D])R

A Gate (02.15.61.1)
CP Set (SCS)

CP Set

CP Set A

CP Set B

CP Set C

CP Set D

CAS CP Set

---------------------B Gate (02.15.61.2)
.... Simi lar to A Gate Above

....-"l-----~~~J---

Figure 72.

CP

Set Pulse Distribution

Machine Timing Cycles
7904 II computer operation consists of several types
of machine cycles concerned with both CPU and channeloperations.
CPU CYCLES

I
II
E
L

Instruction
IBR Instruction
Execution
Logical

CHANNEL CYCLES

B
Chan I
Chan E
Chan L

Buffer
Channel Instruction
Channel Execution
Channel Logical

The CPU cycles are directly concerned with CPU
operations and the 8 cycle-point 1.4 microsecond clock.
The channel cycles are directly concerned with channel operation and the 12 cycle-point 2.1 microsecond
clock.
The cyclic sequence of a computer instruction is
fixed and, depending on overlap conditions, begins
with either an I or II cycle. The total number and
types of machine cycles required for each instruction
is determined by the number of steps to be performed
before the operation is completed. This number varies
depending on the conditions set forth by the particular
instruction.
The various cycles essentially perform the following functions. Each will be discussed in greater detail
in later sections.

I Cycle: The I cycle occurs because of a break in
the overlap sequence. References are made to core
storage and two sequential instructions are received
into the program register and IBR for execution.
II Cycle: The II cycle occurs simultaneously with
an E or L cycle and is used to perform functions concerned with the overlapping instruction in the IBR.

E Cycle: The E cycle is used for data or IA (indirect
address) cycle references to core storage. This E cycle
can be initiated by an instruction in either the program register or IBR depending on the conditions of
overlap.
L Cycle: During the L cycle the computer performs
logical or arithmetic functions without reference to
core storage. This L cycle can be initiated by an instruction in either the program register or IBR depending on the conditions of overlap.

B Cycle: During the B cycle, a data channel uses
core storage for either accepting or delivering data (or
a data channel command word) in connection with an
input-output operation. This B cycle occurs simultaneously with L cycles but never occurs simultaneously with I, E, or II cycles.
Timing

73

Chan I Cycle: The channel I cycle supplies 1.05
microsecond I time gatings to channel banks 1 and 2
and is used primarily for reset functions.
Chan E Cycle: The channel E cycle supplies 2.1
microsecond E times gatings to the CPU circuits as well
as channel banks 1 and 2. This gating is used primarily
during channel operations requiring references to core
storage (i.e., POD'S 54/64 or ENB).
Chan L Cycle: The channel L cycle supplies 2.1
microsecond L time gatings to banks 1 and 2 for channel circuit controls.
The CPU I and E cycle timings are such that they
each gate their own instruction and data memory
references. To accomplish this, I or E time for addressing comes up early (6 time of the previous cycle).
There is, therefore, considerable overlapping of cycle
times as shown in Figure 73.

I
I

6

Time Gating

I

I

~

I
6

E Time Gating

I

i

i

I

7
L Time Gating

"

Time Gating

i

I

Figure 73. Cycle Time Relationship

74

I

iI

6

I

U

I

6

....
i --~L
I

I

Master I Time

I time is not the steadily recurring type of cycle that
existed on previous systems; it results only because of
a break in the overlap sequence of instructions. For
example, this break in sequence might occur because
of a successful transfer or skip condition resulting from
the instruction in the program register or IBR.
Figure 74 shows condensed logic of I time. Note
that even though the I time trigger might be turned
on, its outputs may be blocked until such time that
channel B cycle demands are satisfied. I time outputs
are also gated by the master stop trigger or machine
cycle gate (manual operations).
The basic objectives of the I cycle are to:
1. Select the proper memory/memories and gate the
corresponding address( es) out to MAR( s).
2. Update the program counter to the proper address.
3. Gate the proper instruction(s) from the even/odd
storage bus into the program register, storage register,
tag register and IBR.
4. Perform address modification when applicable.
5. Determine and initiate the next type of machine
cycle.

Machine Cycle Gate
Master Stop Trigger Off

o

Manual I Time Control

(IG)

04.20.10.1

Not B Interrupt
A5(Dl)R CP Set
Not IBR Go to E L
FAD E Time End-O

End-Op Condition

Overlap Conflict Condition

I Time Trigger
Skip Trigger
Pre IA Trigger
I Time Early (Addressing)

Test

I Late Dlyd
I Late
Delayed
Al(Dl)

08.00.18.3

E Time Trigger
Program {
Register
Controls

E Time Early (Addressing)
E Time (for IA)

Pre IA Trigger

Not Indirect Addressing

08.00.19.2
(2G)

Gen Reset

Not B Interrupt For L Time

IBR
Controls
A6(Dl) R
CP Set B

(To CPU 2)
L Time Early

L Time Late

Figure 74. I, E, and L Time Cycle Logic
Timing

75

Address Gating

Objective 1 is initiated in the upper area of Figure 75
(sheet 1). This area shows the decisions required for
initiating an I cycle. The skip trigger coming on as the
result of an instruction in the program register nullifies overlap and forces an I cycle because the instruction in the IBR is going to be bypassed.
If the skip trigger does not come on but there is an
overlap conflict condition, overlap will, again, be inhibited. In this latter case, the computer waits until
the instruction in the program register has ended operation before initiating an I cycle. Special FAD E time
end-op circuitry has been added because of timing
considerations.
If the skip trigger is off and there is no overlap conflict condition (Figure 75), a test is made to see if the
instruction being executed from the IBR will send the
computer into either an E or L cycle. If this ElL test
is successful, the computer proceeds to ElL time to
complete execution of the overlapping instruction. If
the test fails (the IBR contains a I-cycle instruction, for
example) the computer waits until the instruction in
the program register completes operation and then
initiates an I cycle.
Note that the I time trigger is turned on at 5 time
(three clock pulses before the end) of the previous
cycle. Turning the trigger on early allows its outputs
to provide addressing gates starting at 6 time. Machine
cycle design is such that the upcoming cycle provides
its own memory address gating.
With the exception of MAR addressing controls, the
I time does not logically start until the following 0
time.
Any B times requested by a data channel will be
serviced before the I cycle is allowed to continue. This
blocking of I time is accomplished by degating the output of the I time trigger with "B interrupt."
I time outputs can be grouped as follows:
I time early for addressing: These outputs are available starting at 6 time of the preceding cycle and are
used primarily for gating the proper instruction addresses to memory.
I time early: These outputs are delayed outputs of
the I time trigger and are available primarily for gating
functions at the beginning or during early portions of
the I cycle.
I time late: These outputs are delayed longer than
the early pulses and are, therefore, available for gating
functions during the latter portion of the I cycle. The
I time trigger is turned off at I5(DI) time so it is the
delayed outputs that maintain the required gating
until the end of the cycle.
I time late delayed: This output is used to decrement the program counter under HTR control so that
the counter will indicate the actual address of the HTR
instruction.
76

Going into I time is like getting a fresh start in the
program sequence and because of this, two sequential
instructions will be referenced from core storage and
brought into the CPU. Except for certain operations,
the address of one of the next two instructions to be
executed will always be found in either the program
counter, address register, or the address portion of the
IBR. The address of the other instruction can be obtained by incrementing or decrementing the first address. Both of these addresses when gated to the even
and odd memories will retrieve the next two desired
sequential instructions.
Note that the addressing blocks in the lower area
of Figure 75 are divided from left to right into distinct
groups according to function.
Group 1-Address Gating to MAR: One of these
three gates will be active to provide one instruction address to MAR. This same address is gated to the index
adders for either incrementing or decrementing.
Group 2-XAD Gating to j\1 AR: This block provides
the other instruction address to MAR. In the majority of
cases this second address is an incremented (+ 1) value
of the first address. In some cases, however, this second
address is a decremented (-1) value of the first address. Note that the XAD to MAR path is only active
when the computer is in overlap mode and not diagnostic mode.
Group 3-1's to XAD (3-17): These two blocks cause
incrementing or decrementing in the index adders.
Gating a 1 to XAD(17) is an unconditional I6(D2) func~
tion and causes address incrementing (+ 1). Gating 1's
to XAD(3-16) along with the 1 to XAD(17) causes address
decrementing (-1) by performing 1's complement addition.
Group 4-Address Updating Paths: This fourth
functional group takes the incremented (or decremented) XAD address output and routes it to either the
address register or IBR for temporary storage. This address will update the program counter at Il(DI) time.
Group 5-BAR Address Gating to MAR: This last
functional group is used during channel trap operations when addressing the specific data channel trap
location.
When progressing through the series of I time addressing decisions, a channel trap is concerned with
group 5 and directs the routing of the buffer address
register (BAR) to MAR.
For all other I time addressing decisions, groups 1
through 4 are used according to the following rules
(Figure 75):
l. One block (and only one block) is always used
from group l. Either the PC, AR, or IBR will contain the
correct address of one of the next two sequential instructions. This same address is also gated to the index
adders.

2. An entry will always be made into group 2.
Whether or not the index adders are gated to MAR
depends on both overlap mode and diagnostic mode.
3. In group 3, a 1 is always gated to XAD(17) for incrementing purposes. During the two cases where
decrementing is involved, the 1's to XAD(3-16) are also
used.
4. One block (and only one block) is always used
from group 4. These updating paths route the index
adder value to either the address register or IBR as
temporary storage until the program counter can be
updated at the next Il(Dl) time. Note that the value
set into the address register or IBR at this time normally corresponds to the second instruction selected
from memory (i.e., the instruction which will be set
into the IBR at 14 time of the I cycle).
U sing the above rules and making a systematic progression through the maze of addressing decisions
should prove the logic of the I time addressing.
Program Counter Update

Objective 2 updates the program counter to the proper
address. The program counter is always one step ahead
of the current instruction being executed; therefore,
the address to be set into the program counter will
correspond to the instruction destined for the IBR.
In the previous section, addresses were sent to MAR
during I6(D2). At the same time, the incremented (or
decremented) value from the index adders was also
routed and set into either the address register or IBR
(Figure 75, sheet 1). These group 4 routing paths place
the updating program counter address in "temporary
storage." During Il(Dl) time, this address is routed
unmodified to the program counter via the index adders (Figure 75, sheet 2). Note that the pattern of decision making for the updating circuitry is similar to
that for address gating discussed previously.
If the address register or IBR had received an incremented (+ 1) address from the index adders, that corresponding register contains the correct updating
address for the program counter. If, however, the address register or IBR had received a decremented (-1)
address from the index adders, the register originating
the address contains the correct updating address for
the program counter.
In some cases the program counter already contains
the correct address. When these cases occur, the updating paths are blocked and the program counter
value remains unchanged. One case, a successful class
A transfer in trap mode, requires a carry to XAD(17)
during update to put the value 00001 into the program
counter.

Storage Sus Gating

The third objective is to gate the storage buses into
the computer. The instructions which were addressed
at the previous 6 time will be available by 4 time on
the even and odd storage buses.
In Figure 75 (sheet 2) an external trapping condition will nullify the two new instructions arriving
from core storage and, instead, force an STR operation
by turning on PR (s, 9).
Excluding the trap condition, five routing and setting functions are available for the even and odd storage buses:
SB(S,
SB(S,
SB(S,
SB(S,
SB(S,

1-35) ~ SR(S, 1-35) and TR (18-20)
1-2) ~ PR(S, 8-9)
3-11) ~ PR(S, 1-9)
1-35) ~ IBR(S, 1-35) 14(Dl) Set Pulse
1-35) ~ IBR(S, 1-35) 14(D2) Set Pulse

Excluding the XEC instruction and channel traps for
the present, the program counter is the deciding factor
as to which storage bus is routed into the program
register (PR) and IBR. Remember that the program
counter was already updated (incremented) at II time
and is +1 ahead of the current instruction. Because of
this, if the program counter is at an odd value the even
storage bus is gated to the program register and the
odd bus to the IBR. If the program counter is at an
even value the odd storage bus is gated to the program
register and the even bus to the IBR.
A class A instruction coming into the program register is "pre-sensed" from the storage bus. If the instruction is a one cycle class A instruction (TIX, TNX, TXH,
TXL, TXI) circuits are immediately set up to also route
this same instruction into the IBR with an I4(D2) pulse.
Note that this longer I4(D2) pulse overrides the instruction placed in the IBR with the normal I4(Dl)
pulse. The reason for this special gating into the IBR
is because of addressing considerations which will be
discussed in Volume 3.
Tracing through the flow chart (Figure 75-sheet 2)
will also show the storage bus gatings for channel trap
and XEC conditions. In some of these latter conditions
the program counter value (even/odd) may cause some
unnecessary gatings into the IBR. These gatings cause
no problems, however, because overlapping is prevented at this time.
Figures 75 (sheet 2) and 76 provide a summary of
the various SB gating conditions.
After the program register has been set with the new
instruction, a check is made to determine if overlapping
is possible. If so, the IBR loaded trigger is turned on.

Timing

77

Address Modification

Objective number 4 is address modification. This modification is performed during the I5(Dl) clock pulse so
that the modified address (if an index register was
specified) will be available for MAR gating during the
next two clock pulses; i.e., E6(D2) early.
Class A instructions (TIX, TNX, TXH, TXL, TXI) block
address modification. Instead, the I4(D2) period of
time is used to perform the specific test or operation on
the index register (Figure 75, sheet 2). If the conditions
of the test are successful, a PR condition-met-trigger is
turned on; if the test fails, the trigger remains off.
If the instruction in the program register is indexable,
SR(21-35) and the complement of the specified index register(s) are gated to the index adders with a carry to
XAD(17). This 2's complement addition effectively performs a subtraction of the index register value from
the address portion of the instruction. If no index register is specified, all 1's are gated from the index register along with the carry to XAD(17) to effectively subtract zero from the address in SR(21-35).
The modified address resulting in the index adders
is gated to the address register for MAR gating at

SB Gating

E6(D2) time. If the instruction is a POD 76, the index
adders are also routed to the shift counter for further
decoding.

Next Machine Cycle

At the same time that the address modification or class
A testing is being performed, other circuitry is determining the next machine cycle.
If the PR instruction contains bits in positions 12 and
13, SR( 12, 13), and meets the other conditions shown in
Figure 75 (sheet 2), the pre-IA trigger is turned on and
an E cycle follows.
If no E(IA) cycle is called for, a test is made to see if
a I-cycle instruction is in the program register. If so,
the end-op trigger is turned on and another I cycle
follows.
If the instruction in the PR does not call for ending
opera tion, tests are made to see if an E cycle should
follow. If the test is successful, the master E time trigger is turned on and an E cycle follows. If, however,
neither an I or E cycle is requested, the master L time
trigger is turned on and an L cycle follows.

SB Gating Oecision Blocks
XEC Operation

EVEN SB
SS.... SR and TR
SB(S,l-2)-'PR(S,8-9)
SB(S,3-11)-'PR(S,l-9)
SB ....,BR 14(01)
SB~IBR 14(02)
OOD SB
SB....SR and TR
SB(S, 1-2)~PR(S, 8-9)
SB{S,3-11)+PR(S,l-9)
SB .... ,BR 14(01)
SB~IBR 14(02)

78

SB

Normal

~ I~1is{ef- a.ddlOa

1 f.-'

r
es

fr1~"/--,--",,""\
$

I;s't~~sc~on ~

PC

The instructions coming into the computer /
ore blocked. Instead, the computer is
forced into on STR operation by setting
PR(S,9).
Chon Trap

Off

~PC Od:j!~" ;;:~' 'h, 'BR 00"'" W(~C";;:~ Od:j!~" ~''" ~~~~~d;(~~}-

!

\03.06.30.1(2AY

.

I

5B(S,I-2)-PR(S,8-9)
03.0S.13.1 (11)
03.14.00.1 (IA)

!

D

\o3.06"30.1( 2A

SB-IBR

IIII

SB -IBR

03.0B.13.1(3C)

03.0B.13.l(3C)

-t ________

Instructions Such as PAX,
PAC, PCA,PCD, etc.
Details of their execution
found in volume 3.

~~~

SB-SR, TR

II 02.12.52.2(3E)

G

H

T

I

~

~~~

/4(:';

5B(S,I-2)-PR(S,S-9)
03.0S.13.1(IH)
03.14.00.1(lC)

SB(s,3-11)-PR(S,I-9)
03.0S.13.1(IH)
03.14.00.1(lC)

~v=-l~d _ _ _ _ _ _ _ _ _ _

14([)1)
SB-IBR

14(D2)
Set PR(S,9)

14(D2)
SB-IBR

+ _______
03.0B.13.1(3F)

03.0B.13.1(3F)

I

03.14.00.1(2A)

~dd~

f

f{

03.08.16.2

No

Class A
Instructi on

s

F

I

~(';.~ [~D2)

SB(S,3-ll)-PR(S;I-9)
03.08.13.1 (II) 03.14.00.1 (IA)

J1~3.16.13.1(4BV
In:!~~:t~on ~

'llis
\03.06.13.1(4BV

E

Odd

V~

~

....

C

~e~ _ _ _ _ ~ _ _ _ _ _

~C

PpdC-E-ve-n--'PC-O-d·
'd/Even

J \03.06.30.1(2AL~

B

02.12.52.2(3A)

/

Yes

:d~3.06.13.1(4Bi
In;tlr~s;t~n ~ vd I~~;~~~an ~ vd In~:~~~t~on ~ ~ ';~t~~Sc~on ~ Y~ In~!~~:t~on ~.d I~s~~~c~on
~3.06.13.1(4B)/~3.06.13.1(4BV ~3.06.13.1(4By
~3.06.13.1(4Bf·r

II ~ /4~
I

On

PC Even

A

SB -SR, TR

03. 14.00. 1(2B)

Manual operations are covered
in a separate section in volumn 3.
This is the I time preceding the E time of the
STR operation.

The channel trap MDBO latch prevents the
IBR loaded trigger from being set during
the I time following the STR operation. - - - - - - - On

03.08. 17.2(4A)

AR Odd Tgr

03.06.30. I (2A)

03.06.13.1 (4B);

Yes

Off

03.0S.13.1(3G)

},PCCpr<'
'1
PC Odd/Even
Odd

D3R

XEC Trigger

n

t

FP Trap or
Interrupt
(Chon Trap Dem)
3.14.00.1 (2B)

No

..,~ &I /J I I '
L
I .
C I"........
/7
,"-:;,V"uC.T'OVl
ctV~ "Tv-ctPlstev 1/ ;hSi-Y"Wrt-;c'

.L6J ; If

(Note 1)
Manual Ctrls

No

PRPODto
Inhibit Ovlp

No
I5(Dl)
Tum On IBR
Loaded Tgr
03.0S.16.2(3F)

t

.?=

Yes

(TIX, TNX, TXH, TXL, TXI, STR)

03.06.13.1 (4B)

PR Indexable
(PR 6 & 7)
02.10.65.2(5A)

No

l

I

.J

15 Dl)
)II(
15(Dl)
SR(21-35j-XAD
Carry-XAD(I7)
03.06.03.2(4H) ,03.06.13.2(3E)1
03.06.07.1 (2C) ,03.05.52.1 (5A)

15\Dl)
Camp XR-XAD
03.06.03. 2(5F) ,03.06.07.1 (2C)

~

Yes

14(D2)
Comp XR-XAb
03,06.02.3(5 F) , 03.06.07.1 (2C

I

I

t

o

02.12.76.1

Note: A POD 76 instruction
15 CP Set
_will have address modification
XAD-SC
performed if togged.
03.06.03.2(41) ,03.06.11.1 (3F)

Yes
5 (
)
RI2,13=I's_
02.10.65.2 (5E)

/

~N

I

15(ep) Set
Turn On End-Op Tgr
08.00.09.2(3B)

I Time
Sheet I

---

jI

15 CP
Turn on
Pre Set
IA Tgr
02.10.65.2(3B)

0

I
L Time

Figure 75. I Time Flow Chart (Sheet 2 of 2)

J6(Dl)
Reset AR
03.06. 14.2(3D)

the first I cycle of a transfer
instruction ·in trap mode.

See IA Flow Chart
forDetails

14_ _ _ _ _ _---'N~o_< pe':m'i~ed?}-YJ.-"e""s'----..."

, . - - - - - -Yes
- - { Cycle Inst

I

Turn on PR
Cond Met Tgr
03.06.19.1 (3D)

T
~____________.l______________~J
/
,l4---------------------------------------------I
This reset will also occur for

~
N

I

N~TraClassA
Cond Meth e s

"'------------+,

15 CP Set
XAD-AR
02.12.70.1 (4D) ,03.06.02.1 (5A)

14(D2)
SR(3-17) - XAD
03.06.13.1(2B)

I(

14(D2)
1-XAD(l7)
03.06.07.1 (2C) ,03.05.52.1 (5A)

SR(21-35). If no XR. is specified, all l's
gated from XR output circuitry.

(IH)

Yes

03.06.13.1(4C

t
XR value subtracted from instruction address,

Na~OD76

'--------{03.01.01.1

SIR

No

es

16(DI)
Turn On Master E Tgr
08.00.19.2(2B)

E Time

SB Gating
XEC Operation

58 Gating Decision Blocks
Chon TrOD

I~ ~ 1KY1 f01

EVEN SB
V
SB-5R and TR
SB(s,I-2) __ PR(S 8-9) V
sB(S ,3-11) __ PR(S, 1-9)
IBR J4(Dl)
5B
L-SB -IBR J 4(D2)
ODD 5B
sB-5R and TR
SB(S, 1-2) -PR(S,S-9)
SB(S 3-11) - PR(S, 1-9)
V
5B-JBR I4(01)
SB IBR 14(D2

V

V

V

Norm,,1

KVl I~ ~ ~
V

V
V
V
V

V

V
V

V

V

V

V
V

V

V

V
V

V
V-

V

V

V
V

V

V

V
V

V
V

V
V

V

V

V-

V

V
V-

V
V-

V

V

V

V

V
V
V

V-

V

V

Master E Time

Figure 74 shows condensed logic for the E cycle. Note
that this E cycle can be initiated by an instruction in
either the program register or lBR depending on overlap conditions. In either case, the E time trigger is
turned on by 6- time of the preceding cycle to allow
memory addressing. In this manner, E time provides
memory addressing for its own data reference.
Outputs from the E time trigger may be blocked
until channel B time requests are satisfied. This same
situation exists for I time, which was described previously. After all of the B times are satisfied, the blocking is removed and the computer proceeds with the
instruction.
The master E time trigger is reset at E4 time; however, by use of delays, E time gating circuits are extended until the end of the cycle. E time outputs include:
1. E time early for addressing (not deconditioned
bYlA)

2. E time early
3. E time early (for lA)
4. E time late
5. E time late (for lA)
Note that, unless specifically labeled «for lA," E time
gatings (with exception of E time for addressing) are
blocked during an lA (indirect address) cycle. In this
manner the instruction execution is blocked until the
normal E cycle (not lA cycle) occurs. If an instruction
requires several consecutive E cycles (CVR, for exampIe) the master E time trigger is set and reset for each
cycle.
IA E Cycle

Indirect addressing requires making a second reference to core storage. This second reference either obtains the actual data word in cases of data handling
instructions (CLA, ADD, etc.), or the new transfer address in cases of transfer instructions (TRA, TQO, etc.).
During the first memory reference (IA E cycle), a
new word is brought into the storage register from a
location specified by positions 21-35 of the original instruction word. Positions 21-35 of the lA word contain,
in effect, a new memory reference. This new address
when sent to core storage retrieves the desired data (or
transfer address) .
Several examples of indirect addressing are shown
in an earlier section of this manual, «Instruction Addressing."
The basic objectives of an lA cycle are:
l. Make proper reference to memory for the IA
word.
2. Gate the storage bus even/odd into the storage
register.
82

3. Perform address modification according to the
tag specified in the lA word.
4. Determine and initiate the next type of machine
cycle.
5. Select the proper memory(s) and gate the corresponding address(es) to MAR(S).
An lA cycle can be initiated by an instruction in
either the program register (I time) or the lBR (II time).
See Figure 77. Test conditions for the IA cycle are similar in either case.
Indirect addressing has the following restrictions:
1. The instruction must be indexable. Non-indexable
instructions such as the class A type (TlX, TNX, etc.)
make use of the entire decrement portion of the instruction word for indexing purposes. Therefore,. positions 12 and 13 lose their meaning for indirect addressing. Other non-indexable instructions such as PAX, PXA,
SXA, SXD, etc., actually operate on the index register and
are, therefore, not subject to address modification.
2. Except for transfer instructions, indirect addressing is only possible on instructions of 2X, 3X, 4X, 5X,
and 6X operation codes. Codes below 2X and above
6X require L cycles for their execution. Without references to core storage, indirect addressing has no purpose.
3. Transfer instructions can normally be indirectly
addressed. However, this feature is nullified (except
for TTR/ESNT) if the machine is in the trap mode of
operation. When in the trap mode, the address of the
transfer instruction is stored in location 000008 and if
the transfer conditions are met, the computer traps to
location 00001 8 • Because a transfer is never actually
made to the transfer address, indirect addressing in
the trap mode accomplishes no useful purpose. The
programmer's trap subroutine must test to determine
if indirect addressing existed in the transfer instruction.
If the lA cycle is initiated by the program register
instruction, a pre lA trigger is turned on. If the IA cycle
is initiated by the IBR instruction a pre IIA trigger is
turned on. In either case, a common lA trigger is turned
on at the next EO time.
II times are blocked from occurring simultaneously
with the E( lA) cycle because of a conflict in usage of
the index adders at 5 time.
Note that during an II cycle the instruction in the
program register may detect a skip condition which
will bypass the overlapping instruction. A trap condition may also demand recognition ahead of the overlapping instruction. In either of these two cases, overlapping is nullified and the E( lA) cycle is blocked from
occurring.
If the lA cycle is requested by the overlapping instruction (i.e., II time), the lA cycle must wait for an

end-op signal from the instruction in the program register. This condition would occur, for example, if the
overlapping instruction is preceded by a multiply instruction. See example on Figure 77.
IA Memory Reference: The address to be gated to
MAR depends on whether the IA cycle was initiated by
a preceding I or II cycle. This fact is determined by
the OFF and ON states of the end-op trigger, respectively, and causes gating of either the address register
or IBR to MAR (Figure 77). Note that only one address
is sent and only one memory is selected.
A check is made to determine if the value in the address register or IBR is even! odd. If odd, the AR odd
trigger is turned on for later references. The even!odd
conditions are also dependent on whether the computer is in normal or diagnostic mode of operation.
Storage Bus Gating: The data word arriving at E4
time is gated into the storage register. The proper bus
is determined by the status of the AR odd trigger (Figure 77).
Address Modification: At E ( IA) 5 (D 1) time, Figure
77, SR( 21-35) are routed to the index adders together
with the complement of the specified index register. A
carry to XAD( 17) causes 2's complement addition and
the index register value is effectively subtracted from
SR( 21-35).

This new modified memory address is set into the
address register for gating to MAR at E6( D2) time.
This modified address is also gated to IBR( 21-35) if the
IBR loaded trigger is off. If the IBR loaded trigger is off,

the IA cycle was initiated from an II cycle. Under these
conditions, an II cycle may follow the IA cycle. Routing
the modified address to the IBR allows use of memory
conflict detection circuits on Systems 08.00.22.2 (5F).
Next Machine Cycle: One cycle transfer instructions
end-op during the IA cycle; therefore, the next cycle
will be an I cycle. Two cycle transfer instructions require an L cycle to complete operation. Because of
this, an L cycle will follow the IA cycle.
If a I-cycle or 2-cycle transfer condition does not
exist, the next cycle must be an E cycle (except for
possible B cycle interrupts). If conditions allow, an II
cycle may also occur simultaneously with this next E
cycle. Note that the path which turns on the II time
trigger (Figure 77) also turns on the E time trigger.
The reverse condition, however, is not true.
MAR Gating and Selection: A I-cycle E ( IA) transfer
end-op causes two sequential addresses to be sent to
MAR from the address register and index adders. This
condition was covered in a previous section on I time
and in Figure 75.
All other conditions force a data E cycle with the
modified data address sent to MAR from the address
register. If an II cycle is also allowed to occur, the program counter is sent to MAR to fetch a new overlapping
instruction. There is one condition on the PC~MAR gating, however. The IBR loaded trigger being on indicates
an II time without a reference to memory because the
IBR had already been loaded with an instruction during
the previous I time.

Timing

83

Basic IA Cycle Objecti yes

Ves

1. Address memory for IA data word - E6(D2)

2. GateSBtoSR- E4(Dl)
3. Perform Address Modification - E5(Dl)
4. Initiate next machine cycle - E6(Dl)

5. Address Memory -l/E/lI6(D2)

t - - - - - - - - - - - - - - - - - 1 - . _ Indirect Addressint not

Indirect Address not
possible - proceed normally.
The Pre IIA trigger is normally reset at

possible - proceed normally.

the next A2(Dl) time.

~ The Pre IA trigger is reset at the

An overlap conflict or skip condition will
reset the Pre lIA trigger immediately at
6-time.

next A2(DI) time.

II time is not allowed to occur
simultaneously with an E(lA} cy~

1. Reset II Time Tgr

1. Reset I Time Tgr

2. Block II~II
08.00.22.2 (2C)
08.00.22.2 (5E)

2. ResetIlTimeTgr
08.00.18.2 (3B)
08.00.22.2 (2C)

On

Indicates that the
~
instruction in the PR is skipping
around the overlapping Inst.

Ves

A function of the U

Indicates that a condition (such as a channel?
trap) is nullifying the overlap operation.

The f time trigger can not be
turned on until the imtruction
/
in the PR has completed operation.
Example: 0 CLA

n

1 MPV

II

2 ADD'

I

The end-op trigger being off ot this time
indicates an IA cycle initiated by the PR
instruction during an I cycle

E(lA)

The end-op trigger being on at this time
indicates on IA cycle initiated by the IBR
instruction during an II cycle.
The end-op trigger is turned off at

E4(D I) time of the I A cycle.
Systems 08.00.19.2(41 )

Reset ot E7 CP set time of the IA cycle

E4(Dl)
SB-SR
02.12.52.2 (3A)

----.r--

E4(Dl)
SB(18-20) ........TR
02.12.52. 2(3A), 0J.05.22.1 (SA)

The IBR loaded trigger being on ot this time
indi cates entrance from an I cycle with on
overlapping instruction in the IBR .,..------.-::~..(

The IBR loaded trigger being OFF ot this time
indicates entrance from an II cycle.

}---:::::.:....------,

The modified address is also placed into the

~ IBR to make use of the PC-IBR memory conFlict
checking circuitry on Systems OB.OO.22.2(5F}.

On

Ve,

This is really a memory conflict check of the AR and PC. The AR ====~
value was also set into the lBR at the previous E(IA)5(Dl) Time .......

Turned on because of
no request for 1 or E
time
Both paths must be used if
the 11 time trigger was
turned ON.

E(IA)S CP Set
Turn On I Time Tgr
08.00.18.2 (3C)

If the IBR loaded trigger is ON at th;s
time, the tBR had already been loaded ----....r--..On
with a second instruction during
the preceding I time.

See the I time flow
chart (Figure 76) for
complete detoi Is of
address gating.

/

16(D2)
AR-MAR
AR+l-MAR
03.08.15.1

~

Figure 77.

IA

Cycle Flow Chart

"'"
~~---A76~C~P~S-et-------'
Turn On L Time Trigger

08.00.20.2 (3C)

Master L Time

HTR

L time provides a logic cycle of operation during which
the computer performs functions not related to core
storage.
Control circuitry (Figure 74) is similar in some respects to E time because it can be initiated by an instruction in either the program register or IBR depending on overlap conditions (only IBR shift instructions
can force an L cycle).
The turn-on logic is such that an L cycle occurs if
the instruction does not specifically call for an I or E
cycle. The I or E turn-on is at A5 CP set; if these I or
E controls are not present, the master L time trigger is
turned on one clock pulse later at A6 CP set.
As long as the input PR or IBR controls are active, the
L time trigger is turned on again each cycle. In this
manner, the L time trigger remains on as long as
needed. Use of delay circuitry produces both "L time
early" and "L time late" outputs for circuit controls in
CPU-l and CPU-2.
When the master stop trigger is turned on, the computer remains at whatever cycle time it was proceeding
to when the master stop trigger came on. An inhibit L
trigger is turned on by the master stop trigger (Figure
78) to block both the master L time and II time outputs
(Figure 74).
The inhibit L trigger is also turned on by the HTR
and HPR instructions. L time of these two halt instructions is blocked until the start key is depressed. At this
time, the inhibit L trigger is turned off and the computer either transfers or proceeds to the next instruction.

B Interrupt For
L Time

MST Off
Not I Time Late
6 CP Set

(Blocks L & II
Times)
08.00.21.2

Figure 78. Inhibit L Trigger Logic

During channel operations, the CPU remains in L
time until the next instruction is begun.
Master II Time

II time (IBR I time) is the instruction cycle for the overlapping instruction in the IBR. During this cycle address modification and preliminary tests are performed
by the overlapping instruction. When not prohibited,
II time occurs simultaneously with either an E or L
cycle of the preceding instruction.
Figure 79 shows basic condensed logic of the II time
trigger circuitry. Note that II time can be initiated by
instruction controls from either the program register or
IBR. The II time trigger is turned on at 6 time of the
preceding cycle to allow memory addressing. In this
manner, II time performs memory addressing for its
own data reference.
Details of II time together with an II time How chart
are found in Volume 3.

II Time Tgr

E Time Tgr
CP Set
Conditioning and
Blocking Circuits

II Time Early

Gen Reset
Pre IIA Tgr

II Time Late
08.00.22.2

Figure 79. II Time Condensed Logic

86

Master B Time

B (buffer) time is the cycle during which one of the
data channels makes reference to core storage. Most
I/O devices move at a fixed rate and therefore request
or transmit data at specific intervals. When data word
requests are not serviced in time, information is lost
and I/O checks result. Because of this timing requirement, channel B cycle demands are serviced during the
cycle immediately following the request. If the next
CPU cycle is to be an I, E or II cycle, the output of the
master trigger is blocked. If the next CPU cycle is to be
a normal L cycle, both the Band L cycles occur simultaneously.
"B cycle demand" is sent out by the channel early in
the cycle such that the signal arrives at the multiplexor
before channel 9 time. Provided the computer is not
servicing a channel trap or a POD 64 instruction, the
master B time trigger is turned on with the next channel A9(Dl) pulse (Figure 80).

The POD 64 (store channel instruction) restriction prevents a possible alteration in the channel registers
which would cause false error indications while running CE diagnostic programs. B time requests are
blocked during channel trap operations to prevent destroying the trap address in the buffer address register.
The B time request occurs at channel 7 time. Channels requesting additional B cycles cause the B time
trigger to be turned on again in time to prevent the
CPU from regaining cycle control. "Retain priority" conditions (TCH or IA) recognized by the multiplexor lookahead circuitry bypasses the normal turn-on controls.
The B interrupt trigger (Figure 80) blocks outputs
from the master I, E, and II time triggers either during
B times or when the master stop trigger is on. Note that
the B time trigger is under control of channel clock
pulses whereas the B interrupt trigger is under control
of CPU clock pulses. The B time trigger turning on
causes the B interrupt trigger to turn on at CPU-5 time
which is early enough to block the next cyclic output
from the master I, E, and II triggers.

MST On
AS(Dl)
B Interrupt
MST Off
AS CP Set

Ch A9(Dl)
Not POD 64
Not Trap to Channel
B Cycle Demand

(Blocks I, E and II times)

A

Retain Priority (3G)
Ch A7(Dl)

B Time
(B Time Gating)

Figure 80. B Time Condensed Logic

Timing

87

interrupt trigger only blocks one CPU I, E or II cycle.
Case 2 shows the channel 9-CPU-5 timing relationship
where both the B time and B interrupt triggers turn on
during the same clock pulse. In this later case, however,
the timings are such that the B interrupt trigger remains on for one extra cycle and two CPU cycles are
blocked.

Because of timing relationships between the channel
and CPU clocks, the B interrupt trigger can be turned
on and off for two cases (Figure 81). Case 1 shows the
channel 9-CPU-I timing relationship where the B time
trigger turns on at channel 9 time and the B interrupt
trigger turns on four clock pulses later at CPU-5 time.
Considering only one channel B cycle request, the B

Item

B Cycle Demand

B

B Time Trigger

I

C

B Interrupt Trigger

!

I
I

CPU I, E & " times
blocked due to B time

B Cycle Demand

CPU I, E & " times
blocked due to B time

01234567012

B-7

3~5670

I

I

I

I

I

i

1

I

I
I

I B-CPU5

:

B-CPU~

I

I

l i t

I

I
I

Ie
.....
-------1
I
I

I

I

II

CI

I

__

~I----_I
I
I

I

I
I

II

I

I

I
I

I
I

I

I

3

I

I

A-9

r
B-CPU5

I
I
I

2

l~

___________________:

I

B-7

I

I

s-cPu51

,~__________~"______~______
I ______~i""-I""""""""-I~~

I

I

C1
. . . . . . . . . . . . . . ._ _ _ _..

'~------------~,--------l~------~:--------------~

Figure 81. B Time Sequence Chart

88

I

I

I

I,

I

'I

II
D

7

I~----------r___----,~--~r

I

B Interrupt Trigger

6

I

A-9'

I

B Time Trigger

C

~567012345

3

I

CASE 2
A

2

I

I

I

:

D

0 0 0
1 2 3 4 5 6 7 8 9 10 11
1 2 3 4 5 6 7 8 9 10 11
1 2 3 4

~
2
~~----.I-------I--~I
3

A

10 11

I

C

B Cycle

The main system objectives associated with B cycles
are to:
1. Accept B time requests from the data channel
2. Set BAR to the proper address
3. Select the proper even/odd memory
4. Route data and commands to the proper system
areas
5. Test and perfonn TCH and IA functions
6. Initiate subsequent B cycles where applicable
B cycle requests are initiated by circuitry from within the attached data channels and are based on the immediate channel demands. In most cases, the "B cycle
demand" is honored during the cycle following receipt
into the cpu. Refer to Figure 82.
A "B cycle demand" arriving during the execution of
a channel trap operation or POD 64 (store channel) instruction is delayed until after their completion. These
delays are necessary because of conflicts in usage with
the buffer address register, and for diagnostic programming reasons, respectively.
"B cycle demands" are initiated at approximately
channel 3 time and arrive at the cpu circuitry in time
to tum on the B time trigger with a channel A9(Dl)
pulse. The B time interrupt trigger is turned on at
cpu 5 time to block the master I, E, and II time outputs.
This blocking remains in effect until cpu A5 time following the turn off of the B time trigger (Figure 81).
Instruction overlap is suspended during all B cycles.
Only one memory (even/odd) is addressed, and only
one memory select pulse is generated. Therefore, only
one data word is placed on the storage bus.
SDW Cycle

The first function perfonned (Figure 82) is setting
the buffer address register (BAR) to the proper memory
data reference as specified by the channel address
switches (CAS). BAR was reset by a previouschannelAl1
pulse and is now set at BO(D2) time. For a read BDW
cycle, the channel store trigger is turned on to provide
the necessary memory "read-out" and "store" controls.
Selection of the proper memory and BAR gating is
based on BAR(17). The memory select pulse is initiated
at approximately B2 time. For a write BDW cycle, the
data word is available on the storage bus at approximately B7 time for sampling into the channel's data
register. For a read BDW cycle, the channel has the
data word on the storage bus at the proper time to be
sampled into the memory buffer register (Figure 35).
SCW Cycle

Consider a nonnal BCW cycle with no indirect addressing or TCH command (Figure 82). Accepting the
"B cycle demand," turning on the B time trigger and
selecting memory are as explained previously. The

channel determines the memory location by routing an
address from its location counter/command counter
into the multiplexor buffer address register.
Note that all BCW cycles have the characteristics of a
write operation where the data word is taken from
memory and sent to the channel.
The data command read from memory is placed on
the storage bus and sampled into the channel's operation register, word counter and address register. The
channel's location counter (7607) or command counter
(7909) is stepped +1 to indicate the next sequential
command's location.
If the channel is performing a write operation at the
time of the BCW cycle, a BDW cycle is immediately requested. This BDW cycle may not be initiated in time,
however, to prevent the cpu from regaining program
control. This channel must also seek priority with other
channels requesting B cycles on the system.
Indirectly Addressed SCW Cycle

Consider IA commands other than TCH (Figure 82). Accepting the "B cycle demand," turning on the B time
trigger, and selecting memory are the same as explained previously. The initial pass through the flow
chart finds the IA address control trigger off.
Position 18 of both the even and odd storage bus are
oR'ed together, MB(18), as a test for indirect addressing.
oR'ing both storage buses is valid because only one of
the buses will contain information.
Ignore for the moment the special case of a proceed
type command with a word count equal zero. The command word on the storage bus is sampled into the
channel's operation register, word counter, and address register. The operation register and word counter
contain valid data; the address register contents will
be replaced with a new value during the next cycle.
Because of SB(18), an IA address control trigger is
turned on which generates and sends a "retain priority"
signal to all channels (Figure 82). In the multiplexor,
"retain priority" produces an immediate "B cycle demand" and prevents the B time trigger from being
reset. In this manner a second B cycle is initiated and
the cpu is prevented from regaining control.
The IA address control trigger being on allows an
IND 18 trigger to be turned on and its "IND 18" Signal
sent out on banks 1 and 2 to all data channels.
The address portion of the initial BCW data word represents a new memory reference. Because of this, multiplexor storage bus positions 21-35 are routed directly
into the buffer address register (Figure 35). The data
word resulting from the second BCW cycle is placed on
the storage bus as before. This time, however, the data
channel only accepts the address portion (21-35) into
its address register; the original operation coding and
word count remain unaltered. Following this second
Timing

89

cycle, the channel's location counter/command
counter is stepped +1.
The IA address control trigger is turned off at channel A3(D2) time and the IND 18 trigger is turned off at
the following channel AI0(D2). Timing is such that
only one level of indirect addressing is permitted. A bit
in SB( 18) of the second BCW word is ignored and the
IND 18 trigger is not turned on again.
A special case of a proceed type command with a
word count equal zero was ignored in the previous discussion. An IOCP, IORP, or IOSP command with a word
count equal zero must be bypassed. Indirect addressing, therefore, performs no logic and is ignored (Figure
82). The command is routed to the channel and set into
the operation register, word counter and address register as usual. Channel circuitry recognizes the zero word
count condition and initiates another "B cycle demand." Multiplexor lookahead circuitry does not retain
priority in this case.

BCW

TCH Command

Consider a TCH command without indirect addressing.
The TCH acts as a channel transfer instruction to alter
the sequence of I/O commands being executed. The
transfer is accomplished by altering the value in the
channel's location counter (7607) or command counter
(7909). The channel determines the memory location
by routing an address from its location counter/command counter into the multiplexor's buffer address
register (BAR). Accepting the initial "B cycle demand,"
turning on the B time trigger and selecting memory are
as explained previously.
The TCH command is detected (Figure 82) by testing
the storage bus for not S, not 1, 2. The 7607 data channel's operation register, word counter and address register are set as usual; the 7909 sets only the address
register and a TCH trigger. A TCH address control trigger is turned on in the multiplexor and a second B cycle
is immediately initiated by "retain priority."
The address portion of the TCH command contains
the transfer-to address. This address is immediately set

90

into the buffer address register for the next memory
reference. The address is also set into the channel location counter/command counter to indicate the new I/O
command sequence.
The second BCW cycle places the new I/O command
on the storage bus and the operation continues as explained preViously. This new command (Figure 82)
may be a TCH command, another I/O command, or an
indirectly addressed I/O command.
Indirectly Addressed TCH Command

An IA TCH command operates similar in.most respects
to the normal TCH (Figure 82). During the first BCW
cycle, the storage bus indicates not S, not 1, 2, and 18.
As a result, both the "TCH address control" and "IA address control" triggers are turned on. "Retain priority"
circuitry in the multiplexor immediately initiates a second BCW cycle and turns on the IND 18 trigger. The new
(IA) memory reference is routed from SB(21-35) and set
into the buffer address register. Note that "IND 18" control circuitry in the channel prevents setting of the location counter/command counter during the first BCW
cycle.
At channel A3 time, the IA address control trigger is
turned off but the reset to the TCH address control trigger is blocked. "Retain priority" is maintained because
of the TCH address control trigger and the multiplexor
immediately requests the third BCW cycle.
During the second BCW cycle, the address portion of
this IA data word contains the actual TCH transfer-to
address. This address is immediately set into the buffer
address register for the third memory reference, and
also set into the channel location counter/command
counter to indicate the new I/O command sequence.
The IND 18 trigger is turned off during the second BCW
cycle which, in turn, allows the address control trigger
to be turned off at channel A3 time.
The third BCW cycle places the new I/O command on
the storage bus and the operation continues as explained previously.

From Sheet 2
1.
2.
3.
4.
5.
6.

Wait for channel
B cycle demand

Accept B time Requests from channel
Set BAR to proper address
Select the proper even/odd memory
Route data and commands to proper system areas
Test and perform TCH and IA functions
Initiate subsequent B cycles where applicable

Wait unti I completion of either
the channe I trap
or POD 64 /V'"
operation

~

The B Time Interrupt trigger is turned ON at
CPU A5(Dl) time to block the Master I, E,
and II time outputs. This blocking remains
until CPU A5 time following the turn OFF
of the B time trigger.

From Sheet 2
(Start Next Sequential BCW Cycle)

On

Reset at Chan A 10 time following
turn off of the IA address control
trigger

B11 (Dl)
/
Turn On
Ind 18 Trigger
06.10.01.l(2C)

The master B time trigger
reset occurs at every
Channel A7(Dl)

7

The I A Address Control trigger
--z.-and TCH Address Control trigger
will both be in the OFF status on

~:":" :";:":";':" :" :' ':' ' ';' :-Jfu'

"'oo,h >h.

fI~ ,hort.

06.10.01.1(2G,2H)
Off

Data Channel
BAR/
1. Loc Cntr
(7607)
2. Cmmd Cntr
(7909)

B8 -A3
SB -BAR
/
06. 10.00. 1(3C)

~

This gating occurs
after BAR has been
set from the SB

Ch All(Dl)
Reset BAR
03.06.27.1(3H)

The new address is routed directly
from multiplexor circuitry into BAR.
The All(Dl) BAR reset pulse does
not occur at this time because of
"retain priority" being active.

ChAll(Dl)
Reset Chan
Store Tgr
01.00.00.1 (3C)

BO(D2)
CAS --BAR
06.10.00.1 (2B)

BDW Cycles - CAS set from Channel
Address Counter.
BCW Cycles - CAS set from Channel
Location Counter
(7607) or Command
Counter (7909).

...-z---:::

BCW

Even Memory RO
Odd Memory RO
Store prefix
Core Storage
Controls
~ Store Decrement
Store Tag
Store Address
01.00.00.1

(2D)
(2E)
(4D)
(2F)
(4E)
(4F)

B2(Dl) Dlyd
Select Memory
03.06.29.4(3F)

B2(Dl) Dlyd
Select Memory
03.06.29.4(3B)

To Sheet 2

Figure 82. B Time Flow Chart (Sheet 1 of 2)
Timing

91

From Sheet 1

On

(Data Word Cycle)
BOW

!

This trigger will always be OFF on the first
pass through the flow chart.
The trigger being turned ON prevents a second
IA cycle. (Only one level of indirect addressing
is allowed}.

Off

~Also LlPT command for 7909

, . - _......_'" ~

data channel

No

Yes

No

Yes .¥'I--J~~P Channel Commands
10RP
IOSP

/

.( Storage Bus
(3-17) = 0

Yes

Data Channel
Set (7607)
1. Opn Reg.
2. Word Cntr
3. Addr Cntr

Data Channel

~
1. Opn Reg
2. Word Cntr
3. Addr Cntr

Write

Channel initiates
another request for
B (BOW) Cycle
and retains
priority.

The multiplexor retains
priority because the TCH
address control tri gger
was not turned off during
the previous cycle.

To Sheet 1
(Start Next Sequential BCW Cycle)

To Sheet 1

Figure 82. B Time Flow Chart (Sheet 2 of 2)
92

Data Channel
Set
1. Opn Reg
2. Word Cntr
3. Addr Cntr
Step
1. TciCCntr/
2 Cmmd Cntr

Data Channel
Set
1. Op,;-Reg
2. Word Cntr
3. Addr Cntr

1.
2

Channel Cycle Times

Channel L Time

Three channel cycle time triggers (Figure 83) have
been added in CPU-2 to supply 2.1 microsecond cycle
times for data channel usage. While these three cycle
time triggers are controlling the channel, the CPU waits
in CPU L time until the channel operation is completed.
The end of the channel operation is indicated by the
"MF go" trigger which turns on the end-op trigger and
sends the CPU into its next cycle time.

The channel L time trigger (Figure 83) provides 2.1
microsecond cycles necessary for channel operations.
These operations include all of the I/O select, sense,
and test instructions. POD 54 instructions (RCH/LCH/
RSC/STC) also require L cycles prior to the time that the
channel may signal a "proceed to E."
Note that the channel L time trigger is turned on at
channel 11 time which may be aligned with either a
CPU 3 or 7 pulse. Synchronism is not performed as with
the preceding channel E time trigger.

Channell Time

The channel I time trigger (Figure 83) is not the first
channel cycle trigger to be turned on as might be
thought. Instead, it is the last channel cycle time available (I time next) and performs mostly housekeeping
functions (I time resets) in the channel.
Channel E Time

The channel E time trigger (Figure 83) provides a 2.1
microsecond cycle for channel operations requiring a
reference to core storage. These operations would include: enable, store channel, POD 54(RCH/LCH/RSC/STC),
and channel traps.
Circuit controls and timings are such that the channel EO time is aligned with the CPU 4 time. This alignment is necessary for POD 64 and enable instructions.
The channel E time indicates the end of a channel
operation. Because of this, the MF go trigger is turned
on late in the channel E cycle to force an end-op condition and allow the CPU program to continue with the
next instruction.

Channel-CPU Cycle Time Controls

Two triggers are used to control cycle times. The channel "L-E end" trigger controls channel cycle times, and
the "MF go" trigger controls the CPU time.
The channel L-E end trigger coming on signals the
end of the channel operation. In some cases, the channel I time trigger is then turned on to accomplish
housekeeping resets to the channel.
The MF go trigger is normally on. At the start of the
channel operation, the MF go trigger is turned off
which, in turn, turns the "L end-op sync" trigger on
(Figure 83). When the channel operation is completed,
the MY go trigger is turned on again and the output of
tlie "L end-op sync" trigger is gated to produce an "E
or L end-op." This latter signal turns on the end-op
trigger and allows the CPU to continue with the next
instruction.

Timing

93

SOD 02 (Read)
SOD 06 (Write)

I

(~)

'"AO

Not Tape Class AdcIress
Chan End Op
Chan A 1O(D 1)
Any

I/o Test

gj;]IhO"
~

or Sense

,

(4C)

,

Channel E Time

,. } To Channel
Banks 1 & 2

Channel L Time

,

08.00.27.1

-: -AO
~,

~

~

(4B)

""

,..---

... ~

AO

4.- I-~

POD 54
Proceed to E

(4D) H

~
AO

~~

Chan E Time

~

L-I-~

Channel Trap

~

L

Any Select
or Test or
POD 54
A
(3F)

J---------...

Not
POD 54

~

.-1-

(4E)

~

~

A
(4F)

~

~

t---<~

I-r:; Elf
R 3F

AO

08.00.28.1

.... ~
~

Not MST I
Time Early

(4F)

... ~

=

-

AO

Chan L Time

~

POD 54

Reset Ctrl
CTearTtri
Interlock
Reset On
Load

Channel I Time
I R(3D)
'~

I (~)

POD 64
IA Ctrl Tgr Off'
Not A3(D2) (CPU Pulse)
Ch All (D1)
Not B Time
Not BCW

Not
Proceed
to E

T

Ch A6(D1)

Enable

r Hm.

~

T

(4G)

J (5~) I
~

I

-====.

~r>

L

~J-------.....
(:H)

~ "'"'R'('3R)
~R(3R)

0
(4B)
04.20.12.1

'--'---'-

08.00.29.1
Reset CT
Tgrs

A
(4E)

~

T(OR)

AO

,

(4F)
AO

~~

TLJ

Not Manual Stop
Not Channel Trap
13 D1)
Tape Class Addr or POD 54

~1mHr

~ >--

~~

08.00.27.1

,.......

(41)

L End-Op Sync

r---

L--

A
(4S)

L Time Late

n
I'I' ~ U
~

r=-=
~
A

~o(Off~]

P"'"

0

I--

A
(4D)
'----

Ch AO(D1)
L Time
A4(D1)
POD 54
POD 64

(3C)

~

-.

AO
(3D)

I'W J'--~
AO
~~

~

~

(3F)

~

'-+ T(OR)

r---

(4E)

T

94

_:::,~,JOff)

l
.,.
;:-=
,.
~

Figure 83. Channel Cycle Time Logic

Chan L-E

r----

Any I/o Sense or Test
Ch A8(D 1) Delayed
Chan End-Op
Chan A10(D1)

(On)

~~
08.00.27.2

A
(3S)

l~

T

~~
~

R
0"8:"00.02. 2

A

E or L
End-Op

L Time
B Interrupt
I Time
E Time

II Time Late
Not L Time Late
Not E Time Late
A2(Dl)

AO

(3H)

A1(Dl)
A5(Dl)

Mult Time

Mult Time Error
Lite On CE Panel
,

.:

Chan A9(Dl)
CP Set
08.00.22.2

\

I 1;-

-:.

Turn On MST Tgr

~ln.:..:..te::..:.r~lo=ck::......:R=e=5e-,-t_ _ _~ R(2E)

08.00.17.1

Figure 84. Multiple Time Check Circuitry

Multiple Cycle Time Error Detection

Eight different cycle times and two separate clocks
exist in the 7094 II. Only certain cycles can occur simultaneously without causing machine malfunctions. Illegal cycle combinations turn on a multiple time trigger
which immediately stops the computer and lights a
mult time light on the console CE panel.
Test circuitry (Figure 84) monitors the various CPU
cycle times once every cycle. The top group of circuits
checks for the following illegal combinations: I and E;
L and I; Land E; B and I; and Band E.
Note that Band L times are allowed to occur simultaneously.
II time is allowed to occur Simultaneously with an E
or L cycle. II time occurring without either an E or L
time is detected at A0 3H •
Clock alignment is checked at A0 3I • Every channel
A9(DI) pulse should occur Simultaneously with either
a CPU AI(DI) or A5(DI) pulse. An absence of these
conditions turns on the multiple time trigger.
There is no check on multiple channel cycle times.

Waveforms and Variable Delay Adjustments
The oscilloscope being used must contain probes of
the same length. Test the oscilloscope by placing both
probes on the same point and noting if there is any
difference in the time relationship between the A and
B sweeps.
The following adjustments should be made in the
order presented because in some cases a later adjustment is based on the proper earlier setting. It must be
remembered, however, that many of these settings are
nominal (starting point) settings and may vary slightly
with later adjustments or from system to system.

Initial Delay Settings

All variable delays shall be set to the nominal values
specified on Systems 00.92.01.0 (sheets "1 and 2) before
proceeding with the following adjustments. Timings
for F lines should be measured at the 1.5 volt level.

Timing

95

Odd and Even Clock Drive Pulses

Odd and even clock drive pulses should meet all requirements of the waveform shown in Figures 85 and
86 when observed at 03A4C15F (Systems 08.00.44.1,
IF).

Ref -6v

CP Set Pulses

set pulses should meet all requirements ()f the waveform shown in Figure 87 when observed at 01AIC12C
(Systems 02.15.6l.1,4D) and 01BIC20B (Systems
02.15.61.2,5E).

t1 = t2 within 7ns

CP

Figure 85. Clock Drive Pulse

CPU-l CP Set Pulse Width Adjustment

Connect the scope probe to the test points indicated
below and adjust the CP set pulse width by means of
the corresponding V7 delay card. The first two adjustments determine the CP set pulse widths at the A and
B gates, respectively. The last width adjustment is for
setting the FACT triggers during arithmetic operations
and is more critical than most other set pulses.
TEST POINT

LEVEL

01A1E13E
01B1E24B
01B1F21C

-F
-F
+F

WIDTH

DLY LOCATION

50 ± 3 ns 01A1E14 (A-H)
60 ± 3 ns 01B1E25 (B-G)
40 ± 3ns 01B1E12 (D-E)

SYSTEMS

02.15.61.1,4B
02.15.61.2,4A
02.15.61.2,2B
Figure 86. Even and Odd Clock Drive Pulses

CP Set Pulse-Clock Pulse Alignment

In this section the multiplexor CP set pulse is adjusted
with respect to the A7(Dl) CPU-l pulse. This A7(Dl)
pulse is already properly aligned to the CPU-2 pulse because of the VB delay 01D2E21 (Systems 02.15.42.1,
3H).
1. Synchronize the scope on "-F A6(D2)" at 01AlB14B (Systems 02.15.71.1, 4H).
2. Connect scope probe A to "-F A7(Dl)" at 01BlC05E (Systems 02.15.70.8, 41).
3. Connect scope probe B to "+ F CP set" at 01BlE24C (Systems 02.15.61.2, 5A).
4. Adjust the variable delay control at 03B3D03
(Systems 08.00.47.1, 4C) so that the fall of the set pulse
occurs 10 nanoseconds before the fall of the "-F
A7(Dl)" pulse. This 10 nanosecond timing is measured
at the point where both pulses cross the F reference
level (Figure 88).
The optimum multiplexor delay line operation point
is determined by running 9M8l. The setting is the midpoint of the error free operating range of 9M81 running
at normal voltage as the delay line is varied. After determining the optimum operating point and without
disturbing the delay line adjustment, remove and reinstall the delay line knob at 03B3D03 to read zero.

96

1 .5v Ref

t1 = t2 within4ns

Figure 87.

CP

Set Pulse

Figure 88.

CP

Set Pulse--Clock Pulse Alignment

CPU and Channel Memory Select Alignment

Memory selection occurs with different clock pulses
(and from different clocks) when initiated during either
CPU or channel operations. These two memory selects
must be aligned to insure proper operation when memory is being alternately used by both the CPU and
channel.
1. Synchronize the scope on "+F A6(Dl)" at 01AlB05G (Systems 02.15.70.7, 41).
2. Connect scope probe A to "+ F A2(Dl)" at 01A4J24E (Systems 03.06.29.4, 3B).
3. Connect scope probe B to "+F A7(Dl)" at 01A4J24G (Systems 03.06.29.4, 3A).
4. Adjust the V7 delay card at 03A4J17 (A-H) (Systems 08.00.40.1, IG) so that the rise of the channel
A2(Dl) dlyd pulse crosses the reference line at the
same time as the A7(Dl)S pulse, ±3 nanoseconds as
shown in Figure 89.

Figure 89. Memory Select Pulse Alignment

Memory Select and MAR Bus Alignment

This section checks that the MAR bus pulses precede
the MAR set pulse by at least 20 nanoseconds. This
check is made at both the even and odd memories. Figure 90 shows a representative pulse. Note that all of the
test points are at the 7302-3 panels.
1. Execute either a TRA (+0020) 77776, 0 or TRA
77777, 0 as indicated below in continuous enter instruction.
2. Synchronize the scope on "-FE time" at
01A2E12P (Systems 08.00.19.3, 3A). This test point is
in the CPU.
3. Connect scope probe A to the MAR set point indicated below.
4. Connect scope probe B to the MAR bus points indica ted below.
5. All of the MAR bus lines should precede their respective MAR set pulses by at least 20 nanoseconds.

CONDITIONS
Instruction
MAR set
MAR4
MAR 8
MAR 12
MAR 16

EVEN MEMORY
TRA 77776,0
01B3C16D (01.11.01.1 -3B) Probe A
01B3C16E (01.11.01.1 -3B) Probe B
01B3C18E (01.11.01.1 -3F) Probe B
01B3C20V (01.11.02.1 -3C) Probe B
01B3C22V (01.11.02.1 -3G) Probe B

Figure 90. Memory Select-MAR Bus Alignment

ODD MEMORY
TRA 77777,0
01C3C16D (01.41.01.1 -3B) Probe A
01C3C16E (01.41.01.1 -3B) Probe B
01C3C18E (01.41.01.1 -3F) Probe B
01C3C20V (01.41.02.1 -3C) Probe B
01C3C22V (01.41.02.1 -3G) Probe B

Timing

97

Appendix A: Octal-Decimal Integer Conversion Table

0000

0000

to
0777

to
0511

(Octal)

(Decimal)

Octal Decimal

10000- 4096
20000 - 8192
30000 - 12288
40000 - 16384
50000 - 20480·
60000 - 24576
70000 - 28672

1000

0512

to
1777
(Octal)

to
1023

98

(Decimal)

0

1

2

3

4

5

6

7

0000
0010
0020
0030
0040
0050
0060
0070

0000
0008
0016
0024
0032
0040
0048
0056

0001
0009
0017
0025
0033
0041
0049
0057

0002
0010
0018
0026
0034
0042
0050
0058

0003
0011
0019
0027
0035
0043
0051
0059

0004
0012
0020
0028
0036
0044
0052
0060

0005
0013
0021
0029
0037
0045
0053
0061

0006
0014
0022
0030
0038
0046
0054
0062

0007
0015
0023
0031
0039
0047
0055
0063

0100
0110
0120
0130
0140
0150
0160
0170

0064
0072
0080
0088
0096
0104
0112
0120

0065
0073
0081
0089

0066
0074
0082
0090
00~7 0098
0105 0106
0113 0114
0121 0122

0067
0075
0083
0091
0099
0107
0115
0123

0068
0076
0084
0092
0100
0108
0116
0124

0069
0077
0085
0093
0101
0109
0117
0125

0070
0078
0086
0094
0102
0110
0118
0126

0200
0210
0220
0230
0240
0250
0260
0270

0128
0136
0144
0152
0160
0168
0176
0184

0129
0137
0145
0153
0161
0169
0177
0185

0130
0138
0146
0154
0162
0170
0178
0186

0131
0139
0147
0155
0163
0171
0179
0187

0132
0140
0148
0156
0164
0172
0180
0188

0133
0141
0149
0157
0165
0173
0181
0189

0300
0310
0320
0330
0340
0350
0360
0370

0192
0200
0208
0216
0224
0232
0240
0248

0193
0201
0209
0217
0225
0233
0241
0249

0194
0202
0210
0218
0226
0234
0242
0250

0195
0203
0211
0219
0227
0235
0243
0251

0196
0204
0212
0220
0228
0236
0244
0252

0

1

2

3

1000
1010
1020
1030
1040
1050
1060
1070

0512
0520
0528
0536
0544
0552
0560
0568

0513
0521
0529
0537
0545
05.53
0561
0569

0514
0522
0530
0538
0546
0554
0562
0570

1100
1110
1120
1130
1140
1150
1160
1170

0576
0584
0592
0600
0608
0616
0624
0632

0577
0585
0593
0601
0609
0617
0625
0633

1200
1210
1220
1230
1240
1250
1260
1270

0640
0648
0656
0664
0672
0680
0688
0696

1300
1310
1320
1330
1340
1350
1360
1370

0704
0712
0720
0728
0736
0744
0752
0760

0

1

2

3

4

5

6

7

0400
0410
0420
0430
0440
0450
0460
0470

0256
0264
0272
0280
0288
0296
0304
0312

0257
0265
0273
0281
0289
0297
0305
0313

0258
0266
0274
0282
0290
0298
0306
0314

0259
0267
0275
0283
0291
0299
0307
0315

0260
0268
0276
0284
0292
0300
0308
0316

0261
0269
0277
0285
0293
0301
0309
0317

0262
0270
0278
0286
0294
0302
0310
0318

0263
0271
0279
0287
0295
0303
0311
0319

0071
0079
0087
0095
0103
0111
0119
0127

0500
0510
0520
0530
0540
0550
0560
0570

0320
0328
0336
0344
0352
0360
0368
0376

0321
0329
0337
0345
0353
0361
0369
0377

0322
0330
0338
0346
0354
0362
0370
0378

0323
0331
0339
0347
0355
0363
0371
0379

0324
0332
0340
0348
0356
0364
0372
0380

0325
0333
0341
0349
0357
0365
0373
0381

0326
0334
0342
0350
0358
0366
0374
0382

0327
0335
0343
0351
0359
0367
0375
0383

0134
0142
0150
0158
0166
0174
0182
0190

0135
0143
0151
0159
0167
0175
0183
0191

0600
0610
0620
0630
0640
0650
0660
0670

0384
0392
0400
0408
0416
0424
0432
0440

0385
0393
0401
0409
0417
0425
0433
0441

0386
0394
0402
0410
0418
0426
0434
0442

0387
0395
0403
0411
0419
0427
0435
0443

0388
0396
0404
0412
0420
0428
0436
0444

0389
0397
0405
0413
0421
0429
0437
0445

0390
0398
0406
0414
0422
0430
0438
0446

0391
0399
0407
0415
0423
0431
0439
0447

0197
0205
0213
0221
0229
0237
0245
0253

0198
0206
0214
0222
0230
0238
0246
0254

0199
0207
0215
0223
0231
0239
0247
0255

0700
0710
0720
0730
0740
0750
0760
0770

0448
0456
0464
0472
0480
0488
0496
0504

0449
0457
0465
0473
0481
0489
0497
0505

0450
0458
0466
0474
0482
0490
0498
0506

0451
0459
0467
0475
0483
0491
0499
0507

0452
0460
0468
0476
0484
0492
0500
0508

0453
0461
0469
0477
0485
0493
0501
0509

0454
0462
0470
0478
0486
0494
0502
0510

0455
0463
0471
0479
0487
0495
0503
0511

4

5

6

7

0

1

2

3

4

5

6

7

0515
0523
0531
0539
0547
0555
0563
0571

0516
0524
0532
0540
0548
0556
0564
0572

0517
0525
0533
0541
0549
0557
0565
0573

0518
0526
0534
0542
0550
0558
0566
0574

0519
0527
0535
0543
0551
0559
0567
0575

1400
1410
1420
1430
1440
1450
1460
1470

0768
0776
0784
0792
0800
0808
0816
0824

0769
0777
0785
0793
0801
0809
0817
0825

0770
0778
0786
0794
0802
0810
0818
0826

0771
0779
0787
0795
0803
0811
0819
0827

077~

0780
0788
0796
0804
0812
0820
0828

0773
0781
0789
0797
0805
0813
0821
0829

0774
0782
0790
0798
0806
0814
0822
0830

0775
0783
0791
0799
0807
0815
0823
0831

0578
0586
0594
0602
0610
0618
0626
0634

0579
0587
0595
0603
0611
0619
0627
0635

0580
0588
0596
0604
0612
0620
0628
0636

0581
0589
0597
0605
0613
0621
0629
0637

0582
0590
0598
0606
0614
0622
0630
0638

0583
0591
0599
0607
0615
0623
0631
0639

1500
1510
1520
1530
1540
1550
1560
1570

0832
0840
0848
0856
0864
0872
0880
0888

0833
0841
0849
0857
0865
0873
0881
0889

0834
0842
0850
0858
0866
0874
0882
0890

0835
0843
0851
0859
0867
0875
0883
0891

0836
0844
0852
0860
0868
0876
0884
0892

0837
0845
0853
0861
0869
0877
0885
0893

0838
0846
0854
0862
0870
0878
0886
0894

0839
0847
0855
0863
0871
0879
0887
0895

0641
0649
0657
0665
0673
0681
0689
0697

0642
0650
0658
0666
0674
0682
0690
0698

0643
0651
0659
0667
0675
0683
0691
0699

0644
0652
0660
0668
0676
0684
0692
0700

0645
0653
0661
0669
0677
0685
0693
0701

0646
0654
0662
0670
0678
0686
0694
0702

0647
0655
0663
0671
0679
0687
0695
0703

1600
1610
1620
1630
1640
1650
1660
1670

0896
0904
0912
0920
0928
0936
0944
0952

0897
0905
0913
0921
0929
0937
0945
0953

0898
0906
0914
0922
0930
0938
0946
0954

0899
0907
0915
0923
0931
0939
0947
0955

0900
0908
0916
0924
0932
0940
0948
0956

0901
0909
0917
0925
0933
0941
0949
0957

0902
0910
0918
0926
0934
0942
0950
0958

0903
0911
0919
0927
0935
0943
0951
0959

0705
0713
0721
0729
0737
0745
0753
0761

0706
0714
0722
0730
0738
0746
0754
0762

0707
0715
0723
0731
0739
0747
0755
0763

0708
0716
0724
0732
0740
0748
0756
0764

0709
0717
0725
0733
0741
0749
0757
0765

0710
0718
0726
0734
0742
0750
0758
0766

0711
0719
0727
0735
0743
0751
0759
0767

1700
1710
1720
1730
1740
1750
1760
1770

0960
0968
0976
0984
0992
1000
1008
1016

0961
0969
0977
0985
0993
1001
1009
1017

0962
0970
0978
0986
0994
1002
1010
1018

0963
0971
0979
0987
0995
1003
1011
1019

0964
0972
0980
0988
0996
1004
1012
1020

0965
0973
0981
0989
0997
1005
1013
1021

0966
0974
0982
0990
0998
1006
1014
1022

0967
0975
0983
0991
0999
1007
1015
1023

Octal-Decimal Integer Conversion Table (Continued)

2000
2010
2020
2030
2040
2050
2060
2070

0

1

2

3

4

5

6

7

1024
1032
1040
1048
1056
1064
1072
1080

1025
1033
1041
1049
1057
1065
1073
1081

1026
1034
1042
1050
1058
1066
1074
1082

1027
1035
1043
1051
1059
1067
1075
1083

1028
1036
1044
1052
1060
1068
1076
1084

1029
1037
1045
1053
1061
1069
1077
1085

1030
1038
1046
1054
1062
1070
1078
1086

1031
1039
1047
1055
1063
1071
1079
1087

I

2400
2410
2420
2430
2440
2450
2460
2470

0

1

2

3

4

5

6

7

1280
1288
1296
1304
1312
1320
1328
1336

1281
1289
1297
1305
1313
1321
1329
1337

1282
1290
1298
1306
1314
1322
1330
1338

1283
1291
1299
1307
1315
1323
1331
1339

1284
1292
1300
1308
1316
1324
1332
1340

1285
1293
1301
1309
1317
1325
1333
1341

1286
1294
1302
1310
1318
1326
1334
1342

1287
1295
1303
1311
1319
1327
1335
1343

1349
1357
1365
1373
1381
1389
1397
1405

1350
1358·
1366
1374
1382
1390
1398
1406

1351
1359
1367
1375
1383
1391
1399
1407

2100
2110
2120
2130
2140
2150
2160
2170

1088
1096
1104
1112
1120
1128
1136
1144

1089
1097
1105
1113
1121
1129
1137
1145

1090
1098
1106
1114
1122
1130
1138
1146

1091
1099
1107
1115
1123
1131
1139
1147

1092
1100
1108
1116
1124
1132
1140
1148

1093
1101
1109
1117
1125
1133
1141
1149

1094
1102
1110
1118
1126
1134
1142
1150

1095
1103
1111
1119
1127
1135
1143
li51

2500
2510
2520
2530
2540
2550
2560
2570

1344
1352
1360
1368
1376
1384
1392
1400

1345
1353
1361
1369
1377
1385
1393
1401

1346
1354
1362
1370
1378
1386
1394
1402

1347
1355
1363
1371
1379
1387
1395
1403

1348
1356
1364
1372
1380
1388
1396
1404

2200
2210
2220
2230
2240
2250
2260
2270

1152
1160
1168
1176
1184
1192
1200
1208

1153
1161
1169
1177
1185
1193
1201
1209

1154
1162
1170
1178
1186
1194
1202
1210

1155
1163
1171
1179
1187
1195
1203
1211

1156
1164
1172
1180
1188
1196
1204
1212

1157
1165
1173
1181
1189
1197
1205
1213

1158
1166
1174
1182
1190
1198
1206
1214

1159
1167
1175
1183
1191
1199
1207
1215

2600
2610
2620
2630
2640
2650
2660
2670

1408
1416
1424
1432
1440
1448
1456
1464

1409
1417
1425
1433
1441
1449
1457
1465

1410
1418
1426
1434
1442
1450
1458
1466

1411
1419
1427
1435
1443
1451
1459
1467

1412
1420
1428
1436
1444
1452
1460
1468

1413
1421
1429
1437
1445
1453
1461
1469

1414
1422
1430
1438
1446
1454
1462
1470

1415
1423
1431
1439
1447
1455
1463
1471

2300
2310
2320
2330
2340
2350
2360
2370

1216
1224
1232
1240
1248
1256
1264
1272

1217
1225
1233
1241
1249
1257
1265
1273

1218
1226
1234
1242
1250
1258
1266
1274

1219
1227
1235
1243
1251
1259
1'267
1275

1220
1228
1236
1244
1252
1260
1268
1276

1221
1229
1237
1245
1253
1261
1269
1277

1222
1230
1238
1246
1254
1262
1270
1278

1223
1231
1239
1247
1255
1263
1271
1279

2700
2710
2720
2730
2740
2750
2760
2770

1472
1480
1488
1496
1504
1512
1520
1528

1473
1481
1489
1497
1505
1513
1521
1529

1474
1482
1490
1498
1506
1514
1522
1530

1475
1483
1491
1499
1507
1515
1523
1531

1476
1484
1492
1500
1508
1516
1524
1532

1477
1485
1493
1501
1509
1517
1525
1533

1478
1486
1494
1502
1510
1518
1526
1534

1479
1487
1495
1503
1511
1519
1527
1535

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

3000
3010
3020
3030
3040
3050
3060
3070

1536
1544
1552
1560
1568
1576
1584
1592

1537
1545
1553
1561
1569
1577
1585
1593

1538
1546
1554
1562
1570
1578
1586
1594

1539
1547
1555
1563
1571
1579
1587
1595

1540
1548
1556
1564
1572
1580
1588
1596

1541
1549
1557
1565
1573
1581
1589
1597

1542
1550
1558
1566
1574
1582
1590
1598

1543
1551
1559
1567
1575
1583
1591
1599

3400
3410
3420
3430
3440
3450
3460
3470

1792
1800
1808
1816
1824
1832
1840
1848

1793
1801
1809
1817
1825
1833
1841
1849

1794
1802
1810
1818
1826
1834
1842
1850

1795
1803
1811
1819
1827
1835
1843
1851

1796
1"804
1812
1820
1828
1836
1844
1852

1797
1805
1813
1821
1829
1837
1845
1853

1798
1806
1814
1822
1830
1838
1846
1854

1799
1807
1815
1823
1831
1839
1847
1855

3100
3110
3120
3130
3140
3150
3160
3170

1600
1608
1616
1624
1632
1640
1648
1656

1601
1609
1617
1625
1633
1641
1649
1657

1602
1610
1618
1626
1634
1642
1650
1658

1603
1611
1619
1627
1635
1643
1651
1659

1604
1612
1620
1628
1636
1644
1652
1660

1605
1613
1621
1629
1637
1645
1653
1661

1606
1614
1622
1630
1638
1646
1654
1662

1607
1615
1623
1631
1639
1647
1655
1663

3500
3510
3520
3530
3540
3550
3560
3570

1856
1864
1872
1880
1888
1896
1904
1912

1857
1865
1873
1881
1889
1897
1905
1913

1858
1866
1874
1882
1890
1898
1906
1914

1859
1867
1875
1883
1891
1899
1907
1915

1860
1868
1876
1884
1892
1900
1908
1916

1861
1869
1877
1885
1893
1901
1909
1917

1862
1870
1878
1886
1894
1902
1910
1918

1863
1871
1879
1887
1895
1903
1911
1919

3200
3210
3220
3230
3240
3250
3260
3270

1664
1672
1680
1688
1696
1704
1712
1720

1665
1673
1681
1689
1697
1705
1713
1721

1666
1674
1682
1690
1698
1706
1714
1722

1667
1675
1683
1691
1699
1707
1715
1723

1668
1676
1684
1692
1700
1708
1716
1724

1669
1677
1685
1693
1701
1709
1717
1725

1670
1678
1686
1694
1702
1710
1718
1726

1671
1679
1687
1695
1703
1711
1719
1727

3600
3610
3620
3630
3640
3650
3660
3670

1920
1928
1936
1944
1952
1960
1968
1976

1921
1929
1937
1945
1953
1961
1969
1977

1922
1930
1938
1946
1954
1962
1970
1978

1923
1931
1939
1947
1955
1963
1971
1979

1924
1932
1940
1948
1956
1964
1972
1980

1925
1933
1941
1949
1957
1965
1973
1981

1926
1934
1942
1950
1958
1966
1974
1982

1927
1935
1943
1951
1959
1967
1975
1983

3300
3310
3320
3330
3340
3350
3360
3370

1728
1736
1744
1752
1760
1768
1776
1784

1729
1737
1745
1753
1761
1769
1777
1785

1730
1738
1746
1754
1762
1770
1778
1786

1731
1739
1747
1755
1763
1771
1779
1787

1732
1740
1748
1756
1764
1772
1780
1788

1733
1741
1749
1757
1765
1773
1781
1789

1734
1742
1750
1758
1766
1774
1782
1790

1735
1743
1751
1759
1767
1775
1783
1791

3700
3710
3720
3730
3740
3750
3760
3770

1984
1992
2000
2008
2016
2024
2032
2040

1985
1993
2001
2009
2017
2025
2033
2041

1986
1994
2002
2010
2018
2026
2034
2042

1987
1995
2003
2011
2019
2027
2035
2043

1988
1996
2004
2012
2020
2028
2036
2044

1989
1997
2005
2013
2021
2029
2037
2045

1990
1998
2006
2014
2022
2030
2038
2046

1991
1999
2007
2015
2023
2031
2039
2047

2000

1024

to

to

2777

1535

(Octal)

(Decimal)

Octal Decimal
10000 - .4096
20000 - 8192
30000 - 12288
.40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672

3000

1536

to

to

3777

2047

(Octal)

(Decimal)

Octal-Decimal Integer Conversion

99

Octal-Decimal Integer Conversion Table (Continued)

.(000
to
,(777

20.(8
to

(Odal)

(Decimal)

2559

Octal Decimal
10000 - 4096
20000 - 8192
30000 - 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672

2560

to
5777

to
3071

(Odal)

(Decimal)

100

5

6

7

2305 2306 2307
2313 2314 2315
2~21 2322 2323
2329 2330 2331
2337 2338 2339
2345 2346 2347
2353 2354 2355
2361 2362 2363

2308
2316
2324
2332
2340
2348
2356
2364

2309
2317
2325
2333
2341
2349
2357
2365

2310
2318
2326
2334
2342
2350
2358
2366

2311
2319
2327
2335
2343
2351
2359
2367

2369
2377
2385
2393
2401
2409
2417
2425

2370
2378
2386
2394
2402
2410
2418
2426

2371
2379
2387
2395
2403
2411
2419
2427

2372
2380
2388
2396
2404
2412
2420
2428

2373
2381
2389
2397
2405
2413
2421
2429

2374
2382
2390
2398
2406
2414
2422
2430

2375
2383
2391
2399
2407
2415
2423
2431

2432
2440
2448
2456
2464
2472
2480
2488

2433
2441
2449
2457
2465
2473
2481
2489

2434
2442
2450
2458
2466
2474
2482
2490

2435
2443
2451
2459
2467
2475
2483
2491

2436
2444
2452
2460
2468
2476
2484
2492

2437
2445
2453
2461
2469
2477
2485
2493

2438
2446
2454
2462
2470
2478
2486
2494

2439
2447
2455
2463
2471
2479
2487
2495

2496
2504
2512
2520
2528
2536
2544
2552

2497
2505
2513
2521
2529
2537
2545
2553

2498
2506
2514
2522
2530
2538
2546
2554

2499
2507
2515
2523
2531
2539
2547
2555

2500
2508
2516
2524
2532
2540
2548
2556

2501
2509
2517
.2525
2533
2541
2549
2557

2502
2510
2518
2526
2534
2542
2550
2558

2503
2511
2519
2527
2535
2543
2551
2559

0

1

2

3

4

5

6

7

1

2

3

4

5

6

7

4000
4010
4020
4030
4040
4050
4060
4070

2048
2056
2064
2072
2080
2088
2096
2104

2049
2057
2065
2073
2081
2089
2097
2105

2050
2058
2066
2074
2082
2090
2098
2106

2051
2059
2067
2075
2083
2091
2099
2107

2052
2060
2068
2076
2084
2092
2100
2108

2053
2061
2069
2077
2085
2093
2101
2109

2054
2062
2070
2078
2086
2094
2102
2110

2055
2063
2071
2079
2087
2095
2103
2111

4400
4410
4420
4430
4440
4450
4460
4470

2304
2312
2320
2328
2336
2344
2352
2360

4100
4110
4120
4130
4140
4150
4160
4170

2112
2120
2128
2136
2144
2152
2160
2168

2113
2121
2129
2137
2145
2153
2161
2169

2114
2122
2130
2138
2146
2154
2162
2170

2115
2123
2131
2139
2147
2155
2163
2171

2116
2124
2132
2140
2148
2156
2164
2172

2117
2125
2133
2141
2149
2157
2165
2173

2118
2126
2134
2142
2150
2158
2166
2174

2119
2127
2135
2143
2151
2159
2167
2175

4500
4510
4520
4530
4540
4550
4560
4570

2368
2376
2384
2392
2400
2408
2416
2424

4200
4210
4220
4230
4240
4250
4260
4270

2176
2184
2192
2200
2208
2216
2224
2232

2177
2185
2193
2201
2209
2217
2225
2233

2178
2186
2194
2202
2210
2218
2226
2234

2179
2187
219.5
2203
2211
2219
2227
2235

2180
2188
2196
2204
2212
2220
2228
2236

2181
2189
2197
2205
2213
2221
2229
2237

2182
2190
2198
2206
2214
2222
2230
2238

2183
2191
2199
2207
2215
2223
2231
2239

4600
4610
4620
4630
4640
4650
4660
4670

4300
4310
4320
4330
4340
4350
4360
4370

2240
2248
2256
2264
2272
2280
2288
2296

2241
2249
2257
2265
2273
2281
2289
2297

2242
2250
2258
2266
2274
2282
2290
2298

2243
2251
2259
2267
2275
2283
2291
2299

2244
2252
2260
2268
2276
2284
2292
2300

2245
2253
2261
2269
2277
2285
2293
2301

2246
2254
2262
2270
2278
2286
2294
2302

2247
2255
2263
2271
2279
2287
2295
2303

4700
4710
4720
4730
4740
4750
4760
4770

0

5000

4

0

0

1

2

3

4

5

6

7

-_.

1

2

3

5000
5010
5020
5030
5040
5050
5060
5070

2560
2568
2576
2584
2592
2600
2608
2616

2561
2569
2577
2585
2593
2601
2609
2617

2562
2570
2578
2586
2594
2602
2610
2618

2563
2571
2579
2587
2595
2603
2611
2619

2564
2572
2580
2588
2596
2604
2612
2620

2565
2573
2581
2589
2597
2605
2613
2621

2566
2574
2582
2590
2598
2606
2614
2622

2567
2575
2583
2591
2599
2607
2615
2623

5400
5410
5420
5430
5440
5450
5460
5470

2816
2824
2832
2840
2848
2856
2864
2872

2817
2825
2833
2841
2849
2857
2865
2873

2818
2826
2834
2842
2850
2858
2866
2874

2819
2827
2835
2843
2851
2859
2867
2875

2820
2828
2836
2844
2852
2860
2868
2876

2821
2829
2837
2845
2853
2861
2869
2877

2822
2830
2838
2846
2854
2862
2870
2878

2823
2831
2839
2847
2855
2863
2871
2879

5100
5110
5120
5130
5140
5150
5160
5170

2624
2632
2640
2648
2656
2664
2672
2680

2625
2633
2641
2649
2657
2665
2673
2681

2626
2634
2642
2650
2658
2666
2674
2682

2627
2635
2643
2651
2659
2667
2675
2683

2628
2636
2644
2652
2660
2668
2676
2684

2629
2637
2645
2653
26tH
2669
2677
2685

2630
2638
2646
2654
2662
2670
2678
2686

2631
2639
2647
2655
2663
2671
2679
2687

5500
5510
5520
5530
5540
5550
5560
5570

2880
2888
2896
2904
2912
2920
2928
2936

2881
2889
2897
2905
2913
2921
2929
2937

2882
2890
2898
2906
2914
2922
2930
2938

2883
2891
2899
2907
2915
2923
2931
2939

2884
2892
2900
2908
2916
2924
2932
2940

2885
2893
2901
2909
2917
2925
2933
2941

2886
2894
2902
2910
2918
2926
2934
2942

2887
2895
2903
2911
2919
2927
2935
2943

5200
5210
5220
5230
5240
5250
5260
5270

2688
2696
2704
2712
2720
2728
2736
2744

2689
2697
2705
2713
2721
2729
2737
2745

2690
2698
2706
2714
2722
2730
2738
27'6

2691
2699
2707
2715
2723
2731
2739
2747

2692
2700
2708
2716
2724
2732
2740
2748

2693
2701
2709
2717
2725
2733
2741
2749

2694
2702
2710
2718
2726
2734
2742
2750

2695
2703
2711
2719
2727
2735
2743
2751

5600
5610
5620
5630
5640
5650
5660
5670

2944
2952
2960
2968
2976
2984
2992
3000

2945
2953
296.1
2969
2977
2985
2993
3001

2946
2954
2962
2970
2978
2986
2994
3002

2947
2955
2963
2971
2979
2987
2995
3003

2948
2956
2964
2972
2980
2988
2996
3004

2949
2957
2965
2973
2981
2989
2997
3005

2950
2958
2966
2974
2982
2990
2998
3006

2951
2959
2967
2975
2983
2991
2999
3007

5300
5310
5320
5330
5340
5350
5360
5370

2752
2760
2768
2776
2':84
2792
2800
2808

2753
2761
2769
2777
2785
2793
2801
2809

2754
2762
2770
2778
2786
2794
2802
2810

2755
2763
2771
2779
2787
2795
2803
2811

2756
2764
2772
2780
2788
2796
2804
2812

2757
2765
2773
2781
2789
2797
2805
2813

2758
2766
2774
2782
2790
2798
2806
2814

2759
2767
2775
2783
2791
2799
2807
2815

5700
5710
5720
5730
5740
5750
5760
5770

3008
3016
3024
3032
3040
3048
3056
3064

3009
3017
3025
3033
3041
3049
3057
3065

3010
3018
3026
3034
3042
3050
3058
3066

3011
3019
3027
3035
3043
3051
3059
3067

3012
3020
3028
3036
3044
3052
3060
'3068

3013
3021
3029
3037
3045
3053
3061
3069

3014
3022
3030
3038
3046
3054
3062
3070

3015
3023
3031
3039
3047
3055
3063
3071

Octal-Decimal Integer Conversion Table (Continued)

4

5

6

7

3331
3339
3347
3355
3363
3371
3379
3387

3332
3340
3348
3356
3364
3372
3380
3388

3333
3341
3349
3357
3365
3373
3381
3389

3334
3342
3350
3358
3366
3374
3382
3390

3335
3343
3351
3359
3367
3375
3383
3391

3394
3402
3410
3418
3426
3434
3442
3450

3395
3403
3411
3419
3427
3435
3443
3451

3396
3404
3412
3420
3428
3436
3444
3452

3397
3405
3413
3421
3429
3437
3445
3453

3398
3406
3414
3422
3430
3438
3446
3454

3399
3407
3415
3423
3431
3439
3447
3455

3457
3465
3473
3481
3489
3497
3505
3513

3458
3466
3474
3482
3490
3498
3506
3514

3459
3467
3475
3483
3491
3499
3507
3515

3460
3468
3476
3484
3492
3500
3508
3516

3461
3469
3477
3485
3493
3501
3509
3517

3462
3470
3478
3486
3494
3502
3510
3518

3463
3471
3479
3487
3495
3503
3511
3519

3520
3528
3536
3544
3552
3560
3568
3576

3521
3529
3537
3545
3553
3561
3569
3577

3522
3530
3538
3546
3554
3562
3570
3578

3523
3531
3539
3547
3555
3563
3571
3579

3524
3532
3540
3548
3556
3564
3572
3580

3525
3533
3541
3549
3557
3565
3573
3581

3526
3534
3542
3550
3558
3566
3574
3582

3527
3535
3543
3551
3559
3567
3575
3583

0

1

2

3

4

5

6

7

3840
3848
3856
3864
3872
3880
3888
3896

3841
3849
3857
3865
3873
3881
3889
3897

3842
3850
3858
3866
3874
3882
3890
3898

3843
3851
3859
3867
3875
3883
3891
3899

3844
3852
3860
3868
3876
3884
3892
3900

3845
3853'
3861
3869
3877
3885
3893
3901

3846
3854
3862
3870
3878
3886
3894
3902

3847
3855
3863
3871
3879
3887
3895
3903

0

1

2

0

1

2

3

4

5

6

7

6000
6010
6020
6030
6040
6050
6060
6070

3072
3080
3088
3096
3104
3112
3j20
3128

3073
3081
3089
3097
3105
3113
3121
3129

3074
3082
3090
3098
3106
3114
3122
3130

3075
3083
3091
3099
3107
3115
3123
3131

3076
3084
3092
3100
3108
3116
3124
3132

3077
3085
3093
3101
3109
3117
3125
3133

3078
3086
3094
3102
3110
3118
3126
3134

3079
3087
3095
3103
3111
3119
3127
3135

6400
6410
6420
6430
6440
6450
6460
6470

3328
3336
3344
3352
3360
3368
3376
3384

3329
3337
3345
3353
3361
3369
3377
3385

3330
3338
3346
3354
3362
3370
3378
3386

6100
6110
6120
6130
6140
6150
6160
6170

3136
3144
3152
3160
3168
3176
3184
3192

3137
3145
3153
3161
3169
3177
3185
3193

3138
3146
3154
3162
3170
3178
3186
3194

3139
3147
3155
3163
3171
3179
3187
3195

3140
3148
3156
3164
3172
3180
3188
3196

3141
3149
3157
3165
3173
3181
3189
3197

3142
3150
3158
3166
3174
3182
3190
3198

3143
3151
3159
3167
3175
3183
3191
3199

6500
6510
6520
6530
6540
6550
6560
6570

3392
3400
3408
3416
3424
3432
3440
3448

3393
3401
3409
3417
3425
3433
3441
3449

6200
6210
6220
6230
6240
6250
6260
6270

3200
3208
3216
3224
3232
3240
3248
3256

3201
3209
3217
3225
3233
3241
3249
3257

3202
3210
3218
3226
3234
3242
3250
3258

3203
3211
3219
3227
3235
3243
3251
3259

3204
3212
3220
3228
3236
3244
3252
3260

3205
3213
3221
3229
3237
3245
3253
3261

3206
3214
3222
3230
3238
3246
3254
326~

3207
3215
3223
3231
3239
3247
3255
3263

6600
6610
6620
6630
6640
6650
6660
6670

3456
3464
3472
3480
3488
3496
3504
3512

6300
6310
6320
6330
6340
6350
6360
6370

3264
3272
3280
3288
3296
3304
3312
3320

3265
3273
3281
3289
3297
3305
3313
3321

3266
3274
3282
3290
3298
3306
3314
3322

3267
3275
3283
3291
3299
3307
3315
3323

3268
3276
3284
3292
3300
3308
3316
3324

3269
3277
3285
3293
3301
3309
3317
3325

3270
3278
3286
3294
3302
3310
3318
3326

3271
3279
3287
3295
3303
3311
3319
3327

6700
6710
6720
6730
6740
6750
6760
6770

0

1

2

3

4

5

6

7

7000 3584 3585 3586 3587 3588 3589 3590 3591

3

7'020
7030
7040
7050
7060
7070

3600
3608
3616
3624
3632
3640

3601
3609
3617
3625
3633
3641

3602
3610
3618
3626
3634
3642

3603
3611
3619
3627
3635
3643

3604
3612
3620
3628
3636
3644

3605
3613
3621
3629
3637
3645

3606
3614
3622
3630
3638
3646

3607
3615
3623
3631
3639
3647

7400
7410
7420
7430
7440
7450
7460
7470

7100
7110
7120
7130
7140
7150
7160
7170

3648
3656
3664
3672
3680
3688
3696
3704

3649
3657
3665
3673
3681
3689
3697
3705

3650
3658
3666
3674
3682
3690
3698
3706

3651
3659
3667
3675
3683
3691
3699
3707

3652
3660
3668
3676
3684
3692
3700
3708

3653
3661
3669
3677
3685
3693
3701
3709

3654
3662
3670
3678
3686
3694
3702
3710

3655
3663
3671
3679
3687
3695
3703
3711

7500
7510
7520
7530
7540
7550
7560
7570

3904
3912
3920
3928
3936
3944
3952
3960

3905
3913
3921
3929
3937
3945
3953
3961

3906
3914
3922
3930
3938
3946
3954
3962

3907
3915
3923
3931
3939
3947
3955
3963

3908
3916
3924
3932
3940
3948
3956
3964

3909
3917
3925
3933
3941
3949
3957
3965

3910
3918
3926
3934
3942
3950
3958
3966

3911
3919
3927
3935
3943
3951
3959
3967

7200
7210
7220
7230
7240
7250
7260
7270

3712
3720
3728
3736
3744
3752
3760
3768

3713
3721
3729
3737
3745
3753
3761
3769

3714
3722
3730
3738
3746
3754
3762
3770

3715
3723
3731
3739
3747
3755
3763
3771

3716
3724
3732
3740
3748
3756
3764
3772

3717
3725
3733
3741
3749
3757
3765
3773

3718
3726
3734
3742
3750
3758
3766
3774

3719
3727
3735
3743
3751
3759
3767
3775

7600
7610
7620
7630
7640
7650
7660
7670

3968
3976
3984
3992
4000
4008
4016
4024

3969
3977
3985
3993
4001
4009
4017
4025

3970
3978
3986
3994
4002
4010
4018
4026

3971
3979
3987
3995
4003
4011
4019
4027

3972
3980
3988
3996
4004
4012
4020
4028

3973
398r
3989
3997
4005
4013
4021
4029

3974
3982
3990
3998
4006
4014
4022
4030

3975
3983
3991
3999
4007
4015
4023
4031

7300
7310
7320
7330
7340
7350
7360
7370

3776
3784
3792
3800
38{)8
3816
3824
3832

3777
37-85
3793
3801
3809
3817
3825
3833

3778
3786
3794
3802
3810
3818
3826
3834

3779
3787
3795
3803
3811
3819
3827
3835

3780
3788
3796
3804
3812
3820
3828
3836

3781
3789
3797
3805
3813
3821
3829
3837

3782
3790
3798
3806
3814
3822
3830
3838

3783
3791
3799
3807
3815
3823
3831
3839

7700
7710
7720
7730
7740
7750
7760
7770

4032
4040
4048
4056
4064
4072
4080
4088

4033
4041
4049
4057
4065
4073
4081
4089

4034
4042
4050
4058
4066
4074
4082
4090

4035
4043
4051
4059
4067
4075
4083
4091

4036
4044
4052
4060
4068
4076
4084
4092

4037
4045
4053
4061
4069
4077
4085
4093

4038
4046
4054
4062
4070
4078
4086
4094

4039
4047
4055
4063
4071
4079
4087

1.010 3592 3593 3594 3595 3596 3597 3598 3599

6000

3072

to

to

6777

3583

(Octal)

(Decimal)

Octa I Decima I

10000 - 4096
20000 - 8192
30000 - 12288
40000 - 16384
50000 - 20480
60000 - 24576
70000 - 28672

7000

3584

to

to

7777

"095

(Odal)

(Decimal)

40~5

Octal-Decimal Integer Conversion

101

Appendix B: Octal-Decimal Fraction Conversion Table

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC.

.000
.001
.002
.003
.004
.005
.006
.007
.010
.011
.012
.013
.014
.015
.016
.017
.020
.021
.022
.023
.024
.025
.026
.027
.030
.031
.032
.033
.034
.\)35
.036
.037
.040
.041
.042
.043
.044
.045
.046
.047
.050
.051
.052
.053
.054
.055
.056
.057
.060
.061
.062
.063
.064
.065
.066
.067
.070
.071
.072
.073
.074
.075
.076
.077

.000000
.001953
.003906
.005859
.007812
.009765
.011718
.013671
.015625
.017578
.019531
.021484
.023437
.025390
.027343
.029296
.031250
.033203
.035156
.037109
.039062
.041015
.042968
.044921
.046875
.048828
.050781
.052734
.054687
.056640
.058593
.060546
.062500
.064453
.066406
.068359
.070312
.072265
.074218
.076171
.078125
.080078
.082031
.083984
.085937
.087890
.089843
.091796
.093750
.095703
.097656
.099609
.101562
.103515
.105468
.107421
.109375
.111328
.113281
.115234
.117187
.119140
.121093
.123046

.100
.101
.102
.103
.104
.105
.106
.107
.110
.111
.112
.113
.114
.115
.116
.117
.120
.121
.122
.123
.124
.125
.126
.127
.130
.131
.132
.133
.134
.135
.136
.137
.140
.141
.142
.143
.144
.145
.146
.147
.150
.151
.152
.153
.154
.155
.156
.157
.160
.161
.162
.163
.164
.165
.166
.167
.170
.171
.172
.173
.174
.175
.176
.177

.125000
.126953
.128906
.130859
.132812
.134765
.136718
.138671
.140625
.142578
.144531
.146484
.148437
.150390
.152343
.154296
.156250
.158203
.160156
.162109
.164062
.166015
.167968
.169921
.171875
.173828
.175781
.177734
.179687
.181640
.183593
.185546
.187500
.189453
.191406
.193359
.195312
.197265
.199218
.201171
.203125
.205078
.207031
.208984
.210937
.212890
.214843
.216796
.218750
.220703
.222656
.224609
.226562
.228515
.230468
.232421
.234375
.236328
.238281
.240234
.242187
.244140
.246093
.248046

.200
.201
.202
.203
.204
.205
.206
.207
.210
.211
.212
.213
.214
.215
.216
.217
.220
.221
.222
.223
.224
.225
.226
.227
.230
.231
.232
.233
.234
.235
.236
.237
.240
.241
.242
.243
.244
.245
.246
.247
.250
.251
.252
.253
.254
.255
.256
.257
.260
.261
.262
.263
.264
.265
.266
.267
.270
.271
.272
.273
.274
.275
.276
.277

.250000
.251953
.253906
.255859
.257812
.259765
.261718
.263671
.265625
.267578
.269531
.271484
.273437
.275390
.277343
.279296
.281250
.283203
.285156
.287109
.289062
.291015
.292968
.294921
.296875
.298828
.300781
.302734
.304687
.306640
.308593
.310546
.312500
.314453
.316406
.318359
.320312
.322265
.324218
.326171
.328125
.330078
.332031
.333984
.335937
.337890
.339843
.341796
.343750
.345703

.300
.301
.302
.303
.304
.305
.306
.307
.310
.311
.312
.313
.314
.315
.316
.317
.320
.321
.322
.323
.324
.325
.326
.327
.330
.331
.332
.333
.334
.335
.336
.337
.340
.341
.342
.343
.344
.345
.346
.347
.350
.351
.352
.353
.354
.355
.356
.357
.360
.361
.362
.363
.364
.365
.366
.367
.370
.371
.372
.373
.374
.375
.376
.377

.3.75000
.376953
.378906
.380859
.382812
.384765
.386718
.388671
.390625
.392578
.394531
.396484
.398437
.400390
.402343
.404296
.406250
.408203
.410156
.412109
.414062
.416015
.417968
.419921
.421875
.423828
.426781
.427734
.429687
.431640
.433593
.435546
.437500
.439453
.441406
.443359
.445312
.447265
.449218
.451171
.453125
.455078
.457031
.458984
.460937
.462890
.464843
.466796
.468750
.-470703
.472656
.474609
.476562
.478515
.480468
.482421
.484375
.486328
.488281
.490234
.492187
.494140
.496093
.498046

102

~347656

.349609
.351562
.353515
.355468
.357421
.359375
.361328
.363281
.365234
.367187
.369140
.371093
.373046

Octal-Decimal Fraction Conversion Table (Continued)

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC.

.000000
.000001
.000002
.000003
.000004
.000005
.000006
.000007
.000010
.000011
.000012
.000013
.000014
.000015
.000016
.000017
.000020
.000021
.000022
.000023
.000024
.000025
.000026
.000027
.000030
.000031
.000032
.000033
.000034
.000035
.000036
.000037
.000040
.000041
.000042
.000043
.000044
.000045
.000046
.000047
.000050
.000051
.000052
.000053
.000054
.000055
.000056
.000057
.000060
.000061
.000062
.000063
.000064
.000065
.000066
.000067
.000070
• 000071
.000072
.000073
.000074
.000075
.000076
.000077

.000000
.000003
.000007
.000011
.000015
.000019
.000022
.000026
.000030
.000034
.000038
.000041
.000045
.000049
.000053
.000057
.000061
.000064
.000068
.000072
.000076
.000080
.000083
.000087
.000091
.000095
.000099
.000102
.000106
.000110
.000114
.000118
.000122
.000125
.000129
.000133
.000137
.000141
.000144
.000148
.000152
.000156
.000160
.000164
.000167
.000171
.000175
.000179
.000183
.000186
.000190
.000194
.000198
.000202
.000205
.000209
.000213
.000217
.000221
.000225
.000228
.000232
.000236
.000240

.000100
.000101
.000102
.000103
.000104
.000105
.000106
.000107
.000110
.000111
.000112
.000113
.000114
.000115
.000116
.000117
.000120
.000121
.000122
.000123
.000124
.000125
.000126
.000127
.000130
.000131
.000132
.000133
.000134
.000135
.000136
.000137
.000140
.000141
.000142
.000143
.000144
.000145
.000146
.000147
.000150
.000151
.000152
.000153
.000154
.000155
.000156
.000157
.000160
.000161
.000162
.000163
.000164
.000165
.000166
.000167
.000170
.000171
.000172
.000173
.000174
.000175
.000176
.000177

.000244
.000247
.000251
.000255
.000259
.000263
.000267
.000270
.000274
.000278
.000282
.000286
.000289
.000293
.000297
.000301
.000305
.000308
.000312
.000316
.000320
.000324
.000328
.000331
.000335
.000339
.000343
.000347
.000350
.000354
.000358
.000362
.000366
.000370
.000373
.000377
.000381
.000385
.000389
.000392
.000396
.000400
.000404
.000408
.000U1
.000415
.000419
.000423
.000427
.000431
.000434
.000438
.000442
.000446
.000450
.000453
.000457
.000461
.000465
.000469
.000473
.000476
.000480
.000484

.000200
.000201
.000202
.000203
.000204
.000205
.000206
.000207
.000210
.000211
.000212
.000213
.000214
.000215
.000216
.000217
.000220
.000221
.000222
.000223
.000224
.000225
.000226
.000227
.000230
.000231
.000232
.000233
.000234
.000235
.000236
.000237
.000240
.000241
.000242
.000243
.000244
.000245
.000246
.000247
.000250
.000251
.000252
.000253
.000254
.000255
.000256
.000257
.000260
.000261
.000262
.000263
.000264
.000265
.000266
• ()00267
.000270 .
.0002'71
.000272
.000273
.000274
.000275
.000276
.000277

.000488
.000492
.000495
.000499
.000503
.000507
.000511
.000514
.000518
.000522
.000526
.000530
.000534
.000537
.000541
.000545
.000549
.000553
.000556
.000560
.000564
.000568
.000572

.000300
.000301
.000302
.000303
.000304
.000305
.000306
.000307
.000310
.000311
.000312
.000313
.000314
.000315
.000316
.000317
.000320
.000321
.000322
.000323
.000324
.000325
.000326

.000732
.000736
.000740
.000743
.000747
.000751
.000755
.000759
.000762
.000766
.000770
.000774
.000778
.000782
.000785
.000789
.000793
.000797
.000801
.000805
.000808
.000812
.000816
.000820
.000823
.000827
.000831
.000835
.000839
.000843
.000846
.000850
.000854
.000858
.000862
.000865
.000869
.000873
.000877
.000881
.000885
.000888
.000892
.000896
.000900
.000904
.000907
.000911
• 000911~
.000919
.000923
.000926
.000930
.000934
.000938
.000942
.000946
.000949
.000953
.000957
.000961
.000965
.000968
.000972

.000576

.000327

.000579
.000583
.000587
.000591
.000595
.000598
.00'0602
.000606
.000610
.000614
.000617
.000621
.000625
.000629
.000633
.000637
.000640
.000644
.000648
.000652
.000656
.000659
.000663
.000667
.0006'71
.000675
.000679
.000682
.000686
.000690
.000694
.000698
.000701
• Q00705
.000709
.000713
.000717
.000720
.000724
.000728

.000330
.000331
.000332
.000333
.000334
.000335
.000336
.000337
.000340
.000341
.000342
.000343
.000344
.000345
.000346
.000347
.000350
.000351
.000352
.000353
.000354
.000355
.000356
.000357
.000360
.000361
.000362
.000363
.000364
.000365
.000366
.000367
.000370
.000371
.000372
.000373
.000374
.000375
.000376
.000377

Octal-Decimal Fraction Conversion

103

Octal-Decimal Fraction Conversion Table (Continued)
OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC.

OCTAL

DEC,

,000400
,000401
.000402
.000403
.000404
.000405
.000406
.000407
.000410
.000411
,000412
,000413
.000414
,000415
.000416
,000417
.000420
,000421
,000422
.000423
.000424
.000425
.000426
,000427
.000430
,000431
.000432
.000433
.000434
.000435
.000436
.000437
,000440
.000441
,000442
,000443
,000444
.000445
.000446
.000447
.000450
.000451
.000452
,000453
.000454
.000455
.000456
,000457
.000460
,000461
,000462
,000463
.000464
,000465
.000466
,000467
,0004'10
,000471
,000472
.000473
,000474
.000475
,000476
,000477

,000976
.000980
.000984
,000988
.000991
.000995
.000999
.001003
.001007
.001010
.001014
.001018
.001022
.001026
,001029
.001033
,001037
.001041
.001045
,001049
.001052
.001056
,001060
.001064
.001068
,001071
.001075
,001079
.001083
.001087
.001091
,001094
,001098
,001102
.001106
,001110
,001113
,001117
.001121
.001125
,001129
.001132
.001136
.001140
.001144
.001148
.001152
.001155
,001159
,001163
.001167
...001171
.001174
.001178
,001182
,001186
,001190
.001194
,001197
.001201
,001205
.001209
.001213
.001216

,000500
.000501
.000502
.000503
.000504
.000505
.000506
,000507
.000510
.000511
.000512
.000513
,000514
.000515
.000516
,000517
,000520
.000521
.000522
.000523
.000524
.000525
.000526
.000527
.000530
.000531
.000532
.000533
.000534
.000535
,000536
.000537
,000540
.000541
.000542
,000543
.000544
,000545
,000546
,000547
.000550
,000551
.000552
,000553
.000554
.000555
.000556
.000557
,000560
.000561
,000562
.000563
,000564
.000565
.000566
,000567
,000570
.000571
.000572
.000573
.000574
.000575
,000576
.000577

,001220
.001224
.001228
.001232
.001235
.001239
,001243
.001247
.001251
.001255
.001258
,001262
.001266
.001270
.001274
.001277
.001281
.001285
.001289
.001293
.001296
.001300
,001304
.001308
.001312
.001316
.001319
.001323
.001327
.001331
.001335
.001338
.001342
,001346
.001350
.001354
.001358
,001361
.001365
.001369
,001373
.001377
.001380
.001384
.001388
.001392
.001396
.001399
,001403
.001407
,001411
.001415
.001419
,001422
.001426
.001430
.001434
,001438
,001441
.001445
.001449
.001453
.001457
,001461

,000600
.000601
.000602
.000603
.000604
.000605
.000606
.000607
,000610
,000611
.000612
.000613
.000614
,000615
.000616
.000617
,000620
,000621
.000622
.000623
.000624
.000625
.000626
.000627
.000630
.000631
.000632
.000633
.000634
,000635
.000636
,000637
.000640
,000641
.000642
.000643
.000644
.000645
,000646
,000647
.000650
,800651
,000652
,000653
,000654
.000655
.001)656
,000657
,000660
,000661
,000662
.000663
,000664
,000665
.000666
,000667
.000670
,000671
,000672
,000673
.000674
,000675
,000676
.000677

.001464
.001468
.001472
.001476
.001480
.001483
.001487
.001491
,001495
.001499
.001502
.001506
.001510
.001514
.001518
.001522
.001525
.001529
.001533
.001537
,001541
.001544
.001548
.001552
.001556
,001560
.001564
.001567
.001571
.001575
.001579
.001583
.001586
.001590
.001594
,001598
.001602
,001605
,001609
,001613
,001617
.001621
.001625
.001628
.001632
,001636
.001640
,001644
,001647
,001651
.001655
,001659
,001663
.001667
,001670
.001674
,001678
,001682
,001686
.001689
.001693
,001697

.000700
.000701
.000702
.000703
.000704
.000705
.000706
.000707
.000710
.000711
.000712
.000713
.000714
.000715
.000716
.000717
.000720
,000721
.000722
.000723
.000724
.000725
.000726
.000727
.000730
.000731
.000732
.000733
,000734
,000735
,000736
.000737
.000740
.000741
,000742
,000743
,000744
.000745
.000746
.000747
,000750
,000751
,000752
.000753
.000754
.000755
,000756
,000757
.000760
.000761
.000762
,000763
,000764:
,000765
,000766
.000767
,000770
,00.0771
.000772
.000773
.000774
.000775
.000776
.000777

,001708
.001712
.001716
.001720
,001724
.001728
.001731
.001735
.001739
.001743
.001747
,001750
,001754
.001758
.001762
.001766
,001770
.001773
,001777
,001781
.001785
.001789
.001792
.001796
.001800
.001804
.001808
.001811
,001815
.001819
.001823
.001827
.001831
.001834
,001838
,001842
,001846
.001850
,001853
.001857
,001861
.001865
.001869
.001873
.001876
.001880
,001884
.001888
,001892
,001895
,001899
.001903
.001907
,001911
.001914,001918
,001922
,001926
.001930
:001934
.001937
,001941
,001945
.001949

104

-

,OOI7.Dl

,001705

Appendix C: Table of Powers of Two

2- 11

2"

1t

1
2
4
8

0
1
2
3

1.0
0,5
0,25
0,125

16
32
64
128

4
5
6
7

0,062
0,031
0,015
0,007

5
25
625
812 5

256
512
1 024
2 048

8
9
10
11

0,003
0,001
0,000
0,000

906
953
976
488

4 096
8 192
16 384
32 768

12
13
14
15

0.000
0.000
0,000
0,000

244 140
122' 070
061 035
030 517

625
312 5
156 25
578 125

25
125
562 5
281 25

65
131
262
524

536
072
144
288

16
17
18
19

0.000
0,000
0,000
0.000

015
007
003
001

258
629
814
907

789
394
69'7
348

062
531
265
632

5
25
625
812 5

1
2
4
8

048
097
194
388

576
152
304
608

20
21
22
23

0.000
0,000
0,000
0.000

000
000
000
000

953
476
238
119

674
8'37
418
209

316
158
579
289

406
203
101
550

25
125
562 5
781 25

16
33
67
134

777
554
108
217

216
432
864
728

24
25
26
27

0.000
0.000
0.000
0.000

000
000
000
000

059
029
014
00-7

604
802
901
450

644
322
161
580

775
387
193
596

390
695
847
923

625
312 5
656 25
828 125

268435
536 870
1 073 741
2 147 483

456
912
824
648

28
29
30
31

0.000
0.000
0.000
0.000

000
000
000
000

003
001
000
000

725
862
931
465

290
645
322
661

298
149
574
287

461
230
615
307

914
957
478
739

062
031
515
257

5
25
625
812 5

4
8
17
34

294
589
179
359

967
934
869
738

296
592
184
368

32
33
34
35

0.000
0.000
0.000
0.000

000
000
000
000

000
000
000
000

232
116
058
029

830
415
207
103

643
321
660
830

653
826
913
456

869
934
467
733

628
814
407
703

906
453
226
613

25
125
562 5
281 25

68
137
274
549

719
438
877
755

476
953
906
813

736
472
944
888

36
37
38
39

0.000
0.000
0.000
0.000

000
000
000
000

000
000
000
000

014
007
003
001

551
275
637
818

915
957
978
989

228
614
807
403

366
183
091
545

851
425
712
856

806
903
951
475

640
320
660
830

625
312 5
156 25
078 125

Powers of Two

105

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