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2241092-0001_Business-Pro_Professional_Computer_Hardware_Technical_Reference_Apr86 2241092-0001_Business-Pro_Professional_Computer_Hardware_Technical_Reference_Apr86
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HARDWARE TECHNICAL REFERENCE •
BUSINESS·PRO™
Professional
Computer
2241092-0001
April 1986
TEXAS INSTRUMENTS
© 1986, Texas Instruments Incorporated. AJI Rights Reserved.
No part of this pubJlcation may be reproduced, stored In a retrieval system, or transmitted,
In any form .or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of Texas Instruments Incorporated.
MANUAL REVISION HISTORY
BUSINESS-PRO™ Professional Computer Hardware Technical Reference
(2241092-0001 )
Original Issue ..................................... April 1986
The total number of pages in this publication is 532.
The computers offered in this agreement, as well as the programs that TI has created to
use with them, are tools that can help people better manage the ·lnformaUon used in their
business; but tools-Including TI computers-cannot replace sound judgment nor make the
manager's business decisions.
Consequently, TI cannot warrant that Its systems are suitable for any specIfic customer
application. The manager must rely on personal judgment of what is best for his or her
business.
BUSINESS-PRO Hardware Reference
Cont.ents
Contents
Paragraph
Title
Page
Preface
xiii
1 -- Introduction
1.1
1.1.1
1.1. 2
1.1. 3
1.2
1. 2.1
1.2.1.1
1.2.1.2
1.2.1.3
1.2.1.4
1.2.1.5
1. 2.2
1. 2.3
1. 2.4
1. 2.5
1. 2.6
1.3
1. 3.1
1. 3.2
1.3.'3
1.3.3.1
1.3.3.2
1.3.3.3
1.3.3.4
1.4
General
. . . . . .
Workstation Applications
Local Area Networks
Multiuser Environments
BUSINESS-PRO Hardware
System Unit . . . . . . .
Central Processing Unit
System Memory
. . .
Serial and Parallel Ports
Mass Storage System
Expansion Slots
Keyboard . . .
Display Units
Optical Mouse
Communications . . .
Graphics . . .
BUSINESS-PRO Computer Standard Configurations
Single-Drive Floppy System
Winchester System
System Unit Enclosure
Main Logic Board . .
Bus Interface Board
System Power Supply
Mass Storage Device Mounting .
BUSINESS-PRO Specifications . . .
1-1
1-2
1-2
1-2
1-2
1-2
1-2
1-3
· 1-3
1-3
1-3
1-3
1-4
1-4
1-4
1-4
1-5
1-5
1-5
1-5
1-6
1-6
· 1-6
· 1-6
1-7
2 -- Main Logic Board
2.1
General . . . . . . . . . . .
2.2
System Central Processing Unit
2.2.1
Microprocessor Unit • . . . . . .
2.2.2
Optional Numeric Coprocessor
2.2.3
CPU Bus Buffering . . . . . .
2.2.3.1
Address and Control Bus Buffering
2.2.3.2
Data Bus Buffering
. . . .
2.2.4
CPU Clock Generation and Bus Control .
2.2.5
Reset Circuit
. . . . . . . .
2.2.5.1
Software Reset and Shutdown Cycles
2.2.5.2
System Reset . . . .
2.2.6
Control Signals.
. ...... .
2241092-0001
iii
2-1
· 2-8
2-8
2-8
2-8
2-8
2-9
2-11
2-11
2-11
2-12
2-12
BUSINESS-PRO Hardware Reference
Contents
Paragraph
2.3
2.3.1
2.3.2
,2.3.3
2.3.4
2.3.5
2.4
2.4.1
2.4.2
2.5
2.5.1
2.5.1.1
2.5.1.2
2.5.1.3
2.5.1.4
2.6
2.6.1
2.6.2
2.6.2.1
2.6.2.2
2.6.2.3
2.6.3
2.6.3.1
2.6.3.2
2.6.3.3
2.6.3.4
2.6.4
2.6.5
2.6.5.1
2.6.5.2
2.6.5.3
2.6.5.4
2.6.5.5
2.6.5.6
2.6.6
2.6.6.1
2.6.6.2
2.6.6.3
2.6.7
2.6.7.1
2.6.7.2
2.7
Page
Title
Wait-State Control Logic . . . . .
Zero-Wait-State Memory Cycles
.. .
. ..
One-Wait-State Memory Cycles.
.. .
. .
One-Wait-State I/O Cycles . . . . . .
Four-Wait-State Cycles .
. . . .
.
Ten-Wait-State Cycles . . .
.....
System Memory
Main Memory . . . .
System ROMs . . .
...
Memory Control Logic
. . .
. . .
DMA Controller and Memory Page Register . . .
DMA/Refresh Arbiter and Refresh Controller .
Memory Decode Logic . . . . . .
Memory Cycle Generation Logic
Parity Error Logic . . . . . . . . . . .
I/O Subsystem . . . . . . . . . . .
I/O Decode Logic ~ . . . . . . .
Real-Time Clock (RTC) and Nonvolatile RAM.
Battery Circuit
...
.. .
Nonvolatile RAM
. ..
.. .
Real-Time Clock . . .
Keyboard Interface
. . . .
Receiving Data From the Keyboard .
Sending Data to the Keyboard .
. . . .
Keyboard Commands
. . . . . . . . . . .
Keyboard Interface I/O Ports
Parallel Printer Port . . .
Serial Port . . . . . .
Clear-to-Send Signal . .
Data-Set Ready Signal
Data-Carrier Detect Signal .
. . . . .,
Ring Indicator Signal
Data Terminal Ready Signal
Request-to-Send Signal .
Timing Services . . . .
TI Compatible Timer . . .
PC-AT Compatible Timer
Speaker Amplifier . . . . . . . . . . . .
Interrupt System . . . .
Interrupt Levels 0 Through 15 . . .
.
Nonmaskable Interrupt . . . . . . . . . . .
Expansion Bus Interface . . . . . .
...
.
.
.
·
.
·
·
·
·
.
.
·
.
.
·
.
.
2-12
2-13
2-14
2-15
2-15
2-16
2-18
2-18
2-19
2-20
2-20
2-21
2-22
2-22
2-23
2-23
2-24
2-24
2-24
2-24
2-25
2-34
2-35
2-35
2-36
2-38
2-39
2-42
2-44
2-44
2-44
2-45
2-45
2-45
2-45
2-45
2-46
2-46
2-47
2-48
2-49
2-49
3 -- Power Supply
3.1
3.2
Power Supply Output Voltages .
BUSINESS-PRO Power Consumption
iv
· 3-1
3-1
2241092-0001
BUSINESS-PRO Hardware Reference
Paragraph
Contents
Page
Title
4 -- Keyboard
4.1
4.1.1
4.1. 2
4.1. 3
4.1. 4
4.1. 5
4.2
4.2.1
4.2.1.1
4.2.1.2
4.2.2
4.3
4.3.1
4.3.2
4.4
4.4.1
4.4.1.1
4.4.1.2
4.4.1.3
4.4.2
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
4.5.8
4.5.9
4.5.10
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.6.7
4.7
General
. ..
....
Typamatic Transmission
N-Key Rollover . .
Key Click . . .
Mode Indicators
Keyboard Buffer
Keyboard Operations
Keyboard Self-Tests
Basic Assurance Self-Test
Periodic Self-Test . . . .
Power-Up Sequence . . . . .
Keyboard Connector Specifications
Clock Line . . . . . . . . .
Data Line . . . . . . . . .
Hardware Handshaking Protocols
Keyboard Transmission . . .
Transmission Process . . . .
Aborted Keyboard Transmission
Inhibited Keyboard Transmission
System Unit Transmission . . . . .
System-to-Keyboard Commands
. . . . .
Set Key Click Volume Command . . .
Turn Mode Indicator LEDs On/Off Command
Echo Command . . . . . . . . . . . .
No Operation Command . . . . . . . .
Set Typamatic Rate and Delay Command
Enable Command . . . . .
...
Default Disable Command
Set Default Command
Resend Command . . . . .
Reset Command
......... .
Keyboard-to-System Commands
Overrun Command . . . . . .
Self-Test OK Command . . .
Echo Response Command
Break Code Prefix Command . . .
Acknowledge Command . . . .
Diagnostic Failure Command
Resend Command . . . .
Keyboard Configurations
·
·
.' .
. . .
·
·
. .
4-1
4-1
4-2
4-2
4-2
4-2
4-3
4-3
4-3
4-3
4-3
4-4
4-5
4-5
4-6
4-6
4-8
4-9
4-10
4-10
4-12
4-13
4-14
4-15
4-15
4-16
4-17
4-17
4-18
4-18
4-18
4-18
4-19
4-19
4-19
4-19
4-19
4-19
4-19
4-19
5 -- Floppy Disk Drive Controller
5.1
General
. . . . . . . . . . . .
5.1.1
Floppy Disk Controller . . . .
5.1.1.1
Floppy Disk Drive Interface
2241092-0001
v
5-1
5-1
5-2
BUSINESS-PRO Hardware Reference
Contents
Paragraph
5.1.1.2
5.1. 2
5.1.2.1
5.1.2.2
5.1.2.3
Page
Title
Host I/O Interface and Control Logic . . . .
Floppy Disk Controller Programming Information
Floppy Disk Controller IC Internal Registers
Controller Commands
Status Registers .
5-9
5-15
5-15
5-19
5-28
6 -- Hardware Options
General
6.1
RAM Expansion.
6.2
.
6.2.1
128-Kilobyte RAM Expansion Kit
6.2.1.1
128-Kilobyte RAM Expansion Kit Interface Signals
6.2.1.2
128-Kilobyte RAM Expansion Kit Specifications
6.2.2
512-Kilobyte RAM Expansion Kit . . . . . . . . . .
512-Kilobyte RAM Expansion Kit Interface Signals
6.2.2.1
6.2.2.2
512-Kilobyte RAM Expansion Kit Specifications
6.3
BUSINESS-PRO Mass Storage Options . . .
6.3.1
1.2-Megabyte Floppy Disk Drive.
6.3.1.1
1.2-Megabyte Floppy Disk Drive Features
1.2-Megabyte Floppy Disk Drive Ki t . . .
6.3.1.2
6.3.1.3
1.2-Megabyte Floppy Disk Drive Tabulated
Information
. . . . . . .
360-Kilobyte Floppy Disk Drive .
6.3.2
6.3.2.1
360-Kilobyte Floppy Disk Drive Kit
6.3.2.2
360-Kilobyte Floppy Disk Drive Tabulated
Information . . . . . . .
6.3.3
Winchester Disk Controller .
6.3.3.1
Winchester Disk Controller Kit
6.3.3.2
Winchester Disk Controller Diagrams
6.3.3.3
Winchester Disk Controller Tabulated Information
.
6.3.3.4
External Activity Indicator . . .
6.3.4
Winchester Disk Controller System Addresses
6.3.4.1
I/O Port Descriptions . . .
6.3.4.2
Controller Command Functions . .
6.3.5
Winchester Disk Drives . . . . . .
6.3.5.1
Types of Winchester Disk Drives
6.3.6
21-Megabyte Winchester Disk Drive
6.3.6.1
21-Megabyte Winchester Drive Kit
6.3.6.2
21-Megabyte Disk Drive Tabulated Information
6.3.6.3
Configuring a 21-Megabyte Disk Drive . .
6.3.7
40-Megabyte Winchester Disk Drive . . . . . .
6.3.7.1
40-Megabyte Winchester Disk Drive Kit
. . .
6.3.7.2
40-Megabyte Disk Drive Tabulated Information
6.3.7.3
Configuring a 40-Megabyte Disk Drive .
6.3.8
72-Megabyte Winchester Disk Drive
. . .
6.3.8.1
72-Megabyte Winchester Disk Drive Kit
. . .
6.3.8.2
72-Megabyte Disk Drive Tabulated Information
6.3.8.3
Configuring a 72-Megabyte Disk Drive
6.3.9
120-Megabyte Winchester Disk Drive .
vi
6-1
6-3
6-3
6-3
6-3
6- 5
6-5
6-7
6-9
6-9
6-10
6-10
6-10
6-15
6-15
6-16
6-19
6-19
6-19
6-24
6-32
6-32
6-32
6-39
6-43
6-43
6-45
6-45
6-45
6-50
6-53
6-53
6-53
6-58
6-62
6-62
6-62
6-67
6-69
2241092-0001
BUSINESS-PRO Hardware Reference
Paragraph
Contents
Page
Title
6.3.9.1
120-Megabyte Winchester Disk Drive Kit . . . . .
6.3.9.2
120-Megabyte Disk Drive Tabulated Information
6.3.9.3
Configuring a 120-Megabyte Disk Drive
..
6.3.10
Tape System
. ..
.......
6.3.10.1
Tape Drive Kit.
. . . . . . . .
. .
6.3.10.2
Tape Drive. . . . . . . . .
.....
.
6.4
Video Options . . .
...
. . . . .
6.4.1
Video Controllers
. . .
. . . ..
6.4.1.1
TI Mode CRT Controller
. . ..
..
6.4.1.2
TI Mode CRT Controller Board.
...
...
6.4.1.3
Diagnostic Loopback . . . .
...
6.4.1.4
Graphics Controller Board
. . .
6.4.1.5
TIPC Compatibility. . . . .
.
6.4.1.6
PC-AT Mode CRT Controller
. . . ..
..
6.4.1.7
PC-AT CRT Controller Operational Modes.
6.4.1.8
CRT Timing Parameters . . .
....
6.4.2
Color Display Unit. . . . . .
...
.
6.4.2.1
Color Display Unit Kit. . .
.......
6.4.2.2
Color Display Unit Tabulated Information
.
6.4.2.3
Displayed Colors. . . . . . . . . .
6.4.2.4
Keyboard/Mouse Cable Connector J4
. ..
.
6.4.3
Monochrome Display Unit . . . . . .
. ..
6.4.3.1
Monochrome Display Unit Kit . . .
..
. ..
6.4.3.2
Monochrome Display Unit Tabulated Information
6.4.3.3
Displayed Intensities . . . .
......
6.4.3.4
Keyboard/Mouse Cable Connector J4
. ..
.
6.5
TI Mode RS-232 Serial Interface . . . . . . . .
.
6.5.1
TI Mode RS-232 Serial Interface Kit . . . . .
6.5.2
TI Mode RS-232 Serial Interface Tabulated
Information . . . .
...... .
. .
6.5.3
Baud Rate Generation.
........ .
6.6
Optical Mouse . . . . .
. . . . . . . . . ·
6.6.1
Optical Mouse Kit
. . . . . . . .
6.6.2
Optical Mouse Tabulated Information . . . . .
·
6.7
80287 Numeric Coprocessor . . . . . . . . . .
·
6-69
6-70
6-75
6-79
6-79
6-79
6-95
6-95
6-95
6-102
6-109
6-109
6-116
6-117
6-124
6-132
6-135
6-135
6-135
6-137
6-140
6-143
6-143
6-143
6-145
6-148
6-151
6-151
6-151
6-154
6-155
6-155
6-155
6-157
Appendixes
Appendix
A
B
C
D
E
F
G
Title
System Memory and I/O Maps
TI Mode I/O Maps . . . . . .
PC-AT Mode I/O Maps . . .
PAL Programming Information
Logic Diagrams . . . . . . .
Option Board Outline . . . .
Switch and Jumper Settings .
Index
2241092-0001
vii
Page
A-l
· B-1
C-l
. . . D-l
. . . E-l
· F-l
G-l
Contents
BUSINESS-PRO Hardware Reference
Illustrations
Figure
2-1
2-2
Page
Title
2-4
2-5
2-6
2-7
2-8
Main Logic Board Block Diagram . . . . . .
.
Main Logic Board, TI Part No. 2240843-0001, Key
Components . . . . . . .
...... .
Main Logic Board, TI Part No. 2535670-0001, Key
Componen ts . . . . . . .
......... .
Required Input Timing for a Processor-Driven Cycle
One-Wait-State MPU-Driven Memory Cycles . . . .
One-Wait-State MPU-Driven I/O Cycles . . . . .
Four-Wait-State MPU-Driven Memory or I/O Cycle · .
Ten~Wait-State MPU-Driven Memory or I/O Cycle
· .
3-1
3-2
3-3
3-4
Main Logic Board Power Connector . . .
Expansion Bus Board Power Connector . . .
Disk Drives 1 Through 4 Power Connector .
Disk Drives 5 and 6 Power Connector
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
Keyboard Connector Pin Arrangement . . .
Keyboard Data Frame Format
. .
Key Station/Code Map . . . . . . . . . . . . . · . .
Keyboard Transmission Timing -- Completed
Transmission . . . . . . . . . . . . .
Keyboard Transmission Timing -- Aborted Transmission
System Unit Transmission Timing . . . . . . . . . . .
Set Key Click Volume Command Data Byte . . . . . .
Second Byte of the Indicator LED Command
Second Byte of the Set Typamatic Rate Command
Keycap Configuration
Domestic
. . .
Keycap Configuration
Germany
.....
Keycap Configuration
France
Keycap Configuration
Italy
. . .
. . .
Keycap Configuration
Norway......
Keycap Configuration
Spain.
. . .
Keycap Configuration
Sweden
. . . . .
Keycap Configuration
Switzerland
. . . . . .
Keycap Configuration
United Kingdom . . .
5-1
5-2
Functional Block Diagram of Floppy Disk Controller . 5-3
Simplified Block Diagram of Disk Drive Interfaces . . 5-4
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
Winchester Controller Functional Block Diagram
..
Controller Connected in a Two-Drive Configuration.
Controller Connected in a Two-Drive XENIX System . .
Controller Connected in a Three-Drive Configuration
Error Register Bit Definitions . . . . . .
.
Size/Drive/Head Register Bit Definitions . . .
Status Register Bit Definitions .
. . ..
Fixed Disk Control Register . . . . . . .
. .
2-3
viii
. 2-3
2-6
·
·
·
.
.
2-7
2-13
2-14
2-15
2-16
2-17
· . . 3-3
· 3-4
3-5
3-6
4-4
4-6
4-7
4-9
4-10
4-12
4-14
4-15
4-16
4-20
4-20
4-21
4-21
4-22
4-22
4-23
4-23
4-24
6-20
6-21
6-22
6-23
6-33
6-35
6-36
6-39
2241092-0001
BUSINESS-PRO Hardware Reference
Figure
6-9
6-10
6-11
6-12
Contents
Title
Page
Diagnostic Register Bit Definitions . . . . . . . . .
21-Megabyte Disk Drive Select Switches and Terminator
40- and 72-Megabyte Disk Drive Select Switches
and Terminator
.........
......
120-Megabyte Disk Drive Select Pins and Terminator
6-39
6-50
6-59
6-75
Tables
Table
Title
Page
1-1
BUSINESS-PRO System Specifications
2-1
2-2
2-3
2-4
2-5
2-6
2-9
2-10
2-19
2-25
2-41
2-7
2-8
2-9
Address and Control Bus Buffering . . . . . .
..
Buffer States of the Data Bus . . . . . . . . . . . .
RAM Expansion Signal Pin Assignments . . . . . . . .
Real-Time Clock's Internal RAM Addresses . . . . . .
Parallel Printer Port Pin Assignments . . . . . . . .
RS-232 Serial Interface Divisors Using 1.8432 MHZ
Crystal . . . . . . . . . . .
...
. . . .
Serial Port Pin Assignments . . . . . . . . . . . . .
BUSINESS-PRO Interrupt Levels . .
. . ..
Expansion Bus Pin Assignments.
..........
3-1
3-2
3-3
3-4
3-5
3-6
Power Supply Nominal Output Voltages
. . . . . .
Power Configuration Table . . . . . .
......
Main Logic Board Power Connector Pinouts . . . . . .
Expansion Bus Board Power Connector Pinouts .
Disk Drives 1 Through 4 Power Connector Pinouts . .
Disk Drives 5 and 6 Power Connector Pinouts . . . . .
3-1
3-2
3-3
3-4
3-5
3-6
4-1
4-2
4-3
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
Initial Keyboard Default Conditions .
....
Keyboard Connector Pin Assignments . . . . . . . .
Typamatic Rates . . . . . . . . . . . . . . . . . . .
Internal Floppy Disk Controller Connectors J3 .
Internal Floppy Disk Controller Connectors J4
External Interface for Floppy Disk Controller J5 . .
Floppy Disk Controller I/O Port Address Map
. .
3F2 Digital Output Register Bits . . .
......
3F4H Main Status Register . . . . . .
. . . .
3F7H Floppy Disk Diagnostic Register
...
3F7H Floppy Disk Register . . .
...
Definition of Symbols . . . . . . . . . . . . . .
.
4-4
4-5
4-17
5-6
5-7
5-8
5-15
5-16
5-17
5-17
5-18
5-26
6-1
6-2
6-3
6-4
6-5
128-Kilobyte
512-Kilobyte
1.2-Megabyte
1.2-Megabyte
1.2-Megabyte
6-4
6-5
6-11
6-13
6-13
. . 1-7
RAM Interface Signals
. . .
·
RAM Expansion Kit Interface Signals
Floppy Drive Interface Connector PI
Floppy Disk Drive Power Connector P2 . ·
Floppy Disk Drive Jumper Settings
·
ix
2-43
2-44
2-47
2-53
2241092-0001
BUSINESS-PRO Hardware Reference
Contents
Table
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
6-42
6-43
6-44
6-45
6-46
6-47
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Page
Title
1.2-Megabyte Floppy Disk Drive Performance
Specifications
. . . . . . . . . . . . . . .
1.2-Megabyte Floppy Disk Drive Power Requirements
360-Kilobyte Floppy Disk Drive Power Connector P2
360-Kilobyte Floppy Disk Drive Jumper Settings
360-Kilobyte Floppy Disk Drive Specifications . .
360-Kilobyte Floppy Disk Drive Power Requirements
Winchester Disk Controller Control Connector J3
Winchester Disk Controller Control Connector J4
Winchester Disk Controller Data Connector J5
Winchester Disk Controller Data Connector J6
Winchester Disk Controller Data Connector J8
Winchester Disk Controller Data Connector J9
Winchester Disk Controller Switches SWl Through SW4
Winchester Disk Controller Performance Specifications
Winchester Controller I/O Port Addresses
Diagnostic Code Definitions . . . .
Winchester Controller Commands
Controller-Supported Stepping Rates
BUSINESS-PRO Drive Types . . . . .
Comparison of Winchester Disk Drive Types
21-Megabyte Disk Drive Control Connector Jl
21-Megabyte Disk Drive Data Connector J2
21-Megabyte Disk Drive Power Connector J3 .
21-Megabyte Disk Drive Performance Specifications .
21-Megabyte Disk Drive Power Requirements .
40-Megabyte Disk Drive Control Connector J3
40-Megabyte Disk Drive Data Connector J3
40-Megabyte Disk Drive Power Connector J2 .
40-Megabyte Disk Drive Performance Specifications
40-Megabyte Disk Drive DC Power Requirements
72-Megabyte Disk Drive Control Connector J3
72-Megabyte Disk Drive Data Connector J3
72-Megabyte Disk Drive Power Connector J2 . .
72-Megabyte Disk Drive Performance Specifications
72-Megabyte Disk Drive DC Power Requirements
120-Megabyte Disk Drive Control Connector Jl
120-Megabyte Disk Drive Data Connector J2 . .
120-Megabyte Disk Drive Power Connector J3
120-Megabyte Disk Drive Performance Specifications
120-Megabyte Disk Drive DC Power Requirements
Tape Drive Interface Signals Connector Jl
Tape Position Codes . . . . . . . .
Tape Drive Power Connector J2 . . . .
Tape Drive Performance Specifications
Tape Drive Power Requirements . . . .
Tape Controller/Expansion Bus Interface Signals
Tape Controller Jumper Settings .
Tape Controller Diagnostic Indicators
Tape Controller Registers . . . . . .
x
6-14
6-15
6-16
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6-17
6-18
6-25
6-27
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2241092-0001
BUSINESS-PRO Hardware Reference
Table
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6-102
Contents
Page
Title
Tape Controller Performance Specifications . . . . .
Tape Controller Power Requirements . . . . . . . . .
TI Mode CRT Controller/Monitor Interface Connector J3
TI Mode/PC-AT Mode Controller Interface Connector J4
TI Mode CRT Controller Expansion Interface Signals .
TI Mode CRT Controller Performance Specifications.
Video AC Parameters . .
CRT System Memory Map . . . . .
...
CRTC Programming Values . . . .
Color Map . . . . . . . . . . . .
. . . .
Organization of Graphics Screen Memory Into Pixels
Color Combinations
. . . .
Bit Correlations . . . . . . . .
Color Latch Byte . . . . . . .
.
Default Values of Color Latches
TIPC vs BUSINESS-PRO Monochrome Compatibility
PC-AT Mode CRT Controller/Monitor Interface
Connector J3
. . . . . . . . . . . . . . . . . ..
Interface Connector J4
. . . . . . . . . ..
..
PC-AT Mode CRT Controller Expansion Interface Signals
Light Pen Enable Connector J5 . . .
PC-AT CRT Controller Specifications . . .
SWl Seiectable Options . . . . . . . . . . . . . .
PC-AT Controller Monochrome I/O Addresses
PC-AT CRTC Color Graphics I/O Addresses .
Bit Functions of Control Port 3D8H . . .
. . .
Valid Color/Graphics Mode 3D8H
..........
PC-AT CRT Controller Color Select Register
Bit Functions of Status Port 3DAH . . .
. . .
CRT Timing Parameters . . . . . . . . .
. . .
Color Display Unit/Controller Interface Connector J2
Color Display Unit Color Map . . . . . .
...
Color Display Unit Video AC Parameters . . .
..
Keyboard/Mouse Connector J4 . . . . . . . . .
..
Color Display Unit Performance Specifications.
..
Color Display Unit AC Power Requirements
. . . .
Monochrome Display Unit/Controller Interface
Connector J2
. . . . . . . . . . . . . . . . .
Monochrome Display Unit Intensity Levels
·
Monochrome Display Unit Video AC Parameters
·
Keyboard/Mouse Connector J4 . . . . . . . .
Monochrome Display Unit Performance Specifications ·
Monochrome Display Unit AC Power Requirements . .
TI Mode RS-232 Serial Interface Connector Jl
Port-Selection Switches SW1-1 Through SWl-4
TI Mode RS-232 Serial Interface Port Addresses
·
TI Mode RS-232 Interface Programmable Baud Rate
Val ues . . . . . . . . . . . . .
. . .
·
Optical Mouse Interface Signals . . . . . . . . .
Mouse Data Format . . . . . . . . . .
·
Optical Mouse Performance Specifications . . .
xi
6-93
6-94
6-97
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2241092-0001
BUSINESS-PRO Hardware Reference
Preface
Preface
This document provides technical information about the standard
and optional hardware devices of the Texas Instruments (TI)
BUSINESS-PRO(TM) Computer, TI Part No.
2240803-0001.
The
information in this document is intended to be used by system
designers, value added retailers (VARs), maintenance personnel,
and system users.
This manual is divided into the following six
sections and seven appendixes:
Section
1
Introduction -- Provides general information about
the BUSINESS-PRO computer, a general system overview,
and system specifications.
2
Main Logic Board -- Provides detailed information
about the operation and the capabilities of the
BUSINESS-PRO main logic board. This section
includes information about the system central
processing unit, the system memory and memory
control logic, the direct-memory access logic,
the input/output (I/O) control logic, and various
system interfaces.
3
Power Supply -- Provides tabulated information
about the BUSINESS-PRO system power supply.
4
Keyboard -- Provides descriptive information about
BUSINESS-PRO keyboard, its interface to the system,
and the commands used for communication and data
transfer between the system and the keyboard.
5
Floppy Disk Drive Controller -- Provides information about the controller and the floppy disk drive
interface.
6
Hardware Options -- Provides information about the
various optional hardware devices and subsystems
that are available for the BUSINESS-PRO computer.
2241092-0001
xiii
Preface
BUSINESS-PRO Hardware Reference
Appendixes
A
Memory and I/O Maps -- Provides a list of the system
memory addresses and their allocations, and a general
list of the system I/O address allocations.
B
TI Mode I/O Maps -- Provides categorized lists of
the TI mode I/O address allocations.
C
PC-AT Mode I/O Maps -- Provides categorized lists
of the PC-AT mode I/O address allocations.
D
PAL(R) Programming Information -- Provides tables of
the main logic board programmable array logic
(PAL) functions, based on the PAL programming
equations.
E
Logic Diagrams -- Provides system logic diagrams.
F
Option Board Outline -- Gives outline dimensions
for full- and half-size boards.
G
Switch and Jumper Settings -- Gives a summary of
the switch and jumper option settings.
PAL is a
registered
Incorporated.
trademark
xiv
of
Monolithic
Memories,
2241092-0001
Introduction
BUSINESS-PRO Hardware Reference
Section 1
Introduction
1.1
GENERAL
The Texas Instruments (TI) BUSINESS-PRO(TM) Computer, a member of
the TI Professional Computer line, can be configured for a
variety of computer applications. The BUSINESS-PRO offers most
of the features of the Texas Instruments Professional Computer
(TIPC) plus greater memory and mass storage capacity, greater
expandability, and greater speed.
The BUSINESS-PRO can be configured to be compatible with most of
the software designed for the TIPC as well as that designed for
the IBM(R) Personal Computer AT(TM)
(PC-AT).
The computer
supports a wide variety of operating systems, including MS(R)-DOS
and XENIX(R).
While using MS-DOS, the user can switch back and
forth between the TI mode and the PC-AT mode with the appropriate
hardware.
The BUSINESS-PRO computer's unique turbo operating mode increases
the speed of the computer by deleting memory wait states.
This
enhancement
allows
both 16-bit and 8-bit memory transfer
operations with minimum delay.
The BUSINESS-PRO system consists of a high-resolution, bit-mapped
display (either color or monochrome), a combined TIPC and PC-AT
keyboard, and a system unit that includes a floor stand. The
computer and its floor stand fit easily under a desk top.
A
variety of mass storage devices can be installed in the system
unit.
The system can be used as a high-performance, single-user
workstation; a local area network (LAN) server; an artificial
intelligence (AI) workstation; or as a clustered, multiuser
system running in the XENIX software environment.
BUSINESS-PRO is a trademark of Texas Instruments Incorporated.
IBM is a registered trademark and Personal Computer AT is a
trademark of International Business Machines Corporation.
MS and XENIX are registered trademarks of Microsoft Corporation.
2241092-0001
1-1
Introduction
BUSINESS-PRO Hardware Reference
1.1.1 Workstation Applications
The single-user capability is ideal for users who require a
faster computer for processing large quantities of data. Also,
it is appropriate for running memory intensive, AI-based software
that includes integrated window environments and large expert
systems.
The BUSINESS-PRO is also well-suited for users who
require access to large databases
with
natural
language
interfaces or for engineering applications.
1.1.2 Local Area Networks
The LAN server capability of the BUSINESS-PRO provides highperformance and security capabilities to work groups who require
resource sharing and teamwork among different workstations. A
LAN allows users to share databases and peripheral devices, and
to distribute their processing needs.
1.1.3 Multiuser Environments
The multiuser cabability of the BUSINESS-PRO allows multiple
users to share a single processor.
A
typical
multiuser
configuration consists of the BUSINESS-PRO system unit with TI
Model 931 or TI Model 924 Video Terminals connected to it.
The
system unit can provide the mass storage and a printer.
1.2
BUSINESS-PRO Hardware
The BUSINESS-PRO computer hardware is characterized by its highperformance capabilities and configuration flexibility.
The
following paragraphs provide an overview of the BUSINESS-PRO
hardware.
1.2.1 System Unit
The system unit houses the main logic board, the system power
supply, the mass storage devices, and various controllers and
interface boards. The main logic board contains the central
processing
unit
(CPU), direct memory access (DMA) logic,
input/output (I/O) logic, and various supporting circuits.
1.2.1.1 Central Processing Unit.
The CPU is based on the
Intel(R) 80286, 16-bit microprocessor. An optional 80287 numeric
coprocessor
can be added to the CPU to provide enhanced
operations for those applications involving a large number of
floating point mathematic operations.
Intel is a registered trademark of Intel Corporation.
1-2
2241092-0001
BUSINESS-PRO Hardware Reference
Introduction
1.2.1.2 System Memory. The main logic board contains S12K bytes
of ISO-nanosecond RAM that can be expanded to 3.64 megabytes
without using any of the systems 14 expansion slots.
The
expansion slots can be used to expand the main memory up to a
total of 14.64 megabytes.
1.2.1.3
Serial and Parallel Ports.
The main logic board
provides a parallel port and a serial port. The parallel port
can support a printer or other options requiring parallel data.
The serial port is a programmable, PC-AT compatible port that
provides asynchronous communication between the system
and
various options that require serial data transfers.
1.2.1.4
Mass Storage System. The system unit provides mounting
rails that can accommodate up to six half-height mass storage
devices.
For maximum flexibility, the user can choose a
combination of half-height and full-height peripherals (with
appropriate controller required).
The following mass storage
devices are available from Texas Instruments:
*
Half-height, 2l-megabyte Winchester disk drive
*
Full-height, 40-megabyte Winchester disk drive
*
Full-height, 72-megabyte Winchester disk drive
*
Full-height, l20-megabyte Winchester disk drive
*
Half-height, 1.2-megabyte floppy disk drive
*
Half-height, 360-ki1obyte floppy disk drive
*
Half-height, tape backup drive
1.2.1.5 Expansion Slots. The BUSINESS-PRO system unit contains
8 full-size,
and 6 half-size expansion slots. Three of these
slots are 8-bit slots that allow the installation of PC-XT
compatible options.
As an example of the degree of flexibility
the slots can provide, a system with a 3. 64-megabyte main memory,
a floppy controller, a Winchester disk controller with one or
more Winchester disk drives, a video controller, and a tape
backup system still has 10 slots available for other options.
1.2.2 Keyboard
The BUSINESS-PRO keyboard provides both TI and PC-AT operations
with a standard typewriter layout, plus some special keys and
keypads. These include dedicated function keys, cursor control
keys, and a numeric keypad. The keyboard also features tactile
typing response and a variable tilt adjustment.
The standard
configuration provides 100 keys, many of which can be relocated
using special software. Also, spaces are provided for additional
keys, which can increase the total key count to 144.
2241092-0001
1-3
Introduction
BUSINESS-PRO Hardware Reference
1.2.3 Display Units
The BUSINESS-PRO provides optional dual-resolution display units
in either a color version or a monochrome version. Both versions
support software designed for the TIPC as well as software
designed for the IBM color/graphics monitor adapter. The display
units feature tilt/swivel bases that provide two identical
connectors to accommodate a keyboard and/or an optical mouse.
The use of identical connectors permits the keyboard and the
mouse to connect to either side of the monitor base. The units
also provide an internal speaker with volume control.
1.2.4 Optical Mouse
The optical mouse and its associated pad provide fast and easy
cursor control on the display screen. The mouse features three
buttons whose functions depend upon the software. The mouse is
especially useful for graphics applications.
1.2.5 Communications
The communications hardware options include the TI mode RS-232
serial interface and the EtherLink(TM) hardware kit.
The RS-232 provides a serial port for communicating with external
devices such as modems, serial printers, and other computers.
Although the RS-232 is provided for TI mode applications,
specially designed hardware allows its use in the PC-AT mode to
provide a third or fourth communications port.
The EtherLink hardware kit provides a means of connecting the
BUSINESS-PRO to a local area network.
1.2.6 Graphics
The TI mode CRT controller provides high-resolution, bit-mapped,
three-plane graphics in eight colors with the color display unit
or in eight levels of intensity with the monochrome display. The
PC-AT mode CRT controller provides IBM CGA-compatible graphics
and IBM monochrome/printer adapter compatible text (excluding the
printer functions). Both controllers are specially-designed for
use with an 80286-based computer system. They can be installed
simultaneously to allow dual-mode operation.
EtherLink is a trademark of 3Com Corporation.
1-4
2241092-0001
Introduction
BUSINESS-PRO Hardware Reference
1.3
BUSINESS-PRO COMPUTER STANDARD CONFIGURATIONS
The BUSINESS-PRO computer system is available in two standard
hardware configurations: the single-drive floppy system and the
Winchester system.
To allow the user maximum flexibility when
configuring the system, neither of these basic configurations
contains the video controllers or the display units.
1.3.1 Single-Drive Floppy System
The single-drive floppy system includes the following components:
*
System unit with a main logic board
*
Bus interface board that provides 14 expansion slots
*
Keyboard
*
1.2-megabyte floppy disk drive and controller
*
Keylock
1.3.2 Winchester System
The Winchester system includes the following components:
*
System unit with a main logic board
*
Bus interface board that provides 14 expansion slots
*
*
Keyboard
*
21-megabyte,
controller
*
Keylock
1.2-megabyte floppy disk drive and controller
half-height
Winchester
disk
drive
and
1.3.3 System Unit Enclosure
The system unit enclosure is 19.8 centimeters (7.75 inches) wide
47.7 centimeters (18.8 inches) high, and 47.0 centimeters (18.5
inches) deep. The system enclosure houses the bus interface
board, the main logic board, and a system power supply with an
integral ventilation fan. An optional RAM expansion board can be
attached to an edge connector on the main logic board to provide
up to 3 megabytes of additional RAM without using an expansion
slot. Appendix E contains the system interconnect diagram.
2241092-0001
1-5
Introduction
BUSINESS-PRO Hardware Reference
1.3.3.1 Main Logic Board.
The main logic board contains the
CPU,
the memory-control logic,
and I/O control devices.
The
board provides connectors for the 25-pin parallel printer port,
the 25-pin asynchronous serial port, and an 8-conductor keyboard
cable.
It also provides a 100-pin interface connector to the bus
interface board.
1.3.3.2 Bus Interface Board.
The bus interface board provides
the system bus connections between the main logic board and the
option boards.
The board provides eight full-size and six halfsize option slots.
Each option board contains a bulkhead
mounting plate to secure the board in the chassis and to provide
a mount for any required external-access connectors.
The bus
interface board mounts above the main logic board.
A small
interface board connects the two boards togeth~r.
1.3.3.3
System Power Supply.
The system power supply is selfcontained within a box, which mounts inside the system enclosure.
The power supply contains a dc fan that obtains its operating
voltage from the 12-volt secondary of the power transformer.
The
power supply provides 225 watts ouput power to operate a fully
configured system.
The power switch is located on the front panel of the computer.
A cable connects the switch to the rear of the power supply.
The
switch also controls power to a switched power-access connector
to which a display unit can be connected.
This arrangement
allows the user to control power to both the system unit and the
display unit with a single switch.
1.3.3.4 Mass Storage Device Mounting.
The system enclosure
accepts mounting slides for the mass storage devices.
The slides
allow the devices to be installed or removed from the front of
the system unit. A typical configuration includes one or two
1.2-megabyte
floppy disk drives and one or two full-size
Winchester disk drives. A wiring harness from the system power
supply provides power for the devices.
A 34-pin ribbon cable connects between the floppy disk controller
and the floppy drive compartment; it handles data and control
signal transfers between the controller and the first two floppy
drives.
The Winchester disk drives also use a 34-pin ribbon
cable for control of multiple drives,
however,
each drive
requires a separate data interface to the controller.
NOTE
The
addresses
in
this
manual are in
hexadecimal notation,
as stated in column
headings and by a trailing H after the
hexadecimal number.
1-6
2241092-0001
BUSINESS-PRO Hardware Reference
1.4
Introduction
BUSINESS-PRO SPECIFICATIONS
Table 1-1 lists the environmental, electrical, and
specifications for the BUSINESS-PRO computer system.
Table 1-1
physical
BUSINESS-PRO System Specifications
Characteristic
Specification
Environmental requirements:
Temperature:
Operating
+10 to +35 degrees C (+50 to +95
degrees F) with a temperature
gradient of less than 10 degrees
C (50 degrees F) per hour
Nonoperating
-40 to +65 degrees C (-40 to +149
degrees F)
Relative humidity (noncondensing):
Operating
15 to 80 percent
Nonoperating
5 to 95 percent
Altitude
-300 to 12 000 meters (-984.24 to
39 369.50 feet)
Power Requirements:
Voltage:
Domestic
90 to 140 volts ac
International
180 to 264 volts ac
Frequency:
Domestic
57 to 63 Hertz
International
47 to 53 Hertz
2241092-0001
1-7
Introduction
Table 1-1
BUSINESS-PRO Hardware Reference
BUSINESS-PRO System Specifications (Continued)
Specification
Characteristic
Physical dimensions:
System Unit:
width
19.8 em (7.8 in)
Depth
47.0 em (18.5 in)
Height
47.2 em (18.6 in)
Weight
26.1 kg (58.0 Ibs)
Color monitor:
Width
38.1 em (15.0 in)
Depth
38.9 em (15.3 in)
Height
41. 9 em (16.5 in)
Weight
11. 7 kg (26.0 Ibs)
Monochrome monitor:
Width
33.8 em (13.3 in)
Depth
32.3 em (12.7 in)
Height
36.6 em (14.4 in)
Weight
6.8 kg (15.0 Ibs)
Keyboard:
Width
54.1 em (21. 3 in)
Depth
19.3 em (7.6 in)
Height
4.5 em (1. 8 in)
Weight
2.1 kg (4.8 Ibs)
------------------------------------------------------ -------~---
1-8
2241092-0001
BUSINESS-PRO Hardware Reference
Main Logic Board
Section 2
Main Logic Board
2.1
GENERAL
Figure 2-1 shows a block diagram of the BUSINESS-PRO computer's
main logic board.
This board contains the system's central
processing unit (CPU) and its supporting logic, the system memory
and memory control logic, direct-memory access (DMA) logic, and
various other devices and circuits that generate and control
system operations.
Appendix E contains the main logic board's logic diagrams and
index to its various circuits.
2241092-0001
2-1
an
BUSINESS-PRO Hardware Reference
Main Logic Board
VERTICAL BOARD
CONNECTOR
(:::::::::::::::::1
CMA0
_I
.----Jlo,I _
ADDRESS PATH
~
DATA PATH
c:J
CONTROL PATH
mR
EXPANSION CARD ADDRESS BUS
t1
BUFFER
l"'-i?J"~_Lg_)~_I~-} ;.,~_ . ,. 1 '~"r- - - .~B:U:F:F:ER;-f·':~b.·~.·~.·~ .~· :.·; !~ :.]·:~·:~ ·tr~:·2:· :; :·~:i~ (~:·d.r;T~R A~: S~C:EI ~
...
:V:ERJ••
NMI,INTR
r-
,I
l
"'" '""''''
& CONTROL BUS
DRAM
CONTROL
LOGIC
.......
r =t'r-I~"~"~-~-:-:T-B:":"':"D" :~
3 M BYTE
CARD
CONNECTOR
80286
--
CPU
I
r-
-
-
I
L--
r--
L--
'---
REFRESH
CONTROL
80287
SOCKET
&
CONTROL
LOGIC
~
+
,~
TRANCEIVERS
RAM PARITY
LOGIC
HIGH DATA BUS
L
TRANSCEIVER
' - - _......1
82288
BUS
CONTROLLER
f-
'--
-,
I
BUFFER
&MISC.
LOGIC
CLOCK
&
CYCLE
LENGTH
CONTROL
~
...
...
TRANSCEIVER
TRANSCEIVER
I ~
LOW DATA BUS
ls~;ssss~~ss~SSSSS~SSS~~:;;SSSS~~SS~~;ss~~~sssrl:;;ss~~:;;ssSSSS:~SSSS~SSSSSS:SSSS~:;;SSSS~:;;SSSSSS:;;SS~SS~:;;SSst
~
& LATCH
EXPANSION CARD CONTROL BUS
1
1/0 DECODE LOGIC
SYSTEM CONTROL BUS
MISC. 1/0
CONTROL
PORTS
I
.~.~
".
i
11 J:i
l
BUFFERS
G
~;
t~
::
::
(:1
TRANSCEIVERS
t2I
J~
TRANSCEIVER
I DATA BUS
SPf AKER INPUT
h.E'yfH'~RD
INHIBIT
INCOMING INTERRUPTS
\
2287406
2241092-0001
Figure 2-1
Main Logic Board Block Diagram
2-3
BUSINESS-PRO Hardware Reference
Main Logic Board
Figures 2-2 and 2-3 show the locations of the connectors,
jumpers, switches, and the coprocessor on the two versions of the
main logic board. The two boards, TI Part No.
2240843-0001 and
2535670-0001, can be distinguished by the presence or absence of
the coprocessor option jumpers. The original board, TI Part No.
2240843-0001 does not have these jumpers; the later version does.
The following is a list of the reference designators and their
functions:
*
*
*
J2
Expansion bus connector.
J3
Expansion RAM interface connector.
*
*
*
J8
Serial port interface connector.
J9
Parallel port connector.
J4 and J5 -- Coprocessor option jumpers.
JI0
Connector for the 6-volt battery.
*
*
Jll
Keyboard/mouse interface connector.
*
J14
and J15
Interface
expansion RAM board 2.
*
J16 and J17
Interface
expansion RAM board 3.
*
J18
and J19
Interface
expansion RAM board 4.
*
*
J20 -- Power connector for the main logic board.
*
SWl
Five-section, dual-inline-package (DIP) switch
that provides all required manual switching for the main
logic board. The following table shows the use and
setting for each section of the switch.
J12 and J13
Interface
expansion RAM board 1.
connectors
for
connectors
connectors
for
for
connectors
for
on-board
on-board
on-board
on-board
El, E2, and E3 -- Speaker terminals for systems that
not have a speaker in the monitor.
Section
Switch
Switch
Switch
Switch
Switch
Use
I
2
3
4
5
2241092-0001
do
Setting
CRT switch
Parallel port
Serial port
128K-byte DRAM
Base DRAM
Off=mono
Off=port 1
Off=port 1
Off=disable
Off=512K bytes
2-5
On=color
On=port 2
On=port 2
On=enable
On=256K bytes
BUSINESS-PRO Hardware Reference
Main Logic Board
80287
J9
SOCKET
J8
E1
U59
::::.-..._-=;---- E2
E3
J19
J18
0
0
0
0
0
0
0
0
J17
J16
J2
J15
J14
J13
J12
0
SW1
J20
J3
2287490
Figure 2-2
Main Logic Board, TI Part No. 2240843-0001, Key Components
2-6
2241092-0001
Main Logic Board
BUSINESS-PRO Hardware Reference
80287
SOCKET
U59
E1
J4
o~5
J18
J19
0
0
0
0
0
J17
J16
J2
0
0
0
J15
J14
J13
J12
0
SW1
J20
J3
2287491
Figure 2-3
Main Logic Board, TI Part No. 2535670-0001, Key Components
2241092-0001
2-7
Main Logic Board
BUSINESS-PRO Hardware Reference
The following paragraphs describe the circuits of the main logic
board.
2.2
SYSTEM CENTRAL PROCESSING UNIT
The system central processing unit (CPU) consists of an 80286
microprocessor unit and an optional 80287 numeric coprocessor.
The microprocessor unit (MPU) and the coprocessor operate in
parallel so that they appear to associated components as a single
chip.
If both devices are installed, the term CPU refers to both
the 80286 and the 80287. The system CPU also includes the system
clocks, the CPU bus buffers and latches, and the CPU status
decoding and control line generation logic.
The following
paragraphs describe the circuits.
2.2.1 Microprocessor Unit
The MPU can operate in either the real address mode or the
protected virtual address mode. A reset operation places the MPU
in the real address mode, which provides up to 1 megabyte of real
address space. The MPU can then be placed in the protected
virtual address mode, in which 1 gigabyte of virtual addresses
can be mapped into a l6-megabyte real address space.
This mode
also provides memory protection to isolate the operating system
and to ensure privacy for the programs and data of each task.
The only way to return to the real address mode from the
protected virtual address mode is to reset the MPU.
2.2.2 Optional Numeric Coprocessor
An additional socket is available for the installation of an
80287
IC
optional
numeric
coprocessor.
For additional
information, refer to the paragraphs entitled Numeric Coprocessor
in Section 6.
2.2.3 CPU Bus Buffering
A set of address and control latches and various bus buffers
(data, address, and control) are provided as part of the cpu.
The following paragraphs describe these circuits.
2.2.3.1 Address and Control Bus Buffering. The CPU controls the
address and control bus buffers, transceivers, and latches via
the address latch enable (ALE) and hold acknowledge (HOLDA)
signal, and a set of control lines labeled P/MD, D/PM, and PM/D,
where P, D, and M represent processor-driven cycles, DMA-driven
cycles, and master-driven cycles, respectively.
2-8
2241092-0001
BUSINESS-PRO Hardware Reference
Main Logic Board
These control lines assume the following levels for the indicated
type of cycle:
*
P/DM -- High for a processor-driven cycle and low for
master- or DMA-driven cycle.
*
D/PM
High for a DMA-driven
processor- or master-driven cycle.
*
PM/D -- High for a processor- or master-driven cycle and
low for a DMA-driven cycle.
Table 2-1 lists the various devices
various types of cycles.
Table 2-1
and
cycle
a
and low for a
their
states
for
the
Address and Control Bus Buffering
+-----------+----------------------+----------+-----------+
MPU Driven Cycles
Devices
On-Board
Memory
I
Other
DMA
or
Refresh
Cycle
Master
Cycle
+-----------+----------+-----------+----------+-----------+
I U3 and U5 I On
I On
I Off
I Off
I
I U4
I Fall Thru I Off
I Off
I
+-----------+----------+-----------+----------+-----------+
I Latched
+-----------+----------+-----------+----------+-----------+
U35 I Latched I Latched
I Fall
Thrul
I U34,
and U36
A --) B
A --) B
B --) A
Fall Thru
B --) A
I
+-----------+----------+---------~-+----------+-----------+
I U37
I A --) B
I A --) B I B --) A
I B --) A
I
I ~~~,u~~9
I A --) B
I A --) B
BIB --) A
I
+-----------+----------+-----------+----------+-----------+
I A --)
+-----------+----------+-----------+----------+-----------+
I U41
I Off
I Off
I Off
I On
I
I U42
I On
I On
I Off
I Off
I
+-----------+----------+-----------+----------+-----------+
+-----------+----------+-----------+----------+-----------+
2.2.3.2 Data Bus Buffering. The data bus buffers, transceivers,
and latches are, for the most part, under PAL(R) control. To
provide for correct data transfer during 8-bit operations, the
active byte of data is written or read on the low byte of the
system data bus during byte wide cycles.
Data bus transceiver
U2l creates this byte switch.
Table 2-2 shows the different
buffer states for various operations.
Refer to the device
programming tables in AppendixD for more information.
2241092-0001
2-9
Main Logic Board
BUSINESS-PRO Hardware Reference
Table 2-2
CPU Driven
Cycles
Buffer States of the Data Bus
U20
U19
U22
U2l
U93
+-----------+-----------+---------+---------+---------+--------+
I ~~~87
I
Off
I Off
I ~if
I a-)b
I Off
I
+-----------+-----------+---------+---------+---------+--------+
R/W
on-board
memory
a-)b
a-)b
Off
a-)b
Off
+-----------+~----------+---------+---------+-------~-+--------+
8-bit
device
low-byte
transfer
b-)a R
a->b W
8-bit
device
high-byte
transfer
Off
Off
Off
b-)a R
a->b W
*2
b->a R
a->b W
*2
+-----------+-----------+---------+---------+---------+--------+
b-)a R
a-)b W
a-)b R
b-)a W
b->a R
a-)b W
*2
b->a R
a-)b W
*2
+-----------+-----------+---------+---------+---------+--------+
8 bit
device
word
transfer
lo-byte 1st
latch b R
a-)b W
Off
b-)a R
a-)b W
+-----------
b-)a R
a-)b W
---------
hi-byte 2nd
stored->a R
Off W
b->a R
a->b W
a->b R
b->a W
*2
*2
Off
b-)a R
a-)b W
*2
b->a R
a-)b W
*2
b-)a R
a-)b W
*2
b->a R
a-)b W
*2
Off
Off
+-----------+-----------+---------+---------+---------+--------+
I b-)a
16-bit
device
transfer
b-)a R
a-)b W
*1
MASTER
CYCLE
a-)b R
b-)a W
*1,*4
a-)b R
b-)a W
*3,*4
Off
*1
a-)b R
b-)a W
*1
a->b R
b-)a W
*3
Off
*1
I
R
a-)b W
*3
+-----------+-----------+---------+---------+---------+--------+
+-----------+-----------+---------+---------+---------+--------+
DMA
CYCLE
+-----------+-----------+---------+---------+---------+--------+
I
REFRESH
I
Off
I
Off
I
Off
I
Off
I
Off
I
+-----------+-----------+---------+---------+---------+--------+
*1
*2
*3
*4
- Condition true for word or low-byte transfers.
- Condition true if the device accessed is on the specified
bus.
If not, U93 is off, and U22 is driven a->b.
- Condition true for word or high-byte transfers.
- Condition true for transfers involving on-board memory.
2-10
2241092-0001
BUSINESS-PRO Hardware Reference
Main Logic Board
2.2.4 CPU Clock Generation and Bus Control
The
CPU
clock
generator consists of a 24-megahertz can
oscillator, a divide-by-two flip-flop, and a divide-by-four flipflop.
These flip-flops provide the 12-megahertz and 6-megahertz
system clocks, each of which has a duty cycle of 50 percent.
These clocks are buffered by an inverting buffer.
A programmable array logic (PAL) device contains synchronizing
logic for the ARDY-, JRDY-, and OWS- lines from the wait-state
control logic and the RES- line from the power-good circuit.
Refer to the device programming tables in Appendix D for more
information.
2.2.5 Reset Circuit
The main logic board provides the following reset conditions:
*
System reset
this reset.
Power-up and dropout conditions initiate
* MPU software reset -- A software
instruction initiates
this reset to return the MPU to the real address mode
from the protected virtual address mode.
*
Coprocessor software reset
A software instruction
initiates this reset to return the coprocessor to the
real address mode from the protected virtual address
mode.
*
Shutdown reset -- A shutdown cycle initiates this reset.
The following paragraphs describe the reset conditions.
2.2.5.1
Software Reset and Shutdown Cycles. A programmer can
reset the MPU by writing the appropriate command to the keyboard
microprocessor. Writing to I/O address 64H with the pulse output
port bit 0 command (FEH) on the data bus causes the keyboard
microprocessor to pulse the software reset (SFTRST-) signal low
for approximately 6 microseconds, thus initiating a software
reset to the MPU. The paragraph in Section 6 entitled Numeric
Coprocessor describes the method of initiating a coprocessor
software reset.
Multiple protection exceptions, while attempting to execute a
single instruction, initiate a shutdown cycle. When this occurs,
the CPU performs a unique bus operation to indicate to the
hardware that a shutdown cycle is in progress and that an MPU
reset should be initiated.
When either a software reset or a shutdown cycle is executing, a
flip-flop and counter hold the MPU software reset (SOFRES) signal
2241092-0001
2-11
Main Logic Board
BUSINESS-PRO Hardware Reference
true for at least 16 processor clock cycles to ensure that reset
occurs.
SOFRES affects only the MPUand not the coprocessor or
the rest of the system.
2.2.5.2 System Reset. The power-good or reset detection circuit
detects insufficient power conditions if the power on the main
logic board is not sufficient to provide reliable operation. A
TL7705A supply voltage supervisor monitors the +5-volt supply.
This configuration provides automatic restart in the event of a
voltage decrease large enough to affect the power supply but not
enough to completely shut it down. A timing capacitor ensures
that any power-up or dropout activates the reset (RES-) line for
at least 5 milliseconds. This reset condition affects the entire
system.
2.2.6 Control Signals
The B02BB bus controller receives status information from the MPU
and converts it to the following control signals:
*
Memory-read control -- BCMRDC-
*
Memory-write control -- BCMWTC-
*
I/O-read control -- BCIORC-
*
I/O-write control -- BCIOWC-
*
Interrupt acknowledge -- INTA-
These signals, except INTA-, are further qualified before being
passed to the expansion bus.
This qualifying eliminates the
possibility of contention on the data bus. BCMRDC- and BCMWTCare transferred to the expansion bus only when the expansion
memory is enabled (I/O port 6B, bit 3). BCIOWC- and BCIORC- are
transferred to the bus when the ongoing I/O transfer operation is
not an access to the 2-kilobyte nonvolatile RAM.
2.3
WAIT-STATE CONTROL LOGIC
Figure 2-4 shows a processor-driven cycle with two wait states
(Twl and Tw2). A PAL device controls the bus controller outputs
and the number of wait states that are inserted into an MPU
cycle.
This logic supplies five basic MPU cycles whose lengths
can be varied by the expansion bus option boards via the WAITsignal and the zero-wait-state (OWS-) signal. The following
paragraphs describe these wait-state cycles.
2-12
2241092-0001
Main Logic Board
BUSINESS-PRO Hardware Reference
Ts
Tc
TW1
TW2
12 MHz
ALE
XA1-XA19
XAO
BA17-BA23
VALID XA1-XA19 ON BUS
VALID XAO ON BUS
VALID BA17-BA23 ON BUS
NEXT CYCLE ON BUS
*MEIVICS16*IOCS16-
MUST BE VALID ON BUS
*WAIT*OWAITLOW HERE
FOR 1 WAIT
LOW HERE
FOR 2 WAITS .. ETC
2287407
Figure 2-4
Required Input Timing for a Processor-Driven Cycle
2.3.1 Zero-Wait-State Memory Cycles
These cycles are performed whenever the CPU attempts to access
the on-board system memory or the memory expansion board with an
active TURBO (high) signal (I/O port address 68H, bit 0).
An
active TURBO signal turns on a light-emitting diode (LED) on the
front panel of the system unit.
No wait states are inserted for
these
memory
cycles.
Therefore,
the cycle time is 335
nanoseconds.
The bus controller outputs are not delayed.
These
cycles allow both 16-bit and 8-bit memory transfer operations.
2241092-0001
2-13
BUSINESS-PRO Hardware Reference
Main Logic Board
2.3.2 One-Wait-State Memory Cycles
MPU-driven memory cycles for standard, l6-bit memory peripherals
have one wait state as shown in Figure 2-5.
These cycles last
500 nanoseconds from start to completion, and the bus controller
outputs are not delayed.
The following types of transfer
operations use this type of memory cycle:
*
An access to the on-board memory or the 3 megabyte
memory expansion board with the TURBO signal inactive.
*
An access to the system ROMs.
*
An access to the TI compatible video board.
*
A memory cycle with an active (low) expansion bus signal
(MEM16-) .
One-wait-state memory cycles allow both l6-bit and
transfer operations.
I'...
83.3 ns
~I
10.4 ns
~
Te
Te
+
+
.. +
,
t'lfflill
W'IIA
:
XBHEXAI-XA19
:
WRITE ADDRESS VAllO
III/, (11111
NEXT CYCLE ADDRESS
WRITE ADDRESS VALlD
V, (IIIIII/,
NEXT CYCLE ADDRESS
:
,
,
PREVIOUS CYCLE
,
I
17,f/J
YIIA
:
READ ADDRESS VAllO
AO-A23
MA!·MA23
•
,
I
I
BALE
READ ADDRESS VALID
ADDRYlffM
:
,,
READ ADDRESS VALID
WRITE ADDRESS VALID
:
YII,
WRITE ADDRESS VALID
:
•
LSAO
PREVIOUS CYCLE
WII/1
XAO
PREVIOUS CYCLE
Vlfflill
,
:
READ ADDRESS VALID
:
READ XAO VALID
:
~;lffaa
:
LMRDC-
MEM16OR
EQUIVALENT
MOTHERBOARD
SIGNAL
VII.
:
:
,
,
rlllill
VIIIIIIA
VilA
III
:
'/11.
,
,,
,,
VIllA
7777J
rIIlll
WRITE DATA VALID ON BUS
:
rIIllllll III. IIIIIII
,,
DATA ON
WRITE DATA VALID ON BUS
I
+
I
EXPANSION
,,
I
WRITE XAO VALID
:
I
YlIIIIIIII,
fliliA
,,
'IIIIIIIIIJ
V11~
DEN
• XDB-XD15
WRITE ADDRESS VALID
I
I
XDO-XD7
fliliA
I
,,
DT/R
NEXT CYCLE ADDRESS
Mla
I
LMWTC-
,
:
VilA
READ ADDRESS VAllO
BA 17-BA23
memory
WRITE CYCLE
READ CYCLE
12 MHz
+
8-bit
I
BUS MUST
BE VALID
I
Figure 2-5
I
I
I
I
I
One-Wait-State MPU-Driven Memory Cycles
2-14
2241092-0001
Main Logic Board
BUSINESS-PRO Hardware Reference
2.3.3 One-Wait-State I/O Cycles
Figure 2-6 shows an MPU-driven I/O read cycle and an MPU-driven
I/O write cycle; each of which has one wait state. These cycles
are performed for MPU-controlled I/O operations with an active
(low) I/O expansion bus signal (I016-).
The bus controller
outputs are delayed by 83 nanoseconds so that they do not become
active until the middle of the Tc state.
However, they still
become inactive at the normal (end-of-cycle) time. These cycles
require 500 nanoseconds for completion, and they support both 16bit and 8-bit I/O transfer operations.
WRITE CYCLE
READ CYCLE
I
12 MHz
I
1i.LI..J.:LI....-_ _ _ _ _ _ _ _~' __
BALEf-_-:-_ _1lLUI
--1ZZi
XBHE-t-==:-::7':':::-:O-Tl7Tr.rr-:~=~==--------.!...--T77Trr-____,..---==-:---------!I---,,-'T7">
XA1_XA15t--'Pc..:.:R:;.:.EV;.=;'DU~S~C.:.::YC=LEc...J/JJ=-c..:.:R~EA:::..D:;.:.CY.;::CL;:;.EA::::D~DR.:;;;ES::.::S_ _ _ _ _ _;--_....Jti,I..!I..J.......::W:..:.:R!..:.!'TE:..::C~YC:.=:LE:..::A~DD:.:.:R::.::ES;;:..S _ _ _ _ _---;. _ _...lLLL
XAO
PREVIOUS CYCLE
READ CYCLE XAO
WRITE CYCLE XAO
CMDLY I--_--,-_---"~~
IORC-
WRITE DATA VALID ON BUS
22874(19
Figure 2-6
One-Wait-State MPU-Driven I/O Cycles
2.3.4 Four-Wait-State Cycles
Figure 2-7 shows an MPU-driven cycle with four wait states. MPUcontrolled transfer operations are given four wait states if all
of the following conditions are true:
*
Both MEM16- and I016- are inactive (high) for an 8-bit
data transfer operation.
*
The cycle is not an access to on-board memory or
megabyte memory expansion board.
*
The cycle is not an access to the system ROMs.
*
The cycle is
video board.
2241092-0001
the
3
not a memory access to the TI compatible
2-15
Main Logic Board
BUSINESS-PRO Hardware Reference
For four-wait-state cycles, the bus controller butputs are
delayed by 83 nanoseconds so that they do not become active until
the middle of the Tc state. However, they still become inactive
at the normal (end-of-cycle) time. These cycles support only 8bit transfer operations to either memory or the I/O space, and
they require 1 microsecond for completion.
BALE ~_ _-+-_~Ul
XBHEXA 1-XA 19
~P.;,;;RE:..:..:VI.::.;OU;,;;.S,;;.;.CY,;;.;.CL;,;;.E...JU:."-'-_ _ _ _...;.R:::;.EA:.:,.D.;:,;.OR:..,:.W:,:.:;RIc..::TEc.:.:A::.,:DD.:.;,:RE:.:,:SS:...;V,;,.;.:ALc:,ID_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - ._ _ _ _.r.GGoI:
BA17-BA23
~~~=~AO~D~RE~SSGV~AL;§ID==JZ::~~~NE~XT::£CY~C~LE~AD~D~RE~SS==============~==~
X~~P~REV-IO~U~SC~YC~LE~n=~~A~DD~RE~SS~V~AL~ID----------------------------------------~-----CMDLY ~----i----,t~~
IORC-,IOWC
INTA-
WRITEDATAt:=j:=3~~~~~~~~C=================~==:J;~
Figure 2-7
Four-Wait-State MPU-Driven Memory or I/O Cycle
2.3.5 Ten-Wait-State Cycles
Figure 2-8 shows an MPU-driven cycle with ten wait states.
MPUcontrolled access operations are issued ten wait states if all of
the following conditions are true:
*
Both MEM16- and 1016transfer operation.
*
The cycle is not an access to on-board memory or
megabyte memory expansion board.
*
The cycle is not an access to the system ROMs.
*
The cycle is
video board.
are inactive for a l6-bit data
the
3
not a memory access to the TI compatible
2-16
2241092-0001
BUSINESS-PRO Hardware Reference
Main Logic Board
The ten-wait-state transfer mode allows the l6-bit MPU to handle
word communications with 8-bit peripheral devices. The operation
begins as a normal four-wait-state transfer operation, in which
the 80288 outputs are delayed by 83 nanoseconds and the low data
byte is transferred as normal.
At the end of the fourth wait state, the bus controller outputs
are forced to their inactive states.
This signals any device
that is being written to that the current transfer operation is
complete. If the MPU is attempting to read data, the data latch
is clocked at this time. This causes the low-order data byte to
be saved so that it can be read by the MPU at cycle completion.
During the fifth wait state, the MPU forces address line ALTAO
high and latches it, thus causing the high-order data byte to be
transferred.
During the sixth wait state, the bus controller reactivates its
output signals, and the cycle ends after the tenth wait state.
The total cycle time for this type of cycle is two microseconds.
To an option board on the expansion bus, the ten-wait-state cycle
appears to be two consecutive four-wait-state transfer operations
except that the expansion bus signal (BALE) is not activated
during the second (high-byte) transfer.
STATEjEL-+_......RlL--!...-.liL--=-----r.iL--~..r:.4...--=-~L-"---Jlll....+_.....ll!IL--"--.IoII.....--=------''-.---=-....m----"'---Jr:4.-_f,0---J'"''
I
BALE ~-'--UI
•
I
-+-___
CONALEt---+-_ _ _ _ _ _ _ _ _ _ _ _ _ _
XA1- XA19 f--.--Ct used
IR15
D06
Reserved
N/A
Not used
Interrupt
Level
2241092-0001
2-47
Use
Main Logic Board
Table 2-8
BUSINESS-PRO Hardware Reference
BUSINESS-PRO Interrupt Levels (Continued)
TI Mode
PC-AT Mode
Bus
Pin
Use
Bus
Pin
IR03
B25
Serial port 2 or
tape drive
B2S
Serial port 2,
tape drive, or
timer 1
IR04
B24
Serial port I
B23
Parallel port 2
or Ethernet
IROS
B23
Ethernet or
parallel port 2
B24
Serial port 1 or
parallel printer
IR06
B22
Floppy disk
B22
D07
Floppy disk
Winchester drive
IR07
B21
Parallel port 1
B21
Parallel port 1,
keyboard, or
math coprocessor
Interrupt
Level
Use
1-.TrVnt;1 •
.L'4V..LU.
The interrupt levels in this table are listed in their order
of priority. That is, the NMI has the highest priority and
IR07 has the lowest priority.
----------------------------------~---------------------------~-
2.6.7.1 Interrupt Levels 0 Through 15. The principal elements
of the interrupt logic are two 8259A programmable interrupt
controllers, which are cascaded in IBM PC-AT compatible mode and
are programmed for edge-sensitive interrupt detection. These
devices prioritize the incoming interrupts, provide interrupt
masking, and generate an interrupt vector to the CPU during an
interrupt acknowledge cycle (INTA- active). A set of OR gates
allow some of the interrupt levels to be shared. A set of
multiplexers allow switching between TI and PC-AT compatible
interrupts.
During
the
interrupt
acknowledge
cycle,
the
interrupt
controller's internal decoding logic array enables the contents
of the I/O data bus onto the system data bus. This data (which
is expected to be the vector from the programmable interrUpt
controller) cannot be disabled. Therefore, the system can have
no other interrupt controllers.
All expansion interrupt signals are terminated by either a
pulldown resistor pack to ground or a pullup resistor pack to +5
2-48
2241092-0001
BUSINESS-PRO Hardware Reference
Main Logic Board
volts. Generally, the expansion interrupts shared by other
interrupts in the TI mode are pulled down, while all others are
pulled up.
2.6.7.2 Nonmaskable Interrupt. The main function of the NMI is
to detect parity errors in the memory system, but the TI
compatible video option board can also use it to indicate the
vertical synchronization function if it has been enabled by
software. During a nonmaskable interrupt condition, the NMI
input to the MPU must remain active (high) for a minimum of 350
nanoseconds to be recognized by the MPU. Also, to ensure proper
recognition, the NMI line must remain inactive for a minimum of
350 nanoseconds between consecutive NMls.
In the case of
simultaneously occurring NMls, it is possible that only one will
be recognized.
NMls can be masked out to allow testing of the memory system
without possible interruption by parity errors. This can be done
by performing an I/O write operation to port address 6lH with
either bit 2 high (on-board NMls) or bit 3 high (expansion board
NMls).
An I/O write operation to port address 70H with bit 7
high masks out all NMls.
2.7
EXPANSION BUS INTERFACE
The expansion bus interface board contains the I/O expansion bus
interface logic, including all necessary bus connectors and
passive termination. The board mounts above the main logic board
in the system enclosure and connects to the main logic via a
small board called the vertical board. A common wiring harness
connects voltages from the power supply to both the bus interface
board and the main logic board.
The expansion bus interface provides the capability of adding
memory-mapped
and
I/O-mapped devices to the system.
The
interface provides seven DMA channels and an interrupt system for
devices that require interrupts for efficient operation.
It
provides 14 slots with fourteen 62-pin connectors and eleven 38pin connectors. These slots can accommodate any or all of the
following option boards:
*
Six full-length, PC-AT compatible boards with l6-bit DMA
channels.
*
Two full-length, PC-AT compatible boards with 8-bit DMA
channels.
*
Five half-size boards with l6-bit DMA channels.
*
One half-size board with an 8-bit DMA channel.
2241092-0001
2-49
Main Logic Board
BUSINESS-PRO Hardware Reference
Logic sheet 26 (see Appendix E) shows the expansion
bus
connectors.
Table 2-9 lists the connector pin numbers and their
corresponding signals. These signals are defined as follows:
*
6BUS -- Expansion bus clock.
This 6-megahertz, 50
percent duty cycle clock provides synchronization for
the expansion bus option boards.
*
XDO through XD15
Expansion
data
bus.
These
bidirectional
data
lines
carry data between the
expansion interface and the CPU, the system memory, and
the I/O interface.
*
WAITDevices on the expansion bus generate this
signal to indicate to the MPU or the DMA controller that
the current memory cycle or I/O cycle needs to be
extended.
*
AEN
Address enable.
The DMA controller activates
this line to indicate that it has acquired control of
the address bus, the data bus, and the read/write
control signals from the MPU.
*
XAO through XA19 -- Expansion address bus. These lines
are driven by either the CPU, the DMA controller, or a
bus master to address memory and I/O devices within the
system.
These lines are latched by the falling edge of
BALE during CPU driven cycles.
*
DRST
Device reset.
A system power-up operation
generates this signal to initialize the logic on the
expansion bus option boards.
*
SPEAKER -~ This line carries audio from the expansion
bus option boards to the system speaker amplifier. This
signal does not appear on the edge connectors but may be
jumpered to via connector J6 on the expansion bus
interface board.
*
OWS- -- Zero wait states.
An option board generates
this signal to indicate to the system that it needs no
additional wait states to complete the cycle.
The
minimum default for any device on the I/O bus is one
wait state.
*
MWTC- and LMWTCMemory write control and lower
memory write control.
When active (low), these lines
indicate that a memory write operation is in progress.
MWTC- is active for all memory write cycles, while
LMWTC- is active only for write cycles to the lower 1megabyte memory space. These signals can be masked by
software.
2-50
2241092-0001
BUSINESS-PRO Hardware Reference
Main Logic Board
* MRDC- and LMRDC- -- Memory read control and lower memory
read control. When active (low), these lines indicate
that a memory read operation is in progress. MRDC- is
active for all memory read cycles, while LMRDC- is
active only for read cycles to the lower l-megabyte
memory space. These signals can be masked by software.
*
IOWC- -- I/O write control.
When active, this line
indicates that an I/O write operation is in progress.
*
IORCI/O read control.
When active, this line
indicates that an I/O read operation is in progress.
*
l4.3MHZ -- This l4.3l8-megahertz (70-nanosecond period,
50 percent duty cycle) clock is provided to accommodate
any PC-AT compatible option boards that may require it.
*
BA17 through BA23 -- Upper address lines.
These lines
extend
the addressing capability of the expansion
address bus to 16 megabytes.
These lines are not
latched during MPU cycles, and the active (high) state
of BALE can be used to guarantee their validity.
I/O
options latch these lines on the falling edge of either
BALE or address enable (AEN) during DMA cycles.
*
BALE
The CPU uses this line to indicate that it is
placing a valid address on the address bus. When used
in conjunction with AEN, this signal indicates that the
address is valid.
BALE is forced high during DMA and
refresh cycles.
*
NMINonmaskable
interrupt.
The
nonmaskable
interrupt signal logic uses this signal to generate an
NMI input to the MPU. This signal normally indicates a
system parity error condition.
*
IRQ3 through IRQ7 and IRQ9 through IRQ15 -- An I/O
device uses these lines to indicate to the CPU that the
device requires attention. In the event that more than
one device requires service at the same time,
IRQ9
through IRQ15 are cascaded from a slave interrupt
controller at level 2.
Thus, these devices have a
higher
priority than the direct input devices at
interrupt levels IRQ3 through IRQ7.
*
DRQO through DRQ3 and DRQ5 through DRQ7 -- DMA request.
When active (high), these lines indicate to the DMA
controller that a peripheral device requires attention.
Each of these lines is associated with 1 of 7 DMA
channels. Channels 0 through 3 provide a-bit data
transfers; channels 5 through 7 provide 16-bit data
transfers.
2241092-0001
2-51
Main Logic Board
BUSINESS-PRO Hardware Reference
* DACKO- through DACK3- and DACK5- through DACK7-
DMA
acknowledge.
The DMA controller uses these lines to
acknowledge requests from peripheral devices.
Each of
these lines is associated with one of the 7 DMA
channels.
*
T/C -- Terminal count.
The DMA controller activates
this line during a DMA data transfer operation to
indicate that the last data byte has been sent.
*
REFRESH- -- The DMA controller or bus master activates
this line to indicate that a memory refresh cycle has
been requested or is in progress.
*
XBHE- -- Expansion bus high enable. The falling edge of
BALE latches this signal to indicate that an upper data
bus
(XD8
through XD15) transfer operation is in
progress.
*
MASTER- -- An external bus master that desires to gain
control
of the system, activates this line after
activating its associated DRQ line and receiving the
appropriate DACK-. If the bus master requires more than
15 microseconds to complete its operation, it must also
gain control of the system memory refresh to prevent
possible corruption of system memory. The presence of a
coprocessor in the CPU limits DMA (master) cycles to 500
microseconds.
*
MEM16An option board generates this signal to
indicate to the system that it is capable of performing
l6-bit memory data transfer operations.
*
I016An option board generates this signal to
indicate to the system that it is capable of performing
16-bit I/O data transfer operations.
2-52
2241092-0001
BUSINESS-PRO Hardware Reference
Table 2-9
Main Logic Board
Expansion Bus Pin Assignments
-----------------------------------------------------------------Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Number
Name
Number
Name
Number
Name
Name
Number
------------------------------------------------------------------
AOl
A02
A03
A04
A05
A06
A07
A08
A09
A10
All
A12
A13
A14
A15
A16
A17
A18
A19
A20
A2l
A22
A23
A24
A25
A26
A27
A28
A29
A30
A3l
NMIXD7
XD6
XD5
XD4
XD3
XD2
XDl
XDO
WAITAEN
XA19
XA18
XA17
XA16
XA15
XA14
XA13
XA12
XAll
XA10
XA9
XA8
XA7
XA6
XA5
XA4
XA3
XA2
XAl
XAO
BOl
B02
B03
B04
B05
B06
B07
B08
B09
B10
Bll
B12
B13
B14
B15
B16
B17
B18
B19
B20
B2l
B22
B23
B24
B25
B26
B27
B28
B29
B30
B3l
GND
DRST
+5V
IRQ9
-5V
DRQ2
-12V
OWS+12V
GND
LMWTCLMRDCIOWCIORCDACK3DRQ3
DACK1DRQl
REFRESH6BUS
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
DACK2TIC
BALE
+5V
l4.3MHZ
GND
COl
CO2
C03
C04
COS
C06
C07
C08
C09
C10
Cll
C12
C13
C14
C15
C16
C17
C18
XBHEBA23
BA22
BA2l
BA20
BA19
BA18
BA17
MRDCMWTCXD8
XD9
XD10
XDll
XD12
XD13
XD14
XD15
DOl
D02
D03
D04
DOS
D06
D07
D08
D09
D10
Dll
D12
D13
D14
D15
D16
D17
D18
MEM161016IRQ10
IRQll
IRQ12
IRQ15
IRQ14
DACKODRQO
DACK5DRQ5
DACK6DRQ6
DACK7DRQ7
+5V
MASTERGND
------------------------------------------------------------------
2241092-0001
2-53
Power Supply
Business-Pro Hardware Reference
Section 3
Power Supply
3.1
POWER SUPPLY OUTPUT VOLTAGES
This section contains tabulated information about the BUSINESSPRO computer's power supply output voltages.
The nominal output
voltages of the power supply are listed in Table 3-1.
3.2
BUSINESS-PRO POWER CONSUMPTION
Table 3-2 is a list of the basic electrical components that make
up the BUSINESS-PRO, along with the amount of power consumed by
each item.
Nominal Output
Voltage
Average
Maximum
Current
+5.1 Vdc (Reg)
25.0 Amperes
+12.0 Vdc (Reg)
7.5 Amperes
-12.0 Vdc
0.8 Amperes
Table 3-1
2241092-0001
Maximum
Surge
Current
10.8 Amperes
Tolerance
(Percent)
Peak-to-Peak
Ripple
+3, -2
50 millivolts
+/- 5
100 millivolts
+/- 8
100 millivolts
Power Supply Nominal Output Voltages
3-1
Power Supply
Business-Pro Hardware Reference
Table 3-2
Power Configuration Table
------------------------------------------------------ ----------~-
Device
Main Logic Board
Fan
3 Megabyte RAM
Mouse
Keyboard
PC-AT CRT Controller
TI CRT Controller
Speech
LAN
Tape Controller
Winchester Controller
Floppy Controller
TI Communication
TI Communication
Winchester Drive
Winchester Drive
Cartridge Tape
Floppy Disk
Totals
Power Consumed -- Amperes (Typical)
5-volt 12-volt ~12-volt Power Slot
5.50
1.50
0.25
0.40
1.50
1. 50
1. 50
1. 70
1. 50
1. 00
0.05
0.30
0.20
0.05
0.10
18.7
3.6
7.5
2.0
2.0
7.5
7.5
11.1
8.5
7.5
5.0
0.75
0.31
0.31
1. 00
1. 00
1. 00
0.50
0.05
0.05
1.50
1. 50
2.00
1. 00
0.05
0.05
21. 37
6.65
0.25
3.8
2.8
2.8
23.0
23.0
29.0
14.5
Fl
F2
F3
F4
F6
HI
H2
H4
H5
Pl/P2
P3/P4
P5
P6
179.8
------------------------------------------------------ ---------~-
3-2
2241092~0001
Power Supply
Business-Pro Hardware Reference
4.0 ±.4
G)
@ 9 PLACES
POWER SUPPLY
(REFI
P4
STRAIN RELIEF
(REFI
2287412
Figure 3-1
Table 3-3
2241092-0001
Main Logic Board Power Connector
Main Logic Board Power Connector Pinouts
Pin
Number
Output
Wire
Color
1
+5 Vdc
Red
2
+5 Vdc
Red
3
+5 Vdc
Red
5
+12 Vdc
Yellow
6
Ground
Black
7
+5 Vdc
Red
8
Ground
Black
9
Ground
Black
10
Ground
Black
3-3
Business-Pro Hardware Reference
Power Supply
4.0± .4
6 PLACES
P20
POWER SUPPLY
(REF)
2287413
Figure 3-2
Table 3-4
Expansion Bus Board Power Connector
Expansion Bus Board Power Connector Pinouts
Pin
Number
Output
Wire
Color
1
+12 Vdc
Yellow
3
+5 Vdc
Red
4
Ground
Black
5
-12 Vdc
Green
6
+5 Vdc
Red
7
Ground
Black
3-4
2241092-0001
Power Supply
Business-Pro Hardware Reference
STRAIN RELIEF
(REF)
POWER SUPPLY
(REF)
B
A
4
@,
26.0± .6
SECTION A-A
2 PLACES
SECTION B - E
2 PLACES
2287414
Figure 3-3
Table 3-5
Disk Drives 1 Through 4 Power Connector
Disk Drives 1 Through 4 Power Connector Pinouts
Pin
Number
2241092-0001
Output
Wire
Color
1
+12 Vdc
Yellow
2
Ground
Black
3
Ground
Black
4
+5 Vdc
Red
3-5
Business-Pro Hardware Reference
Power Supply
STRAIN RELIEF
(REF)
8.5± .6
4
..
A
~
3.0± .6
~
VIEWA - A
DISK
[ill
POWER
SUPPLY
(REF)
4 PLACES
2287415
Figure 3-4
Table 3-6
Disk Drives 5 and 6 Power Connector
Disk Drives 5 and 6 Power Connector Pinouts
Pin
Number
1
Output
Wire
Color
+12 Vdc
Yellow
2
Ground
Black
3
Ground
Black
4
+5 Vdc
Red
3-6
2241092-0001
BUSINESS-PRO Hardware Reference
Keyboard
Section 4
Keyboard
4.1
GENERAL
The BUSINESS-PRO keyboard provides both TI Professional Computer
(TIPC) and IBM Personal Computer AT (PC-AT) capabilities. This
easy-to-use keyboard includes the following advanced design
features:
*
Typamatic transmission
*
N-key rollover
*
*
Programmable key click
*
Standard typewriter layout
*
Dedicated function keys
*
*
*
Separate cursor-control keypad
Improved tactile response
Numeric keypad
Variable tilt adjustment
The keyboard also features a total of 100 keys. These can be
expanded to a total of 144 by removing dummy keycaps from the
unit and replacing them with normal keycaps. Special software
can be used to program these additional keys.
The following paragraphs describe some of the keyboard features.
4.1.1 Typamatic Transmission
Typamatic transmission is the ability of the keyboard to repeat
keycode transmissions continuously when a key is depressed and
held down. The frequency at which this occurs depends on the
typamatic rate, which can be set by a command from the system
(paragraph 4.5.5). The typamatic delay is also programmable, and
its purpose is to provide sufficient delay between the time that
a key is depressed and the time that typamatic transmission
actually begins. This prevents the accidental repetition of
characters.
2241092-0001
4-1
Keyboard
BUSINESS-PRO Hardware Reference
If you hold down more than one key at a time, only the last key
depressed repeats at the typamatic rate.
When this key is
released, the typamatic action stops even if the other keys are
still held down.
4.1.2 N-Key Rollover
N-key rollover is the ability of the keyboard to recognize and
correctly decode the key depressed most recently regardless of
the number of keys currently depressed.
4.1.3 Key Click
The keyboard features an electronic clicker to provide
a
simulated key click sound. This key click feature is controlled
by system commands (paragraph 4.5.1), which can turn the clicker
on or off or adjust its volume.
4.1.4 Mode Indicators
The mode indicators are three light-emitting diodes (LEDs)
located at the upper right corner of the keyboard.
These LEDs
indicate the state of the capitals lock (Caps Lock), the numbers
lock (Num Lock), and the Scroll Lock keys.
Commands from the
system turn the LEDs on or off.
4.1.5 Keyboard Buffer
The keyboard buffer is a l6-character, first-in, first-out (FIFO)
memory that stores data generated by the keyboard until the
keyboard interface is ready to receive it. In anticipation of a
Resend command from the system, the keyboard buffer retains a
previously transmitted character until
the
next
one
is
transmitted.
If the buffer becomes full,
it substitutes an
Overrun command (command code OOH) for the seventeenth character.
All keystrokes following the overrun condition are lost.
The following commands are
transmitted
buffering) as soon as they are generated:
directly
*
Command code AAH
Self-Test OK command
*
Command code EEH
Echo Response command
*
Command code FAH
Acknowledge command
*
Command code FDH
Diagnostic Failure command
*
Command code FEH
Resend command
4-2
(without
2241092-0001
Keyboard
BUSINESS-PRO Hardware Reference
4.2
KEYBOARD OPERATIONS
After performing a self-test at power-up the keyboard scans the
key-switches and sends the scan codes of pressed keys to the
keyboard interface in the proper sequence. To ensure proper,
fault-free operation, the keyboard also tests its sense amplifier
periodically during normal operation. The following paragraphs
describe the keyboard operations.
4.2.1 Keyboard Self-Tests
The keyboard performs a self-test at power-up and another one
periodically to determine the operational status of the keyboard.
Upon self-test completion, the keyboard sends a status command to
the system.
4.2.1.1 Basic Assurance Self-Test. The keyboard performs the
basic assurance self-test within one second after power-up or
upon receiving a Reset command from the system.
The basic
assurance self-test performs a checksum test on the keyboard
read-only memory (ROM) and an addressing test on its randomaccess memory (RAM). The test also performs an operational check
on the keyboard sense amplifier and turns on all three modeindicator LEDs for 300 milliseconds. Upon self-test completion,
the keyboard sends either a Self-Test OK command or a Diagnostic
Failure command to the system.
4.2.1.2 Periodic Self-Test. The periodic self-test checks the
sense amplifier's response to a known input. If the test fails,
the keyboard sends a Diagnostic Failure command to the system.
If the test passes, the keyboard sends no command.
4.2.2 Power-Up Sequence
At power-up, the keyboard logic generates a power-on reset,
during which the mode-indicator LEDs are turned on for a period
of two to three seconds. Immediately after this power-on reset
operation, the keyboard begins its basic assurance self-test.
During this time, keyboard transmission is inhibited for a period
of 300 milliseconds to 9 seconds, after which the keyboard sends
a status command to the system. Upon passing the self-test, the
keyboard assumes the initial default state and begins its normal
key-switch scanning operation.
Table 4-1 lists the initial
default conditions.
2241092-0001
4-3
Keyboard
BUSINESS-PRO Hardware Reference
Table 4-1
Initial Keyboard Default Conditions
-----------------------~----------------------------------------~
Default State
Function
Typamatic rate
15 +3 keycodes per second
Typamatic delay
500 +10 milliseconds
Operation
Scanning key switches
Key click volume
Off
Mode-indicator LEDs
Off
+
+
4.3
KEYBOARD CONNECTOR SPECIFICATIONS
Figure 4-1 shows the keyboard connector pin arrangement. The
keyboard connector is a 5-pin DIN connector that provides the
required interface signals between the keyboard and the system.
A connector at the base of the BUSINESS-PRO monitor provides a
convenient connection for the keyboard.
Table 4-2 lists the
keyboard connector pin assignments.
PIN2
PIN5
PIN4
PIN 1
PIN3
2287416
Figure 4-1
Keyboard Connector Pin Arrangement
4-4
2241092-0001
BUSINESS-PRO Hardware Reference
Table 4-2
Keyboard
Keyboard Connector Pin Assignments
Function
Pin Number
1
Clock
2
Data
3
Reserved
4
Signal ground
5
5.1 +0.51 volts dc
NOTES:
1. The TTL levels for the data and clock
lines are: high -- 2.4 to 5.25 volts;
low -- 0.0 to 0.4 volt.
2. The cable shield is connected to chassis.
The following paragraphs describe the keyboard interface lines.
4.3.1 Clock Line
The clock line is a bidirectional line that transfers timing and
control information from the system to the keyboard and status
information from the keyboard to the system.
Open-collector
drivers at each end of the clock line enable either the system or
the keyboard to control the state of the line.
In its idle
clocking data
microseconds
consists of a
followed by a
condition, the clock line is normally high. When
or commands, the clock has a period of 60 (±5)
with a 50 percent duty cycle.
A clock cycle
30 microsecond period in which the signal is low
30 microsecond period in which it is high.
4.3.2 Data Line
The data line is a bidirectional line that transfers data from
the keyboard to the system and transfers commands from the system
to the keyboard. All information transfers (data or commands)
are performed in bit-serial fashion. Open-collector drivers at
each end of the data line control the direction and state of the
line.
2241092-0001
4-5
BUSINESS-PRO Hardware Reference
Keyboard
4.4
HARDWARE HANDSHAKING PROTOCOLS
The
following
protocols
for
transmissions.
paragraphs describe
keyboard-to-system
the hardware handshaking
and
system-to-keyboard
4.4.1 Keyboard Transmission
Each keyboard transmission consists of an II-bit frame of serial
data that begins with a single-bit, logical-low start element
(bit 0) and ends with a single-bit, logical-high stop element
(bit 10). The other nine bits (1 through 9) are the 8-bit data
byte (DATAO through DATA7) followed by a single, odd parity bit.
Figure 4-2 shows the data frame format.
10
1
8
9
7
6
I
5
4
3
I
\
[
2
0
1
/
I0 I
L
START ELEMENT
DATAO THROUGH DATA7
ODD PARITY BIT
' - - - - - STOP ELEMENT
2287417
Figure 4-2
Keyboard Data Frame Format
Each key station has a unique make code, which is a two-digit
(single-byte) hexadecimal number. The break code for a given key
station is identical to its make code, except that it is always
preceded by FOH which identifies the code as a a break code.
Thus, a break code transmission requires two data frames, whereas
a make code transmission requires only one. Figure 4-3 shows the
key station numbers and their respective make codes.
4-6
2241092-0001
I-:rj
1-'\!:l
~
I-i
(l)
"""I
-...J
2
C2H
28
3
B9H
29
4
B8H
30
5
B7H
31
6
B6H
32
7
B5H
33
8
B4H
34
9
10
B3H
35
B2H
36
11
B1H
37
12
DFH
38
13
DEH
39
14
15
DOH
140
16
DCH DBH
41
~2
17
18
19
D9H
43
D8H
44
D4H
~5
20
9CH
46
21
96H
47
03H
9BH
95H
BAH
69
70
71
172
76H* 77H* 7EH* 84H*
73
74
75
76
D2H
~4
9AH
95
94H
96
8BH
S7
6CH* 75H * 70H * 7CH*
98
99
100
101
01H
119
99H
120
93H
121
8CH
122
6BH* 73H* 74H * 7BH*
123
124
125
126
~EH
137
98H
138
92H
139
80H
140
69H* 72H* 7AH* 79H*
141
142
143
144
58H* 90H
97H
91H
BEH
BOH
CJ)
03H* bBH* BCH
102
103
104
rt
Pl
rt
02H* bAH* BOH
127
128
129
OEH* 16H* IEH* 26H * 25H * ~EH * 36H * 3DH* 3EH* 46H* 45H* 4EH* 55H * 5DH* 66H*
56
8
59 J60 J61 :
63 J64 J65 *1 66 J67 J68
1;57
ODH*
15H * IDH * 24H * 2DH * 2CH* 35H * 3CH* 43H * 44H
4DH* 54H * 5BH* 5AH *
80
93
82
5
86
87
:11
J83 t 4
J89
1
14H*
ICH * 1BH * 23H * 2BH * 34H * 33H * 3BH* 42H * 4BH * 4CH* 52H * 07H
118
113
11106 1:07 T08 Jl09
10
11
1112
14 :
16 : 17
105
59H*
12H* BFH 1AH* 22H* 21H* 2AH*32H* 31H* 3AH* 41H* 9H* 4AH* 51H*
135
136
134
130
131
132
133
01H* P9H * BEH
llH * C1H
w
105H* 06H * BAH
53
54
55
~
(l)
04H* OCH* BBH
'77
178
79
"<
"""I
1
C3H
27
1-'-
0
t
1~1
19H*
1
t
T J;
1~2 :1
:1,
:!
J~8
1
:1
29H*
r
:!~O :t911~2
~!15
t
I;
05H
~
'"n
0
0..
(l)
::s:
Pl
'"0
2287418
* PC-AT COMPATIBLE KEY SCAN COOS
D6H
122
89H
~8
23
88H
49
24
87H
50
25
86H
51
26
85H
52
70H* 71H* 81H
Keyboard
BUSINESS-PRO Hardware Reference
The keyboard transmits under either of the following conditions:
*
Detection of a valid key depression (make code) or a
valid key release (break code)
*
Recognition of a valid system command
The keyboard supplies the clock that synchronizes the data sent
by the keyboard.
Each keyboard transmission requires a maximum
of 2 milliseconds, and the keyboard samples the clock line at
least
once
every
60
microseconds
during
the keyboard
transmission.
The keyboard responds to each system command or data transmission
within 20 milliseconds unless the system prevents a keyboard
output.
If the keyboard response is invalid or contains a parity
error, the system sends the command or data again.
In this case,
the system does not issue a Resend command.
4.4.1.1 Transmission Process.
Figure 4-4
for a complete data frame transmission.
of a high clock line and a high data line
that it can begin a data transmission.
requires the following steps:
shows a timing diagram
Simultaneous detection
signals the keyboard
Each data transmission
1. The keyboard places the start element on the data
(sets the data line low).
line
2. The keyboard pulses the clock low for one half clock
period,
then changes the clock to its high state to
clock in the start element.
The clock remains high for
one half clock period, thus completing the clock cycle.
3. While the clock is high, the keyboard places the
data bit (DATAO) on the data line.
4. The keyboard performs another clock cycle (as
in
first
step
2) to clock in DATAO.
5. The keyboard repeats steps 3 and 4 for each of the
remaining data bits (DATAl through DATA7) and for the
parity bit.
6 . The keyboard places the stop element on the
(sets the data line high).
data
line
7. The eleventh falling edge of the clock clocks in the
stop element,
and the system holds the clock line low
to indicate that it has received and is processing
data.
8. Upon completion of the data processing, the system
relinquishes control of the clock line, allowing it to
return to its high state.
This indicates that the
4-8
2241092-0001
BUSINESS-PRO Hardware Reference
Keyboard
operation
is
complete
transmission can begin.
and
that
SYSTEM TAKES
CONTROL INHIBITS
KEYBOARD CHECKS FOR
CLEAR-TO-SEND
CLOCK
~
keyboard
KEYBOARD
RELINQUISHES
CONTROL
,/ r
1---...,
n-,
DATA
another
'--"""(f-(-,-----", SYSTEM
"-....READYTO
RECEIVE
START
I DATABITO I DATABIT1
il)DATABIT71
PARITY
STOP
II
!
KEYBOARD BRINGS DATA
LINE LOW
2287419
Figure 4-4
Keyboard Transmission Timing -- Completed Transmission
4.4.1.2 Aborted Keyboard Transmission.
Figure 4-5 shows
timing diagram for a typical aborted keyboard transmission.
a
The system can interrupt a keyboard transmission at any time by
driving the clock line low and holding it in this state. Between
each data bit, the keyboard samples the clock line for a high
condition.
Detection of a low clock at this time indicates a
clock line contention.
If the keyboard detects a clock line contention prior to the
rising edge of the tenth clock cycle, the keyboard aborts the
transmission by turning off the output device of both its clock
line and data line drivers. The aborted data byte then remains
in the keyboard buffer from which it can be resent if the system
requires.
2241092-0001
4-9
Keyboard
BUSINESS-PRO Hardware Reference
KEYBOARD CHECKS FOR
CLEAR-TO-SEND
CLOCK
SYSTEM HOLDS
~I---""
1/
DATA
START
CLOC/KLOW
r,
,
SYSTEM STARTS TRANSMISSION
---1/
il-(l
J-
I DATA.,T" '~DATA.'TN\ I ~I
KEYBOARD BRINGS DATA LINE LOW
KEYBOARD RELINQUISHES CONTROL
2287420
Figure 4-5
Keyboard Transmission Timing -- Aborted Transmission
4.4.1.3
Inhibited Keyboard Transmission.
Detection of a low
clock line during normal sampling inhibits keyboard transmission.
In this case, the keyboard retains any data that is ready to be
transmitted in its buffer and relinquishes control of the data
and clock lines.
Detection of a high clock line and a low data line also causes
any data that is ready to be transmitted to remain stored in the
keyboard buffer. In this case, after storing the data, the
keyboard prepares to receive a transmission from the system.
4.4.2 System Unit Transmission
Figure 4-6 shows a timing diagram for a typical system unit
transmission. A system unit transmission uses the same data
frame format as does a keyboard transmission. The keyboard
begins clocking the data out of the system unit within 15
milliseconds after initiation of a transmission. Each data frame
transmission requires a maximum of 2 milliseconds.
4-10
2241092-0001
BUSINESS-PRO Hardware Reference
A system unit transmission
following conditions:
Keyboard
can
occur
under
either
of
*
There is no keyboard transmission in progress. This is
indicated by the data and clock lines remaining in a
high state for longer than one clock period.
*
The keyboard is transmitting but has not reached the
tenth clock cycle.
In this case, the system unit can
force an abortion of the keyboard transmission, after
which the system transmission can begin.
the
A system transmission requires the following sequence of events:
1. The system unit sets the clock line low for more than
the clock period. The keyboard aborts any transmission
that has not reached the rising edge of its tenth clock
cycle
and
inhibits any transmission not already
started.
2. The system unit places the start element on the data
line (sets the data line low) and holds it in this
state while allowing the clock line to go high.
3. After recognizing the start element, the keyboard waits
a minimum of one half clock cycle, then sets the clock
line low.
4. During the low state of the clock, the system unit
places the first data bit on the data line and holds it
there until after the next falling edge of the clock.
The keyboard samples the data while the clock line is
high.
5. Step 4 is repeated until all eight data
parity bit have been transmitted.
6. The system unit places the stop
line (sets the data line high).
element
bits
on
and
the
the
data
7. The keyboard sets the clock line high. Then, while the
clock line is high, the keyboard sets and holds the
data line low until after the next rising edge of the
clock.
8. After generating one more clock period, the keyboard
turns off the output device of the clock line driver.
This relinquishes control of the clock line.
9. The system unit sets the clock line low and holds it
low for more than one clock cycle to inhibit further
transmission.
2241092-0001
4-11
Keyboard
BUSINESS-PRO Hardware Reference
SYSTEM BRINGS CLOCK HIGH
START ELEMENT IS READY TO BE SAMPLED
~K~EYBOARD
SYSTEM PULLS CLOCK LOW AND
INHIBITS
\.
PULLS CLOCK LOW
\ D BEGINS CLOCKING DATA
CLOCK
INHIBITl~~
DATA
I
~-H--nl
DATA BITO
I {il-____P.;..;A"-"RI;.;..TY-'--...I
SYSTEM PULLS DATA LOW
STOP
---IHI----
KEYBOARD PULLS DATA LOW
2287421
Figure 4-6
4.5
System Unit Transmission Timing
SYSTEM-TO-KEYBOARD COMMANDS
The system-to-keyboard commands are of two general
types:
single-byte commands and dual-byte commands.
The single-byte
commands consist of a command code that causes the keyboard to
perform
a
required function.
The dual-byte commands are
commands, such as the Set Typamatic Rate and Delay command,
for
which
the
system must provide an additional byte.
This
additional byte contains the required data.
4-12
2241092-0001
BUSINESS-PRO Hardware Reference
The system-to-keyboard
commands:
Keyboard
command
set
contains
the
following
*
Command code ECH
Set Key click Volume
*
Command code EDH
Turn Mode Indicator LEDs On/Off
*
Command code EEH
Echo
*
Command code EFH
No Operation
*
Command code FOH
No Operation
*
Command code FIH
No Operation
*
Command code F2H
No Operation
*
Command code F3H
Set Typamatic Rate and Delay
*
Command code F4H
Enable
*
Command code F5H
Default Disable
*
Command code F6H
Set Default
*
Command code F7H
No Operation
*
Command code F8H
No Operation
*
Command code F9H
No Operation
*
Command code FAH
No Operation
*
Command code FBH
No Operation
*
Command code FCH
No Operation
*
Command code FDH
No Operation
*
Command code FEH
Resend
*
Command code FFH
Reset
The
following
commands.
paragraphs
describe
the
system-to-keyboard
4.5.1 Set Key Click Volume Command
When the keyboard receives the command byte (ECH) of this dualbyte command, it responds by sending an Acknowledge command, then
waits for the data byte (Figure 4-7).
2241092-0001
4-13
BUSINESS-PRO Hardware Reference
Keyboard
The data
codes:
byte
contains
of the following key click volume
one
*
00
Key click off
*
01
Low key click volume
*
10
Medium key click volume
*
11
High key click volume
7
6
5
4
3
2
1
o
\-----------..fr-------LKEV
L..-.._ _
CLICK CODE
NOT USED (SET TO ZERO)
2287422
Figure 4-7
Set Key Click Volume Command Data Byte
4.5.2 Turn Mode Indicator LEDs On/Off Command
When the keyboard receives the command byte (EDH) of this dualbyte command, it responds by sending an Acknowledge command, then
waits for the data byte (Figure 4-8). The data byte contains
three data bits, each of which turns one of the three indicator
LEDs either on or off, depending on the state of the bit. A
high-level bit turns the associated LED oni a low-level bit turns
it off. After receiving the data byte, the keyboard responds by
sending an Acknowledge command and setting the indicator LEDs as
required by the data bits.
4-14
2241092-0001
Keyboard
BUSINESS-PRO Hardware Reference
7
6
5
4
3
2
1
o
l LL
.
SCROLL LOCK
NUM LOCK
CAPS LOCK
RESERVED BITS (SET TO ZERO)
2287423
Figure
4~8
Second Byte of the Indicator LED Command
4.5.3 Echo Command
When the keyboard receives the Echo command (EEH), it responds by
transmitting the Echo Response command (EEH) back to the system.
4.5.4 No Operation Command
When the keyboard receives one of the eleven No Operation
commands, it returns an Acknowledge command to the system and
performs no operation other than normal key detection.
2241092-0001
4-15
Keyboard
BUSINESS-PRO Hardware Reference
4.5.5 Set Typamatic Rate and Delay Command
When the keyboard receives the command byte (F3H) of this dualbyte command, it responds by sending an Acknowledge command, then
stops decoding switch closures while waiting for the data byte.
The data byte (Figure 4-9) provides the typamatic rate and delay
information.
Upon receiving the data byte, the keyboard returns
a second Acknowledge command then sets the typamatic delay and
rate
as
indicated by the data byte.
The delay is 250
milliseconds ±20 percent, times the binary value of bits 5 and 6.
The rate can be in the range of 2.0 to 30.0 characters per
second, as shown in Table 4-3.
7
6
5
4
3
2
1
o
LTYPAMATIC RATE
TYPAMATIC DELAY
RESERVED (SET TO ZERO)
2287424
Figure 4-9
Second Byte of the Set Typamatic Rate Command
2241092-0001
BUSINESS-PRO Hardware Reference
Table 4-3
Keyboard
Typamatic Rates
Rate Bits
Rate
(Changes/Second)
Rate Bits
Rate
(Changes/Second)
00000
30.0
10000
7.5
00001
26.6
10001
6.7
00010
24.0
10010
6.0
00011
21.8
10011
5.5
00100
20.0
10100
5.0
00101
18.4
10101
4.6
00110
17.1
10110
4.3
00111
16.0
10111
4.0
01000
15.0
11000
3.7
01001
13.3
11001
3.3
01010
12.0
11010
3.0
01011
10.9
11011
2.7
01100
10.0
11100
2.5
01101
9.2
11101
2.3
01110
8.6
11110
2.1
01111
8.0
11111
2.0
4.5.6 Enable Command
When the keyboard receives an Enable command (F4H), it responds
by sending an Acknowledge command, then it begins
normal
operation (scanning the keycodes).
4.5.7 Default Disable Command
When the keyboard receives the Default Disable command (F5H), it
responds by sending an Acknowledge command.
The keyboard then
clears the keyboard buffer, sets all conditions to their initial
default states, stops scanning keycodes, and awaits further
instructions.
2241092-0001
4-17
BUSINESS-PRO Hardware Reference
Keyboard
4.5.8 Set Default Command
When the keyboard receives a Set Default command (F6H), it
responds by sending an Acknowledge command.
The keyboard then
sets all conditions to their initial default states and continues
to scan keycodes.
4.5.9 Resend Command
The system issues the Resend command (FEH) in response to a
defective data frame from the keyboard. The Resend command must
be sent after a keyboard transmission is completed and before the
next transmission begins.
When the keyboard receives a Resend
command, it resends the last byte transmitted unless the last
byte was a keyboard-to-system Resend command.
In this case, the
keyboard sends the byte that was sent immediately prior to the
keyboard-to-system Resend command.
4.5.10 Reset Command
When the keyboard receives a Reset command (FFH), it responds by
sending an Acknowledge command and waits for the clock and data
lines to indicate that the system has accepted the Acknowledge
command. The keyboard then performs the basic assurance se1ftest, sets all conditions to their initial default states, and
clears the keyboard buffer.
4.6
KEYBOARD-TO-SYSTEM COMMANDS
The keyboard can send a limited number of commands to the system
to indicate certain status information. The keyboard-to-system
command set contains the following commands:
*
*
Command code OOH
Overrun
Command code AAH
Self-Test OK
*
Command code EEH
Echo Response
*
Command code FOH
Break Code Prefix
*
*
*
Command code FAH
Acknowledge
Command code FDH
Diagnostic Failure
Command code FEH
Resend
The following
commands.
paragraphs
describe
4-18
the
keyboard-to-system
2241092-0001
BUSINESS-PRO Hardware Reference
Keyboard
4.6.1 Overrun Command
The keyboard sends an Overrun command (OOH) to indicate to the
system that the keyboard buffer is full.
4.6.2 Self-Test OK Command
The keyboard sends the Self-Test OK command (AAH) to indicate
successful completion of the basic assurance self-test. The
system interprets any other command received while expecting a
Self-Test OK command as a keyboard failure.
4.6.3 Echo Response Command
The keyboard sends the Echo Response commmand (EEH) in response
to an Echo command (EEH) from the system.
4.6.4 Break Code Prefix Command
The Break Code Prefix command (FOH) is the first byte of a dualbyte sequence. This command-code byte precedes a make-code byte
to indicate that the associated key has been released.
4.6.5 Acknowledge Command
The keyboard sends an Acknowledge command (FAH) in response to
any valid command except for Echo or Resend. The Acknowledge
command indicates that the keyboard has received a command and
performed the required function.
If the keyboard is interrupted
while sending an Acknowledge command, it discontinues the command
transmission and accepts the new command.
4.6.6 Diagnostic Failure Command
The keyboard sends the Diagnostic Failure
indicate that either the basic assurance
periodic self-test has failed.
command (FDH) to
self-test or the
4.6.7 Resend Command
The keyboard sends the Resend command (FEH) in response
invalid input or an input containing incorrect parity.
4.7
to
an
KEYBOARD CONFIGURATIONS
Figures 4-10 through 4-18 show the keycap configurations that are
available for the BUSINESS-PRO keyboard.
2241092-0001
4-19
Keyboard
BUSINESS-PRO Hardware Reference
Caps
Lock
Num
L.ock
Scroll
Lock
DOD
1
I
Fl
F2
F3
F'
F5
F6
F7
F8
F9
FlO
F11
F12
.gUp
P90n
\
-,
--
!
1
#
$
%
A
&
2
3
4
5
6
7
Q
T.b
IA
Clrl
OShllt
All
@
*
8
(
)
+
9
a
-
IW IE IR IT IY IU I' 1° IP II
IS ID IF IG IH IJ IK IL I~ I;'
12 IX Ie IV IB IN 1M I~
I~
Back
.
Space
1\
I
lenter ...-J
I; IOShllt
Line
Send
Feed
Figure 4-10
•
Ina
end E..
• ..
Break
Print
Pause
0.1
Num
Lock
7
9
8.
Home
Home
5
1
2
End
0
Ins
t
Caps.
Lock
6
Req
PriSe
PgUp
4 ..
Sya
Scroll
I~
Bteak
.
-*
3
I
PoDn
+
0.,
Keycap Configuration -- Domestic
Capo Num Seton
LoCk Lock Lock
F2
Fa
F4
Ai
Fa
F7
PI
F9
FlO
%
&
.
5
8
7
8
,- ~ IQ IW IE IR IT IV IU II 1° IP Ii H I~
IA IS ID IF IG IH IJ r IL r I~I
..oQo..
IZ IX Ie IV IB IN 1M I~ I~ I~ l..oQo..shIft
o
F1
.
FI1
0
\
1
1
"
2
£
3
•
4
I
9
)
0
.-
-
+
Back
=
S..-
Ctrl
Enter
Shift
AI.
Una
Feed
Sond
Capo
Lock
=
= =
F12
Ins
Dol
Eoc
Num
Lock
PgUp PgDn
...
•
Home
t
End
8
7
Home
-4
5
1
End
2
....
0
•
t
Br....
Print
p-
='
•
~
Byo
Raq
.-
PgUp PrtSc
6
-
3
PgOn
+
Del
'2'"''
Figure 4-11
Keycap Configuration -- Germany
4-20
2241092~0001
Keyboard
BUSINESS-PRO Hardware Reference
Maj
Num
= =
Fl
F3
F2
F4
>
~
1
~&
@!
3
4
"
#
5
I
6
7
r!- ;,
B
!
9
~
.
0
•
I
=. IA IZ IE IR IT IV IU II 1° IP '7
F5
Fe
c.rI
F7
F8
"i)-
F8
F10
Aft
-
-
-
I:.
,; "
-
IQ IS ID IF IG IH IJ IK IL 1M I~ I ~
IW JX IC IV IB IN I~ I; I~ I~ I"i)J
Envoi
F11
+
~~~It
=
F12
+
Ins
Fin
•
"t
Break
Dal PauBe
Esc
Num
7
B
Sy.
9
4
5
1
Fin
2
3
+
6
t
0
In.
Maj
App
ttn
~
" •
- --
Print
Arret
',!,PE'
-t
+
Annul
"",,,
Figure 4-12
Keycap Configuration -- France
GroB. Num
Abbr
= = =
Fl1
Fl
F2
F3
F4
F5
F8
F7
F8
+-,
>1
2
'$
r3
4
%&
5
Bild
B
6
F12
+ Blld t
Ins
End
+
_
IV IX IC IV IB IN 1M
I:
I:
1::-
Pos1
_
Del
Break Print
Psusa
Eing Num Abbr Sys.
Losch t
Antr
Po.,.
1
8
9
Druck
Blld. •
4.,
5
6
I
"i)-
-
~F8--+F-'-0~--~A-It~-Un-a~--rL--~~--~--~~--~--~~--rL~-h-nd'-G-m-Bt--i---r--t--i~o~~-+--'+
Faad
Figure 4-13
•
Keycap Configuration -- Italy
f
2241092-0001
4-21
Einfg
LOsch
BUSINESS-PRO Hardware Reference
Keyboard
Caps
Num Scroll
Lock
Lock
= =
Fll
Fl
F3
F2
~
i
~1
I~
#
~3
$
4
%
5
I
+
&
F12
PgUp PgDn
6
End
F6
F7
F6
F9
FlO
Ins
Del
:::~
Print
Esc
Num
~~~~II
Sys
8
9
7
F4
F5
Lock
=
Lock ~ Req
+
Home
5
..
Home
2
t
o
Send Caps
Lock
Line
Feed
~rtSc
..
1
End
Alt
PgUp
6
3
PgDn
Del
Ins
Keycap Configuration -- Norway
Figure 4-14
Bloc
Bloc
Bloc
Mai
Num
Scorr
= = =
Fl
F2
>
!
-
1
ff-
F3
F4
0-
F5
F6
Clrl
F7
F8
F9
FlO
~
ALT
"
2
£:
3
$
4
%
5
&
I
(
)
=
6
7
8
9
0
?
A
§
U
i
IQ IW IE IR IT IV IU II 1° IP It I:
IA IS 10 IF IG IH IJ IK IL I? I!
IZ IX Ie IV IB IN 1M I: I: I~ I~
I
llmmissJ
Saito
Riga
Figure 4-15
F11
Ins
F12
AvPg RitPg
Fine
7
-
Riter
--
Bloc
Mai
4
5
1
2
Fine
0
Ins
Break
Print
Pause
Bloc Bloc Rich
Sist
Num ~
In.
Riter 8
+
I
Send
Est:
Del
+
9
RitPg Stam
6
3
t
-
-
AvPg
+
Cane
Keycap Configuration -- Spain
4-22
2241092-0001
Keyboard
BUSINESS-PRO Hardware Reference
Caps
Num
Scroll
Lock
Lock
Lock
Cl
0
o
Fl
F2
F3
F4
F5
F8
F7
Fa
>
,, ,.
<
\
%
&""6(*)
)?_,
(=
+* . .
B.ck
F12
Fll
PgUp
In.
PgDn
End
Esc
+-I="Spaca
1
Lock
-a.
Scroll
Sys
Req
7
Home
..
Hom.
IZ IX Ie ]V IB lN 1M I: 1: :IOShlfl
OShIIt
Print
Num
...
t
4
...
5
6
1
2
3
...
End
•
PgDn
~F-e~~F-l0~---+-A-II-r-Lln-.~--~---L---L--~--~--L-~---L---L~r--'-so-n-dr-C'-P.~--~--t---r--i~o--~--r.~--I'+
~
22e1~1
~
~
z
Keycap Configuration -- Sweden
Figure 4-16
Caps
Lock
Num
Lock
Cl
Fll
Fl
F2
F3
F4
F5
F6
F7
Fa
Fe
FlO
>
:
<
\ 1
~
!
"
2
3
#
S
%
"
4
5
6
A
I
7
" (a *
)
tA lS /D
IF IG IH IJ
IZ IX Ie IV IB IN
OShfll
(
) ?
=
9
-
+ -
0
10
IQ IW I E I R I T I Y I U II
Clrt
All
@ £
I P IA
\
I
+
=
iF-
*, ,
jI
-
I:
Send
Feed
PgDn
Space
1° :1)( ':lenlorJ
1: :IOShllt
Lina
PgUp
Caps
Lock
+
.-
Scroll
Lock
Cl
F12
Back
IK IL
1M
0
Home
t
Ins
end
..
Num
esc Lock
7
2241092-000).
Scroll
I Lock
Home
8+
4
.-
5
6
1
end
2
3
0
In.
Keycap Configuration -- Switzerland
4-23
Break
Pause
Break
9
PgUp
2287314
Figure 4-17
Dol
t
Print
SY.
Roq
PrtSe
*
... -
PgDn
Dol
+
Keyboard
BUSINESS-PRO Hardware Reference
Caps
Lock
Num
Lock
Scroll
Lock
CJ
CJ
t:J
F11
F1
F2
>
p.--
!
1
\
F3
F4
F5
F6
F7
F8
?
"2
\
£
.-Back
1-'::-+:':---1$
@
F12
Pgup PgDn
...
IV IX Ie IV IB
End
Esc:
0.,
:~:~~
Print
Num
-a-
Sys
Lock
Space
+
OShif1
Ins
IN 1M I: I~ 17 IOShif1
Home
t
Scroll
Req
7
Home
.. - ..
4
5
1
2
End
6
t
-
3
PgD"
~F-9-4-F-'0-+-~-AI-t~li-n.-r~~--L-~--L-~---L--~~~~--~~~s--~C.-P.~--+--4~-+--~o--~-4~~+
Feed
end
Lock
Ins
Del
2287313
Figure 4-18
Keycap Configuration -- United Kingdom
4-24
2241092-0001
BUSINESS-PRO Hardware Reference
Floppy Disk Drive Controller
Section 5
Floppy Disk Drive Controller
5.1
GENERAL
The standard BUSINESS-PRO floppy disk drive subsystem consists of
a four-drive floppy disk controller and a 1.2-megabyte floppy
disk drive.
This section describes the floppy disk drive
subsystem.
NOTE
The 1.2-megabyte and 360-kilobyte disk drives
are options that can be used with the floppy
disk controller. These drives are described
in Section 6 of this manual.
5.1.1 Floppy Disk Controller
The floppy disk controller is an 8-bit peripheral controller
board that can control both high-capacity (1.2 megabyte) and lowcapacity (360-kilobyte) floppy disk drives.
The controller
contains the logic devices required for generating control
signals
and
handling
data, control, and status transfer
operations between the floppy disk drive subsystem and the host.
These logic devices comprise the following controller circuits:
*
Floppy disk drive interface
*
Host I/O interface and control logic
*
Host DMA interface and control logic
*
Floppy disk controller logic
*
Write precompensation logic
*
High-density and low-density data separators
Appendix E ·contains a logic diagram (Drawing No.
2240921) for
the floppy disk controller. The following paragraphs describe
the floppy disk controller functions.
2241092-0001
5-1
Floppy Disk Drive Controller
BUSINESS-PRO Hardware Reference
5.1.1.1 Floppy Disk Drive Interface. The floppy disk controller
can interface from one to four 1.2-megabyte or 360-kilobyte disk
drives via I/O connectors on the controller
board.
The
controller connectors and their interfaces are as follows:
4
*
J3 (standard usage)
*
J4 (optional
(SWl-3 ON)
*
J5 (optional usage) -- external
(SWl-3 OFF)
usage)
internal disk drives A and B
internal
disk
disk drives C and D
drives
C
and
D
Figure 5-1 is a functional block diagram of the floppy disk
controller. Figure 5-2 is a simplified block diagram of the
interface of the controller connectors to the disk drives.
5-2
2241092-0001
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TI PART NO. 2240922-0001
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REQUIRES USER SUPPLIED
EXTERNAL CHASSIS AND
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PRO-LITE COMPUTER
(OPTIONAL)
2287494
USER-SUPPLIED
(OPTIONAL)
Floppy Disk Drive Controller
BUSINESS-PRO Hardware Reference
Low-impedance ribbon cables connect interface signals between the
three 1/0 connectors on the controller board and the disk drives
via a series of buffers and receivers on the controller.
All
signals for connectors J4 and J5 are controlled through a common
set of drivers, but connector J3 uses a separate set of drivers.
All three connectors have separate receivers and terminating
resistors.
Connectors J3 (standard internal interface) and J4 (optional
internal interface) use 34-pin ribbon cables to connect from one
to four disk drives, mounted internally in the system unit.
The
ribbon cable from connector J3 connects to the first two drives,
which are designated A and B. Drive A is mounted in the top of
the chassis with its drive select 0 jumper installed and its
terminating resistors installed.
If drive B is installed, it is
mounted below drive A with its drive select 1 jumper installed
and its terminating resistors disabled.
Connector J4 is identical to connector J3 except for the drive
select signals which are configured for drive select 2 and drive
select 3 jumpers on the disk drives. These drives are designated
C and D. Drive C is mounted just below drive B with the drive
select 2 jumper installed and the terminating resistors enabled.
The second drive connected to connector J4 is designated drive D
with
its drive select 3 jumper installed and terminating
resistors disabled.
Connector J5 (if used) mates with a 37-pin, D-type connector
which is compatible with the PC-XT expansion floppy disk drive
connector. Two optional external disk drives, designated C and
D, or a PRO-LITE computer expansion cable can be.connected to J5.
NOTE
Any time connector J5 is used for external
configurations, SWl-3 must be set to OFF.
The pinouts for connectors J3 and J4 of the floppy disk
controller are shown in Tables 5-1 and 5-2, respectively. The
pinouts for connector J5 are shown in Table 5-3.
The J5
connector is a 37-pin, D-type connector accessible from the back
panel of the system unit.
2241092-0001
5-5
BUSINESS-PRO Hardware Reference
Floppy Disk Drive Controller
Table 5-1
Internal Floppy Disk Controller Connectors J3
------------------------------------------------------------------,
Signal Return
Signal
Function
Pins
Pins
Name
Source
LOWl-
System
High density=l, low density=O.
2
1
4
3
8
7
INDXl-
Floppy
Indicates index hole.
10
9
DSl-
System
Drive select 1.' \
12
11
DS2-
System
Drive select 2. "] D£1-
16
15
MOENI
System
Drive motors on.
18
17
DIRl-
System
Step in/out direction.
20
19
STEPl-
System
Step in/out command.
22
21
WDATAl-
System
Serial data to drive.
24
23
WEl-
System
Low enables writing
to floppy disk.
26
25
TKOOl-
Floppy
Low indicates head
is over track 00.
28
27
WPl-
Floppy
Indicates disk is
write-protected.
30
29
RDATAl-
Floppy
Serial data from
drive.
32
31
HSLl-
System
Side select; high=O,
low=l.
34
33
DCHGl-
Floppy
Indicates media change
for high-density drive.
Not used.
5-6
ij()M..O
Db
o~
, - OS!
2241092-0001
BUSINESS-PRO Hardware Reference
Table 5-2
Signal
Pins
Return
Pins
Floppy Disk Drive Controller
Internal Floppy Disk Controller Connectors J4
Signal
Name
Source
Function
------------------~----------------------------------- -------------
2
1
LOW2-
System
High density=l, low density=O.
4
3
6
5
DS4-
System
Drive select 4.
8
7
INDX2-
Floppy
Indicates index hole.
14
13
DS3-
System
Drive select 3 .
16
15
MOEN2
System
Drive motors on.
18
17
DIR2-
System
Step in/out direction.
20
19
STEP2-
System
Step in/out command.
22
21
WDATAl- System
Serial data to drive.
24
23
WE2-
System
Low enables writing
to floppy disk.
26
25
TK002-
Floppy
Low indicates head
is over track 00.
28
27
WP2-
Floppy
Indicates disk is
write-protected.
30
29
RDATA2- Floppy
Serial data from
drive.
32
31
HSL2-
Side select; high=O,
low=l.
Not used.
System
-~----------~----------------------~-------------------------------
2241092-0001
5-7
Floppy Disk Drive Controller
BUSINESS-PRO Hardware Reference
Table 5-31 External Interface for Floppy Disk Controller, J5
Signal
Pins
Return
Pins
Signal
Name
Source
Function
20
Not used.
21
Not used.
LOW3-
System
Low speed mode=O,
high speed mode=l.
}/
22
4
23
Not used.
5
24
Not used.
INDX3. MOEN3-
vo
31
Indicates index hole.
System
Enables drive motor 3.
(" DS4-
0'0 \ System
Enables drive select 4.
(
01..\ "- jsystem
Enables drive select 3.
D£3-
\~.MOEN4-
(12
.~~
Floppy
~ ,. System
Enables drive motor 4.
DIR3-
System
Step in/out direction.
STEP3-
System
Step in/out command.
WDATA3-
System
Serial data to drive.
"{i'
~
33
WE3-
System
Low enables writing to
floppy disk drive.
?{p
34
TK003-
Floppy
Low indicates head is
over track 00.
v(
35
WP3-
Floppy
Indicates drive is
write-protected.
Q-7\
7/
-'
Vo
36
RDATA3-
Floppy
Serial data from drive.
(iJ}
I,v
37
HSL3-
System
Side select; high=O,
low=l .
37
DCHG3-
Floppy
Indicates media change
for high-density drive.
.x{
5-8
2241092-0001
Floppy Disk Drive Controller
BUSINESS-PRO Hardware Reference
Floppy Disk Controller Interface to PRO-LITE Computer. Connector
J5 on the floppy disk controller can also be connected to an
external cable for use with the PRO-LITE computer.
In this
configuration the PRO-LITE disk drive is used as the third drive
of the BUSINESS-PRO computer. The diskette used with the PROLITE must be formatted for 40 tracks on the PRO-LITE computer.
(The BUSINESS-PRO computer does not support the 720-kilobyte
microfloppy disk drive.)
To use the PRO-LITE with the BUSINESS-PRO computer,
following steps:
perform
the
1. Connect a modified cable (TI Part Number 2227210-0001)
between J5 on the floppy disk controller and the PROLITE computer.
(Be sure to use the grey-colored cable
because the ground lines are twisted to eliminate
noise.)
2. On the floppy disk controller, set switch SWl-3 to
to enable the external drive connector (J5).
OFF
3. Reboot the PRO-LITE computer. The message SYSTEM ERROR
0030 is displayed on the PRO-LITE screen to indicate
the external drive cable is detected and the PRO-LITE
is configured as the third drive of the BUSINESS-PRO
computer.
4. Reboot the BUSINESS-PRO with MS-DOS 3.05 or greater.
The PRO-LITE drive indicator should flash on and then
off during boot.
5. If you have not already done so, run the BUSINESS-PRO
setup program to select the PRO-LITE as drive C and/or
D.
Make sure you do not receive any
CMOS
or
configuration errors during power-up tests.
6. Format a diskette for 40 tracks, as follows:
To format the diskette on the PRO-LITE, use MS-DOS 2.12
(or greater) commands.
CONFIG A:
2,40 (Configures
double-sided drive.)
drive
A as a 40-track,
FORMAT A:
(Formats the diskette in drive A
track diskette.)
2241092-0001
5-9
as
a
40-
BUSINESS-PRO Hardware Reference
Floppy Disk Drive Controller
5.1.1.2
Host I/O Interface and Control Logic. Connector Pl on
the floppy disk controller board carries the interface signals
between the host and the controller. The host I/O interface
contains the following circuits and devices:
*
Address decode logic
*
DMA interface and control logic
*
Floppy disk controller IC
*
Floppy disk write precompensation
*
Data separators
Address Decode Logic. The address decode logic decodes expansion
bus address lines XAO through XA9 to provide one of two unique
I/O base addresses for the controller board. These I/O base
addresses are in the range of 03F2H through 03F7H (primary), or
0372H through 0377H (alternate). SW2 selects between the primary
address range (SW2 OFF) and the alternate address range (SW2 ON).
The PAL device decodes the individual read/write ports within the
selected
base address and either enables or disables the
expansion data bus transceiver. A buffer provides buffering for
the following expansion bus lines:
*
Address line XAO
*
I/O write line IOWC-
*
I/O read line IORD-
The digital output register is selected via primary I/O base
address 03F2H or alternate I/O base address 0372H as shown in
Table 5-5.
A power-up operation clears the register output
lines. All of these lines are active high except bit 2 (FRST).
A power-up operation sets this line low to reset the floppy
controller IC. This line must be set high before the floppy
controller IC can be accessed. Bits 0 and 1 (DRL and DRH) select
1 of up to 4 floppy disk drives, depending upon the system
configuration. Bit 3 (DMAEN) enables· buffer U12 to gate the
floppy interrupt (FINT) and the device request (LDRQ) onto the
expansion bus level 6 interrupt (IR06) and device request (DRQ)
lines, respectively. Bits 4 througb 7 (MOENl through MOEN4) are
the motor enable lines for floppy disk drives 1 through 4,
respectively.
Each of these lines turns on the motor of its
associated drive.
Primary ports 03F4H and 03F5H and alternate ports 0374H and 0375H
reside in the floppy disk controller IC. Port 03F4H or 0374H is
a
read-only register that provides controller/drive status
information to the host.
The host can access this status
register at any time. Port 03F5H or 0375H is the controller data
5-10
2241092-0001
Floppy Disk Drive Controller
BUSINESS-PRO Hardware Reference
register.
This register stores data and command information, as
well as parameter and status information, for the floppy disk
drives.
Access to this register provides programming for the
subsystem and allows determination of the result of any issued
command.
Writing a binary value of 00 to bits 0 and 1 of port 03F7H or
0377H selects the high-capacity operating mode.
This operating
mode results in the following conditions:
*
Floppy disk
minute (rpm)
*
Data separation rate -- 500 kilobits per second
*
Floppy disk controller IC clock frequency -- 8 megahertz
*
Write clock frequency -- 1 megahertz
drive
motor
speed -- 360 revolutions per
Writing a binary value of either 01, 10, or 11 to bits 0 and 1 of
port 03F7 or 0377 selects the low-density operating mode.
This
operating mode results in the following conditions:
*
*
*
*
Floppy disk drive motor speed -- 300 rpm
Data separation rate -- 250 kilobits per second
Floppy disk controller IC clock frequency -- 4 megahertz
Write clock frequency -- 500 kilohertz
The host can read bit 7 of primary port 03F7 or alternate port
0377 to determine if a disk change has occurred in the selected
floppy disk drive. The remaining bits (0 through 6) are used by
the Winchester controller.
This sharing of the port between the floppy disk controller and
the Winchester controller requires that this port be handled
differently fr~m the other controller ports. When the host reads
this port, the floppy disk controller IC disables the expansion
bus data transceiver, latches the media-change signal (DCHG) at
latch U8 at the beginning of the read cycle, then gates the
signal onto bit 7 of the expansion data bus via U7. When the
host reads other ports on the controller board, U7 is placed in
its tristate condition, and the expansion data bus transceiver is
enabled.
Host DMA Interface and Control Logic. The host DMA interface and
control logic PAL provide the DMA interface signals, signals for
selecting internal or external floppy disk drives 3 and 4, and
other signals for selecting either the high-density or the lowdensity operating modes.
2241092-0001
5-11
Floppy Disk Drive Controller
BUSINESS-PRO Hardware Reference
During DMA operations to the f19PPY disk drive, the PAL device
generates the floppy disk acknowledge (FDACK-) signal in response
to the DMAEN signal from the floppy disk controller and the
DACK2- signal from the host DMA controller. FDACK- enables the
expansion bus data transceiver and provides the device-request
enable signal to the floppy disk controller IC. The terminal
count signal is gated with DACK2- to generate the FTC signal.
This signifies the end of the DMA data transfer operation.
An active EN3/4- signal enables either the external drive
connector (J5) or the internal drive connector (J4), depending
upon the position of SWl-3. Its OFF position enables J5; its ON
position enables J4.
CAUTION
Changipg the position of SWl-3 switches the
input . signals from the drive. It does not
switch the output signals, making it possible
to inadvertently write data to the wrong
disk.. To avoid this possibility, drives
should never be connected to connectors J4
and J5 at the same time.
The mode-select signals (MDSEL and MDSEL-) select eithert.he
high-density or low-density operating mode.
The conditions of
these signals are determined by writing to bits 0 and l a t I/O
port address 03F7H. A binary value of 00 written to this address
sets MDSEL low and MOSEL- high, thus selecting the hi'gh-density
mode.
Writing any other value to this address sets MOSEL high
and MDSEL- low (low-density mode).
Floppy Disk Controller IC. The floppy disk controller handles
data transfer and control operations between the host and the
floppy disk drive. It provides such high-level functions as
serial/parallel
data
conversion,
sector
location,
seek
operations, and disk formatting.
The floppy disk controller's internal clock
frequency
is
controlled by software and can be changed by writing to I/O port
address 03F7H. During high-density operations, the controller
operates at a clock frequency of 8 megahertz to provide a data
transfer rate of 500-kilobits per
second.
For
standard
minifloppy drives with a data transfer rate of 250-kilobits per
second, the clock frequency is set to 4 megahertz.
Floppy Disk Write precompensation. An inherent characteristic of
double-density recording is a condition called bit shift, which
results when cer~ain ~ata patterris are written to a disk. This
bit shift condition tends to move the read data transitions
outside the normal range of the read circuitry, and the condition
5-12
2241092-0001
BUSINESS-PRO Hardware Reference
Floppy Disk Drive Controller
grows progressively worse as the heads move inward toward the
shorter track lengths near the center of the disk.
Optimized write precompensation is provided by shifting the write
data to the disk by a value of 125 nanoseconds. The direction of
the shift is determined by PSO and PSl signal lines of the NEC
controller.
The write precompensation logic uses these lines
from the floppy disk controller IC to shift the data as follows:
Direction of
Shift
PSO
PSI
Normal
o
o
No shift
Late
o
1
125 nanosecond delay
Early
1
o
-125 nanosecond delay
Invalid
1
1
Invalid
Comments
Data Separators.
The floppy disk controller has two
data
separators:
one used for high-density transfer rates (500K bits
per second) and one used for low-density transfer rates (250K
bits per second). These data separators, which work identically,
synchronize the read clock with the read data pulses during data
recovery operations by providing a continuous clock locked in a
phase relationship with the read data.
The circuitry for the data separators is shown on sheets 9 and 10
of the logic diagram located in Appendix E. The data separators
consist of components U23, U26, U27, U28, and U30. U23 is a oneshot multivibrator, with one-half used for high and one-half used
for low data densities. This one-shot multivibrator is used to
shorten and stabilize the pulse width of the incoming read pulses
so that the phase-locked loop (PLL) and data recovery operations
perform properly during the lockup interval.
For the highdensity mode, the one-shot multivibrator fixes the the incoming
read data pulses at 189 nanoseconds, plus or minus 10 percent.
For the low-density mode the incoming read data pulses are fixed
at 392 nanoseconds, plus or minus 10 percent.
The WD1691 at locations U27 (high density) and U28 (low density)
is used to implement a phase-locked loop with U30 (shown on sheet
10 of the logic diagram located in Appendix E), which is the
voltage controlled oscillator (VCO). Other external components
provide the loop filter.
The phase-locked loop provides a
continuous clock that is locked in a specific phase relationship
with transitions in the incoming data. For this system, the
falling edge of the RDDATA- signal should be nearly centered on
the high or low pulse of the RDCLK signal. Data is valid in
2241092-0001
5-13
Floppy Disk Drive Controller
BUSINESS-PRO Hardware Reference
either half of the RCLK signal, but data pulses in adjacent
cycles of the RCLK signal are not allowed.
half
U30 is a dual voltage controlled oscillator with separate enable
signals for each half, ensuring that the two VCOs do not
interfere with one another. While the VCO is operating in the
high-density mode, the half of the VCO for the low-density mode
is disabled, and vice versa. To provide the best capture range
and lock stability, the free-running frequency of the VCO (with
the FC input at pins 1 and 2 of U30 at 1.3 volts, RDDATA- high)
is 4.0 megahertz for high density and 2.0 megahertz for low
density at the Fa output pins. These frequencies are preset at
the factory by adjusting trim pots at R20 (high density) and R19
(low density).
If it is necessary to change the adjustments,
perform the following steps:
1. Ensure RDDATA- is high. This forces the PU and PD
signal lines from U27 and U28 to a tristate condition.
2. Measure the voltage on the FC signal lines with a
device having greater than a 5-megohm input impedance.
This should be 1.3 volts, plus or minus 5 percent.
3. Measure and/or adjust the VCO frequency on
signal lines of U30 (if necessary) as follows:
the
Fa
a. For high density. Measure the frequency at pin
10 of U30 and adjust R20 (if necessary) to obtain
4.0 megahertz, plus or minus 5 percent. When the
adjustments are made correctly, the PLL should be
able to lock up to an incoming pulse train with
the frequency between 425 kilohertz and 575
kilohertz (plus or minus 15 percent) within 150
microseconds. The pulses should be low-going, 2
microseconds maximum, applied to the RDDATAinput (pin 30 of J3 or J4, or pin 17 of J5).
b. For low density. Measure the frequency at pin 7
of U30 and adjust R19 (if necessary) to obtain
2.0 megahertz, plus or minus 5 percent. When the
adjustments are made correctly, the PLL should be
able to lock up to an incoming pulse train with
the frequency between 212 kilohertz and 287
kilohertz (plus or minus 15 percent) within 150
microseconds.
The pulses should be low-going, 2
microseconds maximum, applied to the RDDATAinput (pin 30 of J3 or J4, or pin 17 of J5).
The output generated by the PLL is the read data clock on pins 12
of U28 and U30. These clock lines, one for high density and one
for low density, are fed to a multiplexer where either one can be
selected by MDSEL as the read data clock (RCLK) and supplied to
the NEC765A floppy disk controller IC (pin 22 of Ull on sheet 5
of the logic diagram).
Signal line RD765 from
the
U26
5-14
2241092-0001
BUSINESS-PRO Hardware Reference
Floppy Disk Drive Controller
multiplexer is read data, containing clock and data bits supplied
to pin 23 of Ull as RDATA.
Both the high-density and low-density separators are capable of
working with either· single-density (FM) or double-density (MFM)
data.
The choice is controlled by the MFM line (logic 0 for
single density and logic 1 for double density) from the NEC765A
floppy disk controller IC, which is the data density (DDEN)
input, to pin 15 of U27 and U28.
5.1.2 Floppy Disk Controller Programming Information
The main system processor has access to several internal data and
status registers in the floppy disk controller IC.
5.1.2.1 Floppy Disk Controller IC Internal Registers.
The
uPD765A floppy disk controller IC, located on the floppy disk
controller board, has several internal registers consisting of
data
registers,
status
registers, control registers, and
input/output registers. The functions and I/O port address of
these registers are described in the following paragraphs.
Data Registers and I/O Port Addresses.
The 8-bit data register
(which actually consists of several registers in a stack with
only one register presented to the data bus at one time) stores
data, commands, and parameters and provides floppy disk drive
status information. Data bytes are written into and read out of
the data register in order to obtain the results after a
particular command.
An I/O address map of the floppy disk controller, along with the
register functions at each address, is shown in Table 5-4.
Functions of the bit positions in the registers at each I/O port
address are listed in Tables 5-5 through 5-8.
Table 5-4
Floppy Disk Controller I/O Port Address Map
I/O Port Addresses
Primary Secondary
(Hexadecimal)
Read Registers
write Registers
Digital output
3F2
372
3F4
374
Main
3F5
375
Floppy disk data
Floppy disk data
3F7
377
Digital input
Floppy disk control
Interrupt request level
2241092-0001
sta~us
=
Main status
6; DMA request level
5-15
.=
2
Floppy Disk Drive Controller
Table 5-5
Bit
3F2
BUSINESS-PRO Hardware Reference
Digital Output Register Bits
Signal
Function
0
DRL
Drive select (low bit)
1
DRH
Drive select (high bit)
2
FRST
Function reset
3
DMAEN
Enables interrupts and DMA
4
MOENl
Enables drive A motor
5
MOEN2
Enables drive B motor
6
MOEN3
Enables drive C motor
7
MOEN4
Enables drive D motor
DRH
0
DRL
0
0
1
1
1
0
2
1
1
3
5-16
Drive Selected
0
2241092-0001
BUSINESS-PRO Hardware Reference
Table 5-6
Bit
3F4H
Floppy Disk Drive Controller
Main Status Register
Function
0
Drive A busy/seeking
1
Drive B busy/seeking
2
Drive C busy/seeking
3
Drive D busy/seeking
4
Floppy busy command in
progress
5
Non-DMA mode
6
Data transfer direction
(high=floppy to host)
7
Master-data-register ready
request
Table 5-7
Bits
o
I
3F7H
Floppy Disk Diagnostic Register
Function
Apply to currently selected Winchester drive
6
7
2241092-0001
Diskette change
5-17
Floppy Disk Drive Controller
Table 5-8
3F7H
Bit
BUSINESS-PRO Hardware Reference
Floppy Disk
Register
Function
0
LDO
Mode select low bit
1
LDI
Mode select high bit
2
Not used
3
Not used
4
Not used
5
Not used
6
Not used
7
Not used
NOTE:
The mode select bits are used to select between high-capacity disk
drive mode and low-capacity mode, as follows:
LD1
LDO
o
o
High-capacity (500K bps)
o
1
Low-capacity (250K bps)
1
o
Low-capacity (250K bps)
1
1
Low-capacity (250K bps)
Mode
5-18
2241092-0001
BUSINESS-PRO Hardware Reference
Floppy Disk Drive Controller
5.1.2.2 Controller Commands. The uPD765A floppy disk controller
IC performs 15 different commands, as follows:
*
Read Data
*
Read Deleted Data
*
Write Data
*
Write Deleted Data
*
Read a Track
*
Read ID
*
Format a Track
*
Scan Equal
*
Scan Low or Equal
*
Scan High or Equal
*
Recalibrate
*
Sense Interrupt Status
*
Specify
*
Sense Drive Status
*
Seek
*
Invalid Command
Each command is initiated by a multibyte transfer from the
processor.
The results after execution of the command can also
be a multibyte transfer back to the processor. Because of this
interchange between the processor and the floppy controller, each
command consists of three phases, as follows:
*
Command phase
The processor writes a sequence of
commands to the floppy
controller
directing
the
controller to perform a specific operation.
*
Execution phase
specified operation.
*
Result phase -- When the operation completes, status and
other information are available to the processor through
a sequence of read commands.
2241092-0001
The floppy controller performs the
5-19
Floppy Disk Drive Controller
BUSINESS-PRO Hardware Reference \
Listed below are the codes required to execute each command. The
symbols used in the command phase and result phase are defined in
Table
5-9, which follows the command descriptions.
An X
indicates a don't-care condition.
Read Data.
Command Phase:
MT
X
MF
X
SK
X
0
X
0
X
1
I
HD USI
0
usa
(C,H,R,N,EOT,GPL,DTL)
Result Phase:
(STO,STI,ST2,C,H,R,N)
Comment: The host outputs the nine command phase bytes.
The
floppy disk controller selects the drive, loads the drive heads
(if previously unloaded), and begins reading ID address marks and
ID data fields to locate the selected sector. When the sector is
found, data is transferred (via DMA) to host memory. Multisector
and multitrack operation is allowed. Completion of the command
updates
the result phase registers, interrupts the system
processor (if interrupt is enabled), and unloads the heads
following the head unload interval.
Read Deleted Data.
Command Phase:
MT
X
MF
X
SK
X
0
X
I
X
100
HD USl usa
(C,H,R,N,EOT,GPL,DTL)
Result Phase:
(STO,STI,ST2,C,H,R,N)
Comment:
The Read Deleted Data command and the Read a Track
command are the same except for the command opcode.
The Read
Deleted Data transfers sectors that contain the deleted data
address mark.
5-20
2241092-0001
BUSINESS-PRO Hardware Reference
Floppy Disk Drive Controller
write Data.
Command Phase:
MT
X
MF
X
0
X
00101
X X HD USl usa
(C,H,R,N,EOT,GPL,D1L)
Result Phase:
(STO,ST1,ST2,C,H,R,N)
Comment: The host outputs the nine command phase bytes and the
floppy disk controller selects the drive, loads the heads, and
searches the sector ID fields. When the C,H,R, and N sector
fields match the command register data, the controller transfers
byte data via DMA to the drive.
Command completion updates the
result registers and interrupts the host processor.
Write Deleted Data.
Command Phase:
MT
X
MF
X
0
X
o
1
X X
o
0
1
HD USl USO
(C,H,R,N,EOT,GPL,DTL)
Result Phase:
(STO,ST1,ST2,C,H,R,N)
Comment:
The Write Deleted Data command is the'same as a normal
write operation, except that a deleted data address mark is
written as the beginning of the data field in place of a normal
data address mark.
Read a Track.
Command Phase:
o
MF
SK
0
0
X
X
X
X
X
010
HD USl usa
(C,H,R,N,EOT,GPL,DTL)
Result Phase:
(STO,ST1,ST2,C,H,R,N)
Comment: The Read a Track command and the Read Deleted Data
command are the same except the Read a Track command transfers
all sectors from the index mark through the end of track sector.
2241092-0001
5-21
Floppy Disk Drive Controller
BUSINESS-PRO Hardware Reference
Read ID.
o
Command Phase:
MF
0
X
X
X
Result Phase:
01010
X X HD USl USO
(STO,ST1,ST2,C,H,R,N)
Comment: The first correct 10 information on the cylinder is
stored in the data register. Sector 10 information is read from
the floppy disk during the execution phase.
Format a Track.
Command Phase:
0
MF
X
X
01101
X X HD USl usa
0
X
(N,SC,GPL,D)
Result Phase:
(STO,ST1,ST2,C,H,R,N)
Comment: The selected track is formatted from the index mark
through the last track sector with address marks, ID fields, data
fields,
and field gaps for either the standard single-density or
double-density format.
The 10 field (4 bytes) is furnished by
the host for each sector. The data field is filled with the data
defined in the command register (DTF).
Scan Egual.
Command Phase:
MT
X
MF
X
SK
X
1
X
0
X
0
0
HD USl
1
usa
(C,H,R,N,EOT,GPL,STP)
Result Phase:
(STO,ST1,ST2,C,H,R,N)
Comment: The selected sector is compared on a byte basis between
the drive information and the host data.
If the scan condition
is satisfied, the SH (Scan Equal Hit) bit is set in status
register 2.
5-22
2241092-0001
Floppy Disk Drive Controller
BUSINESS-PRO Hardware Reference
Scan Low or Equal.
Command Phase:
MT
X
MF
X
SK
X
1
X
1
X
0
0
HD US1
1
usa
(C,H,R,N,EOT,GPL,STP)
Result Phase:
(STO,ST1,ST2,C,H,R,N)
Comment:
The Scan Low or Equal command is similar to the Scan
High or Equal command, except for the logical compare condition.
If the condition is not satisfied, the SN (Scan Not Hit) bit is
set in result register ST2.
Scan High or Equal.
Command Phase:
MT
X
MF
X
SK
X
1
X
1
X
1
0
HD US1
1
usa
(C,H,R,N,EOT,GPL,STP)
Result Phase:
(STO,ST1,ST2,C,H,R,N)
Comment: The Scan High or Equal command is sim1iar to the Scan
Low or Equal command, except for the logical compare condition.
If the scan condition is not satisfied, the SN (Scan Not Hit) bit
is set in result register ST2.
Reca1ibrate.
Command Phase:
o
X
0
X
0
X
0
X
011
X 0 US1
1
usa
Comment: The heads of the selected drive are retracted to track
position O. The track 0 position flag is available as a separate
signal from the selected drive and in the ST3 status byte.
2241092-0001
5-23
Floppy Disk Drive Controller
BUSINESS-PRO Hardware Reference
Sense Interrupt Status.
Command Phase:
000
Result Phase:
(STO,PCN)
0
1
0
0
0
Comment:
Controller status register 0 and~the current cylinder
are available in the result registers following this command.
The command clears the floppy section interrupt level.
Specify.
Command Phase:
000
0
0
0
1
1
(SRT,HUT,HLT,ND)
Comment:
The Specify command sets the head load and unload
rates, the drive step rate, and the DMA data transfer mode.
Sense Drive Status.
Command Phase:
o
X
Result Phase:
0
X
0
X
0
X
0
X
1
0
HD USI
0
usa
(ST3)
Comment: This command returns selected drives status ST3
the result phase.
during
Seek.
Command Phase:
o
X
0
X
0
X
0
X
1
X
1
1
HD USI
1
usa
(NCN)
5-24
2241092-0001
BUSINESS-PRO Hardware Reference
Floppy Disk Drive Control leI
Comment:
This command positions the read/write head over thE
proper cylinder on the diskette.
The controller compares thE
current head position with NCN and if there is a difference,
issues step pulses in the proper direction to reach NCN.
Wher
the present cylinder number (PCN) is equal to NCN, the control leI
sets the Seek End flag to STO and terminates the command.
Invalid Command.
Command Phase:
Result Phase:
(------Invalid Codes----)
(STO)
Comment: An invalid command causes bits 7 and 6 of STO to be set
and the controller enters the standby state.
Symbol Descriptions.
above commands.
2241092-0001
Table
5-9 defines the symbols used in the
5-25
Floppy Disk Drive Controller
Table 5-9
Symbol
BUSINESS-PRO Hardware Reference
Definition of Symbols
Name
Definition
AO
Address line 0
Controls selection of main
status register (A = 0)
or data register (A = 1).
C
Cylinder number
Stands for the currently
selected cylinder numbers
o through 76 of the disk drive.
D
Data
Stands for the data pattern
to be written into a sector.
D(0-7)
Data bus
8-bit data bus: D7=MSB, DO=LSB.
DTL
Data length
Stands for the data length to
be read out of or written into
a sector.
EOT
End-of-track
Final sector number on a
cylinder. After EOT, the
controller stops data transfer.
GPL
Gap length
During format commands, GPL
specifies length of Gap 3.
During read/write commands,
GPL is the number of bytes
that VCos stay low after CRC.
H
Head address
Head number 0 or 1 specified
in ID field.
HD
Head
Selected head number 0 or 1.
HLT
Head load time
Head load time in the disk
drive is 2 to 254 milliseconds
in 2 millisecond increments.
HUT
Head unload time
Head unload time after a read or
write is 16 to 254 milliseconds
in 16 millisecond increments.
MF
FM or MFM mode
FM is selected when MF=O; MFM
is selected when MF=1.
5-26
2241092-0001
BUSINESS-PRO Hardware Reference
Table 5-9
Symbol
Floppy Disk Drive Controller
Definition of Symbols (Continued)
Name
Definition
MT
Multitrack
If MT is high after a read/write
operation on side 0, the
controller automatically starts
searching for sector 1, side 1.
N
Number
Number of data bytes written
in a sector.
NCN
New cylinder
number
New cylinder that will be
reached after seek operation.
NCN is the desired position of
the head.
ND
Non-DMA mode
Non-DMA operation.
PCN
Present cylinder
number
Cylinder number at end of
Sense Interrupt Status command.
R
Record
Sector number that will
be read or written.
R/W
Read/write
Read or write signal.
SC
Sector
Number of sectors per cylinder.
SK
Skip
Skip deleted data address mark.
SRT
Step rate time
Stepping rate for all disk
drives.
F=l millisecond,
E=2 milliseconds, and so forth.
STO
STl
ST2
ST3
Status
Status
Status
Status
ST(0-3) represents one to four
status registers.
Status information is available after command
execution.
Not to be confused
with the main status register,
which is selected by AO=O.
0
1
2
3
STP
USO
USl
Scan Test. If STP=l, the data in
contiguous sectors is compared
with data sent during a scan
operation.
If STP=2, alternate
sectors are read and compared.
Unit select
2241092-0001
Selected drive number 0 or 1.
5-27
Floppy Disk Drive Controller
BUSINESS-PRO Hardware Reference
5.1.2.3
Status Registers. Four internal status registers, STO
through ST3, contain information
about
the
floppy
disk
controller.
These registers are used to facilitate the transfer
of data between the controller and the processor. Values of the
bit positions of these registers are noted above in the execution
of the various controller commands. The following paragraphs
describe the status registers.
Status Register 0 (STO).
Bits
7 & 6
Description
Interrupt code (IC)
00 = Normal termination (NT) of the command.
The command was completed and properly
executed.
01
Abnormal termination (AT) of the command.
The execution of the command was started
but was not successfully completeG.
10
Invalid command (IC).
was never started.
The issued command
11 = Abnormal completion because the ready
signal from the disk drive changed states.
5
Seek end (SE). Set to 1 when the controller
completes the Seek command.
4
Equipment check (EC). Set to 1 if a fault
signal is received from the disk drive or
if the track 0 signal fails to occur after
77 step pulses.
3
Not ready (NR). Set to 1 when the disk
drive is in the not ready state and a Read or
Write command is issued to side 1 of a singlesided diskette.
2
Head addresS(HD). Indicates the state of the
head at interrupt.
1 &0
Unit select 1 and 2 (US1 and US2).
Indicates
the unit number of the disk drive at interrupt.
5-28
2241092-0001
BUSINESS-PRO Hardware Reference
Floppy Disk Drive Controller
Status Register 1 (STl).
Bit
Description
7
End of cylinder (EN). Set when the controller
tries to gain access to a sector beyond the
final sector of a cylinder.
6
Not used, always
5
Data error (DE). Set when the controller detects
a CRC (Cyclic Redundancy Check) error in either
the ID field or the data field.
4
Overrun (OR). Set if the controller is not
serviced by the main system within a certain
time limit during data transfers.
3
Not used, always O.
2
No data (ND). Set if the controller cannot
find the sector specified in the ID register
during the execution of a Read Data, Write
Deleted Data, or scan command. This flag is
also set if the controller cannot read the ID
field without an error during the execution of
a Read ID command or if the starting sector
cannot be found during the execution of a Read
Cylinder command
1
Not writable (NW). Set if the controller
detects a write-protect signal from the disk
drive during execution of a write Data, Write
Deleted Data, or Format Cylinder command ..
o
Missing address mark (MA). Set if the
controller cannot detect the ID register
mark. At the same time, the MD of status
register 2 is set.
2241092-0001
o.
5-29
BUSINESS-PRO Hardware Reference
Floppy Disk Drive Controller
Status Register 2 (ST2).
Bit
Description
7
Not used, always D.
6
Command mark (CM)~ This flag is set if the
controller encounters a sector that has a
deleted data address mark during execution of
a Read Data or scan command.
5
Data error in data field (DD). Set if the
controller detects an error in the data.
;
4
Wrong cylinder (WC). Related to no data (ND).
set when the. contents of cylinder C on the
media are different from those stored in the
ID register.
3
Scan equal hit (SH). Set if the contiguous
sector data equals the processor data during
the execution of a scan command.
2
Scan not satisfied (SN). Set if the controller
cannot find a sector on.the cylinder that meets
the condition during a scan command.
1
.Bad cylinder (BC). Related to ND. When the
contents of cylinder C on the medium are
different from the contents stored in the IDR
(internal drive register) and the contents of
cylinder Care FF, then this flag is set.
o
Missing address mark in data field (MD). Set
if the controller cannot' find a data address
mark or a deleted data address mark when data
is read from the medium.
5-30
2241092-0001
BUSINESS-PRO Hardware Reference
Floppy Disk Drive Controller
Status Register 3 (ST3).
Bit
Description
7
Fault (FT). Status of the fault signal from
the disk drive.
6
Write protect (WP). Status of the write-protect
signal from the disk drive.
5
Ready (RY).
disk drive.
4
Track 0 (TO). Status of the track 0 signal from
the disk drive.
3
Two side (TS). Status of the two-side signal
from the disk drive.
2
Head address (HD). Status of the side select
signal from the disk drive.
1
Unit select 1 (US1). Status of the unit select
1 signal from the disk drive.
o
Unit select 0 (USO). Status of the unit select
o signal from the disk drive.
2241092-0001
Status of the ready signal from the
5-31
Hardware Options
BUSINESS-PRO Hardware Reference
Section 6
Hardware Options
6.1
GENERAL
This section provides information about the optional devices that
are available for the BUSINESS-PRO computer system.
These
options are as follows:
*
Random-access memory (RAM) expansion kits (128 kilobytes
or 512 kilobytes)
*
Floppy disk drives (360 kilobytes or 1.2 megabytes)
*
Winchester disk controller
*
Winchester disk drives (21 megabytes, 40 megabytes, 72
megabytes, or 120 megabytes)
*
Tape drive and tape controller
*
*
*
TI mode CRT controller
Color display unit
*
Monochrome display unit
*
RS-232 communications interface
*
Optical mouse
*
Numerical coprocessor
PC-AT mode CRT controller
2241092-0001
6-1
Hardware Options
BUSINESS-PRO Hardware Reference
6.2
RAM EXPANSION
The main logic board contains 512 kilobytes of on-board RAM
consisting of two 256-kilobyte dynamic RAM boards. Two special
64-kilobyte RAM expansion boards (128-kilobyte RAM expansion kit)
allow expansion of this on-board RAM to a total capacity of 640
kilobytes.
In
addition,
a
special
memory area allows
installation of as many as six 512-kilobyte RAM expansion boards
to increase the on-board memory size to 3.64 megabytes. The
following paragraphs describe the 128-kilobyte and the 512kilobyte RAM expansion kits.
6.2.1 128-Kilobyte RAM Expansion Kit
The 128-kilobyte RAM expansion kit increases the available system
memory capacity from 512 kilobytes to 640 kilobytes. The kit
consists of two 64-kilobyte memory boards each of which contains
nine 64-kilobyte by I-bit DRAM devices. These boards occupy
memory addresses 080000H through 09FFFFH.
The 64-kilobyte RAM expansion boards mount directly on the main
logic board via two interface connectors (PI and P2). PI and P2
of the first RAM expansion board connect to J16 and J17 on the
main circuit board. PI and P2 of the second RAM expansion board
connect to J18 and J19. When these boards are installed on the
main circuit board, switch 4 (SWl, pins 4 and 7) must be set to
the ON position. The 128-kilobyte RAM expansion kit contains the
following items:
*
Two 64-kilobyte
2227053-0001
*
128 Kb RAM Expansion manual, TI Part No.
RAM
expansion
boards,' TI
Part
No.
2536082-0001
6.2.1.1
l28-Kilobyte RAM Expansion Kit Interface Signals. Two
connectors (PI and P2) provide the data and control paths between
the 64-kilobyte RAM expansion boards and the main logic board.
Table 6-1 lists and describes the interface signals and shows
their connector and pin assignments.
6.2.1.2 128-Kilobyte RAM Expansion Kit Specifications. The 128kilobyte RAM expansion kit specifications are as follows:
*
RAM cycle time (nonturbo mode) -- 500 nanoseconds
*
RAM cycle time (turbo mode) -- 333 nanoseconds
*
Average supply current
300 milliamperes
*
Type of error checking
odd parity
2241092-0001
6-3
Hardware Options
Table 6-1
Signal
BUSINESS-PRO Hardware Reference
12S-Kilobyte RAM Interface Signals
Connector and
Pin Number
Description
P2-3
P2-2
P2-1
Pl-I
PI-2
Pl-3
PI-IO
Pl-7
Memory data lines 0 through 7. These lines
carry data directly to or from the
expansion board DRAMs with no on-board
buffering.
Pl-4
volts dc for the DRAMs.
PE
PO
Pl-5
Pl-6
Even and odd parity. These lines provide
I/O data to the parity DRAM to reflect the
odd parity that is generated and detected
by the main logic board.
CAS-
P2-6
Column address strobe. The falling edge of
CAS- latches column addresses into the
DRAMs at the beginning of a memory cycle;
a later falling edge latches data in
during a memory write cycle.
RAS-
PI-S
Row address strobe. The falling edge of
RAS- latches row addresses into the DRAMs
at the beginning of a memory cycle; the
signal goes high at the completion of the
cycle.
W2-
P2-4
Memory write strobe. Memory write cycles
activate W2- to allow the falling edge of
CAS- to latch data into the DRAMs; the
signal remains high during a memory read
cycle.
GND
GND
PI-9
P2-14
Ground.
Ground.
AS
A7
A6
AS
A4
A3
A2
Al
AO
PI-II
P2-12
P2-9
P2-11
P2-13
P2-5
P2-10
P2-7
P2-S
PI-12
Address line 0 through S. These
multiplexed address lines provide the DRAM
addresses. These addresses change from row
to column addresses at the beginning of a
memory cycle; they return to row addresses
at cycle completion.
MDO
MDI
MD2
MD3
MD4
MD5
MD6
MD7
+5 Vdc
Not used.
6-4
2241092-0001
Hardware Options
BUSINESS-PRO Hardware Reference
6.2.2 512-Kilobyte RAM Expansion Kit
An optional 3-megabyte RAM expansion board allows use of as many
as six 512-kilobyte RAM expansion kits to increase the total main
logic board capacity to 3.64 megabytes.
The 3-megabyte RAM
expansion board plugs into a connector (J3) on the edge of the
main logic board.
Each 512-kilobyte RAM expansion kit consists of two 256-kilobyte
RAM expansion boards. Each expansion board qcontains nine 256kilobyte by I-bit DRAM devices. These boards mount directly on
the 3-megabyte RAM expansion board via an interface connector
(PI).
The boards occupy memory locations in the range of OlOOOOH
through 03FFFFH. The 512-kilobyte RAM expansion kit contains the
following items:
*
Two 256-kilobyte
2240931-0001
*
512 Kb RAM Expansion manual, TI Part No. 2536071-0001
RAM
expansion
boards,
TI
Part No.
6.2.2.1
512-Kilobyte RAM Expansion Kit Interface Signals.
Connector PI provides the data and control paths between the 256kilobyte RAM expansion boards and the 3-megabyte RAM expansion
board. Table 6-2 lists and describes the interface signals and
shows their pin assignments on connector Pl.
Table 6-2
512-Kilobyte RAM Expansion Kit Interface Signals
Signal
Pin Number
+5 Vdc
+5 Vdc
+5 Vdc
1
2
3
These lines provide the operating voltages
for the 256-kilobyte RAM expansion board's
active devices.
RAO
RAI
RA2
RA3
RA4
RA5
RA6
RA7
RAB
4
5
6
7
B
9
10
11
12
RAM address lines 0 through B. These
multiplexed address lines provide the
addresses for the DRAM devices. These
addresses change from row to column
addresses at the beginning of a memory
cycle. They return to row addresses at
cycle completion. Each line is triple
buffered on the 3-megabyte RAM expansion
board; each buffer drives up to four
256-kilobyte RAM expansion boards.
RAS-
13
Row address strobe. The falling edge of
this signal latches row addresses into the
DRAMs at the beginning of a memory cycle;
the signal goes high at the completion of
the cycle.
2241092-0001
Description
6-5
Hardware Options
Table 6-2
Signal
BUSINESS-PRO Hardware Reference
5l2-Kilobyte RAM Expansion Kit Interface Signals (Continued)
Pin
Number
Description
----------------------------------------~------------- -----------
CAS-
14
Column address strobe. The falling edge of
this signal latches column addresses into
the DRAMs at the beginning of a memory
cycle; it latches write data for write
cycles if W- is already low. CAS- remains
inactive (high) during refresh cycles.
W-
15
Memory write strobe. This signal's high
state selects the read mode, and its
low (active) state selects the write mode.
W- must be active prior to the activation
of CAS- to place the DRAM data outputs
(Qs) in their high-impedance states for
the entire cycle.
This is necessary for
common I/O operation.
PEPO
16
17
Parity data write to the RAM board and
parity data read from the RAM board. Odd
parity is generated and detected by the
main logic board.
MDIR
18
Memory direction. The state of this signal
determines the data transfer direction.
Setting the signal high enables data
through the octal bus transceiver from the
3-megabyte RAM expansion board to the
256-kilobyte DRAMs. Setting the signal low
enables data transfers in the opposite
direction.
MOO
MOl
MD2
MD3
MD4
M05
M06
MD7
MDEN-
19
20
21
22
23
24
25
26
27
Memory data lines 0 through 7. These lines
carry data to and from the RAM expansion
board DRAMs via an on-board octal bus
transceiver.
GND
GND
GND
28
29
30
Ground.
Ground.
Ground.
Memory data enable. Activation of this
signal enables data through the octal bus
transceiver in the direction selected by
the state of MDIR.
6-6
2241092-0001
BUSINESS-PRO Hardware Reference
Hardware Options
6.2.2.2
512-Kilobyte RAM Expansion Kit Specifications.
important specifications of the 512-ki1obyte RAM expansion
are as follows:
*
DRAM cycle time (nonturbo operation)
*
DRAM cycle time (turbo operation) -- 333 nanoseconds
*
DRAM access time
150 nanoseconds
*
RAS refresh rate
64 rows per millisecond
*
Average power consumption -- 5 amperes
*
Type of error checking -- Odd parity
2241092-0001
6-7
500 nanoseconds
The
kit
Hardware Options
BUSINESS-PRO Hardware Reference
6.3
BUSINESS-PRO MASS STORAGE OPTIONS
The mass storage configuration for the BUSINESS-PRO is userselected and can include as many as six half-height mass storage
devices connected to the system in daisy-chain fashion.
The
configuration can include any combination of as many as four
floppy disk drives or four Winchester disk drives. The following
optional mass storage devices are available for use with the
BUSINESS-PRO computer:
*
*
*
*
*
1.2-megabyte floppy disk drive
*
l20-megabyte, full-height Winchester disk drive
*
60-megabyte cartridge tape drive
360-kilobyte floppy disk drive
21-megabyte, half-height Winchester disk drive
40-megabyte, full-height Winchester disk drive
72-megabyte, full-height Winchester disk drive
The following
devices.
paragraphs
describe
the
optional
mass storage
6.3.1 1.2-Megabyte Floppy Disk Drive
The 1.2-megabyte floppy disk drive is a dual-mode disk drive that
records on a S 1/4-inch, floppy diskette. The dual-mode feature
provides the capability of either high-density (96 tracks per
inch) or low-density (48 tracks per inch) recording.
The 1.2-megabyte floppy disk drive circuits use - open-collector
NAND gate buffers as line drivers and Schmitt trigger inverters
as line receivers.
(Use of these Schmitt trigger devices
provides noise immunity for the signal lines.) All input signals
are terminated by ISO-ohm resistors and are pulled up to Vcc in
the last disk drive in the daisy-chain configuration.
2241092-0001
6-9
Hardware Options
BUSINESS~PRO
Hardware Reference
6.3.1.1 1.2-Megabyte Floppy Disk Drive Features. The following
features characterize the 1.2-megabyte floppy disk drive:·
*
Stores and retrieves information on 5 1/4~inch floppy
diskettes (either high-density or low-density)
*
Operates at two speeds:
360 revolutions per minute (rpm) for
media
high-density
300 rpm for low-density media
*
Reads from or writes to high-density diskettes that
provide 1.2 megabytes of storage per diskette.
*
Reads from or writes to double-density
diskettes.
However, diskettes written by the 1.2-megabyte drive are
reliable only in 1.2-megabyte drives thereafter.
6.3.1.2
1.2-Megabyte Floppy Disk Drive Kit. The 1.2-megabyte
floppy disk drive kit, TI Part No. 2240952-0001 consists of the
following components:
*
1.2-megabyte, half-height floppy disk drive, TI Part No.
2240884-0001
*
1.2 Mb Half-Height Floppy Drives
2240891-0001
*
Daisy-chain cable, TI Part No.
manual,
TI
Part
No.
2240837-0001
6.3.1.3 1.2-Megabyte Floppy Disk Drive Tabulated Information.
Tables 6-3 through 6-7 provide tabulated information about the
1.2-megabyte floppy disk drive.
NOTE
The 1.2-megabyte floppy disk drive contains a
set of
eight
dual-inline-package
(DIP)
switches that can be used to insert (switch
ON) or remove (switch OFF) the terminator
resistors from the circuit. These switches
are all set to their ON positions at the
factory.
When installing the drives in a
daisy-chain configuration, you should ensure
that all terminator switches are turned OFF
on all drives except the last one in the
daisy chain.
6-10
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-3
Hardware Options
1.2-Megabyte Floppy Drive Interface Connector PI
Signal
Description
Pin Number
LOW SPEED
2
When active, this input signal
enables low-speed (360-rpm)
operation. Correct read/write
operations are not guaranteed
until at least 400 milliseconds
after a speed change has occurred.
The disk drive uses the DRIVE
SELECT signal to latch this input
line.
HEAD LOAD
4
Not used.
DRIVE
DRIVE
DRIVE
DRIVE
SELECT
SELECT
SELECT
SELECT
0
1
2
3
i 101
i 12 ;
: 14 \
'0J
These input signals activate the
in-use light for a selected disk
drive. They also enable all other
disk drive signals except MOTOR ON.
INDEX
8
This output signal notifies the
disk controller that an index hole
has been detected (once per disk
revolution). with the drive motor
at full speed, the leading edge of
this signal occurs approximately
every 200 milliseconds for
low-speed or approximately every
166.7 milliseconds for high-speed
operation.
MOTOR ON
16
This input signal activates the
drive motor.
DIRECTION
SELECT
18
This input signal determines the
travel direction of the read/write
heads. Its high state causes the
heads to move outward toward track
O. Its low state causes the heads
to move inward toward track 39.
STEP
20
This input signal causes a
single-track movement of the
read/write heads in the direction
specified by the DIRECTION SELECT
signal.
WRITE DATA
22
This input signal provides data
when enabled by an active WRITE
GATE signal.
2241092-0001
6-11
Hardware Options
Table 6-3
BUSINESS-PRO Hardware Reference
1.2-Megabyte Floppy Drive Interface Connector PI (Continued)
Signal
Pin
Number
Description
WRITE GATE
24
This input signal enables the
WRITE DATA signal and disables the
STEP and the READ DATA signals.
TRACK 00
26
This output signal notifies the
controller that the read/write
heads are positioned at track O.
WRITE PROTECT
28
This output signal notifies the
controller that the diskette is
protected against any write
operations and cannot, therefore,
be written to.
READ DATA
30
This output signal notifies the
controller that the drive has
detected a clock or a data bit
under its read/write heads.
SIDE SELECT
32
This input signal determines which
side of the diskette is to be read
from or written to. Its high state
selects side 0 (bottom side). Its
low state selects side 1 (top
side).
.
DISKETTE
CHANGE
34
This output signal notifies the
controller that the diskette has
been changed since the last access
operation. Opening the diskette
~ccess door activates DISKETTE
CHANGE. Either of the following
conditions deactivates the signal:
Power is applied to the drive.
A diskette is installed, the
door is closed, and a step pulse
is issued to the drive.
NOTE:
All odd-numbered pins are connected to ground.
6-12
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-4
Hardware Options
1.2-Megabyte Floppy Disk Drive Power Connector P2
Pin Number
Table 6-5
Jumper
Voltage
±
1
+12
2
+12 volts dc return
3
+5
4
+5 volts dc return
±
0.6 volts dc
0.25 volts dc
1.2-Megabyte Floppy Disk Drive Jumper Settings
Factory
Setting
Function
DSO
DSI
DS2
DS3
In
Out
Out
Out
This jumper configuration designates the
disk drive to be drive 1.
HS
Out
This position of jumper HS prevents
head loading upon activation of the
DRIVE SELECT signal.
.
HM
In
This position of jumper HM causes the
heads to load upon activation of the
MOTOR ON signal.
MR
In
This position of jumper MR disables the
READY signal.
TD
In
This position of jumper TD prevents the
drive from being connected in a
daisy-chain configuration with 8-inch
floppy disk drives.
HL
LB
In
In
This configuration defines pin 4 of data
connector PI as the HEAD LOAD signal.
INU
LA
Out
Out
This configuration defines pin 4 of data
connector PI as in use.
2241092-0001
6-13
Hardware Options
Table 6-6
BUSINESS-PRO Hardware Reference
l.2-Megabyte Floppy Disk Drive Performance Specifications
Specification
Characteristic
High Speed
Low Speed
Capacity:
Formatted
l228.8kilobytes
368.6 kilobytes
Unformatted
1604 kilobytes
500.0 kilobytes
Recording density
9646 bits per inch
5876 bits per inch
Track density
96 tracks per inch
48 tracks per inch
Rotational speed
360 + 5.4 rpm
Tracks per side
80
40
Sector size
512 bytes
512 bytes
Sectors per track
15
8 or 9
Average
91 milliseconds
95 milliseconds
Track-to-track
3 milliseconds
3 milliseconds
Settling time
15 milliseconds
15 milliseconds
300 .±. 4.5 rpm
Access time:
Motor start time
1.2 seconds
(maximun)
Head load time
50 milliseconds
(maximum)
50 milliseconds
(maximum)
Encoding method
Modified frequency
modulation (MFM)
Modified frequency
modulation (MFM)
Data transfer rate
rate
500 kilobits per
second
250 kilobits per
second
Soft read errors
1/10(9) bits read
1/10(9) bits read
Hard read errors
1/10(12) bits read
1/10(12) bits read
Seek errors
1/10(6) seek
operations
1/10(6) seek
operations
Error rate:
6-14
2241092-0001
Hardware Options
BUSINESSRO Hardware Reference
Table 6-7
1.2-Megabyte Floppy Disk Drive Power Requirements
Value
Item
Operating current:
+5 volts dc line
0.4 ampere (typical)
0.5 ampere (maximum)
+12 volts dc line
0.3 ampere (typical)
1.2 amperes (maximum)
Maximum ripple content
(peak-to-peak):
+5 volts dc line
100 millivolts
+12 volts dc line
200 millivolts
Voltage tolerance
+ 5%
Power dissipation
5.6 watts (typical)
6.3.2 360-Kilobyte Floppy Disk Drive
The 360-kilobyte floppy disk drive can store and retrieve up to
360 kilobytes of information on a 5 1/4-inch,
floppy diskette.
The drive uses a direct-drive method of rotation, thus avoiding
the problems inherent to a belt-driven system.
The drive can be
mounted in any of the top four drive positions in the BUSINESSPRO system enclosure.
The 360-kilobyte floppy disk drive circuits use open-collector
NAND gate buffers as line drivers and Schmitt trigger inverters
as line receivers.
(Use of these Schmitt trigger devices
provides noise immunity for the signal lines.) All input signals
are terminated by 150-ohm resistors and are pulled up to Vcc in
the last disk drive in the daisy-chain configuration.
6.3.2.1 360-Kilobyte Floppy Disk Drive Kit.
The 360-kilobyte
2240972-0001 includes the
floppy disk drive kit,
TI Part No.
following items:
*
360-kilobyte, half-height floppy disk drive, TI Part No.
2234298-0002
*
360 Kb Half-Height Flo1212Y Drives
2240978-0001
*
Daisy-chain cable, TI Part No.
2241092-0001
6-15
manual,
TI
2240837-0001
Part
No.
Hardware Options
BUSINESS-PRO Hardware Reference
6.3.2.2
360-Kilobyte Floppy Disk Drive Tabulated Information.
Tables 6-8 through 6-11 provide tabulated information about the
360-kilobyte floppy disk drive.
NOTE
The 360-kilobyte floppy disk drive contains a
set of seven DIP switches that can be used to
insert (switch ON) or remove (switch OFF) the
terminator resistors from the circuit. These
switches are all set to their ON positions at
the factory.
When installing the drives in a
daisy-chain configuration, you should ensure
that all terminator switches are turned OFF
on all drives except the last one in the
daisy chain.
Pins 2 and 34 of the 360-kilobyte floppy disk
drive interface connector Pl are reserved.
All other pin descriptions are the same as
those listed in Table 6-3.
Table 6-8' 360-Kilobyte Floppy Disk Drive Power Connector P2
Pin Number
Voltage
1
+12 + 0.6 volts dc
2
+12 volts dc return
3
+5 + 0.25 volts dc
4
+5 volts dc return
6-16
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-9
Jumper
Hardware Options
360-Kilobyte Floppy Disk Drive Jumper Settings
Function
Factory Setting
DSO
DSI
DS2
DS3
In
Out
Out
Out
This jumper configuration designates
the disk drive to be drive 1.
HS
Out
This position of jumper HS prevents
head loading upon activation of the
DRIVE SELECT signal.
HM
In
This position of jumper HM causes
head loading upon activation of the
MOTOR ON signal.
MX
Out
Not defined.
Table 6-10
360-Kilobyte Floppy Disk Drive Specifications
Specification
Characteristic
Capacity:
368.6 kilobytes
500.0 kilobytes
Formatted
Unformatted
Recording density
5876 bits per inch
Track density
48 tracks per inch
Rotational speed
300
Tracks per side
40
Sector size
512 bytes
Sectors per track
8 or 9
Read/write heads
2
Access time:
Average
Track-to-track
Settling time
148 milliseconds
5 milliseconds
15 milliseconds
Motor start time
1 second (maximum)
2241092-0001
6-17
±
6 rpm
BUSINESS-PRO Hardware Reference
Hardware Options
Table 6-10 360-Kilobyte Floppy Disk Drive Specifications (Continued)
Characteristic
Specification
Head settle time
15 milliseconds
(maximum)
Encoding method
Modified frequency
modulation (MFM)
Data transfer rate
250 kilobits per
second
Error rate:
Soft read errors
1/10(9) bits read
Hard read errors
1/10(12) bits read
Seek errors
1/10(6) seek
operations
Table 6-11
360-Kilobyte Floppy Disk Drive Power Requirements
Item
Value
Operating current:
+5 volts dc line
0.9 ampere (typical)
1.2 amperes (maximum)
+12 volts dc line
0.5 ampere (typical)
1.3 amperes (maximum)
Maximum ripple content
(peak-to-peak):
+5 volts dc line
50 millivolts
+12 volts dc line
100 millivolts
Voltage tolerance
+ 5%
Power dissipation
11 watts (typical)
6-18
2241092-0001
BUSINESS-PRO Hardware Reference
Hardware Options
6.3.3 Winchester Disk Controller
The optional Winchester disk controller is a full-sized,
16-bit
board that controls the operations of as many as four Winchester
disk drives via the industry-standard ST-506 interface. The disk
drives connect to the controller in a daisy-chain configuration.
6.3.3.1 Winchester Disk Controller Kit.
The Winchester disk
controller kit, TI Part No.
2241059-0001 includes the following
items:
*
Winchester disk controller, TI Part No.
*
Winchester Controller manual, TI Part No.
2240925-0001
2241056-0001
6.3.3.2 Winchester Disk Controller Diagrams. Figure 6-1 is a
functional block diagram of the Winchester controller. Figures
6-2 through 6-4 are cabling diagrams of the Winchester controller
connected in two-drive and three-drive configurations. Figure 63 shows the controller connected in a two-drive XENIX system.
2241092-0001
6-19
I'Ij
1-'~
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I - - CORRD
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r+
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WINCHESTER
DRIVE
BUSINESS-PRO Hardware Reference
J3
WINCHESTER
DISK
CONTROLLER
TI PART NO.
2240925-0001
TI PART NO.
2240837-0002
Hardware Options
WINCHESTER DRIVE 1
CONTROL
DSO
TI PART NO.
2232327-0001
SLOT 5/6
DATA
TERMINATOR INSTALLED
J4
TI PART NO.
2240993-0001
TI PART NO.
2240992-0001
WINCHESTER DRIVE 2
CONTROL
34 PIN
DATA
20 PIN
DS2
SLOT 3
TERMINATOR INSTALLED
2287497
Figure 6-2
2241092-0001
Controller Connected in a Two-Drive Configuration
6-21
Hardware Options
BUSINESS-PRO Hardware Reference
J3
WINCHESTER
DISK
CONTROLLER
TI PART NO.
2240925-0001
h
TI PART NO.
2240837-0003
I
~
J5
h
L
TI PART NO.
2232327-0001
~
J6
h
r
I
L
TI PART NO.
2240992-0001
I-J
-c
r
L
WINCHESTER DRIVE 1
CONTROL
34 PIN
DATA
20 PIN
DSO
SLOT 5/6
TERMINATOR INSTALLED
WINCHESTER DRIVE 2
CONTROL
34 PIN
DS2
SLOT 3
DATA
20 PIN
TERMINATOR INSTALLED
2287498
Figure 6-3
Controller Connected in a Two-Drive XENIX System
6-22
2241092-0001
Hardware Options
BUSINESS-PRO Hardware Reference
WINCHESTER
DISK
CONTROLLER
TI PART NO.
2240925-0001
J3
--,
TI PART NO.
2240837-0003
W
~
TI PART NO.
2232327-0001
-
-
DATA
20 PIN TERMINATOR INSTALLED
r-
CONTROL
34 PIN
L
J5
--,
TI PART NO.
2232327-0001
W
DS1
SLOT 5
rL
W
WINCHESTER DRIVE 2
CONTROL
34 PIN
rL
WINCHESTER DRIVE 1
DSO
SLOTS
DATA
20 PIN
TERMINATOR INSTALLED
J4
--,
TI PART NO.
2240993-0001
L
---1
J8
--,
WINCHESTER DRIVE 3
r-
TI PART NO.
2240992-0001
---1
I
L
CONTROL
34 PIN
DS2
SLOT 3
DATA
20 PIN
TERMINATOR INSTALLED
2287499
Figure 6-4
2241092-0001
Controller Connected in a Three-Drive Configuration
6-23
Hardware Options
BUSINESS-PRO Hardware Reference
6.3.3.3
Winchester Disk Controller Tabulated
Information.
Tables 6-12 through 6-20 provide tabulated information about the
Winchester disk controller. The controller connectors and their
functions are as follows:
*
Control connector
drives 1 and 2
*
Control connector
drives 3 and 4
*
Data connector J5 -- handles data transfers between the
controller and disk drive 1
*
Data connector J6 -- handles data transfers between
controller and disk drive 2
*
Drive-in-use connector J7 -- allows the user to attach
the controller to the drive-in-use indicator on the
front of the system enclosure
*
Data connector Ja -- handles data transfers between the
controller and disk drive 3
*
Data connector J9 -- handles data transfers between
controller and disk drive 4
J3
J4
control
control
6-24
interface
interface
for disk
for
disk
the
the
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-12
Hardware Options
Winchester Disk Controller Control Connector J3
Signal
Pin
Number
DSODS1-
26
28
Description
Select signals for drives 1 and 2. The
controller generates these signals to select
the active drive as determined by the
positions of the drive-select jumpers on the
disk drives.
DSO- enables the drive on J5 (drive 1).
DSl- selects the drive on J6 (drive 2).
HSOHS1HS2HS3-
14
18
4
2
Head-select signals 0 through 3. The
controller sets these signals to select 1 of
15 read/write heads. HSO- through HS3- form a
4-bit binary code in the range of 1111
through 0000, where 1111 selects head O.
PWG-
6
Write gate. This controller output signal
enables the write driver to allow the
selected read/write head to record data on
the disk. This signal must remain inactive
during read operations or during the
transmission of step pulses to the disk
drive.
.
PSC-
8
Seek complete. The disk drive activates this
signal to indicate that the drive is selected
and that the read/write heads are in the
correct position. PSC- must be active before
attempting any read or write operations.
PTKOOO-
10
Track O. The disk drive activates this signal
to indicate that the drive is selected and
that the read/write heads are positioned at
track o.
PWF-
12
Write fault. The disk drive activates this
signal to indicate that PWG- is active and
that one or more of the following conditions
is true:
Write current is absent.
2241092-0001
6-25
Hardware Options
Table 6-12
Signal
BUSINESS-PRO Hardware Reference
Winchester Disk Controller Control Connector J3 (Cont)
Pin
Number
Description
PWF- (Continued)
Write data is absent.
The drive is not ready.
An invalid read/write head has been
selected.
Incorrect dc voltage levels.
PSC- is inactive.
PWF- can also indicate that PWG- is inactive
while write current is present. An active
PWF- disables all write operations.
PINDEX-
20
Index. The disk drive activates this signal
to indicate that it has detected the physical
beginning of a track.
PDRDY-
22
Ready. The disk drive activates this signal
to indicate that the drive is receiving
power, that the disk rotation is within the
prescribed tolerance, and that the read/write
heads are over the recording zone. Neither
the selection of a new head nor a normal seek
operation deactivates this signal.
STEP-
24
Step pulse. The controller generates the step
pulse to cause the read/write head to move a
distance of one cylinder in the direction
specified by the state of DIR-.
DIR-
34
Direction. The controller generates this
signal to define the direction of read/write
head movement for stepping operations. Its
low state causes head movement toward the
center of the disk; its high condition causes
head movement toward track O.
NOTE:
All odd-numbered pins, except pin 3, are connected to ground.
Pin 3 has been removed for connector keying. Pin 16 is reserved.
6-26
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-13
Hardware Options
Winchester Disk Controller Control Connector J4
Signal
Pin
Number
DS2DS3-
30
32
Description
Select signals for drives 3 and 4. The
controller generates these signals to select
the active drive as determined by the
positions of the drive-select jumpers on the
disk drives.
DS2- selects the drive on J8.
DS3- selects the drive on J9.
SHDOSHD1SHD2SHD3-
14
18
4
2
Head select signals 0 through 3. The
controller sets these signals to select 1 of
15 read/write heads. HSO- through HS3- form a
4-bit binary code in the range of 1111
through 0000, where 1111 selects head o.
SWG-
6
Write gate. This controller output signal
enables the write driver to allow the
selected read/write head to record data on
the disk. This signal must remain inactive
during read operations or during the
transmission of step pulses to the disk
drive.
SSC-
8
Seek complete. The disk drive activates this
signal to indicate that the drive is selected
and that the read/write heads are in the
correct position. SSC- must be active before
attempting any read or write operations.
STKOOO-
10
Track O. The disk drive activates this signal
to indicate that the drive is selected and
that the read/write heads are positioned at
track O.
SWF-
12
Write fault. The disk drive activates this
signal to indicate that SWG- is active and
that one or more of the following conditions
is true:
Write current is absent.
Write data is absent.
The drive is not ready.
2241092-0001
6-27
Hardware Options
Table 6-13
Signal
BUSINESS-PRO Hardware Reference
Winchester Disk Controller Control Connector J4 (Cont)
Pin
Number
Description
SWF- (Continued)
An invalid read/write head has been
selected.
Incorrect dc voltage levels.
SSC- is inactive.
SWF- can also indicate that SWG- is inactive
while write current is present. An active
SWF- disables all write operations.
SINDEX-
20
Index. The disk drive activates this signal
to indicate that it has detected the physical
beginning of a track.
SDRDY-
22
Ready. The disk drive activates this signal
to indicate that the drive is receiving
power, that the disk rotation is within the
prescribed tolerance, and that the read/write
heads are over the recording zone. Neither
the selection of a new head nor a normal seek
operation deactivates this signal.
SSTEP-
24
Step pulse. The controller generates the step
pulse to cause the read/write head to move a
distance of one cylinder in the direction
specified by the state of SDIR-.
SDIR-
34
Direction. The controller generates this
signal to define the direction of read/write
head movement for stepping operations. Its
low state causes head movement toward the
center of the disk; its high condition causes
head movement toward track O.
NOTE:
All odd-numbered pins, except pin 3, are connected to ground.
Pin 3 has been removed for connector keying. Pin 16 is reserved.
6-28
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-14
Hardware Options
Winchester Disk Controller Data Connector J5
Pin
Signal
Description
Number
,
----------------------------------------------------------------lMFMWR+
lMFMWR-
13
14
Write-data plus and write-data minus
(differential signal pair)
lMFMRD+
lMFMRD-
17
18
Read-data plus and read-data minus
(differential signal pair)
NOTE:
Pins 1, 3, 5, 7, 9, and 10 are reserved. All other pins, except
pin 6, are connected to ground. Pin 6 has been removed for
connector keying.
Table 6-15
Signal
Winchester Disk Controller Data Connector J6
Pin
Number
Description
2MFMWR+
2MFMWR-
13
14
Write-data plus and write-data minus
(differential signal pair)
2MFMRD+
2MFMRD-
17
18
Read-data plus and read-data minus
(differential signal pair)
NOTE:
Pins 1, 3, 5, 7, 9, and 10 are reserved. All other pins, except
pin 6, are connected to ground. Pin 6 has been removed for
connector keying.
2241092-0001
6-29
Hardware Options
Table 6-16
Signal
BUSINESS-PRO Hardware Reference
Winchester Disk Controller Data Connector J8
Pin
Number
Description
3MFMWR+
3MFMWR-
13
14
Write-data plus and write-data minus
(differential signal pair)
3MFMRD+
3MFMRD-
17
18
Read-data plus and read-data minus
(differential signal pair)
NOTE:
Pins 1, 3, 5, 7, 9, and 10 are reserved. All other pins, except
pin 6, are connected to ground. Pin 6 has been removed for
connector keying.
Table 6-17
Signal
Winchester Disk Controller Data Connector J9
Pin
Number
Description
4MFMWR+
4MFMWR-
13
14
Write-data plus and write-data minus
(differential signal pair)
4MFMRD+
4MFMRD-
17
18
Read-data plus and read-data minus
(differential signal pair)
NOTE:
Pins 1, 3, 5, 7, 9, and 10 are reserved. All other pins, except
pin 6 are connected to ground. Pin 6 has been removed for
connector keying.
6-30
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-18
Hardware Options
Winchester Disk Controller Switches SWl Through SW4
Factory
Setting
Switch
Function
SWl
OFF
Sets the controller I/O port address
range to IFOH through IF7H
SW2
OFF
Sets the controller I/O port address
range to 3F6H through 3F7H
SW3
OFF
Not used
SW4
OFF
Not used
NOTE:
Both ranges may be activated at the same time.
Table 6-19
Winchester Disk Controller Performance Specifications
Characteristic
Specification
Possible number of drives
1 through 4
Number of cylinders
2048 (maximum)
Number of sectors
1 to 256
Bytes per sector
256, 512, and 1024
Data encoding
MFM
Number of heads
16 (maximum)
Drive selects
4 (maximum)
Data transfer rate
5 megabytes per second
Error correction capability
5-bit correction span
2241092-0001
6-31
Hardware Options
BUSINESS-PRO Hardware Reference
6.3.3.4 External Activity Indicator.
The
Winchester disk controller external activity indicator
follows the state of the status register.
The activity LED
connector is a 4-pin, single-row, straight header. Pins 1 and 4
of this connector are tied together as the LED+ signal.
Pins 2
and 3 are tied together as the LED- signal. The LED- signal is
driven by an open collector device capable of sinking 40
milliamperes when at a transistor-to-transitor (TTL) level. The
LED+ signal is pulled up to Vcc through a current-limiting
resistor
that limits the LED current to approximately 20
milliamperes.
6.3.4 Winchester Disk Controller System Addresses
The Winchester controller is accessed as an I/O device on the
system unit bus and has two base addresses available to the
programmer.
The primary base address
of
the
Winchester
controller is IFXH/3FXH and the secondary base address is
17XH/37XH. The base address is selected by DIP switches on the
controller board, as described later in this section. The I/O
ports used by the Winchester controller and the function of each
port is shown in Table 6-20.
Table 6-20
Winchester Controller I/O Port Addresses
I/O Address
Primary
Secondary
(Hexadecimal)
IFO
IFl
IF2
1F3
IF4
1F5
1F6
1F7
3F6
3F7
170
171
172
173
174
175
176
177
376
377
Name/Function
Read
Write
Sector buffer
Error register
Sector count
Sector number
Cylinder low
Cylinder high
Size/drive/head
Status register
Reserved
Diagnostic register
Sector buffer
Write precompensation
Sector count
Sector number
Cylinder low
Cylinder high
Size/drive/head
Command register
Fixed disk register
Fixed disk register
6.3.4.1
I/O Port Descriptions. The following sections describe
the operation of each of the I/O ports listed in the table above.
6-32
2241092-0001
BUSINESS-PRO Hardware Reference
Hardware Options
Sector Buffer. This is a RAM area used to hold data to be
transferred to or from the hard disk. The system has access to
this sector buffer when Busy is cleared and BDRQ is active; the
Winchester controller has access to the sector buffer in other
cases. Data is accessed in the buffer serially; the buffer
address
automatically
increments with each read or write
operation. The data register provides a 16-bit path to the
system for sector buffer transfers to and from the system. When
a Read or Write Long command is performed, the four error
detection and correction (ECC) bytes are transferred, one byte at
a time, on XD(0-7) using the system processor byte I/O mode.
(See Table 6-22 for a definition of the long mode flag.)
This
sector buffer contains enough storage capacity to buffer one
sector of data for the hard disk, plus the four ECC bytes for
read/write long commands.
Sector sizes of 256, 512, and 1024
bytes are supported.
Error Register.
The Winchester controller writes
to
this
register to specify errors or diagnostic codes to the system.
The error register is an 8-bit, read-only register containing
error information that pertains to the previous command executed.
The system has access to the error register whenever the Busy bit
is not set.
Data in the error register is valid only if the
error bit is set in the status register or if
internal
diagnostics have been executed.
Diagnostics are executed at
power-up and by execution of the diagnostics command.
In
operational mode, each bit of the register indicates a different
error as shown in Figure 6-5.
(7]
[6]
[5]
(4]
[3]
[2]
[1]
[0]
-------------------------------------------------------------------------------------------------------------------------------------------------
Figure 6-5
Data address mark not found
Track 00 error
Aborted command
Not used
ID not found
Not used
Data ECC error
Bad block detect
Error Register Bit Definitions
At the completion of an internal diagnostic test, the error
register contains one of the following codes, indicating the
status of the hardware. The diagnostic codes are shown in Table
6-21.
2241092-0001
6-33
Hardware Options
BUSINESS-PRO Hardware Reference
Table 6-21
Code
OlH
02H
03H
04H
05H
OAH
Diagnostic Code Definitions
Status
Pass
Controller fault
Sector buffer fault
Not used
Microcontroller fault
Size/drive/head register fault
Write Precompensation Register.
The
write
precompensation
register is an 8-bit, write-only register specifying the cylinder
number divided by four at which write precompensation is to
start.
Loading this register with a value of FF disables write
precompensation.
Sector Count Register. This register specifies the number of
sectors to transfer (0=256) for Read, Verify, or Write commands.
For the Format Track or Set Parameters command, this register
specifies the number of sectors per track. For multiple sector
commands, this register is decremented, and the sector number
register is incremented. This register is a read/write register,
which can be accessed by the system when the Busy bit is cleared.
Sector Number Register.
This read/write register specifies the
sector number of the starting sector for Read, Verify, and Write
commands.
This register is incremented for mUltiple sector
commands. The system has access to this register whenever the
Busy bit in the status register is cleared.
Cylinder High and Low Registers.
The cylinder high and low
registers are read/write registers that specify the cylinder
number of the starting sector in Read, Verify, Write, or Format
Track commands.
~he
controller
supports
multiple
sector
operations across track and cylinder boundaries. The cylinder
low register is an 8-bit register containing the low-order byte
of the cylinder to be accessed. The cylinder high register is an
8-bit register with bits 0, 1, and 2 specifying the high order
bits of the cylinder to be accessed. The controller supports a
maximum of 2047 cylinders.
6-34
2241092-0001
BUSINESS-PRO Hardware Reference
Hardware Options
Size/Drive/Head Register.
The size/drive/head register is an 8bit, read/write register that directly controls the drive and
head selects for the Winchester disk drive, as well as the sector
size bits used in the Read, Verify, Write, and Format commands.
This register is loaded with the maximum number of heads for each
drive before a Set Parameters command is issued. The system has
access to this register when Busy is cleared; otherwise, the
controller has access to the register. Figure 6-6 shows the bit
definitions for this register.
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Head select 0
Head select 1
Head select 2
Head select 3
Drive select, drive 1=0
Sector size 0
Sector size 1
ECC enabled=l
Sector size bit mapping:
00
01
10
11
Figure 6-6
-
256 byte sector
512
1024
undefined
Size/Drive/Head Register Bit Definitions
Status Register.
The status register is an 8-bit, read-only
register that contains status information from the controller.
The system has access to this register at any time, but data in
this register is valid only when the Busy bit is cleared.
This
register must be read to determine the result of any operation.
Reading this register clears the interrupt request on the system
bus.
A
description of the bits in the status register is given
in Figure 6-7.
2241092-0001
6-35
Hardware Options
[7]
[6]
[5]
BUSINESS-PRO Hardware Reference
[4]
[3]
[2]
[1]
[0]
Error
Index from selected drive
Corrected data
Data request
Seek complete from drive
Write fault from drive
Drive ready from drive
Controller busy
Figure 6-7
Status Register Bit Definitions
Command Register. This a-bit, write-only register is used to
load commands for the Winchester controller board when the Busy
bit in the status register is cleared.
Before writing to the
command register the sector count, sector number, cylinder low,
cylinder high, and size/drive/head registers must be loaded.
Writing to the command register clears the interrupt request to
the system. Writing any bit pattern to this register that is not
defined below results in a aborted command error. Valid command
bit patterns are shown in Table 6-22. Stepping rates are given
in Table 6-23.
6-36
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-22
Winchester Controller Commands
Bit Positions
7 6 543 2 1 0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
Hardware Options
0 o 0 0 0
0 o 0 0 1
1 (--R--)
0 o 0 L T
1 o 0 L T
0 o 0 0 T
1 000 0
1 (--R--)
0 o 0 0 B
1 o 000
1 o 001
Command
Scan ID
Get Software Version
Restore
Read
Write
verify
Format Track
Seek
Select Drive Bank
Perform Internal Diagnostic
Set Parameters
NOTES:
R - Stepping rate. The stepping rate field of a command maps to
real values as indicated in the next table.
L - Long mode flag (O=normal mode, normal ECC functions, l=long
mode, no ECC bytes developed or error checking takes place).
When set to 1, the controller does not perform ECC checking on
the data field.
Instead, the data field is extended by four
bytes to include what would normally be the ECC bytes for a
read or write operation.
T - Retry flag (O=enable retry, l=disable retry).
When the
retry flag is set to 1, the controller does not perform retries
on data transfers that generate errors.
B - Bank select (O=set to bank 0, l=set to bank 1). When the
bank select is set to 1, the controller enables selection of
drives 3 and 4. When the bank select is set to 0, the
controller enables selection of drives 1 and 2.
---~-------------------------------------------------- -----------
2241092-0001
6-37
Hardware
BUSINESS-PRO Hardware Reference
Opt~ons
Table 6-23
Rate
R
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Controller-Supported Stepping Rates
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
35us
0.5ms
1.Oms
1.5ms
2.0ms
2.5ms
3.0ms
3.5ms
4.0ms
4.5ms.
5.0ms
5.5ms
6.0ms
6.5ms*
3.2us
l6.0us
NOTE:
* This rate is used for all subsequent operations that do not
specify .a stepping rate.
Fixed Disk Control Register.
This register is an 8-bit, write-only register used to control
the operation of the Winchester controller card. This register
is decoded in the floppy controller I/O address block, and the
address of this register follows the address of the floppy
controller card. Only bits 1, 2, and 3 of this register are
used; bits 0, 4, 5, 6, and 7 are reserved. A description of the
bits in this register is given in Figure 6-8.
The /Inten bit is used to enable/disable the Winchester interrupt
onto the system interrupt bus. The interrupt is enabled by the
power-up reset.
The /Hdr bit is used to generate a software-controlled reset.
When set, the software-controlled reset maintains the fixed disk
section logic reset as long as the bit is on. This bit is set to
a logic 1 for a minimum of 10 microseconds and then reset to a
logic 0 to complete the reset function. The HS3 bit is used to
enable the head select 3 output for accessing heads 8 through,15.
6-38
2241092-0001
Hardware Options
BUSINESS-PRO Hardware Reference
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Reserved
/Inten - Enable interrupt
/Hdr - Reset controller
HS3 - Enable head 3 select
Reserved
Reserved
Reserved
Reserved
Figure 6-8
Fixed Disk Control Register
Diagnostic Register.
This register is an 8-bit, read-only
register used for diagnostics. Bits 0 through 6 refer to the
currently selected hard disk drive.
Bit 7 is used for the
diskette change line for the floppy disk controller logic.
The
bit definitions for this register are given in Figure 6-9.
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
/Drive select 0 (O=selected)
/Drive select 1
/Head select 0
/Head select I
/Head select 2
/Head select 3/reduced write
/Write gate current
Not used
Figure 6-9
6.3.4.2
Diagnostic Register Bit Definitions
Controller Command Functions.
Scan ID - OOH.
Immediately upon recelvlng the Scan ID command,
peripheral controller hardware raises the Busy flag in the host
status register.
At the same time, the Command Ready bit goes
active, activating the 8049 microprocessor IC.
The processor
then executes code to update the head, sector size, and cylinder
registers. Busy is cleared and an interrupt is sent to the host
at the completion of this command.
Get Software Version - OIH.
Upon receiving this command, the
Busy bit is set in the status register. The controller loads the
2241092-0001
6-39
Hardware Options
BUSINESS-PRO Hardware Reference
software major version number into the cylinder high register and
the revision number into the cylinder low register.
Busy is
cleared, and an interrupt is sent to the system at the completion
of this command.
Restore - 10H.
The Restore command sets the Busy bit, and the
controller then executes code to position the heads of the drive
specified by the size/drive/head register and the current bank to
cylinder o.
If track 0 is not detected after 2047 step pulses
have been issued, a track 0 not found error is placed into the
error register, and the error bit is set in the status register.
The stepping rate field of the command is not used for the
restore operation itself but is stored in the controller to be
used as the stepping rate value for operations requiring implied
seek operations, such as read and write commands. The restore
operation waits until a seek complete is detected before issuing
another step pulse. Busy is cleared, and an interrupt is sent to
the system at the completion of this co~and.
Read - 20H.
The Busy bit is set upon receipt of this command.
If the disk drive heads are not already at the specified starting
address, an implied Seek is performed using the stepping rate
previously specified by a Restore or Seek command.
If no
stepping rate has been specified, the default rate of 6.5
milliseconds is used.
The sector is then read into the sector
buffer, ECC (error detection/correction) is applied if
so
specified, and the corrected data bit is activated if required.
If the long bit is set in the command, ECC is not performed on
the input data.
Instead, four extra bytes of data are read from
the disk into the sector buffer.
If an uncorrectab1e error
occurs during the read operation, the appropriate error code is
loaded into the error register, and the error bit is set in the
status register.
The controller then sets the data request bit
in the status register, clears Busy, and sends an interrupt to
the system. The Read command terminates after the system empties
the data register.
For multiple sector read operations, the above sequence repeats
until all sectors are transferred.
If an uncorrectab1e error
occurs,
the
command
terminates.
Note that even if an
uncorrectab1e error does occur, the command does not terminate
until the system empties the data register.
Write - 30H.
Upon receiving the Write command, the controller
sets the Data Request bit in the status register and waits until
the system fills the sector buffer. When the data register is
full, the Busy bit is set. If the heads are not at the specified
starting address, an implied Seek is performed using the stepping
rate previously specified by a Restore or Seek command.
If no
stepping rate has been specified, the default rate of 6.5
milliseconds is used. The sector data is then written to the
disk.
If an error occurs during the write operation, the
appropriate error code is loaded into the error register, and the
error flag is set.
The Write command is terminated by the
6-40
2241092-0001
BUSINESS-PRO Hardware Reference
Hardware Options
controller clearing Busy and sending an interrupt to the system.
For multiple sector write operations, the data request bit is set
each time the controller is ready to receive the next sector
until all sectors are transferred or an un correctable error
occurs.
If an uncorrectable error occurs, the command is
terminated as described above.
Verify - 40H. The Verify command operates in the same manner as
the Read command, with the exception that the long bit is not
valid for this command.
Format Track - 50H.
The Format Track
command
causes
the
controller to raise the data request bit and wait until the
system has filled the sector buffer.
Sector buffer
full
activates the Busy bit in the status register.
If the heads are
not at the specified starting address, an implied Seek is
performed, using the stepping rate previously specified by a
Restore or Seek command. If no stepping rate was specified, the
default rate of 6.5 milliseconds is used.
The track is then formatted according to the data that was loaded
into the sector buffer.
The command is terminated by the
controller clearing the Busy bit and sending an interrupt to the
system. No error checking is done by this command.
Seek - 70H.
The Seek command sets the Busy flag in the status
register and then steps the heads to the sector address specified
by the system. The stepping rate field of the command is used
for the seek operation and is also stored in the controller to be
used as the stepping rate for operations requiring implied seek
operations, such as read and write commands. The Seek command is
terminated by the controller clearing Busy and sending an
interrupt to the system. The controller does not wait for the
drive to complete the seek operation before terminating the
command.
Select Drive Bank - BOH.
Immediately upon receiving the Select
Drive Bank command, peripheral controller hardware raises the
Busy flag in the system status register. At the same time, the
Command Ready bit goes active, activating the B049 microprocessor
IC. The Bank bit of the command is then stored away for use on
all subsequent commands.
Busy is cleared, and an interrupt is
sent to the system at the completion of this command.
Perform Internal Diagnostic - 90H. The Busy bit is set in the
status
register.
The
internal processor, the Winchester
controller IC, the sector buffer, and the
size/drive/head
register are tested for correct operation. The error register is
loaded to reflect the status of the hardware. Busy is cleared
and an interrupt is sent to the system at the completion of this
command.
Upon completion of the command, the error register is
read to determine the results of the diagnostics command.
2241092-0001
6-41
Hardware Options
BUSINESS-PRO Hardware Reference
Set Parameters - 91H.
The Busy bit is set in the
status
register, and the drive parameters are stored by the controller
for use in track and cylinder boundary crossing for multiple
sector operations. Before loading this command into the command
register, the sector count register must be loaded with the
number of sectors per track and the size/drive/head register must
be loaded with the drive and the numbe~ of heads. Busy is
cleared, and an interrupt is generated and sent to the system
upon completion of this command.
6-42
2241092-0001
Hardware Options
BUSINESS-PRO Hardware Reference
6.3.5 Winchester Disk Drives
The optional Winchester disk drives that can be used with
Winchester controller on the BUSINESS-PRO are as follows:
*
2l-megabyte disk drive
*
40-megabyte disk drive
*
72-megabyte disk drive
*
120-megabyte disk drive
the
The features of these are described in the following paragraphs.
6.3.5.1
Types of Winchester Disk Drives.
The label on each
Winchester disk drive specifies the drive type.
Table 6-24 lists
the types of Winchester disk drives currently available from
Texas Instruments that can be used with the BUSINESS-PRO.
TI
part numbers and parameters for each type are also provided.
Table 6-24
Characteristics
TI part number
Formatted capacity
Cylinders
Heads
Drive tracks
Reduced write cur.
Write precomp cyl.
Control byte
Landing zone
Sectors/track
Bytes/sector
Avg. access time
Unformatted cap.
Capacity/track
Comments
16
2243928-2
21MB
615
4
2460
N/R
128
00
656
17
512
85ms
25498368
1046
Rack&Pin
BUSINESS-PRO Drive Types
18
2245231-1
40MB
925
9
4625
N/R
0
00
Auto
17
512
30ms
48174000
9634800
Rotary VC
Drive Types
20
2245231-3
72MB
925
9
8325
N/R
0
00
Auto
17
512
30 ms
86713200
9634800
Rotary VC
25
2243928-1
10MB
612
2
1224
N/R
128
00
656
17
512
85 ms
12749184
10416
Rotary VC
26
2235275-1
18MB
697
3
2091
N/R
128
00
Head Lock
17
512
40 ms
21779856
10416
Rotary VC
28
2238028-1
120MB
918
15
13770
N/R
None
08
Auto
17
512
30 ms
143.43MB
10416
Rotary VC
Upon system start-up, the program automatically installs the disk
drives in the system.
The program also installs the pertinent
parameters for each drive.
Table 6-25 provides a list of all the
drive types that can be used on the BUSINESS-PRO with a
comparison of the Texas Instruments and IBM types of Winchester
disk drives.
2241092-0001
6-43
Hardware Options
Table 6-25
TI
Type
1
2
2
3
4
5
6
7
8
9
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Comparison of Winchester Disk Drive Types
IBM
Type Cylinder
1
4
BUSINESS-PRO Hardware Reference
10
11
12
13
14
15
2
10
11
12
NA
NA
NA
NA
4
NA
NA
NA
NA
NA
306
615
615
940
940
615
462
733
900
820
855
855
306
733
615
925
925
925
925
925
1024
1024
1024
612
697
612
918
640
Write
Landing
Heads Precompensation Zone
4
4
6
8
6
4
8
5
15
128
305
300
615
300
615
512
940
512
940
No
615
256
511
No
733
No
901
3
No
820
5
No
855
7
No
855
8
128
319
7
No
733
Reserved - set to zeros
4
0
Auto
3
0
Auto
5
0
Auto
7
0
Auto
Auto
9
0
3
512
Auto
5
512
Auto
7
512
Auto
8
512
Auto
2
128
656
3
128
Hd lock
2
400
None
15
None
Auto
4
256
Auto
Formatted
capacity
(Megabytes)
10
21
32
65
49
21
32
31
117
21
37
52
21
44
21
24
40
56
72
26
44
62
71
10
18
10
119
22
------------------------------------------------------ ---~----~--
6-44
2241092-0001
BUSINESS-PRO Hardware Reference
Hardware Options
6.3.6 2l-Megabyte Winchester Disk Drive
The
optional
2l-megabyte
Winchester
disk
drive
is
a
microprocessor-controlled disk drive that can handle data at a
rate of 5 megabits per second. The disk drive features open-loop
stepper head positioning and rack-pinion head actuators. The
interface between the disk drive and the Winchester
disk
controller is the industry-standard ST-506.
6.3.6.1
2l-Megabyte Winchester Drive Kit.
The 2l-megabyte
Winchester disk drive kit, TI Part No. 2240994-0001 includes the
following items:
*
2l-megabyte, half-height Winchester disk drive, TI
No. 2243928-0002
*
Daisy-chain cable, TI Part No.
*
Data cable, TI Part No.
*
Half-Height Winchester Drives
2241055-0001
Part
2240837-0001
2240835-0001
manual,
TI
Part
No.
NOTE
Installation of the half-height Winchester
disk drive in drive positions 1 through 4
requires an optional Winchester cable kit, TI
Part No.
2536057-0001.
Installation as a
second
drive
in XENIX systems requires
optional Winchester cable kit, TI Part No.
2536057-0002.
6.3.6.2 2l-Megabyte Disk Drive Tabulated Information. Tables 626 through 6-28 provide tabulated information about the 21megabyte Winchester disk drive.
2241092-0001
6-45
Hardware Options
Table 6-26
Signal
BUSINESS-PRO Hardware Reference
21-Megabyte Disk Drive Control Connector JI
Pin
Number
Description
2
Reserved.
HEAD SELECT 0HEAD SELECT 1HEAD SELECT 2-
14
18
4
The host controller sets these
signals to select one of the four
read/write heads. These signals
form a 3-bit binary code in the
range of 000 (head 0) through 100
(head 4).
WRITE GATE-
6
The host controller generates this
signal to enable the write driver.
This allows data to be recorded on
the disk via a selected read/write
head. During read operations, or
when step pulses are transmitted to
the drive, this signal must be
inactive.
SEEK COMPLETE-
8
The disk drive generates this
signal to indicate to the host
controller that the drive is
selected and that the read/write
heads are in position. SEEK
COMPLETE- must be active before a
read or write operation is
attempted. Anyone of the following
conditions deactivates the signal:
The last leading edge of a step
pulse or series of step pulses
plus a SOO-nanosecond delay has
occurred.
A seek operation is in progress.
A recalibration sequence is in
progress.
TRACK 0-
10
The disk drive generates this
signal to indicate to the host
controller that the read/write
heads are positioned at track o.
6-46
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-26
Hardware Options
21-Megabyte Disk Drive Control Connector Jl (Continued)
Signal
Pin
Number
WRITE FAULT-
12
Description
The disk drive generates this
signal to indicate to the host
controller that WRITE GATE- is
active and that one of the
following conditions is true:
Write current is absent.
Write data is absent.
The drive is not ready.
An invalid read/write head has
been selected.
Incorrect dc voltage levels.
SEEK COMPLETE- is inactive.
WRITE FAULT- can also indicate that
WRITE GATE- is inactive while write
current is present.
An active WRITE FAULT- signal
disables all write operations. The
controller latches this signal on
its leading edge, thus ensuring the
detection of any transient
condition.
16
Reserved.
INDEX-
20
The disk drive generates this
signal to indicate to the host
controller that it has detected
the beginning of a track.
READY-
22
The disk drive generates this
signal to indicate to the host
controller that the drive is
receiving power, has reached its
proper operating speed, and that
the read/write heads are over
the recording zone.
2241092-0001
Hardware Options
Table 6-26
2l-Megabyte Disk Drive Control Connector Jl (Continued)
Pin
Number
Signal
STEP-
DRIVE
DRIVE
DRIVE
DRIVE
BUSINESS-PRO Hardware Reference
SELECT·
SELECT
SELECT
SELECT
DIRECTION IN-
1234-
Description
24
The host controller generates this
signal to cause the read/write
heads to move one cylinder in the
direction specified by the state of
DIRECTION IN-. Pulse dUration can
vary between 2 and 200 microseconds
with a minimum interval of 5
microseconds between pulses. If the
direction of head movement is
toward track 0 and the number of
step pulses exceeds the number of
cylinders, the drive recalibrates
the head to track O.
26
28
The host controller generates these
signals to select the active drive
as defined by the position of the
drive-select switches on the disk
drives. Since all control signals
are gated with DRIVE SELECT-, one
of these signals must be active to
enable communication with the
controller.
30
32
34
The host controller generates this
signal to specify the direction of
read/write head movement. A high
condition of DIRECTION IN- causes
head movement toward track 0; a low
condition causes inward movement of
the heads.
NOTE:
All odd-numbered pins are connected to ground.
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-27
Signal
DRIVE SELECTED-
Hardware Options
2l-Megabyte Disk Drive Data Connector J2
Pin
Number
Description
1
The disk drive activates this
signal 1 microsecond after
detecting the leading edge of
DRIVE SELECT- and deactivates it
1 microsecond after the trailing
edge. This signal acknowledges to
the host that the drive is
selected.
3
Reserved.
5
Reserved.
7
Reserved.
9
Reserved.
SIGNAL GROUND
11
Signal ground.
+MFM WRITE DATA
-MFM WRITE DATA
13
14
This differential signal pair
carries the MFM-encoded data to the
disk drive during a write-to-disk
operation. All disk tracks greater
than 128 are write ·precompensated.
SIGNAL GROUND
15
Signal ground.
+MFM READ DATA
-MFM READ DATA
17
18
This differential signal pair
carries data to the host during
read-from-disk operations.
SIGNAL GROUND
20
Signal ground.
NOTE:
All other pins are connected to ground.
2241092-0001
6-49
Hardware Options
Table 6-28
BUSINESS-PRO Hardware Reference
21-Megabyte Disk Drive Power ConnectorJ3
Pin Number
Voltage
+12 volts dc
+12 volts dc return
+5 volts dc return
+5 volts dc
1
2
3
4
6.3.6.3 Configuring a 21-Megabyte Disk Drive.
A DIP switch
determines the drive number for any given drive (Figure 6-10).
Switches 5 through 8 specify drive numbers 4 through
1,
respectively.
All drives are shipped from the factory with the
switches configured as drive 1 (SW8 is ON).
A
plug-in,
terminating resistor pack must be installed in the last drive of
a daisy-chain configuration and must be removed for all others.
All drives are shipped from the factory with the terminating
resistor pack installed.
DIP switch
pack (E1)
terminating
resistor
pack
ON~~~~~~~
234
5
678
r------------. RPI
J2
19
I
2287508
Figure 6-10
21-Megabyte Disk Drive Select Switches and Terminator
6-50
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-29
Hardware Options
2l-Megabyte Disk Drive Performance Specifications
Specification
Characteristic
Unformatted data capacity:
Bytes per track
10 416
Bytes per surface
6 374 592
Bytes per drive
25 498 368
Media configuration:
Platters per drive
2
Cylinders per drive
612
Tracks per cylinder
4
Sectoring method
Soft
Recording method
MFM-encoded data
Data transfer rate
5 megabits per
second (nominal)
Rotational speed
3 600 ±.36 rpm
Average rotational latency
8.33 milliseconds
Drive start time
25 seconds
Drive stop time
20 seconds
Minimum step pulse rate
2 microseconds
Maximum step pulse period
200 microseconds
Typical seek time:
(NOTE 1)
Track-to-track
15 milliseconds
Buffered settling
85 milliseconds (avg)
Maximum buffered
including settling
190 milliseconds
Window margin
2241092-0001
+18 nanoseconds
(minimum)
6-51
Hardware Options
Table 6-29
BUSINESS-PRO Hardware Reference
2l-Megabyte Disk Drive Performance Specifications (Cont)
Specification
Characteristic
Defective tracks per
drive (NOTE 2)
30 (maximum)
Defect-free media
location
Cylinder 0
Index pulses per
revolution
1
NOTE:
1. Seek time for any given seek operation is measured from the
last step pulse issued. Average seek time is defined as the
quotient of the sum of the time required for all possible
movements divided by the total number of movements.
2. A defective track is defined as a track that contains one
or more media defects.
Table 6-30
2l-Megabyte Disk Drive Power Requirements
Item
Value
Voltage tolerance
+5 percent
Typical operating current:
+5 volts dc line
+12 volts dc line
0.75 ampere
0.75 ampere
Maximum starting current:
+5 volts dc line
+12 volts dc line
1.3 amperes
4.5 amperes
Ripple (equivalent
resistive load):
+5 volts dc line
+12 volts dc line
2 percent
1 percent
(peak-to-peak)
Power consumption:
Typical
Maximum
13.0 watts
15.3 watts
6-52
2241092-0001
BUSINESS-PRO Hardware Reference
Hardware Options
6.3.7 40-Megabyte Winchester Disk Drive
The optional 40-megabyte Winchester disk drive is a full-height
disk drive that features a rotary voice-coil positioner that is
controlled by a closed-loop servo system. To protect its disk
surfaces, the drive positions and locks its read/write heads over
a dedicated landing zone whenever power is removed. The disk
drive interface to the host controller is the industry-standard
ST506.
6.3.7.1
40-Megabyte Winchester Disk Drive Kit. The 40-megabyte
Winchester disk drive kit, TI Part No. 2241087-0001 includes the
following items:
*
40-megabyte, full-height Winchester disk drive, TI
No.
2245231-0001
*
Internal
peripheral
2240835-0001
*
Full-Height Winchester Drives
2536072-0001
cable
assembly,
manual,
TI
TI
Part
Part
Part
No.
No.
NOTE
Installation of the 40-megabyte Winchester
disk drive in drive positions 1 through 4
requires the use of an optional Winchester
cable kit, TI
Part
No.
2536057-0001.
Installation as a second drive in' XENIX
systems requires optional Winchester cable
kit, TI Part No.
2536057-0002.
6.3.7.2 40-Megabyte Disk Drive Tabulated Information. Tables 631 through 6-.35 provide tabulated information about the 40megabyte Winchester disk drive.
NOTE
The 40-megabyte disk drive control connector
and data connector are both designated as J3.
Both connectors are edge connectors located
on two different printed wiring boards inside
the unit. The control connector has 34-pins;
the data connector has 20 pins.
2241092-0001
6-53
Hardware Options
Table 6-31
SELECT
SELECT
SELECT
SELECT
40-Megabyte Disk Drive Control Connector J3
Pin
Number
Signal
HEAD
HEAD
HEAD
HEAD
BUSINESS-PRO Hardware Reference
0123-
14
18
4
2
Signal Description
The host controller sets these
signals to select one of the nine
read/write heads. These signals
form a 4-bit binary code in the
range of 0000 (head 0) through
1000 (head 8).
WRITE GATE-
6
The host controller generates this
signal to enable the write driver.
This allows data to be recorded on
the disk via the selected read/write
head.
For read operations, or when
step pulses are transmitted to the
drive, this signal must be active.
SEEK COMPLETE-
8
The disk drive generates this
signal to indicate to the host
controller that the drive is
selected and that the read/write
heads are in position. SEEK
COMPLETE- must be active before
a read or write operation is
completed. Anyone of the
following conditions deactivates
SEEK COMPLETE-:
The last leading edge of a step
pulse or series of step pulses
plus a 500 nanosecond delay.
A seek operation is in progress.
A recalibration sequence is in
progress.
TRACK 0-
10
The disk drive generates this
signal to indicate to the host
controller that the read/write
heads are positioned at track o.
6-54
2241092-0001
Hardware Options
BUSINESS-PRO Hardware Reference
Table 6-31
40-Megabyte Disk Drive Control Connector J3 (Continued)
Signal
WRITE FAULT-
Pin
Number
12
Description
The disk drive generates this
signal to indicate to the host
controller that WRITE GATE- is
active and that one of the
following conditions is true:
Write current is absent.
Write data is absent.
The drive is not ready.
An invalid read/write head
has been selected.
Incorrect dc voltage levels.
SEEK COMPLETE- is inactive.
WRITE FAULT- can also indicate
that WRITE GATE- is inactive
while write current is present.
An active WRITE FAULT- signal
disables all write operations.
The controller latches this
signal on its leading edge,
thus ensuring the detection of
any transient condition.
16
Reserved.
INDEX-
20
The disk drive generates this
signal to indicate to the host
controller that the drive has
detected the beginning of a
track.
READY-
22
The disk drive generates this
signal to indicate to the host
controller that the drive is
receiving power, has reached its
proper operating speed, and the
read/write heads are over the
recording zone.
2241092-0001
6-55
BUSINESS-PRO Hardware Reference
Hardware Options
Table 6-31
40-Megabyte Disk Drive Control Connector J3 (Continued)
Pin
Number
Signal
STEP-
DRIVE
DRIVE
DRIVE
DRIVE
SELECT
SELECT
SELECT
SELECT
DIRECTION IN-
1234-
Description
24
This controller-generated signal
causes the read/write heads to move
one cylinder in the direction
specified by the state of DIRECTION
IN-. Pulse length can vary between
2 and 200 microseconds with a
minimum interval of 8 microseconds
between pulses. If the direction of
head movement is toward track 0 and
the number of step pulses exceeds
the number of cylinders, the drive
recalibrates the head to track O.
26
These controller-generated signals
select the active drive as defined
by the position of the drive-select
switches on the disk drives. Since
all control signals are gated with
DRIVE SELECT-, one of these signals
must be active to enable communication with the controller.
28
30
32
34
This controller-generated signal
specifies the direction of head
movement. High causes head movement
toward track 0; low causes 'inward
head movement.
NOTE:
All odd-numbered pins are connected to ground.
6-56
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-32
Hardware Options
40-Megabyte Disk Drive Data Connector J3
Pin
Number
Signal
Description
DRIVE SELECTED-
1
The disk drive activates this signal
1 microsecond after detecting the
leading edge of DRIVE SELECT- and
deactivates it 1 microsecond after
the trailing edge. This signal
acknowledges to the host that the
drive is selected.
+MFM WRITE DATA
-MFM WRITE DATA
13
14
This differential signal pair carries
the MFM-encoded data to the disk drive
during a write-to-disk operation. All
disk tracks greater than 128 are write
precompensated.
+MFM READ DATA
-MFM READ DATA
17
18
This differential signal pair carries
data to the host during read-from-disk
operations.
NOTE:
Pins 3, 5, 7, and 9 are reserved. Pins 11, 15, and 20 are
connected to signal ground. All other pins are connected to
chassis ground.
Table 6-33
40-Megabyte Disk Drive Power Connector J2
Pin Number
2241092-0001
Voltage
1
+12 volts dc
2
+12 volts dc return
3
+5 volts dc return
4
+5 volts dc
6-57
Hardware Options
BUSINESS-PRO Hardware Reference
6.3.7.3 Configuring 40-Megabyte Disk Drive. An 8-pin, doublerow (4-position) header and a jumper plug determine the drive
number for any given drive (Figure 6-11).
Jumper positions 1
through 4 specify drive numbers 1 through 4, respectively. All
drives are shipped from the factory with the jumper configured as
drive 1 (jumper plugged into position 1).
A plug-in, terminating resistor pack must be installed in the
last drive of a daisy-chain configuration and must be removed for
all" others.
All drives are shipped from the factory with the
terminating resistor pack installed.
The radial-select option jumper allows the user to select a
radial-cabling configuration in which each drive in the system
requires a separate control and data cable. Drives are shipped
from the factory with this jumper removed to allow the drive to
be connected in a daisy-chain configuration.
6-58
2241092-0001
BUSINESS-PRO Hardware Reference
drive select ~----jumper
~---configurations
__- - .....---
Hardware Options
drive select 1
drive select 2
drive select 3
drive select 4
radial select option (open)
terminator
pack
Power
--
cable
I
2
3
4
+12 V DC
+12 V RET
+ 5 V RET
+ 5VDC
2287509
Figure 6-11
40- and 72-Megabyte Disk Drive Select Switches and Terminator
2241092-0001
6-59
Hardware Options
Table 6-34
BUSINESS-PRO Hardware Reference
40-Megabyte Disk Drive Performance Specifications
Specification
Characteristic
Unformatted data capacity:
Bytes per track
10 416
Bytes per surface
9 634 800
Bytes per drive
48 174 000
Media configuration:
Platters per drive
3
Servo surfaces
1
Data surfaces
5
Cylinders per drive
925
Tracks per cylinder
5
sectoring method
Soft
Recording method
MFM-encoded data
Data transfer rate
5 megabits per
second (nominal)'
Rotational speed
3 600 ±18 rpm
Rotational latency
8.33 milliseconds
(average)
Drive start time
35 seconds
Drive stop time
30 seconds
Step pulse period:
Minimum
8 microseconds
Maximum
200 microseconds
6-60
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-34
Hardware Options
40-Megabyte Disk Drive Performance Specifications (Cont)
Characteristic
Specification
Seek times (typical):
Track-to-track
7 milliseconds
Average
35 milliseconds
925 tracks
85 milliseconds
Maximum bit shift
+31 nanoseconds
Media defects per
drive
44
Defect-free
cylinders
0, 1, and 2
Index pulses per
revolution
1
Write-to-read
recovery time
10 microseconds
(maximum)
Table 6-35
40-Megabyte Disk Drive DC Power Requirements
Value'
Item
Voltage tolerance
j:5 percent
Typical operating current:
+5 volts dc line
+12 volts dc line
0.75 ampere
2.00 amperes
Maximum operating current:
+5 volts dc line
+12 volts dc line
0.9 ampere
2.4 amperes
Maximum starting current:
+5 volts dc line
+12 volts dc line
1.3 amperes
4.5 amperes
Ripple (peak-to-peak):
+5 volts dc line
+12 volts dc line
50 millivolts
100 millivolts
2241092-0001
6-61
Hardware Options
BUSINESS-PRO Hardware Reference
6.3.8 72-Megabyte Winchester Disk Drive
The optional 72-megabyte Winchester disk drive is a full-height
disk drive that features a rotary voice-coil positioner that is
controlled by a closed-loop servo system. To protect its disk
surfaces, the drive positions and locks its read/write heads over
a dedicated landing zone whenever power is removed. The disk
drive interface to the host controller is the industry-standard
ST506.
Kit. The
72No. 2241087-0002
6.3.8.1
72-Megabyte Winchester Disk Drive
megabyte Winchester disk drive kit, TI Part
includes the following items:
*
72-megabyte, full-height Winchester disk drive, TI Part
No.
2245231-0003
*
Internal peripheral
2240835-0001
*
Full-Height Winchester Drives
2536072-0001
cable
assembly,
manual,
TI
TI
Part
Part
No.
No.
NOTE
Installation of the 72-megabyte Winchester
disk drive in drive positions 1 through 4
requires an optional Winchester cable kit, TI
Part No. 2536057-0001.
Installation as a
second
drive
in XENIX systems requires
optional Winchester cable kit, TI Part No.
2536057-0002.
6.3.8.2 72-Megabyte Disk Drive Tabulated Information. Tables 636 through 6-40 provide tabulated information about the 72megabyte Winchester disk drive.
NOTE
The 72-megabyte disk drive control connector
and data connector are both designated as J3.
Both connectors are edge connectors located
on two different printed wiring boards inside
the unit. The control connector has 34-pins;
the data connector has 20 pins.
6-62
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-36
Hardware Options
72-Megabyte Disk Drive Control Connector J3
Pin
Number
Signal
Signal Description
14
18
4
2
The host controller sets these
signals to select one of the nine
read/write heads. These signals
form a 4-bit binary code in the
range of 0000 (head 0) through
1000 (head 8).
WRITE GATE-
6
The host controller generates this
signal to enable the write driver.
This allows data to be recorded on
the disk via the selected read/write
head. During read operations, or when
step pulses are transmitted to the
drive, this signal must be inactive.
SEEK COMPLETE-
8
The disk drive generates this signal
to indicate to the host controller
that the drive is selected and that
the read/write heads are in position.
SEEK COMPLETE- must be active before
a read or write operation is
attempted. Anyone of the following
conditions deactivates the signal:
HEAD
HEAD
HEAD
HEAD
SELECT
SELECT
SELECT
SELECT
a123-
The last leading edge of a step
pulse or series of step pulses
plus a SaO-nanosecond delay.
A seek operation is in progress.
A reca1ibration sequence is in
progress.
TRACK 0-
2241092-0001
10
The disk drive generates this
signal to indicate to the host
controller that the read/write
heads are positioned at track O.
6-63
BUSINESS-PRO Hardware Reference
Hardware Options
Table 6-36
72-Megabyte Disk Drive Control Connector J3 (Continued)
Signal
Pin
Number
WRITE FAULT-
12
Description
The disk drive generates this
signal to indicate to the host
controller that WRITE GATE- is
active and that one of the
following conditions is true:
write current is absent.
Write data is absent.
The drive is not ready.
An invalid read/write head
has been selected.
Incorrect dc voltage levels.
SEEK COMPLETE- is inactive.
WRITE FAULT- can also indicate
that WRITE GATE- is inactive
while write current is present.
An active WRITE FAULT- signal
disables all write opera~ions.
The controller latches this
signal on its leading edge,
thus ensuring the detection of
any transient condition.
16
Reserved.
INDEX-
20
The disk drive generates this
signal to indicate to the host
controller that it has detected
the beginning of a track.
READY-
22
The disk drive generates this
signal to indicate to the host
controller that the drive is
receiving power, has reached its
proper operating speed, and the
read/write heads are over the
recording zone.
6-64
2241092-0001
Hardware Options
BUSINESS-PRO Hardware Reference
Table 6-36
72-Megabyte Disk Drive Control Connector J3 (Continued)
Pin
Number
Signal
STEP-
DRIVE
DRIVE
DRIVE
DRIVE
SELECT
SELECT
SELECT
SELECT
DIRECTION IN-
1234-
Description
24
The host controller generates this
signal to cause the read/write
heads to move one cylinder in the
direction specified by the state
of DIRECTION IN-. Pulse duration can
vary between 2 and 200 microseconds
with a minimum interval of 8 microseconds between pulses. If the
direction of head movement is
toward track 0 and the number of
step pulses exceeds the number of
cylinders, the drive recalibrates
the head to track O.
26
28
30
The host controller generates these
signals to select the active drive
as defined by the position of the
drive-select switches on the disk
drives. Since all control signals
are gated with DRIVE SELECT-, one
of these signals must be active to
enable communication with the
controller.
32
34
The host controller generates this
signal to specify the direction of
read/write head movement. A high
condition of DIRECTION IN- causes
head movement toward track 0; a
low condition causes inward
movement of the heads.
NOTE:
All odd-numbered pins are connected to ground.
2241092-0001
6-65
Hardware Options
Table 6-37
BUSINESS-PRO Hardware Reference
72-Megabyte Disk Drive Data Connector J3
Pin
Number
Signal
Description
DRIVE SELECTED-
1
The disk drive activates this
signal 1 microsecond after
detecting the leading edge of
DRIVE SELECT- and deactivates
it 1 microsecond after the
trailing edge. This signal
acknowledges to the host that
the drive is selected.
+MFM WRITE DATA
-MFM WRITE DATA
13
14
This differential signal pair
carries the MFM-encoded data to
the disk drive during a write-todisk operation. All disk tracks
greater than 128 are write
precompensated.
+MFM READ DATA
-MFM READ DATA
17
18
Thi~ differential signal pair
carries data to the host during
read-from-disk operations.
NOTE:
Pins 3, 5, 7, and 9 are reserved. Pins 11, 15, and 20 are
connected to signal ground. All other pins are connected to
chassis ground.
Table 6-38
72-Megabyte Disk Drive Power Connector J2
Pin Number
Voltage
1
+12 volts dc
2
+12 volts dc return
3
+5 volts dc return
4
+5 volts dc
6-66
2241092-0001
BUSINESS-PRO Hardware Reference
Hardware Options
6.3.8.3 Configuring 72-Megabyte Disk Drive. An 8-pin, doub1erow (4-position) header and a jumper plug determine the drive
number for any given drive. Jumper positions 1 through 4 specify
drive numbers 1 through 4, respectively. All drives are shipped
from the factory with the jumper configured as drive 1 (jumper
plugged into position 1). Refer to Figure 6-11.
A plug-in, terminating resistor pack must be installed in the
last drive of a daisy-chain configuration and removed for all
others. All drives are shipped from the factory with the
terminating resistor pack installed.
The radial-select option jumper allows the user to select a
radial-cabling configuration in which each drive in the system
requires a separate control and data cable. Drives are shipped
from the factory with this jumper removed to allow the drive to
be connected in a daisy-chain configuration.
Table 6-39
72-Megabyte Disk Drive Performance Specifications
Characteristic
Specification
Unformatted data capacity:
Bytes per track
10 416
Bytes per surface
9 634 800
Bytes per drive
86 713 200
Media configuration:
Platters per drive
5
Servo surfaces
1
Data surfaces
9
Cylinders per drive
925
Tracks per cylinder
9
Sectoring method
Soft
Recording method
MFM-encoded data
Data transfer rate
5 megabits per
second (nominal)
)
2241092-0001
6-67
Hardware Options
Table 6-39
BUSINESS-PRO Hardware Reference
72-Megabyte Disk Drive Performance Specifications (Cont)
Characteristic
Specification
Rotational speed
3 600 ±18 rpm
Rotational latency
8.33 milliseconds
(average)
Drive start time
35 seconds
Drive stop time
30 seconds
Step pulse period:
Minimum
8 microseconds
Maximum
200 microseconds
Seek times (typical):
Track-to-track
7 milliseconds
Average
35 milliseconds
925 tracks
85 milliseconds
Maximum bit shift
+31 nanoseconds
Media defects per
drive
44
Defect-free
cylinders
o
Index pulses per
revolution
1
Write-to-read
recovery time
10 microseconds
(maximum)
6-68
and 1
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-40
Hardware Options
72-Megabyte Disk Drive DC Power Requirements
Item
Value
Voltage tolerance
.±.5 percent
Typical operating current:
+5 volts dc line
+12 volts dc line
0.75 ampere
2.00 amperes
Maximum operating current:
+5 volts dc line
+12 volts dc line
0.9 ampere
2.4 amperes
Maximum starting current:
+5 volts dc line
+12 volts dc line
1.3 amperes
4.5 amperes
Ripple (peak-to-peak):
+5 volts dc line
+12 volts dc line
50 millivolts
100 millivolts
6.3.9 120-Megabyte Winchester Disk Drive
The optional 120-megabyte Winchester disk drive is a full-height
disk drive that features a rotary voice-coil positioner that is
controlled by a closed-loop servo system. To'protect its disk
surfaces, the drive positions and locks its read/write heads over
a dedicated landing zone whenever power is removed.
The disk
drive interface to the host controller is the industry-standard
ST506.
6.3.9.1 120-Megabyte Winchester Disk Drive Kit.
The
120megabyte Winchester disk drive kit, TI Part No. 2541087-0001
includes the following items:
*
120-megabyte, full-height Winchester disk drive, TI Part
No.
2238028-0001
*
Internal peripheral
2240991-0001
*
Full-Height Winchester Drives
2536072-0001
2241092-0001
cable
6-69
assembly,
manual,
TI
TI
Part
Part
No.
No.
BUSINESS-PRO Hardware Reference
Hardware Options
NOTE
Installation of the l20-megabyte Winchester
disk drive in drive positions 3 or 4 requires
an optional Winchester cable kit, TI Part No.
2240835~OOOl.
Installation as a second drive
in
XENIX
systems
requires an optional
Winchester cable kit, TI Part No.
25360570002.
6.3.9.2
l20-Megabyte Disk Drive Tabulated Information. Tables
6-41 through 6-44 provide tabulated information about the 120megabyte Winchester disk drive.
NOTE
The l20-megabyte disk drive control connector
(Jl)
and
data connector (J2) are edge
connectors located on two different printed
wiring boards inside the unit. The control
connector has 34-pins; the data connector has
20 pins.
6-70
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-41
SELECT
SELECT
SELECT
SELECT
120-Megabyte Disk Drive Control Connector Jl
Pin
Number
Signal
HEAD
HEAD
HEAD
HEAD
Hardware Options
0123-
14
18
4
2
Signal Description
The host controller sets these
signals to select one of the nine
read/write heads. These signals
form a 4-bit binary code in the
range of 0000 (head 0) through
1000 (head 8).
WRITE GATE-
6
The host controller generates this
signal to enable the write driver.
This allows data to be recorded on
the disk via the selected read/write
head. During read operations, or
when step pulses are transmitted to
the drive, this signal must be
inactive.
SEEK COMPLETE-
8
The disk drive generates this signal
to indicate to the host controller
that the drive is selected and that
the read/write heads are in position.
SEEK COMPLETE- must be active before
a read or write operation is attempted.
Anyone of the following conditions
deactivates the signal:
The last leading edge of a step
pulse or series of step pulses
plus a SOO-nanosecond delay.
A seek operation is in progress.
A recalibration sequence is in
progress.
TRACK 0-
2241092-0001
10
The disk drive generates this
signal to indicate to the host
controller that the read/write
heads are positioned at track o.
6-71
Hardware Options
Table 6-41
BUSINESS-PRO Hardware Reference
120-Megabyte Disk Drive Control Connector Jl (Continued)
Signal
Pin
Number
WRITE FAULT-
12
Description
The disk drive generates this
sign~l to indicate to the host
controller that WRITE GATE- is
active and that one of the
following conditions is true:
Write current is absent.
Write data is absent.
The drive is not ready.
An invalid read/write head
has been selected.
Incorrect dc voltage levels.
SEEK COMPLETE- is inactive.
WRITE FAULT- can also indicate
that WRITE GATE- is inactive
while write current is present.
An active WRITE FAULT- signal
disables all write operations.
The controller latches this
signal on its leading edge,
thus ensuring the detection of
any transient condition.
16
Reserved.
INDEX-
20
The disk drive generates this
signal to indicate to the host
controller that it has detected
the beginning of a track.
READY-
22
The disk drive generates this
signal to indicate to the host
controller that the drive is
receiving power, has reached its
proper operating speed, and the
read/write heads are over the
recording zone.
6-72
2241092-0001
(
I
\
BUSINESS-PRO Hardware Reference
Table 6-41
l20-Megabyte Disk Drive Control Connector Jl (Continued)
Pin
Number
Signal
STEP-
DRIVE
DRIVE
DRIVE
DRIVE
Hardware Options
SELECT
SELECT
SELECT
SELECT
DIRECTION IN-
1234-
Description
24
The host controller generates this
signal to cause the read/write
heads to move one cylinder in the
direction specified by the state of
DIRECTION IN-. Pulse duration can
vary between 2 and 200 microseconds
with a minimum interval of 8 microseconds between pulses. If the
direction of head movement is
toward track 0 and the number of
step pulses exceeds the number of
cylinders, the drive recalibrates
the head to track O.
26
28
The host controller generates these
signals to select the active drive
as defined by the position of the
drive-select switches on the disk
drives. Since all control signals
are gated with DRIVE SELECT-, one
of these signals must be active to
enable communication with the
controller.
30
32
34
The host controller'generates this
signal to specify the direction of
read/write head movement. A high
condition of DIRECTION IN- causes
head movement toward track OJ a
low condition causes inward
movement of the heads.
NOTE:
All odd-numbered pins are connected to ground.
2241092-0001
6-73
Hardware Options
Table 6-42
BUSINESS-PRO Hardware Reference
120-Megabyte Disk Drive Data Connector J2
Pin
Number
Signal
Description
DRIVE SELECTED-
1
The disk drive activates this
signal 1 microsecond after
detecting the leading edge of
DRIVE SELECT- and deactivates
it 1 microsecond after the
trailing edge. This signal
acknowledges to the host that
the drive is selected.
+MFM WRITE DATA
-MFM WRITE DATA
13
14
This differential signal pair
carries the MFM-encoded data to
the disk drive during a write-todisk operation. All disk tracks
greater than 128 are write
precompensated.
+MFM READ DATA
-MFM READ DATA
17
18
This differential signal pair
carries data to the host during
read~from-disk operations.
NOTE:
Pins 3, 5, 7, and 9 are reserved. Pins 2, 4, 6, 8, 11, 12, 15, 16,
and 20 are connected to signal ground.
Table 6-43
120-Megabyte Disk Drive Power Connector J3
Pin Number
Voltage
1
+12 volts dc
2
+12 volts dc return
3
+5 volts dc return
4
+5 volts dc
6-74
2241092-0001
BUSINESS-PRO Hardware Reference
Hardware Options
6.3.9.3 Configuring l20-Megabyte Disk Drive. A 6-pin, singlerow (4-position) header and a jumper plug (refer to Figure 6-12)
determine the drive number for any given drive, as follows:
Jumper Pins
5
4
2
1
and
and
and
and
Drive Select
6
5
3
2
1
2
3
4
All drives are shipped from the factory with the
jumper
configured as drive 1 (jumper on pins 5 and 6). A plug-in,
terminating resistor pack must be installed in the last drive of
a daisy-chain configuration and removed for all others. All
drives are shipped from the factory with the terminating resistor
pack installed.
DISK DRIVE 0
DEVICE-SELECT
JUMPER POSITION
2
3
4
5
DISK DRIVE 1
DEVICE-SELECT
JUMPER POSITION
6
2
3
4
5
- - - [!!!]
J2
,
,
6
-I
>
Jl
'\
/
/1 2 3 4 56,
//
"-....I •••• ··L. . /
/
J3
D
TERMINATOR
RESISTOR
PACK
2286177
Figure 6-12
2241092-0001
l20-Megabyte Disk Drive Select Pins and Terminator
6-75
Hardware Options
Table 6-44
BUSINESS-PRO Hardware Reference
120-Megabyte Disk Drive Performance Specifications
Characteristic
Specification
Unformatted data capacity:
Bytes per track
10 416
Bytes per surface
9 560 000
Bytes per drive
143 430 200
Formatted data capacity:
Bytes per track
8 704
Bytes per surface
7 990 000
Bytes per drive
120 000 000
Media configuration:
Platters per drive
8
Servo surfaces
1
Data surfaces
9
Cylinders per drive
918
Tracks per cylinder
15
Sectoring method
Soft
Recording method
MFM-encoded data
Data transfer rate
5 megabits per
second (nominal)
Rotational speed
3 600 +0 rpm, -7.2 rpm
Rotational latency
8.33 milliseconds
(average)
Drive start time
20 seconds, maximum
Drive stop time
10 seconds, maximum
6-76
2241092-0001
Hardware Options
BUSINESS-PRO Hardware Reference
Table 6-44
120-Megabyte Disk Drive Performance Specifications (Cont)
Specification
Characteristic
Step pulse period:
Minimum
2 microseconds
Maximum
200 microseconds
Seek times (maximum):
Track-to-track
5 milliseconds
Average
30 milliseconds
925 tracks
48 milliseconds
Maximum bit shift
+31 nanoseconds
Media defects per
drive
44
Defect-free
cylinders
o
Index pulses per
revolution
1
Write-to-read
recovery time
8 microseconds,
maximum
/
2241092-0001
6-77
and 1
Hardware Options
Table 6-45
BUStNESS-PRO Hardware Reference
120-Megabyte Disk Drive DC Power Requirements
Item
Value
Voltage tolerance
.±.
Typical operating current:
+5 volts dc line
+12 volts dc line
1.70 ampere
1.60 amperes
Maximum operating current:
+5 volts de line
+12 volts de line
1.9 ampere
2.5 amperes
Maximum starting current:
+5 volts dc line
+12 volts de line
1.9 amperes
4.5 amperes
Ripple (peak-to-peak):
+5 volts de line
+12 volts dc line
50 millivolts
120 millivolts
6-78
5 percent
2241092-0001
BUSINESS-PRO Hardware Reference
Hardware Options
6.3.10 Tape System
The optional BUSINESS-PRO tape system consists of a streaming
tape drive and a tape controller. The tape system provides lowcost backup for the Winchester disk drive and data transportation
from one system to another. The following paragraphs describe
the optional tape drive and the tape controller.
6.3.10.1
Tape Drive Kit.
The tape drive
2240836-0001, contains the following items:
kit, TI Part No.
*
60-megabyte tape drive, TI Part No.
*
Tape controller, TI Part No.
*
Tape controller cable assembly, TI Part No. 2240996-0001
*
Tape Backup Hardware manual, TI Part No. 2241043-0001
*
CT600 tape cartridge,
equivalent)
*
Streaming tape utility, TI Part No.
TI
2536125-0001
2536126-0001
Part
No.
2249438-0001
(or
2534765-0001
6.3.10.2
Tape Drive.
The tape drive is a 1/4-inch streaming,
cartridge tape drive that mounts in the same space as a 5 1/4inch floppy disk drive.
Tape Drive Features.
cartridge tape drive:
The
following
features
characterize the
*
Uses a nine-track, moving-head drive to read and/or
write data in either direction in a serpentine pattern
*
Uses the industry-standard QIC-24 data format
*
Has a built-in tape controller that uses a subset of the
QIC-02 command set
*
Uses either a 60-megabyte
(DC300XL) tape cartridge.
(DC600A)
or a 45-megabyte
Tape Drive Tabulated Information.
Tables 6-46
through
provide tabulated information about the tape drive.
2241092-0001
6-79
6-50
Hardware Options
Table 6-46
Signal
BUSINESS-PRO Hardware Reference
Tape Drive Interface Signals Connector Jl
Pin
Number
Description
GO-
2
Go control for the capstan servo system.
This input signal causes the tape drive
to begin tape motion in the direction
specified by the reverse (REY-) signal.
REY-
4
Direction control for the capstan servo
system. When active, this input signal
causes the tape drive to move the tape
in reverse upon activation of GO-.
TR3TR2TRlTRO-
6
Track select bits. These input signals
form a binary code that causes the tape
drive to select one of nine tracks. The
codes are as follows:
RST-
8
10
12
Track 0
TR3- through TRO- equal 0000
Track 1
TR3- through TRO- equal 0001
Track 2
TR3- through TRO- equal 0010
Track 3
TR3- through TRO- equal 0011
Track 4
TR3- through TRO- equal 0100
Track 5
TR3- through TRO- equal 0101
Track 6
TR3- through TRO- equal 0110
Track 7
TR3- through TRO- equal 0111
Track 8
TR3- through TRO- equal 1000
14
Reset. Activation of this signal for
a period of 70 microseconds or longer
causes the drive to reset its head
assembly to track O.
16
Reserved.
18
Reserved.
20
Reserved.
6-80
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-46
Signal
Hardware Options
Tape Drive Interface Signals -- Connector Jl (Cont)
Pin
Number
Description
DSO-
22
Drive 0 select. This input signal
enables output interface signals,
write current, and erase current.
The tape drive responds to DSOby generating a drive-selected
signal to the controller.
HC-
24
High-current select. The tape
controller activates this input
to the tape drive when it detects
that a 60-megabyte tape has been
installed in the tape drive. This
signal causes the tape drive to
increase its write current.
RDP-
26
Read-data pulses. This output signal
sends serial data to the controller
when recorded data passes under the
read head.
UTHLTH-
28
30
Upper and lower tape hole position
codes. These output signals indicate
to the controller the specific position
of the tape based on the position of
the tape holes with respect to the
drive's tape hole sensors.
SLD-
32
Selected response from tape drive.
This output signal indicates to the
controller that the tape drive has
recognized and responded to a DSOsignal.
CIN-
34
Cartridge in place. This output
signal indicates to the controller
that a tape cartridge has been
inserted in the tape drive.
USF-
36
Unsafe. The tape drive activates
this output signal to notify the
tape controller that it has detected
a write-protected tape cartridge.
When active, this signal prevents
any write or erase operations to
the tape.
2241092-0001
6-81
Hardware Options
Table 6-46
Signal
BUSINESS-PRO Hardware Reference
Tape Drive Interface Signals -- Connector Jl (Cont)
Pin
Number
Description
TCH-
38
Capstan tachometer pulse. The
controller generates eight of
these pulses for each capstan
revolution to control the
capstan speed. Each occurrence
of TCH- represents a tape
movement of 0.145 +0.003 inch
since the last occurrence.
WDAWDA+
40
42
Write-data. This differential
signal pair is sent to the
standard interface during the
time of an active write-enable
signal. The tape drive records
data at a nominal rate of 10 000
flux transitions per inch or a
data density of 8 000 bits per inch.
THD-
44
Read threshold. This input signal
causes the tape drive read
threshold to invoke a 35-percent
qualifying amplitude threshold.
46
Not used.
WEN-
48
Write-enable control. This input
signal allows write data to be
gated to the tape drive write head.
EEN-
50
Erase-enable control. Activation
of this input signal and selecting
track 0 causes the tape drive to
erase the entire tape.
NOTE:
All odd-numbered pins are connected to ground.
6-82
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-47
UTH-
LTH-
Hardware Options
Tape Position Codes
Tape Location
1
1
Beginning-of-tape (BOT). The BOT holes are located
nearest the recording area just to the right of
the tape hole sensor.
o
1
End-of-tape (EOT). The EOT holes are located
nearest the recording area just to the left of
the tape hole sensor.
1
o
Warning zone. The tape hole sensor is located
between the BOT hole and the load-point hole.
o
o
Recording zone. If a BOT or an EOT position
has occurred since the last tape cartridge
insertion, this code indicates that the tape
sensor is located between the load-point hole
and the early-warning hole. Otherwise, this
code indicates that the tape position is unknown.
Table 6-48
Tape Drive Power Connector J2
Voltage
Pin
2241092-0001
1
+12 volts dc
2
+12 volts dc return
3
+5
4
+5 volts dc return
6-83
volts dc
Hardware Options
Table 6-49
BUSINESS-PRO Hardware Reference
Tape Drive Performance Specifications
Specification
Characteristic
Number of tracks
9
Number of write head gaps
2
Number of read head gaps
2
Capacity:
DC600A cartridge
60 megabytes
DC300XL cartridge
45 megabytes
Tape Speed
90 +0.27 inches per second
(ips) long term (greater
than 180 inches)
90 ±0.63 ips short term
(less than 180 inches)
Backup time at 90 ips nonstop:
DC600A cartridge
12 minutes
DC300XL cartridge
9 minutes
Track capacity:
DC600A cartridge
6.67 megabytes
DC300XL cartridge
5.0 megabytes
Recording mode
Nonreturn-to-zero
change on ones (NRZI)
Recording data density
8 000 bits per inch
Encoding method
4 to 5 run-length limited
(RLL)
Flux density
10 000 flux transitions
per inch
Data transfer rate
90 bytes per second
Start/stop time
300 milliseconds (maximum)
6-84
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-50
Hardware Options
Tape Drive Power Requirements
Item
Value
Operating current:
+5 volts dc line
0.6 ampere (maximum)
+12 volts dc line
1.6 ±.0.8 amperes
(cartridge dependent)
Tape start/stop
surge current:
+5 volts dc line
0.6 ampere (maximum)
+12 volts dc line
4.4 amperes for 300
milliseconds (maximum)
Power consumption:
Continuous streaming
32 watts (total)
Start/stop power
surges
59 watts (total)
6.3.10.3 Tape Controller. The tape controller plugs into one of
the BUSINESS-PRO computer's option slots and serves as an
interface between the host expansion bus and the tape drive.
Tables 6-51 through 6-56 provide tabulated information about the
tape controller.
2241092-0001
6-85
Hardware Options
Table 6-51
Signal
Name
XD7
XD6
XD5
XD4
XD3
XD2
XDI
XDO
AEN
XA19
XA18
XA17
XA16
XA15
XA14
XA13
XA12
XAll
XAlO
XA9
XA8
XA7
XA6
XA5
XA4
XA3
XA2
XAI
XAO
BUSINESS-PRO Hardware Reference
Tape Controller/Expansion Bus Interface Signals
Pin
Number
Description
AOI
Not used by the tape system.
A02
A03
A04
A05
A06
A07
A08
A09
AlO
Data 0 through 7. These bidirectional
data lines handle all data transfers
between the host and the tape system.
XDO is the least-significant bLt; XD7
is the most-significant. These lines
are placed in their tristate condition
when not in use.
All
Address enable. This active high signal
prevents both writing to and reading
from the I/O base address through I/O
base address plus seven. This allows
data transfers under DMA control.
A12
A13
A14
A15
A16
A17
A18
A19
A20
A2l
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
Address 0 through 19. These lines carry
the low 20 bits of the system address.
Address 0 is the least-significant bit;
Address 19 is the most-significant bit.
The I/O address is established by
comparing XA3 through XA9 with jumper
settings on the controller. (The default
setting is 220H.) The addresses of the
status, control, and I/O data registers
are offset from the base address as
follows:
Not used by the tape system.
Base address+O=data register.
Base address+l=control and status
register.
Base address+2=DMA start address.
Base address+3=DMA stop address.
Base address+4=reserved.
Base address+5=reserved.
Base address+6=reserved.
Base address+7=reserved.
Base address+8=reserved.
6-86
2241092-0001
BUSINESS-PRO Hardware Reference
Table 6-51
Signal
Name
Hardware Options
Controller/Expansion Bus Interface Signals (Continued)
Pin
Number
Description
GND
B01
Ground.
DRST
B02
Drive reset. This active high signal
resets the tape drive by causing the
controller to write to the DMA stop
register.
B03
Not used by the tape system.
B04
Not used by the tape system.
B05
Not used by the tape system.
B16
B06
B18
DMA request lines. These controller
output signals generate DMA requests
to the host. Jumper settings on the
controller determine which DMA request
line is used. DRQ1 has the highest
priority. These lines are placed in
their tristate conditions when not
being used by the controller to allow
other expansion bus devices to use them.
B07
Not used by the tape system.
B08
Not used by the tape system.
+12V
B09
+12 volts dc from the host power supply.
GND
B10
Ground.
B11
Not used by the tape system.
B12
Not used by the tape system.
IOWC-
B13
I/O write. The rising edge of this
active low signal latches commands
and data into the controller's I/O
registers during an I/O cycle.
IORC-
B14
I/O read. This active low signal
causes the controller to place data
or status information on the data
lines during an I/O cycle.
DRQ3
DRQ2
DRQ1
2241092-0001
6-87
BUSINESS-PRO Hardware Reference
Hardware Options
Table 6-51
Signal
Name
Controller/Expansion Bus Interface Signals (Continued)
Pin
Number
Description
Bl5
B26
Bl7
DMA acknowledge. These active low
signals indicate to the controller
that the host is ready to proceed
with a pending DMA cycle. A set
of jumpers on the controller
establishes which DMA acknowledge
line is used.
The acknowledge and
request lines must be set to the
same priority.
Bl9
Not used by the tape system.
B20
Not used by the tape system.
CXIR7
CXIR6
XIR5
CXIR4
CXIR3
B2l
B22
B23
B24
B25
Interrupt requests. These signals generate
interrupt requests to the host. Jumper
settings on the controller determine which
one of the interrupts is being used. These
lines are placed in their tristate conditions
to allow other expansion bus devices to use
them when they are not being used by the
controller.
T/C
B27
Terminal count. This active high input to
the controller indicates the end of a DMA
cycle.
BALE
B28
Buffered address latch enable.
+5V
B29
+5 volts dc supply line.
14.3MHZ
B30
Oscillator. The controller generates its
own oscillator signal from an on-board
3. 579545-megahertz, crystal-controlled
oscillator. Therefore, the controller does
not use this host-generated oscillator
signal.
B3l
Ground.
DACK3DACK2DACKI-
GND
6-88
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BUSINESS-PRO Hardware Reference
Table 6-52
Jumper
Hardware Options
Tape Controller Jumper Settings
Position
Function
CC
In
Tape format. When installed, this
jumper configures the controller
for the QIC-24 tape format.
DD
Out
Tape speed. When not installed,
this jumper configures the controller
for a tape speed of 90 ips.
y
In
Number of tracks. When installed,
this jumper configures the controller
for 9-track operation.
KK
In
Power-on confidence test. When
installed, this jumper enables
the power-on confidence test.
A9
A8
A7
A6
A5
A4
A3
In
Out
Out
Out
In
Out
Out
I/O register base address. This
configuration of jumpers A3
through A9 sets the base register
address to 220H.
DRQl
DRQ2
DRQ3
Out
Out
In
DMA channel. This configuration
of jumpers DRQl through DRQ3
selects channel 3.
DAKl
DAK2
DAK3
Out
Out
In
DMA acknowledge.
This must match
the DRQ selection.
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Out
In
Out
Out
Out
Out
Interrupt priority. This
configuration of jumpers IRQ2
through selects IRQ3 as the
interrupt level.
FF
Out
Loop on error. This jumper is
for factory use only.
HH
Out
Test configuration. This jumper
is for factory use only.
NN
Out
Not used.
2241092-0001
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Hardware Options
BUSINESS-PRO Hardware Reference
Table 6-53
Tape Controller Diagnostic Indicators
LED
Number
Definition
DSI
Controller chip error
DS2
RAM buffer chip error
DS3
Data separator logic error
DS4
Not used
DS5
Not used
Table 6-54
Register
Tape Controller Registers
Description
Data
The data register is an 8-bit register that
can be either written to or read from. The
data register is located at the I/O register
base address with offset zero.
Control
The control register is an 8-bit register
with individual bits that provide control
information for the tape system. The control
register is located at the I/O register
base address plus one.
Its individual bits
provide the following control functions:
Bit 0
Not used.
Bit 1
Not used.
Bit 2
Not used.
Bit 3
Not used.
Bit 4
Done interrupt enable (DNIEN).
Activation of this bit while the lEN bit
is high gates the operation-completed
condition onto the selected interrupt
line (IRQ5-).
6-90
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BUSINESS-PRO Hardware Reference
Table 6-54
Hardware Options
Tape Controller Registers (Continued)
Register
Description
Control (Continued)
Bit 5 -- Interrupt enable (lEN). Activation
of this bit gates an interrupt condition
onto the selected interrupt request line
(DRQ3-).
Bit 6 -- Request (REQ). Activation of this
bit indicates that the host has written
command information to or has read status
information from the data register.
Bit 7 -- Reset controller microprocessor.
Activation of this bit for a period of at
least 25 microseconds resets the controller
microprocessor and initiates a power-on
confidence test.
Status
The status register is an 8-bit register that
provides certain status information to the
host.
The status register is located at the
I/O register base address plus one. The
individual bits provide the following status
information:
Bit 0
Not used.
Bit 1
Not used.
Bit 2
Not used.
Bit 3
Direction (DIRC). This bit controls
the data-transfer direction between the
controller and the host. Its high state
indicates that the transfer direction is
from the host to the controller.
Bit 4 -- Done (DONE). When active, this bit
indicates that a data transfer between the
controller and the data bus is complete.
Bit 5 -- Exception (EXC). When low, this bit
indicates to the host that an exception
condition exists. The host must issue a
status command to determine the cause of
the condition.
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Hardware Options
BUSINESS-PRO Hardware Reference
Table 6-54
Tape Controller Registers (Continued)
Register
Description
Status (Continued)
Bit 6 -- Ready (RDY). When low, this bit
indicates one of the following conditions:
Command data has been taken from the
data bus.
Status data has been gated to the data
bus.
Either a BOT command, an Erase command,
or a Cartridge Initialization command
has been completed.
A Write File Mark command has been
completed.
The tape system is ready to receive a
block of data, a Write command, or a
Write File Mark command.
The tape system is ready to transmit
the next block of data or is ready to
receive a Read command or a Read File
Mark command.
The controller is ready to receive a
command.
Bit 7 -- Interrupt request flag (IRQF).
When low, this bit indicates an active
interrupt request.
Start DMA
Writing to this 8-bit register initiates a
DMA request. The start DMA register is
located at the I/O register base address
plus two.
Stop DMA
Writing to this 8-bit register turns the
DMA bit off. The start DMA register is
located at the I/O register base address
plus three.
--------~----~---------------------------------------- -----------
6-92
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BUSINESS-PRO Hardware Reference
Table 6-55
Hardware Options
Tape Controller Performance Specifications
Specification
Characteristic
Host bus size
8 bits
Tape drive interface
Compatible with QIC-36
Tape format
QIC-24
Command set
Subset of QIC-02
Tape speed
90 inches per second
Number of tracks
9
Block size
512 bytes
Shipping configuration:
I/O register base
address
220H
DMA request channel
DRQ3
DMA acknowledge
DAK3
Interrupt request
IRQ3
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6-93
Hardware Options
Table 6--56
BUSINESS-PRO Hardware Reference
Tape Controller Power Requirements
Item
Value
Regulation:
+5 volts dc line
+5 percent
+12 volts dc line
+5 percent
Ripple content
(peak-to-peak):
+5 volts dc line
100 millivolts
+12 volts dc line
50 millivolts
Operating current:
+5 volts dc line
0.85 ampere (typical)
1.25 amperes (maximum)
+12 volts dc line
85 milliamperes (typical)
100 milliamperes (maximum)
Power consumption:
Total
5.27 watts
Maximum
7.82 watts
6-94
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BUSINESS-PRO Hardware Reference
6.4
Hardware Options
VIDEO OPTIONS
The video options provide a variety of monitor configurations
with convenient connectors for the mouse and keyboard.
The
following video options are available:
*
TI mode video controller
*
PC-AT mode video controller
*
Color display unit
*
Monochrome display unit
The following paragraphs describe the video options.
6.4.1 Video Controllers
Two optional video controllers allow the user to choose between
TI mode or PC-AT mode video operations. The following paragraphs
provide information about the two controllers: the TI mode CRT
controller and the PC-AT mode CRT controller.
6.4.1.1 TI Mode CRT Controller.
The optional TI mode CRT
(cathode ray tube) controller is a full-sized, l6-bit board that
supports TIPC alphanumeric and 3-plane graphics. The controller
can
display
256
different characters with the following
attributes:
*
Eight colors/levels of intensity
*
Reverse video
*
Underline
*
Nondisplay (blank)
*
Blink
NOTE
The TI mode CRT controller does not support
either an external character font or the
second set of character codes available on
the TIPC.
2241092-0001
6-95
Hardware Options
BUSINESS-PRO Hardware Reference
TI Mode CRT Controller Kit.
The TI mode CRT controller kit, TI
Part No.
2240967-0001 includes the following items:
*
TI mode CRT controller, TI Part No.
*
TI Mode CRT Controller manual, TI Part No.
2240937-0001
2241034-0001
Tables 6-57 through 6-60 provide tabulated information about
TI mode CRT controller.
the
NOTE
This controller provides interfaces to the
attached monitor and to the PC-AT controller
(if present).
The monitor interface is via
connector J3i the PC-AT interface is via
connector J4. Tables 6-57 and 6-58 describe
the signals at connectors
J3
and
J4,
respectively.
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BUSINESS-PRO Hardware Reference
Table 6-57
Hardware Options
TI Mode CRT Controller/Monitor Interface Connector J3
Signal
Pin
Number
Description
MODE SELECT
1
Mode select. The controller generates
this signal to select either the TI mode
or the PC-AT mode of operation. The low
state of the signal places the video
monitor in the TI mode; the high state
places it in the PC-AT mode.
H SYNC
2
Horizontal synchronization for the
attached video monitor.
V SYNC
3
Vertical synchronization for the
attached video monitor (active low).
RED
GREEN
BLUE
INTENSITY
4
6
8
10
Red video, green video, blue video, and
video intensity. These signals form a
4-bit code that determines the color to
be displayed on the video monitor. See
the Color Display Unit section.
NOTES:
The cable shield connects to chassis ground.
Pins 5, 7, 9, 11, 12, and 13 are ground connections.
Pins 14 and 15 are not connected.
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Hardware Options
Table 6-58
Signal
BUSINESS-PRO Hardware Reference
TI Mode/PC-AT Mode Controller Interface Connector J4
Pin
Number
Description
V RED
V GRN
V BLU
INTEN
1
3
5
H DRIVE
9
Horizontal synchronization. This
signal is a buffered version of
H SYNC described in Table 6-57.
V DRIVE
11
Vertical synchronization. This
signal is a buffered version of
V SYNC described in Table 6-57.
7
Red video, green video, blue video,
and video intensity. These signals
are buffered versions of the red,
green, blue, and intensity signals
described in Table 6-57.
Js
13
U38 enable. When low, this signal
enables buffer U38. This device
buffers the color, intensity, and
horizontal/vertical drive signals
for the CRT controller.
TIPC-
15
Mode select. The controller generates
this signal to select either the
TI mode or the PC-AT mode of operation.
The low state of the signal places the
video monitor in the TI mode.
NOTE:
Pins 17 and 19 and all even-numbered pins are grounded.
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BUSINESS-PRO Hardware Reference
Table 6--59
Signal
Hardware Options
TI Mode CRT Controller Expansion Interface Signals
Connector and
Pin Number
Description
NMI-
Pl-l
Nonmaskable interrupt. This
signal is activated by verticalretrace when enabled by software.
GND
Pl-2
Ground.
RESET
Pl-4
Reset. Initializes the CRT
controller board at power-up.
XD15
XD14
XD13
XD12
XDll
XDIO
XD9
XD8
XD7
XD6
XD5
XD4
XD3
XD2
XDI
XDO
P2-35
P2-33
P2-3l
P2-29
P2-27
P2-25
P2-23
P2-2l
Pl-3
Pl-5
Pl-7
Pl-9
PI-II
Pl-13
Pl-15
Pl-17
Expansion data bus. These
bidirectional data lines carry
data between the CRT controller
and the cpu.
+5V
Pl-6
+5 volts dc for the CRT controller
board.
WAIT-
Pl-19
wait. The CRT controller generates
this signal to indicate to the MPU
that the current memory cycle needs
to be extended.
GND
Pl-20
Ground.
AEN
Pl-2l
Address enable. The DMA controller
on the main logic board generates
this signal to indicate that it
has acquired control of the system
buses in order to perform a DMA
cycle.
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Hardware Options
Table 6-59
BUSINESS-PRO Hardware Reference
TI Mode CRT Controller Expansion Interface Signals (Cont)
Signal
Connector and
Pin Number
IOWC-
Pl-26
I/O write control. This signal
indicates that an I/O write cycle
to the CRT is in progress.
XA16
XA15
XA14
XA13
XA12
XAll
XAIO
XA9
XA8
XA7
XA6
XA5
XA4
XA3
XA2
XAl
XAO
Pl-29
Pl-31
Pl-33
Pl-35
Pl-37
Pl-39
Pl-41
Pl-43
Pl-45
Pl-47
Pl-49
Pl-51
Pl-53
PI-55
Pl-57
PI-59
Pl-61
Expansion address bus.
BALE
PI-56
Buffered address latch. The CPU uses
this signal to indicate to the CRT
controller that it is placing a valid
address on the expansion address bus.
+5V
PI-58
+5 volts dc for the CRT controller board.
XBHE-
P2-1
Expansion bus high byte enable. The
falling edge of BALE latches this
signal to indicate that data is being
transferred via the upper eight data
lines (XD8 through XD15).
BA23
BA22
BA21
BA20
BA19
BA18
BA17
P2-3
P2-5
P2-7
P2-9
P2-l1
P2-13
P2-15
Extended address lines. These lines
extend the addressing capability of
the expansion address bus to 16
megabytes.
Description
6-100
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BUSINESS-PRO Hardware Reference
Table 6-59
Signal
Hardware Options
TI Mode CRT Controller Expansion Interface Signals (Cont)
Connector and
Pin Number
Description
MRDC-
P2-17
Memory-read control. This signal
indicates that a memory-read
operation is in progress.
MWTC-
P2-19
Memory-write control. This signal
indicates that a memory-write
operation is in progress.
+5V
P2-32
+5 volts dc for the CRT controller.
MASTER-
P2-34
Master.
The CRT controller monitors
this line to detect DMA access.
GND
P2-36
Ground.
Table 6-60
TI Mode CRT Controller Performance Specifications
Characteristic
Specification
Graphics resolution
720 pixels (horizontal) by
300 pixels (vertical)
Character resolution
80 characters (horizontal)
by 25 characters (vertical)
Total available characters
256
Size of character block
9 pixels (horizontal) by
12 pixels (vertical)
Character attributes
Nondisplay (blank), underline,
reverse video, blink, and
colors/levels of intensity
Colors/levels of intensity
8
Horizontal scan rate
19 200 Hertz
Video bandwidth
18 megahertz
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Hardware Options
BUSINESS-PRO Hardware Reference
6.4.1.2
TI Mode CRT Controller Board. The CRT controller board
supports either a monochrome or a color TTL (transistor-totransistor logic) display and makes the BUSINESS-PRO computer a
complete alphanumeric and raster graphics system.
The controller board provides one page of high-resolution (SO
columns x 25 lines) alphanumeric display and S color graphics
with a resolution of 720 x 300. The system makes no physical
distinction between color and monochrome; the board supports
output in S-level gray scale or S-co10r RGB (red, green, blue).
Color is determined by the monitor used. For logic diagrams of
this controller, refer to Appendix E, drawing number 2223011.
Table 6-61 lists the video ac parameters.
Table 6-61
Video AC Parameters
Parameter
Ref
Value
Video dot frequency
Video dot pu1sewidth
Character block horizontal
Character block vertical
Number of character lines
Characters/character line
Number of active scan lines
Total scan lines
Vertical synchronization width
Vsync front porch
Vsync back porch
Vertical blanking interval
Active vertical display time
Total vertical time
Vertical rate
Hsync width
Hsync front porch
Hsync back porch
Horizontal blanking interval
Active horizontal display time
Total horizontal time
Horizontal rate
A
B
C
D
E
F
G
H
J
K
L
M
N
Q
R
S
T
U
V
W
X
Display Characteristics.
follows:
The
display
lS.OOO megahertz
55.55 nanoseconds
9 dots
12 dots
25 rows
SO columns
300
320
0.156 milliseconds
0.0 milliseconds
0.SS4 milliseconds
1.040 milliseconds
15.60 milliseconds
16.63 milliseconds
60.10 Hertz
4.50 microseconds
2.00 microseconds
5.50 microseconds
12.00 microseconds
39.99 microseconds
51.99 microseconds
19 231 Hertz
characteristics
*
A 7 x 9 character in a 9 x 12 image cell
*
Twenty-five lines of SO characters
6-102
are
as
2241092-0001
BUSINESS-PRO Hardware Reference
Hardware Options
*
A resolution
vertically
*
*
A horizontal scan rate of 19 200 lines per second
*
A dot rate of 18 megahertz
of
720
pixels horizontally x 300 pixels
A vertical scan rate of 60 Hertz
NOTE
The horizontal scan rate is an important
consideration, because many monitors have a
horizontal scan rate
of
15 750.
Only
monitors having a horizontal scan rate of
19 200 lines per second can operate with the
TI mode CRT controller.
Address Map.
The TI mode CRT controller (referred to as the CRT
controller in this section) is located at address ranges COOOOH
through DFFFFH for the CPU, and AOOOOH through BFFFFH for the bus
masters and DMA controllers. However, the alpha board (TI Part
No.
2223100-0001) and graphics board (TI Part No. 2223061-0002)
used in the Texas Instruments Professional Computer (TIPC) are
located at address range COOOOH through DFFFFH. Since the TIPC
does not allow DMA or bus masters, all current software is
compatible.
The CRT controller actually decodes AOOOOH through BOOOOH. The
main logic board inverts lines A17 and A18 on CPU accesses to
AOOOOH through DFFFFH when the CRT controller is enabled (port
12H, bit 1=1). The CRT controller has been remapped to prevent
potential conflicts with the option ROM space in the PC-AT mode,
address range COOOOH through DFFFFH. Table 6-62 shows the memory
map.
The bus masters and DMA controllers should use the
expansion bus address to access the CRT controller, and the CPU
should use the CPU address. When port 12H, bit 1=0, the CRT
controller (with the exception of port 12H) is disabled. To read
or write, any device on the CRT controller port l2H, bit 1 must
equal 1.
NOTE
When the CRT controller is enabled, the
option ROM space is at AOOOOH through BFFFFH
for the CPU and COOOOH through DFFFFH for bus
masters and DMA.
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Hardware Options
BUSINESS-PRO Hardware Reference
Table 6-62
CPU Address
(Hexadecimal)
cocoa
C8000
DOOOO
DEOOO
DE800
DFOOO
to C7FFF
to CFFFF
to D7FFF
to DE7FF
to DEFFF
Bit 0
Expansion Bus
Address
(Hexadecimal)
AOOOO
A8000
BOOOO
BEOOO
BEOOO
BFOOO
Bit 1
Bit 1
Bit 2
Bit 2
Bit 3
Bit 3
BF010
DF020
BF020
DF030
BF030
DF810
BF810
DF811
BF811
DF812
BF8l2
DF813
BF8l3
DF820 Bit 7
BF820 Bit 7
DF820 Bit 6
BF820 Bit 6
Bit 1
Purpose
to A7FFF
to AFFFF
to B7FFF
to BE7FF
to BE7FF
Bit 0
DF010
0012
CRT System Memory Map
(I/O Map)
Graphics plane A
Graphics RAM plane B
Graphics RAM plane C
Active character memory
Phantom character memory
Miscellaneous input buffer
blue feedback, read-only
Miscellaneous input buffer
red feedback, read-only
Miscellaneous input buffer
green feedback, read-only
Miscellaneous input buffer
interrupt pending, read-only
Graphics blue palette latch
write-only
Graphics green palette latch
write-only
Graphics red palette latch
write-only
CRTC address register, writeonly
CRTC status register, writeonly
CRTC registers write access,
write-only
CRTC registers read access,
read-only
Miscellaneous output latch,
interrupt enable
Miscellaneous output latch,
alphanumeric screen enable
High=CRT controller enabled
for alpha graphics board.
Low=CRT controller disabled.
6-104
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BUSINESS-PRO Hardware Reference
Hardware Options
Character Attributes. The video memory of the controller is
organized as 2 kilobytes x 16 bits. The first 8 bits convey
character information. The second 8 bits select the following
attributes on a character basis:
Bit
Description
Intensity
Intensity
Intensity
Character
Reverse
Underline
Blink
Not used
0
1
2
3
4
5
6
7
level 1 (Blue)
level 2 (Red)
level 4 (Green)
enable
NOTE
The three intensity bits (bit 0 through bit
2) determine the gray scale intensity level
and the red-green-blue (RGB) outputs for
color.
Thus, normal monochrome video is
handled by a one-of-eight intensity select,
instead of a high-intensity bit.
To access the character attributes, the software writes the
attribute values into an attribute latch. The attribute value is
then assigned to the character each time that a character is
written to the screen (until a screen read operation is done).
When any character on the screen
copied to the attribute latch.
subsequent latch read operation.
is read, its attributes are
These values are then read by a
Handling the attributes by this method ensures that in block
moves
(moving data from one screen area to another) the
characters retain their attributes.
Character Sets.
The video controller contains a 4-kilobyte
character generator ROM, which contributes 256 characters. This
ROM is internal to the video generator (VG).
Scrolling. The hardware maintains a screen start register that
supports character line scrolling in four directions.
The
software determines the need for a scroll, then changes the value
of this register by one line. The screen appears to jump by one
line.
The scrolling operation always affects all of the screen.
You cannot scroll one region without affecting another.
2241092-0001
6-105
Hardware Options
BUSINESS-PRO Hardware Reference
Since screen memory is limited to 2 kilobytes, a scrolling
operation results in a page wrap; that is, the original top line
of the screen moves to the bottom of the screen. Therefore, the
software must clear the top line of the screen (or bottom) before
the
scroll-up (or scroll-down) operation takes place.
To
simplify programming of the line clear operation, the 2 kilobytes
of memory overlays a 4-kilobyte address space.
Status lines must be implemented in software.
That is, during
scroll operations, the status line must be moved to its new
The screen start register
memory position before writing.
changes the screen-to-memory correspondence.
CRT Controller IC.
The
contains the logic for:
CRT
controller
(CRTC)
IC
(6845EA)
*
Generating the
signals
*
Blanking display during retrace
*
*
Addressing screen memory during screen refresh
*
Starting screen display registers for use in scrolling
horizontal
and
vertical
synchronizing
Cursor coincidence
The CRTC contains 18 registers that must be appropriately set
before board operation begins. To access these registers, the
CPU first writes the address of the register to be accessed into
the CRTC address register. Then, information can be written to
that
register.
When
writing to or reading from (where
applicable) the data register, the information is accessed by the
address latched in the address register.
Table 6-63 shows how to program these registers, using the
signals chip select (CS), register select (RS), and read/write
(R/W-). Assume the following conditions:
*
A character rate (SWM-) of 2.0 megahertz
*
12 lines per character block
*
25 rows on the display
*
24 character
microseconds)
*
20 line times of vertical blanking (1.04 milliseconds)
times
of
horizontal
6-106
blanking
(12.0
2241092-0001
BUSINESS-PRO Hardware Reference
Hardware Options
For more detailed programming information, refer to The Rockwell
Data Book.
Table 6-63
Signal Name
CS- Al VAO
Register
Address
L
L
X
L
L
H
X
L
H
L
o
L
H
L
1
L
H
H
L
2
3
H
L
L
L
L
H
H
L
L
H
L
H
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
X
X
H
H
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CRTC Programming Values
Register Name
Refresh Rate
60 Hertz
No register selected
Set address register
Read status register
Horizontal total characters
minus one
103
Horizontal displayed
characters
80
Horizontal sync position
84
VSYNC width, HSYNC width
39
Vertical total rows minus 1
24
Vertical adjust lines
20
Vertical displayed rows
25
vertical sync position
25
Mode control
00
Scan lines per row minus 1
11
Cursor start line and BLINK
40
Cursor end line
11
Display start address high
00
Display start address low
00
Cursor position address high
00
Cursor position address low
00
Light pen position address high
Light pen position address low
NOTE:
H=High signal; L=Low signal; X=Don't care.
CRT Screen/CPU Arbitration Logic Subsystem.
The CRT controller
arbitration logic gives the programmer free access to the CRT
display.
The refresh memory and its control logic allow two
complete memory cycles between each character displayed on the
screen,
so there is very little overhead time
caused
by
arbitration conflicts.
One cycle accesses the character for
display; the CPU uses the other cycle for read or
write
operations.
Therefore, the CPU waits less than two displaycharacter times for memory access.
All alphanumerics address decode and timing are controlled by the
data address bus selector (DABS).
The attribute logic, character
ROM, and mixing of alphanumerics and graphics are internal to the
video generator (VG).
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BUSINESS-PRO Hardware Reference
Hardware Options
Attribute Interaction.
The attributes available for use with the
character display can be used in any of 128 possible combinations.
The following paragraphs explain what happens when
several
attributes are active at the same time.
The attributes have a priority in their effects, and the highest
priority attributes affect all attributes that have a lower
priority.
The order of priority is as follows:
Hiihest
Lowest
Color attributes (red, blue, green)
Reverse video and cursor
Character enable
Blink
Underline
For example, when the underline and blink attributes are set, both
character and underline blink. When the character enable is set
to disable, no character, underline, or blinking activity is
present. When reverse video and blink are set, the character goes
on and off, the background is lighted, and the foreground is dark
and blinking. When the character enable is set to disable and
reverse video is set, the entire cell is lighted (according to the
color attributes).
The color attributes define the characteristics of the light
portion of the character, that is, either the color (when a color
monitor is used) or the intensity (when a monochrome monitor is
used).
When graphics are used with alphanumerics, the graphics screen
shows through the dark portion of the alphanumeric character
display.
Table 6-64 gives the mapping of colors to intensity in
the video output.
Table 6-64
Code
Color
000
001
010
011
100
101
110
111
Black
Blue
Red
Magenta
Green
Cyan
Yellow
White
Color Map
Monochrome
Intensity Level
0
1
4
5
2
3
6
7
To blank the alphanumerics display to black, set the CRT Enable
bit in the miscellaneous output latch to low.
The board enters
this state on power-up.
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Hardware Options
CRT Interrupt Logic Subsystem.
The CRTC board contains a logic
subsystem that allows the CRTC to generate an interrupt during the
vertical interval. The processor uses this interrupt when doing
scrolls with a status line or other operations that must be done
during the vertical blanking interval. To enable this interrupt,
set the Interrupt Enable bit in the miscellaneous latch to high.
Vertical blanking generates the CPU nonmaskab1e interrupt and sets
the Interrupt Pending bit.
This bit
is
read
from
the
miscellaneous buffer.
To reset the interrupt, set the Interrupt
Enable bit to low.
6.4.1.3 Diagnostic Loopback. One diagnostic test requires that
the three color outputs be looped back to the miscellaneous input
buffer so that the CPU can read them. Using a program with proper
timing from the vertical interval, the CPU can check the action of
the attribute bits and the graphics board palette circuits.
6.4.1.4
Graphics Controller Board.
The graphics
and
the
alphanumerics both use the same number of pixels on the screen:
720 horizontal by 300 vertical. Each pixel can contain a maximum
of three attribute bits (labeled A, B, and C). These attribute
bits are converted by a palette look-up table to three colors:
red, blue, and green.
Aspects of the graphics controller board described in this section
include:
*
Pixel addressing
*
Color selection
*
Timing and synchronization
*
Graphics logic array program
Pixel Addressing.
Each dot on the graphics screen is a pixel.
Each pixel has a 3-bit value associated with it that selects 1 of
8 palettes (0 through 7). Each palette is assigned 1 of 8 colors,
as determined by the contents of the latch. The latch is simply
an array of eight 3-bit values. The palette number of each pixel
is an index into that array. So, the color of a pixel is the
color value of the latch entry that corresponds to the palette
number of the pixel.
Changing either the palette or the color
assigned to the palette changes the color of that pixel. Changing
the color assigned to a palette changes the color of every pixel
with the same palette number.
A plane is a block of memory containing 1 bit for each pixel in
the display. Each of the 3 bits assigned to a pixel is in a
different plane. All three planes are formatted identically; only
the segment address differs from plane to plane. The segment
2241092-0001
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Hardware Options
BUSINESS-PRO Hardware Reference
addresses of the three planes are COOOH, C800H, and DOOOH.
For
example, if a bit assigned to pixel (x, y) is the fifth bit of
memory location COOO:mmmm, then the other 2 bits assigned to that
pixel are the fifth bits of locations C800:mmmm and DOOO:mmmm.
In Table 6-65, memory addresses refer to offsets into the segment
of any of the three graphics planes. This illustration shows the
organization of graphics screen memory into pixels.
Pixels are
numbered (x coordinate, y coordinate) and are zero relative.
Table 6-65
Byte
Address
(Hex)
Organization of Graphics Screen Memory Into Pixels
Pixels Represented
0000-005B
(8,0-15,0)
(0,0-7,0)
005C-OOB7
(8,1-15,1)
(0,1-7,1)
(24,0-31,0)
(16,0-23,0)
. . .
NOTES:
Pixel (0, 0) is the MSB of location OOOL
Pixel (7,0) is the LSB of location OOOL
Pixel (8,0) is the MSB of location 0000.
Pixel (15,0) is the LSB of location 0000.
Pixel (16,0) is the MSB of location 0003.
The bytes are flip-flopped in this way so that if a move
instruction is executed from a word in the graphics plane to a
word register, the register then contains 16 consecutive pixel
bits arranged from MSB to LSB. For example, if a MOV AX, ES:OOOOH
is executed (where ES contains the segment address of the desired
graphics plane), the MSB of AX is pixel (0,0) and the LSB is pixel
(15,0). With this scheme, 45 words are necessary to represent the
720 pixels in each row of the display. One unused word appears at
the end of each line, so a new row begins every 46 words, or 92
bytes.
Line one (zero-relative) begins at byte address 92
decimal, 005CH. Therefore, pixel (0,1) is the MSB of location
005DH and pixel (8,1) is the MSB of location 005CH (because the
bytes are flip-flopped).
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Example:
To find the values of the rightmost 16 pixels on the
of the display, use the following formula.
bottom
line
299 (zero-relative number of last line on display)
x 92 (bytes per line)
- 88 (first word=O, second word=2, so 45th word=88)
27 596
(6BCCH)
So, MOV AX, ES:6BCC puts the values of the last 16 pixels on the
display in AX, with the LSB of AX being the pixel in the lower
right corner.
The three graphics planes are named A, B, and C. The segment
addresses of the planes A, B, and Care COOOH, C800H, and DOOOH,
respectively.
In determining the palette number of a pixel, the
bit from the C plane is the most significant, the bit from the A
plane is the least significant, and the B plane bit is in the
middle.
Example:
To find the color of the pixel in the lower right corner
display, first find the palette number assigned to it.
of
the
The MSB of the palette number is the LSB of DOOOH:6BCCH.
The middle bit of the palette number is the LSB of C800H:6BCCH.
The LSB of the palette number is the LSB of COOOH:6BCCH.
For example, if these three bits are 1, 0, and 1, respectively,
then the color of the lower right pixel is the color assigned to
palette 5.
If the default color assignments are in effect, the
color of the pixel is cyan.
Color Selection. Each of the 8 entries in the latch has 1 bit for
each of the 3 primary colors: green, red, and blue.
The eight
available colors are formed by combinations of those three colors,
as listed in Table 6-66.
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Table 6-66
Green
0
0
0
0
1
1
1
1
Red
0
0
1
1
0
0
1
1
Blue
0
1
0
1
0
1
0
1
Color Combinations
Color
Black
Blue
Red
Magenta
Green
Cyan
Yellow
White
Color
Number
0
1
2
3
4
5
6
7
To access the latch, you must write all 8 bits of a particular
primary color to the appropriate memory location for that color.
You cannot change all 3 bits corresponding to one palette number
in a single write operation.
The latch consists of 3 memory
locations, 1 for each of the primary colors. These locations are:
Blue latch
Green latch
Red latch
DFOO:00I0H
DFOO:0020H
DFOO:0030H
You can write to these locations, but you cannot read from them.
For this reason, it is necessary to maintain a memory image of the
3 color latches if individual palettes are to "be changed. You are
then able to change a single palette by setting the appropriate
bits in the memory image to the desired value and updating all 3
color latches.
Each of the 3 color bits of a palette is in the same bit position
in all 3 color latches. However, the scheme for determining which
bit in the latch is addressed by a pixel is not the same as
determining the palette number.
In determining the latch bit
addressed by the 3-bit value assigned to a pixel, the B plane
value is the most significant, and the C plane value is in the
middle.
The A plane value is still the least significant. Bit 7
is the MSB, and bit 0 is the LSB of the color latch byte.
Table
6-67 displays the correspondence between the bits assigned to a
pixel and the bit positions in any of the 3 color latches.
It
also shows the comparison of these bit positions to the palette
numbers.
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Table 6-67
B Plane
Bit
C Plane
Bit
o
o
o
o
1
1
1
1
o
o
1
1
o
o
1
1
Hardware Options
Bit Correlations
A Plane Latch Bit
Bit
Addressed
Palette
Number
o
o
o
1
1
2
3
1
4
o
1
o
5
2
4
5
1
o
6
1
7
3
6
7
Table 6-68 shows this correspondence horizontally,
color latch byte appears as a byte register.
Table 6-68
so
that
the
Color Latch Byte
B plane bit
1
1
1
1
0
0
0
0
C plane bit
1
1
0
0
1
1
0
0
A plane bit
1
0
1
0
l'
0
1
0
Latch bit addressed
7
6
5
4
3
2
1
0
Palette number
6
1
0
7
3
2
5
4
----------------------------------------------------------------Example:
This example shows how to create a memory image of the default
values of the three color latches.
Combining information from Table 6-66 with information from Table
6-67 yields the information necessary to construct Table 6-69.
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Hardware Options
Table 6-69
BUSINESS-PRO Hardware Reference
Default Values of Color Latches
Palette Number
(Color Number)
Latch
Bit
Green
Bit
Red
Bit
Blue
Bit
-----------------------------------------------------------------
7
6
3
2
5
4
1
0
7
6
5
4
3
2
1
0
(White)
(Yellow)
(Magenta)
(Red)
(Cyan)
(Green)
(Blue)
(Black)
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
0
1
0
1
0
1
0
The default condition is palette number=co1or number; therefore,
the color latches are set as follows:
Green latch=11001100 binary=CCH at DFOO:0020H
Red 1atch=1111000 binary=FOH at DFOO:0030H
Blue 1atch=10101010 binary=AAH at DFOO:0010H
Example:
The following example lists the steps necessary to change
3 to yellow from the default condition (magenta).
palette
1. Find the desired palette number (three) in Table
then, find the associated latch bit (five).
6-69;
2. Find the desired color (yellow) in Table 6-69;
find the bit settings (red=l, green=l, b1ue=0).
then,
3. Set bit five in each of the color latches to the values
determined in the previous step. This change creates
the new values:
a. Green 1atch=11101100 binary=ECH
b. Red latch=11110000 binary=FOH
c. Blue 1atch=10001010 binary=8AH
4. Write the new values (from the previous step) to the
three color latch addresses.
(In this example, it is
not necessary to change the red latch, because the value
did not change.)
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Timing and Synchronization.
The same dot clock that generates internal timing for the
alphanumerics also clocks the graphics video. Monitoring the
display enable (DE) signal from the CRTC chip (6845) helps to
synchronize the pixel outputs from the alphanumerics.
If the DE
signal has been low for a long period, the graphics controller
(CG) assumes that the scan is in the vertical interval. When DE
goes high again, the GC resets the graphics memory and scan
counters to zero.
When DE is low for a short period (during
horizontal retrace, for example), the scan counters are stopped.
This places the last pixel on a line adjacent to the first pixel
on the following line.
The graphics video controller gives the CPU free access to the
screen memory. During a single screen display cycle, the hardware
can access the refresh memory twice--once to read the data for
screen display and once for the CPU to read or write data if
needed.
To provide enough time for this access, a display cycle
accesses 16 adjacent pixels of 3 attribute bits each.
These are
read in parallel and loaded into three 16-bit shift registers for
display. After the memory has been read for screen display, the
CPU access cycle begins if a read or write cycle is requested.
Dynamic memory is used on the graphics video board because of the
large amount of memory required. The memory chips are organized
into 16 kilowords by 4 bits and are packaged in an 18-pin, dualinline-package (DIP). The 8 address lines are multiplexed into
256 row addresses and 64 column addresses to get to the 16 000
locations in the memory. The addresses to the RAM also need to be
multiplexed between the CPU and the refresh counter.
The graphics timing and address decode are controlled by graphics
controller (GC).
Palette latches, the DRAM data interface, and
video shift registers are controlled by the graphics RAM interface
(GRI).
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Hardware Options
6.4.1.5 TIPC Compatibility.
On the TI mode CRTC, the memory
maps are identical to current TIPC software. Otherwise, the
alphanumerics/graphics board is compatible with TIPC software,
except as follows:
*
TI mode CRTC does not support an external character ROM.
*
There is no composite video output. Conversion to black
and white takes place in the monitor itself.
*
The attribute latch operates differently from the TIPC
attribute
latch
on
a 16-bit read operation from
alphanumeric memory.
The TIPC places the attribute
corresponding to the high byte in the attribute latch,
while the BUSINESS-PRO places the low byte in the
attribute latch.
*
The TI mode CRTC
disables the board.
*
The monochrome grey scale does not match the
BUSINESS-PRO grey scale as shown in Table 6-70.
Table 6-70
Code
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
port
12H, which enables and/or
current
TIPC vs BUSINESS-PRO Monochrome Compatibility
Color
0
1
0
1
0
1
0
1
has
Black
Blue
Red
Magenta
Green
Cycfin
Yellow
White
Current TIPC
BUSINESS-PRO
0
1
2
3
4
5
6
7
0
1
4
5
2
3
6
7
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BUSINESS-PRO Hardware Reference
6.4.1.6 PC-AT Mode CRT Controller. The optional PC-AT mode CRT
controller is a full-sized, 16-bit board that supports both PC-AT
monochrome and PC-AT color applications. The controller provides
an interface to the optional PC-AT monitors or any standard NTSC
(National Television System Committee) format peripheral.
Monochrome Mode Character Attributes.
The controller supports
the following character attributes in monochrome (mono) mode:
*
Highlight
*
Reverse video
*
White character/black background
*
Underline
*
Nondisplay (blank)
*
Blink
*
Connection for alternate video controller
Color Mode Character Attributes.
The controller supports one of
the following character attributes in color mode:
*
Any of 16 foreground, any of 8 background, and blink
*
Any 0
Anz.-_of 1-6----£oreground and any of 16 background
*
~
PC-AT Mode CRT Controller Kit.
The PC-AT mode CRT controller
kit, TI Part No.
2240968-0001, includes the following items:
*
PC-AT mode CRT controller (dual mode video board), TI
Part No.
2240940-0001
*
PC-AT II alternate mode
2540315-0001
*
CRT controller cable, TI Part No.
*
PC-AT Mode CRT Controller
0001
CRT
controller,
TI
Part
No.
2240960-0001
manual, TI Part No.
2241039-
PC-AT Mode CRT Controller Tabulated Information.
Tables
6-71
through 6-75 provide tabulated information about the PC-AT mode
CRT controller.
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Hardware Options
NOTE
The BUSINESS-PRO can contain either a basic
PC-AT CRT controller or an alternate PC-AT II
CRT controller, but it cannot contain both
controllers at the same time.
The, J4 edge
connector on the PC-AT CRT controller is tied
to J4 on the TI mode CRT controller via a
daisy-chain cable, TI Part No.
2240960-0001.
The TI mode CRT controller then becomes a
throughput
channel
and connects to the
monitor via edge connector J3.
Tables 6-71
and 6-72 describe the signals at connectors
J3 and J4, respectively, for the PC-AT CRT
controller.
Table 6-71
PC-AT Mode CRT Controller/Monitor Interface Connector J3
Signal
Pin
Number
CVM
1
Mode se1~ct. High=PCAT video rates;
low=mono/TJPC,
video rate. ,
CVH
2
Horizontal synchronization for the
attached video monitor.
CVV
3
Vertical synchronization for the
attached video monitor.
CVR
CVG
CVB
CVI
4
6
8
10
Red video, green video, blue video,
and video intensity. These signals
form a four-bit code that determines
the color to be displayed on the
video monitor.
EXT SYNC- *
14
External synchronization.
Description
NOTES:
The cable shield connects to chassis ground.
Pins 5, 7, 9, 11, 12, and 13 are ground connections.
Pins 14 and 15 are not connected .
. For TI monitors, HSYNC is a high pulse; VSYNC is a low pulse.
*
Used on alternate PC-AT II controller only.
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Hardware Options
BUSINESS-PRO Hardware Reference
Table 6-72 lists and describes the pinouts of edge connector J4,
which connects the PC-AT CRT controller to J4 of the TI mode CRT
controller via a 20-pin daisy-chain cable.
Table 6-72
Signal
Interface Connector J4
Pin
Number
Description
Red video, green video, blue video,
and video intensity. These signals
are buffered versions of the red,
green, blue, and intensity signals
described in Table 6-71.
EXRED
EXGRN
EXBLU
EXINT
1
3
EXHORIZ
9
Horizontal synchronization. This
signal is a buffered version of
HSYNC described in Table 6-71.
EXVERT
11
Vertical synchronization. This
signal is a buffered version of
VSYNC described in Table 6-71.
+5V (VCC)
13
+5 volts dc supply line.
EXVIDON-
15
Board-enable signal from the TI
mode CRT controller.
EXKCYC-
5
7
17
Used on PC-AT II CRT controller
only. Selects monitor speed
(see J3, pin 1).
NOTE:
Pin 19 and all even-numbered pins (2 through 20) are connected
to ground.
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Hardware Options
Table 6-73
Signal
BUSINESS-PRO Hardware Reference
PC-AT Mode CRT Controller Expansion Interface Signals
Connector and Pin
Description
PI-I
Not used.
GND
Pl-2
Ground.
RESET
Pl-4
Reset.
XDIS
XD14
XDl3
XDl2
XDII
XDIO
XD9
XD8
XD7
XD6
XDS
XD4
XD3
XD2
XDI
XDO
P2-3S
P2-33
P2-31
P2-29
P2-27
P2-2S
P2-23
P2-21
PI-3
PI-S
PI-7
PI-9
PI-II
PI-13
PI-IS
PI-17
Expansion data bus. These
bidirectional data lines
carry data between the CRT
controller and the CPU.
+SV
PI-6
+5 volts dc for the CRT controller
board.
WAIT-
PI-19
Wait. The CRT controller generates
this signal to indicate to the MPU
that the current memory cycle needs
to be extended.
GND
PI-20
Ground.
AEN
PI-21
Address enable. The DMA controller
on the main logic board generates
this signal to indicate that it
has acquired control of the system
buses in order to perform a DMA
cycle.
IOW-
Pl-26
I/O write control. This signal
indicates that an I/O write
cycle is in progress.
IOR-
Pl-28
I/O read command.
6-120
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BUSINESS-PRO Hardware Reference
Table 6-73
Signal
PC-AT Mode Controller Expansion Interface Signals (Cont.)
Connector and Pin
Description
+12V
Pl-22
+12 volts dc, for the light pen
connector.
XA16
XA15
XA14
XA13
XA12
XAll
XA10
XA9
XA8
XA7
XA6
XA5
XA4
XA3
XA2
XAl
XAO
Pl-29
Pl-31
Pl-33
Pl-35
Pl-37
Pl-39
Pl-41
Pl-43
Pl-45
Pl-47
Pl-49
Pl-51
Pl-53
Pl-55
Pl-57
Pl-59
Pl-61
Expansion address bus.
BALE
Pl-56
Address latch enable. Falling
edge indicates BA23 through BA17
are valid.
+SV
Pl-58
+5 volts dc for the CRT controller
board.
14.32MHZ
Pl-60
Video clock for color mode.
XBHE-
P2-1
Expansion bus high byte enable.
The falling edge of BALE
latches this signal to indicate
that data is being transferred
via the upper eight data lines
(XD8 through XD1S).
BA23
BA22
BA21
BA20
BA19
BA18
BA17
P2-3
P2-S
P2-7
P2-9
P2-11
P2-13
P2-1S
Extended address lines. These
lines extend the addressing
capability of the expansion
address bus to 16 megabytes.
MRDC-
Pl-24
Memory-read control. Indicates
a memory-read operation is
in progress in the lowest 1
megabyte of address space.
2241092-0001
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Hardware Options
Table 6-73 PC-AT Mode Controller Expansion Interface Signals (Cont.)
Signal
Connector and
Pin Number
Description
MWTC-
Pl-22
Memory-write control. Indicates
a memory-write operation is
in progress in the lowest 1
megabyte of address space.
MEMl6-
P2-2
Device indicates that it is
capable of 16-bit memory
transfers.
+5V
P2-32
+5 volts dc for the CRT
controller.
MASTER-
P2-34
Master. The CRT controller
monitors this signal line
to detect DMA access.
GND
P2-36
Ground.
Table 6-74
Signal
LPENIN
Pin
Number
Light Pen Enable Connector J5
Description
1
Low=light pen active. High to
low transition indicates light
pen detects something.
2
No connection. Key for
connector orientation.
LPENSW
3
Intended for switch from
light pen.
GND
4
Ground.
+5V
5
+5 volts dc supply line.
+l2V
6
+12 volts dc supply line.
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Table 6-75
Hardware Options
PC-AT CRT Controller Specifications
Characteristic
Specification
Monochrome mode:
Character resolution
80 characters (horizontal)
by 25 characters (vertical)
Characters available
256
Character block size
9 pixels (horizontal) by
12 pixels (vertical)
Character attributes
Nondisplay (blank), underline,
reverse video, blink,
highlight, and white
character/black background
Horizontal scan rate
19.2 kilohertz
Video bandwidth
18 megahertz
Composite video output:
Horizontal scan rate
15.75 kilohertz
Color burst
3.58 megahertz
Color/graphics, 80-character
alphanumeric mode:
Character resolution
80 characters (horizontal)
by 25 characters (vertical)
Characters available
256
Character block size
8 pixels (horizontal) by
8 pixels (vertical)
Character attributes
16 foreground and 16
background colors or
16 foreground colors,
8 background, and blink
Horizontal scan rate
15.75 kilohertz
Video bandwidth
14.32 megahertz
2241092-0001
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Hardware Options
Table 6-75
BUSINESS-PRO Hardware Reference
PC-AT CRT Controller Specifications (Continued)
Specification
Characteristic
Color/graphics, 40 character
alphanumeric mode:
Character resolution
40 characters (horizontal)
by 25 characters (vertical)
Characters available
256
Character block size
8 pixels (horizontal) by
8 pixels (vertical)
Character attributes
16 foreground and 16
background colors or
16 foreground colors,
8 background, and blink
Horizontal scan rate
15.75 kilohertz
Video bandwidth
7.16 megahertz
Character resolution for
the 640-dot, graphics mode
640 pixels (horizontal)
by 200 pixels (vertical)
Character resolution for
the 320-dot, graphics mode
320 pixels (horizontal)
by 200 pixels (vertical)
6.4.1.7
PC-AT CRT Controller Operational Modes. The PC-AT mode
CRT controller emulates the functions of the IBM monochrome and
color/graphics display adapters.
The operational mode of the
controller is independent of the type of display unit actually
being used with the controller.
PC-AT CRT Controller Configurations.
The IBM compatible CRT
controller has two versions. The earlier version is referred to
as the PC-AT CRT controller, and the present production version
is referred to as the PC-AT II CRT controller. Both controllers
perform the same basic functions of an IBM monochrome and
color/graphics adapter, and both have a connector (J4) for
passing TIPC compatible video to the CRT monitor, but most of the
differences are transparent to the system software. The primary
difference between the two controllers is a 9-function DIP switch
installed on the PC-AT II controller that allows the user to
select options to customize the system. The BUSINESS-PRO is
shipped from the factory with all switches set to ON.
These
switches are listed and described in Table 6-76 and are also
discussed in detail in the paragraphs following the table.
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BUSINESS-PRO Hardware Reference
Table 6-76
SWl Selectable Options
Function
Switch
1
Interface size select
2
Vertical synchronization polarity
3
Horizontal synchronization polarity
4
Monochrome mode enable
5
Monochrome RAM size select
6 (LSB)
Port 12, bit 4
7
Port 12, bit 5
8
Port 12, bit 6
9 (MSB)
Port 12, bit 7
4-bit select code
Switches 6 through 9
follows:
(SW1-l
through
SWl-9)
are
described
*
SW1-l -- Two data sizes can be transferred on the PC-AT
bus: 8-bit data (SW1-l ON) and 16-bit data (SW1-l OFF).
Any controller board in the OAOOOH through OBFFFH
address space that responds to DMA transfers must be an
8-bit controller, which is true for any system with an
IBM compatible color/graphics adapter.
In the standard
TI configuration, SW1-l is set to ON
for
8-bit
configuration.
*
SWl-2
The polarity of the vertical synchonization
signals going out of the digital port allows the
incorporation of non-TI standard monitors into the
system. In the standard TI configuration, SW1-l is set
to ON for low-pulse vertical synchronization.
*
SWl-3
The polarity of the horizontal synchronization
signals going out of the digital port are switchselectable. This allows the use of non-TI CRT monitors.
SWl-3
is
set
to
ON for high pulse horizontal
synchronization.
2241092-0001
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as
BUSINESS-PRO Hardware Reference
Hardware options
*
SWl-4 -- This switch enables emulation of a monochrome
adapter.
When the switch is OFF, video equipment from
another vendor can be installed.
*
SWl-5
This switch selects monochrome RAM size:
ON=4K-byte
RAM;
OFF=16K-byte RAM.
IBM compatible
monochrome boards have only 4K-bytes of controller RAM,
while the BUSINESS-PRO has 16K-bytes of RAM required for
color/graphics
adapter
emulation.
SWl-5
enables
extended RAM capability because when this switch is ON,
the controller wraps around the 4K-byte RAM boundary.
*
SWl-6 through SWl-9
These switches are matched
against control bits 4 (LSB) through 7 (MSB) in I/O port
12. They are factory set to ON, which identifies the
PC-AT II controller as unit O. This allows placing up
to 16 PC-AT II controllers, each with its own CRT on a
system.
Unit 0 is the only one initialized by the
system ROM.
Other enhancements in the PC-AT II CRTC are as follows:
*
EXTKCYC- signal is added to pin 17 of J4 interboard
connector to allow use of a third-party video board that
is compatible with eitherTI or IBM color/graphics CRT
timing.
*
EXTSYNC- is added to an external synchronization pin of
the CRT controller IC which allows external equipment to
put the PC-AT II controller into synchronization. The
6845 IC Data Manual contains the timing information for
these functions.
NOTE
On the PC-AT CRT controller, all registers
and RAM are available at all times.
On the
PC-AT II alternate CRT controller, only those
registers and RAM addresses belonging to the
current mode are available.
Three major operational modes are possible
controller. They are:
*
Monochrome
*
Color/graphics
*
Pass-through
controller)
(In
conjunction
6-126
with
with
the
the
PC-AT
TI-mode
CRT
CRT
2241092-0001
BUSINESS-PRO Hardware Reference
Hardware Options
Monochrome Mode.
The monochrome mode is entered by writing
to the monochrome mode control port (3B8H).
The controller
be in the monochrome mode to write to the monochrome
register (3B5H).
I/O port 12H must also have bit 1 cleared
to 0).
The I/O addresses available in the monochrome mode are
Table 6-77.
Table 6-77
I/O Address
(Hexadecimal)
data
must
data
(set
shown
in
PC-AT Controller Monochrome I/O Addresses
Function
3B4
Monochrome index register
3B5
Monochrome data register
3B8
Monochrome mode control port
3BA
Monochrome mode status port
Any even address in the range 3BOH through 3B7H is the same as
3B4H, and any odd address in this range is the same as 3B5H.
Port 3B4H is the index register that selects 1 of the 18 internal
registers of the controller.
Port 3B5H accesses the data
selected by port 3B4H.
Refer to Table 6-83
(CRT
Timing
Parameters) for the standard values to be set.
When the program writes to I/O port 3B8H, the PC-AT controller
goes into the monochrome mode.
The bits of port 3B8H are as
follows:
Bit
Description
3
When high, display is enabled; when low, the
screen is blank.
5
When high, blinking is enabled for alpha modes;
when low, the blink attribute bit becomes background
intensity control.
NOTE:
All other bits in port 3B8H are ignored.
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Hardware Options
When I/O
follows:
port
Bit
BUSINESS-PRO Hardware Reference
3BAH is read, status is reported by its bits, as
Description
o
When high, horizontal sync is active.
Blue bit loopback (Not IBM compatible).
Green bit loopback (Not IBM compatible).
Red bit loopback (IBM inputs white here).
1
2
3
Color/Graphics Mode.
When the system writes data
to
the
color/graphics control port (3D8H), the CRT controller goes into
the color/graphics mode. Table 6-78 shows the I/O addresses
available in the color/graphics mode.
Table 6-78
PC-AT CRTC Color/Graphics I/O Addresses
I/O Address
(Hexadecimal)
3D4
3D5
3D8
3D9
3DA
3DB
3DC
Function
Color/graphics index register
Color/graphics data register
Color/graphics mode control port
Color/graphics color select register
Color/graphics mode status port
Clear light pen status
Set light pen status
Any even address in the range of 3DOH through 3D7H is the same as
3D4H, and any odd address in this range is the same as 3D5H.
Port 3D5H is used to access the data selected by port 3D4H. Port
3D4H is the CRT controller index register that selects 1 of the
18 internal registers of the CRT controller. Refer to Table 683, CRT Timing Parameters, for the standard values to set.
In the color/graphics operational mode, the PC-AT CRT
operates in one of the following modes:
*
40-character alphanumeric
*
*
*
80-character alphanumeric
controller
320-dot graphics
640-dot graphics
6-128
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BUSINESS-PRO Hardware Reference
Hardware Options
Color/Graphics Mode Control, Port 3D8H.
Writing
to
the
color/graphics mode control port (3D8H) puts the controller in
the color/graphics mode and selects the color/graphics mode (from
those listed above) that is operational.
Table 6-79 describes
the bit functions of the control port.
Table 6-79
Bits
o
1
2
3
4
5
6
7
Bit Functions of Control Port 3D8H
Functions
80-character alphanumeric mode
320-dot or 640-dot graphics mode
Color burst disable (NOTE 1)
High=video enable; low=screen blank
640-dot graphics
Blink enable (NOTE 2)
Not used
Not used
NOTES:
1. Ignored on PC-AT; operates on PC-AT II; color burst is
automatically disabled for higher resolution modes.
2. If high, blink is enabled for character modes; if low,
this bit becomes background intensity control.
NOTE
The blink attribute alternates between a
character and reverse video,
rather than
between a character and a blank cell.
2241092-0001
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BUSINESS-PRO Hardware Reference
Hardware Options
Table 6-80 shows the bit values of the various graphics modes for
the color/graphics mode control port 3D8H.
Table 6-80
Bits
Valid Color/Graphics Modes for 3D8H
5
4
3
2
1
o
Hex
1
1
0
0
0
0
0
0
I
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
28
29
OA
IA
00
Mode
40-character alphanumeric
80-character alphanumeric
320-pixel graphics
640-pixel graphics
Blank screen
Color Select Register Port 3D9H.
I/O
port
3D9H
primarily
controls the border color and is active in the write mode only.
Table 6-81 describes the contents of the color select register.
Table 6-81
PC-AT CRT Controller Color Select Register
Bit
Alphanumeric
Mode
320-Dot Graphics
Mode
640-Dot Graphics
Mode
o
Blue border
Blue border
Blue foreground
I
Green border
Green border
Green foreground
2
Red border
Red border
Red foreground
3
Border intensity
Border intensity
Foreground intensity
4
Not used
Blue for nonzero
pixels
Not used
5
Not used
Intensity for
nonzero pixels
Not used
6
Not used
Not used
Not used
7
Not used
Not used
Not used
NOTE:
Zero is the standard setting for all modes.
6-130
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BUSINESS-PRO Hardware Reference
Hardware Options
NOTE
In the 320-dot graphics mode, the border
color defined by bits 0 through 3 is also the
color selected for pixel code O.
When the controller is in either the alphanumeric mode or the
320-dot graphics mode, the first nibble is the border color.
In
the 640-dot graphics mode, there is no border, and the first
nibble becomes the foreground color (usually white). Bits 4 and
5 are relevant only in the 320-dot graphics mode where they
provide the blue and intensity values for all nonzero pixels.
IBM terminology describes this as palette select.
Light Pen Ports 3DCH and 3DBH. From a programming point of view,
the light pen interface consists of the Set Light Pen Status
command (3DCH), the Clear Light Pen Status command (3DBH), and
the color/graphics mode status port 3DAH. The light pen sets a
flip-flop that is read via the 3DA status port. Writing data to
light pen control port 3DBH resets the flip-flop and clears the
light pen status. Data written to the light pen control I/O port
3DCH sets the light pen status.
Status Port 3DAH. The color/graphics mode status port (3DAH) is
a read-only port.
Table 6-82 lists and describes the bit
functions of this status port.
Table 6-82
Bits
Bit Functions of Status Port 3DAH
Functions
o
When high, horizontal blanking is active.
1
When high, light pen is triggered.
2
When low, light pen switch is active.
3
When high, vertical synchronization is active.
4
Not used.
I
7
NOTE:
I/O ports 3DDH, 3DEH, 3DFH, 3B9H, and 3BBH read-only ports
at these addresses cannot be created for other equipment.
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Hardware Options
BUSINESS-PRO Hardware Reference
Passthrough -- Alternate Video Port. Writing a logic 1 to bit 1
of port 12 (02) accesses the alternate video controller cable
when the TI mode and PC-AT mode CRT controllers are connected
together.
The LSB of port 12H (01) determines the memory map of
the expansion bus. When bit 1 is a logic I, address ranges AlB
and C/n are swapped.
That is, CPU address OCXXXXH appears as
OAXXXXH on the expansion bus. Standard settings are 00 or 11.
6.4.1.8 CRT Timing Parameters. The CRT controller contains 18
registers that must be programmed before operation of the
controller begins. To access these registers, the CPU first
writes the address of the register to be accessed into the CRTC
register. Then, information can be written to that register. As
a result of this operation, vertical and horizontal scan rates
and other timing parameters are generated throughout the CRTC.
Table 6-83 is a list of the registers that are written to and the
data that is entered into each register to generate the CRT
timing parameters.
6-132
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BUSINESS-PRO Hardware Reference
Table 6-83
CRTC
Register
40-Char.
Mode
o
1
2
3
4
5
6
7
8
o
A (10)
B (11)
C (12)
D (13)
E (14)
F (15)
10 (16)
11 (17)
CRT Timing Parameters
320- or 640Dot Graphics
38
28
2D
OA
IF
06
19
lC
02
07
06
07
o
o
o
o
L
L
38
28
2D
OA
7F
06
64
70
02
01
X
X
80-Char.
Mode
Monochrome
Mode (NOTE 1)
71
50
SA
OA
IF
06
19
lC
02
07
06
07
67
50
54
39
18
14
19
19
00
OB
OA
OB
o
o
o
o
o
L
L
X
o
00
00
X
X
L
L
o
(NOTE 2)
(NOTE 3)
(NOTE 4)
(NOTE 5)
(NOTE 6)
X
NOTES:
Values in this table are hexadecimal except those in parentheses.
X indicates "don't care."
o instead of 00 implies that other values are possible.
Read the 6845 CRT controller manual (Rockwell Data Book) before
using parameters different from those in this table.
1. Monochrome mode is not IBM compatible.
2. Start scan line of cursor.
3. End scan line of cursor.
4. The display start address is one-half the RAM
address.
5. The cursor position is one-half the RAM address.
6. Registers 16 and 17 are light pen position addresses. These
locations are 3 or 4 greater than the actual pen position.
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6-133
Hardware Options
BUSINESS-PRO Hardware Reference
Character Sets.
The character sets for the PC-AT mode CRT controller are
contained in a 24-pin BK-byte by B (8 kilobyte by 8 bit) ROM.
The ROM contains two fonts:
one for monochrome and one for
color/graphics mode.
The lower 4K is
reserved
for
the
color/graphics font, and the upper 4K is reserved for the
monochrome font. The input address lines can be divided into
three groups.
The least significant 4 bits represent the
scanline addresses; the next 8 bits represent the character code;
and the remaining bit indicates the monochrome mode.
Each
character is stored in 16 successive bytes, with the MSB
representing the leftmost column in the character cell.
In the color/graphics mode, the same font is used for both 40character
and 80-character displays; the 40-character mode
doubles the dot width of
the
character.
The
LSB
in
color/graphics characters represents the rightmost bit in an 8character cell. The ninth bit is active in only the monochrome
mode and only for the characters in the range COH through DFH.
When active, it is the same as the eighth bit of the font ROM
data.
6-134
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BUSINESS-PRO Hardware Reference
6.4.2 Color Display Unit
The optional color display unit is a 13-inch, high-resolution
video display unit whose dual-resolution capabilities allow it to
be used with both the TI mode and the PC-AT mode video
controllers.
The unit mounts on a tilt/swivel base which
contains the following connectors:
*
Two interchangeable keyboard/mouse connectors
* A data interface connector
* A power connector
The unit enclosure also contains an audio speaker. Both domestic
and international versions of the display unit are available.
6.4.2.1 Color Display Unit Kit.
The domestic color display unit
kit, TI Part No.
2240805-8003, includes the following items:
* Color display unit, TI Part No.
2240805-0003
*
Monitor cable set, TI Part No.
*
Color Display Unit manual, TI Part No.
2534995-0001
2240838-0001
The international color display unit kit, TI Part No.
8004 includes the following items:
*
Color display unit, TI Part No.
* Monitor cable set, TI Part No.
2240805-
2240805-0004
2534995-0001
*
Power cable, 240 volt, 50 Hertz, TI Part
0002
*
Color Display Unit manual, TI Part No.
No.
2534994-
2240838-0001
6.4.2.2
Color Display Unit Tabulated Information. Tables 6-84
through 6-89 provide tabulated information about the color
display unit.
2241092-0001
6-135
Hardware Options
Table 6-84
Signal
BUSINESS-PRO Hardware Reference
Color Display Unit/Controller Interface Connector J2
Pin
Number
Description
MODE SELECT
1
The CRT controller generates
this signal to place the
attached monitor in either
the TI mode or the PC-AT
mode. The low state of MODE
places the monitor in the
TI mode; the high state
places it in the PC-AT mode.
HSYNC
2
Horizontal synchronization
signal output from the CRT
controller.
VSYNC
3
vertical synchronization
signal output from the CRT
controller.
RED VIDEO
GREEN VIDEO
BLUE VIDEO
INTENSITY
4
6
The state of these controllergenerated signals determine
the color displayed by the
monitor.
SPEAKER
12
A timer on the main logic
board generates "this audio
input to the monitor speaker.
14
No connection.
15
No connection.
KBDATA
17
Keyboard data. This is the
bidirectional serial data
line that carries data
between the keyboard and
the keyboard controller
on the main logic board.
KBCLOCK
21
Keyboard clock. The keyboard
generates this clock to
synchronize data transfers
between it and the keyboard
controller on the main logic
board.
8
10
6-136
2241092-0001
BUSINESS-PRO Hardware Reference
Hardware Options
Table 6-84 Color Display Unit/Controller Interface Connector J2 (Cont)
Signal
Pin
Number
Description
MOUSEDATA
23
Mouse data. This line carries
the serial data from the mouse
to the main logic board.
+5V
22
+5 volts dc supply voltage for
the monitor.
NOTE:
Pin 19 is reserved. Pins 14, 15, 24, and 25 are not connected.
Pins 5, 7, 9, 11, 13, 16, 18, and 20 are connected to ground.
The connector shield is connected to chassis ground.
6.4.2.3 Displayed Colors.
The RED VIDEO, GREEN VIDEO, BLUE
VIDEO and INTENSITY input signals determine the colors displayed
by the color display unit.
Table 6-85 lists the displayed
colors and the signal-state combinations that cause them.
2241092-0001
6-137
Hardware Options
BUSINESS-PRO Hardware Reference
Table 6-85
Color Display Unit Color Map
Signal State
Color
INTENSITY
RED
GREEN
BLUE
----------------------------------------------------------------Black
0
0
0
0
Blue
0
0
0
I
Green
0
0
1
0
Cyan
0
0
1
I
Red
0
1
0
0
Magenta
0
1
0
1
Brown
0
1
1
0
White
0
1
1
1
Gray
1
0
0
0
Light blue
1
0
0
1
Light green
1
0
1
0
Light cyan
1
0
1
1
Light red
1
1
0
0
Light magenta
1
1
0
I
Yellow
I
1
1
0
White
1
1
1
1
-----------------------------------------------------------------
6-138
2241092-0001
Hardware Options
BUSINESS-PRO Hardware Reference
Table 6-86
Color Display Unit Video AC Parameters
PC-AT Mode
Parameter
TI Mode/Mono Mode
Video dot rate
18.000 megahertz
14.318 megahertz
Video dot time
55.550 nanoseconds
69.840 nanoseconds
Active scan lines
300
200
VSYNC pulse width
0.156 milliseconds
1.020 milliseconds
VSYNCH front porch
0.000 milliseconds
1.530 milliseconds
VSYNCH back porch
0.884 milliseconds
1. 400 milliseconds
Vertical retrace
1. 040 milliseconds
3.950 milliseconds
Active
15.600 milliseconds
12.740 milliseconds
Total
16.640 milliseconds
16.690 milliseconds
Vertical rate
60.100 Hertz
59.920 Hertz
HSYNC pulse width
4.500 microseconds
4.470 microseconds
HSYNC front porch
2.000 microseconds
5.590 microseconds
HSYNC back porch
5.500 microseconds
8.940 microseconds
Horizontal retrace
12.000 microseconds
19.000 microseconds
Active
40.000 microseconds
44.700 microseconds
Total
52.000 microseconds
63.700 microseconds
Horizontal rate
19.231 kilohertz
15.700 kilohertz
Total scan lines
320
262
Vertical display
time:
Horizontal display
time:
Horizontal pixels
640
720
-----------------------------------------------------------------
2241092-0001
6-139
Hardware Options
BUSINESS-PRO Hardware Reference
6.4.2.4
Keyboard/Mouse Cable Connector J4.
Two identical
connectors (both labeled J4) located at the front of the display
unit base allow the user to connect both a keyboard and/or a
mouse. Both connectors are identical; therefore, you can use
either one for the keyboard or the mouse.
Table 6-87 lists the
connector signals and their assigned pin numbers.
Table 6-87
Signal
Keyboard/Mouse Connector J4
Pin
Number
Description
KBCLOCK
1
Keyboard clock. The keyboard
generates this clock to synchronize
data over the keyboard data line.
KBDATA
2
Keyboard data. Bidirectional data
line that handles the bit-serial
data transfers between the keyboard
and the main logic board.
3
Reserved.
GND
4
Ground.
+5V
5
+5 volts dc.
MOUSEDATA
6
Mouse data line. Bit-serial data
line that transfers data from the
mouse to the main logic board.
SPEAKER
7
Speaker. Audio output from the
speaker amplifier on the main
logic board.
GND
8
Ground.
NOTE:
The connector shield is connected to chassis ground.
6-140
2241092-0001
Hardware Options
BUSINESS-PRO Hardware Reference
Table 6-88
Color Display unit Performance Specifications
Specification
TI Mode/Mono Mode
PC-AT Mode
Characteristic
Resolution
720 by 300
pixels
640 by 200 or
320 by 200 pixels
Colors displayed
8 (maximum)
16 (maximum)
Character resolution
25 rows by
80 columns
25 rows by
80 columns
Horizontal scan rate
19.231 kilohertz
15.700 kilohertz
vertical scan rate
60.10 Hertz
59.92 Hertz
video dot rate
18.000 megahertz
14.318 megahertz
Display size
9.45 by 7.09
inches
9.45 by 6.69
inches
Table 6-89
Color Display Unit AC Power Requirements
Value
Item
Domestic Version
International Version
Voltage
90 to 140 volts ac
180 to 264 volts ac
Frequency
57 to 63 Hertz
47 to 53 Hertz
Power
110 watts (maximum)
110 watts (maximum)
2241092-0001
6-141
Hardware Options
BUSINESS-PRO Hardware Reference
6.4.3 Monochrome Display Unit
The optional monochrome display unit is a 12-inch, mediumresolution monochrome monitor that features an anti-glare CRT
display and medium-persistence (P42), green phosphor.
The unit
also features dual-mode resolution that allows it to be operated
with either the TI mode or the PC-AT mode CRT controllers.
The
unit mounts on a tilt/swivel base that contains the following
connectors:
*
Two interchangeable keyboard/mouse connectors
*
A data interface connector
*
A power connector
The unit enclosure also contains an audio speaker. Both domestic
and international versions of the display unit are available.
6.4.3.1 Monochrome Display Unit Kit. The domestic version of
the monochrome display unit kit, TI Part No.
2240804-8001,
includes the following items:
* Monochrome display unit, TI Part No.
* Monitor cable set, TI Part No.
*
2240804-0001
2534995-0001
Power cable, 120 volt, 60 Hertz, TI Part
0001
* Monochrome Display Unit manual,
TI
No.
Part No.
25349942240828-
0001
The international version of the monochrome display unit kit,
Part No.
2240804-8002, includes the following items:
*
Monochrome display unit, TI Part No.
* Monitor cable set, TI Part No.
*
Power
0002
cable,
TI
2240804-0002
2534995-0001
240 volt, 50 Hertz, TI Part No.
* Monochrome Display Unit manual, TI
Part
No.
25349942240828-
0001
6.4.3.2
Monochrome Display Unit Tabulated Information. Tables
6-90 through 6-95 provide tabulated information about
the
monochrome display unit.
2241092-0001
6-143
Hardware Options
Table 6-90
BUSINESS-PRO Hardware Reference
Monochrome Display Unit/Controller Interface Connector J2
Signal
Pin
Number
Description
MODE SELECT
1
The CRT controller generates
this signal to place the
attached monitor in either
the TI mode or the PC-AT
mode. The low state of MODE
SELECT places the monitor in
the TI mode; the high state
places it in the PC-AT mode.
HSYNC
2
Horizontal synchronization
signal output from the CRT
controller.
VSYNC
3
vertical synchronization
signal output from the CRT
controller.
RED VIDEO
GREEN VIDEO
BLUE VIDEO
INTENSITY
4
10
The state of these controllersignals determine
the intensity of the monitor
screen display.
SPEAKER
12
A timer on the main logic
board generates this audio
input to the monitor speaker.
KBDATA
17
Keyboard data. This is the
bidirectional serial data
line that carries data
between the keyboard and
the keyboard controller on
the main logic board.
KBCLOCK
21
Keyboard clock. The keyboard
generates this clock to
synchronize data transfers
between the keyboard and the
keyboard controller' on the
main logic board.
6
8
gener~ted
6-144
2241092-0001
BUSINESS-PRO Hardware Reference
Hardware Options
Table 6-90 Monochrome Display Unit/Controller Interface Connector J2
Pin
Number
Description
+5V
22
+5 volts dc supply voltage for
the monitor.
MOUSEDATA
23
Mouse data. This line carries
the serial data from the mouse
to the main logic board.
Signal
NOTE:
Pin 19 is reserved. Pins 14, 15, 24, and 25 are not connected.
Pins 5, 7, 9, 11, 13, 16, 18, and 20 are connected to ground.
The connector shield is connected to chassis ground.
6.4.3.3 Displayed Intensities.
The RED VIDEO, GREEN VIDEO, BLUE
VIDEO,
and INTENSITY input signals determine the intensity level
of the display screen.
Table 6-91
lists
the
displayed
intensities and the signal-state combinations that cause them.
2241092-0001
6-145
Hardware Options
Table 6-91
BUSINESS-PRO Hardware Reference
Monochrome Display unit Intensity Levels
Signal State
Level
INTENSITY
RED
GREEN
BLUE
----------------------------------~------------------- -----------
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
10
1
0
1
0
11
1
0
1
1
12
1
1
0
0
13
1
1
0
1
14
1
1
1
0
15 (Maximum)
1
1
1
1
(Minimum)
-----------------------------------------------------------------
6-146
2241092-0001
Hardw,are Options
BUSINESS-PRO Hardware Reference
Table 6-92
Monochrome Display Unit Video AC Parameters
PC-AT Mode
Parameter
TI Mode/Mono Mode
Video dot rate
18.000 megahertz
14.318 megahertz
Video dot time
55.55 nanoseconds
69.84 nanoseconds
Active scan lines
300
200
VSYNC pulse width
0.156 milliseconds
1.020 milliseconds
VSYNCH front porch
0.000 milliseconds
1.530 milliseconds
VSYNCH back porch
0.884 milliseconds
1. 400 milliseconds
Vertical retrace
1. 040 milliseconds
3.950 milliseconds
Active
15.600 milliseconds
12.740 milliseconds
Total
16.640 milliseconds
16.690 milliseconds
Vertcal rate
60.100 Hertz
59.920 Hertz
HSYNC pulse width
4.500 microseconds
4.470 microseconds
HSYNC front porch
2.000 microseconds
5.590 microseconds
HSYNC back porch
5.500 microseconds
8.940 microseconds
Horizontal retrace
12.000 microseconds
19.000 microseconds
Active
40.000 microseconds
44.700 microseconds
Total
52.000 microseconds
63.700 microseconds
Horizontal rate
19.231 kilohertz
15.700 kilohertz
Total scan lines
320
262
Horizontal pixels
720
640
Vertical display
time:
Horizontal display
time:
2241092-0001
6-147
BUSINESS-PRO Hardware Reference
Hardware Options
6.4.3.4
Keyboard/Mouse Cable Connector J4.
Two identical
connectors (both labeled J4) located at the front of the display
unit base allow the user to connect both a keyboard and/or a
mouse. Both connectors are identical. Therefore, you can use
either one for the keyboard or the mouse. Table 6-93 lists the
connector signals and their assigned pin numbers.
Table 6-93
Signal
Keyboard/Mouse Connector J4
Pin
Number
Description
KBCLOCK
1
Keyboard clock. The keyboard
generates this clock to
synchronize data over the
keyboard data line.
KBDATA
2
Keyboard data. Bidirectional
data line that handles the
bit-serial data transfers
between the keyboard and the
main logic board.
3
Reserved.
GND
4
Ground.
+5V
5
+5 volts dc.
MOUSEDATA
6
Mouse data line. Bit-serial
data that transfers data
from the mouse to the main
logic board.
SPEAKER
7
Speaker. Audio output from
the speaker amplifier on the
main logic board.
GND
8
Ground.
NOTE:
The connector shield is connected to chassis ground.
6-148
2241092-0001
Hardware Options
BUSINESS-PRO Hardware Reference
Table 6-94
Monochrome Display Unit Performance Specifications
Specification
TI Mode/Mono Mode
PC-AT Mode
Characteristic
Resolution
720 by 300
pixels
640 by 200 or
320 by 200 pixels
Intensities displayed
8 (maximum)
16 (maximum)
Character resolution
25 rows by
80 columns
25 rows by
80 columns
Horizontal scan rate
19.231 kilohertz
15.700 kilohertz
vertical scan rate
60.10 Hertz
59.92 Hertz
Video dot rate
18.000 megahertz
14.318 megahertz
Display size
8.11 by 6.06
inches
8.11 by 6.06
inches
Table 6-95
Monochrome Display Unit AC Power Requirements
Value
International Version
Item
Domestic Version
Voltage
90 to 130 volts ac
200 to 250 volts ac
Frequency
57 to 63 Hertz
47 to 53 Hertz
Power
37 watts (maximum)
37 watts (maximum)
2241092-0001
6-149
BUSINESS-PRO Hardware Reference
6.5
Hardware Options
TI MODE RS-232 SERIAL INTERFACE
The optional TI mode video controller is a half-sized,
8-bit
board
that
provides
one
of
two
switch-selectable
TI
communications ports.
The controller
handles
asynchronous
protocols as well as most synchronous protocols, including
synchronous data link control (SDLC) and high-level data link
control (HDLC).
The board does not require the programming of
any software delays when performing back-to-back I/O cycles.
6.5.1 TI Mode RS-232 Serial Interface Kit
The TI mode RS-232 serial interface kit, TI
0001, includes the following items:
*
TI mode RS-232
2240934-0001
*
TI Mode RS-232 Serial Interface
2241042-0001
serial
interface
Part
board,
manual,
TI
No.
2240969-
TI Part No.
Part
No.
NOTE
The TI mode RS-232 serial interface can be
programmed in the PC-AT
mode,
provided
existing software is modified to address its
I/O ports.
6.5.2 TI Mode RS-232 Serial Interface Tabulated Information
Tables 6-96 through 6-99 provide tabulated information about
TI mode RS-232 serial interface.
2241092-0001
6-151
the
Hardware Options
Table 6-96
Signal
BUSINESS-PRO Hardware Reference
TI Mode RS-232 Serial Interface Connector J1
Pin
Number
Signal Name
AA
1
Chassis ground
BA
2
Transmitted data
BB
3
Received data
RTS/CA
4
Request-to-send
CTS/CB
5
C1ear-to-send
DSR/CC
6
Data-set ready
AB
7
Signal ground
DCD/CF
8
Data carrier detect
SCA/CH
11
Secondary request-to-send
SCF/CI
12
Secondary c1ear-to-send
TXC/DB
15
Transmitter clock in
RSC/DD
17
Receiver clock in
DTR/CD
20
Data terminal ready
RI/CE
22
Ring indicator
SCA/CH
23
Secondary request-to-send
DA
24
External transmitter clock
NOTE:
Pins 9, 10, 13, 14, 16, 18, 19, 21, and 25 are not connected.
NOTE
When operated in the TI mode, IRQ10 and IRQ11
are rerouted by the hardware to IRQO and
IRQ1, respectively for TI compatibility.
6-152
2241092-0001
Hardware Options
BUSINESS-PRO Hardware Reference
Table 6-97
Port
Port-Selection Switches SWl-l Through SWl-4
SWl-l
Switch Settings
SWl-2
SWl-3
SWl-4
1
ON
ON
OFF
OFF
2
OFF
OFF
ON
ON
Table 6-98
TI Mode RS-232 Serial Interface Port Addresses
------\,
Port 1
Address
(Hex)
Port 2
Address
(Hex)
OOEO
00E8
Interrupt acknowledge. An I/O write
operation at this address followed
by an I/O write operation performs
an, interrupt-acknowledge operation.
00E4
OOEC
Channel B command. These addresses
allow access to any 1 of 15 read
or write registers that control
the Z8530 operations.
00E5
OOED
Channel B data. These addresses
are used to read received data
and to write transmitted data.
00E6
OOEE
Channel A command. These addresses
allow access to any 1 of 15 read
or write registers that control the
Z8530 operations.
00E7
OOEF
Channel A data. These addresses
are used to read received data
and to write transmitted data.
Function
NOTES:
For additional information on programming the Z8530, refer to
Zilog(R) literature.
1
Zilog is a registered trademark of Zilog Incorporated.
2241092-0001
6-153
Hardware Options
BUSINESS-PRO Hardware Reference
6.5.3 Baud Rate Generation
An on-board 4.9152-megahertz crystal oscillator and a divide-by-2
counter provide a clock for the internal baud rate generators of
the Z8530.
Table 6-99 lists the possible baud rates and their
synchronous (sync) and asynchronous (async) program values.
Table 6-99
TI Mode RS-232 Interface Programmable Baud Rate Values
----------------------------------------------------------------Values
Baud Rate
Sync
Async
Error Percentage
Sync
Async
----------------------------------------------------------------19 200
62
2
0.000
0.000
9 600
126
6
0.000
0.000
7 200
169
9
-1. 960
-3.030
4 800
254
14
0.000
0.000
3 600
339
19
0.098
1. 587
2 400
510
30
0.000
0.000
2 000
612
36
0.065
1. 053
1 800
681
41
-0.049
-0.775
1 200
1 022
62
0.000
0.000
600
2 046
26
0.000
0.000
300
4 094
54
0.000
0.000
200
6 142
82
0.000
0.000
150
8 190
10
0.000
0.000
134.5
9 134
69
0.001
0.001
110
11 169
96
-0.001
0.026
75
16 382
1 022
0.000
0.000
50
24 574
1 534
0.000
0.000
-------------------------~-------~-------------------------------
6-154
2241092-0001
BUSINESS-PRO Hardware Reference
6.6
Hardware Options
OPTICAL MOUSE
The optical mouse is an input-only device that detects the amount
and direction of motion of the mouse on a 9-inch by II-inch
reflective pad.
The mouse features three command buttons. The
mouse communicates to the system through the serial port whose
I/O address is determined by the position of the serial switch on
the main logic board. The mouse connects to either of the 8-pin
connectors on the front of either of the optional display units.
The mouse is compatible with Mouse Systems M2.
6.6.1 Optical Mouse Kit
The optical mouse kit, TI Part No.
following items:
2536970-0001, includes the
*
Optical mouse and pad, TI Part No.
*
Optical Mouse manual, TI Part No.
2240954-0001
2241060-0001
6.6.2 Optical Mouse Tabulated Information
Tables 6-100 through 6-102 provide tabulated
the optical mouse.
Table 6-100
Signal
information
Optical Mouse Interface Signals
Pin
Number
Description
GND
4
Ground.
+5V
5
+5 volts dc.
MOUSEDATA
6
Mouse data line. Bit-serial data
line that transfers data from the
mouse to the main logic board.
GND
8
Ground.
NOTE:
Pins 1, 2, 3, and 7 are not used by the mouse.
2241092-0001
6-155
about
Hardware Options
BUSINESS-PRO Hardware Reference
Table 6-101
Byte
Bit 7
Bit 6
Bit 5
Mouse Data Format
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-----------------------------------------------------------------
R
1
1
0
0
0
0
L
2
X7
X6
X5
X4
X3
X2
Xl
XO
3
Y7
Y6
Y5
Y4
Y3
Y2
Yl
YO
4
X7
X6
X5
X4
X3
X2
Xl
XO
5
Y7
Y6
Y5
Y4
Y3
Y2
Yl
YO
M
NOTES:
l. L, M, and R represent the reporting bits of the left,
middle, and right command buttons, respectively. An
activated button produces a zero bit.
2. Bytes 2 and 3 are the twos complement of report number n.
3 . Bytes 4 and 5 are the twos complement of report number n+l.
4. XO and YO are the least significant data bits.
Table 6-102
Optical Mouse Performance Specifications
Characteristic
Specification
Movement/data generation
Electro-optical
Resolution
100 lines per inch
Data sampling rate
20 reports per second (minimum)
Data rate
1 200 baud
Tracking velocity
30 inches per second (maximum)
6-156
2241092-0001
BUSINESS-PRO Hardware Reference
6.7
Hardware Options
80287 NUMERIC COPROCESSOR
The microprocessor and the coprocessor together compose the
central processing unit of the BUSINESS-PRO computer. Either a
4-megahertz or an 8-megahertz 80287 coprocessor can be added to
the CPU by inserting the coprocessor in the socket provided and
setting the jumper plugs at J4 and J5 for the appropriate clock
speeds.
NOTE
When installing a coprocessor in the main
logic board (TI Part No.
2240843-0001), no
jumpers
are
required.
The
following
information about jumpers J4 and J5 apply
only to the main logic board (TI Part No.
2535670-0001).
When installing a coprocessor operating at 4 megahertz, insert a
jumper plug between pins 1 and 2 of J4 and insert another at J5.
For this operating mode, the coprocessor uses the same system
clock as does the CPU. An internal divider in the coprocessor
reduces this l2-megahertz clock to a frequency of 4 megahertz.
When installing an 8-megahertz coprocessor, insert the jumper
between pins 2 and 3 of J4 and omit the jumper at J5. This
configuration supplies an 8-megahertz, 1/3-duty cycle clock to
the coprocessor.
This clock is not internally divided, so with
this configuration, the coprocessor runs at a frequency of 8
megahertz.
Since the coprocessor and the MPU operate in parallel, the MPU
can continue to perform other functions while the coprocessor
handles mathematical calculations. Both the coprocessor and the
MPU decode the special escape instructions in the instruction
stream, and the MPU supervises all data transfer operations and
instruction execution for the coprocessor.
If the coprocessor is not
present,
the
special
escape
instructions either have no effect or cause an exception.
Therefore, the software should check for the presence of a
coprocessor and use the appropriate routines as required. A math
coprocessor presence bit is located in the RAM internal to the
real-time clock (RTC) chip at bit 1 of address 0014H.
On receiving an instruction, the coprocessor activates its BUSYsignal to notify the MPU that instruction execution is in
progress. The processor WAIT instruction then forces the MPU to
2241092-0001
6-157
Hardware Options
BUSINESS-PRO Hardware Reference
wait for the results of the
processing other instructions.
coprocessor
calculation before
If the appropriate coprocessor internal exception mask is not
set, the device activates its ERROR- signal on detecting an
exception condition.
This ERROR- signal generates hardware
interrupt 13 and causes the BUSY- signal to the MPU to latch in
the busy state. An input/output (I/O) write operation to address
OOFOH with DO through D7 set to zero clears the BUSY- signal. If
the coprocessor needs data to complete its calculation, it
signals the MPU by activating the processor enable request
(PEREQ) line, and the MPU acknowledges the request by activating
the processor enable acknowledge (PEACK-) line.
As with the MPU, a system reset operation places the coprocessor
in the real address mode from which it can be placed in the
protected virtual address mode by an Enter Protected Mode
(FSET~M) instruction.
Just as with the MPU, the only way to
return the coprocessor to the real address mode is to res~t the
device. The operating system can do this without affecting the
MPU or any other circuitry by writing all zeros to data bits DO
through D7 at I/O port address OOFlH.
I/O ports 00F8H to OOFFH are reserved for the 80286/80287
interface.
To guarantee correct operation of the coprocessor,
programs must not perform any I/O operations to these addresses.
6-158
2241092-0001
Memory and I/O Maps
BUSINESS-PRO Hardware Reference
Appendix A
System Memory and I/O Maps
This appendix provides general maps of the BUSINESS-PRO memory
and I/O addresses.
Each table defines the address assignments
for both the IBM Personal Computer AT (PC-AT) mode and the TI
Professional Computer (TI) mode.
Appendixes Band C provide
detailed I/O maps for the TI mode and the
PC-AT
mode,
respectively.
Table A-l
Memory Map (Real Mode)
Address Range
(Hexadecimal)
PC-AT Mode
000000-07FFFF
5l2-kilobyte RAM
5l2-kilobyte RAM
080000-09FFFF
128-ki1obyte RAM
l28-kilobyte RAM
OAOOOO-OBFFFF
Video display RAM
Option memory
OCOOOO-OD7FFF
Option memory
Graphics ROM
OD8000-0DDFFF
Option memory
Reserved
ODEOOO-ODFFFF
Option memory
Char memory
OEOOOO-OEFFFF
Reserved
Reserved
OFOOOO-OFFFFF
64-ki1obyte
system ROM
64-kilobyte
system ROM
2241092-0001
A-l
TI Mode
Memory and I/O Maps
Table A-2
Address Range
(Hexadecimal)
BUSINESS-PRO Hardware Reference
Memory Map (Virtual/Protected Mode)
PC-AT Mode
TI Mode
100000-3FFFFF
3-megabyte memory PWB
3-megabyte memory PWB
400000-EFFFFF
II-megabyte memory
expansion RAM
II-megabyte memory
expansion RAM
FOOOOO-FDFFFF
Reserved
Reserved
FEOOOO-FEFFFF
64-kilobyte reserved
64-kilobyte reserved
FFOOOO-FFFFFF
64-kilobyte system ROM
64-kilobyte system ROM
Table A-3
Address
(Hex)
System I/O Maps
PC-AT Mode
TI Mode
0000
DMA channel 0* address
Timer port
0001
DMA channel 0* word count
Printer input port
0002
DMA channel 1* address
Printer data
0003
DMA channel 1* word count
LEDs and printer output
0004
DMA channel 2 address
DMA channel 2 address
0005
DMA channel 2 word count
DMA channel 2 word count
0006
DMA channel 3 address
DMA channel 3 address
0007
DMA channel 3 word count
DMA channel 3 word count
0008
Read status; write command
Read status; write command
0009
write request register
Write request register
OOOA
Write single mask
register bit
Write single mask
register bit
* DMA channels 0 and 1 are not accessible in the TI mode.
A-2
2241092-0001
BUSINESS-PRO Hardware Reference
Table A-3
Address
(Hex)
Memory and I/O Maps
System I/O Maps (Continued)
PC-AT Mode
TI Mode
OOOB
write mode register
Write mode register
OOOC
Clear byte pointer
flip-flop
Clear byte pointer
flip-flop
OOOD
Read temporary register;
write master clear
Read temporary register;
write master clear
OOOE
Clear mask register
Clear mask register
OOOF
Write all mask register
bits
Write all mask register
bits
0010
Not usable
Not usable
0011
Not usable
Not usable
0012
PC-AT or TI mode port
PC-AT or TI mode port
0013
LED port
Not usable
0014
Not usable
8253 counter 0
0015
Not usable
8253 counter 1
0016
Not usable
'8253 counter 2
0017
Not usable
8253 control
0018
Not usable
8259 interrupt 1
(duplicate)
0019
Not usable
8259 interrupt 1
(duplicate)
OOIA
Not usable
Not usable
I
I
I
OOIF
0020
8259 interrupt 1
8259 interrupt 1
(duplicate)
0021
8259 interrupt 1
8259 interrupt 1
(duplicate)
0022
Not usable
Not usable
I
003F
2241092-0001
I
I
A-3
Memory and I/O Maps
BUSINESS-PRO Hardware Reference
Table A-3
Address
(Hex)
System I/O Maps (Continued)
PC-AT Mode
TI Mode
0040
8254 timer counter 0
8254 timer counter 0
0041
8254 timer counter 1
8254 timer counter 1
0042
8254 timer counter 2
8254 timer counter 2
0043
8254 timer control
register
8254 timer control
register
0044
Not usable
Not usable
I
005F
I
I
0060
Keyboard·data
Keyboard data
0061
Port B
Port B
0062
Not usable
Not usable
0063
Not usable
Not usable
0064
Keyboard status/command
port
Keyboard status/command
port
0065
Not usable
Not usable
I
0067
I
I
0068
Memory control port
Memory control port
0069
Not usable
Not usable
I
006F
I
I
0070
RTC address port/enable
NMI
RTC address port/enable
NMI
0071
RTC data port
RTC data port
0072
Not usable
Not usable
I
007F
0080
I
I
Diagnostic-checkpoint
port
A-4
Diagnostic-checkpoint
port
2241092-0001
BUSINESS-PRO Hardware Reference
Table A-3
Address
(Hex)
Memory and I/O Maps
System I/O Maps (Continued)
PC-AT Mode
TI Mode
0081
DMA channel 2--diskette
(page address)
DMA channel 2--diskette
(page address)
0082
DMA channel 3
DMA channel 3
0083
DMA channel 1
DMA channel 1
0084
Not used
Not used
0086
I
I
I
0087
DMA channel 0
DMA channel 0
0088
Not used
Not used
0089
DMA channel 6
DMA channel 6
008A
DMA channel 7
DMA channel 7
008B
DMA channel 5
DMA channel 5
008C
Not used
Not used
008E
I
I
008F
Refresh
Refresh
0090
Not usable
Not usable
I
I
I
009F
I
OOAO
8259 interrupt 2
8259 interrupt 2
OOAI
8259 interrupt 2
mask register
8259 interrupt 2
mask register
00A2
Not usable
Not usable
I
I
OOBF
I
OOCO
Channel 0 base and
current address
Channel 0 base and
current address
00C2
Channel 0 base and
current word count
Channel 0 base and
current word count
2241092-0001
A-5
Memory and I/O Maps
BUSINESS-PRO Hardware Reference
Table A-3
Address
(Hex)
System I/O Maps (Continued)
TI Mode
PC-AT Mode
00C4
Channel 1 base and
current address
Channel 1 base and
current address
00C6
Channel 1 base and
current word count
Channel 1 base and
current word count
00C8
Channel 2 base and
current address
Channel 2 base and
current address
OOCA
Channel 2 base and
current word count
Channel 2 base and
current word count
OOCC
Channel 3 base and
current address
Channel 3 base and
current address
OOCE
Channel 3 base and
current word count
Channel 3 base and
current word count
0000
Read status; write
command register
Read status; write
command register
0002
Write request register
Write request register
0004
Write single mask
register bit
Write single mask
register bit
0006
Write mode register
Write mode register
0008
CI~ar byte pointer
flip-flop
Clear byte pointer
flip-flop
OODA
Read temporary register;
write master clear
Read temporary register;
write master clear
OODC
Clear mask register
Clear mask register
OODE
Write all mask register
bits
Write all mask register
bits
OOEO
Comm port 1 (TI)
Comm port 1 (TI)
I
00E7
I
I
A-6
2241092-0001
BUSINESS-PRO Hardware Reference
Table A-3
Address
(Hex)
OOES
I
Memory and I/O Maps
System I/O Maps (Continued)
PC-AT Mode
TI Mode
Comm port 2 (TI)
Comm port 2 (TI)
I
OOEF
I
OOFO
Coprocessor busy latch
clear
Coprocessor busy latch
clear
OOFl
Reset coprocessor
Reset coprocessor
00F2
Not usable
Not usable
00F7
I
I
OOFS
I
Coprocessor
I
OOFF
0100
I
I
I
Not used
Not used
I
OllF
0120
Coprocessor
I
Reserved
Reserved
I
016F
I
0170
Fixed disk data register
(alternative)
Fixed disk data register
(alternative)
0171
Fixed disk error/write
precompensation register
Fixed disk error/write
precompensation register
0172
Fixed disk sector count
Fixed disk sector count
0173
Fixed disk sector number
\ Fixed disk sector number
0174
Fixed disk cylinder low
Fixed disk cylinder low
0175
Fixed disk cylinder high
Fixed disk cylinder high
0176
Fixed disk drive/head
Fixed disk drive/head
0177
Fixed disk status/command
register
Fixed disk status/command
register
2241092-0001
A-7
Memory and I/O Maps
BUSINESS-PRO Hardware Reference
Table A-3
Address
(Hex)
System I/O Maps (Continued)
PC-AT Mode
TI Mode
0178
Not used
Not used
OlEF
I
I
I
OlFO
Fixed disk data register
Fixed disk data register
OlFl
Fixed disk error/write
precompensation register
Fixed disk error/write
precompensation register
01F2
Fixed disk sector count
Fixed disk sector count
01F3
Fixed disk sector number
Fixed disk sector number
01F4
Fixed disk cylinder low
Fixed disk cylinder low
OlFS
Fixed disk cylinder high
Fixed disk cylinder high
01F6
Fixed disk drive/head
Fixed disk drive/head
01F7
Fixed disk status/command
register
Fixed disk status/command
register
01F8
Not used
Not used
OlFF
I
I
0200
Game I/O
Game I/O
0207
I
I
0.208
Not used
Not used
021F
I
I
I
I
I
0220
I
Tape drive
Tape drive
0227
I
I
0228
Not used
Not used
0277
I
I
I
0278
I
027F
Printer port 2 (PC-AT)
I
Printer port 2 (PC-AT)
I
A-8
2241092-0001
BUSINESS-PRO Hardware Reference
Table A-3
Address
(Hex)
0280
Not used
I
I
Serial port 2 (PC-AT)
Prototype board
I
Serial port 2 (PC-AT)
I
I
02FF
0300
TI Mode
Not used
I
I
System I/O Maps (Continued)
PC-AT Mode
02F7
02F8
Memory and I/O Maps
Prototype board
03lF
I
I
0320
Not used
Not used
I
I
I
036F
0370
I
Alt floppy controller
I
0377
0378
I
0380
I
Printer port 1 (PC-AT)
I
037F
Printer port 1 (PC-AT)
I
SDLC, bisynchronous 2
I
Alt floppy controller
SDLC, bisynchronous 2
038F
I
I
0390
Not used
Not used
I
I
I
039F
03AO
I
BiSinChronous 1
BisinChronous 1
Monochrome display and
printer
Monochrome display and
printer
03AF
03BO
I
03BF
I
I
03CO
Reserved
Reserved
03CF
I
I
I
2241092-0001
A-9
Memory and I/O Maps
BUSINESS-PRO Hardware Reference
Table A-3
Address
(Hex)
System I/O Maps (Continued)
PC-AT Mode
TI Mode
Color/graphics monitor
adarter
Color/graphics monitor
adarter
03EO
Not used
Not used
03EF
I
I
03DO
I
03DF
I
03FO
I
F10r py controller
F10r py controller
Serial port 1
Serial port 1
03F7
03F8
I
03FF
0400
I
7FFF
8000
I
87FF
8800
I
FFFF
I
I
Duplicate
Duplicate
I
I
Nonvolatile RAM
Nonvolatile RAM
I
I
Duplicate
Duplicate
I
I
A-10
2241092-0001
Memory and I/O Maps
BUSINESS-PRO Hardware Reference
Table A-4
DMA Channel Uses
Use
Channel
Table A-5
Device
Tape Drive
0
Spare
1
SDLC
2
Floppy disk
3
Tape drive
4
Cascade for
controller 1
5
Spare
6
Spare
7
Spare
Tape Drive Interrupt and DMA Levels
Default
Interrupt
Level
3
Default
DMA
Channel
3
Alternate
Interrupt
Levels
2,4,5,6,7
NOTES:
Refer to Table A-4 for DMA channel use.
Refer to Table 2-8 for interrupt map.
2241092-0001
A-11
Alternate
DMA
Levels
1,2
Memory and I/O Maps
Table A-6
BUSINESS-PRO Hardware Reference
Configurable Interrupt Levels
Default Interrupt Levels
PC-AT Mode
TI Mode
Device
TI Mode, RS-232, Serial Port:
Configured for Comm 1
Configured for Comm 2
10
11
00
01
Main Logic Board, Parallel Port:
Configured for Port 1
Configured for Port 2
07
05
07 and 05
04 and 05
Main Logic Board, Serial Port:
Configured for Port 1
Configured for Port 2
04
03
05
03
NOTE:
Refer to Table 2-8 for interrupt map.
A-12
2241092-0001
BUSINESS-PRO Hardware Reference
TI Mode I/O Maps
Appendix B
TI Mode I/O Maps
The tables in this appendix provide detailed
BUSINESS-PRO computer's TI mode.
Table B-1
Address
(Hex)
I/O
maps
Power-Up
State
a
Low
Speaker timer enable
1
Low
Timer 1 interrupt enable
2
Low
Timer 2 interrupt enable
0002
Description
3
Not used
7
I
a
Not used
3
I
I
0001
I
4
Printer port busy (active high)
5
Printer paper out (active high)
6
Printer selected (active high)
7
Printer fault (active low)
a
Printer data
I
I
7
0003
a
Low
LED 1 (low=on, high=off)
1
Low
LED 2 (low=on, high=off)
2
Low
LED 2 (low=on, high=off)
3
2241092-0001
the
Timer, DMA, and LED Control
Bit
0000
for
Not used
B-1
TI Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table B-1
Address
(Hex)
Bit
Timer, DMA, and LED Control (Continued)
Power-Up
State
Description
0003 (Continued)
4
Low
Printer auto-feed (active low)
5
Low
Printer strobe (active low)
6
Low
Printer initialize (active low)
7
Low
Printer interrupt enable (active
high)
0004
Channel 2 base and current address
0005
Channel 2 base and current word
count
0006
Channel 3 base and current address
0007
Channel 3 base and current word
count
0008
Read status, write command register
0009
write request register
OOOA
write single mask register bit
OOOB
Write mode register
OOOC
Clear byte pointer flip-flop
OOOD
Read temporary register;
write master clear
OOOE
Clear mask register
OOOF
Write all mask register bits
B-2
2241092-0001
BUSINESS-PRO Hardware Reference
Table B-2
Address
(Hex)
Bit
TI Mode I/O Maps
Mode Select and Timer
Power-Up
State
Description
0010
Not usable.
0011
Not usable.
0012
o
Low
PC-AT/TI mode enable
(low=PC-AT mode, high=TI mode).
1
Low
PC-AT/TI video enable
(low=PC-AT mode, high=TI mode).
2
Low
When high, this bit allows software
to force a parity error by reading a
memory location in the 640-ki1obyte
address range that has previously been
loaded with OOH, 55H, AAH, or FFH.
3
Read-only parity error (high byte).
4
Read-only parity error (low byte).
Write-only PC-AT video select bit (LSB).
5
Read-only RAM bank parity error code
bit o. Write-only PC-AT video select
bit 1.
6
Read-only RAM bank parity error code
bit 1. Write-only PC-AT video select
bit 2.
7
Read-only RAM bank parity error code
bit 2. Write-only PC-AT video select
bit (MSB) .
0013
Not usable.
0014
8253 counter O.
0015
8253 counter l .
0016
8253 counter 2.
0017
8253 control.
2241092-0001
B-3
TI Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table B-2
Address
(Hex)
Bit
Mode Select and Timer (Continued)
Power-Up
State
Description
0018
8259 interrupt (duplicate) .
0019
8259 interrupt mask register (duplicate) .
001A
Not usable.
I
I
001F
Table B-3
Interrupt Controller 1
Address
(Hex)
Description
0020
8259 interrupt (duplicate) .
0021
8259 interrupt mask register (duplicate) .
0022
Not usable.
I
I
003F
Table B-4
8254-2 Timer
Address
(Hex)
Description
0040
8254 timer counter O.
0041
8254 timer counter l .
0042
8254 timer counter 2.
0043
8254 timer control register.
0044
Not usable.
I
005F
I
B-4
2241092-0001
BUSINESS-PRO Hardware Reference
Table B-5
Address
(Hex)
Bit
8042 Keyboard
Power-Up
State
0060
0061
TI Mode I/O Maps
Description
Keyboard data register:
o
Low
Gate 2 input to 8254-2 timer.
1
Low
Timer 2 output enable (active
high) .
2
High
Parity error enable (active low).
3
High
Expansion bus NMI enable (active
low) .
4
Refresh bit.
5
Timer 2 output.
6
Expansion bus NMI.
7
Parity error.
0062
Not usable.
0063
Not usable.
0064
Keyboard control register read-only
status port:
o
Output buffer full. High indicates
data is available for reading.
1
Input buffer full. High indicates
data has been written into the
buffer but has not yet been read
by the controller.
2
3
2241092-0001
Low
System flag. This bit is defined
by the value written into the
command byte.
Command/data. High indicates data
has been written to address 64H
(command). Low indicates data has
been written to address 60H (data).
B-5
TI Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table B-5
Address
(Hex)
Bit
8042 Keyboard (Continued)
Power-Up
State
Description
0064 (Continued)
4
Inhibit switch. Low indicates all
keyboard functions are inhibited.
5
Transmit time-out. High indicates
a transmission started by the
keyboard controller was not
properly completed.
6
Receive time-out. High indicates
that a transmission started by
the keyboard controller was not
properly completed.
7
Parity error. High indicates a
parity error.
0064
Write-only command port. System
software can use this port to
reset the MPU. Refer to Section 2
of this manual for command
definitions.
0065
Not usable.
0067
I
I
0068
o
Low
Low enables a one-wait-state
memory cycle. High enables a
zero-wait-state memory cycle.
I
Low
Low enables single refreshes.
High enables burst refreshes.
2
Low
Nonvolatile RAM enable (high
disables 2 kilobytes of the
nonvolatile RAM).
3
Low
Low
4
Low
Bank select
enables expansion memory.
B-6
o.
2241092-0001
BUSINESS-PRO Hardware Reference
Table B-5
Address
(Hex)
TI Mode I/O Maps
8042 Keyboard (Continued)
Power-Up
State
Bit
Description
5
Low
Bank select 1.
6
Low
Bank select 2.
7
Low
High allows incoming data from the
parallel printer port of the main
logic board.
Table B-6
Address
(Hex)
0070
Bit
Real-Time Clock and NMI Mask
Power-Up
State
Description
0
Nonvolatile RAM address port
I
I
5
6
7
Not usable
High
NMI enabled (active low)
0071
Nonvolatile RAM data port
0072
Not usable
007F
I
I
2241092-0001
B-7
TI Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table B-7
DMA Page Register
Address
Description
0080
Diagnostic-checkpoint port. This
port is a read/write port in the
LS6l2 page register.
0081
DMA channel 2 (floppy drive).
0082
DMA channel 3 (tape drive).
0083
DMA channel 1 (SDLC) .
0084
Not used.
0086
I
I
0087
DMA channel O.
0088
Not used.
0089
DMA channel 6.
008A
DMA channel 7 .
008B
DMA channel 5.
008C
Not used.
008E
I
I
008F
Refresh.
0090
Not usable.
I
009F
I
B-8
2241092-0001
BUSINESS-PRO Hardware Reference
Table B-8
TI Mode I/O Maps
Slave Interrupt Controller
Address
(Hex)
Description
OOAO
8259 interrupt
OOAI
8259 interrupt mask register
00A2
Not usable
OOBF
I
I
Table B-9
DMA Controller 2
Address
(Hex)
Description
OOCO
Channel 0 base and current address
00C2
Channel 0 base and current word count
00C4
Channel 1 base and current address
00C6
Channel 1 base and current word count
00C8
Channel 2 base and current address
OOCA
Channel 2 base and current word count
OOCC
Channel 3 base and current address
OOCE
Channel 3 base and current word count
OODO
Read status; write command register
00D2
Write request register
00D4
Write single mask register bit
00D6
Write mode register
00D8
Clear byte pointer flip-flop
OODA
Read temporary register; write master clear
OODC
Clear mask register
OODE
Write all mask register bits
2241092-0001
B-9
TI Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table B-I0
Communication Ports
Address
Description
(Hex)
----------------------------------------------------------------OOEO
I
Communication port 1 interrupt acknowledge
I
00E3
00E4
Communication port 1 channel B command
OOES
Communication port 1 channel B data
00E6
Communication port 1 channel A command
00E7
Communication port 1 channel A data
OOES
Communication port 2 interrupt acknowledge
I
I
OOEB
OOEC
Communication port 2 channel B command
OOED
Communication port 2 channel B data
OOEE
Communication port 2 channel A command
OOEF
Communication port 2 channel A data
-------------------------------~-----------------~---- -----------
B-I0
2241092-0001
BUSINESS-PRO Hardware Reference
TI Mode I/O Maps
Table B-llCoprocessor
Address
(Hex)
OOFO
Bit
Description
o
7
Clear-coprocessor busy. Writing Os
to this port clears the latched
busy signal. (Activation of the
coprocessor error signal during a
coprocessor busy condition latches
the busy signal.)
o
I
Coprocessor reset. Writing Os to
this port resets the coprocessor.
I
OOFl
7
00F2
Not usable.
I
00F7
I
00F8
Reserved.
OOFF
I
I
NOTE
Addresses OlOOH through OllFH are not used.
Addresses 0120H through 016FH are reserved.
2241092-0001
B-ll
TI Mode I/O Maps
BUSINESS~PRO
Table B-12
Address
(Hex)
Hardware Reference
Alternate Fixed Disk
Description
Bit
0170
Data register
0171
Error register for read accesses;
write precompensation for write
accesses
0
Data address mark not found
1
Track 000 error
2
Aborted command
3
Not used
4
ID not found
5
Not used
6
Data ECC error
7
Bad block detected
0172
Sector count
0173
Sector number
0174
Cylinder low
0175
Cylinder high
0176
Size/drive/head
0
Head select 0
1
Head select 1
2
Head select 2
3
Head select 3
4
Drive 1=0; Drive 2-1
5
Sector size (low bit)
;1
~
B-12
2241092-0001
TI Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table B-12 Alternate Fixed Disk (Continued)
Address
(Hex)
Description
Bit
0176 (Continued)
6
Sector size (high bit)
7
High=ECC to be enabled
0177
Status register for read accesses;
command register for write accesses
o
Error
1
Index pulse from selected drive
2
Corrected data
3
Data request
4
Seek complete from the drive
5
write fault from the drive
6
Drive ready from the drive
7
Controller busy
NOTE
Addresses 0178H through 01EFH are not used.
2241092-0001
B-13
TI Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table B-13
Address
(Hex)
Fixed Disk
Bit
Description
OlFO
Data register
OlFl
Error register for read accesses;
write precompensation for write
accesses
0
Data address mark not found
1
Track 000 error
2
Aborted command
3
Not used
4
ID not found
5
Not used
6
Data ECC error
7
Bad block detected
01F2
Sector count
01F3
Sector number
01F4
Cylinder low
OlFS
Cylinder high
01F6
Size/drive/head
0
Head select 0
1
Head select 1
2
Head select 2
3
Head select 3
4
Drive 1=0; Drive 2=1
5
Sector size (low bit)
B-14
2241092-0001
BUSINESS-PRO Hardware Reference
TI Mode I/O Maps
Table B-13 Fixed Disk (Continued)
Address
(Hex)
Bit
Description
01F6 (Continued)
6
Sector size (high bit)
7
High=ECC to be enabled
01F7
Status register for read accesses;
command register for write accesses
o
Error
1
Index pulse from selected drive
2
Corrected data
3
Data request
4
Seek complete from the drive
5
Write fault from the drive
6
Drive ready from the drive
7
Controller busy
NOTE
Addresses 01F8H through 01FFH are not used.
Addresses 0200H through 0207H are reserved
for game I/O. Addresses 0208H through 0277H
are not used.
2241092-0001
B-15
TI Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table B-14
Address
(Hex)
Parallel Printer Port 2--0ption Board
Description
Bit
0278
Data latch.
0279
Printer status:
o
I
Not used.
I
2
3
Low indicates an error condition.
4
Printer selected (active high).
5
End of paper (active high).
6
Printer acknowledge (active high).
7
Printer busy (active low).
Printer controls:
027A
o
Strobe (active high).
1
Line feed.
2
Initialize printer (active low).
3
Printer select (active high).
4
Interrupt enable (active high).
5
Not used.
7
I
I
027B
Not usable.
027C
Data latch (duplicate).
027D
Printer status (duplicate):
o
Not used.
2
I
I
B-16
2241092-0001
BUSINESS-PRO Hardware Reference
Table B-14
Address
(Hex)
TI Mode I/O Maps
Parallel Printer Port 2--0ption Board (Continued)
Bit
Description
027D (Continued)
3
Low indicates an error condition.
4
Printer selected (active high).
5
End of paper (active high).
6
Printer acknowledge (active low).
7
Printer busy (active low).
027E
Printer controls (duplicate):
0
Strobe (active high).
1
Line feed.
2
Initialize printer (active low).
3
Printer select (active high).
4
Interrupt enable (active high).
5
Not used.
7
I
I
027F
Not usable.
NOTE
Addresses 0280H through 02F7H are not used.
2241092-0001
B-1?
TI Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table B-1SSerial Port 2
Address
(Hex)
Description
Bit
02F8
Transmit or receive buffer, or
least-significant byte of the
divisor latch.
02F9
Most-significant byte of the
divisor latch or interrupt enable
register. The following bit
definitions apply to the interrupt
enable register:
o
Enable data-available interrupt.
1
Enable transmit holding-register
empty interrupt.
2
Enable receive line status
interrupt.
3
Enable modem status interrupt.
4
Always set to logical O.
I
I
7
Interrupt identification register:
02FA
o
Interrupt is pending indicator.
1
2
These bits identify the highestpriority pending interrupt.
3
Always set to logical O.
I
I
7
Line control register:
02FB
o.
o
Word-length-select bit
1
Word-length-select bit 1.
2
Number of stop bits.
3
Parity enable.
B-18
I~
2241092-0001
BUSINESS-PRO Hardware Reference
Table B-15
Address
(Hex)
TI Mode I/O Maps
Serial Port 2 (Continued)
Bit
Description
02FB (Continued)
4
Even parity select.
5
Stuck parity.
6
Set break.
7
Divisor-latch-access bit.
02FC
Modem control register:
0
Data terminal ready.
1
Request-to-send.
2
Output 1.
3
Output 2.
4
Loop.
5
Always set to logical O.
I
I
7
02FD
2241092-0001
Line status register:
0
Receive data-ready indicator.
1
Overrun error indicator.
2
Parity error indicator.
3
Framing error indicator.
4
Break interrupt indicator.
5
Transmitter holding register
empty.
6
Transmitter shift register empty.
7
Always set to logical O.
B-19
TI Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table B-1S
Address
(Hex)
Description
Bit
Modem status register:
02FE
02FF
Serial Port 2 (Continued)
o
Delta clear-to-send.
1
Delta data-set ready.
2
Trailing-edge ring indicator.
3
Delta receive line signal detect.
4
Clear-to-send.
5
Data-set ready.
6
Ring indicator.
7
Receive line signal detect.
Reserved.
NOTE
Addresses 0300H through 031FH are reserved
for the prototype board.
Addresses 0320H
through 03SFH are not used. Addresses 0360H
through 036FH are reserved.
B-20
2241092-0001
BUSINESS-PRO Hardware Reference
Table B-16
Address
(Hex)
TI Mode I/O Maps
Alternate Floppy Disk Controller
Bit
Description
0370
Not usable
0371
Not usable
0372
Digital output register:
o
Drive select (low bit)
1
Drive select (high bit)
2
Function reset
3
Enable interrupts and DMA
4
Enable drive A motor
5
Enable drive B motor
6
Enable drive C motor
7
Enable drive D motor
0373
Not usable
0374
Status register:
o
Drive A busy/seeking
1
Drive B busy/seeking
2
Drive C busy/seeking
3
Drive D busy/seeking
4
Diskette-busy command in
progress
5
NonDMA mode
6
Data transfer direction
(high=floppy disk to host)
7
Master~data-register
request
2241092-0001
B-2l
ready
TI Mode I/O Maps
Table B-16
Address
(Hex)
BUSINESS-PRO Hardware Reference
Alternate Floppy Disk Controller (Continued)
Description
Bit
0375
Floppy disk data register
0376
Fixed disk register:
o
Reserved
1
Enables interrupt
2
Hard disk reset
3
Head select 3
Diagnostic register:
0377
o
Drive select 0 status
1
Drive select 1 status
2
Head select 0 status
3
Head select 1 status
4
Head select 2 status
5
Head select 3 or reduced
write current status
6
Write gate status
7
Disk change
Floppy disk register:
0377
o
Mode select (low bit)
1
Mode select (high bit)
2
Not used
I
I
7
B-22
2241092-0001
TI Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table B-17
Address
(Hex)
Parallel Printer Port 1 -- Option Board
Bit
Description
0378
Data latch.
0379
Printer status:
o
I
Not used.
3
Low indicates an error condition.
4
Printer selected (active high).
5
End of paper (active high).
6
Printer acknowledge (active low).
7
Printer busy (active low).
I
2
037A
Printer controls:
o
Strobe (active high).
1
Line feed.
2
Initialize printer (active low).
3
Printer select (active high).
4
Interrupt enable (active high).
5
Not used.
I
I
7
037B
Not usable.
037C
Data latch (duplicate).
037D
Printer status (duplicate):
o
Not used.
2
I
I
2241092-0001
B-23
BUSINESS-PRO Hardware Reference
TI Mode I/O Maps
Table B-17
Address
(Hex)
Parallel Printer Port 1 -- Option Board (Continued)
Description
Bit
037D (Continued)
3
Low indicates an error condition.
4
Printer selected (active high).
5
End of paper (active high).
6
Printer acknowledge (active low).
7
Printer busy (active low).
037E
Printer controls (duplicate):
0
Strobe (active high).
1
Line feed.
2
Initialize printer (active low).
3
Printer select (active high).
4
Interrupt enable (active high).
5
Not used.
7
I
I
037F
Not usable.
B-24
2241092-0001
BUSINESS-PRO Hardware Reference
Table B-18
Address
(Hex)
Bisynchronous 2
Description
Bit
8255A-5 port A:
0380
0
Low indicates an interface ring
indicator on condition.
1
Low indicates an interface data
carrier detect on condition.
2
An oscillating condition indicates
that the transmit clock is active.
3
Low indicates an interface clearto-send on condition.
4
An oscillating condition indicates
that the receive clock is active.
5
High indicates a modem status
change.
6
High indicates an active timer 2
output.
7
High indicates an active timer 1
output.
0381
2241092-0001
TI Mode I/O Maps
8255A-5 port B:
0
Low enables the modem interface
data signal rate select.
1
Low enables the modem interface
select standby.
2
Low enables the test function.
3
High resets the modem status
changed logic.
4
High resets the 8273.
5
High enables gate timer 2.
6
High enables gate timer 1.
7
Low enables level 4 interrupt.
B-25
TI Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table B-18
Address
(Hex)
Bisynchronous 2 (Continued)
Bit
0382
Description
8255A-5 port
c:
o
High enables gating of the internal
clock (output).
1
High enables gating of the external
clock (output).
2
High enables the electronic wrap
(output) .
3
Low enables gating of interrupts
3 and 4 (output).
4
An oscillating condition indicates
receive data (input).
5
An oscillating condition indicates
timer 0 output (input).
6
Low indicates test active (input).
7
Not used.
0383
8255 mode set register.
0384
8253 counter O.
0385
8253 counter 1.
0386
8253 counter 2.
0387
8253 control word (mode register).
0388
8273 read-only status register:
o
High indicates that the transmit
interrupt result is available.
1
High indicates that the receive
interrupt result is available.
2
High enables the transmit interrupt.
B-26
2241092-0001
BUSINESS-PRO Hardware Reference
Table B-18
Address
(Hex)
TI Mode I/O Maps
Bisynchronous 2 (Continued)
Bit
Description
0388 (Continued)
3
High enables the receive interrupt.
4
High indicates that the command
result buffer is full.
5
High indicates that the command
parameter buffer is full.
6
High indicates that the command
buffer is full.
7
High indicates a command busy
condition.
0388
8273 write-only command register.
0389
8273 parameter/result.
038A
8273 transmit interrupt status.
038B
8273 receive interrupt status.
038C
8273 data.
038D
Not used.
038F
I
I
NOTE
Addresses 0390H through 039FH are not used.
2241092-0001
B-27
TI Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table B-19
Address
(Hex)
Bisynchronous 1
Bit
03AO
Description
8255A-5 port A for bisynchronous
control:
o
Low indicates an interface ring
indicator .Q!!. condition.
1
Low indicates an interface data
carrier detect on condition.
2
An oscillating condition indicates
the transmit clock is active.
3
Low indicates an interface clearto-send on condition.
4
An oscillating condition indicates
that the receive clock is active.
5
High indicates an active transmit
ready.
6
High indicates an active timer 2
output.
7
High indicates an active timer 1
output.
03A1
8255A-5 port B for bisynchronous
control:
o
Low enables the modem interface
data signal rate selector.
1
Low enables the modem interface
select standby.
2
Low enables the test function.
3
Not used.
4
High resets the 8251A.
5
High enables gate timer 2.
B-28
2241092-0001
BUSINESS-PRO Hardware Reference
Table B-19
Address
(Hex)
TI Mode I/O Maps
Bisynchronous 1 (Continued)
Description
Bit
03Al (Continued)
6
High enables gate timer 1.
7
High gates timers 1 and 2 to
level 4 interrupt.
8255A-5 port C for bisynchronous
control:
03A2
o
High enables gating of the
internal clock (output).
1
High enables gating of the
external clock (output).
2
High enables the electronic
wrap (output).
3
Low enables timers 1 and 2,
interrupt 6, and receive
interrupt 3.
4
An oscillating condition
indicates receive data
(input) .
5
An oscillating condition
indicates timer 0 output
(input).
6
Low indicates test active
(input).
7
Low enables bisynchronous
control.
03A3
8255 mode set register.
03A4
Counter
03A5
Counter 1.
03A6
Counter 2.
2241092-0001
B-29
o.
TI Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table B-19
Address
(Hex)
Bisynchronous 1 (Continued)
Bit
03A7
Description
8253-5 control word (mode
register) :
o
Binary or BCD (binary coded
decimal) counting
1
Mode.
I
I
3
4
Read/load.
5
Read/load.
6
Select counter.
7
Select counter.
03A8
Data select.
03A9
Mode instruction format for BSC:
o
Not used (always 0).
1
Not used (alwa'ys 0).
2
Character length bit.
3
Character length bit.
4
High enables parity.
5
High=even parity.
6
High indicates that SYNDET is
an input.
7
Low=double synchronization
character.
03A9
Command/instruction format for
bisynchronous control:
o
Transmit enable.
1
Data terminal ready.
B-30
2241092-0001
TI Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table B-19
Address
(Hex)
Bisynchronous 1 (Continued)
Description
Bit
03A9 (Continued)
2
Receive enable.
3
Send break character.
4
Error reset.
5
Request-to-send.
6
Internal reset.
7
Enter hunt mode.
Not usable.
03AA
I
I
03AF
Table B-20
Address
(Hex)
Monochrome Display and Printer
. Description
Bit
03BO
Not used
I
I
03B3
03B4
6845 index register
03B5
6845 data register
03B6
Not used
03B7
Not used
03B8
CRT control port 1:
2241092-0001
0
High resolution mode (active high)
1
Not used
2
Not used
B-31
TI Mode I/O Maps
Table B-20
Address
(Hex)
BUSINESS-PRO Hardware Reference
Monochrome Display and Printer (Continued)
Bit
Description
03B8 (Continued)
3
Video enable (active high)
4
Not used
5
Enable blink (active high)
6
Not used
7
Not used
03B9
Reserved
03BA
CRT status port:
o
Horizontal (active high)
1
Green dot data
2
Blue dot data
3
Black/white video
(red dot data)
4
Not used
I
I
7
03BB
Reserved
03BC
Parallel data port
03BD
Printer status port
03BE
Printer control port
03BF
Not used
NOTE
Addresses 03COH through 03CFH are reserved.
B-32
2241092-0001
BUSINESS-PRO Hardware Reference
Table B-21
Address
(Hex)
TI Mode I/O Maps
Color/Graphics Monitor Adapter
Bit
Description
03DO
6845 registers.
03D1
6845 registers.
03D2
Not usable.
03D3
Not usable.
03D4
6845 index register.
03D5
6845 data register.
03D6
Not usable.
03D7
Not usable.
03D8
Mode select register:
o
80x25 alphanumeric mode.
1
Graphics select.
2
Black/white select.
3
Enable video signal.
4
High-resolution (640x200)
black/white mode.
5
Changed background intensity
to blink bit.
6
Not used.
7
Not used.
03D9
~olor
o
I
3
2241092-0001
select register:
These bits select the screen
border color in the 40x25
alphanumeric mode and the
screen background color (CO
and C1) in the mediumresolution (320x200) co1or/
graphics mode.
B-33
TI Mode I/O Maps
Table B-21
Address
(Hex)
BUSINESS-PRO Hardware Reference
Color/Graphics Monitor Adapter (Continued)
Bit
Description
03D9 (Continued)
4
When high, this bit selects an
alternate, intensified color set.
For the alphanumeric mode, this
bit selects the background colors.
5
This bit is used only in the
medium-resolution co1or/
graphics mode to select the
active screen color set.
6
Not usable.
7
Not usable.
03DA
Status register:
0
Display enable.
1
Light-pen trigger set.
2
Light-pen switch made.
3
Vertical syncnronization.
4
Not used.
7
I
I
03DB
Clear light pen latch.
03DC
Preset light pen latch.
03DD
Not usable.
I
I
03DF
NOTE
Addresses 03EOH through 03EFH are not used.
B-34
2241092-0001
BUSINESS-PRO Hardware Reference
Table B-22
Address
(Hex)
TI Mode I/O Maps
Floppy Disk Controller
Bit
Description
03FO
Not usable
03Fl
Not usable
03F2
Digital ouput register:
o
Drive select (low bit)
1
Drive select (high bit)
2
Function reset
3
Enable interrupts and DMA
4
Enable drive A motor
5
Enable drive B motor
6
Enable drive C motor
7
Enable drive D motor
03F3
Not usable
03F4
Status register:
2241092-0001
o
Drive A busy/seeking
1
Drive B busy/seeking
2
Drive C busy/seeking
3
Drive D busy/seeking
4
Disk busy command in
progress
5
NonDMA mode
6
Data transfer direction
{high-floppy disk to host)
7
Master-data-register
ready request
B-35
TI Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table B-22
Floppy Disk Controller (Continued)
.-----------------------------------------~----------- ------------
Address
(Hex)
Description
Bit
03F5
Floppy disk data
03F6
Fixed disk register:
0
Reserved
1
Enables interrupt
2
Hard disk reset
3
Head select 3
03F7
Diagnostic register:
0
Drive select 0 status
1
Drive select 1 status
2
Head select 0 status
3
Head select 1 status
4
Head select 2 status
5
Head select 3 or reduced
write current status
6
Write gate
7
Disk change
03F7
Floppy disk register:
0
Mode select (low bit)
1
Mode select (high bit)
2
I
Not used
I
7
B-36
2241092-0001
BUSINESS-PRO Hardware Reference
Table B-23
Address
(Hex)
TI Mode I/O Maps
Serial Port 1
Bit
Description
03F8
Transmit or receive buffer, or
least-significant byte of the
divisor latch.
03F9
Most-significant byte of the
divisor latch or interrupt enable
register. The following bit
definitions apply to the interrupt
enable register:
o
Enable data-available interrupt.
1
Enable transmit holding-register
empty interrupt.
2
Enable receive line status
interrupt.
3
Enable modem status interrupt.
4
Always set to logical
7
I
I
03FA
Interrupt identification register:
o
Interrupt is pending indicator.
1
2
These bits identify the
highest-priority pending
interrupt.
3
Always set to logical
I
03FB
o.
I
7
2241092-0001
o.
Line control register:
o.
o
Word-length-select bit
1
Word-length-select bit 1.
2
Number of stop bits.
3
Parity enable.
B-37
TI Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table B-23
Address
(Hex)
Serial Port 1 (Continued)
Bit
Description
03FB (Continued)
4
Even parity select.
5
Stuck parity.
6
Set break.
7
Divisor-latch-access bit.
03FC
Modem control register:
o
Data terminal ready.
1
Request-to-send.
2
Output 1.
3
Output 2.
4
Loop.
5
Always set to logical
I
I .
7
03FD
o.
Line status register.
o
Receive data-ready indicator.
1
Overrun error indicator.
2
Parity error indicator.
3
Framing error indicator.
4
Break interrupt indicator.
5
Transmitter holding register
empty.
6
Transmitter shift register empty.
7
Always set to logical
B-38
o.
2241092-0001
BUSINESS-PRO Hardware Reference
Table B-23
Address
(Hex)
TI Mode I/O Maps
Serial Port 1 (Continued)
Bit
03FE
Description
Modem status register:
o
Delta clear-to-send.
1
Delta data-set ready.
2
Trailing-edge ring indicator.
3
Delta receive line signal detect.
4
Clear-to-send.
5
Data-set ready.
6
Ring indicator.
7
Receive line signal detect.
03FF
Reserved.
0400
Duplicate.
7FFF
I
I
8000
I
NonvolatilOe RAM.
87FF
I
88FF
Duplicate.
FFFF
I
I
2241092-0001
B-39
PC-AT Mode I/O Maps
BUSINESS-PRO Hardware Reference
Appendix C
PC-AT Mode I/O Maps
The tables in this appendix provide detailed I/O maps for the
BUSINESS-PRO
computer's
IBM
Personal Computer AT (PC-AT)
compatible mode.
Table C-l
DMA Controller 1
Address
(Hex)
Description
0000
Channel 0 base and current address
0001
Channel 0 base and current word count
0002
Channel 1 base and current address
0003
Channel 1 base and current word count
0004
Channel 2 base and current address
0005
Channel 2 base and current word count
0006
Channel 3 base and current address
0007
Channel 3 base and current
0008
Read status, write command register
0009
Write request register
OOOA
write single mask register bit
OOOB
Write mode register
OOOC
Clear byte pointer flip-flop
OOOD
Read temporary register;
~ord
write master clear
OOOE
Clear mask register
OOOF
Write all mask register bits
2241092-0001
C-l
count
PC-AT Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table C-2
Address
(Hex)
Bit
Power-Up
State
0010
I
0013
I
o
Low
Low=PC-AT mode, high=TI mode.
1
Low
High=TI compatible video.
Low=PC-AT compatible video.
2
Low
When high, this bit allows software
to force a parity error by reading a
memory location in the 640-ki1obyte
address range that has previously been
loaded with OOH, 55H, AAH, or FFH.
3
Read-only high byte parity error.
4
Read-only low byte parity error.
Write-only PC-AT video select bit (LSB).
5
Read-only RAM bank parity error code
bit O. Write-only PC-AT video select
bit 1.
6
Read-only RAM bank parity error code
bit 1. Write-only PC-AT video select
bit 2~
7
Read-only RAM bank parity error code
bit 2. Write-only PC-AT video select
bit (MSB) .
0
Low
LED 1 (low=on, high=off) .
1
Low
LED 2 (low=on, high=off) .
2
Low
LED 3 (low=on, high=off) .
3
I
7
0014
I
001F
Description
Not usable.
0011
0012
Mode Select and Timer
Not used.
I
Not usable.
I
C-2
2241092-0001
BUSINESS-PRO Hardware Reference
Table C-3
PC-AT Mode I/O Maps
Master Interrupt Controller
Address
(Hex)
Description
0020
8259 interrupt
0021
8259 interrupt mask register
0022
Not usable
003F
I
I
Table C-4
8254-2 Timer
Address
(Hex)
Description
0040
8254 timer counter 0
0041
8254 timer counter 1
0042
8254 timer counter 2
0043
8254 timer control register
0044
Not usable
005F
I
I
2241092-0001
C-3
PC-AT Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table C-5
Address
(Hex)
0060
Bit
Power-Up
State
Description
Keyboard data register.
0
I
I
7
0061
8042 Keyboard
0
Low
Gate 2 input to 8254-2 timer.
1
Low
Timer 2 output enable (active high).
2
High
Parity error enable (active low).
3
High
Expansion bus NMI enable (active low).
4
Refresh bit.
5
Timer 2 output.
6
Expansion bus NMI.
7
Parity error.
0062
Not usable.
0063
Not usable.
0064
Keyboard control register read-only
status port:
o
Output buffer full. High indicates
data is available for reading.
1
Input buffer full. High indicates data
has been written into the buffer but
has not yet been read by the controller.
2
Low
System flag. This bit is defined by the
value written into the command byte.
3
Command/data. High indicates data has
been written to address 64H (command).
Low indicates data has been written
to address 60H (data).
4
Inhibit switch. Low indicates all
keyboard functions are inhibited.
C-4
2241092-0001
PC-AT Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table C-5
Address
(Hex)
Bit
8042 Keyboard (Continued)
Power-Up
State
Description
0064 (Continued)
5
Transmit time-out. High indicates that a
transmission started by the keyboard
controller was not properly completed.
6
Receive time-out. High indicates that a
transmission started by the keyboard '
controller was not properly completed.
7
Parity error. High indicates a parity
error.
0064
Write-only command port. System software
can use this port to reset the MPU.
Refer to Section 2 of this manual for
command definitions.
0065
Not usable.
I
I
0067
0068
o
Low
Low enables a one-wait-state memory
cycle. High enables a zero-wait-state
memory cycle.
1
Low
Low enables single refreshes. High
enables burst refreshes.
2
Low
Nonvolatile RAM enable (high disables
2 kilobytes of the nonvolatile RAM).
3
Low
Low enables expansion bus memory.
4
Low
Bank select O.
5
Low
Bank select 1.
6
Low
Bank select 2.
7
Low
High allows incoming data from the
main logic board parallel port.
0069
I
006F
2241092-0001
Not usable.
I
C-5
PC-AT Mode I/O Maps
Table C-6
Address
(Hex)
0070
Bit
BUSINESS-PRO Hardware Reference
Real-Time Clock and NMI Mask
Power-Up
State
Description
0
Nonvolatile RAM address port
5
I
I
6
7
Not usable
High
NMI enabled (active low)
0071
Nonvolatile RAM data port
0072
Not usable
007F
I
I
C-6
2241092-0001
BUSINESS-PRO Hardware Reference
Table C-7
PC-AT Mode I/O Maps
DMA Page Register
Address
(Hex)
Description
0080
Diagnostic-checkpoint port. This
port is a read/write port in the
LS612 page register.
0081
DMA channel 2 (floppy drive).
0082
DMA channel 3 (tape drive).
0083
DMA channel 1 (SDLC) .
0084
Not used.
I
0086
I
0087
DMA channel O.
0088
Not used.
0089
DMA channel 6.
008A
DMA channel 7 .
008B
DMA channel 5.
008C
Not used.
008E
I
I
008F
Refresh.
0090
Not usable.
I
009F
2241092-0001
I
C-7
PC-AT Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table C-8
Slave Interrupt Controller
Address
(Hex)
Description
OOAO
8259 interrupt
OOAI
8259 interrupt mask register
00A2
Not usable
OOBF
I
I
Table C-9
Address
(Hex)
DMA Controller 2
Description
OOCO
Channel 0 base and current address
00C2
Channel 0 base and current word count
00C4
Channel 1 base and current address
00C6
Channel 1 base and current word count
00C8
Channel 2 base and current address
OOCA
Channel 2 base and current word count
OOCC
Channel 3 base and current address
OOCE
Channel 3 base and current word count
OODO
Read status; write command register
00D2
write request register
00D4
Write single mask register bit
00D6
Write mode register
00D8
Clear byte pointer flip-flop
OODA
Read temporary register; write master clear
OODC
Clear mask register
OODE
Write all mask register bits
C-8
2241092-0001
PC-AT Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table C-IO
Communication Ports
Address
(Hex)
OOEO
I
Description
Communication port 1 interrupt acknowledge
00E3
I
00E4
Communication port 1 channel B commanq
OOES
Communication port 1 channel B data
00E6
Communication port 1 channel A command
00E7
Communication port 1 channel A data
00E8
Communication port 2 interrupt acknowledge
I
OOEB
I
OOEC
Communication port 2 channel B command
OOED
Communication port 2 channel B data
OOEE
Communication port 2 channel A command
OOEF
Communication port 2 channel A data
--------------------------------------~------------~------------~
2241092-0001
C-9
PC-AT Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table C-ll
Address
(Hex)
OOFO
I
7
OOFl
Description
Bit
o
o
I
Coprocessor
Clear-coprocessor busy. writing Os to this
port clears the latched busy signal.
(Activation of the coprocessor error signal
during a coprocessor busy condition latches
the busy signal.)
Coprocessor reset. Writing Os to this port
resets the coprocessor.
7
00F2
I
Not usable.
00F7
I
OOFS
Reserved.
OOFF
I
I
NOTE
Addresses OlOOH through OllFH are not used.
Addresses 0120H through 016FH are reserved.
C-IO
2241092-0001
PC-AT Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table C-12
Address
(Hex)
Alternate Fixed Disk
Description
Bit
0170
Data register
0171
Error register for read accesses;
write precompensation for write
accesses
0
Data address mark not found
1
Track 000 error
2
Aborted command
3
Not used
4
ID not found
5
Not used
6
Data ECC error
7
Bad block detected
0172
Sector count
0173
Sector number
0174
Cylinder low
0175
Cylinder high
0176
Size/drive/head
2241092-0001
0
Head select 0
1
Head select 1
2
Head select 2
3
Head select 3
4
Drive 1=0; Drive 2=1
5
Sector size (low bit)
C-ll
PC-AT Mode I/O Maps
Table C-12
Address
(Hex)
BUSINESS-PRO Hardware Reference
Alternate Fixed Disk (Continued)
Description
Bit
0176 (Continued)
6
Sector size (high bit)
7
High=ECC to be enabled
Status register for read accesses;
command register for write accesses
0177
0
Error
1
Index pulse from selected drive
2
Corrected data
3
Data request
4
Seek complete from the drive
5
write fault from the drive
6
Drive ready from the drive
7
Controller busy
NOTE
Addresses 0178H through OlEFH are not used.
C-12
2241092-0001
BUSINESS-PRO Hardware Reference
Table C-13
Address
(Hex)
PC-AT Mode I/O Maps
Fixed Disk
Bit
Description
OlFO
Data register
OlFl
Error register for read accesses; write
precompensation for write accesses.
o
Data address mark not found
1
Track 000 error
2
Aborted command
3
Not used
4
ID not found
5
Not used
6
Data ECC error
7
Bad block detected
01F2
Sector count
01F3
Sector number
01F4
Cylinder low
01F5
Cylinder high
01F6
Size/drive/head
2241092-0001
o
Head select 0
1
Head select 1
2
Head select 2
3
Head select 3
4
Drive 1=0; Drive 2=1
5
Sector size (low bit)
C-13
PC-AT Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table C-13
Address
(Hex)
Fixed Disk (Continued)
Bit
Description
01F6 (Continued)
6
Sector size (high bit)
7
High=ECC to be enabled
01F7
Status register for read accesses;
command register for write accesses
0
Error
1
Index pulse from selected drive
2
Corrected data
3
Data request
4
Seek complete from the drive
5
write fault from the drive
6
Drive ready from the drive
7
Controller busy
NOTE
Addresses 01F8H through OlFFH are not used.
Addresses 0200H through 0207H. are reserved
for game I/O. Addresses 0208H through 02F7H
are not used.
C-14
2241092-0001
BUSINESS-PRO Hardware Reference
Table C-14
Address
(Hex)
PC-AT Mode I/O Maps
Parallel Printer Port 2
Bit
Description
0278
Data latch.
0279
Printer status:
0
I
2
Not used.
I
3
Low indicates an error condition.
4
Printer selected (active high).
5
End of paper (active high).
6
Printer acknowledge (active low).
7
Printer busy (active low).
027A
Printer controls:
0
Strobe (active high).
1
Line feed.
2
Initialize printer (active low).
3
Printer select (active high).
4
Interrupt enable (active high).
5*
Low indicates 128 kilobytes of
memory on the main logic board are
enabled. (Read-only bit on the main
logic board parallel port.)
6*
High indicates all NMIs are being
masked out. (Read-only bit on the
main logic board parallel port.)
NOTE:
*Bits 5 through 7 are not used on PC-AT compatible
parallel port option boards.
2241092-0001
C-15
PC-AT Mode I/O Maps
Table C-l4
Address
(Hex)
BUSINESS-PRO Hardware Reference
Parallel Printer Port 2 (Continued)
Description
Bit
027A (Continued)
7*
High indicates the serial port on
the main logic board is located at
addresses 03F8H through 03FFH.
(Read-only bit on the main logic
board parallel port.)
027B
Not usable.
027C
Data latch (duplicate).
027D
Printer status (duplicate):
0
Not used.
2
I
I
3
Low indicates an error condition.
4
Printer selected (active high).
5
End of paper (active high).
6
Printer acknowledge (active low).
7
Printer busy (active low).
027E
Printer controls (duplicate):
0
Strobe (active high).
1
Line feed.
2
Initialize printer (active low).
3
Printer select (active high).
4
Interrupt enable (active high).
NOTE:
*Bits 5 through 7 are not used on PC-AT compatible
parallel port option boards.
C-16
2241092-0001
BUSINESS-PRO Hardware Reference
Table C-14
Address
(Hex)
PC-AT Mode I/O Maps
Parallel Printer Port 2 (Continued)
Bit
Description
027E (Continued)
027F
5*
Low indicates 128 kilobytes of
memory on the main logic board are
enabled. (Read-only bit on the main
logic board parallel port.)
6*
High indicates all NMIs are being
masked out. (Read-only bit on the
main logic board parallel port.)
7*
High indicates the serial port on
the main logic board is located at
addresses 03F8H through 03FFH.
(Read-only bit on the main logic
board parallel port.)
Not usable.
NOTE:
*Bits 5 through 7 are not used on PC-AT compatible
parallel port option boards.
NOTE
Addresses 0280H through 02F7H are not used.
2241092-0001
C-17
PC-AT Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table C-15
Address
(Hex)
Serial Port 2
Bit
Description
02F8
Transmit or receive buffer, or leastsignificant byte of the divisor latch.
02F9
Most-significant byte of the divisor
latch or interrupt enable register.
The following bit definitions apply
to the interrupt enable register:
0
Enable data-available interrupt.
1
Enable transmit holding-register
empty interrupt.
2
Enable receive line status interrupt.
3
Enable modem status interrupt.
4
Always set to logical O.
I
I
7
02FA
Interrupt identification register:
0
Interrupt is pending indicator.
1
2
These bits identify the
highest-priority pending interrupt.
3
Always set to logical O.
I
I
7
02FB
Line control register:
o.
0
Word-length-select bit
1
Word-length-select bit 1.
2
Number of stop bits.
3
Parity enable.
4
Even parity select.
C-18
2241092-0001
BUSINESS-PRO Hardware Reference
Table C-15
Address
(Hex)
PC-AT Mode I/O Maps
Serial Port 2 (Continued)
Bit
Description
02FB (Continued)
5
Stuck parity.
6
Set break.
7
Divisor-latch-access bit.
02FC
Modem control register:
0
Data terminal ready.
1
Request-to-send.
2
Output 1.
3
Output 2.
4
Loop.
5
Always set to logical O.
I
I
7
02FD
2241092-0001
Line status register:
0
Receive data-ready indicator.
1
Overrun error indicator.
2
Parity error indicator.
3
Framing error indicator.
4
Break interrupt indicator.
5
Transmitter holding register empty.
6
Transmitter shift register empty.
7
Always set to logical
C-19
o.
PC-AT Mode I/O Maps
Table C-15
Address
(Hex)
Serial Port 2 (Continued)
Bit
02FE
02FF
BUSINESS-PRO Hardware Reference
Description
Modem status register:
o
Delta clear-to-send.
1
Delta data-set ready.
2
Trailing-edge ring indicator.
3
Delta receive line signal detect.
4
Clear-to-send.
5
Data-set ready.
6
Ring indicator.
7
Receive line signal detect.
Reserved.
NOTE
Addresses 0300H through 031FH are reserved
for the prototype board.
Addresses 0320H
through 035FH are not used. Addresses 0360H
through 036FH are reserved.
C-20
2241092-0001
BUSINESS-PRO Hardware Reference
Table C-16
Address
(Hex)
PC-AT Mode I/O Maps
Alternate Floppy Disk Controller
Description
Bit
0370
Not usable
0371
Not usable
0372
Digital output register:
o
Drive select (low bit)
1
Drive select (high bit)
2
Function reset
3
Enable interrupts and DMA
4
Enable drive A motor
5
Enable drive B motor
6
Enable drive C motor
7
Enable drive D motor
0373
Not usable
0374
Status register:
2241092-0001
o
Drive A busy/seeking
1
Drive B busy/seeking
2
Drive C busy/seeking
3
Drive D busy/seeking
4
Diskette-busy command in progress
5
NonDMA mode
6
Data transfer direction
(high=f1oppy disk to host)
7
Master-data-register ready request
C-21
PC-AT Mode I/O Maps
Table C-16
Address
(Hex)
BUSINESS-PRO Hardware Reference
Alternate Floppy Disk Controller (Continued)
Bit
Description
0375
Floppy disk data register
0376
Fixed disk register:
0
Reserved
1
Enables interrupt
2
Hard disk reset
3
Head select 3
0377
Diagnostic register:
0
Drive select 0 status
1
Drive select 1 status
2
Head select 0 status
3
Head select 1 status
4
Head select 2 status
5
Head select 3 or reduced
write current status
6
Write gate status
7
Disk change
0377
Floppy disk register:
0
Mode select (low bit)
1
Mode select (high bit)
2
Not used
I
7
I
C-22
2241092-0001
PC-AT Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table C-17
Address
(Hex)
Parallel Printer Port 1
Bit
Description
0378
Data latch.
0379
Printer status:
0
Not used.
I
I
2
3
Low indicates an error condition.
4
Printer selected (active high).
5
End of paper (active high).
6
Printer acknowledge (active low).
7
Printer busy (active low).
037A
Printer controls:
0
Strobe (active high).
1
Line feed.
2
Initialize printer (active low).
3
Printer select (active high).
4
Interrupt enable (active high).
5*
Low indicates 128 kilobytes of
memory on the main logic board are
enabled. (Read-only bit on the main
logic board parallel port.)
6*
High indicates all NMIs are being
masked out. (Read-only bit on the
main logic board parallel port.)
NOTE:
*Bits 5 through 7 are not used on PC-AT compatible
parallel port option boards.
2241092-0001
C-23
PC-AT Mode I/O Maps
Table C-17
Address
(Hex)
BUSINESS-PRO Hardware Reference
Parallel Printer Port 1 (Continued)
Bit
Description
037A (Continued)
7*
High indicates the serial port on
the main logic board is located at
addresses 03F8H through 03FFH.
(Read-only bit on the main logic
board parallel port.)
037B
Not usable.
037C
Data latch (duplicate).
037D
Printer status (duplicate):
0
Not used.
2
I
I
3
Low indicates an error condition.
4
Printer selected (active high).
5
End of paper (active high).
6
Printer acknowledge (active low).
7
Printer busy (active low).
037E
Printer controls (duplicate):
0
Strobe (active high).
1
Line feed.
2
Initialize printer (active low).
3
Printer select (active high).
4
Enable interrupt (active high).
NOTE:
*Bits 5 through 7 are not used on PC-AT compatible
parallel port option boards.
C-24
2241092-0001
BUSINESS-PRO Hardware Reference
Table C-17
Address
(Hex)
PC-AT Mode I/O Maps
Parallel Printer Port 1 (Continued)
Description
Bit
037E (Continued)
037F
5*
Low indicates 128 kilobytes of
memory on the main logic board are
enabled. (Read-only bit on the main
logic board parallel port.)
6*
High indicates all NMls are being
masked out. (Read-only bit on the
main logic board parallel port.)
7*
High indicates the serial port on
the main logic board is located at
addresses 03F8H through 03FFH.
(Read-only bit on the main logic
board parallel port.)
Not usable.
NOTE:
*Bits 5 through 7 are not used on PC-AT compatible
parallel port option boards.
2241092-0001
C-25
PC-AT Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table C-18
Address
Bisynchronous 2
Bit
0380
Description
8255A-5 port A:
o
Low indicates an interface ring
indicator on condition.
1
Low indicates an interface data
carrier detect on condition.
2
An oscillating condition indicates
transmit clock is active.
3
Low indicates an interface
clear-to-send on condition.
4
An oscillating condition indicates
the receive clock is active.
5
High indicates a modem status
change.
6
High indicates an active timer 2
output.
7
High indicates an active timer 1
output.
0381
8255A-5 port B:
o
Low enables the modem interface
data signal rate select.
1
Low enables the modem interface
select standby.
2
Low enables the test function.
3
High resets the modem status
changed logic.
4
High resets the 8273.
5
High enables gate timer 2.
6
High enables gate timer 1.
7
Low enables level 4 interrupt.
C-26
2241092-0001
PC-AT Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table C-18
Address
(Hex)
Bisynchronous 2 (Continued)
Bit
0382
Description
8255A-5 port C:
o
High enables gating of the internal
clock (output).
1
High enables gating of the external
clock (output).
2
High enables the electronic wrap
(output) .
3
Low enables gating of interrupts
3 and 4 (output).
4
An oscillating condition indicates
receive data (input).
5
An oscillating condition indicates
timer 0 output (input).
6
Low indicates test active (input).
7
Not used.
0383
8255 mode set register.
0384
8253 counter O.
0385
8253 counter 1.
0386
8253 counter 2.
0387
8253 mode register.
0388
8273 read-only status register:
2241092-0001
o
High indicates that the transmit
interrupt result is available.
1
High indicates that the receive
interrupt result is available.
2
High enables the transmit
interrupt.
C-27
PC-AT Mode I/O Maps
Table C-18
Address
(Hex)
BUSINESS-PRO Hardware Reference
Bisynchronous 2 (Continued)
Description
Bit
0388 (Continued)
3
High enables the receive interrupt.
4
High indicates that the command
result buffer is full.
5
High indicates that the command
parameter buffer is full.
6
High indicates that the command
buffer is full.
7
High indicates a command busy
condition.
0388
8273 write-only command register.
0389
8273 parameter/result.
038A
8273 transmit interrupt status.
038B
8273 receive interrupt status.
038C
8273 data.
038D
Not used.
038F
I
I
NOTE
Addresses 0390H through 039FH are not used.
C-28
2241092-0001
BUSINESS-PRO Hardware Reference
Table C-19
Address
(Hex)
Bisynchronous 1
Description
Bit
8255A-5 port A for bisynchronous
control:
03AO
o
Low indicates an interface ring
indicator on condition.
1
Low indicates an interface data
carrier detect on condition.
2
An oscillating condition indicates
the transmit clock is active.
3
Low indicates an interface clearto-send on condition.
4
An oscillating condition indicates
the receive clock is active.
5
High indicates an active transmit
ready.
6
High indicates an active timer 2
output.
7
High indicates an active timer 1
output.
03Al
2241092-0001
PC-AT Mode I/O Maps
8255A-5 port B for bisynchronous
control:
o
Low enables the modem interface
data signal rate selector.
1
Low enables the modem interface
select standby.
2
Low enables the test function.
3
Not used.
4
High resets the 8251A.
5
High enables gate timer 2.
6
High enables gate timer 1.
C-29
PC-AT Mode I/O Maps
Table C-19
Address
BUSINESS-PRO Hardware Reference
Bisynchronous 1 (Continued)
Bit
Description
03Al (Continued)
7
High gates timers 1 and 2 to
level 4 interrupt.
8255A-5 port C for bisynchronous
control:
03A2
o
High enables gating of internal
clock (output).
1
High enables gating of external
clock (output).
2
High enables the electronic
wrap (output).
3
Low enables timers 1 and 2,
interrupt 6, and receive
interrupt 3.
4
An oscillating condition indicates
receive data (input).
5
An oscillating condition indicates
timer 0 output "(input).
6
Low indicates test active (input).
7
Low enables bisynchronous control.
03A3
8255 mode initialization.
03A4
Counter
03A5
Counter 1.
03A6
Counter 2.
03A7
8253~5 control word (mode
register) :
o.
0
Binary or BCD (binary coded decimal)
counting.
1
Mode.
3
I
I
C-30
2241092-0001
BUSINESS-PRO Hardware Reference
Table C-19
Address
PC-AT Mode I/O Maps
Bisynchronous 1 (Continued)
Bit
Description
03A7 (Continued)
4
Read/load.
5
Read/load.
6
Select counter.
7
Select counter.
03AB
Data select.
03A9
Mode instruction format for BSC:
0
Not used (always 0).
1
Not used (always 0).
2
Character length bit.
3
Character length bit.
4
High enables parity.
5
High=even parity.
6
High indicates that SYNDET is
an input.
7
Low=double synchronization character.
03A9
2241092-0001
Command/instruction format for
bisynchronous control:
0
Transmit enable.
1
Data terminal ready.
2
Receive enable.
3
Send break character.
4
Error reset.
5
Request-to-send.
6
Internal reset.
C-31
PC-AT Mode I/O Maps
Table C-19
Address
(Hex)
BUSINESS-PRO Hardware Reference
Bisynchronous 1 (Continued)
Description
Bit
03A9 (Continued)
Enter hunt mode.
7
03AA
Not usable.
I
I
03AF
Table C-20
Address
(Hex)
Monochrome Display and Printer
Bit
Description
03BO
Not used
I
I
03B3
03B4
6845 index register
03B5
6845 data register
03B6
Not used
03B7
Not used
03B8
CRT control port 1:
o
High resolution mode (active
high)
1
Not used
2
Not used
3
Video enable (active high)
4
Not used
5
Enable blink (active high)
6
Not used
C-32
2241092-0001
PC-AT Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table C-20
Address
(Hex)
Monochrome Display and Printer (Continued)
Bit
Description
03B8 (Continued)
Not used
7
03B9
Reserved
03BA
CRT status port:
o
Horizontal (active high)
1
Green dot data
2
Blue dot data
3
Black/white video
(red dot data)
4
Not used
I
I
7
03BB
Reserved
03BC
Parallel data port
03BD
Printer status port
03BE
Printer control port
03BF
Not used
NOTE
Addresses 03COH through 03CFH are reserved.
2241092-0001
C-33
PC-AT Mode I/O Maps
Table C-2l
Address
(Hex)
BUSINESS-PRO Hardware Reference
Color/Graphics Monitor Adapter
Bit
Description
03DO
6845 registers.
03Dl
6845 registers.
03D2
Not usable.
03D3
Not usable.
03D4
6845 index register.
03D5
6845 data register.
03D6
Not usable.
03D7
Not usable.
03D8
Mode select register:
0
80x25 alphanumeric mode.
1
Graphics select.
2
Black/white select.
3
Enable video signal.
4
High-resolution (640x200)
black/white mode.
5
Changed background intensity
to blink bit.
6
Not used.
7
Not used.
03D9
Color select register:
0
I
3
These bits select the screen
border color in the 40x25
alphanumeric mode and the
screen background color (CO and
Cl) in the medium-resolution
(320x200) color/graphics mode.
C-34
2241092-0001
PC-AT Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table C-21
Address
(Hex)
Color/Graphics Monitor Adapter (Continued)
Description
Bit
03D9 (Continued)
4
When high, this bit selects an
alternate, intensified color
set. For the alphanumeric
mode, this bit selects the
background colors.
5
This bit is used only in the
medium-resolution color/
graphics mode to select the
active screen color set.
6
Not usable.
7
Not usable.
03DA
Status register:
0
Display enable.
1
Light pen trigger set.
2
Light pen switch made.
3
vertical synchronization.
4
Not used.
7
I
I
03DB
Clear light pen latch.
03DC
Preset light pen latch.
03DD
Not usable.
I
I
03DF
NOTE
Addresses 03EOH through 03EFH are not used.
2241092-0001
C-35
PC-AT Mode I/O Maps
Table C-22
Address
(Hex)
BUSINESS-PRO Hardware Reference
Floppy Disk Controller
Description
Bit
03FO
Not usable
03Fl
Not usable
03F2
Digital ouput register:
o
Drive select (low bit)
1
Drive select (high bit)
2
Function reset
3
Enable interrupts and DMA
4
Enaple drive A motor
5
Enable drive B motor
6
Enable drive C motor
7
Enable drive D motor
03F3
Not usable
03F4
Status register:
o
Drive A busy/seeking
1
Drive B busy/seeking
2
Drive C busy/seeking
3
Drive D busy/seeking
4
Diskette-busy command in
progress
5
NonDMA mode
6
Data transfer direction
(high=floppy disk to host)
7
Master-data-register
ready request
C-36
2241092-0001
BUSINESS-PRO Hardware Reference
Table C-22
Address
(Hex)
PC-AT Mode I/O Maps
Floppy Disk Controller (Continued)
Bit
Description
03F5
Floppy disk data
03F6
Fixed disk register:
o
Reserved
1
Enables interrupt
2
Hard disk reset
3
Head select 3
03F7
Diagnostic register:
o
Drive select 0 status
1
Drive select 1 status
2
Head select 0 status
3
Head select 1 status
4
Head select 2 status
5
Head select 3 or reduced
write current status
6
Write gate status
7
Disk change
03F7
Floppy disk register:
o
Mode select (low bit)
1
Mode select (high bit)
2
I
7
2241092-0001
Not used
I
C-37
PC-AT Mode I/O Maps
BUSINESS-PRO Hardware Reference
Table C-23
Address
(Hex)
Serial Port 1
Description
Bit
03F8
Transmit or receive buffer or leastsignificant byte of the divisor
latch.
03F9
Most-significant byte of the divisor
latch or interrupt enable register.
The following bit definitions apply
to the interrupt enable register:
o
Enable data-available interrupt.
1
Enable transmit holding-register
empty interrupt.
2
Enable receive line status
interrupt.
3
Enable modem status interrupt.
4
Always set to logical O.
I
I
7
03FA
Interrupt identification register:
o
Interrupt is pending indicator.
1
2
These bits identify the
highest-priority pending interrupt.
3
Always set to logical O.
I
I
7
03FB
Line control register:
o
Word-length-select bit O.
1
Word-length-select bit 1.
2
Number of stop bits.
3
Parity enable.
4
Even parity select.
C-38
224l092~OOOl
BUSINESS-PRO Hardware Reference
Table C-23
Address
(Hex)
PC-AT Mode I/O Maps
Serial Port 1 (Continued)
Bit
Description
03FB (Continued)
5
Stuck parity.
6
Set break.
7
Divisor-latch-access bit.
03FC
Modem control register:
0
Data terminal ready.
1
Request-to-send.
2
Output 1.
3
Output 2.
4
Loop.
5
Always set to logical O.
I
I
7
03FD
2241092-0001
Line status ·register.
0
Receive data-ready indicator.
1
Overrun error indicator.
2
Parity error indicator.
3
Framing error indicator.
4
Break interrupt indicator.
5
Transmitter holding register empty.
6
Transmitter shift register empty.
7
Always set to logical O.
C-39
PC-AT Mode I/O Maps
Table C-23
Address
(Hex)
BUSINESS-PRO Hardware Reference
Serial Port 1 (Continued)
Description
Bit
Modem status register:.
03FE
o
Delta clear-to-send.
1
Delta data-set ready.
2
Trailing-edge ring indicator.
3
Delta receive line signal detect.
4
Clear-to-send.
5
Data-set ready.
6
Ring indicator.
7
Receive line signal detect.
03FF
Reserved.
0400
Duplicate.
7FFF
I
I
8000
I
Nonvolatile RAM.
87FF
I
88FF
Duplicate.
FFFF
I
I
C-40
2241092-0001
PAL Programming Information
BUSINESS-PRO Hardware Reference
Appendix D
PAL Programming Information
This appendix tabulates programming information for the various
programmable array logic (PAL) devices on the BUSINESS-PRO main
logic board. These devices respond to various clocks, control
signals, and address information to generate control signals for
memory, DMA, and I/O operations.
The following conventions apply to all tables in this appendix:
*
When the logical AND of terms from one row is ORed with
the logical AND of terms from another row, the output
goes low if the result is true.
*
Output signals are listed in the left hand column.
Some
of these signals are generated by a PAL device only for
its own internal use. These signals are indicated by an
asterisk (*).
*
The input variables and the device pins where they
appear are listed at the top of the columns.
Table D-l through Table D-12 list the functions of the main logic
board PAL devices.
2241092-0001
D-1
PAL Programming Information
Table D-l
BUSINESS-PRO Hardware Reference
Reset/Ready Control PAL U14
Logic Sheet 5
1 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19
6MHZREADY24MHZB
MSO
YR
RX-*
RES12MHZCOWS- I ARDY- I XR
I QO*
MSI
JRDY
Ql*
RESET
IDLE
I
I I
Ql*
QO*
C
C
C
o
C
C
C
o
o
o
C
XR
RESET
RX-*
READY-
C
I I I
o
o
o
1
1
o
o
o
1
1
o
o
o
o
1
1
o
o
o
o
1
I
I
1
C
o
C
C
o
001
001
C
C
C
C
C
C
C
C
C
I
I
I
o
o
o
0
o
o
o
1
o
I
I
1
1
1
1
0
1
1
1 1
1 0
011
1
o
1
o
o
1
o
o
o
o
o
1
010
001
0
o 0
o
1
1
D-2
2241092-0001
BUSINESS-PRO Hardware Reference
Table D-2
PAL Programming Information
Memory and IIO Control PAL U60
Logic Sheet 6
1 2 3
12MHZSTAT
4 5 6
GIA
I STOP
,URjO
Ql
Q2*
Q3
QO*
CEN-
C
C
C
C
C
C
C
I
7 8 9 13 14 15 16 17 19
6MHZ
Q3
QO*
CENI DATACON- Q2*
iWSi
1
1
0
1
1
1
1
0
1
I
jRDi-
I
fl
0
0
1
0
1
0
I i
0
1
0
1
1
1
0
1
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
C
C
C
C
C
C
C
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
C
C
C
C
C
C
0
C
C
C
C
C
C
C
C
0
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
1
o 0 1
110
110
0
0
0
1
1
1
0
1
0
C
C
C
2241092-0001
0
1
1
1
1
0
1
1
0
o
000
1
D-3
0
/IO
BUSINESS-PRO Hardware Reference
PAL Programming Information
Table D-2. Memory and I/O Control PAL U60 (Continued)
Logic Sheet 6
1 2 3 4 5 6 7 8 9 13 14 15 16 17 19
Q3
12MHZ6MHZ
QO*
GIA
CENSTAT I STOP I DATACON- Q2*
Ql
OWSBRDYMM/IO
TURBO
I
CONALE
I
I
I
I
I
I
I
C
o
C
C
C
o
1
1
1
1
MASKOWS C
I
I
0
1
1
1
I
1
1
Table D-3
I
I/O Decode Logic PAL U54
Logic Sheet 9
1
2
3
4
5
6
7
8
9
11
DMAICSTI/IBM
PDMA2
10INTRICS- I
PDMA4
PDMAI
PPICSPDMA3
PDMAO
I
I
I
I
I
I
I
o
o
1
1
o
o
o
1
PRTO-
o
1
o
o
o
o
o
o
PRT3-
1
o
1
o
o
o
o
1
1
1
1
o
o
PRT12-
o
o
o
1
o
o
1
o
o
53CS-
o
1
1
o
1
1
1
1
o
XDMAICS-
INTl-
o
0
o
o
o
o
42CS-
o
o
o
42C/D-
o
o
o
D-4
1
o
o
o
o
2241092-0001
BUSINESS-PRO Hardware Reference
Table D-4
PAL Programming Information
I/O Decode Logic PAL U55
Logic Sheet 9
123
456
7
8
IOWPPICSPDMA3
ADD
CS287PDMAO
OR iDMA4
I
o
o
I
f
1
1
o
I
PRT61-
o
o
o
o
PRT70-
o
1
o
o
PRT71-
o
o
1
1
1
1
o
PRT68-
o
o
o
o
1
1
o
o
o
DATA8DIR- -
RST287-
o
1
o
NPCS-
o
1
1
BUSYCLR-
o
1
o
2241092-0001
11
CSNVRAM
INTA-
I
o
o
o
o
o
o
o
o
1
9
1
1
o
1
1
o
o
D-5
o
BUSINESS-PRO Hardware Reference
PAL programming Information
Table D-5
I/O Decode Logic PAL U56
Logic Sheet 9
2
3
1
INTAXM/IO
4
5
6
7
8
9
11 13 14 15 16
1016CSNVRAM
MEMWDMAENI AENlI SIOWC- I PDMBHE- I Ql
, SYS 6 +
jEN2,
iEMR,
,DMAj
t
DIR245
0
0
1
1
1
0
0
0
1
1
1
1
o
ENDCYCDATAOI
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
o
1
o
o
0
1
0
1
o
o
o
o
o
o
o
o
o
o
o
o
1
1
1
1
o
1
1
1
DMAEN-
o
PDMBHE-
o
PDMAO
o
I
o
o
1
o
o
I
1
o
o
GATE245-
I
1
1
1
1
1
1
o
o
o
o
o
o
o
1
o
o
- NOTE 1
- NOTE 1
- NOTE 2
NOTES:
1. PDMBHE- is an output only when DMAEN- is low.
2. PDMAO is an output only when AEN2- is low.
D-6
2241092-0001
PAL Programming Information
BUSINESS-PRO Hardware Reference
Table D-6
Serial/Parallel Port Decode PAL U85
Logic Sheet 15
1 2 3 4 5 6 7 8 9 11 13 14 15 16 17 18
TI/IBM
PDMA9
PDMA6
PDMA3
PDMAO
PARS TAT
PJMP1 I PDMA8 I PDMA5 I PDMA2 I PARDATSJMP1
PDMA7
PDMA4
PDMA1
PARCNTL
I
PARDAT-
0
o
I
0
o
1
1
1
1
1
1
0
o
o
1
1
1
1
0
1
1
o
1
0
0
0 1 1
0 1 1
000
1
1
0
1
1
1
o
1
1
111 1
0 111
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
o
110
100
000
1
1
o
o o
1
1
1
o
o o o o o
1
1
1
0
1
SEREN-
I
1
1
0
1
PARCNTL
I
I
I
1
PARSTAT
I
I
1
0
I
o
o
0
0
0
I
I
o
o
0
0
0
1
o
o
o
1
1
1
1
1
0
0
1
1
I
I
I
o
PTREN-
o
2241092-0001
I
1
1
1
1
1
1
D-7
o
o
BUSINESS-PRO Hardware Reference
PAL Programming Information
CPU Data Bus Control PAL U92
Table D-7
Logic Sheet 12
1 2 3 4 5 6 7 8 9 12 13 15 16 17 18 19
YMDIR
G1AXLSAO
YMSO
CDIR
24MHZ
XPDMBHEDAK
12MHZ I MAO
J/M*
I
I
I
CDHMBHECDEN
6MHZ
CMAO
I
I
0
0
0
1
1
1
I
I
I
I
I
I
I
I
I
I
I
-------------------------------------------------------
CDH-
CDL-
C
C
C
C
C
C
C
C
0
0
0
0
1
1
C
C
C
C
C
C
C
C
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
1
0
0
0
0
1
1
0
1
0
-------------------------------------------------------
CDIR
C
C
C
C
C
0
0
0
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
1
0
0
0
0
-------------------------------------------------------
J/M*
C
C
C
C
C
C
0
0
0
0
1
-
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
1
0
0
0
0
1
1
-------------------------------------------------------
D-8
2241092-0001
PAL Programming Information
BUSINESS-PRO Hardware Reference
Table D-8
Refresh Arbiter PAL Ul0l
Logic Sheet 19
1 2 3 4 5 6 7 8 9 15 16 17 18 19
DRQ
CK2
RFB
XRFQ*
RSTAEN- I RFQQO*
LKFHHOLDA
Ql*
XDRQ*
LHLDA*
I
I
I I
Ql*
C
C
C
C
1
1
1
1
QO*
C
C
C
C
C
1
1
1
1
1
XDRQ*
DAK
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
I
I
I
o
LHLDA* C
XRFQ*
I
110
100
110 0
110 0
o
1
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
o
1
1
0
0
1
1
1
1
0
1
0
1
1
0
0
1
0
1
0
o
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
1
0
1
0
0
0
0
0
0
2241092-0001
D-9
0
1
1
1
0
PAL Programming Information
BUSINESS-PRO Hardware Reference
Table D-8. Refresh Arbiter PAL UI0l (Continued)
Logic Sheet 19
1 2 3 4 5 6 7 8 9 15 16 17 18 19
CK2
RFB
DRQ
XRFQ*
RSTAEN- I RFQQO*
LKHOLDA
FHQ1*
HLDA *
fDR?*
I
I
RAK-
C
C
HOLD
C
C
C
C
C
C
I I
1
1
0
I i
I
1
1
1
1
1
1
o
o
110
1 0 1
0
0
0
0
0
D-10
0
0
1
0
1
1
0
0
1
1
1
1
0
1
0
2241092-0001
PAL Programming Information
BUSINESS-PRO Hardware Reference
Table 0-9
Refresh Sequence Control PAL U102
Logic Sheet 19
1 2 3
24MHZB
RST-
4 5 6
SOFTRES
I MSI
iOCi0014*
C
001*
C
LRFQ-
C
C
C
I
7 8 9 13 14 15 16 17 18 19
OUTI/8
REFOET
ORAK-*
X2
I 540UTI LRFQ- I 0014* I
B
01 j
iAK,
iK-j
I
o
o
0
i
1
1
1
o
1
o
REFOET
C
o
C
C
C
1
0
C
C
1
1
1
1
o
o
o
o
1
1
o
C
C
C
I
o
C
GLOCK-
I
o
ORAK-*
LK-*
i
0
0
2241092-0001
0-11
1
1
1
BUSINESS-PRO Hardware Reference
PAL Programming Information
Dual-Mode Refresh Generator PAL U104
Table D-10
Logic Sheet 19
9 12 13 14 15 16 17 18 19
5
6 7
8
1
2 3 4
CK590
Xl
Q2*
RCO
24MHZB
SRES
QO*
PRESET
RFBUSY
12MHZ I WAIT- I DB
I
Q1*
IDLE
X2
6MHZ
jAKj
I
Q2*
Q1*
I
C
C
C
C
C
C
0
1
1
1
1
1
1
0
0
0
0
C
C
C
C
C
C
C
0
1
1
1
1
1
1
1
0
0
0
0
0
I
I
I
I
I
I
I
I
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
I
I
1
1
0
0
1
0
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
0
0
0
1
0
1
1
1
--------~--------------------------------------------- -----
QO*
C
C
C
C
C
C
C
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
1
0
1
0
0
0
1
1
----------------------------------------------------------Xl
C
C
C
C
C
C
C
C
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
0
1
0
1
1
1
0
0
1
1
----------------------------------------------------------X2
C
C
C
C
C
C
C
C
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
1
0
1
1
1
0
0
1
1
------------------------------------------------------ -~-~-
D-12
2241092-0001
BUSINESS-PRO Hardware Reference
PAL Programming Information
Table D-10. Dual-Mode Refresh Generator PAL U104 (Continued)
Logic Sheet 19
123 4 567 8 9
24MHZB
SRES
RCO
12MHZ I WAIT- I DB
6MHZ
RAK-
I
RFBUSY C
C
C
C
C
0
1
1
1
1
1
0
0
0
CK590
C
C
C
0
1
1
1
0
PRESET C
C
C
C
0
0
0
1
2241092-'-0001
I
o
I
I
I fDLj I j2
o
o
o
o
0
I I
I
o
o
0
110
o
0
o
o
o
o
1
I
12 13 14 15 16 17 18 19
CK590
Xl
Q2
PRESET
I RFBUSY QO
Ql
001
001
101
0
0
110
1
o
o
D-13
o
o
PAL Programming Information
Table D-ll
BUSINESS-PRO Hardware Reference
Main Memory Control PAL U119
Logic Sheet 22
123
CK2
RO-
I
DIM-* C
C
4
5
6
MDIR
BHE-
jO- I jO
C
o
o
0
0
o
C
0
1
o
1
0
0
1
C
C
C
C
MDH-
C
C
MDL-
C
C
1
o
o
1
o
o
o
1
0
C
WE-
o
o
o
o
o
o
C
C
373EN C
C
I fCAf- I
I IR
0
C
XCAS- C
C
13 15 16 17 18
DIM-*
WELEN
I DIC-*
0
DIC-* C O l
C 1 0
MUX
789
RST
DXC-
0
1
1
o
o
o
o
0
o
o
o
0
o
o
o
0
o
o
o
o
0
D-14
o
o
2241092-0001
BUSINESS-PRO Hardware Reference
Table 0-12
PAL Programming Information
Parity Control PAL U124
Logic Sheet 20
2 3 4 5 6 7 8 9 11 14 15 16 17
GlAOAK
XCASL64KSEL~ POH
MROC- I PKENRST- I IJl12
64KSEL- WENPARERI
POL
I
I
o
L64KSEL-
o
o
I
I
I
0
o
I
1
o
1
o
1
OUMY*
1
1
1
1
1
I
I
-
o
o
1
1
1
NOTE
NOTE
NOTE
NOTE
NOTE
1
1
1
1
1
1 NOTE 2
POH
o
- NOTE 3
POL
o
- NOTE 3
PK
o
0
001
1 0
1
1
o
NOTES:
1. L64KSEL- is an output only when RST- is high.
2. OUMY is an output only when RST- is l"ow.
3. POH and POL are outputs only when WE- is low and RST- is high.
2241092-0001
0-15
Logic Diagrams
BUSINESS-PRO Hardware Reference
Appendix E
System Logic Diagrams
E.l
MAIN LOGIC BOARD LOGIC DIAGRAMS
The first part of this appendix contains the logic diagrams for
the main logic board, drawing number 2240842 (26 sheets).
The
following list of the various logic circuits indicates the logic
diagram sheet on which the circuits are located:
*
Processor logic -- sheet 3
*
*
*
System ROM and reset logic -- sheet 4
*
Reset and nonmaskable interrupt logic -- sheet 7
*
Interrupt controllers
*
Decode logic -- sheet 9
*
*
Ports decode logic
*
Data bus control and internal data ports -- sheet 12
*
Bus latches -- sheet 13
*
Keyboard and mouse interface -- sheet 14
*
Printer logic -- sheet 15
*
DMA controller -- sheet 17
*
DMA/refresh arbiter and refresh controller -- sheet 19
*
Parity error logic -- sheet 20
*
640K memory decode and buffers -- sheet 21
*
DRAM control sequencer -- sheet 22
System clocks -- sheet 5
Coprocessor logic -- sheet 6
sheet 8
sheet 10
Real-time clock -- sheet 11
2241092-0001
E-l
Logic Diagrams
E.2
BUSINESS-PRO Hardware Reference
*
DRAM bank decode and address multiplexer -- sheet 23
*
DRAM bank 0
sheet 24
*
DRAM bank 1
sheet 25
*
Expansion bus interface -- sheet 26
OTHER BUSINESS-PRO LOGIC DIAGRAMS
Other logic diagrams contained in this appendix are as follows:
Diagram Number
Subject
Sheets
2240841
CPU Printed Wiring Board
2
2240845
Bus Interface Connector Board
6
2240849
vertical Board
2
2240921
Floppy Disk Controller Board
10
2240924
Winchester Disk Controller Board
13
2240927
3 Megabyte Expansion Board
7
2240930
256 X 9 DRAM Expansion Card
3
2240933
Communication Board
3
2240936
Alpha Graphics Video Board
9
2223011
Alpha CRT Controller
3
2240939
Dual Mode Video Board
6
2540317
PC-AT Mode II CRT Controller (To Be Supplied)
System Interconnect Diagram (To Be Supplied)
E-2
2241092-0001
Logic Diagrams
BUSINESS-PRO Hardware Reference
I
8
I
7
I
10
5
I
I
4
2
I
REV
A
J
I
I
DESCR I PT I C'N
Ct~ 5008810 (E) D.
I
JOt~ES
DATE
.'~
.
.
g..:"
• :>
I
.... PPR.:j~)ED
1
L ,'
("-;~
t.. J
,~\,.~t~.
D
~
=±D.;-
-
I
2
R E V I S I 0 N S
NOTES . UNLESS OTHERWISE SPECIFIED:
1 . ALL DEVICES ARE PREFIXED filTH SN74 . A LETTER
·'T" IN A PREFIX IS EQUAL TO "LS", At~D A LETTER
"F" AS A SUFFIX IS EQUAL TO CHIP CARRIER.
2. I.)CC IS APPLIED TO PIN 8 OF ALL 8-PIN IC's .
PIN 14 OF ALL 14-PIN IC's, PIN 110 OF ALL
lG-PIN I C' s, PIN 20 OF ALL 2e-PIN ICs, ETC.
8. GROUND IS APPLIED TO PIN 4 OF ALL 8-PIN IC's,
PIN 7 OF ALL 14-PIN IC's, PIN 8 OF ALL 16-PIN
I C·' s, PIN Ie OF ALL 20-PIN IC's, ETC.
4. DEUICE T~PL PIN NUMBERS, AND REFERENCE
DESIGNATOR OF GATES ARE SHOWN AS FOLLOWS:
D
I
8
.J
f..-
04
1)137
00
U06
00 AND 04
= DEUICE T~PES
2 .. AND 3 = PIN NUMBERS
L
U0G AND U07 = REFERENCE DESIGNATORS
5. RESISTANCE ~JALUES ARE IN OHMS.
G. RESISTORS ARE 1/4 WATT, 5%.
7. CAPAC ITANCE VALUES ARE IN 11ICROFARADS.
C
c
-
-
B
B
COHPUTER
-1
QT">:'
-
ITEM
I
NO
PART OR IDENTIF'>:'ING NUI1BER
P A R T S
I
GEHERATED
DWN
R.WHEELER
CHK
REt)
SH
RE~I
SH
REV
SH
A
8
07-03-85
DATE
0S-13-SS
DATE
18
0S-13-SS
S.HALLI'tCE
09:-13:-$5
.... PVD
224121843
8721
NEXT ASS'>:'
USED ON
8
I
7
I
6
P.PETERSON
I
I
43
I
I
NOTES
-
TEXAS 1 HSTRUHEHTS
Data Syst en,s Groul?
A
1
09-15-$5
D"'TE
09 19-95
3
IDRAW I ,·IG
SIZEI FSCM NO
B
NO
B6668
SCALE
4
HAHUALLV
DATE
t-1FG
S.RILE"t
RLSE
5
REVISE
08-1~-SS
APPLICATIOH
SH
HOT
DIAGRAH. LOGIC. DETAILEDHAIH LOGIC. EXCALIBUR
DATE
DATE
W.DILL-ER
RE~J
2241092-0001
S.WALLACE
",PVD ENGR
QA
A
10
A
2121
DO
..
DATE
ENGR
REUISION STATUS OF SHEETS
A
A
A
A A A
A
1
2
3
4
5
6
7
8
A
A
A A
A A
11 12 13 14 15 110 17 18
A
A
21 22 23 24 25 210
;
NOMENCLATURE OR DESCRIPTION
L I S T
P.PETEFi:SON
A
DRAWIHG
I
t.WNEJ
2
I
REV
A
224B842
I SHEET
1
DB
1
elF
26
E-3
BUSINESS-PRO Hardware Reference
Logic Diagrams
8
7
5
2
4
,]08
NC~
NC~
NC~
NC~
NC~
D
+ 12t)
,.
+ 12"
+1"r-Ia
(' 16
+5U
,
c
r
,]28
.... 14
(. 17
/
+31
'3ND
THRU C::::8
E..8
861.)
-
I
~
1
~l
T-
-T
1
T
C5,CE. ..C10,C11
..
C28 THRU C30 ..
C48
TH~_U
E:
.
-12"
16. 1.
__ C3!:l
T6.8
8
~
1
+5lJ
C 138. (: 140., C 1 42
.1
~
~..
::::
-
CE,8 THRU C80
C101..(:102 .. (:13!:l
C141
.01
-
--
C
=*
C81 THRU (:98.
..,.... (:103 THRU C112
.022
~
=*
-
,-5,1
C26
1
)>",,'----..:..::..;:;.'"-04.1---------....-----+------
~'"
""r--
-
C?7
+_ ... C24
0=
-T
~~
5U
1
G113 THRU e1as
.001
-
+.
!
-5,1
] ~n
Co;2..
--
l
l'i'
C28
6.8
J20
.....
D
-12l)
"l
DECOUPLING CAPACITORS
A
A
8
7
5
4
WHEELER
REV
DATE
DHt-l
TEXAS
INSTRUMENTS
06-14-85
ISSUE DATE
224B842
B
SHEET
A
2
3
E-4
2241092-0001
Logic Diagrams
BUSINESS-PRO Hardware Reference
8
s
7
2
4
+51.) _ _ _ _ _ _ _ _ _-,
SHE.
ALE
12
Cot~ALE
1 ·:·
'-'
J
ALTALE
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ISSUE DATE
E-20
2241092-0001
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IDw~48842
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ISSUE DATE
DATE
5-2-85
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19
8-8-·85
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8
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8
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BUSINESS-PRO Hardware Reference
5
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2248842
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2241092-0001
BUSINESS-PRO Hardware Reference
Logic Diagrams
7
5
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GLASS CLOTH, IMPREGNATED RESIN IB STAGEI
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2240841
802779
PART OR IDENTIFYING NUMBER
NOMENCLAiURE OR DESCRIPTION
PARTS
7
6
5
I
SEQ
MARK
MARK
MARK
TINLD
IDENT
NO
._.
2241092-0001
I
29
30'
Z PLACES
9.337 REF
IF
VIEW
SH21C-31
(J)
A
1
D£SCRIP110N
I---
.591
VIEW C
SHZ 10-51
Z PLACES
00
0
0
0
0
2 PLACES
.394
~.IIZ
~
CONTROL
A B C
A B C
A B C
A A C
A B 'e
~
~~'"''''
"w
a:
AT .109
REVISION LEVEL
THIS DRAWING
MARKING
C ONT INU ITY TEST
PROFILE
HOLE CONFIGURATION
DR ILL DECK
LAYER I ICOMP SIDEI
LAYER Z
LAYER 3
LAYER 4
LAYER 5
LAYER 6
LAYER 7
LAYER 8 ICOND SIDEI
I'IIII~IIE~ M"A~ ~II,IEE
I~.
(J)
OOOCD[]C[][]OCO
2240841
REVISIONS
~
--
I'
REV
NOTES: UNLESS OTHERWISE SPECIFIED:
914-01
901-01
903-01
10-00
F-SPEC
PROCESS
PROCESSES
8
00
00
01
00
N'
HGT .09, CLR BLK
CLR WHT,USING ITEM 2 ICAT 51
HGT .09, CLR BLK ICAT 51
THICKNESS .0003 MIN REFLOWED
I
7
1
•
•
•
•
•
9
NOTES
DRAWING 729-467
•
•
0-0
SECTION
SHZ IB -ZI
SCALE NONE
ADDITIONAL
CLASSIFICA110N
FDR CORRELATION TO aOVT/IND SPECIFICATIONS. SEE n
1
UNLE&6 OniERWlSE SPECIFIED
13
4
13
REV STAlUS
,FSHEETS
6
1 I F 1Fl
1SN 1I 12 I
2240843
",v
B721
NEXT ASSY
USED ON
APPLICATION
I
5
t
4
220
DIMENSIONS ARE IN INCHES
ANGLES tl"
TOLERANCES,
3 P't-ACE DECIMALS t.Ol0
2 PLACE DECIMALS t.02
IN1'ERPRET DRAWING PER MIL-D-IOOO
REMOVE ALL BURRS AHO SHARP EDGES
CONCENTRICITY MACHINED DI ...... ETERS .010 FIN
DIMILNSIONAL LIMITS APPLY 8£FORE PROCESSES
PARENl1iETlCAL INFC FOR REF ONLY
~
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.~Ol
:001
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.710 -.001
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LIST
Do.SEL V IDGE
DII
C:A~VE NEGAS
Ej~RG.
WALLACE
D[LLER
cS'USAN
RpEi!:TE
~
2-12-B5
2-12-85
ASTEVE
WES
12 -4 - 84
A (LEY
PETERSON
2-12-85
PROCUREMENT
SPECIFICATION
1
TEXAS
'019"£3214 OR''''.''
SCALE
2
A
INSTRUMENTS
....101.,._ ....
INCORPORATED
II!
(A-GLPW,M!A :H-MTI
NOTES
PR INTED WIR ING BOARD,
CPU
2-12-85
2-!2-85
2-12-85
16
1,4,13)1
14
III
TYPE III
2240841
SHEET
1 T8
I
1
OF
2
10/14/85
E-29
Logic Diagrams
8
7
6
5
4
3
BUSINESS-PRO Hardware Reference
1
2240841
E-30
2241092-0001
Logic Diagrams
BUSINESS-PRO Hardware Reference
I
8
D
I
7
5
I
I
4
NOTES. UNLESS OTHERWISE SPECIFIED:
1 . ALL DEVICES ARE PREFIXED WITH SN74, A LETTER "T"
IN A PREFIX IS EQUAL TO "LS".AND A LETTER "F" AS
A SUFFIX IS EQUAL TO CHIP CARRIER.
". vee IS APPLIED TO PIN 8 OF ALL 8-PIN Ie's.
PIN 14 OF ALL 14-PIN IC's, PIN 16 OF ALL
16-PIN IC's. PIN 20 OF ALL 20-PIN I C" s. ETC.
3. GROUND IS APPLIED TO PIN 4 OF ALL 8-PIN IC's.
PIN 7 OF ALL 14-P I 1'4 IC's. PIN 8 OF ALL 16-PIN
IC" 5 , PIN HI OF ALL 20-P I 1'4 IC's, ETC.
4. DE') I CE TIIPE. PIN NUMBERS. AND REFERENCE
DESIGNATOR OF GATES ARE SHOWN AS FOLLOWS:
1
14
A
DESCRIPTION
II ECN538658
(D) ESPINOZA
t,.,
I,:".,
el
I~,.,
1~3'"
C
Cll-52
"
"
"
+5V
GND
25uF
"
-
"
1
1
~ 25uF
i~·'
r~"
-12V
l
1·lUF
C6
;;;; ~~v
B
'-"PP'FtOVED
29
z
1i
1
D
+5V
.
-
DATE
I '71.2 / & s- I
~
00 AND 04
= DEVICE TIIPES
L
2. AND 3 = PIN NUMBERS
U06 AND U07 = REFERENCE DESIGNATORS
5. RESISTANCE VALUES ARE IN OHMS.
E.. RESISTORS ARE 114 WATT. 5".
. CAPACITANCE VALUES ARE IN MICROFARADS .
+l2V
I
6-25-85
1
04
U07
?
U06
"
PEV
I
I
2
R E V I S I 0 1'4 S
3
~
=±D.;-
-
C
I
6
B
DECOUPLIHG CAPACITORS
~ IJ~MT
-
PART OR IDENTIFIiING NUMBER
,
PARTS
I
I :PHN
D........
co. HERCUIUO
12-14-• •
I CHK
:P"''''''
".HILLER
II
+121J
18
GND
20
LMI.JTC- 22
LMRDC- 24
IOI.JC- 2f>
IORC- 28
DACK3- 39
DRQ3
32
DACK1- 34
DRQl
3f>
RFSH- 38
6MHZ- 40
1R07
42
IR06
44
IR05
4f>
48
IR04
IR03
59
DACK2- 52
TrC
54
56
BALE
+51J
58
14.3MHZ f>0
f>2
GND
1
3
5
7
90
11
13
15
17
19
21
23
25
27
29
31
33
35
XBHEBA23
BA22
BA21
BA20
BA19
BA18
BA17
MRDCMloITCXD8
XD9
XD10
XD11
XD12
XD13
XD14
XD15
MEMlf>1016lRla
lRll
1R12
IR15
IR14
DACK0DRQ0
DACK5DRQ5
DACK6DRQ6
DACK7DRQ7
+51J
MASTER8ND
2
4
6
8
10
12
14
16
18
20
22
24
2S
28
30
32
34
GND
RESET
+SIJ
IR09
-51J
DRQ2
-121)
0WS
+121J
GND
LMI.JTCLMRDCIOI.JCIORCDACK3DRQa
DACK1DRQl
RFSH6MHZlR07
IR0S
IR05
IR04
IR0a
DACK2TrC
BALE
+51J
14.3MHZ
GND
J16
~
XBHEBA23
BA22
BA21
BA20
BA19
BA18
BA17
MRDCMI.JTCXD8
XD9
XD10
XDll
XD12
XD13
XD14
XD15
44
48
50
52
54
56
58
f>0
62
1
3
5
7
90
11
13
15
17
19
21
23
26
27
29
31
33
35
XBHEBA23
BA22
111'121
111'120
111'119
111'118
111'117
MRDCMWTCXD8
XD9
XD10
XD11
XD12
XD13
XD14
XD15
4-
MEMlf>1016lRla
lRll
lR12
IR15
IR14
DACKaDRQ0
DACK5DRQ5
DACK6DRQS
DACK7DRQ7
+6V
MASTERGND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
J20
mRCURIO
I.Sue
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
5a
55
57
59
61
HMIXD7
XD6
XD5
XD4
XD3
XD2
XDl
XD0
WAITAEN
XA19
XA18
XA17
XA16
XA15
XA14
XA13
XA12
XAll
XA10
XA9
XAS
XA7
XA6
XA5
XA4
XA3
XA2
Xl'll
XA0
5
46
H8
[2,"1-5,SJ
1
3
2
4
E.
8
10
12
14
16
18
20
22
24
26
28
30
32
a4
36
38
40
42
J19
EDGE CON
1
3
5
7
90
11
13
15
17
19
21
23
25
27
29
31
33
35
as
DkiI:fs~;f~'E&OUD
2241092-0001
NMIXD7
XDE.
XD5
XD4
XD3
XD2
XDl
XD0
WAITAEN
XA19
XA18
XA17
XA16
XA15
XA14
XAla
XA12
XAll
XA10
XA9
XA8
XA7
XA6
XA5
XA4
XA3
XA2
Xl'll
XA0
J17
EDGE CON
TEXAS INSTRUMENTS
tl-25142
EDGE CON
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
a5
37
a9
41
43
45
47
49
51
53
55
57
59
61
GND
RESET
+SIJ
IR09
-51J
DRQ2
-121J
J15
EDGE CON
1
3
5
7
90
11
13
15
17
19
21
23
25
27
29
31
33
35
I
EDGE CON
EDGE CON
GND
RESET
+SIJ
IR09
-51J
DRQ2
-121J
L~
10~~48845
DAll!
0'\11-19-84
Br·0666SIDRA_GNO
SCALE
I
2248845
I
SHEET
r
EY
;:s
•
i
E-33
Logic Diagrams
~
EDGE CON
GND
RESET
+5V
IR0S
51)
DRQ2
-121)
0WS
+121)
GND
LMWTCLMRDCIOWC
IORCDACK3
DRQ3
DACKI
DRQl
RFSH6MHZlR0?
IR86
IR8S
IR04
IR03
DACK2Tc'C
BALE
+51)
14.3MHZ
GND
--
2
4
6
EDGE CON
I
3
5
7
8
II
13
16
17
18
21
23
25
27
28
31
33
35
3?
39
41
43
45
47
49
51
53
55
57
59
61
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
NMIXD7
XD6
XD5
XD4
XD3
XD2
XDI
XD0
WAITAEN
XA18
XA18
XA17
XAI6
XAI5
XA14
XA13
XA12
XAll
XA10
XA9
XA8
XA7
XA6
XA5
XA4
XA3
XA2
XAI
XA0
1-
GND
RESET
+5V
IR08
-51)
DRQ2
-121)
0WS
+121)
GND
LMWTCLMRDCIOWCIORCDACK3DRQ3
DACK1DRQl
RFSH
6MHZIR07
IR06
IRe5
IR04
IR03
DACK2TIC
BALE
+51)
14.3MHZ
GND
2
4
6
J21
EDGE CON
MEM161016lR18
lRll
lR12
IRIS
IR14
DACK0DRG0
DACKSDRG5
DACK6DRG6
DACK?DRG?
+61)
MASTERGND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
3
5
7
8
11
13
15
17
18
21
23
25
27
28
31
33
35
3?
39
41
43
45
47
49
51
53
55
57
59
61
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
NMIXD7
XD6
XD5
XD4
XD3
XD2
XDI
XDe
WAITAEN
XA18
XAI8
XA17
XA16
XA15
XA14
XA13
XA12
XAll
XA10
XA9
XA8
XA7
XA6
XAS
XA4
XA3
XA2
XAI
XAel
GND
RESET
+51)
IR08
-51)
DRQ2
12L'
0WS
+121)
GND
LMIoITCLMRDCIOIolCIORCDACK3DRQ3
DACK1DRQl
RFSH6MHZIR07
IR86
IR0S
IR04
IR03
DACK2TIC
BALE
+51)
14.3MHZ
GND
1
11
13
15
17
19
21
23
2S
27
29
31
33
36
XBHEBA23
BA22
BA21
BA20
BAl9
BA18
BA17
MRDCMIoITCXD8
XD9
)(D10
XDll
XD12
XD13
XD14
XD16
J22
HAl" BUS
MEMI61016lR10
lRll
lR12
IRI5
IR14
DACK0DRG0
DACK5DRG5
DACK6DRG6
DACK7DRG?
+51)
MASTERGND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
1
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
3
5
7
9
11
13
15
17
18
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
5?
59
61
NMIXD7
XD6
XD5
XD4
XD3
XD2
XDI
XD0
WAITAEN
XA18
XAI8
XA1?
XA16
XA1S
XA14
XA13
XA12
XAII
XA18
XA9
XA8
XA7
XA6
XA5
XA4
XA3
XA2
XAI
XA0
GND
RESET
+5V
IR0S
-51)
DRQ2
-121)
0WS
+121)
GND
LMWTCLMRDCIOWCIORCD'ACK3DRQ3
DACK1DRQl
RFSH6MHZlR8?
IR06
IR0S
IR04
IR03
DACK2Tc'C
BALE
+51)
14.3MHZ
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
J25
EDGE CON
1
3
5
7
90
11
13
15
17
19
21
23
25
27
29
31
33
35
XBHEBA23
BA22
BA21
BA20
BA19
BA18
BA17
MRDCMloITCXD8
XD9
XD10
XDll
XD12
)(D13
XDI-4
XD16
MEMI61016lR10
1 R11
lRI2
IRIS
IR14
DACK0DRG0
DACK5DRQ5
DACK6DRQ6
DACK7DRQ7
+51)
MASTERGND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
J24
1
3
5
7
90
11
13
15
I?
19
21
23
25
2?
29
31
33
36
XBHEBA23
BA22
BA21
BA20
BA19
BAlB
BA1?
MRDCMWTCXD8
XD9
XD18
XDl1
XD12
XD19
XD14
XD15
mRCURIO
~
TEXAS INSTRUMENTS I...... ··,.
[2 .. 3.5.6]
1
3
5
7
8
11
13
15
17
18
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
NMIXD7
XD6
XD5
XD4
XD3
XD2
XDI
XD0
WAITAEN
XA19
XA18
XA17
XA16
XA15
XA14
XA13
XA12
XAll
XA18
XA9
XA8
XA7
XA6
XA5
XA4
XA3
XA2
XAI
XA0
1
3
5
7
90
11
13
15
17
19
21
23
25
27
28
31
33
36
XBHEBA23
BA22
BA21
BA20
BA19
BA18
BA17
MRDCMIoITCXD8
XD9
XD18
XDll
XD12
XD13
XD14
XD15
~
J27
EDGE CON
MEMI61016lRI0
lRl1
lR12
IR15
IR14
DACK0DRG0
DACK5DRQe;
DACK6DRG6
DACK?DRQ?
+5U
MASTERGND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
38
32
3-4
36
J26
Dkit:fl~.t:.N·&OWD
TI-:!!?".?
EDGE CON
2
J23
EDGE CON
3
5
7
90
I
EDGE CON
1
8
J~
ID~~~8045
BUSINESS-PRO Hardware Reference
J28
DAl~-29-8-4
Bf"0666SIDRAWWlGNO.
SCALE
2248945
IIIHEET
I
,AEV
..
i
E-34
2241092-0001
Logic Diagrams
BUSINESS-PRO Hardware Reference
~
EDGE COH
GND
RESET
+51,)
IR09
-51,)
DRQ2
-121,)
0WS
+121,)
GND
LMIJTCLMRDCIOI-ICIORCDACK3DRQ3
DACK1DRQ1
RFSH6MHZlR07
IR06
IR05
IR04
IR03
DACK2V'C
BALE
--
+51,)
14.3MHZ
GND
2
4
E.
8
10
12
14
16
18
20
22
24
26
28
30
32
34
96
38
40
42
44
46
48
50
52
54
56
58
S0
f,2
EDGE COH
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
HMIXD7
XDE.
XD5
XD4
XD3
XD2
XDI
XDe
lolA ITAEH
XA19
XA18
XA17
XA16
XA15
XA14
XA13
XA12
XAII
XA10
XA9
XA8
XA7
XA6
XA5
XA4
XA3
XA2
XAI
XA0
GND
RESET
+51,)
IR09
-51,)
DRQ2
-121,)
0WS
+121,)
GHD
LMI-ITCLMRDCIOI-ICIORCDACK3DRQ3
DACK1DRQl
RFSH6MHZ1R07
IR06
IR05
IR04
IR03
DACK2
T/C
BALE
2
4
E.
8
10
12
14
IE.
18
20
22
24
26
28
30
32
34
36
38
40
42
44
48
50
52
54
56
+51,)
58
14.3MHZ 60
GHD
E.2
J29
EDGE COH
MEMI61016lR10
lR11
lR12
IR15
IR14
DACK0DRQ0
DACK5
DRQ5
DACK6DRQ6
DACK7DRQ7
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
+51,)
32
MASTER- 34
GND
86
HMIXD7
XDE.
XD5
XD4
XD3
XD2
XDI
XD0
IJAITAEH
XA19
XA18
XA17
XA16
XA15
XA14
XA13
XA12
XAll
XA10
XA9
XA8
XA7
XA6
XA5
XA4
XA3
XA2
XAI
XA0
GHD
RESET
+51,)
IR09
-51,)
DRQ2
-121,)
0IJS
+121,)
GHD
LMI-ITCLMRDCIOI-ICIORCDACK3DRQ3
DACKI
DRQl
RFSH6MHZIR07
IR06
IR05
IR04
IR03
DACK2T/C
BALE
+51,)
14.3MHZ
GHD
2
4
E.
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
J31
EDGE COH
1
3
5
7
90
11
13
15
17
19
21
23
25
27
29
31
33
35
MEMI61016lR10
lR11
lR12
IR15
IR14
DACK0DRQ0
DACK5DRQ5
DACK6DRQ6
DACK7DRQ7
XBHEBA23
BA22
BA21
BA20
BA19
BA18
BA17
MRDCMIJTCXD8
XD9
XD10
XDII
XD12
XD13
XD14
XD15
+51,)
MASTER
GND
J80
HAIH BUS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
11
13
15
17
19
21
23
25
27
29
31
33
35
XBHEBA23
BA22
BA21
BA20
BA19
BA18
BA17
MRDCMIJTCXD8
XD9
XD10
XDII
XD12
XD13
XD14
XD15
MEMI610161R10
IRll
IR12
IR15
IRt4
DACK0DRQ0
DACK5DRQ5
DACK6
DRQ6
DACK7
DRQ7
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
+51,)
32
MASTER- 34
GHD
36
GHD
RESET
SPEAKER
IR09
-51,)
DRQ2
-121,)
0IJS
+121,)
GHD
LMI-ITCLMRDCIOI-ICIORCDACK3DRQ3
DACK1DRQl
RFSH6MHZIR07
IR06
IR05
IR04
IR09
DACK2T/C
BALE
~
[2,3,4,6J
13
15
17
19
21
29
25
27
29
31
39
95
37
39
41
49
45
47
49
51
59
55
57
59
61
HMIXD7
XD6
XD5
XD4
XD3
XD2
XD1
XD0
lolA IT
AEH
XA19
XA18
XA17
XA16
XA15
XA14
XA19
XA12
XAll
XA10
XA9
XA8
XA7
XA6
XA5
XA4
XA3
XA2
XAI
XA0
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
XBHEBA23
BA22
BA21
BA20
BA19
BA18
BA17
MRDCMI-ITCXD8
XD9
XD10
XDll
XD12
XD13
XD14
XD15
KBD IND
1
3
2
4
E.
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
6
7
9
11
48
50
52
54
56
+51,)
58
14.3MHZ 60
62
~HD
~
J3
EDGE COH
XBHEBA23
BA22
BA21
BA20
BA19
BA18
BAt7
MRDCMI-ITCXD8
XD9
XD10
XDll
XD12
XD13
XD14
S3
35 XD15
MEMI61016lR10
lRll
lR12
IR15
IR14
DACK0DRQ0
DACK5DRQ5
DACK6DRQ6
DACK7DRQ7
64
66
E.8
70
72
74
76
78
80
82
84
86
88
90
92
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94
MASTER- 96
GHD
98
LEDPR 10~
J3
J34
J82
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2241092-0001
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XD4
XD3
XD2
XDI
XD0
IJAITAEH
XA19
XA18
XA17
XA16
XA15
XA14
XA19
XA12
XAll
XAI0
XA9
XA8
XA7
XA6
XA5
XA4
XA3
XA2
XAI
XA0
I
3
5
7
90
I1
13
15
17
19
21
23
25
27
29
31
TEXAS INSTRUMENTS
T125742
EDGE COH
I
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
J33
EDGE CON
1
3
5
7
90
..
1
EDGE COH
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
E.l
46
I;
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ISSUE DATE
0'1'2-14-84
B1'·06668 r·AW..ONO
SCALE
I
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2248845
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SHEET
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i
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Logic Diagrams
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GND
XD7
XD6
XDS
XD4
XD3
XD2
XDl
XD0
+5U
01 ~
02
03
04
05
06
07
08
09
10
GND
XA3
XA2
XAl
XA0
01
02
03
04
05
I
2248845
[2.9 4.5J
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K OHH PULL-UP/PULL-DONH CIRCUITS.
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TE'R'i1RES
LEDPR
GND
XA19
XA18
XA17
XA16
XA15
XA14
XA13
XA12
+5U
-.
01 ~
02
03
04
05
06
07
08
09
10
GND
BA23
BA22
BA21
:8A20
BA19
BA18
BA17
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02
03
04
05
06
07
08
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XA10
XA9
XA8
XA7
XA6
XA6
XA4
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01
02
03
04
05
06
07
08
09
10
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31,
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XD10
XDll
XD12
XD13
XD14
XD15
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01
02
03
04
05
06
07
08
09
10
-4
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.......
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I
2248849
IDRAWING NO
REV I S ION S
NOTES, UNLESS OTHER~ISE SPECIFIED:
1. ALL DEVICES ARE PREFIXED ~ITH SN74, A LETTER
"T" IN A PREFIX IS EQUAL TO "LS".AND A LETTER
"F" AS A SUFFIX IS EQUAL TO CHIP CARRIER
2. VCC IS APPLIED TO PIN 8 OF ALL 8-PIN IC's.
PIN 14 OF ALL 14-PIN IC's. PIN 16 OF ALL
16-PIN IC's. PIN 20 OF ALL 20-PIN IC's. ETC
3. GROUND IS APPLIED TO PIN 4 OF ALL a-PIN IC's.
PIN 7 OF ALL 14-PIN IC's, PIN 8 OF ALL 16-PIN
IC's. PIN 10 OF ALL 20-PIN IC's. ETC
4. DEVICE TVPE, PIN NUMBERS, AND REFERENCE
DESIGNATOR OF GATES ARE SHO~N AS FOLLO~S:
=iQ;-
REV
A
I
I
DESCR I PT ION
jECN538653 (D) ESPINOZA 6-21-85
:DATE
I
APPROVED
1~/21&~
~
29
04
U07
U06
00 AND 04
= DEVICE TVPES
L
2. AND 3 = PIN NUMBERS
U06 AND U07 = REFERENCE DESIGNATORS
5. RESISTANCE VALUES ARE IN OHMS
6. RESISTORS ARE l,I4 ~ATT. 5:v.
7. CAPACITANCE VALUES ARE IN MICROFARADS
COI1PUTER
I
PART OR IDENTIF~ING NUMBER
PARTS
~CHIN.n
:D!~MET.A.
.818 FJM
_DlMENSION"'L LI~lTS .....PL.... IE~ORE
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2248858
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2241092-0001
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6-21-86
E-37
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(.
(
(.
(
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(
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(
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(.
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
P3
2
)
1 ....
4 (
(.
3
(
6
(.
5
(
8
(.
7
10 (
(.
9
12 (
(
11
14 ("
13 (
16 (
15 .(
18 (
17 (
20 ("
19 (
22 (.
(
21
24 (.
23 (
26 (.
25
28 (
27 (
30 (
29 ....
32
(
31
34
HMIXD7
RESET
XD6
SPEAKER
XD5
IR09
XD4
-5V
XD3TCDRQ2
XD2
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XDI
0WS
XD0
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WAITAEH
LMWTCXA19
LMRDCXA18
IOWCXA17
IORCXA16
DACK3XA15
DRQ3
XA14
DACK1-
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,
,
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33
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P2
35
) 36
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) 53
) 54
) 55
) 56
) 57
) 58
) 59
) 60
) 61
62
( 63
(. 64
( 65
(. 66
( 67
P3
36
35
38
37
40
39
42
41
44
43
46
45
48
XA13
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XA12
RFSHXA11
6MHZXA10
IR07
XA9
IR06
XA8
IR05
XA7
IR04
XA6
IR03
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68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
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TEXAS INSTRUMENTS
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70
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69
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72
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79
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82
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81
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84
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86
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85
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88
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BA21
IRll
BA20
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BA19
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MASTERXD15
DATE
G.MERCURIO 10-12-84
~
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KBD IND
LEDPR
=-
-==
~
TI'25742
IsF 1
47~
50
49
52
51
54
53
56
55
58
57
60
59
62
61
64
63
66
65
68
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BUSINESS-PRO Hardware Reference
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III:tSUE DATE
I
I
SHEET
2
:
6-24-85
E-38
2241092-0001
Logic Diagrams
BUSINESS-PRO Hardware Reference
r--.------.----------------.--.-----.---------.--------------------~-.~~~~~=--_,.----=~-~-----------------------------.--.--.---.-.--.-
R E OJ I S ION S
----.-------- ._._-----_.._-
UNLESS OTHERWISE SPECIFIED:
1. RLL DEVICES ARE PREFIXED WITH SN74. A LETTER
"T" It~ A PREF I X I:; EG'UAL TO "LS".· EXCEPT ~lHEN
IJSEIo AS A SUFFIX . "AT" IS EQUAL TO "ALS" . MID
A LETTER "F" AS A SUFFIX IS EQUAL TO A CHIP
CARRIER
2
UCC IS APPLIEIo TO PIN 8 OF ALL 8-PIN IC's.
PIN 14 OF ALL 14-PIN IC's. PIN 16 OF ALL
lo;-PIt~ IC' g:,
PIt-~ 20 OF ALL 20-PH~
IC" g: . ETC
3. GROUND IS APPLIED TO PIN 4 OF ALL 8-PIN IC'g:.
PIN, OF ALL 14-·PIN IC'g: . PIt~ 8 OF ALL IE.-PIN
IC's. PIN 10 OF ALL 20-"IN IC" s. ETC
4. DEVICE T~PE, PIN NUMBERS. ANIo REFERENCE
DESIGNATOR OF GATES ARE SHOWN AS FOLLOWS:
NOT~S
-RE',J
DESCRIPTION
A
IIATE
._.
EUI538277 (C) E::;PINOZA 6-28-85
._
A .I.IEt~E.JA·~ __
7-~-:35
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BUSINESS-PRO Hardware Reference
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8
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6
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3
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7
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2241092-0001
BUSINESS-PRO Hardware Reference
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7
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XDATA [4] (0-7)
XD7
XD6
XD5
XD4
XD3
XD2
XDl
XD0
D
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-
XA9
XA8
XA7
XA6
XA5
XA4
XA3
XA2
XAl
XA0
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[4]
[4]
[4]
[4]
[4]
[4]
[ 4]
[4]
[4]
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
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0
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I
6
I
5
4
I
I
3
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4
6
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3
5
7
9
11
13
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21
23
25
27
29
31
33
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28
29
30
31
32
33
34
35
36
37
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23
25
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D
B
1
3
5
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11
13
15
17
19
21
23
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35
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I NSTRUHEHTS
8
2241092-0001
I
7
I
D",TE
.. loiN
TEXAS
6
I
5
I
4
C.HALEIi.'
02-21-85
I ....U~ ..... T ..
B
86668
SC: ... LE: NONE
I
3
r ....
l"'IZErSC:M NO
I
A
N'" NO
I
2248921
J SHEET
2
I
IP:v
3
L
E-41
Logic Diagrams
.
c:
BUSINESS-PRO Hardware Reference
.__~e~.________~__________~7__________-L________~6~________~________~~~'__________L-_________4__________~__________3__________~__________._2_________~
+ 5 '}
1
~;
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1
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82
1
2
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14
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5
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4
5
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7
8
9
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8
104
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4
19
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6
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14
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5B
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7B
8B
.
18
17
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15
14
18
12
11
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BDI
BD2
BD8
BD4
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BDE.
BD7
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,
BDe
BDI
BD2
BD:3
BD4
BD5
BD6
BD?
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1273
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18
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3D
4D
5D
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7D
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7
8
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14
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4
A
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DATE
D"~"'"
C. HALE'>:'
ISSUE
2 DRL [8]
5 DRH [6]
E. F~:8T [5]
9 DMAEt·1 [5]
12 ~lOENI [81
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TEXAS
7
=0
-
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4 ?I<
8
B
I
U4
1'245
.:
~
MR- [ E. ]
02-21-85
DATE
2248921
B
SHEET
4
:3
E-42
2241092-0001
Logic Diagrams
BUSINESS-PRO Hardware Reference
8
I
I
7
4
0
3
L--
EN8 ..... 4- [8]
DMAEH [ 4]
FDCS- [ 4]
DACK2- [3]
TiC [8]
I
........-; oS
SI
4-e48e57
5
U88
I
6
U88
14
I
-4
I
8
BDe
BDI
MODE- [ 4]
C
MR-
T
[4]
lPR
2PR
ID
2D
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2CK
lCL
2CL
LDe
LDI
+5 1J
2
3
4
5
6
7
8
8
11
PAL 16LB
I1
12
13
14
15
16
17
18
18
I Ie
VI
TIi
'''2
'i3
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'~5
'riG
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V8
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12
5
U33
...
8
14
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4
4.7K
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2Q ~
5
12
13
2MHZ [9]
C16 [8]
C8 [8]
C4 [8]
8
1
-
T175
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11
2
P
D
Q
CK
CL
f-4
7
3D
4D
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74
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4-228088
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8
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13
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12
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11
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13
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8
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EDI
ED2
ED8
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ED5
ED6
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BIORC- [4]
Blowe- [ 4]
EA0 [4]
FCLK [8]
-
A
765A
FIHT [4]
RDV
lHT 18
DRQ 14
RST
IJCOE 24
DACK
T... C
RCLK 22
RDATA 23
D0
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WDA 80
PSI 31
D2
D3
PS0 32
WCLK 21
D4
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D5
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HD 27
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2 RD
STP 87
3 WF~
SEEK 88
4 CS
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5 Ae
WP . . . TS 84
18 CLK FLT/T0 88
29 use
MFti 26
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HDL ~
85
1
15
Ie.
e.
7
8
9
10
11
12
II
IJFOE [8]
RCLK [9 ]
RD765 [8]
WDA [9]
PSI [8]
PS0 [9]
WCLKP [8]
WEN [7]
HD [7]
DIR [7]
STP [7]
SEEt( [7]
HlOE:'; [6][7]
WPROT [E,] [7]
FLT/TK0 [7]
r'lFM [9]
2s
r--
A
Ull
DATE
DWN
TEXAS
I HSTRUHEHTS
8
2241092-0001
I
7
I
6
I
5
I
4
C. HALE'x"
02-21-85
ISSUE DATE
I
8
lDFlA'HNG NO
SIZE rSCM NO
8666B
SCALE: NON~T
ZZ489Z1
B
I
2
I
I
Jc
FIE'·'
5
SHEET
1
E-43
BUSINESS-PRO Hardware Reference
Logic Diagrams
8
7
150
I
D
J5
6
U32
14
5
2
3
+5U
I
D
10 11 12 18
.... I 6 INDX3., I 16 I.JP3-
I~~____~2~
1
(>l1~1~7~R~D~A~T~A~3-----~-r-i----------------------------------'1
(115
4
I:
TK0e3-
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lAI
1/2
l
I~I ~~18~______________________________________________~I~N~D~E~X~[~5~]__
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8
LA3
1~3
1 A4
I
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16
I.JPROT
[5]
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t -1
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U14
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+5U
1
1
R15
1513
2
C
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1
R14
1513
R16
1513
2
2
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J3
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1
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I
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T248
11
R
15
19
17
2A~2~2
2A3
2~3
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4
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2A4
1/2
U14
___________________________
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3
~
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.... T
U7
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13
L-(
11
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[9]
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8
9
I
[4][7J[8]
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6
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12
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L-________________________-=E.=.l__-!..l-o~
B
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I.JDATA1-
22
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11
I.JDATA2-
22
J4
88
U20
I.JDATA3-
13
J5
3
2
88
U20
12
18
A
A
DWN
TEXAS
C_HALE~
REV
D"'TE
132-21-85
2248921
B
I HSTRUtlEHTS
8
7
5
SHEET
C
6
4
E-44
2241092-0001
Logic Diagrams
BUSINESS-PRO Hardware Reference
8
7
5
6
9
4
2
TK00 [6]
150
U92
I
I
DRH [ 4]
D
39
1
I
2
9
4
5
6
8
9
1
2
4
6
8
.... I 8 INDX1-
< 128
I..IP1( 130 RDATA1( 126 TK001-
"
D
1'248
1/2
1G
1A~'11
1'12
1A
1A3
1A4
1'19
1'14
INDEX [5
J.lPROT [5
RDATA [9
18
16
14
12
U15
4
5 1
SEEK [5]
U8
U16
J4
"" I 8 INDX2-
c
<:
<:
<:
"
11
13
15
17
19
128 I..IP2190 RDATA2126 TK002-
EN2- [5]
STP [5]
I
1/2
2A2~'11
1'12
2A3
2A4
2G
1 '13
1 '14
9
7
5
3
C
3
1
T244
11
13
15
17
19
1'248
2A1
U15
1
21
I
T08
U16
DIR [5]
HD [5]
2A~'11
2A2
2'12
2A9
2'19
2A4
2'14
2G 1/2
3
9
7
5
3
2
16
U17
T
6
16
U17
8
16
U17
11
B
10
16
U17
20", 33
STEP2STEP9-
2O,,"34
DIR1-
18
33
DIR2DIR3-
18
34
HSL1-
32
33
HSL2-
92
34
HSL3-
18
J5
7'
12 ..... 35
11
19
~1~5~
7'
35
B
12
16
U17
______________________________________________. -__
STEP1-
"
4
16
U17
5
U4
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FLT/TK0 [5]
6
J.lE1-
+-__~1~2~~~ MC3487
r-____________
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-=9'-1~
11
.
1~~~~1~0
1
________~
U12
I..IE2-
24 .... J4
I..IE9-
14'\.. J5
/
-,
BJ.lEN [9]
1
A
R1
::t
1
4.7K
R2
+5U
A
4.7K
REV
2248921
TEXAS
I HSTRUI1EHTS
8
2241092-0001
7
6
5
A
E
SHEET
?
4
E-45
Logic Diagrams
e
'7
DRL [4]
DRH [ 4]
5
6
2
3 1
1
9
1
2
T04
U25
10
I
8
2
3
1
2
D81
T02
U18
D
BUSINESS-PRO Hardware Reference
3
I
T08
U16
10, J 3
D82-
12 .... J 3
,
38
U19
D
4
51
D82
D81-
6
,
38
U19
MOEHl [4]
4
MOEH2 [4]
MR- [4]
MOEH1I'2- 16, J 3
6
51
,
38
U20
9
Ie 1
e
38
U20
c
MD8EL [5]
4
16
U22
3
c
2,J 3
,
LOl.l1-
EH3/4- [5]
5
6
I
4
D8S
9
10 1
T02
U18
12
13
B
J
11
D84
12
13
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U16
r
5
98
U21
I
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2
16
U22
A
6,J 4
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8,J 5
B
,
MOEN9/4- 16_""J 4
10
9 1
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38
U21
6
41
MOEN4 [4]
,
I
9
98
U21
9--'!!,.J 5
D84-
S8
U19
2
1 1
,
I
11
I
14,J 4
D83-
38
U19
•
MOEN3 [4]
e
13
12
I
11
'7,J 5
MOEN9-
1
'1
USS
,
_14
4.7K
MOEN4-
+5U
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38
U21
I
E
LOI.l2-
2 .... J 4
LOI.l3-
3,J 5
,
A
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R
V
TEXAS
rCnn.HroAiL~E~V~__~0~2~-~2~1_-~8~5~~~~~~__-L________-r_2_2_4_8
__
92
__1____L-.~
I HS'I".RlI'tDITS
8
'7
6
5
4
s
E-46
2241092-0001
BUSINESS-PRO Hardware Reference
. -______
8 ______~1
Logic Diagrams
_______7_.______~1______6______~1~______5 ______~1________4 ______~1______3_______~1______2______~1________1 ______. _
2MHZ
[5J
8-0S002E.
12
I 13
I
PAL1SR6
LS04
W-- CLK Q 11-0-1=,2,;:S~T.::B+-+_ _ _ _ _ _...:I::.;J2::;5~_-+-_ _ _ _ _ _ _--=.1.::::3--'1
osc
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LS161
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>:J-===10=-:--:+-ir----7
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LS14
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QB
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8
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8-049026
11
1
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5
6
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14
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18
~
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4MHZ
3
12
2MHZ
4
13
lMHZ
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D
~
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...
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U24
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5
r!-=-
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8
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16
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18
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U28
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CK
CL
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1
WCLK
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2
D
P
Q.2..-.
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7
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RD765 [5J
3'1 1-'''--_ _ _-'-':.:....:...::..::.....::..::'-'
5-7
3
--
12
RCLK [5 J
4'1 ....".=-_ _ _-'-c::..:::..;.;......::...::_=_
4B
STR
U26
U34
Q 'l8
lMHZ
1-_4" -_ _ _-'-F..:::C""L'-!;K'--![""5:..:J"..
.-~8~2:-:;1~1:-:;0~5~0~~1~5~SEL
AT74
Q 1-"-6_ _-,
CK
1
CL
'--____---'1
R21
51
1
MDSEL [5]
WDA [4J
PS9 [4J
PS 1 [4J
C
-::::=-
8-058080
-
R3
1
+5V
2
2
8-958092
8-127082
14
RQ
T221
U23
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IoID1691
6
15
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-l
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C3
B
2
5.6K
1
:::~ 100PF
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1
8-127080
2.7K
1
13
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,----=.1.::::0-1 B C
7
RQ
T221
U23
4
8-088118
9
A
'--_ _ _-=-1::.2-tRCLK WDATA
. -_ _ _ _-;-1:::-1c:t R DATA
VCO
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5
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1
17
~
Q
12
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04
03
02
01
STB
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1-71~6---------~U::;C:;.:O""L=-;-:-:(~10:;-:-J
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a
8-070126
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[5]
3
I
U25
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8- 1 94121
4
>:>-::T":0:-4:-----'
15
8
8 - 1 971 24
6
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6
T04
U25
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--
IoID1691
.~:----------------_--------------1_+_~-71~I<:4RDATA
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5
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TI'25742
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2241092-0001
Logic Diagrams
BUSINESS-PRO Hardware Reference
IDWG ~24B924
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6
9
12
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16
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13
14
17
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28
29
30
31
32
33
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21
22
23
24
35
36
37
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2241092-0001
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02-20-85
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2
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02-20-85
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2241092-0001
BUSINESS-PRO Hardware Reference
Logic Diagrams
~
I
2248924
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OWG NO
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WFM-
4
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2
12
3
11
1
13
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CORRD [10]
BDRQ [3l
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4
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8
13
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15
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TEXAS INSTRUMENTS
INCORPORATED
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5
4
R.JAlJENS
DMTE
134-03-85
ISSI.JE DATE
SHEET
2
-->--------_._-
3
2
E-73
Logic Diagrams
8
7
5
6
BUSINESS-PRO Hardware Reference
2
8
4
P1
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""-43
1
2
A:3
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12
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9
4
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PI
WAIT-
18
",/
7:08
lI18C
A
DATE
04-03-85
ISSUE DATE
SHEET
3
8
E-74
2241092-0001
BUSINESS-PRO Hardware Reference
Logic Diagrams
I
a
I
7
I
6
5
I
I
4
NOTES, UNLESS OTHERWISE SPECIFIED:
1 . ALL DEVICES ARE PREFIXED WITH SN74, A LETTER
"T" IN A PREFIX IS EQUAL TO "LS",AND A LETTER
"F" AS A SUFFIX IS EQUAL TO CHIP CARRIER.
2. VCC IS APPLIED TO PIN a OF ALL a-PIN IC's,
PIN 14 OF ALL 14-PIH IC' s. PIN 16 OF ALL
16-PIN IC's. PIN 20 OF ALL 2e-PIH IC's. ETC.
3. GROUND IS APPLIED TO PIN 4 OF ALL 8-PIN IC's.
PIH 7 OF ALL 14-PIN IC's. PIN 8 OF ALL 16-PIN
IC's. PIN 10 OF ALL 20-PIH IC's. ETC.
4. DEVICE T!.'PE. PIN HUMBERS. AND REFERENCE
DESIGNATOR OF GATES ARE SHOWN AS FOLLOWS:
D
I
DESCFUP'rION
1
I
:O"'TE
",pop ROVED
D
r-
04
U07
e0
U06
00 AND 04
.. DEVICE T!.'PES
L
2. AND 3 .. PIN NUMBERS
U06 AND U07 .. REFERENCE DESIGNATORS
RESISTANCE VALUES ARE IN OHMS.
RESISTORS ARE 1/4 WATT. 5:1..
CAPACITANCE VALUES ARE 1101 MICROFARADS.
U2S HAS PIN 14 TIED TO +5VU28
US9 HAS PIH 20 TIED TO +5VU39
5.
6.
7.
8.
9.
C
1.
I
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2
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3
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B
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NO
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PART OR IDENTIF!.'ING HUMBER
PAR T S
I
GENERATED
REVISIOH STATUS OF SHEETS
REV
SH
1
2
S
4
5
6
7
a
9
ENGFt
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D"'TE
"''''
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MFG
DATE
RLSE
USED 0101
2241092-0001
I
7
I
6
I
I
43
4
HAHUALLY
I
I
NOTES:
TEXAS I NSTRUHENTS
Data
S~stems
Group
LOGIC DIAGRAH.
ALPHA GRAPHICS VIDEO
3
IDFt"'W'NG NO
A
I
NONE
_I
I
2
I
I
REV
2248936
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2240934
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CHK
A
DRAWING
SHEET
DB
1
OF
9
1
E-75
Logic Diagrams
8
I
I
7
I
6
5
1
I
4
BUSINESS-PRO Hardware Reference
I
3
I
2
2
XD7
XDG
XD5
XD4
XD3
XD2
XDl
XD0
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[3]
XADDR BUS
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AEN
4
6
3
5
7
XA16
XA 15
XA 14
XA 13
XA12
XA11
XA 10
XA9
XA8
XA7
XA6
XA5
XA4
XA3
XA2
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C
-
D
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112
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11
18
15
17
19
21
22
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23
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8
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25
27
29
31
-
IO~C-
33
35
37
:39
41
43
45
47
49
51
53
55
57
59
61
6MHZ
[4]
[7]
c
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BA22
BA21
BA20
BA 19
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BA17
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XD9
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XD11
XD12
XD13
XD14
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A
B
1
3
5
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9
11
13
15
17
19
21
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25
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29
31
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33
36
35
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EXPANSION BUS CONNECTORS
D.... N
TEXAS
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7
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04-08-85
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2248936
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ISSUE DI'\TE
SCALE: NONE
I
3
I
I
1
2
SHEET
JREV
82
I
E-76
2241092-0001
Logic Diagrams
BUSINESS-PRO Hardware Reference
I
8
I
7
I
6
5
I
I
4
I
3
I
2
XADDR BUS
CONTROL BUS
IOI.IC-
T13B
D
XA9
XA8
+5V
XA6
XA5
XA4
1
2 A
3 B
6 C
<4 51
5 52A
62B
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14 DEC1'x'1
'x'2 ~ DEC2'x'3 ~
'x'4 ~
'x'5 ~
'x'6
'x'7
~
U34
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r
RESET
12
AS27
U15
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1
NODMA
CUR
A17
CRTEN
A18
ADD7
1
2
3
4
5
6
7
8
9
11
U13
IOPORT-
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PL16LBA
11
12
13
14
15
16
17
18
19
19
18
17
16
15
14
13
12
01
IrOl
Ir02
IrOS
Ir04
IrOS
Ir06
02
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I
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16
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T244
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2\(1
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2\(3
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26
8
11
13
15
17
19
[2J
RST-
U27
1
2
4
XA5
XA6
XA7
XA8
XA12
XAll
XA10
XA9
TIPC-
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XDATA BUS
lA~'x'<4
[2J
S0e
U28
-
18
1'x'1
16
1'x'2
1 'x'3 ~
12
9
2'x'1
7
2'x'2
5
2'x'3
2'x'4 3
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2A3
2A4
26
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U38
16
lAl
lA2
1 A3
.::L-
1
-
1
AT244
1
2
4
6
8
11
13
15
17
19
MRDCMI.ITCTIPC
XAe
XA4
XA3
XA2
XAl
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MASTERAEN
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XA7
XA0
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12
13
4.7K
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1
2
131
1
18
16
14
12
9
7
5
3
A5
A6
A7
A8
A12
All
A10
A9
C
r-
U35
[2]
V6CUR [4]
TC BUS
[4J
CUR [4]
R22 :>
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BA17
1
2
Ase4
U26
LED
XAIS
XA14
XA15
XAi6
BA17BA18XADD?
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31313
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BA18
3
4
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1
R2S
47
I
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BA23
BA22
BA21
BA19
TIPCBA28
-=..!::-
A
1
2
3
6
4
5
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A
B
C
61
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62B
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2241092-0001
I
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1
6
I
5
I
5
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A14
A15
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A18
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5
6
9
12
15
16
19
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ALPHA GRAPHICS VIDEO
T373
ID
2D
3D
4D
5D
6D
7D
8D
ENA
OC
U36
T138
D;CR1
3
4
7
8
13
14
17
18
11
1
4
A.
DATE
McBRIDE
84-138-85
ISSUE DATE
SIZE IFSCM NO
B
SCALE: NONE
I
3
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2248936
86668
I
I
2
I
83
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1
E-77
Logic Diagrams
8
7
BUS
BUS
[2J XDATA
2
3
4
6
BUSINESS-PRO Hardware Reference
BDATA BUS (6 ' ~J
,
ADDR BUS [3J
CONTROL BUS [2J
[2JCONTROL
T
BMRDC-
+6V
AT245
I
XD0
XD1
XD2
XD3
XD4
XD6
XD6
XD7
D
2
3
4
6
5
7
8
8
.....
IA
2A
IB
2B
3B
4B
5B
6B
7B
SB
SA
4A
51'1
6A
7A
8A
18
17
16
16
14
13
12
11
DABS
BD0
BDI
BD2
10
II
12
BD8
13
BD4
14
BD5
15
BD6
16
BD7
17
ADD7 57
1'118 5S
A17 59
AI6 60
7
A15 61
A14 62
AI3 63
1'112 64
All 65
66
A5
A4
67
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58
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XD2
XD3
XD4
XD5
XD6
XD7
1'118
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Ai?
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ZBENA15
A14
A13
1'112
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1'14
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~ 188-85
BM
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BD3
BD4
BD6
BD5
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19
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I
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XD8
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XD12
XD13
XD14
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C
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1 A3
4
5
8
11
13
15
17
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1 ':<'3
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2A2
2A3
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14 BD2
12 BD3
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9
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BD6
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9
4
60
2
5
6
8
12
15
16
19
6
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55
54
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C3
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LD18MHZ
20
21
22
23
24
25
25
27
1
14
13
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33
32
31
30
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C6
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B10
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37
36
35
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5
5
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30 T3
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33 T6
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20 CI
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21 C2
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22 C3
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23 C4
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24 C5
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25 C5
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26 C7
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33
32
31
30
28
28
27
25
25
23
21
2
24
22
04-08-85
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2248936
B
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SHEET
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3
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2241092-0001
Logic Diagrams
BUSINESS-PRO Hardware Reference
8
I
I
7
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5
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8
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7
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6
I
5
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4
BUSINESS-PRO Hardware Reference
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3
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2248937
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2
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E-80
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86
SHEET
1
2241092-0001
Logic Diagrams
BUSINESS-PRO Hardware Reference
1
8
I
7
I
5
I
5
[4] GRAPH BUS
I
4
I
3
I
2
1
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1
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1 1 A8
8
A9
7
A10
6
All
5
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4
A13
3
A14
2
A15
68 A15
67 A17
65 A18
65 A18
A3
A4
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A8
A8
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All
Al2
12
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C
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1
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[4]
[5]
[4]
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63
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1
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40
41
42
45
47
48
48
50
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51
53
54
55
55
57
58
58
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3
4
5
5
7
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18
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58
57
56
55
54
3
4
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BD2 12
BD3 13
ED4 14
ED5 15
ED5 15
BD7 17
GED8 19
GBD820
GBD10 21
GBD11 22
GED12 23
GBD13 24
GBD1425
GBD15 26
~
GREDGGRNGBLUTEST
TEST
DCLK
RESET
XDe
XDI
XD2
XD3
XD4
XD5
XD5
XD7
XD8
XD8
XD10
XDll
XD12
XD13
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BHEA15
A15
A0
AD0
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AD2
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AD4
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BD2
BD3
BD4
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5
5
7
8
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53
51
50
48
48
47
46
45
44
43
42
41
413
38
38
37
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AD BUS [8]
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AD4
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AD5
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BB3
BB4
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BB5
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CD3
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CD5
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36
34
33
32
31
313
28
28
18
52
BB BUS [8]
C
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2
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18
17
15
15
14
18
12
11
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GRAI1 BUS
BDATA BUS
[8]
[ 4]
A
TEXAS
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RESET
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18 GND
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330
38
DMUX
38
GRD37
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2248936
I
REV
ISSUE DATE
3
I
87
SHEET
SCALE: NONEI
I
2
I
1
E-81
BUSINESS-PRO Hardware Reference
Logic Diagrams
I
8
[7]
I
I
7
I
5
I
4
I
:8
I
2
GRAI1 BUS
-cV,;:-C..=;C_-:-",,9-1
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12
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11
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MA7
113
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9
14
13
12
11
8
7
6
113
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16
2
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4
1
18
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12
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8
7
6
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3
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6
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113
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3
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6
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113
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17
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BUS
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ALPHA GRAPHICS VIDEO
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8
I
7
I
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5
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4
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132-21-86
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2248936
I
I
2
SHEET
I
REV
88
I
E-82
2241092-0001
BUSINESS-PRO Hardware Reference
Logic Diagrams
8
?
VCC
5
8
4
2
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1
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PIN 14 OF ALL 14-PIN IC's, PIN 16 OF ALL
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3. GROUND IS APPLIED TO PIN 4 OF ALL 8-PIN IC's.
PIN 7 OF ALL 14-PIN IC's. PIN 8 OF ALL 16-PIN
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E-90
2241092-0001
Logic Diagrams
BUSINESS-PRO Hardware Reference
2248939
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E-97
BUSINESS-PRO Hardware Reference
Logic Diagrams
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E-98
2241092-0001
BUSINESS-PRO Hardware Reference
Option Board Outline
Appendix F
Option Board Outline
The following illustrations give outline dimensions for a fullsize board and a half-size board to allow the user to design and
customize his own boards to fit the BUSINESS-PRO cabinet.
TO BE SUPPLIED
2241092-0001
F-l
BUSINESS-PRO Hardware Reference
Switch and Jumper Settings
Appendix G
Switch and Jumper Settings
This appendix is a summary of the switch
available to the user in the BUSINESS-PRO.
TO BE SUPPLIED
2241092-0001
G-1
and
jumper
options
BUSINESS-PRO Hardware Reference
Index
Index
This index lists key topics of this manual
each topic appears, as follows:
and
specifies
where
*
Sections
Section references appear
where n represents the section number.
*
Appendixes -- Appendix references appear as Appendix
where Y represents the appendix letter.
*
Paragraphs
Paragraph
references
appear
as
alphanumeric characters separated by decimal points.
This first character refers to the section or appendix
containing the paragraph, and any other numbers indicate
the sequence of the paragraph within the section or
appendix. For example:
as Section n(
Y,
3.5.2 refers to Section 3, paragraph 5.2.
A.2 refers to Appendix A, paragraph 2.
*
Figures
Figure references appear as Fn-x or FY-x,
where n represents the section and Y represents the
appendix containing the figure; x represents the number
of the figure within the section or appendix.
For
example, F2-7 refers to the seventh figure in Section 2.
*
Tables -- Table references appear as Tn-x or TY-x, where
n represents the section and Y represents the appendix
containing the table; x represents the number of the
table within the section or appendix. For example, TB-4
refers to the fourth table in Appendix B.
*
See and See also references -- See and See also direct
you to other entries in the index. For example:
Logical Unit Number .
See LUNO
Device .
See also individual device names or numbers
Page numbers that correspond to these index references appear
the Table of Contents.
2241092-0001
Index-1
in
Index
BUSINESS~PRO
Hardware Reference
AC Parameters:
Monochrome Display Unit Video
T6-92
T6-61
Video
Acknowledge:
4.6.5
Command .
Interrupt
2.2.6
Address and Control Bus Buffering
· 2.2.3.1
Address Decode Logic
· 5.1.1.2
T5-4
Address I/O Port
Address Map Register
· 6.4.1.2
Addresses:
Controller System
.
6.3.4
5.1.2.1,
T6-20,
T6-77,
T6-78
I/O Port
T2-4
Real-Time Clock .
Alphanumeric Graphics
· 6.4.1.2
TB-16, TC-16
Alternate Diskette Controller I/O Addresses .
TB-12, TC-12
Alternate Fixed Disk I/O Addresses
Applications:
BUSINESS-PRO Computer
1.1
Multiuser
1.1.3
Workstation .
1.1.1
Arbiter, DMA/Refresh
· 2.5.1.1
Arbitration .
· 6.4.1.2
Attribute:
Character
· 6.4.1.6
Latch
· 6.4.1.2
Basic Assurance Self-Test, Keyboard .
Battery Circuit
Baud Rate Generation
Baud Rate Values, TI Mode RS-232
Bisynchronous 1 I/O Addresses
Bisynchronous 2 I/O Addresses
Bit Correlations
Block Diagram:
Floppy Disk Controller
Main Logic Board
Board:
Bus Interface
Main Logic
Break Code Prefix Command
Buffer, Keyboard
Buffering:
Address and Control Bus .
CPU Bus .
Data Bus
Bus Control, CPU
Bus Interface Board .
BUSINESS-PRO:
Applications
Compatibility
Drive Types .
· 4.2.1.1
· 2.6.2.1
6.5.3
T2-6, T6-99
.TB-19, TC-19
.TB-18, TC-18
6.4.1.4, T6-67
Index-2
2241092-0001
F5-1
F2-1
· 1.3.3.2
· 1.3.3.1
4.6.4
4.1. 5
· 2.2.3.1
2.2.3
· 2.2.3.2
2.2.4
· 1.3.3.2
1.1
T6-70
T6-24
BUSINESS-PRO Hardware Reference
Environmental Requirements
Keyboard
Mass Storage Options
Operating Systems
Options .
Physical Dimensions
Power Requirements
Software
Specifications
Byte, Color Latch
Carrier Detect Signal, Data
Central Processing Unit
Character Attributes
Circuit:
Battery .
Reset
Clear-to-Send Signal
Clock Generation, CPU
Clock Line, Keyboard
Clock, Real-Time
Code Definitions, Diagnostic
Codes, Tape position
Color
Combinations
Graphics
Latches .
Map .
Mode
Select Register
Selection
Color Display Unit
AC Power Requirements
Color Map
Combinations
Controller Interface Signals
Kit .
Performance Specifications
Tabulated Information
Video AC Parameters .
Color Latch .
Byte
Color/Graphics
Mode
Monitor Adapter I/O Addresses
Command:
Acknowledge .
Break Code Prefix
Default Disable .
Diagnostic Failure
Echo
Echo Response
Enable
2241092-0001
Index-3
Index
Tl-l
4.1
6.3
1.1
6.1
Tl-l
Tl-l
1.1
1.3, 1.4, Tl-l
T6-68
2.6.5.3
1.2.1.1,2.2
6.4.1.2, 6.4.1.6
2.6.2.1
2.2.5
.2. 6 . 5 . 1
2.2.4
4.3.1
2.6.2, 2.6.2.3
T6-2l
T6-47
. 6.4.1.2
6.4.1.4, T6-66
T6-78
T6-69
T6-64
6.4.1.6
T6-8l
6.4.1.4
6.4 .. 2
T6-89
T6-85
T6-66
T6-84
6.4.2.1
T6-88
6.4.2.2
T6-86
6.4.1.4
T6-68
6.4.1.7
TB-2l, TC-2l
4.6.5
4.6.4
4.5.7
4.6.6
4.5.3
4.6.3
4.5.6
Index
BUSINESS-PRO Hardware Reference
No Operation
4.5.4
Overrun .
4.6.1
Read Data
.5.1.2. 2
Read Deleted Data
5.1.2.2
Resend
4.5.9, 4.6.7
Reset
4.5.10
Self-Test OK
4.6.2
Set Default .
4.5.8
Set Key Click Volume
4.5.1
Set Typamatic Delay
4.5.5
Set Typamatic Rate
4.5.5
Turn Mode Indicator LEDs On/Off
4.5.2
write Data
5.1.2.2
Commands:
Controller
· 5.1.2.2
Keyboard
.2. 6 . 3 . 3
Keyboard-to-System
4.6
System-to-Keyboard
. 4.5
Winchester Controller
T6-22
Communication Ports I/O Addresses
TB-I0, TC-I0
Communications
1. 2.5
Compatibility:
BUSINESS-PRO
T6-70
TIPC
6.4.1.5, T6-70
Computer, PRO-LITE
· 5.1.1.1
Configurations:
Controller
.6.4.1.7
Keyboard
4.7
Two-Drive Controller
F6-2, F6-3
Configuring:
21-Megabyte Disk Drive
6.3
40-Megabyte Disk Drive
· 6. 3 . 7 . 3
72-Megabyte Disk Drive
• 6. 3' . 8 . 3
120-Megabyte Disk Drive
6.3.9.3
Connector:
Keyboard
F4-1
Keyboard/Mouse
T6-87, T6-93
6.4.2.4, 6.4.3.4
Keyboard/Mouse Cable
Light Pen Enable
T6-74
Main Logic Board Power
F3-1
TI Mode RS-232 Serial Interface
T6-96
Winchester Disk Controller Control
T6-12, T6-13
Winchester Disk Controller Data. T6-14, T6-15, T6-16, T6-17
T6-4
1.2-Megabyte Floppy Disk Drive Power
T6-26
21-Megabyte Disk Drive Control
T6-27
21-Megabyte Disk Drive Data .
T6-28
21-Megabyte Disk Drive Power
T6-3l
40-Megabyte Disk Drive Control
T6-32
40-Megabyte Disk Drive Data .
T6-33
40-Megabyte Disk Drive Power
T6-36
72-Megabyte Disk Drive Control
T6-37
72-Megabyte Disk Drive Data .
T6-38
72-Megabyte Disk Drive Power
Index-4
2241092-0001
BUSINESS-PRO Hardware Reference
Index
120-Megabyte Disk Drive Control .
120-Megabyte Disk Drive Data
120-Megabyte Disk Drive Power
360-Kilobyte Floppy Disk Drive Power
Connectors, Main Logic Board
Control:
CPU Bus .
I/O-Read
I/O-Write
Logic
Memory-Read
Memory-Write
Register, Fixed Disk
Signals .
Wait-State
Control Connector:
Winchester Disk Controller
21-Megabyte Disk Drive
40-Megabyte Disk Drive
72-Megabyte Disk Drive
120-Megabyte Disk Drive
Control Logic:
Memory
Wait-State
Controller:
Block Diagram Floppy Disk
Command Functions
Commands
Winchester
Configuration, Two-Drive
Configurations
CRT .
T6-41
T6-42
T6-43
T6-8
. 2.1
DMA •
Floppy Disk .
IC, Floppy Disk
Interface, Floppy Disk
PC-AT Mode CRT
Refresh .
System Addresses
Tape
TI Mode CRT .
Winchester Disk
Controller Functional Block Diagram, Winchester .
Controller Stepping Rates
Controllers, Video
Coprocessor:
I/O Addresses
Numeric .
CPU Bus:
Buffering
Control .
2241092-0001
Index-5
2.2.4
2.2.6
2.2.6
· 5.1.1.2
2.2.6
2.2.6
F6-8
2.2.6
. 2.3
T6-12, T6-13
T6-26
T6-31
T6-36
T6-41
2.5
2.3
F5-1
6.3.4.2
· 5.1.2.2
T6-22
F6-2, F6-3
· 6.4.1.7
· 6.4.1.2
2.5!1
5.1, 5.1.1
· 5.1.1.2
· 5.1.1.1
· 6.4.1.6
· 2.5.1.1
6.3.4
6.3.10.3
· 6.4.1.1
6.3.3
F6-1
T6-23
6.4.1
TB-ll, TC-ll
. 6. 7
2.2.3
2.2.4
Index
BUSINESS-PRO Hardware Reference
..
CPU Clock Generation
CPU Data Bus Control PAL Programming Table
CRT:
Controller
System Memory Map
Timing
CRTC Programming Values .
Cycle:
Four-Wait-State .
One-Wait-State I/O .
One-Wait-State Memory
Processor-Driven
Ten-Wait-State
Zero-Wait-State Memory .
Cycle Timing, Processor-Driven
Cycles, Shutdown
Data Bus Buffering
Data Carrier Detect Signal
Data Connector:
Winchester Disk Controller
21-Megabyte Disk Drive
40-Megabyte Disk Drive
72-Megabyte Disk Drive
120-Megabyte Disk Drive .
Data Format, Mouse
Data Frame Format, Keyboard .
Data Line, Keyboard .
Data Registers
Data Separators .
Data Terminal Ready Signal
Data Transfers, Keypoard
Data-Set Ready Signal
Decode Logic, Address
Default Command, Set
Default Conditions, Keyboard
Default Disable Command
Definitions:
Diagnostic Code .
Diagnostic Register Bit
Error Register Bit
Register Bit
Symbol
Diagnostic:
Code Definitions
Failure Command
Indicators, Tape Controller
Loopback
Register
Register Bit Definitions
Diagram:
Disk Drive Interface
Index-6
2.2.4
TD-7
6.4.1.1, 6.4.1.2
T6-62
6.4.1.8, T6-83
T6-63
2.3.4
2.3.3
2.3.2
F2-4
2.3.5
2.3.1
F2-4
· 2.2.5.1
· 2.2.3.2
2.6.5.3
T6-14, T6-15, T6-16, T6-17
T6-27
T6-32
T6-37
T6-42
T6-101
F4-2
4.3.2
5.1.2.1
5.1.1.2
· 2.6.5.5
· 2.6.3.1
· 2.6.5.2
· 5.1.1.2
4.5.8
T4-1
4.5.7
T6-21
F6-9
F6-5
F6-6, F6-7
T5-9
T6-21
4.6.6
T6-53
· 6.4.1.3
T5-7
F6-9
F5-2
2241092-9001
BUSINESS-PRO Hardware Reference
Winchester Controller Functional Block
Winchester Disk Controller
Digital Output Register .
Disk Drive:
BUSINESS-PRO
Interface Diagram
Pinouts .
Power Connector .
Specifications
Register, Floppy
1.2-Megabyte Floppy.
21-Megabyte Winchester
40-Megabyte Winchester
360-Kilobyte Floppy .
Disk Drive Control Register, Fixed
Disk Drive Controller:
Block Diagram Floppy
Configuring 21-Megabyte .
Configuring 40-Megabyte .
Configuring 72-Megabyte .
Configuring 120-Megabyte
Floppy
IC
Interface
Select Pins, 120~Megabyte
Switches, 40-Megabyte
Terminator, 40-Megabyte .
Terminator, 120-Megabyte
Types, Winchester
Winchester
1.2-Megabyte
360-Kilobyte
Diskette Controller I/O Addresses
Display Characteristics .
Display Unit:
Color
Monochrome
DMA Controller
Channel Uses
Page Register I/O Addresses
Refresh Arbiter .
1 I/O Addresses .
2 I/O Addresses .
Dot Clock
Drive, Tape .
Dual-Mode Refresh Generator PAL Programming Table
F6-1
6.3.3.2
T5-5
T6-24
F5-2
T3-5
F3-3, F3-4
T3-6
T5-B
6.3.1
6:3.6
6.3.7
6.3.2
F6-B
F5-1
• 6. 3 • 6 . 3
· 6.3.7.3
· 6.3.B.3
6.3.9.3
5.1, 5.1.1
· 5.1.1.2
· 5.1.1.1
F6-12
F6-11
F6-11
F6-12
T6-25
6.3.5, 6.3.5.1
5.1.1
5.1.1
TB-22, TC-22
· 6.4.1.2
1.2.3
6.4.2
6.4.3
2.5.1
TA-4
TB-7, TC-7
· 2.5.1.1
TC-l
TC-9
· 6.4.1.4
.6.3.10.2
TD-I0
4.5.3
4.6.3
Echo Command
Echo Response Command
2241092-0001
Index
Index-7
BUSINESS-PRO Hardware Reference
Index
Enable:
Command .
Connector, Light Pen
Environmental Requirements, BUSINESS-PRO
Error Register Bit Definitions
EtherLink
Expansion:
RAM •
Slots
Expansion Bus
Board Power Connector
Board Power Connector Pinouts
Interface
Interface Signals
Features:
Tape Drive
1.2-Megabyte Floppy Disk Drive
Fixed Disk
Control Register
I/O Addresses
Floppy Disk Controller
Block Diagram
IC
Interface
Floppy Disk Register
Floppy System, Single-Drive .
Format:
Keyboard Data Frame .
Mouse Data
Four-Wait-State Cycle
Generation:
Baud Rate
CPU Clock
Generation Logic, Memory Cycle
Graphics
Color
Screen Memory
4.5.6
T6-74
Tl-l
F6-5
1.2.5
. 6.2
. 1.2.1.5
F3-2
T3-4
2.7
2.7, T2-9
6.3.10.2
. 6.3.1.1
F6-8
.TB-13, TC-13
5.1, 5.1.1
F5-1
5.1.1.2
5.1.1.1
T5-8
1.3.1
F4-2
T6-101
2.3.4
6.5.3
2.2.4
· 2.5.1.3
1.2.6, 6.4.1.2
T6-78
T6-65
Handshaking Protocols, Hardware .
Horizontal Blanking .
. 4.4
· 6.4.1.2
IC, Floppy Disk Controller
Indicator, External Activity
Indicators, Keyboard Mode
Intensity Levels
Monochrome Display Unit
Interface:
Expansion Bus
· 5.1.1.2
· 6. 3 . 3 . 4
4.1. 4
· 6.4.1.2
T6-91
. 2. 7
Index-8
2241092-0001
BUSINESS-PRO Hardware Reference
Floppy Disk Controller
I/O .
Keyboard
TI Mode RS-232 Serial
Interface Signals:
Color Display Unit/Controller
Monochrome Display Unit/Controller
Optical Mouse
PC-AT Mode Controller/Monitor
PC-AT Mode CRT Controller Expansion .
PC-AT Mode/TI Mode Controller
Tape Controller/Expansion Bus
Tape Drive
TI Mode CRT Controller Expansion
TI Mode CRT Controller/Monitor
TI Mode/PC-AT Mode Controller
1.2-Megabyte Floppy Disk Drive
128-Kilobyte RAM Expansion Kit
512-Kilobyte RAM Expansion Kit
Internal Registers
Interrupt:
Acknowledge .
Levels
System
Interrupt Controller I/O Addresses
I/O:
Cycle, One-Wait-State
Interface
Port Addresses
Port Addresses Map
Port Descriptions
Ports, Keyboard Interface
Read Control
Write Control
Subsystem
I/O Addresses
Alternate Diskette Controller
Alternate Fixed Disk
Bisynchronous 1 .
Bisynchronous 2 .
Color/Graphics Monitor Adapter
Communication Ports
Coprocessor .
Diskette Controller
DMA Controller 1
DMA Controller 2
DMA Page Register
Fixed Disk
Interrupt Controller
Keyboard
Master Interrupt Controller .
2241092-0001
Index-9
Index
5.1. 1.1
5.1.1.2
2.6.3
• 6. 5
T6-84
T6-90
T6-100
T6-71
T6-73
T6-72
T6-51
T6-46
T6-59
T6-57
T6-58
T6-3
6.2.1.1
. 6.2.2.1
5.1.2.1
2.2.6
2.6.7.1, T2-8
2.6.7
TB-3
2.3.3
5.1.1.2
5.1.2.1, T6-20
T5-4
6.3.4.1
2.6.3.4
2.2.6
2.2.6
. 2.6
T6-77, T6-78
TB-16, TC-16
TB-12, TC-12
TB-19, TC-19
TB-18, TC-18
TB-21, TC-21
TB-IO, TC-I0
TB-ll, TC-l1
TB-22, TC-22
TC-l
TB-9, TC-9
TB-7, TC-7
TB-13, TC-13
TB-3
TB-5, TC-5
TC-4
BUSINESS-PRO Hardware Reference
Index
Mode Select .
Monochrome Display
NMI Mask
.
Parallel Printer Port I .
Parallel Printer Port 2 .
Printer.
.
Real-Time Clock .
Serial Port I
Serial Port 2 .
.
Slave Interrupt Controller
TI Mode DMA .
TI Mode LED .
TI Mode Timer
8254-2 Timer
I/O Cycle, One-Wait-State
I/O Decode Logic
....
I/O Decode Logic PAL Programming Table
TB-2, TC-2
TB-20, TC-20
TB-6, TC-6
TB-17, TC-17
, TB;..,14, TC-14
TB-20, TC-20
TB-6, TC-6
TB-23, TC-23
TB-IS, TC-15
TB-8, TC-8
TB-l
TB-l
TB-l
TB-4
2.3.3
2.6.1
TD-3, TD-4, TD-S
Jumper Settings:
Tape Controller .
1.2-Megabyte Floppy Disk Drive
360-Kilobyte Floppy Disk Drive
Key Click
Keyboard
Basic Assurance Self-Test
Buffer
BUSINESS-PRO
Clock Line
Commands
.
Configurations
Connector
.
Connector Signals
Data Frame Format
Data Line
Data Transfers .
Default Conditions
Interface
Interface I/O Ports .
I/O Addresses
.
Mode Indicators .
Operations
Periodic Self-Test
Power-Up Sequence
Self-Tests
Signals .
Transmission
Aborted .
Inhibited
Transmission Process .
Transmission Timing
Index.-10
T6-52
T6-5
T6-9
.
.
4.l. 3
l. 2.2
· 4.2.l.l
4.l. 5
4.1
4.3.1
· 2.6.3.3
4.7
F4-l
T4-2
F4-2
4.3.2
· 2.6.3.1
T4-l
2.6.3
· 2.6.3.4
TB-5, TC-5
4.l. 4
4.2
· 4.2.l.2
4.2.2
4.2.1
2.6.3
4.4.1
· 4.4.l.2
· 4.4.l.3
.4.4.l.1
F4-5
224109:2-0001
BUSINESS-PRO Hardware Reference
Keyboard Interface
I/O Ports
Keyboard-to-System Commands
Keyboard/Mouse Connector
Keyboard/Mouse Cable Connector
Keycode Map .
Kit:
Color Display Unit
Monochrome Display Unit
Optical Mouse
PC-AT Mode CRT Controller
Tape Drive
TI Mode CRT Controller
TI Mode RS-232 Serial Interface
Winchester Disk Controller
1.2-Megabyte Floppy Disk Drive
21-Megabyte Winchester Drive
40-Megabyte Winchester Disk Drive
72-Megabyte Winchester Disk Drive
120-Megabyte Winchester Disk Drive
128-Kilobyte RAM Expansion
360-Kilobyte Floppy Disk Drive
512-Kilobyte RAM Expansion
Latches, Color
Light Pen:
Enable Connector
Ports
Line:
Keyboard Clock
Keyboard Data
Local Area Networks
Logic:
Address Decode
Control .
I/O Decode
Memory Control
Memory Cycle Generation
Parity Error
Wait-State Control
Loopback
2.6.3
.2.6.3.4
4.6
T6-87, T6-93
6.4.2.4, 6.4.3.4
T4-2
6.4.2.1
6.4.3.1
6.6.1
6.4.1.6
6.3.10.1
6.4.1.1
6.5.1
6.3.3.1
6.3.1.2
6.3.6.1
6.3.7.1
. 6.3.8.1
. 6.3.9.1
6.2.1
6.3.2.1
6.2.2
T6-69
T6-74
6.4.1.7
4.3.1
4.3.2
1.1. 2
5.1.1.2
5.1.1.2
2.6.1
. 2.5
2.5.1.3
2.5.1.4
. 2.3
6.4.1.3
Main Status Register
Main Logic Board
Block Diagram
Connectors
Power Connector
Power Connector Pinouts
Switches
Main Memory Control PAL Programming Table
2241092-0001
Index
Index-l1
T5-6
1.3.3.1
F2-1
2.1
F3-1
T3-3
2.6.3
TD-ll
Index
BUSINESS-PRO Hardware Reference
Map:
Color
Color Display Unit Color
Keycode .
Mass Storage Options, BUSINESS-PRO
Mass Storage System .
Master Interrupt Controller I/O Addresses
Memory:
Control Logic
Graphics Screen
I/O Control PAL Programming Table
Page Register
Read Control .
System
Write Control
Memory Cycle:
Generation Logic
One-Wait-State
Memory Map:
System (CRT).
System (Real Mode)
System (Virtual/Protected Mode) .
Microprocessor Unit
Mode:
Color
Color/Graphics
Indicators, Keyboard
Monochrome
Operational
Select I/O Addresses
TI
Monochrome Display Unit:
AC Power Requirements
Controller Interface Signals
Intensity Levels
I/O Addresses
Kit .
Performance Specifications
.
Tabulated Information
Video AC Parameters
Mouse:
Data Format .
Optical .
Multiuser Applications
T6-64
T6-85
T4-2
6.3
. 1.2.1.4
TC-4
2.5
T6-65
TD-2
2.5.1
2.2.6
2.4
2.2.6
2.5.1.3
2.3.2
T6-62
TA-l
TA-2
2.2.1
,
6.4.1.6
6.4.1.7
4.1. 4
6.4.1.6,6.4.1.7
6.4.1.7
TB-2, TC-2
. 6.4.1.2
6.4.3
T6-95
T6-90
T6-9l
TB-20, TC-20
6.4.3.1
T6-94
6.4.3.2
T6-92
T6-l0l
1.2.4, 6.6
1.1. 3
1.1. 2
TB-6, TC-6
4.5.4
6.4.1.2
2.6.2, 2.6.2.2
• 6. 7
4.1. 2
Networks, Local Area
NMI Mask I/O Addresses
No Operation Command
Nonmaskable Interrupt
Nonvolatile RAM .
Numeric Coprocessor
N-Key Rollover
Index-12
2241092-0001
BUSINESS-PRO Hardware Reference
One-Wait-State:
I/O Cycle
Memory Cycle
Operating Systems, BUSINESS-PRO Computer
Operational Modes
Operations, Keyboard
Optical Mouse
Interface Signals
Kit .
Performance Specifications
Tabulated Information
Options:
BUSINESS-PRO
BUSINESS-PRO Mass Storage
Selectable
Video
Overrun Command
Index
2.3.3
2.3.2
1.1
· 6.4.1.7
4.2
1.2.4, 6.6
T6-l00
6.6.1
T6-l02
6.6.2
6.1
6.3
T6-76
6.4
4.6.1
Page Register, Memory
2.5.1
Palette .
6.4.1.4
Palette Numbers .
· 6.4.1.4
Parallel Printer Port
1.2.1.3, 2.6.4
Signals
T2-5
TB-17, TC-17
1 I/O Addresses
TB-14, TC-14
2 I/O Addresses
Parity Control PAL Programming Table
TD-12
Parity Error Logic
.2.5.1. 4
PC-AT Compatible Timer
· 2.6.6.2
PC-AT Mode Controller/Monitor Interface Signals .
T6-7l, T6-72
6.4.1.6
PC-AT Mode CRT Controller
Kit .
6.4.1.6
Expansion Interface Signals
T6-73
T6-75
Specifications
T6-7l, T6-72
TI Mode Controller Interface Signals .
T6-29
Performance Specifications, 2l-Megabyte Disk Drive
Tl-l
Physical Dimensions, BUSINESS-PRO
Pinouts:
T3-5
Disk Drive Power Connector
T3-4
Expansion Bus Board Power Connector
T3-3
Main Logic Board Power Connector
6.4.1.2, T6-65
Pixels
Port:
Addressing
· 6.4.1.4
T5-4
Address Map, I/O
5.1. 2 . 1, T6-20
Addresses, I/O
6.3.4.1
Descriptions, I/O
2.6.3.4
Keyboard Interface I/O
Light Pen
· 6.4.1.7
1.2.1.3
Parallel
2.6.4
Parallel Printer
2241092-0001
Index-13
Index
BUSINESS-PRO Hardware Reference
Serial
Status
Video
Port-Selection Switches
Power Connector:
Disk Drive
Expansion Bus Board .
Main Logic Board
Tape Drive
21-Megabyte Disk Drive
40-Megabyte Disk Drive
72-Megabyte Disk Drive
120-Megabyte Disk Drive .
360-Ki1obyte Floppy Disk Drive
Power Requirements:
BUSINESS-PRO
Monochrome Display Unit AC
Tape Controller .
Tape Drive
1.2-Megabyte Floppy Disk Drive
21-Megabyte Disk Drive
40-Megabyte Disk Drive DC
72-Megabyte Disk Drive DC
360-Ki1obyte Floppy Disk Drive
Power Supply, System
Output Voltages
Power-Up Sequence, Keyboard .
Precompensation, Write
Printer I/O Addresses
Processor-Driven Cycle
Timing
Programming Table:
CPU Data Bus Control PAL
Dual-Mode Refresh Generator PAL
I/O Decode Logic PAL
.
Main Memory Control PAL .
Memory and I/O Control PAL
Parity Control PAL
Refresh Arbiter PAL .
Refresh Sequence Control PAL
Reset/Ready Control PAL .
Serial/Parallel Port Decode PAL .
Programming Values, CRTC
Protocols, Hardware Handshaking .
PRO-LITE Computer
1.2.1.3, 2.6.5
6.4.1.7, T6-82
.6.4.1.7
T6-97
F3-3, F3-4
F3-2
F3-1
T6-48
T6-28
T6-33
T6-38
T6-43
T6-8
T1-1
T6-95
T6-56
T6-50
T6-7
T6-30
T6-35
T6-40
T6-11
. 1.3.3.3
T3-1
4.2.2
. 5.1.1.2
.TB-20, TC-20
F2-4
F2-4
TD-7
TD-IO
TD-3, TD-4, TD-5
TD-11
TD-2
TD-12
TD-8
TD-9
TD-l
TD-6
T6-63
4.4
. 5.1.1.1
RAM:
Expansion
Expansion Signals
Nonvolatile .
. 6.2
.
.
T2-3
2.6.2, 2.6.2.2
Index-14
2241Q92-0001
Index
BUSINESS-PRO Hardware Reference
Raster Graphics .
Rate, Typamatic .
Rates, Controller Stepping
Read Data Command
Read Deleted Data Command
Real-Time Clock .
Addresses
I/O Addresses
Refresh Arbiter PAL Programming Table
Refresh Controller
Refresh Sequence Control PAL Programming Table
Register:
Color Select
Data
Diagnostic
Digital Output
Fixed Disk Control
Floppy Disk .
Internal
Main Status .
Memory Page .
Status
Tape Controller .
Register Bit Definitions
Diagnostic
Error
Request-to-Send Signal
Requirements:
l.2-Megabyte Floppy Disk Drive Power
21-Megabyte Disk Drive Power
Resend Command
Reset:
Circuit .
Command .
Software
System
Reset/Ready Control PAL Programming Table
Resolution
.
Ring Indicator Signal
Rollover, N-Key .
ROMs, System
RS-232 Serial Interface .
Scan Rate
Screen/CPU Arbitration
Scrolling
Sector Buffer
Select Register, Color
Select Pins, 120-Megabyte Disk Drive
Selectable Options
2241092-0001
Index-IS
· 6.4.1.2
T4-3
T6-23
· 5.1.2.2
· 5.1.2.2
2.6.2, 2.6.2.3
T2-4
TB-6, TC-6
TD-8
· 2.5.1.1
TD-9
T6-81
· 5.1.2.1
T5-7
T5-5
F6-8
T5-8
· 5.1.2.1
T5-6
2.5.1
· 5.1.2.3
T6-54
F6-6, F6-7
F6-9
F6-5
· 2.6.5.6
T6-7
T6-30
4.5.9, 4.6.7
·
·
·
·
·
·
·
·
2.2.5
4.5.10
2.2.5.1
2.2.5.2
TD-l
6.4.1.2
2.6.5.4
4.1. 2
2.4.2
1. 2.5
6.4.1.2
6.4.1.2
6.4.1.2
6.3.4.1
T6-81
F6-12
T6-76
Index
BUSINESS-PRO Hardware Reference
Self-Test:
Keyboard
Keyboard Basic Assurance
Keyboard Periodic
OK Command
Separators, Data
Sequence, Keyboard Power-Up
Serial Interface, RS-232
Serial Port .
Signals
1 I/O Addresses
2 I/O Addresses
Serial/Parallel Port Decode PAL Programming Table
Set Default Command .
Set Key Click Volume Command
Set Typamatic Delay Command .
Set Typamatic Rate Command
Shutdown Cycles .
Signals:
Clear-to-Send
Color Display Unit/Controller Interface
Control .
Data Carrier Detect
Data Terminal Ready
Data-Set Ready
Expansion Bus Interface
Keyboard Connector
Keyboard Interface
Monochrome Display Unit/Controller Interface
Optical Mouse Interface .
Parallel Printer Port
PC-AT Mode Controller/Monitor Interface
PC-AT Mode CRT Controller Expansion Interface
PC-AT Mode/TI Mode Controller Interface
RAM Expansion
Request-to-Send .
Ring Indicator
Serial Port .
Tape Controller/Expansion Bus Interface
Tape Drive Interface
TI Mode CRT Controller Expansion Interface
TI Mode CRT Controller/Monitor Interface
TI Mode/PC-AT Mode Controller Interface .
1.2-Megabyte Floppy Disk Drive Interface
128-Kilobyte RAM Expansion Kit Interface
512-Kilobyte RAM Expansion Kit Interface
Single-Drive Floppy System
Slave Interrupt Controller I/O Addresses
Slots, Expansion
Software:
BUSINESS-PRO Computer
Reset
Index-16
4.2.1
. 4.2.1.1
4.2.1, 4.2.1.2
4.6.2
5.1.1.2
4.2.2
1. 2.5
1.2.1.3, 2.6.5
T2-7
TB-23, TC-23
TB-15, TC-15
TD-6
4.5.8
4.5.1
4.5.5
4.5.5
2.2.5.1
2.6.5.1
T6-84
2.2.6
2.6.5.3
2.6.5.5
2.6.5.2
2.7, T2-9
T4-2
2.6.3
T6-90
T6-100
T2-5
T6-71
T6-73
T6-72
T2-3
2.6.5.6
2.6.5.4
T2-7
T6-51
T6-46
T6-59
T6-57
T6-58
T6-3
. 6.2.1.1
. 6.2.2.1
1. 3.1
TB-8, TC-8
1.2.1.5
. 1.1
2.2.5.1
2241092-0001
BUSINESS-PRO Hardware Reference
Specifications:
BUSINESS-PRO
Color Display Unit Performance
Disk Drive Power Connector
Monochrome Display Unit Performance .
Optical Mouse Performance
PC-AT CRT Controller
Tape Controller Performance
Tape Drive Performance
TI Mode CRT Controller Performance
Winchester Disk Controller
1.2-MegabyteF1oppy Disk Drive
21-Megabyte Disk Drive Performance
40-Megabyte Disk Drive Performance
72-Megabyte Disk Drive Performance
120-Megabyte Disk Drive Performance
360-Ki1obyte Floppy Disk Drive
512-Ki1obyte RAM Expansion Kit
Standard Configurations, BUSINESS-PRO Computer
Status:
Port
Register, Main
Registers
Subsystem, I/O
Switches:
Main Logic Board
Port-Selection
40-Megabyte Disk Drive
Symbol Definitions
Synchronization, Tim}ng and .
System:
Addresses, ContrQ11er
Interrupt
I/O Maps
Mass Storage
Memory
Memory Map, CRT .
Memory Map (Real M.ode)
Memory Map (Virtual/Protected Mode)
Power Supply
Reset
ROMs
Single-Drive Floppy
Tape
Unit
Unit Enclosure
Winchester
System Unit-to-Keyboard:
Commands
Transmission
Transmission Timing .
2241092-0001
Index-17
Index
1.4, T1-1
T6-88
T3-6
T6-94
T6-102
T6-75
T6-55
T6-49
T6-60
T6-19
T6-6
T6-29
T6-34
T6-39
T6-44
T6-10
6.2.2.2
· 1. 3
6.4.1.7, T6-82
T5-6
5.1.2.3
· 2.6
2.6.3
T6-97
F6-11
T5-9
· 6.4.1.4
6.3.4
2.6.7
TA-3
· 1.2.1.4
· 2.4
T6-62
TA-1
TA-2
· 1.3.3.3
· 2.2.5.2
2.4.2
1. 3.1
6.3.10
1. 2.1
1. 3.3
1.3.2
4.5
4.4.2
F4-6
Index
BUSINESS-PRO Hardware Reference
Tabulated Information:
Color Display Unit
Monochrome Display Unit
Optical Mouse
Tape Drive
TI Mode CRT Controller
TI Mode RS-232 Serial Interface
Winchester Disk Controller
1.2-Megabyte Floppy Disk Drive
21-Megabyte Disk Drive
40-Megabyte Disk Drive
72-Megabyte Disk Drive
120-Megabyte Disk Drive
360-Ki1obyte Floppy Disk Drive
Tape Controller:
Drive
Diagnostic Indicators
Expansion Bus Interface Signals
Jumper Settings .
Performance Specifications
Power Requirements
Registers
System
Tape Drive:
Features
Interface Signals
Kit .
Performance Specifications
Power Connector .
Power Requirements
Tabulated Information
Tape Position Codes .
Ten-Wait-State Cycle
Terminator:
40-Megabyte Disk prive
120-Megabyte Disk ~rive
TI Mode .
TI Compatible Timer .
TI Mode CRT Contro11~r
Expansion Interface Signals .
Kit .
Monitor Interface Signals
PC-AT Mode Controller Interface Signals .
Performance Specifications
Tabulated Information
TI Mode DMA and LED 1/0 Addresses
TI Mode RS-232 Serial Interface .
Connector
Kit .
Programmable Baud Rate Values
Tabulated Information
Index-18
6.4.2.2
· 6. 4 . 3 . 2
6.6.2
6.3.10.2
· 6.4.1.1
6.5.2
· 6. 3 . 3 . 3
· 6.3.1.3
· 6.3.6.2
6.3.7.2
6.3.8.2
6.3.9.2
· 6. 3 . 2 . 2
6.3.10.3
6.3.10.2
T6-53
T6-51
T6-52
T6-55
T6-56
T6-54
6.3.10
6.3.10.2
T6-46
6.3.10.1
T6-49
T6-48
T6-50
6.3.10.2
T6-47
2.3.5
F6-11
F6-12
· 6.4.1.2
2.6.6.1
· 6. 4 . 1 . 1
T6-59
· 6. 4 . 1 . 1
T6-57
T6-58
T6-60
6.4.1.1
TB-l
6.5
T6-96
6.5.1
T2-6
6.5.2
2241092-0001
BUSINESS-PRO Hardware Reference
TI Mode Timer I/O Addresses
Timer:
PC-AT Compatible
TI Compatible
Timing:
CRT .
Keyboard Transmission
Processor-Driven Cycle
Services
System Unit-to-Keyboard Transmission
Timing and Synchronization
TIPC Compatibility
Transfers, Keyboard Data
Transmission:
Aborted Keyboard
Inhibited Keyboard
Keyboard
Process, Keyboard
System Unit-to-Keyboard
Timing, Keyboard
Typamatic
Turn Mode Indicator LEDs On/Off Command
Two-Drive Controller Configuration
Typamatic:
Rate
Transmission
Units:
Central Processing
Color Display
Display
Microprocessor
Monochrome Display
System
TB-l
2.6.6.2
2.6.6.1
6.4.1.8, T6-83
F4-5
F2-4
2.6.6
F4-6
6.4.1.4
6.4.1.5, T6-70
2.6.3.1
4.4.1.2
4.4.1.3
4.4.1
4.4.1.1
4.4.2
F4-5
4.1.1
4.5.2
F6-2, F6-3
T4-3
4.1.1
1.2.1.1, 2.2
6.4.2
1. 2.3
2.2.1
6.4.3
1. 2.1
Values, CRTC Programming
Vertical Blanking
Video:
AC Parameters
Controllers
Memory
Options .
Port
Video AC Parameters, Color Display Unit
Volume, Key Click
Wait-State:
Control
Control Logic
2241092-0001
Index
T6-63
6.4.1.2
T6-6l
6.4.1
6.4.1.2
6.4
6.4.1.7
T6-86
4.1. 3
2.3
2.3
Index-19
Index
BUSINESS-PRO Hardware Reference
Winchester Disk Controller
Commands
Control Connector
Data Connector
Diagrams
Functional Block Diagram
Kit .
Specifications
Tabulated Information
Winchester Disk Drives
Types
System
Workstation Applications
Write Precompensation
Write Data Command
6.3.3
T6-22
T6-12, T6-13
T6-14, T6-15, T6-16, T6-17
6.3.3.2
F6-1
6.3.3.1
T6-19
6.3.3.3
6.3.5, 6.3.5.1
T6-25
1. 3.2
1.1.1
5.1.1.2
5.1.2.2
Zero-Wait-State Memory Cycle
2.3.1
1.2-Megabyte Floppy Disk Drive
Features
Interface Signals
Jumper Settings
Kit .
Power Connector
Power Requirements
Specifications
Tabulated Information
21-Megabyte Disk Drive
Configuring .
Control Connector
Data Connector
Kit
Performance Specifications
Power Connector .
Power Requirements
Tabulated Informati.on
40-Megabyte Disk Drive
Configuring .
Control Connector
Data Connector
DC Power Requirements
Kit
Performance Specifications
Power Connector .
Switches
Tabulated Information
Terminator
72-Megabyte Winchester Disk Drive
Configuring .
Control Connector
Data Connector
DC Power Requirements
Index-20
5.1.1, 6.3.1, T6-3
6.3.1.1
T6-3
T6-5
6.3.1.2
T6-4
T6-7
T6-6
6.3.1.3
6.3.6
6.3.6.3
T6-26
T6-27
6.3.6.1
T6-29
T6-28
T6-30
6.3.6.2
6.3.7
6.3.7.3
T6-31
T6-32
T6-35
6.3.7.1
T6-34
T6-33
F6-11
6.3.7.2
F6-11
6.3.8
6.3.8.3
T6-36
T6-37
T6-40
2241092-0001
BUSINESS-PRO Hardware Reference
Kit
Performance Specifications
Power Connector .
Tabulated Information
120-Megabyte Disk Drive .
Configuring
Control Connector
Data Connector
Kit
Performance Specifications
Power Connector .
Select Pins
Tabulated Information
Terminator
128-Kilobyte RAM Expansion Kit
Interface Signals
Specifications
360-Kilobyte Floppy Disk Drive
Jumper Settings
Kit .
Power Connector .
Power Requirements
Specifications
Tabulated Information
512-Kilobyte RAM Expansion Kit
Interface Signals
Specifications
8254-2 Timer I/O Addresses
2241092-0001
Index-21
Index
6.3.8.1
T6-39
T6-38
6.3.8.2
6.3.9
· 6.3.9.3
T6-41
T6-42
· 6.3.9.1
T6-44
T6-43
F6-12
6.3.9.2
F6-12
6.2.1
6.2.1.1
6.2.1.2
5.1.1, 6.3.2
T6-9
6.3.2.1
T6-8
T6-ll
T6-l0
6.3.2.2
6.2.2
· 6.2.2.1
· 6.2.2.2
TB-4
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USER'S RESPONSE SHEET
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