227 5631 0_IBM_1620_Customer_Engineering_Instructional_System_Diagrams_1962 0 IBM 1620 Customer Engineering Instructional System Diagrams 1962

227-5631-0_IBM_1620_Customer_Engineering_Instructional_System_Diagrams_1962 227-5631-0_IBM_1620_Customer_Engineering_Instructional_System_Diagrams_1962

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Customer Engineering
Instructional
System Diagrams

r~ CrJ) InI

lJ ~ b JJJ

Data Processing System

Issued to: _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Branch Office: _ _ _ _ _ _ _ _ _ _ _ _ _ __
Department: _ _ _ _ _ _ _ _ _ _ _ _ _ __
Address: _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

If this manual is misplaced, it should
be returned to the above address.

~rn~

Customer Engineering Instructional System Diagrams
1620 Data Processing System

© 1962 by International Business Machines Corporation

International Business Machines Corp., Product Publications Dept., San Jose, Calif.

1620 SYSTEM DIAGRAM INDEX
DESCRIPTION

DIAGRAM NUMBER

AC POWER DISTRIBUTION
ADD SUB COMP TRG NO 11
ADD SUB COMP TRG NO 12
ADD SUB COMP TRG NO 14
ADD SUB COMP SET/CLR FLAG
ADD SUB COMP
ADD SUB COMP FM 1/2 TRGS
AM TIMING PULSE TRANSMISSION
ARRAY DRIVE HALF SELECT

01.90.10.1
01.60.11. 1
01.60.12.1
01.60.14.1
01.60.20.1
01.60.22.1
01.63.30.1
01.41.03.1
01.30.06.1

BIPASS INCREMENT SWITCH POINT
BIPASS CARRY SW TO MAR UNITS
BIT CORRECTOR FROM MDR
BRANCH TRIGGER
BRANCH TRG GATES
BRANCH BACK CONTROLS
BSA BRANCH TRG NO 18
BUS & 4BV GATE C
BYPASS MAR INC FP

01.55.02.1
01.60.38.1
01.45.50.1
01.25.35.1
01.25.40.1
01.60.50.1
01.60.4B.l
01.00.33.1
01.5S.02.2

C BIT CORRECTORS MBR ODD EVEN BUS
C E PANEL-WIRING SIDE
CABLE CONNECTIONS
CARRY
CARRY IN/OUT TRGS
C E BOX DISPLAY LAMPS
C E SWITCH TRANSMISSION
CHANGE MODE
CIRCUIT BREAKER TIMING CHART-GATE C
CLOCK OSC & CONTROL
CLOCK Cl C2
CLOCK C3 C4
CLOCK C5 C6
CLOCK C7C8
CLOCKC9Cl0

01.40.50.1
01.05.50.1
01.00.25.1
01.60.36.1
01.63.40.1
01.05.60.1
01.41.01.1
01.68.00.1
01.00.36.1
OLlO.05.1
01.10.06.1
01.10.07.1
01.10.08.1
01.10.09.1
01.10.10.1
C .00.03.1
C .00.69.1
01.06.20.1
01.25.25.1
01.80.10.1
01.00.24.1
01.00.21.1
01.00.22.1
01.05.01.1
01.05.02.1
01.05.03.1
01.05.0S.1
01.05.10.1
01.06.01.1
01.06.02.1
01.06.03.1
01.06.05.1
01.06.10.1
01.06.11.1
01.06.15; 1
01.00.91. 1
01.16.10.1
01.62.39.1

COMPo'NENT CIRCUITS
CON CNTRL INS EXEC INS 1-2/CTRL
CONDITIONAL BR TEST
CONDITION SEL AND GATE CTRL
CONNECTOR REFERENCE SHEET GATE 0
CONNECTOR REFERENCE SHEET GATE A
CONNECTOR REFERENCE SHEET GATE B
CONSOLE SWITCHES
CONSOLE SWITCHES
CONSOLE SWITCHES
CONSOLE SWITCHES
CONSOLE CONTROL LAMPS
CONSOLE CONTROL MANUAL RESET
CONSOLE CONTROL MANUAL RESET
CONSOLE CONT ROL MANUAL RESET
CONS CNTRL STRT EXEC STRT/CTRL TRG
CONS CNTRL STP EXEC STP 1/2 TRGS
CONS CNTRL STP EXEC STP 1/2 T RGS
CONS CN'fRL SAVE
CONSOLE CONTROL LAMPS & SWITCHES
CONTROL TRIGGERS
CYC MULT TR 39 RD OUT ACC DIGIT
DATA CHECK TEST
DATAFLOW SCHEMATIC
DATAFLOW SCHEMATIC
DATAFLOW SCHEMATIC
DATAFLOW SCHEMATIC
DATAFLOW SCHEMATIC
DC DISTRIBUTION
DC SUPPLIERS & AC REGULATORS
DC SUPPLIE RS
DEC REG TENS 1-4 NO OP CTRL SEL
DECODE R REG UNITS
DECREMENT 2 SWITCH UNITS
DIG REG UNITS TENS GT PNT TO MARS
DIGIT/BRANCH REG SET;RESET CONTROL
DIGIT/IRANCH REG UNITS C,8,4 BITS
DIGIT/BRANCH REG UNITS 2,1, BITS
DIGIT/BRANCH REG TENS C,8,4 BITS
DIGIT/BRANCH REG TENS 2, I, BITS
DIGIT 1 RECORD MARK TRG
DIGIT FORCE MODE
DIGIT FORCE CONTROLS
DIGIT FORCE DIGIT CONTROL
DIODE T B & RC UNITS GATE C
DISCONNECT CONTROL
DISPLAY ADDRESS
DIVIDE OPTION OP DECODE
DIVIDE FLAG CONTROL
DIVIDE MODE
DIV-ADD
DUMMY TRG NO 21
DUMMY TRG NO 19

01.25.30.1
00.00.05.1
00.00.10.1
00.00.11. 1
00.00.12.1
00.00.13.1
01 .~0.30. 1
01.90.20.1
01.90.21.1
01.20.14.1
01.20.13.1
01.16.05.1
01.55.01.1
01.50.05.1
01.50.07.1
01.50.09.1
01.50.17.1
01.50.19.1
01.63.S0,1
01.66.90.1
01.66.91.1
01.66.92.1
01.00.35.1
01.BO.20.1
01.06.30.1
01.20.18.1
01.65.06.1
01.67.40.1
01.65.04.1
01.60.31.1
01.60.49.1

EDGE CONNECTORS GATES A & B
EQUAL/ZERO TRG
EXEC CYL
EXECUTE TRIGGERS 24, 25
EXPONENT ADD MODE
EXPONENT ADD CONTROLS
EXP ADD MODE MARS CONTROL
EXPONENT ADD EXIT
EXPONENT CHECK INDICATOR LATCH
EXPONENT MODIFY MODE
EXPONENT MODIFY EXIT
EXPONENT MODIFY ENTRY CONTROLS

01.00.20.1
01.60.41.1
01.60.08.1
01.68.24.1
01.66.10.1
01.66.11.1
01.66.12.1
01.66.19.1
01.68.90,1
01.66.80.1
01.66.81.1
01.66.82.1

DESCRIPTION

DIAGRAM NUMBER

EXPONENT MODIFY CONTROLS
EXPONENT MODIFY EXITCONTROLS
EXPONENT MODIFY EXIT CONTROLS
EXPONENT MODIFY REQUIRED
EXPONENT TRANSMIT MODE
EXPONENT TRANSMIT CONTROLS
EXPONENT UNDERFLOW LATCH

01.66.85.1
01.66.87.1
01.66.88.1
01.66.44.1
01.66.30.1
01.66.31.1
01.68.85.1

FALSE TRANSMIT MODE
FALSE TRANSMIT CONTROLS
FIRST DIV CYCLE LAST DIV CYC
FM TRIG DIVIDE CTRL
FP FUNCTION CHARTS PAGES 44-72
FLOATING POINT EXIT
FP FIELD MARK TRIGGERS EXTENDED
FP MARS READ WRITE DRIVERS
FP MAR ZERO DECODE
FP MULTIPLY MODE
FP RESET
FP TIMING PULSE GENERATION
FP TIMING PULSE POWERING
FRACTION ADD MODE
FRACTION ADD SIGN + WORD MARK CONT
FRACTION ADD EXIT
FRACTION COMPARE
FUSE PANEL & PWR SPL Y SEQUENCE
FUSE RELAY & EDGE CONNECTOR CHART PS
FUNCTION CHARTS PAGES 7-43

01.67.20.1
01.67.21. 1
01.65.02.1
01.63.31.1

GATE C
GATE C RELAY CHART
GATE C RELAY CHART
GROUND RETURNS

01.00.23.1
01.00.31.1
01.00.31.2
01.90.35.1

HIGH ORDER ZERO CONTROL
HIGH PLUS AUXILIARY

01.68.40.1
01.66.83.1

I CYCLE TRIGGER
I CYCLE TRG NO 1
I CYCLE TRG NO 2
I CYCLE TRG NO 3
I CYCLE TRG NO 4
I CYCLE TRG NO 6
I CYCLE TRG NO 7
I CYCLE TRG NO 8
I TIMER TRG NO 5
IA DIGIT REG CONTROL
IA MARS CONTROL
IA TRIGGER CONTROL
INCREMENT DECREMENT TRIGGER
INDIRECT ADDRESS EXECUTE TRGS
I NDIRECT ADDRESS EXECUTE TRGS
I NDIRECT ADDRESS EXECUTE TRGS
INHIBIT CONTROL ODD PLANES
INHIBIT CONTROL EVEN PLANES
INHIBIT DRIVERS
INPUT TRANSLATOR ZONES
INPUT TRANSLATOR C 8 F BIT
INPUT TRANSLATOR
INSTRUCTION CYCLE ENTRY POINT
INTEGRATING CIRCUITS LAYOUT
INTERCHANGEABLE SMS CARDS
IR NO 1 READ WRITE DR GATE POINT
IR NO 2 READ WRITE DR GATE POINT
1/0 CONTROL TRG 30
1/0 CONTROL TRG 31
1/0 CONTROL
1/0 CONTROL SYNC/l 0 EXIT TRGS
1/0 CONTROL R/W CALL 19999 STOP TRGS
1/0 READ CODE CHECK
1/0 WR CODE CHECK

01.15.10.1
01.15.11.1
01.15.12.1
01.15.13.1
01.15.14.1
01.15.16.1
01.15.17.1
01.15.1B.l
01.15.IS.l
01.16.13.1
01.16.12.1
01.16.11.1
01.60.05.1
01.16.20.1
01.16.21.1
01.16.22.1
01.30.60.1
01.30.65.1
01.30.80.1
01.BI.41.1
01.Bl.30.1
01.BI.40.1
01.15.05.1
01.00.40. I
01 .OO.OS. I
01.56.10.1
01.56.12.1
01.64.10.1
01.64.11.1
01.64.12.1
01.64.13.1
01.64.14.1
01.Bl.2.0.1
01.B2.30.1

KEYBOARD CONTROL

01.Bl.l0.l

LAMPS 1-68
LAMPS 69-136
LAMPS 137-202
LOAD DIVIDEND
LOAD DIVIDEND
LOAD DIVIDEND
LOAD DIVIDEND

01.05.15.1
01.05.16.1
01.05.17.1
01.65.01.1
01.67.30.1
01.67.31.1
01.67.32.1

CONTROL
MODE
ENTRY CONTROLS
AND DIV ENTRY CONTROLS

MAR DATA TRANSMISSION
MAR ADDR DATA ENTRY INCREMENT 2 SW
MAR UNITS TO DB REG UNITS GATE PT
MAR TENS TO DB REG UNITS GATE PT
MAR VRC UNITS TENS HUND THOU
MAR FIXED ADDRESS SET CONTROL
MAR FIXED ADDRESS SET CONTROL
MARS ADDRESS ENTRY 10 THOU 24 BIT
MARS ADDRESS ENTRY UNITS C
MARS ADDRESS ENTRY UNITS 48 BIT
MARS ADDRESS ENTRY UNITS 12 BIT
MARS ADDRESS ENTRY TENS C BIT 50 TRG
MARS ADDRESS ENTRY TENS 48 BITS
MARS ADDR ENTRY TENS 12 BIT
MARS ADDRESS ENTRY HUND C BIT
MARS ADDRESS ENTRY HUND 48 BIT
MARS ADDRESS ENTRY HUND 12 BIT
MARS ADDRESS ENTRY THOU C BIT
MARS ADDRESS ENTRY THOU 48 BIT
MARS ADDRESS ENTRY THOU 12 BIT
MARS ADDRESS ENTRY 10 THOU POS

01.67.90.1
01.63.60.2
01.56.36.2
01.57.40.2
01.67.00.1
01.69.90.1
01.10.35.1
01.10.36.1
01.66.70.1
01.66.71.1
01.66.79.1
01.67.10.1
01.00.80.1
01.00.81.1

01.41.04.1
01.55.03.1
01.53.01.1
01.53.12.1
01.5B.05.1
01.59.10.1
01.59.15.1
01.55.49.1
01.55.05.1
01.S5.06.1
01.55.09.1
01.S5.15.1
01.55.16.1
01.55.19.1
01 ;S5.25.1
01.55.26.1
01.55.29.1
01 .S5 .35.1
01.55.36.1
01.55.39.1
01.55.45.1

DESCRIPTION
MARS BIT DRIVERS UNIT AND C BIT POS
MARS BIT DRIVERS TENS POS
MARS BIT DRIVERS HUNDREDS POS
MARS BIT DRIVERS THOUSANDS POS
MARS BIT DRIVERS TEN THOU POS
MARS-BIT DR & SENSE WINDING PINS
MARS-BIT DR & SENSE WINDING PINS
MARS READ DRIVERS
MARS WRITE DRIVER
MARS
MARS-RD & WR DRIVE WINDING PINS
MARS SENSE AMP I T &H POS
MARS SENSE AMP H TH T THOUS POS
MATRIX SW A UNITS TENS OUTPUTS
MATRIX SWITCH A UNITS-TENS INPUTS
MA TRIX SW D HUN THOU OUTPUTS
MATRIX SW D HUN THOU INPUTS
MBR RESET CONTROL TRANS
MBR WRITE SAMPLE CONTROL
MBR VRC ODD
MBR VRC EVEN
MBR VRC T TH AND VRC TRIGGER
MDR TO MBR TRANSMISSION
MDR TRANSFER TO MBR CONTROL
MDR MBR 10 INPUT DATA SET CONTROL
MEMORY ARRAY-SIDE A UN TEN-IO THOU PL
MEMORY ARRAY-SIDE D HUN THOU PL
MEMORY MARS CLOCK SAMPLES
MEMORY ARRAY INHIBIT WINDING
MEMORY MAT SWITCH I DRIVERS
MEMORY DECODE SWITCH UNITS
MEMORY DECODE SWITCH TENS
MEMORY DECODE SWITCH HUND
MEMORY DECODE SWITCH THOU
MEMORY SENSE AMPLIFIER CONTROL
MEMORY SENSE AMP GATES
MEMORY SENSE AMP ODD 1248CF
MEMORY SENSE AMP EV 1248CF
MEMORY BUFFER REG ODD C F BITS
MEMORY BUFFER REG ODD 84 BITS
MEMORY BUFFER REG ODD 21 BITS
MEMORY BUFFER REG EVEN C F BITS
MEMORY BUFFER REG EVEN 84 BITS
MEMORY BUFFER REG EVEN 21 BITS
MEMORY DATA REG C F 8 BITS
MEMORY DATA REG 421 BIT
MEMORY DATA REG DISTRIBUTION CF BIT
MEMORY DATA REG DISTRIBUTION 84 BIT
MEMORY DATA REG DISTRIBUTION 21 BIT
MEMORY ADDRESS UNITS C 8 BIT
MEMORY ADDRESS REG UN ITS 42 BITS
MEMORY ADDRESS REG UNIT I TEN C BIT
MEMORY ADDRESS REG TENS 84 BIT
MEMORY ADDRESS REG TEN 21 BIT
MEMORY ADDRESS REG HUND 42 BIT
MEMORY ADDRESS REG THOU 84 BIT
MEMORY ADDRESS REG THOU 21 BIT
MEMORY ADDRESS REG 10 THOU C 21 BIT
MEMORY ADDRESS REG TEN THOU 4 BIT
MEMORY ADDRESS REG HUND C 8 BIT
MEMORY ADDRESS REG HUND I THOU C BIT
MEMORY ARRAY SENSE WINDING OP
MI I/O TO MBR TRANSMISSION
MI MEMORY BUFFER REGISTER TRANS
MI MEMORY BUFFER REGISTER TRANS
MIXED OP CODES
MODULO 3 COUNTER
MOVE FLAG EXECUTION CONTROLS
M/Q TO MDR GATES
MULTI PL Y CLEAR ACCUMULATOR TR 32
MULTIPLE CYCLE CONTROL TR
MULTIPLIER READ MPR DIGIT TR 33
MULT READ MULTIPLICAND DIG TRG 34
MULTIPLIER/QUOTIENT REG C 84 BITS
MULTIPLIER/QUOTIENT REGISTER 21 BIT
MULTIPLIER DOUBLER UNITS
MULTIPLIER DOUBLER HUNDREDS
MULTIPLY MODE CONTROLS

DIAGRAM NUMBER
01.55.55.1
01.55.56.1
01.55.57. I
01.55.58. I
01.55.59. I
01.55.60. I
01.55.61. I
01.56.30. I
01.56.35.1
01.56.40. I
01.56.41.1
01.57.01. I
01.57.03.1
01.30.01. I
01.30.02.1
01.30.03.1
01.30.04.1
01.41.05.1
01.40.05. I
01.40.10.1
01.40.20. I
01.58.09. I
01.4 1.15. I
01.46.10.1
01.47.10. I
01.30.05. I
01.30.05.2
01.10.30. I
01.30.07. I
01.30.10. I
01.30.16. I
01.30.21.1
01.30.26. I
01.30.31. I
01.30.35. I
01.30.40.1
01.30.45. I
01.30.50.1
01.40.07. I
01.40.08. I
01.40.09. I
01.40.17.1
01.40.18. I
01.40.19.1
01.45.05. I
01.45.07. I
01.45.15.1
01.45.16.1
01.45.17.1
01.57.05.1
01.57.07. I
01.57.09.1
01.57.16.1
01.57.18. I
01.57.22. I
01.57.26.1
01.57.28.1
01.57.30. I
01.57.32.1
01.57.20. I
01.57.24. I
01.30.08.1
01.41.16.1
01.41.17.1
01.41.07.1
01.20.20. I
01.68.10. I
01.60.62. I
01.65.08.1
01.62.30.1
01.62.31. I
01.62.33.1
01.62.34.1
01.62.50. I
01.62 .52. I
01.62.55.1
01.62.60. I
01.67.01. I

NOISE CANCELLATION INDUCTORS
NORMALIZING SHIFT RIGHT

01.30.06. I
01.68.42.1

ODD EVEN ADDRESS DATA CONTROL
OP DECODER CODES I I -29
OP DECODER CODES 71-79
OP DECODER CODES 42-49
OP DECODE OPS 01,02,03,09
OP DECODE OPS 05,06,07,08
OP REG UNITS 4 8 C BIT
OP REGISTER UNITS I 2 BIT
OPERATION DECODER CODES 31-34
OPERA TlON DECODER CODES 35-39
OR I READ DRIVER GATE POINT
OR I WRITE DRIVER GATE POINT
OR 2 READ DRIVER GATE POI NT
OR 2 WRITE DRIVER GATE POINT
OR 3 PR NOS I 2 3 READ DRIVER GATE P
OR 3 PR NOS I 23 WRITE DRV GT POINT
OR 3, PR I, PR 2, PR 3 WRITE DRIVER
OR 4, OR 5, CR I READ DRIVER GATE PT
OR 4, OR 5, CR I WRITE DRIVER GATE PT
OUTPUT TRANSLATOR X 0 BIT
OUTPUT TRANSLA TOR 84 21 BIT
OUTPUT TRANSLATOR C BIT
OVERFLOW HIGH PLUS EQUAL ZERO TRGS

01.43.10. I
01.20.19.1
01.20.72. I
01.20.42. I
01.20.16. I
01.20.17. I
01.20.07. I
01.20.09. I
01.20.31. I
01.20.35.1
01.56.14.1
01.56.15. I
01.56.16. I
01.56.17. I
01.56.18. I
01.56.19.1
01.56.19.2
01.56.20.2
01.56.21.1
01.82.20.2
01.82.20.3
01.82.20. I
01.60.40. I

DESCRIPTION

DIAGRAM NUMBER

PAPER TAPE READER CONTROL
POWER SUPPLY SEQUENCING
POWER SUPPLY SEQUENCI NG
POWER SUPPLY WIRING DIAGRAM
POWER SUPPLY WIRING DIAGRAM
POWER SUPPLY WIRING DIAGRAM
POWER SUPPLY WIRING DIAGRAM
POWER SUPPLY WIRING DIAGRAM
PROG TIMER ADD SUB COMP TR NO 13
PROG TIMER ADD SUB COMP RECOMP/OP
PROGRAM TIMER BT E CYCLE TR NO 15 16
PROG TIMER ADD SUB COMP T/C TRG
PR I, PR 2 READ DRIVER GATE PT
PUNCH CONTROL
PUNCH DATA GATE
PWR SPL Y SEQUENCE & FUSE PANEL

01.83.10. I
01.90.40.1
01.90.42.1
01.90.22.1
01.90.23.1
01.90.24.1
01.90.25. I
01.90.26. I
01.60.13. I
01.60.24. I
01.60.45. I
01.63.20.1
01.56.18.2
01.84.10.1
01.84.20. I
01.00.80. I

QUOTIENT COUNTER

01.65.07. I

RC UNITS & T B DIODE GA TE C
READ BUS CXO
READ BUS 84
READ BUS 21
READ CHECK AND WRITE CHECK
READER DATA GATE
RECOMPLEMENT
RECOMPLEMENT TRG 23
REG 48 C BIT L TENS
REG TENS I 2 BIT
RELAY GATE GROUND BUS
RESET CONTROL MBR MDR
RESPONSE AND DISCONNECT
RESPONSE CONTROL
RESULT TRANSMIT MODE

01.00.35.1
01.81.15. I
01.81.15.2
01.81.15.3
01.81.45. I
01.83.20. I
01.60.28. I
01.60.32. I
01.20.10.1
01.20.12. I
01.00.32. I
01.40.03.1
01.80.25. I
01.80.30. I
01.66.40. I

SA & MBR GATES MI TRANSMISSION
SCAN MODE
SCAN MODE CONTROLS
SCAN MODE CONTROLS
SCAN MODE CONTROLS
SCAN MODE CONTROLS
SCAN MODE INCR/DECR CONTROL
SELECT
SENSE & BRANCH ERROR
SENSE BRANCH REG CONTROL
SENSE AND BRANCH DECODER
SENSE SWITCH TEST
SHIFT MODE
SHIFT AND ZERO FILL CONTROLS
SHIFT OPS ENTRY MODE
SHOE CONNECTOR REFERENCE CHART
SHOE CONNECTOR REFERENCE CHART
SYSTEM DISTRIBUTION

01.4 1.06. I
01.66.20. I
01.66.21.1
01.66.22.1
01.66.23. I
01.66.24. I
01.66.25. I
01.80.05. I
01.06.12. I
01.25.05.1
01.25.15.1
01.25.20. I
01.66.50.1
01.66.51.1
01.67.50.1
00.00.20.2
00.00.20.1
01.90.32. I

TI SF CF BNR BD NO CPTR NO 28
TIM MULT TR NO 38 WR SUM DIGIT ACC
TIMER TRG 26 272829 CONTROL
TIMER TRANSMIT OPERA TIONS TRG 26 27
TIMER SF CF BNF BNR BD TRG 29
TIMER MULT RD OUT PR FR MULT TB TRG 35
TIMER MULT RD OUT ACC DIG TRG 36
TIMER MUTLIPL Y READ OUT ADD TABLE
TIMER ADD SUB COMP 1ST CYC TRG
TIMING SAMPLE GENERATION AlB TRG
TIMING SAMPLE GENERATION
TIMING SAMPLE GENERATION
TIMING SAMPLE GENERATION
TIMING SAMPLE GENERATION
TIMER MULT TRG 40 RDOUT ADD TABLE
TIMER MULT WR SUM DIG INTO ACC T41
TNS TNF CONTROLS
TRIGGERS 44 & 45
TRIGGERS 42 44 CTRL
TRIGGERS 42 AND 43
TRUE COMP SW DIGIT I DIGIT
TYPEWRITER OUTPUT SIGNALS
~YPEWRITER OUTPUT & CHECK
TYPEWRITER CAM CONTACTS & CODING
TYPEWRITER CAM CONTACTS & CODING
TYPEWRITER CAM CONTACTS & CODING
TYPEWRITER THYRATHRONS
TYPEWRITER OPERATIONAL CONTROL
TYPEWRITER OPERATIONAL CONTROL
TYPEWRITER CONTROLS
TYPEW~ITER CONTROLS
TYPEWRITER BIT RELAYS
TYPEWRITER KEY MAGNETS
TYPEWRITER KEY MAGNETS
TYPEWRITER KEY MAGNETS
TYPEWRITER KEY MAGNETS

01.60.58. I
01.62.38. I
01.60.56. I
01.60.57. I
01.60.59. I
01.62.35. I
01.62.36. I
01.62.37. I
01.63.10. I
01.10.12.1
01.10.15. I
01.10.22.1
01.10.25.1
01. 10.26.1
01.62.40.1
01.62.41.1
01.60.54.1
01.65.03. I
01.65.09.1
01.65.05. I
01.60.34. I
01.81.50. I
01.81.55. I
01.81.60. I
01.81.62. I
01.81.64. I
01.82.52.1
01.82.60. I
01.82.62.1
01.82.70. I
01.82.72. I
01.82.75.1
01.82.80.1
01.82.82.1
01.82.84.1
01.82.86.1

UNIT PLUGGING CHART AI

01.00.10. I

VOLTAGE DISTRIBUTION PANEL AI
VOLTAGE DISTRIBUTION PANEL A2
VOLTAGE DISTRIBUTION PANEL BI
VOLTAGE DISTRIBUTION PANEL B2
VOLTAGE DISTRIBUTION PANEL D
VOLTAGE SENSE RELAYS & METERING
VRC CNTRL TRG FOR MBR MDR MAR

01.00.15. I
01.00.16.1
01.00.17. I
01.00.18. I
01.00.19. I
01.90.45.1
01.45.30.1

ZtRO FILL MODE
ZERO FILL CONTROLS

01.66.60. I
01.66.6I.J

INTRODUCTION

This manual is intended for instructional purposes.
It does not replace any field machine system diagrams.
The diagrams enclosed within the machine should
always be used for field analysis. These diagrams
are intended for use with the Customer Engineering
fv\anual of Instruction, 1620 Data Processing System,
E Level.
The system diagrams in this manual are at F level and
include Floating Point Arithmetic circuits.

FUNCTION CHART SYMBOLS

6

~

Plus AND Inverter Function (All input legs must be conditioned to +5 level to receive a -5
output level.) The line nome of each input leg specifies a +5 level condition.

~
fT.

1-

Minus OR Inverter Function (When one or more of the input legs is at -5 level, the output is at
+5 level.) The line nome of each input leg specifies a -5 level condition.

A trigger or latch is turned ON.

A trigger or latch is turned OFF.

INVERTER

+"'
f'"'

-+p
t

~&-

(A -5 level is inverted to a +5 level, or a +5 level is inverted ta a -S level.)

INTEGRATOR

(+48V is converted to +5 level when the contact feeding the Integrator is closed. A -5 level
appears on the line when the contact is open.)

DRIVER, Relay Thyratron requires a +S on both inputs.

This symbol is used where two or three conditions (+S) are necessary to turn on AND Latch on or off.
It represents on internal circuit within the latch rather than on external AND block.

iTrg

+SGo,,~

Pulse,
or Ground

D5P

t-t&,
I

t_

t

I

SAMPLE PULSE GENERA TOR

EXCLUSIVE OR

(Provides a + output pulse for setting AC triggers. Requires a + pulse with a
+ gate to "fire".)

(Like inputs produce a +S output. Unlike inputs produce a -S output.

This symbol represents a non-inverting DOT AND emitter follower (AND circuit). Two +5 inputs produce
a +S output.

This symbol represents a non-inverting DOT OR emitter follower (OR circuit). One or Two -S inputs
produce a -S output.

This symbol represents on OR turn on of a Latch. It indicates the associated circuits of a Latch., Extenders etc.
Trg

INSTRUCTION CYCLE - TRIGGER I

7

Not Start 1

01. 15.05. 1

Stop I Trg

W2-~ & --Not Run

-.l

01.06.10.1

Start 1 Tr9

01.06.05.1
High Plus Tr9

01.60.40.1

Run Trg

Trigger No 1

01.06.10.1

01.15.11.1
Console Lamp

01.20.12.1

I/O

Exit Trg
01.64.13.1
Reset OP Reg Tens & Units

OR-2

OR-l

OR-3

-R Read /MRS Array
I Cycle Trigger·
01.15.10.1

(Turned 011 by Trg 8)

T2-D2 (-5)
RO-D2
-R Read
IR-l Array
-R Write

T3-D7

I Cycle Reset 01.15.10. I

Not C8

Reset HOFF" The Following Triggers

lR-l Array

IA Time
Decrement
Reset D/B Units

.*

Set DiS Units

Will be Operative for Each I-Cycle Except No.8

** Op Codes 34, 35, 36, 37, 38, 39, 46, and 47
-12v
CE Switch #7
01.03.30.1
(Incr /MR +1)

-I

&-SAdv

Trigger

No.2

L--\_" 01. 15. 12. 1
Console Lamp

To Page 8

Trigger No. 12
Trigger No. 13
Trigger No. 14
Recomp Control
Recomp

Trigger No. 19
Trigger No. 27
Trigger No. 29

M/O Reg
First Cycle
Field Mark No.1
Field Mark No.2
Carry-in
Carry-out

Digit/RM
First Divide Cycle
Last Divide 'Cycle
Trigger No. 45
Divide Add

Trigger No. 43

Div/Rem Sign

01.16.10.1
01.60.05.1
01.60.12.1
01.60.13.1
01.60.14.1
01.60.24.1
01.60.32.1
01.60 •. 49.1
01.60.57.1
01.60.59.1
01.62.52.1
01.63.10.1
01.63.30.1
01.63.30.1
01.63.40.1
01.63.40.1
01.63.50.1
01.65.02.1
01.65.02.1
01.65.03.1
01.65.04.1
01.65.05.1
01.65.06.1

8

INSTRUCTION CYCLE - TRIGGERS 2, 3, 4 and 5
From Trg No.2

01.55.03.1

Reset D/B Tens
& _ A Adv

Set D/B Tens
(From MBR Odd)

Incr +2
01.55.03.1

Trigger No 3

01.15.13.1

-R Write

-R Write

OR-3 Array

OR-2 Array

Console Lamp

T3-D7

Reset D/B Tens

Set D/B Tens
(From MBR Odd)

Incr +2

& - - B Adv

-R Write

-R Write

01.55.03.1

OR-2 Array

OR-3 Array
Trigger No.4
01. 15. 14. 1

Code
28/18
R5-D6
(Reset)
T4-D4

Code
29/19

Write Units

01.55.01.1
/Not IA Trg
&_A Adv

W3-D2
01.56.35.1

-R Read PRI
Array
01.56.30.1

Trigger No.5

01.15.15.1

-R Write

OR-3 Array

-R Write

OR-2 Array

Console Lamp

I Cycle Trg
01.15.10.1

& --B Adv
Trigger No.6
01.15.16.1
Console Lamp

To Page 9

Write 10 Theus

-R Write

01.55.01.1

OR-l Array
01.56.35.1

-R Write

PR-l Arroy
01.56.35.1

9

INSTRUCTION CYCLE - TRIGGERS 6, 7, and 8
FROM TGR No 6

Not Immediate Code

Reset

W3-D2
·01.S6.3S.1
-R Write OR-I

D/B Tens

Set
D/B Ten.
(From MBR Even)

'5&)
~'rj"$
~
Inv

t

OR

-R Write PR-I

OI:t~~.1

Write

Write

Inv

Tens
Units
01.55.01.1

BI-BNI

OR

Array

Branch
Test Ter
01.2S.3S.1

Reset

Wr Dr

D/B

01.56.3S.1
W3-D2

Tens

Set
D/B
Tens
(From MBR Even)

-R Write OR-I
Array

Trigger No.8
01.IS.18.1

-R Write PR-I
Array

01.S6.3S.1

Console !,amp

E Cycle Entry Trg 01.15. lB.l

BT Trg ClN
To E Cycle

W6-DI2

Entries

. ypass
01.55.02.1

Inv

I-Cycle Entry

TIC Tgr
01.63.20.1
Run Tgr
01.06.10.1

5014

Not
Trg 30

E Cycle

Immed
OP Cod.

Block
MAR
Reset
01.S9.10.1

Start I Tgr
01.06.0S.1

Start 1
Trg

I-Cycle
Tgr
OI.IS.IO.1

Deer Trg

-R Write PR-I
Array
01.56.35.1

TRANSMIT DIGIT, FIELD, RECORD

10

Code
FM 1 28/18

Code 25/15

TRANSMIT DIGIT CODE 25/15
TRANSMIT FIELD CODE 26/16
TRANSMIT RECORD CODE 31

Code 26/16

Note: Decr Trg on When
E-Cycle Entered Except
on OP31 See I-Cycle
Trg 8.

Trigger 26
01.60.57.1
Console Lamp

OR-l
Rd Dr
01.56.14.1

OR-l
Wr Dr
01.56.15.

t

&--EE~ir~le

Not 1st Cycle
B Adv

L

& _E Cycle

First Cycle Trg
01. 63.10.1

OR-2
Rd Dr
01. 56.16.1

OR-2
Wr Dr
01.56.17.1

Not
TN Comp-"
(Codes 72, 73)

W2-D3
01.63.10.1

Reod Y Point
01.30.35.1

1st Cycle Trg

Digit/RM
On
Code 31
Code 26/16
I Cycle Reset _ _
--Trg 28
FM 1
Code 25/15
01.60.56.1

I Cycle Entry
01.15.05.1

ADD, SUBTRACT, COMPARE - TRIGGERS II, 12, and 13

11

Carry-in Trs

High Plus TrS
01.60.40. I

Equal Zero Trg
01.60.41. I

01.63.40. I

Note: Deer TrS is ON (Deer)
See I Cycle Trg 8

Trg
01.63.40. I

Not
Recomp

MDR 2
Bit

Control

&4I--E Cycle Entry

*JstCYcie Trg
01.63.10. I
I Cycle Reset-....
Change Status

of TIC Trg
01.63.20. I
ON- True

OFF - Complement

Field fv\ark
No.2 TrS

01.63.30. I
Not 1st

Cycle

01.60.41. I
Code

24/14
True (TIC ON)
High Plus Trg

01.60.40. I

I Cycle Entry

Change Status

01.15.05. I

Change of Status of

TIC

Trg

01.63.20. I

Equal/Zero Trg

Set MAR Tens

01.60.41. I

C Bit TrS
01.57.09.1

'01.60.24.1
Co~lement

TIC Sw;tch

NoC 0

8 Bit Out
~BAdv

(TIC SwHch 9 Out)
Tic Sw;tch
C Bit Out

Recornp Control

Trg 01.60.24. I
Console Lamp

Code 24/14
I Cycle Reset
To Page .12

O'Flow Check
Auto

O'Flow Stop 01.06. II. I

From Page 11

1

ADD, SUBTRACT, COMPARE - TRIGGER 14

Console lamp

Trg 13

WrDr

Rd Dr
01.56.16.1

FM 2
01.60.28.1

01.63.40.1

&

Set F Bit
(Sign)
01.46.10.1

01.60.14.1

&

Inv
Read Y Point

&.--CO Trg ON

,I,
-f

01.30.35. I

~

E Cycle
Adv

&

Recomp

01.56.17.1

1st Cycle

Co"y In (CI) T",
01.63.40. I

Not Code 29/19

9
Not Code 29/7cP
&

& __ Not Code

Not FM 2

24/14_~+--'

Not Code 24/14"/ .
High Plus OFF / r l ,
High Plus ON
Clear F

FM 2
Set F Bit

Clear

Bit
(Corry)

(Field Def)
01.46.10.1

F Bit
(Corry)

FM 1

Not 1st
Cycle

Not Recomp Control

01.46.10. I
1------,----------,
I Not Floating Point
I
I
Op (0 Decode Op Reg Tens) I

L--r-Ol.60:-41.1-------1

Trigger 11
01.60.11.1

Not End Compare

Floating Point
Arith
HighlPlus Trg

01.60.40.1
Trigger 21

01.60.31. I
Console
Lamp

Recomp

:~~::I~
(Reset)

J"

T

OR-2
Rd Dr

01.56.16.1

r------,

Nor Recomp---.. &
Control

/ i Not 1st Trg 21 t
I Subt Cntr
I
~Not 1st Trg 21 i
L_S..:.t_l ___ 1

Set C Bit
In D/B Reg Units

01.50.07. I

I

Floating Point
Arith

Not FM 2

Not

Recomp~
/'f

Control

& _

Recomp Control

Block
MAR Reset

01.59.10. I

FM 1
01.63.30.1

OR-3

OR-2

Rd Dr

WrDr

01.56.18.1

01.56.17.1

Bypass

FM 2 Trg

01.55.02.1 01.63.30.1
Recomp Trg
(Turned Off By
1.60.32:1
J Cycle Reset)
Console lamp
Trg 12 Time

.:r Trg 13 Time

.r:

'\... r /'

Not Trg 21

Not FM 2~ &

Trg 14 Time

01.60.28.1
Trg 14 Adv

Trigger 23

01.60.32.1

Trg 11

8

1st Cycle Trg
01.63.10.1

Block MAR
Re5et

01.59.10.1

AdV

~

Trg 12
01.60.12.1

1st Cycle TrS

01.63.10.1
Console lamp

MUL TI PL Y FLOW DIAGRAM

No Carry Out
F M

No.2

Carry Out

Field Mark No.1

E Entry Advance

Enter I-Cycle

No Corry Out
Not F M

No.1

No Carry Out

Carry Out
Not F IV'.

C lear Product Area
(00080-00099) to
Zeros.
(Set 00080 in MAR;
Increment PR- 1 in
Continue Clearing

Process)
Trigger 32 Remains
N for Ten Memory
Cycles.

a

I Read Multiplicand

Read Multiplier Digit
From Memory per OR-1
and Store it in the
I
Multiplier/Quotient
Register.
(Decrement OR-1 to
Prepare for Reading
Next Higher-Order
Digit of Multiplier
From Memory. Turn OFF
High;!,lus Trg on
First Cycle if the
Multiplier is Negative.
Set Field Mark No. 1
Trg on Cycle in Which
High-Order Digit of
Multiplier is Read
from Memary.)

Digit from Memory
per OR-3 (per OR-2
on First Cycle of
Each New Multiplier
Digit) and Store it in
MDR.

Develop and Set
Multiply Table
Address in MAR.
Read Multiply
Table Digits
from Memory into
the Digit/Branch
Register. (MDR
Digit/Branch

(Write Back OR-2
Bypassed on First
into Register Units;
C yde of Each
MBR-Odd into
Multiplier Digit to
Digit/Branch
Register Tens.)
Maintain Address
of· Units Position
of Multiplicand
in OR-2.
'----------1
Decrement OR-3 to Prepare for
Reading Next Higher-Order Digit
of Multiplicand from Memory.
Change Status of High/Plus Trg On
First Cycle if Multiplicand is
Negative.
Set Field Mark No •.2 Trg on
Cycles in Which High-Order
Digit of Multiplicand is Read
from Memory.)

Read Product Area
Digit from Memory
per PR-2 (per PR-1
on First Cycle of
each New Multiplier Digit) and
Store it in MDR.

Develop and Set
ADD Table
Address in MAR.
Read ADD Table
Digit from
Memory into
MDR.

(Decrement PR-1
on First Cycle of

(Set Corry Out
Trg if ADD Table

Each Multiplier
Digit Contains a
Digit to Read
Flag Bit. Transfer
Next HigherContents of Digit/
Order Product
Branch Register Tens
Area Digit from
to Digit/Branch
Memory at Start
Register Units for
of Multiplication
Use During Trg 40
by Next Multiplier Time.)
Digit. Write PR-1 '-----'------~
Into PR-2 Bypassed on First Cycle of Each
Multiplier Digit to Maintain Address for
Storing Sum Digit During Trg 38 Time
First Cycle. Write Back PR-2 Bypassed
After First Cycle of Each Multiplier
Digit for Storing Sum Digit During
Trg 38 Time.

Write Sum Digit
Read Product Area
into Product Area Digit from Memory

per PR-2.
(C lear any F Bit
Denoting Carry
Before Placing
Sum Digit in
Product Area.
Write Back PR-2

per PR-3 and Store
it in MDR.

Develop and Set
Write Sum Digit
ADD Table Address Into Product Area
in MAR. Read
Per PR-3.
ADD Table Digit
(C lear any F Bit
from Memory Into
Denoting Carry
MDR.
Before Placing Sum
(Set Carry Out
Digit in Product
Trg if ADD

(Write Back PR-3
Bypassed to Maintain Address for
Table Digit can·
Storing Sum Digit
During Trg 41 Time.) 'tains a Flag Bit.)

Decremented to
Read Next Higher-Order Product ' - - - - - - - - - - - 1
Area Digit from Memory During Trg
36 Time of the multiplication of
the Next Higher-Order Digit of the
Multiplicand by this Same Digit of
the Multiplier. Also Write PR-2
Decremented Into PR-3 for use
During Trg 39 Time.
Set F Bit With Sum Digit on First
Cycle if Higly'Plus Trg is OFF Denoting a Negative Product.
Set Carry In Trg if Carry Out Trg
is ON from Trg 37 Time.)

No.2

Area. Decrement

PR 3 for use During
Trg 39-40-41 Loop
if Carry Out Condition Exists.
Set Field Definition
F Bit with Sum Digit
on Cycle in Which
High-Order Digit of
Pro,duct is Placed in
Product Area. Set
Carry In Trg if
Carry Out Trg is ON
From Trg 40 Time.)

14

MULTIPLY DATA FLOW - TRIGGERS 32,33,34, AND 35

E-C yc Ie Entry
Code 13/23

Trigger 32
Clear

Trigger 33
Obtain
Multiplier Digit

Trigger 34
Obtain
Mcnd Digit
Trigger 35
Mult Table Addr
Two Digit Product

Obtain New
Multiplier Digit

Develop Two
Digit Product

15

MULTIPLY - CODE 23/13

~f
& ..... E Entry Adv

01.62.30.1

*

E Cycle &
Entry
01.62.30.1
C Bit
C Bit
Set 00080 01.40.07.1 01.40.17.1

~l in~"

i-~~·
28/1B

HiS Ius
Trigger

Incr +2

01.60.40.1

01.55.03.1

Equal/Zero

~r->'"-

WrDr

Trigger

01.56.19.1

01.60.41.1

Console

La""

FM 2

TrS 19

01.63.30.1 01.60.49.1
Set

Cycle
Control

M/Q
Reset
M/Q Reg
01.62.50.1

Bypass
01.55.02.1

Trs
01.62.31.1

C4
C6

Wr Dr

OR-2 01.56.17.1
Rd 0,
01.56.16.1
OR-3
_A Adv
Rd 0,
01.56.1B.l

05-08
Special Write Time MARS

T'g

01.63.30.1

Reset-Set

0/8 Ten, (MSR-Odd)
D/S Un;', (MDR)

01.50.05.1

Console Larrp
To Page 17

Reg
F"'m
MDR
01.62.50.1
01.62.52.1

Change Status
of High/Plus Trg

01.60.40.1

16

MULTIPLY DATA FLOW - TRIGGERS 36,37, AND 38

Trigger 32
Cleor

Trigger 33
Obto,n
Multiplier Digit

Obta,n New
Multiplier Digit

Trigger 34
Obto;n
Mend Digit

Develop Two
Digit Product

Trigger 35
Mull Table Add.
Two Digit Product

Trigger 36
Obtain
Product Area Digit
Add Two Digit
Product Un its
Posi t ion""i'iiiC)
Product Area

Trigger 37
Add Table Address
Trigger 38
Read Y
Sum Digit to Memory

Product Area Digit
Add Two Digi'
Product
Position
Prod ue t A reG

Trigger 40
Add Table Address

FM 2

CO

41
y

Sum Digit to Mumory

Trigger 19

co

Dummy Trigger

No CO
FM 1
No CO

! Cycle

17

MULTI PLY - CODE 23/13
From Page 15

01. 10.25. 1
W6-D12

T4-04 (Reset)

R5-D6

Cycle Control

Bypass
01. 55. 02.1

R5-D8
Special Write
Time-fvlARS

& __ A Adv

PR-2
Rd Dr
01.56.18.1

Trigger 37
01.62.37.1

PR-2
PR-2
Rd Dr
Wr Dr
01.56.18.101.56.19.1

PR-1
PR-2
Rd Dr
Wr Dr
01.56.18.1 01.56.19.1

Not
MDR 1 Bit
MDR 2 Bit
MDR 4 Bit
MDR 8 Bit
&
R5-D6
~ 01.63.30.1
Equal/Zero
Trigger
01.60.41.1

R5-D6
Set
D/B Units from
D/B Tens
&--B Adv

Reset
DIB Units

Recomp
Orl

Trigger 38
01.62.38.1

Not
C1

Set fvIA R TIC SW
Add-Addr
8 Bit
01.59.10.1
TIC SW
C Bit

Console Lamp

Not First Cycle
PR-3
Rd Dr
01.56.18.1

Console
Lamp
To Page 19

PR-2
& ___C 0
Rd Dr
Trg 01.56.18.1

*

Carry In
Trigger
01. 63. 40.1

PR-3
Wr Dr
01.56.19.1

PR-2
Wr Dr
01.56.19.1

High/Plus
OFF

First Cycle

Clear MDR F Bit
(Carry After First Cycle) Set F Bit (Sign)
01.46.10.1
01.46.10.1

18

MULTIPLY DATA FLOW - TRIGGERS 39,40,41, AND 19

Trigger 39
Obtain
Product Area Digit
Add Two Digit
Product Tens
Position into
Product Area

Trigger 40
Add Table Address

FM 2

CO

CO

Trigger 41
Read Y

Trigger 19
Dummy Trigger

No CO

FM 1
No

No CO

FM 1

I Cycle

MULTI PLY - CODE 23/13

19

From Page 17

&- B Adv

C 0 Trg
01.63.40.1

Cycle
1st
Control
Cycle
Trg
01.60.49.1
Trg 01.55.02.1
01.62.31. 1
01.63.10.1

Reset
D/B

Units
01.50.05. I

Not

R~Ct~~p
A Adv

l

r-

PR-3
WrDr
01.56.19.1

t

MDR 8 Bit
MDR 4 Bit
RO-D7

MDR 2 Bit
MDR 1 Bit

CI-+~&
W6-D5r __ ~~t

Set MAR
Inv
Add-Addr
TIC
01 • 59 • 10 • 1 Sw 8 Bit~
Set
MAR
&
003XX
TIC
SW C Bit
CO Trg
01.63.40.1

Trg
01.63.40. I

Carry Out
Trg
01.63.40.1

Equa I/Zero Trg
01.60.41. 1

Console Lamp

t

FM 2

&-Carry Out
Carry In
Trg (C I )
01.63.40.1

Clear F Bit
01.46.10.1
(Carry)

Set F Bit
01.46.10.1
(Field Definition)

Console Lamp

Carry Out

o

Trg 33
Trg39_
I-Cycle Trg_

I Cycle Entry
01.15.05.1

Block
MAR
Reset
OR
01.59.10. I ?
01.60.31.1

Set C Bit
D/B Units
01.50.07.1

Not FM 1
Not Carry Out

*

&~A

Adv

Code
23/13

Trigger 39
01.62.39.1

Cycle Control Trg
01.62.31.1

20
Code 28/18

LOAD DIVIDEND - CODE 28/18

T"'U"

& _E Entry Adv

rrg 32
01.62.30.1

Not

(&)_Cyc

WrDr
01.56.18.101.56.19.1

t

MBR Odd MBR Even
Ctrl
Set C Bit Set C Bit
01.40.07.1 01.40.17.1
Incr +2
Block
01.55.03.1 Memory SA
First
01.30.40.1
Cycle
01.63.10.1

Units
Cycle Control
01.62.31.1
Console Lamp

Iv'AR C

rh
01.57.24.1

Iv'AR C
Hund
01.57.20.1

MAR 8
Tens
01.57.16.1

Iv'AR C
Units
01.57.05.1

(00080 in MA R)

Lomp

l

OR-l
Wr Dr
01.56.17.1

OR-l
Rd Dr
)IE Cycle 01.56.16.1

-code 28/18 OR
01.65.01. 1
~Not lst
&
Cycle
R5-D6

r~M

MDR F Bit

Decrement
01.60.05.1 rg

&

'BAdv

1 rrg
*6'i.63.30.1

Lamp

'M

!'' '"
~

"m ~.~
01.56.16.1

Not rNrW2-D3
Comp
OR-2
Reod Y
Wr Dr 01.30.35.1
1st Cycle rrg
01.56.17.1

First Cycle..- &

Code 28/18
Inv

MDR_ &
F Bit

& _E Cycle Adv

rrg 28
01.60.58.1
Lamp

I Cycle
Reset

L-

Rd Dr
01.56.16.1

MDR
F Bit
rrg
01.46.01. 1
(Cleor F Bit)

Byposs
Rd Dr
Wr Dr 01.55.02.1
01.56.18.1 01.56.17.1

SF OP
01.60.59.1
Not
MF
Comp

-<&J- Not Codes

Reset

Reod Y
01.30.35.1

y

I Cycle Entry
01. 15.05.1

43/44/45

MDR F Bit rrg
01.46.10.1
(Set F Bit in 00099)

DIVIDE FLOW DIAGRAM
Carry Out

E-Cycle Entry (Begins Withl
Divide Subtract Cycle)

rrg 45

&

Proceed With New Divide Subtract Cycle

No Carry Out

(Complement Add)

.gJ

Enter Divide Add Cycle
(True Add)
Not FM No. 1
rrg 14
&

rrg 45
FM No.2
rrg 14
FM No.2
rrg 14

I

L..i

'-------1

L--

11

I

1Not 1st Cycle
fMDR F Bit

Set FM
NO.1
rrg

13

12

&

Reset
Carry
Out
Trg

Read Divisor Digit
from Memory per

FM No. I
Divide Add

Set
FM No.2
Trg
Read Digit of
Dividend Field

OR-I and Store it in from Memory
(Product Area)
DIS REG Units.
Per OR-2 and
(Decrement OR-l to Store it in MDR.
Prepare for Reading

Next Higher-Order
Digit of Divisor
from Memory ..

(Write Back
OR- 2 Bypassed to
Maintain Difference Digit

Turn off T/C Trg
for Divide Subtract
Cycles. Turn on TIC
Trg for Divide
Add Cycles.

During Trg 14
Time. r urn off
High/Plus rrg

t

14

I-

+

1

J..~

Set Carry Out Trg

rrg 43

~',";';d' C,oI,

Kf5

I

Enter
I-Cycle

21

FM~

NotDivideAdd
(Divide Subtract)
Incr Value of Quat
Digit in M/Q Reg
Units by One.

Write ADD rable
Develop and Set
ADD Table Address
Digit Into Product
in MAR. Read ADD Area per OR-2.
Table Digit from
Memory into MDR.
(Clear Any F Bit
Denoting Carry
Before Placing
ADD Table Digit

~

42

Write Quotient

Carry Out

&

Divide Add

Not FM No.2
FM No.1
Not Recomp Ctrl

Tim

MDR F Bit
1(& FMNo.l
Carry-In
I-riC Sw 9

&

&

Not Divide Add
(Divide Subtract)

&

Code 29

Set FM No.2
Trg
Block MAR Reset
to Prevent VRC
Error.

Set Zero in
DIB REG Units.

Digit into Memory (Product Area)
Per OR-2 from
MjQRegister Units.
(Set F Bi t for
Quotient Field
Definition on
First Divide

Cycle. Set F Bit
for Sign of
Quotient on Last

Divide Cycle if
Highft'lus Trg is
off

in Product Area.

Write Back OR-2
Decremented .. OR-2 is Used to
Read Next Higher-Order Digit of
Dividend from Memory on Successive

Turn off Equal/
Zero rrg if
Quotient Digit
is Other Than
Zero.)

I,

43

I

,I- Y-,

I

Y
Irc"",o.ii.
44

I

I

Increment OR-3
Reset FM No.1 &
to Prepare for
FM No.2 rrgs
Shifting the
Subtraction of
Carry Out
the Divisor
From the Dividend S.et.
Reset
D,v,de
Divide
One Position to
rrg
Add
rrg
Add
the Right.

furn 9ff First Divide Write OR-3
Cycle rrg
Bypassed Into
After Entry of
OR-2 to Establish
First (High Order)
Position of the
Quotient Digit
Dividend with
Into Memory. Reset Which the Units
M/QRegister to
Position of the
Zero for Deve lopDivisor will be
ment of Next
Associated on
Quotient Digit.
Next Divide Subtract or Divide
Add Cycle.

and Turn on

Subtract and Add Cycles; Also to

Dividend & Re-

Store Quotient Digit During Trg

mainder Sign Trg

42 Time.

Write Back OR-3 Bypassed to Maintain Address if Required for Subsequent Divide Subtract or Divide
Add Cycles.

Set Carey In Trg if Carry Out rrg
is on from Trg 13 Time. Set
F B;t for Remainder Field Definition on Last Divide
Cycle. Sat F Bit for Sign of Remainder on Lost
Divide Cycle if Dividend is Negative.}

rurn on Last Divide Cycle Trg
rurn Lost Divide Cycle rrg
When 00099 is Read into MAR.

on Last Divide
Change Status of
High/Plus Trg on Last Cycle if DiviDivide Add Cycle if dend is Negative.}
Divisor is Negative.)

Write PR-I Bypassed
into OR-l to Define
Units Position of the
Divisor for Next
Divide Subtract or

Divide Add Cycle.
Write Back PR- 1
Bypassed to Ma into in Address of
Units Position of
Divisor for Subsequent Divide
Subtract or Divide
Add Cycles.
Turn on First Cycle
rrg.

22

DIVIDE DATA FLOW - TRIGGERS 11,

12, 13,

14, AND 21

Trigger 11
Obtain
Divisor Digit
Trigger 12
Obtain
Dividend Digit
Trigger 13
Set Add
Table Address

Add and
Subtract
Triggers
(Divide Subtract and Divide Add)

Trigger 14
Read Y
Sum Digit To
Dividend Area

Not FM

Div Add

FM 2
Not FM 2

Trigger 21
Dummy Trigger
Set "0" in DIS Reg

Not Div Add

23

DIVIDE - CODE 29/19

I E Cycle Entry __&_Code 29/19

Code 29/19
Code 2i/11
Ol( Code 22/12
~Code 24/14
01.20.20.1

01.65.02.1

First Divide

Cycle Trg

Trg 42
01.65.06.1

E Cycle Entry

01.60.11.1

__ Set Quo

~

.-J
Carry In

High Plus

Equal/Zero

Trg
01.60.40. I

Trg
01.60.41.1

Trg
01.63.40. I

t

Trg 14
Rd Dr
OR-I
& Set 01.60.14. I
01.56.14. I Wr Dr
Dis
01.56.15.1 Units From
MDR
01.50.05. I

&_E Cycle
Entry

Trg

1st Cycle
Ol.lil.Il.1

T/C
L.-.-------r-;O:--:--;;-TT7,,-~'" Trg
01.63.20. I

Reset Quotient Counter

Bypass
OR-2 01.55.02. I
21
WrDr
01.60.31.1
01.56.17.1

latches
01.65.07.1

01. 50. as. 1
M/Q

etrl

Reset

&-.S,Adv

Corry In Trg

Dis

Units

M/Q

M/Q

Not
Recomp

4 Sit-J

t

Q: :t~t ~:i: ~t

QC 1

Lotch

Latch

.f

Latch

t

~

01.65.07.1

01.50,05. I

01.63.40.1

TIC Switch C Sit

Not

FM 1

Trg 43

Trg
Trg
Trg
Trg

11
21
42
44

Set F Bit

(Field

Step Quotient

Cleor F Bit (Carry) Def~~tion

{Increase Value
Of Quotient
Digit By

Remainder)

One.)

FM 2

24

DIVIDE DATA FLOW - TRIGGERS 42,43,44, AND 45

Trigger 42
Read In Quotient
Digit to Memory
Not Last
Div Cycle

Trigger 43
Shift
Last
Div
Cycle
I-Cycle

Trigger 45
Restore Divisor
Units Pos
M/Q 8

M/Q2~
I-Cycle

25

DIVIDE - CODE 29/19
FRO M Teg Page 23

Set C Bit

Dis Units
01.50.07.1
FromTrg 14

Allow Reset

of MDR
01.40.03. I

Equal/Zero Tr9

01.60.41.1

(lnce)

First Divide
Cycle Trg

01.60.05.1

01.65.02.1

Deer Trg

Not Last Divide Cycle

Reset

MiO Reg
01.62.50.1
01.62.52.1

& --A Adv

Teg 14
01.60.14.1
OR-2

OR-2

Rd Dr
01.56.16.1
&~B

fv\AR 1 Units

No'
MaelTTh
MAR C T Th
T4-D7

Deer Tr9

Wr Dr
01.56.17.1

(Dea)
01.60.05.1

Adv

M/Q Reg 2 Bit
M/Q Reg 8 Bi'

01.65.08.1
PR-l

PR-l

Rd Dr
Wr Dr
01.56.18.1 01.56.19.1

Trg

TrQ

01.63.30.1
Enter I
Cycle

01.15.05.1
&_AAdv
I Cycle

f Rese"

>Ie

Teg 11
=--t01.60. 11. 1

OR-l
Rd Dr

OR-l
Wr Dr

01.56.14.1

01.56.15.1

First Cycle Trg

01.63.10.1

BRANCH - CODE 49

26
Code 49

*-

& ___ E Cycle Adv

Console Lamp

Not
Code 42

T4-D4

(Reset)

OR-2
Rd Dr
01.56.16.1
& -

IR-l
Rd Dr
01.56.10.1

BAdv

Not Code
23/13
I Cycle
I Cycle Entry

Block MAR
Reset
01.59.10.1

Bypass
01.55.02.1

BRANCH AND TRANSMIT - CODE 27/17

27

Code 27/17

t
& -

E Entry Adv
(A Adv Time)

T4-D4
(Reset)
IR-2
RdDr
01.56.12.1

1st Cycle
01.63.10.1

Bypass
01.55.02.1

IR-l
Rd Dr
01.56.10.1

IR-2
Wr Dr
01.56.12.1

& __ B Adv

Code
27/17
01.60.45.1
Not E
Cyc Ent

~

Not Code
28/18
01.60.56.1
E Cyc Adv
(A Adv Time)

Console Lamp

01.10.25.1

&

R5-D6

OR-2
Rd Dr
01.56.16.1

C4
IR-l
Wr Dr
01. 56.10.1

Bypass
01.55.02.1

OR-2
Wr Dr
01.56.17.1

(T4-D7)
Not C6 Not C9

X

(R5-D8)
C6

....-------'

Trigger 26
01.60.57.1

l

T4-D15
Special Write
Gate-MARS

#,E Cycle

Wr Dr
01.56.15.1

MDR F Bit
Not First Cycle

&

R5-D6

'BAdv
Trigger 27
01.60.57.1

Not
Code 72
01.60.57.1

W2-D3
Rd Dr
01.56.16.1

Wr Dr
01.56.17.1

1st Cycle
01.63.10.1

Read Y
Point
01.30.35.1
FM 1

Code
27/17

I Cycle Entry

28

BRANCH BACK - CODE 42
Code 42

& __ E Cycle Adv

Trigger 18
01.60.48.1
Console Lamp
(Reset)
T4-D4
IR-l
Wr Dr
01.56.10.1
Code 42

IR-l
Rd Dr
01.56.10.1

R2-D5

PR-l
Rd Dr
01.56.18.1

Save
Control
01.06.15.1

Console Lamp

Not Code 23/13
Reset

(Mult)

Block
MAR Reset
01.59.10.1

I Cycle Entry
01.15.05.1

IR-2
Rd Dr
01.56.12.1

BRANCH ON DIGIT - CODE 43

29

Code 43

Code 43
MDR2

MDR 8

OR-l
Rd Dr

01.56.14.1

R5-D6

oAdv
E Cycle
Trigger 29

01.60.59.1
Console Lamp

Code 43

Block MAR
Reset

+5 On Digit

01.59.10.1

I Cycle
Entry

I Cycl e Reset

01. 15.05. 1

Console Lamp
Block MAR
Reset
Not Code
23/13
I Cycle __
Reset
I Cycle Entry

01.59.10.1

BRANCH NO FLAG - CODE 44

30

Code 44
Not Trg
18 Gate

Code 44
OR-l
Rd Dr
01.56.14.1

Console Lamp
Console Lamp

Block
MAR Reset
01.59.10.1
E Cycle Adv .... &
I Cycle
Entry

Trigger 18
01.60.48.1

01.15.05.1

T4-D4
(Reset)

IR-I

Wr Dr
,
01.56.10.1

IR-I

Rd Dr
01.56.10. I

Block MAR
Reset
01.59.10.1
I Cycle
Reset

I Cycle
Entry

Bypass
Oi.55.02.1

BRANCH NO RECORD MARK - CODE 45

31

Code 45
NotTrg

.~

18Gate~

--f§[r
Code 45
01.63.50.1
OR-l
01.56.14.1
Rd Dr
R5-D6

-5 Digit/RM

E Cycle
B Adv
Console Lamp

Code 45
01.60.59.1

01.60.59.1

-5 Record Mk _ t - - - - I - - - - - - '

Trigger 29
01.60.59.1
Console Lamp

Block
MAR Reset

E Cycle Adv __ &

I Cycle Entry
01.15.05.1

Trigger 18
01.60.48.1

Bypass
01.55.02.1

Wr Dr
01.56.10.1
Rd Dr
01.56.10.1

&_ BAdv

Not Code
23/13

I Cycle Entry

Block MAR
Reset
01.59.10.1

BRANCH INDICATOR,

32

Digit/Branch

Trg 7 ON

BRANCH NO INDICATOR

Indicator

Reg Code
01 Program Sw 1
02 Program Sw 2
06 I/O Read Chk
07 I/O Write Chk
08 MAR Chk
16 MBR- E
VRC
17 MBR- 0
VRC
Not C7
(T2-D7)

Indicator

01.25.35.1

Digit/Branch
Reg Code
Program Sw 3 03
Program Sw 4 04
O'Flow
14
11
High/Plus
Equa I/Zero 12
HP/EZ
13
Any Data Check 19
Last Card Br 09
Code 47
BI-BNI

Not C4

Console Lamp
E Cycle Entry

E Cycle Entry

E Cycle Entry

E C yc Ie Entry

BT Trg Off

Code 47
01.20.42.1

01.25.40.1

BT Trg Off
01.25.40.1

01.60.48.1
E Cycle Adv ..... &

I Cycle Entry

T4-D4
(Reset)

01.56.10.1

Console Lamp

Reset
01.59.10.1

Not Code
23/13
01.60.49. J
I Cycle Entry

I Cycle

Bypass
01.55.02.1

SET FLAG, CLEAR FLAG

33

E Cycle Adv

Console Lamp

SF-CF
OP

Console
Lamp

OR-2
Rd Dr
01.56.16.1

Code 32
01.60.59.1

01.46.10.1

Read Y
01.30.35.1
Code 33
01.60.59.1

Block
MAR Reset
01.59.10.1
Not Code
43/44/45
Enter I
Cycle
01.15.05.1

I Cycle
Reset
Collector Pull Off

READ NUMERICAllY - CODE 36 (36PPPPPQ01QQ)

34

Inv

Code 36

'---~_4DP

DP:lE--..:--J
Not Write
Num Intlk

Write

Num Intlk

For Numerical Only

CRCS-2

R3 with Rl Picks Rl0

CRCB-I ....

Time

Rl0 Picks the Shift

Time

Solenoid which Shifts

~::~:~ri;~~f:n~

Write

Not Write
Num Drive
(R3-l T)

Num Drive

(R3-lP)

NOTE: Selector Common Contact #2

Must tv1ake After and Break
Block

MAR

Rd;\Vr Call Trg
01.64.14.1

Reset

C-4
(W5-Dl)

Space Interlock

Contact #1

Not C-3

Before Selector Common

Space Interlock

Contact #1

Contact #2

01.59.10.1
Stop Clock

Console lamp

01. 10.05. 1
01.81.10.1

Inv

Response Gate

Not Punch
No Feed

01.80.25.1

l-o_---_ _t----Con$Ole
Not Disc
Gate

448",

Tape Sync

L

Inv

R54-1

01.81.45.1

~-----'lI:DP

No'

CRCB- I
Not
Sel 4

R54-lP

R54-lT

Keyboard

Not CE
Sw 9
R-S Key

Sync rrg

01.64.13.1

MemOF

Timeij

Unlock

Lamp

No,

Rd Chk
01.81.45.1

•

Console Lamp

Console

~-,..:l:::o:::m!:...-p--..,_~__-I/OExit

t
t

No ,sel4

&~BAdv

A TrgON

J

t

InsCtri

MAR 00099

Trg31
01.64.11.1

(RI-D1O)
C-2

Run
Trg OFF

OR-2

Bypass

Rd Dr
01.56.16.1

R2-D5

OR-2
WrDr
01.56.17.1

Reset Off:

Response

Chk Latch

Trg 30

A Adv

Response Gate
Flag Trg

Response

Chk Latch

01.82.30.1

MemOF

Ins 1
Ins ettl
Ins 2
Console Lamp

& ...... B Adv

Rd 8 Num

OR-2
Rd Dr
01.56.16.1

OR-2
WrDr
01.56.17. I

01.~~a.~:. 1

Flag Trg

01.81.10.1

READ NUMERICALLY -

CODE 36 (36PPPPPQ03QQ)

35

.----- ---------- --,

Code 34/36/37

E Entry Adv

:

Not

:

,:

Rdy Relay

,:

I
I

'
'

:

Se131/0:

,,

,

Hold Trg
01.64.12.1
Conso Ie lamp

I,
:
!,,

&"Not Mom OF
'Not Digit/RM

Block

MAR

C4

Reset

01.59.10.1
Console Lamp

(W5-DI)

:
:

Not C3

1______02·~5.:.1~.!.. ___ ..J

Rdr No
Feed Lamp

Stop
Clock
01.10.05.1
Response

Rdr Data

Gate

Rdr Data

Gate

Response Check Error

Gate
~Release

---.....

Stop Trg

Sync Trg

01.06.11.1

&

Rdr
Rdy

Key
I Cyc
Ent

Not
EOL (Tape Level 8)

•

Set MDR
Sample I/O

& _NPRO

Sel3
Hold

~

Non
Process

&

Run Out Trg

01.83.10.1
01.64.13.1
C8
(W0-D5)
C3

I/O Exit_
Trg
01.64.13.1

Sync Trg
Console

Rdr
Not
Rdy

Lamps

Disc.
0l.$O.2S.1 ....G_a_te_ _ _r
&

Console
Lamps

Not Mem
OIFlow

Not Sel 4

---------

Console Lamp

To Input Translator

Trg 31
01.64.11.1

Resp Check Latch

Trg 1

I~.

______P-.J& Reset

R2-D5

Console Lamp

Rd Call

T3-D7

Gate

WrDr
01.56.17.1

Set MDR
Sample
& -BAdv

~HOld Trg

--I0l.64.12.1

Set RM
in MDR

Rd
Chk

INPUT TRANSLATOR

0

R55-1
01.81.50.1

+48 v

}

..f -5 Keyboard

Int

Flag Trg
01.81.10.1
1622
X Bit

OR

Int

..>

1622

1622-()R

Sell

OBit

OR

4 Bit

PT EOl
01.81.15.1

1622
1 Bit

Rd PT 4
01.81.15;2

Rd PT 8
1622
2 Bit

+5 Rd Bus
X/Flag

-5 Rd Bus
X/Flag

Inv

Inv

+S Rd

Bus C

-S Rd
Bus C

~; Rd
Bus 0

PT EOl
01.81.15.3

+5 Rd
BusS

"Bus 0

Inv

Inv

tlnv

-S Rd

Rd PT 1
01.81.15.3

OR

PT EOl
01.81.15.2

Inv

OR

Rd PT 2

1622
8 Bit

rnv

-5 Rd
Bus X

-5 Keyboard
1 Bit

.>

Rd PT 0

Rd PT X
01.81.15.1

+5 Rd
Bus X

rnt

.s--5 Keyboard
2 Bit

-S Keyboard
4 Bit

..r

R57-1
01.81.50.1

01.81.55.1

Int

-S Keyboard
8 Bit

..r

+48v

R58-1

01.81.55.1

Int

-S Keyboard
OBit

-S Keyboard
C Bit

.r

X Bit

R59-1

R60-1
01.81.55.1

01.81.50.1

Int

Int

Int

~~,

C Correction

Relay Network
01.81.55.1

8

+48 v

+48v

+48 v

+48 v

0

8

0

CD

0

Flag Key
+48 v

+48 v

-S Rd
Bus 8

+5 Rd
Bus 4

-S Rd
Bus 4

+5 Rd
Bus 2

-S Rd
Bus 2

Inv

+5 Rd
Bus 1

-5 Rd
Bus 1

Not Rd
Bus 4
Not Rd

Bus 8

Not
Rd Bus 1

Rd Bus 0
01.80.30.1

Rd Bus 4 ------

&

ReI Bus 2
Rd Bus 8

Rd Bus 1
Not Rd Bus 2

... o~"•••,.
Rd Bus ,

Inv

Inv

~

Inv
-5 Rd
O. 1

-5 Blank

-5 Rd
NumO·

+5 Rd

NumO

-5 Rd Bus
0, RM

-5 Rd
8,4, Not 1

+5 Rd
Spec Char

-5 Rd
Spec Char

+5 Rd
8, 3

·,·"t·. ·
Rd Bus 4

Not Rd
Bus X/Flag

Not Rd Bus 8
01.80.40.1

01.80.40.1

-5 Rd
8,4, 1

INPUT TRANSLATOR

-S Rd

-S Rd

Bus 0

Bus X

Not Rd

Code 36
(RN)

B,4, Not 1

Not Rd
Nu'mO

Not Rd

Bus 4
Code 36
(RN)

Not Rd RM

Not

Bus 2

Rd RM

Set MDR
Sample I/O

Set MDR
Sample I/o
Code 36
(RN)

01.45.05.1

Not4, Rd1
B,

01.46.10.1

Not Rd

Bus 0

01.45.05.)

Rd Bus 1
Set MDRI/O
Sample

Not Rd t s e
D R I/O
8,4,1
&t M'Sample
01.45.07.1

01.45.07.1

MDR 1 Bit

MDR 2 Bit
01.45.07.1

01.45.07.1

Not Rd

Bus X

Not Blank

NotRd Bus
, X/Flag

Not Rd PM

01.Bl.41.1

ReI Bus
X/Flog

Not Rd Bus

NotRd
Bus 0

X/Flag

Rd Num 0

Rd Spec Char

&

t

Not
B, 4,Rd1

Set MDRI/O
Sample

MDR 4 Bit
01.45.07.1

MDR B Bit
01.45.OS.1

MDR C BH

MDR F Bit

01.45.05.1

t

Rd 2 Num

Rd Bus 4

Rd B, 4, 1

NotRd
Bus X/Flag

Not Rd R/M

Not
Blank

Not Rd
Bus 0

Rd Num 0

01.Bl.41.1
Not Rd
Num 0

-S Rd
Bus 0

Not Rd
Spec Char

-S Rd
Num 0

~----~ORr-----~

Rd Bus 0, RM
Not Rd 0, 1
+S MBR Even
Not F Bit

Rd 1 Zone

01.81.30.1

Rd 2 Zone..J
I/O RA Sample

01.40.17.1

MBR Even

C Bit

01.40.17.1

I/O RA Sample

01.4O.1B.l

MBR Even
4 Bit

01.40.1B.l

&

lORA Sample

01.40.19.1

MBR Even
2 Bit

01.40.19.1

I/O,RA Sample

01.40.19.1

MBR Even
1 Bit

01.40.19.1

READ ALPHAMERICALLY - CODE 37 (37PPPPPQ03QQ)
From Trg 31

Console Lamp

OR-2
OR-2
Wr Dr
Rd Dr
01.56.17.1 01.56.16.1

Inv

Rd

Incr +2
01.55.03.1

Rd Chk
&--

Block F Bit C2
Reset
MBR-O
MBR-E
and MDR
01.40.03.1

1.

Rd Chk
101.81.45.1

Sync Trg
01.64.13.1

Block
Memory
Sense Amp
Strobe
01.30.40.1

Inv

MDR F Bit
01.45.05.1
01.45.07.1

Not MDR F Bit

MDR C Bit

MDR C Bit Lamp

r----- Console

Lamp

MBR Even Trgl'
01.40.17.1
01.40.18.1
01.40.19.1

MBR Odd Trgs
01.40.07.1
01.40.08.1
01.40.09.1

39

WRITE NUMERICALLY - CODE 38
WRITE ALPHAMERICALLY - CODE 39
DUMP NUMERICALLY - CODE 35 (00100)
Write Co 11 Gate (Codes 35, 38, & 39)

!

"Not Sel 4 I/O

~,

E Entry Adv
Trigger 30

01.64.10.1
Console lamp

Not Write

Record ~rk

Write
Num Intlk

Num Intlk

Sync irg
01.64.13.1

CRCB-2

01.63.50.1

CRCB-l-,

Time

(Turn ON Digit/RM irs)

Time

Write
Num Drive

Not Write
Num Drive

(R3-LP)

(R3-LT)

Block NAR
Reset

For Numerical Only

01.59.10.1

R3 With Rl Picks Rl0
RIO Picks the Shift
Solenoid Which Shifts
the Typewriter Into
Numerical Shift

Stop
Clock

01. 10.05. 1

Rl-3

+5

I-lnv_ _-,}01.64.13.1
DP Not Hold
'-"'''-'=::'''':'=''-''=---JI1

CO"

CEven~

Code
39

1 Bit

MDR

MDR

MBR 2
Bit

2 Bit

4 Bit

j~m'

Even

Code 39

Not
Code 39

1:.1

MDR 1 BH

MDR 2 BH

MBR Not
2 B;t Ev MBR
Not 4

Not
W,
Rm

Pch CX841

Iny

Inv

OR}-------'
01.82.20.3

Iny

Inv

Inv

Inv

Iny

Inv
01.82.22.2

Inv
01.82.20.2

DL

DL

'"~
'"
'"
;;

R22
R25

@f
01.82.75.1

Punch

X Bit
02.84.50.1

~

R28
R31

@Y

Punch
1620
OBit
X Bit 01.82.75.1
04.84.50.1
to 1622
04.83.05.1

Iny

Inv

oi
~

;;

" f"-

01.82.52.1
R21

@Y

Feed
01.84.20.1

DP

DL

;;

01.82.52.1

~

'"oi
~

DP

DL
M

'".,;
R50

GY

Punch
1620
Punch
1620
C Bit
8 Bit
01.82.75.1
OBit 01.82.75.1 C Bit
02.84.50.1 to1622
02.84.50.1
to 1622
04.83.50.1
04.83.05.1

fi

R41

1620
8 Bit

Inv
01.82.20.3

0'

01.82.75.1

to 1622
04.83.05.1

Punch

4 B;t
02.84.50.1

1620
Punch
2 Bit
4 B;t 01.82.75.1
to 1622
02.84.50.1
04.83.05.1

0.i

OR

Tope

DL

01.~~0.1 ~
DP

1620
Punch
2 B;t 01.82.75.1
1 Bit
to 1622
02.84.501
04.83.50.1

fi
;;
1620
1 Bit
to 1622
04.83.50.1

42

WRITE NUMERICALLY - CODE 38

WRITE ALPHAMERICAllY - CODE 39
DUMP NUMERICALLY - CODE 35 (Q02QQ)

E Entry Adv

I/O
Wrife Call Gate (Codes 35/38/39)

Tope feed Switch
+S~ 02.84,50.1

Sel3
Se! 2

OR

~..r--t=cc;---rH--k=-=--r--------------';(M""24~~~~go)

Typwr

Resp

Ndt Tope

Response Gate

feed Code

01.80,25.1

No Feed Megnet

02.84.50.1

(To Punch Mognet! 02.84.50. I)

Output Trons
Error

01.82.30.1

No>
Sel
Write
41/0 Call

~

Gote

& Digit/RM

N-:-'
Sel4

Not Tope Feed
Intlk

PCS-3
Start
Clock

Resp Chk
01.82.30, T
SHINI
Ind-07

Sel2

CONTROL - CODE 34 (34PPPPPQOIQI SPACE
2 CARRIAGE RETURN
8 TABULATE)

43

Code 34

E Entry Adv

Console Lomp

1/0

Sell

Code 34

Block MAR
Reset
01.59.10. I
Stop Clock
01.10.05. I

+48 v

r

Select 1

1/0
MDR
8 Bit

MDR
I Bit

01.81.50.1

DP

R4
Return

P

Not
Sell 1/0

01.82.70.1

Tobulote

CRCB-6 (M 310"-B 360")
01.82.70. I

+48 v

Disconnect Gate Trg

+48v
CRCB-4

f

1

Tab
Intlk
Contact

Corr
Rtn
Inllk
Cont

1

Spoo<
Intlk
Cont

11
6-3

R19 Hold
Console Lomp
Reloy 19
01.80.25.1

Enter
I-Cycle
Trg I

+48 v
5-2

19-3

Carriage

~I'
1 ~r; cD

6

~WYI"

ACC suaT FLCW CHART

HP- ON EQIO OFF(EP>EO)

+

HP OFF EO/O OFF (EP6,i I J. 1

OR~----------------------J

L3

orr

Wl04

II OFF

R304

01.68.10.1

1I

L2
01.68 10.1

01 68. 10.1

CE LAMP

CE LAMP

~R~JO~4~__--..

B4---------------------,

l3 ON

WI 04 _______

8

BLOCK

REsEr
fIRST C'r'
TR
01,63. 10 . 1

NOTE:-THIS

PORTION

15 ALSO S!fJWN ON DIGIT FORCE

CHART PG 55

UNDERFLO

OR EQ 9
F!RST CV

>-__-.-________

.....--_.( B>-__

~----------

UNDERFlQ OR
---<~-EQ ZERO

01.66.92.1

NOT HI
PLUS

SET MOR F
(FRAC SlGN)
01.46.1 0.1

0\ 66.72.1

SET HDR F
(EX? SIGN)

SET EQ

SET MOR F
(E~P FIELD)
01.46.10. I

ZERO ON
01,60.41 I

~

~

01,46.10.1

SET MOil. 8
01.4S.05.1

~

~

I 24 OR 26 1

~
MODULO 3 erR CTRl

I

I
W1

L1

W1

L2

I

11.3

W1

BLOCK TURN OFF OF F I RS1 CV

RJ

I

L3

~I--------~--------------------------------------------------_SSF'RE'ET

FIRST

cv

W2

I

SET MOR I
01.45.07.1

MULTIPLY" DIVIDE
FUN CHART

57

-*I CYCLE

1

-45-

D:P. ADD

OP 03

1

OP 09

1 -. -

-58-

MULTIPLY

FRAC

LOMPARE

SEE NOTE I

1

-60-

FALSE XHIT
SEE NOTE 2

1

-61-

L~~T~~VIDEN:

1-*LOAD DIVIDEND

1
I

-62-

.-51DIV. ENTRY

EXPONENT
MODIFY
ENTRY

1

1 .... -

-52DIVIDE

EXPONENT
MODIFY

J
,

-53-

EXPONENT
MODIFY
EXIT

NO

~4ono

ORooO?

-63RESULT
)("IT

@
-*- SEE

BASIC FUNCTION CHARTS

NOTE I: FNACTION COMPARE DETERMINES THE ADDRESS FOR LOAD DIVIDEND
IF
P>Q (HP ON I IOO-L
P99 TR OFF). P FIELD OXXXXOO.
AFTER EXP MODIFY THE P FIELD WILL CONTAIN xxxx99 AND OVERFL.OW WILL BE OFF.
THIS IS ACCOMPLISHED 8Y OVERFLOW CORRECT RESETI NG THE OVERFLOW LATCH.
AND BLOCKING RECOMP CTRL. BV SUBTRACTING A ONE FROM OcHAND BLOCKING RECOMP)
THE EXPONENT WILL. BE 99.

ENTRY

~

tTEM

45

EX1T

TO PG

I

FORCE OP 23

2

FMUL
TO EXP MODIFY ENTRV

3

EXP MOOIFY REQ'O

4

BLOCK TURN ON
TRII 21 2342
BLOCK FP EXIT
SEE NOTE I PAGE 20

5

·'P~M

LAST EXP ADD CYCLE TO
FMUL ENTRY

BASIC
CHART
51

52
BASIC
CHART

63

FRACTION COMPARE MODE

59

OP 09

LAST EXP
AOD eye
TO FRAC
COMPARE ENTRY

l

a

R3 04

01,66.12.1
FRAC. COMPARE
ENTRY
01. 67.10.1

SET (aMP

01. 63. 20.1
TIc OFF

ENTRV
RESET

----.I

01.6990.1
RESET ZERO

FILL MODE
01.66.60.1

I CYCLE

E CYCLE
ENTRY

RESET
01.15.10.1

TURN ON
TIC TR
(TRUE)
01.63.20.1

01.15.18.1

FRAC COMPARE
MODE

01. 66. 70. 1

......--_C.E.LAHP

INHIBIT TIC
CHANGE
01.63.31. 1

r-- --,
I

I

RESET EXP.

ADO MODE

FORCE
0,,4

I

I

1!.~.~:,:o~.J

01. 66. 10. I

\Jl04
01.10.35.1

FP RESET
01.69901

LAST

NOT FRAC
COMP ENTRY

MDR F
01.45.15.1

ADO eYe.

01.66.11. I

01.67.10.1

r-NOT FRAC. ADD Q
01. 66. 71. I

I
I
I

--,

FRAC COMPARE

I

TO FALSE XM IT

II

01.67.20.1
LL _____
.J

HIIPLUS

CHANGE STATUS
01.60.40.1

TIC-CHANGE
STATUS
01.63,20.1
ENTRY

FROM

PG

LAST EXP ADD CYC TO
FRAC COMPARE ENTRY

45

ITEM

EXIT

TO
PG

I

FRAC COMPARE
TO FALSE XMIT

2

FORCE OP 24

60
BASIC
CHART

F,\l~E

TR,'l,NSMIT

60
FRAC COMPARE
{TO fALSE XMIT

FALSE
XMIT "h)Jf

01.67.20.1
C.E.

LAMP

SlOCt< TR 25

RI:.SET

lO- OIV

FRAC COMPARE

ENTRY

01.67.10.1

r BLOCK TURN ONi
:

0167.32.1

TRrii.'l6·.~~,.~2

I

L ______

~

HIGH PLUS TR.
01.60.40.1

TURN ON
1ST CYCLE
01.63.10.1

fMUL CORRECT FLAG
01.4550.1

FP. RESET
01,69.'30.1

CONSOLE LAMP

SET

F~

01.63

FM 182

01.63.30,1

1
30. I

j - - - - i - - - - _ C O N S O L E LAMP

TR -24
L D ENTRY

01.67.31.1
WR-PR2
A-AQV

----.l

01.67.21. I

01.56.19.1
016721 I

NOT I ST eye
01.63 10. I

B

a

1ST cye TR
01 63.10. I

R3 04

'M I
01 63.30.1

i,LOAD
FAlsE XMiT 10- i
DIVIDEND· ENTRY,

RO-PR2
OI.~6.IS.2

01.,67.30.1
LI _ _
_ _ _ _ _ I'
.J

ENTRY
CL-PR2

01.56.18.2

SET MAR

ooxoo

.

F,.AC C.OMPARE TO FALSE XMIT

01.59.15. I

(

OECR INTO PR2

, ~~~ ri~~~~ ~9M~T cye

(FALSE XMIT ALWAYS ENDS
)
\WITH PR2 SETTING AT IOD-L

ITEM
)

NOT TN ceMP

01.60.45.1

EXIT

FALSE XMIT TO LOAD
Oll/IOENO ENTRY

FROM
PG

.9
TO PG
61

BASIC
CHART

LOA.D DIVIDEND ENTRY
TO

FALSE XMIT
LOAD DIVIDEND ENTRY

61

LO AD DiViDEND
ENTRY
01.67.30.1
LAMP

CE

DIVIDE
ENTRY
01.67.40.1
01.67.32.1

CONSOLE
LAMP

RESET ZERO
FILL MODE

1 cye
RESET

E cYe
ENTRY

01.66.60.1

OI.l~.IO,J

01.15.18,1

TURN ON

TIC TA
(TRUE)
01.63.20.1

GATE

II
8

a

ADV

01.10.

W6 012
OLlO.22.1

II

01.67.31.1

T4 04

BY PASS
01.55.02.2

II

BY

TURN ON
GATE T4 04

01.10.25.1

a~-------------1

01.10.36.1

01.67.32.1

PASS

01.55.02.2

RESET FALSE
XMIT MODE

01.67.20.1

WR PR-2

RD PR-2

01.56.19.2

01.56.18.2

CLEAR
PR-I
01.56.16.1

CLEAR
OR 2

(100-L)

01.56.18.2

CLEAR
OR-I
01..56.14.1

CLEAR
OR 3

01.56.IB.1

C9

TR 25
01.68.24.1
CONSOLE

LAMP

RESET
FM I
FM 2

1ST CY
TR ON

01.63.12.1

01.63.30.1

A ADV
OUO.36.1
LOAD
DIVIDEND

01.67,30.1

1

MODE

a~

NOT FALSE XMIT
01.67.20.1

II

01.67.31.1

WID4

a~------------------------------------------------~
01.67.32.1

01.10.35.1

ENTRY

RD PR-3

FALSE XMIT TO LOAD
DIVIDEND ENT RY

INV

ITEM

01.56.18.2
WI 04

BY PASS
OtS5.02.2

R3 04

WR OR I
01.51.15.1

LOAD DIVIDEND
MODE
01.67.30.1

IF P>Q: LD IN 100-L (BYPASS PR2 TO DIU)

P
()

I

fTl

;::
I>

--<

n
DETAILED DATAFLOW
THIS SECTICN SEE
00.00.13.1

DETAILED
0.'1 TAFLCW
THIS
SEC i ION SEE
00.00.12.1

en

o'"

o
o
o
o
o

U1

I ~~Wg~ L
I 01.30.15.1 r

I

FROM MAR

00.00.11.1

1J

MATRIX
SWI
TCH A
01.30.02.1

1

I S~m~XD

01.30.04.1

I

I
MDR-MBR
TRANSFER

01.46.10.1

I
I

I
I

I/O CONTROL

(lONE DATA)

DIGIT REGISTER
TENS
00.00.11.1

MULTIPLIERI
QUOTIENT
(01 VIDE OPTION)
00.00.11.1

110 CONTROL

(lONE DATA)

00.00.13.1

EVEN

--

ODD

,
01.30 1.05.1

I
l

l
I

SENSE AMP
EVEN

I
I

MBR

EVEN

01.40.17.1

I
I

1

MOR

01.45.05.1

I

-I

J>

."

:10

1

MEMORY
SA CONT

INHIBIT
ODD

01.30.60.1

I

01.30.40.1

i
VRC.10.1.1
01. 40

I

¥
J

ODD

01.40.07.1

g
o

01 . 30.45. 1 '

MBR

I

r

S EN550AMP

J

EVEN-ODD
TGR

01.43.10.1

.. ,I Y

I

tl H~.. ~J

101.40.20.1

00.00.13.1

I
I
I
I
I

01.30.50.1

01.30.65.1

VRe

,----.

l- I

INHIBIT
EVEN

T

t

MEMORY

;----A

I/O CONTROL

INUMER I C O.AT A)
00.00.13.1

a>

N

DIGIT REGISTER
TENS
00.00.11.1

o

OP REGISTER
UNITS
00,00.12.1

r

rDATA

BUS

110 CONTROL
(NUMERIC DATA)
00.00.13.1

DIGIT REGISTER UNITS

MAR TENS

MULTIPLY REGISTER
00.00.11.1

~ OP REGISTER TENS
00.00.12.1

o
o
o
o

~

TO
DECODE SW!T~

00. 00 . 10. 1

MAR

J---.
MAR

TEN

THOU

HUNDS

THQUS.

§r~§~.W~ll

UN} T5

TENS

01.57.20.1

01.57.24 .. 1
TO
01.57.2B.l

01.57.30.1

TO
01.57.24.1

1

01.57.05.1
TO
01. 57 .09.1

01.57.09.1
TO
01. 57.18.1

,"

r~'

_I

MAR VRC

ADDRESS CONTROL

0 1.56.05.101.56.09.1

01.59.10.1-01.59.15.1

~
WRI TE

READ
DRIVERS

I

I

IIE
CYCLE
TR IGGER~

DRIVERS

~

IR-I
01.56.10.1

IR 1

~
~

+-

IR 1
01.56.10.1

IR-2
01.56.12.1

1 R-2

l+-

01.56.12.1

OR-l

OR 1

~

OR-l
01.56.15.1

~
~
~

QR-2

OR 2

~
~

OR 2
01.56.17.1

~

OR 3

~
~
~
~

01.56.14.1
01.56.16.1

~
~
~

OR-3

L-...to

OR 3

01.56.18.1

I R-2

01.56.19.1

PR-I
01.56.16.1

PR 1

~

PR 1
01.56.19.1

PR-2
01.56.18.1

PR 2

*-

PR 2
01.56.19.1

PR 3
01.56.18.1

PR 3

~

PR-3
01.56.19.1

,

T

RO C D - 2 ' } - - '
T2 ( 0 ... 2)

B1 T DRIVERS

I

TEN THOUS

,
HUNDS

THOUS

01.55.59.1

01.55.58.1

I

l 01.55.57.11

0 1.55.56.1

10 1.55.55.

i

T

INCREMENT IDECREMENT SIN! TCH

TEN

THOUS

2 1 C

e
~

THOU

HUNDS

8 4 2 1 C

I ;: ;: ;!;! ;!

8 4 2 1 C

\.f1 \.f1 V> \.f1 \.f1
1JI1JI\J'I\J'I\}l

\.f1\J1
\Jl1JI

I.>lWWI.>lW

N

~

O'o--o-olJ'!

N

0'> 0'>

\J1
\}l

\J1 \J1 \J1 \J1 \J1
1J11J11J11J11J1

NN

N
VI

I-' 1-' ............
0'> (J\ -D -0 VI

0000
(J\ 0' >0-0

::;

1-' ....

1-''''' 1-'1-'

~

. .

-0-0

f

I

1

!

1-'1-' I-'

f't

TENS

C 6 4 2 1

00.00.10.1

U'I

\.f1\.f1

FRGM MDR

00.00.10.1

DATA BUS

\Jl\.f1

\J'I

\J'I

........ 1-'

00000
-J --J--J.o-o

~

00.00.10.1

IJ'!

00000

........

i

I

~lN

1

SWITCH
T/C
01.60.34.1

DECR -1

~

I

TIC
TRIGGER

0l.63.20.1

BYPASS

CARRY SW

01.60.38.1

J
DOUBLER HUND
01.62.60.1

rl
I

"""i"NCR+2
~

r

CARRy
TR IClGER
01 62.40.1

r--

I

I

I

II

DOUBLER UNITS
01.62.55.1

I

MPLR/QUOT REGISTER
01.62.50.1-01.62.52.1

I

I6 I4 I2

I

C

1

I
aN
o

! ! ! I
TO MOR
(0111 IDE 0 PTION)
00.00 10. I
TOS/BDE CODER
12.1

C 8 4 2 1

00000
-J -J-J-O..o

01.60.36.1

UN! TS

8888 88888
\.f1\.f1

-t

n

OQ. CO

~

..
....................
FROM M8R (VEN

,+~

I

T

DIGIT/BRANCH REGISTER

FROM MBR ODD

..

I I

I

'"
3:

IC (CARRY)
+1 sw

~

.

:r

R3 (D-2)
1<3 (D-2)

'J

~

\J1V>
\J1U'

\J1 \J1 \J1\J1
IJ1 U'lIJ1V1

..................... .....................
,.~~,.

8 4 2 1

Vl

n

~ T4 ([)-7)

c

6 4 2 1 C

I

TRIGGERS

UNITS

88888 88888 888e8

~

~

TENS

l4---1-{
J

UNITS

TENS

t

i

T

, ,

~ CYCLE
IIE

1-''''' ....

1-'''''

Jf

o
o
o
o

FROM MBR ODD

00.00.1 0.1

l
OP REGISTER
FROM MD R

00.00.1 0.1

TENS

UNITS

01.20.10.1 01.20.07.1
01.20.12.1 01.20.09.1

I

OP REG DEC
TENS

1 0 1.20.14.1

FROM

I

OP REG DECODER
UNI TS

j

01.20.13 1

1

01 B

REGISTER

00.00.11 .1

I
I

(/)

()

I

I
fTl

s:
l>

-i
()

OP DECODER

l

I

SIB DECODER

01.25.15.1
01.25.20.1

I

I

1

BRANCH
CONTROL
SELECT

01.20.19.1-01.20. 31.1

00.00;1 3.1

J SIB ~
1 01.. 25.25.1

PROGRAM
CONTROL

TEST

I

CYCLE TRS

01.15.05.1-01.15.18.1
E CYCLE TRS

01.60.03.1-01.64.14.1

--

a;
'"o

~

o

o

RUN TRIGGER

~6Lg6t~YGaEr.R'-----------------------------------~
Ol.64.12.1 ______________________________________

o
o

-{~~~~~

'"

TO MDR
(NUMERIC DATA)
00.00.10.1

TO MBR EVEN
~ZONE ~ATA)

FRCM MOR

0.00. 0.1

(NUMERIC DATA)
00.00.10.1

FROM MBR EVEN

(lONE DATA)

00.00.10.1

I/O CONTROL 01.64.10.1-01.64.14.1/01. BO. 05 .1-02. B4. 50.1

Ro-WR
CHECK

READ WRITE (ALL
I/O EXIT
DISCONNECT GATE
RESPONSE GATE

01.81.45.1

SYNC TR

HOLD TR

3UUU
01. 80. 25.1
3UUU
01.64.12.1

I/O STOP

01.06.25.1
01.64.14.1

19999 STOP

I

SELECT
01.80.05.1
01.BO.07.1

I

BRANCH

FROM SIB
DECODER
00.00.12.1

CONTROL

DATA TEST

01. 25.30.1

BRANCH
TEST TR
01.25.35.1

'---

J-----.

ERROR
C I RCU IT
CONTROL
01.06.12.1

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01.06.20.1
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SHOE CONNECTOR
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765432

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01.90.30.1

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,

XI

-

IS GROUND ON ALL SOCKETS.

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xIII

[!]

INDICATES A lDMFD CAPACITOR TO OIJ" PIN

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111. 1611. 1B. 1 •

16217

WIRING SIDE

26 27 26 25 24

23 22

21

2~

19 16 17 16

15 14 13

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o

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Q

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M
N

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26 27 26 25,24 23 22

I--

21 2~ 19 16 17 16

15 14 13

12 11

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- --"'9

-

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f- - - - -\5

4

3

2

--+GB+-""'ONC (FIRST POSITION ON BUS TO
ADJACENT PIN J ON. EACH ROW)
NOTES,

INPUTS SHOWN --+(iB+-~-36 VOLTS
ON 11'1._11'.17.1

X
XI

PIN J

IS GROUND ON ALL SOCKETS
INDICATES VOLTAGE CHAI~

XI I - - - - XIII

--+GB+-"",+12M (Bl)
--+(iB+-~-12 VOLTS

8

--+(iB+-~+12M

(Bl)

--+(iB+-~+12 VOLTS

'~

(!]

INDICATES JUMPER WIRE

INDICATES A 10 MFD CAPACITOR TO

IIJII

PIN,

VOLTAGE DISTRIBUTION
PANEL D

1629

WIRING SIDE
26 25 24 23 J2 2 21

2It 19 18 17 16 15 14 13 12

II

M
N

A
Q

I· -1--:--

-f--.

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I.

9

7

8

6

IlUJ~.19.1

5

4

3

2

I

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~ 42

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_3

.. 2

M

N

B
R

-.3

M

42

N

C

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Q

R

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-

--

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N
P
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N

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D

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43

F

Q

U

26 25 24 23 22 21

28 19 18 17

16 15

14 13 12

II

I. 9

8

5 4

7

3

+-~8

+48 VOL T5
P5TBI -7

VOLTS

01.00.33. I

01.90.30.1
+12VOLTS
PSTB 2-1
11.98.3'.1

-l2 VOLTS
P T8-1
_ .911.31.1

11~ t

2~

~ 3~ ~ 4~ ~

+48 MINUS
DC eND
1&1.9'.21. I

/
54 t 68 78 8~~

I

yM~
I+12M

l-12V

Y

I+12V

GND (FIRST POSITION ON BUS TO ADJACENT
PIN J ON EACH ROW)
NOTES.
~

PIN J IS GROUND ON ALL SOCKETS.
INDICATES VOLTAGE CHAIN.

Xl
XII

XIII

-----

I!J

INDICATES JUMPER WIRE

INDICATES A lUMFD CAPACITOR TO

IIJLI

PIN

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1620

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CONNECTOR REFERENCE SHEET GATE A

01.00,21.1

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AW-B

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AW- 0

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AX-F

AX

AX -

-G

0 1.41.04. t

0 1.41.03.1

01,66.20,1

01,05.50.1

01.40.07.101.41.04.101.41.03.1

01.66,30 I

0155.02.1

01.40.08.1

01

.0 I .8 I ,30. I

01.41.04.1

32

BWl

01. 41.04, I

01.55.03.1

01.40.08. I

0 I . 41 04. I

01.40,09.1

01,41.06.1

01.41.05.1

AX-k

J

01.41.01.
01.41.01.

01 , 66, 60, I

31

CON NECTORS

01.40.07.1

01.66 50.1

BWK

29
30

41.01. I

01.41.07.

01. 41.07.

AX-L

0167.00,1
01.67.00.1

01 66 85 I
01.56,16.1

01 67.0 I, I

01. 50.09,1

01.67.01 I
01,67,30,1

01,5618.2
01,66,71. I
01. 46.10 I

2
4

6

01,66.40.1

01.41.04.1

01. 55.15.1
01,57,05.1

01.40.09.1

01.41.06.1

01. 41.05. I

01 . 4 I ,07. I

0 I .67. 40. I

01.41.04.1

01.57.05, I

01.40.17.1

01.41.06.1

01. 41. os, I

01.41,07.1

01,67,40.1

8

01.66,70,
01,66,80.

01.41.04.1

01.57.07.1

01.40.17.1

01.41.06.1

01.41.05.1

01.41.07.1

01,67.90.1

01.63,30, I
01,66,81.1

01.66.80,1

01.41.04, I

01.57.07.1

01.40.18.1

01.41.06,1

01.41.15.1

01.41.07.1

0167.90.1

01,66.40.1

10
II

0166.81.1
01.67.00, I

01.41.04.1

01,57.09.1

01.40.18.1

01.41.06,1

01.41.15.1

01.41.07,1

0168.10,1

01.66,80.1

9
10

01.41.04.1

01.57.09.1

01.40.19. I

01. 4 I . 06. I

0 I . 41. 15 . I

01.41.07.1

01 68,10.1

01 10.25.1

II

12

01 67.10, I

01.41.04, I

01.57.16.1

01.40.19.101.41.06.101.41.15.1

01.41.07,1

01,68,10. I

01.66.70.1

12

13

0167,20,1

01.41.04.1

01,57.16. I

01.41.06.101.41.15.101.41.17.1

01.63.30,1

13
14

01,66.24. I
01. 66.44.1

14

01.67.30.1

01.41.04.1

01. 57,18. I

01. 05 .01.1

01.41.06.1

01.41.15.1

01.41.17,1

15
16

01,67.30.1
01,67.40, I

01.41.04.. 1
01,41.04.1

01. 57,18. I

01.05.01.1

01.41.06.1

01.41.15.1

01.41.17.1

01. 68.10,
01,68.24.
01.68,24, I

01. 41 . 06. I

01. 4 I . I 5 I

01.41.17.1

01,68.24,

17
18

01.67.40,1
01.66,90.1

01.41.04 I

015720,1
01. 57 .221, I

19
20

01.67.30,1
01,68.40, I

21
22

01.40.17.1

01.41,04.1

01.57.20.1

01,66.85.1
01,60.05.1

6
7
8

15
16

01.41.03.101.41.15.1

01.41.17. I

01.67.90.1

01.41,03,101.41.15.1

01.41.17.1

01.68.24.
01.68,40 I

01.68.90.1
01.68.85.1

01.41.03, I

01.41

01,41.17

01.68.40 I

01.41.03.1

01.41.15.1
01.41,IS.1

01.41.17.10168.42,1
01.41.17.1 01,68.42.1

20
21

01.41.03.1

01.41, IS, I

01.41.17. I

01,68.44.1

22

01.41.03.1
01.41.03.1

01.41.16.1
01.41.IS.1

01.41.17. I
01.41.17.1

01,S8,85,1
01,S8.85.1

24

01

57.07 I

17
18

01,41.04,1

01.57.22.1

01.40.18, I

01.41,04.1

0I.S8,42.1

01.40,18.1

01.41.04.1

01.57,24.1
01.57.24.1

01.68,44.1

01.40.19.1

01.41,04.1

01,57.26.1

23

01.66.25.1

01.40.19.1

01,41.04,1

24

01.66.21.1

01,40.19.1

01.41.04.1

01.57.26.1 01.06.30.1
01.37,28.101.05,01.1

25 01.66.23.1
2601.66.24.1

01.40.19,1
01.81.41.1

01,41.04,1
01.41.04.1

01,57,28,1
01.57,30.1

01.05.02.1 01.41.03,1 01.41.16.101,41.01,1 01,S6,80,1
01.05.01.101.41.03.101.41.16.101.41.01.10168.85.1

26

27

01.68.10.1

01,81.41.1

01.41.04.1

01,57.30.1

01.05.02.1

01.68.90.1

27

28

01.68.10.1

01,81,41.1

29

01.86.n.1

01.03·01,101.41.03.1
01,05.01.1 01.41.03.1
01.05.50, I 01. 41.03, I

0I.S9.90,1
01. 69, 90.1

01.66.24.1
01.00.15.1

01.57,30,1
01.57.32.1
01.60,05. I

01.41.01. I

30
31

01,41.04.1
01,41.04.1
01.41.04.1

01. 41 ,01

I

01.67.10.1

01.41.04.

01.60.05.1

01.60.30.\

01.41.03. I

01.41.01.1

01.66.85.1

2B
2j1
110
31

32

01.90.35.1
CE-80X

01.41.04

01.58.09,1

01.60.30.1
LAMPS ICONS

01.41.03.1

01.41,01, I

01,68.85,1

OXE

1623

lAMPS

01.68.24.1
01.68.24.1

01. 41.03. I

15.1

I

01.41.03.101.41.16.101.41.01,1

1623

01.41.IS. I

1623

01.41.01.1

1623

ax -k

01, 05.50 I

19

23

BX-l

CONNECTOR REFERENCE SHEET
GATE B

01.00.22.1

1620

W CON N ECTORS

BW CONNECTORS ARE THE SAME AS
AW CONNECTORS

REFER TO AWCONNECT(IBS

X CON NECTORS
BX-B

BX-C

BX -E

SX-F

BX-G

BX-H

8X-J

BX-K

eX-L

I

01 .64. 10.1

01. 16.10. I

01 .06, 05. I

01 . 25.30. I

01.05.50. I

01 .83.10. I

01 .45. IS. I

01 67.00 .1

01 66 . 85. I

I

2

01 .64.13.1

01. 16.20. I

01.06. 10.1

01 .45.50. I

01 .20. 07.1

01 .06.10. I

01 .45. 16. I

01.67.00.1

01.56. 16.1

2

3

BX-O

3

01 ,64.13

I

01 , IS. 20. I

01.06. , 1.1

01 .45. 15. I

01 .20.07. I

01 . 64. 12 . I

01.45. 16. I

01. 67 .01.1

01.50 09.1

4

01 .64.14.1

01 . I 6.2 I. I

08 81 .30.1

01 .06.15. I

01 . 45. 16.1

01 .20.07. I

01 .06. 10. I

01 .45 . 16. I

01,67.01.1

01 .56 . I B.2

4

5

01 .10.09.1

01 .16. 22. I 01 .80 05. I

01 .06.20. I

01 .45. IS .1

01 .20.09.1

01. 15. II. I

01 . 60. 54 . I

01. 67.30.1

01 .66.7 I . I

5

6

01 .64 .14. I

01.60. 11.1

01 .06.30. I

01 .45. 17. I

01 .20.09. I

01 .64. II . 1 01 .45. I 5. I

01 . 67.40. I

01 .46 .10.1

6

7

01 .80 .25 .1

01.60. 12..1

01 .06.05.1

01. 45 . 17. I

01 .20.' O. I

01 .64,13.1

01 67.40.1

01 .63 .30. I

7

8

01 .64. 10, I

01 .60. 13.1

01 .80. 20. I

01 ,10.\2. I

01 .50 .01.1

a I .67.90.1

01 .66 .81.1

8

9

01. 20. 35. I

01 .60. 14. I 01 .81 .45, I

01. 15. 10. I

01.50. 07. I

01 .20.10. I

01 .06, 10

01 . 25 .15 . I

01 .67.90.1

01 66 .40. r

9

10

01

20. 35. I

01 .60. 24. I 01 .81 .45. I

01. 15.11 .1

01.50 .07. I

01.20. 12 .1

01 . 64.10. I 01 .25 . '5. ,

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01 66 .80.1

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II

01 .20. 35. I

01 .60.31. I 01 . 80 05. I

01 . 15. 12. I

01.50 09.1

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I

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01 . OS. '0. I 01 . 25 .15 . I 01 .S8.10 .1

13

01 . 20 .31. I

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01

01. 15 . 14. I 01.62 .50. I

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01 . BO. 05. I 01 .45. 15 .1

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01. 60 .40.1

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01 . 60. 40 . I 01 .81 .30. I

16

01 . 20. 20 . I 01 .60 .41 .1

01

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a 1.60. 48. I

01 .64. 12 .1

01 .64 .13. I a I .68.24.1

01 .66 .85.1

14

01 . 62 .50. I

01.60. 49.1

01 . 06 . 01. I 01 .25. 15 . I 01 .68.24.1

01 .60 .05.1

15

06. 05. I

01. 15 .17 . 1 01 . 62.52. I

01.60 . 50. I

01 . 20 .20 . I 01 . 06 . 20 . I 01 .68.24.1

01 .66 .24.1

16

01 . 25 . 05 . I 01 .60 .57 .1

01 .06 05. I

01 . 15 .18. I 01 .62.52. I

01.62. 30.1

01 .20 .31 .1 01 .68 24.1

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17

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01. 10 . 05. I 01 .60 57. I

01 .06 .05. I

01.25 . 35. I 01 . 64.11 .1

01.62.31 . 1 01 .80 . 10. I

01 .25 .30. I

01 .68 40.1

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18

19

01

01

01 .62.3'3. I

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01.05 .50.1

19

20

01 .80. 25. I 01 .06 .30. I

01 . 06

10.1

01. 40 . 20.1

01 . 64. 13. I

01 .62.34. I

21

01 . 06. 10 . I 01

06 .30.1

01 .06. 12. I

01 .43. 10. I

01 .64. 13 '.\

01 .62. 35. I

01 .40 .03. I

a I. 45. 17 .1 01 .68.42.1

21

22

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14 . I 01

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01 .62 .36. I

01

47. 10. I

01 .45. 17. I 01 .68.44.1

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01 . 50 .17. I 01 .64. 14.1

01 .62 .37. I

01 .45 . 17. I 01.68,85.1

23

01 .50 .17. I 01 .65 .02. I

01 .62 .38. I

01 . 81 .45.1

01 .80 . as .1 01 .68.85.1

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01 . 82 . 20 . 2 0 I

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06 30

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01 .81. 15. 3 01 .06. 30. I 01 .60 40

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26

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29

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01 .63. 30. I

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01 . 06. 10. I

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01 .65 .05. I

01 .63. 30. I

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01 .63.40. I

01 . 40. 50. I

01.81. 15 . 3 a I .67.10.1

30

31

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01 .81 .40. I 01 .66_85.1

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01 .64. 1'3. I

06. 05. I

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I 01

25 .20

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LAMPS 1 CONS

OX 01 CONS

50

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01 .60.59. I 01 .63.10. I
LAMPS

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01 .63.20.1
CONSOLE

I .68.85.1
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ox.

A)(-K

32
AX-L

GATE C

TYPEWRITER

1620

CONNECTORS

CXA

1
2
3
4
5
6

01.12.14.1
01.12.82.1

35
36

01.82.80.1
01.82.80.1

13

01.82.86.1

37

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10
11
12
13
14
15
16
17
18

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18 01.82.86.1 42 01.~~
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01.82.86.1 46

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01.00.32.1

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55

54

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01.90.30.1

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X ffl,N~~9t5A~~S le!~F~

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XI ALL POINTS ARE OPERATING
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1620

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1620

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FUSE, RELAY AND EDGE CONNECTOR CHARTS

FUSE

NO

TYPE

CHART
PAGE

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01.90.10.1

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01 .90.45 • I

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01.90.45.1

01.90.45.1

01.90.40. I

01.90.45,1

01.90.40,1

01.90.45.1

113
114
115

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116
117
118

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119
120
121
122
123
124
125
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01. 9.9.45.1

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1620
CONSOLE SWI TCHES
DESCRIPTION

PAGE
01 .05.03.1

EMERGENCY OFF
DISPLAY MAR

01.0S.01.1

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01.05.01.1

INSTANT STOP -

SCE

01.05.01.1

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01.05.02.1

MAR DISPLAY SELECTOR

01.05.05.1

OVERFLOW CHECK

01.05.02.1

PARITY CHECK

01.05.02.1

POWER ON OFF

01. 05.03.1

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01.05.02.1

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01. 05 . 0.2 . 1

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01.05.02.1

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01.05.02.1

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01.05.01.1

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I

POWER ON

01.05.03.1

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01.90.40.1

3

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01.90.10.1

4

PUNCH NO FEED

01.84.10.1

5

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01.83.10.1

6

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01.06.15.1

7

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01.06.20.1

8
9
10

AUTOMATIC,

01.06.05.1

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01.06.10.1

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01.06.12.1

11
12

01.00.91.1

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CONSOLE SWITCHES

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01.67.30.1

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01.67.30.1

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01.67.90.1

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SHIFT OPS ENTRY

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H I ORDER ZERO CNTRL

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01.67.50.1
01.68.40.1

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COUNTER COMPLEMENT

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01.66.25.1

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01. 66.21.1

CE 25

SIGN DIGIT

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01.66.23.1

CE 26

SCAN M I NUS

AXB-26

01.66.24.1

CE 27

MODULE 3 CONTR OL L I

AXB-27

01.68.10.1

CE
CE

CE 12

CE 28

MODULE 3 CONTROL L 2

AU-28

01. 68.10.1

CE 29

H I PLUS AUX IAL IARY

AXB-29

01.66.83.1

CE 30

SCAN Q EXIT

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01.66.24.1

CE 31

-12 VOLTS

AXB-31

01.00.15.1

AXI-32

01.'0.55.1

CE 32

GROUND

2128939

CONSOLE CONTROL MANUAL RESET

"0" 750e

1629

11.16.11.1

-S MANUAL RESET
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11.06.85.1
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p~

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01.63.20.1

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P2
32.1
-S MANUAL RESET
P2
-01.60 ... a.1
-S MANUAL RESET
P2
01.60.51.1
-S MANUAL RESET
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TIMING SAMPLf GEN.RATION

81.10.22.1

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- - - - - - - - - - - - - - - -______________._____~2~1_·~101.28.20.1

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CHECK CONTACTS

C.00.03.1

1620
ALLOY-CURRENT SOURCE

ACY

HEAT SINK

036

R33

R31

120A

75n

-12

370169 REF
MAX CURRENT 600ma

rl
hd

G--

C.OO.05.1
ALLOY-RESISTOR CARD, 3 WATT

AFB
YJA ..
YJB**

R33

11
R31
C

R26

0

+12

R22
E

R24
_F

R28
G

371948 REF

*370788

D

REF

**370789 REF

B-

C-

OE-

AF -

RES I STORS ARE 34. 3n ~ 1/2'" TOL.

F-

* RESISTORS

G-

**

ARE 40.2.0 .:!: 1.0 % TOL.

RESISTORS ARE 17.2n± 1.0% TOL.

CTRL LIGHT DRIVER N TYPE

+12M

AFR

.f.12M

R24

R33

B
150.0

RI
51K

R26
1.8K

R23
A
S.IK

150n

R32
SIK

R30

R31

l.aK

S.IK

':"

':"

+1 M

+12M

R37

R28
H
R27
SIK

150n

SIK

R36
1.8K

R35

G

Ison
R29
1.8K

R25
C

S.IK

-

S .IK

-

':"

+12M

+1 M
RI9

K

Q

RIS
51K

RI3
SIK
RI4

RI8
R

p.

5.IK

5.IK

':"

':"
INPUT

371943 REF

OUTPUT

UP LEVEL O.DV TO -O.SV
DOWN LEVEl-S.56V TO -12.4SV

MAX CURRENT IS.O ma

1620

CARD SCHEMATIC

C.00061
AHK-

CTRL-INVERTER "N" 2 WAY EXTENDER
R20

+12M

R 28

+12M

5.6 K

5.6K

R27

R22

43K

43K

R 29

R2I
0

~5.6K

~.6K

-

'-0'
0-

R9

'Do
F-

1

AHK-

+12M

-

3
AHK-

RI

+12r.t

Oo-----"IM........
5.6K

5.6K

R3

R6
43K

R8

43K

R2

Ho--~~~--~--~
5.6K

5.6 K

O-OKR-

4

AHK-

INPUT AND OUTPUT
UP LEVEL

OV TO -O.2V

DOWN LEVEL - 5. 86V TO -12 .48V

370322 REF

--op-

H-

2

AHK-

1.'4
Col

ALLOY CLUTCH MAGNET DRIVER

1620

C .00.07.1
AHS

-12M

-I?M

R37

RI3

33M

3300.

370336 REF
INPUT

OUTPUT

UP LEVEL

-O.IV TO -O.5V

DOWN LEVEL -S.35V TO -12 .• 8V
MAX CURRENT 1.35 AMR

D

O
CM

CM

-F

-0-

AHS~

AHS~

AHT

ALLOY PUNCH MAGNET DRIVER
+12110-.........- - - - - - . ,
R2"
10K

A

RI9

2K
AAS

R8
10K
-12

+12M 1>""-...-

_ _ _ _ _--.
D5

R4

AAS

2K

AAS

R2
68K

-12

INPUT
-12

016

OUTPUT

370337 REF

[J [J

--..
.

-8-

PM

1--

-D--

-E-

UP LEVEL O.OV TO O.SV
DOWN LEVEL -S.25V TO 12.48V
MAX CURRENT 220 ma

PM

2 1+---

AHT-

06

-F{J0PM
-P

3 G-AH -

1620

CTRL PNP EXCLUSIVE "OR"

C.00.08.1

AHU
-12

-12

-12

R 71
IK

R66
2.7 K

R 44

E

- 12

R67

-12

-12

I 3K

25

R45

IK

R 35

L3K

2.7K

022

R58

AAS

023

R59

+12M

AAS

-12

-12

+12M
R27
3K
R 50

t

I 3K

-12

RI8
11K

R47
3K

-12

R 36

L3K

061
AAS

72
IK

R28
2.71<
R29

063

-12
AAS

S

R33
3 K

R 57
"

K

1.3K

R51

-12

1.3K

+12M

053
AAS

054

INPUT

a

OUTPUT

AAS

R26
3K

R55
11K

-12

370386 REF

UP LEVEL O.DY TO -O.ZY
DOWN LEVEL-S.76V TO -12.48V

+12M

-p-r}--o-bj

-E-[J2 HR- -O-PJAB-1<- AHU-

-L-bd

C.OO.IO.I
CTRL-INVERTERS "N" TYPE UNLOADED COLLECTORS

CAB

-12V

C

1.6K L

12M

+12M

R23
33K

R'3
33K

~~tK

RI5
5.6.

R22
5.6.

RI7
5.6.

+12M
R26
33K

D

RS
5.6.

A

P

-

R3
5.6K

R6
5.6K

'::'

R5
5.6.

RI6
5.6.

R

H

K

-

Q

INPUT

UP LEVEL -O.IV TO -O.4V

OUTPUT

DOWN LEVEL -5.S6V

a

TO

-12.4SV

371931 REF

+IA
+AA
+A
-TO

-P

COR CL

::go

-Q

-10
I

-R

CTRL-INVERTERS "N" TYPE

CD

-12V

-12V
+12M

+12M

R31
1.6.

RI3
33K

R23
33.
E
R21
5,6K

RI5
5.6K

R22
5.6.

RI7
5.6K

A

G

8
R3
5.6K

";'

H

RI6
5.6K

t

t:
1.6.

-12V
L

+12M

R32
1.6.

R26
33K

D

C

RS
5.6K
P
R6
5.6K

-

Q

R

-

R5
5.6K

INPUT

UP LEVEL -O.IV TO -0.4V

OUTPUT

DOWN LEVEL -5.S6 V TO -12.4SV

a

371029 REF

+IA
E-

-P

E

o

-R

ttA

~TO

-00

-Q
3

co--

=fo

CARD SCHEMATIC
+12M

-'2

C.OO.12 .1

1620

CTRL MUP-15
-+12'"

CAU-

+12,..

-'2

-'2
R3
'.6 K

R2
43K

R39
5.6K

G

E
R27
5.6K

R36
5.6K

R26
5.6K
B

-=

-=

-=
R30

R29

5.6K

5.6K

H

+12'"

-'2

-'2

+12M

-'2

R.6
43K

R23
5.6K

D

P
R24

R43

5.6K

5.6K

T5
033

Q

R
R22
5.6K

RI7
R20
33K

R.5

-

5.6K

+12'"

'0'F

H

B

•

CAU

A-

• NPUT AND OUTPUT

370353 REF

UP LEVEL -0 . • V TO -O.4V
DOWN LEVEL -5. 86V TO -'2 48V

5.6K

R4.
5.6K

'-ex
QRK-

L-

2

CAU

D-

-=

C.00.15.1
CTRL-EMITTER

FOLLOWER PNP

CE

+12V

R7

RI3
30ll

30fl

B

+12V

R31

RIG

300n

300n

+12V

-12V

~"'

RI'

300n

-12v

-12V

i"

2.2K

-12 V

G
I·O'MF

f""

2.2K

1.6K

R

0

-12V

VOLTAGE LEVEL
IN
O.QV, TO-:O.2V
-G.OGV TO-IO.S5V

OUT

+0.02
-8.0

371032 REF

NOTE:

D
E

8

I

D
E

-c

GA-

CE:8

Q

PIN TIE TO-12V

D
E

-F

PK-

CE

v:

D
E

-L

HR-

•

CE YB

SDTRL-DRIVER,LOW,POWER-IO BASE NON-INVERTING

DAR

-12

I

1

CIG

T

+ l6.8MF
R27

RII

240n

240n

~6:5

~

D33

AAS

~P~ 6~5

C

07

AAS

t:

F
D32

t~

L

P

AAS

R5
12K

R21
12K

D23

AAS

D22

AAS

AAS
+12M

,
-=

N

D30

H

R3
12K
D"

+12"-1

T3
P 045

P

R20
12K

AAS

240n

AAS

G

DI9

R29

RI2
240n.

Jp ~6~5

+ 12M

+12M

D6
CG

R9

39011
IW±5%

VOLTAGE LEVEL
IN

-12

-7.37V TO 12.48V
-0, I V
TO O.SV

OUT

-6.B7V TO-12.4BV
-O.IV

TO-O.SV

370082 REF

11-0
OAR

6

-

C-DpAR

F-DHAR

E

L-DEAR

SDTRL- INVERTING,HEAVY POWER
DRIVER

1620

C.00.17.
OAT

-'2
R 27

-'2

241l.
R26

R34

.6aa.

3K

R23
620n

c.g
.OI5MF

R20

1.8K

150MMF

R8
2.4K

022
CG

+

C5

T 6.BMF
L---...o

-12

024
G
AAS

RI:

-'2

24n

-'2

R7

.60n

R2'

R.6
620ll.
C28

I.IK

.OISMF

c ••

R6

.50MMF

-'2
R3

.w

39Q1l.

04

• .8K

R2
2.4<

L----------o----~~----~~----~------------------_oH
INPUT

-B-~G-370172 REF

bJ

-F-r'}-bJ

OUTPUT

UP LEVEL - O.IV TO-O.6V
DOWN LEVEL-7.73V TO-12.48V
UP LEVEL-O.'V TO -O.6V
DOWN LEVEL -7.3V TO -9.7V

C.OO.20.1
DAW

SDTRL-INVERTER. 3 WAY. UNLOADED COLLECTORS

+IZM
R5
R
4.7K

R4
18K

R6

+ 12M"

R23

0

4.7K

A
R8
18K

4.7K

R7

-=

4.1K

R

B

IW

4.7K

-12

RII

l

K
4.7K

IK

+12M

R2~

H

4.

L

R3
18K

R25
G
4.7K

R26
4.7K

INPUT

UP LEVEL -O.IV TO -O.SV
DOWN LEVEL -6.87V TO -12.48V

OUTPUT

UP LEVEL -O.IV TO O.5V
DOWN LEvEL 6.87V TO 12.48V

370083 REF

+IA
+AA
+A

COR CL

:68
=£0
J

DAX

SDTRL-INVERTER. 2 WAY. UNLOADED COLLECTORS

R20

+12M

+12M

R28
G

4.7M

C

4.7K

R21

R29

4.7K

4.7K

0

-=

-

- 12

l

IK

+12M

+12M
R9

RI

Q

A
4.7K

L
p

4.7K

R8

R2

4.1K

4.7K

-=

-=
INPUT
OUTPUT

UP LEVEL -0.1 V TO -O.6V
DOWN LEVEL -6.87V TO -12.48V
UP LEVEL -O.IV TO -0.5V
DOWN LEVEL -6.87V TO

370084 REF

'-0-0-

'-D~
H-

AX

'-0'F- OAlC

--0'R-

-12.48V

DRIFT LOGIC DRIVEN DL

1620

C.00.22.1

DBU

-12

+12M

+IZM

-12

+12M

R69
18K

R50

R13

18K

4.7K

R49

R72

4,7K

47K

-12

R71
4.7K

+ 12M
R43
1.5K

- 12
+12M

-12

R68
18K

Q

R62
18K

R66

R63
4.7K

R30

4.7K

240n
1/2W

R65

+12M

R

Do-......""'-....-i.!W
4.7K

R57
18K

12an

.....-'w,,....-g -

I2

INPUT UP LEVEL O.IV TO -o.SV

4.7K

DOWN LEVEL -6.87V TO -12.48V
OUTPUT UPLE~EL +1.5V NOMINAL
(+Cl
DOWN LEVEL-2.5V NOMINAL (-C)

370384 REF

*

101

-F:F,1p-- -E-FJA-- -C-NQ-- -K-F.IR-bJ
bJ
bJ
bJ

-B-~L--

bJ

C.OO.23.1

1620

SDTRL-STANDARD CABLE DRIVER

OED

+12M

+12".

,.....--0 A

13
045

001".-'11\,..,..-+----1
R23

R.

68011.

680n
-12

-12

T2
045

R7

680n
-12

-12
INPUT

--1
...

J ClO.....

UP LEVEL -O.IV TO -0.65V
DOWN LEVEL -6.85V TO -12.48V
UP LEVEL + I.OV NOMINAL
DOWN LEVEL -2.0V NDMI'IAL

OUTPUT

---00 L

371987 REF

-O-DL,-- -c-rDL}- - -B-fOL}-- -F-DL

4 H--

W

bJ

OED-

DE 0-

DEE

SDTRL STA NDARD CABLE TERM INA TOR GATE 0

+12M

+12M

+12M

tl2M

6---008

....-_c

~G
~

371988 REF

-a-DT,--i'-

EE

D
T

-0.,-j(-

2 A--

o

-

IK

-12

-12

-E-O
DEE
-r-

T
3

--

INPUT

OUTPUT

-H-DT.
-II-

L--

G--

DEE-

UP LEVE L + I.OV NOMI NA~
DOWN LEVEL -2.0V NOMINAL
UP LEVEL
-0.1 V TO - S.5V
DOWN LEVEL -S.8SV TO -12.48V

CARD SCHEMATIC

C.OO.24 I

1620

DFA

SDTRL MUP NUMBER 12
.....-

-12

-12

....._ -..........- _.....-0-.2

R68

R69

Rl0

R71

1200n

'200n

1200n

1200n

+12M

+12M

+12M
RI8
18K

R5
IK

R2
18K

R.O

R3

4.7K
RI7

4.7K
R4

Q

4.7K
RI5

4.7K

-.2

-=

R

RG

+12M

4.7K

R6G

300.n.
IW

-=
+12M
+12M

-12

+12M

-12

-12

RI
18K

-12

R49

A
4.7K

R50

G
I NPUT AND OUTPUT
UP '_EVEL -.IV TO -.6V
DOWN LEVEL - 6.87 V TO - 12.48\1

4.7K

R 55

A-OF-

K-DPL-

370224 REF

C - OFF S I DE

+12M

2 Q-OFF SIDE
E - ON S I DE

H - OF A-

SDTRL MUPNUMBER 15

-12

+12M

R39

G-

1 B- ON SIDE
R- DFA-

Q-

+12M

R3
IK

R2
I eK

R35
IK

RIO
18K

D FD

-12

-12

""--_--0

"4
18K

4.7K
R5

R27

4,7K
R30

4.7K

R36
4.7K

H

0--_10--'"

R2G
4.7K

4.7K

R29
4.7K

-=
+12M

-12

+12M

-12

+12M

-12

R44
IK

R4G

.K

R20
18K

R40
IK
RIG
18K

RI9
leK

R23

4.7K
R24

R47

R43

4.1K

4.1K
RI5

4.7K

Q

R22

RI7
4.7K

4.7K

4.7tt

R41

4.7K

C33

E-OL
F-

H-

-

-'2 o---;~
C-

R-

K-

•

B- OFO-

370204 REF

-

P-OL
o-

OOI5"MF

-4:-

2

L- DFO- 0-

INPUT AND OUT PUT
UP LEVEL - 0.1\1 TO -0.6V
DOWN LEVEL - 6.87V TO -12.48V

A

C.OO.25.i
ALLOY-SWiTCH,DECODER

014

034

A

+30V

FS

+3OV

FS

DIS

03'

33MFD

- 3GV

-12V

-36V

-12V

INPUT

UP LEVEL O.DV TO-O.5V

DOWN LEVEL -IO.2V TO -13.8V
OUTPUT

NOMINAL 270 ma

* I NCHANGEABLE

WITH FL

371396 REF
*371789 REF

D O
WO

-A

-8

-c
-0

W

-F

I

-G

E-

-H

l--

-l

2

L- ..

K-

FM

ALLOY-DRiVER, CURRENT

WG"

034
JS

02'
AAS
RI4

5 rail

R28

033
JS

032
JS

~1~'
Pi!
I

031
JS

CO'

07
FS

91n

5rf9~MF

RIO
3K

~H

I
I N I

L:

030
JS

'--HEAT

CI2
5.6MFO

SINK

+
-12V

o

- 36V

CI3

8o---------f
-12V

~
+..L

INPUT

A PIN NOMI NAL 270 ma
E PIN UP LEVEL O.IV TO-O.SV
DOWN LEVEL-G.87V TO-12.48V

* I NTERCtiANGEABLE

371397 REF

*371790 R!F

CURRENT SOURCE

-A

-S GATE _

0

C-

FM--

EO-

WITH FM

C.0030.1

FP

ALLOY-LOAD RESISTOR

i
A

RI
40.2Jl.
2W 1%

c

E

~

f

R4
40.211

RS

40.2A

2W 1%

o

I
G

2WI%

F

R8
40.Z.!l
2W 1%

H

311453 REF

-A-DB--C-

0--

-E-G-

F--

H--

ALLOY -CURRENT SOURCE

G

L33
1.2 MH

R28
82A

R29
IK

027
HEA,l SINK

JS

+12"1

+ 12V

R31

90.0.

5W

C4
1.2MH

:!:~ ...

RI3
4.7K
CI5

+ I 2 V o-----:;i t------.
+30"1

5.6 MF

371454 REF

*370552 REF

D
p

-C

G-

fQ--

~

INPUT

+ 30 V NOMINAL I AMP

OUTPUT

NOMINAL

270 mo

C.OO.35.1
CTRL -

MH

1NVERTER, POWER - PNP

+12M
RI
33K

+12M

R9
430.1\.
IW

R27
33K

R

o

L

RIS

RI4

po--'\Nr---....--~

Ko---~r---~--~

2K

2K
CI5

G

CI3

o---t

Q~

s

-=

5S0MMF

5&OMMF

+12M

R22

~'~

R20

+12M

430A

C4

1~pn

3.31\.

2W±10"~

IW

C

R23
33K

R30
2K

R32
2K

E

-12

A
T4
033

UP

INPUT
B
OUTPUT

371487

REF

0

-KOR KG

LEVEL-O.IV TO-0.6V

DOWN LEVEL-S.87V TO ·12.40V

MH--

L OR LC-

-P OR PO

OR

LR-

r:l

bd

0-

-s

r1
~ROR
~

EC -

-F OR FH

D4

A-

MH--

ER-

MX

CTRL - 1NVERTER "N" 2 WAY

-12\1

+12M

-12V

lR32
I.SK

tl2M

R20

R2B

so-..JV.lIIr-....,
G

5.&K

5.SK

R21

R29

T3
033

5.SK

5.&K

-

-=

+I2V

+ 12M

-'2V

I.SK

RI

1.6K

Qo-~Mr-....,

~

+12M

RI3

R9

A

5.&K

5.&K

K

R8

Ro-~Mr--6--~--~
5.SK

T2
033

H
5.&

K.

-=
INPUT
B
OUTPUT

REF

-IIDG-

-0

I

IIX--

~[]p-

011 LP

1111-

P

R2

-=
371661

L

-EDc- -QOII-F

-R

4

UP LEVEL-C.IV TO-O.4V
DOWN LEVEL -S.86V TO -12 .48V

C.OO.40.1

CTOL - SENSE AMPLIFIER, BUFFER

... 12V

NN

+12V

R29
12K
030

'-----0 A
RIS
sin

L....--------o

C33

l'MFD

0 sTRoeE
INPUT

r,:-F

-12 V

fiK'

-12V

371678 REF

-eO
-

C

OUTPUT

uP LEVEL - O.IV TO - 0.4V

INPUT

DOWN LEVEL-6.S7\' TO-12,48V
NOMINAL VOLTAGE
100 MV PULSE

D

A OR A F -

-0

NN --

F-

NP

CTRL-OR IVER,RELAY .THYRATRON V.M.
A

-+12M
R33
8.2K

034
AAS
R30
I IK

R31
8.2K

-12V

C26
0068 MFO

032
AAS

8
+12M

0
R22
8.2K

-=
H

021
AAS

R8
62n
IW

R9

UK
-12V

RIB
8.2K

C27
.0068 MFD

Dig
AAS

-+12M
R2
8.2K

-=
G

06
AAs

§Pn

R7
I.

RI
8.2K

IK

ell

03
AAS

.0068 MFO

P

-=

INPUT

371684 REF

OUTPUT

-A
-8

0

_~ c_

-0

-E

0
p--

-F
-p

H-

0

3 G-

NP--

UP LEVEL -o.OV TO -0.3V
DOWN LEVEL-S.96V TO-13.2V
C,H8FO.OV TO-O.6V

PIN

CTRL- DRIVERS, VM, LI GHT OR
RELAY

1620

C.00.41.1
PF

F
034
A

_----M_-..I

RI5

R33

20n JW

22!l1 W

B

RIO
16K

T2
026

R23

IK

-

~a8n

R5
4.7K
-12V

-12M

H

016

G

R7
16K

-----+il---J
Gs

RI3

R31

201llW

22nlW

TI
026

R22

Eo-----JVV~.-~~
IK

R21
4.7K

R26
300n

-12M

371750 REF
-0 OR DA

D

":'

B OR F-

PF - -

-12V
INPUT

UP LEVEL -O.IV TO -0.6V
DOWN LEVEL -6.87V TO -12.48V

OUTPUT

O.OV TO -

O.2V I +WI
- IB,OV TO -20.0V (-WI

-E OR EG

D

C OR H-

PF--

c.O 0.4 2.1

PG

CONTROL-SELECTOR,BRAKE OR CLUTCH

RI2
270.n.

G

RI5

,,,.

RIO

~11J'\.1I4W

4.3K

RI6
-12v
2201\.

.. 12 M

R32
56"

R9
4.3K

R31

A

RII

D

B
16011.

3.6K

OUTPUT VARIES FROM -0.1 V TO -12V
INPUT

371777 REF

UP LEVEL -0.1 V TO - 0.4V
DOWN LEVEL - 6.87 V TO -

12.48V

D

FG-

-0

PG--

CTRL- EMITTER

AB-

FOLLOWERS, LOW CURRENT

- 12 V

i

12v

*

PH
CBW

H

.**

R6

R26
68"

7.5 K

-12 V

t 12V

- 12v

t

12V

T4
083

G

R 31
68K

**

R33
7.5K

INPUT - 8V TO -9V
OUTPUT UP LEVEL -0.1 V TO -0.4V
tl2 V

- 12,

DOWN LEVEL - 6.87V TO-12A8V

'*

WHEN PHOTODIODES HAVE ADJUSTING

POTENTIOMETERS USE PIN 2 r 15030

* THESE

371778 REF

O
M

-9

PH-

RESISTORS ARE REMqNED TO

CONVERT PH CARDS TO CBW

I' 2115030 REF

A-

-0

O
M

PH-- C -

-H

DM
PH--

O
M

-G
F_

PH--

E-

C.OO.43.1

PJ

CONTROL- DRIVERS, BRAKE AND CLUTCH

r - - -.....- _ c
R32

GO-----------~~--_1~--_r~
56fl.2W

R30
430
IW

.'!.~

RIO

1-12M

R26

R28

8 Oo-----~.y.~--_4.~--·~:y.~~----4.~--~\N~·~.----••~--~%N\·~.----_oO-12V
13.tl.2W

13.tl.2W

Ho-__________

13J\2W

13.tl.2W

R'6
~~--~----~

56J\2W

R'4
430ft

tl2M
INPUT VARIES FROM -0.1 V TO -IZV
OUTPUT &1.9 V DC AT NO LOAD
48.5 V DC AT PEAK LOAD

371779 REF

-8DE-

-ADc-

-G

_H

. D-

F-

PJ --

PJ- -

PK

CONTROL- LOCK CIRCUIT- PHOTOSENSE

+12M

"37
L6K
r-~fr-_o

-12
A

c_.....""""i
R43
ISOK
H

fl2M

-12V

..

O~-------

INPUT ADJUSTED TO -8.0 V
OUTPUT UP L'EV[L -O·IV TO- 0.4V
DOWN LEVEL -6.87 V TO -12.48 V

371780 REF

-CO
-H

-0

A-

C.00.45.1
RE

ALLOY-THERMOSWITCH N/C 122°F

L

~--------r--- PIN~ A AND B ARE NOr INPUTS OR OUTPUTS

L
A

H
0

t

B

_

THEY INSURE POSITIVE INDICATION
WHEN THIS CARD IS ACCIDENTLY
~¥P~9~TUTEO FOR 311696. 371697 AND

OF

THSW 122"F

371699 REF

O
H

-F

~E

H-

--

SDTRL - 2WAY INVERTER

+12M

R27
18K

~32

R22
18K

-12V

+12M

-12V

IK

R30

IK
IW

R28

R20
I 8
4.7K

4.7K

R21

R2.

4.7K

4.7K

':'
+1 2M

-12V

-12v

+12M

CII+

68~F

R6
18K

-

o::!::-

RI3
IK

R3
18K
RI

R'

A

Q

L
I4
I.

L

4.7K

4.7K

R2

R8
H

4.7K

4.1K

I~PUT

UP LEVEL - O.IV TO 0.6V

a
OUTPUT

371869 REF

DOWN LEVEL - 6.B7V TO 12 .48V

* INTERCHANGEABLE WITH VE

*370366 REF

-BDG-0

I

VE--

-A
-

H

o
VE-~

P

O~LP

-EDc-F

3

E--

_QDK-

-~

E--

1620

CARD SCHEMATIC
SDTRL 93!l COAX LINE

C 00,46,1
TAB-

DRIVER-DISPERSED LOADS

-12

+12M

+12M

+12M

+12M

R.

1.5K

RII

H _

....-'IIIII'r-+--I.

3K
CIO

.ot MF

o

HOL

370066 REF

B1JL

G-

E-

TAB~

TA8~

COL

A1JL

F-

[)-

4,

TAB:

TAB-

INPUT

UP LEVEL -O,IV TO -O,4V
DOWN LEVEL- 6,87 V TO -12 ,48V
OUTPUT NOMINAL - 2.0 V

TCK-

SDTRL- END 0 F LI NE TERMINATORS
+12M

R2
820n

RS
820n.

R6
8200

R7
820n

~A

......os

~C

~o

Rig
Iwa

R22
120n.

R23
120.n

R24
120n.

R8
820n.

_E

R25
120n

R.
820n.

~F

_H

R26
120n

-':'

R28

loon
RI6
lOOn.
RIS
100.n

RI4

~

loon

370334 REF

NOTE

ALL

RIO
820 a

RESISTORS ARE 1/2 WATT AND :!:5%

R27
120n

R4
820a

~K
R21
120

n.

R3
820 n.

0--0
"R20

120 n.

CARD

S D TRL- DISTR I BUTE D LI NE
-12

-12

-t12M

C 00 4-(

1620

SCHEMATIC

TERMINATOR

TDA-

-12

-12

+12M

R30
IK

R42
IK
R41
18K

R28
ISOK

R2'
ISK
027

R3"
180K

016

P

A

ax

BX

*
':'

-12

+12M

-12

R33
I aK

':'
- 12

R34
IK

R31
180K

R45
IBK

DB

-12

+12'"

R46
IK

R43
ISOK

044

BX

ax

*
':'

+ 12M

-12

':'

-12
-12

R37
18K

r. t-----o
C22

R35
leOK

+

I

+ 12 M

6.8MF

012

C20

16BMF

Q

BX

':'

O D D D D
L

L

A

370359 REF

F-

TDA~

R-

L

E-

TDA~

Q-

TDA~

L

L

0-

p-

c-

TO A:

G-

B-

TDA~

1620

C.00.48.1

SDTRL-ALLOY SWITCH

TBD

-12

-12

R 15
4 7.

R 14
1.3K

R38
2.4K

A
C36
270MMF

TI
071

G

~,
C33
210 MMF

8
R34
2.4K

RII

RIO

1.3K

4.7K

INPUT

-12

-12

D

-A-

370171 REF

w

OUTPUT

UP LEVEL -O.IV TO -0.4V
DOWN LEVEL -6.87V TO -12.48V
NOMINAL

OV TO +12V

F-H--

g:::

-K -

-E- T8D-

8 --

C--

SDTRL-MODIFIED MUP NUMBER 12

TCZ

P
-12
+12M

R68

R47

-12

+12M

-12

Ison

-12

1200n.

1/2W

+12"

R69
R5
IK

R4
18K

RI

R73
I son

R42
IK

112W

8
4.7K
R2

TI4
045

4.7K
R3

-

Q

4.7K

RI6
R
4.7K
+12M

R49
A

R26

R25 +12M
4.7K

-12

+12M

12

-12

R54
IK

R52
IK

18K

4.7K
R50
G

-KOP--

-L-

-0-

370335 REF

I

-R-

c-8--

TCZ-

-A-OF--

-G-

_ H-

2 0--

- R-

E-TCZ-

INPUT 8 OUTPUT
UP LEVEL -O.IV TO OAV
DOWN LEVEL - 6.87V TO -IZ.4BV

C 0050 I

VF
TAH*

SDTRL - 3 WAY INVERTER
-12V
CI3

-12 V

E OJ:.

+ 12M

+ 12 M

6S M+F

R~

R 15

R23

R31
IK

4.7K

IK
IW

A
4.7K

R4

R8

ISK

I BK

T4

R33

039

R6

B

Q

4.7K IW

4.7K

RII

R7

4.7K
4.7K

R22
H
4.7K

+12M

R25
G

R3
18K

4.7K

T3

039

R26

I Nf8UT
OUTPUT

4.7K

UP LEVEL -O.IV TO -O.SV
DOWN LEVEL -S.a7V TO 12.48V

*" INTERCHANGEABLE

WITH

VF

371870 REF

* 370367

REF

-OE-8
.... K

I

VG

SDTRL - OSCILLATOR, ONE MC

TAF*
-12V

T2

039

F
c

RI2

43011.

R31
360n

-12V

L7
100

R9

1.8K

C5
150 MMF

UH

OUTPUT

UP LEVEL

-O,IV TO -O.45V

DOWN LEVEL -6.85V TO
TIME; 1 MICROSECOND

-12.48V

± .1%

-12V

"* INTERCHANGEABLE
371868 REF
IE 370365 REF

Q
OS

o

VG--

OR DC

WITH VG

C.OO.55.
SDTRL-TRIGGER, BINARY

-12V

AC

SET

Cig

+12M

-12V

15QMMf

---'W\i-.

....

GATE

R30

RI4

IW

IW

Geon

680n

RIB

A _

+

CIG

TI2M

RI

-=

R

1.3K

....-0

C5

R7
33K

PULSE

AC SET

150MMF

I.3K

021

R34
1.2K

GATE

,..--vlfr--o

6.8~

o o---f

06
CD

CD

o
-12V

0'
CD

011
AC SET

F

PULSE

o---i

PUL SE

AC SET

~L
R26
S.IK

150MMf

t50MMF
R2

R22
E ~-..JV'h--"
1.3K

GATE

C3

Gs

C24

....~~--o

GA TE K

J.3K

RESET

RESET
DC

DC

INPUT

AC SET

POSITIVE SHIFT

DC GATE

UP LEVEL

4.SV

TO 6.0V

O.OV TO - O.6V

DOWN LEVEL -6.87V TO -12.48V
OUTPUT

*

UP LEVEL -O.IV TO -O.6V
DOWN LEVEL MIN -9.96V

INTERCHANGEABLE

WITH VJ

IF F8M :tt:21J5244

371867 REF
*370364 REF

-0
-A
-F
-E
-R
-Q

-L

_K
_H
_C

D

8P -

G-

SDTRL-GENERATOR,SAMPLE PULSE

-If v o----.....--'lfi'r----..,
R7

R'
200n

-12V

025
AAS

C8

+

CIS

-----+--I6.~BF
330MMF

....

RS

IGOll
023
AAS

...- - - - -....- . . .

+

CI3

6.8MF
R22

028

430n

Gs
C33
B

D3I

<>-I

150MM

AU

+12M

R30
6.8K

R32

C2
IK

R 21
IK
+12M

RIO

Ll9
50UH
R34

A
1.2K

-12V

INPUT AC SET POSITIVE SHIFT 4.5V TO 6. 24V

371874 REF

GATE UP LEVEL O.OV To-a.SV

*370370 REF

D
sp

-C

D-

8A OR BE- VL--

DOWN LEVEL-6.B7V TO-12.48V
OUTPUT UP LEVEL O.OV TO-O.5v
DOWN LEVEL.-4.5V TO-S.24V

* INTERCHAillGEABLE WITH VL

IS

INSTALLED.

C00601
SDTRL - INVERTER, POWER - PNP

+12M
+12M
R3

300
IW

n

R6
I SK

RS
300.0.

R23
18K

RI6
2.7K

IW

T2**
039

RIO
2 7K

CIS
100 MMF

CI3

0----.

100 MMf

G~

C5
10 MF

.....-------------~'+l

1
H

R32

2 iK

fl2M

RI9

300.0.
IW

~66__

~§~

-t2v

A
T4

039**

1r

International Business Machines Corporation
Data Processing Division
112 East Post Road, White Plains, New York
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