270830 003_Intel_80C186EB_80C188EB_Microprocessor_Users_Manual_1995 003 Intel 80C186EB 80C188EB Microprocessor Users Manual 1995

User Manual: 270830-003_Intel_80C186EB_80C188EB_Microprocessor_Users_Manual_1995

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80C186EB/80C188EB
Microprocessor
User's Manual

February 1995

Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including
infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions
of Sale for such products.
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear
in this document nor does it make a comm~ment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation.
Intel Corporation and Intel's FASTPATH are not affiliated w~h Kinetics, a division of Excelan, Inc. or its FASTPATH trademark
or products.
'Other brands and names are the property of their respective owners.
Additional copies of this document or other Intel literature may be obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
@INTELCORPORATION. 1995

CONTENTS
CHAPTER 1
INTRODUCTION

1.1
HOW TO USE THIS MANUAL. ...................................................................................... 1-2
RELATED DOCUMENTS .............................................................................................. 1-3
1.2
CUSTOMER SERVICE .................................................................................................. 1-4
1.3
1.3.1
How to Use Intel's FaxBack Service ......................................................................... 1-5
How to Use Intel's Application BBS .......................................................................... 1-5
1.3.2
1.3.3
How to Find the Latest ApBUILDER Files, Hypertext Manuals, and
Data Sheets on the BBS ............................................................................................1-6
CHAPTER 2
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

2.1
ARCHITECTURAL OVERVIEW .................................................................................... 2-1
2.1.1
Execution Unit ...........................................................................................................2-2
2.1.2
Bus Interface Unit .....................................................................................................2-3
2.1.3
General Registers .....................................................................................................2-4
2.1.4
Segment Registers ...................................................................................................2-5
2.1.5
Instruction Pointer .....................................................................................................2-6
2.1.6
Flags .........................................................................................................................2-7
2.1.7
Memory Segmentation ..............................................................................................2-8
2.1.8
Logical Addresses ...................................................................................................2-1 0
2.1.9
Dynamically Relocatable Code ...............................................................................2-13
2.1.10 Stack Implementation .............................................................................................2-15
2.1.11 Reserved Memory and 1/0 Space ...........................................................................2-15
SOFTWARE OVERVIEW ............................................................................................ 2-17
2.2
2.2.1
Instruction Set .........................................................................................................2-17
2.2.1.1
Data Transfer Instructions .............................................................................2-18
2.2.1.2
Arithmetic Instructions ...................................................................................2-19
2.2.1.3
Bit Manipulation Instructions .........................................................................2-21
2.2.1.4
String Instructions ..........................................................................................2-22
2.2.1.5
Program Transfer Instructions .......................................................................2-23
2.2.1.6
Processor Control Instructions ......................................................................2-27
2.2.2
Addressing Modes ..................................................................................................2-27
2.2.2.1
Register and Immediate Operand Addressing Modes ................................... 2-27
2.2.2.2
Memory Addressing Modes ...........................................................................2-28
2.2.2.3
1/0 Port Addressing .......................................................................................2-36
2.2.2.4
Data Types Used in the 80C186 Modular Core Family .................................2-37
,INTERRUPTS AND EXCEPTION HANDLING ............................................................ 2-39
2.3
2.3.1
Interrupt/Exception Processing ...............................................................................2-39
2.3.1.1
Non-Maskable Interrupts ...............................................................................2-42
2.3.1.2
Maskable Interrupts .......................................................................................2-43
2.3.1.3
Exceptions .....................................................................................................2-43

iii

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CONTENTS

2.3.2
'2.3.3
2.3.4
2.3.5

Software Interrupts ..................................................................................................2-45
Interrupt Latency .....................................................................................................2-45
Interrupt Response Time ........................................................................................ 2-46
Interrupt and Exception Priority ............................................................................... 2-46

CHAPTER 3
BUS INTERFACE UNIT

3.1
3.2
3.2.1
3.2.2
3.3
3.3.1
3.3.2
3.4
3.4.1
3.4.2
3.4.3
3.4.4

MULTIPLEXED ADDRESS AND DATA BUS ................................................................ 3-1
ADDRESS AND DATA BUS CONCEPTS ..................................................................... 3-1
16-Bit Data Bus .........................................................................................................3-1
a-Bit Data Bus ...........................................................................................................3-5
MEMORY AND I/O INTERFACES ................................................................................. 3-6
16-Bit Bus Memory and I/O Requirements ............................................................... 3-7
a-Bit Bus Memory and I/O Requirements .................................................................3-7
BUS CYCLE OPERATION ............................................................................................ 3-7
Address/Status Phase ............................................................................................3-1 0
Data Phase .............................................................................................................3-13
Wait States .............................................................................................................. 3-13
Idle States ...............................................................................................................3-18

3~5

BUS CYCLES OO~~OO""

•••• , •••••••••••••••••••••••••••••••••••••••••• •••••••••••••••••••••••••••••••••••••

•••••••••••••••••

3-20

3.5.1
Read Bus Cycles ....................................................................................................3-20
3.5.1.1
Refresh Bus Cycles ....................................................................................... 3-22
3.5.2
Write Bus Cycles .....................................................................................................3-22
Interrupt Acknowledge Bus Cycle ........................................................................... 3-25
3.5.3
3.5.3.1
System Design Considerations ..................................................................... 3-27
3.5.4
HALT Bus Cycle ......................................................................................................3-28
3.5.5
Temporarily Exiting the HALT Bus State ................................................................. 3-30
3.5.6
Exiting HALT ...........................................................................................................3-32
3.6
SYSTEM DESIGN ALTERNATIVES ........................................................................... 3-34
Buffering the Data Bus ............................................................................................3-35
3.6.1
3.6.2
Synchronizing Software and Hardware Events ....................................................... 3-37
3.6.3
Using a Locked Bus ................................................................................................3-38
3.7
MULTI-MASTER BUS SYSTEM DESiGNS ................................................................. 3-39
3.7.1
Entering Bus HOLD ................................................................................................3-39
HOLD Bus Latency ........................................................................................3-40
3.7.1.1
3.7.1.2
Refresh Operation During a Bus HOLD ........................................................ 3-41
3.7.2
Exiting HOLD ..........................................................................................................3-43
3.8
BUS CYCLE PRIORITIES ........................................................................................... 3-44

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CONTENTS

CHAPTER 4
PERIPHERAL CONTROL BLOCK
4.1
PERIPHERAL CONTROL REGiSTERS ........................................................................ 4-1

4.2
PCB RELOCATION REGiSTER .................................................................................... 4-1
4.3
RESERVED LOCATIONS ............................................................................................. 4-4
4.4
ACCESSING THE PERIPHERAL CONTROL BLOCK .................................................. 4-4
4.4.1
Bus Cycles ...............................................................................................................4-4
READY Signals and Wait States .............................................................................4-4
4.4.2
4.4.3
F-Bus Operation .......................................................................................................4-5
4.4.3.1
Writing the PCB Relocation Register ...............................................................4-6
4.4.3.2
Accessing the Peripheral Control Registers ....................................................4-6
4.4.3.3
Accessing Reserved Locations .......................................................................4-6
SETTING THE PCB BASE LOCATION ......................................................................... 4-6
4.5
4.5.1
Considerations for the 80C187 Math Coprocessor Interface ....................................4-7
CHAPTERS
CLOCK GENERATION AND POWER MANAGEMENT
5.1
CLOCK GENERATION .................................................................................................. 5-1
5.1.1
Crystal Oscillator .......................................................................................................5-1
5.1.1.1
Oscillator Operation .........................................................................................5-2
5.1.1.2
Selecting Crystals ............................................................................................5-5
5.1.2
Using an External Oscillator ......................................................................................5-6
Output from the Clock Generator ..............................................................................5-6
5.1.3
5.1.4
Reset and Clock Synchronization .............................................................................5-6
5.2
POWER MANAGEMENT............................................................................................. 5-10
5.2.1
Idle Mode ................................................................................................................5-11
5.2.1.1
Entering Idle Mode ........................................................................................5-11
5.2.1.2
Bus Operation During Idle Mode ...................................................................5-13
5.2.1.3
Leaving Idle Mode .........................................................................................5-14
5.2.1.4
Example Idle Mode Initialization Code .......................................................... 5-15
5.2.2
Powerdown Mode ...................................................................................................5-16
5.2.2.1
Entering Powerdown Mode ...........................................................................5-17
5.2.2.2
Leaving Powerdown Mode ............................................................................5-18
Implementing a Power Management Scheme ........................................................ 5-19
5.2.3
CHAPTER 6
CHIP-SELECT UNIT
6.1
COMMON METHODS FOR GENERATING CHiP-SELECTS ....................................... 6-1
6.2
CHIP-SELECT UNIT FEATURES AND BENEFITS ...................................................... 6-1
CHIP-SELECT UNIT FUNCTIONAL OVERViEW ......................................................... 6-2
6.3
PROGRAMMING ........................................................................................................... 6-5
6.4
Initialization Sequence ..............................................................................................6-6
6.4.1
Start Address ..........................................................................................................6-1 0
6.4.2
Stop Address ..........................................................................................................6-10
6.4.3

CONTENTS

6.4.4
Enabling and Disabling Chip-Selects ......................................................................6-11
6.4.5
Bus Wait State and Ready Control .........................................................................6-11
6.4.6
Overlapping Chip-Selects .......................................................................................6-12
6.4.7
Memory or I/O Bus Cycle Decoding ........................................................................6-14
6.4.8
Programming Considerations ..................................................................................6-14
6.5
CHIP-SELECTS AND BUS HOLD ............................................................................... 6-15
6.6
EXAMPLES ................................................................................................................. 6-15
6.6.1
Example 1: Typical System Configuration .............................................................. 6-15
6.6.2
Example 2: Detecting Attempts to Access Guarded Memory ................................. 6-20
CHAPTER 7
REFRESH CONTROL UNIT
7.1
THE ROLE OF THE REFRESH CONTROL UNIT......................................................... 7-2
7.2
REFRESH CONTROL UNIT CAPABILITIES ................................................................. 7-2
7.3
REFRESH CONTROL UNIT OPERATION .................................................................... 7-2
7.4
REFRESH ADDRESSES ............................................................................................... 7-4
7.5
REFRESH BUS CYCLES .............................................................................................. 7-5
7.6
GUIDELINES FOR DESIGNING DRAM CONTROLLERS ............................................ 7-5
7.7
PROGRAMMING THE REFRESH CONTROL UNIT..................................................... 7-7
7.7.1
Calculating the Refresh Interval ................................................................................7-7
7.7.2
Refresh Control Unit Registers .................................................................................7-7
7.7.2.1
Refresh Base Address Register ......................................................................7-7
7.7.2.2
Refresh Clock Interval Register .......................................................................7-8
7.7.2.3
Refresh Control Register ................................................................................. 7-9
7.7.2.4
Refresh Address Register .............................................................................7-10
7.7.3
Programming Example ...........................................................................................7-11
7.8
REFRESH OPERATION AND BUS HOLD .................................................................. 7-13
CHAPTER 8
INTERRUPT CONTROL UNIT
8.1
FUNCTIONAL OVERViEW ............................................................................................ 8-1
8.1.1
Generic Functions .....................................................................................................8-2
8.1.1.1
Interrupt Masking .............................................................................................8-2
8.1.1.2
Interrupt Priority ...............................................................................................8-3
Interrupt Nesting ..............................................................................................8-4
8.1.1.3
8.2
FUNCTIONAL OPERATION .......................................................................................... 8-4
8.2.1
Typical Interrupt Sequence ....................................................................................... 8-5
8.2.2
Priority Resolution .....................................................................................................8-5
8.2.2.1
Priority Resolution Example ............................................................................8-6
8.2.2.2
Interrupts That Share a Single Source ............................................................ 8-7
8.2.3
Cascading with External 8259As ..............................................................................8-7
8.2.3.1
Special Fully Nested Mode ..............................................................................8-8
Interrupt Acknowledge Sequence .............................................................................8-9
8.2.4
Polling .......................................................................................................................8-9
8.2.5

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CONTENTS

8.2.6
Edge and Level Triggering ...................................................................................... 8-10
8.2.7
Additional Latency and Response Time ................................................................. 8-10
8.3
PROGRAMMING THE INTERRUPT CONTROL UNIT ............................................... 8-11
8.3.1
Interrupt Control Registers ...................................................................................... 8-12
8.3.2
Interrupt Request Register ...................................................................................... 8-16
Interrupt Mask Register ........................................................................................... 8-17
8.3.3
8.3.4
Priority Mask Register .............................................................................................8-18
8.3.5
In-Service Register ................................................................................................. 8-18
8.3.6
Poll and Poll Status Registers ................................................................................. 8-19
8.3.7
End-ot-Interrupt (EOI) Register ............................................................................... 8-21
8.3.8
Interrupt Status Register ......................................................................................... 8-22
Initializing the Interrupt Control Unit ........................................................................ 8-23
8.3.9
CHAPTER 9
TIMER/COUNTER UNIT
9.1
FUNCTIONAL OVERViEW ............................................................................................ 9-1
9.2
PROGRAMMING THE TIMER/COUNTER UNIT .......................................................... 9-6
Initialization Sequence ............................................................................................ 9-11
9.2.1
Clock Sources .........................................................................................................9-12
9.2.2
9.2.3
Counting Modes ......................................................................................................9-12
9.2.3.1
Retriggering ...................................................................................................9-13
Pulsed and Variable Duty Cycle Output .................................................................. 9-14
9.2.4
9.2.5
Enabling/Disabling Counters ................................................................................... 9-15
9.2.6
Timer Interrupts .......................................................................................................9-16
9.2.7
Programming Considerations .................................................................................. 9-16

9.3
TIMING ........................................................................................................................ 9-16
9.3.1
Input Setup and Hold Timings ................................................................................. 9-16
9.3.2
Synchronization and Maximum Frequency ............................................................. 9-17
9.3.2.1
Timer/Counter Unit Application Examples ..................................................... 9-17
9.3.3
Real-Time Clock ..................................................................................................... 9-17
9.3.4
Square-Wave Generator ......................................................................................... 9-17
Digital One-Shot ......................................................................................................9-17
9.3.5
CHAPTER 10
SERIAL COMMUNICATIONS UNIT
10.1
INTRODUCTION ......................................................................................................... 10-1
10.1.1 Asynchronous Communications .............................................................................. 10-1
10.1.1.1
RX Machine ................................................................................................... 10-2
10.1.1.2
TX Machine ................................................................................................... 10-4
10.1.1.3
Modes 1, 3 and 4 ........................................................................................... 10-6
10.1.1.4
Mode 2 .......................................................................................................... 10-7
10.1.2 Synchronous Communications ............................................................................... 10-8
10.2 PROGRAMMING ......................................................................................................... 10-9
10.2.1 Baud Rates ...........................................................................................................10-10

vii

CONTENTS

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10.2.2 Asynchronous Mode Programming ....................................................................... 10-13
10.2.2.1
Modes 1, 3 and 4 for Stand-alone Serial Communications ......................... 10-13
10.2.2.2
Modes 2 and 3 for Multiprocessor Communications ................................... 10-14
Sending and Receiving a Break Character ................................................. 10-14
10.2.2.3
10.2.3 Programming in Mode 0 ........................................................................................ 10-18
10.3 HARDWARE CONSIDERATIONS FOR THE SERIAL PORT ................................... 10-18
10.3.1 CTS Pin Timings ...................................................................................................10-18
10.3.2 BCLK Pin Timings ................................................................................................. 10-18
10.3.3 Mode 0 Timings ....................................................................................................10-20
10.3.3.1
CLKOUT as Baud Timebase Clock ............................................................. 10-20
10.3.3.2
BCLK as Baud Timebase Clock .................................................................. 10-21
10.4 SERIAL COMMUNICATIONS UNIT INTERRUPTS .................................................. 10-21
10.4.1 Channel 0 Interrupts .............................................................................................10-21
10.4.2 Channel 1 Interrupts .............................................................................................10-21
10.5 SERIAL PORT EXAMPLES ....................................................................................... 10-23
10.5.1 Asynchronous Mode Example ..............................................................................10-23
10.5.2 Mode 0 Example ...................................................................................................10-26
10.5.3 MasterlSlave Example ..........................................................................................10-27
CHAPTER 11
INPUT/OUTPUT PORTS
11.1
FUNCTIONAL OVERViEW .......................................................................................... 11-1
11.1.1 Bidirectional Port ..................................................................................................... 11-1
11.1.2 InputPort ................................................................................................................ 11-3
11.1.3 Output Port .............................................................................................................. 11-3
11.1.4 Open-Drain Bidirectional Port ................................................................................. 11-3
11.1.5 Port Pin Organization .............................................................................................. 11-3
11.1.5.1
Port 1 Organization ....................................................................................... 11-7
11.1.5.2
Port 2 Organization ....................................................................................... 11-7
11.2 PROGRAMMING THE 1/0 PORT UNIT....................................................................... 11-7
11.2.1 Port Control Register .............................................................................................. 11-8
11.2.2 Port Direction Register ............................................................................................ 11-8
11.2.3 Port Data Latch Register ......................................................................................... 11-9
11.2.4 Port Pin State Register ......................................................................................... 11-10
11.2.5 Initializing the 1/0 Ports ......................................................................................... 11-11
11.3 PROGRAMMING EXAMPLE ..................................................................................... 11-12

CHAPTER 12
MATH COPROCESSING
12.1
OVERVIEW OF MATH COPROCESSING .................................................................. 12-1
12.2 AVAILABILITY OF MATH COPROCESSING .............................................................. 12-1
12.3 THE 80C187 MATH COPROCESSOR. ....................................................................... 12-2
12.3.1 80C187 Instruction Set ........................................................................................... 12-2
12.3.1.1
Data Transfer Instructions ............................................................................. 12-3
viii

CONTENTS

12.3.1.2
Arithmetic Instructions ................................................................................... 12-3
12.3.1.3
Comparison Instructions ................................................................................ 12-5
12.3.1.4
Transcendental Instructions .......................................................................... 12-5
12.3.1.5
Constant Instructions ..................................................................................... 12-6
12.3.1.6
Processor Control Instructions ...................................................................... 12-6
12.3.2 8OC187 Data Types ................................................................................................ 12-7
12.4 MICROPROCESSOR AND COPROCESSOR OPERATION ...................................... 12-7
12.4.1 Clocking the 80C187 ............................................................................................. 12-10
12.4.2 Processor Bus Cycles Accessing the 80C187 ...................................................... 12-10
12.4.3 System Design Tips ..............................................................................................12-11
12.4.4 Exception Trapping ............................................................ '" ................................ 12-13
CHAPTER 13
ONCE MODE
13.1
ENTERING/LEAVING ONCE MODE ........................................................................... 13-1
APPENDIX A
8OC186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
A.1
8OC186 INSTRUCTION SET ADDITIONS ................................................................... A-1
A.1.1
Data Transfer Instructions ...................................................................................... A-1
A.1.2
String Instructions ................................................................................................... A-2
High-Level Instructions ........................................................................................... A-2
A.1.3
A.2
80C186 INSTRUCTION SET ENHANCEMENTS ......................................................... A-8
A.2.1
Data Transfer Instructions ...................................................................................... A-8
A.2.2
Arithmetic Instructions ............................................................................................ A-9
A.2.3
Bit Manipulation Instructions ................................................................................... A-9
A.2.3.1
Shift Instructions ............................................................................................. A-9
A.2.3.2
Rotate Instructions ....................................................................................... A-10
APPENDIX B
INPUT SYNCHRONIZATION
B.1
WHY SYNCHRONIZERS ARE REQUiRED ................................................................. B-1
B.2
ASYNCHRONOUS PiNS .............................................................................................. B-2
APPENDIX C
INSTRUCTION SET DESCRIPTIONS
APPENDIX D
INSTRUCTION SET OPCODES AND CLOCK CYCLES
INDEX

CONTENTS

FIGURES
Figure
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14

Page
Simplified Functional Block Diagram of the 80C186 Family CPU ................................ 2-2
Physical Address Generation .......................................................................................2-3
General Registers ........................................................................................................2-4
Segment Registers ........................................................................................................2-6
Processor Status Word ................................................................................................2-9
Segment Locations in Physical Memory..................................................................... 2-10
Currently Addressable Segments ...............................................................................2-11
Logical and Physical Address ....................................................................................2-12
Dynamic Code Relocation ..........................................................................................2-14
Stack Operation ..........................................................................................................2-16
Flag Storage Format ..................................................................................................2-19
Memory Address Computation ...................................................................................2-29
Direct Addressing .......................................................................................................2-30
Register Indirect Addressing ......................................................................................2-31
Based Addressing ......................................................................................................2-31
Accessing a Structure with Based Addressing ........................................................... 2-32
Indexed Addressing ....................................................................................................2-33
Accessing an Array with Indexed Addressing ............................... ;............................ 2-33
Based Index Addressing ............................................................................................2-34
Accessing a Stacked Array with Based Index Addressing ......................................... 2-35
String Operand ...........................................................................................................2-36
I/O Port Addressing ....................................................................................................2-36
80C186 Modular Core Family Supported Data Types ................................................ 2-38
Interrupt Control Unit ..................................................................................................2-39
Interrupt Vector Table .................................................................................................2-40
Interrupt Sequence .....................................................................................................2-41
Interrupt Response Factors ........................................................................................2-46
Simultaneous NMI and Exception ..............................................................................2-47
Simultaneous NMI and Single Step Interrupts............................................................ 2-48
Simultaneous NMI, Single Step and Maskable Interrupt.. .......................................... 2-49
Physical Data Bus Models ............................................................................................3-2
16-Bit Data Bus Byte Transfers ....................................................................................3-3
16-Bit Data Bus Even Word Transfers .........................................................................3-4
16-Bit Data Bus Odd Word Transfers ...........................................................................3-5
8-Bit Data Bus Word Transfers .....................................................................................3-6
Typical Bus Cycle .........................................................................................................3-8
T-State Relation to CLKOUT ........................................................................................3-8
BIU State Diagram .......................................................................................................3-9
T-State and Bus Phases ............................................................................................3-10
Address/Status Phase Signal Relationships .............................................................. 3-11
Demultiplexing Address Information ...........................................................................3-12
Data Phase Signal Relationships ...............................................................................3-14
Typical Bus Cycle with Wait States ............................................................................3-15
READY Pin Block Diagram .........................................................................................3-15

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CONTENTS

FIGURES
Figure
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-34
3-35
3-36
4-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8

Page
Generating a Normally Not·Ready Bus Signal ........................................................... 3-16
Generating a Normally Ready Bus Signal .................................................................. 3-17
Normally Not·Ready System Timing ..........................................................................3-18
Normally Ready System Timings ...............................................................................3-19
Typical Read Bus Cycle .............................................................................................3-21
Read·Only Device Interface .......................................................................................3-22
Typical Write Bus Cycle ..............................................................................................3-23
16-Bit Bus ReadlWrite Device Interface ..................................................................... 3-24
Interrupt Acknowledge Bus Cycle ...............................................................................3-26
Typical 82C59A Interface ...........................................................................................3-27
HALT Bus Cycle .........................................................................................................3-30
Returning to HALT After a HOLD/HLDA Bus Exchange ............................................ 3-31
Returning to HALT After a Refresh Bus Cycle ........................................................... 3-32
Exiting HALT (Powerdown Mode) ..............................................................................3-33
Exiting HALT (Active/Idle Mode) .................................................................................3-34
DEN and DT/R Timing Relationships .........................................................................3.35
Buffered AD Bus System ............................................................................................3-36
Qualifying DEN with Chip· Selects ..............................................................................3-37
Timing Sequence Entering HOLD ..............................................................................3-40
Refresh Request During HOLD ..................................................................................3-42
Latching HLDA ...........................................................................................................3-43
Exiting HOLD ..............................................................................................................3-44
PCB Relocation Register ..............................................................................................4-2
Clock Generator ...........................................................................................................5-1
Ideal Operation of Pierce Oscillator ..............................................................................5-2
Crystal Connections to Microprocessor ........................................................................ 5-3
Equations for Crystal Calculations ................................................................................ 5-4
Simple RC Circuit for Powerup Reset ..........................................................................5-7
Cold Reset Waveform ..................................................................................................5-8
Warm Reset Waveform ................................................................................................5-9
Clock Synchronization at Reset.. ................................................................................5-10
Power Control Register ..............................................................................................5-12
Entering Idle Mode .....................................................................................................5-13
HOLD/HLDA During Idle Mode ...................................................................................5-14
Entering Powerdown Mode ........................................................................................5-17
Powerdown Timer Circuit ...........................................................................................5-18
Common Chip·Select Generation Methods .................................................................. 6-2
Chip·Select Block Diagram ...........................................................................................6-3
Chip·Select Relative Timings .......................................................................................6-4
UCS Reset Configuration ............................................................................................. 6.5
START Register Definition ...........................................................................................6-7
STOP Register Definition .............................................................................................6-8
Wait State and Ready Control Functions ................................................................... 6-12
Overlapping Chip·Selects ........................................................................................... 6-13

intel~

CONTENTS

FIGURES
Figure
Page
Using Chip-Selects During HOLD ..............................................................................6-15
6-9
6-10
Typical System ...........................................................................................................6-16
Guarded Memory Detector .........................................................................................6-20
6-11
7-1
Refresh Control Unit Block Diagram .............................................................................7-1
7-2
Refresh Control Unit Operation Flow Chart .................................................................. 7-3
7-3
Refresh Address Formation ..........................................................................................7-4
Suggested DRAM Control Signal Timing Relationships .............................................•. 7-6
7-4
7-5
Formula for Calculating Refresh Interval for RFTIME Register .................................... 7-7
7-6
Refresh Base Address Register ...................................................................................7-8
Refresh Clock Interval Register ....................................................................................7-9
7-7
7-8
Refresh Control Register .... ........................................................................................7-10
7-9
Refresh Address Register .......................................................................................... 7-11
7-10
Regaining Bus Control to Run a DRAM Refresh Bus Cycle ...................................... 7-14
8-1
Interrupt Control Unit Block Diagram ............................................................................8-2
8-2
Using External 8259A Modules in Cascade Mode .......................................................8-8
8-3
Interrupt Control Unit Latency and Response Time ................................................... 8-11
8-4
Interrupt Control Register for Internal Sources ........................................................... 8-13
8-5
Interrupt Control Register for Noncascadable External Pins ...................................... 8-14
Interrupt Control Register for Cascadable Interrupt Pins ............................................ 8-15
8-6
Interrupt Request Register .........................................................................................8-16
8-7
Interrupt Mask Register ..............................................................................................8-17
8-8
Priority Mask Register ................................................................................................8-18
8-9
8-10
In-Service Register .....................................................................................................8-19
8-11
Poll Register ...............................................................................................................8-20
8-12
Poll Status Register ....................................................................................................8-21
8-13
End-ot-Interrupt Register ............................................................................................8-22
8-14
Interrupt Status Register ............................................................................................8-23
9-1
Timer/Counter Unit Block Diagram ...............................................................................9-2
9-2
Counter Element Multiplexing and Timer Input Synchronization .................................. 9-3
Timers 0 and 1 Flow Chart ...........................................................................................9-4
9-3
Timer/Counter Unit Output Modes................................................................................9-6
9-4
Timer 0 and Timer 1 Control Registers ........................................................................ 9-7
9-5
Timer 2 Control Register ..............................................................................................9-9
9-6
Timer Count Registers................................................................................................9-10
9-7
Timer Maxcount Compare Registers ..........................................................................9- 11
9-8
TxOUT Signal Timing .................................................................................................9-15
9-9
Typical 10-Bit Asynchronous Data Frame .................................................................. 10-2
10-1
10-2
RX Machine ................................................................................................................ 10-3
10-3
TX Machine ................................................................................................................ 10-5
Mode 1 Waveform ...................................................................................................... 10-6
10-4
Mode 3 Waveform ...................................................................................................... 10-7
10-5
Mode 4 Waveform .............................................. ,....................................................... 10-7
10-6
10-7
Mode 0 Waveforms .................................................................................................... 10-8
Serial Receive Buffer Register (SxRBUF) .................................................................. 10-9
10-8

xii

CONTENTS

FIGURES
Figure
10-9
10-10
10-11
10-12
10-13
10-14
10-15
10-16
10-17
10-18
10-19
10-20
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
12-1
12-2
12-3
12-4
13-1
A-1
A-2
A-3
A-4
A-5
A-6
B-1

Page
Serial Transmit Buffer Register (SxTBUF) ............................................................... 10-10
Baud Rate Counter Register (BxCNT) ..................................................................... 10-11
Baud Rate Compare Register (BxCMP} ................................................................... 10-12
Calculating the BxCMP Value for a Specific Baud Rate ........................................... 10-12
Serial Port Control Register (SxCON) ...................................................................... 10-15
Serial Port Status Register (SxSTS} ......................................................................... 10-16
CTS Recognition Sequence ..................................................................................... 10-19
BCLK Synchronization ............................................................................................. 10-19
Mode 0, BxCMP > 2 ................................................................................................. 10-20
Channel 0 Interrupts ................................................................................................. 10-22
Channel 1 Interrupts ................................................................................................. 10-22
Master/Slave Example ............................................................................................. 10-28
Simplified Logic Diagram of a Bidirectional Port Pin .................................................. 11-2
Simplified Logic Diagram of an Input Port Pin ............................................................ 11-4
Simplified Logic Diagram of an Output Port Pin ......................................................... 11-5
Simplified Logic Diagram of an Open-Drain Bidirectional Port... ................................ 11-6
Port Control Register (PxCON) .................................................................................. 11-8
Port Direction Register (PxDIR} .................................................................................. 11-9
Port Data Latch Register (PxLTCH) ......................................................................... 11-1 0
Port Pin State Register (PxPIN) ............................................................................... 11-11
80C187-Supported Data Types .................................................................................. 12-8
8OC186 Modular Core Family/80C187 System Configuration .................................... 12-9
80C187 Configuration with a Partially Buffered Bus ................................................. 12-12
80C187 Exception Trapping via Processor Interrupt Pin .......................................... 12-14
Entering/Leaving ONCE Mode ................................................................................... 13-1
Formal Definition of ENTER ........................................................................................ A-3
Variable Access in Nested Procedures ....................................................................... A-4
Stack Frame for Main at LevelL ................................................................................. A-4
Stack Frame for Procedure A at Level 2 ..................................................................... A-5
Stack Frame for Procedure B at Level 3 Called from A. .............................................. A-6
Stack Frame for Procedure C at Level 3 Called from B .............................................. A-7
Input Synchronization Circuit. ...................................................................................... B-1

xiii

CONTENTS

TABLES
Table
1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
3-1
3-2
3-3
3-4
3-5
3-6
3-7
4-1
5-1
5-2
6-1
6-2
6-3
7-1
8-1
8-2
8-3
9-1
9-2
10-1
11-1
11-2
12-1
12-2
12-3
12-4
12-5
12-6
12-7
C-l

xiv

Page
Comparison of 80C186 Modular Core Family Products ............................................... 1-2
Related Documents and Software ................................................................................ 1-3
Implicit Use of General Registers .................................................................................2-5
Logical Address Sources ............................................................................................2-13
Data Transfer Instructions ..........................................................................................2-18
Arithmetic Instructions ................................................................................................2-20
Arithmetic Interpretation of 8-Bit Numbers .................................................................2-21
Bit Manipulation Instructions ......................................................................................2-21
String Instructions .......................................................................................................2-22
String Instruction Register and Flag Use ..................•................................................. 2-23
Program Transfer Instructions ....................................................................................2-25
Interpretation of Conditional Transfers .......................................................................2-26
Processor Control Instructions ...................................................................................2-27
Supported Data Types ...............................................................................................2-37
Bus Cycle Types ......................................................................................................•.3-12
Read Bus Cycle Types ...............................................................................................3-20
Read Cycle Critical Timing Parameters ...................................................................... 3-20
Write Bus Cycle Types ''',',''''''''''',','','','''','''', ........................................................... 3-23
Write Cycle Critical Timing Parameters ......................................................................3-25
HALT Bus Cycle Pin States ........................................................................................3-29
Signal Condition Entering HOLD ................................................................................3-40
Peripheral Control Block ...............................................................................................4-3
Suggested Values for Inductor L 1 in Third Overtone Oscillator Circuit ........................ 5-4
Summary of Power Management Modes ................................................................... 5-19
Chip-Select Unit Registers ...........................................................................................6-5
Memory and I/O Compare Addresses ........................................................................ 6-10
Example Adjustments for Overlapping Chip-Selects .................................................. 6-14
Identification of Refresh Bus Cycles .............................................................................7-5
Default Interrupt Priorities .............................................................................................8-3
Fixed Interrupt Types ...................................................................................................8-9
Interrupt Control Unit Registers ..................................................................................8-11
Timer 0 and 1 Clock Sources .....................................................................................9-12
Timer Retriggering ...............................................................................,...................... 9-13
BxCMP Values for Typical Baud Rates and CPU Frequencies ................................ l0-13
Port 1 Multiplexing Options ........................................................................................ 11-7
Port 2 Multiplexing Options ........................................................................................11-7
80C187 Data Transfer Instructions............................................................................. 12-3
80C187 Arithmetic Instructions................................................................................... 12-4
80C187 Comparison Instructions ............................................................................... 12-5
80C187 Transcendental Instructions .......................................................................... 12-5
80C187 Constant Instructions .................................................................................... 12-6
80C187 Processor Control Instructions ...................................................................... 12-6
80C 187 I/O Port Assignments .................................................................................. 12-10
Instruction Format Variables ........................................................................................ C-l

intel~

CONTENTS

TABLES
Table

C-2
C-3
C-4
0-1
0-2
0-3
0-4
0-5

Page

Instruction Operands ................................................................................................... C-2
Flag Bit Functions ... ..................................................................................................... C-3
Instruction Set ... .......................................................................................................... C-4
Operand Variables ...................................................................................................... 0-1
Instruction Set Summary ............................................................................................. 0-2
Machine Instruction Oecoding Guide........................................................................... 0-9
Mnemonic Encoding Matrix (Left Half) ...................................................................... 0-20
Abbreviations for Mnemonic Encoding Matrix ........................................................... 0-22

CONTENTS

EXAMPLES
Example
Page
5-1
Initializing the Power Management Unit for Idle or Powerdown Mode ....................... 5-16
6-1
Initializing the Chip-Select Unit... ................................................................................ 6-17
7-1
Initializing the Refresh Control Unit ............................................................................7-12
8-1
Initializing the Interrupt Control Unit ...........................................................................8-24
9-1
Configuring a Real-Time Clock...................................................................................9-18
9-2
Configuring a Square-Wave Generator ......................................................................9-21
9-3
Configuring a Digital One-Shot ................................................................................... 9-22
10-1
Asynchronous Mode 4 Example ............................................................................... 10-23
10-2
Mode 0 Example ......................................................................................................10-26
10-3
Master/Slave - Implementing the Master/Slave Routines ............ : ......................... 10-29
10-4
Master/Slave - The _selecCslave Routine ............................................................. 10-30
10-5
Master/Slave - The slave_1 Routine ...................................................................... 10-32
10-6
Master/Slave - The _send_slave_command Routine ............................................ 10-35
11-1
I/O Port Programming Example ................................................................................ 11-12
12-1
Initialization Sequence for 80C 187 Math Coprocessor ............................................ 12-15
12-2
Floating Point Math Routine Using FSI NCOS .......................................................... 12-16

xvi

in1:et

Introduction

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CHAPTER 1
INTRODUCTIO'N
The 8086 microprocessor was first introduced in 1978 and gained rapid support as the microcomputer engine of choice. There are literally millions of 8086/8088-based systems in the world today. The amount of software written for the 8086/8088 is rivaled by no other architecture.
By the early 1980's, however, it was clear that a replacement for the 8086/8088 was necessary.
An 8086/8088 system required dozens of support chips to implement even a moderately complex
design. Intel recognized the need to integrate commonly used system peripherals onto the same
silicon die as the CPU. In 1982 Intel addressed this need by introducing the 80186/80188 family
of embedded microprocessors. The original 80186/80188 integrated an enhanced 808618088
CPU with six commonly used system peripherals. A parallel effort within Intel also gave rise to
the 80286 microprocessor in 1982. The 80286 began the trend toward the very high performance
Intel architecture that today includes the Inte1386™, Intel486™ and Pentium™ microprocessors.
As technology advanced and turned toward small geometry CMOS processes, it became clear
that a new 80186 was needed. In 1987 Intel announced the second generation ofthe 80186 family:
the 8OC186/C188. The 80C186 family is pin compatible with the 80186 family, while adding an
enhanced feature set. The high-performance CHMOS III process allowed the 80C186 to run at
twice the clock rate of the NMOS 80186, while consuming less than one-fourth the power.
The 80186 family took another major step in 1990 with the introduction of the 80C186EB family.
The 80C 186EB heralded many changes for the 80186 family. First, the enhanced 8086/8088 CPU
was redesigned as a static, stand-alone module known as the 80C186 Modular Core. Second, the
80186 family peripherals were also redesigned as static modules with standard interfaces. The
goal behind this redesign effort was to give Intel the capability to proliferate the 80186 family
rapidly, in order to provide solutions for an even wider range of customer applications.
The 80C186EB/C188EB was the first product to use the new modular capability. The
8OC186EB/C188EB includes a different peripheral set than the original 80186 family. Power
consumption was dramatically reduced as a direct result of the static design, power management
features and advanced CHMOS N process. The 80C186EB/C188EB has found acceptance in a
wide array of portable equipment ranging from cellular phones to personal organizers.
In 1991 the 80C186 Modular Core family was again extended with the introduction of three new
products: the 80C186XL, the 80C186EA and the 80C186EC. The 80C186XL/C188XL is a higher performance, lower power replacement for the 8OC186/C188. The 8OC186EAlC188EA combines the feature set of the 8OC186 with new power management features for power-critical
applications. The 80C 186EC/C 188EC offers the highest level of integration of any of the 80C 186
Modular Core family products, with 14 on-chip peripherals (see Table 1-1).

1-1

INTRODUCTION

The 80C186 Modular Core family is the direct result often years ofIntel development. It offers
the designer the peace of mind of a well-established architecture with the benefits of state-of-theart technology.
Table 1-1. Comparison of 80C186 Modular Core Family Products

1.1

HOW TO USE THIS MANUAL

This manual uses phrases such as 80C186 Modular Core Family or 80C188 Modular Core, as
well as references to specific products such as 80C188EA. Each phrase refers to a specific set of
80C186 family products. The phrases and the products they refer to are as follows:

80C186 Modular Core Family: This phrase refers to any device that uses the modular
80C186/C188 CPU core architecture. At this time these include the 80C186EAlC188EA,
80CI86EB/CI88EB, 80C186EC/C188EC and 8OC186XLlC188XL.
80C186 Modular Core: Without the word/amity, this phrase refers only to the 16-bit bus members of the 80C 186 Modular Core Family.
80C188 Modular Core: This phrase refers to the 8-bit bus products.
80C188EC: A specific product reference refers only to the named device. For example, On the
80C188EC. .. refers strictly to the 80C188EC and not to any other device.

1-2

INTRODUCTION

Each chapter covers a specific section of the device, beginning with the CPU core. Each peripheral chapter includes programming examples intended to aid in your understanding of device operation. Please read the comments carefully, as not all of the examples include all the code
necessary for a specific application.
This user's guide is a supplement to the device data sheet. Specific timing values are not discussed in this guide. When designing a system, always consult the most recent version of the device data sheet for up-to-date specifications.

1.2

RELATED DOCUMENTS

The following table lists documents and software that are useful in designing systems that incorporate the 80C186 Modular Core Family. These documents are available through Intel Literature.
In the U.S. and Canada, call 1-800-548-4725 to order. In Europe and other international locations,
please contact your local Intel sales office or distributor.
NOTE

If you will be transferring a design from the 80186/80188 or 8OC186/80C188
to the 80C186XL/80C188XL, refer to FaxBack Document No. 2132.
Table 1-2. Related Documents and Software
Document/Software Title

Document
Order No.

Embedded Microprocessors (includes 186 family data sheets)

272396

186 Embedded Microprocessor Line Card

272079

80186/80188 High-Integration 16-Bit Microprocessor Data Sheet

272430

80C186XUC188XL-20, -12 16-Bit High-Integration Embedded Microprocessor
Data Sheet

272431

80C186EAl80C188EA-20, -12 and 80L 186EAl80L188EA-13, -8 (low power
versions) 16-Bit High-Integration Embedded Microprocessor Data Sheet

272432

80C186EB/80C188EB-20, -13 and 80L 186EB/80L188EB-13, -8 (low power
versions) 16-Bit High-Integration Embedded Microprocessor Data Sheet

272433

80C186EC/80C188EC-20, -13 and 80L 186EC/80L188EC-13, -8 (low power
versions) 16-Bit High-Integration Embedded Microprocessor Data Sheet

272434

80C187 80-Bit Math Coprocessor Data Sheet

270640

Low Voltage Embedded Design

272324

80C186/C188, 80C186XUC188XL Microprocessor User's Manual

272164

80C186EAl80C188EA Microprocessor User's Manual

270950

80C186EB/80C188EB Microprocessor User's Manual

270830

80C186EC/80C188EC Microprocessor User's Manual

272047

8086/8088/8087/80186/80188 Programmer's Pocket Reference Guide

231017

1-3

INTRODUCTION

Table 1-2. Related Documents and Software (Continued)
Document/Software Title
8086/8088 User's Manual Programmer's and Hardware Reference Manual

Document
Order No.
240487

ApBUILDER Software

272216

80C186EA Hypertext Manual

272275

80C186EB Hypertext Manual

272296

80C186EC Hypertext Manual

272298

80C186XL Hypertext Manual

272630

ZCON - Z80 Code Converter

Available on BBS

1.3

CUSTOMER SERVICE

This section provides telephone numbers and describes various customer services.
• Customer Support (U.S. and Canada) 800-628-8686
• Customer Training (U.S. and Canada) 800-234-8806
• Literature Fulfillment
-

800-548-4725 (U.S. and Canada)

+44(0)793-431155 (Europe)

• FaxBack* Service
800-628-2283 (U.S. and Canada)
+44(0)793-496646 (Europe)
916-356-3105 (worldwide)
• Application Bulletin Board System
916-356-3600 (worldwide, up to 14.4-Kbaud line)
916-356-7209 (worldwide, dedicated 2400-baud line)
+44(0)793-496340 (Europe)
Intel provides 24-hour automated technical support through the use of our FaxBack service and
our centralized Intel Application Bulletin Board System (BBS). The FaxBack service is a simpleto-use information system that lets you order technical documents by phone for immediate delivery to your fax machine. The BBS is a centralized computer bulletin board system that provides
updated application-specific information about Intel products.

1-4

intet
1.3.1

INTRODUCTION

How to Use Intel's FaxBack Service

Think of the FaxBack service as a library of technical documents that you can access with your
phone. Just dial the telephone number (see page 1-4) and respond to the system prompts. After
you select a document, the system sends a copy to your fax machine.
Each document is assigned an order number and is listed in a subject catalog. First-time users
should order the appropriate subject catalogs to get a complete listing of document order numbers.
The following catalogs and information packets are available:

Microcontroller, Flash, and iPLD catalog

Development tool catalog

System catalog

DVI and multimedia catalog

BBS catalog

Microprocessor and peripheral catalog

Quality and reliability catalog

Technical questionnaire

1.3.2

How to Use Intel's Application BBS

The Application Bulletin Board System (BBS) provides centralized access to information, software drivers, firmware upgrades, and revised software. Any user with a modem and computer can
access the BBS. Use the following modem settings.
•

14400, N, 8, 1

If your modem does not support 14.4K baud, the system provides auto configuration support for
1200- through 14.4K-baud modems.
To access the BBS, just dial the telephone number (see page 1-4) and respond to the system
prompts. During your first session, the system asks you to register with the system operator by
entering your name and location. The system operator will then set up your access account within
24 hours. At that time, you can access the files on the BBS. For a listing of files, call the FaxBack
service and order catalog #6 (the BBS catalog).

1-5

INTRODUCTION

intela.

If you ~ncounter any difficulty accessing our high-speed modem, try our dedicated 2400-baud
modem (see page 1-4). Use the following modem settings.
• 2400 baud, N, 8, 1

1.3.3

How to Find the Latest ApBUILDER Flies, Hypertext Manuals, and
Data Sheets on the BBS

The latest ApBUILDER files and hypertext manuals and data sheets are available first from the
BBS. To access the files:
1.

Select [F] from the BBS Main menu.

Select [L] from the Intel Apps Files menu.

The BBS displays the list of all area levels and prompts for the area number.

Select [25] to choose the ApBUILDER I Hypertext area.

Area level 25 has four sublevels: (1) GeJ;leral, (2) 196 Files, (3) 186 Files, and (4) 8051
Files.

Select [1] to find the latest ApBUILDER files or the number of the appropriate productfamily sublevel to find the hypertext manuals and data sheets.

Enter the file number to tag the files you wish to download. The BBS displays the approximate download time for tagged files.

1-6

2
Overview of the
80C186 Family
Architecture

CHAPTER 2
OVERVIEW OF THE 80C186 FAMILY
ARCHITECTURE
The 8OC186 Modular Microprocessor Core shares a common base architecture with the 8086,
8088, 80186, 80188, 80286, Intel386™ and Intel486™ processors. The 8OC186 Modular Core
maintains full object-code compatibility with the 8086/8088 family of 16-bit microprocessors,
while adding hardware and software performance enhancements. Most instructions require fewer
clocks to execute on the 8OC186 Modular Core because of hardware enhancements in the Bus
Interface Unit and the Execution Unit. Several additional instructions simplify programming and
reduce code size (see Appendix A, "8OC186 Instruction Set Additions and Extensions").

2.1

ARCHITECTURAL OVERVIEW

The 8OC186 Modular Microprocessor Core incorporates two separate processing units: an Execution Unit (EU) and a Bus Interface Unit (BIU). The Execution Unit is functionally identical
among all family members. The Bus Interface Unit is configured for a 16-bit external data bus
for the 80C186 core and an 8-bit external data bus for the 8OC188 core. The two units interface
via an instruction prefetch queue.
The Execution Unit executes instructions; the Bus Interface Unit fetches instructions, reads operands and writes results. Whenever the Execution Unit requires another opcode byte, it takes the
byte out of the prefetch queue. The two units can operate independently of one another and are
able, under most circumstances, to overlap instruction fetches and execution.
The 80C186 Modular Core family has a 16-bit Arithmetic Logic Unit (ALU). The Arithmetic
Logic Unit performs 8-bit or 16-bit arithmetic and logical operations. It provides for data movement between registers, memory and 110 space.
The 8OC186 Modular Core family CPU allows for high-speed data transfer from one area of
memory to another using string move instructions and between an 110 port and memory using
block 110 instructions. The CPU also provides many conditional branch and control instructions.
The 8OC186 Modular Core architecture features 14 basic registers grouped as general registers,
segment registers, pointer registers and status and control registers. The four 16-bit general-purpose registers (AX, BX, CX and DX) can be used as open~nds for most arithmetic operations as
either 8- or 16-bit units. The four 16-bit pointer registers (SI, 01, BP and SP) can be used in arithmetic operations and in accessing memory-based variables. Four 16-bit segment registers (CS,
DS, SS and ES) allow simple memory partitioning to aid modular programming. The status and
control registers consist of an Instruction Pointer (IP) and the Processor Status Word (PSW) register, which contains flag bits. Figure 2-1 is a simplified CPU block diagram.

2-1

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Address Bus (20 Bits)
I
1:

General
Registers
AH
BH
CH
OH

AL
BL
CL
OL

Data
Bus
(16 Bits)

SP
BP
SI

OS
SS
IP
ALU Data Bus

(16 Bits)

Temporary
Registers

1M
.I .

EU
Control
System

Flags

Execution Unit
(EU)

Internal
Communications
Registers

II'
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Control
I
Logic
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I Instruction Queue

'"'--

External
Bus

~~1 213141516~
: " Q Bus
(8 Bits)
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Bus Interface Unit
(BIU)
A1012-0A

Figure 2-1. Simplified Functional Block Diagram of the 80C186 Family CPU

2.1.1

Execution Unit

The Execution Unit executes all instructions, provides data and addresses to the Bus Interface
Unit and manipulates the general registers and the Processor Status Word. The 16-bit ALU within
the Execution Unit maintains the CPU status and control flags and manipulates the general registers and instruction operands. All registers and data paths in the Execution Unit are 16 bits wide
for fast internal transfers.

2-2

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

The Execution Unit does not connect directly to the system bus. It obtains instructions from a
queue maintained by the Bus Interface Unit. When an instruction requires access to memory or a
peripheral device, the Execution Unit requests the Bus Interface Unit to read and write data. Addresses manipulated by the Execution Unit are 16 bits wide. The Bus Interface Unit, however,
performs an address calculation that allows the Execution Unit to access the full megabyte of
memory space.
To execute an instruction, the Execution Unit must first fetch the object code byte from the instruction queue and then execute the instruction. If the queue is empty when the Execution Unit
is ready to fetch an instruction byte, the Execution Unit waits for the Bus Interface Unit to fetch
the instruction byte.

2.1.2

Bus Interface Unit

The 8OC186 Modular Core and 8OC188 Modular Core Bus Interface Units are functionally identical. They are implemented differently to match the structure and performance characteristics of
their respective system buses. The Bus Interface Unit executes all external bus cycles. This unit
consists of the segment registers, the Instruction Pointer, the instruction code queue and several
miscellaneous registers. The Bus Interface Unit transfers data to and from the Execution Unit on
the ALU data bus.
The Bus Interface Unit generates a 20-bit physical address in a dedicated adder. The adder shifts
a 16-bit segment value left 4 bits and then adds a 16-bit offset. This offset is denved from combinations of the pointer registers, the Instruction Pointer and immediate values (see Figure 2-2).
Any carry from this addition is ignored.

1 2
15

Segment Base )

Offset

Logical
Address

+
Physical Address

=
To Memory

A1500·0A

Figure 2-2. Physical Address Generation

2-3

in1et.

OVERVIEW OF THE aoC186 FAMILY ARCHITECTURE

During periods when the Execution Unit is busy executing instructions, the Bus Interface Unit
sequentially prefetches instructions from memory. As long as the prefetch queue is partially full,
the Execution Unit fetches instructions.

2.1.3

General Registers

The 8OC186 Modular Core family CPU has eight 16-bit general registers (see Figure 2-3). The
general registers are subdivided into two sets of four registers. These sets are the data registers
(also called the H & L group for high and low) and the pointer and index registers (also called the
P& I group).

AX
..................................-:..................................

Accumulator

··································T···················..............
Data
Group

Base

...................................,.................................. Count
CH

.......................................................................................
DH
!!
DL

Pointer
and
Index
Group

Data

Stack Pointer

Base Pointer

Source Index

Destination Index
Al033-0A

Figure 2-3. General Registers

2-4

in1et

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

The data registers can be addressed by their upper or lower halves. Each data register can be used
interchangeably as a 16-bit register or two 8-bit registers. The pointer registers are always accessed as 16-bit values. The CPU can use data registers without constraint in most arithmetic and logic operations. Arithmetic and logic operations can also use the pointer and index registers. Some
instructions use certain registers implicitly (see Table 2-1), allowing compact encoding.
Table 2-1. Implicit Use of General Registers
Register

Operations

Word Multiply, Word Divide, Word 1/0

Byte Multiply, Byte Divide, Byte 1/0, Translate, Decimal Arithmetic

Byte Multiply, Byte Divide

Translate

String Operations, Loops

Variable Shift and Rotate

Word Multiply, Word Divide, Indirect 1/0

Stack Operations

String Operations

The contents of the general-purpose registers are undefined following a processor reset.

2.1.4

Segment Registers

The 80C186 Modular Core family memory space is 1 Mbyte in size and divided into logical segments of up to 64 Kbytes each. The CPU has direct access to four segments at a time. The segment
registers contain the base addresses (starting locations) of these memory segments (see Figure
2-4). The CS register points to the current code segment, which contains instructions to be
fetched. The SS register points to the current stack segment, which is used for all stack operations.
The DS register points to the current data segment, which generally contains program variables.
The ES register points to the current extra segment, which is typically used for data storage. The
CS register initializes to OFFFFH, and the SS, DS and ES registers initialize to OOOOH. Programs
can access and manipulate thetgment registers with several instructions.

&5""1c

2-5

intet

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

15
CS
DS

I Code Segment

r-----------------------~

Data Segment

1--__________S_S_________---1

Stack Segment

Extra Segment

~----------------------~

Figure 2-4. Segment Registers

2.1.5

Instruction Pointer

The Bus Interface Unit updates the 16-bit Instruction Pointer (IP) register so it contains the offset
of the next instruction to be fetched. Programs do not have direct access to the Instruction Pointer,
but it can change, be saved or be restored as a result of program execution. For example, if the
Instruction Pointer is saved on the stack, it is first automatically adjusted to point to the next instruction to be executed.

Reset initializes the Instruction Pointer to OOOOH. The CS and IP values comprise a starting execution address of OFFFFOH (see "Logical Addresses" on page 2-10 for a description of address
formation).

2-6

intet,
2.1.6

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Flags

The 80C186 Modular Core family has six status flags (see Figure 2-5) that the Execution Unit
posts as the result of arithmetic or logical operations. Program branch instructions allow a program to alter its execution depending on conditions flagged by a prior operation. Different instructions affect the status flags differently, generally reflecting the following states:
• If the Auxiliary Flag (AF) is set, there has been a carry out from the low nibble into the high
nibble or a borrow from the high nibble into the low nibble of an 8-bit quantity (low-order
byte of a 16-bit quantity). This flag is used by decimal arithmetic instructions.
• If the Carry Flag (CF) is set, there has been a carry out of or a borrow into the high-order bit
of the instruction result (8- or 16-bit). This flag is used by instructions that add or subtract
multibyte numbers. Rotate instructions can also isolate a bit in memory or a register by
placing it in the Carry Flag.

• If the Overflow Flag (OF) is set, an arithmetic overflow has occurred. A significant digit
has been lost because the size of the result exceeded the capacity of its destination location.
An Interrupt On Overflow instruction is available that will generate an interrupt in this
situation.
• If the Sign Flag (SF) is set, the high-order bit of the result is a 1. Since negative binary
numbers are represented in standard two's complement notation, SF indicates the sign of the
result (0 = positive, 1 =negative).
• If the Parity Flag (PF) is set, the result has even parity, an even number of 1 bits. This flag
can be used to check for data transmission errors.

• If the Zero Flag (ZF) is set, the result of the operation is zero.
Additional control flags (see Figure 2-5) can be set or cleared by programs to alter prpcessor operations:
• Setting the Direction Flag (DF) causes string operations to auto-decrement. Strings are
processed from high address to low address (or "right to left"). Clearing DF causes string
operations to auto-increment. Strings are processed from low address to high address (or
"left to right").
• Setting the Interrupt Enable Flag (IF) allows the CPU to recognize maskable external or
internal interrupt requests. Clearing IF disables these interrupts. The Interrupt Enable Flag
has no effect on software interrupts or non-maskable interrupts.
• Setting the Trap Flag (TF) bit puts the processor into single-step mode for debugging. In
this mode, the CPU automatically generates an interrupt after each instruction. This allows
a program to be inspected instruction by instruction during execution.
The status and control flags are contained in a 16-bit Processor Status Word (see Figure 2-5). Reset initializes the Processor Status Word to OFOOOH.

2-7

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

2.1.7

Memory Segmentation

Programs for the 8OC186 Modular Core family view the 1 Mbyte memory space as a group of
user-defined segments. A segment is a logical unit of memory that can be up to 64 Kbytes long.
Each segment is composed of contiguous memory locations. Segments are independent and separately addressable. Software assigns every segment a base address (starting location) in memory
space. All segments begin on 16-byte memory boundaries. There are no other restrictions on segment locations. Segments can be adjacent, disjoint, partially overlapped or fully overlapped (see
Figure 2-6). A physical memory location can be mapped into (covered by) one or more logical
segments.

2-8

intet~

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Processor Status Word

PSW (FLAGS)

Posts CPU status information.

F F F F

s Z
F F

Al035-0A

Bit
Mnemonic

Bit Name

Reset
State

Overflow Flag

If OF Is set, an arithmetic overflow has occurred.

Direction Flag

If OF Is set, string Instructions are processed high
address to low address. If OF Is clear, strings are
processed low address to high address.

Interrupt
Enable Flag

If IF is set, the CPU recognizes maskable interrupt
requests. If IF is clear, maskable Interrupts are
ignored.

Trap Flag

If TF is set, the processor enters single-step mode.

Sign Flag

If SF is set, the high-order bit of the result of an
operation Is 1, indicating It Is negative.

Zero Flag

If ZF Is set, the result of an operation Is zero.

Function

Auxiliary Flag

If AF Is set, there has been a carry from the low
nibble to the high or a borrow from the high nibble
to the low nibble of an a-bit quantity. Used In BCD
operations.

Parity Flag

If PF is set, the result of an operation has even
parity.

Carry Flag

If CF Is set, there has been a carry out of, or a
borrow Into, the hlgh-order bit of the result of an
instruction.

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a
logic zero to ensure compatibility with future Intel products.

Figure 2-5. Processor Status Word

2-9

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Fully

Overlapped

Logical
Segments

~t-----+--l---t-}--+-}---......I(}
OH

10000H

20000H

Physical
Memory

30000H
Al036-0A

Figure 2-6. Segment Locations in Physical Memory

The four segment registers point to four "currently addressable" segments (see Figure 2-7). The
currently addressable segments provide a work space consisting of 64 Kbytes for code, a 64
Kbytes for stack and 128 Kbytes for data storage. Programs access code and data in another segment by updating the segment register to point to the new segment.

2.1.8

Logical Addresses

It is useful to think of every memory location as having two kinds of addresses, physical and logical. A physical address is a 20-bit value that identifies a unique byte location in the memory
space. Physical addresses range from OH to OFFFFFH. All exchanges between the CPU and
memory use physical addresses.

Programs deal with logical rather than physical addresses. Program code can be developed without prior knowledge of where the code will be located in memory. A logical address consists of
a segment base value and an offset value. For any given memory location, the segment base value
locates the first byte of the segment. The offset value represents the distance, in bytes, of the target
location from the beginning of the segment. Segment base and offset values are unsigned 16-bit
quantities. Many different logical addresses can map to the same physical location. In Figure 2-8,
physical memory location 2C3H is contained in two different overlapping segments, one beginning at 2BOH and the other at 2COH.

2-10

intet~

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

FFFFFH

A
B
Data:

DS:

~--------

Code:

CS:

~------1

Stack:

SS:

~---

Extra:

ES:

G
D

I
I
I
I
I
I
I
I

OH
A1037-{)A

Figure 2-7. Currently Addressable Segments

The segment register is automatically selected according to the rules in Table 2-2. All information
in one segment type generally shares the same logical attributes (e.g., code or data). This leads to
programs that are shorter, faster and better structured.
The Bus Interface Unit must obtain the logical address before generating the physical address.
The logical address of a memory location can come from different sources, depending on the type
of reference that is being made (see Table 2-2).
Segment registers always hold the segment base addresses. The Bus Interface Unit determines
which segment register contains the base address according to the type of memory reference
made. However, the programmer can explicitly direct the Bus Interface Unit to use any currently .
addressable segment (except for the destination operand of a string instruction). In assembly language, this is done by preceding an instruction with a segment override prefix.

2-11

OVERVIEW OF THE aoC186 FAMILY ARCHITECTURE

,....

,....
2 C4H

Physical
Address

2C3H

J "

2 C2H

Offset
(3H)

2 C1H

Segment~

2 COH

Base

2 BFH
2 BEH
2 BOH
2 BCH
2 BBH
Offset
(13H)

Logical
Addresses

2 BAH
2 B9H
2 B8H
2 B7H
2 B6H
2 BSH
2 B4H
2 B3H
2 B2H
2 B1H

Segment
Base

2 BOH

~
Al038-0A

Figure 2-8. Logical and Physical Address

2·12

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Table 2-2. Logical Address Sources
Default
Segment Base

Alternate
Segment Base

Instruction Fetch

NONE

Stack Operation

NONE

Variable (except following)

CS, ES, SS

Effective Address

Type of Memory Reference

Offset

String Source

CS, ES, SS

String Destination

NONE

BP Used as Base Register

CS,DS,ES

Effective Address

Instructions are always fetched from the current code segment. The IP register contains the instruction's offset from the beginning of the segment. Stack instructions always operate on the current stack segment. The Stack Pointer (SP) register contains the offset of the top of the stack from
the base of the stack. Most variables (memory operands) are assumed to reside in the current data
segment, but a program can instruct the Bus Interface Unit to override this assumption. Often, the
offset of a memory variable is not directly available and must be calculated at execution time. The
addressing mode specified in the instruction determines how this offset is calculated (see "Addressing Modes" on page 2-27). The result is called the operand's Effective Address (EA).
Strings are addressed differently than other variables. The source operand of a string instruction
is assumed to lie in the current data segment. However, the program can use another currently
addressable segment. The operand's offset is taken from the Source Index (SI) register. The destination operand of a string instruction always resides in the current extra segment. The destination's offset is taken from the Destination Index (DI) register. The string instructions
automatically adjust the SI and DI registers as they process the strings one byte or word at a time.
When an instruction designates the Base Pointer (BP) register as a base register, the variable is
assumed to reside in the current stack segment. The BP register provides a convenient way to access data on the stack. The BP register can also be used to access data in any other currently addressable segment.

2.1.9

Dynamically Relocatable Code

The segmented memory structure of the 80C 186 Modular Core family allows creation of dynamically relocatable (position-independent) programs. Dynamic relocation allows a multiprogramming or multitasking system to make effective use of available memory. The processor can write
inactive programs to a disk and reallocate the space they occupied to other programs. A disk-resident program can then be read back into available memory locations and restarted whenever it
is needed. If a program needs a large contiguous block of storage and the total amount is available
only in non-adjacent fragments, other program segments can be compacted to free enough continuous space. This process is illustrated in Figure 2-9.

2-13

OVERVIEW OF THE SOC186 FAMILY ARCHITECTURE

After
Relocation

Before
Relocation

Code
Segment

Stack
Segment

r--

CS
SS
OS
ES

I-I-

Code
Segment

Data
Segment

Stack
Segment
Data
Segment
Extra
Segment

Extra
Segment
"

DFreespace
Al039-0A

Figure 2-9. Dynamic Code Relocation

To be dynamically relocatable, a program must not load or alter its segment registers and must
not transfer directly to a location outside the current code segment. All program offsets must be
relative to the segment registers. This allows the program to be moved anywhere in memory, provided that the segment registers are updated to point to the new base addresses.

2-14

intet

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

2.1.10 Stack Implementation
Stacks in the 80C 186 Modular Core family reside in memory space. They are located by the Stack
Segment register (SS) and the Stack Pointer (SP). A system can have multiple stacks, but only
one stack is directly addressable at a time. A stack can be up to 64 Kbytes long, the maximum
length of a segment. Growing a stack segment beyond 64 Kbytes overwrites the beginning of the
segment. The SS register contains the base address of the current stack. The top of the stack, not
the base address, is the origination point of the stack. The SP register contains an offset that points
to the Top of Stack (TOS).
Stacks are 16 bits wide. Instructions operating on a stack add and remove stack elements one
word at a time. An element is pushed onto the stack (see Figure 2-10) by first decrementing the
SP register by 2 and then writing the data word. An element is popped off the stack by copying it
from the top of the stack and then incrementing the SP register by 2. The stack grows J!own in
memory toward its base address. Stack operations never move or erase elements on the stack. The
top of the stack changes only as a result of updating the stack pointer.

2.1.11

Reserved Memory and 110 Space

Two specific areas in memory and one area in I/O space are reserved in the 8OC186 Core family.
• Locations OH through 3FFH in low memory are used for the Interrupt Vector Table.
Programs should not be loaded here.
• Locations OFFFFOH through OFFFFFH in high memory are used for system reset code
because the processor begins execution at OFFFFOH.
• Locations OF8H through OFFH in I/O space are reserved for communication with other Intel
hardware products and must not be used. On the 8OC186 core, these addresses are used as
I/O ports for the 80C187 numerics processor extension.

2-15

intet

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

POP AX
POPBX

Existing
Stack
",r"'

",r"'

112 1 34 ~-.... ~
"'~

1 BB 1 AA

I---i

1062

1060

1ii
'0

105E

105B

105A

105B
TOS
.... 105A

=0
III

1058

1056

1054

1052

1060

105E

105B

105A
TOS
.... 1058
1056

1054

I·

~
c:~
CD 0
III

!US
Coc:
'0 0

r'05O CD: EF :.

1 10

50 SS

I 00

1----

1052

110 1 50

1062

PUSH AX

TOS
.... 1056

..,i

__ I

1
1
1

r'05O CD: EF : [050 : CD: EF
1 10

50 SS

I 00

I
I

50 1SS

Stack operation for code sequence
PUSH AX
POP AX
POPBX
Al013-0A

Figure 2-10. Stack Operation

2-16

in1et
2.2

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

SOFTWARE OVERVIEW

All 80C186 Modular Core family members execute the same instructions. This includes all the
8086/8088 instructions plus several additions and enhancements (see Appendix A, "8OC186 Instruction Set Additions and Extensions"). The following sections describe the instructions by category and provide a detailed discussion of the operand addressing modes.
Software for 80C186 core family systems need not be written in assembly language. The processor provides direct hardware support for programs written in the many high-level languages
available. The hardware addressing modes provide straightforward implementations of based
variables, arrays, arrays of structures and other high-level language data constructs. A powerful
set of memory-to-memory string operations allow efficient character data manipulation. Finally,
routines with critical performance requirements can be written in assembly language and linked
with high-level code.

2.2.1

Instruction Set

The 80C 186 Modular Core family instructions treat different types of operands uniformly. Nearly
every instruction can operate on either byte or word data. Register, memory and immediate operands can be specified interchangeably in most instructions. Immediate values are exceptions: they
must serve as source operands and not destination operands. Memory variables can be manipulated (added to, subtracted from, shifted, compared) without being moved into and out of registers. This saves instructions, registers and execution time in assembly language programs. In
high-level languages, where most variables are memory-based, compilers can produce faster and
shorter object programs.
The 80C186 Modular Core family instruction set can be viewed as existing on two levels. One is
the assembly level and the other is the machine level. To the assembly language programmer, the
80C186 Modular Core family appears to have about 100 instructions. One MOV (data move) instruction, for example, transfers a byte or a word from a register, a memory location or an immediate value to either a register or a memory location. The 80C186 Modular Core family CPUs,
however, recognize 28 different machine versions of the MOV instruction.
The two levels of instruction sets address two requirements: efficiency and simplicity. Approximately 300 forms of machine-level instructions make very efficient use of storage. For example,
the machine instruction that increments a memory operand is three or four bytes long because the
address of the operand must be encoded in the instruction. Incrementing a register, however, requires less information, so the instruction can be shorter. The 80C186 Core family has eight single-byte machine-level instructions that increment different 16-bit registers.
The assembly level instructions simplify the programmer's view of the instruction set. The programmer writes one form of an INC (increment) instruction and the assembler examines the operand to determine which machine level instruction to generate. The following paragraphs
provide a functional description of the assembly-level instructions.

2-17

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

2.2.1.1

intet

Data Transfer Instructions

The instruction set contains 14 data transfer instructions. These instructions move single bytes
and words between memory and registers. They also move single bytes and words between the
AL or AX register and 110 ports. Table 2-3 lists the four types of data transfer instructions and
their functions.
Table 2-3. Data Transfer Instructions
General-Purpose
MOV

Move byte or word

PUSH

Push word onto stack

POP

Pop word off stack

PUSHA

Push registers onto stack

POPA

Pop registers off stack

XCHG

Exchange byte or word

XLAT

Translate byte
Input/Output

Input byte or word

OUT

Output byte or word
Address Object and Stack Frame

LEA

Load effective address

LOS

Load pOinter using OS

LES

Load pOinter using ES

ENTER

Build stack frame

LEAVE

Tear down stack frame
Flag Transfer

LAHF

Load AH register from flags

SAHF

Store AH register in flags

PUSHF

Push flags from stack

POPF

Pop flags off stack

Data transfer instructions are categorized as general purpose, input/output, address object and
flag transfer. The stack manipulation instructions, used for transferring flag contents and instructions used for loading segment registers are also included in this group. Figure 2-11 shows the
flag storage formats. The address object instructions manipulate the addresses of variables instead of the values of the variables.

2-18

int:et

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

LAHF S,Z,U,A,U,P,U,C
SAHF
7 6 5 4 321 0

U = Undefined; Value is indeterminate

o = Overflow Flag

D = Direction Flag
I = Interrupt Enable Flag
T=Trap Flag
S = Sign Flag
Z = Zero Flag
A = Auxiliary Carry Flag
P = Parity Flag
C = Carry Flag
A1014-0A

Figure 2-11. Flag Storage Format
2.2.1.2

Arithmetic Instructions

The arithmetic instructions (see Table 2-4) operate on four types of numbers:
• Unsigned binary
• Signed binary (integers)
• Unsigned packed decimal
• Unsigned unpacked decimal

2-19

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Table 2-5 shows the interpretations of various bit patterns according to number type. Binary numbers can be 8 or 16 bits long. Decimal numbers are stored in bytes, two digits per byte for packed
decimal and one digit per byte for unpacked decimal. The processor assumes that the operands in
arithmetic instructions contain data that represents valid numbers for that instruction. Invalid data
may produce unpredictable results. The Execution Unit analyzes the results of arithmetic instructions and adjusts status flags accordingly.
Table 2-4. Arithmetic Instructions
Addition
ADD

Add byte or word

ADC

Add byte or word with carry

INC

Increment byte or word by 1

AAA

ASCII adjust for addition

DAA

Decimal adjust for addition
Subtraction

SUB

Subtract byte or word

SBB

Subtract byte or word with borrow

DEC

Decrement byte or word by 1

NEG

Negate byte or word

CMP

Compare byte or word

AAS

ASCII adjust for subtraction

DAS

Decimal adjust for subtraction
Multiplication

MUL

Multiply byte or word unsigned

IMUL

Integer multiply byte or word

AAM

ASCII adjust for multiplication
Division

2-20

DIV

Divide byte or word unsigned

IDIV

Integer divide byte or word

AAD

ASCII adjust for division

CBW

Convert byte to word

CWD

Convert word to double-word

intet

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Table 2-5. Arithmetic Interpretation of 8-Bit Numbers

2.2.1.3

Unsigned
Binary

Signed
Binary

Unpacked
Decimal

Packed
Decimal

Hex

Bit Pattern

00000111

10001001

137

-119

invalid

11000101

197

-59

invalid

Bit Manipulation Instructions

There are three groups of instructions for manipulating bits within bytes and words. These three
groups are logical, shifts and rotates. Table 2-6 lists the bit manipulation instructions and their
functions.
Table 2-6. Bit Manipulation Instructions
Logicals
NOT

"Not" byte or word

AND

"And" byte or word

"Inclusive or" byte or word

XOR

"Exclusive or" byte or word

TEST

''Test'' byte or word
Shifts

SHUSAL

Shift logical/arithmetic left byte or word

SHR

Shift logical right byte or word

SAR

Shift arithmetic right byte or word
Rotates

ROL

Rotate left byte or word

ROR

Rotate right byte or word

RCL

Rotate through carry left byte or word

RCR

Rotate through carry right byte or word

Logical instructions include the Boolean operators NOT, AND, OR and exclusive OR (XOR), as
well as a TEST instruction. The TEST instruction sets the flags as a result of a Boolean AND operation but does not alter either of its operands.
Individual bits in bytes and words can be shifted either arithmetically or logically. Up to 32 shifts
can be performed, according to the value of the count operand coded in the instruction. The count
can be specified as an immediate value or as a variable in the CL register. This allows the shift
count to be a supplied at execution time. Arithmetic shifts can be used to multiply and divide binary numbers by powers of two. Logical shifts can be used to isolate bits in bytes or words.

2-21

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

intel·

Individual bits in bytes and words can also be rotated. The processor does not discard the bits rotated out of an operand. The bits circle back to the other end of the operand. The number of bits
to be rotated is taken from the count operand, which can specify either an immediate value or the
CL register. The carry flag can act as an extension of the operand in two of the rotate instructions.
This allows a bit to be isolated in the Carry Flag (CF) and then tested by a IC (jump if carry) or
JNC (jump if not carry) instruction.
2.2.1.4

String Instructions

Five basic string operations process strings of bytes or words, one element (byte or word) at a
time. Strings of up to 64 Kbytes can be manipulated with these instructions. Instructions are available to move, compare or scan for a value, as well as to move string elements to and from the
accumulator. Table 2-7 lists the string instructions. These basic operations can be preceded by a
one-byte prefix that causes the instruction to be repeated by the hardware, allowing long strings
to be processed much faster than is possible with a software loop. The repetitions can be terminated by a variety of conditions. Repeated operations can be interrupted and resumed.
Table 2-7. String Instructions
REP

Repeat

REPElREPZ

Repeat while equaVzero

REPNElREPNZ

Repeat while not equaVnot zero

MOVSBIMOVSW

Move byte string/word string

MOVS

Move byte or word string

INS

Input byte or word string

OUTS

Output byte or word string

CMPS

Compare byte or word string

SCAS

Scan byte or word string

LODS

Load byte or word string

STOS

Store byte or word string

String instructions operate similarly in many respects (see Table 2-8). A string instruction can·
have a source operand, a destination operand, or both. The hardware assumes that a source string
resides in the current data segment. A segment prefix can override this assumption. A destination
string must be in the current extra segment. The assembler does not use the operand names to address strings. Instead, the contents of the Source Index (SI) register are used as an offset to address
the current element of the source string. The contents of the Destination Index (01) register are
taken as the offset of the current destination string element. These registers must be initialized to
point to the source and destination strings before executing the string instructions. The LOS, LES
and LEA instructions are useful in performing this function.

2-22

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

String instructions automatically update the SI register, the DI register, or both, before processing
the next string element. The Direction Flag (DF) determines whether the index registers are autoincremented (DF = 0) or auto-decremented (DF = I). The processor adjusts the DI, SI, or both
registers by one for byte strings or by two for word strings.

If a repeat prefix is used, the count register (CX) is decremented by one after each repetition of·
the string instruction. The CX register must be initialized to the number of repetitions before the
string instruction is executed. If the CX register is 0, the string instruction is not executed and
control goes to the following instruction.
Table 2-8. String Instruction Register and Flag Use
SI

Index (offset) for source string

Index (offset) for destination string

Repetition counter

AUAX

Scan value
Destination for LODS
Source for STOS

Direction Flag
0= auto-increment SI, 01
1 = auto-decrement SI, 01

2.2.1.5

Scan/compare terminator

Program Transfer Instructions

The contents of the Code Segment (CS) and Instruction Pointer (IP) registers determine the instruction execution sequence in the 8OCl86 Modular Core family. The CS register contains the
base address of the current code segment. The Instruction Pointer register points to the memory
location of the next instruction to be fetched. In most operating conditions, the next instruction
will already have been fetched and will be waiting in the CPU instruction queue. Program transfer
instructions operate on the IP and CS registers. Changing the contents of these registers causes
normal sequential operation to be altered. When a program transfer occurs, the queue no longer
contains the correct instruction. The Bus Interface Unit obtains the next instruction from memory
using the new IP and CS values. It then passes the instruction directly to the Execution Unit and
begins refilling the queue from the new loc~tion.
The 8OC186 Modular Core family offers four groups of program transfer instructions (see Table
2-9). These are unconditional transfers, conditional transfers, iteration control instructions and interrupt-related instructions.

2-23

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Unconditional transfer instructions can transfer control either to a target instruction within the
current code segment (intrasegment transfer) or to a different code segment (intersegment transfer). The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment transfer FAR. The transfer is made unconditionally when the instruction is executed. CALL, RET and
JMP are all unconditional transfers.
CALL is used to transfer the program to a procedure. A CALL can be NEAR or FAR. A NEAR
CALL stacks only the Instruction Pointer, while a FAR CALL stacks both the Instruction Pointer
and the Code Segment register. The RET instruction uses the information pushed onto the stack
to determine where to return when the procedure finishes. Note that the RET and CALL instructions must be the same type. This can be a problem when the CALL and RET instructions are in
separately assembled programs. The JMP instruction does not push any information onto the
stack. A JMP instruction can be NEAR or FAR.
Conditional transfer instructions are jumps that mayor may not transfer control, depending on
the state of the CPU flags when the instruction is executed. Each conditional transfer instruction
tests a different combination of flags for a condition (see Table 2-10). If the condition is logically
TRUE, control is transferred to the target specified in the instruction. If the condition is FALSE,
control passes to the instruction following the conditional jump. All conditional jumps are
SHORT. The target must be in the current code segment within -128 to +127 bytes of the next
instruction's first byte. For example, JMP OOH causes a jump to the first byte of the next instruction. Jumps are made by adding the relative displacement of the target to the Instruction Pointer.
All conditional jumps are self-relative and are appropriate for position-independent routines.

2-24

int"et

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Table 2-9. Program Transfer Instructions
Conditional Transfers
JAlJNBE

Jump if above/not below nor equal

JAE/JNB

Jump if above or equal/not below

JB/JNAE

Jump if below/not above nor equal

JBE/JNA

Jump if below or equaVnot above

Jump if carry

JElJZ

Jump if equal/zero

JG/JNLE

Jump if greater/not less nor equal

JGElJNL

Jump if greater or equal/not less

JUJNGE

Jump if less/not greater nor equal

JLE/JNG

Jump if less or equaVnot greater

JNC

Jump if not carry

JNElJNZ

Jump if not equaVnot zero

JNO

Jump if not overflow

JNP/JPO

Jump if not parity/parity odd

JNS

Jump if not sign

Jump if overflow

JP/JPE

Jump if parity/parity even

Jump if sign
Unconditional Transfers

CALL

Call procedure

RET

Return from procedure

JMP

Jump
Iteration Control

LOOP

Loop

LOOPEILOOPZ

Loop if equal/zero

LOOPNEILOOPNZ

Loop if not equaVnot zero

JCXZ

Jump if register CX=O
Interrupts

INT

Interrupt

INTO

Interrupt if overflow

BOUND

Interrupt if out of array bounds

IRET

Interrupt return

2-25

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Iteration control instructions can be used to regulate the repetition of software loops. These instructions use the ex register as a counter. Like the conditional transfers, the iteration control instructions are self-relative and can transfer only to targets that are within -128 to +127 bytes of
themselves. They are SHORT transfers.
The interrupt instructions allow programs and external hardware devices to activate interrupt service routines. The effect of a software interrupt is similar to that of a hardware-initiated interrupt.
The processor cannot execute an interrupt acknowledge bus cycle if the interrupt originates in
software or with an NMI (Non-Maskable Interrupt).
Table 2-10. Interpretation of Conditional Transfers
Mnemonic

Condition Tested

"Jump if ••• "

JAlJNBE

(CF orZF)=O

above/not below nor equal

JAElJNB

CF=O

above or equal/not below

JB/JNAE

CF=1

below/not above nor equal

JBElJNA

(CF or ZF)=1

below or equal/not above

CF=1

carry

JElJZ

ZF=1

equal/zero

JG/JNLE

«SF xor OF) or ZF)=O

greater/not less nor equal

JGElJNL

(SF xor OF)=O

greliter or equal/not less

JLlJNGE

(SF xor OF)=1

less/not greater nor equal

JLE/JNG

«SF xor OF) or ZF)=1

less or equal/not greater

JNC

CF=O

not carry

JNElJNZ

ZF=O

not equal/not zero

JNO

OF=O

not overflow

JNP/JPO

PF=O

not parity/parity odd

JNS

SF=O

not sign

OF=1

overflow

JP/JPE

PF=1

parity/parity equal

SF=1

sign

NOTE: The terms above and below refer to the relationship of two unsigned values;
greater and less refer to the relationship of two signed values.

2-26

intet~
2.2.1.6

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Processor Control Instructions

Processor control instructions (see Table 2-11) allow programs to control various CPU functions.
Seven of these instructions update flags, four of them are used to synchronize the microprocessor
with external events, and the remaining instruction causes the CPU to do nothing. Except for flag
operations, processor control instructions do not affect the flags.
Table 2-11. Processor Control Instructions
Flag Operations
STC

Set Carry flag

CLC

Clear Carry flag

CMC

Complement Carry flag

STD

Set Direction flag

CLD

Clear Direction flag

STI

Set Interrupt Enable flag

CLI

Clear Interrupt Enable flag
External Synchronization

HLT

Halt until interrupt or reset

WAIT

Wait for TEST pin active

ESC

Escape to external processor

LOCK

Lock bus during next instruction
No Operation

NOP

2.2.2

No operation

Addressing Modes

The 80C186 Modular Core family members access instruction operands in several ways. Operands can be contained either in registers, in the instruction itself, in memory or at I/O ports. Addresses of memory and I/O port operands can be calculated in many ways. These addressing
modes greatly extend the flexibility and convenience of the instruction set. The following paragraphs briefly describe register and immediate modes of operand addressing. A detailed description of the memory and I/O addressing modes is also provided.
2.2.2.1

Usually, the fastest, most compact operand addressing forms specify only register operands. This
is because the register operand addresses are encoded in instructions in just a few bits and no bus
cycles are run (the operation occurs within the CPU). Registers can serve as source operands, destination operands, or both.

2-27

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

intet~

Immediate operands are constant data contained in an instruction. Immediate data can be either
8 or 16 bits in length. Immediate operands are available directly from the instruction queue and
can be accessed quickly. As with a register operand, no bus cycles need to be run to get an immediate operand. Immediate operands can be only source operands and must have a constant value.

2.2.2.2

Memory Addressing Modes

Although the Execution Unit has direct access to register and immediate operands, memory operands must be transferred to and from the CPU over the bus. When the Execution Unit needs to
read or write a memory operand, it must pass an offset value to the Bus Interface Unit. The Bus
Interface Unit adds the offset to the shifted contents of a segment register, producing a 20-bit
physical address. One or more bus cycles are then run to access the operand.
The offset that the Execution Unit calculates for memory operand is called the operand's Effective Address (EA). This address is an unsigned 16-bit number that expresses the operand's distance, in bytes, from the beginning of the segment in which it resides. The Execution Unit can
calculate the effective address in several ways. Information encoded in the second byte of the instruction tells the Execution Unit how to calculate the effective address of each memory operand.
A compiler or assembler derives this information from the instruction written by the programmer.
Assembly language programmers have access to all addressing modes.
The Execution Unit calculates the Effective Address by summing a displacement, the contents of
a base register and the contents of an index register (see Figure 2-12). Any combination of these
can be present in a given instruction. This allows a variety of memory addressing modes.

2-28

int"et

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Single Index

Double Index

Encoded
in the
Instruction

Explicit
in the
Instruction

.-------~----.

Displacement

1
1______ - - - - - '

Assumed Unless
Overridden
by Prefix

Effective
Address

BIU

Physical Addr
Al015-0A

Figure 2-12. Memory Address Computation

The displacement is an 8- or 16-bit number contained in the instruction. The displacement generally is derived from the position of the operand's name (a variable or label) in the program. The
programmer can modify this value or explicitly specify the displacement.

2-29

intet,

OVERVIEW OF THE 8OC186 FAMILY ARCHITECTURE

The BX or BP register can be specified as the base register for an effective address calculation.
Similarly, either the SI or the DI register can be specified as the index register. The displacement
value is a constant. The contents of the base and index registers can change during execution. This
allows one instruction to access different memory locations depending upon the current values in
the base or base and index registers. The default base register for effective address calculations
with the BP register is SS, although DS or ES can be specified.
Direct addressing is the simplest memory addressing mode (see Figure 2-13). No registers are involved, and the effective address is taken directly from the displacement of the instruction. Programmers typically use direct addressing to access scalar variables,
With register indirect addressing, the effective address of a memory operand can be taken directly
from one of the base or index registers (see Figure 2-14). One instruction can operate on various
memory locations if the base or index register is updated accordingly. Any 16-bit general register
can be used for register indirect addressing with the lMP or CALL instructions.
In based addressing, the effective address is the sum of a displacement value and the contents of
the BX or BP register (see Figure 2-15). Specifying the BP register as a base register directs the
Bus Interface Unit to obtain the operand from the current stack segment (unless a segment override prefix is present). This makes based addressing with the BP register a convenient way to access stack data.

I~--------~----------~----------r---------~
Opcode I Mod RIM I
Displacement
r---------~--------~~--------_r---------~

I
Al016-0A

Figure 2-13. Direct Addressing

2-30

in1et

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Opcode

Mod RIM

BX
or

BP
or
SI
or

Al017-0A

Figure 2-14. Register Indirect Addressing

Opcode

--------- ..

I Mod RIM I

I
Displacement
I
- - - - ______ 1

I
BX

BP
It

I
Al018-0A

Figure 2-15. Based Addressing

Based addressing provides a simple way to address data structures that may be located in different
places in memory (see Figure 2-16). A base register can be pointed at the structure. Elements of
the structure can then be addressed by their displacements. Different copies of the same structure
can be accessed by simply changing the base register.

2-31

OVERVIEW OF THE 80C186 FAMILV ARCHITECTURE

Displacement

High Address
Age

Displacement

Status
Rate

I-I
I
I
I
I
I
I
I

II
I
I
I

Vac

Sick

Dept

Div

Employee

~----------------~

Age

Vac

Sick

Dept

Div

Employee
Low Address
A1019-0A

Figure 2-16. Accessing a Structure with Based Addressing

With indexed addressing, the effective address is calculated by summing a displacement and the
contents of an index register (SI or DI, see Figure 2-17). Indexed addressing is often used to access elements in an array (see Figure 2-18). The displacement locates the beginning of the array,
and the value of the index register selects one element. If the index register contains OOOOH, the
processor selects the first element. Since all array elements are the same length, simple arithmetic
on the register can select any element.

2-32

intet

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Opcode

----------

I Mod RIM I

Displacement
I
- - - - ______ 1

I
SI
or
DI

Al020-0A

Figure 2-17. Indexed Addressing

High Address

Array (8)
Array (7)
Array (6)
Array (5)
Index Register

Array (4)

Index Register

Array (3)

Array (2)
Array (1)
Array (0)

1 Word
Low Address
Al021-0A

Figure 2-18. Accessing an Array with Indexed Addressing

2-33

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Based index addressing generates an effective address that is the sum of a base register, an index
register and a displacement (see Figure 2-19). The two address components can be determined at
execution time, making this a very flexible addressing mode.

Opcode

--------

I Mod RIM I

Displacement

---------

BX
or
BP

I
I
_I

SI
or
DI

I
A1022·OA

Figure 2-19. Based Index Addressing

Based index addressing provides a convenient way for a procedure to address an array located on
a stack (see Figure 2-20). The BP register can contain the offset of a reference point on the stack.
This is typically the top of the stack after the procedure has saved registers and allocated local
storage. The offset of the beginning of the array from the reference point can be expressed by a
displacement value. The index register can be used to access individual array elements. Arrays
contained in structures and matrices (two-dimensional arrays) can also be accessed with based
indexed addressing.
String instructions do not use normal memory addressing modes to access operands. Instead, the
index registers are used implicitly (see Figure 2-21). When a string instruction executes, the SI
register must point to the first byte or word of the source string, and the 01 register must point to
the first byte or word of the destination string. In a repeated string operation, the CPU will automatically adjust the SI and 01 registers to obtain subsequent bytes or words. For string instructions, the OS register is the default segment register for the SI register and the ES register is the
default segment register for the 01 register. This allows string instructions to operate on data located anywhere within the 1 Mbyte address space.

2-34

in1et

OVERVIEW OF THE 80C186 FAMILV ARCHITECTURE

High Address

Displacement

Parm2

Displacement

Parm 1
IP
Old BP
OldBX
Old AX
Array (6)
Index Register

Array (5)

Array (4)
Array (3)
Array (2)
Array (1)
----.--

Array (0)

----.--

Cou~

~r---------~

--------------~

________________ J_

Temp
Status

~-------------rJ

l _____________ J

~1word~
Low Address
A1024-0A

Figure 2-20. Accessing a Stacked Array with Based Index Addressing

2-35

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Opcode

~__S_I__Ji----~-~I___s_ou_~_ce__EA
__~

Destination EA
A1025-0A

Figure 2·21. String Operand
2.2.2.3

110 Port Addressing

Any memory operand addressing modes can be used to access an 110 port if the port is memorymapped. String instructions can also be used to transfer data to memory-mapped ports with an
appropriate hardware interface.
Two addressing modes.can be used to access ports located in the 110 space (see Figure 2-22). For
direct 110 port addressing, the port number is an 8-bit immediate operand. This allows fixed access to ports numbered 0 to 255. Indirect 110 port addressing is similar to register indirect addressing of memory operands. The OX register contains the port number, which can range from 0 to
65,535. Adjusting the contents of the OX register allows one instruction to access any port in the
I/O space. A group of adjacent ports can be accessed using a simple software loop that adjusts the
value of the OX register.

Port Address

Direct Port
Addressing

Indirect Port
Addressing

Port Address

A1026-0A

Figure 2·22. 110 Port Addressing

2-36

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

2.2.2.4

Data Types Used in the 80C186 Modular Core Family

The 80C186 Modular Core family supports the data types described in Table 2-12 and illustrated
in Figure 2-23. In general, individual data elements must fit within defined segment limits.
Table 2·12. Supported Data Types
Type
Integer

Description
A signed 8- or 16-bit binary numeric value (signed byte or word). All operations assume
a 2's complement representation.
The 80C18? numerics processor extension, when added to an 80C186 Modular Core
system, directly supports signed 32- and 64-bit integers (signed double-words and
quad-words). The 80C188 Modular Core does not support the 80C18?

Ordinal

An unsigned 8- or 16-bit binary numeric value (unsigned byte or word).

BCD

A byte (unpacked) representation of a single decimal digit (0-9).

ASCII

A byte representation of alphanumeric and control characters using the ASCII
standard.

Packed BCD

A byte (packed) representation of two decimal digits (0-9).One digit is stored in each
nibble (4 bits) of the byte.

String

A contiguous sequence of bytes or words. A string can contain from 1 byte to 64
Kbytes.

Pointer

A 16- or 32-bit quantity. A 16-bit pointer consists of a 16-bit offset component; a 32-bit
pointer consists of the combination of a 16-bit base component (selector) plus a 16-bit
offset component.

Floating Point

A signed 32-, 64-, or 80-bit real number representation.
The 80C18? numerics processor extension, when added to an 80C186 Modular Core
system, directly supports floating point operands. The 80C188 Modular Core does not
support the 80C18?

2-37

OVE;RVIEW OF THE SOC186 FAMILY ARCHITECTURE

Signed Byte

Iii iii iii

Unsigned Byte

Sign Bit .J L. Magnitude--.J
1514 +1
Signed Word II iii
Sign Bit .J L.MSB

2423

1615

Sign Bit .J IL.MSB
Signed Quad
Word"

L.MSB

+1
Unsigned 15 i i I
Ii
Word
I L.MSB

iii Ii iii i

L- Magnitude--.J

t.=.:.::..::.:: Magmtude---..J

Signed Double
Word"

Magnitude

i i i87 i
I
0

Magnitude

63+7

+6 4847 +5

+4 3231 +3

+2 1615 +1

Sign Bit .J 'IL.MSB
---------Magnltude----------'
7

Binary Coded
Decimal (BCD)

BCD Digit Ii

ASCII

iii

•••

Iii iii iii
+n

•••

L---...I

Iii iii iii

31
Iii

o
iii iii oI
L---...I

•••

ByteWord n

POinter

Least
Significant Digit

iii Iii i I
+3

BCD Digit 0

Most
Significant Digit
String

o
i

ASCII Character 1 ASCII Character 0

I •••

o
iii

Iii iii iii iii Iii i I

Iii iii

BCD Digit 1

ASCII Character n
Packed BCD

7
Iii
iii

2423

iii

o
o
iii iii

Byte Word 1

Byte Word 0

1615

I
I
I
I
Selector· - - - - " - - - - - O f f s e t - - - -....I
I

I I

Iii

+5
+4
+3
+2
+1
+0 0
Floating Ir=.-I--.---.----,---.---.--,.----,.---,----,r--'I
Point" . .
.
79 +9

Sign Bit .J L-Exponent--.......- - - - - - - - M a g n i t u d e - - - - - - - - - '
NOTE: 'Directly supported if the system contains an 80C187.
Al027-0B

Figure 2-23. 80C186 Modular Core Family Supported Data Types

2-38

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

2.3

INTERRUPTS AND EXCEPTION HANDLING

Interrupts and exceptions alter program execution in response to an external event or an error
condition. An interrupt handles asynchronous external events, for example an NMI. Exceptions
result directly from the execution of an instruction, usually an instruction fault. The user can
cause a software interrupt by executing an "INTn" instruction. The CPU processes software interrupts il! the same way that it handles exceptions.
The 8OC186 Modular Core responds to interrupts and exceptions in the same way for all devices
within the 80C 186 Modular Core family. However, devices-within the family may have different
Interrupt Control Units. The Interrupt Control Unit handles all external interrupt sources and presents them to the 80C186 Modular Core via one maskable interrupt request (see Figure 2-24).
This discussion covers only those areas of interrupts and exceptions that are common to the
80C 186 Modular Core family. The Interrupt Control Unit is proliferation-dependent; see Chapter
8, "Interrupt Control Unit," for additional information.

NMI
Maskable
Interrupt
Request
Interrupt
Control
Unit

CPU

External
Interrupt
Sources

Interrupt
Acknowledge ~
Al028-0A.

Figure 2-24. Interrupt Control Unit

2.3.1

Interrupt/Exception Processing

The 80C 186 Modular Core can service up to 256 different interrupts and exceptions. A 256-entry
Interrupt Vector Table (Figure 2-25) contains the pointers to interrupt service routines. Each entry
consists of four bytes, which contain the Code Segment (CS) and Instruction Pointer (IP) of the
first instruction in the interrupt service routine. Each interrupt or exception is given a type number, 0 through 255, corresponding to its position in the Interrupt Vector Table. Note that interrupt
types 0-31 are reserved for Intel and should not be used by an application program.

2-39

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Memory
Address

3FE
3FC

Table
Entry

Vector
Definition

CS
IP

··

Memory
Address

25~

2E
Type
2C
User
,
2A
Available 28
•
26
24
~.
22
Type 31
20
:
Reserved 1E
,
1C
•
1A
.. Type 22
18
6
Type 21
14
-Serial 0 Trans
12
Type 20
10
c
I~ - Serial 0
OE
Type 1 - Timer 2
OC
I~
OA
pe 18 - Timer 1
08
~
06
Type 17 -INT4
04
i~
02
Type 16 - Numerics
00
I~ (80C186EB only)

CS
IP
CS
IP
CS
IP
CS

82ml
·

IP
CS
IP

80
7E
7C

·.
I

sA 52
~

CS
IP

<6E)

5t..e:
5'f ..e
S2-4A5b ...a
.E..a
'Ie 44

cs
IP
CS
IP

'114<10£

liT;

tll1ee
JIll ee

qz.
lit)
3E

CS/

as
ae

!P'

3"
33'

I....

/CS
IP
CS
IP
2 Bytes

Type 15 - INT3

V'-,/

Table
Entry

IP/

III(

/IP
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
2 Bytes

Definiti~~

FY~Z.

...

.,.~

1/ rze 9-11 - Reserved

Type 8 - Timer 0

I.
Type 7 - ESC Opcode

I.
Type 6 - Unused

I~ Opcode
.. Type 5 - Array
I~ Bounds
.. Type 4 - Overflow
I~
.. Type 3 - Breakpoint
I~
"Type 2 - NMI

I.. Type 1 - Single-Step
.~

~ Type 0 - Divide Error
..1

-I

Type 14 - INT2
~

-I

CS =Code Segment Value
IP = Instruction Pointer Value
A101D-01

($1iF 7/11/15 ~).1!j~~ )

Figure 2-25. Interrupt Vector Table

(

When an interrupt is acknowledged, a common event sequence (Figure 2-26) allows the processor to execute the interrupt service routine.

2-40

The processor saves a partial machine status by pushing the Processor Status Word onto
the stack.

in1et

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

The Trap Flag bit and Interrupt Enable bit are cleared in the Processor Status Word. This
prevents maskable interrupts or single step exceptions from interrupting the processor
during the interrupt service routine.

The current CS and IP are pushed onto the stack.

The CPU fetches the new CS and IP for the interrupt vector routine from the Interrupt
Vector Table and begins executing from that point.

The CPU is now executing the interrupt service routine. The programmer must save (usually by
pushing onto the stack) all registers used in the interrupt service routine; otherwise, their contents
will be lost. To allow nesting of maskable interrupts, the programmer must set the Interrupt Enable bit in the Processor Status Word.
When exiting an interrupt service routine, the programmer must restore (usually by popping off
the stack) the saved registers and execute an IRET instruction, which performs the following
steps.
1.

Loads the return CS and IP by popping them off the stack.

Pops and restores the old Processor Status Word from the stack.

The CPU now executes from the point at which the interrupt or exception occurred.

2-41

intet~

OVERVIEW OF THE 8OC186 FAMILY ARCHITECTURE

Stack

...-----...,

Interrupt Enable Bit
Trap Flag

PSW
CS

Processor Status Word

IP
Code Segment Register
~------~

Instruction Pointer

CS
IP
Interrupt
Vector
Table
A1029-0A

Figure 2-26. Interrupt Sequence

2.3.1.1

Non-Maskable Interrupts

The Non-Maskable Interrupt (NMI) is the highest priority interrupt. It is usually reserved for a
catastrophic event such as impending power failure. An NMI cannot be prevented (or masked)
by software. When the NMI input is asserted, the interrupt processing sequence begins after execution of the current instruction completes (see "Interrupt Latency" on page 2-45). The CPU au•
tomatically generates a type 2 interrupt vector.
The NMI input is asynchronous. Setup and hold times are given only to guarantee recognition on
a specific clock edge. To be recognized, NMI must be asserted for at least one CLKOUT period
and meet the correct setup and hold times. NMI is edge-triggered and level-latched. Multiple
NMI requests cause multiple NMI service routines to be executed. NMI can be nested in this manner an infinite number of times.

2-42

intet
2.3.1.2

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Maskable Interrupts

Maskable interrupts are the most common way to service external hardware interrupts. Software
can globally enable or disable maskable interrupts. This is done by setting or clearing the Interrupt Enable bit in the Processor Status Word.
The Interrupt Control Unit processes the multiple sources of maskable interrupts and presents
them to the core via a single maskable interrupt input. The Interrupt Control Unit provides the
interrupt vector type to the 80CI86 Modular Core. The Interrupt Control Unit differs among
members of the 80CI86 Modular Core family; see Chapter 8, "Interrupt Control Unit," for information.
2.3.1.3

Exceptions

Exceptions occur when an unusual condition prevents further instruction processing until the exception is corrected. The CPU handles software interrupts and exceptions in the same way. The
interrupt type for an exception is either predefined or supplied by the instruction.
Exceptions are classified as either faults or traps, depending on when the exception is detected
and whether the instruction that caused the exception can be restarted. Faults are detected and serviced before the faulting instruction can be executed. The return address pushed onto the stack
in the interrupt processing instruction points to the beginning of the faulting instruction. This allows the instruction to be restarted. Traps are detected and serviced immediately after the instruction that caused the trap. The return address pushed onto the stack during the interrupt processing
points to the instruction following the trapping instruction.
Divide Error - Type 0
A Divide Error trap is invoked when the quotient of an attempted division exceeds the maximum
value of the destination. A divide-by-zero is a common example.
Single Step - Type 1
The Single Step trap occurs after the CPU executes one instruction with the Trap Flag (TF) bit set
in the Processor Status Word. This allows programs to execute one instruction at a time. Interrupts
are not generated after prefix instructions (e.g., REP), after instructions that modify segment registers (e.g., POP DS) or after the WAIT instruction. Vectoring to the single-step interrupt service
routine clears the Trap Flag bit. An IRET instruction in the interrupt service routine restores the
Trap Flag bit to logic "I" and transfers control to the next instruction to be single-stepped.

2-43

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Breakpoint Interrupt -1)rpe 3
The Breakpoint Interrupt is a single-byte version of the INT instruction. It is commonly used by
software debuggers to set breakpoints in RAM. Because the instruction is only one byte long, it
can substitute for any instruction.

Interrupt on Overflow -1)rpe 4
The Interrupt on Overflow trap occurs if the Overflow Flag (OF) bit is set in the Processor Status
Word and the INTO instruction is executed. Interrupt on Overflow is a common method for handling arithmetic overflows conditionally.

Array Bounds Check -1)rpe 5
An Array Bounds trap occurs when the array index is outside the array bounds during execution
of the BOUND instruction (see Appendix A, "80C186 Instruction Set Additions and Extensions").

Invalid Opcode -1)rpe 6
Execution of an undefined opcode causes an Invalid Opcode trap.

Escape Opcode -1)rpe 7
The Escape Opcode fault is used for floating point emulation. With 80C 186 Modular Core family
members, this fault is enabled by setting the Escape Trap (ET) bit in the Relocation Register (see
Chapter 4, "Peripheral Control Block"). When a floating point instruction is executed with the
Escape Trap bit set, the Escape Opcode fault occurs, and the Escape Opcode service routine emulates the floating point instruction. If the Escape Trap bit is cleared, the CPU sends the floating
point instruction to an external8OCl87.
8OC188 Modular Core Family members do not support the 8OC187 interface and always generate
the Escape Opcode Fault.

Numerics Coprocessor Fault -1)rpe 16
The Numerics Coprocessor fault is caused by an external 80C187 numerics coprocessor. The
80C187 reports the exception by asserting the ERROR pin. The 8OC186 Modular Core checks
the ERROR pin only when executing a numerics instruction. A Numerics Coprocessor Fault indicates that the previous numerics instruction caused the exception. The 80C187 saves the address of the floating point instruction that caused the exception. The return address pushed onto
the stack during the interrupt processing points to the numerics instruction that detected the exception. This way, the last numerics instruction can be restarted.

2-44

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

2.3.2

Software Interrupts

A Software Interrupt is caused by executing an "INTn" instruction. The n parameter corresponds
to the specific interrupt type to be executed. The interrupt type can be any number between 0 and
255. If the n parameter corresponds to an interrupt type associated with a hardware interrupt
(NMI, Timers), the vectors are fetched and the routine is executed, but the corresponding bits in
the Interrupt Status register are not altered.
The CPU processes software interrupts and exceptions in the same way. Software interrupts, exceptions and traps cannot be masked.

2.3.3

Interrupt Latency

Interrupt latency is the amount of time it takes for the CPU to recognize the existence of an interrupt. The CPU generally recognizes interrupts only between instructions or on instruction boundaries. Therefore, the current instruction must finish executing before an interrupt can be
recognized.
The worst-case 8OC186 instruction execution time is an integer divide instruction with segment
override prefix. The instruction takes 69 clocks, assuming an 80C 186 Modular Core family member and a zero wait-state external bus. The execution time for an 80C188 Modular Core family
member may be longer, depending on the queue.
This is one factor in determining interrupt latency. In addition, the following are also factors in
determining maximum latency:
1.

The CPU does not recognize the Maskable Interrupt unless the Interrupt Enable bit is set.

The CPU does not recognize interrupts during HOLD.

Once communication is completely established with an 80C187, the CPU does not
recognize interrupts until the numerics instruction is finished.

The CPU can recognize interrupts only on valid instruction boundaries. A valid instruction
boundary usually occurs when the current instruction finishes. The following is a list of exceptions:
1.

MOVs and POPs referencing a segment register delay the servicing of interrupts until
after the following instruction. The delay allows a 32-bit load to the SS and SP without an
interrupt occurring between the two loads.

The CPU allows interrupts between repeated string instructions. If multiple prefixes
precede a string instruction and the instruction is interrupted, only the one prefix
preceding the string primitive is restored.

The CPU can be interrupted during a WAIT instruction. The CPU will return to the WAIT
instruction.

2-45

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

2.3.4

Interrupt Response Time

Interrupt response time is the time from the CPU recognizing an interrupt until the first instruction
in the service routine is executed. Interrupt response time is less for interrupts or exceptions
which supply their own vector type. The maskable interrupt has a longer response time because
the vector type must be supplied by the Interrupt Control Unit (see Chapter 8, "Interrupt Control
Unit").
Figure 2-27 shows the events that dictate interrupt response time for the interrupts that supply
their type. Note that an on-chip bus master, such as the DRAM Refresh Unit, can make use of idle
bus cycles. This can increase interrupt response time.

Clocks
Idle

5
4
5

ReadlP
Idle
Read CS

4
4
4
3
4
4
5

Idle
Push Flags
Idle
Push CS
PushlP
Idle
First Instruction Fetch ......................................
From Interrupt Routine

Total 42
A1030-0A

Figure 2-27. Interrupt Response Factors

2.3.5

Interrupt and Exception Priority

Interrupts can be recognized only on valid instruction boundaries. If an NMI and a maskable interrupt are both recognized on the same instruction boundary, NMI has precedence. The maskable
interrupt will not be recognized until the Interrupt Enable bit is set and it is the highest priority.

2-46

intet

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Only the single step exception can occur concurrently with another exception. At most, two exceptions can occur at the same instruction boundary and one of those exceptions must be the single step. Single step is a special case; it is discussed on page 2-48. Ignoring single step (for now),
only one exception can occur at any given instruction boundary.
An exception has priority over both NMI and the maskable interrupt. However, a pending NMI
can interrupt the CPU at any valid instruction boundary. Therefore, NMI can interrupt an exception service routine. If an exception and NMI occur simultaneously, the exception vector is taken,
then is followed immediately by the NMI vector (see Figure 2-28). While the exception has higher priority at the instruction boundary, the NMI interrupt service routine is executed first.

F=1
NMI

Divide Error

Push PSW, CS, IP
Fetch Divide Error Vector

Push PSW, CS, IP
Fetch NMI Vector

Execute NMI
Service Routine

IRET
Execute Divide
Service Routine

IRET
A1031-0A

Figure 2-28. Simultaneous NMI and Exception

2-47

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Single step priority is a special case. If an interrupt (NMI or maskable) occurs at the same instruction boundary as a single step, the interrupt vector is taken first, then is followed immediately by
the single step vector. However, the single step service routine is executed before the interrupt
service routine (see Figure 2-29). If the single step service routine re-enables single step by executing the IRET, the interrupt service routine will also be single stepped. This can severely limit
the real-time response of the CPU to an interrupt.
To prevent the single-step routine from executing before a maskable interrupt, disable interrupts
while single stepping an instruction, then enable interrupts in the single step service routine. The
maskable interrupt is serviced from within the single step service routine and that interrupt service routine is not single-stepped. To prevent single stepping before an NMI, the single-step service routine must compare the return address on the stack to the NMI vector. If they are the same,
return to the NMI service routine immediately without executing the single step service routine.
NMI

Trap Flag

Instruction

Push PSW, CS, IP
Fetch Divide Error Vector
Trap Flag

Push PSW, CS, IP
Fetch Single Step Vector

Execute Single Step
Service Routine

•••••• Trap Flag

IRET

=???

Al032-0A

Figure 2-29. Simultaneous NMI and Single Step Interrupts

The most complicated case is when an NMI, a maskable interrupt, a single step and another exception are pending on the same instruction boundary. Figure 2-30 shows how this case is prioritized by the CPU. Note that if the single-step routine sets the Trap Flag (TF) bit before executing
the IRET instruction, the NMI routine will also be single stepped.
2-48

OVERVIEW OF THE 80C186 FAMILV ARCHITECTURE

Interrupt Enable Bit (IE)
Trap Flag (TF) = 1
NMI

Timer Interrupt

Interrupt Enable Bit (IE)
Trap Flag (TF) =0

Push PSW, CS, IP Interrupt Enable Bit (IE)
Fetch NMI Vector Trap Flag (TF) =0

Push PSW, CS, IP
Fetch Divide Error Vector

Push PSW, CS, IP
Interrupt Enable Bit (IE)
Fetch Single Step Vector Trap Flag (TF) =0

......

Execute Single Step
Service Routine
~-------'

IRET
Interrupt Enable Bit (IE) = 0
Trap Flag (TF) = ???

Interrupt Enable Bit (IE) = 1
Trap Flag (TF) = X

Push PSW, CS, IP
Fetch Single Step Vector

Interrupt Enable Bit (IE)
Trap Flag (TF) =X

Execute Single Step Service Routine
IRET
A1034-0A

Figure 2-30. Simultaneous NMI, Single Step and Maskable Interrupt

2-49

3
Bus Interface Unit

in1et
CHAPTER 3
BUS INTERFACE UNIT
The Bus Interface Unit (BIU) generates bus cycles that prefetch instructions from memory, pass
data to and from the execution unit, and pass data to and from the integrated peripheral units.
The BIU drives address, data, status and control information to define a bus cycle. The start of a
bus cycle presents the address of a memory or 110 location and status information defining the
type of bus cycle. Read or write control signals follow the address and define the direction of data
flow. A read cycle requires data to flow from the selected memory or 110 device to the BIU. In a
write cycle, the data flows from the BIU to the selected memory or 110 device. Upon termination
of the bus cycle, the BIU latches read data or removes write data.

3.1

MULTIPLEXED ADDRESS AND DATA BUS

The BIU has a combined address and data bus, commonly referred to as a time-multiplexed bus.
Time multiplexing address and data information makes the most efficient use of device package
pins. A system with address latching provided within the memory and 110 devices can directly
connect to the address/data bus (or local bus). The local bus can be demultiplexed with a single
set of address latches to provide non-multiplexed address and data information to the system.

3.2

ADDRESS AND DATA BUS CONCEPTS

The programmer views the memory or 110 address space as a sequence of bytes. Memory space
consists of 1 Mbyte, while 110 space consists of 64 Kbytes. Any byte can contain an 8-bit data
element, and any two consecutive bytes can contain a 16-bit data element (identified as a word).
The discussions in this section apply to both memory and 110 bus cycles. For brevity, memory
bus cycles are used for examples and illustration.

3.2.1

16-Bit Data Bus

The memory address space on a 16-bit data bus is physically implemented by dividing the address
space into two banks of up to 512 Kbytes each (see Figure 3-1). One bank connects to the lower
half of the data bus and contains even-addressed bytes (AO=O). The other bank connects to the
upper half of the data bus and contains odd-addressed bytes (AO=1). Address lines A19:1 select
a specific byte within each bank. AO and Byte High Enable (BHE) determine whether one bank
or both banks participate in the data transfer.

3-1

BUS INTERFACE UNIT

Physical Implementation
of the Address Space for
16-Bit Systems

Physical Implementation
of the Address Space for
8-Bit Systems

1 MByte

512 KBytes

FFFFF
FFFFE

FFFFF
FFFFO

FFFFE
FFFFC

2
1
0

'1'"

07:0

A19:1

....

A19:0

P-

-V

....

5
3
1

r:>

4
2
0

:...

AI.

1"-

'1'"

....

015:8

BHE

07:0

AO
AllO Tcw and Tow define the minimum data setup requirements. The value calculated by their respective equations
must be greater than the device req~irements. To increase the calculated value, insert wait states.

LA15:1
RD

--------1
1/01:8

AD7:0

1/01:8

AD15:8

t--+--aWE
t--+--aCS1
LAO
WR

SHE

L-....t----O

LCS ------_.-----aCS1
A1106-0A

Figure 3-22. 16-Bit Bus ReadIWrlte Device Interface

3-24

intet

BUS INTERFACE UNIT

The minimum device data hold time (from WR high) is defined by TDH' The calculated value
must be greater than the minimum device requirements; however, the value can be changed only
by decreasing the clock rate.
Table 3-5. Write Cycle Critical Timing Parameters
Memory Device
Parameter

Description

Equation

Twc

Write cycle time

TAW

Address valid to end of write strobe (WR high)

3T - TAOLTCH

Tcw

Chip enable (LCS) to end of write strobe (WR high)

TWR

Write recover time

TWHLH

Tow

Data valid to write strobe (WR high)

TOH

Data hold from write strobe (WR high)

TWHOX

Twp

Write pulse width

TWLWH

Twe and Twp define the minimum time (maximum frequency) a device can process write bus cycles. TWR determines the minimum time from the end of the current write cycle to the start of the
next write cycle. All three parameters require that calculated values be &:~~~t~r.than device requirements. The calculated Twe and Twp values increase with the insertion of wait states. The calculated TWR value, however, can be changed only by decreasing the clock rate.

3.5.3

Interrupt Acknowledge Bus Cycle

Interrupt expansion is accomplished by interfacing the Interrupt Control Unit with a peripheral
device such as the 82C59A Programmable Interrupt Controller. (See Chapter 8, "Interrupt Control Unit," for more information.) The BIU controls the bus cycles required to fetch vector information from the peripheral device, then passes the information to the CPU. These bus cycles,
collectively known as Interrupt Acknowledge bus cycles, operate similarly to read bus cycles.
However, instead of generating RD to enable the peripheral, the INTA signal is used. Figure 3-23
illustrates a typical Interrupt Acknowledge (or INTA) bus cycle.
An Interrupt Acknowledge bus cycle consists of two consecutive bus cycles. LOCK is generated
to indicate the sequential bus operation. The second bus cycle strobes vector information only
from the lower half ofthe bus (D7:0).In a 16-bit bus system, D15:13 contain cascade address information and D12:8 float. .

3-25

intet

BUS INTERFACE UNIT

CLKOUT
I
I

I
I

ALE

52:0

I
I
I
I
I
I

INTAO
INTA1
AD15:0
[AD7:0]
I
I

LOCK

i\
I
I

DT/R

II
I
I
I
I
I
I

DEN
A19:16
[A 15:8]
SHE

I
I
I
I
I
I
I
I
I
I
I

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

I
I
I
I
I
I
I
I
I
I
I

III
I

I
I
I
I
I
I
I
I
I
I

I
I
I
I
I
I
I
I
I

I
I
I
I

II
I
I
I
i

I
I
I
I
I
I
I
I
I
I
I

I
I
I

\1I

I
I
I
I

I
{
I

A15:8 are unknown
A19:16 are driven low

RD,WR

NOTE: Vector Type is read from AD7:0 only.
Al064-0A

Figure 3-23. Interrupt Acknowledge Bus Cycle

3-26

int:et

BUS INTERFACE UNIT

Figure 3-24 shows a typical 82C59A interface example. Bus ready must be provided to terminate
both bus cycles in the interrupt acknowledge sequence.
NOTE
Due to an internal condition, external ready is ignored if the device is
configured in Cascade mode and the Peripheral Control Block (PCB) is
located at OOOOH in JIG space. In this case, wait states cannot be added to
interrupt acknowledge bus cycles. However, you can add wait states to
interrupt acknowledge cycles if the PCB is located at any other address.
3.5.3.1

System Design Considerations

Although ALE is generated for both bus cycles, the BIU does not drive valid address information.
Actually, all address bits except A19:16 float during the time ALE becomes active (on both 8and 16-bit bus devices). Address-decoding circuitry must be disabled for Interrupt Acknowledge
bus cycles to prevent erroneous operation.

82C59A

Processor

INTO

14-----1

. -c----

INT

IRO
•

I~---

I----~~

GCSO

,
LA1~

/L--A

AD7:0

1~7\rWR
CS

D7:0

_111...---------'\1-

K~~---------------vr
A1065·0A

Figure 3-24. Typical 82C59A Interface

3-27

BUS INTERFACE UNIT

3.5.4

HALT Bus Cycle

Suspending the CPU reduces device power consumption and potentially reduces interrupt latency
time. The HLT instruction initiates two events:
l.

Suspends the Execution Unit.

Instructs the BIU to execute a HALT bus cycle.

The Idle or Powerdown power management mode (or the absence of both of them, known as Active Mode) affects the operation of the bus HALT cycle. The effects relating to BIU operation and
the HALT bus cycle are described in this chapter. Chapter 5, "Clock Generation and Power Man~
agement," discusses the concepts of Active, Idle and Powerdown power management modes.
After executing a HALT bus cycle, the BIU suspends operation until one of the following events
occurs:
• An interrupt is generated.
• A bus HOLD is generated (except when Powerdown mode is enabled).
• A refresh request is generated (except when Powerdown mode is enabled).
Figure 3-25 shows the operation of a HALT bus cycle. The address/data bus either floats or drives
during Tl, depending on the next bus cycle to be executed by the BIU. Under most instruction
sequences, the BIU floats the address/data bus because the next operation would most likely be
an instruction prefetch. However, if the HALT occurs just after a bus write operation, the address/data bus drives either data or address information during Tl. A19:16 continue to drive the
previous bus cycle information under most instruction sequences (otherwise, they drive the next
prefetch address). The BIU always operates in the same way for any given instruction sequence.
The Chip-Select Unit prevents a programmed chip-select from going active during a HALT bus
cycle. However, chip-selects generated by external decoder circuits must be disabled for HALT
bus cycles.

3-28

intelQt

BUS INTERFACE UNIT

After several TI bus states, all address/data, address/status and bus control pins drive to a known
state when Powerdown or Idle Mode is enabled. The address/data and address/status bus pins
force a low (0) state. Bus control pins force their inactive state. Figure 3-3 lists the state of each
pin after entering the HALT bus state.
Table 3-6. HALT Bus Cycle Pin States
Pin State
Pln(s)

.rm Powerdown
or Idle Mode

Powerdown
or Idle Mode

AD15:0 (AD7:0 for S·bit)

Float

Drive Zero

A15:S (S-bit)

Drive Address

Drive Zero

A19:16

Drive SH or Zero

Drive Zero

BHE (16-bit)

Drive Last Value

Drive One

RD, WR, DEN, DTIR, RFSH (S-blt), S2:0

Drive One

3-29

intel~

BUS INTERFACE UNIT

CLKOUT
ALE

52:0

\
011

AD1S:0
[AD7:0]

Note

[A1S:8]

Note

A19:16

SHE
[RF5H = 1]

NOTE: The AD15:0 [AD7:0] bus can be floating, driving a previous write data value,
or driving the next instruction prefetch address value. For an 8-bit device,
A15:8 either drives the previous bus address value or the next instruction
prefetch address value.
A1066-0A

Figure 3·25. HALT Bus Cycle

3.5.5

Temporarily Exiting the HALT Bus State

A refresh request or bus hold request causes the BID to exit the HALT bus state temporarily. This
can occur only when in the Active or Idle power management mode. The BIU returns to the
HALT bus state after it completes the desired bus operation. However, the BID does not execute
another bus HALT cycle (i.e., ALE and bus cycle status are not regenerated). Figures 3-26 and
3-27 illustrate how the BID temporarily exits and then returns to the HALT bus state.

3-30

BUS INTERFACE UNIT

CLKOUT
....,'--

HOLD

HLDA

_____--Ir

_____

AD15:0
------------------~I~I--------------[ AD7:0
A15:SJ

A19:16

------------~~~I--------------

CONTROL

Note
______v_a_lid____-J~~I---------------

NOTE: A19:16 and control signals remain floating until a valid cycle
occur (Le., the BIU exists HALT or a refresh bus cycle is generated.)
A1067-0A

Figure 3-26. Returning to HALT After a HOLD/HLDA Bus Exchange

3-31

intet

BUS INTERFACE UNIT

CLKOUT ~

ALE ---u
82:0

---il

\'--___-J!

AD1S:0
---il
[AD7:0]
[A1S:8]

---il

A19:16 ---il

R~~~

INote

Note 1

~,--_ _ _A_1_9:_16_=_O_ _ _ __

Address

-'-"Not;"2l\ - -- -Not; "3 -- --

NOTE:
1. Previous bus cycle value.
2. Only occurs for SHE on the first refresh bus cycle after entering HALT.
3. SHE = 1 for 16-bit device, RFSH

=0 for a-bit device.
Al068-0A

Figure 3-27. Returning to HALT After a Refresh Bus Cycle

3.5.6

Exiting HALT

Any NMI or maskable interrupt forces the BID to exit the HALT bus state (in any power management mode). The first bus operations to occur after exiting HALT are read cycles to reload the
CS:IP registers. Figure 3-28 and Figure 3-29 show how the HALT bus state is exited when an
NMI or INTn occurs.

3-32

int"et~

BUS INTERFACE UNIT

CLKOUT

------I~
:~

l
ALE

8 1/2 clocks to first vector fetch

.------,

------I~I-4I------------~I~1--~

82:0

I
I

------I~I~I------------~I~I----~--------------

\'-----AD15:0
[AD7:0]

-----II
------II

[A 15:8]

Note

------II

_ _ BHE
[RF8H = 1]

------II

A19: 16

------II

L.....-_.....J}---

II-I- - - - - - - - - - - - - - - - - - -

~ Time is determi,ned by PDTMR

NMI

(41/2 clocks mln;?t--_______________

NOTE: Previous bus cycle address value,
A1069·0A

Figure 3-28. Exiting HALT (Powerdown Mode)

3-33

intet~

BUS INTERFACE UNIT

Valid

-2-=--=---=--=---=--=-- C§0--

---n----+-E---_---_-- N~te

-JX Address

_ _--1Ir---_ _ _ _ _ _ _......:....:N.=..ot:.;:;e-=3;........_ _ _ _ _

Note 4

Note 3

1. For NMI, delay =4112 clocks. For INTx, delay =7112 clocks (min).
2. If previous bus cycle was a read, bus will float. If previous bus cycle was
a write, bus will drive data value.
3. Previous bus cycle value.
4. If previous bus cycle was a refresh cycle, value will be 8H (A19 = 1);
otherwise, value will be O.
A1070·0A

Figure 3-29. Exiting HALT (Active/Idle Mode)

3.6

SYSTEM DESIGN ALTERNATIVES

Most system designs require no signals other than those already provided by the BIU. However,
heavily loaded bus conditions, slow memory or peripheral device performance and off-board device interfaces may not be supported directly without modifying the BIU interface. The following
sections deal with topics to enhance or modify the operation of the BIU.

3-34

intet
3.6.1

BUS INTERFACE UNIT

Buffering the Data Bus

The BIU generates two control signals, DEN and DTIR, to control bidirectional buffers or transceivers. The timing relationship of DEN and DTIR is shown in Figure 3-30. The following conditions require transceivers:
• The capacitive load on the address/data bus gets too large.
• The current load on the address/data bus exceeds device specifications.
• Additional VOL and V OH drive is required.
• A memory or 110 device cannot float its outputs in time to prevent bus contention, even at
reset.

CLKOUT

\\.-_ _---11

RD,WR
DT/R
DEN

~
_ _ _ -oJI

\
\

_\"---__. .1. . _/

Write Cycle Operation
Read Cycle Operation
Al094-AO

Figure 3-30. DEN and DT/R Timing Relationships

The circuit shown in Figure 3-31 illustrates how to use transceivers to buffer the address/data bus.
The connection between the processor and the transceiver is known as the local bus. A connection
between the transceiver and other memory or 110 devices is known as the buffered bus. Afully
buffered system has no devices attached to the local bus. A partially buffered system has devices
on both the local and buffered buses.

3-35

intet

BUS INTERFACE UNIT

ALE

A19:1V
Processor

Latch

Address Bus

~
V

Address

DT/R

DEN

-=>

CPU Local Bus

Transceiver

~a1aB~ Data

Memory
or

CS ~

1/0
Device

Buffered Bus
A1095-0A

Figure 3-31. Buffered AD Bus System

In a fully buffered system, DEN directly drives the transceiver output enable. A partially buffered
system requires that DEN be qualified with another signal to prevent the transceiver from going
active for local bus accesses. Figure 3-32 illustrates how to use chip-selects to qualify DEN.
DTtR always connects directly to the transceiver. However, an inverter may be required if the polarity of DTtR does not match the transceiver. DTtR goes 19w (0) only for memory and I/O read,
instruction prefetch and interrupt acknowledge bus cycles.

3-36

BUS INTERFACE UNIT

AD15:8
DEN

GCSO

-...

---.. T
AD7:0

D15:8

Buffer'

Buffered
Data
Bus

DT/R

,8/ ...

D7:0

... T
Buffer

8/
/

}

Local
Data
Bus
Al096-01

Figure 3-32. Qualifying DEN with Chip-Selects

3.6.2

Synchronizing Software and Hardware Events

The execution sequence of a program and hardware events occurring within a system are often
asynchronous to each other_ In some systems there may be a requirement to suspend program execution until an event (or events) occurs, then continue program execution.
One way to synchronize software execution with hardware events requires the use of interrupts.
Executing a HALT instruction suspends program execution until an unmasked interrupt occurs.
However, there is a delay associated with servicing the interrupt before program execution can
proceed. Using the WAIT instruction removes the delay associated with servicing interrupts_

3-37

BUS INTERFACE UNIT

The WAIT instruction suspends program execution until one of two events occurs: an interrupt is
generated, or the TEST input pin is sampled low. Unlike interrupts, the TEST input pin does not
require that program execution be transferred to a new location (i.e., an interrupt routine is not
executed). In processing the WAIT instruction, program execution remains suspended as long as
TEST remains high (at least until an interrupt occurs). When TEST is sampled low, program execution resumes.
The TEST input and WAIT instruction provide a mechanism to delay program execution until a
hardware event occurs, without having to absorb the delay associated with servicing an interrupt.

3.6.3

Using a Locked Bus

To address the problems of controlling accesses to shared resources, the BIU provides a hardware
LOCK output. The execution of a LOCK prefix instruction activates the LOCK output.
LOCK goes active in phase 1 of TI of the first bus cycle following execution of the LOCK prefix
instruction. It remains active until phase 1 of TI of the first bus cycle following the execution of
the instruction following the LOCK prefix. To provide bus access control in multiprocessor systems, the LOCK signal should be incorporated into the system bus arbitration logic residing in
the CPU.
During normal multiprocessor system operation, priority of the shared system bus is determined
by the arbitration circuits on a cycle by cycle basis. As each CPU requires a transfer over the system bus, it requests access to the bus via its resident bus arbitration logic. When the CPU gains
priority (determined by the system bus arbitration scheme and any associated logic), it takes control of the bus, performs its bus cycle and either maintains bus control, voluntarily releases the
bus or is forced off the bus by the loss of priority.
The lock mechanism prevents the CPU from losing bus control (either voluntarily or by force)
and guarantees that the CPU can execute multiple bus cycles without intervention and possible
corruption of the data by another CPU. A classic use of the mechanism is the "TEST and SET
semaphore," during which a CPU must read from a shared memory location and return data to
the location without allowing another CPU to reference the same location during the test and set
operations.
Another application of LOCK for multiprocessor systems consists of a locked block move, which
allows high speed message transfer from one CPU's message buffer to another. During the locked
instruction (i.e., while LOCK is active), a bus hold or refresh request is recorded, but is not acknowledged until completion of the locked instruction. However, LOCK has no effect on interrupts. As an example, a locked HALT instruction causes bus hold or refresh bus requests to be
ignored, but still allows the CPU to exit the HALT state on an interrupt.

3-38

BUS INTERFACE UNIT

In general, prefix bytes (such as LOCK) are considered extensions of the instructions they precede. Interrupts and refresh requests that occur during execution of the prefix are not acknowledged until the instruction following the prefix completes (except for instructions that are
servicing interrupts during their execution, such as HALT, WAIT and repeated string primitives).
Note that multiple prefix bytes can precede an instruction.
Another example is a string primitive preceded by the repetition prefix (REP), which can be interrupted after each execution of the string primitive, even if the REP prefix is combined with the
LOCK prefix. This prevents interrupts from being locked out during a block move or other repeated string operations. However, bus hold and refresh requests remain locked out until LOCK
is removed (either when the block operation completes or after an interrupt occurs).

3.7

MULTI-MASTER BUS SYSTEM DESIGNS

The BIU supports protocols for transferring control of the local bus between itself and other devices capable of acting as bus masters. To support such a protocol, the BIU uses a hold request
input (HOLD) and a hold acknowledge output (HLDA) as bus transfer handshake signals. To gain
control of the bus, a device asserts the HOLD input, then waits until the HLDA output goes active
before driving the bus. After HLDA goes active, the requesting device can take control of the local bus and remains in control of the bus until HOLD is removed.

3.7.1

Entering Bus HOLD

In responding to the hold request input, the BIU floats the entire address and data bus, and many
of the control signals. Figure 3-33 illustrates the timing sequence when acknowledging the hold
request. Table 3-7 lists the states of the BIU pins when HLDA is asserted. All device pins not
mentioned in Table 3-7 or shown in Figure 3-33 remain either active (e.g., CLKOUT and
T1 OUT) or inactive (e.g., UCS and INTA). Refer to the data sheet for specific details of pin functions during a bus hold.

3-39

BUS INTERFACE UNIT

CLKOUT

HOLD

HLDA

AD15:0
DEN
A19:16
RD,W~

DT/R
S2:0,BHE
LOCK
NOTES:
1.
2.
3.
4.

T CLiS
T CHOF
T CLOF
T CLOY

: HOLD input to clock low
: Clock high to output float
: Clock low to output fl?at
: Clock low to HLDA high
Al097-0A

Figure 3-33. Timing Sequence Entering HOLD
Table 3-7. Signal Condition Entering HOLD
Signal

HOLD Condition

A19:16, S2:0, RD, WR, DT/R, BHE (RFSH), LOCK

These signals float one-half clock before HLDA
is generated (Le., p'hase 2).

AD15:0 (16-bit), AD7:0 (S-bit), A15:S (S-bit), DEN

These signals float during the same clock in
which HLDA is generated (Le., phase 1).

3.7.1.1

HOLD Bus Latency

The duration between the time that the external device asserts HOLD and the time that the BIU
asserts HLDA is known as bus latency. In Figure 3-33, the two-clock delay between HOLD and
HLDA represents the shortest bus latency. Normally this occurs only if the bus is idle or halted
or if the bus hold request occurs just before the BIU begins another bus cycle.
3-40

in1et

BUS INTERFACE UNIT

The major factors that influence bus latency are listed below (in order from longest delay to shortest delay).
1.

Bus Not Ready serviced.

Locked Bus Cycle - As long as LOCK remains asserted, a bus hold request cannot be
serviced. Performing a locked move string operation can take several thousands of clocks.

Completion of Current Bus Cycle - A bus hold request cannot be serviced until the
current bus cycle completes. A bus hold request will not separate bus cycles required to
move odd-aligned word data. Also, bus cycles with long wait states will delay the
servicing of a bus hold request.

Interrupt Acknowledge Bus Cycle - A bus hold request is not serviced until after an
INTA bus cycle has completed. An INTA bus cycle drives LOCK active.

Refresh Bus Cycles - A bus hold request is not serviced until after the refresh bus cycle
has completed. Refresh bus cycles have a higher priority than hold bus requests.

3.7.1.2

As long as the bus remains not ready, a bus hold request cannot be

Refresh Operation During a Bus HOLD

Under normal operating conditions, once HLDA has been asserted it remains asserted until
HOLD is removed. However, when a refresh bus request is generated, the HLDA output is removed (driven low) to signal the need for the BIU to regain control of the local bus. The BIU does
not gain control of the bus until HOLD is removed. This procedure prevents the BID from just
arbitrarily regaining control of the bus.
Figure 3-34 shows the timing associated with the occurrence of a refresh request while HLDA is
active. Note that HLDA can be as short as one clock in duration. This happens when a refresh
request occurs just after HLDA is granted. A refresh request has higher priority than a bus hold
request; therefore, when the two occur simultaneously, the refresh request occurs before HLDA
becomes active.

3-41

BUS INTERFACE UNIT

CLKOUT

HOLD

HLDA

AD15:0
DEN

RD,WR,
BHE, 52:0

DT/R,

-------1

-------4 \-__________-{

~______

A19:16
LOCK
NOTES:
1. : HLDA is deasserted, signaling need to run refresh bus cycle
2. : External bus master terminates use of the bus
3. : HOLD deasserted
4. : Hold may be reasserted after one clock
5. : BIU runs refresh cycle
.
A109B'()A

Figure 3-34. Refresh Request During HOLD

The device requesting a bus hold must be able to detect a HLDA pulse that is one clock in duration. A bus lockup (hang) condition can result if the requesting device fails to detect the short
HLDA pulse and continues to wait for HLDA to be asserted while the BIU waits for HOLD to be
deasserted. The circuit shown in Figure 3-35 can be used to latch HLDA.

3-42

BUS INTERFACE UNIT

+5
+5

PRE
D

QI---- Latched HLDA

HLDA
CLR

RESOUT
HOLD
A1310-0A

Figure 3-35. Latching HLDA

The removal of HOLD must be detected for at least one clock cycle to allow the BIU to regain
the bus and execute a refresh bus cycle- Should HOLD go active before the refresh bus cycle is
complete, the BIU will release the bus and generate HLDA.

3.7.2

Exiting HOLD

Figure 3-36 shows the timing associated with exiting the bus hold state_ Normally a bus operation
(e.g., an instruction prefetch) occurs just after HOLD is released. However, if no bus cycle is
pending when leaving a bus hold state, the bus and associated control signals remain floating, if
the system is in normal operating mode. (For signal states associated with Idle and Powerdown
modes, see "Temporarily Exiting the HALT Bus State" on page 3-30).

3-43

intet~

BUS INTERFACE UNIT

CLKOUT

HOLD

HLDA

AD15:0
DEN
RD, WR, SHE,
DT IR, 82:0,
A19:16
NOTES:

1. T CLiS

: HOLD recognition setup to clock low
: HOLD internally synchronized
3. T CLOV : Clock low to HLDA low
4. T CHOV : Clock high to signal active (high or low)
5. T CLOV : Clock low to signal active (high or low)
2.~

A1099·0A

Figure 3-36. Exiting HOLD

3.8

BUS CYCLE PRIORITIES

The BIU arbitrates requests for bus cycles from the Execution Unit, the integrated peripherals
(e.g., Interrupt Control Unit) and external bus masters (Le., bus hold requests). The list below
summarizes the priorities for all bus cycle requests (from highest to lowest).
1.

Instruction execution read/write following a non-pipelined effective address calculation.

Refresh bus cycles.

Bus hold request.

Single step interrupt vectoring sequence.

Non-Maskable interrupt vectoring sequence.

3-44

intet,

BUS INTERFACE UNIT

Internal error (e.g., divide error, overflow) interrupt vectoring sequence.

Hardware (e.g., INTO) interrupt vectoring sequence.

8OC187 Math Coprocessor error interrupt vectoring sequence.

General instruction execution. This category includes read/write operations following a
pipelined effective address calculation, vectoring sequences for software interrupts and
numerics code execution. The following points apply to sequences of related execution
cycles.
- The second read/write cycle of an odd-addressed word operation is inseparable from
the first bus cycle.
- The second read/write cycle of an instruction with both load and store accesses (e.g.,
XCHG) can be separated from the frrst cycle by other bus cycles.
- Successive bus cycles of string instructions (e.g., MOVS) can be separated by other bus
cycles.
- When a locked instruction begins, its associated bus cycles become the highest priority
and cannot be separated (or preempted) until completed.

10. Bus cycles necessary to fill the prefetch queue.

3-45

intel·

Peripheral Control
Block

CHAPTER·· 4
PERIPHERAL CONTROL BLoak:
All integrated peripherals in the 80C186 Modular Core family are controlled by sets of registers
within an integrated Peripheral Control Block (PCB). The peripheral control registers are physically located in the peripheral devices they control, but they are addressed as a single block of
registers. The Peripheral Control Block encompasses 256 contiguous bytes and can be located on
any 256-byte boundary of memory or 110 space. The PCB Relocation Register, which is also located within the Peripheral Control Block, controls the location of the PCB.

4.1

PERIPHERAL CONTROL REGISTERS

Each of the integrated peripherals' control and status registers is located at a fixed offset above
the programmed base location of the Peripheral Control Block (see Table 4-1). These registers
are described in the chapters that cover the associated peripheral. "Accessing the Peripheral Control Block" on page 4-4 discusses how the registers are accessed and outlines considerations for
reading and writing them.

4.2

PCB RELOCATION REGISTER

In addition to control registers for the integrated peripherals, the Peripheral Control Block contains the PCB Relocation Register (Figure 4-1). The Relocation Register is located at a fixed offset within the Peripheral Control Block (Table 4-1). If the Peripheral Control Block is moved, the
Relocation Register also moves.
The PCB Relocation Register allows the Peripheral Control Block to be relocated to any 256-byte
boundary within memory or 110 space. The Memory 110 bit (MEM) selects either memory space
or 110 space, and the R19:8 bits specify the starting (base) address of the PCB. The remaining bit,
Escape Trap (ET), controls access to the math coprocessor interface.
"Setting the PCB Base Location" on page 4-6 describes how to set the base location and outlines
some restrictions on the Peripheral Control Block location.

4-1

PERIPHERAL CONTROL BLOCK

PCB Relocation Register

RELREG

Relocates the PCB within memory or 1/0 space.

o
R R R R
111
1
9 876

R R R
1
1
1
543

R
1
2

A1263-0A

Bit
Mnemonic

Reset
State

BltName

Function

Escape Trap

The ET bit controls access to the math coprocessor. If ET Is set, the CPU will trap (resulting In
a Type 7 Interrupt) when an ESC Instruction is
executed.
NOTE: The 8-blt bus version of the device
automatically traps an ESC opcode to the Type 7
Interrupt, regardless of the state of the ET bit.

MEM

Memory 1/0

The MEM bit specifies the PCB location. Set
MEM to locate the PCB In memory space, or
clear it to locate the PCB In I/O space.

R19:8

PCB Base
Address
Upper Bits

OFFH

R19:8 define the upper address bits of the PCB
base address. All lower bits are zero. R19:16 are
Ignored when the PCB is mapped to I/O space.

NOTE:

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 4-1. PCB Relocation Register

4-2

PERIPHERAL CONTROL BLOCK

Table 4-1. Peripheral Control Block

PCB
Offset

Function

PCB
Offset

Function

PCB
Offset

Function

PCB
Offset

Function

OOH

Reserved

40H

T2CNT

80H

GCSOST

COH

02H

EOI

42H

T2CMPA

82H

GCSOSP

C2H

Reserved

04H

POLL

44H

Reserved

84H

GCS1ST

C4H

Reserved

06H

POLLSTS

46H

T2CON

86H

GCS1SP

C6H

Reserved

08H

IMASK

48H

Reserved

88H

GCS2ST

C8H

Reserved

OAH

PRIMSK

4AH

Reserved

8AH

GCS2SP

CAH

Reserved

OCH

INSERV

4CH

Reserved

8CH

GCS3ST

CCH

Reserved

OEH

REQST

4EH

Reserved

8EH

GCS3SP

CEH

Reserved

10H

INSTS

50H

P1DIR

90H

GCS4ST

DOH

Reserved

12H

TCUCON

52H

P1PIN

92H

GCS4SP

D2H

Reserved

14H

SCUCON

54H

P1CON

94H

GCS5ST

D4H

Reserved

16H

14CON

56H

P1LTCH

96H

GCS5SP

D6H

Reserved

18H

IOCON

58H

P2DIR

98H

GCS6ST

D8H

Reserved

1AH

11CON

5AH

P2PIN

9AH

GCS6SP

DAH

Reserved

1CH

12CON

5CH

P2CON

9CH

GCS7ST

DCH

Reserved

1EH

13CON

5EH

P2LTCH

9EH

GCS7SP

DEH

Reserved

20H

Reserved

60H

BOCMP

AOH

LCSST

EOH

Reserved

22H

Reserved

62H

BOCNT

A2H

LCSSP

E2H

Reserved

24H

Reserved

64H

SOCON

A4H

UCSST

E4H

Reserved

26H

Reserved

66H

SOSTS

A6H

UCSSP

E6H

Reserved

28H

Reserved

68H

SORBUF

A8H

RELREG

E8H

Reserved

2AH

Reserved

6AH

SOTBUF

AAH

Reserved

EAH

Reserved

2CH

Reserved

6CH

Reserved

ACH

Reserved

ECH

Reserved

2EH

Reserved

6EH

Reserved

AEH

Reserved

EEH

Reserved

30H

TOCNT

70H

B1CMP

BOH

RFBASE

FOH

Reserved

32H

TOCMPA

72H

B1CNT

B2H

RFTIME

F2H

Reserved

34H

TOCMPB

74H

S1CON

B4H

RFCON

F4H

Reserved

36H

TOCON

76H

S1STS

B6H

RFADDR

F6H

Reserved

38H

T1CNT

78H

S1RBUF

B8H

PWRCON

F8H

Reserved

3AH

T1CMPA

7AH

S1TBUF

BAH

Reserved

FAH

Reserved

3CH

T1CMPB

7CH

Reserved

BCH

STEPID

FCH

Reserved

3EH

T1CON

7EH

Reserved

BEH

Reserved

FEH

Reserved

4-3

int"et

PERIPHERAL CONTROL BLOCK

4.3

RESERVED LOCATIONS

Many locations within the Peripheral Control Block are not assigned to any peripheral. Unused
locations are reserved. Reading from these locations yields an undefined result. If reserved registers are written (for example, during a block MOV instruction) they must be set to OR.
NOTE

Failure to follow this guideline could result in incompatibilities with future
80Cl86 Modular Core family products.

4.4

ACCESSING THE PERIPHERAL CONTROL BLOCK

All communication between integrated peripherals and the Modular CPU Core occurs over a special bus, called the F-Bus, which always carries 16-bit data. The Peripheral Control Block, like
all integrated peripherals, is always accessed 16 bits at a time.

4.4.1

Bus Cycles

The processor runs an external bus cycle for any memory or 110 cycle accessing a location within
the Peripheral Control Block. Address, data and control information is driven on the external pins
as with an ordinary bus cycle. Information returned by an external device is ignored, even if the
access does not correspond to the location of an integrated peripheral control register. This is also
true for the 80CI88 Modular Core family, except that word accesses made to integrated registers
are performed in two bus cycles.

4.4.2

READY Signals and Wait States

The processor generates an internal READY signal whenever an integrated peripheral is accessed. External READY is ignored. READY is also generated if an access is made to a location within the Peripheral Control Block that does not correspond to an integrated peripheral control
register. For accesses to timer control and counting registers, the processor inserts one wait state.
This is required to properly multiplex processor and counter element accesses to the timer control
registers. For accesses to the remaining locations in the Peripheral Control Block, the processor
does not insert wait states.

4-4

PERIPHERAL CONTROL BLOCK

4.4.3

F-Bus Operation

The F-Bus functions differently than the external data bus for byte and word accesses. All write
transfers on the F-Bus occur as words, regardless of how they are encoded. For example, the instruction OUT OX, AL (OX is even) will write the entire AX register to the Peripheral Control
Block register at location [OX]. If OX were an odd location, AL would be placed in [OX] and
AH would be placed at [OX-I]. A word operation to an odd address would write [OX] and [OX1] with AL and AH, respectively. This differs from normal external bus operation where unaligned word writes modify [OX] and [OX+ 1]. In summary, do not use odd-aligned byte or word
writes to the PCB.
Aligned word reads work normally. Unaligned word reads work differently. For example, IN AX,
OX (OX is odd) will transfer [OX] into AL and [OX-I] into AH. Byte reads from even or odd
addresses work normally, but only a byte will be read. For example, IN AL, OX will not transfer
[OX] into AX (only AL is modified).
No problems will arise if the following recommendations are adhered to.
Word reads

Aligned word reads of the PCB work normally. Access only evenaligned words with IN AX, OX or MOV word register, even PCB
address.

Byte reads

Byte reads of the PCB work normally. Beware of reading word-wide
PCB registers that may change value between successive reads (e.g.,
timer count value).

Word writes

Always write even-aligned words to the PCB. Writing an oddaligned word will give unexpected results.
For the 80CI86 Modular Core, use either
- OUT OX, AX or
- OUT OX, AL or
- MOV even PCB address, word register.
For the 80CI88 Modular Core, using OUT OX, AX will perform an
unnecessary bus cycle and is not recommended. Use either
- OUT OX, AL or
- MOV even-aligned byte PCB address, byte register low byte.

Byte writes

Always use even-aligned byte writes to the PCB. Even-aligned byte
writes will modify the entire word PCB location. Do not perform
unaligned byte writes to the PCB.

4-5

PERIPHERAL CONTROL BLOCK

4.4.3.1

Writing the PCB Relocation Register

Whenever mapping the Peripheral Control Block to another location, the user should program the
Relocation Register with a byte write (Le., OUT DX, AL). Internally, the Relocation Register is
written with 16 bits of the AX register, while externally the Bus Interface Unit runs a single 8-bit
bus cycle. If a word instruction (i.e., OUT DX, AX) is used with an 80C188 Modular Core family
member, the Relocation Register is written on the first bus cycle. The Bus Interface Unit then runs
an unnecessary second bus cycle. The address of the second bus cycle is no longer within the control block, since the Peripheral Control Block was moved on the first cycle. External READY
must now be generated to complete the cycle. For this reason, we recommend byte operations for
the Relocation Register.

4.4.3.2

Accessing the Peripheral Control Registers

Byte instructions should be used for the registers in the Peripheral Control Block of an 80C188
Modular Core family member. This requires half the bus cycles of word operations. Byte operations are valid only for even-addressed writes to the Peripheral Control Block. A word read (e.g.,
IN AX, DX) must be performed to read a 16-bit Peripheral Control Block register when possible.

4.4.3.3

Accessing Reserved Locations

Unused locations are reserved. If a write is made to these locations, a bus cycle occurs, but data
is not stored. If a subsequent read is made to the same location, the value written is not read back.
If reserved registers are written (for example, during a block MOV instruction) they must be
cleared to OH.
NOTE
Failure to follow this guideline could result in incompatibilities with future
80C186 Modular Core family products.

4.5

SETTING THE PCB BASE LOCATION

Upon reset, the PCB Relocation Register (see Figure 4-1 on page 4-2) contains the value OOFFH,
which causes the Peripheral Control Block to be located at the top of I/O space (OFFOOH to
OFFFFH). Writing the PCB Relocation Register allows the user to change that location.

4-6

in1et

PERIPHERAL CONTROL BLOCK

As an example, to relocate the Peripheral Control Block to the memory range lOOOO-lOOFFH, the
user would program the PCB Relocation Register with the value llOOH. Since the Relocation
Register is part of the Peripheral Control Block, it relocates to word lOOOOH plus its fixed offset.
NOTE

Due to an internal condition, external ready is ignored if the device is
configured in Cascade mode and the Peripheral Control Block (PCB) is
located at OOOOH in 110 space. In this case, wait states cannot be added to
interrupt acknowledge bus cycles. However, you can add wait states to
interrupt acknowledge cycles if the PCB is located at any other address.

4.5.1

Considerations for the 80C187 Math Coprocessor Interface

Systems using the 80C 187 math coprocessor interface must not relocate the Peripheral Control
Block to location OOOOH in 110 space. The 80C187 interface uses 110 locations OF8H through
OFFH. If the Peripheral Control Block resides in these locations, the processor communicates
with the Peripheral Control Block, not the 80C187 interface circuitry.
NOTE

If the PCB is located at OOOOH in 110 space and access to the math coprocessor
interface is enabled (the Escape Trap bit is clear), a numerics (ESC) instruction
causes indeterminate system operation.

Since the 8-bit bus version of the device does not support the 80C187, it automatically traps an
ESC instruction to the Type 7 interrupt, regardless of the state of the Escape Trap (ET) bit.
For details on the math coprocessor interface, see Chapter 12, "Math Coprocessing."

4-7

in1:et

Clock Generation and
Power Management

int'et
CHAPTER 5
CLOCK GENERATION AND POWER
MANAGEMENT
The clock generation and distribution circuits provide uniform clock signals for the Execution
Unit, the Bus Interface Unit and all integrated peripherals. The 80C186 Modular Core Family
processors have additional logic that controls the clock signals to provide power management
functions.
5.1

(fl-/'"

CLOCK GENERATION

I,!; t'~)

~.-.-'\)I.wA/)

X bUi'.,} "'"
The clock generation circuit (Figure 5-1) includes a crystal oscillator, a divide-by-two counterjM
and reset circuitry. See "Power Management" on page 5-10 for a discussion of power management options.
~~~---------------------e--------- Active Mode
01 -> Powerdown Mode
02 -> Idle Mode
03 -> Active Mode
None
Parameters are passed on the stack as required
by high-level languages

PWRCON equ xxxxH

-power.Jl\gt

-power_mgt
lib_80C186

;substitute PWRCON register
;offset
segment public 'code'
assume cs:lib_80C186
public -power_mgt
proc far
push
mov
push
push

bp
bp, sp
ax
dx

equ

word ptr[bp+6]

mov
mov
and
out
hlt
pop
pop
pop
ret
endp
ends
end

dx, PWRCON
ax, _mode
ax, 3
dx, ax

;save caller's bp
;get current top of stack
;save registers that will
;be modified
;get parameter off the
; stack
;select Power Control Reg
;get mode
;mask off unwanted bits

;enter mode
;restore saved registers

ax
bp

;restore caller's bp

Example 5-1. Initializing the Power Management Unit for Idle or Powerdown Mode

5.2.2

Powerdown Mode

Powerdown mode freezes the clock to the entire device (core and peripherals) and disables the
crystal oscillator. All internal devices (registers, state machines, etc.) maintain their states as long
as Vee is applied. The BIU will not honor DRAM refresh and HOLD requests in Powerdown
mode because the clocks for those functions are off. CLKOUT freezes in a logic high state. Current consumption in Powerdown mode consists of just transistor leakage (typically less than 100
microaIIlps).

5-16

CLOCK GENERATION AND POWER MANAGEMENT

5.2.2.1

Entering Powerdown Mode

Powerdown mode is entered by executing the HLT instruction after setting the PWRDN bit in the
Power Control Register (see Figure 5-9 on page 5-12). The HALT cycle turns off both the core
and peripheral clocks and disables the crystal oscillator. See Chapter 3, "Bus Interface Unit," for
detailed information on HALT bus cycles. Figure 5-12 shows the internal and external waveforms
during entry into Powerdown mode.

elKIN toggles
only when
external
frequency
input is used:

Halt Cycle
:On

T4 or T1

ClKIN
I
I

I
I

-----------,

Indeterminate I

08COUT

------------1

ClKOUT
CPU Core
Clock
Internal
Peripheral
Clock

82:0

ALE

011

\
Al121-0A

Figure 5-12. Entering Powerdown Mode

During the T2 phase of the HLT instruction, the core generates a signal called EntecPowerdown.
EntecPowerdown immediately disables the internal CPU core and peripheral clocks. The processor disables the oscillator inverter during the next CLKOUT cycle. If the design uses a crystal
oscillator, the oscillator stops immediately. When c:LKINoriginates from an external frequency
iJ!ItuUEFI), Powerdown isolates the signal on theCLKIN pin from the internal circuitry. Therefore, the circuit may drive CLKIN during Powerdown mode, although it will not clock the device.

5-17

intet

CLOCK GENERATION AND POWER MANAGEMENT

5.2.2.2

Leaving Powerdown Mode

An NMI or reset returns the processor to Active mode. If the device leaves Powerdown mode by
an NMI, a delay must follow the interrupt request to allow the crystal oscillator to stabilize before
gating it to the internal phase clocks. An external timing pin sets this delay as described below.
Leaving Powerdown by an NMI does not clear the PWRDN bit in the Power Control Register. A
reset also takes the processor out of Powerdown mode. Since the oscillator is off, the user should
follow the oscillator cold start guidelines (see "Reset and Clock Synchronization" on page 5-6).
The Powerdown timer circuit (Figure 5-13) has a PDTMR pin. Connecting this pin to an external
capacitor gives the user control over the gating of the crystal oscillator to the internal clocks. The
strong P-channel device is always on except during exit from Powerdown mode. This pullup
keeps the powerdown capacitor C PD charged up to Vee. C PD discharges slowly. At the same time,
the circuit turns on the feedback inverter on the crystal oscillator and oscillation starts.
The Schmitt trigger connected to the PDTMR pin asserts the internal OSC_OK signal when the
voltage at the pin drops below its switching threshold. The OSC_OK signal gates the crystal oscillator output to the internal clock circuitry. One CLKOUT cycle runs before the internal clocks
turn back on. It takes two additional CLKOUT cycles for an NMI request to reach the CPU and
another six clocks for the vector to be fetched,

0, Except when leaving
Powerdown

Strong P-Channel
Pullup

PDTMR Pin

Weak N-Channel
Pulldown

r---

Exit Powerdown

A1122-0A

Figure 5-13. Powerdown Timer Circuit

5-18

int:et

CLOCK GENERATION AND POWER MANAGEMENT

The first step in determining the proper CPD value is startup time characterization for the crystal
oscillator circuit. This step can be done with a storage oscilloscope if you compensate for scope
probe loading effects. Characterize startup over the full range of operating voltages and temperatures. The oscillator starts up on the order of a couple of milliseconds. After determining the oscillator startup time, refer to "PD1MR Pin Delay Calculation" in the data sheet. Multiply the
startup time (in seconds) by the given constant to get the CPD value. Typical values are less than

1!JF.
If the design uses an external oscillator instead of a crystal, the external oscillator continues running during Powerdown mode. Leave the PDTMR pin unconnected and the processor can exit
Powerdown mode immediately.

5.2.3

Implementing a Power Management Scheme

Table 5-2 summarizes the power management options available to the user. Overall power consumption has two parts: switching power dissipated by driving loads such as the address/data bus,
and device power dissipated internally by the microprocessor whether or not it is connected to
external devices. A power management scheme should consider loading as well as the raw specifications in the processor's data sheet.
Table 5·2. Summary of Power Management Modes
User
Overhead

Relative
Power

Typical
Power

Active

Full

250 mW at 16 MHz

Idle

Low

175 mW at 16 MHz

Low

Powerdown

Lowest

250llW

Low to Moderate

Mode

Chief
Advantage
Full-speed operation
Peripherals are unaffected
Long battery life

NOTE

If an NMI or external maskable interrupt service routine is used to enter a
power management mode, the interrupt request signal should be deassefted
before entering the power management mode.

5-19

6
Chip-Select Unit

CHAPTER 6
CHIP-SELECT UNIT
Every system requires some form of component-selection mechanism to enable the CPU to access a specific memory or peripheral device. The signal that selects the memory or peripheral device is referred to as a chip-select. Besides selecting a specific device, each chip-select can be
used to control the number of wait states inserted into the bus cycle. Devices that are too slow to
keep up with the maximum bus bandwidth can use wait states to slow the bus down.

6.1

COMMON METHODS FOR GENERATING CHIP-SELECTS

One method of generating chip-selects uses latched address signals directly. An example interface
is shown in Figure 6-1(A). In the example, an inverted A16 is connected to an SRAM device with
an active-low chip-select. Any bus cycle with an address between 10000H and IFFFFH (A16
1) enables the SRAM device. Also note that any bus cycle with an address starting at 30000H,
50000H, 70000H and so on also selects the SRAM device.

Decoding more address bits solves the problem of a chip-select being active over multiple address
ranges. In Figure 6-1 (B), a one-of-eight decoder is connected to the uppermost address bits. Each
decoded output is active for one-eighth of the 1 Mbyte address space. However, each chip-select
has a fixed starting address and range. Future system memory changes could require circuit
changes to accommodate the additional memory.

6.2

CHIP-SELECT UNIT FEATURES AND BENEFITS

The Chip-Select Unit overcomes limitations of the designs shown in Figure 6-1 and has the following features:
• Ten chip-select outputs
• Programmable start and stop addresses
• Memory or I/O bus cycle decoder
• Programmable wait-state generator
• Provision to disable a chip-select
• Provision to override bus ready
Figure 6-2 illustrates the logic blocks that generate a chip-select. Each chip-select has a duplicate
set of logic.

6-1

CHIP-SELECT UNIT

27C256

74AC138
07:0

A19

Selects 896K to 1M

A18

Selects 768K to 896K

A17

RO---OIOE

ALE
HLOA
Selects 128K to 256K

A16

Selects 0 to 128K

(A)
Chip-Selects Using
Addresses Directly

(8)
Chip-Selects Using
Simple Decoder
Al168-0A

Figure 6-1. Common Chip-Select Generation Methods

6.3

CHIP-SELECT UNIT FUNCTIONAL OVERVIEW

The Chip-Select Unit (CSU) decodes bus cycle address and status information and enables the
appropriate chip-select. Figure 6-3 illustrates the timing of a chip-select during a bus cycle. Note
that the chip-select goes active in the same bus state as address goesactive, eliminating any delay
through address latches and decoder circuits. The Chip-Select Unit activates a chip-select for bus
cycles initiated by the CPU or Refresh Control Unit.
Any of the ten chip-selects can map into either memory or I/O address space. A memory-mapped
chip-select can start and end on any 1 Kbyte address location. An I/O-mapped chip-select can
start and end on any 64 byte address location. The chip-selects typically associate with memory
and peripheral devices as follows:

6-2

intet

CHIP-SELECT UNIT

Ignore Stop
Address
ISTOP

Stop
Value
Memory/IO
Selector
MEM
Internal
Address
Bus

Chip Select
Enable
CSEN

Stop
Value <
Comparator
Chip
Select

Address
Shifter
Start
Value

Start
Value

Peripheral Control Block
Access Indicator
Al16Q-OA

Figure 6-2. Chip-Select Block Diagram

Mapped to the upper memory address space; selects the BOOT memory device
(EPROM or Flash memory types).
Mapped to the lower memory address space; selects a static memory (SRAM)
device that stores the interrupt vector table, local stack, local data, and scratch
pad data.
GCS7:0

Mapped to memory or I/O address space; selects additional SRAM memory,
DRAM memory, local peripherals, system bus, etc.

6-3

intet~

CHIP-SELECT UNIT

T4
I

CLKOUT
ALE
A15:0
A19:16

GCS7:0
LCS,UCS
S2:0

KAddr6ss valid)>---i-------+-------i-----!

I
I

:
I

I .
I

I
:

l\. . --~--~--~----~--~--~~~
J

I .
I

:
I

:t----{:~'--~:----~:----~--~:~--~---+----~I~
:'---.
: K:
:7
: !\J
1
!\1...--i---_--i----tJl/: !
i
I

StatuS

: :

RD,WR

I
I
I

' :

I
I

A115Q-OA

Figure 6-3. Chip-Select Relative Timings

A chip-select goes active when it meets all of the following criteria:
1.

The chip-select is enabled.

The bus cycle status matches the programmed type (memory or 110).

The bus cycle address is equal to or greater than the start address value.

The bus cycle address is less than the stop address value or the stop address is ignored.

The bus cycle is not accessing the Peripheral Control Block.

A memory address applies to memory read, memory write and instruction prefetch bus cycles.
An 110 address applies to 110 read and 110 write bus cycles. Interrupt acknowledge and HALT
bus cycles never activate a chip-select, regardless of the address generated.
After power-on or system reset, only the UCS chip-select is initialized and active (see Figure 6-4).

6-4

intet

CHIP-SELECT UNIT

Address
Flash

Ready

1MB
,.... __,Data

1023K

Active For
Top 1 KByte

Processor

Memory
Map

o
NOTE:
1. 15 Wait states automatically inserted. Bus READY must be provided.
A1162·0A

Figure 6-4. UCS Reset Configuration

6.4

PROGRAMMING

Two registers, START and STOP, determine the operating characteristics of each chip-select. The
Peripheral Control Block defines the location of the Chip-Select Unit registers. Table 6-1 lists the
registers and their associated programming names.
Table 6-1. Chip-Select Unit Registers
START Register
Mnemonic

STOP Register
Mnemonic

Chip-Select Affected

GCSOST

GCSOSP

GCSO

GCS1ST

GCS1SP

GCS1

GCS2ST

GCS2SP

GCS2

GCS3ST

GCS3SP

GCS3

GCS4ST

GCS4SP

GCS4

GCS5ST

GCS5SP

GCS5

GCS6ST

GCS6SP

GCS6

GCS7ST

GCS7SP

GCS7

UCSST

UCSSP

UCS

LCSST

LCSSP

LCS

6-5

CHIP-SELECT UNIT

The START register (Figure 6-5) defines the starting address and the wait state requirements. The
STOP register (Figure 6-6) defines the ending address and the bus ready, bus cycle and enable
requirements.

6.4.1

Initialization Sequence

Chip-selects do not have to be initialized in any specific order. However, the following guidelines
help prevent a system failure.
1.

Initialize local memory chip-selects

Initialize local peripheral chip-selects

Perform local diagnostics

Initialize off-board memory and peripheral chip-selects

Complete system diagnostics

An unmasked interrupt or NMI must not occur until the interrupt vector addresses have been written to memory. Failure to prevent an interrupt from occurring during initialization will cause a
system failure. Use external logic to generate the chip-select if interrupts cannot be masked prior
to initialization..

6·6

CHIP-SELECT UNIT

Chip-Select Start Register

UCSST, LCSST, GCSxST (x=O-7)

Defines chip-select start address and number of
bus wait states.

o
w w w w
s s s S

15
C

543

C
S

A1163-0A

Bit
Mnemonic

Bit Name

Reset
State

Function

CS9:0

Start
Address

3FFH

Defines the starting (base) address for the chipselect. CS9:0 are compared with the A19:10
(memory bus cycles) or A 15:6 (1/0 bus cycles)
address bits. An equal to or greater than result
enables the chip-select.

WS3:0

Wait State
Value

OFH

WS3:0 define the minimum number of wait
states inserted into the bus cycle_ A zero value
means no wait states. Additional wait states
can be inserted into the bus cycle using bus
ready.

NOTE:

Reserved register bits are shown with gray shading_ Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 6-5. START Register Definition

6-7

CHIP-SELECT UNIT

Chip-Select Stop Register

UCSSP, LCSSP, GCSxSP (x=O-7)

Defines chip-select stop address and other control
functions.

15
C
S

C
S

C
S
5

C
S
4

C
S
3

C
S
2

C
S

E
N

I
S

R
D
Y

0
P
A1164-0A

Bit
Mnemonic

Bit Name

Reset
State

Function

CS9:0

Stop
Address

3FFH

Defines the ending address for the chip-select.
CS9:0 are compared with the A19:10 (memory
bus cycles) or A15:6 (I/O bus cycles) address
bits. A less than result enables the chip-select.
CS9:0 are ignored if ISTOP is set.

CSEN

Chip-Select
Enable

0
(Note)

Disables the chip-select when cleared. Setting
CSEN enables the chip-select.

ISTOP

Ignore Stop
Address

0
(Note)

Setting this bit disables stop address checking,
which automatically sets the ending address at
OFFFFFH (memory) or OFFFFH (I/O). When
ISTOP is cleared, the stop address requirements must be met to enable the chip-select.

NOTE:

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products. The reset state of
CSEN and ISTOP is '1' for the UCSSP register.

Figure 6-6. STOP Register Definition

6-8

CHIP-SELECT UNIT

Chip-Select Stop Register

UCSSP, LCSSP, GCSxSP (x=O-7)

Defines chip-select stop address and other control
functions.

C
S

S
T
0
P

E
M

R
0
Y

A1164-0A

Bit
Mnemonic

MEM

Bit Name

Bus Cycle
Selector

Reset
State

Function

When MEM is set, the chip-select goes active
for memory bus cycles. Clearing MEM activates
the chip-select for 1/0 bus cycles.
MEM defines which address bits are used by
the start and stop address comparators. When
MEM is cleared, address bits A15:6 are routed
to the comparators. When MEM is set, address
bits A19:10 are routed to the comparators.

ROY

NOTE:

Bus Ready
Enable

Setting ROY requires that bus ready be active
to complete a bus cycle. Bus ready is ignored
when ROY is cleared. ROY must be set to
extend wait states beyond the number
determined by WS3:0.

Figure 6-6. STOP Register Definition (Continued)

The correct sequence to program a non-enabled chip-select is as follows. (If the chip-select is already enabled, either reverse the sequence or disable the chip-select before reprogramming it.)

Program the START register

Program the STOP register

6-9

intet

CHIP-SELECT UNIT

6.4.2

Start Address

The START register of each chip-select defines its starting (base) address. The start address value
is compared to the ten most-significant address bits of the bus cycle. A bus cycle whose ten mostsignificant address bits are equal to or greater than the start address value causes the chip-select
to go active. Table 6-2 defines the address bits that are compared with the start address value for
memory and I/O bus cycles.
It is not possible to have a chip-select start on any arbitrary byte boundary. A chip-select configured for memory accesses can start only on multiples of 1 Kbyte. A chip-select configured for I/O
accesses can start only on multiples of 64 bytes. The equations below calculate the physical start
address for a given start address value.
For memory accesses:Start Value (Decimal) x 1024 = Physical Start Address (Decimal)
For I/O accesses:Start Value (Decimal) x 64= Physical Start Address (Decimal)

Table 6-2. Memory and VO Compare Addresses
Address Range

Number of Bits

Comparator Input

Memory

1 Mbyte

A19:A10

1 Kbyte

I/O

64 Kbyte

A15:A6

64 Bytes

Address Space

6.4.3

Resolution

Stop Address

The STOP register of each chip-select defines its ending address. The stop address value is compared to the ten most-significant address bits of the bus cycle. A bus cycle whose ten most-significant bits of address are less than the stop address value causes the chip-select to go active.
Table 6-2 defines the address bits that are compared with the stop address value for memory and
I/O bus cycles.
It is not possible to have a chip-select end on any arbitrary byte boundary. A chip-select configured for memory accesses can end only on multiples of 1 Kbyte. A chip-select configured for I/O
accesses can end only on multiples of 64 bytes. The equations below define the ending address
for the chip-select.
For memory accesses:(Stop Value (Decimal) x 1024) -1= Physical Ending Address (Decimal)
For I/O accesses:(Stop Value (Decimal) x 64) -1= Physical Ending Address (Decimal)

6-10

CHIP-SELECT UNIT

In the previous equations, a stop value of 1023 (03FFH) results in a physical ending address of
OFFBFFH (memory) or OFFBFH (I/O). These addresses do not represent the top of the memory
or I/O address space. To have a chip-select enabled to the end of the physical address space, the
ISTOP control bit must be set. The IS TOP control bit overrides the stop address comparator output (see Figure 6-2 on page 6-3).

6.4.4

Enabling and Disabling Chip-Selects

The ability to enable or disable a chip-select is important when multiple memory devices share
(or can share) the same physical address space. Examples of where two or more devices would
occupy the same address space include shadowed memory, bank switching and paging.
The STOP register holds the CSEN control bit, which determines whether the chip-select should
go active. A chip-select never goes active if its CSEN control bit is cleared.
Chip-selects can be disabled by programming the stop address value less than the start address
value or by programming the start address value greater than the stop address value. However,
the ISTOP control bit cannot be set when chip-selects are disabled in this manner.

6.4.5

Bus Wait State and Ready Control

Normally, the bus ready input must be inactive at the appropriate time to insert wait states into
the bus cycle. The Chip-Select Unit can ignore the state of the bus ready input to extend and complete the bus cycle automatically. Most memory and peripheral devices operate properly using fifteen or fewer wait states. However, accessing such devices as a dual-port memory, an expansion
bus interface, a system bus interface or remote peripheral devices can require more than fifteen
wait states to complete a bus cycle.
The START register holds a four-bit value (WS3:0) that defines the number of wait states to insert
into the bus cycle. Figure 6-7 shows a simplified logic diagram of the wait state and ready control
functions.

6-11

intet~

CHIP-SELECT UNIT

BUSREADY-----------4
READY Control Bit -----\
READY
Wait State Value (WS3:0)

Wait
State
Counter
A1165-0A

Figure 6-7. Wait State and Ready Control Functions

The STOP register defines the RDY control bit to extend bus cycles beyond fifteen wait states.
The RDY control bit determines whether the bus cycle should complete normally (i.e., require
bus ready) or unconditionally (i.e., ignore bus ready). Chip-selects connected to devices requiring
fifteen wait states or fewer can program RDY inactive to automatically complete the bus cycle.
Devices that may require more than fifteen wait states must program RDY active.
A bus cycle with wait states automatically inserted cannot be shortened. A bus cycle that ignores
bus ready cannot be lengthened.

6.4.6

Overlapping Chip-Selects

The Chip-Select Unit activates all enabled chip-selects programmed to cover the same physical
address space. This is true if any portion of the chip-selects' address ranges overlap (i.e., chipselects' ranges do not need to overlap completely to all go active). There are various reasons for
overlapping chip-selects. For example, a system might have a need for overlapping a portion of
read-only memory with read/write memory or copying data to two devices siumltaneously.
If overlapping chip-selects do not have identical wait state and bus ready programming, the ChipSelect Unit will adjust itself based on the criteria shown in Figure 6-8.

6-12

intet

CHIP-SELECT UNIT

Wait
Minimum
WS3:0

Wait
Maximum
WS3:0

Wait
State

Complete
Bus
Cycle

Yes

All66-0A

Figure 6-8. Overlapping Chip-Selects

6-13

CHIP-SELECT UNIT

Table 6-3 lists example wait state and bus ready requirements for overlapping chip-selects and
the resulting requirements for accesses to the overlapped region.
Table6-3. Example Adjustments for Overlapping Chip-Selects
Chip-Select X

Chip-Select Y

Overlapped Region Access

Wait States

Bus Ready

Walt States

Bus Ready

Walt States

Bus Ready

ignored

required

ignored

required

Be cautious when overlapping chip-selects with different wait state or bus ready programming.
The following two conditions require special attention to ensure proper system operation:
1.

When all overlapping chip-selects ignore bus ready but have different wait states, verify
that each chip-select still works properly using the highest wait state value. A system
failure may result when too few or too many wait states occur in the bus cycle.

If one or more of the overlapping chip-selects requires bus ready, verify that all chipselects that ignore bus ready still work properly using both the smallest wait state value
and the longest possible bus cycle. A system failure may result when too few or too many
wait states occur in the bus cycle.

6.4.7

Memory or VO Bus Cycle Decoding

The Chip-Select Unit decodes bus cycle status and address information to determine whether a
chip-select goes active. The MEM control bit in the STOP register defines whether memory or
I/O address space is decoded. Memory address space accesses consist of memory read, memory
write and instruction prefetch bus cycles. I/O address space accesses consist of I/O read and I/O
write bus cycles.
Chip-selects go active for bus cycles initiated by the CPU and Refresh Control Unit.

6.4.8

Programming Considerations

When programming chip-selects active for I/O bus cycles, remember that eight bytes of I/O are
reserved by Intel. These eight bytes (locations OOF8H through OOFFH) control the interface to an
8OC187 math coprocessor. A chip-select can overlap this reserved space provided there is no intention of using the 80C 187. However, to avoid possible future compatibility issues, Intel recommends that no chip-select start at I/O address location OOCOH.

6-14

intet

CHIP-SELECT UNIT

The GCS chip-select outputs are multiplexed with output port functions. The register that controls
the multiplexed outputs resides in the 110 Port Unit. (See Table II-Ion page 11-7 and Figure 11-5
on page 11-8.)

6.5

CHIP-SELECTS AND BUS HOLD

The Chip-Select Unit decodes only internally generated address and bus state information. An external bus master cannot make use of the Chip-Select Unit. During HLDA, all chip-selects remain
inactive.
The circuit shown in Figure 6-9 allows an external bus master to access a device during bus
HOLD.

CSU Chip Select - - - ,

:=====:~

External Master Chip Select -----'

Device select
A1167·0A

Figure 6-9. USing Chip-Selects During HOLD

6.6

EXAMPLES

The following sections provide examples of programming the Chip-Select Unit to meet the needs
of a particular application. The examples do not go into hardware analysis or design issues.

6.6.1

Example 1: Typical System Configuration

Figure 6-10 illustrates a block diagram of a typical system design with a 128 Kbyte EPROM and
a 32 Kbyte SRAM. The peripherals are mapped to 110 address space. Example 6.1 shows a program template for initializing the Chip-Select Unit.

6-15

CHIP-SELECT UNIT

READY

r--

ALE
A19:16
AD15:0

a
t

c I-

r+-h
'--

EPROM
128K

0
R
A
M
512K

Address/
Bus
~ CE

SRAM
32K

r+- CE
I I

Floppy
Disk I - - Control

~ AO

----. CE

DMA

...

HLDA I~
AO:3
HOLD 'CE

HOLD
HLDA
UCS
GCS1
LCS
GCS2
GCSO

Al146-0A

Figure 6-10. Typical System

6-16

CHIP-SELECT UNIT

TITLE
MOD186XREF
NAME

$
$

(Chip-Select Unit Initialization)

External reference from this module
include (PCBMAP. INC)

;File declares Register
;Locations and names.

Module equates
Configuration equates
TRUE
FALSE
READY
CSEN
ISTOP
MEM
10

EQU
EQU
EQU
EQU
EQU
EQU
EQU

OFFH
NOT TRUE
0001H
0008H
0004H
0002H
OOOOH

;BuS ready control modifier
;Chip-Select enable modifier
;Stop address modifier
;Memory select modifier
;1/0 select modifier

;Below is a list of the default system memory and I/O environment. These
;defaults configure the Chip-Select Unit for proper system operation.
;EPROM memory is located from OEOOOO to OFFFFF (128 Kbytes).
;Wait states are calculated assuming 16MHz operation.
;UCS# controls the accesses to EPROM memory space.
EPROM_SIZEEQU
EPROM_BASEEQU
EPROM_WAITEQU

128
; Size in Kbytes
1024 - EPROM_SIZE;Start address in Kbytes
1
;Wait states

;The UCS# START and STOP register values are calculated using the above system
;constraints and the equations below.
UCSST_VALEQU
UCSSP_VALEQU

(EPROM_BASE SHL 6) OR (EPROM_WAIT)
(CSEN) OR (ISTOP) OR (MEM)

;SRAM memory starts at OH and continues to 7FFFH (32 Kbytes).
;Wait states are calculated assuming 16MHz operation.
;LCS# controls the accesses to SRAM memory space.
SRAM_SIZEEQU
SRAM_BASEEQU
SRAM_WAITEQU

o
o

;Size in Kbytes
;Start address in Kbytes
;Wait states

;The LCS# START and STOP register values are calculated using the above system
;constraints and the equations below
LCSST_VALEQU
LCSSP_VALEQU
&

(SRAM_BASE SHL 6) OR (SRAM_WAIT)
(((SRAM_BASE) OR (SRAM_SIZE»
SHL 6) OR
(CSEN) OR (MEM)

A DRAM interface is selected by the GCS1# chip-select. The BASE value defines
the starting address of the DRAM window. The SIZE value (along with the BASE
value) defines the ending address. Zero wait state performance is assumed. The
Refresh Control Unit uses DRAM_BASE to properly configure refresh operation.

Example 6-1. Initializing the Chip-Select Unit

6-17

intet

CHIP-SELECT UNIT

DRAM_BASEEQU
DRAM_SIZEEQU
DRAM_WAITEQU

128
512

Window start address in Kbytes
Window size in Kbytes
Wait states (change to match
system)

;The GCS1# START and STOP register values are calculated using the above systen
;constraints and the equations below
GCS1ST_VALEQU
GCS1SP_VALEQU
&

(DRAM_BASE SHL 6) OR (DRAM_WAIT)
«(DRAM_BASE) OR (DRAM_SIZE»
SHL 6) OR
(CSEN) OR (MEM)

;I/O is selected using the GCS2# chip-select. Wait states assume operation at
;16MHz. The SIZE and BASE values must be modulo 64 bytes. For this example, the
;Floppy Disk Controller is connected to GCS2# and GCSO# is connected to
;the DMA Controller.
IO_SIZEEQU
IO_BASEEQU
IO_WAITEQU

64
256
4

;Size in bytes
;Start address in bytes
;Wait states

DMA_BASEEQU
DMA_WAITEQU

512

;Start address in bytes
;Wait states
;Size assumed to be 64 bytes

;The GCSO# and GCS2# START and STOP register values are calculated using the
;above system contraints and the equations below.
GCS2ST_VALEQU
GCS2SP_VALEQU

«IO_BASE/64) SHL 6) OR (IO_WAIT)
«(IO_BASE/64) OR (IO_SIZE/64»
SHL 6) OR
(CSEN) OR (IO)

GCSOST_VALEQU
GCSOSP_VALEQU

«DMA_BASE/64) SHL 6) OR (DACK_WAIT)
«(DMA_BASE/64) + 1) SHL 6) OR (CSEN) OR (IO)

;The following statements define the default assumptions for SEGMENT locations.
ASSUMECS:CODE
ASSUMEDS:DATA
ASSUMESS:DATA
ASSUMEES:DATA
CODE

SEGMENT PUBLIC

'CODE'

;ENTRY POINT ON POWER UP:
;The power-on or reset code does a jump here after the UCS register is
; programmed.
FW_STARTLABEL

FAR

CLI

;Forces far jump
;Make sure interrupts are
;globally disabled

;Place register initialization code here

Example 6-1. Initializing the Chip-Select Unit (Continued)

6-18

CHIP-SELECT UNIT

;SET UP CHIP SELECTS
UCS#
LCS#
GCS1#
GCS2#
GCSO#

EPROM Select
SRAM
Select
DRAM
Select
FLOPPY Select
DMA
Select
DX, UCSSP
UCSSP_VAL
DX, AL

MOV
MOV
OUT

AX. ,

MOV
MOV
OUT
MOV
MOV
OUT

DX, LCSST
LCSST_VAL
DX, AL
DX, LCSSP
AX. , LCSSP_VAL
DX, AL

;Set up LCS#

DX, GCS1ST
GCS1ST_VAL
DX, AL
AX. , GCS1SP_VAL
DX, GCS1SP
DX, AL

;Set up GCS1#

MOV
MOV
OUT
MOV
MOV
OUT
MOV
MOV
OUT
MOV
MOV
OUT
MOV
MOV
OUT
MOV
MOV
OUT

;Finish setting up UCS#
; Remember, byte writes work ok

AX. ,

; Remember, byte writes work ok

AX. ,

; Remember, byte writes work ok

DX, GCSOST
GCSOST_VAL
DX, AL
AX. , GCSOSP_VAL
DX, GCSOSP
DX, AL

;Set up GCSO#

DX, GCS2ST
GCS2ST_VAL
DX, AL
DX, GCS2SP
AX. , GCS2SP_VAL
DX, AL

;Set up GCS2#

AX. ,

; Remember, byte writes work ok

AX. ,

; Remember, byte writes work ok

;Place remaining User Code here.
CODE

ENDS

;POWER ON RESET CODE TO GET STARTED
ASSUME CS:POWER_ON
POWER_ON SEGMENT AT OFFFFH
MOV
MOV
OUT
JMP

DX, UCSST
UCSST_VAL
DX, AL
FW_START

AX. ,

;Point to UCS register
;Reprogram UCS# for EPROM size
;Jump to start of init code

POWER_ON ENDS

Example 6-1. Initializing the Chip-Select Unit (Continued)

6-19

CHIP-SELECT UNIT

DATA SEGMENT
DATA SEGMENT PUBLIC

'DATA'

256 DUP (?)

;Reserved for Interrupt Vectors

;Place additional memory variable here
DW
STACK_TOP

LABEL

DATA

ENDS

;Stack allocation

500 DUP (?)

WORD

;Program Ends
END

Example 6-1. Initializing the Chip-Select Unit (Continued)

6.6.2

Example 2: Detecting Attempts to Access Guarded Memory

A chip-select is configured to set an interrupt when the bus accesses a physical address region
that does not contain a valid memory or peripheral device. Figure 6-11 illustrates how a simple
circuit detects the errant bus cycle and generates an NMI. System software then deals with the
error. The purpose of using the chip-select is to generate a bus ready and prevent a bus "hang"
condition.

Processor
NMI

GCS5

,...
.....
A1158-0A

Figure 6-11. Guarded Memory Detector

6-20

infel.

Refresh Control Unit

intet
CHAPTER 7
REFRESH CONTROL UNIT
The Refresh Control Unit (RCU) simplifies dynamic memory controller design with its integrated address and clock counters. Figure 7-1 shows the relationship between the B us Interface Unit
and the Refresh Control Unit. Integrating the Refresh Control Unit into the processor allows an
external DRAM controller to use chip-selects, wait state logic and status lines.

~
.A

...

)

CPU
Clock ...

F-Bus
.A

...

)

Refresh Clock
Interval Register

V
9-Bit Down
Counter

Refresh Request

BIU
Interface

CLR Refresh Acknowledge
REO
Refresh Control
Register
12-Bit Address Counter

...

)

Refresh Base
Address Register

7
;'

Refresh Address
Register

... v

13 vi-'
;"

20-Bit
Refresh Address
A1264-01

Figure 7-1. Refresh Control Unit Block Diagram

7-1

REFRESH CONTROL UNIT

7.1

THE ROLE OF THE REFRESH CONTROL UNIT

Like a DMA controller, the Refresh Control Unit runs bus cycles independent of CPU execution.
Unlike a DMA controller, however, the Refresh Control Unit does not run bus cycle bursts nor
does it transfer data. The DRAM refresh process freshens individual DRAM rows in "dummy
read" cycles, while cycling through all necessary addresses.
The microprocessor interface to DRAMs is more complicated than other memory interfaces. A
complete DRAM controller requires circuitry beyond that provided by the processor even in the
simplest configurations. This circuitry must respond correctly to reads, writes and DRAM refresh
cycles. The external DRAM controller generates the Row Address Strobe (RAS), Column Address Strobe (CAS) and other DRAM control signals.
Pseudo-static RAMs use dynamic memory cells but generate address strobes and refresh addresses internally. The address counters still need external timing pulses. These pulses are easy to derive from the processor's bus control signals. Pseudo-static RAMs do not need a full DRAM
controller.

7.2

REFRESH CONTROL UNIT CAPABILITIES

A 12-bit address counter forms the refresh addresses, supporting any dynamic memory devices
with up to 12 rows of memory cells (12 refresh address bits). This includes all practical DRAM
sizes for the processor's 1 Mbyte address space.

7.3

REFRESH CONTROL UNIT OPERATION

Figure 7-2 illustrates Refresh Control Unit counting, address generation and BIU bus cycle generation in flowchart form.
The nine-bit down-counter loads from the Refresh Interval Register on the falling edge of CLKOUT. Once loaded, it decrements every falling CLKOUT edge until it reaches one. Then the
down-counter reloads and starts counting again, simultaneously triggering a refresh request.
Once enabled, the DRAM refresh process continues indefinitely until the user reprograms the Refresh Control Unit, a reset occurs, or the processor enters Powerdown mode.
The refresh request remains active until the bus becomes available. When the bus is free, the BIU
will run its "dummy read" cycle. Refresh bus requests have higher priority than most CPU bus
cycles, all DMA bus cycles and all interrupt vectoring sequences. Refresh bus cycles also have a
higher priority than the HOLDIHLDA bus arbitration protocol (see "Refresh Operation and Bus
HOLD" on page 7-13).

7-2

REFRESH CONTROL UNIT

Refresh Control
Unit Operation

BIU Refresh
Bus Operation

Set "E" Bit

Refresh Request
Acknowledged

Execute
Memory Read

Load Counter
From Refresh Clock
Interval Register

Executed
Every
Clock
Continue
Decrement
Counter

A1265-0A

Figure 7-2. Refresh Control Unit Operation Flow Chart

The nine-bit refresh clock counter does not wait until the BIU services the refresh request to continue counting. This operation ensures that refresh requests occur at the correct interval. Otherwise, the time between refresh requests would be a function of varying bus activity. When the
BIU services the refresh request, it clears the request and increments the refresh address.

7-3

REFRESH CONTROL UNIT

The BIU does not queue DRAM refresh requests. If the Refresh Control Unit generates another
request before the BIU handles the present request, the BIU loses the present request. However,
the address associated with the request is not lost. The refresh address changes only after the BIU
runs a refresh bus cycle. If a DRAM refresh cycle is excessively delayed, there is still a chance
that the processor will successfully refresh the corresponding row of cells in the DRAM, retaining
the data.

7.4

REFRESH ADDRESSES

Figure 7-3 shows the physical address generated during a refresh bus cycle. This figure applies
to both the 8-bit and 16-bit data bus microprocessor versions. Refresh address bits RA 19: 13 come
from the Refresh Base Address Register. (See "Refresh Base Address Register" on page 7-7.)
From Refresh Base
Address Register
From Refresh Address Counter
Fixed
~~--------~----~iir------------------------------~I'-'

20-Bit Refresh Address
A1266-0A

Figure 7-3. Refresh Address Formation

A linear-feedback shift counter generates address bits RA12:1 and RAO is always one. The
counter does not count linearly from 0 through FFFH. However, the counting algorithm cycles
uniquely through all possible 12-bit values. It matters only that each row of DRAM memory cells
is refreshed at a specific interval. The order of the rows is unimportant.
Address bit AO is fixed at one during all refresh operations. In applications based on a 16-bit data
bus processor, AO typically selects memory devices placed on the low (even) half of the bus. Applications based on an 8-bit data bus processor typically use AO as a true address bit. The DRAM
controller must not route AO to row address pins on the DRAMs.

7-4

REFRESH CONTROL UNIT

7.5

REFRESH BUS CYCLES

Refresh bus cycles look exactly like ordinary memory read bus cycles except for the control signals listed in Table 7-1. These signals can be ANDed in a DRAM controller to detect a refresh
bus cycle. The 16-bit bus processor drives both the BHE and AO pins high during refresh cycles.
The 8-bit bus version replaces the BHE pin with RFSH, which has the same timings. The 8-bit
bus processor drives RFSH low and AO high during refresh cycles.
Table 7-1. Identification of Refresh Bus Cycles
BHEIRFSH

16-Bit Device

a-Bit Device

Data Bus Width

7.6

GUIDELINES FOR DESIGNING DRAM CONTROLLERS

The basic DRAM access method consists of four phases:
I.

The DRAM controller supplies a row address to the DRAMs.

The DRAM controller asserts a Row Address Strobe (RAS), which latches the row
address inside the DRAMs.

The DRAM controller supplies a column address to the DRAMs.

The DRAM controller asserts a Column Address Strobe (CAS), which latches the column
address inside the DRAMs.

Most 8OC186 Modular Core family DRAM interfaces use only this method. Others are not discussed here.
The DRAM controller's purpose is to use the processor's address, status and control lines to generate the multiplexed addresses and strobes. These signals must be appropriate for three bus cycle
types: read, write and refresh. They must also meet specific pulse width, setup and hold timing
requirements. DRAM interface designs need special attention to transmission line effects, since
DRAMs represent significant loads on the bus.
DRAM controllers may be either clocked or unclocked. An unclocked DRAM controller requires
a tapped digital delay line to derive the proper timings.
Clocked DRAM controllers may use either discrete or programmable logic devices. A state machine design is appropriate, especially if the circuit must provide wait state control (beyond that
possible with the processor's Chip-Select Unit). Because of the microprocessor's four-clock bus,
clocking some logic elements on each CLKOUT phase is advantageous (see Figure 7-4).

7-5

infelQP

REFRESH CONTROL UNIT

T3fTW

CLKOUT
Muxed
Address

\
NOTES:

1. CAS is unnecessary for refresh cycles only.
2. WE is necessary for write cycles only.
A1267·0A

Figure 7-4. Suggested DRAM Control Signal Timing Relationships

The cycle begins with presentation of the row address. RAS should go active on the falling edge
of T2. At the rising edge of T2, the address lines should switch to a column address. CAS goes
active on the falling edge of T3. Refresh cycles do not require CAS. When CAS is present, the
"dummy read" cycle becomes a true read cycle (the DRAM drives the bus), and the DRAM row
still gets refreshed.
Both RAS and CAS stay active during any wait states. They go inactive on the falling edge ofT4.
At the rising edge of T4, the address multiplexer shifts to its original selection (row addressing),
preparing for the next DRAM access.

7-6

REFRESH CONTROL UNIT

7.7

PROGRAMMING THE REFRESH CONTROL UNIT

Given a specific processor operating frequency and information about the DRAMs in the system,
the user can program the Refresh Control Unit registers.

7.7.1

Calculating the Refresh Interval

DRAM data sheets show DRAM refresh requirements as a number of refresh cycles necessary
and the maximum period to run the cycles. (The number of refresh cycles is the same as the number of rows.) You must compensate for bus latency - the time it takes for the Refresh Control
Unit to gain control of the bus. This is typically 1-5%, but if an external bus master will be extremely slow to release the bus, increase the overhead percentage. At standard operating frequencies, DRAM refresh bus overhead totals 2-3% of the total bus bandwidth.
Given this information and the CPU operating frequency, use the formula in Figure 7-5 to determine the correct value for the RFfIME Register value.
RpERIOD X Fcpu

- - - - - - - - - - = RFTIME RegisterValue
Rows + (ROWS x Overhead%)

Maximum refresh period specified by DRAM manufacturer (in I1s).
Operating frequency (in MHz).
Total number of rows to be refreshed.
Overhead %

Derating factor to compensate for missed refresh requests (typically 1 - 5 %).

Figure 7-5. Formula for Calculating Refresh Interval for RFTIME Register

7.7.2

Refresh Control Unit Registers

Three contiguous Peripheral Control Block registers operate the Refresh Control Unit: the Refresh Base Address Register, Refresh Clock Interval Register and the Refresh Control Register.
A fourth register, the Refresh Address Register, permits examination of the refresh address bits
generated by the Refresh Control Unit.
7.7.2.1

Refresh Base Address Register

The Refresh Base Address Register (Figure 7-6) programs the base (upper seven bits) of the refresh address. Seven-bit mapping places the refresh address at any 4 Kbyte boundary within the
1 Mbyte address space. When the partial refresh address from the 12-bit address counter (see Figure 7-1 and "Refresh Control Unit Capabilities" on page 7-2) passes FFFH, the Refresh Control
Unit does not increment the refresh base address. Setting the base address ensures that the address
driven during a refresh bus cycle activates the DRAM chip select.

7-7

infel~

REFRESH CONTROL UNIT

Refresh Base Address Register

RFBASE

Determines upper 7 bits of refresh address.

o
R
A
1

R
A
1

987

3
A100B-OA

Bit
Mnemonic
RA19:13
NOTE:

Bit Name
Refresh
Base

Reset
State

OOH

Function
Uppermost address bits for DRAM r~fresh
cycles.

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 7-6. Refresh Base Address Register
7.7.2.2

Refresh Clock Interval Register

The Refresh Clock Interval Register (Figure 7-7) defines the time between refresh requests. The
higher the value, the longer the time between requests. The down-counter decrements every falling CLKOUT edge, regardless of core activity. When the counter reaches one, the Refresh Control Unit generates a refresh request, and the counter reloads the value from the register.

7·8

REFRESH CONTROL UNIT

Refresh Clock Interval Register

RFTIME

Sets refresh rate.

o
R
C

R
C

765

321

A1288'OA

Bit
Mnemonic
RC8:0
NOTE:

Bit Name
Refresh Counter
Reload Value

Reset
State

OOOH

Function
Sets the desired clock count between refresh
cycles.

Reserved register bits are shown with gray shading. Reserved bits must be written to a
logic zero to ensure compatibility with future Intel products.

Figure 7-7. Refresh Clock Interval Register
7.7.2.3

Refresh Control Register

Figure 7-8 shows the Refresh Control Register. The user may read or write the REN bit at any
time to turn the Refresh Control Unit on or off. The lower nine bits contain the current nine-bit
down-counter value. The user cannot program these bits. Disabling the Refresh Control Unit
clears both the counter and the corresponding counter bits in the control register.

7-9

intet~

REFRESH CONTROL UNIT

Refresh Control Register

RFCON

Controls Refresh Unit operation.

o
R
C

R
C

R
R
R
C
C
C
321

R
C
0

A1311-0A

Bit
Mnemonic

Bit Name

Reset
State

Function

REN

Refresh
Control Unit
Enable

Setting REN enables the Refresh Unit. Clearing
REN disables the Refresh Unit.

RC8:0

Refresh
Counter

OOOH

These bits contain the present value of the
down-counter that triggers refresh requests.
The user cannot program these bits.

NOTE:

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 7-8. Refresh Control Register
7.7.2.4

Refresh Address Register

The Refresh Address Register (Figure 7-9) contains address bits RAI2:1, which will appear on
the bus as A12: I on the next refresh bus cycle. Bit 0 is fixed as a one in the register and in all
refresh addresses.

7-10

REFRESH CONTROL UNIT

Refresh Address Register

RFADDR

Contains the generated refresh address bits.

o
R
A

R
A

R R R R
A A A A

1
1

1
0

A1501-0A

Bit
Mnemonic

Bit Name

Reset
State

Function

RA12:1

Refresh
Address Bits

OOOH

These bits comprise A12:1 of the refresh
address.

RAO

Refresh Bit
0

AO of the refresh address. This bit is always 1
and is read-only.

NOTE:

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 7-9. Refresh Address Register

7.7.3

Programming Example

Example 7-1 contains sample code to initialize the Refresh Control Unit.

7-11

REFRESH CONTROL UNIT

$mod186
name
FUNCTION: This function initializes the DRAM Refresh
Control Unit to refresh the DRAM starting at dram_addr
at cloc~time intervals.
SYNTAX:

extern void far config_rcu(int

dr~addr,

int clock_time};

INPUTS:

dram_addr - Base address of DRAM to refresh
clock_time - DRAM refresh rate

OUTPUTS:

None
NOTE: Parameters are passed on the stack as
required by high-level languages.

RFBASE
RFTIME
RFCON
Enable

equ
equ
equ
equ

xxxxh

;substitute register offset

xxxxh
xxxxh

8000h

;enable bit

segment public 'code'
assume cs:lib_80186
public _config_rcu
proc far

_clock_time
_dr~addr

push bp
mov bp, sp

;save caller's bp
;get current top of stack

equ
equ

word ptr[bp+6]
word ptr [bp+8]

;get parameters off
;the stack

push
push
push
push

ax
cx

;save registers that
;will be modified

Example 7-1. Initializing the Refresh Control Unit

7-12

intet

REFRESH CONTROL UNIT

mov
mov
out

dx, RFBASE
ax, _dram_addr
dx, al

;set upper 7 address bits

mov
mov
out

dx, RFTIME
ax, _clock_time
dx, al

;set clock pre_scaler

mov
mov
out

dx, RFCON
ax, Enable
dx, al

;Enable RCU

mov

cx, 8

xor

di, di

;8 dummy cycles are
;required by DRAMs
;before actual use

_exercise_ram:
mov word ptr [dil, 0
loop _exercise_ram
pop
pop
pop
pop
pop

_config_rcu
lib_80186

di
dx
cx
ax
bp

;restore saved registers

;restore caller's bp

ret
endp
ends
end

Example 7-1. Initializing the Refresh Control Unit (Continued)

7.8

REFRESH OPERATION AND BUS HOLD

When another bus master controls the bus, the processor keeps HLDA active as long as the
HOLD input remains active. If the Refresh Control Unit generates a refresh request during bus
hold, the processor drives the HLDA signal inactive, indicating to the current bus master that it
wishes to regain bus control (see Figure 7-10). The BIU begins a refresh bus cycle only after the
alternate master removes HOLD. The user must design the system so that the processor can regain bus control. If the alternate master asserts HOLD after the processor starts the refresh cycle,
the CPU will relinquish control by asserting HLDA when the refresh cycle is complete.

7-13

REFRESH CONTROL UNIT

CLKOUT

HOLD

AD15:0

DEN----~----~~~----~----~----~-T----~

RD,WR,
BHE,S2~O

____T-____~~~__-T______~____~__~

DT JR,
A19:16
NOTES:
1. HLDA is deasserted; signaling need to run DRAM refresh cycles less than TCLOV'
2. External bus master terminates use of the bus.
3. HOLD deasserted; greater than TCLiS'
4. Hold may be reasserted after one clock.
5. Lines come out of float in order to run DRAM refresh cycle.
A1269-0A

Figure 7-10. Regaining Bus Control to Run a DRAM Refresh Bus Cycle

7-14

8
Interrupt Control
Unit

in1et
CHAPTER 8
INTERRUPT CONTROL UNIT
The 80C186 Modular Core has a single maskable interrupt input. (See "Interrupts and Exception
Handling" on page 2-39.) The Interrupt Control Unit (ICU) expands the interrupt capabilities beyond a single input. It receives and processes maskable interrupts from multiple sources and presents them to the CPU through the maskable interrupt input. Interrupts can originate from the onchip peripherals and from five external interrupt pins. The Interrupt Control Unit synchronizes
and prioritizes the interrupts and provides the interrupt type vector to the CPU. (See Figure 8-1.)
The Interrupt Control Unit has the following features:
• Programmable priority of each interrupt source
• Individual masking of each interrupt source
• Nesting of interrupt sources
• Support for polled operation
• Support for cascading external 8259A modules to expand external interrupt sources

8.1

FUNCTIONAL OVERVIEW

All microcomputer systems must communicate in some way with the external world. A typical
system might have a keyboard, a disk drive and a communications port, all requiring CPU attention at different times. There are two distinct ways to process peripheral I/O requests: polling and
interrupts.
Polling requires that the CPU check each peripheral device in the system periodically to seewhether it requires servicing. It would not be unusual to poll a low-speed peripheral (a serial port,
for instance) thousands of times before it required servicing. In most cases, the use of polling has
a detrimental effect on system throughput. Any time used to check the peripherals is time spent
away from the main processing tasks.
Interrupts eliminate the need for polling by signalling the CPU that a peripheral device requires
servicing. The CPU then stops executing the main task, saves its state and transfers execution to
the peripheral-servicing code (the interrupt handler). At the end of the interrupt handler, the
CPU's original state is restored and execution continues at the point of interruption in the main
task.

8-1

intet

INTERRUPT CONTROL UNIT

til
Timer 0 Timer 1 Timer 2

Serial
Serial
Receive Transmit

INTO INT1 INT2 INT3 INT4

Interrupt
Priority
Resolver

Vector
Generation
Logic

To CPU Interrupt Request

F - Bus
NOTE: The three timers are multiplexed into a single input, as are the two serial interrupts.
A1203-AO

Figure 8·1. Interrupt Control Unit Block Diagram

(~ 7/J'/~s ~)

8.1.1

Generic Functions

Several functions of the Interrupt Control Unit are common among most interrupt controllers.
This section describes how those generic functions are implemented in the Interrupt Control Unit.
8.1.1.1

Interrupt Masking

There are circumstances in which a programmer may need to disable an interrupt source temporarily (for example, while executing a time-critical section of code or servicing a high-priority
task). This temporary disabling is called interrupt masking. All interrupts from the Interrupt Control Unit can be masked either globally or individually.

8-2

intet

INTERRUPT CONTROL UNIT

The Interrupt Enable bit in the Processor Status Word globally enables or disables the maskable
interrupt request from the Interrupt Control Unit. The programmer controls the Interrupt Enable
bit with the STI (set interrupt) and CLI (clear interrupt) instructions.
Besides being globally enabled or disabled by the Interrupt Enable bit, each interrupt source can
be individually enabled or disabled. The Interrupt Mask register has a single bit for each interrupt
source. The programming can selectively mask (disable) or unmask (enable) each interrupt
source by setting or clearing the corresponding bit in the Interrupt Mask register.
8.1.1.2

Interrupt Priority

One critical function of the Interrupt Control Unit is to prioritize interrupt requests. When multiple interrupts are pending, priority determines which interrupt request is serviced first. In many
systems, an interrupt handler may itself be interrupted by another interrupt source. This is known
as interrupt nesting. With interrupt nesting, priority determines whether an interrupt source can
preempt an interrupt handler that is currently executing.
Each interrupt source is assigned a..Qrioritybetween zero (hi~hest) and seven (lowest). After reset,
the interrupts default to the prioriti~~~sho'wn in Table 8-1. Because the timers share an interrupt
source, they also share a priority. Within the assigned priority, each has a relative priority (Timer
o has the highest relative priority and Timer 2 has the lowest). The serial channel 0 receive and
transmit interrupts also share a priority. Within the assigned priority, the receive interrupt has the
higher relative priority.
Table 8-1. Default Interrupt Priorities

AIAwl&'

?1l..1Ctf.\lj
Interrupt Name

Relative Priority

Timer 0

/IV/O

Timer 1

jlvT I

IIVTlI-

Timer 2

o (a)
o (b)
o (c)
1(a)
1(b)

I~T"2..

S-

Serial Channel 0 Receive

/~T3

Serial Channel 0 Transmit

The priority of each source is programmable. The Interrupt Control register enables the
programmer to assign each source a priority that differs from the default. The priority must still
be between zero (highest) and seven (lowest). Interrupt sources can be programmed to share a
priority. The Interrupt Control Unit uses the default priorities (see Table 8-1) within the shared
priority level to determine which interrupt to service first. For example, assume that INTO and
INTI are both programmed to priority seven. Because INTO has the higher default priority, it is
serviced first.

8-3

INTERRUPT CONTROL UNIT

intet

Interrupt sources can be masked on the basis of their priority. The Priority Mask register masks
all interrupts with priorities lower than its programmed value. After reset, the ~ori!Y M~Kreg
ister contains priority seven, which effectively enabl~s al1int~rruJ?ts. The programmer can then
.
program the register with any valid priority level.
8.1.1.3

Interrupt Nesting

When entering an interrupt handler, the CPU pushes the Processor Status Word onto the stack and
clears the Interrupt Enable bit. The processor enters all interrupt handlers with maskable interrupts disabled. Maskable interrupts remain disabled until either the IRET instruction restores the
Interrupt Enable bit or the programmer explicitly enables interrupts. Enabling maskable interrupts within an interrupt handler allows interrupts to be nested. Otherwise, interrupts are processed sequentially; one interrupt handler must finish before another executes.
The simplest way to use the Interrupt Control Unit is without nesting. The operation and servicing
of all sources of maskable interrupts is straightforward. However, the application tradeoff is that
an interrupt handler will finish executing even if a higher priority interrupt occurs. This can add
considerable latency to the higher priority interrupt.
In the simplest terms, the Interrupt Control Unit asserts the maskable interrupt request to the CPU,
waits for the interrupt acknowledge, then presents the interrupt type of the highest priority unmasked interrupt to the CPU. The CPU then executes the interrupt handler for that interrupt. Because the interrupt handler never sets the Interrupt Enable bit, it can never be interrupted.
The function of the Interrupt Control Unit is more complicated with interrupt nesting. In this case,
an interrupt can occur during execution of an interrupt handler. That is, one interrupt can preempt·
another. Two rules apply for interrupt nesting:
• An interrupt source cannot preempt interrupts of higher priority.
• An interrupt source cannot preempt itself. The interrupt handler must finish executing
before the interrupt is serviced again. (Special Fully Nested Mode is an exception. See
"Special Fully Nested Mode" on page 8-8.)

8.2

FUNCTIONAL OPERATION

This section covers the process in which the Interrupt Control Unit receives interrupts and asserts
the maskable interrupt request to the CPU.

8-4

INTERRUPT CONTROL UNIT

8.2.1

TYpical Interrupt Sequence

When the Interrupt Control Unit first detects an interrupt, it sets the corresponding bit in the Interrupt Request register to indicate that the interrupt is pending. The Interrupt Control Unit checks
all pending interrupt sources. If the interrupt is unmasked and meets the priority criteria (see "Priority Resolution" on page 8-5), the Interrupt Control Unit asserts the maskable interrupt request
to the CPU, then waits for the interrupt acknowledge.
When the Interrupt Control Unit receives the interrupt acknowledge, it passes the interrupt type
to the CPU. At that point, the CPU begin the interrupt processing sequence.(See "InterruptlException Processing" on page 2-39 for details.) The Interrupt Control Unit always passes the vector
that has the highest priority at the time the acknowledge is received. If a higher priority interrupt
occurs before the interrupt acknowledge, the higher priority interrupt has precedence.
When it receives the interrupt acknowledge, the Interrupt Control Unit clears the corresponding
bit in the Interrupt Request register and sets the corresponding bit in the In-Service register. The
In-Service register keeps track of which interrupt handlers are being processed. At the end of an
interrupt handler, the programmer must issue an End-of-Interrupt (EOl) command to explicitly
clear the In-Service register bit. If the bit remains set, the Interrupt Control Unit cannot process
any additional interrupts from that source.

8.2.2

Priority Resolution

The decision to assert the maskable interrupt request to the CPU is somewhat complicated. The
complexity is needed to support interrupt nesting. First, an interrupt occurs and the corresponding Interrupt Request register bit is set The Interrupt Control Unit 'then asserts the
maskable interrupt request to the CPU, if the pending interrupt satisfies these requirements:
1.

its Interrupt Mask bit is cleared (it is unmasked)

its priority is higher than the value in the Priority Mask register

its In-Service bit is cleared

its priority is equal to or greater than that of any interrupt whose In-Service bit is set

The In-Service register keeps track of interrupt handler execution. The Interrupt Control Unit
uses this information to decide whether another interrupt source has sufficient priority to preempt
an interrupt handler that is executing.

8-5

INTERRUPT CONTROL UNIT

8.2.2.1

Priority Resolution Exampte

This example illustrates priority resolution. Assume these initial conditions:
• the Interrupt Control Unit has been initialized
• no interrupts are pending
• no In-Service bits are set
• the Interrupt Enable bit is set
• all interrupts are unmasked
• the default priority scheme is being used
• the Priority Mask register is set to the lowest priority (seven)
The example uses two external interrupt sources, INTO and INTI, to describe the process.
1.

A low-to-high transition on INTO sets its Interrupt Request bit. The interrupt is now
pending.

Because INTO is the only pending interrupt, it meets all the priority criteria. The Interrupt
Control Unit asserts the interrupt request to the CPU and waits for an acknowledge.

The CPU acknowledges the interrupt.

The Interrupt Control Unit passes the interrupt type (in this case, type 12) to the CPU.

The Interrupt Control Unit clears the INTO bit in the Interrupt Request register and sets the
INTO bit in the In-Service register.

The CPU executes the interrupt processing sequence and begins executing the interrupt
handler for INTO.

During execution of the INTO interrupt handler, a low-to-high transition on INT3 sets its
Interrupt Request bit.

The Interrupt Control Unit determines that INT3 has a lower priority than INTO, which is
currently executing (INTO's In-Service bit is set). INT3 does not meet the priority criteria,
so no interrupt request is sent to the CPU. (If INT3were programmed with a higher
priority than INTO, the request would be sent.) INT3 remains pending in the Interrupt
Request register.

The INTO interrupt handler completes and sends an EO! command to clear the INTO bit in
the In-Service register.

10. INT3 is still pending and now meets all the priority criteria. The Interrupt Control Unit
asserts the interrupt request to the CPU and the process begins again.

8-6

INTERRUPT CONTROL UNIT

8.2.2.2

Interrupts That Share a Single Source

Multiple interrupt requests can share a single interrupt input to the Interrupt Control Unit. (For
example, the three timers share a single input.) Although these interrupts share an input, each has
its own interrupt vector. (For example, when a Timer 0 interrupt occurs, the Timer 0 interrupt handler is executed.) This section uses the three timers as an example to describe how these interrupts
are prioritized and serviced.
The Interrupt Status register acts as a second-level request register to process the timer interrupts.
It contains a bit for each timer interrupt. When a timer interrupt occurs, both the individual Inter-

rupt Status register bit and the shared Interrupt Request register bit are set. From this point, the
interrupt is processed like any other interrupt source.
When the shared interrupt is acknowledged, the timer interrupt with the highest priority (see Table 8-1 on page 8-3) at that time is serviced first and that timer's Interrupt Status bit is cleared.
If no other timer Interrupt Status bits are set, the shared Interrupt Request bit is also cleared. If
other timer interrupts are pending, the Interrupt Request bit remains set.
When the timer interrupt is acknowledged, the shared In-Service bit is set. No other timer interrupts can occur when the In-Service bit is set. If a second timer interrupt occurs while another
timer interrupt is being serviced, the second interrupt remains pending until the interrupt handler
for the first interrupt finishes and clears the In-Service bit. (This is true even if the second interrupt has a higher priority than the first.)

8.2.3

Cascading with External 8259As

For applications that require more external interrupt pins than the number provided on the Interrupt Control Unit, external 8259A modules can be used to increase the number of external interrupt pins. The cascade mode of the Interrupt Control Unit supports the external 8259As. The
INT2IINTAO and INT3IINTAI pins can serve either of two functions. Outside cascade mode,
they serve as external interrupt inputs. In cascade mode, they serve as interrupt acknowledge outputs. INTAO is the acknowledge for INTO, and INTAI is the acknowledge for INTI. (See Figure
8-2.)
The INT2IINTAO and INT3/INTAl pins are inputs after reset until the pins are confiugred as outputs. The pull up resistors ensure that the INTA pins never float (which would cause a spurious
interrupt acknowledge to the 8259A). The value of the resistors must be high enough to prevent
excessive loading on the pins.

8-7

INTERRUPT CONTROL UNIT

INT
8259A
or
82C59A

INTO
VCC
-r

INTA

INTAO
Interrupt
Control
Unit

INT
8259A
or
82C59A

INT1
VCC

-INTA

:>
~

INTA1

A1211·AO

Figure 8-2. Using External 8259A Modules in Cascade Mode
8.2.3.1

Special Fully Nested Mode

Special fully nested mode is an optional feature normally used with cascade mode. It is applicable
only to INTO and INTI. In special fully nested mode, an interrupt request is serviced even if its
In-Service bit is set.
In cascade mode, an 8259A controls up to eight external interrupts that share a single interrupt
input pin. Special fully nested mode allows the 8259A's priority structure to be maintained. For
example, assume that the CPU is servicing a low-priority interrupt from the 8259A. While the
interrupt handler is executing, the 8259A receives a higher priority interrupt from one of its sources. The 8259A applies its own priority criteria to that interrupt and asserts its interrupt to the Interrupt Control Unit. Special fully nested mode allows the higher priority interrupt to be serviced
even though the In-Service bit for that source is already set. A higher priority interrupt has preempted a lower priority interrupt, and interrupt nesting is fully maintained.
Special fully nested mode can also be used without cascade mode. In this case, it allows a single
external interrupt pin (either INTO or INTI) to preempt itself.

8-8

intet
8.2.4

INTERRUPT CONTROL UNIT

Interrupt Acknowledge Sequence

During the interrupt acknowledge sequence, the Interrupt Control Unit passes the interrupt type
to the CPU. The CPU then multiplies the interrupt type by four to derive the interrupt vector address in the interrupt vector table. ("InterruptlException Processing" on page 2-39 describes the
interrupt acknowledge sequence and Figure 2-25 on page 2-40 illustrates the interrupt vector table.)
The interrupt types for all sources are fixed and unalterable (see Table 8-2). The Interrupt Control
Unit passes these types to the CPU internally. The first external indication of the interrupt acknowledge sequence is the CPU fetch from the interrupt vector table.
In cascade mode, the external 8259A supplies the interrupt type. In this case, the CPU runs an
external interrupt acknowledge cycle to fetch the interrupt type from the 8259A (see "Interrupt
Acknowledge Bus Cycle" on page 3-25).
Table 8-2. Fixed Interrupt Types

8.2.5

Interrupt Name

Interrupt Type

limerO

limer 1

limer2

Serial Channel 0 Receive

Serial Channel 0 Transmit

INT4

INTO

INT1

INT2

INT3

Polling

In some applications, it is desirable to poll the Interrupt Control Unit. The CPU polls the Interrupt
Control Unit for any pending interrupts, and software can service interrupts whenever it is convenient. The Poll and Poll Status registers support polling.
Software reads the Poll register to get the type of the highest priority pending interrupt, then calls
the corresponding interrupt handler. Reading the Poll register also acknowledges the interrupt.
This clears the Interrupt Request bit and sets the In-Service bit for the interrupt. The Poll Status
register has the same format as the Poll register, but reading the Poll Status register does not acknowledge the interrupt.

8-9

INTERRUPT CONTROL UNIT

8.2.6

Edge and Level Triggering

~( The external interrupts (INT4:0) can be programmed for either edge or level triggering (see "In\ terruptControl Registers" on page 8-12). Both types of triggering are active high. An edge-trig) gered interrupt is generated by a zero-to-one transition on an external interrupt pin. The pin must
I,
remain high until after the CPU acknowledges the interrupt, then must go low to reset the edge,/
detection circuitry. (See the current data sheet for timing requirements.) The edge-detection cir. / cuitry must be reset to enable further interrupts to occur.

A level-triggered interrupt is generated by a valid logic one on the external interrupt pin. The pin
must remain high until after the CPU acknowledges the interrupt. Unlike edge-triggered interrupts, level-triggered interrupts will continue to occur if the pin remains high. A level-triggered
external interrupt pin must go low before the EOI command to prevent another interrupt.
NOTE

When external 8259As are cascaded into the Interrupt Control Unit, INTO and
INTI must be programmed for level-triggered interrupts.

8.2.7

Additional Latency and Response Time

The Interrupt Control Unit adds 5 clocks to the interrupt latency of the CPU. Cascade mode adds
13 clocks to the interrupt response time because the CPU must run the interrupt acknowledge bus
cycles. (See Figure 8-3 on page 8-11 and Figure 2-27 on page 2-46.)

8-10

intet~

INTERRUPT CONTROL UNIT

Clocks
Interrupt presented to control unit .......................~
5
Interrupt presented to CPU .......................~
INTA

First instruction fetch
from interrupt routine

4 }

:~~~

IDLE
READ IP
IDLE
READCS
IDLE
PUSH FLAGS
IDLE
PUSH CS
PUSH IP
IDLE

4
3 (5 if not cascade mode)
4
4
4
3
4
4
5

......................................

Cascade Mode Only

Total 55
A1212·AO

Figure 8-3. Interrupt Control Unit Latency and Response Time

8.3

PROGRAMMING THE INTERRUPT CONTROL UNIT

Table 8-3 lists the Interrupt Control Unit registers with their Peripheral Control Block offset addresses. The remainder of this section describes the functions of the registers.
Table 8-3. Interrupt Control Unit Registers
Register Name

Offset Address

INT3 Control

1EH

INT2 Control

1CH

INn Control

1AH

INTO Control

18H

INT4 Control

16H

Serial Control

14H

Timer Control

12H

Interrupt Status

10H

Interrupt Request

OEH

8-11

INTERRUPT CONTROL UNIT

Table 8-3. Interrupt Control Unit Registers (Continued)
Register Name
In-Service
Priority Mask
Interrupt Mask
Poll Status
Poll
EOI

8.3.1

Offset Address

OCH
OAH
08H
06H
04H
02H

Interrupt Control Registers

Each interrupt source has its own Interrupt Control register. The Interrupt Control register allows
you to define the behavior of each interrupt source. Figure 8-4 shows the registers for the timers
and serial channel, Figure 8-5 shows the registers for INT4:2, and Figure 8-6 shows the registers
for INTO and INTI.
All Interrupt Control registers have a three-bit field (PM2:0) that defines the priority level for the
interrupt source and a mask bit (MSK) that enables or disables the interrupt source. The mask bit
is the same as the one in the Interrupt Mask register. Modifying a bit in either register also modifies that same bit in the other register.
The Interrupt Control registers for the external interrupt pins also have a bit (LVL) that selects
level-triggered or edge-triggered mode for that interrupt. (See "Edge and Level Triggering" on
page 8-10.)
The Interrupt Control registers for the cascadable external interrupt pins (INTO and INTI) have
two additional bits to support the external 8259As. The CAS bit enables cascade mode, and the
SFNM bit enables special fully nested mode.

8-12

INTERRUPT CONTROL UNIT

Interrupt Control Register (intemal sources)

TCUCON, SCUCON,

Control register for the internal interrupt sources

o
M
S
K

P
M
2

P
M
1

P
M
0

A121~AO

Bit
Mnemonic

Bit Name

Reset

State

Function

MSK

Interrupt
Mask

Clear to enable Interrupts from this source.

PM2:0

Priority
Level

111

Defines the priority level for this source.

NOTE: Reserved register bits are shown with gray shading. Reserved bHs must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 8-4. Interrupt Control Register for Internal Sources

8-13

int'et

INTERRUPT CONTROL UNIT

Interrupt Control Register (non-cascadable pins)

12CON, 13CON, 14CON

Control register for the non-cascadable external
internal interrupt pins

o
M
S
K

P
M
2

P
M
1

P
M
0

A1214-AO

Bit
Mnemonic
LVL

Bit Name
Level-trigger

Reset
State
0

Function
Selects the interrupt triggering mode:

o= edge triggering

1 = level triggering.

MSK

Interrupt
Mask

PM2:0

Priority
Level

NOTE:

Clear to enable interrupts from this source.

111

Defines the priority level for this source.

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 8-5. Interrupt Control Register for Noncascadable External Pins

8-14

int:et

INTERRUPT CONTROL UNIT

Interrupt Control Register (cascadable pins)

IOCON, 11 CON

Control register
interrupt pins

for

the

C
A
S

L
V
L

cascadable

external

0
S
F
N
M

M
S
K

P
M
2

P
M
1

P
M
0

A1215-AO

Bit
Mnemonic

Bit Name

Reset
State

Function

SFNM

Special
Fully
Nested
Mode

Set to enable special fully nested mode.

CAS

cascade
Mode

Set to enable cascade mode.

LVL

Level-trigger

Selects the interrupt triggering mode:

o =edge triggering
1

=level triggering.

The LVL bH must be set when extemal 8259As
are cascaded Into the Interrupt Control Unit.
MSK

Interrupt
Mask

Clear to enable interrupts from this source.

PM2:0

Priority
Level

111

Defines the priority level for this source.

NOTE:

Reserved register bits are shown with gray shading. Reserved bHs must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 8-6. Interrupt Control Register for Cascadable Interrupt Pins

8-15

INTERRUPT CONTROL UNIT

8.3.2

Interrupt Request Register

The Interrupt Request register (Figure 8-7) has one bit for each interrupt source. When a source
requests an interrupt, its Interrupt Request bit is set (without regard to whether the interrupt is
masked). The Interrupt Request bit is cleared when the interrupt is acknowledged. An external
interrupt pin must remain asserted until its interrupt is acknowledged. Otherwise, the Interrupt
Request bit will be cleared, but the interrupt will not be serviced.

Interrupt Request Register

REQST

Stores pending interrupt requests

IIII
Bit
Mnemonic

Bit Name

Reset
State

N E
T

321

S
R

A12()6.AQ

Function

INT3:0,INT4

External
Interrupts

0000 0

A bit is set to indicate a pending interrupt from
the corresponding external interrupt pin.

SER

Serial
Channel 0
Interrupt

This bit is set to indicate a pending interrupt
from serial channel 0 (either a receive or a
transmit interrupt).

TMR

Timer
Interrupt

This bit is set to indicate a pending interrupt
from one of the timers.

NOTE:

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 8-7. Interrupt Request Register

8-16

INTERRUPT CONTROL UNIT

8.3.3

Interrupt Mask Register

The Interrupt Mask register (Figure 8-8) contains a mask bit for each interrupt source. This register allows you to mask (disable) individual interrupts. Set a mask bit to disable interrupts from
the corresponding source. The mask bit is the same as the one in the Interrupt Control register.
Modifying a bit in either register also modifies that same bit in the other register.

Interrupt Mask Register

IMASK

Masks individual interrupt sources

0
I
N
T
3

I
N
T

I
N
T
1

I
N
T
0

I
N
T
4

S
E
R

A1207-AO

Bit
Mnemonic

Bit Name

Reset
State

Function

INT3:0,INT4

External
Interrupt
Mask

-eeee-eF'h.) Ih

Set a bit to mask (disable) interrupt requests
from the corresponding extemallnterrupt pin.

SER

Serial
Channel 0
Interrupt
Mask

Set to mask (disable) interrupt requests from
serial channel O.

TMR

Timer
Interrupt
Mask

Set to mask (disable) interrupt requests from
the timers.

NOTE:

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 8-8. Interrupt Mask Register

(f'Z.-/t4/fS- ~)

8-17

intet~

INTERRUPT CONTROL UNIT

8.3.4

Priority Mask Register

The Priority Mask register (Figure 8-9) contains a three-level field that holds a priority value.
This register allows you to mask interrupts based on their priority levels. Write a priority value to
the PM2:0 field to specify the lowest priority interrupt to be serviced. This disables (masks) any
interrupt source whose priority is lower than the PM2:0 value. After reset, the Priority Mask register is set to the lowest priority (seven), which enables all interrupts of any priority.

Priority Mask Register

PRIMSK

Masks lower-priority interrupt sources

IIII
Bit
Mnemonic
PM2:0

NOTE:

Bit Name
Priority
Mask

Reset
State

111

P
P
P
M M M
210

A1216-AO

Function
,

Defines a priority-based interrupt mask.
Interrupts whose priority is lower than this value
are masked.

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 8-9. Priority Mask Register

8.3.5

In-Service Register

The In-Service register has a bit for each interrupt source. The bits indicate which source's interrupt handlers are currently executing. The In-Service bit is set when an interrupt is acknowledged; the interrupt handler must clear it with an End-of-Interrupt (EO!) command. The Interrupt
Control Unit uses the In-Service rtbgister to support interrupt nesting.

8-18

intel~

INTERRUPT CONTROL UNIT

In-Service Register

INSERV

Indicates which interrupt handlers are in process

IIII
Bit
Mnemonic

Bit Name

Reset
State

N N N N
T T T T

N E
R

A1204-AO

Function

INT3:0,INT4

External
Interrupt InService

0000 0

A bit is set to indicate that the corresponding
external interrupt is being serviced_

SER

Serial
Channel 0
Interrupt InService

This bit Is set to indicate that a serial channel
interrupt is being serviced.

TMR

Timer
Interrupt InService

This bit is set to indicate that a timer interrupt Is
being serviced.

NOTE:

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 8-10. In-Service Register

8.3.6

Poll and Poll Status Registers

The Poll and Poll Status registers allow you to poll the Interrupt Control Unit and service interrupts through software. You can read these registers to determine whether an interrupt is pending
and, if so, the interrupt type. The registers contain identical information, but reading them produces different results.

8-19

intet~

INTERRUPT CONTROL UNIT

Reading the Poll register (Figure 8-11) acknowledges the pending interrupt, just as if the CPU
had started the interrupt vectoring sequence. The Interrupt Control Unit updates the Interrupt Request, In-Service, Poll, and Poll Status registers, as it does in the normal interrupt acknowledge
sequence. However, the processor does not run an interrupt acknowledge sequence or fetch the
vector from the vector table. Instead, software must read the interrupt type and execute the proper
routine to service the pending interrupt.
Reading the P~llStatus register (Figure 8-12) will merely transmit the status of the polling bits
without modifying any of the other Interrupt Controller registers.

Poll Register

POLL

Read to check for and acknowledge pending
interrupts when polling

v v v

321

A120B-AO

Bit
Mnemonic

Bit Name

Reset
State

Function

IREO

Interrupt
Request

This bit is set to indicate a pending interrupt.

VT4:0

Vector Type

Contains the interrupt type of the highest
priority pending interrupt.

NOTE:

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 8-11. Poll Register

8·20

INTERRUPT CONTROL UNIT

Poll Status Register

POLLSTS

Read to check for pending interrupts when polling

V
T

v
T

V
T

A1209-AO

Bit
Mnemonic

Bit Name

Reset
State

Function

IREO

Interrupt
Request

This bit is set to indicate a pending interrupt.

VT4:0

Vector Type

Contains the interrupt type of the highest
priority pending interrupt.

NOTE:

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 8-12. Poll Status Register

8.3.7

End-ot-Interrupt (EOI) Register

The End-of-Interrupt register (Figure 8-13) issues an End-of-Interrupt (EOI) command to the Interrupt Control Unit, which clears the In-Service bit for the associated interrupt. An interrupt handler typically ends with an EOI command. There are two types of EOI commands: nonspecific
and specific. A nonspecific EOI simply clears the In-Service bit of the highest priority interrupt.
To issue a nonspecific EOI command, set the NSPEC bit. (Write 8000H to the EO! register.)
A specific EOI clears a particular In-Service bit. To issue a specific EOI command, clear the
NSPEC bit and write the VT4:0 bits with the interrupt type of the interrupt whose In-Service bit
you wish to clear. For example, to clear the In-Service bit for INT2, write OOOEH to the EOI register. The timer interrupts share an In-Service bit. To clear the In-Service bit for any timer interrupt with a specific EOI, write 0OO8H (interrupt type 8) to the EOI register.

8-21

intet,

INTERRUPT CONTROL UNIT

End-of-Interrupt Register

EOI

Used to issue an EOI command

v v v

T
T
321

A121()'AO

Bit
Mnemonic

Bit Name

Reset
State

Function

NSPEC

Nonspecific
EOI

Set to issue a nonspecific EOL

VT4:0

Interrupt
Type

00000

Write with the interrupt type of the interrupt
whose In-Service bit is to be cleared.

NOTE:

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logiC zero to ensure compatibility with future Intel products.

Figure 8-13. End-ot-Interrupt Register

8.3.8

Interrupt Status Register

The Interrupt Status register (Figure 8-14) contains one bit for each interrupt that shares an interrupt source and one bit for the nonmaskable interrupt (NMI). A bit is set to indicate a pending
interrupt and is cleared when the interrupt request is acknowledged. Any number of bits can be
set at anyone time.

8-22

intet

INTERRUPT CONTROL UNIT

Interrupt Status Register

INTSTS

Indicates pending NMI or shared-source interrupts

0
S
R
X

T
M
R

T
M
R
1

T
M
R

A1205-AO

Bit
Mnemonic

Bit Name

Reset
State

Function

NMI

Nonmaskable
Interrupt

This bit is set to indicate a pending NMI.

STX

Serial
Transmit

This bit is set to indicate a pending serial
transmit interrupt.

SRX

Serial
Receive

This bit is set to indicate a pending serial
receive interrupt.

TMR2:0

Timer

A bit is set to indicate a pending interrupt from
the corresponding timer.

NOTE:

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 8-14. Interrupt Status Register

8.3.9

Initializing the Interrupt Control Unit

Follow these steps to initialize the Interrupt Control Unit.
1.

Determine which interrupt sources you want to use.

Determine whether to use the default priority scheme or devise your own.

8-23

INTERRUPT CONTROL UNIT

Program the Interrupt Control register for each interrupt source.
- For external interrupt pins, select edge or level triggering.
-For INTO or INTI, enable cascade mode, special fully nested mode, or both, if you
wish to use them.
- If you are using a custom priority scheme, program the priority level for each interrupt
source.

Program the Priority Mask with a priority mask level, if you wish to mask interrupts based
on priority. (The default is level seven, which enables all interrupt levels.)

Set the mask bit in the Interrupt Mask register for any interrupts that you wish to disable.

Example 8-1 shows sample code to initialize the Interrupt Control Unit.
$modl86
name
;This routine configures the interrupt controller to provide two cascaded
;interrupt inputs (through an external 8259A connected to INTO and INTAO#)
;and two direct interrupt inputs connected to INTl and INT3. The default
;priorities are used.
;The example assumes that the register addresses have been properly defined.
code

segment
assume cs:code
proc near
push dx
push ax
mov ax,OllOlllB
mov dx,IOCON
out dx,ax
mov ax,OlOOllOlB
mov dx,IMASK
out dx,ax
pop ax
pop dx
ret
endp
ends
end

;cascade mode, priority seven
;INTO control register
;unmask INTl and INT3

Example 8-1. Initializing the Interrupt Control Unit

8-24

intet

Timer/Counter Unit

intet~
CHAPTER 9
TIMER/COUNTER UNIT
The Timer/Counter Unit can be used in many applications. Some of these applications include a
real-time clock, a square-wave generator and a digital one-shot. All of these can be implemented
in a system design. A real-time clock can be used to update time-dependent memory variables. A
square-wave generator can be used to provide a system clock tick for peripheral devices. (See
"Timer/Counter Unit Application Examples" on page 9-17 for code examples that configure the
Timer/Counter Unit for these applications.)

9.1

FUNCTIONAL OVERVIEW

The Timer/Counter Unit is composed of three independent 16-bit timers (see Figure 9-1). The operation of these timers is independent of the CPU. The internal TImer/Counter Unit can be modeled as a single counter element, time-multiplexed to three register banks. The register banks are
dual-ported between the counter element and the CPU. During a given bus cycle, the counter element and CPU can both access the register banks; these accesses are synchronized.
The Timer/Counter Unit is serviced over four clock periods, one timer during each clock, with an
idle clock at the end (see Figure 9-2). No connection exists between the counter element's sequencing through timer register banks and the Bus Interface Unit's sequencing through T-states.
Timer operation and bus interface operation are asynchronous. This time-multiplexed scheme results in a delay of 2Yz to 6Y2 CLKOUT periods from timer input to timer output.
Each timer keeps its own running count and has a user-defined maximum count value. Timers 0
and 1 can use one maximum count value (single maximum count mode) or two alternating maximum count values (dual maximum count mode). TImer 2 can use only one maximum count value. The control register for each timer determines the counting mode to be used. When a timer is
serviced, its present count value is incremented and compared to the maximum count for that timer. If these two values match, the count value resets to zero. The timers can be configured either
to stop after a single cycle or to run continuously.
Timers 0 and 1 are functionally identical. Figure 9-3 illustrates their operation. Each has a latched,
synchronized input pin and a single output pin. Each timer can be clocked internally or externally.
Internally, the timer can either increment at v.. CLKOUT frequency or be prescaled by Timer 2.
A timer that is prescaled by Timer 2 increments when Timer 2 reaches its maximum count value.

9-1

int'et

TIMER/COUNTER UNIT

TO In

T1 In

Transition Latch/
Synchronizer

TO
CPU

Counter
Element

Out

T1
Out

CPU
Clock----'
A1292-0A

Figure 9-1. Timer/Counter Unit Block Diagram

9-2

TIMER/COUNTER UNIT

Timer 0 Timer 1 Timer 2
Timer 0 TImer 1 Timer 2
Serviced Serviced Serviced Dead Serviced Serviced Serviced Dead

,.....-'

..........,...."'"

TOIN

T11N
TOOUT
T10UT
NOTES:
1. TOIN resolution time (setup time met).
2. T1IN resolution time (setup time not met).
3. Modified count value written into Timer 0 count register.
4. T1IN resolution time, count value written into Timer 1 count register.
5. T1IN resolution time.
A1293-0A

Figure 9·2. Counter Element Multiplexing and Timer Input Synchronization

9-3

TIMER/COUNTER UNIT

A1294-0A

Figure 9-3. Timers 0 and 1 Flow Chart

9-4

intet

TIMER/COUNTER UNIT

A1295-0A

Figure 9-3. Trmers 0 and 1 Flow Chart (Continued)

(1?'/'Lf/'f" I:.~)

9-5

TIMER/COUNTER UNIT

When configured for internal clocking, the Timer/Counter Unit uses the input pins either to enable timer counting or to retrigger the associated timer. Externally, a timer increments on low-tohigh transitions on its input pin (up to 1;4 CLKOUT frequency).
Timers 0 and 1 each have a single output pin. Timer output can be either a single pulse, indicating
the end of a timing cycle, or a variable duty cycle wave. These two output options correspond to
single maximum count mode and dual maximum count mode, respectively (Figure 9-4). Interrupts can be generated at the end of every timing cycle.
Timer 2 has no input or output pins and can be operated only in single maximum count mode (Figure 9-4). It can be used as a free-running clock and as a prescaler to Timers 0 and 1. Timer 2 can
be clocked only internally, at 1;4 CLKOUT frequency. Timer 2 can also generate interrupts at the
end of every timing cycle.

Maxcount A

Dual Maximum
Count Mode

MaxcountA

Maxcount B

•
One CPU
Clock

•

Single Maximum
Count Mode
A1296-0A

Figure 9-4. Timer/Counter Unit Output Modes

9.2

PROGRAMMING THE TIMER/COUNTER UNIT

Each timer has three registers: a Timer Control register (Figure 9-5 and Figure 9-6), a Timer
Count register (Figure 9-7) and a Timer Maxcount Compare register (Figure 9-8). Timers 0 and
1 also have access to an additional Maxcount Compare register. The Timer Control register controls timer operation. The Timer Count register holds the current timer count value, and the Maxcount Compare register holds the maximum timer count value.

9-6

intet

TIMER/COUNTER UNIT

Timer 0 and 1 Control Registers

TOCON, T1CON

Defines Timer 0 and 1 operation.

15
E
N

I
N
H

I
N
T

M R
C T

R
I
U

E
X
T

A
L
T

C
0
N

A1297-0A

Bit
Mnemonic

Bit Name

Reset
State

Function

Enable

Set to enable the timer. This bit can be written only
when the INH bit is set.

INH

Inhibit

Set to enable writes to the EN bit. Clear to ignore
writes to the EN bit. The INH bit is not stored; it
always reads as zero.

INT

Interrupt

Set to generate an interrupt request when the Count
register equals a Maximum Count register. Clear to
disable interrupt requests.

RIU

Indicates which compare register is in use. When set,
the current compare register is Maxcount Compare B;
when clear, it is Maxcount Compare A.

Maximum
Count

This bit is set when the counter reaches a maximum
count. The MC bit must be cleared by writing to the
Timer Control register. This is not done automatically. If MC is clear, the counter has not reached a
maximum count.

NOTE:

Reserved register bits are shown with gray shading. Reserved bits must be written to a
logic zero to ensure compatibility with future Intel products.

Figure 9-5. Timer 0 and Timer 1 Control Registers

9-7

TIMER/COUNTER UNIT

Timer 0 and 1 Control Registers

TOCON, T1 CON

Defines Timer 0 and 1 operation.

I
N

Bit
Mnemonic

I
N
T

R
I
U

IIII

Bit Name

Reset
State

R
T
G

E
X
T

A
L
T

C
0
N
T

A1297-0A

Function

RTG

Retrigger

This bit specifies the action caused by a low-to-high
transition on the TMR INx input. Set RTG to reset the
count; clear RTG to enable counting. This bit is
ignored with external clocking (EXT=1).

Prescaler

Set to increment the timer when Timer 2 reaches its
maximum count. Clear to increment the timer at ¥I
CLKOUT. This bit is ignored with external clocking
(EXT=1).

EXT

External
Clock

Set to use external clock; clear to use internal clock.
The RTG and P bits are ignored with external clocking
(EXT set).

ALT

Alternate
Compare
Register

This bit controls whether the timer runs in single or
dual maximum count mode (see Figure 9-4 on page
9-6). Set to specify dual maximum count mode; clear
to specify single maximum count mode.

CONT

Continuous
Mode

Set to cause the timer to run continuously. Clear to
disable the counter (clear the EN bit) after each
counting sequence.

NOTE:

Reserved register bits are shown with gray shading. Reserved bits must be written to a
logic zero to ensure compatibility with future Intel products.

Figure 9-5. Timer 0 and Timer 1 Control Registers (Continued)

9-8

TIMER/COUNTER UNIT

Timer 2 Control Register

T2CON

Defines Timer 2 operation.

15
E
N

I
N

Al:t\111-UA

Bit
Mnemonic

Bit Name

Reset
State

Function

Enable

Set to enable the timer. This bit can be written
only when the INH bit is set.

INH

Inhibit

Set to enable writes to the EN bit. Clear to
ignore writes to the EN bit. The INH bit is not
stored; it always reads as zero.

INT

Interrupt

Set to generate an interrupt request when the
Count register equals a Maximum Count
register. Clear to disable interrupt requests.

Maximum
Count

This bit is set when the counter reaches a
maximum count. The Me bit must be cleared
by writing to the Timer Control register. This
is not done automatlca"y. If MC Is clear, the
counter has not reached a maximum count.

CONT

Continuous
Mode

Set to cause the timer to run continuously.
Clear to disable the counter (clear the EN bit)
after each counting sequence.

NOTE:

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 9-6. Timer 2 Control Register

9-9

infel~

TIMER/COUNTER UNIT

Timer Count Register

TOCNT, T1 CNT, T2CNT

Contains the current timer count.

15
T
C
1
5

T
C
1

T
C
1
1

T
C
1
0

T
C
9

T
C

T
C
5

T
C

T
C
1

T
C
0

A1299-0A

Bit
Mnemonic
TC15:0

Bit Name
Timer Count
Value

Reset
State

XXXXH

Function
Contains the current count of the associated
timer_

Figure 9-7. Timer Count Registers

9·10

TIMER/COUNTER UNIT

Timer Maxcount Compare Register

TOCMPA, TOCMPB, T1CMPA, T1CMPB, T2CMPA

Contains timer maximum count value.

15
T
C
1
5

T
C
1

T
C
1
1

T
C
1
0

T
C

T
C
7

T
C

T
C
5

T
C

T
C
1

T
C
0

A1300-0A

Bit
Mnemonic
TC15:0

Bit Name
Timer
Compare
Value

Reset
State

XXXXH

Function
Contains the maximum value a timer will count
to before resetting its Count register to zero_

Figure 9·8. Timer Maxcount Compare Registers

9.2.1

Initialization Sequence

When initializing the Timer/Counter Unit, the following sequence is suggested:
1.

If timer interrupts will be used, program interrupt vectors into the Interrupt Vector Table.

Clear the Timer Count register. This must be done before the timer is enabled because
the count register is undefined at reset Clearing the count register ensures that counting
begins at zero.

Write the desired maximum count value to the Timer Maxcount Compare register. For
dual maximum count mode, write a value to both Maxcount Compare A and B.
Program the Timer Control register to enable the timer. When using Timer 2 to prescale
another timer, enable Timer 2 last If Timer 2 is enabled first, it will be at an unknown
point in its timing cycle when the timer to be prescaled is enabled. This results in an
unpredictable duration of the first timing cycle for the prescaled timer.

9-11

int"et

TIMER/COUNTER UNIT

9.2.2

Clock Sources

The 16-bit Timer Count register increments once for each timer event. A timer event can be a lowto-high transition on a timer input pin (Timers 0 and 1), a pulse generated every fourth CPU clock
(all timers) or a timeout of Timer 2 (Timers 0 and 1). Up to 65536 (2 16) events can be counted.
Timers 0 and 1 can be programmed to count low-to-high transitions on their input pins as timer
events by setting the External (EXT) bit in their control registers. Transitions on the external pin
are synchronized to the CPU clock before being presented to the timer circuitry. The timer counts
transitions on this pin. The input signal must go low, then high, to cause the timer to increment.
The maximum count-rate for the timers is ':4 the CPU clock rate (measured at CLKOUT) because
the timers are serviced only once every four clocks.
All timers can use transitions of the CPU clock as timer events. For internal clocking, the timer
increments every fourth CPU clock due to the counter element's time-multiplexed servicing
scheme. Timer 2 can use only the internal clock as a timer event.
Timers 0 and 1 can also use Timer 2 reaching its maximum count as a timer event. In this configuration, Timer 0 or Timer 1 increments each time Timer 2 reaches its maximum count. See Table
9-1 for a summary of clock sources for Timers 0 and 1. Timer 2 must be initialized and running
in order to increment values in other timer/counters.
Table 9-1. Timer 0 and 1 Clock Sources

9.2.3

EXT

Timer clocked internally at

Timer clocked internally. prescaled by Timer 2.

Timer clocked externally at up to

Clock Source
~

CLKOUT frequency.
~

CLKOUT frequency.

Counting Modes

All timers have a Timer Count register and a Maxcount Compare A register. Timers 0 and 1 also
have access to a second Maxcount Compare B register. Whenever the contents of the Timer Count
register equal the contents of the Maxcount Compare register, the count register resets to zero.
The maximum count value will never be stored in the count register. This is because the counter
element increments, compares and resets a timer in one clock cycle. Therefore, the maximum value is never written back to the count register. The Maxcount Compare register can be written at
any time during timer operation.
The timer counting from its initial count (usually zero) to its maximum count (either Maxcount
Compare A or B) and resetting to zero defines one timing cycle. A Maxcount Compare value of
oimplies a maximum count of 65536, a Maxcount Compare value of 1 implies a maximum count
of 1, etc.

9·12

intet

TIMER/COUNTER UNIT

Only equivalence between the Timer Count and Maxcount Compare registers is checked. The
count does not reset to zero if its value is greater than the maximum count. If the count value exceeds the Maxcount Compare value, the timer counts to OFFFFH, increments to zero, then counts
to the value in the Maxcount Compare register. Upon reaching a maximum count value, the Maximum Count (MC) bit in the Timer Control register sets. The MC bit must be cleared by writing
to the Timer Control register. This is not done automatically.
The Timer/Counter Unit can be configured to execute different counting sequences. The timers
can operate in single maximum count mode (all timers) or dual maximum count mode (Timers 0
and 1 only). They can also be programmed to run continuously in either of these modes. The Alternate (ALT) bit in the Timer Control register determines the counting modes used by Timers 0
and 1.
All timers can use single maximum count mode, where only Maxcount Compare A is used. The
timer will count to the value contained in Maxcount Compare A and reset to zero. Timer 2 can
operate only in this mode.
Timers 0 and 1 can also use dual maximum count mode. In this mode, Maxcount Compare A and
Maxcount Compare B are both used. The timer counts to the value contained in Maxcount Compare A, resets to zero, counts to the value contained in Maxcount Compare B, and resets to zero
again. The Register In Use (RIU) bit in the TImer Control register indicates which Maxcount
Compare register is currently in use.
The timers can be programmed to run continuously in single maximum count and dual maximum
count modes. The Continuous (CaNT) bit in the Timer Control register determines whether a
timer is disabled after a single counting sequence.
9.2.3.1

Retriggering

The timer input pins affect timer counting in three ways (see Table 9-2). The programming of the
External (EXT) and Retrigger (RTG) bits in the Timer Control register determines how the input
signals are used. When the timers are clocked internally, the RTG bit determines whether the input pin enables timer counting or retriggers the current timing cycle.
Table 9-2. Timer Retriggering

Timer Operation

EXT

RTG

Timer counts internal events, if input pin remains high.

Timer counts internal events; count resets to zero on every low-to-high transition on
the input pin.

Timer input acts as clock source.

9-13

TIMER/COUNTER UNIT

When the EXT and RTG bits are clear, the timer counts internal timer events. In this mode, the
input is level-sensitive, not edge-sensitive. A low-to-high transition on the timer input is not required for operation. The input pin acts as an external enable. If the input is high, the timer will
count through its sequence, provided the timer remains enabled.
When the EXT bit is clear and the RTG bit is set, every low-ta-high transition on the timer input
pin causes the Count register to reset to zero. After the timer is enabled, counting begins only after
the first low-to-high transition on the input pin. If another low-to-high transition occurs before
the end of the timer cycle, the timer count resets to zero and the timer cycle begins again. In dual
maximum count mode, the Register In Use (RIU) bit does not clear when a low-to-high transition
occurs. For example, if the timer retriggers while Maxcount Compare B is in use, the timer resets
to zero and counts to maximum count B before the RIU bit clears. In dual maximum count
mode, the timer retriggering extends the use of the current Maxcount Compare register.

9.2.4

Pulsed and Variable Duty Cycle Output

Timers 0 and 1 each have an output pin that can perform two functions. First, the output can be a
single pulse, indicating the end of a timing cycle (single maximum count mode). Second, the output can be a level, indicating the Maxcount Compare register currently in use (dual maximum
count mode). The output occurs one clock after the counter element services the timer when the
maximum count is reached (see Figure 9-9).
With external clocking, the time between a transition on a timer input and the corresponding transition of the timer output varies from 2'12 to 6'12 clocks. This delay occurs due to the time-multiplexed servicing scheme of the Timer/Counter Unit. The exact timing depends on when the input
occurs relative to the counter element's servicing of the timer. Figure 9-2 on page 9-3 shows the
two extremes in timer output delay. Timer 0 demonstrates the best possible case, where the input
occurs immediately before the timer is serviced. Timer 1 demonstrates the worst possible case,
where the input is latched, but the setup time is not met and the input is not recognized until the
counter element services the timer again.
In single maximum count mode, the timer output pin goes low for one CPU clock period (see Figure 9-4 on page 9-6). This occurs when the count value equals the Maxcount Compare A value.
If programmed to run continuously, the timer generates periodic pulses.

9-14

int:et,

TIMER/COUNTER UNIT

Timer 0
Serviced

Internal Count Value

Maxcount -1

TxOUT Pin

NOTE: 1. TCLOV1
Al301-0A

Figure 9-9. TxOUT Signal Timing

In dual maximum count mode, the timer output pin indicates which Maxcount Compare register
is currently in use. A low output indicates Maxcount Compare B, and a high output indicates
Maxcount Compare A (see Figure 9-4 on page 9-6). If programmed to run continuously, a repetitive waveform can be generated. For example, if Maxcount Compare A contains 10, Maxcount
Compare B contains 20, and CLKOUT is 12.5 MHz, the timer generates a 33 percent duty cycle
waveform at 104 KHz. The output pin always goes high at the end of the counting sequence (even
if the timer is not programmed to run continuously).

9.2.5

Enabling/Disabling Counters

Each timer has an Enable (EN) bit in its Control register to allow or prevent timer counting. The
Inhibit (INH) bit controls write accesses to the EN bit. Timers 0 and 1 can be programmed to use
their input pins as enable functions also. If a timer is disabled, the count register does not increment when the counter element services the timer.
The Enable bit can be altered by programming or the timers can be programmed to disable themselves at the end of a counting sequence with the Continuous (CaNT) bit. If the timer is not programmed for continuous operation, the Enable bit automatically clears at the end of a counting
sequence. In single maximum count mode, this occurs after Maxcount Compare A is reached. In
dual maximum count mode, this occurs after Maxcount Compare B is reached (Timers 0 and 1
only).

9-15

TIMER/COUNTER UNIT

intele

The input pins for Timers 0 and 1 provide an alternate method for enabling and disabling timer
counting. When using internal clocking, the input pin can be programmed either to enable the timer or to reset the timer count, depending on the state of the Retrigger (RTG) bit in the control register. When used as an enable function, the input pin either allows (input high) or prevents (input
low) timer counting. To ensure recognition of an input level, it must be valid for four CPU clocks.
This is due to the counter element's time-multiplexed servicing scheme for the timers.

9.2.6

Timer Interrupts

{ All timers can generate internal interrupt requests. Although all three timers share a single inter) rupt request to the CPU, each has its own vector location and internal priority. Timer 0 has the
I highest interrupt priority and Timer' 2 has the lowest.
Timer Interrupts are enabled or disabled by the Interrupt (!NT) bit in the Timer Control register.
If enabled, an interrupt is generated every time a maximum count value is reached. In dual maximum count mode, an interrupt is generated each time the value in Maxcount Compare A or Maxcount Compare B is reached. If the interrupt is disabled after a request has been generated, but
before a pending interrupt is serviced, the interrupt request remains active (the Interrupt Controller latches the request). If a timer generates a second interrupt request before the CPU services
the first interrupt request, the first request is lost.

9.2.7

Programming Considerations

Timer registers can be read or written whether the timer is operating or not. Since processor accesses to timer registers are synchronized with counter element accesses, a half-modified count
register will never be read.

~ Whe~ Timer 0

and Timer 1 use an internal clock source, the ,input pin. ~ust be high to enable

,countmg.
)

9.3

TIMING

Certain timing considerations need to be made with the Timer/Counter Unit. These include input
setup and hold times, synchronization and operating frequency.

9.3.1

Input Setup and Hold Timings

To ensure recognition, setup and hold times must be met with respect to CPU clock edges. The
timer input signal must be valid T CHIS before the rising edge of CLKOUT and must remain valid
T CHIH after the same rising edge. If these timing requirements are not met, the input will not be
recognized until the next clock edge.

9-16

in1et
9.3.2

TIMER/COUNTER UNIT

Synchronization and Maximum Frequency

All timer inputs are latched and synchronized with the CPU clock. Because of the internal logic
required to synchronize the external signals, and the multiplexing of the counter element, the
Timer/Counter Unit can operate only up to 1A of the CLKOUT frequency. Clocking at greater frequencies will result in missed clocks.
9.3.2.1

Timer/Counter Unit Application Examples

The following examples are possible applications of the Timer/Counter Unit. They include a realtime clock, a square wave generator and a digital one-shot.

9.3.3

Real-Time Clock

Example 9-1 contains sample code to configure Timer 2 to generate an interrupt request every 10
milliseconds. The CPU then increments memory-based clock variables.

9.3.4

Square-Wave Generator

A square-wave generator can be useful to act as a system clock tick. Example 9-2 illustrates how
to configure Timer 1 to operate this way.

9.3.5

Digital One-Shot

Example 9-3 configures Timer 1 to act as a digital one-shot.

9-17

TIMER/COUNTER UNIT

$mod186
name examp1e_80186_family_timer_code
; FUNCTION:

This function sets up the timer and interrupt controller
to cause the timer to generate an interrupt every
10 milliseconds and to service interrupts to
implement a real time clock.
Timer 2 is used in this example because no input or
output signals are required.

; SYNTAX:

extern void far set_time (hour, minute, second, T2Compare)

; INPUTS:

hour - hour to set
minute - minute to
second - second to
T2Compare - T2CMPA

;OUTPUTS:

None

;NOTE:

Parameters are passed on the stack as required by
high-level languages

time to.
set time to.
set time to.
value (see note below)

For a CLKOUT of l6Mhz,
f(timer2)

T2CMPA(10ms)

l6Mhz/4
4Mhz
0.25us for T2CMPA

10ms/0.25us
10e-3/0.25e-6
40000

;substitute register offsets
T2CON
T2CMPA
T2CNT
TCUCON
EOI
INTSTS
timer_2_int

equ
equ
equ
equ
equ
equ
equ

xxxxh
xxxxh
xxxxh
xxxxh
xxxxh
xxxxh
19

;Timer 2 Control register
;Timer 2 Compare register
;Timer 2 Counter register
;Int. Control register
;End Of Interrupt register
;Interrupt Status register
;timer 2:vector type 19

data segment public 'data'
public _hour, _minute, _second, _msec
_hour
_minute
_second
_msec

db
db
db
db

?
?
?
?

data ends

Example 9-1. Configuring a Real-Time Clock

9-18

intet

TIMER/COUNTER UNIT

'lib_80186 segment public 'code'
assume cs:lib_80186, ds:data
public _set_time
_set_time proc far
push
mov

bp
bp, sp

;save caller's bp
;get current top of stack

hour
equ word ptr[bp+6]
;get parameters off stack
minute equ word ptr[bp+8]
second equ word ptr[bp+10]
T2Compare equ word ptr[bp+12]
push
push
push

ax
dx
si

;save registers used

push
xor
mov
mov
mov

ds
ax, ax
;set interrupt vector
ds, ax
si, 4*timer_2_int
word ptr ds:[si], offset

timer_2_interrupt_routine
inc
si
inc
si
mov
ds: [si], cs
pop
ds
mov
mov
mov
mov
mov
mov
mov

ax, hour
_hour, al
ax, minute
_minute, al
ax, second
_second, al
_msec, 0

;set time

mov
xor
out

dx, T2CNT

;clear Count register

ax, ax

mov
mov
out
mov
mov
out

dx,
ax,
dx,
dx,
ax,
dx,

mov
xor
out

ax, ax

dx, al
T2CMPA
T2Compare
al
T2CON
OEOO1H
al

dx, TCUCON

;set maximum count value
;see note in header above
;set up the control word:
;enable counting,
;generate interrupt on MC,
;continuous counting
;set up interrupt controller
;unmask highest priority interrupt

dx, al

Example 9-1. Configuring a Real-Time Clock (Continued)

9-19

intet

TIMER/COUNTER UNIT

sti

;enable interrupts

pop
si
pop
dx
pop
ax
pop
bp
ret
set_time endp

push
push
cmp
jae
,inc
jmp

;restore saved registers
;restore caller's bp

;save registers used

_msec, 99
bump_second
_msec
short reset_int_ctl

;has 1 sec passed?
;if above or equal ...

bump_second:
mov
cmp
jae
inc
jmp

_msec, 0
_minute, 59
bump_minute
_second
short reset_int_ctl

;reset millisecond
;has 1 minute passed?

bump_minute:
mov
cmp
j ae
inc
jmp

_second, 0
_minute, 59
bump_hour
_minute
short reset_int_ctl

;reset second
;has 1 hour passed?

bump_hour:
mov
cmp
jae
inc
jmp

-Ylinute, 0
_hour, 12
reset_hour
_hour
reset_int_ctl

;reset minute
;have 12 hours passed?

reset_hour:
mov

_hour, 1

;reset hour

dx, EOr
ax, 8000h
dx, al

;non-specific end of interrupt

mov
mov
out
pop
pop
iret

ends
end

Example 9-1. Configuring a Real-Time Clock (Continued)

9-20

TIMER/COUNTER UNIT

$mod186
name
; FUNCTION:

example_timer1_square_wave_code
This function generates a square wave of given
frequency and duty cycle on Timer 1 output pin.

SYNTAX:

extern void far clock(int mark, int space)

INPUTS:

mark - This is the mark (1) time.
space - This is the space (0) time.
The register compare value for a given time can be
easily calculated from the formula below.
Comparevalue =

OUTPUTS:

(re~ulse_width*f)/4

None

NOTE:

Parameters are passed on the stack as required by
high-level Languages

T1CMPA
T1CMPB
T1CNT
T1CON

equ
equ
equ
equ

xxxxH

;substitute register offsets

xxxxH

xxxxH
xxxxH

lib_80186
segment public 'code'
assume cs:lib_80186
public
_clock

_clock
proc far

push
mov
_space
_mark

bp
bp, sp
equ word ptr[bp+6]
equ word ptr[bp+8]

;save caller's bp
;get current top of stack
;get parameters off the stack

push
push
push

ax
bx
dx

;save registers that will be
;modified

mov
mov
out

dx, T1CMPA
ax, _mark
dx, al

;set mark time

mov
mov
out

dx, T1CMPB
ax, _space
dx, al

;set space time

mov
xor
out

dx, T1CNT
ax, ax
dx, al

;Clear Timer 1 Counter

mov
mov
out

dx, T1CON
ax, C003H
dx, al

;start Timer 1

Example 9-2. Configuring a Square-Wave Generator

9-21

TIMER/COUNTER UNIT

pop
pop
pop
pop
ret
_clock
lib_80186
end

dx
bx
ax

;restore saved registers

;restore caller's bp

endp
ends

Example 9-2. Configuring a Square-Wave Generator (Continued)

$mod186
name example_timerl_l_shot_code
FUNCTION:

This function generates an active-low one-shot pulse
on Timer 1 output pin.

SYNTAX:

extern void far one_shot(int CMPB);

INPUTS:

CMPB - This is the TICMPB value required to generate a
pulse of a given pulse width. This value is calculated
from the formula below,
CMPB =

(re~ulse_width*f)/4

OUTPUTS:

None

NOTE:

Parameters are passed on the stack as required by
high-level languages

TlCNT equ xxxxH
TICMPA equ xxxxH
TICMPB equ xxxxH
TICON equ xxxxH
MaxCount equ 0020H

;substitute register offsets

lib_80186
segment public 'code'
assume cs:lib_80186
public
_one_shot
push
mov

_one_shot
proc far
bp
bp, sp

;save caller's bp
;get current top of stack

Example 9-3. Configuring a Digital One-Shot

9-22

TIMER/COUNTER UNIT

_CMPB

equ word ptr [bp+6]

;get parameter off the stack

push
push
mov
xor
out
mov
mov
out
mov
mov
out
mov
mov
out

ax
dx
dx,
ax,
dx,
dx,
ax,
dx,
dx,
ax,
dx,
dx,
ax,
dx,

;save registers that will be
; modified
;Clear Timer 1 Counter

T1CNT
ax
a1
TICMPA
1
a1
T1CMPB
_CMPB
al
T1CON
C002H
al

;set time before t_shot to 0
;set pulse time

;start Timer 1

CountDown:
test
jz
and
out

in ax, dx
ax, MaxCount
CountDown
ax, not MaxCount
dx, al

;read in T1CON
;max count occurred?
;nQ: then wait
;c1ear max count bit
;update T1CON

pop
pop
pop
ret
one shot
lib_ 80186
end

dx
ax
bp

;restore saved registers
;restore caller's bp

endp
ends

Example 9-3. Configuring a Digital One-Shot (Continued)

9-23

in1:et

Serial
Communications
Unit

intet
CHAPTER 10
SERIAL COMMUNICATIONS UNIT
10.1 INTRODUCTION
The Serial Communications Unit is composed of two identical serial ports, or channels. Each serial port is independent of the other. This chapter describes the operation of a single serial port.
The serial port implements several industry-standard asynchronous communications protocols,
and it readily interfaces to many different processors over a standard serial interface. Several processors and systems can be connected to a common serial bus using a multiprocessor protocol.
The serial port also implements a simple synchronous protocol. The synchronous protocol is most
commonly used to expand the number of I/O pins with shift registers.
Features:
• Full duplex operation
• Programmable seven, eight or nine data bits in asynchronous mode
• Independent baud rate generator
• Maximum baud rate of 1116 the processor clock
• Double-buffered transmit and receive
• Clear-to-Send feature for transmission
• Break character transmission and detection
• Programmable even, odd or no parity
• Detects both framing and overrun errors
• Supports interrupt on transmit and receive

10.1.1 Asynchronous Communications
Asynchronous communications protocols allow different devices to communicate without a common reference clock. The devices communicate at a common baud rate, or bits per second. Data
is transmitted and received in frames . Aframe is a sequence of bits shifted serially onto or off the
communications line.
Each asynchronous frame consists of a start bit (always a logic zero), followed by the data bits
and a terminating stop bit. The serial port can transmit and receive seven, eight or nine data bits.
The last data bit can optionally be replaced by an even or odd parity bit. Figure 10-1 shows a typical to-bit frame.

10-1

SERIAL COMMUNICATIONS UNIT

A1274-0A

Figure 10-1. Typical10-Bit Asynchronous Data Frame

When discussing asynchronous communications, it makes sense to talk about the receive machine (RX machine) and the transmit machine (TX machine) separately. Each is completely independent. Transmission and reception can occur simultaneously, making the asynchronous
modes full-duplex.
10.1.1.1

RX Machine

The RX machine (Figure 10-2) shifts the received serial data into the receive shift register. When
the reception has completed, the data is then moved into the Serial Receive Buffer (SxRBUF)
Register. From there, the user can read the received data byte.
The RX machine samples the RXD pin, looking for a logical low (start bit) signifying the beginning of a reception. Once the logical low has been detected, the RX machine begins the receive
process. Each expected bit-time is divided into eight samples by the 8X baud clock. The RX machine takes the three middle samples and, based on a two-out-of-three majority, determines the
data bit value. This oversampling is common for asynchronous serial ports and improves noise
immunity. This majority value is then shifted into the receive shift register.
Using this method, the RX machine can tolerate incoming baud rates that differ from its own internal baud rates by 2.5% overspeed and 5.5% underspeed. These limits exceed the CCIIT extended signaling rate specifications.
A stop bit is expected by the RX machine after the proper number of data bits. When the stop bit
has been validated, the data from the shift register is copied into SxRBUF and the Receive Interrupt (RI) bit is set. Note that the stop bit is actually validated right after its middle three samples
are taken. Therefore, the data is moved into SxRBUF and the RI bit is set approximately in the
middle of the stop bit time.

10-2

ToPCS
RXD
Pin

l
@

RXD
Sampler

"'w"::I'm'"''''='::I'''m'''''''''=:J'''''''m~'=r~'',''«@m':::I=_''''"'=r"''''@''"''':::I'''''''''''''''''''':::r,,,,%m»,» ~

Shift
Clock

cO·

...

.....
0I

::D

::s
CD

I I

Channel Status Logic

::D

l>
rRI Request
Signal

0
0

3:
3:

c:
Z

.....
9

(,)

•

••

ToPCS

•

::I
SxSTS

en
c:

SERIAL COMMUNICATIONS UNIT

The RX machine can detect several error conditions that may occur during reception:
1.

Parity errors -

A parity error flag is set when the parity of the received data is incorrect.

Framing errors - If a valid stop bit is not received when expected by the RX machine, a
framing error flag is set.

Overrun errors - If SxRBUF is not read before another reception completes, the old data
in SxRBUF is overwritten and an overrun error flag is set. This indicates that data from an
earlier reception has been lost.

The RX machine also recognizes two different break characters. The shorter break character is M
bit times, where M is equal to the total number of bits (start + data + stop) in a frame. The longer
break character is 2M + 3 bit times. A break character results in at least one null (all zero) character with a framing error being received. Other error flags could be set depending on the length
of the break character and the mode of the serial port.
10.1.1.2

TX Machine

A block diagram of the TX machine is shown in Figure 10-3. The TX machine logic supports the
following features:
• parity generation (even, odd or none)
• Clear-to-Send
• break character transmission
• double-buffered operation
A transmission begins by writing a byte to the Serial Transmit Buffer (SxTBUF) Register. SxTBUF is a holding register for the transmit shift register. The contents of SxTBUF are transferred
to the transmit shift register as soon as it is empty. If no transmission is in progress (i.e., the transmit shift register is empty), SxTBUF is copied immediately to the transmit shift register. If parity
is enabled, the parity bits are calculated and appended to the transmit shift register during the
transfer. The start and stop bits are added when the data is transmitted. The Transmit Interrupt bit
(TI) is set at the beginning of the stop bit time.
Double buffering is a useful feature of the TX machine. When the transmit shift register is empty,
the user can write two sequential bytes to SxTBUF. The first byte is transmitted immediately and
the second byte is held in SxTBUF until the first byte has been transmitted.

10-4

£
@

"'11

ca"
e

...

>;!

s:
~

:J
CD

(J)

:II

Baud Clock
Transmit Shift Register

o
s:

s:
c:
z
c;

'"'"f"
.....
9

l>
r
o

(J)

::j

intet

SERIAL COMMUNICATIONS UNIT

The Transmit machine can be disabled by an external source by using the Clear-to-Send feature.
When the Clear-to-Send feature is enabled, the TX machine will not transmit until the CTS pin
is asserted. The CTS pin is level sensitive. Asserting the CTS pin before a pending transmission
for at least 1'12 clock cycles ensures that the entire frame will be transmitted. See "CTS Pin Timings" on page 10-19 for details.
The TX machine can also transmit a break character. Setting the SBRK bit forces the TXD pin
immediately low. The TXD pin remains low until the user clears SBRK. The TX machine will
continue the transmission sequence even if SBRK is set. Use caution when setting SBRK or characters will be lost.
10.1.1.3

Modes 1, 3 and 4

The three asynchronous modes of the serial ports, Modes 1, 3 and 4, operate in approximately the
same manner. Mode 1 is the 8-bit asynchronous communications mode. Each frame consists of a
start bit, eight data bits and a stop bit, as shown in Figure 10-4. When parity is used, the eighth
data bit becomes the parity bit. Both the RX and TX machines use this frame in Mode 1 with no
exceptions.
Mode 3 is the 9-bit asynchronous communications mode (see Figure 10-5). Mode 3 is the same
as Mode 1 except that a frame contains nine data bits. The ninth data bit becomes the parity bit
when the parity feature is enabled. When parity is disabled, the ninth data bit is controlled by the
user. (See "Modes 2 and 3 for Multiprocessor Communications" on page 10-14.) Mode 3 can be
used with Mode 2 for mUltiprocessor communications or alone for "8 data bits + parity" frames.
Mode 4 is the 7-bit asynchronous communications mode. Each frame consists of a start bit, seven
data bits and a stop bit, as shown in Figure 10-6. Parity is not available in Mode 4. Both the RX
and TXmachines use this frame in Mode 4 with no exceptions.

10
Stop

Bit
A1285-0A

Figure 10-4. Mode 1 Waveform

10-6

SERIAL COMMUNICATIONS UNIT

11
Stop
Bit
A1286-0A

Figure 10-5. Mode 3 Waveform

9
Stop
Bit
A1287·0A

Figure 10-6. Mode 4 Waveform
10.1.1.4

Mode 2

Asynchronous Mode 2 is referred to as the "address recognition mode." Mode 2 is used together
with Mode 3 for multiprocessor communications over a common serial link.
In Mode 2, the RX machine will not complete a reception unless the ninth data bit is a one. Any
character received with the ninth bit equal to zero is ignored. No flags are set, no interrupts occur
and no data is transferred to SxRBUF. In Mode 3, characters are received regardless of the state
of the ninth data bit. The following is brief example of using Modes 2 and 3. See "Master/Slave
Example" on page 10-28 for more information.
Assume one master serial port connects to multiple slave serial ports over a serial link. The slaves
are initially in Mode 2, and the master is always in Mode 3. The master communicates with one
sl~ve at a time. The CPU overhead of the serial communications burdens only the master and the
target slave device.
1.

The master transmits the "address" of the target slave, with the ninth bit set, over the serial
link.

All slaves receive the character and check whether that address is theirs.

The target slave switches to Mode 3; all other slaves remain in Mode 2.

The master and the target slave continue the communication with all ninth data bits equal
to zero. The other slave devices ignore the activity on the serial link.

10-7

intet

SERIAL COMMUNICATIONS UNIT

At the end of the communication, the target slave switches back to Mode 2 and waits for
another address.

The parity feature cannot be used when implementing multiprocessor communications with
Modes 2 and 3, as the ninth data bit is a control bit and cannot be used as the parity bit.

10.1.2 Synchronous Communications
The synchronous mode (Mode 0) is useful primarily with shift register-based peripheral devices.
The device outputs a synchronizing clock on TXD and transmits and receives data on RXD in 8bit frames (Figure 10-7). The serial port always provides the synchronizing clock; it can never
receive a synchronous clock on TXD. Communication in the synchronous mode is half-duplex.
The RXD pin cannot transmit and receive data at the same time. Because the serial port always
acts as the master in Mode 0, all transmissions and receptions are controlled by the serial port. In
Mode 0, the parity functions and break character detection functions are not available.

Mode 0 Transmit

Mode 0 Receive
A1289-0A

Figure 10-7. Mode 0 Waveforms

10-8

SERIAL COMMUNICATIONS UNIT

10.2 PROGRAMMING
This section describes how to program the serial port using the appropriate registers. The Serial
Receive Buffer Register (SxRBUF) is shown in Figure 10-8 and the Serial Transmit Buffer Register (SxTBUF) is shown in Figure 10-9. These registers have the same functions in any serial
port mode.

Serial Receive Buffer Register

;Register Mnemonic:

SxRBUF

Received data bytes are stored in SxRBUF.

o
R

888
7 6 5

8
4

321

Al290-0A

Bit
Mnemonic
RB7:0
NOTE:

Bit Name
Received
Data

Reset
State
0

Function
Received data byte.

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 10-S. Serial Receive Buffer Register (SxRBUF)

10-9

SERIAL COMMUNICATIONS UNIT

Serial Transmit Buffer Register

SxTBUF

Bytes are written to SxTBUF to be transmitted.

IIII
Bit
Mnemonic
TB7:0

NOTE:

Bit Name
Transmit
Data Field

B B B B

321

A1291·0A

Reset
State
0

Function
Data byte to be transmitted.

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 10-9. Serial Transmit Buffer Register (SxTBUF)

10.2.1 Baud Rates
The baud rate generator is composed of a IS-bit counter register (BxCNT) and a IS-bit compare
register (BxCMP). BxCNT (Figure 10-10) is a free-running counter that is incremented by the
baud timebase clock. The baud timebase clock can be either the internal CPU clock or an external
clock applied to the BCLK pin. BxCMP (Figure 10-11) is programmed by the user to determine
the baud rate. The most-significant bit ofBxCMP (ICLK) selects which source is used as the baud
timebase clock.
BxCNT is incremented by the baud timebase clock and compared to BxCMP. When BxCNT and
BxCMP are equal, the baud rate generator outputs a pulse and resets BxCNT. This pulse train is
the actual baud clock used by the RX and TX machines. The baud clock is eight times the baud
rate in the asynchronous modes because of the sampling requirements. The baud clock equals the
baud rate in the synchronous mode.

10-10

SERIAL COMMUNICATIONS UNIT

Baud Rate Counter Register

BxCNT

1S-bit baud rate counter value.
0

B B B
C C C
1 1 1
432

B
C
1
1

B
C
1
0

B
C
9

B
C
8

B
C
7

B
C
6

B
C

B
C
4

B
C
3

B
C
2

B
C
1

B
C
0
A1275-0A

Bit
Mnemonic
BC14:0

NOTE:

Bit Name
Baud rate
counter field

Reset
State
0

Function
Reflects current value of the baud rate counter.
NOTE: Writing to this register while the serial
port is transmitting causes indeterminate
operation.

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 10-10. Baud Rate Counter Register (BxCNT)

10-11

intet

SERIAL COMMUNICATIONS UNIT

Baud Rate Compare Register

BxCMP

.
Register Function:

Determines baud rate for the serial port.

15
I
C
L
K

B
R
1
4

B
R
1

B
R
1
1

B
R
1
0

B
R

B
R
7

B
R

B
R
4

B
R

B
R
1

B
R
0

A1276-0A

Bit
Mnemonic
ICLK

Bit Name
Internal
Clocking

Reset
State

Function
Selects the input clock:

o =BCLK is input to baud clock.
1

BR14:0

Baud Rate
Compare
Field

=CPU clock is input to baud clock.

Sets the compare value for the baud rate clock.

Figure 10-11. Baud Rate Compare Register (BxCMP)

The equations in Figure 10-12 show how to calculate the proper BxCMP value for a specific baud
rate (where Fcpu = CPU operating frequency = ~ CLKIN frequency).
Mode 0
If CPU clock is baud timebase clock:

If BCLK is baud timebase clock:

BxCMP =

BxCMP

cpu

Mode 1-4
BxCMP =

cpu

baudrate

baudrate x 8

BCLK
baud rate

BxCMP = _.=B..::C..::L:..:K_
baudrate x 8

-1

Figure 10-12. Calculating the BxCMP Value for a Specific Baud Rate

10-12

intel~

SERIAL COMMUNICATIONS UNIT

Due to internal synchronization requirements, the maximum input frequency to BCLK is one-half
the CPU operating frequency. See "BCLK Pin Timings" on page 10-19 for more information. Table 10-1 shows the correct BxCMP values for common baud rates.
Table 10-1. BxCMP Values for Typical Baud Rates and CPU Frequencies
CPU Frequency
Baud
Rate

25 MHz

20 MHz

BxCMP
Value

Error

BxCMP
Value

16 MHz

%
Error

BxCMP
Value

8 MHz

%
Error

BxCMP
Value

%
Error

19,200

80A2H

-0.14

8081H

0.16

8067H

0.16

8033H

0.16

9,600

8145H

-0.14

8103H

0.16

80CFH

0.16

8067H

0.16

4,800

828AH

0.00

8208H

-0.03

81AOH

-0.08

80CFH

0.16

2,400

8515H

0.00

8411H

-0.03

8340H

0.04

81AOH

-0.08

1,200

8A2BH

0.00

8822H

0.01

8682H

-0.02

8340H

0.04

NOTE
A zero or one value for BxCMP is illegal and results in unpredictable
operation. Programming BxCMP during a transmission or reception causes
indeterminate operation.

10.2.2 Asynchronous Mode Programming
The serial port operation is controlled by two registers. The Serial Port Control (SxCON) Register
controls the mode of operation of the serial port (see Figure 10-13). The Serial Port Status
(SxSTS) Register acts as the flags register, reporting on errors and the state of the RX and TX
machines (see Figure 10-14). Depending on the serial port mode, these registers can have different functionality. This section outlines how to use SxCON and SxSTS to obtain the desired operation from the serial port.
10.2.2.1

Modes 1, 3 and 4 for Stand-alone Serial Communications

When using these modes for their respective seven, eight or nine bit data modes, operation is fairly straightforward. The serial port must be initialized correctly (through SxCON), then SxSTS
needs to be interpreted.
To configure the serial port, first program the baud rate through the BxCMP register, then program SxCON (Figure 10-13 on page 10-16) as follows.
1.

Determine the values for M2:0 for the desired serial port mode.

If parity is used, enable it with the PEN bit. Set the sense of parity (even or odd) with the
EVN bit. Note that parity is not available in Mode 4 (seven bit data).

10-13

SERIAL COMMUNICATIONS UNIT

intel~

If the Clear-to-Send feature is used, set the CEN bit to enable it.

If receptions are desired, set the REN bit to enable the RX machine. Note the TX machine
need not be explicitly enabled.

At this point, you will be able to transmit and receive in the mode specified. Now that the serial
port is operating, you must correctly interpret its status. This is done by reading the SxSTS register (Figure 10-14 on page 10-17) and interpreting its contents. Reading SxSTS clears all bits
except the CTS and TXE bits. SxSTS must first be saved in memory and then each bit can be
interpreted individually.
The RI, TI and TXE bits indicate the condition of the transmit and receive buffers. RI and TI are
also used with the Interrupt Control Unit for interrupt-based communications. The OE, FE and
PE bits indicate any errors when a character is received. Once an error occurs, the appropriate bit
remains set until SxSTS is read. For example, assume a character is received with a parity error
(PE set) and a subsequent error-free character is received. If the SxSTS register was not read between the two receptions, the PE bit remains set.
10.2.2.2

Modes 2 and 3 for Multiprocessor Communications

Programming for multiprocessor communications is much the same as the stand-alone operation.
The only added complexity is that the ninth data bit must be controlled and interpreted correctly.
The ninth data bit is set for transmissions by setting the TB8 bit in SxCON. TB8 is cleared after
every transmission. TB8 is not double-buffered. This is usually not a problem, as very few bytes
are actually transmitted with TB8 equal to one. When writing TB8, make sure that the other bits
in SxCON are written with their appropriate value.
In Modes 2 and 3, the state of the ninth data bit can be determined by the RB8 bit in SxSTS. RB8
reflects the ninth bit for the character currently in SxRBUF. Note that the RB8 bit shares functionality with the PE bit in SxSTS. When parity is enabled, the PE bit has precedence over RB8.
10.2.2.3

Sending and Receiving a Break Character

The serial port can send as well as receive BREAK characters. A BREAK character is a long
string of zeros. To send a BREAK character, set the SBRK bit in SxCON. SBRK drives the TXD
pin immediately low, regardless of the current serial port mode. The user controls the length of
the BREAK character in software by controlling the length of time that SBRK remains set. When
writing SBRK, make sure the other bits in SxCON retain their current states.

10-14

SERIAL COMMUNICATIONS UNIT

Serial Port Control Register

SxCON

Controls serial port operating modes.

T eRE
BEE V
aNN N

P
E
N

M
2

M
1

M
0

A1277-0A

Bit
Mnemonic

Bit Name

Reset
State

Function

SBRK

Send Break

Setting SBRK drives TXD low. TXD remains low
until SBRK is cleared.

TBa

Transmitted
Bit a

TBa is the eighth data bit transmitted in modes 2
and 3.

CEN

Clear-toSend Enable

When CEN is set, no transmissions will occur until
the CTS pin is asserted.

REN

Receive
Enable

Set to enable the receive machine.

EVN

Even Parity
Select

When parity is enabled, EVN selects between even
and odd parity. Set for even, clear for odd parity.

PEN

Parily
Enable

Selting PEN enables the parity generation/checking
for alilransmissionslreceplions_

M2:0

Serial Port
Mode Field

Operaling mode for Ihe serial port channel.

NOTE:

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0

1
0
1

Mode
Synchronous ModeO
10-Bil Asynch Mode1
11-Bil Asynch Mode2
11-Bil Asynch Mode3
9-Bit Asynch Mode4
Reserved
Reserved
Reserved

Reserved register bits are shown with gray shading. Reserved bils must be written to
a logic zero to ensure compalibility wilh future Inlel producls.

Figure 10-13. Serial Port Control Register (SxCON)

10-15

SERIAL COMMUNICATIONS UNIT

The serial port receives BREAK characters of two different lengths. If a BREAK character longer
than M bit-times is detected, the DBRKO bit in SxSTS is set. If the BREAK character is longer
than 2M+3 bit-times, DBRKI in SxSTS is set. M is equal to the total number of bits in a frame.
For example, M is equal to 11 (decimal) in Mode 3.

Serial Status Register

SxSTS

Indicates the status of the serial port.

D
B
R

K
1

F
E

T
S

A1278-0A

Bit
Mnemonic

Bit Name

Reset
State

Function

DBRK1

Detect Break 1

Set when a break longer than 2M+3 bits occurs.

DBRKa

Detect Break a

Set when a break longer than M bits occurs.

RBS/PE

Received
BitS/Parity
Error

Contains the 9th received data bit in modes 2
and 3. PE is set when a parity error occurs. PE
is valid only when parity is enabled in Mode 1,
20r3.

Receive
Interrupt

RI is set when a character has been received
and placed in SxRBUF. Note that RI need not
be explicitly cleared to receive more characters.
Writing a one to this bit will not cause an
interrupt.

Transmit
Interrupt

TI is set when a character has finished transmitting. TI determines when one more
character can be transmitted. Writing a one to
this bit will not cause an interrupt.

NOTE:

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 10-14. Serial Port Status Register (SxSTS)

10-16

SERIAL COMMUNICATIONS UNIT

Serial Status Register

SxSTS

Indicates the status of the serial port.
0

D
8
R
K
1

D
8
R
K
0

R
8
8/
P
E

0
E

C
T
S

A1278-0A

Bit
Mnemonic

Bit Name

Reset
State

Function

Framing Error

FE is set when a framing error occurs. A
framing error occurs when a valid stop bit is not
detected.

TXE

Transmitter
Empty

TXE is set when both SxTBUF and the transmit
shift register are empty. TXE determines when
two consecutive bytes can be written to
SxTBUF for transmission. Accessing SxSTS
does not clear TXE.

Overrun Error

OE is set when an overrun error occurs. An
overrun error occurs when the character in
SxRBUF is not read before another complete
character is received. SxRBUF always contains
the most recent reception.

CTS

Clear To Send

CTS is the complement of the value on the CTF
pin. Accessing SxSTS does not clear CTS.

NOTE:

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 10-14. Serial Port Status Register (Continued)

When either BREAK character is detected, an overrun error occurs (DE is set). SxRBUF will contain at least one null character.

10-17

SERIAL COMMUNICATIONS UNIT

intet~

10.2.3 Programming in Mode 0
Programming is much easier in Mode 0 than in the asynchronous modes. Configuring SxCON
(Figure 10-13 on page 10-16) for Mode 0 requires only two steps:

Program M2:0 with the correct combination for Mode O.

If the Clear-to-Send feature is desired, set the CEN bit.

The serial port is now configured for Mode O. To transmit, write a character to SxTBUF. The TI
and TXE bits reflect the status of SxTBUF and the transmit shift register. Note that the SBRK bit
is independent of serial port mode functions in Mode O.
Receptions in Mode 0 are controlled by software. To begin a reception, set the REN bit in SxCON. The RI bit must be zero or the reception will not begin. Data begins shifting in on RXD as
soon as REN is set. The asynchronous error flags (DE, FE and PE) and break flags (DBRKO and
DBRKl) are invalid in Mode O.

10.3 HARDWARE CONSIDERATIONS FOR THE SERIAL PORT
There are several interface considerations when using the serial port.

10.3.1 CTS Pin Timings
When the Clear-to-Send ~*ur;e.,~q!lble<1 transmissions will not begin until the CTS pin is asserted while a transmission is pending. Figure 10-15 shows the recognition of a valid CTS.
, The CTS pin is sampled by the rising edge of CLKOUT. The CLKOUT high time synchronizes
, the CTS signal. On the falling edge of CLKOUT, the synchronized CTS signal is presented to the
serial port. CTS is an asynchronous signal. The setup and hold times are given only to ensure recognition at a specific clock edge. When CTS is asynchronously, it should be asserted for at least
1Y:z clock cycles to guarantee that the signal is recognized.
CTS is not latched internally. If CTS is asserted before a transmission starts, the subsequent transmission will not begin. A write to SxTBUF "arms" the CTS sense circuitry.

10.3.2 BCLK Pin Timings
The BCLK pin can be configured as the input to the baud timebase clock. The baud time base
clock increments the BxCNT register. However, the BCLK signal does not run directly into the
baud timebase clock. BCLK is first synchronized to the CPU clock (Figure 10-16.) The internal
synchronization logic uses a low-to-high level transition on BCLK to generate the baud timebase
clock that increments the BxCNT register. The CPU recognizes a low-to-high transition by sampling the BCLK pin low, then high.
10-18

SERIAL COMMUNICATIONS UNIT

The CPU samples BCLK on the rising edge of CLKOUT. The CLKOUT high time synchronizes
the BCLK signal. On the falling edge of CLKOUT, the synchronized BCLK signal is presented
to the baud timebase clock.
CTS Resolved
During CLKOUT

High Time
CLKOUT

:.: :-- TCHIH
TCHIS - : :-.;

CTS

CTS
(Internal)

A1279-0A

Figure 10-15. CTS Recognition Sequence

CLKOUT

• .
:-: :-.... TCHIH
:--TCHIH TCHIS-i :-;
:-.;

TCHIS - :

BCLK

Increment BCNT
(Internal)

I
_ _----'I
A12BO-OA

Figure 10-16. BCLK Synchronization

10-19

intet~

SERIAL COMMUNICATIONS UNIT

BCLK is an asynchronous input. However, the pin does have setup and hold times, which guarantee recognition at a specific CLKOUT. If the BCLK input signal has high and low times that
are both at least 1~ CLKOUT periods, than synchronization to CLKOUT is not necessary. However, when the BCLK signal has a high or a low time of less than 1~ CLKOUT periods, meeting
the setup and hold times to CLKOUT is necessary to avoid missing BCLK transitions. The maximum input frequency to BCLK is one-half the frequency of CLKOUT (CPU operating frequency).

10.3.3 Mode 0 Timings
This section shows the timings of the TXD and RXD pins in Mode O. In Mode 0, TXD never
floats. When not transmitting or receiving, TXD is high. RXD floats except when transmitting a
character.
10.3.3.1

CLKOUT as Baud Timebase Clock

The behavior of the transmit/receive clock (on TXD) is governed by the value of BxCMP. When
the BxCMP value is greater than or equal to two. The TXD pin is low for two CLKOUT periods
and is high for (BxCMP - 1) CLKOUT periods (see Figure 10-17). BxCMP cannot be equal to a
one, otherwise the serial port buffer registers (SxRBUF) will not receive the correct data.

CLKOUT

TXD

····L

High For
N-1 Clocks

RXD l,--_B_IT_O_ _ _.....JX,-__B_IT_1_ __
A12B2-A

Figure 10-17. Mode 0, BxCMP > 2

For transmissions, the RXD pin changes on the next CLKOUT falling edge following a low-tohigh transition on TXD. Therefore, the data on the RXD pin is guaranteed to be valid on the rising
edges of TXD. Use the rising edge ofTXD to latch the value on RXD. For receptions, the incoming serial data must meet the setup and hold timings with respect to the rising edge of TXD. These
timings can be found in the AC timings section of the data sheet.

10-20

SERIAL COMMUNICATIONS UNIT

10.3.3.2

BCLK as Baud Timebase Clock

BCLK does not run directly into the baud timebase clock, but is first synchronized to the CPU
clock. BCLK causes the baud timebase clock to increment, but transitions on TXD and RXD (for
transmissions) still occur relative to CLKOUT.
A low-to-high transition on BCLK increments BxCNT. If BxCNT is equal to BxCMP, TXD goes
low approximately 4% CLKOUTs later. TXD will always remain low for two CLKOUT periods
and then go high. TXD will go low again 4V2 CLKOUTs after BxCNT equals BxCMP. Therefore,
the output frequency on TXD is roughly equal to the input frequency on BCLK multiplied by BxCMP. There will be some clock jitter, as the output on TXD will always be some mUltiple of CLKOUTs. This is due to the internal synchronization.

10.4 SERIAL COMMUNICATIONS UNIT INTERRUPTS
Serial communication is usually interrupt-driven. An interrupt needs to occur on each reception
and on each transmission of a character. The RI and TI flags in the SxSTS register (Figure 10-14
on page 10-17) provide the interrupt mechanism for the serial ports. The two serial ports, or channels, have different interrupt circuitry. Serial channel 0 is directly supported by the integrated Interrupt Control Unit. Serial channell is supported by the SINTl output.

10.4.1 Channel 0 Interrupts
Figure 10-18 illustrates the channel 0 interrupt circuitry. Channel 0 receptions assert an internal
signal, Receive_InterrupcRequescO. This signal is routed both to the Interrupt Control Unit and
to the SOSTS register, where it sets the RI bit. The RI bit has no effect on the internal interrupt
request. Writing to RI does not cause an interrupt, and setting it does not prevent interrupts.
Channel 0 transmissions assert an internal signal, TransmiCInterrupCRequesCO. Like the
Receive_InterrupcRequesCO signal, this signal is routed to the Interrupt Control Unit and to the
SOSTS register. This signal sets the TI bit in SOSTS. Like the RI bit, TI has no effect on the internal interrupt request. Writing to TI does not cause an interrupt, and setting it does not prevent interrupts.

10.4.2 Channel 1 Interrupts
Figure 10-18 illustrates the channell interrupt circuitry. Channell receptions assert an internal
Receive_InterrupCRequesC1
signal
and
transmISSIOns
assert
an
internal
TransmiCInterrupCRequesC1 signal. Serial channell is supported by the SINTl output. Each
internal signal is routed to the SlSTS register, where it sets the RI or TI bit. The RI and TI bits
are ORed into the SINTl signal, so setting either bit asserts SINTl. Reading S 1STS clears the RI
and TI bits and deasserts SINTl. (This is the only method available for de asserting SINTl.)

10-21

intet~

SERIAL COMMUNICATIONS UNIT

ChanneLO_lnterrupt_Request

TransmiUnterrupCRequest_O

TII-----I

R
RII-----I

Receive_lnterrupCRequesCO

S
A127o-A

Figure 10-18. Channel 0 Interrupts

Read S1STS

......... R
. TransmiUnterrupCRequesC1

TII-----.

S
SINT1

Receive_lnterrupCRequesC 1

RII------'

S
A1271-0A

Figure 10-19. Channel 1 Interrupts

10-22

int'et

SERIAL COMMUNICATIONS UNIT

10.5 SERIAL PORT EXAMPLES
This section contains examples that show ways to use the serial port.
NOTE

The examples assume that the Peripheral Control Block is located in I/O space.

10.5.1 Asynchronous Mode Example
Example 10-1 contains sample code to initialize Serial Port 0 for 9600-baud operation in asynchronous Mode 4.
$mod186
name

,
;This file contains an example of initialization code for the 80C186EB
;Serial Communications Unit. The example has three procedures:
;ASYNC_CHANNEL_SETUP sets up channel 0 as 9600 baud, full duplex,
;
7 data bits+parity, with CTS# control.
;ASYNC~REC_INT_PROC is an interrupt handler for a reception. The procedure
is nearly empty, since the code to perform error checking
;
and receive buffer handling is application dependent.
;ASYNC_XMIT_INT_PROC is an interrupt handler for a transmission. This
procedure, too, is nearly devoid of code. A typical
application would test the TXE bit, then copy data from
the transmit buffer in memory to the SOTBUF register.
;We assume serial port registers have been correctly defined and the PCB
,
is located in I/O space.
equ Oxxxx
;channel 0 baud rate compare
BOCMP
equ Oxxxx
;channel 0 control
SOCON
equ Oxxxx
;channel 0 status
SOSTS
equ Oxxxx
;channel 0 receive buffer
SORBUF
equ Oxxxx
;channel 0 transmit buffer
SOTBUF
RI_TYPE
equ xx
; receive is interrupt type 20
TI_TYPE
equ 21
;transmit is interrupt type 21
equ Off02h
;end-of-interrupt register
EOI
equ Off14h
;SCU interrupt control register
SCUCON
code_seg
assume

segment public
cs:code_seg

;First, set up the interrupt handler vectors
xor

aX,ax

mov

ds, ax

mov
mov
mov
mov
mov

bx, RI_TYPE* 4
ax,offset ASYNC_REC_INT_PROC
[bx] ,ax
ax, seg ASYNC_REC_INT_PROC
[bx+2] ,ax

;need DS to point to interrupt vector
;table at Oh

Example 10-1. Asynchronous Mode 4 Example

10-23

intet~

SERIAL COMMUNICATIONS UNIT

mov
mov
mov
mov
mov

bx, TI_TYPE*4
aX,offset ASYNC_XMIT_INT_PROC
[bxl,ax
ax, seg ASYNC_XMIT_INT_PROC
[bx+21,ax

;Now set up channel 0 options
mov
mov
out
mov

ax,8067h
dx, BOCMP
dx,ax
aX,0059H

mov
out

dx, SOCON
dx,ax

;for 9600 baud from l6MHz CPU clock
;set baud rate
;CEN=l (CTS enabled)
;REN=O (receiver not yet enabled)
;EVN=l (even parity)
;PEN=l (parity turned on)
;MODE=l (lO-bit frame)
;write to serial control register

;Clear any pending RI or TI, just for safety
mov
in

dx, SOSTS
ax,dx

;clear any old RI or TI

;Clear interrupt mask bit in interrupt unit to allow SCU interrupts
mov
in
and
out

dx,SCUCON
ax,dx
aX,0007h
dx,ax

;Turn on the receiver
mov dx, SOCON
in
ax,dx
or
aX,0020
out dx,ax

;SCU interrupt control
;clear mask bit to enable

;read SOCON
;set REN bit (REN=l, receiver enabled)
;write SOCON

ret
ASYNC CHANNEL_SETUP endp
;Now the receiver is enabled and sampling of the RXD line begins.
;Any write to SOTBUF will initiate a transmission.
;The next procedure is executed every time a reception is completed.

mov
in
test
jnz
test
jnz
test
jnz

dx, SOSTS
ax, dx
al, lOOOOOOOb
parity_error
aI, OOOlOOOOb
framing_error
aI, OOOOOlOOb
overrun_error

;get status info
;test for parity error
;test for framing error
;test for overrun error

;At this point, we know the received data is OK.

Example 10-1. Asynchronous Mode 4 Example (Continued)

10-24

int:et

SERIAL COMMUNICAnONS UNIT

mov
in
and

dx, SORBUF
ax, dx
ax, 07fh

;read received data
;strip off parity bit

;Code to store the data in a receive buffer would go here. It has been omitted
;since this is heavily application dependent.

parity_error:
;Code for parity error handling goes here.

framing_error:
;Code for framing error handling goes here.

overrun_error:
;Code for overrun error handling goes here.

;Now we must issue the end-of-interrupt command to the interrupt unit.
mov dx,EOI
mov aX,8000h
dx, ax
out
iret

;issue non-specific EOI

;This procedure is entered whenever a transmission completes. Typical code
;would be inserted here to transmit the next byte from a transmit buffer
;set up in memory. since the configuration of such a buffer is application
; dependent, this section is omitted.
;Now we must issue the end-of-interrupt command to the interrupt unit.
mov dx,EOI
mov aX,8000h
out dx, ax
iret

;issue non-specific EOI

ends

Example 10-1. Asynchronous Mode 4 Example (Continued)

10-25

SERIAL COMMUNICATIONS UNIT

10.5.2 Mode 0 Example
Example 10-2 shows a sample Mode 0 application.
$mod186
name
i***************************************************** *********

FUNCTION: This function transmits the user's data, user_data, serially
over RXD1. TXD1 provides the transmit clock. The transmission frequency
is calculated as follows:
tran_freq

(0.5*CLKIN/BAUDRATE)-1

A 0-1-0 pulse on P1.0 indicates the end of transmission.

SYNTAX:

extern void far parallel_serial (char user_data,int tran_freq)

INPUTS:

user_data - byte to send out serially
tran_freq - baud rate compare value
None
Parameters are passed on the stack as required by high-level
languages.

OUTPUTS:
NOTE:

i***************************************************** *********

equ
equ
equ
equ

B1CMP
SlCON
SlSTS
SlTBUF
iXXXX

xxxxH
xxxxH
xxxxH
xxxxH

; Channel
; Channel
; Channel
; Channel

1
1
1
1

Baud Rate Compare
Control
Status
Receive Buffer

substitute register offset

;Example assumes that all the port pins are configured correctly and
;PCB is located in I/O space.
lib_80186
segment public 'code'
assume cs:lib_80186
public
-parallel_serial
-parallel_serialproc far
push bp
mov bp, sp
user_data
tran_freq

;save caller's bp
;get current top of stack

equ word ptr [bp+6];get parameters off the stack
equ word ptr [bp+8]
push ax
push dx

;save registers that
;will be modifiled

mov

;clear any pending exceptions

dx, SlSTS

Example 10-2. Mode 0 Example

10-26

intet

Check_4_TI:

SERIAL COMMUNICATIONS UNIT

mov
in
and
out
mov
mov
or
out

dx,
ax,
ax,
dx,
dx,
ax,
ax,
dx,

mov
mov
out

dx, P2CON
ax, Offh
dx, al

;set Port 2.1 for TXD

mov
mov
out
mov
xor
Qut
mov

dx,
ax,
dx,
dx,

;send user's data

P1CON
dx
Ofeh
al
B1CMP
tran_freq
8000h
ax

SlTBUF
user_data
al
SlCON
ax
~x,
dx, ax
dx, SlSTS

ax, dx
in
test ax, 0020h
Check_4_TI
jz

;Get state of port 1 controls
; make sure PI. 0 is port

;set internal clocking bit
; Mode 0, 1 million bps

;Mode 0, No CTS, Transmit

; check for TI bit

mov
xor
out

dx, P1LTCH
ax, ax
dx, al

;pulse PI. 0

not
out

ax
dx, al

;set PLO high

not
out

ax
dx, al

;set PI. 0 low

pop
pop
pop
ret

dx
ax
bp

; restore saved registers
; restore user's bp

...parallel_serial endp
lib_80186
ends
end

Example 10-2. Mode 0 Example (Continued)

10.5.3 Master/Slave Example
This section shows an example of a Mode 2 and 3 master/slave network. Figure 10-20 shows the
proper connection of the master to the slaves. The buffer is necessary to avoid contention on the
receive line. Alternatively, an open-collector buffer could be used and the port pin function could
be deleted.

10-27

SERIAL COMMUNICATIONS UNIT

MASTER

186 Core
Device
Master Transmit Line
TXD~~------------~'-----------~~--~

Master Receive Line

RXD~~--~----------~~~------~--~--

Port
Pin
80C51

Port
Pin
80C196

Port
Pin
186 Core
Device

SLAVES
A1273-0A

Figure 10-20. MfsterSlave Exam.J?!~)

($€IL 7 {3 1 f5" ~
Example 10-3 demonstrates how to implement a master/slave network in a typical system. The
remaining three examples show the routines used in the implementation. Example 10-4 is a master routine that addresses a slave and waits for it to respond. Example 10-5 is a slave routine that
responds to commands sent by the master. Equation 10-6 is the master routine that sends commands to the slave.

10-28

intet

SERIAL COMMUNICATIONS UNIT

$mod186
name
i***************************************************** **************

FUNCTION:
This function demonstrates how to implement the three
masterlslave routines {_slave_1, _select_slave, and _send_slave_commandl
in a typical setup.
NOTE:

It is assumed that the network is set up as shown in
Figure 10-20, that the slave unit is running the
_slave_1 code, and that the PCB is located in 1/0 space.

;

i***************************************************** **************

Slave1
Flash
Disc
False

equ
equ
equ
equ

01h
01h
Ofh
OOh

extrn
extrn
lib_80186

segment public 'code'
select_slave: far
_send_slave_cmd:far
ends

;address assigned to slave unit 1
;command to flash EVAL board LEDs
;command to disconnect from network
;declare external routines

segment public 'code'
assume cs:code

code

_main
proc near
push Slave1
;get slave unit 1 address
;send the address over the network
call far ptr _select_slave
add sp, 2
;adjust sp
cmp ax, false
;was slave 1 properly selected?
je
SlaveExi t
; no: then exi t

public
_main

push Flash

;yes: then send Flash command

;send it
call far ptr
add sp, 2

send_slave_cmd
;adjust sp

;insert a delay routine to allow completion of last command
push Disc

;prepare to disconnect slave

;send it
call far ptr
add sp, 2
SlaveExit:
_main
code

send_slave_cmd
;adjust sp

ret
endp
ends
end _main

Example 10-3. Master/Slave-Implementing the Master/Slave Routines

10-29

SERIAL COMMUNICATIONS UNIT

$mod186
name
i***************************************************** *********;

FUNCTION: This function transmits a slave address, _slave_addr, over the
serial network, with data bit 9 set to one. It then waits for the addressed
slave to respond with its (slave) address. If this address does not match
the originally transmitted slave address, or if there is no response within
a set time, the function will return false (ax = 0). Otherwise, the function
will return true (ax <> 0).
SYNTAX:

extern int far select_slave(int slave_addr);

INPUTS:

_slave_addr - address of the slave on the network

OUTPUTS:

True/False

NOTE:

Parameters are passed on the stack as required by high-level
languages. Example assumes that PCB is located in I/O space.

;

i***************************************************** *********

; substitute register offset in place of xxxxh
P1CON
P2CON
SlCON
SlSTS
SlTBUF
SlRBUF

equ
equ
equ
equ
equ
equ

xxxxh
xxxxh
xxxxh
xxxxh
xxxxh
xxxxh

lib_80l86

segment public 'code'
assume cs:lib_80l86

public
_select_slave

_select_slave
proc far
push bp
mov bp, sp

;get slave address off the stack
_slave_addr equ word ptr [bp+6]
push cx
push dx
mov
in
and
out
mov
mov
out

dx, P1CON
ax, dx
ax, OfOh
dx, al
dx, P2CON
ax, Offh
dx, al

;Port 1
; Port 2
; Serial
; serial
; Serial
; Serial

Control register
Control register
Port 1 Control register
Port 1 Status register
Port 1 Transmit Buffer
Port 1 Receive Buffer

;save caller's bp
;get current top of stack

;save registers that will be
; modi fied
;Get state of port 1 controls
;make sure Pl.0:3 is port
;set Port 2.1 for TXD1, P2.0 RXDl

Example 10-4. Master/Slave - The _selecCslave Routine

10-30

intet

SERIAL COMMUNICATIONS UNIT

mov
in
mov
mov
out
mov
mov

Check_4_RI:

out

SlSTS
;clear any pending exceptions
dx
; prepare to send address
SlCON
0083h
;d9=1, mode 3
ax
SlTBUF
;select slave
slave_addr
;get slave address
dx, al
;send it

mov
mov
out

dx, SlCON
ax, 0023h
dx, ax

;set REN
; enable receiver

xor

cx, cx

; reset time-out counter

mov

dx, SlSTS

; check to see i f data is waiting

dec
jnz

cx
NoTimeOut

; decrement time-out counter
;time-out=false:then continue

xor

ax, ax

jmp
NoTimeOut:

dx,
ax,
dx,
ax,
dx,
dx,
ax,

;time-out=true:set return
;value false (0)
short SlaveExit

ax, dx
in
test ax, 0040h

;test for RI bit

Check_4_RI

; keep checking till data received

mov
in
and

dx, SlRBUF
ax, dx
ax, Offh

;get slave response

xor

ax, _slave_addr;did addressed slave respond?
;ax=O:true else false
ax
;invert state of ax to be consistent
;with false(O) and true(non zero)
dx
; restore saved registers
cx
bp
;restore caller's bp

not
SlaveExit:

pop
pop
pop
ret

lib_80l86

ends
end

Example 10-4. Master/Slave -

;mask off unwanted bits

The _select_slave Routine (Continued)

10-31

intet~

SERIAL COMMUNICATIONS UNIT

$mod186
name

,.**************************************************************.,
slave_i
FUNCTION:

This function represents a slave unit connected to a multiprocessor master/slave network. This slave responds to two
commands:
Flash the LEOs on the EVAL Board, and
Disconnect from the Network.
Other commands are easily added.

SYNTAX:

extern void far slave_i!void);

INPUTS:

None

OUTPUTS:

None

NOTE:

Parameters are passed on the stack as required by high-level
languages. The slave should be running this code before the
master calls the slave. Example assumes PCB is in I/O space.

i***************************************************** *********

;substitute register offsets in place of xxxxh
PiCON
PiLTCH
P2CON
SlCON
SlSTS
SlTBUF
SlRBUF

equ
equ
equ
equ
equ
equ
equ

xxxxh
xxxxh
xxxxh
xxxxh
xxxxh
xxxxh
xxxxh

; Port 1
; Port 1
; Port 2
; Serial
; Serial
; serial
;Serial

Control register
Latch register
Control register
Port 1 Control register
Port 1 Status register
Port 1 Transmit Buffer
Port 1 Receive Buffer

segment public 'code'
assume cs:lib_80i86
MY_Address
TriStateEna
TriStateDis
FlashLEDs
Disconnect
public
_slave_i

equ Oih
equ 08h
equ
OOh
equ Oih
equ Ofh
_slave_i
proc far

;slave 1 network address
;Tri-state buffer enable
;Tri-state buffer disable
;list of commands unit 1 responds to

push
push
push
push

;save registers that will be modified

ax
bx
cx
dx

Example 10-5. Master/Slave -

10-32

The slave_1 Routine

SERIAL COMMUNICATIONS UNIT

DisconnectMode:

SelStatus:
Check_4_RI:

mov
in
mov
in
and
out
mov
mov
out
mov
mov
out

dx, SISTS
ax,dx
dx, PICON
ax, dx
ax, OfOh
dx, ax
dx, P2CON
ax, Offh
dx, ax
dx, PILTCH
ax, TriStateDis
dx, ax

mov
mov
out

dx, SICON
ax, 0022h
dx, ax

select control register
receive, Mode 2

mov
in
test
jz

dx, SISTS
ax, dx
ax, 0040h
Check_4_RI

select status register
get status
data waiting?
no: then keep checking

mov
in
cmp
jne

dx, SlSRUF
ax, dx
aI, My_Address
SelStatus

yes: then get data

mov
mov
out

dx, SICON
ax, 0003h
dx, ax

yes: then switch to Mode 3, transmit
Mode 3

mov
mov
out
mov
mov
out

dx,
ax,
dx,
dx,
ax,
dx,

mov
mov
out

dx, SICON
ax, 0023h
dx, ax

switch to receive mode
Mode 3, receive

mov
in
test
jz

dx, SISTS
ax, dx
ax, 0040h
Wait_4_Cmd

select status register
get status
command waiting?
no: then keep checking

mov
in

dx, SIRBUF
ax, dx

yes: then get command

cmp
je

al, Disconnect; Disconnect command?
DisconnectMode; yes: then disconnect RXD from network

get state of port I controls
make sure PI.O:PI.3 is port
set P2.1 for TXDI, P2.0for RXDI
make sure TXD latch is tristated
set PI.7 to zero

is slave_l being addressed?
no: then ignore

PILTCH
enable tristate buffer
TriStateEna
ax
gate TXD onto master's RXD
SITBUF
echo MY_Address to the master
MY_Address
ax

Example 10-5. Master/Slave -

clear any pending exceptions

The slave_1 Routine (Continued)

10-33

SERIAL COMMUNICATIONS UNIT

cmp
jne

al. FlashLEDs
Wait_4_Cmd

Flash LEDs command
no: then ignore

mov
mov
xor

dx. P1LTCH
ex. 20
ax. ax

yes: then flash LEDs 10 times

Send:

not ax
out dx. ax
mov bx. Offffh

Dly1:

dec
jnz

bx
Dly1

dec
jnz

ex
Send

jmp

short Wait_4_Cmd

pop
pop
pop
pop

ex
bx

ret
endp
ends
end
Example 10-5. MasterlSlave -

10-34

The slave_1 Routine (Continued)

intet

SERIAL COMMUNICATIONS UNIT

$mod186
name
;************************************************************************

SYNTAX:

send_slave_cmd
This function transmits a slave command, _slave_cmd, over
the serial network to a previously addressed slave.
extern void far send_slave_cmd (int slave_cmd)

INPUTS:

_slave_cmd (command to send to addressed slave)

OUTPUTS:

None

NOTE:

Parameters are passed on the stack as required by
high-level languages. Example assumes PCB is in 1/0 space.

FUNCTION:

;

i************************************************************************i

; substitute register offsets in place of xxxxh
SISTS
SICON
SITBUF

equ
equ
equ

xxxxh
xxxxh
xxxxh

serial Port 1 Status register
serial Port 1 Control register
Serial Port 1 Transmit Buffer register

segment public 'code'
assume cs:lib_80l86
public

_send_slave_cmd
_send_slave_cmd proc far
push bp
; save caller's bp
mov bp, sp
; get current top of stack

; get slave command off the stack
_slave_cmd
equ word ptr [bp+6]
push ax
push dx

save registers that are modified
clear any pending exceptions

mov
in
mov
mov
out

dx,
ax,
dx,
ax,
dx,

mov
mov
out

dx, SITBUF
ax,
slave_cmd
dx, al

select slave
get command to send to slave
send it

pop
pop
pop
ret

dx
ax
bx

restore saved registers

SISTS
dx
SICON
0OO3h
ax

prepare to send command
Mode 3

restore caller's bp

ends
end

Example 10-6. Master/Slave -

The _send_slave_command Routine

10-35

intel .

Input/Output Ports

CHAPTER 11
INPUT/OUTPUT PORTS
Many applications do not require full use of all the on-chip peripheral functions. For example, the
Chip-Select Unit provides a total of ten chip-select lines; only a large design would require all
ten. For smaller designs that require fewer than ten chip-selects, these pins would be wasted.
The input/output ports give system designers the flexibility to replace the functions of unused peripheral pins with general-purpose I/O ports. Many of the on-chip peripheral pin functions are
multiplexed with an I/O port. If a particular peripheral pin function is unnecessary in an application, that pin can be used for I/O. The 80C186EB/8OC188EB has four types of ports: bidirectional, input-only, output-only, and open-drain bidirectional.

11.1 FUNCTIONAL OVERVIEW
All port pin types are derived from a common bidirectional port logic module. Unidirectional and
open-drain ports are a subset of the bidirectional module. The following sections describe each
port type. The bidirectional port is described in detail, as it is the basis for all of the other port
types. The descriptions for the unidirectional and open-drain ports only highlight their specific
differences from the common bidirectional module.

11.1.1

Bidirectional Port

Figure, 11-1 shows a simplified schematic of a bidirectional port pin. The overall function of a
bidirectional port pin is controlled by the state of the Port Control Latch. The output of the Port
Control Latch selects the source of output data and the source of the control signal for the threestate output driver. When the port is programmed to act as a peripheral pin, both the data for the
pin and the directional control signal for the pin come from the associated integrated peripheral.
When a bidirectional port pin is programmed as an I/O port, all port parameters are under software control.
The output of the Port Direction latch enables (or disables) the three-state output driver when the
pin is programmed as an I/O port. The three-state output driver is enabled by clearing the Port
Direction latch. The data driven on an output port pin is held in the Port Data latch. Setting the
Port Direction latch disables the three-state output driver, making the pin an input.
The signal present on the device pin is routed through a synchronizer to a three-state latch that
connects to the internal data bus. The state of the pin can be read at any time, regardless of whether the pin is used as an I/O port or for a peripheral function.

11-1

INPUT/OUTPUT PORTS

From Integrated
Peripheral
:;;::::::;:;;;::::;::==~

Read Port
Data latch

) - - - - - - - - - - - , Port/Peripheral
Data Multiplexer
Output Driver

QI---"'''''''

Write Port
Data Latch

Port Data Latch

Read Port
Pin State
....-HSyNC
Read Port
Direction Control

Internal Data
Bus (F-Bus)

Q 1----.--+--+-1
Write Port
Direction
Read Port
Direction

Port Direction Latch

o
Q t---tl........-+-+....
1...--4----1
Port Control Latch

To Integrated
Peripheral

1------;:::::::;::=====,---'
Peripheral
Direction Control
A1247·0A

Figure 11-1. Simplified Logic Diagram of a Bidirectional Port Pin

11-2

INPUT/OUTPUT PORTS

11.1.2 Input Port
Figure 11-3 shows the internal construction of an input port pin. An internal connection permanently disables the three-state output driver. The Port Pin register holds the current state (synchronized to the CPU clock) of the input pin. The Port Direction and Port Data bits are not used for
an input-only port pin; they can be used for storage.

11.1.3 Output Port
Figure 11-3 shows the internal construction of an output port pin. An internal connection permanently enables the three-state output driver. The Port Control latch selects the source of data for
the pin, which can be either the on-chip peripheral or the Port Data latch. The Port Direction bit
has no effect on an output-only pin; it can be used for storage.

11.1.4 Open-Drain Bidirectional Port
Figure 11-4 shows the internal control logic for the open-drain bidirectional port pin. The logic
is slightly different from that for the other port types. When the open-drain port pin is configured
as an output, clearing the Port Data latch turns on the N-channel driver, resulting in a "hard zero"
being present at the pin. A one value in the Port Data Latch shuts off the driver, resulting in a high
impedance (input) state at the pin. The open-drain pin can be floated directly by setting its Port
Direction bit.
The open-drain ports are not multiplexed with on-board peripherals. The port/peripheral data
multiplexer exists for open-drain ports, even though the pins are not shared with peripheral functions. The open-drain port pin floats if the Port Control latch is programmed to select the nonexistent peripheral function.

11.1.5 Port Pin Organization
The port pins are organized as two functional groups, Port 1 and Port 2. Port 1 consists of eight
output-only pins. Port 2 has one bidirectional, two output-only, three input-only, and two opendrain bidirectional pins. Most of the port pins are multiplexed with peripheral functions.

11-3

INPUT/OUTPUT PORTS

From Integrated
Peripheral

Port/Peripheral
Data Multiplexer

Read Port
Data Latch

Output Driver
(Permanently Disabled)

D
QI--..........J
L..-....t,.l_..J

Port Data Latch

SYNC

Internal Data
Bus (F-Bus)
Q
Write Port
Direction
Read Port
Direction

Port Direction Latch

Port Control Latch
To Integrated 1------..;..---------1
Peripheral
A1505-0A

Figure 11-2. Simplified Logic Diagram of an Input Port Pin

11-4

in1et

INPUT/OUTPUT PORTS

Output Driver
(Permenantly Disabled)

Q
Pin

D
QI----4..........

Write Port
Data Latch

Port Data Latch

Read Port
Pin State
SYNC
Read Port
Direction Control

Internal Data
Bus (F-Bus)
Q

Write Port
Direction
Read Port
Direction

Port Direction Latch

D
Q t----1I----t......
L..--4'--...J

Control
Port Control Latch
To Integrated 1-_ _ _ _ _ _ _ _ _ _ _--'
Peripheral
A1248-0A

Figure 11-3. Simplified Logic Diagram of an Output Port Pin

11-5

INPUT/OUTPUT PORTS

From Port
Direction
Latch

Port Data
Latch

SYNC I--_...J

From Port
Control
Latch
A1249-0A

Figure 11-4. Simplified Logic Diagram of an Open-Drain Bidirectional Port

11-6

intet~
11.1.5.1

INPUT/OUTPUT PORTS

Port 1 Organization

Port 1 consists of eight output-only port pins. The Port 1 pins are multiplexed with the generalpurpose chip-selects (GCS7:0). Table 11-1 shows the multiplexing options for Port 1.
Table 11-1. Port 1 Multiplexing Options

11.1.5.2

Pin Name

Peripheral Function

Port Function

P1.7/GCS7

GCS7

P1.7

P1.6/GCS6

GCS6

P1.6

P1.5/GCS5

GCS5

P1.5

P1.4/GCS4

GCS4

P1.4

P1.3/GCS3

GCS3

P1.3

P1.2/GCS2

GCS2

P1.2

P1.1/GCS1

GCS1

P1.1

P1.0/GCSO

GCSO

P1.0

Port 2 Organization

Six of the Port 2 pins are multiplexed with serial channel functions; the other two provide opendrain bidirectional port pin functions. Table 11-2 shows the Port 2 multiplexing options.
Table 11-2. Port 2 Multiplexing Options
Pin Name

Peripheral Function

Port Function

P2.7

None

P2.7 (Open-drain)

P2.6
P2.5/BClKO

None
BClKO

P2.6 (Open-drain)
(Input)

P2.5

P2.4/CTS1

CTS1

(Input)

P2.4

P2.3/SINT1

SINT1

(Output)

P2.3

P2.2/BClK1

BClK1

(Input)

P2.2

P2.1/TXD1

TXD1

(Output)

P2.1

P2.0/RXD1

RXD1

(1/0)

P2.0

11.2 PROGRAMMING THE I/O PORT UNIT
Each port is controlled by a set of four Peripheral Control Block registers: the Port Control Register (PxCON), the Port Direction Register (PxDIR), the Port Data Latch Register (PxLTCH) and
the Port Pin State Register (PxPIN).

11-7

INPUT/OUTPUT PORTS

11.2.1

Port Control Register

The Port Control Register (Figure 11-5) selects the overall function for each port pin: peripheral
or port. For I/O ports, the Port Control Register is used to assign the pin to either the associated
on-chip peripheral or to a general-purpose I/O port. For output-only ports, the Port Control Register selects the source of data for the pin: either an on-chip peripheral or the Port Data latch.

Port Control Register

PxCON (P1 CON, P2CON)

Selects port or peripheral function for a port pin.

p
C
7

p
C
6

p
C
5

p
C
4

C C

A1312-0A

Bit
Mnemonic
PC7:0

NOTE:

Bit Name
Port Control
7:0

Reset
State
FFH

Function
When the PC bit for a specific pin is set, the
associated integrated peripheral controls both
pin direction and pin data. Clearing the PC bit
makes the pin a general-purpose 1/0 port.

Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 11-5. Port Control Register (PxCON)

11.2.2 Port Direction Register
The Port Direction Register (Figure 11-6) controls the direction (input or output) for each pin programmed as a general-purpose I/O port. The Port Direction bit has no effect on output-only port
pins. These unused direction control bits can be used for bit storage.
The Port Direction Register is read/write. When read, the register returns the value written to it
previously. Pins with their direction fixed return the value in this register, not a value indicating
their true direction. The direction of a port pin assigned to a peripheral function is controlled by
the peripheral; the Port Direction value is ignored.

11-8

INPUT/OUTPUT PORTS

Port Direction Register

PxDIR (P1 DIR, P2DIR)

Controls the direction of pins programmed as 1/0
ports.

15
p

0
7

p
0
6

p
0
5

p
0
4

p
0
3

p
0
2

p
0

A1313-0A

Bit
Mnemonic
PD7:0

Bit Name
Port
Direction 7:0

Reset
State
FFH

Function
Setting the PD bit for a pin programmed as a
general-purpose I/O port selects the pin as an
input. Clearing the PD bit selects the pin as an
output.

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 11-6. Port Direction Register (PxDIR)

11.2.3 Port Data Latch Register
The Port Data Latch Register (Figure 11-7) holds the value to be driven on an output or bidirectional pin. This value appears at the pin only if it is programmed as a port.
The Port Data Latch Register is read/write. Reading a Port Data Latch Register returns the value
of the latch itself and not that of the associated port pin.

11-9

INPUT/OUTPUT PORTS

Port Data Latch Register

PxLTCH (P1LTCH, P2LTCH)

Contains the data driven on pins programmed as
output ports.

o
p

L L L
7

P
L
4

P
L
3

P
L

o
A1314-0A

Bit
Mnemonic
PL7:0
NOTE:

Bit Name
Port Data
Latch 7:0

Reset
State

FFH

Function
The data written to a PL bit appears on pins
programmed as general-purpose output ports.

Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products.

Figure 11-7. Port Data Latch Register (PxLTCH)

11.2.4 Port Pin State Register
The Port Pin State Register (Figure 11-8) is a read-only register that is used to determine the state
of a port pin. When the Port Pin State Register is read, the current state of the port pins is gated
to the internal data bus.

11-10

INPUT/OUTPUT PORTS

Port Pin State Register

PxPIN (P1 PIN, P2PIN)

Reads the logic state at a port pin.

o
p

p
p

p
P

p
P
3

p
P
2

p
1

A1315-0A

Bit
Mnemonic
PP7:0

NOTE:

Reset
State

Bit Name
Port Pin
State 7:0

XXXXH

Function
Reading the Port Pin State register returns the
logic state present on the associated pin.

Reserved register bits are shown with gray shading_ Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.

Figure 11-8. Port Pin State Register (PxPIN)

11.2.5 Initializing the VO Ports
The state of the I/O ports following a reset is as follows:
• Port 1 is configured for peripheral function (general-purpose chip-selects, GCS7:0).
• Port 2 is configured for peripheral function. The direction of each pin is the default direction
for the peripheral function (e.g., P2.lITXDl is an output, P2.5IBCLKO is an input). See
Table 11-2 on page 11-7 for details.
There are no set rules for initializing the I/O ports. The Port Data Latch should be programmed
before selecting a pin as an output port (to prevent unknown Port Data Latch values from reaching
the pins).

11-11

INPUT/OUTPUT PORTS

11.3 PROGRAMMING EXAMPLE

Example 11-1 shows a typical ASM86 routine to configure the 110 ports. GCS7 through GCS4
are routed to the pins, while Pl.O through P1.4 are used as output ports. The binary value 0101 is
written to P1.0 through P1.3. The states of pins P2.6 and P2.7 are read and stored in the AL register.
$modl86
name

,
;This file contains sample programming code for the 80Cl86EB I/O Port Unit.

,
;PCB EQUates in an include file.
#include PCBMAP.inc
segment public
assume cs:code_seg
I O_UNIT_EXAMPL
proc near
;write OIOIB to data latch for pins PI.3 through PI.O
mov
mov
out

dx,PILTCH
aI, OIOlb
dx,al

;Gate data latch to output pins. PI.3 to PI.O are port pins.
mov
mov
out

dx,PICON
al,OFOh
dx,al

;Read P2.6 and P2.7.We assume they have not been changed to output pins since
;reset.
mov
in
and

dx,P2PIN
al,dx
al,OCOh;

strip unused bits

;AL now holds the states of the P2.6 and P2.7 pins.

code_seg
end

ends

Example 11·1. VO Port Programming Example

11-12

12
•
Math Coprocesslog

CHAPTER 12
MATH COPROCESSING
The 80C186 Modular Core Family meets the need for a general-purpose embedded microprocessor. In most data control applications, efficient data movement and control instructions are foremost and arithmetic performed on the data is simple. However, some applications do require more
powerful arithmetic instructions and more complex data types than those provided by the 80C 186
Modular Core.

12.1 OVERVIEW OF MATH COPROCESSING
Applications needing advanced mathematics capabilities have the following characteristics.
• Numeric data values are non-integral or vary over a wide range
• Algorithms produce very large or very small intermediate results
• Computations must be precise (i.e., calculations must retain several significant digits)
• Computations must be reliable without dependence on programmed algorithms
• Overall math performance exceeds that afforded by a general-purpose processor and
software alone
For the 80C186 Modular Core family, the 8OC187 math coprocessor satisfies the need for powerful mathematics. The 80C 187 can increase the math performance of the microprocessor system
by 50 to 100 times.

12.2 AVAILABILITY OF MATH COPROCESSING
The 80C 186 Modular Core supports the 80C 187 with a hardware interface under microcode control. However, not all proliferations support the 80C187. Some package types have insufficient
leads to support the required external handshaking requirements. The 3-volt versions of the processor do not specify math coprocessing because the 80C 187 has only a 5-volt rating. Please refer
to the current data sheets for details.
The core has an Escape Trap (ET) bit in the PCB Relocation Register (Figure 4-1 on page 4-2) to
control the availability of math coprocessing. If the ET bit is set, an attempted numerics execution
results in a Type 7 interrupt. The 80C187 will not work with the 8-bit bus version of the processor
because a1l80C187 accesses must be 16-bit. The 80C188 Modular Core automatically traps ESC
(numerics) opcodes to the Type 7 interrupt, regardless of Relocation Register programming.

12-1

MATH COPROCESSING

intet

12.3 THE 80C187 MATH COPROCESSOR
The 80C187's high performance is due to its 80-bit internal architecture. It contains three units:
a Floating Point Unit, a Data Interface and Control Unit and a Bus Control Logic Unit. The foundation of the Floating Point Unit is an 8-element register file, which can be used either as individually addressable registers or as a register stack. The register file allows storage of
intermediate results in the 80-bit format. The Floating Point Unit operates under supervision of
the Data Interface and Control Unit. The Bus Control Logic Unit maintains handshaking and
communications with the host microprocessor. The 8OC187 has built-in exception handling.
The 80C187 executes code written for the Intel387™ DX and Intel387 SX math coprocessors.
The 8OC187 conforms to ANSIIIEEE Standard 754-1985.

12.3.1 80C187 Instruction Set
8OC187 instructions fall into six functional groups: data transfer, arithmetic, comparison, transcendental, constant and processor control. Typical 8OC187 instructions accept one or two operands and produce a single result. Operands are usually located in memory or the 8OC187 stack.
Some operands are predefined; for example, FSQRT always takes the square root of the number
in the top stack element. Other instructions allow or require the programmer to specify the operand(s) explicitly along with the instruction mnemonic. Still other instructions accept one explicit
operand and one implicit operand (usually the top stack element).
As with the basic (non-numerics) instruction set, there are two types of operands for coprocessor
instructions, source and destination. Instruction execution does not alter a source operand. Even
when an instruction converts the source operand from one format to another (for example, real to
integer), the coprocessor performs the conversion in a work area to preserve the source operand.
A destination operand differs from a source operand because the 8OC187 can alter the register
when it receives the result of the operation. For most destination operands, the coprocessor usually replaces the destinations with results.

12·2

MATH COPROCESSING

12.3.1.1

Data Transfer Instructions

Data transfer instructions move operands between elements of the 80C187 register stack or between stack top and memory. Instructions can convert any data type to temporary real and load it
onto the stack in a single operation. Conversely, instructions can convert a temporary real operand
on the stack to any data type and store it to memory in a single operation. Table 12-1 summarizes
the data transfer instructions.
Table 12-1. 80C187 Data Transfer Instructions
Real Transfers
FLD

Load real

FST

Store real

FSTP

Store real and pop

FXCH

Exchange registers
Integer Transfers

FILD

Integer load

FIST

Integer store

FISTP

Integer store and pop
Packed Decimal Transfers

12.3.1.2

FBLD

Packed decimal (BCD) load

FBSTP

Packed decimal (BCD) store and pop

Arithmetic Instructions

The 80C187's arithmetic instruction set includes many variations of add, subtract, multiply, and
divide operations and several other useful functions. Examples include a simple absolute value
and a square root instruction that executes faster than ordinary division. Other arithmetic instructions perform exact modulo division, round real numbers to integers and scale values by powers
of two.
Table 12-2 summarizes the available operation and operand forms for basic arithmetic. In addition to the four normal operations, "reversed" instructions make subtraction and division "symmetrical" like addition and multiplication. In summary, the arithmetic instructions are highly
flexible for these reasons:
• the 80C187 uses register or memory operands
• the 80C 187 can save results in a choice of registers

12-3

intel~

MATH COPROCESSING

Available data types include temporary real, long real, short real, short integer and word integer.
The 80C187 performs automatic type conversion to temporary real.
Table 12-2. 80C187 Arithmetic Instructions
Addition

Division
Divide real

FADD

Add real

FDIV

FADDP

Add real and pop

FDIVP

Divide real and pop

FIADD

Integer add

FIDIV

Integer divide

FDIVR

Divide real reversed

Subtraction
FSUB

Subtract real

FDIVRP

Divide real reversed and pop

FSUBP

Subtract real and pop

FIDIVR

Integer divide reversed

FISUB

Integer subtract

FSUBR

Subtract real reversed

FSQRT

Square root

FSUBRP

Subtract real reversed and pop

FSCALE

Scale

FISUBR

Integer subtract reversed

FPREM

Partial remainder

FRNDINT

Round to integer

Multiplication

Other Operations

FMUL

Multiply real

FXTRACT

Extract exponent and significand

FMULP

Multiply real and pop

FABS

Absolute value

FIMUL

Integer multiply

FCHS

Change sign

FPREMI

Partial remainder (IEEE)

12-4

intet
12.3.1.3

MATH COPROCESSING

Comparison Instructions

Each comparison instruction (see Table 12-3) analyzes the stack top element, often in relationship
to another operand. Then it reports the result in the Status Word condition code. The basic operations are compare, test (compare with zero) and examine (report tag, sign and normalization).
Table 12-3. 80C187 Comparison Instructions

12.3.1.4

FCOM

Compare real

FCOMP

Compare real and pop

FCOMPP

Compare real and pop twice

FICOM

Integer compare

FICOMP

Integer compare and pop

FTST

Test

FXAM

Examine

FUCOM

Unordered compare

FUCOMP

Unordered compare and pop

FUCOMPP

Unordered compare and pop twice

Transcendental Instructions

Transcendental instructions (see Table 12-4) perform the core calculations for common trigonometric, hyperbolic, inverse hyperbolic, logarithmic and exponential functions. Use prologue code
to reduce arguments to a range accepted by the instruction. Use epilogue code to adjust the result
to the range of the original arguments. The transcendentals operate on the top one or two stack
elements and return their results to the stack.
Table 12-4. 80C187 Transcendental Instructions

FPTAN

Partial tangent

FPATAN

Partial arctangent

F2XM1

2x-1-

FYL2X

Y log2X

FYL2XP1

Y log2(X+1)

FCOS

Cosine

FSIN

Sine

FSINCOS

Sine and Cosine

12-5

int'et

MATH COPROCESSING

12.3.1.5

Constant Instructions

Each constant instruction (see Table 12-5) loads a commonly used constant onto the stack. The
. values have full SO-bit precision and are accurate to about 19 decimal digits. Since a temporary
real constant occupies 10 memory bytes, the constant instructions, only 2 bytes long, save memory space.
Table 12-5. 80C187 Constant Instructions

12.3.1.6

FLDZ

Load + 0.1

FLD1

Load +1.0

FLDPI

Load

FLDL2T

Loadlog2 1o

FLDL2E

Load IOg2e

FLDLG2

Load IOg102

FLDLN2

Load log. 2

Processor Control Instructions

Computations do not use the processor control instructions; these instructions are available for
activities at the operating system level. This group (see Table 12-6) include~ initialization, exception handling and task switching instructions.
Table 12-6. 80C187 Processor Control Instructions

12-6

FINIT/FNINIT

Initialize processor

FLDENV

Load environment

FDISI/FNDISI

Disable interrupts

FSAVElFNSAVE

Save state

FENI/FNENI

Enable interrupts

FRSTOR

Restore state

FLDCW

Load control word

FINCSTP

Increment stack pOinter

FSTCW/FNSTCW

Store control word

FDECSTP

Decrement stack pointer

FSTSW/FNSTSW

Store status word

FFREE

Free register

FCLEXlFNCLEX

Clear exceptions

FNOP

No operation

FSTENVIFNSTENV

Store environment

FWAIT

CPU wait

MATH COPROCESSING

12.3.2 80C187 Data Types
The microprocessor/math coprocessor combination supports seven data types:
• Word Integer representation.

A signed 16-bit numeric value. All operations assume a 2's complement

• Short Integer - A signed 32-bit numeric value (double word). All operations assume a 2's
complement representation.
• Long Integer - A signed 64-bit numeric value (quad word). All operations assume a 2's
complement representation.
• Packed Decimal- A signed numeric value contained in an 80-bit BCD format.
• Short Real - A signed 32-bit floating point numeric value.
• Long Real- A signed 64-bit floating point numeric value.
• Temporary Real - A signed 80-bit floating point numeric value. Temporary real is the
native 8OC187 format.
Figure 12-1 graphically represents these data types.

12.4 MICROPROCESSOR AND COPROCESSOR OPERATION
The 8OC187 interfaces directly to the microprocessor (as shown in Figure 12-2) and operates as
an I/O-mapped slave peripheral device. Hardware handshaking requires connections between the
8OC187 and four special pins on the processor: NCS, BUSY, PEREQ and ERROR. These pins
are not available in some package types. Refer to the data sheet for details.

12-7

intet

MATH COPROCESSING

Increasing Significance

lIE

Word
Integer

Short
Integer

(Two's Complement)

lsi

(Two's Complement)

Magnitude

31
Long
Integer

lsi

Magnitude

(Two's
Complement)

Packed
Decimal

Short
Real

Long
Real

lsi

Biased
Exponent

63
Temporary
Real

lsi
79

Significand

Biased
Exponent

64~

52"'-1 ...
Significand

NOTES:

S = Sign bit (0 = positive, 1 = negative)
dn = Decimal digit (two per byte)
X = Bits have no significance; 80C187 ignores when loading. zeros when storing .
... = Position of implicit binary point
I = Integer bit of significand; stored in temporary real, implicit in short and long real
Exponent Bias (normalized values):
Short Real: 127 (7FH)
Long Real: 1023 (3FFH)
Temporary Real: 16383 (FFFH)
A1257·0A

Figure 12-1. 80C187-Supported Data Types

12-8

MATH COPROCESSING

External

Latch

Oscillator

Buffer

D15:8

AD15:0
ALE I---+-CLKOUT I---~
80C186
Modular
Core

RESOUT

RESET

NPWR

NPRD

BUSY

ERROR

PEREQ

Buffer
D7:0

NCS

OE T

NPS1

CS
DEN
DTiR

A1255-01

Figure 12-2. 80C186 Modular Core Family/80C187 System Configuration

12-9

intet

MATH COPROCESSING

12.4.1 Clocking the 80C187
The microprocessor and math coprocessor operate asynchronously, and their clock rates may differ. The 80C187 has a CKM pin that determines whether it uses the input clock directly or divided
by two. Direct clocking works up to 12.5 MHz, which makes it convenient to feed the clock input
from the microprocessor's CLKOUT pin. Beyond 12.5 MHz, the 80C187 must use a multiplyby-two clock input up to a maximum of 32 MHz. The microprocessor and the math coprocessor
have correct timing relationships, even with operation at different frequencies.

12..4.2 Processor Bus Cycles Accessing the 80C187
Data transfers between the microprocessor and the 80C187 occur through the dedicated, 16-bit

110 ports shown in Table 12-7. When the processor encounters a numerics opcode, it first writes
the opcode to the 80C187. The 8OC187 decodes the instruction and passes elementary instruction
information (Opcode Status Word) back to the processor. Since the 80C187 is a slave processor,
the Modular Core processor performs all loads and stores to memory. Including the overhead in
the microprocessor's microcode, each data transfer between memory and the 80C187 (via the microprocessor) takes at least 17 processor clocks.
Table 12-7. 80C187 VO Port Assignments
I/O Address

Read Definition

Write Definition

OOFBH

Status/Control

Opcode

OOFAH

Data

OOFCH

Reserved

CS:IP, DS:EA

OOFEH

Opcode Status

Reserved

The microprocessor cannot process any numerics (ESC) opcodes alone. If the CPU encounters a
numerics opcode when the Escape Trap (ET) bit in the Relocation Register is a zero and the
8OC187 is not present, its operation is indeterminate. Even the FINITIFNINIT initialization instruction (used in the past to test the presence of a coprocessor) fails without the 8OC187. If an
application offers the 80C187 as an option, problems can be prevented in one ofthree ways:
• Remove all numerics (ESC) instructions, including code that checks for the presence of the
8OC187.
• Use a jumper or switch setting to indicate the presence of the 80C187. The program can
interrogate the jumper or switch setting and branch away from numerics instructions when
the 80C 187 socket is empty.
• Trick the microprocessor into predictable operation when the 80C187 socket is empty. The
fix is placing pull-up or pull-down resistors on certain data and handshaking lines so the
CPU reads a recognizable Opcode Status Word. This solution requires a detailed knowledge
of the interface.

12-10

MATH COPROCESSING

Bus cycles involving the 8OC187 Math Coprocessor behave exactly like other 110 bus cycles with
respect to the processor's control pins. See "System Design Tips" for information on integrating
the 80C187 into the overall system.

12.4.3 System Design Tips
All 8OC187 operations require that bus ready be asserted. The simplest way to return the ready
indication is through hardware connected to the processor's external ready pin. If you program a
chip-select to cover the math coprocessor port addresses, its ready programming is in force and
can provide bus ready for coprocessor accesses. The user must verify that there are no conflicts
from other hardware connected to that chip-select pin.
A chip-select pin goes active on 80C 187 accesses if you program it for a range including the math
coprocessor 110 ports. The converse is not true - a non-80C187 access cannot activate NCS (numerics coprocessor select), regardless of programming.
In a buffered system, it is customary to place the 8OC187 on the local bus. Since DTR and DEN
function normally during 80C187 transfers, you must qualify DEN with NCS (see Figure 12-3).
Otherwise, contention between the 8OC187 and the transceivers occurs on read cycles to the
8OC187.
The microprocessor's local bus is available to the integrated peripherals during numerics execution whenever the CPU is not communicating with the 80C 187. The idle bus allows the processor
to intersperse DRAM refresh cycles with accesses to the 8OC187.
The microprocessor's local bus is available to alternate bus masters during execution of numerics
instructions when the CPU does not need it. Bus cycles driven by alternate masters (via the
HOLDIHLDA protocol) can suspend coprocessor bus cycles for an indefinite period.
The programmer can lock 80C187 instructions. The CPU asserts the LOCK pin for the entire duration of a numerics instruction, monopolizing the bus for a very long time.

12-11

MATH COPROCESSING

External
Oscillator

Latch

Buffer
D15:8
AD15:0
ALE 1---+-

CLKOUT 1 - - - -

80C186
Modular
Core

RESOUT

RESET

NPWR

NPRD

BUSY

Buffer
D7:0

ERROR

PEREQ

NCS

OE T

NPS1

CS
DEN

DT/R

A1255-01

Figure 12-3. 80C187 Configuration with a Partially Buffered Bus
12-12

MATH COPROCESSING

12.4.4 Exception Trapping
The 80C 187 detects six error conditions that can occur during instruction execution. The 80C 187
can apply default fix-ups or signal exceptions to the microprocessor's ERROR pin. The processor
tests ERROR at the beginning of numerics instructions, so it traps an exception on the next attempted numerics instruction after it occurs. When ERROR tests active, the processor executes a
Type 16 interrupt.
There is no automatic exception-trapping on the last numerics instruction of a series. If the last
numerics instruction writes an invalid result to memory, subsequent non-numerics instructions
can use that result as if it is valid, further compounding the original error. Insert the FNOP instruction at the end of the 80C 187 routine to force an ERROR check. If the program is written in
a high-level language, it is impossible to insert FNOP. In this case, route the error signal through
an inverter to an interrupt pin on the microprocessor (see Figure 12-4). With this arrangement,
use a flip-flop to latch BUSY upon assertion of ERROR. The latch gets cleared during the exception-handler routine. Use an additional flip-flop to latch PEREQ to maintain the correct handshaking sequence with the microprocessor.

12.5 Example Math Coprocessor Routines
Example 12-1 shows the initialization sequence for the 80C187. Example 12-2 is an example of
a floating point routine using the 80C187. The FSINCOS instruction yields both sine and cosine
in one operation.

12-13

MATH CO PROCESSING

80C186
Modular Core
ERROR
RESOUT

CSx
INTx
latch

BUSY
PEREa
ALE

NCS

A19:A16
AD15:0

RD
WR
ClKOUT

A
D
D
R
E
S
S

C
'74

015:0

a
Q

ClK
A2

A19:0

CMD1

NPWR

CMDO

NPRD

80C187
NPS1
CKM

PEREa
BUSY

NPS2

e4--~D

a~~~

'74

ERROR
RESET
A1256-01

Figure 12-4. 80C187 Exception Trapping via Processor Interrupt Pin

12-14

MATH COPROCESSING

$modlB6
name
example_BOClB7_init
; FUNCTION:

This function initializes the BOClB7 numerics coprocessor.

; SYNTAX:

extern unsigned char far lB7_init(void);

; INPUTS:

None

;OUTPUTS:

unsigned char - OOOOh -> False -> coprocessor not initialized
ffffh -> True -> coprocessor initialized

;NOTE:

Parameters are passed on the stack as required by
high-level languages.
segment public 'code'
assume cs:lib_BOlB6

push
mov

bp
bp, sp

cli
fninit
fnstcw

;disable maskable interrupts
[bp-2]

sti

Ok:

;save caller's bp
;get current top of stack

;init BOClB7 processor
;get current control word
;enable interrupts

mov
and
cmp
je
xor
pop
ret

ax, [bp-2]
ax, 0300h
ax, 0300h
Ok
ax, ax
bp

and
fldcw

[bp-2], Offfeh
[bp-2]

;unmask possible exceptions

mov
pop
ret

aX,Offffh
bp

;return true (BOClB7 ok)
;restore caller's bp

;mask off unwanted control bits
;PC bits = 11
;yes: processor ok
;return false (BOClB7 not ok)
;restore caller's bp

_lB7_initendp
lib_BOlB6ends
end

Example 12-1. Initialization Sequence for 80C187 Math Coprocessor

12-15

intet~

MATH COPROCESSING

$modl86
$modcl87
name
; DESCRIPTION:

This code section uses the 80Cl87 FSINCOS transcendental
instruction to convert the locus of a point from polar
to Cartesian coordinates.

;VARIABLES:

The variables consist of the radius, r, and the angle, theta.
Both are expressed as 32-bit reals and 0 <= theta <= pil4.

;RESULTS:

The results of the computation are the coordinates x and y
expressed as 32-bit reals.

;NOTES:

This routine is coded for Intel ASM86. It is not set up as an
HLL-callable routine.
This code assumes that the 80Cl87 has already been initialized.
assume cs:code, ds:data

data

segment at OlOOh
r
dd x.xxxx
theta dd x.xxxx
x
dd ?
dd ?
Y
ends

code

segment at 0080h

mov
mov

proc far
ax, data
ds, ax

data

convert

fld
fld
fsincos
fmul
fstp
fmul
fstp

r
theta
st, st(2)
x
y

;substitute real operand
;substitute real operand

;load radius
;load angle
;st=cos, st(l)=sin
;compute x
;store to memory and pop
;compute Y
;store to memory and pop

convert endp
code

ends
end

Example 12-2. Floating Point Math Routine Using FSINCOS

12-16

int:et

ONCE Mode

in1et
CHAPTER 13
ONCE MODE
ONCE (pronounced "ahnce") Mode provides the ability to three-state all output, bidirectional, or
weakly held high/low pins except OSCOUT. To allow device operation with a crystal network,
OSCOUT does not three-state.
ONCE Mode electrically isolates the device from the rest of the board logic. This isolation allows
a bed-of-nails tester to drive the device pins directly for more accurate and thorough testing. An
in-circuit emulation probe uses ONCE Mode to isolate a surface-mounted device from board logic and essentially "take over" operation of the board (without removing the soldered device from
the board).

13.1 ENTERING/LEAVING ONCE MODE
Forcing AI9/0NCE low while RESIN is asserted (low) enables ONCE Mode (see Figure 13-1).
Maintaining AI9/0NCE and RESIN low continues to keep ONCE Mode active. Returning
AI9/0NCE high exits ONCE Mode.
However, it is possible to keep ONCE Mode always active by deasserting RESIN while keeping
AI9/0NCE low. Removing RESIN "latches" ONCE Mode and allows AI9/0NCE to be driven
to any level. A 19/0NCE must remain low for at least one clock beyond the time RESIN is driven
high. Asserting RESIN exits ONCE Mode, assuming AI9/0NCE does not also remain low (see
Figure 13-1).

A19/0NCE
All output,
bidirectional,
weakly held
pins except
OSCOUT
NOTES:

1. Entering ONCE Mode.
2. Latching ONCE Mode.
3. Leaving ONCE Mode (assuming 2 occurred).
A1260-0A

Figure 13-1. Entering/Leaving ONCE Mode

13-1

intet

80C186 Instruction
Set Additions and
Extensions

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APPENDIX A
80C186 INSTRUCTION SET
ADDITIONS AND EXTENSIONS
The 80C 186 Modular Core family instruction set differs from the original 8086/8088 instruction
set in two ways. First, several instructions that were not available in the 8086/8088 instruction set
have been added. Second, several 8086/8088 instructions have been enhanced for the 80C186
Modular Core family instruction set.

A.1

80C186 INSTRUCTION SET ADDITIONS

This section describes the seven instructions that were added to the base 8086/8088 instruction
set to make the instruction set for the 80C186 Modular Core family. These instructions did not
exist in the 8086/8088 instruction set.
• Data transfer instructions
PUSHA
POPA
• String instructions
INS
OUTS
• High-level instructions
ENTER
LEAVE
BOUND

A.1.1

Data Transfer Instructions

PUSHAIPOPA
PUSHA (push all) and POPA (pop all) allow all general-purpose registers to be stacked and unstacked. The PUSHA instruction pushes all CPU registers (except as noted below) onto the stack.
The POPA instruction pops all registers pushed by PUSHA off of the stack. The registers are
pushed onto the stack in the following order: AX, CX, DX, BX, SP, BP, SI, DI. The Stack Pointer
(SP) value pushed is the Stack Pointer value before the AX register was pushed. When POPA is
executed, the Stack Pointer value is popped, but ignored. Note that this instruction does not save
segment registers (CS, DS, SS, ES), the Instruction Pointer (IP), the Processor Status Word or any
integrated peripheral registers.

A-1

80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS

A.1.2

in1et

String Instructions

INS source_string, port
INS (in string) performs block input from an I/O port to memory. The port address is placed in
the DX register. The memory address is placed in the DI register. This instruction uses the ES
segment register (which cannot be overridden). After the data transfer takes place, the pointer register (DI) increments or decrements, depending on the value of the Direction Flag (DF). The
pointer register changes by one for byte transfers or by two for word transfers.
OUTS port, destination_string
OUTS (out string) performs block output from memory to an I/O port. The port address is placed
in the DX register. The memory address is placed in the SI register. This instruction uses the DS
segment register, but this may be changed with a segment override instruction. After the data
transfer takes place, the pointer register (SI) increments or decrements, depending on the value
of the Direction Flag (DF). The pointer register changes by one for byte transfers or by two for
word transfers.

A.1.3

High-Level Instructions

ENTER size, level
ENTER creates the stack frame required by most block-structured high-level languages. The first
parameter, size, specifies the number of bytes of dynamic storage to be allocated for the procedure
being entered (I6-bitvalue). The second parameter, level, is the lexical nesting level of the procedure (8-bit value). Note that the higher the lexical nesting level, the lower the procedure is in
the nesting hierarchy.
The lexical nesting level determines the number of pointers to higher level stack frames copied
into the current stack frame. This list of pointers is called the display. The first word of the display
points to the previous stack frame. The display allows access to variables of higher level (lower
lexical nesting level) procedures.
After ENTER creates a display for the current procedure, it allocates dynamic storage space. The
Stack Pointer decrements by the number of bytes specified by size. All PUSH and POP operations
in the procedure use this value of the Stack Pointer as a base.
Two forms of ENTER exist: non-nested and nested. A lexical nesting level of 0 specifies the nonnested form. In this situation, BP is pushed, then the Stack Pointer is copied to BP and decremented by the size of the frame. If the lexical nesting level is greater than 0, the nested form is used.
Figure A-I gives the formal definition of ENTER.

A-2

intet~

80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS

The following listing gives the formal definition of the
ENTER instruction for all cases.
LEVEL denotes the value of the second operand.
Push BP
Set a temporary value FRAME_PTR: = SP
If LEVEL > 0 then
Repeat (LEVEL - 1) times:
BP:=BP - 2
Push the word pointed to by BP
End Repeat
Push FRAME_PTR
End if
BP:=FRAME_PTR
sp:=sp - first operand

Figure A-1. Formal Definition of ENTER

ENTER treats a reentrant procedure as a procedure calling another procedure at the same lexical
level. A reentrant procedure can address only its own variables and variables of higher-level calling procedures. ENTER ensures this by copying only stack frame pointers from higher-level procedures.
Block-structured high-level languages use lexical nesting levels to control access to variables of
previously nested procedures. For example, assume for Figure A-2 that Procedure A calls Procedure B, which calls Procedure C, which calls Procedure D. Procedure C will have access to the
variables of Main and Procedure A, but not to those of Procedure B because Procedures C and B
operate at the same lexical nesting level.
The following is a summary of the variable access for Figure A-2.
1.

Main has variables at fixed locations.

Procedure A can access only the fixed variables of Main.

Procedure B can access only the variables of Procedure A and Main.
Procedure B cannot access the variables of Procedure C or Procedure D.

Procedure C can access only the variables of Procedure A and Main.
Procedure C cannot access the variables of Procedure B or Procedure D.

Procedure D can access the variables of Procedure C, Procedure A and Main.
Procedure D cannot access the variables of Procedure B.

A-3

intet

80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS

Main Program (Lexical Level 1)
Procedure A (Lexical Level 2)
Procedure B (Lexical Level 3)

Procedure C (Lexical Level 3)
Procedure D (Lexical Level 4)

A1001-0A

Figure A-2. Variable Access in Nested Procedures

The first ENTER, executed in the Main Program, allocates dynamic storage space for Main, but
no pointers are copied_ The only word in the display points to itself because no previous value
exists to return to after LEAVE is executed (see Figure A-3)_

15
OldBP
BPM

•

Display Main
Dynamic
Storage
Main

* BPM = BP Value for MAIN
A1002-0A

Figure A-3. Stack Frame for Main at Level 1

After Main calls Procedure A, ENTER creates a new display for Procedure A. The first word
points to the previous value of BP (BPM). The second word points to the current value of BP
(BPA). BPM contains the base for dynamic storage in Main. All dynamic variables for Main will
be at a fixed offset from this value (see Figure A-4)_

A-4

intet

80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS

0
OldBP
BPM

BPM

--"
~

BPM
BPA·

}

DisplayA

}

Dynamic
Storage A

•BPA --

BP Value for Procedure A
Al003·0A

Figure A-4. Stack Frame for Procedure A at Level 2

After Procedure A calls Procedure B, ENTER creates the display for Procedure B. The first word
of the display points to the previous value of BP (BPA). The second word points to the value of
BP for MAIN (BPM). The third word points to the BP for Procedure A (BPA). The last word
points to the current BP (BPB). Procedure B can access variables in Procedure A or Main via the
appropriate BP in the display (see Figure A-5).
After Procedure B calls Procedure C, ENTER creates the display for Procedure C. The first word
of the display points to the previous value of BP (BPB). The second word points to the value of
BP for MAIN (BPM). The third word points to the value of BP for Procedure A (BPA). The fourth
word points to the current BP (BPC). Because Procedure B and Procedure C have the same lexical
nesting level, Procedure C cannot access variables in Procedure B. The only pointer to Procedure
B in the display of Procedure C exists to allow the LEAVE instruction to collapse the Procedure
C stack frame (see Figure A-6).

A-5

80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS

OldBP
BPM

BPM
BPM
BPA

BPA
BPM
BPA
BPB

}

Display B

}

Dynamic

Storage B

A1004-0A

Figure A-S. Stack Frame for Procedure B at Level 3 Called from A

A-6

80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS

OldBP
BPM

BPM
BPM
BPA

BPA
BPM
BPA
BPB

BPB
BPM
BPA
BPC

}
}

DisplayC

Dynamic
Storage C

-""
~

A1005-0A

Figure A-6. Stack Frame for Procedure C at Level 3 Called from B

LEAVE
LEAVE reverses the action of the most recent ENTER instruction. It collapses the last stack frame
created. First, LEAVE copies the current BP to the Stack Pointer, releasing the stack space allocated to the current procedure. Second, LEAVE pops the old value ofBP from the stack, to return
to the calling procedure's stack frame. A RET instruction will remove arguments stacked by the
calling procedure for use by the called procedure.

A-7

80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS

BOUND register, address
BOUND verifies that the signed value in the specified register lies within specified limits. If the
value does not lie within the bounds, an array bounds exception (type 5) occurs. BOUND is useful
for checking array bounds before attempting to access an array element. This prevents the program from overwriting information outside the limits of the array.
BOUND has two operands. The first, register, specifies the register being tested. The second, address, contains the effective relative address of the two signed boundary values. The lower limit
word is at this address and the upper limit word immediately follows. The limit values cannot be
register operands (if they are, an invalid opcode exception occurs).

A.2

80C186 INSTRUCTION SET ENHANCEMENTS

This section describes ten instructions that were available with the 8086/8088 but have been enhanced for the 80C186 Modular Core family.
• Data transfer instructions
-

PUSH

• Arithmetic instructions
IMUL
• Bit manipulation instructions (shifts and rotates)
SAL
SHL
SAR
SHR
ROL
ROR
RCL
RCR

A.2.1

Data Transfer Instructions

PUSH data
PUSH (push immediate) allows an immediate argument, data, to be pushed onto the stack. The
value can be either a byte or a word. Byte values are sign extended to word size before being
pushed.

A-8

intet
A.2.2

80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS

Arithmetic Instructions

IMUL destination, source, data
IMUL (integer immediate multiply, signed) allows a value to be multiplied by an immediate operand. IMUL requires three operands. The first, destination, is the register where the result will
be placed. The second, source, is the effective address of the multiplier. The source may be the
same register as the destination, another register or a memory location. The third, data, is an immediate value used as the multiplicand. The data operand may be a byte or word. If data is a byte,
it is sign extended to 16 bits. Only the lower 16 bits of the result are saved. The result must be
placed in a general-purpose register.

A.2.3

Bit Manipulation Instructions

This section describes the eight enhanced bit-manipulation instructions.
A.2.3.1

Shift Instructions

SAL destination, count
SAL (immediate shift arithmetic left) shifts the destination operand left by an immediate value.
SAL has two operands. The first, destination, is the effective address to be shifted. The second,
count, is an immediate byte value representing the number of shifts to be made. The CPU will
AND count with IFH before shifting, to allow no more than 32 shifts. Zeros shift in on the right.

SHL destination, count
SHL (immediate shift logical left) is physically the same instruction as SAL (immediate shift
arithmetic left).

SAR destination, count
SAR (immediate shift arithmetic right) shifts the destination operand right by an immediate value. SAL has two operands. The first, destination, is the effective address to be shifted. The second, count, is an immediate byte value representing the number of shifts to be made. The CPU
will AND count with IFH before shifting, to allow no more than 32 shifts. The value of the original sign bit shifts into the most-significant bit to preserve the initial sign.

SHR destination, count
SHR (immediate shift logical right) is physically the same instruction as SAR (immediate shift
arithmetic right).

A·9

80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS

A.2.3.2

Rotate Instructions

ROL destination, count
ROL (immediate rotate left) rotates the destination byte or word left by an immediate value. ROL
has two operands. The first, destination, is the effective address to be rotated. The second, count,
is an immediate byte value representing the number of rotations to be made. The most-significant
bit of destination rotates into the least-significant bit.

ROR destination, count
ROR (immediate rotate right) rotates the destination byte or word right by an immediate value.
ROR has two operands. The first, destination, is the effective address to be rotated. The second,
count, is an immediate byte value representing the number of rotations to be made. The least-significant bit of destination rotates into the most-significant bit.

RCL destination, count
RCL (immediate rotate through carry left) rotates the destination byte or word left by an immediate value. RCL has two operands. The first, destination, is the effective address to be rotated.
The second, count, is an immediate byte value representing the number of rotations to be made.
The Carry Flag (CF) rotates into the least-significant bit of destination. The most-significant bit
of destination rotates into the Carry Flag.

RCR destination, count
RCR (immediate rotate through carry right) rotates the destination byte or word right by an immediate value. RCR has two operands. The first, destination, is the effective address to be rotated.
The second, count, is an immediate byte value representing the number of rotations to be made.
The Carry Flag (CF) rotates into the most-significant bit of destination. The least-significant bit
of destination rotates into the Carry Flag.

A-10

intel·

Input
Synchronization

APPENDIX B
INPUT SYNCHRONIZATION
Many input signals to an embedded processor are asynchronous. Asynchronous signals do not require a specified setup or hold time to ensure the device does not incur a failure. However, asynchronous setup and hold times are specified in the data sheet to ensure recognition. Associated
with each of these inputs is a synchronizing circuit (see Figure B-1) that samples the asynchronous signal and synchronizes it to the internal operating clock. The output of the synchronizing
circuit is then safely routed to the logic units.
Asynchronous
Input

1----10

9 or (AF) = 1
then
(AL) ~ (AL) + 6
(AH) ~ (AH) + 1
(AF) ~ 1
(CF) ~ (AF)
(AL) ~ (AL) and OFH

Flags
Affected
AF ./
CF ./
DFIF OF?
PF?
SF?
TF ZF?

(AL) ~ (AH) x OAH + (AL)
(AH) ~O

AF?
CF?
DFIF OF?
PF ./
SF ./
TF ZF ./

(AH) ~ (AL) / OAH
(AL) ~ (AL) % OAH

AF?
CF?
DFIF OF?
PF ./
SF ./
TF ZF ./

Modifies the numerator in AL before
dividing two valid unpacked decimal
operands so that the quotient
produced by the division will be a valid
unpacked decimal number. AH must
be zero for the subsequent DIV to
produce the correct result. The
quotient is returned in AL, and the
remainder is returned in AH; both highorder half-bytes are zeroed.
Instruction Operands:
none
AAM

ASCII Adjust for Multiply:
AAM
Corrects the result of a previous multiplication of two valid unpacked
decimal operands. A valid 2-digit
unpacked decimal humber is derived
from the content of AH and AL and is
returned to AH and AL. The high-order
half-bytes of the multiplied operands
must have been OH for AAM to
produce a correct result.
Instruction Operands:
none

NOTE:

C-4

The three symbols used in the Flags Affected column are defined as follOWS:
- the contents of the flag remain unchanged after the instruction Is executed
? the contents of the flag is undefined after the instruction is executed
./the flag is updated after the instruction is executed

int'et

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Description

Name
AAS

ASCII Adjust for Subtraction:
AAS
Corrects the result of a previous
subtraction of two valid unpacked
decimal operands (the destination
operand must have been specified as
register AL). Changes the content of
AL to a valid unpacked decimal
number; the high-order half-byte is
zeroed.

Flags
Affected

Operation
if
((AL) and OFH) > 9 or (AF)
then
(AL) f- (AL) - 6
(AH) f- (AH) - 1
(AF) f- 1
(CF) f- (AF)
(AL) f- (AL) and OFH

AF v'
CF v'
DFIF OF?
PF?
SF?
TF ZF?

Instruction Operands:
none
ADC

Add with Carry:
ADC desf, src
Sums the operands, which may be
bytes or words, adds one if CF is set
and replaces the destination operand
with the result. Both operands may be
signed or unsigned binary numbers
(see AAA and DAA). Since ADC incorporates a carry from a previous
operation, it can be used to write
routines to add numbers longer than
16 bits.

(CF) 1
then
(dest) f- (dest) + (src) + 1
else
(dest) f- (dest) + (src)

AF v'
CF v'
DFIF OF v'
PF v'
SF v'
TF ZF v'

Instruction Operands:
ADC
ADC
ADC
ADC
ADC
ADC

NOTE:

reg, reg
reg, mem
mem, reg
reg, immed
mem, immed
accurh, immed

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
v'the flag is updated after the instruction is executed

C-5

INSTRUCTION SET DESCRIPTIONS
Table C~4. Instruction Set (Continued)
Name
ADD

Description
Addition:

Operation

Flags
Affected

(dest) +- (dest) + (src)

AF ,/
CF ,/
DFIF OF ,/
PF ,/
SF ,/
TF ZF ,/

(dest) +- (dest) and (src)
(CF) +- 0
(OF) +- 0

AF?
CF ,/
DFIF OF ,/
PF ,/
SF ,/
TF ZF ,/

ADD dest, src
Sums two operands, which may be
bytes or words, replaces the
destination operand. Both operands
may be signed or unsigned binary
numbers (see AAA and DAA).
Instruction Operands:
ADD reg, reg
ADD reg, mem
ADDmem, reg
ADD reg, immed
ADD mem, immed
ADD accum, immed
AND

And Logical:
AND dest, src
Performs the logical "and" of the two
operands (byte or word) and retums
the result to the destination operand. A
bit in the result is set If both corresponding bits of the original operands
are set; otherwise the bit Is cleared.
Instruction Operands:
AND reg, reg
AND reg, mem
ANDmem, reg
AND reg, Immed
AND mem, immed
AND accum, immed

NOTE:

C-6

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
'/the flag is updated after the Instruction is executed

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
BOUND

Description
Detect Value Out of Range:
BOUND dest, src
Provides array bounds checking in
hardware. The calculated array index
is placed in one of the general purpose
registers, and the upper and lower
bounds of the array are placed in two
consecutive memory locations. The
contents of the register are compared
with the memory location values, and if
the register value is less than the first
location or greater than the second
memory location, a trap type 5 is
generated.

Operation
if
({dest) < (src) or (dest) > ((src) + 2)
then
(SP) ~ (SP) - 2
((SP) + 1 : (SP)) ~ FLAGS
(IF)~O

(TF) ~ 0
(SP) ~ (SP) - 2
((SP) + 1 : (SP)) ~ (CS)
(CS) ~ (1EH)
(SP) ~ (SP) - 2
((SP) + 1 : (SP)) ~ (IP)
(IP) ~ (1CH)

Flags
Affected
AF CFDFIF OFPFSFTF ZF -

Instruction Operands:
BOUND reg, mem
CALL

Call Procedure:
CALL procedure-name
Activates an out-of-line procedure,
saving information on the stack to
permit a RET (return) instruction in the
procedure to transfer control back to
the instruction following the CALL. The
assembler generates a different type
of CALL instruction depending on
whether the programmer has defined
the procedure name as NEAR or FAR.

if
Inter-segment
then
(SP) ~ (SP) - 2
((SP) + 1:(SP)) ~ (CS)
(CS)~SEG

(SP) ~ (SP) - 2
((SP) +1:(SP)) ~ (IP)
(IP) ~ dest

AFCFDFIF OFPFSFTF ZF -

Instruction Operands:
CALL near-proc
CALL far-proc
CALL memptr16
CALL regptr16
CALL memptr32
NOTE:

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
'(the flag is updated after the instruction is executed

C-7

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Description

Name
CBW

Convert Byte to Word:
CBW
Extends the sign of the byte in register
AL throughout register AH. Use to
produce a double-length (word)
dividend from a byte prior to
performing byte division.

Operation
if
(AL) < SOH
then
(AH) ~ 0
else
(AH) ~ FFH

Instruction Operands:

Flags
Affected
AFCFOFIF OFPF SF TF ZF -

none
CLC

Clear Carry flag:

(CF)

AFCF ,(
OFIF OFPFSF TF ZF -

(OF)

AFCFOF ,(
IF OFPF SF TF ZF -

CLC
Zeroes the carry flag (CF) and affects
no other flags. Useful in conjunction
with the rotate through carry left (RCL)
and the rotate through carry right
(RCR) instructions.
Instruction Operands:
none
CLO

Clear Direction flag:
CLO
Zeroes the direction flag (OF) causing
the string instructions to autoincrement the source index (SI) and/or
destination index (01) registers.
Instruction Operands:
none

NOTE:

C-8

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
'(the flag is updated after the instruction is executed

int'et

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Description

Name
CLI

Clear Interrupt-enable Flag:

Operation
(IF)~O

CLI
Zeroes the interrupt-enable flag (I F).
When the interrupt-enable flag is
cleared, the 8086 and 8088 do not
recognize an external interrupt request
that appears on the INTR line; in other
words maskable interrupts are
disabled. A non-maskable interrupt
appearing on NMI line, however, is
honored, as is a software interrupt.

Flags
Affected
AFCFDFIF
OFPFSFTF ZF -

Instruction Operands:
none
CMC

Complement Carry Flag:
CMC
Toggles complement carry flag (CF) to
its opposite state and affects no other
flags.

AF -

(CF)=O
then
(CF)~ 1
else

CF '"
DFIF OFPF SF TF ZF -

(CF)~O

Instruction Operands:
none
NOTE:

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the Instruction is executed
"'the flag is updated after the instruction is executed

C-g

intel«t

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Description

Name
CMP

Compare:

Operation

Flags
Affected

(dest) - (src)

AF v'
CF v'
OFIF OFv'
PF v'
SF v'
TF ZF v'

(dest-string) - (src-string)
if
(OF) = 0
then
(SI) +- (SI) + DELTA
(01) +- (01) + DELTA
else
(SI) +- (SI) - DELTA
(01) +- (01) - DELTA

AF v'
CF v'
OFIF OFv'
PF v'
SF v'
TF ZF v'

CMP dest, src
Subtracts the source from the desti·
nation, which may be bytes or words,
but does not return the result. The
operands are unchanged, but the flags
are updated and can be tested by a
subsequent conditional Jump
Instruction. The comparison reflected
In the flags Is that of the destination to
the source. If a CMP Instruction Is
followed by a JG Oump if greater)
Instruction, for example, the Jump Is
taken if the destination operand is
greater than the source operand.
Instruction Operands:
CMP reg, reg
CMP reg, mem
CMPmem, reg
CMP reg, immed
CMP mem, Immed
CMP accum, immed
CMPS

Compare String:
CMPS dest-string, src-string
Subtracts the destination byte or word
from the source byte or word. The
destination byte or word Is addressed
by the destination Index (01) register
and the source byte or word is
addresses by the source index (SI)
register. CMPS updates the flags to
reflect the relationship of the
destination element to the source
element but does not alter either
operand and updates SI and 01 to
pOint to the next string element.
Instruction Operands:
CMP dest-string, src-string
CMP (repeat) dest-string, src-strlng

NOTE: The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the Instruction Is executed
? the contents of the flag is undefined after the Instruction Is executed
v'the flag is updated after the instruction Is executed

C-10

intet~

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
CWO

Description
Convert Word to Doubleword:
CWO
Extends the sign of the word in register
AX throughout register OX. Use to
produce a double·length (doubleword)
dividend from a word prior to
performing word division.

Flags
Affected

Operation
if

AFCFOFIF OFPFSF TF ZF -

(AX) < BOOOH
then
(OX) f- 0
else
(OX) f- FFFFH

Instruction Operands:
none
OAA

Decimal Adjust for Addition:
OAA
Corrects the result of previously
adding two valid packed decimal
operands (the destination operand
must have been register AL). Changes
the content of AL to a pair of valid
packed decimal digits.
Instruction Operands:

if
((AL) and OFH) > 9 or (AF)
then
(AL) f- (AL) + 6
(AF) f- 1
if
(AL) > 9FH or (CF) 1
then
(AL) f- (AL) + 60H
(CF) f- 1

AF v'
CF v'
OFIF OF?
PF v'
SF v'
TF ZF v'

none
OAS

Decimal Adjust for Subtraction:
OAS
Corrects the result of a previous
subtraction of two valid packed
decimal operands (the destination
operand must have been specified as
register AL). Changes the content of
AL to a pair of valid packed decimal
digits.

if
((AL) and OFH) > 9 or (AF)
then
(AL) f- (AL) - 6
(AF) f- 1
if
(AL) > 9FH or (CF) 1
then
(AL) f- (AL) - 60H
(CF) f- 1

AF v'
CF v'
OFIF OF?
PF v'
SF v'
TF ZF v'

Instruction Operands:
none
NOTE:

C-11

intet~

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name

DEC

Description
Decrement:

Operation

(dest)

(dest) - 1

DEC dest
Subtracts one from the destination
operand. The operand may be a byte
or a word and is treated as an
unsigned binary number (see AAA and
DAA).
Instruction Operands:

Flags
Affected
AF ,f
CFDFIF OF ,f
PF ,f
SF ,f
TF ZF ,f

DEC reg
DECmem
NOTE:

C-12

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
,fthe flag is updated after the instruction is executed

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Description

Name
OIV

Divide:
OIV

src

Performs an unsigned division of the
accumulator (and its extension) by the
source operand.
If the source operand is a byte, it is
divided into the two-byte dividend
assumed to be in registers AL and AH.
The byte quotient is returned in AL,
and the byte remainder is returned in
AH.
If the source operand is a word, it is
divided into the two-word dividend in
registers AX and OX. The word
quotient is returned in AX, and the
word remainder is returned in OX.
If the quotient exceeds the capacity of
its destination register (FFH for byte
source, FFFFH for word source), as
when division by zero is attempted, a
type 0 interrupt is generated, and the
quotient and remainder are undefined.
Nonintegral quotients are truncated to
integers.
Instruction Operands:
OIV reg
OIVmem

NOTE:

Operation
When Source Operand Is a Byte:
(temp) f- (byte-src)
if
(temp) I (AX) > FFH
then (type 0 interrupt is generated)
(SP) f- (SP) - 2
((SP) + 1:(SP)) f- FLAGS
(IF) f- 0
(TF) f- 0
(SP) f- (SP) - 2
((SP) + 1:(SP)) f- (CS)
(CS) f- (2)
(SP) f- (SP) - 2
((SP) + 1:(SP)) f- (IP)
(IP) f- (0)
else
(AL) f- (temp) I (AX)
(AH) f- (temp) % (AX)

Flags
Affected
AF?
CF?
OFIF OF?
PF?
SF?
TF ZF?

When Source Operand is a Word:
(temp) f- (word-src)
if
(temp) I (OX:AX) > FFFFH
then (type 0 interrupt is generated)
(SP) f- (SP) - 2
((SP) + 1:(SP)) f- FLAGS
(IF) f- 0
(TF) f- 0
(SP) f- (SP) - 2
((SP) + 1:(SP)) f- (CS)
(CS) f- (2)
(SP) f- (SP) - 2
((SP) + 1:(SP)) f- (IP)
(lP) f- (0)
else
(AX) f- (temp) I (OX:AX)
(OX) f- (temp) % (OX:AX)

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
.Ithe flag is updated after the instruction is executed

C-13

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
ENTER

Description
Procedure Entry:
ENTER locals, levels
Executes the calling sequence for a
high-level language. It saves the
current frame pOinter in BP, copies the
frame pOinters from procedures below
the current call (to allow access to
local variables in these procedures)
and allocates space on the stack for
the local variables of the current
procedure invocation.
Instruction Operands:
ENTER locals, level

ESC

Escape:
ESC
Provides a mechanism by which other
processors (coprocessors) may
receive their instructions from the 8086
or 8088 instruction stream and make
use of the 8086 or 8088 addressing
modes. The CPU (8086 or 8088) does
a no operation (NOP) for the ESC
instruction other than to access a
memory operand and place it on the
bus.

Operation

Flags
Affected

(SP) f- (SP) - 2
((SP) + 1:(SP)) f- (BP)
(FP) f- (SP)
if
level>
then
repeat (level - 1) times
(BP) f- (BP) - 2
(SP) f- (SP) - 2
((SP) + 1:(SP)) f- (BP)
end repeat
(SP) f- (SP) - 2
((SP) + 1:(SP)) f- (FP)
end if
(BP) f- (FP)
(SP) f- (SP) - (locals)

AF CFDFIF OFPF SFTF ZF -

AF CFDFIF OFPF SF TF ZF -

mod;c 11
then
data bus f- (EA)

Instruction Operands:
ESC immed, mem
ESC immed, reg
NOTE:

C-14

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
'(the flag is updated after the instruction is executed

intet

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Description

Name
HLT

Halt:

Operation
None

HLT
Causes the CPU to enter the halt
state. The processor leaves the halt
state upon activation of the RESET
line, upon receipt of a non-maskable
interrupt request on NMI, or upon
receipt of a maskable interrupt request
on INTR (if interrupts are enabled).

Flags
Affected
AFCFDFIF OFPFSFTF ZF -

Instruction Operands:
none
NOTE:

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
'(the flag is updated after the instruction is executed

C-15

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
IDIV

Description
Integer Divide:
IOIV

src

Performs a signed division of the
accumulator (and its extension) by the
source operand. If the source operand
is a byte, it is divided into the doublelength dividend assumed to be in
registers AL and AH; the single-length
quotient is returned in AL, and the
single-length remainder is returned in
AH. For byte integer division, the
maximum positive quotient is +127
(7FH) and the minimum negative
quotient is -127 (81 H).
If the source operand is a word, it is
divided into the double-length dividend
in registers AX and OX; the singlelength quotient is returned in AX, and
the single-length remainder is returned
in OX. For word integer division, the
maximum positive quotient is +32,767
(7FFFH) and the minimum negative
quotient is-32,767 (8001H).
If the quotient is positive and exceeds
the maximum, or is negative and is
less than the minimum, the quotient
and remainder are undefined, and a
type 0 interrupt is generated. In
particular, this occurs if division by 0 is
attempted. Nonintegral quotients are
truncated (toward 0) to integers, and
the remainder has the same sign as
the dividend.
Instruction Operands:
IOIV reg
IOIVmem

NOTE.

C-16

Operation
When Source Operand is a Byte:
(temp) f- (byte-src)
if
(temp) / (AX) > 0 and
(temp) I (AX) > 7FH or
(temp) I (AX) < 0 and
(temp) I (AX) < 0 - 7FH - 1
then (type 0 interrupt is generated)
(SP) f- (SP) - 2
((SP) + 1:(SP)) f- FLAGS
(IF) f- 0
(TF) f- 0
(SP) f- (SP) - 2
((SP) + 1:(SP)) f- (CS)
(CS) f- (2)
(SP) f- (SP) - 2
((SP) + 1:(SP)) f- (IP)
(IP) f- (0)
else
(AL) f- (temp) / (AX)
(AH) f- (temp) % (AX)

Flags
Affected
AF?
CF?
OFIF OF?
PF?
SF?
TF ZF?

When Source Operand is a Word:
(temp) f- (word-src)
if
(temp) I (OX:AX) > 0 and
(temp) I (OX:AX) > 7FFFH or
(temp) I (OX:AX) < 0 and
(temp) I (OX:AX) < 0 - 7FFFH - 1
then (type 0 interrupt is generated)
(SP) f- (SP) - 2
((SP) + 1:(SP)) f- FLAGS
(IF) f- 0
(TF) f- 0
(SP) f- (SP) - 2
((SP) + 1:(SP)) f- (CS)
(CS) f- (2)
(SP) f- (SP) - 2
((SP) + 1:(SP)) f- (IP)
(IP) f- (0)
else
(AX) f- (temp) I (OX:AX)
(OX) f- (temp) % (OX:AX)

The three symbols used In the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
"the flag is updated after the instruction is executed

intet

INSTRUCTION SET DESCRIPTIONS

Table C-4_ Instruction Set (Continued)
Description

Name
IMUL

Integer Multiply:
IMUL sre
Performs a signed multiplication of the
source operand and the accumulator.
If the source is a byte, then it is
multiplied by register AL, and the
double-length result is returned in AH
and AL. If the source is a word, then it
is multiplied by register AX, and the
double-length result is returned in
registers OX and AX. If the upper half
of the result (AH for byte source, OX
for word source) is not the sign
extension of the lower half of the
result, CF and OF are set; otherwise
they are cleared. When CF and OF are
set, they indicate that AH or OX
contains significant digits of the result.

Operation
When Source Operand is a Byte:
(AX) f- (byte-src) x (AL)
if
(AH) =sign-extension of (AL)
then
(CF) f- 0
else
(CF) f- 1
(OF) f- (CF)

Flags
Affected
AF?
CF ,(
OFIF OF ,(
PF?
SF?
TF ZF?

When Source Operand is a Word:
(OX:AX) f- (word-src) x (AX)
if
(OX) =sign-extension of (AX)
then
(CF) f- 0
else
(CF) f- 1
(OF) f- (CF)

Instruction Operands:
IMUL reg
IMULmem
IMULimmed
Input Byte or Word:

IN aeeum, port
Transfers a byte or a word from an
input port to the AL register or the AX
register, respectively. The port number
may be specified either with an
immediate byte constant, allowing
access to ports numbered 0 through
255, or with a number previously
placed in the OX register, allowing
variable access (by changing the value
in OX) to ports numbered from 0
through 65,535.

When Source Operand is a Byte:
(AL)

(port)

When Source Operand is a Word:
(AX)

(port)

AF CFOFIF OFPFSF TF ZF -

Instruction Operands:
IN AL, immed8
IN AX, OX
NOTE:

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
'(the flag is updated after the instruction is executed

C-17

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Description

Name
INC

Increment:

Operation
(dest)

(dest) + 1

INC dest
Adds one to the destination operand.
The operand may be byte or a word
and is treated as an unsigned binary
number (see AAA and OAA).
Instruction Operands:
INC reg
INCmem
INS

In String:

(dest) ~ (src)

INS dest-string, port
Performs block input from an 1/0 port
to memory. The port address is placed
in the OX register. The memory
address is placed in the 01 register.
This instruction uses the ES register
(which cannot be overridden). After the
data transfer takes place, the 01
register increments or decrements,
depending on the value of the direction
flag (OF). The 01 register changes by 1
for byte transfers or 2 for word
transfers.

Flags
Affected
AF ,/
CFOFIF OF ,/
PF ,/
SF ,/
TF ZF ,/

AF CFOFIF OFPF SF TF ZF -

Instruction Operands:
INS dest-string, port
INS (repeat) dest-string, port
NOTE:

C-18

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
'/the flag is updated after the instruction is executed

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
INT

Description
Interrupt:
INT interrupt-type
Activates the interrupt procedure
specified by the interrupt-type
operand. Decrements the stack pointer
by two, pushes the flags onto the
stack, and clears the trap (TF) and
interrupt-enable (IF) flags to disable
single-step and maskable interrupts.
The flags are stored in the format used
by the PUSHF instruction. SP is
decremented again by two, and the CS
register is pushed onto the stack.

Operation
(SP) ~ (SP) - 2
«SP) + 1:(SP)) ~ FLAGS
(IF) ~ 0
(TF) ~ 0
(SP) ~ (SP) - 2
«SP) + 1:(SP)) ~ (CS)
(CS) ~ (interrupt-type x 4 + 2)
(SP) ~ (SP) - 2
«SP) + 1:(SP)) ~ (I P)
(IP) ~ (interrupt-type x 4)

Flags
Affected
AFCFDFIF ,/
OFPF SF TF ,/
ZF -

The address of the interrupt pointer is
calculated by multiplying interrupttype by four; the second word of the
interrupt painter replaces CS. SP
again is decremented by two, and I P is
pushed onto the stack and is replaced
by the first word of the interrupt painter.
If interrupt-type 3, the assembler
generates a short (1 byte) form of the
instruction, known as the breakpoint
interrupt.

Instruction Operands:
INT immed8
NOTE:

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
'/the flag is updated after the instruction is executed

C-19

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
INTO

Description
Interrupt on Overflow:
INTO
Generates a software interrupt if the
overflow flag (OF) is set; otherwise
control proceeds to the following
instruction without activating an
interrupt procedure. INTO addresses
the target Interrupt procedure (its type
is 4) through the interrupt pOinter at
location 10H; it clears the TF and IF
flags and otherwise operates like INT.
INTO may be written following an
arithmetic or logical operation to
activate an interrupt procedure if
overflow occurs.

Operation
if
(OF) = 1
then
(SP) +- (SP) - 2
((SP) + 1:(SP» +- FLAGS
(IF) +- 0
(TF) +- 0
(SP) +- (SP) - 2
((SP) + 1:(SP» +- (CS)
(CS) +- (12H)
(SP) +- (SP) - 2
((SP) + 1:(SP» +- (IP)
(IP) +- (10H)

Flags
Affected
AF CFOFIF OFPF SF TF ZF -

Instruction Operands:
none
IRET

Interrupt Return:
IRET
Transfers control back to the point of
interruption by popping IP, CS, and the
flags from the stack. IRET thus affects
all flags by restoring them to previously
saved values. IRET is used to exit any
interrupt procedure, whether activated
by hardware or software.

(IP) +- ((SP) + 1:(SP»
(SP) +- (SP) + 2
(CS) +- ((SP) + 1 :(SP»
(SP) +- (SP) + 2
FLAGS +- ((SP) + 1:(SP»
(SP) +- (SP) + 2

AF
CF
OF
IF
OF
PF
SF
TF
ZF

AF CFOFIF OFPF SF TF ZF -

./
./
./
./
./
./
./
./
./

Instruction Operands:
none
JA
JNBE

Jump on Above:
Jump on Not Below or Equal:
JA disp8
JNBE disp8

((CF) = 0) or ((ZF) = 0)
then
(IP) +- (lP) + disp8 (sign-ext to 16 bits)

Transfers control to the target location
if the tested condition ((CF=O) or
(ZF=O» is true.
Instruction Operands:
JA short-label
JNBE short-label
NOTE:

C-20

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
./the flag is updated after the instruction is executed

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
JAE
JNB

Description
Jump on Above or Equal:
Jump on Not Below:
JAE disp8
JNB disp8

Operation
if
(CF) = 0
then
(I P) f- (I P) + disp8 (sign-ext to 16 bits)

Transfers control to the target location
if the tested condition (CF = 0) is true.
Instruction Operands:
JAE short-label
JNB short-label
JB
JNAE

Jump on Below:
Jump on Not Above or Equal:
JB disp8
JNAE disp8

if
(CF) = 1
then
(IP) f- (IP) + disp8 (sign-ext to 16 bits)

Transfers control to the target location
if the tested condition (CF = 1) is true.
Instruction Operands:
JB short-label
JNAE short-label
JBE
JNA

Jump on Below or Equal:
Jump on Not Above:
JBE disp8
JNA disp8

if
«CF) = 1) or «ZF) = 1)
then
(I P) f- (I P) + disp8 (sign-ext to 16 bits)

Transfers control to the target location
if the tested condition «C =1) or
(ZF=1)) is true.
Instruction Operands:

Flags
Affected
AF CFDFIF OFPF SFTF ZF AF CFDFIF OFPF SF TF ZF AFCFDFIF OFPFSFTF ZF -

JBE short-label
JNA short-label
JC

Jump on Carry:
JC disp8
Transfers control to the target location
if the tested condition (CF=1) is true.

if
(CF) = 1
then
(IP) f- (IP) + disp8 (sign-ext to 16 bits)

Instruction Operands:
JC short-label

NOTE:

AFCFDFIF OFPFSFTF ZF -

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
,l'the flag is updated after the instruction is executed

C-21

intel·

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
JCXZ

Description
Jump If ex Zero:
JCXZ dispB
Transfers control to the target location
if CX is O. Useful at the beginning of a
loop to bypass the loop If CX has a
zero value, I.e., to execute the loop
zero times.

Operation
If
(CX) = 0
then
(IP) +- (IP) + disp8 (sign-ext to 16 bits)

Instruction Operands:

Flags
Affected
AFCFDFIF OFPFSFTF ZF -

JCXZ short-label
JE
JZ

Jump on Equal:
Jump on Zero:
JE dispB
JZ dispB

If
(ZF) = 1
then
(IP) +- (IP) + disp8 (sign-ext to 16 bits)

Transfers control to the target location
If the condition tested (ZF = 1) is true.
Instruction Operands:
JE short-label
JZ short-label
JG
JNLE

Jump on Greater Than:
Jump on Not Less Than or Equal:
JG dlspB
JNLE dlspB

if
«SF) = (OF» and «ZF) = 0)
then
(IP) +- (IP) + disp8 (sign-ext to 16 bits)

Transfers control to the target location
if the condition tested (SF = OF) and
(ZF=O) is true.
Instruction Operands:

AFCFDFIF OFPF SFTF ZF AFCFDFIF OFPFSF TF ZF -

JG short-label
JNLE short-label
JGE
JNL

Jump on Greater Than or Equal:
Jump on Not Less Than:
JGE dispB
JNL dlspB

If
(SF) = (OF)
then
(IP) +- (IP) + dlsp8 (sign-ext to 16 bits)

Transfers control to the target location
Hthe condition tested (SF=OF) is true.
Instruction Operands:
JGE short-label
JNL short-label
NOTE:

C-22

AFCFDFIF OFPFSF TF ZF -

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the Instruction Is executed
"'the flag Is updated after the Instruction Is executed

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
JL
JNGE

Description
Jump on Less Than:
Jump on Not Greater Than or Equal:
JL disp8
JNGE disp8

Operation
if
(SF) "'- (OF)
then
(IP) ~ (IP) + disp8 (sign-ext to 16 bits)

Transfers control to the target location
if the condition tested (SF~F) is true.
Instruction Operands:
JL short-label
JNGE short-label
JLE
JNG

Jump on Less Than or Equal:
Jump on Not Greater Than:
JGE disp8
JNL disp8

if
((SF) "'- (OF)) or ((ZF) = 1)
then
(IP) ~ (IP) + disp8 (sign-ext to 16 bits)

Transfers control to the target location
If the condition tested ((SF"'-OF) or
(ZF=O)) is true.
Instruction Operands:

Flags
Affected
AFCFDFIF OFPF SF TF ZF AFCFDFIF OFPFSFTF ZF -

JGE short-label
JNL short-label
JMP

Jump Unconditionally:
JMP target
Transfers control to the target location.
Instruction Operands:

if
Inter-segment
then
(CS) ~ SEG
(IP) ~ dest

JMP short-label
JMP near-label
JMP far-label
JMP memptr
JMP regptr
JNC

Jump on Not Carry:
JNC disp8
Transfers control to the target location
if the tested condition (CF=O) is true.

if
(CF) = 0
then
(I P) ~ (I P) + disp8 (sign-ext to 16 bits)

Instruction Operands:
JNC short-label

NOTE:

AF CFDFIF OFPFSF TF ZF AFCFDFIF OFPFSFTF ZF -

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
'(the flag is updated after the instruction is executed

C-23

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
JNE
JNZ

Description
Jump on Not Equal:
Jump on Not Zero:
JNE disp8
JNZ disp8

Operation
if
(ZF) = 0
then
(IP) ~ (IP) + disp8 (sign-ext to 16 bits)

Transfers control to the target location
if the tested condition (ZF = 0) is true.
Instruction Operands:
JNE short-label
JNZ short-label
JNO

Jump on Not Overflow:
JNO disp8
Transfers control to the target location
if the tested condition (OF = 0) is true.

if
(OF) = 0
then
(I P) ~ (IP) + disp8 (sign-ext to 16 bits)

Instruction Operands:
JNO short-label

JNS

Jump on Not Sign:
JNS disp8
Transfers control to the target location
if the tested condition (SF = 0) is true.

if
(SF) = 0
then
(IP) ~ (IP) + disp8 (sign-ext to 16 bits)

Instruction Operands:
JNS short-label

JNP
JPO

Jump on Not Parity:
Jump on Parity Odd:
JNO disp8
JPO disp8

if
(PF) = 0
then
(IP) ~ (IP) + disp8 (sign-ext to 16 bits)

Transfers control to the target location
if the tested condition (PF=O) is true.
Instruction Operands:
JNO short-label
JPO short-label
NOTE:

C-24

Flags
Affected
AFCFDFIF OFPF SF TF ZF AFCFDFIF OFPF SF TF ZF AF CFDFIF OFPFSFTF ZF AF CFDFIF OFPF SF TF ZF -

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
'(the flag is updated after the instruction is executed

intet

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Description

Name
JO

Operation

Jump on Overflow:

JO disp8
Transfers control to the target location
if the tested condition (OF 1) is true.

(OF) 1
then
(IP) ~ (IP) + disp8 (sign-ext to 16 bits)

Instruction Operands:
JO short-label

JP
JPE

Jump on Parity:
Jump on Parity Equal:

(PF) 1
then
(IP) ~ (lP) + disp8 (sign-ext to 16 bits)

JP disp8
JPE disp8
Transfers control to the target location
if the tested condition (PF 1) is true.

Instruction Format:
JP short-label
JPE short-label
JS

Jump on Sign:

JS disp8
Transfers control to the target location
if the tested condition (SF 1) is true.

(SF) 1
then
(I P) ~ (I P) + disp8 (sign-ext to 16 bits)

Instruction Format:
JS short-label

LAHF

Load Register AH From Flags:

(AH)

(SF):(ZF):X:(AF):X:(PF):X:(CF)

LAHF
Copies SF, ZF, AF, PF and CF (the
8080/8085 flags) into bits 7, 6, 4, 2 and
0, respectively, of register AH. The
content of bits 5, 3, and 1 are
undefined. LAHF is provided primarily
for converting 8080/8085 assembly
language programs to run on an 8086
or 8088.

Flags
Affected
AFCFDFIF OFPFSFTFZF AFCFDFIF OFPFSFTF ZF AFCFDFIF OFPFSFTF ZF AFCFDFIF OFPF SF TF ZF -

Instruction Operands:
none
NOTE:

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
"the flag is updated after the instruction is executed

C-25

int"et~

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Description

Name
LOS

Load Pointer Using DS:
LOS dest, src

Operation

Flags
Affected

(dest) +- (EA)
(OS) +- (EA + 2)

AF CFOFIF OFPF SF TF ZF -

(dest) +- EA

AF CFOFIF OFPF SF TF ZF -

(SP) +- (BP)
(BP) +- ((SP) + 1:(SP))
(SP) +- (SP) + 2

AF CFOFIF OFPF SF TF ZF -

Transfers a 32-bit pointer variable from
the source operand, which must be a
memory operand, to the destination
operand and register OS. The offset
word of the pOinter is transferred to the
destination operand, which may be
any 16-bit general register. The
segment word of the pointer is
transferred to register OS.
Instruction Operands:
LOS reg16, mem32
LEA

Load Effective Address:
LEA dest, src
Transfers the offset of the source
operand (rather than its value) to the
destination operand.
Instruction Operands:
LEA reg16, mem16

LEAVE

Leave:
LEAVE
Reverses the action of the most recent
ENTER instruction. Collapses the last
stack frame created. First, LEAVE
copies the current BP to the stack
pointer releasing the stack space
allocated to the current procedure.
Second, LEAVE pops the old value of
BP from the stack, to return to the
calling procedure's stack frame. A
return (RET) instruction will remove
arguments stacked by the calling
procedure for use by the called
procedure.
Instruction Operands:
none

NOTE:

C-26

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
'(the flag is updated after the instruction is executed

intet

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
LES

Description
Load Pointer Using ES:
LES dest, src

Operation

Flags
Affected

(dest) ~ (EA)
(ES) ~ (EA + 2)

AFCFDFIF OFPF SF TF ZF -

none

AFCFDFIF OFPF SFTF ZF -

Transfers a 32-bit pOinter variable from
the source operand to the destination
operand and register ES. The offset
word of the pOinter is transferred to the
destination operand. The segment
word of the pointer is transferred to
register ES.
Instruction Operands:
LES reg16, mem32
LOCK

Lock the Bus:
LOCK
Causes the 8088 (configured in
maximum mode) to assert its bus
LOCK signal while the following
instruction executes. The instruction
most useful in this context is an
exchange register with memory.
The LOCK prefix may be combined
with the segment override and/or REP
prefixes.
Instruction Operands:
none

NOTE:

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
'(the flag is updated after the instruction is executed

C-27

intet

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
LOD5

Description
Load String (Byte or Word):
LOD5 src-string
Transfers the byte or word string
element addressed by 51 to register AL
or AX and updates 51 to point to the
next element in the string. This
instruction is not ordinarily repeated
since the accumulator would be
overwritten by each repetition, and
only the last element would be
retained.
Instruction Operands:
LOD5 src-string
LOD5 (repeat) src-string

LOOP

Loop:
LOOP disp8
Decrements CX by 1 and transfers
control to the target location if CX is
not 0; otherwise the instruction
following LOOP is executed.

Operation
When Source Operand is a Byte:
(AL) ~ (src-string)
if
(DF) =0
then
(51) ~ (51) + DELTA
else
(51) ~ (51) - DELTA
When Source Operand is a Word:

(CX) ~ (CX) - 1
if
(CX) *-0
then
(IP) ~ (IP) + disp8 (sign-ext to 16 bits)

AF CFDFIF OFPF 5F TF ZF -

(CX) ~ (CX) - 1
if
(ZF) = 1 and (CX) *- 0
then
(IP)~(IP) + disp8 (sign-ext to 16 bits)

AF CFDFIF OFPF 5F TF ZF -

LOOP short-label
Loop While Equal:
Loop While Zero:
LOOPE disp8
LOOPZ disp8
Decrements CX by 1 and transfers
control is to the target location if CX is
not 0 and if ZF is set; otherwise the
next sequential instruction is executed.

AF CFDFIF OFPF 5F TF ZF -

(AX) ~ (src-string)
if
(DF) =0
then
(51) ~ (51) + DELTA
else
(51) ~ (51) - DELTA

Instruction Operands:
LOOPE
LOOPZ

Flags
Affected

Instruction Operands:
LOOPE short-label
LOOPZ short-label
NOTE:

C-28

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
"the flag is updated after the instruction is executed

intet~

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name

Description

LOOPNE
LOOPNZ

Loop While Not Equal:
Loop While Not Zero:
LOOPNE disp8
LOOPNZ disp8
Decrements CX by 1 and transfers
control to the target location if CX is
not 0 and if ZF is clear; otherwise the
next sequential instruction is executed.

Operation

Flags
Affected

(CX) to- (CX) - 1
if
(ZF) 0 and (CX) *" 0
then
(I P) to- (I P) + disp8 (sign-ext to 16 bits)

AFCFDFIF OFPF SFTF ZF -

(dest)to-(src)

AF CFDFIF OFPFSF TF ZF -

Instruction Operands:
LOOPNE short-label
LOOPNZ short-label
MOV

Move (Byte or Word):
MOV dest, src
Transfers a byte or a word from the
source operand to the destination
operand.
Instruction Operands:
MOV mem, accum
MOV accum, mem
MOV reg, reg
MOVreg, mem
MOVmem, reg
MOV reg, immed
MOV mem, immed
MOV seg-reg, reg16
MOV seg-reg, mem16
MOV reg16, seg-reg
MOV mem16, seg-reg

NOTE:

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
"the flag is updated after the instruction is executed

C-29

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
MOV5

Description
Move String:

Operation
(dest-string)

(src-string)

MOV5 dest·strlng, src-string
Transfers a byte or a word from the
source string (addressed by SI) to the
destination string (addressed by 01)
and updates 51 and 01 to point to the
next string element. When used In
conjunction with REP, MOVS
performs a memory-to-memory block
transfer.

Flags
Affected
AFCFOFIF OFPF5FTF ZF -

Instruction Operands:
MOVS dest-string, src-string
MOVS (repeat) dest-string, src-string
MUL

Multiply:
MULsrc
Performs an unsigned multiplication of
the source operand and the accumulator. If the source is a byte, then it is
multiplied by register AL, and the
double-length result is retumed In AH
and AL. If the source operand Is a
word, then It is multiplied by register
AX, and the double-length result is
returned In registers OX and AX. The
operands are treated as unsigned
binary numbers (see AAM). If the
upper half of the result (AH for byte
source, OX for word source) is nonzero, CF and OF are set; otherwise
they are cleared.
Instruction Operands:

When Source Operand Is a Byte:
(AX) ~ (AL) x (src)
If
(AH) 0
then
(CF) ~O
else
(CF) ~ 1
(OF) ~ (CF)

AF?
CF ,(
OFIF OF ,(
PF?
SF?
TF ZF?

When Source Operand Is a Word:
(OX:AX) ~ (AX) x (src)
if
(OX) 0
then
(CF) ~O
else
(CF) ~ 1
(OF) ~(CF)

MUL reg
MULmem
NOTE:

C-30

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction Is executed
? the contents of the flag Is undefined after the Instruction Is executed
'(the flag is updated after the instruction is executed

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
NEG

Description
Negate:
NEG dest

Operation
When Source Operand is a Byte:
(dest)
(dest)

FFH - (dest)
(dest) + 1 (affecting flags)

~
Subtracts the destination operand,
which may be a byte or a word, from 0 When Source Operand is a Word:
and returns the result to the desti(dest) ~ FFFFH - (dest)
nation. This forms the two's
(dest) ~ (dest) + 1 (affecting flags)
complement of the number, effectively
reversing the sign of an integer. If the
operand is zero, its sign is not
changed. Attempting to negate a byte
containing -128 or a word containing32,768 causes no change to the
operand and sets OF.

Flags
Affected
AF .;'
CF .;'
DFIF OF.;'
PF .;'
SF .;'
TF ZF .;'

Instruction Operands:
NEG reg
NEG mem
NOP

No Operation:

AFCFDFIF OFPFSF TF ZF -

None

NOP
Causes the CPU to do nothing.
Instruction Operands:
none

NOT

Logical Not:
NOT dest
Inverts the bits (forms the one's
complement) of the byte or word
operand.

When Source Operand is a Byte:
(dest)

FFH - (dest)

When Source Operand is a Word:
(dest)

FFFFH - (dest)

Instruction Operands:
NOT reg
NOTmem
NOTE:

AFCFDFIF OFPF SFTF ZF -

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
.;'the flag is updated after the instruction is executed

C-31

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Description

Name
OR

Logical OR:
OR dest,src
Performs the logical "inclusive or" of
the two operands (bytes or words) and
retums the result to the destination
operand. A bit in the result is set if
either or both corresponding bits in the
original operands are set; otherwise
the result bit is cleared.

Operation
(dest) +- (dest) or (src)
(CF) +- 0
(OF) +- 0

Flags
Affected
AF?
CF ,(
OFIF OF'(
PF ,(
SF ,(

TFZF ,(

Instruction Operands:
OR reg, reg
OR reg, mem
ORmem, reg
OR accum, Immed
OR reg, Immed
OR mem, immed
OUT

Output:

(dest) +- (src)

OUT port, accumulator
Transfers a byte or a word from the AL
register or the AX register, respectively, to an output port. The port
number may be specified either with
....... ; ............ 80.... 100+.0. h,.t.a. I'nnC!tant alln,.,inn

tall ... lIlu;;n,.........."" ..,., .."" ...."""1 .... _11.' _ .. _ ..... ~

access to ports numbered 0 through
255, or with a number previously
placed In register OX, allowing variable
access (by changing the value in OX)
to ports numbered from 0 through
65,535.
Instruction Operands:

AFCFOFIF OFPFSFTF -

ZF -

OUT immed8, AL
OUT OX, AX
NOTE: The three symbols used in the Flags Affected column are defined as follOWS:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
,(the flag is updated after the instruction is executed

C-32

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
OUTS

Description
Out String:

Operation

Flags
Affected

(dst) ~ (src)

AF CFOFIF OFPF SF TF ZF -

(dest) ~ «SP) + 1 :(SP))
(SP) ~ (SP) + 2

AFCFOFIF OFPFSFTF ZF -

OUTS port, src_string
Performs block output from memory to
an 1/0 port. The port address is placed
in the OX register. The memory
address is placed in the SI register.
This instruction uses the OS segment
register, but this may be changed with
a segment override instruction. After
the data transfer takes place, the
pointer register (SI) increments or
decrements, depending on the value
of the direction flag (OF). The pOinter
register changes by 1 for byte
transfers or 2 for word transfers.
Instruction Operands:
OUTS port, src_string
OUTS (repeat) port, src_string
POP

Pop:
POP dest
Transfers the word at the current top of
stack (pointed to by SP) to the
destination operand and then
increments SP by two to point to the
new top of stack.
Instruction Operands:
POP reg
POP seg-reg (CS illegal)
POP mem

NOTE:

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
"the flag is updated after the instruction is executed

C-33

intet~

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
POPA

Description
Pop All:
POPA
Pops all data, pointer, and index
registers off of the stack. The SP value
popped is discarded.
Instruction Operands:
none

POPF

Pop Flags:
POPF

Operation

Flags
Affected

(01) f- «SP) + 1:(SP»
(SP) f- (SP) + 2
(SI) f- «SP) + 1:(SP»
(SP) f- (SP) + 2
(BP) f- «SP) + 1:(SP»
(SP) f- (SP) + 2
(BX) f- «SP) + 1:(SP»
(SP) f- (SP) + 2
(OX) f- «SP) + 1:(SP»
(SP) f- (SP) + 2
(CX) f- «SP) + 1:(SP»
(SP) f- (SP) + 2
(AX) f- «SP) + 1:(SP»
(SP) f- (SP) + 2

AFCFOFIF OFPF SF TF ZF -

Flags f- «SP) + 1:(SP»
(SP) f- (SP) + 2

AF
CF
OF
IF
OF
PF
SF
TF
ZF

(SP) f- (SP) - 2
«SP) + 1:(SP» f- (src)

AFCFDFIF OFPF SF TF ZF -

Transfers specific bits from the word at
the current top of stack (pointed to by
register SP) into the 8086/8088 flags,
replacing whatever values the flags
previously contained. SP is then
incremented by two to point to the new
top of stack.

0/
0/
0/
0/
0/
0/
0/
0/
0/

------------. -.---------

In ..t ...".lnn nn.....n'h.·

none
PUSH

Push:
PUSH src
Decrements SP by two and then
transfers a word from the source
operand to the top of stack now
pointed to by SP.
Instruction Operands:
PUSH reg
PUSH seg-reg (CS legal)
PUSH mem

NOTE:

C-34

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction Is executed
o/the flag is updated after the instruction is executed

intet

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Description

Name
PUSHA

Push All:
PUSHA
Pushes all data, pOinter, and index
registers onto the stack. The order in
which the registers are saved is: AX,
CX, DX, BX, SP, BP, SI, and DI. The
SP value pushed is the SP value
before the first register (AX) is pushed.
Instruction Operands:
none

PUSHF

Push Flags:
PUSHF

Operation
temp t- (SP)
(SP) t- (SP) - 2
((SP) + 1:(SP)) t(SP) t- (SP) - 2
((SP) + 1:(SP)) t(SP) t- (SP) - 2
((SP) + 1:(SP)) t(SP) t- (SP) - 2
((SP) + 1:(SP)) t(SP) t- (SP) - 2
((SP) + 1:(SP)) t(SP) t- (SP) - 2
((SP) + 1:(SP)) t(SP) t- (SP) - 2
((SP) + 1: (SP)) t(SP) t- (SP) - 2
((SP) + 1:(SP)) t-

(AX)
(CX)
(DX)
(BX)

(BP)
(SI)
(DI)

(SP) t- (SP) - 2
((SP) + 1:(SP)) t- Flags

Instruction Operands:
none

AFCFDFIF OFPFSFTF ZF -

(temp)

Decrements SP by two and then
transfers all flags to the word at the top
of stack pOinted to by SP.

NOTE:

Flags
Affected

AFCFDFIF OFPFSFTF ZF -

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
-"the flag is updated after the instruction is executed

C-35

int:et

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
RCL

Description
Rotate Through Carry Left:
RCL

dest, count

Rotates the bits in the byte or word
destination operand to the left by the
number of bits specified in the count
operand. The carry flag (CF) is treated
as "part of" the destination operand;
that is, its value is rotated into the loworder bit of the destination, and itself is
replaced by the high-order bit of the
destination.
Instruction Operands:
RCL
RCL
RCL
RCL
RCR

reg, n
mem, n
reg, CL
mem, CL

Rotate Through Carry Right:
RCR

dest, count

Operates exactly like RCL except that
the bits are rotated right instead of left.
Instruction Operands:
RCR
RCR
RCR
RCR

reg, n
mem, n
reg, CL
mem, CL

Flags
Affected

Operation
(temp) ~ count
do while (temp) 0
(tmpcf) ~ (CF)
(CF) ~ high-order bit of (dest)
(dest) ~ (dest) x 2 + (tmpcf)
(temp) ~ (temp) - 1
if
count 1
then
if
high-order bit of (dest) (CF)
then
(OF) ~ 1
else

AF CF ,(
DFIF OF ,(
PF SF TF ZF -

(OF)~O

else
(OF) undefined
(temp) ~ count
do while (temp) 0
(tmpcf) ~ (CF)
(CF) ~ low-order bit of (dest)
(dest) ~ (dest) 12
high-order bit of (dest) ~ (tmpcf)
(temp) ~ (temp) - 1

count 1
then
if
high-order bit of (dest)
next-to-high-order bit of (dest)
then

AFCF ,(
DFIF OF ,(
PF SF -

......
,.- ZF -

(OF)~1

else
(OF)~O

else
(OF) undefined
NOTE:

C-36

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
'(the flag is updated after the instruction is executed

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Description

Name
REP
REPE
REPZ
REPNE
REPNZ

Repeat:
Repeat While
Repeat While
Repeat While
Repeat While

Equal:
Zero:
Not Equal:
Not Zero:

Controls subsequent string instruction
repetition. The different mnemonics
are provided to improve program
clarity.
REP is used in conjunction with the
MOVS (Move String) and STOS (Store
String) instructions and is interpreted
as "repeat while not end-of-string' (CX
not 0).

Operation
do while (CX) * 0
service pending interrupts (if any)
execute primitive string
Operation in succeeding byte
(CX) +- (CX) - 1
if
primitive operation Is CMPB,
CMPW, SCAB, or SCAW and
(ZF) *0
then
exit from while loop

Flags

Affected
AFCFDFIF OFPFSFTF ZF -

REPE and REPZ operate identically
and are physically the same prefix byte
as REP. These instructions are used
with the CMPS (Compare String) and
SCAS (Scan String) instructions and
require ZF (posted by these instructions) to be set before initiating the
next repetition.
REPNE and REPNZ are mnemonics
for the same prefix byte. These
instructions function the same as
REPE and REPZ except that the zero
flag must be cleared or the repetition is
terminated. ZF does not need to be
initialized before executing the
repeated string instruction.
Instruction Operands:
none
NOTE:

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
'(the flag is updated after the instruction is executed

C-37

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Description

Name
RET

Return:
RET optional-pop-value
Transfers control from a procedure
back to the instruction following the
CALL that activated the procedure.
The assembler generates an intrasegment RET if the programmer has
defined the procedure near, or an
intersegment RET if the procedure has
been defined as far. RET pops the
word at the top of the stack (pointed to
by register SP) into the instruction
pOinter and increments SP by two. If
RET is intersegment, the word at the
new top of stack is popped into the CS
register, and SP is again incremented
by two. If an optional pop value has
been specified, RET adds that value to
SP.

Flags
Affected

Operation

(IP) f- «SP) 1:(SP»
(SP) f- (SP) + 2
if
inter-segment
then
(CS) f- «SP) + 1 :(SP»
(SP) f- (SP) + 2
if
add immed8 to SP
then
(SP) f- (SP) + data

AFCFDFIF OFPF SF TF ZF -

(temp) f- count
do while (temp) 0
(CF) f- nign-oraer bit of (dest)
(dest) f- (dest) x 2 + (CF)
(temp) f- (temp) - 1
if
count 1
then
if
high-order bit of (dest) (CF)
then
(OF) f-1
else
(OF) f- 0
else
(OF) undefined

AF CF ,(

Instruction Operands:
RETimmed8
ROL

Rotate Left:
ROL dest. count
Rotates the destination byte or word
left by the number of bits specified in
the count operand.
Instruction Operands:
ROL reg, n
ROLmem, n
ROL reg, CL
ROLmem CL

NOTE:

C-38

DFIF OF ,(
PF SF TF ZF -

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
'(the flag is updated after the instruction is executed

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
ROR

Description
Rotate Right:
ROR

dest, count

Operates similar to ROL except that
the bits in the destination byte or word
are rotated right instead of left.
Instruction Operands:
ROR reg, n
ROR mem, n
ROR reg, CL
RORmem, CL

SAHF

Store Register AH Into Flags:

Operation
(temp) (- count
do while (temp) ;t 0
(CF) (-low-order bit of (dest)
(dest) (- (dest) /2
high-order bit of (dest) (- (CF)
(temp) (- (temp) - 1
if
count 1
then
if
high-order bit of (dest) ;t
next-to-high-order bit of (dest)
then
(OF) (- 1
else
(OF) (- 0
else
(OF) undefined

AF CF v'
DFIF OFv'
PF SF TF ZF -

(SF):(ZF):X:(AF):X:(PF):X:(CF) (- (AH)

AF v'
CF v'
DFIF OFPF v'
SF v'
TF ZF v'

SAHF
Transfers bits 7, 6, 4, 2, and 0 from
register AH into SF, ZF, AF, PF, and CF,
respectively, replacing whatever
values these flags previously had.
Instruction Operands:
none
NOTE:

Flags
Affected

C-39

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
SHL
SAL

Description
Shift Logical Left:
Shift Arithmetic Left:
SHL dest,
SAL dest,

count
count

Shifts the destination byte or word left
by the number of bits specified in the
count operand. Zeros are shifted in on
the right. If the sign bit retains its
original value, then OF is cleared.
Instruction Operands:
SHL
SHL
SHL
SHL
SAR

reg, n
mem, n
reg, CL
mem, CL

SAL
SAL
SAL
SAL

reg, n
mem, n
reg, CL
mem, CL

Shift Arithmetic Right:
SAR

dest, count

Shifts the bits in the destination
operand (byte or wprd) to the right by
the number of bits specified in the
count operand. Bits equal to the
original high-order (sign) bit are shifted
in on the left, preserving the sign of the
original value. Note that SAR does not
produce the same result as the
dividend of an "equivalent" IDIV
instruction if the destination operand is
negative and 1 bits are shifted out. For
example, shifting -5 right by one bit
yields -3, while integer division -5 by 2
yields -2. The difference in the instructions is that IDIV truncates all numbers
toward zero, while SAR truncates
positive numbers toward zero and
negative numbers toward negative
infinity.

Operation
(temp) ~ count
do while (temp) '" 0
(CF) ~ high-order bit of (dest)
(dest) ~ (dest) x 2
(temp) ~ (temp) - 1
if
count = 1
then
if
high-order bit of (dest) '" (CE)
then

Flags
Affected
AF?
CF ,(
DFIF OF ,(

PF ,(
SF ,(
TF ZF ,(

(OF)~1

else
(OF)~O

else
(OF) undefined
(temp) ~ count
do while (temp) '" 0
(CF) ~ low-order bit of (dest)
(dest) ~ (dest) 12
(temp) ~ (temp) - 1
if
count = 1
then

" high-order bit of (dest) '"

AF?
CF ,(
DFIF OF ,(

PF ,(
SF ,(
TF "71::'

£.1

./
•

next-to-high-order bit of (dest)
then
(OF)~1

else
(OF)~O

Instruction Operands:
SAR
SAR
SAR
SAR
NOTE:

C-40

reg, n
mem, n
reg, CL
mem, CL

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
'(the flag is updated after the instruction is executed

· INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
SBB

Description
Subtract With Borrow:
SBS dest, src
Subtracts the source from the destination, subtracts one if CF is set, and
returns the result to the destination
operand. Both operands may be bytes
or words. Both operands may be
signed or unsigned binary numbers
(see AAS and DAS)

Operation
if
(CF) = 1
then
(dest) =(dest) - (src) - 1
else
(dest) ~ (dest) - (src)

Flags
Affected
AF ,/
CF ,/
DFIF OF ,/
PF ,/
SF ,/
TF ZF ,/

Instruction Operands:
SSB reg, reg
SBB reg, mem
SBB mem, reg
SBB accum, immed
SSB reg, immed
SBS mem, immed
NOTE:

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
'/the flag is updated after the instruction is executed

C-41

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
SCAS

Description

Operation

Scan String:

When Source Operand Is a Byte:

SCAS dest-string
Subtracts the destination string
element (byte or word) addressed by
01 from the content of AL (byte string)
or AX (word string) and updates the
flags, but does not alter the destination
string or the accumulator. SCAS also
updates 01 to point to the next string
element and AF, CF, OF, PF, SF and
ZF to reflect the relationship of the
scan value in AUAX to the string
element. If SCAS is prefixed with
REPE or REPZ, the operation is
interpreted as "scan while not end-ofstring (CX not 0) and string-element
scan-value (ZF 1)." This form may be
used to scan for departure from a
given value. If SCAS is prefixed with
REPNE or REPNZ, the operation is
interpreted as "scan while not end-ofstring (CX not 0) and string-element is
not equal to scan-value (ZF 0)."

(AL) - (byte-string)
if
(OF) 0
then
(01) +- (01) + OELTA
else
(01) +- (01) - OELTA

When Source Operand is a Word:

Flags
Affected
AF ./
CF ./
OFIF OF ./
PF ./
SF ./
TF ZF ./

(AX) - (word-string)
if
(OF) 0
then
(01) +- (01) + OELTA
else
(01) +- (01) - OELTA

Instruction Operands:
SCAS dest-string
SCAS (repeat) dest-string
NOTE:

C-42

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
./the flag is updated after the instruction is executed

intet

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
SHR

Description
Shift Logical Right:
SHR

dest, src

Shifts the bits in the destination
operand (byte or word) to the right by
the number of bits specified in the
count operand. Zeros are shifted in on
the left. If the sign bit retains its original
value, then OF is cleared.
Instruction Operands:
SHR
SHR
SHR
SHR

STC

reg, n
mem, n
reg, CL
mem, CL

Set Carry Flag:

Operation
(temp) +- count
do while (temp) *- 0
(CF) +-Iow·order bit of (dest)
(dest) +- (dest) 12
(temp) +- (temp) - 1
if
count 1
then
if
high-order bit of (dest) *next-to-high-order bit of (dest)
then
(OF) +-1
else
(OF) +- 0
else
(OF) undefined

AF?
CF V"
OFIF OF V"
PF V"
SF V"
TF ZF V"

(CF) +- 1

AFCF V"
OFIF OFPFSFTF ZF -

(OF) +- 1

AF CFOF V"
IF OFPFSFTF ZF -

STC
Sets CF to 1.
Instruction Operands:
none

STO

Set Direction Flag:
STD
Sets OF to 1 causing the string instructions to auto-decrement the SI and/or
01 index registers.
Instruction Operands:
none

NOTE:

Flags
Affected

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
V"the flag is updated after the instruction is executed

C-43

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Description

Name
STI

Set Interrupt-enable Flag:

Operation
(IF)

Flags
Affected
AFCFDFIF ~
OFPFSFTF ZF -

STI
Sets IF to 1, enabling processor
recognition of maskable interrupt
requests appearing on the INTR line.
Note however, that a pending interrupt
will not actually be recognized until the
instruction following STI has executed.
Instruction Operands:
none
STOS

Store (Byte or Word) String:

(DEST)

Transfers a byte or word from register
AL or AX to the string element
addressed by DI and updates DI to
point to the next location in the string.
As a repeated operation.

Instruction Operands:
STOS dest-string
STOS (repeat) dest-string

NOTE:

C-44

When Source Operand Is a Byte:

STOS dest·string

(AL)

(DF) = 0
then
(DI) ~ (DI) + DELTA
else
(DI) ~ (DI) - DELTA
When Source Operand Is a Word:

AFCFDFIF OFPF SF TF ZF -

(DEST) ~ (AX)
If
(DF) =0
then
(DI) ~ (DI) + DELTA
else
(DI) ~ (DI) - DELTA

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
~the flag is updated after the instruction Is executed

intet

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
SUB

Description
Subtract:

Operation
(dest) (- (dest) - (src)

SUB dest, src
The source operand is subtracted from
the destination operand, and the result
replaces the destination operand. The
operands may be bytes or words. Both
operands may be signed or unsigned
binary numbers (see AAS and DAS).

TEST

AF"
CF"
DFIF OF"
PF"
SF"
TF ZF "

Instruction Operands:
SUB
SUB
SUB
SUB
SUB
SUB

Flags
Affected

reg, reg
reg, mem
mem, reg
accum, immed
reg, immed
mem, immed

Test:
TEST dest, src
Performs the logical "and" of the two
operands (bytes or words), updates
the flags, but does not return the
result, i.e., neither operand is
changed. If a TEST instruction is
followed by a JNZ Oump if not zero)
instruction, the jump will be taken if
there are any corresponding one bits
in both operands.

(dest) and (src)
(CF) (- 0
(OF) (- 0

AF?
CF"
DFIF OF"
PF"
SF"
TF ZF "

Instruction Operands:
TEST reg, reg
TEST reg, mem
TEST accum, immed
TEST reg, immed
TEST mem, immed
NOTE:

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
"the flag is updated after the instruction is executed

C-45

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
WAiT

Description
Wait:

Operation
None

AFCFDFIF OFPF SF TF ZF -

(temp) f- (dest)
(dest) f- (src)
(src) f- (temp)

AF CFDFIF OFPF SF TF ZF -

WAIT
Causes the CPU to enter the wait state
while its test line is not active.
Instruction Operands:
none

XCHG

Exchange:
XCHG dest, src
Switches the contents of the source
and destination operands (bytes or
words). When used in conjunction with
the LOCK prefix, XCHG can test and
set a semaphore that controls access
to a resource shared by multiple
processors.

Flags
Affected

Instruction Operands:
XCHG accum, reg
XCHG mem, reg
XCHG reg, reg
NOTE:

C-46

The three symbols used ill the F!ags Affected co!umn are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
v"the flag is updated after the instruction is executed

infel~

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)
Name
XLAT

Description
Translate:

Operation

Flags
Affected

AL t- ((BX) + (AL»

AFCFDFIF OFPFSFTF ZF -

(dest) t- (dest) xor (src)
(CF) t- 0
(OF) t- 0

AF?
CF .I
DFIF OF .I
PF .I
SF .I
TF ZF .I

XLAT translate-table
Replaces a byte in the AL register with
a byte from a 2S6-byte, user-coded
translation table. Register BX is
assumed to pOint to the beginning of
the table. The byte in AL is used as an
index into the table and is replaced by
the byte at the offset in the table corresponding to AL's binary value. The first
byte in the table has an offset of O. For
example, if AL contains SH, and the
sixth element of the translation table
contains 33H, then AL will contain 33H
following the instruction. XLAT is
useful for translating characters from
one code to another, the classic
example being ASCII to EBCDIC or
the reverse.
Instruction Operands:
XLAT src-table
XOR

Exclusive Or:
XOR dest, src
Performs the logical "exclusive or' of
the two operands and returns the
result to the destination operand. A bit
in the result is set if the corresponding
bits of the original operands contain
opposite values (one is set, the other
is cleared); otherwise the result bit is
cleared.
Instruction Operands:
XOR
XOR
XOR
XOR
XOR
XOR

NOTE:

reg, reg
reg, mem
mem, reg
accum, immed
reg, immed
mem, immed

The three symbols used in the Flags Affected column are defined as follows:
- the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
.Ithe flag is updated after the instruction is executed

C-47

intel·

Instruction Set
Opcodes and Clock
Cycles

APPENDIX D
INSTRUCTION SET OPCODES
AND CLOCK CYCLES
This appendix provides reference information for the 8OC186 Modular Core family instruction
set. Table D-I defines the variables used in Table D-2, which lists the instructions with their formats and execution times. Table D-3 is a guide for decoding machine instructions. Table D-4 is a
guide for encoding instruction mnemonics, and Table D-S defines Table D-4 abbreviations.
Table 0-1. Operand Variables
Variable
mod

Description
mod and rim determine the Effective Address (EA).

rim

rim and mod determine the Effective Address (EA).

reg

reg represents a register.

MMM

MMM and PPP are opcodes to the math coprocessor.

PPP

PPP and MMM are opcodes to the math coprocessor.

TTT defines which shift or rotate instruction is executed.

rim

EA Calculation

mod

Effect on EA Calculation

000

(BX) + (SI) + OISP

rim ,. 110, OISP =0; disp-Iow and disp-high are absent

001

(BX) + (01) + OISP

rim =110, EA =disp-high:disp-Iow

010

(BP) + (SI) + OISP

OISP

011

(BP) + (01) + OISP

OISP

100

(SI) +OISP

rim

1 01

(OI)+OISP

OISP follows the second byte of the instruction (before any required data).

110

(BP) + OISP, if mod ,. 00

(BX)+OISP

reg

is treated as a reg field

Physical addresses of operands addressed by the BP register are computed
using the SS segment register. Physical addresses of destination operands of
string primitives (addressed by the 01 register) are computed using the ES segment register, which cannot be overridden.

disp-high:disp-Iow, if mod =00
111

=disp-Iow, sign-extended to 16 bits; disp-high is absent
=disp-high:disp-Iow

16-bit(w=1)

a-bit (w=O)

000

TTT

Instruction

000

ROL

001

ROR

010

RCL

011

RCR

100

SHUSAL

101

SHR

110

111

SAR

D-1

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table 0-2. Instruction Set Summary
Function

Format

Clocks

Notes

DATA TRANSFER INSTRUCTIONS
MOV=Move
register to register/memory

1000100w

mod reg rim

1000101w

mod reg rim

immediate to register/memory

1100011 w

mod 000 rim

data

immediate to register

1011 w reg

data

memory to accumulator

1010000w

addr·low

accumulator to memory

1010001w

addr·low

addr·high

10001110

modO reg rim

219

segment register to register/memory

10001100

modO reg rim

2111

2112

219
data ifw=l

12113

(1)

data ffw=l

314

(1)

addr·high

9
8

PUSH = Push

XCHG = Exchange

4/17

DATA TRANSFER INSTRUCTIONS (Continued)

...------,

XLAT = Translate byte to AL

11010111

IN = Input from
fixed port

variable port

OUT = Output from
fixed port

\1110010W

\ port

NOTES:
1. Clock cycles are given for 8-bitl16-bit operations.
2.
Clock cycles are given for jump not taken/jump taken.
3. Clock cycles are given for interrupt taken/interrupt not taken.
4.
If TEST =0
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, "80C186
Instruction Set Additions and ExtenSions," for details.

0-2

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table 0-2. Instruction Set Summary (Continued)
Function

Format

variable port

Clocks

Notes

LEA = Load EA to register

LOS = Load pointer to DS

SAHF = Store AH into flags

PUSHF = Push flags

POPF = Pop flags

ARITHMETIC INSTRUCTIONS
AOO = Add
reg/memory with register to either

OOOOOOdw

mod reg rim

immediate to register/memory

100000sw

mod 000 rim

data

4116

immediate to accumulator

0000010w

data

data ifw=1

314

reg/memory with register to either

000100dw

mod reg rim

immediate to register/memory

100000sw

mod 010 rim

data

4116

immediate to accumulator

0001010w

data

data ifw=1

3/4

1111111w

mod 000 rim

3110

(1)

AOC = Add with carry
3110

(1)

INC = Increment
3115

01000 reg

AAA = ASCII adjust for addition

00110111

OAA = Decimal adjust for addition

00100111

NOTES:
1 . Clock cycles are given for 8-bitl16-bit operations.
2. Clock cycles are given for jump not taken/jump taken.
3. Clock cycles are given for interrupt taken/interrupt not taken.
If TEST = 0
4.
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, "80C 186
Instruction Set Additions and Extensions," for details.

0-3

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table 0-2. Instruction Set Summary (Continued)
Function

Format

Clocks

Notes

SUB = Subtract
reglmemory with register to either

001010dw

mod reg rim

immediate from register/memory

100000sw

mod 101 rIm

data

immediate from accumulator

0001110w

data

data Hw=1

reg/memory with register to either

000110dw

mod reg rIm

immediate from registerlmemory

100000sw

mod 011 rIm

data

immediate from accumulator

0OO1110w

data

data ifw=1

3110

I
I

data if sw=OI

4116
314

(1)

SBB = Subtract with borrow

3110

data if sw=OI

4116
314

(1)

ARITHMETIC INSTRUCTIONS (Continued)
DEC = Decrement
registerlmemory

lllllllw

01001 reg

NEG = Change sign

mod 001 rim

3115
3

111101 1 w

mod reg rIm

0011101 w

mod reg rIm

3110

0011100w

mod reg rIm

immediate with register/memory

100000sw

mod 111 rim

data

Irnrnediate with accumu:ator

0011110w

data

data If ....;;;;1

CMP = Compare

AAS = ASCII adjust for subtraction

00111111

DAS = Decimal adjust for subtraction

00101111

MUL = multiply (unsigned)

1111011 w

3110

I
!

data if sw=OI

3/10

314
7
4

mod 100 rim

26-28

35-37

memory-byte

32-34

memory-word
IMUL = Integer multiply (signed)
register-byte

11111011W

(1)

mod 101 rIm

41-43

I
25-28

34-37

memory-byte

31-34

NOTES:
1. Clock cycles are given for 8-bit/16-bit operations.
2.
Clock cycles are given for jump not taken/jump taken.
3. Clock cycles are given for interrupt taken/interrupt not taken.
4. If TEST = 0
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, "80C186
Instruction Set Additions and Extensions," for details.

D-4

INSTRUCTION SET OPCOOES AND CLOCK CYCLES

Table 0-2. Instruction Set Summary (Continued)
Function

Format

memory-word

Clocks

Notes

40-43

ARITHMETIC INSTRUCTIONS (Continuerd)'---_ _ _ _. -_ _ _ _---.
AAM = ASCII adjust for multiply

11010100

DIV = Divide (unsigned)

1111011 w

memory-byte

memory-word
IDIV = Integer divide (signed)

11 1 1101 1 w

mod 111 rim

memory-byte

memory-word

11010101

CBW = Convert byte to word

10011000

CWO = Convert word to double-word

10011001

BIT MANIPULATION INSTRUCTIONS
NOT= Invert register/memory

11111011w

00001010

AAD = ASCII adjust for divide

mod 010 rim

AND = And
reg/memory and register to either

001000dw

mod reg rim

immediate to register/memory

1000000w

mod 100 rim

data

immediate to accumulator

0010010w

data

data ifw=1

3110
4/16
314

(1)

BIT MANIPULATION INSTRUCTIONS (Continued)
OR=Or
reg/memory and register to either
immediate to register/memory

000010dw

3110

1000000w

4/10

NOTES:
1 . Clock cycles are given for 8-bitl16-bit operations.
2. Clock cycles are given for jump not taken/jump taken.
3. Clock cycles are given for interrupt taken/interrupt not taken.
4.
If TEST = 0
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, "80C186
Instruction Set Additions and Extensions," for details.

0-5

INSTRUCTION SET OPCOOES AND CLOCK CYCLES

Table 0-2. Instruction Set Summary (Continued)
Function
immediate to accumulator

Format
10000110W

data

data ifw=1

Clocks

Notes

314

(1)

XOR = Exclusive or
reg/memory and register to either

001100dw

mod reg rIm

immediate to register/memory

1000000w

mod 110 rIm

data

immediate to accumulator

0011010w

data

data ifw=1

mod reg rIm

3110

4110
314

(1)

TEST= And function to flags, no result
register/memory and register

1000010w

immediate data and register/memory

1111011 w

mod 000 rIm

data

4110

immediate data and accumulator

1010100w

data

data ifw=1

314

3110

(1)

ShlftS/Romles
register/memory by 1

2115

LODS = Load byte/word to AIJAX

STOS = Store byte/word from AIJAX

Repeated by counl In CX:

SCAS = Scan byte/word

5+15n

LODS = Load byte/word to AIJAX

6+11n

STOS = Store byte/word from AIJAX

6+9n

NOTES:
1. Clock cycles are given for 8-biU16-bit operations.
2.
Clock cycles are given for jump not taken/jump taken.
3. Clock cycles are given for interrupt taken/interrupt not taken.
4. If TEST = 0
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, "80C186
Instruction Set Additions and Extensions," for details.

0-6

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table 0-2. Instruction Set Summary (Continued)
Function

Format

Clocks

Notes

PROGRAM TRANSFER INSTRUCTIONS
Conditional Transfers - jump il:
JElJZ= equaVzero

01110100

disp

4/13

(2)

JUJNGE = less/not greater or equal

01111100

disp

4/13

(2)

JLElJNG = less or equaVnot greater

011111 10

disp

4/13

(2)

JBJJNAE = below/not above or equal

01110010

disp

4/13

(2)

JC = carry

01110010

disp

4/13

(2)

JBElJNA = below or equal/not above

01110110

disp

4/13

(2)

JP/JPE = parity/parity even

01111010

disp

4/13

(2)

JO= overflow

01110000

disp

4/13

(2)

JS = sign

01111000

disp

4/13

(2)

JNElJNZ = not equal/not zero

01110101

disp

4/13

(2)

disp

4/13

(2)

PROGRAM TRANSFER INSTRUCTIONS (Continued)
JNUJGE = not less/greater or equal

01111101

JNLElJG = not less or equaVgreater

01111111

disp

4/13

(2)

JNBJJAE = not below/above or equal

01110011

disp

4/13

(2)

JNC = not carry

011 10011

disp

4/13

(2)

JNBElJA = not below or equaVabove

01 1 10111

disp

4/13

(2)

JNP/JPO = not parity/parity odd

01 1 11011

disp

4/13

(2)

JNO = not overflow

01110001

disp

4/13

(2)

JNS = not sign

01111001

disp

5/15

(2)

direct within segment

11101000

disp-Iow

reg/memory indirect within segment

11111111

mod 010 rim

indirect intersegment

11111111

mod 011 rim

direct intersegment

10011010

segment offset

Unconditional Transfers
CALL = Call procedure
disp-high

15
13/19

(mod?11)

38
23

selector
RET = Return from procedure
within segment

111000011

NOTES:
1. Clock cycles are given for 8-bit/16-bit operations.
2. Clock cycles are given for jump not taken/jump taken.
3. Clock cycles are given for jnterrupt taken/interrupt not taken.
If TEST = 0
4.
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, "80C186
Instruction Set Additions and ExtenSions," for details.

0-7

intet

INSTRUCTION SET OPCOOES AND CLOCK CYCLES

Table 0-2. Instruction Set Summary (Continued)
Function

Format

within segment adding immed to SP

11000010

intersegment

11001011

intersegment adding immed to SP

11001010

data-low

Clocks

Notes

18
22

data-low

disp-Iow

PROGRAM TRANSFER INSTRUCTIONS (Continued)
JMP = Unconditional jump
shortllong

11101011

direct within segment

11101001

disp-Iow

reg/memory indirect within segment

11111111

mod 100 rim

indirect intersegment

11111111

mod 101 rim

direct intersegment

11101010

segment offset

disp-high

14
26

(mod ?11)

11/17

selector
Iteration Control
LOOP = Loop CX times

11100010

disp

6/16

(2)

LOOPZILOOPE =Loop while zero/equal

11100001

disp

5/16

(2)

LOOPNZlLOOPNE =
Loop while not zero/not equal

11100000

disp

5/16

(2)

JCXZ = Jump if CX = zero

11100011

disp

6/16

(2)

Interrupts
INT = Interrupt
, Type specified

Type 3

PROCESSOR CONTROL INSTRUCTlONrS_ _ _ _ _-,
CLC = Clear carry

11111000

NOTES:
1. Clock cycles are given for 8-bitl16-bit operations.
2. Clock cycles are given for jump not taken/jump taken.
3. Clock cycles are given for interrupt taken/interrupt not taken_
4.
If TEST 0
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, "80C186
Instruction Set Additions and Extensions," for details.

D-8

intel~

INSTRUCTION SET OPCOOES ANO CLOCK CYCLES

Table 0-2. Instruction Set Summary (Continued)
Function

Clocks

Format

CMC = Complement carry

11110101

STC = Set carry

11111001

CLD = Clear direction

11111100

2
2

STD = Set direction

11111101

CU = Clear interrupt

11111010

sn = Set interrupt

11111011

HLT= Halt

11110100

WAIT = Wait

10011011

LOCK = Bus lock prefix

11110000

2
modPPP rIm

ESC = Math coprocessor escape

11011 MMM

NOP = No operation

10010000

00101110

00110110

Notes

(4)

SEGMENT OVERRIDE PREFIX

00111110

00100110

NOTES:
1. Clock cycles are given for 8-bitl16-bit operations.
2. Clock cycles are given for jump not taken/jump taken.
3. Clock cycles are given for interrupt taken/interrupt not taken.
4.
If TEST = a
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, "80C186
Instruction Set Additions and Extensions," for details.

Table 0-3. Machine Instruction Decoding Guide
Byte 1

ASM-86 Instruction Format

Bytes 3-6

Byte 2
Hex

Binary

00000000

mod reg rIm

(disp-Io),(disp-hi)

add

00000001

mod reg rIm

(dlsp-Io),(dlsp-hi)

add

regl61mem18,reg16

00000010

mod reg rIm

(disp-Io),(disp·hl)

add

reg8,reg8lmem8

00000011

mod reg rIm

(disp-Io),(disp-hi)

add

reg16,regl61mem16

00000100

data·8

add

AL,immed8

0000 0101

data·lo

add

AX,lmmed16

0000 0110

push

0000 0111

pop

0000 0100

reg8lmem8,reg8

mod reg rIm

data·hi

(disp·lo),(disp·hi)

reg8lmem8, reg8

0-9

intet

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table 0-3. Machine Instruction Decoding Guide (Continued)
Byte 1

Hex

Binary

Bytas3-6

Byte 2

ASM-86 Instruction Format

0000 1001

mod reg rim

(disp-Io),(dlsp-hi)

regl61mernl6,regl6

0000 1010

mod reg rim

(disp-Io),(disp-hl)

reg8,reg6lmern8

0000 1011

mod reg rim

(disp-Io),(dlsp-hi)

reg16,reg161rnem 16

0000 1100

data-8

AL,lmmed8

0000 1101

data-Io

0000 1110

00001111

00010000

mod reg rim

(disp-Io),(disp-hi)

ade

data-hi

AX,immed16

push

reg8lmem8,reg8

00010001

mod reg rim

(dlsp-Io),(disp-hi)

ade

regl61meml6,regl6

00010010

mod reg rim

(disp-Io),(dlsp-hi)

ade

reg8,reg8lmem8

00010011

mod reg rim

(disp-Io),(disp-hl)

00010100

data-8

00010101

data-Io

data-hi

ade

reg18,reg161rnem16

ade

AL,immed8

ade

AX,Immed16
SS

00010110

push

00010111

pop

00011000

mod reg rim

(disp-Io),(disp-hl)

sbb

reg8lmem8,regB

00011001

mod reg rim

(dlsp-Io),(disp-hi)

sbb

regl61meml6,regl6

00011010

mod reg rim

(disp-Io),(disp-hl)

sbb

regB,reg8lmem8

00011011

mod reg rim

(disp-Io),(disp-hi)

sbb

reg16,reg161rnem 16

00011100

data-B

sbb

AL,lmmed8

00011101

data-Io

sbb

AX,immed16

00011110

push

00011111

pop

00100000

mod reg rim

(disp-Io),(disp-hi)

and

reg8lmemB,regB

0010 0001

mod reg rim

(dlsp-Io),(disp-hl)

and

regl61meml6,regl6

00100010

mod reg rim

(disp-Io),(disp-hi)

and

regB,reg8lmemB

00100011

mod reg rim

(disp-Io),(disp-hi)

and

regl6,regl61meml6

0010 0100

data-B

and

AL,immedB

00100101

data-Io

and

AX,Immed16

00100110

ES:

(segment override prefix)

00100111

daa

0010 1000

mod reg rim

(disp-Io),(disp-hi)

sub

0010 1001

mod reg rim

(disp-Io),(dlsp-hl)

sub

regl61meml6,regl6

0010 1010

mod reg rim

(dlsp-Io),(disp-hl)

sub

regB,reg61memB

0010 1011

mod reg rim

(disp-Io),(disp-hi)

sub

reg16,reg161rnem16

0010 1100

data-8

sub

AL,lmmed8

0010 1101

data-Io

sub

AX,immed16

0-10

data-hi

reg8lmemB,regB

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table D-3. Machine Instruction Decoding Guide (Continued)
Byte 1
Bytes 3-6

Byte 2
Hex

ASM-86 Instruction Format

Binary

00101110

os:

00101111

das

00110000

mod reg rIm

(disp-Io),(disp-hi)

xor

00110001

mod reg rIm

(disp-Io),(disp-hi)

xor

00110010

mod reg rIm

(disp-Io),(disp-hi)

xor

00110011

mod reg rIm

(disp-Io),(disp-hi)

00110100

data-8

00110101

data-Io

data-hi

(segment override prefix)

reg8lmem8,reg8
reg161mem16,reg16
reg8,reg8lmem8

xor

reg16,reg161mem16

xor

AL,immed8

xor

AX,immed16
(segment override prefix)

00110110

SS:

00110111

aaa

00111000

mod reg rIm

(disp-Io),(disp-hi)

xor

reg8lmem8, reg8

00111001

mod reg rIm

(disp-Io),(disp-hi)

xor

reg161mem16,reg16
reg8,reg8lmem8

00111010

mod reg rIm

(disp-Io),(disp-hi)

xor

00111011

mod reg rIm

(disp-Io),(disp-hi)

xor

reg16,reg161mem16

00111100

data-8

xor

AL,immed8

00111101

data-Io

xor

AX,immed16

00111110

OS:

(segment override prefix)

00111111

aas

01000000

inc

01000001

inc

01000010

inc

01000011

inc

01000100

inc

01000101

inc

BP
SI

data-hi

01000110

inc

01000111

inc

01001000

dec

01001001

dec

01001010

dec

01001011

dec

0100 1100

dec

01001101

dec

01001110

dec

01001111

dec

01010000

push

01010001

push

01010010

push

0-11

int:et

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table D-3. Machine Instruction Decoding Guide (Continued)
Byte 1
Byte 2
Hex

ASM-86 Instruction Format

Bytes 3-6

Binary

0101 0011

push

0101 0100

push

0101 0101

push

0101 0110

push

01010111

push

0101 1000

01011001

01011010

pop

01011011

pop

0101 1100

pop

01011101

pop

0101 1110

pop

01011111

pop

01100000

pusha

01100001

01100010

01100011

01100100

01100101

01100110

01100111

pop

popa
mod reg rIm

bound

reg16,mem16

01101000

data-Io

data-hi

push

immed16

01101001

mod reg rIm

data-Io, data-hi

imul

immed16

0111 0000

IP-inc-8

short-label

0111 0001

IP-inc-B

jno

short-label

01110010

IP-inc-8

jb~naeljc

01110011

IP-inc-8

jnbljae~nc

0111 0100

IP-inc-8

je~z

short-label

01110101

IP-inc-8

jneljnz

short-label

0111 0110

IP-inc-8

jb~na

short-label

01110111

IP-inc-8

jnbe~a

short-label

01111000

IP-inc-8

short-label

01111001

IP-inc-8

jns

short-label

0111 1010

IP-inc-8

jp/jpe

short-label

0111 1011

IP-inc-8

jnp/jpo

short-label

0111 1100

IP-inc-8

jl/jnge

short-label

01111101

IP-inc-8

jnVjge

short-label

D-12

short-label
short-label

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table D-3. Machine Instruction Decoding Guide (Continued)
Byte 1
Byte 2
Hex

Bytes 3-6

0111 1110

IP-inc-8

jle/jng

0111 1111

IP-inc-8

jnle/jg

short-label

10000000

mod 000

rim

(disp-Io),(disp-hi), data-8

add

reg8imem8,immed8

mod 001

rim

(disp-Io),(disp-hi), data-8

reg8imem8,immed8

mod 010

rim

(disp-Io),(disp-hi), data-8

adc

reg8imem8,immed8

mod 011

rim

(disp-Io),(disp-hi), data-8

sbb

reg8imem8,immed8

mod 100 rim

(disp-Io),(disp-hi), data-8

and

reg8imem8,immed8

rim

(disp-Io),(disp-hi), data-8

sub

reg8imem8,immed8
reg8imem8,immed8

mod 101

10000001

10000010

10000011

short-label

mod 110 rim

(disp-Io),(disp-hi), data-8

xor

mod 111

rim

(disp-Io),(disp-hi), data-8

cmp

reg8imem8,immed8

mod 000

rim

(disp-Io),(disp-hi), data-Io,data-hi

add

reg16/mem16,immed16

mod 001

rim

(disp-Io),(dlsp"hi), data-Io,data-hi

reg161mem16,immed16

mod 010

rim

(disp-Io),(disp-hi), data-Io,data-hi

adc

reg16/mem16,immed16

mod 011

regl61mem16,immed16

rim

(disp-Io),(disp-hi), data-Io,data-hi

sbb

mod 100 rim

(disp-Io),{disp-hi), data-Io,data-hi

and

reg16/mem16,immed16

mod 101

rim

{disp-Io),(disp-hij, data-Io,data-hi

sub

reg16/mem16,immed16

mod 110

rim

(disp-Io),{disp-hi), data-Io,data-hi

xor

regl61mem16,immed16

mod 111

rim

(disp-Io),{disp-hi), data-Io,data-hi

cmp

regl61mem16,immed16

mod 000

rim

(disp-Io),{disp-hi), data-8

add

reg8imem8,immed8

mod 001

rim

mod 010

rim

(disp-Io),{disp-hi), data-8

mod 011

rim

(disp-Io),{disp-hi), data-8

adc

reg8imem8,immed8

sbb

reg8imem8,immed8

mod 100 rim
mod 101

rim

mod 110

rim

mod 111

rim

(disp-Io),{disp-hi), data-8

cmp

reg8imem8,immed8

mod 000

rim

(disp-Io),{disp-hi), data-SX

add

reg 16/mem 16,immed8

mod 001

rim

mod 010

rim

(disp-Io),{disp-hi), data-SX
(disp-Io),{disp-hi), data-SX

mod 011

rim

mod 100

rim

mod 101

rim

(disp-Io),{disp-hi), data-8

sub

reg8imem8,immed8

adc

reg16/mem16,immed8

sbb

reg 16/mem 16,immed8

(disp-Io),{disp-hi), data-SX

sub

reg16/mem16,immed8

mod 110 rim

ASM-86 Instruction Format

Binary

mod 111

rim

(disp-Io),(disp-hi), data-SX

cmp

reg16/mem16,immed8
reg8imem8,reg8

10000100

mod reg

rim

(disp-Io),{disp-hi)

test

10000101

mod reg

rim

(disp-Io),{disp-hi)

test

reg 16/mem 16, reg 16

10000110

mod reg

rim

(disp-Io),{disp-hi)

xchg

reg8,reg8imem8

0-13

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table D-3. Machine Instruction Decoding Guide (Continued)
Byte 1 .

Hex

Byte 2

ASM-86 Instruction Format

Bytes 3-6

Binary

10000111

mod reg rIm

(dlsp-Io),(disp-hi)

xchg

reg16,regl61mem 16

10000100

mod reg

rIm

(disp-Io),(disp-hi)

moY

reg8lmem8,reg8

1000 1001

mod reg

rIm

(disp-Io),(disp-hi)

moy

regl61mem16,reg16

1000 1010

mod reg rIm

(disp-Io),(dlsp-hi)

moy

reg8,reg8lmem8

10001011

mod reg rIm

(disp-Io),(disp-hi)

moy

reg16,regl61mem16

10001100

mod OSR rIm

(disp-Io),(disp-hi)

moy

regl61mem16,SEGREG

10001101

mod reg rIm

(disp-Io),(dlsp-hi)

lea

reg16,mem16

10001110

mod OSR rIm

(dlsp-Io),(disp-hi)

moy

SEGREG,regl61mem16

mod 1- rIm

mod 1- rIm
8F

1000 1111

pop

10010000

nop

mem16
(xchg AX.AX)

10010001

xchg

AX,CX

10010010

xchg

AX,OX

10010011

xchg

AX,BX

10010100

xchg

AX,SP

10010101

xchg

AX,BP

10010110

xchg

AX,SI

10010111

xchg

AX,OI

10011000

cbw

10011001

10011010

10011011

wait

10011100

push!

10011101

pop!

10011110

sah!

cwd
disp-Io

disp-hi,seg-Io,seg-hi

call

far-proc

10011111

10100000

addr-Io

addr-hi

moy

AL,mem8

10100001

addr-Io

addr-hl

moY

AX,mem16

10100010

addr-Io

addr-hi

moy

mem8,AL

10100011

addr-Io

addr-hi

mov

mem16,AL

10100100

moys

dest-strB,src-strB

10100101

moys

dest-str16,src-str16

10100110

crnps

dest-str8,src-strB

10100111

crnps

dest-str16,src-str16

10101000

data-8

test

AL,immed8

10101001

data-Io

test

AX,Immed16

0-14

lah!

data-hi

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table 0-3. Machine Instruction Decoding Guide (Continued)
Byte 1
Byte 2
Hex
AA

10101010

ASM-86 Instruction Format

AB
AC

slos

desl-slrS

10101011

slos

desl-slrlB

10101100

lods

sre-slrS

10101101

lods

sre-slrlB

10101110

seas

desl-slrS

10101111

seas

desl-slrlB

10110000

dala-8

mov

AL,immedS

10110001

dala-B

mov

CL,immedB

10110010

dala-B

mov

DL,immedB

10110011

dala-B

mov

8L,immedB

10110100

dala-B

mov

AH,immedB

10110101

dala-B

mov

CH,immedS

10110110

dala-B

mov

DH,immedS

10110111

dala-8

mov

8H,immedS

10111000

dala-Io

dala-hi

mov

AX,immedlB

10111001

dala-Io

dala-hi

mov

CX,immedlB

10111010

dala-Io

dala-hi

mov

DX,immedl6

10111011

data-Io

data-hi

mov

8X,immedl6

10111100

data-Io

data-hi

mov

SP,immedl6

10111101

data-Io

data-hi

mov

8P,immedl6

10111110

data-Io

data-hi

mov

SI,immedl6

10111111

data-Io

data-hi

mov

DI,immedlB

11000000

11000001

mod 000

rIm

dala-B

ral

regB/memS, immedB

mod 001

rIm

data-B

rar

regB/memS, immedS

mod 010

rIm

dala-B

rei

regB/memB, immedB

mod 011

rIm

data-B

rer

regB/memB, immedS

mod 100

rIm

data-B

shl/sal

regB/memB, immedB

mod 101

rIm

data-B

shr

regB/memB, immedB

mod 110

rIm

mod 111

rIm

data-B

sar

regB/memB, immedB

mod 000

rIm

data-B

rol

reglB/memI6, immedB

mod 001

rIm

data-B

ror

reglB/memI6, immedB

mod 010

rIm

dala-B

rei

reglB/memI6, immedB

mod 011

rIm

data-B

rer

reglB/memI6, immedB

mod 100

rIm

data-B

shl/sal

reglBlmeml6, immedB

mod 101

rIm

data-8

shr

reglB/memI6, immedB

mod 110 rIm

Bytes :Hi

Binary

D-15

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table D-3. Machine Instruction Decoding Guide (Continued)
Byte 1

ASM-86 Instruction Format

Bytes 3-6

Byte 2

Hex

Binary

11000010

mod 111 rIm

data-8

sar

regl61meml6, immed8

data-Io

data-hi

ret

immed16 (intrasegment)

(disp-Io),(disp-hi)

11000011

1100 0100

mod reg rIm

11000101

mod reg rIm

(disp-Io),(disp-hi)

Ids

reg16,mem16

11000110

mod 000 rIm

(disp-lo),(disp-hi),data-8

mov

mem8,immed8

mod 010 rIm
mod 011 rIm

mod 101 rIm
mod 110 rIm

11000110

mod 111 rIm

11000111

mod 000 rIm

(disp-Io),(disp-hi),data-Io,data-hi

mod 011 rIm

mod 101 rIm

mod 110 rIm

mod 100 rIm

mod 111 rIm
data-Io

mem16,immed16

mod 010 rIm

mov

mod 001 rIm

11001001

reg16,mem16

mod 100 rIm

11001000

(intrasegment)

les

mod 001 rIm

ret

data-hi, level •

enter

immed16, immed8

leave

11001010

ret

immed16 (intersegment)

1100 1011

ret

(intersegment)

11001100

int

11001101

int

immed8

11001110

11001111

11010000

data-Io

data-hi

data-8

into
iret
mod 000 rIm

(disp-Io),(disp-hi)

rol

reg8lmem8,1

mod 001 rIm

(disp-Io),(disp-hi)

ror

reg8lmem8,1

mod 010 rim

(disp-Io),(disp-hi)

rei

reg8lmem8,1

mod 011 rIm

(disp-Io),(disp-hi)

rer

reg8lmem8,1

mod 100 rIm

(disp-Io),(disp-hi)

saVshl

reg8lmem8,1

mod 101 rIm

(disp-Io),(disp-hi)

shr

reg8lmem8,1

mod 110 rIm
mod 111 rIm

0-16

(disp-Io),(disp-hi)

sar

reg8lmem8,1

intet

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table D-3. Machine Instruction Decoding Guide (Continued)
Byte 1
Byte 2
Hex

Bytes 3-6

11010001

mod 000

rim

(disp-Io),(disp-hi)

rol

reg161mem16,1

mod 001

rim

(disp-Io),(disp-hi)

ror

reg161mern16,1

mod 010

rim

(disp-Io),(disp-hi)

rei

reg161mem16,1

mod 011

rim

(disp-Io),(disp-hi)

rcr

reg161mem 16,1

mod 100 rim

(dlsp-Io),(disp-hi)

salish I

reg161mern 16,1

rim

(disp-Io),(dlsp-hi)

shr

reg161mem16,1

mod 101

mod 110 rim

rim

(disp-Io),(disp-hi)

sar

reg161mern16,1

mod 000 rim

(disp-Io),(disp-hi)

rol

reg6lmem8,CL

mod 001

rim

(disp-Io),(disp-hi)

ror

reg6lmem8,CL

mod 010

rim

(disp-Io),(disp-hi)

rei

reg6lmem8,CL

mod 011

rim

(disp~o),(disp-hi)

rcr

reg6lmemB,CL

mod 100 rim

(disp-Io),(disp-hi)

sal/shl

reg6lmemB,CL

rim

(disp-Io),(disp-hi)

shr

reg6lmem8,CL

mod 111
02

11010010

mod 101

mod 110 rim

11010011

mod 111

rim

(disp-Io),(disp-hi)

sar

reg6lmem8,CL

mod 000

rim

(disp-Io),(disp-hi)

rol

reg161mern16,CL

mod 001

rim

(disp-Io),(disp-hi)

ror

reg161mem16,CL

mod 010 rim

(disp-Io),(disp-hi)

rei

reg161mem16,CL

rim

(disp-Io),(disp-hi)

rcr

reg161mem16,CL

mod 100 rim

(disp-Io),(disp-hi)

saVshl

reg161mem16,CL

rim

(disp-Io),(disp-hi)

shr

reg161mem16,CL

mod 011

mod 101

mod 110 rim
mod 111

ASM-86 Instruction Format

Binary

rim

(disp-Io),(disp-hi)

sar

reg161mem16,CL

11010100

0000 1010

aam

11010101

00001010

aad

11010110

11010111

xlat

source-table

11011000

mod 000 rim

(disp-Io),(disp-hi)

esc

opcode,source

11011001

mod 001

rim

(disp-Io),(disp-hi)

esc

opcode,source

11011010

mod 010

rim

(disp-Io),(disp-hi)

esc

opoode,source

11011011

mod 011

rim

(disp-Io),(disp-hi)

esc

opcode,source

11011100

mod 100 rim

(disp-Io),(disp-hi)

esc

opoode,source

11011101

mod 101

rim

(disp-Io),(disp-hi)

esc

opcode,source

11011110

mod 110 rim

(disp-Io),(disp-hi)

esc

opoode,source

OJ;'

11011111

mod 111

rim

(disp-Io),(disp-hi)

esc

opcode,souree

11100000

IP-inc-B

loopnelloopnz

short-label

0-17

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table D·3. Machine Instruction Decoding Guide (Continued)
Byte 1

Hex

Binary

Bytes 3-6

Byte 2

ASM-86 Instruction Format

11100001

IP-inc-8

loopeJloopz

short-label

11100010

IP-lnc-8

loop

short-label

11100011

IP-inc-8

icxz

short-label

11100100

dala-8

AL,immed8

11100101

data-8

AX,Immed8

11100110

dala-8

out

AL,lmmed8

out

AX,immed8

11100111

data-8

11101000

IP-inc-Io

IP-Inc-hl

call

near-proc

11101001

IP-inc-Io

IP-inc-hi

jmp

near-label

11101010

IP-Io

IP-hl,CS-lo,CS-hi

imp

far-label

11101011

IP-inc-8

imp

short-label

11101100

AL,DX

11101101

AX,DX

11101110

out

AL,DX

11101111

out

AX,DX

11110000

lock

(prefix)

11110001

11110010

repne/repnz

11110011

replrepe/repz

11110100

11110101

11110110

erne
mod 000 rIm

(disp-lo),(dlsp-hi),data-8

11110111

mod 010 rIm

(dlsp-Io),(dlsp-hi)

not

reg8lmem8

mod 011 rIm

(disp-Io),(dlsp-hi)

neg

reg8lmem8

mod 100 rIm

(dlsp-Io),(dlsp-hl)

mul

reg8/mem8

mod 101 rIm

(disp-Io),(disp-hl)

Imul

regB/mem8

mod 110 rIm

(disp-Io),(disp-hl)

dly

reg8lmem8

mod 111 rim

(disp-Io),(disp-hl)

Idiy

regB/mem8

mod 000 rIm

(dlsp-lo),(dlsp-hi),dala-IO,dala-hi

test

regl81mem16,immed16

mod 001 rIm

0-18

reg8lmem8,immed8

mod 001 rim

test

mod 010 rim

(disp-Io),(disp-hl)

not

regl61mem16

mod 011 rIm

(dlsp-Io),(disp-hl)

neg

regl61mem16

mod 100 rIm

(disp-Io),(dlsp-hi)

mul

regl61mem16

mod 101 rIm

(disp-Io),(dlsp-hl)

Imul

regl61mem16

mod 110 rIm

(disp-Io),(dlsp-hl)

diy

regl61mem16

mod 111 rIm

(dlsp-Io),(dlsp-hi)

idiy

regl61mem16

intel~

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table D-3. Machine Instruction Decoding Guide (Continued)
Byte 1
Byte 2
Hex

11111000

11111001

sIC
cli

11111010

11111011

sti

11111100

cld

11111101

11111110

sId
mod 000 rIm

(disp..lo).(disp-hi)

inc

mem16

mod 001 rIm

(dlsp-Io).(disp..hi)

dec

mem16

mod 010 rIm

11111110

mod 011 rIm
mod 100 rIm
mod 101 rIm
mod 110 rIm
mod 111 rIm

11111111

mod 000 rIm

(disp-Io).(disp..hi)

inc

'mem16

mod 001 rIm
mod 010 rIm

(disp-Io).(disp..hi)

dec

mem16

(disp-Io).(disp..hi)

cali

regl61mem16 (inlrasegmenl)

mod 011 rIm

(disp-Io).(disp-hi)

cali

mem16 (inlersegmenl)

mod 100 rIm

(disp..lo).(disp-hi)

jmp

regl61mem16 (inlrasegmenl)

mod 101 rIm

(disp-Io).(disp-hi)

jmp

mem16 (inlersegmenl)

mod 110 rIm

(disp..lo).(disp-hi)

push

mem16

mod 111 rIm

ASM-8& Instruction Format

Bytes 3-6

Binary

D-19

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table D-4. Mnemonic Encoding Matrix (Left Half)
KG

ADD

Ox
1x

2x
AM

3x
4x
5x
6x
7x

ex
Dx

Fx
NOTE: Table 0·5 defines abbreviations used In this matrix. Shading indicates reserved opcodes.

0·20

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table 0-4. Mnemonic Encoding Matrix (Right Half)

PUSH

b.t.r/m

w.t.r/m

SBB

b.t.r/m
SBB

w.t.r/m

SBB

b.i
SBB

-"'Ii
SBB

_CS
PUSH

b,t.r/m

w,t.r/m

b,t.r/m

w,t,r/m

SUB

b,i
SUB

w,i
SUB

OS
SEG

b,t,r/m

w.t,r/m

b,t,r/m

w.t,r/m

CMP

b.i
CMP

w,i
CMP

=CS
SEG

AAS

b,t.r/m

w.t.r/m

b,t,r/m

w,t,r/m

DEC

b,i
DEC

w.i
DEC

=OS
DEC

DEC

AX
POP

CX
POP

OX
POP

BX
POP

SP
POP

BP
POP

SI
POP

POP

AX
PUSH

CX
IMUL

OX
PUSH

BX
IMUL

SP
INS

BP
INS

SI
OUTS

OUTS

w.i
JS

w,i
JNS

b,i

JNU

JPE

w,i
JNPI
JPO

JPI

JNGE

JGE

b
JLEI
JNG

w
JNLEI
JG

LEA

MOV

POP

sr.t.r/m

rim

SAHF

LAHF

SBB

OS
OAS

1x
2x
3x

MOV

b.t.r/m

w.t.r/m

sr.t.r/m

CBW

CWO

b.t.r/m
CALL

WAIT

PUSHF

TEST

L,O
STOS

bJa_
MOV

'JV,ia
MOV

MOV

i.... AX
ENTER

i....CX
LEAVE

i.... OX
RET

i.... BX
RET

i....SP
INT

i.... BP
INT

i.... SI

INTO

i.... OI
IRET

I
ESC

(any)

ESC

l(i+SP)
ESC

tvpe3

ESC

CALL

JMP

2
JMP

JMP

OUT

CLC

STC

CLI

STI

CLS

STD

Grp2

b,r/m

w,r/m

POPF

POP

4x
5x
6x
7x
8x
9x

STOS

LOOS

SCAS

Ax
Bx
CX
OX
Ex
Fx

NOTE: Table 0-5 defines abbreviations used in this matrix. Shading indicates reserved opcodes.

D-21

intelQt

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table 0·5. Abbreviations for Mnemonic Encoding Matrix
Abbr

Definition

Abbr

Definition

Abbr

Definition

Abbr

Definition

to CPU register

byte operation

immediate to 8!1Cumulator

memory

direct

Indirect

rIm

EA is second byte

variable

from CPU register

immediate byte, sign extended

short intrasegment

word operation

immediate

long (intersegment)

segment register

w
z

zero

Byte 2

Immed

mod 000 rIm
mod 001 rIm
mod 010 rim

ADC

RCL

NOT

CALL id

mod 011 rim

SBB

RCR

NEG

CALLI, id

mod 100 rIm

AND

SHLIBAL

MUL

JMPld

mod 101 rIm

SUB

SHR

IMUL

JMPi,ld

Shift

Grp1

ADD

ROL

lEST

INC

ROR

DEC

Grp2

mod 110 rim

XOR

DIV

PUSH

mod 111 rIm

CMP

BAR

IDIV

mod and rhn determine the Effective Address (EA) calculation. See Table 0-1 for definttlons.

0·22

Index

in1et
INDEX
80C187 Math Coprocessor, 12-2-12-8
accessing, 12-10-12-11
arithmetic instructions, 12-3-12-4
bus cycles, 12-11
clocking, 12-10
code examples, 12-13-12-16
comparison instructions, 12-5
constant instructions, 12-6
data transfer instructions, 12-3
data types, 12-7-12-8
design considerations, 12-10-12-11
example floating point routine, 12-16
exceptions, 12-13
I/O port assignments, 12-10
initialization example, 12-13-12-16
instruction set, 12-2
interface, 12-7-12-13
and chip-selects, 6-14, 12-11
and PCB location, 4-7
exception trapping, 12-13
generating READY, 12-11
processor control instructions, 12-6
testing for presence, 12-10
transcendental instructions, 12-5
8259A Programmable Interrupt Controllers, 8-1
and special fully nested mode, 8-8
cascading, 8-7, 8-8
interrupt type, 8-9
priority structure, 8-8
82C59A Programmable Interrupt Controller
interfacing with, 3-25-3-27

A
Address and data bus, 3-1-3-6
16-bit, 3-1-3-5
considerations, 3-7
.8-bit, 3-5-3-6
considerations, 3-7
See also Bus cycles, Data transfers
Address bus, See Address and data bus
Address space, See Memory space, I/O space
Addressing modes, 2-27-2-36
and string instructions, 2-34
based, 2-30,2-31,2-32

based index, 2-34,2-35
direct, 2-29
immediate operands, 2-28
indexed, 2-32, 2-33
indirect, 2-36
memory operands, 2-28
register indirect, 2-30, 2-31
register operands, 2-27
AH register, 2-5
AL register, 2-5,2-18,2-23
ApBUILDER files, obtaining from BBS, 1-6
Application BBS, 1-5
Architecture
CPU block diagram, 2-2
device feature comparisons, 1-2
family introduction, 1-1
overview, 1-1,2-1
Arithmetic
instructions, 2-19-2-20
interpretation of 8-bit numbers, 2-20
Arithmetic Logic Unit (ALU), 2-1
Array bounds trap (Type 5 exception), 2-44
ASCII, defined, 2-37
Asynchronous inputs, synchronizing, B-2
Auxiliary Flag (AP), 2-7,2-9
AX register, 2-1,2-5,2-18,2-23,3-6

B
Base Pointer (BP), See BP register
Baud Rate Compare Register (BxCMP), 10-12
Baud Rate Counter Register (BxCNT), 10-11
BBS, 1-5
BCD, defined, 2-37
Bit manipulation instructions, 2-21-2-22
BOUND instruction, 2-44, A-8
BP register, 2-1,2-13,2-30,2-34
Breakpoint interrupt (Type 3 exception), 2-44
Bus cycles, 3-20-3-45
address/status phase, 3-10-3-12
and 80C187, 12-11
and CSU; 6-14
and Idle mode, 5-13
and PCB accesses, 4-4
and Powerdown mode, 5-16

Index-1

INDEX

and T-states, 3-9
data phase, 3-13
HALT cycle, 3-28-3-34
and chip-selects, 6-4
HALT state, exiting, 3-30-3-34
idle states, 3-18
instruction prefetch, 3-20
interrupt acknowledge (INTA) cycles, 3-6,
3-25-3-26,8-9
and chip-selects, 6-4
operation, 3-7-3-20
priorities, 3-44-3-45, 7-2
read cycles, 3-20-3-21
refresh cycles, 3-22, 7-4, 7-5
control signals, 7-5,7-6
during HOLD, 3-41-3-43,7-13-7-14
wait states, 3-13-3-18
write cycles, 3-22-3-25
See also Data transfers
Bus hold protocol, 3-39-3-44
and CLKOUT, 5-6
and CSU, 6-15
and Idle mode, 5-14
and refresh cycles, 3-41-3-43, 7-13-7-14
and reset, 5-9
latency, 3-40-3-41
Bus Interface Unit (BID), 2-1,2-3,2-11,3-1-3-45
and DRAM refresh requests, 7-4
and TCU, 9-1
buffering the data bus, 3-35-3-37
modifying interface, 3-34-3-37, 3-37
relationship to RCU, 7-1
synchronizing software and hardware events,
3-37-3-38
using a locked bus, 3-38-3-39
using multiple bus masters, 3-39-3-44
BX register, 2-1, 2-5, 2-30

C
Carry Flag (CP), 2-7,2-9
Chip-Select Unit (CSU), 6-1
and HALT bus cycles, 3-28
and READY, 6-11-6-12
and wait states, 6-11-6-12
block diagram, 6-3
bus cycle decoding, 6-14
examples, 6-15-6-20

Index-2

features and benefits, 6-1
functional overview, 6-2-6-5
programming, 6-5--6-15
registers, 6-5--6-15
system diagram, 6-16
See also Chip selects
Chip-selects
activating, 6-4
and 80C187 interface, 6-14, 12-11
and bus hold protocol, 6-15
and DRAM controllers, 7-1
and guarded memory locations, 6-20
and reserved 110 locations, 6-14
enabling and disabling, 6-11
initializing, 6-6-6-15
methods for generating, 6-1
multiplexed 110 port pins, 11-7
overlapping, 6-12-6-14
programming considerations, 6-14
start address, 6-10,6-14
stop address, 6-10
timing, 6-4
CL register, 2-5, 2-21, 2-22
CLKOUT
and bus hold, 5-6
and power management modes, 5-6
and reset, 5-6
Clock generator, 5-6-5-10
and system reset, 5-6-5-7
output, 5-6
synchronizing CLKOUT and RESOUT, 5-65-7
Clock sources, TCU, 9-12
Code (programs), See Software
Code segment, 2-5
Counters, See Timer Counter Unit (TCU)
CPU, block diagram, 2-2
Crystal,See Oscillator
CS register, 2-1,2-5,2-6,2-13,2-23,2-39,2-41
Customer service, 1-4
CX register, 2-1,2-5,2-23,2-25,2-26

D
Data, 3-6
Data bus, See Address and data bus
Data segment, 2-5
Data sheets, obtaining from BBS, 1-6

intet

INDEX

Data transfers, 3-1-3-6
instructions, 2-18
PCB considerations, 4-5
PSW flag storage formats, 2-19
See also Bus cycles
Data types, 2-37-2-38
DI register, 2-1,2-5,2-13,2-22,2-23,2-30,2-32,
2-34
Digital one-shot, code example, 9-17-9-23
Direction Rag (DF), 2-7,2-9,2-23
Display, defined, A-2
Divide Error trap (Type exception), 2-43
Documents, related, 1-3
DRAM controllers
and wait state control, 7-5
clocked, 7-5
design guidelines, 7-5
unclocked, 7-5
See also Refresh Control Unit
DS register, 2-1,2-5,2-6,2-13,2-30,2-34,2-43
DX register, 2-1,2-5,2-36,3-6

E
Effecti ve Address (EA), 2-13
calculati on, 2-28
Emulation mode, 13-1
End-of-Interrupt (EDI)
command, 8-21
register, 8-21, 8-22
ENTER instruction, A-2
ES register, 2-1,2-5,2-6,2-13,2-30,2-34
Escape opcode fault (Type 7 exception), 2-44, 12-1
Examples, code, See Software
Exceptions, 2-43-2-44
priority, 2-46-2-49
Execution Unit (EU), 2-1,2-2
Extra segment, 2-5

F
Fault exceptions, 2-43
FaxBack service, 1-5
F-Bus
and PCB, 4-5
operation, 4-5
Rags, See Processor Status Word (PSW)
Floating Point, defined, 2-37

H
HALT bus cycle, See Bus cycles
HOLD/HLDA protocol, See Bus hold protocol
Hypertext manuals, obtaining from BBS, 1-6

I/O devices
interfacing with, 3-6-3-7
memory-mapped, 3-6
110 ports, 11-1-11-12
addressing, 2-36
bidirectional, 11-1
configuration example, 11-12
initializing, 11-11
input-only, 11-3
open-drain bidirectional, 11-3
output-only, 11-3
overview, 11-1
port 1, 11-7
port 2, 11-7
programming, 11-7...:11-12
registers, 11-7-11-11
reset status, 11-11
110 space, 3-1-3-7
accessing, 3-6
reserved locations, 2-15,6-14
Idle mode, 5-11-5-16,5-16
bus operation, 5-13
control register, 5-12
entering, 5-11, 5-13
exiting, 5-14-5-15
exiting HALT bus cycle, 3-34
initialization code, 5-15-5-16
Idle states
and bus cycles, 3-18
Immediate operands, 2-28
IMUL instruction, A-9
Input/output ports, 11-1
Inputs, asynchronous, synchronizing, B-1
INS instruction, A-2
In-Service register, 8-5,8-7,8-18,8-19
Instruction Pointer (lP), 2-1,2-6,2-13,2-23,2-39,
2-41
reset status, 2-6
Instruction prefetch bus cycle, See Bus cycles
Instruction set, 2-17, A-I, D-l
additions, A-I

Index-3

INDEX

arithmetic instructions, 2-19-2-20, A-9
bit manipulation instructions, 2-21-2-22, A-9
data transfer instructions, 2-18-2-20, A-I,
A-8
data types, 2-37-2-38
enhancements, A-8
high-level instructions, A-2
nesting, A-2
processor control instructions, 2-27
program transfer instructions, 2-23-2-24
reentrant procedures, A-2
rotate instructions, A-IO
shift instructions, A-9
string instructions, 2-22-2-23, A-2
!NT instruction, single-byte, See Breakpoint
inte"upt
INTO instruction, 2-44
INTA bus cycle, See Bus cycles
Integer, defined, 2-37, 12-7 .
Interrupt Control registers, 8-12
for external pins, 8-14, 8-15
for intemal sources, 8-13
Interrupt Control Unit (lCU), 8-1-8-24
block diagram, 8-2
cascade mode, 8-7
initializing, 8-23, 8-24
interfacing with an 82C59A Programmable
Interrupt Controller, 3-25-3-27
operation with nesting, 8-4
programming, 8-11
registers, 8-11
special fully nested mode, 8-8
with cascade mode, 8-8
without cascade mode, 8-8
typical interrupt sequence, 8-5
Interrupt Enable Flag (IF), 2-7,2-9,2-41
Interrupt Mask register, 8-17
Interrupt Request register, 8-16
Interrupt Status register, 8-7,8-22,8-23
Interrupt Vector Table, 2-39,2-40
Interrupt-on-overflow trap (Type 4 exception),
2-44
Interrupts, 2-39-2-43
and CSU initialization, 6-6
controlling priority, 8-12
edge- and level-sensitive, 8-10
and extemal8259As, 8-10
enabling cascade mode, 8-12
Index-4

enabling special fully nested mode, 8-12
latency, 2-45
reducing, 3-28
latency and response times, 8-10, 8-11
maskable, 2-43
masking, 8-2,8-12,8-17
priority-based, 8-18
multiplexed, 8-7
nesting, 8-4
NMI,2-42
nonmaskable, 2-45
overview, 8-1
priority, 2-46-2-49, 8-3
default, 8-3
resolution, 8-5, 8-6
processing, 2-39-2-42
reserved, 2-39
response time, 2-46
selecting edge- or level-triggering, 8-12
software, 2-45
timer interrupts, 9-16
types, 8-9
See also Exceptions, Inte"upt Control Unit
INTn instruction, 2-45
Invalid opcode trap (Type 6 exception), 2-44
IRET instruction, 2-41

L
LEAVE instruction, A-7
Local bus, 3-1,3-39, 12-11
Long integer, defined, 12-7
Long real, defined, 12-7

M
Math coprocessing, 12-1
hardware support, 12-1
overview, 12-1
Memory
addressing, 2-28-2-36
operands, 2-28
reserved locations, 2-15
Memory devices, interfacing with, 3-6-3-7
Memory segments, 2-8
accessing, 2-5,2-10,2-11,2-13
address
base value, 2-10,2-11,2-12
Effective Address (EA), 2-13

INDEX

logical, 2-10, 2-12
offset value, 2-10, 2-13
overriding, 2-11, 2-13
physical, 2-3,2-10,2-12
and dynamic code relocation, 2-13
Memory space, 3-1-3-6

N
Normally not-ready signal, See READY
Normally ready signal, See READY
Numerics coprocessor fault (Type 16 exception),
2-44, 12-13

o
ONCE mode, 13-1
One-shot, code example, 9-17-9-23
Ordinal, defined, 2-37
Oscillator
external
and powerdown, 5-19
selecting crystal, 5-5
using canned, 5-6
internal crystal, 5-1-5-10
controlling gating to internal clocks,
5-18
operation, 5-2-5-3
selecting C 1 and L1 components, 5-35-6
OUTS instruction, A-2
Overflow Flag (OF), 2-7, 2-9, 2-44

p
Packed BCD, defined, 2-37
Packed decimal, defined, 12-7
Parity Flag (PP), 2-7,2-9
PCB Relocation Register, 4-1, 4-3, 4-6
and math coprocessing, 12-1
PDTMR pin, 5-18
Peripheral Control Block (PCB), 4-1
accessing, 4-4
and P:Bus operation, 4-5
base address, 4-6-4-7
bus cycles, 4-4
READY signals, 4-4
reserved locations, 4-6
wait states, 4-4
Peripheral control registers, 4-1, 4-6

Pointer, defined, 2-37
Poll register, 8-9, 8-19, 8-20
Poll Status register, 8-9,8-19,8-20,8-21
Polling, 8-1, 8-9
POPA instruction, A-I
Port Control Register (PxCON), 11-8
Port Data Latch Register (PxLTCH), 11-10
Port Direction Register (PxDIR), 11-9
Port Pin State Register (PxPIN), 11-11
Power consumption, reducing, 3-28,5-19
Power Control Register, 5-12
Power management, 5-10-5-19
Power management modes
and HALT bus cycles, 3-28,3-30,3-32
compared, 5-19
Powerdown mode, 5-16-5-19,7-2
and bus cycles, 5-16
control register, 5-12
entering, 5-17
exiting, 5-18-5-19
exiting HALT bus cycle, 3-33
initialization code, 5-15-5-18
Priority Mask register, 8-18
Processor control instructions, 2-27
Processor Status Word (PSW), 2-1,2-7,2-41
bits defined, 2-7,2-9
flag storage formats, 2-19
reset status, 2-7
Program transfer instructions, 2-23-2-24
conditional transfers, 2-24, 2-26
interrupts, 2-26
iteration control, 2-25
unconditional transfers, 2-24
Programming examples, See Software
PUSH instruction, A-8
PUSHA instruction, A-I

R
RCL instruction, A-lO
RCR instruction, A-lO
Read bus cycles, See Bus cycles
READY
and chip-selects, 6-11
and normally not-ready signal, 3-16-3-18
and normally ready signal, 3-16-3-17
and PCB accesses, 4-4
and wait states, 3-13-3-18

Index-5

INDEX

block diagram, 3-15
implementation approaches, 3-13
timing concerns, 3-17
Real, defined, 12-7
Real-time clock, code example, 9-17-9-20
Refresh address, 7-4
Refresh Address Register (RFADDR), 7-10
Refresh Base Address Register (RFBASE), 7-7,
7-8
Refresh bus cycle, See Bus cycles
Refresh Clock Interval Register (RFTIME), 7-7,
7-8
Refresh Control Register (RFCON), 7-9,7-10
Refresh Control Unit (RCU), 7-1-7-14
and bus hold protocol, 7-13-7-14
and Powerdown mode, 7-2
block diagram, 7-1
bus latency, 7-7
calculating refresh interval, 7-7
control registers, 7-7-7-10
initialization code, 7-11
operation, 7-2
overview, 7-2-7-4
programming, 7-7-7-12
relationship to BIU, 7-1
Register operands, 2-27
Regi~ters, 2-1
control, 2-1
data, 2-4,2-5
general, 2-1,2-4,2-5
H & L group, 2-4
index, 2-5,2-13,2-34
P & I group, 2-4
pointer, 2-1,2-5,2-13
pointer and index, 2-4
segment, 2-1,2-5,2-11,2-12
status, 2-1
Relocation Register, See PCB Relocation Register
Reset
and bus hold protocol, 5-6
and clock synchronization, 5-6-5-10
cold, 5-7, 5-8
RC circuit for reset input, 5-7
warm, 5-7, 5-9
ROL instruction, A-IO
ROR instruction, A-I0

Index-6

S
SAL instruction, A-9
SAR instruction, A-9
Serial Communications Unit (SCU)
asynchronous communications, 10-1-10-8,
10-13-10-18
example, 10-24-10-28
mode 1, 10-6
mode 2, 10-7
mode 3, 10-6
mode4, 10-6
baud rates, 10-10--10-13
bilUd timebase clock, 10-21, 10-22
BCLK pin timings, 10-19-10-21
break characters, 10-4, 10-15
channel 0 interrupts, 10-22
channell interrupts, 10-22
crs# pin timings, 10-19
examples, 10-24-10-36
features, 10-1
framing errors, 10-4
hardware considerations, 10-19-10-22
interrupts, 10-22
master/slave example, 10-28-10-36
multiprocessor communications, 10-14
overrun errors, 10-4
overvie\v, 10- 1-10-8
parity errors, 10-4
programming, 10-9-10-19
receiver, 10-2
RX machine, 10-2
stand-alone communications, 10-13
synchronous communications, 10-8, 10-19
example, 10-27
timings, 10-21
transmitter, 10-4
TX machine, 10-4
Serial Port Control Register (SxCON), 10-16
Serial Port Status Register (SxSTS), 10-17, 10-18
Serial ports, See Serial ConimlUlications Unit
(SCU)
•
Serial Receive Buffer Register (SxRBUF), 10-9
Serial Transmit Buffer Register (SxTBUF), 10-10
SHL instruction, A-9
Short integer, defined, 12-7
Short real, defined, 12-7

INDEX

SHR instruction, A-9
Sl register, 2-1,2-5,2-13,2-22,2-23,2-30,2-32,
2-34
Sign Flag (SF), 2-7, 2-9
Single-step trap (Type 1 exception), 2-43
Software
code example
80C187 floating-point routine, 12-16
80C187 initialization, 12-13-12-15
digital one-shot, 9-17-9-23
I/O port configuration, 11-12
ICU initialization, 8-24
real-time clock, 9-17-9-19
SCU asynchronous mode, 10-24
SCU master/slave network, 10-2810-36
initialization code, 10-30-10-32
_select_slave routine, 10-31-10-32
_send_slave30mmand routine,
10-36
_slave_l routine, 10-33-10-35
SCU synchronous mode, 10-27
square-wave generator, 9-17-9-22
TCU configurations, 9-17-9-23
data types, 2-37, 2-38
dynamic code relocation, 2-13,2-14
interrupts, 2-45
overview, 2-17
See also Addressing modes, Instruction set
Square-wave generator, code example, 9-17-9-22
SS register, 2-1,2-5,2-6,2-13,2-15,2-30,2-45
Stack frame pointers, A-2
Stack Pointer, 2-1,2-5,2-13,2-15,2-45
Stack segment, 2-5
Stacks, 2-15
START registers, CSU, 6-5,6-7,6-11
STOP registers, CSU, 6-5,6-8,6-12
String instructions, 2-22-2-23
and addressing modes, 2-34
and memory-mapped I/O ports, 2-36
operand locations, 2-13
operands, 2-36
Strings
accessing, 2-13,2-34
defined, 2-37
Synchronizing asynchronous inputs, B-1

T
Temporary real, defined, 12-7
Terminology
"above" vs "greater", 2-26
"below" vs "less", 2-26
device names, 1-2
Timer Control Registers (TxCON), 9-7, 9-8
Timer Count Registers (TxCNT), 9-10
Timer Counter Unit (TCU), 9-1-9-23
application examples, 9-17-9-23
block diagram, 9-2
clock sources, 9-12
configuring a digital one-shot, 9-17-9-23
configuring a real-time clock, 9-17-9-19
configuring a square-wave generator, 9-179-22
counting sequence, 9-12-9-13
dual maxcount mode, 9-13-9-14
enabling and disabling counters, 9-15-9-16
frequency, maximum, 9-17
initializing, 9-11
input synchronization, 9-17
interrupts, 9-16
overview, 9-1-9-6
programming, 9-6-9-16
considerations, 9-16
pulsed output, 9-14-9-15
retriggering, 9-13-9-14
setup and hold times, 9-16
single maxcount mode, 9-13,9-14-9-16
timer delay, 9-1
timing, 9-1
and BIU, 9-1
considerations, 9-16
TxOUT signal, 9-15
variable duty cycle output, 9-14-9-15
Timer Maxcount Compare Registers (TxCMPA,
TxCMPB), 9-11
Timers, See Timer/Counter Unit (TCU), Watchdog
timer
Trap exceptions, 2-43
Trap Flag (TF), 2-7,2-9,2-43,2-48
T-state
and bus cycles, 3-9
and CLKOUT, 3-8
defined, 3-7

Index-7

INDEX

w
Wait states
and bus cycles, 3-13
and chip-selects, 6-11-6-14
and DRAM controllers, 7-1
and PCB accesses, 4-4
and READY input, 3-13
Word integer. defined, 12-7
Write bus cycle. 3-22

Z
Zero Flag (ZF). 2-7. 2-9, 2-23

Index-8

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