27_WD10C23 27 WD10C23
User Manual: 27_WD10C23
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WD10C23 Self-Adjusting Data Separator ee:e WESTERN DIGITAL • WD10C23 TABLE OF CONTENTS Section Title 1.0 INTRODUCTION ....................................................... 27-1 1.1 Features ........................................................ 27-1 DESCRIPTION ........................................................ 27-2 2.1 Zone Bit Recording ................................................ 27-2 2.2 Read Operations . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5 2.3 Write Operations .................................................. 27-5 EXTERNAL COMPONENTS PARTS LIST ................................... 27-6 PIN DESCRIPTIONS. . . . . . . . . . . . . . . .. . ................................. 27-8 ARCHITECTURE ..................................................... 27-10 5.1 Synchronization Field Detector ...................................... 27-10 5.2 Acquisition Sequencer ...................................... : ...... 27-10 5.3 Phase-Locked Loop (PLL) .......................................... 27-11 5.4 Read Data Conditioner ............................................ 27-12 5.5 Read Data Detector ............................................... 27-12 5.6 Phase Margining .......•......................................... 27-12 5.7 Crystal Oscillator ................................................. 27-16, 5.8 Write Data Conditioner ............................................ 27~16 5.9 Delay-Locked Loop,(DLL) .......................................... 27-16 5.10 Pulse Former .................................................... 27-16 5.11 Power-on Reset .................................................. 27-16 5.12 Test Modes ..................................................... 27-17 ELECTRICAL CHARACTERISTICS ....................................... 27-19 6.1 Absolute Maximum Ratings ......................................... 27-19 6.2 Standard Test Conditions .......................................... 27-19 6.3 Digital Signals ................................................... 27-20 6.4 Analog Signals (Crystal Oscillator) ................................... 27-23 6.5 Phase-Locked Loop .............................................. 27-24 TIMING CHARACTERISTICS ......................... ,................... 27-27 7.1 Disk Drive Raw Read Data ......................................... 27-27 7.2 Disk Drive Raw Read Data Frequency Detector ......................... 27-28 7.3 Read Data Conditioner ............................................ 27-29 7.4 Read Data Detector (Percentage Window Shift) ........................ 27-30 7.5 Read Data Detector (Adaptive Window Shift) ........................... 27-30 7.6 Phase-Frequency Detector ......................................... 27-31 7.7 Write Data Conditioner ............................................ 27-33 7.8 TTL XTALIN Input Clock, WCLK Output ............................... 27-33 7.9 Delay Line ...................................................... 27-35 PRODUCT COMPATIBILITY ............................................. 27-38 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Page ADVANCE INFORMATION 11-26-90 27-i WD10C23 LIST OF ILLUSTRATIONS Fig ute Title 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin Designation (DIP) ................................................... 27-1 Pin Designation (QUAD) ................................................. 27-1 WD10C23 Block Diagram ................................................ 27-4 External Components ................................................... 27-7 AWS Optimum Center Frequency ......................................... 27-1t. AWS Non-Optimum Frequency ........................................... 27-14 Disk Drive Raw Read Data liming ........................................ 27-27 Read Data Conditioner Timing ............................................ 27-29 Phase Detection liming ................................................. 27-32 Velocity Lock Mode .................................................... 27-32 Write Data Conditioner Timings ........................................... 27-34 Delay Line Timing ..................................................... 27-35 Hard Sector Format wlWG Pulse Option .................................... 27-36 Hard Sector Format w/Soft Sector RIW ..................................... 27-37 Table Title 2 3 4 Frequency Band Selection ................................................ 27-3 Phase Margin Control .................................................. 27-15 Test Mode Matrix ... ................................................... 27-18 Product Compatibility for Data Separators .................................. 27-38 Page LIST OF TABLES 27~ii Page ADVANCE INFORMATION 11-26-90 WD10C23 INTRODUCTION 1.0 INTRODUCTION The WD10C23 ReadlWrite Channel is an LSI device implemented in 1.25 micron high-speed CMOS. It is specifically designed to be compatible with the Western Digital WD53C221 42C221 WD50C12 series of Hard Disk Controllers, and with disk drives conforming to the popular ST506/412 interface standard and recent speedenhanced versions. In addition it will support optical applications when used with the WD60C31 A ENDEC. SHIFT2X 28 GND 27 LPF WGATE 28 VCON RGATE 25 PUMP WPCEN 24 VCC 23 RCLK 22 RDATA 21 SCiCOlIST WCLK 9 20 VF1 XTALIN 10 19 tiS XTALOUT 11 18 WSCLK DRUN 12 17 RLlJIIiIFJI1 VF2 13 16 WPCDATA RAWDATA 14 15 VFO WDATA 1.1 Features • 5-15Mbitlsec data rates with no component changes • Fixed/variable frequency control for zone bit recording • Pin selectible hard/soft sector support and 2,7 RLLcoding • Precision internal self-adjusting VCO -compensates for component, temperature, voltage, and aging variations . -one sigma phase jitter to within 250 psec at 15 Mbitlsec • Dual gain charge pump -high gain for faster frequency acquisition -low gain for greater jitter rejection -charge pump balance to within ± 5% • Dual mode phase frequency detector -phase frequency detection for velocity lock on XTALIN reference and on the data synchronization field, thus eliminating quadrature and harmonic locks -phase only detection (phase lock) while tracking data -phase window centering is precisely controlled to within ± 1 nsec • Frequency independent data detection window optimization -window centering is precisely controlled to within ±1 nsec -window loss controlled to withil') 1 nsec -"built in" PMA with window shifting from 0 to 100% at ± 1 nsec accuracy -adaptive window centering for correction for channel antisymmetry • Crystal controlled processing of the write data OPTICAL FIGURE 1. PIN DESIGNATION (DIP) VCON LPF 27 OPTICA 28 18 WSCLK 17 RLL.!MFM 16 WPCDATA SHIFT2X 15 VFO GND 14 RAWDATA WGATE VF2 RGATE DRUN FIGURE 2. PIN DESIGNATION (QUAD) • Dual level precompensation of ±6.25% and/or ± 12.5% of the window, accurate to within ± 1 nsec ADVANCE INFORMATION 11-26-90 27-1 WD10C23 2.0 DESCRIPTION DESCRIPTION The WD10C23 uses a single 5 volt supply and has been designed for 5Mbitlsec MFM encoding, or 5 to 15 Mbit/sec data rates using RLL encoding. Variable frequency applications, or various fixed frequency applications may be accommodated through selection of the VF control bus. One of the key features of the WD10C23 is the group of internal delay lines, that are automatically set by the XTALIN frequency. These precision elements allow for a high degree of accuracy in the handling of write precompensation, window centering, and window shifting. Further developments in this technology enable the unique implementation of Adaptive Window Shifting/Centering (AWS). In a typical application, the WDj OC23 performs all of the handling of the sensitive read/write signals between a disk controller and data drivers and receivers. Read data corresponds to previous write data, with added phase, frequency, and write splice noise. The fundamental purpose of the WD10C23 is to remove these sources of noise, and present a clean digital signal to the controller. 27-2 2.1 Zone Bit Recording The WD10C23 was designed for use in zone bit recording schemes. In these applications, the data rate is varied to create a fixed bit density (flux transitions/inch or Fel) from the outer radius of the media. To maintain optimum performance as the data rate changes, loop parameters (i,e., gain, bandwidth, etc.) must be modified. This is accomplished through selection of appropriate frequency bands. The WD10C23 accommodates five different bands. COMP: 5 Mbitlsec MFM and 7.5 Mbitlsec RLL BANDO: RLL, variable frequencies ranging from 5 to 7.5 Mbitlsec BAND1: RLL, variable frequencies ranging from 7.5 to 10.6 Mbitlsec BAND2: RLL, variable frequencies ranging from 10.6 to 15 Mbitlsec BAND3: RLL, 15 Mbitlsec BANDO-3 may be programmed for zone bit recording, or strapped for fixed frequency applications. In these four bands, LPF must be connected to the external filter, and an external resistor placed across PUMP and VCON. The COMP band allows for backwards compatibility with previous Western Digital data separators through component de-population. See Table 1 for information to help you select a frequency band that is appropriate for your application. The Table 1 columns, Ko and Kcl, when unbroken, represent regions across which the gains are montonic. Across these boundaries, defined by a change in the state of the VFONF1 controls, the gains are re-centered to optimize for the respective frequency bands. ADVANCE INFORMATION 11-26-90 WD10C23 DESCRIPTION Recording Mode Select V F 1 V F R L L 0 Frequency Band (Data Rate MHz) Band Name VCO Charge Open Filter Reslstors* Gain Pump Loop Pump-VCON LPFt_ Ko Galn·* Gain INT* EXT INT EXT KcI Fixed Frequency Fixed or Variable Frequency Formats Z Z 0 1 0 0 0 1 1 1 1 0 1 Kol Comp ~ ~ 3ka BandO Band1 Kor Koo Ko1 Kolr KoIO Kol1 10.6< / <15.0 Band2 Band3 /=15.0 Ko2 Ko3 '/=5.0 /=7.5 5.0.s./<7.5 7.5....s./.s.10.6 Kd2 Kd3 00 00 00 00 Kol2 6ka Kol3 3.5ka 3kn -2.8ka - 5250 3070 1500 - TABLE 1. FREQUENCY BAND SELECTION *The following information is not intended to represent device specifications, but is indicative of typical values. See the PLL section for actual specifications. **Charge Pump Gain, and thus, Loop Gain, is reduced by half in phase lock. tLPF internal resistance is to GROUND, external resistance is to the filter fPUMP to VCON internal resistor is shorted during velocity lock ADVANCE INFORMATION 11-26-90 27-3 • WD10C23 DESCRIPTION 'J" data -12.5% -6.25% 0% Multiplexor +6.25% +12.5% Delay To Ex1emal Filler PUMP LPF + 12.5 select Delay REF Phase elk Deteclor Phase Error Charge Filter VCON VCO Pump DRU 2/416 req RDATA data Hard Disk ref ell Acquisition Sequencer TRACK FIGURE 3. WD10C23 BLOCK DIAGRAM 27-4 ADVANCE INFORMATION 11-26-90 PTICAL RCLK Controller WD10C23 DESCRIPTION 2.2 Read Operations 2.3 The WD10C23 performs phase-locked loop data synchronization on read data from the drive. For soft-sector applications, an on-board synch field detector automatically switches the PLL from the stable crystal reference to the read data. Phasefrequency detection (velocity lock) is used at the beginning of the synch field to quickly and reliably acquire lock to the data. Use of this technique eliminates susceptibility to harmonics and asymmetry. The WD1 OC23 then switches to phase-only detection to complete the phase acquisition before the end of the synch field, and to enable tracking of random read data. The phase jump at the acquisition-to-tracking switchover due to multiplexing, seen in other circuits, is avoided through the use of a zero phase jump design. When switching to phase detection, the WD10C23 reduces the charge pump gain for better jitter rejection. A preCisely centered detector samples the data at twice the underlying data rate to remove the phase jitter. A proprietary technique adjusts the window width, T, to the current data rate, providing greater phase margin. The regenerated signal, along with a fixed-phase synchronous clock, are output for the controller's digital circuits. Write Operations The WD10C23 performs conditioning on write data to the drive. Data from the controller is precisely synchronized with the crystal reference at twice the data frequency, thus minimizing the addition of digital phase jitter on the write data to the drive. If enabled, precompensation is achieved via delay taps available through proprietary CMOS delay line technology. The delay line is servo-controlled to the crystal reference for precision. Synchronized, precompensated write data is thus sent directly to the drive's write circuits. Precompensation levels are programmable to be either 12.5 or 6.25 percent of the window, defined by the inverse of the crystal frequency. The SH IFT2X input allows dynamic control of early and late precompensation magnitude for more complex precompensation schemes. In addition, SHIFT2X may be programmed using track information for zone bit precompensation schemes. ADVANCE INFORMATION 11-26-90 27-5 WD10C23 3.0 EXTERNAL COMPONENTS PARTS LIST EXTERNAL COMPONENTS PARTS LIST The parts list shown below gives typical component values for 5 Mbitlsec MFM and 5-15 Mbitlsec RLL data rates. Contact your local Western Digital sales representative for more information on how to change these values, to accommodate different data rates. See the diagram on the opposite page for the location of each component. 10C23 EXTERNAL COMPONENTS for 5 Mbits/sec (MFM) and 5-15 Mbits/sec (RLL) PART # TYPE VALUE C111 C112 C101 C106 L101 R107 R301 R302 capacitor capacitor capacitor capacitor ---------- cer. , SOlo, SOV, COG car. , SOlo, SOV, COG tan.,20%,10V +80-20%, SOV, zSu resistor resistor resistor 4700 pF 1S0 pF 47J.1F 0.1 J.1F 3.3 ohm S90 ohm 301 ohm 3.01Kohm Y101 C104 C10S crystal capacitor capacitor 10-1S MHz 68pF 47pF .01%,3Ieads car. , SOlo, SOV, COG cer. , SOlo, 50V, COG Y101 C104 C10S crystal capacitor capacitor 15-20 MHz 33pF 22pF .01%,3Ieads cer. , SOlo, SOV, COG cer. , SOlo, SOV, COG Y101 C104 C10S crystal capacitor capacitor 20-30 MHz 22pF 10pF .01 %, 3 leads cer. , SOlo, SOV, COG cer. , 5%, SOV, COG 27-6 SPECIFICATIONS 5%,114 w 1%, 1/4 W, 100 ppm 1%,114 W, 100 ppm 1%, 1/4 W, 100 ppm ADVANCE INFORMATION 11-26-90 WD10C23 EXTERNAL COMPONENTS PARTS LIST R302 resistor is left open for compatibility mode. R30! & R302 resistors are left open for BAN DO. Ll0l T Vee 24 ....CD ~= .~ ~ 0 U e (.) ~ Ul Ul 3 RGATE 4 WPEN 5 LATE 6 EARLY 7 8 WDATA WCLK 0c::: ....0 WGATE CD Control (.) 12 RCLK 23 VF2 13 20 e VFO WSCLK WSHIFT 25 22 "T1 (i) WD10C23 27 Rl07 15 18 a.. Preeomp [ SHIFT2 Magnitude c::: 0 m~[ .~ !:: RLLlMF 17 HS 15 OU OPTlCA~ -0..0 c::: • VCON 26 9 DRUN RDATA WSHIFT Freq Ba~d [ VFl Cl06 28 21 SC 14 16 RAWDATA 10 11 2 WPCDATA ] -. XTAlI:~ ~ XTALOUT g-g C/)(1) ~Cl0 Vss 0 <" (1) -'(1) g i3 '< FIGURE 4. EXTERNAL COMPONENTS ADVANCE INFORMATION 11-26-90 27-7 WD10C23 4.0 PINDESCRIPTIONS PIN DESCRIPTIONS Signals have the same pin numbers for both packages. PIN NUMBER 27-8 MNEMONIC SIGNAL NAME FUNCTION 1/0 SHIFT2X SHIFT2X Shift two times. When false, selects ±6.25% of the window for write precompensation and window shifting. When true, selects two times that amount or ± 12.5 of the window. Internal pull up. 2 GND GROUND GROUND. 3 WGATE WRITE GATE Write gate. Set high when recording onto the disk. Write gate takes precedence over read gate. 4 RGATE READ GATE Read gate. Set high when the Controller intends to read. 5 WPCEN WRITE PRECOMP ENABLE Write precompensation enable. When high, it enables EARLY, LATE, and SHIFT2X for precompensation. 6 LATE 7 EARLY EARLY 8 WDATA WRITE DATA 9 WCLK WRITE CLOCK 10 XTALIN XTALIN 11 XTALOUT XTALOUT 0 Output pins for a crystal oscillator circuit. 12 DRUN DATA RUN 0 The output of a frequency detector connected to RAW DATA. Short, high frequency periods cause it to go high; long, low frequency periods cause it to go low. Used for detecting high frequency synch fields. Not used in hard sector. 13 VF2 LATE VARIABLE FREQUENCY CONTROL Negative true inputs used to delay write data for write precompensation: Negative true inputs used to advance write data for write precompensation. Internal pullup. Write data to be conditioned and sent out through WPCDATA to be written onto the disk. 0 Clock signal at one half the XTALIN frequency. Input pins for a crystal oscillator circuit. If an external frequency source is desired, XTALIN can be driven and XTALOUT left open. Tri-state input used during reads to select the operating frequency bands for PLL. Also selects the window shift diagnostic modes. VF2 is compatible with the WSHIFT pin on the 1OC20Al21 Al20B/22B when VFO and VF1 are open. ADVANCE INFORMATION 11-26-90 WD10C23 PIN DESCRIPTIONS PIN NUMBER MNEMONIC SIGNAL NAME I/O FUNCTION 14 RAWDATA 15 VFO 16 WPCDATA 17 RLUMFM 18 WSCLK WINDOW SHIFT CLOCK Window shift clock reference. Internal pullup. 19 HS HARD SECTOR When true, disables DRUN qualification on reads. RGATE controls the acquisition sequence to and from data. Internal pull up. 20 VF1 VARIABLE FREQUENCY Variable frequency tri-state input used during reads to select the operating frequency bands for PLL. Also selects the window shift diagnostic modes. 21 SC/COAST SEEK COMPLETE When low, disables RAWDATA and keeps VCO on reference. May be used to coast through defects when tracking. Internal pullup. 22 RDATA READ DATA 0 Detected and regenerated version of RAWDATA. Jitter has been removed and pulses have been synchronized with RCLK. 23 RCLK READ CLOCK 0 VCO divided to the data rate. Tracks the base frequency of RAWDATA during a read operation; otherwise tracks the crystal frequency. 24 Vee 25 PUMP 26 VCON 27 LPF 28 OPTICAL RAW DATA Data received from the drive read circuits. Includes an internal pullup resistor to allow tri-state multiplexing of the drives' data receivers. VARIABLE FREQUENCY Variable frequency tri-state input used during reads to select the operating frequency bands for PLL. Also selects the window shift diagnostic modes. WRITE PRECOMP DATA 0 RLUMFM SELECT When high, selects RLL (2,7) mode. When low, selects MFM (1,3) mode. Internal pullup. POWER -SUPPLY PUMP +5 Volts. Power supply input. 1/0 Charge pump output to the external filter. VCOINPUT FILTER OUTPUT OPTICAL Write precompensation data sent to the drive write circuits. Low when WGATE is low. Input to the external filter. 0 Output of the external filter. 1/0 Optical mode select. Used to enable test modes. Internal pullup. ADVANCE INFORMATION 11-26-90 27-9 WD10C23 5.0 ARCHITECTURE ARCHITECTURE The twelve major functions within the WD10C23 are listed below: • Synchronization Field Detector • Acquisition Sequencer • Phase-Locked Loop (PLL) -Phase-Frequency Detector -Charge Pumps -Filter -Voltage Controiler Oscillator (VCO) • Read Data Conditioner • Read Data Detector • Phase Margining • Crystal Oscillator • Write Data Conditioner • Delay-Locked Loop (DLL) • Pulse Former • Power-on Reset • Test Modes 5.1 Synchronization Field Detector The purpose of this circuit is to reliability discriminate between the high frequency of a PLL synchronization field and the lower frequencies immediately preceding it. The criterion used is pulse period discrimination on RAWDATA. If the period between consecutive rising edges of RAWDATA is short with respect to the threshold, then DRUN will go high; if long, then DRUN will go 10w.The pulses in the synchronization field must have the shortest period in the format (Le. 3T for 2, 7 RLL; 2T for 1, 3 MFM). The pulses in the field preceding the synchronization field must have a period sufficient to drop DRUN. In MFM mode, the optimum discrimination threshold is set using an internal delay line. In RLL mode, the threshold is set digitally. . When a synchronization field is detected; DRUN will remain high until address mark detection. At this time, the Synchronization Field Detector is put to sleep. Upon de-assertion of RGATE, the Detector will be awakened. Although the Synchronization Field Detector is not used in hard sector mode (by either the controller or the internal Acquisition Sequencer), DRUN will still respond to pulse period information on RAWDATA. 27-10 5.2 AcquiSition Sequencer The Acquisition Sequencer sends sequencing control signals to the appropriate circuits when the WD10C23 switches between the read, write, and idle modes. 5.2.1 Idle-to-Read Sequencing The soft sector read sequence begins when the Synchronization Field Detector raises DRUN in response to high frequency data on the RAW~ DATA input. If DRUN remains high for two NRZ byte times, the Sequencer switches the Phase Frequency Detector from the crystal reference to the incomin~ data. The Phase-Frequency Detector is in phase-frequency (velocity lock) mode with the PLL set at high gain. At the end of six bytes of velocity lock to data, RGATE is polled. If the controller has been issued a read command, RGATE will be true, and the Sequencer will switch the Phase-Frequency Detector to phase lock mode phase lock. The charge pump are set for low gain for improved jitter rejection. At this time, the Acquisition Sequencer is put to sleep and disables the Synchronization Field Detector. Upon the dropping of RGATE, the Sequencer awakens the Synchronization Field Detector, sets the·Phase Detector back to velocity lock, and sets the charge pumps back to high gain. For hard sector formats, the acquisition sequence· is slightly altered. RGATE alone initiates the acquisition sequence data, without qualification of the Synchronization Field Detector. At the end of eight bytes in velocity lock, the sequence is as described above. 5.2.2 Idle-to-Write Sequencing The write sequencer is initiated by the assertion of WGATE. WGATE disables the Aquisistion Sequencer, which in turn puts the Synchronization Field Detector to sleep. The Phase Detector is forced to remain on the crystal reference for the duration of the write. ADVANCE INFORMATION 11-26-90 WD10C23 ARCHITECTURE 5.3 5.3.1 5.3.3 Filter Phase-Locked Loop (PLL) Phase~Frequency Detector The Phase-Frequency Detector can be operated in two modes. The velocity lock mode is used for acquisition when the PLL is switched to read data, and is always used when the PLL is following the reference crystal oscillator. Whenever the device is not reading, the PLL is locked to XTALIN. The second mode, phase lock, is standard phaseonly detection. The Acquisition Sequencer switches to this mode when frequency acquisition is essentially complete on data, and phase acquisition is nearly complete as well. Phase-only mode must, of course, be used to lock to the data following the synch field, since that will contain the three frequencies inherent in MFM or the six frequencies inherent in RLL mode. In either mode, the Phase-Frequency detector converts a phase difference between the veo and input to a pulse width equal to the phase difference. The polarity of the phase error determines whether a signal will be routed to the pump up or pump down circuitry in the Charge Pump section. 5.3.2 Charge Pumps This circuit converts the pulse widths received from the Phase-Frequency Detector to proportional amounts of charge into or out of the Filter. The symmetry of the Charge Pumps is continuously determined by the voltage on the VeON. A proprietary technique selects a pump up current which precisely matches that of the pump down at the given filter voltage. When in phase lock, the gain is reduced by two. The Filter converts the current pulses from the Charge Pumps to a voltage output to the veo. The Filter has been carefully designed to the specific requirements of damping factor, acquisition time, capture range, and jitter rejection; and within the context of its effect on veo operation. Roughly speaking, it functions to filter out high frequency signals due to RAWDATA read data jitter, while passing the low frequency signals associated with the more slowly varying underlying frequency of RAWDATA, and handling a step • change in input frequency when switching between drive data and reference. The Filter is internal, with the exception of external components. In variable frequency applications, two additional external resistors are required. 5.3.4 Voltage Controlled Oscillator(VCO) The veo consists of an internal charge pump and ring oscillator. Thus, the veo requires no expensive components, and has no tuning requirements for voltage, temperature, or aging. The veo converts the voltage developed by the Filter to a control voltage for the ring oscillator. The non-linear I-V characteristic inherent in most internal veo designs, is eliminated by a proprietary technique, and loop gain is linearized over a wide frequency band. The veo runs at four times the channel rate and is divided down for extremely high precision duty cycles. ADVANCE INFORMATION 11-26-90 27-11 WD10C23 5.4 ARCHITECTURE Read Data Conditioner This circuit synchronizes the output of the Read Data Detector and produces the signals RCLK and RDATA. RCLK is a square wave at either one or two times the data rate selected via the OPTICAL. input (see Table 3). During data tracking, the frequency of RCLK mirrors the slo:"ly varying frequency of th.e raw data from the drive, RAW DATA. RDATA is a regenerated form of RAWDATA, with all jitter removed and positive pulses one window wide. It is synchronous with RCLK. RCLK ~dges occur nominally in the center of RDATA pulses to allow sufficient setup and hold time for the digital circuits in the controllers that u~e these signals. For the 2XRCLK, .RDATA and RCLK edges are coincideht., RDATA is DC low during velocity lock, and is activated by the A~ quisition Sequencer approximately at the transItion to phase lock. RCLK will stop for several winclowS. at the transition to phase lock for internal synchronization of the Read Data Detector and Read Data Conditioner; 5.5 Read OatS Detector The Read Data Detector 'latches the incoming drive data and presents it to the synchronization circuits of the Read Data Conditioner. Window shifting. is performed here using one of several techniques described below. To maximize phase margin, the window at the Read bata. Detector is preCisely centered and tracks the tTequency of the incoming data. 5.6 Phase Margining Phase margining is performed at the Read Data Detector by shifting the incoming raw read data either early or late with respect to the Read Data Detector's sampling clock or strobe. Window shifting is accomplished in one of two fashions described below, and is summarized in Table 2. 5.6.1 Window Shifting as Percentage of the Window The first technique is compatible with previous Western Digital data separator designs. Window shifting is achieved by advanCing or delaying the raw read data to the Read Data Detector through precision internal delay stages. Shifting is programmable to either ±6.2S% or ± 12.S% of the window, and is inversely proportional to the crystal frequency. 27-12 Window shifting as a percentage of the window applies for fixed frequency as well as variable frequency applications. 5.6.2 Adaptive Window Shifting/Centering (AWS) This technique uses an external reference clock, WSCLK, to set the timing relationship of the r.aw read data to the Data Detector strobe. By allOWing for a continuous, precision, user controlled strobe placement, the effective detection window may be advanced or delayed as desired. This feature, when used in conjunction with micro-processor in.teraction at the VFO-2 inputs (see Table 2) may be used to: • Create an adaptive window centering scheme to offset any asymmetry induced by the read channel electronics • Provide system self-test in the form of built-in PMA capabilities • Execute error recovery algorithms Using AWS, the absolute range of window placement is dictated by the VFO-2 control pins. Once the· range, N, has been selected, window placement within that range is proportional to the period of the reference (WSCLK) with a gain of approximately 1/2 to 1/6. Thus, for every 1ns of change on the external source, window shift resolution ranges from 166 ps to SOO ps. The value of N is the closest value which represents one quarter of the window, T/4" for any given data rate. For each of the twelve rang~s, there exists some frequency on WSCLK for which the range is optimum. That is, the window position may be programmed symmetrically about this frequency up to plus or minus one-half window. When this center frequency is equal to the data rate, it is known as the Optimum Center Frequency, denoted f(N). Since "range" is now equal to "window", strobing may be programmed about f(N) up to ±window/2, denoted T/2. As the data rate varies from f(N), the range set by N may be insuffient to achieve window placement across the full window. However, placement across the full window may be obtained by using a different value of N for early shifting than that for late shifting. Here are some examples. ADVANCE INFORMATION 11-26-90 WD10C23 ARCHITECTURE Example 1: If the actual data rate is 10.4Mbit/sec, selecting N=12 gives a 10.4Mbit/sec center frequency, f(12). We have selected an Optimum Center Frequency. The window at 10.4Mbit/sec is 48ns. Varying WSCLK from 4.44Mhz to 12.32Mhz will allow window shifting over a range of 24ns to 72ns, or 48ns ±T/2 (Figure 5). For the partial range of 24ns to just under 48ns, the data is shifted from window center to the late edge of the window, respectively. This is equivalent to window shifting from Ons to 24ns, or Ons to +T/2. For the partial range of just over 48ns to 72ns, the data is shifted into the next window, from that window's early edge to its center, respectively. This is equivelant to window shifting from -24ns to Ons, or -T/2 ns to Ons. In the example, window shifting of ±T/2 was achieved. If however the actual data rate was 10Mbit/sec, a single value of N would be insufficient (we would not be at an Optimum Center Frequency). Example 2: For an actual data rate of 10Mbit/sec the window is 50ns. Again selecting N=12, the range of shifting achieved by varying WSCLK from 4.44Mhz to 12.32Mhz will be 24ns to 72ns, as in the example above (Figure 6). For the partial range of 25ns to just under 50ns, the data is shifted from window center to the late edge of the window respectively. This is equivelent to window shifting from Ons to 25ns respectively, or Ons to +T/2. For the partial range of just over 50ns to 72ns, _ _ the data is shifted into the next window, from ~ that window's early edge to 3ns from its center respectively. This is equivelant to window shifting from -25ns to -3ns respectively, or -window/2 ns to -3ns. Thus the range provided by N=12 is not sufficient to allow early window shifting over the full half window. If N were selected to be 13, the range would change from 24-72ns, to 26-78ns. Using the same analysis as above, this would. allow early window shifting from -24ns to Ons, and late window shifting of Ons to 25ns, or Ons to +T/2. Thus by using one value of N for the early window shifting, and another value for late, the full range of ±window/2 may be achieved. Selection of N may be made by looking for the Optimum Center Frequency f(N) which is closest the data rate in Table 2. N may also be determined using the relationships listed after Table 2. ADVANCE INFORMATION 11-26-90 27-13 WD10C23 ARCHITECTURE (delay) 0 nsec 48ns 24ns 12.32 MHz 6.53 MHz ) ( fWSCLK ~ OATA / 24nsec ~ 24nsec + / / range for N=12 / / / \ \ / -.I / early window shift - 24nsec late window shift +24nsec / 72ns 4.44 MHz / '\ window2 window1 f DR = 10.4 MHz FIGURE 5. AWS OPTIMUM CEt20.0 MHz />20.0 MHz * Externally generated oscillator; XTALOUT open Power Supply Currents: Vcc SYMBOL CHARACTERISTIC leeA Ices MIN TYP MAX UNIT 5v active current 5v static cu rrent 25 6 35 10 rnA rnA CONDITIONS Vee = 5.25;· Vee = 5.25;·· * ICCA measured as follows : Highest current draw is at 15 MbiVsec during a write operation, with WSCLK programmed to 14 MHz and the VF pins programmed to one of the Adaptive Window Shift states. Idle currents will be several mamps lower. ** Iccs measured as follows: During the Reset Test Mode, pull XTALIN high after the required number of XTALIN clocks. Follow by grounding WGATE, RGATE, WPCEN; all other pins floating. Power Supply Voltage: Vce SYMBOL CHARACTERISTIC Power reset inactive Power reset active MIN TYP MAX UNIT 4.1 CONDITIONS V 2.6 V * At this level Vee level and above, the power-qualified reset is guaranteed to be inactive. ** At this level Vee level and below, the power-qualified reset is guaranteed to be active. ADVANCE INFORMATION 11-26-90 27-21 WD10C23 ELECTRICAL CHARACTERISTICS MOS Outputs:WCLK, RCLK, RDATA, DRUN SYMBOL CHARACTERISTIC MIN TYP MAX UNIT VOH VOL tRISE tFALL Output high volt Output low volt Rise time Fall time 2.4 0.4 7.0 4.0 V V nsec nsec CONDITIONS IOH=-201JA IOL=+201JA 0.8 to 2.0 V; • 2.0 to 0.8 V; • • Specified with a maximum external load of 20 pF; intended for high impedence MOS receivers, whose input threshold requirement is TLL compatible (Le. 2.010.8V VIHlVIL) TTL Outputs:WPCDATA SYMBOL CHARACTERISTIC VOH VOL tRISE tFALL Output high volt Output low volt Rise time Fall time MIN TYP MAX UNIT 2.4 0.4 7.0 4.0 V V nsec nsec CONDITIONS IOH=-4001JA IOL=+2.0mA 0.8 to 2.0 V; • 2.0 to 0.8 V; •• • Specified with 20 pF/20 kn load to Vss; intended for TLL receivers "Specified with 20 pF load to Vssl2 kQ load to Vee; intended for TLL receivers 27-22 ADVANCE INFORMATION 11-26-90 WD10C23 ELECTRICAL CHARACTERISTICS 6.4 Analog Signals (Crystal Oscillator) Input: XTALIN SYMBOL CHARACTERISTIC MIN TYP MAX UNIT ILlO( Input leakage currents Input bias volt -100 1.0 VIBIAS +100 1.8 nA V CONDITIONS VINNoUT=VIBIAS XTALOUT floating Leakage measured after the internal Power-On Reset has timed out. Output: XTALOUT SYMBOL IOLS 10HS RBO RBS CHARACTERISTIC MIN TYP MAX UNIT Short circuit sink current Short circuit source current Operating bias resistance Startup bias resistance 4.5 -1.6 1.1 8 18 rnA -9.4 rnA 5.6 Mohrn 70 Kohrn CONDITIONS Vcc:=+5; XTALlN=2.5V,XTALOUT=5V Vcc=+5; XTALlN,XTALOUT=0 *Measured after the internal Power Qualified Reset has timed out, RBO is the feedback resistance between XTALIN and XTALOUT. With Vcc=SV, XTALOUT RBO is modelled as a resistance combination with the measured leakage resistance, RLKX = VIBIAslILKX. With XTALlN=VIBIAS, XTALOUT = ILKX measured at the XTALIN input is given by VIBIAS(1/RBO + 1/RLKX) for leakage to GND, or by VIBIAS(1/RBO + 1/RLKX)-S/RLKX for leakage to Vcc. After measuring ILKX, RBO may be computed. **Measured during the internal Power Qualified Reset, Rss is the internal parallel resistor combination of RBO and an additional resistor activated during Power Qualified Reset. RBS is modelled as a parallel resistance to the measured leakage resistance RLKX = VIBIAslILKX. To ensure that PQR is active, the supply should be set at 2.SV. At this supply setting, measure VIBIAS. With XTALlN=VIBIAS, XTALOUT = and Vcc=2.SV, ILKX measured at the XTALIN input is given by VIBIAS(1/RBS + 1/RLKX) for leakage to GND, or by VIBIAS(1/RBS + 1/RLKX)-2.S/RLKX for leakage to Vcc. =av, av, av, ADVANCE INFORMATION 11-26-90 27-23 WD10C23 6.5 ELECTRICAL CHARACTERISTICS Phase-Locked Loop Filter Input/Output: PUMP, VCON SYMBOL iu(v ILKP ICLP VCAP VCDP ICLN VCLN Rpvc Rpvo RpV1 RpV2 RpV3 Rpvv CHARACTERISTIC VCON leakage current PUMP leakage current PUMP clamp current PUMP clamp act threshold PUMP clamp deact thrsh'd VCON clamp current VCON clamp threshold Pump-VCON comp res Pump-VCON BANDO res Pump-VCON BAND1 res Pump-VCON BAND2 res Pump-VCON BAND3 res Pump-VCON Vlock res MIN TYP MAX UNIT -100 4 2.7 .55 1.3 .5 2.2 4.0 2.3 531 100 nA 100 nA 15 rnA 3.9 V 1.15 V 4.5 rnA .95 V 3 5 Kohm ohm ohm 9.8 Kohm 6 3.5 5.6 Kohm 627 1381 ohm CONDITIONS* VCON=Vcc, PUMP =Vcc!GND, VCONlPUMP=Vcc, -IpUMP ~ 2.5 rnA, -IpUMP < 2.5 rnA, -VCON=GND, -IVCON = -1!lA, -- t t t t t :j: - High impedence is guaranteed by placing the device in the Reset Test Mode to open the PUMP to the VCON resistor, tristate the Charge Pump, and disable the PUMP clamp. Leakage on VCON is not measured to Vee, as there is a low voltage clamp on this pin. _. The PUMP clamp will activate, pulling PUMP low, when VCON rises above the PUMP clamp activation threshold voltage. The PUMP clamp is latched until VCON falls below the clamp deactivation threshold. The VCON clamp will activate, keeping VCON above ground, when VCON falls below the VCON clamp threshold. Both clamp currentslvoltages should be measured after tristating the Charge Pump by disabling the RAWDATA input in phase lock, and selecting BANDO or BAND1 to open the internal resistance betweeen PUMP and VCON. t Measured during phase lock, this is the internal filter resistance between PUMP and VCON. The measurement should be made in the correct band with PUMP =1.5 V and VCON = 2.0 V. :t: Measured during velocity lock, this is the internal filter resistance between PUMP and VCON. The measurement may be made in any band with PUMP = 1.5 V and VCON = 2.0V 27-24 ADVANCE INFORMATION 11-26-90 WD10C23 ELECTRICAL CHARACTERISTICS Filter Input/Output: LPF SYMBOL CHARACTERISTIC ILKL RLPC RLPO RLP1 RLP2 RLP3 Leakage current LPF-GND comp res LPF-GND BAN DO res LPF-GND BAND1 res LPF-GND BAND2 res LPF-GND BAND3 res MIN TYP MAX UNIT -10 10 1.5 300 75 ohm ohm 4.B Kohm 950 ohm 250 ohm 2.B 525 150 CONDITIONS IJA • Tristate on LPF is guaranteed by setting VFO/=OO or zz . •• This in the internal filter resistance between LPF and GND. The measurement should be made in the correct band with LPF=2.0 V. Charge Pump: PUMP SYMBOL IPLP IPLV IPHP IPHV RPB RKOVP RKOH1 CHARACTERISTIC MIN TYP MAX UNIT Comp/BANDO-2 pmp cur Comp/BANDO-2 pmp cur BAND3 pump current BAND3 pump current Pump cur symmetry ratio Vlock-Plock pmp gain ratio Hi-Io band pump gain ratio 40 BO BO 160 .95 1.9 1.9 200 400 400 BOO 1.05 2.1 2.1 IJA IJA IJA IJA CONDITIONS· phase lock velocity lock phase lock velocity lock lup:ldown Ko Vlock:Plock K03:Ko2 • Currents are for the measured VCON voltages found at the frequency extremes of the specified frequency bands2 and are specified as magnitudes. Pump current is related to VCON approximately by 1== (VCON - Vt) . P ADVANCE INFORMATION 11-26-90 27-25 .. WD10C23 ELECTRICAL CHARACTERISTICS VCO: VCON SYMBOL VCON KOM KOR Koo K01 K02 K03 KOLM KOLR KOLO KOL1 KOL2 KOL3 CHARACTERISTIC MIN TYP MAX UNIT VCO N-Channel control volt .9 Comp VCO gain 150 Comp VCO gain 150 BANDO VCO gain 150 BAND1 VCO gain 50 BAND2 VCO gain 50 BAND3 VCO gain 50 Comp open loop gain 15 Comp open loop gain 15 BANDO open loop gain 10 BAND1 open loop gain 10 BAND2 open loop gain 10 BAND3 open loop gain 30 2.4 450 450 500 450 450 450 45 45 45 50 50 79 CONDITIONS V %N %N %N %N %N %N %mAN %mAN %mAN %mAN %mAN %mAN 5Mbit MFM," . 7.5Mbit RLL, •• MFM,t RLL,t t t t t * This is the voltage developed by the filter and charge pump used to drive the internal VCO. The VCON voltage will be within this range for each of the four Ko settings in Table 1. ** The VCO frequency is proportional to the square of the voltage, VCON, on the VCON input. VCO gain is given by % (~f 1 fAVE) (1/~ VCON ), or 4000 (f2 - f1) 1(/2 + f1) where f2 and f1 are the frequencies at VCON ± 25mV respectively. The gains are specified for the VCON'S found at the frequency extremes of the frequency bands. (Le., at 5 and 7.5 MHz for BANDO). t The open loop gain is given_,as a product of Ko and the average Charge Pump current. Specifically, K01 = KolAVE = 2000 (f2 - f1) (12+11)1 (f2 + f1) where 12 and 11 are the Charge Pump currents found at the VCON voltages determine f2 and f1 , respectively. 27-26 ADVANCE INFORMATION 11-26-90 WD10C23 TIMING CHARACTERISTICS 7.0 TIMING CHARACTERISTICS The following timings have been, where applicable, expressed in terms of the data rate by T = 1/(2x NRZ data frequency), for data frequencies in the range of 5 to 15 MBitisec. Several timings are referenced using a phase relationship of input signals called NULL phases. These phases should be such that there is zero phase error at the Phase Detector and zero net charge transfer on the PUMP pin. When the PLL is acquiring data in velocity lock mode, for a given set of conditions there is one phase of RAWDATA with respect to VCOIN which results in zero net current on PUMP. This phase is called NULLV (denoted eV). 7.1 Disk Drive Raw Read Data SYMBOL CHARACTERISTIC tROH tRCL tROT tROT The equivalent phase relationship found when the PLL is tracking data in phase detection mode is called NULLP(denoted ep). When the PLL is tracking the crystal reference, the corresponding NULL, NULLX (denoted ex), refers to the equivalent phase between XTALIN and the VCO. All timings are measured with in~ut levels of 2.4V VIH and .4V VIL, Ta = 0 °c to 70 C; Vss = OV, Vee = 5 V + 0.25 V. Closed loop PLL timings will be guaranteed to within ±1 ns for power supply ripple of no more than 30m V peak to peak. Transition times are measured at the 2.0 V cross- _ ing for high going transitions, and at the O.B V . . crossing for low going. Any deviations from these criteria will be specified. MIN TYP MAX UNIT nsec nsec nsec nsec RAW DATA pulse width high 15 RAWDATA pulse width low 15 RAWDATA period T RAW DATA period 2T CONDITIONS MFM mode, * RLLmode, * * This timing is intended to indicate that two consecutive bit shifts, in a direction such that a minimum interval is created, can be tolerated up to just under T/2ns each without recycle failure in the phase or data detectors. , RDT - 'RD L I 'RDL RAWDATA FIGURE 7. DISK DRIVE RAW READ DATA TIMING ADVANCE INFORMATION 11-26-90 27-27 WD10C23 TIMING CHARACTERISTICS 7.2 Disk Drive Raw Read Data Frequency Detector SYMBOL CHARACTERISTIC MIN TYP MAX UNIT tORL tORH tOR DRUN low freq threshold 2.50T 2.62ST 2.7ST nsec DRUN high freq threshold 1.188T 1.313T 1.438T nsec DRUN threshold 4T 5T nsec CONDITIONS MFM mode,' MFM mode,' RLL mode," • DRUN is guaranteed to be high for RAWDATA frequencies greater than tORL but less that tORH. For frequencies less than tORL, DRUN will not remain high, and for those greater than tORH DRUN behavior is not specified. DRUN low pulse widths will always reflect the pulse periods on RAWDATA for those periods which cause DRUN to drop. Thus the minimum will typically be 2.625T nsec. ** DRUN minimum low pulse widths will be typically T nsec. 27-28 ADVANCE INFORMATION 11-26-90 WD10C23 TIMING CHARACTERISTICS 7.3 Read Data Conditioner SYMBOL CHARACTERISTIC tRDP tRCP tRCS tRCH CONDITIONS· MIN TYP MAX UNIT RDATA pulse width T nsec RCLK pulse width T nsec RDATA setup to RCLK T/2-6.6 T/2 T/2+6.6 nsec RDATA hold from RCLK T/2-6.6 T/2 T/2+6.6 nsec _~X RDATA t RCP- - - - + FIGURE 8. READ DATA CONDITIONER TIMING ADVANCE INFORMATION 11-26-90 27-29 WD10C23 TIMING CHARACTERISTICS 7.4 Read Data Detector (Percentage Window Shift) SYMBOL CHARACTERISTIC toow towc tOWSE1 tOWSL1 tOWSE2 tOWS12 MIN TYP MAX UNIT Data Detect Window T-1 DD Center Window xl2-1 DD Window Shift Early 1X -T/16-1 DD Window Shift Late 1X T/16-1 DD Window Shift Early 2X -T/S-1 DD Window Shift Late 2X T/S-1 T xl2 xl2+1 T/16 -T/16+1 T/16 T/16+1 TIS -T/8+1 TIS T/8+1 nsec nsec nsec nsec nsec nsec CONDITIONS x = Toow,' SHIFT2X=GND SHIFT2X=GND SHIFT2X=Vcc SHIFT2X=Vcc • Window centering, towc, is not a function of window loss and is thus correctly specified in terms of toow. 7.5 Read Data Detector (Adaptive Window Shift) SYMBOL CHARACTERISTIC tws AWS Accuracy MIN TYP MAX UNIT 5 CONDITIONS %/ans ** The accuracy is specified as the error in the gain (slope), 36/N, as given by equation 4 from Table 2. The tws error is determined by multiplying the difference in TWSCLK from 153.2 ns. For example, if the required TWSCLK is 160.2 ns, then the maximum tws error will be the 0.05x(160.2 -153.2)=350ps. If the required TWSCLK were 150.2 ns, the maximum error would be 0.05x(150.2-153.2)ns=-150ps. 27-30 ADVANCE INFORMATION 11-26-90 WD10C23 TIMING CHARACTERISTICS 7.6 Phase-Frequency Detector 7.6.1 Phase Lock Mode SYMBOL CHARACTERISTIC tPDW tpwc MIN TYP MAX UNIT Phase Detect Window Phase Centering Window xl2-1 T xl2 nsec xl2+1 nsec CONDITIONS X=TPDW, • • The phase detection window must be equal to T. Any apparent gain or loss in the window must be due to tester inaccuracy and/or statistical error in the measurement. Phase window centering is not a function of window size, and is thus correctly specified in terms of TpDW. 7.6.2 Velocity Lock Mode (MFM) SYMBOL CHARACTERISTIC tVDW tvWE tvWL Velocity Lock Detect Window Velocity Lock Early Window Velocity Lock Late Window 7.6.3 Velocity Lock Mode (RLL) SYMBOL CHARACTERISTIC tVDW tvwE tvwL MIN TYP MAX UNIT 4T nsec 2T 2T nsec nsec MIN TYP MAX UNIT Velocity Lock Detect Window Velocity Lock Early Window Velocity Lock Late Window 6T nsec 3T 3T nsec nsec ADVANCE INFORMATION 11-26-90 CONDITIONS CONDITIONS 27-31 • WD10C23 TIMING CHARACTERISTICS 1 tpwc---- //, PUMP CURRENT , / / , , , , , / / , / /1 / , / 0 / / , , / / , ~ / -I / t pwc ROR / , / V i , / , PHASE / / V NPV FIGURE 9. PHASE DETECTION TIMING • t vow - , vwe---+ ~ 'vw,,-----+ /1 pu"" currant V / //: 0 / / t / / t / , / , , / , / 1/ / :/ ~' • t VWE -----0 -G-v / / i :/ / / ~.- 2~R FIGURE 10. VELOCITY LOCK MODE 27-32 / + /: ! / / \ ~ / / ADVANCE INFORMATION 11-26-90 - PHASE ERROR WD10C23 TIMING CHARACTERISTICS 7.7 Write Data Conditioner SYMBOL CHARACTERISTIC twcs twCH tpCE1 tpCL1 tpCE2 tpCL2 tpcp tWPD WD setup to WCLK WD hold from WCLCK Early precomp 1X Late precomp 1X Early precomp 2X Late precomp 2X WPCDATA high WDATA to WPCDATA MIN TYP MAX UNIT 8 3 T/16-1 T/16 T/16+1 T/16-1 T/16 T/16+1 T/8-1 T/8 T/8+1 T/8-1 T/8 T/8+1 T-10 T .5T 2.75T+50 nsec nsec nsec nsec nsec nsec nsec nsec CONDITIONS ". SHIFT2X=GND ". SHIFT2X=GND ". SHIFT2X=VCC ". SHIFT2X=VCC •••• SHIFT2X=GND • Timings are for WDATA. EARLY. LATE. and SHIFT2X. ** Differential measurement of rising edge of precompensated WPCDATA versus non-precompensated WPCDATA. *** Measured for early and late precompensated WPCDATA. 7.8 TTL XTALIN Input Clock, WCLK Output SYMBOL CHARACTERISTIC MIN TYP MAX UNIT txs txp twCD Crystal startup XTALIN freq @TIL levels 45 WCLK duty cycle 2 20 55 msec MHz % CONDITIONS 40/60% Duty Cycle * WCLK duty cycle is specified for the high phase. at any voltage between 0.8-2.0 V. This guarantees the worst case duty cycle seen at the input of a receiver. whose input threshold is specified to be within this voltage range. See the Output Driver section of the DC Electrical Characteristics above for load limitations. ADVANCE INFORMATION 11-26-90 27-33 WD10C23 TIMING CHARACTERISTICS EARLY LATE ~ ~t ~ ~~[i-t-WOC----+-----------------tw~~~ t wcs WCH WCLK ~ WDATA ______________~ WPCDATA ~ _tpcp WPCDATA (EARLY 2X) t PCE2 r---------+--.. - PCEl WPCDATA_ _ _ _ _ _ _ _ _ _ _ _ _ _- J (NOMINAL) PCLl ---II> +--- WPCDATA -----------------r---J ~~~:~~ - ~= --1/ (LATE2X)--------------1- FIGURE 11. WRITE DATA CONDITIONER TIMINGS ADVANCE INFORMATION 11-26-90 PCP WD10C23 TIMING CHARACTERISTICS 7.9 Delay Line SYMBOL CHARACTERISTIC tDRC MIN TYP MAX UNIT Delay-Locked Loop Time Constant .4 1.5 CONDITIONS msec * This is the time required for the DOL to acquire the XTALIN frequency. It should be used in conjunction with txs to determine the time from power up to device ready. x T ~I---T-6. f R ~ ~ I I I I I I I L----~----==-==_=~~ o E L A y I I I I ;rI I I V L I 0.636. delay I lORe ----+1.1 TIME FIGURE 12. DELAY LINE TIMING ADVANCE INFORMATION 11-26-90 27-35 WD10C23 TIMING CHARACTERISTICS repeated for each sector ................ : index ______ -J~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~_._ _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ sector ---------~------------------------------------~~--------- WG =r----~--~~t during format WG -+. tFWGOFF-+ :.FWGON .- ~~--------------- ~____~______~______~~ during write :- tWGON : --+. RG ----~----~/. tGOFF1: ~tWGOFF2: ---II- tRGON1 : +-- ----+: :'--t :-+: .. - RGON2-+ GAP1 '" ~--~---------- +-- WS+ID PLO ~n''''"i'+V'.11 x+9 ,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ IDENTDefinition: NOTES: 1. n=contents of Sector Number Register during Format command. 2. CL=controlier latency. OSCl.!;;1 byte times. 3. x=contents of PLO register. ID PLO Length is erogrammable during Format command. DATA PLO Length is programmable during Wnte command. Data PLO Length is 11 during Format Data PLO Length is 12±1 during write if x=O. 4. twooN=17±1 bit times with respect to RD in. 5. two0FF1=28 bit times with respect to WD out 6. IRGOFF1=9±1 bit times wtth respect to RD in. 7. IRGOFF2=9±1 bit times wtth respect to RD in. . 8. lRooNl=Z+CL byte times with respect to INDEX/SECTOR (SCT). Sector is tied to DRUNSCT always. z=contents of internal GAP register. 9. IRGON2=35±1 bit times with respect to RD in. 10. GAP2= speed tolerance + comined ENDEC delays + other GAP requirements (I.e. SERVO) GAP2 Length= (time between sector pulses) - (time from start of GAP1IGAP3 to end of data pad) 11. lFwooN=n+S112+CL byte times with respect to INDEX/SECTOR. n=contents of Sector Number Register during Format twGOFf"20 bit times with respect to WD out FIGURE 13. HARD SECTOR FORMAT w/WG PULSE OPTION 27-36 ADVANCE INFORMATION 11-26-90 WD10C23 TIMING CHARACTERISTICS repeated for each sector· index________ ~~~__________________________________________·---------------------- sector---------7------------------------------------------~~,------------~~----------------- DRUN~------~~~ WG ~----~:~~--------------~--------------~-------------~. tFWGOFF--+ during format WG=-____~--~--~------~~ t • t : ,WGOFFl --+ , during write WGON -----.; RG _ _ _ _~_ _ _~/ tGOFF1: ---+: t RGON1 . +-- ~ ~~---------------'4-- ~ ~tWGOFF2· ~~--~------------+-t '+- 42C22A , 10 FORMAT , PAD : 2 # Bytes :4-- :--+: RGON2-+ 4-- x+14:!-1 t'---_______________________________________ IDENT Definftion: NOTES: 1. n=conten1s of Sector Number Register during Format command. 2. CL=controlier latency. O:S;C~l byte times. 3. x=conten1s of PLO register. ID PLO Length is programmable during Format command. DATA PLO Length is programmable during Wr~e command. Data PLO Length is 11 during Fonnat Data PLO Length is 12±1 during write if x=O. 4. !waoN= 17±1 bit times with respect to RD in. 5. lwaoFF1=28 bit times with respect to WD out. 6. IRGOFF1=9±1 bit times with respect to RD in. 7.tRooFF2=9±1 bit times with respect to RD in. 8. IRGON1=19±1 bit times with respect to DRUN. SECTOR is tied to DRUNSCT during Format and DRUN is tied to DRUNSCT during Read and Write. 9. lRaoN2=35±1 bit times with respect to RD in. 10. GAP2= speed tolerance ... comined EN DEC delays ... other GAP requirements (I.e. SERVO) GAP2 Length= (time between sector pulses) - (time from start of GAP1/GAP3 to end of data pad) FIGURE 14. HARD SECTOR FORMAT wi SOFT SECTOR RIW ADVANCE INFORMATION 11-26-90 27-37 WD10C23 8.0 PRODUCT COMPA TlBIL/TY PRODUCT COMPATIBILITY The following is a matrix of the features for each of the data separators from Western Digital's family of devices. Market Number CMOS WD10C 20A WD10C WD10C WD10C 21A 20B 22B 3f..lSM 3f..lSM 14 3f..lSM 14 3 ..J min ext componts 15 3f..lSM 15 ext delay line ..J ..J ..J ..J , int delay line extVCO ..J ..J ..J ..J ..J ..J ..J ..J ..J ...J ...J ...J ..J ..J ..J ..J RLL encoding 5 Mbit ..J ..J 7.5 Mbit ..J ..J ..J 10 Mbit 15 Mbit ...J var frequency soft sector 1.25 f..lDM ..J int VCO MFM encoding WD10C 23 ..J ..J ..J ..J ...J write precomp ext dly ext dly window shift ext dly ext dly ± 12.5 % ± 12.5 % ± 12.5 % ± 12.5 % hard sector ...J ..J * ** adapt win centering ..J TABLE 4. PRODUCT COMPATIBILITY FOR DATA SEPARATORS ± 12.5 % I ± 6.25 % ** ± WIN/2 * 27-38 ADVANCE INFORMATION 11-26-90
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