30240 90002 HP 30240A Thin LAN 3000 V Link Local Area Network Interface Controller (LANIC) Installation And Service Manual Ja

30240-90002_HP_30240A_ThinLAN_3000_V_Link_Local_Area_Network_Interface_Controller_(LANIC)_Installation_and_Service_Manual_Jan1988 30240-90002_HP_30240A_ThinLAN_3000_V_Link_Local_Area_Network_Interface_Controller_(LANIC)_Installation_and_Service_Manual_Jan198

User Manual: manual pdf -FilePursuit

Open the PDF directly: View PDF .
Page Count: 85

Download
Open PDF In Browser	View PDF

HP 3000 Computer Systems

HP 30240A
ThinLAN 3000/V Link
Local Area Network Interface Controller

(LANle)
Installation and Service Manual

Fli;'

HEWLETT

a:'~ PACKARD

HEWLETT-PACKARD COMPANY
Roseville Networks Division
8000 Foothills Boulevard
Roseville, California 95678

Manual Part Number 30240-90002
E0188
Printed in U.S.A.
January 1988

Notice
The information contained in this document is subject to change without notice.
HEWLETT-PACKARD COMPANY MAKES NO WARRANTY OF ANY KIND WITH REGARD TO
THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Hewlett-Packard shall not be
liable for errors contained herein or for incidental or consequential damages in connection with the furnishing, performance or use of this material.
Hewlett-Packard assumes no responsibility for the use or reliability of its software on equipment that is not
furnished by Hewlett-Packard.
This document contains proprietary information. which is protected by copyright. All rights are reserved.
No part of this document may be photocopied. reproduced or translated to another language without the
prior written consent of Hewlett-Packard Company.
Copyright@ 1988 by HEWLETI-PACKARD COMPANY

Reader Comment Sheet
Information Networks Group
ThinLAN 3000/V Link LANIC
30242-90002

January 1988

We welcome your evaluation of this manual. Your comments and suggestions help us to improve our
publications. Please explain your answers under Comments. below. and use additional pages if necessary.
Is this manual technically accurate?

Yes

Are the concepts and wording easy to understand?

Yes

Is the format of this manual convenient in size. arrangement. and readability?

Yes

Comments:

This form requires no postage stamp if mailed in the U.S. For locations outside the U.S.. your local company representative will ensure that your comments are forwarded.

FROM:
Name
Company
Address

Date

-----------

FOLD

111111

NO POSTAGE
NECESSARY
IF MAILED
IN THE
UNITED STATES

BUSINESS REPLY MAIL
FIRST CLASS PERMIT NO. 256 ROSEVILLE, CALIFORNIA
POSTAGE WILL BE PAID BY ADDRESSEE
PUblications Manager

HEWLETr-PACKARD COMPANY
Roseville Networks Division
8000 Foothills Boulevard
Roseville, California 95678-6598

FOLD

Printing History
New editions are complete revisions of the manual. Update packages, which are issued between editions,
contain additional and replacement pages to be merged into the manual by the customer. The dates on the
title page change only when a new edition or a new update is published. No information is incorporated
into a reprinting unless it appears as a prior update; the edition does not change when an update is
incorporated.
A software code may be printed before the date; this indicates the version level of the software product at
the time the manual or update was issued. Many product updates and fixes do not require manual changes
and, conversely, manual corrections may be done without accompanying product changes. Therefore, do
not expect a one-to-one correspondence between product updates and manual updates.
First Edition

January 1988

Safety Considerations
GENERAL - This product and related documentation must be reviewed for familiarization with
safety markings and instructions before operation.

damage to or destruction of part or all
of the product. Do not proceed beyond
a CAUTION sign until the indicated
conditions are fully understood and met.

SAFETY SYMBOLS
Instruction manual symbol: the product
will be marked with this symbol when it
is necessary for the user to refer to the
instruction manual in order to protect
the product against damage.

..1_
-

Indicates hazardous voltages.

Indicates earth (ground) terminal (sometimes used in manual to indicate circuit
common connected to ground chassis).

WARNING

The WARNING sign denotes a hazard.
It calls attention to a procedure or practice that, if not correctly performed or
adhered to, could result in personal inDo not proceed beyond a
jury.
WARNING sign until the indicated
conditions are fully understood and met.

I CAUTION I
The CAUTION sign denotes a hazard.
It calls attention to an operating procedure or practice that. if not correctly
performed or adhered to, could result in

I CAUTION I
STATIC SENSITIVE DEVICES
When any two materials make contact,
their surfaces are crushed on the atomic
level and electrons pass back and forth
between the objects. On separation. one
surface comes away with excess
electrons (negatively charged) while the
other is electron deficient (positively
charged). The level of charge that is
developed depends on the type of
material. Insulators can easily build up
charges in excess of 20.000 volts. A person working at a bench or walking
across a floor can build up a charge of
many thousands of volts. The amount
of static voltage developed depends on
the rate of generation of the charge and
the capacitance of the body holding the
charge. If the discharge ha ppens to go
through a semiconductor device and the
transient current pulse is not effectively
diverted by protection circuitry, the
resulting current flow through the
device can raise the temperature of internal junctions to their melting points.
MOS structures are also susceptible to
dielectric damage due to high fields.

Safety Considerations (continued)

The resulting damage can range lrom
complete destruction to latent degradation.
Small geometry semiconductor
devices are especially susceptible to
damage by static discharge.
The LANIC card is shipped in a
transparent static shielding bag. The
card should be kept in this bag at all
times until it is installed in the system.
Save this bag for storing or transporting
the card. When installing the card in
the system, do not touch any components. Hold the card by its edges.
WARNING

SAFETY EARTH GROUND - The
computer in which this product is installed is a safety class I product and Is
provided with a protective earthing terminal. An uninterruptible safety ground
must be provided from the main source
to the product input wiring terminals,
power cord, or supplied power cord set.
Whenever it is likely that the protection
has been impaired, or. before the power
cord is removed from the wall receptacle,
the interface cable connector must be
removed from the computer system and
insulated from exposed conductive
surfaces.

(such as lightning or disturbances in the
electrical utilities power grid) In the area
surrounding the network to which this
product is connected. These surfaces
should be handled with caution,
especially when the interface cables are
not connected to a properly grounded
computer system.
SERVICING .
WARNING

Any servicing, adjustment, maintenance,
or repair of assemblies or subassemblies
of the computer system must be performed only by qualified personnel.
WARNING

This product is not designed for attachment to a network serving an area which
contains multiple unconnected power system safety grounds. Before installing
this product, verify that all of the power
system safety grounds are securely interconnected in the area served by the local
network.
Special caution should be
taken for cable systems run between
buildings or exposed to weather
environments.

WARNING
WARNING

At infrequent intervals, exposed metal
surfaces of the interface cables may be
subject to transient hazardous voltages
due to strong electrical disturbances

Do not connect this .product to an ungrounded "thick" network coaxial cable
as defined by this manual.

Preface
This manual provides installation and servicing information for the HP 30240A
ThinLAN 3000/V Link Local Area Network Interface Controller (LANIC) card.
This manual is organized as follows:
Chapter 1

General Information

Chapter 2

Installation

Chapter 3

Principles of Operation

Chapter 4

Maintenance

Appendix A

Configuration Information

Related documents include the following manuals:
LAN Cable and Accessories Installation Manual, part number 5959-7680
LA N 3000 Diagnostic and Trouhleshooting Guide, part number 30242-90003
H P 3000 System Operation and Resource M anagemenr Reference Manual, part
number 32033-90005

Contents

Chapte r 1
General Information

Page

I-I

Introdu ction
General Description
Equipment Supplied
System Interfa ce
Link Address
Specifications
Standa rd Specifications
Option 242 Specifications
LANIC Specifications

I-I
1-1
1-3
1-4
1-5
1-6
1-6
1-8
1-10

Chapte r 2
Installation

Page
2-1

Introdu ction
Curren t Requirements
Channel Address Switch
Cables
Standa rd Cables
Option 242 Cable
Installing the LANIC
Start Up and Verification
Reshipment

2-1
2-1
2-2
2-3
2-3
2-4
2-5
2-8
2-9

Chapte r 3
Principles of Operation
Introdu ction
Functional Description
LAN Interfa ce Contro ller (LANIC)
Host to LANIC Comm unicati on
LANIC MPU and Firmw are
Local Communications Controller
Direct Memory Access
"
Firmw are Downl oad and Configuration
Firmw are Downl oad
Setting Station Address
Queue Initialization
Transmit Operation

Page
3-1

3-1
3-1
3-1
3-2
3-3
3-3
3-3
3-4
3-4
3-4
3-4
3-5

Contents (continued)

Types of Packets Transmitted
Transmit Buffer Management
Queuing of Transmit Buffers
Transmit Operation Example
Receive Operation
Types of Packets Received
Receive Buffer Managaement
Queuing of Received Packets
Receiver Blind Spots
Receive Operation Example
Error Management
Selftest Operation
System Interrupt
SINTRO Selftest Interrupt
SINTRl LANIC Interrupt
Interactive Command Completion
Interactive Command Acknowledgment
Batch Command Completion
Fatal Error Response
LANIC Resets
Power-On Reset
'Hard Reset.
Soft Reset
Z-80 Reset
Power-Fail Warn
Self Test
Manually Initiated Self Test
Remotely Initiated Self Test
Idle Self Test
Visual Indicators
Attachment Unit Interface (AUI) Circuitry
MAU Power Control Circuit
LEOs
DO LED Pair
CL LED Pair
CR LED Pair
H Through Nand * LEOs
TX, RX, MN. OL, RO. Q. and IT LEOs
Medium Attachment Unit
Receiver
Transmitter
Jabber Fault Detection
Collision Detection

3-5
3-5
3-5
3-5
3-6
3-6
3-6
3-6
3-6
3-7
3-8
3-8
3-8
3-9
3-9
3-9
3-10
3-10
3-10
3-11
3-11
3-11
3-12
3-12
3-12
3-13
3-13
3-13
3-13
3-13
3-14
3-15
3-15
3-19
3-19
3-19
3-20
3-20
3-22
3-22
3-22
3-22
3-23

Contents (continued)

Chapte r 4
Mainte nance
Introdu ction
Repair Philosophy
Self Test

Appendix A
Configuration Information
Introdu ction
Config uration Dialog

Index

Page
4-1
4-1
4-1
4-2

Page
A-I
A-I
A-I

Page
Index- l

Figures and Tables
Figure
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 4-1.

Page
Typical Local Network (LAN)
HP 3000 Series 39-58 System Architecture
HP 3000 Series 68 and 70 System Architectre
LANIC Switch and LED Locations
LANIC Cable Diagram
ThinMAU AUI Cable Diagram
ThickMAU AUI Cable Diagram
LANIC Functional Block Diagram
AUI Interface Diagram
LANIC LEOs
MAU Functional Block Diagram
LANIC Switch and LED Locations

Table
Table 1-1.
Table 1-2.
Table 1-3.
Table 3-1.
Table 4-1.
Table 4-2.

1-2
1-4
1-5
2-2
2-3
2-3
2-4
3-2
3-14
3-16
3-23
.4-4

Page
ThinLAN Specifications
ThickLAN Specifications
LANIC Specifications
LANIC Resets·and Their Effects
Selftest LEOs and Subtest Descriptions
Reporting of Unexpected Results from Self Test

1-6
1-8
.1-10
3-11
.4-5
.4-8

General Information

Introduction
This manual presents installation and service instructions for the HP
30240A
ThinLA N 3000/V Link Local Area Netwo rk Interfa ce Controller.
This chapte r
has general inform ation abollt the HP 30240A ThinLA N 3000/V Link
produc t.
and includes a description and specifications.

General Description
The HP 30240A ThinLA N 3000/V link is an implem entatio n of the
IEEE 802.2
and IEEE 802.3 Local Area Netwo rk (LAN) standa rds and is used in
HP 3000
compu ter systems. The HP 30240A allows the HP 3000 to commu nicate
with
other HP 3000's over an IEEE 802.3. Type IOBASE2 Local Area Netwo
rk (LAN).
The IEEE 802.3 Local Area Networks (LANs) consist of three major
elements: a
coaxial cable transmission medium. units to access this medium (Mediu
m
Attach ment Units, MAUs). and controllers. For the HP 30240A. the
contro ller is
the Local Area Network Interfa ce Contro ller (LANIC).
The HP 30240A ThinLA N 3000/V link is available for use with the
HP 3000
Series 42 and 52; and the HP 3000 Series 48. 58. 68. and 70. Except
for the Series
37. the LANIC and MAU are the same for all other HP 3000 Series~
howev er.
two differe nt LANIC cables are offered (see the paragr aph "Equip
ment
Supplied").
The ThinLA N 3000/V link functions as an intelligent Direct Memo
ry Access
(DMA) channel which communicates with the host system via the
system I/O
backplane. Local intelligent contro l is provided by a microp rocesso
r and
firmwa re on the LAN Interfa ce Contro ller (LANIC). An 8-bit 2-80B
microprocessor (MPU) on the LANIC handles all the LAN/3000-to
-host
commu nicatio n and performs many link-level operat ions indepe ndently
of the
host. An 82586 Local Communications Contro ller (LCC) on the LANIC
perform s high-speed serial operations. packet address checking. networ
k
conten tion control. packet formatting, and Cyclic Redun dancy Check
(CRC)
generation and checking. The LCC is contro lled by the 2-80B throug
h local
(card-resident) memory.

Genera l Inform ation
1-1

A fitting called a BNC "T" for the ThinMAU or a lap for the ThickMAU,
pierces the coaxial cable and provides a connection from the cable to the
Medium Attachment Unit (MAU). An Attachment Unit Interface (AUI) cable
connects the MAU to the LAN Interface Controller (LANIC). The LANIC,
besides controlling the other LAN elements, also is the interface with the Local
Area Network to the computer system. A typical Local Area Network is shown
in Figure 1-1.

HP 3000

r - - - - - - f LANlC

AUI CAElLE

AUI CABLE

COAXIAL CABLE

50-OHM
TERMINATOR

COAXIAL CABLE

AUI CABLE

'------Il»IIC

HP 3000

L . . - - - - - t LANIC

HP JOOO

Figure 1-1. Typical Local Area Network (LAN)

General Information
1-2

Equipment Supplied
Standard equipment supplied with the HP 30240A is listed below:
Standard Equipment
1
Thin Medium Attachment Unit Assembly .........•.......... 28641 ~60004
1
BNC "T" Connector
1250-0781
1252-1650
1 BNC "T" Connector Cover
5955-2252
1 BNC "T" Connector Cover Instruction Sheet
1 ThinMAU Installation Manual
28641-90001
Option 242 - ThickMAU Option
Delete:
BNC "T" Connector
BNC liT" Connector Cover
Connector Cover Instruction Sheet
Thin Medium Attachment Unit Assembly
ThinMAU Instruction Manual
Add:
Coaxial Tap
MAU
6-metre AUI Cable

1250~0781

1252-1650
5959-2252
28641-60004
28641-90001
0362-0819
30241-60102
92254A

In addition: one of the following options (depending on the HP 3000 type) adds
the following equipment:
Option 300 for the HP 3000 Series 42 and 52
1 Series 4X/6X LAN Interface Controller (LANIC card)
1 Series 42/52 LANIC Internal Cable
I
ThinLAN 3000/V Link Installation and Service Manual

30242-60001
30241-60002
30240-90002

Option 400 for the HP 3000 Series 48 and 58
I Series 4X/6X LAN Interface Controller (LANIC card)
I Series 48/58 LANIC Internal Cable
1 ThinLAN 3000/V Link Installation and Service Manual

30242-6000 I
30241-60003
30240-90002

Option 500 for the HP 3000 Series 68 and 70
1 Series 4X/6X LAN Interface Controller (LANIC card)
1 Series 68, and 70 LANIC Internal Cable
I
ThinLAN 3000/V Link Installation and Service Manual

30242-60001
30241-60003
30240-90002

General Information
1-3

System Interface
As noted previously. the ThinLAN 3000/V link interfaces to the host computer
system through the LAN Interface Controller (LANIC). The LANIC functions
as an I/O channel and fits into the backplane of HP 3000 Series 42. 44. 48. 58. 68.
and 70 computers.
Figure 1-2 shows how the LANIC connects to a Series 42. 48. 52. or 58 computer
system. The CPU, Memory, Asynchronous Data Communications Controller
(ADCC) or Advanced Terminal Processor (ATP). General Input/Output
Controller (GIC), Intelligent Network Processor (INP). and LANIC all physically
fit into the backplane (the backplane is called the Intermodule Bus (1MB».

Figure 1-2. HP 3000 Series 39 through 58 System Architecture

General Information
1-4

The architecture for the Series 68 and 70 computers is significantly different
than the other HP 3000 series. as shown in Figure 1-3. The CPU and memory fit
into the Central System Bus (CSB), and one or more IMBs connect to the csa via
Common Bus Interfaces (CBls) and 1MB Interfaces (lMBls). I/O DMA
operations do not go directly to memory, but are handled by the IMBI.

AUt

CENTRAL SYSTEM BUS

Figure 1-3. HP 3000 Series 68 and 70 System Architecture

Link Address
The last six hexadecimal digits of the link level address for the LANIC are
indicated on the board stiffener to the left of the channel address switch (CHAN
ADDR) on a label titled "Station Address". The full address is 08 00 09 XX XX
XX. where XX XX XX represents the value on the label.

General Information
1-5

Specifications
Standard Specifications
Table 1-1. ThinLAN Specifications

Features
Compatible with IEEE 802.3 Standard for access to Type 10BASE2 coaxial cable.
Carrier-Sense Multiple Access with Collision Detection (CSMA/CD) protocol controls network
access using no master node.
On-board node self test that checks the operation of the node hardware including the ThinMAU.
Every node on the network cable is accessible by any other node on the network with ,no store
and forward.
10 Megabit-per-second hardware date transfer rate.
Each I8S-metre cable segment supports up to 30 nodes.
YSLI implementation for reliability and lower cost.
Microprocessor off-loads host computer and gather network statistics.

Electrical Characteristics
Data Rate: Transmitted in bursts of 10 Mbits/sec.
Maximum Coaxial Cable Length:

185 metres for one segment.

Maximum Distance from Node to Network Trunk: One metre maximum for external AUI cable.
Required Distance Between T's on Coaxial Cable Trunk:
coaxial cable at least 0.5 metre apart.

ThinMAU at AUI Connector
AUI signaling conforms to IEEE 802.3.
CO terminated but unused.
Operating voltage; 8.0Y to I3.S0Y at 400mA maximum.

General Information
1-6

Each ThinMAU must be located on the

Table 1-1. ThinLAN Specifications (Continued)

ThinMAU at Coaxial Cable
Coax signaling compatible with IEEE 802.3 recommended signaling levels.
Receiver based collision detection.
Compatible with any coaxial cable meeting IEEE 802.3 type 10. base 2 physical specifications.

ThinMAU Physical Characteristics
Size:

152 mm long by 114 mm wide by 25 mm thick (6.00 by 4.50 by 1.00 inches).

Weight: 0.90 kg (2.0 lbs).

ThinMAU Power Requirements
8.0 to 13.50 volts
0.400 ampere maximum

Environmental Specifications
Complete environmental specifications are in the LAN Cable and Accessories Installation Manual
(part number 5955-7680).

General Information
1-7

Option 242 Specifications
Table 1-2. ThickLAN Specifications

Features
Compatible with IEEE 802.3 Standard for access to O.4-inch diameter baseband coaxial cable.
Carrier-Sense Multiple Access with Collision Detection (CSMA/CD) protocol controls network
access using no master node.
On-board node self test that checks the operation of the node hardware including the AUI and
ThickMAU.
Every node on the network cable is accessible by any other node on the network with no store
forward.
10 Megabit-per-second hardware data transfer rate.
Each SOO-metre cable segment supports up to 100 nodes.
VLSI implementation for reliability and lower cost.
Microprocessor off-loads host computer and gathers network statistics.

Electrical Characteristics
Date Rate: Transmitted in bursts of 10 Mbits/sec.
Maximum Coaxial Cable Length: 500 metres for one segment.
Maximum Distance from Node to Network Trunk: 48-metres maximum for external AUI cable.
Required Distance Between Taps on coaxial Cable Trunk: Each ThickMAU with its cable tap
must be located on the coaxial at a position that is an exact multiple of 2.5 metres from the end
of the cable. The coaxial cable available from HP is marked every 2.5 metres to show where
ThickMAUs may connect.

ThickMAU Coaxial Cable to AUI Cable Isolation
+/-707V DC. SOOV AC RMS. 50/60 Hz
Will conduct repetitive surges of up to 4A without damage (between the shields).

General Information

1-8

Table 1-2. ThickLAN Specifications (Continued)

ThickMAU at AUI Connector
AVI signaling conforms to IEEE 802.3.
CO terminated but unused.
Jabber is reset 500 millisecond after Jabber Fault is removed

ThickMAU at Coaxial Cable
Coax signaling compatible with IEEE 802.3 recommended signaling levels.
Receiver based collision detection.
Will tap any .04-inch coaxial ca ble meeting IEEE 802.3 physical specifications.

ThickMAU Physical Characteristics
Size: 320 mm long by 95 mm wide by 30 mm thick (12.25 by 3.75 by 1.25 inches).
Weight: 0.55 kg (1.2 Ibs).

ThickMAU Power Requirements
9.5 to 15.75 volts.
0.4 amp maximum

Environmental Specifications
Complete environmental specifications are in the LAN Cable and Accessories Installation Manual
(part number 5955-7680).

General Information
1-9

LANIC Specifications
Table 1-3. LANIC Specifications

LANIC at AUI Connector
A VI signaling conforms to IEEE 802.3.

CO not driven.
VP +12V +/-6% @ O.5A; overcurrent protected @ 1.2A maximum.

Interframe spacing = 9.6 usec minimum.

LANIC Physical Characteristics
Size: 331 mm long by 28.5 mm wide by 22.5 mm thick (13.04 by 1l.2 by 0.89 inches).
Weight:

739 grams (26 ounces).

LANIC Power Requirements
Voltage
+5V +/-O.5V
+12V +/-0.6V

General Information
1-10

Current
4.7A
0.5A

Power Dissipation
23.5W
6.0W (either MAU attached)

Installation

Introduction
This chapter contains information on installing and verifying proper operation
of the LANIC card. part number 30242-60001. Information on installing the
MAD is in the LAN Cable and Accessories Installation Manllal, part number
5955-7680.

I CAUTION I
Some of the components used in this product are susceptible to damage by static
discharge. Refer to the Safety Considerations information at the front of this
manual before handling the card.

Current Requirements
The LANIC circuit card obtains its operating voltages from the host computer.
The current requirements of the card are listed in the power requirements entry
of Table 1-3.
All HP 3000 Computer systems can supply adequate current to accommodate the
LANIC card without the need for any power supply modification. However, it
is possible that the + 12V supply in the HP 3000 system may be set to a low
voltage such that the VP lead on the AUI cable may not provide the minimum
voltage specified by IEEE 802.3 (+11.28V). If MAD replacement does not correct
an apparent MAD problem. the VP voltage should be checked. This is done by
connecting an accurate voltmeter between the +12 and GND test points near the
LEOs on the LANIC card. This must be done when the MAU is connected to
the LANIC and MAD power is on (as indicated by the VP LED). MAU power
can be turned on by executing the LANIC self test. Consult the appropriate
HP 3000 CE handbook for instructions on adjusting the +12V power on the
particular system involved.

Installation
2-1

Channel Address Switch
For the LANIC card, the channel address is set by a CHAN ADDR rotary
switch. SW2. located on the front edge of the card. See Figure 2-1 for the
location of SW2. SW2 can be set to any value between I and 15. however.
ensure that no Gles. ADCCs. or SIBs are set to the same channel number. \Vhile
it is physically possible to set the address switch to values 1 to 15. yOll should
exercise some caution in your choice of channel number. For instance. in all HP
machines. it is assumed that the console has a DRT of 8. Therefore, choosing to
make the LANIC channel address of I in a 4X. 5X, or in the first 1MB of a
6X/7X machine will cause problems. Once you have set SW2 to a value. jot the
value down. The formula used to calculate the DRT number from the hardware
address is: (lMB# x 128) + (channel# x 8) + device #.

• OCOI'OMI.lIlI,l.II.

tL.d..L8j ..8...lzs II iti o. ~
010 010 010 010 0 0 0 0 0 00

LANICTEST

(RESET)

[j!!]

Figure 2-1. LANIC Switch and LED Locations

Installation
2-2

Cables
Standard Cables
Two cables are llsed to connec t the LANIC to the MAU: an interna
l LANIC
cable and the AUI cable. The LANIC cable has a hood connec tor
on one end
and a female IS-pin 0 connec tor on the other. A cabling diagram
for the
LANIC cable is shown in Figure 2-2.

P2
JO-PlN HOOD CONNECTOR

PI
IS-PIN 0 CONN£CTOR

RED

WHlrE

C1-A 0RAH0f:
Ct-B YEU..OW

\'C

~rAOE

COMMON) BlACK -.;-;..0.....
01-11. BROWN
01-8 WHITE

CR£EN
YELLOW

'lIP (VOl.TACE PLUS)

R£O
00-11. SLUE
00-8 GREEN

Figure 2-2. LANIC Cable Diagram

For the ThinM AU the AUI cable uses a male IS-pin D connec tor on
one end
and the other end is wired directly into the ThinMAU. See Figure
2-3 for the
cabling diagram.

P2
IS-PIN 0 CONNECTOR
(MALE)

VP (VOl.TAGE PLUS) REO

OI-B WHITE
00-8 OR£EN
O-S YELLOW

(VOUACE COIAtON) ~
01-11. BROWN
DRAIN W1R£ (1N1'£RNAL SHI£U)

00-11. ewE
CI-A ORANGE

0I0'ERAU. 8RAIO SHlELO
(CONNECTED »tROUGH METAWzm SHEU.)

Figure 2-3. ThinM AU AUI Cable Diagram

Install ation
2-3

Option 242 Cable
For the ThickMAU the AUI cable uses a male i5-pin D connector on one end
and a female I5-pin D connector on the other. See Figure 2-4 for this cabling
diagram.

,,-PlN 0 CONNECTOR

"-PIN 0 CONNECTOR

(F'EMALE)

(MALE)

REO
WHITE
GREEN
YEu.ow

VP (VOI.TAOE Pl"U$) Rf:D
01-8 WHITE
DO-8 OMEN
0-8 YELLOW

VC (VOI.TACE COYotON) BlACK
01-04' 8ROWN
ORNN WIRE (..1'EANAL SHIEI.O)
DO-A BLUE
CI-A ORIHOE

OVERAlL BRAID SHlEl.O
(CONNECTED THROUGH METAWUD SHELL)

Figure 2-4. ThickMAU AUI Cable Diagram

Installation
2-4

Installing the LANIC

I CAUTION I
Some of the Compo nents lIsed in this produc t are susceptible to damag
e by static
discharge. Refer to the Safety Considerations inform ation at the front
of this
manual before handling the card.

Install the LANIC as follows:

I CAUTION I
All system power must be off when installing or removing any device
or card in
the system.

1. Before installing the LANIC, perfor m a full HP 3000 backup.
2. Shut down MPE.
3.

Ensure that SW2 is set to the intended channe l address. (It may be
llseful to
obtain an IOMA P of all devices presently on the system. Refer to
the
H P 3000 System Operation and Resource M anagemenl Relerence Manua
l,
part numbe r 32033-90005 for details.)

Turn off all system power.

Open the door of the I/O section card cage on the back of the HP
3000
Compu ter system.

Insert the LANIC card into a vacant card cage slot as follows:
The LANIC is considered to be a high-speed channe l and, mllst be
config ured so that its priority is higher than any GIC. Priorit y is
established by the position of I/O cards in the card cage; the closer
to the
CPU (or the IMBI in the case of the Series 68 and 70), the higher the
priority.
Series 42 and 52. The LANIC can be installed in any slot in the range
of
13 throug h 25. The adding of the LANIC card may require the movem
ent
of cards in the card cage to give the LANIC the required relative priority
.

Installa tion
2-5

Slots 13 and 14 are unique in the Series 42 and 52 in that they are
interdependent upon slot 15 in some situations. Specifically, if either a
GIC. SIB. or LANIC occupies slot 13 and/or 14, and if slots 16 through 25
have one or more GICs, SIBs. or LANICs, then a GIC. SIB, or LANIC
MUST be in slot 15.
Note that the card in slot 15 need not be identical to the others under
consideration. For instance, if a LANIC is in slot 13, and a GIC or SIB is
in 16 through 25, then any may be installed in 15.
If ADCCs are installed in 13 and 14, as is commonly the case, then put the
LANIC is slot 15.
Series 48 and 58. The LANIC can be installed in any slot in the range of
14 through 24 (card cage 1) and any slot in the range of 1 through 7 (card
cage 2). The adding of the LANIC card may require the movement of
cards in the card cage(s) to give the LANIC the required relative priority.
Series 68 and 70. The LANIC must be installed in the I/O portion of the
card cage. The adding of the LANIC card may require the movement of
cards in the card cage to give the LANIC the required relative priority.
Special considerations apply to the placement of GICs, SIBs, and LANICs
in Series 68 and 70 systems:
Between a GIC, SIB, or LANIC, and the next GIC, SIB, or LANIC, there
may be a maximum of nine slots.
The "next" card need not be identical to its neighbor as long as it is one of
the three types (GIC, SIB, or LANIC)
As an example. an SIB in slot 10 with a LANIC in slot 21, and GICs in
slots 22 and 23, is not legal because there are greater than nine slots
between the SIB and the LANIC. (The device cards such as INPs, AIBs,
etc., do not matter in this case.)
An SIB in slot 10, LANIC in slot 17, and GIC in slot 22 is legal because
there are nine or fewer slots between each card.
Finally, this limitation does not span IMBs. Each 1MB must conform only
individually.

Installation
2-6

Record the location of the LANIC in the configurat.ion section of the
System Support Log.

Conne ct the hood connec tor of the approp riate LANIC cable (part
numbe r
30241-60002 for Series 42 and 52; part numbe r 30241-60003 for
Series 48,58,
68, and 70) to connec tor J2 of the LANIC card. Conne ct the other
end of
the LANIC cable as follows:
Series 42 and 52. Fasten the LANIC cable connec ting box to the
grounding strip at the bottom of the SPU (system processor unit) frame
.
with the captive thumbscrew attached. Be sure the raised mount ing
lug is
inserted in a hole in the grounding strip. Tighte n the thumb screw
securely.
Conne ct the ThinM AU AUI cable to the LANIC cable connec tor.
Series 48 and 58. Fasten the LANIC cable connec tor, with its mount
ing
panel attache d, to the junctio n panel on the side of the card cage.
Use
only cutout numbers 2, 3, 5,6, 7, or 8 for the LANIC cable. Conne
ct the
ThinM AU AUI cable to the LANIC cable connec tor.
Series 68 and 70. Fasten the LANIC cable connec tor, with its mount
ing
panel attache d. to the junctio n panel on the side of the card cage.
Conne ct the ThinM AU AUI cable to the LANIC cable connec tor.
Note
that the junctio n panel on Series 68 and 70 systems consists of two
sets of
24 slots with a cable trough above and below each set. In each
set of 24
slots, there are 12 upper and 12 lower slots. The LANIC internal cable
should be installed in one of the lowest 12 slots with the MAU AUI
cable
routed throug h the lower cable trough.

Install ation
2-7

Start Up and Verification
For start up and preliminary verification of the LANIC. perform the following:

1. Turn on computer system power.
2.

A self test. which is contained on the card. will execute at power on. There
are 15 LEOs on the front edge of the LANIC card (see Figure 2-1). The
seven LEOs on the top are used to indicate activity on the AUI cable. The
eight LEOs on the bottom are used by self test.
The power-on self test begins with all eight selftest LEOs blinking on and
off in unison for approximately 10 seconds. Thereafter, the bottom LED
(labeled "ST") is lit to indicate that the self test is in progress. and the
remaining seven selftest LEDs will perform a binary count. incrementing
from 0000001 to 0101110 and executing a self test for each binary code
displayed. Some tests require several seconds to execute. some tests
require much less. but the LEDs will be lit for at least 100 milliseconds
for every test. thus each code will be visible as the LEOs increment the
count. No binary codes are skipped. The binary codes and the self tests
they represent are listed in Chapter 4.
Watch the LEOs as the selftest program executes. If the self test
completes with no errors, the ST LEO will be on and the other seven
LEOs will be off (a code of all zeros) for five seconds. After five
seconds, the ST LED will go off. and the remaining LEOs will reflect
activity on the LANIC. If the self test fails, the code of the test that
failed will be displayed for a minimum of 20 seconds. This display will
continue until the system accesses the link, while the selftest LED blinks
slowly.
Note that if the self test indicates failure 36H or 46H, this could indicate
that the MAU is not connected. Verify that it is connected. If the
failures are still indicated. the error could be in the MAU, or the coaxial
cable. If the LANIC fails self test, refer to Chapter 4 for maintenance
procedures. and for further information on the self test.

Installation
2-8

Start up the system in accordance with the procedures contained in
Appendix A of this manual and in the HP 3000 System Operation and
Resource Management Relerence M anllal. part number 32033-90005.

Run the LAN diagnostic on the LANIC/MAU combination. Refer to the
LA N / 3000 Diagnostic and Troubleshooting Guide, part number 30242-90003
for information on running the diagnostic.

Reshipment
If any item of the ThinLAN 3000/V link is to be shipped to Hewlett-Packard for
any reason, attach a tag identifying the owner and indicating the reason for
shipment. Include the part number of the item being shipped.
Pack the item in the original factory packing material, if available. If the
original material is not available. good commercial packing material should be
used. Commercial packing and shipping companies have the facilities and
materials to repack the item. BE SURE TO OBSERVE ANTI-STATIC
PRECAUTIONS.

Installation
2-9

Principles of Operation

Introduction
This chapter has a description of the HP 30240A ThinLAN 3000 IV Link, Local
Area Network Interface Controller (LANIC). The description gives the
principles of operation.

Functional Description
The HP 30240A ThinLAN 3000/V link is an implementation of the IEEE
8022 and IEEE 802.3 Local Area Network (LAN) standards and is used to allow
HP 3000 computer systems to communicate with other HP 3000's over a Local
Area Network (LAN). The IEEE 8022 Local Area Network standard defines a
logical link control protocol, and IEEE 802.3 Local Area Network standard
defines a bus utilizing CSMA/CD (Carrier Sense Multiple Access/Collision
Detect) as the access method.
The ThinLAN 3000/V link functions as an intelligent Direct Memory Access
(DMA) channel which communicates with the host system via the system
backplane. Local intelligent control is provided by a microprocessor and
firmware on the LAN Interface Controller (LANIC).
The ThinLAN 3000/V link consists of a LAN Interface Controller (LANIC), an
Attachment Unit Interface (AUI), and a Medium Attachment Unit (MAU). The
MAU attaches to a coaxial cable which connects the various computer systems
together on the Local Area Network~ and the LANIC provides the interface
between the LAN and the computer system.

LAN Interface Controller (LANIC)
The LANIC is an intelligent DMA channel which communicates with the host
system via the system backplane. On the network end of the LANIC. the AUI
carries bit-serial data and control information to and from the MAU. which
attaches directly to the network coaxial cable. A functional block diagram of
the LANIC is shown in Figure 3-1.

Principles of Operation
3-1

Host to LANIC Communication
The host communicates with LANIC through channel registers and data
structures stored in system memory. Basic channel communication registers
provide for channel identification, interrupt control, and diagnostics. Of primary
importance are the Control Register (CR) and Status Register (SR), which provide
for the input and output of control and status information. Link-level
commands and status are passed via two queue structures stored in system
memory shared by the LANIC and the host.

1--------1

r-----,

1 --L

1
1

I
I

I
I
HI
I

DNA
INTERF'ACE

T LLI
I~
~

I~~

CHANNEL
LOGIC
AND
REGISTERS

I
I
I

BACKPLANE

INTERF'ACE
MODULE

I
I

I
I
I
I
,

PROTOCOL
CONTROLLER

AUI
INTERF'ACE

Z-80B

MPU

16 KSYTE

RAM

115

Ii I
I
I WI I
L

e KSYTE
ROM

MAIN
MODULE

Figure 3-1. LANIC Functional Block Diagram

Principlt~S

3-2

of Operation

UI
~:CABLE

-.-J

LANIC MPU and Firmware
Local intelligent control is provided by a microprocessor (MPU) and firmware
on the LANIC card. An 8-bit microprocessor. type Z-80B. handles all the
LANIC-to-host communication and performs many link-level operations
independently of the host. The MPU also is responsible for performing an
on-board self test to detect and locate hardware faults. The firmware for the
MPU resides in both ROM and RAM. The ROM firmware has the self test.
MPU interrupt control. and bootstrap programs. The link-level operational
firmware is downloaded into LANIC RAM from system memory.

Local Communications Controller
The Local Communications Controller (LCC) is a high-performance LSI device
that performs most of the data link and physical link functions for the local
network architecture. The LCC performs high-speed serial operations. packet
address checking. network contention control. packet formatting, and CRC
(Cyclic Redundancy Check) generation/checking. The LCC is controlled by the
MPU through local memory.

Direct Memory Access
The LANIC can transfer data directly to and from system memory. Once the
host has given the LANIC the location of data buffers in system memory, data is
transferred without host intervention. This allows maximum system performance
by uploading the task of packet transmission and reception from the host.
allowing the host to spend more of its time on other processing.

Principles of Operation

3-3

Firmware Download and Configuration
Although the self test~ diagnostic~ and bootstrap firmware are all resident in
ROM~ the operational firmware must be downloaded from the host into the
LANIC local memory. After the firmware is downloaded~ control is passed to it
and the LANIC is ready to be configured. Configuration comprises the 82586
chip configuration~ setting the station address. and initializing the command
response queues.
Firmware Download

The host initiates the downloading of firmware from system memory to the
LANIC local RAM. The LANIC performs the actual transfer via its DMA
facility. After the transfer. the LANIC computes the checksum of the data in
local RAM and compares it with the checksum computed by the host. This
ensures that the download firmware is transferred correctly. The entire
firmware may be downloaded via a sequence of download operations. The host
has full control of firmware operation and can suspend firmware execution at
any time and dump LANIC memory and hardware status to system memory.
Setting Station Address

The LANIC supports both globally and locally administered ~ddressing. Globally
administered addressing is supported by a ROM on the LANIC that has a unique
48-bit address code. This address can be read by the host. Setting the station
address is accomplished by a process involving the Duplicate Address Check
(DAC) protocol. The host supplies the LANIC with a candidate station address.
The LANIC sends an Exchange Identification (XID) packet with this address in
the destihation field. If any node is using the same station address, it sends the
packet back to the LANIC. The LANIC waits for any response to come back
before establishing its station address. If the DAC protocol fails. the host is
notified to take further action.
Queue Initialization

Once operational. most of the communication between the host and the LANIC
is via a pair of queue structures in system memory. One queue~ the Command
Queue (CQ). is used by the host to send commands to the LANIC. The other
queue. the Response Queue (RQ), is used by the LANIC to return status to the
host. Each queue is fixed in size with fixed-length entries. however these
parameters are programmable when the queues are configured by the host. The
head and tail pointers are stored in system memory along with each queue. The
host informs the LANIC of new entries in the CQ by means of the
READ_QUEUE command. The LANIC informs the host of new RQ entries by
means of the system interrupt facility.

Principles of Operation
3-4

Transmit Operation
Types of Packets Transmitted

The LANIC can transmit any size packet up to the maximum packet size. Short
packets are automatically padded to meet minimum packet length requirements.
Transmit Buffer Management

The host is responsible for setting aside transmit buffers in system memory. The
starting address and length of each buffer is sent to the LANIC via the XMIT
request. Each buffer is identified by a unique ID number. When the LANIC has
successfully transmitted a transmit buffer, or when it encounters an irrecovera ble
error, it returns the ID number and status to the host via the Response Queue
(RQ). The host must ensure that transmit buffers are frozen in system memory
from the time the XMIT request is entered into the CQ until the LANIC returns
the buffer ID in the RQ.
Queuing of Transmit Buffers

The transmit operation requires a number of steps and there in no way to predict
when a transmit buffer is actually sent. Transmit buffers queue up in the CQ
and in an internal transmit queue. The buffer at the head of the transmit queue
is processed when no receive packets are being processed. Even then, there may
be a delay due to the CSMA/CD protocol.
Transmit Operation Example

A transmit frame is assembled by the host in system memory. The host then adds
to the CQ an XMIT request containing the address and length of the transmit
frame and the ID number. The LANIC will process this command after it
completes operations in progress and gets the command from the CQ. The
LANIC then copies the contents of the frame buffer from system memory to its
local memory. The next phase is undertaken by the 82586 LCC chip. The 82586
handles the CSMA/CD protocol, serializes the data from the local memory
buffer, sends it out on the network, and generates the frame check sequence.
After the 82586 LCC is finished with the frame, LANIC firmware records the
frame completion status and ID number in the RQ.

Principles of Operation
3-5

Receive Operation
Types of Packets Received

The LANIC will only receive packets addressed to its station address (except
when promiscuous mode is configured). These packets may be individually
addressed, broadcast, or multicast, if the LANIC has been configured for such
operation. Packets that are shorter than minimum or longer than maximum are
not returned to the host, however, the statistical counters are updated.

Receive Buffer Managaement

The host is responsible for setting aside receive buffers in system memory. The
starting address and length of each buffer are sent to the LANIC via the RECV
command. These buffers are identified via a unique ID number. When the
LANIC fills a receive buffer, it returns the ID number to the host via the
Response Queue (RQ). From the time that the host enters the buffer descriptor
into the CQ until the LANIC returns the ID number in the RQ, the host must
ensure that the buffer is frozen in physical memory. Since neither the host nor
the LANIC have control over what time a packet arrives, there must be a
sufficient number of buffers ready for the LANIC to receive bursts of packets,
otherwise packets will be lost. For further information on lost packets, see the
paragraph "Receiver Blind Spots".
Queuing of Received Packets

Received packets may be queued by the LANIC before being reported to the
host. In order to report received packets to the host, the LANIC microprocessor
must access system memory. However, it may not be able to do this during a
burst of receive packets because the LANIC DMA capability will be saturated
with packet transfers to system memory. The microprocessor will update the RQ
as soon as a lull in received packet traffic occurs.
Receiver Blind Spots

Under certain conditions, the LANIC can fail to receive a packet. The following
conditions are necessary for the LANIC to receive a packet at any time:
The receiver must be turned on.
There must be a buffer ready to receive the packet.
The LANIC must be able to write to memory fast enough to prevent losing
data.
If any of the above conditions are not met, receive packets will be lost.

Principles of Operation
3-6

Receive Operation Example
The host allocates one or more receive buffers and enters RECV commands
containing the buffer descriptors and IDs into the CQ. The LANIC removes
these descriptors from the CQ and puts them on an internal queue. and turns the
82586 LCC receiver on. The LCC prepares for packet reception by taking the
first buffer descriptor off the internal queue. The LCC looks at the destination
address of all packets on the network. When the destination address matches the
LANIC station address. the LCC deserializes the packet and starts writing it to
system memory using the current receive buffer descriptor. At the end of the
packet. the LCC compares the CRC and re-uses the buffer descriptor if there was
an error in packet reception. Otherwise. the LCC records the packet reception.
prepares the next buffer descriptor from the internal queue. and interrupts the
microprocessor. When the microprocessor acknowledges the interrupt, the LCC
adds the status and ID number of the completed packet(s) to the RQ.

Principles of Operation

3-7

Error Management
The LANIC detects command, system, and network errors, takes recovery action
when appropriate, and reports status to the host. Command format errors are
simply reported to the host, but do not result in any interruption of operations in
progress. The LANIC attempts recovery of certain errors, such as ThickMAU
jabber, and if recovery is successful, the LANIC reports the recovery to the host
for logging, and continues operation. When the LANIC detects a
non-recoverable error, such as a system memory error, it aborts all operations in
progress, reports the nature of the error to the host via the system interrupt
mechanism. and waits for further action by the host.

Selftest Operation
The LANIC executes a self-contained selftest program on system reset. or under
host software control. Additionally. self test can be initiated via a switch on the
card. or by power-on. The LANIC selftest program tests a portion of the LANIC
hardware. The selftest result code is displayed visually on the LANIC card (see
Chapter 4), and can be programmatically read by the host via a channel register
dedicated to selftest result codes.

System Interrupt
The LANIC can request a host software interrupt via two pseudo-device
interrupts. When the host issues the OBn command to the LANIC, the data
returned has either a zero or a one in bit 15. corresponding to the interrupting
device number. Device number zero corresponds to the interrupt called SINTRO.
and device number one corresponds to the interrupt called SINTRI. If both
interrupt requests, SINTRO and SINTRI. are active simultaneously the interrupt
code for SINTRO is returned.
Operation of the LANIC IRQ (Interrupt Request) is as follows:
If either or both of SINTRO and SINTRI are set and the interrupt mask.
MASKF. is set. then the channel asserts the IRQ line on the backplane.
Eventually, the host detects that IRQ is asserted and invokes the microcode
routine to handle interrupts. This microcode performs an IPOLL to determine
which channel(s) are requesting. and then an OBn to determine which device
on the channel to service. After determining which channel and device to
service. the microcode issues a WIOC command to clear SINTR, and
dispatches the appropriate software interrupt routine.

Principlc~

3-8

of Operation

SINTRO Selftest Interrupt

The SINTRO interrupt request is activated by the ROM-based selftest firmware
when the self test sequence completes or whenever an idle self test failure is
detected. The host software reads the STR channel register to determine the
type of error detected. A more detailed description of the self test is contained
in Chapter 4.
SINTR1 LANIC Interrupt

This interrupt is activated by either the ROM-based kernel firmware or by the
downloaded operational firmware to signal the host software that some event in
the LANIC has occurred. Host software reads the SR channel register to
determine what type of event has occurred. The types of events fall into two
groups:- those related to a command issued to LANIC by the host software, and
those resulting from internal LANIC operations.
Interactive Command Completion

This response is given when the LANIC completes the execution of an
interactive command. The command-specific bits of the response code contain
status and error codes whose meanings depend on the associated command as
shown below.

Command code
Completion status

Completion status
,

, Command
,
I

code
I

= Command code originally
= See below and paragraph
00 01
02 03

04 08 09 -

OA 08 -

given
"Self test"
command executed correctly
sync between driver and LANIC established
(e.g., an all-ones word written into CR)
illegal length command
command not found
command doesn't match length
host buffer crosses bank boundary
non-word address on download or dump
checksum didn't check (DOWNLOAD command)
illegal start address (START CODE command)

Principles of Operation
3-9

Interactive Command Acknowledgment

This response is given after the firmware reads the first word of a multiple-word
command from the CR. This response is useful for avoiding the host software
busy-wait on CRFULL after the first word of a multiple-word command has
been written to the DR. This problem is due to the fact that the first word may
not be accepted by the LANIC for several milliseconds, but the succeeding words
are handshaken with negligible delay. A command acknowledgment response is
not given for a single-word command as it is followed by a command
completion response anyway. See below.

-8

Undefined
I

11
I

12
I

14
I

15
I

Batch Command Completion

The response shown below is given when the firmware completes the execution
of a batch command:

Undefined

6
I

Fatal Error Response

The fatal error response is given when and event occurs that requires the LANIC
to be fe-initialized. All operations in progress are aborted and pending operations
are suspended. The LANIC is in the KERNEL state after giving this response.

Catastrophe Code
I

1'1

3-10

Additional information
I

Catastrophe code = fatal error type (41H
Additional information = error number

Principles of Operation

11
I

= SW,

42H

= HW)

LANIC Rese ts
There are three types of resets on the LANIC: power- on reset, hard
reset, and
soft reset. The power-on reset is the highest priorit y and the soft reset
is the
lowest priority. The resets are nested such that a higher priorit y reset
includes all
lower priorit y resets. Table 3-1 summarizes the LANIC reset operati
ons.
Table 3-1. LANIC Resets and Their Effect s
Affected
Function
MAUP OWER
SELFTEST
VISIND
MHSEN
SLVHS
MASTER HIS
CRFU L
MASKF
SINTRO
SINTR I
Z-80 RESET

PON
OFF
YES
ON
OFF
RESET
RESET
0
0
0
0
PULSE

INIT
IOeL

Hardrs t
OFF
YES
ON
OFF

OFF
NO
ON
OFF

---

RESET
0
0
0
0
PULSE

RESET
0
0
0
0
LATC H

Softrs t
OFF
NO

--OFF

--RESET

---

-NO

Power-On Reset

The PON signal on the backplane causes a power- on reset. The entire
hardw are
and firmwa re state of LANIC is initialized and all LANIC operat ions
on the
backplane cease. When the PON goes active, the LANIC enters the
SELFTEST
state.
Hard Reset

Hard reset aborts all operations in progress on the LANIC, resets all
contro l
registers, and forces the LANIC into the SELFTEST state. Self test
is then
perfor med and the internal status of the firmwa re prior to the reset
is
unrecoverable. LANIC commands (except further hard resets) must
not be issued
until the selftest sequence has completed. At the end of the selftes
t sequence, the
LANIC will go to the KERN EL state, waiting for comma nds from
the host.
Hard reset is started by the backplane commands PON, SRST, IOCL,
INIT,
WREG 14, WREG 15, and by activating the selftest switch.
The HARD RST clears the channel interru pt mask flip-flo p MASK
F, clears both
SINTRO and SINTR I interru pt requests, and illuminates the VISIN
D visual
indicators (LEDs). In addition, the master handshake enable flip-flo
p, MHSEN, is
cleared;"

Principles of Operat ion
3-11

Soft Reset

Soft reset suspends all hardware operations in progress and puts the LANIC into
the KERNEL state. waiting for further commands. In this way. most of the
LANIC internal state information is preserved. The microprocessor is not reset
and information pertaining to the RQ entries remains valid. The firmware is
forced to the KERNEL state and communication with the host software is
restricted to the CR and SR only.
The soft reset is typically issued when a LANIC failure has been detected by the
host (e.g., LANIC is unresponsive). The firmware is thus forced to communicate
with the host software. Since self-test has not been performed, diagnostics of
the firmware can take place by issuing the MEMORY_DUMP command.
Soft reset can be initiated by the LANIC or by host software. The LANIC
hardware initiates soft reset by detecting certain system bus errors. These errors
are: system bus timeout, memory parity error. bus parity error, or memory
bounds violation. System software can initiate a soft reset by writing register 14
(ABORT register) on the LANIC with bit 15=1.
Z-80 Reset

The IOCL and INIT commands effect a. HARDRST. but the microprocessor
remains reset. This feature is useful for diagnostics which need to reset the
hardware registers without initiating the selftest sequence. The microprocessor
remains reset until a normal HARDRST in issued.
Power-Fail Warn

When the backplane power-fail warn signal (PFW) is active. the LANIC is
prevented from requesting or initiating a system bus master handshake. If the
PFW signal becomes active while the LANIC is requesting. but has not yet been
acknowledged bus master. then the LANIC backs off from requesting the bus
while PFW is active.

Principles of Operation
3-12

Self Test
The LANIC has a selftest feature that performs tests of internal circuitry and
provides a status code indicating the result. Before the execlltion of each selftest
step. the step number is written to the STR and the VISIND registers. When the
self test is complete. the LANIC interrupts the host and enters the KERNEL
state where it is ready to accept interactive commands.

Manually Initiated Self Test

Self test is manually initiated by the selftest switch on the LANIC card. The
location of this switch is shown in Figure 2-1 in Chapter 2.

Remotely Initiated Self Test

Self test is remotely initiated by the backplane command WREG 15. or by the
backplane signals PON or SRST (Power On or System Reset).

Idle Self Test

During operation of the LANIC. various tests of hardware are performed when
no other tasks are being processed. If a hardware failure is detected, an error
code is placed into the STR register and the host interrupt request is set.

Visual Indicators

Fifteen light-emitting diodes (LEDs) are used on the LANIC card to indicate
LANIC activity. The locations of the LEDs are shown in Figure 2-1 in Chapter
2. Eight of the LEDs are used for self test results and are described in Chapter 4;
the remaining seven LEDs are used for indicating activity on the LANIC card
and the LAN network. These LEDs are described in the paragraph "LEDs", later
in this chapter.

Principles of Operation
3-13

Attachment Unit Interface (AUI) Circuitry
The Attachment Unit Interface (AUI) is the interface between the LANIC board
and the Medium Attachment Unit (MAU). The AUt MA U, and the coaxial
trunk cable comprise an analog network. The analog network provides the
physical connection between Local Area Network (LAN) nodes.
A block diagram of the AUf interface circuitry is shown in Figure 3-2. The AUI
interface consists of four blocks:
• A type 802.3 chip
• Level 1 circuitry
• MAU power control
• AVI activity trace LEDs

SWITCHED 12 VOLT

TO PROTOCOL
CONTROLLER
~--...,.-~

t----~)-~

Figure 3-2. AUf Interface Block Diagram

The 8023 chip performs the following functions:
Decodes receive clock
Decodes receive data
Generates transmit clock
Encodes transmit data with clock
Decodes CONTROL IN
Detects carrier present
Loops transmit data to receive data for diagnostics
The AUI side of the 8023 chip consists of two balanced receivers
(DATA5IN + CONTROL5IN) and one balanced driver (DATA50UT). The
signals from these circuits are put through a passive balancing network and are
then transformer coupled to the AUI pairs.
Principles of Operat.ion
3-14

MAU Power Control Circuit

The MA V power control circuit provides three functions:
1.

12-Volt Switch: The Z-80B MPU can turn the 12V to the AUI on or off

12-Volt Current Protect: If the current to the AVI goes above 1.2A, the
power control circuit switches the +12V off, thus protecting the LANIC and
the system from shorts in the AUI cable or MAV. The Z-80B will detect the
fault and attempt to restart MAU power. If the attempt fails, the Z-80B
notifies the host system of the fault.

12-Volt Sense: The Z-80B can determine if power to the AUI is on or off.
However, it is not able to accurately measure the exact voltage being
supplied. The IEEE 802.3 standard requires VP (+12V) to be greater than
11.28 volts. It is possible that the +12-volt power supply may be adjusted low
enough such that less than 11.28 volts is present at the LANIC edge under
load. If faulty ThinMAU operation is suspected, and ThinMAU replacement
has not corrected the problem, the VP voltage should be checked. The VP
voltage can be checked by connecting an accurate voltmeter between the
+12V and GNO test points on the LANIC. If the voltage under load is
found to be less than 11.28V, the system +12V power supply must be checked
and adjusted to the upper end of the allowable range. If the power supply is
already set at the upper end of its range, the LANIC may need to be
replaced. Consult the appropriate CE H andhook for details.

LEOs
The LANIC uses 15 LEOs to monitor activities on the card and the LAN
network. The locations of the LEOs are shown in Chapter 2, Figure 2-1; the
labels and functions of the LEOs are shown in Figure 3-3.
The seven LEDs labeled A through G monitor activity on the A UI interface.
The eight LEDs labeled H through Nand * monitor LANIC MPU activity. A
great deal of information about the state of the network and the LANIC and
system software can be gained by studying the LEDs. They are provided as an
aid in problem detection and resolution.
Each of the 15 LEOs is labeled with two different labels. The single alphabetic
labels are helpful for quick reference to the LEDs; the two-letter mnemonics are
intended to remind users of the function being indicated by the LED.

Principles of Operation
3-15

ABC

ypi

[CL

L I EDOL I [CRLITX

0 0

•

0 0 0 0000000

ill

lli

Dl'.TA OUT

i
EOCE

LE't'£L

orr
en

I
~...

EILN<

orr

~
i
ON

!
lII:

Iii

en
ON

Figure 3-3. LANIC LEDs

Principles of Operation
3-16

The meanings of the eight MPU (microprocessor unit) activity monitoring LEDs
are as follows:
Mnemonic

MPU Activity in Progress

On when the LANIC is processing and transmitting a frame.

On when the LANIC is processing a frame that was received at
an address which the LANIC recognized as its own.

On when the LANIC is monitoring all link activity, or is
monitoring activity sent to a particular address not its own.

On when the LANIC receives a command from the SPU
(system processor unit) to start downloading operating
firmware. Off when the SPU commands the MPU to begin to
execute the downloaded feature.

On when ROM-resident firmware is being executed by the
MPU. Off when downloaded firmware is being executed by
the MPU.

On when the MPU is quiescent. During such times, it is
checking for activity that requires attention.

On when the MPU is executing an idle test of internal LANIC
circuitry. During idle test, the MPU tests hardware on the
LANIC that can be exercised without affecting readiness to
process frames. The idle test also runs before the node becomes
operational on the link.

On when the MPU is executing the ROM-resident self test,
which verifies proper operation of the LAN hardware
subsystem. \Vhen the ST LED is lit, the other seven MPU
activit.y LEOs are interpreted as self test progress and failure
indicators. rather than according to the mnemonics given above.
For details of the use of self test, see Chapter 4 of this manual
and the LA N/3000 Diagnostic and Trouhlcshoo/ing Guide. part
number 30242-90003.

The seven AUI activity LEOs are intended to be used as aids in determining
activity on the network, and whether the source of this activity is this node or
some other node on the network. These seven LEOs monitor the four functions
shown below.

Principles of Operation
3-17

Mnemonic

Function Monitored

Data Qut. On when data is transferred from this LANIC to the
Data Out AUI pair.

~ohlision Detect.

~aB.rier Sense.

On when data is detected coming into the node
on the Data In AUI pair. or on when the coJIision function is
detecting collisions. The CR indicator does not come on due to
SQE heartbeat.

'yoltage flus. This LED indicates the voltage present on this
12-volt supply lead to the MAU.

On when a collision is detected by the MAU
on this node. Since the MAU detects collisions whether it is
transmitting or not. the CL indicator comes on for every
collision that occurs on this coaxial cable. The CL indicator
does not come on when the MAU sends an SQE heartbeat after
transmission.

Each of the indicators for DO. CL. and CR consist of a pair of LEDs. labeled E
and L. The pair is driven in such a manner that all conditions of activity from
occasional isolated events to continuous events can be distinguished by the
unaided eye. This is accomplished in the following manner:
Each time that the event being monitored by an LED pair begins. the E LED
is turned on and remains on for 6 msec regardless of the length of the event.
The L LED turns on at the beginning of the event and turns off at the end of
the event.
Following this algorithm. a single isolated event of short duration produces a 6
msec blink of the E LED. and the L LED is on for the length of the event,
which is short. Therefore. the L LED appears to remain off.
As the frequency of events of short duration increases. the E LED appears to
be constantly lit. and the L LED begins to glow.
When short duration events occur constantly. both the E and L LEOs will
appear to be constantly lit.
A single event of very long duration produces a single 6 msec blink of the E
LED at the beginning of the event. and the L LED turns on and stays on for a
long time. until the event is completed.
Continuously occurring events of very long duration will cause the E LED to
blink at the beginning of each event for 6 msec. and the L LED will appear to
be constantly lit.
Events on a normally-operating network are all of short duration. For instance,
a maximum length frame requires only 1.2 msec to transmit; a minimum length
frame requires only 51 jJ.sec to transmit. Collisions have a maximum duration of

Principles of Operation

3-18

only 49 }.lsec. For events of short duration such as these, the E and L LEDs can
be visualized as a sort of two-column bar graph. Frequency of activity is
increasing as the frequency of flashing of the E LED increases while the L LED
is off or very dim. \Vhen the E LED is always on, the L LED indicates further
increase in activity by becoming brighter and brighter until it reaches full
intensity. This state of the E and L LEDs indicates continuous short events.
To understand the indications given by the DO. CL. and CR LEDs. it is necessary
to understand how the signals that drive these LEDs are related to the signals on
the AUI cable.

DO LED Pair

The event indicated by the DO LED pair is the enabling of the data encoder by
the protocol controller on the LANIC. The event begins when the encoder is
turned on. While the encoder is on, a continuous stream of encoded dat.a bits is
transmitted by the LANIC to the DO AVI pair. The event ends when the data
encoder is disabled. When the encoder is disabled. data bits are no longer sent to
the DO pair. The transmission of a single frame to the A VI DO pair is one
event. and will cause the E LED to blink on for 6 msec. The L LED will be lit
for the length of time required to transmit the data bits to the AUI pair. a
maximum of 1.2 msec for a maximum length frame.

CL LED Pair

The event indicated by the CL LED pair is the occurrence of the Signal Quality
Error (Collision) signal on the Control In pair of the AVI cable. When t.he
MAV. whether it is transmitting to the coaxial cable or not. detects a collision on
the cable. it sends the SQE signal to the LANIC on the CI pair. SQE is signalled
by a 10 MHz signal on the CI pair. The event begins when the first transition is
received at the LANIC. and ends 200 nsec after the last transition is received.
The SQE heartbeat. which is a short burst of 10 MHz signal on the CI pair after
each transmission by the LANIC on DO. does not cause the E LED to blink.
although it does cause the L LED to light for approximately I j..lsec. which is too
short to be seen. Likewise, no collision occurring on the network within 5.3 }.lsec
of cessation of transmission by the LANIC will light the E LED. The SQE
heartbeat is blocked from triggering the E LED so that the CL LEOs will
indicate the frequency of collisions occurring on the network.

CR LED Pair

The event indicated by the CR LED pair is the reception of data on the Data In
pair in the AUI cable. or the occurrence of the collision event described above.
The event begins when the first data transition arrives on the A VI DI pair. or
when the collision event begins. whichever occurs first. The event ends 200 nsec
after the last data transition on the DI pair. or when the collision event ends.
whichever occurs last.

Principles of Operation
3-19

H Through Nand .. LEDs

When the LANIC has been reset either by power-up of the system or by the
operating software. all eight of the MPU activity indicators (LEOs H through N
and *) will be on continuously. This indicates that the MPU is not executing.
Additionally. the VP LED will be off. which indicates that the MAU is not
powered. The other AUI activity indicator LEOs will all be off.
After the LANIC has successfully passed self test. and the pass code pattern has
been displayed as required. the * LED will be off. and the other seven MPU
activity indicator LEOs will now indicate the MPU activity. The * LED being
off indicates that the H-N LEOs are to be interpreted as individual activity
indicators according to their two-letter mnemonics. (See the following
paragraphs.)

TX, RX, MN, DL, RO, Q, and IT LEOs

When self test passes. the SPU is interrupted and notified of the event. Between
the time that this interrupt is given and the time when the SPU begins to access
the LANIC. the RO and Q LEDs will be lit. This indicates that the LANIC is
executing ROM code and is quiescent. while waiting for the SPU to take control.
In addition. the VP LED will be lit. indicating that the MAU is powered. Any
activity on the network coaxial cable will be indicated by the state of the CL
and CR LED pairs. The LANIC will never transmit in this state. and therefore.
the DO LED pair will remain inactive.
When the SPU prepares the LANIC for operation. it first must download the
operating firmware from system memory to the LANIC. When this process
begins. the DL LED turns on. and the Q and IT LEOs will go off. After each
download command. the Q LED lights for a few milliseconds. At least seven
download commands occur, but they may not be separately distinguishable.
However. the pattern that occurs on one working system will occur on all other
working systems. so if suspicious. compare the download pattern on the suspected
system with a system that works.
After the download is complete. the SPU will instruct the MPU to begin to
execute the downloaded firmware. When this occurs. the RO and DL LEOs will
go off. The Q and IT LEOs will turn on.
A short time later the SPU will instruct the LANIC to set its individual address.
When this occurs. the LANIC performs a duplicate address check. which is
accomplished by transmitting 10 frames to the network with a 500 millisecond
separation between frames. The TX and the DO E LED will both come on for
each of the 10 frames. In addition. the CR E LED will indicate that the frames
were sent to the coaxial cable and caused the carrier to come on. If collisions
are encountered, the frames will be retried up to 15 times each, with resultant
activity indicated by the CL LEOs. The RX LED will not light during the
duplicate address check due to our own transmission. even though the duplicate
address check frame is addressed to the transmitting LANIC. If the RX LED
lights during duplicate address checking. it is due either to a duplicate station

Principles of Operation
3-20

being detected or to an ordinary frame being address to the LANIC. If a reply
to the duplicate address check is received, this will cause the address check to
fail. no further check frames will be sent, and t.he system software will close the
link and clear the LANIC, forcing all the LANIC MPU LEDs to come on and
stay on.
If the duplicate address check passes, the link is opened. and frame transmission
and reception will commence. The LEDs will indicate activity as it occurs.
During normal network operation. frame transmission causes the LEDs to
operate in the following manner, assuming that the network and the LANIC
were both idle before the transmit request arrived at the LANIC from the SPU:
While idle. the VP. Q. and IT LEDs are on.
When the MPU begins processing the transmit command. the Q and IT LEDs
go off, and the TX LED comes on. The LANIC begins the transmit process
by reading the frame from the system to the on-card memory.
Once the frame is in LANIC local memory. and the network is free, the serial
transmission process begins. This causes the DO E LED to light. The DO L
LED will also be turned on for the duration of the frame transmission. but
this mayor may not he visible, depending upon the length of the individual
frame being sent.
The serial data reaches the MAU and is transmitted to the coaxial cable. The
MAU begins to receive its own signal from the coax. and sends it back down
the AUI cable. The LANIC detects data arriving on the DI pairof the AUI
cable, and the CR E LED is lit.. The CR L LEO will also be lit for the
duration of the frame, but this mayor may not be visible. If the DO L LED is
visible, the CR L LED will also be visible for approximately the same length
of time.
If no collision is occurs. the CR and DO E LEDs will go off after 6
millisecond, followed quickly by the transmit LED going off, and the Q and
IT LEOs coming on. If a collision is encountered. the CL E LED will come
on. and the frame will be retransmitted up to 15 times. The retransmissions
will cause the DO and CR E LEDs to appear to be on. and the DO and CR L
LEDs will probably appear to be partially lit, with t.he intensity of the L LEOs
determined by frame length. number of retransmissions required, and the time
separation of the retransmissions. The CL LEOs will also display behavior
similar to the CR and DO LEDs if multiple retransmissions are required before
the frame is successfully transmitted. In the collision case, it must be
remembered that other network activity will also cause the CL and CR LEOs
to light, and the activity caused by the LANIC will be superimposed on the
network activity being displayed by the CR and CL LEDs. A little experience
at observing the LEOs will allow the occurrence of single or multiple
collisions to be easily distinguished.

Principles of Operation
3-21

Medium Attachment Unit
A functional block diagram of the MAU is shown in Figure 3-4. As shown, the
MAU has four functional areas:
• Receive Function. Receives serial data bit streams from the coaxial
cable and sends these to the LANIC.
• Transmit Function. Accepts serial data bit streams from the LANIC,
and transmits this data to the coaxial cable.
• Jabber Fault Detection. Detects an abnormally long output data
stream ("jabber") from the LANIC. and inhibits transmission to the
coaxial cable.
• Collision Detection. Detects the presence of two or more simultaneous
transmissions on the coaxial cable and informs the LANIC of this
condition.

Receiver
The coaxial receiver has a high input impedance. (The high impedance is
necessary to allow up to 100 users to connect to the coax and not load down the
cable.) The data received from the coax is then amplified and shaped to
compensate for attenuation caused by the coaxial cable. The data is then sent
through a cable driver to the LANIC via the twisted pair of the AUI cable. The
MAV also has a DC squelch function which turns off the AVI cable driver
when no data is present on the coax as is indicated by a lack of DC component
in signals on the coaxial cable.
Since the receiver passes all data from the coaxial cable to the AVI cable. the
receiver also monitors data sent by its own LANIC, thus implementing a local
loop-back and monitoring function.

Transmitter
The transmitter accepts data from the LANIC and transmits this data to the
coaxial cable. Data is transmitted to the cable using a high-impedance current
sink. Current drive of the coaxial cable causes multiple transmitters' signals to
add without damage to the transmitters. The coaxial cable driver adheres to the
recommended value for drive level specified in the IEEE 802.3 Standard.

Jabber Fault Detection
If the LANIC should try to send data for a time longer than the longest data
packet allowed. the network throughput could be affected. (If the LANIC
transmitted continuously. no other node could access the network.) The jabber
fault detection circuitry detects any attempt by the MAU to transmit for longer
the 20 milliseconds. and prevents this from happening by turning the transmitter

Principles of Operation
3-22

off. The LANIC is informed of the shut-off condition by a continuous signal
(SQE) on the CI pair of the AUI cable. The MAU is prevented from
transmitting until 500 milliseconds after the Jabber Fault is removed.

Collision Detection
When a collision occurs on the coaxial cable. the DC voltage on the cable
increases in magnitude and the collision detection circuitry senses this condition.
The LANIC is informed of this condition by a signal sent from the MAU on the
CONTROL IN (CI) cable pair (part of the AUI cable). The collision detection
scheme employed implements receiver-based collision detection. This means that
the presence of two or more transmitters can be detected even when the MA U is
not transmitting.
To insure that the collision detection circuitry is working satisfactorily. it is
tested each time a data packet is sent. At the end of each transmitted packet. a
'Heartbeat', or SEQ (Signal Quality Error) test signal (which is a short burst of the
collision indicator signal) is sent to the LANIC.

Receiver

To/F rom Coaxial
Cable
-(

Transmitter
TofF rom Lanic

t
Jabber
Detection
Circuitry

t
Collision
Detection
Circuitry

Figure 3-4. MAU Functional Block Diagram

Principles of Operation
3-23

Maintenance

Introduction
This chapter contains general maintenance instructions for the LANIC card.
Included is the repair philosophy for the LANIC card and information on the
self test. See the LA N /3000 Diagnosf;c and Trouhleshooting Guide, part number
30242-90003. for detailed procedures to be used in tr.oubleshooting networks
containing the ThinLAN 3000/V link. and for diagnostic procedures to be used
in isolating failures in ThinLAN 3000/V nodes to the field replaceable assembly.

Repair Philosophy
Field repair of the LANIC cards is limited to the replacement of the card itself.
To exchange a LANIC card. remove it from the system and prepare it for
reshipment to Hewlett-Packard in accordance with the instructions presented in
Chapter 2.

Maintenance
4-1

Self Test
A self test is included in ROM on the LANIC card. The self test runs at
power-on, when the LANIC TEST (RESET) switch on the LANIC card is
pressed. or when invoked by the LAN diagnostic.

NOTE
The self test consists of several tests which check approximately half the
circuitry on the LANIC card as well as performing a simple test of the MAU.
The ThinLAN 3000/V link diagnostic must be run to perform a complete test of
the LANIC card. See the LAN/ 3000 Diagnostic and Troubleshooting Guide. part
number 30242-90003 for a description of the diagnostic.

I CAUTION I
Pressing the LANIC test performs a hard reset on the LANIC card before the
self test is initiated. Networking operations in progress will be disrupted by
pressing the reset switch. Once self test has started,· allow it to complete prior to
pressing the switch again. Pressing the selftest switch when the link is open or
while self test is active has a slight possibility of crashing the system.

To run the LANIC self test, perform the following:
1.

Determine that the LANIC is not in use. This can be done by typing

:SHOWDEV nn
at any terminal on the system, where nn is the logical device number of the
LANIC. If you see

LDEV
36

AVAIL
AVAIL

OWNERSHIP

VOL . . . etc.

or something similar. the LANIC is not in use. If you see

LDEV
36

AVAIL
UNAVAIL

OWNERSHIP
SYS #1

VOL . . . etc.

the LANIC is probably in use, and you should do a

NETCONTROL NET=xxx;STOP
before proceeding.

Maintenance
4-2

Open the computer card cage door and observe the selftest LEOs (see Figure
4-1 for the locations of the LEOs). Note whether the LEOs indicate normal
activity or whether the ST/* LEO is blinking slowly and LEOs H through N
are displaying a steady pattern. If a steady pattern is being displayed by
LEOs H through N, make a written record of which LEOs are lit. (This
·information may be needed later if the problem is intermittent.)

Press the LANIC TEST RESET switch (see Figure 4-1) to initiate the self test.

Observe the selftest LEOs. Refer to Table 4-1 for the meanings of the
various LEO patterns. If the self test completes with no errors. the selftest
LEO (ST/*) will be on and LEOs H through N will be off (a code of all
zeros) for a period of five seconds. After five seconds. the ST/* LEO will go
off and LEOs H through N will reflect activity on the LANIC. If the self
test fails, the code of the test that failed will be displayed by LEOs H
through N and the ST/* LEO will blink slowly for at least 20 seconds
(allowing time for the code to be noted).

If the LANIC fails self test. except as noted below. replace the LANIC card
in accordance with the procedures given in Chapter 2. Re-run the self test
after the new card is installed. If the new card passes self test and there still
appears to be a problem on the network. run the LAN diagnostic (it is
possible for the LANIC to pass self test and still not be functioning properly).
The diagnostic tests more of the LANIC card circuitry and also tests the A VI
and MAU. Refer to the LA N / 3000 Diagnostic and Troubleshooting Guide.
part number 30242-90003. for information on running the LAN diagnostic.

NOTE
The last test of the test sequence (2E. Loopback on Medium) requires that
the ThinMAU be connected to the LANIC. If it is not connected to the
LANIC. the last test will report a failure. The LANIC. however. may not
be defective in this case.

If an intermittent problem is suspected. the self test may be looped by
holding the LANIC TEST RESET switch in with an alligator clip. The self
test will then loop until a failure is detected. and will preserve the failure
code as described in step 4 as long as the switch remains in.

If the self test completes with no error indications. the LAN/3000 diagnostic
must also be run to completely check the LANIC. AUI cable. and MAU.
Run the diagnostic as described in the LA N /3000 Diagnostic and
Troubleshooting Guide. part number 30242-90003.

Maintenance
4-3

P.3'

ABCOEF'GHI JKLMN.

~lwd~lw8~lw3~1~~§~ioc ~

000000000000000

Figure 4-1. LANIC Switch and LED Locations

Maintenance
4-4

Table 4-1. Selftest LEDs and Subtest Descriptions

CODE
LED
INDICATION
HEX
NO.

H I J K L MN

SUBTEST

DESCRIPTION

0 0 0 0 0 0 1 1 Z-80

Instruction set

0 0 0 0 0 1 0 1 EPROM

Checksum

0 0 0 0 0 1 1 1 Station Address PROM

Checksum

0 0 0 0 1 0 0 1 High Byte Latch

0 0 0 0 1

0 0 0 0 1 1 0 1 Byte RAM Data

Odd addresses

0 0 0 0 1 1 1 1 Byte RAM Address

Incrementing addresses

0 0

0 0 0 1 0 0 1 1 Word RAM

1 1 Byte RAM Data

1 0 0 0 1 Byte RAM Address

Even addresses

Decrementing addresses
Address tests

A 0 0 0 1 0 1 0 1 Word/Byte Address

Address mapping

B 0 0 0 1 0 1 1 1 Z-80

Memory reference instructions

1 1 0 0 1 MDIAG register

Proper state after reset

SYSCON register
0

0 0 0 1 1 0 1 1 eTe

Data test

0 0 0 1 1 1 0 1 eTe

Mode 0 counting

1 1 1 1 1 CTC

Mode 2 counting

0 0 1 0 0 0 0 1 CTC

Mode 4 counting

0 0 1 0

1 0 0 1 0 1 Z-80 interrupt

1 0 0 1 1 1 2-80 NMI

1 1 Interrupt PAL

1 0 0 1 MHSDIS

Bit 4 set and cleared

Non-Maskable Interrupt
DMA Handshake Disabled

Maintenance
4-5

Table 4-1. Selftest LEDs and Subtest Descriptions (Continued)

CODE
LED
INDICATION
HEX
NO.

HI J KL M N

SUBTEST

1 0 1 0 1 1 PADDR to BADDR bus

DESCRIPTION
Low 15 bits

0 0 1 0 1 1 0 1 ZBANKL reg ister

Low Z-80 bank bit

0 0 1 0 1 1 1 1 ZBANKH register

Eight high Z-80 bank bits

0 0 1 1 0 0 0 1 Pre lim ina ry FIFO

INREADY, ADVREADY, OUTREADY

0 0 1 1 0 0 1 1 FIFO Data

BDATA(7)

0 0 1 1 0 1 0 1 FIFO Data

BEA(7,8)

0 0 1 1 0 1 1 1 FIFO Data

BDATA(2:6)

0 0 1 1 1 0 0 1 FIFO Data

BDATA(0,1,13:15)

0 0 1 1 1 0 1 1 FIFO Data

BDATA(8:12)

0 0 1 1 1 1 0 1 FIFO Data

BA( 11 : 15)

0 0 1 1 1 1 1 1 FIFO Data

BA(6:10)

0 1 0 0 0 0 0 1 FIFO Data

BA(1:5)

0 1 0 0 0 0 1 1 R14

Configuration register

0 1 0 0 0 1 0 1 OBII register

Value; Channel number not 0

0 1 0 0

0 1 001 0 0 1 MAU Power

0 1

0 1 0 1 1 R13

CR, CR Full Bit

0 1

0 1 1 0 1 R15

Selftest Result register

Maintenance
4-6

1 1 1 COMCON register

Values from reset
On/Off (AUI/MAU not requ ired)

Table 4-1. Selftest LEDs and Subtest Descriptions (Continued)

CODE
LED
INDICATION
HEX
NO.

SUBTEST

H I J K L MN*

DESCRIPTION

0 1 0 0 1 1 1 1 82586

Interrupt

0 1 0 1 0 0 0 1 82586

Reset

0 1 0 1 0 0 1 1 PBUS register
addressing

0 1 0 1 0 1 0 1 82586

RAM addressing

0 1 0 1 0 1 1 1 82586

Diagnose

0 1 0 1 1 0 0 1 8023

Loopback

0 1 0 1 1 0 1 1 82586

Write to FIFOs

0 1 0 1 1 1 0 1 MAU

Loopback on medium

ST (Selftest) LED

The final test in Table 4-1, the MAU loopback test, sends the following frame on
the coaxial cable:
DESTINATION ADDRESS = SOURCE ADDRESS =
the unique station address of this LANIC, from the station
address PROM, which may also be found on the LANICs
identifying label
TYPE FIELD:

2 bytes containing the data field length, 1134 bytes

DATA FIELD:

3 SAP bytes - 0, 1, 3EH - identifying this frame as a test
response frame with null DSAP and SSAP
31 ASCII bytes =
"HP3000_NODE_XXXXXXXXXXXX TEST. ", where
XXXXXXXXXXXX is the station address in ASCII
1100 bytes with a binary incrementing pattern

Maintenance
4-7

Table 4-2. Reporting of Unexpected Results from Self Test
1"'f'\f"\L'
,",VVL.

LED
INDICATION
INDICATION
HEX
NO.

H I J K L MN *

1 1 1 1 0 1 0 1

The 82586 failed to clear its command word.

1 1 1 1 0 1 1 1

Self-Test Result register (R15)

1 1 1 1 1 0 0 1

2-80 stack underflow during self-test.

1 1 1 1 1 0 1 1

Unexpected Z-80 Non-Maskable Interrupt (NMI).

1 1 1 1 1 1 0 1

Unexpected 2-80 interrupt.

1 1 1 1 1 1 1 1

The LANIC was reset, but self-test never started, or LED
circuitry failed. Certain system resets will freeze
the LANIC processor and leave the LEOs in this state.
This condition, then, only indicates a LANIC failure at
power-on, when the self-test switch is pressed, or when
the LANIC diagnostic starts self-test.

DESCRIPTION OF FAILURE

bi~

0 bad.

* ST (Selftest) LED
Note that the above codes are displayed withollt the

Maintenance
4-8

n*n

LED flashing.

Configuration Information

Introduction
This appendix describes how to configure MPE to include the ThinLAN 3000/V
link.

The MPE configuration must be modified when a LANIC card is added to the
computer system. Before configuring MPE, install the LANIC card as described
in Chapter 2.

Configuration Dialog
The following configuration dialog deals only with configuring a LA NIC card
into the system. The complete configuration dialog is contained in the H P 3000
System Operation and Resource Management Relerence Manual. part number
32033-90005.
To begin the configuration dialog. log onto the system as MANAGER.syS,
define the output files as shown below, and initiate a SYSDUMP as outlined in
the following steps.

NOTE
Where necessary to distinguish user input from computer output. the user input
is underlined. The "Step No." in the dialog below corresponds to the "Step
Number" in the dialog contained in the H P 3000 System Operation and Resource
."4 anagement Rc:/erence A1 anual. part number 32033-90005.
It is essential that the LANIC driver. IOLANO.PURSYS be present when the
UPDATE or COLDSTART or RELOAD is done. You may verify that the driver
is present by typing:

:LISTF IOLANO.PUB.SYS

Define the output files and initiate SYSDUMP as follows:

:HELLO MANAGER.SYS
:FILE T;DEV=TAPE
:FILE L;DEV=LP
:SYSDUMP *T,*L
Configuration Information
A-I

Step No.

Prompt and Response

ANY CHANGES?

YES

SYSTEM I D=HP 32033v. uu. ff?

MEMORY SIZE?

I/O CONFIGURATION CHANGES?

LIST I/O DEVICES?

LIST CS DEVICES?

HIGHEST DRT =

[RETURN I

(RETURN)

YES

NO
NO

xx.?

xx is the current highest hardware device address that can be
assigned. Press [RETURNl if xx is satisfactory. Otherwise. enter
a higher DRT number.

LOGICAL DEVICE #?
To specify a device to be added or removed, enter the logical
device number (Idev) of that device.
Entering .Q. or [RETURN I ends the I/O Configuration Changes
procedure.

The dialog now prints the DEVICE NAME? prompt. Press [RETURNI.

DRT #?
To add a device. enter its DRT entry number. This number is
supplied by your C.E. The formula used to calculate the DRT
number from the hardware address is:

(IMB# x 128)

(channel# x 8)

device #

To remove a device. enter Q; the dialog returns to the
LOGICAL DEVICE #? prompt.

Configuration Information
A-2

UNIT #?

SOFTWARE CHANNEL #?

TYPE? 17

SUBTYPE?

DRIVER NAME?

9
IOLANO

Step No.

Prompt and Response

DEVICE CLASSES?
Enter a device class name (up to eight alphanumeric
characters, beginning with a letter). Multiple class names,
separated by commas. may be entered at one time.

The dialog now prints the LOGICAL DEVICE #? prompt described in
step 8. If all I/O configuration is complete, press [RETURN I and
the I/O configuration portion of the SYSDUMP dialog will end.
If I/O configuration is not yet complete. enter a logical device
number and repeat the above configuration procedure.

MAX # OF OPENED SPOOLFILES = xxx

LIST I/O DEVICES?

LIST CiS DEVICES?

YES

TERMINAL TYPE CHANGES?

CLASS CHANGES?

LIST I/O DEVICES?

ADDITIONAL DRIVER CHANGES?

(RETURNI

NO
NO
NO

The dialog now prints the I/O CONFIGURATION CHANGES? prompt
described in step 4. If all I/O configuration is complete. press (RETURNI and
the dialog continues at step 77. Otherwise, enter YES, and repeat the
configuration procedure from step 4.

SYSTEM TABLE CHANGES?

MISC CONFIGURATION CHANGES?

112

LOGGING CHANGES?

119

DISC ALLOCATION CHANGES?

133

SCHEDUL I NG CHANGES?

134

SEGMENT LIMIT CHANGES?

142

SYSTEM PROGRAM CHANGES?

144

SYSTEM SL CHANGES?

NO
NO

(RETURNI

NO
NO

Configuration Information
A-3

Step No.

153

Prompt and Response

ENTER DUMP DATE?

Enter one of the following:

[RETURN I

Copies the modified MPE.
mm/dd/yy
mm/dd/yy is some date in the future. Copies the modified

MPE and the current accounting structure (but no files).
mm/dd/yy
where mm/ dd/yy is usually the date of the most recent system

backup. Copies the modified MPE, the current accounting
structure, and any files that were changed on or since the
specified date.

o
Copies the entire system (MPE, the current accounting
structure, and all files).

154

ENTER DUMP FILE SUBSETS?

155

LIST FILES DUMPED?

156

You are now requested to assign the serial storage device (a tape if
you initiated SYSDUMP as shown at the beginning of this dialog) on
which you have arranged for the system to be copied.

~ETURNI

[RETURN I

Once the system has been copied. the following message is printed:

END OF SUBSYSTEM

Configuration Information
A-4

Index
Special Characters
8023 chip, 3-14

A
Address code, 3-4
Address, link, 1-5
Attachment unit interface, 3-14
AUI, 3-14

B
Batch command completion, 3-10
Blind spots, 3-6
Buffer ID number, 3-5
Buffer management, 3-5
Buffer management, receive, 3-6

c
Collision detection, 3-23
Cables, 2-3
Standard, 2-3
Option 242, 2-4
Channel address switch, 2-2
CL LEOs, 3-19
Coaxial cable transmission medium, 1-1
Code, address, 3-4
Command acknowledgment, 3-10
Command completion, batch, 3-10
Command errors, 3-8
Command queue, 3-4
Communication, host to LANIC, 3-2
Configuration dialog, A-I
CR LEDs, 3-19
Current requirements, 2-1

D
DAC protocol, 3-4
Description
functional, 3-1
general, 1-1

Index-l

Index (continued)

Dialog, configuration, A-l
Direct memory access, 3-3
DMA, 1-1, 3-1, 3-3
DO LEDs, 3-19
Duplicate address check, 3-4

E
Error management, 3-8
Errors, 3-8
Error, response to fatal, 3-10
Example, receive operation, 3-7
Example, transmit operation, 3-5
Exchange identification packet, 3-4

F
Failure to receive a packet, 3-6
Fatal error response, 3-10
Firmware configuration, 3-4
Firmware downloading, 3-4
Firmware, 3-3
Functional description, 3-1
LANIC,3-1

G
General description, I-I
Global addressing, 3-4

H
H through Nand * LEOs, 3-20
Hard reset, 3-11
Host to LANIC communication, 3-2

10 number. 3-5

IEEE 802, I-I
Installation
channel address switch, 2-2
current requirements, 2-1
switches, 2-2
Installing the LANIC, 2-5
Intelligent control, 3-3
Interactive command acknowledgment, 3-10
Interactive command completion, 3-9

Index-2

Index (continued)

Interface, system, 1-4
Interrupt request, 3-8
Interrupt, system, 3-8
Interrupt, SINTRO self test, 3-9
Interrupt, SINTR 1, 3-9
IRQ,3-8

J
Jabber fault detection, 3-22

L
LAN controller, I-I
LAN, I-I
LANIC functional description, 3-1
LANIC interrupt, 3-9
LANIC resets, 3-11
LANIC specifications, 1-10
LANIC, 1-1
LCC, 3-3
LEOs H through Nand *, 3-20
LEOs, 3-15
Link address, 1-5
Local addressing, 3-4
Local Area Network, 1-1
Local Communications Controller, 3-3

M
Medium attachment unit, 3-22
MAU power control circuit, 3-15
Microprocessor, 3-3
MPU, 3-3

N
Network errors, 3-8

o
Option 242 cable, 2-4
Option 242 specifica tions, 1-8

Index-3

Index (continued)

p
Packets, receive. 3-6
Packet, failure to receive, 3-6
Power-fail warn, 3-12
Power-on reset. 3-11

a
Queue initialization, 3-4
Queuing of received packets, 3-6
Queuing of transmit buffers, 3-5

R
Receiver, 3-22
Receive buffer management, 3-6
Receive operation example, 3-7
Receive operation, 3-6
Receive packets, 3-6
Receiver blind spots, 3-6
Repair philosophy, 4-1
Resets, 3-11
Reshipment. 2-9
Response to fatal error. 3-10

s
Standard specifications. 1-6
Self test. 3-8. 3-13. 4-2
Selftest interrupt, 3-9
Serial interface chip, 3-14
Setting station address. 3-4
SINTRO selftest interrupt, 3-9
SINTRI LANIC interrupt, 3-9
Soft reset, 3-11
Specifications
LANIC, 1-10
Option 242, 1-18
Standard. 1-6
Standard Cables, 2-3
Start up, 2-8
Station address, 3-4
Switches, 2-2
System errors, 3-8
System interface, 1-4
System interrupt. 3-8

Index-4

Index (continued)

T
Transmitter, 3-22
Transmission medium, 1-1
Transmit buffer management, 3-5
Transmit operation example, 3-5
Transmit operation, 3-5
TX, RX, MN, DL, RO, Q, and IT LEDs, 3-20

z
Z-80 reset, 3-12

Index-5

SALES & SUPPORT OFFICES
Arranged alphabetically by -country
Canberra, Australia
Capttal Territory

roduct Une ...../.upport Ke,
., Product LIne
~

II Componen"

Computer . , .......
EIeotronIc ....truIMn.. a ....urement .ptems
. . . . . . ProdUcta
.......... Computation Products
..... onIJ tor specific product line
SUpport only tor .,.ecIIIo product .....

product line capablllty.The, do not

IPORTANT:1'heM.,......

........ or eupport.""""'" tor lilt product. within aline. at all

catIonLContllct fOUl' local ..... oIftoe tor Information regarding locations .......
It eupport Is ......... tor specific products.

EADQUARTERS OFFICES
there Is no
office listed for your area, contact one of these
Nldquart
offices.

ORTH/CENTRAL AFRICA

WE8TERNUSA

....tt-Packard S.A.
rue du BoIa-du-Lan

Hewtett·Packard Co.
5161 lankershlm Blvd.
NORTH NOLLYWOOD. CA 91601
Tel: (818) 505-5800

-1-1217 IIEYRIN 1, Switzerland
•: (022) 83 12 12
1Iex: 27835 hmea
lbte: HEWPACKSA Geneve

IIA
....tt·Packard Asia Ltd.
IF, 26 Harbour Rd.,
lnChal, HONG KONG
P.O. Box 863, Hong Kong
I: 5-8330833
lex: 76793 HPA HX
lble: HPASIAL TO

lNADA
_U-Packard (Canada) Ltd.
77 Goreway Drive
. . . . .AUQA. Ontario L4V 1M8
I: (416) 878-9430
lex: 089-8844
~STERN EUROPE
wIett·Packard Ges.m.b.h.

lbIgaaae 1
).80x 72
1222 VIENNA. Austria
I: (222) 2500-0
ex: 1 3 4425 HEPA A
lRTHERN EUROPE
wleU-Packard S.A.
D. HooPlaan 241
).Box999
·1183 AG AM8TELYEEN
• Netherlands
: 20 547999
ex: 18919 hpner
UTH EA8T EUROPE
.tett..Packard S.A.
rid Trade center
t AYe'lue Louts C8saI
15 Colntrln, GENEVA. Switzerland
: (022) 98 96 51
ex: 27225 hpaer

!DITERRANEAN
ID MIDDLE EAST
-.tt·Packard S.A.
cJlterranean and Middle East
watlons
Ina·Centre
i
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.6
Linearized : No
XMP Toolkit : Adobe XMP Core 4.0-c321 44.398116, Tue Aug 04 2009 14:24:30
Modify Date : 2013:07:02 09:08:41-07:00
Create Date : 2013:07:01 11:12:53-07:00
Metadata Date : 2013:07:02 09:08:41-07:00
Creator Tool : Adobe Acrobat 8.31
Format : application/pdf
Document ID : uuid:67d42d52-f804-7c46-a804-a675e4212d9b
Instance ID : uuid:005a9ad0-6f41-be4b-a1c9-4a3c55c3dc9f
Producer : Adobe Acrobat 8.31 Paper Capture Plug-in
Has XFA : No
Page Count : 85
Creator : Adobe Acrobat 8.31

EXIF Metadata provided by EXIF.tools

30240 90002 HP 30240A Thin LAN 3000 V Link Local Area Network Interface Controller (LANIC) Installation And Service Manual Ja

30240-90002_HP_30240A_ThinLAN_3000_V_Link_Local_Area_Network_Interface_Controller_(LANIC)_Installation_and_Service_Manual_Jan1988 30240-90002_HP_30240A_ThinLAN_3000_V_Link_Local_Area_Network_Interface_Controller_(LANIC)_Installation_and_Service_Manual_Jan198

30240-90002_HP_30240A_ThinLAN_3000_V_Link_Local_Area_Network_Interface_Controller_(LANIC)_Installation_and_Service_Manual_Jan1988 30240-90002_HP_30240A_ThinLAN_3000_V_Link_Local_Area_Network_Interface_Controller_(LANIC)_Installation_and_Service_Manual_Jan198

Navigation menu

Versions of this User Manual:

Views

Navigation