3029900_Maintenance_Training_Manual_Mar1983 3029900 Maintenance Training Manual Mar1983
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TeleVideo®
Terminal Maintenance
Training Manual
March 1983
Copyright c 1981 by TeleVideo Systems, Inc. All rights reserved. No part of this publication may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in
any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without
the prior written permission ofTeleVideo Systems, Inc., 1170 Morse Avenue, Sunnyvale, California 94086.
Disclaimer
TeleVideo Systems, Inc. makes no representations or warranties with respect to the contents hereof and
specifically disclaims any implied warranties of merchantability or fitness for any particular purpose. Further,
TeleVideo Systems, Inc. reserves the right to revise this publication and to make changes from time to time
in the content hereof without obligation of TeleVideo Systems, Inc. to notify any person of such revision
or changes.
TeleVideo Systems, Inc., 1170 Morse Avenue, Sunnyvale, California 94086
408/745-7760
3029900 . ~ Te/eVideo 5/83 Printed in U.S.A.
.....
(
;
.("
...
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I,
')
TABLE OF
CONTENTS
SECTION
·-WARRANTY, ORDERING SPARE PARTS, KEY CAPS, SPARE KITS
1
970 THE OF, SCHEMATICS, PARTS LIST
2
950 THE OF, SCHEMATICS, PARTS LIST
3
925 THE OF, SCHEMATICS, PARTS LIST
4
912/920 THE OF, SCHEMATICS, PARTS LIST
5
910/910+ THE OF, SCHEMATICS, PARTS LIST
6
VIDEO MODULE/POWER SUPPLY - -
7
970 VIDEO MODULE/POWER SUPPLY - -
8
TERMINAL TROUBLE SHOOTING GUIDE -
9
970 TERMINAL TROUBLE SHOOTING GUIDE -
10
SPECIFICATION SHEETS
11
SERVICE NOTES
12
The material contained in this handbook is the property of TeleVideo Systems, Inc_. and is not to be photocopied,
duplicated or reproduced without the express written permission of TeleVideo Systems. Inc.
(;
ORDERING SPARE PARTS
Parts are ordered directly from Terminal Spare Parts order entry
at our coporate head quarters in Sunnyvale, California.
Call
(408) 745-7760 or (800) 538-8725 (outside California). For
international customers Telex 910-399-9621, attention Terminal
Spares Order Entry. Contract customers and institutions can order
parts on a Purchase Order and be invoiced; please have Purchase
Order number and TeleVideo part number ready at time of call.
All other customers must order parts on a C.O.D. or cash-inadvance basis.
There is a S50.00 minimum on All orders (except
manuals).
For orders placed in California, add 6.5% sales tax. There is a
shipping and handling charge of SlO.OO per order.
There will be
no drop shipments, so please include the shipping and billing
addresses with your order. Shipments are made Best Way, which is
UPS or U.S. Mail.
Any special shipping requests will be
accommodated, but any extra costs incurred will be added to the
invoice.
NORTHWEST REGION
(
MIDWEST REGION
EASTERN REGIO
SOUTHEAST REGION
WESTERN REGION
SOUTHERN REGION
(
REGIONAL SALES OFFICE
WESTERN REGION
SOUTHERN REGION
505 N. TUSTIN AVE.
SUITE 253
SANTA ANA, CA. 92705
(714) 557-6095
4560 BELTLINE RD.
SUITE 424
DALLAS, TX 75293
(214) 980-9978
EASTERN REGION
SOUTHEAST REGION
202 JOHNSON RD.
SUITE A-I07
ATRUIM 1
MORRIS PLAINS, NJ 07950
(20U 267-8805
5901-C PEACHTREE-DUNWOODY RD.
SUITE 260
ATLANTA, GA. 30328
(404) 399-6464
MIDWEST REGION
NORTHWEST REGION
1170 MORSE AVE
SUNNYVALE, CA.
(408) 745-7760
94086
125 E. LAKE ST.
SUITE 203
BLOOMINGDALE, ILL. 60108
(312) 351-9350
(
October 29, 1982
TERMINAL SPARE PART PRICE LIST WITH REFERENCE TO NEW PART
NUMBERS
DESCRIPTION
OLD piN
NEW PiN
UNIT
PRICE
*****************************************************************
MANUALS
*****************************************************************
INSTAL & USER GUIDE 910
INSTAL & USER GUIDE 910PLUS
INSTAL & USER GUIDE 912/920
INSTAL & USER GUIDE 925
INSTAL & USER GUIDE 950
MAINTENANCE MANUAL 910/910PLUS
MAINTENANCE MANUAL 912/920
MAINTENANCE MANUAL 925
MAINTENANCE MANUAL 950
B300005-001
B300021-001
B300001-001
B300013-001
B300002-002
B300005-002
B300001-002
B300013-002
B300002-002
2004800
2004600
2001800
2003500
2002000
2002600
2001900
2003600
2002100
5.001
5.001
5.001
5.001
5.001
50.001
50.001
50.001
50.001
*****************************************************************
MODULES
*****************************************************************
POWER
VIDEO
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
SUPPLY MODULE
MODULE
BOARD 910
BOARD 910 GIA
BOARD 910PLUS
BOARD 910PLUS GIA
BOARD 912/920B
BOARD 912/920C
BOARD 925
BOARD 925 GIA
BOARD 950
BOARD 950 GIA
KEYBOARD ASSEMBLY 910/910PLUS
KEYBOARD ASSEMBLY 912B
KEYBOARD ASSEMBLY 912C
KEYBOARD ASSEMBLY 920B
KEYBOARD ASSEMBLY 920C
KYBD ASSEMBLY WIHOUSING 925/950
TUBE, Blw P4 12 n
TUBE, GREEN P31 12"
BC-01642
BC-01643
B900011-001
B900011-001
B900011-003
B900011-003
B900001-001
B900001-001
B900014-001
B900014-001
B900002-001
B900002-001
2195700
2195800
2014000
2014001
2014002
2014500
2009000
2009002
2015500
2015501
2009500
2009501
91. 00 I
93.001
395.001
395'.00 I
395.001
395.001
458.001
458.001
514.001
514.001
539.001
539.001
K030330-003
K030330-001
K030330-003
K030330-002
K030330-004
K030331-001
T300002-001
T300002-002
2090001
2206500
2090000
2089900
2090100
2090200
2049100
2049300
105.001
105.001
105.001
126.001
126.001
175.001
179.001
179.001
*****************************************************************
CASES
*****************************************************************
TOP CASE 910/912
TOP CASE 920
TOP CASE 925/950
TOP CASE KEYBOARD 925/950
BOTTOM CASE 910/912/920
BOTTOM CASE 925/950
BOTTOM CASE KEYBOARD 925/950
BEZEL TOP CASE 925/950
BEZEL KEYBOARD 925/950
CRT-010267
CRT-OI0334
CRT-05001
CRT-04001
CRT-OI0268
CRT-05002
CRT-04002
CRT-05003
CRT-04003
1
2151600
2153800
2141800
2204200
2151700
2141700
2199100
2141900
2198000
97.801
97.801
97.801
25.001
70.201
70.201
35.001
20.001
10.001
***************************************************.************
KITS/OPTIONS
****************************************************************
PATTERN GENERATOR (912/950 INSTALLED)
DEMO PROGRAM EPROM 910
DEMO PROGRAM EPROM 910PLUS
DEMO PROGRAM EPROM 925
DEMO PROGRAM EPROM 950
CONVERSION KIT 910
CONVERSION KIT 910PLUS
CONVERSION KIT CP/M WORDSTAR 950
CURRENT LOOP KIT 910/910PLUS
A300006-001
CURRENT LOOP KIT 925
A300006-002
MEMORY KIT 2ND PAGE 912/920
A300004-001
MEMORY KIT 2ND PAGE 925/950
A300004-002
MEMORY KIT 3RD,4TH PAGE 950
A300004-003
MEMORY KIT 2ND, 3RD, 4TH PAGE 950
SP PTS LOGIC BOARD 910
A300001-007
SP PTS LOGIC BOARD 910 G/A
SP PTS LOGIC BOARD 910PLUS
A300001-009
SP PTS LOGIC BOARD 910PLUS G/A
SP PTS LOGIC BOARD 912/920
A300001-001
SP PTS LOGIC BOARD 925
A300001-011
SP PTS LOGIC BOARD 925 G/A
SP PTS LOGIC BOARD 950
A300001-005
SP PTS LOGIC BOARD 950 G/A
~, PTS MECH 910/910PLUS
A300001-010
SP PTS MECH 912/920
A300001-003
SP PTS MECH 925/950
A300001-006
SP PTS POWER SUPPLY/VIDEO MOD
A300001-002
SP PTS ADDITIONAL PARTS
A300001-004
2122300
8000094
8000073
8000072
8000119
2169700
2169100
2187400
2131000
2131100
2001400
2001500
2001600
2231700
2000600
2225400
2000800
2225500
2000000
2001000
2225300
2000400
2233000
2000900
2000200
2000500
2000100
2000300
200.00
16.00
16.00
16.00
16.00
25.00
25.00
100.00
50.00
60.00
35.00
40.00
80.00
120.00
112.22
158.12
124.19
162.70
150.80
135.71
181. 61
183.08
218.90
60.23
66.03
54.05
134.28
202.25
****************************************************************
ELECTRICAL COMPONENTS
CAPACITORS
.****************************************************************
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CERAMIC 1.0PF lKV SPARK GAP
CERAMIC 220PF 50V
CERAMIC .01UF 16V 20%
CERAMIC 330PF 50V 20%
CERAMIC .1UF 50V 10%
DIP MICA 10PF
ELECTROLYTIC 22UF 15V
ELECTROLYTIC 22UF 50V
ELECTROLYTIC 4.4UF 35V 10%
ELECTROLYTIC 10UF 16V 20%
ELECTROLYTIC lUF 16V 10%
ELECTROLYTIC .22UF 35V
ELECTROLYTIC 100UF 10V
ELECTROLYTIC 22UF 100V
ELECTROLYTIC 2.2KUF 10V
ELECTROLYTIC 100UF 160V
ELECTROLYTIC 22UF 160V
ELECTROLYTIC 220UF 16V
ELECTROLYTIC 3.3KUF 35J
ELECTROLYTIC 4.7KUF 16V
ELECTROLYTIC 4. 7UF 16V
ELECTROLYTIC 470 35V
C900100-012
CC-50221SL
C900100-001
C900100-003
C900100-008
C600100-001
C700100-001
C700100-003
C700100-008
C700100-010
C700100-013
C700100-016
CE-10107S
CE-I0226SH
CE-I0228S
CE-16107SH
CE-16226SH
CE-16227S
\,.,t,-.:L':l338S
CE-35478S
CM-16475
CT-35338S
2
2030900
2195900
2028700
2029100
2030100
2024100
2025700
2026100
2026900
2027300
2027900
2028500
2196000
2196100
2196200
2196300
2196400
2199300
2196500
2196600
2196700
2198200
2.04
.72
.72
.72
.72
.72
.72
.72
2.08
.72
1. 08
.72
.72
.72
2.28
6.60
1.27
.72
6.91
6.56
.72
1.68
(l
(
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
C600100-002
C600100-004
C600100-005
C600100-006
C600100-007
C600100-008
C900100-002
C900100-004
C900100-005
C900100-007
C900100-009
C900100-010
CM-20682H
CM-50102
CM-50103
CM-50473
CM-50474
CM-60104H
CO-40473H
C800100-001
C700100-002
C700100-005
C700100-009
C700100-011
CT-35334
CN-152065
MICA 20PF
MICA 100PF 50V 5%
MICA 47PF 50V 5%
MICA 150PF 500V 1%
MICA 330PF 500V 5%
MICA 390PF 500V 5%
MONOLYTHIC.OIUF 50V 10%
MONOLYTHIC 330PF 100V 20%
MONOLYTHIC 47PF 100V 5%
MONOLYTHIC 68PF lKV 20%
MONOLYTHIC .039UF 50V 10%
MONOLYTHIC .039UF 50V 5%
MYLAR .0068UF 200V
MYLAR .001UF 50V
MYLAR .01UF 50V
MYLAR .047UF 50V
MYLAR .47UF 50V
MYLAR .1UF 600V
MYLAR .047UF 400V
RADIAL LEAD lUF 15V
TANTALUM .68UF 50V
TANTALUM 3.3UF 50V 10%
TANTALUM 10UF 25V 10%
TANTALUM 4.7UF 16V 10%
TANTALUM .33UF 35V
NON POLARIZED .20UF 50V
2024300
2024700
2024900
2025100
2025300
2025500
2028900
2029300
2029500
2029900
2030300
2030500
2196800
2196900
2197000
2197100
2197200
2197300
2197500
2027901
2025900
2026300
2027100
2027500
2198100
2197400
.72
.72
.72
.72
.95
1.07
.72
.72
1.08
.72
.72
1.08
.72
.72
.72
.72
1.44
1.35
1.86
.72
1.74
2.40
1. 98
.96
1.20
4.63
****************************************************************
DIODES - REGULATORS - TRANSISTORS
*******************************************************~********
DIODE ZENER IN759A/RD12EB
DIODE IN914
DIODE IN920/KDS8513A
DIODE IN4001
DIODE IN4004/DS-130TBDIODE IN5391/DS135D
DIODE DSA17C/MR500
DIODE DS18/IDS135D
DIODE DSl13A/MRI-I000
DIODE LEC MV55A RED
DIODE P6KE
REGULATOR LAS1512
REGULATOR LAS16CB
REGULATOR LAS1605
REGULATOR LAS1812
REGULATOR 78M05
TRANSISTOR 2N2219A
TRANSISTOR 2N2907A
TRANSISTOR 2N3019
TRANSISTOR 2N3906/2SA495
TRANSISTOR 2N4401/2SCl166
TRANSISTOR 2N5551/2SC983
TRANSISTOR 2N6121/2SCl173
TRANSISTOR 2N6124/2SA473
TRANSISTOR 2SC2233/MJE13006
TRANSISTOR KTC 1627A/MPSA06
TRANSISTOR 2N3904/KTC1815
SD-I0254
S360100-000
SD-I0258
S360100-001
SD-I0257
SD-01251
SD-01253
SD-01252
SD-01255
S360100-003
S360100-002
SI-0551
R600005-001
R600004-003
SI-01553
R600000-001
S350100-000
S350100-003
S350100-002
ST-I0351
S350100-001
S350100-009
ST-01353
ST-01354
S350100-010
S350100-007
S350100-006
3
2201600
2047500
2201800
2047700
2202200
2200600
2201500
2201400
2201700
2048100
2047900
2202500
2126900
2126800
2202400
2126100
2045300
2045900
2045700
2042200
2045500
2047100
2199700
2202100
2047300
2046700
2046500
1.82
.72
.90
.91
1.00
.72
1.94
.72
6.29
3.00
4.20
35.00
18.60
23.70
35.00
3.96
3.60
.97
2.64
.91
2.02
2.59
4.00
4.28
22.80
2.07
4.50
************************************~~~***********.**************
FIRMWARE
*****************************************************************
SYSTEM EPROM 910
SYSTEM ROM 910
SYSTEM EPROM 910PLUS
SYSTEM ROM 912/920B (A49B1)
SYSTEM ROM 912/920C (A49C1)
SYSTEM EPROM 925
SYSTEM EPROM 925
SYSTEM ROM 950 (A41)
SYSTEM ROM 950 (A42)
CHAR GEN EPROM 910/910PLUS
CHAR GEN ROM 910/910PLUS
CHAR GEN ROM 912/920 (A3-2)
CHAR GEN EPROM 925
CHAR GEN ROM 925
CHAR GEN ROM 950 (A32)
CHAR GEN ROM 950 (A33)
KYBD EPROM 910/910PLUS
KYBD ENCDR 910/910PLUS
KYBD ENCDR 910/910PLUS
KYBD ROM 925/950
(U6)
I800000-020
I800000-015
I800000-040
1740010-049
I740010-050
I800000-033
I800000-031
I800000-001
I800000-007
I800000-021
I800000-016
I740010-053
I800000-021
I800000-016
I800000-003
I800000-002
I800000-019
I800000-020
I740011-013
I800000-009
8000020
8000015
8000040
2033800
2034000
8000033
8000031
8000001
8000007
8000021
8000016
2034600
8000021
8000016
8000003
8000002
8000019
2053200
2051800
8000009
37.50
18.90
25.00
25.80
25.80
37.50
37.50
18.90
18.90
37.50
18.90
14.94
37.50
18.901
18.901
18.901
21. 00 I
22.501
22.501
37.501
(
*****************************************************************
INTERGRATED CIRCUITS
*****************************************************************
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
lC
IC
lC
IC
lC
lC
lC
lC
lC
lC
IC
IC
IC
IC
IC
1740010-000
1740010-001
1740010-002
1740010-003
1740010-004
1740010-005
1740010-006
I740010-007
I740010-008
1740010-009
I740010-010
I740010-011
1740010-012
1740010-013
1740010-014
I740010-015
1740010-016
1740010-017
1740010-018
I740010-019
1740010-020
1740010-021
1740010-022
1740010-023
1740010-024
1740010-025
1740010-026
I740010-027
I740010-029
1740010-031
74S00
74LSOO
74LS03
74S04
74LS04
74LS05
74LS08
74LS10
74SL20
74LS32
74LS42
74LS51
74S74
74LS74
74LS86
74LS109
74LS139
74LS157
74LS163
74LS166
74LS173
74LS174
74LS253
74LS367
74LS373
74LS374
75188N/1488
75189AN/1489
TILl17
NE555
4
2024000
2024200
2024400
2024600
2024800
2025000
2025200
2025400
2025600
2025800
2026000
2026200
2026400
2026600
2026800
2027000
2027200
2027400
2027600
2027800
2028000
2028200
2028400
2028600
2028800
2029000
2029200
2029400
2029800
2030200
2.20
1. 72
1.72
2.41
1. 80
1.80
1. 80
1. 80
1. 72
1. 86
2.55
1.80
3.58
1. 80
2.07
2.00
3.181
2.761
4.561
5.041
4.141
3.181
3.241
2.761
3.481
3.481
4.141
4.141
4.481
2.581
(
(
.
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
Ie
IC
Ie
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
1740010-032
1740010-033
1740010-034
1740010"'035
I740010-Q36
1740010-051
1740010-054
1740010-055
1740010-057
1740010-059
1740010-061
1740010-:-063
1740010-068
1740010-069
1740010-070
1740010-074
1740010-076
1740010-080
1740010-081
1740010-084
1740010-086
1740010-088
1740010-089
1740010-096
1740010-097
1740010-099
1740010-105
1740011-000
1740011-002
1740011-003
1740011-004
1740011-005
1740011-007
1740011-008
1740011-009
1740011-010
1740011-012
1740011-017
1740011-019
1740011-018
DP8304
AMD2111-4A
2502HP
TMS9927/5027
P8035
HIIG3
7406
4N38
7414
2114
74LS245/N8T245N
74LS191
74LS273
74S240
74LS175
74S32/629
74LSl1
93S16PC
74LS138
74LS02
74LS241
AM26LS31
AM26LS32
74LS240
74LS244
74S174
74LS14
6116
6502A
6545
6551 IMHz
6552A
Z80A SIO/2
Z80A CTC
Z80A CPU
Z80A DMA
64K RAM DYN
68B045 2 MHz
SY6551A-l 2MHz
SY6545A-l 2MHz
910/910 PLUS GATE ARRAY
925 GATE ARRAY
950 GATE ARRAY A
950 GATE ARRAY B
2030400
2030600
2030800
2031000
2031200
2034200
2034800
2035000
2035400
2035800
2036200
2036600
2037600
2037800
2038000
2038800
2040000
2040800
2041000
2041600
2042000
2042400
2042600
2044000
2044200
2044600
2045800
2049200
2049600
2049800
2155700
2050200
2050600
2050800
2051000
2051200
2051600
2052600
2053000
2052800
2057400
2057400
2057600
2057800
17.59
13.32
15.52
81.76
41.05
3.45
2.05
4.32
1. 92
9.75
5.76
2.70
3.48
8.82
1. 74
1. 80
1.14
6.60
1.68
1.14
3.54
7.92
7.92
3.54
. 5.52
3.96
1. 44
40.00
28.94
66.24
28.80
27.21
58.00
16.80
21.18
56.76
83.76
31.50
24.00
50.10
42.60
42.60
23.88
23.88
****************************************************************
RESISTORS & POTENTIOMETERS
****************************************************************
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
CF
CF
CF
CF
CF
CF
CF
CF
CF
CF
68 OHM 1/4W 5%
270 OHM 1/4W 5%
330 OHM 1/4W 5%
470 OHM 1/4W 5%
510 OHM 1/4W 5%
lK OHM 1/4W 5%
1.8K OHM 1/4W 5%
3.3K OHM 1/4W 5%
4.7K OHM 1/4W 5%
180 OHM 1/4W 5%
R514000-001
R514000-002
R514000-003
R514000-004
R514000-005
R514000-006
R514000-007
R514000-009
R514000-011
R514000-012
5
2051100
2051300
2051500
2051700
2051900
2052100
2052300
2052700
2053100
2053300
.72
.72
.72
.72
.72
.72
.72
.72
.72
.72
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
POT
POT
POT
POT
POT
CF 1M OHM 1/4W 5%
CF 750 OHM 1/4W 5%
CF 1.2K OHM 1/4W 5%
CF lOOK OHM 1/4W 5%
CF 51K OHM 1/4W 5%
CF 22 OHM 1/4W 5%
CF 47K OHM 1/4W 5%
CF 150 OHM 1/4W 5%
CF 10K OHM 1/4W 5%
CF 200 OHM 1/4W 5%
CF 33 OHM 1/4W 5%
CF 100 OHM 1/4W 1%
CF 51 OHM 1/4W 5%
CF 22K OHM 1/4W 5%
CF 27K OHM 1/4W 5%
CF 47 OHM 1/4W 5%
CF 2.7K OHM 1/4W 5%
CF 91 OHM 1/4W 5%
CF 2.2K OHM 1/4W 5%
CF 3.9K OHM 1/4W 5%
CF 6.8K OHM 1. 4W 5%
CF 30K OHM 1/4W 5%
CF 56K OHM 1/4W 5%
PACK lK OHM SIP 10%
PACK 6.2K OHM SIP 10%
PACK 10K OHM SIP 5%
PACK 4.7K OHM SIP 10%
PACK lK OHM SIP 5%
CF 510 OHM 1/2W 5%
CF 220 OHM 1/2W 5%
CF 390 OHM 1/2W 5%
CF 820 OHM 1/2W 5%
CF 1.5K OHM 1/2W 5%
CF 10K OHM 1/2W 5%
CF 2.2M OHM 1/2W 5%
WW 0.6 OHM 2W
BRIGHTNESS & VERTICAL HEIGHT
VERTICAL LINEARITY
VIDEO B +
FOCUS
CONTRAST
R514000-014
R514000-015
R514000-016
R514000-017
R514000-018
R514000-024
R514000-025
R514000-026
R514000-027
R514000-028
R514000-029
R514000-031
R514000-037
R514000-038
R514000-043
R514000-045
R514000-048
R514000-049
R514000-050
R514000-051
R514000-052
R514000-053
R514000-054
R514000-100
R514000-101
R514000-103
R514000-104
R514000-111
R514003-000
R514003-001
R514003-002
R514003-003
R514003-004
R514003-005
R514003-006
RC02608J
RF-07104B
RF-07202B
RF-07473B
RV-24205B
RV-24501B
2031500
2031700
2031900
2032100
2032300
2033500
2033700
2033900
2034100
2034300
2034500
2034900
2036100
2036300
2037300
2037700
2038300
2038500
2038700
2177400
2039100
2039300
2039500
2040500
2040700
2041100
2041300
2042700
2045100
2186000
2176600
2186200
2186300
2186400
2186500
2177100
2177700
2177800
2177900
2180100
2180200
.72
.72
.72
.72
.72
.72
.72
.72
.72
.72
.72
.72
.72
.72
.72
.72
.72
.72
.72
.72
.72
.72
.72
1.58
1. 73
2.04
1.20
3.00
.72
.72
.72
.72
.72
.72
.72
.72
1.06
1.06
1. 06
3.86
2.77
(J
(
****************************************************************
TRANSFORMERS/COILS
****************************************************************
TRANSFORMER; FLYBACK KFS-00093
TRANSFORMER; HORIZ DR HDT19
TRANSFORMER; POWER W/CON CRT858
COIL INDUCTOR 27UH .3PIE
COIL LINEARITY ADJUSTABLE
COIL LINEARITY NON ADJUSTABLE
COIL DEFLECTION YOKE W/CONN
KYS-00060
IC-01467
IC-01466
IC .... 01465
IC-01464
IC-01463
IC-01462
IC-01461
2201300
2201200
2201100
2201000
2213600
2200900
2200800·
55.48
4.08
129.24
1.20
7.20
5.24
31.63
()
6
****************************************************************
MISCELLANEOUS
****************************************************************
1740010-090
M200401-001
M200401-002
M200401-003
M200401-004
M200401-006
I740010-056
FC12503A
M200104-001
CRYSTAL 16MHZ OSC
CRYSTAL 23.814 MHZ (912/920)
CRYSTAL S.7143MHZ
CRYSTAL 1.8432 MHZ
CRYSTAL 8.0000 MHZ
CRYSTAL 13.6080 MHZ
CRYSTAL 23.814 Kll14A (950)
FUSE, 3A 125V 2SEA.
FUSE, lA 250V 25EA.
POWER ADAPTER PATTERN GEN
THERMISTER, SDT-I00
3312453
2042800
2098600
2098601
2098602
2098603
2098605
2035200
2223700
2223300
2176300
2180300
27.00
11.11
7.85
8.16
4.80
8.70
37.08
11. 85
11. 85
41. 40
1. 44
****************************************************************
MECHANICAL COMPONENTS
KEYCAPS
****************************************************************
KEY CAP
KEYCAP
KEYCAP
KEYCAP
KEYCAP
KEYCAP
KEYCAP
KEYCAP
KEYCAP
KEYCAP
KEYCAP
KEYCAP
KEY CAP
KEYCAP
KEYCAP
KEYCAP
KEYCAP
KEYCAP
KEYCAP
KEY CAP
KEYCAP
KEYCAP
KEYCAP
KEYCAP
KEYCAP
KEY CAP
KEYCAP
KEYCAP
KEYCAP
KEYCAP
KEYCAP
KEY CAP
KEYCAP
KEY CAP
KEYCAP
KEYCAP
DG lXl
DG lXl SCULP
DG lXl BLANK (25ea)*
DG lXl SCULP BLANK
o (25ea)*
DG lXl SCULP BLANK -7 (2Sea)*
DG lXl SCULP BLANK +7 (25ea)*
DG lXl SCULP BLANK +14 (25ea)*
DG lXl-1/2
DG lXl-1/2 SCULP
DG lXl-1/2 BLANK (2Sea)
DG lXl-1/2 SCULP BLANK +7 (25ea)*
DG lX8
DG lX8 SCULP
LG lXl
LG lXl SCULP
LG lXl BLANK (25ea)*
LG IX! SCULP BLANK 0 (25ea)*
LG IX! SCULP BLANK -7 (25ea)*
LG IX! LOW PRO
LG lXl LOW PRO SCULP
LG lXl LOW PRO BLANK (25ea)*
LG IX! LOW PRO SCULP BLANK (25ea)*
LG lXl-1/4
LG lXl-1/4 SCULP
LG lXI-1/4 BLANK (25ea)*
LG lXI-1/4 SCULP BLANK +7 (2Sea)*
LG lXI-1/2
LG lXl-1/2 SCULP
LG lXl-1/2 BLANK (25ea)*
LG lXl-1/2 SCULP BLANK -7 (2Sea)*
LG "L" RETURN
LG "L" BLANK (RETURN)
LG "L" SCULP RETURN
LG "L" SCULP BLANK (RETURN)
BLACK lXl
BLACK lXl BLANK (25ea)*
7
20XXXXX
20XXXXX
2222100
2231600
2231300
2231400
2231500
2072XXX
2084XXX
2222200
2231200
2077400
2089700
207XXXX
208XXXX
2222400
2231100
2231000
207XXXX
2089XXX
2222500
2223100
2077300
2089600
2222600
2230900
2072XXX
2084XXX
2222300
2230800
2077100
2077101
2089400
2161602
20XXXXX
2053700
.72
.72
13.50
22.50
22.50
22.50
22.50
1. 52
2.56
33.00
33.00
1. 98
3.00
.72
.72
15.00
22.50
22.50
.72
.72
13.50
22.50
1. 52
2.44
31. 50
28.50
1. 52
2.56
33.00
33.00
1. 86
3.90
2.76
3.90
.72
22.50
KEYCAP
KEYCAP
KEY CAP
KEYCAP
KEYCAP
KEY CAP
KEYCAP
KEYCAP
KEYCAP
KEYCAP
KEY CAP
KEYCAP
KEYCAP
KEYCAP
20'63XXX
2221800
2077500
206XXXX
2221900
2063700
2222000
2202700
2090300
2090500
2090400
2090600
2090900
2091000
BLACK lXl-l/2
BLACK lXl-1/2 BLANK (25ea)*
BLACK lX8
TAN lXl
TAN lXl BLANK (25ea)*
TAN lXl-1/2
TAN lXl-1/2 BLANK (25ea)*
SET 910/910PLUS
SET 912B
SET 912C
SET 920B
SET 920C
SET 925/950
SET 925/950 SCULP
1. 80
30.00
2.70
.72
18.00
1. 80
37.50
52.44
52.44
52.44
63.24
56.58
79.29
59.10
(
*BLANK KEYCAPS SOLD IN QTY 25
****************************************************************
SWITCHES
****************************************************************
KEYSWITCH
KEYSWITCH - ALPHA LOCK
SWITCH TOP ADJ 7 POS DIP
SWITCH TOP ADJ 10 POS DIP
SWITCH SIDE ADJ 10 POS DIP
PUSHBUTTON SWITCH
SWITCH POWER ON/OFF SPST
SWITCH POWER SELECT, DPDT
KS-123456
KS-123457
M200101-001
M200101-002
M200101-003
M200101-004
M200107-001
M200108-001
2199400
2199500
2174200
2181000
2096800
2096900
2097300
209740()
3.60
6.22
3.84
3.90
5.70
'17.88
7.89
6.92
****************************************************************
MISCELLANEOUS
****************************************************************
CABLE ASY KEYBOARD 912/920
B510003-003 2005900
25.08
CABLE ASY KEYBOARD 910
B510003-009 2005901
25.08
CABLE ASY KEYBOARD 925/950
B510000-001 2005700
10.92
CABLE ASY MODEM RJl1
B510002-001 2135900
17.34
CONNECTOR 2 PIN RT ANGLE
M200601-006 2098703
.72
CONNECTOR 2 PIN STR WAF
M200603-002 2098800
.72
CONNECTOR 5 PIN STR WAF
M200603-005 2098802
.72
CONNECTOR 40 PIN HDR STRAIGHT
M200209-004 2098107
7.50
CONNECTOR KEYBOARD PCB 26PIN
M200601-004 2098701
4.21
CONNECTOR KEYBOARD RJ11
M200202-001 2097900
2.22
CONNECTOR RIGHT ANGLE RS232
M200201-001 2097800
10.62
CONNECTOR STRAIGHT RS232
M200201-005 2174300
20.00
CORD, POWER 6'3" 3 PRONG CONN
2109000
19.87
E-RING MINIMUM 25
CRT-010174
2223600
5.70
EQL ASY SPACE BAR DAMPER
K030500-003 2096300
.72
EQL ASY SPACE BAR, GUIDE STEM
K030500-002 2096200
.90
EQL ASY SPACE BAR, KEY GUIDE
K030500-001 2091200
1. 80
EQL ASY SPACE BAR KEYGUIDE ARM
K030500-004 2096400
3.60
FUSE HOLDER, CLIP
4301512
2180400
.72
FUSE HOLDER, PANEL MOUNT
M200106-001 2097200
21. 00
INSULATION PAD TRANSISTOR
M200100-002 2180800
.72
INSULATOR PAD CRYSTAL
M220000-001 2099700
1. 02
KNOB, CONTRAST
CRT-010124
2153000
.72
KEYSTOPPERS 100ea
KS123458
2223800
12.00
8
(
(
PIVOTSHAFT MINIMUM 25
SHROUD CONN 910/912/920
SHROUD CONN MODEM 910/912/920
SHROUD CONN 925/950
SHROUD CONN MODEM 925/950
SOCKET IC 14 PIN
SOCKET IC 16 PIN
SOCKET IC 18 PIN
SOCKET IC 24 PIN
SOCKET IC 28 PIN
SOCKET IC 40 PIN
SOCKET Ie 16 PIN LOW PROFILE
CRT-OI0138
M400011-001
M400011-002
M400008-001
M400008-002
M200301-004
M200301-007
M200301-001
M200301-002
M200301-005
M200301-003
M200303-003
9
2197800
2100200
2100201
2100100
2100103
2098403
2098405
2098400
2098401
2098404
2098402
2174601
4.68
10.00
20.00
10.00
20.00
.78
.72
.83
1.10
1. 32
1. 80
6.00
(
(J
PART LIST: KEYCAPS
I
970 DETACHABLE KEYBOARD
MODEL:
DESCRIPTION
DATE_12/09/82 _ _
PAGE_1 __ OF __ 4_
PART NUMBER
SCULPTURED/MATTED
PRINTED
BLANK
I
I PRINTED
BLANK
I COMMENTS I NOTES
------------------------------------------------------------------------------------------------o DEGREES
(1)
-----1X1 LIGHT GREY BLANK
2161600
n
lX1
lX1
1X1
1X1
1X1
1X1
1Xl
1X1
1X1
1X1
1X1
1X1
1X1
lXl
1X1
1X1
1X1
lX1
1X1
1X1
1X1
1X1
1X1
1X1
1X1
1X1
1X1
1X1
1X1
lXl
1X1
1Xl
lXl
1Xl
lXl
LG SETUP/NOSCROLL
LIGHT GREY F1
LIGHT GREY F2
LIGHT GREY F3
LIGHT GREY F4
LIGHT GREY F5
LIGHT GREY F6
LIGHT GREY F7
LIGHT GREY F8
LIGHT GREY F9
LIGHT GREY FlO
LIGHT GREY F11
LIGHT GREY F12
LIGHT GREY F13
LIGHT GREY F14
LIGHT GREY F15
LIGHT GREY F16
LG CHAR INSERT
LG CHAR DELETE
LG LINE INSERT
LG LINE DELETE
DARK GREY BLANK
DG LOC ESC/ESC
DARK GREY 1/1
DARK GREY 2/@
DARK GREY 3/#
DARK GREY 4/$
DARK GREY 5/%
DARK GREY 6/
DARK GREY 7/&
DARK GREY 8/*
DARK GREY 9/(
DARK GREY 0/)
DARK GREY -/
DARK GREY =/+
2088700
2085000
2085100
2085200
2085300
2085400
2085500
2085600
2085700
2085800
2085900
2086000
2087600
2087700
2087900
2087800
2088000
2086100
2086200
2086300
2086400
------2084200
2077800
2077900
2078000
2078100
2078200
2078300
2078400
2078500
2078600
2078700
2078800
2078900
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161700
0
n
0
n
0
n
0
n
0
n
0
n
0
n
0
n
0
n
0
n
0
n
0
n
0
n
0
n
0
n
0
n
0
n
0
n
0
n
0
n
0
+14 DEGREES
n
+14
n
(2)
+14
n
+14
+14
"
+14
"
+14
"
+14
"
·n
+14
n
+14
n
+14
n
+14
n
+14
n
+14
v
~
PARTLIS'1': KEYCAPS
MODEL: 970 DETACHABLE KEYBOARD
DESCRIPTION
lXl DARK GREY '1lXl DARK GREY \/1
lXl DG BACK SPACE
lXI-1/2 DARK GREY TAB
lXl DARK GREY Q
lXl DARK GREY W
lXl DARK GREY E
lXl DARK GREY R
lXl DARK GREY '1'
lXl DARK GREY Y
lXl DARK GREY U
lXl DARK GREY I
lXl DARK GREY 0
lXl DARK GREY P
lXl DARK GREY[/]
lXl-I/2 DG LINE FEED
lXI-1/4 LG-CLEAR SPACE
lXl LIGHT GREY CONTROL I
lXl DARK GREY ALPHA LOCK I
lXl DARK GREY A
I
lXl DARK GREY S
I
lXl DARK GREY D
I
lXl DARK GREY F
I
lXl DARK GREY G
IX 1 DARK GREY H
lXl DARK GREY J
lXl DARK GREY K
lXl DARK GREY L
lXl DARK GREY ;/:
lXl DARK GREY '/R
LIGHT GREY RLII! RETURN
lXl LIGHT GREY BREAK
lXl DARK GREY BACK TAB
lXl-I/2 LG SHIFT
lXl DARK GREY Z
DATE _ _12/09/82_ _
PAGE _2_ OF _4_
PART NUMBER
SCULPTURED/MATTED KEYCAP
PRINTED
I BLANK
2230100
2079100
2079200
2084500
2080600
2080700
2080800
2080900
2081000
2081100
2081200
2081300
2081400
2081500
2081600
2084400
2088400
2086900
2081800
2081900
2082000
2082100
2082200
2082300
2082400
2082500
2082600
2082700
2082800
2082900
2089400
2087000
2081700
2084700
2083000
~
2161700
2161700
2161700
2161801
2161800
2161800
2161800
2161800
2161800
2161800
2161800
2161800
2161800
2161800
2161800
2161801
2161802
2161600
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161602
2162101
2161900
2161902
2161900
PRINTED
BLANK
COMMENTS I NOTES
R
+14
R
+14
R
+14
R
+7
R
+7
II
+7
R
+7
R
+7
+7 DEGREES
R
+7
R
+7
II
+7
II
+7
R
+7
II
+7
R
+7
R
+7
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
-7
-7
-7
DEGREES
II
"
II
III
R
II
"
II
II
II
II
II
II
II
II
l1li
II
PARTLIST: KEYCAPS
970 DETACHABLE KEYBOARD
MODEL:
DESCRIPTION
DATE_12/09/82 _ _
PART NUMBER
I SCULPTURED/MATTED KEYCAPI
I PRINTED
I BLANK
PRINTED
PAGE __ 3 __ OF __ 4___
BLANK
I COMMENTS I NOTES
--------------------------------------------------------------------------------------------------lXl
lXl
lXl
lXl
lXl
lXl
lXl
lXl
lXl
lXl
lXl
lXl
lXl
lX8
lXl
lXl
-IXl
lXl
lXl
lXl
lXl
lXl
lXl
lXl
lXl
lXl
lXl
lXl
lXl
lX2
lXl
lXl
lXl
lXl
DARK GREY X
DARK GREY C
DARK GREY V
DARK GREY B
DARK GREY N
DARK GREY M
DARK GREY ,1<
DARK GREY .1>
DARK GREY II?
DARK GREY {I}
LIGHT GREY DEL
(LP)
LG PRINT
LG FUNCTION (LP)
DARK GREY SPACE BAR
LG HOME (LP)
LG CURSER (LP)
LG LINE ERASE
LG PAGE ERASE
LIGHT GREY SEND
DARK GREY 7
DARK GREY 8
DARK GREY 9
DARK GREY 4
DARK GREY 5
DARK GREY 6
DARK GREY 1
DARK GREY 2
DARK GREY 3
DARK GREY ,
DARK GREY 0
DARK GREY
DARK GREY DARK GREY PAGE
DARK GREY CE
2083100
2083200
2083300
2083400
2083500
2083600
2083700
2083800
2083900
2084000
2087100
2089300
2089000
2089700
2089100
2140500
2086500
2086600
2088500
2079900
2080000
2080100
2079600
2079700
2079800
2079300
2079400
2079500
2080400
2088100
2080500
2080300
2087200
2087300
2161900
2161900
2161900
2161900
2161900
2161900
2161900
2161900
2161900
2161900
2161901
2162101
2162101
I
I
I
I
I
-------
2162101
2162101
2161600
2161600
2161600
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2251300
2161601
2161601
2161601
2161601
J
I
I
J
I
I
I
I
I
-7
-7
-7
-7
-7
-7
-7
-7
-7
-7
-7
0
0
0
0
0
0
0
0
0
0
0
0
0,
0
0
0
0
0
0
0
0
0
0
It
It
It
It
It
It
It
It
It
DEGREES
It
-tI
It
(3)
(3)
It
It
It
It
It
It
It
It
It
It
It
It
It
It
It
It
It
It
It
It
It
(3)
(3)
(4)
v
v
PART LIST: KEYCAPS
MODEL: 970 DETACHABLE KEYBOARD
DESCRIPTION
lXl
2xl
2xl
lXl
DARK GREY RESET
LIGHT GREY TAB
LIGHT GREY ENTER
DARK GREY 00
DATE_12/09/82_ _
PAGE_4_0F_4_ _
PART NUMBER
SCULPTURED/MATTED KEYCAPI
PRINTED
I BLANK
I
2087400
2088200
2088300
2180700
~
PRINTED
2161601
2251400
2251400
2161601
NOTES
1) DEGREES REFER TO SCULPTURED/MATTED KEYCAPS ONLY
2) SLASH BETWEEN TWO CHARACTERS (ie: 1/1) FOR CLARITY AND IS NOT
PRINTED ON KEYCAP
3) LOW PROFILE KEYS
4) SAME KEY CAN BE USED FOR ALL FOUR CURSER POSITIONS
BLANK
COMMENTS
o DEGREES
o n
o n
o n
NOTES
PART LIST: KEYCAPS
925 DETACHABLE KEYBOARD
MODEL:
950 DETACHABLE KEYBOARD
STEPPED
PRINTED
DESCRIPTION
DATE_11/15/82_
PAGE __1 __0F __3 __
~ART NUM~~R
KEYCAPS
I BLANK
I
I
SCULPTURED/MATTED KEYCAPSI
I COMMENTS/NOTES
PRINTED
BLANK
I
-------------------------------------------------------------------------------------------------1X1 LIGHT GREY BLANK
1X1 LG NO SCROLL/SETUP
1X1 LIGHT GREY F1
1X1 LIGHT GREY F2
1X1 LIGHT GREY F3
1X1 LIGHT GREY F4
1X1 LIGHT GREY F5
1X1 LIGHT GREY F6
1X1 LIGHT GREY F7
1X1 LIGHT GREY F8
1X1 LIGHT GREY F9
1X1 LIGHT GREY FlO
1X1 LIGHT GREY F11
1X1 LG CHAR INSERT
1X1 LG CHAR DELETE
1X1 LG LINE INSERT
1X1 LG LINE DELETE
1X1 DARK GREY BLANK
1X1 DG ESC/LOC ESC
1X1 DARK GREY 1/1
1X1 DARK GREY 2/@
1X1 DARK GREY 3/#
1X1 DARK GREY 4/$
1X1 DARK GREY 5/%
1X1 DARK GREY 6/
1X1 DARK GREY 7/&
1X1 DARK GREY 8/*
1X1 DARK GREY 9/(
1X1 DARK GREY 0/)
1Xl DARK GREY -/_
lXl DARK GREY =/+
lXl DARK GREY '/1X1 DARK GREY \/1
1X1 DG BACK SPACE
1X1-1/2 DARK GREY TAB
1X1 DARK GREY Q
1X1 DARK GREY W
1X1 DARK GREY E
1X1 DARK GREY R
A
------2075500
2073100
2073200
2073300
2073400
2073500
2073600
2073700
2073800
2073900
2074000
2074100
2074200
2074300
2074400
2074500
-------
2072300
2065900
2066000
2066100
2066200
2066300
2066400
2066500
2066600
2066700
2066800
2066900
2067000
2067100
2067200
2067300
2072600
2068700
2068800
2068900
2069000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2072400
2065800
2065800
2065800
2065800
-------
2088700
2085000
2085100
2085200
2085300
2085400
2085500
2085600
2085700
2085800
2085900
2086000
2086100
2086200
2086300
2086400
------2084200
2077800
2077900
2078000
2078100
2078200
2078300
2078400
2078500
2078600
2078700
2078800
2078900
2079000
2079100
2079200
2084500
2080600·
2080700
2080800
2080900
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161600
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161700
2161801
2161800
2161800
2161800
2161800
o DEGREES
(1)
0
"
0
"
0
"
II
0
0
"
0
"
0
"
II
0
II
0
0
"
0
"
0
"
0
"
0
"II
0
0
"
+14 DEGREES
+14 "
(2)
+14 II
+14 "
+14 "
+14 II
+14 "
+14 "
+14 "
+14 "
+14 "
+14 "
+14 "
+14 "
+14 II
+14 II
+14 "
+7
"
+7
"
+7
"
n
+7
n
+7
v
~
PA'-R'. ,1ST: KEYCAPS
925 DETACHABLE KEYBOARD
MODEL:
950 DETACHABLE KEYBOARD
DESCRIPTION
I STEPPED
I PRINTED
~
eARl NUM13
KEYCAPS
I BLANK
DA'j'F._11/15/82_
PAGE __ 2__0F __3 __
SCULPTUREDIMATTED KEYCAPSI
PRINTED
I COMMENTSINOTES
I BLANK
------------------------------------------------------------------------------------------------
1X1
1X1
1X1
1X1
1X1
1X1
1X1
DARK
DARK
DARK
DARK
DARK
DARK
DARK
GREY T
GREY Y
GREY U
GREY I
GREY 0
GREY P
GREY [/1
1Xl-1/2 DG LINE FEED
1Xl-1/4 LG CLEAR SPACE
1X1 LIGHT GREY CTRL
1X1 DARK GREY ALPHA LOCK
1X1 DARK GREY A
1X1 DARK GREY S
1X1 DARK GREY D
1X1 DARK GREY F
1X1 DARK GREY G
1X1 DARK GREY H
1X1 DARK GREY J
1X1 DARK GREY K
1X1 DARK GREY L
1X1 DARK GREY ;1:
1X1 DARK GREY 'I"
LIGHT GREY "L" RETURN
1X1 LIGHT GREY BREAK
1X1 DARK GREY BACK TAB
1Xl-1/2 LG SHIFT
1X1 DARK GREY Z
1X1 DARK GREY X
1X1 DARK GREY C
1X1 DARK GREY V
1X1 DARK GREY B
1X1 DARK GREY N
1X1 DARK GREY M
1X1 DARK GREY ,1<
1X1 DARK GREY .1>
1X1 DARK GREY II?
2069100
2069200
2069300
2069400
2069500
2069600
2069700
2072500
2077300
2075000
2069900
2070000
2070100
2070200
2070300
2070400
2070500
2070600
2070700
2070800
2070900
2071000
2077100
2075100
2069800
2072800
2071100
2071200
2071300
2071400
2071500
2071600
2071700
2071800
2071900
2072000
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2072400
2077200
2073000
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2077101
2073000
2065800
2072700
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2081000
2081100
2081200
2081300
2081400
2081500
2081600
2084400
2(789600
2086900
2081800
2081900
2082000
2082100
2082200
2082300
2082400
2082500
2082600
2082700
2082800
2082900
2089400
2087000
2081700
2084700
2083000
2083100
2083200
2083300
2083400
2083500
2083600
2083700
2083800
2083900
2161800
2161800
2161800
2161800
2161800
2161800
2161800
2161801
2161802
2161600
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161602
2161600
2161900
2161902
2161900
2161900
2161900
2161900
2161900
2161900
2161900
2161900
2161900
2161900
+7 DEGREES
+7
"
+7
"
+7
"
II
+7
II
+7
+7
"
+7
"n
+7
o DEGREES
II
0
II
0
0
"
0
"
II
0
II
0
0
"
0
"
0
"II
0
II
0
0
"
0
"
II
0
II
-7
-7
"
-7
"
-7
"
-7
"
II
-7
II
-7
-7
"
-7
"
II
-7
-7
"
II
-7
PJ...
LIST: KEYCAPS
MODEL:
925 DETACHABLE KEYBOARD
950 DETACHABLE KEYBOARD
DESCRIPTION
lXl DARK GREY {I}
lXl LIGHT GREY DEL
lXl LG PRINT eLP)
lXl LG FUNCT (LP)
lX8 DARK GREY SPACE BAR
1X1 LG HOME
(LP)
1X1 LG CURSER (LP)
1X1 LG LINE ERASE
1X1 LG PAGE ERASE
1Xl LIGHT GREY SEND
lX1 DARK GREY 7
IX 1 DARK GREY 8
1X1 DARK GREY 9
lXl DARK GREY 4
1X1 DARK GREY 5
1X1 DARK GREY 6
1X1 DARK GREY 1
1X1 DARK GREY 2
1Xl DARK GREY 3
1X1 DARK GREY ,
lXl DARK GREY 0
1X1 DARK GREY •
1X1-1/2 LG ENTER
1X1 DARK GREY -
STEPPED
PRINTED
2072100
2075200
2077000
2076700
2077400
2076800
2076900
2074600
2074700
2075300
2068000
2068100
2068200
2067700
2067800
2067900
2067400
2067500
2067600
2068500
2068300
2068600
2072900
2068400
DATE_l1/15/82_
PAGE __3 __0F __ 3 __
PART NUl-, ...iR
KEYCAPS
I BLANK
2065800
2073000
2076500
2076500
2076500
2076500
2073000
2073000
2073000
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2072700
2065800
SCULPTURED/MATTED KEYCAPS
I BLANK
PRINTED
2084000
2087100
2089300
2089000
2089700
2089100
2140500
2086500
2086600
2088500
2079900
2080000 .
2080100
2079600
2079700
2079800
2079300
2079400
2079500
2080400
2080200
2080500
2084800
2080300
NOTES:
I)DEGREES REFER TO SCULPTURED/MATTED KEYCAPS ONLY
2)SLASH BETWEEN TWO CHARACTERS (ie: 1/1) IS FOR CLARITY AND IS NOT
PRINTED ON KEYCAP
3)LOW PROFILE KEYCAPS
4)SAME KEYCAP CAN BE USED FOR ALL FOUR CURSER POSITIONS
2161900
2161901
2162101
2162101
2162101
2162101
2161600
2161600
2161600
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2161601
2162103
2161601
COMMENTS/NOTES
-7
-7
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
DEGREES
II
II
II
(3)
(3)
II
"
"
"
II
"
II
"
II
II
II
II
"
"
"
II
II
II
II
II
(3)
(3) (4)
(
(
PART LIST: KEYCAPS
I
910/910PLUS KEYBOARD
MODEL:
9I2C/920C KEYBOARD
DESCRIPTION
fAlIT NUMBER
DATE_II/10/82 _ _
PAGE_l __ OF __3_
1910/910PLUS I 912C/920C
I PRINTED
I PRINTED
BLANK
COMMENTS
-----------------------------------------------------------------------------------------2073000
lXl LIGHT GREY BLANK
(1)
------2073000
lXl LIGHT GREY Fl
2073100
lXl LIGHT GREY F2
lXl LIGHT GREY F3
lXl LIGHT GREY F4
lXl LIGHT GREY F5
lXl LIGHT GREY F6
lXI LIGHT GREY F7
lXI LIGHT GREY F8
IXI LIGHT GREY F9
IXI LIGHT GREY FlO
IXI LIGHT GREY Fll
lXI LG CHAR INSERT
lXl LG CHAR DELETE
lXl LG LINE DELETE
IXI LG LINE DELETE
lXl DARK GREY BLANK
lXl DARK GREY ESC
lXI DARK GREY 111
1X1 DARK GREY 2/@
lX1 DARK GREY 3/1
IXI DARK GREY 4/$
1X1 DARK GREY 5/%
IX1 DARK GREY 6/"
IXI DARK GREY 71 &
IXI DARK GREY 8/*
IXI DARK GREY 9/(
1X1 DARK GREY on
1X1 DARK GREY -1_
lXI DARK GREY =1 +
1X1 DARK GREY '11Xl DARK GREY \/1
lX1 DG BACK SPACE
1XI-1/2 DARK GREY TAB
IX 1 DARK GREY Q
lXI DARK GREY W
lX1 DARK GREY E
lXI DARK GREY R
1XI DARK GREY T
lX1 DARK GREY Y
1X1 DARK GREY U
lX1 DARK GREY I
-------------
---------------
2073200
2073300
2073400
2073500
2073600
.2073700
2073800
2073900
2074000
2074100
2074200
2074300
2074400
2074500
2072200
2065900
2066000
2066100
2066200
2066300
2066400
2066500
2066600
2066700
2066800
2066900
2067000
2067100
2067200
2067300
2072600
2068700
2068800
2068900
2069000
2069100
2069200
2069300
2069400
2072200
2065900
2066000
2066100
2066200
2066300
2066400
2066500
2066600
2066700
2066800
2066900
2067000
2067100
2067200
2067300
2072600
2068700
2068800
2068900
2069000
2069100
2069200
2069300
2069400
-------
-------------------------
-------------------
--------------
-------
-------
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2073000
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2072400
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
(l)
(1)
(1)
(1)
(1)
(l)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
PARTLIST: KEYCAPS
MODEL:
910/9l0PLUS KEYBOARD
9l2C/920C KEYBOARD
DESCRIPTION
IXI DARK GREY 0
IXl DARK GREY P
lXl DARK GREY[/]
lXI-1/2 DG LINE FEED
IXl-1/4 LG CLEAR SPACE
IXI LIGHT GREY CTRL
lXl DG ALPHA LOCK
IXI DARK GREY A
IXI DARK GREY S
IXI DARK GREY D
IX1 DARK GREY F
lXl DARK GREY G
1Xl DARK GREY H
IXI DARK GREY J
IXI DARK GREY K
lXI DARK GREY L
lXl DARK GREY il:
lXl DARK GREY '/R
LIGHT GREY -L ft RETURN
1Xl LIGHT GREY BREAK
lXl DARK GREY BACK TAB
1Xl-1/2 LG SHIFT
lXI DARK GREY Z
IX1 DARK GREY X
lXl DARK GREY C
1Xl DARK GREY V
IXI DARK GREY B
IXI DARK GREY N
lXI DARK GREY M
lXl DARK GREY ,1<
IXI DARK GREY .1>
lXl DARK GREY II?
IX1 DARK GREY {I}
lXl LIGHT GREY DEL
lXl LIGHT GREY PRINT(LP)
IXl LG CONV/BLOCK (LP)
lXl LG FUNCT (LP)
IX8 DARK GREY SPACE BAR
lXl LG HOME eLP)
lXl LG CURSER (LP)
lXl LG LINE ERASE
lXl LG PAGE ERASE
lXl LG SEND LING
IXI LG SEND PAGE
lX1 DARK GREY 7
lXl DARK GREY 8
lXl DARK GREY 9
IXI DARK GREY 4
DATE _ _ 11/10/82 _ _
PAGE _2__ OF __ 3~
PART NUMBER
19IO/910PLUS I 912C/920C
I PRINTED
I PRINTED
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
20695'00
2069600
2069700
2072500
2077300
2075000
2069900
2070000
2070100
2070200
2070300
2070400
2070500
2070600
2070700
2070800
2070900
2071000
2077100
2075100
2069800
2072800
2071100
2071200
2071300
2071400
2071500
2071600
2071700
2071800
2071900
2072000
2072100
2075200
2077000
2076700
2077400
2076800
2076900
2068000
2068100
2068200
2067700
2069500
2069600
2069700
2072500
2077300
2075000
2069900
2070000
2070100
2070200
2070300
2070400
2070500
2070600
2070700
2070800
2070900
2071000
2077100
2075100
2069800
2072800
2071100
2071200
2071300
2071400
2071500
2071600
2071700
2071800
2071900
2072000
2072100
2075200
2076600
2076700
2077400
2076800
2076900
2074600
2074700
2075300
2074900
2068000
2068100
2068200
2067700
BLANK
2065800
2065800
2065800
2072400
2077200
2073000
2073000
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2077101
2073000
2065800
2072700
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2073000
2076500
2076500
2076500
2076500
2076500
2073000
2073000
2073000
2073000
2065800
2065800
2065800
2065800
COMMENTS
(
(3 )
(3 )
(3 )
(3 )
(3) (4)
(1)
(1)
(1)
(1)
(
PARTLIST: KEYCAPS
'ODEL: 910/910PLUS KEYBOARD
912C/920C KEYBOARD
~ART
1910/910PLUS
PRINTED
DESCRIPTION
I
DATE_II/10/82 _ _
PAGE _3_ OF _3_
NUMBER
I 912C/920C
I PRINTED
BLANK
COMMENTS
-----------------------------------------------------------------------------lXl DARK GREY 5
lXl DARK GREY 6
lXl DARK GREY 1
lXl DARK GREY 2
lXl DARK GREY 3
lXl DARK GREY ,
lXl DARK GREY 0
IX 1 DARK GREY
lXI-1/2 LG ENTER
lXl DARK GREY -
.
2067800
2067900
2067400
2067500
2067600
2068500
2068300
2068600
2072900
2068400
2067800
2067900
2067400
2067500
2067600
2068500
2068300
2068600
2072900
2068400
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2065800
2072700
2065800
I)KEYCAPS ARE FOR 920C KEYBOARD ONLY.
2)SLASH BETWEEN TWO CHARACTERS (ie: 1/1)IS FOR CLARITY AND IS NOT
PRINTED ON KEYCAP
3)LOW PROFILE KEYCAPS
4)SAME KEYCAPS CAN BE USED FOR ALL FOUR CURSER POSITIONS
(
()
SPARE PART KITS
The following are the terminal spare part kits available through
TeleVideo Systems, Inc.
Each model terminal has been designated the
following spare part kits:
A)
B)
C)
D)
Main Logic
Power supply/Video module
Mechanical components
Additional parts
The suggested stocking levels have been identified as follows:
For
are
For
For
For
the first 50 terminals lea of
suggested.
the next 50 terminals add lea
the next 50 terminals add lea
the next 50 terminals add lea
kits A, B, C, & D
of kits A, & B
of kits A, B, C, & D
of kits A, & B
The list price of the spare part kits (as shown on the Terminal
Spare Parts Price List) reflect a 25% discount, if the items were
purchased seperately.
*Attached are the kits currently available through TeleVideo.
(
SPARE PARTS KIT
MODEL: 910 TTL
LOGIC BOARD
PART NUMBER:
2000600
PART t
2029200
2029400
2035800
2036200
2049600
2051800
2052800
2053000
8000020
2028700
DATE_02/10/83_
, DESCRIPTION
IC 75188N/1488
IC 75189AN/1489
IC 2114 RAM
IC 74LS245/N8T245N
IC 6502A 2MHz CPU
IC KYBD ENCODER 910/910PLUS
IC SY6545A-l 2MHz CRTC
IC SY6551A-1 2MHz UART
IC EPROM SYS PROG 910
CAP CERAMIC .01uf/16V 20% (2ea)
(
(
(J
DATE_02/10/83_
SPARE PARTS KIT
MODEL: 910 GATE ARRAY
LOGIC BOARD
PART NUMBER: 2225400
PART t
2029200
2029400
2035800
2036200
2049600
2051800
2052800
2053000
8000020
2057400
2028700
DESCRIPTION
IC 75188N/1488
IC 75189AN/1489
IC 2114 RAM
IC 74LS245/N8T245N
IC 6502A 2MHz CPU
IC KYBD ENCDR 910/910PLUS
IC SY6545A-1 2MHz CRTC
IC SY6551A-1 2MHz UART
IC EPROM SYS PROG 910
IC GATE ARRAY 910/925
CAP CERAMIC .01uf/16V 20% (2ea)
(
(
SPARE PARTS KIT
MODEL:
910PLUS TTL
LOGIC BOARD
PART NUMBER:
2000800
DATE_02/10/83_
PART t
DESCRIPTION
2029200
2029400
2035800
2036200
2049600
2051800
2052800
2053000
8000040
2028700
IC 75188N/1488
IC 75189AN/1489
IC 2114 RAM
IC 74LS245/N8T245N
IC 6502A 2MHz CPU
IC KYBD ENCDR 910/910PLUS
IC SY6545A-l 2MHz CRTC
IC SY6551A-l 2MHz UART
IC EPROM SYS PROG 910PLUS
CAP CERAMIC .01uf/16V 20% (2ea)
(:
(!
DATE_02/10/83_
SPARE PARTS KIT
MODEL:
910PLUS GATE ARRAY
LOGIC BOARD
PART NUMBER:
2225500
PART I
2029200
2029400
2035800
2036200
2049600
2051800
2052800
2053000
8000040
2057400
2028700
DESCRIPTION
IC 75188N/1488
IC 75189AN/1489
IC 2114 RAM
IC 74LS245/N8T245N
IC 6502A 2MHz CPU
IC KYBD ENCDR 910/910PLUS
IC SY6545A-1 2MHz CRTC
IC SY6551A-1 2MHz UART
IC EPROM SYS PROG 910PLUS
IC GATE ARRAY 910/925
CAP CERAMIC .01uf/16V 20% (2ea)
(;
DATE_02/10/83_
SPARE PARTS KIT
MODEL:
912C/920C TTL
LOGIC BOARD
PART NUMBER:
2000000
PART I
2026600
2027400
2028400
2029200
2029400
2030800
2031000
2031200
2034000
2035800
2098600
2028700
DESCRIPTION
IC 74LS74
IC 74LS157
IC 74LS253
IC 1488/75188N
IC 75189AN/1489
IC 2502HP UART
IC TMS 9927/5027 CRTC
IC P8035 CPU
IC SYSTEM ROM 912/920C A49C1
IC 2114 RAM
XTAL 23.814 MHz CRYSTAL (912/920)
CAP CERAMIC .01uf/16V 20% (2ea)
(
(
(
DATE_02/10/83_
SPARE PARTS KIT
MODEL: 925 GATE ARRAY
LOGIC BOARD
PART NUMBER:
2225300
PART t
2029000
2029200
2029400
2035800
2049600
2052800
2053000
8000031
8000033
2057400
2028700
DESCRIPTION
IC 74LS374
IC 75188N/1488
IC 75189AN/1489
IC 2114 RAM
IC 6502A 2MHz CPU
IC SY6545A-1 2MHz CRTC
IC SY6551A-1 2MHz UART
IC EPROM SYS PROG (A50)
IC EPROM SYS PROG (A49)
IC GATE ARRAY 910/925
CAP CERAMIC .01uf/16V 20% (2ea.)
(i
DATE_02/10/83_
SPARE PARTS KIT
MODEL:
925 TTL
LOGIC BOARD
PART NUMBER:
2001000
PART I
'DESCRIPTION
202900()
2029200
2029400
2035800
2049600
2052800
2053000
8000031
8000033
2028700
IC 74LS374
IC 75188N/1488
IC 75189AN/1489
IC 2114 RAM
IC 6502A CPU
IC SY6545A-1 2MHz CRTC
IC SY6551A-1 2MHz UART
IC EPROM SYS PROG 925 (A50)
IC EPROM SYS PROG 925 (A49)
CAP CERAMIC .01uf/16V 20% (2ea)
(l
(:
(,:
SPARE PARTS KIT
MODEL:
950 TTL
LOGIC BOARD
PART NUMBER:
2000400
DATE_02/10/83_
PART t
DESCRIPTION
2029200
2029400
2035200
2035800
2049600
2049800
2155700
2050200
8000043
8000044
2028700
IC 75188N/1488
IC 75189AN/1489
CRY Kll14A 23.814 MHz
IC 2114 RAM
IC 6502A CPU
IC 6545 CRTC
IC 6551 UART
IC 6522A VIA
IC EPROM SYS PROG 950
IC EPROM SYS PROG 950
CAP CERAMIC .01uf/16V
(950)
(A41)
(A42)
20% (2ea)
(
(
(;
DATE_02/10/83_
SPARE PARTS KIT
MODEL:
950 GATE ARRAY
LOGIC BOARD
PART NUMBER:
2233000
PART t
2029200
2029400
2035200
2049600
2049800
2155700
2050200
8000043
8000044
2057600
2057800
2049200
2028700
DESCRIPTION
IC 75188N/1488
IC 75189AN/1489
CRY Kll14A 23.814MHz (950)
IC 6502A CPU
IC 6545 CRTC
IC 6551 UART
IC 6552A VIA
IC EPROM SYS PROG 950 (A25)
IC EPROM SYS PROG 950 A20)
IC GATE ARRAY 950 A (A34)
IC GATE ARRAY 950 B (A37)
IC 6116 RAM 150ns
CAP CERAMIC .01uf/16V 20% (2ea)
(
("
.SPARE PARTS KIT
MODEL:
910/910PLUS
MECHANICAL
PART NUMBER: 2000900
DATE_02/l0/83_
PART •
DESCRIPTION
2005901
2223700
2223300
2199400
2096800
2097300
2097800
2100200
2180200
CABLE ASY KEYBOARD 910/910PLUS
FUSE 3A 125V (25EA)
FUSE 1A 250V (25EA)
KEYSWITCH (3ea)
SWITCH, SIDE ADJ 10 POS DIP
SWITCH, POWER ON/OFF SPST
CONNECTOR RIGHT ANGLE RS232
SHROUD, CONN 910/912/920
POT, CONTRAST
(I
(
()
DATE_02/10/83_
SPARE PARTS KIT
MODEL:
912/920
MECHANICAL
PART NUMBER: 2000200
PART I
2005900
2223700
2223300
2199400
2174200
2181000
2096800
2097300
2097800
2100200
2180200
DESCRIPTION
CABLE ASY, KEYBOARD 912/920
FUSE, 3A/125V (25ea)
FUSE, 1A/250V (25ea)
KEYSWITCH
Dea)
SWITCH, TOP ADJ. 7 POSe DIP
SWITCH, TOP ADJ. 10 POS DIP
SWITCH, SIDE ADJ. 10 POS DIP.
SWITCH, POWER ON/OFF SPST
CONNECTOR RIGHT ANGLE RS232
SHROUD CONN 910/912/920
POT, CONTRAST
(
()
SPARE PARTS KIT
MODEL: 925/950
MECHANICAL
PART NUMBER: 2000500
DATE_02/10/83_
PART t
DESCRIPTION
2005700
2223700
2223300
2199400
2096800
2097300
2097800
2097900
2100100
2180200
CABLE ASY KEYBOARD 925/950
FUSE 3A 125V (25EA)
FUSE lA 250V (25EA)
KEYSWITCH (3EA)
SWITCH SIDE ADJ 10 POS DIP
SWITCH POWER ON/OFF SPST
CONNECTOR RIGHT ANGLE RS232
CONNECTOR KEYBOARD RJll
SHROUD, CONNECTOR 925/950
POT, CONTRAST
(
(
SPARE PARTS KIT:
MODEL: 910/910PLUS
912/920 925/950
POWER SUPPLY & VIDEO MODULE
PART NUMBER: 2000100
PART t
2197300
2199300
2200800
2201000
2213600
2200900
2200600
2201500
2201600
2126800
2126900
2176600
2201200
2201300
2045500
2047100
2047300
2046700
2280000
2177700
2177800
2177900
DATE_02/10/83_
DESCRIPTION
CAP MYLAR, .lUF/600V (C504)
CAP ELECTROLYTIC 220UF (C305)
DEFLECTION YOKE W/CONN KYS-00060 (L202)
COIL INDUCTOR 27UH .3PIE (L302)
COIL LINEARITY ADJUSTABLE (L201)
COIL LINEARITY S.4UH NON ADJUSTABLE (L201)
DIODE INS391/0S135D (2ea)
DIODE DSA17C/MR500 (4ea)
DIODE, ZENER IN7S9A/RD12EB (0112)
REGULATOR, LAS1605 2A/5V (IC2)
REGULATOR, LAS16CB 2A/13.8V (ICl)
RESISTOR, CF 390 ohm 1/2w 5% (R102)
TRANSFORMER HORIZ DR HOT19 (T301)
TNFR FLYBACK KFS-00093 (T302)
TRANSISTOR 2N4401/2SCl166 (Q301)
TRANSISTOR 2NS5S1/2SC983 (Q103/Q10S)
TRANSISTOR 2SC2233/MJE13006 (Q302)
TRANSISTOR KTC1627A/MPSA06 (QI02)
CAP NON POLARIZED 16uf/2SV (C306)
POT lOOK BRIGHT/VERT HEIGHT (SFR1/SFR4)
POT 2K VERT LINEARITY (SFR2)
POT SK B+ 7SVOLT ADJUST (SFR3)
(
(
(J
SPARE PART KITS
MODEL: ALL
ADDITIONAL PARTS
PART NUMBER: 2000300
DATE_02/10/83_
PART t
DESCRIPTION
2024000
2024200
2024400
2024600
2024800
2025000
2025200
2025400
2025600
2025800
2026000
2026200
2026600
2138500
2027400
2027600
2048200
2027800
2028000
2028200
2044200
2138600
2028400
2028600
2028800
2029000
2030200
2030400
2030600
2044200
2030900
2047500
2201700
2201800
2202200
2180100
2177100
2041300
2040700
2152800
2097400
2180300
2201100
2225600
2199700
2202100
IC 74S00
74LSOO
74LS03
74S04
74LS04
74LS05
74LS08
74LSIO
74LS20
74LS32
74LS42
74LS5l
74LS74
74LSl12
74LS157
74LS163
74LS164
74LS166
74LS173
74LS174
74LS244
74LS251
74LS253
74LS367
74LS373
74LS374
NE555
DP 8304
AMD2lll-4A
74LS244
CAP CERAMIC 1.Opf lKV SPARK GAP
DIODE, IN9l4
DIODE DS l13A/MRI-lOOO
DIODE, IN920/KDS85l3A
DIODE, IN4004/DS130TB
POT FOCUS 2M ohm
RESISTOR 0.6ohm WW 2W
RESISTOR PAC 4.7K ohm
RESISTOR PAC 6.2K ohm
SPEAKER 80hm w/CONN
SWITCH, POWER SELECT, DPDT
THERMISTER, SDT-IOO
TRNF, POWER W/CONN (910/920/925/950)
TRNF, POWER W/CONN (970 ONLY)
TRANS 2N6l2l/25Cl173
TRANS 2N6l24/25A473
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4-1
Overview
The terminal is controlled by a zao microprocessor operating at a clock
speed of 4.0Mhz.
The Z80 can address all 64K memory and refreshes the
dynamic RAM via the built in dyhamic memory refresh counter during one Ml
cycle.
Display Fundamentals
The SMC 9007 video processor/controller is the heart of the display unit.
It has 14 address lines and can address up to 16k of video memory.
The
chip has a row-table addressing mode and each data row on the screen has itE
own starting address.
A row table exists in memory which contains the
starting address of each data row.
For a screen with 26 data rows the row
table will consist of 26 14 bit address each pointing to the first
character position of its respective data row.
The controller is programmed to handle 26 rows by 80 or 132 columns.
A
Double Row Buffer (DRB) allows the buffer be loaded at a slower speed while
the other buffer is displaying at screen painting speed.
This is
especially important in attribute assembly mode (hidden attribute).
After
the DRB is loaded the controller address lines are three stated for the
remaining scan lines of the data row, thereby permitting full processor
access to memory during these scan lines.
The percentages of total memory
cycles available to the processor is approximately (10-2)/10 which equals
to 80%.
During attribute assembly,
the attribute data is latched into the
controller during one clock cycle, both the character and its attribute is
driven out and written into the row buffer (two 8 bit row buffers) •
This
allows one to reserve 8 bits for font and 8 bits for attributes and each
attribute only affects the character associated with it.
Smooth scrolling all or part of the screen (split screen) is accomplished
by a scroll offset register and two programmable registers which define
the start data row and the end data row of the smooth scroll operation.
The offset register will. force the scan line counter outputs of the
controller to start at the programmed offset value rather than zero for the
data row that starts the smooth scroll internal.
Row attributes such as double height double width or single height single
width are programmed by the most significant 2 bits of the row address
pointer in the row-table.
4-3
(
Communications
The keyboard is scanned and decoded by using a single chip microcomputer on
the seperate keyboard PCB. Keyboard entry is transmitted to the processor
serially at 9600 baud and received thru an SIO.
Key codes are assigned
using a PROM located on the keyboard PCB. The keyboard would interrupt the
CPU for every character that is entered.
The modem interface is similar to the keyboard interface and also uses half
a ZaO-SIO tie to the interrupt line.
The SIO is connected via a pair of
line driver and receiver to a standard EIA RS-232 connector.
The printer also uses half a ZaO-SIO
interrupt control on the interrupt line.
connector.
serial interface with optional
The SIO is connected to an RS232
4-4
Character Generation
The character generator is 16k bytes of static RAM.
The fonts are loaded
from system RAM into the font RAM by the CPU.
The characters are in a 6Xa
matrix placed in a aXlO cell with half-dot shift to achieve a llX8
resolution.
Bit 0 and 7 on the character font are used to control the
half-dot shift.
4-5
(
Terminal Memory
2K bytes of CMOS RAM with memory power back up, are used to store the
-terminal's set up parameters and the special function key codes.
Tbe terminal has 16K RAM space for display memory which provides up to 2
pages in hidden attribute mode.
The CRT controller constantly refreshes
the display memory to the display screen.
The terminal can have up to 24K bytes of EPROM (2764) space for firmware
program code space.
The rest of the RAM space not used by the display RAM
can be used for program data space.
4-6
Operating Clocks
The zao CTC timing controller is used as a baud rate generator to generate
the correct frequency clock for the 2 SIO channels.
The baud rate on each
channel is software programmable from 50 to 19.2K baud.
()
4-7
Interrupt Signals
The 970 CPU interrupt structure allows the peripheral device to identify
the starting location of the interrupt service routine. This mode (mode 2)
allows an indirect call to any memory location by a single 8 bit vector
supplied by the peripheral.
In this mode, the peripheral generating the
interrupt places the vector onto the data bus in response to an interrupt
acknowledge.
The vector then becomes the least significant eight bits of
the l6-bit indirect pointer.
The lEO and lEI lines of the peripheral devices are connected together in a
daisy-chain fashion with the devices closest to the CPU having the lowest
priority.
Frame interrupt interrupts the CPU every 1/60 second or 1/50 second
depending on line frequency setting.
This can be used as the real time
clock source.
The CRT controller frame interrupt must be enabled in order
to generate the frame interrupt.
In response to this interrupt, the CPU
jumps to location 66H.
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NOTES UNLESS OTHERWISE SPECIFIED
1.
ALL RESISTORS ARE VALUED IN OHI'S
AND ARE 1IIIW WATT ~ 5'70,
2.
ALL CAPAC TORS ARE VALUED IN
ARE 50 VDC !20:;.
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AND
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1
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5
6
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8
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10
11
12
13
14
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2
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REFERENC[f
DESIGNATOR
NmlENCLATUREjDESCRI PT I ON
PART
C1,3,5,32
c6
C7-17,19-24,2629.33-37
C2,4,25,38-160
C30
C18,31
Cap E1ec 22uf 15V 5%
Cap Tant 4.7uf 16v 10%
Cap Cer 330 pf 50V 20%
2025700
2027500
2029100
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Cap Mono 47pf 100V 5%
Cap Mono .01uf 50V 10%
2030100
2029500
ABO
A92
A74,85
A44,79
A73
A5,24,72,104,10B,
113,116
A39,117
A2,18,46,63,76,
110
A100
IC
IC
IC
IC
IC
IC
2051000
ZBOA CPU A
Z80A CTC A
Z80A SIO/2A
74LS109
74LSl12
74LS74
f\UMBER/RE~IARKS
2028900
2050Boo
2050600
2027000
213B5OO
2026600
IC 74S04
IC 74LS04
2024600
IC 7414
2035400
2024Boo
NOTES:
PAGE :. OF 6
DATE
TITLE
~~B
ASSY CONTROL BOARD 970
5-4-83
-----_._--
---
O.,TeleVideo Systp~s, Inc.
~
~
ItEM/
FIND
NO.
19
QTY PER
A
D
7
..
7
3
3
- 20
REV LEVEL.
REFERENCE/
DESIGNATOR
1
A9,12,26,32,58,
66,109
A20,30,38
A7,17,25,47,62,
6 8 ,71, 81 , 91
A86,103
A36,98
A88,93
A83
A6,15,23,37,45,
61,64
A31
Al14
A9Q,97
A55,115
A41
A34
A65,70
A33
1
A48
1
A49
21
9
9
22
23
24
25
26
2
2
L
2
2
2
1
1
7
7
}.
27
28
1
2
29
2
30
1
31
1
32
2
33
1
34
1
35
1
36
NOTES:
ASS~I/
..
1
1
2
2
1
1
2
~
NO~IENCLATURL/nESCR
I PTI ON
PART NUMBER/REMARKS
Ie 74LS08
2025200
Ie 7 LlLSOO
Ie 74LS32
2024200
2025800
Ie
Ie
Ie
Ie
Ie
2044200
2041600
2041000
2027200
2029000
74LS244
74LS02
74LS138
74LS139
74LS374
,
Ie
Ie
Ie
Ie
Ie
Ie
Ie
Ie
Ie
Ie
74LS174
74LS51
74LS241
74LS163
74LS164
74LS367
74LS245, N8T245N
74LS173
74S251
74S74
202'8200
202'6200
2042000 2027600
2048200
.2028600
2036200
2028000
2138600
2026400
PAG.f: 2 OF 6
TIIL1:
VATE
3 ASSY CONTROL BOARD 970
5-4-83
O.1eIeVideo Syst- ns,Inc.
!
I
i
ITHI/
FIND
l~TY
NO.
A
D
37
1
1
38
1
39
40
41
PER
ASS~I/
REFERENCU
lll:S I GNATOR
REV LEVEL
NOMENCLATURE/llESCRIPTION
PART
1
A50
A19
IC 74LS166
IC 74LS10
2027800
2025400
3
3
A1,8,14
IC 7406
2034800
1
1
A22
IC 74LS86
2026800
5
5
A16,28,40,52,67
IC 74LS157
2027400
2
2
A43,51
IC 75188N
2029200
45
46
3
3
A27,35,57
IC 75189AN
2029400
1
1
A56
8000139
47
1
1
A82
IC EPROM
US/UK CHARGEN
,.
IC 970 EPROM Firmware
48
1
1
A69
IC 9007 CRT Controller
2139900
49
4
4
A53,54,59,60
IC 9006-135 Buffer CRT Sgl
2140000
.'
t\Ur-.IBER/RE~IARKS
42
43
44
8000100
Row
50
8
8
A94,95,101,102,
IC 4116 16K Dynamic RAM
106,107,111,112
120 ns
2139200
51
1
1
Al05
IC 2Kx8 6116 CMOS Static RAM 2138700
52
2
2
A3,42
IC 4N38
2035000
,
53
1-
1
AlO
21.2544 MHZ Clock OSC
2138900
54
1
1
A4
IC 93S16PC
2040800
55
1
1
All
IC 74S32
2038800
NOTES:
PAG2 .3 OF 6
TITLE
P~1
ASSY CONTROL BOARD 970
UATE 5-4-83
!
!
O..ThleVideo Syst,...~s, Inc.
v
~
ITHI/
RLHRENCEj
llLSIGNATOR
QTY PLR i\SSf\I/REV LEVH
FINIl
NO.
56
57
58
59
60
A
D
2
2
1
1
1
1
~
NOMLNCLi\TURl:jDI:SCRIPTION
PAin
A77,78
A87
A99
IC 74soo
2024000
IC 970 EPRON Firmware
IC 970 EPROM Firmware
8000101
8000102
2098603
21 1n400
2098401
f\UIIIBERjREr.lARKS
.'
61
62
63
64
1
1
Y2
Cry 8.0000 MHZ
1
1
Y1
6
6
Cry 13.4784 MHZ
Socket 24p IC DIP
4
4
8
8
XA53,54,56,59,
60,105
Socket 40p IC DIP
XA69,74,80,85
XA94,95,101,102, Socket 16p IC DIP
106,107,111,112
Socket 28p IC DIP
XA82,87,92,99
P2,5
Plug 5P Str Waf
P3,4
Conn 25P PCB Metal D-Sub Fern
P1
Conn6P RJ12 970 Logic Bd
,
65
66
4
4
2
2
67
68
2
2
1
1
69
70
71
72
2098402
2098405
2098404
2098802
2165300
2141200
-
73
74
1
VRl
1
Volt Reg 79L05AC
2126200
NOTI:S:
PAGE '. OF 6
'.-."
.
TlIL
UATE
'B ASSY CONTROL BOARD 970
"'--- .....-,,-"""'~
5-4-83
O..1eleVideo Systr'"llS, Inc.
I
lTHI/
l)'l'Y PER
FIND
J\SS~I/
REHRENCL/
REV LEVEL
NmIENCLJ\TURL/IlESCR I PT I ON
PART f\;UMBER/RHIARKS
NO.
A
D
Ill:S r GNATOR
75
76
77
78
9
9
2
2
1
A-
1
2
2
R39-43,47-49,56
R27,28
R9
R5,67
Res
Res
Res
Res
elF
elF
elF
elF
10K Ohm 1.4w 5%
3.3K Ohm 1.4W 5%
6,80 Ohm 1. 4w 5%
22 Ohm 1/4W 5%
2034100
2052700
2037100
2033500
3
3
1
1
2
2
4
4
2
2
4
4
2
2
5
5
8
8
Res
Res
Res
Res
Res
Res
Res
Res
Res
elF
elF
elF
M/F
elF
elF
elF
elF
elF
33 Ohm 1/4W 5%
82 Ohm 1/4w 5%
68 Ohm 1/4W 5%
100 Ohm 1/4w 1%
220 Ohm 1/4w 5%
330 Ohm 1/4w 5%
270 Ohm 1/4W 5%
470 Ohm 1/4W 5%
1K Ohm 1/4w 5%
2034500
2144000
2051100
2034900
2040300
2051500
2051300
2051700
2052100
1
1
1
1
R3,59,71
R72
R11,75
R4,50-52
R66,73
R16,19,30,31
R17,18
R8,12,20,68,69
R1.6.7.22.35.65.
70,74
R13
R33
R14.15 23.24.29
32~J4.t36- 38.4446.53-55.57.6064
79
80
81
82
83
84
85
86
87
88
8g
gO
22
91
2
.'
-
-
22
R25,2b
2
Res elF 51K Ohm 1/4w 5%
Res elF lOOK Ohm 1/4w 5%
Res elF 4.7K Ohm 1/4w 5%
2032300
2032100
2053100
Res elF 510 Ohm 1/2W 5%
2045100
NOTES:
PAGE
~
OF 6
TlTU:
r
~
ASSY CONTROL BOARD 970
UATE
5-4-83
O~1.eleVideo Systr-ns, InC.
v
~
ITEM/
FIND
NO.
QTY PER
A
ASS~I/
REV LEVEL
v
-
REFERENCE/
DESIGNATOR
D
NmIENCLATURE/Dl:SCR I PT ION
PART NUMBER/REMARKS
92
1
1
RP6
Res PK 33 Ohm 16 Pin DIP
2041700
93
1
1
RP1,3,5
2041300
94
1
1
R10
Res PK 4. 7K Ohm lOP SIP
Res C/F 180 Ohm 1/4W 5%
95
96
1
1
R21
Res C/F 2K 1/4w 5%
2036900
2
2
RP2,4
Res PK 2.2K Ohm lOP SIP
2230000
97
2
2
Trans 2N2907A
2045900
98
6
6
CRl-6
Diode 1N914
2047500
99
100
4
4
Q1,3,8,9
Trans 2N2219A
2045300
1
1
Q6
Trans 2N3019
204.5700
,.
.Q5,7
2053300
111
112
i
113
114
115
116
117
1
1
118
1
1
119
1
1
~
CR7
B1
Diode Zener 1N756 8.2V
2244500
Battery Holder
2050101 .
Battery
2050001
..
-.
-
NOTES:
PAGE ::,,. OF 6
TITLE
~rB
.~-
ASSY CONTROL BOARD 970
DATE
5-4-83
O.1eleVideo SyStp~S, InC.
950 THEORY OF OPERATION
Table of Contents
Page
MAIN LOGIC BOARD
Overview------------------------------------------------ 1
CPU Timing and Control
3
Display Controller
5
Video and Character Generation
7
Visual Attributes
8
Input/Output Circuits
10
KEYBOARD
Overview----------------------------------------------Keyboard Layout
Keyboard Interface
Scanning Method
11
12
14
15
POWER SUPPLY-------------------------------------------17
VIDEO MONITOR
18
1
(
(
C' "
i
950 THEORY OF OPERATION
MAIN LOGIC BOARD
Overview
Please refer to pages 1, 2, 3, and 4 of the block diagrams as you
read the text that follows.
Page 1 shows the power-on reset, which is controlled by A17.
During power-up, this chip sends the signals necessary to reset the
CPU and to perform the initial diagnostic routine. -This routine
reads the switches in the back of the terminal and configures it for
the proper handshaking protocol.
The 950's CPU is a 6502, located at A53.
The Shift clock (OSCl) generates the timing for the 950's logic
system. The Stretch clock functions as the main clock for the CPU.
Other clock circuits include the Crystal clock to the UARTs, the
Shift clock, the DC Carry clock, the C clock, and the QC clock.
The CPU's address bus (6502 bus) addresses the ROM chips (A4l and
A42).
The ROMs contain the operating instructions, the power-up
diagnostics, and the other intructions necessary to operate the
terminal. Most systems only use two ROMs, but the 950 contains an
additional, optional ROM (A52).
The decoding gates (ASS and A63) select one of the three ROMs.
The other decoder (A62) selects either the Dl8P.MEM (display memory)
or the lOP.8EL (input/output select) signal.
The auxiliary chip on this page (6522) reads switches (81 and
82), and generates the control signals for the video attributes and
the bell, as well as several auxiliary control signals used to
address the display RAM.
On page 2 of the block diagram, note the continuation of the 6502
and the 6522.
The CRT controller chip (CRTC 6545) generates the signals
necessary to control the monitor portion of the terminal. It outputs
three primary signals: horizontal synch, vertical synch, and cursor.
These signals go to the video module.
The display RAMs are addressed by the 14 address bits coming from
the CPU bus, as well as the memory address bits from the CRTC.
1
The multiplexers in the center of the page (A43 through A46)
alternately select whether the CPU or the CRTC is permitted to
address the system and the display RAMs (A25 through A28, A34 through
A37) •
(
..
The Phase clock controls this process. During one phase of the
clock the CPU can address RAM. During the other phase, this
multiplexer allows the CRTC to address RAM.
When the CPU addresses the system display RAMs, the bidirectional
latch at A14 is enabled to either input or output data from the
system RAMs. When the CRT controller addresses the RAMs, the latch
at A24 holds the display data.
Normally, the outputs of the CRTC would be used for scrolling.
However, since the 950 has a smooth scroll option, the output of the
counter latches at the bottom of page 2 (A60 and A6l) are used to
scroll. The CPU controls these latches through the decoder at A62.
On page 3 of the block diagrams, the row
from these counter latches (A60 and A6l) and
the latch above it (A24) are used to address
ROMs (A32 and A33). The character-generator
to a parallel-to-serial shift register.
address signals corning
the display data from
the character-generator
ROMs then output 14 bits
The DC.Carry signal loads these 14 bits at the shift register
(A22 and A23), and the shift clock shifts the data into the video
logic and the drivers as a serial data stream.
The eight bits of display data from latch A24, as well as one bit
from the character generator ROMs, address the attribute registers.
(
The attribute registers' output also addresses the video logic
and drivers, as do the video attribute signals sent by 6522. These
signals (dark on light, cursor, force blank, blink rate, and maximum
intensity) control the video attributes through the video logic and
drivers. Note that, in the 950, the maximum intensity signal (MI) is
standard. To highlight, the 950 uses half intensity. The output is
routed to the video module.
.
The XTALI clock (clock source) controls the three UARTs on page 4
of the block diagrams.
A49 receives data from the keyboard.
A50 receives and transmits data for the main port (P3).
ASI receives and transmits data for the printer port (P4).
()
2
CLOCK
OSC
...
25,814
1.83 MHZ
"-';"-1.5
MHZ
OSC 1
~
....
TO UARTS
A4
SHIFT CLOCK
~
W
DC·CARRY
1. 701 MHZ
..
~
-'-, 14
1, 701 MHZ
CCLK
A3
.,..
POWER
ON
RESET
CLOCK
STRETCH
~0
..
.
~
AS,6,8
A17
~
--,.
6502
CPU
RESET
A53
~0 NMI,0Z,IRQ
A15-0,D7-0,
DECODE~
~
~
2
~
R If" l=Tr
3
A62
IOP'SEL
DISP'MEM
h.
I'-'
~
t::>-
p~
....
~
h.
DECODE ,....
k
I"-'
A58,63
~
ADDRESS
U')
.....J
<::;
z
lJ
......
V
V
DATA
~
....
....
~
0
0
ROM
ROM
Rml
A41
A42
A52
-
[f)
U')
YIA 6522
:::l
I=Q
N
c
L()
'-D
...
\
PA0-3
~DRESS &DA~
v-........
FIG. 1
PB0-5
PART PB7
OF PA4
6522
PAS
.,/
V
'"
S\\'ITCHES
S1 , S2
BELL
BI DIRENA
BOW
PA7
FORCE BLANK
~CB:'
BLI RATE
CPU, TIMING AND CONTROL
....
..
.
....
.
....
~
"..
~DRESS
"'i
_ IRO
&
DA~
v
- "--"
PART OF
6522
PB6
PA6
..,
.....
(\
-. IRQ CAl CA2 -
NMI
TIMING
LOGIC
...
CCLK
--CRTC RES
~--------~~--~C
...
~I\r. . - - - -ADDRESS
AND DATA
\
---------.- /
14 J
Y
ADDRESS
ADDRESS
...
RES
CCLK
HSN
CTRC
6545 VSN
t-41~--....
.....
I------~-
MA
ASS
I
MULTIPLEXER
...
(
A43-46
140
SYSTEM R.A]\1
DI SPLAY RA~l
BIDIRECTIONAL
TRANCEIVER
A
V
8I
...
A25-28, 34-37
8T2450 8 I
\ rt>r
LATCH
'--+-l---J~ 74 LS 3 74
l/'-'------'
~ll1A ~ ~ ~~
_______/~~/)D
A14
8 I
I
Q DISPlAY DAT
I
A24
CRTC RES
1------""""'-
DE CO DE
ADDRESS .,)
~-------~:
COUNTER
LATCH
A62
0-3 RO\\' ADDRESS
'\
1---____~D~A~TA~7~-_4~__________~vI
PAGE 2
A60,61
(
DC CARRY
SHIFT CLOCK
14 / ...
....
.
'\
"
ROW ADDRESS -/ CHARACTER
GEN ROMS
1)
....
DISPLAY
0
LD
SHIFT
REG
\i
A22,23
DA~
A32.33
'"\
~
A1,2,10,11 Q1
A
~
j ~
A
M.1.
....
,..
.
ATTRIBUTE
REGISTERS
-./ A18,19,20,
21,30
BOW
CURSOR
FORCE BLANK
BLI-RATE
FIG. 3 VIDEO GENERATION
PAGE 3
VIDEO
OUT
VIDEO LOGIC AND
DRIVER
,~
.
.".,
AI'
(
UART
I.......
-----------~--,-«,PO'·
PI ..
PO -
pr-
u-----~
"
tI),
...:l
<:
zt..:)
tI.l
tI.l
/Xl
':
'
DRIVERS
RECEIVERS
AND
SWITCHING
LOGIC
UART
~
::>
.'.,'
A50
N
'0
L/')
\0
A39,4O,47
48,56,57,
58,59
UART
FROM 6522 VIA
,BELL
A5I
CLOCK SOURCE
BIDIR "
CONTROL,
(
FIG. 4 I/O CIRCUITS
(
PAGE 4
CPU Timing and Control
A 23.814 MHz. oscillator (OSC 1, sheet 6) generates the timing
for the 950's entire internal logic system. Known as the Shift (or
dot) clock, it drives the two shift registers (A22 and A23). :These
registers bring in parallel data and shift it out as serial dot data.
The active low* shift clock is gated with the terminal count
output of the C.clock (Character clock) counter. Together they
driv~ a latch (A24,· sheet 4) that holds data from character
addresses 0 through 7, as well as the flip-flop (A3l, Sheet 4) that
controls the DEL CURSOR signal.
A 4-bit binary counter (A3, sheet 6) divides the shift clock's
rate by 14, creating eight 1.701 mHz clocks.
The C.clock, which is the time base for character generation,
drives the CRT chip (6545, sheet 2). The active low C.clock has two
purposes. It drives the Hex D flip-flops (A64 and A7l) that time
the CRTC RESET. It also controls the Stretch clock, which
generates clock periods twice the normal length (1175ns vs. 588ns)
.
upon command f rom the CPU.
This circuit (sheet 6) accesses slower memory or peripheral
devices. The final output (called ·00" or "Phase Zero clock") goes
to the 6502 and all the peripheral chips. The Phase Zero clock
controls the CPU bus timing, and it triggers all data transfers
between the CPU and the other internal processors.
The DC.carry signals function a. two clocks. The active high
DC.Carry clock drives a flip-flop (A19, sheet .4) that is part of the
video attribute circuitry. The active low DC.Carry clock is
connected to the LD or Shift/Load enable lines (A22 a~d A23, pin 15,
sheet 4) of two parallel-to-ser ial shift registers -(A22 and A23).
These registers are part of the characacter generation circuitry.
The XTALl clock drives UARTs A49, A50, and A5l, which interface
data to and from the terminal.
The QC clock combines with three RAM address lines (A15, sheet
3) to form a l-of-lO decoder. The decoder's output goes to the
chip select lines of each system RAM and each page of memory. The
QC clock also deselects the RAM chips while the address lines are
settling.
Line lock and smooth scroll are two 950 features not normally
attainable with the 6545 CRT controller. To use them, additional
circuity is required.
*The active low state is indicated by a bar above the signal name.
3
To achieve line lock, the top of the 6545's display register
must be reloaded at the beginning of each character row. A general
description of this circuitry follows.
To achieve smooth scroll, a 'CPU-loadable count-up counter (A60,
sheet 4) must replace the 6545's internal scan line counter.
CLOCK
OSC
23.814
7
~IfIZ
1. 83
13
1'0 UARTS
A4
OSC 1
SIIIFT CLOCK
- : 14
DC·CARRY
1.701
CCLK
1. 70 l~IIIZ
I
A3
POWER
ON
RESET
.6502
CPU
A53
t~ NMI .!t'Z, IRQ
A15-~ D7-0
.0;'" 1=+r
'
iiEE'T
---.-
DECODE~
~III;:
CLOCK
STRETCH
A17
~
~IIIZ
~~
AS,6,S
10P'SEL
DISP' ~IHI
~
2
3 0-+ DECODE
A62
k
~
~ ASS ,63
PJ,
')
"''\
l/
ADDRESS
v:l
-'
<
2:
t..:l
(
RO~I
RO~I
RO~I
A41
A42
A52
A
V
DATA
r\..
: t:
v:l
V)A 65""
:::>
'"
PA0-3
N
0
o.n
>C
....
A
V
~DDR[SS
&
DAT'~
.
PB0-S
.
S\I'JTCIIES
SI ,52
P'
"
PART PB7
OF PA~
6522
.--......
P/\S
BOll
P/\ -
FORe!: HL\:\I\
~
Figure 1
BUL
BI IlIRL:\A
Ill. 1
R.\TE
CPU, Timing, and Control
4
(
Display Controller
The 6545 (ASS) generates each character's memory address in
the display RAMS (A25 through A28) as it is to be displayed. It
also generates the horizontal and vertical synchronization (synch)
pulses necessary to control the deflection circuits of the monitor
(CRT).
Notel. In the text that follows, the term "scan line" refers to
one of ten scan lines created by the electron beam, which makes up
one data row.
The 6522's timer (T2) counts horizontal scan lines. When a
specified number of scans have been executed, it interrupts the
CPU (6502) with the NMI-interrupt. The CPU then loads the memory
address of the next data row into the CRT controller (6545).
At the same time the NMI-interrupt is issued to the CPU, the
CRTC reset timer (A64 and A7l, sheet 7) is cleared, causing it to
reset. The reset is released after seven C.CLK periods, and the
CRTC starts timing the next character row. This operation allows
the CPU to determine the order of the display lines so that some
lines can be locked while others scroll.
To achieve a smooth scrolling effect, the number of scan lines
in the character row and the starting scan line of each row must be
specified.
The 6522's timer, which
specifies the number of scan
Normally, ten lines are used
a smooth scroll, this number
bottom rows.
counts horizontal synch pulses,
lines in the present character row.
when smooth scroll is disabled. During
ranges between 1 and 10 on the top and
To do this, the processor loads a 4-bit value into a latch (A6l,
sheet 4). When the CRTC is reset, this value is transferred to the
counter (A60, sheet 4) and becomes the first scan line of the next
data line. Each horizontal synch pulse then increases this value
until the start of the next data line. At that point, it is preset
again to a value determined by the CPU.
The CPU and the display controller share access to the system
and display RAM during the alternate phase of the 6502's Phase 2
clock.
During the positive portion of the Phase 2 clock, the CPU
address can be gated onto the RAM address bus through multiplexers
(A43 through A46, sheet 2). A bidirectional transceiver (A14,
sheet 3) passes data between the CPU data bus and the RAM data bus.
5
During the negative portion of the Phase 2 clock, the 6545
address bus (ASS) is gated onto the RAM address bus, allowing the
video data to be loaded into a latch (A24, sheet 4). This address
becomes the input for the character generators and'the attribute
generation circuitry.
'
(
,
This alternating ("interleaved") access allows the processor to
operate at normal speed without interruption or degradation 'of the
display quality (which could be caused by accidental appropriation
of the d~~play bus by the processor as it accesses data).
'
~'"''''
I
~
,-,\
ll'\]j
'I
1',\1'] ()]:
(,:;""
V
t
PB(,
IT' \
'0il
[',1('
C\ '
11,1'
'C,\ 1 ,-
~
'I
[~,I
.
[\G
WG[C
CCl.~
CRTC RLS
,...
RLS
- CCLK
"'\
A
K
ADDRLSS ,\\[) [),\T,\
'I
/
v
1.1 J
ADDRESS
ADDRLSS
,
I~
j
<
G
~[A
}
0
IIsr-;
CTRC
6545 VSr-;
ASS
~[ULtIPLEXER
c.:;
A43-46
:.r.
14~
:.r.
::<:
:J
SYSTEM RAJ,[
DISPLAY RA~[
01
c
Vl
.0
A
/
\
'I
BIDIRECTIO)\AL
TRA\CEIVER
HT245
HI
llA'(1I
/
I
")
~
"
A25-28, 34-37
A
0
8 1
\....
I
A14
/
,
LATCH
74LS374
\
Q
/ D
'"
r
8 1
~
DISP~AY DAT
I
A24
"
CRTC RLS
~
"IIIIIU,"~
\
vi
[/IC()Il!:
cour-;n:n
LIITCII
A(,2
n - ~ nOli ADDRESS
II,~'I
'\
A 7 - ,1
'"
I'
/ IIbO ,(,]
"
~
Pigure 2
6
Display Controller
(.
Video and Character Generation
To create the 950's display, the CRT scans horizontally from
left to right, and vertically from top to bottom. Depending on the
terminal's Hertz setting, the scan consists of 250 horizontal scan
lines, each repeated 50 or 60 times per second. Each scan line
displays 80 sections of l4-dot pixels. Each character line contains
ten horizontal scan lines. This makes each character cell 14 pixels
wide ?y 10 pixels high.
Characters are formed when the electron beam turns on
individual pixels. The CRTC "MA" lines access the display memory
once each character time (14 dot clocks). Once each cycle, the data
from the display memory is then latched by the character address
latch (A24, sheet 4). The output from this latch drives the eight
most significant address lines of the character generator ROMs (A32
and A33, sheet 4).
The scan-line counter controls the four least significant
address lines of the character generators. The scan-line counter's
output changes only at the end of the scan line, when horizontal
synch goes high.
The character generator's output is a l4-bit word that
represents the pixel pattern to be displayed. The Shift clock loads
this word into a l4-bit parallel-in/serial-out shift register (A22
and A23, sheet 4), and shifts it out, one bit at a time.
Thus, as the present pixel pattern of one character is loaded,
the character address of the next character is latched. The bits
shifted out of the shift register are mixed with display enable and
the cursor and attribute data, creating the video output to the
monitor. This signal turns the CRT's electron beam on and off as the
beam sweeps the raster.
DC CARRY
CLOO:
5111 F1
~
"-
) CIIAR:\CTLR
CE:\ RO~IS
ROil ADlIRLSS
[IISPLA)
[)A~
~I
A~:
::;::;
I
v
6
LD
SIlIn
RLG
A22 ,2::;
.I.
---... ATTRIllUTL
"\
RLGISTLRS
--..
VIflEO LOGIC
DRIVER
AI
,c, 10,11
A:\D
VIDEO
OUT
Ql
'I"
/ AIR,19,20,
II'
~
1 ,::;0
BOll
CURSOR
FORC!: BLA:\l\
flLI-RAn.
Figure 3
Video and Character Generation
7
(
Visual Attribu'.es
The 950 hi] s five visual a ttr ibutes:
blank, underline, and reverse video.
half intensity, blink,
The only attribute created on a character-by-character basis is
half inte~sity. All other attributes are "field" attributes; i.e.
they have a specified starting and ending point. All characters
between these points are affected by the attribute selected.
In the 95(" attributes are stored in the display RAM just like
displayed characters. An attribute character occupies a character
space on the screen and is displayed as a half intensity space. The
attribute becomes active immediately to the right of that space and
remains in effect until the end of the screen.
Since an attribute is stored as a character in
RAM, the character generation logic processes it as
a displayed character. However, the byte stored in
attribute character differs from that for a display
bits 4 and 7 are always set, while bits 5 and 6 are
the display
though it were
RAM for an
character in that
always reset.
Bits 0 through 3 define the active attribute.
When the loworder character generator ROM (A33, sheet 4) is accessed by these
codes ~90 through 9F), the resulting data bit (A33, pin 17) is output
as a hlgh.
A21 ' s data input comes from the output of a four-channel, twoto-one multiplexer (A20). While nonattribute characters are
displayed, the multiplexer is driven by the output of A19. During an
attribute character time, the output of Nand gate All is low, and it
selects the A input to the multiplexer. This input connects with the
output of the And gates that compare the previous attributes (output
of A21) to the new attributes (output of A24).
If the previous attribute bit and the corresponding bit of the
new attribute are both high, the output of the And gate is high. If
one or both are low, the ouptut of the And gate is low and the
attribute is turned off.
Thus, if an attribute is true for both the previous attribute
and the new attribute, it is true while the new attribute is
displayed on the screen. Otherwise, it turns off when the new
attribute character starts.
8
(
_
The 950's attributes continue from character line to character
line. Since any attribute on the previous line must be displayed on
the current line until a new attribute is found, the logic must
remember the last attribute of the previous line.
To summarize, A21's output is used by the video logic to turn
visual attributes on or off. Its input can corne from two sources:
the output of the AND gates and the output of A19.
The output of the And gates defines the attribute(s) to be
displayed during the attribute character, while A19's output
determines the attribute(s) to be displayed during a nonattribute
character.
A19's output is set to equal the previous character line's
attribute until a new attribute is encountered. At that time, the
output changes to the new attribute. AlB is used to remember the
last attribute of a character in any character line.
Since each character line contains ten scan lines, the attribute
data changes ten times. At the end of the displayed portion of each
scan line, the Display Enable signal changes from high to low. This
signal is then inverted and fed into a two-input Nand gate with the
Delayed Display Enable signal, which changes one character time after
Display Enable. Both signals are high only during the Blst character
time of each scan line, creating a low pulse on the output of the
Nand gate (A13 and All). This pulse enables the output of a tristate latch (AlB).
AlB's input comes from A20 and is latched only during the last
scan line of the character row (pin 9, clock enable). This
"remembers" the last attribute data of any character line. AlB's
output is latched into Al9 at the end of the displayed portion of
each scan line. A19's output then defines the attribute to be
displayed during the current nonattribute character time.
The signals for Delayed Display Enable, Delayed Cursor, Dot
Serial, BoW, Force Blank, and Visual Attribute Data are combined on
sheet 6. They are gated together through AI, A9, AIO, and All, and
are amplified to proper voltage and current levels by an NPN
transistor QI (sheet 6). This transistor drives the video signal to
the video module and/or external monitor (i.e. composite video).
9
Input/Output Circuits
Each of the three peripheral ports is controlled by a seperate
6551 UART.
~
UART A50 receives and transmits data for the main port (P3)
UART A5l receives and transmits data for the printer port (P4)
UART A49 receives data from the keyboard
The UARTs receive serial data, convert it to parallel data, and
tie it dir'ectly to the CPU's data bus with input drivers, receivers,
and switching circuits (A39, 40, 47, 48, 56, 57, 58, 50, sheet 5).
The use of seperate UARTs for the P3 and P4 ports allows the
setting of different baud rates for each port.
The 1489 quadruple input line receivers (AS7 and A40) convert
RS232C voltage levels to TTL voltage levels. The 1488 quadruple
output line drivers (A48 and A39) convert TTL voltage levels to
RS232C voltage levels.
The output of AS9, a quadruple 2-to-l multiplexer, selects the
output line drivers. A59 can select between two inputs (A or B), and
route it to its respective outputs.
Figure 4
10
I/O Circuits
(
KEYBOARD
Overview
The 950 contains a microprocessor-based keyboard. The
firmware monitors keyboard scanning, return-line testing, and
communication with the control board.
In addition to the standard keyboard, additional parts let you
create a keyboard that allows new key codes to be programmed into the
keyboard PROM (2716).
Standard Keyboard
(Version 1)
Requires 5 volts (typical input current = 80 milliamps)
8048 microprocessor
lk byte ROM capacity (internal to the 8048)
Asynchronous serial transmit and receive
Baud rate = 1200 bits/sec.
Word structure = 1 start bit, 8 data bits, 1 stop bit
Version 2 Keyboard with EPROM
Requires 5 volts (typical input current = 150 milliamps)
8035 microprocessor
2K x 8 byte EPROM 2716 (external to 8035)
Status display - 8 LED display
Asynchronous serial transmit and receive
Baud rate = 1200 bits/sec.
Word structure = 1 start bit, 8 data bits, 1 stop bit
The Version 2 keyboard with the 2716 EPROM requires a larger
memory map and storage capability in the microprocessor. Therefore,
you must also change the standard lK x 8B 8048 microprocessor to a
2K x 8B 8035.
To install it, cut jumpers A through M on the circuit side of
the logic board and install the following components in the
appropriate locations.
Components
U2,U3
U4
U5
U7
C2,C3
C4,C5
R2
74LS367
75L5373
EPROM (2716)
74LS05
{.Oluf cap}
{lO% 50V}
lK 5% 1/4 watt
11
Keyboard Layout
~
The keyboard contains 101 keys on a PC board, as shown
in Figures 5-A and 5-B.
The key switches are arranged in an X-Y matrix (Figure 6).
four special keys (CTRL, SHIFT, FUNCT, and ALPHA LOCK) are not
included in the X-Y matrix.
Only
r::1
E.J
(I
Figure 5-A
Keyboard Layout
r.;;1D
EJ L.J
Figure 5-B
Keypad Layout
(
12
xu
Xl
X2
X3
X4
X5
X6
,
•
1
,
2
@
•
9
(
0
)
...
II
..
II"
%
6
7
&
Q
W
8
*
=
+
E
R
Y
U
I
0
P
A
S
D
F
G
H
J
K
Z
X
C
V
L
B
X8
...
4
X9
..
XIO
..
II"
5
T
SP
...
$
TAB
..
X12
4
#
II'
X7
XII
A
3
,
,
"
N
,
M
5
6
/
DEL
?
7
8
9
3
,
0
1
2
SEND
HOME
F4
F5
F6
PRINT
BREAK
-
ESC
Fl
F2
F3
F9
FlO
Fll
RETURN
ENTER
F7
F8
! ! ! ! ! ! ! !
YO
Yl
I CTRL
Y2
Y3
SHIFT
I
ALPHA
Y4
Y5
Y6
IFUNCT I
! ! ! !
FIGURE 6
KEYBOARD X-Y t'IATRIX
13
ARRA~GH!EKT
1'7
Keyboard
Inte~face
Communication between the main control board and the keyboard
controller is asynchronous. The standard asyr,chronous format used
by the 950 (Figure 9) consists of one start bjt, eight data
bits,' and one stop bit. The baud rate is set to 1200 bit,s/sec.
~
Control
Board
~.
~
,
Keyboard
Controller
8048
or
8035
•
(
Keyboard
(
f
Figure 7
Keyboard Interface
(
(
Keyboard Scanning Method
The keyboard microprocessor (8048 01 8035) drives the scan lines
(X lines), one at a time, to a low vo1ta~e. The return lines (Y lines)
are tested by the microprocessor.
The keyboard matrix output ports (10 through 14, 20 through 27)
latch the XO through X12 lines to the keyboard. The connections are
shown in Figure 7.
Whenever a low voltage is detected on a Y input line, it means
that a key has been depressed. That key is at the intersection of
the driven line (X) and the detected line (Y).
PORT 1
X12
PORT 2
XII XIO X9
X7
X8
X6
X5
X4
X3
X2
Xl
XO
TO KEYBOARD
FIGURE 8 8048 PORTS
The return matrix lines (Y lines) from the keyboard are read
by the microprocessor's data bus (DO through D7). The connections
are shown in Figure 8.
DBO
DBI
DB2
DB3
DB4
DBS
DB6
DB7
II
YO
•
Yl
II
Y2
of
1'3
..
..
..
...
....
FRml KEYBOARD
Y4
YS
Y6
1'7
FIGURE 9
15
8048 DATA BUS
Basic Scan Routine
Starting the scan routine resets the transmit flag and enables
the external interrupt for receiving status from the control board.
(
The keyboard matrix is scanned from the top row to the bottom
row. As soon as a key is pressed, the row is tested bit by bit, from
left to right. The matrix key codes are immediately encoded and
stored in.two registers (NEWKY 1 and NEWKY 2).
If the results of a matrix scan indicate that more than two keys
are depressed, the program enters a delay loop for 11 ms. Meanwhile,
the whole matrix is read once again to verify that the key is still
depressed. After the key is proven to be valid, the microprocessor
sends the proper code to the terminal.
If the depressed key is a repeat key, the last portion of the
scan routine controls the length of the repeat delay (0.5 sec.) and
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2026600
17
1
Al
IC 74LS86
2026800
I
I
NOTES:
.
TITLE
PCB ASSY 950 CONTROL BOARD
IJATE
11-11-82
0"1eleVideo Systems, Inc.
_...,--
,
"
-,... ..,--..
...
~
lTHI/
FINn
NO.
18
"-'
~TY
PLR
ASS~I/
RLrrRLNCLI
({LV LLVLL
Ill: S I CNATO I{
B
19
1
6
20
21
22
23
2
2
1
3
24
25
26
4
1
2
27
28
29
2
1
1
30
31
32
4
1
1
33
1
A53
A55
34
35
36
3
1
1
A49-51
1\54
1\14
37
1
1
OSC-1
A41
38
1\62
A20,43-46,59
A3,4
A22,23
A18
A19 pl,64
1\65-68
A24
A39,48
A40,57
A47
A56
1\25-28
A34-37
~
N()~ILNCLAT!JRLlIlESCl{
II''!' I ON
PART NLJMBERjRHI1\RKS
Ie 74LS139
Ie 74LS157
2027200
2027400
Ie 74LS163
2027600
Ie 74LS166
Ie 74LS173
IC 74LS174
2027800
2028000
2028200
IC 74LS367
IC 74LS374
IC 75l88N
2028600
2029000
2029200
IC 75189AN
IC TILl17
IC 4N38
2029400
2029800
2035000
IC 2114ICB RAM
IC 6116 RAM 150ns
2035800
2049200
2049600
2049800
IC 6502A Micro
IC 6545 Cantr CRT
IC 6551 Hlllz UART
IC 6522A
IC 74LS245
CRY Kl114A 23.814MHz OSC
IC 2532 [PROM FOOD Sys Prg9 C O
II
I
I
I
.
2155700
2050200
2036200
2035200
8000043
NOTES:
.
TITLE
!lATL
PCB ASSY 950 CONTROL BOARD
~
------
- ----------- -------
-----
11-11-82
O. 1eleVideo Systems, Inc.
I
ITEM/
QTY PER
Flf\ill
J\SS~I/
ilLS I (;NJ\TOR
B
1
1
1
NO.
39
40
41
RI:FFRLNCL/
Rl:V LJ:VH
A33
11.32
A42
.'
42
43
1
1
44
45
46
47
2
1
' 2
48
1
2
1
20
49
50
51
11.15
11.17
R6,41
R32
R2,33
R21,22,29,31,
35-37
R4
R42,43
R34
Rl,3,5,8,9,10,14
15-20,23-25,38,
40,44
R11,28,39,45,46
R26
R12
RPl-4
7
52
53
,54
55
5
1
1
4
NO~lLNCL/\TIJRE/IlLSCR
I PT ION
IC ROM Up Char Gen
IC ROM Low Char Gen
IC 2532[0000 EPROM Sys
PART NUMBER/R01ARKS
8000002
8000003
8000044
Prog 950
IC 74LS42
IC NE555
2026000
2030200
Res CP 750 Ohm 1/4W 5%
Res CF 51K Ohm 1/4W 5%
Res CP 68 Ohm 1/4W 5%
2031700
2032300
2051100
Res CF 4700 Ohm 1/4W 5%
2053100
Res CF 270 Ohm 1/4W 5%
Res CF 330 Ohm 1/4W 5%
Res CF 510 Ohm 1/4W 5%
Res CF 1000 Ohm 1/4W 5%
2051300
2051500
2051900
2052100
Res
Res
Res
Res
2052700
2032100
2031500
2042700
CF
CF
CF
PK
3300 Ohm 1/4W 5%
lOOK 1/4W 5%
1M Ohm 1/4W 5%
lK Ohm 8 Pin SIP
NOTES:
.
TITLE
PCB ASSY 950 CONTROL BOARD
DATE
11-11-82
•.:IeleVideo Systems, Inc.
.
,.".,
--,
~
~
ITEM/
FIND
NO.
56
57
58
QTY I'LR
l~rHRENCIJ
REV LEVU.
IlLSIGNATOR
B
2
R27,30
R7
1
59
60
61
62
63
64
- 65
66
67
68
69
70
71
72
73
ASS~I/
'-'"
NmIENCLATURE/nESC1~
I PT ION
PART NUMBER/REMARKS
,',
Res CF 510 Ohm 1/2W 5%
Res CF 22 Ohm 1/4W 51
2045100
2033500
J
2
1
1
Ql,4
Q2
Q3
Tran 2N2219A
Tran 2N3019
Tran 2N2907A
2045300
2045700
2045900
4
1
Dl-4
D5
Diode IN914
Diode IN4001
2047500
2047700
I
2
SI,2
Switch 10 Pos Dip/20P Side
Adj
2096800
74
75
NOTES:
.
TITLE
PCB ASSY 950 CONTROL BOARD
DATE
11-11-82
---------
O.1eleVideo Systems, Inc.
,
I
,
ITEM/
FIND
NO.
. 76
I 77
78
80
81
82
83
,
84
85
86
87
B
REFI:RENC!:j
DESIGNATOR
1
9
3
3
R13
XA32-37,41,42,S2
XA49-S1
XAS3-SS
Res CF
Socket
Socket
Socket
2
2
1
1
3
P3,4
P2,S
PI
P9
Ql,2,4·
Conn 2SP PCB D-Sub Fern
Plug SP Str Waf
Conn PCB RJ11 Fern (AMP)
Plug 2 P Str Waf
Insu1 Pad Tran 300S-A Large
Qry PER
ASS~I/
REV LEVEL
I
NOf-IENCLATUREjIlESCR I PT ION
47K
24P
28P
40P
Ohm 1/4W 5%
IC Dip
IC Dip
IC Dip
PART NUMBERjRHfARKS
2033700
2098401
2098404
2098402
2097800
2098802
2097900
2098800
2180800
NOTES:
TITLE
PCB ASSY 950 CONTROL BOARD
------ - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - ---------
DATE 11-11-82
.~l£leVideo Systems, Inc.
(
THI/
; 11\ II
.Il.
I~n
H2
/'U~
AS91/1~I:V
IU: F U{/;t\CJ:/
I.U'l:I.
IlI:SI C:\ATOn
~mIU\CI.ATIJIU./ IlESCR
II'T IOt\
PART t\LJr.IIU:R/RUIAIU\S
1
..,
3
-t
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
1
1
1
48
1
1 '7
.'
1
1
-t
1
2
1
1
5
C23
C26
C20
C27-55,57-75
C22
C4-19,25
Cl,2,3
C21
C2-1
Cap
Cap
Cap
Cap
Cap
Cap
Cap
Cap
Cap
Al,4,38,42
A2
C3,22
AS
A6
A7,12,16,21,28
IC
IC
IC
IC
IC
Ie
r.lica 20pf 50V 10'),
Tant 4.7uf 16V 10~
Cer .luf 50V 10\
Cer .01uC 16V 20~
Elect IOuf 16V 20'1,
r.lono 330p f IOOV 20t
Elect 22uf 50V 10%
r.lono .0ltiC 50V JO%
Mica 47pf 50V 5'1,
74LS367
7-1I.S42
6116 RA\I 150ns
4N38
65-15 ContI' CRT
74LS157
r-;OTES:
2024300
2027500
2030100
2028700
2027300
2029300
2026100
2028900
2024900
2028600
2026000
2049200
2035000
2049800
2027400
.-.
"_..
.
-
PAGE 1 OF 4
TITLE
PCB ASS)' CONTROL BOARD 950 GATE ARRAY
UA1EI1_11_82
O.1eleVideo Systems, InC.
v
THI/
Ir\J1
o.
22
23
24
25
26
27
28
29
30
31
-,
.)-
33
~
(~TY
1
1
3
1
:)(1
1
37
1
38
39
40
1
41
42
1
ASS~I/
REV 1.I:\1E1.
I~t:
F I: RU,Ct:/
ilLSIC~ATOR
B2
2
1
1
1
1
2
2
34
35
I'I.R
1
1
]
1
~
r-.;m.IEr\CI.ATLJRE/IlESCR I PT IOr\
PART
:\lI~IBER/RHIARI\S
A9,32
AI0
All
A14
A25
A18,23
A19,24
IC
IC
IC
IC
IC
IC
IC
74189AN
TIL1l7
6502A ~licro
741.500
2532 EPRml FOOO Sys
75188N
74L532
2029400
2029800
2049600
2024200
8000043
2029200
2025800
A26
A27
A29,33,36
A34
A37
A35
A39
A43
A45
A20
IC 741.5245
IC 741.5374
<.
IC 6551 UART Ulllz
IC G/;,\ 950(A)
IC Glf\. 950(B)
I C NE,555
IC 7406
IC 6522A
CRY 1\1114A 23.814~1I1: 05C
IC 2532 EOOO EPRm.1 Sys
2036200
2029000
2155700
2057600
2057800
2030200
2034800
2050200
2035200
8000044
A31
A30
IC ROM UP Char Gcn
IC ROM Char Gcn Low 950
~~
-
I,
8000002
8000003
.,
,
NOTES:
PAGE 2 OF 4
TITLE
,
.,
.,_, PCB ASSY COt\TROL BOARD 950 GATE ARRAY
!lATE
11-11-82
O:IeleVideo Systems, Inc•
!\. _oJ
'-..
. ...
- ~)
IlU-11
I-I :-'11
\().
43
4 ·1
45
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5
3
10
11,34 ,3-:' ,-t:~
\ 1\ 29 • :>:-i :> ()
XI\ -;; ,8 13,15,17,
20,22 25,:>0,31
\J\(J,
4h
47
1
Ph
48
2
sIn ,2
49
'J
<-
\mll.\CI.,\lIJIU / vRllS("I{ II'T
I ()\
PAin
Socket IC 40P H: DIP
Socket I C ,28P Ie lJIP
Socket IC ~.1P Ie DIP
\LJ~IHLH
/
I
I{ nt' In.s
2098402
2098404
2098401
I
I
P3,4
Socket 14 Pin Ie DIP
S~ 10 Pos DIP/ZOP Side Adj
Conn 25P PCB D-SlIb Fern
2098403
2096800
2097800
1
PI
Conn PCB IU 11 Fern (MIP)
2097900
1
P2,5
Plug 51' Str \'iar
1
Q3
Insul PaJ Tran 3005-A
2098802
2180800
58
59
60
1
Roll
61
7
Rlh, 17,28-30,34,
...
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Res CF 33 1/4~ 5~
Res CF 11\ 1/41\' 5 ':,
!
50
51
52
53
54
55
56
57
2034500
,
.
2052100
PAGE 3 OF 4
PCB ASSY COf\TROL BOARD 950 GATE ARRAY
DATE
11-11-82
O.1eleVideo Systems, Inc.
~-~--
,,'
-------
i
I
t\OTES:
TITLE
1
--.~--
v
~
ITEr-I/
I:
11\ Il
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QTY I'LR
62
63
64
65
1
1
1
2
66
5
13
67
'68
1
69
1
-
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I
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ADDRESS
~
RAM
~ ......
R/W
fJI
DISPLAY
n_
l 1
~
I..
DATA BUS
CHARACTER~
GENERATOR
ROM
AG-A2
V
~IPARAllEl ~I
~
CLOCK
I
.
n ____ • L_
CIRCUITRY
DOT C OC!\
I
I
1-
VIOEO
~
§
OUTPUT
I
SERIAL
KEYBOARO
DATA
CIRCUITRY ; - - COIiPOSITE
VIDEO
EXT
MUX
tt
u
IIAIN PORT lORlNTER
(HOSTI
PORT
11I
lOAOE lORINT
%
<
925 CONTROL BOARD
BLOCK DIAGRAM
Figure 4-1
6
..
~
<
..
~
TO VIDEO AMP
1125 MONITOR
FOR EXT MONITOR
~----
FfFf
! i'OM
Fnoo
Read
Only
II 1
ROM /I 2
03
02
01
00
I
'"
PROGflAPli DATA
EFFF
EOOO
OFFF
0000
Unu5ed ROM /I 1
I
04
05
06
07
S
R
PROGRAM DATA
g[b
Unused ROM /I 2
'"
BFFF
Unused 1/0
"I
Qnn4
Write
Control Latch II 2
Read
Dipswitch Port
Read
Dipswitch Port
Write
Control Latch 1/ 1
--
Soare
Read/Wr
*2
*1
Oispla
9003 Mode
BOWl
WOB
Bell
9002 SP/MK
OlE
Pur.
Timeout Keyc llCk
Blank
OnlOff
Baud
Rate 3
Baud
Rate 3
60/
50Hz
DTR
Baud
Rate 2
Baud
Rate 2
Cursor
Under
iMonltor
Mode
Spare
Baud
Rate 1
Baud
Rate 1
Blln"K
Clock
Baud
Rate 0
Baud
Rate 0
l'age
Print
Exten.
Control Register
9001 Stop
Bits
9000 CPU
Reset
Rr
Stop
8063 Bits
BOWl
WOB
Word
925/
Length 920
925/
BiDirec. 920ATT
Word
lnth 1
Rcvr--Clk Baud
Word
lnth 0 Source Rate 3
Baud Baud
Rate 2 Rate 1
Baud
...
Rate 0
ReadlWr
Command Register
8062 Par.2
Par .1
Par. Q
Xmit 0
OTR
Read/.k
Status Register
8061 Read:
ReadlWr
Transmit or Receive Data 8060 Read:
Read
Dipswitch Port II 5
8050 Not Used
Write
Reset IRQ
Rn4rl
Read/Wr
Edit
Norm/
Xmit 1
Frhn
I~~~
Status Reg is ter
Write: Program Reset(No Data)
Receive Register
Write: Transmitter Register
Cursor Cursor
0
1
DTR
SRTS
l5aua l5auCl
Rate 2 Rate 1
Read/Wr
Command Register
8032 Par.2
Par.1
Par.O
Read/Wr
Status Register
8031 Read:
Status Register
Xmit 0 Rcv
OTR
IRa
Write: Program Reset(No Datar
Read/Wr
Transmit or Receive Reg.
8030 Read:
Receive Register
Write: Transmit Register
Norm/
8021
Address Register
(Contains Reg. Number)
8020
REGISTE~
Char
Char
8010 Set 1
Set 0
8000 Not Used
On/Off
Not Used
Line/Pg Timeout 601
Att. - Blank
50Hz
*4
Dipswiteh Port
Read
Dipswitch Port , 3
Unused Display
RM1
OISPLA; PARAMETERS
I
I
ACIA
Xmit 1
Echo
Read or Write
Regs 0-31
Read
I....
l5auCl
Rate 0 I"
Control Register
Revr Llk 'l5auCl
Word
Lnth 0 Source Rate 3
Write
AClA
) 1/0
112
(Keybd 1
NU UAIA
Word
Lnth 1
.,
Main
Not Used
Stop
8033 Bits
Read/Wr
Printer
III
(Host)
(
,;
) em
NUMBER
Keyc 1 ick
Not Used
CRI
COI"fn
Comm
CR-lF Mode 1 Mode 0
Test
I
...
7FFF
4COO
Page 2
4BFF
4800
47FF
0 isp
RAM
Page 1
,;
4000
3FFF
.,
Unused Sys. RAM
Sys.
RA~1
0400
03FF
0000
VARIABLE PROGRAM rTA
1
925 MEMORY MAP
Table 4-1
,;
(
I
8
I
7
I
6
I
4
5
I
3
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5'70
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CONTROL
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LOGIC
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CRT CHIP
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-1-
1st PAGE
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VIDEO GENERATION
2nd PAGE
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-I
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VID\o
ll.GNAY,.
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.J
The CPU has control over all functional sections of the terminal via a
data/address bus and additional control lines.
The Display and Communi-
cation sections have some circuitry that runs independently of the CPU.
(
The Display section refreshes the video continuously, automatically.
The Communication section can send and receive words at the serial level
without CPU intervention.
The CPU ia the Intel 8035.
(See Appendix A, 8035 Specification)
The
bussed expansion capability of the CPU is used in order to provide external
program memory, data read/write memory, display memory, and memory-mapped
1/0.
Depending on firmware requirements 2K or 4K bytes of external program
ROM can be accommodated.
(Instead of the 8035, it is possible to use
an 8048 or 8049 CPU, thus lK bytes or 2K bytes, respectively, of external
(
program ROM memory can be omitted.)
In addition to the internal data memory of the CPU, there is a
25~
x 8
Data RAM (two 2111's) external to the CPU that is usable as read/write
storage by the firmware.
The characters being displayed on the screen are accessed by the CPU
via two 2K-byte blocks of read/write memory (RAM).
This memory is on the
same external data/address bus as the 256 x 8 Data RAM and is accessed in a
similar manner.
In addition to the normal read/write control lines, the
Display RAM requires that the address multiplexing logic be properly
controlled by the CPU for transfers to/from the display RAM.
The I/O Signal lines on the CPU chip that are not used for the expansion
-2-
data/address bus', are used for various control and status function ••
Additional I/O data, control, and status ports are gained by use of the
expansion bus.
Part of the data expansion
theae Input and Output capabilities.
~ddresses
are u.ed to implement
(This is known as memory·mapped I/O.)
Thus, these I/O ports are treated by firmware in a manner similar to the
RAM accesses, but are used for I/O transfers.
Via the I/O (direct and memory-mapped) the CPU interfaces to:
and
(1)
the CRT chip and other display circuitry
(2)
the UART and other communication circuitry
(3)
the keyboard.
The display I/O gives the CPU control over the CRT chip (including initializing
the CRT chip. reading/writing the cursor position, and scrplling) and some
video display circuitry (including a FORCE BLANK control),
Once initialized the
CRT chip and other display circuitry can automatically
perform the continuous refreshing required of the CRT by generating the
video, horizontal sync, and vertical sync signals required by the CRT.
The communication I/O gives the CPU control over the UART chip {including
initializing the UART's mode and sending/receiving characters on the word
level) and some other communication circuitry (including printer port
control, BREAK control, and control over the RS232 'ready' and 'clear'
types of Signals.
Once initialized the UART chip and other communication circuitry
automatically perform the parallel-to-serial. serial-to-parallel. and
signal level conversions required for the serial interfaces.
-3-
The Keyboard I/O allows the CPU and its firmware to scan the switch matrix
that is connected to the keyboard connector.
.
~ )
A clock generator provides the CR1lchip with the exact clock frequency
required.
Additionally, frequencies are tapped off for use by the CPU
and the communication baud rate generator.
Accessable switches and jumpers allow the user to select many option.
and configurations.
Operation of the above system capabilities is described in more
detail in the following sections.
Page references are to the schematics
of this terminal controller module.
(
-4-
2.
OPERATION OF THE CPU INTERFACES
The CPU is the center of control in this terminal (system).
This section
describes the CPU, the expansion bus, and the interfaces used to control
the other parts of the system.
Sections 2.1 through 2.4 provides most
of the information required by the firmware programmer in order to control
the system.
2.1
CPU
The CPU (Central Processing Unit)
is the 8035 (A54, schematic page 1).
It is the Intel "Single Chip Computer". containing control circuitry for
program execution, as well as program registers, read/write memory, and
I/O ports.
The 8035, a member of the 8048 family of single chip computers,
is the version which does not contain the program ROM memory internally.
The
system could, if deSired, use an 8048 or 8748 (each of which has lK bytes of
internal program memory) or an 8049 (which has 2K bytes of internal program
memory).
Using these devices can eliminate the need for all or part of the
external program memory (A49 and A50, page 2).
implementation and cost trade-off decision.
The exact configuration is an
When using internal program'mem-
ory the EA (External Access) pin must be grounded by installing jumper WI (page 1).
Appendix A contains the current 8035/8048/8748/8049 specification.
CLOCK:
The CPU clock is the +6MHz (5.9535 MHz, more precisely) signal
produced by the clock generator (page 4).
(See Section 5.1.)
nected to the CPU Xl pin (A54-2, page 1).
X2 requires no connection.
RESET:
8S
It is con-
CPU power-up reset is effected in the normal manner by connecting
the I)lF eapacitor (Cl) to CPU pin 4 (RESET, A54-4, page 1) and to ground.
A resistor, internal to the cPU, provides the RC time constant.
-5-
ALE:
The Address Latch Enable (ALE. A54-ll, page 1) signal occurs once
during each CPU cycle (every
internal CPU cycle as well
of external cycles:
2.5~sec.).
This occurs during every
every external CPU cycle.
8S
instruction
fet~h
There are two types
and data read/write.
(i
ALE is used
for both in order to latch the 8 lower address bits.
PSEN: . Following ALE, for each external instruction fetch, the Program Store
Enable
(PSEN, A54-9, page 1) signal occurs, see Figure 2.1.
Th1.s causes
a byte to be read from the program ROM (see Section 2.3.1 and 4.1).
FIGURE 2.1:
IILE
INSTRUCTION FETCH FROM EXTERNAL PROGRAM MEMORY
I--I~-'u--l-'ev--I
I
--'L
1-1_ _ _ _.---1,....1
(See Appendix A
for AC/DC
characteristics.)
(
RD and WR:
FollOWing ALE, for each external data read/write, either
the BUS read (RD, A54-8, page
signal occurs.
1)
or the BUS write (WR, A54-l0, page 1)
This causes a byte to be either read from external data
memory or written to external data memory, see Figure 2.2.
FIGURE 2.2:
WRITE TO EXTERNAL DATA MEMORY
READ FROM EXTERNAL DATA MEMORY
J
---'r
L
r--'ce--l
M ----------------~l
Jr----------------
ALE
II-._ _ _
ALE
J
L
"'0
IUS
(See Appendix A for AC/DC Characteristics.)
-6-
FlOATING
(
This system uses these read/write cycles to perform external accesses
to Data RAM (Section
2.3.2)~
Display RAM (Section 2.3.3), and memory
mapped I/O (Section 2.4).
All other CPU signals are used as bus or I/O signals.
They are described
in other sections of this document:
PIN NAME
A54
PIN NUMBER
SIGNAL
Section
DBe~DB7
12 -+ 19
Data Bus
2.2
P2f-+P23
21-'24
Address Signals (4MSBS)
2.2.2
P24
35
+4Hz FLASHER
2.4.1
p25
36
-DCR
2.4.2
P26
37
-PTR RDY
2.4.2
P27
38
-HALF DUPLEX
2.4.2
INT
6
-VSYNC
2.4.1
Tl
39
-ADV BLANK
2.4.1
Tf
1
p1f~
P17
PROG
-CTS
{KEYBOARD
CONNECTOR P1- 8-+15
27.-.34
25
-RESETUART
2.4.2
2.4.3
2.4.2
Figure 2.2.1 CPU Signals
2.2
BUS
During the external CPU cycles described in Section 2.1, the Data/Address
bus signal lines carry the address information to the external components
and the data information to or from those components.
2.2.1
DATA
The eight data lines +DBe through +DB7 carry the data between the CPU pins
(A54-l2~19,
1 through 4).
page 1) and all of the external memory and I/O devices (pages
Additionally, during ALE, data lines provide the eight
-7-
least significant address signals to the D inputs of the address latch
(74LS373, ASI, page 1).
(See timing in Figure. 2.1 and 2.2).
The data
linea are pulled up to provide adequate high drive characteristics.
2.2.2
(
ADDRESS
There are twelve address lines, +A. through +All, used to address the
memories and memory mapped I/O.
The eight least significant address
bits are latched (in 74LS373, ASI, page 1) during ALE.
The outputs of
this latch provide
+A~
on pagea 2 and 3.
The four most significant addres8 bits are provided by
through A7, all of which are used by the memories
the CPU via the output pins
and +All.
P2.~P23
(AS4 - 21-'24) for +AS, +A9, +AlO,
Four 74LS04 inverters (of A67) buffer +.All and
+Al~.
which
. are used for memory and memory-mapped I/O selection.
All twelve Address lines go to the program ROMs (A49 and ASO) on page 2.
(See Section 2.3.1.)
The data's address space is used by the RAMs and the memory mapped I/O.
When +.All is high +Ae through +AIO address the display RAM, page 3, aee
Section 2.3.3.
When +All is low, and +AI' is low, then +.A. through +A7
address the data RAM (page 2, A52 and AS3, see Section 2.3.2).
When +.All
i® low, and +Al' is high, then the memory mapped I/O decoder (74LS42,
ASS, page 1) is enabled, see Section 2.4.
-8-
(
2.3 MEMORY INTERFACES
2.3.1
PROGRAM RCI1 INTERFACE
When external program instruction memory is required, then Ie locations
A49 and A50 (page 2) are used.
The types and
~onfigurations
of ROMs
used determine the operation:
CONFIGURATION
RCl-l
In A49
ROM
In A50
411·
NO EXTERNAL ROM
NONE
fn:
2K EXTERNAL ROM
LOCATED 0 .... 2K
f!3 :
~J4.
4K
fF5 :
4K EXTER NAI. ROM
.JUMpERS
W26
W27
NONE
D.C.
D.C.
oC
D.C
NONE
2316E
OUT
IN
OUT
IN
2K EXTERNAL ROM
LOCATED 2K~4K
2316E
NONE
OUT
IN
OUT
IN
EXTERNAL ROM
2316E
2316E
OUT
IN
OUT
IN
2332
NONE
IN
OUT
IN
OUT
Figure 2.3.1 ROM Configuration
W28
W29
D.C •• DON'T CARE
The configuration determines which instruction fetches will result in
external ROM accesses.
Note that an 8048, which has 1K of internal
program memory, will only execute external fetches for the lK to 4K
address range (unless the EA pin is pulled high).
Section 4.1 describes
the operation of the RCl-ls.
2.3.2
D~~A
RAM INTERFACE
The 256 x 8 Data RAM is selected when the external address is:
A9
D.C.
A8
A7
D.C.
byte select
Al
D.C. • DON'T CARE
which t in hex, is OXX • lXX • 2XX • 3XX, where XX is the byte select.
2.3.3 DISPLAY RAM INTERFACES
There are two 2048 byte display RAM PAGES.
displayed in standard operation.)
(Only 1920 bytes are actually
(four 2114's; A6, AS, AIO, and A12; on
schematics page 3) can be addressed when +PG SEL is set true (output bit •
-9-
to memory mapped I/O location 4,C; see Section 2.4.1.).
PAGE 2 (four
2114's; A5, A7, A9, and All; on schematics page 3) can be addressed when
(
+PGSEL is set false (i.e., to zero).
F'or whichever of the two PAGEs is enabled (by +PGSEL), the Display RAM
is selected when the external address is:
All
1
Al~A'
byte select
which, in hex, is 8XX-FXX.
Performing a read or write to external data
m~ry
in this address range
will automatically override the refresh circuitry's addressing of the
Display RAM. giving the CPU priority at all times.
Section 2.4.1 describes
how the CPU can be synchronized with the refreshing to accomplish accesses
only during blanking periods.
(
Due to hardware implementation efficiencies the addressing of the 1920
characters being displayed on the CRT is not a direct linear mapping
within the 2048 byte Display RAMs.
Table 2.1 shows 80 character by 24
line display with the corresponding Display RAM locations for each
character.
2.4
I/O CONTROL AND STATUS INTERFACES
All memory mapped I/O ports use the 74LS42 decoder (AS8, page 1) to
detect the +A2, +A3, +A10, and +All address lines.
+A2 and +A3 select
which port is being addressed, while the combination of +All • 0 and
+A10 - 1 is required for all memory mapped operations.
Additionally
the keyboard circuitry uses +Ae and +Al, and the CRT chip uses +Ae,
'+Al. +A4, and +AS for additional
addressi~g.
-10-
(
,
DEC-rO-----------15(16---------- 3l-f 32:.-----..:---:...--47148-----------63164:...-------------79
CHAR
ROW
HEX'1-----------F 10----------lF 20----------2FI30-----------3FI40--------------4F
ROW
CHAR
DEC
HEX
(")
()
1
1
2
2
3
3
5
5
4
I
I-'
I-'
I
6
7
B
9
10
11
12
13
14
15
16
17
1B
19
20
21
22
23
DEC.
POSITION:
4
6
7
B
9
A
B
c
D
E
F
1'1
11
12
13
14
15
16
17
800-----------------------------------------------------B3F EOO------------EOF
B40---------------------------------------------------- -87F E40------------E4F
88()-----------------------------------------------------BBF EBo------------EBF
Bcn--------------------------------------------------- --6FF ECO------------ECF
FOO------------FOF
9()O-----------------------------------------------------93F
940-----------------------------------------------------9TF F40------------F4F
9Bo--------------------------------------------------- --9BF FBo------------FBF
9C()-----------------------------------------------------9FF FC()------------FCF
AI)0-----------------------------------------------------A3F ElO------------ElF
A4'l-------------.--------------------------------------~7F E50------------E5F
ABo-----------------------------------------------------ABF E90------------E9F
ACO-----------------------------------------------------AFF EDO------------EDF
BI)O-----------------------------------------------------B3F FlO------------FlF
B4o----------------------------------------------------BTF F50------------F5F
B80-----------------------------~----------------------~BF F90------------F9F
BCn-----------------------------------------------------BFF FDO------------FDF
C'lO-----------------------------------------------------C3F E20------------E2F
E60------------E6F
c40-----------------------------------------------------C7F
c8o-----------------------------------------------------CBF EAO---~--------EAF
CC0-----------------------------------------------------CFF EEO------------EEF
DOO-----------------------------------------------------D3F F20------------F2F
D40---------------------------------------____________ --D7F
DBn---------------------------------------------------- -DBF
DCn-------------------------.----------------------------DFF
F60------------F6F
FAO------------FAF
FEO------------FEO
o
1
2
3
4
5
I-1l
0
tjn
0
r+tj
::r'tj
(1)
00'0
00
::s
no.
::r' ~.
III
III
II
12
13
14
15
16
17
IB
19
20
21
22
23
::s
tj()Q
6
T
3
9
10
(1)
(/)
Ot;:1
r+ ~.
(1) (/)
t-i
~
C3
tj'O
~
>C PI
N
N
.....
.....
'<
;~
.....
::S~
(1)0.
0.
t;:1tj
..... (1)
(/)
(/)
'O(/)
..... (1)
III (/)
'<
The 74LS42 (AS8) decoder must also be enabled by the delayed signal
which is the OR of the RD and WR signals.
(This delay provides ade-
()
quate data setup time for the UART.)
"c" input (A58-l) to the decoder, which
The WR signal provides the
causes decoder outputs 18-+3 to be "I/O writes" and 4"'7 to be "I/O reads."
I/O beyond the memory mapped I/O comes directly from CPU I/O pins.
All
of the I/O is described in Sections 2.4.1 through 2.4.4, below.
CRT CHIP AND bISPLAY CONTROL
2.4.1
CRT CHIP:
The CRT chip responds to the following memory-mapped I/O
Figure 2.4 .la CRT Chip Addressing
addresses:
11
0
10
1
0
1
ADDF ESS HT
6
5
8
9
7
D.C. D.C D.C D.C X.
D.C. D.C D.C D.C 0
II
~
0
ADDR IN
HEX*
RD
or WRT
CRT CHIP
OPERATION
SELECT CRT CHIP
WRT
WRT
WRT
WRT
WRT
WRT
WRT
RD
CONTROL REG
1
0
1
0
1
0
1
400
401
402
403
410
411
412
413
4
3
2
X
1 0
0
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
I
1
0
0
0
420
RD
Ii
1
0
0
1
421
RD
i. II
1
1
1
0
0
1
1 0
1 1
0 0
422
423
430
RD
RD
WRT
1
1
0
1
431
WRT
1
1
1
1 0
1 1
432
433
RD
RD
0
1
1
I
i
I
I
I
I
I
I
,
,11
,
1 D.C.
·0
D.C D.C D.C 1
0
0
i..
D. C.
:II
DON'T CARE
~"'Assumes
"
"
"
"
"
"
II
"
"
"
"
"
-
(
1
2
3
4
5
6
Processor Self Load
NOT USED
Read Cursor Char
Addr.
Read Cursor Line
Addr.
Reset
Up Scroll
Load Cursor Char
Addr.
Load Cursor Line
Addr.
Start Timing Chain
Non-Procelsor self
Load
NOT U ED
DON'T CARES • ,
The above CRT Chip operations are as defined in the 5027 CRT CHIP specifi-
cations, Appendix B.
In order to attain the 24 lines of 80 characters each
at either 50 Hz or 60 Hz, the Control Registers should be loaded by the
-12-
(
Figure
CPU as follows:
VALUE
50 Hz
CONTROL
REG IS TEll
68
43
f
1
2
3
4
5
22
32
6
17
40
97
2.~.lb
IN HEX)
60 Hz
68
43
40
97
f7
17
17
Section 5.2 describes the operations directed by the
registers.
-VSYNC:
Control Register
abo~e
control
The CPU receives the vertical synchronizing signal at the INT
input of the CPU (A54-6, page 1).
This allows the CPU firmware to perform
timed operations based on the very precise 50 Hz or 60 Hz -VSYNC 8ignal. '
-ADVBLANK:
The CPU can synchronize to the displaY'8 blanking
sensing this signal.
t~e
by
This allows the CPU to perform Display RAM accesses
only during blank times, if desired. to avoid visable effects on the display.
When the CRT CHIP is programmed with the standard values (as listed
above) the -ADVBLANK signal is 25 character time8 long (active low) during
horizontal blanking.
However, Display RAM acce88 by the refre8h circuitry
8tarts one character time before the end of -ADVBLANK.
This mean8 that
from the detected leading edge of -ADVBLANK the CPU has 24 character
times (less the sampling period) during which it can be guaranteed blankinl.
Each character time is 588 nsec. which mean the CPU has l4.lJLsec (le8s
the Tl sampling period) to perform the Di8play Ram read or write without
effecting the refresh logic.
+4Hz FLASHER:
The CPU firmware is to generate this output at P24 (A54-35) by
using the -VSYNC interrupt input (see above) and dividing down appropriately.
+4Hz FLASHER is used to flash the Curaor (if jumpered to do so by inserting
W25) and is divided by 2 to generate the 2 Hz signal used to gate the
blinking video fie1d(s) on ana off.
-13-
+FORCE BLANK:
The CPU firmware can force the video to be blanked by
outputting a 1 on this bit.
+FORCE BLANK is part of the 74LS174 Output
Port (A47-1S, page 1) which is loaded by performing the memory-mapped
I/O write to location 4ft (HEX) or, more
Address Bit:
11
Value:
o
10
9
8
7
precis~ly,
6
5
~
4
3
2
1
lDCDCDCDCDCDC
1
100
DC • OON'T CARE
Data bit 5 is the +FORCE BLANK bit.
Firmware would normally keep an
image of this port in RAM, such that only the bits of interest can be
changed without affecting the others.
A summary of output port 40CH is:
Output to 40CH
Bit
Signal
7
DON'T CARE
6
OON'T CARE
5
+FORCE BLANK (see above)
4
+SEL LPT
(see Section 2.4.2)
3
.. BREAK
(
"
"
11
)
2
-RQS
(
"
"
"
)
1
+BEEP
(
"
"
2.4.4)
~
+PG SEL
(see below)
+PG SEL:
Figure 2.4.1c Output Port
40CB Summary
(
The CPU firmware selects which 2048-byte PAGE of display RAM is
to be displayed.
(Only 1920 characters are actually displayed.)
This
also selects which RAM is accessed by the CPU via the Display RAM addresses
(Section 2.3.3).
select PAGE 2.
+PG SEL is set to a , to select PAGE 1 and is set to a 1 to
This control bit is data bit' on output port
described under +FORCE BLANK. above.
-14-
4~
as
2.4.2
UART AND COMMUNICATION CONTROL
UART CHIP:
The UART Chip responds to the following memory-mapped I/O
addresses:
ADDRESS BIT
ADDR
IN HEX*
READ
or WR~
UART
OPERATION
404
READ
Read Data Enable
DC DC
408
WRT
Write Data Strobe
DC DC
408
READ
11
10
9
8
7
6
5
4
3
2
0
1
DC
DC
DC
DC
DC
DC
0
1
DC DC
0
1
DC
DC
DC
DC
DC
DC
1
0
0
1
DC
DC
DC
DC
DC
DC
1
0
1
0
Status Word Enable
!Data
~ Status
3
2
1
0
DC •
DON'T CARE
DON'T CARES •
* Assumes
e
FE, FRAME ERROR
PE, PARITY ERROR
TIttT» TRANSMIT
BUFFER El-lPTY
DTA, DATA
AVAILABLE
Figure 2.4.2 UART Chip Address
The above UART Chip operations are as defined in the UART specification
in Appendix C.
The hardware operation of the UART interface is described
in Section 6.
+RESET UART:
The CPU firmware can pulse this line by using I/O expander
instructions (which strobe the PROG output pin of the CPU, A54-25, page 1).
This signal is connected to the UART's RESET input.
+SEL LPT:
The CPU controls this signal by performing a memory-mapped
output operation to address 40CH with bit 4 baing +SEL LPT:
-15-
Output 40CH
.ill.
Signal
7
DON'T CARE
"
"
6
(
5
+FORCE BLANK (Section 2.4.1)
4
+SEL LPT
3
-BREAK
(see below)
-2
-RQS
(see below)
1
+BEEP
(see Section 2.4.4)
0
+PG SEL
(
"
"
2.4.1)
When set to 1, the +SEL LPT control line enables the line printer serial
communication transmitter (connector P4-3, PRT DATA (RS 232), page 2) and
disables the normal transmitter data driver (connector P3-2, TXD (RS 232),
page 2).
When set to
~,
(
+SEL LPT disables the printer transmitter and
enables the normal serial transmitter.
Add~tionally,
+SEt LPT selects
the line plfinter serial baud rate (as determined by switches 53) when set
to a I, or the normal serial baud rate (as determined by switches Sl).
This
allows the printer and normal serial interfaces to have independent baud
rates.
(Note that the UART does not receive serial data at the normal
baud rate when the printer is enabled.)
-BREAK:
This signal is controlled by the CPU using address 4_CH, bit 3
(see above).
-BREAK, when set to
line to the "break" state.
e forces
the selected serial transmit
This allows the CPU firmware to create the
desired Break condition for the desired duration.
-RQS:
This output bit (address
4~CH,
bit 2, see above) directly drives
the normal terminal serial interface's RTS (Request to Send, P3-4, page 2)
-16-
(
)
which also goes to the modem connector (P6-4, page 2).
Additionally
this can drive DTR (P3-20, page 2), if enabled using switch S5-3, 12.
This bit can also drive the printer's serial port TERM RDY lines
P4-8 and/or p4·6 (page 2) which can be connected by jumpers W12 and
Wll, respectively.
-DCR:
The CPU can input -DCR on I/O pin P25 (A54-36, page 1).
signal can come from any of 3 different places:
This
(1) "OCR (RS232)" at
P3-6 (page 2) which can be enabled by switch S5-1, 14; (2) "OCR (RS232)"
at P3-B (page 2) which can be enabled by switch S5-2, 13; and (3) Modem
connector p6-7 (page 2).
-PIR RDY:
The firmware inputs this signal via the CPU I/O pin P26
(A54-31, page 1).
It is the Printer Ready signal derived from connector
P4-20 (+PTRRDY (RS232), page 2).
-HALF DUPLEX:
The CPU firmware reads CPU I/O pin P27 (A54-38, page 1)
to determine the Full/Half Duplex mode.
When -HALF DUPLEX is
~
the firm-
ware should enter half duplex mode and when 1 the terminal should be in
full duplex mode.
-HALF DUPLEX is derived from switch S2-3,18 (page 1),
one side of which is grounded.
2.4.3
KEYBOARD I/O INTERFACES
The outputs to the Keyboard matrix consist of the 8 lines from the CPU
I/O pins Ple-.P17
(A54-21~34J
page 1) which are connected to Keyboard
connector pins Pl-8 through Pl-15, respectively.
from the matrix and 4 inputs from individual keys.
up by 1K ohm resistors to +5V.
-17-
There are 12 inputs
All inputs are pulled
Figure 2.4.3 Keyboard 110 Interfaces
The CPU reads Keyboard inputs via the i0110wing memory-mapped I/O reads:
11
ADDR
IN HEX'"
(
KEYBOARD INPUTS (P1 Connector Pins)
On Data Bits
7
6
4
3
5
1
2
0
r+-50Hz(ALPRA) 26 (SHFT) (Cm (FUNe) 16 20
3
4
6
5
25
"
"
"
"
" 17 21
4
3
2
1
0
1 DC DC DC DC DC DC
1
1 0
0
4~
1
1
0
1
4f)D
1
1
1
0
4f)E
"
"
24
"
"
"
18
22
1
1
1
1
4l'F
"
II
7
"
"
"
19
23
10
0
0
ADDRESS BIT
9 8 7 6 5
I
1 DCI:C DC DC DC DC
IX:
*
-
t Non Keyboard
,
DON T CARE
Assumes DON'T CARES - .,
Note that the 4 individual keys are input on all four addresses.
"-50 Hz"
is also input with these input operations and is to determine the terminal's
refresh rate upon power up, as described in Section 2.4.4.
Appendix D provides the descriptions of keyboard matrix with which this
(
system has been interfaced.
2.4.4
-50 Hz:
OTHER I/O INTERFACES
As described under Section 2.4.3, above. this Signal can be read
by the CPU firmware on memory-mapped I/O address 4f)C (as well as many
others) on data bit 7.
The firmware should sense this bit during power-up
and initialize the CRT chip accordingly (see Section 2.4.1).
When -50 Hz - f)
then the SO Hz mode should be established, else the 60 Hz mode.
This signal
is derived from switch S2 pins 17 and 4 (pin 4 is grounded).
+BEEP:
The CPU firmware can control the beeper (audio Signal, 1200 Hz) with
bit 1 of the memory-mapped I/O write to address 40CH (see, aiso, Sections
2.4.1 and 2.4.2 for the other control bits affected).
The +BEEP signal is
(J
-18-
gated with the +1200 Hz signal
(on page 1 with 74LSOO, A61-1,2,3)
which is then inverted to drive transistor Q2 which, in turn,
drives the 8 ohm speaker connected to P7-1,2.
When +BEEP is 0
the gating is such that the +1200 Hz is removed and the transistor
Q2 is put in the off (non-conducting) state.
-19-
3.
OPERATION OF JUMPERS AND SWITCHES
Presented below is a summary of the switches and jumpers used in the
system.
Included are short descriptions of their functions and refer-
ences to other pertinent sections of this document.
Though redundant,
this section should provide quick reference for software, hardware, and
systems technical personnel.
JUMPEF
iF
WI
DESCRIPTION
INSERTED
~SE
INTERNAL PROGRAM
MEMORY (ROM)
REMOVED
USE EXTERNAL
PROGRAM MEMORY
(ROM)
Scheme
Page
1
Reference
Sections
Comments
2.1
W2
NOT USED
W3
"
W4
"
W6
11>3 CONN:
~URRENT
~HORT
LOOP SEND
SERIES
510
KEEP 510
IN SERIES
2
6.3
l3>
W7
NOT USED
W8
"
W9
"
WlO
"
Wll
"
W12
p4- 6 NOT CONN
P4 CONN: TERM RDY
SENT
ON
P4-6
kRS232C)
2
6.3
W13
P4-8 NOT CONN
P4 CONN: TERM RDY
RS232C) SENT ON P4-8
2
6.3
(
Table 3.0 Summary of Switches and Jumpers
(,
-20-
JUMPEF
#
DESCRIPTION
INSERTED
Schem.
RFX)VED
Pa~e
I
Reference
Sections
Comments
P3 CURRENT LOOP SEND
~ONN
~O P3-25
W16
~NN "EMITTER END"
rr'0 P3-13
"EMITTER END"
NOT CONN TO P3-1
2
6.3
[»
W17
~ONN
P3-13 NOT CONN
TO GND
2
6.3
[3>
W15
fro
"COLLECTOR END"
P3-25
B>
"COLLECTOR END"no ,..2
CONNECTED TO
P3 "25
'EMITTER END"
2
NOT CONN TO P3_2c
W14
~ONN
"EMITTER END"
P3-13 TO GND
6.3
6.3
~
W22
Not used
W23
Not used
W24
Not used
W25
~URSOR FLASHES OFF
PN (INVERSE VIDEO)
CURSOR DOES NOT
FLASH AND IS
INVERSE VIDEO
5
5.4
W26
lFor 2332 ROM at A49
for all others
2
2.3.1, 4.1
W27
!For 2316E, 8316E, 2ne for all others
~OMS at A49 or A50
2
2.3.1, 4.1
W28
!For 2332 ROM at A49
for all others
2
2.3.1, 4.1
W29
or 2316E, 8316E,
2716 ROMs at A49 or
1\50
for all others
2
2.3.1, 4.1
W30
all character
~enerator PROMs
For no standard
character generator PROMs
5
~or
-21-
5.3
IrJUMJ:'ID
/I
INSERTED
DESCRIPTION
REMOVED
Scheme
Page
Reference
Sections
Comment.
(
OPTIONAL RESISTORS
R28
P3 CONN:
CURRENT LOOP SEND,
PULLS HIGH END TO
NOT PULLED UP
2
6.3
[9
+12V.
(
(
SWITCH
PINS
11
DESCRIPTION
Scheme Reference
CLOSED
OPEN
Page
Sections' Ccmments
COMMUNICATION PORT BAUD RATE SELECT (P3-2 and 3)
Sl
1-2
2-1
3-1
4-17
5-16
6-15
7-14
19,200
9,600
4,800
2,400
1,200
600
300
8-13
150
9-12
Sl 10-11
110
~
S2 10n1.l
II
NOT 19,200
NOT 9,600
NOT 4,800
NOT 2,400
NOT 1,200
NOT
600
NOT
300
NOT
150
NOT
75
NOT
110
75
SHORT OUT 270
IN SERIES WITH
CHARACTER VIDEO
6
6
6
6
6
6
6
6
6
6
6.1
6.1
6.1
6.1
6.1
6.1
6.1
6.1
6.1
6.1
KEEP 270 IN SERIES 5
(FOR COMPOS VIDEO)
5.4
OPEN FOR COMPOS
VID (SEE S2-1,20)
2-19
SELECT LOWER HAD SELECT UPPER HALF
OF CHARACTER GEN OF CHARACTER GENERATOR
ERATOR
5
5.3
3-18
HALF DUPLEX
FULL DUPLEX
1
2.4.2
4-17
50Hz
60Hz
1
2.4.4
5-16
PARITY IN TRANS
AND RCV
NO PARITY
2
6'.2; C (see also S2-9,12)
6-15
1 STOP BIT
(TRANS)
2 STOP BITS (TRANS) 2
7-14
NBI
-
"
52
BIT:~2_7.14:CLOSED
OPEN CLOSED
OP~
6.2; C
PER S2-8,13:CLOSED CLOSED OPEN OPEN 2
8-13 NB2 CHAR 11BITS ==
5
6
7
8.J
6.2; C
9-12
2
6.2; C (see also S2-5,16)
5
5.4
SEND AND RECEIVE: EVEN PARITY
ODD PARITY
1-20 a)+VIDEO P2-4
GETS COMPOS SYNC
TOO
a)+VIDEO P2-4 HAS
NO SYNC's
b)+TTL VIDEO BE- b)+TTL VIDEO P2-6
COMES VIDEO WIlli IS ONLY COMPOS SYNC
COMPOS SYNC(P2-6)
-23-
S2-10,11 SHOULD
BE OPEN FOR VIDEO
WITii COMPOS SYNC
1--.
SWITCH
If. PINS
DESCRIPTION
CLOSED
OPEN
NOT 19,200
19,'200
S3 1-20
NOT 9,600
9,600
2-19
4,800
NOT 4,800
3-18
2,400
NOT 2,400
4-17
1,200
NOT 1,200
5-16
600
600
NOT
6-15
300
NOT
300
7-14
NOT
150
150
8-13
75
75
NOT
9-12
i
S3 10-1'
NOT
110
110
5 1-14 CONN P3: RECEIVE ~ NOT RECEIVE DCR
DCR(RS232C) FROM IFROM P3-10
F3-10
2-13 CONN P3: RECEIVE po NOT RECEIVE DCR
DCR(RS232C) FROM FROM P3-8
P3-8
3-12 CONN P3: P3-20
(DTR) DRIVEN BY
SAME AS RTS (P3-4
P3-20 (DTR) NOT
4-11 CONN P3: P3-20
(DTR) PULLED TO
PULLED HIGH
+12VVIA 3.3K
5-10
CONN P3: RECEIVE DO NOT RECEIVE
6-9
SERIAL DATA
SERIAL DATA
RS232C
P3-3
RS232C
P3··3
,
Scheme
PSSl;e
6
6
6
6
6
6
6
6
6
6
2
Reference
Sections
Comments
6.1
6.1
6.1
6.1
6.1
6.1
6.1
6.1
6.1
6.1
~
')
6,3
tr;>
,
2
(I
6.3
h
rv
I
I
iS5 7-8
!
I CONN
P3: RECEIVE
SERIAL DATA CUR ..
RENT LOOP P3-12,
24
j..:.
2
2
00 NOT RECEIVE
SERIAL DATA CURRENT
LOOP P3 .. 12,24
)B>
6.3
1-
1_
0>
1--
(
6.3
CLOSED CONDITIONS OF SWITCHES WITHIN INDICATED SWITCH GROUP
ARE MUTUALLY EXCLUSIVE
,
IJ>'
MUTUALLY EXCLUSIVE CURRENT LOOP SEND CONNECTIONS FOR P3
P3 CONN: ISOLATED (W6 .. W-14. W-16 INSERTED) VS. I-SIDE GND (R28,
WIS, W17 INSERTED)
(/
4.
f!OGRAM MEMORY OPERA nON
The operation of the hardware for the program memory is described in
sections 4.1 (program ROM) and 4.2 (data RAM).
The functional inter-
face for system and firmware reference is described in sections 2.3.1
and 2.3.2.
4. 1
PROGRAM ROM
When external program memory is required by the CPU, the (P)ROMs at
locations A49 and A50 (page 2) are used.
The two ROMs have the 11 address lines and the 8 output data lines in
common.
(+A7~+A~)
The lower 8 address lines
come from the address latch
(ASl, page 1) and +AIO, +A9, and +A8 come from CPU port 2:
buffered), bit 1 (AS4-22) and bit
~
(A54-21), respectively.
data lines are connected to the CPU data bus
bit 2 (A54-23,
The output
(+DB7~+D~).
If the ROMs are 2316E types (i.e., 16K bits) then memory address bit All
,
(derived from CPU port 2 bit 3, AS4-24) selects which ROM is enabled when
-PSEN goes active.
+.All and its inverse are each gated with -PSEN (page 1,
A66-1,2,3 and A66-11,12,13) yielding -ROMICS or
active when -PSEN goes active.
goes active for +All-1.
-ROM~CS
-ROM~CS
-ROM~CS.
goes active for
one of which goes
+Al1-~
and -ROM1CS
selects the ROM at A50 (page 2, ASO-20).
-ROMlCS selects the ROM at A49 (A49-20).
Note that for 23l6E-type ROMs
jumper W29 is inserted (and W28 is not) in order to pass the -ROMICS signal.
Jumper W21 must be inserted (and W26 not inserted) for 2316E ROMs.
This
provides pin 21 (on A49 and ASO) with +SV, which is required for PROMs
(2716 or 2758) that may be used, and provides the high logic level for the
ROMs that have a positive chip select at this pin.
-25-
If a 2332-type (i.e., 32K bit) ROM is used then jumper W28 and W26
must be inserted while omitting W29 and W27.
This provides A49-20
(
with -PSEN directly such that this ROM is selected on every -PSEN cycle,
not just when +A1l=1.
Jumper W26 connects +All to A49-2l providing the
ROM with the required 12th address bit.
The negative chip select at pin 18 (on A49 and A50) is permanently grounded.
4.2
DATA RAM
The 2llLA (or BIllA) RAM chips (page 2, A52 and A53) comprise a 256 x 8
block of read/write memory. with A52 providing for data bits 7. 6, 5,
and 4 and A53 for bits 3, 2, 1
101-.104 (pins
11~14)
data bus +DB7
+D~
and~.
This data leaves and enters via
on A52 and A53, and is connected to the CPU
(see page 2).
The required 8 address bits are
+A7-++A••
(
This 256 x 8 RAM is enabled when +AlO and +All are both logic. by generating -DSCS (page 1, A66.4,5,6) which connects to A52-l5 and A53-l5.
-DSCS in conjunction with -RD pulse (from the CPU, page 1, A54-8) causes
the RAMs' outputs to be enabled (via A52 and A53 pin 9).
During -RD the
addressed data is then driven onto the data bus.
-DSCS in conjunction with -WR pulse (from the CPU, A54-l0) causes the
RAMs (viaA52 and A53 pins 16) to write the 8 bits from the data bus at
the addressed internal locations.
()
-26 ..
5.
5.1
DISPLAY OPERA nON
CLOCK GENERATION
The crystal oscillator (page 4) uses an astable 74S04 configuration to
generate the 23.814 MHz signal (at A55-4).
resonant at 23.814 MHz.
The crystal is series
The 7415109 flipflop
(A56-2~7)
divides the
basic clock by 2 to provide an 11.907 MHz "square" wave, +CLK (A56-6)
and -CLK (A56-7).
These two signals go on to the Video Generation
circuitry on page 5 (see Section 5.4) to provide the gating and shifting
clock for the basic dot of the video generation.
See Figure 5.1 for the timing diagram.
The 7415163 dot counter (page 4, A57) provides the display character clock
(+DC CARRY, A57-l5) to the video generation logic (page 5) and its frequency
equivalent, -DC2 (A55-l2), to the 5027 CRT Chip (at A23-l2, page 4).
The
counter's bits QA' QB' and QC generate the dot counter bits +DC0, +DCl, and
+DC2, respectively.
+Dc0 and +DC2 are used on page 5 by the video gener-
ation circuitry (Section 5.4).
(11.907
~
+DCl generates an asyrnetrical 3.402 MHz
3.5) signal which is used on page 6 by the baud rate generator
(Section 6.1).
+CLK is divided by 2 by the 7415109 (page 4, A56-10-.l5) to generate
+6MHz (actually 5.9535 MHz) on A56-10.
+6MHz goes to the CPU (page 1,
A54-2) to provide the basic CPU clock.
5.2
CRT CHIP OPERATION
The CRT 5027 Video Timer and Controller ("VTAC" or. "CRT CHIP") for SMC
Microsysterns Corporation is described in detail by the specification in
Appendix B.
This section describes the CRT Chip's specific operation
-27-
23.814 MHz
(ASS-4)
..-84 ns.
~
~
+CLK
11.907 MHz
(AS6-6)
I
l
E
+DC.
(AS7-14)
l
+DC1
(AS7-13)
J
F
9
A
B
(A57-12)
D
E
F
~
I
I
9·
A,
I
I
-----'I
+De 2
C
I
+DC CARRY
(AS7-1S)
r
Ji
I
I
r
I
I
- ul
.
~I- - - - - - - - -
I
I
1..----.-..41 .
+6 MHz
(AS6-10)
DISPLAY DOT TIME
6
7
I
1
2
l]
4
5
6
7
I
1
•
N
CD
•
FIGURE 5.1
CLOCK GENERATION TIMING DIAGRAM
j~
i
~
~
when the control registers are programmed for this system as described
in Section 2.4.1.
Clock Input:
The clock input (DCC, A23-12, page 4) to the CRT chip is at
the display character rate.
Figure 5.1.
It is the same as the inverse of +DC2 in
The CRT Chip Specification in Appendix B shows timing of the
output signals relative to the input clock.
Hardware Addressing Operation:
Accessing the CRT CHIP (page 4) is performed
by presenting the proper address inputs
(A~A0,
A23-2,l,40, and 39) and
then providing a negative strobe at the data select (DS. A23-9).
on the address inputs the chip performs a read (DB7-.DB0,
the CPU data bus
+DB7~+D~)
the CPU data bus
+DB7~+DB0).
or a write (the chips DB7
Depending
A23-l8~25,
drive
DB0 accept data from
Of the 16 addressable I/O registers (ports
in the CRT CHIP) 9 are output (write) and 7 are input (read) ports.
The
address table in Section 2.4.1 shows which ports are write and which are
read.
are:
Note that the address lines connected to the chip's address pins
+A5, +A4, +Al and
+A~
to the chip's A3, A2, AI, and
A~,
respectively.
Since the CRT Chip wants only one control strobe (Le., not both a read
and a write strobe) the read and write outputs of the I/O decoder (page 1,
A58) for address decodes "400" are logically ORId (by A43-11,12,13, page 1)
yielding -SEL CRT CHIP.
Chip (A23-9, page 4).
This signal provides the data select for the CRT
The "400" decoded signal, in conjunction with the
4 address lines, accounts for the I/O address locations (as presented in
the table in Section 2.4.1),
Operation of CRT Chip programming:
As stated in Section 2.4.1 the 7 control
registers must be programmed for either 50 Hz or 60 Hz
-29-
f~r
standard operation:
VALUE (IN B!X)
50 Hz
60 Hz
OONTROL
REGISTER
,
68
43
_yO
97
22
32
17
1
2
3
4
5
6
(
68
43
ltelfP
97
'17J7
17
Variations from this might be possible for special cases, but for 24 lines
of 80 displayed characters (at 50 Hz or 60 Hz refresh rates) it is necessary to use these values with the clock generation and video generation
circuitry provided in this system.
The above control register values provide the following
~arameters
to the
CRT Chip (see also the CRT Chip timing, Figure 5.2):
5.2.1 -- Control Register
Bits
7~_
150 Hzl
~
• Ni Horizontal Line count where Total Characters/Line .. N + 1.
Total Characters/Line" 68 16 + 1
(
.. 104 10 + 1
[60 Hzl
--Same--
5.2.2 -- Control Register 1
Bit 7;
Interlaced/Non-Interlaced
where 1 .. Interlaced;
Bits
" .. Non-Interlaced
150 Hzl
Bit 7 ... , Non-Interlaced
~O Hzl
--Same--
6~3
.. N; Horizontal Sync Width
where Horiz Sync Width Character Times .. N
(N .. 1-.15; N ..
[50 H~
'J
disallowed)
Hortz Sync Width Char Times .....§..
[60 Hz I --Same--30-
(
Bits 2..,
- N;
Horizontal Sync Delay
where Horiz Sync Delay Char Times -
(N -
150
1~;
Hzl
160 Hz I
5.2.3 -- Control
N
N - 0, disallowed)
Borb Sync Delay Char Times -
....L
·-Same--
Re~ister
2
Bit 7, not used (- .)
Bits
6~3
- N; Scans/Data Row
Where Scans/Data Row - N + 1
150
Hzl
Scans/Data Row .. 9 + 1
- 10 10
-I
--Same-T; Characters/Data Row
160 Hz
Bits
2~.
where T is defined in a table in the CRT Chip Specification
(Appendix B, last page).
For DB 2 .. I, OBI • •• DB • • 1 .the
Characters per Data Row • 80
150 Hzl
Characters/Data Row - f(T)
- f(S)
160
Hzl
--Same--
5.2.4 -- Control Rerister 3
Bits 7, 6 - Tj Skew Bits (Refer to 5.4)
where T is defined in a table in the CRT Chip Specification
(Appendix B, last page).
For DB 7 - 1, DB 6 - • the Skew Bits
are Sync/Blank Delay - 1 Character Time
-31-
Cursor Delay -
Iso Hzl
• Character Time
(
Skew Bits - f(T)
- f(2 1O )
- Sync/Blank Delay of 1 Char Times
Cursor Delay of no Char Times
160 Hz
Bits
5-;"~
;;1;.
I
--Sarne--
N;DataRows!Frarne -
=N+
where Number of Data Rows
(N
=~
150 Hzl
1
63)
~
Number of Data Rows
17 16 + 1
= 23 10 +
1
= 24
160 Hzl
--Same--
(
5.2.5 -- Control Register 4
Bits
7~~
~
N;
Scans/Frame
where, in non-interlaced mode,
Scans/Frame
150 Hzlscans/Frame
= 2N +
=2
0
256
22 16 + 256 10
= 2-34 10
+ 256
10
... 68 10 + 256 10
... 324 10
160 HzlscanS/Frame - 2'.7 + 256
- 14 + 256
(/
-32-
5.2.6 -- Control Register 5
Bits
7~
- N;
Vertical Data Start
where N • number of raster lines after leading edge of
vertical sync of vertical start position.
/50 Hzl
Vertical Data Start (raster lines) • 32 16
• 50 10
~ Vertical Data Start (raster lines)
=
17 16
• 23 10
5.2.7 -- Control Register 6
Bits 7, 6, not used (- .)
Bits
5~0
a
N;
Last Displayed Data Row
where N = Address of last displayed data row, N = 0 to 63
[ 50 Hzl
Last Displayed Data Row • 17 16
• 23 10
160 Hzl
--Same--
Figure 4.2 presents the timing of a frame showing the relationship between
the Valid Character Addresses (for the 24 aO-character rows) and the
Blanking and Sync signals.
The left and right edges correspond to the
start of Horizontal Sync, and the top and bottom edges (different for 50 Hz
and 60 Hz) correspond to the start of Vertical Sync.
The inner solid-lined
rectangle (24 Data Rows x ao characters) represents the time during which
the CRT Chip outputs valid addresses on
(A23-4,S,7,a), and
DR4~DR'
H6~' (A23-32~3a,
(A23-30,29,2a,27,26).
The
• to 79 on each scan across the ao character positions.
page 4),
H6~H'
R3~R'
lines go from
R3~R'
count out
the 24 character rows, covering all rows • through 23 on each frame (the
starting and ending counts are programmatically changed using the Last Data
-33-
~
~
START
HSYNC
50 Hz
r;;4
r-
~I
.~
I
~I
til
z:
Ul
...J,
~
til
Ul:
a:;
el:
~
a
&i
:z;
<
~
~
~
U
U)
..;;t
N
M
STAJlT
VERT
SYNC
•
..
N
=
0
In
~
N
M'
til
H'
H
<
til
...J
a'.
Ul
t:ol
:z;
....l
~
gj
,...
~:
N
0
&n
0
N
..
N
~.
I
CHARACTER
ADDRESSES
VALID
..(
~
..(
~:
CI
N
..j
..
N
:::t:
::t:
0
0'
-tJ
-tJ
I
~
~
c:l
H:
::t:
~~
~,
Ul
:>
fST
~~
~
a'.
..(:
~
~
u
til
tila'.
~,
~
H
....l
i
1 CH~r:!~ TIME (DI~.PLAY)
-eLK
A56-6
-u-
+DCCAR
I
I
A42-3
Display Dot Times
Shift
LJd
ADV DOT FF
A17-9
I
6 ] -Lll~]-=.;.,.Z--L..J......;:;
.. ~---L1_~~]L......5;;;.....~:.1...-1LI 7"J 1 [~2~= [3
IFrom
Reg
QH A2-13
(
DZ
Char Gen
I
I 04 I D:LI
J 0 ID?I P6 J D5
I
I
niLPi=I
~]:iiLl
I
QzIli I pZ-.ID6 ]
D5
I (I
5
I
=
041 D31
I
D6:I Dsln£:[Di.:i D2
I
[0
I
~i:L~~
I ~J:04I
D~I
NORM OOT FF
A17-5
First 3
Dot Positions
D1
1.
SELECTED VIDEO:
Is ELECTS
Clear Shift REG
AZ-9 ... A16-2
If
A19-3 '" 1
Dot Positions
ID0
IAnv DOT FF
o NORM
Last 4
OOT FF
I
0
SELECTS
ADV DOT FF
NORM DOT FF
=: J
(
FIGURE 5. 5:
VIDEO OOT
-44-
DISPLAY SIGNAL RELATIONSHIPS (VIDEO, BLANK, CURSOR, HSYNC):
The rela-
tionships between the various signals that directly effect the display
are shown in Figure 5.6.
The top portion of the diagram has the relative
character positions for the "display RAM", "character generation", and
"displaying video" activities.
(See Figure 5.3 for more details.)
Shown
in Figure 5.6 are the first few and last few character positions for a
horizontal scan line.
The following signals are controlled by CRT outputs:
(1)
RAM Accessing (display RAM address for indicated character)
(2)
-ADV BLANK (delay by 1 with respect to addresses)
(3)
CRV (delayed by 0 with respect to addresses)
(4)
HSYN (delayed by 1 with respect to addresses)
The delays are as programmed into the CRT chip, see Section 5.2.
-ADV
BLANK is delayed one more character time (by A35-2,5, page 4, as clocked
by +DCCAR) in order to line it up with displaying video.
This +BLANK
signal (A35-5) goes through an open collector driver (A14-12,l3, page 5)
in order to blank the video.
ADV BLANK and BLANK a:e used for addition
gating functions as described in other parts of this section.
Additionally,
-ADVBLANK goes to the CPU's Tl input (A54-39, page 1) to permit synchronization with the video by the CPU for performing accesses to the display
RAM without disturbing the display refresh.
(See Section 5.3.)
The cursor signal from the CRT Chip (A23-16, page 4) is delayed 2 character
times (by A35-9,12 and A34-1,12, clocked by +DCCAR, page 5) to line it up
with the video being displayed.
The +CURSOR signal complements the normal
video signal (using A21-l,2,3 and A21-4,5,6, page 5) including the effect
-45-
+DC CARRY
A')7-1,)
n
Jl
n
n
n- - j 5
n
n
n
II
n
n.
CHARACTER POS ITIO~S:
RAM ACCESSING
CHARACTER GENI·:RATlOr>;
ACCESS DIG
IllS I'll, Y I ~c
\' lill':ll
x
o
x
x
~
x
x
x
.)
I
o
71",
74
x
x
x
x
x
77
/~
7')
x
),
x
x
/h
; I
7K
lY
x
x
x
'.'.' (Bl ..A:\;~/SY:;C)
DU.r"
,
,
~
-AI>\'
RIA:;I\
/\.'1-17
=
1
~
I
.~
(C
_____________~I
'7~----------------~~
__________________
~
r---
- HLA:;I\
BlANK
S~·--ll-r-S-I'-IA-\-·---------------------,
- - - - - - - - - - - - - - - - - - - -_ _~
,\}')-')
',1'111 (TRS{lK :\T
CRV
A23-1h
L -_ _ __ _
POSITl(l\~-
__.... --;-__
--:-11 All \A NCr Il I~
«TRSO!{.\ Cl'RSPR
~
~)El~Y=ry
~
r ,
, 7~-------------------
___________--'1 (TKS()K
1). h PLA Y l
-
+{]IRSOR
,\]4-9
1"- r
(L _ _ _ _ _ _
~_:__-......,..._ _ _ _- - - .' (!10K SYNC lJELAY=)
-IISYN
AZJ-IS
+HSYNC (=11 ORIVE)
.'\1-3
J
~ ')0 1
Dl'TY (YCLE
55
lACTeAL
PORCH
FRONT
=
I
2
P2-1
,':Sec Section ').2 for CRT prt'gramming.
NOTE:
Sec Figure'). 3 f0r character p0si tion detai is.
FIGrRE S.h:
~.
DISPLAYED VIDEO RELATIOr\SlIIPS
~
~
of the INVERT VIDEO bit (A28-6 to A2l-2) of the control register.
Addi-
tional gating (at A18-ll,12,13, page 5) permits optional (by installing
jumper W2S) 4 Hz flashing (on-off) of the video at the cursor position.
For this option when the cursor is flashing "on" (A18-U-e), the ZeroIntensity driver (AlS-l,2,3, page 5) is disabled and "on" video is injected
into the video signal (at A19-l, page 5).
During Zero-Intensity this
causes video to be "on" (not because of the injected "on" video but because the Zero-Intensity signal, A32-6, disables the video driver, AlS-4,
5,6, through an inverter, A33-l,2,12,13).
During other (non-zero) inten-
sities the cursor "on" causes the character position to have all dots
"on" because of the injected "on" video.
This causes the character's
background to change (flash) to the same polarity as the character itself
(which is -already inverted once or twice by the +CURSOR signal and, possibly,
by the INVERT VIDEO control bit).
Horizontal sync (A23-lS, page
) is programmatically delayed in the CRT
Chip by 4 character times (1 for SYNC/BLANK DELAY and 3 for HSYN DELAY,
see Section 5.2) from the end of the last RAM address character position.
With video being delayed 2 more character times a 2-character "front
porch" is provided (see Figure 5.6 and Appendix B).
HSYN (A23-15) is
inverted (A36-l0,11, page 4) to drive a one-shot (Al-2,3) which generates
a horizontal drive signal (called +HSYNC) that goes to the video connector
(P2-l, page 5).
(-HSYNC is also used for other timing (on page 5) as
described in the paragraph below that presents the video control register.)
VSYNC (A23-11, page 4), which is inverted twice (A56-12,13 and AS6-I,2,
page 4) and driven (by A14-l0,ll, page 5) onto -VSYNC (P2-5), has the
timing as described in Section 5.2 and Appendix B.
-47-
(VSYNC signals are
also used for video control register timing, see below.)
-COMPSYNC (A23-
10, page 4) is inverted (AI5-11,12,13, page 5) and driven (by inverting
(
driver A14-8,9,
page 5) onto P2-6 •. Its main use is to provide the com,
posite sync to the multi-level video signal (by closing switch 52-10,11
and opening switch 82-1,20, page 5).
When the switch settings are made
then P2-6 provides +TTL VIDEO in addition to a TTL composite sync signal.
HALF-DOT-SHIFT LOGIC:
As described in Section 5.3 each scan line of each
character can specify a half dot shift characteristic for each the first
3 dot positions and the last 4 dot positions.
DI (from A3-l0, page 5)
selects the half dot shift for the first 3 dot positions (D1=1 selects the
advance dots, Dl=0 selects normal dots.
shift for the last 4 dot positions.
D0 (A3-9) selects the half dot
Section 5.3 shows a portrayal of
Dl and D0 are latched into A4S-2,5 and A45-l2,9
the 4 possibilities.
(respectively) by +DCCAR (A42-3 to A45-3 and A45-11) which is the same
time as when the shift register is loaded.
The outputs of A45-5,6 deter-
mine whether the normal or advanced dot is selected.
enables (via A18-4,5,6) the advanced dot (from AI7-9).
The Q output (A45-5)
The Q output
(AI7-6) enables (via AI8-l,2,3) the normal dot (from AI7-S).
+DC.a~
(inverted
~y
+DC2-l and
A44-12,13, page 5) cause (via A46-3.4,5.6 and A46-8,9,
lOtll) the selecting flip-flop A45-2,5) to take on the value of the flipflop that stored the D0 value A45-9.l2).
This occurs between the 3rd and
4th dot time (see Figure 5.1) causing the dot shift patterns shown in
Figure 5.4.
The dot-select gates (Al8-4,5,6 and AI8-l,2,3) have their
outputs OR'd (with other signals at AI9-2,4) to form the pre-complemented
video signal at Al9-6.
IN-STREAM VIDEO CONTROL REGISTER:
Six flip-flops implement a 4-bit control
register that captures video control information from the display character
-48-
(
stream.
As described in Section 5.3 the control information comes from
the outputs of the pipeline latch (A4, page 5) and uses up 32 (of the
possible 128) character encodings.
A control character is denoted by
having bits 6 and 5 equal to • (+DRD6 and +DRD5, A4-5,2) which is detected
by the gate A22-1,2,3, page 5.
(A44-l,2) to yield +CONTROL.
The output of this gate (A22-3) is inverted
The control register flip-flops are clocked
by signals that are essentially the same as +DCCAR (see Figures 5.l and
5.5) but are enabled only under the following conditions:
(1)
+CONTROL is true;
(2)
valid characters are in the character stream at the pipeline
register A4 (which is when the signal -ADVBLANK is high, see
Figure 5.6);
(3)
the intensity control bits (+DRDl,2) require that +DRD4-1 to
be clocked.
These conditions are gated (using A43-l2,l, A4l-4,5,6, A4l-8,9,lO,
A42-4,5,6, artd A42-8,9,lO, allan page 5) with +DCCARRY (at A43-5) and
-CLK (at A42-4 and A42-l0) to generate the clocking signals for the
UNDERLINE (+DRD,) and INVERT VIDEO (+DRDl) bits (as clocked from A42-6)
and the INTENSITY bits (+DRD3,2, as clocked from A42-8 which is inverted
by A44-l0,11, page 5).
CONTROL CODES:
BIT 6=', BIT
THEN START UNDERLINE
END
UNDERLINE
5-'
BIT '=1
BIT .-.
START INVERSE VIDEO
BIT 1=1
END INVERSE VIDEO
BIT 1='
IF ALSO BIT 4-1 THEN
START ZERO INTENSITY
BIT
•
2
•
START FLASH (2Hz)
1
1
-49-
3
mRMAL
BIT
3 2
1 ,
NORMAL
,
1
Bit' of control characters (+DR~, A4-9) is clocked
UNDERLINING:
(A29-ll) into the UNDERLINE flip-flop (A29-9,12, page 5).
If +DRDe a 1,
then, to prevent the control character position itself {which is blanked,
as described in the "SHIFT-REGISTER" paragraph above) from being underlined, a second flip-flop (A2B-9,12) provides a one-character delay.
The second flip-flop is clocked by +DCCAR at every character time.
If
+DRDf-., then the output of the first flip-flop (A29-9) clears the second
immediately (via A2B-13), causing the underline to disappear at the oeginning of a control character:
+DRDe-l
CTL
xxxxx [llI XXXXXXX
a'
CTL
rn
XXXXXX
X's are
Displayed
Characters
(\
Blanked
Control Character Positions
The actual underlining (as controlled by A2B-9) is gated (at AlB-8,9,10,
page 5) with +lOth Dot Row which indicates the last rastor scan line for
a character row (as denoted byA20-ll,12,13 and inverted by ABO-l,2,3,
page 5).
The output of the gate (AlB-B) forces a video "on" condition
(at A19-5).
(See also Inter-Scan-Line Storage,_ below.)
INVERTED VIDEO:
Bit 1 of control characters (+DROl, A4-6) are clocked
(A29-3) into the INVERTED VIDEO flip-flop (A29-2,5, page 5).
As with the
UNDERLINE flip-flop pair (described above), the INVERTED VIDEO has two
flip-flops (A29-2,5, and A28-2,5) which, when Bit 1=1, delay the effect
on the video until the following character, but when Bit la' they turn
off the inverse video immediately (using the second flip-flop's clear,
-50-
(
A28-l).
The actual inverting (as controlled by A28-6) i8 exclusive
OR'd with the +CURSOR signal (at A21-l,2,3, page 5) and the video signal
(using
A~1-4,5,6).
Thus the video may, in effect, be complemented
twice, once by the INVERT VIDEO control and once by the +CURSOR signal.
If the flashing cursor option (jumper W25) is not installed then the
presence of the cursor at the end of an INVERT VIDEO field will cause
ambiguity in visually determining the cursor position on the screen.
(See also Inter-Scan-Line Storage, below.)
INTENSITY CONTROLS:
When bit 4 (+DRD4, A4-l4) of control characters
equals 1, then bits 3 and 2 (+DRD3,2, A4-16,lS) are clocked (A3l-3,11)
into the INTENSITY control flip-flops (A3l-2,S and A3l-9,12, page S).
These flip-flops affect the intensity immediately when loaded.
When bit
3 (A3l-5) and bit 2 (A3l-9) both equal zero, this is detected (by gating
A31-6 and A31-l0 at A32.4,S,6, page 5) and causes a driver (AlS-I,2,3)
to zero the video.
(This driver may be disabled at the cursor position
at a 4 Hz on-off rate, if the flash cursor option, jumper W2S, is installed.
See CURSOR, above.)
When bit 3 and bit 2 both equal one, this is detected
and gated with a 2 Hz square ware (at
A33-~,4,S,6,
produce a video flashing (on-off) effect.
page 5) in order to
The gate's output (A33-6) inhib-
its and clears the dot shift register (via AI9-l0.8).
above.)
(See SHIFT REGISTER,
Any other combinations of bits 3 and 2 (specifically bit 3.2, • 1.0
or • •• 1) allow the normal intensity to be used.
INTER-SCAN-LlNE STORAGE OF CONTROL REGISTER:
The register AlO (page 5)
stores the CONTROL REGISTER values at the end of the 80th character at the
10th scan line of a character row.
At the beginning of each of the 10 scan
-51-
lines of the next character row the values in the storage register are
loaded into the control register flip-flops.
This allows UNDERLINE,
INVERTED VIDEO, and INTENSITY controls to carryover from one character
row to the next character row.
()
The storage register (A30) is loaded at
the end of the tenth scan line by gating -BLANK, +ADVBLANK, and +lOth
DOT ROW (all at A33-8,9,10,11, page 5) which, when all equal to 1, define
that the 80th character on scan line 10 is being displayed.
The gate's
output (A33-8) passes through A32-9,8 to provide one of the load enables
for the storage register (A30-9).
The other load enable (A30-l0) is
driven true by -10th DOT ROW (A20-ll through A32-l1,12,13).
In this way
the storage register is loaded with the control register bits -BIT0 (from
A29-8), -BIT 1 (A29-6), -BIT 2 (A3l-l0, and +BIT 3 (A3l-5) into storage
register data input 40, 3D, 20, and 10 (A30-l1,12,13,14), respectively.
Before loading the control register flip-flops at the beginning of each
(
scan line, all flip-flops are set to their initialized condition by the
-HSYNC (A36-10, page 4) signal:
UNDERLINE (A29-9) is set to • (via A29-l3)
INVERT VIDEO (A29-S) is set to • (via A29-l)
INTENSITY (bits 3.2 at A31-S,9) is set to
1,.
(via A31-4,13)
The outputs of the storage register are enabled (A30-2) by the combination
of +ADV BLANK and +BLANK (at A20-4,S,6) (except during VSYNC, see below).
These outputs go to the 4 control flip-flops causing them to preset or clear
in a manner appropriate with the stored bit value.
If a stored bit is high
at the output then the corresponding flip-flop is not changed because the
"initialized state" (see above) is already correct.
If a stored bit is low
()
-52-
at the output then the flip-flop is forced to the opposite of the "initialized state".
The flip-flops end up in the state indicated by the ItaraRe
register:
BIT #
INITIALIZED
VAWE
UNDERLINE
STORAGE
REGISTER
VAWE
INTENSITY
1
2
.
3
1
.
1
.,1
( .. -BITl) .,
1
I)
(m -BIT2)
1
(- -BIT.)
INVERT VIDEO
FINAL FLIP-FLOP
VAWE
1
.,
(- +BIT3) .,
.,
1
1
Figure 5.7 Storage Register Value
Addi tiona 11y , during vertical blanking, the signal -VSYNC (A36-l2, page 4)
causes (through A32-B,9,lO and A32-11,12,ll) both enables (A30-9,lO) of the
storage register be driven true.
+VSYNC (A36-2) forces the storage regis-
ter'e outputs to be disabled (at A30-1).
This causes the control flip-flops
to stay in their initialized state as forced by -HSYNC (from Al6-10, page 4.
to A29-1, A29-1l, A31-4, and A31-ll, page 5).
register to have the same values.
This also causes the storage
Following VSYNC these values are:
UNDERLINE - .,
INVERT VIDEO - .,
INTENSITY -
HALF.. INTENSITY
I,'
(i.e., NORMAL)
(-"PROTECTED" by firmware):
Bit 7 of every character (A4-12,
+DRD7, page 5) controls whether or not that character is displayed with
half intensity.
At the same time the shift register is loaded +DCCAR (A42-3,
page 5) loads (A16-ll. page 5) +DRD7 (A16-7) in a flip-flop whose output
(A16-9) is
dri~en ~by
A15-B,9,lO) through 510 ohms (R9) to the combined video
-53-
I
node.
With the driver's output (A15-8) low the combined Video is loaded
down more. causing the intensity level, if any, to be reduced.
(
COMBINED VIDEO:
The following open-collector drivers make up the combined
video Signal (A15-6, page 5);
Half intensity A15-8 through 510 ohm, R9
Zero intensity A15-3
Video (Dots)
AlS-6
BLANK
A14-l2
FORCE BLANK
A14-2
+FORCE BLANK's driver (A14-l,2) allows the CPU to blank the screen at any
time (to avoid unsightly display effects, for example, during massive display data accesses).
The CP.U writes a 1 in bit 5 to external data (memory
mapped I/O) address 40CH to cause the screen to blank.
52-l~20
For video without sync signals switch
is elosed.
(See 5ection 2.4.1.)
(
is opened and switch 52-10,11
Resistors R2 and R3 (510 ohms and lK ohm) provide the level
pullup capability.
The emitter-follower implementation of Ql provides a
high input impedance and a low output impedance which drives (through R4,
68 ohms) +VIDEO (P2-4).
A convenient ground signal is provided on P2-3.
For composite video (i.e., video with sync signals) switch 52-1,20 is closed
and switch S2-l0,ll is opened.
This puts a 260 ohm resistor (Rl) in series
with the previous combined video which prevents zero intensity from reaching
as low a level at 52-1.
Closing 52-1,20
allows composite sync (A14-8) to
cause the lowest level in the new video signal.
signal is output on P2-6 +TTL VIDEO.
This "TTL" driven video
As above. the signal is driven by
the emitter follower (Ql) to drive +VIDEO (P2-4).
-54-
(I
6.
COMMUNICATION OPERATION
6.1
Baud Rate Generation
The baud rate frequencies for the computer (P3) and printer (P4) serial
communication interfaces are determined by the counters and switches
shown on page 6 of the schematics.
The input clock is TDCl (A57-l3, page
4), which is an asymmetrical 3.402 MHz signal (see Figure 5.0).
The
first counter (A73, page 6) divides this by 11 to yield a 309,273 Hz signal (A73-ll) suitable for the 19,200 baud rate.
Counter A70 and A7l
each provide 4 levels of dividing by 2 to yield clocks for 9600 down to
75 baud.
Counter A72 divides A70's output by 11 to yield (at A72-ll) a
clock suitable for 110 baud.
Switch S1 selects the baud rate for the computer (P3) port by enabling
one (and only one, as enforced by the user) signal to A74-9 (page 6).
(See Section 3's table for switch settings.)
Switch S3 does the same for
the printer (P4) port by enabling one signal to A74-2.
The CPU selects
one of these two signals with +SELLPT (A74-1,2,3) the printer port and
-SELLPT-1 enables (at A74-8,9,lO) the computer port.
by the CPU as bit 4 in memory mapped I/O port 40CH.
+SELLPT is controlled
(See Section 2.4.1.)
The selected baud rate results in +BAUD GEN (A47-ll,l2,l3) which goes to
the UART (A48-12,40, page 2).
6.2
UART Operation
Details of the UART chip's (A48, page 2) internal operation are given in
its specification in Appendix C.
Section 2.4.2 presents programmer-level
I/O information.
-55-
UART I/O Interface:
Three I/O ports (2 read and 1 write) are used to
interface the CPU to the UART.
The data write port (address 408-H) is
enabled by address decoder output 2 (A5S-3, page 1) which goes to the
UART's - 05 (A48-23, page 2).
When pulsed (as per Section 2) on this
input the UART receives a byte on CPU data
connected to UART inputs
(address 40am
read outputs
J
O~.
(page 2).
~ines (+DB7~.)
which are
The data read pulse, -RDE
from the decoder (A58-6) enables (RDE, A4S-4) the UART's
(R08~L)
onto the CPU data bus
(+DB7~.~
respectively).
-RDE also pulsed the UART's reset Data available input (A4S-1S).
The
status word enable read pulse, -SWE (address 404H) , from the decoder
(A58-7) enables (48-10) four status bits onto the CPU data bus:
FE, Frame Error,
from A48-l4 to +OB3
PE, ·Parity Error,
from A48-l3 to +DB2
TBMT, Transmit Buffer Empty,
from A48-22 to +OBl
DTA, Data Available,
from A48-19 to +080.
UART 5WITCHCONTROL5:
Five switches provide operational control over the
UART, see Appendix C and Section 3:
52-5, 16
Parity
A48-35
52-6, is
Stop Bits
A48-36
52 ... 7, 14
Number of Bits
A4S-38
52-8, 13
S2-9, 12
"
"
"
ODD/EVEN PARITY
A48-37
A48-39
The -HALF DUPLEX Signal goes directly into the CPU (A54-38, page 18, from
switch S2-3,18).
It is not implemented with the UART, but by the firmware.
-56-
(
UART RESET:
The CPU resets the UART by pulsing the -PROG pin (A54-25.
page 1) which is inverted (by A67-1.2. page 1) yielding +RESETUART to
drive the UART's MR input (A48-2l, page 2).
UART SERIAL OPERATION:
As described in Appendix C the UART uses the
receive and transmit clocks, (A48-l7,40) at 16 times the baud rate, to
transmit data (A48-25) and receive data (A48-20).
The clock is as
selected in the BAUD RATE GENERATION logic (+BAUDGEN, A74-ll, page 6j see
Section 6.1).
6.3
SERIAL INTERFACES
The computer and printer serial interfaces can be either RS232C-type
levels or current loop.
The serial data is transmitted as both RS232 and
current loop (for the selected interface).
Two switches must be set to
select which type of data will be received on the computer port:
Receive RS232C on P3-3 -- Close 55-6,9
Receive Current Loop on P3-l2,24 -- Close 55-7,8
(only one switch should be closed).
6.3.1 RS232 Operation:
C(JotPUTER PORT, P3 :
Receive nata is input on P3-3 (by A60-12, page 2) and passed through
switch S5-6,9 to the UART (A48-20).
(See also Section 6.3.3 for P6).
Clear to send is input on P3-5 (by A60-8,lO) yielding -CTS which the CPU
can input on T' (A54-l, page 1).
(See also Section 6.3.3.)
-57-
A "Data Carrier Ready" signal can be selectively input on P3-6 (as
switched by 55-1,14) or on P3-8 (as switched by 55-2,13).
With both
switches open 3.3Kit resistor (R32) pulls the input to +12V, the true
condition.
(
The output of the RS232 receiver (A60-ll, page 2) becomes
-OCR which the CPU can read on port 2 bit 5 (45-36, page 1).
(See also
Section 6.3.3.)
Transmit Data'for the computer RS232 port is driven to P3-2, TXD, (by
A59-4,5.6, page 2).
The input to the driver (A59-4.5) is enabled (at
A61-4,5,6) by the control signal -SELLPT (A62-4 to A61-5) which. before
inversion (by A62-3,4), is +SELLPT as output by the CPU on bit 4 of
memory mapped I/O port 40CH (See Section 2.4.1).
When -SELLPT disables
the transmit port (-SELLPT low) the output (at A59-6, P3-2) is kept low
(defined by the RS232C specification as the "OFF". marking condition, or
binary 1 condition.)
-BREAK (A47-10, page 1, CPU output to 40CH bit 3)
when true (low) can force (via A61-l1,12,13, page 2) the transmit data to
the spacing condition (RS232 is positive, defined as
A6l-4,5,6) by -SELLPT being high.
"ONtI ) i f
(
enabled (at
The data signal itself (at A61-l2) comes
from the UART's -TXD output (A48-25).
(See also Section 6.3.3 for P6.)
The CPU controlled -RQS signal (A47-7, page 1, CPU output to 4.CH bit 2)
is
the source for driving (using A59-2,3, page 2) the RT5signal at P3-4.
By closing switch 55-3,12 this driver will also drive DTR at P3-20.
Alter-
natively, DTR could be pulled permanently to the "ON" (positive) state
I
,
by closing switch 55-4,11 (and leaving 55-3,12 open).
Pin P3-7 is ground on the R5232 computer port.
(1
-58-
PRINTER PORT, P4:
The RS232 printer port has no serial data receive capability.
However
+PRTRDY (P4-20, page 2) is received (by A60-4,6) and sent to the CPU as
-PRTRDY (A60-6, page 2) on CPU port 2 bit 6 (A54-37, page 1).
If P4-20
is left disconnected, then a 3.3KJt resistor (R1B) pulls the signal to
the ON state.
Transmit Data for the printer RS232 port is driven to P4-3, PRT DATA (by
A59-8,9,lO, page 2).
The input to the driver (AS9-9,lO) is enabled (at
A6l-8,9,10) by the control signal +SELLPT (A47-12, page 1) which is output
by the CPU on bit 4 of output location 40CH (See Section 2.4.1).
The
transmit data is otherwise controlled by +SELLPT and -BREAK in the same
manner as described above (for -SELLPT and -BREAK) for the computer RS232
transmit data, above.
The data, as above, originates from the UART's -TXD
(A48-2S).
The RS232 printer port also drives (with AS9-l1,12,13) p4-6 (by installing
jumper Wl2) and/or P4-8 (by installing jumper W13) with the CPU controlled
signal -RQS (A47-7, page 1, CPU output to 40CH bit 2).
Pin P4-7 is ground on the RS232 printer port.
6.3.2 Current Loop Operation
COMPUTER PORT, P3:
interfaces.
The computer has both transmit and receive current loop
The receive circuit uses an opto isolator (4N37 at A6-3, page 2)
to receive a current loop with current (conventional) entering at P3-12
(RXDl) and leaving at P3-24 (RXD2).
path.
Adiode (02) provide a reverse current
The opto-isolator's output (A63-5) feed an inverted (A62-10,11), the
-59-
output of which (when passed by • closed 85-7,8 switch) provide the
UART with serial input data (A48-20).
(Note that the R8232 switch 85-6,9
should be open during current loop operation).
The current loop receiver
circuit is very low impedance such that the equipment driving
t~is
(
input
must limit the current, to not more than 40 mA (with a 20 mA minimum).
The current loop driver for the computer port is opto-isolated (A65,4N33)
also.
Its source (via A62-5,6) is the same as what is input to the RS232
driver, causing it to parallel that pin's actions (See Section 6.3.1).
A
completely isolated output is provided at P3-25 (TXDl) and P3-l3 if
jumpers Wl4 and Wl6 are installed (and jumpers W15, Wl7, and W6, and
resistor R2.8 are not installed).
Alternatively by installing R28, W6, Wl5,
and Wi7, a current (limited by R28) can be driven into P3-25 (TXDl) and
returned to ground at P3-13 (TXD2).
(
(
7.
KEYBOARD OPERATION
The keyboard matrix is driven on connector PI (pins 8 to 15) by the CPU
with bits 7 to • of port 1 (A54-34 to 27), page 1).
The twelve inputs
are received by multiplexers (with all of A69 and A68-9 to 15, and 2, page
1) to be received by the CPU via the four memory-mapped input locations
4,C, 4'D, 4,E, and 4'F (Hex) as described in Section 2.4.3.
This is done
using the 4fC decoder output KBRD (A58-9, page 1) and +Al and +A, (at
A69-2,14 and A68-2, 14), causing the multiplexers to output data on +DBe
(A69-9), +DBI (A69-7), +DB5 (A68-9).
Additionally for all addresses
4'C to 4'F separate switches from the keyboard are input on the following
bits:
+DB2
Pl-5
FUNC
(using A76-11,12)
+DB3
Pl-6
CTL
(using A76-l3,14)
+DB4
PI-4
S11FT
(using A76-2,3)
+DB5
PI-3
ALPHA
(using A76-4,5)
See also Section 2.4.3 for CPU interface usage and Appendix C for the
standard keyboard matrix expected on the interface.
-61-
(I
(
(J
ITHI/
FIr-.iD
NO.
,
RL FT:RENCI:/
QTY PER AS91/ Rl:V LEVEl.
DrSIGNATOR
NOMI:NCLATURI:/ nESCH I PT J ON
PART NUMBER/RH1ARKS
K
L
E
G
H
1
1
1
1
1
1
C2
Cap DIP t-lica 10pf 100D03
2024100
2
3
4
3
1
47
3
1
47
C3,6,7
C1
unmarked
Cap R/L 22uf 15V
Cap R/L 1uf 15V
2025700
2027901
Cap C/D .01uf 20% 16V
2028700
5
1
4
1
1
1
C10
Cap C/D .Oluf 10% 50V Y5P
2028900
6
2
2
0
0
2
C11,12
Cap C/D 330pf SOV 20%
2029100
7
1
1
1
1
1
A42
IC 74S00
2024000
8
5
5
5
5
5
A18,20,40,61.74
IC 74LSOO
2024200
9
1
1
1
1
1
A15
IC 74LS03
2024400
10
1
1
1
1
1
ASS
IC 74S04
2024600
11
5
1
5
1
5
1
5
1
A36,38,44,62,67
IC 74LS04
2024800
12
5
1
IC 74LS05
2025000
13
2
2
2
2
2
IC 74LS08
2025200
14
2
2
2
2
2
IC 74LSIO
2025400
15
1
1
1
1
1
IC 74LS20
2025600
16
3
3
3
3
3
IC 74LS32
2025800
17
1
1
1
1
1
A14
A32,43
A33,46
A19
A22,39,66
A58
IC 74LS42
2026000
18
1
1
1
1
1
A37
IC 74LS51
2026200
19
1
1
1
1
1
IC 74S74
2026400
20
8
8
7
8
8
A17
AI6,28,29,31,34,
IC 74LS74
2026600
3
3 3
1
1 1
47 47 47
35,45,77
NOTJ:S:
PAGE 1 OF 5
TIT 1.\;
1Ji\'J'L
CONTROL BOARD, TVI-912/920 TERMINAL
02-01-83
O.ThleVtdeo Systems, Inc.
I
I
v
v
ITEM/
flNIl
NO
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
QTY PER J\SS~I/REV LEVEL
K
1
1
1
4
5
1
1
2
2
1
1
1
1
1
1
1
1
1
1
2
1
L
1
1
1
4
5
1
1
2
2
1
1
1
1
1
1
1
1
1
1
2
1
E
1
1
3
5
1
1
2
2
1
1
1
1
1
0
1
1
1
1
2
1
G H
1 1
1 1
1
4 4
5 5
1 1
1 1
2 2
2 2
1 1
1 1
1
1
1
1
0
1
1
1
1
2
1
1
1
1
1
1
1
1
2
1
REfERENCE/
llESIGNATOR
A21
A56
A27
A24,25,26,78
A57,70-73
A2
A30
A41,47
A68,69
A76
A51
A4
A59
A60
A65
A63
A3
Al
A13
A52,53
A48
-
~
NGr.1ENCLATURE/JlESCR T PT ION
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
74LS86
74LS109
74LS139
74LS157
74LS163
74LS166 ,
74LS173
74LS174
75LS253
74LS367
74LS373
IC~ 7 4LS3 74
IC 75188N
IC 75189AN
IC H11G3
IC TILI17, 4N37
IC 2316 ROM A3-2
IC NE555
IC DP8304
IC AMD2111-4A
IC 2502, AY-5-1013A
PART NUMBER/REMARKS
2026800
2027000
2027200
2027400
2027600
2027800
2028000
2028200
2028400
2028600
2028800
j
I
I
I
202900'0
2029200
2029400
2034200
2029300
2034600
2030200
2030400
2030600
2030800
I
I
NOTES:
i
,
PAGE 2 OF 5
IlIYIT
TITLE
CONTROL BOARD, TVI-912/920 TERMINAL
02-01-83
O.1eleVideo Systems, Inc.
ITEM/
FINn
NO.
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
QTY PER J\SS~I/ REV LEVE',
G H
K L E
1 1
1 1 1
1 1 1
1 1
4 4 4
4 4
(4 (4) (4)
1 1
0
1 1
0
(1 0 0
(1 0 0
1 1
1 1 1
1 1
1 1 (1 1 1
2 2 2
2 2
2 2 (2 2 2
4 4 4
4 4
1
1 1
3 3 1
1 1
3 3 2
2 2
1 1 0
0 1
1 1 1
1 1
1 1 1
1 1
2 2 2
2 2
RI: FERENCE!
IH:S I GNi\TOR
A23
A54
A6,8,10,12
A5,7,9,11
A49B
A49C
A49R
A50R
S5
S3
Sl,2
P3,4
XA5,7,9,11
XA49
XA50
XA23,54
XS4
Xl
P7
P2,5
NOI\IENCLJ\TURE/I1ESCR I PT ION
PART NUMBER/REMARKS
IC 5027,5037,TMS9927
2031000
Ie Microprocessor P8035
IC TMS4045-25NL, 2114 300NS
IC TMS 4045 Option-2nd page
IC 8332A 32K ROM A49B
IC 8332A 32K ROM A49C
IC 2316 16K ROM A49R
IC 2316 16K ROM A50R
IC A49C1
Dip Switch 7 Pas Top
Dip Switch 10 Pas Top
Dip Switch 10 Pos Side
Connector RS232 RIA
Socket Ie 18 Pin
Socket IC 24 Pin
Socket Ie 24 Pin
Socket IC 40 Pin
Socket IC 14 Pin
Cry 23.814 MHz Fundamental
Plug 2 Pin
Plug 5 Pin
2031200
2035800
2032600
2032600
2032200
2032400
2034000
2174200
2181000
2096800
2097800
2098400
2098401
2098401
2098402
2098403
2098600
2098501
2098706
·NOTES:
I
PAGE 3 OF 5
TITI.E
CONTROL BOARD, TVI-912/920 TERMINAL
-----_.
-
IlAT I:
2-1-83
O.'IeleVideo Systems, Inc.
I
v
~
~
..
ITEf'.I/
riND
NO.
63
64
65
66
67
68
69
70
71
72
73
74
7S
76
77
78
79
80
81
82
83
K
1
2
1
2
3
1
2
2
6
2
1
1
2
1
5
QTY PER ASSf\I/REV LEVEL
L E
G H
1 1
1 1
2 2
2 2
1 1
1 1
2 2
2 2
4 4
3 4
1 1
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2 3
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1 1
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6 6
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REFERENCIJ
IlESfGNATOO
PI
R4,31
R22
Rl,19
Rl1,20,29,30
R13
R2,14,25
R9
R3,S,B,10,15,16
R34
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1
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u~_
~~_
NOMENCLATlJRE/I1ESCRIPTION
. Plug 26
Res C/F
Res C/F
Res C/F
Res C/F
Res C/F
Res C/F
Res C/F
Res C/F
Res C/F
Res C/F
Res C/F
Res C/F
Res C/F
Res CIF
Res C/F
Res C/F
Res C/F
Pin
68 Ohm 5% 1/4W
1BO Ohm 5% 1/4W
270 Ohm 5% 1/4W
330 Ohm 5% 1/4W
470 Ohm 5% 1/4W
510 Ohm 5% 1/4W
750 Ohm 5% 1/4W
lK Ohm 5% 1/4W
lK Ohm 5% 1/4W
lK Ohm 5% 1/4W
1.2K Ohm 5% 1/4W
I.BK Ohm 5% 1/4W.
3.3K Ohm 5% 1/4W
3.3K Ohm 5% 1/4W
4.7K Ohm 5% 1/4W
4.7K Ohm 5% 1/4W
51K Ohm 5% 1/4W
Res C/F 1M Ohm 5% 1/4W
Res Pack lK Ohm
PART NUMBER/REMARKS
2098701
2051100
2053300
2051300
2051500
2051700
2051900
2031700
2052100
2052100
2052100
2031900
2052300
2052700
2052700
2053100
2053100
2032300
2032500
2031500
2040500
NOTES:
PAGE 4 OF 5
IM"!'L
TITLE
CONTROL BOARD, TVI-912/920 TERHINAL
2-1-83
O~1eleVideo Systems, Inc.
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84
85
86
87
88
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2040700
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R43
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TR 2N4401
Diode 1N914
P6KE15A Diode
2033300
2045500
2047500
2047900
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NOTES:
PAGE 5 OF 5
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PAGE 1 OF 5
TITLE
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CONTROL BOARD, TVI-912/920 TERMINAL
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2051800
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2026600
2029400
2029200
2053000
2028200
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PAGE 1 OF 4
1M']' L
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PCB ASSY CONTROL BOARD 910
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PAGE 2 OF 4
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PCB ASSY CONTROL BOARD 910
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NOTES:
PAGE 3 OF 4
TITLE
llAT I:
1-14-83
PCB ASSY CONTROL BOARD 910
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PAGE 4 OF 4
TIT I.E
PCB ASSY CONTROL BOARD 910
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NOTES:
PAGE 1 OF 5
IlATI:
TITI.E
PCB ASSY CONTROL BOARD 910 GATE ARRAY
1-13-83
O. TeleVideo Systems, Inc.
I
v
I TEI\I/
FIND
NO.
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
~
~
QTY PER AS91/ REV LEVEL
A
1
1
1
1
1
1
1
1
1
1
1
3
Rl:FERENCI:/
DESIGNATOR
A24
A35
A21
A7
A25
A20
A19,23,26
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
R6
R9-13,18,24,25
R7
R8
R2
Res
Res
Res
Res
Res
All
A29
A28
A34
A22
1
8
1
1
1
NOMENCLATURE/DESCRIPTION
PART NUMBER/REMARKS
74LS174
74LSOO
74LS08
74LS32
G/A 910/925
74LS02
74LS04
74S04
7406
74LS163
CRT Cant SY6545A-1
74LS157
2028200
2024200
2025200
2025800
2057400
2041600
2024800
2024600
2034800
2027600
2052800
2027400
3.3K 1/4W 5%
4.7K 1/4W 5%
47K 1/4W 5%
1M Ohm 1/4W 5%
lOOK 1/4W 5%
2052700
2053100
2033700
2031500
2032100
CF
CF
CF
CF
CF
NOTES:
PAGE 2 OF 5
IIAT I;
TITLE
PCB ASSY CONTROL BOARD 910 GATE ARRAY
~-
1-14-83
O~1eleVideo Systems, Inc.
I TE~I/
QTY PER
FIND
NO.
43
44
45
46
47
48
49
50
51
52
53
A
AS91/ REV LEVEL
RI:FERENCI:/
IlI:S I GNATOR
NmlLNCLATURL/ llLSCR I Pl ION
270 Ohm 1/4W 5%
750 Ohm 1/4W 5%
1K 1/4W 5%
22 Ohm 1/4W 5%
68 Ohm 1/4W 5%
2051300
2031700
2052100
2033500
2051100
Res CF 330 Ohm 1/4W 5%
Res CF 470 Ohm 1/4W 5%
Res CF 1.8K 1/4W 5%
Res CF 33 Ohm 1/4W 5%
Res CF 10K 1/4W 5%
2051500
2051700
2052300
2034500
2034100
RP1,5
RP2-4
Res Pk 4.7K Ohm lOP SIP
2041300
Res Pk 4.7K Ohm 8P SIP
2042900
C18
C2,3,7
Cap Mica 10pf 50V 5%
Cap E1ec 22uf 15V -10% to
+100%
Cap E1ec 10uf 16V 20%
2024100
2025700
R22
R14.21
R1,20,23,28
R19
R3
R4 ,5 ,17
R1
R15
Res
Res
Res
Res
Res
R26
R27
2
3
58
59
1
3
60
61
62
1
27
1
1
2
4
1
1
3
1
1
1
1
54
55
56
PART NUMBER/REMARKS
CF
CF
CF
CF
CF
57
C5
C6,9,21-43
C4
Cap Cer .01uf 16V 20%
Cap Cer .1uf 50V 10%
2027300
2028700
2030100
NOTES:
PAGE 3 OF 5
11A'I E
TITLE
PCB ASSY CONTROL BOARD 910 GATE ARRAY
1-14-83
O.JeleVideo Systems, Inc.
,
"-"
~
~
ITUI/
FINn
NO.
A
63
1
C1
Cap Mica 20pf 50V 10%
2024300
64
1
C8
Cap Mono .039uf 50V 10%
2030300
65
1
C19
Cap Tant 4.7uf 16V 10%
2027500
66
67
8
1
C10-17
C20
Can Cer 330nf SOV 20%
Cap Tant 10uf 25V 10%
2029100
2027100
2
CRl,2
Diode IN914
2047500
2
Ql,2
Tran 2N4401 NPN/Silicon
2045500
75
1
Y2
Crystal 13.608 MHz
2098605
76
1
Y1
Crystal 1. 8432 MHz
2098602
2
SW1,2
Switch 10 Pos DIP
2096800
81
3
A13,17,38
Socket IC, 24 Pin
2098401
82
4
A1,20,22,27
Socket IC, 40 Pin
2098402
83
1
A15
Socket IC, 28 Pin
2098404
QTY PER
J\SS~I/REV
RI;FI:RENCI:/
LEVU,
DLSlr.NJ\TOR
NmlLNCLJ\TURE/nESCR I PT rON
PART NUMBER/REMARKS
68
69
70
71
72
73
74
77
78
79
80
NOTLS:
PAGE 4 OF 5
IlinL
T ITL!:
PCB ASSY CONTROL BOARD 910 GATE ARRAY
---
------
-
-
-------------
1-14-83
O,,'IeleVideo Systems, Inc.
...
ITHI/
riND
A
NO.
QTY PER
B~C;
2
86
87
88
89
90
91
92
93
94
1
2
1
REV LEVEL
REFERENCE!
D!:SIGNATOR
P6
P3 4
PI
P2,S
P7
1
84
ASS~I/
NOf\II:NCLATURE/IlESCR I PT I ON
Socket IC. 16 Pin
Conn 2SP PCB D-Sub Fern
Plug 26P RT 3
Conn SP STR Wafer
Conn 2P STR Wafer
PART NUMBER/REMARKS
2098405
2097800
2098701
2098802
2098800
NOTES:
PAGE 5 OF 5
TITLE
PCB ASSY CONTROL BOARD 910 GATE ARRAY
'-----
IlATE
- -
1-14-83
O.1eleVideo Systems, Inc.
(
(
VIDEO MONITOR/POWER SUPPLY
SCHEMATICS AND PARTS LIST
TeleVideo Systems, Inc.
1170 Morse Ave., Sunnyvale, CA 94086
(408) 745-7760 TWX 910-338-7633 "TVI VIDEO"
()
(1
TO
POWER SUPPLY MODULE-P11
DRIVE TRANSFORMER
TO
DEFLECTION YOKE-P12
. I
TO CONTROL BOARD I
(SIGNAL)-p10
.
FLY BACK
TRANSFORMER
o
H. V ANODE CAP
CRT SOCKET
VIDEO MONITOR MODULE
o
o
o
-+- HEAT SINK (B)
o
o
o
DC 13.8V (LAS 16CB)
DC 5V (LAS 1605)
UNREGULATED
DC OUT PUT
--~nl~
-
..~~:~
I,
"00
.== . ()
=;= ,
~=~ARD
VIDEO B+
ADJUST POT
()
=
=
~
TO
0 -~ ~ IT ~ ; r~WE~~1LE
i 'J === gg
L
j t 1:lr ~WER
.~
F102
FUSE (3A)
(+13,8V)
.
F103
FUSE (3A)
(+5V)
POWER SUPPLY MODULE
TRANSFORMER
--P13
v
~
~
V- HEIGHT
-
v - LINEARITY
-
-
-
I
CONTRAST
-
-
~: t
-
,n
•
.
!
I
L
I
..
~~
:;
'3"
:
~u
J~~I
{,
r-i:J
+-~
I 1N914
C500
050'1
0"
KDlIIJ!
+, 'II -
~~
"'m
2" !l::c
~
1'"'' !~t
- ~I
~
~
10 !
_ 1t7'\
i
--111
, : I
0;102
--:~II
'r+o,IIWJeL-___
i; L_
-WI
i
I
.
'~--I
':
l
'
I
e
-
T 101
~2V
GNO
5V
UY
J 5
Vp_p 124
M\\\\MA
-
!\
.~I~~ l~~mt
-
r
r
C E
~3
lSA 495
25Cl72
P
0 iJ
I
I ,
,2SC 2211
25C"U
'- __ ..f
~ i, I I
POWER TRANS
!
1§4.n
~
.:'
o
(! :
j
:
ti]j
2'iC 1~73
2SC 98)
~I
I
I
~I
BeE
h ~-,:J
..
0
·LAS1&Q15
lAS '5C8
0
I.
2.
All resistance values in OHM K =1.000 M=I,OOO,OOO.
All copacitor values in FARAD U=IO" p=16'~
3.
Unless otherwise stated, working vottages of capacitors Gre SOyolts ..
4.
This schematic diooram cover. basic or repre.entative dlassis only. Thar'e may be same
KfC 1627...
component or portiol schematic difference between acluai chassis and the schema lie diaoram •
KTA10115
D
KTC 1'"
'1
TR
WAVEFORM and VOLTAGE
Attachement 1
BaseCIn)
Transis tor
Locat
'- ion
vtg'
DC
AC
Funct
Parts
- ion
CIC 1) LAS1512
Regula
- t ion
CIC 2) LAS1605
"..
(lC 3) LASl812
Wave
DC
V
Form
vtg'
AC
Vp.p
V
Vp-p
~
12
0,0
0,0
0,0
1,6
~
5
0,0
0,0
0,0
0,'
~J
-12
0,0
0,0
0,0
V
Vp-p
12
2,5
- - - ------;---;
2SCS09
Form
Vtg'
DC
AC
Emit ter( GND)
T-
Wave
Form
~-I:t~- ~::-I ~o _--_-_---_-----if-o--'o-+-o--'~- --------...
(IC I.) LAS1SCB
Q102
Wave
Collector lOut j
"',.
t-- - -- -----
!
78.7 : 0,0:
I
---
---I
I
I
86,1. 11,5
1
~ 98,0
0,0
i
a 203
2~9~ ~ ~~loo~11-~-----~-7-5,-7~0-,O~---,~~~~~-,-'-,-9~-O_,O~
~
I
I
~
~
,--.---l
v~rrt,ve
i 'T(
i ~~
,------- ---- - r--r2SC"7~rV~r~t t+~--.~- ~:_r~------+_8--,7-6+--6-,-S-+-~-----=-~----'-t
'a
2SAL7]
0103
____
0201
____
2SAL95 VertP",e 2,0
I
0,6
I
-- - - - - --'--1---'------'---+-- Dr I ve
0202 2S072
3,01
:
0,68 0,5
8,0
0,57
Q 301
6,5 •
0,0
0,0
-------=+---+----+---~-----II
9,36
2SC735
V:~t
Horiz
8,0
6,5
-0,25
0,61.
2SC2233
Horiz
-0,08
6
Out
....-0-5-0-'+-2-S-C-9S-.3+V--;;::
0302 OS-lOA
~~
0,0
0,0
8,6
6,5
12
20
0,0
0,0
12,8
121.
0,0
0,0
76.8
25
-0,8
2,8
~~
....,
Drive
0302
1,7
----1----
--~--------
20L
1,0
kJ1f
I!
:r~ 1flJ
Oampin:; 12,8
A
uu
132
DC Voltage reading taken with VTVM from point indicated to chasSIS ground_
AC Voltage reading taken with Oscilloscope from point indicated to chassis ground
lJlJ
(
ITHI/
FINn
NO.
QTY PER ASS~I/RJ:V LLVEL
H.HTRENCL/
IlI:S I GNATOI~
NmILNCLATURL/ IlLSCI~ I PT I ON
PART
NU~'1HER/RBIARKS
1
RI0l
2.2M Ohm 1/2W CFR
2186500
2
3
RI02
RI05,106,208
390 Ohm 1/2W CFR
2186100
2053100
4
RI07
5
RI08
6
RI09,201,205
4.7K Ohm 1/4W CPR
3.9K Ohm 1/4W CFR
27K Ohm 1/4W CFR
2.7K Ohm 1/4W CFR
7
RII0
30K Ohm 1/4W CFR
2039300
8
R202
lOOK Ohm 1/4W CPR
2032100
9
R203
2.2K Ohm 1/4W CFR
2038700
10
R204 ,212 ,213
0.6 Ohm 2W
11
R206,503
820 Ohm 1/2W CFR
2186200
12
R207
2039100
13
R209,505
6.8K Ohm 1/4W CFR
47K Ohm 1/4W CFR
14
R210
330 Ohm 1/4W CPR
2051500
15
R211
150 Ohm 1/4W CFR
2033900
16
R214
270 Ohm 1/4W CFR
2051300
17
R301
470 Ohm 1/41\' CFR
2051700
18
R501
47 Ohm 1/4W CFR
2037700
19
R502
90 Ohm 1/4W CFR
2177600
20
R.504
56K Ohm 1/4W CFR
2039500
21
R506
220 Ohm 1/2W CFR
2186000
NOTLS:
~ire
2177400
2037300
2038300
Wound Res
2177100
2033700
I
PAGE 1 OF 5
Ili\TL
TIT!.!:
VIDEO MONITOR AND POWER SUPPLY PARTS LIST
----
--
--
----
1-13-83
O"TeleVideo Systems, Inc.
ITEM/
fiND
NO.
22
23
24
25
26
27
28
29
30
31
QTY PER
ASS~I/REV
LEVEL
Rl:fERENCEj
DESIGNATOR
R507,509
R508
SFR1, SFR4
SFR2
SFR3
VRI
VR2
TlI201
C101-109
C113
C114,115
Cl16
Cl17
C119
C120
C201
C202,204
C203
C205
C206
C207
32
33
34
35
36
37
38
39
40
41
42
~
~
\..,;
NOMENCLATURE/DESCRIPTION
1.5K Ohm 1/2W CFR
10K Ohm 1/2W CFR
lOOK Ohm Pot
2K Ohm Pot
5K Ohm Pot
500 Ohm Pot
2H Ohm Pot
1.1K Ohm Thurmister
O.OluF 16V Ceramic 20%
3,300uF 35V Electrolytic
0.33uF 35V Tantal
470uF 35V Electrolytic
4700uF 16V Electrolytic
110uF 160V Electrolytic
22uF l60V Electrolytic
10uF 16V Electrolytic
4.7uF 16V Tanta.l
22uF 15V Electrolytic
100uF 10V Electrolytic
22uF 10V Electrolytic
2200uF 10V Electrolytic
PART NUMBER/REMARKS
2186300
2186400
2177700
2177800
2177900
2180200
2180100
2180300
2028700
2196500
2198100
21982002196600
2196300
2196400
2027300
2027500
2025700
2196000
2196100
2196200
NOTES:
PAGE 2 OF 5
TITLE
VIDEO MONITOR AND POWER, SuPPLY PARTS LIST
P/H L
1-13-83
OwlCleVideo Systems, Inc.
_l
ITEM/
QTY PER ASS~I/RJ:V LEVEL
F I Nfl
NO.
I~LFERENCL/
!
NmlJ:NCLATlJRL/nLSCR I IlT I ON
IlI:S I CNATOl~
PART NUMBER/REMARKS
43
C208
0.047uF/50V t,Iylar
2197100
44
45
C209
C301
0.OOluF/50V Mylar
4.7uF/16V Electrolytic
2196900
2196700
46
C302
0.01uF/50V Mylar
2197000
47
C303
0.0068uF/200V J.ly1ar
2196800
48
C304
0.047uF/400V Mylar
2197500
49
C305
220uF/16V Electrolytic
2199300
50
C306
16uF/25V NP
2280000
51
C307
0.039uF/50V Hylar
2030500
52
C501
220PF 50V Ceramic
2195900
53
C502
54
C503
O.OluF 50V Ceramic
2028900
55
C504
O.luF 600V Mylar
2197300
56
C505
22uF 100V Electrolytic
2196100
57
C506
0.47uF 50V Mylar
2197200
58
SG501
1KV Spark Gap
2030900
59
S~;}O
60
SW102
O.01uF/50V
1
2197000
SPST 115V 10A/230V SA Pwr SW
2097300
DPDT 115/230V Power Line
2097400
Slide Switch
61
F101
1A/250V
2097000
62
F102,103
3A/125V
2193100
NOTES:
PAGE 3 OF 5
T ITLT:
I )I\'/' I;
VIDEO HONITOR AND POWER SUPPLY PARTS LIST
-------- -------
------
.--.----------~--
----------
1-13-83
----
O,JeleVideo Systems, Inc.
---
-~
ITEMI
FlNO
NO.
63
QTY PER
~
~
~
J\SS~I/REV
l~EFERENCIJ
LEVEL
NOMENCLJ\TURE/I1ESCRfPTJON
DESIGNATOR
PART NUMBER/REMARKS
M003
Fuse Clip
2180400
64
Q102
KTC 1627A or MPS-A06
2046700
65
Q103,501
2SC983 or 2N5551
2193200
66
Q201
KTA 1015 or 2N3906
2042200
67
Q202
KTCl1815 or 2N3904
2046500
68
Q203
2SCl173 or 2N6121
2199700
69
Q204
2SA473 or 2N6124
2202100
70
Q301
KTC 200(2SCl166) or 2N4401
2045500
71
Q302
2SC2233 or HJE13006
2047300
72
IC1
LAS 16CB 13.8V Regulator
2126900
73
IC2
LAS 1605 5V Regulator
2126800
74
V501
B
75
V501
CRT Green P31 12"
2049300
76
D101-108
DS 135D or 1N5391 Rectifier
2200600
77
D109
DS 135C Rectifier
2201400
78
D111,112
EQA01-l2 or 1N759A Zener
2201600
& W Pr
12"
2049100
Diode
79
D302
DS-113A or MRI-1000 Damper
2201700
Diode
80
D501
1N914 or KDS1553 Switching
2047500
Diode
NOTES:
I
PAGE 4 OF 5
T ITI..L
I
IJi\TL
VIDEO NONITOR AND POWER SUPPLY PARTS LIST
-~.
1-13-83
.~1eleVideo
Systems,Inc_,
I
I·
I
ITHI/
FINn
NO.
QTY PER
i\SS~I/
RI:V LI:VLL
RLHRLNCLj
ilLS I GNi\TOR
D502
81
NmILNCLi\TlJRL/DLSCR 11'1' ION
DS-130TB or lN4004 600V
pi\ln NUMBER/REMi\RKS
2202200
Rectifier
D201,202,301
82
KDS-8513A or IN920 Silicon
2201800
Diode
.
83
D113,114
DS 135D Rectifier
2200600
84
L202
KYS-00060 D.Y Coil
2200800
85
L201
5.4ulI Linearity Coil
2200900
86
L201
Adjustable Linearity Coil
2213600
87
L302
27uIl Inductor Coil
2201000
88
T101
Power Transformer
2201100
89
T301
Drive Transformer
2201200
90
T302
Flyback Transformer
2201300
NOTES:
PAGE 5 OF 5
T IT I.E
VIDEO t-l0NITOR AND POWER SUPPLY PARTS LIST
-_.-
Il/\TL
1-13-83
O. TeleVideo Systems, Inc.
(
(
VIDEO MONITOR/POWER SUPPLY
SCHEMATICS AND PARTS LIST
TeleVideo Systems. Inc.
1170 Morse Ave .• Sunnyvale. CA 94086
(408) 745-7760 TWX 910-338-7633 "TVI VIDEO"
(
(
)
VIDEO MONITOR
The Video Monitor is made up of two sections; the vertical
amplifier and the horizontal amplifier. These amplifiers provide
the voltages necessary to drive the CRT yoke, which deflects the
electron beam across the CRT.
The electron beam which is generated by the CRT electron gun
is swept across and down the screen to create what are called
scan lines, which we discussed in character
generation. The
movement of the beam is driven by vertical and horizontal sweep
rates which are both determined by the display circuitry on the
logic board. The horizontal sweep is approximatly 16KHz and the
vertical sweep is usually 60Hz for domestic and 50Hz for European
applic~tions.
The Horizontal sync pulses corning into the Video Monitor
are inverted by transistor Q305 and then trigger IC301. In the
precision timing mode of operation, the pulse width of IC301 is
precisely controlled by R304, R306 and C312. The output Of IC301
is then coupled by 0303 and Q301 to drive transformer T301. The
output of T301 is then amplified by Drive transistor Q302. This
transistor drives both horizontal yoke windings,
as well as the
step-up transformer that produces the anode high voltage and the
grid voltage for the CRT grid in the neck of the CRT. A new width
coil is used for better Raster width control.
The Vertical sync. pulse's corning into the Video Monitor are
converted to a sawtooth wave-form. When this is first done the
sawtooth pulse is going from a negative leading edge to a positive falling edge, the pulse goes through transistor 0202 and is
inverted to it's usable form. Now the pulse is going from a
positive 2 volt leading edge to a negative - 2.5 volt falling
edge. The timing here is critical because with in one sawtooth
pulse there are 250 horizontal pulse's that will occur. This is
the total number of horizontal scan lines on the CRT. The sawtooth pulse has to be proportional to all the previous pulse's or
the timing will be wrong for the vertical sweep as well as the
horizontal sweep. When the vertical sweep is negitive 0201
is
conducting and C202 will be discharging. During the positive
portion Q201 will cut off and allow C202 to charge. ,During the
time that C202 is charging the electron beam will be scanning.
The vertical sweep scans from top to the bottom, once the scan
reaches the bottom of the page a (blank) occurs the video beam is
turned off and it is retraced back to the top of the screen, this
is the time when C202 is discharging. After the retrace the beam
is once again turned on and begins it's scan routine. Adjusting
SFRI (vert. height) and SFR2 (vert. linearity) will change the
rate of charge of C202 thus changing the slope of the sawtooth
pulse.
POWER SUPPLY
(
Voltages are created and regulated as follows. A 24VAC
voltage is rectified by Diode 0105, 106, 107 and 108 resulting in
a 31VDC output.
This 31V is then filtered through
CI06
(3300MF/50V) and applied to five Volt switching regulator lCI03.
The output voltage of lCI03 is filtered by LIOI (200uH 5%) and
ClIO (2200MF/IOV).
The raw 24VDC voltages for the positive and negative l2VDC
are rectified by Diodes 0101, 102, 103 and 104. The +24V is
regulated by lCIOl and 0101 for output voltage +12V. This is then
filtered through Cl16. Negative 12V is stabilized by lCI02 and
filtered by CI05.
A 79 volt AC waveform is applied to the halfwave rectifier
0109 which is filtered by Cl15. the resulting 92VDC level is then
regulated by a series voltage regulator. The stabilization
network comprised of sensing and control elements, 0103 and 0102.
The 75VDC level goes to the Cathode of the CRT tube and spot
killed quickly by 0501 and C506 to protect burn out on the screen
surface of when user turned off.
The high voltage needed to drive the CRT tube V501 are
derived from the flyback transformer T302 on the Video Monitor.
(
(/
TUBE SPECIFICATION
14 INCH 90 DEGREE. HIGH RESOLUTION
DISPLAY TUBE
340CXB 4N
The 340CXB4N is a 14 inch 90 degree high resolution, rectangular
display tube primarily intended for use as a alpha-numerical and
graphic display tube for computer peripheral devices. The tube is
'provided with banded type integral implosion protection (with mounting
lugs). The tube features a low reflectance, high contrast screen. '
ELECTRICAL M1A
Heating
Indirect by AC or DC:
Heater voltage • • • • • • • • • • • • • • • •• 12.0 volts
Heater current • • • • • • • • • • • • • • • •• 75 nA
..• • • • • ...·..•
..............•
Focusing Method •• ' ••
• • Electrostatic
Deflection Method ••
• • Magnetic
Deflection Angles (Approx.)
Diagonal • • • • • • •
• • • • • • • • • • • • 90 degrees
Horizontal • • • • • • • • • • • • • • • • • • • • 80 degrees
Vertical • • • • • • • • • • • • • • • • • • • • • 65 degrees
Anode voltage
• • • • • • • • • • • • • • •
max.
. . . . . 16,000
9,000 min.
volts
volts
Using high voltage with this tube internal flash-overs may occur,
which may cause damage to the cathode of the tube and to various
circuit components on the video monitor board.
Therefore it is
necessary to provide protective circuits using spark-gaps' etc. These
should be connected as illustrated in figure 11 below.
Figure 1.
No other connections between external conductive coating and chassis are
permissible.
OPTICAL DMA
Faceplate. • • • • • • • • • • • • • • • • • • • • • • Filterglass
~
scree~:i~r~f:e~t:o~ :r~a:m~n:
: : : : : : : : : : : : i~~:i~~zed
Appearance • • • • • • • • • • • • • • • • • • • • Low Reflective*
*
.
The dark-colored screen, in combination with the filterglass,
produces the low reflectivity (equivalent to a 20% light
transmission filterglass) for easy-to-see display.
MECHANICAL'~
Tube Dimensions:
Overall length • • • • • • • • • • • • • • • • • •
Greatest dimensions of tube (excluding lugs)
Diagonal. • • • • • • • • • • • • • • • • • • •
Width • • • • • • • • • • • •
• • • • • • • •
Heigth. • •
• • • • • • •
• • • • • • • • •
Useful screen dimensions (projected)
Diagonal. •
• •
• • •
• • • • • • • • •
Width • • • •
• •
•
• •
• • • • • • • •
Heigth.
• • •
•
• • • • • • • • • • • •
·
··
·
··
·
·
··
·
·
· ··
297.0 max. mm
348.3 +/- 2.7 mm
295.3 +/- 2.7 mm
237.0 +/- 2.7 mm
322.3 min. mm
270.2 min. mm
210.7 min. mm
Pin Position Alignment • • • • • • • • • • • • • • • • Pin No 7 aligns
approx. with anode
contact.
Operating Position •• • • • • • • • • • • • • • • • • Any
Weight (approx.) • • • • • • • • • • • • • • . • • • • 3.5 kg
Implosion Protection • • • • • • • • • • • • • • • • • Tension band
(with mounting lugs)
(\
GENERAL CONSIDERATIONS:
1.
~
handling.
Care should be taken not to scratch the tube.
2.
Impact. The tubes should never be exposed to impacts of more
than 30G during handling or transportation.
3.
Grounding. The external conductive coating of the tube should
be grounded with multiple contacts (e.g. a contact plate having
many fingers.) Poor contact might cause local heating resulting
in tube leakage.
()
WARNING
SHOCK HAZARD:
The high voltage at which the tube is operated may be very
dangerous.
Design
of
the equipment should
include
safeguards to prevent the user from coming in contact with
the high voltage. Extreme care should be taken i~ the
servicing or adjustment of any high voltage circuit.
Caution
must be exercised during the replacement
or
servicing of the tube since a residual electrical charge is
stored within the tube. Before handling the tube remove any
undersible residual high voltage charge from the tube, by
shorting the anode contact button
to the frame of the
terminal as illustrated in figure 12. Discharging the high
voltage to isolated metal parts sucha as cabinets and
control brackets may produce a shock hazard.
CRT
Jumper
CorJ_~
Figure 2.
TABLE 6-1
SIGNAL WAVEFORMS
DC
AC COL .(OUT) DC
12
0.0
0.0 0.0
-12
0.0
0.0 0.0
s 0.0
0.0 0.0
AC EMIT( GND)
LOCATION FUNCTION
DC
AC BASE (IN)
ICI01
REGULATION
22
1.0
ICl02
"
-22
0.0
IC013
"
28
1.0
/\J
QI0l
"
22
1.0
/'\.../
QI02
"
65
0.0
100 1.0
QI03
"
125
0.0
50
Q201
VERT
AMP
Q202
"
0.2
Q203
"
5.0 8.0
~
12
0.0
S.O 8.0
~
Q204
"
4.0 8.0
fZ---J
0.0 0.0
4.0 8.0
~
Q30l
HORIZ
AMP
-0.7 1.5
Q302
"
Q303
"
Q304
"
0.6 0.0
Q305
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-1. 2 2.2
Q501
VIDEO
AMP
0.4 0.0
/\J
12
0.0
0.0 0.0
/'\J
0.0
lrU -O.:S 0.6 ~
0.5
~ 3.5 8.0 f"..J
-0.8 3.0
JLJl
-3.0 4.0
lJLJ
2.2 1.5
JLJ1
~
65
0.0
12
0.0
0.0 1.5
~
0.0 0.0
0.0 160
/"LM
0.0 0.0
3.0 1.5
JLJl
0'.8 3.5
0.0 3.0
'V\
1f'V
0.0 0.0
ULJ
0.0 0.0
0.0 8.0
37
27
~
0.0 0.0
15
0.0
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0.0 0.0
ALL VOLTAGE MEASURES MADE WITH OSCILLOSCOPE
DC READING TAKEN OF SIGNAL BASELINE
AC READING TAKEN OF PEAK TO PEAK AMPLITUDE
NOTE:
ANY RIPPLE MEASUREMENT LESS THAN ONE VOLT IS NOT ILLUSTRATED.
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1.
MOTES:
A
1
All RESISTOR VAWES II OHMS.
2
All CAPACITOR VALUES II FARADS.
3
UNLESS OTHERWISE STAT§!f WORKING VOLTAGES
OF CAPACITORS ARE 50 WllLTS.
II
THIS SCHEMATIC DIAGRM COVERS BASIC OR
REPRESENTATIVE CHASSIS ONLY. THERE MAY BE
SOI'IE COIIPONEIITS OT PARTIAL SCHEMATIC
BETllEEN ACTUAL CHASS I S AND THE SCHEMATIC
DIAGIWI.
--
TMllDOC:UIIINT.THlIIIIlI'EfITt'OI
T'ILIVIDEOSYS1'DII.IHC.AHDCIOMT"
N"OfIMAnDN WHICH •
(;iONP'lDI!NTW..
AHO~","TOTIl.EVIOEO.fiIO
l
MR'fOf"..DC\ICUMIHT .....,..CCPIED.
MNOOIJOII) (MIl DIKUIIID TO THIN)
I'M'MS WITMCIUf THl P9IOft \IWI'TTItlI
~OI"TELDIOfO"""'1NC
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........ ••
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7
6
5
4
3
- . ....
-- -::.
.
-. ..
.....
CON""""
.....
N.
....
-
-~IDOn
••1eIlMdeo Systems, Inc..> 2i'
PCB SCHEMATIC DIAGRAM
POWER SPLY VIDEO MON ~no
3201200
-..
SHEET
2
1
()
(
(
)
TERMINAL TROUBLESHOOTING GUIDE
Document 2191400
Revision B
28 February 1983
Disclaimer
Te1eVideo Systems, Inc. makes no representations or warranties with
.respect to this document. Further, Te1eVideo Systems, Inc. reserves
the right to make changes in the specifications of the products
described within manual at any time without notice and without
obligation of Te1eVideo Systems, Inc. to notify any person of such
revision or changes.
Te1eVideo is a registered trademark of Te1eVideo Systems, Inc.
Te1eVideo Systems, Inc.
1170 Morse Avenue
Sunnyvale, California 94086
(
(
)
.
\
,
(J
1.
INTRODUCTION
This is a general troubleshooting guide to be used with the
Operator's Manual, Maintenance Manual, and Service Bulletins as
required. By following the procedures described here, you should
be able to quickly isolate and repair most field failures.
The following sections are included:
Page
Overview of Terminal Modules
2-1
Functional Description of Modules
3-1
Troubleshooting the Logic Board
4-1
Visual Inspection
Large Scale Integration Failures
Data Line Operation
Debugging Tables for TTL Boards
Debugging Tables for GA Boards
4-1
4-2
4-3
4-4
4-12
Troubleshooting the Keyboard
5-1
Visual Inspection
Debugging Table
5-1
5-3
Troubleshooting the Video Monitor
Visual Inspection
Debugging Guide
Troubleshooting the Power Supply
Visual Inspection
Debugging Guide
6-1
6-1
6-3
7-1
7-1
7-2
2.
OVERVIEW OF TERMINAL MODULES
The design of TeleVideo·terminals permits fast fault isolation
since the terminal hardware is divided into four main modules:
1.
Video monitor
2.
Power supply
3.
Main logic board
4.
Keyboard
The video monitor and power supply are common to all TeleVideo
terminals and may be freely interchanged. Terminal keyboards are
interchangeable, as outlined in the section on the keyboard. The
main logic board is the only module that provides each terminal
with its unique characteristics.
The quickest and easiest way to isolate the malfunctioning module
is to exchange (swap) each module with a known good module. Once
the faulty module is identified, refer to the appropriate
troubleshooting table.
WARNING 1
High voltages are retained by the CRT tube and capacitors even
after power has been turned off. As soon as you open the case,
clip one end of a wire to the chassis. Attach the other end of
the wire to an insulated screwdriver. Being careful not to
touch the metal part of the screwdriver, gently slip the metal
end of the screwdriver under the cap of the anode, as shown in
Figure 2-1.
(
rRT
"node
~Ieta
1
frame
Figure 2-1
Discharging Voltages
2-1
()
3.
FUNCTIONAL DESCRIPTION OF MODULES
Logic Board
The logic board processes and controls all data received and
transmitted, and generates the video and sync signals required to
display data.
The logic board consists of the following five functional areas:
1.
2.
3.
4.
5.
Display processor
Display generator
Keyboard interface
Main port interface
Printer port interface
Power Supply
The power supply provides DC operating voltages to all circuits
in the terminal. The power supply contains two user-replaceable
3 AG-type fuses.
Video Monitor
The video monitor contains horizontal, vertical, and intensity
modulation circuits which produce a television-type conventional
noninterlaced raster display on the screen. Character signals
received from the display generator cause intensified dots to
appear at precise intervals on a raster line. These dots, when
combined with other dots on other raster lines above and/or below
a given line, produce characters.
Keyboard
910/910 PLUS/912C/920C--This keyboard sends matrixed data via a
ribbon cable to the logic board, where the ASCII code is generated.
This data is encoded in the 910/910 PLUS by the keyboard encoder
(position AI) and in the 912C/920C by the CPU (position A54) and
the multiplexers (positions A68 and A69).
The keyboards for these models are all functionally interchangeable. The 910/910 PLUS keyboard has a PRINT keycap where 912C/
920C models have a BLOCK/CONV keycap. The 920C keyboard is also
fitted with an additional top row of function and editing keys.
925/950--0n this keyboard, data is encoded by a microprocessor on
the keyboard (position U6) and sent in an ASCII serial data
stream to the logic board via the coiled cable. On the logic
board, the keyboard interface circuits convert the keyboard data
from serial to parallel data for input to the display processor
circuitry. All detachable keyboards are identical and
interchangeable.
3-1
4.
TROUBLESHOOTING THE LOGIC BOARD
Visual Inspection
With the Logic Board Instal1ed--Turn off power to the terminal,
open the case, and check the following possible problem areas:
*
Internal and external switch settings:
correct?
*
Socketed chips:
their sockets?
*
Connectors:
are they all
are they 'all plugged tightly into
look for
Loose or damaged connectors
Broken or loose securing clips on pins at
connectors
Bad crimps
Dirty contacts
*
*
Wires:
are any broken, loose, or frayed?
Components:
are any overheated or burned?
With the Logic Board Removed--Make these inspections with the
logic board removed. The procedure for removing the logic board
varies slightly according to the model. Follow the appropriate
directions for your model.
910/910 PLUS/912C/920C
To remove the logic board:
1.
Turn the power off.
2.
On the logic board, disconnect:
Pl
P2
P3
P4
PS
P6
P7
(keyboard input)
(video signals)
(RS232C port) if connected
(printer port) if connected
(voltage connector)
(modem connector) if connected
(speaker connector)
3.
Remove the four (910/910 PLUS) or six (9l2C/920C)
securing screws on the logic board.
4.
Carefully remove the logic board.
4-1
(
925/950
1.
Turn the power off.
2.
On the logic board, disconnect:
PI
P3
P4
P6
3.
(keyboard input)
(RS232C port) if connected
(printer port) if connected
(modern connector) if connected
Carefully slide the logic board half way out of the
terminal and disconnect:
P2 (video signals)
P5 (voltage connector)
4.
Carefully slide the logic board entirely out of the
terminal.
with the logic board removed, inspect the logic board for:
*
*
*
*
*
Overheated or burned components
Missing or broken components
Cracked, broken, or lifted traces
Poor solder joints (loose solder balls, cold solder
joints, or solder bridges)
Bent pins
STOP!
If defects are found, correct them and recheck the terminal
before continuing.
If no defects are found, reinstall the logic board before
proceeding with the procedures in the next section, Large Scale
Integration Failures.
Large Scale Integration Failures
Since most failures involve Large Scale Integration (LSI) chips,
this step will quickly repair most failures encountered.
Exchange all socketed chips, one at a time, with known good
chips. If the logic board malfunctions after the chips are
swapped, confirm the operation of the data lines described in the
next section, Data Line Operation.
4-2
NOTE!
The remainder of this guide involves troubleshooting to the
component level and requires schematics, an oscilloscope, a
working knowledge of transistor-transistor logic (TTL), and basic
debugging skills.
(
)
Data Line Operation
Confirm that the data lines are operating properly before
proceeding further.
NOTE!
It is beyond the scope of this bulletin to list all possible
data line problems.
The best place to check the data lines is directly from the C~U
(see page I of the schematics). There should be activity on all
data lines and the signals should range from 0 (ground) to +4.5 to
+5.0 volts. If the malfunction persists after you have confirmed
proper operation of the data lines, follow the procedures in the
next section, Debugging Tables.
Debugging Tables
NOTE!
The items listed in the tables in this section are only suspect
areas: they should not be automatically replaced when the
symptoms listed are present.
()
4-3
Table 4-1
910/910 PLUS Logic Board Debugging Guide
Suspect Areas
Part No. Position
Symptom
No video
6502
6545
2114
or
6116
Crystal
74LS163
2332
2N2219
Distorted video
6502
6545
6116
or
2114
Schematic
Page
1 of 5
A39
2 of 5
A26
A30, A3l, 2 of 5
A36, A37
A24
Y2
A15
A45
Q2
2
3
3
1
4
A39
A26
A24
1 of 5
2 of 5
2 of 5
of
of
of
of
of
5
5
5
5
5
2332
74LS166
A30, A31, 2 of 5
A36, A37
A48
3 of 5
A49
3 of 5
Horizontal bar across screen
6545
74S04
A26
A22
2 of 5
4 of 5
Loss of underline, reverse video,
blinking, or blanking
74LS174
6545
A42
A26
3 of 5
2 of 5
Loss of half intensity
74LS175
6545
A4l
A26
3 of 5
2 of 5
Loss of all attributes
6545
74S74
A26
A40*
2 of 5
3 of 5
Unable to transmit data
75188
6551A
AI0
A19
4 of 5
4 of 5
Unable to receive data
75189
655lA
A5
A19
4 of 5
4 of 5
Poor/no printing
75189
75188
6551A
A5
AlO
A19
4 of 5
4 of 5
Incorrect/no keyboard response
Notes
*Must be a Texas Instruments part.
**If used.
4-4
AY-5-3600 Al
2716
A2**
4 of 5
5 of 5
5 of 5
Table 4-1
Continued
Suspect Areas
Part No. Position
Symptom
Schematic
Page
SHIFT or CTRL keys do not function A6-5-3600 Al
7406 A12
RP4
5 of 5
5 of 5
5 of 5
ALPHA LOCK or FUNCT keys do not
function
AY-5-J600 Al
74LS364
A8
RP4
5 of 5
5 of 5
5 of 5
Keys repeat
AY-5-3600 Al
5 of 5
*Must be a Texas Instruments part.
**If used.
(
4-5
Table 4-2
912/920 Logic Soard Debugging Guide
Suspect Areas
Part No. Position
Symptom
No video, no beep
No video, constant beep
Horizontal bar across screen
Schematic
Page
8035
5027
23.814-MHz
Crystal
74LS109
74LS163
System ROMs
System ROMs
2332
A54
A23
Xl
1 of 6
4 of 6
4 of 6
A56
A57
A49
A50*
A3
4 of 6
4 of 6
5027
2114
page
2114
page
A23
4 of 6
A6, A8, 3 of 6
A10, A12
A5, A7, 3 of 6
A9, All
RAM,
1
RAM,
2
2 of 6
2 of 6
5 of 6
5027
74LS08
74LS05
A23
A32
A14
4 of 6
5 of 6
5 of 6
Area X of screen**
2114 RAMs
2114 RAMs
A8
A12
3 of 6
3 of 6
Area Y of screen**
2114 RAMs
2114 RAMs
A6
A10
3 of 6
3 of 6
74LS157
A24,
3 of 6
A25, A26
A40
3 of 6
A54
1 of 6
A23
4 of 6
Bad video or incorrect character
displayed in:
Bad video on entire screen
74LSOO
8035
5027
Notes
* If installed
**
x
y
Areas X and Y of Screen
4-6
Table 4-2 Continued
5uspect Areas
Part No. Position
5ymptom
Schematic
Page
Distorted characters
2316
8035
2114 RAMs
A3
A54
A5
through
A12
5 of 6
1 of 6
3 of 6
Unable to transmit
75188
74LS157
2502
A59
A78
A48
2 of 6
2 of 6
2 of 6
Unable to receive
75189
74LS157
2502
A60
A78
A48
2 of 6
2 of 6
2 of 6
Loss of blinking or blanking
74LS74
5027
A35
A23
4 of 6
4 of 6
Loss of half intensity
74LS74
74LS03
5027
A16
A15
A23
5 of 6
Loss or underlining/reverse video
74L574
74L574
5027
A28
A29
A23
5 of 6
5 of 6
4 of 6
Incorrect or no keyboard input
8035
74L5253
74L5253
A54
A68
A69
1 of 6
1 of 6
1 of 6
ALPHA LOCK, SHIFT, CTRL, or
Function keys do not function
74L5364
74L542
A76
A58
1 of 6
1 of 6
Unable to select one or more
baud rates
74LS163
Counter
A70
through
A73
Sl
6 of 6
Baud rate
switch
74LSOO Nand A74
Gate
4-7
(
5 of 6
4 of 6
6 of 6
6 of 6
(
Table 4-3
925 Logic Board Debugging Guide
Suspect Areas
Part No. Position
Symptom
"J:) beep, no video
Y2
13.6080MHz Crystal
A55
74LSOO
A37
74LS139
A60
6502A
A59
6545A-l
Schematic
Page
7 of 7
4
4
1
2
of
of
of
of
7
7
7
7
Lonstant beep, no video
6502A
6545A-l
74LS223
A60
A59
A44
1 of 7
2 of 7
7 of 7
Horizontal bar
74504
6545A-l
A16
A59
7 of 7
2 of 7
Bad video
10uf cap
74LS74
6545A-l
C41
A6
A59
1 of 7
4 of 7
2 of 7
Distorted characters
74LS166
2332
A30
A31
2 of 7
2 of 7
Unable to transmit to computer
75188
6551
74LS32
A34
A32
A26
5 of 7
5 of 7
5 of 7
Unable to receive from computer
75189
6551
A9, A17
A32
5 of 7
5 of 7
Unable to transmit to printer
75188
74LS32
6551
A34, A25
A26
A32
5 of 7
5 of 7
5 of 7
Unable to receive from printer
75189
74LS32
75188
A9, A19
A26
A25
5 of 7
5 of 7
5 of 7
Loss of any video attribute
74LS173
A19, A20,
A21
A40
A39
A50, A49
3 of 7
74LS245
74LS374
2332
No keyboard communication*
1.8432-MHz Yl
Crystal
A33
6551
A60
6502A
2 of 7
2 of 07
1 of 7
5 of 7
5 of 7
1 of 7
*Refer also to Service Bulletin 2, Eliminating Keyboard Lockup
4-8
Table 4-'3
Contin.ued
(
Suspect Areas
Pa.rt No. Position
Symptom
Unable to select switbh bank Sl
Unable to select switch bank S2
Switch
74LS244
Resistor
pack
Switch
74LS244
Resistor
pack
Unable to select switch bank S3
Switch
74LS244
Resistor
pack
81
AS3, AS2
RP5
Schematic
Page
6 of 7
6 of 7
6 of 7
S2
A5l, A52,
A53
RPI
6 of 7
6 of 7
S3
6 of 7
6 of 7
6 of 7
A43, ASl,
RP4
6 of 7
(
(
4-9
Table 4-4
950 Logic Board Debugging Guide
Suspect Areas
Part No. Position
Symptom
No video, no beep
6502
6551
6545
Program
ROMs
User ROMs
Character
Generator
ROMs
23.824-MHz
Crystal
74LS163
74LS109
Schematic
Page
A53
A49, A50
A5l
A56
A4l, A42
1 of 7
A52
A32, A33
1 of 7
4 of 7
aSCI
6 of 7
A3
A6
6 of 7
6 of 7
5 of 7
2 of 7
1 of 7
No video, constant beep
6545
2114 RAMs
A56
2 of 7
A25, A26, 3 of 7
A27, A28
Horizontal bar across screen
6545
2114 RAMs
A56
2 of 7
A25, A26, 3 of 7
A27, A28
Bad video, one section of screen
2114
2114
2114
2114
A25
A26
A27
A28
3 of 7
3 of 7
3 of 7
3 of 7
6116
6116
6116
6116
A37
A34
A35
A36
3
3
3
3
74LS157
A43
through
A46
ASS
A53
2 of 7
Bad video on only one page
Page
Page
Page
Page
1
2
3
4
Bad video on entire screen
6545
6502
Distorted characters
2332
74LS166
6502
All 2114's
4-10
A32, A33
A22, A23
A53
A25
through
A28
of
of
of
of
7
7
7
7
2 of 7
1 of 7
4
4
1
3
of
of
of
of
7
7
7
7
Table 4-4
Continued
(
Suspect Areas
Part No. Position
Symptom
)
Schematic
Page
Unable to transmit to system
1488
741S32
6551
741S157
A48
A58
A50
A59
5 of 7
5 of 7
5 of 7
5 of 7
Unable to receive from system
1489
741S08
6551
A57
A29
A51
5 of 7
5 of 7
5 of 7
Unable to transmit to printer
1488
74LS32
6551
74LS157
A39
A58
ASl
A59
5
5
5
5
Unable to receive from printer
1489
6551
A40
AS1
5 of 7
5 of 7
Loss of any video attribute
74LS174
74L8157
74LS174
A19
A20
A21
4 of 7
Incorrect or no keyboard input
6502
6551
A53
A49
1 of 7
3 of 7
Unable to select one or more
baud rates
6502
6552
74LS367
RP 2
RP 3
Switch 1
A53
A54
A65, A66
1 of 7
7 of 7
7 of 7
7 of 7
7 of 7
7 of 7
of
of
of
of
7
7
7
7
4 of 7
4 of 7
(
()
4-11
RGate ArrayR Logic board,
Supplement Debugging Guide
Although the components are laid out differently, RGate
ArrayR boards are completely interchangable with TTL boards. When
troubleshooting the RGate ArrayR Logic boards care should be
taken when handling the CMOS devices. The RGate ArrayR chip
positions are listed below. When exchanging these custom CMOS
chips one must be grounded to earth ground to avoid damage to the
chip from static discharge.
Model No.
910, 9l0Plus
925
950, Chip A
Chip B
Televideo
Part Number
2057400
2057400
2057600
2057800
Location
A22
A39
A34
A37
Follow the procedure in the begining of this section for
visual inspection of the logic board.
4-12
a
Table 4-5 910/910 PLUS GA Logic Board Debugging Guide
Symptom
Suspect Areas
Part No. Position
Schematic
Page
No video
6545A-1
6502
6116
Crystal
2532
74LS163
74LS166
2N2219
70200-11B
A20
A27
A13
Y2
A38
A25
A18
02
A22
2
1
2
3
1
3
3
4
3
of
of
of
of
of
of
of
of
of
5
5
5
5
5
5
5
5
5
Distorted video
6545A-1
6116
70200-11B
74LS166
2532
A20
A13
A22
A18
A38
2
2
3
3
.1
of
of
of
of
of
5
5
5
5
5
Horizontal Bar across screen
6545A-1
74LS08
A20
A37
2 of 5
2 of 5
Loss of Attribute
70200-11B A22
6545A-1
A20
3 of 5
2 of 5
Unable to Transmit to Computer
or printer
75188
6551A-1
A9
A15
4 of 5
4 of 5
Unable to Receive from Computer
or printer
75189
6551A-1
A10
A15
4 of 5
4 of 5
Inncorect/ no keyboard response
AY-5-3600 Al
2716
A2
A3,A8
74LS367
5 of 5
5 of 5
5 of 5
Shift or CTRL keys inoperative
AY-5-3600 Al
A7
7406
resistor RP2
pack
5 of 5
5 of 5
5 of 5
Alpha Lock or Funct keys
inoperative
AY-5-3600 Al
74LS367
A8
resistor RP2
pack
5 of 5
5 of 5
5 of 5
Repeating keys
AY-5-3600 Al
5 of 5
(1
(
()
4-13
Table 4-6 925 GA Logic Board Debugging Guide
Symptom
Suspect Areas
Part No. Position
Schematic
page
Crystal
70200-llA
74LS139
6502
6545A-l
Y2
A39
A38
All
A28
6
3
3
1
2
Constant beep/ no video
6545A-l
74LS273
6502
A28
A26
All
2 of 6
6 of 6
1 of 6
Horizontal bar across screen
6545A-l
74S04
A28
A40
2 of 6
3 of 6
Bad video
10uF cap C28
6545A-l
A28
70200-lla A39
1 of 6
2 of 6
3 of 6
Distorted characters
2332
74LS166
2 of 6
2 of 6
Loss of Attribute
70200-llA A39
A14,A15
2333
3 of 6
1 of 6
No transmit to computer or
printer
75188
655lA-l
74LS32
A23
A4
A24
4 of 6
4 of 6
4 of 6
No receive from computer or
printer
75189
655lA-l
A2
A4
4 of 6
4 of 6
No keyboard response
Crystal
655lA-l
6502
Y3
AS
All
4 of 6
4 of 6
1 of 6
Unable to select Sl
Switch
74LS244
resistor
pack
Sl
A3,A4l
RPI
5 of 6
5 of 6
5 of 6
Unable to select 'S2
Switch
74LS244
S2
A3,A4l,
A34
RP2
5 of 6
5 of 6
S3
A34,A29
RP4
5 of 6
5 of 6
5 of 6
No video/ no beep
,
resistor
pack
Switch
74LS244
resistor
pack
Unable to select S3
4-14
A17
A12
of
of
of
of
of
6
6
6
6
6
5 of 6
Table 4-7 950GA Logic, Board Debugg ing ,Guide ,:
Symptom
Suspect Areas Schemati..e
Part No. Position Page
6502
All
1 of 7
50f 7
6551
A29,A33
A36
6545
A6
2 of 7
740012
A34
4 of 7
A20,A25
2532
1 of 7
A30,A31
4 of 7
2332
Crystal OSC 1
4 of 7
No video/ no beep
No video/ constant beep
6545
6116
A6
A3
2 Of 7
3 of 7
Horizontal bar across screen
6545
7406
A6
A39
2 of 7
6 of 7
Bad video
6116
6545
6502
740012
AS,A13
A17,A22
A7,A12
A16,A21
A6
All
A34
3
3
2
2
2
1
4
Distorted characters
2332
740012
740012
A30,A31
A34
A37
4 of 7
4 of 7
6 of 7
Loss of Attributes
740012
A34
4 of 7
Unable to transmit to computer
75188
74LS32
6551
74LS157
A18
A19
A29
A28
5
5
5
5
Unable to receive from computer
75189
740012
6551
A9
A37
A29
5 of 7
6 of 7
5 of 7
Unable to transmit to printer
75188
74LS32
6551
74LS157
A23
A24
A33
A28
5 of 7
5 of 7
5 'Ot 7
5 of 7
Unable to receive from printer
75189
6551
A32
A33
5 of 7
5 of 7
Inncorect/ no keyboard response
6551
6502
74LS32
A36
All
A19
5 of 7
1 of 7
5 of 7
74LS157
4-15
of
of
of
of
of
of
of
of
of
of
of
7
7
7
7
7
7
7
(
(
7
7
7
7
(
)
Table 4-7 continued
Symptom
Suspect Areas Schematic
Part No. Position Page
Unable to select Sl
Switch
resistor
pack
74LS367
6552
6502
Unable to select S2
Switch
resistor
pack
74LS367
6552
6502
4-16
Sl
RPl,RP2
7 of 7
7 of 7
Al,A4
A43
All
7 of 7
7 of 7
1 of 7
S2
RP2
7 of 7
7 of 7
A4,A38
A42
A43
All
7 of 7
7 of 7
1 of 7
5.
TROUBLESHOOTING THE KEYBOARD
Visual Inspection
With the Keyboard Installed--Turn off power to the terminal.
Check keyboard alignment; are any keys binding on the cover?
Open the top case.
910/910 PLUS/912/920
Remove the two screws from the bottom front corners of the
terminal. Carefully tip the top case back until it rests on a
firm surface.
.
NOTE!
The terminal will now be top heavy and may tip over if there is
not sufficient table space to support the top.
925/950
Remove the four screws from the bottom of the keyboard case.
Carefully life off the top of the keyboard case and set it aside.
(
Check the following areas:
*
Key switches:
Foreign objects (e.g., paperclips, staples,
matches)
Liquid residue (e.g., coffee, soft drinks)
Broken keyswitches
Missing or incorrectly placed keycaps
*
Cables:
Broken wires
Loose wires at connectors
Creased, kinked, or cut cables
*
Connectors:
Loose or damaged connectors
(
Bent pins
Dirty contacts
5-1
NOTE!
If def~cts are found, correct them and recheck the terminal
before continuing.
With the Keyboard Removed--Make the following inspections with
thE keyboard removed from its case. The procedure for removing
the keyboard varies slightly according to the model.
910/910 PLUS/9l2/920
To remove the keyboard:
1.
Unplug the ribbon cable from the logic board.
2.
Remove the two securing screws and washers from the
inner bottom corners of the keyboard.
3.
Carefully remove the keyboard from the surrounding
case.
925/950
To remove the keyboard:
1.
Disconnect on the keyboard:
P6 (speaker connector)
P7 (keyboard cable)
2.
Remove the four screws from the bottom corners of the
keyboard case.
3.
Carefully remove the keyboard from the bottom case.
Inspect the keyboard for:
*
*
*
*
Overheated, damaged, or burned components
Cracked, shorted, broken, or lifted traces
Poor solder joints (loose solder balls, cold solder
joints, or solder bridges)
Broken, loose, or frayed wires
NOTE!
If any defects are found, correct them and recheck before
continuing.
5-2
Table 5-1
Keyboard Debugging Guide
Symptom
Suspect Areas
Models
One key inoperative/
intermittent
Respective keyswitch
Open trace/bad solder joint
8048 keyboard CPU, position
U6
A
A
B
Several keys inoperative/intermittent
A
Open/shorted trace
A
Broken/loose jumper
C, D
Defective ribbon cable
C, D
Bent pin at ribbon cable
connectors
B
8048 keyboard CPU, position
U6
B
10K ohm resistor packs,
positions RP2, RP3
10K ohm resisto~,pps!tion R3 B
All keys inoperative
Open/shorted trace
Defective ribbon or keyboard
cable
8048 keyboard CPU, position
U6
7805 +5V regulator, position
VI
5.7143-MHz crystal, position
Xl
SHIFT, FUNCT, or ALPHA
LOCK keys
CTRL key inoperative
Incorrect characters
10K ohm resistor Pack,
position RP2
8048 keyboard CPU, position
U6
10K ohm resistor pack,
position R2
8048 keyboard CPU, position
U6
Shorted trace
Shorted/improperly plugged
ribbon cable
8048 keyboard CPU, position
U6
Legend
A = All
B == 925/950
C = 910/910 PLUS
D = 912/920
5-3
A
A
B
B
B
B
B
A
C, D
B
(
Table 5-1
Continued
Symptom
Suspect Areas
Keys repeat
Respective keyswitch*
Shorted trace
Shorted ribbon cable
8048 keyboard CPU, position
U6
Models
B, D
A
C, D
B
Legend
A = All
B = 925/950
C = 910/910 PLUS
D = 912/920
Note
*On the 910/910 PLUS terminals, a key which is shorted will not
repeat on power up. Instead, any key pressed will repeat until
another key is pressed.
5-4
6.
TROUBLESHOOTING THE VIDEO MONITOR
(
Visual Inspection
With the Video Monitor Installed--Turn off power to the terminal,
open the case, and check the following possible problem areas:
*
Connectors:
look for
Loose or damaged connectors
Broken or loose securing clips on pins at
connectors
Bad crimps
Dirty contacts
*
Wires:
are any broken, loose, or frayed?
*
Components:
are any overheated, leaking, or burned?
If any defects are found, correct them and recheck the terminal
before continuing.
With the Video Monitor Removed--The following inspections should be
made with the video monitor removed.
(
To remove the video monitor:
1.
With the power off and the cover removed, disconnect
the following connections on the video monitor:
JIO (signal input)
JIl (DC power)
J12 (yoke)
2.
Disconnect the following parts on the CRT tube:
CRT socket (small printed circuit board at rear of
tube)
Anode lead (SEE WARNING ON PAGE 2-1)
Ground wire
3.
Remove the three securing screws on the video monitor.
4.
Carefully remove the video monitor.
(
6-1
With the video monitor removed, inspect it for:
*
*
*
*
*
Overheated, leaking, or burned components
Missing or broken components
Cracked, broken, or lifted traces
Poor solder joints (loose solder balls, cold solder
joints, or solder bridges)
Bent pins
NOTE!
If defects are found, correct them and recheck the terminal
before continuing.
If no defects are found, reinstall the video monitor.
Apply power.
WARNING!
High voltages are present on the video logic board.
CARE during troubleshooting.
USE EXTREME
The four adjustments which can be made to the video board are
listed in Table 6-1. The controls are shown in Figure 6-1.
Table 6-1 Video Board Adjustments
Problem
Control
Characters are too bright or too dim
Brightness
Whole screen is too taIlor too short
Height
Characters are not even in height from
the top to the bottom of the screen
Linearity
Characters are not sharp
Focus
6-2
Foc...;s
jj(~lcr.t
Briqhtness
V~rtlcal
LInearIty
Figure 6-1
Location of Controls on Video Board
Debugging Guide
This section will help you troubleshoot specific malfunctions.
Table 6-2 lists voltage levels and wave forms.
SYMPTOM:
1.
2.
No Vertical Deflection
Check 0201 collector for vertical deflection.
a.
If it is present, proceed to Step 2.
b.
If it is not present, check the base of 0201.
c.
If vertical deflection is present at the base, isolate
the 0201 collector to see if signal is being pulled
down. If there is still no output at 0201, suspect
0201.
d.
If vertical deflection is not present at the base,
troubleshoot between the base of 0201 and PIO pin 5
(vertical sync signal from the logic board).
-
Check 0202 collector for vertical deflection.
a.
If it is present, proceed to Step 3.
b.
If it is not present, check the base of 0202.
()
6-3
Bosetln)
Transistcr
Locot
'. ion
Port S
(lC 1 ) LAS1512
Fu net
DC
V
. ion
Regula
Vtg'
AC
Vp.p
12
CollectN ( Out i
Vtg'
DC
AC
V
Vp-2
Wove
Form
2.5
~
12
0,0
. t Ion
Emit ter( GND)
vtg'
Wove
Wove
DC
V
AC
Vp.p
0,0
0,0
0,0
0,0
00
0,0
O,C
(l,G
r . . .....j"---....-J JC ,l)
0.1)
Form
(lCn
LAS160S
",
1,E,
r" ...... / . . . . . . ''---1
S
0,0
CI C
LAS 1812
/,
0,1
r· ..· ......
r. . . . . ,. . ..)
. 12
0,0
,
"
1 I.
I
r",
13 ,8
0,0
BCI).
1 ~.
75.7
0,0
---
1 "'~
0,0
0,6
0,57
~.~
1,0
1,7
e ,r,
6,"-
l,~
0,0
0,
1?
o,~
------
87E,
6,S
0,0
0,0
8,6
6,5
12
20
t111
0.0
0,0
_~rJl
0,0
0,0
J)
( 1C L. ) LAS1SCB
o10?
2SC :)CfJ
"
7e)
CI
0103
2SC 983
"
12,0
0,0
.........../
--.....J
u
---
-----
----
.----
Form
----
--L..--------"-
0201
25Al.95
Vert Pree
2,G
3,0
0202
25C372
Vf> r t
~,,':::TIl ,::::;;~p
G C, p
"
I
C
25(1173
Vert
2SAL.73
VerI
..,
9.Jf,
E:
~,
8,0
5,5
-{l.2S
0,51.
Out
0301
2S( 735
HorlZ
2Scn]3
2SC9fJ
----
6
~
128
121.
0.1.
3
1fu'
76.8
25
Amp
0102 D5-113A
~
·O.OB
Horlz
Video
'\
~
~~
..-.,
-
Out
0501
-..
--l"~,
,...
i
.~
Drive
0302
I
i
Out
o 20L.
I'
"
Drive
a 2:]3
I
I
Dr I ve
Damplrt; 12.8
132
1~IlJ
_rJl
1'0,8
DC Voltage reading taken with VTVM from pain! indicated to chasSls ground,
AC VoIIage reading laken wilh Oscillu~cope Iron
Table 6-2
pOIII!
mdlcakd to
ChaSSIS
ground
Voltage Levels and Waveforms
6-4
V1/1
rj
2,B
~~
~~
mf
3.
c.
If vertical deflection is present at the base, isolate
the 0202 collector to see if signal is being pulled
down. If there is still no output at 0202, suspect
0202.
d.
If vertical deflection is not present at the base,
troubleshoot back from the base of 0202.
(
Check the negative side of C207 for vertical deflection.
a.
If vertical deflection is present, the vertical drive
section of the video monitor is good. If a vertical
problem still exists, check the following areas:
Connections
CRT socket
Related components (small pcb at neck of CRT)
b.
If vertical deflection is not present at C207, check
the 0203 emitter.
c.
If vertical deflection is not present at the 0203
emitter, check the base of 0203.
d.
If vertical deflection is present at the base, suspect
0203.
e.
If not present at the base of 0203, troubleshoot back.
f.
If 0203 emitter is good, check 0204 emitter.
g.
If vertical deflection is not present at 0204 emitter,
check the base of A204.
h.
If present at base, suspect A204.
i.
If not present at base, troubleshoot back from 0204.
NOTE!
Since 0203 and 0204 are a matched set of push/pull amplifiers,
replace both if one require replacement.
SYMPTOM:
1.
No Horizontal Deflections
Check the 0301 deflector for horizontal deflections.
a.
If horizontal deflections are present, proceed to Step
2.
b.
If not present, check the base of 0301.
6-5
(
2.
c.
If horizontal deflections are present at the base,
isolate the Q30l collector to see if signal is being
pulled down.
d.
If there is no output at the Q301 collector, suspect
Q301.
e.
If horizontal deflections are not present at the base
of Q30l, troubleshoot between the base of Q301 and PIO
pin I (horizontal sync signal from the logic board).
Check the Q302 deflector for horizontal deflections.
a.
If horizontal deflections are present, proceed to Step
3•
b.
If not present, check the base of Q302.
c.
If horizontal deflections are present at the base,
isolate the Q302 collector to see if signal is being
pulled down.
d.
If there is no output at the Q302 collector, suspect
A302.
e.
If horizontal deflections are not present at the base
of Q30l, suspect T30l (drive transformer) or Q302.
f.
If the proper signal is present at Q302 collector,
suspect the following areas:
C306
L201
SYMPTOM:
1.
No Video
Suspect the following areas:
L302
Q302
Q30l
T302 (FBT)
C305
Q501
2.
Check for cracked, broken, or lifted traces.
SYMPTOM:
Jittery Screen
1.
Make sure that yoke connector J12 is not dirty.
2.
Suspect C504.
6-6
3.
Check for
(
*
Bad crimps
*
Po6r solder joints (loose solder'balls, cold solder
joints, or solder bridges)
SYMPTOM:
Poor Linearity
1.
If horizontal linearity is the problem, check L201.
2.
If vertical linearity is the problem, check the following:
a~
Adjust SFT 2 (linearity potentiometer)
b.
Q203 and Q204
SYMPTOM:
Fuses Blow and/or Voltage is Low
1.
Check T302 (FBT)
2.
Check for cracked, broken, or lifted traces.
(
()
6-7
7.
TROUBLESHOOTING THE POWER SUPPLY
Visual Inspection
With the Power Supply Installed--Turn off power to the terminal,
open the case, and check the following possible problem areas:
*
Connectors:
look for
Loose or damaged connectors
Broken or loose securing clips on pins at
connectors
Bad crimps
Dirty contacts
Depressed pins in connectors
*
*
*
Wires:
are any broken, loose, or frayed?
Components:
are any overheated, leaking, or burned?
Bad fuse
NOTE!
Check the fuse with an ohm meter.
visual check.
*
Do not rely on a
Loose fuse holder
If defects are found, correct them and recheck the terminal
before continuing.
With the Power Supply Removed--The following inspections should be
made with the power supply removed.
7-1
To r enlove the powe r supply:
(
1.
Turn the power off and remove the cover.
2.
Unplug the power cord from the wall outlet.
3.
Disconnect Kl (AC input) on the power supply.
4.
Disconnect Jll on the video monitor.
5.
Disconnect J5 on the logic board.
6.
Remove the securing screws on the power supply (four on
the 925/950~ three on 910/910 PLUS/9l2/920).
7.
Carefully remove the power supply.
With the Power Supply Removed--Inspect the power supply for:
*
*
*
Overheated, leaking, or burned components
Bad crimps
Bad connectors/connections
NOTE!
If defects are found, correct them and recheck the terminal
before continuing.
Disassemble the power supply by removing the four securing screws
and spacers which hold the small pcb on the heat sink.
Debugging Guide
This section will help you troubleshoot specific malfunctions.
Table 6-2 lists voltage levels and waveforms.
7-2
(
SYMPTOM:
1.
No +5V DC
Remove FI03 and check for approximately +13V on one side of
the fuseholder.
a.
If correct voltage is not present, suspect the
following areas:
CI05 through CI08
DI05 through DI08
Bad crimps
Loose or damaged connectors
Broken or loose securing clips on pins at
connectors
b.
If correct voltage is present, suspect the following
areas:
FI03 (fuse)
LAS1605
Cl14
Cl13
Bad crimps
Loose or damaged connectors
Broken or loose securing clips on pins at
connectors
SYMPTOM:
1.
+5V DC is Low
Check the following areas:
LAS1605
Bad crimps
Loose or damaged connectors
Broken or loose securing clips on pins at
connectors
7-3
SYMPTOM:
1.
No
+12V DC or 13.8V DC
Remove FI02 and.check for +24V on one side of the
fuseholder.
a.
If correct voltage is not present, suspect the
following areas:
CI01 through CI04
DI0] through D104
Bad crimps
Bad connectors/connections
Broken or loos~ clips
b.
If correct voltage is present, suspect the following
areas:
LAS15CB/LAS16CB
Cl15
ell3
Bad crimps
Loose or damaged connectors
Broken or loose securing clips on pins at
connectors
SYMPTOM:
1.
(
+12V DC or +13.8V DC is Low
Check the following areas:
LAS15CB
el13
Bad cr irLps
Loose or damaged connectors
Broken or loose securing clips on pins at connectors
(I)
7-4
SYMPTOM:
1.
No -12V nr
Check the following areas:
CIOI and CI02
DIOI and DI02
Dl12
Cl16
Bad crimps
Loose or damaged connectors
Broken or loose securing clips on pins at
connectors
SYMPTOM:
1.
No +75V DC
Check the following areas:
CI09 (can be removed; do not need to be replaced)
C120
Cl19
0102
0103
SYMPTOM:
+7SV DC is Low
1.
Adjust SFR3.
2.
If +75V DC cannot be adjusted, check the following areas:
0103
Cl09
If no defects are found, reinstall the video monitor. Make sure
the securing screws are locked tight before proceeding.
Apply power.
7-5
(
()
TROUBLESHOOTING GUIDE FOR 970 TERMINAL
1
(:
(~
\
This is a general troubleshooting guide to be used with the
Operator's Manual, Maintenance Manual, and Service Bulletins as
required. By following the procedures described here, you should
be able to quickly isolate and repair most field failures.
Overview of Terminal Modules
1
Functional Description of Modules
2
Troubleshooting the Logic Board
3
Visual Inspection
Large Scale Intergration Failures
Data Line Operation
Self tests
Debugging Table
Troubleshooting the Keyboard
Visual Inspection
Debugging Table
3-1
3-2
3-3
3-4
3-5
4
4-1
4-2
Troubleshooting the Video Monitor
Visual Inspection
Debugging Guide
5
5-1
5-2
Troubleshooting the Power Supply
Visual Inspection
Debugging Guide
6
6-1
6-2
2
SECTIO~
The
1
(
OVERVIEW OF TERMINAL MODULES
design \o~ Televideo terminals permits fast fault
the, terminal is 9ivided into four main modules.
isolation
sinc~
1.
Video monitor
2.
Power supply
3.
Main logic board
4.
Keyboard
The 970 terminal begins a new generation.of terminals. The design
of the video monitor and DC power supply boards has been
simplified to use fewer DC voltages. This change in design makes
these two boards unique and noninterchangeable with the earlier
Televideo terminals 910, 912, 920, 925 and 9S0.Interchange the
video monitor and power supply boards only with boards of the
same type. However a logic board of the older type terminal maybe
connected to the video monitor and power supply of the 970.
To verify a malfunctioning module exchange (swap) each module
with a known good one. Once the malfunctioning module is
identified, refer to the appropriate section in this guide for
futher troubleshooting.
(
()
3
D~SCHARGE rRQC~DUBE
High voltages are retained by the CRT tube and capacitors even
after power has been turned off. As soon as you open the case,
clip one end of a wire to the chassis. Attach the other end of
the wire to an insulated screwdriver. being careful not to touch
the metal part of the screwdriver, gently slip the metal end of
the screwdriver under the cap of the anode, as shown in Figure
1.1
CRT
Test C1 ip
Jumper CorJ~W---ol.
FIGURE 1-1 Discharging Voltages
4
SECTION
~.
FUNCTIONAL
DESCRIPTIQ~
or
MODULES
LOGIC BOARD
The logic board processes, stores and manipulates data received
and transmitted, and generates the video and sync signals
necessary to display data on the terminal's screen.
The
main logic board is divided into the four
following
active
sections'~
1.
Main processor
2.
Display processor
3.
16K RAM memory
4.
I/O Interface logic
POWER SUPPLY
The power supply supplies four DC voltages 12v, -12v, 75v, and 5v
to circuits within the terminal. Two fuses located on the power
supply are user replaceable.
(
.
VIDEO MONITOR
video monitor contains horizontal, vertical, and video
amplification circuits which produce a television-type noninterlaced raster display. Video signals received from the display
circuitry generate pixels (dots) at various positions across scan
lines. These pixels, when combined with other pixels of scan
lines above and/or below a given line, produce characters.
Th~
KEYBOARD
Data is encoded by a 8049 microprocessor located in position A6
of the keyboard. The encoded data is sent to the main logic
board serially via the coiled interface cable. On the main logic
board the serial data is converted to parallel and applied to the
main processor which by way of terminal firmware deciphers the
two bytes of encoded data received from the keyboard processor.
(
5
TBOQijLESHOOTING
~
~
LOGIC ijOARD
VISUAL INSPECTION
With the logic board installed and power r~moved, remove the two
screws at the bottom of the vented cooling tower and swing the
bottom part of the panel away from the case, and check the items
listed below.
1.
Socketed chips: are they all securely seated into their
sockets and are the chip pins all straight?
2.
Connectors: look for
Loose, damaged or corroded connectors
Bad crimps
3.
Wires: are any broken, loose or frayed?
4.
Components: are any components deformed or discolored?
With the logic board removed, make the following inspections.
To remove the logic board:
1.
Turn the power off.
2.
On the logic board, carefully disconnect:
PI, P2, P3, P4 and PS connectors
3.
Remove the four screws in the four corners of the logic
board
4.
Carefully remove the logic board.
6
(l
With the logic board removed, closely inspect the board for:
1.
Deformed, discolored or missing components.
2.
Cracked, broken or lifted traces.
3.
Poor solder joints (loose solder
joints, or solder bridges). _
4.
Bent pins on the IC chips.
balls,
cold
solder
NOTE!
If defects are found, correct them and retest the terminal before
continuing.
~
LSI FAILURES
Since most malfunctions involve LSI chips, this step may quickly
remedy most failures. Exchange all socketed chips with known good
chips, testing the terminal after exchanging each LSI chip. If
the logic board still malfunctions after completeing the previous
steps, confirm the operation of the data lines as outlined in the
section Data Line Operation...
(
The remainder of this section involves troubleshooting to the
component level and requires schematics, an oscilloscope, a
working knowledge of transistor-transistor logic (TTL) with
experience in TTL troubleshooting •
.J.,..l
~
L.INE OPERATION
Confirm that the
proceeding futher.
data
lines
are
operating
properly
before
NOTE!
It is beyond the scope of this troubleshooting guide to list all
possible data line problems.
With the logic board reconnected check the data and address lines
that interface
the zeo CPU chip with the rest of the terminal
logic. There should be activity on all data and address lines
with voltages rangeing from Ov to 5v. If the malfunction persists
after you have confirmed proper operation of the data lines,
follow the procedure in the next section, Debugging Table.
(
7
The following tests are designed to aid the service personel
troubleshooting the 970 terminal.
in
Two 25 pin male RS232 connectors are needed to make a test cable.
The cable is an one to one pin assignm~nt for the following pin
requirements:2, 3, 4, 5, 6, 7, 8 and 20. This cable is to be used
when testing the comunications of the terminal.
tests: Depressing shift SET UP 1 will display all
characters and attributes on the screen. Depressing shift SET UP
3, 4 or ESC t 8 will fill the entire screen with one particular
character. This test is helpful 1 when -adjusting the terminal
focus, height or linearity.
Displa~
Comunication tests: A test cable as outlined above is required to
successfully exercise the test. Connect one end of the test cable
to P3 and the other end to P4. Depress shift SET UP 2 or one of
the sequences below. The result of the test, PASS or FAIL will be
displayed in the lower right of the status line.
Confidence test; Confidence test wil preform certain tests to the
terminal. Depress ESC [ 2 1 Ps Y to initiate the test. Ps is the
parameter indicating the test to be done. Ps is computed by
taking the weight indicated for each desired test and adding them
together. The values assigned each test are defined in table 3.1 •.
TABLE 3-1
WEIGHT
TEST PERFORMED
1
ROM AND RAM TEST
(CHECK ROMS' LRC AND
TEST DISPLAYABLE RAM)
2
RS-232C PORT TEST
(P3-P4 LOOPBACK
CONNECTOR REQUIRED)
4
EIA CONTROL TEST
(P3-P4 LOOPBACK
CONNECTOR REQUIRED)
8
REPEAT SELECTED TEST(S)
INDEFINITELY (UNTIL
FAILURE OR POWER OFF)
8
~
LOGIC BQARD DEBUGGING TABLE
NOTE!
The items listed in the table in this section are only suspect
areas: they should not be automatically replaced when the
symptoms listed are present.
SYMPTOM
SUSPECT AREAS
PART NO.
Z80
9007
6116
74LS166
74S25l
2N22l9
No video
SCHEMATIC
POSITION
A80
A69
A56
A50
A48
03
PAGE
11
14
15
15
15
16
I
Constant or no beep
8049 (KYBD)
Z80
Firmware
A6
A80
A82,87,99
11
11
12
No cursor
9007
74LS374
A69
A6
14
16
Distorted characters
6116
74LS245
74LS374
74LS173
74LS157
74LS166
74S25l
Firmware
A56
A65
A64
A33
A40
A50
A48
A82,87,99
15
15
i5
Bad video every other line
9006
A54,60
#8
Bad attribute"
9006
A53,59
18
Loss of specific attribute
9007
74LS374
A69
A37,45
i4
i8
Horizontal bar
9007
74LS32
74LS32
A69
A68
A7
14
14
19
No transmit P3
75188
Z80 SIO
Z80 CTC
A43
A74
A92
17
17
110
No transmit P4
75188
Z80 SIO
Z80 CTC
A5l
A74
A92
'717
""
"
9
(
IS
15
15
15
.2
110
(
~
DEBUGGING TABLE CONTINUED
SYMPTOM
SUSPECT AREAS
PART NO.
26LS31
Z80 SIO
Z80 CTC .
No transmit P7
POSITION
A89
A85
A92
SCHEMATIC
PAGE
.7
.7
.10
No-receive P3
75189
74LS08
Z80 SIO
Z80 CTC
A27
A58
A74
A92
.7
17
.7
.10
No receive P4
75189
Z80 SIO
Z80 CTC
A57
A74
A92
.7
.7
t10
No receive P7
26LS32
Z80 SIO
Z80 CTC
A84
A85
A92
.7
.7
.10
Incorrect or no kybd response 7414
Z80 SIO
Z80 CTC
74LS138
A100
A85
A92
A93
17
17
110
19
Incorrect Baud rate
Z80 CTC
74LS138
74LS163
A92
A93
Al15
110
19
.1
Loss of Bidirectional
comunication
74LS374
74LS32
A23
A62
12
17
10
SECTIQB i
~
TROUBLESHOOTING
~
KEYBOARD
(
VISUAL INSPECTION
Disconnect the keyboard from the rest of the terminal and remove
the six screws from the bottom of the keyboard case. Carefully
lift of the top of the keyboard case and set it aside.
Check the Key switches for the following:
1.
Foreign objects (e.g., paperclips, staples, matches)
2.
Liquid residue (e.g., coffee, soft drink)
3.
Broken keyswitches
4.
Missing or incorrectly placed keycaps
NOTE I
If defects are found, correct them and retest the terminal before
continuing.
Visual Inspection with the keyboard removed from the case
Remove the screws from the corners of the keyboard and remove the
keyboard from its case.
Inspect the keyboard for:
1.
Deformed or discolored components
2.
Cracked, shorted, or lifted traces
3.
Poor solder joints (loose solder balls, solder bridges,
or cold solder joints)
11
(
llJl KEYBOARD DEBUGGING l'ABLE
SUSPECT AREAS
SYMPTOM
SCHEMATIC
POSITION
PAGE
PART NO.
Keyswitch
11
Open trace,solder joint 11
11
8049 (kybd) A6
One key inoperative/
intermittent
S~veral
keys inoperative/intermittent
Open/shorted
8049
74LS145
Resistorpack
trace
A6
A4,5
RPI
11
11
11
11
All keys inoperative
Open/shorted
8049
Regulator
Crystal
trace
A6
VRI
Y1
11
11
11
II
Incorrect characters
Shorted trace
A6
8049
11
11
No beep or key click
8049
A6
11
12
SECTION .2
~
()
TROUBLESHOOTING THE VIDEOHQNITOR ;.
VISUAL INSPECTIQN
With the video monitor installed turn off the power to the
terminal, remove the two screws from the rear of the CRT case and
place the cover aside. Check the following possible problem areas:
1.
Connectors: look for
A. Loose or damaged connec'tors
B.
Dirt~
contacts
c.
Bad crimps
2.
Wires: are any broken,
3.
Components: are any deformed, leaking, or discolored?
If any defects are found,
before continuing.
loose~
or frayed?
correct them and retest the terminal
With the video monitor remov.d--The following inspections
be made.
should
(
To remove the video monitor:
1.
With the power off remove and set the cover aside and
disconnect the following
connections on the video
monitor:
A. Jl
(DC voltages)
Bil PIO (signal)
C. Jll (yoke)
2.
Disconnect the following parts on the CRT tube:
A. CRT socket (small circuit board at rear of tube)
CAUTION pull socket off straight back to avoid breaking
the small nipple of tube.
B. Anode lead (WARNING see discharge procedure in section
one)
C. Ground wire
3.
Remove the securing screws on the video monitor.
4.
Carefully slide the video monitor out of the case.
13
With the video monitor removed inspect it for:
1.
Deformed, leaking, or discolored components
2.
Missing or damaged components
3.
Cracked or lifted traces
4.
Poor solder joints (loose solder balls, solder bridges,
or cold solder joints)
NOTE!
If defects are found, correct them and retest the terminal before
continuing.
If no defects are found,
power.
reinstall the video monitor and
apply
WARNING!
High voltages are present on the video monitor • USE EXTREME
during troubleshooting.
~
The four adjustments which can be made to the video monitor
listed in Table 5-1. The controls are shown in Figure 5-1.
are
TABLE 5-1
PROBLEM
CONTROL
Intensity of characters too bright, too dim
Bright
Whole screen is to taIlor to short
Height
Characters are not even in height from the
top to the bottom of the screen
Linearity
Characters are not in focus
Focus
14
(
FIGURE 5-1
~
VIDEO MONITOR DEBUGGING GUIDE
The remainder of this section deals with specific
and possible causes.
SYMPTOM:
1.
malfunctions
No Vertical Defection
Check the emmiter of 0201 for the vert. signal.
A. If it is present, proceed to step 2.
B. If it is not present, check the base of 0201.
C. If the vertical deflection is not present at the base,
troubleshoot between the base of 0201 and PIO pin five.
2.
Check the collector of 0202 for the vert. signal.
A. If it is present, proceed to step 3.
B. If it is not present, check the base of 0202.
C. If the vertical deflection is not present at the
troubleshoot back from the base of 0202.
15
base,
(
3.
Check the negative side of C207 for vertical deflection.
A. If vetical deflection is present, the vertical drive of
the video monitor is good. The following areas should be
checked if the vertical deflection continues to fail.
(1) Connectors PIO and J12
(2) Yoke windings
B. Check emmiter of 0203.
C. Check base of 0203.
D. If v~rtical deflection
0203.
present at base of 0203
suspect
E. If not present at base of 0203, troubleshoot back.
F. If 0203 emmiter is good, check 0204 emmiter.
G. Check base of 0204.
H. If vertical
0204.
deflection present at base of 0204
suspect
I. If not present at base, troubleshoot back from 0204.
Since 0203 and 0204 are a matched pair of push/pull
amplifiers, replace both if one fails.
SYMPTOM: No Horizontal Deflection
1.
Check the collector of 0305 for horizontal pulses.
A. If the pulse is present, proceed to step 2.
B. If absent check the base of 0305.
C. If the Horizontal deflection is not present at the base
troubeshoot between the base of 0305 and PIO pin one.
2.
Check the output of IC301 at pin 3 if absent suspect IC30l.
3.
Check the collector of 0303 for horizontal pulse.
A. If present proceed to step 4.
B. If absent monitor the emmiter of 0303.
C. If not present at the emmiter troubleshoot back.
16
4.
Check the
pulses.
collector
of 0301
for
horizontal
deflection
(
A. If pulses are present proceed to step 5.
B. If missing check for a signal at the base of 0301.
C. If no signal present troubleshoot back.
5~
Check the collector of Q302 for the horizontal signal.
A. If present the horizontal deflection amplifiers
operating properly. Check the connection from Jll
the yoke windings.
are
to
B. If not present check the base of 0302 for the signal.
C. If the signal is absent at the base of Q302 troubleshoot
back.
(
(
17
SECTION
~
.6.
TROUBLESHOOTING
~
POWER SUUPLY
VISUAL INSPECTION
With the Power Supply Installed--Turn off power to the
complete the procedure on removal of the logiC board,
the following possible problem areas:
1.
terminal,
and check
Connectors: look for
A. Loose or damaged connectors
B. Dirty contacts
C. Bad crimps
D. Bad fuse
2.
Wires: are any broken, loose, or frayed?
3.
Components: are any deformed, leaking, or discolored?
NOTE I
Check the fuse with an ohm meter. Do not rely on a visual
check.
4.
Loose fuse holder
5.
If defects are found, correct them and retest the terminal.
18
With the Power Supply removed--The following inspections
be made.
should
(
\)
To remove the power supply:
1.
Turn off the power and unplug the power cord from the
wall outlet.
2.
Remove the main logic board as outlined in section 3.
3.
Disconnect K1, K2 on the power supply PCB.
4.
Carefully slide the power supply PCB up away from the
regulators and remove it.
With the Power Supply Removed--Inspect the power supply for:
1.
Deformed, leaking, or discolored components
2.
Burned or lifted traces
3.
Bad crimps on K1 and K2 connectors
4.
Poor connections
If defects are found, correct the defects and retest the terminal
before proceeding.
(
(
19
.
~
POWER SUPPLY DEBUGGING GUlpE
The remainder of this section deals with specific
and possible causes.
SYMPTOM:
1.
malfunctions
No +SV DC
Remove Fl03 and check for approximately 34V DC. If the
correct voltage is not present, suspect the following
components:
A. Dl05 through Dl08
B. Bad crimps, or poor connections to Kl.
If the correct voltage is present, suspect the following
components:
2.
A. Fl03
B. 80S06Z
C. CI06 through Cl12
SYMPTOM:
1.
+SV DC is low
Check the following components:
A. Iel03 (80506Z)
B. Cl06 through Cl12
C. Damaged or loose connectors
SYMPTOM:
1.
No +12V DC
Remove FI02 and check for approximately 26V DC. If the
voltage
is
not present,
suspect the
following
components:
A. DlOl through Dl04
B. Bad crimps or poor connections to KI.
2.
If the correct voltage is present, suspect the following
components:
A. ICIOI (3l22P)
B. QlOl
C. CIOI, CI02, Cl03, and Cl16
20
SYMPTOM:
1.
(:
+12V DC is low
Check the following components:
A. RI02
B. lCIOl (3122P)
C. CI03
D. Damaged or loose connectors
SYMPTOM:
1.
No -12V DC
Check the following components:
A. 0101 through 0104
B. CI04 and CI05
C. ICI02 (7912)
D. Damaged or loose connections
SYMPTOM:
1.
No +75V DC
Check the following components:
(
A. 0109
B. C1l3, C114, and C115
C. QI02 and QI03
SYMPTOM:
+75V DC is low
1.
Adjust SFR3
2.
If unable to adjust SFR3, check the following components
A. Q102 and Q103
B. 0110
()
21
Intel
8048 H/8048H-1 /S035H LlS035H L-1
HMOS SINGLE COMPONENT S-BIT MICROCOMPUTER
• 8048H/8048H-1 Mask Programmable ROM
• 8035HL/8035HL-1 CPU Only w:ith Power Down Mode
ROM
• 641K xx 88 RAM
CP,U, ROM, RAM, 110 in Single
• a-BIT
Package
• High Performance HMOS
• Reduced Power Consumption
1.4 usec and 1.9 usec Cycle Versions
• All
Instructions 1 or 2 Cycles.
• Over 90 Instructions: 70% Single Byte
27 1/0 Lines
• Interval TimerlEvent Counter
• Easily Expandable Memory and 1/0
Compatible with 808018085 Series
• Peripherals
• Two Single Level Interrupts
The Intelt!) 8048H/8048H-1/8035HLlB035HL-1 are totally self-sufficient, B-bit parallel computers fabricated
on single silicon chips using Intel's advanced N-channel silicon gate HMOS process.
The 804BH contains a 1K X B program memory, a 64 X8 RAM data memory, 27 110 lines, and an 8-bit
timerlcounter in addition to on-board oscillator and clock circuits. For systems that require extra capability
the 8048H can be expanded using standard memories and MCS-80'·/MCS-:-B5'· peripherals. The B035HL is
the equivalent of the 804BH without program memory and can be used with external ROM AND RAM.
To reduce development problems to a minimum and provide maximum flexibility, a logically and functionally
pin compatible version of the B04BH with UV-erasable user-programmable EPROM program memory is available. The 874B will emulate the 804BH up to 6 MHz clock frequency with minor differences.
The 8048H is fully compatible with the B04B when operated at 6 MHz.
These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have
extensive bit handling capability as well as facilities for bOlh binary and BCD arithmetic. Efficient use of
program memory results from an instruction set conSisting mostly of Single bit instructions and no instructions over 2 bytes in length.
PIN CONFIGURATION
BLOCK DIAGRAM
LOGIC SYMBOL
~r
TO
ITAL 2
VCC
T1
P27
IUsn
P2.
ft
P25
P24
ITAI. 1
iHl'
fA
1(0
;SEN
\iii
ALE
I'll
01 2
1'10
Ol~
VOO
PROG
P23
01 5
01,
I041H
I035HL
I04IH·l
IOl5HL·1
"4
P13
P12
01,
1'22
1'21
Vss
P20
WORDS
OATA
MEMORY
,~
1024 WORDS
PROGRAM
MEMORY
CLOCK
PORT
' 2
P17
Pll
Pl5
01 0
Oi,
0114
PORT
·1
A
')
I BIT
CPU
-
'v--
V
• BIT
TIMEII
EVENT COUNTER
V
27
1/0 LINES
IUS
In.el CorpOtaflon aSlumes no ,esponl.blhty for the uN of any ttrCUlt~ Olne, than cueul")' Imbodled '" an In,•• produCI NO other CI'ClIll palent heenHS .re Implied
&In'el Corpor.hOf\ 1110
AFN·Ol4ilA·OI
infel
8048H/S048H·1 /S035H lIS035H l-1
~OO~[LO[MJOrm&OOW
PIN DESCRIPTION
Designation
Pin:
Function
VSS
Circuit GND potential
Vce
20
26
40
PROG
25
Output strobe for 8243 110
expander.
P10-P17
Port 1
P20-27
Port 2
27-34
8-bit Quasi-bidirectional
port.
B-bit quasi-bidirectional
port.
P20-P23 contain the four
high order program counter
bits during an external program memory fetch and
serve as a 4-bit I/O expander
bus for 8243.
VOO
21-24
35-38
DBD-DB7
BUS
12-19
Pin:
Main power supply; +5V
during operation.
True bidirectional port
which can be written or read
synchronously using the
RD. WR strobes. The port
can also be statically
latched.
Input pin testable using the
conditional transfer instructions JTO and JNTO. TO
can be designated as a clock
output using ENTO CLK
instruction.
T1
39
Input pin testable using the
JT1. and JNT1 instructions.
Can be designated the
timer/counter input using
the STRT eNT instruction.
INT
6
Interrupt input. Initiates an
interrupt if interrupt is
enabled. Interrupt is disabled after a reset. Also
(
Function
testable with conditional
jump instruction.
(Active low)
Low power standby pin
Contains the 8 low order
program counter bits during
an external program
memory fetch. and receives
the addressed instruction
under the control of PSEN.
Also contains the address
and data during an external
RAM data store instruction,
under control of ALE, RD.
and WR.
TO
Designation
RD
8
Output strobe activated
during a BUS read. Can be
used to enable data onto the
bus from an external device.
Used as a read strobe to
external data memory.
(Active low)
RESET
4
Input which is used to
initialize the processor.
(Active low)
(Non TTL V,H)
WR
10
Output strobe during a bus
write. (Active low)
Used as write strobe to
external data memory.
ALE
11
Address latch enable. This
signal occurs once during
each cycle and is useful as a
clock output.
The negative edge of ALE
strobes address into external data and program
memory.
F5'S'EN
9
Program store enable. This
output occurs only during a
fetch to external program
memory. (Active low)
SS
5
Single step input can be
used in conjunction with
ALE to "single step" the
processor through each
instruction. (Active low)
EA
7
External access input which
forces all program memory
fetches to reference ~xternal
memory. Useful for emulation and debug. and
essential for testing and
program verification.
(Active high)
XTAL1
2
One side of c"rystal input for
internal oscillator. Also
input for external source.
(Non TTL VIH)
XTAL2
3
Other side of crystal input.
AFN·QU,\A·O,
(
(
intel
804SH/S04SH-11S03SH L.. 1IS03SH L-1
-"'STRUCT~ON
SET
Sub,outln.
MnemOllle
ADD A, R
ADD A,@R
ADD A,' dlla
ADDC A, R
ADDC A,@Ro
ADDC A.' dala
ANL A. R
ANt A.@R
ANL A.' dlla
ORL A. R
ORL A@R
ORL A. /I dall
XRL A. R
XRL A. @R
XRL. A .• dala
INC A
DEC A
CLR A
CPL A
DA A
SWAP A
RL A
RLC A
RR A
RRC A
D..erlpllon
Add ,eglSle, to A
Add data memory 10 A
Add Immedllte to A
Add ,eglsle, with car,y
Add dala memo,y wllh carry
Add Immedlale wIth carry
And ,eglsle, 10 A
And dlla memory 10 A
And Immedlale to A
0, ,eglste, to A
Or dlla memo,y to A
Or Immedlale to A
Exc.luslve. or ,eglste, 10 A
ExclusIve or dall memory 10 A
ExclusIve 0, Immedlale 10 A
Incremenl A
Dec,emenl A
Clear A
Complemenl A
DecImal adlusl A
Swap nibbles 01 A
Rotale A lell
ROlale A lell Ihrough ca,ry
Rotale A rlghl
ROlale A rlghl Ihrough carry
,, ,
,
B,I•• C,e",
1
2
2
1
1
2
2
t
1
2
2
1
,
,
2
2
1
2
2
oun
oun
,
l
,,
Byl•• C,e'"
2
2
,
2
2
2
2
2
2
2
2
2
2
2
2
2
2
R.gl,'.r.
Mn.monle
INC R
INC@R
DEC R
D •• crlpllon
Incremenl ,eglsler
Incremenl dala memory
Decremenl reg Isler
Brt• 1 Cye",
O..crlpllon
Jump uncondlllonal
Jump Indorecl
Decremenl regIster and skIp
Jump on carry = ,
Jump on carry = 0
Jump on A ze,o
Jump on A not ze,o
Jump on TO = 1
Jump on TO = 0
Jump on Tt = 1
Jump on Tt = 0
Jump on FO = 1
Jump on Fl = ,
Jump on Ilmer flag
Jump on INT = 0
Jump on accumulato, bll
1,1•• Crele.
De.erlpllon
Clear carry
Complemenl carry
CLea, flag 0
Complemenl flag 0
Clear flag'
Complemenl flag'
Brl •• Crel ••
2
2
2
2
FIIg.
Mn.monlc
CLA C
CPL C
CLR FO
CPL FO
CLR Fl
CPL F'
,
,,
Mnemonic
MOVA. R
MOV A. @R
MOV A.' data
MOV R. A
MOV@R. A
MOV R • dala
MOV @R. 'oala
MOV A PSW
MOV PSW. A
XCH A. R
XCH A. @R
XCHD A.@R
,
,
,,
,
,
MOVX A @R
MOVX @R. A
MOVP A. @A
MOVP3 A, @
D •• c"ption
Byl •• Cycl ••
Move ,eglsler 10 A
Move dala memory 10 A
Move Immedlale 10 A
2
2
Move A 10 regis Ie,
Move A 10 dala memo,y
Move Immedlale 10 ,eglsle,
2
2
Move Immedlale 10 dala memo,y 2
2
Move PSW 10 A
Move A 10 PSW
Exchange A and ,eglster
Exchange A and dala memo,y
Exchange nIbble 01 A and
,eglsle,
Move exlernal dala memory 10 A
2
Move A 10 exlernal dala memory
2
Move 10 A Irom currenl page
2
2
Move 10 A I,om page 3
,
Timer /Counl.,
D.lerlpllon
Read IIme,/counler
load Ilmer/counle,
Slarlllmer
Slarl counle,
SlOP Ilme,/counler
Enable IIme,/counler Interrupl
DIsable Ilme,/counter Inlerrupl
Byl •• Crc",
Mn.monle
EN'
DIS'
SEL RBO
SEL RB,
SEL MBO
SEL MB'
ENT 0 ClK
D.lerlpllon
Enable external Inlerrupl
DIsable external inlerrupl
Select reg ISler bank 0
Selecl ,eglsler bank ,
Selecl memory bank 0
Selecl memory bank ,
Enable Clock Oulpul on TO
Byle. Cycl ••
1
Mnemonic
NOP
D.lcrlpllon
No ope,atlon
Byl.' Crcl ••
1
1
Mn.monlc
MOVA T
MOV T. A
STRT T
STRT CNT
STOP TCNT
EN TCNT,
DIS TCNTt
Conlrol
B'lnch
Mn.monlc
JMP add,
JMPP@A
DJNZ R. add,
JC add,
JNC add,
JZ add,
JNZ addr
JTO addr
JNTO add,
JTt addr
JNT, addr
JFO addr
JF, addr
JTF add,
IN' addr
JBb addr
D •• crlplion
Jump 10 sub'oulllle
Relurn
Relu,n and ,eSlo,e stalus
D.la Move.
Inpul/Oulput
D ••crlptlon
MnemonIc
Inpul porI 10 A
IN A. P
OUlpul A 10 port
P. A
And Immedlale 10 port
ANL p.' dal.
ORL P.• dlla
Or Immedlale 10 porI
INS A. BUS
Inpul BUS 10 A
BUS. A
Oulpul A 10 BUS
ANL BUS .• dlla And Immedlale 10 BUS
ORL BUS .• dala Or Immedlale 10 BUS
MOVD A.P
Inpul explnde, port 10 A
MOVD P, A
Oulpul A 10 expande, port
ANlD P. A
And A 10 expander porI
ORLD P . A O r A 10 explnder port
Mn.monlc
CALL addr
RETR
RETR
Byt •• Cyel..
,
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
,
S04SH/S04SH-1/S03SHL/S03SHL-1
A.C. CHARACTERISTICS (PORT 2 TIMING) TA = O°C to 70°C, VCC = 5V± 10%, VSS =OV
.
Parameter
Symbol
8048H
8035HL
6 MHz
Min.
8048H-'
803SHL-'
8 MHz
Max.
Min.
11 MHz
.
Min.
Max.
Max.
Unit
tcp
Port control Setup Before Falling
Edge of PAOG,
110
105
ns
tpc
Port Control Hold After Falling
Edge of PAOG,
100
90
ns
tpA
PAOG to Time P2 Input Must Be Valid
tpF
Input Data Hold Time
top
Output Data Setup Time
250
210
200
ns
tpo
Output Data Hold Time
65
35
20
ns
tpp
PAOG Pulse Width
1200
970
700
ns
tpL
Port 2 I/O Data Setup
350
300
250
ns
tLP
Port 2 I/O Data' Hold
150
65
20
ns
al0
700
150
0
0
150
0
(
650
ns
150
ns
PORT 2 TIMING
ALl
J
\'--_ _~I
-ilCAr (
\'-------:----~
r-
OUT'UT
'C"
'ORT 20 3 DATA
I
POIIT COHTROL
1DP
T'PDl
I
OUTPUT DATA
EXPANDER
'OIlT
I
IN'UT
PORT 20 3 DATA
PCH
PORT COHTROL
,pc~
LICP-
I
'1I0G------~~··--{-,
I
BUS TIMING AS A FUNCTION OF TCY •
SYMBOL
TLL
TAL
TLA
TCC (1)
TCC (2)
TOW
TWO
TOA
FUNCTION OF
7/30
TCY
1/10
TCY
1/15
TCY
1/2
TCY
2/5
TCY
2115
TCY
1115
TCY
0
TeV
MIN
MIN
MIN
MIN
MIN
MIN
MIN
MIN
SYMBOL
TCC (1) : AOIWA
T
(2) : PSEN
cc
• APPROXIMATE VALUES NOT INCLUDING GATE DELAYS.
TAD (1)
TAD (2)
TAW
TAD (1)
TAD (2)
TAFC
TCA
FUNCTION OF TeV
11/30
MAX TAD (1) : AD
TCV
3/10
MAX TAD (2) : PSEN
TCY
3/10
MIN
TCY
1/2
MAX
TCY
1/3
MAX TAO(1):AO
TCY
1/30
MIN TAO (2) : PSEN
TCY
1/15
MIN
TCY
(
8048H/8048H-1/8035HL/8035HL-1
WAVEFORMS
""'1-----r- -. -ILl---!
ALE
ICY-··--
-----1
I
JI
L.._ _ _ _ _ _- '
L
J
ALE
J
~'ee-j
I-
~lllA
PSEN
_
_L..--I- - - - - I
IAFe:
IUS FLOATING
I-
--------,
I--
L
-'DR
I
FLOATING
!:~,:'
-lAD
Read From External Data Memory
Instruction Fetch From External Program Memory
WR
-I
f--
~
~-
J
~
iFlOATING
_ _ _:1'AL
ALE
I
liD
leA
L
lec
2.4V - - - - " " " \
O.4SV
.
,oX
,..._ _ __
0 ,~X 20~
_ _ _ _- - '
TEST POINTS
2
-:0
_
-
'---_ __
-
IUS
Input and Output for A.C.Tests.
Write to External Data Memory
A.C. CHARACTERISTICS TA = ODC to 70 DC VCC = VOO = 5V ± 10%, VSS = OV
8048H
803SHL
8048H-1
803SHL-1
Symbol
Parameter
tLL
ALE Pulse Width
400
270
150
ns
tAL
Address Setup to ALE
75
75
70
ns
tLA
Address Hold from ALE
65
65
50
ns
tcc
Control Pulse Width (PSEN, AD, WA) 700
490
300
ns
tow
Data Setup before WA
370
370
280
ns
two
Data Hold after WA
80
80
40
ns
ICY
Cycle Time
2.5
1.875
1.36
J.ls
tOA
Data Hold
tAD
PSEN. AD to Data In
tAW
Address Setup to WA
tAD
Address Setup to Data In
tAFC
Address Float to AD. PSEN
tCA
Control Pulse to ALE
6 MHz
8 MHz
11 MHz
Conditions
Min. Max. Min. Max. Min. Max. Unit (Note 1)
NOTE 1: Controloutputl
BUS outputl
0
CL = 10 pF
CL = 150 pF
200
0
500
150
340
210
230
0
950
100
ns
200
ns
ns
200
650
400
ns
0
0
-1
ns
10
10
0
ns
NOTE 2: BUS High Impedance Load: 20 pF
CL = 20pF
(NOTE 2)
(
PART NUMBER
R6551
R6500 Microcomputer System
DATA SHEET
Asynchronous Communication Interface Adapter (ACIA)
Th. R6551 Asynchronous Communicltion Int.rflC' Adept.r
IACIAI provides I progrlm-controlled int.rflCe betw_n B-bit
microprocessor·baaed syst.ms Ind IIri.1 communic.tion dltl
IIts and mod.ms.
W,th its on-chip blud rite gen.rator, the R6551 is ceplbl. of
trinsmitttng It 15 differ.nt prog"m·aelectlbl. rites betwHn
SO baud Ind 19,200 baud, Ind ree'iving It .ither the transmit
rite or It 16 times In IlCternll clock rite. The R6551 hIS pro· .
grlmmlble word lengths of 5, 6, 7, or 8 bits; even, odd 'or no
perity; 1. 1·1/2 or 2 stOP bits.
W,th the R6551, I cryltll is the only required elCternll support
component - eliminlt,ng the multiple-component suPPOrt thlt
il typiCllly nHded.
In Idchtion. the R6551 is designed for maximum programmed
control from the CPU. to simplify hlrdware implem.ntltion. A
control reg'ster Indl separlte command reginer permit the CPU
to '"ily llleet the R6551', operatinll mode. end chICk detl,
perameters and stltuS.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Compltible with B·bit microprocessors
Full duplex or hllf duplex operltion with buffered rece,ver
end transminer
15 programmable Blud R,tlS ISO to 19,2001
Receiver dltl flte mlY be identiCl1 10 blUd rite or mlY be
16 tim" the extern~1 clock input
Dltl set/m.m control functions
Programmlble word lenllths, number of Itop bits. Ind parity
bit gene fit ion Ind detection
Programmlble interrupt control
Software reset
Progrlm·selectable seri.lecho mode
Two chip IIlects
2 MHz or 1 MHz clock rate
Sinille +5V :t5% p_r supply
2B·pin pllstic or ceramic DIP
Full TTL compatibility
Number
PICk...
Type
Frequency
R....
OOC to +700 C
OOC to +70o C
R6551P
Pllstic
1 MHz
R6551AP
Plastic
2MHz
R6551C
Ceramic
1 MHz
R6551AC
Cerlmic
2 MHz
OOC to + 70°C
OOC to+700C
<::.
DATA
16--ru
BUS
BUFFERS
TRANSMIT
DATA.
IHIFT
REGIITERS
i1IO
"'--Rf1
AJW
"'--mf
CSO
es;
RSO
I/O
CONTROL
a..""'.. R.c
"--XTL.
I--.XTLO
"51
AIW
"2
VSS
CSO
C51
iAQ
If£!
A.C
XTll
XTlO
07
D6
05
5
6
7
8
O.
eft
9
03
02
T.O
10
0'
D'fR
"12
~
A.O
ASO
AS'
,.
13
DO
C Aock_"ln'er _ _' Corpof •• oOn , . ,
All A,o"" A.... P"n'eeI ,n U S.A
JI2
iii
TIMING
• CONTROL
LOGIC
aTJ(
11ft
vee
VIS
RECEIVE
DATA.
SHIFT
REGISTERS
R.D
bD
6'ErI
vee
R6551 Pin Configuration
:::T
a
=
o
c
•
n
o
3
3
c
_.
n
Ordering Information
TemperetuN
:1
n
::I
1)().07
Or.r
l>
~
R6SS1 Interface Diagram
cha,.. Wllhoul
_ICe
to
,..1
Doc_ft' No. 21000 DIS
R.". 1 • .Ienuery
!
o·::I
Control Register
INTERNAL ORGANIZATION
The Control Register selects the desired baud rate, frequency
lOurce, word length, and the number of stop bits.
RII
iiiO
I
L..~
I
&Ill
II"';
".c:
c:so
C$;
• TLI
(
•
1_ 1'.L.'• .L. . . 1_
I
' ,••1' ••"••"."1I
I
hO
DOD'
aLICTEO hUO IlATE ' •••
H!
•••
•••
•••
••••
••
•••,
,•••
, ,
,• ••
•••,
,.
....
ano
.
••
"
·...
....
IIfJi
.n
'"
_d
••0
...I......
..'10.. _
,....
c.....
_
10
--.•- --'10
_
lID
_
--..... -1M
_
~--------- .ICIIVIII CLOCI _ I , _
,...........
.·' .......1"--=...
................
' - - - - - - - - - - - - - _ . 0 LlIIOGTN IWLI
R65S1 BI')ck Diagram
Transmitter/Receiver
Bits 0·3 of the Control Register select the divisor used to generate the
baud rate for the Transmitter. If the Receiver clock is to use the same
baud rate as the Transmitter, then RxC becomes an output pin and
can be used to slave other circuits to the R6551.
II, ...
.
, ,
"
'---------------- ..OO'." ......u
....1
'-'It.e
,·z .........
........
......
.,
.,t'.. WL· ..........."1
'....L·._ ....'I
R65S1 Control Register
~-""'T'--R.D
(
~---------------------- R.C
Command Register
ICTLI
XTLO
The Command Register controls specific modes and functions_
Transmitter/Receiver Clock Circuits
L.-J
~
Transmit and Receive Data Registers
These registers are used as temporary data storage for the 6551 Transmit and Receive circuits. The Transmit Data Register is characterized
as follows:
•
Bit 0 is the leading bit to be transmitted.
•
Unused data bits are the high-order bits and are "don't care"
for transmission.
OATA fE .... INAL .IADY lOT.,
•• Del. ' ......1 NIM ......" dS,.. .....
1 • DItII T............. fGTl' UwI
lNTu • ...,. IIOUIIT DIIAoILU 11_
•• IIIIaI ......
' · ••00......
TIIANWo"n ,'''',,",,"
ITICI
II
_"L
m.N... T, _ _ ... O_
. , 11ft. L... ,....-. I.......... .....,
, • 11ft. L.... T,..... I....' ..... INIIIIIIII
.. .......
_.......
. . . _0_
1 111ft. ",
L._
. , Tr..-.;t:
,.,... ~
_ .......
.. ToO
' - - - - - - - - - - IIKIIVI.ICHO _ I
"'UI'
' ••....,1. . . . . .
The Receive Data Register is characterized in a similar fashion:
L-_ _ _ _ _ _ _ _ _ _ _ ....OTYMODII_LU_.
.... _ROL_
....,c..O_
,......
, ,.....
........" •• a.-...t
•
Bit 0 is the leading bit received.
L..--------------.A."'tMODI
•
•
Unused data bits are the high-order bits and are "0" for the
receiver.
Pari'y bits are not contained in the Receive Data Register, but
are stripped-off after being used for IICternal parity checking.
Parity and all unused hlgh-order bits are "0"_
I I
,_*"........
11000000,.,.•• T,................
•
""11"
I~I~I~I:I:I:I:I:I=='-
,
1'. . Patti,
, . 1IIffII ..... y •• T~
..... ya...t.D .......
, , ....... ""'.cY',............
..... ,OIeIIlD......
R6551 Command Register
esc, CS1
Status Register
The StlltuS Register reports the status of various RS551 functions
l I I I I I 11]
L ,,,,"y "."1,
IChip Selects)
The two chip select inputs are normally connected to the processor
address lines either directly or through decoders. The R6551 is selected
when eso is high and CSl is low.
RSO, RS1 (Reviner Selects)
E...,·
o • ,..
The two register select lines are normally connected to the processor
address lines to allow the processor to select the various R6551 internal
registers,
The following table indicates the Inlernal register select
coding:
1,-
1 • P.,IIlV I"., Detect"
f'''''"1fIIfI
1".,-
o .... ".-"" ',ro'
1 " FI~ E"~ De,. ."
0 -....
0 . . . . ' ..
'·'tIM
T'-"Im..,
DeUI Reti'$l~
RS1
RSO
Write
Read
0
0
Trllnsmit Data
Register
Receiver Data
Register
0
1
Programmed
Reset (Data is
"Don't Care")
Status Register
1
0
Command Register
1
1
Control Register
fMP'tv
O·
.... I""".
1 .. ER'ItIM't
t
D.15
c."...,
O.. ctC1 I~I
o ..
DeD to .... 1000ecl'
1 .. oeD h.... INol OCliH11!1l!1
Dill. $tvt Rudy IDSRI
o.
DSA fDw CR_"I
1.m~INoI 111_,.,1
ktc.. rvlM
unal
OiliNG .,...,'.
1 .. l"t8t"fYl"l .... 0eN".
Note that only the Command and Control registers are read/write.
The Programmed Reset operation does not cause any data transfer,
but is used to clear Bits 0 through All
~ - - . . CoIyIor..Roght............
"'""ed III U.S.A
Byt..
Byt..
Bytes
Byt..
II,.
•
I
-!
n
~
8
m
•o
fit
21
(I)
Ordering Informetion
Order Number:
.......
n
R65XX __ _
Microproc.ssors with On-Chip Clock Osciliitor
Modll
a
IT.mperlture Range:
No suffix· DoC to +700 C
E .....OoC to +850 C
(Industrial'
MT. -6So C to +1250 C
CMilitary)
M· MIL-STD.a83.
CI. . 8
Package:
e·
Ceramic:
p. PI-"=
(Not AIt.ible for
M or MT .,fflx)
FfWt/Uincy Ringe:
No suffix· 1 MHz
A· 2 MHz
Mod.1 Oesignltor:
XX· 02,03,04, ... 15
NOTE: Contact your local Rockwell Repre.ntatiVl
concerning IVliiability.
SpeclfleetlOM .,bjeGt to
chWlgll wl1hout no. .
."
...
c:
-
R6500 Signal Description
ClGcbI.,.•
~
The R651X requlntl a two ph. . non-overlllPPlng clock that runs
III the V cc volt... lwei.
Non n.lt'" l..-rupt CAllI)
The R650X clocks are IUpplled with en In ..maI clock uener1lltor.
The' fnlquanc:y of theM clockl II axtamally controlled.
RIll II en unconditional Interrupt. FoilowI", completion of the
current instruction, tha sequanc:e of operations defined for iRa
will be performed, ,...rdl... of the state Interrupt m.k fill. The
veCtor add,.... loaded Into tha progrlm counter,low and high, are
locatlOl:ll FFFA end FFFB raapactlvely, tharHy transferring program control to tha memory vector located at thlll add,.....
Tha Instructions loaded It these locations c.... tha microproc·
IIIOr to brlnch to a non-m.kab/a interrupt routine in memory.
Add,.. .... IAO..A11)
Th_ outp<l are TTL compatlbla, ClPabia of driving onaltandard
TTL load and 130pF.
o.u IIuI (00.07.
Eight pins ara used for tha data bus. Thil II a bidirectional bus,
traNferring data to and from tha device end paripheral.. Tha out·
p<I ara t,i .. tate buffars capable of driving one standard TTL load
and 130 pF.
DlltlIIuI Enable IDBEI
Thil TTL compatibla input allows external control of the t,i ..tate
dati output buffers and will enable tha microprocessor bus driver
when In tha high nata. In normal operation DBE would be driven
by tha ph... two '.2' clock, thus allowing da .. outp< from
microproceuor only during
During tha rud cycla, tha dati
bus drivers ara Internally disa6led, becoming ...ntlllly an open
cin:ult. To dlJlble data bul driversaxtamally, DBE should be hald
low.
.2'
R..ty (HDV)
This input signal allows the ullr to halt or single cycle thl micro·
proclUOr on all cycles except write eycl... A nllJlltive transition
'to tha low stlte during or coincident with phlle one 1.1' will halt
thl microprocessor with the output addr... lines reflecting the
currant addr... being fltched. If Ready il low during a write
eycle, it is ignored until the following raed operation. Thil con·
dition will remain through a subsequent phlle two 1.2' in which
the Reedy signal is low. This feature allows microprocessor inter·
facing with the low speed PROMs II well II fISt Imax. 2 cycle'
Direct Memory Ace... IOMA).
lnt.rupt H. . . . liAO)
This TTL level input requests that an Interrupt sequence begin
within the microprocessor. Tha microprocessor will complete the
current instruction being eXlCuted before recognizing the request.
At that tlma, tha interrupt milk bit in the StatUI Code Register
will be examined. If the interrupt milk fll9 il not lit, the microprocessor will begin en interrupt sequence. Tha Program Counter
and PrOClllor StatuI Register are stored in the stack. The micro·
processor will then lit the interrupt mask flau high so that no fur·
ther internJpts may occur. At the end of this cycle, the program
counter low will be loaded from address FFFE, and program
counter high from locatiC)n FFFF, therefore transferring program
control to the memory vector located at these addresses. Tha
ROV signal must be in the high state for any interrupt to be rec·
ognized. A 3Kn external resistor should be used for proper
wire·OR operation.
A naptive going edge on thl. Input raQUelti that a non-malclble
Interrupt sequence be generated within the microproc.or.
NMI also ,.quintl an axtemal 31< n retll.tar ~ Vcc for pFoplr
wlra-OR operationl.
Inputs iRQ and NMI are hardw. . Interrup1l.lin. that are SImpled during .2 (ph. 21 and will btuln the appropriate intarrupt
(ph..
followi", the complation of tha curroutine on the
rant Instruction.
.1
l'
let Overflow Fill (1.0.)
A negative going edge on this input IIts the. overflow bit In the
Statui Code Regilter. Thillign.1 il sampled on tha trliling edge of
.1 and must be .xt.rnally synchronized.
SYNC
Thll output line il provided to identify thOM eyela in which the
microprocessor is doing In OP CODE fatch. The SVNC line I0Il
high during
of an OP CODE fetch and Itaya high for the
remainder of that cycla. If tha RDV line II pulled low during the
clock pulll In which SVNC want high, tha prOClllOr wlilitop
in its current Ita.. and will remain in the ItllI until the RDV line
goes high. In this manner, the SVNC Ilgnll Cln be used to control
ROV to Caull lingl. instruction execution.
.1
.1
(
Ha.t
This Input is uled to ....t or ltart tha microproclllOf from I
power down condition. During the time that this line is held low,
writing to Or from tha microprocessor is inhibited. Wh.n a posi·
tive edge Is detected on the input, tha microproclllOr will imm..
diately begin the reset sequence.
After a system initi.lilltion tlma of Ilx clock cycl.., tha m.k
interrupt flag will be set and the microprocessor will loid the program counter from the memory vactor location. FFFC.nd FFFO.
Thil is the Itart location for program co!'trol.
After VCC reaches ".75 volts in a power up routine, reset mUit be
held low for at least two clock cycles. At thil time the RfW Ind
ISYNC) signal will becOme valid.
When the reset signal 90IS high following these two clock eycla,
the microprocessor will proceed with tha normal raset procadure
detailed above.
(/
ADDRESSING MODES
ACCUMULATOR ADDRESSING - Thil form of edd,..ing iI
nlPrnented with a one byte i"'truction, implying an aperation on
the accumuletor.
IMPLIED ADDRESSING - In the implied edd,.ng mode, the
add,.. containing the aperanc:l It implicitly Ita1IId In the _ration
code of the lnatruction.
IMMEDIATE ADDRESSING - In Immadl. . edd,..lnt, the
operand iI contained In the MCond byte of the inatruction, with
no further memory edd,..ing required,
RELATIVE ADDRESSINO- Relative eddraaslng .. uaed only
with InndI IIIItNC1ionI and .tabn. . a daItIMtIon for the condition_lnndI_
ABSOLUTE ADDRESSING - In abIolute edd,..lng, ~MCOnd
b\lte of the instruction rpacif... the eight low order bitl of the
affective add,.. while the third byte rpaciflas the eight high
order bitl. ThUI, the absolute add,..lng modi _IOWI
to
the antlre 85K bytal of addmuble memory.
-=-
ZERO PAGE ADDRESSING - The zero page Instructlonl _low
for thoner codl and execution tim.. by only fetching the MCond
b\lte of the instruction and _mine , zaro high edd,.. b\lte.
Ca,.,ful u. of the zaro paga can ,..,It in lignifant incre_ in
code 'fficlency.
INDEXED ZERO PAGE ADDRESSING - IX, Y indexing) - Thil
form of addressing il ul8d in conjunction with the index regi.ter
and i. referred to .. "Zero Page. X" or "Zaro Page, Y". The effective addrea il calculated by adding the IICOnd byte to the contents of the index regilter. Since this is a form of "Zero Paga"
addreaing. the content of the second byte referenc:ea e location in
page zaro. Additionelly due to the "Zero Page" addreuing neture
of this mode, no carry i,added to the high order 8 bits of memory
and crouing of page boundari.. don no,t occur.
INDEXED ABSOLUTE ADDRESSING - (X, Y indexing) - Thil
form of addressing il ul8d in conjunction with X and Y index "It
ilter end is referred to .. "Absolute. X", end "Absolute, Y". The
effective addre. il formed by adding the contents of X or Y to
the addrea contlined in the second Ind third byt.. of the innruction. Thi. mode Illows the index regilter to contein the index or
count velue end the instruction to contein the base addreu. This
type of indexing IIiOWI eny locltion referencing end the index to
modify multiple fields resulting in reduced coding Ind execution
time.
The MCond bvtI of th. instruction bacom. the aperand which ..
an "Offeet" added to the COnlanti of the lower eight bits of the
progrem counter when the counter ..... It the nut Instruction.
The range of the offIet II -128 to +127 by. . from the next
instruction.
INDEXED INDIRECT ADDRESSING - In indexad Indirect
addreuing (referred to .. (Indirect, XII, the aacond by. of the
instruction It added to the contents of the X index register, discerding the carry. The result of this addition points to I memory
10000ion on page zero whOM contents Is thl low ordareight bitl
of the effective add,... The next memory location in page Zlro
conteinl the high ordar eight bits of the effectivi add,.... Both
memory locltions specifying the high and low order by. . of the
effective add,.. must be in paga zaro.
INDIRECT INDEXED ADDRESSING - In indirect Indexad
addreaing (referred to .. (lndirectl, YI, the second byte of the
instruction points to I memory 10000ion in paga zaro. Thl contents of thil memory locltion il added to the contents of the Y
index regiltlr, the result being the low ordar eight bits of the
effective add,... Thl clrry from this addition is added to the
contents of the next p . zaro memory 10000lon, the result baing
the high order eight bits of the effactive add,...
ABSOLUTE INDIRECT - The second byte of the innruction
contains the low order light bits of e memory location. Thl high
order eight bill of that memory locltion is contained in tha third
byte of the illltruction. The contents of the fully lPICified memory location II the low order byte of the effective add,... The
next memory location COntlilll the high ordar byte of thl Iffectiva address which is loaded into the sixt.en bits of the progrem
counter.
INSTRUCTION SET - ALPHABETIC SEQUENCE
ADC Add Memory to Accumulator with Cerry
AND "AND" Memory with AccumulltOr
ASL Shift left On. Bit (Memory or Accumulatorl
BCC
BCS
BEQ
BIT
BMI
8NE
BPl
BRK
BVC
BVS
Branch on Carry CI.lr
Branch on Carry Set
Brlnch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Breek
Branch on Overflow Clelr
Branch on Overflow Set
ClC
ClD
Cli
CLV
CMP
CPX
CPY
Clear Cerry Fleg
Clear Decimal Mode
Cleer Interrupt Disable 8it
Clear Overflow FIlii
Compare Memory and Accumulator
Compare Memory and Index X
Compare Memory end Index Y
DEC Decrement Memory by One
OEX Decrement Index X by One
DEY Decrement Index Y by One
EOR "Exclusive-or" Memory with Accumulator
INC
INX
INY
Increment Memory by One
Increment Index X by One
Increment Index Y by One
JMP
JSR
Jump to New Location
Jump to New Location Saving Return Addr...
LOA
LOX
LOY
LSR
Load Accumulator with Memory
load Index X with Memory
load Index Y with Memory
Shift One Bit Right (Memory or Accumulltorl
NOP No Operation
ORA "OR" Memory with Accumulator
PHA
PHP
PlA
PlP
Push Accumulltor on Steck
Push Proceuor StatuI on Steck
Pull Accumulator from Stack
Pull Proceaor Status from Steck
ROL
ROR
RTI
RTS
Rotate One Bit left IMemory or Accumulatorl
Rotate One Bit Right (Memory or Accumulatorl
Return from Interrupt
Return from Subroutine
SBC
SEC
SED
SEI
STA
STX
STY
Subtract Memory from Accumulator with Borrow
Set Carry FIlii
Set Decimal Mode
Set Int,rNpt Disable StatUI
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
TAX
TAY
TSX
TXA
TXS
TYA
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Accumulator to Index X
Accumulator to Index Y
Stack Pointer to Index X
Index X to Accumulator
Index X to Stack Regilter
Index Y to Accumulator
vss
ROV
. , (OUT)
iiiQ
N.C.
NMi
REs
.2 (OUT)
S.D.
. 0 liN)
N.C.
N.C.
SYNC
VCC
AO
RiW
A1
02
03
04
A2
A3
A4
FUN,. of R&502
•
•
•
00
01
A6
A7
OS
06
07
A1S
A8
A14
A9
A10
A13
A12
A11
VSS
AS
R6502 - 40 Pin P.cbge
•
•
•
•
(
6SK Addressable Bytes of Memory CAO-A151
IRQ Interrupt
On·the
3
I~
3 2
I'
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2
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3
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IIlIANCH Otli C
= 0 ,2,
10
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I"ANCM ON C :; 1 '2,
10
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'0
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= 0 ,2'
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=,
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JUMP TO NEW lOC
JUMPSUB
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ADO 1 TO PIlI IF' BRANCH OCCURS TO SA~E PAGE
A002TO N IF 8RANCH OCCURS TO DIFFERENl PAGE
,3,
CARRy NOl :: BORROW
II,
IF IN DEcn~AL MODE Z F LAC. IS INVALID
ACCUMULA TOA MUS' BE CHECKED FOR ZERO RESUL 1
I
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ACCUMULATOR
MEMORV PER£FF£CTIVE ADDRESS
"'EMORY PER SlACK POINTER
·-
ADO
SUITA.CT
•V
.ND
OA
•
UCLUSlvE~
Tv A
M·
"EMORVll' 7
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MEMORV IIT6
n
•
NO CYCLES
NO BTTES
Timing for Reading Date from Memory or Peripherals
Clock Timing - R6502, 03, 04, 05, 06, 07
--j toe-- TR.O
·olINI ~-""-H-"'''''---~!!"
1.SV --\.. . . . . ;:"".:'"'-:. . .
--1
r-TF.O
I---rn
::.l..
"'OL
PWH.OH--l
-------', I-- --l '\
O.4~"'"L1._SV____O.4_V-1l'~ ':::2
PWH"j
·210UTI
RNi
=\. _______.J/
. 1 1 0 U T I ! = UV
~
REF "A"
REF
=t-
ADDRESS FROM
CPU
DATAFROM_~
"a"
2.0V
+-___-r___
____
~
MEMORY
RDY.S.O.
SYNC
Timing for Writing Data to Memory or Peripherals
Clock Timing - R6512, 13, 14, 15
r-REF"A"
,.-------T
...
CYC
------~
Rfij
.,
(
ADDRESS FROM
CPU
-r___
DATAFROM __- ;_________
~
CPU
REF "8"
Not.: "REF." muns Ref••nee Points on clocks.
PROGRAMMING MODEL
15
I
I7
A
I7
Y
(
X
A
I INDEX REGISTER
Y
0
IINDEX REGISTER
X
0
I
PCl
I
S
8 7
11
I ACCUMULATOR
0
7
PCH
7
0
7
INlvl
o
IBJDJIjZJCJp ROCESSOR STATUS REG 'P"
L
CARRY
' - - - ZERO
1· TRUE
1· RESULT ZERO
IPAOGRAM COUNTER "PC"
IRQ DISABLE
I STACK POINTER
DECIMAL MODE
1 - TRUE
BRK COMMAND
1 • BRK
1 • DISABLE
0
"s"
OVERFLOW
1· TRUE
NEGATIVE
1· NEG.
REGISTER SECTION
AD
tll
r-
....
..... r - -
CONTROL SECTION - - - I.....
INDEX
"EGISTE"
~
INTE""UPT
LOGIC
Y
11.2
11.3
11.4
.....
.....
.....
INDEX
"EGISTER
X
~
STACK
POINT
REGISTER
E
"-
"DY
ABL
-
~H
z
11.5 4 -
Ali
I
J
Al 4 -
(5)
a:
w
INSTRUCTION
DECODE
~
.....
Z
-I.!'rw
ALU
~
A1 4 - 1 . ADDRESS
BUS
All
"9
AID
A',
:z:
4-r--
0
....
c
ACCUMU~ATOR
oJ
A
C
Z
~
w
.,
·2
t+- fI, liN)
!
~
PC~
....
~
~
PCH
IC=
INPUT
DATA
LATCH
(OLI
~
A,3 4 -
...
....
4-L--
I
DATA BUS
BUFFER
PROCESSOR
STATUS
REGISTER
p
J
L...
1:::
t'
l
....
t t.
1
DO
01
02
11 .
03
B BIT LINE
04
05
I
Not.
,
2.
--
INSTRUCTION
REGISTER
Dli
• 1 BIT LINE
01
Clock G.n,r.l0r il not included on "6512, 13. '., '5
Addr.".". Capability and control option, va'y with Nth
Of 'hi R6S00 Productl.
RS500 Internal Architecture
DATA
BUS
}
R6512. 13. ' •• 111
fl2 11N )
CLOCK
GENERATOR
~
L0-
LEGEND
~H
-
A12 4 -
A'S
TIMING
CONTRO~
r-
~
ABH
A'.
~
a:
....
r-r--
.---
DBE
(:
(
(
PART NUMBER
DOCUMENT NO. 29000 047
REVISION 1. OCT. 1978
R6522
R6500 Microcomputer System
DATA SHEET
VERSATILE INTERFACE ADAPTER (VIA)
SYSTEM ABSTRACT
FEATURES
The 8·blt R6500 microcomputer system II produced with N·
channel. SllIcon·gate, depleiton·loild technology.
Its perform.
ance speeds are enhanced by advanced system architecture.
Its mnovatlVI' architecture results in smaller chips - Ihe semi·
conductor threshold 10 cost·effectivlty. System cost·effectivity
is further enhanced bv provldl.ng 8 family of 10 software-com·
pa"ble microprocessor (CPU) devices, memory and 110 devices. , ,
as well as low-cost deSIgn aids and documentation.
•
Organized for simplified software control of many functions
•
Compatible with the R650X and R6S1 X family of micro·
processors ICPUs)
•
Bi-directional. 8·bit data bus for communication with micro·
processor
•
Two Bi-directional.8-bit input/output ports for interfllCe with
peripheral devices'
OESCR IPTION
•
CMOS and TTL compatible input/output peripheral ports
The R6522 VIA adds two powerful, fle.ible Interval Timers.
a serlal-to·parallel/parallel·to·serlal shift register and input latch·
ing on the peflpheral porlS to the capabilities of the R6520
Peripheral Interface Adapter (PIA) device. Handshaking capa'
b,llty IS expanded to allow control of bl~irectional data trans·
fers between VIAs In multiple processor systems and between
peripherals.
•
Oata Olrection Registers allow each peripheral pin to act
either an input or an output
•
fnterrupt Flag Register allows the microprocessor to readily
determine the source of an interrupt and provides convenient
control of the interrupts within the chip
•
Handshake control logic for input/output peripheral data
transfer operations
Control of peripherals IS primarilv through two 80bit bidirectional
ports. Each of these ports can be programmed to aetas an input
or an output. Peripheral I/O lines can be selectively controlled
by the Interval Timers to generate programmable-frequency IQuare
waves and/or to count ell1ernallv generated pulses. Positive control of VIA functions is gained through its internal register organization: Interrupt Flag Register. Interrupt Enable Register. and
two Function Control Registers.
•
Oata latching on peripheral input/output ports
•
Two fullV'programmable interval timers/counters
•
Eight-bit Shift Register for serial interface
•
Forty.pin plastic or ceramic OlP package.
liS
Ordering Information
Order
Number
Package
Type
Frequency
Temperature
Range
R6522P
R6522AP
R6522C
R6522AC
R6522PE
R6522APE
R6522CE
R6522ACE
R6522CMT
PlastiC
PlastiC
Ceramic
Ceramic
PlastiC
PlastiC
Ceramic
Ceramic
CeramiC
1 MHz
2MHz
1 MHz
2MHz
1 MHz
2MHz
1 MHz
2 MHz
1 MHz
OOC to +700 C
OOC to +70 0 C
OOC to +70 0 C
OOC to +70 0 C
40 0 C to +85 0 C
40 0 C to +85 0 C
40~C to +85~C
40 C to +85 ~
_55°C to +125 C
RIIT
DAtA IU~
TO
6:.00
CPU
CONTROL
ROW
112 (lOCt:
Rf C,I S1fR AND
CHIP SHE(TS
R6522
IRQ
8 lIT
DATA PORT
CONTROL
Basic R6522 Interface Diagram
@
Rockwell In........ ,on,1 Co< ""'ilion 1178
All Righu Rese, ..d
"',n.td ,n USA.
TO
PERIPHERALS
VSS
PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
CBl
CB2
VCC
CAl
CA2
RSO
RSI
AS2
RS3
REs
~O
01
02
03
04
05'
06
07
.2
CSt
Cs2
R/W
iFi'Ci
Pin Configuration
\
Speclflcatlonl ,ublect to
chen.. wlthou, notice
:z
G
U
""<
"
::I
U
):
-r"'
n
-
:2
OPERATION SUMMARY
Register Select Lines (RIO. RS'. RS2. RS3)
The four Register select lines are ncrmally connected to the processor address bus lines to allow the processor to select the internal R6522
register which is to be accessed .. The sixteen possible combinations access the registers as follows:
Rag....
Remarb
RS3
RS2
RS'
RIO
L
L
L
L
ORB
L
L
L
H
ORA
L
L
H
L
DDAB
L
L
H
H
DDAA
L
H
L
L
T1L·L
T1C·L
Write Latch
Aead Counter
T1C·H
Trigger Tl L·LlT1C·L
Transfer
H
L
H
L
,
Controls Handshake
L
H
H
L
T1L·L
L
H
H
H
Tl L·H
RU
RS2
RS'
RSO
R ......
H
L
L
L
T2L-L
T2C-L
Write Latch
Reed Counter
H
L
L
H
T2C·H
Triggers T2L-L/T2C·L
Transfer
H
L
H
H
L
H
H
ACR
H
H
L
L
PCA
H
H
L
H
IFA
H
H
H
L
lEA
H
H
H
H
OAA
Remarb
(
SA
No Effect on
Handshake
NOle: L" O.4V DC. H ,. 2.4V DC.
Timer 2 Control
RS3
RS2
RS'
RSO
RIW- L
H
L
L
L
Write T2L·L
Aead T2C-L
Clear Interrupt flag
H
L
L
H
Write T2C·H
Transfer T2L·L to T2C·L
Clear Interrupt flag
Aead T2C·H
R/W-H
(
Writing the Timer' Register
The operat;ons which take place when writing to each of the four Tl addresses are as follows:
RS3
RS2
RS'
RSO
L
H
L
L
Write into low order latch
L
H
L
H
Write into high order latch
Write into high order counter
Transfer low order latch into low order counter
Reset Tl interrupt flag
L
H
H
L
Write low order latch
H
Write high order latch
Aeset Tl interrupt flag
X
I
H
H
Operation (R/w • LI
Reading the Timer 1 Registers
For readIng the T,mer 1 registers. the four addresses relate directly to the four registers as follows;
RS3
RS2
RSl
RSO
Operation (RIW • HI
L
H
L
L
Read Tl low order counter
Reset T 1 interrupt flag
L
H
L
H
Aead T1 high order counter
L
H
H
L
Read Tl low order latch
L
H
H
H
Read Tl high order latch
(
TIMING CHARACTERISTICS
Read Timing Characteristics (lo.ding 130 pF and one TTL 1oMI)
Symbol
Min
Typ
T ACR
180
Del.y time, clock positive transition to d.tI valid on bus
TCDR
-
Peripher.1 data setup time
TpCR
300
-
Dati bus hold time
THR
10
Rise and fall time for clock input
T RC
-
Per_....
Del.y tim•• .cIdr.SI v.lid
10
clock positive tr.nsition
-
....
Unh
-
nS
395
nS
-
nS
-
nS
25
nS
TRF
PHASE TWO
CLOCK
k-~~--~--+---~-------------~4V
ADDRESS
----~~--+_--;----r-------------------OAV
PERIPHERAL
DATA
~~~~---+---+------------------~V
T
DAV
r---""I- - _H.!' ________ ~V
DATA BUS
- - - - - --DAV
Read Timing Characteristics
Write Timing Characteristics
P.rameter
Symbol
Min
Typ
Enable pulse width
TC
0.47
Delay time, address valid to clock pOSitive transition
T ACW
180
-
Delay time, data valid to clock negative transition
T DCW
300
-
Delay time, read/write negative transition to clock positive
transition
TWCW
180
-
Data bus hold lime
T HW
10
Delav time, Enable negatIve transition to peripheral data valid
TCpw
-
Delay tIme, clock negative transition to peripheral data valid
CMOS (VCC . 30%)
T CMOS
-
-
PHASE TWO
CLOCK
,..------------ ~4V
ADDRESS
_.....:;=.;,
1::::r--__
---,::~~~~t:====~:~4V
1
CMOS
UV
TDCW+--~
-O.4V
READ/WRITE
DATA BUS
- - - - - - - - - O.4V
- - - - - - - - -VCC
-----------_ Jr'--------Z.4V
PERIPHERAL
DATA
Write Timing Characteristics
Max
Unit
25
,.S
-
nS
nS
-
nS
1.0
,..S
2.0
,..S
nS
I/O Timing Characteristics
Symbol
ChwllCte,iI1ic
Min
Typ
-
••
Unit
1.0
flS
1.0
liS
R.se and tall time lor CAl, C8l, CA2 and C82 ,nput sign.ls
TRF
Delay t.me, clock negative transition to CA2 negative
transItion (read handshake or pulse model
TCA2
-
Delay tIme, clock negatove Iransition to CA2 positive
Iransltoon (pulse model
T RSl
-
-
1.0
liS
Delay tIme. CA 1 aCllve tranSItIon
(handshake model
T RS2
-
-
2.0
liS
Delav tIme, clock posItIve Iransltlon to CA2 or C82 negative
transitIon (wrole handshake)
TWHS
-
-
1.0
,.,S
Delav lIme, peripheral data valid to C82 negalive transition
T DC
0
-
1.5
liS
Delay lIme. clock poSItive tranSItion to CA2 or CB2 positive
IranSlllon (pulse model
T RS3
-
-
1.0
115
Delav lIme, CBl actIve transition to CA2 or C82 positive
transItIon (handshake model
T RS4
-
-
2.0
115
Delay lIme. peripheral data valId
transItIon (Inpul latch,ng)
TIL
300
-
-
ns
Delay tIme CB 1 negallve transilion. to CB2 dala valid
(,"Iernal SR clock, shIft oull
TSRl
-
-
300
ns
Delav lIme, negallve transItIon of CBl input clock to CB2 data
valid (external clock, shift out)
TSR2
-
-
300
ns
Delav tIme, CB2 dala lIalid to positive transition of CBl clock
Ishlfl In, internal or external clock)
TSR3
-
-
300
ns
Pulse WIdth - PBG Input Pulse
T IPW
2
T ICW
2
-
,.,S
Pulse WIdth - CB 1 Input Clock
Pulse Spacing - PBG Input Pulse
liPS
2
-
,.,S
Pulse Spacing - CB 1 Input Pulse
IICS
2
-
-
"s
10
10
CA2 positive transilion
CAlor CBl ac;tive
PB6 INPUT PULSE
COUNTING MODE
C T'PW=:1___
C82SERIAL
DATA IN
T ICW
~
(
(
,."
2.4V
- - - -O.4V
~.4V
2.4V
CB1CLOCK
TSR2
2.4V
CB2SERIAL
DATA OUT
O.4V
I/O Timing Characteristics
(
Timer 1 Operating Modes
Two bits are proliided in the Auxiliary Control Aegister to allow selection of the Tl operating modes. These bits and the four possible modes
are as follows:
ACR7
Output
Enable
ACR6
"FrH·Run"
Enable
0
0
Mode
Generate a single time-out interrupt each time T1 is loaded
0
1
Generatll continuous interrupts
1
0
Generate a single interrupt and an output pulse on PB7 for
each Tl load operation
1
1
Generate continuous interrupts and a square walle output
on PB7
FUNCTION CONTROL
Control of the lIarious functions and operating modes within the A6522 is accomplished primarily through two registers, the Peripheral Control Register (PCRI, and the Auxiliary Control Register (ACRI. The PCR IS used primarily to select the operating mode for the four peripheral
control pins. The Auxiliary Control Register selects the operating mode for the Interllal Timers (Tl, T21. and the Serial Port (SRI.
Peripher.' Control Register
The Peripheral Control Register is organized as follows:
Bit fI
7
I
I
6
CB2 Control
Function
5
4
CB1
Control
3
I
2
I
CA2 Control
1
0
CAl
Control
Typical functions are shown below:
PCR3
PCR2
PCR1
Mod.
0
0
0
Input mode - Set CA2 interrupt flag !lFRO) on a negative transition of the input Signal. Clear
I FRO on a read or write of the Peripheral A Output Register.
0
0
1
Independent interrupt input mode - Set IFRO on a negative transition of the CA2 input signal. Reading or writing ORA does not clear the CA2 interrupt flag.
0
1
0
Input mode - Set CA2 interrupt flag on a positille transition of the CA2 input signal. Clear
IFRO with a read or write of the Peripheral A Output Register.
0
1
1
Independent interrupt input mode - Set I FRO on a posltille transition of the CA2 input signal. Reading or writing ORA does not clear the CA2 interrupt flag.
1
0
0
Handshake output mode - Set CA2 output Iowan a read or write of the Peripheral A Output
Register. Reset CA2 high with an active tranSition on CA1.
1
0
1
Pulse output mode - CA2 goes low for one cycle following a read or write of the Peripheral
A Output Register.
1
1
0
Manual output mode - The CA2 output IS held low in this mode.
1
1
1
Manual output mode - The CA2 output is held high in this mode.
Auxili-v Control Register
Many of. the functions in the Auxiliary Control Register have been discussed previously. However, a lUl!'lmary of this register is presented
here as a conven.ient reference for the R6522 user. The Auxiliary Control Register is organized. follows:
7
Bit'
Function
I
T1 Control
4
5
6
T2
Control
I
3
1
2
Shift Register Control
1
0
PB
Latch
Enlble
PA
Latch
Enable
(
Shift Registar Control
The Shift Register operating mode is selected a. follows:
ACR4
ACR3
ACR2
0
0
0
Shift Register Disabled.
0
0
1
Shift in under control of Timer 2.
0
1
0
Shift in under control of system clock.
0
1
1
Shift in under control of external clock pulses.
1
0
0
Free-running output at rate determined by Timer 2.
1
0
1
Shift out under control of Timer 2.
1
1
0
Shift out under control of the system Clock.
1
1
1
Shih out under control of external clock pulses.
Mode
(
T2 Control
Timer 2 operates in two modes. If ACR5 "0, T2 acts as an interval timer in the one-shot mode. If ACR5 • 1, Timer 2 acts to count a predetermined number of pulses on pin PB6.
(
PAATNUIIBER
A8545-1
R6500 Microcomputer System
DATA SHEET
CRT CONTROLLER (CRTC)
DESCRIPTION
FEATURES
The R6545-1 CRT Controller (CRTC) Is designed to interface
an 8-b1t microprocessor to CRT raster scan video displays.
and adds an advanced CRT controller to the established and
expanding line of R6500 products.
• Compatible with 8-bit microprocessors
• Up to 2.5 MHz character Clock operation
• Refresh RAM may be configured In row/column or atraIght
binary addressing
• Alphanumeric and limited graphics capability
• Up and down scrolling by page. line. or character
• Programmable Vertical Sync Width
• Fully programmable display (rows. columns. character
matrix)
The R6545-1 provides refresh memory addresses and character generator raw addresses which allow up to 16K characters with 32 scan lines per character to be addressed. A
major advantage of the R6545-1 is that the refresh memory
may be addressed in either straight binary or by raw/column.
Other functions in the R6545-1 include an intemal cursor regIster which generates a cursor output when its contents are
equal to the current refresh address. Programmable cursor
start and end registers allow a cursor of up to the full character scan In height to be placed on any scan lines of the
character. Variable cursor display blink rates are provided.
A light pen strobe input allows capture of the current refresh
address in an internal light pen register. The refresh address
Hnes are configured to provide drect dynamic memory refresh.
All timing for the video refresh memory signals is derived
from the character clock input. Shift register. latch. and multiplex control signals (when needed) are provided by external
high-speed timing. The mode control register allows noninterlaced video display modes at 50 or 60 Hz refresh rate.
The internal status register may be used to monitor the
R6545-1 operation. The RES input allows the CRTC-generated field rate to be dynamically-synchronized with line frequency Jitter.
ORDERING INFORMATION
Pert
Package
Number
Type
R6545-1P
R6545-1AP
R6545-1C
R6545-1AC
Plastic
Plastic
Ceramic
Ceramic
• AackweIIlrMmIIIkInII Corpordon 1880
Temperature
Frequency
1 MHz
2 MHz
1 MHz
2 MHz
Range
O°C to
Ooc to
O°C to
O°C to
+70°C
+700C
+700C
+70°C
•
•
•
•
•
•
•
•
•
•
Non-interlaced scan
50/60 Hz operation
Fully programmable cursor
Light pen register
Addresses refresh RAM to 16K characters
No external DMA required
Internal status register
4Q-Pin ceramic or plastic DIP
Pin-compatible with MC6845
Single +5 ±5% Volt Power Supply
vss
m
LPEN
CCO/MAO
CC1/MA1
CCZ/MA2
CC3/MA3
CotIMA4
CCIS/MAIS
CC8/MA8
CC7/MA7
CRO/MAS
CRt/MAg
CR2/MAtO
CR3/MAt1
CR4/MA12
CRIS/MA13
DISPLAV ENABLE
CURSOR
VCC
VSVNC
HaVNe
RAO
RA1
RA2
'RA3
RA4
DO
Dt
D2
D3
D4
DIS
DI
D7
5
R8
.2
FVW
CCLK
R8545-1 Pin Configuration
AlIRIgIa~
SpecIICIIb. MjlclIO
cIw1ge wIhauI ~
Printed In U.S.A.
Doau........... D17
D.a....
t_
INTERFACE SIGNAL DESCRIPTION
CPU INTERFACE
~ (PhD. 2 Clock)
The input clock is the system Phase 2 (;2) clock and is used
to trigger all data transfers between the system processor (CPU)
and the R6545-1. Since there is no maximum limit to the allowable
clock time, it Is not necessary for it to be a continuous
clock. This capability permits the R6545-1 to be easily interfaced
to noo-6500 compatible microprocessors..
;2
R/'R (Read/Write)
The R/W input signal generated by the processor is usen to
control the direction of data transfers. A high on the R/W pin
allows the processor to read the data supplied by the R6545-1,
a low on the R/W pin allows data on data lines 00-07 to be
written into the R6~5·1.
CI (Chip Select)
The Chip Select input is normally connected to the processor
address bus either directly or through a decoder. The R6545-1
is selected when OS is low.
CURSOR (Cursor Coincidence)
The CURSOR Signal is an activ~hlgh output used to indicate
when the scan coincides with the programmed cursor position.
The cursor position may be programmed to be any· character
()
in the address field. Furthermore, within thechar8cter,the cursor may be programmed to be any block of scan lines;'slnce
the start scan line and the end scan line are both programmable.
The cursor position may be delayed by one character time by
setting Bit 5 of RB to A "1".
LPEN (Light Pen Strobe)
The LPEN signal is an edge-sensitive input used to load the
internal Ught Pen Register with the contents of the Refresh
Scan Counter at the time the active edge occurs. The actiVe
edge of LPEN is the low-to-high transition.
CCLK (Clock)
The CCLK signal is the character timing clock input and Is used
as the time base for all internal count/control functions.
An
The Register Select input is used to access internal registers.
A low on this pin permits writes (R/W = low) into the Address
Register and reads (R/W = high) from the Status Register. The
contents of the Address Register is the identity of the register
accessed when RS is high.
The ~ signal is an active-low input used to initialize all internal scan counter circuits. When RES is low, all internal
counters are stopped and cleared, all scan and video outputs
are low, and control registers are unaffected.
must stay
low for at ,least one CCLK period. All scan timing is initiated
when
goes high. In this way,
can be used to synchronize display frame timing with line frequency.1!i!§ may also
be used to synchronize multiple CRTC's in horizontal and/or
vertical split screen operati6n.
(
DO-D7 (Data Bus)
REFRESH RAM AND CHARACTER ROM INTERFACE
00-07 are the eight data lines used to transfer data between
the processor and the R6545-1. These lines are bidirectional
and are normally high-impedance except during read cycles
when the chip is selected (~ = low).
MAo-MA13 (Refresh RAM Address Lines)
RS (Register Select)
VIDEO INTERFACE
HSYNC (Horizontal Sync)
The HSYNC signal is an active-high output used to determine
the horizontal position of displayed text. It may drive a CRT
monitor directly or may be used for composite video generation.
HSYNC time position and width are fully programmable.
VSYNC (Vertical Sync)
The VSYNC signal is an active high output used to determine
the vertical position of displayed text. Like HSYNC, VSYNC may
be used to drive a CRT monitor or composite video generation
circuits. VSYNC time position and width are both programmable.
DISPLAY ENABLE (Display Enable)
The OISPLAY ENABLE signal is an active-high output used to
indicate when the R6545-1 is generating active display information. The number of horizontal display characters per row
and the number of vertical display rows are both fully programmable and together are used to generate the OISPLAY ENABLE
signal. OISPLAY ENABLE can be delayed one character time
by setting bit 4 of RS equal to 1.
m
m
m
These 14 signals are active-high outputs used to address the
Refresh RAM for character storage and display operations. The
starting scan address is fully programmable and the ending
scan address is determined by the total number of characters
displayed, which is also programmable, in terms of charactersl
line and lines/frame.
There are two selectable address modes for MAO-MA13:
In the straight binary mode (RB, Mode Control, bit 2 = "a"),
characters are stored in successive memory locations. Thus,
the software must be designed such that row and column character coordinates are translated into sequentially-numbered addresses. In the row/column mode (RB, Mode Control, bit 2 =
"1 "), MAO-MA7 become column addresses CCO-CC7 and MASMA 13. become row addresses CRO-CR5. In this case, the software can manipulate characters in terms of row and column locations, but additional address compression circuits are needed
to convert the CCO-CC7 and CRO-CR5 addresses into a m.,mory-efficient binary address scheme.
RAo-RA4 (Raster Addre•• Lines)
These 5 signals are active-high outputs used to select each raster scan within an individual character row. The number of raster
scan lines is programmable and determines the character height,
including spaces between character rows.
.
()
INTERNAL REGISTER ORGANIZATION
Aeed
Addr_ RII"r
a
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AS
4 3 2 1 0
X
0
0
1
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
,
1
1
1
,,
,,
,
,,
1
1
1
1
1
1
,
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
X
X
X
0
0
0
0
X
X
X
0
0
1
X
X
X
0
,
,, , ,
,, , ,
0
0
0
0
1
1
,
1
0
0
0
1
0 0
0
0
1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0
,
Aeg.
No.
X
X
X
RO
R1
R2
R3
R4
R5
R6
R7
RS
R9
R10
R11
R12
R13
R14
R15
R'6
R17
Allister Neme
Address Register
Status Register
Horizontal Total Char
Horizontal Displayed Char
Horizontal Sync Position
YSYNC, HSYNC Widths
Vertical Total Rows
Vertical Total Adjust lines
Vertical Displayed Rows
V\!rtical Sync Position
Mode Control
Scan line
Cursor Start line
Cursor End Line
Display Start Address (HI
Display Start Address (L1
Cursor Position Addrass (HI
Cursor Position Address (L1
light Pan Register (HI
Light Pen Register (LI
Allister Units
Register No.
Wrltlt
(AJW·
(A/W.
Highl
Lowl
V VV
V
V
No. of Characters/Row
No. of Characters/Row
Character Position
No. of Scan lines, .characters
No. of Character Rows
No. of Scan lines
No. of Character Rows
No. of Character Rows
V
V
V
-
V
V
V
V
V
V".
-
V
V
V
-
5
5
5
5
5
V V V
4
V II 5 4
V'" V 1/ 4
V
V
V
V
-
4 3 2 1 0
V ./ 6 4
7 6 5 4
V
V l/ 5
V
7 6 6 4
:/ V 6 4
7 6 5 4
V
,,
,,
,,
,,
,
5V ./ ../ /
8
8
6
6
6
6
4
4
4
4
4
../
L / / 4
/' 6 5 4
L 6 6 4
7 6 6 4
7
7
7
7
V
No. of Scan Lines
Scan Line No.
Scan line No.
-
7 6 & 4 3 2 1 0
V V ~ ~ VV V
V
_..
A. . . . Bit
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
,
1
1
1
0
0
0
0
0
0
0
0
0
0
O.
0
0
0
0
0
0
0
Table 1. Overall Register Structure and Addressing
UND
-
CPU I/F
STATUS REGISTER (SR)
VIDEO I/F
~D7~~~~------~~~~HSVNC
1--4I~ VSVNC
DISPLA V ENABLE
~2--e...
CUASOR
LPEN
RNi ---t..
Ci---t..
RS -
.....~--....,...,J
This 8-bit register contains the status of the CRTC. Only two
bits are assigned, as follows:
CCLK
RES
'"----.v...----'
- - - - N O T USED
L.I
MAO.MA13
RAO-AA4
REFRESH AAM AND CHARACTER ROM
Vert.1 A.T.... (VATI
.
o - Saln II not .....-ty iii Ito .....1 _
time.
1 - Saln 10 ......ntly In Ito ....icII ..._
tllM.
N_ "'-' thit bit .......Iy . - to • H1 U . . . . . . . . . . . . . . .
but . - to • T
fiwo ~ clOck
t i _ ....0,. ....iCeI ......10 "'-' orit-.l
tim..... for
RAM .....ionI _ _ idld.
R6545·1 Interface Diagram
...t,_ - .
Nf'"
' - - - - LPEN A.....' Full (LAFI
o • A. . . .'A1.o'A17h............ bythlCPU.
INTERNAL REGISTER DESCRIPTION
ADDRESS REGISTER
This S-bit write-only register is used as a "pointer" to direct
CRTC/CPU data transfers within the CRTC. Its contents is the
number of the desired register (0-17). When CS and RS are low,
then this register may be loaded; when CS is low and RS is
high, then the register selected is the one whose identity is
stored in this address register.
In"
1 -
LPEN stroM hi. ......
_ .....
' - - - - - - No! Ueed
NOTE:
The StltUI Regine, tlk" the State.
I-I 0 11 1-1-1 -I -1-1
immedilt.ly afte, _ , IVeel tu,n""n.
R~HORaONTALTOTALCHARACTERS
R7-VERTlCAl SYNC POSlnON
This 8-bit write-only register contains the total of displayed and
non-displayed characters, minus one, per horizontal line. The
treq!'!9!'!C}'-ott-!S'tNC-!s-th!..!s-determinedbyt!'!!s-register.
This 7-bit write-only register is used to select the character row (
time at which the vertical SYNC pulse is desired to occur and, . .
thu$,.ls-used-toposiOOn-t!'!e-displayea-text-ln-the·vertical dll'GCtion.
R1-HORIZONTAL DISPLAYED CHARACTERS
RI-MODE CONTROL (MC)
This 8-blt wrlte-only register contains the number of displayed
characters per horizontal line.
This 8-bit writ8-0nly register selects the operating modes of the
R6545-1. as follows:
.
R:i-HORIZONTAL SYNC POSmON
11
Me7
This 8-blt wrlte-only register contains the position of the horizontal SYNC on the horizontal line, in terms of the character
location number on the line. The position of the HSYNC determines the left to right location of the displayed text on the video
screen. In this way, the side margins are adjusted.
-
••
""" """
-
caK
3210
MC4 Me3 Me2 Me. MCO
D••
0
RAD
-
0
~
R3--HORIZONTAL AND VERTICAL SYNC WIDTHS
....... Pn>gram 10 "0"
NotUood
..._-.. ,
-
This 8-bit write-only register contains the widths of both HSYNC
and VSYNC, as follows:
,
)
AM Addl'Ollintl ModI fAA"1
or .., ..... ' binary
r Row/Column
---- ...........
,
II
'0
am to "0"
D_" no""",
ftIIbIt;
stlow (DESI
O· for
1 • to awtlllV Display EnebN OM dMlraetrW tilM.
C._Ilkew ICSKI
o ..
1
HSYNC Pulse Width
at
for
no
."v.
'D dobV Cut'Mf' ana ciwlrlM:1. ,ime!.
}~
The width of the horizontal Ivnc
pulse (HSYNC) in the number of
charllele, clock times (CCLK).
(
' - - - - - - - - - VSVNC Pulse Width
The width of the vertical .vnc
pulse (VSVNC) in the number of
IOCan lines. When bits 4·7 are
• " "0". VSYNC will be 16 ICin
lin.. wide,
Control of these parameters allows the R6545-1 to be interfaced
to a variety of CRT monitors, since the HSYNC and VSYNC
timing signals may be accommodated without the use of external one shot timing.
Rg.........ROW SCAN LINES
This 5-bit write-only register contains the number of scan lines,
minus one, per character row, including spacing .
R1~CURSOR START LINE
R11-CURSOR END LINE
These 5-bit write-only registers select the starting and ending
scan lines for the cursor. In addition, bits 5 and 6 of R10 are
used to select the cursor blink mode, as follows:
R4-VERTICAl TOTAL ROWS
Bit
Bit
The Vertical Total Register is a 7-bit register containing the total
number of character rows in a frame, minus one. This register,
along with R5, determines the overall frame rate, which should
be close to the line frequency to ensure flicker-free appearance.
If the frame time is adjusted to be longer than the period of the
line frequency, then RES may be used to provide absolute
synchronism.
...!.
..!...
Cursor Blink Mode
0
0
1
0
1
0
1
1
Display Cursor Continuously
Blank Cursor Continuously
Blink Cursor at 1/16 Field Rate
Blink Cursor at 1/32 Field Rate
RS-VERTICAl TOTAL liNE ADJUST
The Vertical Total Line Adjust Register (R5) is a 5-bit write-only
register containing the number of additional scan lines needed
to complete an entire frame scan and is intended as a fine adjustment for the video frame time.
R6-VERTICAl DISPLAYED ROWS
This 7·blt write-only register contains the number of displayed
character rows in each frame.
R12-DISPLAY START ADDRESS HIGH
R13-DISPLAY START ADDRESS lOW
These registers form a 14-bit register whose contents is the
memory address of the first character of the displayed scan (thfJ
character on the top left of the video display, as in Figure 1).
Subsequent memory addresses are generated by the R6545-1
as a result of CCLK input pulses. Scrolling of the display Is accomplished by changing R12 and R13 to the memory address
associated wit" the first character of the desired line of text to
be displayed first. Entire pages of text may be scrolled or
changed as well via R12 and R13.
(
..
NUMBER OF HORIZONTAL TOTAL CHARACTERS IROI
r~--------------------_A~-------------NUMBER OF HORIZONTAL DISPLAYED CHARACTERS IR11
__--__~,
r~--------------~A~--------------~,
START ADORED HIGH IR12,START ADDRED LOW IR131-
§
F=
NUMBER OF
VERTICAL
TOTAL
ROWS
IR41
a
~
\
NUMBER OF
VERTICAL
DISPLAV
ROWS
IRII
• N~R Of'
ICAN LIN
11111
!"-
\
CURIOII STAIIT LiNt Ilitli
--"
INO LINI 111111
POSITION ADDRED HIGH IR141
CURIOR POSITION ADDRED LOW IR111
HORIZONTAL
RETRACE,
PERIOD
INON-DISPLAVI
DISPLAV PERIOD
VERTICAL RETRACE PERIOD
INON-DISPLA VI
VERTICAl.
TOTAL
{
ADJUST IRIiI
Figure 1. Video Display Format
R14-CURSOR POSmOl4 HIGH
R15-CURSOR POsmON LOW
DESCRIPTION OF OPERATION
These registers form a 14-bit register whose contents Is the
memory address of the current cursor position. When the video
display scan, counter (MA lines) matches the contents of this
register. and when the scan line counter (RA lines) falls within
the bounds set by R10 and R11. then the CURSOR output becomes active. Bit 5 of the Mode Control Register (RS) may be
used to delay the CURSOR output by a full CCLK time to accommodate slow access memories.
VIDEO DISPLAY
R16-UGHT PEN HIGH
R17-UGHT PEN LOW
These registers form a 14-bit register whose contents is the light
pen strobe position. in terms of the video display address at
which the strobe occurred. When the LPEN input changes from
low to high. then. on the next negative-going edge of CCLK. the
contents of the internal scan counter is stored in registers R16
and R17.
REGISTER FORMATS
Register pairs R12/R13. R14/R15. and R16/R17 are formatted
In one of two ways:
(1) Straight binary. if register RS. bit 2 = "0".
(2) Row/Column. if register RS. bit 2 = "1". In this case the
low byte is the Character Column and the high byte is the
Character Row.
Figure 1 Indicates the relationship of the various program registers in the R6545-1 and the resultant video dllplay.
Non-displayed areas of the Video Display are used for horizontal and vertical retrace funclions of the CRT montor. The h0rizontal and vertical sync slgna/s. HSYNC and VSYNC. are pr0grammed to occur during these intervals and are used to trigger
the retrace in the CRT monitor. The pulse widths are C0nstrained by the monitor requirements. The time position of the
pulses may be adjusted to vary the display margins (left, right,
top. and bottom). '
REFRESH RAM ADDRESSING
Shared Memory Mode (RI, bit 3 = "0")
In this mode. the Refresh RAM address lines (MAO-MA13) dlrectly reflect the contents of the internal refresh scan character
counter. Multiplex control. to permit addressing and aeIectIon of
the RAM by both the CPU and the CATC, must be provided
external to the CRTC. In the Row/Column addl'88l mode. linea
MAQ-MA7 become character column addresses (CCO-CC7) and
MA8-MA13 become character row addresses (CRO-CR5).
ADDRESSING'MODES
BIts 5 and 61n the Cursor Start Une High Regiller (R10) control (
the CUI'8Of' dIIpIay and bInk ..... as foIowa:
Row/Column
In this mode, the CRTC add,... lines (MAQ-MA13) are generated 18 8 column (MAO-MA7) and 6 raw (MA8-MA13) addreI8I8. Extra hardware II needed to comprees thll addl'888lng
Into a straight binary sequence In order to COI'188IV8 memory in
the refreIh RAM.
Bit 8
Bit I
au.., Opeqtlnt . . . .
0
0
1
1
0
1
0
1
Diiplev CUl10r Continuoully
Blenk CUI'IOI' Continuoully
Blink Cunar et 1/18 Field Rete
Blink CUrIOr et 1/32 Field Rete
....ry
In this mode, the CRTC addl'8S8 lines are straight binary and
no compr888iOn circuits are needed. However, software c0mplexity 18 Increased since the CRT characters cannot be stored
In tenns of their raw and column locations, but must be
sequential.
USE OF DYNA.C RAM FOR REFRESH MEMORY
The R8545-1 permits the use of dynamic RAMS 18 storage devIce8 for the Refresh RAM by continuing to Increment memory
addl'88888 In the non-dlsplay Intervals of the scan. This is 8 viable technique, since the DIapIay Enable signal controls the
actual video display blanking. Figure 2 Illustrates Refresh RAM
addresalng for the cue of binary addressing for 80 columns and
24 raws with 10 non-dlsplayed columns and 10 non-dlsplayed
raws.
The cursor of Up to 32 ci'laraeters In height can be d~ on
and between the scan lines 18 loaded Into the Cursor Start Une
(R10) and Cursor End Une (R11) RegiIter8.
The cursor is positioned on the screen by loading the Cursor
Position Address High (R14) and Cursor PoaI1Ion Addresa Low
(R15) registers with the desired refresh RAM add..... The cursor can be positioned in any of the 18K character positions.
Hardware paging and data scrolling Is thus allowed without loss
of cursor position. Figure 3 is an example of the display cursor
scan line.
UNDERLINE
OVER LINE
CURSOR
CURSOR
BOX
CURSOR
o
0
O~~~~~
2
3
2
3
2
3
TOTAL -10
.
DISPLAY -10
,
0
1
2
3
76
83
156
H
78
79
80
81
161
89
169
80
81
82
157
158
158
160
160
161
162
237
2,38
239
240
249
240
241
242
317
318
319
320
329
1680 1681
1682
1757 1758 1758 1780
1789
1649
1780 1761
1762
1837 1838 1839 1840
1840 1641
1642
1917 1918 1919 1920
1929
1820 1921
1922
1997 1998 1999 2000
2009
2000 2001 2002
2077 2078 2079 2080
2089
2640 2641 2642
2717 2718 2720
2729
"8115
"6iii1
"
' .
15
IS
(l
7 7 7
8
8
8
9
9
10
11
1011
9
10:1+~~:t:
11
CURSOR START
LINE - 9
CURSOR START
LINE - 1
CURSOR START
LINE· 1
CURSOR END
LlNE-9
CURSOR END
LINE - 1
CURSOR END
Figure 3.
LlNE-9
Cursor Display Scan Line Control Examples
Figure 2. Memory Addrlllin, Example (SO x 24)
CURSOR OPERAnON
A one character wide cursor can be controlled by storing values
Into the Cursor Start Una (R10) and Cursor End Una (R11) regIstirs and Into the Cursor Position Address High (R14) and Cursor Position Low (R15) registers.
()
MPU READ TIMING CHARACTERISTICS
(V cc = 5.0V ±5%. T A = 0 to' ?OoC. unless otherwisil noted)
1 MHz
Ch.rllCtllriltic
2 MHz
Min
M8x
TCYC
1.0
02 Pulse Width
TC
440
Address Set·Up Time
T ACR
180
Address Hold Time
Cycle Time
Symbol
Min
.M8x
-
0.5
-
200
ns
-
-
90
-
ns
-
Unit
lAS
TCAR
0
Rm Set·Up Time
TWCR
180
-
90
-
ns
Read Access Time
340
-
0
ns
TCDR
-
150
ns
Read Hold Time
THR
10
-
10
-
ns
Data 8us Active Time
(Invalid Data)
TCDA
40
-
40
-
ns
It, and tf ..
10 to 30 ns)
READ CYCLE
MEMORY AND VIDEO INTERFACE CHARACTERISnCS
(
(Vee· 5.0V ±.5%. Til.· 0 to loDe. unletl oth.rwi .. noted I
, MH.
Svmbol
Ch"H*istiCi
2MH.
Min
Mo.
Mi"
Mo.
«I
Char. Clock CYcle Tim.
TCCY
0.'
«I
0.'
Chlr. Clock Pulse Width
200
-
200
MAO-MA 13 Propag.tion OellY
TCCH
T MAO
300
RAO·RA4 Prop.gltion D.IIV
T RAO
DISPLAY ENABLE P,OP. O.lev
TOTO
T HSO
-
HVSNC Propagation D.IIY
-
VSYNC Prop-altion
TVSO
Cursor PrOP1911ion DeilY
TCOD
-
LPEN Strobe Width
T LPH
150
LPEN 10 CCLK DeilY
T LPI
20
CCLK to LPEN Delay
T LP2
0
300
450
450
450
-
-
450
-
-
160
300
300
. '450
450
450
450
-
20
0
Unite
.'.,
"'
"'
.,"'
n.
"'n.
n.
n.
t,.. tf • 20 n. {mlxl
SYSTEM TIMING DEFINITIONS
~------------TCCy------------~-i
2.0V
2.0V
CCLK
\\..---
SIGNAL'
(800 Belowl
•
(
SIGNAL
SYMBOL (XI
SIGNAL
MAO·MAI3
TMAO
RAO·RA4
T RAO
DISPLAY ENABLE
TOTO
HSYNC
T HSO
VSVNC
TvSO
CURSOR
TCOO
LIGHT PEN STROBE TIMING DEFINITIONS
CCLK
O.BV
I-----..J
LPEN
lEE NOTE
---Ill...___
MAQ.MA13 _ _ _ _
..,..JIl...___
"_+,_ _ _
"_+2_ _ _ [
NOTE:
SLASH AREA DEFINES THE ''WINDOW'' IN WHICH AN
LPEN POSITIVE EDGE WILL CAUSE ADDRESS N+2 TO
LOAO INTO LIGHT PEN REGISTER. TRANSITIONS ON
EITHER SIDE OF THIS "WINDOW" WILL RESULT IN
UNPREDICTABLE VALUES BEING LOADED INTO THE
LIGHT PEN REGISTER.
(
SPECIFICATIONS
Maximum Ratings
Symbol
Rating
Supply Voltage
Valul
VCC
V IN
Input Voltage
Operating Temperature Aange
TOp
TSTG
Storage Tem peratu re
Unit
-0.3 to +7.0
Vdc
-0.3 to +7.0
Vdc
o to +70
°c
°c
·55 to 150
All inputs contain protection circuitry to prevent damage due to high static discharges. Care should be taken to prevent unnecessary application of voltages in excess of the allowable limits.
Electrical Characteristics
(V CC
=
5.0V ±5%, T A = 0·70 o C, unless otherwise noted)
Symbol
Characteristic
Min
Max
Unit"
Vdc
Input High Voltage
V IH
2.0
Input Low Voltage
V IL
0.3
VCC
0.8
liN
-
2.5
~dc
ITSI
-
10.0
"Adc
V OH
2.4
-
Vde
VOL
-
0.4
Vdc
Po
-
1000
mW
CIN
-
10.0
pF
12.5
pF
10.0
pF
Input Leakage (02, AtW,
rn, ~, AS, LPEN, CCLK)
Vdc
Three-State Input Leakage (00-07)
(V IN
=
0.4 to 2.4V)
Output High Voltage
I LOAO = 205 "Adc (00-07)
ILOAD = 100 "Ade (all others)
Output Low Voltage
I LOAD = 1.6 mAde
Power Dissipation
Input Capacitance
02,ANV,RES.CS.AS.LPEN.CCLK
00-07
COUT
Output Capacitance
TEST LOAD
2.41<0
Fl8545-1 PIN
130pF
I
R
R-11Kn FOR 00-07
-24Kn FOR ALL OTHER OUTPUTS
(~
(
(/
CRT 5027
CRT 5037
OlI't'OO1letltkln so you keep ahead ofpn
CRT 5057*
. IL PC FAMILY
CRT Video Timer and Controller
VTAC®
tal
PIN CONFIGURATION
FEATURES
o Fully Programmable Display Format
Characters per data row (1-200)
Data rows perf.rame (1-64)
Raster scans per data row (1-16)
D Programmable Monitor Sync Format
Raster Scans/ Frame (256-1023)
"Front Porch"
Sync Width
"BackPorch"
Interlace/ Non-I nterlace
Vertical Blanking
Lock Line Input (CRT 5057)
o Direct Outputs to CRT Monitor
Horizontal Sync
Vertical Sync
Composite Sync (CRT 5027, CRT 5037)
Blanking
Cursor coincidence
o Programmed via:
Processor data bus
External PROM
Mask Option ROM
o Standard or Non-Standard CRT Monitor Compatible
Refresh Rate: 60Hz, 50Hz, ...
Scrolling
Single Line
Multi-Line
o Cursor Position Registers
o Character Format: 5x7, 7x9, ...
o Programmable Vertical Data Positioning
o Balanced Beam Current Interlace (CRT 5037)
o Graphics Compatible
A2
A3
CS
R3
R2
GNO
Rl
Rt!
os [
LLI/CSYN
VSYN
DCC
Voo
Va;
o
o
o
[
[
[
[
[
[
[
[
[
[
[
[
[
HSYN [
CRV [
BLC
OB7(
OB6 [
OB5 [
1
2
3
4
5
6
7
8
.....,
40
39
~ Al
At!
HfJ
37 ~ Hl
36 ~ H2
35 PH3
34 ~ H4
33 ~ H5
H6
32
10
31 PH7/0R5
90
11
30 P OR4
12
29 P OR3
13
28 POR2
14
27 PORl
15
26 PORf!
16
25 POBfII
24 POB1
17
18
23 POB2
19
22 0B3
20
21
OB4
38
PACKAGE: 4O-Pin D.I.P.
o Split-Screen Applications
o
o
o
o
o
o
o
Horizontal
Vertical
Interlace or Non-Interlace operation
TTL Compatibility
BUS Oriented
High Speed Operation
COPLAMOS® N-Channel Silicon
Gate Technology
Compatible with CRT 8002 VDACTM
Compatible with CRT 7004
GENERAL DESCRIPTION
The CRT Video Timer and Controller Chip (VTAC)@ is a user programmable40-pinCOPLAMOS@) nchannel MOS/LSI
device containing the logic functions required to generate all the timing signals for the presentation and formatting of
interlaced and non-interlaced video data on a standard or non-standard CRT monitor.
With the exception of the dot counter, which may be clocked at a video frequency above 25 MHz and therefore not
recommended for MOS implementation, all frame formatting, such as horizontal, vertical, and composite sync, characters
per data row, data rows per frame, and raster scans per data row and per frame are totally user programmable. Thedata row
counter has been designed to facilitate scrolling.
Programmi ng is effected by loading seven 8 bit control registers directly off an 8 bit bidirectional data bus. Four register
address lines and a chip select line provide complete microprocessor compatibility for program controlled set up. The device
can be "self loaded" via an external PROM tied on the data busasdescribed intheOPERATION section. Formatting canalso
be programmed by a single mask option.
In addition to the seven control registers two additional registers are provided to store the cursor character and data
row addresses for generation 01 the cursor video signal. The contents of these two registers can also be read out onto the
bus for update by the program.
Three versions of the VTAC@) are available. The CRT 5027 provides non-interlaced operation with an even or odd
number olscan lines per data row, or interlaced operation with an even number of scan lines per data row. The CRT 5037
may be programmed for an odd or even number of scan lines per data row in both interlaced and non-interlaced modes.
Programming the CRT 5037 for an odd number of scan lines per data row eliminates character distortion caused by the
uneven beam current normally associated with odd field/even field interlacing of alphanumeric displays.
The CRT 5057 provides the ability to lock a CRT's vertical refresh rate, as controlled by the VTAC'stli vertical sync
pulse, to the 50 Hz or 60 Hz line frequency thereby eliminating the so called "swim" phenomenon. This is particularly
well suited for European system requirements. The line frequency waveform. processed to conform to the VTAC's8
specified logic levels, is applied to the line lock input. The VTACtli will inhibit generation of vertical sync until a zero to
one transition on this input is detected. The vertical sync pulse is then initiated within one scan line after this transition
rises above the logic threshold of the VTAC.tII
To provide tne pin required for the line lock input, the composite sync output is not provided in the CRT 5057.
'FOR FUTURE RELEASE
121
Description of Pin Functions
PinNa.
25-18
Symbol
Name
DB~-7
Data Bus
OS
12
DCC
38-32
H¢-6
7,5,4
R1-3
I/O
Chip Select
Register
Address
Data Strobe
3
CS
39,40,1,2 A~-3
9
Inputl
Output
31
H7/DRS
DOT Counter
Carry
Character
Counter Outputs
Scan Counter
Outputs
H7/DRS
8
Rf6
Scan Counter LSB
0
26-30
DR0-4
0
17
15
11
10
BL
HSYN
VSYN
CSYNI
LLI
Data Row
Counter Outputs
Blank
Horizontal Sync
Vertical Sync
Composite Sync Outpull
Line Lock Input
CRV
Vee
Voo
Cursor Video
Power Supply
Power Supply
16
14
13
0
0
0
0
0
0
Oil
0
PS
PS
(
Function
Data bus. Input bus lor control words from microprocessor or
PROM. Bidireciional bus for cursor address.
Signals chip that it is being addressed
Register address bits for selecting one of seven control
registers or either of the cursor address registers
Strobes DB~-7 into the appropriate register or outputs the
cursor character address or cursor line address onto the data bus
Carry from off chip dot counter establishing basic character
clock rate. Character clock.
Character counter outputs.
Three most significant bits of the Scan Counter; row select
inputs to character generator.
Pin definition is user programmable. Output is MSB of
Character Counter if horizontal line count (REG.91) is ::=:'128;
otherwise output is MSB of Data Row Counter.
Least significant bit of the scan counter. In the interlaced mode with an even number of scans per data row,
RI!! will toggle at the field rate; for an odd number of
scans per data row in the interlaced mode, RQI will toggle
at the data row rate.
Data Row counter outputs.
Defines non active portion of tfbrizontal and vertical scans.
Initiates horizontal retrace.
Initiates vertical retrace.
Composite sync is provided on the CRT 5027 and CRT 5037.
This output is active in non-interlaced mode only. Provides a true
RS-170 composite sync wave form. For the CRT 5057, this pin is
the Line Lock Input. The line frequency waveform, processed to
conform to the VTAC'sil!l specified logic levels, is applied to this pin.
Defines cursor location in data field.
+ 5 volt Power Supply
+ 12 volt Power Supply
.....
.....,
." ="
...,.
.~~~
.311••40
•••
, ••
2
--1=-3----4
BLOCK DIAGRAM
122
(
I )
Operation
The design philosophy employed was 10 allow the device to interface effectively with either a microprocessor based or
hardwire logic system. The device is programmed by the user in one of two ways; via the processor data bus as part of the
system initialization routine, or during power up via a PROM lied on the data bus and addressed directly by the Row Select
outputs of the chip. (See figure 4). Seven 8 bit words are required to fully program the chip. Bit assignments for these words
are shown in Table 1. The information contained in these seven words consists of the following:
Horizontal Formatting:
Characters/Data Row
A 3 bit code providing 8 mask programmable character lengths from 20 to 132.
The standard device will be masked for the follOWing character lengths; 20, 32.
40,64, 72,80, 96, and 132.
Horizontal Sync Delay
3 bits assigned providing up to a character times for generation of "front porch".
Horizontal Sync Width
4 bits assigned providing up to 15 character times for generation of horizontal
sync width.
Horizontal Line Count
a bits assigned providing up to 256 character times for total hOrizontal formatting
Skew Bits
A 2 bit code providing from a 0 to 2 character skew (delay) between the
horizontal address counter and the blank and sync (hOrizontal, verttcal. composite)
signals to allow for retimlng of video data prior to generation of composite video
signal. The Cursor Video Signal IS also skewed as a function of this code.
Vertical Formatting:
Interlaced/Non-interlaced
Scans/Frame
This bit provides for data presentation with odd/even field formatting for Interlaced systems. It modifies the vertical timing counters as desCribed below.
A logic 1 establishes the interlace mode.
a bits assigned, defined according to the follOWing equations: Let X=
value of a
aSSigned bits.
1) in interlaced mode-scans/frame = 2X + 513. Therefore for 525 scans,
program X = 6 (00000110). Vertical sync will occur precisely every 262.5 scans,
thereby producing two interlaced fields.
Range = 513 to 1023 scans/frame, odd counts only.
2) in non-interlaced mode-scans/frame = 2X + 256. Therefore for 262 scans,
program X = 3 (00000011).
Range = 256 to 766 scans/frame, even counts only.
In either mode, vertical sync width is fixed at three hOrizontal scans ('" 3H).
Vertical Data Start
8 bits defining the number of raster scans from the leading edge of vertical
sync until the start of display data. At this raster scan the data row counter is
set to the data row address at the top of the page.
Data Rows/Frame
6 bits assigned providing up to 64 data rows per frame.
Last Data Row
6 bits to allow up or down scrolling via a preload defining the count of the last
displayed data row.
Scans/Data Row
4 bits assigned providing up to 16 scan lines per data row.
Additional Features
Device Initialization:
Under microprocessor control-The device can be reset under system or program control by presenting a 1'"" address
on A3-9'. The device will remain reset at the top of the even field page until a start command is executed by presenting a 1110
address on A3-\lJ.
Via "Self Loading"-In a non-processor environment, the self loading seguence is effected by presenting and holding the
1111 address on A3-{J, and is initiated by the receipt of the strobe pulse (DS). The 1111 address should be maintained long
enough to insure that all seven registers have been loaded (in most applications under one millisecond). The timing
sequence will begin one line scan after the 1111 address is removed. In processor based systems, self loading is initiated by
presenting the ,,111 address to the device. Self loading is terminated by presenting the start command to the device which
also initiates the timing chain.
Scrolling-In addition to the Register 6 storage of the last displayed data row a "scroll" command (address 1(11)
presented to the device will increment the first displayed data row count to facilitate up scrolling in certain applications.
123
Control Registers Programming Chart
Horizontal Line Count:
Characters/Data Row:
Horizontal Sync Delay:
Horizontal Sync Width:
Skew Bits
Scans/Frame
Total Characters/Line = N + 1, N = 0 to 255 (DBO = LSB)
DB2 OBi
DBO
()
0
0
20 Active Characters/Data Row
0
1 = 32
0
1
0
40
0
1
1
0
64
1
0
0
72
0
1
1
80
1
1
0
96
1
1
1
132
= N, from 1 to 7 character times (DBO = LSB) (N = 0 Disallowed)
N, from 1 to 15 character times (DB3 = LSB) (N = 0 Disallowed)
Sync/Blank Delay
Cursor Delay
DB7 DB8
(Character Times)
0
0
0
0
1
0
1
0
0
1
1
2
1
1
2
2
8 bits assigned, defined according to the following equations:
value of 8 assigned bits. (DBO LSB)
Let X
1) in interlaced mode-scans/frame = 2X + 513. Therefore for 525 scans,
program X 6 (00000110). Vertical sync will occur precisely every 262.5
scans, thereby producing two interlaced fields.
Range
513 to 1023 scans/frame, odd counts only.
2) in non-interlaced mode-scans/frame = 2X + 256. Therefore for 262
scans, program X 3 (00000011).
Range
256 to 766 scans/frame, even counts only.
In either mode, vertical sync width is fixed at three horizontal scans (= 3H).
N = number of raster lines delay after leading edge of vertical sync of
vertical start position. (DBO = LSB)
Number of data rows = N + 1, N = 0 to 63 (DBO LSB)
N = Address of last dsplayed data row, N = 0 to 63, ie; for 24 data rows,
program N = 23. (DBO LSB)
Register, 1, DB7 1 establishes Interlace.
Interlace Mode
programmed number of
CRT 5027: Scans per Data Row = N + 1 where N
data rows. N = 0 to 15. Scans per data row must be even counts only.
CRT 5037, CRT 5057: Scans per data Row = N + 2. N
0 to 14, odd or even
counts.
Non-Interlace Mode
CRT 5027, CRT 5037, CRT 5057: Scans per Data Row = N + 1, odd or
even count. N = 0 to 15.
(
=
=
=
=
=
=
=
=
=
=
=
Vertical Data Start:
Data Rows/Frame:
Last Data Row:
Mode:
Scans/Data Row:
=
=
(
=
=
=
=
U
ttl"~ ~
D~~~--~r----------~
SMC
CAT 5027. CAT 5037
or CAT 5057
VTAC/!)
DB7 ~~--++-I+H+p---(>1i::I
RJ
SELF LOADING SCHEME
FOR VTAce SET-UP
32.SPAOM
HARRIS HM· 7602
OR EQUIVALENT
5
(from system )
A. R;.
Figure 4.
1
srOA1i
Au
cs
t--t-H
HA,t--+-HH
HA)
ROW SELECTS
TO CHARACTER GENERATOR
124
(
\
Register Selects/Command Codes
Description
Select/Command
A3 A2 A1
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
Af
0
1
0
1
0
1
0
1
Load Control Register 0
Load Control Register 1
Load Control Register 2
Load Control Register 3
Load Control Register 4
Load Control Register 5
Load Control Register 6
Processor Initiated Self Load
0
0
0
0
1
0
Read Cursor Line Address
Read Cursor Character Address
Reset
0
0
1
See Table 1
Command from processor instructing
VTAC" to enter Self Load Mode (via external PROM)
Resets timing chain to !QQ left of page. Reset
is latched on chip by OS and counters are
held until released by start command.
Increments address of first displayed data
row on page. ie; prior to receipt of scroll
command-top line = 0, bottom line = 23.
After receipt of Scroll Command-top line
1, bottom line = O.
Up Scroll
0
0.=
o 0
o
1
Load Cursor Character Address'
Load Cursor Line Address'
Start Timing Chain
1
0
Receipt of this command after a Reset or
Processor Self Load command will release
the timing chain approxfmately one scan line
later. In applications requiring synchronous
operation of more than one CRT 5027 the
dot counter carry should be held low during
the DS for this command.
DevicELl"'ili begin self load via PROM
when DS goes low. The 1111 command
should be maintained on A3-0 long
enough to guarantee self load. (Scan
counter should cycle through at least
once). Self load is automatically terminated and timing chain initiated when the
all "1 's" ..£Qndition is removed, independent of DS. For synchronous operation
of more than one VTAC®, the Dot Counter
Carry should be held low when the command is removed .
Non-Processor Self Load
• NOTE: During Self-Load, the Cursor Character Address Register (REG 7) and the Cursor Row Address
Register (REG 8) are enabled during states 0111 and 1000 of the R3-R0 Scan Counter outputs respectively.
Therefore, Cursor data in the PROM should be stored at these addresses.
TABLE 1
BIT ASSIGNMENT CHART
HORIZONTAL LINE COUNT
REG_I?,
I
,
i , , ,~,
SKEW BITS
DATA ROWS/FRAME
REG3Iffi,;,
,
i
i ,
,~,
LAST DISPLAYED DATA ROW
,~--'-,-'-I. . .i--L.,---I.,--'~,
.
REG6L..-'...............
SCAN LINES/FRAME
,
REG
SCANS/DATA ROW
CHARACTERS/DATA ROW
21 , ~,
I; I
i ITlJ
I
,.
,
,~,
CURSOR CHARACTER ADDRESS
I
REG
71 ~, , , , , , '~I
VERTICAL DATA START
~
:;:::=;::,=*=',:::::;:,=;:I:::::;I:::L..,~
REG 5 . - l = 1; : : : : ,
CURSOR ROW ADDRESS
I
125
REG 8
~-'-,-,-I........i---LI--,I---,~
1...-1.L.......L..-'
I
AC TIMING DIAGRAMS
(
FIGURE' VIDEO TIMING
DOTCARRY
COUNTER
I
I~
________________________________________-JI
I~--------------------PWL--------------------~~------PWH----~~
H'-7
H SYNC. V SYNC. BLANK.
CURSOR VIDEO.
COMPOSITE SYNC
...- - - - T o " , - - -......._--1
FIGURE 2 LOAD/READ TIMING
~------------------------------------~
FIGURE 3 SCAN AND DATA ROW COUNTER TIMING
1\
HSYNC------------j
---- - , /
R8-3
DAJ-5
-------------f----..J1 \....
_____ __
-ToEL 3 ° -
°R0-3 and DRQJ-5 may change prior to the falling edge of H sync
CRT 15051 LINE LOCK
LINE LOCK IN
(110 HZ. 110 HZ)
'---.-'11
CRT 15051 LOGIC
THRESHOLD
I
I
I
l.-l-lIF LINE LOCK----.l
1"FlINELOCK ± I H ,
VERTI~SVNC _ _ _ _ _-+---,
LINE
LOCK
i--------'--------.. . .
....
~------~j~i·-----~'--~~~i~----------OUT
(
MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range ............
. ............. O°C to + 70°C
Storage Temperature Range ..................
. ................. - 55°C to + 150°C
Lead Temperature (soldering, 10 sec.) ....................................... " ...................... +325°C
Positive Voltage on any Pin. with respect to ground .................................................... + 18.0V
Negative Voltage on any Pin. with respect to ground .................................................... - 0.3V
. Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies
exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on and off.
In addition, voltage transient~ on the AC power line may appear on the DC output. For example, the
bench power supply programmed to deliver + 12 volts may have large voltage transients when Ihe
AC power is switched on and off. If this possibility exists it is suggestecj that a clamp circuil be used.
ELECTRICAL CHARACTERISTICS (TA=O°C to 70 D C, Vee= +5V:<::5%, VOO~ + 12V:<::5%. unless otherWise noted)
Parameter
Min.
Typ.
D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low Level, VIL
High Level. V,H
Vee-l.5
OUTPUT VOLTAGE LEVELS
Low Level-VOL for R!l-3
Low Level-VoL all others
High Level-VOH for RIl-3, DB"'-7
2.4
High Level-VoH all others
2.4
INPUT CURRENT
Low Level, ilL (Address, CS only)
Leakage, IlL (All Inputs except Address, CS)
INPUT CAPACITANCE
Data Bus, C,N
OS, Clock, C,N
All other, C,N
DATA BUS LEAKAGE in INPUT MODE
los
POWER SUPPLY CURRENT
Ice
80
40
100
A.C. CHARACTERISTICS
DOT COUNTER CARRY
frequency
PWH
PWL
tr. If
DATA STROBE
PW&s
ADDRESS, CHIP SELECT
Set-uptime
Hold time
DATA BUS-LOADING
Set-up time
Hold time
DATA BUS-READING
TOEL2
TOEL'
OUTPUTS: HIl-7. HS, VS, BL. CRV,
CS-ToELI
OUTPUTS: RIl-3, DRI6-5
TOEL3
10
25
10
Max.
Unit
0.8
Vee
V
V
0.4
0.4
V
250
10
p.A
p.A
15
40
15
pF
pF
pF
10
p.A
100
70
mA
mA
V
Comments
IOL" 3.2ma
IOL ·,l.6ma
IOH ',BOlla
IOH.04Olla
V ,N =O.4V
O$.VINS,vce
O.4V"'" V ,N
TA
0.2
35
215
4.0
10
150ns
50
MHz
ns
ns
ns
=
"'"
5.25V
25C
Figure
Figure
Figure
Figure
1
1
1
1
Figure 2
10l-'s
125
50
ns
ns
Figure 2
Figure 2
125
75
ns
ns
Figure 2
Figure 2
60
ns
ns
Figure 2. CL = 50pF
Figure 2, CL= 50pF
125
ns
Figure 1, CL=20pF
500
ns
Figure 3, CL=20pF
125
5
*
·R~-3 and DR0-5 may change prior to the falling edge of H sync
Restric.tions
1. Only one pin is available for strobing data into the device via the data bus. The cursor X and Y coordinates are therefore
loaded into the chip by presenting one set of addresses and outputed by presenting a differenl set of addresses. Ther~fore
the standard WRITE and READ control signals from most microprocessors must be "NORed" externally 10 present a single
strobe (OS) Signal to the device.
2. In interlaced mode the total number of character slots assigned to Ihe horizontal scan musl be even 10 insure Ihal vertical
sync occurs precisely between horizontal sync pulses.
127
General Timing
HQRIZQNTAL TIMING
START QF LINE N
Jl
START QF LINE N+ 1
n
flzll71III/ZII/IIII/I/iIOn
I
ACTIVE VIDEQ=
CHARACTERS PER DATA LINE
.
HQRIZQNTAL SYNC DELAY
IFRONT PQRCHI
I
]mIll
.
.
HQRIZQNTAL SYNC WIDTH
i"
HQRIZCNTAL LINE CQUNT= H - - - - - -...........,
VERTICAL TIMING
START CF FRAME M CR 0.00 FIELD
1-
JI
~
VERTICAL DATA
START
n
~
ACTIVE VIDEC=
DATA RQWS PER FRAME
.
vm
VERTICAL SYNC
!!! 3H
Composite Sync Timing
SYNv~
VOH
-\
.VI/I I ZZllUllillZZU7/IIIZZZ1111
o=j"
-I
VOH
H
START QF FRAME Mt 1 QR EVEN FIELD
SCANL~ESPERFRAME
i
~
n~~nL----------lnL--_1L
I'
,
i
V SYNC : .
.
V-OL-r!------~
:"""--H
['
~---------
~4--- H ------.i
L.JLJL
VOH:
:"'HI2-+l:
Ur
COMPOSITt1
SYNC VOL
Vertical Sync Timing
.1
- - fRAME M - - - - - - - SC:A~
OAT"-: H:-
ri1
SCANS ROW - ,
COUNTER AO
N . CJ
U U
0
~
CQUNTf A IS HELD
RE5£ 1 [)URH'\I(j V HLANIO.
rn m n
u. u u
J
Gil r1l III r;l
Po
U U LJ U
0
")
b
.j
m
IRAMt M · ' - - - - - - • • •
(
1
~'
U LII
"
23 --
9
L _ _ _, _ _--.J
.IIERTICAl OATA START <;C"'''''
BlANM
REt,
~I
.JlllW1LW~
1'"1 _______
VE~TICAL
S'VNC
EXAMPLE BASED ON Non Intf"litCPdIRI'9'
8",
01 "4r1>l1,1'U""~ 'O"'itn~ ditt.1'':'''
Start-up, CRT 5027
When employing micrcprccessQr cQntrolied Icading Qf the CRT 5027's registers, the fQllQwing sequence of instructions is necessary:
o
o
o
COMMAND
Start Timing Chain
Reset
Load Register 0
o
o
LQad Register 6
Start Timing Chain
ADDRESS
1
1
1 o
o o
o
1
1
1
0
The sequence of START RESET LOAD START is necessary to insure proper initialization of the
registers.
,
This sequence is not required if register loading is via either of the Self Load modes. This sequence
is optional with the CRT 5037 or CRT 5057.
,Circuit dlagraJ'lls utiliZing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility IS
assumed for ,naccuraciesiFurthermore, such informatIon .does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others: SMC reserves the right to make changes
at any time in order to Improve design and supply the best product possible.
128
(
COM2502
COM2017
you
iftaI pn
COM2502/H
COM2017/H
Universal Asynchronous Receiver/Transmitter
35 Marcus Blvd, Hauppauge NY 11787
(516) 273-3100 TWX-510-227-8898
rnrrwlllHftlYl SO
(31
keep
Of
UART
Pin Configuration
FEATURES
Vee
Voo
o Direct TTL Compatibility- no interfacing circuits
Gnd
R"m:
required
ROB
R07
R08
RDS
RD4
RD3
R02
RD1
RPE
RFE
ROR
o Full or Half Duplex Operation -
can receive and
transmit simultaneously at different baud rates
o Fully Double Buffered -
eliminates need for precise
external timing
o Start Bit Verification - decreases error rate
o Fully Programmable-data word length, parity mode,
swr
number of stop bits; one, one and one-half, or two
o High Speed Operation-40K baud, 200ns strobes
o Master Reset- Resets all status outputs
o Tri-State Outputs- bus structure oriented
o Low Power- minimum power requirements
o Input Protected-eliminates handling problems
o Ceramic or Plastic Dip Package-easy board insertion
RCP
ROAR
ROA
RSI
TCP
POE
NOBl
NDB2
NSB
NPB
CS
TD8
T07
T08
T05
T04
T03
T02
TOI
TSO
TEOC
TI5'S'
TBMT
MR
PACKAGE: 40-Pin D.I.P.
Functional Block Diagram
TOl TD2 T03 T04 TOS T08 T07 TD8
'11m'
23
25
TSO
TEOC
~
GENERAL DESCRIPTION
The Universal Asynchronous Receiver/Transmitter is
an MaS/LSI monolothic circuit that performs all the
receiving and transmitting functions associated with
asynchronous data communications. This circuit is
fabricated using SMC's P-channellow voltage oxidenitride technology. The duplex-mode, baud rate, data
word length, parity mode, and number of stop bits are
independently programmable through the use of external controls. There may be 5, 6, 7 or8 data bits, odd/even
or no parity, and 1, or 2 stop bits or 1.5 stop bits when
utilizing a 5-bit code from the COM 2017 or COM 2017/H.
The UART can operate in either the full or half duplex
mode. These programmable features provide the user
with the ability to interface with all asynchronous
peripherals.
59
TBMT
APE
AFE
ROR
ADA
18
21
1
2
Rtrof
MR
~~~
Gnd
DESCRIPTION OF OPERATION- TRANSMITTER
;,'
commences. TSO goes low (the start bit), TEOC
goes low, the TBMT goes high indicating that the
data in the data bits buffer register has been loaded
into the transmitter shift register and that the data
bits buffer register is available to be loaded with
new data.
If new data is loaded into the data bits buffer register
, at this time, TBMT goes low and remains in this state '
until ,the present transmission is completed. One
full character time is available for loading the next
character with no loss in speed oftransmission. This
is an advantage of double buffering.
Data transmission proceeds in an orderly manner:
start bit, data bits, parity bit (if selected). and the
stop bit(s). When the last stop bit has been on the
line for one bit time TEOC goes high. If TBMT is
low, transmission begins immediately. If TBMT is
high the transmitter is completely at rest and, if
desired, new control bits may be loaded prior to the
next data transmission.
At start-up the power is turned on, a clock whose
frequency is 16 times the desired baud rate is
applied and master reset is pulsed. Under these
conditions TBMT, TEOC, and TSO are all at a high
level (the line is marking).
When TBMT and TEOC are high, the control bits
may be set. After this has been done the data bits
may be set. Normally, the control bits are strol)ed
into the transmitter prior to the data bits. However,
as long as minimum pulse width specifications
are not violated, iDS and CS may occur simultaneously. Once the date strobe (TDS) has been
pulsed the TBMT signal goes low, indicating that
the data bits buffer register is full and unavailable to
receive new data.
If the transmitter shift register is transmitting previously loaded data the TBMT signal remains low.
If the transmitter shift register is empty, or when it is
through transmitting the previous character, the
data in the buffer register is loaded immediately into
the transmitter shift register and data transmission
(
TRANSMITTER BLOCK DIAGRAM
(
ODD/EVEN
PARITY SELECT
DB6 DB7 DB6 DBS DB4 DB3 DB2 OBI
CONTROL
STROBE
~--4--- DATA STROBE
TRANSMITTER
BUFFER
EMPTY
16xT
CLOCK
SERIAL
OUTPUT
TIMING GENERATOR
PARITY BIT GENERATION LOGIC
END OF
CHARACTER
DESCRIPTION OF OPERATION-RECEIVER
At start-up the power is turned on, a clock whose
frequency is 16 times the desired baud rate isapplied
and master reset is pulsed. Thedataavaiiable(ADA)
signal is now low. There is one set of control bits for
both the receiver and transmitter.
Data reception begins when the serial input line
transitions from mark (high) to space (low). If the
ASlline remains spacing for a1/2 bittime, agenuine
start bit is verified. Should the line return to a mark-
ing condition priorto a 1/2 bittime, the start bit verification process begins again. A mark to space
transition must occur in order to initiate start bit
verification. Once a start bit has been verified, data
reception proceeds in an orderly manner: start bit
verified and received, data bits received, parity bit
received (if selected) and the stop bit(s) received.
If the transmitted parity bit does not agree with the
received parity bit, the parity error flip-flop of the
60
status word buffer register is set high, indicating a
parity error. However, if the no parity mode is selected, the parity error flip-flop is unconditionally
held low, inhibiting a parity error indication. If a
stop bit is not received, due to an improperly framed
character, the framing error flip-flop is set high,
indicating a framing error.
Once a full character has been received internal
logic looks at the data available (RDA) signal. If, at
this instant, the RDA signal is high the receiver
assumes that the previously received character has
not been read out and the over-run flip-flop is set
high. The only way the receiver is aware that data
has been read out is by having the data available
reset low.
At this time the RDA output goes high indicating
that all outputs are available to be examined. The
receiver shift register is now available to begin receiving the next character. Due to the double buffered receiver, a full character time is available to
remove the received character.
RECEIVER BLOCK DIAGRAM
FRAMING
ERROR
RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1
TRANSMITTER
BUFFER EMPTY
RESET DATA
AVAILABLE
BITS FROM
HOLDING _____________
CONTROL
REGISTER
J:::::::;:::::~::~~~==========~======l
SERIAL
INPUT
RIGHT
JUSTIFY LOGIC
16xR
CLOCK
DESCRIPTION OF PIN FUNCTIONS
PIN NO.
SYMBOL
NAME
FUNCTION
Vee
Power Supply
+5 volt Supply
2
Voo
Power Supply
-12 volt Supply
3
GND
Ground
Ground
4
ROE
Received Data
Enable
A low-level input enables the outputs (RDS-RD1) of the
receiver buffer register.
5-12
RDS-RD1
Receiver Data
Ou.tputs
These are the S tri-state data outputs enabled by ROE.
Unused data output lines, as selected by NDB1 and NDB2,
have a low-level output, and received characters are right
justified, i.e. the LSB always appears on the RD1 output.
13
RPE
Receiver Parity
Error
Thistri-state output (enabled by SWE) is at a high-level if
the received character parity bit does not agree with the
selected parity.
14
RFE
Receiver Framing
Error
This tri-state output (enabled by SWE) is at a high-level if
the received character has no valid stop bit.
61
DESCRIPTION OF PIN FUNCTIONS
PIN NO.
SYMBOL
FUNCTION
NAME
15
ROR
Receiver Over
Run
This tri-state output (enabled by SWE) is at a high-level if
the previously received character is not read (RDA output
not reset) before the present character is transferred into
the receiver buffer register.
16
SWE
Status Word
Enable
A low-level input enables the outputs (RPE, RFE, ROR,
RDA, and TBMT) of the status word buffer register.
17
RCP
Receiver Clock
This input is a clock whose frequency is 16 times (16X) the
desired receiver baud rate.
18
ROAR
Receiver Data
Available Reset
A low-level input resets the RDA output to a low-level.
19
RDA
Receiver Data
Available
This tri-state output (enabtP.d by SWE) is at a high-level
when an entire character has been received and transferred
into the receiver buffer register.
20
RSI
Receiver Serial
Input
This input accepts the serial bit input stream. A high-level
(mark) to low-level (space) transition is required to initiatE:
data reception.
21
MR
Master Reset
This input should be pulsed to a high-level after power
turn-on. This sets TSO, TEOC, and TBMT to a high-level
and resets RDA, RPE, RFE and ROR to a low-level.
22
TBMT
Transmitter
Buffer Empty
This tri-state output (enabled by SWE) is at a high-level
when the transmitter buffer register may be loaded with
new data.
23
TDS
Transmitter
Data Strobe
A low-level input strobe enters the data bits into the
transmitter buffer register.
24
TEOC
Transmitter End
of Character
This output appears as a high-level each time a full character
is transmitted. It remains at this level until the start of
transmission of the next character or for one-half of a TCP
period in the case of continuous transmission.
25
TSO
Transmitter
Serial Output
This output serially provides the entire transmitted
character. TSO remains at a high-level when no data is
being transmitted.
26-33
TD1-TD8
Transmitter
Data Inputs
There are 8 data input lines (strobed by TDS) available.
Unused data input lines, as selected by NDB1 and NDB2,
may be in either logic state. The LSB should always be
placed on TD1.
34
CS
Control Strobe
A high-level input enters the control bits (NDB1, NDB2,
NSB, POE and NPB) into the control bits holding register.
This line may be strobed or hard wired to a high-level.
35
NPB
No Parity Bit
A high-level input eliminates the parity bit from being
transmitted; the stop bit(s) immediately follow the last data
bit. I n addition, the receiver requires the stop bit(s) to follow
immediately after the last data bit. Also, the RPE output is
forced to a low-level. See pin 39, POE.
62
(
)
(
\
(
)
DESCRIPTION OF PIN FUNCTION
PIN NO.
FUNCTION
NAME
SYMBOL
f
36
NSB
Number of
Stop Bits
This input selects the number of stop bits. A low-level input
selects 1 stop bit; a high-level input selects 2 stop bits.
Selection of 2 stop bits when programming a 5 data bit word
generates 1.5 stop bits from the COM 2017 or COM 2017/H.
37-38
NDB2,
NDB1
Number of Data
Bits/Character
These 2 inputs are internally decoded to select either5, 6, 7,
or 8 data bits/character as per the following truth table:
NDB2 NDB1
data bits/character
L
L
5
L
H
6
H
L
7
H
H
8
39
POE
Odd/Even Parity
Select
The logic level on this input, in conjunction with the NPB
input, determines the parity mode for both the receiver and
transmitter, as per the following truth table:
MODE
NPB POE
L
L
odd parity
L
H
even parity
H
X
no parity
X = don't care
Transmitter
Clock
This input is a clock whose frequency is 16 times (16X) the
desired transmitter baud rate.
40
TCP
TRANSMITTER TIMING-8 BIT, PARIT,(, 2 STOP BITS
I
TOS
~
TBMT
__________
~r--
TSO
~;2:~il.· ... ID~T~~~~~jsToPl'sTOP2IsTART
TEOC
------,~____lI_m_e_______________________ L_ _ _ __
~
Bil
I---
TRANSMITTER START-UP
...JLJLJU"
I
I
TCP
--I
TDS
TSO
~---,L.
______
1/18
Bit
time
f--
Upon data transmission Initiation, or when not transmitting at 100fMlineutillzation, lhe Itart bit will be placed
on the TSO line at the high to tow transition 01 the TCP clock following the trailing edge of TOS.
RECEIVER TIMING-8 BIT, PARITY, 2 STOP BITS
RSt
~~A.2I .... ·Io~T~a}~R~1 STOP I'STOP2IsTART
CENTER BIT
SAMPLE
RDA'
ROA"
-oot I+- 1116 B,ttime
---- ------------- ---...,
II
"The RDA.line was previously not reset (ROR = high~lev.I),
··The RDA line was previously reset (ROR = low·level).
START BIT DETECT/VERIFY
RCP
RSI
MS~-'
.
~"'rIfy.
. 1'---_·_-
Begin verify
If the ASIline remains spIcing for. 1/2 bit time, I genuine stl" bit is verified. Should the liM return to.
marking condition prior to .1/2 bit time. the start bit verification proceu begin. again.
63
MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range .........................•............•............... DoC to +70°C
Storage Temperature Range .................................................... -55 0 C to +150° C
Lead Temperature (soldering, .10 sec.) .............•....................................... +325° C
Positive Voltage on any Pin, Vce ............................................................ +0.3V
Negative Voltage on any Pin, Vee ......................... ; .................................. -25V
( r
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.
ELECTRICAL CHARACTERISTICS (TA == 0° C to 70 0 C, Vce = +5V ±5%, VDO == -12V ±5%, unless otherwise noted)
Parameter
D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, VIL
High-level, VIH
OUTPUT VOLTAGE LEVELS
Low-level, VOL
High-level, VOH
INPUT CURRENT
Low-level, IlL
OUTPUT CURRENT
Leakage, ILO
Short circuit, los"
INPUT CAPACITANCE
All inputs, CIN
OUTPUT CAPACITANCE
All outputs, COUT
POWER SUPPLY CURRENT
lee
Min.
Max.
Unit
0.8
Vee
V
V
0.4
V
V
1.6
mA
see note 4
-1
10
.u A
mA
SWE == RDE
VOUT=OV
5
10
pf
VIN = Vee, f
10
20
pf
SWE = RDE = VIH, f = 1MHz
28
28
mA
mA
All outputs = VOH, All inputs
Typ.
Voo
Vee-1.5
2.4
0.2
4.0
100
A.C. CHARACTERISTICS
CLOCK FREQUENCY
(COM2502, COM20i7)
(COM2502H, COM2017H)
PULSE WIDTH
Clock
Master reset
Control strobe
Transmitter data strobe
Receiver data available reset
INPUT SET-UP TIME
Data bits
Control bits
INPUT HOLD TIME
Data bits
Control bits
STROBE TO OUTPUT DELAY
Receive data enable
Status word enable
OUTPUT DISABLE DELAY
Conditions
IOl == 1.6mA
IOH == 100.uA
TA
DC
DC
400
640
1
= VIH, 0 ::=; VOUT ::=; +5V
= 1MHz
= Vee
= +25°C
KHz RCP, TCP
KHz RCP, TCP
RCP, TCP
MR
CS
500
200
200
200
.us
ns
ns
ns
ns
;:::0
;:::0
ns
ns
TD1-TD8
NPB, NSB, NDB2, NDB1, POE
;:::0
;:::0
ns
ns
TD1-TD8
NPB, NSB, NDB2, NDB1, POE
Load = 20pf +1 TTL input
RDE: TpOl, Tpoo
SWE: TpOl, Tpoo
RDE,SWE
350
350
350
(
ns
ns
ns
TlJS
RDAR
"Not more than one output should be shorted at a time.
NOTES: 1. If the transmitter is inactive (TEOC and TBMT are at a high-level) the start bit will appear on the TSO line within
one clock period (TCP) after the trailing edge of ms.
2. The start bit (mark to space transition) will always be detected within one clock period of RCP' guaranteeing
a maximum start bit slippage of 1/16th of a bit time.
3. The tri-state output has 3 states: 1) low impedancetoVce 2~'8E impedanceto GND 3) high impedance OFFe
10M ohms. The "OFF" state is controlled by the SWE and
inputs.
4. Under steady state conditions no current flows for TTL or MaS interfacing. (COM 2502 or COM 2502/H)
64
(
DATA/CONTROL TIMING DIAGRAM
VIH
VIL
- - - Tpw·
DATA INPUTS
tr =tf = 20 ns
VIH
VIL
TSET-UP~O
THOLD ~O
CS
CONTROL INPUTS
~:~
____ fiole----
Tpw·
---..:;-.j
:~:T~. L
VIL
~_ _ _ _ _ _ _ _ _ _ _ __
"Input information (Data/Control) need onl~valid during
the last Tpw, min time of the input strobes (TDS, CS).
OUTPUT TIMING DIAGRAM
Outputs Disabled
OUTPUTS
(RD1-RD8, RDA,
RPE, AOA, RFE, TBMT)
VOH
VOL
TPD1, TPDO
NOTE: Waveform drawings not to scale for clarity.
ROAR
------~ ~---200ns--~
VIL
VIH
- - - - - - - - - -
VOL
TMBT
VOL
RDA
14---- 300ns - - - - - + I
65
400ns
FLOW CHART-TRANSMITTER
FLOW CHART-RECEIVER
(
YES
HAS
NO
A STAAT
BIT BEEN? VERIFIED
8-16. elK
(
NO
HAS
THE LAST
STOP BIT BEEN ON 1 HE
LINE FOR 1 BIT
TIME?
RESET DATA A.VAILABLE - 0.4. = 0
Circuit diagrams utilizing SMC products are included as a means of illuslraling typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the besl product pOSSible.
66
(
APPENIX D
KEYBOARD MATRIX
912C/920C
Below is the matrix ("schematic· ) that is expected on the
keyboard attached to connector Pl. The character interpretation
is actually a firmware decision.
#0
8
COLUMN
PINI
II
9
'2
10
13
11
$
ROW 10
20
N
4
R
G
11
16
X
ESC
TAB
A
T
H
1,.
Q
S
6
Y
J
W
D
%
12
M
21
5
!
#3
14
C
17
<
22
#4
#6
15
12
13
14
LINE BLOCK I
II
FEED
CONVI
\I
_I
I
LI
I
-I
*1
I
I_______ ~_L
+
0
•
I•
?
/
=(
17
15
I
l
z
CLEAR
9
@
IS
18
16
23
#7
19
18
26
V
2
>
&
B
7
I
3
E
25
LINE
ERA
LINE
DEL
LINE
INS
110 24
F8
19
III
I
F71
I
I
7
ALPHA
LOCK
3
SHIFT
4
I
I
I
I
FUNCT
5
I
CTRL
6
GROUND
1£2
U
P
ENTER
SPACE
BAR
DEL
0
BACK
SPACE
K BERAK
HOME
}
]I
{
F
[ IRETURN
SEND
BACK I SEND
PAGE
LINE ERASE
_~!\BJ. __ ]? AGE
-CHAR
CHARI
F11
F101
DEL
INSI
F9
----1--I
I
F31
F21
F1
F5
F41
I
I
I
I
I
-,,
F6
I
I
I
)
1
APPENDIX D
KEYBOARD MATRIX
()
912B/920B
Below is the matrix ("schematic") that is expected on the keyboard
attached to connector Pl.
The character interpretation is actually a
firmware decision.
COLUMN
#1
P IN fF~
~
8
9
IF2
10
4t3
it4
its
11
I'
1
#6
14
P
ROW 4t0
20
N
4
R
G
CR
PAGE
]
4n
16
X
TAB
ESC
A
I
L
:
Z
In
21
M
5
T
H
PRINT
Eo-
8
t
#3
17
C
1
Q
S
0
.
-
CLEAR
#4
22
.
6
y
J
RUB
I
9
it5
18
V
2
W
D
It6
23
.
7
U
K
In
19
#8
26
4t9
25
B
IFlO 24
4t11
7
E
P
(a
0
BREAK
SP
1\
HOME
[
PROT
F
LF
"-
BRK
SND
PAl
SD
LIN
ERA
Fll
FlO
F9
F3
F2
Fl
LIN
ERA
LIN
DEL
LIN
INS
CRR
DEL
F8
F7
F6
F5
F4
~3~
SHFT
~4~__~__
FUNC
~5,-
CTL
_loL--
~
CLR
TAB
TAB
CRR
INS
AUHA
6
3
~
(
PG
__~__
__~__
_.-r-_
GROUND ...:1:.a..:2_ _
(
D-1
APPENDIX E
CONNECTOR LISTS
PI
KEYBOARD CONNECTOR (See also Appendix D)
PIN 1
Ground for Keyboard
2
3
"
"
"
Input from keyboard ALPHA KEY
Bit 6 of 4'C to 4'F
4
"
"
"
SHFT KEY
" 4 "
"
"
5
"
"
"
FUNC KEY
"
2 "
"
"
6
"
"
"
CTL KEY
"
3 "
"
"
7
Input from keyboard
Matrix
Bit 5 of 4t'F
8
Output to keyboard
Matrix Column
Bit
9
Output to keyboard
Matrix Column
Bit 1 of Port 1
10
Output to keyboard
Matrix Column
Bit 2 of Port 1
11
Output to keyboard
Matrix Column
Bit 3 of Port 1
12
Output to keyboard
Matrix Column
Bit 4 of Port 1
13
Output to keyboard
Matrix Column
Bit 5 of Port 1
14
Output to keyboard
Matrix Column
Bit 6 of Port 1
15
Output to keyboard
Matrix Column
Bit 7 of Port 1
16
Input from keyboard Matrix
Bit 1 of 4,C
17
Input from keyboard Matrix
Bit 1 of 4'D
18
Input from keyboard Matrix
Bit 1 of 4,E
19
Input from keyboard Matrix
Bit 1 of 4'F
20
Input from keyboard Matrix
Bit ~ of 4fC
21
Input from keyboard Matrix
Bit fJ of 4,n
22
Input from keyboard Matrix
Bit fJ of 4f)E
23
Input from keyboard Matrix
Bit f) of 4f)F
24
Input from keyboard Matrix
Bit 5 of 4f)E
E-1
of Port 1
"
Pl
KEYBOARD CONNECTOR (Continued)
25
Input from keyboard Matrix
Bit 5 of 4,D
26
Input from keyboard Matrix
Bit 5 of 4IC
P2
VIDEO CONNECTOR
PIN 1
-HlSYNC
2
''KEY''
3
VIDEO SHIELD GROUND
4
+VlDEO
5
-VSYNC
6
+Tl'L VIDEO
(or -CCNPSYNC with S2-10. 11 open)
COMPUTER PORT
P3
PIN 1
2
TXD (RS232)
Transmit Data, Output
3
RCVD (RS232)
Receive Data, Input
4
RTS (RS232)
Request to Send, Output
5
CTS (RS232)
Clear to Send, Input
6
DCR2 (RS232)
"Data Carrier Ready, (S5-2, 13), Input
7
GROUND
8
DCRl (RS232)
"Data Carrier Ready" (S5-1, 14). Input
12
RXDl
(TrY)
Current Loop Receive Data 1, Input
13
TXD2
(TTY)
Current Loop Transmit Data 2, (Return) Output
(
9
10
11
14
15
(
16
17
£-2
!
P3
OOHPUTER. PORT (Continued)
PIN 18
19
DTR
(R8232)
24
RXD2
(TTY)
Current Loop Receive Data 2 (Returns) Input
25
TXD 1
(TTY)
Current Loop Transmit Data 1, Output
20
Data Terminal Ready (85-3, 12 and 85-4,11), Output
21
22
23
PRINTER PORT
P4
PIN
1
2
3
PRT DATA
(R8232l Transmit Data, Output
4
5
6
TERM RDY2 (R8232) "Terminal Ready" (WI2), Output
7
GROUND
8
TERM RDYI (R8232) "Terminal Ready" (W13), Output
9
10
11
12
13
14
15
16
17
E-3
p4
PRINTER PORT (Continued)
PIN 18
(l
19
20
+PRTRDY
(RS232)
Printer Ready, Input
21
22
23
24
25
POWER SUPPLY CONNECTOR
P5
PIN
1
-12V
2
"KEY"
3
GROUND
4
+5V
5
+12V
(
P7
PIN 1
2
Speaker 8.r.L
"
"
(
E-4
\
Z8400
~
Zilog
Processing Dail
...... J
~-l
_.
081
-=j
={
c_
Pia
De.criptlo...
Au-Als, Address Bus (output, active High,
3-state). Ao-Als form a 16-bit address bus. The
Address Bus provides the address for memory
data bus exchanges (up to 64K bytes) and for
I/O device exchanges.
·.USACK. Bus Acknowledge (output, active
Low). Bus Acknowledge indicates to the
requesting device that the CPU address bus,
data bus, and control signals MREQ, 10RQ,
RD, and WR have entered their highimpedance states. The external circuitry
can now control these Hnes.
BUSREQ. Bus Request (input, active Low).
Bus Request has a higher priority than NMI
and is always recognized at the end of the cur·
rent machine cycle. BUSREQ forces the CPU
address bus, data bus, and control signals
MREQ, 10RQ, RD, and WR to go to a highimpedance state so that other devices can
control these lines. BUSREQ is normally wireORed and requires an extern~ lor
these applications. Extended BUSREQ
periods due to extensive DMA operations can
prevent the CPU from properly refreshing
dynamic RAMs.
Du-D,. Data Bus (tnpuVoutput, active High,
3-state). Do-D? constitute an 8-blt bidirectional
data bus, used for data exchanges with
memory and I/O.
HALT. Half Slate (output, acttve Low). HALT
indicates that the CPU has executed a Halt
instruction and is awaiting either a non·
maskable or a maskable interrupt (wtlh the
"zao
WAIT. Wait (input, active Low). WAIT
indicates to the CPU that the addressed memory or I/O devices are not ready for a data
transfer. The CPU continues to enter a Wail
state as long as this signal is active. Extended
zscrcPu Celltral
F_ur_
mi!sk enabled) before opertltion can resume.
While halted, the CPU executes NOPs to
maintain memory refresh.
lutructloa
Set
INT.. Interrupt Request (input, active Low).
Interrupt Request is generated by I/O devices.
The CPU honors a request at the end of the
current instruction if the internal softwarecontrolled interrupt eMble flip-flop (IFF) ts
enabled. INT is normally wire-ORed and
requires an external pullup for these
appliCdtions.
IORQ. Input/Output Request (output, active
Low, 3-state). 10RQ indicates that the lower
half of the address bus holds a valid I/O
address for an 110 read or write operdtion.
10RQ is also generated concurrently with Ml
during an interrupt acknowledge cycle to indicate that an interrupt response vector can be
placed on the data bus.
MI. Machine Cycle One (output, active Low).
MI, together with MREQ, indicates that the
current machine cycle is the opcode felch
cycle of an instruction execution. M'l, together
with IORQ, indicates an interrupt acknowledge
cycle.
MREQ, Mem~uesf(output, active
Low, 3-state). MREQ indicates that the address
bus holds a valid address for a memory read or
memory write operation.
NMI. Non-Maskable Interrupt (input, active
Low). NMI has a higher prtority than INT. NMI
is always recognized at the end of the current
instruction, independent of the
status of the interrupt enable flip-flop, and
automatically forces the CPU to restart at
location 0066H.
RD. Memory Read (output, active Low,
3-state). RD indicates that the CPU wants to
read data from memory or an liD device. The
addressed I/O device or memory should use .
this Signal to gate data onto the CPU data bus.
RESET. Reset (input, active Low). RESET
initializes the CPU as follows: it resets the
interrupt enable flip-flop, clears the PC and
Registers I Snd R, and sets the interrupt statuI
to Mode O. During reset time. the address and
data bus go to a high-impedance state, and all
control output signals go to the inactive state.
Note that RESET must be active for a minimum
of three full clock cyCles before the reset
operation is complete,
RFSH. Refresh (output, active Low). RFSH,
together with MREQ, indicates that the lower
seven bits of the system's address bus can be
is a trademark. of Zi 1og. Inc.
with whom the publisher is not associated."
WAIT periods can prevent the CPU from
refreshing dynamic memory properly.
WK. Memory Write (output, active Low,
3-state). WR indicates that the CPU data bu.
holds valid data to be stored at the addressed
Qlemory or va location.
used as a refresh address jo the system's
dynamic memories.
o
o
The ZBO microprocessor has one of the most
powerful and versatile instruction sets
available in any 8-btt microprocessor. It
JnclYdes such unique operations as a block
move for fast, efficient data transfers within
memory or between memory and JlO. It also
.allows operations on any hit in any location in
menmi'y.
Yfle following is a summary of the ZOO
instruction set and shows the assembly
language mnemonic. the operation, the flag
status. and gives comments on each instruction, Tile Z8G CPU Technical Manual
(03COO29-0l) and Assembly Language
Prooromming Manual (03-0002-01) contain
significantly more details for ·programming
use_
The instructions are dtvlded tnto the
follOWing categories:
General-purpose arithmetic and CPU
control
o J6- bit arithmetic operations .
o Ratates and shifts
o
o 16-bit loads
I-BII
LOad
Group
-
Exchanges, block transfers, and ..... rches
-
........
•
•"-
I
PlY. C
r - r'
LOr. "
LOr. n
LOr. tRL)
Llh. UK+d)
r r -
Bit set, resel, and test operations
o Jumps
o
o
Calls, returns, and restarts
InpUt and output operations
.A variety of addressing modes are
Implemented to permit efficient amUaat data
transfer between various registers, memory
locations. and input/output devices. These
addressinq mades Include:
o a-bit load.
o
8-blt arithmetic and logic operaliOfls
o Immediate
0 Indexed
o
o
Immediate extended
o Register hmlrect
o Relative
o
o
o
Extended
" III III . . . , .
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o Modlfted page zero
57
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51
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41
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I
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@]~n
....
I
m_r.(HLI (IX + d) p
CY md,eal.. 'he c-a"y 11,,,11<>,,
IS·Bit
Arithmetic
Group
--
•
m_ r (HL),IlX +d) OY .. dl
ComplelTl<'lnl ""rry
00 110 111 37
00 oo:J OOJ 00
.,....,.
II 101 101 ED
01 010 )10 56
mod" 2
It
RRm
SRA m
01 OOJ 110 46
x • x
-SlA m
II Ito 011 F3
11 III 011 FB
II 101 JOt ED
Sellnlerrupl
mode I
Set Interrupt
1M2
71 U3 210.. . , . .
00 100 III Il
01 lIb 110 76
IFF - 0
IMI
110." Mo." II 1I00of T
Opeode
•
OAA
"
X
•
X
\1 101001 E9
II Oil \01 DO
II 101 001 E9
If condillon J, met
J.... Groap
(Conllnued)
-
-
..-
JPlm
•
....
I
--
Dna..
• ,IY.
I
PC-IT
1- 8-1
•
I
.u 1.0,
I
•
•
I
-
C
.
•
--
a....! ........... ,
" IU III -
.....
c,.a.. _
II III 101 'D
11101001 a
00 010 000 10
lupUI cad
13
PC - PC ••
SUIDIDIIr7 of
_2 .............._ ...
~I
CALL ..
Flag
OperalloR
PCt
(SP-lJ PC- ..
CALLoc.
liiio
~
.
-1Gt
(SP-I)
..........
-.
licondlllon
--~
•
I
•
I
I
•
•
11001 101 CD
PCt. -
PClf
I
(SP)
-- . --
.
I
•
,Bce."".
17
liccjalnle.
I
.........
•
X
•
IIccOOO
Hee.f....
•
-'..........
I
X
•
I
•
X
•
11 101
QI 001
11101
01 000
",,01
101
IOJ
101
...
ED
4D
ED
45
"-pi
X
{SP-U - PCH
PCt.
•
X
•
II
t
111
II
PCH - 0
PCL - P
CCF
IN ~{C,
INI. IND. OUTI. auTO
INIR. INDR. OTUI.. OTDR
LDI. LOD
LOIR. LODR
CPt; CPIR; cpo: CPDR
II cell true.
~
"""",,pi
000 Ai
001
010
all
100
Condillon
non-zero
Z ani
He non-carry
C carry
PO pull}' odd
LOA.f. LOA.R
SIT b.,
101 PE plrlty even
110 P mqn poNllq,
III M "Qh~_
Symbobc
Symbol
;.,. liaH
Notation
S
Z
PlY
001
OBH
010
10H
all ISH
100 20H
101 28H
110 30H
III JBH
NOTl
'RETH Ioado IfF:z - lffl
IDputcad
INA,In)
A-In)
Output Group
DI ,. IC)
r-ICI
Ifr _ IlOonl.ytM
tl.Q._t1lbeaJt.ct.d
I
INI
(HW-(CI
8 - 8-1
HL-HL+I
(HU - Ie)
8 - 8-1
HL-HL+ I
X
I
DI"
_.nUI
DIDO
(HL) - (C)
B -.B-I
HL-Hl-I
IHU-{Cj
B-B-l
•
X
•
11 all 011 DB
II
nloAo - A1
X
1
X
P
a
II 101 101 ED
01 r 000
12
CtoAo - A7
81oAe,-AJS
1
X X X X
I
111011"01 ED
10 100 010 A2
"
CloA(j - A7
BIoAa - AI5
I
X X X I
I
II 101 101 ED
10 110010 B2
21
eloAQ._ A7
810Aa - AI5
(n}-A
(C)-r
OUTI
(e)- (HL)
8 - B-1
HL-HL+I
(CJ-IHU
S - 8-1
HL-HL+l
vnul
X
1
X X X X
I
11101101 ED
10101010 AA
I
I
X X X X
I
II 101 101 ED
10111010 SA
..
X
•
I
•
I
•
Ie) -IHL)
8 - 8-1
HL-HL-I
•
N
H&N
I.
c
5
(Uh,O)
•
I.
CIoAo - A7
BIoAa - AI5
21
_
PlY II
X
X
eloAo-A7
BIoAa-AI5
C
................. .
" HI
1
uo...
ayw. 0ydeI; .......
II 101 101 ED
10111011
5
21
"-e 10 Ao - A7
BtaAs-At5
IDB_O)
',"
"V
Z
1
..
..
C
x
X
XI,
X
1
X
1
1
X
X
1
0,
g g}
~
x
0
X
I
,
X
X
X
X
0
0
,
X
X
1
1
X
X
0
1
,
X
X
P
()
I
1
1
X
X
X
X
X
X
X
0
X
0
1
1
X
P
P
•
x a
X
a'
X
X
X
X
X
X
X
X
1
X
X
X
, ,
X ,
X
X
,
X
x
X
x
X
II
x,
0
X
0
X
x
1
0
0
0
1
IFF
X
1
1
---
S·b,' add or add WIth carry.
B·b,t mblr4Ct, aublrac:t With carTJ".
and MQaie lIIcc:um.ulalor.
a bllincrefllllni.
a·blt decremlllnt.
16bltlldd
16·bltlKid wlthearry.
Ift·blt,ubtr4Ctwilhcarry.
lIot4l11o.ccumuw.tor
Rotalll o.nd vult 1000Ilon•.
Rot4111 doQ11 Lelt and rlQht.
Dec,ft'lll .dlu,1 4ccumuialor.
CompLeru.nl accumuialOr.
Selc:arry
Complemant <:IIIrry.
Inpulrwq,_rtnd,rec!.
1
1
:}
81oc:1r. mput end output. Z • 0 II 8 ... 0 olhlllrw. . Z _ O.
0
0
:}
81oc:1r. traneier InIlruc"ho.... PlY .. I II BC ... O. ot:herw. . PIV - O.
1
81ocl:. _reh InlltrudlOl1&. Z .. 1 II A _ (HL). otMrwl.. Z _ o. PlY _ I
Ii Be ... O. otharw... P/V _ O.
T"" contlllnt of the tnte~rupt lllnable fhp·llop (IFF) .. COJHIId IDIo It. P/V 1I.q.
The Mill! 01 bl' b 01 1oc4hon 1 " copied trllo the Z I~
Operatl_
Sign
S "'" 1 If the MSB 01 the result is 1.
Zero flag. Z = I if the result of Ihe oper"lion IS O.
P",rdy or overllow fl(u;~. Panty (P) and overflow
(V) share the S4me flag. LOCJlcal oper",hons affect
thiS !lag with the p4rtly 01 the result while
arithmetic oper4tlons affect thiS flag with the
overflow altha result. 11 PlY holas p4nty. P/V ::::
1 II the result of the oper"hon IS even, P/V :::: 0 il
result lit odd. tJ PlY holds overllow. 'P/V :z 1 If
the result 01 the operallon produced an overllow.
HaH·c",rry 114'1. H :::: 1 II the ",dd or sublr",ct
operation produced 4 catTy mto or borrow lrom
bit 4 01 the dccumuldtor.
Add/Subtract
N :: 1 If the preVious oper&hon was a subtract.
H "nd N
are used an conjunctla"n with the
decirDtll adjust Instruction (DAA) to properly correct the result into packed BCD fOrm"t following
",dddion or subtr.schon uSing operands with
pdcked BCD form"!.
Carry/Link flag. C = I if the oper"'tion produced
a carry from the MSB 01 the oper",nd or result.
n"g.
Q;ll"tlpoN
loc;lcalopillratlOllll
Symbol
I
o
1
X
V
n"q.
n"qs
R
()pe.
16-blt value In ranqe < O. 65535 > .
I.
U 010011 D3
n II 101 101 ED
01 r 001
II
I.
CIoAo - A7
810-'8 - AI5
21
eloAo - A7
SIoAa - AI5
X
I
X X X X
I
11 101 101 ED
10 100 011 A3
I
I
X
I
11101101 ED
10110 ell 8l
a.....
a.o
OUTD
5
{!f8ttOJ
X
(liB_D)
(l)
CT'.
"15
{IJ R-OJ
-,....,
B·O
OUT (C). r
mAs -
(l)
HL-HL-I
DUr(n}·A
Ac<:.
(l)
8.0
DID
'H
X
1
H
X
",16
iU S .. OJ
•
ADD A .• : AOC A .•
SUB •. sse A. I. CP •. NEG
AND.
OR I. XOR.
INC.
DEC.
ADD DO...
ADCHL...
SBC HL . •
RLA. IILeA. RRA. RRCA
RL m. RLC m, RR m;
RRC m. SLA m;
SCF
II
...... ,..........
(SP-21-
I
DM
10
lIlT
"sr.
I
x
SJlA m, SRL m
RLD. RRD
11 001 001 C9
CClat_
IlErNI
ap.r.u-..
Ie) - (HW
8-B-1
HL-HL-I
R-,...Iunld
B • 0
CPL
U .........
IIETI
10
-ISP+l)
.........
---.
BIT~
•
17
II cc 100
X •
<:Au. ..
BIT
OTDII
III" O.
..-.tt._Ul .... ..-u........... --..
. . . . . . . . . hfa·l~nll. . . Ullhe,."..< -Ill. Ill',
. - l l............. _ _ _ _
.. _'*_"'pe . . . . PC ..
CaDCIIICI
........ Groap
"-Ie
UJ. O.
- .-2-
UB.O,
1I011S: •
.............
Output Group
(Continued)
X X X
12
5
IUS ... OJ
•
I.
nloAo - A7
Ace. 10 As - AI5
CIoAo - A7
BIoAa - AI5
IUB-OJ
•
CD
1
I
X X X
Il01"l: (i)11 .... ~afl-I .. _tt.ZU'OIll ..........._II
I
II 101 101 ED
10 101 011 A8
I.
CIoAo - A7
810 As - AI5
.. _ .
4
~
~
~
18410
~
zaer DNA DIrect
Me..ory Aceess Co.troller
Zilog
F_......
...!
D::
",,:{,
.::s{
Pin
DeKrlpUOD
this DMA la the addressed port il its CE pin
and its WR or RD pins are simultaneously
active. As an output, alter the DMA has taken
control 01 the system buses, it indicates that
the 8-blt or 16-blt address bus holds a valid
port address for another I/O device involved in
a DMA transler 01 data_ When 10RQ and Mi
are both active simultaneously, an interrupt
acknowledge is Indicated .
MI. Machine Cycle One (input, active Low).
Indicates that the current CPU machine cycle
is an instruction fetch. It is used by the DMA
to decode the return-from-interrupt instruction
(RETI) (ED-4D) sent by the CPU. During twobyte instruchon fetches,
is active as each
opcode byte is letched. An Interrupt acknowledge is indicated when both
and
.fORO are active.
MREQ. Memory Request (output, active Low,
3-state). This indicates that the address bus
holds a valid address for a memory read or
write operation. After the DMA has taken control 01 the system buSes, it indtcates a DMA
--...
,y...
}='
Ao-Als, System Address Bus (output, 3-state).
Addresses generated by the DMA are sent to
both source and destination ports (main
memory or I/O peripherals) on these lines.
BAl. Bus Acknowledge In (input, active Low).
Signals that the system buses have been
released for DMA control. In multiple·DMA
configurations, the BAI pin of the highest
priority DMA is normally connected to the Bus
Acknowledge pin 01 th"e CPU. Lower-priority
DMAs have their BAI connected to the BAO 01
a higher-priority DMA.
BAO. Bus Acknowledge Oul (output, active
Low). In a multiple-DMA configuration, this
pin signals that no other higher-priority DMA
has requested t' " system buses. sAl and BAO
form d daisy clidin for multiple-DMA priority
resolution over bus control.
BUSREQ. Bus Request (bidirectional, active
Low, open drain). As an output, it sends
requests lor control of the system address bus,
data bus and control bus to the CPU. As an
input, when multiple DMAs are strun2..~ther in a priority daisy chain via BAI and
BAO, it senses" when another DMA has
requested the buses and causes this DMA to
refrain from bUB requesting until the other
DMA is finished. Because it Is a bidirectional
pin, there cannot be any bullers between this
DMA and any other DMA. It can, however,
have" buller between it and the CPU because
it is unidirectional Into the CPU. A pull-up
resistor is connected to this pin.
Chip Enable and Wail (input,
active Low). Normally this functions only as a
CE line, but it can also be programmed to
serve a 'WXIf function. As a CE line from the
CPU, it becomes active when WI! and iOl\O
wwm.
are active and the liD port address on the
system address bus is the DMA's address,
thereby allOWing a transfer of control or command bytes from the CPU to the DMA. As a
WJ!JT line Irom memory or 110 deVices, alter
the DMA has received a bus-request acknowledge from the CPU, it causes wait states
to be inserted in the DMA's operation cycles
thereby slOWing Ihe DMA to a speed that
matches the memory or I/O device.
m
m
CLK. System Clock (input). Standard l-80
Single-phase clock at 2.5 MHz (2-80 DMA) or
4.0 MHz (2-80A DMA). For slower system
clocks, a TTL gate with a pullup resistor may
be adequate to meet the timing and voltage
level specificdtion. For higher-speed systems,
use a clock driver with an active pullup to
meet the VIH specification and risetime
requirements. In all cases there should be a
resistive pullup to the power supply of 10K
ohms (max) to ensure proper power when the
DMA is reset.
Du-Dr. System Dolo Bus (bidirectional,
3-state). Commands Irom the CPU, DMA
status, tmd data from memory or liD
peripherals are transferred on these lines.
Programming
lEI. Interrupt Enable In (input, active High).
This is used with lEO to lorm a priority daisy
chain when there is more than one interruptdriven device. A High on this Hne indicates
that no other device of higher priority is being
serviced by a CPU interrupt service routine.
lEO. Interrupt Enable Out (output, active
High). lEO is High only il lEI is High and the
CPU is not servicing an interrupt from this
DMA. Thus, this Signal blocks lower-priority
devices from interrupting while a higherpriority device is being serviced by its CPU
interrupt service routine.
INT/PULSE. Interrupt Requesl (output, active
Low, open drain). This requesta a CPU interrupt. The CPU acknowledges the interr~ by
pulling its 10RQ output Low during an MI
cycle. It is typically connected to the INT pin
01 the CPU with a pullup resistor and tied to
all other INT pins in the system. This pin can
also be used to generate periodic pulses to an
external device. It can be used this way only
when the DMA is bus master (i.e., the CPU's
BUSREQ and BUSACK lines are both Low
and the CPU cannot see interrupt.).
10RQ. Input/Output Request (bidirectional,
active Low, 3·.tate). As an Input, this Indicates
that the lower haU 01 the address bus holds a
valid 110 port address lor transfer of control or
status bytes Irom or to the CPU, respectively;
The 2-80 DMA has two programmable lundamental states: (l) an enabled state, in which
it can gain control of the system buses and
direct the transfer of data between ports, and
(2) a disabled state, in which it can initiate
neither bus requests nor data transfers. When
the DMA is powered up or reset by any means,
it is automatically placed into the disabled
state. Program commands can be written to it
by the CPU in eithpr state, but this auto~
matically puts the DMA in the disabled stale,
which is maintained until an enable command
is issued by the CPU. The CPU must program
the DMA in advance of any data search or
transfer by addressing it as an 110 port and
sending a sequence of control bytes using an
Output instruction (such as OTIR for the
2·80 CPU)"
Writing... Control or command bytes are written into one or more of the Write Register
groups (WRO- WR6) by lirst writing to the base
register byte in that group. All groups have
base registers and most groups have additional
associated registers. The associated registers
in a group are sequentially accessed by first
writing" byte to the base register containing
register-group identification and pointer bits
(1's) to one or more of that base register's
associated registers.
This is illustrated in Figure 8b. In this
figure, the sequence in which associated
registers within a group can be written to is
shown by the vertical position of the aSSOCiated
registers. For example, if a byte written to the
DMA contains the bits that identily WRO (bits
DO, DI and D7), and also contains j's in the
bit posHians that point to the associated "Port
A Starting Address (low byte)" and "Port A
Starting Address (high byte)." then the next
two bytes written to the DMA will be stored in
these two registers, in that order.
5
transfer request from or to memory.
111). Read (bidirectional, active Low, 3-state).
As an input, this indtcates that the CPU wanta
to read status bytes lrom the DMA's read
registers. As an output, alter the DMA has
taken control 01 the system buses, it indicates a
DMA-controlled read "Irom a memory or 110
port address.
RDY. Ready (input, programmable active Low
or High). This is monitored by the DMA to
determtne when a peripheral device aaaoctated
WIth a DMA port ta ready lor a read or wrtlt>
operation. Depending on the mode 01 DMA
operation (Byte, Burst or Contlnuoua), Ihe RDY
line indirectly controls DMA activity by causing the BUSREQ line to go Low or High.
WIt Write (bldtrectlonal, active Low, 3-state) .
As an input, this indicates that the CPU wants
to write control or command byte. to the DMA
write registers. As an output, alter the DMA
has taken control of the system buses, "it
indicates a DMA-controlled write to a memory
or 110 port address.
Reading, The Head Registers (RRO-RR6) are
read by the CPU by addreSSing the DMA as an
110 port using an Input instruction (such as
INIR lor Ihe 2·80 CPU). The readable bytes
contain DMA status, byte-counter values, and
port addresses since the last DMA reset. The
registers are always read in a fixed sequence
beginning with RRO and ending with RR6.
However, the register read in this sequence is
determined by programming the R'ead Mask in
WR6. The sequence 01 reading is initialized by
writing an Initiate Read Sequence or Set Read
Status command 10 WR6. Alter a Reset DMA,
the sequence must be imtialized. with the
Initiate Read Sequence command or a Read
Status command. The sequence of reading all
registers that are not excluded by the Read
Mask register must be completed before d new
Initiate Read Sequence or Read Status
command.
Flx..t·Addr_ ProgrammlDIJ. A special cir·
cumstance arises when programming a desH·
nation port to have a fixed address. The load
command in WR6 only loads a fixed address te>
a port selected as the source, not to a port
selected as the destination. Therefore, a fixed
destination address must be loaded by temporarily declaring it a lixed-source address
and subsequently declaring the true source as
such, thereby implicitly m.aking the other a
destination.
•
The following example illustrates the steps in
this procedure, assuming that transfers dre 10
occur from a variable-address source (Port A)
to d fixed-address destination (Port B):
I. Temporarily declare Port B as soUrce in
WRO.
2. Load Port B address in WR6.
3. Declare Port A dS source in WHO.
Programming
(Continued)
4. Load Port A dddress 10 WH6.
5. Enable DMA
INT~':UE;r":~!.~) !
R.ad ftegiater 0
D,
D.
(I,
I .. ,
0,
D, D.
I
II
n.
D.
I x I
I
I
..
STATUS 'HE
I L-, l:".o,,"U""
... saCCOIHIED
- READY AClIVE
:
Zilog
J.. STOil' 0" IIAICH
:
.
Features
I I II I I I
~o
Z8420
Z80~ PIO Parallel
Input/Output Controller
~
Writ. R.glalw 3 Gro,,"p
WR6.
Jtl
110-11,. Pori B Bus (bidirectIOnal, 3-state). This
11111,11( IYT£!O .. COMP .. IIIEI
8-bit bus transfers data, status, or control
information between Port B a.nd a. peripheral
device. The Port B data bus can supply
1.5 rnA at 1.5 V to drive Darlington transistors.
So is the least slgnific,?-nt bit of the b~s.
L==~==: :1i;~~~luPENDltjG
Il • fND OF Il~~
aeadR.gtslerl
Writ.
l---r---l 11-
TT]IYTECOUNTEfillOWIYlEl
f. CUogp
IYTE COUNTER tltlGH IYTE)
'"'~~:!
CONO"ItOQIlAI
,~
Roo.d Regillt«'"
T
I"OIIT I STARTING "OORIII
ILOWOYTlI
~~~~ ~~~~~£U COUNTER
T ITTJ
O
i
CI : : I t i l I ;o.!!::r:"EI>SCOUNTEIl
WrtleKegt.t.OGrov.p
...ll I !.L
lNTIl:JlinU'T ON RI
STAYUI AFFECTa VI :CIOIII .. ,
~:!~~~l
E':!
I .. 'ULSI! OiNEIIAUD
~:T~l~I(
I.T...RUPT {
CO.TftOL
0,0. 0,°.0,0,0,0"
ill .1_ t. I I I 1 'IUE IIEGII1'E" IYTE
/!!,, .,
1 _ I'OIIT
._1'0111',
I'OIIT A STAIIYlNG A£Kl.IIiEU
YICTOII IS AUYo...nC"LL Y
MODIFIED AS SHOWN
ONlY.f "SlAIUS
.."ft:cys ... t::CTOJliRIIIYIIIIIT
{I ! .
0
,
,
1
D
1
(lO.IYrE)
I'0Il1 A STARTING ADOREA
INTERRUPT ON lillY
.. INURIIIUPl 0"1 M.. TCH
.. INTEARU'l 01'1 END OF ILOCI(
_INTERRUPTONMAICI1
AN~ ENII Of IlOCK
Wrl,. ReglatlN"5Gra .. p
=~;.::=aTH
I' I n I I I 10 ill 01...SEAEOISTEIII_IYTf
A.EADY "'CliVE lOW
I _ llEADY ACTIVE MIGIH
/1D-C!O"lLY
Output Mode. ThiS Signal goes octive to indicate tha! the
Port A outpul register has been loaded and the peripheral
data bus IS stable and ready lor Iransler to the perIpheral
deVIce.
, - EWilf MULTIPLEXED
Write 8.giahlr I Group
Il, 0, U, 0, D, 0, 0,
10'
!
i
Il
:
,
~ : :1~~ ~:II~~~i'~'E~I(OF ILOCK
0"
)l!O[O!.ARIIEGIITEIII'TE
1 . I"OI'll .lIS uo
~ ::g:~: :gg:~::
~ ~ I-
n
~
II
0, 0, 0, 0, 0, 0,- 0, 0.
:g:EE:::::
100'" A"DOIIQ& FlliD
~
i
I,! I I
!, I, I USEMEGISTEIIIYTE
I I I I t _. <_.~u_
IIOORT ....... IIIA.LE TIMINO .YTIl:
II III I
GENOIl '!!. (;:YCLE EAJliLT
Input Mod•. ThiS signa} IS active when the Port A input
register IS empty and rsady to accept data trom the
'penpheral deVIce.
Writ. RegillllN" 6 Group
l.1'01I1AISMEMOIIl
n o .. CYCLE LUlIlTK .. ~
0 I a CYCLE U"IGllf .. l
: ~: ~c~n:Ttt
2
ill NOS '" CYCU EAIILY .. 1
..
IiiUiRi £NOCI '" CYCLE EAIILY "
o .. 1NIlli ENOS
v.
II
"
I
n;. Cl_ftIESH
,_ C7 ~ !IIESET POMT A TIMINO
0 ~ CI .. IIESH IOOftf I llMING
,
"
,,~O]
_
,
,
"
CYCU UJliU
"
1 _ Cf
Bidirectional Node. ThiS signal is active when data is
dvalldble m the Port A output rSQlsler tor t.ransler to the
perlpherdl deVIce. In thiS mode, data IS not placed on the
Pori A data bus, unless ASTB IS <'Jictlve.
~ LOAD
_ CONTlJoIUE
Conlrol Mod.. ThiS slgn",1 IS disabled and forced to a Low
st<'lte.
_"'f.
1
GIS .... lEI .. TEIIIIUPTS
"" .. I _ E .... lIlEINTEMflUPT5
0 ~ .. ) • RESET _111<10 OISAillE INTERRUPTI
I ~ 11 .. EN"ILE .. HEARElI
~
: :: ;
ASTB. Port A Strobe Pulse From Peripheral
Device (input, active Low). The meaning of
:~I~~r~:~~~Ss;!~~s DYTE
this signal depends on the mode of operation
selected for Port A as follows:
Wrlile a.p... 2 GtotIp
Dr Do 0. II. 0. 0. II, 0-
1.1 I I !
lolololUHltl;w~nlUYTI!
Il l.""',." .....,
l-fOIIIT . . . 1IO
,
•
•
•
t
~
~1
.. PORY I ADDAIU Dl!CIIIIIIENTa
.. JI'OfIT I ADOIIEN INCRlE1IPI11
.. PORf'AODM"FIli.IU)
II ! !.C~CL£LfNGTH"4
I I I I I I I
I
WlLNO&V.CYCU:IAllLT .. !
• DADe "" CTCU UN,y ...
~_I6C1'CUINILY.'
IJIOIrfIVAJlLdUTlIMCUYTi
Output Mod•. The posItive edge 01 thiS gtrobe IS issued' by
the perlpher<'ll to acknowledge the receipt of data made
aVllil<'lble by the PIO.
D I .. 17" ENIoILEDMA
" "" II" DlSAllEOIIA
~ I'! I I "
0
1
I
RegIster A Ready (output, active
H,igh). The meaning of this signal depends on
the mode of operation selected for Port A as
follows:
L
BlOCK LENGTH
IttICiIHIYTIE)
110-1.7' Port A Bus (bidirectional, 3-state).
This 8-bit bus transfers data, status, or control
information between Port A of the PIO and a
peripheral device. Ao -is the least significant
bit of the Port A data bus.
AHDY.
tHIGH lYrE!
0,0,11,0.0.,0,0,0"
I
8STB. Port B Strobe Pulse From PerIpheral
Devlce (input, active Low). Thls signal is
Pin
D..cription
00 Noruu:
m TRANSFlIl
• IlEAACH
-UAJlCl1ITfWIIIIFIUI
0-1"0111 I_I'OIITA
This Signal is similar to ARDY, except that in
the Port A bidirectional mode this signal is
High when the Port A input register is empty
and ready to accept data from the peripheral
device.
,
T-1 -[TJ :;.0;; :~:RESS COUNTEJI
R_d!logbleri
i Ii -iEIIA:A:::s:~:L~::A'lEI
IIII ~L-"A,",""
Input Mode. The strobe is issued by the peripher<'Ji1 to iO<'ld
data lrom the peripheral mlo the Port A input register.
Ddla 15 loaded mto the PIO when thil> Signal is active.
'---== IYTE
on. COUtu;::"
<.,",," "'.w
on"
IHllliK DYTEI
POI'I! A ADDRESS (LOW ITTEt
1'0111 A ADOIIIE" \HIQI1IYTlEt
Bidirectional Mod•. When thiS sigMI is active, data lrom
the Port A output register 18 gated onlo the Port A bidirecbOMI data bus. The posihve edge 01 the strobe ocknowledges the receipt 01 the d.ata.
1'0111' I AIHIRES.,lO. IYTEI
~T I ADOIIIUS (MIG" IYTlI
•
' " CYCLE l.aJtllTH .. a
".CTCLfLeNGTH_1
I 1
DOJeOfU8l!
, .. i:RIQ\"'V.CYCLIUN.Y
Conlrol Nod•. The strobe
II
inhibited internally.
Slmildr to ASTB, except that In the Port A
bidirectional mode this signal strobes data
from the peripheral device into the Port A
input register.
C/O. Control Or Dota Select (input,
High = C). This pin defines the type of data
transfer to be performed between the CPU and
the PIa. A High on this pin during a CPU
write to the PIO causes the Z-80 data bus to be
interpreted as a command for the port selected
by the B/X Select line. A Low on this pin
means that the Z-80 data bus is being used to
transfer data between the CPU and the PIO.
Often address bit Al from the CPU i. used for
this function,
CEo Chip Enable (input, active Low). A Low
on this pin enables the PIO to accept com·
mand or data inputs tram the CPU during a
write cycle or to transmit data to the CPU dur,ng d read cycle. This signal is generally
decoded from four lIO port numbers for Ports
A and B, data, and control.
CLI[. System Clock (input). The Z-80 PIO uses
the standard singleR phase Z-80 system clock..
Do-07.
ZBD CPU Dota Bus (bidirectional,
3-state). This bus is used to transfer all data
dnd commands between the Z-80 CPU and the
Z-80 PIO. Do is the least significant bit.
lEi. Interrupt Enable In (input, active High).
This signal is used to form a priority-interrupt
daisy chain when more them one interruptdriven device is being used. A High level on
this pin indicates that no other devices of
higher priority are being serviced by a CPU
interrupt service routine.
FISJ1II'e lb. Wdt. Reg. . . .
6
/~
B).
BHDY. RegIster B Ready (output, active High).
,0lllY!J sr .. JlillHO .. OOllEII
[HIIlH IYTI!)
R_dRegbIW.s
=
This pin defines which port is accessed during
a data transfer between the CPU and the PIO .
A Low on this pin selects Port A; a High
selects Port B. Often address bit AI:J from the
CPU is used for this selection function.
CONTINUO'
Rtoad Regilll ... 3
I i ! ' ! I I I I ~~:y~:flEi5COUHTER
r-
B/A. Port B Or A Select (input, High
.~::! !
Re (41'8 with a 4 MH~ clock). The
maximum timer interval is 256 x r; x 256 (16.4 ms
with a 4 MHz clock). For longer intervals
timers may be casCaded.
laterrupt Vector. Progr-DIJ. If the Z-80
eTC has one or more interrupts enabled, it
can supply interrupt vectors to the Z-80 CPU.
To do so, the Z-80 CTC must be pre-programmed with the mast-significa~t five bits of
the interrupt vector. Programming consists of
writing a vE!clor word to the 1/0 port corresponding to the Z-80 CTC Channel O. Note
that Do of the vector word is al.,-ays zero, to
distinguish the vector from a channel control
word. DI and D2 are not used. in programming
the vector word. These bits are supplied by
the interrupt logic to identify tbe channel
requesting interrupt service with a unique
interrupt vector (Figure 7). Channel 0 has ihe
highest priori~y.
"'T_O._~"
0 .. VECTOR
[D>[..jiiJ 0.1 0,1 .. 10.1 .. 1
1 .. CONTROL WORD
~NTlHUED
DI'E.....T1ON
1 _ SOFTWAIIE I!IESEr
~~~~~
TlllaC:ORST••T
a .. NO TIME CONSTANT FOLLOWS
1 _ TIME CONSTANT fGU.OWS
nMmI ........ •
~ .. ::E:c,.~:~IEL~:;::
L-
rq.. !.. lo.! .. !.. I°,J .. 1
.......
VJ-Va-.J
· ·SUI"PUlD
L 0• _TIEtIIWI'T ';n.WORD
1 - COtITIKI&. WCMlD
CHAMNELlOENTlAEtI
(AUTa.A1lCaU'f tllllEllTI!D
.'CTCIc....
N..
n.
•
0_
•
1 _ CH"NNELl
, a. CHANNR!
1·1. CttAtINElI
1 .. CLKIllIa PULSE sr..IITS TIMEfi
"TIMUMODEONLY
Fl_l.
Fl_ 5.
n_ Coutaat Ward
........ 7...-.opt V _ Wo«i
C........l CoaIrol Wo«i
8
~
~
~
Z8440
~
Zilog
Pin
DftcrlplioD
(Continued)
ZSfr 110 Serial
mput/Output ConlroUer
f eatur..
""
r--- -
".~
l..fl..-
ilt.n~
CU:. Syslem Clock (input). The SIO uses the
standard l-80 System Clock to synchronize
internal signlll5. This is a single-phase clock.
CTSA, CTSB. Clear To Send (inputs, active
Low). When programmed as Auto Enables, a
Low on these inputs enables the respective
transmitter. If not programmed as Auto
Enables, these inputs may be programmed as
general-purpose inputs. Both inputs are
Schmitt-trigger buffered to accommodate slowrisetime signals. The SIO detects pulses on
these inputs and interrupts the CPU on both
logic level transitions. The Schmitt-trigger buffering does not guarantee a specified noiselevel margin.
.-....
.~
...., {
CM"-rtI
"TaMtU"
CC*TMK.
Pili
o-alptioD
RxCA, RxeB. Receiver Clocks (inputs),
Receive data is sa.mpled on the rising edge of
RxC. The Receive Clocks may be I, 16,32 or
64 times the data rate in asynchronous modes.
These clocks may be driven by the 2-80 CTC
Counter Timer Circuit for programmable baud
rate generation. Both inputs are Schmitt·
trigger buffered (no noise level margin is
speCified).
In the 2-80 510/0 bonding option, RxCB is
bonded together with TxCB.
Do-o,.
.
Figures I through 6 illustrate the three pin
configurations (bonding options) available in
the SID. The constraints of a 40-pin package
make it~sBible to bring out the Receive
Clock (RxC), Transmit Clock (TxC), Data Ter-
minal Ready (DTR) and Sync (SYNC) signals
for both channels. Therefore, either Channel B
lacks a signal or two signals are bonded
together in the three bonding options offered:
SYNCB
lacks i5TRl'i
• 2-80 SI0/2 lacks
• 2-80 slon
• 2-90 SIOIO has all four signals, but TxCB
and RxCB are bonded together
The first bonding option above (SI0/2) is the
preferred version for most applications. The
pin descriptions are as follows:
B/A. Channel A Or B Selecl (input, High
selects Channel B). This input defines which
channel is accessed during a data transfer
between the CPU and the SIO. Address bit Ao
from the CPU is often used for the selection
function.
C/O. Conlrol Or Data Select (input, High
selects Control). This input defines the type of
information transfer performed between the
CPU and the SIO. A High at this input during
a CPU write to the SIO causes the information
on the data bus to be interpreted as a command for the channel selected by B/A. A Low
at C/O means thdt the information on the data
bus is data. Address bit Al is often used for
this function.
CE. Chip Enable (Input, acllve Low). A Low
level at this input enables the S10 to accept
command or data input from the CPU during a
write cycle or to transmit data to the CPU
during a read cycle,
BIA, C/O, CE and RD to transfer commands
and data between the CPU and the SIO. When
CE, RD and 10RO are all active, the channel
selected by B/A. transfers data to the CPU (a
read operation). When CE and 10RO are
active but RD is inactive, the channel selected
by BIA. is written to by the CPU WIth either
data or control information as speCified by
C/O. If 10RO and Ml are aclive simult"neously, the CPU is acknowledging an interrupt
and the SIO automatically places its interrupt
vector on the CPU data bus if it is the highest
priority device requesting an interrupt.
Mi. Mochme Cycle (input from 2-80 CPU,
active Low). When M1 is active and RD is also
active, the 2-80 CPU is fetching an instruction
from memory; when M 1 is active while IORQ is
active, the SIO accepts MI and 10RQ as an
interrupt <'!cknowledge if the SIO is the highest
priority device that has interrupted the 2-80
CPU.
System Data Bus (bidirectional,
3·state). The system data bus transfers data.
and commands between the CPU and the 2-80
SIO. Do is the least significant bit.
DeDA. DeDS. Dolo Carrier Delect (inputs,
active Low). These pins function as receiver
enables if the SIO is programmed for Auto
Enables; otherwise they may be used as
general-purpose input pins. Both pins are
Schmitt-trigger buffered to accommodate slowrisetime signals. The SIO detects pulses on
these pins and interrupts the CPU on both
logIC level transitions. Schmitt· trigger buffering does not guarantee a speCific noise-level
margin.
RD. Read Cycle Status (input from CPU,
active Low). If R5 is active, a memory or 110
re~d ~ration.J.~r: progress. RD is used with
BI A, CE and 10RO to transfer data from the
510 to the CPU.
RxDA. RxDB. Receive Dala (inputs, active
High). Serial data at TTL levels.
RESET. Resel (input. active Law). A Low
DTfIA. DTRS. Data Termmal Ready (outputs,
active Low). These outputs follow the state programmed into 2·80 SIO. They can also be programmed as general· purpose outputs.
In the 2-80 SIOII bonding option, DTRB is
omitted.
RESET disables
both receivers and transmitters, forces TxDA and TxDB marking, forces
the modem controls High and disables all
interrupts. The control registers must be
rewritten after the SIO is reset and before data
is transmitted or received.
lEI. Interrupt Enable In (input, active High).
ThIS signal is used with lEO to form a priority
daisy chain when there is more than one
interrupt-driven device. A High on this line
indicates that nO other device of higher priority is being serviced by a CPU interrupt service routine.
RTSlI.. RTSB. Request To Send (outputs,
aclive Low). When the RTS bit in Write
Register 5 (Figure 14) is set. the RTS output
goes Low. When the RTS bit is reset in the
Asynchronous mode, the output goes High
after the transmitter is empty. In Synchronous
lEO. Interrupt Enable Out (output, active
High). lEO .. HIgh only if lEI IS High and the
CPU is not servicing an interrupt from this
510. Thus, this signal blocks lower priority
devices from interrupting while a higher
priority device is being serviced by its CPU
interrupt service routine.
modes, the RTS pin strictly follows the state of
the HTS bit. Both pins can be used as generalpurpose outputs.
SYNCA. SYNCS. SynchronizatIOn (inputs/outputs, active Low). These pins can act either as
inputs or outputs. In the asynchronous receive
mode, they are inputs similar to CIS and
DCD. In this mode, the transitions on these
lines affect the state of the Sync/Hunt status
INT. Inlerrupt Request (output, open drain,
active Low). When the SIO is requesting an
interrupt, it pulls INT Low.
IORQ. Input/Ql1lput Request (input from CPU,
active Low). IORQ is used in conjunction with
9
bns in Read Register 0 (Figure 13), but have
no other function. In the External Sync mode,
these lines also ect 6£1 inputs. When external
synchronization is achieved, SYNC must be
dri ven Low on the.second fialQQ edge of RxC
after that rising edge of lixL: on which the last
bit of the sync character was received. In
other words, after the sync pattern is detected,
the external logiC must wait for two full
Receive Clock cycles to activate the SYNC
input. Once SYNC is forced Low, it should be
kept Low until the CPU informs the external
synchronization detect logic that synchroniza.-tion has been lost or a new message is about to
start. Character assembly begins on the rising
edge of RxC that immediately precedes the
foiling edge of SYNC in the External Sync
mode.
In the internal synchronization mode
(Monosync and Bisync), these pins act as outputs thd.t are active during the pc"Irt of the
receive clock (RxC) cycle, in which sync
characters are recognized. The sync condition
is not latched, so these outputs are active each
time a sync pdttern is recognized, rega.rdless
of character boundo.ries.
In the Z-BO SI0/2 bonding option, SYNCB
is omitted.
T;;CA.
Transmiiter Clocks (inputs). In
asynchronous modes, the Transmitter Clock.s
may be I. 16. 32 or 64 times the ddta rate;
however, the clock multiplier for the transmitter and the receiver must be the same. The
Transmit Clock inputs are Schmitt-trigger buffered for relaxed rise- and fall-time requirements (no noise level margin is specified).
Transmitter Clocks m.y be dMven by the 2-80
CTC Counter Timer Circuit for programmable
baud rate generation.
In the Z-BO SIOm bondlnQ option, ~ Is
bonded l&1elhei' 'WIth !!XL:n.
bDA, TxDB. Transmil Dala (outputs, active
High). Serial data .t TTL levels. TxD changes
from the falling edge of TxC,
W/RDYA, W/RDH. Wail/Ready A, Waif!
Ready B (outputs, open drain when programmed for Wait function, driven High and
Low when programmed for Red.dy function).
These dual-purpose outputs may be programmed as Ready lines for a DMA controller
or as Wait lines that synchronize the CPU to
the SIO data rate. The reset state is open
drain.
r;cs.
Programming'
The system program first issues d series of
commands that initialize the basic mode of
operation and then other commands that
qualify conditions within the selected mode.
For example, the asynchronous mode,
character length, clock rate, number of stop
hits. even or odd parity might be set first; then
the interrupt mode; dnd finally, receiver or
transmitter enal!e.
Both channels contain registers that must be
programmed via the system program prior to
operation. The chdIlnel-selecl input (B/A) and
the control/data input (ClDi are the command·
structure addressing controls, and aTe normally controlled by the CPU address bus. Figures
15 and 16 illustrate the timing relationships for
programming the write registers and transferring data and status.
Read Reglat.... The SIO ccntains three read
registers for Channel B and two read registers
for Channel A (RRO·RR2 in Figure 13) that can
be read to obtain the status information; RH2
cont~ins the internally-modifiable inter'rupt
vector and is only in the Chdnnel B register
set. The status information includes error conditions, interrupt vector and standard
communications-interface sign.lls.
To read the contents of a selected read
register other than RHO. the system program
must- first write the pointer byte to WHO in
exactly the same· way as a write register .operation. Then, by executing a read instruction,
the contents of the addressed read register can
be read by the CPU.
The status bits of RRO and RRI are carefully
grouped to simphfy status monitoring. For
example. when the interrupt vector indicates
that a Special Receive Condition interrupt has
occurred, all the appropriate error bits can be
read from a single register (RRl).
Write Regtaten. The SIO contains eight write
registers for Channel B and seven write
WRO is a special case in that all of the basic
commands can be written to it with a single
byte. Reset (mternal or external) imtializes the
pointer bits Do-D2 to point to WRO. Th,s
implies that a channel reset must not be combined WIth the pointing to any register.
ProgrlllllDllDII
(Continued)
WRITE REGISTER 0
WRITE REGJStER "
10" .. 1.. 10.\ .. 1.. 10,1 .. ,
,t ,I IIEOISTEIIO
,,, 0,, IIEGISTEII1
IIEGISTER:
AEOISTEAJ
,, ,, REGISTEIiI
,, ,, :::::~~::
MEG!aTf.II1
10,10.'0.1 0.1 .. 1.. 10,1 .. 1
o
READ REGISTER 0
0
0
,
0
1
0
I I L -..
AAITYEN .... I.L.
..IdIIITYEVENIODD
D SYNC MDDCS ENULE
1 1STOfOSITICHAI'I...CTEII
1'It STOP8ITSlCKA,,",CTEIII
1 2 STOP BlTIICHAJlACTEII
o
~ ~IS~~TS;~;CC::~
NULLCC
SENOAI OAT (SDt.Q
IIESETI! 'ISTAruIUrfTEIIIWI"TI
o
.....
! : f E:r~
(I
1.. 10.1 .. 10.1 0,1 .. 10,1 .. 1
o
1
L..==
1111 ~t
.L-••
INTCH
PEHOING ICH .... OHL VI
,""'"''''''''''
Ta SUFFEIIEII~TY
~:Cl"UNT
:
o
}
C"
,
o
TaUNDEIiRUNlEOIi
SfiEAlUA&C)IIT
1
~ ~
::r"8:': '"
IlOMINTICH-ADNLY)
NULL CODE
IIf.SET II. CIIC CHECKER
IIflET T. CRC dENfUTDA
IIINT T. UNOERNlNIEOII UTCH
·Vs.eDW,tn hleonallSla'us
Inl."U(lII/lOCle
READ REGIStER It
III
L-AC"EN'
.!: '..::
~
,
,
,
D
~
~AIIITYfllIlO.
II. OVEIIIWN EItROR
CIlCIFIlAIIINGEliItOIt
I!NDOFFIIAIIEIIDLCi
TUHd
W'Ih-5pe-t,,,~.,,,
TV'''_~
STAT~
ICH.SONLY)
o ,
R. INT OH 'IIIIT CHAAACTP
, .0
!NT ON ALL
,
CNAllACTEIIII"AIIJTY AFFECTS YECTOII} }
INT 0loI ALL b CHAIlACTEIIS ",AIII" DOH NOT """ICT
·QooJn
IlEADV ON lIlT
EADVFUNCTlOlII
I
~~}~=~
WRITE REGIStER 2 (CKAIRIEL • OIU.Y)
WRITE REGIStER •
1.. 1.. '0.10.1 .. 1.. 10.1 .. 1
1111
J
~~~~ll}
WRITE REGIStER I
WlllTE REClSTEIl 7
' .. I~lo.l .. I.. I.. loN
1.. 10.10.1 .. 1.. 10.10.10.1
II.L.::::......"
~E~c.r.;!~~=:::.-g
L.~========~~III~~
FI....... '3. -Regia... III F...........
II. J"TSlCMA""CTEIII
1 Ib 7 'ITS/CHAMCTfli
II A. . . .TIICHAIIACTU
1 R•• 8IrliCHAIlAC-TUI
•
registers for Channel A (WRO- WR7 in Figure
14) that are programmed separately to configure the functional personality of the channels; WR2 contains the interrupt vector for
both channels and is only in the Channel B
register set. With the exception of WRO, programming the write registers requires two
bytes. The first byte is to WRO and contains
three bits (00-0:2) thai point to the selected
register; the 'second byte is the actual control
word that is written into the register to COl"'
figure the SIO.
Of •
1.. '.. 10.10.1 .. 1,,'0,1 .. 1
IIII
SlalUSAliltClS
o;P.og •• n ......
".r.'IITIIC~"
ConOollO'l
IIII~U~~-
Con",,_..-
L.
0 hS8ITSiOllLEUjlCHAIlACTIJI
•
, .,.7 8/TSlCH.. IIACTEII
l O T•• 8ITllCHoUIACtH
Spec ...1
i'JIEAOyEItAaLI
·Resollue DMlolfa, lO,gnl
R. B"..ch.'acle" Plog'~mmea
~
I ~i::::U
II -=======~~
o
E
,
[DtTo.TIi,It>, i~IDllo.lo.l
V.CIOI
ID.(o.lo.ID.I~ID,!D,!a.1
1
READ REGISTER 2
1111
WJU1'E REGISTER 5
.OIl.INT~LE
I FIELOsn,
IFIELDln.1N
)
IN ~IIf.VJOI3 HCOtoID HlEVJOUI
SYTl
SYVE
.D
WIU1'E REGISTEIl 1
10" .. 1.. \0.10.1 .. 10"0.1
L-.,,, .., •••OUE
~
L-=::f.INTEtlASU:
AFI'ICU VlCTCMI
~lli' ""'..., I I.
IDdo.!D.!o.lo,!o.lo,!DoI
IDLC MODt: (lHn no FLAGI
EXTERNAL SYNC IIOH
D .1 CLOCI( MOOI!
, XllCLOCKIIOH
• X:12 CLOCK MOot
, .... CLOC.. ~
:~To:.:ro.~b CHARACTEII
IVNC"f'
I"NC"TF
llll'~~~lli}
. lYtIC SIT'.
lYtIC lIT II
·FD-
"
..
A
...
"
"
[
....
L
R!I
CAT Il007
VAll- •
AOORESS BUS
VPAC·
oft
vg~'
51
\ll.T
•
Sl.'
~
0
R3 Ft2
Wl!m ~CKE"ClK
~
DIN 7~'
CRT!IOO6
SINGLE
ROW BUFFEA
'
I
4
1
1
B
U
S
OOUT1-'
(IE'
He
Rl R
CUFtSOR VSVNC
J
RETBl
LDISI'I
ATTRIBUTES
CAT IlOO2
YOAC"
o
J
'ct:tIt
C\J S
A
T
A
}i
-
CIII.ANI(
A
riDn
IG~~ORI
VDC
CI4AAACTERIATTRlIIUTElI
GENERATOR
1\7-'
TO
VIDEO
(
IoiONITOR
FIGURE 6: CRT 9007 CONFIGURATION WITH SINGLE ROW BUFFER
---,L-......-l:-----------(111----------_,
...__------__ .. ____
...._-..h!
n
I!-_ _----tl
~;-
VLT
•
I
I
I
eo _ _
,
I
'I:
""'-
I
I
l 11[:
.074 ~:
VA1~
lij~qij
~-
.
0
•
~I
jr-----------~---------------
!!
: \'1..____-;.-_________
.l
0: 0
•
liJI--~IM:::':P~~~AN~H=CE:::-r------
li,'L
i
0 0:: 0
.
I(CLOCKS
'CLOCKS
CURS:
_l)fj~tiJ:=:fl:a-vCURSOR AT 5TH CHARACTER POSITION :-4'1." IF 2XH OR :..-.n
(NO SKEW) ' - - - '
OR
n
5 CLOCKS:
2XW
'----~ ~~
c[&d i;
I
SL3-0
I
2XW
STABLE
COUNT~:
----..
II
STABLE COUNT
•
FIGURE 7: CRT 9007 SINGLE ROW BUFFER TIMING (32 CHARACTERS PER DATA ROW)
4
(
Double Row Buffer Operation
Figure 8 shows the CRT 9007 used in conjunction with a
CRT9212 Double Row Buffer. The Double Row Buffer has
a read buffer which is read at the painting rate of the CRT.
during each scan line in the data row. WhOe the read buffer",.·.,
is being read and supplying data to the character generator
for the current displayed data row, the write buffer is being
loaded with the next data row to be displayed. This
arrangement allows for relaxed write timing to the write buffer
as it may be filled in the time it takes for N scan lines on the
CRT to be painted where N is the number of scan lines per
data row. Used in this configuration, the CRT 9007 takes
advantage of the relaxed write buffer timing by stealing
memory cycles from the processor to fill the write buffer
(Direct memory access operation). The CRT 9007 sends
the DMAR (DMA request) signal, awaits an ACK (acknowledge) signal and then drives out on VA 13-VAO the address
at which the next video data resides. The CRT 9007 then
activates the WBEN (write buffer enable) signal to write the
data into the buffer. If for example there are 80 characters
per data row, the CRT 9007 performs 80 DMA operations.
The user has the ability to program the number of DMA cycles
performed during each DMAR-ACK sequence, as well as
PROCESSOR
the delay between each DMAR-ACK sequence, via the DMA
CONTROL REGISTER (RA): If 8 DMA operations are
performed for each ACK received, 10 such ~MAR-AC?K
seque.nces must be performed to completely fill the wnte
buff~r. The programmed ~elay allows the user to evenI)'
dlstnbute the DMA op~ratlons so as. not to h?ld up the process,?r for an excesslv~ length of time. This feature also
permits other DMA devlce~ tobe used and a!l~ws the processor to r~~pond ~o real time events. In addition, the ,:,ser
has the ~bllrty to dlsa.ble t~e. CRT 9OP7 DMA mechanls~.
Rgure 9 Illustrates typical timing for the CRT 9007 used with
the CRT 9212 Double Row Buffer.
Since the CRT 9212 Double Row Buffer has separate inputs
for read and write clocks (RCLK, WCLK), it is possible to
display proportional character widths (variable number of
dots per character) by reading out the buffer at a character
clock rate determined by the particular character. The writing of the buffer can be clocked from a different and constant character clock. Figure 10 illustrates the CRT 9007
used with two double row buffers and a CRT 9021 Video
Attributes Controller chip to provide proportional character
display.
INTRf---------------,
/lPi/IC
...C K I - - - - - - - . . . . ,
DM ...ROf------,
...ODR
OAT...
DMAR
MEMORY
...
RAM
VIDEO RAM
...
ROM
...ODRESS BUS
...
..
.
ACK
GND
INT
CRT 9007
YPAC·
V07-'
lWE
N IlRl!
SLD
VI T
B
U
1
!1m
lJ
...
...T
r!
CRTDOUBlE1212
-..JI., ... ,..
+5V
v""~,
o
5
111
RST
!
CURS
74378
~
J
aaac
~~.~~
DCIUT'''I--- l~~J1"'TTRIBUTES
y
__..:..j
CRT8OO2
"-----,.1>."IJ
IIE:.--_ ' - - _......11 ...7-.
~-----~
CHARACTER/...
GENERATOR
I
VDCI----.....
VDAC'·
TTRlBUTES
AOWBUFFER
I~~ORI
VlDEOI-------~ITOR
'----------~
FIGURE 8: CRT 9007 CONFIGURATION WITH DOUBLE ROW BUFFER
HS
---,L--J.. _____
--- . . ,r-"'---------------.
.
--L-Jr--______
~-
~T_,~
ORB--,~
~
_______
~-
~~--------··~U~--------------~
____________________________________
ACK ---l}-~
_______··~I
(
~
I
.... 16 OMA CYCLES -1.8 DELAY,,",
VA1~----~1J~~~~~~;t--------~Jn~~~~~~j-----------Bilili~-----------------VD7-8
x
x
x
WBEN
CURS
FIGURE 9: CRT 9007 DOUBLE ROW BUFFER TIMING (32 CHARACTERS PER DATA ROW)
(
INTR
PROCESSOR
ACK
DMARa
DATA
AD""
•
...
MEMORY
ROM
RAM
VIDEO RAM
:.
'"
,
..
DMAA
ACK
J.
.
INT
H!
V,,1M
r
ADDRESS BUS
CRT 9007-VPAC'"
-'"
'r---Y YO'"
.A..
'Ii
-y
,
D1N7"
SCAN LINE DATA
r
oy
......
I;lK
00\IT7..
CRT 9212
DOUBLE ROW BUFFER
-'"
..
,
WI;;
-'"
-'"
...
CHARACTER WIDTH
CHARACTER
ROM
"n·oM
r
L....J...,
-,I
CHARACTER ATTRIBUTES
...
• r
•
,t,,7 .. "
CRT 9021
VOC
r--
IHCl
ATTRIBUTES
VIDEO
VIDEO ATTRIBFRS
CONTROLl R
FIGURE 10: CRT 9007 CONFIGURATION FOR PROPORTIONAL CHARACTER DISPLAY
6
~
I-CHAR.
CODE
. ooun-l
CLOCK
GENERATOR
r----
CRT 9212
DOUBLE ROW BUFFER
DIN'"
TO
MONIT OR
=
BUFFER
CONTROLS
DATA
BUS
}
VI
TOMONITOR
(
Repetitive Memory Addressing Operation
In this operation mode, the CRT 9007 will repeat the
sequence of video addresses for every scan line of every
data row. The CRT 9007 address bus will enter Its high
Impedance state during all horizontal retrace intervals
(except the retrace interval at a data row boundary If the
CRT 9007 is configured ina row driven addressing mode).
This arrangement allows for such low end contention
schemes as retrace intervention (the processor is only
allowed access to video memory during retrace intervals)
and processor priority (the processor has an unlimited
access to video memory). A high end contention scheme
can be employed which uses a double speed memory such
that in a single character period both the processor and the
CRT 9007 are permitted access to video memory at predetermined time slots. Figure 11 Illustrates the CRT 9007
configured with a double speed memory. Typical timing for
this mode is illustrated in figure 12.
.
INTRI-.------------------,
PROCESSOR
"P/"C
ADORt--_ _. ,
DATA
D
A
ROM
RAM
l
n
II!
CRT 9007
VPACTM
VIDEO
RAM
}!
vs
~
CURS
CBLANI(
CURSOR
RETBL
ATTRIBUTES
DCLI(
..Il.rt.I1..Il.
U-L-
U
cct:R
n-.J
VIDEO
RAM
ADDRESS
n!
-::::::J.
rVPAC
X
PROCESSOR
X
VPolC
~ESSOA
'------,1/
A7.,
CRT 8002
VDACTM
CHARACTER/A ITRIBUTES
GENERATOR
VSYNC
VIDEO
TO MONITOR
~
DCLI(
CLOCK
GENERATOR
CCLI(
T1
T2
FIGURE 11: CRT 9007 CONFIGURATION WITH DOUBLE SPEED MEMORY
•
FIGURE 12: CRT 9007 REPETITIVE MEMORY ADDRESS TIMING (32 CHARACTERS PER DATA ROW)
7
Attribute Assemble Operation
This configuration allows the user to retain an 8 bit wide video
memory in which attributes occupy memory locations but
not positions on the CRT. This mode assumes that every
other display position In video memory contains an attr!· .
. buteo During one clock cycle, attribute data Is latched into
the CRT 9007; during the next clock cycle a character location Is addressed. The attribute data is driven out along with
a WBEN Signal allowing the character plus its associated
attribute to be written simultaneously to two 8 bit double row
buffers. Fi~ure 13 illustrates the memory organization used
for the Attnbute Assemble mode. The first entry in each data
row must begin with an attribute.
Figure 14 shows the CRT 9007 configured in'the Attribute
Assemble mode used with two CRT 9212 Double Row
Buffers and 8, 16Kx1 dynamic RAMS. This mode, since it
retains an 8 bit wide memory while providing all the advantages of a 16 bit wide memory, lends itself to some cost
effective designs using dynamic RAMS. The CRT 9007 will
refresh dynamic RAMS because twice the number of the
programmed characters per data row are accessed
sequentially for each data row. * Figure 15 illustrates typical
timing of the CRT 9007 used in the Attribute Assemble mode.
Memory Addr8III (typ)
Memory Data (8 bits)
uooo
AllrlluteO
0001
Character 0
0D02
AIIrbIte 1
0003
Character 1
o
o
o
0
0
0
2N
Attribute N .
2N+1
CharacterN
Figure 13: Attribute Assemble Memory Organization
·Note: For 50 Hz operation there usually is about 3 milliseconds extra vertical blanking where refreshing might fail. In this situation the
CRT 9007 can be programmed with about 5 more "dummy" data rows while extending the vertical blank signal. This allows
the CRT 9007 to start addressing video memory much earlier within the vertical blanking interval and hence provide reftesh to
the dynamiC RAMS. When displaying double height or double width data rows, only half as many sequential locations are
accessed each data row and dynamic RAM refresh might fail.
PROCESSOR
.... """"
,.
""TA
•
'"'"
DMAAC
-
I-r--_
IIQ
CQ
3"~~
(
lOT
~
"""
.
"""
1-'-
OM
A--~
RAMS
A
07..
Y
J..
,..
A
T
.(:
~'"
.
-v'
"""
OfT
""M
.
CRT 9007
VPAC fM
1107..
IlCll!
WIlEN'" VLT
CtJAS
Ill!
lUI
TO
MONITOR
"
'*-
"
B
U
S
............
~I
-
nr
C~T~ IICU
Mn
~""TA
-"OOUBl£ ROW BUFFER""""
(ATTRIBUTES)
II!
.J
1 t , t
J.-....
t t
VOEN--crr~1I!B IIIICIR
;t-4DOUBlE ROW BUFFER""""
(DISPlAy)
II!
YI
I
10
1111
'i~
. . . .t . . IIDa.....&..DtIR..,..
..
I
L. ....
'Q':" :'t
r
.....,...
...
CRT 8002
VDAC" .
CHARACTER/ATTRIBUTES
GENERATOR
FIGURE 14: CRT 9007 CONFIGURATION FOR ATTRIBUTE ASSEMBLE MODE
8
rM1
V IDOT~1
---J
.....
-
......,
GENERATOR
TO
Smooth Scroll Operation
Smooth scroll requires that all or a portion of the screen move
the data row that starts the smooth scroll interval. To allow
up or down an integral number of scan lines at a time. 2 user
complete flexibility in smooth scroll direction and rate, one
pr~rammable registers allow one to define the "start data
can update the offset register In the positive as well as negrow • and the "end data row" for the smooth scroll opera~ . ative direction and can also offset any number of scan lines
tIon. A SMOOTH SCROLL OFFSET REGISTER (R17).
each frame. Since a smooth scroll can momentarily result
when used in conjunction with a CRT 9007 vertically timed
In a partial data row consisting of one scan line, the loading
interrupt, allows the user to synchronize the update of the
of the write buffer under DMA operations for the start and
offset register to the vertical frame rate. The offset register
end data row of the smooth scroll operation is forced to occur
causes the scan line counter outputs of the CRT 9007 to
in one scan line. This condition ovenjdes the programmastart at the programmed offset value rather than zero for
ble DMA CONTROL REGISTER (RA).
~~r::::~·~'-~--~Q~""'''''''''''-VlT
1 ...._ _ _ _....
r _...............~n~-------
ORB --,....____.....___.....___..........___....................______.....___~r-.....---...............---..........~"~-------
ooo~
WBEN
• DMA cycles will always end at a character fetch
FIGURE 15: CRT 9007 ATTRIBUTE ASSEMBLE TIMING (32 CHARACTERS PER DATA ROW)
9
ADDRESSING MODES
Row Table Addressing
.ri
In this addressing mode, each data row in video memory is
designated by its own starting address. This provides greater
flexibility with respect to screen operations than with other
addressing schemes used by previous CRT controllers.· The
row table, which is a list ('jf starting addresses for each data
row, can be configured in one of 2 ways. The choice of row
table format is highly dependent upon the particular application and the programmer's preference since each format
allows full utili~ation of the CRT 9007 features,
T~~~ .
: l.
Row
Table
In
Memory
.~
'"
.,..:.. .....
~:...
C
.
o
. ."
E
I
:.,- .
. ..
..
F
0
0
0
lsi Char
2nd Char
Contiguous Row Table Format
In this format, the TABLE START REGISTER (RC and RD)
points to the address where the row table begins. The contents of the first 2 locations define the starting address of
the first data row. These 2 bytes define a 14 bit address where
the first byte is the low order 8 bits and the second byte is
the high order 6 bits. The 2 most significant bits of the second byte define double height/width characteristics to the
current data row. The contents of the third and fourth locations define the address where the second data row begins.
Figure 16 illustrates the contiguous row table organization
in video memory.
lsi
Dala
0
0
0
Lasl Char
Row
0
0
0
lsi Char
2nd Char
2nd
0
0
0
Dala
Row
Lasl Char
Linked List Row Table Format
0
0
In this format the TABLE START REGISTER (RC and RD)
paints to the memory location which starts the entire
addressing sequence into operation. The first byte read is
the lower 8 bits and the second byte read is the upp.er 6 bits
of the next data row's start address. The 2 most Significant
bits of the second byte define double height/width characteristics for the data row about to be read. The third, fourth,
fifth, etc., bytes read are the first, second, third, etc., char·
acters of the current data row. Figure 17 illustrates the linked
list row table organization in video memory.
Table Start Register
lsi Char
2nd Char
3rd
Dala
0
0
0
Row
Lasl CIlar
FIGURE 16:
CONTIGUOUS ROW TABLE ADDRESS FORMAT
(
I
Row table address for second data row
~
I Byte 1 I Byte 2 I Byte 3 I Byte 4 I
,
I
000
I Byte N I
'V
characters for first data row
J
Row table address for third data row
~
I Byte 1 I Byte 2 I Byte 3 I Byte 4 I 000 I Byte N I
c.~
l
V
characters for second data
J
row
FIGURE 17: LINKED LIST ROW TABLE ADDRESS FORMAT
Sequential Addressing
In this addressing mode, characters on the display screen
are located in successive memory locations. The TABLE
START REGISTER (RC and RD) paints to the address of
the first character of the first data rowan the screen. In this
mode the TABLE START REGISTER does not point to the
start of a table but the start of the screen. As each character
10
is read by the CRT 9007 for display refresh, the intemal video
address register is incremented by one to access the next
character.
For more versatile systems operation in the sequential
addressing mode, SEQUENTIAL BREAK REGISTER 1
(R10) and SEQUENTIAL BREAK REGISTER 2 (R12) may
be used to define the data rows at which two additional
()
sequential display areas begin. Note that DATA ROW END
REGISTER (R12) is defined as SEQUENTIAL BREAK
REGISTER 2 (R12) for the sequential addressing mode only.
The starting addresses for these two additional display areas
are defined by AUXILIARY ADDRESS REGISTER 1 (RE
and RF) and AUXILIARY ADDRESS REGISTER 2 (R13 and
R14). When the raster begins painting a data row equal to
the number programmed in one of the sequential break
registers, the CRT 9007 addresses the video memory
sequentially starting with the address specified by the corresponding auxiliary address register. Figure 18 illustrates
a display with 80 characters per data row having sequential
breaks at data rows 3 and 6.
Usin9. the sequential addressing mode with 2 breaks, it is
possible to rolla portion of the screen and keep the rest of
the screen stable. Double height/width characteristics can
be attached to the 2 sequentiallv addressed screens defined
by SEQUENTIAL BREAK REGISTERS 1 and 2 by using the
2 most significant bits of AUXILIARY ADDRESS REGISTERS 1 and 2. See the description of these 2 registers for
their bit definition.
Double HelghtIWidth Operation
When double height/width characters (2XH/2XW) are displayed, the following will occur:
1. the CRT 9007 will address half as many characters for
each data row by incrementing its address every other
character clock.
2. the high speed video shift register supplying serial video
to the CRT must shift out dots at half frequency.
3. For double height, the scan line counter outputs (SL3SLO or SLG, SLD) are incremented every other scan
line.
The CRT 9007 is informed of the double height or double
width display modes via the 2 most significant bits of the
row table address or the 2 most significant bits of the AUXILIARY ADDRESS registers depending on the selected
addressing mode. In any case, once the information is
obtained by the CRT 9007, it must initiate the 3 tasks listed
above. Tasks 1 and 3 are performed as appropriate and task
2 is performed using the CURS output of the CRT 9007 during CBLANK (horizontal retrace) to signal the external logiC
that a change in the dot shift frequency is required. Tile exact
time of activation and deactivation of the CURS signal during horizontal retrace is a function of addressing mode,
operation mode and actual scan line number to be painted.
Tables 1 and 2 show the cursor activation and deactivation
times as a function of the buffer configuration and addressing mode for the top scan line of a new data row. Tables 1
and 2 assume a cursor skew of zero. A cursor skew will effect
the cursor position during trace as well as retrace time. For
all subsequent scan lines, the CURS Signal is activated 3
CCLK's after VLT trailing edge and stays active for exactly
1 CCLK assuming no cursor skew. When the cursor is placed
on a double height or double width data row, it will become
active for 2 CCLK's to allow the cursor to be displayed as
double width. If the cursor position is programmed to reside
OPERATION
MODE
Repetitive Memory
Addressing
I
Single row buffer
Double row buffer
ADDRESSING MODE
Row Driven (linked list
or contiguous)
Sequential
1 CCLK after high byte 1 CCLK afler TSC
of row table read
leading edge
1 CCLK after high byte 1 CCLK after TSC
of row table read
leading edge"
1 CCLK after high byte 1 CCLK after ACK
leading edge
of row table read
Table 1: Double HelghtIWldth CURS activation for top scan
line of new data row.
TABLE START REGISTER = 1000
AUXILIARY ADDRESS REGISTER 1 = 2000
AUXILIARY ADDRESS REGISTER 2 = 0800
SEQUENTIAL BREAK REGISTER 1 = 3
SEQUENTIAL BREAK REGISTER 2 = 6
o.t.Row
o
1
2
3
4
5
6
7
8
Address range
1000 to 104F
1050 to t09F
10A0 to fOEF
2000 to 204F (Break 1)
205Oto209F
2OA0to20EF
0800 to 084F (Break 2)
085Oto089F
08A0to08EF
o
o
o
Figure 18: Sequential Addressing Example
With Two Breaks
in the top half of a double height data row, it may become
active for all scan lines in both the current and next data row
to allow the cursor to be displayed as double height.
For row driven addressing, a particular data row or pair of
data rows can appear in one of the following ways as a
function of the two most significant bits of the row table
address (bits 15 and 14).
-Single height, single width (Row table address bits 15,
14 = 00). The CRT 9007 will display the particular data
row as single height, single width.
-Single height, double width (Row table address bits 15,
14 = 01). The CRT 9007 will display the particular data
row as single height double width by accessing half as
many characters as appear in a single width data row.
The CURS signal becomes active during horizontal
retrace in the manner described previously.
-Double height, double width top half (Row table address
bits 15, 14 = 10). In addition to providing the special tim-.
ing associated with single height double width data rows,
the scan line counter is started from zero and incremented every other scan line until N scan lines are painted
(N is the number of scan lines per single height data row).
. In this way, new dot information appears every other scan
line and the top half of the data row appears in N scan
lines.
-Double Height, Double Width Bottom Half (Row table
address bits 15, 14 = 11)-Same as Double Height,
Double Width Top except the scan line counter is started
from N/2 (or (N-1 )/2 if N is odd), and incremented every
other scan line until N scan lines are painted. In single
row buffer operation, a double height bottom data row
can never stand alone and is assumed to follow a double
height top data row.
OPERATION
MODE
Repetitive Memory
Addressing
Single row buffer
Double row buffer
ADDRESSING MODE
Row driven (linked list
Sequential
or contiguous)
at the leading edge of at the leading edge of
VLT
VLT
at the leading edge of at the leading edge of
VLT
VLT
1 CCLK after leading
1 CCLK after leading
edge of CURS
edge of CURS
Table 2: Double HelghtIWldth CURS deactivation for top scan
line of new data row.
11
PROCESSOR ADDRESSABLE REGISTERS
All CRT 9007 registers are selected by specifying the
address on VAS-Q and asserting CS. All 14 bit registers are
written or read as two oonsecutive 8 bit registers addressed
low byte first. Only the VERTICAL CURSOR REGISTER
and the HORIZONTAL CURSOR REGISTER are readlwrite
registers with 2 different addresses for read or write operations. The register address assigned to each register represents the actual address in hexadecimal form that must
appear on VAS-O. Figure 2 illustrates all processor to CRT
9007 register timing. Tables 3a, 3b, and 3c summarize all
register bits and provide register addresses.
HORIZONTAL TIMING REGISTERS
The following 4 registers define the horizontal timing
parameters. Figure 19 relates the horizontal timing to these
registers.
acter times, represents the number of displayable characters during the horizontal trace interval. The difference RO
minus R1 represents the number of character times reserved
for horizontal retrace. This register Is programmed with the
binary number (N-1) where N Is the displayable characters
.
per data row.
HORIZONTAL DELAY (R2)
This a bit write only register, programmed in units of character times, represents the time between the leadinQ edge
of horizontal sync and leading edge of VLT. This register is
programmed with N where N represents the time of horizontal delay. By programming this time greater than the
horizontal blank interval, one can obtain negative front porch
(horizontal sync begins before the horizontal blank interval).
CHARACTERS PER HORIZONTAL PERIOD (RO)
HORIZONTAL SYNC WIDTH (R3)
This a bit write only register, programmed in units of character times, represents the total number of characters in
the horizontal period (trace plus retrace time). This register
is programmed with the binary number N where N is the
total characters in the horizontal period. The horizontal period
should not be programmed for less than 12 characters.
This a. bit write only register defines the horizontal sync width
in units of character time.s. The start of the sync pulse is
defined by the HORIZONTAL DELAY REGISTER and the
end is independent of the start of the active display time.
This register is programmed with N where N is the horizontal sync width. However this register must be programmed
less than or equal to [(A/2)-1] where A is the programmed
contents of REGISTER 0 rounded to the smallest even
integer.
CHARACTERS PER DATA ROW (R1)
This a bit write only register, programmed in units of char-
(
VERTICAL TIMING REGISTERS
The following 5 registers define the vertical timing parameters. Figure 20 relates the vertical timing to these registers.
displayed on the screen. This register is' programmed with
(N-1) where N is the number of data rows displayed.
VERTICAL SYNC WIDTH (R4)
SCAN LINES PER DATA ROW (RS)
This a bit write only register defines the vertical sync width
in units of horizontal periods. The start of this signal is defined
by the delay register (R5) and the end is independent of
the start of the active display time. This register is programmed with N where N is the vertical SYNC width.
The 5 LSBs of this write only register define the number of
scan lines per data row. These 5 bits are programmed with
(N-1) where N is the number of scan lines per data row. When
programming for scan lines per data ro~(~eater than 16,
only the serial scan line pin option (SLD,
) can be used.
VERTICAL DELAY (RS)
SCAN LINES PER VERTICAL PERIOD (RS; R9)
This a bit write only register, programmed in units of horizontal periods. represents the time between the leading edge
of vertical sync and the leading edge of the first VLT after
the vertical retrace interval. This register is programmed with
(N-1) where N represents the time of the vertical delay.
Registers R9 and the 3 most significant bits of Ra define
the number of scan lines for the entire frame. Ra contains
the 3 most siQnificant bits of the 11 bit programmed value
and R9 contains the a least significant bits of the 11 bit programmed value. The 11 bits are programmed with N where
N is the number of scan lines per frame. In the 2 interlace
modes, the programmed value represents the number of
scan lines per field.
VISIBLE DATA ROWS PER FRAME (R7)
This a bit write only register defines the num~r of data rows
ONE SC~N LINE
"""-
--
VLT
HOR.SYNC
I·
"1 . (RO-R1)-+
R1
RO
ACTIVE DISPLAY TIME
J
FIGURE 19: CRT 9007 HORIZONTAL TIMING
12
I
I
~2....
I
FR3~
(
......---ONE COMPLETE FRAME--~....
.......- - - R7 x R8---...~--t1
....
--~---------R9--~~------~~
VERT. BLANKING
(NO SKEW)
DATA ROW DISPLAY TIME
II
~R5"'"
I
I
'--_____--'F -==L
R4
VERT. SYNC
FIGURE 20: CRT 9007 VERTICAL TIMING
PIN CONFIGURATION/SKEW BITS REGISTER (RS)
This 8 bit write only register is used to select certain pin
configurations and to skew (delay) the cursor and the blank
signals independently with respect to the video signal sent
to the monitor. The bits take on the following definition:
Bit 7, 6 (Pin Configuration)
These 2 bits, as illustrated in tables 4 and 5, define all pinout
configurations as a function of double row buffer mode and
non double row buffer mode. (The buffer mode is defined
in the CONTROL REGISTER bits 3,2, and 1.) The attribute
assemble mode is assumed to be a double row buffer mode
and obeys table 4.
Bits 5, 4, 3 (Cursor skew)
These three bits define the number of character clocks the
cursor signal is skewed (delayed) from the VLT signal. The
CRT 9007 PIN NUMBER
REGISTER RS BITS
7
6
28
0
1
1
1
DMAR
DMAR
0
0
1
0
29
30
31
32
VLT signal is active for all characters within a data row and
a non skewed cursor will always become active within the
active VLT time at the designated position. The cursor can
be skewed from ato 5 character clocks (Bits 5, 4 and 3 programme(j from 000 to 101, bit 5 is the most significant bit;
bit 3 is the least significant bit). For double heighVwidth data
rows, the cursor signal appearing during horizontal retrace
is also skewed as programmed.
Bits 2, 1, (Blank skew)
a
These three bits define the number of character clocks the
horizontal blank component of the CBLANK signal is skewed
(delayed) from the VLTsignal. The edges of VLTwili line up
exactly with the edges of the horizontal component of the
CBLANK signal if no skew is programmed. The CBLANK
can be skewed from to 5 character clocks (Bits 2, 1 and
programmed from 000 to 101, bit 2 is the most significant
bit; bit a is the least significant bit).
a
a
CRT 9007 PIN NUMBER
REGISTER 6 BITS
33
WBEN SLG SLD CSYNC ACK
WBEN SLG SLD LPSTB ACK
NOT PERMITTED
NOT PERMITTED
29
30
31
32
33
7
6
0
1
1
0
0
1
SL 1 SLO CSYNC TSC
SL3
SL2
SL 1 SLO LPSTB TSC
SL3
SL2
VBLANK CSYNC SCG SLD LPSTB TSC
0
1
NOT PERMITTED
28
Table 4: Pin configuration for double row buffer and attribute
assemble modes.
Table 5: Pin configuration for Single Row Buffer and Repetitive
Memory Addressing Modes.
DMA CONTROL REGISTER (RA)
These 4 bits define the number of DMA operations in one
DMAR-ACK sequence. Bit 3 is the 11l0st and bit ais the least
significant bit respectively. When programmed with a number N, the CRT 9007 will produce 4 (N + 1) DMA cycles before
relinquishing the bus. When programmed with 0000, the
minimum DMA Burst will occur (4 x 1 =4) and when programmed with 1111 the maximum DMA Burst will occur
(4 x 16 = 64). When bits 6, 5, and 4 are programmed with
111, no DMA delay will occur and the Burst count will equal
the number of programmed characters per data row as
specified in R1. Refer to figures 9 and 15 which illustrate a
DMA burst of 16 and a DMA delay of 8 for double row buffer
and attribute assemble modes respectively. For single row
buffer operation, no DMA delay is permitted and bits 6, 5,4
must be programmed with 000.
This 8 bit write only register allows the user to set up a DMA
burst count and delay as well as disable the DMA mechanism of the CRT 9007. The register bits have the following
definition:
Bit 7 (DMA Disable)
A logic one will immediately force the CRT 9007 DMA request
to the inactive level and the CRT 9007 address bus (VA13VAO) wi" enter its high impedance state. After enabling the
DMA mechanism by setting this bit to a logic zero, a start
command must be issued (see START COMMAND, R15).
Bits 6, 5, 4 (OMA Burst Delay)
These 3 bits define the number of clock delays (CCLK)
between successive DMAR-ACK sequences. Bit 6 is the
most and bit 4 is the least significant bit respectively. When
programmed with a number N, the CRT 9007 wi" delay for
4 (N + 1) clock cycles before initiating another DMA request.
If 111 is programmed, however, this will result in a zero delay
allowing a" characters to be retrieved from video RAM in
one DMA burst regardless of the value programmed for the
DMA burst count.
Bits 3, 2, 1,0 (DMA Burst Count)
CONTROL R~GISTER (RB)
This 7 bit write only register controls certain frame operations as we" as specifying the operation mode used. Internal to the CRT 9007, this register is double buffered. Changes
in the r~ister are reflected into the CRT 9007 at a particular
time dunng vertical retrace. This allows the user to update
the CONTROL REGISTER at any time without running the
risk of destroying the frame or field currently being painted.
13
The bits take on the following definition:
Bit 6 (PS/SS)
= 0; The smooth scroll mechanism is enabled permitting the SMOOTH SCROLL OFFSET REGISTER (R17) to be loaded in the scan line counter (SL3o or SLG, SLD signals) allowing for a scroll on the
screen of a predetermined number of scan lines per
frame or field. The starting and ending of the smooth
scroll operation is define9 by the DATA ROW START
REGISTER (R11) and DATA ROW END REGISTER (R12) respectively.
= 1; The page blank mechanism is enabled. The
CBLANK signal is made active high for a continuous period of time starting and ending at the data
row defined by the DATA ROW START REGISTER
(R11.) and DATA ROW END REGISTER (R12)
respectively.
Sits 5, 4 (Interlace)-these 2 bits define one of 3 displayed
modes as illustrated in figure 21
= 00; Non interlaced display
= 10; Enhanced video interlace. This display mode will
produce an interlaced frame with the same dot
information painted in adjacent odd/even scan lines.
== 11; Normal video interlace. This display mode will
produce an interlaced frame with odd scan lines of
characters displayed in odd fields and even scan
lines displayed in even fields. This mode can be used
to allow the screen to show twice as many data rows
at half the height since it effectively doubles the
character density on the screen.
= 01; This combination is not permitted. ,
Bits 3, 2,1 (Operation modes): These 3 bits define the various buffer configuration modes as follows:
= 000; (Repetitive memory addressing)-In this mode
the address information (VA13-VAO) appears during every visible scan line and the address bus enters
its high impedance state during all retrace intervals.
When using a row driven addressing mode (linked
list or contiguous), the address bus is in the high
impedance state for all retrace intervals except the
horizontal retrace interval prior to the top scan line
of a new data row. This period can be disting!,!ished
from other retrace intervals because the DRB (data
row boundary) Signal is active.
= 001; (Double row buffer)-In this mode, the CRT
9007 will address a particular data row from video
memory one data row prior to the time when it is
ctisplayed on the CRT. During vertical retrace, the
first data row is retrieved and loaded into the double
row buffer. At the next data row boundary (in this
case atthe end of vertical retrace), the first data row
feeds the character generator while the second data
CHARACTER
SCAN LINE
CHARACTER
SCAN LINE
0
0
1
2
00000
0
1
3
-e
3
4
-e
6
0
0
0
1~-1
-
-
~~
(8) NON-INTERLl.CE
~-------·2
4
_ _____ 3
-
-------- 5
-------- 7
6
----------- 1
1-----;---- 5 4 - - - - - - - - - . 3
1---------6
------ 7
6
---------- 5
---------- 7
Odd Even
Odd
Even
Field Field
Field
Field
(b) ENHANCED
(e) NORMAL VIDEO
INTERLl.CE
VIDEO INTERLl.CE
FIGURE21: CRT 9007 INTERLACE MODES
14
(
-f-:-:-<>- 1
I-;::;--~-;..--- 3 0 -
?j ?j.~-- 4
5
()
CHARACTER
SCAN LINE
--7--",,-,,-0 2_
4-
0000
5
7
2
row is retrieved from video memory. The address
bus will enter its high impedance state in accordance with the DMA mechanism for address bus
arbitration.
=: 100; (Single row buffer)-In this mode, during the
first scan line of each data row, ·the CRT 9007 will
address video memory, load the buffer and feed the
character generator at the painting rate of the CRT.
If the CRT 9007 is used in a row driven addressing
mode, it will drive the address.bus during the retrace
period prior to the first scan line of each data row in
order to retrieve the row table address. It will automatically enter the high impedance state at the end
of the first visible scan line of each data row. If the
CRT 9007 is used in a sequential addressing mode,
it will drive the address bus only during the visible
line time of the first scan line of each data row.
= 111; (Attribute assemble)-In the attribute assemble mode, character data and attribute data are
shared in consecutive alternating byte locations in
memory. When the CRT 9007 reads an attribute byte,
it loads it into its internal attribute latch. During the
next memory access, a character byte is fetched.
At this time the CRT 9007 isolates its bus from the
main system bus and outputs the previously latched
attribute. A WeEN signal is produced during every
character byte fetch to allow the character and its
associated attribute to be simultaneously latched into
two double row buffers. This mode assumes that
there exists twice as many byte locations as there
are displayable character positions on the CRT. The
first byte of every data row is assumed to be an
attribute.
All other combinations of the CONTROL REGISTER bits 3, 2, 1 are not permitted.
Bit 0 (2XC/1 XC): This bit allows for either single or double
height cursor display when the cursor is placed within a
double height data row as follows:
= 1; (Single height cursor)-The CURS signal will
appear during every scan line for single height data
rows and will appear only during the top half or bottom half of a double height data row depending upon
where the VERTICAL CURSOR REGISTER (R18,
R38) defines the CURSOR data row.
= 0; (Double height cursor)-If the VERTICAL CURSOR REGISTER (R18, R38) places the cursor in
the top half of a double height data row, the CURS
Signal will appear during ~very scan. line of the top
half (the current data row) and the bottom half (the
next data row) of the double height data row. If the
cursor is placed in the bottom half of a double height
data row or if it is placed in a single height data row,
the CURS signal will only appear during the one
particular data row.
(
TABLE START REGISTER (Re AND RD)
This 16 bit write only register contains a 14 bit address which
is used in a variety of ways depending on the addressing
mode chosen; the 2 remaining bits define the addressin~
mode. Register C contains the lower 8 bits of the 14 bit
address. The 6 least significant bits of register D contain
the upper 6 bits of the 14 bit address. The 2 most significant
bits of register D define four addressing modes as follows:
Register D bits 7, 6:
= 00; (Sequential addressing mode)-The CRT 9007
will address video memory in a sequential fashion
starting with the 14 bit address contained in REGISTER D bits 5-0 and REGISTER C bits 7-0. One
break is allowed in the sequential addressing scheme
as defined by SEQUENTIAL BREAK REGISTER 1
(R10) and AUXILIARY ADDRESS REGISTER 1 (RE
and RF).
= 01; (Sequential roll addressing mode)-The CRT
9007 will address video memory in a sequential
fashion starting with the 14 bit address contained in
REGISTER D bits 5-0 and REGISTER C bits 7-0.
SEQUENTIAL BREAK REGISTER 1 and AUXILIARY ADDRESS REGISTER 1 can be used to cause
one sequential break as described in the sequential
addressing mode. A second break in the sequential
addressing can be defined by SEQUENTIAL BREAK
REGISTER 2 (R12) and AUXILIARY ADDRESS
REGISTER 2 (R13 and R14) permitting upto 3 separate sequentially addressed screens to be painted.
= 10; (Contiguous row table mode)-The CRT 9007
will address video memory according to the contiguous row table format. The 14 address bits contained in REGISTER D bits 5-0 and REGISTER C
bits 7-0 define an address that paints to the beginning of the contiguous row table.
= 11; (Linked list row table mode)-The CRT 9007 will
address video memory according to the linked list
row table format. The 14 address bits contained in
REGISTER D bits 5-0 and REGISTER C bits 7-0
define the address at which the second row table
entry and the first data row reside.
SEQUENTIAL BREAK REGISTER 1 (R10)
This 8 bit write only register defines the data row number in
which a new sequential video address begins as specified
by AUXILIARY ADDRESS REGISTER 1 (RE and RF). To
disable the use of this break, the register should be loaded
with a data row count greater than the number of displayable data rows on the screen.
DATA ROW START REGISTER (R11)
This 8 bit write only register defines the first data row number at which a page blank or smooth scroll operation will
begin. Bit 6 of the CONTROL REGISTER determines if a
page blank or smooth scroll operation will occur.
~ATA ROW END/SEQUENTIAL BREAK
REGISTER 2 (R12)
This 8 bit write only register has a dual function depending
on the addressing mode used. For row driven addressing
(contiguous or linked list as specified by the 2 most significant bits of the TABLE START REGISTER) this register
AUXILIARY ADDRESS REGISTER 1 (RE and RF)
This 16 bit write only register contains a 14 bit address. The
6 least significant bits of REGISTER F contain the upper
order 6 bits ofthe 14 bit address and REGISTER E contains
the 8 lower order bits of the 14 bit address. When the current data row equals the value programmed in SEQUENTIAL BREAK REGISTER 1 (R1 0) the remainder of the screen
is addressed sequentially starting at the 14 bit address
specified in this register. This sequential break overrides
any row driven addressing mode useH prior to the sequential break.
The 2 most significant bits of REGISTER F allow one to
attach double height and/or double width characteristics to
every data row in this sequentially addressed area in the
following way:
For Double row buffer or attribute assemble mode REGISTER F Bits 7, 6
= 00; single height single width
= 01; single height double width
= 10; even data rows are double height double width
top half odd data rows are double height double
width bottom half
= 11; odd data rows are double height double width
top half even data rows are double height double width bottom half
For Single row buffer or repetitive memory addressing mode
REGISTER F Bits 7, 6
= 00; single height single width
= 01; single height double width
= 10; odd data rows are double height double width
top half even data rows are double height double width bottom half
= 11; even data rows are double height double width
top half
odd data rows are double height double width
bottom half
defines the data row number which ends either a page blank
or smooth scroll operation. The row numerically one less
than the row defined by this register is the last data rowan
which the page blank or smooth scroll will occur. To use the
page blank feature to blank a portion of the screen that
includes the last displayed data row, this register must be
programmed to zero. For sequential addressing, this regIster can cause a break in the sequential addressing at the
data row number specified and a new sequential addressing sequence begins at the address contained in AUXILIARY ADDRESS REGISTER 2.
AUXILIARY ADDRESS REGISTER2(R13and R14)
This 16 bit write Qnly register contains a 14 bit address. The
6 least si~nificant bits of REGISTER 14 contain the upper
order 6 bits of the 14 bit address and REGISTER 13 contains the 8 lower order bits of the 14 bit address. In the row
driven addressing mode, this register is automatically loaded
by the CRT 9007 with the current table address. The two
most significant bits of REGISTER 14 specify one of four
combinations of row attributes {for example double height
15
double width) on a row by row basis. Refer to the section
entitled Double Height/Double Width operation for the
meanirlQ of these 2 bits. In the sequential addressing mode,
this register can be loaded by the processor with a 14 bit
address and a 2 bit row attributes field. The bit positions are
identical for the row driven addressing mode. When the
current data row equals the value programmed in DATA ROW
END/SEQUENTIAL BREAK REGISTER 2 (R12), the
remainder of the screen is addressed sequentially starting
at the location specified by the programmed 14 bit address.
The 2 most significant bits of register 14 allow one to attach
double height and or double width characteristics to every
data row in this sequentially addressed area. The bit definitions take on the same meaning as the 2 most significant
bits of AUXILIARY ADDRESS REGISTER 1 and affect the
display in an identical manner.
START COMMAND (R15)
After all vital screen parameters are loaded, a START command can be initiated by addressing this dummy register
location within the CRT 9007. A START command must be
issued after the DMA mechanism is enabled (DMA CONTROL REGISTER bit 7).
RESET COMMAND (R16)
The CRT 9007 can be reset via software by addressing this
dummy location. Activation of the RST input pin or initiating
this software command will effect the CRT 9007 in an identical manner. The reset state of the CRT 9007 is defined as
follows:
Reset state
CRT 9007 outputs
High impedance
VA13-0
High impedance
VD7-0
High
HS
High
VS
High
CBLANK
Low
CUS
Low
VLT
High
ORB
Low
INT
Low
Pin 28
Low
Pin 29
Low
Pin 30
Low
Pin 31
Low
Pin 32
SMOOTH SCROLL OFFSET REGISTER (R17)
This register is loaded with the scan line offset number to
allow a smooth scroll operation to occur. The offset register
causes the scan line counter output of the CRT 9007 to start
at the programmed value rather than zero for the data row
that starts the smooth scroll interval. The start is specified
In the DATA ROW START REGISTER (R11). Typically, this
register is updated every frame and it ranges from zero (no
offset) to a maximum of the programmed scan lines per data
row (maximum offset). For example, if 12 scan lines per data
row are programmed (scan line 0 to scan line 11) an offset
of zero will cause an unscrolled display. An offset of one will
cause a display starting at scan line 1 and ending at scan
line 11 (eleven scan lines total). An offset of eleven will cause
a display starting at scan line eleven.
The next scan line will be zero, starting the subsequent data
row. To allow smooth scroll of double height rows, the programmed range of the register is from zero to twice the programmed scan lines per data row. Whenever the offset
register if greater than the programmed scan lines per data
row, bit 7 of the register must be set to a logic 1 (offset overflow). It must be set to a logic zero at all other times. The 6
bit offset value occupies bits 6 through 1. Bit 0 must always
be pr~rammed with a logic zero. By setting the offset overflow (bit 7) to a logic 1, it is· possible to have the bottom half
16
of a double height data row stand alone in Single Row Buffer
Mode by programming the scrolled data row as double height
top half and loading R17 with the proper value.
VERTICAL CURSOR REGISTER (R18 or R38)
This 8 bii'readtwrite register specifies the data row in whiCh
the cursor appears. To write into this register it is addressed
as R18 and to read from this register it is addressed as R38.
(
HORIZONTAL CURSOR REGIS.TER (R19 or R39)
This 8 bit read/write register specifies the character position in which the cursor appears. To write Into this register
it is addressed as R19 and to read from this register it is
addressed as R39.
It should be noted that the vertical and horizontal cursor is
programmed in an X-Y format with respect to the screen
and not dependant upon a particular location in video
memory. The cursor will remain stationary during all·scroll
operations.
INTERRUPT ENABLE REGISTER (R1A)
This 3 bit write only register allows each of the three CRT
9007 interrupt conditions to be individually enabled or disabled according to the following definition:
Bit 6 (Vertical retrace interrupt)-This bit, when set to a logic
one, will cause the CRT 9007 to activate the INT Signal when
a vertical retrace (I.e., the start of the vertical blanking interval)
begins.
Bit 5 (Light pen interrupt)-This bit, when set to a logic one,
will cause the CRT 9007 to activate the INT signal when the
LIGHT PEN REGISTER (R3B, R3C) captures an X-Y coordinate. This interrupt, which occurs at the beginning of vertical
retrace, reflects the occurrence of a LPSTB input on the
frame or field just painted. This interrupt need not be enabled when other CRT 9007 interrupt conditions are enabled
since the STATUS REGISTER (R3A) will flag the occurance of a light pen update and servicing can be done off of
other interrupts,
Bit 0 (Frame timer)-This bit, when set to a logic one, allows
the CRT 9007 to activate the INT Signal once every frame
or field at a time when a potential smooth scroll update may
occur. In this way the user can use the frame timer interrupt
as both a real time clock and can service smooth scroll
updates and other frame oriented operations by using the
appropriate status bits. This interrupt will occur after the last
row table entry is read by the CRT 9007. In single row buffer
operation, this will occur one data row before the start of
vertical retrace. In double row buffqr operation, this will occur
two data rows before the start of vertical retrace.
STATUS REGISTER (R3A)
This 5 bit. register flags the various conditions that can
potentially cause an interrupt regardless of Whether the
corresponding condition is enabled for interrupt. In this way
some or all of the conditions can be reported to the processor via the STATUS REGISTER. If some of the conditions
are enabled for interrupt, the processor, in response to an
interrupt, simply has to read the STATUS REGISTER to
determine the cause of the interrupt. The bit definition of the
STATUS REGISTER is as follows:
Bit 7 (Interrupt Pending)-This bit will set when any other
status bit, having its correspondinQ interrupt enabled,
. experiences a.O to 1 transition. In thiS manner, when the
processor services a potential CRT 9007 interrupt, it only
has to test the interrupt pending bit to determine if the CRT
9007 caused the interrupt. If it did, the individual bits can
then be tested to determine the details of the CRT 9007
interrupt. Any noninterruptable status change (corresponding interrupt enable bit reset to a logic 0) will not be
reflected in the interrupt pending bit and must be polled by
(
the processor in order to provide service. The interrupt
pending bit is reset when the status register is read. All other
bits except Light Pen Update are reset to a logic 0 at the
end of the vertical retrace interval. The light pen update bit
is reset to a logic 0 when the HORIZONTAL LIGHT PEN.
REGISTER is read.
Bit 6 (Vertical Retrace)-A logic 1 indicates that a vertical
retrace interval has begun.
Bit 5 (Light Pen Update)--:-A logic 1 indicates that a new
coordinate has been strobed into the LIGHT PEN REGISTER. It is reset to a logic zero when the HORIZONTAL LIGHT
PEN REGISTER is read. The light pen coordinates may have
to be modified via software depending on light pen characteristics.
Bit 2 (oddleven)-For a normal video interlaced display, this
bit is a logic 1 when the field about be painted is an odd field
and is a logic zero when the field about be painted is an
even field.
FIELD
ONE
INTERLACED
Bit 0 (Frame timer occurred)-This bit becomes a logic 1
either one or two data rows before the start of vertical retrace.
Since this bit is set when the CRT has finished reading the
row table for the frame or field just painted, it permits row
table manipulation to s~art at the earliest possible ~ime~ . .
VERTICAL LIGHT PEN REGISTER (R3B)
This 8 bit read only register contains the vertical coordinate
captured at the time the CRT 9007 received a light pen strobe
signal (lPSTB).
HORIZONTAL LIGHT PEN REGISTER (R3e)
This 8 bit read only register contains the horizontal coordinate captured at the time the CRT 9007 received a light pen
strobe signal. When a coordinate is captured, the appropriate status bit is set and further transitions on lPSTB are
ignored until this register is read. The reading of this register will reset the light pen status bit in the STATUS REGISTER. The captured coordinate may have to be modified
in software to allow for light pen response.
I
HS
CSYNC
VS------------------------~
r-
FIELD
INTEW&ED
I
HS
-CS-YN-C
~
,~ !~~
3 SCAN LINES BEFORE VS""'- PROG. VSYNC WIDTH ~ 3 SCAN LINES AFTER VS ~
__~--____--__---------I------------~--------~---------
___________________________r_------------~
______________________
FIGURE 3: TYPICAL SYNC WAVEFORMS FOR INTERLACED AND NON-INTERLACED MODES
CCLK
CCLK
VlTl
,
I
I
I
I
I
VLT
I
I
SLG
I
I
I
I.e
SLD
5 CLOCKS
I~
.'
5 CLOCKS
I
I
I
I
I~I~I~I~I~I.
FIGURE 4: SERIAL SCAN LINE TIMING: NON INTERLACE
OR SINGLE WIDTH CHARACTERS
.,
I
SLG
...
SLD
[
5 CLOCKS
I
6 CLOCKS
.'Ixl~I~I~I~I~1
I
I
I
I
I
•
FIGURE 5: SERIAL SCAN LINE TIMING: INTERLACE,
DOUBLE HEIGHT OR DOUBLE WIDTH
CHARACTERS
17
MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range ..........•...•.•....••...••.....•..•....•.............. , .. ~ ....•...... 0° to + 70°C
Storage Temperature Range. . . . . • . . . . . . . . . . • . . . . • . • . . • . . . . . . • • • . . • . . . . . . . . . . . . . . . . • . . . . . . . . . .. - 55°C to + 150°C
Lead Temperature (soldering, 10 sec.) •..•.•....•.••.•.•.•....•.•••....•.....•..•......•.•.•...••........ , + 325°C
Positive Voltage on any Pin, with respect to ground ................. ; ......................................... + 15V
Negative Voltage on any Pin, with respect to ground. : -.. ::-:•• ; ':-.: '; ~''': ; '..•••. :-. : ... : .• ;-; ; •... '. ; .•. '. :-.".;' ... : .. .-. - 0.3V
. ·Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the AbsOlute Maximum Ratings
not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the
AC power is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility
exists it is suggested that a clamp circuit be used.
DC ELECTRICAL CHARACTERISTICS T" =OOC to
VL
V..,
Vrtt2
Va.
VOH
t,
PARAMETER
Input voltage
Low
High
High
Output voltage
Low
High
Input leakage current
+ 700C, Vee. =5.0V:!:: 5%
MIN
TYP
MAX
UNITS
0.8
V
V
V
~excePt~
0.4
V
V
1a.=1.6mA
IOH= 4O!LA
10
50
!LA
!LA
O""VIN""VCC ; excluding CCLK
O""VIN""VCC ; for CCLK
10
25
pF
pF
all inputs except eco<
CCLKinput
100
rnA
2.0
4.3
2.4
1L2
Input capacitance
CIN ,
C1N2
COMMENTS
L input
Power supply current
Icc
AC ELECTRICAL CHARACTERISTICS- TA =O°C to + 70°C, Vee =5.0V :!:: 5%
lev
tau.
toeH
toeR
PARAMETER
Clock
clock period
clock low
clock high
clock rise time
toeF
clock fall time
TYP
MAX
UNITS
10
ns
ns
ns
ns
10
ns
tVA
125
125
150
150
100
ns
ns
ns
ns
ns
los..
los
to.
Iosv
500
185
185
185
ns
ns
ns
ns
ns
10,
MIN
250
23
203
COMMENTS
measured from 10% to 90%
points
measured from 90% to 10%
points
(
Output delay'
tar
Io:a
to.
tvos
50
'Ivao
0
tSl.G
tSlD
ns
185
185
185
ns
ns
ns
140
50
400
ns
ns
ns
ns
ns
ns
ns
ns
125
ns
41ev
ns
measured to the 2.3V or 0.5V
level on VA13-VAO
valid for loading auxiliary
address register 2 or the
attribute latch
~=5OpF
Processor Read/writ&!
100
0
155
100
O
~
~
!tow
!,.os
ttt-
10
t.m
-"
Miscellaneous timing
I.TS
iAW
.
NOTE:
1. Timing measured from the 1.5V level of the rising edge of CCLR to the 2.4V
(high) or 0.4V (low) voltage level of the output unless otherwise noted.
2. Reference points are 2.4V high and 0.4V lOW.
3. Loading on all outputs is 30 pF except where noted.
18
measured from the O.4V level
of ACK or fSC falling edr.e
measured from the 0.4V evel
falling edge to 0.4V level
rising edge
()
CCU<
VLT,WBEN
~ I ~ ~~
~!-tc...~l======~'======~r-----~====b~========~i
"I
'---
~----I
.......--~'---..Jr-----.,!!tt--.r_-_-_-_-_-.:_t.,._-_-_-___
-'.J.t04-1
---------+-------------
VA13-e
)(
--------~====~~~==~-------
________~__------------------~---------------p.~-------
~
~
CSYNC,DMAR,INT(l£ADtNGEDCIEONLYI
~------------------~----+-------------------~
..
CBLANK, CUR..;.S~_ _ _ _ _t::====i;.:====J~
~-----Ioo------J-I~-------
14-----100
V07-0
I-------Ios. - - - - - - - . . ,
________-+________________
SLG
ATTRIBUTE OR
){
1
Ivoo---------~J ATTRIBUTE
J~~~~W~T.~~~LE~~~~~A~IN-J~~~\--------J~~_~~~~~~~_ _ ___
I+-t-.:-t- '--f
)(
--------~====~==~~--
-I
..
----------+----------~-~~
,-~.----SLD
)[
-----~~==~.~~,====~------
FIGURE 22: CRT 9007 TIMING PARAMETERS: OUTPUT SIGNALS
VD7" (WRITE)
HIGH IMPEDANCE
VD7"(READ)
lr:==-.
- ...
,
--===1(
!NT (laJling edge only)
FIGURE 2: CRT 9007 PROCESSOR READ AND WRITE
TIMING PARAMETERS
FIGURE 23: CRT 9007 MISCELLANEOUS
TIMING PARAMETERS
19
ADOAE88 DECXJDE
AllgilllrTwPe
WIVT1ii
VAS
VM
VAl
VAl
VAl
V,.
0
0
0
0
0
0
_0'
m
0
0
0
0
0
1
MSB
WIVT1ii
0
0
0
0
1
0
WRITE
0
0
0
0
1
,
MSB
WIVT1ii
0
0
0
1
0
0
MSB
WIVT1ii
0
0
0
1
0
1
MSB
0
0
0
1
1
0
PIN
WIVT1ii
WIVT1ii
0
0
0
0
1
0
1
0
0
4
0
0
0
1
0
1
0
1
05'
~R
1M
I
III
D1
D2
ALPERIOO I
atAAACTERSPE
MSB'
WIVT1ii
REGISTER
BIT DEFNTION
OiARACTERS PER DATA ROW
HORIZONTAL DELAY
I
H6RIzoNT'AL SYNC WIDTH
MSB
VER'TlCAl. SYNC WIDTH
' IIERTII::Ai. DELAY
CONFlG-I
URATION
CURSOR SKEW
i.S8
MS8
,I
MSB
I
(B8)
E
(BID))
(87)
I
MSB
LS8
FlO
LS8
Rl
LS8
112
LS8
R3
LS8
FI4
LS8
lIS
BlANK SKEW
LS8
(
R6
I
VISIBLE DATA ROWS PER ~E
MSB
SCAN
(HElQ
LS8
R7
LS8
N
LS8(BO)
R8
'SCAN UNES PEA DATA ROW
SCAN LINES PER FRAME -"
'11[;
Table 3a: CRT 9007 Screen Format Registers
RegisIer Type
WRITE
WRITE
VAS
0
0
VM
VIo3
0
,
0
VAl
VA'
0
,
VM
D7
0
os
D8
~I
PIIS'
X
WRITE
0
0
WRITE
0
0
1
0
MS8
WRITE
0
0
1
1
1
1
WRITE
0
,
ATTR~sl
0
0
0
0
MSB
0
0
0
'0
0
1
MSB
~SSI
1
0
0
1
0
MSB
1
MSB
0
ATTR~J
0
LS8
RE
AUXILIARY ADDRESS REGISTER 1 (MS BYTE)
MSB
LS8
.-'
RF
R12
0
1
RD
DATA ROW ENDISEQUENTIAL BREAK REGISTER 2 LS8
WRITE
0
LS8
Rl1
MSB
0
MS8
RC
LS8
1
0
LS8
TABlE SmT REGISTER (MS BYTE)
RB
RIO
0
1
2XCIIxC
LS8
0
1
OPERATION MODES I
DATA ROW START REGISTER
0
0
INTERLACE
MODES
RA
LS8
'SEQUENTIAL BREAK REGISTE~ ,
1
0
MSB
AUXILIARY ADDRESS REGISTER 1 (LS BYTE)
0
WRITE
0'
I
DMA BURST COUNT
TABlE START REGISttR (LS BYTE)
WRITE
1
D2
DMA BURST DELAY
MS8A
LS8
DISABLE
, ,
, ,
,
1
WRITE
1M
I
DMA
, ,
0
"
REGISTER
NUMBER
(HEX)
BIT DEFINITION
ADDRESS DECODE
AUXILIARY ADDRIOSS REGISTER 2 (lS BYTE)
T
LS8
1113
AUXILIARY ADDRESS REGISTER 2 (MS BYTE)
MSB
LJ
1
LS8
R14
(
Table 3b: Control and Memory Address Registers
~Type
VAS
VM
VIo3
VAl
VAl
WRITE
0
1
1
0
,
0
,
0
READ OR
WRITE
0
1
1
0
READ OR
WRITE
VM
0
1
0
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
,
0
1
,
0
1
0
D7
1
1
1
,
,
,'I
1
1
0
0
1
1
,
0
0
os
D8
DCJ
1M
~R
D2
(HElQ
01
START COMMAND
i!1
FLOW
RESET COMMAND
I
I
I
,
QfFSETVALUE
Rte
•
LS8I
MSB
HORIZONTAL CURSOR REGISTER (coL COORD.)
MSB
NT
,
R15
veRnc:AL.CURSOR REGISTER (ROW COORD.)
MSB
0
MSB I
R1I..-RII
LS8
RII..- ...
FRAME
R3A
VERT1pAL LIGHT PEN REGI~R (ROW COORD.)
LS8
RIB
HORIZONTALLlGHTPENREGI~(CO:--~')
L88
R3C
.j,~J
MSB
LS8
lilA
"JSTA~REGISTER
I J
PEND- ' RE· LIGHT
ING TRACE PEN
1
At7
i=
VERlRRlJPTENABlE REGISTER
TICAl.
RE· LIGHT
TRACE PEN
X
X
X
X
X
,
REGISTER
BIT DEFINITION
ADDRESS DECODE
0IlDi
EVEN
X
TIMER
Table 30: Cursor, Light Pen, Offset, and Status Registers
Circuit diagrams utilizing SMC products are Included asa means ,of Illustrating typical semiconductor applications. consequently complete information sufficient for construction purposes Is not necessarily given. The
~
Information has been carefully checked and is believed to be entirely reliable. However. no responsibility II
'I J~ ....... 1Ihd " " - NY 11111 assumed for inaccuracies. Furthermore. such information does not convey to the purchaser oflhe semiconductor
I~" m 3100' TWHIO:Z27._ devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
DIJ",mmoettIillWip/Clllapft!adOfWQIIS. at any time in order to improve design and supply the best product possible.
(
CRT 9006-135
CRT 9006-83*
DARD MICROSYSTEMS
/lPC FAMILY •
35 M.¥cus Blvd . Hal(lpauge. N V 11787
1516) 273· 3100 TWX· 510·227·8898
mrn'll'tttinn SO you CiI1 keep ftaI of \QI'S.
Single Row Buffer
SRB
PIN CONFIGURATION
FEATURES:
o Low Cost Solution to CRT Memory Contention Problem
o Provides Enhanced Processor Throughput for CRT
Display Systems
o Provides 8 Bit Wide Variable Length Serial Memory
o Permits Active Video on All Scan Lines of Data Row
o Dynamically Variable Number of Characters per Data Row... 64,80, 132, ... up to a Maximum of 135
o Cascadable for Data Rows Greater than 135 Characters
o Stackable for Invisible Attributes or Character
Widths of Greater than 8 Bits
o Three-State Outputs
o 4MHz Typical Read/Write Data Rate
Static Operation
Compatible with SMC CRT 5037, CRT 9007, and other
CRT Controllers
024 Pin Dual In Line Package
0+5 Volt Only Power Supply
TTL Compatible Inputs and Outputs
o Available in 135 Byte Maximum Length (CRT 9006-135)
or 83 Byte Maximum Length (CRT 9006-83)
o
o
DOUT3
GND
DOUT2
DOUT4
DOUTl
DOUTS
DOUT"
DOUT6
ClK
DOUT7
WREN
OE
ClRCNT
OF
CKEN
DIN7
DINO
DIN6
DIN1
DINS
DIN2
DIN4
DIN3
+sv
Package: 24-pin D.J.P.
APPLICATIONS:
o CRT Data Row Buffer
o Block-Oriented Buffer
o Printer Buffer
o Synchronous Communications Buffer
o Floppy Disk Sector Buffer
o
GENERAL DESCRIPTION
The SMC Single Row Buffer (SRB) provides a low cost solution to memory contention between the system processor and
CRT controller in video display systems.
The SRB is a RAM-based buffer which is loaded with character
data from system memory during the firs! scan line of each
data row. While data is being written into the RAM it is also
being output through the multiplexer onto the Data Ouput
(DOUT) Lines. During subsequent scan lines in the data row,
the system will disable Write Enable (WREN) and cause data
to be read out from the internal RAM for CRT screen refresh,
thereby releasing the system memory for processor access
for the remaining N-1 scan lines where N is the number of
scan lines per data row. The SRB enhances processor throughput and permits a flicker-free display of data.
,!F
or
eLK
CKEN
I
ADORESS
COUNTER
I
R...
I
''''''''
I
I
-'00.
READ DATA
OCTAL
2 TO 1
..ux
I
t------i
3-STATE
L
U •
T T
P C
~
WRIT
2fj~=~==~
o
H
8
U
,
,
DOUT7-'
F
R
l
P T
N •
u C
T H
Single Row Buffer Block Diagram
'FOR FUTURE RELEASE
135
()
(,
(
CRT 9212
f..LPC FAMILY
3S MillI:US Blvd. HauiJ!WOe. N.Y. 11788
15161273·3100 • TWX·Sl0·22]·189II
t'IIIft'WfHlMSO PI cal keep Dad of,:m.
Double Row Buffer
ORB
FEATURES
PIN CONFIGURATION
o Low Cost Solution to CRT Memory
Contention Problem
o Provides Enhanced Processor Throughput for
CRT Display Systems
o Replaces Shift Registers or Several RAM and
Counter IC's in CRT Display System
o Permits Display of One Data Row While Next
Data Row is Being Loaded
o Data May be Written into Buffer at Less Than
the Video Painting Rate
o Double Data Row Buffer Permits Second Data
DIN2 1
DIN1 2
DINO 3
DOUT7 4
DOUT6 5
DOUT5 6
DOUT4 7
Vee 8
DOUT3 9
DOUT210
DOUT1 11
DOUTO 12
28DIN3
27 WCLK
26 OE
25 WEN2
24 WEN1
D
DIN713
DIN614
Row to be Loaded Anytime during the Display
of the Preceding Data Row
23 GND
22 ROF
. 21 WOF
20 REN
19 CLRCNT
18 fOG
17 RClK
16 DIN4
15 DINS
PACKAGE 28-pin D.I.P.
o Permits Active Video on All Scan Lines of
Data Row
o Three-State Outputs
o Dynamically Variable Number of Characters
per Data Row-... 64,80, 132, ... up to
a Maximum of 135
o Up to 4 MHz ReadlWrite Data Rate
o Compatible with SMC CRT 5037, CRT 9007.
and other CRT Controllers
o Cascadable for Data Rows Greater than
135 Characters
o Stackable for "Invisible Attributes"
or Character Widths of Greater than 8 Bits
o 28 Pin Dual-In-Line Package
o + 5 Volt Only Power Supply
D TTL Compatible
GENERAL DESCRIPTION
The CRT 9212 Double Row Buffer (ORB) provides
a low cost solution to memory contention between the
system processor and the CRT controller in video display systems.
The CRT 9212 ORB is a RAM-based buffer'Which
provides two rows of buffering. It appears to the system as two octal shift registers of dynamically variable length (2-135 bytes) plus steering logic.
The CRT 9212 permits the loading of one data row
while the previous data row is being displayed. The
loading of data may take place during any of the scan
line times of the data row. This relaxed time-constraint allows the processor to perform additional
processing on the data or service other high priority
interrupt conditions (such as a Floppy Disk DMA
request) which may occur during a single video scan
line. The result is enhanced processor throughput and
flicker-free display of data.
MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range ................................................................... : .... O'C to + 70°C
Storage Temperature Range ..............: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55'C to + 150°C " f
Lead Temperature (soldering, 10 sec.) ....................................................................... + 325 ( 'to .
Positive Voltage on any Pin, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. + S.OV' ....~
Negative Voltage on any Pin, with respect to ground. . . .. .. .. . .. .. . . . .. . .. .. . . . . . . .. .. . .. .. .. . .. . . .. .. . . . . . . . . .. - 0.3V t
·Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
ELECTRICAL CHARACTERISTICS (TA =DoC to 70°C, Vee = + 5V ± 5%)
DC CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low Level VH..
Level VI."
Level V
OUTPUT VOLTAGE LEVELS
Low Level VOl
Level V
INPUT LEAKAGE CURRENT
High leakage ILHl
Low Leakage ILL,
High Leakage IU<2
low
INPUT CAPACITANCE
CIN ,
0.8
v
V
2.0
4.2
V
0.4
2.4
excludiV9~; WCU<
V
V
rn:
excluding
excluding WEN1
WEN1
10
10
400
400
rn:
10
15
pF
100
mA
SUPPLY CURRENT
AC CHARACTERISTICS'
tcvw
tc""
fcKH
fcKL
250
250
200
30
DC
10
10
fcKA
fcKF
los
to...
~",2
~~
~ ~
..
50
0
0
100
0
trw
175
175
175
175
~
too.,
fop!
fcs
~
~
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write clock period
Read clock period
measured from 10% to 90% points
measured from 90% to 10% points
referenced to 'FiCtR
referenced to 'FiCtR
CL = 50 pF; referenced from WCU<
CL = 30pF
1fcvw
1 • Reference points for all AC~C[Kmeters are 2.4V high and O.4V low.
2· For REN. referenced from
; for WEN1 or WEN2 referenced to wrxR.
3· For ROF. referenced from RCU{; for WOF referenced from wrxR.
4· At least 1 WClK rising edge must occur between CLRCNT or TOO (whichever occurs last) and WEN (= WEN1-WEN2).
wcLi<'
I
RCLf<"
I
I
l,---;/~:-----------------------------~tl)----------------------------..... ,. ...
~--~I~~---~ ~:~
I
I
r--;-
,-,
____________________________ ____________ _____________
~"'
~
'C-
I
I
I
I
I
INTERNAL
RAMADDR
(WRITE)
I
7I!III!!////!;/I1!//////!!1I!!/&t~-AD-DR-O--'x ADDR
-~!I!!////I!//Il/.
1 X,--_A_DDR_2
\\.._....1r-----------.. .lllt·--------------------------
WEN
,...-----.
(=WEN1.WE_N2...;..)_ _ _ _ _~1
INTERNAL
WEN
WOF~
(.~l--""/
• in general WCLK and RCLK can be different
FIGURE 3: CRT 9212 DOUBLE ROW BUFFER WRITE TIMING
+5V
WENl
WEN2
,. RCLK
9212
"Au
" WCLK
~
..
: ..,
REN
J
..
...
v_
DIN7·0
CLRCNT
TOG
-
.....
-
I...--. WEN 1
WEN 2
.... RCLK
~ WCLK
REN
...
<
"
...
DOUT7-0
ROF
WOF
..
.......
.....
.-
DIN7-0
,
--
.......
,.
9212
"Bit
'.. '
DOUT7-0
..
::::,.
.:
I
.........
>: ',)
y
.'"
CLRCNT
TOG
FIGURE 4: CRT 9212 CASCADED CONFIGURATION
FOR DATA ROW LENGTHS UP TO 270 CHARACTERS
"7
--.
-y
fi;;:;
...
;)
", .......
..,.'
INTR
PROCESSOR
"P,,,c
ACK
DMARa
"ODR
DATA
~
"-
DMAR
MEMORV
ADM
RAM
VIDEO RAM
..
..
".
liCK
1 1 1
RIfT
+5V
GNo
-
INT
~
ADORE
VAl3-.
BUS
CRTDOO7
AS
VPAC"
""
"'.
"
CBlANK
V07-'
-
VS
WBEN
I'll!
Sl.D
VLT
srn
~.t ~3~
0
A
T
II
B
U
S
1
wtLII.
r
WEN. f'Oll tlAC...'!" RfN
CAT 9212
DOUBLE
L-J.,
01'111"
~c
ATIRIBUTES
I rlDh
'f}
. . ~~.~,~~W~,~~
1
ROW BUFFER
col
!
ACLK
ilOUT'4
ct:rR'
CURS
LD'SR
CRT8002
VOAC··
J
o
R
CLOCK
I GENERATOR
I
VOC
CHARACTERIATIRIBUTES
GENERATOR
A7·'
r
}i
VIDEO
Oll>-CIND
TO
MONITOR
FIGURE 5: CRT 9212 CONFIGURED WITH THE CRT 9007 VPAC AND THE CRT 8002 VDACTM
~----------------~~.~~l----------------~
RCLKORWCLK
DIN7-0
REN, WEN 1,2
DOUT7·0
WOF,ROF
CLRCNT OR TOG
WEN 1,2
f~
Iwr
*
FIGURE 6: CRT 92121/0 TIMING
©4/82-SM
DESCRIPTION OF PIN FUNCTIONS
SYMBOL
DINO-DIN7
PIN NO.
3-0,28,
16-13
12-9,7-4
NAME
Data inputs
Data outputs
DOUTODOUT7
17
Read Clock
RcrR
18
Toggle Signal
TOO
19
Clear Counter
CLRCNT
20
Read Enable
REN
21
Write Overflow
WOF
22
Read Overflow
ROF
24,25
Write Enable
26
Output Enable
27
Write Clock
8
23
Power Supply
Ground
WEN1,
WEN2
O"E
WC[R
Vee
GND
FUNCTION
DINO-DIN7 are the data inputs from the system memory.
DOUTO-DOUT7 are the data outputs from the CRT 9212 internal data output
latch. Valid information will appear on DOUTO-DOUT7 two RC[R periods after
the rising edge of REN. This introduces two pipeline delays when supplying data
to the character generator.
RcrR increments the current "read" address register, clocks data through the
"read" buffer and moves data through the intemal pipeline at the trailing edge.
TOG alternates the function of each buffer between read and write. TOO normally' occurs at eve data row boundary. Switching of the buffers occurs when
both TOO and CLR NT are low.
Clear COunter clears the current "read" address counter at the next 'RCO< positive edge. CLRCNT is normally asserted low at the beginning of each horizontal
retrace interval. CLRCNT clears the current "write" address counter when the
TOO is active.
REN enables the loading of data from the selected "read" buffer into the output
latch. Data is loaded when Read Clock is active.
WOF hi~h indicates that data is being written into the last memory position (position 135 . When WOF is high, further writing into the selected "write" buffer is disabled. WOF may be connected to the WEN1 or WEN2 inputs of a second CRT
9212 for cascaded operation where data row lengths of greater than 135 characters are desired. See figure 4.
The Read Overflow output is high when data is being read from the last memory
position (position 135). ROF high disables further readin~ from the selected
"read" buffer. ROF may be connected to the REN input 0 a second CRT 9212 for
cascaded operation where data row lengths of greater than 135 characters are
desired. DOUTO-7 will switch into a hi~h impedance state at the second positive
transition of R'C[K after ROF goes hici . See figure 4.
WEN allows input data to be written into the selected "write" buffer during WCCK
active. Both WEN1 and WEN 2 must be high to enable writing. WEN1 has an
internal pull up resistor allowing it to assume a high if pin 24 is left open.
When the O"E input is lov< the data outputs DOUTO-DOUT7 are enabled. When
O"E is high, DOUTO-DOUT7 present a high impedance state. DE has an internal
pulldown resistor allowing it to assume a low if pin 26 is left open.
WC[R clocks input data into the selected "write" buffer and increments the current "write" address register when WEN1 and WEN2 are high.
+ 5 Volt supplv
Ground
6
OPERATION
Figure 1 illustrates the internal architecture of the CRT
9212. It contains 135 bytes of RAM in each of its two buffers. In normal operation, data is written into the input latch
on the positive-going edge of Write Clock (WCLK). When
both Write Enable (WEN1, WEN 2) Signals go high, the next
WCLK causes data from the input latch to be written into
the selected buffer (1 or 2) and the associated address
counter to be incremented by one. Loading of the selected
RAM buffer continues until WEN goes inactive or until the
buffer has been fully loaded. At the next data row boundary,
the Toggle Signal (TOG) will.9..Q..!Q~When Clear Counter
(CLRCNT) goes low, the next Read Clock (RCLK) will begin
to reset both buffer address counters to zero, swijching the
buffer just loaded from a "write buffer" to a "read buffer",
permitting the next row of data to be written into the other
buffer. Data from the current "read" buffer is read' out of the
buffer and to the output latch whenever Read Enable (REN)
is high during a Read Clock (RCLK). Each read-out from
the buffer RAM causes the "read" address counter to be
incremented. REN is normally high during the entire visible
line time of each scan line of the data row. CLRCNT resets
the present "read" address counter. The negative edge of
CLRCNT is detected by the CRT 9212 and the internal "read"
address counter is cleared independent of the CLRCNT
pulse width. The CLRCNT input may be tied to the REN
input for proper operation.
Figures 2 and 3 illustrate the functional timing for reading
and writing the CRT 9212. It is possible to cascade two or
more CRT 9212's to allow for data storage greater than 135
bytes by employing the read overflow (ROF) and write
overflow (WaF) outputs. Figure 4 illustrates two CRT 9212's
cascaded together.
The CRT 9212 is compatible with the CRT 9007 video
processor and controller (VPACTM) and the CRT 8002 video
display attributes controller (VDAC TM). A typical video
configuration employing the three parts is illustrated in
figure 5.
...
ADDRESS
COUNTER 1
AODR7-0
RAM 1
135x8
y
~
4
.
V
...<
)
r--
DIN7-0
...
...
y
110 CONTROL
L
A
T
C
H
.....
~
r-
OCTAL
2-1
MUX
"'
./
L..-
...
1/0 CONTROL
f--J\ i~
hi t[-\l
H
'-
3 STATE
DRIVER
~
DOUT7-0
...)
l~
~
>-
TO
CLR
ADDRESS
COUNTER 2
...
ADDR7-0 )
...
RAM 2
135 x 8
OE
--K
RCL
READIWRITE
CONTROL
REN
WCLK
WEN1
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